1986_PMI_Linear_and_Conversion_Products_Data_Book 1986 PMI Linear And Conversion Products Data Book
User Manual: 1986_PMI_Linear_and_Conversion_Products_Data_Book
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Alpha- .
numerIC
Index
Part
Number
Page
ADC-910 ............. 12-7
ADC8208 ........... 1219
AMP-Ol ......... , ... , .. 6-5
AMP-OS ............. 6-27
BUF-03 ................ 7-4
CMP-OJ ................ 8-6
CMP-02., ............ 8-14
CMP-04 .............. 8-22
CMP-05 .............. 8-30
CMP-07 , ............. 8-37
CMP-404 ............ 8-40
DAC-OJ .............. 11-10
DAC-02 .............. 11-14
DAC-03 ............. 11-14
DAC-05 ........ , .... 11-14
DAC-06 .............. 11-19
DAC-08 ............. 11-23
DAC-IO ............. 11-34
DAC-20 ............. 11-42
DAC-86 ............. II-50
DAC-88 ............. 11-58
DAC-89 .............. 11-67
DAC-100 ............. 11-76
DAC-208 ........... 11-84
DAC-210 ............ 11-88
DAC-312 ............ 11-92
DAC-888 ........... 1l-104
DAC-1408 .......... 11-116
DAC-1508 .......... 11-116
DAC-80l2 .......... 11-122
DAC-8212 .......... 11-131
DAC-8408 .......... 11-136
DMX-88 ........... , .13-74
GAP-OJ .............. 15-~
JM3851O/10l04 ..... 5-273
JM3851O/10106 ..... 5-276
JM3851O/ll004 ..... 5-279
JM3851O/ll30l .... 11-209
JM3851O/ll302 .... 11-209
JM3851O/ll40l ..... 5-282
JM38510/11402 ..... 5-282
JM3851O/11403 ..... 5-282
JM3851O/11404 ..... 5-282
JM3851O/11405 ..... 5-282
JM3851O/11406 ..... 5-282
JM38510/13501 ..... 5-292
JM3851O/13502 ..... 5-292
JM38510/13503 ..... 5-295
MAT-OJ ................ 9-5
MAT-02 .............. 9-11
MAT-04 ............. 9-23
MUX-08 ............ 13-48
MUX-16 ............. 13-59
MUX-24 ............ 13-48
MUX-28 ............ 13-59
MUX-88 ............ 13-69
OP-OJ ................. 5-12
OP-02 ................ .5-18
OP-04 ................ 5-26
01'-05 ................ 5-34
01'-06 ................ 5-43
OP-07 ................ 5-51
OP-08 ................ 5-61
OP-09 ................ 5-68
01'-10 ................. 5-75
01'-11 ................ 5-68
01'-12 ................ 5-87
OP-14 ................ 5-26
OP-15 ................ 5-91
01'-16 ................ 5-91
OP-17 ................ 5-91
OP-20 ............... 5-105
01'-21 ................ 5-1ll
01'-22 ............... ,5-117
01'-27 ............... 5-128
OP-32 ............... 5-140
OP-37 ............... 5-152
01'-41 ............... 5-164
OP-43 ................ 5-175
OP-50 ............... 5-180
OP-77 ................ 5-191
01'-90 ............... 5-197
OP-207 ............. 5-199
01'-215 .............. 5-205
OP-220 ............. 5-212
01'-221 .............. 5-220
OP-227 .............. 5-228
OP-400 ............. 5-239
OP-420 ............. 5-241
OP-421 .............. 5-246
PKD-OJ .............. 15-19
PM-108 .............. 5-252
PM-Ill ............... 8-48
PM-119 ............... 8-54
PM-139 ............... 8-56
PM-146 ............ ,.5-256
PM-155 .............. 5-259
PM-156 .............. 5-259
PM-157 .............. 5-259
PM-208 ............. 5-252
PM-211 ............... 8-48
PM-219 .............. 8-54
PM-246 ............. 5-256
PM-308 ... , ......... 5-252
PM-319 .............. 8-54
PM-339 .............. 8-56
PM-355 ............. 5-259
PM-356 ............. 5-259
PM-357 ............. 5-259
PM-562 ............. 11-140
PM-565 ............ 11-148
PM-725 ............. 5-265
PM-741 .............. 5-268
PM-747 ............. 5-270
PM-2108 ............ 5-252
PM-7226 ............ 11-149
PM-7524 ............ 11-150
PM-7528 ............ 11-159
PM-7533 ............ 11-175
PM-7541 ............ 11-185
PM-7542 ............ 11-195
PM-7543 ............ 11-196
PM-7545 ............ 11-197
PM-7548 ........... 11-208
PM-7645 ............ 11-197
REF-OJ ............... 10-4
REF-02 ............... 10-11
REF-03 ............ , .. 10-19
REF-OS .............. 10-21
REF-IO .............. 10-22
RPT-82 .............. 16-4
RPT-83 .............. 16-4
SMP-IO ............... 14-6
SMP-11 ............... 14-6
SMP-81 .............. 14-15
SW-OJ ................. 13-7
SW-02 ................. 13-7
SW-05 ..... , .......... 13-14
SW-06 ............... 13-22
SW-20l ............. 13-33
SW-202 ............. 13-33
SW-751O ........ , .... 13-40
SW-7511 ............. 13-40
I,
Linear and
Conversion
Products
1986/1987
Data Book
The PMI
Commitment
PMI is committed to
building long-term
customer relationships
resulting in mutual
growth.
At PMI we dedicate
ourselves to leadership
in customer service,
quality; and technology.
Our goal is flawless
performance and
professional excellence.
Copyright@ 1986
Precision Monolithics Inc.
PMI reserves the right to make changes to the products
contained in this data book to improve performance, relIabIlity,
or manufacturability. Consequently, contact PMI for the latest
available specifications and performance data.
Although every effort has been made to ensure accuracy of the
information contained in this data book, PMI assumes no
responsibility for inadvertent errors.
PMI assumes no responsibility for the use of any circuits
described herein and makes no representation that they are free
of patent infringement.
The products in this catalog are manufactured under one or
more of the following patents: 4,055,773; 4,056,740; 4,068,254;
4,088,905; 4,092,639; 4,109,215; 4,118,699; 4,131,884; 4,138,671;
4,142,117; 4,168,528; 4,210,830; 4,228,367; 4,260,911; 4,272,656;
4,285,051; 4,333,047; 4,340,851; 4,374,335; 4,449,067; 4,471,321;
4,503,381; 4,538,115; 4,542,349.
Precision Monolithics Inc.
Life Support and Nuclear Facility Applications Policy
As a general policy, Precision Monolithics Inc. (PMI) does not
recommend the use of any of its products In (a) life support
applications where failure or malfunction of the PMI product
can be reasonably expected to cause failure of the life support
device or to significantly affect Its safety or effectiveness, or (b)
any nuclear facility applications. PMI Will not knowingly sell
its products for use in such applicatIOns unless it receives In
writing assurances satisfactory to PMI that (a) the risks of
injUry or damage have been minimized (b) the customer
assumes all such risks, and (c) the liability of PMI is adequately
protected under the circumstances.
Examples of devices considered to be life support deVices are
neonatal oxygen analyzers, nerve stimulators (whether used for
anesthesia, pain relief, or other purposes), autotransfusion
devices, blood pumps, defibrillators, arrhythmia detectors and
alarms, pacemakers, hemodialysis systems, peritoneal dialysis
systems, neonatal ventilator incubators, ventilators for both
adults and infants, anesthesia ventilators, and infuSIOn pumps,
as well as other devices designated as "cntical" by the FDA. The
above are examples only and are not intended to be conclusive
or exclusive of any other life support device.
Examples of nuclear facility applicatIOns are applications in
[a) a nuclear reactor, or [b) any device designed or used in
connection With the handling, processing, packaging,
preparation, utilizatIOn, fabricating, allOYing, storing, or
disposal of fissionable matenal or waste products thereof.
Table of Contents
1
Ordering Information 2
Product Assurance Program 3
Industry Cross Reference 4
Operational Amplifiers 5
Instrumentation Amplifiers 6
Voltage Followers/Buffers t
Voltage Comparators 8
Matched Transistors 9
Voltage References 10
Digital-to-Analog Converters 11
Analog-to-Digital Converters 12
Analog Switches/Multiplexers 13
Sample-and-Hold Amplifiers 14
Special Functions 15
Communications Products 16
Package Information 17
Sales Offices, Representatives and Distributors 18
~~--
--~-
---
~-
~
-~---~
---~---
-
---
TABLE OF
CONTENTS
PI I. t.: I .... HIII ]\101101 It
Section
h
1~'"
I Ill:
2
Ordering Information
2-2
Package Products Part
Numbering System
2-3
Dice Part
Numbering System
2-4
Dice Information
2-5
Reliability Information
2-6
Discontinued Device Types
Ordering Guide
Section
3
Section
5 continued
5-26
OP.04/OP.14
Dual Matched High-Performance
Operational Amplifiers
5-34
Instrumentation
Operational Amplifier
5-43
Introduction
3-3
Processing
Section
5-51
5-61
4
5-68
5
5-4
Definitions
5-6
Selection Guide
5-12
OP-Ol
5-87
OP-12
Precision Low-Input-Current
Operational Amplifier
5-91
OP.15/0P.16/0P.17
Precision JFET-Input
Operational Amplifiers
Inverting High-Speed
Operational Amplifier
5-18
OP·I0
Dual Matched Instrumentation
Operational Amplifier
Operational Amplifiers
Introduction
OP·09/0p·n
Quad Matched 741-1)rpe
Operational Amplifiers
Alphanumeric Direct
Replacement Guide
5-4
OP·08
Precision Low-Input-Current
Operational Amplifier
5-75
Section
OP·07
Ultra-Low Offset Voltage
Operational Amplifier
Industry Cross Reference
4-2
OP·06
High-Gain Instrumentation
Operational Amplifier
Product Assurance Program
3-3
OP·05
5-105
OP·02
OP-20
Micropower Operational Amplifier
General-Purpose
Operational Amplifier
5-111
OP·21
Low-Power Operational Amplifier
1-2
TABLE OF
CONTENTS
Pll(I<"IOlll\'lollolnhlt:"IIH:
Section
5 continued
Section
5 continued
5-117
OP·21
5-212
OP·220
Programmable Micropower
Operational Amplifier
Dual Micropower Operational Amplifier
5-220
5-128
OP·27
5-228
5-239
5-175
5-241
OP-41
5-246
OP-43
PM-I0SA/PM-20SA/PM-30SAI
PM-I0S/PM.20S/pM·30S1
5-252 PM·210SA/PM·21OS
Quad Low-Power Operational Amplifier
Low-Input-Current
Operational Amplifiers
OP-50
5-256
PM·155A/PM-355A/pM.1551
PM.156A/PM·356A/PM.1561
5-259 PM-157A/PM·357A/PM.157
OP·90
Low-Voltage Micropower
Operational Amplifier
5-199
Monolithic JFET-Input
Operational Amplifiers
OP-207
5-265
Dual Ultra-Low Vas Matched
Operational Amplifier
PM-725
Instrumentation Operational Amplifier
5-268
5-205
PM-146/PM.246
Programmable Quad
Operational Amplifiers
OP·77
Next Generation OP-07 (Ultra-Low
Offset Voltage Operational Amplifier)
5-197
OP·421
Low-Bias-Current JFET
Operational Amplifier
High-Output-Current
Operational Amplifier
5-191
OP-420
Quad Micropower Operational Amplifier
Low-Bias-Current, Fast JFET
Operational Amplifier
5-180
OP-400
Quad Low-Offset Low-Power
Operational Amplifier
OP-37
Low-Noise Precision High-Speed
Operational Amplifier
5-164
OP·227
Dual Low-Noise Low-Offset
Instrumentation Operational Amplifier
OP·32
High-Speed Programmable Micropower
Operational Amplifier
5-152
OP·221
Dual Low-Power Operational Amplifier
Low-Noise Precision
Operational Amplifier
5-140
~
0
OP·215
PM-741
Compensated Operational Amplifier
Dual Precision JFET-Input
Operational Amplifier
1·3
~--
------
~----
----
-
-
------~--
~--~--
~----~-
U
~
0
~
~
TABLE OF
CONTENTS
Plll:I..,IOIl 1\101l011thH: ...
Section
5-270
IIH:
S continued
Section
PM·747
Dual Compensated
Operational Amplifier
5-273
5-279
7-3
Introduction
7-4
BUF·03
J~851O/10104
High-Speed Voltage Follower/Buffer
JAN Single Low-Input-Current
Operational Amplifier
5-276
7
Voltage Followers/Buffers
Section
8
J~8510/10106
Voltage Comparators
JAN Dual Low-Input-Current
Operational Amplifier
8-3
Introduction
8-3
Definitions
JM3851O/11004
JAN Quad 741-1}rpe
Operational Amplifier
8-6
J~851O/11401/11402/11403/11404/
8-14
CMP·Ol
Fast Precision Comparator
5-282 11405/11406
JAN JFET-Input Operational Amplifiers
CMP·02
Low-Input-Current
Precision Comparator
5-292 JM38510/13501/13502
Ultra-Low Offset Voltage
Operational Amplifiers
8-22
CMP·04
Quad Low-Power Precision Comparator
8-30
5-295 JM38510/13503
Low-Noise Precision
Operational Amplifier
CMP·05
High-Speed Precision Comparator
8-37
CMP·07
Very High-Speed Comparator
Section'
8-40
Instrumentation Amplifiers
6-3
Introduction
6-3
Definitions
6-5
8-48
PM.111/PM.211
Precision Voltage Comparators
AMP· 01
8- 54
Low-Noise Precision
Instrumentation Amplifier
PM.119/PM.2.19/PM.319
Dual Comparators
8-56
6-27
CMP.404
Quad Low-Power Precision Comparator
AMP·05
PM.139/PM.139A/PM.339A
Quad Low-Power Voltage Comparators
Fast-Settling JFET
Instrumentation Amplifier
1-4
TABLE OF
CONTENTS
PrecIsion MOllo]ithics Inc.
C/)
Section
9
Section
11
~
Matched Transistor Arrays
Digital-to-Analog Converters
9-3
Introduction
11-4
Introduction
U
9-3
Definitions
11-4
Definitions
0
9-4
Parameter Comparison Tables
11-8
Selection Guide
9-5
MAT-Ol
Matched Monolithic Dual Transistor
11-10
DAC-Ol
6-Bit Voltage-Output D/A Converter
~
MAT-02
11-14
DAC-02/DAC-03/DAC-OS
lO-Bit-Plus-Sign Voltage-Output
D/A Converters
Z
0
9-11
Low-Noise, Matched Dual
Monolithic Transistor
9-23
MAT-04
11-19
Section
10
11-23
DAC-08
8-Bit High-Speed Multiplying
D/A Converter
11-34
DAC-lO
lO-Bit High-Speed Multiplying
D/A Converter
11-42
DAC-20
2-Digit BCD High-Speed Multiplying
D/A Converter
Voltage References
10-3
Introduction
10-3
Definitions
10-4
REF-Ol
+10V Precision Voltage Reference
10-11
REF-02
+5V Precision Voltage
Reference/Temperature Transducer
10-19
REF-03
+2.5V Precision Voltage Reference
10-21
REF-OS
+5V Precision Voltage Reference
10-22
DAC-06
Two's-Complement lO-Bit
Voltage-Output D/A Converter
Matched Monolithic Quad Transistor
11-50
DAC-86
COMDAC® Companding
D/A Converter
11-58
DAC-88
COMDAC® Companding
D/A Converter
REF-lO
11-67
+ 10V Precision Voltage Reference
DAC-89
COMDAC® Companding
D/A Converter
1-5
f.l-<
tj
TABLE OF
CONTENTS
Precision Mo])olithics Inc.
Section
11
11-76
DAC·I00
Section
contmued
11-149
10-Bit Current-Output D/A Converter
11-84
DAC·208
DAC·210
11-159 PM·7528
Dual 8-Bit Buffered Multiplying CMOS
D/A Converter
DAC·312
12-Bit High-Speed Multiplying
D/A Converter
11-175
11-104 DAC·888
BYTEDAC® 8-Bit High-Speed
"Microprocessor Compatible"
Multiplying D/A Converter
11-116
11-185
PM·7541
CMOS 12-Bit Monolithic Multiplying
D/A Converter
DAC·1508A/1408A
11-195 PM·7542
12-Bit Multiplying CMOS
D/A Converter
11-122 DAC·8012
CMOS 12-Bit Multiplying D/A
Converter "With Memory"
11-196 PM·7543
12-Bit Serial-Input Multiplying CMOS
D/A Converter
DAC·8212
Dual 12-Bit Buffered Multiplying
CMOS D/A Converter
11-197
11-136 DAC·8408
Quad 8-Bit Multiplying CMOS D/A
Converter With Memory
PM.7545/PM.7645
12-Bit Buffered Multiplying CMOS
D/A Converters
11-208 PM·7548
12-Bit Multiplying CMOS
D/A Converter
11-140 PM·562
12-Bit Multiplying Current-Output
D/A Converter
11-148
PM·7533
CMOS Low Cost lO-Bit Multiplying
D/A Converter
8-Bit Multiplying D/A Converters
11-131
PM·7226
11-150 PM·7524
CMOS 8-Bit Buffered Multiplying
D/A Converter
11-Bit Voltage-Output D/A Converter
11-92
continued
Quad 8-Bit CMOS D/A Converter
With Voltage Output
9-Bit Voltage-Output D/A Converter
11-88
11
11-209 JM38510/11301/11302
JAN 8-Bit Multiplying D/A Converters
PM·565A
Complete High-Speed 12-Bit
Monolithic D/A Converter
1-6
TABLE OF
CONTENTS
Precision Monolithics Inc.
Section
12
Analog-to-Digital Converters
12-3
Introduction
12-3
Definitions
12-7
ADC-910
High-Speed "Microprocessor
Compatible" A/D Converter
12-19
ADC-8208
Microprocessor-Compatible 8-Bit
CMOS A/D Converter
Section
Analog Switches/Multiplexers
Introduction
13-3
Definitions
13-7
SW-Ol/SW-02
Quad SPST JFET Analog Switches
13-14
SW-05
Dual SPST JFET Analog Switch
13
13-69
MUX-88
8-Channel Analog Multiplexer For
PCM CODECs
13-74
DMX-88
8-Channel Analog De-Multiplexer
Section
14
contmued
Sample-and-Hold Amplifiers
13
13-3
Section
14-3
Introduction
14-3
Definitions
14-6
SMP-IO/SMP-ll
Low-Droop-Rate/Accurate Sampleand-Hold Amplifiers
14-15
SMP-81
Telecommunications Sample-andHold Amplifier
Section
15
Special Functions
SW-06
Quad SPST JFET Analog Switch
15-3
Introduction
15-3
Definitions
13-33
SW-201/SW -202
Quad SPST JFET Analog Switches
15-4
13-40
SW-7510/SW-7511
Quad SPST JFET Analog Switches
GAP-Ol
General-Purpose Analog Signal
Processing Subsystem
15-19
PKD-Ol
Monolithic Peak Detector
13-22
13-48
MUX-08/MUX-24
8-Channel/Dual 4-Channel JFET
Analog Multiplexers
13-59
MUX-16lMUX-28
16-Channel/Dual 8-Channel JFET
Analog Multiplexers
1-7
TABLE OF
CONTENTS
Precision Monolithics Inc.
Section
16
Section
Communications Products
16-3
16-4
Introduction
17-17
17-17
17-18
17-18
RPT-82/RPT-83
Package Information
17-19
17-19
17-19
17-19
17-20
17-20
17-20
17-20
Metal Cans
6-Lead TO-78 Metal Can
8-Lead TO-99 Metal Can
lO-Lead TO-IOO Metal Can
17-4
17-4
17-5
17-5
17-6
17-7
17-8
8 -Lead Ceramic DIP
14-Lead Ceramic DIP
16-Lead Ceramic DIP
18 -Lead Ceramic DIP
20-Lead Ceramic DIP
24- Lead Ceramic DIP
28 -Lead Ceramic DIP
Ceramic DIPs
17-13
17-13
17-14
17-14
17-15
17-16
lO-Lead Flatpack
lO-Lead Flatpack, Bottom-Brazed
14-Lead Flatpack
14-Lead Flatpack, Bottom-Brazed
16-Lead Flatpack
16-Lead Flatpack, Bottom-Brazed
24- Lead Flatpack
24-Lead Flatpack, Bottom-Brazed
Leadless Chip Carriers
17-21
17-22
20-Position Chip Carrier
28-Position Chip Carrier
Section
18
Sales Offices, Representatives,
and Distributors
Side-Brazed DIPs
17-9
17-9
17-10
17-10
17-11
17-12
10-Lead Cerpack
14-Lead Cerpack
16-Lead Cerpack
24-Lead Cerpack
Flatpacks
17
17-3
17-3
17-3
continued
Cerpacks
PCM Repeaters
Section
17
14-Lead Side-Brazed DIP
16-Lead Side-Brazed DIP
18-Lead Side-Brazed DIP
20-Lead Side-Brazed DIP
24-Lead Side-Brazed DIP
28-Lead Side-Brazed DIP
18-2
Sales Offices, Representatives
North America
18-4
Authorized Distributors
North America
18-6
Sales Offices, Representatives
International
Epoxy DIPs
18-7
Authorized Distributors
International
8-Lead Epoxy DIP
14-Lead Epoxy DIP
16-Lead Epoxy DIP
18 -Lead Epoxy DIP
20-Lead Epoxy DIP
24- Lead Epoxy DIP
1-8
Table of Contents 1
Ordering Infornlation 2
Product Assurance Program 3
Industry Cross Reference 41
Operational Amplifiers 5
Instrumentation Amplifiers 6
Voltage Followers/Buffers 7
Voltage Comparators 8
Matched Transistors 9
Voltage References 10
Digital-to-Analog Converters 11
Analog-to-Digital Converters 12
Analog Switches/Multiplexers 13
Sample-and-Hold Amplifiers 14
Special Functions 15
Communications Products 16
Package Information 17
Sales Offices, Representatives and Distributors 18
ORDERING
INFORMATION
Precision MOl1olithics Inc.
PACKAGED PRODUCTS PART NUMBERING SYSTEM
, . . . . - - - - - - - - - Device Type Be Model Number
r--------
IiI
~-----
CAC-08 BI
_ _ __
Q /883
!
I
L . . ._ _ _ _
Burn-In Option
Electrical Grade
Package Suffix
MIL-STD-883, Class B, Revision C Option
PMI -55 0 C to +125 0 C devices are available with MIL-STD-883,
Class B, Revision C screening as standard products. To order an 883
part, simply add the designation 1883 to the part number. For example,
the DAC-08AQ, screened to the 883 requirements would be ordered as
a DAC-08AQ/883. Contact factory for 883 device specifications.
Package Type
S = Not used
T = 28 lead Ceramic DIP
TC = 28 position LCC'
U = Not used
o = Not used
V = 24 lead Ceramic DIP
P = Epoxy DIP
X = 18 lead Ceramic DIP
Q = 16 lead Ceramic DIP
V = 14 lead Ceramic DIP
R = 20 lead Ceramic DIP
Z = 8 lead Ceramic DIP
RC = 20 position LCC'
"Available on certain 883 products
Note: See more complete listing on page 17-2.
H
= 6 lead TO-78 Can
= 8 lead TO-99 Can
K = 10 lead TO-100 Can
J
L.....-_ _ _ _
1 -_ _ _ _ _ _
Select electrical grade from data sheet.
PMI offers all 00/70°C and -25°/+85°C devices with burn-in per method
1015.5 of MIL-STD-883, 160 hours at +125°C or 80 hours at +150°C at
PMI's option. Parts with this option are specified with the letters BI added between the model number and the electrical grade. For example, to
order DAC-08EQ with burn-in, the part number is DAC-08BIEQ.
' - - - - - - - - - - Device types are listed on next page. Select model number from
product listings.
MIL-M-38S10
PMI's factory is certified to produce JAN parts per MIL-M-38510. Consult factory for availability of specific slash sheet part numbers. At this
writing, devices with Part 1 or Part 2 approval include PM-155A,
PM-156A, PM-157A, PM-108A, PM-210BA, PM-4136, DAC-08, OP-07,
and OP-27. Other types are being qualified.
See Table of Contents for JAN data sheet listings.
2·2
ORDERING
INFORMATION
I'n:cisiou MOlloli;thics Inc.
DICE PART NUMBERING SYSTEM
r----------- Device Type Be Model Number
r-------- Electrical Grade
N = Top, G = Middle, GR = Lowest
r------- Temperature-Tested Ole Option (125
r---- Visual Criteria
0
C)
A = MIL-STD-883, Method 2010, Test Condition A.
B = MIL-STD-883, Method 2010, Test Condition B.
r--- Backing Suffix
__ 1
-I
C = Plain, CG = Gold Backed
CAe-OS N T B C
I .
All PMI dice are available with ellher plain backing or, for a 50% adder
plus a $250 lot charge, a 1-micron-thick eutectic-bonded gold backing.
Several PMI devices are available with min/max wafer probe limitsfordice
tested at +125 0 C. See specific data sheet.
' - - - - - - - - Data sheets give specific available grades for each PMI device.
1----------- Device 1\tpe
ADC
AMP
aUF
CMP
DAC
DMX
GAP
JAN
MAT
MUX
OP
PKD
PM
REF
RPT
SMP
SW
-
Analog-to-Digital Converter
Instrumentation Amplifier
Buffer (Voltage Follower)
Comparator
Digital-to-Analog Converter
De-Multiplexer
General-Purpose Analog Processor
MIL-M-38510 Slash Sheet
Matched Transistor
Multiplexer
Proprietary Operational Amplifier
Peak Detector
Second-Source, Industry Specifications
Voltage Reference
PCM Line Repeater
Sample-and-Hold Amplifier
Analog Switch
' - - - - - - - - - - - Select model number from product listings.
2-3
ORDERING
INFORMATION
Precision Monolithics Inc.
DICE INFORMATION
is separated into individual dice. Due to variations in assembly methods and normal yield loss,
PMI does not guarantee specifications after
packaging for standard dice. Sample assembly
and testing in standard PMI packages to specified LTPD's and min/max specifications are
available at extra cost. Consult factory for dice
lot qualification negotiation.
Triple Passivation
Triple Passivation is a three-step process which
provides superior reliability and protection for
all PMI integrated circuits. First, a specially
treated thermal silicon dioxide layer is grown.
This protects the junctions and also attracts any
residual ionic impurities to the top surface of the
oxide, where they are held fixed. Next, a layer of
silicon nitride is applied to prevent the entry of
any potential contamination or impurities. The
third step is the thick glass overcoat layer which
leaves only the bonding pads exposed. This
"glassivation" protects the die from damage during assembly and is especially important in minimizing yield loss during shipment and assembly
of dice for hybrid circuits.
Shipping
Protection during shipment is provided by a wafflepack carrier with anti-static shield and
cushioning strip. In addition, the wafflepack is
vacuum sealed in a polyethylene bag.
Military/Aerospace Applications
PMI devices are widely used in military and
aerospace programs. A partial listing includes:
Quality Assurance
PMI believes that quality and reliability must be
built into the product; no amount of testing can
replace these inherent properties. For this reason, devices are fabricated and processed with
many exclusive processes and controls added to
improve quality and reliability. The integrity of
aluminum metallization is confirmed by
sampling wafer lots using Scanning Electron
Microscope (SEM) examinations per Method
2018 specifications.
Military Aircraft
F-4
8-18
Sikorsky UH-60A
A-1O
Sikorsky SH-3
YC-15
P-3
S-3A
KC-10
Mechanical Information
Missile/Spacecraft
Aluminum metallization with a nominal thickness of 10,000 angstroms is standard for all
devices. Die thickness is 19 mils minimum to 21
mils maximum. Minimum bonding pad size is 4.0
mils X 4.0 mils for all devices.
Viking
(Mars Orbitor)
Aerosat
Harm Missile
DSCS-3
Sparrow Missile
Trident
TDRSS
TV SAT
Intelsat 5
Minuteman
Visual Inspection
All dice are 100% visually inspected to the applicable visual criteria per MIL-STD-883 Method
2010, Condition 8.
Electrical Testing
All dice are 100% tested to the 25° C DC wafer
test limits shown in this catalog before the wafer
2-4
F-111
F-15
8-52
F-18
Alpha Jet
E-3A
F-16
F-5
Tornado
Milstar
Voyager
(Jupiter/Saturn)
Stinger Missile
Standard Missile"
Tiros-N
Cruise Missile
Ariane
Roland
Eurosat
Space Shuttle
ORDERING
INFORMATION
Precision Monolithics Inc.
Electronic Systems
Omega
Tram
Aims (MK86)
F-16
(Ground Support)
Pave Spike
AWACS
Miscellaneous
RFP Model 35 #13
Project 4620
Heads-Up Display
DST 1860
Walleye
PMS
Aerial Surveillance
Camera
ICs to the unique in-house speCifications of
their customers. PMI recognizes your special
needs and welcomes the opportunities provided
by the military/aerospace industry. Hi-rei is a
cornerstone of PMl's business and we will continue to offer the extra processing that your
applications require.
A4KU
MK-48
8-52 Radar Mod
Pathfinder Radar
MK-46
Seaguard
Gepard
Radiation Resistance
As a leading supplier of precision linear ICs to
the military/aerospace industry, PMI is supportive of the system designer's needs for readily
available, standard components that are radiation resistant. A number of standard PMI linear
integrated circuits have characteristically demonstrated good resistance to radiation. These
devices have been subjected to radiation levels
necessary to perform effectively in military/aerospace radiation environments, and they are
now being used in a number of demanding military and space programs.
Cutty Sark
Compass Tie
System 27
ACM
VCS
Naval Submarine
Periscope
RELIABILITY INFORMATION
MIL-STD-883C
PM I standard "883" parts are man ufactu red to
be in full compliance with all MIL-STD-883
requirements. See Section 3 for more details.
Experiments to isolate the processing mechanisms that led to PMl's increased radiation
hardness characteristics have pointed heavily
toward the use of a silicon nitride passivation
layer. While we do not believe that this process
is the only radiation hardening advantage of PMI
devices, it does add a great deal to survivability.
Specials
At PMI, we have a proven track record for handling "customer specials". Many IC manufacturers shy away from processing precision linear
For more information request PMl's "Radiation
Resistance" brochure.
2-5
z
9
~
2
z
......
ORDERING
INFORMATION
JPMI)
Precision Monolithics Inc.
DISCONTINUED DEVICE
TYPES ORDERING GUIDE
Note 2. DAC-76 -55 0 CI+ 1250 C types may be ordered as
DAC-86 specials.
Note 3. DAC-89EX has idling currents on the outputs
requiring matched load resistors. DAC-89EX has
higher speed and accuracy and is an improved,
direct, pin-lor-pin replacement lor DAC-87 in most
designs.
Between 1978 and 1985 some device types,
individual grades, and package options were
discontinued. This guide is provided to help the
designer to select an appropriate alternative
device.
Alternative Device "TYpe
OP-07 connected as a
voltage follower.
BUF-02
OP-16 connected as a
voltage follower.
DAC-04
DAC-06 nearest grade.
DAC-76
DAC-86 nearest grade.
DAC-78
DAC-88EX.
DAC-87
DAC-89EX.
DAC-101 DAC-100 "03" nearest
grade.
DAC-206 DAC-01 nearest grade.
DAC-808 DAC-888 is the most
similar device.
OP-03
OP-04 with externallyconnected V+ pins.
OP-18
LM101 is the most
similar device.
OP-19
MC17418 is the most
similar device.
OP-24
OP-27GP, improved
replacement.
OP-34
OP-37GP, improved
replacement.
PM-1458 OP-14 nearest grade.
PM-1558 OP-14 nearest grade.
PM-4136 OP-09 nearest grade.
888-725 OP-06 or PM-725
nearest grade.
888-741
OP-02 nearest grade.
888-747 OP-04 or PM-747
nearest grade.
888-1458 OP-14 nearest grade.
888-1558 OP-14 nearest grade.
8W-03
8W-06 is a functional
replacement.
8W-04
8W-06 is a functional
replacement.
"TYpe
BUF-01
Note(s)
1
1,2
1
3
Package "TYpe
Affected
Device Type
"K" (TO-100)
PM-747.
"N" (Flatpack)
DAC-100N9.
"Y" (14-pin DIP) 8ee list below.
Remarks
Available
on 8pecials.
Available
on 8pecials.
Available
on 8pecials.
"Y" Package Option: Affected Device Types
CMP-01
OP-02
PM-725
CMP-02
OP-06
PM-741
OP-01
OP-220
The "Y" package option was discontinued for
some products. They are all available in other
package types including "J" (TO-99), "P" (Epoxy
DIP), or "Z" (Ceramic 8-pin Mini-DIP). 8ee
individual data sheets for available package
options for each device.
Discontinued-Electrical-Grade Ordering Guide
The following electrical grades were discontinued but are available with different
specifications in the same packages. 8ee
individual data sheets.
CMP-01 B
MAT-01 F
PM-255
PM-256
CMP-02B
OP-01 E
PM-257
DAC-05B
OP-01 F
PM-339
DAC-05F
OP-04GR
PM-355
DAC-20E
OP-08B
PM-356
DAC-88C
OP-08F
PM-357
DAC-89C
OP-09C
PM-2208
DAC-10001
OP-09G
PM-2308
DAC-10002
PM-239
REF-Om
DAC-100DD05 PM-239A
DAC-100DD06
Five volt output versions of DAC-02 and DAC-05,
"X2" suffix, were discontinued. They may be
ordered as DAC-03X2 specials.
8ixty volt breakdown versions of MAT -01 were
discontinued (MAT-01H and MAT-01FH).
Note 1. Direct, pin-lor-pin replacement. No design
changes required.
2-6
Table of Contents 1
Ordering Information 2
Industry Cross Reference 4
Operational Amplifiers 5
I
i
6:
I
Instrumentation Amplifiers
Voltage Followers/Buffers 7
Voltage Comparators 8
Matched Transistors 9
Voltage References 10
Digital-to-Analog Converters 11
Analog-to-Digital Converters 12
Analog Switches/Multiplexers 13
Sample-and-Hold Amplifiers 14
Special Functions 15
Communications Products 16
Package Information 17
Sales Offices, Representatives and Distributors 18
PRODUCT
ASSURANCE
Precision Monolithics Inc.
3-3
Introduction
3-3
Processing
3-2
PRODUCT
ASSURANCE
Precision Monolithics Inc.
INTRODUCTION
nearest PMI Sales Office or the Literature
Department for the latest issue of the PMI Reliability Bulletin.
PMI has long been recognized as a High Quality/Reliability supplier of Commercial, Industrial
and Military/Aerospace Products. The PMI Product Assurance Department plays a vital role in
controlling processes to ensure the manufacture
of highly reliable, cost-effective product, and
to make certain that all pertinent customer
specifications and requirements are met.
The Reliability Department also performs failure
analyses as required.
Program Management - The primary responsibility of the Program Management Department
is to ensure that the MIL-M-38510 JAN Program
and other special customer program requirements
are met. This is accomplished by monitoring the
in-house procedures used to define each process step of a particular program. If necessary,
baselining documentation is written detailing
specific procedures and processing flows. A
Configuration Control System consisting of
maintenance of PMI standard baselining for
each device type, as well as notification to customers of major process and product changes,
are also responsibilities of this group.
ORGANIZATION
Product Assurance Department of PMI is composed of four functional departments: Process
Quality Control, Quality Assurance, Reliability,
and Program Management.
RESPONSIBILITIES
Process Control- The primary responsibility of
the Process Control Department is to establish
and maintain effective controls over process
integrity by monitoring manufacturing processes
and equipment operation; to provide real-time feedback of information concerning the status of
these controls; and to initiate statistically
valid techniques to further improve quality and
reliability levels. These concepts are used
extensively throughout all manufacturing
processes.
Contact the nearest PMI Sales Office or the Literature Department for a copy of the comprehensive PMI Product Assurance Manual.
QUALITY LEVELS
PMI processes to stringent quality standards.
Quality guarantees range from parts-per-million on Standard Product to imposed Quality
Levels dictated by customer specification on
custom orders.
Current information on Quality Levels is
available upon request; contact the nearest PMI
Sales Office or the Literature Department.
Quality Assurance (Standard and HI-Rei) - The
primary responsibility of the Quality Assurance
Department is to assure that the delivered product meets PMI or Customer Product Standards
of reliability and quality. Process monitors and
gate inspections are designed so that all devices
are properly tested and required sample tests are
performed prior to shipment. Inspection records
and reports concerning monitor and inspection
data keep all cognizant personnel fully informed
about the status of the quality level of products
going through final test operations.
PROCESSING
The cornerstone of the manufacturing of PMI
hermetic products is the strict adherence to all
requirements of MIL-STD-883, Level B, for our
"883" product line. All PMI hermetic products,
be they "full 883" or not, receive the benefit of
MIL-STD-883 processing through assembly.
The manufacture of plastic devices is inherently
different from hermetic in the area of assembly.
Automation of the assembly line has produced a
tightly process-controlled product that requires
few interim inspections from wafer fabrication to
pre-mold visual. Plastic product may also be
obtained with a burn-in (BI) option (see Section
2, Ordering Information for further details).
Reliability - The Reliability Department assures
a high and consistent reliability of PMI products.
The Reliability Department establishes, defines,
and maintains evaluation programs to determine process/product reliability. The Reliability
Department will issue periodic reports on the
results of all evaluation testing. Contact the
3-3
:§
~
C)
~
~
~
u~
~
~
......
Q
~
~
PRODUCT
ASSURANCE
DATA SHEET SPECIFICATIONS
PMI standard product is guaranteed to meet the
published limits under the test conditions shown
in the data sheet. Where practical, PM I performs
100% testing of the indicated parameters;
however, following accepted industry practice,
certain parameters may be guaranteed by
sample testing or by using design and/or
characterization data.
PMI provides separate data sheets for all "883"
products in strict conformance with MIL-STD883, Method 5005.8 and MIL-M-38510F,
Appendix B. Interim Electrical Test Parameters
(pre-burn-in), Final Electrical Test 'Parameters,
Group A Test Parameters, and guidelines used
for PDA calculations, are all detailed in tabular
form on the "883" data sheets.
It Is highly recommended that the "883" data sheet
be used as a baseline for new military or
aerospace Source Control Drawings. Consult
your sales representative to obtain these "883"
data sheets.
Upon completion of this internal re-qualification, PMI informs all customers who have
requested process change notification with a
complete description of the change, along with
applicable reliability or characterization data.
Upon request, PMI will assist customers in their
internal re-qualification effort.
STANDARD PROCESS FLOWS
(JAN 38510. Cia •• B. 883 Cia., B; PMllndu,trlaIiCommerclal)
010 Flbrlcallon
Incoming Inspection 01 all orltlcal raw materials used In fabrication, (I.e. wafers,
masks, dopant. chemicals).
Scanning electron microscope/x-ray dlsburslve system controls oxide profiles,
diffUSion profiles and metallization Integrity,
Ole sort - automated eleotrlcal teat at room or elevated temperature as required,
Ole preparation - wafer saw
Ole sort visual
ToA••• mbly,
H.rmetfa
Semiautomatic die attach
TESTING
Testing of electrical parameters is generally
performed using pulse testing techniques on
automated test equipment. Unless otherwise
specified, chip temperature remains close to the
ambient temperature.
PROCESS CHANGE NOTIFICATION
PMI reviews all process, product, and package
changes for possible impact on form, fit, or
function. All major changes are submitted for a
re-qualification, which may include electrical,
mechanical, and/or thermal characterization.
Where applicable, reliability re-qualification is
performed.
(eutectic)
PI.,II.
Automatic die attach (epoxy)
Semiautomatic bonding
(aluminum wire)
Automatic bonding (gold wire)
FlowS 1, 2, 3
F're-mold visual
Continued on facing page.
F'lsstlc molding
F'ost-mold cure
Temperature cycle
Electrical test (Flow 4)
Continued on faCing page,
PRODUCT
ASSURANCE
......ccision MOllolithics Inc.
Flow 1
MIL·SID·883
MEIHOD 8004 CLASS B/
JAN 3B810
Flow 2
MIL·SID·8B3
MEIHOD 8004 CLASS B
(Soo Nolo 1)
Flow 3
PMI SIANDARD
HERMEIIC DEVICES
Flow 4
PMI SIANDARD
PLASIIC DEVICES
Ellclrlcal 100t
+28'C (Optional)
Burn-In Test
Mulll·Optlon
Final Eleclrlcal lest
al+25'C
(See
ote3)
I
NOlES:
1. M IL·883 product Is a..omblod/lesled porlho roqulre·
mont. ot MIL·M·38510 and MIL·SID·883, Rov, C, Class
B, as well as te.ted !=Ief PMI electrical test programs.
PDA = 5'110 @ 25'C (Subgroup 1).
Note: In·hous.t.st .paclflcatlons are aVClllable upon
reque.t.
2. Standard prOduct Is available with burn-In options.
Multiple burn-In conditions are available.
3. Standard product II tested at 25°C with programs
guard banded tor all temperatures.
4. As required by dotallod 'po.llication.
QAPlanl
Clearance
country of Origin AssemblyCodes: United States = 5, Korea"" K. Philippines = D, Puerto Rico = P
3·5
QAPlanl
Clearance
Table of Contents 1
Ordering Information 2
Product Assurance Program 3
Industry Cross Reference 4
Operational Amplifiers 5
Instrumentation Amplifiers 6
Voltage Followers/Buffers 7
Voltage Comparators 8
Matched Transistors 9
Voltage References 10
Digital-to-Analog Converters 11
Analog-to-Digital Converters 12
Analog Switches/Multiplexers 13
Sample-and-Hold Amplifiers 14
Special Functions 15
Communications Products 16
Package Information 17
Sales Offices, Representatives and Distributors 18
ALPHANUMERIC DIRECT
REPLACEMENT GUIDE
Precision Monolithics Inc.
Device
PMI Replacement
Device
PMI Replacement
Device
PMI Replacement
AD10SAH
AD10SH
AD140S-7D
AD140S-8D
AD150S-8D
PM10SAJ
PM10SJ
DAC140SA7Q
DAC140SASQ
DAC150SASQ
AD7524KN
AD7524LN
AD7524SD
AD7524TD
AD7524UD
PM7524HP
PM7524GP
PM7524BQ
PM7524BQ
PM7524AQ
ADDACOSCD
ADDACOSD
ADDACOSED
ADDACOSHD
ADDAC100JD
DACOSCQ
DACOSQ
DACOSEQ
DACOSHQ
DAC100BCQ7
AD20SAH
AD20SH
AD30SAH
AD30SAN
AD30SH
PM20SAJ
PM20SJ
PM30SAJ
PM30SAP
PM30SJ
AD752SAQ
AD752SBQ
AD752SCQ
AD752SJN
AD752SKN
PM752SFR
PM752SFR
PM752SER
PM752SHP
PM752SHP
ADDAC100KD
ADDAC100LD
ADDAC100SD
ADG200AA
ADG200AP
DAC100ABQ7
DAC100AAQ7
DAC100BCQ5
SW05BK
SW05BY
AD562AD
AD562KD
AD562SD
AD7226KN
AD7226TD
PM562FV
PM562HV
PM562AV
PM7226GP
PM7226AR
AD752SLN
AD752SSD
AD752STD
AD752SUD
AD7533AD
PM752SGP
PM752SBR
PM752SBR
PM752SAR
PM7533FQ
ADG200BA
ADG200BP
ADG200CJ
ADG201AP
ADG201BP
SW05FK
SW05FY
SW05GP
SW201BQ
SW201FQ
;,D7506JD
AD7506JN
AD7506KD
AD7506KN
AD7506SD
MUX16ET
MUX16ET
MUX16ET
MUX16ET
MUX16BT
AD7533BD
AD7533CD
AD7533JN
AD7533KN
AD7533LN
PM7533FQ
PM7533EQ
PM7533HP
PM7533HP
PM7533GP
ADG201CJ
ADOP07AH
ADOP07CH
ADOP07CN
ADOP07DH
SW201GP
OP07AJ
OP07CJ
OP07CP
OP07DJ
AD7506TD
AD7507JD
AD7507JN
AD7507KD
AD7507KN
MUX16BT
MUX2SET
MUX2SET
MUX2SET
MUX2SET
AD7533SD
AD7533TD
AD7533UD
AD7541AD
AD7541BD
PM7533BQ
PM7533BQ
PM7533AQ
PM7541FX
PM7541EX
ADOP07DN
ADOP07EH
ADOP07EN
ADOP07H
Am140SL6
OP07DP
OP07EJ
OP07EP
OP07J
DAC140SA6Q
AD7507SD
AD7507TD
AD7510DIJD
AD7510DIKD
AD7510DISD
MUX2SBT
MUX2SBT
SW7510FQ
SW7510FQ
SW7510BQ
AD7541JN
AD7541KN
AD7541SD
AD7541TD
AD7542BD
PM7541HP
PM7541GP
PM7541BX
PM7541AX
PM7542FR
Am140SL7
Am140SLS
Am140SN6
Am140SN7
Am140SNS
DAC140SA7Q
DAC140SASQ
DAC140SA6P
DAC140SA7P
DAC140SASP
AD7511DIJD
AD7511DIKD
AD7511DISD
AD7511DITD
AD7520JD
SW7511FQ
SW7511FQ
SW7511BQ
SW7511BQ
PM7533FQ
AD7542GBD
AD7542GKN
AD7542GTD
AD7542KN
AD7542TD
PM7542ER
PM7542GP
PM7542AR
PM7542HP
PM7542BR
Am150SLS
Am6012DC
Am6012DM
Am6012PC
Am6070ADC
DAC150SASQ
DAC312FR
DAC312BR
DAC312FR
DACS6CX
AD7520JN
AD7520KD
AD7520KN
AD7520LD
AD7520LN
PM7533HP
PM7533FQ
PM7533HP
PM7533EQ
PM7533GP
AD7543BD
AD7543GBD
AD7543GKN
AD7543GTD
AD7543KN
PM7543FR
PM7543ER
PM7543GP
PM7543AR
PM7543HP
Am6070DC
Am6072DM
Am6S5DL
Am6S5DM
Am6S5HL
DACS6EX
DACSSEX
CMP07FQ
CMP07BQ
CMP07FK
AD7520SD
AD7520TD
AD7520UD
AD7521JD
AD7521JN
PM7533BQ
PM7533BQ
PM7533AQ
PM7541FX
PM7541HP
AD7543TD
AD7545CQ
AD7545GCQ
AD7545GLN
AD7545GUD
PM7543BR
PM7545FR
PM7545ER
PM7545GP
PM7545AR
Am6S5HM
CA10SAT
CA10ST
CA145SE
CA145SG
CMP07BK
PM10SAJ
PM10SJ
OP14CP
OP14EP
AD7521KD
AD7521LD
AD7521LN
AD7521SD
AD7521TD
PM7541FX
PM7541FX
PM7541HP
PM7541BX
PM7541BX
AD7545LN
AD7545TD
AD7545UD
AD754SAQ
AD754SBQ
PM7545HP
PM7545CR
PM7545BR
PM754SFR
PM754SER
CA145SS
CA145ST
CA155SS
CA155ST
CA20SAT
OP14EP
OP14C
OP14J
OP14J
PM20SAJ
AD7521UD
AD7524AD
AD7524BD
AD7524CD
AD7524JN
PM7541BX
PM7524FQ
PM7524FQ
PM7524EQ
PM7524HP
AD754SJN
AD754SKN
AD754SSD
AD754STD
ADDACOSAD
PM754SHP
PM754SGP
PM754SBR
PM754SAR
DACOSAQ
CA20ST
CA30SAT
CA30SE
CA30ST
CA339AD
PM20SJ
PM30SAJ
PM30SP
PM30SJ
PM 339AY
4·2
ALPHANUMERIC DIRECT
REPLACEMENT GUIDE
Precision Monolithics Inc.
Device
PMI Replacement
Device
PMI Replacement
Device
PMI Replacement
CA339AG
CA747CE
CA747CG
CA747CT
CA747T
CMP04FP
OP04CY
OP04CY
OP04CK
OP04K
DG202CJ
DG202CK
DG506AR
DG506BR
DG506CJ
SW202GP
SW202FQ
MUX16AT
MUX16ET
MUX16FT
LF13201N
LF13202D
LF13202N
LF13333D
LF13333N
SW201GP
SW202FQ
SW202GP
SW06FQ
SW06GP
DAC0800LCJ
DAC0800LCN
DAC0801LCJ
DAC0801LCN
DAC0802LCJ
DAC08EQ
DAC08EP
DAC08CQ
DAC08CP
DAC08HQ
DG507AR
DG507BR
DG507CJ
DG508AP
DG508BP
MUX28AT
MUX28ET
MUX28FT
MUX08AQ
MUX08EQ
LF13508D
LF13508N
LF13509D
LF13509N
LF155AH
MUX08EQ
MUX08EP
MUX24EQ
MUX24EQ
PM155AJ
DAC0802LCN
DAC0806LCJ
DACOB06LCN
DAC0807LCJ
DAC0807LCN
DAC08HP
DAC1408A6Q
DAC1408A6P
DAC140BA7Q
DAC1408A7P
DG508CJ
DG509AP
DG509BP
DG509CJ
HI-200-2
MUX08FP
MUX24AQ
MUX24EQ
MUX24FP
SW05BY
LF155AJ-8
LF155H
LF156AH
LF156AJ-8
LF156H
PM155AZ
PM155J
PM156AJ
PM156AZ
PM156J
DAC0808LCJ
DAC0808LCN
DAC0808LD
DAC08ADM
DAC08CDC
DAC140BA8Q
DAC1408A8P
DAC1508A8Q
DAC08AQ
DAC08CQ
HI-200-4
HI-200-5
HI-201-2
HI-201-4
HI-201-5
SW05FY
SW05GP
SW201BQ
SW201FQ
SW201GP
LF156J-8
LF157AH
LF157AJ-8
LF157H
LF351H
PM156Z
PM157AJ
PM157AZ
PM157J
OP15FJ
DAC08CN
DAC08DM
DACOBEDC
DAC08EF
DACOBEN
DAC08CQ
DAC08Q
DAC08EQ
DACOBEQ
DAC08EP
HI1-506-2
HI1-506-5
HI1-506A-2
HI1-506A-5
HI1-507-2
MUX16BT
MUX16FT
MUX16BT
MUX16ET
MUX28BT
LF353H
LF355AH
LF355AJ-8
LF355BJ
LF356AH
OP215FJ
PM355AJ
PM355AZ
PM355Z
PM356AJ
DAC08F
DAC08HC
DAC08HD
DAC08HF
DAC08HN
DAC08Q
DAC08HP
DAC08HQ
DAC08HQ
DAC08HP
HI1-507-5
HI1-507A-2
HI1-507A-5
HI1-562A-2
HI1-562A-5
MUX28ET
MUX28AT
MUX28ET
PM562AV
PM562AV
LF356AJ-8
LF357AH
LF357AJ-8
LF411ACH
LF411ACN
PM356AZ
PM357AJ
PM357AZ
OP15EJ
OP15EZ
DAC10BDM
DAC10CDM
DAC10FCC
DAC10GDC
DAC6012ADC
DAC10BX
DAC10CX
DAC10FX
DAC10GX
DAC312FR
HI1-562A-8
HI1-7541AD-4
H11-7541 BD-4
HI1-7541JD-5
HI1-7541KD-5
PM562HVl883
PM7541 FX
PM7541 EX
PM7541HP
PM7541GP
LF411AMH
LM108AD
LM108AH
LM108AJ-8
LM108D
OP15AJ
PM108AZ
PM108AJ
PM108AZ
PM108Z
DAC6012ADM
DAC6012DC
DAC6012DM
DG200AA
DG200AAA
DAC312BR
DAC312FR
DAC312BR
SW05BK
SW05BK
HI1-7541SD-2
HI1-7541TD-2
HI2-200-2
HI2-200-4
HI3-506-5
PM7541BX
PM7541AX
SW05BK
SW05FK
MUX16FT
LM108H
LM108J-8
LM139AD
LM139AF
LM139AJ
PM108J
PM108Z
PM139AY
PM139AY
PM139AY
DG200AAK
DG200ABA
DG200ABK
DG200ACJ
DG200AP
SW05BY
SW05FK
SW05FY
SW05GP
SW05BY
HI3-506A-5
HI3-507-5
HI3-507A-5
HI3-508A-5
HI3-509A-5
MUX16ET
MUX28FT
MUX28ET
MUXOBEP
MUX24EP
LM139D
LM139F
LM139J
LM1458AH
LM1458AJ-8
PM139Y
PM139Y
PM139Y
OP14EJ
OP14EZ
DG200BA
DG200BP
DG200CJ
DG201AAK
DG201ABK
SW05FK
SW05BY
SW05GP
SW201BQ
SW201FQ
HI4-508A-2
HI4-508A-5
HI4-509A-2
HI4-509A-5
LF11201D
MUX08BQ
MUX08EQ
MUX24BQ
MUX24FQ
SW201BQ
LM1458AN
LM1458H
LM1458J
LM1458N
LM1558AH
OP14EP
OP14CJ
OP14CZ
OP14DP
OP14AJ
DG201AP
DG201BP
DG201CJ
DG202AK
DG202BK
SW201BQ
SW201FQ
SW201GP
SW202BQ
SW202FQ
LF11202D
LF11333D
LF11508D
LF11509D
LF13201 D
SW202BQ
SW06BQ
MUX08AQ
MUX24AQ
SW201FQ
LM1558AJ
LM194H
LM208AD
LM208AH
LM208AN
OP14AZ
MAT02AH
PM20BAZ
PM208AJ
PM208AZ
~
U
~
~
~
~
(/)
(/)
~
U
~
~
::J
Cl
Z
>-+
4-3
---~~-~----
-
--------
-
--~------~---~-----
--
-~"-
--
------
-----
._----.
-
-- -
----
--.
------
ALPHANUMERIC DIRECT
REPLACEMENT GUIDE
Precision Monolithics Inc.
Device
PMI Replacement
Device
PMI Replacement
Device
PMI Replacement
LM208D
LM208H
LM208N
LM239AD
LM239D
PM208Z
PM208J
PM208Z
CMP04FY
CMP04FY
MC1504U10
MC1504U5
MC15088F
MC1508L8
MC1558G
REF01AZ
REF02AZ
DAC15088Q
DAC1508A8Q
OP14J
MP7506KD
MP7506TD
MP7507JD
MP7507JN
MP7507KD
MUX16ET
MUX16BT
MUX28ET
MUX28FT
MUX28ET
LM239F
LM239N
LM258P
LM2901F
LM2901J
CMP04FY
CMP04FP
OP221GZ
CMP04FY
CMP04BY
MC1558NG
MC1558NU
MC1558U
MC1741CG
MC1741CP1
OP14AJ
OP14AZ
OP14Z
OP02CJ
OP02CP
MP7507KN
MP7507SD
MP7507TD
MP7508DIJD
MP7508DIJN
MUX28FT
MUX28BT
MUX28BT
MUX08EQ
MUX08EP
LM2901N
LM308AD
LM308AH
LM308AJ-8
LM308AN
CMP04FP
PM308AZ
PM308AJ
PM308AZ
PM308AP
MC1741CU
MC1741G
MC1741NCG
MC1741NCP1
MC1741NG
OP02HJ
OP02J
OP02Z
OP02HZ
OP02J
MP7508DIKD
MP7508DISD
MP7524AD
MP7524BD
MP7524CD
MUX08EQ
MUX08AQ
PM7524FQ
PM7524FQ
PM7524EQ
LM308D
LM308H
LM308J-8
LM3302N
LM339AD
PM308Z
PM308J
PM308Z
CMP04FP
PM339AY
MC1741NU
MC1741SCG
MC1741SCP1
MC1741SG
MC1741U
OP02Z
OP01HJ
OP01CP
OP01J
OP02Z
MP7524JN
MP7524KN
MP7524LN
MP7524SD
MP7524TD
PM7524HP
PM7524HP
PM7524GP
PM7524BQ
PM7524BQ
LM339AF
LM339AJ
LM339AN
LM339D
LM339N
PM339AY
PM339AY
CMP04FP
PM339AY
CMP04FP
MC1747CL
MC1747CP2
MC1747G
MC1747L
MC3302N
OP04EY
OP04EY
OP04BK
OP04BY
CMP04FP
MP7524UD
MP7528BD
MP7528CD
MP7528KN
MP7528LN
PM7524AQ
PM7528FR
PM7528ER
PM7528HP
PM7528GP
LM358JG
LM394H
LM725AH
LM725CH
LM725CN
OP221HZ
MAT02EH
OP06AJ
OP06EJ
OP06GZ
MC35001AG
MC35001AU
MC35001BG
MC35001BU
MC4741CL
OP16AJ
OP16AZ
OP16GJ
OP16BZ
OP11GY
MP7528TD
MP7528UD
MP7533BD
MP7533CD
MP7533KN
PM7528BR
PM7528AR
PM7533FQ
PM7533EQ
PM7533HP
LM725H
LM747AH
LM747AJ
LM747CH
LM747CJ
OP06BJ
OP04K
OP04AY
OP04CK
OP04CY
MC4741CP
MC4741L
MC7506KN
MC7506SD
MP200DIAA
OP11GP
OP11CY
MUX16FT
MUX16BT
SW05BK
MP7533LN
MP7533TD
MP7533UD
MP7541TD
MP7621AD
PM7533GP
PM7533BQ
PM7533AQ
PM7541AX
PM7541FX
LM747CN
LM747EJ
LM747EN
LM747H
LM747J
OP04DY
OP04EY
OP04CY
OP04BK
OP04Y
MP200DIAP
MP200DIBA
MP200DIBP
MP201DIAP
MP201DIBP
SW05BY
SW05FK
SW05BY
SW201BQ
SW201FQ
MP7621BD
MP7621JN
MP7621KN
MP7621SD
MP7621TD
PM7541EX
PM7541HP
PM7541GP
PM7541BX
PM7541AX
MC14087F
MC14088F
MC1408F
MC1408L6
MC1408L7
DAC14087Q
DAC14088Q
DAC1408A7Q
DAC1408A6Q
DAC1408A7Q
MP201DICJ
MP4136CY
MP4136Y
MP5520AD
MP5520AZ
SW201GP
OP09FY
OP09BY
DAC01Y
DAC01AY
MP7623AD
MP7623BD
MP7623JN
MP7623KN
MP7623SD
PM7541FX
PM7541EX
PM7541HP
PM7541GP
PM7541BX
MC1408L8
MC1458CG
MC1458CP1
MC1458CU
MC1458G
DAC1408A8Q
OP14CJ
OP14CP
OP14CZ
OP14CJ
MP5520BD
MP5520CD
MP5520DD
MP5520FD
MP5520HD
DAC01BY
DAC01CY
DAC01DY
DAC01FY
DAC01HY
MP7623TD
MP7645CD
MP7645LN
MP7645UD
MPC4D
PM7541AX
PM7645ER
PM7645GP
PM7645AR
MUX24FQ
MC1458N
MC1458NP1
MC1458NU
MC1458P
MC1458P1
OP14CP
OP14EP
OP14EZ
OP14CP
OP14DP
MP562AD/BIN
MP562KD/BIN
MP562SD/BIN
MP7506JD
MP7506JN
PM562FV
PM562HV
PM562AV
MUX16ET
MUX16FT
MPC8S
MPOP01AJ
MPOP01AZ
MPOP01CJ
MPOP01CP
MUX08FQ
OP01AJ
OP01AZ
OP01CJ
OP01CP
4-4
ALPHANUMERIC DIRECT
REPLACEMENT GUIDE
Precision M0]101ithics Inc.
Device
PMI Replacement
Device
PMI Replacement
Device
PMI Replacement
MPOP01CZ
MPOP01GJ
MPOP01GZ
MPOP01HJ
MPOP01HP
OP01CZ
OP01GJ
OP01GZ
OP01HJ
OP01HP
MPOP12FJ
MPOP12FZ
MPOP12GJ
MPOP12GZ
MPOP27AJ
OP12FJ
OP12FZ
OP12GJ
OP12GZ
OP27AJ
MPREF02HP
MPREF02HZ
MPREF02J
MPREF02Z
NE5007E
REF02HP
REF02HZ
REF02J
REF02Z
DAC08CQ
MPOP01HZ
MPOP02AJ
MPOP02AZ
MPOP02BJ
MPOP02BZ
OP01HZ
OP02AJ
OP02AZ
OP02BJ
OP02BZ
MPOP27AZ
MPOP27BJ
MPOP27BZ
MPOP27CJ
MPOP27CZ
OP27AZ
OP27BJ
OP27BZ
OP27CJ
OP27CZ
NE5008F
NE5009F
NE532H
NE532N
OP07AH
DAC08EQ
DAC08HQ
OP221CJ
OP221GZ
OP07AJ
MPOP02CJ
MPOP02CP
MPOP02CZ
MPOP02DJ
MPOP02DP
OP02CJ
OP02CP
OP02CZ
OP02DJ
OP02DP
MPOP27EJ
MPOP27EP
MPOP27EZ
MPOP27FP
MPOP27FZ
OP27EJ
OP27EP
OP27EZ
OP27FP
OP27FZ
OP07AH/883
OP07AJ8
OP07 AJ8/883
OP07AT
OP07CH
OP07AJ/883
OP07AZ
OP07AZ/883
OP07AJ
OP07CJ
MPOP02DZ
MPOP02EJ
MPOP02EP
MPOP02EZ
MPOP02J
OP02DZ
OP02EJ
OP02EP
OP02EZ
OP02J
MPOP27GJ
MPOP27GP
MPOP27GZ
MPOP37AJ
MPOP37AZ
OP27GJ
OP27GP
OP27GZ
OP37AJ
OP37AZ
OP07CJ8
OP07CJG
OP07CN8
OP07CNB
OP07CT
OP07CZ
OP07CZ
OP07CP
OP07CP
OP07CJ
MPOP05AJ
MPOP05AZ
MPOP05BJ
MPOP05CJ
MPOP05CZ
OP05AJ
OP05AZ
OP05BJ
OP05CJ
OP05CZ
MPOP37BJ
MPOP37BZ
MPOP37CJ
MPOP37CZ
MPOP37EJ
OP37BJ
OP37BZ
OP37CJ
OP37CZ
OP37EJ
OP07DE
OP07DH
OP07DN8
OP07DNB
OP07DT
OP07Z
OP07DJ
OP07DP
OP07DP
OP07DJ
MPOP05DJ
MPOP05EJ
MPOP05EZ
MPOP05J
MPOP05Z
OP05DJ
OP05EJ
OP05EZ
OP05J
OP05Z
MPOP37EP
MPOP37EZ
MPOP37FJ
MPOP37FP
MPOP37GJ
OP37EP
OP37EZ
OP37FJ
OP37FP
OP37GJ
OP07EDE
OP07EH
OP07EJ8
OP07EJG
OP07EN8
OP07EZ
OP07EJ
OP07EZ
OP07EZ
OP07EP
MPOP07AJ
MPOP07AZ
MPOP07CJ
MPOP07CP
MPOP07CZ
OP07AJ
OP07AZ
OP07CJ
OP07CP
OP07CZ
MPOP37GP
MPOP37GZ
MPREF01AJ
MPREF01AZ
MPREF01CJ
OP37GP
OP37GZ
REF01AJ
REF01AZ
REF01CJ
OP07ET
OP07H
OP07H/883
OP07J8
OP07J8/883
OP07EJ
OP07J
OP07J/883
OP07Z
OP07Z/883
MPOP07DJ
MPOP07DP
MPOP07DZ
MPOP07EJ
MPOP07EP
OP07DJ
OP07DP
OP07DZ
OP07EJ
OP07EP
MPREF01CP
MPREF01CZ
MPREF01EJ
MPREF01EZ
MPREF01HJ
REF01CP
REF01CZ
REF01EJ
REF01EZ
REF01HJ
OP07T
OP12AJG
OP12BJG
OP12CJG
OP12EJG
OP07J
OP12AZ
OP12BZ
OP12CZ
OP12EZ
MPOP07EZ
MPOP07J
MPOP10CY
MPOP10EY
MPOP11AY
OP07EZ
OP07J
OP10CY
OP10EY
OP11AY
MPREF01HP
MPREF01HZ
MPREF01J
MPREF01Z
MPREF02AJ
REF01HP
REF01HZ
REF01J
REF01Z
REF02AJ
OP12FJG
OP12GJG
OP15AH
OP15BH
OP15CH
OP12FZ
OP12GZ
OP15AJ
OP15BJ
OP15CJ
MPOP11BY
MPOP11EY
MPOP12AJ
MPOP12AZ
MPOP12BJ
OP11BY
OP11EY
OP12AJ
OP12AZ
OP12BJ
MPREF02AZ
MPREF02CJ
MPREF02CP
MPREF02CZ
MPREF02DJ
REF02AZ
REF02CJ
REF02CP
REF02CZ
REF02DJ
OP15EH
OP15FH
OP15GH
OP16AH
OP16BH
OP15EJ
OP15FJ
OP15GJ
OP16AJ
OP16BJ
MPOP12BZ
MPOP12CJ
MPOP12CZ
MPOP12EJ
MPOP12EZ
OP12BZ
OP12CJ
OP12CZ
OP12EJ
OP12EZ
MPREF02DP
MPREF02DZ
MPREF02EJ
MPREF02EZ
MPREF02HJ
REF02DP
REF02DZ
REF02EJ
REF02EZ
REF02HJ
OP16CH
OP16EH
OP16FH
OP16GH
OP227AJ
OP16CJ
OP16EJ
OP16FJ
OP16GJ
OP227AY
4-5
--
----~-
------
--
-----~--~------
----
--
----
~---
.--
~
U
~
~
~
~
~
t/)
t/)
~
U
~
!;;
:::J
Cl
Z
ALPHANUMERIC DIRECT
REPLACEMENT GUIDE
Precisioll Monolithics Inc.
Device
PMI Replacement
Device
PMI Replacement
Device
PMI Replacement
OP227CJ
OP227EJ
OP227FJ
OP227GJ
OP27AT
OP227CY
OP227EY
OP227FY
OP227GY
OP27AJ
REF-01CDE
REF-01CT
REF-01DDE
REF-01DE
REF-01EDE
REF01CZ
REF01 CJ
REF01HZ
REF01Z
REF01EZ
TSC9496CJ
TSC9496EE
XRC277
.uA0801CDC
.uA0801CPC
REF01HP
REF01 EJ
RPT82FQ
DAC08EQ
DAC08CP
OP27BDE
OP27BT
OP27BT/883
OP27CDE
OP27CH
OP27BZ
OP27BJ
OP27BJ/883
OP27CZ
OP27CJ
REF-01ET
REF-01HT
REF-01T
REF-02ADE
REF-02AT
REF01EJ
REF01HJ
REF01J
REF02AZ
REF02AJ
.uA0801DM
.uA0801EDC
.uA0802ADC
.uA0802APC
.uA0802BDC
DAC08Q
DAC08EQ
DAC1408A8Q
DAC1408A8P
DAC1408A7Q
OP27CH/883
OP27CJ8
OP27CJ8/883
OP27CT
OP27EDE
OP27CJ/883
OP27CZ
OP27CZ/883
OP27CJ
OP27EZ
REF-02CDE
REF-02CT
REF-02DDE
REF-02DE
REF-02EDE
REF02CZ
REF02CJ
REF02HZ
REF02Z
REF02EZ
.uA0802BPC
.uA0802CDC
.uA0802CPC
.uA0802DM
.uA0802DMQB
DAC1408A7P
DAC1408A6Q
DAC1408A6P
DAC1508A8Q
DAC1508A8Q/883
OP27EH
OP27EJ8
OP27EN8
OP27ET
OP27FT
OP27EJ
OP27EZ
OP27EP
OP27EJ
OP27FJ
REF-02ET
REF-02HT
REF-02T
REF01AH
REF01CH
REF02EJ
REF02HJ
REF02J
REF01AJ
REF01CJ
.uA0802EPC
.uA108AH
.uA1 08H
.uA1 39ADM
.uA139DM
DAC08EP
PM108AJ
PM108J
PM139AY
PM139Y
OP27GDE
OP27GH
OP27GJ8
OP27GN8
OP27GT
OP27GZ
OP27GJ
OP27GZ
OP27GP
OP27GJ
REF01CN8
REF01EH
REF01H
REF01HH
REF01HN8
REF01CP
REF01 EJ
REF01J
REF01HJ
REF01HP
.uA208AH
.uA208H
.uA308AH
.uA308H
.uA3303PC
PM208AJ
PM208J
PM308AJ
PM308J
OP11FP
OP37ADE
OP37AH
OP37AH/883
OP37AJ8
OP37AJ8/883
OP37AZ
OP37AJ
OP37AJ/883
OP37AZ
OP37AZ/883
REF02AH
REF02CH
REF02CN8
REF02DH
REF02DN8
REF02AJ
REF02CJ
REF02CP
REF02DJ
REF02DP
.uA339ADC
.uA714EHC
.uA714HC
.uA714HM
.uA714LHC
PM339AY
OP07EJ
OP07CJ
OP07AJ
OP07DJ
OP37AT
OP37BDE
OP37BT
OP37BT/883
OP37CDE
OP37AJ
OP37BZ
OP37BJ
OP37BJ/883
OP37CZ
REF02EH
REF02H
REF02HH
REF02HN8
RM725T
REF02EJ
REF02J
REF02HJ
REF02HP
PM725J
.uA725HC
.uA725HM
.uA725TC
.uA741CJG
.uPC1251 C
PM725CJ
PM725J
PM725CP
PM741CZ
OP220GZ
OP37CH
OP37CH/883
OP37CJ8
OP37CJ8/883
OP37CT
OP37CJ
OP37CJ/883
OP37CZ
OP37CZ/883
OP37CJ
RM741T
RM747DC
SA1458N
SA741
SE532H
PM741J
OP04Y
OP14BZ
OP02BZ
OP221 BJ
.uPC1251D
.uPC151C
.uPC151 D
.uPC154D
.uPC156D
OP220FZ
OP02BZ
OP02CZ
OP05CZ
PM208Z
OP37EDE
OP37EH
OP37EJ8
OP37EN8
OP37ET
OP37EZ
OP37EJ
OP37EZ
OP37EJ
OP37EJ
SE5534AFE
SE5534FE
SSS1408A-6Q
SSS1408A-7Q
SSS1408A-8Q
OP27BZ
OP27CZ
DAC1408A6Q
DAC1408A7Q
DAC1408A7Q
.uPC251C
.uPC251 D
.uPC339C
.uPC358C
.uPC4581 C
OP14EP
OP14EZ
CMP04FP
OP221HZ
OP15GZ
OP37GDE
OP37GH
OP37GJ8
OP37GN8
OP37GT
OP37GZ
OP37GJ
OP37GZ
OP37GP
OP37GJ
SSS1508A-8Q
TSC7541BD
TSC7541JN
TSC7541KN
TSC7541SD
DAC1508A8Q
PM7541EX
PM7541HP
PM7541GP
PM7541BX
.uPC603D
.uPC610D
.uPC624C
.uPC624D
.uPC648D
DAC01CY
DAC02CCX1
DAC08EP
DAC08EQ
DAC312FR
RC1458NB
RC3302DB
RC725T
REF-01ADE
REF-01AT
OP14CP
CMP04FP
PM725CJ
REF01AZ
REF01AJ
TSC7541TD
TSC9495CE
TSC9495CJ
TSC9495EE
TSC9496CE
PM7541AX
REF02HJ
REF02HP
REF02EJ
REF01HJ
.uPC801C
OP15FZ
4-6
Table of Contents 1
Ordering Information 2
Product Assurance Program 3
Industry Cross Reference 4
Operational Amplifiers 5
Instrumentation Amplifiers 6
Voltage Followers/Buffers 7
Voltage Comparators 8
Matched Transistors 9
Voltage References 10
Digital-to-Analog Converters 11
Analog-to-Digital Converters 12
Analog Switches/Multiplexers 13
Sample-and-Hold Amplifiers 14
Special Functions 15
Communications Products 16
Package Information 17
Sales Offices, Representatives and Distributors 18
OPERATIONAL
AMPLIFIERS
Precision Monolithics Inc.
5-4
Introduction
5-4
Definitions
5-6
Selection Guide
5-12
OP-Ol
Inverting High-Speed
Operational Amplifier
5-18
5-91
5-105
5-111
5-43
5-51
OP-02
5-117
OP-04/0P-14
5-128
op-os
Instrumentation
Operational Amplifier
5-140
5-75
5-87
OP-27
OP-06
High-Gain Instrumentation
Operational Amplifier
5-152
OP-32
High-Speed Programmable Micropower
Operational Amplifier
OP-37
Low-Noise Precision High-Speed
Operational Amplifier
OP-07
5-164
OP-41
Low-Bias-Current JFET
Operational Amplifier
OP-08
Precision Low-Input-Current
Operational Amplifier
5-68
OP-22
Programmable Micropower
Operational Amplifier
Low-Noise Precision
Operational Amplifier
Ultra-Low Offset Voltage
Operational Amplifier
5-61
OP-21
Low-Power Operational Amplifier
Dual Matched High-Performance
Operational Amplifiers
5-34
OP-20
Micropower Operational Amplifier
General-Purpose
Operational Amplifier
5-26
OP-lS/0P-16/0P-17
Precision JFET-Input
Operational Amplifiers
5-175
OP-43
Low-Bias-Current, Fast JFET
Operational Amplifier
Quad Matched 741-Type
Operational Amplifiers
5-180
OP-I0
Dual Matched Instrumentation
Operational Amplifier
OP-SO
High-Output-Current
Operational Amplifier
5-191
OP-12
Precision Low-Input-Current
Operational Amplifier
OP-77
Next Generation OP-07 (Ultra-Low
Offset Voltage Operational Amplifier)
5-197
OP-09/0P-ll
OP-90
Low-Voltage Micropower
Operational Amplifier
5-2
OPERATIONAL
AMPLIFIERS
Pn'CI;"IOIl MOIlolnh,,:s Inc
5-199
OP-207
5-265
5-268
5-205
OP-215
5-270
OP-220
5-273
OP-221
5-276
OP-227
5-279
OP-400
JM38510/11401/11402/11403/11404/
OP-420
5-282 11405/11406
JAN JFET-Input Operational Amplifiers
Quad Micropower Operational Amplifier
5-246
OP-421
5-292 JM38510/13501/13502
Ultra-Low Offset Voltage
Operational Amplifiers
Quad Low-Power Operational Amplifier
PM-I08A/PM-208A/PM-308A/
PM-I08/PM-208/PM-308/
5-252 PM-2108A/PM-2108
5-295
Low-Input-Current
Operational Amplifiers
5-256
IM38510/11004
JAN Quad 741-Type
Operational Amplifier
Quad Low-Offset Low-Power
Operational Amplifier
5-241
JM38510/10106
JAN Dual Low-Input-Current
Operational Amplifier
Dual Low-Noise Low-Offset
Instrumentation Operational Amplifier
5-239
JM38510/10104
JAN Single Low-Input-Current
Operational Amplifier
Dual Low-Power Operational Amplifier
5-228
PM-747
Dual Compensated
Operational Amplifier
Dual Micropower Operational Amplifier
5-220
PM-741
Compensated Operational Amplifier
Dual Precision JFET-Input
Operational Amplifier
5-212
PM-725
Instrumentation Operational Amplifier
Dual Ultra-Low Vos Matched
Operational Amplifier
IM3851O/13503
Low-Noise Precision
Operational Amplifier
PM-1461PM-246
Programmable Quad
Operational Amplifiers
PM-155A/PM-355A/PM-1551
PM-156A/PM-356A/PM-1561
5-259 PM-157A/PM-357A/PM-157
Monolithic JFET-Input
Operational Amplifiers
5-3
~
!-I-l
......
~
2
~
~
0......
~C3
OPERATIONAL
AMPLIFIERS
Precision MOllolith ics Inc.
INTRODUCTION
High Accuracy
OP-05, OP-06,
OP-07, OP-77
OP-27, OP-37, OP-50
OP-227, OP-207, OP-10
OP-08, OP-12
OP-50
Precision Monolithics pioneered in the development of low-offset, high-gain operational
amplifiers for use in precision applications. A
proprietary linear bipolar process with nitride
passivation was developed to achieve low noise,
enhanced long-term reliability, and improved resistance to radiation effects. PMI operational
amplifier processing capability includes JFET
and super-beta devices as well as standard NPN
and PNP devices. A zener-zap trimming technique was designed to reduce input offset voltage at the wafer testing stage. Offset trimming
is performed in discrete steps by applying highcurrent pulses through automatically-selected
zener diodes. High-current pulsing shorts the
zener which is parallel-connected to a trim resistor. Zener-zap trimming provides a very reliable
and stable reduction of input offset voltage. PMI
has developed many innovative operationalamplifier circuit designs based on their lownoise, low-drift processing in combination with
zener-zap offset trimming.
The table below summarizes the PMI families
of operational amplifiers. All feature low input
offset voltage, low drift, and high open-loop
gain.
Low Vos, High Gain
Low Vos, Low Noise
Dual
Low IB, Low Power
High Output Current
Low Power, Low Input-Bias-Current
OP-21
Single
OP-221
Dual
OP-41
JFET Input
PM-108/208/308,
PM-2108 (Dual)
Micropower
OP-20
OP-22/32
OP-220
OP-420,OP-421
Low IB, LM-108 Type
Singles, Low ISY
Programmable
Dual
Quad
DEFINITIONS
Average Bias Current Drift (TCla) - The ratio
of change in input bias current to a change in
temperature.
Average Offset Current Drift (TClos) - The ratio
of change in input offset current to a change in
temperature.
Average Offset Voltage Drift (TCVos) - The
ratio of change in input offset voltage to a
change in temperature.
Operational Amplifiers
General Purpose, Bipolar Input
OP-02
Single
OP-04, OP-14
Dual
Quad
OP-09, OP-11
OP-01
High Speed, Inverting
Average Offset Voltage Drift With External
Trimming (TCVOSN) - The ratio of the change
in input offset voltage to a change in temperature with the input offset voltage trimmed
to zero at room temperature.
General Purpose, JFET Input
PM-155, PM-156,
PM-157
Standard JFET Input
38510 Versions
MIL-Grade, 38510
Common-Mode Input Resistance (RlnCM)
- The ratio of input voltage range to the change
in input bias current over this range.
Precision, High-Speed Improved JFET Input
OP-15, OP-16, OP-17,
OP-43, OP-215 (Dual)
Common-Mode Rejection Ratio (CMRR)
- The ratio of the common-mode voltage range
(CMVR) to the peak-to-peak change in equivalent input offset voltage (CME) over this
range. CMRR is specified for a specific CMVR.
CMRR = 20 10glO (CMVR/CME)
5·4
OPERATIONAL
AMPLIFIERS
Precision Monolithics Inc.
Gain-Bandwidth Product (GBW) - The
frequency at which the open-loop gain equals
unity.
Input Bias Current (Ia) - The average of the
currents into the two input terminals when the
output is at zero volts with no load. IB is
measured at VCM = O.
Power Dissipation (Pd) - The total power
dissipated in the amplifier with the output at
zero volts with no load.
Input Noise Current (I np _p) - The peak-to-peak
noise current within a specified frequency band.
Slew Rate (SR) - The ratio of a change in
output voltage to the minimum time required to
effect this change under large-signal drive conditions. Slew rate may be specified separately
for positive and negative-going changes.
Power Supply Rejection Ratio (PSRR) - The
inverse ratio of change in input offset voltage to
a change in power supply voltage. PSRR can be
specified in dB or jJ.VIV.
Input Noise Current Density (In) - The rms
noise current in a 1Hz band centered on a
specified frequency.
Supply Current (ISY) - The current required
from the power supply to operate the amplifier
with no load and the output at zero volts.
Input Noise Voltage (enp-p) - The peak-to-peak
noise voltage within a specified frequency band.
Input Noise Voltage Density (en) - The rms
noise voltage in a 1Hz band centered on a
specified frequency.
Unity-Gain Closed-Loop Bandwidth (BW)
-The frequency at which the magnitude of the
small-signal voltage gain of the amplifier, operated closed-loop as a unity-gain follower, is
3dB below unity.
Input Offset Current (los) - The difference
between the currents into the two input
terminals when the output is at zero volts with
no load.
MATCHING PARAMETER DEFINITIONS
Input Resistance-Differential Mode (RIN) - The
ratio of small-signal change in input voltage to a
change in input current at either input terminal
with the other grounded.
Input Offset Voltage Match (~Vos) - The difference between the offset voltages of side A and
side B (VasA - VOSB)· If VaSA = VOSB, the net
differential offset voltage at the output of the
amplifier pair equals zero.
Input Offset Voltage Tracking (TC~Vos)
- The ratio of change in ~VOS to a change in
temperature.
Input Voltage Range (IVR) - The range of input
voltage for which the device will operate as a
linear amplifier.
Average Nonlnvertlng Bias Current (Ia+) - The
average of the side A and side B noninverting
input bias currents:
Large-Signal Voltage Gain (Avo) - The ratio
of change in output voltage (over a specified
range) to a change in input voltage.
IBA+ + IBB+
2
Noninverting Input Offset Current (los +) - The
difference between the noninverting input bias
currents of side A and side B; (IBA+ -IBB+).
Inverting Input Offset Current (los -) - The
difference between the inverting input bias
currents of side A and side B; (I BA- - I BB- ).
Average Drift Of Noninverting Bias Current
(TCla+) - The ratio of change in noninverting
bias current to a change in temperature.
Input Offset Voltage (Vos) - The voltage which
must be applied between the input terminals to
obtain zero output voltage with no load.
Open-Loop Output Resistance (Ro) - The
small-signal driving-point resistance of the
output terminal with respect to ground at a
specified quiescent DC output voltage and
current.
Output Voltage Swing (Vo) - The peak output
voltage that can be obtained without clipping
into a specified load resistance.
5-5
II
OPERATIONAL
AMPLIFIERS
Precision Monolithics Inc.
Average Drift of Noninverting Offset Current
(TClos+) - The ratio of change in noninverting
offset current to a change in temperature.
rate needs. Distortion is often critical for audio
use and fast settling may be essential in a dataconversion application.
Common-Mode Rejection-Ratio Match (aCMRR)
- The difference between the common-mode
rejection ratios (expressed in volt/volt of side A
and side B. aCMRR in dB = 20 10glO (aCMRR in
volt/volt).
Output Load - Op amps are sometimes called
upon to drive long cables, storage capacitors,
transformers, or other semiconductors. Highspeed circuits generally require low-impedance
feedback elements and the load is usually low
impedance; therefore, relatively high output
current drive is needed for high-speed circuits.
Power Supply Rejection-Ratio Match (aPSRR)
- The difference between the power supply
rejection ratios (expressed in volt/volt) of side A
and side B. aPSRR in dB = 20 10glO (aPSRR in
volt/volt).
Channel Separation - The ratio of change in
offset voltage of one channel to a change in
output voltage in the second channel.
Environmental Conditions - Temperature
range and power supply characteristics are very
important factors. Power supply drain is often
critical in battery-powered equipment, process
control systems, and satellites. In addition,
op-amp package type is generally dictated by
environmental and cost factors. Another factor
to consider is the electrical environment. Minimize accuracy degradation from unavoidable
ground noise and power supply fluctuations by
choosing an op amp with high CMRR and
PSRR.
SELECTION PRINCIPLES
Selecting an operational amplifier can be a
frustrating experience. The choice of circuit
configuration, and of associated component
values, interrelates to the choice of op amp for
a given application. Op amps are specified as
open-loop devices, but in a circuit application
they generally have feedback applied. The
designer must predict the closed-loop circuit
performance as determined by his choice of op
amp and choice of circuit configuration (and
component tolerances). Detailed literature is
available on circuit configurations to accomplish
particular analog circuit functions using op
amps. This Selection Guide gives recommended
guidelines and a design strategy for selecting op
amps to best meet your needs.
2. Use the published op-amp specifications
and characterization graphs.
PMI provides comprehensive specification
tables with well-defined test conditions for
operation at 25° C and over specific temperature ranges. The "Typical Performance Curves"
show the characteristic response of an op amp to
variations in frequency, temperature, supply
voltage, or load impedance. Since op amps often
perform much better than indicated by their mini
max specification limits, the designer may be
tempted to ask for special selection to tighter
limits. Although sometimes necessary, special
selection tends to be costly. A better strategy is
to select a standard op amp that meets the
application need on a worst-case basis. Careful
initial selection of a high-performance standard
op amp will provide predictable circuit performance on a continuing basis.
The first design steps are to:
1. Completely define the design objectives.
Input Signal- Determine the signal level,
frequency content, and impedance of the input.
Accuracy Required - For lillear amplification,
this consists of limits for offset, gain error, and
nonlinearity. Establish your bandwidth and slew
5-6
OPERATIONAL
AMPLIFIERS
Precision Monolithics Inc.
Two factors will generally dictate the op amp
choice:
1. The loop gain (excess of open-lOOp gain
over closed-loop gain) must be sufficient at
the highest frequency of interest. For example,
if 1.0% accuracy at 10kHz is required when
operating at closed-loop gain of 10, then the op
amp must have an open-loop gain of at least
1000 at 10kHz (10/1000 = 1%). When operating
at high closed-loop gains, decompensated op
amps generally offer the advantage of better
gain bandwidth product without a price/
performance penalty.
Selection Process
Operational amplifiers can be divided into four
basic functional categories:
Category
Primary Characteristics
General Purpose
"741" types.
High Accuracy
Low input offsets
(Vas < 1mV), high DC
gain, high CMRR, and
low noise. Leading part
types are OP-05, OP-07,
OP-27, OP-50, and
OP-77.
High Speed
Optimized for high slew
rate, high gain-bandwidth, and fast settling
time.
Low Power,
Wide Supply Range
Low supply drain
(Isy < 1 mAl, wide input
and output voltage range.
Includes micropower
(Isy < 100J.LA) units for
battery operation.
2. Slew rate must be high enough to follow the
fastest signal input without causing distortion or
other anomalies. Slew-rate symmetry, linearity,
and overload recovery should be considered.
The detrimental effects of slew-rate limiting can
be subtle; it is best to avoid trouble by choosing
an op amp with at least a 20% safety margin in
minimum slew-rate.
High speed implies a need for high output
current. Applications such as audio amplifiers,
active filters, DAC-output amplifiers, and fast
integrators often require high output currents for
driving feedback capacitors or low-impedance networks. Driving such capacitive loads as long
cables or storage capacitors at high frequency
requires high output currents.
There can be overlap between some categories, while others are mutually exclusive.
For example, the PMI OP-22 covers both "High
Accuracy" and "Low Power". However, "High
Speed" and "Low Power" tend to be mutually
exclusive; it is difficult to simultaneously
optimize both speed and power.
DC Considerations
If the frequency requirements are relatively
modest (SR < 10VlJ.Ls) and the circuit requires
closed-loop gain above unity, choose a "High
Accuracy" op amp. These op amps feature:
Economics is another important dimension of
the selection process. The "General Purpose"
category is generally lowest in cost, but a "High
Accuracy" op amp with low input-offset-voltage
may be more cost effective if it eliminates the
need for external trimming components. The
PMI high-accuracy OP-07 is often used in place
of general-purpose 741-types because of its
low input-offset-voltage and high gain.
Low Input Offsets
Low Input Offset
Voltage
Low Input Bias
Current
- Bipolar Input
Stage
- JFET Input
Stage
AC Considerations
Consideration of AC requirements for an
application is a good starting pOint in the op
amp selection process. If high frequency
(GBW> 10MHz, SR > 10VlJ.Ls) is the primary
concern, then the choice quickly narrows down
to the "High Speed" category.
5-7
Vas':501mV,
TCVas':50 2J.LV/o C
18':50 100nA (18':50 10nA
is desirable)
18':50 200pA
II
OPERATIONAL
AMPLIFIERS
Precision MOllolithics Inc.
High Open-Loop
DC Gain
High Common-Mode
Rejection
Low Input Noise
at 100Hz
AVOL;:::: 1,000,000
The OP-41/43 JFET-input op amps have less
than ±5pA of input bias current, and the OP15/16/17 JFET-input op amps have bias currents
specified to within ±50pA. At high temperature,
however, the input bias current for JFET-input
op amps rises to a level which is typically 3
orders of magnitude higher than the roomtemperature value.
The OP-05, OP-07, OP-77, and OP-50 are bipolar op amps which have input bias cancellation
circuitry that significantly reduces input-biascurrent, and maintain low input-bias-current
levels over temperature. For example, the OP05/07/77 op amps have bias-current limits set at
±4nA over the full Military temperature range.
The OP-08, which is an improved LM108, has a
superbeta input stage which also provides very
good high-temperature high-impedance operation (Is S; 3nA at 125°C).
The OP-22/32 programmable micropower op
amps have PNP input stages which also have
very low input bias current over temperature.
Their input-bias-current remains below 5nA over
the full Military temperature range.
CMR;:::: 100dB
en
S;
15nVly'HZ
A leading op amp in the High-Accuracy
category is the PMI OP-77 with these key
specifications:
Vas S; 25,..tV
Is S; ±2nA, los S; 2nA
AVOL ;:::: 5,000,000
CMRR;:::: 114dB
en S; 11 nVly'HZ at 1000Hz
The OP-77 performs very well even at high
closed-loop gains. For example, consider a
non inverting configuration with a closed-loop
gain of 100. Assume a signal source with a range
of ±0.1V and source impedance of 10kO. If the
feedback resistances are chosen to be relatively
low, then the maximum offset caused by input
bias current will be 4.4nA (Is + 10512 = 4.4nA)
multiplied by the 10kO source resistance, or
44~V. Total input offset, even without external
offset nulling, will be less than 119~V (approximately 0.12% of full-scale). The effect of CMRR
is negligible in this example; the ±0.1V input
divided by 110dB of common-mode rejection is
only 0.3~V referred-to-input. Gain error factor is
1/(1 + AVCL/AvoL), which is a gain error of
approximately AVCL/AVOL. The DC gain error at
AVCL of 100 will be less than 10015,000,000, a
0.002%-of-full-scale gain error. The worst-case
sum of offset and gain errors for this example is
only 0.12% of full-scale, and is achieved without
any external trimming of offset or gain.
Low noise, always desirable, is sometimes the
primary consideration. In many high-gain
active-filter or audio-amplifier applications, low
noise can be more important than DC offset.
These are the three basic rules for obtaining low
noise:
Using low
impedances minimizes the effect of current
noise flowing through the source impedance,
reduces resistor thermal noise, and reduces stray
pick-up of RF noise.
2. Restrict the system bandwidth - Noise
outside the frequency range of interest can usually
be attentuated by filtering. Block high-frequency power-supply noise from the signal path
by use of decoupling capacitors at the op-amp
supply inputs.
1. Design with low impedances -
Selection of a specific op-amp type within the
High-Accuracy category is generally determined
by impedance levels of the input signal and
feedback elements. High impedances
(Rs> 10kO) imply a need for an op amp with low
input bias currents. This need for low bias current can be met through use of FET-input op
amps, or by using bipolar-input op amps specifically deSigned for low input-bias-current.
3. Select a low-noise op amp - Some op amps,
such as the bipolar-input OP-27, are designed
for minimum noise. The input stage current is
set to a relati~IY high value which reduces input
noise (5.5nVl Hz max at 10Hz). Output swing
5·8
OPERATIONAL
AMPLIFIERS
Pn."ClS10ll
M0l101ithics Inc.
is increased to ± 10V into 600n to allow the use
of low-impedance, low-noise feedback
elements.
The PMlline of low-power, wide-supply-range
op amps all feature high open-loop gain, low
input offsets, and high CMRR. They can provide
high accuracy even at high closed-loop gain.
Power Supply Considerations
The op-amp power-supply requirements are the
next factors to consider. If the circuit is to be
operated from a battery, such as in portable
instruments, missiles, or spacecraft, then narrow
the selection to the "Low-Power, Wide Supply
Range" category. Low-power op amps are
designed for minimum quiescent supply current.
Speed is traded off for lower power consumption and output drive is generally reduced. The
input and output stages are designed for linear
operation over a wide voltage range which is
very helpful for single-power-supply operation.
The low-power family includes programmable
micropower op amps that offer the designer
another dimension in circuit design. The quiescent supply current is set by an external resistor
which allows the circuit designer to trade off
quiescent supply current against speed. Since
the quiescent current directly controls slew rate
and gain-bandwidth product, these programmable op amps are easily frequencycompensated in such circuits as active filters,
oscillators, or multi-stage instrumentation
amplifiers.
DC ERROR CALCULATIONS FOR STANDARD CONFIGURATIONS
NONINVERTING CONFIGURATION
r--- ,
I INPUT I
I
I
I
Rs I
I
I
IVI'U
I
I _ _ .JI
~
(1+ ~~) [vos + (R~~R~2 - RS) Is + (R~~R~2 + Rs) I~S ]
Output Offset =
Special Cases:
Max Output Offset = (1
+
~~)
(vos + Rs lOS) if Rs =
R~~ ~2
- (1+ ~~) [vos + IR~\R~2 -Rslls] if 10soC Is
(lOS)].
R1 R'2
R2) [
- (1 + "Fi1 Vos + Rs Is + "'2 If Rs > R1 + R2
Note: Is is the average of the Input bias currents and los is the difference.
Gain Error -
(1
+ ~~)
A:O +
C~RR
• where Avo = Open-Loop Gain and Avo> (1
5-9
+ ~~)
OPERATIONAL
AMPLIFIERS
PreClsiOIl MOllolithlcS Inc.
INVERTING CONFIGURATION
INPUT
r----.,
I
I
I
I
I VI 'V
IL ____ .JI
Output Offset = (1 +
:~) [V os + (R~~ R~2 - RC)
Ie +
(R~~R~2 + Rc) I~S]
if Rs - 0
Special Cases:
MaxOutputOffset= (1+
:~)
(VOS+RCIOS) ifRc= :::2R2
- (1+ :~) [VOS+
- (1 +
IR~1+R~2-Rclle]
if 10s4!i Ie
:~) [VOS + R~1+R~2 (Ie + I~S)] if Rc = 0
Note: Ie is the average of the input bias currents and los is the difference.
1 + RRs
Gain Error - (1 + RR2) -A
1
VO
1
~
R1
,where Avo = Open-Loop Gain and Rs 4!i R1
5-10
OPERATIONAL
AMPLIFIERS
PrecisloJl Monolithics Inc.
input voltage noise. The OP-08 and OP-12 provide an excellent combination of low input-biascurrent, low offset voltage, and moderate power
drain. The OP-07 and its improved version, the
OP-77 offer a selection of the lowest offset
voltages (60,.LV max to 250lo'V max) combined
with low input-bias-current (±2nA max to
±12nA max) and have become an industry
standard for high-precision applications.
OPERATIONAL AMPLIFIER
SELECTION GUIDE
The Operational Amplifier Selection Guide
chart highlights PMl's line of operational amplifiers. The matrix indicates the most essential
parametric differences for each product group.
"General Purpose" op amps are usually the least
expensive and are recommended for applications where impedance levels are relatively
low, closed-loop gain is low, and speed
requirements are moderate. JFET inputs provide
lower input-bias-currents and better bandwidth
than standard bipolar inputs, but input voltage
offsets and noise are generally better for the
bipolar input amplifiers.
The "High Accuracy" category presents the best
amplifiers for high-gain applications. A combination of low input-offset-voltage, high openloop gain, and high CMRR provide excellent DC
accuracy even at high closed-loop gain. The
OP-27, OP-37 and OP-50 are best for minimum
General Purpose
Bipolar
Monolithic Technology
Precision
HighSpeed
JFET
Input
JFET
Packages
Single
Dual
Quad
Ultra Low Ollset, Vas < 200"V
Low Offset, Vas < lmV
Low Bias Current
Is" 100pA
High Gain, AYOL;o, 1 Million V/V
High Slew Rate, SR > 10V/"s
Low Power
Isy < 1mA/Ampllfler
Isy < 1OOIlA/Amplifler
1kHz)
en "SnV/JRZ
In" 0 25pA/JRZ
High
Accuracy
Low Power,
Low InputBiasCurrent
Micropower
•••••• •••••••••••
••••••
•
•
• • • • • •• •••• • • • • •
•
•
••
•
•
•
•
••
•
• ••
•••••
••••
• •• • •
•
••••••
•
•• ••• ••
•
•
•
••• •
••••• •
• •
•
• • • ••• ••
• •
• •• • •
•••
••••••• • •
••••
Bipolar Input
Low Noise (10
JFET
PMI is a leader in op amps featuring low power
consumption. The OP-20/21/22132 are
micropower op amps that operate with only a
few microamps of supply drain. PSRR and
CMRR are high, and the input-voltage-range is
wide. Such features work together to make
these amplifiers ideal for battery-powered
applications or for operation from a single
supply voltage. The OP-22/32 can be
programmed to operate over any supply current
from 11o'A to 400lo'A and is excellent for batterypowered designs.
•
•
•
•
•
5-11
OP-Ol
INVERTING HIGH -SPEED
OPERATIONAL AMPLIFIER
Precision MOIlolithics Inc.
FEATURES
•
•
•
•
•
•
•
•
•
•
and excellent DC input characteristics. An internal feedforward frequency compensation network provides simplicity of application - no external capacitors are required for
stable, high-speed performance. The fast output response Is
achieved without sacrifice of input bias current or power
consumption. A 250kHz typical power bandwidth is attained
with a small-signal bandwidth of only 2.5MHz, thus board
layout is non-critical. The OP-01 is completely protected at
both input and output, fits standard 741 sockets, and is offset
nulled with a 10k!} potentiometer.
Fast Settling Time ................... 1J's to 0.1% Max
High Slew Rate .......................... 12V1J's Min
Po_r Bandwidth ........................ 150kHz Min
Low Power Consumption .........•........ 90mW Max
Excellent DC Specifications
Internally Compensated
Ideal DAC Output Amplifier
MIL-STD-SS3 Processing Available
Fits Standard 741 Sockets
Low Cost
The fast output response combined with excellent settling
time makes the OP-011deal for use as a OfA converter output
amplifier.
ORDERING INFORMATIONt
PACKAGE
TA= 25°C
YosMAX
(mY)
HEFIMETIC
TO-"
I-PIN
HEFIMETIC
DIP
I-PIN
0.7
0.7
5.0
5.0
OP01J'
OP01HJ
OP01GJ'
OP01CJ
OP01Z'
OP01HZ
OP01GZ'
OP01CZ
PLASTIC
DIP
I-PIN
OP01HP
OP01CP
PIN CONNECTIONS
OPEFIATING
TEMPEFlATUFlE
flANGE
BAL98
MIL
COM
MIL
COM
N.C. 7
v+
sour
-IN 2
'For devices processed In total compliance to MIL-STD-883. add 1883 after
part number. Consult factory tor 883 data sheet.
tAli commercial and Industrial temperature range parts are available with
burn-In. For ordering information see 1986 Data Book, Section 2.
+IN 3
EPOXY MINI-DIP
(P-Sutflx)
&
S-PIN HERMETIC DIP
(Z-Sufflx)
GENERAL DESCRIPTION
The OP-01 series of monolithic inverting high-speed operational amplifiers combines high slew rate, fast settling time
5 BAL
4
v- (CASEI
TO-SS
(J-Sufflx)
SIMPLIFIED SCHEMATIC
V+
*Q1. QZ, Q3 AND Q4 FORM A
THERMALL V CROSS-COUPLED
QUAD. as. 0&1, 06 AND 06 1
COMPRISE A SIMILAR
THERMALLY CROSS-COUPLED
QUAD.
R'O
~---+--<>OUTPUT
RD
R,
RS
R2
BALANCE
5-12
1/86, Rev. A
---------Im
OP-01INVERTING HIGH-SPEED OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
(Note 2)
Lead Temperature (Soldering, 60 sec) ••••••••••••• 300·C
Total Supply Voltage, OP-01, OP-01 H, OP-01 N, OP-01 NT,
OP-01G, OP-01GT .............................. ±22V
OP-01G, OP-01C, OP-01GR ..................... ±20V
Power Dissipation (Note 1) ...................... 500mW
Differential Input Voltage .......................... ±30V
Input Voltage (Note 3) •••••••••••••••••••••••••••• ±15V
Short-Circuit Duration •••••••••••••••••••••••• Indefinite
Operating Temperature Range
OP-01, OP-01G ..................... -55·C to +125·C
OP-01H,OP-01C ....................... O·C to +70·C
DICE Junction Temperature (Tj) ••••••• -6S·C to +150·C
Storage Temperature Range
J and Z Packages.. .. .. .. • .. • .. .. ... -65· C to + 150· C
P Package ......................... -65·C to +125·C
ELECTRICAL CHARACTERISTICS at Vs = ±
15V, TA
NOTES:
1. See table lor maximum ambient temperature rating and derating lactor.
PACKAGE TYPE
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
7.1mW'oC
TO-99 (J)
80°C
8-Pin Hermetic DIP (Z)
75°C
6.7mW'oC
8-Pln Plastic DIP (P)
35°C
5.6mW'oC
2. Absolute maximum ratlngaapplyto both packaged parlsand DICE, unless
otherwisa noted.
3. For supply voltages less Ihan ±15V, Ihe maximum Input vollage Is the
supply voltage.
= 25·C, unless otherwise noted.
OP-01
OP-01H
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
RsS20kO
Input Ollsal Current
los
Input Bias Currant
Is
Input Voltage Range
IVR
Common-Mode
Rejection Ratio
CMRR
VCM =±10V
RsS 20kO
PSRR
Vs = ±5V to ±20V
RsS 20kO
Output Voltage Swing
Vo
RL ;;,5kO
RL;;'2kO
Large-Signal
Voltage Gal n
Avo
RL;;'2kO
Vo =±10V
Power Consumption
Power Supply
Rejection Ratio
MIN
TYP
MAX
0.3
MIN
~
TYP
MAX
UNITS
0.7
2.0
5.0
mV
0.5
2.0
2.0
20
nA
18
30
25
100
nA
±12
±13
±12
±13
V
85
110
80
100
dB
10
100
60
150
I'VN
±12.5
±12.0
±13.5
±13.0
±12.5
±12.0
±13.5
±13.0
V
50
100
25
75
VlmV
Pd
VOUT=O
50
90
50
90
mW
Settling Time
to 0.1% (Summing
Node Error)
ts
Av =-1
(Notes 1, 2)
VIN =5V
0.7
1.0
0.7
1.0
I'S
Slew Rate
(Notes 2, 3)
SR
Av =-I,
Rs =3k to 5kO
12
18
12
18
VII's
Large-Signal
Bandwidth
(Notes 3, 4)
150
250
150
250
kHz
Smail-Signal
Bandwidth
(Notes 3, 4)
1.5
2.5
1.5
2.5
MHz
150
ns
Risatime
Ir
Overshoot
OS
Av =-l
VIN = 50mV
150
%
NOTES:
1. RL= 25kO; CL = 50pF. See Settling Time Test Circuil.
2. Sample tested.
3. See applications Information.
4. Guaranteed by design.
5-13
ffi
OP-01G
OP-01C
1/86, Rev. A
::l
~
~
~
-~
0
;;.I.l
ts
~ OP-01 INVERTING HIGH-SPEED OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs = ±15V, -55·C:5 TA:5 +125·C for OP-01, OP-01G and O·C:5 TA:5 +70·C for
OP-01 H, OP-01 C, unless otherwise noted.
OP-01
OP-01H
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs" 20kn
Input Offset Current
los
Input Bias Current
Is
Input Voltage Range
IVR
MIN
TYP
MAX
TYP
MAX
UNITS
0.4
1.0
3.0
6.0
mV
4
4
40
nA
50
50
200
nA
30
Common-Mode
Rejection Ratio
CMRR
VcM =±10V
Rs" 20kn
Power Supply
Rejection Ratio
PSRR
Vs = ±5V to ±20V
Rs" 20kn
Large-Signal
Voltage Gain
Avo
Output Voltage Swing
Vo
Offset Voltage
Drift (Note 1)
TCVos
RL~2kn
RL~5kn
RL~2kn
±13
±10
±13
V
85
110
80
100
dB
100
60
150
",VN
30
80
15
50
VlmV
±125
±12.0
±13.5
±13.0
±12.5
±120
±13.5
±13.0
V
2
Rs ,,5kn
MIN
±10
10
Vo =±10V
OP-01G
OP-01C
8
5
20
,..VloC
NOTE:
1. Sample tested.
5-14
1/86, Rev. A
----------l~ OP-01 INVERTING HIGH-SPEED OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
(125°C TESTED DICE AVAILABLE)
1.
2.
3.
4.
5.
8.
NULL
INVERTING INPUT
NON INVERTING INPUT
VNULL
OUTPUT
7. V+
For additional DICE information refer to
1986 Data Book, Section 2.
DIE SIZE 0.046 X 0.042 Inch, 1932 sq. mils
(1.17X 1.07 mm,1.25 sq. mm)
WAFER TEST LIMITS
at Vs= ±15V, TA=25°C for Op·01N, OP·01G and OP·01GR devices; T A =125°C for OP·01NT and
OP·01GT devices, unless otherwise noted.
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Input Offset Current
los
Input Bias Current
Ie
Input Voltage Range
IVR
OP-01NT
LIMIT
OP-01N
LIMIT
OP-01GT
LIMIT
OP-01G
LIMIT
OP-01GR
LIMIT
UNITS
1.0
0.7
3.0
2.0
5.0
mVMAX
Rs" 20kO
Common-Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
Output Voltage
Swing
VOM
RL " 5kO
RL" 2kO
Large-Signal
Voltage Gain
Avo
RL" 2kO
Vo =±10V
Power Consumption
Pd
VOUT=O
VcM =±10V
Rs" 20kO
Vs = ±5V to ±20V
Rs" 20kO
4
2
10
20
nAMAX
50
30
100
50
100
nAMAX
±10
±12
±10
±12
±12
VMIN
85
85
80
80
80
dBMIN
60
80
100
100
150
"VN MAX
±12.5
±12.0
±12.5
±12.0
±12.5
±12.0
±12.5
±12.0
±12.5
±120
VMIN
30
50
25
50
25
VlmV MIN
90
90
mWMAX
90
NOTES:
For 2S Q C characteristics of NT & GT devices, see N & G characteristics respectIVely
Electrical tests are performed at wafer probe to the limIts shown Due to vanatlons in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotIate specIfications based on dice lot qualification through sample lot assembly and testIng.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ± 15V, TA =
25° C, unless otherwise noted.
ALL GRADES
TYPICAL
UNITS
AVCL =-1. Rs =3kOt05kO
18
VI,..
V ,N = 5V
Av=-1
RL = 2kO (See Settling Time Test CirCUIt)
C L =50pF
1.0
"s
Large-Signal
Bandwidth
250
kHz
Smail-SIgnal
BandWIdth
2.5
MHz
Risetlme
150
ns
PARAMETER
SYMBOL CONDITIONS
Slew Rate
SR
Settling Time to
ts
0.1%
(Summing Node Error)
5-15
1/86, Rev. A
----------I!EMD
OP-01 INVERTING HIGH-SPEED OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
LARGE-SIGNAL
PULSE RESPONSE
SMALL-SIGNAL
PULSE RESPONSE
TIME (500ms!DIV)
Vs
e
±15V, AV
TIME (100ms/DIV)
=-1, AL .. 2kn. CL ,. 50pF
Vs "':t15V, AV '" -1, AL
UNITY-GAIN BANDWIDTH
V8 SOURCE RESISTANCE
I _I
1,
2.
3.
4.
6.
-2
r-
0'1
II
I
I
I
~
'm
3
R
~
w
• >;
";:!
~ 4
0
1\1
0,10
0
\
1\
6
1.00
10.0
FREQUENCY (MHz)
-,
III
2.
3.
4.
RS'" 10kO
INVERTING
•
AV;;;' 60
3. NON·
3
INVERTING
AV" 10
I
I
4. NON·
INVERTING
~
I
1\
1\
...l
0.10
\\
[
~O~;AGE
FOLLOWER)
2~)~
I
Y
o 111111111 111111111 II!I
o 111111111 111111111 1111
0.001 0,01
1, INVERTING
A V "-'
2 2. NON.
I
•
RS" 100.0
RS,. lkn
RS" 3.3kO I
1\.1 M
jI.,[
2
,.
'2
,
1r,
60
LARGE-SIGNAL OUTPUT
SWING V8 FREQUENCY
II
I
~
iii 8 0
l!
z
_'U
\
I
I
'00
I
......
-4
0.01
'20
II
1111
AS. 2,6kO
RS·6.0krl
RS" 10kn
RS" 33kG
RS. 100kn
Or--- 1"'\0{
OPEN-LOOP GAIN
V8 FREQUENCY
=2kn, CL .. 50pF
Ulill
1.00
10,0
100
1000 10,000
0,001
0.10
1.00
10,0
FREQUENCY (MHz)
PREQUENCY (kHz)
APPLICATIONS INFORMATION
0,01
FAST INVERTING AMPLIFIER
The OP-01 incorporates an internal feed-forward compensation network to provide fast slewing and settling times in all
inverting and mOderate-to-high-gain noninverting applications. Unity-gain bandwidth is a function of the total equivalent source resistance seen by the inverting terminal. Proper
choice of this resistance will allow the user to maxmlze
bandwidth while assuring proper stability. The equivalentinverting-terminal~resistance is defined as R'N II RF, and it
must be greater than 3.3kO to assure stability in all closedloop gain configurations including unity gain. Should
R,N" RF:5 3.3kO, a resistor (Rs) may be placed between the
inverting input and the sum node to provide the required
resistance. (See Fast Inverting Amplifier Diagram.) Lower
values of total equivalent resistance may be used to improve
bandwidth in higher closed-loop gain configurations, as
indicated by the Open-Loop Gain vs. Frequency plot.
Rp
Reo= RS+ RIN II RF
FOR AV = -1, Rea ;';'3.3kn
Rp = Rea
5-16
1/86, Rev. A
_ _ _ _ _ _ _ _~~ OP-01 INVERTING HIGH-SPEED OPERATIONAL AMPLIFIER
TYPICAL APPLICATIONS
SETTLING-TIME TEST CIRCUIT
Settling time may be measured using the circuit shown
below. This circuit Incorporates the "false sum node" technique to produce accurate, repeatable results. For a 5V Input
step, 0.1 % settling will be achieved when the false sum node
settles to within ±2.5mV of Its final value. The oscilloscope
used for observation of the false sum node should have wide
bandwidth, fast overload recovery time, and be used with a
low capacity probe (S 10pF, including strays). A Tektronix
7504 scope with a 7A 11 probe or equivalent Issuggested. The
pulse generator should have a 50n output impedance and be
capable of a 5V rise time in S 20ns with ringing less than
2.5mV after 0.5I's. Measurements to 0.1 % require RINto equal
RFwithin 0.01%; Rsand Reare used as trimming resistors to
achieve this matching.
VA TO SCOPE CIN - l0pF
rAS
INPUT
rAI
A7
&kll
..7kG
~
SOn:l:1%
aBOn±li%
E2
~
"',BV
1¥
24011
~
OUTPUT
Bkll
to.6%
A3
~
PRECISION POWER-BOOSTER CIRCUIT
AI
1&00:t:1%
A2
:1:0.8%
AS
LSB
TVPICAL SETTLING
TIME O.Bj.l1
~
AF - . ,
10kn A 10kO
to.I5%
:1:0.8%
Al
Msa
0-0- - - - - - - - - - ,
AIN - . ,
1aOOt'"
FAST VOLTAGE-OUTPUT D/A CONVERTER
O. '~F:I:'O%
""BV
7 ~
2W
o•.en
RL>
2kll
10kO
9
CL C;;
50pF
10ka
l&kll
VOUT
I
AL
4 O,1J.1F:t:1""
~
6
100n
20kll
0:-
0:-
-lav
2400
TYPICAL PERFORMANCE
OFFSET NULLING CIRCUIT
SLEW RATE--------------"" 18V/j.ls
01% SETTLING-------4J.1s (RL ·500n)
aUIESCENT SUPPLY CURRENT---15mA
v+
V-
5·17
1/86, Rev. A
~
f.I.l
~
OP-02
GENERAL-PURPOSE
OPERATIONAL AMPLIFIER
Precision Monolithics Inc.
c
FEATURES
guaranteed over the full operating temperature range.
Precision Monolithics' exclusive Silicon-Nitride "Triple
Passivation" process reduces "popcorn noise." A thermallysymmetrical input-stage design provides low input offset
voltage drift and insensitivity to output load conditions.
• Excellent DC Specifications
• Low Noise ............................. O.65/Np _p Typ
• Low Drift (TeVos) ........................ 81lVl" C Max
• Silicon-Nitride Passivation
• 125 0 C Tested Dice Available
• "Premium" 741 Replacement
The OP-02 is a direct replacement for the 741. It is ideal for
upgrading existing designs where accuracy improvements
are required and for eliminating special low-drift or low-noise
selected types.
ORDERING INFORMATIONj'
PACKAGE
TA = 25°C
VosMAX
(mV)
TO-99
a-PIN
HERMETIC
DIP
a-PIN
0.5
0.5
2.0
2.0
5.0
5.0
OP02AJ'
OP02EJ
OP02J'
OP02CJ
OP02BJ'
OP02DJ
OP02AZ'
OP02EZ
OP02Z'
OP02CZ
OP02BZ'
OP02DZ
* For devices processed
PIN CONNECTIONS
PLASTIC
DIP
a-PIN
OPERATING
TEMPERATURE
RANGE
OAfd,'NC'v.
MIL
COM
MIL
COM
MIL
COM
OP02EP
OP02CP
OP02DP
-IN 2
'.
+IN 3
bOUT
5 BAL
4 V- (CASel
TO-99
(J-Suffix)
total compliance to MIL-STO-883, Add 1883 after
part number. Consult factory for 883 data sheet
In
tAil commercial and Industnal temperature range parts /:Ire available with
burn-In. For orderrng Information see 1986 Data Book, Section 2
GENERAL DESCRIPTION
This high-performance general-purpose operational amplifier provides significant Improvements over industry-standard
and "premium" 741 types while maintaining pln-for-pin
compatibility, ease of application, and low cost Key specifications, such as Vos. los, lB. CMRR, PSRR, and Avo are
SIMPLIFIED SCHEMATIC
f --
THERMALLY CROSS CDUPLfD
QUAD U!:>, 05, Qfj AND U6'
COMPRISE. A SIMILAR THER
MALL YCROSS COlJPLEDOUAO
o---.,~-
EPOXY MINI-DIP
(P-Suffix)
---------------------'
-- .-.------ - - - - - - - _ . _ - - - - - - - - - - - - - - - - - - - - - - ,
"Q1, Q2, 03 AND Q4 FORM II
··IN
8-PIN HERMETIC DIP
(Z-Suffix)
~----
U8
_._-
--
-
~
r
09
- -__
----
- -----.-.-..:::-
OUT
Rll
5-18
1/86, Rev. A
-----------l~ OP-02 GENERAL-PURPOSE OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
(Note 2)
Supply Voltage ••••••••••••••••••••••••••••••••••• ±22V
NOTES:
1 See table for maximum ambient temperature rating and deratmg factor.
Power Dissipation (Note 1) ...................... 500mW
Differential I n put Voltage • • • • • • • • • • . • • • • • • . • • • • • • •• ± 30V
Input Voltage ......................... '" Supply Voltage
Output Short-Circuit Duration •••••••••••..•.•• Indefinite
PACKAGE TYPE
Operating Temperature Range
OP-02A, OP-02, OP-02B
••••••••••••.
-55°C to +125°C
OP-02E, OP-02C, OP-02D •••••••••••••••• O°C to +70°C
Storage Temperature Range •••••••••••
-65°C to +150°C
at Vs
7.1mW/'C
TO-99 (JI
ao'c
36'C
56mW/'C
8-Pln Hermetic DIP (ZI
75'C
6.7mW/'C
Absolute maximum ratings apply to both packaged parts and DICE. unless
otherwise noted.
= ±15V, TA = 25°C, unless otherwise noted.
OP-02A
OP-02E
PARAMETER
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
a-Pm PlastiC DIP (PI
Lead Temperature (Soldering, 60 sec) ••.•••••••••• 300°C
DICE Junction Temperature (Tj ) •.••••• -65°C to +150°C
ELECTRICAL CHARACTERISTICS
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs" 20kO
Input Offset Current
los
0.5
Input Bias Current
Is
18
Input ResistanceDifferential-Mode
R'N
(Note21
MIN
OP-02
OP-02C
TYP
MAX
0.3
0.5
MIN
TYP
20
30
OP-02B
OP-02D
MAX
MIN
TYP
MAX
UNITS
3
5
mV
5
5
25
nA
50
30
100
nA
34
5.7
2.0
5.2
±10
±13
±10
±13
±10
±13
V
85
100
80
95
70
85
dB
3.5
MO
Input Voltage Range
IVR
Common-Mode
Rejection Ratio
CMRR
VCM = ±10V
Rs" 20kO
Power Supply
Rejection Ratio
PSRR
Vs = ±5 to ±20V
Rs" 20kO
Output Voltage Swing
Vo
RLe: 2kO
±12
±13
±12
±13
±12
±13
V
Large-Signal
Voltage Gain
Avo
RLe: 2kO
Vo =±10V
100
250
50
200
25
150
VlmV
Power Consumption
Pd
Vo=OV
Input Noise Voltage
8 np _p
O.IHz to 10Hz
Input Noise
Voltage Density
en
fo= 10Hz
fo= 100Hz
fo= 1000Hz
Input Noise Current
i np _p
0.1 Hz to 10Hz
Input NOise
Current Density
'n
fo= 10Hz
fo= 100Hz
fo= 1000Hz
Slew Rate
SR
Large-Signal
Bandwidth
(Note 11
Vo= 20Vp _p
(Note 11
Closed-Loop
Bandwidth
BW
Rlsetlme
tr
Overshoot
as
AVCL = +1
(Note 31
AVCL =+1
Y,N = 50mV (Note 11
10
40
30
60
70
50
100
100
50
90
150
90
IfoVIV
mW
0.65
0.65
0.65
IfoVp_p
25
22
21
25
22
21
25
22
21
nVl$.
12.8
12.8
12.8
pA p
1.4
0.7
0.4
14
07
0.4
1.4
0.7
0.4
pAl$.
0.25
0.5
4
0.5
0.25
0.5
VII's
8
8
4
8
kHz
1.3
1.3
13
MHz
200
0.25
e-
350
10
(Note 11
200
350
10
200
350
ns
10
%
NOTES:
1. Sample tested.
2. Guaranteed by input bias current.
3. Guaranteed by risetlme.
5-19
1/86, Rev. A
~
~
.....
>-LI
::sp..
~
~
0
.....
~
~
0
IfMD
OP-02 GENERAL-PURPOSE OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS
at Vs = ± 15V, -55' C :5 TA:5 + 125' C, unless otherwise noted.
OP-02A
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
RsS 20kn
TCVos
Rs =50n
Average Input Offset
Voltage Drift (Note 1)
Input Offset Current
los
Average Input Offset
Current Drift (Note 1)
TClos
Input Bias Current
Ie
Input Voltage Range
IVR
Common-Mode
Rejection Ratio
CMRR
VCM=±10V
RsS 20kn
Power Supply
Rejection Ratio
PSRR
Vs = ±5 to ±20V
RsS 20kn
Large-Signal
Voltage Gain
Avo
Output Voltage Swing
Vo
RL~2kn
Vo=±10V
RL~2kn
MIN
TYP
OP-02
MAX
MIN
MAX
TYP
MAX
UNITS
1.4
3
3
6
mV
8
4
10
8
20
p'vrc
5
2
10
5
50
nA
7.5
75
15
150
30
300
pArC
30
60
40
100
50
200
nA
0.5
2
±13
±10
±13
±10
±13
V
80
95
80
95
70
85
dB
10
30
60
Input Offset Voltage
Vos
Rs S20kn
Average Input Offset
Voltage Drift (Note 1)
TCVos
Rs= 50n
Input Offset Current
Average Input Offset
Current Drift (Note 1)
100
100
150
p.VIV
50
100
25
60
25
60
VlmV
±12
±13
±12
±13
±10
±13
V
unless otherwise noted.
OP-02E
SYMBOL CONDITIONS
MIN
±10
ELECTRICAL CHARACTERISTICS at VS= ±15V, O'C:5 TA:5 +70'C,
PARAMETER
OP-02B
TYP
MIN
TYP
OP-02C
MAX
MIN
0.4
OP-02D
TYP
MAX
TYP
MAX
UNITS
1.2
3
3
6
mV
MIN
2
8
4
10
8
20
p'vrc
los
0.7
4
1.4
10
5
60
nA
TClos
7.5
120
15
250
70
500
pA/'C
Input Bias Current
Ie
22
50
25
100
50
200
nA
Input Voltage Range
IVR
Common-Mode
Rejection Ratio
CMRR
VCM = ±10V
RsS20kn
Power Supply
Rejection Ratio
PSRR
Vs = ±5 to ±20V
RsS20kn
large-Signal
Voltage Gain
Avo
Output Voltage Swing
Vo
RL~2kn
Vo =±10V
RL~2kn
±10
±13
±10
±13
±10
±13
V
60
100
80
90
70
85
dB
10
30
60
100
100
150
p.VIV
50
100
25
60
15
25
VImV
±12
±13
±12
±13
±10
±13
V
NOTE:
1. Sample tested.
5-20
1/86, Rev. A
-----------l~ OP-02 GENERAL-PURPOSE OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS (125°C TESTED DICE AVAILABLE)
1.
2.
3.
4.
5.
6.
NULL
INYERTING INPUT
NONINYERTING INPUT
YNULL
OUTPUT
7. Y+
DIE SIZE 0.046 X 0.042 Inch, 1932 sq. mils
(1.17 X 1.07 mm, 1.25 sq. mm)
WAFER TEST LIMITS at Vs = ± 15V, TA = 25° C for
OP-02GT devices, unless otherwise noted.
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Input Offset Current
los
Input Bias Current
I.
Input Voltage Range
IVR
Common-Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
Output Voltage Swing
For additional DICE information refer to
1986 Data Book, Section 2.
OP-02N, OP-02G
and
OP-02GR
devices;
TA
= 125° C for OP-02NT and
OP-02NT
OP-02N
OP-02GT
OP-02G
OP-02GR
LIMIT
LIMIT
LIMIT
LIMIT
LIMIT
0.5
3
RsS 20kO
UNITS
mVMAX
3
25
nAMAX
50
30
60
50
200
nAMAX
±13
±13
±13
±13
±13
VMIN
VCM = ±10V
RsS 20kO
80
85
80
80
70
dBMIN
PSRR
Vs = ±5V to ±20V
RsS 20kO
60
60
100
100
150
I'V/v MAX
±12
±12
±12
±12
±12
VMIN
50
100
25
50
25
VimV MIN
90
90
mWMAX
Vo
RL" 2kO
Large-Signal
Voltage Gain
Avo
RL" 2kO
Vo= ±10V
Power Consumption
Pd
Vo=OV
90
NOTE:
For 25°C characteristics of NT and GT devices, see Nand G characteristics, respectively.
Electrical tests are performed at wafer probe to the limits shown. Due to variations In assembly methods and normal yield loss, yield after packaging Is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS at
PARAMETER
SYMBOL
Input Resistance
Differential-Mode
RIN
Input Noise Voltage
enp •p
0.1 Hz to 10Hz
Input Noise
Voltage Density
en
fo= 10Hz
fo= 100Hz
fo= 1000Hz
Input Noise Current
I np _p
0.1 Hz to 10Hz
Input Noise
Cu rrent Density
in
fo= 10Hz
fO = 100Hz
fo= 1000Hz
Slew Rate
SR
Large-Signal
Bandwidth
Vs
= ±15V, TA = 25° C, unless otherwise noted.
CONDITIONS
OP-02NT
OP-02N
OP-02GT
OP-02G
OP-02GR
TYPICAL
TYPICAL
TYPICAL
UNITS
5.7
5.2
3.5
MO
0.65
0.65
0.65
I'Vp.p
25
22
21
25
22
21
25
22
21
nViVHz
12.8
12.8
12.8
pA p_p
1.4
0.7
0.4
1.4
0.7
0.4
1.4
0.7
0.4
pAlVHz
0.5
0.5
0.5
ViI's
Vo= 20Vp_p
8
kHz
Closed-Loop
Bandwidth
BW
AVCL = +1
1.3
1.3
1.3
MHz
Risetime
tr
Av=+1
VIN = 50mV
200
200
200
ns
Overshoot
OS
15
15
15
%
8
I'V/oC
30
pAlOC
Average Input Offset
Voltage Drift
Average Input Offset
Cu rrent Drift
TCVos
Rs= 5000
(Note 1)
7.5
TClos
5-21
15
1/86, Rev_ A
f&......
....
::sp..
~
~
0
......
~
~
0
------------IIEM!) OP-02 GENERAL-PURPOSE OPERATIONAL AMPLIFIER
BURN-IN CIRCUIT
OFFSET NULLING CIRCUIT
~
+20V
-----2N7
•
OP·02
'V·
-20V
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT SPOT NOISE
VOLTAGE VI FREQUENCY
INPUT WIDEBAND NOISE VI
BANDWIDTH (0.1 Hz TO
FREQUENCY INDICATED)
INPUT SPOT NOISE
CURRENT VI FREQUENCY
1000
10
100
Vs = 115V
TA "2SOC
RS son
Imlll
Vs -
~
.tl~~~
r-
TA=2SoC
Vs .t15V
TA"'+25"C
TYPICAL
V
TYPICAL
1.0
1
1.0
10
100
1000
0.01
0.10
FREQUENCY 1Hz)
10
~
1000
TA
25"e ~
f=
.-
....... ,.......
10
i
2'00
S!
~
Ii:
i
'/
Ii
1.0
a:
~
0.1
o
0.1
100
10
POWER CONSUMPTION
VI POWER SUPPLY
100
. / NEGATIVE SWING
10
1.0
BANDWIDTH (kHz)
VI TEMPER~TURE
= :t:15V
12
1000
100
DIFFERENTIAL
INPUT RESISTANCE
~OS'~'~E ~,~~
~ 25"le
V;
T
14
1.0
FREQUENCY (Hz)
OUTPUT VOLTAGE VI
LOAD RESISTANCE
,.
O. 1
0.1
0.1
0.10
0.01
1.0
LOAD RESISTANCE TO GROUND (kO)
10
-60
-20
+20
+60
TEMPERATURE (eC)
5-22
+100
+140
10
/
1.0
20
40
60
TOTAL SUPPLY VOLTAGE, V+ TO V- (VOL TSI
1/86, Rev. A
-------------l!rHD
OP-02 GENERAL-PURPOSE OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
POWER CONSUMPTION
vs TEMPERATURE
35
50
Vs;c ±15V
I
\
OPEN-LOOP GAIN
vs TEMPERATURE
OUTPUT SHORT·CIRCUIT
CURRENT vs TIME
1
I
OP 02A
I-- f--(D VIN(PIN 3) =-
30
t- t--.
TA.+d~Gl
is'
"Iv
300
r--
-10mV, Vo" +15V VO" -15V
® VIN(PIN 3}" +10mV,
45
- -- -- ---r--._._-t--
\
-
._--'-----
.-
1\
1\\
25
~p OZE,C
I'.....
I-- -
.-
20
--- I--I--
+ 20
-20
+60
+140
+100
I-- -
175
--
2
....0
-20
INPUT OFFSET CURRENT
vs TEMPERATURE
+140
10
60
OP 02
l - I--
100
20
'\
1,5
075
-
10
OP 02A
050
e:..-'-
OP 02E
'"
..........
50
'\
"-...
05
I--
o
-20
+20
+60
+100
+140
40
'" U::t-N~~r
I'<
025
30
"
QP.02
" ".........
20
r-.....
+20
-20
-60
OP 02C
+60
+100
OPEN-LOOP GAIN vs
POWER SUPPLY VOLTAGE
TA-
1
25'C
=
10kH
110
t---.
~p\~~~\~ ~p\~;~\\
J
-60
-20
~P~\2\~\~P~
100
90
1
80
:
200
I--- ~
=
!
110
I
60
50
±5
±10
t:15
POWER SUPPLY (VOLTS)
,20
Ii
!
"
I
I
100
lk
5-23
+140
1IIIIInttt
olW~~I
10k
100k
'I
\
I
I
\
I
100
I,
I
\
I
10
lk
!Ii
"!ili'
i \
I
"
' ~I
I
I
\
70
50
lilil:!
T';'~ 25"C!~1
80
60
II
FREQUENCY (Hz)
+100
lill
~pl~~~I~ dp'~~;11
I
I
10
100
90
70
I
Opl:'AL
-
+60
PSRR vs FREQUENCY
120
±lSV
I
100
+20
TEMPERATURE (OC)
t~~I~~!cl
Vs
r-
OP-02E
+140
~P~2-
I--
o
CMRR vs FREQUENCY
120
OP 02e
.........
..........
10
TEMPERATURE (OC)
RL
+100
INPUT BIAS CURRENT
VB TEMPERATURE
25
OP 02e -
-
+60
+20
TEMPERATURE ('C)
50H
125
300
'\.
~15V
150 - R S
-60
\
50
,
o
UNTRIMMED OFFSET VOLTAGE
vs TEMPERATURE
:'\.
--
- I - I--
TIME FROM OUTPUT BEING SHORTED (MINUTES)
TEMPERATURE (OC)
i= Vs
r-
r--- -
1"( ..........
1"-
/'
/
. -I - -
"'-...
15
35
-60
-
\ [\.
40
V~' ';5V
"",
10k
I
"!I i
lOOk
FREQUENCY (Hz)
1/86, Rev. A
------------1~ OP·02 GENERAL·PURPOSE OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
MAXIMUM UNDISTORTED
OUTPUT VI FREQUENCY
~llIIJ!lc
VS=:l:15V
1\
,, iii 'ITTJ
I
j
1\
III
- r-.
80
'00
'\
TA·I
'\
i
II
'\
'\
: i;
10
100
FREQUENCY (kHz)
"'"
'\
III!
-40
'000
TA.2!OC
VS-:t16V -
80
vs·.,sv -
'\
11\1
25'6
II
III
,
11::1
'I
\
o
'20
I
CLOSED·LOOP RESPONSE
FOR VARIOUS GAIN
CONFIGURATIONS
OPEN·LOOP
FREQUENCY RESPONSE
""\
"'
-20
0.1
1.0
10
100
1k
10k 'OOk
FREQUENCY 1Hz!
1M
10M
10
100
1k
10k
lOOk
1M
10M
FREaUENCV (Hz)
TYPICAL APPLICATIONS
HIGH-8TABILITY VOLTAGE REFERENCE
'mA
A3
A2
6,4M2
+15V
>'::"""--+-"-j- - - 0 VOUT· +'ov
2mA
paR R2· 3.6kH AND
A3·6.4kB,
Vour· 1.5826V Z
A'
IF V
1.SkO
L-_ _ _ _ _ _ _
~
z
OR
6.4V, THEN
Vour" +10V
Vz
B.4V
ABSOLUTE VALUE CIRCUIT
A3
'Okll
A.
10kn
A5
DESIGN EQUATIONS
10ka
POSITIVE INPUT
D'
FD3333
1.
VA" 0, 02 OFF, D1 ON
2.
EO.(-E~N,R3).(1f)"EIN~
3. With R1 .. R3
EIN
R1
= R4"
R6: EO" EIN
4. Vas error Included: EO" EIN + 2Vos
10kn
D2
F03333
RZ
10kn
NEGATIVE INPUT
1. 01 OFF, 02 ON
2.
-~I,N.~ + R3 ~~4
3,
EO·VA
4,
With R3 .. R4" AS: EO" 1.5VA
_(R2~~R(~; ~~3(!·6~4~IN
5,
EO"
6.
With R1 .. R2 .. R3 .. R4: EO" -EIN
7.
VOS error Included:
EO" -EIN + 1.6VOS2 - O.5VOS1
For both Inputs: EO = + IEINI
8.
5·24
(1+R32~4)
1/86, Rev. A
-----------I~ OP·02 GENERAL·PURPOSE OPERATIONAL AMPLIFIER
TYPICAL APPLICATIONS
DAC·08 OUTPUT AMPLIFIER
INPUT/OUTPUT TABLE
B1 B2 B3 B4 B5 BI B7 B8 10mA
6,DDOkO
CAe·os
6,OkO
1.992
FULL-SCALE
-2 LSB
1.964 -9.920
HALF-SCALE
HSB
0
HALF-SCALE
0
0
0
0
0
0
HALF-SCALE
-LSB
FOR COMPl.EMENTARY OUTPUT (OPERATION ASA NEGATIVE
l.OGIC DAe) CONNECT NON.INVERTING INPUT OF OP·AMP TO
TO (PIN 2), CONNECT 10 (PIN 4) TO GROUND.
EO
FULL·SCALE
-1 LSB
ZERO-SCALE
HSB
ZERO-SCALE
0
0
0
0
0
0
0
0
-9.960
1.008
-5.040
1.000
-5.000
0.992
-4.960
0.0008 -0.040
0
0
0.000
0.000
~
~
tt:
e2
~
g~
~
~
()
5·25
1/86, Rev. A
OP-04/0P-14
DUAL MATCHED HIGH-PERFORMANCE
OPERATIONAL AMPLIFIERS
Precision Monolithics Inc.
FEATURES
•
•
•
•
•
•
•
•
•
•
pin-for-pin compatibility, ease of application, and low cost.
Key speCifications, such as Vos, los, Ie, CMRR, PSRR and
Avo, are guaranteed over the full operating temperature
range. Precision Monolithics' exclusive Silicon-Nitride "Triple
Passivation" process reduces "popcorn noise". A thermallysymmetrical input stage design provides low TCVos, TClos,
and insensitivity to output load conditions. This series is ideal
for upgrading existing designs where accuracy improvements are desired. For more stringent requirements, refer to
the OP-207, OP-220, or OP-221 dual-matched operational
amplifier data sheets.
Excellent DC Input Specifications
Matched Vos and CMRR
OP-14 Fits Standard 1458/1558 Sockets
Internally Compensated
Low Noise
Low Drift
Low Cost
00 CI +70 0 C and -55 0 CI +125 0 C Models
SIlicon-Nitride Passivation
Models with MIL-STD-883 Class B Processing
Available From Stock
PIN CONNECTIONS
ORDERING INFORMATIONt
PACKAGE
TA ~ 25' C -:;::;::-;:::-=~H;;:E:::R,;,;,M;.:E,;,;,T;,,:IC~=_ _..;P:..;L::.:A:;;S:;.T:.:IC:.., OPERATING
vos
TO-99 TO-l00
DIP
DIP
TEMPERATURE
(mV)
0.75
0.75
20
2.0
5.0
50
a-PIN
l0-PIN
a-PIN
l4-PIN
8-PIN
OP14AJ'OP04AK' OP14AZ' OP04AY'
OP14EJ
OP14EZ OP04EY OP14EP
OP14J' OP04K' OP14Z' OP04Y'
OP14CJ OP04CK OP14CZ OP04CY OP14CP
OP14BJ'OP04BK' OP14BZ' OP04BY'
OP140J
OP14DZ OP040Y OP140P
RANGE
MIL
COM
MIL
COM
MIL
COM
-IN (A)
1
+IN (A)
2
SAL (A)
3
SAL (8)
5
-IN (8)
7
B
BAL (B)
8-PIN HERMETIC DIP
(Z-Sufflx) OP-14
"
14-PIN HERMETIC DIP
(Y-Sufflx)
OP-04
EPOXY MINI-DIP
(P-Sufflx) OP-14
OUT
v+
I~A1
9 OUT IBI
(A) 2
8 V+ (8)
A
-IN (A) 3
B
-+
-
v+
8
10 N.C.
'For devices processed In total compliance to MIL-STO-883, add /883 after
part number. Consult factory for 883 data sheet.
t All commercial and industnal temperature range parts are available With
burn~ln. For ordering information see 1986 Data Book, Section 2.
OUT
IAI~+
7 OUT IBI
-IN (A) 2
6 -IN (8)
7 -IN (8)
+IN (A) 3
+IN (A) 4
GENERAL DESCRIPTION
The OP-04/0P-14 series of dual general-purpose operational
amplifiers provides significant improvements over industrystandard 747 and 1458/1558 (OP-14) types while maintaining
S
v-
5 +IN (B)
6 +IN (8)
4
TO-100 (K-Sufflx)
OP-04
v-
TO-99 (J-Sufflx)
OP-14
SIMPLIFIED SCHEMATIC (Each Amplifier)
"01,02,03 AND 04 FORM A
THERMALLY CROSS·COUPLEO
OUAD 05,05 1,06 AND 06 1
COMPRISE A SIMILAR
THERMALLY CROSS·COUPLED
OUAD
-IN
o--------t:====---,
+IN
.9~
R1
RB
R3
BALANCE
BALANCE ACCESSIBLE WITH OP·04 IN 14·PIN HERMETIC DIP ONLY
5-26
1/86, Rev, A
--------1~
OP-04/0P-14 DUAL MATCHED HIGH-PERFORMANCE OPERATIONAL AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS
(Note 2)
Supply Voltage ................................... ±22V
Internal Power Dissipation (Note 1) ••....•...••.. 500mW
Differential Input Voltage .......................... ±30V
Input Voltage .•••••••...••..........•.••• Supply Voltage
Output Short-Circuit Duration ••••••.•.••••.••• Indefinite
Storage Temperature Range
J, K, Y, and Z Packages •.•••.•.••••. -65°C to +150°C
P Package ••••.•...•••••••••••••••. -65°C to +125°C
Lead Temperature Range (Soldering, 60 sec) •••••• 300°C
Operating Temperature Range
A, Plain, B-Suffix ................... -55°C to +125°C
E, C, D-Suffix .......................... O°C to +70°C
DICE Junction Temperature (Tj) •.•.••. -65°C to +150°C
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
14-Pin Hermetic DIP (Y)
OP-04
NOTES:
100'C
10.0mW/·C
TO-100 (K)
OP-04
80'C
71mWrC
TO-99 (J) OP-14
80'C
7.1mW/·C
8-Pin Hermetic DIP (Z)
OP-14
75'C
6.7mWrC
8-Pin Plastic DIP (P)
OP-14
36'C
5.6mW/·C
2.
1. See table for maximum ambient temperature rating and derating factor
MATCHING CHARACTERISTICS
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
Absolute maximum ratings apply to both packaged parts and DICE, unless
otherwise noted.
~
i-J-l
at Vs = ± 15V, TA = 25° C, unless otherwise noted.
I-<
J;..I.;
OP-04A OP-04E
OP-14A OP-14E
TYP
MIN
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Match
t;,Vos
Rs:S 20kn
Common-Mode Rejection
Aatio Match
t;,CMRR
VcM =±10V, As:S 100n
1--4
OP-040P-04C
OP-140P-14C
MAX
MIN
TYP
~
~
MAX
UNITS
0.3
94
mV
106
94
106
dB
OP-04A OP-04E
OP-14A OP-14E
SYMBOL
CONDITIONS
Input Offset Voltage
Match
t;,Vos
Rs :S20kn
Common-Mode Aejection
Ratio Match
t;,CMAA
VCM = ±10V, As:S 100n
MIN
90
ELECTRICAL CHARACTERISTICS (Each Amplifier)
~
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
As :S20kn
Input Offset Current
los
0.5
Input Bias Current
I.
18
Input Resistance -
Differential-Mode
R'N
Input Voltage Range
IVA
(Note 3)
CMRA
VCM =±10V
As:S 20kn
Power Supply
Aejection Aatio
PSAA
Vs = ±5V to ±20V
As:S 20kn
Output Voltage Swing
Vo
ALe: 2kn
Common-Mode
Aejection Aatio
MIN
TYP
MAX
05
1.5
i-J-l
()
OP-04 OP-04C
OP-140P-14C
MIN
100
90
TYP
MAX
UNITS
15
mV
100
dB
at Vs = ± 15V, TA = 25° C, unless otherwise noted.
OP-04A10P-14A
PARAMETER
TYP
MAX
0.3
075
OP-04/0P-14
MIN
50
TYP
20
OP-04B/OP-14B
MAX
MIN
75
TYP
MAX
UNITS
3
5
mV
25
nA
100
nA
30
135
2.0
7.5
±10
±13
±10
±13
±10
±13
V
85
100
80
95
70
85
dB
60
10
±12
~
0
1--4
MATCHING CHARACTERISTICS at Vs= ±15V, -55°C::5 T A ::5 +125°C for OP-04A, OP-14A, OP-04 and OP-14,
O°C::5 TA::5 70°C for OP-04E, OP-14E, OP-04C and OP-14C, unless otherwise noted.
PARAMETER
~
30
±12
±13
5-27
Mn
±13
100
100
±12
±13
150
~VIV
V
1/86, Rev. A
~ OP-04/0P-14 DUAL MATCHED HIGH-PERFORMANCE OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS (Each Amplifier)
at Vs
= ±15V. TA = 25°C. unless otherwise noted. (Continued)
OP-04A10P-14A
PARAMETER
SYMBOL
CONDITIONS
Large-Signal
Voltage Gam
Ava
RL2: 2kO
Va = ±10V
Power Consumption
INote2)
Pd
Vo=OV
Input Noise Voltage
ene-e
0.1 Hz to 10Hz
Input Noise Voltage
Density
en
10= 10Hz
10 = 100Hz
10 = 1000Hz
Input Noise Current
i ne-e
0.1 Hz to 10Hz
Input Noise Current
Density
in
10= 10Hz
10 = 100Hz
10= 1000Hz
Channel Separation
CS
Slew Rate I Note 1 )
MIN
TYP
100
250
MAX
50
50
SR
Av=+1, V,N=50mV p_p
RL = 2kO, C L = 50pF
12.8
12.8
pAe-~
1.4
0.7
0.4
1.4
0.7
0.4
1.4
0.7
0.4
pAiy'HZ
100
260
0.25
1.0
350
CONDITIONS
Input Offset Voltage
Vas
RsS 20kO
Average Input Offset
Voltage Drift I Note 1)
TCVos
Rs= 500
80
0.5
0.25
8
4
1.3
1.0
260
at Vs
MIN
los
TClos
Input Bias Current
Ie
Input Voltage Range
IVR
Common-Mode
Rejection Ratio
CMRR
VcM =±10V
Rs S20kO
Power Supply
Rejection Ratio
PSRR
Vs = ±5V to ±20V
RsS 20kO
Large-Signal
Voltage Gain
Ava
RL2: 2kO
Vo =±10V
Output Voltage Swing
Vo
RL2: 2kO
0.5
VII's
kHz
1.3
MHz
260
350
ns
10
5
10
%
= ±15V. -55° C:5 TA:5 +125° C. unless otherwise noted.
TYP
MAX
0.4
1.5
OP-04/0P-14
MIN
7.5
120
30
60
OP-04B/OP-14B
TYP
MAX
1.2
3
4
10
8
20
I'V/oC
10
10
50
nA
15
250
70
500
pA/oC
40
100
50
200
nA
10
Input Offset Current
Average Input Olfset
Current Drift INote 1)
dB
350
10
OP-04A10P-14A
SYMBOL
mW
12.8
ELECTRICAL CHARACTERISTICS'(Each Amplifier)
PARAMETER
90
nVly'HZ
1.3
OS
50
I'V~.~
1.0
Overshoot I Note 1)
90
V/mV
25
22
21
8
Av = +1. V'N = 50mV Pop
RL = 2kO. C L = 50pF
200
UNITS
0.65
4
tr
25
MAX
25
22
21
Va = 20V p_p
Rlsetime (Note 1)
TYP
0.65
0.5
AVCL = +1.0
200
MIN
25
22
21
0.25
BW
OP-04B/OP-14B
MAX
0.65
RL = 2kO.
C L = 100pF
Closed-Loop
Bandwidth INote 4)
TYP
50
90
100
Large-Signal
Bandwidth INote 1)
OP-04/0P-14
MIN
MIN
TYP
MAX
UNITS
mV
±10
±13
±10
±13
±10
±13
V
80
100
80
95
70
85
dB
10
30
60
100
100
150
J.lVIV
50
100
25
60
25
60
V/mV
±12
±13
±12
±13
±10
±13
V
NOTES:
1. Sample tested.
2. Power dissipation per amplifier.
3 Guaranteed by input bias current
4. Guaranteed by maximum rJsetlme.
5-28
1/86, Rev. A
~ OP-04/0P-14 DUAL MATCHED HIGH-PERFORMANCE OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS (Each Amplifier) at Vs = ±15V, TA = 25° C, unless otherwise noted.
OP-04E/OP-14E
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs" 20kO
Input Offset Current
los
Input Bias Current
Ie
Input ResistanceDifferential-Mode
R'N
Input Voltage Range
IVR
Common-Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
Output Voltage Swing
MIN
TYP
MAX
0.3
0.75
OP-04C/OP-14C
MIN
TYP
MAX
OP-04D/OP-14D
MIN
TYP
(Note 3)
VCM =±10V
Rs" 20kO
UNITS
mV
0.5
18
MAX
50
20
75
30
25
nA
100
nA
2.0
7.5
±10
±13
±10
±13
±10
±13
V
85
100
80
95
70
85
dB
Vs = ±5V to ±20V
1.35
10
Rs" 20kO
MO
30
60
100
100
150
!'V/v
Vo
RL ", 2kO
±12
±13
±12
±13
±12
±13
V
Large-Signal
Voltage Gal n
Avo
R L ", 2kO
Vo =±10V
100
250
50
200
25
150
V/mV
Power Consumption
(Note 2)
Pd
Vo=OV
Input Noise Voltage
en~e
0.1 Hz to 10Hz
Input Noise Voltage
Density
en
fo= 10Hz
fo = 100Hz
fo= 1000Hz
Input Noise Current
Ine' e
0.1 Hz to 10Hz
Input Noise Current
Density
In
fo= 10Hz
fo= 100Hz
fo= 1000Hz
Channel Separation
CS
Slew Rate (Note 1)
SR
Large-Signal
Bandwidth (Note 1 )
,......
50
90
Vo= 20Vp_p
0.25
50
50
90
mW
0.65
!,Ve-e
25
22
21
25
22
21
25
22
21
nV/v"HZ
12.8
12.8
12.8
pA e' e
1.4
0.7
0.4
1.4
0.7
0.4
1.4
0.7
0.4
pA/v"HZ
100
0.5
0.25
Closed-Loop
Bandwidth (Note 4)
BW
AVCL = +1
Risetime (Note 1)
t,
Av = +1, V,N = 50mV
RL = 2kO, C L = 50pF
260
350
Overshoot (Note 1)
OS
Av= +1, V,N = 50mV
RL = 2kO, C L = 50pF
5
10
1.3
08
80
0.5
0.25
8
4
13
0.8
260
350
10
dB
0.5
V/!'s
kHz
1.3
260
MHz
350
ns
10
%
NOTES:
1. Sample tested.
2. Power dissipation per amplifier.
3. Guaranteed by input bias current.
4. Guaranteed by maximum risetime.
5-29
~
::s
~
~
0.65
4
0.8
90
0.65
100
RL = 2kO, CL= 100pF
~
~
1/86, Rev. A
~0
,......
~
~
--------l~ OP-04/0P-14 DUAL MATCHED HIGH-PERFORMANCE OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS (Each Amplifier) at Vs = ±15V, 0° C :5 TA:5 +70° C, unless otherwise noted.
OP-04E/OP-14E
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
RsS20kO
Average Input Offset
Voltage Drift (Note 1)
TCVos
Rs= 500
Input Offset Current
los
Average Input Offset
Current Drift (Note 1)
MIN
TYP
MAX
0.4
OP-04C/OP-14C
MIN
OP-04D/OP-14D
TYP
MAX
TYP
MAX
UNITS
1.5
1.2
3
3
6
mV
8
4
10
8
20
p.V/oC
10
2
10
10
50
nA
MIN
TClos
7.5
120
15
250
70
500
pA/oC
Input Bias Current
19
30
60
40
100
50
200
nA
Input Voltage Range
IVR
Common-Mode
CMRR
VCM =±10V
RsS 20kO
Power Supply
Rejection Ratto
PSRR
Vs = ±5V to ±20V
RsS 20kO
Large-Signal
Voltage Gain
Ava
Rejection Ratio
Output Voltage Swing
RL~
2kO
Vo= ±10V
RL~
Va
2kO
±10
±13
±10
±13
±10
±13
V
80
100
80
95
70
85
dB
10
50
±12
30
60
100
100
150
p.VN
100
25
60
15
25
VlmV
±13
±12
±13
±10
±13
V
NOTES:
1. Sample tested.
2. Power dissipation per amplifier.
3. Guaranteed by design.
BURN-IN CIRCUIT (1/2 of OP-04, OP-14)
OFFSET ADJUST CIRCUIT
V+
V+
+20V
-
~
~
-20V
vPIN NUMBERS ARE FOR "Y" PACKAGE ONLY
5-30
1/86, Rev. A
_ _ _ _ _-;~ OP-04/0P-14 DUAL MATCHED HIGH-PERFORMANCE OPERATIONAL AMPLIFIERS
DICE CHARACTERISTICS
OP-14
OP-04
DIE SIZE 0.080 x 0.050 Inch, 4000 sq. mils
(2.03 x 1.27 mm, 2.58 sq. mm)
For additional DICE information refer to
1986 Data Book, Section 2.
1. INVERTING INPUT (A)
2. NONINVERTING INPUT (A)
8.
9.
10.
11.
12.
13.
14.
3. BALANCE (A)
4. V5. BALANCE (B)
6. NONINVERTING INPUT (B)
7. INVERTING INPUT (B)
BALANCE (B)
V+
OUTPUT (B)
V+
OUTPUT (A)
V+
BALANCE (A)
1. INVERTING INPUT (A)
2. NON INVERTING INPUT (A)
3. BALANCE (A)
4. V5. BALANCE (B)
6. NON INVERTING INPUT (B)
7. INVERTING INPUT (B)
8. BALANCE (B)
9. V+(B)
10. OUTPUT (B)
11. NO CONNECTIONS
12. OUTPUT (A)
13. V+(A)
14. BALANCE (A)
NOTE: 9. 11 and 13 are Internally connected.
WAFER TEST LIMITS at Vs
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs$ 20kO
Input Offset Voltage
Match
tJ.Vos
Rs$ 20kO
Input Offset Current
los
Input Bias Current
I.
Input Voltage Range
IVR
Common-Mode
Rejection Ratio
~
~
= ± 15V, TA =25°C, unless otherwise noted.
CMRR
OP-04G
OP-14G
OP-14GR
LIMIT
LIMIT
LIMIT
UNITS
6
mVMAX
mVMAX
Rs$ 20kO
VCM~±10V
tJ.CMRR
Power Supply
Rejection Ratio
PSRR
Vs ~ ±5V to ±20V
Rs$ 20kO
Output Voltage SWing
Vo
Large-Signal
Voltage Gain
1:.1...
0.75
VCM~±10V
Common-Mode Rejection
Ratio Match
......
OP-04N
OP-14N
200
nAMAX
50
75
500
nA MAX
±10
±10
±10
VMIN
85
80
70
dBMIN
94
94
60
100
150
!J.VIV MAX
RL " 10kO
RL " 2kO
±12
±12
±12
±12
±12
±10
VMIN
Avo
RL" 2kO
Vo~ ±10V
100
50
25
V/mV MIN
Power Consumption
(Both Amplifiers)
Pd
VOUT~ 0
170
170
180
mWMAX
Channel Separation
CS
100
100
Rs$1000
dBMIN
dB MIN
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal Yield loss, Yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±15V,
PARAMETER
SYMBOL
CONDITIONS
TA
= 25° C, unless otherwise noted.
OP-04N
OP-14N
OP-04G
OP-14G
OP-14GR
TYPICAL
TYPICAL
TYPICAL
UNITS
200
200
200
ns
Av~+1
Rlsetime
tr
Overshoot
OS
Slew Rate
SR
V'N~
50mV
RL ~ 2kll
C L ~ 50pF
Av~+1
V'N~
50mV
RL ~ 2kll
C L ~ 50pF
%
RL ~ 2kO
C L ~ 100pF
0.25
5·31
0.25
VII'S MIN
1/86, Rev. A
::s
~
~
~
0
......
t:
~
0
--------1!EMD
OP-04/0P-14 DUAL MATCHED HIGH-PERFORMANCE OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CHARACTERISTICS (Each Amplifier)
UNTRIMMED OFFSET VOLTAGE
VI TEMPERATURE
INPUT OFFSET CURRENT
VI TEMPERATURE
INPUT BIAS CURRENT
VI TEMPERATURE
2.6
70
60
OP.(J4
OP·14
'\
'\
OP.(J4C
OP·14C
'\
OP.(J4A
.......
~~~= OP·I'A
.......
I,
i'-
I'...
~~E
-20
+20
+80
+100
TEMPERATURE rC}
+140
-80
OPEN-LOOP GAIN VB
POWER SUPPLY VOLTAGE
300
-
-20
+20
+60
+100
TEMPERATURE rC}
I"'-....
"
'00
so
IL
OP.CJ4A & OP-04E
OP·14A 81 OP,'4E
OP·'4
r--
OP~~P')4A
+140
W~!U
TA·2lfC
111111111
'00
\
OP·0481
OP.(J4C
0P·,4&
OP·14C
op.,. "OP·14C \
60
70
60
o
OP-04
/
+20
+80
+100
TEMPERATURE (OCI
110
70
o
-20
-
r-.
CMRR VB FREQUENCY
;:~':2&"C
1IIIIIIrrnI
J.lll[l~
OP-04C
OP·14C
CP.(J4E
OP·,4E
-60
+'40
11111111111
110
"- .......
.......
o
'20
OP·04A 81 QP.()4E
OP 14A 81 OP·14E
TA "2SOC
r-...
'0
17"
PSRR VB FREQUENCY
'20
RL" 10k
t-t-
OP.04A
OP-14A
o
-60
CP·l'
~I-
OP·04E
I'-..
I....
OP.Q4C - OP.o4
r--.~
:t6
:1:10
:1:1&
'20
POWER SUPPLY (VOLTS)
1000.
INPUT SPOT NOISE
VOLTAGE VI FREQUENCY
60
,
60
\
I\.
60
'0
100
1k
'Ok
FREQUENCY (Hz)
'00k
'0
100
1k
FREQUENCY (Hz)
'Ok
'OOk
INPUT WIDEBAND NOISE VI
BANDWIDTH (0.1 Hz TO
FREQUENCY INDICATED)
INPUT SPOT NOISE
CURRENTvsFREQUENCY
'0
=
-
~
~IOO
. '0_,,_
Vs '" t15V
TA·2&"C
/
I
~
~
~
0.0'
0.'0
'.0
'0
FREQUENCY (Hz)
'00
'000
O"OL.,O""J.WO"','-OI.l..l.OWJ''',O.uJ.ww...I.J..wJIIL..I.~
FREQUENCY (Hz)
5·32
0,
,
0.,
1,0
10
BANOWIDTH (kHz)
'00
1/86, Rev. A
------I~ OP-04/0P-14 DUAL MATCHED HIGH-PERFORMANCE OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CHARACTERISTICS (Each Amplifier)
OPEN-LOOP GAIN
vs TEMPERATURE
,
300
,
'20
I--
VS .. :t15V
250
~200
z
§"
./
'"
/
"
-
'00
" "1"'-
so
t\.
'\
" 150
CLOSED-LOOP RESPONSE
FOR VARIOUS
GAIN CONFIGURATIONS
OPEN-LOOP
FREQUENCY RESPONSE
40
'\
Vs ."'6V '
TA-2S·C
~
60
+20
+80
+'00
TEMPERATURE rCI
+140
1.0
10
100
lk
10k lOOk
1M
'0
10M
~
NEGATIVE SWING
'OM
FREQUENCY (Hz)
a
k- ~
10
~
[I
ffl
0:
\
'l
r--..
~
0.'
'.0
0.'
1000
'0
-60
-20
+20
POWER CONSUMPTION
VI TEMPERATURE
35
VS=±15V
.1
I
\
I
+100
-
OP·04A
OP 14A
~A· 25~C
Vs ='±15V
1--(1) VIN)PIN
3)1.
-,Lv. vL=+,L -
@V1N(PIN3),,+10mV, Vo
\
1
~\
OP·04E
,OP.14E
/
I'- "'"-
+140
OUTPUT SHORT-CIRCUIT
CURRENT vs TIME
50
TA" 2(fC
+60
TEMPERATURE (-C)
LOAD RESISTANCE TO GROUND (kn!
POWER CONSUMPTION
vs POWER SUPPLY
'000
~ 1.0
o
100
FREQUENCY (kHz)
'0
"
1M
"'
II!
~
"
lOOk
INPUT RESISTANCE
VI TEMPERATURE
!
\
1Otc.
POSITIVE SWING
Vs= :l:15V
TA""26"C
a:
1k
'00
, -'
TA'" 2SOC
'4
VS" ±16V
r
100
OUTPUT VOLTAGE vs
LOAD RESISTANCE
,.
11111111
'" '"
-20
0.1
FREQUENCY (Hz)
MAXIMUM UNDISTORTED
OUTPUTvsFREQUENCY
10
"-
-
-40
-20
VS'":t15V
TA '" 25°C -
"""
~ 100
....0
I
80
\
"'"- I--
-15V
,
"
r---....
..........
'.0
o
20
40
TOTAL SUPPLY VOLTAGE. V+ TOV- (VOLTS)
60
36
-60
-20
+20
+60
TEMPERATURE
5-33
+100
rei
.140
'6 o
TIME FROM OUTPUT BEING SHORTED (MINUTES)
1/86, Rev. A
op-os
INSTRUMENTATION
OPERATIONAL AMPLIFIER
Precision MOllolithics Inc.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
voltage and bias current combined with very high levels of gain,
input impedance, CMRR, and PSRR.
Low Noise • • .. • • • • • • • • • • • •• 0.6/lVp-p Max, 0.1 to 10Hz
Low Drift VI. Temperature •••••••••••••• 0.5/lVloC Max
Low Drift VI. Time •••••••••••••••••• 0.2/lVlMonth Typ
Low Blal Current ....................... 2.0nA Max
High CMRR ............................ 114dB Min
High PSRR ............................ 100dB Min
High Gain ............................ 300,000 Min
High RIN Differential ...................... 30MCl Min
High RIN CM ........................... 200GCl Typ
Internally Compenseted •••••••••• Steble to 500pF Load
Fits 725, 108A and 741 Sockets
125° C Temperature Tested Dice
The OP-05 is a direct replacement in 725, 108A, and unnulled 741
sockets allowing instant system performance improvement
without redesign. The OP-05 is an excellent choice for a wide
variety of applications including strain gauge and thermocouple
bridges, high-gain active filters, buffers, integrators, and sampleand-hold amplifiers. For dual-matched versions, refer to the
OP-207 and OP-10 data sheets.
PIN CONNECTIONS
VOSTS~7V+
ORDERING INFORMATIONt
PACKAGE
HERMETIC
TA - 25°C
PLASTIC OPERATING
DIP
V08MAX TO...
DIP
TEMPERATURE
(mV)
8-PlN
8-PlN
14-PlN
a-PIN
RANGE
Of'OSAJ- OPOSAZ' Of'OSAY'
0.15
MIL
0.5
OPOSJ'
OPOSZ'
OP05Y'
MIL
0.5
OP05EJ
OPOSEZ
OP05EY OP-DSEP
COM
1.3
OP05CJ OPOSCZ OPOSCY OP05CP
COM
+
-IN 2
60UT
+IN 3
5 N,C.
•
v-leASE)
TO-99
(J-Sufflx)
EPOXY MINI-DIP
(P-Sufflx)
"
S-PIN HERMETIC DIP
(Z-Sufflx)
• For devices processed In total compliance to MIL-STO-883, add 1883 after
part number. Consult factory for 883 data sheet
tAli commercial and Industrial temperature range parts are available with
burn-In. For ordenng information see 1986 Data Book, Section 2.
14-PIN HERMETIC DIP
(Y -Suffix)"
GENERAL DESCRIPTION
'This package not
recommended for
new designs.
The OP-05 series of monolithic instrumentation operational
amplifiers combine excellent performance in low-signal-Ievel
applications with the simplicity of use of a fully-protected,
internally-compensated opamp. The OP-05 has low input offset
SIMPLIFIED SCHEMATIC
W~--~--------~------~----4I--------~--~------~------~------r-~---r--~
R.B
R1B
a1.
R9
OB
OUTPUT
~--4--t::.la.
NON
INVERTING
INPUT
027
INVERTINGo-...;.;..."...J'----~----I---........------_K
INPUT
025
R10
028
RB
V-~~----------------------~--~--~--~
5-34
______~__~--~
1/86, Rev, A
-----------l~ OP-OS INSTRUMENTATION OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS (Note 3)
NOTES:
1. See table for maximum ambient temperature rating and derating factor
Supply Voltage ................................... ±22V
Internal Power Dissipation (Note 1) .............. SOOmW
Differential Input Voltage .......................... ±30V
Input Voltage (Note 2) ............................ ±22V
Output Short-Circuit Duration ................. Indefinite
Storage Temperature Range
J, Y, and Z Packages ................ -6SoC to +1S0°C
P Package ..............•.......... -6SoC to +12SoC
Operating Temperature Range
OP-OSA,OP-OS ..................... -SsoC to +12SoC
OP-OSE, OP-OSC ....................... 0° C to + 70° C
Lead Temperature Range (Soldering, 60 sec) ...... 300°C
DICE Junction Temperature. . . . • . . . . .. -6So C to + 1S00 C
ELECTRICAL CHARACTERISTICS at Vs = ±1SV,
TA =
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
PACKAGE TYPE
SO'C
7.1mW/'C
14-Pin HermetiC DIP (VI
100'C
100mW/'C
S-Pin Hermetic DIP (ll
75'C
6.7mW/'C
S-Pln Plastic DIP (PI
36'C
5.6mW/'C
TO-99 (JI
2.
3.
For supply voltages less than ±22V, the absolute maximum Input voltage IS
equal to the supply voltage.
Absolute maximum ratings apply to both packaged parts and DICE, unless
otherWise noted
2So C, unless otherwise noted.
OP-05A
PARAMETER
SYMBOL
Input Offset Voltage
Vas
Long-Term Input Offset
Voltage Stability
AVos/Time
Input Offset Current
los
Input Bias Current
18
Input Noise Voltage (Note 2)
e np _p
en
Input Noise Voltage Density
(Note 2)
CONDITIONS
0.2
TYP
MAX
UNITS
015
0.2
0.5
mV
1.0
02
1.0
~V/Mo
2.0
1.0
2.S
nA
±2.0
±10
±3.0
nA
0.1 Hz to 10Hz
0.35
0.6
0.35
0.6
~Vp_p
fo= 10Hz
fo= 100Hz
fo= 1000Hz
10.3
10.0
9.6
IS.0
13.0
11.0
14
30
14
30
pA p_p
0.32
0.14
0.12
O.SO
0.23
0.17
0.32
0.14
0.12
O.SO
0.23
0.17
pAlJHZ
Input NOise Current DenSity
(Note 21
In
fo= 10Hz
fo= 100Hz
fo= 1000Hz
R 1NCM
007
MIN
0.7
O.IHz to 10Hz
Input ReslstanceCommon-Mode
MAX
(Note 3)
Input Voltage Range
IVR
Common-Mode Rejection Ratro
CMRR
VCM = ±13 5V
Power Supply Rejection Ratio
PSRR
Vs= ±3V to ±ISV
Large-Signal Voltage Gain
Ava
RL2: 2kO, Vo= ±10V
RL 2: 5000, Va = ±0.5V
Vs = ±3V (Note 31
Output Voltage SWing
Va
RL2: 10kO
RL2: 2kO
RL2: lkO
30
10.3
10.0
9.6
IS.0
13.0
110
nVlJHZ
60
MO
200
200
GO
±13.5 ±14.0
±135 ±140
126
300
150
20
114
126
500
200
500
500
150
500
4
10
±12.5 ±130
±12.0 ±12.S
±105 ±12.0
4
V
dB
10
~V/v
VlmV
±12.5 ±13.0
±120 ±12S
±10.5 ±12.0
V
SleWing Rate (Note 2)
SR
RL 2: 2kO
0.1
0.3
0.1
0.3
V/~s
Closed-Loop Bandwidth
(Note 2)
BW
AVCL = +10
0.4
0.6
04
0.6
MHz
Open-Loop Output ReSistance
Ro
Vo=O,lo=O
60
Pd
No load
Vs = ±3V, No load
90
Power Consumption
Offset Adjustment Range
Rp= 20kO
60
120
6
90
4
0
120
6
4
NOTES:
1. Long-term Input offset voltage stability refers to the averaged trend line
of Vosvs. Time over extended periods after the first 30 days of operation
Excluding the initial hour of operation, changes In Vas during the first 30
operating days are tYPically
Sample tested.
Guaranteed by design.
..
---'-------------------~---~
----_._-------
mW
mV
2.5~V.
Refer to typical performance curve.
1/86, Rev. A
5-35
-
>J,:I
,......
~
::sp..
~
<:
.....:I
~
0,......
~
>J,:I
SO
114
II
~
OP-05
TYP
±0.7
i np _p
R'N
MIN
(Note 1)
Input Noise Current
(Note 2)
Input Resistance Differential-Mode
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
~--~----
p..
0
-----------l~ OP-OS INSTRUMENTATION OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs = ±15V, -55 0 C S; TA S; +125 0 C, unless otherwise noted.
OP-OSA
PARAMETER
SYMBOL
Input Offset Voltage
Vos
Average Input Offset Voltage
Drift Without External Trim
With External Trim
TCVOS
TCVOSn
Input Offset Current
los
Average Input Offset Current
Drift
TCI OS
(Note 2)
TCl a
(Note 2)
MIN
CONDITIONS
(Note 2)
Rp= 20kO (Note 3)
MAX
TYP
MAX
UNITS
0.10
0.24
0.3
0.7
mV
0.3
0.2
0.9
0.5
0.7
0.3
2.0
1.0
/IoViOC
1.0
4.0
1.8
5.6
nA
50
pA/OC
±1
±4
±2
±6
nA
25
13
50
pAlOC
±13.0 ±13.5
Input Voltage Range
IVR
Common-Mode Rejection Ratio
CMRR
VCf" = ±13.0V
Power Supply Rejection Ratio
PSRR
VS=±3Vto±18V
Large-Signal Voltage Gain
AVO
RL ", 2kO, Vo= ±10V
MIN
25
Input Bias Current
Average Input Bias Current
Drift
OP-OS
TYP
110
123
200
400
5
±13.0 ±13.5
123
150
400
V/mV
±12.0 ±12.6
V
20
±12.0 ±12.6
Output Voltage Swing
V
110
dB
20
ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = 25 0 C, unless otherwise noted.
Op-osc
OP-OSE
PARAMETER
SYMBOL
Input Offset Voltage
Vos
Long-Term Input Offset
Voltage Stability
LlVOs/Time
Input Offset Current
CONDITIONS
MIN
(Notes 1. 2)
lOS
I nput Bias Current
TYP
MAX
TYP
MAX
UNITS
0.2
0.5
0.3
1.3
mV
0.3
1.5
0.4
2.0
1.2
3.8
1.8
6.0
nA
±1.2
±4.0
±1.8
±7.0
nA
MIN
Input Noise Voltage (Note 2)
0.1 Hz to 10Hz
0.35
0.6
0.38
0.65
Input Noise Voltage Density
(Note2)
fO= 10Hz
fo= 100Hz
fo= 1000Hz
10.3
10.0
9.6
18.0
13.0
11.0
10.5
10.2
9.8
20.0
13.5
11.5
nVly"RZ
14
30
15
35
pA p_p
0.32
0.14
0.12
0.80
0.23
0.17
0.35
0.15
0.13
0.90
0.27
0.18
pA/y"RZ
Input Noise Current (Note 2)
inp_p
0.1 Hz to 10Hz
Input Noise Current Density
(Note 2)
fO= 10Hz
fo= 100Hz
fo= 1000Hz
Input Resistance Differential-Made
(Note 3)
15
IVR
Common-Mode Rejection Ratio
CMRR
Power Supply Rejection Ratio
PSRR
VS=±3Vto±18V
AvO
RL ", 2kO. Vo= ±10V
RL ", 5000. Vo= ±0.5V
Vs = ±3V (Note 3)
Large-Signal Voltage Gain
MO
160
120
GO
±13.5 ±14.0
±13.0 ±14.0
110
123
100
120
200
500
120
400
150
500
100
400
5
RL ",10kO
RL ",2kO
RL ",lkO
Output Voltage Swing
8
33
Input ResistanceCommon-Mode
Input Voltage Range
50
20
±12.5 ±13.0
±12.0 ±12.8
±10.5 ±12.0
32
Slewing Rate (Note 2)
SR
RL ="' 2kO
0.1
0.3
0.1
0.3
BW
AveL = +1.0
0.4
0.6
0.4
0.6
Open-Loop Output Resistance
VO=O.IO=O
60
Power Consumption
No load
Vs = ±3V. No load
90
120
4
6
Offset Adjustment Range
Rp= 20kO
NOTE: See notes on previous page.
5-36
V/mV
±12.0 ±13.0
±".5 ±12.8
±12.0
Closed-Loop BandWidth
(Note 2)
4
V
dB
V
MHz
o
60
95
150
8
4
mW
mV
1/86, Rev. A
------------1~ OP-05 INSTRUMENTATION OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs= ±15V, Q·G:S TA:S +7Q·G, unless otherwise noted.
OP-05C
OP-05E
PARAMETER
SYMBOL
Input Offset Voltage
Vas
Average Input Offset Voltage
Drift Without External Trim
W,th External Trim
TCVos
TCVoSn
Input Offset Current
los
Average Input Offset Current
Drift
TClos
(Note 2)
Rp= 20kfl (Note 3)
(Note 2)
Input BIas Current
Ie
Average Input Bias Current
Drift
TCl a
Input Voltage Range
IVR
Common-Mode RejectIon RetIa
CMRR
VCM = ±13.0V
Power Supply Rejection Ratio
PSRR
Vs= ±3Vto ±18V
Large-SIgnal Voltage GaIn
Ava
RL 2:2kfl, Vo =±10V
Va
RL2: 2kfl
Output Voltage Swing
MIN
CONDITIONS
(Note 2)
TVP
MAX
TVP
MAX
UNITS
0.25
0.6
0.35
1.6
mV
0.7
0.2
2.0
0.6
1.3
0.4
4.5
1.5
p'vrc
1.4
53
2.0
8.0
nA
8
35
12
50
pAl"C
±15
±5.5
±2.2
±9.0
nA
13
35
18
50
pAloC
±13.0 ±13.5
107
123
180
450
MIN
±13.0 ±13.5
ffi
120
p.VN
......
100
400
VlmV
±11.0 ±126
V
::l
p..
32
±120 ±12.6
V
97
10
dB
51
~
~
NOTES:
1. Long-Term I nput Offset Voltage Stability refers to the averaged trend line
of Vas vs. Time over extended periods after the first 30 days of operation.
Excluding the initial hour of operation, changes In Vas during the first 30
operating days are typically 2.5p.V. Refer to typical performance curve.
2. Sample tested.
3. Guaranteed by design.
~
0......
~
~
C5
5-37
1/86, Rev. A
-----------l~ OP-05 INSTRUMENTATION OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS (125° C TESTED DICE AVAILABLE)
1. BALANCE
2. INVERTING INPUT
3. NONINVERTING INPUT
4. V5. NO CONNECTION
6. OUTPUT
7. V+
8. BALANCE
For additional DICE information refer to
1986 Data Book, Section 2.
DIE SIZE 0.100 X 0.051 Inch, 5100 sq. mils
(2.54 X 1.30 mm, 3.29 sq. mm)
WAFER TEST LIMITS
at Vs = ± 15V, TA = 25°C for OP·05N, OP·05G and OP·05GR devices; TA = 125°C for OP·05NT and
OP·05GT devices, unless otherwise noted.
OP·OSNT
OP·OSN
OP·OSGT
Op·OSG
OP·OSGR
LIMIT
LIMIT
LIMIT
LIMIT
LIMIT
UNITS
Vas
0.25
0.15
0.7
0.5
1.3
mVMAX
PARAMETER
SYMBOL CONDITIONS
Input Ollset Voltage
Input Offset Current
los
4.0
2.0
5.7
3.8
6.0
nAMAX
Input Bias Current
I.
±4
±2
±6
±4
±7
nAMAX
Input Resistance
Dillerential Mode
R'N
(Note 2)
±13.S
±13.0
±13.S
±13.0
VMIN
110
114
110
110
100
dBMIN
20
10
20
20
30
~VNMAX
RL = 10kO
RL = 2kO
RL =lkO
±12.0
±12.S
±12.0
±10.S
±12.0
±12.S
±12.0
±10.S
±12.0
±11.S
VMIN
RL = 2kO
Vo =±10V
200
200
150
200
120
VlmVMIN
±30
±30
±30
±30
±30
V MAX
120
150
mWMAX
IVR
CMRR
VCM = ± 13.5V at +25° C
VCM = ± 13.0 at + 125' C
Power Supply
Rejection Ratio
PSRR
Vs = ±3V to ±18V
Output Voltage Swing
Va
Large-Signal
Voltage Gai n
Avo
Dillerential Input
Voltage
Pd
MOMIN
±13.0
Input Voltage Range
Common-Mode
Rejection Ratio
Power Consumption
15
20
120
Vour = OV
NOTES:
1. For 25° C characteristics of NT & GT devices see N & G characteristics
respectively.
2. Guaranteed by design.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS
at Vs= ±15V. TA= +25°C, unless otherwise noted.
OP·OSNT
OP·OSN
OP·OSGT
Op·OSG
OP·OSGR
TYPICAL
TYPICAL
TYPICAL
TYPICAL
TYPICAL
UNITS
Rs" 500
0.3
0.3
0.7
0.7
1.2
~VloC
Rs" 500, Rp = 20kO
0.2
0.2
0.3
0.3
0.4
~VloC
8
8
12
pAloC
0.3
0.3
0.3
0.3
VI~s
0.6
06
0.6
0.6
MHz
PARAMETER
SYMBOL CONDITIONS
Average Input
Offset Voltage Drift
TCVos
Nulled Input
Offset Voltage Drift
TCVOSn
Average Input
Ollset Current Drift
TClos
Slew Rate
SR
RL" 2kO
0.3
Closed-Loop
Bandwidth
BW
AVCL = +1
0.6
5-38
1/86, Rev. A
-----------I~ OP-05 INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
TRIMMED OFFSET
VOLTAGE VB TEMPERATURE
16
1.0
30
Vas TRIMMED TO <5f.1V AT 25"C
NULLING POT" 20k11
-
I--
2 OP-05E
3 OP-05
I
4. OP-05C
I
(il
Q
I
1\ a>
12
OP-05C
/
1 OP-05A
~
-
JI5
I ~/
~\ I~'/
""-
I" IF
o
-60
..
reJ
100
~
1 DAY 1WK 1 MO 6MO
....
2
0
~
~
LONG-TERM
ERROR
DRIFT
ERROR BAND
-12
o
1
1
1
1
1
1
1
1
1
1
5 ~rr~rH~rH~-H~-Hffi*-H~~.!IIII
1
1
1.0
10
100
1
2
1k
1
~ ~20
V~.j'5)-
TIME (SEC)
~
:;
VB
....
i(
0:
0
....
1.0
~
ie
II I 11111
Ii!a:
Ii!a:
UNTRIMMED -550 C TO 125°C
a:
0
a: 0.1
~
~
a:
a:
0
a:
ffi
-
10
0.01
100
UIllJU1k I IlL
10k
":E
lOOk
MATCHED OR UNMATCHED SOURCE RESISTANCE (n)
11
12
0.5
I-+-+-+--+-:-i-/--"..
:E
TRIMMED _55°C TO 125°C
9
ill
~
,.~
8
:c
:: l1'eTO 711'e
*
UNTRIMMED 25°C
ffi
~
10
:;
!
-sSOc TO 125°C
Vs '" ±15V
7
(CURVES ARE SYMMETRICAL
ABOUT ZERO FOR .6.VOS < 0)
MAXIMUM ERROR
SOURCE RESISTANCE
QP-05A
6
1.0
10k
10
.§.
5
t
TIME (HOURS)
VB
4
TRIMMED
OFFSET VOLTAGE DRIFT
c:;
w
1
40
20
3
TIME (MONTHS)
~M~
~~~~~~~~~~~-W~.
0.1
100
TA "'70°C
8
~~~~~ffiOO-HffiOO-H~-H~
0,01
50
r-- ~
r-- ~~~
: 10 r-- "Ai 1 1
r-~
/1' 1 1 1
5 5
IMMERSEO
IN 7rfJC OIL BATH
~ r-- - OEVleE
-2
0.001
I--
20
~ 15
WARM·UP
DRIFT
BAND
....
RS = 5051
Vs "" ±15V
TA '" 25°C
~
o
~~~~{)~INE
-16
25
g
w
~
~ . .c..0,3p.V/mo TREND LINE
30
~
~
1
-
OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK
4f+ttttI1H-11tt1iiH'iffttm-'Tt_...,..,._...,..,._+!J!IIII
....
05E
TEMPERATURE ("C)
w
g
I--r
....o.r".-. •.•'j"O·2;v/mo TREND LlNEJ
~~~ 3JNlrno TREND LINEr¥~~~LINE
,
V'.
,
i
f-- c--
OP-05A
-50
OFFSET
VOLTAGE DRIFT WITH TIME
~
--;
0,01
TEMPERATURE
1 SEC 1 MIN 10MIN
~~~~~LINE~~~""~""""'':':~
OP-06
I-"
V
IS /
.--r-
-
/
\\
~
TYPICAL OFFSET
VOLTAGE STABILITY VB TIME
UNTRIMMED OFFSET
VOLTAGE VB TEMPERATURE
I
I~~' RI' ~R121
lk
10k
SOURCE RESISTANCE (.11)
5-39
lOOk
,.::>
X
""
UNTRIMMED -55"C ITJ
112~n
UNTRIMMED 25"C
01
,/
II 11111
TRIMMED -55"C TO 126°C
RS -R 1 -R 2
II 11111
0.0\00
lk
111111
10k
lOOk
MATCHED SOURCE RESISTANCE (n)
1/86, Rev. A
I
--
-----------I~ OP-G5 INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
MAXIMUM ERROR
INPUT BIAS CURRENT
VI TEMPERATURE
VI SOURCE RESISTANCE
10
1
OP..QSC
O'c TO 70'C
i
UNTRIMMED'c;.C to 70'C
12 '.0
UNTRIMMED 2&'C
iI
i
0.'
TRIMMED
~ ±16~
Vs
VS~±,15IV
C TO 70'
100
-
VS
~±16J
•
OP·08
,
::::::: ~OBIE /
........ ......
RS- R, - R2
0.0'
~I -
", "-
i-'
INPUT OFFSET CURRENT
VI TEMPERATURE
1111111
~loP..Q81
OP.QIA
./
r--.
IOP-,
1k
10k
MATCHED SOURCE RESISTANCE 1111
10Dk
o
-&0
so
100
INPUT WIDEBAND NOISE
VI BANDWIDTH (0.1 Hz
TO FREQUENCY INDICATED)
,0
=
;t; r-- ?
".
~
10
".,
,00
TEMPERATURa (Oe)
TEMPERATURE I'C)
OP-05 LOW FREQUENCY NOISE
OP.Q&C
::::---
0
-110
,21
......
1000
VOLTAGE NOISE DENSITY
VI FREQUENCY
EEEm!';C=;:=:;:====g
V. . :l:lIV
_ TA- +28"C
~
ISEE NOISE TEST CIRCUIT)
I---"
0.1
.00
1k
100k
10k
'0
FREQUENCY 1Hz)
BANDWIDTH 1Hz)
120
110
,00
.j
J~~I ~I~B"~ 'JJ.lll
Vs ':3~ ±'BV
j ~~~~
TO
11lilllL
-OP..QSC
aD
OPEN-LOOP GAIN VI
POWER SUPPLY VOLTAGE
CMRR VI FREQUENCY
PSRR VI FREQUENCY
,30
120
JJJlt
OP-O&C
110
~
J~~lllm
~
t~I~~\.J
1000
IIII
_I
100
/
~so
1\
70
so
&0
0.'
'.0
_I_
I- TA-+2B"C
TA - +2S'c
VCM -±13,&V
..........
~
10
lk
~
70
~
10
'00
FREQUENCY 1Hz)
....... ......
10k
80
'.0
,0
100
'k
FREQUENCY 1Hz)
5-40
,Ok
lOOk
o
o
:1:10
±IS
±S
POWER SUPPLY VOLTAGE (VOLTS)
±20
1/86, Rev. A
------------I~ OP-05 INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN-LOOP GAIN
VB FREQUENCY
120
r-
"
Z
~ 40
j
"
AV.1L
AV·
[\
0,'
,0
'00
'k
,Ok 'Oak
-20
'M 'OM
FREQUENCY IHI)
,J
'0 ,00
3.
::::: TA-+26"C
,
"-1'-
1k
10k
100k
FREQUENCY IH.)
r\
1\
o
1M
tL
t?
V
-20
-'0
V
"~ -10
~
! -20
,.
./
V
~
I
o
40
60
TOTAL SUPPLY VOLTAGE, V+ TO V- (VOL. TS)
20
20
VS·±16V TA",26°C._
-30
-30
i'
-20
-10
10
I
I
20
'M
10k
lOOk
FREaUENCV {H;cl
MAXIMUM OUTPUT VOLTAOE
VI LOAD RESISTANCE
-3.
AT IVDIFFI S 'ov, Ilel ~~~~ :g::~:f) ~
,,-
',0
'k
10M
S'.A IOP·OBCI ...,
/
11111
VS=±15V
TA" +250 C :
INPUT BIAS CURRENT VI
DIFFERENTIAL INPUT VOLTAGE
POWER CONSUMPTION
VI POWER SUPPLY
1000
~
AV· ,
-40
~
VS=±15V_
TA '" 26°C
80
I'\.
2B
I I
t--
AV.10~
~
~
'00
-
TA" +26"C
I"
80
~
VSI=±15~
i'--
MAXIMUM OUTPUT SWING
VB FREQUENCY
CLOSED-LOOP GAIN
VB FREQUENCY
2.
i
I-
Ii;
i2
II:
~
,B
a'"
.~
! ,.
!
"
~
"
z
>=
ffi
>
!
30
30
DIFFERENTIAL INPUT VOLTAGE {VOLTS}
~
::>
TAI.+2~d I
II I
I I I! III
VS.±'BV
VIN "±10mV
POSITIVE SWING
NEGATIVE SWING
1/1/
rl
i
•
100
1k
10k
1.0AC RESISTANCE TO GROUND (m
TYPICAL LOW·FREQUENCY NOISE TEST CIRCUIT·
TYPICAL OFFSET VOLTAGE TEST CIRCUIT
+15V
200kO
100.11
600
,oon
~----~---oVo
INPUT REFERRED NOISE '"
~ .. :;,~~~m
.
2oonV/em
~10Hz
FILTER
* OBSERVATION TIME LIMITED TO 10 SECONDS MAXIMUM.
5·41
1/86, Rev. A
----------l1£MD
OP-GS INSTRUMENTATION OPERATIONAL AMPLIFIER
FSET NULLING CIRCUIT
Offset stability can be degraded by stray thermoelectric
voltages arising from dissimilar metals at the contacts to the
input terminals. Best operation will be obtained when both
input contacts are maintained at the same temperature,
preferably close to the temperature of the device's package.
v+
TYPICAL APPLICATIONS
OUTPUT
INPUT
STABLE, HIGH-IMPEDANCE BUFFER
SR = O.25V/.usec
NOTE: PIN OUTS SHOWN FOR J, P, AND Z PACKAGES.
BURN-IN CIRCUIT
ZIN
::gg~~o9n
OUTPUT NOISE .. 0 35/JV P-P TYP
OUTPUT OFFSET .. O.2mV TVP
IN = ±1.0nA
OUTPUT
BANDWIDTH .. 600kHz
HIGH IMPEDANCE, HIGH COMMON-MODE REJECTION
INSTRUMENTATION AMPLIFIER
A4
2kn
RS
20k.l1
NOTE: PIN OUTS SHOWN FOR J, P, AND Z PACKAGES.
APPLICATIONS INFORMATION
OP-05 series devices may be fitted directly to 725 and
10S/10SA Series sockets with or without removal of external
compensation components. Additionally, the OP-05 may be
fitted to unnulled 741 series sockets. However, if conventional
741 nulling circuitry is in use, it should be modified or
removed to enable proper OP-05 operation. The OP-05
provides stable operation with load capacitance of up to
500pF and ±10V swings; larger capacitances should be
decoupled with a 500 resistor.
ADJUST R7 FOR MAXIMUM CMRR
5-42
1/86, Rev. A
OP-06
HIGH -GAIN INSTRUMENTATION
OPERATIONAL AMPLIFIER
Precision Monohthics Inc.
FEATURES
• Very High Voltage Gain ................ 1,OOOV/mV Min
• Low Offaet Voltage and Offaet Current
• Low Drift va. Temperature
(TCVoa) •......•.........•.......... O.8!,V/oC Max
• Low Input Voltage and Current Nolae
• Low Offset Voltage Drift with Time
• High Common-Mode Rejection ............ 120dB Typ
• High Power Supply Rejection •....•..••.... 2!'v/V Max
• Wide Supply Range ................... ±3.0V to ±22V
• MIL-STD-883 Proceaalng Available
• Slew Rate to .........•....................... 100V/!'a
Superior DC input characteristics include very low offset
voltage and current, extremely high open-loop gain, low 1/f
and wideband noise, and low "popcorn" noise. Low offset
voltage drift is improved by a nulling technique that optimizes
TeVos performance when Vos is nulled to zero. Very high
common-mode and power supply rejection enable accurate
performance in noisy environments.
Flexible external compensation provides wide-bandwidth
and high slew rate operation in high closed-loop gain
applications. Excellent long-term stability, and compatibility with MIL-STD-883 processing, make the OP-06 an
excellent choice for high-reliability applications. For example,
process control and aerospace applications; including strain
gauge and thermocouple amplifiers, low-noise audio amplifiers, and instrumentation amplifiers. The OP-06 is a direct
replacement for all 725 types providing superior DC and
noise performance plus the unique feature of complete Input
differential Yoltage and output short-circuit protection.
ORDERING INFORMATIONt
PACKAGE
TA =2SoC
Voa MAX
(mV)
0.2
0.2
0.5
0.5
1.3
1.3
TO-99
a-PIN
HERMETIC
DIP
a-PIN
OPERATING
TEMPERATURE
RANGE
OP06EJ
OP06AJ*
OP06FJ
OP06BJ*
OP06GJ
OP06CJ*
OP06EZ
OP06AZ*
OP06FZ
OP06BZ*
OP06GZ
OP06CZ*
COM
MIL
COM
MIL
COM
MIL
PIN CONNECTIONS
VOSeTn7V+
·For devices processed In total compliance to MIL-STD-BB3, add IBB3 after
part number. Consult factory for BB3 data sheet.
t All commercial and Industrial temperature range parts are available with
burn-In. For ordering Information see 19B6 Data Book, Section 2.
-IN 2
+
6 OUT
+IN 3
5 COMP
•
V-leASE)
GENERAL DESCRIPTION
The OP-06 monolithic instrumentation operational amplifier
is designed for accurate high-gain amplification of low level
signals. High common-mode rejection reduces Signal
degradation when large common-mode voltages are present.
I-PIN HERMETIC DIP
(Z-SuHlx)
TO-99 (J-Sufflx)
SIMPLIFIED SCHEMATIC
R,9""
_ _-
.....--0 OUTPUT
R20**
R3
'-I--l-......r
026
*027,028, R21, R22, COM·
PRISE THE INPUT PROTEC·
TION CIRCUIT
R5
R6
Rl0
R11
R'5
R'6
R17
"'023,029, R,9, R20 COM·
PRISE THE OUTPUT PRO·
TECTION CIRCUIT.
V-
S·43
- - - _..•. _--, ' - _ . , - - - - - -
1/86, Rev. A
--------f~ OP-G6 HIGH-GAIN INSTRUMENTATION OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
(Note 3)
Supply Voltage ••••••••••••••••••••••••••••••••••• ±22V
Internal Power Dissipation (Note 1) •••••••••••••• 500mW
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
TO-99(J)
SOOC
7.1 mW'o C
S-Pin Hermetic DIP (Z)
75°C
6.7mVrC
Differential Input Voltage •••••••••••••••••••••••••• ±30V
PACKAGE TYPE
Input Voltage (Note 2) ..•..•••..•••.•••...•••••••. ±22V
Output Short-Circuit Duration ••••••••••••••••• Indefinite
Storage Temperature Range. • • • • • • • • ••
-65' C to + 150' C
Operating Temperature Range
OP-06A, OP-06B, OP-06C ••••••••••• -55'C to +125'C
2. Forsupply voltages less than ±22V, the absolute maximum input voltage Is
equal to the supply voltage.
3. Absolute ratings apply to both DICE and packaged parts, unless otherwise
noted.
OP-06E, OP-06F, OP-06G ••••••••••••••• O'C to +70'C
Lead Temperature Range (Soldering, 60 sec) •••••• 300' C
DICE Junction Temperature •••••••••••
-65' C to + 150' C
ELECTRICAL CHARACTERISTICS at Vs = ±
15V, TA
= 25' C, unless otherwise noted.
OP-06A/E
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
Rs S 2OkO (Note 2)
Input Offset Current
Input Bias Current
Input Noise Voltage
Density
Input Noise Current
Density
Input Resistance
MIN
OP 08B/F
OP-08C/G
o
TYP
MAX
0.06
los
Ie
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
0.2
0.2
0.5
0.4
1.3
mV
0.3
2.0
0.75
5.0
2
13
nA
30
70
30
so
40
110
nA
en
fO= 10Hz (Note 1)
10= 100Hz (Note 1)
10= 1000Hz (Note 1)
90
8.0
7.0
15.0
9.0
7.5
9.0
8.0
7.0
15.0
9.0
7.5
9.0
8.0
7.0
15.0
9.0
7.5
nVl.JHz
In
10= 10Hz (Note 1)
10= 100Hz (Note 1)
10= 1000Hz (Note 1)
0.5
0.25
0.15
1.2
0.8
0.25
0.5
0.25
0.15
1.2
0.6
0.25
0.8
0.3
0.2
1.4
0.7
0.3
pAl.JHz
R'N
(Note 3)
0·8
1.8
0.7
1.8
05
1.5
MO
Large-Signal
Voltage Gain
Ava
Rl" 2kO,
Vo=±10V
1,000
3,000
1,000
3,000
500
3,000
VlmV
Output Voltage
Swing
Va
Rl " 10kO
Rl " 2kO
Rl " lkO
±12.5
±120
±11.0
±13.0
±128
±12.5
±12.5
±12.0
±11.0
±13.0
:1:12.8
±12.5
±12.0
±11.5
±13.0
±12.8
±12.0
V
Input Voltage Range
IVR
±13.5
:1:14.0
±13.5
±14.0
:1:13.5
±14.0
V
114
120
114
120
110
115
dB
CMRR
VCM=±13.5V
Rss2OkO
Power Supply
Rejection Ratio
PSRR
VS =±3Vto ±18V
Rs S2OkO
Power Consumption
Pd
Common-Mode
Rejection Ratio
Large-Signal
Voltage Gain
Ava
Rl ,,5000, (Note 3)
Vo=±0.5V
Vs=±3V
Power Consumption
Pd
Vs=±3V
100
0.5
2.0
10
5.0
2.0
10
pVN
90
120
90
120
110
150
mW
100
600
4
6
so
600
4
6
600
VlmV
4
mW
NOTES:
1. Sample tested.
2. Thermoelectric voltages generated by dissimilar metals at the contacts to
the input terminals can degrade drift performance. Both Sides of the
contacts should be kept at approximately the same temperature. All
temperature gradients should be minimized.
3. Guaranteed by design.
5-44
1/86, Rev. A
---------1~ OP-06 HIGH-GAIN INSTRUMENTATION OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs= ±15V, -55·C ~ TA~ +125·C, unless otherwise noted.
OP-06B
OP-06A
PARAMETER
MIN
TYP
MAX
0.08
RS = 500 (Note. 1. 2)
RS = 500 (Note. 2. 3)
Rp= 20kO
SYMBOL
CONDITIONS
Vos
Rs" 20kO (Note 2)
TCVos
TeVosn
MIN
OP-06e
TYP
MAX
0.28
0.3
0.3
0.8
0.2
0.25
0.8
4.0
22
40
60
120
MIN
TYP
MAX
UNITS
07
0.5
16
mV
07
2.0
14
45
~VI"C
0.6
028
1.0
0.5
15
10
06
2.0
40
180
2.0
3.0
25
90
14
150
pA/OC
25
45
70
180
35
45
110
180
nA
Input Offset Voltage
(Without external
trim)
Average Input Offset
Voltage Drift (Without external tnm)
Average Input Offset
Voltage Drift (With
external tnm)
Input Offset Current
Average Input Offset
Current Dnft
Input Bias Current
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
lOS
TCIOS
20
18
CMRR
PSRR
VCM = ±13 5V
Rs" 20kO
109
112
109
95
110
Vs = ±3V to ±18V
dB
15
Rs" 20kO
AvO
TAMAX
TAMIN
Output Voltage
Swmg
1.000
700
3.500
2.000
1.000
3.500
400
3.200
700
1.800
300
1.700
±120
±12.6
±12.0
±126
±11.0
±12.6
ELECTRICAL CHARACTERISTICS at Vs= ±15V, Q·C ~
~VIV
SYMBOL
CONDITIONS
Vos
RS" 20kn (Note 2)
TCVos
TCVosn
MIN
V/mV
V
TA~ 7Q·C, unless otherwise noted.
OP-06E
PARAMETER
112
nA
VO =±10V;R L ?:2kO
Large-Signal
Voltage Gain
(Note 1)
15
OP-06F
TYP
MAX
008
RS = 500 (Note. 1. 2)
RS = 500 (Note. 2. 3)
Rp= 20kO
MIN
OP-06G
TYP
MAX
028
0.25
03
08
0.2
025
08
40
MIN
TYP
MAX
UNITS
06
0.5
1.6
mV
07
20
14
4.5
~V/OC
0.6
028
10
0.5
1.5
~V/OC
10
065
20
5.0
180
20
30
15
25
nA
90
14
150
pAlOC
80
180
35
45
110
Input Off.et Voltage
(Without external
trim)
Average Input Offset
Voltage Drift (Without external tnm)
Average Input Offset
Voltage Dnft (With
external trim)
Input Offset Current
lOS
Average Input Offset
Current Dnft
Input BIBS Current
Common-Mode
Rejection RatiO
Power Supply
Rejection Ratio
TCIOS
Output Voltage
Swing
20
18
CMRR
PSRR
VCM =±135V
Rs ,,20kO
109
22
60
40
120
112
Vs = ±3V to ±18V
109
10
Rs" 20kO
30
45
50
112
15
95
7.0
180
110
30
nA
dB
15
~VIV
VO=±10V. RL 2!2kO
Large-Signal
Voltage Gain
(Note 1)
AVO
TAMAX
TAMIN
1.000
800
3.500
2.000
1.000
800
3.500
1.800
400
3.200
300
1.700
±120
±126
±120
±126
±110
±126
V/mV
V
NOTES:
1.
2.
Sample tested.
Thermoelectric voltages generated by dissimilar metals at the contacts to
the Input terminals can degrade drift performance. Both sides of the
3
5-45
contacts should be kept at approximately the same temperature. All
temperature gradients should be minimized.
Guaranteed by Input bias current
1/86, Rev. A
---------llEHD
OP-06 HIGH-GAIN INSTRUMENTATION OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
6.
NULL
INVERTING INPUT
NONINVERTING INPUT
VCOMPENSATION
OUTPUT
7. V+
8. NUll
For additional DICE information refer to
1986 Data Book, Section 2.
DIE SIZE 0.094 X 0.050 Inch, 4700sq. mils
(2.39 X 1.27 mm, 3.03 sq. mm)
WAFER TEST LIMITS
at
Vs = ± 15V,
TA
= 25° C for OP-06N, OP-06G and OP-06GR devices; TA = 125° C for OP-06NT and
OP-06GT devices, unless otherwise noted. (Note 2)
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
RsS 20kO
Input Offset Current
los
Input Bias Current
18
Input Resistance
Differential Mode
R'N
Input Voltage Range
IVR
OP-06NT
LIMIT
OP-06N
LIMIT
OP-06GT
LIMIT
OP-06G
LIMIT
OP-06GR
LIMIT
UNITS
0.3
0.2
0.7
0.5
13
mVMAX
5
13
nA MAX
60
70
70
80
110
nAMAX
0.7
0.5
MOMIN
0.8
(Note II
Common-Mode
Rejection Ratio
CMRR
VCM =±13.5
RsS 20kO
Power Supply
Rejection Ratio
PSRR
Vs= ±3V to ±18V
RsS 20kO
±13.0
±13.5
±13.0
±13.5
±13.5
VMIN
108
114
108
114
110
dB MIN
10
p.VIV MAX
±12.0
±12.5
±12.0
±11.0
±12.0
±115
VMIN
6
Output Voltage Swing
Vo
RL"= 10kO
RL"= 2kO
RL"= lkO
±12.0
±12.5
±12.0
±11.0
Large-Signal
Voltage Gam
Avo
RL"= 2kO
Vo= ±10V
1000
1000
800
1000
500
VlmV MIN
±30
±30
±30
±30
±30
V MAX
120
150
mWMAX
Differential Input
Voltage
Power Consumption
(VOUT = OVI
Pd
120
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS
at
Vs = ±15V,
TA
= +25°C, unless otherwise noted.
OP-06NT
TYPICAL
OP-06N
TYPICAL
OP-06GT
TYPICAL
OP-06G
TYPICAL
OP-06GR
TYPICAL
UNITS
R s S500
0.3
0.3
0.7
0.7
1.4
p.VI'C
RsS 50kO
Rp= 20kO
0.2
0.2
0.28
0.28
0.5
p.V/'C
3
3
8
8
14
pA/'C
PARAMETER
SYMBOL
CONDITIONS
Average Input Offset
Voltage Drift
TCVos
Nulled Input Offset
Voltage Dnft
TCVoSn
Average Input Offset
Current Drift
TClos
NOTES:
I. Guaranteed by input bias current.
2. For +25'C specifications of OP-OSNT and OP-06GT, see OP-OSN and
OP-06G respectively.
5-46
1/86, Rev. A
---------I~ OP-08 HIGH-GAIN INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
SLEW RATE
USING RECOMMENDED
COMPENSATION NETWORKS
OPEN-LOOP RESPONSE FOR
VALUES OF COMPENSATION
ISO ,--....,..__-....,..--,----,---,
120
100
t--""~-"...2_----t---t--j
CLOSED-LOOP FREQUENCY
RESPONSE FOR VALUES OF
COMPENSATION
8Or----c:::::::r-r--r-T"""---,
Vs· :t1SV
TA-26'IC
8Oi--....- -.....;;::-t-+-',....;;:---j
10
1..0
!~ @~--~---..~~t-~~--;
~
0.1
c
0,01
"
~
'"
§ ~I---+--~~~+-~~--j
~ o~---~----.l-.~=+-+-"""'..-l
NO COMPENSATION NEEDED
-20~--~--+-~-+-+-~~
IIIIIIIIIIIINI
-30 1.':0--::::-----:I::-k--:I~Ok:---:1:-:00::-k--:-::.L...-:-!,OM
III
0.001
N
1.0
FREQUENCY (Hz)
FREQUENCY COMPENSATION
COMPENSATION VALUES
Avel
R1
C1
(0)
(j.lF)
10000
10k
50pF
1000
470
0.001
100
47
0.01
10
27
0.05
270
1
10
0.05
39
0.0015
0.02
COMPENSATION CIRCUIT (J or Z PACKAGE)
OFFSET VOLTAGE
TRIM
USE R3 (= 51.11) WITH
CAPACITIVE LOAD
R3
*THE COMPENSATION NETWORK (R1, ell SHOULD BE RE·
TURNED TO THE V-TERMINAL. IF THE NETWORK IS RE·
TURNED TO GROUND, SERIOUS DEGRADATION OF POWER
SUPPLY REJECTION PERFORMANCE WITH FREQUENCY
WILL OCCUR. SEe TYPICAL CURVES (PSRR vs FREQUENCY).
**THE TRIMMING POTENTIOMETER SHOULD BE 20krl. FOR
OPTIMUM NULLED OFFSET VOLTAGE DRIFT see TYPI·
CAL CURVES (TRIMMED OFFSET VOLTAGE DRIFT AS A
FUNCTION OF TRIMMING POTENTIOMETER)
5-47
I
C,
FREQUENCY
R, COMPENSATION
V- OR GND·
1/86, Rev. A
---------IIEMD
OP·06 HIGH·GAIN INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
TRIMMED OFFSET VOLTAGE
V8 TEMPERATURE
30
~
VOSTRIMMEDTO
!
>
~
o
~6"VAT25'~
NULLINO POT'" 20kn
1
1. OP.O~A
\
"
~
o
w
310
~ !)
I..'
~
",'I
~
~
w
"~
5
>
I
I
75
100
0.Q1
100
125
-75 -50
....
k-'
~
!!
f=:::::--
~
--
-
f-
-0.6
op·OeA -
OP·06B
-II
1+-1
°r 1- 0J_061
-25
25
50
o
125
130
I
Op 06B
I I
I
Rp .. 50kn
r- ~~
r-- ~n
1'0..
Vs
-75
-50
-25
Vs
75
100
125
II ~ll
~
110
-75 -50
1\
20
~~~ERNAL
1
III
75
100
125
4
lOOk
1M
NEGATIVE
i-'
1\
I
/1
\
/
i
I
vS,7,~~,·V
FREQUENCY (Hz)
50
II I
pU,J,U
~~'= ~5~6'
70
TA" 25°C
10k
25
MAXIMUM OUTPUT VOLTAGE
V8 LOAD RESISTANCE
5
1k
0
TEMPERATURE (OC)
3
I: .
80
100
-25
100
\
90
10
t--
'(
1. OP-06G
2. OP-OSA, OP-06B, OP-06E
OP-06F (OOC TO 70°C)
3. ALL GRADES
NO
COMPENSATION
~ ~
1
VS" ±16V
l"'-
I"'- ,..,..-}
I
I
PSRR VI FREQUENCY
(OP-06B, OP-06E)
90
70
~
~
,I ±3V
rc)
120
I
80
1000
lOa
.........
-..,.,
o
25
50
TEMPERATURE
~±l.V
1-""'"
~1P-06El
r- --
FREQUENCY
I
I
I
10
I
OP·06G
0.1
II
0.1
INPUT BIAS CURRENT
vs TEMPERATURE
~OS~
~
IOP.06G •
OP·06G
11111111
0.01
TIME (HOURS)
"- .LJ-
OP-OSA, OP-OSB, OP-06E, OP-OSF
120
III~[
-S
0,001
1
0,4
0.6
0.8
1.0
1.2
UNTRIMMED OFFSET VOLTAGE Vas (mV) (CURVES
ARE SYMMETRICAL ABOUT ZERO FOR VOS < 0)
V8
~
WARM·UP DRIFT ERROR BAND
Vs' ±16V=
02
CMRR
r-I
LONG TERM DRIFT
ERROR BAND
(NON·CUMMULATIVE)
60
V
.Y
06
-1.0
i
l"i-"
OFFSET CURRENT
VB TEMPERATURE
....
.R'i lOt'
Ap·2Okn
.............. 1--., I-
...
Vs "'±15V
TEMPERATURE (OC)
0
..... 1--" ~
11111111
g
~
son
10
to.•
~
~
OP-06E--/
Vs" ±16V
Rp" SkU
a:o
VOs~20~VATT"O " HOURS
3
2
-
RS"
1.0
~
"~
~
":ll: -3
- OP·OSA
TRIMMED OFFSET VOLTAGE
DRIFT AS A FUNCTION OF
TRIMMING POTENTIOMETER
(Rp) SIZE AND Vos
isfa
-
I-
~~~~R ~JJ~~I,I~s ~u ~~~ID~~~I~~.IOI
~w
w
a 25 50 75
TEMPERATURE (DC)
-25
0. 1
~
-I"- OP.OS,:--I
i I
o
'ill
-50
-Or
i
~\ /AV
"-\ //7
-75
-
- r- OP.06G
i
/ J
1/ il 1/
CD ~~ /
L I).!.!
/~
\
1.0
1
V
/
2. OP-06E
3. OP·06G
4. OP·O C
20
tt
VS .. :t15V
OFFSET VOLTAGE DRIFT
WITH TIME
OFFSET VOLTAGE
V8 TEMPERATURE
60
10
1
2
3.
4.
5
100
C1
C1
C1
C1
R2
C1
R2
1k
10k
FREQUENCY (Hz)
100k
1M
100
TA = 2SoC
Vs '" ±15V
VIN" ±10mV
I 11111
10k
1k
LOAD RESISTANCE TO GROUND (n)
0.OO1pF, R1 .. 47051 FROM PIN 5 TO V0.1pF, R1 '" 5R TO V0.OO1pF: R1 = 470R FROM PIN 5 TO GND
0.05pF, R1 = 100, C2 = OD2pF,
39.11 TO V0.05pF, R1 = 10.11, C2 = O.02pF,
39.11 TO GND
5·48
1/86, Rev. A
---------I~ OP·06 HIGH·GAIN INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE NOISE DENSITY
VI FREQUENCY
INPUT WIDEBAND NOISE
VI BANDWIDTH
1000
NOISE FIGURE VI
SOURCE RESISTANCE
12
'00
;:: (O,Q1Hz TO FREQUENCY INDICATED)
R, • 470n, C, • o.oO'.F TO
_
~
~
oz
-
RS" 10kn
r-N.
RS" 0
_
III
'Hz
!
~
~
V
1.0
10Hz
10
0.'
'k
100
FREQUENCY (Hz)
OPEN·LOOP GAIN
TEMPERATURE
E
~
lk
10k
SOURCE RESISTANCE (n)
OPEN·LOOP GAIN VB
SUPPLY VOLTAGE
MAXIMUM OUTPUT SWING
VB FREQUENCY
'0
Ll
20
!: 16
~
,,12
II
J
II
1\
J
11
;
*
~ 4
106
,oS
L-_"-_"-_.l-_..!..._..!...--J
-80
-40
0
40
80
120
160
TEMPERATURE (OC)
0
IAT lVD,IFF
I.-
o
I\
0
,1, ~V. I
"30nA, OP-OSB/A/F
"40nA, OP-06G ONL~
1\
V
o
±S
±10
:1:15
±20
POWER CONSUMPTION
SUPPLY VOLTAGE
-30
'00
'0
'25
~
V
J 1
J 1
J J
v
-'0
20
01 FFERENTIAL INPUT VOLTAGE (VOLTS)
'M
~:: ;~;~-20
"- f"."
b-"
/
=---
t:::::::
30
30
TA " 25°C
I
i I I
'0
20
30
40
60
60
TOTAL SUPPLY VOLTAGE, V+ TO V- (VOLTS)
5·49
~~N"(~~5~1"
.1 .1
-10mV,_
1 1
VIN (PIN 3) '" +10mV, _
Vo '" -16V
20
'0
',000
lOOk
46
,
-10
~
JJ"'-.
OUTPUT SHORT·CIRCUIT
CURRENT
VB
1000
GAIN ..
'00
~
1k
10k
FREQUENCY (Hz)
t-
1/
-20
GAIN ..
SUPPLY VOLTAGE (VOLTS)
INPUT BIAS CURRENT VB
DIFFERENTIAL
INPUT VOLTAGE
V
GAIN - 10,000
GAIN'"
::>
V
~~
-, 0
lOOk
o
~
o
./"'"
r06~~§§
-30
-30
GAIN .. 1
E24
i.--'""'
~
-20
'00
lOOk
VA - 2SOC
~
z
10k
2.
'07
100Hz
1kHz
BANDWIDTH (Hz)
lk
VB
'07~m
Vs" ±15V
I--
Jd'1
~
TA " 26°C
10
VS" ±1SV
1.
~
TA" 26°C
I
1.0
1.0
ill
'0
---
Rs·60kn
ISii
v-
~
,0
'6
o
,
1 1 1 1-
TIME FROM OUTPUT BEING SHORTED (MINUTES)
1/86, Rev. A
---------I~ OP-06 HIGH-GAIN INSTRUMENTATION OPERATIONAL AMPLIFIER
GUARANTEED PERFORMANCE CHARACTERISTICS
l
~
g
.fa
~..
~
10
~
OP.()8B
, -sSOC TO 125°C
~
1.0
~
S
y UNTRIMMED -5S0c TO 125°C
0.1
ill
II IIIII U-
~
ill
W TRIMMED -66°C TO 12SOC
::E 0.01
100
~
c
."'
Y UNTRIMMED
0.1
II IIIII
II
lk
10k
SOURCE RESISTANCE, Rt {OJ
~
II lIill
0
II III
:e
tOOk
0.01
100
Wn ij'lutTtl1
lk
10k
tOOk
SOURCE RESISTANCE, Rt (n)
op·06G
OOc TO 7efC
Y UNTRIMMED OOc TO 7fPC
1.0
These graphs depict maximum error
referred to the Input as a function of
source resistance (R, I. Curves Ware
shown with Vos trimmed at +25'C and
include errors due to Vos and los over
the indicated temperature range. Curves
Y and Z plot maximum errors with Vos
not trimmed.
Z UNTRIMMED 2&oC
0.1
ill
W TRIMMED DoC TO 70°C
"" =t
X
"
"
~
"~
lk
10k
SOURCE RESISTANCE, Rt (0)
0:
0:
*.
/
!
0.1
10
~
.fil
i
1111
100
>-
~
0:
0:
W TRIMMED -55"C TO 126°C
::I 0.01
tOOk
: Z UNT~I~~~.~ 2.'C .
$
126°C
I IIIII
UNT~'MMED ----------.I-l
......
.....
18
24
15
mW
~
0......
~
>.I-l
p.,
COMPENSATION CIRCUITS
0
ALTERNATE
R2
STANDARD
R2
R1
R1
OUTPUT
R3
OUTPUT
R3
Cf;;' Rl ~lR2 Co
CS'" 100pF
Co '" 30pF
IMPROVES REJECTION OF POWER
SUPPLY BY A FACTOR OF TEN
OFFSET VOLTAGE TEST CIRCUIT
BURN-IN CIRCUIT
200kn
>--""'--0 Va
5-63
1/86, Rev. A
!fHD
OP-08 PRECISION LOW-INPUT-CURRENT OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs = ±15V for G Grade and Vs = ±20V for
otherwise noted.
Grade,
E
Ooe:5 TA:5
OP-OSE
PARAMETER
SYMBOL
Input Offset Voltage
Vos
Average Input
Offset Vollage
Drift
TCVos
Input Offset Current
los
Average Input
Offset Current
Drift
TClos
CONDITIONS
MIN
(Note 1)
(Note 1)
Input Blal CUrrent
Is
Input Voltage Range
IVR
Vs· ±15V
Common-Mode
Rejection Ratio
CMRR
VOM - ±13.5V
Power Supply
Rejection Ratio
PSRR
Vs-UVto±15V
+70 o e, unless
OP-OSG
TYP
MAX
TYP
MAX
UNITS
0.10
0.26
0.32
1.4
mV
0.50
2.5
1.5
10
p.V/'C
0.08
0.30
0.12
6.5
nA
0.50
2.5
2.0
50
pAl'C
1.0
2.6
1.4
8.5
nA
MIN
±13.5
±14.0
±13.5
±14.0
V
100
118
80
112
dB
2
10
3
100
/AVIV
RL~2kO,
Large-Signal
Voltage ' ,
,I
y, ,CS = 'OOO~""""
I
80
,. r-....
20
'20
240
b,j.,
INPUT BIAS CURRENT
AND INPUT OFFSET CURRENT
VB TEMPERATURE
OPEN-LOOP GAIN
VB SUPPLY VOLTAGE
'=2.·C
015
0'0
40
20
,.
005
90
10M
l- t- I--
-55°C
I-"'i:'"
100
--
"0
±tS
SUPPLY VOLTAGE (VOLTS)
5-86
'20
o
J""-.. ........
-55 -35 -15
5
25
46
65
85
105
125
TEMPERATURE (OC)
1/86, Rev. A
---------I~ OP-08 PRECISION LOW-INPUT-CURRENT OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT
vs SUPPLY VOLTAGE
POWER SUPPLY
REJECTION RATIO (PSRR)
va FREQUENCY
SUPPLY CURRENT
vs TEMPERATURE
600
600 . - . . , - - , - , - - . . . , - ; - , - - - , - - , - - ,
NO LOAD
NO LOAD
500
<
..:;. 400
>-
~
a
300
;
-55':;'"
t
ffi
400
II-t;:;f-::t:+=+~~JII
200
I--+-+-t---+--+-t---+--+-I
~
::>
"~
125°C
~
iii
<
25"C
l---- r-
~
200
100
'5
±10
±15
±20
SUPPLY VOLTAGE (VOLTS)
o~~~-~~-=~~~~~
___
5
~
~
~
~
1~
-20 ' - - - ' - - - ' - - - ' - - - - ' - - - - '
100
1~
11<
10k
APPLICATIONS INFORMATION
100k
1M
10M
FREQUENCY (Hz)
TEMPERATURE (OC)
TYPICAL APPLICATION
The op-oa series has very low input offset and bias currents;
the user is cautioned that printed circuit board leakage
currents can produce significant errors, especially at high
board temperatures. Careful attention to board layout and
cleaning procedure is needed to take full advantage of the
oP-Qa performance. Board leakage is minimized byencircling
the input pins with a guard ring maintained at the same
potential as the inputs. This guard ring should be driven by a
low impedance source, such as an amplifier's output
or ground.
BILATERAL CURRENT SOURCE
R2
2Me!
Rl
4M51
R3
':"
4Me!
RS«A3
RS
lke!
RS
~'L
3Op'
R4
2Me!
'VE
RL
ER,
IF Rl=R3 AND R2=R4+R5 THEN
RaRs
IL IS INDEPENDENT OF VARIATIONS
IN RL
'LS!'':"
5-67
1/86, Rev. A
OP-09/0P-ll
QUAD MATCHED
741-TYPE OPERATIONAL AMPLIFIERS
Prcci sion Monolithics Inc.
fier is designed to have equal positive-going and negativegoing slew rates. This is an important consideration for good
audio system performance.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Guaranteed Vos ......•.............•..... SOOI'V Max
Guaranteed Matched CMRR ................ 94dB Min
Guaranteed Matched Vos .................. 7S0l'V Max
RC/RM4136 Direct Replacement (OP-09)
LM148/LM348 Direct Replacement (OP-11)
Low Noise
Silicon-Nitride PasslYatlon
Internal Frequency Compensation
Low Crossoyer Distortion
Continuous Short-Circuit Protection
Low Input Bias Current
Each of the four amplifiers has the proven OP-02 advantages
of low noise, low drift, and excellent long-term stability. Precision Monolithics' exclusive Silicon-Nitride "Triple Passivation" process reduces "popcorn noise", provides high reliability, and assures long-term stability of parameters.
The OP-09 and OP-11 are ideal for use in designs requiring
minimum space and cost while maintaining OP-02-type
performance.
OP-09's and OP-11's with processing per the requirements of
MIL-STD-883 are available. For dual-741-type versions, see
the OP-04/14 data sheet.
ORDERING INFORMATIONt
TA = 25°C
VosMAX
(mY)
HERMETIC
DIP
14-PIN
05
OP-09AY'
OP-llAY'
0.5
OP-09EY
OP-llEY
2.5
OP-09BY'
OP-llBY'
25
OP-09FY
OP-lIFY
5.0
OP-l1CY'
50
OP-lIGY
EPOXY
DIP
14·PIN
LCC
OPERATING
TEMPERATURE
RANGE
OPI1AAC/883
OP-lIEP
PIN CONNECTIONS
OP-09
MIL
OP-11
COM
MIL
OP-09FP
OP·l1FP
COM
OP-llGP
COM
MIL
14-PIN HERMETIC DIP (V-Suffix)
EPOXV DIP (P-Suffix)
'For devices processed In total compliance to MIL-STD-883, add 1883 after
part number. Consult factory for 883 data sheet
tAli commerCial and Industrial temperature range parts are available with
burn-In. For ordering information see 1986 Data Book, Section 2.
GENERAL DESCRIPTION
The OP-09 and OP-11 provide four matched 741-type operational amplifiers in asingle 14-pin DIP package. The OP-11 is
pin compatible with the LM148, LM348, RM4156, and HA4741
amplifiers. The OP-09 is pin compatible with the RM4136 and
RC4136. The amplifiers are matched for common-mode
rejection ratio and offset voltage which is very important in
designing instrumentation amplifiers. In addition, the ampli-
OP-11ARC/883
LCC
(RC-Sufflx)
"z
SIMPLIFIED SCHEMATIC (One 01 Four Amplifiers Is Shown)
(-lIN
(+)INo--t-------+---'
'----J--+--+-o OUTPUT
5-68
1/86, Rev. A
----------I~ OP-09/0P-11 QUAD MATCHED 741-TYPE OPERATIONAL AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS (Note 2)
Supply Voltage .•.••......•......••••..•.......... ±22V
OP-09GR and OP-11GR (Only) ...........•...... ±18V
Internal Power Dissipation (Note 1)
RC, V-Package ............................... 800mW
P-Package ................................... 500mW
Differential Input Voltage .............•.........•.. ±30V
Input Voltage .........•.....••.......•... Supply Voltage
Output Short-Circuit Duration ....•...•...... Continuous
(One Amplifier Only)
Storage Temperature Range
RC, V-Package ..................... -65·C to +150·C
P-Package ......................... -65·C to +125·C
Lead Temperature Range (Soldering, 60 sec) ...... 300· C
DICE Junction Temperature (Tj ) ••••• -65· C to + 150· C
OP-11A,OP-11B,
OP-11C,OP-11ARC ................. -55·C to +125·C
OP-11E, OP-11F, OP-11G ................ 0·Cto+70·C
NOTES:
1.
See table for maximum ambient temperature and derating factor.
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
14-Pm Hermetic DIP (YI
70'C
10.0mW/'C
14-Pm Plastic DIP (PI
42'C
SmW/'C
LCC (RCI
70'C
7.8mW/'C
PACKAGE TYPE
2
Operating Temperature Range
OP-09A,OP-09B .........•......•.• -55·C to +125·C
OP-09E,OP-09F ....•.........•.•....... o·e to +70·e
Absolute maximum ratingsapply to both DICE and packaged parts. unlesa
otherwise noted.
~
~
j:.l..j
.....,
::l
p.,
MATCHING CHARACTERISTICS at Vs = ±15V, TA = +25·e, Rs S 100n, unless otherwise noted.
OP-09A, OP-09E
OP-11A,OP-11E
PARAMETER
SYMBOL
Input Offaet Voltage Match
~Vos
Common-Mode Rejection
Ratio Match
~CMRR
CONDITIONS
MIN
VcM =±12V
VcM =±12V
Q4
TYP
MAX
0.5
~
OP-09a, OP-09F
OP-11a, OP-11F
MIN
TVP
MAX
0.75
0.8
2.0
mV
20
1
120
20
I'VIV
dB
120
Q4
UNITS
O·C S TAS +70·e for OP-09E, OP-09F, OP-11 E and OP-11 F, RsS 100n. unless otherwise noted.
SYMBOL
Input Offset Voltage Match
~Vos
Common-Mode Rejection
Rallo Match
~CMRR
CONDITIONS
V cM =±12V
V cM =±12V
-
OP-09a, OP-09F
OP-11a,OP-11F
MIN
MIN
Q4
5-69
---~."-~
OP-09A, OP-09E
OP-11A,OP-11E
TVP
MAX
TYP
MAX
O.S
1.0
1.0
2.5
mV
3.2
110
20
3.2
110
20
I'ViV
dB
94
~
~
MATCHING CHARACTERISTICS at Vs= ±15V. -55·e S TAS +125·e for OP-09A, OP-09B, OP-11A and OP-11B,
PARAMETER
~
9
UNITS
1/86, Rev. A
~ OP·09/0P·11 QUAD MATCHED 741·TYPE OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS (Each Amplifier) at Vs = ±15V TA = 25°C, unless otherwise noted.
OP·09A1E
OP·11A1E
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
RsS tOkO
Input Offset Current
Input BIas Current
TYP
MAX
0.3
los
MAX
TYP
MAX
UNITS
0.5
0.6
2.5
t.2
5.0
mV
55
20
25
50
75
200
nA
Is
180
300
300
500
300
500
nA
Input ReSIstance
DifferentIal Mode
R'N
017
0.29
0.1
0.17
0.1
017
MO
Input Voltage Range
IVR
±12
±13
±12
±13
±12
±13
V
Common-Mode
Rejection Ratio
CMRR
VcM =±12V, RsS 10kO
100
120
100
120
70
100
dB
Power Supply
RejectIon Ratio
PSRR
Vs = ±5 to ±15V,
RsS 10kO
4
MIN
OP·11C/G
TYP
(Note3)
MIN
OP·09B/F
OP·11B/F
32
4
MIN
10
32
100
"VIV
Output Voltage Swing Vo
RL ,,2kO
±11
±13
±11
±13
±11
±13
V
Large-Signal Voltage
GaIn
Avo
RL S2kO, Vo =±10V
100
650
100
650
50
500
V/mV
Power Consumption
(Note 1)
Pd
Vo=OV
105
0.7
0.7
07
"VI!:~
18
14
12
18
14
12
18
14
12
nVl..;HZ
Input Noise Voltage
180
123
180
210
340
mW
enf:!-~
0.1 Hz to 10Hz
Input Noise Voltage
Density
en
fo= 10Hz
fo= 100Hz
fo= 1000Hz
Input Noise Current
'np-p
o 1Hz to 10Hz
Input NOIse Current
Density
In
fo= 10Hz
fo= 100Hz
fo= 1000Hz
Channel SeparatIon
CS
100
130
100
130
130
dB
Slew Rate (Note 2)
SR
07
10
0.7
1.0
0.7
10
VI"s
Va = 20V p_p
11
16
11
16
11
16
kHz
BW
AVCL =+1.0
2.4
3.0
2.4
30
2.4
3.0
MHz
Rlsetime (Note 2)
tr
Av = +1, V ,N = 50mV
Overshoot (Note 2)
OS
Large-Signal
Bandwidth (Note 2)
Closed-Loop
Bandwidth (Note 4)
17
17
17
pA~_~
1.8
1.5
1.2
1.8
1.5
1.2
1.8
15
12
pAl..;HZ
110
145
110
145
110
145
ns
15
25
15
25
15
25
%
NOTES:
1. Total dissipation for all four amplifiers in package
2. Sample tested.
3. Guaranteed by Input bIas current.
4. Guaranteed by ,"setlme.
5·70
1/86, Rev. A
---------l~ OP-09/0P-11 QUAD MATCHED 741-TYPE OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS (Each Amplifier) at Vs = ±15V, -55° C:'S TA:'S +125° C, unless otherwise noted.
OP-09B
OP-11B
OP-09A
OP-11A
PARAMETER
SYMBOL
Input Offset Voltage
Vas
Average Input Offset
Voltage Drift (Note 3) TCVos
Input Offset Current
MIN
CONDITIONS
Rs $10kn
los
Average Input Offset TCI
Current Drift (Note 3)
as
Input Bias Current
Input Voltage Range
IVR
Common-Mode
Rejection Ratio
CMRR
VCM =±12V,
PSRR
Vs = ±5 to ±15V,
Rs $10kn
Ava
R L ;"2kn, Vo =±10V
Power Supply
Rejection Ratio
Large-Signal
Voltage Gain
Rs
$10kn
Output Voltage SWing Va
Power Consumption
TYP
MAX
UNITS
1.0
10
35
15
60
mV
10
40
15
40
04
20
MIN
jJ.V/'C
20
40
40
60
250
300
0.1
03
0.3
0.6
03
06
200
375
400
650
400
800
nA
nA
±12
±13
±12
±13
±12
±13
V
100
120
100
120
70
100
dB
32
32
10
100
50
250
50
250
25
100
V/mV
±11
±13
±11
±13
±11
±13
v
115
Vo=OV
(Note 1)
MAX
MAX
MIN
OP-11C
TYP
TYP
115
200
200
250
400
mW
ELECTRICAL CHARACTERISTICS (Each Amplifier) at Vs = ±15V, DOC:'S TA:'S +7DoC, unless otherwise noted.
OP-09E
OP-11E
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
Average Input Offset
Voltage Drift
TCVos
Input Offset Current
los
MIN
TYP
MAX
Rs $10kn
0.4
Rs $10kn
Average Input Offset
Current Drift (Note 3) TClos
Input BIBS Current
Input Voltage Range
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
Large-Signal
Voltage Gain
IVR
CMRR
VCM =±12V,
PSRR
Vs = ±5 to ±15V,
Rs $10kn
Rs
$10kn
Ava
Output Voltage Swing Va
Power Consumption
(Note 1)
OP-09F
OP-11F
Vo=OV
MIN
OP-11G
TYP
MAX
MIN
0.8
08
30
TYP
MAX
UNITS
1.5
60
mV
2.0
10
4.0
15
4.0
14
30
40
60
250
300
nA
01
03
03
06
0.3
06
nA/'C
200
350
400
550
400
600
nA
±12
±13
±12
±13
±12
±13
V
100
120
100
120
70
100
dB
4
32
32
10
100
50
250
50
250
25
100
V/mV
±11
±13
±11
±13
±11
±13
V
115
200
115
200
250
400
mW
NOTES:
Total diSSipation for all four amplifiers in package.
2
Sample tested.
3.
Guaranteed but not tested.
5-71
1/86, Rev_ A
---------I1fMD
DICE CHARACTERISTICS
OP-08l0P-11 QUAD MATCHED 741-TYPE OPERATIONAL AMPLIFIERS
(125° C
TESTED DICE AVAILABLE)
OP-09
OP-11
1.
2.
3.
4.
5.
6.
1.
2.
3.
4.
5.
6.
7.
OUTPUT (A)
INVERTING INPUT (A)
NONINVERTING INPUT (A)
V+
NON INVERTING INPUT (B)
INVERTING INPUT (B)
OUTPUT (B)
B. OUTPUT (C)
9. INVERTING INPUT (C)
10. NONINVERTING INPUT (C)
11. V12. NON INVERTING INPUT (0)
13. INVERTING INPUT (D)
14. OUTPUT (D)
15. V+
INVERTING INPUT (A)
NONINVERTING INPUT (A)
OUTPUT (A)
OUTPUT (B)
NONINVERTING INPUT (B)
INVERTING INPUT (B)
7. VB. INVERTING INPUT (C)
9. NON INVERTING INPUT (C)
10. OUTPUT (C)
11.
12.
13.
14.
15.
V+
OUTPUT (0)
NONINVERTING INPUT (0)
INVERTING INPUT (D)
V+
DIE SIZE 0.085 X 0.070 Inch, 5950 sq. mill
(2.16 X 1.78 mm, 3.84 sq. mm)
DIE SIZE 0.085 X 0.070 Inch, 5950 sq. mill
(2.16 X 1.78 mm, 3.84 sq. mm)
NOTE:
Ellher or both V+ pads may be used without any change In performance.
For addilional DICE Information refer to
1986 Data Book, Section 2.
WAFER TEST LIMITS at Vs= ±15V, T A =25°C for OP·09/11N, OP·09/11G and OP·09/11GR devices; TA=125°C for
OP·09/11 NT and OP·09/11 GT devices, unless otherwise noted.
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Input Offset Current
los
Input Bias Current
Ie
Input Voltage Range
IVR
OP-09NT
OP-11NT
OP-09N
OP-11N
OP-09GT
OP-11GT
OP-11G
OP-09GR
OP-11GR
LIMIT
LIMIT
LIMIT
LIMIT
LIMIT
UNITS
1.0
0.5
3.5
2.5
5.0
mVMAX
RsS 10kO
20
20
50
50
200
nAMAX
300
300
500
500
500
nAMAX
±12
±12
±12
±12
±12
VMIN
100
100
100
100
70
dBMIN
32
32
32
32
100
I'VNMAX
Common-Mode
Rejection Ratio
CMRR
VcM =±12V
RsS 10kO
Power Supply
Rejection Ratio
PSRR
Vs =±5Vto±15V
RsS 10kO
Output Voltage Swing
Vo
RL 210kO
RL =2kO
±11
±11
±12
±11
±11
±11
±12
±11
±11
±11
VMIN
Avo
RL22kO
Vo =±10V
50
100
50
100
50
V/mVMIN
Pd
VOUT=O
No Load
200
ISO
200
ISO
340
mWMAX
Large-Signal
Voltage Gain
Power Consumption
(Four Amplifiers)
NOTES:
For 25°C characteristics of NT & GT devices, see N & G characteristics, respectively.
Electrical tests are performed at wafer probe to the limits shown. Due to variations In assembly methods and normal yield loss, yield after packaging Is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS at
PARAMETER
SYMBOL CONDITIONS
Slew Rate
SR
Unity Gain Bandwidth
GBW
Channel Separation
CS
Vs
=±15V, TA =+25°C, unless otherwise noted.
OP-08NT
OP·11NT
OP-08N
OP-11N
OP·09GT
OP-11GT
OP-11G
OP-09GR
OP-11GR
TYPICAL
TYPICAL
TYPICAL
TYPICAL
TYPICAL
UNITS
2
2
2
2
2
MHz
130
130
130
130
130
dB
Av=1
RL 22kO
Av= 100
f= 10kHz
Rs= lkO
VI"s
S-72
1/86, Rev. A
----------1~ OP·09/0P·11 QUAD MATCHED 741·TVPE OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT OFFSET VOLTAGE
VI TEMPERATURE
BIAS CURRENT VI
TEMPERATURE
OFFSET CURRENT VI
TEMPERATURE
300
-0.10
~w
i
~
o
... ~
-0.20
-030
,
...... ......
~
r-.... ~
-0.40
-0.60
-80 -40 -20
0
20
40
60
.;'~
.....
......
0
-60 -40 -20
80 100 120 140
.....
......
0
20
40
80
80 100 120 140
1.4
\
~
PH~i
eo
I
\
GAIN
I
I-- -
\
.....
\
VS" :t16V
TA-+25"C
20
-<10 -20
0
20
40
eo eo
o
100 120 140
0.1
TEMPERATURErC)
OPEN·LOOP GAIN V8
SUPPLY VOLTAGE
BOO
TA'+25l C
700 -RL-2kn
/'
600
~ 500
V
2
:c
400
~300
~
1.0
10
100
1k
10k
100k
13
e5l
1.2
0:
f5
1. 1
90
w
10
\,
\
\
~
45
136
\
RL- 2k
CL"00pF
o
15
-80 -40 -20
~
'"~
eo
VS'" ±15V
RL -2kO -
I
!-"-
100
100
~
o
80 100 120 140
NORMALIZED SLEW RATE
AND BANDWIDTH
VI TEMPERATURE
200
"
"""
100
OPEN-LOOP GAIN AND PHASE
VI FREQUENCY
40
!
t
60
",
iii
I-
40
...... ~
""~
",
OPEN·LOOP GAIN VI
TEMPERATURE
I
-eo
1I
-~~
200
TEMPERATURE (OC)
/
300
20
~
0:
0:
TEMPERATURE (OC)
120
400
0
1
TEMPERATURE (OC)
700
&00
~
", ~
800
600
V~""5V
IV
)±15J
vl . t}sv
BO
~
~>
~
I
CMRR
-
0.7
80
0:
0:
i!i
--80 -40 -20
10M
FREQUENCY
11111111111
120
VS'"±15V
r-...
TA '" 25°C
100
,
I
I
80
i
60
20
20
o
o
10
100
----
._-------
1k
FREQUENCY (Hz)
5·73
._.
-
111111111
Vs" :t15V
TA '" 25°C
i
60
1.0
0 20 40 80 aD 1ao 120 140
TEMPERATURE I·C)
PSRR VI FREQUENCY
100
20
.....
140
120
j
",
BANDWIDTH " -
O.B
1M
140
100
/
V8
SLEW RATE
"-
FREQUENCV (Hz)
/
6
10
1&
POWER SUPPLY VOLTAGE "VI
~~
08
40
o
Va· :t16V
0.9
40
200
....
1- ~
10k
lOOk
o
1.0
10
100
1k
FREQUENCY IH.I
10k
101M<
1/86, Rev. A
-----------1m
OP-09/0P-11 QUAD MATCHED 741-TYPE OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CHARACTERISTICS
CHANNEL SEPARATION va
FREQUENCY
NOISE CURRENT DENSITY
va FREQUENCY
NOISE VOLTAGE DENSITY
va FREQUENCY
1000
V S .. ;t16V
TA=+2!1'C
INPUT~V1
10kf.!
CS -20109 1DOV,
~_
r--
?
Vz
VZ
1
100
1k
10k
lOOk
01
10
FREQUENCY (Hz)
L--L~Llllli-~-L~WL__LL~Uill
10
"'"
100
1k
FREQUENCY (Hz)
1k
10k
FREQUENCY (Hz)
MAXIMUM OUTPUT SWING
va FREQUENCY
VOLTAGE FOLLOWER
PULSE RESPONSE
TRANSIENT RESPONSE
100
28
~
+20
~
";:
~(::
3
V S =±15V
TA =+2SOC
\
~ 20
1
IIIII
1\
.
2
RL .. 2k.!l
o
0
~ 16
~-1
~w
....
~-2
~-3
-20
I
,.
~
g8
5
200
400
2
800
4
8
8
10
TIME
TIME (ns)
12
14 18
,8
5o 4
~
(~sl
~f....
o
OUTPUT VOLTAGE va
LOAD RESISTANCE
lOOk
FREQUENCY (Hz)
---
POSITIVE SWING
I(
Ij
(
NEGATIVE SWING
I I I
Vs ~ ±16V
-
1/
-
I-:--
r-
-
Vs - ±16V
.......
.......
ffi
~
o
o
10
LOAD RESISTANCE TO GROUND (kSlI
III
TA '" +26°C
I
TA '" 2!i"C
~
0.1
POWER CONSUMPTION va
TEMPERATURE
QUIESCENT CURRENT VI
SUPPLY VOLTAGE
16
10
o
10
20
30
TOTAL SUPPLY VOLTAGE (VOLTS)
5-74
1M
10k
lk
.......
r-.
110
100
--60 ....0 -20
0
20
40
80
80
100 120 140
TEMPERTURE I-C)
1/86, Rev. A
OP-IO
DUAL MATCHED INSTRUMENTATION
OPERATIONAL AMPLIFIER
Prec ISlon 1\1011olIthH'::s Inc
FEATURES
•
•
•
•
•
•
•
•
•
•
•
is provided between channels of the dual operational
amplifier.
Extremely Tight Matching
Excellent Individual Amplifier Parameters
Offlet Voltage Match ..................... O.18mV Max
Offset Voltage Match VI Temp •...•.•.•.. O.8p.V/ o C Max
Common-Mode Rejection Match .......•..• 114dB Min
Power Supply Rejection Match ....•..•.... 100dB Min
Blal Current Match ....................... 3.0nA Max
Low Nolle .............................. O.6p.Vp•p Max
Low Blal Current ......................... 3.0nA Max
High Common-Mode Input Impedance •... 200GO Typ
Excellent Channel Separation ...•.•....•.. 126dB Min
The excellent specifications of the individual amplifiers
and tight matching over temperature enable construction of
high-performance instrumentation amplifiers. The deSigner
can achieve the guaranteed specifications because the
common package eliminates temperature differentials which
occur in designs using separately housed amplifiers.
Matching between channels is provided on all critical parameters including offset voltage, tracking of offset voltage vs.
temperature, non inverting bias currents, and common-mode
and power-supply rejection ratios. The individual amplifiers
feature extremely low offset voltage, offset voltage drift, low
noise voltage, low bias current, internal compensation and
input/output protection.
ORDERING INFORMATIONt
TA=25°C
VosMAX
(mV)
HERMETIC
DIP
14-PIN
OPERATING
TEMPERATURE
RANGE
0.5
0.5
0.5
0.5
OP10AY'
OP10EY
OP10Y'
OP10CY
MIL
COM
MIL
COM
PIN CONNECTIONS
14-PIN CERAMIC DIP
(V-Suffix)
• For devices processed In total compliance to MIL-STD-883, add 1883 after
part number. Consult factory for 883 data sheet
tAli commercial and Industrial temperature range parts are available with
burn-In For ordering information see 1986 Data Book, Section 2.
GENERAL DESCRIPTION
NOTE:
Device may be operated even if insertion is reversed; this is due to
inherent symmetry of pin locations olampliliers A and B.
The OP-10 series of dual-matched Instrumentation operational amplifiers consists of two independent monolithic
high-performance operational amplifiers in a single 14-pin
dual-in-line package. Tight matching of critical parameters
SIMPLIFIED SCHEMATIC (1/2 OP-10)
V+o-----~--------~----~----_.------~--._----~------~----~~~--~--,
RS
OUTPUT
Rl0
+IN
-IN
-------+----<--------f,.,
O--'N'..-<........
v-o-------------~~--------------------~--+_--~~~~------4_--~--~
5·75
1/86, Rev. A
---------l~ OP·10 DUAL MATCHED INSTRUMENTAnON OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
DICE Junction Temperature (Tj) ••••••• -65'C to +150'C
Lead Temperature Range (Soldering, 60 sec) •••••• 300'C
Supply Voltage ••••••••••••••••••••••••••••••••••• ±22V
Internal Power Dissipation (Note 1) •••••••••••••• 500mW
Differential Input Voltage •••••••••••••••••••••••••• ±30V
Input Voltage (Note 2) •••••••••••••••••••••••••••• ±22V
Output Short·Circuit Duration ••••••••••••••••• Indefinite
Storage Temperature Range ••••••••••• -65'C to +150'C
Operating Temperature Range
Op·10A,OP-10
-55'C to +125'C
.....................
at Vs
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
Dual-in-Llne (V)
106'C
11.3mW/·C
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
2. For supply voltages less than +22V, the absolute maximum Input voltage Is
equal to the supply voltage.
OP-10E,OP·10C •••••••••••••••••••••••• O'C to +70'C
INDIVIDUAL AMPLIFIER CHARACTERISTICS
PACKAGE TYPE
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
= ± 15V, TA = 25' C, unless otherwise noted.
Op·10A
PARAMETER
SVMBOL
Input Offset Voltage
Vas
Long-Term Input Offset
Voltage Stability
<1VosfTlme
MIN
CONDITIONS
(Notes 1. 2)
OP·10
TVP
MAX
MIN
TVP
MAX
0.2
0.5
0.2
0.5
mV
0.25
1.0
0.25
1.0
",V/Mo
nA
UNITS
Input Offset Current
los
1.0
2.8
1.0
2.8
Input Bias Current
Ie
±1
±3
±1
±3
nA
Input Noise Voltage
enp-e
(Note 2) O.IHz to 10Hz
0.35
0.6
0.35
0.6
",Ve:e
Input Noise Voltage
Density
en
fo= 10Hz
(Note 2) fa = 100Hz
fo= 1000Hz
10.3
10.0
9.6
18.0
13.0
11.0
10.3
10.0
9.6
18.0
13.0
11.0
nVl../HZ'
Input Noise Current
Ine-e
(Note 2) O.IHz to 10Hz
Input Noise Current
Density
In
fo= 10Hz
(Note 2) fo = 100Hz
fo= 1000Hz
Input Resistance Differential-Mode
RIN
(Note 3)
Input Resistance Common-Mode
RINCM
20
14
30
14
30
pAe:e
0.32
0.14
0.12
0.80
0.23
0.17
0.32
0.14
0.12
0.80
0.23
0.17
pA/../HZ'
60
20
200
Input Voltage Range
IVR
Common·Mode Rejection
Ratio
CMRR
VCM =±13V
Power Supply Rejection
Ratio
PSRR
Vs = ±3V to ±18V
Large-Signal Voltage
Gain
Ava
RL" 2kll, Vo = ±10V
RL" soon, Vo = ±0.5V,
Vs = ±3V [Note 3)
Output Voltage Swing
Va
RL" 10kn
RL ,,2kO
RL"lkO
60
MO
200
GO
±13
±14
±13
±14
V
110
126
110
126
dB
4
10
4
10
p.VIV
200
500
200
500
150
500
150
500
±12.5
±12.0
±10.5
±13.0
±12.8
±12.0
±12.5
±12.0
±10.5
±13.0
±12.8
±12.0
V
VlmV
Slew Rate
SR
RL" 2kO
0.17
0.17
Vlp.s
Closed-Loop Bandwidth
BW
AVCL =+1.0
0.6
0.6
MHz
Open-Loop Output
Resistance
Ro
Vo=O.lo=O
80
Pd
Each Amplifier
Vs =±3V
90
4
Rp= 20kO
±4
±4
mV
8
8
pF
Power Consumption
Offset Adjustment Range
Input CapaCitance
C1N
NOTES:
1. Long·Term Input Offset Voltage Stability refers to the averaged trend line
of Vos vs. Time over extended periods after the first 30 days of operation.
Excluding the Initial hour of operation. changes in Vos during the first 30
operating days are typically 2.5",V - refer to typical parformance curves.
80
120
6
90
4
0
120
6
mW
2. Sample tested.
3. Guaranteed by design.
5·76
1/86, Rev. A
~
OP·10 DUAL MATCHED INSTRUMENTATION OPERATIONAL AMPLIFIER
INDIVIDUAL AMPLIFIER CHARACTERISTICS at Vs= ±15V, -55°C:5 TA:5 +125°C, unless otherwise noted.
Op·10A
PARAMETER
SYMBOL
Input Ollset Voltage
Vos
Average Input Ollset
Voltage Drift
Without External Trim
TCVos
TCVosn
With External Trim
Input OIIset Current
Average Input OIIaet
Current Drift
MIN
MAX
TVP
MAX
UNITS
0.3
0.7
0.3
0.7
mV
(Note 2)
0.7
2.0
0.7
2.0
,.V/oC
Rp= 20kO (Note 3)
0.3
1.0
0.3
1.0
,.VloC
1.8
5.6
1.8
5.6
nA
los
TClos
Input Bias Current
la
Average Input Blaa
Current Drift
TCl a
OP·10
TVP
CONDITIONS
(Note 2)
(Note 2)
I nput Voltage Range
IVR
Common·Mode Rejection
Ratio
CMRR
VcM =±13V
Power Supply Rejection
Ratio
PSRR
Vs=±3Vto±18V
Large-Signal Voltage
Gain
Avo
RL~
Output Voltage Swing
Vo
RL~2kO
MIN
8
50
8
50
pArC
±2
±8
±2
±8
nA
13
50
13
50
pA/oC
±13.0
±13.5
±130
±13.5
V
106
123
106
123
dB
loLl
5
2kO, Vo= ±10V
MATCHING CHARACTERISTICS at Vs =
±15V, TA = 25°C,
20
5
,.VN
20
150
400
150
400
VlmV
±12.0
±12.8
±12.0
±12.6
V
unless otherwise noted.
OP·10
PARAMETER
SYMBOL
TVP
MAX
TVP
MAX
UNITS
Input Offset Voltage
AVos
007
0.18
0.12
0.5
mV
Average Nonlnvertlng
Bias Current
la+
±1.0
±3.0
±1.3
±4.5
nA
Nonlnvertlng Offset
Current
Ios+
0.8
2.8
1.1
4.5
nA
Inverting Offset Current
loS-
0.8
28
1.1
4.5
nA
Common-Mode Rejection
Ratio Match
ACMRR
VcM =±13V
Power Supply Rejection
Ratio Match
APSRR
Vs =±3Vto ±18V
Channel Separation
CS
(Note 2)
CONDITIONS
MATCHING CHARACTERISTICS at Vs =
MIN
114
123
126
140
3
±15V, -55°C:5 TA:5 +125°C,
MIN
106
120
126
140
10
4
SYMBOL
Input Offset Voltage
Match
AVos
With External Trim
CONDITIONS
TCAVos
(Note 2)
TCAVosn
Rp = 20kO (Note 3)
Channel A only
MIN
NOTES:
1. Long-Term Input Ollset Voltage Stability refers to the averaged trend line
of Vos vs. Time over extended periods after the IIrst30 days of operation.
excluding the Initial hour of operation, changes In Vos during the IIrst30
operating days are typically 2.5"V - refer to typical performance curves.
-~
~
dB
,.VN
20
dB
OP·10
TVP
MAX
01
0.3
0.45
0.3
MIN
TVP
MAX
UNITS
0.2
0.9
mV
1.3
0.9
2.5
"VI"C
0.8
04
1.2
"VI"C
2. Sample tested.
3. Guaranteed by deSIgn
1/86, Rev. A
5·n
~-~---
~
unless otherwise noted.
Op·10A
PARAMETER
~
0
OP·10A
Input Offset Voltage
Tracking
Without External Trim
-2
ffi
~--~-
----------
--~-
--
-
-- - - -
~ OP·10 DUAL MATCHED INSTRUMENTATION OPERATIONAL AMPLIFIER
MATCHING CHARACTERISTICS at Vs =± 15V. -55°C ~ TA ~ +125° C. unless otherwise noted. (Continued)
OP·10A
PARAMETER
SYMBOL
Average Nonlnverting
Bias Current
IB+
Average Drift of
Nonlnvertlng
B,as Current
TCI B+
Noninvertlng Offset
Current
loot
Average Drift of
Nonlnvertlng
Offset Current
TClos+
MIN
CONDITIONS
(Note 2)
(Note 2)
Inverting Offset Current
los-
Common-Mode ReJeclion
Ratio Match
ACMRR
VcM =±13V
Power Supply Rejection
Rallo Match
APSRR
Vs = ±3V to ±18V
108
OP·10
TVP
MAX
±2.0
TVP
MAX
UNITS
±6.0
±2.4
±8.0
nA
10
40
15
2.0
6.5
2.4
12
50
18
2.0
6.5
2.4
120
6
MIN
103
pAl"C
9.0
pArC
9.0
117
20
nA
nA
dB
32
/LVIV
INDIVIDUAL AMPLIFIER CHARACTERISTICS at Vs =± 15V. TA = 25° C. unless otherwise noted.
Op·10E
PARAMETER
SYMBOL
Input Offset Voltage
Vos
Long-Term Input Offset
Voltage Stability
AVos/Time
Input Offset Current
los
Input Bias Current
IB
Input NOise Voltage
enp~p
Input Noise Voltage
Density
Input Noise Current
CONDITIONS
MIN
(Notes 1, 2)
OP·10C
TVP
MAX
TVP
MAX
UNITS
0.2
0.5
0.2
0.5
mV
0.3
1.5
0.5
MIN
/Lv/Mo
12
38
1.8
6.0
±1.2
±4.0
±1.8
±7.0
nA
(Note 2) O.IHz to 10Hz
0.35
0.6
0.38
0.65
/LV~_~
en
fo= 10Hz
(Note 2) fo = 100Hz
fo= 1000Hz
10.3
10.0
9.6
18.0
13.0
11.0
10.5
10.2
9.8
20.0
13.5
11.5
nV/..jHZ
In~-~
(Note 2) 0.1 Hz to 10Hz
Input Noise Current
Density
In
fo= 10Hz
(Note 2) fo= 100Hz
fo= 1000Hz
Input Resistance Differential-Mode
R'N
(Note 3)
Input Resistance Common-Mode
R'NCM
Input Voltage Range
IVR
Common-Mode Rejection
Rallo
CMRR
VCM =±13V
Power Supply Rejecllon
Ratio
PSRR
Vs =±3Vto±18V
Large-Signal Voltage
Gain
Avo
RL ;" 2kll. Vo = ±10V
RL ;" 5000, Vo = ±O 5V,
Vs = ±3V (Note 31
Output Voltage SWing
Vo
RL ;" 10kO
RL ;"2kO
RL ;"lkO
nA
14
30
15
35
pA~::E
0.32
0.14
0.12
0.80
0.23
017
0.35
0.15
0.13
0.90
0.27
0.18
pAl..jHZ
15
50
±13
±14
±13
±14
V
106
123
100
120
dB
8
160
4
20
33
MO
120
GO
10
200
500
120
400
150
500
100
400
±12.5
±12.0
±10.5
±13.0
±128
±12.0
±12.0
±11.5
±13.0
±12.8
±12.0
32
/LV/V
V/mV
NOTES:
1. Long-Term Input Offset Voltage Stability refers to the avereged trend line
of Vos vs. Time over extended periods after the IIrst30 days of operation.
Excluding the Inillal hour of operation, changes in Vosdurlng the IIrst30
operating days are typically 2.5/LV - refer to typical performance curves.
V
2. Sample tested
3. Guarantaed by design.
5·78
1/86, Rev. A
----------l~ OP-10 DUAL MATCHED INSTRUMENTATION OPERATIONAL AMPLIFIER
INDIVIDUAL AMPLIFIER CHARACTERISTICS at Vs= ±15V, QOC ~ TA~ +7QoC, unless otherwise noted. (Continued)
OP-10E
PARAMETER
SYMBOL
CONDITIONS
Slewing Rate
SR
RL<" 2kO
Closed-Loop Bandwidth
BW
Open-Loop Output
Resistance
Power Consumption
TYP
OP-10C
MAX
MIN
TYP
MAX
UNITS
0.17
0.17
V/~s
AveL =+10
0.6
0.6
MHz
Ro
Vo= 0.10= 0
60
60
0
Pd
Each Amplifier
Vs= ±3V
90
4
Rp= 20kO
±4
Offset AdJustment Range
Input Capacitance
MIN
120
6
95
4
150
8
±4
mW
mV
pF
C,N
INDIVIDUAL AMPLIFIER CHARACTERISTICS at Vs= ±15V, QOC ~ TA~ +7QoC, unless otherwise noted.
OP-10E
PARAMETER
SYMBOL
Input Offset Voltage
Vas
CONDITIONS
MIN
OP-10C
TYP
MAX
0.25
06
MIN
TYP
MAX
UNITS
0.35
1.6
mV
Without External Trim
TCVos
With External Trim
TCVOSn
Input Offset Current
los
Average Input Offset
CUrrent Drift
TClos
Input Bias Current
la
Current Dnft
Input Voltage Range
Common~Mode
Rejection
Ratio
Power Supply Rejection
Ratio
Large-Signal Voltage
Gain
Output Voltage Swing
i:2
~
......
~
::l
~
Average Input Offset
Voltage Drift
Average Input Bias
II
Rp= 20kO
(Note 2)
0.7
2.0
1.2
4.5
~V/oC
(Note 3)
0.3
1.0
0.4
1.5
~V/oC
1.4
53
2.0
8.0
nA
8
50
12
50
pA/oC
±15
±55
±2.2
±9.0
nA
13
50
18
50
pA/oC
(Note 2)
TCl a
(Note 2)
IVR
CMRR
VeM = ±13V
PSRR
Vs = ±3V to ±18V
Ava
RL<" 2kO, Vo= ±10V
Va
RL <" 2kO
±130
±135
±13.0
±13.5
V
103
123
97
120
dB
32
10
51
~VIV
100
400
100
400
V/mV
±12.0
±12.6
±11.0
±12.6
V
NOTES:
1. Long-Term Input Offset Voltage Stability refers to the averaged trend line
of Vas vs Time over extended penods after the first 30 days of operation.
Excludmg the initial hour of operation, changes in Vas during the first 30
operating days are typically 2.Sp.V - refer to tYPical performance curves.
2. Sample tested
3. Guaranteed by design
5-79
1/86, Rev_ A
~
~
0
......
~
~
~
0
IfHD
OP-10 DUAL MATCHED INSTRUMENTATION OPERATIONAL AMPLIFIER
MATCHING CHARACTERISTICS at Vs = ± 15V, TA = 25° C, unless otherwise noted.
OP·10E
PARAMETER
SYMBOL
CONDITIONS
MIN
OP·10C
TYP
MAX
MIN
0.5
TYP
0.3
mV
MAX
UNITS
Input Offsst Voltage
Match
AVos
0.12
Average Nonlnvertlng
Bias Current
Ie+
±1.3
±4.5
±2.0
nA
Nonlnvertlng Offset
Current
los+
1.1
4.5
1.a
nA
1.1
4.5
1.a
nA
117
dB
Inverting Offset Current
loS""
Common-Mode Aejectlon
Aatlo Match
ACMAA
VCM =±13V
Power Supply Aejectlon
Aatlo Match
APSAA
Vs=±3Vto±1av
Channel Separation
CS
(Note II
MATCHING CHARACTERISTICS at Vs= ±15V, DOC ~
106
120
20
126
TA$
p.VlV
140
120
SYMBOL
Input Offset Voltage
Match
t!.Vos
Input Offset Voltage
Tracking
Without External Trim
With External Trim
dB
+7DoC, unless otherwise noted.
OP·10E
PARAMETER
137
MIN
CONDITIONS
OP·10C
TYP
MAX
0.1S
0.7
0.4
MIN
TYP
MAX
UNITS
mV
TCAVos
(Note II
0.9
2.3
1.3
p.VI'C
TCt!.VOSn
AL = 20kO
Channel A Only (Note 21
0.3
0.9
0.6
p.VI'C
±2.0
±6.0
±2.S
nA
12
40
18
pAl'C
2.0
6.0
2.8
nA
pAl'C
Average Nonlnverting
Bias Current
18+
Average Drift of
Nonlnverting Bias Current
TCI 8+
Nonlnvertlng Offset
Current
18+
Average Drift of
Nonlnvertlng Offset Current
TClos+
(Note 11
(Note II
Input Offset Current
los-
Common-Mode Aejection
Aatlo Match
t!.CMAA
VcM =±13V
Power Supply Aejection
Aatlo Match
APSAA
Vs= ±3V to ±1aV
103
15
50
20
2.0
6.0
2.a
nA
114
dB
117
6
32
p.VIV
NOTES:
I. Sample tested.
2. Guaranteed by design.
5-80
1/86, Rev. A
--------100
OP·10 DUAL MATCHED INSTRUMENTATION OPERATIONAL AMPLIFIER
BURN·IN CIRCUIT
OFFSET NULLING CIRCUIT
V+
NC
14 I
20kn
,
14
'::- .....
3
;r
4
+18V 0 - -
13
>-+''''----<> OUT A
INPUT
N.C.
' -_ _-\,'c::.'_ _-oV_
12
-lav
QP·10
QP·10
5
~
11
l1 . .
10
";"
7 8
r---~---ov11
•
N,C.
>--~---oOUT B
INPUT
9
20kS1
N.C
V+
TYPICAL PERFORMANCE CHARACTERISTICS
MATCHING CHARACTERISTICS
TRIMMED OFFSET VOLTAGE
MATCH vs TEMPERATURE
40
=
r- Vas TRIMMED TO
+15V
-55 C TO +12S"C
VS'" ±15V
~
i<
~
I
100.11
OP-l0E
Vs'" ±15V
III
~
0
lOon
aOc TO 70"C
OP-l0A
Q
.§
UNTRIMMED
55"C TO
+12~C
-
III
~
~
UN~RI,JJJ~ O"c
I 11111111
10
UNTRIMMED 25°C
01
TRIMMED
~
TO 70"C
UNTRIMMED 2s<'C
I I LII V
1
sSOC TO +12!i"'C
~
~
INPUT REFERENCE NOISE '"
25~~O '" ~~.~b~ '" lOOnV/em
TRIMMED
x
~
~
I 11111111
001
II
II
lk
100
10k
00 1
100
TOOk
INPUT WIDEBAND NOISE
VB BANDWIDTH
(0.1 Hz TO FREQUENCY
INDICATED)
1000
10
AS1 - RS2 - 200kn
Vs - +15V
TA -+2S"C
THERMAL NOISE OF SOURCE
RESISTORS INCLUDED
~
EXCLUDED
t--.
100
'>
."!
w
w
~
0z
/
~
w
'"~
lOOk
10k
SOURCE RESISTANCE (n)
VOLTAGE NOISE DENSITY
VB FREQUENCY
~
I
lk
SOURCE RESISTANCE (.\1)
OP-10 LOW FREQUENCY NOISE
oCc TO 70°C
J I liW
~
10
0
>
--
5
z
~
RS'" 0
1.0
~
--
-V s = 15V
-Yf5°f
1
10
1.0
10
1
100
1k
100
BANDWIDTH (Hz)
OFFSET VOLTAGE DRIFT
WITH TIME
TYPICAL OFFSET VOLTAGE
STABILITY vs TIME
TOOk
10k
1k
FREQUENCY (Hz)
TRIMMED OFFSET VOLTAGE
VB TEMPERATURE
30
'>
'> 4I+HmFH11tIII~-mtltm-mttnC11'1't1III!C11'm1IIt-ij4111
."!
w
'"~
~
~
~
0
>
~
0
WARM-UP
0
DRIFT
LONG·TERM
ERROR
BAND
DRIFT
~0
15
l.I.
~
-3
~
-4
G -4rt~rH~rH~rH~rHffl$-Hffl$~,ffift
~
_6~~~~~~~~~~-W~-U~
10
10
5-82
100
lk
M
~
10k
:;
~
3)
2)
(3 /
\ \
w
-5
TIME (HOURS)
\
10
>
Vf~~~rH~rH~rH*I-H*I'
01
/
/
1
I
CD
w
:;
-2
0001001
I
-
0
ERROR BAND
-1
o
20
~
~j~ g~=~gc
3
>
~
-2
TIME (MONTHS)
'"~
Vas TRIMMED TO < 5J,1V AT 25"C
NULLING POT'" 20kn
1
1/20P-l0E
2
1/20P-l0A
f-25
0
2
f-
tl
."!
w
5
~
1 &l
10
IF
a
-75
-50
-25
25
50
75
100 125
TEMPERATURE (OC)
1/86, Rev. A
---------I~ OP-10 DUAL MATCHED INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
CMRR
130
IlllIi
'20
FREQUENCY
VB
PSRR
'20
Jllll!l~
1/20P-l0C
110
1/20P-l0C
90
t\
BO
80
70
~
~
1k
'00
_I
~
AV=10
20
~
0'
lOOk
'0
OPEN-LOOP GAIN
VB FREQUENCY
t--
I"
BO
60
40
1k
'00
'Ok
"- ~
-40
10
100
lk
lOOk
1M
10M
-
r-....
600
.........
r-....
200
o
±s
±10
:l:1S
±20
MAXIMUM OUTPUT VOLTAGE
vs LOAD RESISTANCE
20
-
r--
o
-75
-50
-25
25
75
100
POWER CONSUMPTION
POWER SUPPLY
125
VB
1000
TA =+2SoC
LoLI l1E
'5
50
TEMPERATURE (OC)
II II
TA=+2SJC
Vs = ±15V
VIN = ±10mV
=
Vs ±1SV
TA '" +25"C
20
'OM
200
MAXIMUM OUTPUT SWING
vs FREQUENCY
24
I.,...-
400
POWER SUPPLY VOLTAGE (VOLTS)
I-
\
1M
BOO
FREQUENCY (Hz)
2B
lOOk
Vs = ±15V
400
o
10k
1000
TA = +25~C
/f-""
10k
1k
'00
OPEN-LOOP GAIN vs
TEMPERATURE
600
""
"
10
OPEN-LOOP GAIN vs POWER
SUPPLY VOLTAGE
800
-20
"'-
-20
FREOUENCY (Hz)
Vs = ±15V
TA '" +25°C_
20
0'
'0
lOaD
~
~
FREQUENCY (Hz)
fREaUENCY (Hz)
'00
~
J
AV'" 100
60
'Ok
J±15V
AV=~
60
50
10
Vs
TA '" 2SoC
BO
AV=l
70
60
10
'00
40
90
,20
I'~~ = 25Jb'l
llllIJ
'00
100
CLOSED-LOOP GAIN
VB FREQUENCY
FREQUENCY
1;;JlliUI
~
110
VB
E
V
100
NEGATIVE SWING
'6
'0
'2
1\
o
1k
10k
lOOk
FREQUENCY (Hz)
'M
o
'00
1/,/
II
IL
10
1k
LOAD RESISTANCE TO GROUND (n)
5-83
10k
'0 o
I
20
40
60
TOTAL SUPPLY VOLTAGE, V+ TO V- (VOLTS)
1/86, Rev. A
--------I~ OP-10 DUAL MATCHED INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT BIAS CURRENT VI
DIFFERENTIAL INPUT
VOLTAGE
OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK
30
;;
-"
w
~g
IlL L I
IlL L L
25
.1
~ 15 - f -
!:
-~
10
~
w
~
< 6J,1V AT 25°C
~
-20
S1
a
~
V
V iL
10
~
~
~ -10
;:
~ -20
60
~
80
100
TIME (SEC)
,
/
ffi
DEVICE IMMERSED
IN 700C OIL BATH
40
Vs! ±15v'
- -c-
~
--_-0 OUTPUT
R3
2kn
R2
Skn
Rl + R2) R6
VOUT=V 1N ( 1+ R 3 R4
= lOa
GAIN LIN = 0 002%
SLEW RATE = 25V/j.ls
PSAR = 112dB
GAIN
R5
2kn
lo-----+--l+
R7
20kn
'F~=~
THEN CMRR = 120dB
ADJUST R7 FOR MAXIMUM CMRR
5-85
1/86, Rev. A
~
I-I-l
......
~
~
~
~
0
......
~
I-I-l
C5
---------l1fHD
OP-10 DUAL MATCHED INSTRUMENTATION OPERATIONAL AMPLIFIER
CMRR VB FREQUENCY
INSTRUMENTATION AMPLIFIER (3 OP-AMP DESIGN)
PRECISION DUAL TRACKING VOLTAGE REFERENCES
USING OP-10
125
120
R'
V+
115
i'-
m
110
~
""u
'05
""
2
\j
,
'00
2
95
3
AS - 100kn,
BALANCED
AS = loon, lkn,
UNBALANCED
RS = 20kn,
BAI~fNCED
90
'0
10
R2
R4
R5
,
\
R6
\
R6=
~!: ~;
V2
\
100
1k
FREQUENCY (Hz)
PRECISION DUAL TRACKING VOLTAGE REFERENCES
USING OP-10
INSTRUMENTATION AMPLIFIER (2 OP-AMP DESIGN)
Precision dual tracking voltage references using a single
reference source are easily constructed using OP-10. These
references exhibit low noise, excellent stability vs. temperature and time, and have excellent power supply rejection.
V+
Rl
In the circuit shown, R3 should be adjusted to set IREF to
operate VREF at its minimum temperature coefficient current.
Proper circuit start-up is assured by Rz, Z1, and 01.
V1 = VREF (1
R4
99kn
VOUT
(1+~)
+ R2)
R1
Vl
V2
~=~
±O.005%
V2=V1 (-R5)
R4
Output Impedance (dIL:1.0mA-5.0mA) ...... 0.25 x 10-30
5-86
1/86, Rev. A
OP-12
PRECISION LOW- INPUT- CURRENT
OPERATIONAL AMPLIFIER (INTERNALLY COMPENSATED)
Precision Monolithics Inc.
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
The PMI OP-12 is an improved version of the popular LM108A
low-power op amp. The OP-12 is internally compensated and
its chip dimensions are only 42 X 58 mils. Offset voltage is
lower; the total worst-case input offset voltage over-55° C to
+ 125° C for the OP-12A is only 350"V. In addition, the OP-12
drives a 2kO load which is five times the output current
capability of the 108A. Thisexcellent performance is achieved
by applying PMI's ion-implanted super-beta process and
on-chip zener-zap trimming capabilities. The internal compensation makes this op amp ideal for hybrid assembly
applications.
Low Offset Voltage ........................ 150"V Max
Low Offset Voltage Drift ................ 2.5"Vlo C Max
Load Current Capability ..................... 5mA Min
Internal Frequency Compensation
125°C Temperature Tested Die
Low Offset Current ...................... 200pA Max
Low Bias Current ......................... 2.0nA Max
Low Power Consumption .......... 18mW Max@±15V
High Common-Mode Input Range .......... ±13V Min
MIL-STD-883 Class B Processing Available
Silicon-Nitride Passivation
ORDERING INFORMATIONt
PIN CONNECTIONS
NC
NCS'V'
PACKAGE
TA = 25°C
VosMAX
(mV)
HERMETIC
TO-99
8-PIN
HERMETIC
DIP
8-PIN
OPERATING
TEMPERATURE
RANGE
0.15
0.15
0.30
0.30
1.0
1.0
OP12AJ'
OP12EJ
OP12BJ'
OP12FJ
OP12CJ'
OP12GJ
OP12AZ'
OP12EZ
OP12BZ'
OP12FZ
OP12CZ'
OP12GZ
MIL
COM
MIL
COM
MIL
COM
8
"+
-IN 2
+IN3
5NC
v-
• For deVices processed In total compliance to M I L-STD-883. add /883 after
part number Consult factory for 883 data sheet
t All commercial and industnal temperature range parts are available with
burn-In. For ordenng Information see 1986 Data Book, Section 2.
60UT
4
(CASE)
TO-99 (J-Suffix)
8-PIN HERMETIC MINI-DIP
(Z-Sufflx)
SIMPLIFIED SCHEMATIC
R5
OUTPUT
L---+--~-o6
R6
5-87
1/86, Rev. A
--------IIEHD
OP·12 PRECISION LOW·INPUT·CURRENT OPERATIONAL AMPLIFIER
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
ABSOLUTE MAXIMUM RATINGS (Note 4)
Supply Voltage
OP·12A, Op·12B,
OP·12E, Op·12F, All DICE except GR •••••••••••• ±20V
OP·12C, OP·12G, GR DICE Only ................ ± 18V
Operating Temperature Range
Op·12A, Op·12B, OP·12C ••••••••••• -55°C to +125°C
OP·12E, Op·12F, Op·12G •••••••••••••••• O°C to +70°C
Storage Temperature Range ••••••••••• -65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) •••••• 300°C
Internal Power Dissiption (Note 1) ............... 500mW
Differentiallnpul Current (Note 2) •••••••••.••••• ±10mA
Input Voltage (Note 3) ............................ ±15V
Output Short·Clrcuil Duration ••••••••••••••••• Indefinite
DICE Junction Temperature (Tj) ••••••• -65°C to +150°C
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
TO-99 (J)
80'C
7,1mW/'C
8-Pin Hermetic DIP (Z)
75'C
8,7mW/'C
PACKAGE TYPE
2, The inputs are shunted with back-to-back diodes for overvoltage protection, Therefore. excessive current will flow If a differential Input voltage In
excess of 1V Is applied between the Inputs unless some limiting resistance
Is provided,
3, For supply voltages less than ± 15V, the absolute maximum Input voltage Is
equal to the supply voltage,
4, Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted,
ELECTRICAL CHARACTERISTICSatVs=±20Vand TA=25°CforA, B, Eand Fgrades, Vs=±15V, andTA =25°CforCand
G grades, unless otherwise noled.
OP·12A/E
TYP
MAX
MIN
OP·12B/F
TYP
MIN
MAX
OP·12C/G
MIN
TYP
MAX
Vos
0,07
0,15
0,18
0,30
0,25
1,0
mV
Input Offset Current
los
0,05
0,20
0,05
0,20
0,08
0,50
nA
Input Bias Current
18
0,8
2,0
0,8
2,0
1,0
5,0
nA
Input ResistanceDifferential-Mode
R'N
(Note 1)
PARAMETER
SYMBOL
Input Offset Voltage
CONDITIONS
UNITS
26
70
26
70
10
50
Mil
Input Voltage Range
IVR
Vs= ±15V
±13
±14
±13
±14
±13
±14
V
Common-Mode
Rejection Ratio
CMRR
VCM = ±13V
104
120
104
120
84
116
dB
Power Supply
Rejection Ratio
±13
±10
±14
±12
±13
±10
±14
±12
±13
±10
±14
±12
BO
300
BO
300
40
250
50
150
50
150
PSRR
Vs= ±5V to ±15V
Output Voltage
Swing
Vo
RL2: 10kll, Vs =±15V
RL 2:2kll. Vs =±15V
63
Large-Signal
Voltage Gain
Avo
RL 2: 10kll
Vo =±10V
RL 2: 2kll
Vo =±10V
Power Consumption
Pd
Vs = ± 15V. No Load
Vs =±5V. No Load
Input Noise Voltage
en~pE!
0,1 Hz to 10Hz
0,9
0,9
O,g
",V
Input Noise
Voltage Density
en
fo= 10Hz
fo= 100Hz
fo= 1000Hz
22
21
20
22
21
20
22
21
20
nVlVH%
Input Noise Current
",VlV
V
VlmV
100
1B
6
18
12
4
24
mW
e-e
Ine-e
0,1 Hz to 10Hz
3
pA e-e
Input Noise
Current Density
In
fo= 10Hz
fo = 100Hz
fo= 1000Hz
0,15
0,14
0,13
0,15
0,14
0,13
0.15
0,14
0,13
pA/VH%
Slew Rate
SR
RL 2: 2kll
0,12
0,12
0.12
VI",s
Closed-Loop
Bandwidth
BW
AVCL = +1
0,80
O,BO
O,BO
MHz
Open-Loop Output
Resistance
Ro
Vo=O,lo=O
200
200
200
Il
NOTE:
1, Guaranteed by input bias current.
5·88
1/86, Rev. A
IfMD
OP-12 PRECISION LOW-INPUT -CURRENT OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs =± 15V, for C grade, Vs =±20V for A and B grades, -55· C ~ TA~ +125· C, unless
otherwise noted.
OP-12A
PARAMETER
SYMBOL
Input Offset Voltage
CONDITIONS
MIN
OP-12B
TYP
MAX
Vos
0.12
Average Input Offset
Voltage Drift
TCVos
MIN
OP-12C
TYP
MAX
MIN
TYP
MAX
UNITS
0.35
0.28
0.60
0.40
2.0
mV
0.50
2.5
1.0
3.5
1.5
10
~V/'C
Input Offset Current
los
0.12
0.40
0.12
0.40
0.18
1.0
nA
Average Input Offset
Current Drift
TClos
0.50
2.5
0.50
2.5
1.0
5.0
pA/'C
Input Bias Current
Ie
1.2
3.0
1.2
3.0
1.8
10
nA
Input Voltage Range
IVR
Vs= ±15V
±13
±14
±13
±14
±13
±14
V
Common-Mode
Rejection Ratio
CMRR
VOM = ±13V
100
116
100
116
80
112
dB
Power Supply
Rejection Ratio
PSRR
Vs = ±5 to ±15V
Large-Signal
Voltage Gain
Avo
R L ", 5kO
Vo =±10V
Output Voltage
Swing
Vo
RL ", 10kO, Vs =±15V
RL "'5kO. Vs =±15V
Power Consumption
Pd
Vs = ±15V, No Load
ELECTRICAL CHARACTERISTICS at Vs
otherwise noted.
4
10
10
100
p.VIV
120
40
120
15
80
V/mV
±13
±10
±14
±13
±13
±10
±14
±13
±13
±10
±14
±12
V
18
9
9
18
15
24
mW
~
OP-12F
OP-12G
SYMBOL
TYP
MAX
TYP
MAX
TYP
MAX
UNITS
Vos
0.10
0.26
0.23
0.45
0.32
1.4
mV
Average Input Offset
Voltage Drift
TCVos
0.50
2.5
1.0
3.5
1.5
10
p.V/'C
Input Offset Current
los
0.08
0.30
0.11
0.60
0.12
0.70
nA
Average Input Offset
Current Drift
TClos
0.50
2.5
1.0
5.0
1.0
5.0
pA/'C
1.0
2.6
1.2
5.2
1.4
6.5
nA
MIN
MIN
MIN
Input Bias Current
Ie
Input Voltage Range
IVR
Vs =±15V
±13
±14
±13
±14
±13
±14
V
Common-Mode
Rejection Ratio
CMRR
VOM =±13V
100
116
100
116
80
112
dB
Power Supply
Rejection Ratio
PSRR
Vs= ±5 to ±15V
Large-Signal
Voltage Gain
Avo
RL ", 10kO
Vo= ±10V
R L ", 2kO
Vo =±10V
Vo
Power Consumption
Pd
~
-~
= ±15V for G grade, Vs = ±20V for E and F grades, O·C ~ TA ~ 70·C, unless 0
PARAMETER
R L ", 10kO
Vs =±15V
RL ", 5kO
Vs= ±15V
....
::l
p...
Input Offset Voltage
Output Voltage
Swing
~
~
40
OP-12E
CONDITIONS
I-
4
10
10
100
60
200
60
200
25
100
25
100
±13
±14
±13
±14
±13
±14
±12
±10
±12
±10
±12
25
p.VIV
150
V/mV
80
V
±10
Vs = ± 15V. No Load
9
18
18
15
24
mW
For typical performance characteristics, see OP-08 data sheet. Assume
Co=30pF.
5-89
1/86, Rev. A
~
15
I
I
-----------l1fMD
OP-12 PRECISION LOW-INPUT-CURRENT OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS (125°C TESTED DICE AVAILABLE)
1.
2.
3.
4.
6.
7.
8.
DIE SIZE 0.058 X 0.042 Inch, 2436 sq. mils
(1.47 X 1.07 mm, 1.57 sq. mm)
WAFER TEST LIMITS
at Vs=
NO CONNECTION
INVERTING INPUT
NON INVERTING INPUT
VOUTPUT
V+
NO CONNECTION
For additional DICE informalion refer 10
1986 Dala Book, Seclion 2.
± 15V, TA = 25°C for Op·12N, Op·12G and Op·12GR devices; TA = 125°C for OP·12NT and
OP-12GT devices, unless otherwise noted. (Note 2)
OP-12NT
OP-12N
OP-12GT
OP-12G
OP-12GR
LIMIT
LIMIT
LIMIT
LIMIT
LIMIT
Vos
035
015
0.6
03
Input Offset Current
los
02
02
0.2
0.2
0.5
Input Bias Current
Ie
Input Voltage Range
IVR
±13
±13
±13
±13
±13
VMIN
Common-Mode
Rejection Ratio
CMRR
VCM = ±13V
100
104
100
104
84
dBMIN
Power Supply
Rejection Ratio
PSRR
Vs
Output Voltage Swing
Vo
R L <: 10kfl
R L ;" 2kfl
R L ;"5kfl
PARAMETER
SYMBOL
I nput Offset Voltage
2
=
nAMAX
nAMAX
10
±5V to ±15V
UNITS
mVMAX
10
±13
±13
±10
±10
±13
63
±13
±10
±13
±10
80
50
40
~V/v
MAX
VMIN
±10
R L ;" 10kfl. Vo= ±10V
R L <:2kfl, Vo =±10V
R L ;"5kfl, Vo =±10V
80
R'N
(Note II
26
26
26
26
10
MflMIN
ISY
0
VOUT=O
0.6
06
0.6
0.6
0.8
mAMAX
Large-Signal
Voltage Gain
Avo
Input ResIstance
Supply Current
CONDITIONS
80
50
40
10UT=
NOTES:
1. Guaranteed by design.
80
VlmV MIN
40
2.
For 25°C specifications of OP-12NT and OP-12GT, see OP-12N and
OP-12G , respectively.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS
at Vs
= ± 15V, unless otherwise noted.
OP-12NT
OP-12N
OP-12GT
OP-12G
OP-12GR
TYPICAL
TYPICAL
TYPICAL
TYPICAL
TYPICAL
UNITS
TCVos
05
0.5
10
1.0
15
~V;oC
TClos
05
0.5
10
10
10
pA/oC
PARAMETER
SYMBOL
Average In put Offset
Voltage Drift
Average Input Offset
Current Dnft
CONDITIONS
5-90
1/86, Rev. A
OP-15/ OP-16/ OP-17
PRECISION JFET-INPUT
OPERATIONAL AMPLIFIERS
Precision Monolithics Inc.
FEATURES (All Devices)
op amps. All devices offer offset voltages as low as 0.5mV with
TCVosguaranteed to 5!,VloC. A unique input bias cancellation
circuit reduces the IB by a factor of 10 over conventional
designs. In addition, PMI specifies I Band loswith the devices
warmed up and operating at 25°C ambient.
• Significant Performance Advantages over LF155. 156 and
157 Devices.
• Low Input Offset Voltage ................•.. 500!'V Max
• Low Input Offset Voltage Drift ................ 2.0!,Vlo C
• Minimum Slew Rate Guaranteed on All Models
• Temperature-Compensated Input Bias Currents
• Guaranteed Input Bias Current @ 125°C
• Bias Current Specified WARMED UP Over Temperature
• Internal Compensation
• Low Input Noise Current ....•............ 0.01pAlVHz
• High Common-Mode Rejection Ratio ............ 100dB
• Models With MIL-STD-883 Processing Available
• 125°C Temperature Tested DICE
These devices were designed to provide real precision
performance along with high speed. Although they can be
nulled, the design objective was to provide low offset-voltage
without nulling. Systems generally become more cost effective as the number of trim circuits is decreased. PMI achieves
this performance by use of an improved Bipolar compatible
J FET process coupled with on-chip, zener-zap offset trimmi ng.
The OP-15 provides an excellent combination of high speed
and low input offset voltage. In addition, the OP-15 offers the
speed of the 156A op amp with the power dissipation of a
155A. The combination of a low input offset voltage of 500!'V,
slew rate of 13V1!,s, and settling timeof 1200ns toO.1% makes the
OP-15 an op amp of both preCision and speed. The additional
features of low supply current coupled with an input bias current
of 9nA at 125° C ambient (not junction) temperature makes the
OP-15 ideal for a wide range of applications.
OP-1S
•
•
•
•
156 Speed With 155 Dissipation ........•... (80mW Typ)
Wide Bandwidth ................................ 6MHz
High Slew Rate ..............•.•....•.......... 13V1!,s
Fast Settling to ±0.1% .....•..•...............• 1200ns
OP-16
• Higher Slew Rate .............••...•........... 25V1!,s
• Faster Settling to ±0.1% ....•.................... 900ns
• Wider Bandwidth ....•.•..•....•..............•. 8M Hz
The OP-16 features a slew rate of 25V1!,s and a settling time of
900ns to 0.1% which represents a significant improvement in
speed over the 156. Also, the OP-16 has all the DC features of
the OP-15.
OP-17
• Highest Slew Rate .......•........•...•.. , •.... 60Vl!,s
• Fastest Settling to ±0.1% ........................ 600ns
• Highest Gain Bandwidth Product •.•............ 30M Hz
The OP-17 has a slew rate of 60Vl!,s and is the best choice
for applications requiring high closed-loop gain with high
speed. Applications include high-speed amplifiers for current
output DACs, active filters, sample-and-hold buffers, and
photocell amplifiers.
GENERAL DESCRIPTION
The PMI JFET-input series of devices offer clear advantages
over industry-genenc devices and are superior in both cost
and performance to many dielectrically-isolated and hybrid
See the OP-215 data sheet for a dual configuration of the
OP-15.
SIMPLIFIED SCHEMATIC
'"NOTE
R7, RS ARE ELECTRONICALLY
ADJUSTED ON CHIP FOR
MINIMUM OFFSET VOLTAGE
022
,---+----+--o (61 OUTPUT
V-14Io--....................- - - - -.............-
......-+-.......- - - - + - - -.......___..........- -........-
5-91
........---'
1/86, Rev. A
i.
I
I
I
II
--------l~ OP-15/0P-16/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
ORDERING INFORMATIONt
ABSOLUTE MAXIMUM RATINGS (Note 2)
Supply Voltage
All Devices Except C, G (Packaged) & GR Grades .. ±22V
C, G (Packaged) & GR Grades .................. ±18V
Internal Power Dissipation (Note 1) .............. 500mW
Operating Temperature
A, B, & C Grades ................... -55·C to +125·C
E, F & G Grades ........................ O·C to +70·C
Maximum Junction Temperature ................ +150·C
DICE Junction Temperature (Tj) ....... -65·C to +150·C
Differential Input Voltage
All Devices Except C, G (Packaged) & GR Grades .. ±40V
C, G (Packaged) & GR Grades .................. ±30V
Input Voltage (Note 3)
All Devices Except C, G (Packaged) & GR Grades .. ±20V
C, G (Packaged) & GR Grades .................. ±16V
Input Voltage
OP-15A, OP-15B, OP-15E, OP-15F ............... ±20V
OP-15C,OP-15G ............................... ±16V
OP-16A, OP-16B, OP-16E, OP-16F ............... ±20V
OP-16C,OP-16G ............................... ±16V
OP-17A, OP-17B, OP-17E, OP-17F ............... ±20V
OP-17C,OP-17G ............................... ±16V
Output Short-Circuit Duration ................. Indefinite
Storage Temperature Range ........... -65·C to +150·C
Lead Temperature Range (Soldering, 60 sec) .... +300·C
PACKAGE
TO-89
8-PIN
8-PIN
HERMETIC
DIP
OPERATING
TEMPERATURE
RANGE
0.5
OP15AJ'
OP16AJ'
OP17AJ'
OP15AZ'
OP16AZ'
OP17AZ'
MIL
0.5
OP15EJ
OP16EJ
OP17EJ
OP15EZ
OP16EZ
OP17EZ
COM
1.0
OP15BJ'
OP16BJ'
OP17BJ'
OP15BZ'
OP16BZ'
OP17BZ'
MIL
1.0
OP15FJ
OP16FJ
OP17FJ
OP15FZ
OP16FZ
OP17FZ
COM
3.0
OP15CJ'
OP16CJ'
OP17CJ'
OP15CZ'
OP16CZ'
OP17CZ'
MIL
3.0
OP15GJ
OP16GJ
OP17GJ
OP15GZ
OP16GZ
OP17GZ
COM
TA = 2S·C
VOSMAX
(mV)
'For devices processed in total compliance to MIL-STD-883, add 1883 after
part number. Consult factory for 883 data sheet.
t All commercial and industrial temperature range parts are available with
burn-in. For ordering information see 1986 Data Book, Section 2.
PIN CONNECTIONS
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
N.C.
•
BALe7V+
~
-IN 2
+IN 3
PACKAGE TYPE
6 OUT
5 BAL
v-
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
TO-99 (J)
SO·C
7.1mWfOC
Hermetic S-Pin Dip (Z)
75·C
6.7mW/·C
4
(CASE)
2.
TO-99
(J-Suffix)
8-PIN HERMETIC DIP
(Z-Sufflx)
3
5-92
Absolute maximum ratings apply to both packaged parts and DICE. unless
otherwise noted.
Unless otherwise speCified the absolute maximum negative input voltage is
equal to the negative power-supply voltage.
1/86, Rev, A
----------1~
OP·15/0P·16/0P·17 PRECISION JFET·INPUT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, TA = 25°C, unless otherwise noted.
Op·15A1E
Op·16A1E
OP·17A1E
PARAMETeR
SYMBOL CONDITIONS
Input Offset Voltage
Vas
T1= 25'C (Note I)
Input Offset Current
los
Device Operating
Tj= 25'C (Note I)
Device Operating
Input Bias Current
la
MIN
Rs= 500
T1=25'C (Note I)
Device Operating
TI = 25'C (Note I)
Device Operating
Op·15B/F
Op·16B/F
OP·17B/F
TYP
MAX
0.2
0.5
MIN
10
22
10
25
Op·15
OP-D16/0P-17
OP-16/0P-17
Ava
Output Voltage
Swing
Supply Current
Slew Rate
RL " 2kO
ISY
OP-15
OP-16/0P-17
SR
OP-15
OP-16
OP-17
10
18
45
OP-15
OP-16
OP-17
4.0
6.0
20
AVCL = +1 (Note 3)
Gain Bandwidth
Product
GBW
Closed-Loop
Bandwidth
CLBW
AVCL = +1
AVCL = +5
Settling Time
Input Voltage Range
(Note 3)
2.7
4.6
MAX
UNITS
0.5
30
mV
20
40
20
50
12
20
12
20
50
100
50
125
pA
±30 ±100
±40 ±200
±30 ±100
±40 ±250
±60
±80
±60
±80
±200
±400
±200
±500
pA
10'2
10'2
o
200
VlmV
±12
±13
±11 ±12.7
V
220
4.0
7.0
2.7
4.6
MIN
50
±12
±13
±11 ±12.7
4.0
7.0
2.8
4.8
60
7.5
12
35
11
21
50
25
17
40
6.0
8.0
30
3.5
5.5
15
5.7
7.6
28
3.0
5.0
11
5.4
7.2
26
13
25
14
OP-15
OP-16
OP-17
TYP
1.0
6
75
±12
±13
±11 ±12.7
RL = 10kO
RL = 2kO
AVCL = +5 (Note 3)
240
100
Vo= ±10V
MAX
0.4
10
Input Resistance
Large·Signal
Voltage Gain
TYP
10
±15
±50
±18 ±110
±15 ±50
±20 ±130
OP-15
OP·15C/G
Op·16C/G
OP·17C/G
9
19
11
13
18
10
12
17
MHz
MHz
9
OP-15
4.5
1.5
1.2
4.5
1.5
1.2
4.7
1.6
1.3
to 0.01%
to 0 05% (Note 2)
to 0.10%
OP-16
3.8
1.2
0.9
3.8
1.2
0.9
4.0
1.3
1.0
to 0.01%
to 0.05% (Note 4)
to 0.10%
OP-17
1.5
0.7
0.6
1.5
0.7
0.6
1.6
0.8
0.7
±10.5
mA
9
to 0.01%
to 0.05% (Note 2)
to 0.10%
IVR
5.0
8.0
±10.5
±10.3
V
Common-Mode
Rejection Ratio
CMRR
VCM =±10.5V
VcM =±10.3V
Power Supply
Rejection Ratio
PSRR
Vs= ±10V to ±18V
Vs =±10Vto±15V
10
Input Noise
Voltage Density
fO= 100Hz
fo= 1000Hz
20
15
20
15
20
15
nV/y"Hz
Input Noise
Current Density
fO= 100Hz
fo= 1000Hz
0,01
0,01
0,01
0.01
0.01
0.01
pAly"Hz
3
3
3
pF
100
86
86
100
82
51
10
51
10
Input Capacitance
NOTES:
1. Input bias current is specified for two different conditions. The TJ= 25'C
specification is with the junction at ambient temperature; the Device
Operating specification is with the device operating in a warmed-up
dB
96
80
inverting input pin on the amplifier) to settle to within a specified percent of
its final value from the time a 10V step input is applied to the inverter. See
settling time test circuit.
3. Sample tested.
4. Settling time is defined hereforaA v =-5connection with R F= 2kO.lt isthe
time required forthe error voltage (the voltage at the inverting input pin on
the amplifier) to settle to within 0.01% of its final value from the time a 2V
step input is applied to the inverter. See settling time test circuit.
condition at 25° C ambient. The warmed-up bias current value is correlated
to the junction temperature value via the curves of lavs TJ and IBvs TA. PMI
hass bias current compensation circuit which gives Improved bias current
over the standard JFET input opamps. IBand losare measured at VCM=O.
2. Settling time is defined herefora unity gain inverter connection using 2kO
resistors. It is the time required for the error voltage (the voltage at the
5·93
1/86, Rev. A
----------IIEMD
OP-15/0P-16/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS at Vs =
± 15V, -55°C :S TA:S 125°C, unless otherwise noted.
OP-15A
OP-16A
OP-17A
PARAMETER
SYMBOL CONDITIONS
I nput Offset Voltage
Vos
Average In put
Offset Voltsge Drift
Without External
Trim
With External
Trim
TCVos
Input Offset
Current (Note 1)
Input Bias
Current (Note 1 )
Input Voltage Range
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
MIN
OP-15B
OP-16B
OP-17B
TYP
MAX
TYP
MAX
TYP
MAX
UNITS
0.4
0.9
0.7
2.0
0.9
4.5
mV
2
5
3
10
4
15
Rs=50n
MIN
OP-15C
OP-16C
OP-17C
MIN
(Note 2)
I'VI'C
TCVOSn
Rp= l00kn
Tj= 125'C
TA = 125'C
Device Operating
los
Ie
OP-15
3
4
0.6
4.0
0.8
6.0
1.0
0.8
7.0
1.2
11
1.5
17
0.6
4.0
0.8
6.0
1.0
9.0
1.0
8.5
1.3
14.5
1.7
22
9.0
nA
TJ =125'C
TA = 125'C
Device Operating
OP-16/0P-17
TJ =125'C
TA = 125'C
DevIce Operating
OP-15
±1.2
±5.0
±1.5
±7.5
±1.8
±10
±1.7
±90
±2.2
±14
±2.7
±19
±1.2
±5.0
±1.5
±7.5
±1.8
±10
±2.0
±11
±2.5
±18
±3.0
±25
nA
TJ = 125'C
TA = 125'C
DevIce Operating
IVR
CMRR
2
OP-16/0P-17
±104
±10.4
85
VCI~=±104V
97
85
±10.25
VCM = ± 10.25V
80
15
57
V
97
15
dB
93
57
PSRR
Vs= ±10V to ±18V
Vs =±10Vto±15V
Large-Signal
Voltage Gain
Avo
RL ,,2kn
Vo =±10V
35
120
30
110
25
100
V/mV
Output Voltage
Swing
Vo
RL " 10kn
±12
±13
±12
±13
±12
±13
V
23
100
I'VN
NOTES:
1. Input bias current Is specified for two different condItIons. The TJ = 25' C
speCification is with the junction at ambient temperature; the Device
Operating speCification Is with the device operating In a warmed-up
condition at 25'C ambient. The warmed-up bias current value Is correlated to the junction temperature value via the curves of Ie vs TJ and Ie vs
TA• PMI hasa bias current compensation circuit which gives Improved bias
current over the stsndard JFET input op amps. Ie and los are measured
at VCM=O.
2. Sample tested.
5-94
1/86, Rev. A
~
OP-15/0P-16/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS at Vs = ±15V,
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Average Input
Offset Voltage Drift
Without External
Trim
With External
Tnm
OP-15F
OP-16F
OP-17F
MIN TYP MAX
OP-15G
OP-16G
OP-17G
MIN TYP MAX
03
0.55
1.5
07
3
10
3.S
UNITS
mV
(Note 2)
15
~VI'C
TCVOSn
Rp= 100kn
3
OP-15
Device Operating
los
OP-16/0P-17
OP-15
Device Operating
I.
4
0.04
0.30
006
0.45
O.OS
0.65
0.06
055
OOS
O.SO
0.10
1.2
0.04
030
0.06
0.45
OOS
065
007
070
010
11
015
1.7
nA
TJ = 70'C
TA = 70'C
TJ = 70'C
TA = 70'C
±010 ±0.40
±012 ±060
±0.14 ±O.SO
±013 ±o 75
±016
±0.19
±11
~
~
......
~
......
......:l
±15
nA
T J = 70'C
TA = 70'C
OP-16/0P-17
Device Operating
Input Voltage Range
075
TCVos
Device Operating
Input Bias
Current (Note 1)
unless otherwise noted.
OP-15E
OP-16E
OP-17E
MIN TYP MAX
Rs= son
T J = 70'C
TA = 70'C
Input Offset
Current (Note 1 )
ooe:s TA:S 70 oe,
±010 ±040
±012 ±060
±015 ±0.90
±020
±104
IVR
85
±1.4
±10.4
98
85
±0.14 ±OSO
±025
-<
......:l
±20
±10.25
V
98
Common-Mode
Rejection Ratio
CMRR
VCM = ±10 4V
VCM = ± 10.25V
Power Supply
Rejection Ratio
PSRR
Vs = ±10V to ±18V
Vs = ±10V to ±15V
Large-Signal
Voltage Gain
Avo
Rl2: 2kn
Vo= ±10V
65
200
50
180
35
160
VlmV
Output Voltage
Swing
Vo
Rl2: 10kn
±12
±13
±12
±13
±12
±13
V
80
13
57
13
dB
94
57
20
100
~VIV
~
0......
~
~
NOTES:
Input bias current IS specified for two different conditions The T J= 25° C
specification IS with the Junction at ambient temperature, the Device
Operating specification IS With the device operating In a warmed-up
condition at 25°C ambient. The warmed-up biBS current value IS correlated to the Junction temperature value via the curves of IBvS T J and 18 vs
T A- PMI hasa bl8S current compensation circuit which gives improved bias
current over the standard JFET input op amps 1B and los are measured
atVCM=O.
Sample tested.
5-95
~
::E
1/86, Rev. A
C5
--------I~ OP-15/0P-16/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
DICE CHARACTERISTICS (125'C TESTED DICE AVAILABLE)
OP-16
OP-15
DIE SIZE 0.068 X 0.056 Inch, 3808 sq. mils
(1.73 X 1.42mm, 2.46 sq. mm)
1.
2.
3.
4.
5.
6.
BALANCE
INVERTING INPUT
NONINVERTING INPUT
VBALANCE
OUTPUT
7. V+
OP-17
DIE SIZE 0.068 X 0.056 Inch, 3808 sq. mils
(1.73 X 1.42mm, 2.46 sq. mm)
DIE SIZE 0.068 X 0.056 Inch, 3808 sq. mils
(1.73 X 1.42mm, 2.46 sq. mm)
5. BALANCE
6. OUTPUT
1.
2.
3.
4.
5.
6.
7. V+
7. V+
1. BALANCE
2. INVERTING INPUT
3. NON INVERTING INPUT
4. V-
BALANCE
INVERTING INPUT
NONINVERTING INPUT
VBALANCE
OUTPUT
For addillonal DICE Informallon refer 10 1986 Data Book, Secllon 2.
WAFER TEST LIMITS at Vs= ± 15V, TA = 25'C for OP-15/16/17N, OP-15/16/17G and OP-15/16/17GR devices; TA = 125' C for
OP-15/16/17NT and OP-15/16/17GT devices, unless otherwise noted.
OP-15NT
OP-16NT
OP-17NT
OP-15N
OP-16N
OP-17N
OP-15GT
OP-16GT
OP-17GT
OP-15G
OP-16G
OP-17G
OP-15GR
OP-16GR
OP-17GR
PARAMETER
SYMBOL CONDITIONS
LIMIT
LIMIT
LIMIT
LIMIT
LIMIT
UNITS
Input Offset Voltage
Vos
Rs= 500
0.9
0.5
2.0
1.0
3.0
mVMAX
Large-Signal
Voltage Gain
Avo
Vo =±10V
RL = 2kO
35
100
30
75
50
VlmV MIN
Input Voltage Range
IVR
±10.4
±10.5
±10.4
±10.5
±10.3
VMIN
Common-Mode
Rejection Ratio
CMRR
VCM = ±IVR
85
86
85
86
82
dB MIN
Power Supply
Rejection Ratio
PSRR
Vs = ± 10V to ±20V
Vs = ±10V to ±15V
57
51
57
51
Output Voltage
Swing
Vo
RL = 10kO
RL = 2kO
Supply Current
ISY
OP-15
OP-16,OP-17
Input Bias Current
19
OP-15
OP-16, OP-17
±9
±11
±14
±18
nAMAX
Input Offset Current
los
OP-15
OP-16, OP·17
7.0
8.5
11,0
14,5
nAMAX
80
±12
±12
±11
±12
±12
±11
4
±12
±11
p.VIV MAX
VMIN
mAMAX
NOTES:
For2S'C characteristics of OP-15/16/17NT and OP-15/16/17GT, see OP-1S/16/17N
and OP-15/16/17G characteristics, respectively.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal Yield loss, yield after packaging Is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
5-96
1/86, Rev. A
~ OP-15/0P-16/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
TYPICAL ELECTRICAL CHARACTERISTICS at Vs =
PARAMETER
SYMBOL CONDITIONS
Average Input Offset
Drift Unnulled
TCVos
Average Input Offset
Drift Nulled
TCVOSn
Input Offset Current
los
Input Bias Current
IB
Slew Rate
SR
ts
GBW
Closed-Loop
Bandwidth
CLBW
C, unless otherwise noted.
OP-1SNT
OP-16NT
OP-17NT
OP-1SN
OP-16N
OP-17N
OP-1SGT
OP-16GT
OP-17GT
OP-1SG
OP-16G
OP-17G
OP-1SGR
OP-16GR
OP-17GR
TYPICAL
TYPICAL
TYPICAL
TYPICAL
TYPICAL
Rp= 100kn
UNITS
~V/'C
3
3
pA
±15
±15
±15
±15
±15
pA
OP-15
OP-16
OP-17
13
25
60
13
25
60
11
21
50
11
21
50
9
17
40
V/~s
to 0.01%
to 0.05%
to 0.10%
OP-15
4.5
1.5
1.2
4.5
1.5
1.2
4.5
1.5
1.2
4.5
1.5
1.2
4.7
1.6
1.3
to O.Q1%
to 0.05%
to 0.10%
OP-16
3.8
1.2
0.9
3.8
1.2
0.9
3.8
1.2
0.9
3.8
1.2
0.9
4.0
1.3
1.0
OP-17
1.5
0.7
0.6
1.5
0.7
0.6
1.5
0.7
0.6
1.5
0.7
0.6
1.6
OS
0.7
OP-15
OP-16
OP-17
6.0
8.0
30
6.0
8.0
30
5.7
7.6
28
5.7
7.6
28
5.4
7.2
26
MHz
OP-15
OP-16
OP-17
14
19
11
14
19
11
13
18
10
13
1S
10
12
17
9
MHz
20
15
20
15
20
15
20
15
20
15
nVl..jHZ
0.Q1
0.01
0.01
0.01
0.Q1
0.01
0.Q1
0.Q1
0.Q1
0.Q1
pAl..jHZ
3
3
3
AVCL = +1
to 0.01%
to 0.05%
to 0.10%
Gain Bandwidth
Product
0
~VI'C
AVCL = +5
Settling Time
(see settling time
test circuits)
±15V, TA = +25
AVCL = +1
AVCL = +5
Input Noise Voltage
Density
en
f= 100Hz
f = 1000Hz
Input Noise Current
Density
in
f = 100Hz
f = 1000Hz
Input Capacitance
C 'N
~.......
~s
~
~
~....:I
~
0
.......
~
...:I
~
pF
NOTES:
For 25' C characteristics of OP-15/16/1 7NT and OP-15/16/1 7GT. see OP-15/16/1 7N
and OP-15/16/17G characteristics, respectively.
5-97
.....
1/86, Rev. A
0
--------I~ OP-15/0P-16/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CHARACTERISTICS (OP-15/0P-16/0P-17)
MAXIMUM OUTPUT SWING
vs LOAD RESISTANCE
0
I IIII
7
~ ~1
4
,
1
f---
1111
VOLTAGE NOISE vs
SOURCE RESISTANCE
±20;------r-----,------;-----~
w
'-'
Z
±15 ~--+--___t--____;,r_-___T_--I
~
"~ "0
0
.,
+l~~~C
2
~--~--_+--+--~-____J
100
;i
+25°C
5
1000 ; - - - - - , - - - - - , - - - - - . . , - - - - - , - - - - ,
~
IU~ ",15J
V
_550C
g
I
I
COMMON-MODE INPUT
VOLTAGE RANGE
vs SUPPLY VOLTAGE
>
10r-----r----+----+--~~~~
~--+--__,!'---------,,L-+_----I
>-
;;;
w
.j;,
~
"0~
o 11-____""'--~-*Ci)AMPLIFIER
,.,.
0
100
lk
10k
lOOk
NEGATIVE
°0~----±~5~----±~,0~----±1~5-----±~2-0
0
<.>
SUPPLY VOLTAGE (VOLTS)
OUTPUT LOAD RESISTANCE (n)
±1:WARMEO-UP
vs"" IN FREE AI1±±
±15V
TA"'25°C
80
I
I
I
I
70 CDUNDERCANCELLED 18
!>-
60
~
40
30
iii0:
50
<.>
~
iii
>-
I
I
= +16pA @VCM '" ~
CD PERFECTLY CANCLLED IB = a @VCM = 0
CD OVERCANCELLED IS = -16pA \@VCM,=
--r-----1
'1 , .A'JaT/
I
----T-t-
20
.,
'
(i)
10
e--+--
f-
;;;
V
V
v'/
~
0~~~~~~~~~~s:S~~~~URED
__
____
____
___ J
~
1M
~
10M
lG
lOG
40
RL eo 2k
TA = 25°C
>"
SOak r---------SSoC
400k
;;- 300k
25°C
200k
w
>-
g
""
i
~
100M
OUTPUT VOLTAGE SWING
vs SUPPLY VOLTAGE
----
-
1----125'C
100k
V
/
RL'2kn-
~
1;
./
-10
lOOk
SOURCE RESISTANCE (n)
1M
§
,
G)/
001L-____
OPEN-LOOP
VOLTAGE GAIN
vs SUPPLY VOLTAGE
INPUT BIAS CURRENT
vs COMMON-MODE VOLTAGE
100
90
NOISE
0N~~~;ON RESISTOR
Z
V
/
L
-20
10k
-30
-12-10-8 -6 -4 -2
0
2
4
6
81012
±5
8
"
7
!
"
±s
±10
±15
SUPPLY VOLTAGE (VOLTS)
".['.----l'-II
'20
'r r I I I /~)V
,",,[\\----jl----j
t;;
5
z
o
laOnA
IIIIII
IIIIII
g ,;".
o~
o
INPUT BIAS CURRENT vs
AMBIENT TEMPERATURE (UNITS
ARE WARMED-UP IN FREE AIR)
OFFSET VOLTAGE DRIFT
vs TEMPERATURE OF
REPRESENTATIVE UNITS
NULLED OFFSET
VOLTAGE DRIFT
vs POTENTIOMETER SIZE
P
±20
±l0
±lS
SUPPLY VOLTAGE (VOLTS)
INPUT COMMON-MODE VOLTAGE (VOLTS)
V
MAX
~~
V' /i:H
1P-rrJ
,/,/
V
100pA
/
-4F--+--~--+-~---+--~--1
-6 L--L__-L__L-~__-L__-L~
-50
-25
o
25
50
TEMPERATURE ec)
5-98
75
100
125
I I
vV'
Vs = ±15V
.- ,/
VS'" ±1SV
III
10pA
10
30
50
70
90
110
130
150
AMBIENT TEMPERATURE (OC)
1/86, Rev. A
---------l~ OP-15/0P-16/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CHARACTERISTICS (OP-1S/0P-16/0P-17)
BIAS CURRENT vs TIME
IN FREE AIR
(OP-1S)
'oA
'oA
ISY = ; ~~~ ~g~ ¥:pxc'tuR~i~s
15SA MAX
lDOpA
OP-1SAMAX
lDOpA
lDnA
J
155ATVV
OP-15AMA~V
156A/1S7A TYP
'oA
~~ ~ V VV
= 25"C
ISY '" 6.7mA FOR MAX CURVES
5.0mA FOR TVP CURVES
100pA
OP.,J TYP
V40
60
80
100
120
140
20
TIME AFTER POWER APPLIED (SEC)
60
80
100
120
'~6~,.LLtV / v
V~/
VI~ v-V vtrrr
V:':'5ATYP
'"
10pA
140
'0
30
50
70
90
110
130
150
AMBIENT TEMPERATURE (OC)
TIME AFTER POWER APPLIED (SEC)
INPUT BIAS CURRENT vs
AMBIENT TEMPERATURE (UNITS
ARE WARMED-UP IN FREE AIR)
(OP-16/0P-17)
lDOnA
40
~,/
V
,
I I
10pA
20
/~
"''Y v"...
OP-16A/OP-17A TVP
t-"
V
/~
Vs - +15V
TA
./
o
,JJJ
156A/1S7 A MAX
7 ,L;;p'6A/Or-17~ L
15SA TYP
10pA
lDOnA
-
Vs'" ±15V
TA = 2S"C
V r-
INPUT BIAS CURRENT vs
AMBIENT TEMPERATURE (UNITS
ARE WARMED-UP IN FREE AIR)
(OP-1S)
BIAS CURRENT vs TIME
IN FREE AIR
(OP-16/0P-17)
SUPPLY CURRENT
SUPPLY CURRENT
vs SUPPLY VOLTAGE
vs SUPPLY VOLTAGE
(OP-16/0P-17)
(OP-1S)
35r---r---,---,---,
55~----r-----.-----'-----'
_30~--~--r---r--~
50~----~----+-----4---~
Y
lanA
156A/157A TY
'oA
"
OP-'6A/
V V
,~ :?~ V v~-:lLLlp
lDOpA
1
~
::;
~
-'
"
~
2.5
1-------::-5=5'-::-Cp.-=-b--=f------/
2SoC
_55°C
~
25°C
::>
~ 20~--~--r---r--~
"V v"
30
50
40
125°C
10pA
10
4.5
125°C
70
90
110
130
JUNCTION TEMPERATURE ("C)
150
'5~--~--~--~-~
±s
±10
±15
o
±20
SUPPLY VOLTAGE (VOLTS)
3.5
0
±5
±10
±15
±20
SUPPLY VOLTAGE (VOLTS)
TYPICAL PERFORMANCE CHARACTERISTICS (OP-1S)
LARGE-SIGNAL
TRANSIENT RESPONSE
SMALL-SIGNAL
TRANSIENT RESPONSE
SETTLING TIME
0.5
'.0
'.5
2_0
25
SETTLING TIME (/-Isec)
5-99
1/86, Rev. A
---------f1EMD
OP-15/0P-16/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CHARACTERISTICS (OP-1S)
BANDWIDTH VI
TEMPERATURE
CLOSED-LOOP BANDWIDTH
AND PHASE SHIFT VI FREQUENCY
18
16
"12
\..
\
m 10
:s 8
z
;;
-
PHASE
90
~AJGI~ ~ ~l
100
Vs = ±15V
120
TA = 25°C
w
\
-10
\ \
1M
!:i
12
~
~
70
OJ 80
a: 50
~a:
~
~
"
I"-
100
~
'\.
1
~TIVE
~
20
:s
J.,
AV
Vs" ±15V
-
-- r--
POllTlVE
-60
-26
60
76
80
~
80
~a:
100
i
40
~"
20
"'"10k
v
"
1\
,
1Q
100
1k
10k
tOOk
1M
10M 100M
VOLTAGE NOISE DENSITY
VI FREQUENCY
,.0
11111111
~ 120
7'
~
80
!!l0
80
I
It~lt~
~ 100
>
>-
T .. 26°C
~
z
1/1 CORNER FREQUENC
w
~g
~
10M
"
10M 100M
\.
VS" :t1SV
TA" 2ir'C
OUTPUT IMPEDANCE
VI FREQUENCY
"-
1M
1M
FREQUENCY(Hz)
t\.
lOOk
tOOk
\
o
125
SUPPLY
I'\.
10k
~
a:
fe)
T
"-
........
0
z
25
~6"C-
l"-
1k
100
iii
AMBIENT TEMPERATURE
TAo
FREQUENCY (Hz)
100
COMMON-MODE REJECTION
RATIO VI FREQUENCY
11111Il\00
20
lk
10
FR EQUENCY 1Hz)
100 r-1'"T1"TT1!1""-I'"T1"T11Tor-o-n"T11Tor-o-nrmm
10
100
I\.
20
~
0L-~--~--~--~~--~~
10M
I"-
30
'\.
126
"- .OS'~'VE""- "-
NEGATIVE
SUPPLY
r--- r-----
10
16
60
10
1M
-- " "
I\.
40
0
40
o
c5
>
SLEW RATE
30
POWER-SUPPLY REJECTION
RATIO VI FREQUENCY
90
80
60
[\.
w
VI TEMPERATURE
~ 40
FREQUENCY (Hz)
o
~
26
-26
1 r-i
tOOk
~100
80
"
"
;!
s
TA -26"C-
-20
-60
60
o
120
- --
PRODUCT
80
...... .....
110
CLlED-Lla. I ._
......... ~IDTHAV=+l
;;
70
~
~ 4
iii
Z
GAIN BANDWIDTH
t-.....
100
~
< 5%
TEMPERATURE reI
1\
.
±20V IS
o
100M
!i
~
< VS "
I--
VS. ±16V
TA-26°C
AV" +1
1\
~ 20
a
~
12
:!
II
10M
FREQUENCY (Hz)
r-,
;24
18
~
z
16
MAXIMUM OUTPUT SWING
VI FREQUENCY
2.
g
........
AV = +1
\.
-6
;
160
20
:;
200
!\ \
-6
150
190
"
-4
~
180
-2
BANDWIDTH VARIATION FROM
±5V
140
170
\
g
2.
V~ ±1lv
r- ........
VS'" ±15V
130
r-- r- \AV> 10 \
6
"
~
120
28
110
!\
OPEN-LOOP GAIN
VI FREQUENCY
10k
lOOk
FREQUENCV (Hz)
5-100
1M
10M
40
20
o
1
10
100
1k
'Ok
FREQUENCY IHzl
1/86, Rev. A
--------I~ OP-15/0P-16/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CHARACTERISTICS (OP-16)
LARGE-SIGNAL
TRANSIENT RESPONSE
SMALL-SIGNAL
TRANSIENT RESPONSE
SETTLING TIME
10
~
~
~
"IE
0
'"z
~
w
'~"
0
>
>-
-.
~:J
0
-10
D.
0
,.
10
20
2.
SETTLING TIME (,lIsee)
CLOSED-LOOP BANDWIDTH
AND PHASE SHIFT
VI FREQUENCY
m
W
\.\.
N
12
~
6
4
g
2
0
00
28
120
+++ ~:(
1 00
1W
2.
100
Vs = ±15V
1~
140
20
80
1 50
16
60
12
.0
\..
\.
\
8 r-AV> 10
tlI
~
PHAJE
\.
aw
i
-
iA
1
26"C
170
180
'\. \
\.
\. \
\
-.
-6
-8
100
1M
10M
100M
28
0
-50
_I
i
=18
~
8
~
~ 4
AV=+l
VS =±15V -
o
10M
-60
tOOk 1M
........
-25
25
---------------------
50
75
100M
1\
1\
\
Vs = ±15V
TA = 25"C
AMBIENT TEMPERATURE (OC)
10M
I\.
20
5-101
--
10k
40
10
"
lk
60
~"'30 ':::-",..
~~E
~
., 20
1M
100
COMMON-MODE REJECTION
RATIO VB FREQUENCY
100
~50
FREQUENCY (Hz)
10
FREQUENCY (Hz)
SLEW RATE
TEMPERATURE
-"
Z40
1"-
1
125
80
1\
o
tOOk
"\.
100
N~GATIJE
so
a~ 12
6
VB
1 1
¥!: ~~~~
AV=+l
~
'"
z 20
I"'\
-20
25
7S
50
TEMPERATURE (OC)
-25
70
I-- t-
'\
BANDWIDTH VARIATION FROM
±5V ... Vs ... ±20V IS < 5%
MAXIMUM OUTPUT SWING
VI FREQUENCY
~24
I~
20
FREQUENCY (Hz)
;;;
[\
200
\. 1\
-10
vJ . ±lsl
TA= 26"C- f--
160
{HASE
~
- r--..
1~
11
AV" +1
OPEN-LOOP GAIN
VB FREQUENCY
BANDWIDTH VI
TEMPERATURE
100
125
o
1
10
100
lk
10k
tOOk
1M
10M 100M
FREOUENCY(Hz)
1/86, Rev. A
-------- - - - - - - - - - - - - - - -
-
----------
---------ilEMD
OP-15/0P-16/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CHARACTERISTICS (OP-16)
POWER-SUPPLY REJECTION
RATIO VI FREQUENCY
~
60
- '" '"
50
I--- "---SUPPLY
i!:
40
a:
30
120
iii
110
.E 100
0
;:: 90
"a:
z
80
~
70
0
~
::>
"!
!i!
"'"
"'-
NEGATIVE
"-
~ 100
~
~
80
"-
III
60
SUPPLY
f'-
10
100
1k
10k
tOOk
IWllU
T
= 25°C
c
oz
"'-
1M
1/f CORNER FREQUENC
w
~
40
g
20
~
o
1111111
~ 120
/'
"- I'\.
10
140
T
POSI~IVE-
"'- t"\.
20
"
IJJI11L
TA=~5°C-
"'-
VOLTAGE NOISE DENSITY
VI FREQUENCY
100 r-rnmn,---rnl11Trr-rnl11Trr-rn"1T111l
"""1
I
"""
f'-
OUTPUT IMPEDANCE
VI FREQUENCY
o
10M
tOOk
10k
FREQUENCY (Hz)
1M
10
1
10M
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
TYPICAL PERFORMANCE CHARACTERISTICS (OP-17)
SMALL-SIGNAL
TRANSIENT RESPONSE
LARGE-SIGNAL
TRANSIENT RESPONSE
SETTLING TIME
+10 . . - - . . . . - - . . . . , . - - - - ; . - - - , - - - - - ,
~
~
~
Vs = ±15V
TA" 26°C
AV= -5
+5~41~~~--+---r--1
~
il:
i"
a ~-+----+--+---+----;
w
~g
~~~~~~--+---+----;
>-
::>
§
CLOSED-LOOP BANDWIDTH
AND PHASE SHIFT
VI FREQUENCY
28
"\. I.....
Vs = ±15V
TA = 25"C
'\.
l\.
2.
18
AV
RS =
12
90
50
110
Vs
"'-
130
PHASE MARGIN" 63"
150
=1 +5
\
soon
Rf = 200kO
170
\
.\ \
\\
\\
20
~
120
±15V
"
~AIN ~ANDWI~TH
-
f-CLOSEDL:
190
FREQUENCY (Hz)
80
r- r--
-... ~+5J.
BANDWIDTH,
-
'\
"
"\.
t"\.
20
""
Vs = ±15V
FROM
-so
"\.
40
r- TA = 25°C
BANDWIDTH VARIATION
100M
,
80
10
±5V.;;;: Vs.;;;: ±lO V IS
10M
I-- 1---",,"
I
100
" " PRODUCT
30
\\
1M
OPEN-LOOP
FREQUENCY RESPONSE
BANDWIDTH VI
TEMPERATURE
40
AV"~O
20
-10 L-_.w..._-L_-"-.L....._-L_.....J
2.5
05
10
15
20
15
SETTLING TIME (psecl
-25
< 5%
25
50
-20
75
TEMPERATURE (OC)
5-102
100
125
1
1
10
100
1k
10k
tOOk
1M
10M 100M
FREQUENCY (Hz)
1/86, Rev. A
-------.. .1fHD
OP·15/0P·16/0P·17 PRECISION JFET·INPUT OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CHARACTERISTICS (OP-17)
SLEW RATE VI
TEMPERATURE
MAXIMUM OUTPUT SWING
VI FREQUENCY
28
110
Vs = ±15V' I
~
~
"z
~
>-
24
I
!
20
I
I
16
::>
:=
6
I
12
""
I
~
IiI
!\
\
i
4
'I
I
lOOk
II
90
i
80
II
r\
!
100
II
I
~
"
~
~~: !~DC 7
...........
............
-50
-25
25
50
75
--
20
Vs = t15V
TA=25"C
I I
10
125
100
100
"
!
i
1'['
;':
i
I
~
40
1.0
%
!< 20
.,
1;
/
1k
10k
t
I
-
'\
-- - -
lk
10k lOOk
FREQUENCY (Hz)
1M
10M 100M
IIIIII I
~ 120
~
I
I
80
w
5"
60
40
g
20
t
o
1
10M
1M
TA=Z5"i
1/1 CORNER FREQUENC
w
"
i
I
100k
~
~
,
I
I
100
Z
I
I
IW11IU
>
>-
I
AV = 10
!
,/
01
10M
il
/
I
/
I'
,
~
.r
./1
I1II1111
A~'~ 100
§ 60
1M
!
140
10
0
i\
.J-
+-- \
f--
Vs = ±15V
>=
a: 80
z
1
\
VOLTAGE NOISE
vs FREQUENCY
100
.!:. 100
0
10k
lOOk
FREQUENCY (Hz)
w
c 40
o
~
z
o
~
OUTPUT IMPEDANCE
vs FREQUENCY
TA=25"C
1k
-t
a:
8
TA=2S"C
100
- - -- - - C--
;J
AMBIENT TEMPERATURE (OC)
.--,---r--.,----,--......,.--,
10
j:: 60
ill
40
10M
\
a:
50
iii
::>
-- ---
80
z
o
........... r-.
POWER·SUPPLY REJECTION
RATIO VI FREQUENCY
ll:
~
r--... r--.....
-
""""-
~
VS= ±15V-
r--...
60
"
100
_I
AV = +5
~ '-!OSITIVE
FREQUENCY {Hz}
120
I
~EGATIVE
70
,
1M
r-.....
COMMON-MODE REJECTION
RATIO VI FREQUENCY
10
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
BASIC CONNECTIONS
INPUT OFFSET VOLTAGE NULLING
SETTLING·TIME TEST CIRCUIT - OP-15/0P-16
2kH 0 1%
+15V
V'
:oy o---.-~2k'VnV'0\r'%-+---"-I
5kU
01%
VOUT
-15V
5kU 0 1%
2N4416
+15V
NOTE Vas CAN BE TRIMMED WITH POTENTIOMETERS
RANGING FROM 10kSl TO lMn FOR MOST UNITS
TevOS WILL BE MINIMUM WHEN Vas IS ADJUSTED
WITH A 100kn POTENTIOMETER
5·103
1/86, Rev. A
II
_ _ _ _ _ _ _----j~ OP-15/0P-16/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
SETTLING-TIME TEST CIRCUIT - OP-17
2kO 0.1%
TYPICAL APPLICATIONS
CURRENT-TO-VOLTAGE AMPLIFIER OUTPUT
A2 5kn
DIGITAL
INPUTS
+10V
MSB
LSB
RAEF
5kn
-
'4
'6
+15V
-1SV
~15V
APPLICATIONS INFORMATION
DYNAMIC OPERATING CONSIDERATIONS
As with most amplifiers, care should be taken with lead dress,
component placement, and supply decoupling in order to
ensure stability. For example, resistors from the output to an
Input should be placed with the body close to the input to
minimize "pick-up" and maximize the frequency of the
feedback pole by minimizing the capacitance from the Input
to ground.
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the Input of the device (usually the Inverting Input) to
AC ground set the frequency of the pole. In many Instances
the frequency of this pole Is much greater than the expected
3dB frequency of the closed-loop gain and consequently
there is negligible effect on stability margin. However, If the
feedback pole Is less than approximately six times the
expected 3dB frequency, a lead capacitor should be placed
from the output to the negative Input of the op amp. The value
of the added capacitor should be such that the RC timeconstant of this capacitor and the resistance It parallels Is
greater than, or equal to, the original feedback pole time
constant.
5-104
1/86, Rev. A
OP-20
MICRO POWER OPERATIONAL AMPLIFIER
(SINGLE OR DUAL SUPPLY)
Precision MOllolithlcs Inc.
FEATURES
•
•
•
•
•
•
•
•
•
•
+30V. or from dual supplies of ±2.5V to ± 15V. The input
voltage range extends to the negative rail. therefore input
signals down to zero volts can be accomodated when
operating from a single supply.
Low Supply Current ........................ 55",A Max
Single-Supply Operation ................ +5V to +30V
Dual-Supply Operation. . . . . . .. . . . . . . .. ±2.5V to ± 15V
Low Input Offset Voltage .................. 250",V Max
Low Input Offset Voltage Drift .......... 1.5",V/oC Max
High Common-Mode Input Range ... V- to V+ (-1.5V)
High CMRR and PSRR .................... 100dB Min
High Open-Loop Gain . . . . . . . . . . . . . . . . . . . .. 120dB Min
No External Components Required
741 Pinout and Nulling
Precision performance in high-gain applications is readily
obtained when using the OP-20. The B/F grade features a
maximum input offset voltage of 250",V. minimum CMRR of
95dB. and open-loop gain of over 500.000. Quiescent supply
current is a maximum of only 55",A at ±2.5V or BO",A at ± 15V.
The low input offset. high gain. and low power consumption
brings precision performance to portable instruments. satellites. missile control systems. and many other batterypowered applications.
ORDERING INFORMATIONt
PACKAGE
T A =25'C
VosMAX
(MV)
250
250
250
500
500
500
1000
TO-99
a-PIN
HERMETIC
DIP
a-PIN
OP20BJ'
OP20FJ
OP20BZ'
OP20FZ
OP20CJ'
OP20GJ
OP20CZ'
OP20GZ
OP20HJ
OP20HZ
PLASTIC
DIP
a-PIN
PIN CONNECTIONS
OPERATING
TEMPERATURE
RANGE
OP20FP
OP20GP
OP20HP
N.C
8
MIL
IND
COM
MIL
IND
COM
COM
_I::QV: OUT
HN~BAL
TO-99
(J-Sufflx)
4
v- (CAse)
'For devices processed in total compliance to MIL-STD-883, add /883 after
part number. Consult factory for 883 data sheet.
tAil commercial and industrial temperature range parts are available with
burn-in. For ordering Information see 1986 Data Book, Section 2.
EPOXY MINI-DIP
(P-Sulflx)
And
a-PIN HERMETIC DIP
(Z-Sulflx)
GENERAL DESCRIPTION
The OP-20 is a monolithic mlcropower operational amplifier
that can be operated from a Single power supply of +5V to
SIMPLIFIED SCHEMATIC
r-----~------.-----------~--~--~--~--------~----~--~~--~-
1\\
II
\
l/
3100
w
V
"~
80
1'..
r--....
>
~
0
~
;r
120
1111111
f-
Vs = ±15V
RL = 25kn
100
TA = 2SoC
\
0
II
CLOSED-LOOP GAIN
VB FREQUENCY
INPUT OFFSET VOLTAGE
POWER SUPPLY VOLTAGE
TRIMMED OFFSET VOLTAGE
VB TEMPERATURE
60
40
80
--
AVCL = 1000
60
1111 I 1111
AVCL = 100
r-
40
20
~
~~I
1111 I I
AVCL = 1
20
NULLED TO ZERO OFFSET AT 25°C
-25
-75
WITH 10k POT
-25
25
o
175
125
75
o
TEMPERATURE (Oel
-
700
~s = ~15v'
12
. / I--"""
...
70
V~ = ±i5V
50
/
300
-50
50
TEMPERATURE (Oe)
100
150
100k
10k
- --
:=t===
...... ~~
TA = 12SoC
500
100
10
100
1k
FREQUENCY (Hz)
1.0
SUPPLY CURRENT
SUPPLY VOLTAGE
60
200
I
111111
VB
600
400
-100
-20
001
±15
INPUT OFFSET CURRENT
VB TEMPERATURE
INPUT BIAS CURRENT
VB TEMPERATURE
14
±5
±10
SUPPLY VOLTAGE (VOLTS)
I'-.
I
- -"
./
40
,/
30
,/
20
I---- J.--"
~
...,.;
--
TA = 2soC ' -
I I I
~55~
10
o
-100
-50
50
TEMPERATURE (Oe)
SMALL-SIGNAL TRANSIENT RESPONSE
100
150
±5
±10
±1S
SUPPLY VOLTAGE (VOLTS)
LARGE-SIGNAL TRANSIENT RESPONSE
OUTPUT
OUTPUT
Rl
CL
25"~100PF
5-109
1/86, Rev. A
------------t~ OP-20 MICROPOWER OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE NOISE DENSITY
vs FREQUENCY
MAXIMUM OUTPUT VOLTAGE
VB LOAD RESISTANCE
1000
CURRENT NOISE DENSITY
vs FREQUENCY
,---r--,---,---,---'
10
'"~
1
OL-_~
1k
10k
01
lOOk
__
~_~
10
__
100
0.0 1
01
~_~
lk
10k
10
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
R LOAD (nJ
.....
TYPICAL APPLICATIONS
TEMPERATURE SENSOR
r------~--------~-----------._-----o+9VOLTS
''''
1kn
100kn
">-""'--0 OUTPUT
DESIGN EQUATIONS
A,VBE
=..!5..!
q
A.VBE = 85,8
~
In
In
(~)
Ie'
('e2)
iC1
!.uVrK]
VOUT'" 10H.6.VBE)
IF
-=
C
1soc
~
60
TA'"
VS=±15V-
28
24
~
40
Vs = ±15V
RL = 10kn
~
20
~
20
16
12
~
"
10
100
1k
10k
lOOk
lk
FREQUENCY (Hz)
10k
lOOk
1M
FREQUENCY (Hz)
5-115
1/86, Rev. A
-------------I~ OP-21 LOW-POWER OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE NOISE DENSITY
VB FREQUENCY
1000 r---r----,r--"T""--.,-----,
~
i1:
~
w
~
10
~
!1:
~
1001-"'C-,,-t---I1---+----t----i
""
1.0
~
~
Q
w
'-t---~---+
a
z
CURRENT NOISE DENSITY
vs FREQUENCY
'"
~
~
a:
10 t---t---II---+----t----i
o. 1
'"
r--....
a:
B
0,0 1
01
10~1--~-~1~0-~10-0-~1k---J,0k
FREQUENCY (Hz)
1.
100
1k
10k
FREQUENCY (Hz)
NONINVERTING
SMALL-SIGNAL RESPONSE
NONINVERTING
LARGE-SIGNAL RESPONSE
OUTPUT
40kD.
10kn
100pF
OUTPUT
100pF
5-116
1/86, Rev. A
OP-22
PROGRAMMABLE MICROPOWER OPERATIONAL AMPLIFIER
(SINGLE OR DUAL SUPPLY)
Precision Monolithics Inc.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Programmable Supply Current .......... lilA to 400ilA
Single Supply Operation ................ + 3V to + 30V
Dual Supply Operation ................ ± 1.5V to ± l5V
Low Input Offset Voltage ...................... lOOIlV
Low Input Offset Voltage Drift ............. O.75IlV/oC
High Common-Mode Input Range ... V- to V+ (-1.5V)
High CMRR and PSRR ........................ l15dB
High Open-Loop Gain ..................... l800V/mV
±30V Input Overvoltage Protection
Unity-Gain Stable
LM4250 Pinout and Nulling
used in circuits with high closed-loop gain. The low offsets
and high gain accuracy of the OP-22 bring precision performance to the micropower field.
GENERAL DESCRIPTION
The OP-22 is a versatile op amp designed for operation from
battery or solar-cell power sources. Supply current is programmable over a range of lilA to 400ilA with a single external resistor. Input voltage range is very wide and extends
down to the negative rail, thus the common-mode input voltage range includes ground when operating from a single
supply voltage. This ability to provide high DC performance
over a wide input range is particularly useful in single-battery
applications. In addition, the OP-22 is characterized over a
wide supply range of ±1.5V-to ±15V, or +3V to +30V for
single supply.
The OP-22 is a monolithic micropower operational amplifier
designed to provide excellent accuracy in high-gain applications. Offsets are very low which generally eliminates any
need for external nulling of Vos. The OP-22 is internally
compensated and unity-gain stable. It also features high
open-loop gain, CMRR, and PSRR. This assures good gain
accuracy and rejection of powersupplyvariationseven when
The OP-22 pin-out and offset nulling are identical to the
LM4250 and many other micropower operational amplifiers.
This functional commonality allows easy upgrading of system performance. By selection of set resistor value, the
circuit designer can readily use the OP-22 in place of such
amplifiers as the LM108, LMl12, LM4250,IlA776, and ICL8021
in high-gain, low-frequency applications.
SIMPLIFIED SCHEMATIC
r-------~------~--------~----------~--~--------~--~------~--~--~--Ov.
OUTPUT
-IN
.,N 0---+---+-------+------1~...J
+--
c,
~~+_------_H~-+--------~--+---~--~------~--------+-------~--~---*--Ov-
5-117
1/86, Rev. A
---------I1fMD
OP-22 PROGRAMMABLE MICROPOWER OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
(Note 2)
NOTES:
Supply Voltage ..••••.•••.•••.•.•••••••••••••••••• ± 18V
Power Dissipation (Note 1) •.••••••••••••••••.••• SOOmW
See table for maximum ambient temperature rating.
Differential Input Voltage .•••••••••••••••••.••••••• ±30V
Absolute raMgsapplyto both DICE and packaged parts. unless otherWise
noted.
Input Voltage ••••.•••••.•... " ••••••••••• Supply Voltage
Storage Temperature Range
J and Z Packages. • • • . • . . . • • • . • • •• ••
-6So C to + lS0° C
Operating Temperature Range
OP-22A, OP-22B (J or Z package)
-SsoC to +12SoC
OP-22E, OP-22F (J or Z package)
•.•
••••
MAXIMUM AMBIENT
TEMPERATURE
Vs = ±15V
and ISET= 10~A
-2SoC to +8So C
OP-22HJ, OP-22HZ •••••••••••••••.•.•.• O°C to + 70°C
Lead Temperature Range (Soldering, 60 sec) •••••• 300°C
DICE Junction Temperature ••••••••••• -6SoC to +lS0°C
ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
OP-22A/E
TYP
MAX
MIN
OP-22B/F
MIN
TYP
MAX
100
200
Vas
Input Offset CUrrent
los
VeM=O
02
Input Bias Current
18
ISET= I~A, VeM =0
ISET = 10"A, VeM = 0
26
19
Input Voltage Range
IVR
V+ =+5V,
V-=OV
Vs = ±15V
Rejection Ratio
Power Supply
Rejection Ratio
(Note 11
CMRR
Vs =±15V
(Note2)
-15V
PSRR
(Note21
S;
124°C
124°C
at Vs = ± 1.SV to ± lSV, 1 ILA S ISET S 10ILA. TA = +2So C, unless otherwise noted.
Input Offset Voltage
Common-Mode
TO-99IJ)
8-Pin Hermetic DIP IZ)
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
VCM :5 +13 5V
300
MIN
500
400
03
3.0
24
30
75
35
40
30
0/35
0/35
0/35
-15/+135
-15/+135
100
95
115
105
85
18
18
1000
05
-15/+135
Vs =±15Vto±15V,
and v-= av,
OP-22H
TYP
MAX
UNITS
~V
nA
10
50
nA
V
95
10
dB
32
"ViV
V+ = 3V to 30V
Vs = ±15V,
'SET = l,uA.
Large-Signal
Voltage Gain
Ava
1000
1800
500
900
250
500
V/mV
1000
1800
500
900
300
500
V/mV
±O 8
±082
±O 8
±082
±075
±O 8
V
±14
±142
±14
±14.2
±135
±14
V
RL = lOOk!!
Vs = ±15V,
ISET= 10,uA,
RL = 10k!!
Vs =±15V,
Output Voltage
Va
Swmg
ISET = I"A, RL = lOOk!! &
ISET = 10"A, RL = 10k!!
Vs =±15V,
ISET= l"A, RL = lOOk!! &
'SET = lO,uA, RL = 10kC}
AveL = +10,
Closed-Loop
BandWidth
BW
Slew Rate
SR
Vs = ±15V,
250
250
250
kHz
008
008
008
V/"s
ISET = 10"A, RL = 10k!!
Vs = ±15V,
Supply Current
No Load
ISY
ISET = 10"A,
RL = 10kn
Vs = ±15V, ISET = l"A
Vs = ± 15V, ISET = 10"A
15
150
17
170
16
160
19
190
18
180
21
210
"A
Vs = ±1 5V, ISET = l,uA
105
105
125
125
14
140
16
160
17
170
20
200
"A
Vs =±1 5V, ISET = 10"A
NOTES:
Sample tested for Single-supply operation, 100% tested for dual-supply
operation
2, Measured With Vas unnutled and ISET constant
5-118
1/86, Rev. A
~
OP-22 PROGRAMMABLE MICROPOWER OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs= ±1.5V to ±15V, 1p.A S ISETS 10p.A, -55°C S TAS+125°C forOP-22AJ/AZ and
OP-22BJ/BZ, -25°C S TA S +85°C for OP-22EJ/EZ and OP-22FJ/FZ, and O°C S TA S +70°C for OP-22HJ and OP-22HZ,
unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
TCVos
Unnulled
OP-22A/E
MIN
TYP MAX
OP-22B/F
MIN
TYP MAX
075
15
10
20
15
30
"V/'C
175
400
350
600
500
1200
"V
nA
25
pA/'C
10
50
nA
MIN
OP-22H
TYP MAX
UNITS
Average Input
Offset Voltage
Dnft (Note 1)
Input Offset Voltage
Vas
Input Offset Current
los
VCM=O
TClos
(NOle 1)
Average Input Offset
Current Drift
Input Bias Current
Input Voltage
Range
VS~±15V
Power Supply
Rejection Ratio
-15V:::; VCM :5 +13 2V
(Note 3)
ISET ~ 1"A
ISET ~ 10"A
PSRR
Voltage Gam
Output Voltage
V
99
105
80
80
90
90
dB
32
10
10
32
32
56
p,V/v
400
200
400
100
250
V/mV
1000
300
750
150
300
V/mV
±O 75
±O 65
±O 75
±O 6
±07
200
V
Vs
No Load
ISY
±136
±136
±138
±130
±138
±135
V
Vs == ±15V. ISET = l,uA
Vs = ±15V, ISET -= 10,uA
16
160
18
180
17
170
20
200
20
200
25
250
"A
Vs =±15V, I SET 1.uA
Vs = ± 1 5V, ISET = 10,uA
12
120
14
140
15
150
18
180
19
190
25
250
"A
'=;
NOTES:
Sample tested
2 VCM~ 1 5V
3
ORDERING INFORMATIONt
Measured With Vas unnulled and I SET constant
PIN CONNECTIONS
PACKAGE
(/LV)
TO-99
8-PIN
HERMETIC
DIP
a-PIN
OPERATING
TEMPERATURE
RANGE
300
300
500
500
1000
OP22AJ'
OP22EJ
OP22BJ'
OP22FJ
OP22HJ
OP22AZ'
OP22EZ
OP22BZ'
OP22FZ
OP22HZ
MIL
IND
MIL
IND
COM
TA = 25°C
VOSMAX
P;
~
~
0......
~
~
P;
0
ISET = 10,uA, RL = lOki!
Supply Current
~......
P-<
......
......:I
......:I
V+= 3V to 30V INote 21
= ±15V,
ISET ~ 1"A. RL ~ 100kn &
SWing
0/3.2
-15/+132
80
86
105
115
V- ~ OV.
Vs::O ± ISV,
bOO
I SET ;:; 10jJ.A, RL 10k!!
------,----_.
Vs = ±1 5V,
±o 65
'SET = 1/J-A, RL "'- 10m,!} &
' SET ::;; 10p.A, Rl = 10k!}
Va
4.5
34
Vs::::: ± 1 5V to ± 15V &
'SET =- 1J1A, RL _. 100kn
Ava
7.5
35
0/32
-15/+132
80
90
Vs = ±15V,
Large-Signal
33
27
= ±15V
CMRR
(Note 31
15
5
30
0/32
-15/+132
V+~+5V. V-~OV
Vs
Common-Mode
Rejection Ratio
28
21
ISET ~ 10"A. VCM ~ 0
IVR
05
10
ISET ::::: lJ.tA, VCM :::: 0
18
03
02
.. NOTE DO NOT SHORT PIN 8 TO v- OR GROUND
SEE APPLICATIONS INFORMATION
ISET*
8
~e·
IN 2
- ! -
+IN 3
BAL
6 OUT
5 BAL
4
v- (CASE)
'For devices processed in total compliance to MIL-STD-883, add /883 after
part number. Consult factory for 883 data sheet
TO-99
(J-Sufflx)
tAli commercial and Industrial temperature range parts are available With
burn-in. For ordering information see 1986 Data Book, Section 2
5-119
8-PIN HERMETIC DIP
(Z-Sufflx)
1/86, Rev, A
---------I~ OP-22 PROGRAMMABLE MICROPOWER OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
1. BALANCE
2. INVERTING INPUT
3. NON INVERTING INPUT
4. V5.
6.
7.
8.
For additional DICE Information refer to
1986 Data Book, Section 2.
DIE SIZE 0.069 X 0.049 Inch, 3381 sq. mils
(1.75 X 1.24 mm, 2.18 sq. mm)
WAFER TEST LIMITS at Vs = ±1.5V to
±15V, 11'A:5 ISET:5 10I'A, TA
PARAMETER
SYMBOL
Input Offset Voltage
VOS
Input Offset Current
los
(Note 11
Input Bias Current
18
ISET= 11'A
ISET= 1Ol'A
Input Voltage Range
IVR
V+ = +5V, V- = OV
Vs=±15V
Common-Mode
Rejection Ratio
CMRR
Vs = ±15V, -15V S VCM S +13,5V
(Note 2)
Power Supply
Rejection Ratio
PSRR
Vs =±1,5Vto±15V
V- = OV, V+ = 3V to 30V (Note 21
Large-Signal
Voltage Gain
Output Voltage
Swing
Supply Current
No Load
Avo
Vo
ISY
BALANCE
OUTPUT
V+
ISET
CONDITIONS
(Note 11
= 25° C, unless otherwise noted.
OP-22N
OP-22G
OP-22GR
LIMIT
LIMIT
LIMIT
UNITS
300
500
1000
I'VMAX
3
nAMAX
30
7,5
35
10
50
nAMAX
0/3,5
-15/+13,5
0/3,5
-151+13,5
0/3,5
-15/+13,5
VMIN
100
95
85
dB MIN
18
32
I'VIV MIN
Vs= ±15V,
ISET= 11'A, RL = 100kO,
1000
500
250
V/mV MIN
Vs = ±15V,
ISET= 10I'A, RL = 10kO,
1000
500
300
V/mV MIN
Vs = ±1,5V,
ISET= 11'A. RL = 100kO &
ISET= 10I'A, RL = 10kO,
±0,8
±0,8
±0,75
VMIN
Vs =±15V,
ISET = 11'A, RL = 100kO &
ISET = lO/lA, RL = 10kO,
±14
±14
±13,5
VMIN
Vs =±15V,l sET =1I'A,
Vs = ±15V, ISET = lO"A
17
170
19
190
21
210
I'AMAX
Vs =±1,5V, ISET= 11'A.
Vs = ±1,5V, ISET= 1OI'A,
12,5
125
16
160
20
200
~MAX
NOTES:
1, VCM=O
2, Measured with Vas un nulled and ISET held constant.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice, Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing,
TYPICAL ELECTRICAL CHARACTERISTICS at
noted,
PARAMETER
SYMBOL
CONDITIONS
Average Input
Offset Voltage Drift
TCVos
Unnulled
Large-Signal
Voltage Gain
Avo
Vs= ±15V
ISET = 1/lA, RL = 100kO &
ISET = 10I'A, RL = 10kll
Vs
= ±1.5V to ±15V, 11'A :5ISET:510I'A, TA = +25°C, unless otherwise
5-120
OP-22N
OP-22G
OP-22GR
TYPICAL
TYPICAL
TYPICAL
UNITS
1,0
1,5
2,5
I'V/'C
1800
900
500
V/mV
1/86, Rev. A
----------1~ OP·22 PROGRAMMABLE MICROPOWER OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
,.
1000
'00
TA .. 25 c
IJs 1'!5V I
e
Vs • ±1.5V
VS·±15~
ASET TO GND
;;
j
100
I-
Vs· ±16V
RSETTOV-=
10
¥
VS ·±15V
v:.VS ·t1.5V
.3
~
VB
TA -25 Ge
TA ·26 C
'00 F=
BIAS CURRENT
SET CURRENT
SUPPLY CURRENT
VB SET CURRENT
SET CURRENT
SET RESISTOR
VB
ill
'0
'"
a'"
a'"'"
..
~
t;; ,
~
Vs" ±1.SV
RSET TO GND
0,'
~
10
Vs· ±1.6V
RSET TO V-
0.01
100k
'Ok
1M
10M
seT RESISTOR
,~
0,'
0,'
100M
,
'0
SET CURRENT (,uAI
~m
OFFSET CURRENT
VB SET CURRENT
1000
¥:: i~o6CV
0.1
'00
1
'000
'30
TO t16V
I I IIIII
12.
~
'00
~
EAT Vs· ±1.5V TO ±16V
122
1260
./
~5'
~
o
,,
-
/
'0
11.
_55 0
-
1'1
I 1.56' I
,
OP'22~
116
I
"'
110
'D.
'06
'D'
'02
ts .1±1,~vlid ;,I~v
I I IIIII
I
I 11111
"'
HAT Vs· ±1.5V TO t16V
110
, I I IIIII '0
",
'00
PHASE MARGIN
vs SET CURRENT
Vs = ±15V
90
T A"" 2s Q e
VB
,
,
OP·22F
I
I
OP·22H
SLEW RATE
SET CURRENT
¥!: ~~~~
-+-++I+H--t--l-+-+++t-H
.0 ~+:R:+:I:tttt-It111tt11
I
'00
SET CURRENT tuA)
SET CURRENT (pA)
COMMON·MODE REJECTION
VB SET CURRENT
11.
I
'0
'00
seT CURRENT (IlA)
'20
FAT
11.
25'
~
I I IIIII
120
it , 0
'0
F ATVS· 3V TO 30V
12.
100
TA _2e G e
EATVS-3VT030V
12.
>
'00
POWER SUPPLY REJECTION
VB SET CURRENT
OFFSET VOLTAGE
VB SET CURRENT
I
10
seT CURRENT !,uA)
0,0
/
,
/
1
Vs .1±15V
T A " 2sC e
'0
SET CURRENT (IlA)
'00
10
SET CURRENT ("A)
5·121
'00
0.00
,
0,'
,
'0
'00
SET CURRENT (MA)
1/86, Rev. A
_ _ _ _ _ _ _ _---j~ OP·22 PROGRAMMABLE MICROPOWER OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
GAIN·BANDWIDTH PRODUCT
vs SET CURRENT
1M
Vs
TA
--
±15V
1:':-
2SOC
15 a
70
145
60
140
1/
13a
12 5
/
!I
40
.....
i---
"'" f-/\.. r-...
~
30
~~ ~"'\.
~ !\:.OiJA
10,AJ
~'\ ~'\.
'SET = l,.A
20
12a
I
Vs = ±15V
TA '" 2SOC
AVCL = 100
50
135
I
lOOk
FREQUENCY RESPONSE
vs SET CURRENT
OPEN·LOOP GAIN
vs SET CURRENT
5,A
10k
10
11 5
"
11 a
1k
V
01
1
10
SET CURRENT CuA)
-10
105
II
I
10a
CLOSED·LOOP
FREQUENCY RESPONSE
120
140
60
-.........
40
20
,
120
100
-
100
10k
1k
100k
12a
......
01
....... .......
"'......
10
40
40
! 111111
vllJU~1
30
I
I111I11
TA = 25°C
30
"
>'"
25
"z
vJ=U,IW
20
~
>-
~
15
1111111
1.5
~
::>
0
~
10
~
25
ISET = l/JA
I
10
'1/
a
"
a
10k
a
01
10
"' "
100
1k
10k
FREQUENCY (Hz)
VOLTAGE NOISE
vs FREQUENCY
+15=\
.II +5-,
il;
20
=10'j,\
a
100k
35
1-
'SET
1k
100
"
a
MAXIMUM OUTPUT CURRENT
vs SET CURRENT AT
Vs = ±15V, +5 AND ±1.5
PEAK-TO·PEAK
OUTPUT SWING
vs LOAD RESISTANCE
35
10a
""-
FREQUENCY (Hz)
FREQUENCY (Hz)
~
"'-rOSIT1VE
NEGATIV~
a
1M
ISET'" 10,.A
14a
20
-60
10
"
>'"
Vs = ±15V
16a
40
-40
1M
18a
Vs'" ±15V
ISET = lO.uA
60
.........
""
lOOk
COMMON-MODE REJECTION
vs FREQUENCY
80
"'
-20
10k
POWER SUPPLY REJECTION
vs FREQUENCY
160
80
lk
FREQUENCY (Hz)
180
~!: ~~~~
100
SET CURRENT (pA)
ISET = 10iJ.A
100
~
100
10
100
-20
10
1-
"z
>-
~
::>
~
+15
<1
10k
.3
>~
~
::>
"::>>-
V': \01'
v-:: ~
1k
rJ....\. -15
-15
v-::
j:
::>
0
100
"-~
0
05
a
100
a
1k
10k
lOOk
LOAD RESISTANCE (nJ
1M
10
01
10
SET CURRENT (pAl
5·122
100
10 L-...I....Ll..LL1.llL.....L...I...Wllll._Ll.illllll
0.1
10
100
FREQUENCY (Hz)
1/86, Rev. A
---------IIEHD
OP·22 PROGRAMMABLE MICROPOWER OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
CURRENT NOISE
vs FREQUENCY
SUPPLY CURRENT
vs TEMPERATURE
10
17
Vs - ±15V
TA - 2SOC
Vs" ±15V
~
~
16
V
15
:::::-
~ 14
~
---
BIAS CURRENT
vs TEMPERATURE
'SET
~ l/lA
'SET" lOIlA
II
10
11
iil
'SET'" lilA
01
01
>
~
100
~
150
"
>w
~
140
'SET - 10ilA
ISET
--
'SET = lOMA Vs
=
±1 s v - I - - 20
[--.
3
~~'SET -
r-....
15
:0
2
I--,:;;,;,A Js,,,15VTb,;~ f',
10
lOjlA Vs
+15V
I--
[\
~
1,A
............
is
9
-75
-50
-25
25
50
75
100
o
90
125
-75
-50
-25
~
1
>-
~
::>
is
o
25
50
75
TEMPERATURE (Oel
lOa
!
">-w
"~
100
FREQUENCY (Hz)
"~
~
1
>1l
~, 10
10
4
~
120
Vs = 1 5V
25
5
~
130
~
12
160
'SET = lOJjA
>~ 13
i3
30
170
125
-~
~
.......
>.Lo
~
(:l;
OFFSET CURRENT
vs TEMPERATURE
iSET - 1 TO 10pA
Vs = ±1 5V TO ±15V
'SET = 10pA
80
60
>~
40
1M
20
-- r-- - ~
0
.......
"""" r--
~
VS-+3V_
~
~
(:l;
r-
::>
tu" -20
if
.......... t-..,
~ -40
0
lOOk
........
-60
AV" +1, C L = 30pF
'SET = 50l-lA
-80
Vs = ±15V
-100
-75
-50
-25
25
~
~
10M
100
!
SMALL·SIGNAL
TRANSIENT RESPONSE
OPEN·LOOP GAIN
vs TEMPERATURE
50
75
100
125
10k
-75
-45
TEMPERATURE (Oel
SMALL·SIGNAL
TRANSIENT RESPONSE
-15
15
45
75
105
135
TEMPERATURE (Oel
SMALL-SIGNAL
TRANSIENT RESPONSE
SMALL·SIGNAL
TRANSIENT RESPONSE
AV '" +1, CL '" 30pF
AV = +1, CL = 30pF
AV = +1, C L = 30pF
'SET = lilA
Vs'" ±15V
ISET
Vs" ±15V
'SET = 100tlA
Vs = ±lSV
=
lO/1A
5·123
1/86, Rev. A
----------l1fHD
OP-22 PROGRAMMABLE MICROPOWER OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
SMALL-SIGNAL
TRANSIENT RESPONSE
SMALL-SIGNAL
TRANSIENT RESPONSE
SMALL-SIGNAL
TRANSIENT RESPONSE
AV '" +10, CL '" 30pF
'SET = lpA
Vs = ±15V
APPLICATIONS INFORMATION
OP-22 series units may be inserted directly into LM4250,
!LA776 and ICL8021 sockets with or without removal of
external nulling components. The value of set resistor for a
given supply current varies between types and the manufacturer's data sheets should be consulted for this information.
Table 1 compares set resistor values for the OP-22 and the
LM4250. (RSETconnected to V-).
Biasing the OP-22 with a fixed resistor produces a supply
current approximately proportional to supply voltage. In
applications where a constant drain is required with varying
supply, RSET can be replaced by current generators. Two
suggested arrangements are shown below:
la)
TABLE 1
Supply Current VS, Set Resistor for OP-22 and LM4250
ISY= 1O!LA
VSUPPLY
±1.5V
±3.0V
±5.0V
±12V
±15V
ISET
OP-22
2.2Mfl
6.8Mfl
13Mfl
33Mfl
43Mfl
O.67!'A
LM4250
1.3Mfl
2.7Mfl
4.7Mfl
12Mfl
15Mfl
1.B!,A
ISY= 30"A
OP-22
6BOkfl
2.2Mfl
4.3Mfl
11Mfl
15Mfl
20!,A
LM4250
430kfl
910kfl
1.5Mfl
3.9Mfl
5.1Mfl
6.0!'A
ISY= 100"A
OP-22
220kfl
680kfl
1.3Mfl
3.3Mfl
4.3Mfl
6.7!'A
LM4250
120kfl
270kfl
470kfl
1.2Mfl
1.5Mfl
20!,A
Rl
v-
Ib)
SET-RESISTOR SELECTION
10Mn
The value of set resistor for selected supply current may be
calculated using the "Supply current vs. Set current" curve
and the formula;
RSET= (VSUPPLY - 2V SE) .....•...•.............•..... (1)
ISET
2,
2N930
Alternatively, the "Supply Current vs. Set Current" graph may
be used in conjunction with the "Set Current vs. Set Resistor"
graph. VSUPPLY in formula (1) refers to the total supply
voltage with RSET connected between pin 8 and negative
supply. RSET may be connected to ground in which case
VSUPPLY in (1) is the positive supply.
CAUTION: Shorting of pin 8 to negative supply or ground
will cause excessive ISET which in turn will cause excessive
supply current to flow. ISET should always be limited.
5-124
1/86, Rev. A
----------I1fHD
OP-22 PROGRAMMABLE MICROPOWER OPERATIONAL AMPLIFIER
OFFSET VOLTAGE ADJUSTMENT
APPLICATIONS CIRCUITS
The offset vOltage can be trimmed to zero using a 100kO
potentiometer (see offset nulling circuit). Adjustment range
is approximately ±5mV. Resolution of the nulling can be
increased by using a smaller pot in conjunction with fixed
resistors as shown below.
A micropower bandgap voltage reference operating at a
quiescent current of 15/LA may be constructed using an OP22 and a MAT-01 dual transistor (see Figure 1). The circuit
provides a 1.23V reference with better performance than
micropower I.C. shunt regulators and has the advantages of
being a series regulator.
MICROPOWER 1.23 VOLT BANDGAP REFERENCE
39kn
39kn
20kn
PIN 1 o-----v'w----vW~--___v'VV'---__o PIN 5
SUPPLY
+3V TO +30V
1-
lN914
This arrangement has a ±500/LV adjustment range. Offset
nulling of the OP-22 has negligible effect on the value of
TCVos·
Vour'" 1 23V
a-SmA
OFFSET NULLING CIRCUIT
v+
22Mn
OUTPUT
INPUT
ov
QUIESCENT CURRENT, 15~A AT 5V INCREASING TO 20J.,lA AT lOV
OUTPUT VOLTAGE TEMPERATURE COEFFICIENT (OVER OC TO 70"C), 20ppml"C TYP
LINE REGULATION, 0 01%/VOL T
LOAD REGULATION, 000l%/mA
100kn
RSH
Figure 1
v-
GATED MICROPOWER AMPLIFIER
+5V
GAIN'" 50
BURN-IN CIRCUIT*
500kn
+18V
470nF
o--------j I----w>l---+--<-""""
OUTPUT
2!"-- 7
6
OP-22
3+/'
v.
~
INPUT
OUTPUT
OV
36Mn
...............
-lav
Figure 2
·Other CIrcuits may apply at PMl's discretion
5-125
1/86, Rev. A
---------I~ OP-22 PROGRAMMABLE MICROPOWER OPERATIONAL AMPLIFIER
MICROPOWER INSTRUMENTATION AMPLIFIER - POWER DRAIN ~ 3mW WITH ±5 VOLT SUPPLIES
r----.------------------~------._----------------------~~--------------O~v
OFFSET ADJUST
1M!!
1k!!
300kO
01%
l00nF
3OOk!!
01%
MAXIMUM
OUTPUT :t3V
RL ;> 3OkO
22Mn
50pF
OV
50pF
SOp'
-5V
-5V
VOLTAGE GAIN
111m-
Rt = R4
R2 = R3
20kfl:
DUAL TRANSISTOR
MAT.Q1AH
-IN
FD333
R2
R3
R4
1kn01%
1kno 1%
500kn 0 1%
499kn 0 1%
INPUT BIAS CURRENT
2kn CMRR ADJUST
OV
+INo-----------------______________________________________
< lDnA
CMRR> 100dB "80Hz
PSRR > 70de
TC Vas < 02p.V/"C
NONLINEAR lTV < 0 001%
(Av = 500)
~
Figure 3
In Figure 2, the OP-22 is used as a gated amplifier where
power consumption and bandwidth are controllable. Rs can
be selected for a specific lower-power operation or omitted
so the amplifier can be completely shut down.
TWO TERMINAL 4-20mA TRANSMITTER
+5 VOLT
REFERENCE
2mAMAX
A micropower instrumentation amplifier that consumes less
than 3mW with ±5V supplies is shown in Figure 3. Offset
voltage drift is less than 0.2".v/oC and common-mode
input range is ±3V with CMRR of over 100dB at 60Hz.
5kU 1%
Process control systems use two-wire 4-20mA current transmitters when sending analog signals through noisy environments. The "zero" or "offset" current of 4mA may be used to
power the transmitter signal conditioning amplifiers and/or
excite a d.c. transducer. This allows remote signal conditioning without having a remote power source. Power is provided
at the receiving end where the signal current is monitored by
a precision son resistor. The 4-20mA transmitter shown in
Figure 4 has high stability, excellent linearity, and generates
the 4-20mA current output. A 5V reference is available for
powering transducers and micropower amplifiers at a maximum current of 2mA.
SIGNAL
SOURCE
0-10OmV
lOon 1%
80kn 1%
~----~~-------------------110
COMPLIANCE
LINEARITY
Figure 4
5-126
10 VOLT TO 40 VOLT
.
.
I
0002% OF SPAN
LINE REJECTION, OFFSET
0 002%/VOL T
SPAN.
. DOO6%NOLT
TEMPERATURE COEFFICIENTS. OFFSET
. 0002%fC
(_25°C TO +8SoCI
SPAN
a D01%jOe
1/86, Rev. A
-----------l~ OP-22 PROGRAMMABLE MICROPOWER OPERATIONAL AMPLIFIER
MICROPOWER WIEN-BRIDGE OSCILLATOR (Pd < 500ILW)
-=-9V
~----------------~--~VOUT
3Vp-p AT 1kHz
Al - OP·22
01, D2 - lN914
THD <05%ATVour=3Vpp
Figure 5
MICROPOWER 5 VOLT REGULATOR
QUIESCENT CURRENT"" 50,uA AT 9V
LOAD REGULATION, 0 001% I rnA
LINE REGULATION, 0 01% / VOLT
TEMPERATURE COEFFICIENT, 40ppm;oC (_25°C TO +85 C)
Q
+6 5V';;; VIN .;;;; +30V
r-----t----o
301kD
1%
100kn
1%
1Mn
l1kH
1%
D1
301kn
1%
+5V
OUTPUT
(10mAMAX)
10M.I1
D2
SET
OUTPUT
20kD
4---~----~--~-----------4----~--~-------4------o0V
Al, A2 - DP·22, Q1 - 2N2222
D1, 02 - MAT·Ol OR MATCHED DIODES
Figure 6
Ie regulators typically draw 2mA to SmA quiescent current
compared to only SOILA with this discrete implementation.
Maximum load current is 10mA as shown, and can be
increased by changing Ql to a power transistor and proportionately increasing the set current of A2.
Figure S shows a micropower Wien-bridge oscillator
designed for battery-powered instrumentation. Output level
is controlled by nonlinear elements Dl and D2. When
adjusted for 3V p-p output, the distortion level is below O.S%
at 1 kHz.
The S volt regulator in Figure 6 is intended for instrumentation requiring good power efficiency. Low-power 3-terminal
5-127
1/86, Rev. A
OP-27
LOW-NOISE PRECISION
OPERATIONAL AMPLIFIER
PrCClSl0U
Monolithics Inc
FEATURES
L
•
•
N I
ow
{ ... 80nV
(0.1 Hz to 10Hz)
p_p
0................. ...............
3nV/.jiiZ'
•
Low Drift ......•..•...•...........•........ 0.2p.VfO C
d
{ . . . . . . .. 2.8V/ p.8 Slew Rite
HI h S
g
pee.. .. .. .. .. .. .. .. .. 8MHz Glln Blndwldth
•
•
•
•
Low Vas ....................................... 10p.V
Excellent CMRR ............... 126dB It VCM of ±11V
High Open-Loop Glln .... .. .. .. .. .. .. .. ... 1.8 Million
Fits 725, OP-07, OP-05, AD510, AD517, 5534A locketl
ORDERING INFORMATIONt
A low input bias current of ±10nA Is achieved by use of a
bias-current-cancellation circuit. Over the military temperature range, this circuit typically holds IB and los to ±20nA
and 15nA respectively.
The output stage has good load driving capability. Aguaranteed swing of ± 10V Into 600n and low output distortion make
the OP-27 an excellent choice for professional audio applications.
PSRR and CMRR exceed 120dB. These characteristics,
coupled with long-term drift of 0.2p.Vlmonth, allow the circuit
designer to achieve performance levels previously attained
only by discrete designs.
PACKAGE
TA = 25'C HIRMETIC HERMETIC
TO-It
DIP
Voa MAX
(pV)
a·PIN
a·PIN
25
26
60
60
100
100
OP27AJ'
OP27EJ
OP27BJ'
OP27FJ
OP27CJ'
OP27GJ
PLASTIC
DIP
a·PIN
OP27AZ'
OP27EZ
OP27SZ'
OP27FZ
OP27CZ'
OP27GZ
LCC
OP27EP
OP27BRC/883
OP27FP
OP27GP
OPERATING
TEMPERATURE
RANGE
PIN CONNECTIONS
MIL
INO/COM
MIL
INO/COM
MIL
INO/COM
BALttiBAL.7V+
-IN2
lOUT
+IN 3
'For device. processed In total compliance to MIL-STD-883. add 1883 after
part number. Consult factory for 883 data sheet.
tAli commercial and Industrial temperature range parts are available with
burn-In. For ordering Information see 1986 Data Book. Section 2.
6 N.C.
4 V-ICASE)
TO-SS
(J-Sufflx)
8-PIN HERMETIC DIP
(Z-Sufflx)
EPOXY MINI-DIP
(P-Sufflx)
GENERAL DESCRIPTION
The OP-27 precision operational amplifier combines the low
offset and drift of the OP-07 with both high-speed and lownoise. Offsets down to 25p.V and drift of 0.6p.V/oC maximum
make the OP-27 Ideal for precision Instrumentation applications. Exceptionally low noise, en = 3.5nV/y'Hz", at 10Hz, a
low 1/f noise corner frequency of 2.7Hz, and high gain (1.8
million), allow accurate high-gain amplification of low-level
signals. A gain-bandwidth product 018MHz and a 2.8V1p.sec
slew rate provides excellent dynamic accuracy In high-speed
data-acquisition systems.
OP-27BRC/883
LCC PACKAGE
(RC-Sulllx)
SIMPLIFIED SCHEMATIC
r-----~--------~------~--~--~----~------~~~_4~v.
OUTPUT
NON·
INVERTING
INPUT!o:'I-t--t"""1-t---lE:-i~
INVERTING
INPUT<>-H..........--<~_ _ _ _ _
-+____--'
• R1 &. A2 ARE PERMANENTL V ADJUSTED
AT WAFER TEST FOR MINIMUM
OFFSET VOL TAoe
~---------+--~----+-------~+-"""~~v-
5-12S
1/86, Rev. A
-----------l1rHD OP-27 LOW-NOISE PRECISION OPERATIONAL AMPLIFIER
Low cost, high-volume production of OP-27 is achieved by
using an on-chip zener-zap trimming network. This reliable
and stable offset trimming scheme has proved its effectiveness over many years of production history.
Operating Temperature Range
OP-27A, OP-27B, OP-27C (J, Z, RC) .. ,. -55° C to +125° C
OP-27E, OP-27F, OP-27G (J, Z) ....... -25°C to +85°C
OP-27E, OP-27F, OP-27G (P) ............ 0° C to +70° C
Lead Temperature Range (Soldering, 60 sec) ...... 300° C
DICE Junction Temperature ......... " -65° C to + 150° C
The OP-27 provides excellent performance in low-noise
high-accuracy amplification of low-level Signals. Applications include stable integrators, precision summing amplifiers, precision voltage-threshold detectors, comparators,
and professional audio circuits such as tape-head and
microphone preamplifiers.
NOTES:
1.
The OP-27 is a direct replacement for725, OP-06, OP-07 and
OP-05 amplifiers; 741 types may be directly replaced by
removing the 741 's nulling potentiometer.
See table for maximum ambient temperature rating and derating factor.
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
PACKAGE TYPE
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
TO-99 (JI
BO'C
7.1mW/'C
B-Pin Hermetic DI P (ZI
7S'C
6.7mW/'C
ABSOLUTE MAXIMUM RATINGS (Note 4)
B-Pin PlastiC DIP (PI
62'C
S.6mW/'C
Supply Voltage ................................... ±22V
Internal Power Dissipation (Note 1) .............. 500mW
Input Voltage (Note 3) ............................ ±22V
Output Short-Circuit Duration ................. Indefinite
Differential Input Voltage (Note 2) ................ ±0.7V
Differential Input Current (Note 2) ............... ±25mA
Storage Temperature Range. . . . . . . . . .. -65° C to + 150° C
LCC
BO'C
7BmW/'C
2.
The OP-27's inputs are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise. If differential input
3.
4.
voltage exceeds ±0.7V, the input current should be limited to 2SmA.
For supply voltages less than ±22V, the absolute maximum input voltage is
equal to the supply voltage.
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = 25° C, unless otherwise noted.
OP-27A/E
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Long~Term
Vos
Stability
loS
Input Bias Current
Ie
Input Nol.e Voltage
e np _p
Input Noise
Input Nol.e
Current Density
en
In
Input ReslstanceDifferential-Mode
Input ReslstanceCommon-Mode
Input Voltage Range
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
Large-Signal
Voltage Gain
RIN
Slew Rate
OP-27B/F
MAX
TYP
MAX
UNITS
25
20
60
30
100
"V
1.0
0.3
1.5
0.4
2.0
"VIM a
50
12
75
nA
MAX
10
0.2
MIN
35
±40
±12
±5S
±15
±80
nA
O.OB
0.18
0.08
0.18
0.09
0.25
"VP-P
fo
3.5
5.5
3.5
5.5
3.8
8.0
fo
3.1
4.5
3.1
4.5
3.3
5.8
3.0
3.8
3.0
3.8
3.2
4.5
0.1 Hz to 10Hz
(Note. 3, 61
= 10Hz (Note 31
=30Hz (Note 31
fo = 1000Hz (Note 31
fo = 10Hz (Notes 3,81
fo = 30Hz (Notes 3.61
fo = 1000Hz INotes 3,81
1.7
4.0
1.7
4.0
1.7
1.0
2.3
1.0
2.3
0.4
0.6
0.4
0.6
1.0
0.4
1.3
INote 71
0.94
= ±11V
VOM
PSRR
Vs
Avo
RL " 2kll, Vo = ±10V
RL c eoon, Vo = ±10V
pA/yHz
0.7
Mil
Gn
±11.0
±12,3
±110
±12.3
±11.0
±12.3
V
114
128
106
123
100
120
dB
=±4V to ±18V
10
10
20
1000
1800
1000
1800
700
800
1500
800
1500
600
1500
RL " 2kll
±12.0
±13.8
±12.0
±13.8
±11.5
±13.5
RL " 80011
±10.0
±11.5
±10.0
±115
±10.0
±ns
17
2.8
17
2.8
1.7
28
RL " 2kn INote 41
5-129
-------~-~-------~-
~---~-.~--
~
nV/yHz
0.8
2.5
CMRR
SR
MIN
±10
IVR
Vo
OP-27C/G
TYP
TYP
R'NOM
Output Voltage
Swing
(Note tl
Vos/Tlme (Note. 2, 31
Input Offset Current
Voltage Density
MIN
1500
"VIV
VlmV
V
VI"s
1/86, Rev. A
-----------I~ OP-27 LOW-NOISE PRECISION OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = 25°C, unless otherwise noted. (Continued)
OP-27A/E
PARAMETER
SYMBOL CONDITIONS
Gam Bandwidth Prod GBW
Open-Loop Output
(Note41
MIN
TYP
50
80
_P_o_w_e_rC_o_n_s_u_m~p_tlo_n___P~d______V~e~_______________________ 90
Offset Adjustment
Rp~
Range
MIN
TYP
50
80
70
Ve~O,le~O
Resistance
OP-27B/F
MAX
10kn
OP-27C/G
MAX
MIN
TYP
50
80
MHz
70
n
70
140
90
140
100
±40
±40
NOTES:
1 Input offset voltage measurements are performed - 05 seconds after
application of power. AlE grades guaranteed fully warmed-up
2. Long-term input offset veltage stability refers to the average trend line of
Ves vs. Time over extended penods after the first 30 days of operallon
Excluding the initial hour of operation, changes In Ves dUring the first 30
3
MAX
170
±4.0
UNITS
mW
mV
days are typically 2 5/lV - refer to typical performance curve.
Sample tested
4. Guaranteed by design
5
See test CIrcuit and frequency response curve for 0.1 Hz to 10Hz tester.
6
7.
See test CircUit for current nOise measurement
Guaranteed by Input bias current.
ELECTRICAL CHARACTERISTICS for Vs = ±15V, -55°C:s TA:S +125°C, unless otherwise noted.
OP-27B
OP-27A
TCVes
TCVeSn
los
Ie
Input Voltage Range
IVR
Common-Mode
Rejection RatiO
Power Supply
ReJectton RatiO
CMRR
PSRR
Vs
AVO
R L ,,2kll,
Large-Signal
Voltage Gam
70
300
06
03
13
0.4
18
!lVl'C
02
Average Input
Input BIBS Current
200
(Note21
(Note 31
Ves
Input Offset Current
MAX
50
30
Input Offset Voltage
Offset Dnft
TYP
60
(Note II
CONDITIONS
~
Output Voltage
SWing
MIN
UNITS
15
50
22
85
30
135
nA
±20
±60
±28
±95
±35
±150
nA
±103
±115
±103
±115
±10 2
±11.5
V
108
122
100
119
94
116
dB
16
±4 5V to ±18V
VO~±10V
MIN
OP-27C
MAX
MAX
SYMBOL
MIN
TYP
TYP
PARAMETER
4
20
51
!lVN
600
1200
500
1000
300
800
VlmV
±115
±135
±110
±132
±105
±130
v
ELECTRICAL CHARACTERISTICS for Vs = ±15V. -25°C:S TA:S +85°C for OP-27J and OP-27Z. O°C:s TA:S +70°C for
OP-27P. unless otherwise noted.
OP-27F
OP-27E
PARAMETER
SYMBOL
Input Offset Voltage
Ves
Average Input
TCVes
TCVOS n
Offset Drift
Input Offset Current
los
Input BIBS Current
18
Input Voltage Range
IVR
Common-Mode
Rejection RatiO
CMRR
Power Supply
Rejection RatiO
PSRR
Large-Signal
Voltage Gain
AvO
Output Voltage
SWing
Vo
CONDITIONS
MIN
(Note21
(Note 31
Vs
~
OP-27G
TYP
MAX
TYP
MAX
50
40
140
55
220
06
03
13
04
18
!lVI'C
TYP
MAX
20
02
MIN
MIN
UNITS
10
50
14
85
20
135
nA
±14
±60
±1a
±95
±25
±150
nA
±105
±118
±105
±11a
±10 5
±11.8
V
110
124
102
121
96
118
dB
±4 5Vto ±18V
16
15
750
1500
±117
±136
NOTES:
2
32
!lVN
700
1300
450
1000
VlmV
±114
±135
±110
±13.3
V
The TeVos performance IS within the specifications unnulled or when
nulled with Rp ~ 8kll to 20kll TCVes IS 100% tested for AlE grades,
sample tested for B/C/F/G grades
Guaranteed by deSign
Input offset voltage measurements are performed by automated test
equipment approximately 05 seconds after appllcallon of power AlE
grades guaranteed fully warmed-up
5-130
1/86, Rev. A
------------1~ OP-27 LOW-NOISE PRECISION OPERATIONAL AM_P_L_IF_I_ER
_ _ _ _ _ _ _ _ _ __
DICE CHARACTERISTICS
1. NULL
2. (-) INPUT
3. (+) INPUT
4. V6. OUTPUT
7. V+
8. NULL
For additional DICE inlormation reler to
1986 Data Book, Section 2.
DIE SIZE 0.054 X 0.108 Inch, 5832 sq. mila
(1.37 X 2.74mm, 3.76 sq. mm)
WAFER TEST LIMITS at Vs = ± 15V, T A = 25 0 C for
OP-27GT devices, unless otherwise noted.
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
(Note 1)
Input Offset Current
los
PARAMETER
Input Bias Current
I.
Input Voltage Range
IVR
Common-Made
Rejection RatiO
CMRR
VCM = IVR
Power Supply
Rejection RatiO
PSRR
Vs =±4Vto±18V
Large-Signal
Voltage Gain
Avo
R L ,,2kO, Vo =±10V
RL"aOOO, Vo=±10V
Output Voltage Swing
Vo
RL" 2kO
RL" 6000
Power Consumption
Pd
Vo=O
OP-27N, OP-27G,
and
OP-27GR
devices;
TA
= 125
0
C for
OP-27NT
and
OP-27NT
LIMIT
OP-27N
LIMIT
OP-27GT
LIMIT
60
35
200
60
100
p.VMAX
50
35
85
50
75
nAMAX
nAMAX
OP-27G OP-27GR
LIMIT
LIMIT
UNITS
±60
±40
±95
±55
±80
±103
±11
±10.3
±11
±11
VMIN
108
114
100
106
100
dBMIN
10
20
p.VIV MAX
1000
800
800
±12.0
±10.0
±11.5
±10.0
VMIN
140
170
mWMAX
10
1000
600
500
600
±11.5
±12.0
±10.0
±110
140
700
VlmV MIN
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ± 15V, TA = +25 0 C, unless otherwise noted.
SYMBOL
CONDITIONS
Average Input Offset
Voltage Dnft
TCVosor
TCVoSn
Nulled or Unnulled
Rp = 8kO to 20kO
Average Input Offset
Current Dnft
TClos
Average Input Bias
Current Dnft
TCI.
Input NOise
Voltage DenSity
en
fo= 10Hz
fo= 30Hz
fo= 1000Hz
Input NOise
Current DenSity
In
fo= 10Hz
fo= 30Hz
fo= 1000Hz
Input NOise Voltage
e np _p
o 1Hz to 10Hz
Slew Rate
SR
R L,,2kO
Gain BandWidth Prod uct
GBW
OP-27N
TYPICAL
OP-27G
TYPICAL
OP-27GR
TYPICAL
UNITS
02
03
04
p.VI'C
80
130
180
pAl'C
100
160
200
pAl'C
35
31
30
35
31
30
3.8
33
32
nVl,jHZ
17
10
04
17
10
04
17
10
0.4
pAl,jHZ
008
008
0.09
p.Vp-p
28
28
28
VII'S
8
8
8
MHz
NOTE:
1 Input offset voltage measurements are performed by automated test
equipment approximately 0.5 seconds after appllcallon of power.
5-131
~
::l
I=l-<
~
~
0>-<
~
f:J.:t
NOTE:
Electrical tests are performed at wafer probe to the limits shown Due to variations In assembly methods and normal yield loss, yield after packaging IS not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing
PARAMETER
ffi
>-<
1/86, Rev. A
C5
------------l~ OP·27 LOW·NOISE PRECISION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
0.1 Hz TO 10Hzp _p NOISE TESTER
FREQUENCY RESPONSE
A COMPARISON OF
OP AMP VOLTAGE
NOISE SPECTRA
VOLTAGE NOISE DENSITY
vs FREQUENCY
100 1""""1-n-mrrr-TTnnnr"T"l-mmr---rTTlm11
l~~~!OO
~
100
-I";
741
TA-2S0C
I¥
6
I.,--+-+H+++l+-H++f++t+
Vs '" ±15V
'55 P-d-f-t++ttIt--H-+ttttft--H-+ttttH
>
~
4
f-->.cl,4
30
i,tZ..:LJ
>-
i<
1
:;:
-25
25
50
75
100
125
0
-
60
Vs
'\
r-....
50
'\
I"'\.
±15V-
-1 0
10
25
~
9>u
"
""
0
--
it
100
lk
10k lOOk
FREQUENCY (Hz)
1M
t-SLEW
"1'-.
10M 100M
20
15
1\
-25
25
50
TEMPERATURE fC)
5-133
75
50
75
z
<1
100
125
TnTT
100
125
iil
PHASE \ "
MARGIN
t"
~
"" 700
160 w
\
lBO
~
200
r-..
1M
100
140
~
-5
80
120.-
1\
II
-10
-50
O;"27A
25
TA = 25"c
Vs ~ ±15V
~Ll
10
b
~
z
:iI
"
-75
--
~
8 J:
7
I'\.
-25
OP-278
GAIN, PHASE SHIFT vs
FREQUENCY
10
l-- GBW
'\
0
~ .......... -
TEMPERATURE (OC)
SLEW RATE, GAIN-BANDWIDTH
PRODUCT, PHASE MARGIN vs
TEMPERATURE
1'\
o
10
,","",
OP·27C
-75 -50
150
I--"M
I"
20
0
OP-278
01--$1
'"w
5
~
30
TEMPERATURE (OC)
I'\.
70
~
a:
a h
OP-27A
13
0,-
1'\
I I
Vs =±15V-
40
1
>-
III
OPEN-LOOP GAIN vs
FREQUENCY
0
50
~
TIME (SEC)
11 0
INPUT OFFSET CURRENT
vs TEMPERATURE
OP-27C
ufe OIL BATH
20
TIME AFTER POWER ON (MINUTES)
\ \ '\
10
0
-
-...
INPUT BIAS CURRENT
vs TEMPERATURE
~
tu
-
TIME (MONTHS)
V~.~'5)-
I I I I I I
I I I I I
w
OP·27 C/G
-4
OP·27C
OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK
;;
-
A.
-2
I
100
Vs - .,6V
/
./'" h.
I
......
75
T1-+2J
f---
-6
....... OP-278
!"
T~VOSI
-60
~
OP 27A
!'.....
-40
- v . . . .....
-4
I
r::o-
...."
......:;:
-2
OP 27A
>~ -2 0
WARM-UP OFFSET
VOLTAGE DRIFT
I-..
.Y
Opi 7A
0
g
LONG-TERM OFFSET
VOLTAGE DRIFT OF SIX
REPRESENTATIVE UNITS
10M
FREQUENCY (Hz)
220
100M
1/86, Rev. A
------------t1fMD
OP-27 LOW-NOISE PRECISION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN-LOOP VOLTAGE GAIN
vs SUPPLY VOLTAGE
28
I
5
o -TA =
.A"
24
Vs
V
/";..-
RL=600n
/
±15V
14
- poslmJE
12
-
16
V
NEGATIVE
SWING
J/
12
IV
~
SWING
10
f/
\
05
00
10
=
16
20
~V
0
18
II ~~Io 2l,ll
RL '" 2kS1
2SOC
MAXIMUM OUTPUT VOLTAGE
vs LOAD RESISTANCE
MAXIMUM OUTPUT SWING
vs FREQUENCY
20
30
40
o
50
10k
1k
TOTAL SUPPLY VOLTAGE (VOLTS)
SMALL-SIGNAL OVERSHOOT
vs CAPACITIVE LOAD
2 mV
It II
-2
10M
lOOk
1M
FREQUENCY (Hz)
100
1k
10k
LOAD RESISTANCE (n)
SMALL-SIGNAL TRANSIENT
RESPONSE
100
TA=2SoC
Vs '" ±15V
'----
t---
LARGE-SIGNAL TRANSIENT
RESPONSE
2
1(; 00 S
I
--
I,gS
+5V
50mV
80
I
-'"
60
/
40
/
20
o
Vs eo ±15V
VIN=100mV
AV"'+l
V
o
OV
OV
500
1000
I
I
1500
2000
-50mV
11111
,;;::
~
=
-5V
AVCl = +1, C L = lSpF
I
I
;;==
I
I
VS'" ±15V
AVCL = +1
Vs = ±15V
TA '" 25°C
TA "'25°C
I
=
-
2500
CAPACITIVE LOAD (pF)
SHORT-CIRCUIT CURRENT
vs TIME
60
COMMON-MODE INPUT RANGE
vs SUPPLY VOLTAGE
CMRR vs FREQUENCY
16r-----~-----r----_r~~~
140
IIIIIIIIH
50
40
30
"-
~
TA = +2SOC
TA'" 25 C
Vs = ±1SV
120
Vs '" ±15V
VCM '" ±10V
~sc~1
-
12 I-----+_--
:\
100
Iscf+)
10
o
I\.
80
0
1
TIME FROM OUTPUT SHORTED TO GROUND (MINUTES)
60
100
1k
I
-12~----t-----1-~~~~---1
-16~
10k
lOOk
1M
o
____
~
±5
____
~
±lO
____
~
____- J
±1S
±20
SUPPLY VOLTAGE (VOLTS)
FREQUENCY (Hz)
5-134
1/86, Rev. A
-----------I~ OP-27 LOW-NOISE PRECISION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE NOISE TEST CIRCUIT (0.1 Hz-TO-10Hz)
LOW-FREQUENCY NOISE
O.lIJF
120
80
40
"'r'
""1
-::-
NOTE
-'0
SCOPE
Xl
RIN = lMn
4.3kO
-80
-120
-::- 110kO
o 1Hz TO 10Hz PEAK-TO-PEAK NOISE
ALL CAPACITOR VALUES ARE FOR
NON POLARIZED CAPACITORS ONLY.
NOTE:
Observation time limited to 10 seconds.
OPEN-LOOP VOLTAGE GAIN VB
LOAD RESISTANCE
24
'2
~ 20
f-f--
~Alel,~!bl
Vs
=
~ 140
±15V
1!
z 18
<1
~
PSRR VB FREQUENCY
160
if
16
o
~
Y
'"~ 100
~ '4
~
>12
'"~
~ 8
o
is
g
Z
~
o
~
10
08
06
0'
100
:>
~
ffi
II
~
lk
10k
100k
1=
TA
12 0 ........
25O~-
~
O-paSITI\~
NEGATIVE
~UPPLY
SUPPl Y
60
~
'0
20
10
LOAD RESISTANCE (il)
100
lk
10k
~
lOOk
~
1M
10M 100M
FREQUENCY (Hz)
(see Offset Nulling Circuit). Other potentiometer values from
1kO to 1 MO can be used with a slight degradation (0.1 to
0.2p.V/oC) of TCVos. Trimming to a value other than zero
creates a drift of approximately (Vos/300) p.V/ oC. For example, the change in TCVos will be 0.33p.V;o C if Vos is adjusted
to 100p.V. The offset-voltage adjustment range with a 10kO
potentiometer is ±4mV. If smaller adjustment range is required, the nulling sensitivity can be reduced by using a
smaller pot in conjuction with fixed resistors. For example,
the network below will have a ±280p.V adjustment range.
APPLICATIONS INFORMATION
OP-27 Series units may be inserted directly into 725, OP-06,
OP-07 and OP-05 sockets with or without removal of external
compensation or nulling components. Additionally, the OP27 may be fitted to unnulled 741-type sockets; however, if
conventional 741 nulling circuitry is in use, it should be modified or removed to ensure correct OP-27 operation. OP-27
offset voltage may be nulled to zero (or other desired setting)
using a potentiometer (see Offset Nulling Circuit).
The OP-27 provides stable operation with load capacitances
of up to 2000pF and ± 10V swings; larger capacitances should
be decoupled with a 500 resistor inside the feedback loop.
The OP-27 is unity-gain stable.
47k!1
Thermoelectric voltages generated by dissimilar metals at
the input terminal contacts can degrade the drift performance. Best operation will be obtained when both input
contacts are maintained at the same temperature.
lknpOT
47kn
v+
OFFSET VOLTAGE ADJUSTMENT
The input offset voltage of the OP-27 is trimmed at wafer
level. However, if further adjustment of Vos is necessary, a
10kO trim potentiometer may be used. TCVos is not degraded
5-135
NOISE MEASUREMENTS
To measu re the 80nV peak-to-peak noise specification of the
OP-27 in the 0.1 Hz to 10Hz range, the following precautions
must be observed:
(1) The device has to be warmed-up for at least five minutes.
As shown in the warm-up drift curve, the offset voltage
1/86, Rev. A
----------IIEM!) OP-27 LOW-NOISE PRECISION OPERATIONAL AMPLIFIER
typically changes 4/LV dueto increasing chip temperature
after power-up. In the 10-second measurement interval,
these temperature-induced effects can exceed tens-ofnanovolts.
bias-current cancellation circuit. The OP-27A/E has IB and
los of only ±40nA and 3SnA respectively at 25° C. This is
particularly important when the input has a high sourceresistance. In addition, many audio amplifier designers
prefer to use direct coupling. The high IB' Vos, TeVos of
previous designs have made direct coupling difficult, if not
impossible, to use.
(2) For similar reasons, the device has to be well-shielded
from air currents. Shielding minimizes thermocouple
effects.
Voltage noise is inversely proportional to the square-root of
bias current, but current noise is proportional to the squareroot of bias current. The OP-27's noise advantage disappears
when high source-resistors are used. Figures 1, 2, and 3
compare OP-27 observed total noise with the noise performance of other devices in different circuit applications.
(3) Sudden motion in the vicinity of the device can also "feedthrough" to increase the observed noise.
(4) The test time to measure 0.1 Hz-to-10Hz noise should not
exceed 10 seconds. As shown in the noise-testerfrequencyresponse curve, the 0.1 Hz corner is defined by only one
zero. The test time of 10 seconds acts as an additional
zero to eliminate noise contributions from the frequency
band below 0.1 Hz.
Total noise = [(Voltage nOise)2
(resistor noise)2]112
+ (current
noise X RS)2
+
(5) A noise-voltage-density test is recommended when
measuring noise on a large number of units. A 10Hz
noise-voltage-density measurement will correlate well
with a 0.1 Hz-to-10Hz peak-to-peak noise reading, since
both results are determined by the white noise and the
location of the 1/f corner frequency.
Figure 1 shows noise-versus-source-resistance at 1000Hz.
The same plot applies to wideband noise. To use th is plot, just
multiply the vertical scale by the square-root of the
bandwidth.
UNITY-GAIN BUFFER APPLICATIONS
When Rt:51000and the input is driven with a fast, large signal
pulse (> 1V), the output waveform will look as shown in the
pulsed operation diagram below.
NOISE vs SOURCE RESISTANCE
(INCLUDING RESISTOR NOISE)
AT 1000Hz.
100
During the fast feedthrough-like portion of the output, the
input protection diodes effectively short the output to the
input and a current, limited only by the output short-circuit
protection, will be drawn by the signal generator. With
Rt ;:: 5000, the output is capable of handling the current
requirements (IL:5 20mA at 10V); the amplifier will stay in its
active mode and a smooth transition will occur.
50
~;jtI
OP-08/10B
~
mp-oJ
2
1 Rs UNMATCHED
5534
e 9 RS=RS1=10k,RS2=O
2 RS MATCHED
eg RS=10k.RS1~RS2"5k
When Rt > 2kO, a pole will be created with Rt and the
amplifier's input capacitance (8pF) that creates additional
phase shift and reduces phase margin. A small capacitor
(20 to SOpF) in parallel with Rt will eliminate this problem.
OP-27/37
W-~SISTOR
NOISE ONLY
1
50 100
500
1k
itt>
RS2
5k
10k
50k
RS - SOURCE RESISTANCE (m
PULSED OPERATION
Figure 1
At Rs < 1kO, the OP-27's low voltage noise is maintained.
With Rs> 1kO, total noise increases, but is dominated by the
resistor noise rather than current or voltage noise. It is only
beyond Rsof 20kO that current noise starts to dominate. The
argument can be made that current noise is not importanttor
applications with low-to-moderate source resistances. The
crossover between the OP-27 and OP-07 and OP-08 noise
occurs in the 1S-to-40kO region.
Figure 2 shows the 0.1 Hz-to-10Hz peak-to-peak noise. Here
the picture is less favorable; resistor noise is negligible, current noise becomes important because it is inversely proportional to the square-root of frequency. The crossover with the
OP-07 occurs in the 3-to-SkO range depending on whether
balanced or unbalanced source resistors are used (at3kO the
IB' los error also can be three times the Vos spec.).
COMMENTS ON NOISE
The OP-27 is a very low-noise monolithic op amp. The outstanding input voltage noise characteristics of the OP-27 are
achieved mainly by operating the input stage at a high quiescent current. The input bias and offset currents, which would
normally increase, are held to reasonable values by the input-
5-136
1/86, Rev. A
----------I~ OP-27 LOW-NOISE PRECISION OPERATIONAL AMPLIFIER
10Hz NOISE vs
SOURCE RESISTANCE
(INCLUDES RESISTOR NOISE).
PEAK-TO-PEAK NOISE (0.1 to
10Hz) VB SOURCE RESISTANCE
(INCLUDES RESISTOR NOISE).
1k
100
OP-08/108
553..
500
50
h2
III
OP-07
II:
~
IIII
100
V
~l-07
OP-27/37
, RS UNMATCHED
1 RSUNMATCHED
e!l RS"RS1=lOk,RS2-o
2 RSMATCHED
e9
~~::Ig~~~
100
~.
r~r-2TJ,
5k
10k
1
50
50k
RS - SOURCE RESISTANCE (n)
Figure 3
Therefore, for low-frequency applications, the OP-07 is better than the OP-27/37 when Rs> 3ko.. The only exception is
when gain error is important. Figure 3 illustrates the 10Hz
noise. As expected, the results are between the previous two
figures.
<5000
Typically used in low-frequency
applications.
Magnetic
tapehead
<15000
Low Ie very Important to reduce
self·magnetization problems when
direct coupling is used. OP-27 Ie
can be neglected.
Magnetic
phonograph
cartridges
<15000
Similar need for low Ie in direct
coupled applications. OP-27 will not
introduce any self·magnetization
problem.
Linear variable
differential
transformer
<15000
Used in rugged servo-feedback
applications. Bandwidth of interest is
400Hz to 5kHz.
500
100
1k
Sk
10k
50k
AS - SOURCE RESISTANCE (n)
Figure 4 is an example of a phono pre-amplifier circuit using
the OP-27 for A 1; R1-R2-C1-C2 form a very accurate RIAA
network with standard component values. The popular method
to accomplish RIAA phono equalization is to employ
frequency-dependent feedback around a high-quality gain
block. Properly chosen, an RC network can provide the three
necessary time constants of 3180, 318, and 75/,s.1
COMMENTS
Strain gauge
As2
AUDIO APPLICATIONS
Table 1
SOURCE
IMPEDANCE
~.
rOnpl~~~
The following applications information has been abstracted
from a PMI article in the 12/20/80 issue of Electronic DeSign
magazine and updated.
For reference, typical source resistances of some signal
sources are listed in Table 1.
DEVICE
e 9 RS~10k.RS1~AS2~5k
HRESISTOR
""
500 1k
RsmRS1~lOk,RS2"O
2 RSMATCHED
a 9 RS"',Ok,RSl"'RS2 a Sk
10
50
t/
V
553'
50
Figure 2
~
op-oa/1os
V
For initial equalization accuracy ana stability, precision
metal-film resistors and film capacitors of polystyrene or
polypropylene are recommended since they have low voltage
coefficients, dissipation factors, and dielectric absorption. 4
(High-K ceramic capacitors should be avoided here, though
low-K ceramics-such as NPO types, which have excellent
dissi pation factors, and somewhat lower dielectric absorptioncan be considered for small values.)
C4 (2)
(+1220~(~1
R5
P---9~
-=-
IF ROllOFF
OUT
IN
C3
OPEN-LOOP GAIN
OUTPUT
FREQUENCY
AT:
OP-07
OP-27
OP-37
3Hz
100dB
124dB
125dB
10Hz
100dB
120dB
125dB
30Hz
90dB
110dB
124dB
R1
97 Sk.n
R3
100.11
G = 1kHz GAIN
For further information regarding noise calculations, see
"Minimization of Noise in Op-Amp Applications", Application
Note AN-15.
=0101 (1+*)
Figure 4
5-137
= 98 677 (39 9 dB) AS SHOWN
1/86, Rev. A
----------l1fMD
OP-27 LOW-NOISE PRECISION OPERATIONAL AMPLIFIER
The OP-27 brings a 3.2nV/y'HZ voltage noise and 0.45
pAly'HZ current noise to this circuit. To minimize noise
from other sources, Rs is set to a value of 1000, which
generates a voltage noise of 1.3nVly'HZ. The noise increases the 3.2nVly'HZ of the amplifier by only 0.7dB. With
a 1kO source, the circuit noise measures 63dB below a 1mV
reference level, unweighted, in a 20kHz noise bandwidth.
The network values of the configuration yield a 50dB gain at
1kHz, and the dc gain is greater than 70dB. Thus, the worstcase output offset is just over 500mV. A single 0.471'F output
capacitor can block this level without affecting the dynamic
range.
The tape head can be coupled directly to the amplifier input,
since the worst-case bias current of BOnA with a 400mH, 100
I'in. head (such as the PRB2H7K) will not be troublesome.
Gain (G) of the circuit at 1kHz can be calculated by the
expression:
One potential tape-head problem is presented by amplifier
bias-current transients which can magnetize a head. The
OP-27 and OP-37 are free of bias-current transients upon
power up or power down. However, it is always advantageous
to control the speed of power supply rise and fall, to eliminate transients.
G = 0.101 (1+ : : )
For the values shown, the gain is just under 100 (or 40dB).
Lower gains can be accommodated by increasing Rs, but
gains higher than 40dB will show more equalization errors
because of the BMHz gain-bandwidth of the OP-27.
In addition, the dc resistance of the head should be carefully
controlled, and preferably below 1kO. For this configuration, the bias-current-induced offset voltage can be greater
than the 100l'V maximum offset if the head resistance is not
sufficiently controlled.
This circuit is capable of very low distortion over its entire
range, generally below 0.01% at levels up to 7V rms. At 3V
output levels, it will produce less than 0.03% total harmonic
distortion at frequencies up to 20kHz.
Capacitor Cs and resistor R4 form a simple -6dB-per-octave
rumble filter, with a corner at 22Hz. As an option, the switchselected shunt capacitor C4, a non polarized electrolytic,
bypasses the low-frequency roll off. Placing the rumble filter's high-pass action after the preamp has the desirable
result of discriminating against the RIAA-amplified lowfrequency noise components and pickup-produced lowfrequency disturbances.
A simple, but effective, fixed-gain transformerless microphone preamp (Fig. 6) amplifies differential signals from lowimpedance microphones by 50dB, and has an input impedance of 2kO. Because of the high working gain of the circuit,
an OP-37 helps to preserve bandwidth, which will be 110kHz.
As the OP-37 is a decompensated device (minimum stable
gain of 5), a dummy resistor, Rp, may be necessary, if the
microphone is to be unplugged. Otherwise the 100% feedback from the open input may cause the amplifier to oscillate.
A preamplifier for NAB tape playback is similar to an RIAA
phono preamp, though more gain is typically demanded,
along with equalization requiring a heavy low-frequency
boost. The circuit in Fig. 4 can be readily modified for tape
use, as shown by Fig. 5.
Common-mode input-noise rejection will depend upon the
match of the bridge-resistor ratios. Either close-tolerance
(0.1%) types should be used, or R4Shouid be trimmed for best
CMRR. All resistors should be metal-film types for best stability and low noise.
Noise performance of this circuit is limited more by the input
resistors R1 and R2 than by the op amp, as R1 and R2 each
generate a 4nVly'HZ noise, while the op amp generates a
3.2nVly'HZ noise. The rms sum of these predominant noise
sources will be about 6nVly'HZ, equivalent to 0.91'V in a
20kHz noise bandwidth, or nearly 61 dB below a 1mV input
signal. Measurements confirm this predicted performance.
a 47J.1F
TAPE
HEAD
R,
c,
R1
313kn
R2
O.OlMF
f
5kn
loon
R1
T1 '" 31BOMS
lkSl
R3
316kn
T2 '" 50ps
Cl
R6
5.u F
loon
Figure 5
LOW IMPEDANCE
MICROPHONE INPUT ~
While the tape-equalization requirement has a flat highfrequency gain above 3kHz (T2 = 50l's), the amplifier need
not be stabilized for unity gain. The decompensated OP-37
provides a greater bandwidth and slew rate. For many applications, the idealized time constants shown may require
trimming of R1 and R2 to optimize frequency response for
non ideal tape-head performance and other factors. s
5-138
(Z= 50 TO 200n)
~,,~
Rl R2
~
R7
1
OUTPUT
10kn
R2
R4
1k"
316M2
Figure 6
1/86, Rev_ A
------------t1£HD
OP-27 LOW-NOISE PRECISION OPERATIONAL AMPLIFIER
For applications demanding appreciably lower noise, a highquality microphone-transformer-coupled preamp (Fig. 7)
incorporates the internally-compensated OP-27. Tl is a
JE-11SK-E 1S00/1SkO transformer which provides an optimum source resistance for the OP-27 device. The circuit has
an overall gain of 40dB, the product of the transformer's
voltage setup and the op amp's voltage gain.
eliminated in such cases, but is desirable for higher gains to
eliminate switching transients.
Capacitor C2 and resistor R2 form a 21's time constant in this
circuit, as recommended for optimum transient response by
the transformer manufacturer. With C2 in use, AI must have
unity-gain stability. For situations where the 21's time constant is not necessary, C2 can be deleted, allowing the faster
OP-37 to be employed.
Some comment on noise is appropriate to understand the
capability of this circuit. A 1500 resistor and Rl and R2 gain
resistors connected to a noiseless amplifier will generate 220
nV of noise in a 20kHz bandwidth, or 73dB below a 1mV
reference level. Any practical amplifier can only approach
this noise level; it can never exceed it. With the OP-27 and Tl
specified, the additional noise degradation will be close to
3.6dB (or-69.S referenced to 1mV).
C2
1800pF
R1
R2
121n
11oof!
OUTPUT
References
150[2
SOURCE
*T1 '" JENSEN JE-l 1SK-E
1.
Llpshltz. S.P, "On RIAA Equalization Networks," JAES, Vol 27, June 1979,
p.458-481.
2
Jung, W G , IC Op Amp Cookbook, 2nd Ed., H.W. Sams and Company,
1980
JENSEN TRANSFORMERS
10735 Burbank Blvd
N Hollywood, CA 91601
Jung, W G , Audio IC Op Amp ApplicatIOns, 2nd Ed, H W. Sams and
Company, 1978
Figure 7
4
Gain may be trimmed to other levels, if desired, by adjusting
R2 or R1 . Because of the low offset voltage of the OP-27, the
output offset of this circuit will be very low, 1.7mVor less, for a
40dB gain. The typical output blocking capacitor can be
BURN-IN CIRCUIT
Jung, W G , and Marsh, R.M , "Picking Capacitors," Audio, February &
March, 1980.
5. Otala, M , "Feedback-Generated Phase Nonlinearity in Audio Amplifiers,"
London AES Convention, March 1980, preprint 1976.
6. Stout, D.F, and Kaufman, Moo Handbook of Operational Amplifier Circuit
Design, New York, McGraw Hill, 1976
OFFSET NULLING CIRCUIT
7
6
> - - ' - - - 0 OUTPUT
5-139
1/86, Rev. A
II
II
OP-32
HIGH-SPEED (AveL 2: 10) PROGRAMMABLE MICROPOWER
OPERATIONAL AMPLIFIER (SINGLE OR DUAL SUPPLY)
['recision Monolithics Inc
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Programmable Supply Current ............ 1j.1A to 2mA
Single Supply Operation ................ +3V to +30V
Dual Supply Operation ................ ±1.5V to ±15V
Low Input Offset Voltage ...................... 100j.lV
Low Input Offset Voltage Drift .............. 0.5j.1V1°C
High Com/TIon-Mode Input Range ... V- to V+ (-1.5V)
High CMRA and PSRR ........................ 115dB
High Open-Loop Gain . . . . . . . . . . . . . . . . . . . .. 2000VlmV
±30V Input Overvoltage Protection
Fast ............................ 1V1j.1s@ ISY= 300j.lA
LM4250 Pinout
Compensated for Minimum Gain of 10
ORDERING INFORMATIONt
PACKAGE
EPOXY
HERMETIC
DIP
DIP
8-PIN
8-PIN
TA=25'C
YosMAX
(IlY)
300
300
OP32EP
500
500
1000
OP32FP
OP32GP
OPERATING
TEMPERATURE
RANGE
OP32AZ'
OP32EZ
OP32BZ'
OP32FZ
OP32GZ
MIL
INO
MIL
INO
INO
low, and both are stable with changes in temperature, supply
voltage, and set current. High CMRR and PSRR ensure
precision performance when the OP-32 is used with an
unregulated battery or vehicular electrical system.
The wide input voltage range, including the negative supply
or ground, allows use in single-battery applications. The
OP-32 is characterized over a wide supply range of ± 1.5V to
± 15V. This guarantees predictable performance with any
commonly available supply.
The ability to operate at relatively high speed with low power
consumption makes this amplifier ideal for remote applications where power is limited. The programmability allows
each amplifier in a system to be set for the minimum power
consumption necessary for each specific application.
Programmability also makes it possible to adjust the bandwidth and phase shift.
The OP-32 pinout is identical to the LM4250 and many other
micropower operational amplifiers. This allows easy upgrading of system performance.
PIN CONNECTIONS
8-PIN EPOXY DIP
(P-Sufflx)
* For devices processed in total compliance to M1L-STD-883, add /883 after
part number. Consult factory for 883 data sheet.
8-PIN HERMETIC DIP
(Z-Suffix)
t All
commercial and industnal temperature range parts are available with
burn-In. For ordering information see 1986 Data Book, Section 2
GENERAL DESCRIPTION
NOTE: DO ~ SHORT PIN 8 TO v- OR GROUND
seE APPLICATIONS INFORMATION
The OP-32 is a high-speed, high-gain programmable operational amplifier. Both offset voltage and offset current are
SIMPLIFIED SCHEMATIC
r-----~------~------~--------~--~----~~~------~--~~--ov+
+---t-~_f::c_---l'::____,t
Vs = ±1.5V
10
100
i
0
/.
fI"
~
10
~
's= ±1
0
r-f-rn
I- liTII\)
NEGATIVE-
1
10
~-55"
I
If
100
1000
"/
1/
01
100
10
SUPPLY CURRENT ("AI
OPEN-LOOP GAIN
vs SUPPLY CURRENT
150
100
Vs:; ±15V
ISY
TA = 2SOC
450J.lA
fo""'"
~
-
~
10
I--
+15
~
I~
,..-
+10
I,...-
'SY - 150j./A
+5
-5
TA"'25°C
145
--
-10
140
135
Vs· ±15V
130
v! J5l
120
=
115
110
100l1li1&11
105
'0 ,L ....J.....u.ll!.u.,0~J.....l..J..!.Ull,0':..0....J....J....JUJ.J.lJI,000
-15
100
10
1000
100
SUPPLY CURRENT (j.lA)
SUPPLY CURRENT (pA)
1/86, Rev. A
5-145
..
~---
I
I
125
COMMON-MODE VOLTAGE (VOLTS)
-----~----------
100
SUPPLY CURRENT (pAl
MAXIMUM OUTPUT CURRENT
VB SUPPLY CURRENT AT
Vs= ±15V, +5V AND ±1.5V
BIAS CURRENT vs
COMMON-MODE VOLTAGE
1
100
1000
SUPPLY CURRENT (j.lA)
--
---~-~
----=--~---
-
--- ----------------
.~-
-- --
-----~--~----
--::--
---_.-
--------1~ OP·32 HIGH·SPEED PROGRAMMABLE MICROPOWER OPERATIONAL AMPLIFIER
TYPICAL DC OPEN-LOOP INPUT-OUTPUT CHARACTERISTICS
Isy= 1mA, RL = 100kO
Isy = 1mA, RL = 10kO
20
15
10
'>
-"
~
;:
~
-5
-10
-15
-25 -20 -15 -10
-5
0
5
10
15
20
25
-20 -15 -10
OUTPUT (VOL lS)
-5
0
5
10
15
20
25
-25 -20 -15 -10
OUTPUT (VOLTS)
-5
0
5
10
15
20
25
OUTPUT (VOL IS)
ISY = 100ILA, RL = 2kO
20
20
20
15
15
15
10
10
'>
~
-"
~
;:
~
10
'>
-"
~
~
;:
-5
~
-10
;:
-5
~
-10
-15
-15
-20
-20
-25 -20 -15 -10 -5
5
10
15
-15
-20
-25 -20 -15 -10 -5
20 25
-5
-10
5
10
15
20
25
-25 -20 -15 -10 -5
OUTPUT (VOLTS)
OUTPUT (VOLTS)
5
10
15
20 25
OUTPUT (VOLTS)
TEST CIRCUIT
20
Vy
15
10
~
~
;:
~
-5
-10
-15
":"
-20
-25 -20 -15 -10
-5
5
10
OUTPUT (VOL TS)
15
20
25
-25 -20 -15 -10 -5
o
5
10
15
20
25
R2»Rl, R3
R2
Vy '" -
Ra
-=
1
AVOL Your
OUTPUT (VOL TS)
5·146
1/86, Rev. A
-------I~ OP-32 HIGH-SPEED PROGRAMMABLE MICROPOWER OPERATIONAL AMPLIFIER
TYPICAL AC PERFORMANCE CHARACTERISTICS
GAIN-BANDWIDTH PRODUCT
vs SUPPLY CURRENT
POWER SUPPLY REJECTION
vs SUPPLY CURRENT
SLEW RATE vs
SUPPLY CURRENT
10M
130
Vs
T A =2SoC
OP32E AT Vs = 3V TO 30V
+15V
128
TA - 2S C C
I
126
V
1M
I 1111111
OP32F AT Vs '" 3V TO 30V
124
QP32E AT Vs =- ±1 5V TO ±15V
122
I
120
I 1111111
QP32F AT Vs = ±1 5V TO ±15V
~
lOOk
118
I
100
140
150
COMMON-MODE REJECTION
vs SUPPLY CURRENT
120
v~ ±15~
140
116
'SY = 150l1A
114
130
"
80
60
....
100
20
90
lOOk
10k
1M
-75
-50
-25
FREQUENCY (Hz)
10
II
TA == 25°C
f-
'SY = lmA
oulp1l
01
.......
001
35
10
30
03
25
01
20
003
1
001
1
0003
DISTORTION..",
0003
i-"
0001
o
1k
10k
FREQUENCY (Hz)
75
"
100
104
T A =2S0C
Vs = ±15V
102
100
10
125
100k
VOLTAGE NOISE
vs FREQUENCY
25
-
00003
100
1000
1000
30
'SY = lOOfJA
.......
100
SUPPLY CURRENT lilA)
35
T~O;5~~'11
DISTORTION
20
1\i\'"
l
1k
0
z
10
"~
101b
10k
100
~,
o
100k
0
;
5~A I.
','!v ;5"~ I
0
w
'SY = 150.uA
0
>
SWING
FREQUENCY (Hz)
5-147
15
OUTPUT
I,~y
~
~
0001
1,..001-'
00003
100
50
r- Jp32~
106
TOTAL HARMONIC
DISTORTION vs FREQUENCY
SWING
003
25
108
TEMPERATURE (OC)
TOTAL HARMONIC
DISTORTION vs FREQUENCY
03
110
........
~ r......
40
1k
I
r-lp32~
112
'SY - 150flA
120
110
100
QP32E
118
=
TA =25°C
....
SUPPLY CURRENT I/lA)
COMMON-MODE REJECTION
vs TEMPERATURE
:~ll~l±l~~1I1
120
100
10
SUPPLY CURRENT (MAl
COMMON-MODE REJECTION
vs FREQUENCY
10
I I 1111111
1000
SUPPLY CURRENT (IlA)
o
L
I 1111111
QP32G AT Vs = ±1 5V TO ±15V
110
10
1
100
II IIJIIJI
114
112
IL
10k
116
ISY = 1 SmA
10
01
W In
10
100
FREQUENCY (Hz)
1/86, Rev. A
-------I!EMD
OP-32 HIGH-SPEED PROGRAMMABLE MICROPOWER OPERATIONAL AMPLIFIER
TYPICAL AC PERFORMANCE CHARACTERISTICS
SMALL-SIGNAL TRANSIENT RESPONSE vs SUPPLY CURRENT
Isy = 1.51'A
ov
ov
ov
ov
ov
ov
ov
ov
ov
ov
ISy=1.5mA
TEST CIRCUIT
+1SV
10kH
ov
>----+---~OUTPUT
RSET
100kn
ov
-15V
5-148
1/86, Rev. A
-------t~ OP-32 HIGH-SPEED PROGRAMMABLE MICROPOWER OPERATIONAL AMPLIFIER
TYPICAL AC PERFORMANCE CHARACTERISTICS
LARGE-SIGNAL TRANSIENT RESPONSE vs SUPPLY CURRENT
ISY= 1.5",A
OV
ov
OV
ov
ov
ov
RFt
RFt = 11kn, R F2 " lQOkn, Al = lMn
RFl '" 110kn, RF2 '" lMn, RL "OPEN
=
11kf':!, RF2 = 100kn, RL
=
lMn
~
>J..l
........
>J-.
~
~
ISY= 150",A
ISY= 750",A
ISY= 450",A
~
~
OV
OV
0
........
~
OV
>J..l
~
OV
OV
RFt = , lkn, RF2 = 10kn, RL = 100kn
0
OV
RFt = 1 lkn, RF2 = 10kn, RL
Isy=1.5mA
= 100kn
RFt = , lkn, RF2 = 10kn, RL = lOOk!,,:!
TEST CIRCUIT
+15V
OV
> - -.......~---o OUTPUT
ov
5-149
1/86, Rev. A
-------l~ OP-32 HIGH-SPEED PROGRAMMABLE MICROPOWER OPERATIONAL AMPLIFIER
APPLICATIONS INFORMATION
CURRENT SETTING CIRCUITS
SETTING SUPPLY CURRENT
The op amp power supply current is determined by the
current flowing out of pin 8. Pin 8 isat the V+ voltage less two
diode drops. which is approximately V+ minus 1.1 V. Do not
connect pin 8 to ground or V- without a set resistor in series
or excessive supply current will be drawn which may damage
the OP-32.
V.--------~~---------------
The set resistor value is selected to make the power supply
current optimum for the specific application. Adjusting the
OP-32 power supply current determines the slew-rate.
bandwidth. and the output current limits (see Performance
Characteristics). The supply current is nominally 15 times the
set current and the set resistor value is calculated from:
Rs =
(VSUPPLY - 1.1 V)
ISET
2N411BA
Rl
V-------~--~~------~----_
(a)
• where Isy"" 151sET
(See graph below)
v+--------~----------~------
Note that the set resistor can go to either negative supply or
to ground. If the set resistor goes to negative supply. then
VSUPPLY= (V+) - (V-). For a single-supply circuit. VSUPPLY is
simply (V+). If the supply voltage varies widely. set current
can be stabilized with circuits (a). (b). or (c).
10Mn
The relationship between supply voltage. supply current and
set current can be approximated by:
2,
.!g ""10+ (V+)-(V-) (TA=250C)
2N930A
6
ISET
R1
The ratio -IISY increases with temperature by approximately
SET
0.05%/oc.
V- - -
------4>___1----____......._ _ _ _ - -
(b)
SUPPLY CURRENT vs TEMPERATURE
1
_I
7
61-- Vs = ±15V -
5
170
.I
r- l,uA
160
l.---r-r
t:.-I-~A
150
4
140
3
130
2
120
1!--Vr '5V 0
9
~
~
~
k
r- 10,uA
v+-------~----------~-----R2
:2''"
"
-;
1
>-
1)
110
*
~
R1
il:
T
~
100
V--------4--~~
~
m
LED
iil
______~-----
90
~
rn
(e)
TEMPERATURE (OC)
INPUT BIAS CURRENT
Input bias current varies directly with set current. The set
current required for a given supply current ranges from
Isy!10.5 at ± 1.5V supply voltage to I sy!15 at ± 15V. Therefore.
I swill be highest at the minimum supply voltage condition of
±1.5V (or 3V) for any given supply current.
5-150
1/86, Rev. A
--------I~ OP-32 HIGH-SPEED PROGRAMMABLE MICRO POWER OPERATIONAL AMPLIFIER
BATTERY-POWERED, GAIN-OF-100 AMPLIFIER
OFFSET NULLING CIRCUIT
R,
v.
5.06kn
R2
500k.l1
.9V
>----0 OUTPUT
INPUT
Vo
Vo = 100VIN
v-
Figure 1
Using an OP-32B/F, we can expect an IB + los/2 of less than
S.SnA when operating at ISY of 1S",A, so the input offset
caused by IBR1 will be negligible (S.SnA x S.OSkO - 43",V).
OFFSET VOLTAGE ADJUSTMENT
The offset voltage can be trimmed to zero using a 100kO
potentiometer (see offset nulling circuit). Adjusting the pot
wiper towards pin S causes the output to go positive.
Adjustment range is approximately ±SmVat Vs= ±1SV. The
Vos adjust range is proportional to supply voltage. Resolution of the nulling can be increased by using a smaller pot in
conjunction with fixed resistors.
If power supply voltages vary widely and the set current is
established by a resistor, the op amp supply currents will vary
in proportion to the supply voltage changes. Vas will remain
almost constant with supply current changes if the null pins
(1 and S) are not used. If a Vos adjust pot is used, current
variations may flow through the offset pot causing an
apparent Vos change. If a Vas adjust pot is used in combination with widely-varying supply voltages, a set-current
stabilizer circuit as shown in (a), (b), or (c) is recommended.
The set resistor Rs needed for a supply current of 1S",A is
calculated from:
Rs =
AVCL= 1 + R,
100 = 1 + SOOkO
R1
:. R1 = S.OSkO
1SV-1.1V
1",A
Offset voltage adjustment is optional. An OP-32B/F has
maximum input offset voltage of SOO",V which would cause
an output offset voltage of SOmV. Drift over temperature is
very low, typically less than 1.0",Vlo C, and is guaranteed to be
less than 2.0",Vlo C. PSRR is also low, only S",VIV, so battery
voltage change_has negligible effect on offset.
Most micropower programmable op amps lose open-loop
gain and CMRR at low supply currents. The OP-32 design
overcomes these limitations so accuracy is maintained at
supply currents of only a few microamps. The OP-32B/F
used in this example has a minimum open-loop gain of over
117dB. Gain error due to finite open-loop gain will be less
than 10017S0,000, which is only 133 PPM. CMRR will typically
be 110dB, an error of 3PPM. Gain accuracy of the circuit is
almost entirely dependent on the accuracy of the R1/R2 ratio;
the op amp contributes less than 0.01S% gain error.
BATTERY-POWERED, GAIN-OF-100 AMPLIFIER
The simple non inverting amplifier circuit shown in Figure 1
provides an accurate gain-of-100 while operating from a pair
of 9V batteries. The circuit requires only 1S",A of supply
current. Slew-rate is approximately O.OSVI",sec and output
swing is ±SV.
R2
VSUPPLy-1.1V
Isy/1S
:. Rs = 1S.9MO
APPLICATIONS EXAMPLE
A value of SOOkO was chosen for R2' For a gain of 100, R1 is
calculated as:
-9V
Considering all error sources, this simple x 100 batterypowered circuit using an OP-32B/F is capable of achieving
excellent accuracy. Without external adjustments of any
kind, output offset will be less than S4mV and gain accuracy
will be better than ±0.01S% (exclusive of R2/R1 error). Gain
linearity, slew-rate symmetry, and stability over temperature
are all excellent with the OP-32, making circuit performance
very predictable.
5-151
1/86, Rev. A
OP-37
LOW-NOISE PRECISION HIGH-SPEED
OPERATIONAL AMPLIFIER (AVCL 2: 5)
Precision Monolithics Inc.
FEATURES
• Low Noise .. . . . . . . . . . . . . . . .. 80nV pop (0.1 Hz to 10Hz)
.. ... ....... ............ 3nV/y'HZ at 1kHz
• Low Drift .................................. 0.2/JoV;o C
• High Speed ......................... 17V1/Jos Slew Rate
................... 63MHz Gain Bandwidth
• Low Input Offset Voltage ....................... 10/JoV
• Excellent CMRR ... 126dB (Common-Voltage of ± 11V)
• High Open-Loop Gain .. . . . . . . . . . . . . . . . . . .. 1,8 Million
• Replaces 725, OP-05, OP-06, OP-07, AD510, AD517,
SE5534In Gains >5
PACKAGE
25
25
60
60
100
100
OP37AJ'
OP37EJ
OP37BJ'
OP37FJ
OP37CJ'
OP37GJ
OP37AZ'
OP37EZ
OP37BZ'
OP37FZ
OP37CZ'
OP37GZ
The low input bias current of± 10nA and offset current of7nAare
achieved by using a bias-current-cancellation circuit. Over
the military temperature range this typically holds I B and los
to ±20nA and 15nA respectively.
The output stage has good load driving capability. A guaranteed swing of ± 10V into 600n and low output distortion make
the OP-37 an excellent choice for professional audio
applications.
PSRR and CMRR exceed 120dB. These characteristics,
coupled with long-term drift of 0.2/JoVimonth, allow the circuit
ORDERING INFORMATIONt
TA = 25'C HERMETIC HERMETIC
DIP
vos MAX TO-99
8-PIN
8-PIN
(.V)
(e n =3.5nVlVHZ at 10Hz),a low 1/f noise corner frequency of
2.7Hz, and the high gain of 1.8 million, allow accurate high-gain
amplification of low-level signals .
PLASTIC
DIP
8·PIN
LCC
OPERATING
TEMPERATURE
RANGE
OP37EP
OP37BRC/883
OP37FP
OP37GP
PIN CONNECTIONS
'-::':~.::"'
MIL
INO/COM
MIL
IND/COM
MIL
IND/COM
"NVNC
4
• For dev,ces processed ,n total compliance to M IL·STD·883. add /883 after
part number. Consult factory for 883 data sheet.
t All commerCial and industrial temperature range parts are avaIlable with
burn-In. For ordering Information see 1986 Data Book, Section 2.
v- (CASE)
8-PIN HERMETIC DIP
(Z-Sufflx)
TO·99
EPOXY MINI-DIP
(J-Sufflx)
(P-Sufflx)
GENERAL DESCRIPTION
The OP-37 provides the same high performance as the OP-27,
but the design is optimized for circuits with gains greater
than five. This design change increases slew rate to 17V1/Josec
and gain-bandwidth product to 63MHz.
OP-37BRC/883
LCC PACKAGE
(RC-Suffix)
The OP-37 provides the low offset and drift of the OP-07 plus
higher speed and lower noise. Offsets down to 25/JoV and drift
of 0.6/JoVioC maximum make the OP-37 ideal for precision
instrumentation applications. Exceptionally low noise
SIMPLIFIED SCHEMATIC
r-------~--------~--------~--~--~r-----~------~--~~--~-ov,
OUTPUT
NON~
INVERTING
INPUT (0.':..1+-+~r-+----j~-k.
INVERTING
INPUT H
~~4--+-+
______
~
______
~
5-152
1/86, Rev. A
----------1~ OP-37 LOW-NOISE PRECISION HIGH-SPEED OPERATIONAL AMPLIFIER
designer to achieve performance levels previously attained
only by discrete designs.
Operating Temperature Range
OP-37A, OP-37B, OP-37C (J, Z, RC) .... -55°Cto+125°C
OP-37E, OP-37F, OP-37G (J, Z) ...... -25°C to +B5°C
OP-37E, OP-37F, OP-37G (P) ............ O°C to +70°C
Lead Temperature Range (Soldering, 60 sec) ...... 300°C
DICE Junction Temperature ........... -65°C to +150°C
Low-cost, high-volume production of the OP-37 is achieved by
using on-chip zener-zap trimming. This reliable and stable
offset trimming scheme has proved its effectiveness over
many years of production history.
NOTES:
The OP-37 brings low-noise instrumentation-type performance to such diverse applications as microphone, tapehead, and RIAA phono preamplifiers, high-speed signal conditioning for data acquisition systems, and wide-bandwidth
instrumentation.
1.
See table for maximum ambient temperature rating and derating factor.
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
PACKAGE TYPE
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
TO-99IJI
80'C
7.1mW/'C
8-Pin Hermetic DIP IZI
75'C
S.7mW/'C
ABSOLUTE MAXIMUM RATINGS (Note 4)
8-Pin Plastic DIP (P)
62'C
5.SmW/'C
Supply Voltage ................................... ±22V
Internal Power Dissipation (Note 1) .............. 500mW
Input Voltage (Note 3) ............................ ±22V
Output Short-Circuit Duration ................. Indefinite
Differential Input Voltage (Note 2) ................ ±0.7V
Differential Input Current (Note 2) ............... ±25mA
Storage Temperature Range ........... -65° C to +150° C
LCC
80'C
7.8mW/'C
2.
The OP-37's Inputs are protected by back-to-back diodes. Current limiting
resistors are not used
3.
4.
In
order to achieve low noise. If differential input
voltage exceeds ±O.7V, the input current should be limited to 25,mA.
For supply voltages less than ±22V, the absolute maximum input voltage IS
equal to the supply voltage.
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = 25° C, unless otherwise noted.
OP-37B/F
OP-37A/E
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vas
(Note 1)
Long-Term Vas
Stability
Vas/Time
(Notes 2,3)
los
Input BIBS Current
18
Input NOise Voltage
8 np _p
o 1Hz to 10Hz
(Notes 3,5)
to =
Voltage DenSity
fa
fo
'n
Input ReslstanceCommon-Mode
Input Voltage Range
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
~
~
10Hz INotes 3, 6)
30Hz I Notes 3, 6)
fo=1000Hz (Notes3,6)
Input ReslstanceDifferential-Mode
10Hz (Note 3)
fo =30Hz (Note 3)
to ~ 1000Hz INote 3)
en
Input Noise
Current DenSity
Voltage Gain
Output Voltage
Swing
MAX
10
MIN
MAX
TYP
MAX
25
20
60
30
100
"V
0.2
10
0.3
15
04
2.0
"V/Mo
50
12
75
nA
±10
±40
±12
±55
±15
±80
nA
008
018
008
018
009
025
"Vp-p
35
31
55
45
35
31
55
45
3.8
33
nV/y"HZ
30
3.8
30
38
32
8.0
56
45
17
40
17
40
1.7
10
0.4
23
06
10
23
06
10
04
0.4
094
IVR
CMRR
VCM = ±11V
PSSR
Vs
~
SR
GBW
0.7
'--"~'--~--
--~-~---
M!!
±123
±11.0
±12.3
V
114
126
106
123
100
120
dB
10
1000
~
fo~
1800
1500
800
250
RL" 2k!!INote 4)
fo
10kHz (Note 4)
10
1000
700
800
250
±13.8
±11.5
±12.0
±10.0
---~~--
~
20
1800
1500
700
1500
400
1500
700
200
500
±13.8
±11.5
±11.5
±10.0
±13.5
±11.5
"V/V
VimV
V
11
17
11
17
11
17
V/"s
45
63
40
45
63
40
45
63
40
MHz
lMHz
---:---~--'~-----
G!!
±11.0
1/86, Rev. A
5-153
-
pA/y"HZ
06
±123
±12.0
±10.0
RL " 2k!!
RL " 600!!
Slew Rate
UNITS
±110
±4V to ±18V
RL " lk!!, Vo ~ ±10V
Avo
RL ~ 600!!, Va ~ ±IV, Vs ~ ±4V, INote 4)
Gain Bandwidth Prod.
MIN
2.5
R 1NCM
Va
OP-37C/G
TYP
13
(Note 7)
R'N
RL" 2k!!, Vo ~ ±10V
large-Signal
TYP
35
Input Offset Current
Input NOise
MIN
--
,-----
----
----,--- '--
--- -
----
.--
--
---------I~ OP-37 LOW-NOISE PRECISION HIGH-SPEED OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs = ±15V. TA = 25°C. unless otherwise noted. (Continued)
OP-37A1E
PARAMETER
SYMBOL CONDITIONS
Open-Loop Output
MIN
TYP
Ro
Resistance
Power Consumption
TYP
OP-37C/G
MAX
MIN
70
140
90
Rp = 10k!!
Range
MIN
70
Vo=O
Offset Adjustment
OP-37B/F
MAX
MAX
UNITS
170
mW
!!
70
140
90
±40
TYP
100
±40
±4Q
mV
NOTES:
Input offset voltage measurements are performed by automated test
equrpment approximately 0.5 seconds after application of power AlE
grades guaranteed fully warmed up.
Long-term input offset voltage stability refers to the average trend line of
Vas VB. Time over extended penods after the first 30 days 01 operation.
Excluding the rnitlal hour 01 operation, changes in Vas dunng the first 30
days are typically 2.51-lV - refer to tYPical performance curve
Sample tested
Guaranteed by design.
5. See test circUIt and frequency response curve for 0 1Hz to 10Hz tester.
6 See test CircUit for current noise measurement.
Guaranteed by Input bias current.
3.
ELECTRICAL CHARACTERISTICS for Vs = ± 15V. -55°C:s TA:S +125°C. unless otherwise noted.
OP-37A
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
(Note 11
Average Input
TCVos
(Note 2)
Offset Dnft
TCVOs n
(Note3)
Input Offset Current
los
Input Bias Current
Is
Input Voltage Range
IVR
Common-Mode
Rejection Aatlo
Power Supply
Rejection RatiO
CMRR
VCM == ±10V
PSRR
vs = ±4 5V to ± l8V
MIN
SWing
30
02
OP-37C
TYP
MAX
TYP
MAX
60
50
200
70
300
06
03
13
04
18
MIN
MIN
UNITS
15
50
22
85
30
135
nA
±20
±60
±28
±95
±35
±150
nA
±1t 5
±10.3
±11.5
±10.2
±115
v
108
122
100
119
94
116
dB
16
20
51
600
1200
500
1000
300
800
VlmV
±115
±13.5
±110
±132
±10 5
±13.0
v
AvO
Output Voltage
MAX
±103
Large-Signal
Voltage Gain
OP-37B
TYP
ELECTRICAL CHARACTERISTICS for Vs
= ±15V. -25°C:S TA:S +85°C for OP-37J and OP-37Z. O°C:s TA:S +70° C for
OP-37P. unless otherwise noted.
OP-37E
PARAMETER
SYMBOL
Input Offset Voltage
Vas
Average Input
Offset Drift
TCVOS
TCVoSn
Input Offset Current
los
Input Bias Current
Ie
Input Voltage Range
IVA
Common-Mode
Rejection Aatio
Power Supply
Rejection Ratio
Output Voltage
SWing
MIN
(Note 21
(Note3)
CMRR
PSRR
Vs = ±4.5V to ± 18V
AVO
RL 2: 2k!!. Vo = ±10V
Large-Signal
Voltage Gam
CONDITIONS
OP-37F
MAX
TYP
MAX
50
40
140
55
220
06
03
13
04
18
MAX
20
0.2
MIN
MIN
UNITS
10
50
14
85
20
135
nA
±14
±60
±18
±95
±25
±150
nA
±10 5
±11.8
±10.5
±118
±10.5
±118
v
110
124
102
121
96
118
dB
15
16
32
750
1500
700
1300
450
1000
VlmV
±117
±136
±114
±13.5
±11.0
±133
v
NOTES:
1.
OP-37G
TYP
TYP
2.
The Tevos performance is within the specifications unnulled or when
nulled with Rp =8kil to 20k!!. TCVos is 100% tested for AlE grades. sample
tested for BICIFIG grades.
3. Guaranteed by design.
Input offset voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power. AlE
grades guaranteed fully warmed up.
5-154
1/86, Rev. A
---------I~ OP-37 LOW-NOISE PRECISION HIGH-SPEED OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
DIE SIZE 0.054 X 0.096 Inch, 5184 sq. mils
(1.37 X 2.44 mm, 3.35 sq. mm)
1.
2.
3.
4.
6.
7.
8.
For additional DICE information refer to
1986 Data Book, Section 2.
NULL
(-) INPUT
(+) INPUT
VOUTPUT
V+
NULL
WAFER TEST LIMITS at Vs = ± 15V, TA = 25° C for OP-37N, OP-37G and OP-37GR devices; TA = 125° C for OP-37NT and
OP-37GT devices, unless otherwise noted.
OP-37NT
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
(Note 1)
Input Offset Current
los
Input 818S Current
Ie
Input Voltage Range
IVR
Common-Mode
Rejection Ratio
CMRR
VcM =±11V
Power Supply
Rejection Ratio
PSRR
TA =25'C, Vs =±4Vto±18V
TA = 125'C, Vs = ±4 5V to ±18V
Large-Signal
Voltage Gain
Ava
Output Voltage Swing
Va
Power Consumption
Pd
RL~2kO,
RL~
RL~
RL~
Vo =±10V
1kO, Vo =±10V
OP-37G OP-37GR
LIMIT
LIMIT
LIMIT
LIMIT
UNITS
60
35
200
60
100
~VMAX
50
35
85
50
75
nAMAX
±60
±40
±95
±55
±80
nAMAX
±103
±11
±10.3
±11
±11
V MIN
108
114
100
106
100
dB MIN
10
16
10
10
20
10
20
600
1000
800
500
1000
800
700
±12.0
±100
±11.0
±120
±100
±11.5
±10.0
VMIN
140
170
mWMAX
±11.5
2kO
6000
OP-37N OP-37GT
LIMIT
140
Vo=O
~VIV
MAX
VlmV MIN
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±15V,
TA =
OP-37NT
CONDITIONS
Average Input Offset
Voltage Drift
TCVos or
Nulled or Unnulled
Rp = 8kO to 20kO
TeVoSn
+25°C, unless otherwise noted.
OP-37N OP-37GT
OP-37G OP-37GR
TYPICAL
TYPICAL
TYPICAL
TYPICAL
TYPICAL
UNITS
0.2
02
03
03
04
~V/'C
80
80
130
130
180
pAl'C
100
100
160
160
200
pAl'C
nV,jHZ
Average Input Offset
Current Dnft
TClos
Average Input Bias
Cu rrent Drift
TCl e
Input NOise
Voltage DenSity
en
fo= 10Hz
fa = 30Hz
fa = 1000Hz
3.5
31
30
35
31
30
35
31
3.0
35
3.1
30
38
33
32
Input Noise
Current Density
in
fa = 10Hz
fa = 30Hz
fa = 1000Hz
1.7
1.0
04
1.7
10
04
17
10
0.4
17
10
04
17
10
0.08
008
008
008
17
17
17
17
17
VI"s
63
63
63
63
63
MHz
Input NOise Voltage
e np _p
a 1Hz to 10Hz
Slew Rate
SR
RL~
Gain Bandwidth Product
GBW
fo= 10kHz
2kO
pAlVHZ
04
009
~
J.N p _p
-------.~---
NOTE:
Input offset voltage measurements are performed by automated test
equipment approximately a 5 seconds after application of power
R~\I_
5-155
------
"'~-
---
---~-----=-
>.L..
::s
P;
~.....:I
~
0......
~
r::r:
~
0
Electncal tests are performed at wafer probe to the limits shown Due to vanatlons In assembly methods and normal Yield loss, Yield after packaging IS not
guaranteed for standard product dice Consult factory to negotiate specificatIOns based on dice lot qualification through sample lot asembly and testing
SYMBOL
~
......
P;
NOTES:
For25'C charactenstlcsof OP-37NT and OP-37GT deVices, see OP-37N and
OP~37G charactenstlcs, respectively
PARAMETER
~
..- - - - - - -
~~-----
--..
-
~
~
-.
-~-
---
fit
----------l~ OP-37 LOW-NOISE PRECISION HIGH-SPEED OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
NOISE-TESTER FREQUENCY
RESPONSE (O.1Hz TO 10Hz)
100
90
-
80
\\
'0
9
l~
o2
60
6
,
4
is
>
,
0'
, 0
,
,
,
I
.......
lOW NOISE
AUDIO
III CORNEA
27Hz /
I/f CORNER
'" 2 7Hz
~~ , OP AMP
I IIIII
IJ UllL
INSTRUMENTATION
1
100
1000
10
FREQUENCY (Hz)
INPUT WIDEBAND VOLTAGE
NOISE vs BANDWIDTH (O.1Hz
TO FREQUENCY INDICATED)
III
AVOIO RANGE
TO 20kHz
RANGE, TO DC
'0
100
FREQUENCY (Hz)
1/1 CORNER
-- -
~ ~OP-37
2
I
10
-
l/f CORNER
n'i'IIII~IW FIIIIIIIIICY ITl'l il l GAiNI
30
00'
741
.......
3
"iO
I
TEST TIME OF 10sec MUST BE USED TO
40
r-
TA '" 2S C
Vs = ±15V
D
,>5 I'
~
~
l-
'00
8
7
70
50
A COMPARISON OF
OP AMP VOLTAGE
NOISE SPECTRA
VOLTAGE NOISE DENSITY
VB FREQUENCY
1000
'00
FREQUENCY 1Hz)
TOTAL NOISE vs SOURCE
RESISTANCE
VOLTAGE NOISE DENSITY
VB TEMPERATURE
100 F~=Ff=RR'fFF====="!1
~TA=250C
~ ~
15,V--t-;rtttt'-_ ~ .. rl-_V_'r-=_±t-
1---I--H-rI+++1--
RS '" 2Rl
0',,_
lk
10k
~
~
"~
o
> 21---i--t---r-+--t---t--1
,
100
lOOk
BANDWIDTH (Hz)
VOLTAGE NOISE DENSITY
VB SUPPLY VOLTAGE
lk
SOURCE RESISTANCE
10k
-
-50
-25
25
0
50
75
'00
125
TEMPERATURE (DC)
(m
SUPPLY CURRENT vs
SUPPLY VOLTAGE
CURRENT NOISE DENSITY
VB FREQUENCY
50
100
T!
3 P-i--t-=.,...=-AT 1kHz
w
= 2SoC
40
AT 10Hz
I--
AT
~
lkH~
I
30
20
Ilf CORNER
r- - " , 140Hz
01
'0
20
30
TOTAL SUPPLY VOL TAGE (V+ - V-I (VOLTS)
40
11111111
10
TA "" _5SD C
I
100
lk
FREQUENCY (Hz)
5-156
10
10k
15
25
35
45
TOTAL SUPPLY VOLTAGE (VOLTS)
1/86, Rev. A
-------4~ OP-37
LOW-NOISE PRECISION HIGH-SPEED OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
LONG-TERM OFFSET
VOLTAGE DRIFT OF SIX
REPRESENTATIVE UNITS
OFFSET VOLTAGE DRIFT OF
EIGHT REPRESENTATIVE
UNITS V8 TEMPERATURE
60
40
'>
.3
20
~
w
~
...~~
.;::",
-
/
aP-37C
OP-376
V /'
V
- -/'
V .....,<..
~ 2
/
/'
-40
TRIMMING WITH"'
10k POT DOES
NOT CHANGE
T~VOS,
-60
-75
50
25
,
,
0
25
~ -6
:::
o
I
OP-37C/G
6
./'
"~
I
I
5
.L"..
0
-
'"
i'-'
-2
-4
........ OP-37C
100
-6
125 150 175
o
TEMPERATURE (OC)
~
30
I
I
~
~ 25
g
t;;
2SOC
~
~ 15
f-If-f--
}j
z
<
r+-
10
f-r-
Ii
w
40
Vs
=
I I
Vs = ±15V-
±15V
~
i \ OP-37C
OP-37C
[\,1\,
,,~
RESPONSE
i' "- ....
"r--.
BA' I I
IIf I I I
OP-37B
~kI...u
I
40
60
80
100
-25
80
TAI= +2StC
75
70
RL ;;:,. 2kS1
"'"
BO
60
40
65
'"
60
'\.
55
r\.
~
C
\
102
103
104
10 5
FREQUENCY (Hz)
10 6
20
~
15
oj
107
108
Vs ""5V
75
100
125
....-
~
150
-75
-50
-25
-
10
-50
-25
90
60
85
I'..
50
75
70
i
OP 37A
25
50
40
Vs
75
100
60
r- 55
I. ~,l~ II
125
-80
-100
TA -"+2SoC
1-10-
-120
PHASE
30
\
65
-...
0
GAIN, PHASE SHIFT vs
FREQUENCY
80
r- ~W
OP-37B
TEMPERATURE (oC)
I
75
v
~
o ·4
OP-37B
........
50
"~
,-'"
0
OP-37A
r-..
-20
i!;
w
A
"., OPT
WARM-UP OFFSET
VOLTAGE DRIFT
-140
MARGIN
'" 71°
-160
20
AV '" 5
-180
10
"
50
SLEW
-200
45
40
a
+25
+50
+75
TEMPERATURE (OC)
5-157
+100
+125
-10
lOOk
-220
1M
10M
100M
FREQUENCY (Hz)
1/86, Rev. A
---------I~ OP-37 LOW-NOISE PRECISION HIGH-SPEED OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN-LOOP VOLTAGE GAIN
VB SUPPLY VOLTAGE
MAXIMUM OUTPUT SWING
V8 FREQUENCY
28
2S
18
v}= 1"lsU
Rl ·2k.l1
.Y
-TALsoc
20
MAXIMUM OUTPUT VOLTAGE
V8 LOAD RESISTANCE
/'
/
~ 24
o
2:.
Rl=lkn
/'-
16
TA = 2S'e
f-
1\
20
poJITIJe
I-
~
" 16
.;'
~
~ /'"
NEGATIVE
SWING
:11
"
IV
~
8
~
4
"..
os
//
12
~
~
~
00
t-
o
10
20
30
40
TOTAL SUPPLY VOLTAGE (VOLTS)
105
TA'" 2SoC
Vs = ±15V
I III
~2
104
50
100
106
10k
lk
LOAD RESISTANCE (11)
FREQUENCY (Hz)
SMALL-SIGNAL OVERSHOOT
VB CAPACITIVE LOAD
:;;;..-
SWING
LARGE-SIGNAL TRANSIENT
RESPONSE
SMALL-SIGNAL TRANSIENT
RESPONSE
80
Vs = ±15V
VIN =20mV
+50mV
AV = +5 (lkn, 260m
BO
I-
0
0
~
i;
40
I
I-
~
a:
~
20
o
+10V
. / i'-"
~
V
-TOV
-somv • • • •
I
o
ov
ov
Vs"' ±15V
Av = +5 (1kil, 2500)
TA = +25°C
Vs = ±15V
AV = +5 (1kil. 250n)
TA =+2s<'C
1000
1600
CAPACITIVE LOAD (pFJ
500
2000
SHORT-CIRCUIT CURRENT
VB TIME
140
60
<'50
120
S
I-
"-
a')
~ 40
::>
"'-=
u
I-
:;
~ 30
U
a:
""-
lBr-----r-----;------r~~-,
l!ll!I"Jvi I
r-
12r-------1---
TA =+2SoC
VCM = tlDV
I"
T A = +250
Vs = ±15V
r--.'sc~1
COMMON-MODE INPUT RANGE
VB SUPPLY VOLTAGE
CMRR VI FREQUENCY
ac~
ll:
iii 100
:!1.
a:
a:
Ej
~
~,
z
~ 20
-41-----~~~+----_+_----__1
! ~81------I----,3~
ISC (+)
""o
41-----:i;d~~+----+----_l
.. 01----7'-+-----+----_+_----__1
\
80
8
60
___
-121------\----+-~~..---_l
10
o
TIME FROM OUTPUT SHORTED TO GROUND (MINUTES)
-16 L....____- ' -____- ' -____--'-____--.J
40
lk
10k
lOOk
FREQUENCY (Hz)
5-158
1M
10M
±S
±15
±20
SUPPLY VOLTAGE (VOLTS)
1/86, Rev. A
---------l~ OP-37 LOW-NOISE PRECISION HIGH-SPEED OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN-LOOP VOLTAGE GAIN
vs LOAD RESISTANCE
LOW-FREQUENCY NOISE
NOISE TEST CIRCUIT (O.1Hz TO 10Hz)
120
~
80
~
40
o
z
w
t:l
~
o
>
VOLTAGE GAIN
- 50,000
-40
-80
-120
a 1Hz TO
10Hz PEAK-TO-PEAK NOISE
1--H1'+t+ttt+-+-H-iffl-t-+-H-I+ttti
04L-~~~L-~~llllL-~-U~
NOTE:
NOTE
0.6
lOa
lk
Observation time limited to 10 seconds,
ALL CAPACITOR VALUES ARE FOR
NON POLARIZED CAPACITORS ONLY
10k
LOAD RESISTANCE
100k
1m
SLEW RATE
PSRR vs FREQUENCY
160
140
120
100
80
TA
-~
1=
25O~_
SLEW RATE vs LOAD
19
t--
TA = J25 0 C
AV '" +5
15
NEGATIVE
~UPPLY
17
~
16
60
0
20
lk
10k
~ ~
AVCL = +5
VO" 20V p-p
SUPPLY
100
20
tAl. ~Wl"
Vs = ±15V
18
-POSITI~
10
vs SUPPLY VOLTAGE
p~
---::
FALL
,.
V
~
100k
~
1M
10M 100M
FREQUENCY (Hz)
15
100
lk
10k
100k
o
±S
'3
LOAD RESISTANCE en)
APPLICATIONS INFORMATION
Thermoelectric voltages generated by dissimilar metals at
the input terminal contacts can degrade the drift performance. Best operation will be obtained when both input
contacts are maintained at the same temperature.
±l2
±15
±18
±2l
OFFSET NULLING CIRCUIT
OP-37 Series units may be inserted directly into 725, OP-06,
OP-07, and OP-05 sockets with or without removal of external
compensation or nulling components. Additionally, the OP37 may be fitted to unnulled 741-type sockets; however, if
conventional 741 nulling circuitry is in use, it should be modified or removed to ensure correct OP-37 operation. OP-37
offset voltage may be nulled to zero (or other desired setting)
using a potentiometer (see offset nulling circuit).
The OP-37 provides stable operation with load capacitances
of up to 1000pF and ± 10V swings; larger capacitances should
be decoupled with a 500 resistor inside the feedback loop.
Closed-loop gain must be at least five. For closed-loop gain
between five to ten, the designer should consider both the
OP-27 and the OP-37. For gains above ten, the OP-37 has a
clear advantage over the unity-gain-stable OP-27.
±9
SUPPLY VOLTAGE (VOLTS)
>...
~-'------{)v+
>-7...'6____.0 OUTPUT
OFFSET VOLTAGE ADJUSTMENT
The input offset voltage of the OP-37 is trimmed at wafer
level. However, if further adjustment of Vos is necessary, a
10kO trim potentiometer may be used. TCVosis not degraded
(see offset nulling circuit). Other potentiometer values from
1kO to 1MO can be used with a slight degradation (0.1 to
0.2p.V/o C) of TCVos. Trimming to a value other than zero
creates a drift of approximately (Vosl300) p.V/ o C. For exam-
5·159
1/86, Rev. A
II
_ _ _ _ _ _ _;~ OP-37 LOW-NOISE PRECISION HIGH-SPEED OPERATIONAL AMPLIFIER
pie, the change In TeVos will be 0.33~Vloe If Vos is adjusted
to 100~V. The offset-voltage adjustment range with a 10kO
potentiometer is ±4mV. If smaller adjustment range Is required, the nulling sensitivity can be reduced by using a
smaller pot in conjunction with fixed resistors. For example,
the network below will have a ±280~V adjustment range.
4.7kG
1kGPOT
4.7kG
INSTRUMENTATION AMPLIFIER
A three-op-amp instrumentation amplifier provides high gain
and wide bandwidth. The Input noise of the circuit below Is
4.9nVlJ"HZ. The gain of the input stage is set at 25 and the
gain of the second stage is 40; overall gain Is 1000. The
amplifier bandwidth of 800kHz Is extraordinarily good for a
preciSion Instrumentation amplifier. Set to a gain of 1000, this
yields a gain-bandwidth product of 800M Hz. The full-power
bandwidth for a 20Vp _p output is 250kHz. Potentiometer R7
provides quadrature trimming to optimize the instrumentation amplifier's Ae common-mode rejection.
BURN-IN CIRCUIT
"6 0 1%
soon
"8
20kn 0.1%
R6
R9
198kSl
soon 0 1%
NOISE MEASUREMENTS
To measure the 80nV peak-to-peak noise specification of the
OP-37 in the 0.1 Hz to 10Hz range, the following precautions
must be observed:
• TRIM R2 FOR AVCL = 1000
• TRIM R10 FOR de CMRR
• TRIM R7 FOR MINIMUM Your
AT V CM = 20V p_p, 10KHz
(1) The device has to be warmed-up for at leastfive minutes.
As shown In the warm-up drift curve, the offset voltage
typically changes 4~V due to increasing chip temperature after power-up. In the 10 second measurement interval, these temperature-induced effects can exceed tensof- nanovolts.
,40
l~ -l
,
"
"
,20
(2) For similar reasons, the device has to be well-shielded
from air currents. Shielding minimizes thermocouple
effects.
r-.
iii 100
RS = lkG,
BALANCED
:s
""iIj
"s = ,00 3kO. The only exception is
when gain error is Important. Figure 3 illustrates the 10Hz
noise. As expected, the results are between the previous two
figures.
2 RSMATCHED
egRs=lOk,RS1=RS2-5k
];
~~:~I~~~
10
50 100
Figure 2
500 1k
100
,=iY>,
Figure 2 shows the 0,1 Hz-to-10Hz peak-to-peak noise. Here
the picture Is less favorable; resistor noise is negligible, current noise becomes important because it is inversely proportional to the square-root of frequency. The crossover with the
OP-07 occurs in the 3-to 5kO range depending on whether
balanced or unbalanced source resistors are used (at3kO the
IB' los error also can be three times the Vos spec.).
553.
QP-07
~ol,sr I~~~IT
beyond Rs of 20kO that current noise starts to dominate. The
argument can be made that current noise is not important for
applications with low-to-moderate source resistances. The
crossover between the OP-37 and OP-07 and OP-08 noise
occurs In the 15-to-40kO region.
PEAK-TO-PEAK NOISE (0.1 to
10Hz) VB SOURCE RESISTANCE
(INCLUDES RESISTOR NOISE)
500
8gRS"lOk,Rs,"Rs2"6k
~RESISTOR
RS2
500 1k
2RSMATCHED
fT'J.
itt>
~~SISTOR
NOISE ONLY
1
1 As UNMATCHED
egRs-Rs''''Ok,RS2aQ
2 RSMATCHED
.gRS"'Ok,RS,-RS2006k
=iY>,
R52
500 1k
5k 10k
RS - SOURCE RESISTANCE (m
50k
For reference, typical source resistances of some signal
sources are listed in Table 1.
prefer to use direct coupling. The high IB' Tevos of previous
designs have made direct coupling difficult, If not Impossible,
to use.
Table 1
DEVICE
Voltage noise Is Inversely proportional to the square-root of
bias current, but current noise Is proportional to the squareroot of bias current. The OP-37's noise advantage disappears
when high source-resistors are used. Figures 1, 2, and 3
compare OP-37 observed total noise with the noise performance of other devices In different circuit applications.
Total noise = f(Voltage nolse)2
(reSistor nolse 2 ]1/2
SOURCE
IMPEDANCE
<5000
Typically used In low-frequency
applicatIons,
MagnetIc
tapehead
<15000
Low Ie very Important to reduce
self-magnetization problems when
direct coupling IS used, OP-37 Ie
can be neglected
Magnetic
phonograph
cartridges
<15000
SimIlar need for low Ie In dIrect
coupled applications, OP-37 WIll not
Introduce any self-magnetIZatIon
problem,
Linear vanable
dIfferentIal
transformer
<15000
Used in rugged servo-feedback
applications Bandwidth of onterest
is 400Hz to 5kHz,
+ (current noise x RS)2 +
Figure 1 shows nolse-versus-source-reslstance at 1000Hz.
The same plot applies to wide band noise. To use this plot,
just multiply the vertical scale by the square-root of the
bandwidth.
At Rs<1 kO, the OP-37's low voltage noise is maintained, With
Rs< 1kO, total noise Increases, but Is dominated by the resistor noise rather than current or voltage noise. It Is only
5-161
COMMENTS
Straon gauge
1/86, Rev. A
II
--------I~ OP-37 LOW-NOISE PRECISION HIGH-SPEED OPERATIONAL AMPLIFIER
AUDIO APPLICATIONS
The following applications information has been abstracted
from a PMI article in the 12120/80 issue of Electronic Design
magazine and updated.
0412)
220~F
~~
,___ 6 ,~okn-:;;.
LF ROLLOFF
":'
OUT
C3
This circuit is capable of very low distortion over Its entire
range, generally below 0.01% at levels up to 7V rms. At 3V
output levels, it will produce less than 0.03% total harmonic
distortion at frequencies up to 20kHz.
Capacitor C3 and resistor R4 form a simple -6dB-per-octave
rumble filter, with a corner at 22Hz. As an option, the switchselected shunt capacitor C4, a non polarized electrolytic,
bypasses the low-frequency roll off. Placing the rumble filter's high-pass action after the preamp has the desirable
result of discriminating against the RIAA-amplifled lowfrequency noise components and pickup-produced lowfrequency disturbances.
A preamplifier for NAB tape playback is similar to an RIAA
phono preamp, though more gain Is typically demanded,
along with equalization requiring a heavy low-frequency
boost. The circuit in Fig. 4 can be readily modified for tape
use, as shown by Fig. 5.
O.47~F
C2
O.Ot~F
R3
,001000
pF
150
0
250
>1000
250
>1000
ps
-----"
Open-Loop Output
Resistance
150
Ro
150
NOTES:
1 Warmed up VCM = 0
2 Guaranteed by CMR test
3 Guaranteed but not tested
'OP-41G SPECIFICATIONS ARE SUBJECT TO CHANGE AT TIME OF INTRODUCTION
ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = -55° C/+125° C, unless otherwise noted.
OP-41A
PARAMETER
SYMBOL
Offset Voltage
CONDITIONS
MIN
OP-41B
TYP
MAX
Vas
400
1000
TCVos
25
MIN
TYP
MAX
UNITS
600
2000
/J.V
35
10
/J.vrc
Temperature
Coefficient of
Input Offset
Voltage
Offset Current
los
(Note 1)
40
1000
50
2000
pA
Bias Current
18
(Note 1)
4000
7500
4500
15000
pA
Ava
RL = 2kO
Va = ±lOV
Output Voltage
SWing
Va
RL = 2kO
Supply Current
ISY
Open-Loop
1000
5000
500
3000
VlmV
±120
±125
±115
±12.5
V
Va = OV
75
IVR
(Note 2)
±11
+15
-11 5
±11
+15
-115
V
CMR
VCM = ±11V
95
105
85
100
dB
PSRR
Vs = ±10V to ±20V
Short CirCUit
Output Current
Isc
Short Circuit to Ground
Slew Rate
SR
Voltage Gain
Input Voltage
Range
Common-Mode
Rejection
Power Supply
Rejection Ratio
Gain Bandwidth
Power Bandwidth
Capacitive Load
Stability
12
75
40
±6
GBW
BWp
Av = +1
(Note 3)
100
+12
-17
±36
±6
12
mA
10
100
pV/v
+12
-17
±36
mA
13
13
Vips
500
500
kHz
20
20
kHz
>1000
pF
>1000
100
NOTES:
Warmed up. VCM = 0
Guaranteed by CMR test
Guaranteed but not tested
5-166
1/86, Rev. A
---
-------
~ OP-41
LOW-BIAS-CURRENT JFET OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs
= ±15V,
TA
= -25°C/+85°C
for ElF grades and O°C/70°C for G grade, unless
otherwise noted.
OP-41E
PARAMETER
SYMBOL
Offset Voltage
CONDITIONS
OP-41G*
OP-41F
TYP
MAX
Vos
250
1000
TCVos
3.5
MIN
MIN
TYP
MAX
500
2000
MIN
TYP
MAX
UNITS
500
2000
IJ V
Temperature
Coefficient of
Input Offset
Voltage
Offset Current
los
(Note 1)
Bias Current
Is
(Note 1)
Open-Loop
Voltage Gain
Avo
RL
Vo
=2kO
=±10V
Output Voltage
Swing
Vo
RL
=2kO
Supply Current
ISY
Vo
Input Voltage
Range
Common~Mode
Rejection
Power Supply
Rejection Ratio
240
IJVloC
75
100
10
200
20
500
300
1000
100
pA
500
pA
1000
5000
500
4000
300
3000
VlmV
±12.0
±126
±115
±125
±11
±126
V
=OV
75
IVR
(Note 2)
±110
+15
-115
±11
+15
-115
±11
+15
-115
V
CMR
VCM
95
110
85
100
85
100
dB
PSRR
Vs
Short CIrcuIt
=±1W
=±10V to ±20V
Short CIrcuit
Output Current
7.5
Isc
±6
to Ground
75
12
5-
40
+16
-18
±36
±6
1.2
10
100
+16
-18
±36
75
±6
1.2
mA
10
100
IJVIV
+20
-18
±36
mA
Slew Rate
SR
13
13
13
Gain Bandwidth
GBW
500
500
500
kHz
Power Bandwidth
BWp
20
20
20
kHz
>1000
pF
Av = +1
(Note 3)
Capacitive Load
Stability
100
>1000
100
>1000
100
VII'S
NOTES:
VCM = 0
2. Guaranteed by CMR test.
3. Guaranteed but not tested.
'OP-41G SPECIFICATIONS ARE SUBJECT TO CHANGE AT TIME OF INTRODUCTION
1. Warmed up.
BURN-IN CIRCUIT
+18V
10k!}
+3Vo----''Mr--,
10kfl.
-lav
5-167
1/86, Rev. A
II
ffi.....
i:l-<
::sp..,
~
~
0.....
~
~
p..,
0
_ _ _ _ _ _ _ _ _--;~ OP-41 LOW-BIAS-CURRENT JFET OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
1.
2.
3.
4.
OFFSET VOLTAGE NULL
INVERTING INPUT
NONINVERTING INPUT
NEGATIVE SUPPLY
5. OFFSET VOLTAGE NULL
6. AMPLIFIER OUTPUT
7. POSITIVE SUPPLY
For additional DICE information refer to
1986 Data Book, Section 2.
DIE SIZE 0.103 X 0.074 inch, 7622 sq. mils
(2.62 X 1.88mm, 4.92 sq. mm)
WAFER TEST LIMITS at Vs = ±15V, TA = 25° C, unless otherwise noted.
PARAMETER
SYMBOL
Offset Voltage
Vas
Bias Current
CONDITIONS
OP-41N
LIMIT
UNITS
1000
/-IV MAX
18
(Note 1)
20
pA MAX
Open-Loop Voltage Gain
Ava
RL = 2kO
500
VlmV MIN
Output Voltage SWing
Va
RL = 2kO
±12
VMIN
Supply Current
ISY
Va = OV
12
mAMAX
Input Voltage Range
IVR
(Note 2)
±11
VMIN
Common-Mode
RejectIon
CMR
VCM = ±11V
90
dB MIN
Power Supply
Rejection RatiO
PSRR
Vs = ±10V to ±20V
80
/-IVIV MAX
Isc
Short Circuit to Ground
±6
±36
mAMIN
mAMAX
Short CirCUit
Output Current
Slew Rate
Capacitive Load
Stability
SR
Av = +1
VI/-Is MIN
(Note 3)
250
pF MIN
NOTES:
1 VCM =0
2 Guaranteed by CMR test
3 Guaranteed but not tested
Electrical tests are performed at wafer probe to the limits shown Due to vanatlons In assembly methods and normal Yield loss, Yield after packaging IS not guaranteed
for standard product dice Consult factory to negotiate specifications based on dice lot qualificatIon through sample lot assembly and testing
5-168
1/86, Rev_ A
-----------I1fMD
OP-41 LOW-BIAS-CURRENT JFET OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
BIAS CURRENT vs
TEMPERATURE
OFFSET CURRENT vs
TEMPERATURE
BIAS CURRENT vs
COMMON-MODE VOLTAGE
'a'
'00
/
'a'
!...
~a:
::>
'02
!...
/'/
'0'
u
~
a;
/
/
V
/
'a'
10-1
V
10-2
-50
-75
~
-25
25
50
75
100
-'5
-10
w
"
:I:
u
1\
-600
-500
w
:;"
~
-400
0
> -300
~
>
3
\
0
-100
8
~
\
6
"~
o
>
~
,
o
±10
'5
±15
'20
'00
840
820
80
::> 800
60
u
-- -
~
720
700
'4
IV
-
1...
i:la:
'8
'25
~~
±16
820
780
r- ........
760
740
I
720
'0
'2
700
-75
-50
'""'-.........
\.
"
80
"-
40
±20
0'
PHASE
'00
100
lk
FREQUENCY (Hz)
5-169
10k
,'0
,
,
,
20
"
lOOk
50
75
1M
-r--...
'20
'00
80
~
10
'40
90
' - MARGIN
'" 77"
25
100
125
POWER SUPPLY REJECTION
vs FREQUENCY
70
~
-25
TEMPERATURE (c GI
60
20
SUPPlVVOLTAGE (VOLTS)
840
u
~ij;
-20
±12
'00
a:
::> 800
'40
860
740
75
--
OPEN-LOOP GAIN AND
PHASE vs FREQUENCY
900
~
50
SUPPLY CURRENT
vs TEMPERATURE
TIME AFTER SUPPLY TURN-ON (MIN)
880
~
25
860
o
±20
SUPPLY CURRENT
ij; 760
/
a
880
o
vs SUPPLY VOLTAGE
780
i
2
SUPPLY VOLTAGE (VOLTS)
~
v
a:
a
...
'5
900
Ii:
1\
\
-200
~
0'
'0
-5
'0
Z
~
~
WARM-UP DRIFT vs TIME
-800
-700
/
COMMON-MODE VOLTAGE (VOLTS)
OFFSET VOLTAGE vs
SUPPLY VOLTAGE
>
3
::>
u
o
a
125
TEMPERATURE (c c)
10
~
~
io"""
.V
V
/
60
'" " , " '\
-PSR
40
30
20
40
o
,
+PSR
~
i\.
"'- ~
10
100
lk
10k
lOOk
1M
FREQUENCY (Hz)
1/86, Rev. A
_ _ _ _ _ _ _ _ _----;~ OP-41 LOW-BIAS-CURRENT JFET OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
MAXIMUM OUTPUT SWING
VI FREQUENCY
COMMON-MODE REJECTION
VI FREQUENCY
14
,
120 ~!±!!I:IH-~-++I+ItHf--t-tlfJttttt-ttttttlt
100
I.
30
140 r-r"l"T11mr-T"T1"1'TT111"""T"nmrm-TTTmr-r1rmm
-pJs'u~
OUTPUT
13
;;;
\
H+H+llII-+H+I1I!I..-l
MAXIMUM OUTPUT VOLTAGE
VI LOAD RESISTANCE
~
~ 12
o
C
11
"'~
10
~
9
...
8
g
6
o
>
1\!,
it
~
~~¥~J~VE_
7
IfJ
o
10k
lk
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC
DISTORTION VI FREQUENCY
SLEW RATE VI
TEMPERATURE
Vo = 10Vp-p
¥/
~
I.
~
01
001
~ -I-
i-"
::;:... ~VCL
~-
~
1-0...
i"""-o .......:
!<"'a: '4
~ 13
=10
~,
-
POSITIVE
-
NEGATIVE
12
0.001
00001
100
11
III
1k
/
-2
-4
-6
-8
10
-75
10k
AV ·-1
RL'" 2.Skn
T001%/A
A ~OO.J,%
16
AveL ·'00
lOOk
SETTLING TIME
10
17
10
10k
lk
RL = 2kn
RL = 10kU
10
1.
LOAD RESISTANCE 1m
18
100
3
100
-10
-50
-25
25
50
75
100
125
o
I~ ,TO 0.01%
TOO1~
""
t'....
10
12
SETTLING TIME (,..IS)
TEMPERATURE (coC)
FREQUENCY (Hz)
"" '"
SMALL-SIGNAL OVERSHOOT
VI CAPACITIVE LOAD
40
3.
~
30
!!
2.
8ili
20
~
16
Z
a:
,
~
"
II
10
o
/X
~
il
o
500
1000
1600
2000
2500
3000
3500
CAPACITIVE LOAD (pF)
5-170
1/86, Rev. A
-----------I~ OP-41 LOW-BIAS-CURRENT JFET OPERATIONAL AMPLIFIER
OFFSET VOLTAGE ADJUSTMENT
FIGURE 3: SMALL-SIGNAL TRANSIENT RESPONSE
Offset voltage is adjusted by a potentiometer of 10kO to 100kO
resistance. This potentiometer should be connected between
pins 1 and 5 with the wiper connected to the V- supply. (See
Figure 1.) Nulling Vos will change TCVos by no more than
5fJV/o C per millivolt of Vos change
FIGURE 1: INPUT OFFSET VOLTAGE NULLING
v'
FIGURE 4: SMALL-SIGNAL TRANSIENT RESPONSE WITH
1000pF LOAD
vNOTE
Vas CAN BE TRIMMED WITH POTENTIOMETER
RANGING FROM 10kn TO 100kn
APPLICATIONS INFORMATION
TYPICAL AC PERFORMANCE CHARACTERISTICS
Figure 2 shows the overload recovery time after the output
saturates at each supply. A high degree of slew-rate symmetry
is maintained even during severe input overload The photo
also shows the well controlled linear characteristics of the
amplifier and freedom from oscillations The OP-41 's symmetry
greatly reduces the generation of large DC components in the
output when the amplifier is overdriven. This significantly
reduces system recovery time after an overload.
FIGURE 5: WIDE-DYNAMiC-RANGE LIGHT DETECTOR
""4pF
109 n
Figure 3 shows the unity-gain small-signal transient response
of the OP-41. Note the clean symmetrical waveform.
Figure 4 illustrates the high degree of stability even when
loaded with 1000pF at unity-gain. Heavy capacitive loading will
cause stability problems with many amplifiers.
>---<>--. Va'" 0 5V!nW
Figure 5 illustrates the use of the OP-41 in a high sensitivity,
wide-dynamlc-range light detector. ThiS circuit Will produce an
output voltage proportional to the light input over a60dB range.
FIGURE 2: OVERLOAD RECOVERY TIME AT Av = 10
CMR MEASUREMENT METHODS
Two separate methods are used to measure the CMR. The first
method is used over the range of 10Hz to 20kHz. This method
grounds the input circuitry and applies the common-mode
signal to the remainder of the op amp, Figure 6.
The AMP-01 eliminates loading on the output stage. This
assures that the OP-41 output is not required to deliver current
into the feedback circuit. The effects of the DUT open-loop gain
changing with frequency are therefore significantly reduced.
The Circuit does not require tight resistor matching. DC data
sheet limits may be verified using this method. Circuit accuracy
is dependent on the high CMR of the AMP-01.
5-171
1/86, Rev. A
------------l!EMD
OP-41 LOW-BIAS-CURRENT JFET OPERATIONAL AMPLIFIER
FIGURE 6: CIRCUIT USED TO MEASURE CMR FROM 10Hz
TO 20kHz
transmitters. Loss of accuracy can also occur from surface and
bulk leakages in printed circuit boards. Both of these conditions
can be avoided by the following methods.
Hum and RF pickup are eliminated or reduced by keeping all
high Impedance leads, including feedback resistor leads, inside
shielded enclosures. In addition to shielding, power supply
lines should be bypassed where they pass through the shielding. This will prevent noise from being retransmitted from the
power supply lines inside the shielded enclosure.
9kn
1kH
1kH
AMP-01
AV= 1
Noise can also be created by the flexing of coax cable. These
signals can be caused by mechanical vibrations inside or
outside the shielding. Prevention consists of securely supporting all high-impedance shielded lines to prevent motion.
Printed circuit board leakage currents can easily exceed the
OP-41 bias currents or the incoming signal. Leakage currents
can be minimized by using Teflon insulators to support wires
instead of using PC traces. An alternate method is guarding the
high impedance traces. When the OP-41 is in the inverting
mode, the signal traces should have grounded guard traces on
both sides, Figure 8. The opposite side of the board should be
used as a ground plane and shield, if not otherwise used. A
ground plane is implemented by leaving copper on all areas
that are not being used for signal or power conduction. Ground
connection should be made to all areas of isolated copper. In
the noninverting configuration, the OP-41 's output signal or a
portion of it should be used to drive the guard traces, Figure 9
When the guard drive voltage is equal to the input signal,
leakage currents will be effectively eliminated.
An alternate circuit may be used to make high-frequency
measurements from 2kHz to 500kHz, Figure 7. The 2kHz to
20kHz data overlap can be used to verify the accuracy of the
respective test methods.
This method drives the input stage with the test signal and
requires an accurate ratio of resistors, R4/R3 = R1/R2. To
measure CMR to 100dB requires ratio matching to better than
10ppm. For this reason, it is not practical to use the second
method at low frequencies where CMR is greater than 80-100dB.
The OUT output is normally connected directly to R4 which
may cause problems. If the OUT is not buffered with a broadband low-output-impedance amplifier, the frequency-dependent output impedance of the OUT, in series with R4, rapidly
unbalances the resistor ratios. This causes frequency dependent errors. The OP-27 provides good performance over the
range of frequencies used.
FIGURE 8: CURRENT-TO-VOLTAGE CONVERTER
r--------..,
I
I
GUARD"./
I
I
FIGURE 7: CIRCUIT USED TO MEASURE CMR FROM 2kHz
TO 500kHz
r-----J
I
I
2
>,~~-oOUT
rOGAIN/PHASE METER
R4
R3
>-+~·~~IN/PHASE
1kn
FIGURE 9: VERY HIGH IMPEDANCE NON INVERTING
AMPLIFIER
METER
R2
1kn
"v
R1
9kn
GUARDING AND SHIELDING
In applications where the input is at high impedance, careful
shielding is required to prevent hum pickup from power line
sources or detection of RF from radio stations and nearby radar
5-172
1/86, Rev. A
-----------I~ OP-41 LOW-BIAS-CURRENT JFET OPERATIONAL AMPLIFIER
The High Q Notch Filter benefits from the low bias current and
high input impedance of the OP-41 , Figure 10. These features
enable small value capacitors and large resistors to be used in
this 60Hz notch filter. The 5pA bias current only develops 100/lV
across R1 and R2.
FIGURE 10: HIGH
FIGURE 12: AMPLIFIER FOR PIEZOELECTRICTRANSDUCERS
~--o---O-------------jI~
250n
+IN~--W~-------+-_+----'
I
IL
I
I
I
I
I
I
____________ _
----------------~
V-
*NOTE SEPARATE SUPPLIES FOR OUTPUT STAGE
Manufactured under the follOWing patents 4.471,321 and 4.503.381
5-180
1/86, Rev. A
-------------I~ OP-50 HIGH-OUTPUT-CURRENT OPERATIONAL AMPLIFIER
The OP-50 is stable for closed-loop gains above 50, and can
be externally compensated for closed-loop gains in the range
of 5 to 50. The amplifier is designed for use in high-gain
and/or high-output-current applications. For example, an
OP-07 coupled with an output buffer can be replaced by a
single OP-50 amplifier.
A thermal-shutdown circuit protects the OP-50 from overdissipation. When the die temperature reaches approximately
165°C, the output stage automatically shuts down. The
amplifier input stage remains fully operational, thereby protecting the signal source from any loading changes caused
by a complete shutdown.
lon-implanted superbeta transistors, combined with a patented input bias current cancellation circuit, provide an input
bias current of only 5nA and input offset current of 1nA. Over
the full military temperature range, input bias current and
input offset current for an A-grade device does not exceed
8nA and 3nA, respectively. Input offset voltages are trimmed
to a maximum of 25/N (A/E grades) and 1OOl'V (B/F grades)
using PMI's zener-zapping technique. This low offset eliminates the need for an offset trimpot in most applications.
COMPENSATION FOR GAINS BETWEEN 5 AND 50
The OP-50 can be compensated for inverting gains between
5 and 50 using a series resistor and capacitor. These values
can be adjusted to minimize overshoot for a given application. The recommended compensation is'
Lowvoltage-noise, typically4.5nV/VHZ at 1kHz, isachieved
in the OP-50 with minimum sacrifice of input protection.
Overload protection is provided by input resistors of 2500
and emitter-base diodes. The input resistors provide current
limit protection against differential inputs of up to ±10V; and
the diodes prevent avalanche breakdown which could
degrade the IB' los, and matching of the input stage transistors. External resistors can be added to the input to guard
against higher input voltages; however, the added resistors
will degrade noise voltage performance. When minimum
noise voltage is required, source resistance should be kept
below a few hundred ohms.
GAIN RANGE
RC
5 <; AveL <; 20
20 <; AveL <; 50
AveL 2: 50
56011
3.3kll
47nF
1nF
No compensation reqUired
COMPENSATION
Separate output-stage power supply pins are provided on the
OP-50 to allow control of device power dissipation and output voltage swing. The maximum voltage which may be
applied across the power supply pins is ±18V. The guaranteed specifications are based on operating both stages at
±15V; however, there is minimal effect on DC performance
when the main amplifier is operated at ±15V and the output
stage is operated at a reduced voltage. When operating both
the main amplifier and the output stage at the same voltages,
the corresponding power supply pins may be tied together.
Decoupling capacitors are recommended between the power
supply pins and analog ground. It is necessary to use decoupiing capacitors on each power supply pin when operating
the output stage at supply voltages less than the amplifier
supply voltage. Do not operate the output-stage negative
power supply pin at a more negative voltage than the negative supply pin (V-).
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (Note 2) ........................... ±18V
Internal Power Dissipation (Note 3) .............. 500mW
Input Voltage ............................ Supply Voltage
Differential Input Voltage (Note 4) ................. ±10V
Differential Input Current (Note 4) ............... ±20mA
Output Short-Circuit Duration ................. Indefinite
Storage Temperature Range ............ -65°C to +150°C
Operating Temperature Range
OP-50A, B ........................... -55°C to +125°C
OP-50E, F ..................... , ., ... ,. -25°C to +85°C
Lead Temperature (Soldering, 60 sec) ............. 300°C
DICE Junction Temperature (TJ) •••••••• -65°C to +150°C
A thermally-symmetric die layout, which differs from other
op amp designs by the positioning of more devices along the
center line, provides the OP-50 with a thermal drift of less
than 0.3I'V;CC. This layout feature is critical to the maintenance of high open-loop gain when driving large-current
loads and dissipating hundreds of milliwatts in the device.
The use of a heatsink is recommended to reduce internal
temperature rise when operating at high output power levels.
The use of standard dual-in-line package heatsinks will help
to dissipate heat to the environment. Other techniques, such
as the use of external voltage-dropping resistors, allow heat
to be dissipated outside of the package. See Figure 5, "Driving
500 Loads", in the applications section.
PACKAGE TYPE
14-Pin
Hermetic DIP (Y)
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
106°C
11.3mW/oC
NOTES:
,
Absolute ratings apply to both DICE and packaged parts, unless
2
otherWise noted
Supply voltage rating applies to all power supply pinS No device pins
should be connected to a voltage more negative than the supply
to V-, pin 5
3
4
5-181
See table for maximum ambient temperature ratmg and derating factor
The OP-50's Inputs are protected by 250!! senes resistors and protection
diodes If the differential Input voltage exceeds ±10V, the Input current
must be limited to ±20mA
1/86, Rev. A
II
~
OP-SO HIGH-OUTPUT-CURRENT OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at V+ = +VOP = +15V, V- = -Vop =-15V, TA = 25°C, no compensation, unless otherwise
noted.
OP-50A/E
MAX
TYP
MAX
Vas
10
25
50
100
~V
18
±1
±5
±1
±10
nA
SYMBOL
Input Offset Voltage
Input Bias Current
MIN
OP-508/F
TYP
PARAMETER
CONDITIONS
MIN
01
0.1
UNITS
Input Offset Current
los
Input Voltage Aange
IVA
CMAA:> 100dB
Va
AL:> 50 on
A L :>501l (Note 1)
±13
±25
±134
±40
±13
±25
±13,4
±40
Output Voltage SWing
Va
V+ = +Vop = +5V,
V- = -Vop = -5V
AL = 5001l
AL = 501l
±3.5
±25
±38
±28
±3.5
±25
±38
±28
Slew Rate
SA
AL:> 2kll
Ac= 56011
C c = 47nF
25
30
25
30
V/~s
CMAA
VCM = ±10V
126
140
110
120
dB
PSAA
Vs = ±5V to ±15V
05
~V!V
Ava
Vo =±lOV, RL = 1kll
10
20
75
15
V/~V
AVCL = 50 (Note 2)
15
25
15
25
MHz
±10
±25
±10
±25
mV
Output Voltage SWing
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
Large-Signal
Voltage Gain
Galn~Bandwidth
Product
GBW
Offset Voltage
Aange Adjust
Input NOise Voltage
±12
0.1
Ap=100kll
€np-p
f = 0,1 Hz to 10Hz
012
NOise Voltage Density
eo
f= 10Hz
f = 1kHz (Note 3)
55
4,5
NOise Current
Inp-p
05
No Load
26
3.3
POSitive Current Limit
+lse
Output shorted to Ground
60
95
120
Negative Current limit
-Ise
Output shorted to Ground
60
85
120
55
4.5
Common-Mode
Input Resistance
Capacitive Load
Capability
Settling-Time
jN p _p
85
60
0.3
023
nVljHZ
pAljHZ
26
3,3
mA
60
95
120
mA
60
85
120
mA
Differential-Mode
Input ReSistance
V
pA p. p
ISY
Current
10
V
f = 0 1Hz to 10Hz
i = 100Hz
f = 1kHz
NOise Current Density
V
012
85
60
0.3
0,23
QUiescent Supply
nA
±12
Mfl
RIND
20
R 1NCM
CL
AVCL:> 5
Ac= 56011 (Note 2)
Cc=47nF
t,
Settling to 0,01%, Va = 20Vp_p
A VCL = 500
AVCL = 1000
10
20
10
30
60
Gil
nF
30
60
~s
NOTES:
Guaranteed by current limit tests
2 Guaranteed by deSign
3, Sample tested,
5-182
1/86, Rev. A
-----------l~ OP-50 HIGH-OUTPUT-CURRENT OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at V+ =
+VOP = +15V, V- = -Vop = -15V, -25°C:'O: TA:'O: +85°C, no compensation, unless
otherwise noted.
OP-50E
CONDITIONS
MIN
OP-50F
TYP
MAX
MIN
TYP
MAX
UNITS
20
45
50
150
~V
015
0.3
03
PARAMETER
SYMBOL
Input Offset Voltage
Vas
Input Offset
Voltage Drift
TCVos
Input Bias Current
la
±2
±7
±2
±25
nA
Input Offset Current
los
0.2
2.5
0.2
20
nA
Input Offset
Current Drift
Input Bias
Current Dnft
(Note 1)
~V/'C
pArC
TClos
TCl a
20
50
Input Voltage Range
IVR
CMRR;e 100dB
Output Voltage SWing
Va
RL;e 500!!
±12
±134
±12
±134
V
CMRR
VCM~
120
130
105
120
dB
PSRR
Vs ~ ±5V to ±15V
05
ISY
No Load
28
28
rnA
15
15
V/MV
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
QUiescent Supply
Current
Open-Loop Gam
±115
pArC
±10V
±11.5
V
~
VOUT~
Ava
RL ~
±10V,
(Note 2)
1k!!
1 25
05
1 25
MVIV
ELECTRICAL CHARACTERISTICS atV+=+Vop=+15V,
V-=-Vop =-15V, -55°C:'O:TA :'O:+125°C, no compensation, unless
otherwise noted.
OP-50A
MAX
TYP
MAX
20
55
50
200
015
03
03
Is
±2
±8
±2
±20
nA
los
05
3
05
12
nA
Input Offset Voltage
Vos
Input Offset
Voltage Drift
TCVos
Input Bias Current
Input Offset Current
Current Dnft
Input Bias
Current Dnft
OP-50B
TYP
SYMBOL
MIN
CONDITIONS
MIN
UNITS
MV
MV/'C
pA/'C
Telos
20
TCl a
50
±115
pArC
±115
Input Voltage Range
IVR
CMRR;e fOOdB
Output Voltage Swing
Va
RL;e soon
±12
±132
±12
±132
V
CMRR
VCM~
120
130
105
120
dB
Power Supply
Reiection Ratio
PSRR
Vs ~ ±5V to ±15V
0.5
Quiescent Supply
Current
ISY
No Load
2.8
2.8
rnA
Ava
Vo= ±10V,
(Note 1)
RL = 1kll
10
10
V/MV
Common-Mode
Rejection Ratio
Open-Loop Gain
±10V
1.25
V
0.5
1.25
MVIV
NOTE:
1. Tested at +125'C, guaranteed by design at -55'C.
1/86, Rev. A
5-183
- - - -. .
~~~~-
~
~
~
2. Guaranteed by design
PARAMETER
~
9
NOTES:
TeVos tested on E grade, guaranteed by design on F grade specification
Input Offset
~
......
-~----
-~-
O~
------------l~ OP-50 HIGH-OUTPUT-CURRENT OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
1.
2.
5.
6.
7.
9.
10.
11.
12.
13.
14.
15.
NONINVERTING INPUT
INVERTING INPUT
VOUTPUT
-VOP
V+
+Vop
COMPENSATION
COMPENSATION
NULL
NULL
V- (OPTIONAL BONDING PAD)'
For addilional DICE informalion refer 10
1986 Dala Book, Section 2.
DIE SIZE 0.110 X 0.148 inch, 16,280 sq. mils
(2.79 X 3.76 mm, 10.50 sq. mm)
WAFER TEST LIMITS at V+ = +VOP = +15V, V- = -Vop = -15V, TA = 25°C, no compensation, unless otherwise noted.
OP-SOG
CONDITIONS
PARAMETER
SYMBOL
Input Offset Voltage
Vas
LIMIT
100
~V
Input Bias Current
18
±10
nAMAX
UNITS
MAX
Input Offset Current
los
Output Voltage SWing
Va
RL " soon
Output Voltage SWing
Va
V+ ~ +VoP ~ +5V. VRL ~ soon
RL ~ son
Common-Mode
Rejection Ratio
CMRR
VCM == ±10V
Power Supply
Rejection Ratio
PSRR
Vs ~ ±5V to ±15V
Large-Signal
Voltage Gain
Ava
Va
±10V. RL ~ 1kn
7.5
Positive Current Limit
+Isc
Output shorted to Ground
60
mAMIN
Negative CUrrent LimIt
-I se
Output shorted to Ground
60
mAMIN
QUiescent Supply
Current
ISY
No Load
3.3
mAMAX
nAMAX
~
~
-Vop
~
±13
VMIN
±35
±25
V MIN
110
dBMIN
-5V
~V/V
V/~V
MAX
MIN
NOTE:
Electrical tests are performed at wafer probe to the limIts shown Due to vanatlons In assembly methods and normal Yield loss, Yield after packaging IS not
guaranteed for standard product dice Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing
5-184
1/86, Rev. A
----------11EH!>
OP·50 HIGH·OUTPUT·CURRENT OPERATIONAL AMPLIFIER
TYPICAL ELECTRICAL CHARACTERISTICS at V+ = +Vop= +15V, V-= -Vop= -15V, TA = 25°C, no compensation, unless
otherwise noted.
OP·50G
PARAMETER
SYMBOL
CONDITIONS
Slew Rate
SR
RL ", 2kn
Rc = S60n
C c =47nF
NOise Voltage Density
e,
f= 10Hz
f= 1kHz
Input Noise Voltage
enp-p
i,
NOIse Current Density
TYPICAL
UNITS
V/~s
5.5
4.5
nV/VHZ
f = 0.1Hz to 10Hz
012
jJ.V p_p
f= 10Hz
f = 1kHz
02
0.15
pA/VHZ
--------
AVCL~ 5
Capacitive Load
Capability
CL
nF
10
Rc = S60n
C c =47nF
NOISE TEST CIRCUIT (0.1 TO 10Hz)
O.lpF
100kO
100kn
+15V
2kO
BURN-IN CIRCUIT
OFFSET NULLING CIRCUIT
+18V
V+
10kn
OUTPUT
R,
100
krl
ALL RESISTORS ARE 1% METAL FILM.
V-
5·185
1/86, Rev. A
-------------t1fW
OP-50 HIGH-OUTPUT-CURRENT OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs TEMPERATURE
INPUT BIAS CURRENT
vs SUPPLY VOLTAGE
30
40
30r-----,-----~------~-----,
TA =2SOC
Vs = ±15V
30
20
20
........
-30
~ t-.....
1.0
........
05
.........
- --
f'
-40
-75
-50
-25
25
50
75
100
1.0
I-----+------t----=='T""-"""d
05~----~----_4------+-----~
±s
125
TEMPERATURE 1°C)
±lO
±lS
±20
SLEW RATE vs
TEMPERATURE
__
VOLTAGE (VOLTS)
SLEW RATE vs
TEMPERATURE
50
Vs = ±15V
AVCL '" 20
45
45f---t-+--t---I--+- ~~: ~l;:n
05
40
CC '" 1nF
04
~
/
03
"-
01
2.
......
40 f-__t-+-+---I--++SR
~C =~~~PF
35
."
~ 35~~::~~~~~~~~~~-J
~
J
"
02
-"""1'----
"rR
30f---t-+-+---I--+-~-f-~
V
-SR
'"
30
~
25
~
20
w
~
AV~l
= 10
Vs = ±15V
RC = 560n
Cc=47nF
Rl = lkH
Cl = 1000pF
15
10
25f---t-+-+---I--+-~-f-~
20.L-~
-75
-50
-25
25
50
75
100
125
-75
__~__~~__-L__~__~~
-50
-25
TEMPERATURE (OC)
25
50
150
-75
-50
-25
25
- '"
50
75
100
125
'" 1.5 f-H+++Ittt--++Hfttttt-t+tvlltt---+++t+tffi
110
0:
100
~
t-t+t+Hltt--+++t+tffi--l+f+ttIll-+f-ttHttl
~
120
w
O~~~~~~~~~~~WU
1000
140
~
z
0
130
r--
~
~
\
90
0:
80
1il
90
~
~
70
1
10
lOa
lk
FREQUENCY (Hz)
10k
.....
I\.
'\
lOOk
""-
r'\.
70
60
r"-
60
100
&:
TA = 25°C
Vs'" ±15V
A VCL '" 1000
...........
'" I"
120
;J
0:
UNCOMPENSATED
~
§ 110
80
t-t+t+Hitt-+++t-Hffi--l:+f+ttItt--+f-ttHttl
150
TA = 25°C
VCM = ±lOV '
AVCL = 1000
130
."
10
lOa
CAPACITIVE LOAD (nF)
PSRR vs
FREQUENCY
VSI~I±'5V
140
AVCL'" 10
RL = lkn
RC = 560n
Cc = 47nF
.2Of-+-++++Itff-++HHitlf-t+t+Hltt--+++t+tffi
1
o
125
CMRR vs
FREQUENCY
Vs'" ±1SV
0.1
100
_....
TEMPERATURE (OC)
SLEW RATE vs
CAPACITIVE LOAD
!\
75
-
r¥
05
o
0.5
____
10
COMMON~MODE
06
~
____
-5
SUPPLY VOLTAGE (VOLTS)
INPUT OFFSET CURRENT
vs TEMPERATURE
-. 1.0
____
-10
±25
~
-20
15~----+----__t------+-----~
~
~
~
1.5
"-
~
i""""oo ~
~
i<
........
-10
~
r"""Ioo.
~
10
>
tu
~
e
Vs = ±15V
25~--==~_.~_4------+-----~
25
o
~w
""~
e
INPUT BIAS CURRENT
vs COMMON-MODE VOLTAGE
"
"-
-PSRR
+PSRR
50
1
10
100
1k
10k
lOOk
1M
FREQUENCY (Hz)
NOTE:
The symbol ±Vsis used to indicate the supply voltages when the main amplifier
and the output stage are being operated at the same voltages.
5-186
1/86, Rev. A
-------------l~ OP·50 HIGH·OUTPUT·CURRENT OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
PSRR VB
FREQUENCY
SUPPLY CURRENT
VB TEMPERATURE
SUPPLY CURRENT
vs SUPPLY VOLTAGE
150
COMPENSATED
".:s 130 ~ ~
140
'~"
g
'\
~ 110
i
100
a:
90
~
80
Vs = ±15V
AVCL = 1000
1\. ~
120
Vs'" ±15V
35~-+--~~~~--+--+--4-----l
TA = 25°C
"
'\.
\
i
Cc = lnF
RC=33kil
~
I
::i~
~
">
~
\-PS~R
~
+PSRR\ \
~
70
so
10
1
100
lk
20~_t--+-_t--_r--r-_t--+-_4
1 5 1-_t--+-_t--_r--r-_t--+-_4
100k
-75
1M
-50
25
50
75
100
±5
125
±10
:1:15
±20
±25
CURRENT NOISE DENSITY
VB FREQUENCY
VOLTAGE NOISE DENSITY
VB FREQUENCY
20
...
......
,
80
40
-25
SHORT-CIRCUIT CURRENT
VB TEMPERATURE
~ 100
~
2t---+--+---I----+---1
SUPPLY VOLTAGE (VOLTS)
120
60
~
TEMPERATURE (CC)
ffi
~
~
10t--+--1-~1--t--+_-+--1--1
1.8
~
12
1,4
~
10
I
~
~
.....
-
r--..
~
.......
25
-25
50
75
100
,
1,2
!ll
5
z
ffi
~
\
~ 10
08
04
"
0.2
o
126
TEMPERATURE (OCI
'"
!il
'"~
1\
8
10
6
i'
4
100
1k
10k
o
10
1
FREOUENCY (Hz)
TOTAL HARMONIC
DISTORTION
VB FREQUENCY
"'
AVCL = 1000
VS "'±15V
!:;
o
> 2
~
1
1~~=25'e'
C
!!!
0.6
§
o
-60
16
a:
20
-75
14
TA - 26~~"
Vs· ±15V-
Vs - j:15V
~
a
o~~--~~~~--~~--~~
180
at::
4 t---_t----+-----j----_r------l
ill
a:
FREQUENCY (Hz)
140
i
t<
05t--+--1-~1--t--+_-+--1--1
~
10k
li;;;;;;~;;;~;t;::;;+:~::4::::j
251--+--+_-I--+--+--+--+_---1
30
100
lk
10k
FREQUENCY (Hz)
TOTAL HARMONIC
DISTORTION
VB LOAD RESISTANCE
o TO 1Hz
NOISE VOLTAGE DENSITY
006
Vs· ±15V
TA = 25°C
RL = 5000
t---I-t-1H-+t-ttt---t Vs = ±15V
Vo '" 20Vp _p
AVCl"" 100
~--~HI-++t-ttt---+f '" 1kHz
Vo = 20V p _p
Ave L- 3OO Ave L = 100
Ave L -10 I",\~
Ave L=5,
~
gaol
o
100
,/
o
OH,
""
1k
lH,
800/J.V FULL SCALE
10 O/J.V/DIV VERTICAL
AVCL = 10,000
io"""'" ....-!I::::
FREQUENCY (Hz)
0061--t~~H+t-tt1't--tI---H+t-H+I
10k
~00L---~~~~~1~k--~~~LU~'0k
LOAD RESISTANCE (m
5·187
1/86, Rev. A
II
-----------l~ OP-50 HIGH-OUTPUT-CURRENT OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
GAIN, PHASE SHIFT
vs FREQUENCY
'40
... IIIII
I~Hds~
'20
70
90
60
I'
;;
15
i'o.
80
50
170
20
o
T
AI~I~I~QC
'00
'0
'90
20
210
'0
'Ok
lOOk
'M
'k
'0
-SWING
Vs = ±10V
~
+SW1NG
I='"
w
~
8
~
TA =25°C
6
~
-SWING
::>
1
iSWl'NGI
III'""'"
3
'00
'k
,k
'00
'OM
'Ok
MAXIMUM OUTPUT SWING
vs FREQUENCY
~/II
11111 II
11111 II
I'A~CL =5
ill
II III
30
TA
=2SOC
AVCL = 20
Vs = ±15V
Vs = ±15V
~
TA = 25°C
25
~
AC = 3.3k.l1
Cc = lnF
30
0
::>
C L = 100pF
20
"
AVCL = 20
~
i1
~
15
~
o
~
"
"'"
0'
'Ok
Rl = lkn
w 20
'5
'0
Vs = ±5V
o
TA = 2SOC
8
~ 2.
7
5
1
II
SMALL-SIGNAL OVERSHOOT
vs CAPACITIVE LOAD
35
~
~
5
I
LOAD RESISTANCE In)
40
Z
~
o
V'"+SWING
FREQUENCY (Hz)
45
"
~
10
::>
'M
lOOk
'Ok
50
o
~
Vs = ±15V
'"''''1k
OUTPUT VOLTAGE SWING
vs LOAD RESISTANCE
9
~
~
~
FREQUENCY (Hz)
~
"~ '1
30
TION
-SW'~~
w
150
NO
VS= ±15V
13
~ '2
GAIN
40
14
o
2:.
"
~
40
60
~
z
130
z
"
OUTPUT VOLTAGE SWING
vs LOAD RESISTANCE
110
'00
~
CLOSED-LOOP GAIN
vs FREQUENCY
70
ill1l11illil
IlllL-H'lJlJJ
'0
'00
CAPACITIVE LOAD (nFj
LOAD RESISTANCE (nJ
'0
~
'"~
AVCL '" 1000
1000
0
'00
1\
'k
100k
'Ok
,M
FREQUENCY (Hz)
OUTPUT IMPEDANCE
vs FREQUENCY
'00
TA " 25°C
. ~S
10
i ~'I~V
III
'.0
t=:=IA~C~1 ~ '000
O.
,
"
00
,
000
,
'0
'00
AVe l.·l00
'k
'Ok
lOOk
'M
FREQUENCY (Hz)
5-188
1/86, Rev. A
------------11fMD
OP-50 HIGH-OUTPUT-CURRENT OPERATIONAL AMPLIFIER
overdriving of the long-tailed transistor pair and stop saturation of the output transistor. Power supply voltage is set to
±5V to lower the quiescent power dissipation and minimize
thermal feedback due to output stage dissipation. Operating
from ±5V supplies also reduces the OP-50 rise and fall times
as the output slews over a reduced voltage range. This, in
turn, reduces the output response time
TCVos TEST CIRCUIT
100kfl 1%*
+15V
1001%*
It IS common practice with voltage comparators to ground
one Input terminal and to use a single-ended input. The
historic reason is poor common-mode rejection on the input
stage. In contrast, the OP-50 has very high common-mode
rejection and is capable of detecting microvolt level differences in the presence of large common-mode signals.
-15V
The comparator IS not fast, but It is very sensitive and can
detect signal differences as low as O.3p.V. With large input
overdrives, the circuit responds in approximately 31'S. If
sharp transitions are needed, the use of a TTL Schmit!trigger input is recommended. A table of Response Time vs.
Input Overdrive is shown below.
"VISHAV TYPE S102K RESISTORS
APPLICATIONS INFORMATION
HIGH-SENSITIVITY VOLTAGE COMPARATOR
A comparator capable of resolving a submicrovolt difference
signal is shown in Figure 1. The OP-50, operating without
feedback, drives a second gain stage which generates a TTLcompatible output signal. Schottky-clamp diodes prevent
INPUT OVERDRIVE
Positive Output Delay
Negative Output Delay
100mV
10mV
1mV
100"V
10"V
3.2,,5
1.8,,5
5,,5
5,,5
40,,5
50,,5
340"s
380,,5
2.4ms
4.5ms
. -......- - - -.....- - - -......,....._----o+5V
*,on,
22kfl
*'
10nF
CERAMIC
15kO
2X
1N8263
820.0
10nF
~-+--+-~--_+-----+--oW
'--+-______________-+_____-o_5V
FIGURE 1: HIGH-SENSITIVITY VOLTAGE COMPARATOR
1/86, Rev. A
5-189
--
-------
- -------------------
--
----------I~ OP-50 HIGH-OUTPUT-CURRENT OPERATIONAL AMPLIFIER
INTEGRATOR AND UNITY-GAIN BUFFER
Figure 2 shows a method of obtaining unity-gain in a buffer
configuration. The R1 and C1 network provides input compensation to circumvent the minimum gain requirement
Figure 3 shows the same technique applied in the inverting
mode to form a high precision integrator.
l00kn ±O 1%
lkO ±1%
+15V
10k!l±Ol%
VIN(OIFF)
lkn
[~-,\N'v-_4
...
lOm±Ol%
>''---......~IM,.-..,...-o 'OUT
10M2 ±O 1%
100kn±O 1%
2kn
RourTRIM
HOWLAND CURRENT PUMP
VOLTAGE COMPLIANCE ±11 OV@'OUT=20mA
OUTPUT RESISTANCE, ROUT (AT lOUT = 20mA AND RL .;;;; SOOn) E!!2Mn
STABLE WITH ALL VALUES OF CAPACITIVE LOAD
FIGURE 2: UNITY GAIN BUFFER
FIGURE 4: 20mA CURRENT SOURCE
C
DRIVING 500 LOADS
The OP-50can provide up to SOmA into a500 load and up to
26mA into a 5000 load. The output is stable driving capacitive
loads of up to 10nF.
V,No-......Mr-+---.!..j
Cl
o lJ.lF
660n
FIGURE 3: INTEGRATOR
20m A CURRENT SOURCE
The 20m A current source exploits the high output current
and high linearity capabilities of the OP-50. Five precision
resistors and a trim potentiometer are required in this circuit
configuration, known as the Howland Current Pump. The
trim potentiometer is used to balance the resistive feedback
dividers. This maximizes the current-source output impedance. Compensation is selected for a voltage gain of 10.
Applications that make use of the high output current capability of the OP-50 will cause increased power dissipation in
the amplifier. To reduce internal dissipation in these applications, external voltage dropping resistors can be connected
in series with the output-stage power supply pins. As shown
in Figure 5,1300 resistors can be attached to pin 7 (-Vop) and
to pin 10 (+Vop). To maintain stability and specified performance levels, 0.0471'F decoupling capacitors should be used
as Indicated from pin 7 and pin 10 to ground.
,-------._-o+15V
-IN
>''----",,-0 Va
+IN
Compliance is better than ±11 V at an output current of 20mA
and the trimmed output resistance is typically 2MO with
RL:5 5000. The transfer function is given by:
son
C3
LOAD
'~~n o04L{C4*-:
O.047iJ f
lOUT =
VIN (DIFF) X 10.1
101
Amps
' - - - -.......----o-16V
NOTE
RESISTORS Rl AND R2 REDUCE IC POWER DISSIPATIDN
VIN (DIFF) is the differential input voltage. For the resistor
values shown in Figure 4, the maximum VIN (DIFF) is 200mV.
FIGURE 5: DRIVING 500 LOADS
5-190
1/86, Rev. A
OP-77
NEXT GENERATION OP-07
(ULTRA-LOW OFFSET VOLTAGE OPERATIONAL AMPLIFIER)
Precision Monolithics Inc.
PRELIMINARY
FEATURES
•
•
•
•
•
•
•
•
Low initial Vos drift and rapid stabilization time, combined
with only 50mW power consumption, are significant improvements over previous designs. These characteristics, plus the
exceptional TCVos of 0.3/l-V/oC maximum and the low Vos of
25/l-V maximum, eliminates the need for Vos adjustment and
increases system accuracy over temperature.
Outstanding Gain Linearity
Ultra High Gain ........................ SOOOV/mV Min
Low Vos ................................... 2S/l-V Max
Excellent TCVos ...................... " 0.3/l-V/oC Max
High PSRR ................................ 3/l-V/V Max
High CMRR .............................. 1.0/l-V/V Max
Low Power Consumption .................. 60mW Max
Fits 0 P- 07, 725, 108A/308A, 741 Sockets
PSRR of 3/l-V/V (110dB) and CMRR of 1.0/l-V/V maximum
virtually eliminate errors caused by power supply drifts and
common-mode Signals. This combination of outstanding
characteristics makes the OP-77 ideally suited for highresolution instrumentation and other tight error budget
systems.
ORDERING INFORMATIONt
PACKAGE
HERMETIC
DIP
8-PIN
TO-99
8-PIN
OP77AJ'
OP77EJ
OP77BJ'
OP77FJ
OP77AZ'
OP77EZ
OP77BZ'
OP77FZ
OP77GZ
PLASTIC
DIP
8-PIN
OP77EP
OP77FP
OP77GP
This product is available in five standard grades and three
standard packages: the TO-99 can and the 8-pin mini-dip in
ceramic or epoxy.
OPERATING
TEMPERATURE
RANGE
The OP-77 is a direct or upgrade replacement for the OP-07.
OP-05, 725, or 108A op amps. 741-types can be replaced by
eliminating the Ves adjust pot
MIL
INO
MIL
INO
COM
PIN CONNECTIONS
'For devices processed in total compliance to M IL-STO-883, add /883 after
part number. Consult factory for 883 data sheet.
tAil commercial and industrial temperature range parts are available with
burn-in, For ordering information see 1986 Data Book, Section 2
Vas
GENERAL DESCRIPTION
TRIEM":R~:
vas
-IN 2
The OP-77 significantly advances the state-of-the-art in
precision op amps. The OP-77's outstanding gain of
10,000,000 or more is maintained over the full ±10V output
range. This exceptional gain-linearity eliminates incorrectable system nonlinearities common in previous monolithic
op amps, and provides superior performance in high closedloop-gain applications.
+IN 3
60Ul
5 N,C.
4 V- (CASEI
TO-99 (J-Suffix)
EPOXY MINI-DIP (P-Suffix)
8-PIN HERMETIC DIP
(Z-Suffix)
SIMPLIFIED SCHEMATIC
V+07----~----------~----------~------~--~----~~----~------~~~~--_.
R7
*NOTE
R2A AND R2B ARE
ELECTRONICALLY
ADJUSTED ON CHIP
AT FACTORY
NONINVERTING
INPUT
INVERTING
INPUT
4
v-o---~----------------------~--~----~---+--------~~-+--~
This preliminary product information Is based on testing of a limited number of devices. Final specilicatlons may vary. Please contact local sales
ollice or distributor for final data sheet.
5-191
1/86, Rev. A
-----------I~ OP-77 NEXT GENERATION OP-07 - PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
(Note 2)
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
Supply Voltage •••••••••••••••••••••••••••••••••••• ±22V
Internal Power Dissipation (Note 1) ••••••••••••••• 500mW
Differential Input Voltage ••••••••••••••••••••••••• , ±30V
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
Input Voltage (Note 3) •••••••••••••••••••••••••••.• ±22V
Output Short-Circuit Duration •••••••••••••••••• Indefinite
PACKAGE TYPE
Storage Temperature Range
J and
Z Packages
•••••••••••••••••••• -65° C to + 150° C
P Package ••••••••••••••••••••••••••• -65° C to + 125° C
Operating Temperature Range
OP-77A, OP-77B ••••••••••••••••••••• -55°C to +125°C
OP-77E, OP-77F •••••••••••••••••••••• -25° C to +85° C
OP-77G •••••••••••••••••••••••••••••••••• O°C to 70°C
Lead Temperature Range (Soldering, 60 sec) •••••••• 300° C
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
TO·99 (J)
BO'C
7.1mW/'C
B-Pin Hermetic DIP (Z)
75'C
6.7mW/'C
B-Pin Plastic DIP (P)
36'C
5.6mW/'C
2.
Absolute maximum ratings apply to both packaged parts and DICE, unless
3.
otherwise noted.
For supply voltages less than ±22V, the absolute maximum input voltage is
equal to the supply voltage.
DICE Junction Temperature (Tj) •••••••• -65° C to + 150° C
ELECTRICAL CHARACTERISTICS
at Vs
PARAMETER
SYMBOL
CONDITIONS
I nput Offset Voltage
Vas
Long-Term Input Offset
Voltage Stability
aVos/Time
= ±15V, TA = 25°C, unless otherwise noted.
OP-77A
Input Offset CUrrent
los
Input Bias Current
I.
Input Noise Voltage
8 np _p
Input Noise Voltage Density
Input Noise Current
MIN
(Note 1)
OP-77B
TYP
MAX
10
25
0.2
1.5
1.2
2.0
O.IHz to 10Hz (Note 2)
0.35
en
fa = 10Hz (Note 2)
fa = 100Hz (Note 2)
fa = 1000Hz (Note 2)
10.3
10.0
9.6
i np_p
O.IHz to 10Hz (Note 2)
Input NOise Current Density
In
fa = 10Hz (Note 2)
fa = 100Hz (Note 2)
fa = 1000Hz (Note 2)
Input Resistance Differential-Mode
R'N
(Note 3)
Input ResistanceCommon-Mode
R'NCM
Input Voltage Range
IVR
Common-Mode Rejection Ratio
CMRR
VCM = ±13V
Power Supply Rejection Ratio
PSRR
Vs = ±3V to ±18V
Large-Signal Voltage Gain
Ava
R l ,,2kll, Vo=±10V
Output Voltage Swing
Va
Rl " 10kll
Rl " 2kll
Rl "lkll
Slew Rate
SR
Rl " 2kll (Note 2)
Closed-Loop Bandwidth
BW
Avel =
Open-Loop Output Resistance
Ro
Vo=O,lo=O
60
Pd
Vs = ±15V, No Load
Vs = ±3V, No Load
50
3.5
Rp = 20kll
±3
Offset Adjustment Range
-02
26
NOTES:
1. Long-Term Input Offset Voltage Stability refers to the averaged trend line of
Vas vs Time over extended periods after the first 30 days of operation
ExcludIng the initIal hour of operation, changes in Vas dunng the first 30
operatrng days are tYPically 2.5~V
60
UNITS
~V
~V/Mo
2.B
1.2
2.B
nA
0.6
0.35
0.6
~Vp.p
lB.O
13.0
11.0
10.3
10.0
9.6
lB.O
13.0
11.0
nV/JHZ
nA
14
30
14
30
pA p_p
0.32
0.14
0.12
O.BO
0.23
0.17
0.32
0.14
0.12
O.BO
0.23
0.17
pA/JHZ
45
±14
0.1
18.5
45
Mil
200
Gil
±13
±14
1.0
1.0
+ 1 (Note 2)
MAX
20
0.1
-0.2
200
±13
TYP
0.2
0.1
Power Consumption
MIN
V
0.1
1.6
1.0
3
~VIV
~VIV
5000
12000
2000
BOOO
VlmV
±13.5
±12.5
±12.0
±14.0
±13.0
±125
±13.5
±12.5
±12.0
±14.0
±13.0
±12.5
V
0.1
0.3
0.1
0.3
V/~s
0.4
0.6
0.4
0.6
MHz
60
60
4.5
50
3.5
±3
Il
60
4.5
mW
mV
2. Sample tested.
3. Guaranteed by design.
5·192
1/86, Rev. A
------------I1fHD
OP-77 NEXT GENERATION OP-07 - PRELIMINARY
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, -55° C:s TA:S +125°C, unless otherwise noted.
PARAMETER
SYMBOL
Input Offset Voltage
Vas
Average Input Offset
Voltage Drift
TCVos
Input Offset Current
los
Average Input Offset Current
Onft
TClos
Input Bias Current
Ie
Average I nput Bias Current
Drift
TCI B
Input Voltage Range
IVR
Common-Mode Rejection Ratio
CMRR
CONDITIONS
MIN
OP-77A
TYP MAX
(Note 1)
(Note 1)
-02
MIN
60
45
120
~V
01
03
02
06
~V/'C
01
22
01
45
nA
05
25
05
50
pAI'C
(Note 1)
-02
25
±13
Power Supply Rejection Ratio
PSRR
Vs = ±3V to ±18V
Large-Signal Voltage Gain
Ava
RL ,,2kll, Vo =±10V
Output Voltage Swing
Va
RL " 2kll
Power Consumption
Pd
Vs = ±15V, No Load
UNITS
25
24
01
24
nA
15
±135
VCM = ±13V
OP-77B
TYP MAX
±13
10
35
pA/'C
±135
V
0.1
~VIV
~V!V
2000
6000
1000
4000
V/mV
±12
±125
±12
±12.5
V
60
75
60
75
mW
Sample tested.
Guaranteed by design
TYPICAL LOW-FREQUENCY NOISE TEST CIRCUIT
TYPICAL OFFSET VOLTAGE TEST CIRCUIT
~
......
.....:l
~
1
~
~
~
33k.l1
loon
Vo
Vas =
4~~O
r
INPUT REFERRED NOISE =
OUTPUT
47J.1.F
v-
OPTIONAL OFFSET NULLING CIRCUIT
-=
(""'10Hz FILTER)
2~~OO
BURN-IN CIRCUIT
100kf2
+1av
>-....- - - - - - o v +
+
T 10J.l.F
\J
1051
7 6
> - ' - - - - - 0 OUTPUT
'C2
* 1 PER BOARD
10,u.F~
-18V
5-193
~
0......
0
loon
=-
INPUT
......
~
25Mn
200kn
50n
~
~
~.....:l
NOTES:
1.
2.
II
1/86, Rev. A
~ OP·77 NEXT GENERATION OP·07 -
PRELIMINARY
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, TA = 25° C, unless otherwise noted.
OP·77E
PARAMETER
SYMBOL
Input Offset Voltage
Vos
Long· Term Vos
Stability
Vos/Tlme
Input Offset Current
los
Input Bias Current
Ie
Input Noise Voltage
e np _p
Input Noise
Voltage Density
MIN
CONDITIONS
(Note 1)
OP·77F/G
TYP
MAX
10
25
MIN
0.3
MAX
UNITS
20
60
/lV
0.4
0.1
1.5
1.2
2.0
O.IHz to 10Hz
(Note 2)
0.35
en
fo= 10Hz
fo = 100Hz (Note 2)
fo= 1000Hz
Input Noise Current
I np_p
O.IHz to 10Hz
(Note 2)
Input Noise
Current DensIty
In
fo= 10Hz
f 0 = 100Hz (Note 2)
fo= 1000Hz
Input ResistanceDifferential-Mode
R'N
(Note 3)
-0.2
TVP
/lV/Mo
0.1
2.8
nA
1.2
2.8
nA
0.6
0.38
0.65
/lV p_p
10.3
10.0
9.6
18.0
13.0
11.0
10.5
10.2
9.8
20.0
13.5
11.5
nV/VHZ
14
30
15
35
pA p_p
0.32
0.14
0.12
0.80
0.23
0.17
0.35
0.15
0.13
0.90
027
0.18
pAlVHZ
26
45
±13
±14
-0.2
18.5
45
Mil
200
Gil
±13
±14
V
Input ReslstanceCommon-Mode
R 'NCM
Input Voltage Range
IVR
Common-Mode
RejectIon RatIO
CMRR
VCM =±13V
0.1
1.0
0.1
16
/lViV
Power Supply
Rejection Ratio
PSRR
Vs = ±3V to ±18V
1.0
3.0
1.0
3.0
/lVIV
Large-SIgnal
Voltage Gain
Avo
R L 2:2kll,
Vc= ±10V
5000
12000
2000
6000
V/mV
Output Voltage
SWIng
Vo
RL2: lOkI!
RL 2: 2kfl
RL2: Ikll
±13.5
±12.5
±12.0
±14.0
±13.0
±12.5
±13.5
±125
±12.0
±14.0
±13.0
±12.5
V
Slew Rate
200
SR
RL2: 2kfl (Note 2)
0.1
0.3
0.1
0.3
VI/ls
Closed-Loop
Bandwidth
BW
AVCL = +1
(Note 2)
0.4
0.6
0.4
0.6
MHz
Open-Loop Output
Resistance
Ro
Vo=O,lo=O
60
60
II
Power Consumption
Pd
Vs = ±15V, No Load
Vs = ±3V, No Load
50
35
Rp= 20kl!
±3
Offset Adjustment
Range
60
45
50
3.5
±3
60
4.5
mW
mV
NOTES:
1. Long-Term Input Offset Voltage Stability refers to the averaged trend line
of Vos vs. TIme over extended periods after the first 30 days of operation.
Excluding the initIal hour of operation, changes In Vos during the fIrst 30
operating days are typically 2.5/lV.
2. Sample tested
3. Guaranteed by deSIgn.
5·194
1/86, Rev. A
------------I~ OP-77 NEXT GENERATION OP-07 - PRELIMINARY
ELECTRICAL CHARACTERISTICS at Vs
=
±15V, -25°C
~ TA ~
+85°e for OP-77E/F, ooe
~ TA ~
+lOoe for OP-77G,
unless otherwise noted.
PARAMETER
SYMBOL
Inpul Offset Voltage
Vos
Average Input Offset
Voltage Dnft
TCVos
Input Offset Current
los
Average Input Offset
(Note 1)
(Note 1)
TClos
Current Drift
MIN
CONDITIONS
-02
OP-77E
TYP MAX
OP-77F/G
MIN
TYP MAX
UNITS
10
45
20
100
MV
01
03
02
06
MvrC
01
22
01
45
nA
05
85
pArC
24
60
nA
15
60
pArC
0.5
40
24
4.0
-02
Input Bias Current
la
Average Input Bias
Current Drift
TCl a
Input Voltage Range
IVR
Common-Mode
Rejection Ratio
CMRR
VCM~±13V
0.1
10
01
30
MV/V
PSRR
Vs ~ ±3V to ±18V
10
30
10
50
MVIV
Large-Signal
Voltage Gal n
Avo
RL" 2kO
Vo ~ ±10V
Output Voltage
SWing
Vo
RL" 2kO
Power Consumption
Pd
Vs ~ ±15V. No Load
(Note 1)
40
±13.0 ±13.5
±130 ±135
V
Z2
~
Power Supply
Rejection Ratio
2000
6000
1000
4000
±12
±13.0
±12
±130
60
75
60
V/mV
V
75
mW
~
::sp...
~
......:l
~
~
~
OPEN-LOOP GAIN LINEARITY
10M2
OP-77
Vy
TYPICAL
PRECISION OP AMP
Vy
10k!)
.......
0
.......
NOTES:
1. Sample tested.
2. Guaranteed by design.
1M"
~
Vx
l-l0V
.,..
II
OV
l+l0V
V,
AVO"" 650V/mV
RL =2k.\l
NOTES
1 GAIN NOT CONSTANT CAUSES NONLINEAR ERRORS
2 AVO SPEC IS ONLY PART OF THE SOLUTION
3 CHECK YOUR QP AMP PERFORMANCE, ESPECIALLY AT TEMPERATURES
AVO"" 10,CODV/mV
RL '" 2M2
This is the output gain linearity trace for the new OP-77. The
output trace is virtually horizontal at all pOints, assuring
extremely high gain accuracy. The average open-loop gain is
truly impressive - approximately 10,000,000.
Actual open-loop voltage can vary greatly at various output
voltages. All automated testers use end-point testing and
therefore only show the average gain. This causes errors in
high closed-loop gain circuits. Since this is so difficult for
manufacturers to test, you should make your own evaluation.
This simple test Circuit makes it easy. An ideal op amp would
show a horizontal scope trace.
5-195
1/86, Rev. A
0
------------I~ OP-77 NEXT GENERATION OP-07 - PRELIMINARY
DICE CHARACTERISTICS
1.
2.
3.
4.
6.
7.
8.
DIE SIZE 0.100 x 0.061 Inch, 6100 sq. mils
(2.54 X 1.55 mm, 3.935 sq. mm)
BALANCE
INVERTING INPUT
NONINVERTING INPUT
VOUTPUT
V+
BALANCE
For additional DICE Information refer to
1986 Dala Book, Section 2.
WAFER TEST LIMITS at Vs = ± 15V, TA = 25° C for OP-77N/G devices.
OP-77N
OP-77G
LIMIT
LIMIT
UNITS
Vos
40
75
JIoVMAX
Input Offset Current
los
2.0
2.8
nAMAX
Input Bias Current
Is
±2
±2.8
nAMAX
Input Resistance
Differential-Mode
R'N
26
17
MOMIN
Input Voltage Range
IVR
±13
±13
VMIN
16
JIoVIV MAX
3
3
JIoVIV MAX
PARAMETER
SYMBOL
Input Offset Voltage
CONDITIONS
(Notel)
Common-Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
Vs = ±3V to ±18V
Output Voltage Swing
Vo
RL = 10kO
RL =2kO
RL = lkO
±13.5
±12.5
±12.0
±13.5
±12.5
±120
VMIN
Large-Signal
Voltage Gain
Avo
RL =2kO
Vo =±10V
2000
1000
VlmV MIN
±30
±30
V MAX
60
60
mWMAX
Differential Input
Voltage
Power Consumption
Pd
NOTES:
1. Guaranteed by deSign.
Electrical tests are performed at wafer probe to the limits shown. Due to variations In assembly methods and normal Yield loss, Yield after packaging IS not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = +25°C, unless otherwise noted.
OP-77N
OP-77G
TYPICAL
TYPICAL
UNITS
Rs= 500
0.1
0.2
JIoVl'C
Rs = 500, Rp = 20kO
01
0.2
p.VI'C
05
0.5
pArC
RL " 2kn
03
0.3
V/p.s
AVCL = +1
0.6
0.6
MHz
PARAMETER
SYMBOL
CONDITIONS
Average Input Offset
Voltage Drift
TCVos
Nulled Input Offset
Voltage Drift
TCVOSn
Average I n put Offset
Current Drift
TClos
Slew Rate
SR
Closed-Loop
Bandwidth
BW
5-196
1/86, Rev. A
OP-90
LOW-VOLTAGE MICROPOWER
OPERATIONAL AMPLIFIER
Precision M0l101ithics Inc.
ADVANCEPRODUCTINFO~TION
FEATURES
The OP-90 draws only 12j.1A of quiescent supply current. while
able to deliver over SmA of output current to a load. The extremely
low input offset voltage of less than 50j.1V virtually eliminates any
need for external Vas nulling. It has an open-loop gain of over 2
million. a CMRR above 110dB, and a PSRR that IS under 10j.1VN.
The OP-90 features a noise voltage density of 35nV/,j'RZ at
30Hz, a very low value in comparison to other micropower
opamps.
• Single/Dual Supply Operation .•.•...• + 1.6V to + 36V
..•..... :!:O.8V to:!: l8V
• Input and Output Swing to Ground in Single
Supply Operation
• Low Supply Current .•••..•.....•...•••.• l8j.1A Max
• High Output Drive .•..•...•.•••.••••.••••. SmA Min
• Low Input Offset Voltage •.•..•.•••.•••••• SOj.1V Max
• High Open-Loop Gain .••....•..•...• 2000VlmV Min
With its low offset voltage and high gain, the OP-90 brings
preCision performance to micropower applications. The low
supply voltage requirements of the OP-90 combined with its
minimal power consumption enables it to be powered by batteries
or solar cells and is ideal for applications in portable Instruments,
remote sensors, and satellites.
ORDERING INFORMATIONt
PACKAGE
TA = 2S·C
VosMax
(j.1V)
HERMETIC
DIP
8-PIN
50
50
100
100
OP90AZ*
OP90EZ
OP90BZ*
OP90FZ
PLASTIC
DIP
8-PIN
OPERATING
TEMPERATURE
RANGE
OP90EP
OP90FP
PIN CONNECTIONS
MIL
INO
MIL
INO
• For deVices processed In total compliance to MIL·STD-883. add 1883 after part
number Consult factory for 883 data sheet
t All commercial and Industnal temperature range parts are available with burn-In
For ordering Information see 1986 Data Book. Section 2.
GENERAL DESCRIPTION
8-PIN HERMETIC DIP
(Z-Sufflx)
The OP-90 is a high-performance micropower op amp operable
from a single supply of + 1.6V to +36V or from dual supplies of
:!:O.SV to :!:1SV. Input voltage range extends to the negative rail
allowing the OP-90 to accommodate input signals down to zero
volts in single supply operation. The OP-90's output will swing to
ground when operating from a single supply. enabling "zero inzero out" operation.
ELECTRICAL CHARACTERISTICS at Vs
PARAMETER
Input Oftset
Voltage
Input Oftset
Current
SYMSOL
Vos
CONDITIONS
Vs~
8-PIN EPOXY MINI-DIP
(P-Suffix)
= :!:15V, TA = 25°C, unless otherwise noted.
OP-90A/E
MIN TYP MAX
±15V
OP-90B
MIN TYP
150
50
v+ ~ +5V,V-~-5V
18
Input NOise
Vo~age DenSity
10
en
fo~30Hz
Input Voltage
Range
IVR
Vs = ±15V
V+ = +5V. V-~OV
Common-Mode
Rejection RatiO
CMRR
VCM~
Power Supply
Rejection RatiO
PSRR
Vs ~ ±1Vto ±15V
±14V
OP-90F
MIN TYP
MAX
UNITS
250
100
ILV
2
25
nA
15
20
nA
250
100
los
InputSlas
Current
MAX
35
40
35
nV/$z
-15/+14.2
0/+42
-15/+140
0/+40
-15/+140
0/+40
V
110
107
104
dB
10
15
15
ILVN
This advance product Informat/on describes a product In development at the time of this printing. Finalspecllications may vary. Please contact
local sales ollice or distributor for IInal data sheet.
5-197
._--- -
-~~~~~
~~~-
1/86, Rev. A
~
OP-90 LOW-VOLTAGE MICROPOWER OPERATIONAL AMPLIFIER - ADVANCE INFORMATION
ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = 25°C, unless otherwise noted. (Continued)
OP-90B
OP-90A/E
PARAMETER
SYMBOL CONDITIONS
Large,Slgnal
Voltage Gain
Ava
RL ,,100kil
Output Voltage
SWing
Va
RL ,,100kil
Gain Bandwidth
Product
GBW
Supply Current
ISY
Slew Rate
SR
MIN
Vs~
V+
~
±15V
+5V, V-~ OV
TYP
MAX
MIN
TYP
OP-90F
MAX
MIN
TYP
MAX
UNITS
2000
1000
1000
V/mV
±142
0/+42
±140
0/+40
±140
0/+40
V
25
No Load
25
18
8
5-198
18
8
kHz
25
20
8
!LA
V/ms
1/86, Rev. A
OP-207
DUAL ULTRA-LOW Vas
MATCHED OPERATIONAL AMPLIFIER
PreCiSion MOf)ohthlcs Inc.
FEATURES
•
•
•
•
•
•
•
•
parameters is provided between the channels of this dual
operational amplifier.
Low VOS ....................•••••......... 100~V Max
Offlet Voltage Match ....•.•...•..........•. 90~V Max
Offsat Voltage Match VI. Temp•.•....•.. 1.0~V/oC Max
Common-Mode Rejection Match ..........• 103dB Min
Blal Current Match ....................... 3.SnA Max
Low Noise .............................. O.8~Vp_p Max
Low Blal Current ......................... 3.0nA Max
High Channel Separation ........••. . . . . . .• 126dB Min
The excellent specifications of the individual amplifiers
combined with the tight matching and temperature tracking
between channels provide high performance in instrumentation amplifier designs. The individual amplifiers feature
very low input offset voltage, low offset voltage drift, low
noise voltage, and low bias current. Each amplifier is fully
compensated and protected.
Matching between channels is provided on all critical parameters including offset voltage, tracking of offset voltage vs.
temperature, non inverting bias currents, and commonmode rejection.
ORDERING INFORMATIONt
TA=25°C
VosMAX
(!IV)
HERMETIC
DIP
14-PIN
OPERATING
TEMPERATURE
RANGE
100
100
200
200
OP207AY'
OP207EY
OP207BY'
OP207FY
MIL
COM
MIL
COM
PIN CONNECTIONS
NOTES:
1. Device may be operated even
If Insertion IS reversed; this Is
due to Inherent symmetry
of pin locations of amplifiers
A and B.
2 V-IA) and V-IB) are Internally
connected VIS substrate
resistance.
• For devices processed In total compliance to MIL-STD-883, add /883 after
part number. Consult factory for 883 data sheet.
tAli commercial and Indust"al temperature range parts are available with
burn-In. For ordering informallon see 1986 Data Book, Section 2
GENERAL DESCRIPTION
The OP-207 series of dual matched operational amplifiers
consists of two independent OP-07 high performance operational amplifiers in a single 14-pin dual-in-line package.
Exceptionally low offset voltage and tight matching of critical
14-PIN HERMETIC DIP
(V-Suffix)
SIMPLIFIED SCHEMATIC (1/2 OP-207)
v+o-----~--------~----~----~------~--~----~~----~--------~--~---
R9
OUTPUT
Rl0
+IN
-IN D-''M~I----''''----+--'''''------c
v-o---------------~----------
____________
~--~----~--+_------~~--~~
5-199
~~
--~~~
---------------
1/86, Rev. A
II
---------I1fMD
OP-207 DUAL ULTRA-LOW VOS MATCHED OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
Lead Temperature (Soldering, 60 sec) •••••••••••• 300·C
Supply Voltage ••••••••••••••••••••••••••••••••••• ±22V
Internal Power Dissipation (Note 1) •••••••••••••• 500mW
Differential Input Voltage •••••••••••••••••••••••••• ±30V
Input Voltage (Note 2) •••••••••••••••••••••••••••• ±22V
Output Short-Circuit Duration ••••••••••••••••• Indefinite
Storage Temperature Range ••••••••••• -65·C to +150·C
Operating Temperature Range
OP-207A,OP-207B ••••••••••••••••• -55·C to +125·C
OP-207E, OP-207F ••••••••••••••••••••• O· C to + 70· C
NOTES:
1. See table for maximum ambient temperature rating and derating lactor.
MATCHING CHARACTERISTICS at Vs = ±
15V, TA
PACKAGE TYPE
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
106°C
1'.3mW/oC
14-Pln Hermetic DIP
2. For supply voltages less than ±22V, the absolute maximum Input voltage Is
equal to the supply voltage.
= 25· C, unless otherwise noted.
OP-207A1E
PARAMETER
SYMBOL
CONDITIONS
Input Offset VOltage Match
AVos
Rs=loo0
Average Nonlnvertlng
Bias Current
le+
MIN
OP-207B/F
TYP
MAX
TYP
MAX
30
90
50
280
"V
±1.5
±3.5
±1.5
±6.0
nA
MIN
UNITS
Nonlnverting Ollset Current
los+
±0.7
±3.5
±1.0
±6.0
nA
Inverting OllS9t Current
los-
±0.7
±3.5
+1.0
±6.0
nA
Common-Mode Rejection
Ratio Match
ACMRR
VcM =±13V
Power Supply Rejection
Ratio Match
APSRR
Vs = ±3V to ±18V
103
96
32
Channel Separation
126
MATCHING CHARACTERISTICS at Vs =
120
140
114
dB
10
126
51
140
"VIV
dB
± 15V, -55· C :5 TA:5 125· C, unless otherwise noted.
OP-207A
OP-207B
TVP
MAX
TVP
MAX
UNITS
Rs= 1000
70
180
180
450
"V
(Note 1)
Rp=20kO (Note I)
0.5
0.3
1.0
1.0
0.9
0.4
1.5
1.3
"vrc
±6
±3
±12
nA
PARAMETER
SYMBOL
CONDITIONS
Input Ollset Voltage Match
AVos
Input Ollset Voltage
Tracking
WIthout External Trom
With External Trim
TCAVos
TCAVosn
MIN
Average Nonlnvertlng
Bias Current
le+
±2
Average Drift 01 Noninverting Bias Current
TCl e+
10
Nonlnverting Ollset
Current
los+
Average Drift of NonInverting Ollset
Current
TCl os+
2
MIN
12
6.5
3
12
2
Inverting Offset Current
los-
Common-Mode Rejection
Ratio Match
ACMRR
VcM =±13V
Power Supply Rejection
Ratio Match
APSRR
Vs = ±3V to ±18V
100
12
6.5
3
94
51
12
114
16
nA
pAloC
15
117
10
pArC
nA
dB
100
"VIV
NOTE:
1. Sample tested.
5-200
1/86, Rev. A
---------tlfMD
OP-207 DUAL ULTRA-LOW VOS MATCHED OPERATIONAL AMPLIFIER
MATCHING CHARACTERISTICS at VS= ±15V, D·C S TAS 7D·C, unless otherwise noted.
OP-207E
PARAMETER
MAX
TYP
MAX
UNITS
I!.vos
Rs= 1000
80
150
120
350
p.V
TC.l.Vos
TC.l.VoSn
(Note 1)
Rp = 20kO (Note 1)
0.5
0.3
1.0
1.0
0.9
0.4
1.5
1.3
p'vrc
±2
±5
±3
±10
nA
CONDITIONS
Input Offset Voltage Match
Input Offset Voltage
Tracking
Without External Tri m
With External Trim
Average Noninverting
Bias Current
le+
Average Drift of Noninverting Bias Current
TCl e+
Noninverting Offset
Current
los+
Average Drift of NonInverting Offset
Current
TClos+
MIN
OP-207F
TVP
SYMBOL
Inverting Ollsst Current
los-
Common-Mode Rejection
Ratio Match
.l.CMRR
VcM =±13V
Power Supply Rejection
Ratio Match
.l.PSRR
Vs =±3Vto±18V
MIN
10
12
2
3
12
15
5
100
3
117
10
94
pArC
10
pA/'C
10
114
51
16
nA
nA
dB
100
p.VIV
NOTE:
1. Sample tested.
~
~
~
~
Po<
~
~
-~
0
OFFSET NULLING CIRCUIT
BURN-IN CIRCUIT
~
~
2
3
>--+"'-----oN c
4
+18V
1
20k!!
14
-')..
;r
SIDE
IN PUT
~
v+
13
OUT (A)
12
v-
5
v-
OP-207
-18V
11
11
>--I"-----oN c
IN PUT
10
10
~
_.;,.9
•
~-
-
5-201
6
OUT (B)
7
20kH
V+
1/86, Rev. A
IfMD
OP-207 DUAL ULTRA-LOW VOS MATCHED OPERATIONAL AMPLIFIER
INDIVIDUAL AMPLIFIER CHARACTERISTICS at Vs = ±15V, TA = 25°C, unless otherwise noted.
OP-207A1E
MAX
TYP
MAX
UNITS
Rs= 1000
35
100
60
200
p.V
(Note 1)
0.3
I.S
0.4
2.0
p.VlMo
nA
SYMBOL
CONDITIONS
Input Ollset Voltage
Vas
Input Ollset Voltage
StabIlity
<1VosfTlme
MIN
OP-207B/F
TYP
PARAMETER
MIN
Input Oflset Current
los
0.9
28
15
60
Input Bias Current
Is
±1
±3
±2
±7
nA
I nput Noise Voltage
8ne:1!
O.IHz to 10Hz (Note 2)
0.35
0.6
0.35
0.6
p.Vp-p
Input Noise Voltage
Density
en
fa = 10Hz (Note 2)
fa = 100Hz (Note 2)
10 = 1000Hz (Note 2)
10.3
100
9.6
18.0
130
10.3
10.0
9.6
18.0
13.0
nV/y"Hz"
Input Noise Current
Inf!.E!
O.IHz to 10Hz (Note 2)
Input Noise Current
Density
in
fa = 10Hz (Note 2)
fo= 100Hz (Note 2)
fo= 1000Hz (Note 2)
I nput Resistance Differential Mode
R'N
(Note 3)
Input Resistanca Common-Mode
R,NC...
20
14
30
14
30
pAp_~
0.32
0.14
0.12
0.80
0.23
032
0.14
0.12
0.80
0.23
pNy"Hz"
60
8
200
30
MO
120
GO
±13
±14
:1'13'
±14
V
106
123
100
120
dB
Input Voltage Range
IVR
Common-Mode
Rejecloon Ratio
CMRR
Vc ... = ±13V
Power Supply Rejection
Ratio
PSRR
Vs= ±3V to ±18V
Large-Signal Voltage
Gain
Avo
RL2: 2kO, Vo = ±10V
Output Voltage Swing
Va
RL2: 10kO
RL2: 2kO
R L 2:1kO
Slew Rate
SR
RL 2:2kO
Closed-Loop Bandwidth
BW
AvCL =+1
Open-Loop Output
Resistance
Ro
Vo=O,lo=O
Power Consumption
Pd
No Load, Both AmplifIers
180
Rp= 20kO
±4
±4
mV
8
8
pF
Offset Adjustment Range
I nput Capacitance
20
C 'N
32
p.VN
200
500
150
400
VlmV
±12.S
±120
±100
±13.0
±128
±120
±12.S
±120
±10.0
±13.0
±128
±120
V
02
02
VII's
06
0.6
MHz
80
60
0
240
200
300
mW
NOTES:
Long-Term Input Offset Voltage StabIlity refers to the averaged trend line
of Vos vs Tome over extended periods alter the fIrst 30 days of operatIon
ExcludIng the Initial hour of operatIon, changes on Vos dUring the fIrst 30
operatIng days are tYPIcally 2 Sp.V Parameter IS sample tested
2. Sample tested
3 Guaranteed by deSIgn
5-202
1/86, Rev. A
~ OP-207 DUAL ULTRA-LOW VOS MATCHED OPERATIONAL AMPLIFIER
INDIVIDUAL AMPLIFIER CHARACTERISTICS at Vs = ±15V, -55· C:5 TA:5 125· C, unless otherwise noted.
OP-207A
MAX
TVP
MAX
UNITS
Rs= lOOn
75
230
100
400
p.V
Rp=20kll (Notes 1, 21
04
04
13
07
07
1.8
18
56
30
120
SVMBOL
CONDITIONS
Input Ollset Voltage
Vos
Average Input Ollset
Voltage Drift
WIthout External Trim
With External Trim
TCVos
TCVOsn
Input OIIset Current
los
Average Input Ollset
Current Drift
TClos
MIN
OP-207B
TVP
PARAMETER
MIN
10
Input BIas Current
I.
Average Input BIas
Current Drift
TCI.
Input Voltage Range
IVR
Common-Mode
Relection Ratio
CMRR
VcM =±13V
Power Supply
RejectIon RatIo
PSRR
Vs = ±3V to ±18V
Large-Signal Voltage
Gain
Ava
RL "'2kn. Vo =±10V
Output Voltage Swing
Va
RL ",2kn
12
±30
±5.6
±40
12
p.V/'C
nA
pAl'C
±140
nA
18
pA/'C
±13
±135
±13
±135
V
103
120
97
117
dB
~
~
......
~
32
10
51
p.VIV
150
400
120
350
VlmV
±120
±12.8
±12.0
±12.8
V
OP-207E
SYMBOL
MIN
CONDITIONS
TVP
OP-207F
MAX
MIN
TVP
MAX
Input OIIset Voltage
Vas
Rs= 100n
60
200
90
350
Average Input Offset
Voltage Drift
WIthout External Trim
WIth External Trim
TCVos
TCVOSn
Rp = 20kn (Notes 1, 21
04
04
13
07
07
1.8
14
5
25
10
Input Ollset Current
los
Average Input Ollset
Current Drift
TClos
Input Bias Current
I.
Average Input Bias
10
±2
±3
12
TCI.
Current Drift
12
±5
Input Voltage Range
IVR
Common-Mode
RejectIon Ratio
CMRR
VcM =±13V
Power Supply
RejectIon Ratio
PSRR
Vs = ±3V to ±18V
Large-Signal Voltage
Gain
Ava
RL ",2kn, Vo =±10V
Output Voltage Swing
Va
RL ", 2kn
UNITS
p.V
p.V/'C
nA
pAl'C
±11
18
nA
pAl'C
±13
±135
±13
±135
V
103
120
97
117
dB
7
32
10
51
p.VIV
150
400
120
350
VlmV
±120
±128
±120
±12.8
V
NOTES:
1. Exclude first hour of operation to allow for stabilization of external
CircUitry.
2. Sample tested
5-203
-------- --- - - - - -
~...:l
~
0
......
INDIVIDUAL AMPLIFIER CHARACTERISTICS at Vs = ±15V, Q·C:5 TA:5 7Q·C, unless otherwise noted.
PARAMETER
::s
p..
1/86, Rev. A
~
~
C5
---------I~ OP-207 DUAL ULTRA-LOW VOS MATCHED OPERATIONAL AMPLIFIER
APPLICATION OF DUAL MATCHED OPERATIONAL
AMPLIFIERS
ADVANTAGES OF DUAL MATCHED OPERATIONAL
AMPLIFIERS
Dual matched operational amplifiers provide a powerful tool
for the solution of some difficult circuit design problems.
Circuits include true instrumentation amplifiers, extremely
low drift, high common-mode rejection DC amplifiers, low
DC drift active filters, dual tracking voltage references, and
many other demanding applications. These designs all
require good matching between two operational amplifiers.
The circuit below, a differential-in, differential-out amplifier,
shows how errors can be reduced. Assuming the resistors
used are matched, the gain of each side will be identical; if the
offset voltage of each amplifier is matched, then the net
differential voltage at the amplifiers output will be zero. Note
that the output offset error of this amplifier is not a function of
the offset voltage of the individual amplifiers, but only a
function of the difference between the amplifiers' offset
voltages. This error-cancellation principle holds fora number
of input-referred error parameters - offset voltage, offset
voltage drift, inverting and noninverting bias currents,
R3
r20kn
~p--ov,
,
2
R,
~
3
'3
V
OP-207
"
R2
'0
~
V
POWER SUPPLIES
The V+ supply terminals are completely independent and
may be powered by separate supplies if desired. However,
this approach would sacrifice the advantages of the powersupply-rejection-ratio matching. The V- supply terminals are
both connected to the common substrate and must be tied to
the same voltage.
OFFSET TRIMMING
Offset voltage trimming is provided for each amplifier.
Guaranteed performance over temperature is obtained by trimming one side (side A) to match the offset of the other. A net
differential offset of zero results. This procedure is used
during factory testing of the devices. The same results are
obtained by trimming side S to match side A or by nulling
each side individually.
The OP-207 is designed to provide best drift performance
when trimmed with a 20kO potentiometer; this value provides
about ±4mV of adj ustment range which is adequate for most
applications. Trimming resolution can be increased by use of
the circuit shown below.
- .....
510:---
4
IN PUT
*
'4
common-mode and power supply rejection ratios. Note also
that the impedances of each input, both common-mode and
differential-mode, are extremely high, an important feature
not possible with single operational amplifier circuits.
Common-mode rejection can be made exceptionally high;
this is very important in instrumentation amplifiers where
errors due to large common-mode voltages can be far greater
than errors due to noise or drift with temperature. For example, consider the case of two op amps, each with BOdS
(100I'VIV) CMRR. If the CMRR of one device is +100I'VlV
CMRR and the other is-100I'VlV, then the net CMRR will be
200l'VlV, a 6dS degradation. The matching of CMRR
increases the effective CMRR when used as an instrumentation input stage.
OUTPUT
•
y:.c'___~""".,--_-.:.:.:;N't,LL
---J;...
N't,;:;:LL_ _-",~.,....
R4
5-204
RB
1/86, Rev. A
OP-215
DUAL PRECISION JFET-INPUT
OPERATIONAL AMPLIFIER
Precision Monolithlcs Inc.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Low input offset voltages. low input currents. and low drift are
featured in these high-speed amplifiers.
High Slew Rate .......................... 10V/,..s Min
Fast Settling Time .................. 0.9,..s to 0.1% Typ
Low Input Offset Voltage Drift ........... 10,..V/oC Max
Wide Bandwidth ......................... 3.5MHz Min
Temperature-Compensated Input Bias Currents
Guaranteed Input Bias Current ..... 18nA Max (125° C)
Bias Current Specified Warmed-Up Over Temperature
Low Input Noise Current ........... 0.01pAlv"HZTyp
High Common-Mode Rejection Ratio. . . . . . .. 86dB Min
Pin Compatible With Standard Dual Pinouts
125°C Temperature Tested DICE
Models With MIL-STD-883 Class B Processing Available
On-chip zener-zap trimming is used to achieve 10wVoswhile
a bias-current compensation scheme gives a low input bias
current at elevated temperatures. Thus the OP-215 features
an input bias current of 18nA at 125°C ambient (not junction)
temperature which greatly extends the application usefulness of this device.
Applications include high-speed amplifiers for current output
DACs. active filters. sample-and-hold buffers. and photocell
amplifiers. For additional preCision JFET op amps. see the
OP-15/16/17 data sheet.
PIN CONNECTIONS
ORDERING INFORMATIONt
PACKAGE
TA = 2SoC
VosMAX
(mV)
TO-99
a-PIN
1.0
1.0
2.0
2.0
4.0
6.0
OP215AJ'
OP215EJ
OP215BJ'
OP215FJ
OP215CJ'
OP215GJ
v+
HERMETIC HERMETIC OPERATING
DIP
TEMPERATURE
DIP
a-PIN
14-PIN
RANGE
OP215AZ'
OP215EZ
OP215BZ'
OP215FZ
OP215CZ'
OP215GZ
OP215AY'
OP215EY
OP215BY'
OP215FY
OP215CY'
OP215GY
8
OUT (AI@_++_70UT(B)
MIL
COM
MIL
COM
MIL
COM
-IN (A) 2
6 -IN (BI
+IN (A) 3
5 +IN (81
4
v-
TO-99
(J-Suffix)
• For deVices processed In total compliance to MIL-STD-883, add /883 after
part number Consult factory for 883 data sheet
tAli commerCial and industrial temperature range parts are available with
burn-In For ordering information see 1986 Data Book, Section 2
14-PIN HERMETIC DIP
(V-Suffix)
'V+ IAI & v+ I BIINTERNALLY CONNECTED
GENERAL DESCRIPTION
The OP-215 offers the proven JFET-input performance advantages of high speed and low input bias current with the
tracking and convenience advantages of a dual op-amp
configuration.
8-PIN HERMETIC DIP
(Z-Suffix)
SIMPLIFIED SCHEMATIC (1/2 OP-21S)
v+
NONINV
INPUT+
r----+---~--O OUTPUT
Al0
'--+----.. Q12
A12
v-o--~~~~-----~--+-+---
__~-+---~---+-+----+-~-~
S·20S
1/86, Rev. A
----------I~ OP-215 DUAL PRECISION JFET-INPUT OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
(Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply
voltage.)
Output Short-Circuit Duration ••••••••••••••••• Indefinite
Storage Temperature Range •••••.•••• -65·C to +150·C
Lead Temperature (Soldering, 60 sec) •••••••••••• 300·C
DICE Junction Temperature (T,) ••••••• -65·C to +150·C
(Note 2)
Supply Voltage
OP-215A, OP-2158, OP-215E, OP-215F
(All DICE except GR) ••••••••••••••••••••••••••• ±22V
OP-215C. OP-215G (GR DICE only) •••.••••.••••• ±18V
Internal Power Dissipation (Note 1) ••••.••••••••• 500mW
Operating Temperature Range
OP-215A, OP-2158, OP-215C •.•••••• -55·C to +125·C
OP-215E, OP-215F. OP-215G •••••.••.••• O·C to +70·C
Maximum Junction Temperature (T,) ••••••••••••• +150·C
Differential Input Voltage
OP-215A, OP-2158,
OP-215E, OP-215F,
NOTES:
I See table for maximum ambient temperature rating and derating factor
PACKAGE TYPE
AI DICE
GR)
+40V
(I
except
•••••• -
(All DICE except
GR
TO-99
+20V
) •••••• -
2
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
Rs= 500
'G'Grade
Input Offset Current
los
Input BIBS Current
18
Input Resistance
R'N
large-Signal Voltage
Gain
Output Voltage
SWing
MIN
OP-21SB/F
TYP
MAX
02
10
MIN
MAX
TYP
MAX
UNITS
08
20
20
2.5
4.0
60
mV
50
100
3
100
200
pA
±200
±400
±15
±18
±300
±600
pA
50
100
T, = 25"C (Note 11
Device Operating
T, = 25"C (Note 1)
±15
Device Operatmg
±18
±100
±300
±15
±18
1012
Ava
150
500
75
220
Va
RL = 10ka
RL =2kO
±12
±11
±13
±127
±12
±13
±12.7
±11
85
60
Slew Rate
SR
AveL =+1
10
18
7.5
18
GBW
(Note 3)
35
57
35
57
CLBW
AveL = +1
13
Settling Time
ts
to001%
to 0 05% (Note 2)
toO 10%
23
11
09
Input Voltage Range
IVR
BandWidth
Common~Mode
Rejection RatiO
Power Supply
RejectIon RatiO
Input NOI.e Voltage
DenSity
Input NOise Current
DenSity
Input Capacitance
MIN
10 12
RL ,,2kO
Vo=±10V
60
OP-21SC/G
TYP
'G' Grade
Closed-Loop
6.7mW'·C
Vs = ± 15V, TA = 25· C, unless otherwise noted.
ISY
Product
7ImW'·C
7S·C
Absolute maximum ratings apply to both packaged parts and DICE. unless
Supply Current
Gain BandWidth
10.OmW'·C
BO·C
otherwise noted
OP-21SAlE
PARAMETER
lOO·C
(J)
B-Pin Hermetic DIP (Z)
OP-215C, OP-215G (GR DICE only) •••••••••••••• ±16V
ELECTRICAL CHARACTERISTICS at
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
14-Pin Hermetic DIP IY)
OP-215C, OP-215G (GR DICE only) ••••••••••••.• ±30V
Input Voltage
OP-215A, OP-2158,
OP-215E, OP-215F,
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
1012
0
50
200
VlmV
±12
±11
±13
±12.7
85
7.0
7.0
V
10.0
12.0
mA
15
VIps
54
MHz
13
12
MHz
2.3
1.1
0.9
24
12
1.0
ps
V
30
+10.2
-102
+148
-11 5
+10.2
-102
+148
-115
+10.1
-10.1
+148
-11.5
86
82
100
100
86
100
100
82
80
96
CMRR
V = ±IVR A, B, C Grades
eM
E, F, G Grades
PSRR
Vs = ±10V to ±18V
Vs= ±10V to ±15V
10
en
fo= 100Hz
fo= 1000Hz
20
15
20
15
20
15
nVl.JHZ
In
fO= 100Hz
fO= 1000Hz
001
001
0.01
001
001
001
pA/.JHZ
3
3
3
pF
C'N
82
51
10
80
16
5-206
dB
96
100
pVN
1/86, Rev. A
IfHD
OP-215 DUAL PRECISION JFET-INPUT OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs = ±15V, -55°C ~ TA ~ +125°C, unless otherwise noted.
OP-215A
PARAMETER
SYMBOL
CONDITIONS
MIN
Input Offset Voltage
Vas
Rs= 50n
TCVos
TCVosn
{Note 31
Rp= 100kn
los
TA = + 125°C, Device Operating
0.8
1.2
TI = +125'C
TA = +125°C, Device Operating
±1.5
±22
OP-2158
TYP
MAX
0.5
2.0
MIN
OP-215C
TYP
MAX
1.5
3.0
MIN
TYP
MAX
UNITS
3.0
60
mV
Average Input Offset
Voltage Dnft
Without External Trim
WIth External Tnm
Input Offset Current
(Note 1)
Input Bias Current
(Note 1)
Input Voltage Range
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
I.
Voltage Gain
Output Voltage
Swing
TI =+125'C
IVR
CMRR
VcM=±IVR
PSRR
Vs = ±10V to ±16V
Vs = ±10V to ±15V
Large-Signal
Ava
Va
10
RL2: 2kn
Vo =±10V
A L =:: 10kO
10
14
±1Q
±18
~VI'C
0.8
12
14
1.0
15
12
22
nA
±15
±2.2
±10
±18
±1.8
±2.7
±15
±28
nA
+102
-102
+14.6
-11.3
+102
-10.2
+146
-113
+101
-101
+14.6
-113
V
82
97
82
97
80
93
dB
10
100
15
100
23
126
~VIV
30
110
30
110
25
100
VlmV
±12
±13
±12
±13
±12
±13
V
CONDITIONS
Input Offset Voltage
Vas
Rs=50n
TCVos
TCVOSn
{Note 31
Rp= 100kn
los
T, = +70°C
TA = + 70° C, Device Operating
MIN
TYP
MAX
0.4
165
MIN
OP-215G
TYP
MAX
14
2.65
MIN
TYP
MAX
UNITS
3.5
8.0
mV
Voltage Drift
With External Trim
Input Offset Current
{Note 11
Input Bias Current
(Note11
I.
Input Voltage Range
IVR
Common-Mode
Rejection Ratio
Power Supply
Rejection RatiO
Output Voltage
SWing
15
TJ = +70'C
TA = +70°C, Device Operating
15
~V/'C
006
0.08
045
080
0.06
0.08
0.45
0.80
0.08
0.10
0.65
1.2
±0.12
±0.16
±0.70
±140
±0.12
±O 16
±0.70
±140
±0.14
±0.19
±1.8
±0.9
nA
nA
+102
-10.2
+14.7
-11.4
+102
-102
+147
-11.4
+10.1
-10 1
+147
-113
V
80
98
80
98
76
94
dB
CMRR
VCM=±IVR
PSRR
Vs = ±10V to ±16V
Vs = ±10V to ±15V
Ava
RL " 2kn
Va = ±10V
50
180
50
180
35
130
V/mV
Va
RL " 10kn
±12
±13
±12
±13
±12
±13
V
Large-Signal
Voltage Gain
~
~
~
0
Average Input Offset
Without External Tnm
~.....:I
0
......
OP-215F
OP-215E
SYMBOL
:::s
~
~
ELECTRICAL CHARACTERISTICS at Vs = ±15V, DOC ~ TA~ +7DoC, unless otherwise noted.
PARAMETER
~
......
....
13
100
13
100
20
NOTES:
1. Input bias current is specified for two different conditions. The TI = 25' C
specification is with the junction at ambient temperature; the Device
Operating specification is with the device operating in a warmed-up
condition at 25° C ambient. The warmed-up bias current value is correlated to the junction temperature value via the curves of lavs. T Jand IBvs.
T A. PMI has a bias current compensation circuit which gives improved
bias current and bias current over temperature vs. standard JFET input op
amps. Is and los are measured at VCM = O.
2.
3.
5-207
159
~VIV
Settling time isdefined here for a unity gain inverter connection using 2kO
resistors. It is the time required for the error voltage (the voltage at the
Inverting input pin on the amplifier) to sellie to within a specified percent of
its final value from the time a 10V step input is applied to the inverter. See
settling time test circuit.
Sample tested.
1/86, Rev. A
---------f1fMD
OP-215 DUAL PRECISION JFET-INPUT OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS (125°C TESTED DICE AVAILABLE)
8.
9.
10.
11.
12.
13.
14.
1. INVERTING INPUT (A)
2. NONINVERTING INPUT (A)
3. NULL(A)
4. V5. NULL(B)
6. NONINVERTING INPUT (B)
7. INVERTING INPUT (B)
NULL (B)
V+
Vo (B)
V+
Vo (A)
V+
NULL (A)
ALL v+ PADS ARE INTERNALLY CONNECTED
DIE SIZEO.059 X 0.093 Inch,5487 sq. mlls(1.50X 2.36 mm,3.54 sq. mm)
For additional DICE Information refer to 1986 Data Book, Section 2.
WAFER TEST LIMITS at Vs= ±15V, TA = 25° C for OP-215N,
OP-215GT devices, unless otherwise noted.
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Input Bias Current
Is
Input Offset Current
los
Large-Signal
Voltage Gain
Avo
Input Voltage Range
IVR
Common-Mode
Rejection Ratio
Rs=500
Vo =±lOV,
RL =2kO
OP-21SNT
LIMIT
OP-215G
OP-21SN
LIMIT
and OP-215GR devices; TA =
125° C
for OP-215NT and
OP-21SGT
LIMIT
OP-21SG
LIMIT
OP-21SGR
LIMIT
UNITS
2
3
2
6
mVMAX
±18
±18
nAMAX
14
14
nAMAX
30
150
30
75
50
VlmVMIN
±10.2
±10.2
±10.2
±10.2
±10.1
VMIN
82
dBMIN
CMRR
VcM=±IVR
82
86
82
86
Power Supply
Rejection Ratio
PSRR
Vs =±lOto±16V
Vs= ±10 to ±15V
100
51
100
60
Output Voltage Swing
Vo
RL = 10kO
RL =2kO
±12
Supply Current
ISY
100
±12
±11
±12
8.5
p.VlV MAX
±12
±11
±12
±11
VMIN
8.5
12.0
mAMAX
NOTES:
For 25° C characteristics of NT & GT devices, see N & G characteristics respectively.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging Is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs =
PARAMETER
Average Input
Offset Voltage Drift
Average Input
Offset Voltage Drift
±15V, TA = +25°C,
unless otherwise noted.
OP-21SNT
TYPICAL
OP-21SN
TYPICAL
OP-21SGT
TYPICAL
OP-21SG
TYPICAL
OP-21SGR
TYPICAL
UNITS
TCVos
Unnulled
Rp= 100kO
2
2
3
3
4
"VI"C
TCVosn
Nulled
Rp= 100kO
0.5
0.5
2
"VloC
pA
SYMBOL CONDITIONS
Input Offset Current
los
Input Bias Current
Is
Slew Rate
SR
AVCL =+1
Settling Time
ts
to 0.01%
to 0.05%
to 0.10%
Gain Bandwidth
Product
GBW
Closed-Loop
Bandwidth
CLBW
Input Noise
Voltage Density
3
3
3
3
3
±15
±15
±15
±15
±15
pA
17
17
16
16
15
VI"s
2.2
1.1
0.9
22
1.1
0.9
2.3
1.1
0.9
2.3
1.1
0.9
2.4
1.2
10
"s
6.0
6.0
5.7
5.7
5.4
MHz
AVCL = +1
14
14
13
13
12
MHz
en
fo= 100Hz
fo= 1000Hz
20
15
20
15
20
15
20
15
20
15
nVl0iZ
Input Noise
Current Density
in
fo= 100Hz
fo= 1000Hz
0.01
0.01
0.01
0.01
0.01
pA/0iZ
Input Capacitance
C
3
pF
'N
3
3
5-208
3
1/86, Rev. A
----------tlfMD
OP-215 DUAL PRECISION JFET-INPUT OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
SETTLING TIME
LARGE-SIGNAL
TRANSIENT RESPONSE
,0r----r--~T7--~----~~~
SMALL-SIGNAL
TRANSIENT RESPONSE
-10~--~--~~--~----~~~
o
SETTLING TIME (ps)
CLOSED-LOOP
BANDWIDTH AND
PHASE SHIFT VI FREQUENCY
,.
18
~
,
14
PHASE MARGIN - 66°C
'\.
12
10
I\.
-
AV>10
f-
,
\
-2
-.
-4
Vs = :!:15V
TA=2S"C
-8
-10
1M
24
130
9
140
t:
~
~
II:
Ei'"
'80
'90
i
~
......
'6
10
~
'2
":ilz ........
10M
o
100M
~0
2
~
"
~
~
""
~
~
"~
24
-,
20
,.
12
\
-25
o
1001<
25
50
75
TEMPERATURE ("Cl
SLEW RATE
~
60
"
40
~
20
VB
100
20
10
100
lk
10k
tOOk
FREQUENCY (Hz)
1M
FREQUENCY (Hz)
1M
10M 100M
COMMON-MODE REJECTION
RATIO VI FREQUENCY
TEMPERATURE
100
lV, = .1,5V
""" \.
Vs = ±15V
r- -..
NEGATIVE
r- ~ -..
TA '" 25"C
~
60
~
~
40
.....
\.
POSITIVE
20
........
"
~
1
125
80
I'
Vs = ±15V
TA;;; 2SoC
r\.
AV"+1
50
1'1..
,
-20
-60
60
8
4
r-
70
VS· :!:15V
TA" 25"C
AV-+ t
I-
60
~
I
i"""-o ~:THAv=+l
PRODUCT
FREQUENCY (Hz)
28
"
CLo,lo-LJ. ._
w
~
II
MAXIMUM OUTPUT SWING
VI FREQUENCY
z
;;:
GAIN BANDWIDTH
AV=+1
100
:!!
.±5V ",VS <±20V IS <5%
20
200
"'\1
Oi
BANDWIDTH VARIATION FROM
ffi
'70
'20
Vs'" ±15V
120
'50
'"",
28
90
'00
110
160
\.
OPEN-LOOP
FREQUENCY RESPONSE
BANDWIDTH vs TEMPERATURE
10
10M
o
-50
-25
26
60
75
AMBIENT TEMPERATURE (OCI
5-209
100
125
o
1
10
100
lk
tOle
tOOk
1M
10M 100M
FREQUENCY (Hz)
1/86, Rev. A
---------l~ OP-215 DUAL PRECISION JFET-INPUT OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE NOISE DENSITY
VI FREQUENCY
OUTPUT IMPEDANCE
vs FREQUENCY
POWER SUPPLY REJECTION
VI FREQUENCY
120
'40
r-
~ 100
90
z
>=
0
~
80
60
g,
50
~
a:
40
~
.:
'1
" "'" ,"-
r-- SUPPLY
NEGATIV~
70
a:
~
VS=I±J,'W
TA = 25°C
110
~
20
o
10
100
lk
10k
1M
100
":Jj
"',"' "'
"'
"'
100k
~
~
~UPPLY
0
80
60
z
w
"~
40
>
20
0
I'..
10
120
~
POSITIvE_
I'...
30
TA = 25°C
~
10M
Tk
lOOk
'Ok
FREQUENCY (Hz)
'M
r~/fCORNER
tiil'illilNCi
I1111111
o
10M
1
FREOUENCY (Hz!
,k
100
'0
I
10k
FREQUENCY (Hz)
BASIC CONNECTIONS
SETTLING TIME TEST CIRCUIT
2k.l1 01%
+15Vo------t-----1---+------,
:OJ
-'2k"'' 0.,..'%......--=-I
0 -.......
0
•
5k"
01%
-15Vo-+--+---,=="""---+-+---,\M-+---"-----0
-OV
OUT
IAI
+IN
-5V
NOTE.
Vas CAN BE TRIMMED WITH POTENTIOMETERS RANGING FROM
10kn TO lMn FDA MOST UNITS Tevos WILL BE MINIMUM WHEN
Vas IS ADJUSTED WITH A 100kn POTENTIOMETER.
(PINOUT FOR "J" AND
"z" PACKAGES ONLY)
("Y" PACKAGE ONLY)
5-210
1/86, Rev. A
------------l~ OP-215 DUAL PRECISION JFET-INPUT OPERATIONAL AMPLIFIER
BASIC CONNECTIONS
APPLICATIONS INFORMATION
DYNAMIC OPERATING CONSIDERATIONS
TYPICAL BURN-IN CIRCUIT
As with most amplifiers, care should be taken with lead dress,
component placement and supply decoupling in order to
ensure stability. For example, resistors from the output to an
input should be placed with the body close to the input to
minimize "pick-up" and maximize the frequency of the
feedback pole by minimizing the capacitance from the input
to ground.
+15V
100kn
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) to
AC ground sets the frequency of the pole. In many instances,
the frequency of this pole is much greater than the expected
3dB frequency of the closed-loop gain and consequently
there is negligible effect on stability margin. However, if the
feedback pole is less than approximately six times the
expected 3dB frequency, a lead capaCitor should be placed
from the output to the negative input of the op amp. The value
of the added capaCitor should be such that the RC time
constant of this capacitor and the resistance it parallels is
greater than, or equal to, the original feedback-pole time
constant.
20051
lOOkS?;
NOTES
1
TA ""125°CTO+150°C
2
RESISTORS ARE TYPE
RN55D, ±1%
-15V
("J" AND .. z" PACKAGES ONLY)
5-211
1/86, Rev. A
OP-220
DUAL MICROPOWER OPERATIONAL AMPLIFIER
(SINGLE OR DUAL SUPPLY)
Precision Monolithics Inc.
FEATURES
Excellent TCVos Match ................. 2p.VfO C Max
Low Input Offset Voltage .................. 150p.V Max
Low Supply Current. . . . . . . . . . . . . . . . . . . . . . . . . .. 100p.A
Single-Supply Operation ................ +5V to +30V
Low Input Offset Voltage Drift ............. O.75p.VfOC
High Open-Loop Gain.. . . . . . . . . . . . . . . . . . .. 2000V/mV
High PSRR ................................... 3p.VIV
Low Input Bias Current. . . . . . . . . . . . . . . . . . . . . . . .. 12nA
Wide Common-Mode Voltage
Range ...................... V- to within 1.5V of V+
• Pin Compatible with 1458, LM158, LM2904
•
•
•
•
•
•
•
•
•
ORDERING INFORMATIONt
offset voltage, and input offset voltage tracking as low as
1.0p.V/o C, make this the first micropower precision dual
operational amplifier.
The excellent specifications of the individual amplifiers combined with the tight matching and temperature tracking
between channels provides high performance in instrumentation amplifier designs. The individual amplifiers feature
extremely low input offset voltage, low offset voltage drift,
low noise voltage, and low bias current. They are fully
compensated and protected.
Matching between channels is provided on all critical
parameters including input offset voltage, tracking of offset
voltage vs. temperature, non-inverting bias currents, and
common-mode rejection ratios.
PACKAGE
TA = 25°C
VosMAX
!IN)
150
150
300
300
750
750
HERMETIC
TO-99
8-PIN
HERMETIC
DIP
8-PIN
OPERATING
TEMPERATURE
RANGE
OP220AJ'
OP220EJ
OP220BJ'
OP220FJ
OP220CJ'
OP220GJ
OP220AZ'
OP220EZ
OP220BZ'
OP220FZ
OP220CZ'
OP220GZ
MIL
INO
MIL
INO
MIL
INO
PIN CONNECTIONS
8 V+
OUT IAI@.70UTIBI
A
- +
B
+ -
-IN (A) 2
6 -IN (B)
+IN (AI 3
,. For devices processed In total compliance to MIL-STO-883, add 1883 after
part number Consult factory for 883 data sheet
t All commercial and industrial temperature range parts are available with
burn-In For ordenng mformatlon see 1986 Data Book, Section 2
5 +IN (B)
4V-
TO-99
(J-Suffix)
8-PIN HERMETIC DIP
(Z-Suffix)
GENERAL DESCRIPTION
The OP-220 is a monolithic dual operational amplifier that
can be used either in single or dual supply operation. The low
SIMPLIFIED SCHEMATIC (Each Amplifier)
r-----~------~----------~--~~--~--~--------~------~--~--~--~V+
OUTPUT
_IN
+IN
0----+------+-----1-------+---'
O---~--~--~--~------~------~-------4~------
__------~-----4~--~--~~V-
*ACCESSIBLE IN CHIP FORM ONLY
5-212
1/86, Rev. A
IfMD
ABSOLUTE MAXIMUM RATINGS
OP-220 DUAL MICROPOWER OPERATIONAL AMPLIFIER
(Note 1)
Supply Voltage •••.•..••••••••••••••••••.•.••••••• ±18V
Power Dissipation •.•••••.•.••.•.••••••••..••.•. 500mW
DICE Junction Temperature (TJ) •••.•••
Differential Input Voltage •••.•••... 30V or Supply Voltage
Input Voltage ••••••• , •••.••.••••••.•••••. Supply Voltage
NOTE:
Lead Temperature (Soldering, 60 sec) ••••••••••••• 300°C
Absolute rallngs apply to both DJCE and packaged parts. unless otherwIse
noted
I
Output Short-Circuit Duration ••..•.••...•..•.. Indefinite
Storage Temperature Range •••.••••.•. -65°C to +150°C
-65°C to +150°C
Operating Temperature Range
OP-220A,
OP-220E,
B, C ••••••••.•.•.•••••••.• -55°C to +125°C
F, G ....................... -25°C to +85°C
ELECTRICAL CHARACTERISTICS
at Vs = ±2.5V to ± 15V, TA = +25° C, unless otherwise noted.
OP-220AlE
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Vs = ±2.5V to ± 15V
Input Offset Current
MIN
OP-220B/F
TYP
MAX
120
MIN
OP-220C/G
TYP
MAX
TVP
MAX
UNITS
150
250
300
500
750
p.V
MIN
II
~
los
VCM=O
015
15
02
2
0.2
3.5
nA
Input BIas Current
I.
VCM=O
12
20
13
25
14
30
nA
~
......
Input Voltage Range
IVR
V+=5V, V-=OV,
Vs= ±15V
V
::l
Po.
Common-Mode
Rejecllon RatIo
CMRR
V+=5V, V-=OV,
OV"VCM,,35V
Vs =±15V,
-15V" VCM " 13 5V
Power Supply
PSRR
Vs =±25Vto±15V
V-= OV. V+ = 5V to 30V
large-SIgnal
Voltage Gain
Avo
V+= 5V, V-= OV, RL = lOOkn
tv" Vo ,,3 5V
Vs = ± 15V, RL = 25kn
Vo=±IOV
Output Vollage
SWing
Vo
Rejection Ratio
V+=5V, V-=OV,
RL = 10kn
Vs = ± 15V. RL = 25kn
0/35
-15/135
0/35
-15/135
0/35
-15/135
90
100
85
90
75
85
95
100
90
95
80
90
3
6
10
18
10
18
32
57
32
57
500
1000
500
800
300
500
1000
2000
1000
2000
800
1600
07/4
07/4
08/4
±14
±14
±14
SR
RL = 25kn, (Note I)
0.05
005
005
AVCL = +1, RL = 25kn
200
200
200
ISY
Vs =.t2 5V, No Load
Vs = ± 15V, No Load
100
140
liS
ISO
liS
170
125
190
125
205
ELECTRICAL CHARACTERISTICS at Vs= ±2,5V to ±15V. -55°C:5 TA:5 +125°C for OP-220A,
-25°C:5 TA:5 +85°C for OP-220 E, F, and G. unless otherwise noted.
OP-220AlE
Average Input Offset TCV
Voltage Drift (Note I )
os
CONDITIONS
Vos
Input Offset Current
los
VCM=O
Inpul BIas Current
I.
VCM=O
Input Voltage Range
IVR
V+=5V, V-=OV,
Vs =±15V
Common-Mode
RejectIon Ratio
CMRR
V+=5V, V-=OV,
OV"VCM "3 2V
Vs =±15V
-15V" VCM " 13.2V
Power Supply
Rejection Ratio
PSRR
MIN
Vs =±15V
Input Offset Voltage
Vs = ±2.5V to ± 15V
V-=OV, V+=5Vt030V
"VIV
~
0......
~
OP-220B/F
TVP
MAX
075
B, and
V/p.s
kHz
135
220
,.A
C,
OP-220C/G
TYP
MAX
IS
12
2
200
300
400
500
1000
1300
p.V
05
2
06
25
08
5
nA
12
25
13
30
14
40
nA
0/32
-15/132
MIN
0/32
-15/132
MIN
TYP
MAX
UNITS
3
p.V/oC
0/3.2
-15/13.2
V
85
90
80
85
70
80
90
95
85
90
75
85
dB
6
10
18
32
5·213
-."--------~~--~
18
32
57
100
57
100
~
~
V
BW
SYMBOL
100
180
V/mV
BandWIdth
PARAMETER
~
dB
Slew Rate
Supply Current
(Both AmplifIers)
~
180
320
p.VIV
1/86, Rev. A
.
_.-
~
---~.-.~
IfMD
OP-220 DUAL MICROPOWER OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs = ±2.5V to ± 15V. -55° C ~ TA ~ + 125° C for OP-220A.
-25°C ~ TA ~ +85° C for OP-220 E, F, and G, unless otherwise noted. (Continued)
OP-220A/E
PARAMETER
SYMBOL
Large-Signal
Voltage Gain
Avo
CONDITIONS
Vs=±15V. RL =50kn
Vo =±10V
V+= 5V. V-= OV.
Output Voltage
SWing
Vo
Supply Current
(Both Amplifiers)
Isv
RL = 20kn
Vs = ± 15V. RL = 50kn
MIN
TYP
500
OP-220B/F
MAX
MIN
1000
500
TYP
e, and C.
OP-220C/G
MAX
800
MIN
400
09/38
0.9/38
1/38
±138
±138
±13.8
135
190
Vs = ±2 5V. No Load
Vs = ±15V. No Load
TYP
170
155
185
250
200
280
MAX
500
UNITS
V/mV
V
170
275
210
330
~A
NOTE: 1 Sample tested
MATCHING CHARACTERISTICS at Vs = ± 15V, TA = 25°C, unless otherwise noted.
OP-220AlE
PARAMETER
SYMBOL
Input Offset
Voltage Match
avos
Average Nonlnvertlng
Bias Current
Nonlnvertlng
Offset Current
CONDITIONS
MIN
OP-220B/F
OP-220C/G
TYP
MAX
300
250
15
TYP
MAX
150
18+
VCM=O
10
20
los+
VCM=O
07
15
180
1M
10k ,ook
SLEW RATE vs
TEMPERATURE
'iii 32 ~VS·±'5V
GAIN
60
o
36
Tl2.le
VS-±1.V-
r\
~
MAXIMUM OUTPUT SWING
VB FREQUENCY
w
'!l
100
!i1
z
ffi
w
~
!;
i'
~ 010
::>
"
001
10
01
10
100
1
1000
1
11
100
1000
FREQUENCY (Hz)
FREQUENCY (Hz)
SMALL-SIGNAL TRANSIENT RESPONSE
LARGE-SIGNAL TRANSIENT RESPONSE
OUTPUT
OUTPUT
r
10kO
'00PF
26.n
5-217
--.~.~---
-----~-
----_.
1/86, Rev. A
------------t[fMD 01'-220 DUAL MICROPOWER OPERATIONAL AMPLIFIER
INSTRUMENTATION AMPLIFIER APPLICATIONS
Of THE OP-220
Dynamic range is limited by Al as well as A2; the output of Al
is:
TWO·OP·AMP CONFIGURATION
The excellent input characteristics of the OP-220 make it
ideal for use in instrumentation amplifier configurations
where low-level differential signals are to be amplified. The
low-noise.low input offsets. low drift. and high gain combined
with excellent CMRR provide the characteristics needed for
high-performance instrumentation amplifiers. In addition.
the power supply current drain is very low.
If the instrumentation amplifier were designed for a gain of 10
and maximum Vd of ± lV. then RN/Ro would need to be four
and Vo would be a maximum of ±10V. Amplifier Al would
have a maximum output of ±5V plus 2VCM. thus a limit of
±10Von the output of Al would imply a limit of±2.5Von VCM.
The circuit of Figure 1 is recommended for applications
where the common-mode input range is relatively low and
differentiai gain will be in the range of 10 to 1000. This twoop-amp instrumentation amplifier features independent
adjustment of common-mode rejection and differential gain.
Input impedance is very high since both inputs are applied to
noninverting op amp inputs.
A nominal value of 100kO for RN is suitable for most applications. A range of 2000 to 25kO for Ro will then provide a gain
range of 10 to 1000. The current through Ro is Vd/RO. so the
amplifiers must supply ±10mV/2000 when the gain is at the
maximum value of 1000 and Vd is at ± 10mV.
Rejecting common-mode inputs is most important in accurately amplifying low-level differential signals. Two factors
determine the CMR of this instrumentation amplifier configuration (assuming infinite gain):
RO
(1) CMRR of the op amps
(2) Matching of the resistor network (RalR4 = R2/R,)
GAIN
r-'IIV'v---"M-.........
R1
AOJ
In this instrumentation amplifier configuration. error due to
CMRR effect is directly proportional to the differential CMRR
of the op amps. Forthe OP-220A/E. this combined CMRR is a
minimum of 9BdB. A combined CMRR value of 100dB and
common-mode input range of ±2.5V indicates a peak inputreferred error of only ±25~V.
R2
Vl
R3
R4
{1121
OP220
VCM + 1/2V d <>'-+--------~
ReSistor matching IS the other factor affecting CMRR.
Defining Ad as the differential gain of the instrumentation
amplifier and assuming that R,. R2. R3 and R4 are approximately equal (RN will be the nominal value). then CMRR will
be approximately Ad divided by 4AR/RN' CMRR at differential gain of 100 would be BBdB with resistor matching of 0.1%.
Trimming R, to make the ratio R3/R4 equal to R2/R, will
directly raise the CMRR until it is limited by linearity and
resistor stability considerations.
Vo
R4[ 1 +2"
1 (R2
R3) + AD
R2+R3J Vd+ii3
R4 (R3
R2) VCM
iii+'R4
Ri- ifi
Vo=R'3
IF Rl· R2· R3· R4, THEN Vo" 2 (1
+i5,) Vd
Figure 1. Two-Op-Amp Instrumentlltlon Amplifier
Configuration
The high open-loop gain of the OP-220 is very important in
achieving high accuracy in the two-op-amp instrumentation
amplifier configuration. Gain error can be approximated by:
The input voltages are represented as a common-mode
input VCM plus a differential input Yd' The ratio R3/R4 is
made equal to the ratio R2/R, to reject the common-mode
input VCM. The differential signal Vd is then amplified according to:
Gain Error -
2 AAdA
0, 02
~1
where Ad is the instrumentation amplifier differential gain
and A02 is the open-loop gain of op amp A2. This analysis
assumes equal values of R,. R2. R3. and R4. For example.
consider an OP-220 with A02 of 700V/mV. If the differential
gain Ad were setto 700. the gain error would be 1/1.001 which
is approximately 0.1%.
Note that gain can be independently varied by adjusting Ro.
From considerations of dynamic range. resistor tempco
matching. and matching of amplifier response. it is generally
best to make R,. R2. R3. and R4 approximately equal. Designating R,. R2. R3. and R4 as RNaliows the output equation to
be further simplified:
Vo=2(1 +
+ .
1 +_d_
A02
Another effect of finite op amp gain is undesired feedthrough
of common-mode input. Defining Ao, as the open-loop gain
of op amp A1. then the common-mode error (CME) at the
output due to this effect will be approximately
CME-
~~)Vd' where RN= R, = R2= R3= R4
5·218
~
1 +Ad
Ao,
Ao,
VCM
1/86, Rev. A
-----------I~ OP-220 DUAL MICROPOWER OPERATIONAL AMPLIFIER
For AdI'Ao,,~1, this simplifies to (2 AdI'A01) xVcM.lftheopamp
gain is 700V/mV, VCM is 2.SV, and Ad is setto 700, then the error
at the output due to this effect will be approximately SmV.
The OP-220 offers a unique combination of excellent dc
performance, wide input range, and low supply current drain
that is particularly attractive for instrumentation amplifier
design.
THREE-OP-AMP CONFIGURATION
A three-op-amp instrumentation amplifier configuration
using the OP-220 and OP-22 is recommended for applications requiring high accuracy over a wide gain range. This
circuit provides excellent CMR over a wide input range. As
with the two-op-amp instrumentation amplifier circuits, tight
matching of the two op amps provides a real boost in performance. The OP-22 is a micropower op-amp featuring
programmable supply current.
A simplified schematic is shown in Figure 2. The input stage
(A 1 and A2) serves to amplify the differential input Vd without
amplifying the common-mode voltage VCM. The output stage
then rejects the common-mode input. With ideal op-amps
and no resistor matching errors, the outputs of each amplifier
will be:
V,
RI
= - (1 +2R'~Vd
- - + VCM
Ro 2
Vo
The differential gain Ad is 1 + 2R,/Roand the common-mode
input VCM is rejected.
VCM + 1I2Vd()..:...---I
R2
V-
This three-op-amp instrumentation amplifier configuration
using an OP-220 at the input and an OP-22 at the output
provides excellent performance over a wide gain range with
very low power consumption. A gain range of 1 to 2000 is
practical and CMR of over 120dB is readily achievable.
Figure 2. Three-Op-Amp Instrumentation Amplifier
Using OP-220 and OP-22
5-219
1/86, Rev. A
OP-221
DUAL LOW-POWER OPERATIONAL AMPLIFIER
(SINGLE OR DUAL SUPPLY)
PrecisIon MOllolithics Inc.
FEATURES
•
•
•
•
•
•
•
•
Excellent TCVos Match .............•... 2p.V/oC Max
Low Input Offset Voltage •................. 150p.V Max
Low Supply Current . . . . . . . . . . . . . . . . . . . . .. 550p.A Max
Single Supply Operation ................ +5V to +30V
Low Input Offset Voltage Drift .......•..... O.75p.VI"C
High Open-Loop Gain ......... . . . . . . .. 1500VlmV Min
High PSRR ................................... 3p.V/V
Wide Common-Mode Voltage
Range ...................... V-to within 1.5V of V+
• Pin Compatible with 1458. LM158. LM2904
ORDERING INFORMATIONt
PACKAGE
TA=25°C
VosMAX
(p.V)
150
150
300
300
500
500
HERMETIC
TO-99
a-PIN
HERMETIC
DIP
a-PIN
OPERATING
TEMPERATURE
RANGE
OP221AJ*
OP221EJ
OP221BJ*
OP221FJ
OP221CJ*
OP221GJ
OP221AZ*
OP221EZ
OP221BZ*
OP221FZ
OP221CZ*
OP221GZ
MIL
INO
MIL
INO
MIL
INO
wide supply voltage range. wide input voltage range, and low
supply current drain of the OP-221 make it well-suited for
operation from batteries or unregulated power supplies.
The excellent specifications of the individual amplifiers combined with the tight matching and temperature tracking
between channels provide high performance in instrumentation amplifier designs. The individual amplifiers feature
very low input offset voltage, low offset voltage drift, low
noise voltage, and low bias current. They are fully compensated and protected.
Matching between channels is provided on all critical
parameters including input offset voltage, tracking of offset
voltage vs. temperature, non-inverting bias currents, and
common-mode rejection.
PIN CONNECTIONS
B V+
.. For devices processed In total complJance to MIL-STD-883, add /883 after
part number Consult factory for 883 data sheet
tAli commerCial and industrial temperature range parts are available With
burn-m For ordering information see 1986 Data Book. SectIOn 2
• v-
TO-99 (J-Suffix)
8-PIN HERMETIC DIP
(Z-Sufflx)
GENERAL DESCRIPTION
The OP-221 is a monolithic dual operational amplifier that
can be used either in single or dual supply operation. The
SIMPLIFIED SCHEMATIC (Each Amplifier)
r-----~------~----------~~-4~--~--~--------~------~--~--~--~V+
-IN
+IN
OUTPUT
0-----+------+-----+-------+---
~--~--~--~--~------~----~~------~~-------+------~----~~--*---~~V*ACCESSIBLE IN CHIP FORM ONLY
5-220
1/86, Rev. A
------------1~ OP-221 DUAL LOW-POWER OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS (Note 2)
Lead Temperature (Soldering, 60 sec.) ............ 300°C
DICE Junction Temperature (TJ) ••••••• -65°C to +150°C
Supply Voltage ................................... ±18V
Power Dissipation (Note 1) ...................... 500mW
Differential Input Voltage .......... 30V or Supply Voltage
Input Voltage ............................ Supply Voltage
Output Short-Circuit Duration ................. Indefinite
Storage Temperature Range ........... -65°C to +150°C
Operating Temperature Range
OP-221A, B, C ...................... -55°Cto+125°C
OP-221E, F, G ....................... -25°C to +85°C
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
PACKAGE TYPE
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
TO-99 (J)
80°C
71mW/OC
8-Pin Hermetic DIP (Z)
75° C
6 7mW/o C
NOTES:
1 See table for maximum ambient temperature ratmg and derating factor
2 Absolute rallngs apply to both DICE and packaged parts, unless otherwise
noted
ELECTRICAL CHARACTERISTICS at Vs = ± 2.5Vto ± 15V, TA = 25° C, unless otherwise noted.
OP-221B/F
OP-221AlE
TYP
MAX
Vos
75
150
Input Offset Current
los
05
3
Input Bias Current
18
50
80
Input Voltage Range
IVR
V+ = 5V, V-=OV
Vs =±15V
Common-Mode
ReleCtlon RatiO
CMRR
V+=5V. V-=OV
OV$VcM $35V
Vs =±15V
-15V $ VcM $13 5V
Power Supply
Rejection RatiO
PSRR
Vs= ±2 5V to ±15V
V-=OV. V+=5Vt03OV
Large-Signal
Voltage Gain
AvO
Vs = ± 15V, RL = 10kO
Vo =±10V
Output Voltage
SWing
Vo
V+=5V. V-=OV.
RL = 10kO
Vs =±15V. RL = 10kO
Slew Rate
SR
Bandwidth
BW
PARAMETER
SYMBOL
Input Offset Voltage
Supply Current
(Both Amplifiers)
ISY
CONDITIONS
RL = 10kO. (Note 1)
MIN
MIN
OP-221C/G
TYP
MAX
TYP
MAX
150
300
250
500
5
15
60
100
70
0/35
-15/135
0/35
-15/135
MIN
UNITS
nA
120
0/35
-15/135
nA
v
90
100
85
90
75
85
95
100
90
95
80
90
dB
10
18
3
6
10
18
32
57
32
57
1500
1000
07/4.1
07/4.1
0.8/4
±138
±138
±13.5
0.2
03
02
450
600
Vs = ±2 5V. No Load
Vs = ± 15V. No Load
800
03
02
600
800
550
800
100
180
500
800
V/mV
V
0.3
kHz
600
600
850
550
850
650
900
ELECTRICAL CHARACTERISTICS at Vs=±2.5V to± 15V, -55° CS: TAS:+ 125° Cfor OP-221 A, Band C;-25° Cs: TAS:+85° C
for OP-221 E, F and G, unless otherwise noted.
OP-221B/F
OP-221A1E
PARAMETER
SYMBOL
CONDITIONS
MIN
Average Input Offset TCIl
Voltage Drift (Note 1)
os
Input Offset Voltage
Vos
Input Offset Current
los
VCM=O
Input Bias Current
Ie
VCM=O
IVR
V+ = 5V. V- = OV
Vs =±15V
CMRA
V+ = 5V, V- = OV
OV$VcM $32V
Vs =±15V
-15V$ VcM $13 2V
Input Voltage Range
Common-Mode
Relection RatiO
MAX
075
1.5
12
150
300
250
450
400
700
I'V
5
15
7
2
10
nA
65
120
80
140
nA
55
0/32
-15/132
-----
100
TYP
0/32
-15/132
MAX
MIN
TYP
0/32
-15/132
MAX
UNITS
3
I'VioC
V
85
90
80
85
70
80
90
95
85
90
75
85
dB
5-221
~-----
MIN
OP-221C/G
TYP
1/86, Rev. A
-----------I~ OP·221 DUAL LOW·POWER OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at VS= ±2.5V to ±
15V, -55° C~ TA~+ 125° C for OP-221 A, Band C;-25° C~ TA~+85° C
for OP-221 E, F and G, unless otherwise noted. (Continued)
PARAMETER
SYMBOL
CONDITIONS
Power Supply
Rejection Ratio
PSRR
Vs =±25Vto±15V
V-= OV. V+= 5V to 30V
Large-Signal
Voltage Gain
Ava
Vs =±15V, RL = 10kn
Vo =±10V
Va
V+ = 5V, V-=OV,
RL = 10kn
Vs = ±15V, RL = 10kn
Output Voltage
SWing
Supply Current
(Both Amplifiers)
OP-221A1E
TYP
MAX
MIN
6
10
18
32
500
700
±135
650
900
TYP
MAX
UNITS
57
100
180
320
JlVIV
600
0.8/38
±14
OP-221C/G
MIN
57
100
800
08/3.8
Vs = ±2.5V, No Load
Vs = ± 15V, No Load
ISY
18
32
1000
±135
OP-221B/F
MIN
TYP
MAX
V/mV
09/37
±14
550
900
V
±132
700
950
600
950
750
1000
JlA
NOTE:
1 Sample tested.
MATCHING CHARACTERISTICS
at Vs = ± 15V, TA = 25° C, unless otherwise noted.
CONDITIONS
OP-221AlE
MIN
TYP
MAX
PARAMETER
SYMBOL
Input Offset
Voltage Match
tJ.Vos
Average Nonmvertmg
BIBS Current
'6+
80
Nonlnvertmg Input
Offset Current
105+
5
Common-Mode
Rejection Ratio
Match (Note 11
tJ.CMRR
VCM = -15V to +13 5V
Power Supply
Rejection Ratio
Match (Note 21
tJ.PSRR
Vs = ±2.5V to ± 15V
50
MATCHING CHARACTERISTICS
OP-221B/F
MIN
TYP
MAX
200
150
400
TYP
MAX
UNITS
250
600
JlV
120
nA
10
nA
100
4
87
92
OP·221C/G
MIN
72
14
dB
44
140
JlV/V
at Vs = ±15V, -55°C ~ TA ~ +125°C for OP-221A, Band C; -25°C ~ TA ~ +85°C for
OP-221 E, F and G, unless otherwise noted. Grades E, F, and G are sample tested.
PARAMETER
SYMBOL
CONDITIONS
OP·221A1E
TYP
MAX
MIN
OP·221B/F
MIN
TYP
MAX
OP-221C/G
MIN
TYP
MAX
UNITS
400
800
JlV
140
nA
Input Offset
Voltage Match
tJ.Vos
Average Nonmverting
BIBS Current
'6+
VCM=O
100
120
Input Offset
Voltage Tracking
TCtJ.Vos
(Note 3)
2
3
3
Nonmvertmg Input
Offset Current
105+
VCM=O
7
6
Common-Mode
Rejection Ratio
Match (Note 11
tJ.CMRR
VcM =-15Vto+132V
Power Supply
Rejection Ratio
Match (Note 2)
tJ.PSRR
100
400
250
3
87
90
82
26
600
85
72
78
JlV/'C
12
80
nA
dB
250
JlV/V
NOTE:
tJ.CMRR 1520 log10 VcMI tJ.CME, where VCM IS the voltage applied to both
nonmvertmg inputs and .:lCME is the difference In common-mode
Input-referred error.
tJ.PSRR IS Input-Referred Differential Error
tJ.Vs
3. Sample tested
5·222
1/86, Rev. A
-----------l1fMD
OP-221 DUAL LOW-POWER OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
1. INVERTING INPUT (A)
2. NONINVERTING INPUT (A)
3. BALANCE (A)
4. V5.
6.
7.
•.
9.
10.
11.
12.
13.
14.
DIE SIZE 0.096 X 0.061 Inch, 5856 sq. mils
(2.44 X 1.55 mm, 3.78 sq. mm)
NOTE: All V+ PADS ARE INTERNALLY CONNECTED
BALA~PE (B)
NONIN\tERTING INPUT (B)
INVERTING INPUT (B)
BALANCE (B)
V+
OUT (B)
V+
OUT (A)
V+
BALANCE (A)
For additional DICE intormation refer to
1986 Dala Book, Section 2.
~
~
......
;:..t.,
~
~
WAFER TEST LIMITS at Vs= ± 2.SV to ± 1SV, TA = 2S"C, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
Input Offset Current
los
Input BIas Current
Ie
VCM=O
Input Voltage Range
IVR
V+=5V, V-=OV
Vs =±15V
Common-Mode
RejectIon RatIO
CMRR
V- = OV, V+ = 5V, OV" VCM " 3 5V
Vs = ±15V, -15V" VCM " 13 5V
Power Supply
RejectIon RatIO
PSRR
Vs =±2.5Vto±15V
V-= OV, V+ = 5V to 30V
Large-SIgnal
Voltage Gain
Ava
Vs =±15V
RL = 10kO
Output Voltage SWing
Va
V+ = 5V, V- = OV, RL = 10kO
Vs =±15V, RL = 10kO
Supply Current
(Both Amphliers)
ISY
Vs = ±2 5V, No Load
Vs = ± 15V, No Load
VCM=O
OP-221N
OP-221G
OP-221GR
LIMIT
LIMIT
LIMIT
UNITS
200
350
500
p.VMAX
35
5.5
7
nAMAX
85
105
120
nAMAX
0/35
-15/13.5
0/3.5
-15113.5
0/35
-15/135
V MIN/MAX
VMIN
88
93
83
88
75
80
dBMIN
12.5
22.5
40
70
100
180
p.VIV MAX
1500
1000
800
V/mV MIN
07/41
±138
07/41
±138
0.8/4
±13.5
V MIN/MAX
VMIN
560
810
610
860
650
900
p.AMAX
NOTE:
Electrical tests are performed at wafer probe to the lImIts shown Due to variatIons In assembly methods and normal YIeld los., YIeld alter packaging IS not
guaranteed for standard product dIce Consult factory to negotIate specIficatIons based on dIce lot qualifIcatIon through sample lot assembly and testIng
5-223
1/86, Rev. A
~
9
~
~
~
------------l~ OP·221 DUAL LOW·POWER OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
NORMALIZED INPUT OFFSET
VOLTAGE VI TEMPERATURE
OFFSET VOLTAGE SHIFT DUE
TO THERMAL SHOCK
INPUT OFFSET VOLTAGE
vs SUPPLY VOLTAGE
400
100
40
DEVICE IMMERSED
Vs = ±16V
75
!
50
25
...
0
g
.......
~
"-
~
5
~ 250
t;;
"- ,~
~
"
-75
-100
-50
-26
0
25
50
TEMPERATURE
75
100
150
~
100
o
126
re)
...~
a
65
80
65
~
60
~
5&
!
/ r"""-- r-....
/
70
V
50
./
V
45
I-..
L
/
.....
V
r---.
-
50
~
TEMPERATURE
75
SlF
V
AlE
50
45
""
~
ii!
+~oc
..... 1---"
500
400
~
300
200
........
o
.t2 5
:1:5
--
:1:75
~
........
.....-
C/G
.,::rc
...- ~
Loc
:1:10 :1:125 :1:15 :1:17,6 :1:20
POWER SUPPLY VOLTAGE (VOL lSI
~
I-
1.0
AlE
V
0
'fC/G
15
"IF
'/ t/"
~
05
'""""
r--
50
~
75
~
1~
~
o
700
500
400
300
f..-" V
V
i..--" V
--
0
25
,/
50
75
"IF
If
AlE
,/
100 126 160
TEMPERATURE (DC)
SUPPLY CURRENT vs
TEMPERATURE AT
Vs = ± 15V AND ±2.5V
INITIAL OFFSET VOLTAGE
DRIFT VI TIME
I
V =:t15V..,
..
;;....-
--- ---
.... ...
::::=-
--
I--
./ ~ ~
,/
800
.00
--
io'
TEMPERATURE (Cle)
900
I-""
-
i.-
/ V
rei
600
V
INPUT OFFSET CURRENT
VI TEMPERATURE
-75 -50 -26
1000
700
10 20 30 40 50 60 70 80 90 100
TIME (SEC)
100 126 150
900
600
-20
-20 -10 0
20
v. ", l....-" r-I-..
55
I'...
1000
"..~
.
:1:17.5
25
60
SUPPLY CURRENT VI SUPPLY
VOLTAGE FOR OP·221A1E
.s
:1:15
3.0
35_ _ _
26
:1:126
75
40
0
:1:10
.5
35
-76 -50 -25
:1:76
VS"':l:2SV
c/G
/'
40
:1:5
70
/
lL
:1:2.5
-10
INPUT BIAS CURRENT
VI TEMPERATURE
80
VS=:t1SV
--
.......... AlE
POWER SUPPLY VOLTAGE (VOL lSI
85
75
o
I
,... 8/F
V
~
........
C/G
V
....V
r--....
50
INPUT BIAS CURRENT
VI TEMPERATURE
!
\
f\.
,
200
o
.".
1\
g
-60
-75
--J
300
!i1
:5-25
!
-~~
;;
"~
~
IN 700C OIL BATH
350
-
~ ;;..-
C/G
"IF
AlE
C/G
"IF
AlE
\ \
U.VS'>25V
200
100
-75 -50 -25
0
25
50
75
TEMPERATURE (DC)
5·224
100 125 150
-2 0 L-J.........J--L---l_L--J......-L-L---J:--J
o 1 2 3 4 5 6 7 8 9 10
TIME (MINUTES)
1/86, Rev. A
------------1~ OP-221 DUAL LOW-POWER OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN-LOOP GAIN AT ±15V
VB TEMPERATURE
OPEN-LOOP GAIN AT ± 5V
VB TEMPERATURE
140
OPEN-LOOP GAIN
SUPPLY VOLTAGE
VB
140
140
~
do
do
120
;;;
'
VB FREQUENCY
100
10
80
~
~
~
70
50
40
3
z
:!:
§
g
~
60
30
20
~
1\
~
3z
10
~
a'"
........
10
"
01
10
100
lk
10
FREQUENCY (Hz)
100
lk
FREQUENCY (Hz)
NONINVERTING STEP RESPONSE
INPUT
OUTPUT
INVERTING STEP RESPONSE
10kfl
INPUT 10k.Q
OUTPUT
5-226
1/86, Rev. A
-----------I1fW
OP-221 DUAL LOW-POWER OPERATIONAL AMPLIFIER
SPECIAL NOTES ON THE APPLICATION OF
DUAL MATCHED OPERATIONAL AMPLIFIERS
The high open-loop gain of the OP-221 is very important in
achieving good CMRR in this configuration. Finite open-loop
gain of A1 (Ao,) causes undesired feedthrough of the
common-mode input. For Ad/ Ao, «1, the common-mode
error (CME) at the output due to this effect is approximately
(2 Ad/A o,) x VCM. This circuit features independent adjustment of CMRR and differential gain.
ADVANTAGES OF DUAL MONOLITHIC
OPERATIONAL AMPLIFIERS
Dual matched operational amplifiers provide the engineer
with a powerful tool fordesigning instrumentation amplifiers
and many other differential-input circuits. These designs are
based on the principle that careful matching between two
operational amplifiers can minimize the effect of DC errors in
the individual amplifiers.
Three-Op-Amp Configuration
The three-op-amp circuit (Figure3). has increased commonmode voltage range because the common-mode voltage is
not amplified as it is In Figure 2. The CMR of this amplifier is
directly proportional to the match of the CMR of the input op
amps. CMRR can be raised even further by trimming the
output stage resistors.
Reference to the circuit shown in Figure 1, a differential-in,
differential-out amplifier, shows how the reductions in error
can be accomplished. Assuming the resistors used are
ideally matched, the gain of each side will be identical. If the
offset voltages of each amplifier are perfectly matched, then
the net differential voltage at the amplifier's output will be
zero. Note that the output offset error of thiS amplifier IS not a
function of the offset voltage of the individual amplifiers, but
only a function of the difference (degree of matching)
between the amplifiers' offset voltages. This error-cancellation principle holds for a considerable number of input
referred error parameters - offset voltage, offset voltage
drift, inverting and noninverting bias currents, commonmode and power supply rejection ratios. Note also that the
impedances of each input, both common-mode and differential-mode, are high and tightly matched, an important
feature not practical with single operational amplifier circuits.
RD
GAIN
r-'Vv.---J\Nv----<~ ADJ
R1
Vl
V
+
INPUT
OP·221
R2
-=1=-
~
~
(1/2)
OP·221
VCM + 1/2Vd
Va"
of
R4
R3
R3
R'
R2
R4 [ 1 + 2"
, (R2
R3) + R2+R3]
R3
FIT + R4
~
Figure 2
R4 (R3
R4
Vd + Ra
R2)
- AT
IF R1 = R2= R3=R4, THENVO=2 (1
VCM
+~)Vd
+
R'
OUTPU
-
V
VCM -1/2Vd
RD
R4
Vo
Figure 1
INSTRUMENTATION AMPLIFIER APPLICATIONS
Two-Op-Amp Configuration
The two-op-amp circuit (Figure 2). is recommended where
the common-mode input voltage range is relatively limited;
the common-mode and differential voltage both appear at V1.
R2
v-
Figure 3
5-227
1/86, Rev. A
II
OP-227
JPMI)
DUAL LOW-NOISE LOW-OFFSET INSTRUMENTATION
OPERATIONAL AMPLIFIER
Prccisiol1 Monolithics Inc.
FEATURES
•
•
•
•
•
•
•
•
•
Excellent Individual Amplifier Parameters
Low Vos ................................... 80!'V Max
Offset Voltage Match ....................... 80!'V Max
Offset Voltage Match vs Temperature ..... l!'V/oC Max
Stable Vos vs Time ...................... l!'V/Mo Max
Low Voltage Noise ................. 3.9nV/y'HZ Max
Fast ..................................... 2.8V/!,s Typ
High Gain ............................ 1.8 Million Typ
High Channel Separation ............... . .. 154dB Typ
ORDERING INFORMATIONt
TA=25°C
YosMAX
(!'Y)
HERMETIC
DIP
14-PIN
OPERATING
TEMPERATURE
RANGE
80
80
120
120
180
180
OP227AY'
OP227EY
OP227BY'
OP227FY
OP227CY'
OP227GY
MIL
INO
MIL
INO
MIL
INO
• For devices processed In total compliance to MIL-STD-883. add /883 after
part number Consult factory for 883 data sheet
tAli commercial and Industnal temperature range parts are available with
burn-in. For ordering information see 1986 Data Book, Section 2
When used in a three-op-amp instrumentation amplifier configuration, the OP-227 can achieve a CMRR in excess of
100dB at 10kHz. In addition, this device has an open-loop
gain of t5M typical with a 1kO load. The OP-227 also features
an 18 of ± 10nA typical, an los of 7nA typical, and guaranteed
matching of input currents between amplifiers. These outstanding input current specifications are realized through the
use of a unique input current-cancellation-circUit which
typically holds 18 and los to ±20nA and 15nA respectively
over the full military temperature range.
Other sources of input-referred errors, such as PSRR and
CMRR, are reduced by factors In excess of 120dB for the
individual amplifiers. D.C. stability is assured by a long-term
drift specification of tOllY/month.
Matching between channels is provided on all critical parameters including offset voltage, tracking of offset voltage vs.
temperature, noninverting bias current, CMRR, and power
supply rejection ratio. This unique dual amplifier allows the
elimination of external components for offset nulling and
frequency compensation.
The OP-227 is pin compatible with the OP-l0 and OP-207.
PIN CONNECTIONS
GENERAL DESCRIPTION
14-PIN CERAMIC DIP
(V-Suffix)
The OP-227 is the first dual amplifier to offer a combination of
low offset, low noise, high speed and guaranteed amplifier
matching characteristics in one device. The OP-227 with a
Vos match of 25!'V typical, a TCVos match of O.3!,VfDC
typical, and a l/f corner of only 2.7Hz is an excellent choice
for precision low nOise designs. These D.C. characteristics,
coupled with a slew rate of 2.SV/!,s typical and a small-signal
bandwidth of SMHz typical, allow the designer to achieve AC
performance previously unattainable with op-amp-based
instrumentation designs.
NOTES:
1 Device may be operated even If
insertion IS reversed, this IS
due to Inherent symmetry of
pm locations of amplifiers A
and 8
V-IAI and V-181 are Internally
connected via substrate
resistance
SIMPLIFIED SCHEMATIC (1/2 OP-227)
r-------~----------~--------~--~~--~-------.------~~~--~~~~v,
OUTPUT
NON
INVERTING
INPUT I,,'_I-+-~~""'-+----E----t:
INVERTING
INPUT H
~4-~~~~------+-------~
L---------------~----~------~----------~~~~--~_v-
5-228
1/86, Rev. A
_ _ _ _ _--j~
OP-227 DUAL LOW-NOISE LOW-OFFSET INSTRUMENTATION OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
NOTES:
Supply Voltage •••••••••••••••••••••••••••••.••••• ±22V
1. See table for maximum ambient temperature rating and derating factor.
Internal Power Dissipation (Note 1) •••••••••••••• 500mW
Input Voltage (Note 3) •••••••••••••••••••••••••••• ±22V
Output Short-Circuit Duration ••••.•••••.••••.. Indefinite
Differential Input Voltage (Note 2)
•••••••.•••.••••
±0.7V
Differential Input Current (Note 2) ••••••••••••••• ±25mA
Storage Temperature Range •••••••••••
PACKAGE
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
14-Pin (V)
106'C
11.3mW/'C
-65°C to +150°C
Operating Temperature
OP-227 A, OP-227B, OP-227C ••••••• -55° C to + 125° C
OP-227E, OP-227F, OP-227G ••••••••• -25°C to +85°C
3
Lead Temperature Range (Soldering, 60 sec) •••••• 300°C
The OP-227's Inputs are protected by back-to-back diodes. Current
limiting resistors are not used In order to achieve low noise. If differential
input voltage exceeds ±0.7V, the input current should be limited to 25mA.
For supply voltages less than ±22V, the absolute maximum input voltage is
equal to the supply voltage.
INDIVIDUAL AMPLIFIER CHARACTERISTICS
at Vs
PARAMETER
SYMBOL CONDITIONS
OP-227A/E
MIN
TVP
MAX
Input Offset Voltage
Vas
Long· Term Vas
Stability
Vas/Time (Notes 2,4)
Input Offset Current
los
Input Bias Current
18
= ±15V, TA = 25°C, unless otherwise noted.
(Note 1)
OP-227B/F
TVP
MAX
MIN
OP-227C/G
MIN
TVP
MAX
80
40
120
60
180
~V
0.2
1.0
0.3
1.5
0.4
2.0
~V/Mo
50
12
75
nA
35
±IO
±40
±12
±55
±15
±BO
nA
O.OB
0.20
O.OB
0.20
0.09
0.2B
~Vp.p
9.0
5.9
4.6
nV/v"HZ
Input Noise Voltage
8 np _p
0.1 Hz to 10Hz
(Notes 3, 5)
Input Noise
Voltage Density
en
fo = 10Hz (Note 3)
fo=30Hz (Note 3)
fo = 1000Hz (Note 3)
3.5
3.1
3.0
6.0
4.7
3.9
3.5
3.1
3.0
6.0
4.7
3.9
3.B
3.3
32
Input Noise
Current Density
in
fo= 10Hz (Notes 3, 6)
fo = 30Hz (Notes 3, 6)
fa = 1000Hz (Notes 3, 6)
1.7
1.0
04
4.5
2.5
0.7
17
1.0
04
45
2.5
0.7
1.7
1.0
04
Input ResistanceDifferential-Mode
A'N
Input Resistance Common-Mode
R 1NCM
(Note 7)
IVA
CMAA
VCM = ±11V
Power Supply
Rejection RatiO
PSAA
Vs = ±4V to ±IBV
Ava
A L <:2kn, Vo=±IOV
AL<: 600n, Vo= ±IOV
Va
AL<: 2kn
AL<: 600n
Output Voltage Swing
Mn
Gn
±123
±110
±123
±11.0
±12.3
V
114
126
106
123
100
120
dB
10
10
20
1800
1500
1000
800
1800
1500
700
600
1500
1500
V/mV
±12.0
±10.0
±13.8
±115
±12.0
±IO.O
±13.8
±115
±11.5
±IO.O
±13.5
±11.5
V
28
1.7
2.8
17
2.8
V/~s
5
8
5
SA
AL <: 2kn (Note 4)
GBW
(Note 4)
Open-Loop Output
Resistance
Ao
Vo=O,lo=O
70
Power Consumption
Pd
Each Amplifier
90
1.7
Ap= 10kn
±4
5
NOTES:
Input offset voltage measurements are performed by automated test
equipment approximately 05 seconds after application of power
AlE grade specifications are guaranteed fully warmed up
Long-Term Input Offset Voltage Stability refers tothe average trend line of
Vos vs Time over extended periods after the first 30 days of operation
Excluding the Initial hour of operation, changes In Vos dUring the first 30
70
140
90
70
140
100
±4
4
5.
7
MHz
--
----~---
n
170
±4
mW
mV
days are tYPically 2 5JlV - refer to tYPical performance curve.
Sample tested
Parameter IS guaranteed by design
See test circuit and frequency response curve for 0 1Hz to 10Hz tester.
See test circuit for current nOise measurement
Guaranteed by Input bias current
1/86, Rev. A
5-229
- - - - - ---------
~VIV
1000
800
Slew Aate
--------
------
---"------
------------
~
~
......
>L.
......
.....:I
p..
~
~
0
......
~
~
p..
0
±IIO
Gain Bandwidth Prod.
Offset Adjustment
Aange
0.7
25
Input Voltage Aange
Voltage Gain
PA/v"HZ
0.7
094
13
Common-Mode
Rejection RatiO
Large-Signal
UNITS
20
------JIEMD
OP-227 DUAL LOW-NOISE LOW-OFFSET INSTRUMENTATION OPERATIONAL AMPLIFIER
INDIVIDUAL AMPLIFIER CHARACTERISTICS for Vs = ± 15V, -55° C ~ TA ~ + 125° C, unless otherwise noted.
OP-227A
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
(Note 1)
Average Input
Offset Drift
TCVos
TCVOsn
(Notes 2, 3)
Input Offset Current
los
Input Bias Current
Ie
Input Voltage Range
IVR
Common-Mode
MIN
CMRR
VCM
Power Supply
Rejection Ratio
PSRR
Vs ~ ±4.5V to ±18V
Large-Signal
Voltage Gain
AvO
RL;e 2kll, Vo
Output Voltage SWing
Vo
Rejection Ratio
~
±10V
~
±10V
OP-227B
TYP
MAX
60
0.3
MIN
MAX
TYP
MAX
UNITS
180
80
270
110
350
!'V
10
0.4
1.5
0.5
1.8
15
50
22
85
30
135
nA
±60
±28
±95
±35
±150
nA
±10.0
±115
±10.0
±115
±10.0
±11.5
V
108
122
100
119
94
116
dB
16
20
Input Offset Voltage
Vos
Average Input
TCVOS
TCVOS n
Offset Drift
Input Offset Current
500
1000
300
800
V
±11.5
±13.5
±110
±132
±105
±130
V
~
TA ~ 85° C, unless otherwise noted.
OP-227F
TYP
MAX
(Note 1)
40
(Note 2)
0.5
MIN
los
Common-Mode
Rejection Ratio
Power Supply
Rejection RatiO
IVR
CMRR
PSRR
Large-Signal
Voltage Gain
AVO
Output Voltage Swing
Vo
Vs
~
MIN
OP-227G
TYP
MAX
TYP
MAX
140
60
200
85
280
10
04
15
0.5
18
MIN
UNITS
10
50
14
85
20
135
nA
±14
±60
±18
±95
±25
±150
nA
± 10.0
± 11.8
±10.0
±11.8
110
124
102
121
±10.0
±11.8
V
96
118
dB
16
15
±4.5V to ±18V
RL;e 2kll
51
1200
Input Bias Current
Input Voltage Range
4
600
OP-227E
SYMBOL CONDITIONS
MIN
±20
INDIVIDUAL AMPLIFIER CHARACTERISTICS for Vs = ±15V, -25°C
PARAMETER
OP-227C
TYP
32
750
1500
700
1300
450
1000
V/mV
±11.7
±13.6
±11.4
±13.5
±11.0
±133
V
NOTES:
Input Offset Voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power.
2. The TeVos performance is within the specifications unnulled or when
nulled with Rp = 8kO to 20kO, optimum performance is obtained with
Rp ~ 8kll.
Sample tested.
MATCHING CHARACTERISTICS for Vs = ± 15V, TA = 25° C, unless otherwise noted.
OP-227A/E
PARAMETER
SYMBOL CONDITIONS
MIN
Input Offset Voltage
Match
Average Nonmverting
Bias Current
Noninverttng Offset
Current
los+
Inverting Offset Current
Common-Mode
110
Rejection Ratio Match
Power Supply
Rejection RatiO Match
IlPSRR
Vs ~ ±4V to ±18V
Channel Separation
CS
(Note 1)
OP-227B/F
TYP
MAX
25
MIN
MAX
80
35
±10
±40
±12
±12
TYP
MAX
150
55
300
±12
±55
±15
±90
nA
±60
±15
±80
±20
±130
nA
±60
±15
±80
±20
±130
nA
123
103
120
10
126
OP-227C/G
TYP
154
5-230
MIN
97
117
10
126
154
UNITS
dB
20
126
154
dB
1/86, Rev. A
-----
~
------
OP-227 DUAL LOW-NOISE LOW-OFFSET INSTRUMENTATION OPERATIONAL AMPLIFIER
MATCHING CHARACTERISTICS for Vs= ±15V, TA = -55°C to +125°C, unless otherwise noted.
OP-227A
PARAMETER
SYMBOL CONDITIONS
Input Ollset Voltage
Match
t!.Vos
Input Ollset Voltage
Tracking
TCt!.Vos
Average Noninverting
Bias Current
la+
Average Drift of NonInverting Bias Current
TCl a+
Nonlnvertlng Ollset
Current
los+
MIN
Nulled or
Unnulled (Note 2)
I
_la+A+la+a
a + - - -2- -
OP-227B
TYP
MAX
55
MIN
MAX
180
75
0.3
1.0
±20
±60
100
Average Drift of NonTC1 08+
Inverting Ollset Current
±90
Inverting Ollset Current
I os-
108-= I a-A-I a-a
t!.CMRR
VCM=±10V
Power Supply
Rejection Ratio Match
t!.PSRR
V8 = ±4.5V to ±18V
MAX
UNITS
300
100
480
p.V
0.4
1.5
0.5
1.8
p.V/'C
±28
±95
±35
±170
nA
200
±140
±45
200
±25
105
TYP
±35
130
Common-Mode
Rejection Ratio Match
MIN
160
±25
los+ = I a+A-1a+a
OP-227C
TYP
±35
±90
118
97
16
pA/'C
±250
250
±140
90
3
pA/'C
±45
114
±250
110
20
nA
nA
dB
4
51
p.VIV
TYP
MAX
UNITS
OP-227F
OP-227E
SYMBOL CONDITIONS
Input Ollset Voltage
Match
t!.Vos
Input Ollset Voltage
Tracking
TCt!.Vos
Average No",nvertlng
Bias Current
la+
TYP
MAX
40
NUlled or
Unnulled (Note 1 )
_la+A+la+a
a+--2- -
Average Drift of NonInvertl ng Bla. Cu rrent
TCl a+
Noninverting Ollset
Current
los+
I
MIN
MIN
210
90
400
p.V
~
0.3
1.0
0.4
1.5
05
1.8
p.V/·C
C5
±14
±60
±18
±95
±25
±170
nA
±20
140
±90
±25
±90
±25
130
los- = la-A-I a- a
VcM =±10V
Power Supply
Rejection Rat,o Match
t!.PSRR
Vs = ±4.5V to ± 18V
0......
65
MIN
ILl
Average Drift of NonTClos+
inverting Ollset Current
los-
OP-227G
140
±20
t!.CMRR
~
MAX
los+ = I a+A-1a+a
Common-Mode
Rejection Ratio Match
2
TYP
80
Inverting Ollset Current
~
~
MATCHING CHARACTERISTICS for Vs = ±15V, TA = -25°C to +85°C, unless otherwise noted.
PARAMETER
ffi
......
106
180
±140
±35
±140
±35
200
98
120
15
pA/'C
±250
250
117
90
pA/'C
±250
112
16
3
nA
nA
dB
32
p.VIV
NOTES:
1. Sample tested.
2. Guaranteed by de.'gn.
1/86, Rev. A
5-231
~~~~~~~-------
-~--~-~--~-----
-~---
-
-------~-~-
------II£MD
OP-227 DUAL LOW-NOISE LOW-OFFSET INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE NOISE TEST CIRCUIT (0.1 Hz-TO-10Hzp _p)
LOW-FREQUENCY NOISE
120
~
100
80
~
0
z
40
~
-40
."
236pfF
SCOPE
-80
>
XI
RIN"",M,Q
-120
110kn
o 1Hz TO 10Hz PEAK-TO-PEAK NOISE
NOTE: OBSERVATION TIME MUST BE LIMITED TO 10 SECONDS
TO ENSURE 0.1 Hz CUTOFF.
VOLTAGE NOISE DENSITY
va FREQUENCY
,a
'00
9
8
1
INPUT WIDEBAND NOISE
va BANDWIDTH (0.1 Hz TO
FREQUENCY INDICATED)
COMPARISON OF OP-AMP
VOLTAGE NOISE SPECTRA
t---!i;;
10
141
TA - 25"C
Vs • +15V
TA '" 2SoC
Vs '" ±15V
~
\
\
I/f CORNER
'" 2 7Hz
-
,
......
,
Ilf CORNER
Ilf CORNER
27Hz
~~
I
~~
lOW NOISE
AUDIO
QP AMP
IIIII
11111
INSTRUMENTATION
RANGE, TO DC
1~,~-L~~lO~-L~W,~oo~-L~WJ'k
10
1
IIIII
AUDIO RANGE
TO 20kHz
00
100
lk
TOTAL NOISE va
SOURCE RESISTANCE
VOLTAGE NOISE DENSITY
va TEMPERATURE
~
lOOk
~
I-----I-jl-+++++fj--
RS "" 2R1
.
~
r-~'O~_
~
10k
'00
1
12
lk
CURRENT NOISE DENSITY
va FREQUENCY
==~
5Vt-+1+H+--_
I-I--_VS-t-=-j±1r-
100
BANDWIDTH (Hz)
100 F===f===f9''FffffF=====t'I
TA=2"C
,
FREQUENCY (Hz)
FREQUENCY (Hz)
F
........ 1-"
I/f CORNER
-- -
OP-227
AT 10Hz
~'kHz
Ilf CORNER
I-- - =
0'
100
'k
SOURCE RESISTANCE (.Q)
10k
-50
-25
25
50
75
TEMPERATURE (OC)
5-232
100
125
10
140Hz
IIIIIIII I
100
lk
FREQUENCY (Hz)
10k
1/86, Rev. A
------I~ OP-227 DUAL LOW-NOISE LOW-OFFSET INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT
OFFSET VOLTAGE DRIFT
OF REPRESENTATIVE UNITS
VI SUPPLY VOLTAGE
OFFSET VOLTAGE
STABILITY WITH TIME
120
10
OP-227C
100
80
-
I--TA = +12~
/ / --:::::: /
'~
~
V
TA • +25°C,
t;:: ---:::. ~
"'"
f-"""
>
Ii;
~
~
'0
......
......
.;><
I'-..
-60
-
W
5
~
ffi
~
~
~
~
~
-75 -66 -36 -15 6
Tl
=
;;
+,J
V
/
~
-
OP-'~7B1F
.
I
;::
;::
~
lILV-
OP-227AjE
V~=~,.)-
I I
--I
1
2
3
4
5
1-- B~
1--
7
0
-20
50
~
110
VS .. ±15V -
m 90
I
10
OP-227B
4J.J
§"
o
-75 -50
--
-25
"o
~
OP-221B
i--
0
UI
60
80
'"
50
75
125
50
75
"
'\
125
150
SLEW RATE, GAIN-BANDWIDTH
PRODUCT, PHASE
MARGIN VI TEMPERATURE
1
=~M
±1SV-
-GBW
I'\.
'\
50
-
II'\.
50
100
Vs
"
'\..
30
-
I'\.
r-
-SLEW
I'\.
"
-"I'"
.......
10
100
lk
10k 100k
FREQUENCY (Hz)
5-233
- ----------------
25
80
-10
100
0
I'\.
10
I
25
-25
TEMPERATURE (oC)
OP-227A
TEMPERATURE (oC)
-50
100
70
z
,I'\.
12
OP-227 A
r-...
:;: 70
,~ ~ ~,..,
40
20
:!!
OP-227C
10 11
OP-227C
r-..r-., i'r-., ~rr--
I
OPEN-LOOP GAIN
VI FREQUENCY
II
~
9
IJU
TIME (SEC)
130
t-
20
SHOCK
'If I
w
=
III-- V
OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK
~ 25
OP-227C/G
3
j!:
O.'.V/~ ~
TIME (MONTHS)
'"~
t;
4
'"'"
TEMPERATURE (GCI
3~
r- Vs =±15V
~
iii
...... OP- 27.
-100
TOTAL SUPPLY VOLTAGE (VOLTS)
WARM-UP DRIFT
.....
r-..
-so
,
"" OP-f'7A
:.-::: -.?' I'-..
--10
.I
./
..... iX r-...""'"
f'
-,0
~
0
VrA'" -5S O C
-t-
60
~
V ,..... OP-~.
1M
10M 100M
-75
-50
-25
0
25
50
TEMPERATURE
75
100
125
fe)
1/86, Rev. A
-------1~
OP·227 DUAL LOW·NOISE LOW·OFFSET INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
GAIN, PHASE SHIFT
VI FREQUENCY
25
20
15
~
~10
\
Z
~
80
Tl J2~~1
~LJ
20 ;--TA
140
1M
10M
10
r--- poslmv1e
Rl= lkH
l-
;...-
SWING
I"
NEGATIVE
SWING
//
V
//
200
'\
220
100M
I--
Vs '" ±15V
60
80
>-
5
~ 30
Vs = ±15V
U
VIN =lOOmV
AV= +1
a:
"I":
-
-:s~1
' SC (+)
~
o
i:!i
TA '" +25 0
Vs = ±1SV
20
10
500
10M
FREQUENCY (Hz)
SMALL-SIGNAL
TRANSIENT RESPONSE
1000
1500
2000
CAPACITIVE LOAD (pFl
a
2500
LARGE-SIGNAL
TRANSIENT RESPONSE
TIME FROM OUTPUT SHORTED TO GROUND (MINUTES)
MATCHING CHARACTERISTIC
CMRR MATCH VI FREQUENCY
140
+50mV
+5V
OV
OV
120
'"
100
-50mV
-5V
80
AVCL = +1, CL:; 15pF
Vs = ±15V
AVCL" +1
TA"25 C
TA = 25°C
Q
Vs
=±15V
60
1k
10k
lOOk
1M
10M
FREQUENCY (Hz)
5·234
1/86, Rev. A
-----t1EHD
OP-227 DUAL LOW-NOISE LOW-OFFSET INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
COMMON-MODE INPUT RANGE
vs SUPPLY VOLTAGE
OPEN-LOOP VOLTAGE GAIN
VB LOAD RESISTANCE
140
~AI.12~!~II+-+++t+Htt--+H++HH
:: r-
121---+--
• ±15V"t--t-t:J;;I#!!+--++++++1H
120
218t-~-K~r,~-H~-f--+-HH+HH
's
::Sl00
~ 20 t-- Vs
c
"
/
a:
a:
~'6t-~-K~~~-H~-f--+-HH+HH
~e 80
l!
"~14t-~-K~t-~-H~-f--+-HH+HH
g'2t-~-K~t-~-H~-f--~HH+HH
-4~-~~~-~---~---4
-16
a:
a:
~10t-~~~t-~-H~-f--~HH+HH
II
80
~
~
l5
i'
~
-80
~O
~
'
~...
.....
l- f- r- O·-f27'
,... I:>oc f""'.t--.
~
r--. I'"
..... r-.,
V
iiia:
"'" OP-227A
-
......
k
~
~
..... ~ F- OP-227A
~
"
-100
ffi
\
40
\
\
-
~0'-227S
......
-I20
Z
;> ,-227S
\
-56
-35 -15
5
"-
""- ""
0•.227?'10
TEMPERATURE (OC)
25
45
65
85 105
-55
125
-35
TEMPERATURE (OC)
MATCHING CHARACTERISTIC;
CMRR MATCH
VB TEMPERATURE
~
\
\
r-.,
r
o
~
\ \
j P-22 A
Z
25 45 65 85 105 125 145 165
30
>
........
0
' \ OP-227C
9
\
\OP-227C
i'\OP-227C
'\. "-
>
.,.Z 10
I
I
5
20
">=z
I
" ' OP-2278
/'
-120
-75 -55 -35 -15
""
OP-2278
r-- r-.,
30
~
80
a:
OP-~27C
~k
MATCHING CHARACTERISTIC;
p.,
AVERAGE OFFSET
~
CURRENTvsTEMPERATURE
~
(INVERTING OR NONINVERTING) ~
40
I
./~
~
MATCHING CHARACTERISTIC;
AVERAGE NONINVERTING
BIAS CURRENT
VB TEMPERATURE
-15
......
5
25
45
65
85
105
125
TEMPERATURE (OC)
CHANNEL SEPARATION
vs FREQUENCY
125
160
OP-227A
d•.22;s
V
120
L'
115
V
",.....
Ol-227l
.......
r......
r--...
",.....
V
V
110
'"
140
'\
120
""\
100
80
105
-55 -35
I'
60
-15
5
25
46
65
85
105
100
125
TEMPERATURE ("C)
10k
1k
lOOk
1M
10M
FREQUENCV (Hz)
1/86, Rev. A
5-235
~--------------.------~----
-- -
-----.--
~~~-
------I~ OP-227 DUAL LOW-NOISE LOW-OFFSET INSTRUMENTATION OPERATIONAL AMPLIFIER
BASIC CONNECTIONS
INSTRUMENTATION AMPLIFIER APPLICATIONS OF THE
OP-227
The excellent input characteristics of the OP-227 make it
ideal for use in instrumentation amplifier configurations
where low-level differential signals are to be amplified. The
low-noise, low input offsets, low drift, and high gain combined with excellent CMR provides the characteristics
needed for high-performance instrumentation amplifiers. In
addition, CMR vs. frequency is very good due to the wide
gain-bandwidth of these op amps.
OFFSET NULLING CIRCUIT
V+(A)
10kO
'4
(-)0-4--1
The circuit of Figure 1 is recommended for applications
where the common-mode input range is relatively low and
differential gain will be in the range of 10 to 1000. This twoop-amp instrumentation amplifier features independent
adjustment of common-mode rejection and differential gain.
Input impedance is very high since both inputs are applied to
non-inverting op amp inputs.
>-_-+'.:.3-oOUTIA)
INPUTS
1+10---"-If--I
'--_ _-+'"'-2--0 V-fA)
OP....227
.-----+=---o V-IBI
1+lo-...!'.!.j'f--I
INPUTS
>--+"---oOUTIBI
FIGURE 1: Two-Op-Amp Instrumentation Amplifier Configuration
I-Io-.:.::'O+---I
RO
Rl
R2
V+(B)
V1
VCM - 1/2Vd
APPLICATIONS INFORMATION
0-----1
R4
R3
NOISE MEASUREMENTS
Vo
To measure the 80nV peak-to-peak noise specification of the
OP-227 in the 0.1 Hz to 10Hz range, the following precautions
must be observed:
VCM + 1/2Vd 0 - - - - - - - - - - - 1
-m:r-
R4 [ 1 + '2
'(R2
R3) + R2+R3J Vd
Vo='R3
if'j+Fi4
(1) The device has to be warmed-up for at least five minutes.
As shown in the warm-up drift curve, the offset voltage
typically changes 4p.V due to increasing chip temperature after power-up. In the 10-second measurement
interval these temperature-induced effects can exceed
tens-of-nanovolts.
Vo= R4 (1 + R3 + R2+ R3) Vd, where R3_ R2
R3
R4
Ro
R4 -R;'
(3) Sudden motion in the vicinity of the device can also
"feedthrough" to Increase the observed noise.
VCM
The output voltage Vo, assuming ideal op amps, IS given in
Fig. 1. The input voltages are represented as a commonmode input VCM plus a differential input Vd. The ratio R3/R4is
made equal to the ratio R2/Rl to reject the common-mode
input VCM. The differential signal Vd is then amplified
according to:
(2) For similar reasons, the device has to be well-shielded
from air currents. Shielding minimizes thermocouple
effects.
(4) The test time to measure 0.1 Hz to 10Hz noise should not
exceed 10 seconds. As shown in the noise-tester frequency-response curve, the 0.1Hz corner is defined by
only one zero. The test time of 10 seconds acts as an
additional zero to eliminate noise contributions from the
frequency band below 0.1 Hz.
R4 (R3
R2)
+ii3
R4 - R1
Note that gain can be independently varied by adjusting Ro.
From considerations of dynamic range, resistor tempco
matching, and matching of amplifier response, it is generally
best to make R10 R2, R3, and R4 approximately equal. Designating Rl, R2, R3, and R4 as RN allows the output equation to
be further simplified:
(5) A noise-voltage-density test is recommended when
Vo=2(1 +
measuring noise on a large number of units. A 10Hz
noise-voltage-density measurement will correlate well
with a 0.1 Hz-Io-10Hz peak-Io-peak nOise reading, since
both results are determined by the white noise and the
location of the 1/f corner frequency.
:~)Vd' where RN= Rl = R2= R3= R4
Dynamic range is limited by A1 as well as A2; the output of A1
is:
5-236
1/86, Rev_ A
_ _ _ _ _--/~ OP-227 DUAL LOW-NOISE LOW-OFFSET INSTRUMENTATION OPERATIONAL AMPLIFIER
If the instrumentation amplifier were designed for a gain of 10
and maximum Vd of ±1V, then RN/Ro would need to be four
and Vo would be a maximum of ±10V. Amplifier A1 would
have a maximum output of ±SV plus 2VCM, thus a limit of
±10V on theoutputof A1 would imply a limitof±2.SVon VCM.
A nominal value of 10kO for RN is suitable for most applications. A range of 200 to 2.SkO for Ro will then provide a gain
range of 10 to 1000. The current through Ro is Vd/Ro, so the
amplifiers must supply ±10mV/200 (or ±O.SmA) when the
gain is at the maximum value of 1000 and Vd is at ± 10mV.
A complete instrumentation amplifier designed for a gain of
100 is shown in Figure 2. It has provision fortrimming of input
offset voltage, CMR, and gain. Performance is excellent due
to the high gain, high CMR, and low noise of the individual
amplifiers combined with the tight matching characteristics
of the OP-227 dual.
FIGURE 2: Two-Op-Amp Instrumentation Amplifier Using
OP-227 Dual
Rejecting common-mode inputs is important in accurately
amplifying low-level differential signals. Two factors determine the CMR in this instrumentation amplifier configuration
(assuming infinite gain):
995kQ
3
,e
10
VCM + 1/2Vd
~l[
~
"
~
13
i-I-l
......
~
12
::s
~
v-
~
"
K
~
6
5
v+
Va
=
100Vd
v-
~
a......
~
10kn, 0 1%
10kn, 0 1%
i-I-l
C;
A three-op-amp instrumentation amplifier configuration
using the OP-227 and OP-27 is recommended for applications requiring high accuracy over a wide gain range. This
circuit provides excellent CMR over a wide frequency range.
As with the two-op-amp instrumentation amplifier circuits,
the tight matching of the two op-amps within the OP-227
package provides a real boost in performance. Also, the lownoise, low offset, and high gain of the individual op-amps
minimize errors.
where Ad is the instrumentation amplifier differential gain
and A02 is the open-loop gain of op amp A2. This analysis
assumes equal values of R" R2, R3, and R4. For example,
consider an OP-227 with A02 of 700V/mV. If the differential
gain Ad were set to 700, then the gain error would be 1/1.001
which is approximately 0.1%.
A simplified schematic is shown in Figure 3. The input stage
(A 1 and A2) serves to amplify the differential input Vd without
amplifying the common-mode voltage VCM. The output
stage then rejects the common-mode input. With ideal opamps and no resistor matching errors, then the outputs of
each amplifier will be:
Another effect offinite op amp gain is undesired feedthrough
of common-mode input. Defining Ao, as the open-loop gain
of op amp A1, then the common-mode error (CME) at the
output due to this effect will be approximately
1 +&L.
1
OP-227
19m
1 +_d_
A02
1
A01
2
7
--~--
~
25n
GAIN
The high open-loop gain of the OP-227 is very important to
achieving high accuracy in the two op-amp instrumentation
amplifier configuration. Gain error can be approximated by
CME-
•
VCM - 1/2Vd
II
~
":"
In this instrumentation amplifier configuration, error due to
CMR effect is directly proportional to the CMR match of the
op amps. Forthe OP-227 this .:lCMR isa minimum of97dBfor
the "G" and 110dB for the "E" grade. A .:lCMR value of 100dB
and common-mode input range of ±2.SV indicates a peak
input-referred error of only ±2S!'V. Resistor matching is the
other factor affecting CMR. Defining Ad as the differential
gain of the instrumentation amplifier and assuming that R"
R2, R3and R4are approximately equal (RNWili bethe nominal
value), then CMR for this instrumentation amplifier configuration will be approximately Ad divided by 4.:lR/R N. CMR at
differential gain of 100 would be aadB with resistor matching
of 0.1%. Trimming R, to make the ratio R3/R4 equal to R2/R,
will raise the CMR until limited by linearity and resistor
stability considerations.
v+
e--
son
(1) CMR of the op amps
(2) Matching of the resistor network ratios (R3/R4 = R2/R,)
Gain Error -
ADJUST
OFFSET
eMR
10kn
01%
2R,)Vd
(
V,=-1+--+VCM
Ro 2
VCM
Ao,
VO=V2-V,=(1
For Ad/Ao,,~1, this simplifies to (2 AJ Ao,) x VCM.lftheop amp
gain is 700VlmV, VCM is 2.SV, and Ad is set to 700, then the error
at the output due to this effect will be approximately SmV.
+~:')Vd
VO=AdVd
5-237
1/86, Rev. A
------I~
OP-227 DUAL LOW-NOISE LOW-OFFSET INSTRUMENTATION OPERATIONAL AMPLIFIER
The differential gain Ad is 1 +2R1/Roand the common-mode
input VCM is rejected.
FIGURE 3: Three-Op-Amp Instrumentation Amplifier Using
OP-227 and OP-27
While output error due to input offsets and noise are easily
determined. the effects of finite gain and common-mode
rejection are more subtle. CMR of the complete instrumentation amplifier is directly proportioned to the match in CMR of
the input op-amps. This match varies from 97dB to 110dB
minimum for the OP-227. Using 100dB. then the output
response to a common-mode input VCM would be:
R1
Vo
[VolcM = Ad VCM X 10-5
=
(1 + 2RRa1 ) Vd
RO
Va
R1
CMRR of the instrumentation amplifier. which is defined as
20 log lOAd/ACM. is simply equal to the aCMRR of the OP-227.
While this aCMRR is already high. overall CMRR of the complete amplifier can be raised by trimming the output stage
resistor network.
V2 R2
VCM + 1/2V d
0----1
R2
Finite gain of the input op-amps causes a scale factor error
and a small degradation in CMR. Designating the open-loop
gain of op-amp A1 as A01. and op-amp A2 as A02. then the
following equation approximates the output:
[AdVd+ R;
2R1 ( 1 1)
1
A01- A 02 VCM
This can be simplified by defining Ao as the nominal openloop gain and aAo as the differential open-loop gain. Then
The unity-gain output stage contributes negligible error to
the overall amplifier. However. matching of the four-resistor
R2-network is critical to achieving high CMR. Consider a
worst-case situation where each R2 resistor has an error of
±aR2. If the resistor ratio is high on one side and low on the
other. then the common-mode gain will be 2aR 2/R2. Since
the output stage gain is unity. CMRR will then be R2/2aR2. It
is common practice to trim the R2 resistor connected to
ground to maximize overall CMRR for the total instrumentation amplifier circuit.
The high open-loop gain of each amplifier within the OP-227
(700.000 minimum at 25° C into RL ~ 2k) assures good gain
accuracy even at high values of Ad. The effect of finite openloop gain on CMR can be approximated by:
This three-op-amp instrumentation amplifier configuration
provides excellent performance over a wide gain range. A
gain range of 1 to 2000 is practical and CMR of over l20dB
is achievable.
Vo -
1
1+!3.!U_+_l_)
Ro \A01
A02
CMRR_ A 02
!1Ao
If aAo/ Ao were 6% and Ao were 600.000. then the CMRR due
to finite gain of the input op-amps would be approximately
l40dB.
5·238
1/86, Rev. A
OP-400
QUAD LOW-OFFSET LOW-POWER
OPERATIONAL AMPLIFIER
Precision Monolithics Inc.
ADVANCEPRODUCTINFO~TION
FEATURES
•
•
•
•
•
•
•
GENERAL DESCRIPTION
Low Input Offset Voltage ••••••••.•••.•.• 100llV Max
Low Input Offset Voltage Drift ••.••••.•• O.5IlVloC Max
High Open-Loop Gain ••.•••••••••••• 2000VlmV Min
Low Input Bias Current ••••.•••••••••••.••• 1nA Max
Low Noise Voltage Oensity ...•••.• 12nVI JHZat 1kHz
Low Supply Current (per Amplifier) ••••••• 700llA Max
Pin Compatible to LM148, LM348, RM4156, and HA4741
with Improved Performance
ORDERING INFORMATIONt
PACKAGE
TA = 25°C
VosMax
(IlV)
HERMETIC
DIP
14·PIN
100
100
300
300
OP400AY'
OP400EY
OP400BY'
OP400FY
PLASTIC
DIP
14·PIN
OPERATING
TEMPERATURE
RANGE
MIL
INO
MIL
INO
OP400EP
OP400FP
The OP-400 is a monolithic quad operational amplifier that
combines precision performance and low power consumption.
This precision is guaranteed by an input offset voltage of less
than 100llV with a drift of under 0.5IlVloC. an input offset current
below 0.2nA, and an open-loop gain of over 2 million into a 2k!l
load. In addition, the OP-400 has an input bias current of less
than 1nA and a CMRR and PSRR of over 115dB. The OP-400
meets low power requirements by drawing less than 700llA of
supply current per amplifier. Voltage noise density of the OP-400
is a low 12nV/JRZat 1kHz.
The OP-400 is pin compatible with the LM148, LM348, RM4156,
and HA4741 op amps and can be used to improve systems using
these devices. It is an ideal choice for applications where multiple
op amps are required and precision performance and low power
consumption is critical.
PIN CONNECTIONS
• For devices processed In total compliance to MIL·STD-883. add 1883 after part
number Consult factory for 883 data sheet
t All commercial and Industrial temperature range parts are available With burn-In
For ordering Information see 1986 Data Book. Seellon 2
14·PIN HERMETIC DIP
(V·Suffix)
14·PIN PLASTIC DIP
(P·Suffix)
ELECTRICAL CHARACTERISTICS at Vs = ±15V. TA = 25°C. unless otherwise noted.
OP·400A/E
MIN TYP MAX
Op·400B/F
MIN TYP MAX
UNITS
vas
100
300
",V
InputOOset
Current
los
02
0.5
nA
Input Bias
Current
Ie
3
nA
Input Noise
Voltage DenSity
en
Input Voltage
Range
IVR
PARAMETER
SYMBOL
Input Offset
Voltage
Common-Mode
Relectlon RatiO
Power Supply
Relectlon RatiO
Large-Signal
Vo~ageGaln
CONDITIONS
fo~
12
1kHz
12
nV/JHz
±12
±12
V
CMRR
VCM~
±12V
115
115
dB
PSRR
Vs ~ ±5Vto ±18V
18
18
",VN
Ava
RL ", 10kO
RL "'2kO
5000
2000
2500
1000
V/mV
This advance productlnlormatlon describes a product In development at the time 01 this printing. Final specilications may vary. Please contact
local •• Ie. ollice or distributor lor IInal dat. sheet.
5-239
1/86, Rev. A
II
------I1fMD
OP-400 QUAD LOW-OFFSET, LOW-POWER OPERATIONAL AMPLIFIER -
ADVANCE INFORMATION
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, TA = 25°C, unless otherwise noted. (Continued)
OP-400A/E
PARAMETER
SYMBOL
CONDITIONS
MIN
Output Voltage
Swing
Vo
RL~ 10k!}
±12
Gain Bandwidth
Product
GBW
Supply Current
(All Amplifiers)
ISY
Slew Rate
SR
TYP
OP-400B/F
MAX
MIN
TYP
MAX
±12
UNITS
V
MHz
No Load
2
0.3
5-240
2.8
2.8
0.3
mA
VI",s
1/86, Rev. A
OP-420
QUAD MICROPOWER
OPERATIONAL AMPLIFIER
Precision MOI1olithics Inc.
FEATURES
•
•
•
•
•
•
•
•
•
power single operational amplifier. A Darlington PNP input
stage allows the input common-mode voltage to include V-.
The wide input range combined with low power-supply drain
(-40/-lA/section at 5Vj, provides a unique solution for designs
requiring high functional density and portable operation.
Applications include two-wire transmitters for process
control loops, battery-operated remote-line filters, signal
preconditioning amplifiers, and a variety of multiple-gain
block arrays.
Low Supply Current ........... 200/-IA Max@Vs=+5V
Single-Supply Operation ................ + 5V to + 30V
Dual-Supply Operation ................ ±2.5V to ±15V
Low Input Offset Voltage .................. 500/-IV Typ
Low Input Offset Voltage Drift ............ 5/-1V/oC Typ
High Common-Mode Input Range ... V- to (V + - 1.5V)
High CMRR .............................. 100dB Typ
High Open-Loop Gain ................. 1100V/mV Typ
LM 148 Pinout
For micropower applications requiring offset nulling, see the
OP-20, OP-21 and OP-22 data sheets.
ORDERING INFORMATIONt
PACKAGE
TA = 25°C
Vos MAX
(mV)
HERMETIC
DIP
14-PIN
2.5
2.5
4.0
4.0
6.0
OP420BY'
OP420FY
OP420CY'
OP420GY
OP420HY
PIN CONNECTIONS
LCC
OPERATING
TEMPERATURE
RANGE
OP420CRC/883
MIL
IND
MIL
IND
COM
• For devices processed in total compliance to MIL-STD-883, add /883 after
part number. Consult factory for 883 data sheet.
t All commercial and industnal temperature range parts are available with
burn·m. For ordering information see 1986 Data Book, Section 2.
14-PIN HERMETIC DIP
(Y-Sufflx)
GENERAL DESCRIPTION
The OP-420 quad micropower operational amplifier is a
single-chip quad patterned after the OP-20 precision micro-
OP-420CRC/883
20-LEAD LCC
(RC-Sulflx)
SIMPLIFIED SCHEMATIC (1/4 Shown)
-IN
+IN
0--+---+----1_----1---_..1
5-241
1/86, Rev. A
-----------I1fHD
OP-420 QUAD MICROPOWER OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS (Note 2)
OP-420HY ............................. O°C to +70°C
DICE Junction Temperature (TJ) ••••••• -65°C to +150°C
Supply Voltage ................................... ± 18V
Internal Power Dissipation (Note 1) .............. 500mW
Differential Input Voltage .......................... ±30V
Input Voltage ............................ Supply Voltage
Output Short-Circuit Duration ................ Continuous
(One Amplifier Only)
Storage Temperature Range ........... -65°C to + 150°C
Lead Temperature Range (Soldering. 60 sec) ...... 300°C
Operating Temperature Range
OP-420BY. OP-420CY ............... -55°C to +125°C
OP-420FY. OP-420GY ................ -25°C to +85°C
NOTES:
1 See table for maximum ambient temperature rating and derating factor.
PACKAGE TYPE
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
100·C
10.0mW/·C
14-PIn Hermetic DIP (V)
2. Absolute maximum ratings apply to both packaged parts and DICE. unless
otherwise noted.
ELECTRICAL CHARACTERISTICS at Vs = ±15V. TA = +25°C. unless otherwise noted.
OP-420B
OP-420F
MAX
Vs = ±2.5V to ± 15V
0.5
25
los
Vs= ±2.5V to ±15V
0.5
15
IB
Vs= ±2.5V to ±15V
9
20
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Input Offset Current
(Note 1)
Input Bias Current
(Note 1)
MIN
OP-420C
OP-420G
TYP
PARAMETER
MIN
TYP
OP-420H
MAX
MIN
TYP
MAX
UNITS
4
2
6
mV
0.8
25
1.2
6
nA
12
30
18
40
nA
Input NOise Voltage
Density
fo= 10Hz
fo= 100Hz
50
50
50
Input Noise Current
Density
fO= 10Hz
fo= 100Hz
0.12
0.12
0.12
V+=+5V. V-=OV
Vs =±15V
Input Voltage Aange
IVA
Common-Mode
Aejection Aatio
CMAA
Power Supply
Aejection Aatio
PSAA
Vs = ±2.5V to ± 15V; &
V-= OV. V+= 5V t030V
Large-Signal
Voltage Gain
Avo
AL = 25kO.
Vo= ±1OV
Slew Aate
SA
V+=+5V. V-=OV
Closed-Loop
Bandwidth
BW
ISY
Vs = ±2.5V. No Load
Vs = ±15V. No Load
0/3.5
-15/13.5
v
83
100
80
96
76
90
83
100
80
96
76
90
dB
10
600
AVCL = +1.0
AL = 10kO
V + = 5V. V- = OV.
A L = 10kO
Vs= ±15V.
AL = 25kO
Output Voltage
Swing
Supply Current
(Four Amplifiers)
OV'" VCM '" 3.5V
Vs= ±15V
-15V", VCM '" 13.5V
0/3.5
-15/13.5
0/3.5
-15/13.5
nVlVHZ
20
30
1100
400
50
900
30
200
80
JIoVIV
800
VlmV
0.05
0.05
0.05
VII's
150
150
150
kHz
0.7/4.1
0.8/4.0
0.9/3.8
±14.0
±14.0
±13.8
V
140
330
200
360
170
360
300
460
200
390
400
600
JIoA
NOTE:
1. IBandlosaremeasuredatVCM=O
5-242
1/86, Rev. A
~
OP-420 QUAD MICROPOWER OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs= ±15V, -55°C $ TA$+125° C for OP-420B and
for OP-420F and OP-420G, and 0° C $ TA $ + 70° C for OP-420H, unless otherwise noted.
OP-420B
OP-420F
PARAMETER
SYMBOL
CONDITIONS
Average Input Offset
TCVos
Voltage Drift (Note 1 )
Unnulled
Input Offset Voltage
Vas
Vs = ±2.5V to ± t5V
Input Offset CUrrent
(Note 2)
los
Vs =±2.5Vto±15V
Input Bias Current
(Note 2)
IB
Vs = ±2.5V to ± 15V
IVR
V+=+5V. V-=OV
Vs =±t5V
CMRR
V+ = +5V. V- = OV.
OV,; VCM'; 3.2V
Vs =±15V.
-15V'; VCM $ 13.2V
Input Voltage Range
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
PSRR
Vs = ±2.5V to ±15V
and V-=OV. V+=5V
t030V
Large-Signal
Voltage Gain
Ava
Vs = ±15V. RL = 50kO.
Va = ±10V
Output Voltage
Swing
Va
V+=5V.V-=OV.
RL = 20kO
Vs=±15V.
RL = 50kO
Supply Current
(Four Amplifiers)
ISY
Vs = ±2 5V. No Load
Vs = ±15V. No Load
MIN
TYP
OP-420C, -25°C$ TA$+85°C
OP-420C
OP-420G
MAX
MIN
TYP
OP-420H
MAX
to
15
3.5
5.5
MIN
TYP
MAX
UNITS
15
25
J1.V/'C
75
mV
nA
40
30
0/32
-15/13.2
0/3.2
-15/13.2
60
0/32
-15/13.2
nA
V
76
96
73
92
73
86
76
96
73
92
73
86
dB
II
~
~
.......
~
15
300
25
50
200
800
80
100
650
1.0/38
0.9/3.9
40
100
400
J1.VIV
V/mV
11/3.6
V
±138
±13.8
170
390
300
500
±13.6
210
420
400
640
250
500
600
800
J1.A
::sPo.
~
~
0.......
~
~
Po.
0
NOTES:
1. Sample tested.
2. lsand los are measured at VCM = O.
5-243
1/86, Rev. A
----------l~ OP·420 QUAD MICROPOWER OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
1. OUTPUT 1
2. INVERTING INPUT 1
3. NONINVERTING INPUT 1
4. V+
5. NONINVERTING INPUT 2
6. INVERTING INPUT 2
7. OUTPUT 2
8. OUTPUT 3
9. INVERTING INPUT 3
10. NONINVERTING INPUT 3
11. V12. NONINVERTING INPUT 4
13. INVERTING INPUT 4
14. OUTPUT 4
For addilional DICE informalion refer 10
1986 Dala Book, Section 2.
DIE SIZE 0.092 X 0.086 Inch, 7912 sq. mils
(2.34 X 2.18 mm, 5.10 sq. mm)
WAFER TEST LIMITS at VS= ±15V,
TA
= 25°C, unless otherwise noted.
OP·420N
OP·420G
OP·420GR
LIMIT
LIMIT
LIMIT
UNITS
Vs = ±2 5V to ±15V
25
4
6
mVMAX
los
Vs = ±2.5V to ±15V, (Note 1)
1.5
25
18
Vs = ±2.5V to ±15V, (Note 1)
20
30
40
nAMAX
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Input Offset Current
Input Bias Current
Input Voltage Range
IVR
Common·Mode Rejection Ratio
CMRR
V+=+5V, V-=OV
OV 5 VCM 5 3.5V
Vs = ±15V, -15V 5 VCM 513 5V
Power Supply Rejection Ratio
PSRR
Vs = ±2.5V to ±15V
V- = OV, V+ = +5V to +30V
Large·Signal Voltage Gain
Avo
RL = 25kll, Vo =±10V
Vo
V+=+5V, V-=OV
RL = 10kll
Vs= ±15V
RL = 25kll
ISY
No Load, (Four Amplifiers)
Output Voltage Swing
Supply Current
nAMAX
-15/13.5
-15/135
-15/13.5
V MIN
83
83
80
80
76
76
dBMIN
30
50
80
",V/v MAX
600
400
200
VlmV MIN
0.7/4.1
08/4.0
09/3.8
VMAX
±14.0
±14.0
±13.8
VMIN
360
460
600
",A MAX
NOTES:
1. 18 and lOS are measured at VCM = O.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging IS not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
5·244
1/86, Rev. A
------------1~ OP-420 QUAD MICROPOWER OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
CLOSED-LOOP GAIN
vs FREQUENCY
INPUT OFFSET CURRENT
vs TEMPERATURE
120
100
600
;
IIII IIIII
AVCL = 100
~40
c:: 400
il
E
300
r-.
AVCL = 1
o
111111
vV
;;
100
I
15
15
150
15k
15k
150k
-100
-50
50
100
150
-100
TEMPERATURE (OC)
FREQUENCY (Hz)
MAXIMUM OUTPUT VOLTAGE
vs LOAD RESISTANCE
17
r----i'-
L
~ 200
r-.
i
-
~S' ;,5)
/
>-
IIII I I
-20
015
Ii
~
I~~~~ .I,~I
20
,........
500
~
AVCL = 1000
Z
12
<
TA = 2SOC
80
~60
14
v~. ,,~v
1111111
Vs = ±15V
RL '" 25kD
100
INPUT BIAS CURRENT
vs TEMPERATURE
-so
50
100
150
TEMPERATURE (CC)
INPUT CURRENT NOISE
DENSITY (in) vs FREQUENCY
INPUT VOLTAGE NOISE
DENSITY (en) vs FREQUENCY
10
1 1.1
JJ,I,H
TA = 2!fc
~
~
~
iii , 00
~
o
"-
w
~
V
is
z
>z
V
/
1k
il
>i<
II III
V
II III
/'
10k
100k
LOAD RESISTANCE tn)
t--
~ 010
VS =+5,OV
;;
10 L-LUJ.lill'--LUJ..UJJL..LUJ.lillL..LUJ.lillJ
o,
10
100
1000
FREQUENCY (Hz)
SMALL-SIGNAL TRANSIENT RESPONSE
001
01
10
10
100
1000
FREQUENCY (Hz)
LARGE-SIGNAL TRANSIENT RESPONSE
OUTPUT
5-245
1/86, Rev. A
OP-421
QUAD LOW-POWER
OPERATIONAL AMPLIFIER
PreciS10n MOl1olithics Inc.
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
The OP-421 quad low-power operational amplifier is a singlechip quad patterned after the OP-21 single operational
amplifier. The PNP input stage allows the input commonmode vOltage to include V-. Featuring a low power-supply
current (150/,A/section typical at 5V), the OP-421 offers a
unique solution for designs requiring a combination of high
function density, wide bandwidth, and low-power operation.
Applications for the OP-421 include low-power active filters,
battery-operated remote line filters, and signal preconditioning amplifiers. In addition, the ever-present problem of
crossover distortion in low-power devices is eliminated by a
unique double-buffered output section.
Low Supply Current .. ...................... 1mA Max
Slew Rate .............................. O.25V//,s Min
Single Supply Operation ................ +5V to +30V
Low Input Offset Voltage .................. 500/,V Typ
Low Input Offset Voltage Drift .......... 10/,V/oC Max
High Common-Mode Input Range ... V- to V+ (-1.5V)
High CMRR .............................. 100dB Typ
High Open-Loop Gain .. ................ 400V/mV Typ
Single-Chip Monolithic Construction
Pin Compatible With LM124, LM148, and OP-11
ORDERING INFORMATIONt
TA = 25°C
VosMAX
(mV)
HERMETIC
DIP
14-PIN
OPERATING
TEMPERATURE
RANGE
2.5
2.5
4
4
OP421 BY'
OP421FY
OP421CY'
OP421GY
OP421HY
MIL
IND
MIL
IND
COM
6
PIN CONNECTIONS
• For devices processed In total compliance to MIL'STD-883, add /883 after
part number Consult factory for 883 data sheet.
tAil commercial and Industrial temperature range parts are available with
burn-In For ordering mformatlon see 1986 Data Book, Section 2
14-PIN HERMETIC DIP
(V-Suffix)
SIMPLIFIED SCHEMATIC (1/4 Shown)
v'
-IN
"N
O---+----+-----+--------1f---'
5-246
1/86, Rev. A
-~
---
IfM!) OP-421 QUAD LOW-POWER OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
(Note 2)
Supply Voltage •••••••••••••••••••••••.••••••••••• ± 18V
DICE Junction Temperature (TJ)
.......
-6S·C to +1S0·C
Internal Power Dissipation (Note 1) •••••••••••••• SOOmW
Differential Input Voltage •••••••••••••••••••••••••• ±30V
NOTES:
1. See tabJe for maximum ambient temperature rating and derating factor
Input Voltage •••••••••••••••••••••••••••• Supply Voltage
Output Short-Circuit Duration •••••.••••••••• Continuous
(One Amplifi!!r Only)
-6S·C to +1S0·C
Storage Temperature Range •••••••••••
PACKAGE TYPE
Lead Temperature Range (Soldering, 60 sec) •••••• 300·C
-SS· C to +12S·C
OP-421 FY, OP-421 GY •••••••••••••••• -2S·Cto+8S·C
OP-421HY • • • • • • • • • • • • • • • • • • • • • • • • • • • •• O· C to + 70· C
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Input Offset Current
Input Bias Current
Input NOise Voltage
Density
l00'C
10.0mW/'C
2. Absolute maximum ratings apply to both packagad parts and DICE. unless
otherWise noted
±1SV, TA = +2S·C, unless otherwise noted.
OP-421B
OP-421F
PARAMETER
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
14-Pln Hermetic DIP (V)
Operating Temperature Range
OP-421 BY, OP-421 CY •••••••••••••••
ELECTRICAL CHARACTERISTICS at Vs =
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
MIN
OP-421C
OP-421G
MAX
Vs =±2.5Vto±15V
0.5
2.5
los
Vs = ±2.5V to ± 15V
0.6
50
20
10
Ie
Vs= ±2 5V to ±15V
20
50
50
80
en
fo= 10Hz (Note 1)
fo= 100Hz (Note 1)
20
15
40
30
20
15
40
30
Input Noise Current
Density
in
fO= 10Hz (Note 1)
fo= 100Hz (Note 1)
0.3
02
0.6
0.4
0.3
02
06
0.4
Input Voltage Range
IVR
V+=+5V. V-=OV
Vs =±15V
Common-Mode
Rejection Ratio
CMRR
V+=+5V. V-=OV.
OVSVcM S+3.5V
Vs=±15V.
-15VSV CM S+13.5V
Power Supply
Rejection Ratio
PSRR
Vs = ±2.5V to ±15V; &
V-=OV. V+= 5Vto30V
Large-Signal
Voltage Gai n
Avo
Vo=±10V
RL = 10kO
Output Voltage
Swing
Vo
V+ = 5V. V-= OV
RL = 5kO
Vs=±15V.
RL = 10kO
Closed-Loop
Bandwidth (Note 2)
BW
AveL =+1.0.
RL = 10kO
Supply Current
(Four Amplifiers)
ISY
Vs = ±2.5V. No Load
Vs = ± 15V. No Load
0/3.5
-15/13.5
MIN
TVP
OP-421H
TYP
MAX
MIN
4
0/3.5
-15/13.5
MAX
UNITS
......
2
6
mV
50
20
nA
:::l
~
100
150
nA
20
15
40
30
nV/..jHZ
0.3
0.2
0.6
0.4
pA/..jHZ
0/3.5
-15/13.5
V
83
100
80
96
76
90
83
100
80
96
76
90
200
30
20
100
400
50
200
30
100
07/4.0
0.8/39
0.9/38
±14
±139
±138
80
,.V/v
VlmV
200
V
10
1.9
0.6
1.2
1.0
10
18
1.9
0.7
14
Slew Rate
SR
(Note 1)
0.25
05
025
Channel Separation
CS
(Note 1)
100
120
100
1.0
1.5
2.3
1.9
0.9
18
MHz
2.0
30
mA
05
0.25
05
VI,.s
120
100
120
dB
NOTES:
1. Sample tested.
2. Guaranteed by design.
5·247
-
.
__ . - - - - - - - . _
..
_ - - - - - - - _ . - ..
---
~
~
~
0....,
~
~
~
dB
10
ffi
TYP
1/86, Rev. A
0
IEHD
OP-421 QUAD LOW-POWER OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, -55 0 C:o; TA:O; + 125 0 C for OP-421 Band OP-421 C, -25 0 C:O; TA:O; +85 0
for OP-421 F and OP-421 G, and 00 C:O; TA:O; + 70 0 C for OP-421 H, unless otherwise noted.
OP-421B
OP-421F
PARAMETER
SYMBOL
MIN
CONDITIONS
TYP
OP-421C
OP-421G
MAX
Average Input Offset
TCVos
Voltage Drift (Note 1 )
Input Offset Voltage
Vos
Input Offset Current
los
Input Bias Current
18
I nput Voltage Range
IVR
Common-Made
Rejection Ratio
CMRR
Power Supply
Rejection RatiO
PSRR
Large-Signal
Voltage Gain
Avo
Output Voltage
Swing
Vo
V+=+5V. V-=OV
Vs = ±15V
1.6
70
25
MAX
15
1.8
5.5
3.0
60
= +5V, V- = OV.
OV" VCM " +3 2V
Vs =±15V.
-15V"VCM ,,+13.2V
RL = 10kO
UNITS
10
15
p.VI'C
3
7.5
mV
15
6.0
30
nA
125
140
230
nA
0/3.2
-15/13.2
V
96
74
94
73
86
78
96
74
94
73
86
dB
15
15
100
RL = 20kO
TYP
78
Vs= ±2 5V to ±15V; &
V-=OV. V+=5Vt030V
Vo= 10V
MIN
MAX
0/3.2
-15/13.2
0/3.2
-15/13.2
V+=5V. V-=OV
50
50
25
25
50
200
80
80
100
40
40
50
0.8/3.9
09/3.8
1.0/3.7
±13.8
±137
±13.7
100
100
100
p.VIV
VlmV
V
Vs= ±15V.
RL = 20kO
ISY
3.5
OP-421H
TYP
10
= ±2.5V to ±15V
Vs = ±2.5V to ± 15V
Vs = ±2.5V to ± 15V
Vs
V+
Supply Current
(Four Amplifiers)
MIN
C
Vs = ±2.5V, No Load
Vs = ± 15V, No Load
12
2.0
0.68
1.5
2.5
0.68
1.5
2.5
2.0
3.2
0.68
2.0
3.2
3.0
4.0
mA
NOTE:
1 Sample tested.
BURN-IN CIRCUIT
-18
v
13
12
11
10
v-
v+
GND
+18 V
5-248
1/86, Rev. A
-----------I~ OP-421 QUAD LOW-POWER OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
DIE SIZE 0.086 X 0.092 Inch, 7912 sq. mils
(2.34 X 2.18 mm, 5.10 sq. mm)
OUTPUT 1
INVERTING INPUT 1
NON INVERTING INPUT 1
V+
NON INVERTING INPUT 2
INVERTING INPUT 2
OUTPUT 2
OUTPUT 3
INVERTING INPUT 3
NONINVERTING INPUT 3
II
VNON INVERTING INPUT 4
INVERTING INPUT 4
OUTPUT 4
i:2
For addilional DICE informalion refer to
1986 Data Book, Section 2.
~
......
~
WAFER TEST LIMITS at Vs= ±15V,
TA =
25°C, unless otherwise noted.
OP-421N
LIMIT
OP-421G
LIMIT
OP-421GR
LIMIT
UNITS
2.5
4
6
mV MAX
10
20
nAMAX
50
SO
150
nAMAX
-15113.5
-15113.5
-15113.5
VMIN
CMAA
V+=+5V, V-=OV
OV:5 VCM :5 +3.5V
Vs =±15V,
-15V:5VCM :5+13.5V
S3
SO
76
dBMIN
PSAA
Vs= ±2.5V to ±15V; and
V- = OV, V+ = +5V to 30V
30
50
SO
!'VIV MAX
Ava
Vo =±10V
AL = 20kO
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
Vs = ±2.5V to ± 15V
Input Offset Current
los
Vs = ±2.5V to ±15V
Input Bias Current
Ie
Vs = ±2.5V to ±15V
Input Voltage Aange
IVA
Common-Mode
Aeiection Aatio
Power Supply
Rejection Ratio
Large-Signal
Voltage Gain
::sp.,
~
Output Voltage Swing
Va
V+ = +5V, V- = OV, AL = 5kO
Vs = ± 15V, AL = 10kO
Supply Current
(Four Amplifiers)
ISY
Vs = ± 2.5V, No Load
Vs = ± 15V, No Load
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ± 15V,
Input Noise Voltage
Density
Closed-Loop
Bandwidth
SYMBOL
CONDITIONS
en
fo= 10Hz
fo= 100Hz
BW
AVCL =+1.0
AL = 10kO
~
~
p.,
0
200
200
100
VlmV MIN
0.714.0
±14
0.SI3.9
±13.9
0.913.S
±13.S
VMIN
1.0
I.S
1.5
2.3
2.0
3.0
mAMAX
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations In assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
PARAMETER
~
0
......
TA =
+25° C, unless otherwise noted.
OP-421N
TYPICAL
OP-421G
TYPICAL
OP-421GR
TYPICAL
20
15
20
15
20
15
nVIJHZ
19
1.9
1.9
MHz
0.5
0.5
Vi!,s
120
120
dB
Slew Aate
SA
0.5
Channel Separation
CS
120
5-249
UNITS
1/86, Rev. A
-----------I1fMD
OP·421 QUAD LOW·POWER OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN·LOOP
FREQUENCY RESPONSE
-..,
'"
60
""
RL = 2kn
10
'\
100
'\
20
1\
10
1 - - - - + - - - - i -"R'L-=.:-;2"'Ok:c",---!
vl.~ lL
15
40
10
120
20
100
lk
10k
lOOk
FREQUENCY (Hz)
80 L -_ _ _
1M
10M
15
POSITIVE
Wj1llllc
SWING
___
___
10k
1M
lOOk
FREQUENCY (Hz)
SUPPLY CURRENT vs
SUPPLY VOLTAGE
GAIN BANDWIDTH vs
SUPPLY VOLTAGE
26
1.]l.I,VS-',5V
NEGATIJ~II
IV
1\
i'-lk
30
10
20
TOTAL SUPPLY VOLTAGE (VOLTS)
OUTPUT SWING vs
OUTPUT LOAD
\
1----+----\-----1
~
80
r----..,-----,-------,
~
100
140
~
120
OUTPUT SWING
vs FREQUENCY
OPEN·LOOP GAIN
vs POWER SUPPLY VOLTAGE
24
SWING
10
22
I
20
V
.
,:
o
10
100
lk
10k
_55°C
m~r
-
r-
18
I-:"
16
'"
~
V
-
14
lOOk
1M
10
LOAD RESISTANCE 1m
20
30
±5
POWER SUPPLY REJECTION
RATIO vs FREQUENCY
±75
±1O
±125
SUPPL Y VOLTAGE (VOLTS)
SUPPLY VOLTAGE (VOLTS)
COMMON·MODE REJECTION
RATIO vs FREQUENCY
120
100
it'
80
11'\
60
40
40
H-tttttlt-+Httltlt-t-H-tttffiH-ttfI11lk:-H-tHtIH
20
I
10
100
lk
10k
lOOk
o lk
lk
10k
lOOk
1M
FREQUENCY (Hz)
FREQUENCY (Hd
5·250
1/86, Rev. A
-----------l{fMD OP-421 QUAD LOW-POWER OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE FOLLOWER
LARGE-SIGNAL RESPONSE
VOLTAGE FOLLOWER
SMALL-SIGNAL RESPONSE
OUTPUT
OUTPUT
5OmV/DIV
, VOLT/OIV
2~s/DIV
5,us/OIV
INPUT
INPUT
Vs = av, +15V
CL = 50pt
Vs" av, +15V
RL'" lOkn
TA = 25°C
CL = 50pf
RL = 10kfl.
TA '" 2soC
NOISE CHARACTERISTICS
INPUT NOISE VOLTAGE
DENSITY vs FREQUENCY
INPUT NOISE CURRENT
DENSITY vs FREQUENCY
1000
10
@
-"'
.~100 r-...
>
~c
:Ji
0
Z
w
10
"!:;
~
"-
0
'"
~
1
'"
r---..
!$
00 1
01
10
01
10
100
lk
10k
10
100
lk
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
1/86, Rev. A
5-251
~~~~---~
---~-
~
~-
~
~~-
PM.108A/PM.2108A
LOW·INPUT·CURRENT OPERATIONAL AMPLIFIERS
PM·I08A/PM·208A/PM·308A/PM·I08/pM·208/pM·308/pM·2108A/PM·2108
PrecIsion Mo]]o]ithics Inc.
FEATURES
•
•
•
•
•
•
•
•
•
•
directly interchangeable with industry-standard types,
Precision Monolithics' advanced processing provides the
PM-108A series with a significant improvement in input noise
voltage. Low supply current drain over a wide power-supply
range makes the PM-108A attractive in battery operated and
other low-power applications. The low bias current provides
excellent performance with piezoelectric and capacitive
transducers and in such high-impedance circuits as longperiod integrators and sample-and-holds. For improved
performance see OP-08, OP-12, OP-20, OP-21 , and OP-22.
Low Offset Current ...................... 200pA Max
Low Bias Current ........................... 2nA Max
Low Power Consumption •......... 18mW Max @ ± 15V
Wide Supply Range ..................... ± 3V to ± 20V
High Power-Supply Rejection Ratio ......... 96dB Min
Low Offset Voltage Drift ................. 5p.V/oC Max
High Common-Mode Input Range .•...... ± 13.5V Min
High Common-Mode Rejection Ratio . . . . . . .. 98dB Min
MIL-STD-883 Processing Models Available
Silicon-Nitride Paulvatlon
The PM-2108A contains two superbeta, PM-108A op amps
in a single 16-pin DIP. Compared to the Single PM-108A
types, this model offers higher packaging density, closer
thermal tracking between the two amplifiers, and reduced
insertion cost.
GENERAL DESCRIPTION
The PM-108A series of precision operational amplifiers
feature very low input offset and bias currents. Although
ORDERING INFORMATIONt
PACKAGE
HERMETIC
TA = 25°C
VosMAX
(mV)
TO·99
a·PIN
a·PIN
16-PIN
0.5
0.5
05
2.0
2.0
7.5
PM108AJ'
PM208AJ
PM308AJ
PM108J'
PM208J
PM308J
PM108AZ'
PM208AZ
PM308AZ
PM108Z'
PM208Z
PM308Z
PM2108AO'
PLASTIC
DIP
a·PIN
DIP
OPERATING
TEMPERATURE
RANGE
LCC
PM108ARC/883
MIL
INO
COM
MIL
INO
COM
PM308AP
PM21080'
'For devices processed In total compliance to MIL·STD·883, add 1883 after
part number. Consult factory for 883 data sheet
tAli commercial and industrial temperature range parts are available with
burn·,n For ordering information see 1986 Data Book. Section 2.
SIMPLIFIED SCHEMATIC (Pin numbers for PM-108 only. Circuit Is 1/2 2108.)
111
caMP
181
COMP
r------_--1r--+---+-_--.......--------_---o V+
171
R5
L..--I--"'--0161
OUTPUT
131
+
R6
121
~------~-~~--------~--_4-_4-
5-252
__
~--__o~1
V-
1/86, Rev. A
_ _ _ _ _ _ _--I~PM-108A1PM-2108A LOW-INPUT-CURRENT OPERATIONAL AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
PM-10BA, PM-1OS, PM-20BA, PM-20S,
NOTES:
1. Maximum package power diSSipation vs. ambient temperature
PM-210SA, PM-2108, PM-10SARC •..••••....••.•• ±20V
PM-30BA, PM-30S .............................. ± 1SV
Internal Power Dissipation (Note 1) ••.•••.•...••• 500mW
Differential Input Current (Note 2) ••••.•••••••.•. ±10mA
Input Voltage (Note 3) ............................ ±15V
Output Short-Circuit Duration ••••••..•••....•• Indefinite
Operating Temperature Range
PM-10BA, PM-1OS, PM-210SA,
PM-210S, PM-10SARC •••••••••.•••••• -55·C to +125·C
PM-20BA, PM-20S .................... -25·C to +S5·C
PM-30BA, PM-30S ...................... O·C to +70·C
Storage Temperature Range
(C-, J-, Z- or ARC-Package) •••.•••••. -65·C to +150·C
(P-Package) ......................... -65·C to +125·C
Lead Temperature Range (Soldering, 60 sec) ••.••. 300·C
ELECTRICAL CHARACTERISTICS at ±5V S
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
TO-99 (JI
80'C
7.1mW/'C
PlastIc 8-Pin DIP (PI
36'C
5.6mW/'C
HermetIc 8-PIn DIP (ZI
75'C
6.7mW/'C
HermetIc 16-Pln DIP (QI
100'C
10.0mW/'C
80'C
7.8mW/'C
PACKAGE TYPE
LCC (RCI
2
The Inputs are shunted with back-to-back dIodes for overvoltage protectIon Therefore, If a dIfferentIal input voltage In excess of tV is applied
between the Inputs, excessive current wIll flow, unless some limiting
resistance IS provided.
3. Forsupplyvoltages less than ±15V, the absolute maximum input voltage IS
equal to the supply voltage.
VsS ±20V and TA = 25·C, unless otherwise noted.
PM-108A1PM-2108A
PM-208A
PARAMETER
SYMBOL
Input OIIset Voltage
MAX
TYP
MAX
UNITS
Vos
0.3
0.5
0.7
2.0
mV
Input Offset Current
los
0.05
0.2
0.05
0.2
nA
Input Bias Current
Ie
0.8
2.0
0.8
2.0
nA
Input Resistance
RIN
(Note II
30
70
30
70
MO
Avo
Vs =±15V, VouT =±10V,
RL~ 10kO
80
300
50
300
V/mV
ISY
10UT=O, VOUT=O,
Each AmplIfIer
Supply Current
MIN
PM-108/PM-2108
PM-208
TYP
Large-Signal Voltage GaIn
CONDITIONS
03
MIN
06
0.3
0.6
mA
ELECTRICAL CHARACTERISTICS at ±5V S VsS±20V, -55· C S TAS + 125· C for PM-10SA, PM-10S, PM-210SA and PM-210S,
-25·C S TAS +S5·C for PM-20SA, PM-20S, unless otherwise noted.
PM-108A1PM-2108A
PM-208A
PARAMETER
SYMBOL
Input Offset Voltage
Vos
Average Input Offset
Voltage Drrft
TCVos
Input Offset Current
los
Average Input Offset
Current Drrft
TClos
Input Bias Current
Ie
CONDITIONS
MIN
TYP
MAX
TYP
MAX
04
1.0
10
3.0
mV
5
3
15
p.VI'C
0.1
04
01
04
nA
0.5
25
05
2.5
pA/'C
3
nA
(Note21
(Note 21
Large-Signal Voltage Gain
Avo
Vs =±15V. VouT =±10V.
RL~ 10kO
Output Voltage SWIng
Vo
Vs = ± 15V, RL = 10kO
Input Voltage Range
IVR
Vs =±15V
Common-Mode
RejectIon Rallo
CMRR
Vs= ±15V, VCM = ±13 5V
Power-Supply
RejectIon RatIO
PSRR
Vs = ±5V to ±20V
Supply Current
ISY
VOUT=O. TA = MAX,
Each AmplifIer
40
200
±13
±14
±135
96
NOTES:
1 Guaranteed by mput bias current.
2
5-253
PM-108/PM-2108
PM-208
MIN
25
200
VlmV
±13
±14
V
±135
110
UNITS
85
V
100
dB
3
15
15
100
p.VN
015
04
015
04
mA
Sample tested
1/86, Rev. A
_ _ _ _ _ _ _---l~PM-108A1PM-2108A LOW-INPUT-CURRENT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS at ±5V:5 VS:5 ±2DV and TA = 25'C, unless otherwise noted.
PM-308A
PARAMETER
SYMBOL
Inpul Offset Voltage
Input Offset Current
MIN
PM-308
TYP
MAX
TYP
MAX
UNITS
Vas
0.3
0.5
2.0
7.5
mV
lOS
02
1.0
0.2
1.0
nA
1.5
70
1.5
7.0
nA
CONDITIONS
Input Bias Current
MIN
Input Resistance
(Note 1)
10
40
10
40
MO
Large-SIgnal Voltage Gain
Ava
Vs =±15V, VouT =±10V,
R L ", 10kO
80
300
25
300
VlmV
ISY
10UT=O, VOUT=O,
Each Amplifier
Supply Current
0.8
0.3
0.8
mA
TYP
MAX
UNITS
3.0
10.0
mV
6
30
p.V/'C
0.3
1.5
nA
10
pA/'C
10
nA
0.3
ELECTRICAL CHARACTERISTICS at ±5V:5 Vs:5 ±15V and D'C:5 TA:5 HD'C, unless otherwise noted.
PM-308A
PARAMETER
SYMBOL
Input Offset Voltage
Vas
Average Input Offset
Voltage Drift
TCVOS
Input Offset Current
los
Average Input Offset
Current Drift
TCIOS
Input Bias Current
18
MIN
CONDITIONS
PM-308
TYP
MAX
0.4
0.73
MIN
(Note 1)
0.3
1.5
(Note 1)
10
2
10
Large-Signal Voltage Gain
Ava
VS =±15V, VouT =±10V,
R L ", 10kO
Output Voltage Swing
Va
Input Voltage Range
IVR
Common-Mode
Rejection Ratio
CMRR
Power-Supply
Rejection Ratio
PSRR
Vs = ±5V to ±15V
Supply Current
ISY
VOUT=O, TA = MAX,
Each AmplIfier
60
200
15
100
V/mV
Vs = ±15V, RL = 10kO
±13
±14
±13
±14
V
Vs= ±15V
±14
96
±13
80
110
3
15
V
100
15
0.23
dB
100
0.23
p.VIV
mA
NOTE:
1.
Guaranteed by input bias current.
PIN CONNECTIONS
PM-108ARC/883
COMP
B
COMPe.
7v+
-IN 2
...
+IN 3
EPOXY MINI-DIP
(P-Sufflx)
AND
8-PIN HERMETIC DIP
(Z-Sufflx)
6 OUT
5 NC
4
v- (CASE)
16-PIN HERMETIC DIP
(O-Suffix)
TO-99
(J-Sufflx)
5-254
LCC PACKAGE
(RC-Suffix)
1/86, Rev_ A
----------1lmD
PM-108A1PM-2108A LOW-INPUT-CURRENT OPERATIONAL AMPLIFIERS
APPLICATIONS INFORMATION
The PM-10BA series has very low input offset and bias
currents; the user is cautioned that printed circuit board
leakages can produce significant errors, especially at high
board temperatures. Careful attention to board layout and
cleaning procedure is required to achieve the PM-10BA's
rated performance. It is suggested that board leakage be
minimized by encircling the input pins with a guard ring
maintained at a potential close to that of the inputs. The
guard ring should be driven by a low impedance source such
as an amplifier's output or ground.
COMPENSATION CIRCUITS
STANDARD
ALTERNATE
R2
R2
R1
R1
R3
R3
~"---+---o OUTPUT
R1
Cf;;;'R1+R2 Co
>-=-----{) OUTPUT
Cs = 100pF
Co = 30pF
(IMPROVES REJECTION OF POWER SUPPLY NOISE BY A FACTOR OF TEN)
5-255
1/86, Rev. A
II
I-~-146/I-~-246
PROGRAMMABLE QUAD
OPERATIONAL AMPLIFIER
Precision Monolithics Inc.
ADVANCE PRODUCT INFORMATION
CROSS REFERENCE
FEATURES
• Wide Supply Range ................ ± 1.2V to ± 22V
• Programmable Operation
Supply Current (per Amplifier) ..... 3.511A to 1.75mA
Gain-Bandwidth Product ........... 10kHz to 4MHz
• High Gain ............................. 100dB Min'
• Low Noise ........................ 2SnVlJAZTyp'
• High Power-Supply Rejection ............ SOdB Min'
• Excellent Channel Separation ............ 120dB Typ'
• At ISET
PMI
NATIONAL
EXAR
PM1460
PM2460
LM146J
LM246J
XR-146M
XR-246N
PIN CONNECTIONS
= to",A.
ORDERING INFORMATIONt
TA = 25°C
VosMAX
(mV)"
CERAMIC
DIP
PACKAGE
OPERATING
TEMPERATURE
RANGE
5
PM1460'
PM2460
MIL
IND
6
16-PIN CERAMIC DIP
(Q-Suffix)
l6-PIN EPOXY DIP
(P-Suffix)
• For devices processed in total comphance to MIL-STD-883, add 1883 after part
number. Consult factory for 883 data sheet.
.. At ISET = 10",A.
t All commercial and Industrial temperature range parts are available With burn-m.
For ordering Information see 1986 Data Book, Section 2.
SIMPLIFIED SCHEMATIC
r-------------------~~--------~-----------ov+
~--_+----+_--~_oOUT
r------------,
I
(EXTERNAL)
v+ v+
I
I
I
I
I
I
I
II
1
RSET
RSEl
ISET
L____
_
I
I
t
TO OTHER
OPAMPS
-.
I
ISET
____
.JI
v-
This advance product information describes a product in development at the time of this printing. Final specifications may vary_ Please contact
local sales ollice or distributor for final data sheet.
5-256
1/86, Rev. A
-----l~ PM-146/PM-246 PROGRAMMABLE QUAD OPERATIONAL AMPLIFIER -
ADVANCE INFORMATION
GENERAL DESCRIPTION
The PM-146 monolithic quad operational amplifier incorporates
four independent programmable low-power amplifiers. Using two
external resistors, the supply currents may be programmed for
the optimal combination of bias and offset currents, gainbandwidth product, slew rate, input noise, and output currents.
By means of this capability, the user can achieve the required
level of speed and performance while maintaining the minimum
possible power consumption.
The PM-146 operates with a supply voltage down to ±1.5V,
which makes the amplifier well-suited to applications utilizing
battery or solar-cell supplies. Since speed is controlled by the
programming current, the slew rate and gain-bandwidth of the
PM-146 remain relatively unchanged with varying supply
voltages. The extreme versatility afforded by the PM-146's
programmability allows the device to be tailored to a wide variety
of applications, including active filters, oscillators, and generalpurpose amplifiers.
Gain-bandwidth products of 2MHz with slew rates of 1V/",s, at a
supply current drain of 1mA per amplifier, are achieved using a
programming ("set") current of 30",A. At the other end of the
spectrum, bias currents of 1nA at a supply drain of only 3.5",A per
amplifier are obtained with a set current of 0.1 ",A for applications
where speed is not important.
The pin configuration of the PM-146 matches the OP-11 pin-out,
with the addition of the two programming pins on one end. These
pins are internally protected to survive a momentary short to the
power supply rails.
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, ISET = 10",A, TA = 25°C, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
Rs s 50D
(Note 1)
Input Offset Current
los
(Note1)
Input Bias Current
18
(Note 1)
Supply Current
(4 Op Amps)
ISY
Open Loop
Voltage Gain
Ava
RL ~ 10kD,
dVOUT = ±10V
PM-146Q
MIN
TYP MAX
PM-246Q
MIN
TYP MAX
05
5
05
6
mV
20
2
100
nA
50
100
50
250
nA
14
20
14
25
mA
UNITS
~
100
1000
50
1000
V/mV
±135
±14
±135
±14
V
Input Voltage Range
IVR
(Note 2)
Common· Mode
Rejection
CMR
VCM ~ ",13 5V,
Rss 10kD
80
100
70
100
dB
PSR
Rss 10kD
80
100
74
100
dB
Va
RL", 10kD
±12
±14
±12
±14
5
20
08
12
Power· Supply
Rejection
Output Voltage SWing
Short-CirCUit
Output Current
Ise
Gain-Bandwidth
Product
GBW
Phase Margin
<1>0
Slew Rate
SR
Input NOise
1kHz
en
f~
Channel Separation
CS
RL ~ 10kD,
t.vOUT ~ OVto "'12V
Input Resistance
R'N
C'N
Voltage Density
Input Capacitance
~
~
.......
.....
::l
35
20
05
V
35
mA
12
MHz
60
04
60
Degrees
04
V/fLS
28
28
nV/VHZ
120
120
dB
10
10
MD
20
20
pF
NOTES:
1. VeM ~ OV.
2 Guaranteed by CMR test
5-257
1/86, Rev. A
~
~
0.......
~
~
~
0
-----I~ PM-146/PM-246 PROGRAMMABLE QUAD OPERATIONAL AMPLIFIER -
ELECTRICAL CHARACTERISTICS at Vs = ±15V,
ISET
= 10/-LA, -55°c:5 TA :5
ADVANCE INFORMATION
+ 125°C for PM-146Q, -25°c:5 TA :5 +85°c for
PM-246Q, unless otherwise noted.
PM-146Q
PARAMETER
Input Offset Voltage
SYMBOL
CONDITIONS
Vas
Rs$50n
(Note 1)
Input Offset Current
los
(Notel)
Input Bias Current
18
(Note 1)
Supply Current
(40pAmps)
Isv
Ava
RL = 10kn,
ilVOUT = ±10V
IVR
(Note2)
Open Loop
Voltage Gain
Input Voltage Range
Common-Mode
Rejection
Power-Supply
Rejection
Output Voltage Swing
MIN
PM-246Q
TYP
MAX
05
6
25
50
100
15
20
1.5
MIN
TYP
MAX
UNITS
05
7.5
mV
2
100
nA
50
250
nA
25
mA
50
1000
25
1000
V/mV
±13.5
±14
±13.5
±14
V
CMR
Rs$50n
VCM = ±13.5V
70
100
70
100
dB
PSR
Rs$50n
76
100
74
100
dB
Va
RL ", lOkn
±12
±14
±12
±14
V
NOTES:
1. VOM = OV.
2 Guaranteed by CMR test.
ELECTRICAL CHARACTERISTICS at Vs
= ± 15V, ISET = 1 /-LA, TA = 25°C, unless otherwise noted.
PM-146Q
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
PM-246Q
TYP
MAX
Vas
Rs$50n
(Notel)
0.5
(Note 1)
Input Bias Current
18
Supply Current
(4 Op Amps)
Isv
Gain-Bandwidth
Product
GBW
MIN
80
MIN
TYP
MAX
UNITS
5
0.5
7
mV
75
20
75
100
nA
140
250
140
300
fJ.A
100
50
100
kHz
NOTE:
1. VOM
= OV
ELECTRICAL CHARACTERISTICS at Vs
= ±1.5V, ISET = 10/-LA, TA = 25°C, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
Rs$50n
(Note 1)
Input Voltage Range
PM-146Q
IVR
(Note 2)
Common-Mode
Rejection
CMR
RS $ son
VOM = ±0.7V
Output Voltage Swing
Va
RL ", 10kn
MIN
PM-246Q
TYP
MAX
0.5
5
±O 7
MIN
0.5
±0.7
80
±0.6
TYP
UNITS
mV
V
80
±O 6
MAX
dB
V
NOTES:
1. VOM = OV.
2 Guaranteed by CMR test.
5-258
1/86, Rev. A
]E»~-155Jl/]E»~-156Jl/]E»~-157Jl
MONOLITHIC JFET- INPUT
OPERATIONAL AMPLIFIERS
Precision Monolithics Inc.
LOW SUPPLY CURRENT - PM-155A/PM-355A/pM-155
GENERAL PURPOSE - PM-156A/PM-356AjPM-156
WIDE-BANDWIDTH - PM-157A/pM-357A/PM-157
FEATURES
GENERAL DESCRIPTION
All Devices
• Low Input Bias and Offset Currents
• Low Input Offset Voltage ...................... 1.0mV
• Low Input Offset Voltage Drift .............. 3.0/lV/ o C
• Low Input Noise Current ............... O.01pAly'"HZ
• High Common-Mode Rejection Ratio ........... 100dB
The PM JFET-input series provides low input current, high
slew rate, and direct interchangeability with LF155, 156, and
157 types. These operational amplifiers use a new process
which allows fabrication of matched JFET transistors and
standard bipolar transistors on the same chip. High accuracy
and low cost make the PM JFET-input series useful in new
designs and as replacements for modular and hybrid types.
Unlike many designs, nulling the input offset voltage does
not degrade common-mode rejection ratio or input offset
voltage drift. Low input voltage noise and current noise plus a
low 1/f noise corner frequency allow these amplifiers to be
used in a variety of low noise, wide-bandwidth applications.
•
PM-155 (Only) ................... LF155 Replacement
Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2mA
•
•
PM-156 (Only) ................... LF156 Replacement
High Slew Rate ............................ 12V//lsec
Fast Settling to ±O.01% ....................... 4.0/lsec
Dynamic specifications for the PM-155 include a slew rate of
5V1 /lS, a 2.5MHz gain bandwidth product, and settling time to
within ±0.01% of final value in 5.0,..s. The PM-156 has a slew
rate of 12V/,..s and a settling time of 4.0/ls to ±0.01% of final
value.
PM-157 (Only) ................... LF157 Replacement
• Wide-Bandwidth Decompensated (AVCL = 5 Min) ... 20MHz
• High Slew Rate ............................ 45V//lsec
• Fast Settling to ±O.01% ....................... 4.0/lsec
The PM-157 is a very fast decompensated device. This results
in a 45V/,..s slew rate, a 20MHz gain bandwidth product, and a
settling time of 4.0,..s. Decompensation requires a minimum
closed-loop gain of five because of stability considerations.
For improved performance, see the OP-15/0P-16/0P-17 data
sheet. For duals, see the OP-215 data sheet.
SIMPLIFIED SCHEMATIC
5-259
1/86, Rev. A
II
--------1~
PM-155A/PM-156A/PM-157A MONOLITHIC JFET-INPUT OPERATIONAL AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
PM-155A, PM-156A, PM-157A, PM-155, PM-156, PM-157,
PM-355A, PM-356A, PM-357A ................. ±22V
Internal Power Dissipation
PM-155A, PM-156A, PM-157, PM-155, PM-156,
PM-157 .................................... 670mW
PM-355A, PM-356A, PM-357 A ................... 500mW
(Derate based on a thermal resistance of 150° C/W
junction to ambient or 45° C/W junction to case.)
Operating Temperature Range
PM-155A, PM-156A, PM-157 A, PM-155, PM-156,
PM-157 ....•.•.•....•.....•...... -55°C to +125°C
PM-355A, PM-356A, PM-357 A .•......... 0° C to + 70° C
Maximum Junction Temperature (Tj)
PM-155A, PM-156A, PM-157A, PM-155, PM-156,
PM-157 ................................•... +150°C
PM-355A, PM-356A, PM-357 A ...•..•••........ -+ 100° C
Differential Input Voltage
PM-155A, PM-156A, PM-157A, PM-155, PM-156, PM-157,
PM-355A, PM-356A, PM-357A ................. ±40V
Input Voltage
PM-155A, PM-156A, PM-157A, PM-155, PM-156, PM-157,
PM-355A, PM-356A, PM-357A ...............•. ±20V
NOTE:
The absolute maximum negative input voltage is equal to the negative power
supply voltage.
Output Short-Circuit Duration ................. Indefinite
Storage Temperature Range. . • . . . . . . .. -65° C to + 150° C
Lead Temperature Range (Soldering, 60 sec) .... +300°C
ELECTRICAL CHARACTERISTICS at ±15V::; Vs::; ±20V, -55°C::; TA ::; +125°C and THIGH = +125°C for PM-155A,
PM-156A and PM-157A, 0° C::; TA::; +70° C and THIGH= +70°C for PM-355A, PM-356A and PM-357 A, unless otherwise noted.
PM-1SSAI
PM-1S6A1
PM·1S7A
PM-3SSAI
PM·3S6A1
PM·3S7A
PARAMETER
SYMBOL
CONDITIONS
TYP
MAX
Input Offset Voltage
Vas
Rs = 500
1.4
2.5
Input Offset Voltage Drift
TCVos
Rs=500
3
( aTCVos)
avos
Rs= 500
05
Change in Input Offset
Drift with Vos Adjust
MIN
MIN
TYP
MAX
1.2
2.3
UNITS
mV
p.VloC
p.V/oC per mV
0.5
Input Offset Current
los
T,,; THIGH (Note 1)
4.0
10
0.4
1.0
nA
Input Bias Current
Ie
T,'; THIGH (Note 1)
±10
±25
±2
±5
nA
Large-Signal Voltage Gain
Ava
Vs =±15V, Vo =±10V,
RL = 2kO
25
75
25
75
VlmV
Output Voltage Swing
Va
Vs = ± 15V, RL = 10kO
Vs = ± 15V, RL = 2kO
±12
±10
±13
±12
±12
±10
±13
±12
V
Input Voltage Range
IVR
Vs =±15V
±10.4
+151
-12.0
±104
+15.1
-120
V
CMRR
VcM=±IVR
85
100
85
100
dB
PSRR
(Note 2)
Common~Mode
Rejection
RatIO
Power Supply Rejection
Ratio
10
57
10
57
p.VIV
NOTES:
1 PMI has a bias current compensation cIrcuit which gives Improved bias
current overthe standard JFET Inputop amps. 'Band los are measured at
VCM=O.
2. Power supply rejection ratio is measured for both supply magnitudes
Increasing or decreasing simultaneously, In accordance With common
practice.
5-260
1/86, Rev. A
---------t~ PM-155A/PM-156A1PM-157A MONOLITHIC JFET-INPUT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS at ±15V:5 VS:5 ±20V. TA = 25°C. unless otherwise noted.
PM·155A1
PM·156A1
PM·157A
PARAMETER
SYMBOL
CONDITIONS
Input Ollset Voltage
Vos
Rs = 500
Input Offset Current
los
TI = 25'C (Note 1)
3
10
Input Bias Current
Ie
TI = 25'C (Note 1)
±30
±50
Input Resistance
R'N
Large-Signal Voltage Gain
Supply Current
Slew Rate
Avo
ISY
SR
MIN
GBW
ts
Vs =±15V, Vo =±10V,
RL = 2kO
en
Vs =±ISV
AVCL = +1, Vs= ±ISV
AVCL =+1. Vs =±ISV
Vs = ±15V (Note 2)
Input Noise Current
In
Input Cspacitance
C 'N
Rs =
Rs =
Rs =
Rs =
1000, I
1000, I
1000, I
1000, I
50
PM-15S
PM-15S/PM-1S7
Vs =±15V(Note3)
Input NOise Voltage
MIN
10'2
AVCL =+5, Vs =±ISV
Selliing Time (to ±0.01%)
MAX
TYP
MAX
UNITS
2
mV
3
10
pA
±30
±50
pA
2
AVCL =+5, Vs =±15V
Gain Bandwidth Product
TYP
PM-355A1
PM·356A1
PM·357A
=
=
=
=
100Hz
1000Hz
100Hz
1000Hz
PM-ISS
PM-1S6
PM-I 57
PM-15S
PM-156
PM-I 57
PM-ISS
PM-ISS
PM-I 57
PM-ISS
PM-156/PM-1S7
I = 100Hz, Vs = ± ISV
1= 1000Hz. Vs =±ISV
10'2
200
2
50
4
7
12
45
40
15
2.5
45
20
200
2
5
3
3
10
40
0
VlmV
4
7
mA
10
40
5
12
45
VII's
4.0
15
2.5
4.5
20
MHz
50
40
40
40
1.5
1.5
/'S
25
20
15
12
25
20
15
12
nVl..,fHZ
001
0,01
0.Q1
0.01
pN..,fHZ
3
3
pF
~
......
NOTES:
1. PMI has a bias current compensation circuit which gives improved bias
current over the standard JFET input opamps.IBand losare measured at
VCM=O.
2. Selliing time is dell ned here lor a unity gain inverter connection uSing 2kO
resistors. It IS the time required lor the error voltage (the voltage at the
Inverting Input Pin on the ampliller) to sellle to within 0.01% 01 its final
value Irom the time a 10V step input is applied to the inverter. See selliing
time test circuit.
3. Sallling time IS dellned herelora Av=-S connection with R F= 2kO.ltls
the time required lor the error voltage (the voltage at the Inverting Input
pin on the amplifier) to sellie to within 0.01% 01 Its Ilnal value Irom the time
a 2V step input is applied to the inverter. See selliing time test circuit.
5-261
ge
1/86, Rev. A
~
::s
I=l-<
~
~
0
......
~
~
--------1~ PM-155A/PM-156A/PM-157A MONOLITHIC JFET-INPUT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS at TA = +25 0 C, ± 15V:S Vs:S ±20Vfor PM-155, PM-156 and PM-157, unless otherwise noted.
PM-155
PM-156
PM-157
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs~50n
TYP
MAX
Input Offset Current
los
T,~
25°C (Note 1)
3
20
Input Bias Current
Ie
T,~
pA
25°C (Note 1)
±30
±100
Input Resistance
R'N
pA
Large-Signal Voltage GaIn
Avo
±15V.
Rl ~ 2kn
Supply Current
ISY
Vs~±15V
Slew Rate
SR
Vs~
AVCl ~+1,
MIN
mV
Vo~
±10V,
50
PM-155
PM-156
PM-157
Vs~±15V
Settling Time (to ±O,Ol%)
Input Noise Voltage
GBW
ts
en
Input Noise Current
in
Input Capacitance
C'N
AVCl ~+1,
Vs~±15V
AVCl ~+5,
Vs~±15V
Vs~±15V
(Note 2)
Vs~±15V
(Note 3)
Rs ~
Rs ~
Rs ~
Rs ~
f
f
~
~
lOOn,
100n,
100n,
lOOn,
f
f
f
f
~
~
~
~
100Hz
1000Hz
100Hz
1000Hz
n
200
VlmV
7.5
30
12
40
4
rnA
VII's
PM-155
PM-156
PM-157
25
5
20
MHz
PM-155
PM-156
PM-157
5
4
4
p.s
25
20
15
12
nV/jHZ
0,01
pAljHZ
3
pF
PM-155
PM-156/PM-157
100Hz, Vs ~ ± 15V
1000Hz, Vs ~ ±15V
10'2
2
5
PM-155
PM-156/PM-157
Avcl ~ +5, Vs ~ ±15V
Gain Bandw,dth Product
UNITS
NOTES:
1. PMI has a bias current compensation circuit which gives improved bias
current over the standard J FET input op amps, leand I osare measured at
VCM~ O.
2. Settling time is defined here for a unity gain inverter connection using 2kn
resistors. It is the time required for the error voltage (the voltage at the
inverting input pin on the amplifier) to settle to within 0.01% of its final
value from the time a 10V step input is applied to the inverter. See settling
time test circuit.
3. Settling time is defined here for a Av~-5 connection with RF~ 2kn.1t is the
time required for the error voltage (the voltage at the Inverting input pin on
the amplifier) to settle to within 0.01'10 of its final value from the time a 2V
step input is applied to the inverter. See settling time test circuit.
5-262
1/86, Rev. A
-------l~ PM-155A/PM-156A/PM-157A MONOLITHIC JFET-INPUT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS at ± 15V:O; Vs:O;±20V and -55 0 C:O; TA:O; + 1250 C and THIGH= +125 0 C for PM-155, PM-156
and PM-157, unless otherwise noted.
PM-155
PM-156
PM-157
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs= 500
Input Offset Voltage
Drift
TCVos
Rs = 500
( aTCVos)
avos
Rs= 500
Change In Input Offset
Drift With Vas Adjust.
MIN
TYP
MAX
UNITS
4
mV
p.V/'C
p.V/'C
per mV
0.5
20
nA
±50
nA
Input Offset Current
los
T,'; THIGH (Note I)
Input Bias Current
18
T,'; THIGH (Note I)
Large-Signal Voltage
Gain
AyO
Vs= ±15V, Vo= ±10V
RL = 2kO
25
75
V/mV
Output Voltage Swing
Va
Vs= ±15V, AL = 10kO
Vs = ±15V, RL = 2kO
±12
±10
±13
±12
V
±10.4
+151
-12.0
V
100
dB
Input Voltage Range
IVR
±2
Vs = ±15V
Common-Mode
Rejection Ratio
CMRR
VcM=±IVR
Power Supply
Rejection Ratio
PSRR
(Note 2)
85
10
~......
~
~
p.,
57
p.VIV
NOTES:
1. PMI has a bias current compensation circuit which gives improved bias
current overthe standard JFET input op amps. IBand IOSara measured at
VCM = 0, T, = +125'C.
2. Power supply rejection ratio is measured for both supply magnitudes
increasing or decreasing simultaneously, In accordance with common
practice.
ORDERING INFORMATIONt
PIN CONNECTIONS
~
.....:l
~
0......
~
~
C5
PACKAGE
TA = 2S'C
VosMAX
(mV)
TO-99
8-PIN
8-PIN
HERMETIC
DIP
2.0
PMI55AJ'
PMI56AJ'
PMI57AJ'
PMI55AZ'
PMI56AZ'
PMI57AZ'
2.0
PM355AJ
PM356AJ
PM357AJ
PM355AZ
PM356AZ
PM357AZ
PMI55J'
PMI56J'
PMI57J'
PM155Z
PM156Z
PM157Z
5.0
LCe
OPERATING
TEMPERATURE
RANGE
PM155ARC/883
PM156ARC/883
MIL
NC
8
_,::0
V
:OUT
"SC7.AL
COM
8-PIN HERMETIC DIP
(Z-Sufflx)
v-
4
(CASE)
TO-99 (J-Sufllx)
MIL
• For deYlces processed In total compl,ance to MIL-STD-883, add 1883 after
part number Consult factory for 883 data sheet.
tAil commercial and industrial temperature range parts are available with
burn-In. For ordering Information see 1986 Data Book, Section 2.
PM-155ARC/883,
PM-156ARC/883
20-LEAD LCC
(RC-Suffix)
5·263
1/86, Rev. A
_ _ _ _ _---IIfMDPM-155A1PM-156A1PM-157A MONOLITHIC JFET-INPUT OPERATIONAL AMPLIFIERS
BASIC CONNECTIONS
If both inputs exceed the negative common-mode voltage
limit, the amplifier will be forced to a high positive output. If
only one input exceeds the negative common-mode voltage
limit, a phase reversal takes place forcing the output to the
corresponding high or low state. In either of the above
conditions, normal operation will return when both inputs are
returned to within the specified common-mode voltage range.
SETTLING-TIME TEST CIRCUIT
2kn 0 1%
+15V
:oy
o-_'2-J1"A'0,..,'_%......"-1
5k"
01%
_15V
VOUT
POWER SUPPLY CONSIDERATIONS
Power supply polarity reversal can result in a destroyed unit.
Av=-l
2N4416
Exceeding the positive common-mode limit on a single input
will not change the phase of the output. However, if both
inputs exceed the limit, the output of the amplifier will be
forced to a high state.
+1SV
.. 400.11 ±O 1% FOR PM·157A
** lk.l1 ±O 1% FDA PM·157A
INPUT OFFSET VOLTAGE NULLING
NOTE
FOR POTENTIOMETERS WITH A TEMPERATURE COEFFICIENT";;; 10Qppm/"C,
THE ADDED TCVos WITH NULLING IS"" 0 5/NloC/mV Of ADJUSTMENT
DYNAMIC OPERATING CONSIDERATIONS
As with most amplifiers, care should be taken with lead
dress, component placement, and supply decoupling in
order to ensure stability. For example, resistors from the
output to an input should be placed with the body close to the
input. This minimizes "pick-up" and increases the frequency
of the feedback pole by minimizing the capacitance from
input to ground.
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device to AC ground sets the frequency
of the pole. In many instances, the frequency of this pole is
much greater than the expected 3dB frequency of the
closed-loop gain. Consequently, the pole has negligible
effect on stability margin. However, if the feedback pole is
less than approximately six times the expected 3dB frequency, a lead capacitor should be placed from the output to
the inverting input of the op amp. The capacitor value should
be such that the RC time constant of the capacitor and
feedback resistor is greater than, or equal to, the original
feedback-pole time constant.
APPLICATIONS INFORMATION
INPUT VOLTAGE CONSIDERATIONS
The PM series JFET input stages can accommodate large
input differential voltages without external clamping as long
as neither input exceeds the negative powersupply. An input
voltage which is more negative than V- can result in a
destroyed unit.
5-264
1/86, Rev. A
PM-725
INSTRUMENTATION
OPERATIONAL AMPLIFIER
Precision Monolithics Inc.
FEATURES
•
•
•
•
•
•
•
addition, Precision Monolithics' exclusive Silicon-Nitride
"Triple Passivation" process minimizes "popcorn noise" and
provides maximum reliability and long-term stability. For
improved specifications, refer to the OP-06 series data sheet.
For devices with internal frequency compensation, refer to
the OP-05 instrumentation amplifier and OP-07 ultra-low offset
voltage operational amplifier data sheets.
Extremely High Gain ......................... 3M Typ
Low Offset Voltage and Offset Current
Low Drift with Temperature
High Common-Mode ReJecllon ............ 110dB Min
High Power Supply ReJecllon ............. 10p.VIV Max
Silicon-Nitride Passlvallon
Dlfferenllal-Input Overvoltage Protecllon
II
PIN CONNECTIONS
ORDERING INFORMATIONt
PACKAGE
HERMETIC
TA=2S"C
VosMAX
(mV)
1.0
2.5
TO·99
a·PIN
DIP
a·PIN
PM725J"
PM725CJ
PM725Z"
PM725CZ
vos
PLASTIC
DIP
a·PIN
PM725CP
OPERATING
TEMPERATURE
RANGE
-IN 2
MIL
COM
e
rn
+
+IN 3
7V+
6 OUT
5 COMP
4
v-leASE)
* For devices processed in total compliance to MIL-STD-S83, add 1883 after
part number. Consult factory for 883 data sheet.
commercial and industrial temperature range parts are available with
burn·,n. For ordering information see 1986 Data Book, Section 2
TO-99
(J-Sufflx)
t All
GENERAL DESCRIPTION
8-PIN HERMETIC DIP
(Z-Sufflx)
&
EPOXY MINI-DIP
(P·Sufflx)
The PM-725 series of monolithic instrumentation operational
amplifiers provide industry-standard 725 specifications. In
SIMPLIFIED SCHEMATIC
v+
A1'
OUTPUT
A20
v-
5·265
1/86, Rev. A
------------1~ PM-725 INSTRUMENTATION OPERATIONAL AMPLIFIER
PM-725C .•.•••••••.••••••••..•••..••••• 0° C to + 70° C
Lead Temperature Range (Soldering, 60 sec) ••••.. 300° C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ••••••••••••••••••••.•.•••..••••..• ±22V
Internal Power Dissipation (see note) ••••••..•.•• 500mW
Differential Input Voltage ••••••••••••..•.•...•••... ±30V
Input Voltage ••••••••••••••••••••••.•.••• Supply Voltage
Output Short-Circuit Duration ••••••••••••...•• Indefinite
Storage Temperature Range
J and Z Packages • • . • . • . • • • • • • . • • . .. -65° C to + 150° C
P Package ••••..••..•.••.•••.•..••• -65°C to +125°C
Operating Temperature Range
PM-725 .•••••••••••...•.••••.••.••. -55° C to + 125° C
ELECTRICAL CHARACTERISTICS at Vs = ±
15V, TA
NOTE:
1, See table for maximum ambient temperature rating and derating factor,
PACKAGE TYPE
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
TO-99 (JI
BO°C
7,lmW/oC
B-Pin Plastic DIP (PI
36°C
5,6mW/oC
B-Pin Hermetic DIP (ZI
75°C
6,7mW/oC
= 25° C, unless otherwise noted.
PM-725
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs 510kO
Input Offset Current
los
Input Bias Current
Is
Input Noise Voltage
en
MIN
MAX
TYP
MAX
UNITS
0,5
1,0
0,5
25
mV
20
2
35
nA
100
42
125
nA
42
fo = 10Hz
fo= 100Hz
fo= 1000Hz
Input Resistance
R'N
Input Voltage Range
IVR
Large-Signal Voltage
Gain
Avo
RL ",2kO, Vo =±10V
Common-Mode
Rejection Ratio
CMRR
Rs 510kO, VcM =±13,5V
Power Supply
Reiection Ratio
PSRR
Rs 510kO, Vs =±5Vto±15V
Output Voltage Swing
Vo
RL ",10kO
RL ",2kO
Output Resistance
Ro
Vo=O,lo=O
Power Consumption
Pd
No Load
PM-725C
TYP
MIN
15
9
B
1.5
nV/y'HZ
1,5
MO
±13.5
±14
±13,5
±14
V
1,000
3,000
250
3,000
VlmV
110
120
94
120
dB
10
±12,0
±10,0
±13,5
±13.5
BO
2
±12.0
±10,0
150
5·266
15
9
B
35
±13,S
±13,5
V
150
105
BO
p.V/v
0
150
mW
1/86, Rev. A
-----------l~ PM-725 INSTRUMENTATION OPERATIONAL AMPLIFIER
COMPENSATION CIRCUIT
OFFSET VOLTAGE NULL CIRCUIT
R3"
Rl
Cl
C2
R2
.V-OR~
GND
-:-
.USE R3 '" 510 WHEN THE AMPLIFIER
IS OPERATED WITH CAPACITIVE LOAD
PINOUTS FOR J, Z, AND P PACKAGES,
COMPENSATION COMPONENT VALUES
",
C,
CuF)
"2
C2
1m
(p.F)
00015
AV
In)
10,000
'Ok
470
47
50pF
27
005
270
'0
0,05
3.
1,000
'00
'0
II
0001
0.01
0.02
-FOR MAXIMUM PSRR VS FREQUENCY
COMPENSATION NETWORK SHOULD
BE RETURNED TO v-
PINOUTS FOR J, Z, AND P PACKAGES,
ELECTRICAL CHARACTERISTICS at Vs=±15V, -55° C:5TA:5+125°Clor PM-725, O°C:5TA:5+700 Clor PM-725C, unless
otherwise noted,
PM-725
MIN
TYP
PM-725C
MAX
MIN
TYP
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs510kO
Average Input Offset
Voltage Drift
TCVos
Rs = 500, Unnulled (Note 1)
Average Input Offset
Voltage Drift
TCVOSn
Rs = 500, Nulled
0.6
Input Offset Current
los
TA=MAX
TA=MIN
1.2
7.5
20
40
1.2
4.0
Average Input Offset
Current Drift
TClos
(Note 1)
35
150
10
Input Bias Current
18
TA = MAX
TA = MIN
20
80
100
200
30
100
Large-Signal Voltage
Gain
Avo
RL <:2kO, TA = MAX
RL <:2kO, TA=MIN
Common-Mode
Rejection Ratio
CMRR
Rs 510kO, VCM =±13.5V
Power Supply
Rejection Ratio
PSRR
Rs 5 10kO, Vs = ±5V to ± 15V
Output Voltage Swing
Vo
RL <: 2kO
1.5
3.5
100
20
±10
±10
UNITS
mV
2
".V/oC
0.6
I'V/oC
125
125
1,000
250
MAX
35
50
nA
pA/oC
125
250
nA
VlmV
115
dB
20
I'V/v
V
NOTE: 1. Sample tested.
5-267
1/86, Rev. A
PM-741
COMPENSATED
OPERATIONAL AMPLIFIER
Precision Monolithics Inc.
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
The PM-741 series of internally-compensated operational
amplifiers provide industry-standard 741 specifications. In
addition, Precision Monolithics' exclusive Silicon-Nitride
"Triple Passivation" process provides high reliability and
long-term stability of parameters. For higher performance
general purpose op amps, refer to the OP-02 data sheet. See
the OP-04/0P-14 data sheet for duals.
Industry Standard 741 Specifications
Internal Frequency Compensation
Continuous Short·Clrcult Protection
Silicon-Nitride Passivation
Low Noise
ORDERING INFORMATIONt
TA = 25°C
PACKAGE
OPERATING
VosMAX
TO-99
I-PIN
TEMPERATURE
RANGE
PM741J
PM741CJ
MIL
COM
(mV)
5.0
6.0
PIN CONNECTIONS
8Ne
BAL~7V'
TO-99
t All
commercial and industnal temperature range parts are available with
burn-in. For ordenng mformatlOn see 1986 Data Book, Section 2.
-IN 2
-
+IN3
6 OUT
(J-Sufflx)
SBAL
4
v- (CASE)
SIMPLIFIED SCHEMATIC
~--",,-------.£"Q20
R"
OUTPUT
,----+--0
R8
ABSOLUTE MAXIMUM RATINGS
Rl0
Operating Temperature Range
PM-741 ............................ -55°C to +125°C
PM-741C ............................... O°C to +70°C
Supply Voltage
PM-741 ........................................ ±22V
PM-741C ....................................... ±18V
Internal Power Dissipation (Note 1) .............. 500mW
Differential Input Voltage .......................... ±30V
Input Voltage ........................... , Supply Voltage
Output Short-Circuit Duration ................. Indefinite
Storage Temperature Range ........... -65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) ...... 300°C
NOTE:
1. See table for maximum ambient temperature rating and derating factor.
PACKAGE TYPE
TO-99 (J)
5-268
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
eo°c
7.1mW/oC
1/86, Rev. A
------------I1fMD PM-741 COMPENSATED OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at
TA
= 25° C, Vs =
± 15V, unless otherwise noted.
PM-741
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
Rs " 10kfl
Input Offset Current
MIN
TYP
PM-741C
MAX
MIN
MAX
UNITS
5.0
TYP
6.0
mV
los
200
200
nA
Input Bias Current
18
SOO
500
Input Resistance
R'N
(Note II
Large-Signal
Voltage Gain
Avo
R L " 2kfl. Vo= ±IOV
Supply Current
ISY
VOUT= 0
0.3
Mfl
50,000
25,000
V/v
2.8
2.8
ELECTRICAL CHARACTERISTICS at -55° C::; TA::; + 125° C for PM741, 0° C::; TA::; +70° C for PM741 C, Vs =
otherwise noted.
PM-741
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs" 10kn
Input Offset Current
los
Input Bias Current
18
Large-Signal
Voltage Gain
Avo
Output Voltage Swing
nA
0.3
MIN
TYP
mA
±15V, unless
PM-741C
MAX
MIN
TYP
MAX
UNITS
6.0
7.5
mV
500
300
nA
15
08
JIoA
25.000
15.000
V/v
Vo
±12
±10
±12
±10
V
±12
±12
V
70
70
dB
Input Voltage Range
IVR
Common-Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
R L " 2kfl. Vo=±IOV
142
Rs" 10kfl
142
JIoV/v
NOTE:
I. Guaranteed by design
TYPICAL OFFSET NULLING CIRCUIT
TYPICAL BURN-IN CIRCUIT
v-
~20V
5-269
1/86, Rev. A
PM-747
DUAL COMPENSATED
OPERATIONAL AMPLIFIER
Precision Monolithics Inc.
FEATURES
GENERAL DESCRIPTION
•
The PMI series of internally-compensated operational amplifiers provides industry-standard 747 specifications. In addition,
Precision Monolithics' exclusive Silicon-Nitride "Triple Passivation" process provides maximum reliability and long-term
stability of parameters for lowest overall system operating cost.
•
•
•
•
Dual PM-741 Internally-Compensated Operallonal
Amplifier
Internal Frequency Compensation
Low Power Consumption
Continuous Short-Circuit Protection
Silicon-Nitride Passivation
PIN CONNECTIONS
ORDERING INFORMATIONt
TA = 25°C
VosMAX
(mY)
PACKAGE
HERMETIC
DIP
14-PIN
OPERATING
TEMPERATURE
RANGE
5.0
6.0
PM747Y
PM747CY
MIL
COM
14-PIN DIP
(Y-Sufflx)
*V+ (A) AND v+ (B)
INTERNALLY CONNECTED
tAli commercial and industrial temperature range parts are available with
burn~in, For ordering information see 1986 Data Book, Section 2.
SIMPLIFIED SCHEMATIC (1/2 of Circuit Shown)
R9
OUTPUT
,----1'--C
Rl0
5·270
1/86, Rev. A
-----------I~ PM-747 DUAL COMPENSATED OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Supply Voltage
PM-747 •.•.•..•••...•••.•••.•.••••••.•..•.•••.. ±22V
PM-747C ••.••.•••.•..•••••••••.•••••.•.•••••••• ±18V
Internal Power Dissipation (Note 1)
Y Package ••..•.....•.••.•••••.•...•••.....•. 670mW
PM-747
............................
NOTE:
1. See table for maximum ambient temperature rating and derating factor.
Differential Input Voltage .......................... ±30V
Input Voltage ••.••.••.•••.•••••••••••.••• Supply Voltage
Output Short-Circuit Duration •.•.••••••...•••. Indefinite
PACKAGE TYPE
Storage Temperature Range ••••••••••• -65°C to +150°C
Lead Temperature Range (Soldering. 60 sec) ••••.• 300°C
14-Pin Hermetic DIP (Y)
ELECTRICAL CHARACTERISTICS
-55°C to +125°C
PM-747C ............................... O°C to +70·C
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
83· C
10.0mW/·C
at TA = 25°C. Vs= ±15V. unless otherwise noted.
PM-747
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs '; 20kO
MIN
PM-747C
TYP
MAX
1.0
5.0
MIN
TYP
MAX
UNITS
1.0
6.0
mV
Input Offset Current
los
20
200
20
200
nA
Input Bias Current
18
80
500
80
500
nA
Input Resistance
R'N
Input Capacitance
C 'N
(Note 1)
022
Offset Voltage
Adiustment Range
Large-Signal
Voltage Gain
Avo
RL "2kO. Vo =±10V
Output Voltage Swing
Vo
RL" 10kO
RL " 2kO
Output Resistance
Ro
Isc
Output Short-Circuit
Current
Supply Current
ISY
Input Voltage Range
IVR
Common~Mode
Rejection Ratio
Power Supply
Rejection Ratio
Rs'; 20kO. VCM = ±10V
PSRR
Vs = ±5V to ±20V
Vs =±5Vto±18V
2.0
MO
14
0.3
1.4
pF
±15
±15
mV
50
200
25
200
V/mV
±12
±10
±14
±13
±12
±10
±14
±13
V
75
75
0
25
25
rnA
Per Amplifier. No Load
CMRR
2.0
1.7
2.8
1.7
2.8
rnA
±12
±13
±12
±13
V
70
90
70
90
dB
30
150
30
150
50
85
!'VIV
Power Consumption
Pd
Per Amplifier. No Load
50
Transient Response.
Risetime
Overshoot
Y,N = 20mV. RL = 2kO
C L ,; 100pF
0.3
5
0.3
5
!,s
Slew Rate
SR
RL ,,2kO
0.7
0.7
V/!'s
Channel Separation
CS
120
120
dB
Unity Gain
85
mW
%
NOTE:
1. Guaranteed by input bias current.
5·271
1/86, Rev. A
I
ffi
......
j:.l..,
~
~
~
0
......
~
~
C5
~
PM-747 DUAL COMPENSATED OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs=±15V, -55· C:5TA:5+125· Cfor PM-747, O·C:5TA:5+70·Cfor PM-747C, unless
otherwise noted.
PM-747
MAX
TYP
MAX
UNITS
Rs:5 20kn
1.0
6.0
1.0
7.5
mV
los
TA = MAX
TA = MIN
7
85
200
500
7
30
200
300
nA
18
TA = MAX
TA = MIN
0.03
0.3
0.5
15
0.03
0.10
0.5
0.8
!loA
Output Voltage Swing
Va
RL--+--------If---'
I
I
I
r-.J
I
I
I
I
I
I
I
OUTPUT
I
I
IL ____ ...lI
vNOTE: BIAS CIRCUIT SHOWN IN DASHED BOX IS COMMON TO ALL DEVICES.
5-279
1/86, Rev. A
----------I~ JM-38510/11004 JAN QUAD 741-TYPE OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
The differential input voltage range shall not exceed the supply voltage
range.
Supply Voltage Range (Note 1) •.•••.••.•••••••.•..••• ±22V
4
Input Voltage Range (Note 2) ••.•...••.•••••••.•.•••• ±22V
Short circuit may be to ground orelther supply. Rating applies to +125'C
case temperature or +75° C ambient temperature
Differential Input Voltage Range (Note 3) ..•••..•••..•• ±30V
Input Current Range ..••..•.••.•..••..•..•.••• 10 to 0.1 mA
For short-term test (In the specific burn-in and lile-test configuration
where required and up to 168 hours maximum)
1j =
2750 C.
Storage Temperature Range •••.•....•••.• -65°C to +150°C
Output Short-Circuit Duration (Note 4) ........... Unlimited
RECOMMENDED OPERATING CONDITIONS
Lead Temperature (Soldering, 60 sec) ••..••••.••..••• 300°C
Junction Temperature
Supply Voltage Range •••••••.•.•••••••••••••• ±5V to ±20V
Ambient Temperature Range •.••.••.••.•.•.• -55° to +125° C
(Tj) (Note 5) ..•••.••..•...•..• 175°C
NOTES:
1 Voltages In excess of these may be applied for short-term tests If voltage
difference does not exceed 44 volts
2
For supply voltages less than ±20V. the absolute maximum input voltage IS
equal to the supply voltage
ELECTRICAL CHARACTERISTICS
at ±5V:S Vcc:S ±20V and -55°C:S TA:S 125°C, Rs = 50n, unless otherwise noted.
04 LIMITS
PARAMETER
Input Offset Voltage
Input Offset Voltage
Temperature Sensitivity
SYMBOL
CONDITIONS
MIN
MAX
UNITS
V,O
TA =25'C
-55'C ST. S 125'C
(Note 1)
-5
-6
5
6
mV
t.V,o/t.T
-55'C S T. S 125'C
-25
25
pVl'C
-75
75
-150
150
-55'C ST. S 25'C
-1000
1000
25'C ST. S 125'C
-500
500
+118
Rs =20kO,
25'C S T. S 125'C
TA =-55'C
(Note 1)
-250
-400
-1
-1
-lIB
Rs =20kO,
25'C ST. S 125'C
TA =-55'C
(Note 1)
-250
-400
-1
-1
+PSRR
+Vee
-100
100
-PSRR
+Vee
-100
100
25' C S TA S 125' C, Rs
(Note 1)
Input Offset Current
Input Offset Current
Temperature Sensitivity
1,0
RatiO
Input Voltage Common-Mode
Rejection
Output Short C"CUlt
Current
=20kO
nA
.l1,o/t.T
Input Bras Current
Power Supply Rejection
T. =-55' C, Rs
(Note 1)
=20kO
CMR
'08(+)
pAI'C
=10V, -Vee =-20V
=20V, -Vee =-10V
Common-Mode Range =30V
(Note 2)
±Vee =±15V, 25'C ST. S 125'C
(Note 3)
nA
pVIV
76
dB
-80
mA
Output Short C"cUlt
Current
Supply Current
Output Voltage SWing
loS I_I
±Vee = ±15V, T. = -55'C
(Note 3)
80
Icc
T. = -55'C
Vee = ±15V
TA = 25'C
(Note 4)
TA = 125'C
13
11
11
+Vop
_
RL = 10kO
Vee - ±20V, RL = 2kO
-Vop
_
RL = 10kO
Vee - ±20V, RL = 2kO
mA
+16
+15
V
(MaXimum)
5-280
-16
-15
1/86, Rev. A
-----------I1fMD
JM-38510/11004 JAN QUAD 741-TYPE OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at ±5V :5,Vcc :5,±20V and -55 0 C :5,TA :5,125° C, Rs = 500, unless otherwise noted. (Continued)
04 LIMITS
PARAMETER
Open-Loop Voltage Gain
(Single Ended)
SYMBOL
CONDITIONS
A VS (+)
RL = 10kO, ±Vo = ±15V.
TA = 25°C
-55°C S TA S 125°C
50
25
AVSH
RL = 2kO, ±Vo = ±15V.
TA =25°C
-55°C STA S 125°C
50
25
RL = 10kO, TA = 25°C
RL = 2kO, ±Vcc = ±5V,
10
10
Avs
MIN
MAX
UNITS
V/mV
-55°C ::;TA ::; 125°C
Transient Response
Rise Time
Transient Response
Overshoot
Slew Rate
NOise
(Broadband)
Noise
(Popcorn)
Channel Separation
TR ltr )
±Vcc = ±20V, Av = 1
TRIOS)
±Vcc = ±20V
SR(+)
±Vcc = ±20V, Av = 1
N,(BB)
TA = 25° C, ±Vcc = ±20V,
Rs = 500
N,(PC)
TA = 25° C, ±Vcc = ±20V,
Rs = 20kO
CS
TA =25°C
OFFSET VOLTAGE
CONDITION
!is
50
!is
06
JiV rms
dB
80
NOTES:
1. Tested at VCM = 0, +15V and -15V with ±Vcc = ±20V, and at VCM = OV and
-2.5V with ±Vcc = ±5V
2. CMR is determined by measuring Input offset voltage as follows
03
3
Only one amplifier shorted to ground atone time, 0 :5 t :5 25ms Continuous
limits will be considerably lower and apply for -55°C :5 TA ::;: 25° C
Icc limits are the total for all four amplifiers at no load, connected as
followers with the nonlnvertlng inputs grounded
.Vee
+Vee
35V
-5V
15V
5V
-35V
-15V
BURN-IN CIRCUIT
6800
680n
J"'.'
680n
680n
,on
300n
-,v
J
O ,.,
+15V
aoon
1_
+10V
o".''--_~--'-IL-_ _ _~===~I-''--------'
,on
1_
O.1j.1F
NOTES
1 RESISTORS ARE ±5%
2 VOLTAGE TOLERANCE -OV. +1.6V
-15V
5-281
1/86, Rev. A
II
J~38510/11401/11402/11403/
11404/11405/11406
JAN JFET-INPUT
OPERATIONAL AMPLIFIERS
Precision MOllolithics Inc.
GENERAL DESCRIPTION
This data sheet covers the electrical requirements for a
monolithic, low-power, internally-compensated JFET-input
operational amplifier as specified in MIL-M-38510/114 for
device types 01 to 06. Devices supplied to this data sheet are
manufactured and tested at PMl's MIL-M-38510 certified
facility and are listed in QPL-38510.
not have identical operational performance characteristics
across the military temperature range or reliability factors
equivalent to the MIL-M-38510 device.
Military Device Type
Generic-Industry Type
01
04
LF-155
LF-155A
LF-156
LF-156A
LF-157
LF-157A
Complete device requirements will be found in MIL-M-38510
and MIL-M-38510/114 for Class B processed devices.
02
05
03
06
GENERIC CROSS-REFERENCE INFORMATION
This cross-reference information is presented for the convenience of the user. The generic-industry types listed may
SIMPLIFIED SCHEMATIC
{2}
o---+......+-'--f--+----+-+-----+---.:+-++---~
NOTE: For values of C1, C2, RS, RB see the
following table:
5-282
0104
0205
030B
C1
7pF
1.7pF
C2
7pF
1.7pF
RS
7.2kn
3.Bkn
RB
7.2kn
3.Bkn
1/86, Rev. A
-----I~ JM38510111401/11402111403/11404/11405/11406 JAN JFET-INPUT OPERATIONAL AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range ............................ ±22V
Input Voltage Range (Note 1) ...................... ±20V
Differential Input Voltage Range ••••••••••••••••••• ±40V
Lead Temperature (Soldering, 60 sec) ••••••••••••• 300·C
Junction Temperature ••••••••••••••• Tj = 17S· C (Note 3)
Storage Temperature Range ••••••••••• -6S·C to +1S0·C
Output Short-Circuit Duration •••••••• Unlimited (Note 2)
NOTES:
1. The absolute maximum negative Input voltage is equal to the negative
power supply voltage.
2. Short circuit may be to ground to either supply. Rating applies to + 125°C
case temperature or + 750 C ambient temperature.
3. For short-term test (In the specific burn-In and hfe test configuration when
reqUired and up to 168 hours maximum), TJ= 275°C
RECOMMENDED OPERATING CONDITIONS
Supply Voltage Range ................... ±S to ±20 VDC
Ambient Temperature Range ••.••••••• -SS·C to +12S·C
ELECTRICAL CHARACTERISTICS at Vcc from ±SV to ±20V; source resistance = SO ohm; ambient temperature range =
-SS·C to +12S·C and figure 1, unless otherwise noted.
PARAMETER
Input Offset
Voltage
Input Offset Voltage
Temperature Sensitivity
Input Offset Current
SYMBOL
CONDITIONS
V,O
±vec = ±5V, VCM = OV
TA = 25°C
±Vee =±20V
VcM =±15V,OV
-55°CSTA S+125°C
av,o
"3T
1,0
+I JB
Input Bias Current
(Note 1)
(Note 2)
(Note 3)
-liB
01 LIMITS
MIN
MAX
-5
5
04 LIMITS
MIN
MAX
-2
UNITS
-2.5
25
30
-10
10
p.V/oC
~
±Vcc = ±20V, VCM = OV,
TJ=25°C
T 1= 125°C
-20
-20
20
20
-20
-20
20
20
pA
nA
0
......
-100
-10
3500
60
-100
-10
3500
60
pA
nA
±VCC = ±20V, VCM = +15V
TJ=25°C
tS25ms
TJ=125°C
±Vee = ±15V, VCM = +10V
TJ= 25°C
tS25ms
TJ= 125°C
±Vcc = ±20V, -15V S VCM S OV
TJ= 25°C
ts 25ms
T1= 125°C
-100
-10
300
50
-100
-10
300
50
pA
nA
-100
-10
100
50
-100
-10
100
50
pA
nA
+ Vce = 10V, -Vec = -20V
+ Vee = 20V, -Vee = -10V
85
85
dB
Input Voltage Common-Mode
Rejection (Note 4)
CMR
±Vee= ±20V
V,N =±15V
85
85
dB
Adjustment for
I n put Offset Voltage
V,oADJ(+)
V,oADJ(-)
±Vec= ±20V
±Vcc=±20V
Output Short-Circuit Current
(for Positive Output) (Note 5)
108 [+)
±Vcc =±15V
tS25ms
(Short Circuit to Ground)
Output Short-Circuit Current
(for Negative Output)
(Note 5)
108[-)
±Vec= ±15V
ts 25ms
(Short CirCUit to Ground)
Supply Current
Icc
TA = -55°C
±Vee = ±15V, TA = +25°C
TA =+125°C
Output Voltage Swing
(Maximum)
VOP
±Vce = ±20V, RL = 10kfl
±Vee = ±20V, RL = 2kfl
Open-Loop Voltage Gain
(Single Ended) (Note 6)
AV8
~
p.,
-30
+PSRR
-PSRR
AV8 [+)
AV8 [_)
~
±Vce=±20V
VCM=OV
Power Supply
Rejection Rallo
Open-Loop Voltage Gain
(Single Ended) (Note 6)
~
~
......
2
mV
-7
II
+8
+8
-8
±Vce=±20V, Vo uT =±15V
RL = 2kfl, TA = 25°C
-55°C S TAS +125°C
±Vee =±5V
RL =2kfl
VouT =±2V
-50
~
~
C5
mV
-8
-50
mA
50
50
mA
6
4
4
6
4
4
mA
±16
±15
±16
±15
V
50
25
50
25
V/mV
10
10
VlmV
1/86, Rev. A
5-263
~----
~
~----
-
-
._--_._--
---~--
------1~
JM38510/11401/11402I11403/11404/11405/11406 JAN JFET-INPUT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS at Vcc from ±5V to ±20V; source resistance = 50 ohm; ambient temperature range =
-55°C to +125°C and figure 1. unless otherwise noted. (Continued)
01 LIMITS
PARAMETER
MIN
SYMBOL
CONDITIONS
Transient Response
Rise Time
TRltr)
±Vee= ±ISV. RL =2kfi. A y = I
CL = 100pF. See Figure 2
V,N= SOmV
Transient Response
Overshoot
TRIOS)
±Vee = ±ISV. RL = 2kfi. Av= I
CL = 100pF. See Figure 2
V,N=SOmV
Slew Rate
SR(+)
and
SR(-)
V,N = ±SV. ±Vee = ±ISV
Av= I. See Figure 2
TA =2S·C
TA = -SS·C. +12S·C
Sellilng Time
ts(+)
and
ts(-)
±Vec = ± ISV (0.1% error)
TA = 2S·C. Av =-1
See Figure 3
NOise (Referred to Input)
Broadband
N,(BB)
N,(PC)
NOise (Referred to Input)
Popcorn
04 LIMITS
MAX
MIN
MAX
UNITS
150
150
ns
40
40
%
2
Vlp.s
3
1.5
4000
4000
ns
±Vcc = ±20V. TA = 2S·C
Bandwidth = 5kHz
10
10
I'V rms
±Vec=±20V. TA =2S·C
Bandwidth = 5kHz
80
80
P.Vpk
NOTES:
I Bias currents are actually Junction leakage currents which double
(approximately) for each 10·C Increase In Junction temperature T,.
Measurement of bias current IS specified at TJrather than TA• since normal
warm-up thermal transients will affect the bias currents. The measurements
for bias currents must be made within 2Sms or Sloop time constants after
power is first applied to the device for test Measurement at TA= -55· C IS
not necessary since expected values are too small for tYPical test systems.
2. Bias current IS sensitive to power supply Yoltage, common-mode voltage
and temperature as shown by the following typical curves:
IIB(nAl
,.+ /
____-'_-'-_':_1-'--"-=---1-'
_-'-1_-"1_ _ _ _ _ TA(OCI
-50
-25
26
50
75
100
3
Negative lie minimum limits reflect the characteristics of deVice with bias
current compensation
4 CMR IS calculated from V'c measurements at Vet.! = +ISV and -ISV
5. Continuous limits shall be conSiderably lower. Protection for shorts to
either supply eXists prOViding that TJ(max):;; 17S·C
6. Because of thermal feedback effects from output to Input. open-lOOp gain
IS not guaranteed to be linear or positive over the operallng range. These
'equlrements. if needed. should be specified by the user In additional
procurement documents.
IIBlpA)
tVee .. t20V
400
200
..
----.~~:=---15/-10
-6
~=o:r::--'--_y'mlyl
10
15
POWER AND THERMAL CHARACTERISTICS
Package
CASE OUTLINE
Per MIL-M-38510. Appendix C. Case Outline A-1 (8 Lead
Can). Package Type Designator "G".
8 Lead Can
(TO-GG)
Case outline
G
Maximum allowable
Maximum
Maximum
power dlsalpatlon
8J-C
8J-A
330mW at TA = 12S·C
40·CIW
ISO·CIW
PIN CONNECTIONS AND ORDERING INFORMATION
N.C.
Jan Device
JM38510/11401 BGC
JM38510/11404BGC
JM38510/11402BGC
JM38510/11405BGC
JM38510/11403BGC
JM38510/11408BGC
S
o:.~~: C\+::T
+IN~~~~t"T
4
PMI Device Type
PM155J1/38510
PM155AJ1/38510
PM156J1/38510
PM156AJ1/38510
PM157J1/38510
PM157AJ1/38510
-Vee
NOTE: Lead Flnlsh·Gold Plate
Check With factory for other qualified lead finishes
(PIN 4 CONNECTED TO CASE)
5-284
1/86, Rev. A
-----l1fMD
JM38510/11401/11402l11403/11404/11405/11406 JAN JFET-INPUT OPERATIONAL AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range
............................ ±22V
Short CIrcuit may be to ground to either supply. Rating applies to + 125°C
case temperature or +7S Q C ambient temperature
3. For short-term test (In the specific burn-In and life test configuration when
required and up to 168 hours maximum), T, = 275°C.
Input Voltage Range (Note 1) ...................... ±20V
Differential Input Voltage Range •.•.•••••...•••..•• ±40V
Lead Temperature (Soldering. 60 sec) ..••••••••••. 300°C
Junction Temperature
............... Tj = 175° C (Note 3)
Storage Temperature Range ••.••••••.•
Output Short-Circuit Duration.. ••••••
RECOMMENDED OPERATING CONDITIONS
-65°C to +150°C
Unlimited (Note 2)
Supply Voltage Range
ELECTRICAL CHARACTERISTICS at Vcc from ±5V to ±20V; source resistance
-55°C to +125°C and figure 1. unless otherwise noted.
Input Offset
Voltage
SYMBOL
CONDtTIONS
V,o
±Vee = ±5V, VeM = OV
TA = 25°C
±Vee= ±20V
VeM = ±15V, OV
-55°C:S TA:S + 125°C
LIMITS
MtN
MAX
-5
05
LIMITS
MIN
MAX
UNITS
-2
±Vcc= ±20V
AT
VeM = OV
Input Offset Current
1'0
±Vee = ±20V. VeM = OV.
T, = 25°C
T, = 125°C
±Vee = ±20V. VeM = +15V
T, = 25°C
t:s 25ms
T, = 125°C
±Vee = ±15V, VeM = +10V
T, = 25°C
t:S25ms
T, = 125°C
±Vee = ±20V,-15V:S VeM:S OV
T, = 25°C
tS25ms
T, = 125°C
~
30
-10
10
/,V/oC
-20
-20
20
20
-20
-20
20
20
pA
nA
0
......
-100
-10
3500
60
-100
-10
3500
60
pA
nA
-2.5
2.5
I=l-.
-100
-10
300
50
-100
-10
300
50
pA
nA
-100
-10
100
50
-100
-10
100
50
pA
nA
Input Bias Current
(Note 1)
(Note 2)
(Note3)
-I'B
Power Supply
Rejection Ratio
+PSRR
-PSRR
+Vee= 10V, -Vee = -20V
+Vee = 20V, -Vee = -10V
85
85
dB
Input Voltage Common-Mode
Rejection (Note 4)
CMR
±Vee =±20V
V'N= ±15V
85
85
dB
Adiustment for
Input Offset Voltage
V,oADJ(+)
V,oADJ(-)
±Vee=±20V
±Vee= ±20V
Output Short-Circuit Current
(for Positive Output) (Note 5)
105 (+)
±Vee= ±15V
t:s 25ms
(Short CircUit to Ground)
Output Short-CirCUit Current
(for Negative Output)
(Note 5)
1051 - 1
Supply Current
Icc
TA =-55°C
±Vee =±15V, TA =+25°C
TA = +125°C
Output Voltage Swing
(Maximum)
VOP
±Vee = ±20V, RL = 10kfl
±Vee = ±20V, RL = 2kfl
AVS(+I
±Vee = ±20V, VOUT = ±15V
RL = 2kfl, TA = 25°C
-55°C:5TA:5+125°C
Open-Loop Voltage Gain
(Single Ended) (Note 6)
Open-Loop Voltage Gain
(Single Ended) (Note 6)
+8
+8
-8
-50
±Vee= ±15V
t:s 25ms
-8
-50
mV
rnA
50
50
rnA
11
11
7
rnA
(Short Circuit to Ground)
AV51 - 1
AV5
±Vee= ±5V
RL = 2kfl
VouT =±2V
5-285
ffi......
-30
-7
~
II
::s
~
mV
Input Offset Voltage
Temperature SensItivity
+I'B
-55°C to +125°C
= 50 ohm; ambient temperature range =
02
PARAMETER
................... ±5 to ±20 VDC
Ambient Temperature Range ••••••••••
NOTES:
1. The absolute maximum negative Input voltage IS equal to the negative
power supply voltage.
±16
±15
±16
±15
V
50
25
50
25
V/mV
10
10
V/mV
1/86, Rev. A
~
~
>.t.l
C5
------l!EMD
JM38510/11401/11402l11403/11404111405/11408 JAN JFET-INPUT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS at Vcc from ±5V to ±20V; source resistance = 50 ohm; ambient temperature range =
-55°C to +125°C and figure 1, unless otherwise noted. (Continued)
02 LIMITS
PARAMETER
SYMBOL
CONDITIONS
Transient Response
Rise Time
TR ltr )
±Vcc= ±15V. RL = 2kO, Av= 1
C L = 100pF, See Figure 2
V'N=50mV
Transient Response
Overshoot
TRIOS)
±Vcc= ±15V, RL = 2kO, Av= 1
C L = 100pF, See Figure 2
V,N =50mV
Slew Rate
SR(+)
and
SR(-)
V,N = ±5V, ±Vcc= ±15V
Av = I, See Figure 2
TA = 25°C
TA= -55°C, +125°C
Settling Time
ts(+)
and
ts(-)
±Vcc= ±15V (0 1% error)
TA=25°C. Av=-1
See Figure 3
Noise (Relerred to Input)
Broadband
N,(BB)
Noise (Relerred to Input)
Popcorn
N,(PC)
MIN
MAX
UNITS
100
100
ns
40
40
%
7.5
VI"s
10
5
1500
1500
ns
±Vcc= ±20V, TA = 25'C
Bandwidth = 5kHz
10
10
",V rms
±Vcc =±20V, TA =25°C
Bandwidth = 5kHz
80
80
"Vpk
NOTES:
Bias currents are actually Junction leakage currents which double
(approximately) lor each 10'C increase In junction temperature TJ.
Measurement 01 bias current specilled at TJrather than TA, since normal
warm-up thermal transients will allect the bias currents. The measurements
lor bias currents must be made within 25ms or 5 loop time constants alter
power IS lirst applied to the device for test. Measurement at TA =-55°C IS
not necessary since expected values are too small lor typical test systems.
2. Bias current Is sensitive to power supply voltage, common-mode voltage
and temperature as shown by thelollowlng typical curves:
IS
_____
-' _'- _: _:"-'t_nA_I~,-/~I~ I- 'I~- - l"
-60
-25
26
50
75
TAI'el
100
3. Negative 1,9 minimum limits reflect the characteristics of device with bias
current compensation.
4. CMR is calculated from V,O measurements at VCM = +15V and -15V.
5. Continuous limits shall be considerably lower. Protection lor shorts to
either supply exists providing that TJ(max) S 175°C
Because of thermal feedback ellects from output to input, open-loop gain
not guaranteed to be linear or positive over the operating range. These
reqUirements, II needed, should be speCified by the user in additional
procurement documents.
IIB(pAI
400
200
-15/-'0
OS LIMITS
MAX
MIN
IS
-5
5-286
1/86, Rev. A
_ _ _ _ _-l~JM38510/11401/11402/11403/11404/11405/11406 JAN JFET-INPUT OPERATIONAL AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range ............................ ±22V
Input Voltage Range (Note 1) ...................... ±20V
Differential Input Voltage Range ................... ±40V
Lead Temperature (Soldering, 60 sec) ............. 300°C
Junction Temperature ............... Tj = 175°C (Note 3)
Storage Temperature Range ........... -65°C to +150°C
Output Short-Circuit Duration........ Unlimited (Note 2)
3.
Short circuit may be to ground to e,thersupply. Rating applies to +125'C
case temperature or +75°C ambient temperature.
For short-term test (In the specific burn Min and life test configuration when
required and up to 168 hours maXimum), TJ = 275°C
RECOMMENDED OPERATING CONDITIONS
Supply Voltage Range ................... ±5 to ±20 VDC
Ambient Temperature Range .......... -55° C to +125°C
NOTES:
The absolute maximum negative mput voltage IS equal to the negative
power supply voltage.
ELECTRICAL CHARACTERISTICS at Vcc from ±5V to ±20V; source resistance
-55°C to +125°C and figure 1, unless otherwise noted.
= 50 ohm; ambient temperature range =
03 LIMITS
PARAMETER
Input Offset
Voltage
SYMBOL
V,o
MIN
CONDITIONS
±Vee ~ ±5V. VeM
TA ~ 25'C
±Vee~ ±20V
VeM ~ ±15V, OV
~
OV
-5
Input Offset Current
tiV,o
tiT
1'0
+I'B
±20V
OV
±Vee ~ ±20V, VeM ~ OV.
T, ~ 25'C
T, ~ 125'C
10
30
-10
-20
-20
20
20
-20
-20
20
20
pA
nA
300
50
-100
-10
300
50
pA
nA
±Vee ~ ±20V. -15V" VeM " OV
T, ~ 25'C
t::;25ms
T, ~ 125'C
-100
-10
100
50
-100
-10
100
50
pA
nA
Adjustment for
Input Offset Voltage
V,oADJ(+)
V,oADJ(-)
±Vcc= ±20V
±Vee ~ ±20V
Output Short-Circuit Current
(for Pos,tive Output) (Note 5)
1081 +1
±Vee~ ±15V
t:525ms
(Short Circuit to Ground)
1051 -)
t-:;25ms
±Vee ~ ±20V
V'N~
±15V
±Vee~
85
85
dB
85
85
dB
+8
+8
-8
-50
-8
-50
mV
mA
±15V
50
50
11
11
mA
(Short Circuit to Ground)
TA~-55'C
Icc
±Vee~±15V, TA~+25'C
7
7
TA ~ +125'C
Output Voltage Swing
(Maximum)
VoP
±Vee ~ ±20V, RL ~ 10kO
±Vee ~ ±20V, RL ~ 2kO
Open-Loop Voltage Gain
(Single Ended) (Note 6)
A VS (+)
±Vee ~ ±20V. VOUT ~ ± 15V
RL ~ 2kO, TA ~ 25'C
-55'C"TA ,,+125'C
Open-Loop Voltage Gain
(Single Ended) (Note 6)
/JV/'C
-100
-10
+Vee ~ 10V, -Vee ~ -20V
+Vee ~ 20V, -Vee ~ -10V
Avsl -)
mA
±16
±15
±16
±15
V
50
25
50
25
V/mV
10
10
V/mV
±Vee~
Avs
±5V
RL ~ 2kO
VOUT~ ±2V
5-287
p...
~
~
-30
pA
nA
CMR
Supply Current
2.5
3500
60
Input Voltage Common-Mode
Rejection (Note 4)
(Note 5)
-25
-100
-10
+PSRR
-PSRR
.......
~
3500
60
Power Supply
Rejection Ratio
~
;:..t.:I
~
-100
-10
-I'B
(for Negative Output)
UNITS
±Vee ~ ±20V, VeM ~ +15V
T, ~ 25'C
t,,25ms
T, ~ 125'C
±Vee ~ ±15V, VeM ~ +10V
T, ~ 25'C
t,,25ms
T, ~ 125'C
Input Bias Current
(Note 1)
(Note 2)
(Note3)
Output Short-Circuit Current
MAX
-2
-7
±Vee~
VeM~
06 LIMITS
MIN
mV
-55'C" TA" +125'C
Input Offset Voltage
Temperature SensitiVity
MAX
1/86, Rev. A
~
0
.......
~
;:..t.:I
p...
0
_ _ _ _-t[fMDJM38510111401/11402111403/11404/11405/11406 JAN JFET-INPUT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS at Vcc from ±5V to ±20V; source resistance = 50 ohm; ambient temperature range =
-55°C to +125°C and figure 1, unless otherwise noted. (Continued)
03 LIMITS
PARAMETER
MIN
SYMBOL
CONDITIONS
Transient Response
RlaeTlme
TR 'trl
±Vcc= ±15V. Rl = 2kfl. Av= 5
C l = l00pf. See Figure 2
V'N=50mV
Transient Response
Overshoot
TR 'OSI
±Vcc= ±15V. Rl = 2kfl. Av= 5
C l = 100pF. See Figure 2
V'N=50mV
Slew Rate
SR(+)
and
SR(-)
V'N=±1V. ±Vcc=±15V
Av = 5. See Figure 2
TA =25'C
TA =-55'C. +125'C
Settling Time
18(+)
and
18(-)
±Vcc= ±15V (0.1% error)
TA =25'C. Av=-5
See Figure 3
Noise (Referred to Input)
Broadband
N,(BB)
Noise (Referred to Input)
Popcorn
N,\PC)
450
na
25
25
%
VI"s
40
25
30
20
±Vcc=±20V. TA =25'C
Bandwidth = 5kHz
10
10
p.V rms
±Vcc=±20V. TA =25'C
Bandwidth = 5kHz
80
80
"Vpk
'nA I
____-'-_.L'_::_J...L_ ...1,..:/=--,L--'-,
_.L'___.... TAI'CI
-50
-26
25
50
75
100
Negat,ve I'B minimum limits reflect the characte"stlcs of device with bias
current compensation.
4. CMR Is calculated from V,c measurements at VCM = +15V and -15V.
5 Conllnuous limits shall be considerably lower. Protection for shorts to
either supply exists providing that TJ(max) ,; 175' C.
6. Because of thermal feedback ellects from output to Input. open-lOOp gain
IS not guaranteed to be linear or positive over the operating range. These
requrrements, If needed, should be specified by the user in additional
procurement documents.
:tVee '" :l:2QV
-,,,e~;::z=---....!!!!!!~=:e:::-L--_Vcm(V)
10
450
ns
400
-5
UNITS
800
200
-16/-10
MAX
MIN
800
NOTES:
1. Bias currents are actually Junction leakage currents which double
(approximately) for each 10'C increaae in junction temperature TI'
Measurement of bias current is specified at TJratherthan TA• since normal
warm-up thermal transients will allect the bias currents. The measurements
for bias currents must be made within 25ms or 5 loop time constants alter
power islirst applied to the device for test. Measurement at TA = -55' C is
not necessary since expected values are too small for typical test systems.
2 Bias current is sensitive to power supply voltage. common-mode voltage
and temperature as shown by the following typical curves:
".,oAl
06 LIMITS
MAX
16
5-288
1/86, Rev. A
-----I~ JM38510111401/11402111403/11404/11405/11406 JAN JFET-INPUT OPERATIONAL AMPLIFIERS
(SEE NOTE 3)
150pF
-- -If- -
K5b
560pF
K5a
!----A
499kO
(SEE NOTE 3)
--If----
II
NO
CONNECTION
102kn
(SEE NOTE 1)
499n
499Mn
499n
102kn
(SEE NOTE 3)
=*=
I
I
49.9kn
I
±1%
-=E:-
NOTES:
1. All resistors are ±O.I% tolerance and all capacitors are ±10%
tolerance, unless otherwise specified.
2. Precautions shall be taken to prevent damage to the D.U.T. during
insertion into socket and change of state of relays (I.e. disable
voltage supplies. current limit ±Vcc. etc.).
3. Compensation capacitors should be added as required for test
circuit stability Two general methods for stability compensation
exist. One method is with a capacitor for nulling amp feedback. The
other method is with a capacitor in parallel with the 49.9kn closedloop feedback resistor. Both methods should not be used simultaneously. Proper wiring procedures shall be followed to prevent
unwanted coupling and oscillations, etc. Loop response and
settling time shall be consistent with the test rate such that any
value has settled for at least five loop time constants before the
value is measured.
4. Adequatesettling time should be allowed such that each parameter
has settled to within 5% of Its final value.
5.
All relays are shown in the normal de-energized state.
S
The nulling amplifier shall bea M38510/10101XXX. Saturation of the
nulling amplifier IS not allowed on tests where the E (Pin 5) value IS
measured.
7. The load resistors 2050nand 11.1 kn yield effective load resistances
of 2kn and 10kn respectively.
8. Any oscillation greater than 300mV in amplitude (peak-to-peak)
shall be cause for device failure.
Figure 1. Test Circuit for Static Tests
5-289
1/86, Rev. A
~ JM38510111401/11402/11403/11404/11405/11406
10pF (SEE NOTE 2)
I~~~
o.1MF
JAN JFET-INPUT OPERATIONAL AMPLIFIERS
DEVICE TYPES
DEVICE TYPES
~
~
K9a
:;
5
'50
-
-
225
-
-45
50
i
~VO
-
w
'"~
0
>
Vo
~
=>
i=
=>
0
'5-
TIME (ns)
NOTES:
1. Resistors are ± 1.0% tolerance and capacitors are ± 10% tolerance
2 This capacitance includes the actual measured value with stray and
wire capacitance.
3 PrecautIOns shall be taken to prevent damage to the D U T during
insertIOn into socket and In applying power
+5
~
w
+25
~
!!
~
~
5
-25
-5
'----W;;;A-;";V7.Eo;oF;;COR"'M='- - - - . . . L - - :W
:::cA""V;;:E-::cFO"'R;;M:-:3;---TIME (us)
{POSITIVE SLEW RATE)
PARAMETER
SYMBOL
TR
(tr)
TR 10si
SR (+J
SR (-I
DEVICE
TYPE
INPUT PULSE
SIGNAL AT
tr ~ SOns
OUTPUT
PULSE
SIGNAL
EQUATION
ALL
+50mV
WAVEFORM 1
ALL
+50mV
WAVEFORM 1
TA (OS! "" 100 (.lVOIVO! %
-5V to +5V STEP
-1Vto+1VSTEP
WAVEFOAM2
WAVEFORM 2
SA
+5V to -5V STEP
-lV to +lV STEP
WAVEFORM 3
WAVEFORM 3
SR (-) = ..lVOI-)/.lt(-l
01,02,04, 05
03,06
01, 02, 04, 05
03,06
(NEGATIVE SLEW RATE)
TR ItrJ-.lt
(+) "" .1VO (+)/.lt(+)
Figure 2. Test Circuit for Transient Response and Slew Rate.
5-290
1/86, Rev. A
-----I1fMD
JM38510/11401111402/11403/11404/11405/11406 JAN JFET-INPUT OPERATIONAL AMPLIFIERS
II
NOTES:
Resistors are ± 1.0% and capacitors are ± 10%, unless otherwise
specified.
2 Precaution shall be taken to prevent damage to the D.U.T during
insertion Into socket and In applying power
3. For device types 01,02,04 and OS, 51 is open, A v =-1 and V,N = 10V.
4. For device types 03 and 06, 51 is closed, Av = -5 and Y,N = 2V.
5. Settling time, ts measured on Pm 5, IS the Interval dunng which the
summing node is not nulled within the specified accuracy referred
to the output.
Figure 3. Test Circuit for Settling Time
BURN-IN
Devices supplied by PMI have been subjected to burn-in per
Method 1015 of MIL-STD-883 using test condition C with
circuit shown on Figure 4 or test condition F using circuit
shown on Figure 5.
+40V
47kD.
OPEN
47k.\1
Figure 4. Test Circuit, Burn-In (Steady-State Power and
Reverse Bias) and Operating Life Test
NOTE
ALL RESISTORS ARE ±20%
Figure 5. Accelerated Burn-In and Life Test Circuit
5-291
1/86, Rev. A
J~38510/13501/13502
ULTRA-LOW OFFSET VOLTAGE
OPERATIONAL AMPLIFIERS
Precision Monolithics Inc.
FEATURES
•
•
•
•
Low Vos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .• 25!N
Low Vos Drift ............................. 0.61'V/oC
Low Noise ................................ 0.61' Vpop
Wide Supply Voltage Range ............. ±4.5V to ±20V
MILITARY DEVICE TYPE
GENERIC-INDUSTRY TYPE
01
OPO?A
02
OPO?
For an 833-processed device with improved electrical specifications, review the OP-07 data sheet.
ORDERING INFORMATION
JAN SLASH SHEET
PMI DEVICE
JM38510/13501 BPB
JM38510/13502BPB
OPO? AZ2/38510
OPO?Z2/38510
JM38510/13501 BGC
JM38510/13501 BGA
OPO? AJ1/38510
OPO? AJ3/38510
JM38510/13502BGC
OPO? J1/38510
PIN CONNECTIONS
TR'EM
Vas :R~:
S
Vas
-IN 2
GOUT
+IN 3
5NC
4
GENERAL DESCRIPTION
8-PIN HERMETIC DIP
TIN-REFLOW LEAD TYPE
(Z2-Suffix)
This data sheet covers the electrical requirements for a monolithic, low offset voltage, internally-compensated operational
amplifier as specified in MIL-M-38510!135 for device type 01 and
02. Devices supplied to this data sheet are manufactured and
tested at PMI's MIL-M-38510 certified facility and are listed in
QPL-38510.
v-
(CASE)
TO-99
GOLD-PLATE LEAD TYPE
(J1-Sufflx)
SOLDER-DIPPED LEAD TYPE
(J3-Suffix)
Complete device requirements will be found in MIL-M-38510
and MIL-M-38510!135 for Class B processed devices.
POWER AND THERMAL CHARACTERISTICS
Case
Oulline
GENERIC CROSS-REFERENCE INFORMATION
This cross-reference information is presented for the convenience of the user. The generic-industry types listed may not
have identical operational performance characteristics across
the military temperature range or reliability factors equivalent to
the MIL-M-38510 device.
Package
Maximum Allowable Maximum Maximum
Power Dissipation
°JC
°JA
P
Dual-In-Line 208mW @ TA
= 125'C
50'C/W
120°C/W
G
8-Lead CAN 16?mW @ TA
= 125'C
60'C/W
150'C/W
SIMPLIFIED SCHEMATIC
V+o---~----------~----------.-----~~-.----~~----~------~-+--+---~
7
R7
*NOTE
R2A AND RlB ARE
ELECTRONICALLY
ADJUSTED ON CHIP
AT FACTORY,
R9
OUTPUT
6
NONINVERTING
INPUT
R,O
INVERTING
INPUT
4
v-o---~--------------------~--~----~--~--------~--~--~
5-292
1/86, Rev. A
~~~~~~~-t~ JM38510/13501/13502 ULTRA-LOW OFFSET VOLTAGE OPERATIONAL AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Supply Voltage (Vce) ••.••.••.•.•.•..•.•....••..• ±22V
Input Voltage Range (V,NI .......•.•.••••.•..•...• ±VCC
Differential Input Voltage Range •.•..•.•.•.•..••..• ±30V
Output Short-Circuit Duration (Note 1 I
Lead Temperature (Soldering, 60 sec) ..•.•.•••... +300°C
Storage Temperature Range .••...•.•..•. -65°C to +150°C
Junction Temperature (TJI ..•..•.•....•.•.•...•. +150°C
Maximum Power Dissipation (Pol (Note 2) ••.••.•• 500mW
Supply Voltage Range •••..••.••..••...••. ±4.5V to ±20V
Ambient Temperature Range .•••..••..•• -55°C to +125°C
NOTES:
1 Output may be shorted to ground Indefinitely at Vs = ±15V, TA = 25°C
Temperature and/or supply voltages must be limited to ensure diSsipation
rating
IS
not exceeded
Maximum power diSSipation versus ambient temperature
ELECTRICAL CHARACTERISTICSat±4.5V:S Vcc:S±20Vand -55°C:STA:S 125°C, Rs=50n unnulled, unless otherwise noted.
01 LIMITS
PARAMETER
SYMBOL
Input Offset Voltage
V,o
Input Offset Voltage
:,v,ol.n
Temperature Sensitivity
+1 18
CONDITIONS
TA = 25°C
TA = 25°C
MIN
-liB
Input Offset Current
Power Supply Rejection Ratio
"0
TA = 25°C
02 LIMITS
MIN
MAX
UNITS
-75
-200
75
200
~V
-06
06
-13
13
~VloC
(Note 1)
-2
-4
-3
-6
3
4
(Note 1)
-2
-4
4
-3
-6
3
6
(Note 1)
-2
-4
4
-28
-56
28
56
+PSRR
10
10
-PSRR
+Vee = 15V, -Vee = -20V to -5V
TA = 25°C
10
10
+PSRR
+Vee = 20V to 5V. -Vee = -15V
20
20
-PSRR
+Vee = 15V. -Vee = -20V to -5V
20
20
PSRR
Vee = ±4 5V to ±20V
TA = 25°C
10
10
Vee = ±4 5V to ±20V
20
20
nA
nA
~VIV
Tested at VeM = 0, Vee = ±15V
Due to the Inherent warm-up drift, testing shall occur no sooner than three
(3)
minutes after applicatIOn of power
5-293
.....:l
p..
~
~
0
......
~
~
C5
NOTES:
2
~
......
......
25
60
+Vee = 20V to 5V. -Vee = -15V
TA = 25°C
ge
~
-25
-60
(Notes 1, 2)
Input Bias Current
TA = 25°C
MAX
1/86, Rev. A
--------I~ JM38510/13501/13502 ULTRA-LOW OFFSET VOLTAGE OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICSat±4.5V5 Vcc 5±20Vand -55°C5TA 5125°C, Rs=500unnulled, unless otherwise noted.
(Continued)
01 LIMITS
PARAMETER
Common-Mode Rejection Ratio
SYMBOL
CONDITIONS
VCM
~
±13V, TA
VCM
~
MIN
~
25'C. Vcc
~
±15V
MAX
02 LIMITS
MIN
110
110
±13V
106
106
Via Adj 1+1
TA = 25°C I Note 11
05
Via Adj 1-1
TA = 25°C I Note 11
MAX
CMAA
dB
05
Adjustment for Input Offset
Output Short-Circuit Current
mV
'051+1
t:s; 25ms INote 1, 3)
1081 - 1
t~
Icc
Output Voltage SWing (Mlnlmuml
Vap
(Single-Ended 1
Slew Aate
Input NOise Voltage DenSity
Avs
~
Voltage
enp~p
-65
65
25'C
65
(Note 1)
5
AL
~
1kll, INote 11
-10
10
-10
10
RL
~
2kll. I Note 11
-12
12
-12
12
TA
~
25'C
300
200
rnA
V
fa
fa
~
~
~
fa~
Low Frequency Input NOise
-65
-0.5
rnA
SA(+I. SA(-I V,N
e,
-05
25ms (Note 1, 3)
TA
Supply Current
Open Loop Voltage Gain
UNITS
f
~
10V. TA
10Hz
100Hz
1kHz
(Note 21
~
25'C. I Note 11
TA = 25°C, I Note 1)
0 1Hz to 10Hz, TA
~
25'C, INote 11
200
150
08
VlmV
08
VlMS
18
14
12
18
14
12
nV/VHZ
06
0.6
MVp_p
NOTES:
Tested at VCM ~ 0, Vee ~ ±15V
VauT ~ 0 to +10V for Avsl+1 and VauT ~ 0 to -10V for AVS'-' AL ~ 2,0001l
3 Continuous short-Circuit lImits are considerably less than the indicated test lImits, since maximum power diSSipation cannot be exceeded.
5-294
1/86, Rev. A
JM38510/13503
LOW-NOISE PRECISION
OPERATIONAL AMPLIFIER
Precision Monolithics Inc.
FEATURES
•
•
•
•
•
•
Low VOS' ...•.••.....................•...... 25!-'V
Low VOS Drllt ............................. 0.6!-,VloC
High Speed ••.....•.........•........•.... 1.7V1!-,s
Low Noise .••..•..•.........•..•..•..•... 0.18!-'Vp_p
High Gain ..•...•..•...•................ 1.0 Million
Wide Supply Voltage Range .•••.•••••.• ±4.5V to ± 18V
MILITARY DEVICE TYPE
GENERIC-INDUSTRY TYPE
03
OP27A
For an 833-processed device with improved electrical specifications, review the OP-27 data sheet.
PIN CONNECTIONS
ORDERING INFORMATION
JAN SLASH SHEET
.~:.:~:~
PMI DEVICE
J M3851 0/13503B PC
OP27 AZ2/38510
J M3851 0113503BGC
OP27 AJ1/38510
+INV,'NC
4 V- (CASE)
GENERAL DESCRIPTION
This data sheet covers the electrical requirements for a monolithic, low offset vOltage, internally-compensated operational
amplifier as specified in MIL-M-38510/135 for device type 03.
Devices supplied to this data sheet are manufactured and
tested at PMI's MIL-M-38510 certified facility and are listed in
QPL-38510.
8-PIN HERMETIC DIP
TIN REFLOW LEAD TYPE
TO-99
GOLD PLATE LEAD TYPE
(Z2-Sullix)
(J1-Suffix)
POWER AND THERMAL CHARACTERISTICS
Case
Outline
Complete device requirements will be found in MIL-M-38510
and MIL-M-38510/135 for Class B processed devices
GENERIC CROSS-REFERENCE INFORMATION
Package
Maximum Allowable Maximum Maximum
Power Dissipation
BJC
BJA
P
Dual-In-Line 20BmW @ TA ; 125°C
50°C/W
120°C/W
G
8-Lead CAN 167mW@TA ; 125°C 60°C/W
150°C/W
This cross-reference information is presented for the convenience of the user. The generic-industry types listed may not
have identical operational performance characteristics across
the military temperature range or reliability factors equivalent to
the MIL-M-38510 device.
SIMPLIFIED SCHEMATIC
r-------~--------~--------~--~----~------._------~_.--~~~v+
R3
R4
Vos Ad)
R"
OUTPUT
NONINVERTING
INPUT (o:+I-+-<~~-+---fi::,--~
INVERTING
INPUT
t-J
~4-~~~
________
~
______
~
* R1 &. R2 ARE PERMANENTL V ADJUSTED
AT WAFER reST
L---------------~--
5-295
__ ______ __________
~
~
~~--~~~~v-
1/86, Rev. A
---------I!EM:D
JM38510/13503 LOW-NOISE PRECISION OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Supply Voltage (VCC) •.•.•.••••••..•..••••...•..• ±22V
Input Voltage Range (VIN) ...•.....•....•.•....•.• ±Vcc
Differential Input Voltage Range ....•..••.•..•.•... ±0.7V
Output Short-Circuit Duration (Note 1)
Lead Temperature (Soldering. 60 sec) ...•........ +300·C
Storage Temperature Range .....•.•..... -65·C to + 150·C
Junction Temperature (TJ ) •••••••••••••••••••••• +150·C
Maximum Power Dissipation (Po) (Note 2) .....•.. 500mW
Supply Voltage Range .••••...•..•......•. ±4.5V to ±18V
Ambient Temperature Range .•.•.••..... -55·C to +125·C
NOTES:
1 Output may be shorted to ground ,ndeflnitely at Vs = ±15V. TA = 25'C
Temperature and/or supply voltages must be limited to ensure dissipation
rating Is not exceeded.
2. Maximum power dissipation versus ambient temperature.
ELECTRICAL CHARACTERISTICS at ±4.5V:5 VCc:5 ±20V and -55·C:5 TA:5125·C. Rs = 50n unnulled. unless otherwise noted.
03 LIMITS
PARAMETER
SYMBOL
Input Ollset Voltage
v,o
Input Ollset Voltage
Tempersture Sensitivity
_W,o/·H
+I'B
CONDITIONS
MIN
MAX
UNITS
TA = 25'C
-25
-60
25
60
p.V
-06
0.6
p.VI'C
(Note 1)
-40
-60
40
60
(Note I)
-40
-60
40
60
(Note 11
-35
-50
35
50
TA = 25'C
(Notes 1. 2)
nA
Input Bias Current
-I'B
Input Ollset Current
Power Supply AeJecllon Aatlo
TA = 25'C
TA = 25'C
1'0
+PSRA
+Vee = 18V to 5V. -Vee = -15V
TA = 25'C
10
-PSAA
+Vee = 15V, -Vee = -18V to -5V
TA = 25'C
10
+PSAA
+Vee = 18V to 5V, -Vee =-15V
16
-PSAA
+Vee = 15V, -Vee = -18V to -5V
16
Vee = ±4 5V to ±18V
TA = 25'C
10
PSAA
Vee = ±4 5V to ±18V
16
nA
p.V/v
NOTES:
1. Tested at VeM = 0, Vee = ±15V
2. Due to the inherent warm-up drift, testing shall occur no sooner than three (3) minutes after appllcallon of power
5-296
1/86, Rev. A
----------I~ JM38510/13503 LOW-NOISE PRECISION OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at ±4.5V::; Vee::; ±20V and -55°C::; TA ::; 125°C, Rs = 500 unnulled, unless otherwise noted.
(Continued)
03 LIMITS
PARAMETER
Common-Mode Rejection Ratio
SYMBOL
114
Via Ad] (-)
1081 + 1
t,; 25ms, (Note 1,3)
-50
1081 - 1
t,; 25ms, (Note 1,3)
eMRR
Via Adj (+)
Supply Current
MIN
= ±11V, TA = 25'e, Vcc = ±15V
VCM = ±11V, VCC = ±15V
TA = 25'e, (Note 1)
TA = 25'e, (Note 1)
Adjustment for Input Offset
Output Short-CircUit Current
CONDITIONS
Icc
VCM
VoP
TA
= 25'e
mV
-05
4
= 500!!. (Note 11
RL = 2k!!. (Note 11
= 25'e
Slew Rate
SR(+I, SR(-I Y,N
Input NOIse Voltage DenSity
en
fa
fa
fa
e np _p
f = 0 1Hz to 10Hz
TA = 25'e, (Note 11
In
fa
fa
fa
Input NOise Current Density
0.5
(Note 11
Avs
Voltage
dB
108
rnA
Open Loop Voltage Gain
(Single-Ended I
Low Frequency Input NOise
UNITS
70
-10
RL
Output Voltage Swing (Minimum)
MAX
TA
-115
(Note 2)
= 10Hz
= 100Hz
= 1kHz
TA
TA
10
V
= 10V, TA = 25'e, (Note 11
= 10Hz
= 100Hz
= 1kHz
rnA
115
1000
500
V/mV
17
V/~s
5.5
40
3.8
nV/VHZ
018
J.l.Vp.p
40
15
08
pA/VHZ
= 25'e, (Note 11
= 25'e, (Note
11
II
~
~
......
.....
~
p..,
~
~
0
......
~
~
p..,
NOTES:
0
1.
2
Tested at VCM = 0, Vcc = ±15V
Your = a to +10V for Avs (+) and Your
3.
Continuous short-circuit limits are considerably less than the Indicated test limits, Since maximum power diSSipation cannot be exceeded
= 0 to -10V for AvsH
RL
= 2,000!!
5-297
1/86, Rev. A
Table of Contents 1
Ordering Information 2
Product Assurance Program 3
Industry Cross Reference 4
Operational Amplifiers 5
Instrumentation Amplifiers 6
Voltage Followers/Buffers 7
Voltage Comparators 8
Matched Transistors 9
Voltage References 10
Digital-to-Analog Converters 11
Analog-to-Digital Converters 12
Analog Switches/Multiplexers 13
Sample-and-Hold Amplifiers 14
Special Functions 15
Communications Products 16
Package Information 17
Sales Offices, Representatives and Distributors 18
INSTRUMENTATION
AMPLIFIER
Prcclsion MOllolithics Inc.
6-3
Introduction
6-3
Definitions
6-5
AMP-Ol
Low-Noise Precision
Instrumentation Amplifier
6-27
AMP-OS
Fast-Settling JFET
Instrumentation Amplifier
8-2
INSTRUMENTATION
AMPLIFIER
P . . ecIsion MouoiIthics Inc.
INTRODUCTION
An instrumentation amplifier is a committed
gain block that amplifies a differential input voltage by a precisely set gain. Voltages common
to both inputs are rejected. Differential gain is
set by one or two external resistors, usually over
a range of 1 to 1000. Instrumentation amplifiers
are designed to have very high input impedance;
this assures that the gain will not be affected by
signal-source impedances (Rs). Input bias current must be low to minimize input offset voltages due to 18 X Rs. In the output stage, low
output impedance keeps the output voltage from
being affected by the load impedance. Instrumentation amplifiers employ heavy negative
feedback which provides excellent gain linearity
even at high gains.
Most instrumentation amplifiers have an output
sense pin (SENSE) and a reference input pin
(REFERENCE). As shown in Figure 1, the load is
usually connected between SENSE and REFERENCE points. The amplifier will make VOUT =
GVIN despite voltage drops between OUTPUT
and LOAD, or from REFERENCE to GROUND.
The SENSE and REFERENCE inputs are particularly useful for driving remote loads with high
currents. The essential characteristics of
instrumentation amplifiers-high input impedance, low output impedance, low offset, high
linearity, stable gain, and ability to reject
common-mode inputs-make them very useful
for amplifying low-level transducer outputs.
Transducers such as thermocouples, straingage bridges, biological probes, and current
shunts produce small differential signals superimposed on common-mode bias voltages. In
addition, common-mode ground noise is usually
prevelant. Instrumentation amplifiers are gain
blocks that have been optimized for preamplifying low-level transducer signals in the presence
of common-mode noise.
The PMI AMP-01 instrumentation amplifier has
all the features needed for use in high-accuracy
data-acquisition systems and high-performance
instruments:
• Wide Gain Range (0.1:5 G :510,000)
• High Input Impedance
• Low Input Bias Current
• Low Offsets
• Excellent Linearity
Unlike conventional instrumentation amplifiers,
the AMP-01 has high output drive capability; it
can supply ±10V at ±50mA. This enhanced output drive capability enables the AMP-01 to drive
unusually large capacitive loads without encountering stability problems.
Gain of the AMP-01 is set by the ratio of two
external resistors according to:
- (20 X RSCALE)
VOUTR
VIN
GAIN
Output sense and reference pOints are provided.
The AMP-01 is unusually versatile, and can be
connected as a precision current source or
high-performance op amp as well as a conventional instrumentation amplifier.
The AMP-05 JFET instrumentation amplifier
supports high-speed applications, such as
analog-multiplexed data acquisition and fast
analog signal proceSSing. The design offers a
1010'S maximum settling-time to 12 bits at gains
up to 1000, and with 14-bit linearity. The AMP-05
also provides on-board circuits for guard
driving, which maximizes input signal speed,
and a precision current source for transducer or
reference excitation.
AMP-05 features include:
• Input bias current, 25pA max.
• High gain-bandwidth product, 200M Hz
• 6V/Io's output slew-rate with a 1000pF load
• High common-mode rejection, 110dB min.
DEFINITIONS
Offset at the output of an
instrumentation amplifier consists of two terms,
a gain-dependent input-offset-voltage and a
gain-independent output-offset-voltage. Total
offset is the sum of the unity-gain-output-offset
(Voos) plus input-offset (VIOS) multiplied by the
gain (Output Offset = Voos + GVIOS). At high
gain, the input offset term dominates. For the
AMP-01 and AMP-05, both input and output
offsets can be trimmed externally if desired .
Voltage Offsets -
~
~
~
::s
~
:..(
Z
0
~
f-i
§
~
~
(-<
v:l
Z
t--I
INSTRUMENTATION
AMPLIFIER
Precision Monolithics Inc.
Power Supply Rejection - Offset changes with
variations in the power supply voltages. The
ability of the instrumentation amplifier to reject
fluctuations in power supply voltage is referred
to as "power supply rejection". It varies with
gain and is different for the positive and negative supplies. The offset change referred-toinput (RTI) is usually specified in dB form. For
example, a PSR of 100dB at a gain of 1000 would
imply an input-offset-voltage change of lO#-,Vper-volt of power supply change. The output
offset change-per-volt of power-supply change
would be 10mV. PSR in the specification tables
is measured at DC.
to reject common-mode inputs. The ratio of
change in output voltage to a change in
common-mode input voltage is the commonmode gain (/1VO//::",vCM). The ratio of differential gain (G) to common-mode gain (ACM) is
defined as common-mode rejection ratio
(CMRR). The CMR is conventionally specified in
log form; CMR = 20 10glO CMRR.
Input Bias Current - The input bias currents
are currents flowing into (or out of) the two
inputs of the amplifier. The value given in the
specification table is the maximum current into
either input. Input offset current is the difference between the two input bias currents.
As an example, consider a CMR of 120dB at a
gain of 1000 with a common-mode input range
of ±10V. The 120dB of CMR implies a CMRR of
1000/ACM = 1,000,000, or a common-mode gain
of 1/1000. A ± 10V common-mode input will
cause an output change of ± 10mV for this
example (CMR = 120dB, G = 1000).
Since instrumentation amplifiers are designed to
amplify differential signals while rejecting
common-mode inputs, common-mode gain
stays essentially independent of gain setting.
Therefore, CMRR increases almost directly with
the gain setting.
Input Voltage Range - The linear operating
range of the amplifier is referred to as the "input
voltage range". When operating at high gains
with small differential inputs, this input range is
the common-mode input voltage range.
Gain Equation Accuracy - Differential gain is
given as a function of the two external resistors.
For the AMP-01 and AMP-OS, the relationship is
ideally 20 x Rs/RG. The specified accuracy
limits indicate the accuracy of the amplifier
given an exact ratio of Rs/RG.
Common-Mode Rejection - Common-mode
rejection (CMR) specifies the amplifiers ability
INSTRUMENTATION AMPLIFIER FUNCTIONAL DIAGRAM
SIGNAL SOURCE
SENSE
I
OUTPUT
VCM
RSCALE
":" GROUND
6-4
AMP. 01
LOW-NOISE
PRECISION INSTRUMENTATION AMPLIFIER
Precision Monolithics Inc.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
PIN CONNECTIONS
Low Offset Voltage ......................... 50/LV Max
Very Low Offset Voltage Drift ........... 0.3/LV/oC Max
Low Noise. . . . . . . . . . . . . . . . .. 0.12/LVp _p (0.1 Hz to 10Hz)
Excellent Output Drive ............... ±10V at ±50mA
Capacitive Load Stability ...................... to 1/LF
Gain Range ............................ 0.1 to 10,000
Excellent Linearity ................. 16-Bit at G = 1000
High CMR ...................... 125dB Min (G = 1000)
Low Bias Current ........................... 3nA Max
May be Configured as a Precision Op-Amp
Output-Stage Thermal Shutdown
18-PIN HERMETIC DIP
(X-Suffix)
I
'Make no electrical connection to these pms
ORDERING INFORMATIONt
PACKAGE
CERDIP
18-PIN
AMP01AX'
AMP01BX'
AMP01EX
AMP01FX
LCC
z
'i'
OPERATING
TEMPERATURE
RANGE
AMP01BTC/883
MIL
MIL
IND
IND
Voos NULL
6
NC
,
AMP-01 BTC/883
28-LEAD LCC
(TC-Suffix)
"For devices processed In total compliance to MIL-STD-BS3, add /883 after
part number Consult factory for 883 data sheet
t All commercial and industrial temperature range parts are available with
burn-In For ordering Information see 1986 Data Book, Section 2
SIMPLIFIED SCHEMATIC
r-----------~~-------------------------Ov+
r----------O+voP
>-------0 OUTPUT
-IN
o----"o/W----------t-------------j-------,
+IN
O---¥,Iy--.---[,
'-----------0 -VOP
R3
47Skn
I--~-~M.--O SENSE
R4
25kn
'---------~------~----------~_----_ov-
Manufactured under the following U S. patents 4,471.321 and 4,503,381
6-5
1/86, Rev. A
---------;[fM!) AMP-G1 LOW-NOISE PRECISION INSTRUMENTATION AMPLIFIER
c. The current-feedback design is immune to CMR degradation when series resistance is added to the reference
input. A small (trimmable) offset change results from
added resistance, e.g. a printed circuit track.
GENERAL DESCRIPTION
The AMP-01 is a monolithic instrumentation amplifier
designed for high-precision data acquisition and instrumentation applications. The design combines the conventional
features of an instrumentation amplifier with a high-current
output stage. The output remains stable with high capacitance loads (1I'F), a unique ability for an instrumentation
amplifier. Consequently, the AMP-01 can amplify low-level
signals for transmission through long cables without requiring an output buffer. The output stage may be configured as a
voltage or current generator.
.
The AMP-01 utilizes low-drift thin-film resistors to minimize
output offset temperature drift. A feedback voltage-to-current
converter is employed having high linearity and low noise,
particularly at low frequencies. Parameter shifts during
packaging are eliminated by a post-assembly trimming
technique which electronically adjusts the output offset
voltage.
Input offset voltage is very low (20I'V) which generally
eliminates the external null potentiometer. Temperature
changes have minimal effect on offset; TCVlos is typically
0.15I'VI·C. Excellent low-frequency noise performance is
achieved with a minimal compromise on input protection.
Bias current is very low, less than 10nA over the military
temperature range. High common-mode rejection of 130dB,
16-bit linearity at a gain of 1000, and 50mA peak output
current are achievable simultaneously. This combination
takes the instrumentation amplifier one step further towards
the ideal amplifier.
The AMP-01 input transistors Q1 and Q2 feed active loads,
yielding stage gain in excess of 4000 (see simplified
schematic) The output amplifier, A1, is a two-stage design
having a gain of about 50,000 driving a 1000 load. Overall
gain of 2 x 108 yields excellent linearity, even at high
closed-loop gains.
AC performance complements the superb DC specifications.
The AMP-01 slews at 4.5V1l's into capacitive loads of up to
15nF, settles in 50l's to 0.01% at a gain of 1000, and boasts a
healthy 26MHz gain-bandwidth product. These features
make the AMP-01 ideal for high-speed data-acquisition
systems.
Superbeta transistors use a new transistor geometry resulting in an input noise of only 5nVly"HZ at G = 1000. Noise
includes contributions from the gain-setting resistor and
internal overload-protection resistor. The input stage
achieves an offset voltage drift of less than 0.3I'VI·C
(E Grade).
Gain is set by the ratio of two external resistors over a range
of 0.1 to 10,000. A very low galn-temperature-coefficlent of
10ppml"C is achievable over the whole gain range. Output
voltage swing is guaranteed with three load resistances; 500,
5000, and 2kO. Loaded with 5000, the output delivers ± 13.0V
minimum. A thermal shutdown circuit prevents destruction
of the output transistors during overload conditions.
The AMP-01 uses a unique two-pole compensation scheme
where the load capacitance is incorporated into the dominate
pole. Stable operation results even with high capaCitance
loads. The high output current capability (90mA peak) allows
the 4.5V1l's slew-rate to be maintained with load capacitance
as high as 15nF.
The AMP-01 can also be configured as a high-performance
operational amplifier. In many applications, the AMP-01 can
be used in place of op-amp/power-buffer combinations.
ABSOLUTE MAXIMUM RATINGS (Note 2)
Low bias current is achieved by using lon-implanted superbeta transistors combined with a new bias-current cancellation system, patents applied for. Input bias current remains
below 10nA over the military temperature range, -55·C
to +125·C.
Supply Voltage ................................... ± 18V
Internal Power Dissipation (Note 1) ...•.......... 500mW
Common-Mode Input Voltage ...•...•.... Supply Voltage
Differential Input Voltage, RG2: 2kO •....••...•..... ±20V
RG< 2kO ................ ±10V
Output Short-Circuit Duration •............••.• Indefinite
Storage Temperature Range. • . . . • . . . .. -65· C to + 150· C
Operating Temperature Range
AMP-01A, B ........................ -55·Cto+125·C
AMP-D1E, F ......................... -25·Cto+85·C
Lead Temperature (Soldering, 60 sec) .•......•..•. 300· C
DICE Junction Temperature (Ti) .•.•... -65· C to + 150· C
THEORY OF OPERATION
An instrumentation amplifier, unlike an op amp, requires
precise internal feedback. The two techniques presently in
use are resistive and current feedback.
The AMP-01 employs the current feedback approach which
has significant advantages over resistive feedback. Advantages of current-feedback are:
a. The technique yields a very high common-mode rejection ratio. The AMP-01 CMR is in excess of 130dB at a
gain of 1000.
b. The gain of the current feedback design is set by the
ratio of two external resistors. Using external resistors
allows any practical gain to be set with high precision
and very low gain temperature coefficient.
PACKAGE TYPE
18-Pln Hermetic DIP (X)
MAXIMUM AMBIENT
TEMPERATURE FOR
RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
100'0
10mW/'C
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
2. Absolute ratings apply to both DICE and packaged parts. unless otherwise
noted.
6-6
1/86, Rev. A
[fMDAMP-01 LOW-NOISE PRECISION INSTRUMENTATION AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, Rs = 10k!l, RL = 2k!l,
TA
= 25° C, unless otherwise noted.
AMP-01A
PARAMETER
AMP-01B
TYP
MAX
TA = 25'C
-55'C" TA" +125'C
20
40
SYMBOL
CONDITIONS
V,OS
MIN
MIN
TYP
MAX
UNITS
50
80
40
60
100
150
0.3
0.3
1.0
/"V/'C
OFFSET VOLTAGE
I nput Offset Voltage
/"V
TCV ,OS
-55'C" TA " +125'C
0.15
Output Offset Voltage
Voos
TA =25'C
-55'C" TA" +125'C
1
3
3
6
2
6
6
10
mV
Output Offset Voltage Drift
TCVoos
RG = c (Note 3)
-55'C" TA " + 125'C
20
50
50
120
/"VI'C
Input Offset Voltage Drift
Offset Referred to Input
vs. Positive Supply
V+ = +5V to +15V
PSR
Offset Referred to Input
vs. Negative Supply
V- = -5V to -15V
G = 1000
G=100
G= 10
G=1
120
110
95
75
130
130
110
90
110
100
90
70
120
120
100
80
dB
-55'C" TA " +125'C
G = 1000
G= 100
G= 10
G= 1
120
110
95
75
130
130
110
90
110
100
90
70
120
120
100
80
dB
G=
G=
G=
G=
110
95
75
55
125
105
85
65
105
90
70
50
115
95
75
60
dB
110
95
75
55
125
105
85
65
105
90
70
50
115
95
75
1000
100
10
1
~
~
......
dB
60
Input Offset Voltage Trim
Range
Vs = ±4.5V to ±18V
(Note 1)
±6
±6
mV
Output Offset Voltage Trim
Range
Vs= ±4.5V to ±18V
(Note 1)
±100
±100
mV
1
4
la
TA =25'C
-55'C" TA " +125'C
Input Bias Current Drift
TCl a
-55'C" TA" +125'C
40
TA = 25'C
-55'C" TA ,,+125'C
0.2
0.5
TClos
-55'C"TA ,,+125'C
3
Input ReSIstance
R'N
DifferentIal, G = 1000
Differential, G" 100
Common-Mode, G = 1000
Input Voltage Range
IVR
TA = 25' C (Note 2)
-55'C" TA" + 125'C
Input Offset Current
los
Input Offset Current Drift
3
10
6
1.0
3.0
0.5
1.0
6
15
50
nA
pAl'C
2.0
6.0
nA
pAl'C
INPUT
Common-Mode.
CMR
Rejection
10
20
±10.5
±10.0
±10.5
±10.0
V
125
120
100
85
130
130
120
100
115
110
95
75
125
125
110
90
dB
-55°C S TA~ +125°C
G=I000
G=100
G=IO
G=I
120
115
95
80
125
125
115
95
110
105
90
75
120
120
105
90
dB
2.
Refer to section on common-mode rejection
AMP-01AX specIficatIon changed from lOOI"V/'C to 50/"V/'C, effective
January, 1985
respectively.
6-7
.--
Gfl
VCM = ±10V, lkfl
source imbalance
G = 1000
G = 100
G= 10
G=1
NOTES:
I. Vms and Voos nulling has minimal affect on TCV,DS and TCVDDS,
~----
10
20
-~--~~~--.----
--------
~
p..
Z
0
~
~
~
:E
~
INPUT CURRENT
Input Bias Current
~
~
PSR
-55'C" TA" +125'C
G = 1000
G= 100
G= 10
G=1
II
1/86, Rev. A
G;
Z
......
[fM!)
AMP-01 LOW-NOISE PRECISION INSTRUMENTATION AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs= ±1SV, Rs= 10kO, RL = 2kO,
TA =
2SoC, unless otherwise noted.
AMP-01E
PARAMETER
MIN
SYMBOL
CONDITIONS
Input Offset Voltage
V,OS
TA =2S"C
-2S"CSTA S+85"C
Input Offset Voltage Drift
TCV ,OS
-2S"CSTA S+85"C. (Note 21
Voos
TA = 2S"C
-25"CS TAS +85"C
TCVoos
Ra = ... (Note 2)
-2S"CSTA S+85°C
AMP-01F
TYP
MAX
20
40
MIN
TYP
MAX
50
80
40
60
100
150
0.15
03
0.3
1.0
~VI"C
3
3
6
2
6
6
10
mV
20
100
50
120
~VI"C
UNITS
OFFSET VOLTAGE
Output Offset Voltage
Output Offset Voltage Drift
Offset Referred to Input
vs Positive Supply
V+ = +SV to +lSV
Offset Referred to Input
vs Negative Supply
V- = -SV to -15V
PSR
PSR
G= 1000
G= 100
G=10
G=l
120
110
95
75
130
130
110
90
110
100
90
70
120
120
100
80
-2s oCSTA S+8SoC
G = 1000
G=100
G=10
G=l
120
110
95
75
130
130
110
90
110
100
90
70
120
120
100
G = 1000
G=100
G=10
G=l
110
95
75
55
125
105
85
65
105
115
95
75
-2s oCSTA S+85°C
G = 1000
G= 100
G=10
G=l
110
95
75
55
125
105
85
65
105
90
70
50
~V
dB
dB
80
90
70
50
dB
60
115
95
75
60
dB
Input Offset Voltage Trim
Range
Vs = ±4.5V to ± 18V
(Note 1)
±6
±6
mV
Output Offset Voltage Tnm
Range
Vs =±45Vto±18V
(Note 1)
±100
±100
mV
INPUT CURRENT
Input Bias Current
Ie
TA =25"C
-25°CSTA S+SSoC
Input Bias Current Dnft
4
3
10
2
6
1.0
3.0
0.5
1.0
6
15
nA
TCl e
-25°CSTA S+85°C
40
Input Offset Current
los
TA = 25°C
-25°C 5 TAS +85°C
0.2
0.5
Input Offset Current Drift
TClos
-2s oCSTAS+85°C
3
5
pN°C
Input ReSistance
R'N
Differential. G = 1000
Differential, G 5 100
Common-Mode, G = 1000
10
20
1
10
20
GO
Input Voltage Range
IVR
TA = 25°C (Note 3)
-25°C:5 TA:5 + 85°C
50
pArC
2.0
6.0
nA
INPUT
Common-Mode
Rejection
CMR
±10.5
±10.0
±10.5
±10.0
V
VCM = ±10V, lkO
source Imbalance
G = 1000
G=l00
G=10
G=l
125
120
100
85
130
130
120
100
115
110
95
75
125
125
110
-25°C 5 TAS +85°C
G = 1000
G=l00
G=10
G=l
120
115
95
80
125
125
115
95
110
105
90
120
120
105
75
90
NOTES:
1. V,OS and Voos nulhng has minimal affect on TCV,os and TCVoos,
respectively.
dB
90
dB
Sample tested
3
6-8
Refer to section on common-mode rejection
1/86, Rev. A
IEWAMP-01 LOW-NOISE PRECISION INSTRUMENTATION AMPLIFIER
ELECTRICAL CHARACTERISTICS at
Vs
=
± 15V,
Rs
= 10kO, RL = 2kO, TA = 25° C, unless otherwise noted.
AMP-01A1E
PARAMETER
SYMBOL
MIN
CONDITIONS
AMP-01B/F
TYP
MAX
03
0.6
0.0007
MIN
TYP
MAX
UNITS
0.5
0.8
%
10k
VIV
0.005
0.005
0.005
0.010
00007
0005
0005
0.007
0.015
%
10
5
15
ppm/oC
GAIN
G ~ 20 x Rs
RG
Gam Equation
Accuracy
Accuracy Measured
from G ~ 1 to 1000
Gain Range
01
G
G ~ 1000
G~ 100
G~10 (Note1)
Nonlinearity
10k
G~1
Temperature Coefficient
1 S G S 1000
(Notes 1, 2)
GTe
5
01
OUTPUT RATING
II
±130
±13.0
±25
±13.8
±13.5
±40
±13.0
±13.0
±2.5
±138
±13.5
±4.0
V
Over Temp.
(Note3)
±120
±12.0
±138
±13.5
±12.0
±12.0
±13.8
±13.5
V
~
......
Positive Current limit
Output-to-Ground Short
60
100
120
60
100
120
rnA
Negative Current Limit
Output-to-Ground Short
60
90
120
60
90
120
rnA
::sp..
Capacitive Load Stability
1SGS1000
No Oscillations, (Note 1)
01
Output Voltage
Swing
RL ~ 2kO
RL ~ 5000
RL ~ 500
V OUT
RL ~ 2kO
RL ~5OOO
Thermal Shutdown
!,F
165
°C
G~100
G~
10
G~1
NOise Current Density, RTI
fO~
In
1kHz, G ~ 1000
10
59
540
10
59
540
nV/yHZ
0.15
0.15
pAlyHZ
G ~ 1000
G~ 100
9 np _p
012
016
14
13
G~10
G~1
Input Noise Current
i
0.12
016
1.4
13
o 1Hz to 10Hz, G ~ 1000
ne-e
2
570
100
82
26
G~1
BW
Slew Rate
SR
G~10
ts
To 0 01 %, 20V step
G=1
G=10
G~ 100
G = 1000
Settling Time
e
pAp-
G=10
G= 100
G = 1000
35
4.5
12
13
15
50
3.0
570
100
82
26
kHz
4.5
VI!,s
12
13
15
50
!,s
NOTES:
1.
2.
3.
Guaranteed by design.
Gain tempec does not include the effects of gam and scale reSistor
tempec match.
-55°C STA S + 125°C for AlB grades, -25°C STA S + 85°C for ElF grades
6-9
-
-
----,.~-
-.
-
-
-----_.-----
:E
~
E-<
Z
......
!,Vp.p
DYNAMIC RESPONSE
Smail-Signal
Bandwidth (-3dB)
Z
~
rJ)
o 1Hz to 10Hz
Input NOise Voltage
0
f-'
1kHz
G ~ 1000
fo~
en
~
~
NOISE
Voltage Density, RTI
~
Z
165
Junction Temperature
Temperature
01
ge
----------
1/86, Rev. A
_ _ _ _ _ _ _ _-I~AMP-01 LOW-NOISE PRECISION INSTRUMENTATION AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs= ±15V. Rs= 10kO. RL = 2kO. TA = 25°C. unless otherwise noted.
AMP-01A1E
PARAMETER
SYMBOL
CONDITIONS
MIN
AMP-018/F
TYP
MAX
50
65
MIN
TYP
MAX
UNITS
SENSE INPUT
Input Resistance
R'N
Input Current
"N
Voltage Range
35
Relerenced to V-
35
280
-10.5
(Note I)
50
65
280
+15
-10.5
65
35
kO
"A
+15
V
65
kO
REFERENCE INPUT
Input Resistance
R'N
Input Current
liN
Voltage Range
35
50
280
Relerenced to V(Note I)
-10.5
50
280
+15
-10.5
"A
+15
V
VlV
Gain to Output
POWER SUPPLY -25'CS TA S+65'C lor ElF Grades. -55'C S TAS +125'C lor AlB Grades
Supply Voltage Range
Vs
+V linked to +Vop
-V linked to -Vop
Quiescent Current
10
+V linked to +Vop
-V linked to-Vop
±IS
±4.5
3.0
3.4
4.8
4.8
±4.5
3.0
3.4
±18
V
4.8
4.8
rnA
NOTE:
I. Guarantesd by design.
6-10
1/86, Rev. A
---------I~ AMP·en LOW·NOISE PRECISION INSTRUMENTATION AMPLIFIER
DICE CHARACTERISTICS
1. RG
2. RG
3. -INPUT
4. VOOS NULL
5. VoosNULL
6.
7.
8.
9.
TEST PIN"
SENSE
REFERENCE
OUTPUT
10.
11.
12.
13.
14.
15.
16.
17.
18.
V- (OUTPUT)
VV+
V+ (OUTPUT)
Rs
Rs
VIOS NULL
VIOS NULL
+INPUT
"Make no electrical connection
II
For additional DICE information refer to
1986 Dala Book, Section 2.
DIE SIZE 0.110 X 0.148 Inch, 16,280 sq. mils
(2.79 X 3.76 mm, 10.50 sq. mm)
WAFER TEST LIMITS at VS= ±15V, Rs= 10kO, RL = 2kO, TA= 25°C, unless otherwise noted.
PARAMETER
SYMBOL
Input Offset Voltage
VIOS
Output Offset Voltage
Voos
Offset Referred to Input
vs. Positive Supply
PSR
CONDITIONS
V+ ~ +5V to +15V
G ~ 1000
G~ 100
G~10
G~1
Offset Referred to Input
vs. Negative Supply
PSR
Input Bias Current
Ie
Input Offset Current
los
Input Voltage Range
IVR
V- ~ -5V to -15V
G ~ 1000
G ~ 100
G~10
G~
1
AMp·01NBC
AMp·01GBC
LIMIT
LIMIT
UNITS
60
120
I'VMAX
S
mVMAX
120
110
95
75
110
100
90
70
110
95
75
55
105
90
70
50
4
Guaranteed by CMR Tests
dBMIN
dBMIN
nAMAX
3
nAMAX
±10
±10
VMIN
125
120
100
85
115
110
95
75
06
OS
% MAX
±13
±13
±2.5
±13
±13
±2.5
VMIN
VCM~
Common-Mode
Rejection
G~
CMR
±10V
1000
G~100
G~
10
G~1
Gain Equation
Accuracy
Output Voltage Swing
G ~ 20 X Rs
RG
VOUT
RL ~2kn
RL ~ 500n
RL ~ 50n
dB MIN
Output·Current Limit
Output·to-Ground Short
±60
±60
mAMIN
Output-Current Limit
Output-to-Ground Short
±120
±120
rnA MAX
4.S
4.S
rnA MAX
Quiescent Current
10
+ V Linked to + Vop
-V Linked to -Vop
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations In assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specificatiOns based on dice lot qualification through sample lot assembly and testing.
6·11
1/86, Rev. A
_ _ _ _ _ _ _ _-lOOAMP-01 LOW-NOISE PRECISION INSTRUMENTATION AMPLIFIER
TYPICAL ELECTRICAL CHARACTERISTICS at Vs= ±15V, Rs= 10kO, RL = 2kO,
PARAMETER
SYMBOL
Input Offset
Voltage Dnft
TCV,os
Output Offset
Voltage Drift
TCVoos
Input Bias
Current Drift
Input Offset
Current Drift
CONDITIONS
RG=ao
TCI.
TA =
25°C, unless otherwise noted.
AMP-01NBC
AMP-D1GBC
TYPICAL
TYPICAL
UNITS
0.15
0.30
p.vrc
20
50
p.VloC
40
50
pArC
5
pArC
0.0007
0.0007
%
TClos
Nonlinearity
G = 1000
Voltage Noise Density
en
G = 1000
fO= 1kHz
5
Current NOIse Density
in
G = 1000
fO= 1kHz
0.15
0.15
pAlv'HZ
Voltage Noise
e np _p
G = 1000
o 1Hz to 10Hz
0.12
012
p.Vp_p
Current NOise
inp_p
G = 1000
0.1Hz to 10Hz
2
pA p_p
Small-Signal
Bandwidth (-3dB)
BW
G = 1000
26
26
kHz
Slew Rate
SR
G=10
4.5
4.5
VII'S
Settling Time
ts
To 0.01%. 20V Step
G = 1000
50
50
p.s
6-12
nVlv'HZ
1/86, Rev. A
------------I~ AMP-Ol LOW-NOISE PRECISION INSTRUMENTATION AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT OFFSET VOLTAGE
VB TEMPERATURE
50
rv~=±,L
40
~
30
w
"
20
o~
>
-10
~
-20
>-
-
_ TA
,..,.-
10
~
o
INPUT OFFSET VOLTAGE
VB SUPPLY VOLTAGE
V
/ V-
I'"
!25
0
t-v~="L
C
~
1-
I""':
r--..
"-
..............
-1
3-
-2
4
-3
........ r-....
r--...
-4
-40
-75 -50 -25
-6
0
25
50
75
lOa 125
o
150
TEMPERATURE (Oe)
\
10
05
00
::20
±15
:,:25
1
25
50
75
±15
±lQ
'jblgb
G
v~~"= 2V p p
Vs == ±15V
120
130
T~I~}5°C
G'" 100
100
V
02
120
±20
COMMON-MODE REJECTION
VB FREQUENCY
140
~5'='~;~~
04
V
±5
POWER SUPPLY VOLTAGE (VOLTS)
TA == 2S"C
I"'-.. r-....
o
100 125 150
COMMON-MODE REJECTION
VI VOLTAGE GAIN
140
"~V
-15
0
TEMPERATURE (oC)
06
V-
-
-10
-2
-75 -50 -25
INPUT OFFSET CURRENT
VI TEMPERATURE
V5 =
0
-05
POWER SUPPL Y VOLTAGE (VOL lS)
08
1~
_T)25 C
05
1
±10
==
~
V
r'-...
1
~
10
/
\
25
INPUT BIAS CURRENT
VB SUPPLY VOLTAGE
J
\
0
TEMPERATURE (OC)
15
-05
o
-5_ _ -25
20
1\
15
±20
±15
V~ = "~V
TA ='25°C
-10
±lQ
INPUT BIAS CURRENT
VI TEMPERATURE
25
20
±5
POWER SUPPLY VOLTAGE (VOLTS)
OUTPUT OFFSET VOLTAGE
CHANGE VB SUPPLY VOLTAGE
-02
r-....
2
-4
-30
00
r-....
UNIT No
..........
-2
OUTPUT OFFSET VOLTAGE
VB TEMPERATURE
80
G
60
==
10
~
G == 1
40
~
110
20
-04
-06
-75 -50 -25
100
0
25
50
75
TEMPERATURE (OC)
100 125 150
/
1
0
10
100
VOL TAGE GAIN, G
6-13
1k
10k
1
10
100
1k
10k
lOOk
FREQUENCY (Hz)
1/86, Rev_ A
II
---------;m
AMP·01 LOW·NOISE PRECISION INSTRUMENTATION AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
COMMON·MODE VOLTAGE
RANGE VB TEMPERATURE
16
POSITIVE PSR
FREQUENCY
140
V~M .10
J±,L .....
14
12
10
11111
I I
100
Vl",L
80
I I
60
80
60
I
20
20
25
50
o
75
100
10
1
125 150
1k
100
+1V
I'
G=1
lOOk
100
10
1k
10k
lOOk
CLOSED·LOOP OUTPUT
IMPEDANCE VB FREQUENCY
I~S.' ±\J~I
RL = 2kl1
'"
14
12
0,
FREOUENCY (Hz)
30
V~.I ±I,~~
25
"~
10k
MAXIMUM OUTPUT SWING
vs FREQUENCY
20
/
10
Vs = :t15V
TA = 2SoC
avs
G=1
MAXIMUM OUTPUT VOLTAGE
VB LOAD RESISTANCE
w
~ ~'ig'
~
FREQUENCY (Hz)
16
100
40
0
=1000
G - 100
1\
TEMPERATURE (OC)
18
~
G
120
ll.VS = :tlV
J±5l
o
~0
140
TA = 2SoC
40
I
-50 -25
IIIII I
G = 100
G=1
VB
1e~'~ ±;J~I
111111
0'1000
120
I I
~75
NEGATIVE PSR
FREQUENCY
VB
15
0
>
~
"
"0
10
~
o
10
100
1K
10K
o
100
LOAD RESISTANCE In)
60
TOTAL HARMONIC
DISTORTION
VB LOAD RESISTANCE
0.02
I
I 11111111
007 _ Vs'" !15V
RL =600n
006 :- Your = 20V p-p
W~II,J
20
1M
FREQUENCY (Hz)
008
W~~,JJ
40
100k
TOTAL HARMONIC
DISTORTION
VB FREQUENCY
V~I~I ±1SV
TA = 2SOC
W~~,JJo
10k
FREQUENCY (Hz)
CLOSED·LOOP VOLTAGE
GAIN VB FREQUENCY
80
1k
1\
GJoJo
I
004
001
V
003
0-1
~
G ;"10,
002
1/ tl'dl~~
-20
001
-40
10
,
005
W~I,
1
vl. Lt III
G= 100
f = 1KHz
VOUT = 20Vp-p
100
lk
10k
FREQUENCY (Hz)
lOOk
1M
o
.......
~
10
100
FREQUENCY (Hz)
6·14
1K
10K
o
100
1K
10K
LOAD RESISTANCE (n)
1/86, Rev. A
---------I~ AMP-G1 LOW-NOISE PRECISION INSTRUMENTATION AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
SLEW RATE VB
LOAD CAPACITANCE
SLEW RATE VB
VOLTAGE GAIN
SETTLING TIME TO 0.01%
VB VOLTAGE GAIN
70
~sl.lll!~~
Js!'~W
r- 20V
STEP
60
50
4
-"
w
Ii
40
"
30
:Ji
20
>-
o
2
~
,
100p
VOLTAGE GAIN, G
VOLTAGE NOISE DENSITY
VB FREQUENCY
"
lOOn
'0"
,"
o
\
1--++ttItttI--t-tttttttt-+tttllllll,oU
,
1000
'00
VOL lAGE GAIN, G
RTI VOLTAGE NOISE
DENSITY VB GAIN
POSITIVE SUPPLY CURRENT
VB SUPPLY VOLTAGE
_TA=2~OC
Vs = +15V
t= 1KHz
~
~,oo._.
'0
:Ji
0
z
--- -
:Ji
o2
w
W
:1
~ 'O~I;I~I
~
C;
0
>
~
0
'0
LOAD CAPACITANCE (F)
".~s:J
15
~';
,"
i.-"
'0
,
'0
'00
,.
'0'
,L-~~llllL-~~llllL-~-W~
1
10
FREQUENCY (Hz)
NEGATIVE SUPPLY CURRENT
VB SUPPLY VOLTAGE
-s
r--
7
TA =
100
lK
o
o
±5
±10
±15
±20
VOLTAGE GAIN, G
POWER SUPPLY VOLTAGE (VOLTS)
POSITIVE SUPPLY CURRENT
VB TEMPERATURE
NEGATIVE SUPPLY CURRENT
VB TEMPERATURE
v~."L
2~OC
6
5
-4
-3
-2
,
o
o
-
.......-'
,
o
±5
±10
±15
POWER SUPPLY VOLTAGE (VOLTS)
±20
-75 -50 -25
0
25
50
75
TEMPERATURE (Oe)
6-15
100 125
150
~'::75~-5~0---!2::-5~0-2:!::5"'-:5!:0--:7'::5--:-!'O::-0-':-':2:-5-7.'50
TEMPERATURE (OC)
1/86, Rev. A
---------I~ AMP-01 LOW-NOISE PRECISION INSTRUMENTATION AMPLIFIER
INPUT AND OUTPUT OFFSET VOLTAGES
GAIN
Instrumentation amplifiers have independent offset voltages
associated with the input and output stages. While the initial
offsets may be adjusted to zero, temperature variations will
cause shifts in offsets. Systems with auto-zero can correct
for offset errors, so initial adjustment would be unnecessary.
However, many high-gain applications don't have auto zero.
For these applications, both offsets can be nulled, which has
minimal effect on TCVlos and TCVoos.
The AMP-01 uses two external resistors for setting voltage
gain over the range 0.1 to 10,000. The magnitudes of the
scale resistor, Rs, and gain-set resistor, RG, are related by the
formula: G =20X RglR G, where G is the selected voltage gain
(Refer to Figure 1).
The input offset component is directly multiplied by the
amplifier gain, whereas output offset is independent of gain.
Therefore, at low gain, output-offset-errors dominate, while
at high gain, input-offset-errors dominate. Overall offset
voltage, Vos, referred to the output (RTO) is calculated as
follows;
v.
"N
Vos(RTO)= (VIOSX G) + Voos.. ······ .. ········ .. ·· .. ·· .. ······· .. ··········.. · (1)
where VIOS and Voos are the input and output offset voltage
specifications and G is the amplifier gain. Input offset nulling
alone is recommended with amplifiers having fixed gain
above 50. Output offset nulling alone is recommended when
gain is fixed at 50 or below.
-IN
In applications requiring both initial offsets to be nulled, the
input offset is nulled first by short-circuiting RG, then the
output offset is nulled with the short removed.
VOL TAGE GAIN, G
The overall offset voltage drift TCVos, referred to the output,
is a combination of input and output drift specifications.
Input offset voltage drift is multiplied by the amplifier gain, G,
and summed with the output offset drift;
RS
( 20R'G )
v-
Figure 1. Basic AMP-Ol connections for gains 0.1 to 10,000.
The magnitude of Rs affects linearity and output referred
errors. Circuit performance is characterized using Rs = 10kO
when operating on ±15 volt supplies and driving a ±1 0 volt
output. Rs may be reduced to 5kfl in many applications
particularly when operating on ±5 volt supplies or if the
output voltage swing is limited to ±5 volts. Bandwidth is
Improved with Rs = 5kfl and this also increases commonmode rejection by approximately 6dB at low gain. Lowering
the value below 5kfl can cause Instability in some circuit
configurations and usually has no advantage. High voltage
gains between two and ten thousand would require very low
values of RG. For Rs = 10kfl and Av=2000we get RG = 1000;
this value is the practical lower limit for RG. Below 1000,
mismatch of wlrebond and resistor temperature coefficients
will introduce significant gain tempco errors. Therefore, for
gains above 2,000, RG should be kept constant at 1000 and
Rs increased. The maximum gain of 10,000 is obtained with
Rs set to 50kO.
TCVos (RTO) = (TCVlosx G) + TCVoos·············· .. ·· .. ·········· .. (2)
where TCVlos is the input offset voltage drift, and TCVoos is
the output offset voltage specification. Frequently, the
amplifier drift is referred back to the input (RTI) which is then
equivalent to an input signal change;
TCVos(RTI)=TCVlos+ TCVoos···········································(3)
G
For example, the maximum input-re'terred drift of an
AMP-01 EX set to G = 1000 becomes;
TCVos (RTI) = 0.3JlV/oC + 100JlVrC = O.4JlV/oC max.
1000
INPUT BIAS AND OFFSET CURRENTS
Input transistor bias currents are additional error sources
which can degrade the input Signal. Bias currents flowing
through the signal source resistance appear as an additional
offset voltage. Equal source resistance on both inputs of an
IA will minimize offset changes dueto bias current variations
with signal voltage and temperature. However, the difference
between the two bias currents, the input offset current,
produces a non-trimmable error. The magnitude of the error
is the offset current times the source resistance.
Metal-film orwirewound resistors are recommended for best
results. The absolute values and TC's are not too important,
only the ratio metric parameters.
AC amplifiers require good gain stability with temperature
and time, but DC performance is unimportant. Therefore, low
cost metal-film types with TC's of 50ppm/oC are usually
adequate for Rs and RG. Realizing the full potential of the
AMP-01 's offset voltage and gain stability requires precision
metal-film or wirewound resistors. Achieving a 15ppm/oC
gain tempco at all gains requires Rs and RG temperature
coefficient matching to 5ppm/o C or better.
Acurrent path must always be provided between the differential inputs and analog ground to ensure correct amplifier
operation. Floating inputs, such as thermocouples, should
be grounded close to the signal source for best commonmode rejection.
6-16
1/86, Rev. A
------------I~ AMP-01 LOW-NOISE PRECISION INSTRUMENTATION AMPLIFIER
vOltage gain. For example, at 25° C, IVR is specified as ±10.5
volt minimum with ±15 volt supplies. Using a ±10 volt
maximum swing output and substituting the figures in (4)
simplifies the formula to:
1M
Vs - +15V
§
100
k~
CMVR = ±
AS
I"
10k
100
1
10
100
VOL TAGE GAIN
. . . . (5)
ACTIVE GUARD DRIVE
'"
1k
Rejection of common-mode noise and line pick-up can be
improved by using shielded cable between the signal source
and the IA. Shielding reduces pick-up, but increases input
capacitance, which in turn degrades the settling-time for
signal changes. Further, any imbalance in the source resistance between the inverting and noninverting inputs, when
capacitively loaded, converts the common-mode voltage into
a differential voltage. This effect reduces the benefits of
shielding. AC common-mode rejection is improved by"bootstrapping" the input cable capacitance to the input signal, a
technique called "guard driving". This technique effectively
reduces the input capacitance. A Single guard-driving signal
is adequate at gains above 100 and should be the average
value of the two inputs. The value of external gain resistor RG
is split between two resistors RG1 and RG2; the center tap
provides the required signal to drive the buffer amplifier
(Figure 2).
10k
RG AND Rs SELECTION
Gain accuracy is determined by the ratio accuracy of Rs and
RG combined with the gain equation error of the AMP-01
(0.6% max for AlE grades).
All instrumentation amplifiers require attention to layout so
thermocouple effects are minimized. Thermocouples formed
between copper and dissimilar metals can easily destroy the
TCVos performance of the AMP-01 which is typically
O.15p.V/0 C. Resistors themselves can generate thermoelectric
EMF's when mounted parallel to a thermal gradient. "Vis hay"
resistors are recommended because a maximum value for
thermoelectric generation is specified. However, where
thermal gradients are low and gain TC's of 20-50ppm are
sufficient, general-purpose metal-film resistors can be used
for RG and Rs.
GROUNDING
The majority of instruments and data acquisition systems
have separate grounds for analog and digital Signals. Analog
ground may also be divided into two or more grounds which
will be tied together at one point, usually the analog powersupply ground. In addition, the digital and analog grounds
may be joined, normally at the analog ground pin on the
A-to-D converter. Following this basic grounding practice is
essential for good circuit performance (Figure 3).
COMMON-MODE REJECTION
Ideally, an instrumentation amplifier responds only to the
difference between the two input signals and rejects
common-mode voltages and noise. In practice, there is a
small change in output vOltage when both inputs experience
the same common-mode voltage change; the ratio of these
vOltages is called the common-mode gain. Common-mode
rejection (CMR) is the logarithm of the ratio of differentialmode gain to common-mode gain, expressed in dB. CMR
specifications are normally measured with a full-range input
voltage change and a specified source resistance unbalance.
Mixing grounds causes interactions between digital circuits
and the analog signals. Since the ground returns have finite
resistance and inductance, hundreds of millivolts can be
developed between the system ground and the data acquisition components. Using separate ground returns minimizes
the current flow in the sensitive analog return path to the
system ground point. Consequently, noisy ground currents
from logic gates do not interact with the analog signals.
The current-feedback design used in the AMP-01 inherently
yields high common-mode rejection. Unlike resistive feedback designs, typified by the three-op-amp lA, the CMR is not
degraded by small resistances in series with the reference
input. A slight, but trimmable, output offset voltage change
results from resistance in series with the reference input.
Inevitably, two or more circuits will be joined together with
their grounds at differential potentials. In these situations,
the differential input of an instrumentation amplifier, with its
high CMR, can accurately transfer analog information from
one circuit to another.
The common-mode input voltage range, CMVR, for linear
operation may be calculated from the formula'
CMVR = ± (IVR
5
For all gains greater than or equal to 10, CMVR is ±10 volt
minimum; at gains below 10, CMVR is reduced.
' " AG
1k
(10 -~)
SENSE AND REFERENCE TERMINALS
The sense terminal completes the feedback path for the
instrumentation amplifier output stage and is normally
connected directly to the output. The output signal is
specified with respect to the reference terminal, which is
normally connected to analog ground.
JV~~TI) ..... (4)
IVR is the data sheet specification for input voltage range;
VOUT is the maximum output signal; and G is the chosen
6-17
1/86, Rev. A
II
----------t~ AMP-01
LOW-NOISE PRECISION INSTRUMENTATION AMPLIFIER
+15V
• C5
AV
=
+---____T..J lOJ.iF
R4
VOLTAGE GAIN, G" (20 x RS)'
RGt
NC
500 WITH COMPONENTS SHOWN
SENSE
.,NQ-- " - - - - - - - - - - - < ; > VOUT • ±3V MAX
5011
LOAD
-IN 0------"-1
C2
o 04711F
VOLTAGE GAIN, G =
CO:GRs)
-1---'
o
J...
~'IV\"""'-----l~1
047,uF
RESISTORS R, AND R2 REDUCE Ie DISSIPATION
'-----------------e--------o-15V
Figure 5. Driving son loads.
6-19
1/86, Rev. A
----------l~ AMP-01 LOW-NOISE PRECISION INSTRUMENTATION AMPLIFIER
Protection can also be achieved by connecting back-to-back
9.1V zener diodes across the differential inputs. This technique does not affect the input noise level and can be used
down to a gain of 2 with minimal increase in input current.
Although voltage-clamping elements look like short circuits
at the limiting voltage, the majority of signal sources provide
less than 50mA, producing power levels that are easily
handled by low-power zeners.
to several hundred milliwatts (for example, the 4-20mA
current transmitter application, Figure 8). Excessive dissipation will cause thermal shutdown of the output stage thus
protecting the device from damage. A heatsink is recommended in power applications to reduce the die temperature.
Several appropriate heatsinks are available; the Thermalloy
6010B is especially easy to use and is inexpensive. Intended
for dual-in-line packages, the heatsink may be attached with
a cyanoacrylate adhesive. This heatsink reduces the thermal
resistance between the junction and ambient environment to
approximately 80° C/W. Junction (die) temperature can then
be calculated by using the relationship:
Simultaneous connection of the differential inputs to a lowimpedance signal above 10V during normal circuit operation
is unlikely. However, additional protection involves adding
1000 current-limiting resistors in each signal path priorto the
voltage clamp; the resistors increase the input noise level to
just 5.4nVlyHZ (refer to Figure 6).
Tj-T.
Pd = - - OJ.
Input components, be they multiplexers or resistors, should
be carefully selected to prevent the formation of thermocouple junctions which would degrade the input signal.
where T J and T. are the junction and ambient temperatures
respectively, OJ' is the thermal resistance from junction to
ambient, and Pd is the device's internal dissipation.
OVERVOLTAGE PROTECTION
Instrumentation amplifiers invariably sit at the front end of
instrumentation systems where there is a high probability of
exposure to overloads. Voltage transients, failure of a transducer, or removal of the amplifier power supply while the
signal source is connected may destroy or degrade the
performance of an unprotected amplifier. Although it is
impractical to protect an IC internally against connection to
power lines, it is relatively easy to provide protection against
typical system overloads.
*OPTIONAl PROTECTION
RESISTORS, SEE TEXT
+15V
LINEAR INPUT RANGE,
±5VMAXIMUM
DIFFERENTIAL PROTECTION
TO ±30V
lOon lW*
"N<>--'\NI.-.---j
91V lW
Your
ZENERS
loon lW*
-IN <>--'\NI,....---j
The AMP-01 is internally protected against overloads for
gains of up to 100. At higher gains, the protection is reduced
and some external measures may be required. Limited
internal overload protection is used so that noise performance would not be significantly degraded.
-15V
AMP-01 noise level approaches the theoretical noise floor of
the Input stage which would be 4nVlyHZat 1kHz when the
gain is set at 1000. Noise is the result of shot noise in the input
devices and Johnson noise in the resistors. Resistor noise is
calculated from the values of RG (2000 at a gain of 1000) and
the input protection resistors (2500). Active loads for the
input transistors contribute less than 1nVlyHZof noise. The
measured noise level is typically 5nV/yHZ.
Figure 6. Input overvoltage protection for gains 2 to 10,000.
POWER SUPPLY CONSIDERATIONS
Achieving the rated performance of precision amplifiers in a
practical circuit requires careful attention to external influences. Forexample, supply noise and changes in the nominal
voltage directly affectthe input offset voltage. A PSR of 80dB
means that a change of 100mV on the supply, not an
uncommon value, will produce a 10j.LV input offset change.
Consequently, care should be taken in choosing a power unit
that has a low output noise level, good line and load
regulation, and good temperature stability.
Diodes across the input transistor's base-emitter junctions,
combined with 2500 input resistors and RG, protect against
difrerential inputs of up to ±20V for gains of up to 100. The
diodes also prevent avalanche breakdown that would degrade
the 18 and los specifications. Decreasing the value of RG for
gains above 100 limits the maximum input overload protection to ± 10V. External series resistors could be added to
guard against higher voltage levels at the input, but resistors
alone increase the input noise and degrade the signal-tonoise ratio, especially at high gains.
6-20
1/86, Rev. A
-----------l~ AMP-01 LOW-NOISE PRECISION INSTRUMENTATION AMPLIFIER
APPLICATIONS INFORMATION
+1SV
COMPLIANCE, TYPICALLY !10V
LINEARITY - 0 01%
r 0 047 ,1.1F
OUTPUT RESISTANCE AT 20mA - 5Mn
POWER BANDWIDTH {-3d8} - 60kHz
I NTO
LOAD
soon
-IN
(20' RS)
0------''-1
lOUT = VIN AG x A,
A, = loon FDA IOUT=!20mA
V 1N =±100mV FOR ±20mA FULL SCALE
-15V
Figure 7. High-compliance bipolar current source with 13-blt linearity.
r------~------------------~-----o;~~ov
ALL RESISTORS 1% METAL FILM
Rs , 2 Okn
+INo--------"'1
ROUT TRIM
RG
275kn
v-
REF-02
'0
RS ' 221kn
11
-IN
ZERO TRIM
A,
0--------='1
R,
loon
lOon
L---------------4--------~~~120mA
L - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___o-5V
COMPLIANCE OF lOUT, +20V WITH +30V SUPPLY (OUTPUT w r
t
OV}
DIFFERENTIAL INPUT Of 100mV FOR l6mA SPAN
OUTPUT RESISTANCE
~
5MH AT lOUT
20mA
LINEARITY 0 01% OF SPAN
Figure 8. 13-bllllnear 4-20mA transmitter constructed by adding a voltage reference. Thermocouple signals can be accepted
without preampliflcation.
6-21
1/86, Rev. A
_ _ _ _ _ _ _ _-I~AMP-01 LOW-NOISE PRECISION INSTRUMENTATION AMPLIFIER
, - - - - - -.....- - - - - - - - . - - - - - - o + 1 5 V
10kn
+IN
o-----'''"l
SENSE
10051
~...:c.-+-¥.IV-_4--~O---O~~l~~ INTO lOn)
''''
-IN
0-----'-1
VOLTAGE GAIN, G '= 100
POWER BANDWIDTH (-3dB), 60KH2
QUIESCENT CURRENT, 4mA
LINEARITy-a 01%@FULL
l
OUTPUT INTO 10H
L - - - - -.....- - - - - - - - - * - - - - - - o - 1 5 V
Figure 9. Adding two transistors Increases output current to ±1A without affecllng the quiescent current of 4mA. Power bandwidth Is 60kHz.
+15V
Q1, Q2
Q3, Q4, 05.
lel
Jl10
Jl07
AS·l0kn
. CMP-04
~
::~O---------------------------~1:~:G
IC'
0P15GZ
200kn
20kn
2kn
196n
t 0047"F
1'4 ...
-I
~
RS" 2
RG
47kn
'13
~-("'>':"""'t--oOUT
AMP-01
47kn
v~ 10
l
47M2
Voas
f
13
5
H
LlNEARITy ..... a 005%, G'" 10 & 100
....... 002%. G = 1 & 1000
GAIN ACCURACY, UNTRIMMED-05%
SETTLING TIME TO 01%, ALL GAINS,
LESS THAN 75ps
IC1
8'
+15V o_-4~'I2117k1l"~+_--".::.°I_-_I_---I---_+--.J
a
12
GAIN SWITCHING TIME, LESS THAN lOOps
"
27kn
REFERENCE
t-----OGND
~~
/
~
t-_-O.6 1-_+-_---'
~11
7~
:?~4
14
D
V~~S:j
~
47kn
-15V
TTL COMPATIBLE INPUTS
Figure 10. The AMP-01 makes an excellent programmable-gain Instrumentation amplifier. Combined gain-switching and
settling lime to 13-bits falls below 1001'S. Linearity Is beUer than 12-blts over a gain range 1 to 1000.
6·22
1/86, Rev. A
_ _ _ _ _ _ _ _--I!fMDAMP-01 LOW-NOISE PRECISION INSTRUMENTATION AMPLIFIER
r---~~---------------------------------------t--------------------O+'5V
AS_ 10kfl
*MATCHEDTOO.l%
+IN C>--------"'-j
SENSE
15kn
*Skn
REFERENCE
-IN C>---------'-j
T0047MF
~OV
(20 , RS)
-+______
L-____________________
VOLTAGE GAIN, G'" - -
~------+_-------+--------------------O-'5V
RG
MAXIMUM OUTPUT, 20Vp-p INTO 600.11
THO 00l%@1KHz,20Vp-pINT0600n, G=10
DIFFERENTIAL
OUTPUT
OUTPUT
COMMON-MODE
REFERENCE
(±5V MAX)
Figure 11. A differential Input Instrumentation amplifier with differential output replaces a transformer In many applications. The
output will drive a 6000 load at low distortion, (0.01%).
+15V
POWER BANDWIDTH (-3dB)-150KHz
TOTAL HARMONIC DISTORTION-a 006%
@lKHz, 20Vp-p INTO 500.11 111000pF
1
R,
~~----------------+-------~~------~~OVOUT
390n
R,
495kn
NC
NC
CLOSED-LOOP VOL lAGE GAIN MUST BE
GREATER THAN 50 FOR STABLE OPERATION
-15V
VOL TAGE GAIN, G = (1 +
~)
Figure 12. Configuring the AMP-01 as a nonlnvertlng operational amplifier provides exceptional performance. The output
handles low load Impedances at very low distortion, 0.006%.
6-23
1/86, Rev. A
----------l[fMI> AMP·ln LOW·NOISE PRECISION INSTRUMENTATION AMPLIFIER
NC
NC
":>-"--_+---0 Your
47kn
R R2
1 - GAIN (G)
+15V
20V p-p INTO 500fllll000pF.
R3 = Rl II R2
R4
-15V
TOTAL HARMONIC DISTORTION:
= 1.5kfl @ G = 1
1.2kfl @ G = 10
120fl @G = 100 & 1000
<0.005% @ 1kHz, VOUT
20V p.p,
=
G = 1 TO 1000
Figure 13. The Inverting operational amplifier configuration has excellent linearity over the gain range 1 to 1000, typically
0.005%. Offset voltage drift at unity gain Is Improved over the drift in the Instrumentation amplifier configuration.
+15V
I
+
-=
lO F
/./
POWER BANDWIDTH
(-3dB)~60KHz
TOTAL HARMONIC DISTORTION~O.OOl%
@ 1 KHz, 20Vp·p INTO 500flll 1000pF
1
~~-------~----~------~--oVOUT
"2
47k.l1
NC
NC
-15V
Figure 14. Stability with large capacitive loads combined with high output current capability make the AMP-D1 Ideal for line
driving applications. Offset voltage drift approaches the TCVIOS limit, (0.3IlYlo C).
6·24
1/86, Rev. A
_ _ _ _ _ _ _ _--I~AMP-01 LOW-NOISE PRECISION INSTRUMENTATION AMPLIFIER
NOISE TEST CIRCUIT (O.lHz to 10Hz)
162kn
v'
V-
">-~-4---o OUTPUT
11
200kH
20k~1
2kH
1 82kH
200n
162MD.
en (G = 1, 10, 100) =
en (G = 1000)
=
V'
V-
909kH
'O~~~~
1~~~~
loon
lkH
SETTLING-TIME TEST CIRCUIT
200n lOT
V'N
20V p-p
191knOl%
2 x HSCH-l001
10kH
01%
2kH
01%
10kUO 1%
11kD.
01%
102n
01%
lOn
01%
200kn
01%
6-25
1/86, Rev. A
----------l!EMD
AMP-01 LOW-NOISE PRECISION INSTRUMENTATION AMPLIFIER
INSTRUMENTATION AMPLIFIER WITH AUTO-ZERO
r-------------------------~~------------~------------~---------------------------o+15V
RS ' TOkH
VOL TAGE GAIN, G =(20 x RS)
RG
VOUT
75kS1
,.
1SkH
14
13
±lmA
OAe-OB
15
R,
lOOH
7 Skll
001jJF
TTL INPUT
"OFFSET"
°v
TTL INPUT
"ZERO"
-15V
BURN-IN CIRCUIT
+18V
10kn
::::~----+--< VOUT
lOkn
~ 0 047,uF
-lav
6-26
1/86, Rev. A
AMP-OS
FAST-SETTLING JFET
INSTRUMENTATION AMPLIFIER
Precision Monolithics Inc.
PRELIMINARY
FEATURES
PIN CONNECTIONS
Settling-Time to 12-Bit Accuracy, G ~ 1000 .. 12fLS Max
14-Bit Gain Linearity at G ~ 1000
On-Board Dual Guard Drivers
On-Board lOOfLA Precision Current Source
Low Bias Current ....•........... 50pA Max @ 25°C
. • . . . • . . . . . . . .. 20nA Max @ 125°C
• Temperature Stable CMR
• . . . . • • . . • . . . • . .• 105dB Min Over -55°C to + 125°C
• High Slew-Rate with 500pF Load ......••..• 5V1fLS Min
•
•
•
•
•
-GUARD
DRIVE
Voos NULL 4
Voos NULL 5
II
14 VIOS NULL
13 ~g~=~~T
ORDERING INFORMATIONt
CERDIP
l8-PIN
PACKAGE
OPERATING
TEMPERATURE
RANGE
AMP05AX'
AMP05BX'
AMP05EX
AMP05FX
MIL
MIL
IND
IND
REFERENCE 8
SENSE 9
18-PIN HERMETIC DIP
(X-Suffix)
• For devices processed In total compliance to MIL-STD-883, add /883 after part
number. Consult factory for 883 data sheet.
t AU commercial and industnal temperature range parts are available with burn-In
For ordenng information see 1986 Data Book, Section 2
SIMPLIFIED SCHEMATIC
r---------------~----~------~----~----------------------_4r_---Ov+
OUT
-GUARD
DRIVE
REFERENCE
47 SkU
475kn
1---.....---'lNV-----+----oSENSE
25kO
25HZ
1V
L---------------*-----*-------~----~----------------------~~--_Ov-
This preliminary producllnformatlon Is based on lesllng of a IImiled number of devices. Final specifications may vary. Please conlacllocal sales
office or dlslrlbulor for final dala sheet.
6-27
1/86, Rev. A
---------I~ AMP-OS FAST -SETILING JFET INSTRUMENTATION AMPLIFIER -
GENERAL DESCRIPTION
PRELIMINARY
resistance. Internal input protection allows a 30V differential
overload at all gain settings. AMP-05 voltage gain is set by the
ratio of two external resistors over the range 0.1 to 2000 and a low
gain temperature-coefficient of 20ppm/oC is achievable in the
range 1 to 1000.
The AMP-05 is a fast JFET instrumentation amplifier designed
for high-speed analog signal-processing and analog-multiplexed data acquisition systems. Settling-time to 12-bits is 12J-Ls
maximum, with better than 14-bit linearity at all gains up to 1000.
Two functions are added to the instrumentation amplifier that reduce external component count in many applications. On-board
dual guard drivers maintain good settling-time and commonmode rejection performance when shielded cable connects the
input signal to the AMP-05. A precision 100J-LA current source is
also provided for transducer excitation, powering a low-current
voltage reference, and other functions.
The AMP-05's outputs can all drive large capacitive loads without
oscillation. The amplifier output is guaranteed stable with loads
up to 2,000pF and the guard drivers can tolerate up to 10,000pF
without oscillation.
Sense and reference pins complete the output feedback-loop
and provide an output ground reference, respectively. The reference pin may be used for zeroing system offsets, where autozero hardware is employed. ReSistance, in series with the reference terminal, does not degrade common-mode rejection on
PMl's AMP-05, which is a significant problem with instrumentation amplifiers employing the three op-amp configuration.
The AMP-05 employs a current-feedback technique which provides a high and stable common-mode rejection, 105dB minimum over the military temperature range. JFET inputs reduce
bias current to 50pA maximum at 25°C and only 20nA maximum
at 125°C; low bias current reduces errors due to signal-source
6-28
1/86, Rev. A
Table of Contents 1
Ordering Information 2
Product Assurance Program 3
Industry Cross Reference 4
Operational Amplifiers 5
Instrumentation Amplifiers 6
,
Voltage Followers/Buffers 7
Voltage Comparators 8
Matched Transistors 9
Voltage References 10
Digital-to-Analog Converters 11
Analog-to-Digital Converters 12
Analog Switches/Multiplexers 13
Sample-and-Hold Amplifiers 14
Special Functions 15
Communications Products 16
Package Information 17
Sales Offices, Representatives and Distributors 18
VOLTAGE
FOLLOWERS/BUFFERS
Precision Monolithics Inc.
7-3
7-4
Introduction
BUF.03
High-Speed Voltage Follower/Buffer
7-2
VOLTAGE
FOLLOWERS/BUFFERS
Precision M0l101ithics Inc.
INTRODUCTION
feedback can provide better frequency
response. In addition, output current can be
increased substantially beyond that of conventional Ie operational amplifiers.
The BUF-03 is a high-speed, unity-gain Ie that
is optimized for the buffer function. A FET input
provides high input impedance. On-chip zenerzap trimming is used to reduce the offset voltage. The output stage is designed to supply
approximately 70mA of peak current. These features combine to make the BUF-03 an Ie analog
buffer of unique capability.
The function of a unity-gain buffer is to accurately reproduce the input signal under widelyvarying load conditions. To do this, buffers must
have high input impedance, wide bandwidth,
and high output drive. Offsets and gain error
need to be minimized.
The buffer function can be implemented by use
of general-purpose operational amplifiers connected as unity-gain voltage followers, but
higher performance can be obtained by optimizing a circuit specifically for buffering. A design
dedicated to unity-gain buffering and using no
7-3
BUF-03
HIGH-SPEED VOLTAGE
FOLLOWER/BUFFER
Precision Monolithics Inc.
FEATURES
•
•
•
•
•
•
•
•
•
•
in an open-loop circuit employing source followers and
emitter followers, the BUF-03 utilizes a quasi-quad FET input
structure to optimize both speed and D.C. input characteristics. On-chip zener-zap trimming is used to achieve low
offset voltage while careful biasing throughout results in
excellent gain linearity over the full input voltage range,
Very High Slew Rate .................. 220V//Lsec Min
Wide Bandwidth ............................. 63MHz
Load Drive Current .. . . . . . . . . . . . . . . . . . . . .. 70mA Peak
Easily Drives Large Capacitive Loads Without Oscillation
High Input Resistance .................... " 5 x 10"0
Low Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . .. 20
very Low Bias Current (Warmed-Up) ...... 400pA Max
Low Offset Voltage ......................... 6mV Max
Unity Gain ................................. 0.997V/V
Excellent Gain Linearity ....................... 0.015%
Applications for which the BUF-03 is well-suited include
high-speed line drivers, isolation amplifiers for driving
reactive loads, and high-speed sample-hold circuits.
PIN CONNECTIONS
ORDERING INFORMATIONt
TA = 2S"C
VosMAX
(mV)
6
6
'5
15
N.C .
PACKAGE
TO-99
8-PIN
OPERATING
TEMPERATURE
RANGE
BUF03AJ'
BUF03EJ
BUF03BJ'
BUF03FJ
MIL
COM
MIL
COM
•
NUL&,'7V+
N.C.2
6 OUTPUT
INPUT 3
TO-99 (J-Sufflx)
5 NULL
4
v-CeASE)
'For devices processed ,n total compl,ance to MIL·STD·883, add /883 after
part number. Consult factory for 883 data sheet.
t All commercial and Industrial temperature range parts are available with
burn-In. For ordenng information see 1986 Data Book, Section 2.
OPTIONAL OFFSET NULLING CIRCUIT
:>...~~---ov+
GENERAL DESCRIPTION
The BUF-03 is the first very high-speed monolithic voltage
follower. Featuring performance previously unobtainable in a
monolithic unit, it offers a combination of both exceptional
speed and excellent input/output specifications. Implemented
INPUT
0-----',
>-"----0 OUTPUT
SIMPLIFIED SCHEMATIC
,--~--.----~-~--------~r-ov+
OUTPUT
INPUT
L-----~----~--~---~-~~v-
7-4
1/86, Rev, A
-----------l~ BUF-03 HIGH-SPEED VOLTAGE FOLLOWER/BUFFER
ABSOLUTE MAXIMUM RATINGS (Note)
Maximum Junction Temperature (Tj) .............. 175° C
Storage Temperature Range. . .. . . . . . .. -65° C to + 175° C
Operating Temperature Range
BUF-03A, BUF-03B ................. -55°Cto+125°C
BUF-03E, BUF-03F ..................... 0°Cto+70°C
Lead Temperature (Soldering, 60 sec) ............. 300°C
DICE Junction Temperature (Tj) ....... -65°C to +175°C
Supply Voltage (V+ to V-) .......................... 36V
Internal Power Dissipation (P d ) (see curves)
in still air, no heat sink ......................... 1.05W
with heat sink, ()JA = 90° C/W ................... 1.40W
Input Voltage (for Vs < ± 1BV, maximum input
voltage is equal to supply) ...................... ±1BV
Continuous Output Current ....................... 70mA
Peak Output Current ............................. 100mA
Short-Circuit Protection (Maximum Pd or TJ
not to be exceeded) ................ Indefinite at BOmA
NOTE: Absolute ratings apply to both DICE and packaged parts. unless
otherwise noted.
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, TA = 25° C, TCHIP = 75° C, device fully warmed-up, unless
otherwise noted. (Note 1)
8UF-03A/E
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
220
250
8UF-038/F
MAX
MIN
TYP
MAX
UNITS
180
250
VI!'sec
AC SPECIFICATIONS
Slew Rate
SR
RL" 2kO. C L = 50pF
Power Bandwidth
PBW
V ,N = 10Vp_p' R L ,,2kO
BandWidth
BW
aV ,N ='; 2Vp_p
63
50
MHz
90
100
nsec
7
nsec
Settling Time
ts
To 0.1 %. ± 10V step
Capacitive Load Capability
C LOAD
No Oscillations
Propagatton Delay
td
Step Input
Rise Time
t,
av =0.5V
Wide Band Input Noise Voltage
Vn
DC to 50MHz
Input Noise Voltage Density
en
f= 10kHz
Input Offset Voltage
Vos
Rs '; 20kO
Input Bias Current
I.
9
MHz
!'F
7
nsec
350
400
!'VRMS
50
60
nV/y'HZ
DC SPECIFICATIONS
Input Resistance
150
6
4
15
mV
400
180
700
pA
_ 4X10 11
_5X1Q11
R'N
09960
09945
09925
Voltage Gain (V,N = ± 10V)
Avo
R L " 10kO
RL" 2kO
RL" 1kO
Nonlinearity (Note 2)
NL
V,N =±10V. R L ,,2kO
V,N =±7V. RL" 1kO
Maximum Output Error
OUTerror
Y,N = + 10V. OV. -10V
Rs =Ot020kO
R L ;::: 2kO in all combinations
Power Supply Rejection Ratio
PSRR
Vs = ±6V to ±18V
Supply Current
ISY
No Load
Peak Load Current
IL(PKI
Output ResIstance
Ro
Offset Voltage Nulling Range
avos
Input Voltage Range
(Reduced Accuracy)
IVR
09975
0.9960
09945
09940
09930
0.9905
09970
0.9950
09930
0015
0013
0023
0.023
0017
0015
003
0.03
%FS.
40
60
50
85
mV
010
071
0.15
1.42
mV/v
19
25
19
25
mA
70
70
mA
±80
±80
mV
±115
±115
V
2
If no heat Sinking IS used, the chip temperature (m still air) may exceed
1050 C The effect of this elevated temperature Will be to mcrease the Input
bias current by a factor of eight, increase the Vos specification by
TCVos X 30' C, and ,educe device speed by 10%.
Nonlinearity IS computed using linear regression techniques with data
from five POtnts (e g. -10V. -5V. OV. +5V, and +10V for ±10V full-scale
linearity)
1/86, Rev. A
7-5
...- - - - - - -
V/V
0
Rp" 1kO
NOTES:
1. The BUF-03 package thermal resistance. In stili air. IS 145°C/W (45'C/W
Junction-ta-case, 10QoC/W case-te-amblent). The chip temperature of 75° C
IS achieved by redUCing the case-to-amblent thermal resistance to 45° C/W
An Inexpensive heat Sink, such as the Thermalloy 2271 B or 6203, IS
recommended for use In thiS application. In addition, if the deVice IS
operated In a forced-air enVironment, or is attached to a PC board which
has good thermal conductivity, the chip temperature may be further
reduced.
.~-----~-~--
0
-----
..
_-
-------------,-
-----_.
~
~
>l.o
~
~
~
~
....:l
....:l
0>l.o
f.I.l
~
b
~
~
BUF-03 HIGH-SPEED VOLTAGE FOLLOWER/BUFFER
ELECTRICAL CHARACTERISTICS at Vs =
± 15V, -55 0 e:s TA:S + 125 0 e, T CHIP( MAX) = + 165 0 e, device fUlly warmed-up,
unless otherwise noted. (Note 1)
BUF-03A
PARAMETER
SYMBOL
CONDITIONS
Slew Rate
SR
R L ", 2kll, C L = 50pF
Input Offset Voltage
Vos
Rs" 2kll
Average Input Offset
Voltage Dnft
TCVos
Rs" 2kll, (Note 2)
Input Bias Current
18
TA =+125°C
Voltage Gam
Avo
R L ",
Power Supply Relectlon RatiO
PSRR
Vs = ±7V to ±15V
Supply Current
ISY
TA=+125°C
MIN
TYP
BUF-03B
MAX
MIN
220
2kll, Y,N = ± 10V
09920
TYP
MAX
220
UNITS
VllJ.sec
6
20
10
35
mV
50
100
90
170
pVloC
25
75
30
90
0.9955
09902
0.9942
nA
VIV
Gain Drift with Temperature
ppmfOC
0.15
126
020
2.24
mVIV
18
24
18
24
mA
ELECTRICAL CHARACTERISTICS at Vs=±15V, ooe :STA:S+70oe, TCHIP(MAX) =+120 o e, device fully warmed-up, unless
otherwise noted.
BUF-03E
PARAMETER
SYMBOL
CONDITIONS
Slew Rate
SR
R L ",2kll
Input Offset Voltage
Vos
Rs" 2kll, C L = 50pF
Average Input Olfset
Voltage Drift
TCVos
Rs" 2kfl, (Note 2)
Input Bias Current
18
TA =+70°C
Voltage Gain (V ,N = ± 10V)
Avo
R L ", 2kll
Power Supply Reiecllon Ratio
PSRR
Vs= ±7V to ±15V
Supply Current
ISY
TA =+70°C
MIN
TYP
BUF-03F
MAX
MIN
240
TYP
14
40
80
90
15
0.9935
MAX
0.9958
09918
UNITS
Vlpsec
240
28
mV
150
pVloC
1.8
nA
0.9946
VIV
ppm/oC
Gain Drift with Temperature
0.12
19
25
016
178
mVIV
19
25
mA
NOTES:
1. In order to operate the device at an ambient temperature of +125° C, more
extensive heat sinking must be used to ensure that the chip temperature
never exceeds the absolute maximum of +1750 C. Thechip temperature of
+ 1650 C is achieved by reducing the case-te-ambient thermal resistance
to 30° C/W (e g., Thermalloy 2227)
2. Guaranteed by design.
7-6
1/86, Rev. A
-------------1~ BUF-03 HIGH-SPEED VOLTAGE FOLLOWER/BUFFER
DICE CHARACTERISTICS
1.
3.
4.
5.
6.
7.
DIE SIZE 0.070 X 0.048 Inch, 3360 sq. mils
(1.78 X 1.22 mm, 2.17 sq. mm)
NULL
INPUT
NEGATIVE SUPPLY
NULL
OUTPUT
POSITIVE SUPPLY
For additional DICE information refer to
1986 Data Book, Section 2.
WAFER TEST LIMITS at Vs = ± 15V, Tj =25°C, unless otherwise noted.
SYMBOL
CONDITIONS
Inpul Offsel Vollage
Vos
Rs" 20kll
Slew Rale I Nole 1 )
SR
RL ;" 2kll, C L = 50pF
Vollage Gain
Avo
R L ;" 10kll, V,N = ±10V
Power Supply Rejection Ratio
PSRR
Vs =±6Vlo±18V
Supply Currenl
ISY
No Load
PARAMETER
aUF-03N
BUF-03G
LIMIT
LIMIT
UNITS
6
15
mVMAX
VI~sec
220
180
09960
0.9940
VIV MIN
MIN
071
142
mVIV MAX
25
25
rnA MAX
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations In assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualificatIOn through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ± 15V, TJ = 25° C, unless otherwise noted.
aUF-03N
aUF-03G
TYPICAL
TYPICAL
UNITS
ILIPK)
70
70
rnA
I npul Bias Currenl
18
40
60
pA
Input Resistance
R'N
5 X 10"
5 X 10"
Il
Oulpul Reslslance
Ro
Offsel Vollage Nulling Range
avos
±80
±80
mV
Inpul Vollage Range
I Reduced Accuracy)
IVR
±115
±115
V
MHz
PARAMETER
SYMBOL
Peak Load Current
CONDITIONS
Il
Rp;" 1kll
Power Bandwidth
PBW
V,N = 10Vp_p, RL ;" 2kll
Bandwidlh
BW
av,N " 2Vp_p
63
55
Seltling Time
Is
To 01%, ±10V slep
90
100
Capacitive Load Capacily
C LOAD
No Oscilialions
9
MHz
ns
~F
Propagalion Delay
Id
Slep Inpul
ns
Rise Time
I,
av ,N = 0.5V
ns
Wide Band Inpul Noise Vollage
Vn
DC 10 50MHz
en
f = 10kHz
Inpul Noise Vollage Densily
350
400
#lVRMS
50
60
nV/VHZ
NOTE:
1. Sample lesled.
7-7
1/86, Rev. A
-----------l1fHD
BUF-03 HIGH-SPEED VOLTAGE FOLLOWER/BUFFER
TYPICAL PERFORMANCE CHARACTERISTICS
GAIN AND PHASE RESPONSE
vs FREQUENCY
SLEW RATEvs
CAPACITIVE LOAD
500
300
250
~
~
~
W
I-
;i
1il
til
IIII
TA '" 2sOe
Vs '" ±15V
400
-
TA'25°C
LARGE-SIGNAL
FREQUENCY RESPONSE
240
GAIN
Cl = 50pF
28
~0
Ii
I I I:
200
GAIN
CL'" 10pF
/
IlJ.I.
~
---
-2
II
IIII
lOD
-4
PHASE
CL'" 10pF
70
-6
50
100
-8
150
:--
"z
~
":=""
"0
~
l'lj
V
~
120 [:B
~
ew
~
60
1/
~
5:
200
300 400 500
700
CAPACITIVE LOAD (pF)
14
\.
12
. IIII
~
1.0
~
08
z
o
\
-
006
~
\ 1\
2
04
·1
02
30°C!W CASE TO
AMBIENT HEAT
SINK
8JA '" 7SoC/W
1
1
1
40
~
20
f5
~
gj 140
- r--
~;~I~~:~?w
I
I
"~
~
120
i<
~
(Dr
Vs '" ±15V
TA=25"C
ElJA = 90°clW
r-- V
-10
-15
5
10
15
:,....-
GAIN ERROR
vs TEMPERATURE
310
V i--"""
-0.70
Vs = ±15V
ElJA = 900 C!W
~
'"
~
w
!;t
-0.50
-
i'- ~
NEGATIVE
250
...........
~
~
cil
-0.60
r-- ...........
270
230
~
210
,
-2
0
INPUT VOLTAGE (VOL IS)
10
190
-50
-25
0
RL = 1kfl
"""
1-1-"""
RL
'ii
;
"" '"
'-..,
100
-0.40
iii
POSITIVE
25
50
75
TEMPERATURE (OC)
7-8
45
AMBIENT TEMPERATURE (OC)
..........
-6
25
SLEW RATE
vs TEMPERATURE
290
_ _L__~_~
125
65
85
001L-_~_~_~
-5
OUTPUT VOLTAGE {VOLTS)
WARMED UP
TA '" 25°C
Vs '" ±15V
,....
.........-
y
-80
100
80
-10
'--'T""--r---r--.-~T""-"
SAFE OPERATING
AREA
-60
50
75
100 125 150 175 200
AMBIENT TEMPERATURE (OC)
,....
100
V
~
8JA'" 90°C/W
!160
60
INPUT BIAS CURRENT vs
TEMPERATURE (WARMED-UP)
100
""
"":= -20
"0_40
-
180 -
40
/
INPUT BIAS CURRENT
VB INPUT VOLTAGE
200
4
6
10
20
FREQUENCY (MHz)
100
~
NO HEAT SINK
I
25
-
~
45°C!W CASE TO
AMBIENT HEAT SINK
8JA '" 90"C/W
w
60
80
'" '"X I\'
ili
40
OUTPUT CURRENT
vs OUTPUT VOLTAGE
60
\
"
~
-40
4
6 8 10
20
FREQUENCY (MH.:1
\
12
~
0
MAXIMUM POWER
DISSIPATION vs
AMBIENT TEMPERATURE
"
16
6
I
1000
20
~
I I ILl.....•........
150
TA '" 2sOe
SR = 250V / tlseC
~
180
-_
-
vsl •• !svl I I
24
125
ffi2
2'"
I
1-"""
RIL .110:"
-0.30
<1
" -0.20
Vs - ±15V
VIN= ±10V
-0.1 0
ElJA= 90 0 C/W
I
o
-50
-25
25
50
75
I
100
125
TEMPERATURE (Oc)
1/86, Rev. A
-------------t~ BUF-03 HIGH-SPEED VOLTAGE FOLLOWER/BUFFER
TYPICAL PERFORMANCE CHARACTERISTICS
GAIN ERROR VI
INPUT VOLTAGE
NONLINEARITY VI
FULL-SCALE VOLTAGE
50
0.05
TA '" 25°C
Vs = ±15V
_
-
0.03
./
1/
V
/
...........
000
±5
£,
~
RLi?
10
i
>-- I- ,..... ---+-1'::
RL"""a·-
001
z
19
./
-2026
I
10
""- ~
18
15
i2l
15
-50
±24
I
-25
I
I
I
I
-6
-10
Vs
TA=25"C _
I
I I
-2
0
2
10
INPUT VOLTAGE (VOLTS)
OUTPUT SHORT-CIRCUIT
CURRENT VI TIME
-
~
TA = 25"C
:VS=±15V
eJA" g(f'c/W
;: 80
1£
r---....
...........
""::> \'r-...
~
" 70 -r-VIN
Ii
"
<3
"~60
I-
...........
---
0
25
50
75
100
125
TEMPERATURE (OC)
SLEW RATEvs
SUPPLY VOLTAGE
VIN"' -tOV ~
r--_
+10V
-
I-
r-
(SHORT CIRCUIT TO GROUND)-
o
20
50
SUPPLY VOLTAGE (±VOLTSJ
I
,I ±15~-
/
RL = 2000
l
Ri' 5 0a
/'
-100
'"
~
/
90
16
±18
r---
I-"
I
17
±15
/
o
Vs = ±15V
eJA = 90°C/W
iO -
t12
~
i<
~
/
SUPPLY CURRENT
VI TEMPERATURE
I- TA 125.c
:1;9
"V
~ ~RL~ 10kn,_
I-
RL '" 50n
100
-300
21
••
~
/
INPUT VOLTAGE (VOLTS)
21
./'
)'( V
, RL' 200a
,I
200
V
6
SUPPLY CURRENT
,. / '
V V"
/
VI SUPPLY VOLTAGE
./"
300
-200
-10
±10
,;
/
FULL-SCALE (VOLTS)
20
RL = lkn
TA" :ZS-c
V
0.02
~S' ~'5VI
_
RL"'6000 /
GAIN ERROR VI
INPUT VOLTAGE
I I I I I I I I
40
60
80
--
100
120
TIME FROM SHORT (SEC)
SLEW RATE
300
---
TA=25"C
250
I-"'"
¥
~
C
200
RISE
w
~
"
~ 150
oj
100
50
±5
/
FALL
/
V
/
...........
/V /
V
V
±7
±9
.t11
±13
±15
SUPPLY VOLTAGE (VOL T8)
7-9
1/86, Rev. A
-----------I~ BUF-03 HIGH-SPEED VOLTAGE FOLLOWER/BUFFER
HIGH-SPEED 6-BIT AID BUFFER
APPLICATIONS INFORMATION
+15V
OPERATING THE BUF-03 AT REDUCED
POWER SUPPLIES
24~;:------'.!..._--------'''l
OUTPUT
0-----..------..,--_.-----,
Rl
2kn
12k,Q
SAMPLE +15V
LOGIC
r~--~+136V
IN
R2
12k!2
SAMPLE,;;; 0
av
Vl
HOLD -7V
DIGITAL _
GROUND -
R4
{
150n
~
soon TO 6V
TTL GATE LOAD
fAN OUT = 4
NO LOAD
-0.10
0.06
60
-60
120
90
TTL GATE LOAD
FANOUT=4
NO LOAD
60
90
120
RESPONSE TIME (nsec)
OFFSET VOLTAGE
TEMPERATURE
==
=TA=25"C
Vs
10
j°"fN
>
iu
~
o
r--
TYPICAL
""'\!)I I II
010
10
100
':;UI~V
YI
25
50
" ~;"'('
1
Vs = ±15V
,RS = 50n
75
750
~s- ~ 0 -
100
2
"- ~ \.!.l."
""
r---:.
a:
a:
[j300
tfu tx.:
:l
1O
"- t-.
"- t--
~ 200
INPUT BIAS CURRENT
V8 DIFFERENTIAL
INPUT VOLTAGE
r-,-,---r-...,......,-,r-T""'"'-""''''''''''''''''''
-
~
~ ~o 1-+-++--+-l~-l-+-~+~__l100 ffi
a:
a:
a~
Vs+ = 15V
500
7nA CHANGE
200
a
300
:l
1O 400
~
m
~ 300
Vs+= 5V
400
~
t--
~
eMP·01
eMP·01E
~
Z
fooC TO 7cf'C)
2
CMP.Q1C
-25
25
75
TEMPERATURE (OC)
125
Vs = ±lSV
100
---------~~~~~-
f-
o
500
~
~
700
-5~,L2~-_~8~L-_~4~--~L-~4~--~l-J,2
DIFFERENTIAL INPUT VOLTAGE (VOLTS)
5
~
600
TA = 25"C
8-11
-
'----
I
(O"C TO 70"C)
CMP Ole
-25
5V _
_VS+=5V_
25
I
75
125
INPUT VOLTAGE RANGE
VB TEMPERATURE
~ 200
1
CMP-Ol
CMP·01E
Vs+ '" 15V
--vs+
TEMPERATURE (OC)
1 700 I-+-++--+-l~-l-+-..J.-..-+--I--I
I
L
~...........
-75
125
I-
~ 400
Vs+ '" 15V
~
I
~
-25
"" ~ 'lzl
eMP·01
eMp,01E
(O"C TO 70"C)
eMP·Ole
TEMPERATURE (OC)
INPUT BIAS CURRENT
V8 TEMPERATURE
,I5V "
I
001
-50
MATCHED SOURCE RESISTANCE (k,n)
BOO
=2
!!
eMP·01
eMp·01E
eMP·Ole
2
I
1
~=
~
1
I III
!
II
I
I
~
UNNULLED
W
~o
-tl
600
I
,>-
-
1
V:..-
SE
01
10
INPUT OFFSET CURRENT
V8 TEMPERATURE
VB
-15V" Vs-" 0
-W
-g:{
(Vos+ OVERDRIVE)
(Vos- OVERDRIVE)
\,. RISE
150
'0
+15V
,........
-75
2
3.
VIN~FALL
-60
INPUT OFFSET ERROR V8
SOURCE RESISTANCE
100
soon TO SV
~
160
RESPONSE TIME (nsec)
!!
1
! -005
-015
10
CL '" 12pF INCLUDING PROBE
AND JIG CAPACITANCE
~ ~\ CD
>
W
-005
RESPONSE TIME TEST CIRCUIT
~
V+
V+ -05
CC'CI=E::E±:J
--r--
1: : : ]
~V+-l01-__+-+-+_~~~~±-~r-__l
~ V+ -1 5 I-~-+--I-__+-+-;W
~ V+ -2 0 I---+-+-l--l-+----'-l-~f___l
~
W
~V-+201---+-+-+--4-~----'+-~I---l
~V-+15~~:::F~~~--~~~~~__j
.
~ v- +1
0
I---l.-+--I-~-
V-+05~-T-~f-+-_l-+-+__lI___l
-25
75
25
TEMPERATURE I"CI
125
1/86, Rev. A
--------------i~ CMP-01 FAST PRECISION COMPARATOR
TYPICAL PERFORMANCE CHARACTERISTICS
RESPONSE TIME
FOR 100mV STEP AND VARIOUS INPUT OVERDRIVES
~
f-
NJ LOA~
VS=±15V
TA=25°C
RS=50n
/
....- -;::? :::.V
/:: / ' /
!/ V /
JV
~
I
?
w
w
.,
§:
"~ -005 r--- r- ,' lmV
'mV
5mV
3
~
20mV
I-
-010
~
1
2
3
4
005
.,
f----' - 4
240
360
10
1125'~
V
~
V
V
V
lmV
120
~~~~ r---
~
L
I-::
2
3
VS= +15V
TA = 25°C
20mV
V
V
llill
01
'0
r---
I
120 , - ; - , - , - , , - - , - - , - ,
f---+-+---j-Vs '" ±15V. Vo
I
f""""
TA=2SoC
V
OUTlpUT LOW
/
v-::
t-- t--
10
20
30
40
OUTPUT SINK CURRENT (rnA)
I
o
50
o
~
8
~~
5V, Vi = ov, Vo = LOW
TEMPERATURE (ee)
RESPONSE TIME
FOR SV STEP AND SmV OVERDRIVE
V
/
~
5
-1
~
-2
~
STROBE
=
~7~5r_~5~0-_~~=--~~0-~2~5r60=--=75r~100~~125
±20
±5
±10
±15
±SUPPLY VOLTAGE (VOLTS)
/
33kn
t---j----j---i---r--t---t---r---j
~ 20 t---j--t-- Vs
NEGATIVE SUPPLY
2kf!
~_---oV+
>:-'~--O OUTPUT
LOW_
~60t---j---j--i--r--t--t--r---j
X
OFFSET TRIMMING AND
STROBE CIRCUIT
=
I--+=I--+=I==t==t=j=:::j
E
V
OUTPUT H , / '
100
+_1
Z80t==J:::~~~;vS~O='~'i5V~'~V~O=O=H~IG~H==l
'"
'xJOSITIVE SUPPLY
-5SoC
100
POWER CONSUMPTION
VI TEMPERATURE
SUPPLY IS +45V
V
10
SOURCE RESISTANCE (k.l1)
r- MIINIMU~ posiTivE
I--- I--
~
360
240
SUPPLY CURRENT VB
SUPPLY VOLTAGE
25'~
+sv,;;; Vs+,,;;; +15V
-15V";; Vs- -;;;; ov
L
25
,.,
>
OUTPUT
V
~
~
~~=L~~5~-
~ -4
TA = 25°C
RS =50.11-
~
'I
-5
100
200
RESPONSE TIME (nsec)
8·12
4"'
0
~
;;
/
INPUT
~
3l'J
-3
o
>
v-
~.
=>
0
RESPONSE TIME (nsec)
SATURATION VOLTAGE
VI SINK CURRENT
~
RS MATCHED TO 1 0%
1200
12
120
420
RESPONSE TIME (nsec)
A
"~
~ -0 05
1
120
V
V V
......
~~
5mV OVERDRIVE
20mV OVERDRIVE
3
lOamV STEP
NO LOAD
3 "
2 0
>
>1
2mV OVERDRIVE
1
w
>-
1
~ -015
0 10
,
5
Vs = t15V_ 4
T A =25°C
~
\ 1\
1 \
b('> cD 18
l 1 _\
~o
J
12k
~
NO LOAD
RS=50.11_
}~
r;5¢ I¢
B
.......
RESPONSE TIME VI
SOURCE RESISTANCE
1
300
=>
0 0
~5
NJ LOAi -
0
\
~4
"" 3
~
~
INPUT
\
OUTPUT
>-2
=>
~
is
Vs = ±15V
TA =2SoCAS = 50.11
II
1
\
0
:10
~
~
-'.
100
200
300
RESPONSE TIME (nsec)
1/86, Rev. A
--------------1~ CMP-01 FAST PRECISION COMPARATOR
wideband circuits, it is recommended that the supplies be
bypassed near the socket of the device.
APPLICATIONS INFORMATION
The CMP-01 provides fast response times even with small
overdrives; to achieve this performance requires very high
gain at high frequencies. The CMP-01 is completely free of
oscillations; however, small values of stray capacitance from
output to input when combined with high-source resistances
can cause an unstable condition. DC characteristics are not
affected, but when the input is within a few microvolts of the
transition level, certain conditions can create an oscillation
region. The width of this oscillatory region and the size of
source resistance where oscillations begin is a strong function of the stray coupling present. The following suggestions
are offered as a guide towards minimizing the conditions for
oscillation: matched source resistors, minimized stray capacitances (e.g., a ground plane between output and input), or
capacitive output loading (CLl. The capacitive loading techniques will eliminate the oscillations, but result in slower
response time. Matched bypass capacitors across the input
resistors also can eliminate the instability,
MINIMIZING OSCILLATION
BURN-IN CIRCUIT
V+
and if C 2: 20 F (m~~imUm step s~ze)
s
P minimum overdrive
the response time will approximate the response time for low
values of Rs. It should be noted that the offset nulling
terminals do not require bypassing for stability. As with all
-=
V-leASE)
MIL-STD·883. METHOD 1015, CONDITION B
a-BIT TRACKING AID CONVERTER
r - - - - - - - - - - + - - - - - - - - - - - < P - - - - - - - - - - < > CLOCK
IN
MAXIMUM CLOCK RATE'" 3 OMHz
~r~
£\~
1'
_
_
-
--15V
• c
•
,
C
UfO
Ufo
Q
8284
UP/DOWN
COUNTER
,.
9
'3
12 11
6
6
~
•
UP/DOWN
COUNTER
OUT
2 CARRY
,.
3
+5V TRACK
W
.284
9
••
•
7
if
'1/4740.
24.n
~
CLOCK
OUT
C
FOR CLOCK RATE'" 30MHz
C = 470pf
~
,.
""'l~ ,N9'4 ~
.2;:..
'7
......
+15V
::st
DAC-l00cCQ3
\'----+.-::-----r.:-----r:,...-----I,.
R1N!i!!E 4.8kn
~Np~~OG
r-......---.---o+5V
• I. T•
LSB
lN914
'--_____...-_--+__~3r - -.......VIN - 0 TO +10V
9
MSB
10-BIT D/A CONVERTER
::s~
••an
'6
I"
o------,r----t--------'
MAXIMUM FULL SCALE
SINE WAVE INPUT
IS 4000Hz
2
2000
FULL SCALE
ADJUST L - -.....------~-,.V
8·13
1/86, Rev. A
CMP-02
LOW-INPUT- CURRENT
PRECISION COMPARATOR
Precision MOTlohthics Inc
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The CMP-02 is a monolithic low input current comparator
using an advanced NPN-Schottky Barrier Diode process. It
features superior input characteristics with extremely low
offset voltage, offset current, bias current and temperature
drift. High common-mode and power supply rejection plus
good response time contribute to excellent performance in
the most demanding applications. The balanced offset
nulling, large output drive, and wired-OR capability combined with internal pull-up maximize application convenience. The CMP-02 is capable of operating over a wide range
of supply voltages, including Single plus 5 volt supply
operation, and is pin-compatible to earlier 111,106, and 710
types. For applications requiring faster response time, please
refer to the CMP-01 fast preCision comparator data sheef.
Low Offset Voltage .....•..•... 0.3mV Typ, 0.8mV Max
Low Offset Current ....•......... 0.3nA Typ, 3nA Max
Low Bias Current .......•.••••.. 28nA Typ, SOnA Max
Low Offset Drift .•.•...............••• 1I'VloC,4pA/oC
High Gain ..........•..•...•............. 200,000 Min
High CMRR .....•...........••. 110dB Typ, 94dB Min
High Input Impedance .•..•.••.............•.. _18MO
Fast Response Time •....••.... 190ns Typ, 270ns Max
Standard Power Supplies ..•...... +SVor ±SV to ±18V
Guaranteed Operation from Single +SV
No Pull-Up Resistor Required for TTL Drive
Wired OR Capability
Fits 111, 106, 710 Sockets
Easy Offset Nulling .....•..• Single 2kO Potentiometer
Easy to Use ................... Free from Oscillations
PIN CONNECTIONS
ORDERING INFORMATIONt
v+
PACKAGE
HERMETIC
+25·C
Vos
(mV)
0.8
2.8
B
TO-.
a·PIN
DIP
a·PIN
PLASTIC
DIP
a·PIN
CMP02J'
CMP02EJ
CMP02CJ
CMP02Z'
CMP02EZ
CMP02CZ
CMP02EP
CMP02CP
OPERATING
TEMPERATURE
RANGE
MIL
COM
COM
GNBo
70UT
+IN 2 :
6 BALANCE
-IN 3
5 BALANCE
4
v-teASE)
'For devices processed In total compliance to MIL-STD-883, add /883 after
part number. Consult factory for 883 data sheet.
tAli commercial and industrial temperature range parts are available With
burn-In. For ordering Information see 1986 Data Book, Section 2
8-PIN HERMETIC MINI-DIP
(Z-Sufflx)
TO-99
(J-Sufflx)
EPOXY MINI-DIP
(P-Sufflx)
SIMPLIFIED SCHEMATIC
w~
____
~
____
~
__
~~
____
~
____
~
____
~
____
~
____
~
____
~
____
~
INPUT
INVERTING
v-~----*-----*---~
8-14
1/86, Rev, A
----------I1fMD
CMP-02 LOW-INPUT-CURRENT PRECISION COMPARATOR
ABSOLUTE MAXIMUM RATINGS (Note 2)
Storage Temperature Range ••••••••••••• -65·C to +150·C
P-Suffix ............................. -65·C to +125·C
Lead Temperature (Soldering, 60 sec) •••••••••••••• 300·C
Output Short-Circuit Duration - to ground ••••••• Indefinite
to V+ ........... 1 Minute
NOTES:
1. Maximum package power dissipation va. ambient temperature.
Total Supply Voltage, V+ to V- ..................... 36V
Output to Ground ••••••••••••••••••••••••• -5V to +32V
Output to Negative Supply Voltage. • • • • • • • • • • • • • • • •• 50V
Ground to Negative Supply Voltage •••••••••••.•.••• 30V
Positive Supply Voltage to Ground .••••••••••••••••• 30V
Positive Supply Voltage to Offset Null ••••••••••.• 0 to 2V
Power Dissipation (See Note 1) ••••••••••••••.••• 500mW
Differential Input Voltage .......................... ±llV
Input Voltage (Vs = ± 15V) ••••••••••••••••••••••••• ± 15V
Output Sink Current (Continuous Operation) ••••••• 75mA
Operating Temperature Range
CMP-02 ............................ -55· C to + 125· C
CMP-02E, CMP-02C .................... 0·Cto+70·C
DICE Junction Temperature (Tj) ••••••• -65· C to + 150· C
ELECTRICAL CHARACTERISTICS at Vs
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
PACKAGE TYPE
TO-99 (J)
SO"C
7.1mW'"C
Mini-DIP (P)
36"C
5.6mW'"C
Hermetic Mini-DIP (Z)
75"C
6.7mW'"C
2. Absolute ratings apply to both DICE and packaged parts, unless otherwise
noted
= ± 15V, TA = 25· C, unless otherwise noted.
CMP-02
CMP-02E
PARAMETER
SYMBOL CONDITIONS
Input Ollset Voltage
Vos
Input OIIoet Voltage
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
CMp·02C
TYP
MAX
TYP
MAX
UNITS
RsSSkO. (Note 1)
0.3
08
04
28
mV
Vos
Rs S 50kO. (Note 1)
0.3
0.9
0.4
3
mV
Input OIIset Current
los
(Note 1)
03
30
0.4
15
nA
Input Bias Current
18
28
50
35
100
nA
Vl
MO
0
Differential Input
MIN
Resistance
R'N
(Note 2)
17
Voltage Gain
Av
Vo=0.4Vto 2.4V, (Notes 1. 2)
200
tr
100mV step, 5mV Overdrive
No Load (No Pull-Up)
5kO to 5V (Pull-Up)
TTL Fan-Out = 4. No Pull-Up
Response Time
(Note 3)
MIN
09
500
190
190
190
100
270
500
190
190
190
VlmV
~
~
I=l-<
270
ns
~
U
15
Input Slew Rete
15
VI".s
Input Voltage Range
CMVR
±12.5
±13.0
±125
±13.0
V
Common-Mode
Rejection Ratio
CMRR
94
110
90
110
dB
Power Supply
Rejection Ratio
PSRR
5V S Vs+ S 18V,
-18VSVs_SOV
SO
100
74
98
dB
Positive Output
Voltage
Y,N '" 3mV, 10 = 320".A
V,N ",3mV, 10= 24O".A
V,N ",3mV,1 0 =OmA
24
3.2
VOH
4.8
2.4
24
34
48
V
24
Saturation Voltage
VOL
Y,N S -10mV. ISink = OmA
Y,N S -10mV, ISink S 6.4mA
Y,N S -10mV. Isink S 12mA (CMP-{)2 only)
016
03
038
040
0.45
05
016
031
0.40
0.45
V
Output Leakage Current
ILEAK
V,N'" 10mV. Vo =+30V
003
2.0
0.05
8.0
".A
Positive Supply Current
1+
V,N S-l0mV
5.5
80
5.6
8.5
mA
Negative Supply Current
1-
V,N S-l0mV
1.1
2.2
1.2
2.2
mA
Pd
V,N S-l0mV
99
153
102
161
mW
Nulling Pot'" 2kO
±5
Power Dissipation
Offset Voltage
Adjustment Range
NOTES:
1. These Parameters are specified as the maximum values required to drive
the output between the logiC levels ofO.4Vand 2.4V With a 1kO load tied to
+5V; thus, these paremeters define an error band which takes Into
±5
mV
account the worst case effects of voltage gain and Input impedance.
2. Guaranteed by deSign.
3 Sample tested
8-15
1/86, Rev. A
Pol
~
tj
~
IfMD
CMP-G2 LOW-INPUT-CURRENT PRECISION COMPARATOR
ELECTRICAL CHARACTERISTICS at Vs = 5V,
VS-
= OV, TA = 25
0
C, unless otherwise noted.
CMP-G2
CMP-02E
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vas
Rs S5kO. (Note 1)
Input Ollset Current
los
(Note 1)
Input Bias Currenl
Is
Voltage Gain
Av
Vo=0.4V to 2.4V, (Notes 1. 2)
Response Time
tr
l00mV Step, 5mV Overdrive
5kO to 5V (Pull-Up)
TTL Fan-out = 4, 5kO to 5V
Input Voltage Range
MIN
MAX
TVP
MAX
UNITS
0.4
1.5
0.5
3.5
mV
0.25
3
0.35
14
nA
24
45
30
90
50
250
250
250
250
1.8-3.5 1.7-3.8
CMVR
VOL
0.3
Positive Supply Current
1+
VIN S-l0mV
2.2
Power Dissipation
Pd
VIN S-l0mV
11
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, -55 0 C ::; TA::;
1250
MIN
50
VIN S -3.5mV, I oink S 6.4mA
Saturation Voltage
CMP-G2C
TYP
na
1.8-3.5 1.7-3.8
0.45
nA
VlmV
V
0.3
0.45
3
2.3
3.6
mA
15
11.5
18
mW
V
C, unless otherwise noted.
CMP-G2
PARAMETER
SYMBOL CONDITIONS
MIN
TVP
MAX
UNITS
0.4
1.6
2.8
mV
Input Offset Voltage
Vas
RsS 5kO, (Note 1)
Vs+=5V, Vs-=OV, (Note 1)
Average Input Offset
Voltage Drift
Without External Trim
With External Trim
TCVos
TCVoSn
Rs=500
Rs=500
1.5
1.0
Input Offset Current
los
TA= +125'C, (Note 1)
TA =-55'C, (Note 1)
0.3
0.4
Average Input Offset
Current Drift
TClos
+25'Cs TAS +125'C
-55'CSTA S+25'C
2
4
Input Bias Current
Is
TA=+125'C
TA =-55'C
Voltage Gam
Av
Vo= O.4V to 2.4V, (Notes I, 2)
tr
l00mV Step, 5mV Overdrive
TA = +125'C, No Load
TA = -55' C, No Load
Response Time
0.5
25
45
100
pvrc
4
12
nA
pArC
50
120
500
nA
VlmV
310
ns
155
Input Voltage Range
CMVR
±12
±13
V
Common-Mode
Rejection Ratio
CMRR
88
106
dB
Power Supply
Relection Ratio
PSRR
5VS Vs+S 15V, -15V S Vs_S OV
75
96
dB
Positive Output Voltage
VOH
VIN~4mV,lo=200pA
VOL
VINS-l0mV,lsonk=OmA
VIN S-l0mV, Isonk = 6.4mA
Saturation Voltage
2.4
3
0.20
0.32
V
0.4
0.5
V
NOTES:
1. These Parameters are specified as the maximum values required to drive
the output between the logic levels of 0.4 V and 2.4V with a 1kO load tied to
+5V; thus, these parameters define an error band which takes Into
account the worst case effects of voltage gain and Input Impedance.
2. Guaranteed by design.
3. Sample tested.
8-16
1/86, Rev. A
----------I~ CMP-GZ LOW-INPUT-CURRENT PRECISION COMPARATOR
ELECTRICAL CHARACTERISTICS at Vs = ±15V, O·C S
TAS
70·C, unless otherwise noted.
CMP-02E
PARAMETER
MIN
SYMBOL CONDITIONS
MAX
0.4
0.5
1.4
2.4
Input Offset Voltage
Vos
Rs S 5kO. (Note 1)
Vs+=5V. Vs-=OV, (Note 1)
Average Input Offset
Voltage Drill
Without External Trim
With External Trim
TCVos
TCVoSn
Rs= SOO
Rs= SOO
1.5
Input Offset Current
los
TA = +70·C, (Note 1)
TA=O·C, (Note 1)
0.3
0.4
Average Input Offset
Current Drill
TClos
+25·CSTA S+70·C
0·CSTA S+2S·C
2
4
I nput Bias Current
Ie
TA =+70·C
TA=O·C
Voltage Gain
Av
Vo = 0.4V to 2.4V, (Notes I, 2)
Response Time
t,
l00mV Step, 5mV Overdrive
TA = +70·C, No Load
TA = O·C, No Load
26
34
100
CMP-02C
TVP
MIN
TVP
MAX
UNITS
0.5
0.6
3.5
4.3
mV
1.8
1.2
0.4
0.5
3
6
I'VI·C
15
25
3
5
SO
60
33
42
70
500
225
160
nA
pAl·C
100
160
nA
500
VlmV
225
160
ns
Input Voltage Range
CMVR
±12.0
±13
±12
±13
V
Common-Mode
Rejection Ratio
CMRR
90
loe
66
loe
dB
Power Supply
Rejection Ratio
PSRR
5V S Vs+ S 1SV, -15V S Vs-S OV
77
98
70
88
dB
Positive Output Voltage
VOH
Y,N 2: 4mV, 10 = 200l'A
2.4
3.2
2.4
32
VOL
Y,N S -10mV, Is,nk = 0
V'N S -10mV, Is,nk = 6.4mA
Saturation Voltage
0.17
0.30
0.17
0.31
0.4
05
V
0.4
0.5
V
~
0
~
NOTES:
1. These Parameters are specified as the maximum values ,equired to drive
the output between the logic levels of O.4V and 2.4V with a 1kO load tied to
+5V; thus, these parameters define an error band which takes into
account the worst case effects of voltage gain and input impedance.
2. Guaranteed by design.
3. Sample tested.
1=1-<
~
U
~
~
tj
~
1/86, Rev. A
S-17
~~~---.--.-.
'-"'--.-.-.
-. .
-'~'-'---'-'---'
-.-
----------I~ CMPo02 LOW-INPUT-CURRENT PRECISION COMPARATOR
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
8.
7.
8.
DIE SIZE 0.085 X 0.042 Inch, 2730 sq. mill
(1.851 X 1.089 mm, 1.781 Iq. mm)
WAFER TEST LIMITS at
Vs= ±1SV, TA=2S"C.
PARAMETER
SYMBOL
CONDITIONS
Vos
Rs :55kO
Rs:5SOkO
Input Offset Voltage
Input Offset Current
los
Input Bias Current
Ie
Differential Input Resistance
RIN
Input Voltage Range
CMVR
Common-Mode Rejection Ratio
CMRR
Power Supply Rejection RatiO
GROUND
NONINVERTING INPUT
INVERTING INPUT
NEGATIVE SUPPLY (SUBSTRATE)
BALANCE
BALANCE
OUTPUT
POSITIVE SUPPLY
For additional DICE inlormallon refer to
1986 Data Book, Section 2.
CMP-02N
CMP-02GR
LIMIT
LIMIT
UNITS
0.8
0.9
2.8
3
mVMAX
3
15
nAMAX
50
100
nAMAX
MOMIN
1.7
0.9
±12.5
±12.5
VMIN
VCM=±CMVR
94
90
dBMIN
PSRR
5V:5 Vs+:5 18V
-18V:5 Vs -:5 OV
80
74
dBMIN
Positive Output Voltage
VOH
VIN ",3mV, 10= 320l'A
V,N ", 3mV, 10 = 240I'A
Saturation Voltage
VOL
I.,nk = S.4mA
Output Leakage Current
I LEAK
VIN'" 10mV, Vo = 30V
2.4
2.4
VMIN
0.45
0.45
V MAX
2
8
I'AMAX
mAMAX
Positive Supply Current
1+
V1N :5-10mV
8
8.5
Negative Supply Current
1-
V1N :5-10mV
2.2
2.2
mAMAX
Power Consumption
Pd
VIN:5-10mV
153
161
mWMAX
WAFER TEST LIMITS at
Vs + = SV
CMP-G2N
CMP-G2GR
PARAMETER
SYMBOL
CONDITIONS
LIMIT
LIMIT
UNITS
Input Offset Voltage
Vos
Rs :55kO
1.5
3.5
mVMAX
Input Offset Current
los
3
14
nAMAX
and Vs -
=
av, TA = 2S"C.
NOTE:
Electrtcal tests are performed at wafer probe to the limits shown. Due to variations In assembly methods and normal yield loss, yield after packaging Is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs =
PARAMETER
SYMBOL
Average Input Offset
Voltage Drtft
TCVos
Average Input Offset
Current Drill
TClos
Response Time
tr
±15V.
CONDITIONS
Rs=SOO
l00mV Step, 5mV Overdrtve
No Load (No Pull-Up), TA = 25°C
8-18
CMP-02N
CMP-02GR
TYPICAL
TYPICAL
UNITS
1.5
1.8
I'VI"C
4
5
pArC
190
190
ns
1/86, Rev. A
-------------I~ CMP-02 LOW-INPUT-CURRENT PRECISION COMPARATOR
TYPICAL PERFORMANCE CHARACTERISTICS
RESPONSE TIME,
100mV STEP, 5mV OVERDRIVE, VARIOUS LOADS
RESPONSE TIME TEST CIRCUIT
5~
CL = 1ZpF INCLUDING PROBE
~",,":-+---l----+---4 4 0
AND JIG CAPACITANCE
~
w
3
~
+-t------+-----l'~_l'<_A~---12 ~
t;
~o
~
~
~
~ -005
~ -010
~
::>
o
010
w
w
it
, :=
+-+---+--j Vs
TA
+_+---+_-j RS
~
= i15V
= 2SOC
=
0.05
~
son
>-
it'!: -005
-0.15
-60
0
1:lQ
'80
'50
INPUT OFFSET ERROR VB
SOURCE RESISTANCE
OFFSET VOLTAGE
TEMPERATURE
r
2. CMP·02C
10
>-
~o
1=
F--
>-
itz
- '0
~
/
IIIIII
WORST CASE
o
>
2
~
-I
1
TYPICAL
0001
0010
.... r-
~~2
==
TA
2S"C
~YI
-25
25
MATCHED SOURCE RESISTANCE (MD.)
,l\..
"'-
40
30
""
~
.........
"U);
~
\2..i r-
20
t-
1
2
1
-75
I
-25
I
=
75
lOa
125
25
TEMPERATURE (OC)
75
-75
V+
V+ -0 5
,
125
-25
0
~
V+ -1 0
~
75
V+-l 5
---
1
~
: Vs+
1
w
~
3
Vs = ±15V
TA = 2SoC
-4
8-19
~
+1 5
V-+l 0
V-+05
57
12
DIFFERENTIAL INPUT VOLTAGE (VOLTS)
V- +2 0
g v;:
-f--
III
-8
125
:-1 Vs+ = 5V
w
;2
30
-12
Vs+ i5V
25
~ V+ -2 0
'0
r- -15V';;; VS-.;;; OV
~~
Vs+ i15V -
INPUT VOLTAGE RANGE
VB TEMPERATURE
20
1 I
J I
I.-.,..;..IVS+=SV -
TEMPERATURE (OC)
40
t:-i+
"
Vs+= 15V
-(i)
IRS," 50"
50
CMp·02
CMP·02E
1
\
w: :::::::
±15V
VS+=5V -
g~=:g~E
(O°c TO 70°C)
CMP·02C
-
I
50
Vs+ = 5V
'0 ~
Vs
- -
60
VS+=lSV _
1--1
~ 200
INPUT BIAS CURRENT
vs DIFFERENTIAL
INPUT VOLTAGE
I I
1 I
Vs+ = 15V
>-
TEMPERATURE (Oel
INPUT BIAS CURRENT
VB TEMPERATURE
50
o
2
2 CMp·02C
~ I-.."=:
~
CMP-02C
;;:
00'
-50
~400
WCT070°C)
I\0'-UIL~~
100
II
1 CMP·02
CMP·02E
(DOC TO 70°C)
1\.'\
'\
13
1
;;:
100
~
II
CMP·02
If-
;;:
±15V
1111'
0100
010
r\.
;: 600
CMP·OZE
>-
Vs
,
f--- f---
i
21""
o
1
2
I IIIIII
0'
INPUT OFFSET CURRENT
VB TEMPERATURE
VB
6-1-(, .::.-
UNNULLED
"~
;;
~
{Vas + OVERDRIVE I
(Vas - OVERDRIVE)
800
:;.§
~
rFALL
VIN-I.. RISE
'0
~' g~=:~~E
a:
210
'80
RESPONSE TIME (nsec)
o
ffi
'50
RESPONSE TIME (nsec)
'00
~a:
120
-60
210
=
15V
:1
1
~
I
1
~---I---l--l-----/--+-----''-I-----~--l
1---1===t=:::1=-1-~~d::::-I---j
--L- -15V"';;; VS-';;; OV
+5V;;;; VS+';;;; +15V
V- '--'-_---'-_l-----'_....L_..L_L.........J
-75
-25
0
25
75
125
TEMPERATURE re)
1/86, Rev. A
----------l~ CMP-02 LOW-INPUT-CURRENT PRECISION COMPARATOR
TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT VI
SUPPLY VOLTAGE
SATURATION VOLTAGE
VI SINK CURRENT
'0
1125o~
V
V
.:.,.
V
V V
,.....
~
V
l-- SUPPLY
25°~
V -55 C
,.......
IQ
10
20
30
40
OUTPUT SINK CURRENT
'00 f--f_+--:C;;..:,VS::.=::.':,:';:5V:;.,.:V;;,O.:=..:L::;OW;:"';;;;j
i.--
10<-
....... Ve"OSITIVE SUPPLY
/
o
50
lmAI
Y
V
V":
- f-- f-
~~~~~~:~~1~~
I
l?
OUr
-
r---r-..-----r-..---I--r-..-----r~
I
I
TA'" 2SoC
V
i...--::i ~
If'
'20
M'~'MU~ISPOS'~'VE
+45V
V
POWER CONSUMPTION
VI TEMPERATURE
OUTPUT HIGH
NEGATIVE SUPPLY
!
o
±5
±10
±15
-75
±20
'20
<"
T A '" 25°C
Vs = ±15V
100
S
ilia:
80
\ t-...
a:
"">-
:;
"a:
Ii
>a:
f.-..
Ti-!-
......
I'.
60
ill
V-leASE}
OUTPUT
~t= 10 SEe
~M~
40
33kn
STROBE
I
20
MIL-STD-883, METHOD 1015, CONDITION B
l0
>--+-----0 V+
t = 1 SEC
0
I.
I-
furUI TSIHOrTyD fT I' = 10
'0
0
'5
OUTPUT VOL rAGE (VOLTS)
RESPONSE TIME VI
SOURCE RESISTANCE
RESPONSE TIME,
100mV STEP AND VARIOUS INPUT OVERDRIVES
2
3
4
I
20mV
V
~
12,000
;:::
/
/
V
(/) rJ- J$) i¢ ,
/V/
/
~
-/
.....--::
V
/
w
~~ =L~~5~-
~ -0.10
TA = 25"C
~
-015
-60
120
TA=25°C
As = son
~0
'~"
c'4; ~
\
\
0,10
0.05
i<
4~
\
3~
2g
0,' ~
>-
,.
100mV STEP
NO LOAD
RS MATCHED TO 1.0%
~
r\
,0
0
I I
RESPONSE TIME {nsec}
\
\
\
\
"'
>
360
\
NO LOAD \
Vs = ±15V
AS=50n -
240
\
1\
2:
'~" -005
i<
'25
I-
I
I'
>-
'mV
2mV
5mV
I
75
I I
.....
V+
I
I
25
OFFSET TRIMMING AND
STROBE CIRCUITS
OUTPUT SHORT-CIRCUIT
CURRENT VI OUTPUT VOLTAGE
STANDARD BURN-IN CIRCUIT
,
-25
± SUPPLY VOLTAGE (VOLTS)
0
0"
2
3.
'mV
2mV
5mV
4.
20mV
I,.
1200
w
;::
w
k1
~a:
1=',
~~
420
'2
-005
-60
120
240
RESPONSE TIME (nsec)
8-20
360
420
2l.,... 3
'20
>~
./
I-
!Ii
2mV OVERDRIVE
5mV OVERDRIVE
20mV OVERDRIVE
TTTTIIlf Tn
0'
Vs = :t15V
TA I=
10
10
SOURCE RESISTANCE (knJ
~~CI
'00
1/86, Rev. A
----------I~ CMP-02 LOW-INPUT-CURRENT PRECISION COMPARATOR
APPLICATIONS INFORMATION
The CMP-02 provides fast response times even with small
overdrives; to achieve this performance requires very high
gain at high frequencies. The CMP-02 is completely free of
oscillations; however, small values of stray capacitance from
output to input when combined with high-source resistances
can cause an unstable condition. DC characteristics are not
affected, but when the input is within a few microvolts of the
transition level, certain conditions can create an oscillation
region. The width of this oscillatory region and the size of
source resistance where oscillations begin is a strong function ofthe stray coupling present. The following suggestions
are offered as a guide towards minimizing the conditions for
oscillation: matched source resistors, minimized stray capacitances (e.g., a ground plane between output and input), or
capacitive output loading (CLl. The capacitive loading techniques will eliminate the oscillations, but result in slower
response time. Matched bypass capacitors across the input
resistors also can eliminate the instability,
and if C :::: 20 F (m~~imUm step s~ze)
S
p
minimum overdrive
the response time will approximate the response time for low
values of Rs. It should be noted that the offset nulling
terminals do not require bypassing for stability. As with all
wideband circuits, it is recommended that the supplies be
bypassed near the socket of the device.
PRECISION, DUAL LIMIT, GO/NO GO TESTER
+15V
V L '" 32V
IL < 75mA
UPPER
LIMIT
MINIMIZING OSCILLATION
INPUT
LAMP
-15V
OUTPUT
•
LOWER
LIMIT
-15V
8-21
1/86, Rev. A
CMP-04
QUAD lDW-POWER
PRECISION COMPARATOR
PrecisIon Monolithics Inc.
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
Four preCision independent comparators comprise the CMP04. Performance highlights include a very low offset voltage,
low output saturation voltage and high gain in a single supply
design. The input voltage range includes ground for single
supply operation and V- for split supplies. A low power
supply current of 2mA, which is independent of supply
voltage, makes this the preferred comparator for precision
applications requiring minimal power consumption. Maximum logic interface flexibility is offered by the open-collector
TTL output.
High Gain ............................. 200VlmV Typ
Single or Dual Supply Operation
Input Voltage Range Includes Ground
low Power Consumption (1.5mW/Comparator)
low Input Bias Current .................... 100nA Max
low Input Offset Current ................... 10nA Max
low Offset Voltage ......................... 1mV Max
low Output Saturation Voltage ...•.... 250mV @ 4mA
logic Output Compatible with TTL, DTl, ECl, MOS and
CMOS
• Directly Replaces lM139/239/339 Comparators
PIN CONNECTIONS
ORDERING INFORMATIONt
2S"C
Vos
(mV)
DIP PACKAGE
HERMETIC
14-PIN
PLASTIC
14-PIN
OPERATING
TEMPERATURE
RANGE
CMP04FP
MIL
INO
COM
CMP04BY'
CMP04FY
14-PIN HERMETIC DIP
(V-Suffix)
14-PIN EPOXV DIP
(P-SuHlx)
• For devices processed In total compliance to MIL-STD-883, add /883 after
part number Consult factory for 883 data sheet
tAli commerCial and mdustrial temperature range parts are available with
burn-In, For ordering information see 1986 Data Book, Section 2
SIMPLIFIED SCHEMATIC (1/4 CMP-04)
TYPICAL INTERFACE
Driving CMOS
50
v.
100kn
OUTPUT
r ......-f--+<>-INPUT
Driving TTL
50
*SUBSTRATE DIODES
8-22
1/86, Rev_A
----------I~ CMP-04 QUAD LOW-POWER PRECISION COMPARATOR
ABSOLUTE MAXIMUM RATINGS
(Note 2)
Input Current (VIN
< -3.0V) •••••••••••••••••••••••• 50mA
36V or±18V
Output Short-Circuit to GND •••••••••••••••• Continuous
Differential Input Voltage •••.••••••••••••••••••••• 36VDC
Lead Temperature (Soldering, 60 sec) ••••••••••••• 300· C
NOTES:
1 See table for maximum ambient temperature rating and derating factor.
2. Absolute maximum ratings apply to both packaged parts and DICE, unless
otherwise noted.
Supply Voltage •••.••••.•••..•••••••••.••••
Input Voltage ••••••.••..••••..••••••.••••• -0.3V to +36V
Power Dissi pation (Note 1) ••••••••.•••••••••...• 500mW
Operating Temperature Range
CMP-04FY ••••••••••••••••••••••••••
-25° C to +85° C
to + 70· C
PACKAGE TVPE
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
DICE Junction Temperature (Tj) •••••••
Storage Temperature Range. • • • • • • • . ••
-65°Cto+150°C
-65° C to + 150° C
Hermetic DIP IV)
100'C
10mW/'C
P-Suffix • • • • • • • • • • • • • • • • • • • • • • • • • • ••
-65° C to + 125· C
50'C
6mW/'C
CMP-04BY •••••••••••••••.•••••••••
-55° C to + 125° C
CMP-04FP •••••••••••••••••••••••••••••
O· C
Plastic DIP IP)
ELECTRICAL CHARACTERISTICS at V+ =
+5V, TA
PARAMETER
SVMBOL
CONOITIONS
Input Offset Voltage
Vas
Rs=OO, RL =5.1kO
Vo = 1.4V, INote 1)
Input Offset Current
los
I,NI+) -I'NI-)
RL =5.1kO
Vo= 1.4V
= 25· C, unless otherwise noted.
CMP-04B/F
MIN
Input Bias Current
Ie
I,NI+) or I'NI-)
Av
RL " 15kO, V+ = 15V, INote 5)
Large-Signal Response Time
t,
Y'N = TTL Logic SWing
VAEF = 1 4V, INote4)
VAL = 5V, RL = 5.1kO
Small-Signal Response Time
t,
Y,N = 100mV Step, (Note 4)
5mV Overdrive
VAL = 5V, RL = 5.1kO
Input Voltage Range
CMVR
INote2)
CMRR
INotes 3,5)
Power Supply Rejection Ratio
PSRR
Saturation Voltage
VOL
MAX
0.4
25
80
100
V+ = +5V to 18V, INote 5)
nA
nA
200
VlmV
300
ns
C/.l
~
1.3
I'S
V
80
100
dB
80
100
dB
= 0,
2S0
400
mV
'SINK:54mA
Output Sink Current
ISINK
V,NI-) " 1V,
V,NI+) = 0, V0 51 SV
Output Leakage Current
ILEAK
V,N (+) ,,1V,
V,NI-) = 0, Vo = 30V
01
100
nA
1+
RL =~, All Camps
V+ = 30V
08
20
mA
Supply Current
6
16
mA
NOTES:
1. At output SWitch pOint, Vo = 1 4V, Rs = 00 with V+ from SV; and over the
full input common-mode range 10V to V+ -1.SV).
2. The Input common-mode voltage or either Input signal voltage should not
be .IIowed to go negative by more than 0.3V. The upper end of the
common-mode voltage range IS V+-1.5V, but either or both Inputs can go
to +30V without damage.
3. RL " 1SkO, V+ = 15V, VCM = 1.SV to 13.5V.
4. Sample tested.
5, Guaranteed by design,
8-23
•
0
V+-1.5
v,NI-) " 1V, V,NI+)
UNITS
mV
10
Voltage Gain
Common-Mode Rejection Ratio
TYP
1/86, Rev_ A
~
~
~
U
>LI
~
tj
~
-----------f!fMD
CMP-04 QUAD LOW·POWER PRECISION COMPARATOR
ELECTRICAL CHARACTERISTICS at V+ = +5V. For CMP-04BY, -55 0 C::; TA::; 1250 C. For CMP-04FY, -25 0 C::; TA::; 85 0 C.
For CMP-04FP, 00 C ::; TA::; 70 0 C, unless otherwjse noted.
CMP-04B/F
(Nole 3)
PARAMETER
MIN
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs = on. RL = 5.1kn
vo= 1.4V, (Note 1)
'nput Offset Current
'os
"N(+) -"N(-)
RL = 5.1kn
Vo = l.4V
Input Bias Current
'8
"N(+) or "N(-)
Vo'tage Gai n
Av
RL " 15kn. V+ = 15V, (Note 5)
Large-Signa' Response Time
t,
V'N = TTL Log'c Swing
VREF = 1.4V. (Note 4)
VRL = 5V, RL = 5.1kn
Small-Signal Response Time
t,
V'N = 100mV Step. I Note 4)
SmV Overdrive
VRL = 5V. RL = 5.1kn
TYP
MAX
UNITS
mV
70
4
20
40
200
CMVR
INote2)
CMRR
INotes 3. 5)
60
Power Supp'y Rejection Ratio
80
nA
125
VlmV
300
ns
1.3
I'S
0
'nput Voltage Range
Common-Mode Rejection Ratio
nA
V+-1.5
100
V
dB
PSRR
V+ = +5V to 18V
Saturation Voltage
VOL
V'N(-)" 1V, V'NI+) = O.
IS'NK,,4mA
100
Output Sink Current
'SINK
V'NI-)" 1V.
V'NI+) =0, Vo ,,1.5V
Output Leakage Current
'LEAK
V'NI+)" 1V.
V'N'-) = 0, Vo = 30V
0.1
200
nA
Supply Current
1+
RL =~. All Comps
V+= 30V
1.2
3.0
rnA
250
5
dB
700
16
mV
rnA
NOTES:
1. At output switch pOint. Vo=l.4V. Rs=Onwith V+from5V; andoverthefull
input common-mode range (OV to V+ -1.5V)
2. The input common-mode voltage or either Input signal voltage should not
be allowed to go negative by more than 03V. The upper end of the
common-mode voltage range is V+-1.SV, but either or both inputs can go
to +30V without damage.
3. R L " 15kn, V+ = 15V. VCM = 1.5V to 13.5V.
4. Sample tested.
5. Guaranteed by design
8-24
1/86, Rev. A
------------t~ CMP-04 QUAD LOW-POWER PRECISION COMPARATOR
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
6.
7.
OUTPUT (2)
OUTPUT (1)
POSITIVE SUPPLY
INVERTING INPUT (1)
NONINVERTING INPUT (1)
INVERTING INPUT (2)
NONINVERTING INPUT (2)
8.
9.
10.
11.
12.
13.
14.
INVERTING INPUT (3)
NONINVERTING INPUT (3)
INVERTING INPUT (4)
NONINVERTING INPUT (4)
GROUND (SUBSTRATE)
OUTPUT (4)
OUTPUT (3)
For additional DICE information refer to
1986 Data Book, Section 2.
DIE SIZE 0.052 x 0.056 Inch, 2912 sq. mils
(1.32 x 1.42 mm, 1.88 sq. mm)
WAFER TEST LIMITS at V+ = +5V, TA = 25°C, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
Rs=OO, RL =5.1kO
Va = 1.4V, INote 1)
Input Offset Current
los
I'NI+) -I'NI-)
R L =5.1kO
Vo=1.4V
Input Bias Current
18
I'NI+) or
I'NI-), INote 1)
CMP-04N
CMP-04G
LIMIT
LIMIT
UNITS
mVMAX
Voltage Gain
Av
R L " 15kO, V+ = 15V, (Note 3)
Input Voltage Range
CMVR
INotes 2, 3)
Common-Mode Rejection Ratio
CMRR
Power Supply Rejection Rat,o
PSRR
Saturation Voltage
VOL
10
25
nAMAX
100
100
nAMAX
80
50
V+-1.5
V+-15
VMAX
INote4)
80
80
dBMIN
V+ = 5V to +18V
80
80
dBMIN
~
400
400
mVMAX
0
6
mAMIN
100
nA MAX
2
mAMAX
V'NI-)" 1V, V'N(+) = 0,
I SINK ::54mA
Output Sink Current
ISINK
V'NI-)" 1V,
V'NI+) =0, VaS 1.5V
Output Leakage Current
ILEAK
V'NI+) ,,1V,
V'NI-) = 0, Va = 30V
Supply Current
1+
RL =~, All Comps
V+ = 30V
100
VlmVMIN
NOTE:
Electrical tests are performed at wafer probe to the limits shown Due to vanatlons In assembly methods and normal Yield loss, Yield after packaging IS not
guaranteed for standard product dice Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testmg
TYPICAL ELECTRICAL CHARACTERISTICS at V+ = +5V, unless otherwise noted.
PARAMETER
~
p:;
0
CMP-04N
CMP-04G
TYPICAL
TYPICAL
UNITS
Ir
V'N = TTL LogiC Swing
VREF = 14V, I Note 5)
VRL =5V, RL =51kO
600
600
ns
Ir
V'N = 100mV Step, (Note 5)
SmV Overdrive
VRL =5V, RL =5.1kO
1.3
1.3
I'S
SYMBOL
CONDITIONS
Large-Signal Response Time
Small-S'gnal Response Time
common-mode voltage range IS V+-1.5V, but either or both Inputs can go
to +30V without damage
NOTES:
1. At output switch pOint, Vo= 1.4V, Rs=OO with V+ from 5V; and overthe
full input common-mode range 10V 10 V+ -1.5V)
2. The input common-mode voltage orelther input signal voltage should not
be allowed to go negative by more than 0.3V. The upper end of Ihe
3. Guaranteed by design.
4. RL " 15kO. VCM = 1.5V to 13.5V
5 Sample tested.
8-25
1/86, Rev. A
Po<
~
U
r..t.l
~
b
§2
_ _ _ _ _ _ _ _ _---;~ CMP-04 QUAD LOW-POWER PRECISION COMPARATOR
TYPICAL PERFORMANCE CHARACTERISTICS
OFFSET VOLTAGE
VI TEMPERATURE
+0.2
......
~ +0.1
~
g
~
""'
~ -0.1
r-
t\..
I
't\..
-0.2
I
~ 140
~130
10
100 120 140
~ 100
I
09
"
-
07
~
J
16
20
26
30
36
-3.0
40
'to...
~
o
-40 -20
...-
«> 80
40
80
-
80 100 120 140
OUTPUT VOLTAGE VI
OUTPUT CURRENT AND
TEMPERATURE
- -TA =
,..
-t.Jc-
o"c
...-
TA = +70"C
.....
.
03
20
I--'"
-55'5,..-
...
,
05
I
90
-
~
TEMPERATURE (OC)
SUPPLY CURRENT
VB SUPPLY VOLTAGE
l\.
1/
~ 110
r--1.0
V+ - SUPPLY VOLTAGE Noel
TA
'\.
~
~
0
Jl-2.0
11
I
~ 120
g
r-..
~
1.0
a:
""
..... 1--
0 20 40 80 80
TEMPERATURE (OCI
160
2.0
I
VOLTAGE GAIN
VI TEMPERATURE
150
TA • 2"Cl7lfC
"-
TA"lfC
-0.3
-40 -20
~
~
a:
~ ~,.;,
1\
:g
>
3.0
80
+0.3
~
INPUT OFFSET CURRENT
VI TEMPERATURE
INPUT BIAS CURRENT
VI V+ AND TEMPERATURE
~,2.·C
70
80
--40 -20
0
20 40 60 80
TEMPERATURE ("el
100 120 140
10
20
6.0
~
'...
g~
i~
4.0
3.0
~o 2.0
0>
~, ~ '~"
w
~gs '"
5.0
"~
4.0
\
r'~
I
- > -100
'f I
1.•
-
..
f- I- TA"2"C .
I I I
I.
TA -25"C
1.0
VIN
I
I I
i~-60
5.1K
~
I I
5mV
II
0> 1.0
0
I
I
3.0
~~2.0
V OUT
,~
0••
w
g~
56
IN
...
100
INPUT OVERDRIVE = lOOmV
100mV
1.0
,
••0
+5Voc
. '
10
RESPONSE TIME FOR
VARIOUS INPUT
OVERDRIVES - POSITIVE
TRANSITION
I
5.0mV"VERDRIVE
6.0
1.0
10 - OUTPUT SINK CURRENT (rnA)
(Voel
RESPONSE TIME FOR
VARIOUS INPUT
OVERDRIVES - NEGATIVE
TRANSITION
w
0.1
40
30
SUPPLY VOLTAGE
I
I
2.0
TIME
8-26
I
1.0
0••
TIME (LIsee)
Vour
0:-
1.•
2.0
(~secl
1/86, Rev, A
-------------l~ CMP-04 QUAD LOW-POWER PRECISION COMPARATOR
TYPICAL APPLICATIONS
OUTPUT STROBING
INVERTING COMPARATOR WITH HYSTERESIS
V+
V+
+VIN
0---------1
V+
0----./11'01'--.---1
3kn
1Mn
Va
1Mn
*OR LOGIC WITHOUT
PULLUP RESISTOR
LIMIT COMPARATOR
SQUAREWAVE OSCILLATOR
V+
LED
+VREF HI
o--.NV'---i
f == 186kHz
Va
~
o
~
lOOk.l1
+VREF LOW
•
Po<
O--.NV'---i
~
U
~
o
COMPARING INPUT VOLTAGES OF OPPOSITE POLARITY
NON INVERTING COMPARATOR WITH HYSTERESIS
V+
V+
100kn
+VREF
0--------1
VINl
3kn
o--Mf----,
51k.l1
lOOkn
10kn
Va
8-27
1/86, Rev. A
~
~
~
-------------I~ CMP-G4 QUAD LOW-POWER PRECISION COMPARATOR
ONE-SHOT MULTIVIBRATOR
PULSE GENERATOR
V+
V+l
Rl
0-
tM!)
to
,M!)
'Ok!)
100pF
+VIN
15M2
0'
lN914
_ _ r:1-:'-- v+
o--j 1--....- - . -......--1
lm:=JPW~o
to
t1
Vo
to
lN914
t,
t2
lM.Q
,Mn
FOR LARGE RATIOS OF Rl/R2
D1 CAN BE OMITTED.
AND GATE
OR GATE
V+
39kn
200kn
3kn
3kn
10Ok.l1
A o------",'VV---,
+Q,Q75V
+0 375V
100kn
"0"
"1"
100kn
"0"
l00kn
lkn
"1"
100k.l1
lkn
lkn
1M2
l=A+B+C
ONE-SHOT MULTIVIBRATOR WITH INPUT LOCK OUT
V+
rE
~
+4V
,.
lMil
10Mn
lMn
15kn
560M2
100kn
+VIN
o---.vW'--.---......----+--I
o
Vo
10MO
to
t,
T = 03mSEC
100ld1
240kn
62k!l
8-28
1/86, Rev. A
------------i1fMD
CMP-04 QUAD LOW-POWER PRECISION COMPARATOR
TYPICAL APPLICATIONS
TIME DELAY GENERATOR
V+
,Okll
200k1l
'5k1l
3.0kIl
V+
10k.{l
o
V03
IO
r-
13
V3
6lkS)
3.OkIl
10MO
'0""
a1kO
-.-
10
VO.
V.
Ve,
I
o=r-••
V+
3.Okn
'0""
v+
.=r.,
10
VOl
V,
V;=r-L 10kn
'0
..
INPUT GATING SIGNAL
J
-=
e,
51kn
O.OO'_F
-::-
+VIN
BURN-IN CIRCUIT
GND
(OV)
GND
tOY)
~
,.
3.Ok
3.6k
'3
,.
~
....3 .......
1
+39V
3.Ok 30k
,"::~ZENER
~6.8VT06'V
ONE EACH
PER BOARD
1 WATT
6SOCKETS
~b~J~NT
S
'0
8
, .AZ-• ,;ot±--
, ~
•
•
3
'OOk
"
11
6
•
7
+36V
470k
MIL-STo 883, METHOD 1016, CONDITION B
8-29
----
-- ---------------
1/86, Rev. A
CMP-05
HIGH -SPEED PRECISION COMPARATOR
(WITH LATCH CIRCUIT)
Precision Monolithics Inc.
FEATURES
•
•
•
•
•
•
accuracy along with high speed. An exceptionally fast
response time of 60nsec is possible with only 1/2 LSB
overdrive (12-bit, 10-volt system).
Precision Input Stage
Input Offset Voltage. . . . . . . . . . . . . . . . . . . . . . . .. 150!'V
Input Offset Current ......................... 15nA
Fast Response Time (5mV Overdrive) ............ 38ns
High Voltage Gain ......................... 16,OOOV/V
Latch Function with TTL Compatible Input
TTL Compatible Output
Available In Hermetic Mini-DIP Package
The CMP-05 design makes itthe ideal component in systems
requiring high speed with excellent lOW-level analog signal
resolution. High-speed 12-bit successive approximation AID
converters, zero crossing detectors and logic threshold
detectors are typical system applications.
PIN CONNECTIONS
ORDERING INFORMATIONt
Vs+
•
PACKAGE
25°C
vos
(~v)
600
600
1000
1000
1000
HERMETIC
PLASTIC
TO-99
8-PIN
DIP
8-PIN
CMP05BJ'
CMP05FJ
CMP05CJ'
CMP05GJ
CMP05BZ'
CMP05FZ
CMP05CZ'
CMP05GZ
DIP
8-PIN
OPERATING
TEMPERATURE
RANGE
CMP05GP
MIL
INO
MIL
INO
COM
DIGITAL@7DUT
GROUND
+
+IN 2
-
6
-IN 3
8-PIN HERMETIC MINI-DIP
(Z-Suffix)
Vs- (CASE)
EPOXY MINI-DIP
(P-Suffix)
TO-99
(J-Suffix)
"For devices processed In total compliance to M IL-STO-883, add /883 after
part number Consult factory for 883 data sheet.
tAil commercial and Industrial temperature range parts are available with
burn-In. For ordenng information see 1986 Data Book, Section 2
~~li~E
,5 N C.
4
LOGIC TABLE
LATCH ENABLE
o or NC
GENERAL DESCRIPTION
1
The CMP-05's very high speed and precision input specifications make it the ideal comparator in systems needing 12-bit
OUT
Comparing
Latched
SIMPLIFIED SCHEMATIC DIAGRAM
L-~~--~
______-+________
~
____
8-30
~~
______
~
__
~
____________
~vs_
1/86, Rev. A1
------------I~ CMP-05 HIGH-SPEEO PRECISION COMPARATOR
ABSOLUTE MAXIMUM RATINGS (Note 2)
Positive Supply Voltage ............................. +6V
Negative Supply Voltage ........................... -18V
Power Dissipation (Note 1) ...................... 500mW
Differential Input Voltage ........................... ±5V
Latch Enable Input Voltage ........... -0.5V to V+ Supply
Operating Temperature Range
CMP-05B/C (J or Z Package)
(Note 3) ............................ -55·C to +125·C
CMP-05F/G (J or Z Package) .......... -25·C to +85·C
CMP-05G (P Package) .................. O·C to +70·C
DICE Junction Temperature (Ti) ......... -65·C to +150·C
Storage Temperature Range ............ -65· C to + 150· C
P-Suffix ............................. -65·C to +125·C
Lead Temperature (Soldering. 60 sec) ............. 300·C
Output Short-Circuit Duration - to ground .... Indefinite
- to V+ = 5.0V ... 1 Minute
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
TO-99 (JI
eo'c
7.1mW/'C
Epoxy Mini-DIP (PI
36'C
S.6mW/'C
Hermetic Mini-DIP IZI
7S'C
6.7mW/'C
PACKAGE TYPE
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
2. Absolute maximum rallngsapply to both packaged parts and DICE, unless
otherwise noted
3. Latch IS functional for -55°C ~ TA ::::: +85 0 C
-------------1[fMD CMP-05 HIGH-SPEED PRECISION COMPARATOR
ELECTRICAL CHARACTERISTICS at Vs+ =5.0V, Vs-=-5.0V, and Latch Enable grounded. ForCMP-05B/C, -55°C :5TA:5
125°C. For CMP-05F/G, -25°C:5 TA:5 85°C (J, Z Packages) and O°C:5 TA:5 70°C (P Package), unless otherwise noted.
CMP-05B/F
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs = 50n
Input Offset Voltage Drift
TCVos
MIN
CMP-05C/G
TYP
MAX
MIN
TYP
MAX
0.3
1.5
0.55
2.0
mV
1.5
7.5
2.5
15
I'VI'C
nA
UNITS
Input Offset Current
los
40
250
70
400
Input 81as Current
Ie
1.1
2.5
1.5
3.8
Voltage Gain
Avo
(Note 1)
6
11
10
Vim V
Input Voltage Range
CMVR
(Note 1)
±2.9
±3.2
±2.9
±3.2
V
Common-Mode Rejection
Ratio
CMRR
VCM = ±2.9V, (Note 1)
83
90
80
88
d8
Power Supply Rejection
Ratio
PSRR
±4.75V $ Vs $ ±5.25V
P Package
Output High Voltage
VOH
V,N " 10mV. 10 = OI'A
V,N " 10mV, 10 = 240l'A
V,N " 10mV, 10 = 160l'A
Saturation Voltage
VSAT
63
178
2.4
2.4
80
150
252
400
I'VIV
2.4
V
2.4
0.18
0.2
Y,N $ -10mV, ISINK = OmA
Y,N $ -10mV, ISINK = 9.6mA
Y,N $ -10mV, ISINK = 6.4mA
0.40
0.40
0.20
0.40
0.30
0.40
V
Positive Supply Current
Is+
Vo $ 0.4V
11
16
12
17
Negative Supply Current
1.--
Vo $ 0.4V
12
17
13
19
mA
Power DIssipation
Pd
Vo $ 0.4V
115
165
125
180
mW
Latch Input Current
Logic 1
Logic 0
'LH
'LL
VLH =3V, (Notes 1, 4)
VLL = 0.8V. (Notes 1. 4)
18
10
90
18
10
90
50
tpd +
Voo= 1.2mV, (Notes 1, 2)
Voo = 5.0mV. (Notes 2. 5)
125
92
125
92
ns
tpd-
Voo = 1.2mV, (Notes 1, 2)
Voo = 5.0mV, (Notes 2, 5)
115
88
115
88
ns
t LPO +
(Notes 2, 4, 5)
56
30
56
30
ns
Input to Output High
Response Time
Input to Output Low
Response Time
Latch Disable Time
tLPoNOTES:
1. Guaranteed by design.
2. Times are for 100mV step inputs. See switching time waveforms.
3. A high on the latch enable input will cause the latch to assume the state
Minimum Input Timing Requirements·
LATCH
3V
1.4V- -
Parameter
-
-
-
--- -
T- - - - -
VIN
Minimum
Limit
Units
_. - -
·'~t:Jr- ~:~
OIFF,~~~~TlAL vos~t. -~+4 ,...-------\1
-1--------_\J __
-J.-'\.
VOLTAGE
50
of the comparator and not follow subsequent inputs.
4. Latch is functional for -55'C $ TA $ +85'C.
5. Sample tested.
SWITCHING TIME WAVEFORMS
E~ATBCL~
mA
ts
th
tw
Setup Time
Hold Time
Latch Pulse Width
35
10
25
ns
'ts, th' tw are tested with Y,N = 100mV and Voo= 5mV.
- - - - --
00
tLPO_-j
t pd
VOH
OUTPUT t.4V- -
-
-
-
VSAT _ _ _ _ _
8-32
1/86, Rev. A1
------------t/fMD CMP-Cl5 HIGH·SPEED PRECISION COMPARATOR
DICE CHARACTERISTICS
1.
2.
3.
4.
6.
DIGITAL GROUND
NON INVERTING INPUT
INVERTING INPUT
NEGATIVE SUPPLY (SUBSTRATE)
LATCH ENABLE
7. OUTPUT
6. POSITIVE SUPPLY
For addilional DICE Informallon rafar 10
1984 Dala Book, Sacllon 2.
DIE SIZE 0.051 X 0.045 Inch, 2295 sq. mila
(1.295 X 1.143mm, 1.481 sq. mm)
WAFER TEST LIMITS at Vs = ±5V, TA = 25° C, unless otherwise noted.
CMP·05G
LIMIT
UNITS
tooo
IlVMAX
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs= son
Input Offset Current
los
150
nAMAX
Input Bias Current
Ie
1.8
IlAMAX
Voltage Gain
Avo
(Note 1)
Input Voltage Range
CMVR
(Note 1)
Common·Mode Rejection
Ratio
CMRR
VCM = ±2.9V
(Note 1)
Power Supply Rejection Ratio
PSRR
Positive Output Voltage
Saturation Voltage
Positive Supply Current
VlmV MIN
±3.0
VMIN
80
dBMIN
±4.75 :s Va:S ±S.25
Vs+ = SV, Vs- = -SV to -15V
178
63
IlV/V MAX
VOH
V,N ~ 10mV, 10 = OIlA
2.4
VMIN
VSAT
V,N:S 10mV, 10 = OIlA
0.4
V MAX
1+
Vo :SO.4V
16
mAMAX
Negative Supply Current
1-
Vo :SO.4V
18
mAMAX
Negative Supply Current
I-
V- = -ISV, Vo:S 0.4V
20
mAMAX
Latch Input Voltage
Logic 1
Logic 0
VlH
Vll
Latch Enabled
Latch Disabled
2.0
0.8
VMIN
V MAX
Latch Input Current
Logic 1
Logic 0
IlH
III
VlH = 3.0V, (Notes 1,4)
Vll = 0.8V, (Notes 1, 4)
45
2S
IlAMAX
Input to Output High
Response Time
tpd+
Voo = S.OmV, (Notes 1,2)
60
nsMAX
Input to Output Low
Response Ti me
tpd-
Voo = S.OmV, (Notes 1, 2)
60
nsMAX
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to vanations in assembly methods and normal yield loss, Yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±5V, TA = 25°C, unless otherwise noted.
CMp·05G
PARAMETER
SYMBOL
CONDITIONS
Input to Output High
Response Ti me
TYPICAL
UNITS
tpd+
Voo = 1.2mV, (Note 2)
41
ns
Input to Output Low
Response Time
tpd-
Voo = 1.2mV, (Note 2)
37
ns
Latch Disable Time
tlPO
(Notes 3,4)
so
ns
NOTES:
1. Guaranteed by design.
2. Times are for 100mV step inputs.
3. See switching time waveforms.
4. Latch IS functional for -5SoC:S TA S 8SoC.
8·33
1/86, Rev. A1
~
~
~
~
U
~
~
tj
~
------------l~ CMP-05 HIGH-SPEED PRECISION COMPARATOR
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT BIAS CURRENT
vs DIFFERENTIAL
INPUT VOLTAGE
VOLTAGE GAIN
VB FREQUENCY
100
I I II
90
VS" ±5V
1200
VSAT vs LOAD CURRENT
,...._~-,..---,---r--:;o_.....,
0.600
./
0.450
TA "" 2SOC
TA = +2SOC ........
1000 ( - - + - - - J . - - + - P - - - - I - - _ _ _ j
0.400
.....
800 (--t---r----\-+f--r---r-___j
ii)
:;
~
600
TA = +125°C
0350
I~
0300
~V
~
g
0250
....... ~
400 f - - + - - + - - + + - \ - - + - _ f - _ _ _ j
0200
40
200f--+--~-+--~--_f--___j
0'00
30
0.1
10
100
FREQUENCY (MHz)
-150
1200
600
60
40
-
'\ "\ t'<;j'B
1"-
-75 -50
0
25
10
50
Llw
,.:.~~
/
/
75
100
0
125
/
70
40
t-- 1 2mV OVERDRIVE
~
t--
V
+
ILOAD
OUT
8
2
10
12
14
....-
L
V
16
VOL
18
20
/ /
Vs" ±5V
I-- lOOmV INPUT STEP
50
. . , TA' _55°C
200
90
60
20
N
-25
o
..,
V
RESPONSE TIME vs BALANCED
SOURCE RESISTANCE
I
100
30
o
v~. '5V'
80
30
"- b--- 'OS
200
120
110
50
1,\
400
V
~
~
ILOAD (rnA)
RESPONSE TIME vs
TEMPERATURE
Vs = ±5V
800
150
./.
DIFFERENTIAL INPUT VOLTAGE (mY)
INPUT CURRENTS vs
TEMPERATURE
toaD
0.150
i"'"
~
~ /'
/
E
w
~
;::
"""""SmV OVERDRIVE
,...... ........-
125
w
~
~
V
- ,oor
TA '" 25°C
_ 150
/
/
175
-
/ /
Lv OLDRIVV~ / /
IN'UIT STEP
100
CC 75
50
25
./" ~
/ Vsmv
OVERDRIVE
,/
::..-o
BALANCED SOURCE RESISTANCE {knj
TEMPERATURE (OC)
8-34
1/86, Rev. A1
------------I~ CMP-05 HIGH-SPEED PRECISION COMPARATOR
TYPICAL PERFORMANCE CHARACTERISTICS
RESPONSE TIME
TO SmV AND 1.2mV
(= 1/2 LSB) OVERDRIVES
RESPONSE TO 10MHz
SINE WAVE
+10mV
INPUT
14
INPUT
-
,
I'
I
,
+2V
OUTPUT
+1V
I
OV
I
r
r... r':.'=. ::1
r
i
+3V
,
OUTPUT
1
Iii
.!!!!!!!
10ns/DIV
HO~mV
J,
L 1.c:50mv;l;
-VOD
10mV
Ir 2~mV
r- ~oD'25mv",,-
'0 ~ V /
'51 ff fd- 1";:- ~ --- -J"
rlsmv
'\ ~"I 1\ IX /
l00m~omv
I I
:t-
Ipd_RESPONSE TIME
Ipd+ RESPONSE TIME
---
12mV
OVERDRIVE
--1- llii
20ns/DIV
14
5mV
OVERDRIVE
i
,
~
+10mV
-1. . .·1~
14
-- --- -\-
\ \
1'-5mV-'·fmv
,12mV
+-h ~f v- --- --\
\ \
' - 10my
+100
+100
t
t
Vos
-100
10
t
INPUT OVERDRIVE (VOO)
VOS
t
-100
20
30
40
50
60
70
INPUT OVERDRIVE (VOO)
10
20
30
40
50
60
70
RESPONSE TIME (ns)
RESPONSE TIME (ns)
CMP-OS NEGATIVE COMMONMODE INPUT RANGE vs
NEGATIVE SUPPLY
RESPONSE TIME vs
OVERDRIVE VOLTAGE
-17
CMP-05
-15
VIN = 100mV + VOO
TA = 2SoC
V+=+50V
TA = 25°C
100
-13
/V
-11
80
-9
60
-7
V
/
40
::::::: :::::.....
-5
20
tpr
-3
-2
-4
-6
-8
-10
-12
-14
7
-16
tpd+
10
30
70100
V oo (mV)
NEGATIVE SUPPLY VOL rAGE (VOLTS)
8-35
1/86, Rev. A1
•
-------------l~ CMP-05 HIGH-SPEED PRECISION COMPARATOR
APPLICATION INFORMATION
Fortunately, in high-speed circuitry the comparator inputs
will be driven at a fast rate, in which case no transition region
oscillations will occur. As the minimum slew rate versus
source resistance curve indicates, if the input is driven at a
rate exceeding 6mVll'sec, no oscillations will occur with
source resistors of less than 1kO. Examples of "clean" transitions can be observed in the photographs of the response
time with SmV and 1.2mVoverdrives, and the response to the
10 and 2SMHz input signals.
The CMP-OS is a very accurate device providing fast response
time even with small-Microvolt level-overdrives. To achieve
this performance requires high gain at high frequencies. As
shown in the voltage gain versus frequency curve, the gainbandwidth product of the CMP-OS is 1.S X 1011 Hz. It maintains its full gain to approximately8MHz and rolls off at a very
fast rate beyond that frequency due to the fact that five poles
occur in the 30 to 60MHz range. At 30MHz the gain of the
comparator is still 2000. Therefore, in the transition region
small values of source lead inductance and stray feedback
capacitance can cause an oscillatory condition.
Forexample (in the figure below) with L=0.1I'H, Cs=0.1SpF,
the closed-loop gain of the circuit at 30MHz is:
In order to not degrade its speed the CMP-OS's inputs are not
internally clamped. If large differential voltages are present it
is recommended that the inputs be clamped with high speed,
low capacitance diodes such as the H.P. S082-283S, which is
a Schottky Diode.
A - _1_ v- LCsw2 -10
As in all high-speed devices, it is to the user's advantage to
keep the source impedances low and matched.
7
1
X 0.1S X 10-12 X (271' X 30 X 10 6 )2
880
1
LATCH
The CMP-05 has a latch feature which functions over -55° C
to +85° C. When the latch is enabled, the output stays in its
existing logic state regardless of the input signal. The input
timing requirements of the latch are presented in the Switching Time Waveforms. The latch opens up a broader applications area at no sacrifice in total system speed. Effectively,
the latch allows high speed sampling of comparison decisions. This is important in automatic test equipment limit
comparators, in measuring pods used in logic analyzers and
other similar synchronous measurement circuitry needing
fast clocking frequencies. The latch pulse width tw allows
sampling of input signals to take place in 2Snsec.
POTENTIAL FEEDBACK SOURCES
Cs
VOUT
With the open-loop gain at 2000 oscillation will occur since
the phase shift exceeds 180°C. To minimize these problems
powersupplies should be decoupled, lead lengths should be
kept as short as possible, and a ground plane should be used
to reduce the stray feedback capacitance. In addition, a
ground plane substantially diminishes the possibility of the
output current spike coupling back to the inputs through the
ground lead. Keeping a separate digital ground (pin 1) and
analog ground (to which the inputs are referenced) also
reduces the magnitude of the problem.
The latch prevents self oscillation (due to positive feedback)
from taking place when slowly-moving high-sourceimpedance signals pass thru the linear amplification region
of the comparator. This is successfully accomplished by
rapidly strobing the comparator near its minimum tw time
which prevents self oscillation from making a complete cycle
since tw is shorter than the total response time tpd through
the comparator.
12-BIT FAST AID CONVERTER
SERIAL
DATA OUT
CONVERSION TIME vs ACCURACY
1.25
\
\
100
CLOCK
(WOI\ST CASE)\
+15V
DAC-312
LS8
CMP..()5
075
050
r--
(TVr
REF-Ol
025
000
100
,\
DAC-3~
CMP..()5
200
300
\
'"
400
500
600
700
BOO
CONVERSION TIME PEA TRIAL (n5)
CONVERSION
TIME (nl)
SAR
CMP-oS
NOTE
TYP
33
92
WORST
CASE
55
TOTAL
375ns
125
680n8
x 13
49J.1s
88,us
DEVICE(S) CONNECTED TO ANALOG INPUT MUST BE CAPABLE OF SOURCING 4.0mA
A BUFFER (eg aUF·OJ) MAY BE REQUIRED
8-36
1/86, Rev. A1
CMP-07
VERY HIGH -SPEED COMPARATOR
(WITH LATCH CIRCUIT)
Precision MOll0lithics Inc.
PRELIMINARY
FEATURES
•
•
•
•
•
•
•
latch timing is also faster than the Am685, resulting in less uncertainty when used as a sampling comparator.
Input-to-Output Propagation
Delay at 5mV Overdrive ..............• 6.5ns Max
latch-to-Output Propagation
Delay at 5mV Overdrive ............... 5.5ns Max
latch Pulse Width •....•.•................ 2ns Min
low Power Dissipation ................. 200mW Max
ECl Compatible Complementary Outputs and latch Input
50 Ohm Line Driving Capability
Pin Compatible with Am685
The CMP-07 is specified for operation with a standard -5.2V ECl
power supply and a +6V supply. The circuit operates with a +5V
supply with some reduction in input voltage range. The output
stage directly drives 50n transmission lines.
The CMP-07 electrical characteristics are ideally suited for use in
data conversion systems, logic analyzer probes, automatic test
equipment, pulse detectors, and simple flash converters.
PIN CONNECTIONS
ORDERING INFORMATIONt
PACKAGE
TO-100
DIP
OPERATING
TEMPERATURE
RANGE
CMP07BK'
CMP07FK
CMP07BO'
CMP07FO
MIL
IND
16-PIN CERDIP
(Q-Suffix)
TO-100
(K-Suffix)
GND1
v@."o
9 GN02
• For devices processed In total ocmpliance to MIL-STD-883. add 1883 after part
number. Consult factory for 883 data sheet.
tAil ocmmerClal and industrial temperature range parts are available with burn-In
For ordering information see 1986 Data Book, Section 2.
+IN2
+
-IN 3
-
LE 4
saOUT
7QOUT
,
6 N.C.
v-
NOTEPin 5 IS connected to package
GENERAL DESCRIPTION
LOGIC TABLE
The CMP-07 is a very high-speed comparator with complementary EeL output logic compatibility. It offers the same propagation
delay specifications as the Am685, at 66% of the Am685's power
consumption, reducing heat generation and improving reliability.
LATCH ENABLE
OUT
LOW
LATCHED
HIGH
COMPARING
BLOCK DIAGRAM
INPUT
+IN 0 - I - -
-IN10-
r>....
1--1;:/
LEVELSHIFTI
2NDSTAGEI
LATCH
STAGE
~
Q
0
>
OUTPUT STAGE
ii
Q
LE
V
LE
>
Q
RL
RL
LATCH ENABLE
BUFFER
LE
~
VT
>
IV
--O OUTPUT
50n
-VREF
4.7k
0-.,....--01
50H
S011
-5.2V
-2.0V
(PINS SHOWN FOR DUAL-IN-LINE PACKAGE)
OUTPUT PULSEWIDTH "" 0.75 C (Rl
+ R2)
8-39
1/86, Rev_ A
•
:
CMP-404
®IPMI)
QUAD LOW-POWER
PRECISION COMPARATOR
Precision Monolithjcs Inc.
FEATURES
•
•
•
•
•
•
•
The low input-offset-voltage makes the CMP-404 an ideal
companion to CMOS logic when the stability and accuracy of
a bipolar technology is needed along with low power consumption. The open-collector outputs with pull-up resistors
provide CMOS interface with excellent noise immunity.
Improved isolation between comparators was achieved by
use of an independent bias circuit for each comparator. This
is especially important when one comparator is detecting
low-level signals while an adjacent comparator is being
driven by a high-level signal. In single-supply operation, the
inputs can operate at ground. The CMP-404 can operate from
5 to 30 volts single supply or ±2.5 to ±15 volts dual supply.
Very Low Power Consumption .............. 1.5mW Max
Low Input Offset Voltage .................. , .. 1mV Max
Very Low Drift ............................ 3/lV/o C Typ
High Output-Drive Current .................. 25mA Typ
Single or Dual Supply Operation
Ideal for CMOS Logic Interface
LM139 Pinout
ORDERING INFORMATIONt
25°C
Vos(mV)
HERMETIC
DIP PACKAGE
1
2
1
CMP404AY'
CMP404BY'
CMP404EY
CMP404FY
2
OPERATING
TEMPERATURE
RANGE
Window comparators, limit comparators, multivibrators, one
shots, voltage-controlled oscillators, and set-point detectors
are common applications.
MIL
MIL
INO
INO
PIN CONNECTIONS
• For devices processed in total compliance to MIL-STD-883. add 1883 after
part number. Consult factory for 883 data sheet.
t All commercial and industrial temperature range parts are available with
burn-in. For ordering information see 1986 Data Book, Section 2.
GENERAL DESCRIPTION
Four precision-input comparators provide excellent speed
with low power consumption through use of a novel Schottkyclamped design. These open-collector output comparators
only consume 365 microwatts each, yet they make accurate
5mV decisions in only four microseconds. In addition, they
can drive load currents of 25mA. This output stage is ideal for
driving relays, lamps, and LEDs.
14-PIN HERMETIC DIP
(V-Suffix)
SIMPLIFIED SCHEMATIC (1/4 OF CMP-404)
V+
......-o OUT
+--t---r>l--I~>I-+INPUT
-'NPUT
o-_--+----jf-+-----+----I
8-40
1/86, Rev. A
-----------I~ CMP-404 QUAD LOW-POWER PRECISION COMPARATOR
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage ............................ 36V or
± 18V
Storage Temperature Range ............. -6S0Cto + 1S0°C
Input Voltage ............................... -0.3V to V+
Input Current (Note 2) ............................. 20mA
Output Voltage •.•••••••••••••••.•.•••.•••• -0.3V to 36V
Output Short-Circuit to V+ (Note 3) ••.... , •..•.•..•. SOmA
Power Dissipation
•••.••...••••....••••••.•.•.•• SOOmW
Lead Temperature (Soldering, 60 sec) ••............ 300° C
10mW/oC
...•.......•........... 100°C/W
NOTE:
1. Absolute maximum ratings apply to both packaged parts and DICE, unless
otherwise noted.
2. Limit for input current that flows when input voltage signals exceed V+ or
GND forward biasing internal junctions.
3. Short circuits to V+ can cause excessive heating and eventual destruction.
The maximum output current is SOmA.
Derate Above 100°C by .......................
Thermal Resistance (I1JA)
Operating Temperature Range
CMP-404EY/FY ....................... -2SoC to + 8SoC
CMP-404AY/BY ...................... -SsoC to + 12SoC
DICE Junction Temperature (Tj) .......•. -6So C to+ 1S0° C
ELECTRICAL CHARACTERISTICS at V+= SV, RL =
S.1 kOand-SSo C$TA$12S0C forCMP-404AY/BY; -2SoC $TA $8S0C
for CMP-404 EY/FY, unless otherwise noted.
PARAMETER
Input Offset Voltage
SYMBOL
Vas
Average Input Offset
Voltage Drift
TCVos
Input Offset Current
los
Input Bias Current
I.
CMP-404A/E
MIN
TYP
MAX
CONDITIONS
mV
Rs = 5011, Full Temp
mV
IINI+I-IINI-I' TA=25'C
10
25
nA
IINI+I-IINI-I' Full Temp
50
100
nA
10
liN 1+1 or liN I-I' TA = 25'C
Av
RL = 15kll
tr
Voo=5mV, V STEP =100mV
RL =5.1kll, TA=25'C(Note4)
Large-Signal
Response Time
tr
VIN = TTL Logic Swing
V RE ,= 1.4V, RL =5.1kll
Input Voltage Range
CMVR
Saturation Voltage
VOL
50
Output Leakage Current
ISINK
10
3.5
3.5
~s
0.8
0.8
~s
0
75
TA = 25'C, (Note 2)
50
V+ -1.5
V+ -15
V
V+ -2
V+ -2
V
85
0.32
75
0.4
85
0.32
0.5
VIN (_I = W
VIN (+I=OV, Vo=2V, (Note 5)
10
25
001
TA = 25'C, (Note 3)
nA
nA
Vim V
TA = 25'C
RL = 15kll, (Note 6)
100
200
400
400
Full Temp, (Note 2)
Output Sink
Current
50
100
TA = Full Temp
CMRR
~V/'C
3
Rs = 5011
Small-Signal
Response Time
Common-Mode
Rejection Ratio
UNITS
Rs = 5011, TA = 25'C
liN 1+1 or liN I_I' Full Temp
Voltage Gain
CMP-404B/F
MIN
TYP
MAX
10
0.1
dB
0.4
V
0.5
V
25
001
mA
0.1
~A
0.4
~A
ILEAK
Full Temp, (Note 3)
Power Supply
Rejection Ratio
PSRR
V+ = 5V to 30V, RL = 15kll
Supply Current
1+
RL =co
04
75
100
220
65
300
100
220
dB
350
~A
NOTES:
1. TYPical values are reported for TA = 25'C.
2. ISINK = 1mA, VIN H = W, VIN (+1 = OV
3. VIN (_I = OV, VIN 1+1 = W, Va = 30V
4. Guaranteed by design. See response-time test circuIt.
5. Output Sink Current should be limited to SOmA by external resistance
6. Applies over the CMVR range
8-41
1/86, Rev. A
~
0
~
p.j
:E
0
U
~
~
b
~
_ _ _ _ _ _ _ _ _ _~~ CMP-404 QUAD LOW-POWER PRECISION COMPARATOR
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
6.
7.
OUTPUT (2)
OUTPUT (1)
POSITIVE SUPPLY
INVERTING INPUT (1)
NONINVERTING INPUT (1)
INVERTING INPUT (2)
NONINVERTING INPUT (2)
8.
9.
10.
11.
12.
13.
14.
INVERTING INPUT (3)
NON INVERTING INPUT (3)
INVERTING INPUT (4)
NON INVERTING INPUT (4)
GROUND
OUTPUT (4)
OUTPUT (3)
For additional DICE information refer to
1986 Data Book, Section 2.
DIE SIZE 0.068 X 0.076 inch, 5168 sq. mils
(1.727 X 1.93 mm, 3.33 sq. mm)
WAFER TEST LIMITS at V+
=
5V, RL = 5.1 kfl., TA = 25°C, unless otherwise noted.
CMP-404G
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
Rs ~ 50ll
Input Offset Current
los
IIN(+) -liN (-)
Input Bias Current
18
IIN(+)
Voltage Gain
Av
RL
~
15kll
LIMIT
25
or IIN(-l
Input Voltage Range
CMVR
Common-Mode Rejection RatiO
CMRR
RL
~
15kll
Power Supply Rejection RatiO
PSRR
V+
~
5V to 30V. RL
Saturation Voltage
VOL
'SINK = 1mA
Output Sink Current
'SINK
V,N I_I ~ 1V
V,N 1+1 ~ OV. Va ~ 2V
Output Leakage Current
'LEAK
V,N I_I ~ OV
V,N 1+1 ~ 1V, Va
Supply Current
1+
RL
=
UNITS
mVMAX
~
~
15kll
nAMAX
50
V/mV MIN
V+ -15
VMAX
75
dBMIN
65
dBMIN
0.4
VMAX
10
mAMIN
0.1
30V
300
!Xl
nAMAX
100
~A
MAX
~AMAX
NOTE:
Electrical tests are performed at wafer probe to the limits shown Due to vanatlons in assembly methods and normal Yield loss, Yield after packaging is not
guaranteed for standard product dice Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing
TYPICAL ELECTRICAL CHARACTERISTICS at V+
=
5V, unless otherwise noted.
CMP-404G
PARAMETER
SYMBOL
Large-Signal
Response Time
tr
Smail-Signal
Response Time
tr
CONDITIONS
V,N ~ TTL LogiC SWing
VREF~
Voa~
1 4V, RL ~ 51kll
5mV. VSTEP ~ 100mV
RL~51kll
8-42
TYPICAL
UNITS
0.8
~s
35
~s
1/86, Rev. A
-----------t1fMD
CMP·404 QUAD LOW·POWER PRECISION COMPARATOR
TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT
VI TEMPERATURE
50
VeIM'
400
~
~
a:
300
a:
a
~
200
~
~~
~3V
~
-~
-V
100
"
o
~
~
.........
30
20
/25, 12
10
_
0
~
~
~
o
=
~
o
o
16
20
10
VIN=lV
01
06
........ ........
-03
-50
-25
........ ........
32
-75
36
75
125
800
700
~0
'1'1..\
500
400
?
0
>
300
,
200
-75
:>
-so
-25
25
50
TEMPERATURE (OC)
75
100
125
100
125
OUTPUT CURRENT
OUTPUT VOLTAGE
II
_55°C
III
r1
III
15r---+-~fL~~~-+---+---1
I[j
'/
10~--+-~~~~---+---+--~
I
I/, rj III
& e:::;;. ;....-V
o
01
02
03
04
05
OUTPUT VOLTAGE (VOL TS)
OUTPUT VOL TAGE (VOL TS)
NEGATIVE RESPONSE TIME
vs OVERDRIVE
POSITIVE RESPONSE TIME
vs OVERDRIVE
60
60
50
50
"
40
V OD = 50mV
20mV
30
lOmV
~
0
5mV
?
0
>
20
V+= 5V
TA I= 250 C (
l
(
40 rVOD
10mV
=50mV
5mV
30
20mV
20
10
'>
'>
2
o
75
I\,
E
100
50
VB
10
1\
25
TEMPERATURE (OC)
AL'" lSk.l1
.,.,.
-25
I
J
........
100
OPEN-LOOP GAIN
VI TEMPERATURE
600
-50
~
II
_25°e,-..:
02
o
50
28
~~:~-..:
---- -
04
25
24
J II
JJ
08 - - - I T A ' 125"e
02
-04
-75
l
12
V+ =5V
r-
-55 o e
OUTPUT CURRENT
OUTPUT VOLTAGE
V+ =5V
V CM = OV
~
C
VB
04
-02
r
SUPPL Y VOLT AGE (VOLTS)
OFFSET VOLTAGE
VI TEMPERATURE
-01
........
r- r-
~ ~e
TEMPERATURE (OC)
03
V+ = 5V
40
.-- ""'" .....
i"'"
ol
I-
"..,
v+=;"- ~
INPUT OFFSET CURRENT
VI TEMPERATURE
INPUT BIAS CURRENT
VB SUPPLY VOLTAGE
E
-50
2
V+=5V
-100
TA = 25°C
10
20
TIME (us)
8-43
30
40
100
50
:>
10
2,0
30
4.0
TIME (/.Is)
1/86, Rev. A
-----------I~ CMP·404 QUAD LOW·POWER PRECISION COMPARATOR
TYPICAL PERFORMANCE CHARACTERISTICS
POSITIVE RESPONSE TIME
VB TEMPERATURE
NEGATIVE RESPONSE TIME
VI TEMPERATURE
RESPONSE TIME
VI OVERDRIVE
40
sv
V+ =
V+! 5V
I-- I
r-...
54
OVERDRIVE
--
~~
Lmv
I'-.
w
"
~
iji 3
z
~
0:
2
+2OmV
+rmv
...
...........
--
-50
-25
25
50
75
100
125
-75
TA = 25°C
\
30
i"""--
g
w
i'-
"
25
1\
20
\
~
r-
~
l!1
~
15
10
50mV
-25
0
25
50
75
100
TEMPERATURE (OC)
TEMPERATURE lOCI
RESPONSE TIME
OUTPUT LEAKAGE
VI TEMPERATURE
VI COMMON-MODE VOLTAGE
r.... r--.
~
0.'
o
-50
\'NEGATIVE OVERDRIVE
\~
r- POSIT~
OViRDRI~VE
0:
-20mV
o
-75
V+ '" 5V
3.
oVELRJ
t----;;;;;;;:; ~V
125
o
5
10
15
20
25
30
35
40
45
50
OVERDRIVE (mY)
INPUT-OUTPUT
TRANSFER CHARACTERISTIC
120
V+
=5V
v+ = 30V
TA '" 2S Q C
100
]
w
"~ 4
w
~
Z
~
-5mV OVERDRIVE
.0
+5m) OVERbRIVE
60
3
I
II
I
40
20
o
05
10
15
20
25
30
35
-75
- ""
/
~
-50
-25
25
50
75
100
125
-4
TEMPERATURE (OC)
COMMON-MODE VOL T AGE IVOL TS)
BURN-IN CIRCUIT
-3
-2
-1
0
INPUT VOLTAGE (mV)
RESPONSE-TIME TEST CIRCUIT
~~~o-~------------~--,-----~--------t--o~~~
•• V
+36V
o-.,+--+--.....~~......~---II------+---+----VH OR VS- 10kn
-
-.-.--.-
------------I~ CMP-404 QUAD LOW-POWER PRECISION COMPARATOR
TTL-COMPATIBLE ANALOG SWITCH
2N4391
TTL
CONTROL
INPUT
LeVEL SHIFTER
SWITCH DRIVER
-15V
LOW-FREQUENCY OPERATIONAL AMPLIFIER
OUTPUT STROBING
AV = 1000V/V
+5V
+5V
15kn
>-.......--
2.0
~
g
i
~
z
~ 0.2
-
o
-25
0
25
50
75
100
05
-55
w
"
-20,0
>-
-17.5
(,)
.
".
'":!
S
0:
0:
""
-15.0
'\
-12.5
25
50
75
100
125
-55
o
-25
25
50
75
100
COMMON-MODE LIMITS
vs TEMPERATURE
y+
VCM= OV
Vs=±15V
1
>ffi
.......
"
(,)
:--.....
~
o
...... r--....
>-
>-
~
10
12
-8
INPUT
-4
+4
COMMON~MODE
+8
+12
+16
-03
./
-04
-05
-55
f-Of--
4
_
~
~
~
~
~
m
TEMPERATURE (OC)
SATURATION VOLTAGE
vs SINK CURRENT
14r----;-----;-----r----~--_,
V
........
1.21----t---+--+--+---1
",..
~ 10~-~--_+--~--+_-~
~
a 08
.
1---+~~~--4---~~-1
~
~~
0.6
1---+-""-"+-""'~"""'-~""''''''''..-1
0.4
1---+....c--+:,.".'5'''I'''=----+---1
>
OUTPUT
RL == 600n
'"
0.2
0.21--""=---+--4---+---1
I
-05
_
125
Vs=±15V
ISINK = SOmA
0.8
1\
I \
-10
100
- --~
o. 2
F~~L6W~R 1\
0
0.4
y-
....... I-'"
0
::E
"8
0
VS= 30V
OUTPUT
Ri"10kfl
-1.5
SATURATION VOLTAGE
vs TEMPERATURE
T~ ~ 2~oC
_ COL~~~~~~----/I
0 - _I
8
;
TEMPERATURE (0C)
TRANSFER FUNCTION
-
~ -1.0
"
:;
J
0255075
-25
VOLTAGE (V)
50
/
r--
VOLTAGE
REFERRED TO SUPPLY VOLTAGES
E
/
~ -0.2
bOM~ON-MODE
125
-0.5
/
-0.1
!§
......... r.....
f--
",..
0:
20
o
-1.
"- ~
INPUT OFFSET CURRENT
vs TEMPERATURE
.....
>-
~
~
1
"15 30
"""
INPUT BIAS CURRENT
40
0
-22.5
Z
0:
0:
VCM == OY
Vs=±15V
TEMPERATURE (QC)
TA == 25°C
~
1>-
I'....
TEMPERATURE (OC)
50
.."
o
-25
-25.0
TEMPERATURE (OC)
vs COMMON-MODE VOLTAGE
'"~
/
---- -
o
125
VV
1.5
... 1.0
~
V
.§.
a
-55
V
VCM == OV
,. 08
INPUT BIAS CURRENT
vs TEMPERATURE
-275
ov
Vs == ±15V
"~
INPUT OFFSET VOLTAGE
vs TEMPERATURE
05
DIFFERENTIAL INPUT VOLTAGE (mV)
10
0
-55
-25
0255075
TEMPERATURE (
>E
~
\
\~
\
"
100
TA = 25°C
50
Vs= ±lSV
t--
~
i!:
1
o
240
05
10
15
20
25
30
3.5
TIME (n8)
TIME (/-t8)
COMMON-MODE REJECTION
RATIO vs TEMPERATURE
vs TOTAL SUPPLY VOLTAGE
TIME (n8)
RESPONSE TIME FOR
VARIOUS INPUT OVERDRIVES
180
120
\1\
20m~~ r\
~~~-./ 1\
-15
Vs = ±15Y
60
-5
~-."
~ ,,\
10
-10
TA = 25°C
200
e"
~€
:>
rD :/
,-
15
w
t:>
0
TA == 25°C
150
100
N J. rrl
/. r-J
II 1/'1
, \1\
L\ 1\
RESPONSE TIME FOR
VARIOUS INPUT OVERDRIVES
RESPONSE TIME FOR
VARIOUS INPUT OVERDRIVES
40
TOTAL SUPPLY CURRENT
•
120 ...--;-..,....-r--,--,.---,--,
20mV""""\.
5
::~~ I
i1. J
1/
II V
~
"
L
-
-10
-15
100~~=t::t::::t=t=~~
1
1 "I
50~-+--4---~-+--+-~--~
'-
601---+--+--1---+---+--t----1
~
401---+--+---1---+---+--t----1
~
i!
g~
i!:
20~-+--4---~-+--+-~--~
-50
TA= 25°C
ys~ ±1'5V
~- -100
o
o~~-~-~-L-~~-~
0.5
1.0
1.5
2.0
2.5
3.0
35
~.
VS=±15V
4.0
-55
-25
25
TIME (J.ls)
50
75
100
125
1
o
TA,= 25°C
I I
10
YIN = 10mV
15
20
25
30
35
TOTAL SUPPLY VOLTAGE (V)
TEMPERATURE (Oel
SUPPLY CURRENT
vs TEMPERATURE
4.5
40
3.5
3.0
Ys '" ±15V
.........
..........
2.5
NO LOAD
"
~
'~
~
t"-.....
..........
2.0
~
..........
1.5
1.0
-55
""
........
["..
-25
0
25
50
75
100
125
TEMPERATURE (0C)
8-53
1/86, Rev. A
J»1Vl-119/J»1Vl-219/J»1Vl-319
DUAL
COMPARATORS
Precision MOllolithics Inc.
ADVANCEPRODUCTINFO~TION
FEATURES
•
•
•
•
•
•
allowing output swings of up to +35V. High output drive capability facilitates RTL, DTL, and TTL interfacing, as well as relay and
lamp driving at currents up to 25mA. Typical response time of
80ns with ±15V power supplies makes the PM-119 ideal for
application in fast AID converters, level shifters, oscillators,
and multivibrators.
Fast Response Time ..•••....••••..•.•••• 80ns Typ
High Output Drive Current •...•.••...•.•••••• 2SmA
Single or Dual Supply Operation •••••.•. + SV to ± 1SV
Open Collector Outputs ••••..••••..•.•• Up to + 3SV
Inputs and Outputs Can Be Isolated from System Ground
Two Independent Comparators
PIN CONNECTIONS
ORDERING INFORMATIONt
PACKAGE
v+
HERMETIC
DIP
14-PIN
TO-100
10-PIN
PM119K'
PM219K
PM119Y'
PM219Y
PM319Y
EPOXY
DIP
14-PIN
OPERATING
TEMPERATURE
RANGE
PM319P
MIL
IND
COM
OUTA~'0
9 -IN9
GNOA 2
A
8 +INB
+ - - +
+INA 3
B
-INA 4
7 GNDB
6 aUTe
5
v, For devices processed In total compliance to MIL-STD-883, add 1883 after part
number. Consult factory for 883 data sheet.
NOTE'
Pin 5 (V-) is connected to case.
t All commercial and industnal temperature range parts are available with burnMln
For ordering information see 1986 Data Book, Section 2.
14-PIN EPOXV DIP
(P-Suffix)
TO-100
(K-Suffix)
14-PIN HERMETIC DIP
(V-Suffix)
GENERAL DESCRIPTION
The PM-119 is adual high-speed voltage comparator designed to
operate from a single +5V supply up to ±15V dual supplies.
Open-collector outputs are provided for logic interface flexibility,
SIMPLIFIED SCHEMATIC (Each Comparator)
r---4r~~------~--~--~--------------~--~~--~----------4r-----OV+
A1
A6
3Sk!!
R2
4kU
3k0
R7
3k0
R3
4kn
~--~-----4r
~
__
~
____________
-{~Q8
Q4
R1.
13kU
+IN
A15
300n
OUTPUT
Q14
Q16
R16
6000
A17
Q17
30
GND
v-
This advance product Information describes a product in development at the time of this printing. Final speCifications may vary. Please contact
local sales office or distributor for final data sheet.
8-54
1/86, Rev. A
--------t~ PM-119/PM-219/PM-319 DUAL COMPARATOR -
ELECTRICAL CHARACTERISTICS at Vs =
ADVANCE INFORMATION
± 15V, ground pin at ground and TA = 25°C, unless otherwise noted.
PM-119/PM-219
PARAMETER
SYMBOL
CONDITIONS
Vos
Rs '" 5kU (Note 1)
los
I.
Input Offset
Voltage
Input Offset
Current
Input BIas
Current
VottageGain
(Collector)
Response TIme
'Vc
t,
PosItIve Supply
Current
PosItIve Supply
Current
NegatIve Supply
Current
PM-319
MIN
TYP
MAX
TYP
MAX
UNITS
07
40
2.0
80
mV
(Nole1)
30
75
80
200
nA
(Note 1)
150
500
250
1000
nA
(Note 2)
MIN
to
V ,N = 100mV Step
Voo =5mV(Note3)
40
V/mV
80
80
ns
43
4.3
mA
40
8
ISY
Vs =+5V,OV
ISY+
Vs= ±15V
8
11.5
8
11.5
mA
ISY-
Vs= ±15V
3
45
3
4.5
mA
NOTES:
1. The offset vottage, offset current, and bIas current gIven are the maxImum values
required to drive the collector output to wIthIn 1V of the supplies with a 7 5kU
II
load. These parameters defIne an error band and take Into account the worst
case effects of voaage gam and Input Impedance.
2. Average of 'V+ and 'V- over a ± 10V output range measured at the emItter
3. The respcnse lime specihed IS for a 100mV Input step wIth a 5mV overdrive and
IS the time reqUired for the slowest edge.
1/86, Rev. A
8-55
-----------------
----------
I»~-139/I»~-139jl/I»~-339jl
QUAD LOW-POWER
VOLTAGE COMPARATORS
Precision MOl1o]ithics Inc.
FEATURES
are offered in a design that features single power supply
operation. The input voltage range includes ground for
convenient single supply operation. The 2mA power supply
current, independent of supply voltage - coupled with the
single supply operation, makes this comparator ideal for low
power applications. Open collector outputs allow maximum
applications flexibility.
• Single or Dual Supply Operation
• Input Voltage Range Includes Ground
• Low Power Consumption (2mW/Comparator)
• Low Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . .. 25nA
• Low Input Olfset Current ....................... ±5nA
• Low Olfset Voltage ............................ ±2mV
• Low Output Saturation Voltage (250m V @ 4mA)
• Logic Outputs Compatible with TTL, DTL, ECL, MOS
and CMOS
• Directly replaces LM139 and LM139A/339A Comparators
PIN CONNECTIONS
ORDERING INFORMATIONt
PACKAGE
+25°C
Vos
(mV)
14-PIN
HERMETIC DIP
±2"
±5"
±2
PM139AY"
PM139Y"
PM339AY
OPERATING
TEMPERATURE
RANGE
LeC
PM139ARC/883
MIL
MIL
COM
14-PIN HERMETIC DIP
(Y-Sufflx)
"For devices processed In total compliance to MIL-STD-883, add 1883 after
part number. Consult factory for 883 data sheet
tAil commercial and industrial temperature range parts are available with
burn-In. For ordering information see 1986 Data Book, Sechon 2.
PM-139ARC/883
LCC PACKAGE
(RC-Suffix)
TYPICAL INTERFACE
GENERAL DESCRIPTION
The PM-139 has four independent voltage comparators, each
with precision DC specifications. Low offset voltage, bias
current, power consumption and output saturation voltage
DRIVING CMOS
50V
SIMPLIFIED SCHEMATIC (ONE COMPARATOR)
10Ok.n
v+
OUTPUT
DRIVING TTL
50V
,..........- i - -......-o-INPUT
I
I
I
,
I
I
~*
~*
I
I
....L
....L..
*SUBSTRATE DIODES
8-56
1/86, Rev. A
---------l(fHD PM-139/PM-139A1PM-339A QUAD LOW-POWER VOLTAGE COMPARATORS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V+ ........................ 36V or ± 18V
Differential Input Voltage. • • • • • • • •• • • • • . • . • • • • • • • • •• 36V
Input Voltage ••.••.•••••••••••••.••••••..• -O.3V to +36V
Power Dissipation Hermetic DIP ••••.•.••.••..••• 500mW
Derate Above 100°C .••...•.••••••.......••••• 10mW/oC
Output Short-Circuit to Ground •••...•...••• Continuous
ELECTRICAL CHARACTERISTICS at V+ =
Input Current (V IN < -O.3V) ........................ 50mA
Operating Temperature Range
PM-339A •••••.•....•.....•.•...•••.•••• O°C to +70°C
PM-139A/139/139ARC ...........•..•. -55°C to +125°C
Storage Temperature Range ..•••..•.•. -65°C to +150°C
Lead Temperature (Soldering, 60 sec) ••••••••••••• 300°C
+5V, TA = 25°C, unless otherwise noted.
PM-339A
PM-139A
PARAMETER
SYMBOL
CONOITIONS
Input Offset Voltage
Vos
I Note 1)
Input Bias Current
18
I'NI+) or I'N(-) with
Oulput in Linear Range
Input Offset Current
los
I'NI+) or I'NI-)
CMVR
(Notes 2, 5, 61
Is
RL = GO on all Comparators
V+=30V
Avo
RL2! 15kO, V+ = 15V
Ito support large
Vo swingl (Note 5)
t,
V'N = TTL Logic Swing,
VREF = I.4V, VRL = 5V,
RL = 5.1kO, (Note 41
Response Time
t,
VRL = 5V, RL = 5.1kO
(Notes 3. 41
Output Sink Current
'SINK
V'N(-I2! IV, V,N(+I = 0,
V0 51.5V
Saturation Voltage
VOL
V'NI-) 2! IV, V,N(+I = 0,
IS , NK 54mA
250
ILEAK
V'N(+) 2! IV, V'NI-I = 0,
Vo= SOV
0.1
Input Common-Mode
Voltage Range
Supply Current
Voltage Gain
Large-Signal
Response Time
Output Leakage
Current
ELECTRICAL CHARACTERISTICS
MIN
TYP
MAX
MIN
TYP
PM-139
MAX
MIN
TYP
MAX
UNITS
mV
25
100
3
25
a
3.5
25
a
0.8
50
25
100
nA
50
3
25
nA
3.5
V
3.5
a
0.8
50
200
6
250
200
50
0.8
mA
200
V/mV
300
300
300
ns
1.3
1.3
1.3
I'S
16
mA
16
6
400
16
6
250
400
250
0.1
400
0.1
mV
nA
at V+ = +5V, -55°C:::; T A :::; +125°C for PM-139/139A and O°C:::; TA:::; +70°C for
PM-339A, unless otherwise noted.
PM-139A
PM-339A
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
(Note 11
Input Offset Current
los
I'N(+) or I'N(-)
100
Input Bias Current
18
I'NI+) OR I'NI-I with
Output in Linear Range
300
Input Common-Mode
Voltage Range
CMVR
I Notes 3, 5)
Saturation Voltage
VOL
V'NI-) 2! IV, V'N(+) = 0,
IS ,NK 54mA
Output Leakage
Current
I LEAK
V'NI+) 2! IV, V'NI-) = 0,
Vo= 30V
Differential Input
Voltage
MIN
TYP
MAX
MIN
TYP
PM-139
MAX
MIN
MAX
UNITS
9
mV
150
100
nA
400
300
nA
V+-2
V
700
mV
4
a
V+-2
700
a
V+-2
700
a
TYP
I'A
36
Keep All V'N's 2! OV
NOTES:
1. Atoutputswitch point, Vo=I.4V, Rs= 00 with V+from 5V,and over the full
input common-mode range 10V to V+ -1.5V).
2. The input common-mode voltageoreitherinput voltage signal should not
be allowed to go negat,ve by more than 0.3V The upper end of the
common-mode voltage range is V+-l.5V, but either or both inputs can go
to +SOV without damage.
3.
36
36
V
The response time specified is for a 100mV input step with 5mV overdrive.
For larger overdrive signals 300ns can be obtained. See characteristics
section.
4. Sample tested.
5. Guaranteed by design.
6 Posrtrve CMVR lim,t equals V+ -1 5V fo, supply voltages other than 5V
8-57
1/86, Rev_ A
II
---------I~ PM-139/PM-139A1PM-339A QUAD LOW-POWER VOLTAGE COMPARATORS
TYPICAL APPLICATIONS
AND GATE
OR GATE
V+
200kn
39kn
3kn
+Q.07SV
1001<0
100kf2
Ao--JYVv-~
Ao--JYVv-~
100k.Q
100ldl
100kn
100kn
l=A+B+C
"0"
OIl"
"0" "1"
TIME DELAY GENERATOR
V+
10kn
15kn
200kn
30kn
v+
o
10kn
to
r-
t3
V03
30kf2
51kn
V+
10Mn
w
----------;~~
o=rto
t2
10kU
__
V02
Ve1
I
V2
51M"!
30kn
v,
v+
10Mn
oT
tt
to
lOkS}
VA'
V
+-r--1
o .--1
to
L-
J c,
10kn
INPUT GATING SIGNAL
S1kn
O.OOl,uF
14
":"
+VIN
8-58
1/86, Rev. A
----------l~ PM-139/PM-139A1PM-339A QUAD LOW-POWER VOLTAGE COMPARATORS
TYPICAL APPLICATIONS
ONE-SHOT MULTIVIBRATOR WITH INPUT LOCK-OUT
V+
n="'
~
15
lMn
0
lMn
100kn
lOMS}
~
15kn
560M2
~
+VIN
:=IEV+
-T
0
~
7
>-----
100k.\1
+
:;/'
to
Va
'1
T;; 03mSEC
10Mn
100pF
-=-
62kn
I
ONE-SHOT MULTIVIBRATOR
240k.l1
-=-
BURN-IN CIRCUIT
V+
GND
GND
(OV)
(OVI
V+l
0-
'0
3.•
kn
1.
kn
13
12
11
~
100pF
o------l H
3.
.......--+---l
~
10
9
8
'«
+VIN
2&=
~~
1
100
kn
+36V
3 .•
kn
"[ ~~''''"
2
3 .•
A58VT062V
lWATT
ONE EACH
PER BOARD
8-59
3
kn
I'
5
•
7
+36V
470kn
l, SOCKETS
~~J~i~NT
MIL STD 8B3, METHOD 1015, CONDITION B
1/86, Rev_ A
II
Table of Contents 1
Ordering Information 2
Product Assurance Program 3
Industry Cross Reference 4
Operational Amplifiers 5
Instrumentation Amplifiers 6
Voltage Followers/Buffers 7
Voltage Comparators 8
Matched Transistors 9
Voltage References 10
Digital-to-Analog Converters 11
Analog-to-Digital Converters 12
Analog Switches/Multiplexers 13
Sample-and-Hold Amplifiers 14
Special Functions 15
Communications Products 16
Package Information 17
Sales Offices, Representatives and Distributors 18
MATCHED
TRANSISTOR ARRAYS
PreClS10n Monolithlcs Inc.
9-3
Introduction
9-3
Definitions
9-4
Parameter Comparison Tables
9-5
MAT-Ol
Matched Monolithic Dual Transistor
9-11
MAT-02
Low-Noise, Matched Dual
Monolithic Transistor
9-23
MAT-04
Matched Monolithic Quad Transistor
9-2
MATCHED
TRANSISTOR ARRAYS
Precision Monolith ics Inc.
INTRODUCTION
Broadband Noise Voltage (enRMS) - The rootmean-square noise voltage referred to the input
over a specified bandwidth at a specified collector
voltage and current.
Monolithic dual and quad transistor arrays
feature inherently close matching of electrical
parameters and very low thermal differentials. In
addition, PMI arrays are specifically designed
for low offset voltage, low offset voltage drift,
low noise, and high gain, specified over a wide
range of collector currents. Monolithic duals are
optimized for amplifier input use and provide the
best possible input stage performance. The dual
and quad transistors are excellent for use in
high-performance audio systems, high-gain
instrumentation amplifiers, and precision current
mirrors.
Both the dual and quad transistors are also
designed for minimal base-to-emitter resistance
which makes log conformity excellent. For an
ideal transistor, the base-to-emitter voltage is
equal to (kT/q) In (Ie/ls). An added term, Ie rSE,
causes departure from this idealized logarithmic
relationship. The MAT-02 and new MAT-04 have
very low rSE over a wide range of collector
current. Circuits for squaring, RMS-to-DC
conversion, and logarithmic amplification can be
accurately implemented through use of these
10w-rSE products. The MAT-04 preliminary data
sheet is shown in the Advanced Products
Section.
Current Gain Match (~hFE) - The difference in
hFE between the transistors at a specified voltage
and current, expressed as a percentage of the
lower of the two hFE'S.
(1 -
hFE1) X 100
hFE2
Excess Emitter Resistance (rSE) - The
effective resistance between the base and
emitter terminals of each transistor.
Noise Voltage (enp-p) - The peak-to-peak noise
voltage referred to the input over a specified
bandwidth at a specified collector voltage and
current.
Noise Voltage Density (en) - The rms noise
voltage referred to the input in a 1Hz band
surrounding a specified frequency, measured
at a specified collector voltage and current.
Offset Current (los) - The difference between
the base currents at a specified collector voltage
and current.
Offset Current Change (~Ios/ ~VCB) - The ratio
of the change in offset current to the change in
collector-base voltage producing it.
The well-defined relationship between VSE and
collector current can also be used for temperature sensing or for generating bandgapreference voltages. The low noise, low offsets,
and high gain combined with a wide operating
range for collector current make these monolithic arrays very useful for a diverse range of
applications.
Offset Voltage (Vos) - The difference between
the base-emitter voltages (VSE1-VSE2) at a
specified collector voltage and current.
DEFINITIONS
Average Offset Current Drift (TClos) - The
ratio of the change in los to the change in temperature producing it.
Average Offset Voltage Drift (TCVos) - The ratio
of the change in Vos to the change in temperature producing it.
Bias Current (Is) - The average of the base
currents at a specified collector voltage and
current.
9-3
II
~
0
f-<
~
V~l:
@
::c
U
~
MATCHED
TRANSISTOR ARRAYS
Precision MOIlolithics Inc.
Parameter Comparison Table (Ie = 10J,LA) for MAT-02
Device
MAT-02A1E""
MAT-02B/F""
LM194
LM394
MAT-01AH
MAT-01GH
LM114A
LM114
LM115A
LM115
AD810"
AD811"
AD812"
AD813"
AD818*
BVCEO
Min
(V)
Vos
Max
(mV)
40
40
40
40
45
45
45
45
60
60
35
45
35
45
20
.05
.15
.05
.15
0.1
0.5
0.5
2.0
0.5
2.0
3.0
1.5
1.0
0.5
1.0
TCVos
Max
(p.V/OC)
hFE
Min
los
Max
(nA)
TClos
Max
(pAloC)
0.3
1
0.3
1
0.5
1.8
2.0
10
2.0
10
15
7.5
5.0
2.5
5.0
400
300
300
200
500
250
500
250
250
250
100
200
400
200
200
0.5
1.3
0.7
2.0
0.6
3.2
2.0
10
2.0
10
2.0
10
2.5
5
10
90
150
N.C.
N.C.
90
150
600
300
300
300
300
" Discontinued
""Temperature range for A-grade and B-grade is -55° C to + 125° C; temperature range for
E-grade and F-grade is -25° C to +85° C.
Parameter Comparison Table (Ie = 10J,LA) for MAT-01 to 2N-Types
Device
MAT-01GH
2N2639
2N2640
2N2642
2N2643
2N2915
2N2915A
2N2916
2N2916A
2N2917
2N2918
2N2919
2N2919A
2N2920
2N2920A
2N2060
2N2060A
2N2060B
BVCEO
Min
(V)
Vos
Max
(mV)
TCVos
Max
(p.V;oC)
hFE
Min
%hFE
Match
Max
los
Max
(nA)
TClos
Max
(pAl°C)
45
45
45
45
45
45
45
45
45
45
45
60
60
60
60
60
60
60
0.5
5.0
10
5.0
10
3.0
2.0
5.0
2.0
10
5.0
3.0
1.5
3.0
1.5
5.0
3.0
1.5
1.8
10
20
10
20
10
5.0
10
5.0
20
20
10
5.0
10
5.0
10
5.0
5.0
250
50
50
100
100
60
60
150
150
60
150
60
60
150
150
25
25
25
8
10
20
10
20
10
15
10
15
20
20
10
10
10
10
10
10
10
3.2
20
40
10
20
17
26
7
10
150
1000
2000
500
375
600
900
N.C.
300
1450
750
600
600
N.C.
300
N.C.
N.C.
N.C.
17
7
17
17
7
7
40
40
40
Notes: 1. TClos Max and los Max calculated from published data.
2. N.C. = Insufficient published data to calculate.
3. All of above are physically interchangeable pin-for-pin with MAT-01 and MAT-02 series.
9·4
MAT-Ol
MATCHED MONOLITHIC
DUAL TRANSISTOR
Precisioll Monolithics Inc.
FEATURES
ABSOLUTE MAXIMUM RATINGS (Note 4)
• Low VOS (VBE Match) ....................... 40~V Typ
100~V Max
• Low TCVos ............................ 0.5~ V,· C Max
• High hFE .................................... 500 Min
• Excellent hFE Linearity from 10nA to 10mA
• Low Noise Voltage ......... 0.23~Vp_p - 0.1 Hz to 10Hz
• High Breakdown ............................ 45V Min
Collector-Base Voltage (BVCBO)
MAT-01AH, GH, N ............................... 45V
Collector-Emitter Voltage (BVCEO)
MAT-01AH, GH, N ............................... 45V
Collector-Collector Voltage (BVcd
MAT-01AH, GH, N ............................... 45V
Emitter-Emitter Voltage (BVEE)
MAT-01AH, GH, N ............................... 45V
Emitter-Base Voltage (BVEBO) (Note 1) ............•... 5V
Collector Current (Ic) ............................. 25mA
Emitter Current (IE) ............................... 25mA
Total Power Dissipation
Case Temperature:540·C (Note 2) .............. 1.BW
Ambient Temperature:5 70·C (Note 3) ......... 500mW
Operating Ambient Temperature. . . . . .. -55· C to +125· C
Operating Junction Temperature ...... -55· C to +150· C
Storage Temperature ................. -65· C to +150· C
Lead Temperature (Soldering, 60 sec) ............. 300· C
DICE Junction Temperature. . . . . . . . . .. -65· C to +150· C
ORDERING INFORMATIONt
TA=2S·C
VosMAX
(mV)
0.1
0.5
PACKAGE
OPERATING
TEMPERATURE
RANGE
MAT01AH'
MAT01GH'
MIL
MIL
• For devices processed in total compliance to MIL-STD-883, add /883 after
part number. Consult factory for 883 data sheet.
t All commercial and industrial temperature range parts are available with
burn-in. For ordering information see 1986 Data Book, Section 2.
NOTES:
1. Application of reverse bias voltages In excess of rating shown can result In
degradation of hFE and hFE matching characteristics. Do not attempt to
measure BVEBO greater than the 5V rating shown.
2. Rating applies to applications using heat sinking to control case temperature. Derate linearly at 16.4mW/' C for case temperatures above 40' C.
3. Rating applies to applications not using heat sinking; device in free air only.
Derate linearly at 6.3mW/' C for ambient temperatures above 70' C.
4. Absolute maximum ratings apply to both DICE and packaged devices.
GENERAL DESCRIPTION
The MAT-Ol is a monolithic dual NPN transistor. An exclusive Silicon Nitride "Triple-Passivation" process provides
excellent stability of critical parameters over both temperature and time. Matching characteristics include offset voltage
of 40~V, temperature drift of 0.15~VI· C, and hFE matching of
0.7%. Very high hFE is provided over a six decade range of
collector current, including an exceptional hFE of 590 at a
collector current of only 10nA. The high gain at low collector
current makes the MAT-Ol ideal for use in low-power,
low-level input stages.
PIN CONNECTIONS
(TOP VIEW)
81
C@."C2
2
E1 3
6
82
TO-7a
(H-Sufflx)
5 E2
NOTE:
Substrate
IS
connected to case.
9-5
1/86, Rev. A
I
~
MAT-01 MATCHED MONOLITHIC DUAL TRANSISTOR
ELECTRICAL CHARACTERISTICS at VCB = 15V,
Ic
= 10J'A, TA = 25
C, unless otherwise noted.
0
MAT-G1AH
SYMBOL
CONDITIONS
Breakdown Voltage
BVeEo
le= IOOI'A
Offset Voltage
Vos
Offset Voltage Stability
First Month
Long-Term
Vos/Time
Offset Current
los
0.1
0.6
0.2
3.2
nA
Bias Current
la
13
20
18
40
nA
45
(Note 1)
(Note 2)
Current Gain
hFE
Current Gain Match
ah FE
le= IOI'A
100nA Sic SlOmA
enp~p
Broadband NOise
Voltage
Noise Voltage
Density
Voltage
MAX
MIN
0.1
2.0
0.2
MAX
UNITS
0.10
0.5
mV
V
2.0
0.2
590
770
840
500
TYP
45
0.04
le= 10nA
le= IOI'A
le= 10mA
Low Frequency Noise
MIN
TYP
MAT-01GH
PARAMETER
250
I'ViMo
430
560
610
0.7
0.8
3.0
1.0
1.2
8.0
O.IHz to 10Hz (Note 3)
0.23
0.4
0.23
0.4
enRMS
1Hz to 10kHz
0.60
en
fo= 10Hz (Note 3)
fo= 100Hz (Note 3)
fo= 1000Hz (Note 3)
7.0
6.1
6.0
9.0
7.6
7.5
7.0
6.1
6.0
9.0
76
7.5
0.5
3.0
0.8
8.0
I'VN
15
3
70
pAN
0.60
%
I'Vp.p
I'VRMS
nV/y'HZ
Offset Voltage Change
avOS/aVeB
OS VeaS 30V
Offset Current Change
aIOS/avCB
OS Vea S30V
Collector-Base
Leakage Current
leBO
VeB = 30V, IE=O
(Note 4)
15
50
25
200
pA
Collector-Emitter
Leakage Current
ICES
VCE = 30V, VaE = 0
(Notes 4, 6)
50
200
90
400
pA
Collector-Collector
Leakage Current
Icc
Vee = 30V, (Note 6)
20
200
30
400
pA
Collector Saturation
Voltage
IB= O.lmA, le= lmA
IB= lmA, Ic= 10mA
0.12
0.8
0.20
0.12
0.8
0.25
VeEISATi
V
Gain-Bandwidth Product
IT
VCE = 10V, Ic = 10mA
450
450
MHz
Output Capacitance
COb
VeB =15V,I E =0
2.8
2.8
pF
Collector-Collector
Capacitance
C cc
Vee=O
8.5
8.5
pF
ELECTRICAL CHARACTERISTICS at
VCB
= 15V, Ic = 10J'A, -55
0
C::;
TA::;
+125
0
C, unless otherwise noted.
MAT-01AH
PARAMETER
SYMBOL
Offset Voltage
Vos
Average Offset
Voltage Drift
TCVos
Offset Current
los
Average Offset
Current Drift
TClos
Bias Current
IB
Current Gain
hFE
Collector-Base
CONDITIONS
MIN
(Note 7)
(NoteS)
167
MAT-01GH
TYP
MAX
TYP
MAX
UNITS
0.06
0.15
0.14
0.70
mV
0.15
0.50
0.35
1.8
I'vrc
0.9
8.0
1.5
15.0
nA
10
90
15
150
pArC
28
60
36
130
nA
400
MIN
77
300
Iceo
TA =125°C, Vee=30V,
IE = 0 (Note 4)
15
80
25
200
nA
Collector-Emitter
Leakage Current
ICES
TA = 125°C, VeE = 30V,
VeE = 0 (Notes 4, 6)
50
300
90
400
nA
Collector-Collector
Leakage Current
Icc
TA = 125°C, Vee = 30V
(Note 6)
30
200
50
400
nA
Leakage Current
9-6
1/86, Rev. A
------------l~ MAT-01 MATCHED MONOLITHIC DUAL TRANSISTOR
DICE CHARACTERISTICS
1.
2.
3.
5.
6.
7.
DIE SIZE 0.035 X 0.025 Inch, 875 sq. mils
(0.89 X 0.64 mm, 0.58 sq. mm)
COLLECTOR (1)
BASE (1)
EMITTER (1)
EMITTER (2)
BASE (2)
COLLECTOR (2)
For additional DICE information refer to
1986 Data Book, Section 2.
WAFER TEST LIMITS at VCB = 15V and Ic = 10!,A, TA = 25°C, unless otherwise noted.
MAT-01N
PARAMETER
SYMBOL
Breakdown Voltage
BVCEO
Offset Voltage
CONDITIONS
LIMITS
UNITS
45
VMIN
Vos
05
mVMAX
Offset Current
los
3.2
nAMAX
Bias Current
Is
40
nAMAX
Cu rrent Gai n
hFE
250
MIN
Current Gain Match
~hFE
8.0
% MAX
Offset Voltage Change
~Vos/~Vcs
Offset Current Change
~los/~Vcs
Collector Saturation Voltage
VCEISATI
0" v cs " 30V
I B =O.lmA, Ic= lmA
8.0
".VN MAX
70
pAN MAX
0.25
VMAX
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to vanations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consun factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS at VCB = 15V and Ic = 10l'A, TA = 25°C, unless otherwise noted.
MAT-01N
TYPICAL
PARAMETER
SYMBOL
CONDITIONS
Average Offset Voltage Drift
TCVos
0.35
".VloC
Average Offset Current Drift
TClos
15
pArC
Collector-Emitter-Leakage Current
ICES
VCE = 30V, VSE = 0
90
pA
Collector-Base-Leakage Current
leBo
VcB =30V,I E=0
25
pA
Gain Bandwidth Product
fT
VCE = 10V, Ie = lOrnA
450
MHz
Offset Voltage Stability
~Vos/T
First Month (Note 1 )
Long-Term (Note 2)
2.0
02
".V/Mo
NOTES:
1. Exclude first hour of operation to allow for stabilization
2 Parameter describes long-term average dnft after first month 01 operation
3 Sample tested.
The collector-base (I CBO ) and collector-emitter (ICES) leakage currents
may be reduced by a factor of two to ten times by connecting the substrate
(package) to a potential which IS lower than either collector voltage.
5.
6.
9-7
UNITS
Guaranteed by los test limits over temperature
Icc and ICES are guaranteed by measurement of I CBO
Vos
Guaranteed by Vos test (TCVos = for Vos '" VSE) T = 298°K for TA
= 250C
T
1/86, Rev. A
-----------I~ MAT·01 MATCHED MONOLITHIC DUAL TRANSISTOR
TYPICAL PERFORMANCE CHARACTERISTICS
OFFSET VOLTAGE
VI TEMPERATURE
BASE-EMITTER VOLTAGE
COLLECTOR CURRENT
OFFSET VOLTAGE VI TIME
200
~
OV.;.vCB';;;30V
VI
10mA
'0
~
'50
;;
3
w
""~
'00
§;
~
V
0
~
-
- -
50
I--
o
o
-50
-26
~
g
w
-2
"
"" .....
z
MAT-OM
~\~~
-
100
126
j-s
'DOpA
-'0
'OpA
160
o
1
2
3
V
l'• 800
8
7
8
9
10 11 12 13
CURRENT GAIN
TEMPERATURE
V
--
~
~'0.0
z
~ 800 I--+--+--;I'-'!--!-=>""!-+--+----I
~
a:
a:
f= :M~;:~;
~
g
2OO.~~
-75
~', = '25'C.
III
/
1.0
II~A I ~~"C
0:
0,1
-50
__'---L~__~-..l__~-.J
-26
50
75
100
0.01
0.01
125
Ilil
I
0.'
'.0
I
10.0
100.0
COLLECTOR CURRENT (rnA)
NOISE VOLTAGE
NOISE CURRENT DENSITY
r---,--...,--,...--,....-.....,
VI
1000 , . . . . - . . . . . , . - - . . , . . - - , - - - , - - . . . . . ,
NOISE CURRENT
DENSITY T A'" 25cC
~
~
.
.i!lili
>
;;
i.
GAIN·BANDWIDTH
COLLECTOR CURRENT
'000
500
g 200
g
MAT-OI,
~
~
"III"
I
60
z
'0
~
/
1/
20
/
Z
z
"./:'
O·'O..., - _....._-,l.O--,.J.OO---'l.k--'.JOk
9·8
VeE'" 10V
/
/
10pA
FREQUENCY (Hz)
TA = 26°C_
J
~
i5
/
/
g:100
'00
z
FREQUENCY (Hz)
lilll
z
o
COLLECTOR CURRENT
Ie" 300J..(A TYPICAL
aoo
700
," '0,'.
I
Ie = 10f,lA TYPICAL
600 80D
\"~'C
S
J
Ie .. 1o~ WORST CASE
400
~
a400 I---A----.;F---i-
1nA 10nA l00nA 'J.lA 10~ 10Cl,uA lmA 10rnA tCOmA
'000
300
w
I
I
o
200
SATURATION VOLTAGE
COLLECTOR CURRENT
800r--+--~--+--4--~~4
TA=25°C VeB'" 15V
200
100
tt
100.0
I
a:
a:
a
10
STRAIGHT Ll
.7
VI
MAT~
i---'""
t. VBE = 0
TA = 125'C
50
50
nA
Icc
Vec = VMAX
TA = 125'C
30
40
nA
Offset Voltage
Collector-Emitter
Leakage Current
Collector-Collector
Leakage Current
80
40
0.08
0.03
90
40
60
275
225
175
150
0.3
"V/'C
15
nA
150
pArC
70
nA
250
200
150
100
CJ)
~
0
~
....
~r-<
Cl
~
NOTES:
V
1. Guaranteed by Vos test (TeVos ~ ~ for Vos
e-
O;
w
"~
+125°C
01
+25°C
111111
001
COLLECTOR CURRENT (rnA)
NOISE VOLTAGE
DENSITY VB FREQUENCY
15c
001
0001
100
10
COLLECTOR CURRENT (rnA)
VB
~
f-
01
COLLECTOR CURRENT (rnA)
IC=lJ.'A-
...... 1-0.
10
Ie .
\O"A~
0
>
~
I'..
'"~
iT11111
10
01
001
0001
COLLECTOR CURRENT (mA)
~
10
8
&:
04
100
I
100
w
Z
in
"e-~
10
SMALL-SIGNAL OUTPUT
CONDUCTANCE VB
COLLECTOR CURRENT
I
10
"
I--'
01
1000
w
Z
~
001
COLLECTOR CURRENT (rnA)
SMALL-SIGNAL INPUT
RESISTANCE VB COLLECTOR
CURRENT
VeE"" 5V
10
01
0001
175
TEMPERATURE (oC)
WI~I+'5U
001
~
~
100
05
IL
10
'1
;:
(EXCLUDES ICBO)
100
01
06
0001
100
0
~
BASE-EMITTER-ONVOLTAGE VB COLLECTOR
CURRENT
I
e-
'00
COLLECTOR CURRENT (mA)
07
L
I
V v,;;=I'IlA
./
/
/
GAIN BANDWIDTH
COLLECTOR CURRENT
1000
V
700
~
1I111
....
600
;;
w
VB
Ic=~mA .,1
800
J 1,I,Iimreitt
".
~
~
z
900
1111
I
800
CURRENT GAIN
vs TEMPERATURE
le= lmA
I
01
01
10
100
lk
FREQUENCY (Hz)
9-15
10k
lOOk
---------I1ffiD
MAT-02 LOW NOISE, MATCHED DUAL MONOLITHIC TRANSISTOR
TYPICAL PERFORMANCE CHARACTERISTICS
TOTAL NOISE VB
COLLECTOR CURRENT
NOISE CURRENT
DENSITY VB FREQUENCY
100
100
_ T A "'2SoC
- V c e - SV
1
~
r---
~
~
1.0
a
IC=10,uA
w
0
z
01
1w
Ic=lmA
~
0
~
le-1OmA-
i
~
80
10
.......
'"
==
f = 1kHz
60
...........
RS
z
=
~
10
if
lOOkn
./
Til
40
"
g
§
100
t--.
20
III
R~ - ~~kn
....
10
100
lk
10k
AS'" lkn
001
0001
lOOk
01
0.01
100
40
/'
~
w
~
";:;z
/'
40
TA '" 25°C
~
1\
;:;"
Z
~
,,""
"
30
w
\.
I
":\:
/
,
TA ='25 0 C
8
13
I
01
30
125
COLLECTOR-BASE
CAPACITANCE VB
REVERSE BIAS VOLTAGE
50
10
100
75
TEMPERATURE (OC)
COLLECTOR-TO-COLLECTOR
CAPACITANCE VB COLLECTOR-TOSUBSTRATE VOLTAGE
COLLECTOR-TO-COLLECTOR
LEAKAGE VB TEMPERATURE
""
-""
50
25
COLLECTOR CURRENT {mAl
FREOUENCY (Hz)
::;
g;
V
01
o
001
01
1
I II
0
~
IC=1JA
IIIII
COLLECTOR-TO-BASE
LEAKAGEwTEMPERATURE
~
20
20
I
\
\
~
10
10
-
-
001
25
50
75
125
100
10
20
30
40
COLLECTOR-TO-COLLECTOR
CAPACITANCE VB
REVERSE BIAS VOLTAGE
10
30
40
50
8'
TA
1.5
20
REVERSE BIAS VOLTAGE (VOL IS)
EMITTER-BASE CAPACITANCE
VB REVERSE BIAS VOLTAGE
25
20
10
50
COLLECTOR-TO-SUBSTRATE VOL TAGE (VOLTS)
TEMPERATURE ( C)
84
=1250C
~
1\
\
w
;:;"
82
80
z
78
13
::
""
r--.....
I
~
76
74
" ."
I
TA=25°C
"-
-
.......
"""" ........
72
70
"""" r.......
68
""""
66
10
20
30
40
01
50
0.2
03
04
0.5
REVERSE BIAS VOLTAGE (VOL TS)
REVERSE BIAS VOLTAGE (VOL IS)
9-16
1/86, Rev. A
---------I1fHD
MAT-02 LOW NOISE, MATCHED DUAL MONOLITHIC TRANSISTOR
LOG CONFORMANCE TEST CIRCUIT
R1
1kn
1V-l0V
RAMP
GENERATOR
R2
10kS1
I
LOG CONFORMANCE TESTING
An error term must be added to this equation to allow for the
bulk resistance (rBE) of the transistor. Errordue to the op amp
input current is limited by use of the OP-15 BIFET-input op
amp. The resulting AMP-01 input is:
The log conformance of the MAT-02 is tested using the
circuit shown above. The circuit employs a dual transdiode
logarithmic converter operating at a fixed ratio of collector
currents that are swept over a 10:1 range. The output of each
transdiode converter is the VBE of the transistor plus an error
term which is the product of the collector current and rBE, the
bulk emitter resistance. The difference of the VBEisamplified
at a gain of x100 by the AMP-01 instrumentation amplifier.
The differential emitter-base voltage (AVBE) consists of a
temperature-dependent DC level plus an AC error voltage
which is the deviation from true log conformity as the collector
currents vary.
IC1
kT
AVBE = - In q
IC2
q
k=
q=
T=
Is =
Ic =
s
(2)
A ramp function which sweeps from 1V to 10V is converted by
the op amps to a collector current ramp through each
transistor. Because IC1 is made equal to 10 IC2' and assuming
TA = 25 0 C, the previous equation becomes:
AVBE = 59mV + 0.9 IC1 rBE (ArBE - 0)
As viewed on an oscilloscope, the change in AV BE for a 10:1
change in Ie is then displayed as shown below:
The output of the transdiode logarithmic converter comes
from the idealized intrinsic transistor equation (for silicon):
Ic
kT
V BE = - In -I where
+ IC1 rBE1 - IC2 rBE2
(1)
_ _ _ _ )
VOUT {
Boltzmann's Constant (1.38062 x 10- 23 J/oK)
Unit Electron Charge (1.60219 x 10- 19 C)
Absolute Temperature, 0 K (= 0 C + 273.2)
Extrapolated Current for VBE-O
Collector Current
-
-
-
-
-
-
-
-
~VO"90IC1'BE
)
59V
COLLECTOR CURRENT
1rnA
9-17
I
10mA
1/86, Rev_ A
_ _ _ _ _ _ _ _--IIfMDMAT-02 LOW NOISE, MATCHED DUAL MONOLITHIC TRANSISTOR
With the oscilloscope AC coupled. the temperature dependent term becomes a DC offset and the trace represents the
deviation from true log conformity. The bulk resistance can
be calculated from the voltage deviation avo and the change
in collector current (9mA):
avo
1
rBE = 9mA x 100
easily accomodated by various offsetting techniques. Protective diodes across each base-to-emitter junction would
normally be needed. but these diodes are built into the
MAT -02. External protection diodesare therefore not needed.
For the circuit shown in Figure 1. the operational amplifiers
make 11 = VX/R1. 12 = Vy/R2. 13 = VZ/R3. and 10 = Vo/Ro.The
output voltage for this one-quadrant. log-antilog multiplier/
divider is ideally:
(3)
This procedure finds rBEfor Side A. Switching R1 and R2 will
provide the rBEfor Side B. Differential rBEis found by making
R1 = R2.
R3 Ro Vx Vy
Vo=---R1 R2
Vz
(Vx. VY. Vz>O)
(4)
If all the resistors (Ro. R1• R2• R3) are made equal. then Vo=
VxVy/Vz. Resistorvalues of 50kO to 100kOare recommended
assuming an input range of 0.1V to +10V.
APPLICATIONS: NONLINEAR FUNCTIONS
MULTIPLIER/DIVIDER CIRCUIT
The excellent log conformity of the MAT -02 over a very wide
range of collector current makes it ideal for use in log-antilog
circuits. Such nonlinear functions as multiplying. dividing.
squaring. and square-rooting are accurately and easily
implemented with a log-antilog circuit using two MAT-02
pairs (see Figure 1). The transistor circuit accepts three input
currents (110 12, and 13) and provides an output current 10
according to 10 = 1112/13. All four currents must be positive in
the log-antilog circuit. but negative input voltages can be
ERROR ANALYSIS
The base-to-emitter voltage of the MAT-02 in its forwardactive operation is:
kT Ic
VBE=-InI s +rBElc.VCB-O
q
(5)
The first term comes from the idealized intrinsic transistor
equation previously discussed (see equation (1)).
Co
R3
Vz
'1~
R1
Vx
-=3.3krt
-'0
RO
R2
Vy
Vo
R3RO VXVy
vo= R,R 2
-=-
--vz
-=-
Figure 1. One-Quadrant Multiplier/Divider
9-18
1/86, Rev. A
---------l~ MAT-02 LOW NOISE, MATCHED DUAL MONOLITHIC TRANSISTOR
approximately 26m V and the error due to an rBEleterm will be
rBElcl26mV. Using an rBE of 0.40 for the MAT-02 and
assuming a collector-current range of up to 200!,A, then a
peak error of 0.3% could be expected for an rBEle error term
when using the MAT-02. Total error is dependent on the
specific application configuration (multiply, divide, square,
etc.) and the required dynamic range. An obvious way to
reduce ICrBE error is to reduce the maximum collector
current, but then op amp offsets and leakage currents
become a limiting factor at low input levels. A design range of
no greater than 10!,A to 1mA is generally recommended for
most nonlinear function circuits.
,-----________---.'1
v,o---~4A~1_----~---_k
3kD.
A powerful technique for reducing error due to lerBEis shown
in Figure 2. A small voltage equal to ICrBE is applied to the
transistor base. For this circuit:
Figure 2. Compensation of Bulk Resistance Error
Extrinsic resistive terms and the Early effect cause departure
from the ideal logarithmic relationship. For small VeB , all of
these effects can be lumped together as a total effective bulk
resistance rBE. The rBEle term causes departure from the
desired logarithmic relationship. The rBEterm for the MAT -02
is less than 0.50and ArBEbetween the two sides is negligible.
(10)
The error from rBEle is cancelled if Rc/R2 is made equal to
rBE/R 1. Since the MAT -02 bulk resistance is approximately
0.390, an Rc of 3.90 and R2 of 10R 1 will give good error
cancellation.
Returning to the multiplier/divider circuit of Figure 1 and
using Equation (4):
In more complex circuits, such as the circuit in Figure 1, it
may be inconvenient to apply a compensation voltage to
each individual base. A better approach is to sum all
compensation to the bases of Ql. The "A" side needs a base
voltage of (Vo/Ro+ Vz/R3) rBEand the "S" side needs a base
voltage of (Vx/Rl + Vy/R2) rBE. Linearity of better than ±0.1 %
is readily achievable with this compensation technique.
VBE1A + VBE2A - VBE2B - VBE1B + (11 + 12- 10 - 13) rBE = 0
If the transistor pairs are held to the same temperature, then:
11 12
kT
ISlA IS2A
kT
-In - - = -In I
I
+ (1 1 + 12 - 10 - 13) rBE
q
13 10
q
51B 52B
(6)
Operational amplifier offsets are another source of error. In
Figure 2, the input offset voltage and input bias current will
cause an error in collector current of (Vos/R1) + lB. A low
offset op amp, such as the OP-07 with less than 75!'V of Vos
and IB of less than ±3nA, is recommended. The OP-22/32, a
programmable micropower op amp, should be considered if
low power consumption or single-supply operation is
needed. The value of frequency-compensating capaCitor
(Co) is dependent on the op amp frequency response and
peak collector current. Typical values for Co range from
30pF to 300pF.
If all the terms on the right-hand side were zero, then we
would have In (1 1 12/1310) equal to zero which would lead
directly to the desired result:
10 =
11 12
1;-' where 11, 12, 13, 10> 0
(7)
Note that this relationship is temperature independent. The
right-hand side of Equation (6) is near zero and the output
current 10 will be approximately 11 12/13' To estimate error,
define I$> as the right-hand side terms of Equation (6):
ISlA IS2A
q
1$>= In I
I
+kT(ll+ 12- lo- 13)rBE
SlB S2B
FOUR-QUADRANT MULTIPLIER
A simplified schematic for a four-quadrant log/antilog multiplier is shown in Figure 3. As with the previously discussed
one-quadrant multiplier, the circuit makes 10 = 11 12113. The
two input currents, 11 and 12, are each offset in the positive
direction. This positive offset is then subtracted out at the
output stage. Assuming ideal op amps, the currents are:
(8)
For the MAT-02, In (ISA/lsB) and lerBE are very small. For
small 1$>, .1$> - 1 + I$> and therefore:
(9)
(11 )
Vx
Vy
VR
Vo
VR
1 0 = - + - + - + - 13=Rl
R1
R2
Ro'
R2
The In (ISA/lsB) terms in I$> cause a fixed gain error of less than
±0.6% from each pair when using the MAT-02, and this gain
error is easily trimmed out by varying Ro. The lerBEterms are
more troublesome because they vary with signal levels and
are multiplied by absolute temperature. At 25° C, kT/q is
From 10= 11 12/13, the output voltage will be:
Ro R2
VO="""R;2
9-19
Vx Vy
VR
(12)
1/86, Rev. A
II
------------I~ MAT·02 LOW NOISE, MATCHED DUAL MONOLITHIC TRANSISTOR
Collector-current range is the key design decision. The
inherently low rSE of the MAT-02 allows the use of a relatively
high collector current. For input scaling of ± 10V fUll-scale
and using a 10V reference, we have a COllector-current range
for I, and 12 of:
( -10
R,
+1Q..)
:5lc:5 (1Q..+~)
R2
R,
R2
MULTIFUNCTION CONVERTER
The multifunction converter circuit provides an accurate
means of squaring, square rooting, and of raising ratios to
arbitrary powers. The excellent log conformity of the MAT-02
allows a wide range of exponents. The general transfer
function is:
(13)
Vo = Vv
Practical values for R, and R2 would range from SOkO to
100kO. Choosing an R, of 82kO and R2 of 62kO provides a
collector-current range of approximately 391-'A to 2831-'A. An
Ro of 108kO will then make the output scale factor 1/10 and
Vo = Vx Vv/10. The output, as well as both inputs, are scaled
for ± 10V fUll-scale.
Vz
Vo= 10 ( 10
)m
(16)
As with the multiplier/divider circuits, assume that the
transistor pairs have excellent matching and are at the same
temperature. The In ISA/lss will then be zero. In the circuit of
Figure 4, the voltage drops across the base-emitter junctions
of 01 provide:
(I, + 12-13-10) rSE+ pVo= 0
The currents are known from the previous discussion, and
the relationship needed is simply:
Ro
(1S)
Vx , Vv, and Vz are input voltages and the exponent "m" has a
practical range of approximatelyO.2 to S. Inputs Vxand Vvare
often taken from a fixed reference voltage. With a REF-01
providing a precision + 10V to both Vx and Vv, the transfer
function would simplify to:
Linear error for this circuit is substantially improved by the
small correction voltage applied to the base of 01 as shown
in Figure 3. Assuming an equal bulk emitter resistance for
each MAT-02 transistor, then the error is nulled if:
Vo=~Vo
(vz)m
Vx
(14)
Iz
Rs
kT
Rs + KRA VA =
In T,;
(17)
q
The output voltage is attenuated by a factor of rseiRo and
applied to the base of 01 to cancel the summation of voltage
drops due to rSEIC terms. This will make In (I, 12/1310) more
nearly zero which will thereby make 10 = I, 12/13 a more
accurate relationship. Linearity of better than 0.1% is readily
achievable with this circuit if the MAT -02 pairs are carefully
kept at the same temperature.
Iz is Vz/R, and Ix is Vx/R,. Similarly, the relationship for 02 is:
Rs
Rs+(1·K)RA
kT
10
In q
Iv
(18)
-::--..:=--:-:-::- VA = -
10 is VoiRo and Iv is Vv/R,. These equations for 01 and 02
can then be combined.
In ~ = In
Rs + KRA
Rs + (1-K)RA
Ix
Iv
.!sL
(19)
+15V
RO=10Bkn
R,=82kn
R2 =62kn
"2
Vx
",
Vy
",
"2
"2
"2
Figure 3. Four-Quadrant Multiplier
9·20
1/86, Rev. A
----------IM
MAT-02 LOW NOISE, MATCHED DUAL MONOLITHIC TRANSISTOR
Substituting in the voltage relationships and simplifying
leads to:
better than 1% are readily achievable with this circuit configuration and can be better than ±0.1% over a limited operating
range.
Vz)m,where
Ro
( Vx
Vo=R';'"Vy
FAST LOGARITHMIC AMPLIFIER
The circuit of Figure 5 is a modification of a standard
logarithmic amplifier configuration. Running the MAT-02 at
2.5mA per side (full-scale) allows a fast response with wide
dynamic range. The ci rcuit has a 7 decade current range. a 5'
decade voltage range. and is capable of 2.5l'sec settling time
to 1% with a 1 to 10V step.
(20)
m = Re+ KRA
Re + (1-K) RA
The factor "K" is a potentiometer position and varies from
zero to 1.0, so "m" ranges from ReI(R A+ Re) to (Re+ RA)/R e.
Practical values are 1250 for Reand 5000 for RA; these values
will provide an adjustment range of 0.2 to 5.0. A value of
100kO is recommended for the R1 resistors assuming a fullscale input range of 10V. As with the one-quadrant multiplier/
divider circuit previously discussed. the Vx. Vy. and Vzinputs
must all be positive.
The output follows the equation:
R3 + R2 kT
VREF
Vo=----In - R2
q
Vin
(21 )
The output is inverted with respect to the input. and is nominally -1 Vldecade using the component values indicated.
The op amps should have the lowest possible input offsets.
The OP-07 is recommended for most applications. although
such programmable micropower op amps as the OP-22 or
OP-32 offer advantages in low-power or single-supply
circuits. The micropower op amps also have very low inputbias-current drift. an important advantage in log/antilog
circuits. External offset nulling may be needed. particularly
for applications requi ring a wide dynamic range. Frequencycompensating capacitors. on the order of 50pF. may be
required for A2 and A3. Amplifier A1 is likely to need a larger
capacitor. typically 0.0047I'F. to assure stability.
Accuracy is limited at the higher input levels by bulk emitter
resistance. but this is much lower for the MAT-02 than for
other transistor pairs. Accuracy at the lower signal levels
primarily depends on the op amp offsets. Accuracies of
LOW-NOISE x1000 AMPLIFIER
The MAT-02 noise voltage is exceptionally low. only
1nVlV"HZ at 10Hz when operated over a collector-current
range of 1 to 4mA. A single-ended x1000 amplifier that takes
advantage of this low MAT-02 noise level isshown in FigureS.
In addition to low noise. the amplifier has very low drift and
high CMRR. An OP-32 programmable low-power op amp is
used for the second stage to obtain good speed with minimal
power consumption. Small-signal bandwidth is 1MHz. slewrate is 2.4V1l's, and total supply current is approximately
2.8mA.
1
RO (Vz m
Vo=-VyRl
Vx
R1=100kn
Ro~100kn
CO -O.0047MF
R A=500n
Rs =125n
VyO-~AA~----------------------~
Figure 4. Multifunction Converter
9-21
1/86, Rev. A
------------J~ MAT-D2 LOW NOISE, MATCHED DUAL MONOLITHIC TRANSISTOR
Transistors 02 and 03 form a 2mA current source
(0.65V/3300 - 2mA). Each collector of 01 operates at 1mAo
The OP-32 inputs are 3V below the positive supply voltage
(RLle - 3V). The OP-32's low input offset current, typically
less than 1nA. and low offset voltage of 1mV cause negligible
error when referred to the amplifier input. Input stage gain is
gmRL. which is approximately 100 when operating at Ie of
1ma with RL of 3kO. Since the OP-32 has a minimum openloop gain of 500.000. total open-loop gain for the composite
amplifier is over 50 million. Even at closed-loop gain of 1000.
the gain error due to finite open-loop gain will be negligible.
The OP-32 features excellent symmetry of slew-rate and
very linear gain. Signal distortion is minimal.
The IS ET• using ±15V supplies and an RSET of 549kO. is
approximately 52p.A which will result in supply current of
784p.A.
Dynamic range of this amplifier is excellent; the OP-32 has an
output voltage swing of ±14V with a ±15V supply.
Input characteristics are outstanding. The MAT-02B/F has
offset voltage of less than 150p.V at 25°C and a maximum
offset drift of 1p.V/oC. NUlling the offset will further reduce
offset drift. This can be accomplished by slightly unbalancing
the collector load resistors. This adjustment will reduce the
drift to less than 0.1p.V/oC.
Input bias current is relatively low due to the high current
gain of the MAT-02. The minimum f3 of 400 at 1mA for the
MAT-02B/F implies an input bias current of approximately
2.5p.A. This circuit should be used with signals having
relatively low source impedance. A high source impedance
will degrade offset and noise performance.
Frequency compensation is very easy with this circuit; just
vary the set-resistor Rs for the desired frequency response.
Gain-bandwidth of the OP-32 varies directly with the supply
current. A set resistor of 549kO was found to provide the best
step response for this circuit. The resultant supply current is
found from:
RSET
(V+) - (V-) - (2VBE) I - 15 I
.SYSET
ISET
This circuit configuration provides exceptionally low input
noise voltage and low drift. Noise can be reduced even
further by raising the COllector currents from 1mA to 3mA.
but power consumption is then increased.
(22)
+'5V
o------""'tn;"'"T'M,,---,
4kn
V,N
(0 to lOV)
".
20kn
V ,N
"3
75kn
+15V
V REF
'OV
"2
4kn
..on
",
R2" TEL LABS Q81E (+0 35%/-C)
-15V
-15V
+15V
Figure 5. FaIt Logarithmic Amplifier
Figure 6. Low-Noise, Single-Ended X1000 Amplifier
9-22
1/86, Rev. A
MAT-04
MATCHED MONOLITHIC
QUAD TRANSISTOR
Precision Monolithics Inc.
PRELIMINARY
FEATURES
•
•
•
•
•
•
PIN CONNECTIONS
Low Offset Voltage ..................... 150fLV Max
High Current Gain .........••..•••........ 400 Min
Excellent Current Gain Match ...•.....•.... 2% Max
Low Noise Voltage at 100Hz, 1mA .•..• 2.5nV/vHzMax
Excellent Log Conformance ....•... rBE
O.SO Max
Matching Guaranteed for All Transistors
=
14-PIN HERMETIC DIP
(V-Suffix)
14-PIN EPOXV DIP
(P-Suffix)
ORDERING INFORMATIONt
PACKAGE
TA = 25°C
VosMAX
lfN)
HERMETIC
DIP
14-PIN
150fLV
150fLV
300fLV
300fLV
MAT04AY'
MAT04EY
MAT04BY'
MAT04FY
EPOXY"
DIP
14-PIN
OPERATING
TEMPERATURE
RANGE
MIL
IND
MIL
IND
MAT04EP
MAT04FP
ABSOLUTE MAXIMUM RATINGS (Note 1)
Collector-Base Voltage (BVCBO) . . . . . . . . . . . . . . . . . . . 40V
Collector-Emitter Voltage (BVCEO ) . . . . . . . . . . . . . . . . .. 40V
Collector-Collector Voltage (BVcc) ................. 40V
Emitter-Emitter Voltage (BVEE ) . . . . . . . . . . . . . . . . . . . . 40V
Collector Current .............................. 30mA
Emitter Current ............................... 30mA
Substrate (Pin-4 to Pin-ll) Current ................ 30mA
Total Power Dissipation (Note 2) ................ 500mW
Operating Temperature Range
MAT-04AY, BY ..................... -55 D C to + 125D C
MAT-04EY, FY, EP, FP ............... -25 D C to +85 D C
Storage Temperature
Y Package ........................ -65 D C to + 150D C
P Package
.. -65 D C to + 125D C
Lead Temperature (Soldering, 60 sec) .............. 300D C
• For devices processed In total compliance to MIL-STD-883, add 1883 after part
number. Consult factory for 883 data sheet.
•• Epoxy packaged devices available in 1st Quarter, 1986.
t All commercial and industnal temperature range parts are available with burnMln.
For ordenng Information see 1986 Data Book, Section 2
GENERAL DESCRIPTION
The MAT -04 is a quad monolithic NPN transistor that offers
excellent parametric matching for precision amplifier and nonlinear circuit applications. Performance characteristics of the
MAT-04 include high gain (400 minimum) over a wide range
of collector current, low noise (2.5nV/vHz maximum at 100Hz,
Ic = 1mA) and excellent logarithmic conformance. The MAT-04
also features a low offset voltage of 150fLV and tight current gain
matching, to within 2%. Each transistor of the MAT-04 is
individually tested to data sheet specifications. For matching
parameters (offset voltage, input offset current, and gain match),
each of the dual transistor combinations are verified to meet
stated limits. Device performance is guaranteed at 25 C and over
the industrial and military temperature ranges.
NOTES:
Absolute maximum ratings apply to both DICE and packaged devices
The table below lists maximum ambient temperature ratings and derating
factors
D
PACKAGETYPE
The long-term stability of matching parameters is guaranteed by
the protection diodes across the base-emitter junction of each
transistor. These diodes prevent degradation of beta and matching characteristics due to reverse bias base-emitter current.
14-Pln
Hermetic DIP (Y)
14-Pln
Epoxy DIP (P)
The superior logarithmic conformance and accurate matching
characteristics of the MAT -04 makes it an excellent choice for use
in log and antilog circuits. The MAT-04 is an ideal choice in
applications where low noise and high gain are required.
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
100·C
10mW/·C
42°C
6mW/·C
This preliminary product Information Is based on testing of a limited number of devices. Final specifications may vary. Please contact local sales
office or distributor for final data sheet.
9-23
1/86, Rev. A
II
~
MAT-04 MATCHED MONOLITHIC QUAD TRANSISTOR - PRELIMINARY
ELECTRICAL CHARACTERISTICS at TA = 25°C unless otherwise noted. Each transistor is individually tested. For matching
parameters (Vos. los. Ilh FE ) each dual transistor combination is verified to meet stated limits. All tests made at endpoints unless otherwise noted.
MAT-04A/E
PARAMETER
Current Gain
Current Gain
Match
Offset Voltage
SYMBOL
CONDITIONS
MIN
TYP
hFe
10",Asle S 1mA
OVsVee s30V
(Note 1)
400
800
ahFe
Ie = 100",A
OVsVee s 30V
(Note 2)
Vos
aVos/ale
Offset Voltage
Changevs
Collector Current
Offset Voltage
Bulk Emitter Resistance
ree
Input Bias Current
Ie
Input Offset Current
los
Breakdown Voltage
300
",V
10",Asle s1mA
Vee=OV
5
25
10
50
",V
50
100
100
200
",V
0.4
0.6
0.4
0.6
!l
125
250
165
330
nA
0.6
5
13
nA
OVsVee s 30V
10",As Ie s 1mA
Vee=OV
le= 100",A
OVsVee s 30V
le= 100",A
Vee=OV
Collector-Base
Leakage Current
leBO
Vee = 40V
5
NOIse Voltage
DenSity
en
Vee=OV
le=1mA
(Note 3)
Gain Bandwidth
Product
fT
Output Capacitance
C OBO
Vee = 15V
f=1MHz
le=O
Input CapaCitance
C eeo
Vee=OV
f=1MHz
le=O
2
1.8
1.8
fo= 10Hz
fo= 100Hz
fo=1kHz
le=1mA
Vee = 10V
V
40
40
0.03
Sample tested.
%
100
Vee(SAT)
3
4
150
le= 10",A
10~,
800
UNITS
50
le= 100",A
le=1mA
Current gain match IS defined as:
300
MAX
10",Asle s1mA
OVS Vee s30V
BVeeo
2.
TYP
2
Collector Saturation
Voltage
NOTES:
Current gam measured at Ie =
MIN
0.5
1Of.loA:s;:lc:S;1mA
avos/avee
Change vs Vee
MAT-04B/F
MAX
0.06
0.03
0.06
5
3
2.5
2.5
2
1.8
1.8
V
pA
4
3
3
nV/$z
300
300
MHz
10
10
pF
40
40
pF
100j.LA and 1mA.
100 (alB) (hFe min)
ah Fe =
Ie
9-24
1/86, Rev. A
-----------I~ MAT-04 MATCHED MONOLITHIC QUAD TRANSISTOR -
ELECTRICAL CHARACTERISTICS
at
-25°C
:5 TA :5
85°C
PRELIMINARY
unless otherwise noted. Each transistor is individually tested. For
matching parameters (Vos. los) each dual transistor combination is verified to meet stated limits. All tests made at endpoints unless
otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
MIN
Current Gain
hFE
10.,As Ics 1mA
OVSVcB s 30V
(Note 1)
225
Offset Voltage
Vos
10.,As Ics 1mA
OVsVcB s30V
Average Offset
VoltageDnft
TCVos
VCB~OV
Input Bias Current
IB
Input Offset Current
los
MAT-04E
TYP
MAX
625
60
MIN
200
210
MAT-04F
TYP
MAX
UNITS
500
120
420
!'-V
0.4
2
!,-V/'C
445
200
500
nA
20
8
40
nA
Ic ~ tOO!,-A
0.2
(Note 2)
Average Offset
Current Drift
TClos
Ic ~ 100!,-A
oVsVcB s 30V
Ic~
160
100!,-A
VCB~OV
Ic ~ 100!,-A
Breakdown Voltage
BVCEO
Ic~
Collector-Base
Leakage Current
ICBO
VCB~40V
Collector-Emitter
Leakage Current
ICES
VCE~40V
Collector-Substrate
Leakage Current
Ics
Vcs~40V
ELECTRICAL CHARACTERISTICS
at
10!,-A
-55°C
:5 TA :5
100
50
VCB~OV
40
pA/'C
40
0.5
V
05
nA
nA
0.7
125°C
07
nA
unless otherwise noted. Each transistor is individually tested. For
matching parameters (VOS. los) each dual transistor combination is verified to meet stated limits. All tests made at endpoints unless
otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Current Gain
hFE
10.,As Ic s 1mA
OV s VcB :s30V
(Note 1)
Offset Voltage
Vos
TCVos
Input Bias Current
IB
Input Offset Current
los
Average Offset
Current Drift
MAT-04B
MIN
TYP
MAX
175
lOjJ-As les 1mA
TClos
UNITS
475
70
125
250
425
140
500
!'-V
02
0.4
2
!,-V/'C
210
570
235
800
nA
6
30
12
60
nA
100!,-A
VCB~OV
Ic ~ 100!,-A
OV
ICBO
VCB~4OV
Collector-Emitter
Leakage Current
ICES
VCE~40V
Collector-Substrate
Leakage Current
Ics
VCS~
100
50
VCB~
Ic~
10!,-A
40
40
pA/'C
V
5
nA
100
100
nA
7
7
nA
40V
NOTES:
1. Current gain measured at Ic ~ 10!,-A, 100!,-A and 1mAo
2. Guaranteed by Vos test (TCVos ,,; Vos/T for Vos < < VBE ) T ~ 298'K for
TA ~ 25'C.
1/86, Rev. A
9-25
--------
::r::
U
100!,-A
OVsVcB s30V
Ic~
BVCEO
~E-<
~
VCB~OV
Breakdown Voltage
~
.....
Cl
100!,-A
Collector-Base
Leakage Current
~
0
(Note 2)
Ic~
V)
V)
OVsVcB s 30V
Ic~
Average Offset
Voltage Drift
MAT-04A
MIN
TYP
MAX
II
----
--------
~
----------1~ MAT-04 MATCHED MONOLITHIC QUAD TRANSISTOR -
PRELIMINARY
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
DIE SIZE 0.059 x 0.059 inch, 3481 sq. mils
(1.50 x 1.50 mm, 2.25 sq. mm)
Q1 COLLECTOR
Q1 BASE
Q1 EMITTER
SUBSTRATE
Q2EMITTER
Q2BASE
Q2 COLLECTOR
Q3 COLLECTOR
Q3BASE
Q3EMITTER
SUBSTRATE
Q4EMITTER
Q4BASE
Q4 COLLECTOR
For additional DICE information refer to
1986 Data Book, Section 2.
WAFER TEST LIMITS at TA = 25°C unless otherwise noted. Each transistor is individually tested. For matching parameters (Vas,
los, t.h FE ) each dual transistor combination is verified to meet stated limits. All tests made at endpoints unless otherwise noted.
MAT-04N
PARAMETER
Current Gain
Current Gain Match
Offset Voltage
SYMBOL
hFE
AhFE
Vos
Offset Voltage
Changevs
AVos/Alc
Collector Current
Offset Voltage
Change vs VCB
Bulk Emitter Resistance
AVoS/AVCB
Ic~ 100"A
OV <; VCB <; 30V
Ic ~ 100"A, VCB ~ OV
10,.,..A.::.;l c .:s::1mA
OV <; VCB <; 30V
10,.,..As les 1mA
VCB ~ OV
10"A <; Ic <; 1rnA
OV" VCB <; 30V
1O/-1A51cs 1mA
rBE
Collector Saturation
Voltage
CONDITIONS
VCE(SAT)
Input Bias Current
IB
Input Offset Current
los
Breakdown Voltage
BVCEO
VCB~OV
IB~ 100"A
Ic~lrnA
Ic ~ 100"A
OV=:::;Vcs ::s:30V
Ic~ 100"A
VCB~ OV
Ic~ 10"A
LIMITS
UNITS
300
MIN
4
%MAX
300
"V MAX
50
"V MAX
200
"V MAX
0.6
flMAX
0.06
VMAX
330
nAMAX
13
nAMAX
40
VMIN
NOTE:
Electrical tests are performed at wafer probe to the limits shown Due to vanatlons in assembly methods and normal Yield loss, Yield after packaging IS not guaranteed for
standard product dice. Consult factory to negotiate based on dice lot quahflcatlon through sample lot assembly and testing
9-26
1/86, Rev. A
----------l~ MAT-04 MATCHED MONOLITHIC QUAD TRANSISTOR -
PRELIMINARY
TYPICAL PERFORMANCE CHARACTERISTICS
CURRENT GAIN
vs COLLECTOR CURRENT
1200
2000
+125oclll
~
1100
GAIN BANDWIDTH vs
COLLECTOR CURRENT
CURRENT GAIN
vs TEMPERATURE
1800
VCB=3o/
11111
1000
1600
vc~ ~'ci~'
900
800
II
700
+d5.hl
!
1400
~
1200
a:
:::)
500
"
500
-5r1
400
10f!.
100jJ.
1m
/
800
/
600
400
10m
COLLECTOR CURRENT (A)
BASE-EMITTER-ON-VOLTAGE
vs COLLECTOR CURRENT
0.65
s
~
m
0.55
a:
~
!
.
~
-25
25
75
125
"iii
~I
lOlL
1001'-
1m
10m
COLLECTOR CURRENT (A)
SATURATION VOLTAGE vs
COLLECTOR CURRENT
100f,!.
1m
10m
100m
SMALL SIGNAL OUTPUT
CONDUCTANCE vs
COLLECTOR CURRENT
"
1M
,
.;!;
,
1lz
~
1'.
O~
,
"
100fl.
V
01
I
2
II
10f.l
v
0
"
lOOk
I
10
"
10k
1f.l
10f!.
SMALL SIGNAL INPUT
RESISTANCE (hie) VS
COLLECTOR CURRENT
1
0.35
I
1f.l
COLLECTOR CURRENT (A)
-'
040
01
175
TEMPERATURE (Oe)
2l
t/
0.45
V
Ie
-'
~
... V
....... V
100
i
/
0 SO
V
10M
~
/
en
le= 1rnA
Vcs=ov"""
~
0.60
I
, /V
200
-75
300
"
/
V"
"i i 1000
a:
I
1/
V
001
1m
,
11-'
10f.!.
100j.l
1m
COLLECTOR CURRENT (A)
COLLECTOR CURRENT (A)
NOISE VOLTAGE DENSITY
vs FREQUENCY
NOISE VOLTAGE DENSITY
vs COLLECTOR CURRENT
10
'-'0HZ
"- r--...
I
100Hz
.........
+125°C
r--
.-""
+ 25°C
-55·C..,J,.
1
I
10m
10,
100j.L
1m
COLLECTOR CURRENT (A)
10m
0.1 L-_L-_L._L._.J...._.J....---l
100m
10
100
1k
10k
lOOk
FREQUENCY (Hz)
9-27
o
o
3m
6m
9m
12m
COLLECTOR CURAENT (A)
1/86, Rev. A
----------1~ MAT-04 MATCHED MONOLITHIC QUAD TRANSISTOR -
PRELIMINARY
TYPICAL PERFORMANCE CHARACTERISTICS
COLLECTOR-TO-BASE
CAPACITANCE VB COLLECTORTO-BASE VOLTAGE
TOTAL NOISE VB
COLLECTOR CURRENT
200
160
r~1
As
20
! 1Jo~h
",,'
~
w
~
..
50
l'....1'-
~ 120
40
~~
o
'"
-
10f.(,
Rs
As
\
-
80
;!
~
COLLECTOR-TO-SUBSTRATE
CAPACITANCE VB COLLECTORTO-SUBSTRATE VOLTAGE
\
........
1'--0..
= 10kU
1,Lll
o
1m
100f.l
COLLECTOR CURRENT (AI
o
10
15
20
25
COLLECTOR-TO-BASE VOLTAGE (VOLTS)
APPLICATION NOTES
30
o
o
ro
~
~
~
COLLECTOA· TO·SUBSTAATE VOLTAGE (VOLTS)
FIGURE 2: Current Mirror, lOUT = 2 (IREF)
It is recommended that one of the substrate pins (Pins 4 and 11)
be tied to the most negative circuit potential to minimize coupling
between devices. Pins 4 and 11 are internally connected.
lOUT
Q1
APPLICATIONS
CURRENT SOURCES
The MAT-04 can be used to implement a variety of high impedance current mirrors as shown in Figures 1,2, and 3. These current mirrors can be used as biasing elements and load devices for
amplifier stages.
Q4
V-
FIGURE 1: Unity Gain Current Mirror, lOUT = IREF
lOUT
FIGURE 3: Current Mirror, lOUT = 112 (lREF)
02
lOUT
Q1
04
Q4
V-
V-
The unity-gain current mirror of Figure 1, using a MAT-04AY, has
an accuracy of better than 1% and an output impedance of over
100MO at 100f1A. Figures 2 and 3 show modified current mirrors
designed for a current gain of two, and one-half respectively. The
accuracy of these mirrors is reduced from that of the unity-gain
source due to base current errors but is still better than 2%.
Figure 4 is a temperature independent current sink that has an
accuracy of better than 1% over the military temperature range at
an output current of 100f1A to 1mA. The Schottky diode acts as a
clamp to insure correct circuit start - up at power on. The resistors
used in this circuit should be 1% metal-film type.
9-28
1/86, Rev. A
---------I~ MAT-04 MATCHED MONOLITHIC QUAD TRANSISTOR -
PRELIMINARY
FIGURE 4: Temperature Independent Current Sink, lOUT = 10V/Rn
+15V
lOUT
lOUT
lOUT
-----,
100pF
I
14
MAT.04AY
12
I
I
I
_ _ _ _ _ --.J
R
R
-15V
NONLINEAR FUNCTIONS
An application where precision matched-transistors are a powerful tool is in the generation of nonlinear functions. These circuits
are based on the transistor's logarithmic property which takes the
following idealized form:
This circuit uses two MAT-04AYs and maintains an accuracy of
better than 0.5% over an input range of 10mV to 10V. The layout
of the MAT-04s reduces errors due to matching and temperature
differences between the two precision quad matched-transistors.
Op amps A 1 and A2 translate the input voltages into logarithmic
valued currents (IA and IB in Figure 5) that flow through transistor
0 3 and Os. These currents are summed by transistor 0 4
(10 = IA + IB = ,jI,2 + 122) which feeds the current-to-voltage
Ie
kT
VBE= - I n q
Is
ro,~rt" ron"";"
The MAT-04, with its excellent logarithmic conformance, maintains this idealized function over many decades of collector current. This, in addition to the stringent parametric matching of the
MAT-04, enables the implementation of extremely accurate logl
antilog circuits.
of ""
~p A3. To m.""," -"'Y, 1%
metal-film resistors should be used.
~
0
f-<
;:a
~
~
@
:r:
u
The circuit of Figure 5 is a vector summer that adds and subtracts
logged inputs to generate the following transfer function:
VOUT =
II
~
~ ,jVA2 + VB2
9-29
1/86, Rev. A
---------tlfMD
MAT-04 MATCHED MONOLITHIC QUAD TRANSISTOR - PRELIMINARY
FIGURE 5: Vector Summer
C3
.OOpF
A
233kH
~~~-------------------oyOOT
I-----;;A:;:-~
L _____ J
L __ ~ ___ ,
...---+1-ie•
/
I
8
I
C2
L ________ .....l
~
MAT-04
10
I
I
I
~--+--+I~~
A,No---J\I\_---<~=-I
33kO
L __________
LOW NOISE, HIGH SPEED INSTRUMENTATION AMPLIFIER
The circuit of Figure 6 is a very low noise, high speed amplifier,
ideal for use in precision transducer and professional audio applications. The performance of the amplifier is summarized in
Table I. Figure 7 shows the input referred spot noise over the
0-25kHz bandwidth to be flat at 1.2nVI JHz: Figure 8 highlights
the low llf noise corner at 2Hz.
(
R10R11 )
R10 + R11
R3
F---.JV\/'v--OB'N
33kn
~
TABLE I: Instrumentation Amplifier Characteristics
The circuit uses a high speed opamp, the OP-17, preceded by an
input amplifier. This consists of a precision dual matched-transistor, the MAT-02, and a feedback V-to-I converter, the MAT-04.
The arrangement of the MAT-04 is known as a "linearized cross
quad" which performs the voltage-to-current conversion. The
OP-17 acts as an overall nulling amplifier to complete the feedback loop. Resistors Rl, R2, and R3, R4 form voltage dividers
that attenuate the output voltage swing since the "cross quad" arrangement has a limited input range. Biasing for the input stage is
set by zener diode Zl. At low currents the effective zener voltage
is about 3.3V due to the soft knee characteristic of the zener
diode. This results in a bias current of 5301lA per side forthe input
stage. The gain equation for this amplifier is:
VOUT
~
r
I
I
I
~~w~+I--~--~
v+
R.
I
.oooPFI
L _________________ ________
----------,
--;-,?
Q6'3"<9H
r---~--~
I
l'OOOpF
/r--l
v-
L~~---l
Input Noise
Voltage Density
G= 1000
G=100
G=10
Bandwidth
G=500
G=100
G=10
Slew Rate
1.2nV/v'HZ
3.6nV/v'HZ
30nVlv'HZ
400kHz
1MHz
1.2MHz
4OV/".s
Common-Mode
Rejection
G= 1000
130dB
Distortion
G=100
f = 20Hz to 20kHz
0.03%
Settling Time
G=1000
Power Consumption
10".s
350mW
(R4+R3)
R3
----=-=------=.-=---=------'~
Y,N
RG
and for the values shown in Figure 6 this equation becomes:
VOUT = 33000
Y,N
RG
9-30
1/86, Rev_ A
---------I~ MAT-04 MATCHED MONOLITHIC QUAD TRANSISTOR -
PRELIMINARY
FIGURE 6: Low Noise, High Speed Instrumentation Amplifier
r---------------~----------------------t_---------------------------o+1SV
R.
RS
68kn
6.8kn
C1
R7
500pF
1.Sk!l
:>"--.....---oVOUT
-15V
+IN
R4
10kH
Z1
3.9V
IN748A
RG = 33k!l
RG = 33kn
RG = 330n
RG = 33n
GAIN
GAIN
GAIN
GAIN
=
=
=
=
1
10
100
1000
R10
R.
39kn
~----~~----------
____
~
__________________________________________________-o_1SV
FIGURE 7: Spot Noise of the Instrumentation Amplifier from
0-25kHz at a Gain of 1000
FIGURE 8: Low Frequency Noise Spectrum Showing Low 2Hz
Noise Corner. Gain = 1000.
NORMALIZED VERTICAL AXIS = 2.6nV/-vHZ/DIVISION
REFERENCED TO INPUT.
HORIZONTAL AXIS == 0 TO 25kHz.
HORIZONTAL AXIS = 0 TO 5Hz
9-31
1/86, Rev. A
II
---------I~ MAT-04 MATCHED MONOLITHIC QUAD TRANSISTOR -
PRELIMINARY
FIGURE 9: Voltage-Controlled Attenuator
r-----~------------------------~----~----------------------ov+
R3
R4
3DkO
aDkO
R7
30k!!
R6
30kn
I-
R8
30kn
v+
VOUT
MAT·04
I
I
C2
~ 100,F
R13
R14
4.7kfl
330n
V CONTROL
v+
Rl0
22kO
Rll
10kO
2N2222
Q5
R2
R5
30kU
3Dkn
~----------------------------+-------------------~----o~
VOLTAGE-CONTROLLED ATTENUATOR
The voltage-controlled attenuator (VCA) of Figure 9, widely used
in professional audio circles, can easily be implemented using a
MAT-04. The excellent matching characteristics of the MAT-04
enables the VCA to have a distortion level of under 0.03% over a
wide range of control voltages. The VCA accepts a 3V RMS input
and easily handles the full 20Hz-20kHz audio bandwidth as
shown in Figure 10. Noise level for the VCA is more than 110dB
below maximum output.
The ideal transfer function for the voltage-controlled attenuator is:
VourlVlN =
1 + exp
Where k
T
Boltzmann constant 1.38 x 10-23 J/oK
temperature in OK
electronic charge = 1.602 x 10-19C
q
(
(-V control)
(2
R14
) / ( kT ) )
R13 + R14
q
From the transfer function it can be seen that the maximum gain
of the circuit is 2 (6dB).
In the voltage-controlled attenuator, the input signal modulates
the stage current of each differential pair. Op amps A2 and A3 in
conjunction with transistors 05 and 06 form voltage-to-current
converters that transform a single input voltage into differential
currents which form the stage currents of each differential pair.
The control voltage shifts the current between each side of the
two differential pairs, regulating the signal level reaching the output stage which consists of op amp A 1. Figure 11 shows the increase in signal attenuation as the control voltage becomes more
negative.
To insure best performance, resistors R2 through R7 should be
1% metal film resistors. Since capacitor C2 can see small
amounts of reverse bias when the control voltage is positive, it
may be prudent to use a nonpolarized tantalum capacitor.
9-32
1/86, Rev. A
----------1~ MAT-04 MATCHED MONOLITHIC QUAD TRANSISTOR -
PRELIMINARY
FIGURE 11: Voltage-Controlled Attenuator,
Attenuation vs Control Voltage
FIGURE 10: Voltage-Controlled Attenuator,
Attenuation vs Frequency
10
)CU~l~L Joll
/'
-10
!
-5
,IV
~ -20
/
iii
-10
i
V CONTROL
-15
~
= -1V
-20
10
-30
"IV
-40
-50
-25
100
,.
---
/
-60
10.
-3
100k
FREQUENCY (Hz)
-2
-1
CONTROL VOLTAGE (VOLTS)
II
9-33
1/86, Rev. A
Table of Contents 1
Ordering Information 2
Product Assurance Program 3
Industry Cross Reference 4
Operational Amplifiers 5
Instrumentation Amplifiers 6
Voltage Followers/Buffers 7
Voltage Comparators 8
Matched Transistors 9
Voltage References 10
Digital-to-Analog Converters 11
Analog-to-Digital Converters 12
Analog Switches/Multiplexers 13
Sample-and -Hold Amplifiers 14
Special Functions 15
Communications Products 16
Package Information 17
Sales Offices, Representatives and Distributors 18
VOLTAGE
REFERENCES
PrecisioJl MOllolithics Inc.
10-3
Introduction
10-3
Definitions
10-4
REF-Ol
+ lOV Precision Voltage Reference
10-11
REF-02
+ 5V Precision Voltage
Reference/Temperature Transducer
10-19
REF-03
+2.5V Precision Voltage Reference
10-21
REF-OS
+ 5V Precision Voltage Reference
10-22 REF-lO
+ lOV Precision Voltage Reference
10-2
VOLTAGE
REFERENCES
Precision MOlloilthlcs Inc
INTRODUCTION
Voltage references provide a constant output
voltage irrespective of changes in input voltage,
output current, or temperature. References are
needed in such diverse equipment as power
supplies, panel meters, calibration standards,
precision current sources, data conversion systems, and control set-point circuits.
Line regulation, load regulation (output impedance), and temperature coefficient specifications indicate how close a reference will be to an
ideal voltage source. Line regulation specifies
reference-output-voltage vs. input-voltage
changes. Output voltage changes due to load
current variations are reflected by load regulation specifications. Temperature coefficient
specifications indicate output voltage variation
over temperature.
PMI references use the bandgap principle which
sums voltages with negative and positive
temperature coefficients to yield a stable output
voltage over temperature. A transistor baseemitter-junction voltage (VBE) exhibits a negative temperature coefficient. Two transistors
operating with unequal current densities will
have different VBES and the difference, ~VBE,
exhibits a positive temperature coefficient.
When ~VBE is amplified and added to VBE, a
near-zero temperature coefficient results if the
sum equals 1.23V. The 1.23V level is then amplified to provide stable output voltages of +S.OOV
or + 10.00V. The bandgap technique has the
advantages of low power consumption, low noise,
and excellent long-term stability.
PMl's zener-zapping technique allows for trimming of the ~VBE amplification factor to ensure
low output voltage temperature coefficients.
Additional zapping trims the output's absolute
value to within specified limits.
The REF-01 and REF-02 are stable + 10.00V and
+S.OOV monolithic bandgap voltage references.
Output voltages are adjustable with small effect
on output-voltage temperature coefficients. The
REF-02 provides an additional output voltage
that has a linear temperature dependence.
The REF-OS and REF-10 are premium versions
of the REF-01 and REF-02 that have guaranteed
long-term stability and MIL-STO-883 process-
ing. Extensive testing over a long period of time,
combined with tight control of processing, has
enabled PMI to specify limits on output change
with time.
DEFINITIONS
Line Regulation - The ratio of the change in
output voltage to the change in input (line) voltage producing it. It includes the effects of
self-heating.
Load Regulation - The ratio of the change in
output voltage to the change in load current. It
includes the effects of self-heating.
Output Change With Temperature (~VOT) - The
absolute difference between the maximum output voltage and the minimum output voltage
over the specified temperature range expressed
as a percentage of the typical output voltage.
~VOT = IVMAX- VMINlx 100
Vo (Typical)
Output Temperature Coefficient (TCVo) - The
ratio of output change with temperature variation to the specified temperature range
expressed in ppm/o C. For example, TCVo is
defined as ~VOT divided by the temperature
range; i.e.,
TCV (O°C to +700C) = ~VOT(O°C to +70°C)
o
700C
and TCVo(-SSOC to +12S0C)
~VOT(-SSOC to +12S0C)
180°C
Output Turn-On Settling Time (tON) - The time
required for the output voltage to reach its final
value within a specified error band after application of VIN.
Output Voltage Noise (enp_p) - The peak-topeak output noise voltage within a specified frequency band.
Quiescent Supply Current (ISY) - The current
required from the supply to operate the device
with no load.
10-3
- - -- .. --- - - - -
=
I
~
S:2
A
-
S2
I
REF-Ol
+lOV PRECISION
VOLTAGE REFERENCE
Prcci sion MOllO} ithics Inc.
FEATURES
•
•
•
•
•
•
•
•
•
•
drain of 1mA, and excellenttemperature stability are achieved
with an improved bandgap design. Low cost, low noise, and
low power make the REF-01 an excellent choice whenever a
stable voltage reference Is required. Applications include
DIA and AID converters, portable instrumentation, and digital voltmeters. Full military temperature range devices with
screening to MIL-STD-883 are available. For guaranteed
long-term drift see the REF-10 data sheet.
10 Volt Output ........................... ±0.3% Max
Adjustment Range .......................... ±3% Min
Excellent Temperature Stability ....... 8.5ppml" C Max
Low Noise ......................... . . . .. 30~Vp_p Max
Low Supply Current ....................... 1.4mA Max
Wide Input Voltage Range ................. 13V to 33V
High Load-Driving Capability ................... 20m A
No External Components
Short-Circuit Proof
MIL-STD-883 Screening Available
PIN CONNECTIONS
NC•
NCO'N'C
ORDERING INFORMATIONt
PACKAGE
TA =25'C
avo MAX
(mV)
TO-SS
'-PIN
± 30
± 30
± 50
± 50
±100
REF01AJ'
REF01EJ
REF01J'
REF01HJ
REF01CJ
HERMETIC PLASTIC
DIP
DIP
'-PIN
'-PIN
REFOIAZ'
REFOIEZ
REF01Z'
REF01HZ
REF01CZ
LCC
REFOI RC/883
REF01HP
REF01CP
OPERATING
TEMPERATURE
RANGE
VIN 2
6 Your
NC3
MIL
COM
MIL
COM
COM
5 TRIM
4
GROUND
ICASE)
TO-99
REF-01RC/883
LCC
(RC-Sufflx)
(J-Sufflx)
• For devices processed in total compliance to M I L-STD-883. add /883 after
part number. Consult factory for 883 data sheet.
tAli commerCial and industrial temperature range parts are available with
burn-In. For ordering Information see 1986 Data Book, Section 2
EPOXY MINI-DIP
(P-Sufflx)
GENERAL DESCRIPTION
8-PIN HERMETIC DIP
(Z-Sufflx)
The REF-01 precision voltage reference provides a stable
can be adjusted over a ±3% range with
minimal effect on temperature stability. Single-supply operation over an input voltage range of 12V to 40V. low current
+10V output which
SIMPLIFIED SCHEMATIC
,----~--.,------1r_-------_----
;:: 0015
100
z
II1IIIIIIIIII
~
II
v/
~ 0.005
~
75"C
7
0.D10
~
'O'~O~~'~OO~UW~'k-W~~'O-k~lli'~O~OkLlllliW'M
DEVICE IMMERSED
IN 75"C OIL BATH
o
-10
FREQUENCY (Hz)
FREQUENCY (Hz)
TA = TA =
- - ,.1/
0.020
o
100
1M
tOOk
VIN = 15V
0025
~
~
z
::;
1111111
16
:l::>
:.la:
w
I
!5
w
0
031
~
-"
z
[
§?
r
I
~
!~ l000~11~11'1111'1
0031 )
0,1
!I
~ 0.030
o
I
1
I
36
_ 0035
~
~ ~N"~:'i.V
001 ~
56
46
10,000
OUTPUT CHANGE DUE TO
THERMAL SHOCK
10
30
20
40
50
60
TIME (SEC)
3.
NORMALIZED
LINE REGULATION
vs TEMPERATURE
NORMALIZED LOAD
REGULATION (diL = 10mA)
vs TEMPERATURE
MAXIMUM LOAD CURRENT
vs INPUT VOLTAGE
14
1.4
13
1.3
SHORT CIRCUIT PROTECTION
30
/' .00mwMIAX~
I
/
/
07
10
,.
~ 11
V
~
V
VIN
=
15V
30
-60 -40 -20
0.7
0
20
40
60
0,6
-60 -40 -20
80 100 120 140
0
'"
ffi
1'-
....... 1---"
a
10
~
09
~
i
1i
V
0
20
40
60
60
80
100 120 140
v
V
"
08
VI~
o
-60--40 -20
V
11
~
i'-r-.
,. 10
40
QUIESCENT CURRENT
vs TEMPERATURE
11.2
VIN = 15V
20
TEMPERATURE (Oel
13
1'- r-...
V
w 0.8
f'--...
"~
::>
/"
TEMPERATURE (oG)
a:
~ 20
,.9 15
.... P'
V
z
30
a;
O.g
7
::;
MAXIMUM LOAD CURRENT
vs TEMPERATURE
1
>- 2.
E
illa:
""
INPUT VOLTAGE (VOLTS)
/'
w
~ 1,0
06
2.
20
t!
/
a:
~ 08
g
TA '" 25"C
:/
g 1.2
/
"~ 1.1
"'" 10
~
~
ffi 0.9
DISSIPATION
I
/
u
~ 12
07
-60 -40 -20
80 100 120 140
TEMPERATURE (OC)
0
20
40
60
"
'~V
80 100 120 140
TEMPERATURE (OCI
10-8
1/86, Rev. A
------------I~ REF-01 +10V PRECISION VOLTAGE REFERENCE
TYPICAL APPLICATIONS
AID CONVERTER REFERENCE
D/A CONVERTER REFERENCE
ANALOG
+15V
INPUT
o TO +10V
+15V
10kO
+lSV
MSB
-=
LSB
-1SV
-lSV
+1SV
B'
B5
BS
B7
B8
82 83 84 85 86 87 88
81
POS. FULL-SCALE -1 LSB
SERIAL
OUTPUT
E
NEG. FULL-SCALE + 1 LSB
0
NEG. FULL-SCALE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CONNECT "START" TO
"CONVERSION COMPLETE"
FOR CONTINUOUS CONVERSIONS
START
+4.960
0
ZERO-SCALE
-15V
0.000
CONVERSION
COMPLETE
-4.960
0
TTL CLOCK
INPUT 225MHz
-5000
±10V REFERENCE
PRECISION CALIBRATION STANDARD
+15V
+10V
II
m
~l'A
1
{
-
REF-Ol
10kil
12
V'N
10kn
GND
+
S
Va
+15V
9V
REF-Ol
1
rv
10000V
5
TRIM
GND
lOOka
t
-lOV
-15V
CURRENT SOURCE
!2+
CURRENT SINK
VOLTAGE COMPLIANCE
1SV
-25V TO +3V
~~OUT
V'N
V'N
VO!---
Va
REF-al
TRIM
~
VOLTAGE COMPLIANCE
-3V TO +25V
~
REF·O'
R
lOUT '" 10 ~v +lmA
TRIM
GND
~
R
lOUT = 10~v +lmA
GND
j'
l'
+'OUT
6-15V
10-9
1/86, Rev. A
------------I~ REF-01 +10V PRECISION VOLTAGE REFERENCE
REFERENCE STACK WITH EXCELLENT LINE
REGULATION
PRECISION CURRENT SOURCE
A current source with 25V output compliance and excellent
output impedance can be obtained using this circuit. REF-01
®keeps the line voltage and power dissipation constant in
the only important error consideration at room
device
temperature is the negative supply rejection of the op amp.
The typical 3JJ,V/v PSRR of the OP-02E will create an 8ppm
change (31JV/v x 25V/10V) in output current over a 25V range.
For example, a 10mA current source can be built (R = 1kO)
with 300MO output impedance.
Three REF-01's can be stacked to yield 10.000, 20.000, and
30.000V outputs. An additional advantage is near-perfect line
regulation of the 10.0V and 20.0Voutput. A 32V to 60V input
change produces an output change which is less than the
noise voltage of the devices. A load bypass resistor (RB)
provides a path for the supply current (Isy) of the 20.000V
regulator.
In general, any number of REF-01's can be stacked this way.
For example, ten devices will yield outputs of 10, 20, 30 ...
100V. The line voltage can range from 105Vto 130V. However,
care must be taken to ensure that the total load currents do
not exceed the maximum usable current (typically 21mA).
CD;
25V
Ro=----8 X 1Q-6 x 10mA
t
12
50V
V ,N
32V to 60V
V ,N
6 Va
Va
TRIMM ED
QUTPU TS
30.00OV
6
REF-01
REF-O'
®
TRIM
GND
GND
4
2
V ,N
Va
10kn
4
2
V ,N
6
Va
REF-01
: =c
CD
6
20.0 OOV
R
(TRIM FOR
REF-01
CALIBRATION)
-----<
GND
4
6
R
TRIM 5
GND
2
V ,N
~:J
Va
4
10.00OV
REF-01
~~
6
6
10kn
QP-02E
+
3
TRIM
GND
Vo
780
.§
~
15V
/
~ 730
V
~
6 680
~
/
630
/
g 580
~
~
530
450
V
/
430
-60 -40 -20
0
20
40
60
80
to +12.SV,
REFERENCE STACK WITH EXCELLENT LINE
REGULATION
Two AEF-01's and one AEF·02 can be stacked to yield 5.000V,
15.000V and 25.000Voutputs. An additional advantage ofthis
circuit is near·perfect line regulation of the 5.0V and 15.0V
outputs. A 27V to 55V input change produces an output
change which is less than the noise voltage of the devices. A
load bypass resistor (AB) provides a path for the supply
current (Isy) of the 15.000V regulator.
In general, any number of AEF·01's and AEF-02's can be
stacked this way. For example, ten devices will yield ten
outputs in 5Vor 10V steps. The line voltage can range from 100V
to 130V. However, care must be taken to ensure that the total
load currents do not exceed the maximum usable current
(typically 21mA).
sso
830
SWing
100 120 140
TEMPERATURE 1°C)
TEMPERATURE CONTROLLER
. l227V TO 55V
v+
V ,N
(12 TO 32V)
Va
,------t---------_--,
c---- ---
I
I
I
I
~27kn
TRIM
GND
;.
c,. R6
I
V~
HEATING
ELEMENT
5
3 \
10kn
4
2
Vo 1-'-c1-'VI."v-~t-1
REF·02
GND
.1
RI
(92kn)
250 OOV
REF-01
.1,. R7
r-----------,
•
V ,N
1 ~~n
Va
6
1500OV
T I"-;-""'V--+-=-i
REF-01
IL
I
NOTE
4 _ .J
_ _ _ _(SEE
__
_II
__
R2
15kn
R5
TRIM 5
GND
2
22kn
V,N
Va
R4
27k.\1
6
4
10kn
500OV
REF-02
NOTES
1 REF-02 SHOULD BE THERMALLY CONNECTED
TO SUBSTANCE BEING HEATED
2 NUMBERS IN PARENTHESES ARE FOR A
SETPOINT TEMPERATURE OF 60°C
3 R3= Rl11R211R6
TRIM
OND
6
10kn
RB
68kn
4
10·17
1/86, Rev. A
II
-------l1fMD
REF-02 +5V PRECISION VOLTAGE REFERENCE/TEMPERATURE TRANSDUCER
PRECISION CURRENT SOURCE
A current source with 3SV output compliance and excellent
output impedance can be obtained using this circuit. REF-02
®keeps the line voltage and power dissipation constant in
device G) ; the only important error consideration at room
temperature is the negative supply rejection of the op amp.
The typical 3p.VlV PSRR of the OP-02E will create a 20ppm
change (3p.VIV x 3SVlSV) in output current over a 3SV range.
For example, a SmA current source can be built (R = 1kO)
with 3S0Mll output impedance.
CURRENT SINK
12
10UT
V,N
Vo ~
REF-02
3
TRIM
~
R
lOUT '" 6.~V +lmA
GND
l'
J-15V
VOLTAGE COMPLIANCE. -8V TO 25V
+SOV
3SV
Ro = 20 X 10- 6 X SmA
.-------':..rVo
D/A CONVERTER REFERENCE
REF-02
5,DkS1
GNO
MSB
+'6V
LSB
V,N
VO~----~----~~--'
REF-02
R
(TRIM FOR
CALIBRATION)
GND
±3V REFERENCE
Vo=O TO 35V
+7.6V
RC -'.-&sEC
VIN
vour"'6'--..------r-----<> Vo(+}
REF-02HJ
=
+3.OV
R1
2Ok!!
OND
CURRENT SOURCE
R2
13.3kO
12+1SV
V,N
Vo ~
REF-02
3
TRIM
!......o
R
lOUT. 6.~ +lmA
GND
>---1~--o
VoH • -3 OV
l'
t
lOUT
VOLTAGE COMPLIANCE' -25V TO +8V
10-18
1/86, Rev. A
REF-03
+2.SV PRECISION
VOLTAGE REFERENCE
Precision Monolithics Inc.
PRELIMINARY
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
The REF-03 preCision voltage reference provides a stable
+2.5V output which can be adjusted over a ±3% range with
minimal effect on temperature stability. Single-supply operation over an input voltage range of 4.5V to 33V, low current
drain of 1mA, and excellent temperature stability are achieved
with an improved bandgap design. Low cost, low noise, and
low power make the REF-03 an excellent choice whenever a
stable voltage reference is required. Applications include DIA
and AID converters, portable instrumentation, and digital
voltmeters. Full military temperature range devices with
screening to MIL-STD-883 are available.
2.5 Volt Output ............................... ±O.3%
Adjustment Range .............................. ±3%
Excellent Temperature Stability ............. 3ppm/oC
Low Noise .................................... 5/LVp_p
Low Supply Current ....................... 1.4mA Max
Excellent In Single +5V Systems
Wide Input Voltage Range ................ 4.5V to 33V
High Load-Driving Capability ..•................ 20m A
No External Components
Short-Circuit Proof
ORDERING INFORMATIONt
PIN CONNECTIONS
PACKAGE
TO-99
8-PIN
HERMETIC
DIP
8-PIN
REF03AJ'
REF03EJ
REF03BJREF03FJ
REF03AZREF03EZ
REF03BZREF03FZ
PLASTIC
DIP
8-PIN
REF03EP
REF03FP
N
N.CO·7N.C
OPERATING
TEMPERATURE
RANGE
C.
8
MIL
INO
MIL
INO
VIN 2
6 VOUT
N.C, 3
• For devices processed in total compliance to MIL-STO-883. add /883 after
part number. Consult factory for 883 data sheet.
t All commercial and industrial temperature range parts are available with
burn-in For ordering Information see 1986 Data Book, Section 2
5 TRIM
a-PIN EPOXY MINI-DIP
(P-Suffix)
4
GROUND
(CASE)
a-PIN HERMETIC DIP
(Z-Sufflx)
TO-99
(J-Sufflx)
SIMPLIFIED SCHEMATIC
.......r----...,...--------~---o
r-----~-
INPUT
2
R15
019
OUTPUT
6
A12'" 2kil
R9"'" 6kil
R11"", 2kn
R2
4
k---------~-------------~----~--~GROUNO
This preliminary product Information Is based on testing of a limited numberof devices. Final specifications may vary. Please contact local sales
office or distributor for final data sheet.
10-19
1/86, Rev. A
II
----------I~ REF-03 +2.SV PRECISION VOLTAGE REFERENCE -
ABSOLUTE MAXIMUM RATINGS
(Note 2)
DICE Junction Temperature (Tj) ••...••
••••.•.•••••..•...•....•.•....•........•.
40V
Power Dissipation (Note 1) ........•.....•.....•• 500mW
Output Short-Circuit Duration
NOTES:
1 See table for maximum ambient temperature rating and derating factor
(to Ground or VIN) •••.••••••••••.•••••.••••• Indefinite
PACKAGE TYPE
Storage Temperature Range
J, and
Z Packages .••...•••..•••..•• -65°C to +150°C
P Package
-65°C to +150°C
Lead Temperature (Soldering, 60 sec.) •••...••••.• 300°C
Input Voltage
REF-03
PRELIMINARY
........••....••.••••.•••
Operating Temperature Range
ELECTRICAL CHARACTERISTICS
SYMBOL
CONDITIONS
Output Voltage
Vo
IL
Output Adlustment Range
.6.Vtnm
Re
Output Voltage NOise
8
ne -e
71mW;oC
67mW;oC
56mW/"C
2 Absolute maximum ratings apply to both packaged parts and DICE, unless
otherwise noted.
~
MIN
0
~
10kO
REF-03A/E
MAX
TYP
2493
2500
±30
±33
0.1Hz to 10Hz (Note 5)
V,N
Load Regulation (Note 4)
80"C
75"C
36"C
at V IN = +15V, TA = 25°C, unless otherwise noted.
PARAMETER
Line Regulation (Note 4)
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
TO-99 (JI
8-PIn Hermetic DIP (ZI
8-PIn Plastic DIP (P)
-65°C to +125°C
REF-03A,REF-03B ................. -55°Cto+125°C
REF-03E, REF-03F ....... .. • .. . . • .. •• -25° C to +85° C
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
IL
~
2508
MIN
REF-038/F
TYP
MAX
2485
2500
±30
±3.3
UNITS
2.515
V
%
7.5
7.5
MV
e-e
4 5V to 33V
0006
0010
0.006
0.010
%/V
10m A
0005
0008
0006
0.010
%/mA
10
14
10
1.4
mA
~Oto
Turn-on Settling Time
ton
To ±0.1% of Final Value
QUiescent Supply Current
ISY
No Load
MS
Load Current
IL
10
21
10
21
mA
Sink Current
Is
-03
-05
-03
-0.5
mA
30
mA
Short-Circuit Current
Ise
ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
Temperature (Notes 1. 2)
= + 15V, -55° C :s:: TA :s:: + 125° C and IL = OmA, unless otherwise noted.
MIN
CONDITIONS
(Note 31
TCVo
Temperature Coefficient
at V IN
-25"Co> TA 0> +85"C
-55°C::;TA::;+125°C
Ouput Voltage Change With
Output Voltage
30
Vo~O
REF-03A1E
TYP
MAX
MIN
REF-038/F
TYP
MAX
UNITS
003
006
009
015
011
018
028
045
%
30
85
100
25.0
ppm/"C
Change in Vo Temperature
Coefficient With Output
07
07
ppm/%
Adjustment
Line Regulation
(VIN ~ 4'5V to 33V) (Note 4)
Load Regulation
(lL ~ a to 8mA) (Note 4)
-25° C:::; TA ::; +85° C
-55"C 0> TA 0> +125"C
0007
0009
0012
0015
0007
0009
0012
0.015
%/V
-25°C:::; TA ::; +85°C
-55"Co>TA o>+125"C
0006
0007
0010
0012
0.007
0009
0012
0015
%/mA
NOTES:
1
6.VOT IS defined as the absolute difference between the maximum
output voltage and the minimum output voltage over the specified
temperature range expressed as a percentage of 2 5V
AV
OT
3.
~IVMAX-VMINI
25V
TCVo (-25" to +85"CI
x 100
~
and TCVo (-55" to + 125" C)
..lVOT specification applies trimmed to +2 500V or untnmmed
TCVo IS defined as ~VOT diVided by the temperature range, Ie,
,WOT (-25" to +85"C)
110"C
~
-WOT (-55" to +125"CI
180"C
Line and Load Regulation specificatIOns Include the effect of self-heating.
5. Sample tested.
10-20
1/86, Rev. A
REF-OS
+5V PRECISION VOLTAGE REFERENCE
(GUARANTEED LONG-TERM STABILITY)
Precision Monolithics Inc.
FEATURES
• 5 Volt Output
• Guaranteed Long-Term Stability
. . . . . . . . . . . . . .. 100ppm/1000 Hrs Max
• Excellent Temperature Stability ....... 8.5ppm/ o C Max
• Low Noise. ... ..... ... .... ... ..... ... ... 15,.Np _p Max
• Low Supply Current.... .. ..... ..... .. .. .. 1.4mA Max
• Wide Input Voltage Range .................. 8V to 33V
• High Load-Driving Capability ................... 20mA
• Short-Circuit Proof
• Processed Per MIL-STD-883
effect on temperature stability. Long-term drift is guaranteed
at 100ppm/l000 hrs. maximum. Single-supply operation over
an input voltage range of 7V to 40V, low current drain of 1 mA,
and excellent temperature stability are achieved with an
improved bandgap design. Low cost, low noise, and low power
make the REF-05 an excellent choice whenever a stable
voltage reference is required. Applications include D/A and
AID converters, portable instrumentation, and digital voltmeters. The versatility of the REF-05 is enhanced by its use as
a monolithic temperature transducer. For +10V Precision
Voltage References see the REF-l0 data sheet.
GENERAL DESCRIPTION
ELECTRICAL CHARACTERISTICS/
ABSOLUTE MAXIMUM RATINGS
Contact factory for 883 data sheet with full electrical specifications. Typical performance characteristics and applications information are provided in the REF-02 data sheet.
The REF-05 precision voltage reference provides a stable +5V
output which can be adjusted over a ±6% range with minimal
LONG-TERM DRIFT PLOT (Average of 20 Devices)
PIN CONNECTIONS & ORDERING INFORMATION
0
NC
NC()'NC
0
0
8
0
,1\
0
"- tv' 1'...
REF-05
...... t-.....
o
VIN 2
t-
TEMP 3
-10 0
TO-99 (J-Sufflx)
REF-05AJ/883
REF-05BJ/883
6 VOUT
5 TRIM
4
GROUND
CASE
0
0
om_
•
•
_
m
_
~
_
DAYS ELAPSED
SIMPLIFIED SCHEMATIC
,-_____
-....,.---_~-------_---<>
~NPUT
R15
019
OUTPUT
6
R12 =6 lkH
R9 "'" 18kH
TRIM
5
3
TEMP
0-+----
Rll "'" 2kH
R2
L-_ _ _ _ _ _ _~~--_ _ _ _ _ _ _ _ _ _~---~~-_<~ROUND
10-21
1/86, Rev_ A
II
REF-tO
+lOV PRECISION VOLTAGE REFERENCE
(GUARANTEED LONG-TERM STABILITY)
Precision Monolithics Inc.
FEATURES
GENERAL DESCRIPTION
•
•
The REF-10 precision voltage reference provides a stable
+10V output that can be adjusted over a ±3% range with
minimal effect on temperature stability. Long-term drift is
guaranteed at 50ppm/1000 hrs. maximum. Single-supply
operation over an input voltage range of 13V to 40V, low
current drain of 1mA, and excellent temperature stability are
achieved with an improved bandgap design. Low cost, low
noise, and low power make the REF-10 an excellent choice
whenever a stable voltage reference is required. Applications
include D/A and AID converters, portable instrumentation,
and digital voltmeters. For+5V precision voltage references,
see the REF-05 data sheet.
•
•
•
•
•
•
•
10 Volt Output
Guaranteed Long-Term Stability
...................... " SOppm/1000 Hrs Max
Excellent Temperature Stability ....... 8.Sppm/o C Max
Low Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . ... 30,",Vp _p Max
Low Supply Current . . . . . . . . . . . . . . . . . . . . .. 1.4mA Max
Wide Input Voltage Range ................. 13V to 40V
High Load-Driving Capability ................... 20mA
Short-Circuit Proof
Processed Per MIL-STD-883
LONG-TERM DRIFT PLOT (Average of 20 DevIces)
ELECTRICAL CHARACTERISTICSI
ABSOLUTE MAXIMUM RATINGS
40
Contact factory for 883 data sheet with full electrical specifications. Typical performance characteristics and applications information are provided in the REF-01 data sheet.
20
-20
t;:
"~
~
....
-40
~
-......REF-l0
Q
-60
-80
PIN CONNECTIONS & ORDERING INFORMATION
NC
NC07NC
- r- -
8
-100
VIN 2
-120
-140
o
20
40
60
80
100
120
140
160
NC 3
180
TO-99 (J-Sufflx)
REF-10AJ/883
REF-10BJ/883
6 VOUT
5 TRIM
4
DAYS ELAPSED
GROUND
(CASE)
SIMPLIFIED SCHEMATIC
,--____-+_--.-____- - - - - - - - . _ - - 0 INPUT
2
R15
a19
OUTPUT
6
R3
A12 "" 16.7kn
R9 ""5OkO
R5
TRIM
5
a1Jr~~~~--_4~~-----~~-----4----_+
R1
A11 .... 2kn
R2
~_ _ _ _ _ _ _~~------------~---~~-_a~ROUND
10-22
1/86, Rev. A
Table of Contents 1
Ordering Information 2
Product Assurance Program 3
Industry Cross Reference 4
)
Operational Amplifiers 5
Instrumentation Amplifiers 6
Voltage Followers/Buffers 7
Voltage Comparators 8
Matched Transistors 9
Voltage References 10
Digital-to-Analog Converters 11
Analog-to-Digital Converters 12
Analog Switches/Multiplexers 13
Sample-and-Hold Amplifiers 14
Special Functions 15
Communications Products 16
Package Information 17
Sales Offices, Representatives and Distributors 18
D/A
CONVERTERS
Precision MOJlolithlcs Inc.
11-4
Introduction
11-4
Definitions
11-8
Selection Guide
11-10
DAC-Ol
11-84
11-88
11-92
11-104 DAC-888
BYTEOAC® 8-Bit High-Speed
"Microprocessor Compatible"
Multiplying OJA Converter
DAC-06
Two's-Complement lO-Bit
Voltage-Output OJA Converter
11-23
11-116
DAC-08
8-Bit High-Speed Multiplying
OjA Converter
11-34
DAC-IO
11-131
DAC-20
11-136 DAC-8408
Quad 8-Bit Multiplying CMOS OJA
Converter With Memory
DAC-86
COMOAC® Companding
OJA Converter
11-58
11-140
11-148
PM-565A
Complete High-Speed 12-Bit
Monolithic OJA Converter
DAC-89
COMOAC® Companding
OjA Converter
11-76
PM-562
12-Bit Multiplying Current-Output
OjA Converter
DAC-88
COMOAC® Companding
OjA Converter
11-67
DAC-8212
Dual 12-Bit Buffered Multiplying
CMOS OjA Converter
2-0igit BCD High-Speed Multiplying
OJA Converter
11-50
DAC-1508A/1408A
8-Bit Multiplying OJA Converters
11-122 DAC-8012
CMOS 12-Bit Multiplying OJA
Converter "With Memory"
lO-Bit High-Speed Multiplying
OjA Converter
11-42
DAC-312
12-Bit High-Speed Multiplying
OjA Converter
DAC-02/DAC-03/DAC-05
lO-Bit-Plus-Sign Voltage-Output
OJA Converters
11-19
DAC-210
11-Bit Voltage-Output OjA Converter
6-Bit Voltage-Output OJA Converter
11-14
DAC-208
9-Bit Voltage-Output OJA Converter
11-149 PM-7226
Quad 8-Bit CMOS OJA Converter
With Voltage Output
DAC-IOO
lO-Bit Current-Output OJA Converter
11-2
n/A
CONVERTERS
Precision Monolithics Inc.
11-150 PM-7524
CMOS 8-Bit Buffered Multiplying
D/A Converter
11-196 PM-7543
12-Bit Serial-Input Multiplying CMOS
D/A Converter
11-159 PM-7528
Dual 8-Bit Buffered Multiplying CMOS
D/A Converter
11-197
11-175
PM-7545/PM-7645
12-Bit Buffered Multiplying CMOS
D/A Converters
11-208 PM-7548
12-Bit Multiplying CMOS
D/A Converter
PM-7533
CMOS Low Cost lO-Bit Multiplying
D/A Converter
11-185 PM-7541
CMOS 12-Bit Monolithic Multiplying
D/A Converter
11- 209 JM38510/11301/11302
JAN 8-Bit Multiplying D/A Converters
11-195 PM-7542
12-Bit Multiplying CMOS
D/A Converter
III
11-3
D/A
CONVERTERS
Precision Monolithics Inc.
INTRODUCTION
Figure 11.1 Gain and Offset Error Defined
A D/A converter accepts a digital input and
produces an analog output. The basic DAC
consists of a voltage or current reference, binaryweighted precision resistors, a set of electronic
switches, and a means of summing the weighted
currents.
Three important criteria for selecting a good
DAC are resolution, accuracy, and speed. Other
essential requirements to be considered are
temperature stability, input coding, output
format, reference requirements, and power
consumption.
Since introducing the first monolithic D/A
converter in 1970, PMI has continually
improved and updated its DAC product line.
Using both bipolar and CMOS technologies,
PMI offers complete selections of parametric
trade-offs available from these technologies.
Very high speed, internal references and
amplifiers are key features of the bipolar
technology DACs. The CMOS technology DACs
offer a much higher degree of logic interface
function, while maintaining absolute minimums
in power dissipation. A wide offering of
microprocessor-interfaceable DACs simplify
connection to 4,8, and 16-bit microprocessor
systems. The DAC with "memory" is another
first offered by PMI to simplify system selfdiagnosis of data path integrity.
The selection guides following the definitions
will aid you in quickly locating the appropriate
DAC for your application.
/'
/"
/
,,"
,,"
fJ';/
~"
OFFSET
,,/
ERROR o /'
T
""0-O-IG-IT-A-L-IN-P-U-T-
OIGITAL INPUT
A.C. Feedthrough - The ratio of the amplitude
of signal at the DAC output to the reference
input with all DAC switches off. This parameter
is expressed in dBs.
BCD - The abbreviation BCD stands for binarycoded decimal. It is a binary code used to
represent decimal numbers in which the digits 0
through 9 are coded, using the 4-bit binary
8-4-2-1 code.
Binary - A positive-weighted code in which a
number is represented by:
N = a020 + a1 2 1 + a2 22 + ... + a n2n
where each coefficient "aj" has a value of zero
or one. Data converters use this code in its
fractional form where:
N = a 12-1 + a 22- 2 + a32- 3 + ... + a n2- n
and N has a fractional value between zero
and one.
Bit - The unit of binary information. It can have
the value of zero or one.
Bipolar Output - When the analog signal range
includes both positive and negative values, the
output is said to be bipolar. The transfer
characteristic of an ideal 2-quadrant bipolaroutput DAC is shown in Figure 11.2.
Differential Nonlinearity (DNL) - Differential
nonlinearity is the worst case deviation of any
adjacent analog outputs from the ideal 1 LSB
step size. The deviation of the actual "step size"
from the ideal step size of 1 LSB is called
differential nonlinearity error or DNL. DACs
with DNL greater than ±1 LSB may be
non monotonic. Maximum DNL error is less than or
equal to twice the maximum INL. (See Figure 11.3)
DEFINITIONS LINEAR DIGITAL-TO-ANALOG
CONVERTERS
Absolute Accuracy - The absolute accuracy of
a DAC is the difference between the actual
unadjusted analog output and the ideal output
that is expected when a given digital code is
applied. Sources of error include full-scale error
(gain error), zero-scale error (offset error),
nonlinearity errors, and the drift of all of these.
Therefore, absolute accuracy includes all
deviations from the ideal. (See Figure 11.1)
11-4
n/A
CONVERTERS
Precision MOl1olithics Inc.
same relative accuracy (the output can change
absolutely).
Full Scale (FS) - The full-scale output of a
DAC is its maximum voltage or current. For a
binary DAC, the full-scale output occurs when
the digital inputs are all ones. The full-scale
value is one LSB less than the reference value.
Figure 11.2 Bipolar Output Converter
QUADRANT
1
+F8
ANALOG
/
/
/
ANALOG
OUTPUT
/
/
/
GAIN ~RROR
t~~T~~~~
/
Full-Scale Gain Error (GFSE) - See Gain Error.
Full-Scale Range (FSR) - The difference
between the maximum analog output and the
minimum analog output of a DAC.
Gain Drift (TCGFS) - The variation of the fullscale value (voltage or current) measured over
the operating temperature range is called gain
drift. This parameter has units of %FS, ppmFS,
or LSB. It may also be expressed % of FS/oC,
ppmFS/oC, etc.
Gain Error (GFSE) - The difference between the
actual and the ideal analog output range,
expressed as a percent of full-scale or in terms
of LSB value (see Figure 11.1). It is the deviation
in slope of the DAC transfer characteristic from
ideal.
Glitch - A glitch is a switching transient
appearing in the output during a code transition.
Its value is expressed as a product of voltage
(V x ns) or current (mA x ns) and time duration or
charge transferred (in Picocoulombs).
Integral Nonlinearity (INL) or Nonlinearity (NL)
- This is the single most important DAC
specification. PMI measures INL as the
maximum deviation of the analog output (from
the ideal) from a straight line drawn between the
end pOints, expressed as a percent of full-scale
range or in terms of LSBs. (See Figure 11.5)
For DACs, a specification of ±1/2 LSB INL
guarantees monotonicity and ±1 LSB maximum
differential nonlinearity.
Least Significant Bit (LSB) - The analog value
of the LSB is the smallest change that can occur
in the output of a DAC. It corresponds to a onebit change in the binary input. The analog value
will be either a voltage or current.
FSR
LSB (Analog Value) = - 2n
where FSR = Full-Scale Range
n = number of bits
DIGI;::~ +---=I'=-,z.¥...L..=':'::::'=:.!+ ~r:ITAL
/
/
/
/
/
IDEAL ANALOG OUTPUT
/
/
/
L ____ _
-F8
ANALOG
QUADRANT
3
Figure 11.3 Nonlinearity (NL) and Differential
Nonlinearity (DNL)
//;/
DNL = -1 1/2 LSB
.....
,.1
/
/
....... NON-MONOTONIC POINT
.DNL=+1 LSB
001
010
011
I
100
I
101
I
110
111
Dynamic Range (DR) - The dynamic range of a
DAC is the ratio of the largest output to the
smallest output (excluding zero) expressed in
decibels (dB). For linear DACs, this ratio is 2 n ,
where n = number of bits of resolution.
DR (in dB) = 20 L091Q2n '" 6n for linear DACs;
(COMDACs® are 66 or 72dB.)
Endpoint Linearity - See Integral Nonlinearity.
Functional Compliance - The functional
compliance of a DAC is the voltage range over
which the current output can be driven and for
which the DAC output current will maintain the
11-5
II
n/A
CONVERTERS
Precision Monolithics Inc.
Figure 11.5 Nonlinearity
Most Significant Bit (MSB) - The analog value
of the MSB is the largest incremental output
change obtainable by switching a single input
bit. The analog value will be either a voltage or
current.
FSR
MSB (Analog Value) = - 2
Monotoniclty - A DAC is monotonic if the
analog output either increases or remains the
same for an increasing digial input code. If the
DNL is less than or equal to ±1 LSB,
monotonicity is guaranteed. (See Figure 11.3)
Figure 11.4 DAC Transfer Curves
ANALOG
OUTPUT
Nonlinearity (NL) - See Integral Nonlinearity.
Offset Drift (TCVos, TClos) - The variation of
the offset (voltage or current) measured over the
operating temperature range. The offset drift is
divided by the temperature range over which it is
measured, and expressed in ppm per degree
centigrade or percent of full-scale range. This
parameter applies to DACs operating in the
bipolar output mode. See zero-scale drift for
DACs operating in the unipolar output mode.
Offset Error (VOSE, lOSE) - The offset error is
the error at analog zero for a data converter
operating in the bipolar mode.
Output Resistance (Ro) - Output resistance is
the equivalent internal resistance for a current
output 01 A converter as seen at its output. It is
measured as the change in output current ~I
with the change in output voltage ~V. It is a
direct measure of the true compliance.
Power Supply Sensitivity (Pss) - The change in
the output of the converter due to a change in
the power supply value. This may be expressed
as a percent of full-scale range per one percent
change in the power supply, or as a percent of
full scale per volt of power supply change.
Normally Pss is specified at DC; it is sometimes
specified over a given frequency range.
Multiplying DACs - The DAC multiplies an
analog reference by a digital word. Some DACs
can multiply only positive digital words by a
positive reference. This is known as single
quadrant operation (Quadrant I, see Figure 11.4).
Two quadrant operation (Quadrants I and III)
can be performed by a DAC that usually
operates in Quadrant I by configuring the
output for bipolar output operation. This is
accomplished by offsetting the output by a
negative MSB (1/2 of FSR), so that the MSB
becomes the sign bit. CMOS DACs provide four
quadrant operation by allowing the use of both
positive and negative references. (Quadrants
I, II, III, IV).
11·6
n/A
CONVERTERS
Precision MonoHthics Inc.
Relative Accuracy - See Integral Nonlinearity.
Resolution (n) - The resolution of a DAC is the
number of states (2n) that the FSR is divided (or
resolved) into, where n is equal to the number
of bits.
Settling Time - Settling time is the elapsed time
for the analog output to reach its final value
within a specified error band after a digital input
code change. It is usually specified for a fullscale change and measured from the 50% point
of the logic input change to the time the output
reaches its final value within the specified error
band. (See Figure 11.6)
Zero-Scale Drift (TCVzs. TClzs) - The variation
of zero scale measured over the operating
temperature. It is expressed in ppmFS/oC, or
%FS/OC, etc.
Zero-Scale Symmetry Error (VZSS) - This
definition applies only to sign-magnitude DACs.
It is the change in the analog output produced
by switching the sign bit with a zero-code input
to the magnitude bits. It is expressed in units of
voltage, current, or in fractions of an LSB.
DEFINITIONS - COMPANDING DACs
The companding (COMDAC®) DACs that PMI
manufactures are the DAC-86, DAC-88, and the
DAC-89. They are constructed such that the
more significant bits of the digital input have a
larger than binary relationship to the less
significant bits. This decreases the resolution
of the more significant bits, which increases the
analog signal range. The effect of this is to
compress more data into the more significant bits.
Chord - The mathematical formula, describing
the DAC transfer function, is implemented by
performing a piecewise linear approximation of
the function. The straight line segments used in
the approximation are called chords.
Chord Endpoints - The digital code corresponding to the maximum analog output for a
given chord is called the chord endpoint.
Figure 11.6 Settling Time Measurement
+6.Vo
I--.---'------;J_-+--..".-VO
I:~~~ "'SLEWING~
SETTLING TIME TO
FIN~NG
±Avo-----.-I
Three-State Outputs - A digital output circuit
that can be programmed to output a logic low,
logic high, or a high output impedance state.
These devices are generally connected to digital
buses.
True Compliance - The true compliance of a
DAC is the voltage range over which the current
output can vary while the DAC maintains an
absolute accuracy of ±1/2 LSB. The higher the
DAC output impedance, the better the voltage
compliance will be.
Unipolar Output - A DAC operates in the
unipolar output mode when the analog output
starts at zero, stopping at a full-scale positive or
negative value, while the digital inputs are
changed from zero to all-ones code. The analog
output occurs in one quadrant.
Zero-Scale Error (VZSE. IZSE) - The zero-scale
error is the error at analog zero for a data
converter operating in the unipolar mode.
Dynamic Range (DR) - The dynamic range of a
DAC is the ratio of the largest output to the
smallest output (excluding zero) expressed in
decibels (dB). For the COMDACs® this would be
output (117 15) divided by output (10 1)' This is then
converted to dB using the formula:
DR=20L091O(~)
10,1
(dB)
Encode Current - The encode current is the
difference between 10E(+) and 100 (+) or the
difference between 10E (_) and 100 (_) at any
code.
Full-Scale Symmetry Error - The full-scale
symmetry error of a DAC is the difference
between the maximum and the minimum analog
output values. For the COMDACs® this is the
difference between 100 (_) and 100 (+) or 10E (+)
and 10E (_).
11·7
II
n/A
CONVERTERS
Precision MOIlolithics Inc.
Output-Level Notation - Each output current
level may be designated by the digital input
code as Ie,s; where c = chord number and s =
step number. For example, 100 = zero scale
current; 101 = first step from zero; 10 ,15 =
endpoint of the first chord (Co); and 17,15 = fullscale current.
Steps - Each chord is divided into equal increments called steps.
Step Nonlinearity - This is the deviation of the
actual step size from the ideal step size within a
chord. In a linear DAC, it corresponds to
differential nonlinearity.
DIGITAL-TO-ANALOG CONVERTER
SELECTION GUIDE
PMI offers a complete line of digital-to-analog
converters (DACs), all of which are guaranteed to
be monotonic over their operating temperature
ranges, and some which have become industry
standards. The DACs have been arranged in a
matrix, which highlights their primary
characteristics so that the user can easily
narrow the selection, according to specific
requirements. More detailed specifications are
then tabulated in each product group.
Voltage Output
..
Current Output
'
E
..."'"9
5
0
0
N
0
N
0
<0
'"
•
6-Blts
8-Blts
10-Bits
12-Blts
•
0
0
••••
••
Input Coding
BCD
Binary
Complementary Binary
Sign Magnitude
Input Latches
~p
Compatible
Two's Complement
Complementary Current Outputs
Internal Reference
Logic Threshold Control
JAN Qualified
Operating Temperature Range
Military
Industrial
Commercial
'Compandlng
0
0
0
'"
<0
<0
<0
0
co .,;
'" '"
<0
~
...::;;.,;
'"5
"'"
'" ;:; ;:; tl1? '"::i; u u u '"~ ~ ~ "~ u ~
U
U
« « « « « '"
« C§ « ::;; ::;; ::;; ::;; C§ ::;;
0
0
0
0
0
11. 0
0
11. 11. 11. 11.
11.
'" U U U
U
U
« « « « «
0
0
0
0
0
Resolution
"'"~
'"<0
U
«
tl
«
<0
CMOS
0
0
0
••
co
••
<0
<0
••• •
•
<0
•
•••
•
• • ••• ••••••
•
•
••••
•
• •••
•
••• • • • • •
•
••••••
••• •• ••
•
••• ••• ••••• ••••••
• • ••••••••
•••••••••••••• ••••••
11-8
n/A
CONVERTERS
Precision Monoltthics Inc.
DIGITAL-TO-ANALOG CONVERTER SELECTION GUIDE
Six-Bit
DAC-01
6-Bit Voltage-Output D/A
31's settling, includes ref., 250mW power dissipation
8-Bit
8-Bit
8-Bit
8-Bit
85ns settling, 1LSB gain error, 0.1%INL
Includes ref., 0.1 %INL, 750ns settling
8-bit input latch, 0.1%INL, 400ns settling
0.19%INL, 250ns settling, 157mW power dissipation
Eight-Bit
DAC-08*
DAC-208
DAC-888
DAC-1508A1
1408A
PM-7524
PM-7528
JM385101
11301-11302
High-Speed Multiplying D/A
Plus Sign Voltage-Output D/A
High-Speed I'P-Compatible D/A
Multiplying D/A
'hLSB INL, 1mW power dissipation, 10ppm/oC
gain drift
1% matching, +5V to +15V single supply, 0.5LSB INL
CMOS 8-Bit Multiplying D/A with
Latches
CMOS Dual 8-Bit Buffered
Multiplying D/A
JAN Qualified DAC-08
MIL-M-38510/113 device types 01 and 02
Eight-Bit Companding
DAC-86
DAC-88
DAC-89
Companding D/A Converter
Companding D/A Converter
Companding D/A Converter ('A' Law)
1'255 law, meets D3 specs, encode and decode
Improved accuracy and speed over DAC-86
11-bit accuracy and resolution around zero
Ten-Bit and BCD
DAC-021
03/05
DAC-06
DAC-10
DAC-20
DAC-100
DAC-210
PM-7533
10-Bit-Plus-Sign Voltage-Out DIA
Includes ref., ±10V out, 21's settling
Two's Complement 10-Bit VoltageOut D/A
10-Bit High-Speed Multiplying D/A
2-Digit BCD High-Speed Multiplying D/A
10-Bit Current-Output D/A
10-Bit-Plus-Sign Voltage-Output D/A
CMOS Low-Cost 10-Bit Multiplying D/A
Includes ref., 1LSB INL, 1.51's settling
85ns settling, 10ppmfOC drift, 0.05% INL
85ns settling, 0.25LSB gain error, 0.25LSB INL
Includes ref., 375ns settling, 15ppm/oC drift
Includes ref., 0.05%INL, 1.51's settling
0.5LSB INL, 4-quadrant multiplying, 2mA Isy
Twelve-Bit
DAC-312
DAC-8012
PM-562
PM-7541
PM-75451
7645
0.012%DNL, 0.025%INL, 250ns settling
Data read back, 0.5LSB INL, 2ppm/oC TC
12-Bit High-Speed Multiplying D/A
CMOS 12-Bit Multiplying D/A with
Memory
12-Bit Multiplying D/A Converter
CMOS 12-Bit Multiplying D/A
CMOS 12-Bit Multiplying D/A with
Latches
0.25LSB INL, 1.51's settling, 0.5LSB DNL
0.5LSB INL, 4-quadrant multiplying, 2mA Isy
0.5LSB INL, 1LSB gain error, 2mA ISY
"IndIcates product avaIlable In LCC package (1986)
11·9
a
DAC-Ol
6-BIT VOLTAGE-OUTPUT
D/A CONVERTER
PreciSIOil MOIlO]ithics Inc.
FEATURES
•
•
•
•
•
•
•
•
voltage reference and fast summing op amp on one chip.
Monolithic construction provides low power consumption
and high reliability. Wide power supply range, three output
voltage options, and three input code options assure flexibility for a wide variety of applications. A seventh bit may also be
added for greater resolution. Introduced in 1970, the DAC-01
is still the fastest, lowest power, most accurate 6-bit complete
monolithic DAC available. The DAC-01 is ideal for CRT
deflection circuits, servo pOSitioning controls, digitally programmed power supplies and pulse generators, modem and
telephone system digitizing and demodulation circuits, digital filters, and 6-bit AID converters.
Fast........................... 3/o1s Settling Time Max
Complete ....... Includes Reference, Ladder, Op Amp
Low Power Consumption ................ 250mW Max
6-Blt Resolution .....•.•.............. 7-Blt Accuracy
3 Output Options .••.•.............. +10V, ±5V, ±10V
Standard Power Supplies .•..•.......... ±12V to ±18V
TTL - Compallble Logic Levels
MIL-STD-883 Cia.. B Processing Available From Stock
ORDERING INFORMATIONtt
14-PIN HERMETIC DIP
FULL TEMP.
N.L. LSB
MILITARY
TEMP.
±1/8
DAC01AY"
DACOW"
DAC01BY"
DAC01FY"t
±1/4
COMMERCIAL
TEMP.
PIN CONNECTIONS
DAC01CY
DAC01HYt
DAC01DY
±1I2
14
MSB B1
• For devices processed In total compliance to MIL-STD-883, add /883 after
part number Consult factory for 883 data sheet
tUmpolar only - all others unipolar or bipolar
trAil commercial and Industrial temperature range parts are available With
burn-In, For ordering information see 1986 Data Book, Section 2,
LSB 86
6
1....-_-1
GENERAL DESCRIPTION
FULL-SCALE TRIM
12
BIPOLAR/UNIPOLAR
11
SUM NODE
10
SCALE FACTOR
9
GROUND
8
ANALOG OUTPUT
14-PIN HERMETIC DIP
(V-Suffix)
The DAC-01 is a complete monolithic 6-bit digital-to-analog
converter. The device contains current steering logie, current sources, a diffused resistor ladder network, precision
SIMPLIFIED SCHEMATIC
,
OIGITAL LOGIC INPUTS
MSB
1
v+
LSB
2
3
4
5
7
6
SUM
11
MODE
--
10
SCALE
FACTOR
IFS = 2mA
I I
1
I I I
r-...
r-...
.......
J J J J J"" J
VREF
.......
.......
~
~
"r~
541<
~>--
@ @
541<
- .........
""
+/
•
ANA LOG
OUTPUT
I
b13v-
14J FULL
SCALE
TRIM
11-10
BIPOLAR/
UNIPOLAR
12
•
GROUND
1/86, Rev. A
_ _ _ _ _ _ _ _ _ _---\~ DAC-01 6-BIT VOLTAGE-OUTPUT D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS (See Note 3)
Storage Temperature ................. -65°C to +150°C
Lead Temperature (Soldering, 60 sec) ............. 300°C
Output Short-Circuit Duration (Note 2) ........ Indefinite
Operating Temperature
DAC-01A, DAC-01, DAC-01B,
DAC-01F ......................... -55°C to +125°C
DAC-01C, DAC-01H, DAC-01D .......... O°C to +70°C
DICE Junction Temperature (Ti) ....... -65°C to +150°C
V+ Supply Voltage to Ground ................. 0 to +18V
V- Supply Voltage to Ground .................. 0 to -18V
Logic Input to Ground ...................... -0.7 to +6V
Internal Power Dissipation (Note 1) .............. 500mW
NOTES:
Rating applies to ambient temperatures of 100°C For temperatures above
100·C. derate linearly at 10mWI"C.
2. Short circuit may be to ground or either supply. Rating applies to + 125· C
case temperature or +75° C ambient temperature.
3 Absolute maximum ratings apply to both DICE and packaged parts. unless
otherWise noted.
ELECTRICAL CHARACTERISTICS at Vs = ±15Vand over the rated operating temperature range, unless otherwise noted.
PARAMETER
SYMBOL
Output Options
DAC-01A
DAC-01
DAC-01B
DAC-01F
DAC-01C
DAC-01H
DAC-01D
Unipolar
Bipolar
Unipolar
Bipolar
Unipolar
Bipolar
Unipolar
Unipolar
Bipolar
Umpolar
Unipolar
Bipolar
UNITS
Temperature Range
TA
-55/+125
-55/+t25
-55/+125
-55/+125
0/+70
0/+70
0/+70
·C
Nonlinearity 25° C/Maxlmum
NL
±0.20
±0.40
±0.40
±040
±040
±0.40
±0.78
%FS
Nonlinearity Over
Temperature - Maximum
NL
±0.30
±0.45
±0.45
±0.45
±0.45
±0.45
±0.78
%FS
Full-Scale TempcoMaximum
Tc
±80
±80
±120
±80
±160
±160
±160
ppm/·C
25
25
25
40
25
40
50
mV
Unipolar Zero-Scale Output
V
Voltage - Maximum (Notes 1,2) zs
ELECTRICAL CHARACTERISTICS for all DAC-01 grades, Vs = ±15V and over the rated operating temperature range
unless otherwise noted.
DAC-01
PARAMETER
Unipolar Full Range
Output Voltage I Note 3)
SYMBOL
CONDITIONS
VFR
2kO load, 10gic:O; 0.8V, short pm 13 to pin 14.
Short pin 12 to Ground and pin 10 to pin 11.
Bipolar Output Voltage INote 3)
±5 Volt Range
VFR+
VFR±10 Volt Range
VFA+
VFRBipolar Offset Voltage (Note 1)
MIN
2kO load, short pin 11 to pin 12.
Short pin 13 to pin 14, short pin 10 to pin 11
Logic Inputs :0; 0.8V
Logic Inputs 2: 2 OV
Open pm 10
Logic Inputs,; 0.8V
Logic Inputs 2: 2.0V
MAX
UNITS
+10.0
+11.75
V
+4.93
-5.94
+5.94
-4.93
V
+9.86
-11.89
+11.89
-9.86
V
±40
±80
±5 Volt Range
± 10 Volt Range
±112 II V FR+ I -I VFs-1 )
TYP
Resolution
±70
±140
6
Logic Input "0"
V 1NL
Logic Input "1"
V ,NH
Logic Input Current. Each Input
liN
Power Supply Sensitivity
Pss
±12V'; Vs'; ±18V VFS ~ 10.0V
Power Consumption
Pd
No Load
Supply Current
1+
1-
V+= +15V
V-= -15V Logic Inputs'; 0.8V
Setting Time to ±1/2 LSB
INote4)
ts
2.0V ,; Logic Level,; 0.8V TA = 25· C
mV
Bits
0.8
V
±2
±8
p.A
±0.01
±015
200
250
mW
7.3
9.3
mA
3
P.s
V
NOTES:
1. Zero-scale or bipolar offset voltage can be trimmed to zero Yolts or to the
exact one's or two's complement condition with an external resistor
network to pin 11.
2. Logic input voltage 2: 2.0V
3.
4.
11-11
15
Full-scale IS adjustable to precisely 10V for unipolar operation and 10V or
20V peak-to-peak bipolar operation with an external 5000 potenllometer
from pin 14 to V-.
Guaranteed by design
1/86, Rev. A
II
_ _ _ _ _ _ _ _ _--IIfMDDAC-01 8-BIT VOLTAGE-OUTPUT DlA CONVERTER
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
8.
B1 (MSB)
B2
B3
B4
BS
B8 (LSB)
7. V+
8.
9.
10.
11.
12.
13.
14.
ANALOG OUTPUT
GROUND
SCALE FACTOR
SUM NODE
BIPOLAR/UNIPOLAR
VFULL-SCALE TRIM
DIE SIZE 0.092 X 0.054 Inch, 4988 sq. mill (2.34 X 1.37 mm, 3.21 Iq. mm)
For additional DICE Information ref.r to
1988 Data Book, Section 2.
WAFER TEST LIMITS at TA=25°C.
DAC-01N
BIPOLAR AND
UNIPOLAR
DAC-01G
BIPOLAR AND
UNIPOLAR
PARAMETER
SYMBOL
CONDITIONS
LIMIT
LIMIT
UNITS
Nonlinearity
NL
VS =±15V
114
1/2
L.S.B.MAX
Zero-Scale Voltage
VZS
VS =±15V
25
35
mVMAX
WAFER TEST LIMITS at Vs= ± 15V, TA= 25°C, unless otherwise noted.
DAC-D1
PARAMETER
SYMBOL
CONDITIONS
Unipolar Full-Scale Output
Voltage (All Models)
VFR
2kn Load. Logic S 0.8V. Short V- to Full-Scale Trim. Unipolar/
Bipolar to Ground. and Scale Factor to Sum Node
VFRt
VFR-
2kn Load. Short Sum Node to Unipolar/Bipolar.
Short V- to Full-Scale Trim and Scale Factor to Sum Node.
Logic Inputs S O.BV
Logic Inputs ~ 2.0V
Open-Scale Factor
Logic Inputs S 0.8V
Bipolar Output Voltage
±5 Volt Range
± 10 Volt Range
VFRt
VFR-
Logic Inputs ~ 2.0V
± 5 Volt Range
±to Volt Range
Bipolar Offset Voltage
±1I2 (IVFRtl-IVFR-I)
LIMIT
UNITS
10.00
11.75
VMIN
V MAX
+4.93
-5.94
VMIN
V MAX
+9.78
VMIN
-11.89
V MAX
±1/2
LSBMAX
6
Bits MAX
Logic Input "0"
V1NL
0.8
V MAX
Logic Input "I"
V1NH
2
VMIN
LogiC Input Current. Each Input
Vov
±8
pAMAX
Power Supply Rejection
PSR
±12V S Vs S ±18V. Vs = 10.OV
0.15
'IIoFSNMAX
Power Consumption
Pd
No Load
250
mWMAX
Resolution
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations In asesmbly methods and normal yield loss, yield after packaging Is not
guaranteed for standard product dice. Consult factory to negotiate specifications baesd on dice lot qualification through sample lot asesmbly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS at 25° C.
DAC-01N
DAC-01G
TYPICAL
TYPICAL
To ±1/2 LSB
1.5
1.5
,.s
VS=±15V
eo
90
ppmfOC
PARAMETER
SYMBOL
CONDITIONS
Settling Time
ts
Full-Scale Tempco
11-12
UNITS
1/86, Rev. A
-----------l~ DAC-01 a-BIT VOLTAGE-OUTPUT D/A CONVERTER
BASIC CIRCUIT CONNECTIONS
APPLICATIONS INFORMATION
FULL-SCALE ADJUSTMENT TECHNIQUE
INPUT CODES
The DAC-01 uses standard complementary binary coding for
unipolar operation (all inputs logic high produces zero output voltage). One's complement coding may be Implemented
by shorting pin 11 to pin 12 and inverting the MSB (all other
bits are not inverted). Complementary offset binary coding
may be implemented by shorting pin 11 to pin 12, and Injecting approximately 5/JA into pin 11 (which Is at ground potential) by using the "optional Zero-Scale or bipolar offset
adjustment" circuit. Two's complement code is achieved
when the MSB for complementary offset binary Is Inverted.
FULL-SCALE ADJUST
A 500n pot from pin 14 to V- can be used to adjust the
Full-Scale output voltage to exactly 10 volts in unipolar mode
or 10 to 20 volts peak-to-peak in bipolar mode. If no pot is
used, connect pin 14 to V-.
~15V
OPTIONAL ZERO-SCALE OR
BIPOLAR OFFSET ADJUSTMENT
SCALE FACTOR
For+ 10 volts or±5 volt outputs, short pin 10 to pin 11 (adjusts
the feedback resistor around the output amplifier). For ±10
volt output, leave pin 10 open. Intermediate output voltages
may be obtained by placing a pot between pin 10 and pin 11.
This will, however, seriously degrade the Full-Scale temperature coefficient due to the mismatch between the
+1150ppmfOC tempco of the diffused resistors and the pot
tempco.
100kn
v- O----I'o/V'----{) v+
4701d1
I
"
OAe-01
CAPACITIVE LOADS
When driving capacitive loads greater than 50pF in Unipolar
mode or 30pF in Bipolar mode a 100pF capacitor may be
placed from pin 11 to ground for added stability.
ADDITION OF 7th BIT
-15Vo-~-------,
100kS)
IN4148
LOWER RESOLUTION APPLICATIONS
When less than 6 bits of resolution is required, connect
unused bits to a voltage level greater than +2.0 volts. The +5
volt logic supply is adequate.
27MH
I
MSB
~ ~T AL
INPUT
o---r------'
LSB
11-13
1/86, Rev. A
III
])1lC-02/])1lC-03/])1lC-05
lO-BIT-PLUS-SIGN VOLTAGE-OUTPUT
D/A CONVERTERS
Precision Monolithics Inc.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
tage reference, current steering logic, current sources, R-2R
resistor network, logic-controlled polarity switch, and high
speed internally-compensated output op amp. Monotonicity
guaranteed over the entire temperature range is achieved
using an untrimmed diffused R-2R resistor network. The buffered reference input is capable of tracking over a wide range
of voltages, increasing application flexibility. The wide power
supply range, low power consumption, wide logic input
compatibility and sign-magnitude coding assures utility in a
wide range of applications including CRT displays, data
acquisition systems, A/D converters, servo positioning controls, and audio digitizing/reconstruction systems.
Complete ........... Includes Reference and Op Amp
Compact .................. Single 18-Pln DIP Package
Bipolar Output . . . . . . .. (± 10V) Sign-Magnitude Coding
DAC-03 - Unipolar Only; ............... +5V or +10V
Monotonlclty Guaranteed
Nonlinearity ................................. ± 1 LSB
Fast .............................. 2.0JLs Settling Time
Stable.................. Full-Scale Tempco 60ppm/o C
Low Power Consumption ................ 300mW Max
TTL, CMOS Compatible Inputs
MIL-STD-883 Class B Processing Available on DAC-05
ORDERING INFORMATION
MONOTONOCITY
BITS
10
9
8
7
The DAC-03 is similar in construction to the DAC-02/DAC-05
except for a unipolar only output. This device is intended for
low cost, limited temperature range applications, with the
same general specifications as its premium counterparts.
t
PACKAGE: la-PIN HERMETIC DIP
MILITARY
TEMp·
DAC05AX
DAC05CX
COMMERCIAL TEMP
DAC02ACX
DAC02BCX
DAC02CCX
DAC02DDX
PIN CONNECTIONS
DAC03ADX DAC05EX
DAC03BDX
DAC03CDX DAC05GX
DAC03DDX
• For devices processed in total compliance to MIL-STD-883, add /883 after
part number. Consult factory for 883 data sheet.
t All commercial and Industrral temperature range parts are available with
burn-in. For ordering Information see 1986 Data Book, Section 2,
18-PIN DIP
(X-Suffix)
GENERAL DESCRIPTION
The DAC-02 and DAC-05 are complete 10-bit plus sign D/A
converters on a single monolithic chip. All elements of a
complete sign-magnitude DAC are included; precision vol-
SIMPLIFIED SCHEMATIC
~---------OIGITAL LOGICINPUTS--------~
BIT 2
~~~~~iN.~,~,~r<:ID-IT--t---t--f__-+_-+_-+-+--+-___j--t_-_t_-~-~
> __
ANALOG
t-t--<,OUTPUT
ANALOG GROUND
11-14
1/86, Rev. A
-------------
--
_ _ _ _ _ _-I~ DAC-02IDAC-03/DAC-05 10-BIT-PLUS-SIGN VOLTAGE-OUTPUT D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
(Note)
Lead Temperature (Soldering, 60 sec) ............ 300·C
Output Short Circuit Duration ••••••••••••••••• Indefinite
(Short circuit may be to ground or either supply.)
NOTE: For ambIent temperatures above 100' C derate 100mW/' C.
Operating Temperature Range
DAC-05A, C •••••••••••••••••••••••• -55· C to + 125· C
DAC-02 and DAC-03, All
DAC-05E, G •••••••••••••••••••••.•••••• O· C to + 70· C
Storage Temperature Range
-65·C to +150·C
V+ Supply to Analog Ground •.••••••••••••••• Oto+18V
V- Supply to Analog Ground ••••••••••••••••••
to -18V
Analog Ground to Digital Ground
Oto ±0.5V
..........
............
OUTPUT VOLTAGE RANGE SELECTION TABLE
PRODUCT
OUTPUT
VOLTAGE
RANGE
ADD AS
SUFFIX TO
PART NO.
DAC02
DAC03
DAC03
DAC05
±10V
01o+10V
010 +5V
±10V
1
1
2
1
o
Logic Inputs to Digital Ground •••••••• -5V to (V + -0.7V)
Internal Reference Output Current •••••••••••••.• 300l'A
Reference Input Voltage •••••••••••••••••••••• Oto +10V
Internal Power Dissipation •••••••••••••••••••••• 500mW
=
ELECTRICAL CHARACTERISTICS at Vs ± 15V, 0:,; TA :,; + 70· C for DAC-02 and DAC-05E & G, TA
and -55 :,; TA:'; + 125· C for DAC-05A & C, unless otherwise noted.
PARAMETER
SYMBOL CONDITIONS
DAC-02
DAC-D3
DAC-OS
AC
BC
CC
DO
AD
BD
CD
DO
AlE
AC/BC
CC
DO
AD/BD
CD
DO
Monotonoclty
Nonlinearity
NL
C/G
MIN
= 25· C
AC/BC/CC
Full-Scale Tempco
EtG
C
DO
ALL
EXT REF
Settling Time
Full Range Output
Voltage (Note 1)
Zero-Scale Offset
ts
To 112 LSB. 10V Step (Note 4)
ALL
VFR
VFR+ (SB High)
VFA- (SB Low)
DAC-03+10V
+5V
ALL
ALL
Vzs
Full Range BIpolar Symmetry
Vzss
VFRS
ALL
±01
±02
±04
±0.5
% FS
±60
±60
±45 ±100
±60 ±120
±150
ppm/'C
±30
±40
ppm/'C
ALL
ALL
SB High. All other logIc
Inputs low. TA = 25'C
±5
±10
±10
mV
ALL
±2
±10
mV
±5
±10
±10
mV
ALL
±1
±1
±4
±30
±30
±60
±80
mV
±20
±10
±70
±50
mV
mV
ALL
ALL
(Note 2)
VFR+-IVFR-I
(Note 3)
AC/BC/CC
DO
AC/BC/CC
DO
N/A
N/A
ALL
ALL
TA = Min or Max
TA=25'C
Reference Input Bias Current
±1
±1
±5
ALL
I.
ALL
ALL
ALL
100
nA
Reference Input Impedance
Z,N
ALL
ALL
ALL
200
MO
Reference Input Slew Rate
SR
ALL
ALL
EtG
AlC
1.5
V/p.$
Reference Output Voltage
VREF
ALL
ALL
ALL
6.7
Volts
11-15
U
()
0
~
~
......
......
Q
Volts
-
0
C)
+11.5
-10
+115
+5.75
ALL
+10
-11.5
+10
+5.00
~
~
0
f;<
,."
ALL
ALL
ALL
TA = Min or Max
Zero-Scale Symmetry
ALL
ALL
UNITS
BIts
AlE
A
Tc
MAX
10
9
8
ALL
for DAC-03
Z
TYP
C/G
INTREF
~
~
1/86, Rev. A
I
-------I!EMD
DA~2IDAC_o3IDAC_o510-BIT-PLUS-SIGN VOLTAGE-OUTPUT DlA CONVERTER
ELECTRICAL CHARACTERISTICS at Vs =± 15V, 0 ~ TA ~ + 70° C for DAC-02 and DAC-05E & G, TA = 25° C for DAC-03
and -55 ~ TA~ +125°C for DAC-05A & C, unless otherwise noted. (Continued)
PARAMETER
SYMBOL CONDITIONS
liN
Logic Input 0
Logic Input 1
V,NL
V,NH
Positive Supply Current
1+
SB High. All other
logiC Inputs low.
Negative Supply Current
1-
SB High. All other
logic Inputs low
Vs= ±12 to ±18V
Power Supply Sensitivity
Pss
Power DisSipation
Pd
DAC-02
DAC-03
DAC-D5
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
AC/BC/CC
DD
ALL
Each input
-5V to IV+ - 0.7)V
Logic Input Current
AC/BC/CC
DD
10
ALL
ALL
Guaranteed by VFR test
ALL
0.8
2
-10
-9
-9 -11.6
ALL
TA = Min to Max
Output Drive Current
/loA
ALL
ALL
T A =25·C
NOTES:
1. Reference output termonal connected directly to reference Inputterminal.
RL = 2kO for 10V devices. RL = lkO for 5V devices. all logic inputs"2.0V
2. Zero-scale symmetry Is the change in the output voltage produced by
swltchong the sign-bit with all logic bits low IVzs+ - Vzs-).
UNITS
±10
+7
+10
+7 +11.6
ALL
ALL
AC/BC/CC
DD
MAX
±1
Volts
mA
mA
-10 -11.6
TA = Min to Max
T A =25·C
10UT= 0
TVP
ALL
ALL
AC/BClCC
DD
MIN
ALL
ALL
- ±0.Q15 ±0.05
-±0.015 ±01
±0.05 ±01
± 02 ±.05
225
225
200
250
% VFsIV
300
350
300
350
mW
5
mA
3. Full-scale bipolar symmetry is the magnitude of the difference between
VFR+and IVFR-I.
4. Guaranteed by design.
BURN·IN TEST CIRCUIT
-IBV±O.5V
+IBV±O.5V
10
NOTE:
PINS 14. 15. III 17 MUST NOT BE CONNECTED TO
A COMMON BUS BETWEEN DEVICES.
11-16
1/86, Rev. A
-------tlfMI>
DAC-02/DAC-03/DAC·0510·BIT·PLUS·SIGN VOLTAGE·OUTPUT D/A CONVERTER
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
6.
7.
8.
9.
BIT 1·MSB
BIT2
BIT3
BIT4
BITS
BIT6
BIT7
BIT8
BIT9
10.
11.
12.
13.
14.
15.
16.
17.
18.
BIT 10
DIGITAL GROUND
VANALOG GROUND
ANALOG OUTPUT
REF IN
V+
REF OUT
SIGN BIT
For additional DICE information refer to
1986 Data Book, Section 2.
NOTE:
Voltage output range programmable by connecting
'(10VI to analog output for 10 volt range. Jumps from
"(5VI to analog output for 5 volt range t Bits 11 & 12 (not
normally used)
DIE SIZE 0.163 X 0.090 Inch; 14,670 sq. mils
(4.14 X 2.286 mm, 9.464 sq. mm)
WAFER TEST LIMITS at Vs = ± 15V, TA = 25° C and +10V full-scale output, unless otherwise noted.
PARAMETER
CONDITIONS
Resolution
(Bits 11 and 12
Not Normally Used I
Bipolar Output
Unipolar Output
Monotonicity
Nonlinearity
DAC-02-N
DAC·02-G
LIMIT
LIMIT
UNITS
13
12
13
12
Bits MAX
9
S
Bits MIN
±01
±02
% FS MAX
±10
±10
mVMAX
mVMAX
Zero-Scale Offset
Sign Bit High, All Other
Inputs Low
Zero-Scale Symmetry
± 10V Full-Scale
±5
±5
Full-Scale Bipolar Symmetry
± 10V Full-Scale
±60
±60
mVMAX
Power Supply Rejection
Vs =±12Vto±1SV
005
005
'I, VFriV MAX
Power Dissipation
300
300
mWMAX
Lagle Input "0"
OS
OS
V MAX
±11.5
±10
±11.5
±10
V MAX
VMIN
Lagle Input "1"
Full Range
Output Voltage
VMIN
Sign-Bit
High or Low
NOTE:
Electncal tests are performed at wafer probe to the limits shown. Due to vanatlons In assembly methods and normal Yield loss, Yield after packaging IS not
guaranteed for standard product dice Consult factory to negotiate speCifications based on dice lot qualification through sample lot assembly and testing
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ± 15V and + 10V full-scale output, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Full-Scale Tempeo
Internai Reference
Settling Time ITA = 25° CI
To ±1/2 LSB 10 Volt Step
DAC-02-N
DAC·02·G
TYPICAL
TYPICAL
UNITS
60
60
ppmfOC
2
I'S
Logic Input Current
NOTE:
When ordering DICE In this series, use DAC-02 numbers and grades above
11·17
1/86, Rev. A
I
_ _ _ _ _ _--I~ DAC-ii2iDAC-03iDAC-iiS iO-BIT-PLUS-SIGN VOLTAGE-OUTPUT D/A CONVERTER
TYPICAL APPLICATIONS
will be obtained if a low tempco resistor is used or if pot and
resistor tempcos match. Alternatively, a single pot of ::;72kO
may be used.
The DAC-02's, DAC-03's and DAC-OS's logic input stages
require about 1J.LA and are capable of operation with inputs
between -S volts and V+ less 0.7 volt. This wide input voltage
range allows direct CMOS interfacing in most applications,
the exception being where the CMOS logic and D/A converter
must use the same positive power supply.
REFERENCE INPUT BYPASS
Lowest noise and fastest settling operation will be obtained
by bypassing the reference input to analog ground with a
0.01 J.LF disk capacitor.
In this special case, a diode should be placed in series with
the CMOS driving device's Voolead as shown in Figure 1. The
diode limits Vo to V+ less 0.7 volt - since the output from the
CMOS device cannot exceed this value, the DAC's maximum
input voltage rule is satisfied. Summarizing: in all applications, the DAC-02, DAC-03 and DAC-OS require either no
interfacing components, or at most a single inexpensive
diode for full CMOS compatibility.
GROUNDING
For optimum noise rejection, separate digital and analog
grounds have been brought out. Best results will be obtained
if these grounds are connected together at one point only,
preferably near the DAC-02, DAC-03 and DAC-OS package,
so that the large digital currents do not flow through the
analog ground path.
CMOS LOGIC INTERFACE CIRCUIT
APPLICATIONS INFORMATION
LOWER RESOLUTION APPLICATIONS
For applications not requiring full 1O-bit resolution, unused
logic inputs should be tied to ground.
v-
v+
UNIPOLAR OPERATION
Operation as a 10-bit straight binary converter may be
implemented by permanently tying the sign-bit to +SV (for
positive full-scale output) or to ground (for negative fullscale output). In the DAC-03 only, Pin 18 unipolar enable is
tied to Pin 17.
VOLTAGE
OUTPUT
INPUTS,;;;; V+ LESS
IN4148
07 VOLTS
POWER SUPPLIES
The DAC-02, DAC-03 and DAC-OS will operate within specifications for power supplies ranging from ± 12Vto ± 18V. Power
supplies should be bypassed near the package with a 0.1J.LF
disk capacitor.
CMOS DR IVING
DEVICE
vSS
CAPACITIVE LOADING
The output operational amplifier provides stable operation
with capacitive loads up to 100pF.
CONNECTION INFORMATION
REFERENCE OUTPUT
For best results, reference output current should not exceed
100J.LA.
FULL-SCALE ADJUSTMENT CIRCUIT
r---
DIGITAL INPUTS
MS'
FULL
SCALE
ADJUST
POT
~
USE WITH EXTERNAL REFERENCES
Positive-polarity external reference voltages referred to
analog ground may be applied to the reference input terminal to improve full-scale tempco, to provide tracking to other
system elements, or to slave a number of DAC-02's, DAC-03's
and DAC-OS's to the reference output of anyone of them.
This reference voltage should be between +SV to +7V for
optimum performance.
SIGN*
LSB BIT V+
~'-O.=,,+-+---f'.
SIGN PLUS MAGNITUDE CODING TABLE
(DAC-02, DAC-03 and DAC-05)
LSB
SIGN-BIT MSB
+ FULL SCALE
+ HALF-SCALE
ZERO-SCALE (+)
ZERO-SCALE (-)
- HALF-SCALE
FULL-SCALE
FULL-SCALE ADJUSTMENT
Full-scale output voltage may be trimmed by use of a potentiometer and series resistor as shown; however, best results
11-18
1
0
0
0
1
0
0 0
0 0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1/86, Rev. A
DAC-06
TWO'S-COMPLEMENT lO-BIT VOLTAGE-OUTPUT
D/A CONVERTER
Precision Monolithics Inc.
FEATURES
•
•
•
•
•
•
•
•
are included - precision voltage reference, current steering
logic, current sources, R-2R resistor network, bipolar offset
circuit and high speed internally compensated output op
amp. Monotonicity guaranteed over the entire operating
temperature range is achieved using an untrimmed diffused
R-2R resistor network. The buffered reference Input is
capable of tracking over a wide range of voltages, increasing
application flexibility. The user may also easily implement
one's complement, straight offset binary, or unipolar operation. The ±12V to ±18V power supply range, low power
consumption, TTL and CMOS compatibility, wide logic input
compatibility and adaptable logic coding capability assure
utility in a wide range of applications.
Complete ............. Includes Reference and Op Amp
Compact ...............•... Single 18-Pln DIP Package
Bipolar Output ..........•.. Two's Complement Coding
Monotoniclty Guaranteed
Nonlinearity.................................. ± 1 LSB
Fast •..............•........•..... 1.51's Settling Time
Low Power Consumption ................• 300mW Max
TTL, CMOS Compatible Inputs
ORDERING INFORMATIONt
MONOTONICITY
BITS
10
9
B
PACKAGE 18-PIN HERMETIC DIP
MILITARY
TEMP
COMMERCIAL
TEMP
PIN CONNECTIONS
DAC-OBEX
CAC-06BX'
CAC-06CX'
CAC-06FX
CAC-06GX
18
• For devices processed In total compliance to MIL-STD-BB3, add IBB3 after
part number Consult factory for BB3 data sheet.
tAli commercial and Industrial temperature range parts are available with
burn·1n For ordertng information see 1986 Data Book, Section 2
BIT 7
7
BIPOLAR ADJUST
17
REFERENCE OUTPUT
16
POSITIVE POWER SUPPLY
16
REFERENCE INPUT
14
ANALOG OUTPUT
13
ANALOG GROUND
12
NEGATIVE POWER SUPPLY
11
DIGITAL GROUND
GENERAL DESCRIPTION
The DAC-06 is a complete 10-bit two's complement DlA
converter on a Single 90 x 163 mil monolithic chip. All elements of a complete bipolar output two's complement DAC
18-PIN DIP (X-SUFFIX)
I
SIMPLIFIED SCHEMATIC
, " - - - - - - - O I G I T A L LOGIC INPUTS -------~\
SIGN
BIT
1
REF
BIT
2
2
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
V+
BIPOLAR
,.
345678910ADJUST
3
4
5
6
7
8
9
10
18
+-__4-__~__-+____~__+-__4-__~__-+__~~__~~__~
OUTPU~T~~-{O~~~~~~~__
REF
INPUTo-+--+_~
,.
DIGITAL
GNO
~l1~~1---------+-~~~~~-+~-+~--~--~--~~-++--+~--h
ANALOG
OUTPUT
>--H"",.'"
13
12
ANALOG GROUND
V-
1/86, Rev. A
11-19
---~--
--------
----
--------I~ DAC-iiii TWO'S-COMPLEMENT 10-BIT VOLTAGE-OUTPUT D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
DAC-OSB, C ......................... -55°C to +125°C
DAC-OSE, F, G .......................... 0° C to + 70° C
DICE Junction Temperature (TJ) ••••••••• -S5°C to +150°C
Storage Temperature Range ••••••.•••••• -S5°C to +150°C
V+ Supply to Analog Ground ................... 0 to +18V
V- Supply to Analog Ground .................... 0 to -18V
Analog Ground to Digital Ground ••••••••••••••• 0 to ±0.5V
ELECTRICAL CHARACTERISTICS at
DAC-OSE, F & G, unless otherwise noted.
PARAMETER
SYMBOL
Vs
=
Logic Inputs to Digital Ground •• , •••••• " -5V to (V+ -0.7)V
Internal Reference Output Current ••••••••••••••••• 3ool'A
Reference Input Voltage ... • • • • .. • • .. .. .. .. .. ... 0 to + 10V
Bipolar Offset Input Voltage .................... 0 to +10V
Internal Power DisSipation ••••••••••••••••••••••• 500mW
Lead Temperature (Soldering, SO sec) •••••••••••••• 300°C
Output Short-Circuit Duration ••••••••••••••••••• Indefinite
(Short circuit may be to ground or either supply)
±15V; -55°C S TA S +125°C for DAC-OSB
CONDITIONS
DAC-08
Resolution
Monotonlcity
Nonlinearity
Full-Scale Tempco
ts
10
E
BIF
CIG
10
TYP
MAX
UNITS
Bits
Bits
E
BIF
CIG
±O.I
±0.2
±0.4
% FS
TA = Full Temp.
E
BIF
CIG
±0.2
±0.3
±0.5
% FS
Total Internal
Ref Con nected
Zero Drift Ext
Ref Applied
Settling Time
MIN
All
and O°C S TA S +70°C for
TA= 25'C
NL
TC'JFS
& C;
B
ElF/G
C
±45
±45
±60
All
±30
To ± 112 LSB. 10V Step
All
1.5
Short Pin 18 to
TA =25'C
All
±I
Ground I Note I I
TA = Full Temp.
All
±90
±IOO
±120
ppml'C
ppml'C
p.s
±5
mV
Unipolar Zero-Scale Output
Vzs
±IO
mV
Bipolar Offset Voltage
BPOff
Connect Pins 15. 17 & 18 INote 31
All
-5
+2.5
% Range
Full Range Output Voltage
VFR
Connect Pin 15 to 17 I Note 21
RL = 2kll
All
10
11.5
V
±2
Reference Input Bias Current
I.
All
100
nA
Reference Input Impedance
Z,N
All
200
Mil
Reference Input Slew Rate
SR
All
1.5
VII's
Reference Output Voltage
VREF
All
6.7
Logic I nput Current
liN
Logic Input "0"
Logic I nput "I"
Power Supply Sensitivity
Pss
Supply Current
10
V,NL
All
0.8
V,NH
All
1+
V
V
±0.02
±0.05
% FSN
All
±0.02
±O.I
%FSN
10
mA
All
-9
-10
mA
TA = 25'C
All
250
300
mW
TA = Full Temp.
All
350
mW
All
TA=25'C
Po
,..A
All
Vs =±12Vto±18V TA=25'C
TA = Full Temp.
1Power DiSSipation
V
All
Each Input -5V to IV+ -0.7IV
NOTES:
1. May be operated in the 0 to + 10V unipolar mode by shorting Pin 18 to
Ground.
2. VFR = IVFR+I + IVFR-Iand istrimmabletoexactly 10Vrangewith the circuit
shown in typical applications.
3. Bipolar offset voltage is trimmable to exact two's or one's complement
condition with the circuit shown in typical applications.
11-20
1/86, Rev. A
--------l!EMD
DAC-Oe TWO'S-COMPLEMENT 10-BIT VOLTAGE-OUTPUT D/A CONVERTER
TYPICAL APPLICATIONS
ADJUSTING FOR TWO'S COMPLEMENT CODING
1. Connect Full-Scale Adjust and Bipolar Adjust Circuitry as
shown In figure.
REFERENCE OUTPUT
For best results, reference output current should not exceed
1001LA.
2. Turn all bits OFF (VFs--1 LSB) = 1000000000
3. Adjust Bipolar Pot for VFS at output ............ -5.000V
POWER SUPPLIES
The DAC-OS will operate within specifications for power
supplies ranging from ± 12V to ± 18V. Power supplies should
be bypassed near the package with a 0.11LF disk capacitor.
Chip users should connect the substrate to V-.
4. Turn all bits ON (VFR+) = 0111111111
5. Adjust Full-Scale Pot for desired
VFR+ value ................................... +4.990V
S. Check Zero-Scale Reading (Vzs) = 0000000000
If this reading Is outside desired Vzs range, readjust BIpolar Pot until the output reads O.OOOOV.
GROUNDING
For optimum noise rejection, separate digital and analog
grounds have been brought out. Best results will be obtained
if these grounds are connected together at one point only,
preferably at the DAC-OS package, so that large digital
currents do not flow through the analog ground path.
TWO'S COMPLEMENT CODING TABLE
INPUT
MSB
LSB
IDEAL
OUTPUT
+4.990V
VFS+ -1 LSB
0 1 1
1
0
VFS+-2LSB
0 1 1 1 1
+1LSB
0 0 0 0 0 0 0 0 0
Zero
0 0 0 0 0 0 0 0 0 0
CAPACITIVE LOADING
The output operational amplifier provides stable operation
with capacitive loads up to 100pF.
+4.980V
+0.010V
FULL-SCALE OUTPUT RANGE AND
BIPOLAR OFFSET ADJUSTMENT CIRCUIT
O.OOOV
-1LSB
1 1 1 1 1 1
-0.010V
VFs-+1LSB
0 0 0 0 0 0 0 0 1
-4.990V
VFS-
0 0 0 0 0 0 0 0 0
-5.000V
;----DIGITAL INPUTS ~
MSB
Lse
V+
ADJUSTING FOR ONE'S COMPLEMENT CODING
1. Connect Full-Scale Adjust and Bipolar Adjust Circuitry as
shown in above figure.
2. Turn all bits OFF (VFR-) = 1000000000
ANALOG
I
13
GNO*u
3. Adjust Bipolar Pot for VFR- at output .......... -5.0000V
4. Turn all bits ON (VFR+) = 0111111111
5. Adjust Full-Scale Pot for desired
VFR+value .................................. +5.0000V
·SEE APPLICATION NOTES FOR DETAILS
**Tle TO GROUND FOR UNIPOLAR OPERATION
"*GROUNDING - FOR OPTIMUM NOISE REJECTION, SEPARATE DIGITAL AND ANALOG GROUNDS HAVE BEEN BROUGHT
OUT BEST AESUL T5 WILL BE OBTAINED
ONE'S COMPLEMENT CODING TABLE
INPUT
MSB
LSB
IDEAL
OUTPUT
VFS+ -1 LSB
0
1
+5.000V
VFs+-2LSB
0
0
+4.990V
+0
0 0 0 0 0 0 0 0 0 0
+0.005V
-0
1 1 1 1 1 1 1 1 1
-0.005V
VFs-+2LSB
0 0 0 0 0 0 0 0 1
-4.990V
VFs-+1LSB
0 0 0 0 0 0 0 0 0
-5.000V
IF THESE GROUNDS ARE CONNECTED
TOGETHER AT ONE POINT ONLY, PREFERABLY NEAR OAe-OS PACKAGE, so THAT
THE LARGE DIGITAL CURRENTS 00 NOT
FLOW THROUGH THE ANALOG GROUND
PATH
EXTERNAL ADJUSTMENT NETWORK
Full-scale output range and bipolar offset may be adjusted
by using the circuit shown in the figure above. Best results
will be obtained when low tempco pots and resistors are
used, or if pot and resistor tempcos match.
Note that two zero states will straddle (±1/2 LSB) the true zero. Therefore the
DAC will give symmetrical outputs for both positive and negative full-scale.
11-21
1/86, Rev_ A
---------I~ DAC-06 TWO'S-COMPLEMENT 10-BIT VOLTAGE-OUTPUT D/A CONVERTER
CODE CONVERSION TO OFFSET BINARY
Offset binary coding is exactly the same as two's complement
coding except that the most significant bit occurs in true,
ratherthan inverted form and the output states are relabeled.
To convert the DAC-06 to offset binary code operation,
simply place a logic inverter in series with the MSB input
(Pin 1) and invert the MSB value shown in steps 2,4 and 6 of
the two's complement adjustment procedure shown above.
the CMOS logic and D/A converter must use the same
positive power supply.
In this special case, a diode should be placed in series with
the CMOS driving device's Voolead as shown in Figure 1. The
diode limits Vo to V+ less 0.7 volt - since the output from the
CMOS device cannot exceed this value, the DAC's maximum
input voltage rule is satisfied. Summarizing: in all applications, the DAC"06 requires either no interfacing components,
or at most a single inexpensive diode for full CMOS
compatibility.
OFFSET BINARY CODING TABLE
INPUT
MSB
LSB
IDEAL
OUTPUT
1
+4.990V
1 0
+4.980V
VFS+ -1LSB
VFs+-2LSB
1 1 1 1 1 1
ZERO
0 0 0 0 0 0 0 0 0
v-
v+
VOLTAGE
0.00
-1LSB
0 1
1 1 1
-0.005V
VFS-+1LSB
0 0 0 0 0 0 0 0 0
-4.990V
VFS-
0 0 0 0 0 0 0 0 0 0
-5.000V
1
CMOS LOGIC INTERFACE CIRCUIT
OUTPUT
INPUTS';;'; V+ LESS
07 VOLTS
IN4148
INTERFACING WITH CMOS LOGIC
CMOS DR IVING
DEVICE
The DAC-0610gic input stages require about 11'A and are
capable of operation with inputs between -5 volts and V+ less
0.7 volt. This wide input voltage range allows direct CMOS
interfacing in most applications, the exception being where
vss
11-22
1/86, Rev. A
DAC-08
8-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
(UNIVERSAL DIGITAL LOGIC INTERFACE)
Pn:ClSlOll MOl1olithlcs Inc.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
interface to all popular logic families with full noise immunity
is provided by the high swing, adjustable threshold logic
input.
Fait Sattllng Output Current ..................... 85nl
Full-Scale Current Prematched to ± 1 LSB
Direct Interface to TTL, CMOS, ECL, HTL, PMOS
Nonlinearity to ,0.1% Maximum Over Temperature Range
High Output Impedance and
Compliance ....................••..•.. -10V to +18V
Complementary Current Outputl
Wide Range Multiplying Capability ..• 1MHz Bandwidth
Low FS Current Drift ......•.••..••.•...•• ±10ppm/oC
Wide Power Supply Range •••..•..•.•. ±4.5V to ±18V
Low Power Conlumptlon •...•.......... 33mW @ ±5V
Low COlt
High voltage compliance complementary current outputs are
provided, increasing versatility and enabling differential
operation to effectively double the peak-to-peak output
swing. In many applications, the outputs can be directly
converted to voltage without the need for an external op amp.
All DAC-08 series models guarantee full8-bit monotonicity,
and nonlinearities as tight as ±0.1 % over the entire operating
temperature range are available. Device performance is
essentially unchanged over the ±4.5 to ± 18V power supply
range, with 33mW power consumption attainable at ±5V
supplies.
GENERAL DESCRIPTION
The DAC-08 series of 8-bit monolithic digital-to-analog
converters provide very high-speed performance coupled
with low cost and outstanding applications flexibility.
The compact size and low power consumption make the
DAC-08 attractive for portable and military/aerospace applications; devices processed to MIL-STD-883, Level Bare
available.
Advanced circuit design achieves 85ns settling times with
very low "glitch" energy and at low power consumption.
Monotonic multiplying performance is attained over a wide
20 to 1 reference current range. Matching to within 1 LSB
between reference and full-scale currents eliminates the
need for full-scale trimming in most applications. Direct
DAC-08 applications include 8-bit, 1~s AID converters, servo
motor and pen drivers, waveform generators, audio encoders
and attenuators, analog meter drivers, programmable power
supplies, CRT display drivers, high-speed modems and other
applications where low cost, high speed and complete input!
output versatility are required.
EQUIVALENT CIRCUIT
I
4'" lOUT
2
... -
lOUT
VREF {o-+)--'-'14'+-_.--+-------,
1st-_--II .......
VREF {-o-)--'-'
11-23
----
- ------------
1/86, Rev. A
-----------tlfMD
DAc-oa a-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
Logic Inputs ••••••••••••••••••••••••• V- to V- plus 36V
VLC ••••••••••••••••••••••.•••••••••••••••••••• V-to V+
Analog Current Outputs (at Vs- = 15V) ••••••••••• 4.25mA
° ......................
°
DAC-OBAO,
-55°C to +125°C
DAC-OBHO, EO, CO, HP, EP, CP •••••••• O°C to +70°C
DICE Junction Temperature (Ti) ••••••• -65°C to +150°C
Storage Temperature
Package •••••••• -65° C to 150° C
Storage Temperature P Package ••••••• -65° C to + 125° C
Power Dissipation
• • • • • • • • • • • • • • • • • • • • • • • • • . • •• 500mW
Derate above 100°C •••••••••••••••••••••••• 10mW/oC
Lead Temperature (Soldering, 60 sec) ••••••••••••• 300°C
V+ Supply to V- Supply.. • • • • • • • • • • • • ••• •• . • •• • • • •• 36V
ELECTRICAL CHARACTERISTICS at Vs =
+ 70° C for DAC-OBC, E
Reference Input (V14 to VIS) •••••••••••••••••••• V- to V+
Reference Input Differential Voltage
(V14 to VIS) ••••••••••••••••••••••••••••••••••••• ±1BV
Reference Input Current (114) ••••••••••••••••••••• 5.0mA
NOTE: Absolute ratings apply to both DICE and packaged parts, unless
otherwise noted.
±15V, IREF= 2.0mA, -55°C::> TA::> +125°C for DAC-OB/OBA, O°C::> TA::>
& H, unless otherwise noted. Output characteristics refer to both lOUT and lOUT.
DAC-08A/H
PARAMETER
SYMBOL
CONDITIONS
MIN
Resolution
8
Monotonlclty
8
TVP
MIN
TVP
MIN
TVP
MAX
UNITS
Bits
±0.1
ts
DAC-08C
MAX
Bits
Nonlinearity
Settling Time
DAC-08/E
MAX
±0.19
±0.39
%FS
To ± 1/2 LSB. all bits switched
ON or OFF. TA=25"C. (Note)
85
135
85
150
85
150
ns
TA =25"C
(Note)
35
35
80
80
35
35
80
80
35
35
80
80
ns
±10
±50
±10
±80
±50
±10
±80
Propagation Delay
Each bit
All bits swltchsd
Full-Scale Tempco
(Note)
tpLH
tpHL
TCI FS
Output Voltage Compliance
(True Compliance)
DAC-D8E
Full-Scale current change
Vee
< 1/2
'FR4
VREF = 10.000V
R'4' R,s = 5.0ookO
TA = +25"C
Full Range Symmetry
'FRS
IFR4 -I FR2
Zero-Scale Current
Izs
Full Range Current
lOR,
Output Current Range
IOR 2
Output Current Noise
LSB. ROUT> 2OMO typical
-10
1.984
+18
-10
1992
2.000
1.94
±0.5
±4
01
R'4' R,s =5.0001<0
VREF=+15.0V. V-=-10V
VREF = +25 OV, V-=-12V
+18
-10
1.99
2.04
1.94
±1
±8
02
+18
Volts
1.99
2.04
mA
±2
±16
pA
pA
0.2
21
2.1
2.1
4.2
4.2
4.2
ppm/"C
mA
25
'REF =2mA
25
25
nA
Logic Input Levels
Logic "0"
LogiC Input "1"
VIL
V,L
0.6
VLC=OV
LogiC "a"
Logic Input "I"
'lL
'IH
VLC=OV
VIN = -10V to +0.8V
Y,N = 2.0V to 18V
Logic Input Current
-2
0.002
0.8
-10
10
-2
0.002
0.8
-10
10
-2
0.002
VOlts
-10
10
pA
LogiC Input Swing
VIS
V-=-15V
-10
+16
-10
+18
-10
+18
Volts
LogiC Threshold Range
VTHR
Vs = ±15V. (Note)
-10
+13.5
-10
+135
-10
+135
Volts
Reference Bias Current
I,.
-3
pA
Reference Input Slew Rate
Power Supply Sensitivity
dl/dt
PSSI FS+
PSSIFS-
-1
REa =2oo0
RL = 1000
Cc=OpF
-3
-1
-3
-1
See fa.t pulsed
4
ref. info.
mAl",s
follOWing (Note)
V+ = 4.5V to 18V
V- = -4 5V to -IBV
'REF= lamA
-±0.0003
- ±0002
±0.01
±0.01
-±0.0003
- ±0.OO2
±001
±OOI
-±O 0003
- ±O002
±0.01 %<1la/%<1V+
±O.OI %41a1'1b<1V-
NOTE: Guaranteed by design
11·24
1/86, Rev. A
----------I~ DAc-oa a-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
ELECTRICAL CHARACTERISTICS at Vs = ±15V, IREF= 2.0mA, -55°C:::; TA:::; +125°C for DAC-08/0BA, O°C:::; T A :::;
+ 70° C for DAC-OBC, E & H, unless otherwise noted. Output characteristics refer to both lOUT and lOUT. (Continued)
DAC-OSA/H
PARAMETER
Power Supply Current
MIN
MAX
MAX
23
-4.3
TYP
MAX
3.8
-58
23
-4.3
38
-58
23
-43
38
-58
+5V. -15V. 'REF ~ 2 OmA
24
-64
3.8
-7.8
24
-6.4
3.8
-78
2.4
-6.4
3.8
-78
±15V, IREF ~ 2 OmA
2.5
-6.5
38
-78
25
-65
3.8
-78
2.5
-6.5
38
-78
= 10mA
33
lOB
48
33
4B
136
33
103
48
+5V. -15V, IREF ~ 2 OmA
136
±15V, IREF = 2.0mA
135
174
135
174
108
135
136
174
1+
1-
Vs = ±5V, IREF = 1 OmA
1+
11+
Vs
~
Vs
~
±5V, IREF
Pd
MIN
DAC-OSC
TYP
CONDITIONS
1-
Power DISSipation
DAC-OS/E
TYP
SYMBOL
MIN
UNITS
mA
mW
NOTE: Guaranteed by deSign.
ORDERING INFORMATIONt
PIN CONNECTIONS
16-PIN DUAL-IN-LINE PACKAGE
NL
OPERATING
TEMPERATURE
RANGE
HERMETIC
PLASTIC
01%
DACOSAO'
DACOSHO
DACOSHP
019%
DACOSO'
DACOSEO
DACOSEP
COM
039%
DACOSCO
DACOSCP
COM
LCC
MIL
COM
DACOSRC/SS3
MIL
For deVices processed In total compliance to M IL-STO-883, add /883 after
part number Consult factory for 883 data sheet
tAil commercial and industrial temperature range parts are available with
burn-In For ordenng information see 1986 Data Book, Section 2
*
16-PIN DUAL-IN-LiNE
PACKAGE
DAC-OBRC/SB3
20-LEAD LCC
(Re-Suffix)
I
11-25
1/86, Rev. A
-----------l~ D.C-08 8-BIT HIGH-SPEED MULTIPLYING OJ. CONVERTER
DICE CHARACTERISTICS
(125°C TESTED DICE AVAILABLE)
1. VLC
9.
10.
11.
12.
13.
14.
15.
16.
2. lOUT
3. V4.
5.
6.
7.
8.
DIE SIZE 0.085 X 0.062 Inch, 5,270 sq. mils
(2.159 X 1.575 mm, 3.4 sq. mm)
lOUT
BIT 1 (MSB)
BIT2
BIT3
BIT4
BIT5
BIT6
BIT 7
BIT 8 (lSB)
V+
VREF (+)
V REF (-)
COMP
For additional DICE information refer to
1986 Dala Book, Section 2.
WAFER TEST LIMITS at Vs = ±15V. IREF = 2.0mA, TA = 125° C for DAC-OSNT, DAC-OSGT devices; TA = 25°C for
DAC-OSG and DAC-OSGR devices, unless otherwise noted. Output characteristics apply to both lOUT and lOUT.
PARAMETER
DAC-OSNT
LIMIT
DAC-OSN
LIMIT
DAC-OSGT
LIMIT
8
8
8
8
8
8
8
Bits MIN
±Ol
±O.I
±0.19
±0.19
±0.39
%FSMAX
Full-Scale Current
Change < 112 LSB
+18
-10
+18
-10
+18
-10
+18
-10
+18
-10
Volts MAX
Volts MIN
VREF = 10.000V
R'4' R,s= 5.000kO
204
1.94
2.04
194
204
1.94
2.04
1.94
2.04
1.94
mAMAX
mAMIN
±8
±8
±8
±8
±16
p.AMAX
4
4
4
p.AMAX
SYMBOL CONDITIONS
Resolution
Monotonicity
Nonlinearity
Output Voltage
Compliance
Full-Scale Current
Vee
'FS4 or
'FS2
Full-Scale Symmetry
I FSS
Zero-Scale Current
I zs
2
DAC-OSG
LIMIT
DAC-OSN.
DAC-OSGR
LIMIT
UNITS
Bits MIN
V-=-IOV,
'FS1 0r
Output Current Range
V AEF
= +15V
V-=-12V,
VREF = +25V
'FS2
R'4' R,s = 5.000kO
2.1
21
2.1
21
2.1
mAMIN
42
42
4.2
4.2
4.2
mAMIN
08
08
08
0.8
V MAX
LogiC Input "0"
V,L
0.8
Logic Input "1"
V,H
2
I'H
VLe = OV
Y,N = -IOV to +0.8V
Y,N = 2.0V to 18V
V's
V-=-15V
Logic Input Current
LogiC "0"
Logic "1"
Logic Input SWing
I,L
Power Supply
Sensitivity
±IO
±10
±10
±IO
±IO
±IO
±IO
±IO
p.AMAX
+18
-10
+18
-10
+18
-10
+18
-10
+18
-10
V MAX
VMIN
-3
-3
-3
-3
-3
p.AMAX
0.01
0.01
001
om
0.01 %FS/%V MAX
Power Supply Current
Vs= ±15V
I REF ,; 2 OmA
3.8
-7.8
3.8
-7.8
3.8
-7.8
38
-78
3.8
-7.8
mAMAX
Power Dissipation
Vs= ±15V
I REF ,; 2.0mA
174
174
174
174
174
mWMAX
1'5
PSSI FS +
PSSI FS _
1+
Pd
VMIN
±10
±IO
Reference Bias
Current
2
V+ = 4.5V to 18V
V-=-45Vto-18V
IREF = I OmA
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
11-26
1/86, Rev. A
-----------l~ DAc-oa a-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
TYPICAL ELECTRICAL CHARACTERISTICS
at
Vs = ±15V,
and IREF =
2.0mA,
unless otherwise noted. Output
characteristics apply to both lOUT and lOUT.
ALL GRADES
PARAMETER
SYMBOL CONDITIONS
Reference Input
Slew Rate
dlldt
Propagation Delay
t pLH , tpHL TA = 25"C, Any Bit
Settling Time
TYPICAL
UNITS
mA/p.s
To ± 1/2 LSB, All Bits
SWitched ON or OFF,
TA =25"C
ts
35
ns
85
ns
NOTE:
For DAC08NT & GT 25"C characteristics, see DAC08N & G characteristics
respectively.
VJ
~
~
~
~
BURN-IN CIRCUIT
PULSED REFERENCE OPERATION
0
\?+VREF
U
C2
l
(OPTIONAL RESISTOR
:::RREF FOR OFFSET INPUTS
RIN
U
0
+18V
1
.....l
REa"" 14
~
......
200n
ovJL..
Rp
TYPICAL VALUES
RIN = SkD.
0
~
+VIN = 10V
OAC·OS
~......
C)
......
FAST PULSED
REFERENCE OPERATION
Q
C3
.0
2SV--
-lav MIN
Rl = 9kD.
Cl =OOOl .. F
C2, C3 = 0 01!1F
a 5V-05mAlOUT
-2 SmA-
REa"" 200n
RL = lOon
Cc
=
200NSEC/DIV1SION
a
TRUE AND COMPLEMENTARY
OUTPUT OPERATION
.
FULL-SCALE SETTLING TIME
LSB SWITCHING
ALL BITS SWITCHED ON
.."
24V-
24VLOGIC INPUT
lOUT
OmA -
1 OOlA'
04VOV-
lOrnA'
8pA0-
I
04V-
I
OUTPUT -1/2LSBSETTLING
0-
!
I
I
lOUT
+1/2LSB-
I
\
~
l(}oW.l
(000010000)
IREF = 2mA
(111111111)
5ONSEC/OIVISION
SETTLING TIME FIXTURE
IFS = ZmA, RL '" lkfl
1/2LSB
11-27
~
..
~.-
~------
50NSEC/OIVISION
= 4j.tA
1/86, Rev. A
-----------11fM!} DAC-08 8-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
FULL-SCALE CURRENT VI
REFERENCE CURRENT
6.0
LSB PROPAGATION
DELAYVIIFS
500
LIMIT fOR
V-C>'6V
TA" TMIN TO TMAX
ALL BITS "HIGH"
'0
8
5.0
I
o
~
is
I
I
0.05
002
0'
0.6
20
10
0.01
0.05
0.2
1,0
5.0
IFS. OUTPUT FULL SCALE CURRENT (mAl
~
cc·
1.
-8
~
1\,
1SpF, VIN ·2.OVp-p
,
~
CENTERED AT +1,OV LARGE
LARGE SIGNAL
CC'" 16pF. VIN '" 60mVp-p
CENTERED AT +200mV
SMALL SIGNAL
0.2
0.5
1,0
~
2.0
5,0
10
FREQUENCY (MHz)
LOGIC INPUT CURRENT VI
INPUT VOLTAGE
ALL BITS ON
~2
0
VTH - VLC VI TEMPERATURE
,00
2.0
80
'.8
TA = TMIN TO TMAX
3.6
:li
I
ov
-2
-'0 2.
-'2
-'4 01
'LSB-mlli
4.0
Cj
~
a:
1LS8-7.~
1\
1,0
2.0
3.0
4.0
'REF, REFERENCE CURRENT (mA)
VRtS"
~-4
t-
REFERENCE AMP
COMMON-MODE RANGE
12.8
.
2
~
LIMIT FOR
3.2
•
~
I!:
v- - -5V
/
iii
:s
1/
1/
R'4= R'6='';'
RL '" 6000
ALL BITS "ON"
400
V
'.0
REFERENCE INPUT
FREQUENCY RESPONSE
t-- Noie.
pcislTlV~ COJMON ~ODE1_
RANGE IS ALWAYS (V+I -'.5V
I I
2.4
V-= -f6V
2.0
I
1.6
II
.""'"
'REF'" 2mA
!
J .1J
'.2
0.8
,
~
20
-14
-10
-8
-2
10
14
18
""5. REFERENCE COMMON MOOE VOLTAGE (VOLTS)
OUTPUT CURRENT VI
OUTPUT VOLTAGE (OUTPUT
VOLTAGE COMPLIANCE)
4.0
ALL SITS ON
3.6
T A'" TMIN TO TMAX
1.2
~
............
r--..
>"
Il
'REF - O~imA
0.4
............
~O.8
40
§'"
,
'REF - 1rnA
I
~0
~ 60
V+ .. +1SV
V---6V
<"
'ffi"
-12.0 -8,0
-40
l
0.4
4.0
80
120
o
'60
LOGIC INPUT VOLTAGE (VOLTS)
OUTPUT VOLTAGE COMPLIANCE
V8 TEMPERATURE
+50
+100
TEMPERATURE (OCI
+'60
BIT TRANSFER
CHARACTERISTICS
+28.0 I " ' " " ' T " - - T " " - - - r - - " ' T " - - T " " '
'.8
NOTE B1 THROUGH lSI
+24.01--+--+_---+--+--+_--1
'.S
CHARACTERISTICS SITS ARE FULLY SWITCHED, WITH
LESS THAN 1/2 LIB ERROR, AT LESS THAN ±100mV
FROM ACTUAL THRESHOLD THESE SWITCHING
HAV~
IDENTICAL TRANSFER
POINTS ARE GUARANTEED TO LIE BETWEEN 0.8 AND
32
20 VOLTS OVER THE OPERATING TEMPERATURE
RANGE IVLe .. OOVI
v- '" -16V
I
II
I~EF
B'
IRE! - 2.0!.,.
'REF" 2mA
V- '" -5V
FOR OTHER V- OR 'REF, SEe
OUTPUT CURRENT VS OUTPUT
l'mA
82
r---r-
VOLTAGE CURVE
I
I
04
-14
-...---1,...,....-+--1
J
0.2
'REF" O.2mA
-10
-6
-2
2
6
10
14
18
v
V
-j
--6V
'sv
-12.0 -8.0 --4.0
B4
85
B3
\
0
4.0
8.0
12.0 16.0
lOGIC INPUT VOLTAGE (VOLTS)
DUPUT VOLTAGE (VOLTS)
11-28
1/86, Rev. A
----------1~ DAc-oa a-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
POWER SUPPLY
CURRENT VB V+
'00
POWER SUPPLY
CURRENT VB V10.0
AL~ Blis "H:GH'·I OR \o~"
9.0
1
8. 0
~ 7.0
r-
1-
~
3.0
~
1+ -
;:
a:
I I I I
'.0
'0
o
o
2.0 4.0 6 a 8.0 10012.0 140 16.0 18.0 20,0
V+, POSITIVE POWER SUPPLY (Vdc)
r- r-- v_I
~ 4.0
a:
~ 3.0
-40
-2.0
-6.0
--80
-12.0
-16.0
-20,0
-10.0
-14.0
-lB.O
r,_- r-
1+-
r-
I
I
'.0
o
+--
r- f---- V+ ~ +15V
.: 2.0
1+
-'5V
I
il:
1- WITH IREF = O.2mA _
=
IREF = 2.0mA
"
:: 5.0
1- WITH 'REF = lmA
~ 30
.: 20
A~L BITS "~'GH" OR I"LOW"
I
I
~ 6.0
4,0
2 20
o
t~ 7.0
1- WITH IREF = 2mA -
~ 5.0
a.. 4.0
18.0
II
7.0
a
ia 5.0
9.0
I I
8. 0
~ 6.0
~ 6.0
i>l
ffi
ffi
10,0
BI~S Mlv B~ "HI~H" ~R "~ow.!
9.0
1
POWER SUPPLY CURRENT
VB TEMPERATURE
o
-50
+50
+100
TEMPERATURE ('Ie)
+150
V-, NEGATIVE POWER SUPPLY (Vdc)
BASIC CONNECTIONS
BASIC POSITIVE REFERENCE OPERATION
ACCOMODATING BIPOLAR REFERENCES
MSB
LSB
81 B2B3 B4 B5 B6 B7 B8
+VREF
RREF
~
VIN-%-
~ 'REF
,.
RIN
RREF
(R14j
R'5
'5
VREF = +10.000V
RREF = 5.000k
R15 = RREF
Cc = O.01,uF
VLC = OV (GROUND)
'REF ~ PEAK NEGATIVE SWING OF liN
+VREF
RREF "" R15
~_
O.'~F
,.
RREF
I
R'5
(OPTIONAL)
VIN~____
_:':Y.B..E..E
15
v-
255
J
V+
VLC
'FR - RREF x""2OG'
10 + TO = IFR FOR
1-_ _ _ _ _ _ _- '
HIGH INPUT
0 l~F
IMPEDANCE
ALL LOGIC STATES
+VREF MUST BE ABOVE PEAK POSITIVE SWING OF VIN
BASIC UNIPOLAR NEGATIVE OPERATION
MSB
Bl
LSB
81 82 8384 85 86 87 88
IREF =
2.000mA
EO
,.
10
2
B2
B3
B4
B5
B6
B7
B8 lemA IOmA
1.992
FULL RANGE
HALF-SCALE +LSB
0
HALF-SCALE
0
HALF-SCALE -LSB
0
ZERO-SCALE + LSB
0
0
ZERO-SCALE
0
0
11-29
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Eo
Eo
0.000
-9.960 - .000
1.008
0.984
-5.040 -4.920
1.000
0.992
-5.000 -4.960
0.992
1.000
-4.960 -5.000
0.008
1.984
-0.040 -9.920
0.000
1992
0.000 -9.960
1/86, Rev. A
II
-----------1~ DAc-oa a-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
BASIC CONNECTIONS
BASIC BIPOLAR OUTPUT OPERATION
11 12 13 14 15 B8 17 18
+10.00OV
MSB
LSB
POS. FULL RANGE -LSB
81 B2 B3 B4 B6 B8 B7 B8
10.000kO
IREF(+I =
10.
,.
2.01lOmA
1O.OOOkn
2
RECOMMENDED FULL-SCALE ADJUSTMENT CIRCUIT
Eo
0 - 9.840 + 9.920
ZERO-SCALE +LSB
0
0
0
0
0
0
1 - 0.080 + 0.180
ZERO-SCALE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
+ 0.080
NEG. FULL-SCALE +LSB
0
0
0
0
0
0
0
+ 9.920 - 9.840
NEG. FULL-SCALE
0
0
0
0
0
0
0
0 + 10.000 - 9.920
ZERO-SCALE -LSB
i0
Eo
1 - 9.920 +10.000
POS. FULL RANGE
0.000 + 0.080
0.000
BASIC NEGATIVE REFERENCE OPERATION
LOWT.C.
VREF
4.6kIl
"ov
39kn
.,"
RREF
.L.- "
,-----A/IIV---t ' •
IREF(+) "'=' 2mA
~1V
10k!!
APP~OX
POT
.".
-: -VREF
,.
R'6
,.
NOTE. RREF SETS IFS: R16 IS FOR
BIAS CURRENT CANCELLATION
OFFSET BINARY OPERATION
10ka
MSB
LSB
81 B2 B3 B4 B5 B8 87 B8
."""
11 12 13 14 15 18 17 18
6000kn
POS. FULL RANGE
ZERO-SCALE
• Ok!!
.".
.".
+15V -16V
1
1
1
1
1
0
0
0
0
0
0
0
NEG. FULL-SCALE +1 LSB
0
0
0
0
0
0
0
NEG. FULL-SCALE
0
0
0
0
0
0
0
Eo
+4960
0.000
-4.980
0
-5.000
-15V
11-30
1/86, Rev. A
----------I~ DAc-oa a-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
BASIC CONNECTIONS
NEGATIVE LOW IMPEDANCE OUTPUT OPERATION
POSITIVE LOW IMPEDANCE OUTPUT OPERATION
IFR '"
~
tREF
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC OAC),
CONNECT INVERTING INPUT OF OP-AMP TO
(PIN 2); CONNECT 10 (PIN 4)
TO GROUND.
TO
FOR COMPLEMENTARY OUTPUT {OPERATION AS A NEGATIVE LOGIC OAC},
CONNECT NON INVERTING INPUT OF OP-AMP TO 10 (PIN 2),CQNNECT 10 (PIN
4) TO GROUND
INTERFACING WITH VARIOUS LOGIC FAMILIES
CMOS, HTl, NMOS
Eel
VTH = VLC +1 4V
+15V CMOS
VTH=+76V
TTL, DTL
V+
+1SV
VTH '" +1.4V
20M2
13k"
9.1kn
Vee
3k"
62k.\1
TO PIN 1
'----+-<: Vee
20kn
TO PIN 1
'----t---o Vee
R3
62kn
II
-52V
TEMPERATURE COMPENSATING VLC CIRCUITS
APPLICATIONS INFORMATION
15. The voltage at pin 14 is equal to and tracks the voltage at
pin 15 due to the high gain of the internal reference amplifier.
R 15 (nominally equal to R 14 ) is used to cancel bias current
errors; R15 may be eliminated with only a minor increase in
error.
REFERENCE AMPLIFIER SET-UP
The DAC-08 is a multiplying D/A converter in which the
output current is the product of a digital number and the
input reference current. The reference current may be fixed
or may vary from nearly zero to +4.0mA. The full-scale output
current is a linear function of the reference current and is
given by:
Bipolar references may be accomodated by offsetting VREF
or pin 15. The negative common-mode range of the reference
amplifier is given by: VCM- = V- plus (lREF x 1kO) plus 2.5V.
The positive common-mode range is V+ less 1.5V.
255
I FR = 256 x I REF, where I REF = 114.
When a DC reference is used, a reference bypass capacitor is
recommended. A 5.0V TTL logic supply is not recommended
as a reference. if a regulated power supply is used as a
reference, R14 should be split into two resistors with the
junction bypassed to ground with a O.1I'F capacitor.
In positive reference applications, an external positive reference voltage forces current through R14 into the VREF(+) terminal (pin 14) of the reference amplifier. Alternatively, a negative reference may be applied to VREF(-) at pin 15; reference
current flows from ground through R14 into VREF(+) as in the
positive reference case. This negative reference connection
has the advantage of a very high impedance presented at pin
For most applications the tight relationship between IREFand
IFs will eliminate the need for trimming I REF. If required,
full-scale trimming may be accomplished by adjusting the
value of R 14, or by using a potentiometer for R 14. An improved
11-31
1/86, Rev. A
-----------l~ DAc-oa a-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided where 10 + fO = IFS. Current appears at the "true" (10)
output when a "1" (logic high) is applied to each logic input.
As the binary count increases, the sink current at pin 4
increases proportionally, in the fashion of a "positive logic"
DI A converter. When a "0" is applied to any input bit, that
current is turned off at pin 4 and turned on at pin 2. A
decreasing logic count increases fQ as in a negative or
inverted logic D/A converter. Both outputs may be used
simultaneously. If one of the outputs is not required it must
be connected to ground orto a point capable of sourCing ' FS;
do not leave an unused output pin open.
method of full-scale trimming which eliminates potentiometer T.C. effects is shown in the recommended full-scale
adjustment circuit.
Using lower values of reference current reduces negative
power supply current and increases reference amplifier negative common-mode range. The recommended range for
operation with a DC reference current is +0.2mA to +4.0mA.
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
AC reference applications will require the reference amplifier
to be compensated using a capacitor from pin 16 to V-. The
value of this capacitor depends on the impedance presented
to pin 14: for R14 values of 1.0, 2.S and S.OkO, minimum values
of Cc are 1S, 37, and 7SpF. larger values of R14 require
proportionately increased values of Cc for proper phase
margin, such that the ratio of Cc(pF) to R14 (kO) = 1S.
Both outputs have an extremely wide voltage compliance
enabling fast direct current-to-voltage conversion through a
resistor tied to ground or other voltage source. Positive
compliance is 36V above V- and is independent of the
positive supply. Negative compliance is given by V- plus
(I REF X 1kO) plus 2.SV.
For fastest response to a pulse, low values of R14 enabling
small Cc values should be used. If pin 14 is driven by a high
impedance such as a transistor current source, none of the
above values will suffice and the amplifier must be heavily
compensated which will decrease overall bandwidth and
slew rate. For R14 = 1kO and Cc = 1SpF, the reference amplifier slews at 4mAl/ls enabling a transition from 'REF = 0 to
I REF = 2mA in SOOns.
The dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. This
feature is especially useful in cable driving, CRT deflection
and in other balanced applications such as driving centertapped coils and transformers.
POWER SUPPLIES
The DAC-08 operates over a wide range of power supply
voltages from a total supply of 9V to 36V. When operating at
supplies of ±SV or less, IREF s; 1mA is recommended. low
reference current operation decreases power consumption
and increases negative compliance, reference amplifier negative common-mode range, negative logic input range, and
negative logic threshold range; consult the various figures
for guidance. For example, operation at -4.SV with IREF =
2mA is not recommended because negative output compliance would be reduced to near zero. Operation from lower
supplies is pOSSible, however at least 8V total must be applied
to insure turn-on of the internal bias network.
Operation with pulse inputs to the reference amplifier may be
accomodated by an alternate compensation scheme. This
technique provides lowest full-scale transition times. An
internal clamp allows quick recovery of the reference amplifier from a cutoff (lREF = 0) condition. Full-scale transition
(Oto 2mA) occurs in 120ns when the equivalent impedance at
pin 14 is 2000 and Cc=O. This yields a reference slew rate of
16mAl/ls which is relatively independent of RIN and VIN
values.
LOGIC INPUTS
The DAC-08 design incorporates a unique logic input circuit
which enables direct interface to all popular logic families
and provides maximum noise immunity. This feature is made
possible by the large input swing capability, 2/lA logic input
current and completely adjustable logic threshold voltage.
For V-= -15V, the logic inputs may swing between -10V and
+ 18V. This enables direct interface with + 1SV CMOS logic,
even when the DAC-08 is powered from a +SV supply. Minimum input logic swing and minimum logic threshold voltage
are given by: V- plus (IREF x 1kO) plus 2.SV. The logic threshold may be adjusted over a wide range by placing an
appropriate voltage at the logic threshold control pin (pin 1,
VLC ). The appropriate graph shows the relationship between
VLC and VTH over the temperature range, with VTH nominally
1.4 above VLC. For TTL and DTl interface, simply ground pin
1. When interfacing ECl, an IREF= 1mA is recommended. For
interfacing other logic families, see preceding page. For general set-up of the logic control circuit, it should be noted that
pin 1 will source 100/lA typical; external circuitry should be
designed to accommodate this current.
Fastest settling times are obtained when pin 1 sees a low
impedance. If pin 1 is connected to a 1kO divider, for example, it should be bypassed to ground by a 0.01 /IF capaCitor.
Symmetrical supplies are not required, as the DAC-08 is
quite insensitive to variations in supply voltage. Battery
operation is feasible as no ground connection is required:
however, an artificial ground may be used to insure logic
swings, etc. remain between acceptable limits.
Power consumption may be calculated as follows:
Pd = (1+) (V+) + (1-) (V-). A useful feature of the DAC-08
design is that supply current is constant and independent of
input logic states; this is useful in cryptographic applications
and further serves to reduce the size of the power supply
bypass capacitors.
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the
DAC-08 are guaranteed to apply over the entire rated operating temperature range. Full-scale output current drift is low,
typically ± 10ppm/o C, with zero-scale output current and
drift essentially negligible compared to 1/2 lSB.
The temperature coefficient of the reference resistor R14
should match and track that of the output resistor for min11-32
1/86, Rev. A
----------l!mD
DAc-oa a-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
imum overall full-scale drift. Settling times of the DAC-08
decrease approximately 10%at-55° C; at +1250 C an increase
of about 15% is typical.
to logic input amplitude and rise and fall times, due to the
high gain of the logic switches. Settling time also remains
essentially constant for IREF values. The principal advantage
of higher I REF values lies in the ability to attain a given output
level with lower load resistors, thus reducing the output RC
time constant.
The reference amplifier must be compensated by using a
capacitor from pin 16 to V-. For fixed reference operation, a
0.01 ",F capacitor is recommended. For variable reference
applications, see previous section entitled "Reference Amplifier Compensation for Multiplying Applications".
Measurement of settling time requires the ability to accurately resolve ±4",A, therefore a lkO load is needed to
provide adequate drive for most oscilloscopes. The settling
time fixture shown in schematic labelled "Settling Time
Measurement" uses a cascode design to permit driving a 1kO
load with less than 5pF of parasitic capacitance at the
measurement node. At IREF values of less than 1.0mA,
excessive RC damping of the output is difficult to prevent
while maintaining adequate sensitivity. However, the major
carry from 01111111 to 10000000 provides an accurate
indicator of settling time. This code change does not require
the normal 6.2 time constants to settle to within ±0.2% of the
final value, and thus settling times may be observed at lower
values of I REF.
MULTIPLYING OPERATION
The DAC-08 provides excellent multiplying performance
with an extremely linear relationship between I FS and IREF
over a range of 4mA to 4",A. Monotonic operation is maintained over a typical range of I REF from 100",A to 4.0mA.
SETTLING TIME
The DAC-08 is capable of extremely fast settling times,
typically 85ns at IREF = 2.0mA. Judicious circuit design and
careful board layout must be employed to obtain full performance potential during testing and application. The logic
switch design enables propagation delays of only 35ns for
each ofthe8 bits. Settling timeto within 1/2 LSB of the LSB is
therefore 35ns, with each progressively larger bit taking
successively longer. The MSB settles in 85ns, thus determining the overall settling time of 85ns. Settling to 6-bit
accuracy requires about 65 to 70ns. The output capacitance
of the DAC-08 including the package is approximately 15pF,
therefore the output RC time constant dominates settling
time if RL > 5000.
DAC-08 switching transients or "glitches" are very low and
may be further reduced by small capacitive loads at the
output at a minor sacrifice in settling time.
Fastest operation can be obtained by using short leads,
minimizing output capacitance and load resistor values, and
by adequate bypassing at the supply, reference and VLc
terminals. Supplies do not require large electrolytic bypass
capacitors as the supply current drain is independent of input
logic states; 0.1 ",F capacitors at the supply pins provide full
transient protection.
Settling time and propagation delay are relatively insensitive
SETTLING TIME MEASUREMENT
FOR TURN-ON, VL '" 2 7V
fOR TURN-OfF, VL = 07V
VL
II
'5V
lkH
+04V
VOUT lX
~
PROBE
OV
---I"""
-04V
100kn
R1S
2kn
15kr:!
15
T01JJF
-15V
11-33
-=-
1
1/86, Rev. A
DAC-I0
lO-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
(UNIVERSAL DIGITAL LOGIC INTERFACE)
Precision Monolithics Inc.
FEATURES
•
•
•
•
•
•
•
All DAC-10 series models guarantee full 10-bit monotonicity,
and nonlinearities as tight as ±O.05% over the entire operating temperature range are available. Device performance is
essentially unchanged over the ± 18V power supply range,
with 85mW power consumption attainable at lower supplies.
Fast Settling .................................... 85ns
low Full-Scale Drift ....................... 10ppm/o C
Nonlinearity to 0.05% Max Over Temp Range
Complementary Current Outputs ............ 0 to 4mA
Wide Range Multiplying Capability ... 1MHz Bandwidth
Wide Power Supply Range .. +5, -7.5 Min to ±18V Max
Direct Interface to TTL, CMOS, ECl, PMOS, NMOS
A highly stable, unique trim method is used, which selectively
shorts zener diodes, to provide 1/2 LSB full-scale accuracy
without the need for laser trimming.
Single-chip reliability coupled with low cost and outstanding
flexibility make the DAC-10 device an ideal building block for
AID converters, Data Acquisition systems, CRT display,
programmable test equipment, and other applications where
low power consumption, input/output versatility, and longterm stability are required.
ORDERING INFORMATlONt
18-PIN HERMETIC
DUAL-IN-LINE PACKAGE
MILITARY TEMP."
COMMERCIAL TEMP.
NL
LSB
±1/2
±1
DAC10BX'
DAC10CX'
DAC10FX
DAC10GX
PIN CONNECTIONS
* For devices processed In total compliance to Ml L-STD-883, add 1883 after
part number Consult factory for 883 data sheet
tAil commercial and Industrral temperature range parts are available with
burn-In For ordenng Information see 1986 Data Book, Section 2
GENERAL DESCRIPTION
18-PIN HERMETIC
The DAC-10 series of 10-bit monolithic multiplying digitalto-analog converters provide high-speed performance and
full-scale accuracy,
DUAl-IN-lINE PACKAGE
(X-Suffix)
Advanced circuit design achieves 85ns settling times with
very low 'glitch' energy and low power consumption, Direct
interface to all-popular logic families with full noise immunity
is provided by the high-swing, adjustable-threshold logiC
inputs.
SIMPLIFIED SCHEMATIC
VREFI-)
17
0--+---1
CQMP
v-
Manufactured under one or more of the following patents
4,055,770,4,056,740,4,092,639
11-34
1/86, Rev. A
----------I~ DAC-10 10-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
Logic Inputs •••••••••••••••••.••••••• V- to V- plus 36V
VLC ••••••••••••••••••••••••••••••••••••••••••• V-to V+
Analog Current Outputs •••••••••••••••••• + 18V to -18V
Reference Inputs (V 16 to V17) ••.•••••••••••••••• V- to V+
Reference Input Differential Voltage
(V16 to V17) •••••••••••••••••••••••••••••••••••.• ±18V
Reference Input Current (1 16) ••••••••••••••••••••• 2.SmA
Operating Temperature
DAC-10BX, CX ..................... -SS·C to +12S·C
DAC-10FX, GX ••••••••••••••••••••••••• O· C to + 70· C
DICE Junction Temperature (TI ) .•••••. -6S·C to +1S0·C
Storage Temperature ••••••••••••••••• -6S· C to + 1S0· C
Power Dissipation • • • • • • • • • • • • • . • • • • • • • • • • • • • •• SOOmW
Derate above 100· C •••••••••••••••••••••••••• 10mW/· C
Lead Temperature (Soldering, 60 sec) ••••••••••••• 300· C
V+ Supply to V- Supply. • • • • •• • • • • • • • • • • • • • •• • • • • •• 36V
NOTE: Absolute rallngs apply to both DICE and packaged parts, unless
otherwise noted
ELECTRICAL CHARACTERISTICS at Vs= ±1SV; IREF= 2mA; -SS·C:5 TA:512S·C for DAC-10B and DAC-10C,
O·C:5 TA:5 70·C for DAC-10F and G, unless otherwise noted. Output characteristics apply to both lOUT and lOUT.
DAC-10B/F
PARAMETER
SYMBOL
CONDITIONS
MIN
Monotonicity
TYP
MAX
10
Nonlinearity
NL
0.3
DNL
0.3
Settling Time
ts
Output Capacitance
Co
Propagation Delay
tpLH
tpHL
All Bits Switched
Output Voltage
ComplIance
All Bits Switched ON or OFF
Settle to 0.05% of FS (See Note)
MIN
TVP
MAX
10
Differential Nonlinearity
65
~
~
DAC-10C/G
0.5
135
UNITS
Bits
0.6
LSB
07
LSB
150
65
ns
18
18
VOC
Full-Scale Current
<1 LSB
Change
50
50
-5.5
+10
50
50
-55
+10
Gain Tempco
TCI F•
(See Note)
±10
±25
±10
±50
ppm/DC
Full-Scale Symmetry
I FSS
IFA-I FA
0.1
4
0.1
4
"A
Zero-Scale Current
Izs
0.01
0.5
Full-Scale Current
IFA
DI/dt
3.996
4.072
"A
rnA
Reference Input Slew Rate
Reference Bias Current
Power Supply Sensitivity
Power Supply Current
Ie
PSSI F.+
PSSI F....
1+
11+
I-
Power Dissipation
Pd
Logic Input Levels
V,L
V,H
Logic Input Currents
I,L
I'H
(See Nota)
rouT.
3.960
0.01
0.5
3.996
4.032
3.920
6
SYMBOL
0.001
0.0012
2.3
-9
18
-59
231
85
4.5V " V+" 18V
-18V" V-" -10V
V.=±15V,IAEF=2mA
V. = +5V1-7.5V; IAEF= lmA
V.=+5V/-7.5V; 'AEF= lmA
0.01
0.01
4
-15
4
-9
276
107
VLC=O
2
10
VLC-O; 5V" V,N " 0.8V
2V"V ,N ,,18V
at Vs = ±1SV; IREF = 2m A; TA
-5
0.001
Differential Nonlinearity
Output Voltage
Compliance
DNL
VOC
Full-Scale Current
CONDITIONS
0.01
0.01
%~IFsI%~V
2.3
-9
1.8
-59
231
85
4
-15
4
-9
276
107
TVP
10
mW
V
"A
DAC-10G
MAX
MIN
3.978
TYP
MAX
3.996
0.6
+10
-5 -6/+15
LSB
0.7
4.014
3.956
UNITS
Bits
0.5
0.3
-5 -6/+18
Izs
10
10
0.3
Full-Scale Current <1 LSB
Change
VAEF = 10.000V,
R,. = R,s = 5.000kO
5
0.001
rnA
= 2S·C, unless otherwise noted. Output characteristics
MIN
Full-Scale Symmetry
Zero-Scale Current
"A
0.001
0.0012
0.8
2
10
10
NL
mAl"s
-3
0.8
Monotonicity
Nonlinearity
V
6
DAC-10B/C/F
PARAMETER
ns
3
ELECTRICAL CHARACTERISTICS
apply to both lOUT and
RL -5kO
RL =0
pF
3.996
LSB
+10
V
4.036
rnA
0.1
4
0.1
4
"A
0.01
0.5
0.01
0.5
pA
NOTE: Guaranteed by design
11-35
1/86, Rev. A
~
~
0
U
0
0
~
0
~
~
0
.....
Cl
II
----------I~ DAC·10 10·BIT HIGH·SPEED MULTIPLYING D/A CONVERTER
DICE CHARACTERISTICS
1. VLC (LOGIC)
THRESHOLD CONTROL
2. iO
3. V4. 10
5. B1 (MSB)
B2
B3
B4
B5
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
B6
B7
B8
B9
B10 (LSB)
V+
VREF (+)
17. VREF (-)
18. COMPENSATION
For additional DICE Information refer 10
1986 Dala Book, Section 2.
DIE SIZE 0.086 X 0.090 Inch, 7740 sq. mils
(2.184 X 2.286 mm, 4.993 sq. mm)
WAFER TEST LIMITS at
Vs = ± 15V, IREF = 2m A, TA = 25°C, unless otherwise noted. Output characteristics refer to both
lOUT and lOUT·
PARAMETER
SYMBOL
CONDITIONS
Resolution
DAC·10G
LIMIT
LIMIT
UNITS
10
10
Bits MIN
10
10
Bits MIN
±0.5
±1
LSBMAX
True 1 LSB
+10
-5
+10
-5
V MAX
VMIN
IFS ±3.996 MA
±18
±40
/JAMAX
0.5
0.5
/JAMAX
Monotonicity
Nonlinearlly
NL
Output Voltage Compliance
Voe
Zero-Scale Current
Izs
All Bits OFF
Logic Input "1"
Output Current Range
DAC·10N
VIH
IIN= 100nA
Logic Input "0·'
VIL
VLe@Ground
IIN=-100/JA
Posilive Supply Current
1+
V+= 15V
Negative Supply Current
1-
V-=-15V
2
2
VMIN
0.8
0.8
V MAX
4
4
mAMAX
-15
-15
mAMAX
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly melhods and normal yield loss, yield after packaging is nol
guaranteed for slandard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample 101 assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS
at Vs = ±15V, and IREF = 2mA, unless otherwise noted. Output
characteristics refer to both lOUT and lOUT·
PARAMETER
Settling Time
Gain Temperature
Coefficient (TCI
SYMBOL
CONDITIONS
ts
To ±1/2 LSB When Output is
Switched from 0 to FS
VAEF Tempco Excluded
DAC·10N
DAC·10G
TYPICAL
TYPICAL
UNITS
85
85
ns
±10
±10
ppm FS/oC
Output CapaCitance
18
18
pF
Output Resistance
10
10
MO
11·36
1/86, Rev. A
-----------l[fffi) DAC-10 10-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT CURRENT VI
OUTPUT VOLTAGE
(OUTPUT VOLTAGE COMPLIANCE)
TRUE AND COMPLEMENTARY
OUTPUT OPERATIONS
OUTPUT VOLTAGE
COMPLAINCE VI TEMPERATURE
+280r-,-----~--_,----~----_r_,
80
ALL BITS ON
+240 f-+---+---I~--+--+-I
72
OmA
TA" TMIN TO TMAX
lOUT
6.4
~
;t
5.6
E
;: 48
1.0mA
illa:
2.0mA
v-
= -15V
v-
= -10V
C.)
t~EF _1'mA
I-
~ 2.4
:>
01.6
(00000000)
("111111)
rJ::~ii'i~iili~+~
+120
IREF = 2mA
r
4.0
":> 3.2
lOUT
+200
+160
~
IR~F
0.6
-40
= Ol2mA
-80f-+--+---I~--+--+-I
IREF = 2mA
-120~~
-14 -10
-6
10
-2
14
____
-50
18
100
90
"<
E
I
1
80
BO
~ 70
~ 60
~ 60
1l
:>
~
50
~ 50
8::
40
~ 40
" 30
" 30
iil
~ 20
1.0
o
2.0
4,0
I
lmd_
o
-40
-20
V+, POSITIVE POWER SUPPLY (Vdc)
-80
I
I
-60
-laO
-160
-140
~~
+150
i:il
40
"~
30
~
20
1-
I
I
ALL BITS "HIGH" OR "LOW"
I
V+ =
l,sv
I.
I
I
10
1J I
-120
80
~ 60
u
~ 50
~
WITH IREF = 02mA
10
60 80 10012014,016018020,0
T
____
IREF = 20mA
~ 70
I I I
~
o
IREF =
r-
I-
1- WITH IREF = 02mA
2 20
'j- -
;;
!
I I I
t-i'- WITH
I I
~
+100
v- = -15V
90
1- WITH IREF = 2mA
~ 7.0
____
+50
100
J
BITS MAY BE "HIGH" OR "LOW"
ALL BITS "HIGH" OR "LOW"
90
~
POWER SUPPLY CURRENT
VI TEMPERATURE
POWER SUPPLY CURRENT VI V-
10.0
__
TEMPERATURE (Cel
OUTPUT VOLTAGE (VOLTS)
POWER SUPPLY CURRENT VI V+
~
-200
-50
-180
+50
+100
+150
TEMPERATURE (OCJ
V-, NEGATIVE POWER SUPPL V (Vdc)
BASIC CONNECTIONS
ACCOMMODATING BIPOLAR REFERENCES
BASIC POSITIVE REFERENCE OPERATION
+VREF
IFR"
+~:~~
It
~g~! It 2
10 + iO = IFR FOR
ALL LOGIC STATES
RREF
MSB
LSB
B1 B2 B3B4 B5 B6 B7 B8 B9 Bl0
~
VIN~
~ IREF
16
RIN
DAC-10
10
17
IREF---'
R17
IREF
RREF"'" R17
V+
VLC
VREF " +10 ODOV
RREF " 5DDOk
R15 = RREF
CC" O.D1.uF
VLC '" OV (GROUND)
~
~
PEAK NEGATIVE SWING OF liN
+VREF o--A,RR"E,,'_-,,'6'-j
...
R17
(OPTIONAL)
VIN~__
HIGH INPUT
OAC-l0
17
L-______________J
IMPEDANCE
+VREF MUST BE ABOVE PEAK POSITIVE SWING OF VIN
11-37
1/86, Rev_ A
II
-----------1~ DAC-10 10-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
BASIC NEGATIVE REFERENCE OPERATION
RECOMMENDED FULL-SCALE ADJUSTMENT CIRCUIT
LQWTC
~l~V o-- +VRE'
I
...
jOPTIONAL RESISTOR
OFFSET INPUTS
~RREF lFOR
,
,.
RL
REQ 5000.
Both outputs have an extremely wide voltage compliance
enabling fast direct current-to-voltage conversion through a
resistor tied to ground or other voltage source. Positive
compliance is 36V above V- and is independent of the
positive supply. Negative compliance is + 10V above V-.
The dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. This
feature is especially useful in cable driving, CRT deflection
and in other balanced applications such as driving centertapped coils and transformers.
Settling time and propagation delay are relatively insensitive
to logiC input amplitude and rise and fall times, due to the
high gain of the logic switches. Settling time also remains
essentially constant for IREF values down to 1mA, with
gradual increases for lower IREF values lies in the ability to
attain a given output level with lower load resistors, thus
reducing the output RC time constant.
POWER SUPPLIES
The DAC-1O operates over a wide range of power supply
voltages from a total supply of 9V to 36V. When operating with
V-supplies of-10Vor less, IREF~ 1mA is recommended. Low
reference current operation decreases power consumption
and increases negative compliance, reference amplifier
negative common-mode range, negative logiC input range,
and negative logic threshold range; consult the various
figures for guidance. For example, operation at -9V with
IREF = 2mA is not recommended because negative output
compliance would be reduced to near zero. Operation from
lower supplies is possible, however at least 8V total must be
applied to insure turn-on of the internal bias network.
Measurement of settling time requires the ability to accurately resolve ± 2/o1A, therefore a 4kO load is needed to provide
adequate drive for most oscilloscopes. The settling time
fixture of schematic titled "Settling Time Measurement" uses
a cascode design to permit driving a 4kO load with less than
5pF of parasitic capaCitance at the measurement node. At
IREF values of less than 1mA, excessive RC damping of the
output is difficult to prevent while maintaining adequate
sensitivity. However, the major carry from 0111111111 to
1000000000 provides an accurate indicator of settling time.
This code change does not require the normal 6.2 time
constants to settle to within ±0.2% of the final value, and thus
settling times may be observed at lower values of IREF.
Symmetrical supplies are not required, as the DAC-10 isquite
insensitive to variations in supply voltage. Battery operation
is feasible as no ground connection is required; however, an
artificial ground may be used to insure logic swings, etc.
remain within acceptable limits.
DAC-10 switching transients or "glitches" are very low and
may be further reduced by small capacitive loads at the
output at a minor sacrifice in settling time.
Fastest operation can be obtained by using short leads,
minimizing output capacitance and load resistor values, and
by adequate bypassing at the supply, reference and VLC
terminals. Supplies do not require large electrolytiC bypass
capaCitors as the supply current drain is independent of input
logic states; 0.1/o1F capaCitors at the supply pins provide full
transient protection.
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the
DAC-1O are guaranteed to apply over the entire rated operating temperature range. Full-scale output current drift is
tight, typically ±10ppm/oC, with zero-scale output current
and drift essentially negligible compared to 1/2 LSB.
11-41
-----_ _..
-----.-
1/86, Rev. A
~
~
~
ou
C)
o
~
~
,....;j
is
~
~
~
DAC-20
2-DIGIT BCD HIGH-SPEED MULTIPLYING D/A CONVERTER
(UNIVERSAL DIGITAL LOGIC INTERFACEI
Precision Monolithics Inc.
between reference and full-scale currents eliminates the
need for full scale trimming in most applications. Direct interface to all popular logic families with full noise immunity is
provided by the high swing, adjustable threshold logic
inputs.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Fast Settling Output Current ..................... 85n8
Full-Scale Current Prematched to ±O.3 lSB
Direct Interface to TTL, CMOS, ECl, PMOS, NMOS
Nonlinearity to ±1/2 lSB Maximum Over Temp.
High Output Impedance and Compliance -10V to +18V
Complementary Current Outputs
Wide Range Multiplying Capability ... 1MHz Bandwidth
low FS Current Drift .................... ± 10ppml~C
Wide Po_r Supply Range ............. ±4.5V to ±18V
low Po_r Consumption ............... 37mW @ ±5V
low Cost
Complementary current outputs with -10V to + 18V voltage
compliance enable resistive termination, a voltage output
without an external op amp.
Both DAC-20 models guarantee full 2-digit monotonicity,
some have nonlinearity as tight as ± 112 LSB over the entire
operating temperature range. Nonlinearity is unchanged
over the ±4.5V to ± 18V power supply range, with 37mW
power consumption attainable at ±5V supplies.
ORDERING INFORMATIONt
NL
LSB
±1/2
The compact size and low power consumption make the
DAC-20 attractive for portable applications.
16-PIN DUAL-IN-LiNE PACKAGE
COMMERCIAL TEMPERATURE RANGE
HERMETIC
PLASTIC
DAC20CQ
DAC20CP
DAC-20 applications include AID converters, audio attenuators, analog meter drivers, programmable power supplies,
high-speed modems and other applications where low cost,
high speed and complete input/output versatility are
required.
t All
commerCial and industrial temperature range parts are available with
burn-In For ordering information see 1986 Data Book, Section 2.
PIN CONNECTIONS
GENERAL DESCRIPTION
VLC
The DAC-20 series of 2-digit BCD monolithic multiplying
digital to analog converters provide very high-speed performance coupled with low cost and outstanding applications
flexibility.
16-PIN
DUAl-IN-LiNE
PACKAGE
Advanced circuit design achieves 85ns settling times with
very low "glitch" energy and at low power consumption.
Monotonic multiplying performance is attained over a wide 20
to 1 reference current range. Matching to within 1 lSB
EQUIVALENT CIRCUIT
.-
r-~-'---r~--~~~~--~~--~~~~----lr-oIOUT
Manufactured under one or more of the following patents: 4,055,773; 4,056,740; 4,002,639
11-42
1/86, Rev. A
---------f~ DAC-20 2-DIGIT BCD HIGH-SPEED MULTIPLYING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
(TA = 25° C, unless otherwise noted)
Operating Temperature Range
DAC-20
CP ........................ 0° C to + 70° C
DICE Junction Temperature (TJ) ••••••• -65°C to +150°C
Storage Temperature Range
V+ Supply to V- Supply.. • • • • •• • • • • • • • • • • • • • • • ••••• 36V
Logic Inputs ......................... V- to V- plus 36V
VLC ••••••••••••••••••••••••••••••••••••••••••• V-to V+
Reference Inputs (V14, V15) ..................... V- to V+
Reference Input Differential Voltage (V14 to V15) •••• ±18V
Reference Input Current (114) ••••••••••••••••••••• 5.0mA
ca,
a Package
......................... -65°C to +150°C
P Package ......................... -65° C to + 125° C
Power Dissipation •••••••••••••••••••••••••••••• 500mW
Derate above 100° C •••••.•••••••••••••••••• 10mW/o C
NOTE: Absolute ratings apply to both DICE and packaged parts unless
otherwise noted.
Lead Temperature (Soldering, 60 sec) ••••••••••••• 300° C
ELECTRICAL CHARACTERISTICS
characteristics refer to both lOUT and
at Vs= ±15V, IREF= 2.0mA, O°C:5 TA:5 70°C, unless otherwise noted. Output
~
!'OuT.
DAC-20C
PARAMETER
SYMBOL
CONDITIONS
MIN
TVP
MAX
UNITS
Resolution
BCD 0 to 99 steps
2
Digits
Monotonicity
BCD 99 steps
2
Digits
Nonlinearity
NL
0000 0000 to 1001 1001
Settling Time
ts
To ±1I2 LSB (±0.5% FS)
all bits sWitched ON or
OFF, TA = 25·C (Note 1)
85
150
ns
Propagation Delay
Each Bit
All bits sWitched
tpLH
tpHL
TA =25·C (Note 1)
35
60
ns
Full Tempco
TCI FS
(Note 1)
±10
±60
ppml"C
Output Voltage Compliance
(True Compliance)
Voe
Full-scale current change
< 1/2 LSB « 0.5% FS)
ROUT> 2OMO typical
IREF= 1mA
-10
+18
V
Full Range Output
(Digital Input 1001 1001)
IFR4
TA = 25·C, IREF= 2mA
1.92
Zero-Scale Current
Izs
Output Current Range
lOR
Logic Input Levels
LogiC ''0''
Logic "1"
V,L
V,H
LogiC I nput Current
Logic ''0''
Logic "1"
I,L
I'H
±1I2
V-=-10V
V- = -12V to -18V
2.2
4.2
1.98
2.04
mA
0.2
5
I'A
2
2
VLe=OV
Y,N = -10V to +0 8V
Y,N = 2V to 18V
-2
0.002
V'S
V-=-15V
VTHR
Vs =±15V (Note 1)
-10
-1
Reference Bias Current
1'5
Reference Input Slew
Rate
dlldt
(Note 1)
Power Supply Sensitivity
PSSI FS+
PSSI FS-
V+ = 4.5V to 18V
V- = -4.5V to -18V
IREF= 1mA
Power Supply Current
1+
11+
1-
mA
0.8
VLe=OV
LogiC Input SWing
4
V
±10
±10
I'A
+18
V
+135
V
-3
I'A
8
mNl's
±Q.0003
±0.03
%4.I FS
±0.002
±0.03
%4.V
3.8
-6.5
3.8
-9.1
mA
Vs =±15V,I REF =2mA
2.3
-5.0
2.5
-7.8
Vs =±5V,I REF =1mA
Vs = ±15V, IREF= 2mA
37
152
52
194
mW
Vs =±5V,I REF =1mA
NOTE:
1. Guaranteed by deSign.
1/86, Rev. A
11-43
-'~~----
U
0
~
0
LogiC Threshold Range
Pd
~
0
U
-10
Power Dissipation
LSB
~
.., - - - - - - - - - -
,-',
-
-'-,
----
~
~
U
......
0
II
---------I~ DAC·20 2·DIGIT BCD HIGH·SPEED MULTIPLYING D/A CONVERTER
DICE CHARACTERISTICS
1. VLC
2. TOUT
3. V4.
lOUT
5.
8.
7.
8.
BIT 1 (MSB)
BIT2
BIT3
BIT4
9.
10.
11.
12.
13.
14.
15.
18.
BITS
BIT8
BIT 7
BIT 8 (LSB)
V+
VRE'(+)
VRIF (-)
COMP
For additional DICE Information refer to
1986 Data Book, Section 2.
DIE SIZE 0.085 X 0.085 Inch, 5,525 sq. mila
(2.159 X 1.651 mm, 3.58 sq. mm)
WAFER TEST LIMITS at Vs = ±
15V, IREF = 2.0mA,
TA = 25°C, unless otherwise noted. Output characteristics
refer to both
lOUT and lOUT'
DAC·20G
PARAMETER
SYMBOL
LIMIT
BCD 0 to 99 steps
Resolution
Monotonlclty
Nonlinearity
CONDITIONS
BCD 99 steps
NL
FS = 1001 1001
Output Voltage Compliance
UNITS
Digits MIN
Digits MIN
±112
LSB MAX
Voe
Full-Scale Current Change
<1/2 LSB
+18
-10
VMAX
VMIN
Full-Scale Current
I FS4
VREF = 10V
R'4, R,5 = 5kO
2.04
1.92
mAMAX
mAMIN
Zero-Scale Current
Izs
Output Current Range
lOR
Logic "0" Input Level
V'L
Logic "1" tnput Level
V'H
Logic Input Current
Logic "0"
Logic "1"
I'L
I'H
p.AMAX
V- = -10V
V- = -12V to -IBV
2.1
4.2
mAMIN
0.8
V MAX
VMIN
V'N = -10V to +O.BV
V'N = 2V to lBV
±10
±10
p.AMAX
+IB
-10
V MAX
VMIN
±0.03
±0.03
%Il.I FS MAX
%Il.V
Logic Input Swing
V,s
V-=-15V
Power Supply Sensitivity
PSSIFs+
PSSI F5-
V- = -4.5V to -IBV
V- = -4.5V to -18V
IREF= lmA
Power Supply Current
1+
1-
VS=±IBV
IREF ,,2mA
3.B
-7.B
mAMAX
Power Dissipation
Pd
VS=±IBV
IREF " 2mA
194
mWMAX
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations In assembly methods and normal yield loss, yield afler packaging is not
guaranteed for standard product dice. Consult factory to negotiate speCifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS
at Vs = ±15V, IREF = 2.0mA, unless otherwise noted specified. Output
characteristics refer to both lOUT and lOUT.
DAC·20G
PARAMETER
SYMBOL
Reference Input Slew Rate
dlldt
Propagation Delay
tPLH' tpHL
ts
Settling Time
CONDITIONS
TYPICAL
UNITS
B
mAlp.s
TA = 25°C, Any Bit
35
ns
To ± 1/2 LSB, All Bits Switched
ON or OFF, TA = 25°C
85
ns
11·44
1/86, Rev. A
--------I~ DAC-20
2-DIGIT BCD HIGH·SPEED MULTIPLYING D/A CONVERTER
TYPICAL REFERENCE PERFORMANCE CHARACTERISTICS
REFERENCE AMP
COMMON·MODE RANGE
(DIGITAL INPUT 10011001)
FULL·SCALE CURRENT VI
REFERENCE CURRENT
(DIGITAL INPUT 1001 1001)
2.8
5.0
2.4
1
~
0:
0:
""
~
5
2.0
V~. -,~V
V- .1_5V
I
I
'.1
2mA
·1
ili0:
L.I,mA
!:;
'iEF
4.0
1
....
IV•• 1,6v
V
3.0
0:
2.0
j!:
I
-1'1
[
0.0
~18
~12
~4
-8
[
12
1/
'.0
IAt.o12mA
POSITIVE COMMON MODE IS ALWAYS (V+) -1.5V;
NEGATIVE COMMON MODE RANGE IS V- PLUS
(tREF
x SOOn)
-y
-
-
9 2.0
3.0
2.0
4.0
l
-'"
6.0
'2
REFERENCE INPUT FREQUENCY
RESPONSE (DIGITAL INPUT
10011001)
OUTPUT CURRENT
OUTPUT VOLTAGE
(OUTPUT VOLTAGE COMPLIANCE)
(DIGITAL INPUT 10011001)
VB
~
iO
:s
........
'.2
i'
~
-4
5
0
~
~
0:
0.4
-8
-'0
-'2
0.0
-15 -60 -25
0
25
50
75
100 125 150 175
-'4 0.1
2.4
'.1
r-..
R'4 .. R,S " 1kn
Rt. "50on
0.5
I
r
r
0.4
2.0
5.0
-12
FREQUENCY (MHz)
I I
! I
~
[
II
[
I J
-8
-4
12
16
OUTPUT VOLTAGE (VOLTS)
CURVE 1: Cc " 15pF, V1N .. 2.0Vp_p CENTERED AT
+1.0V, LARGE SIGNAL.
CURVE 2' Cc = 15pF, V IN = 50mVp_p CENTERED AT
+200mV, SMALL SIGNAL.
POWER SUPPLY
CURRENT VI V+
POWER SUPPLY
CURRENT VI V-
8.0
1.0
BITS "HIGH" OR "LOW"
1....
BITS MAY BE "HIGH" OR "LOW"
I-
....
1i0:i
1i0:i
4.0
il:
iil
1+
0:
~
""~
4.0
M
iil
I I I Ii_
!- WI~H I~EF J0.2JA _
0:
~
'.0
=2mA
I- WITH IREF '" lmA
0:
0:
"">
t
I - WITH IREF
=<
.§ 6.0
6.0
~
'.0
M
MUUUUW~N~~W
V+, POSITIVE POWER SUPPLY (Vdc)
1+
I-
M~~_~~~~~~~
V-, NEGATIVE POWER SUPPLY (Vdc)
11-45
<:
0'
~
iAEF .I'mA
IREF" O.2mA
-16
10
I
r
0.0
1.0
I
IREF'" 1mA
0.8
II I
TEMPERATURE (oC)
v-, ~5V
'.2
\
vRtS " ov
I I I I II
0.2
L-,L
II
2.0
-I
~
0.8
'0\
-2
!:;
>
:I:
q
./
~
Z
~
2.8
i'
~
U
o
o
TA "'TMIN TOTMAX
~
'6
LOGIC INPUT VOLTAGE (VOLTS)
THE RECOMMENDED RANGE FOR OPERATION WITH
WITH A OC REFERENCE CURRENT IS +O.2mA
TO +4.0mA.
NOTE:
PLUS 2.6V,
2.0
'.1
~
I
00
'.0
IREF' REFERENCE CURRENT (mA)
VTH - VLC VI TEMPERATURE
~
'[
!.!
L
0.0
V,S. REFERENCE COMMON MODE VOLTAGE (VOLTS)
NOTE:
LIMIT FOR
V~I·
V
0.0
16
'"
V
"
0.4
6.0
/
0
0.8
~
V
!/
il
'.2
8.0
FOR
~MIN ITO iMA~- I - i-,L1MIT
V-; -'6V
T1·
I I
T A· TMIN TO TMAX
LOGIC INPUT CURRENT
VI INPUT VOLTAGE
1/86, Rev. A
---------t~ DAC-20 2-DIGIT BCD HIGH-SPEED MULTIPLYING D/A CONVERTER
TYPICAL REFERENCE PERFORMANCE CHARACTERISTICS
OUTPUT VOLTAGE COMPLIANCE
'I TEMPERATURE
POWER SUPPLY CURRENT
VI TEMPERATURE
80
,.
~
ALL BITS "HIGH" OR "LOW'
~
1-
6.0
'REF'" 2.DmA
iiia:
w
a:
~
I
v- .. -15V
1.
'2
il
40
~
!
v+ = +16V
a:
1+
~ 20
-4
~
-8
ooL-J-~
-26
0
25
50
75
100 125
150
-75 -50 -25
TEMPERATURE (CCI
__L-J-~__L-J-~~
0
25
50
75
laO 125
150
TEMPERATURE {CCI
The unused output must be connected to ground or some
voltage source capable of sourcing 1.65 times IREF. A detailed
discussion of reference input operation begins on the next
page.
BASIC OUTPUT CONNECTIONS
With complementary current outputs, the DAC-20 may be
used with either positive true or negative true (complementary) logic. Current appears at the "true" output (10) when a
"1" is applied to a logic input. As the BCD-coded input
increases, the sink current at Pin 4 increases proportionately,
in the fashion of a "positive logic" D/A converter. When a "0"
is applied to a logic input, that current is turned OFF at Pin 4
and ON at Pin 2 (lQj which is used for negative true or
"negative logic" D/A converters.
Both outputs have an extremely wide voltage compliance
enabling fast direct current-to-voltage conversion through a
resistor tied to ground or other voltage source. Positive
compliance is 36V above V- and is independent of the
positive supply. Negative compliance is given by V- plus
(I REF X 8000) plus 2.5V.
POSITIVE VOLTAGE OUTPUT
NEGATIVE TRUE LOGIC INPUTS
POSITIVE TRUE LOGIC INPUTS
+,ov
V REF
5000len 14
-=DECIMAL
INPUT
+15V -16V
-=-
-15V
BCD INPUT
MID
LID
10
0
0000
0000
0
10
0001
0000
020mA
+1.0V
20
0010
0000
0.40mA
30
0011
0000
O.SOmA
40
0100
0000
80
1000
99
1001
DECIMAL
INPUT
+15V -15V
BCD INPUT
MSD
LSD
iO
0
1111
1111
0
10
1110
1111
020mA
+1.0V
+2.0V
20
1101
1111
0.4OmA
+2.0V
+3.0V
30
1100
1111
o SOmA
+3.0V
0.80mA
+4.0V
40
1011
1111
O.80mA
+40V
0000
1.SOmA
+8.0V
80
0111
1111
1.60mA
+8.0V
1001
198mA
+9.9V
99
0110
0110
1.98mA
+9.9V
Eo
0
11-46
Eo
0
1/86, Rev. A
---------I~ DAC-20 2-DIGIT BCD HIGH-SPEED MULTIPLYING D/A CONVERTER
NEGATIVE VOLTAGE OUTPUT
POSITIVE TRUE lOGIC INPUTS
NEGATIVE TRUE LOGIC INPUTS
MSO
LSD
~,.---"'---.
+10V
V REF
5000krl. 14
500kil
+1SV -15V
DECIMAL
INPUT
-15V
BCD INPUT
MSD
LSD
0000
0000
10
0001
0000
20
0010
30
0011
10
-15V
+15V -15V
DECIMAL
INPUT
Eo
0
BCD INPUT
MSD
LSD
~
0
1111
1111
0
10
1110
1111
o 20m A
Eo
0
020mA
-1.0V
-1.0V
0000
0.40mA
-20V
20
1101
1111
0.40mA
-2.0V
0000
o BOmA
-30V
30
1100
1111
O.BOmA
-30V
40
0100
0000
O.BOmA
-40V
40
1011
1111
O.BOmA
-4.0V
BO
1000
0000
1 BOmA
-B.OV
BO
0111
1111
1.BOmA
-BOV
99
1001
1001
1.98mA
-9.9V
99
0110
0110
1.9BmA
-9.9V
REFERENCE OPERATION
POSITIVE
NEGATIVE
MSD
MSD
LSD
~~
B1 82 63 B4 65 86 B7 BB
~R~~\ 14 r'",-"'-"....I"-...o;....-..;=",",",
o---.,......NV''-'I
VREF{+)
IREF
DAC-20
VREF{-)
DAC-20
R1S 15
FOR FIXED REFERENCE,
TTL OPERATION,
TYPICAL VALUES ARE
VREF = +10 COOV
RREF = 5 COOk
R'5"",RREF
Cc = 00lpF
VLC '" OV (GROUND)
LSB
MSB
RREF
(R14)'4
VREF{+)
R15,S
r
o lJ.1F
-=-
V REF {+)
LSD
~~
B1 82 83 B4 65 B6 B7 B8
MSB
16
Cc
v-
FOR FIXED REFERENCE,
TTL OPERATION,
TYPICAL VALUES ARE
13
CQMP
coov
v+
VREF = +10
RREF = 5 COOk
R,S "'" RREF
Cc =' 001IJF
VLC = OV (GROUND)
VLC
16
f'F CC~l::
v-
13
V+
VLC
VREFH
I FS = RREF
I FS '" RREF
TO'"
10 +
IREF x 165
FOR ALL LOGIC INPUT STATES
iQ ""
10 +
IREF x 165
FOR ALL LOGIC INPUT STATES
REFERENCE AMPLIFIER SETUP
The DAC-20 is a multiplying converter in which the output
current is the product of a digital number and the input reference current. The reference current may be fixed or may vary
from nearly zero to +4.0mA. The full range output current is a
linear function of the reference current and is given by:
In positive reference applications an external positive reference voltage forces current through R14 into the VREF(+)
terminal (Pin 14) of the reference amplifier. Alternatively. a
negative reference may be applied to VREF(-) at Pin 15; reference current flows from ground through R14 into VREF(+). as
in the positive reference case. This negative reference con-
11-47
1/86, Rev. A
II
----------I1fMD
DAC-20 2-DIGIT BCD HIGH-SPEED MULTIPLYING D/A CONVERTER
nection has the advantage of a very high impedance presented at Pin 15. The voltage at Pin 14 is equal to and tracks the
voltage at Pin 15 due to the high gain of the internal reference
amplifier. R1s(nominally equal to R 14 ) is used to cancel bias
current errors and may be eliminated with only a minor
increase in error.
When a DC reference in used, a reference bypass capacitor is
recommended. A 5V TTL logic supply is not recommended
as reference. If a regulated power supply is used as a reference, R14 should be split into two resistors with the junction
bypassed to ground with a O.ltLF capacitor.
For most applications the tight relationship between IREFand
IFR will eliminate the need for trimming IREF. If required,
full-scale trimming may be accomplished by adjusting the
value of R14.
The reference amplifier must be compensated by using a
capacitor form Pin 16 to V-. For fixed reference operation, a
O.OltLF capacitor is recommended. For variable reference
applications, see section entitled "Multiplying Operation."
VTH e:: VLC +1.4V
+15V CMOS
VTH = +7,6V
VTH '" +1 4V
+1SV
9.1kn
VLe
Fastest settling times are obtained when Pin 1 sees a low
impedance. If Pin 1 is connected to a 1kO divider, for example, it should be bypassed to ground by a 0.01 tLF capacitor.
MULTIPLYING OPERATION
Bipolar references may be accommodated by offsetti ng V REF
or Pin 15. The negative common-mode range of the reference
amplifier is given by: VCM-= V- plus (IREFX 8000) plus 2.5V.
The positive common mode range is V+ less 1.5V.
AC reference applications will require the reference amplifier
to be compensated using a capacitor from Pin 16 to V-. The
value of this capacitor depends on the impedance presented
to Pin 14: for R14 values of 1.0, 2.5 and 5.0kO, minimum value
of Cc are 15, 37, and 75pF. larger values of R14 require
62k.\1
ECl
The logic input threshold is l.4V above VLC. For TTL and DTl
interface, simply ground Pin 1. When interfacing ECl, an
IREF = 1mA is recommended. For interfacing other logic
families, see the figure. Pin 1 will source lOOtLA typically, so
the external circuitry must be designed to accommodate this
current. Note that the threshold voltage has the temperature
dependence of two forward biased diodes. The two VLC
setting circuits shown, include temperature compensation.
The DAC-20 provides excellent multiplying performance
with an extremely linear relationship between IFS and IREF
over a range of 2mA to 4tLA. Monotonic operation is maintained over a typical range of I REF from lOOtLA to 2mA.
LOGIC INPUT OPERATION AND INTERFACING
TTL
For V-= -15V, the logic inputs may swing between -10V and
+ 18V. This enables direct interface with a + 15V CMOS logic,
even when the DAC-20 is powered from a +5V supply. Minimum logic threshold voltage are given by: V- plus (IREF x
8000) plus 2.5V. The logic threshold may be adjusted over a
wide range by placing an appropriate voltage at the logic
threshold control pin (Pin 1, VLc).
CMOS, NMOS, PMOS
ACCOMMODATING BIPOLAR REFERENCES
V'
20kn
13kn
14
VIN~
DAC-20
3kn
3kn
TO PIN 1
39k.\1
20kn
15
TO PIN 1
VLe
VLe
R3
6.2kn
'REF> PEAK NEGATIVE SWING OF 'iN
-S.2V
14
LOGIC THRESHOLD CONTROL
VIN~
The DAC-20 design incorporates a unique logic input circuit
which enables direct interface to all popular logic families and
provides maximum noise immunity. This feature is made
possible by the large input swing capability, 2JJ.A logic input
current and completely adjustable logic threshold voltage.
R 15 (OPTIONAL) 15
DAC-20
RREF'" R16
V REF (+) MUST BE ABOVE. PEAK POSITIVE
SWING OF Y,N
11-48
1/86, Rev. A
---------I~ DAC-20 2-DIGIT BCD HIGH-SPEED MULTIPLYING D/A CONVERTER
proportionately increased values of Cc for proper phase
margin.
however, an artificial ground may be useful to insure logic
swings, etc., remain between acceptable limits.
For fastest response to a pulse, low values of R'4 enabling
small Cc values should be used. If Pin 14 is driven by a high
impedance such as a transistor current source, none of the
above values will suffice and the amplifier must be heavily
compensated, which will decrease overall bandwidth and
slew rate. For R'4 = 1kO and Cc = 15pF, the reference amplifier slews at 4mAl JJ.s enabling a transition from I REF=O to I REF
= 2mA in 500ns.
Power Consumption may be calculated as follows:
Pd = (1+) x (V+) + (1-) x (V-). A useful feature of the DAC-20
design is that supply current is constant and independent of
input logic states; this reduces the size of the power supply
bypass capacitors.
BURN-IN CIRCUIT
Operation with pulse Inputs to the reference amplifier may be
accommodated by the alternate compensation scheme shown
above. This technique provides lowest full-scale transition
times. An internal clamp allows quick recovery of the reference amplifier for a cutoff (IREF = 0) condition. Full-scale
transition (0 to 2mA) occurs in 120ns when the equivalent
impedance at Pin 14 is 2000 and C c = O. This yields a reference slew rate of 16mVI JJ.s, which is relatively independent of
RIN and V1N values.
NOTES
PULSED REFERENCE OPERATION
-18V
, RESISTORS ARE RS lA TYPE
2 CAPACITORS ARE CKR05BX102KL TYPE
3 CONNECT 0 O1 .. F SOV CAPACITORS FROM
V+ AND V- TO GROUND FOR EACH 6
VREF{+j
9
)
DEVICES
OPTIONAL RESISTOR
FOR OFFSET 1NPUTS
:: RREF
r
I
TEMPERATURE PERFORMANCE
'4
The nonlinearity and monotonicity specification of the
DAC-20 are guaranteed to apply over the entire rated operating temperature range. Full-scale output current drift is tight,
typically ± 10ppm/o C, with zero-scale output current and
drift essentially negligible compared to 1/2 LSB.
ovJL
TYPICAL VALUES
R 1N " 5k
V1N (+) '" lOV
NO CAP
The temperature coefficient of the reference resistor R'4
should match and track that of the output resistor for minimum overall full-scale drift.
POWER SUPPLY CONSIDERATIONS
SETTLING TIME OPTIMIZATION
The DAC-20 operates over a wide range of power supply
voltages from a total supply of 9V to 36V. When operating at
supplies of ±5V or less, IREF S; 1rnA is recommended. Low
reference current operation decreases power consumption
and increases negative compliance, reference amplifier
negative common-mode range, negative logic Input range,
and negative logic threshold range; consult the various
figures for guidance. For example, operation at -4.5V with
IREF = 2mA is not recommended because negative output
compliance would be reduced to near zero. Operation from
lower supplies is possible. However, at least 8V total must be
applied to insure turn-on of the internal bias network.
The DAC-20 is capable of extremely fast settling times, typically 85ns at IREF = 2.0mA. Judicious circuit design and
careful board layout must be employed to obtain full performance potential during testing and application. The output
capacitance of the DAC-20, including the package, isapproximately 15pF; therefore the output RC time constant dominates settling time if RL > 5000.
Fastest operation can be obtained by using short leads, minimizing output capacitance and load resistor values, and by
adequate bypassing at the supply, reference and VLC terminals. Supplies do not require large electrolytic bypass
capaCitors as the supply current drain is independent of input
logic states; 0.1JJ.F capaCitors at the supply pins provide full
transient protection.
Symmetrical supplies are not required, as the DAC-20 is
quite insensitive to variations in supply voltage. Battery
operation is feasible as no ground connection is required:
11-49
1/86, Rev. A
I
DAC-86
COMDAC® COMPANDING
D/A CONVERTER (w255 LAW)
Precision Monolithics Inc.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
.iiiiiiiiiiiiiliiiiii
+V FS -
Conforms With Bell System 1'"255 Companding Law
Meets 03 Compandor Tracking Specifications
Both Encode and Decode Capability
Tight Full-Scale Tolerance Eliminates Calibration
Low Full-Scale Drift Over Temperature
Extremely Low Noise Contribution
Multiplying Reference Inputs
Simplifies PCM System Design
High Reliability
Low Power Consumption and Low Cost
Two Grades Available
ANALOG
OUTPUT
0COMDAC®
TRANSFER
CHARACTERISTIC
-V FS -
o
x 000 0000
DIGITAL INPUT
111 1111
GENERAL DESCRIPTION
The DAC-86 monolithic COMDAC® D/A Converter provides
a 15 segment linear approximation to the Bell System ,.,-255
companding law. The law is implemented by using three bits
to select one of eight binarily-related chords (or segments)
and four bits to select one of sixteen linearly-related steps
within each chord. A sign bit determines signal polarity, and
an encode/decode input determines the mode of operation.
Accuracy is assured by specifying chord end point values,
step nonlinearity, and monotonicity over the full operating
temperature range. Typical applications include PCM carrier
systems, digital PBX's intercom systems, and PCM recording.
For CCITT "A" Law models, refer to the DAC-89 data sheet.
PIN CONNECTIONS & ORDERING INFORMATION
ENCODE/DECODE SELECT
1 = ENCODE
SIGN BIT INPUT
1"" POSITIVE
MOST SIGN I FreANT CHORD
BIT INPUT
SECOND CHORD BIT INPUT
LEAST SIGNIFICANT
CHORD BIT INPUT
MOST SIGNIFICANT STEP
BIT INPUT
1
18
In(1+l'lxl)
< <
_
Y(x) - sgn(x)
In(1 + 1') -1 - x - 1
for a normalized coding range of ± 1
where: x = input signal level
Y = output compressed signal level
I' = 255
This law is implemented with a eight chord (or segment)
piecewise linear approximation with 16 linear steps in each
chord. Dynamic range of 72dB in both polarities is achieved
with eight-bit coding.
EQUIVALENT CIRCUIT
00
=
16
DECODe OUT E/D Sa = 01
4
15
ENCODE OUT E/O S8 = 10
5
14 ENCODe OUT E/O S8
13
BELL 1'"255 LAW TRANSFER CHARACTERISTIC
The DAC-86 transfer characteristic is a piecewise linear
approximation to the Bell System ,.,-255 law expressed by:
POSITIVE POWER SUPPL Y
DECODE OUT E/D S8
=
I
, ", ""
STEP
INPUTS
CHORD
INPUTS
SB
87 86 65 84
E/D
11
NEGATIVE POWER SUPPLY
NEGATIVE REFERENCE
INPUT
SECOND STep BIT INPUT
7
THIRD STEP BIT INPUT
8
11
m~G~VE REFERENCE
LEAST SIGNIFICANT STep
BIT INPUT
9
10
lOGIC THRESHOLD
CONTROL
l8-PIN HERMETIC DUAL-IN-LINE
(X-Suffix)
REFERENCE
AMPLIFIER
GRADE
DAC-86EX
DAC-86CX
TEMP. RANGE
-25° C!+85° C
-25° C!+85° C
ACCURACY
±1/2 Step
±1 Step
13
V~
11-50
V+
VLe
1/86, Rev. A
------------I~ DAC-86 COMDAC@COMPANDINGD/ACONVERTER
ABSOLUTE MAXIMUM RATINGS
V+ Supply to V- Supply
•••••••••••••••••••••••••••
36V
Logic Inputs
.................. V- plus SV to V- plus 36V
VLC Swing ••.•••••••••••••••••••••••••• V- plus SV to V+
Operating Temperature
Analog Current Outputs
Storage Temperature
••••••• V- plus SV to V- plus 36V
••••.•••••••••••
•••••••••••••••••
-25°C to +S5°C
-65° C
Reference Inputs •••••••••••••••••••••.•.•••••• V- to V+
Power Dissipation
Reference Input Differential Voltage
Derate Above 100°C ..........................
Reference Input Current
•.••.•••.••••.• ± 1SV
•••••••••••••••••••••••• 1.25mA
ELECTRICAL CHARACTERISTICS
at Vs
to +
150° C
•••••••••••.••.•.••..•....•••• 500mW
10mW/oC
Lead Temperature (Soldering, 60 sec) •••.••••••••• 300°C
= ±15V, IREF = 52S.uA. -25° C:S TA:S +S5° C, for all 4 outputs, unless otherwise
noted.
DAC-86E
PARAMETER
SYMBOL
CONDITIONS
Resolution
8 chords with 16 steps each
Dynamic Range
20 log (17.15''1 0 ."
Monotoniclty
Sign-Bit + or-
Chord End-Point Accuracy
All Chords
Error relative to Ideal values
at IFS = 2007.75pA
Encode DeCision Level Current
Additional output
encode/decode = 1
MAX
MIN
TYP
MAX
UNITS
±128
±128
±128
±128
±128
±128
Steps
72
72
72
72
72
72
dB
128
To within ±1/2 step
Full-Scale Drift (C7 ) (Note 2)
alFS
Full temperature range
Output Voltage Comphance
Voe
Full-Scale Symmetry Error
10 (+) - 10 (-)
Decode or encode pair
Input Code 111 1111
Zero-Scale Current (Co)
I zs
Measured at selected output
with 0000000 Input
Disable Current (All bits high)
'DIS
Leakage of output disabled
by ElD and SB
1/2
5/8
±1/16
±1/10
-5
" 1/2 step
+18
Logic Input Levels. LogiC "0"
V,L
VLe-OV
LogiC Input Levels. LogiC "1"
V ,H
VLe = OV
liN
Y,N = -5V to + 18V
LogiC Input Swing
V's
V-=-15V
Step
±1/10
±1/4
Step
+18
Volts
0
.....:l
-5
±1/40
±1/4
Step
1/40
1/8
1/40
1/4
Step
75
nA
±1
Step
0.8
0.8
Volts
120
120
pA
+18
Volts
75
±1/2
20
42
20
mA
Volts
-5
+18
-3
1'2
Reference Input Slew Rate
dl/dt
Power Supply SenSitiVity Over
Supply Range (Refer to
Characteristic Curves)
PSSI FS+
PSSI F5-
V+ = 4 5V to 18V. V- = -15V
V- = -10 8V to -18V. V+ = 15V
Power Supply Current
1+
11+
1-
Power Dissipation
Pd
-12
025
-5
-3
-12
025
pA
mAlJls
±1/20
±1/1O
±1/2
±1/2
±1/20
±1/10
±1/2
±1/2
Step
Vs =+5V.-15V.I FS =20mA
Vs = +5V. -15V. I FS = 2.0mA
Vs = ±15V. I FS = 2.0mA
Vs = ±15V, I FS = 2.0mA
27
-6.7
2.7
-6.7
45
-93
45
-9.3
2.7
-67
27
-67
4.5
-93
45
-93
mA
Vs = +5V, -15V, I FS = 2.0mA
Vs = ±15V, I FS = 2.0mA
114
141
167
207
114
141
167
207
mW
NOTE:
1. Inacompanding DACtheterm LSB IS not used because the step size within
each chord is different For example, In the first chord around zero (Col
step size is O.5~A, while In the last chord near full-scale (C 7) step size is
64~A Settling time vanes for each of the chord bits and step bits and a
maximum specification IS misleadmg. In decode operatIOn, the DAC-86
and OP-16 combination will decode eight channels In the encode mode,
the DAC-86 and CMP-01 combinatIOn Will encode eight channels. Both
encode and decode statements assume a 5.2~sec channel time.
Guaranteed by design
1/86, Rev. A
11-51
-----
U
C)
0
~
~
Reference Bias Current
-----=----~.--------
3/4
±1/8
4.2
Logic Input Current
~
0
1/2
±1/40
Error relative to Ideal values
at IFS = 2007.75pA
I FSR
1/4
~
Step
J,tsec
Full-scale current change
Output Current Range
Steps
~
i:.J.:I
±1
±1/2
3/8
ts
Step Accuracy
All Chords
TYP
128
Setthng Time (Note 1)
U)
DAC-86C
MIN
--~--.---.~------
--
--
"...,---~-------.-----
~
,.....
C)
,.....
Q
II
------------1!EMD DAC-88 COMDACIS COMPANDING D/A CONVERTER
OUTPUT CURRENT DC TEST CIRCUIT
"'
LINE SELECTION TABLE
+VREF
""
ENCODEI
DECODE
SIGN
BIT
1
10E(+)
2
1
0
10E(-)
(E01 /R2 )
3
0
1
100(+)
(E02/R3 )
4
0
0
100H
(E02/R4 )
TEST
GROUP
1
18.94kll
~RAEFJ
11
"'2
20k1l
-15V
+16V
(E01 /R1 )
NOTE: Accuracy Is specified In the test circuit using the tables below to be
within the specified proportion of a step at the maximum value In each chord.
Monotonlclty Is guaranteed for all Input codes.
R1 .. A2 "' R3" A4 .. 2.5kll
·VREF IS ADJUSTED BEFORE TESTING EACH DEVICE
TO PROVIDE IDEAL FULL SCALE OUTPUT CURRENT.
OUTPUT
MEASUREMENT
':"
CONDENSED CURRENT OUTPUT TABLES (lREF = 528j.1A)
IDEAL DECODE OUTPUT CURRENT IN MICROAMPS AT CHORD ENDPOINTS
~
STEP
0000
15
1111
STEP SIZE
4
6
000
001
010
011
100
101
110
111
0.0
8.25
24.75
57.75
123.75
255.75
519.75
1047.75
7.5
23.25
54.75
117.75
243.75
495.75
999.75
2007.75
2
4
8
16
32
64
0.5
IDEAL ENCODE OUTPUT CURRENT IN MICROAMPS AT CHORD ENDPOINTS
~
STEP
0
15
0
4
000
001
010
011
100
101
110
111
0000
0.25
8.75
25.75
59.75
127.75
263.75
535.75
1079.75
1111
7.75
23.25
55.75
119.75
247.75
503.75
1015.75
2039.75
16
32
64
STEP SIZE
0.50
4
NOTE:
These tables may be extended to Include all of the encode/decode currents
(Ideal with SI REF =528I'A) by multiplying anyof the numbers in the normalized
tables by 0.51'A.
PARAMETER DEFINITIONS
CHORD ENDPOINTS
FULL-SCALE DRIFT
The maximum code in each chord; used to specify accuracy.
The change in output current over the full operating temperature
with VREF= 10.000V, Rll = lB.94kO, and R12= 20kO.
STEPS
FULL-SCALE SYMMETRY ERROR
Increments in each chord which divides the chord into
16 equal levels.
The difference between 100(-) and 100(+) or the difference
between 10E(-) and 10E(+) at full-scale output.
OUTPUT LEVEL NOTATION
OUTPUT VOLTAGE COMPLIANCE
Each output current level may be deSignated by the code
Ie,s where C = chord number and S = step number. For
example, 10,0 = zero-scale current; 10,1 = first step from zero;
10,15 = endpoint of first chord (Co); 17,15 = full-scale current.
The maximum output voltage swing at any current level
which causes < 1/2 step change in output current.
CHORDS
DYNAMIC RANGE
Groups of linearly-related steps in the transfer function. Also
known as segments.
Ratio of full-scale current to step size in chord zero, expressed
in dB. This can be measured peak or peak-to-peak with the
same result.
11·52
1/86, Rev. A
-------------im DAC-88 COMDAce COMPANDING D/A CONVERTER
magnitude AID converter. However, a compressing AID has
one significant difference. In a conventional (linear converter), the step size Is a constant percentage of full-scale. In a
compressing AID converter, the step size Increases as the
output changes from zero-scale to full-scale.
BASIC ENCODE OPERATION
(COMPRESSING AID CONVERSION)
BASIC ENCODE CONNECTIONS
±&V ANALOG INPUT
When the DAC Is used In the feedback loop of a successive
approximation analog to digital converter (ADC) the DAC
outputs are used as decision levels to determine the edges of
the quantizing bands. When the DAC Is used In the decode
mode the outputs correspond to the center of the quantizing
bands. The encode mode output exceeds the decode mode
output by one-half step. See AN-39 for detailed explanation.
r-I
'*
GROUND
FOA
SINGLE
ENDED
INPUTS
SUCCESSIVE
APPROXIMATION
REGISTER
DIGITAL
OUTPUTS
ISAAI
SIGN
BIT
tt1*S=~
JCHOAD
I1
BITS
BITS
JSTEP
123458789
VFlEF
+fOV
A"
2Ok"
-16V
+1BV
ENCODE DECISION LEVELS
Compressing A/D conversion with the DAC-86 requires a
comparator, an EXCLUSIVE-OR gate, and a successive
approximation register - the usual elements in any sign-
ENCODING SEQUENCE
An encoding sequence begins with the sign-bit decision.
During this time the comparator functions as a polarity detector. The encode/decode (E/D) input is held at a logic "0". In
this mode, current flows into the decode outputs, and the
comparator is effectively disconnected from the DAC. Once
the Input polarity has been determined, the ElD input toggles
to a logic "1" allowing current to flow into IOE(+) or IOE(-)'
For positive Inputs, currentflows Into IOE(+) through R1, and
the comparator's output Is entered as the answer for each
successive decision. For negative inputs, current flows into
IOE(-) through R2 developing a negative voltage which Is
compared with the analog Input. An EXCLUSIVE-OR gate
Inverts the comparator's output during negative trials to
maintain the proper logic coding, all ones for full-scale and
all zeros for zero-scale.
The bits are converted with a successive removal technique,
starting with a decision at the code 011 1111 and turning off
bits sequentially until all decisions have been made.
C = chord no. (0 through 7)
S = step no (0 through 15)
NORMALIZED ENCODE LEVEL (SIGN BIT EXCLUDED) (Ic,s= 2[2 c (S + 17) -16.5]
~
STEP
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
4319
0
0000
1
35
103
239
511
1055
2143
1
0001
3
39
111
255
543
1119
2271
4575
2
0010
5
43
119
271
575
1183
2399
4831
3
0011
7
47
127
287
607
1247
2527
5087
4
0100
9
51
135
303
639
1311
2655
5343
5
0101
11
55
143
319
671
1375
2783
5599
6
0110
13
59
151
335
703
1439
2911
5855
7
0111
15
63
159
351
735
1503
3039
6111
8
1000
17
67
167
387
767
1567
3167
6367
9
1001
19
71
175
383
799
1631
3295
6623
10
1010
21
75
183
399
831
1695
3423
6879
11
1011
23
79
191
415
863
1759
3551
7135
12
1100
25
83
199
431
895
1823
3679
7391
13
1101
27
87
207
447
927
1887
3807
7647
14
1110
29
91
215
463
959
1951
3935
7903
1111
31
95
223
479
991
2015
4063
8159
4
8
16
32
64
128
256
15
STEP SIZE
11-53
1/86, Rev. A
•
•
------------IIEMD DAC-86 COMDACII!> COMPANDING D/A CONVERTER
100(+) forcing a positive voltage atthe operational amplifier's
output. When the sign-bit input is low, logic "0", all of the
output current flows into 100(-) through R2 forcing a negative
voltage output. The sign-bit steers current into 100(+) or
100(-), therefore the output will always be symmetrical,
limited only by the matching of R1 and R2.
ENCODE TRANSFER CHARACTERISTICS
(AID CONVERSION)
DIGITAL
OUTPUT 1+)
DECODE TRANSFER CHARACTERISTIC
(D/A CONVERSION)
ANALOG
OUTPUT (+)
DIGITAL
OUTPUT (-J
BASIC DECODE OPERATION
(EXPANDING Df A CONVERSION)
0/A conversion with the OAC-86 is implemented by using an
operational amplifier connected to the decode outputs. The
decode mode of operation is selected by applying a logic "0"
to the encode/decode input. This enables the 100(+) or
100(-) to be selected by the sign-bit input. When the sign-bit
input is high, a logic "1 ", all of the output current flows into
ANALOG
OUTPUT 1-)
NORMALIZED DECODE OUTPUT (SIGN BIT EXCLUDED) (lc,s=2[2 C (5+ 16.5) -16.5J
~
STEP
C =chord no. (Othrough 7)
5=step no (Othrough 15)
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
0
0000
0
33
99
231
495
1023
2079
4191
1
0001
2
37
107
247
527
1087
2207
4447
2
0010
4
41
115
263
559
1151
2335
4703
3
0011
6
45
123
279
591
1215
2463
4959
4
0100
8
49
131
295
623
1279
2591
5215
5
0101
10
53
139
311
655
1343
2719
5471
6
0110
12
57
147
327
687
1407
2847
5727
7
0111
14
61
155
343
719
1471
2975
5983
8
1000
16
65
163
359
751
1535
3103
6239
9
1001
18
69
171
375
783
1599
3231
6495
10
1010
20
73
179
391
815
1663
3359
6751
11
1011
22
77
187
407
847
1727
3487
7007
12
1100
24
81
195
423
879
1791
3615
7263
13
1101
26
85
203
439
911
1855
3743
7519
14
1110
28
89
211
455
943
1919
3871
7775
15
1111
30
93
219
471
975
1983
3999
8031
16
32
64
128
256
STEP SIZE
4
11-54
1/86, Rev. A
-----------I~ DAC-86 COMDAC8 COMPANDING D/A CONVERTER
NORMALIZED TABLES
BASIC DECODE CONNECTIONS
The encode and decode tables are used to calculate the ideal
output current at any point. For example, in decode mode at
13.7 (011 0111) find 343. 343/8031 x IFS = 85.75/lA (IFS =
2007.75/lA). Alternatively. use the condensed current tables
and add up the number of steps.
R1
25kO
R11
18.94kO
(RREf)
IREF
BASIC REFERENCE CONSIDERATIONS
R12
20kn
Full-scale output current is ideally 2007 .75/lA when the reference current is 528/lA in the decode mode. In the encode
mode IFS= 2039.75/lA due to the additional 112 step (32/lA).
A percentage change in IREF will produce the same percentage change in output current.
IREF=~
IDEAL VALUES
'REF = 528pA
IFS = 2016j.1A
The large step size at full-scale allows the use of inexpensive
references in many applications. In some situations VREF may
even be the positive power supply. For example, with V+ =
15V, RREF= 15V/528/lA or 28.4kO. When using a power supply
as a reference. R11 becomes two resistors, R11 A and R11 B,
and the junction bypassed to ground with a 0.1/lf monolithic
capacitor.
NOTE: THIS CONFIGURATION WILL DECODE 24 CHANNELS
REFERENCE AMPLIFIER SETUP
The CAe-86 is a multiplying CIA converter. The output current is the product of the normalized digital input and the
input reference current. The reference current may be fixed
or may vary from nearly zero to + 1.0mA. The full-scale output
current is a linear function of the reference current.
DECODE OUTPUT VOLTAGE
E/D SB B1 B2 B3 B4 B5 B6 B7 VOLT
o
1
(+) ZERO-SCALE +1 STEP 0
1
0
0
0
0
0
0
1
o
1
0
0
0
0
0
0
0
OV
000000000
OV
POS FULL-SCALE
(+)
ZERD-SCALE
(-) ZERO-SCALE
(-) ZERO-SCALE +1 STEP 0
0
0
0
o
0
1
1
NEG FULL-SCALE
In external reference applications a positive reference voltage forces currentlhrough R11 in the the VR(+) terminal (pin
11) of the reference amplifier. Alternatively, a negative reference may be applied to VR(-) at pin 12; reference current
flows from ground through R11 into VR(+). This negative
reference connection has the advantage of presenting a very
high impedance at pin 12. The voltage at pin 11 isequal toand
tracks the voltage at pin 12 due to the high gain olthe internal
5019V
0
0
0
0.0012
-00012
0
-5.019V
I
SYSTEM TEST CIRCUIT
MULTIPLEXER
MULTIPLEXER
D/A
AiD
.
OAeSAMPLE/HOLD
ANALOG
CHANNELS
CMNn
IN
1-_ _-', r-:;;;:;:--"---~
j
ANALOG
CHANNELS
OUT
REF01/02
CROSSTALK
-75dB
IDLE CHANNEL NOISE
21dBnc
(AVERAGE CHANNEL VALUE)
NOTES
118kHz SAMPLING CONDITIONS AID CONVERSION TIME
1554j.1s
2 AUDIO TEST ANALYZER CONTAINS AC MESSAGE FILTER
AND 3kHz FLAT FILTER
11-55
1/86, Rev. A
-----------l1£MD
DAC-88 COMDAC® COMPANDING D/A CONVERTER
accomplished by selecting Rll or by using a potentiometer
for Rll.
reference amplifier. R12 (nominally equal to Rll) is used to
cancel bias current errors and may be eliminated with a
minor increase in error.
Using lower values of reference current reduces negative
power supply current and increases reference amplifier negative common-mode range. While the recommended operating range of DC reference current is 0.1 rnA to 1.0mA, monotonic operation is maintained over an even wider range.
POSITIVE REFERENCE OPERATION
VRH
+10V
RnA
LOGIC INPUT AND POWER SUPPLY
CONSIDERATIONS
DIGITAL INPUTS
INTERFACING CIRCUIT FOR
ECl, CMOS, HTl, AND NMOS lOGIC INPUTS
ENCODE
OUTPUTS
DECODE
OUTPUTS
Eel
CMOS, HTL, NMOS
V'
VREF
IREF = RREF
DECODE OUTPUTS
IDEAL VALUES
ENCODe OUTPUTS
IDEAL VALUES
IREF"" 528.uA
IFS '" 201611A
IREF "" 528iJA
IFS
=
13k.Q
2048J,1A
NOTES
,
2
RECOMMENDED WHEN VREF IS V+ OR THE LOGIC POWER SUPPLY
PINS'1 AND 12 ARE eQUAL IN VOLTAGE VREF IS IMPRESSED
ACROSS Rll (RREF)
20k.l1
"A"
"A"
39kS1
20k.l1
52V
NOTES.
1
SET THE VOLTAGE "A" TO BE AT THE DESIRED LOGIC INPUT
SWITCHING THRESHOLD
2
ALLOWABLE RANGE OF LOGIC THRESHOLD IS TYPICALLY
-5V TO +13V WHEN OPERATING THE DAC-S6 ON ±15V SUPPLIES
NEGATIVE REFERENCE OPERATION
ENCODE
OUTPUTS
lOGIC INPUTS
The DAC-86 interfaces with various logic families by referencing VLC (pin 10) at a potential which is 1.4V below the
desired logic input switching threshold. However, this
voltage source must be capable of sourcing and sinking a
changing current at pin 10.
DECODE
OUTPUTS
ENCODE OUTPUTS
DECODE OUTPUTS
IDEAL VALUES
IDEAL VALUES
IREF = 528iJA
lfS = 2016iJA
IREF '" 528}JA
IFS = 2048/.1A
The negative voltage at the logic inputs must be limited to
+ 10V with respect to V- (pin 13).
NOTE
PINS 11 AND 12 ARE EQUAL IN VOLTAGE VREF IS IMPRESSED
POWER SUPPLIES
ACROSS All (RREFl
Power supply current drain is relatively independent of
voltage and temperature and completely independent of the
logic input states.
When operating with V- between -15V and -l1V, output
negative voltage compliance, Voc(-), reference input
amplifier common-mode voltage range, and logic input
negative voltage range are reduced by an amount equivalent
to the difference between -15V and the V- supply in use.
Operation with V+ between +5V and +15V affects VLC and
the reference amplifier common-mode positive voltage range
in the same manner.
REFERENCE AMPLIFIER OPERATION
For most applications a + 10.0V reference, such as the PMI
REF-Ol, is recommended for optimum full-scale temperature
performance. (This also minimizes the contributions of reference amplifier Vos and TCVos). For most applications the
tight relationship between IREF and IFS eliminates the need
for trimming IREF; but if desired full-scale trimming is
11-56
1/86, Rev. A
-----------l1EMD DAC-88 COMDAC· COMPANDING D/A CONVERTER
SYSTEM PERFORMANCE CHARACTERISTICS
STANDARD OUTPUT CONNECTIONS
SIGNAL TO QUANTIZING DISTORTION vs INPUT LEVEL
VREF
~
"OY
5.
."on
z
1••1M
...9
II:
0
I;; 40
C
.'2
~
;!
20kn
0
~
~
3.
"in
"
Z
20
--5.
STANDARD ENCODE/DECODE
CONNECTIONS REQUIRE
1VocHI <: IVAmul
-40
-30
-2.
-1.
+1.
INPUT lEVEL IdBmO_1_ _ C MSG WTG
I.ILAW _ _ _ _ 3kHz FLAT
OUTPUT COMPLIANCE EXTENSION CONNECTIONS
GAIN TRACKING
Rl
COMPARATOR
VREF
+10V
...
,."on
+15
_ +10
~
:3 -+05
z
~
00
.'2
~~~~~~~~~~~~~~~~~
20kn
~
~
~
-05
-1.
-3.
-20
-1.
EXTENDED RANGE CONNECTION ALLOWS
-0
V Anth <: Vocl-l/n
WHERE n .. R2JR1 + R2
INPUT LEVEL (dBmOI
-16
VA MUST DRIVE Rl
+ R2
" L A W - - - C MSGWTG
____ 3kHz FLAT
NEGATIVE OUTPUT VOLTAGE COMPLIANCE Voc(-)
OUTPUT VOLTAGE COMPLIANCE
The DAC-86 has true current outputs with wide voltage compliance that enables single ended and balanced load drive
capability. Positive voltage compliance is +18V and negative
voltage compliance is -5.0V with IREF= 528~A and V = -15V.
Negative voltage compliance Voc(-) for other values of IREF
and V- may be obtained from the table, or calculated as
follows:
VOC(-) min = (V-)
V-
1.0mA
IFS
2.0mA
-12V
-2.SV
-2.0V
-O.4V
-1SV
-S.SV
-S.OV
-3.4V
-1SV
-S.SV
-S.OV
-6.4V
4.0mA
MINIMUM NEGATIVE COMPLIANCE
VOC(-) MIN = (V-) + (2 IREF 1.6kO) + S.4V
+ (2 IREF X 1.6kO) + 8.4V
Output voltage compliance can be extended in both encode
and decode modes using the connections shown above.
DICE
For applicable DICE information, see DAC-88 Data Sheet.
11-57
1/86, Rev. A
II
DAC-88
COMDAOs> COMPANDING
D/A CONVERTER (~-25S LAW)
Precision M0l101ithics Inc.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
GAIN TRACKING
IMPROVED ACCURACY over DAC-86
IMPROVED SPEED over DAC-86
Conforms With Bell System 1'"255 Companding Law
Meets 03 Compandor Tracking SpeCifications
Both Encode and Decode Capability
Tight Full-Scale Tolerance Eliminates Calibration
Low Full-Scale Drift Over Temperatura
Extremely Low Noise Contribution
Multiplying Reference Inputs
Simplifies PCM System DeSign
High Reliability
Low Power Consumption and Low Cost
Fully Specified Dice Available
-15
fA) GAIN TRACKING PERFORMANCE OF DAC-88IN 8-CHANNEL SYSTEM
GENERAL DESCRIPTION
BELL 1'"255 LAW TRANSFER CHARACTERISTIC
The DAC-88 monolithic COMDACI8> D/A Converter provides
a 15 segment linear approximation to the Bell System 1'"255
companding law. The law is implemented by using three bits
to select one of eight binarily-related chords (or segments)
and four bits to select one of sixteen linearly-related steps
within each chord. A sign bit determines signal polarity, and
an encode/decode input determines the mode of operation.
The DAC-88 transfer characteristic is a piecewise linear
approximation to the Bell System 1'255 law expressed by:
Y(x) = sgn(x)
In(1+l'lxl)
< <
In(1 + 1') -1 - x - 1
for a normalized coding range of ± 1
where: X = input signal level
Y = output compressed signal level
I' = 255
Accuracy is assured by specifying chord end point values,
step nonlinearity, and monotonicity over the full operating
temperature range. Typical applications include PCM carrier
systems, digital PBX's, intercom systems, and PCM recording. For CCITT "A" Law models, refer to the DAC-89 data
sheet.
This law is implemented with an eight chord (or segment)
piecewise linear approximation with 16 linear steps in each
chord. DynamiC range of 72dB in both polarities is achieved
with eight-bit coding.
PIN CONNECTIONS & ORDERING INFORMATION
EQUIVALENT CIRCUIT
ENCODE/DECODE SELECT
1 = ENCODE
SIGN BIT INPUT
1 = POSITIVE
MOST
1
POSITIVE POWER SUPPl Y
2
DECODE OUT E/D S8 '" 00
SIGNIFICA~JT~~~~~
SECOND CHORD BIT INPUT
LEAST SIGNIFICANT
CHORD BIT INPUT
MOST
STEP
INPUTS
87 86 B5 B4
DECODE OUT E/D SB = 01
ENCODE OUT E/D
sa = 10
14
ENCODE OUT E/D
sa = 11
13
NEGATIVE POWER SUPPLY
4
5
SIGNIFIC~~~~;~~
SECOND STEP BIT INPUT
7
THIRD STEP BIT INPUT
8
LEAST SIGNIFICANT STEP
BIT INPUT
9
CHORD
INPUTS
8382 B1
sa
'/0
~J~'tTIVE REFERENCE
L.._ _- '
11
r~~~~'VE REFERENCE
10
LOGIC THRESHOLD
CONTROL
VRf'l <>-',,+-,......--.,
18-PIN HERMETIC DUAL-IN-LiNE
(X-Suffix)
REFERENCE
AMPLIFIER
,.
DAC-8S
Grade
DAC-88EX
Temp. Range
-25°C/+85°C
13
Accuracy
±1/4 Step
V-
11-58
18
V·
VLe
1/86, Rev. A
-------------I1fMD
DAC·88 COMDAC~ COMPANDING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
V+ Supply to V- Supply. • • • • • • • •• • •• • • • • • . • • • • • • • •• 36V
VLC Swing •••.••••••••••••••••••.•••••• V- plus SV to V+
Analog Current Outputs ••••••• V- plus SV to V- plus 36V
Reference Inputs ••.•••.•••••••••••••••••.•...• V- to V+
Reference Input Differential Voltage ••••.•••.•••••• ± 1SV
Reference Input Current ••••••••.••••••••.•.•••• 1.2SmA
Logic Inputs •••••••••••••.•••• V- plus SV to V- plus 36V
Operating Temperature ••••••••.•••••••
-2S·C to +SS·C
Storage Temperature •••••••••.••••••• -6S·C to +1S0·C
Power Dissipation •••••••••.•••.•.•••••••••••••• SOOmW
Derate Above 100·C •...•........•••..••••.••• 10mW/·C
Lead Temperature (Soldering, 60 sec) •••.••••.•.•• 300·C
NOTE: Absolute ratings apply to both DICE and packaged parts. unless
otherwise noted.
ELECTRICAL CHARACTERISTICS at Vs=± 1SV, IREF= S2SI'A, -2S· C:STA:S+SS· C, all 4 outputs, unless otherwise noted.
DAC·88E
PARAMETER
SYMBOL
Resolution
CONOITIONS
8 chords with 16 steps each
MIN
TYP
MAX
UNITS
±128
±128
±128
Steps
72
72
72
V')
~
~
~
Dynamic Range
20 log (i7,1s110,11
Monotonicity
Sign-Bit + or -
Chord End-POint Accuracy
Chord Zero
Error relative to Ideal values
at I FS = 2007 75"A
±1/4
Step
0
Chord End-Point Accuracy
All Chords Other Than Zero
Error relative to Ideal values
at I FS = 2007 75"A
±1/2
Step
C)
Encode Decision Level Current
Additional output
encode/decode = I
5/8
Step
Settling Time (Note I)
Settling Time In Chord Zero
128
dB
Steps
U
0
3/8
1/2
ts
To within ± 1/2 step
500
ns
Tseo
To within ±1/2 step
500
ns
Full-scale Drift (C 7 ) (Note 3)
Full temperature range
Output Voltage Compliance
Voe
Full-Scale current change
S 1/2 step
Full-Scale Symmetry Error
(Note 2)
10 (+)-1 0 (-)
Decode or encode pair
Input Code 1111111
Zero-Scale Current (Co)
(Note 2)
Izs
Measured at selected output
with 0000000 Input
±1/16
±I/IO
Step
+18
Volts
±1/4O
±1/8
Step
1/40
1/8
Step
5
-5
Leakage of output disabled
by ElDand SB
100
nA
Step Accuracy
Chord Zero
Error relative to ideal values
at I FS = 2007 75"A
±1/4
Step
Step Accuracy
All Chords Other Than Zero
Error relative to ideal values
at I FS = 2016"A
±1/2
Step
Output Current Range
42
Vle = OV
Logic Input Current
Y,N = -5V to + 18V
Logic Input Swing
V'S
V-=-15V
-3
V+ = 4.5V to 18V, V- = -15V
V- = -10.8V to -18V, V+ = 15V
__
._----
"A
+18
Volts
-12
±1/20
±I/IO
"A
mAl"s
±1/2
±1/2
Step
DAC-88 and CMP-DI combination will encode eight channels. Both
encode and decode statements assume a 5.2"s channel time.
2. Current specifications relate to differential currents between (+) and H
output leads. At the selected outputs, equal idle currents are present
simultaneously on both current output leads.
3. Guaranteed by design.
1/86, Rev. A
11-59
.
120
025
NOTES:
I. In a companding DAC the term LSB is not used because the step size
within each chord is different. For example, in the first chord around zero
(Co) step size IsO.5"A, while in the last chord near full-scale (C 7 ) step size
Is 84"A. Settling time varies for each of the chord bits and step bits and a
maximum specification is misleading. In decode operation, the DAC-88
and OP-16 combination Will decode 24 channels In the encode mode, the
-~
rnA
Volts
Volts
-5
dl/dt
Power Supply Sensitivity Over
Supply Range (Refer to
Characteristic Curves)
0
08
2
Reference Bias Current
Reference Input Slew Rate
2.0
Vle = OV
Logic Input Levels. Logic "I"
-~
.~.------
~
~
0
~
~
C)
......
Q
Disable Current (All bits high)
(Note 2)
Logic Input Levels, Logic "0"
~
II
------------1M
DAC-88 COMDAC- COMPANDING DlA CONVERTER
ELECTRICAL CHARACTERISTICS at Vs= ±15V, IREF= 528~A, -25"C S TAS +85"C, all 4 outputs, unless
otherwise noted. (Continued)
DAC-88E
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply Current
1+
11+
1-
Vs =+5V.-15V.I FS =2.0mA
Vs = +5V, -15V, IFS = 2.0mA
Vs =±15V,I FS =2.0mA
Vs =±lSV.I FS =2.0mA
2.7
-6.7
2.7
-8.7
5.5
-12
5.5
-12
mA
Power Dissipation
Pd
Vs = +SV. -lSV. IFS = 2.0mA
Vs = ±15V. I FS = 2.0mA
114
141
207
262
mW
Full-Scale Current Deviation
From Ideal Deviation
(See Tables) (Note 2)
IFS(D)
IFS(E)
VREF 10.000V, TA = 25' C
Rll = 19.53kO, R12 = 20kO
±1/2
±1/2
Step
Idle Current (Note 2)
II
10
!SA
NOTE:
2. Current specifications relate to differential currents between (+) and (-)
output leads. At the selected outputs. equal Idle currents are present
simultaneously on both current output leads.
DICE CHARACTERISTICS
1. ElD
2.
3.
4.
5.
6.
7.
8.
9.
SIGN-BIT
BIT 1 (MSB)
BIT2
BIT3
BIT4
BITS
BIT6
BIT 7 (LSB)
10. VLC
11. VR (+)
12. VR (-)
13. V14. IOE (+)
15. 10E (-)
16. 100 (+)
17.100(-)
18. V+
For additional DICE information refer to
1986 Data Book, Section 2.
DIE SIZE 0.123 X 0.085 Inch, 10,455 sq. mils
(3.124 X 2.159 mm, 6.745 sq. mm)
WAFER TEST LIMITS at Vs= ±15V, IREF= 5281'A, TA=25°C, all 4 outputs, unless otherwise noted.
DAC-88N
PARAMETER
SYMBOL
Resolution
CONDITIONS
8 chords with 16 steps each
Dynamic Range
20 log (1 7, ,si'o, ,)
Monotonicity
Sign-Bit+ or-
Chord End-Point Accuracy
Chord Zero
(NOTE 3)
LIMIT
UNITS
±128
Steps MIN
72
dB MIN
128
Steps MIN
Error relative to Ideal values
atl Fs = 2007.7SI'A
±1I4
Step MAX
Chord End-Point Accuracy
All Chords Other Than Zero
Error relative to Ideal values
at I FS = 2007. 751'A
±1/2
Step MAX
Encode Decision Level
Current
Additional output
encode/decode = 1
3/8
5/8
Step MIN
Step MAX
-5
+18
Volts MIN
Volts MAX
Output Voltage Compliance
Voe
Full-scale current change
S 1/2 step
11-60
1/86, Rev. A
_ _ _ _ _ _ _ _ _ _-I~DAC.88 COMDAce COMPANDING D/A CONVERTER
WAFER TEST LIMITS
at Vs= ±15V, IREF= 5281'A, TA = 25°C,
8114 outputs,
unless otherwise noted. (Continued)
DAC·88N
(NOTE 3)
PARAMETER
SYMBOL
CONDITIONS
Full-Scale Symmetry Error
(Note 2)
10 +-1 0 -
Decode or encode pair
Input Code 1111111
Zero-Scale Current (Note 2)
Izs
Disable Current (All bits high)
(Note 2)
lOIS
LIMIT
UNITS
±1/8
Step MAX
Measured at selected output
0000000 input
1/8
Step Max
Leakage of output disabled
by ElD and SB
100
nAMAX
Step Accuracy
Chord Zero
Error relative to Ideal values
at IFS = 2oo7.75"A
±1/4
Step MAX
Step Accuracy
All Chords Other Than Zero
Error relative to Ideal values
at IFS = 2016"A
±1/2
Step MAX
4.2
mAMIN
Output Current Range
I FSR
Logic Input Levels. Logic "0"
VIL
VLC=OV
0.8
Volts MAX
Logic Input Levels. Logic "I"
VIH
VLC=OV
2
Volts MIN
Logic Input Current
liN
VIN= -5V to +18V
120
"A MAX
VIS
V-=-15V
-5
+18
Volts MIN
Volts MAX
Logic Input Swing
Reference Bias Current
112
-12
"A MAX
Power Supply Sensitivity Over
Supply Range
PSSI FSPSSI FS-
V+ = 4.5V to 18V
V- = -10.8V to -18V
±112
±1/2
Step MAX
Step MAX
1+
1-
Vs =±15V.IFS=2.0mA
5.75
-12.0
mAMAX
1+
1-
Vs = ±15V. IFS= 20mA
5.75
-12.0
mAMAX
IFSD
VREF 10.000V. TA = 25'C
±1/2
Step MAX
IFSE
Rll = 19.53kO
R12 =20kO
±1/2
Step MAX
Power Supply Current
Full-Scale Current Deviation
From Ideal Deviation
(See Tables) (Note 2)
NOTE:
Electrical tests performed at wafer probe to the limits shown. Due to variations in assembly methods and normal Yield loss. yield aiter packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing
TYPICAL ELECTRICAL CHARACTERISTICS
at Vs = ± 15V, and TA = 25° C, unless otherwise noted.
DAC·88N
PARAMETER
SYMBOL
CONDITIONS
TYPICAL
UNITS
Settling Time (Note 1)
ts
To within ± 1/2 step
500
ns
Settling Time in Chord Zero
Tsco
To within ±1/2 step
500
ns
Full-Scale Drift (C 7)
COMPANDING D/A CONVERTER
When the DAC is used in the feedback loop of a successive
approximation analog to digital converter (ADC) the DAC
outputs are used as decision levels to determine the edges of
the quantizing bands. When the DAC is used in the decode
mode the outputs correspond to the center of the quantizing
bands. The encode mode output exceeds the decode mode
output by one-half step. See AN 39 for detailed explanation.
BASIC ENCODE OPERATION
(COMPRESSING AID CONVERSION)
ENCODE DECISION LEVELS
Compressing AID conversion with the DAC-88 requires a
comparator, an EXCLUSIVE-OR gate, and a successive
approximation register - the usual elements in any sign
magnitude AID converter. However, a compressing AID has
one significant difference. In a conventional (linear converter), the step size is a constant percentage of full-scale. I n a
compressing A/D converter, the step size increases as the
output changes from zero-scale to full-scale.
ENCODING SEQUENCE
An encoding sequence begins with the sign-bit decision.
During this time the comparator functions as polarity detector
only. The Encode/Decode (ElD) input is held ata logic "0". In
this mode current flows into the decode outputs, and the
comparator is effectively disconnected from the DAC. Once
the input polarity has been determined, the ElD input toggles
to a logic "1" allowing current to flow into 10E(+) or 10E(-)'
BASIC ENCODE CONNECTIONS
For positive inputs, currentflows into 10E(+) through R1, and
the comparator's output is entered as the answer for each
successive decision. For negative inputs, current flows into
10E(-) through R2 developing a negative voltage which is
compared with the analog input. An EXCLUSIVE-OR gate
inverts the comparator's output during negative trials to
maintain the proper logic coding, all ones for full-scale and
all zeros for zero-scale.
±5VANALOG
INPUT
~
+
r-I
-:;:-
FOR
GROUND
Rl
2."
SINGLE
ENDED
INPUTS
SUCCESSIVE
APPROXIMATION
L.
-15V
__
-t~~REiG~'S:TEiRj'S~AR~'q~--<> OUTPUTS
DIGITAL
The bits are converted with a successive removal technique,
starting with a decision at the code 011 1111 and turning off
bits sequentially until all decisions have been made.
SIGN BIT
m-mSICHORO
I rl=
BITS
I
STEP
BASIC DECODE OPERATION
(EXPANDING DJ A CONVERSION)
BITS
V REF
1 2 3 4 5 6 7 8
9
+10V
0/ A conversion with the DAC-88 is implemented by using an
operational amplifier connected to the decode outputs. The
decode mode of operation is selected by applying a logic "0"
to the Encode/Decode input. This mode enables the 100(+)
or 100(-) to be selected by the sign-bit input. When the signbit input is high, a logic "1", all of the output currentflows into
Rll
v R'
OAe-S8
11+-
l~:~r
12 'REF
V R-
R12
20kn
-15V
+15V
DECODE TRANSFER CHARACTERISTIC
(O/A CONVERSION)
ENCODE TRANSFER CHARACTERISTICS
(AID CONVERSION)
ANALOG
OUTPUT 1+)
ANALOG
INPUT (-)
ANALOG
INPUT (+)
ANALOG
OUTPUT I-J
11·63
1/86, Rev. A
------------l1fHD
DAC-88 COMDAC@COMPANDINGD/ACONVERTER
I OO( +) forcing a positive voltage at the operational amplifier's
output. When the sign-bit input is low, logic "0", all of the
output current flows into 100H through R2 forcing a negative
voltage output. The sign-bit steers current into 100(+) or
100H, the output will therefore always be symmetrical,
limited only by the matching of Rl and R2.
NORMALIZED TABLES
The encode and decode tables are used to calculate ideal
output current at any pOint. For example, in decode mode at
13 ,7 (011 0111) find 343. 343/8031 x IFs = 85.75,..A (lFS =
2007.75,..A). Alternatively, use the condensed current tables
and add up the number of steps.
C = chord no. (0 through 7)
8 = step no. (0 through 15)
NORMALIZED ENCODE LEVEL (SIGN BIT EXCLUDED) (Ic,s = 2[2 c (8 + 17) -16.5J
CHORO
o
2
o
4
5
001
010
011
100
101
110
111
0000
35
103
239
511
1055
2143
4319
0001
39
111
255
543
1119
2271
4575
0010
43
119
271
575
1183
2399
4831
0011
47
127
287
607
1247
2527
5087
STEP
000
0100
9
51
135
303
639
1311
2655
5343
0101
11
55
143
319
671
1375
2783
5599
0110
13
59
151
335
703
1439
2911
5855
0111
15
63
159
351
735
1503
3039
6111
1000
17
67
167
367
767
1567
3167
6367
9
1001
19
71
175
383
799
1631
3295
6623
10
1010
21
75
183
399
831
1695
3423
6879
11
1011
23
79
191
415
863
1759
3551
7135
12
1100
25
83
199
431
895
1823
3679
7391
13
1101
27
87
207
447
927
1887
3807
7647
4
6
14
1110
29
91
215
463
959
1951
3935
7903
15
1111
31
95
223
479
991
2015
4063
8159
16
32
64
128
256
STEP SIZE
4
NORMALIZED DECODE OUTPUT(SIGN BIT EXCLUDED) (lc,s=2[2 c (8+ 16.5)-16.5J
o
C = chord no. (0 through 7)
8 = step no. (0 through 15)
4
5
6
000
001
010
011
100
101
110
111
o
33
99
231
495
1023
2079
4291
37
107
247
527
1087
2207
4447
41
115
263
559
1151
2335
4703
45
123
279
591
1215
2463
4959
131
295
623
1279
2591
5215
o
0000
2
0010
3
0011
4
0100
8
49
5
0101
10
53
139
311
655
1343
2719
5471
6
0110
12
57
147
327
687
1407
2847
5727
0001
4
0111
14
61
155
343
719
1471
2975
5983
8
1000
16
65
163
359
751
1535
3103
6239
9
1001
18
69
171
375
783
1599
3231
6495
10
1010
20
73
179
391
815
1663
3359
6751
11
1011
22
77
187
407
847
1727
3487
7007
12
1100
24
81
195
423
879
1791
3615
7263
13
1101
26
85
203
439
911
1855
3743
7519
14
1110
28
89
212
455
943
1919
3871
7775
1111
30
93
219
471
975
1983
3999
8031
4
8
16
32
64
128
256
15
STEP SIZE
11-64
1/86, Rev_ A
-------------t~ DAC-88 COMDACI!J COMPANDING D/A CONVERTER
SYSTEM TEST CIRCUIT
MULTIPLEXER
MULTIPLEXER
DIA
AID
DAC·
••
SAMPLE/HOLD
ANALOG
CHANNELS
CMp·01
1-_ _-''- r-:=::-I~--~
DAC·
••
IN
ANALOG
CHANNELS
OUT
REF·
01/02
SAR
CROSSTALK
~ 75dB
IDLE CHANNEL NOISE
21dBnc
(AVERAGE CHANNEL VALUE)
NOTES
118kHz SAMPLING CONDITIONS AJD CONVERSION TIME
1554jJs
2 AUDIO TEST ANALYZER CONTAINS AC MESSAGE FILTER
AND 3kHz FLAT FILTER
BASIC REFERENCE CONSIDERATIONS
Full-scale output current is ideally 2007 .75/JA when the reference current is 528/JA in the decode mode. In the encode
mode IFS= 2039.75/JA due to the additional 1/2 step (32/JA). A
percentage change in I REF will produce the same percentage
change in output current.
The large step size at full-scale allows the use of inexpensive
references in many applications. In some applications VREF
may even be the positive power supply. Forexample, with V+
= 15V, RREF = 15v/528/JA or 28.4kO. When using a power
supply as a reference, R11 becomes two resistors, R11 A and
R11B, and the junction bypassed to ground with a 0.1/Jf
monolithic capacitor.
REFERENCE AMPLIFIER OPERATION
DECODE OUTPUT VOLTAGE
E/D 58 81 82 83 84 85 86 87
POS FULL-SCALE
(+1 ZERO-SCALE +1 STEP
(+1 ZERO-SCALE
(-I ZERO-SCALE
(-I ZERO-SCALE +1 STEP
NEG FULL-SCALE
The DAC-88 is a multiplying D/A converter. The output current is the product of the normalized digital input and the
input reference current. The reference current may be fixed
or may vary from nearly zero to + 1.0mA. The full-scale output
current is a linear function of the reference current and is
given for all four outputs in the figures above.
Eo
5.019V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
o 0012V
o
o
OV
OV
-o.0012V
REFERENCE RECOMMENDATIONS
1 -5.019V
For most applications a + 10.0V reference, such as the PMI
REF-01, is recommended for optimum full-scale temperature
performance.
BASIC DECODE CONNECTIONS
POWER SUPPLIES
DIGITAL INPUTS
Power supply current drain is relatively independent of voltage and temperature and completely independent of the
logic input states.
R11
18.94
00
(RREFI
ANALOG
OUTPUT
±5V
IDEAL VALUES
-12V
+12V
>5V
NOTE:
THIS CONFIGURATION WILL DECODE 24-CHANNELS
IREF '" 528jJA
IFS'" 2007.7SjJA
When operating with V- between -15V and -11V, output
negative voltage compliance, VOC(-) , reference input amplifier common-mode voltage range, and logic input negative
voltage range are reduced by an amount equivalent to the
difference between -15V and the V- supply. Operation with
V+ between +5V and +15V affects VLC and the reference
amplifier common-mode positive voltage range in the same
manner.
11-65
1/86, Rev. A
II
_ _ _ _ _ _ _ _ _ _-I~DAC.88 COMDAC. COMPANDING D/A CONVERTER
capability. Positive voltage compliance is + 18V and negative
voltage compliance is -5.0V with IREF= 528"A and V =-15V.
Negative voltage compliance Voc(-) for other values of IREF
and V- may be obtained from the table. or calculated as
follows:
STANDARD DUTPUT CONNECTIONS
Voc(-) min = (V-)
""
'894
kn
+ (2 IREF X 1.6kO) + 8.4V
Output voltage compliance can be extended in both encode
and decode modes using the connections shown in the
compliance extension diagram.
RREf
",.
ZOkn
NEGATIVE OUTPUT VOLTAGE COMPLIANCE VOC(-)
STANDARD ENCODE/DECODE
CONNECTIONS REQUIRE
IVOC!_II':; IVAmllxl
COMPLIANCE EXTENSION CONNECTIONS
IFS
V-
1.0mA
2.0mA
-12V
-2.SV
-2.DV
-D.4V
-lSV
-S.SV
-S.DV
-3.4V
-lSV
-S.SV
-S.DV
-S.4V
4.0mA
MINIMUM NEGATIVE COMPLIANCE
Rl
VocH MIN = (V-)
COMPARATOR
""
+ (2 IREF 1.SkO) + S.4V
SIGNAL TO QUANTIZING DISTORTION vs INPUT LEVEL
1894
kn
RREF
jJLAW - - - C MSG WTG
_ _ _ _ 3kHz FLAT
"12
20kU
VAm8X ~ Vael-I/n
WHERE n '" R2/R, + R2
VA MUST DRIVE Rl + R2
zo
OUTPUT VOLTAGE COMPLIANCE
-so
INPUT LEVEL (dBmO)
The DAC-88 has true cu rrent outputs with wide voltage compliance that enables single ended and balanced load driving
APPLICATIONS
PHOTODIODE LINEARIZING CIRCUIT
ce
elK
SAR
0
ee
DATA
OUT
elK
IOE_
CMP+
DAC-88
CMP-
SIB
11·66
1/86, Rev. A
DAC-89
COMDAC® COMPANDING
D/A CONVERTER ("1\' LAWI
Precision Monolithics Inc.
+v FS -
FEATURES
•
•
•
•
•
•
•
•
•
11-Blt Accuracy and Resolution Around Zero
Sign Plus 66dB Dynamic Range
True Current Outputs: -5V to +18V Compliance
Tight Full-Scale Tolerance Eliminates Calibration
Low Full-Scale Drift Over Temperature
Low Power Consumption and Low Cost
Ideal for PCM and 8-Blt ",p Applications
Outputs Multiplexed for Time Shared Applications
Fully Specified Dice Available
. . . . . . . ..
ANALOG
OUTPUT
0-
COMOAC®
TRANSFER
CHARACTERISTIC
GENERAL DESCRIPTION
The DAC-89 monolithic COMDAC® converter provides the
complete decode function for "A" Law PCM CODECs. The
DAC-89 may be configured in an encoder, decoder, or timeshared between encoding and decoding.
AX
Y = 1 + In A
A= 87.6
The DAC-89 implements this law with an eight chord (or
segment) piecewise linear approximation for each polarity
with sixteen linear steps in each chord. The first two chords
are co-linear and of equal step size, and may be considered
as one chord of 32 steps. Step sizes of the remaining six
chords are binarily related to the first chord.
y= 1+lnAX 1/A~X~1
1 + In A
PIN CONNECTIONS & ORDERING INFORMATION
CHORD BIT INPUT
EQUIVALENT CIRCUIT
POSITIVE POWER SUPPLY
DECODE OUT E/D S8 = 00
4
5
CHORD
INPUTS
6382 61
S6
E/D
ENCODE OUT EJO S8 = 10
14
ENCODE OUT E/O S8 = 11
13
NEGATIVE POWER SUPPLY
NEGATIVE REFERENCE
INPUT
POSITIVE REFERENCE
INPUT
LOGIC THRESHOLD
CONTROL
7
THIRD STEP BIT INPUT
8
11
LEAST SIGNIFICANT STEP
BIT INPUT
9
10
TOP VIEW
18-PIN HERMETIC DUAL-IN-LINE
(X-Suffix)
GRADE
DAC-89EX
STEP
INPUTS
87 86 8584
DECODE OUT E/D S8 = 01
MOST SIGNIFICANT STEP
BIT INPUT
SECONe STEP BIT INPUT
0 ~ X ~ 1/A where:
Y = Output signal level of the compressor (encoder).
The DAC-89 output is an approximation to the CCITT "A"
law which can be expressed as:
2
, ", ""
X = Normalized input signal level of the compressor
(encoder), V1NNFS.
CCITT "A" LAW CHARACTERISTIC
1
0000
DIGITAL INPUT
Specifying chord end-pOint values assures accuracy chord
nonlinearity, and monotonicity over the full operating
temperature range. For companding D/A converters with
Bell ,.,.255 law conformance, refer to the DAC-88 data sheet.
For industrial, process control, and audio applications, see
the DAC-86 data sheet.
ENCODE/DECODE SELECT
1"" ENCODE
SIGN BIT INPUT
1 '" POSITIVE
MOST SIGNIFICANT CHORD
BIT INPUT
SECOND CHORD BIT INPUT
LEAST SIGNIFICANT
x 000
o ", ""
TEMP RANGE
-25°C/+85°C
REFERENCE
AMPLIFIER
13
ACCURACY
±1/4 step
v-
11-67
VLe
1/86, Rev. A
_ _ _ _ _ _ _ _ _ _--1~DAC-88 COMDAC- COMPANDING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
V+ Supply to V- Supply. . . . . . .. . . . . .. .. .. .. . . . . .... 36V
VLC Swing. . • . . . . • • • • . • • . • • • . • • • . • • • . •• V- plus 8V to V+
Analog Current Outputs ••.•••• V- plus 8V to V- plus 36V
Reference Inputs ......••••••.•••.••.•••...•••. V- to V+
Reference Input Differential Voltage .•..••.•....... ± 18V
Reference Input Current .••••.•••.•.. '••.•.•••.•. 1.25mA
Logic Inputs .................. V- plus 8V to V- plus 36V
Operating Temperature Range .•...•.... -25°C to +85°C
Storage Temperature Range. . . . . • . • . •. -65° C to + 150° C
Power Dissipation .............................. 500mW
Derate Above 100° C .......................... 10mW/o C
Lead Temperature (Soldering, 60 sec) ..••.•..••.•• 300°C
NOTE: Absolute ratings apply to both DICE and packaged perts unless
otherwise noted,
ELECTRICAL CHARACTERISTICS at Vs=± 15V, IREF= 512",A, -25° C:5 TA:5+85°C, all 4 outputs, unless otherwise noted.
In a companding DAC the term LSB is not used because the step size within each chord is different. For example, in the first
chord around zero (Co) step size is 1.0",A, while in the last chord near full-scale (C7) step size is 64",A.
DAC-89E
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±128
±128
±128
Steps
Resolution
8 chords with 16 steps each
Dynamic Range
20 log (1 7, ,sllo,o)
Monotonicity
Sign Bit + or-
Chord End-Point Accuracy
Chord Zero
Error relative to Ideal values
at I FS = 20161'A
±1/4
Step
Chord End-Point Accuracy
All Chords Other Than Zero
Error relative to ideal values
atlFS = 20161'A
±1/2
Step
Step Accuracy
Chord Zero
at 'FS = 20161'A
±1/4
Step
Step Accuracy
All Chords Other Than Zero
Error relative to ideal values
at IFS = 20161'A
±1/2
Step
Encode Decision Level Current
Additional output
Encode/Decode = 1
3/4
Step
Settling Time (Note 1)
ts
To within ± 1/2 step
Full-Scale Drift (Note 3)
AI FS
Full temperature range
±1/4
Step
Output Voltage Compliance
VOC
Full-scale current change
S 1/2 step
+18
Volts
Full-SCale Current Deviation
from Ideal (See Tables) (Note 2)
'FS(D)
IF.(E)
VREF 10.oo0V TA = 2SoC
Rll = 19.53kO, R12 = 20kO
±1/2
±1/2
Step
Step
Full-Scale Symmetry Error
(Note 2)
' 0 (+) -10(-)
Decode or Encode pal r
±1/8
Step
Zero-Scale Current
(Note 2)
Izs
Measured at selected output
with 000 0000 Input
1/2
3/4
Step
Dlseble Current (Note 2)
lOIS
Disabled by EtD and SB
S.O
100
Idle Current (Note 2)
I,
as
66
128
Error relative to ideal values
1/4
Output Current Range
I FSR
VREF= 2S,oooV TA = 2SoC
V,L
VLC=OV
Logic Input Levels, Logic "1"
V,H
VLC=OV
Logic Input Current
'iN
V,N =-SVto+18V
Logic Input SWing
V's
V-=-lSV
"2
Reference Input Slew Rate
dlldt
Power Supply Sensitivity Over
Supply Range (Refer to
Characteristic Curves)
PSSI FS+
PSSI F5-
±1/20
-S
±1/40
ns
10
Logic Input Levels, Logic ''0''
Reference Bias Current
112
SOO
1/4
4,2
2.0
0
mA
0.8
Volts
Volts
-5
-3
120
I'A
+18
Volts
-12
0.25
NOTES:
1. Settling time varies for each of the chord bits and step bits and a maximum
specification may be misleading. In decode operation, the DAC-89 and
OP-16 combination will decode 8 channels. In the encode mode, the
DAC-89 and CMP-Dl combination will encode 8 channels. Both encode
and decode statements assume a 3,91's channel time,
nA
I'A
2,0
V+ = 4.5V to 18V. V- = -15V
V- = -10.8V to -18V, V+ = lSV
dB
Steps
±1/20
±1/10
I'A
mAIl's
±1/2
±1I2
Step
Current specifications relate to differential currents between (+) and (-)
output leads. At the selected outputs, equal idle currents are present
simultaneously on both current output leads,
3. Guaranteed by design.
2
11·68
1/86, Rev. A
-----------l1fMD DAC-89 COMDACII COMPANDING D/A CONVERTER
ELECTRICAL CHARACTERISTICS at VS= ±15V, IREF= 512j.1A, -25° CS TAS +85° C, all 4 outputs, unless otherwise noted.
In a companding DAC the term LSB is not used because the step size within each chord is different. For example, In the first
chord around zero (Co) step size is 1.0j.lA, while in the last chord near full-scale (C7) step size Is 64j.1A. (Continued)
DAC-89E
PARAMETER
SYMBOL
CONDITIONS
TVP
MAX
UNITS
1+
Vs = +5V. -15V. I FS = 2 OmA
Vs =+5V,-15V,I Fs=2.0mA
Vs = ±15V, IFS = 2.0mA
Vs = ±15V, I FS = 2.0mA
2.7
-6.7
2.7
-6.7
5.5
-12
5.5
-12
mA
Vs = +5V, -15V. I FS = 2.0mA
Vs =±15V,I FS =2.0mA
114
141
207
262
mW
1-
Power Supply Current
1+
1-
Power Dlssipatton
MIN
"->
r:(
~
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
8.
7.
8.
9.
ElD
SIGN-BIT
BIT 1 (MSB)
BIT2
BIT3
BIT4
BIT5
BIT8
BIT 7 (LSB)
10.
11.
12.
13.
14.
15.
18.
17.
18.
~
0
VLC
VR (+)
U
VR (-)
C)
V-
0
10E (+)
10E (-)
100(+)
100(-)
~
V+
0
~
~
For additional DICE Information refer to
1988 Data Book, Section 2.
C)
DIE SIZE 0.123 X 0.085 Inch, 10.455 sq. mils
(3.124 X 2.159 mm, 8.745 sq. mm)
6
II
WAFER TEST LIMITS at Vs= ±15V, IREF= 528"A, TA=25°C, all 4 outputs, unless otherwise noted.
DAC-89N
(NOTE3)
PARAMETER
SYMBOL
Resolution
CONDITIONS
8 chords with 16 steps each
Dynamic Range
LIMIT
UNITS
±128
Steps MIN
66
dBMIN
128
Steps MIN
Error relative to ideal values
at IFS = 2007.75I'A
±1/4
Step MAX
Chord End-point Accuracy
All Chords Other Than Zero
Error relative to ideal values
at IFS= 2007.751'A
±1I2
Step MAX
Encode Decision Level
Current
Additional output
encode/decode = 1
114
3/4
Step MIN
Step MAX
-5
+18
Volts MIN
Volts MAX
±1/8
Step MAX
Monotonlcity
Sign-Bit + or-
Chord End-point Accuracy
Chord Zero
Output Voltage Compliance
Voe
Full-Scale Symmetry Error
(Note 2)
Zero-Scale Current (Note 2)
Disable Current (All bits high)
(Note 2)
Full-scale currenl change
S 1/2 step
Decode or encode pal r
Input Code 1111111
Izs
Measured at selected output
0000000 input
1/4
Step Max
lOIS
Leakage 01 output disabled
by ElDand 58
100
nAMAX
11-89
1/86, Rev. A
_ _ _ _ _ _ _ _ _ _-l~DAC-88 COMDAce COMPANDING D/A CONVERTER
WAFER TEST LIMITS at VS= ±15V. IREF= 5~1I~A. TA= 25°C. all 4 outputs. unless otherwise noted. (Continued)
DAC-89N
(NOTE 3)
PARAMETER
SYMBOL
LIMIT
CONDITIONS
UNITS
Step Accuracy
Chord Zero
Error relat,ve to ,deal values
at I FS = 2007.7Sp.A
±1I4
Step MAX
Step Accuracy
All Chords Other Than Zero
Error relative to ,deal values
at I FS = 2016p.A
±1/2
Step MAX
Output Current Range
Logic Input Levals, Logic "0"
Logic Input Levels, Logic "I"
VLe=OV
Logic Input Current
V'N=-SVtO+18V
VREF= 2S.000V, TA = 2SoC
4.2
mAMIN
VLe = OV
0.8
Volts MAX
2
Volts MIN
V-=-ISV
Logic Input Swing
p.AMAX
-S
+18
Volts MIN
Volts MAX
-12
p.AMAX
V+ = 4 SV to 18V
V- = 10 8V to -18V
±1I2
±1I2
Step MAX
Step MAX
1+
1-
Vs = ± ISV, I FS = 2.0mA
S.S
-12.0
mAMAX
1+
1-
Vs=±ISV,I FS =2.0mA
S.7S
-12.0
mAMAX
VAEF 10.000V. TA = 2SoC
±1I2
Step MAX
Rll = 19.53kO
R12=20kO
±1/2
Step MAX
Reference Bias Current
Power Supply Sensitivity Over
Supply Range (Refer to
Characteristic Curvas)
Power Supply Current
120
Full-Scale Current Deviation
From Ideal Deviation
(See Tables) (Note 2)
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations In assembly methods and normal yield loss, yield after packaging Is not
guarenteed for standard product dice. Consult factory to negotiate spaciflcations based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ± 15V. and TA = 25° C. unless otherwise noted.
DAC-89N
PARAMETER
SYMBOL
CONDITIONS
TYPICAL
UNITS
Settling Time (Note 1)
ts
To within ± 1/2 step
SOO
ns
Settling Time In Chord Zero
Tseo
To within ±1/2 step
SOO
ns
Full-Scale Drift (C7)
~IFS
Full temperature range
±1/2O
Step
Reference Input Slew Rate
dl/dt
Power Dissipation
Idle Current (Note 2)
02S
mNp.s
Po
Vs +SV,-ISV
114
mW
Po
Vs =±ISV
141
mW
10
p.A
I,
NOTES:
1. In a companding DAC the term LSB Is not used because the step s,ze
within each chord is different. Forexample, in the first chord around zero
(Co) step size is O.Sp.A. While in the last chord near full-scale (C 7) step size
is 64p.A. Settling time varies for each of the chord bits and step bits and a
maximum speCification is misleading
2. Current specifications relate to differential currents between (+) and (-)
output leads. At the selected outputs, equal Idle currents are present
simultaneously on both current output leads
3. See DAC-89E for typical values.
11-70
1/86, Rev_ A
------------l~ DAC-89 COMDAC® COMPANDING D/A CONVERTER
OUTPUT CURRENT DC TEST CIRCUIT
R1
LINE SELECTION TABLE
DIGITAL INPUTS
+VREF
TEST
GROUP
ENCODE/
DECODE
SIGN
BIT
OUTPUT
MEASUREMENT
R11
1953kn
(RREF)
10E(+)
11
2
12
R12
>OkG
0
3
0
4
0
0
(E01/R1 )
10E(-)
(E01/R2 )
100(+)
(E02/R3)
100(-)
(E02/R4)
NOTE: Accuracy is specified in the test circuit using the tables below to be
Al '" R2 = R3 = R4 = 2 Skll
·VAEF IS ADJUSTED BEFORE TESTING EACH DeVICE
TO PROVIDE IDEAL FULL-SCALE OUTPUT CURRENT
within the specified proportion of a step at the maximum value in each chord.
Monotonlcity is guaranteed for all Input codes.
-:"
CONDENSED CURRENT OUTPUT TABLES
IDEAL DECODE OUTPUT CURRENT IN MICROAMPS AT CHORD ENDPOINTS
4
CHORO
o
000
001
010
011
100
101
110
111
0000
0.5
165
33
66
132
264
528
1056
1111
15.5
31.5
63
126
252
504
1008
2016
8
16
32
64
STEP
o
15
STEP SIZE
IDEAL ENCODE OUTPUT CURRENT IN MICROAMPS AT CHORD ENDPOINTS
4
CHORO
o
2
STEP
000
0000
15
1111
16
001
010
011
100
101
110
111
17
34
68
136
272
544
1088
32
64
128
256
512
1024
2048
16
32
64
STEP SIZE
4
NOTE:
These tables may be extended to include aU of the encode/decode currents
(ideal with IREF= 512"A) by multiplying any of the numbers in the normalized
tables by 0.5"A.
IDEAL OUTPUT CURRENT
The difference between the (+) and (-) currents (encode or
decode) at any code.
PARAMETER DEFINITIONS
STEP NONLINEARITY
Step size deviation from ideal within a chord.
OUTPUT VOLTAGE COMPLIANCE
ENCODE CURRENT
The maximum output voltage swing at any current level
which causes <1/2 step change in output current.
The difference between 10E(+) and 100(+) or the difference
between 10E(-) and 100(-) at any code.
CHORDS
FULL-SCALE DRIFT
Groups of linearly-related steps in the transfer function. Also
known as segments.
The change in output current over the full operating
temperature with VREF = 10.000V. R11 = 19.53kO. and
R12 = 20kO.
The maximum code in each chord; used to specify accuracy.
FULL-SCALE SYMMETRY ERROR
STEPS
The difference between 100(-) and 100(+) or the difference
between 10E(-) and 10E(+) at full-scale output.
Increments in each chord which divides the chord into 16
equal levels.
CHORD ENDPOINTS
11-71
1/86, Rev. A
II
_ _ _ _ _ _ _ _ _ _--I~DAC-89 COMDAC@COMPANDINGD/ACONVERTER
OUTPUT LEVEL NOTATION
Each output current level may be designated by the code Ie s
where C = chord number and S = step number. For example,
10 .0 = zero-scale current: 10 .1 = first step from zero; 10,15 =
endpoint of first chord (Co); 17.15 = full-scale current.
DYNAMIC RANGE
Ratio of full-scale current to step size in chord zero expressed
in dB.
BASIC ENCODE OPERATION
(COMPRESSING AID CONVERSION)
For positive inputs, current flows into 10E(+) through R1, and
the comparator's output is entered as the answer for each
successive decision. For negative inputs, current flows into
10E(-) through R2 developing a negative voltage which is
compared with the analog input. An EXCLUSIVE-OR gate
inverts the comparator's output during negative trials to
maintain the proper logic coding, all ones for full-scale and
all zeros for zero-scale.
The bits are converted with a successive removal technique
starting with a decision at the code 0111111 and sequentially
turning off bits until all decisions have been made.
ENCODE DECISION LEVELS
ENCODING SEQUENCE
An encoding sequence begins with the sign-bit decision.
During this time the comparator functions as a polarity detector only. The Encode/Decode (E/D) input is held at logic "0".
In this mode current flows into the decode outputs, and the
comparator is effectively disconnected from the DAC. Once
the input polarity has been determined, the ElD inputtoggles
"1" allowing current to flow into 10E(+) or 10E(-).
Compressing A/D conversion with the DAC-89 requires a
comparator, an EXCLUSIVE-OR gate, and a successive
approximation register - the usual elements in any signmagnitude AID converter. However, a compressing AID has
one significant difference. In a conventional (linear) converter, the step size is a constant percentage of full scale, but in a
compressing A/D converter, the step size increases as the
output changes from zero-scale to full-scale.
BASIC DECODE CONNECTIONS
When the DAC is used in the feedback loop of a successive
approximation analog to digital converter (ADC), the DAC
outputs are used as decision levels to determine the edges of
the quantizing bands. When the DAC is used in the decode
mode the outputs correspond to the center of the quantizing
bands. The encode mode output exceeds the decode mode
output by one-half step. See AN 39 for detailed explanation.
:t5V ANALOG INPUT
r ----
..!...
-=-
R2
2.5k
(GROUND FDA
SINGLE-ENDED
INPUTS)
SUCCESSIVE
DIGITAL
APPROXIMATION
REGISTER {SARI
ENCODE TRANSFER CHARACTERISTIC
(AID CONVERSION)
OUTPUTS
DIGITAL
SIGN
rH$a=t=~}
OUTPUT (+)
BIT
CHORD
BIT
~}STEP
BITS
1 2 3 4 5 6 7 8 9
81 83 85 B7
S8 82 84 B6
11
VREF
+10V
E/D
V R (+)
DAC-89
.......
Rll
19.53kn
(AREFJ
'REF
VAH 12
R12
2OkCOMPANDINGD/ACONVERTER
NORMALIZED ENCODE DECISION LEVELS (SIGN-BIT EXCLUDED)
NORMALIZED ENCODE DECISION
CHORO
STEP
3
4
,00
,0,
110
, ,1
68
0"
,36
272
544
,088
2176
0
000
0000
00,
0,0
34
6
000,
4
36
72
,44
288
576
,,52
2304
00,0
6
38
76
,52
304
608
,2,6
2432
00"
0,00
8
,0
40
80
,60
320
640
,280
2560
42
84
,68
336
672
,344
0,0,
,2
44
88
176
352
704
1408
2688
28,6
0,,0
,4
46
92
184
368
736
,472
2944
0",
,000
16
48
96
,92
384
768
,536
3072
,8
50
,00
200
400
800
,600
3200
9
,0
,00,
20
52
,04
4,6
832
,664
3328
,0,0
22
54
,08
208
2,6
432
864
1728
3456
"
,0"
,,00
24
56
,,2
224
448
896
,792
3584
26
58
,,6
232
464
928
,856
37,2
13
,4
,,0,
28
60
,20
240
480
960
,920
3840
",0
30
62
,24
248
496
992
,984
3968
""
32
64
,28
256
5,2
,024
2048
"4096
,6
32
64
,28
,2
,5
STEP SIZE
·Vlrtual Decision Level
BASIC DECODE OPERATION
(EXPANDING D/A CONVERSION)
NORMALIZED TABLES
The encode and decode tables are used to calculate ideal
output current at any code point. For example, in decode
mode at 13,7 (0110111) find 188. 188/4032 times IFSof 20161'A
equals 941'A.
D/ A conversion with the DAC-89 is implemented by using an
operational amplifier connected to the decode outputs. The
decode mode of operation is selected by applying a logic "0"
to the Encode/Decode input. This mode enables the 100
outputs, disables the 10Eoutputs, and allows 100(+) or 100(-)
to be selected by the sign-bit input. When the sign-bit input is
high, logic "1", the output current flows into 100(+) forcing a
positive voltage at the operational amplifier's output. When
the sign-bit input is low, logic "0", the output current flows
into 100(-) through R2 forcing a negative voltage output. The
sign-bit steers current into 100 (+) or 100H, the output will
therefore always be symmetrical, limited only by the matching of R1 and R2.
E/D SB B1 B2 B3 B4 B5 B6 B7
,,,
Eo
5.040V
POS FULL-SCALE
0
(+1 ZERO-SCALE+' STEP
0
,
0 0
0
0
0
0
1
0.OO12V
(+1 ZERO-SCALE
0
1 0
0
0
0
0
0
0
0.004V
(-I ZERO-SCALE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(-I
ZERO-SCALE +1 STEP
NEG FULL-SCALE
0
1
,
0.004V
-o.0012V
-5.040V
DECODE TRANSFER CHARACTERISTIC
(D/A CONVERSION)
BASIC DECODE CONNECTIONS
ANALOG
OUTPUT (+)
R1
2.5kn
R12
.ok"
VREF
IREF = RREF
IDEAL VALUES
'REF = 512j.1A
IFS = 2016,uA
ANALOG
OUTPUT (-)
11-73
1/86, Rev. A
I
~ DAC-89
COMDAC® COMPANDING D/A CONVERTER
NORMALIZED DECODE OUTPUT (SIGN-BIT EXCLUDED)
NORMALIZED DECODE OUTPUT
CHORD
STEP
000
0
4
6
001
010
011
100
101
110
111
0000
33
66
132
264
528
1056
2112
0001
35
70
140
280
560
1120
2240
0010
37
74
148
296
592
1184
2368
3
0011
39
78
156
312
624
1248
2496
4
0100
41
82
164
328
656
1312
2624
43
86
172
344
688
1376
2752
0101
11
0110
13
45
90
180
360
720
1440
2880
0111
15
47
94
188
376
752
1504
3008
8
1000
17
49
98
196
392
784
1568
3136
9
1001
19
51
102
204
408
816
1632
3264
10
1010
21
53
106
212
424
848
1696
3392
6
11
1011
23
55
110
220
440
880
1760
3520
12
1100
25
57
114
228
456
912
1824
3648
13
1101
27
59
118
236
472
944
1888
3776
14
1110
29
61
122
244
488
976
1952
3904
1111
31
63
126
252
504
1008
2016
4032
8
16
32
64
128
15
STEP SIZE
2
BASIC REFERENCE CONSIDERATIONS
Full-scale output current is ideally 20l61'A when the reference
current is 5121'A in the decode mode. In the encode mode I FS
= 20481'A due to the additional one-half step (32I'A). A percentage change in IREF caused by changes in VREF or RREF
will produce the same percentage change in output current.
Output voltage compliance can be extended in both encode
and decode modes using the output compliance extension
connections. (Figures 1 and 2).
NEGATIVE OUTPUT VOLTAGE COMPLIANCE VoC<-)
The large step size at full scale allows the use of inexpensive
references in many applications. In some applications VREFmay
even be the positive power supply. For example, with V+ =
l5V, RREF= l5V/5l21'A or 29.3kD. When using a powersupply
as a reference, Rll should be two resistors, RllA and RllB,
and the junction bypassed to ground to provide decoupling.
OUTPUT VOLTAGE COMPLIANCE
V-
1.0mA
IFS
2.0mA
4.0mA
-12V
-2.BV
-2.DV
-DAV
-lSV
-S.BV
-S.DV
-3.4V
-lBV
-B.BV
-B.DV
-S.4V
MINIMUM NEGATIVE COMPLIANCE
VocH MIN = (V-) + (2 IREF 1.6k!l) + BAV
The DAC-89 has true current outputs with wide voltage compliance that enables single ended and balanced load driving
capability. Positive voltage compliance is + l8V and negative
voltage compliance is-5.0V with IREF= 5l21'A and V= -15V.
Negative voltage compliance Voc(-) for other values of IREF
and V- may be obtained from the table, or calculated as
follows:
IDLE OUTPUT CURRENT
In the selected output state (encode or decode), equivalent
idle currents are present on the (+) and H output leads. The
output will be symmetrical with the external resistor matching
determining the overall system accuracy.
VocH min = (V-) + (2 IREF X 1.6kD) + 8.4V
11-74
1/86, Rev. A
_ _ _ _ _ _ _ _ _ _---l~DAC-89 COMDAC® COMPANDING D/A CONVERTER
OUTPUT COMPLIANCE EXTENSION CONNECTIONS
STANDARD ENCODE/DECODE CONNECTIONS
VREF
+10V
DIGITAL INPUTS
R12
20kn
STANDARD ENCODE/DECODE
CONNECTIONS ReQUIRE
IVOC{-)I';;; IVAmaxl
Figure 1
EXTENDED RANGE CONNECTIONS
R1
COMPARATOR
VREF
+10V
R11
1953kn
(RREF)
R12
20kn
EXTENDED RANGE CONNECTION ALLOWS
II
eo A2/R, + R2
VA MUST DRIVE Al + R2
WHERE n
Figure 2
IDEAL DECODE OUTPUT CURRENT IN MICROAMPS (SIGN-BIT EXCLUDED)
IDEAL DECODE OUTPUT
CHORD
0
001
010
011
100
101
110
111
05
165
33
66
132
264
528
1056
0001
1.5
175
35
70
140
280
560
1120
0010
2.5
18.5
37
74
148
286
592
1184
0000
5
3
000
STEP
0011
3.5
19.5
39
78
156
312
624
1248
0100
45
205
41
82
164
328
656
1312
0101
5.5
215
43
86
172
344
688
1376
0110
65
22.5
45
90
180
360
720
1440
0111
7.5
23.5
47
94
188
376
752
1504
1000
8.5
245
49
98
196
392
784
1568
1001
9.5
25.5
51
102
204
408
816
1632
10
1010
10.5
265
53
106
212
424
848
1696
11
1011
11.5
275
55
100
220
440
880
1780
12
1100
12.5
28.5
57
114
228
456
912
1824
13
1101
13.5
29.5
59
118
236
472
944
1888
14
1110
14.5
305
61
122
244
488
976
1952
15
1111
155
31.5
63
126
252
504
1008
2016
4
8
16
32
STEP SIZE
2
----
----------
-----~---------
64
1/86, Rev. A
11-75
---
-----
-~,--
DAC-IOO
IO-BIT CURRENT-OUTPtn:
D/A CONVERTER
l'"n:CISIOII
MOlloltthlt.:s IIIC
FEATURES
•
•
•
•
•
Faat Settling ...•.•.• 225naec (8 Blta), 375naec (10 Blta)
Stable ....••...•....•... Tempcol to ±15ppm/oC Max
Commercial, Indultrlal and Military Modell Available
TTL Compatible Logic Inputl
Wide Supply Range ..................... ±6V to ±18V
The small size, wide operating temperature range, and high
reliability construction make the DAC-100 Ideal for aerospace
applications. Other applications include use in servopositioning systems, X-V plotters, CRT displays, programmable power supplies, analog meter movement drivers,
waveform generators and high speed analog-to-digltal
converters.
GENERAL DESCRIPTION
The DAC-100 Isa complete 10-bit resolution digital-to-analog
converter constructed on two monolithic chips in a single
16-pin DIP. Featuring excellent linearity vs. temperature
performance, the DAC-100 includes a low tempco voltage
reference, ten current source/switches and a high stability
thin-film R-2R ladder network. Maximum application flexibility is provided by the fast current output, matched bipolar
offset and feedback resistors. Resistors are included for use
with an external op amp for voltage output applications.
PIN CONNECTIONS
16-PIN HERMETIC
DUAL-IN-LiNE
PACKAGE
(Q-SuHlx)
Although all units have 10-bit resolution, a wide choice of
linearity and temperature coefficient options are provided to
allow price/performance optimization.
ORDERING INFORMATIONt
N.L.·
%FS
MAX
TEMPCO·
ppm/oC
MAX
INDUSTRIAL TEMPERATURE
Vo = ±2.5V15V
Vo = ±5V110V
MILITARY TEMPERATURE
Vo = ±2.5V15V
Vo=±5V110V
±O.OS
±1S
DAC100AAC7
±O.OS
±30
DAC100ABC7
DAC100ABC8
±O.OS
±60
DAC100ACCS/883
DAC100ACC6/883
DAC100ACC7
DAC100ACC8
±O.10
±30
DAC100BBCS/883
DAC100BBC6/883
DAC100BBC7
DAC100BBC8
DAC100BCCS/883
DAC100BCC6/883
DAC100BCC7
DAC100CCCS/883
DAC100CCC6/883
±O.10
±60
±O.10
±120
±O.20
±60
±O.20
±120
±O.30
±120
t All
commercial and industrial temperature range parts are available with
burn-In For ordering Information see 1986 Data Book, Section 2.
• Part number construction: The 1st letter following DAC-l00 (A-D) refers to
COMMERCIAL TEMPERATURE
Vo=±5V110V
Vo = ±2.5V15V
DAC100AAC8
DAC100ACC3
DAC100ACC4
DAC100BCC8
DAC100BCC3
DAC100BCC4
DAC100CCC7
DAC100CCC8
DAC100CCC3
DAC100CCC4
DAC100DDC7
DAC100DDC8
DAC100DDC3
DAC100DDC4
the nonlinearity specification; the 2nd letter (A-D) refers to the full-scale
tampeo; the letter Q refers to the package, and the end numeral indicates the
output voltage and temperature.
SIMPLIFIED SCHEMATIC
I
v+~~~~~tt:it~:1-c
3
AS
612kH
I.
RS
BIPOLAR REF
11-76
As
ANALOG
OUTPUT
-FOR 10V OR t6V OPERATION,
RS .. 4.BBkfl (PACKAGE 03,
06, Q71
FOR 6V OR t26V OPERATION,
RS = 2.44k0 (PACKAGE 04,
as,
OS)
1/86, Rev. A
------------1\fMD DAC·100 10·BIT CURRENT·OUTPUT D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
(Note 2)
DICE Junction Temperature. •• • • • • • • •• -2S· C to + 1S0· C
Storage Temperature Range ••••••••••• -6S·C to +1S0·C
L.ead Temperature (Soldering, 60 sec) ••••••••••• +300·C
V + Supply to V- Supply .................... 0 to +36V
V+ Supply to Output ••••••••••••••••••••••• 0 to + 1SV
V- Supply to Output ••••••••••••••••••••••• 0 to -1SV
L.oglc Inputs to Output ................... -1V to +6V
Power Dissipation (Note 1) .................... SOOmW
Operating Temperature Range 03, 04 •••• O· C to + 70· C
OS, 06, 07, OS ..................... -SS·Cto+12S·C
NOTES:
1. Rating applies to ambient temperature of 100' C. Above 100' C. derate at
10mW/'C.
2. Ratings apply to DICE and packaged parts. unless otherwise noted.
ELECTRICAL CHARACTERISTICS at Vs = ± 1SV, -25· C S TAS + SS· C for 07 and OS devices; O· C S TAS +70· C for 03 and
04; -SS· C S TA S + 12S· C for OS and 06 devices, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
DAC·100
NL
(±1/2LSB -10 bits)
(±1/2LSB - 9 bits)
(±1/2LSB - 8 bits)
(±3/4LSB - 8 bits)
Resolution
Nonlinearity
(For nonllnearlty/tempco
combinations, see Ordering
Information)
Full·Scale Tempco
(See Full'Scale Test Circuit)
Settling Time TA = 25'C
Full·Range Output VOltage
(Limits guarantee adjustabillty
to exact 10.0 (5.0)V with a
2000 Trimpot. between
Adjust and V-I
MIN
TVP
MAX
10
Tc
ts
V. R
to ±0.05% FS
to±O.l%FS
to ±0.2% FS
to ±0.4% FS
to ±0.8% FS
UNITS
Bits
ABCD-
±0.05
±0.1
±0.2
±0.3
-A
-B
-C
-D
±15
±30
±60
±120
ppm/'C
ALL
ALL
ALL
ALL
ALL
375
300
225
150
100
ns
Connect FS Adjust to V10V Models (03. 05, 07)
(See Full·Scale Test Circuit)
5V Models (04, 06, 08)
V,N =0.7V
10
%FS
Vzs
U
Measured with respect to
ALL
Logic Inputs: High
V,NH
Logic Inpuls: Low
V,NL
Measured with respect to
output pin
ALL
Logic Input Current, Each Input
liN
V,N =Oto+6V
ALL
Logic Input Resistance
R'N
V,N = Oto +6V
ALL
Logic Input Capacitance
output pin
C 'N
ALL
Output Resistance
Ro
ALL
Output Capacitance
Co
ALL
2.1
%FS
V
0.7
5
V
/loA
3
mO
500
kO
pF
13
pF
Applied Power Supplies: V+
ALL
+6
+18
Applied Power Supplies: V-
ALL
-6
-18
V
±0.10
% per Volt
Power Supply Sensitivity
Pss
Vs= ±6V to ±18V
Power Consumption
Po
Vs= ±15V
Vs= ±6V
Vs= ±15V
03,04
03,04
05.06, 07. 08
ALL
200
80
200
V
300
mW
250
Positive Supply Current
1+
Vs =+15V
Vs= +15V
03,04
05.06,07,08
10
8.33
mA
Negative Supply Current
1-
Vs = -15V
Vs =-15V
03,04
05,06,07,08
-10
-8.33
mA
11·n
~
~
~
5.55
0.013
0
I
V
ALL
V,N = 2.1V
~
C)
(See Basic Unipolar Voltage Output Circuit)
Zero·Scale Output Voltage
~
0
11.1
5
~
1/86, Rev. A
C)
.....
0
I
_ _ _ _ _ _ _ _ _ _--IIfMDDAC-100 10-BIT CURRENT-OUTPUT D/A CONVERTER
DICE CHARACTERISTICS
DAR-01
DAI-G1
DIE SIZE 0.089 X 0.063 Inch, 5607 sq. mils
(2.26 x 1.6 mm, 3.616 sq. mm)
DIE SIZE 0.060 x 0.067 Inch, 5360 sq. mils
(2.032 x 1.70 mm, 3.45 sq. mm)
1. Ra
2.
3.
15.
16.
2.
3.
4.
5.
6.
7.
8.
9.
VOUTPUT
FULL-SCALE ADJ
RS
R - Pads are connected to similarly
marked pads on DAI-01
VOUTPUT
BIT 10 (LSB)
BIT9
BIT8
BIT7
BIT6
BIT5
10.
11.
12.
13.
14.
BIT4
BIT 3
BIT2
BIT 1 (MSB)
V+
R - Pads are connected to similarly
marked pads on DAR-01
Note: Pads 4 - 14, See DAI-G1
Note: Pads 1, 2, 15, 16, See DAR-01
These die versions are available on special order; contact your PMI sales office.
WAFER TEST LIMITS at TA = 25°C for the R-2R Ladder Network comprised of R1-R8, R12, R23, R34, R45 and R56 when
connected to an ideal DAI-01, unless otherwise noted.
DAR-01-N
PARAMETER
CONDITIONS
Nonlinearity
VRI =3.2V
TYP
MIN
-
DAR-01-G
MAX
MIN
±0035
TYP
MAX
UNITS
±0.05
%
WAFER TEST LIMITS at TA = 25°C, VR1 = 3.2V, unless otherwise noted.
DAR-01
PARAMETER
CONDITIONS
Resistance Rl
Absolule Measurement
Ratio RCI to Rl
,
MIN
TYP
MAX
UNITS
2.56
3.84
kO
Ideal = 1.00503 to 1
-1
+1
%
Ratio Rl to RSI
Ideal = 1.29959 to 1
-1
+1
%
Ratio Rl to RS2
Ideal = 1.29959 to 1
-1
+1
%
Ratio RB to Rl
Ideal = 192211 to 1
-1
+1
%
.
\
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations In assembly methods and normal Yield loss. yield after packaging IS not
guaranteed for standard product dice. Consult factory to negotiate speCifications based on dice lot qualification through sample lot assembly and testing.
11-78
1/86, Rev. A
------------I1rHD
DAC-100 10-BIT CURRENT-OUTPUT D/A CONVERTER
TYPICAL ELECTRICAL CHARACTERISTICS in common to all grades.
DAR-01
PARAMETER
CONDITIONS
Absolute Temperature CoeffiCient
All Resistors
Tracking Temperature CoeffiCient
All Resistors with Respect to Rl
TYP
MIN
MAX
UNITS
±180
ppm/'C
3
ppm/'C
WAFER TEST LIMITS at TA = 25° C when connected to an ideal DAR-01, unless otherwise noted.
DAI-01-N
PARAMETER
SYMBOL
CONDITIONS
Nonllneanty
NL
Vs =±15V
VMCR
Vs =±15V
Internal Reference
Voltage
MIN
DAI-01-G
TYP
MAX
MIN
TYP
±0.05
6900
66
6.6
MAX
UNITS
±0.1
%
6.900
V
WAFER TEST LIMITS at Vs = ± 15V, TA = 25° C when connected to an ideal DAR-01, unless otherwise noted.
DAI-01
PARAMETER
MIN
CONDITIONS
Resolullon
Analog Output Current
All Bits Low, V- Connected to FS Adjust
Zero-Scale Output Current
All Bits High, V- Connected to FS Adjust
Logic Input "0"
Measured with Respect to Output
Logic Input "I"
Measured with Respect to Output
Supply Current
All Bits High, V- Connected to FS Adjust
Power Supply Rejection
Vs = ±6V to ±18V
MAX
UNITS
10
TYP
10
Bits
1840
2274
IJ.A
±0011
%I F5
07
V
8.33
mA
0.1
%IFsfV
21
V
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to vanations In assembly methods and normal Yield loss, Yield after packaging IS not
guaranteed for standard product dice Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±15V, and when connected to an ideal DAR-01, unless otherwise
noted.
DAI-01-N
PARAMETER
MIN
CONDITIONS
Full-Scale Temperature CoeffiCient (Note)
TYP
±60
DAI-01-G
MAX
MIN
TYP
MAX
I
UNITS
±60
ppm/'C
NOTE:
Full-Scale Temperature CoeffiCient is defined as the change in output voltage
measured," the basIc unipolar voltage output test CirCUit shown on the
DAC-l00 data sheet and IS expressed In ppm between 25'C and either
temperature extreme diVided by the corresponding temperature change.
1/86, Rev. A
11-79
----
-_.-
.
__
._--
-----------I~ DAC-100 10-BIT CURRENT-OUTPUT D/A CONVERTER
BASIC CONNECTIONS
REDUCED RESOLUTION APPLICATION
BASIC UNIPOLAR VOLTAGE OUTPUT CIRCUIT
v+
TYPICAL SETTLING TIME
FOR 1/2 SCALE CHANGE
"'" 1 OIlS
lOUT
6
VOUT
LOGIC CODING - The DAC-100 uses complementary or
inverted binary logic coding, i.e., an all "zeroes" Input produces a full range output, while an all "ones" Input produces a
zero-scale output. Each lesser significant bit's weight is onehalf the previous more significant bit's value. High logic input
turns the bit "OFF," low logic Input level turns the bit "ON".
BASIC BIPOLAR VOLTAGE OUTPUT CIRCUIT
LOGIC COMPATIBILITY - The input logic levels are directly
compatible with TTL logic and may also be used with CMOS
logic powered from a single +5 volt supply.
NONLINEARITY (NL) - The maximum deviation from an
ideal straight line drawn between the end pOints, expressed
as a percent of full-scale range (FSR) or given In terms of
LSB value. The end pOints are zero-scale output to full-scale
output for unipolar operation and minus full-scale to positive
full-scale for bipolar operation.
VOUT
V+
BIPOLAR OPERATION - The DAC-100 may be converted to
bipolar operation by injecting a half-scale current into the
output; this is accomplished by connecting the internal bipolar resistor to a +6.4 volt reference. Trimming of the zero
output may be facilitated by placing a 5000 adjustable resistance in series with the +6.4 volts.
APPLICATIONS INFORMATION
FULL RANGE OUTPUT ADJUSTMENT - The output current of the DAC-100 may be reduced to produce an exact
10.000 (5.000) volt output by connecting a 2000 adjustable
resistance between the full-scale adjust pin and V-. Adjustment should be made with an input of all "zeroes."
VOLTAGE AT OUTPUT PIN - The DAC-100 is designed to
be operated with the voltage at the output pin held very close
to zero volts. Input logic threshold levels are directly affected
by output pin voltage changes; voltage swings at the output
may cause loss of linearity due to improper switching of bits.
Large voltage swings may cause permanent damage and
should be avoided. Proper operation can be obtained with
output voltages held within ±0.7 volts; a pair of back-to-back
silicon diodes tied from the output to ground is a convenient
way of clamping the output to this limit.
LOWER RESOLUTION APPLICATIONS - The DAC-100
may be used in applications requiring less than 10 bits of
resolution. All unused logic inputs must be tied to logic high
for proper operation. "Floating" logic inputs can cause
improper operation.
11-80
1/86, Rev. A
-------------l~ DAC-100 10-BIT CURRENT-OUTPUT D/A CONVERTER
TYPICAL APPLICATIONS
BINARY-COOED-DECIMAL D/A CONVERSION
'5V
EXTERNAL REFERENCE CONNECTION
+15V
+1SV
ANALOG SUM OF TWO DIGITAL NUMBERS
v*CAN BE EXPANDED TO 3 DIGITS BY ADDITION OF A THIRD OAe AND
99 TO 1 CURRENT DIVIDER
INTERFACING WITH CMOS LOGIC
The DAC-100 requires only about 1/LA of input current into
each logic stage. This enables use with CMOS inputs as long
as one rule is observed; logic input voltages should not
exceed 6.5 volts or V+, whichever is smaller. To provide an
understanding of this rule, it is necessary to discuss the logic
input stage design.
LOGIC INPUT STAGE DESIGN
For simplicity, only one of the ten identical input circuits is
shown below. The DAC-100 uses a fast current-steering
technique that switches a bit-weighted current between the
positive supply (V+) and the analog output, which is usually
constrained to be at zero volts (virtual ground) by an external
summing amplifier.
v-
DAC-100 - LOGIC INPUT STAGE
DIGITALLY PROGRAMMED LEVEL DETECTOR
ANALOG
OUTPUT
ZERO
VOLTS
VREF
1 = VIN
> VREF
O=VtN-Oo-o---:-+---t---f'
REFERENCE
INPUT
CAPACITIVE LOADING
The output operational amplifier provides stable operation
with capacitive loads up to 100pF.
ANALOG
REFERENCE OUTPUT
Reference output current, lref' should not exceed
GROUND
100~A.
INTERFACING WITH CMOS LOGIC
The DAC-20810gic input stage requires approximately 1~A,
lin, and is capable of operation with inputs between -5V and
(V+ -0.7 Volts). The wide input voltage range allows direct
CMOS interface with no additional components required.
Full-Scale output voltage is trimmed using.the circuit configuration shown above. Low tempco metal-film resistors are
recommended. External components should be mounted
near the package to ensure good temperature tracking.
REFERENCE INPUT BYPASS
Low noise and fast settling operation can be obtained by
bypassing the Reference Input to Analog Ground with a
O.01~F monolithic capacitor.
EXTERNAL REFERENCES
Positive external reference voltages may be applied to the
reference input terminal to improve Full-Scale temperature
coefficient. External references are used when cascading
several converters or when tracking is required between system elements.
GROUNDlflfG
Separate digital and analog grounds have been provided for
optimum noise rejection. Best results will be obtained when
analog and digital ground are connected together at one
point only. This configuration ensures neglible digital currents flowing in analog ground.
MULTIPLYING OPERATION
Two-quadrant multiplying operation is achieved by applying
an analog input (0 to +10V) to the Reference input terminal.
The DAC output is the scaled product ofthe input voltage and
the digital code.
APPLICATIONS INFORMATION
SIGN - MAGNITUDE CODING TABLE
SIGN BIT
MSB
LOWER RESOLUTION APPLICATIONS
For applications requiring less than 8-Bit resolution, connect
unused logic inputs to ground.
LSB
+ FULL-SCALE
-1 LSB
UNIPOLAR OPERATION
Operation as an 8-Bit binary converter may be implemented
by connecting the Sign-Bit to +5V for positive Full-Scale
output, and OV for negative Full-Scale.
+ HALF-SCALE
0 0 0 0 0 0 0
ZERO-SCALE (+)
+5 VOLT OPTION
The output voltage range can be modified by connecting the
5V option pin (pin 13) to the analog output (pin 14). The 5V
11-86
0 0 0 0 0 0 0 0
ZERO-SCALE (-)
-HALF-SCALE
0
0
-FULL-SCALE
+1 LSB
0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
1/86, Rev. A
------------I~ DAC-208 9-BIT VOLTAGE-OUTPUT D/A CONVERTER
UNIPOLAR OPERATION
5VOPTION
+15V
MSB 82 83 84
85 B6 87
88 58
REF-Ol
15
REF
DAC-208
IN
ANALOG DIGITAL
vANALOG
GROUND
V+
GROUND GROUND
10
12
OUTPUT
'6
9
RANGE
o -+5V
10Mf
SHOWN WITH
EXTERNAL REFERENCE
v+
APPLICATIONS
AUDIO ATTENUATOR
V+
2QkH
V-
+5V
3V :$;V REF :,,>10V
AUDIO
INPUT
10kn
€9
> __.....___
AUDIO
OUTPUT
---1~NEF
}-----<>8
CAG-20B
+5V
ANALOG
GROUND
DIGITAL
GROUND
INPUTS
Ql
Q2
03 04
05 06
Q7
as
74LS116
DIGITAL
INPUT
11-87
RESET
ENABLE
1/86, Rev. A
II
DAC-210
ll-BIT VOLTAGE-OUTPUT D/A CONVERTER
110 BITS PLUS SIGN)
Precision Monolithics Inc.
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
The DAC-210 is a complete, monolithic 10-bit plus sign DAC
with a ± 10V output. A precision voltage reference, a logic
controlled polarity switch and output amplifier are included.
Linearity, monotonicity, and full-scale temperature coefficient are guaranteed over the full operating temperature
range. Ease of application is achieved by the total D/A system
specs given for nonlinearity and zero-scale offset. System
specs eliminate the complex error budget analysis required
by less "complete" DACs. Sign-magnitude coding minimizes
the "major-carry" zero-code errors inherent in offset coding
schemes. Reliability is enhanced by a monolithic design,
100% burn-in, and a hermetic DIP package. MIL-STD-883
Class B processing is available on -55 0 C to +1250 C grades.
Complete ........... Includes Reference and Op Amp
Bipolar Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 10V
Sign-Magnitude Coding
No Bipolar Offset Adjustment Required
10-Blt Linearity Maintained over Full Temperature
Multiplying Operation
Fast.............................. 1.5/Ls Settling Time
Monotonlclty Guaranteed
Reliable ............................. 100% Burned-In
Models with MIL-STD-883 Class B Processing Available
ORDERING INFORMATIONt
18·PIN HERMETIC DUAL IN-LINE PACKAGE
TEMPCO
(ppmrc)
±40
±60
±30 Typ
NL%FS
MILITARY
COMMERCIAL
±O.O5
±O.O5
±O.10
DAC210AX'
DAC210BX'
DAC210EX
DAC210FX
DAC210GX
PIN CONNECTION
• For devices processed in total compliance to MIL-STD-883. add /883 after
part number. Consult factory for 883 data sheet.
t All commercial and industrial temperature range parts are available with
burn-in. For ordenng information see 1986 Data Book. Section 2.
18-PIN DIP
(X-Suffix)
SIMPLIFIED SCHEMATIC
DIGITAL lOGIC INPUTS
(
BIT 1
1
W2
W3
W4
WS
W.
W.
WS
W9
23456789
BIT 10 '\
10
SIGN BIT
olGI
TAL
GND
R/2
v-
11·88
1/86, Rev. A
~ DAC-210 11-BIT VOLTAGE-OUTPUT D/A CONVERTER
ELECTRICAL CHARACTERISTICS- MILITARY AND COMMERCIAL GRADES atVs=±15V,-55°e::; TA::;+ 125°e,
for A and B grades. ooe::; TA::; +70oe for E, F and G grades, unless otherwise noted.
DAC-210AlE
PARAMETER
SYMBOL
Resolution
Including Sign
II
II
II
10
10
9
Nonlinearity
Zero-Scale
Offset Voltage
Bipolar Full Range
Voltage Symmetry
NL
TA = 2SoC
TA = Full Range
TA = Full Range (A onlyl
-
MAX
MIN
TVP
DAC-210G
MIN
Monotonlclty
TYP
DAC-210B/F
CONOITIONS
MAX
±O.OS
±O.OS
±0.07S
±O.OS
±OlO
Vzs
TA=2SoC
TA = Full Range
±O.OS
±0.06
±O.I
±O.I
V FRS
TA =2SoC
TA = Full Range
40
SO
60
70
Vzss
TA = Full Range
Tc
I ntemal Reference
External Reference
MIN
TYP
MAX
UNITS
Bits
Bits
±O.IO
%FS
%FS
60
mV
SO
(VFR+-I VFR-I I
Zero-Scale
Voltage Symmetry
2
mV
(Vzs+ - Vzs-I
Gain Tempco
Output Voltage
Range
VOR +
RL =2kO
VCR-
Differential
Nonlinearity
DNL
TA =25°C
Selliing Time
Ts
(Note 41
Reference Input
Slew Rate
SRREF
Reference Input
Impedance
Z,N
Reference Input
MultiplYing Range
IVR m
Reference Amplifier
Bandwidth
BW
Reference Output
Voltage
VREF
DACOutput
Current
10
Reference Output
Current
IREF
Output Slew Rate
SRo
Logic Input Current
liN
LogiC "0" Input
Voltage
V,NL
Logic "I" Input
Voltage
V,NH
Power Supply
Sensitivity
(Note 21
Pss
Positive Supply
Current
Negetlve Supply
Current
ForO 1% TYPical
Nonlinearity
(Note II
±40
±60
±IS
+IIS
-10.0
+10.0
-II.S
+10.0
-I1.S
+II.S
-10.0
±I
+10.0
-II.S
±I
ppm/oC
+11 S
-10.0
V
±I
LSB
I.S
I.S
I.S
I'S
I.S
I.S
I.S
VII's
200
200
200
MO
10
3
3
10
3
0
7.6
S
0
100
10
V
±2
7.6
S
0
100
±IO
±2
0.&
2.0
V
S
mA
100
10
10
-SVSV,SV+
I'A
10
±IO
±2
0.&
2.0
VII's
±IO
I'A
0.&
V
2.0
V
TA =2SoC
O.OlS
O.OS
O.OlS
O.OS
O.otS
0.1
TA = Full Range
o.olS
0.1
O.OlS
0.1
O.otS
0.1
1+
7
9
7
9
1-
-10
-12
-10
-12
%VFsN
NOTES:
1. Guaranteed by design.
2. Power Supplies - The DAC-210 Will operate within specifications for
power supplies ranging from ±I2V to ±I&V. Power supplies should be
bypassed near the package with a 0.1 I'F disk capacitor.
- ---------
-10
9
mA
-12
mA
3. Guaranteed by VOR test, RL = 2kO.
4. To within ±SmV of final sellied value, (±IO volt output step, RL = 2kO. I
1/86, Rev. A
11-89
-~
U
0
~
~
~......
C)
76
-
~
C)
MHz
(Note 31
~
0
±30
±30
±30
~
-------
------- ------
CS
II
-------------l~ DAC-210 11-BIT VOLTAGE-OUTPUT D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
DAC-210A, B ....................... -55° C to + 125° C
DAC-210E, F, G ........................ O°C to +70°C
DICE Junction Temperature (Tj) ....... -65° C to + 150° C
Storage Temperature Range ........... -65°C to +150°C
V+ Supply to Analog Ground .................. 0 to + 18V
Analog Ground to Digital Ground. . . . . . . .. .. .. 0 to ±0.5V
Logic Inputs to Digital Ground ........ -5V to (V+ -0.7V)
V+ Supply to V- Supply ............................ 36V
Internal Reference Output Current .. . . . . . . . . . . . . .. 300ltA
Reference Input Voltage ....................... 0 to + 10V
Internal Power DisSipation ...................... 500mW
Derate Above 100°C .......................... 10mW/oC
Lead Temperature (Soldering, 60 sec) ............. 300°C
Output Short-Circuit Duration ................. Indefinite
(Short-circuit may be to ground or either supply.)
NOTE: Absolute rallngs apply to both DICE and packaged parts unless
otherwise noted.
DICE CHARACTERISTICS
1. 81 (MS8)
2.82
3.83
4.84
5. 85
6. 86
7. 87
8. 88
10.
11.
12.
13.
14.
15.
810 (LSB)
DIGITAL GROUND
yANALOG GROUND
ANALOG OUTPUT
REFERENCE INPUT
16. y+
17. REFERENCE OUTPUT
18. SIGN BIT
NOTE: For5voltoutputoptlon (+5Vonly) * Isconnectedtoanalogoutput **IS
connected to analog ground
9. 89
DIE SIZE 0.117 X 0.086 Inch, 10,062 sq. mils
(2.972 X 2.18 mm, 5.942 sq. mm)
For additional DICE information refer to
1986 Data Book, Section 2.
WAFER TEST LIMITS at Vs = ± 15V, + 10V full-scale output, TA =25°C, unless otherwise noted.
PARAMETER
CONDITIONS
Resolution
Bipolar Output
Unipolar Output
DAC-210N
LIMIT
DAC-210G
LIMIT
DAC-210GR
LIMIT
11
10
11
10
11
10
Bits MAX
±0,05
±01
±0,2
%FSMAX
±5
±10
±10
mVMAX
±1
±2
±2
mVMAX
UNITS
10
Monotonicity
Nonlinearity
Sign-Bit High, All Other
Zero-Scale Offset
Inputs Low
Zero-Scale Symmetry
Vzs + - Vzs-
Full-Scale Bipolar
Bits MIN
± 10V Full-Scale
±40
±80
±80
mVMAX
Power Supply
Rejection
Vs~±12Vto±18V
005
0,05
0,1
%VFslV MAX
Power Consumption
IOUT~O
300
300
300
mWMAX
0,8
0,8
0,8
V MAX
2
2
VMIN
11,5
10
115
10
11,5
10
V MAX
VMIN
-10
-115
-10
-11,5
-10
-11.5
V MAX
VMIN
±1
±1
±1
LSBMAX
Symmetry
Logic Input "0"
Logic Input "1"
V+ (Sign-Bit High)
Analog Output Voltage
(All Bits High)
V- (Sign-Bit Low)
Differential Nonlinearity
NOTE:
Electrical tests are performed at wafer probe to the limits shown Due to variations In assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate speCificatIOns based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ± 15V and + 10V full-scale output, unless otherwise noted.
DAC-210N
TYPICAL
DAC-210G
TYPICAL
DAC-210GR
TYPICAL
UNITS
Internal Reference
15
30
30
ppm/'C
ts
To ±112 LSB
10 Volt Step
1,5
1,5
1.5
I'S
liN
TA~25'C
PARAMETER
SYMBOL
CONDITIONS
Full-Scale Tempeo
TCVFS
Settling Time
(TA ~ 25'C)
Logic I nput Current
I'A
11-90
1/86, Rev. A
--------------l~ DAC-210 11-81T VOLTAGE-OUTPUT D/A CONVERTER
CONNECTION INFORMATION
TYPICAL APPLICATIONS
FULL-SCALE ADJUSTMENT - Full-scale output voltage
may be trimmed by use of a potentiometer and series resistor
as shown; however, best results will be obtained if a low
tempco resistor is used or if pot and resistor tempcos match.
Alternatively, a single pot of 2: 75kO may be used.
10-BIT SIGN-MAGNITUDE ADC
ANALOG
INPUT
±10V
+15V
CLOCK START +5V
SERIAL
DATA
FULL SCALE ADJUSTMENT CIRCUIT
DIGITAL INPUTS
,r--MSB
LSB SIGN BIT V+
REFERENCE
OUTPUT
FULL
REFERENCE
SCALE ~......::'N::,P;:.UT'--I---+_---<
ADJUST
POT
LOWTC
10Kr.!
62K"
ANALOG
GROUND
v-
OIGITACGROUND
REFERENCE INPUT BYPASS - Lowest noise and fastest
settling operation will be obtained by bypassing the reference input to analog ground with a O.01I'F disk capacitor.
62kn
NOTES
1 CONNECT END OF CONV TO START
FOR CONTINUOUS OPERATION
2 FOR NON-CONTINUOUS OPERATION,
HOLD START LOW FOR ONe CLOCK
CYCLE CONVERSIONS BEGIN ON THE
NeXT LOW TO HIGH TRANSITION
3 CONVERSION IS COMPLETED IN 12
CLOCK CYCLES
VARIABLE REFERENCES - Operation as a two-quadrant
multiplying DAC is achieved by applying an analog input
varying between 0 and + 10V to the reference input terminal.
The DAC output is then the scaled product of this voltage and
the digital input.
APPLICATIONS INFORMATION
,,,-
LOWER RESOLUTION APPLICATION - For applications
not requiring full 10-bit resolution, unused logic inputs
should be tied to ground.
GROUNDING - For optimum noise rejection', separate digital and analog grounds have been brought out. Best results
will be obtained if these grounds are connected together at
one point only, preferably at the power supply, so that the
large digital currents do not flow through the analog ground
path.
CAPACITIVE LOADING - The output operational amplifier
provides stable operation with capacitive loads up to 100pF.
REFERENCE OUTPUT - For best results, reference output
current should not exceed 100I'A.
SIGN - MAGNITUDE CODING TABLE
SIGN-BIT
+ FULL-SCALE
-1 LSB
MSB
INTERFACING WITH CMOS LOGIC - The DAC-210's logic
input stages require about 11'A and are capable of operation
with inputs between -5 volts and V+. This wide input voltage
range allows direct CMOS Interface with no additional
components.
LSB
1 1 1 1 1 1 1 1 1 1
+ HALF-SCALE
1 0 0 0 0 0 0 0 0 0
ZERO-SCALE (+)
o0 0
o0 0
o0
ZERO-SCALE (-)
0
-HALF-SCALE
0
-FULL-SCALE
+1 LSB
0
0 0 0 0 0 0 0
USE WITH EXTERNAL REFERENCES - Positive polarity
external reference voltages referred to analog ground may be
applied to the reference input terminal to improve full-scale
tempco, to provide tracking to other system elements, or to
slave a number of DAC-210's to the reference output of any
one of them.
0 0 0 0 0 0 0
0 0 0 0 000
111111111
11-91
--------
----
1/86, Rev_ A
II
DAC-312
12-BIT HIGH-SPEED MULTIPLYING
D/A CONVERTER
Pn.."clsion MOllollthlcs
Jill:.
FEATURES
•
•
•
•
•
•
•
•
•
•
excellent power supply rejection ratio of ±.001% Fs/%.:lV.
Operating over a power supply range of +5/-11 V to ±18Vthe
device consumes 225mW at the lower supply voltages with an
absolute maximum dissipation of 375mW at the higher
supply levels.
Guaranteed Differential Nonlinearity ........•.. 0.012%
Nonlinearity ..•..•.••.•.•.•.•.•.....••.....•. 0.025%
FaIt Settling Time ............................. 250nl
High Compliance ....................... -5V to +10V
Differential Outputs ......................... 0 to 4mA
Guaranteed Monotonlclty .. .. .. .. .. .. .. .. . .. ... 12 Bltl
low Full-Scale Tempco •..••. • • . • . . . • • . . • •• 10ppm/· C
Circuit Interface to TTL, CMOS, ECl, PMOS/NMOS
low Power Conlumptlon ...•.•.•..•.•.....••. 225mW
Indultry Standard AM8012 Pinout
With their guaranteed specifications, Single chip reliability
and low cost, the DAC-312 device makes excellent building
blocks for AID converters, data acquisition systems, video
display drivers, programmable test equipment and other
applications where low power consumption and complete
input/output versatility are required.
GENERAL DESCRIPTION
PIN CONNECTIONS & ORDERING INFORMATIONt
The DAC-312 series of 12-bit multiplying digital-to-analog
converters provide high speed with guaranteed performance
to 0.012% differential nonlinearity over the full commercial
operating temperature range.
Based on the segmented design approach pioneered by PMI
with the COMDAC@ line of data converters, the DAC-312
combines a 9-bit master DlA converter with a 3-bIt (MSB's)
segment generator to form an accurate 12-bit DlA converter
at low cost. This technique guarantees a very uniform step
size (up to ±1I2 LSB from the ideal), monotonicity to 12 bits
and integral nonlinearity to 0.05% at its differential current
outputs. In order to provide the same performance with a
12-blt R-2R ladder deSign, an integral nonlinearity over
temperature of 1/2 LSB (0.012%) would be required.
20-PIN HERMETIC
DUAl-IN-LiNE
PACKAGE
(R-Sufflx)
MODEL
TEMP RANGE
DNL
DAC312BR
DAC312FR
DAC312ER
-SS·CI +12S·C
O· CI+ 70· C
0·CI+70·C
±1 LSB
± 1 LSB
±1/2 LSB
Military Temperature Range Devices
With MIL-STD-883 Class B Processing
The 250nssettling time with low glitch energy and low power
consumption are achieved by careful attention to the circuit
design and stringent process controls. Direct interface with
all popular logiC families is achieved through the logic
threshold terminal.
MODEL
TEMP
DNL
DAC312BRl883
-SS·C/+12S·C
±1 LSB
• For devices processed In total compliance to MIL-STD-883, add /883 after
part number. Consult factory for 883 data sheet.
tAli commercial and Industrial temperature range parts are available with
burn-In. For ordering Information see 1986 Data Book, Secllan 2.
High compliance and low drift characteristics (as low as
10ppm/·C) are also features of the DAC-312 along with an
FUNCTIONAL DIAGRAM
82
V(+I
83
84
B6
Be
87
B8
89
a10
811
LSB
812
-
~----~~~-+~~~~-Hr-~-+~~--~~Io
~--~1-~~+T~~++~~HH~Hr~~-r~~
16
COMP
17
V{-)
Manufactured under one or more of the following patents: 4,055,773; 4,058,740; 4,092,839
11-92
1/86, Rev. A
-----------t~ DAC-312 12-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
DAC-312B .......................... -55°C to +125°C
DAC-312E, DAC-312F ................... 0° C to + 70° C
DICE Junction Temperature. • • • •• . • . •. -65° C to + 150° C
Storage Temperature (Tj ) •••••••••• • • ••
-65° C to + 125° C
Lead Temperature (Soldering, 60 sec) ............. 300° C
Power Supply Voltage ............................. ± 18V
ELECTRICAL CHARACTERISTICS
Logic Inputs
.............................. -5V to +18V
Analog Current Outputs
................... -8V to + 12V
Reference Inputs V 14, V15 •••••••••••••••.••••••. V- to V+
Reference Input Differential Voltage (V14, to VIS) ..•• ±18V
Reference Input Current (114) ..•.••.••••.••••..•• 1.25mA
NOTE: Absolute ratings apply to both DICE and packaged parts. unless
otherwise noted.
at Vs = ±15V, IREF= 1.0mA, -55°C:5 TA:5125°C for DAC-312B, O°C:5 TA:5 70°C for
DAC-312E, DAC-312F, unless otherwise noted. Output characteristics refer to both lOUT and lOUT.
DAC-312E
PARAMETER
SYMBOL
CONDITIONS
MIN
TVP
DAC-312B/F
MAX
MIN
Resolution
12
12
Monotonicity
12
12
Differential
Nonlinearity
D.N.L.
Nonlinearity
N.L.
Deviation from ideal step size
Deviation from ideal straight line
VREF = 10.OOOV
R'4 = R'5 = 10.000kO
Full-Scale Current
3.967
Full-Scale Tempco
Output Voltage
Compliance
VOC
D.N.L. Specification guaranteed
over compliance range
Full-Scale
Symmetry
I FSS
IIFSI-IIFSI
Zero-Scale Current
IZS
Settling Time
ts
All bits switched
50% point logic swing to
50% point output (See Note)
Propagation
Delay - all bits
Output Resistance
Output Capacitance
Logic Input Levels "0"
V,L
Logic Input Levels "I"
V,H
Sensitivity
dl/dt
R'41eQI = 8000
Cc = OpF (See Note)
PSSI FS+
PSSI FS-
V+=+13.5Vto+16.5V, V-=-15V
V-= -13.5V to -16.5V, V+ = +15V
Power Supply
Range
V-
Power Supply
Current
1+
11+
%FS
3.999
4.063
mA
±IO
±O.OOI
±40
±0.OO4
ppm/OC
%FS/OC
+10
Volts
+10
3.935
-5
±I
±0.4
0.10
500
250
500
ns
25
50
25
50
ns
>10
>10
MO
20
20
pF
0.8
0.8
40
-5
+18
-5
+18
o
-2
o
-0.5
-2
±0.0005
±O.00025
±O.OOI
±O.OOI
%FS/%aV
18
-10.8
Volts
-0.5
-
V+ = +5V. V- = -15V
V+ = +15V. V- = -15V
Volts
4
4
1-
Volts
Volts
2
40
V+=+5V. V-=-15V
V+=+15V, V-=-15V
±2
250
±0.OOO5
±0.00025
4.5
-18
V+
Power
Dissipation
±0.05
2
Logic Input Swing
Power Supply
±0.05
±30
±0.003
VLC = GND
Reference Bias
Current
Reference Input
Slew Rate
Bits
%FS
LSB
±IO
±O.OOI
V,N =-5 to +18V
Logic Input Current
Bits
010
To ±1/2 LSB, all bits
switched ON or OFF (See Note)
UNITS
±0.0250
±I
4.031
±0.4
MAX
±0.0125
±0.5
3.999
-5
TVP
±O.OOI
±O.OOI
18
-10.8
4.5
-18
3.3
-13.9
3.9
-13.9
7
-18
7
-18
3.3
-13.9
3.9
-13.9
7
-18
225
267
305
375
225
267
305
375
7
mA
-18
mW
NOTE: Guaranteed by design.
11-93
1/86, Rev. A
II
----------I~ DAC-312 12-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
DICE CHARACTERISTICS
1. B1 (MSB)
2. B2
3. B3
11. B11
12. B12 (LSB)
5. B5
6. B6
13.
14.
15.
16.
7.87
17. V-
8. B8
18. 10
19.
20. V+
4.84
VLC/AGND
VREF (+)
VREF (-)
COMP
ro
9.89
10. B10
For additional DICE information refer to
1986 Data Book, Section 2.
DIE SIZE 0.140 X 0.095 inch, 13,300 sq. mils (3.56 X 2.41 mm, 8.58 sq. mm)
WAFER TEST LIMITS
at Vs
= ± 15V, IREF =1.0mA, TA =25 ·C, unless otherwise noted. Output characteristics refer to
both lOUT and lOUT'
PARAMETER
SYMBOL
CONDITIONS
DAC-312N
LIMIT
DAC-312G
LIMIT
UNITS
12
12
Bits MIN
Resolution
Monotonlcity
Nonlinearity
Output Voltage
Compliance
VOC
Full-Scale
Current
Full-Scale Current
Change <1/2 LSB
VREF = 10.0OQV
R,., R,s = 10 OOOkfl
12
12
Bits MIN
±005
±0.05
%FSMAX
+10
-5
+10
-5
V MAX
VMIN
4.031
3.967
4.063
3.935
mAMAX
mAMIN
~AMAX
Full-Scale Symmetry
I FSS
±1
±2
Zero-Scale Current
I zs
0.1
0.1
~AMAX
±0.012
±1/2
±0025
±1
%FSMAX
Bits (LSB) MAX
0.8
0.8
V MAX
+18
-5
VMAX
VMIN
Differential
Nonlineanty
DNL
Deviation from
ideal step size
Logic Input Levels "0"
V,L
VLC = GND
Logic Input Levels "1"
V,H
VLC = GND
VMIN
Logic Input SWing
V's
+18
-5
Reference Bias
Current
115
-2
-2
~AMAX
Power Supply
SensitivIty
PSSI FS+
PSSI FS _
V+ = +13.5V to +16.5V. V-= -15V
V- = -13.5V to -16.5V, V+ = +15V
±0.001
±0.001
±0.001
±0.001
%/%MAX
Power Supply
Current
1+
1-
Vs =±15V
'REFS 1.0mA
-18
-18
Power
Dissipation
Po
Vs =+15V
I REF ",0mA
375
375
mAMAX
mWMAX
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations In assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS
at 25°C; Vs = ±15V, and IREF
= 1.0mA, unless otherwise noted. Output
characteristics refer to both lOUT and lOUT'
PARAMETER
SYMBOL
Reference Input
Slew Rate
dl/dt
Propagation Delay
tpLH • tpHL
Any Bit
Settling Time
ts
To ±1/2 LSB. All
Bits SWitched ON
orOFF.
Full-Scale
TC ,FS
DAC-312N
TYPICAL
CONDITIONS
DAC-312G
TYPICAL
8
11-94
UNITS
mA/~s
25
25
ns
250
250
ns
±10
±10
ppm/·C
1/86, Rev_ A
----------l~ DAC-31212-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT CURRENT vs
OUTPUT VOLTAGE
(OUTPUT VOLTAGE COMPLIANCE)
50
36 VH"!-15V
1
t-
~
24
"
20
t::>
I!:::>
0
TA =TMIN TOTMAX
I
r
I
08
00
-14
I
I
-10
-6
-
~::>
-1 1
I
I
I
I
I
I
I
I
-
N~TESI
f--
r rI I
1
I
I
r
10
-14
14
r 1
-10
-6
1
ALL BITS ON
1
I
I
1
1
POWER SUPPLY CURRENT
vs TEMPERATURE
/"
V
-138
-136
~~
-4
1
POWER SUPPLY CURRENT vs
POWER SUPPLY VOLTAGE
-142
-2
I
10
-2
..;.,
J
V 1S REFERENCE COMMON MODE (VOLTS)
-140
FOR OTHER V!-! OR !REF'
~~;~~;~~TL.i~~~~~~~E:
~~,~
"
::-
:
1
-!OTMA~_
TA=+MIN
'REF = 0 2mA
04
:
IS ALWAYS iV-)+1 B+(lREFX3kSH
DB
-2
f' ! :~:~~S~I~~~~~N~ci~'6TFES ~ I
'I OUTPUT VOLTAGE WITH
•
VH" -16V, I REF"':; 1 OmA
I
10
IS ALWAYS (V+) -1 25V
NEGATIVE COMMON MODE VOL rAGE
'REF=05mA
16
16~~nl~
:: ~::::;i~~:"(\~}f~..:i+'-+_-l
POSITIVE COMMON MODE VOLTAGE
OUTPUT VOLTAGE (VOLTS)
~L-~~~~~~~~~
14
-100
-50
0
50
100
150
200
TEMPERATURE fC)
TRUE AND COMPLEMENTARY
OUTPUT OPERATION
Vs" ±15V
- I REF = 1 DmA-
"
I
-134
-132
-13
"
-14
-15
r--
12
I
I
a:: -12
~
rl
0
-"
-10
-
"
-
:~~11 WHffii
~
28
32
r
a:
a: 24
::>
t- 20
I
IRE~=02lA
I
12
1l~
t-
~
04
a:
.,
36
E
ALL, BITS ON
IREF =05mA
16
I I
'REF = 1 OmA
40
.I
I
I
I
28
a:
a:
::>
H~I-I.J08V I
32
42
I
IREF - 1 OmA
40
OUTPUT COMPLIANCE
vs TEMPERATURE
REFERENCE AMPLIFIER
COMMON-MODE RANGE
o
8
'~EF ~ 1 O~A
J(-l
10
12
14
16
18
20
] EtH·jj J
-100
REFERENCE AMPLIFIER
SMALL-SIGNAL
FREQUENCY RESPONSE
11111111
10
JJillllL
10
I
-8
-10
-12
001
150
200
250
GAIN ACCURACY vs
REFERENCE CURRENT
10
I 11111111
I 11111111
I I
I I
~
R14 = R15 - lkn
RL = loon, Cc = 5pF
V15 = oV
VIN =1Vp-p
CENTERED AT +500mV
"'''
~
--<
100
12
I
RL = 200n.
VR1S= OV
VIN = 5OmVp·p
CENTERED AT +l00mV
-4
50
REFERENCE AMPLIFIER
LARGE-SIGNAL
FREQUENCY RESPONSE
R14 - R15 = lkn
-2
0
~
>
~ 04
a:
03
-8
.,
-10
"
01
--<
1 CC OpF
2 CC=5pF
3 CC = lOpF
FREQUENCY (MHz)
"
~ 07
~ 06
0
~ 05
a
-4
I
10
09
~ 08
"
-2
Ii'll
01
(111111111111)
IREF= 1 OmA
TEMPERATURE (OC)
POWER SUPPLY VOLTAGE (VOLTS)
12
-50
(0000 0000 0000)
-12
001
~
z 02
01
10
FREQUENCY (MHz:)
11-95
0
0
01
02
03
04
05
06
07
08 09
10
REFERENCE INPUT CURRENT (mAl
1/86, Rev. A
----------I~ DAC-312 12-81T HIGH-SPEED MULTIPLYING D/A CONVERTER
BASIC CONNECTIONS
NEGATIVE LOW IMPEDANCE OUTPUT OPERATION
POSITIVE LOW IMPEDANCE OUTPUT OPERATION
OAe-3l2
OAC-312
409.
'FR" 4096
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC),
CONNECT INVERTING INPUT OF OP-AMP TO
TO GROUND
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC oAe),
CONNECT NON-INVERTING INPUT OF OP-AMP TO
(PIN 19), CONNECT
ro (PIN 191. CONNECT '0 (PIN 18)
ro
'0 (PIN 18) TO GROUND
ACCOMMODATING BIPOLAR REFERENCES
BASIC NEGATIVE REFERENCE OPERATION
RREF
r,...------..
VREFH
REF
14~--------------'
-=
DAC-312
o-___"R,,1·r--'5..
L..-_ _ _ _J
14
,.
R'N
"::"
x 4 X 'REF
NOTE'
RREF SETS IFS: R16 IS fOR A
DAC-312
BIAS CURRENT CANCELLATION
'REF;;" PEAK NEGATIVE SWING OF 'IN
RECOMMENDED FULL-SCALE
ADJUSTMENT CIRCUIT
LOWTC
14
-
Rl.
(OPTIONAL)
,.
VREF o-~__4~5k~"~~14r--------------,
+5 ooov
DAC -312
IREF{+) .... 'mA
HIGH INPUT
IMPEDANCE
POT
BASIC POSITIVE REFERENCE OPERATION
LSB
81 B2 B3 B4 B5 S6 87 BB 89 810 S11 812
IREFR15
APPROX.
Skll
PULSED REFERENCE OPERATION
MS.
V REF (+)
«
J
RREF
(R16) 14
t
lOkll
VREF (+) MUST BE ABOVE PEAK POSITIVE SWING OF VIN
V REF (+)
OAC-312
39k~15
:! R
'0
(OPTIONAL RESISTOR
REF
FOR OFFSET INPUTS
O~~R~'N~~'~___~4!:Jr-------------~ 18
V
L
REQ .... 800n
15
Rp
DAC-312
16
19
20 13
FOR FIXED REFERENCE,
TTL OPERATION,
TYPICAL VALUES ARE.
ov.JL
VREF· +10.000V
VH
V REF (+)
4096
IFR = RREF
X 4096 X 4
TYPICAL VALUES:
RIN "1kSl
V{+) VLC RREF = 10 OOOkO
R15 = RREF
Rp = 4kO
VIN(+) = 1V
Cc' 001.F
V LC " OV (GROUND)
--L-.
ro
1
10 +
= IFR FOR ALL
LOGIC STATES
REO· RIN
11-96
1
1
+ R; + RREF
1/86, Rev. A
----------IIEMD
DAC-312 12-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
BASIC CONNECTIONS
INTERFACING WITH VARIOUS LOGIC FAMILIES
TTL
ECl
HTl
V TH '" +1 4V
V(+)
OAe-3l2
2Dkn
13kn
V lC
13
TO PIN 13
Vle
V le
R
i
20kn
+15V
TO PIN 13
V TH '" V LC + 14V
39kn
62kn
400pA
FOR +15V CMOS
V TH =+76V
lkH
-S2V
Vle
V
1
z = 6 2V
NOTES
1 seT THE VOLTAGE "Au TO THE DESIRED LOGIC
INPUT SWITCHING THRESHOLD
01M
-=-
'
2
ALLOWABLE RANGE OF LOGIC THRESHOLD IS
TYPICALLY -5V TO +135V WHEN OPERATING
THE OAe ON :t15V SUPPLIES
BIPOLAR OFFSET (TRUE ZERO)
ROFF
R1
2 aOOmA
5000kn
5k"
II
REF-ol
+10V
OAC-3l2
VREF
R14"'-- =R15
1.0mA
812
R15
R2
OPTIONAL FOR
2's COMPLEMENT
10kn
5k"
OPERATION
MS8
lS8
NOTE.
CODE MAY BE COMPLEMENTED BY REVERSING '0 &
CODE FORMAT
OUTPUT SCALE
Offset binary;
true zero output
Positive full-scale
Positive full-scale -LSB
+LSB
Zero-scale
-LSB
Negative full-scale +LSB
Negative full-scale
2's complement;
true zero output
MSB complemented
(Need inverter at 81 )
iQ
MSB
Bl
B2 B3 B4 B5 B6 B7 B8
Positive full-scale
Positive full-scale -LSB
+1 LSB
Zero-scale
-1 LSB
Negative full-scale + LSB
Negative full-scale
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
B9 Bl0 Bll
1
0
0
1
0
0
0
0
0
1
0
0
LSB
10
B12 (mAl
(mAl
VOUT
3.999
3998
0000
0.001
99951
-9.9951
0
2.001
2.000
1.999
99902
1998
0.0049
1999
0.000
2.000 -0.0049
0
0
0001
0.000
3998
3999
3999
3.998
0000
99951
0001
1998
1999
99902
00049
0000
-00049
1
0
0
0
0
0
1
0
2001
2000
1999
2000
0.001
0000
3998
3999
----
~---------
-10.000
-9.9951
-10000
1/86, Rev. A
11-97
--~-~--'"-~------
10
--~
- _ . _ - - .-. . - - - - -
----
-----------I1fMD
DAC-312 12-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
BASIC CONNECTIONS
BASIC UNIPOLAR OPERATION
A1
25k
A1'
10k"
REF-01
+10V
OAC-312
B12
V REF
R14"'-- =R15
1.0mA
A15
A2
10kO
2.51<
MSB
LSB
NOTE
CODE MAY BE COMPLEMENTED BY REVERSING '0 &
CODE FORMAT
OUTPUT SCALE
Straight Binary,
Positive full-scale
Positive full-Scale - LSB
LSB
Zero-scale
unipolar with true
mput code, true
zero output
Complementary binary;
unipolar with
complementary Input
code, true zero output
Positive full-scale
Positive full-scale -LSB
LSB
Zero-scale
iQ
MSB
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
1
o
o
o
o
1
1
1
1 1
1 1
1
1
000000000
0000000000
o o o o o o
o o o o o o
o o
o o
1
1
1
o
o
1
LSB 10
B12 (mA)
1
o
1
o
o
1
o
1
10
(mA)
VOUT
3999
3998
0.001
0000
0000
0.001
3998
3.999
9.9976
9.9951
00024
00000
0000
0001
3998
3999
3.999
3998
0001
0.000
9.9976
99951
0.0024
00000
SYMMETRICAL OFFSET OPERATION
A1
25k
?»-<_ _
A1'
10kn
~\
IO~
REF-Ol
+10V
DAC-312
V_OOUT
.'2
V REF
R14=-- =R15
10mA
A15
10kn
M~B
CODE MAY BE COMPLEMENTED BY REVERSING
OUTPUT SCALE
Straight offset binary,
Positive full-scale
symmetrical about zero,
no true zero output
Positive full-scale -LSB
(+ I Zero-scale
I-I Zero-scale
Negative full-scale -LSB
Negative full-scale
o
o
o
Positive full-scale
o
Positive full-scale -LSB
I +I Zero-scale
I-I Zero-scale
NegatIVe full-scale -LSB
Negative full-scale
'a & iQ
MSB
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
CODE FORMAT
no true zero output
MSB complemented
(need Inverter at B1)
125k
LSB
NOTE
1 's complement,
symmetrical about zero,
R2
R3
25k
"
OPTIONAL
~.
1
1
1
o
o
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
LSB 10
B12 (mA)
1
1
1
o
o
1
1
1
1
1
0
1
1
1
o
o
o
1
1
1
1
0
1
o
1
o
0
0
o
o
0
0
o o
o o
0
0
o o
o o
o
o
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
o
1
o
o
1
o
o
1
o o
1
1
1
1
1
1
o o o o o o o o o
1
1
1
o
o
1
1
1
o o o o o o o o
o o o o o o o o
1
11-98
1
1
1
o
o
o
1
o
10
(mA)
VOUT
3999 000
99976
3998 0001
99927
2000 1999 00024
1999 2000 -00024
0.001 3998 -99927
0000 3.999 -9.9976
3999 0000 9.9976
3998 0001
99927
2000 1999 00024
1999 2000 -00024
0001 3998 -99927
0000 3999 -99976
1/86, Rev. A
----------I~ DAC-312 12-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
APPLICATIONS INFORMATION
REFERENCE AMPLIFIER SETUP
The DAC-312 is a multiplying D/A converter in which the
output current is the product of a digital number and the
input reference current. The reference current may be fixed
or may vary from nearly zero to +1.OmA. The full range output
current is a linear function of the reference current and is
given by:
4095
IFR = 4096 X 4 X (IREF) = 3.999IREF'
where I REF = 114
I n positive reference applications, an external positive reference voltage forces current through R14 into the V REF (+)
terminal (pin 14) of the reference amplifier. Alternatively, a
negative reference may be applied to V REF (-) at pin 15 Reference current flows from ground through R14 Into VREF(+) as
in the positive reference case. This negative reference connection has the advantage of a very high impedance presented at pin 15. The voltage at pin 14 is equal to and tracks
the voltage at Pin 15 due to the high gain of the internal
reference amplifier. R15 (nominally equal to R14) is used to
cancel bias current errors.
Bipolar references may be accomodated by offsetting VREF
or pin 15. The negative common-mode range of the reference
amplifier is given by: VCM-= V- plus (I REF X 3kO) plus 1.23V.
The positive common-mode range is V+ less 1.BV.
When a DC reference is used, a reference bypass capacitor is
recommended. A 5.0V TTL logic su pply is not recommended
as a reference. If a regulated power supply is used as a
reference, R14 should be split into two resistors with the
junction bypassed to ground with a 0.1/LF capacitor.
For most applications the tight relationship between IREFand
IFS will eliminate the need for trimming IREF. If required, full
scale trimming may be accomplished by adjusting the value
of R14, or by using a potentiometer for R14. An improved
method of full-scale trimming which eliminates potentiometer T.C. effects is shown in the Recommended Full-Scale
Adjustment circuit.
The reference amplifier must be compensated by uSing a
capacitor from pin 16 to V-. For fixed reference operation, a
0.01/LF capacitor is recommended. For variable reference
applications, see section entitled "Reference Amplifier Compensation for Multiplying Applications."
MULTIPLYING OPERATION
The DAC-312 provides excellent multiplying performance
with an extremely linear relationship between IFS and IREF
over a range of 1mA to 1/LA Monotonic operation is maintained over a typical range of IREF from 100/LA to 1.OmA.
Although some degradation of gain accuracy will be realized
at reduced values of IREF. (See Gain Accuracy vs Reference
Current).
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
AC reference applications will require the reference amplifier
to be compensated using a capacitor from pin 16 to V-. The
value of this capacitor depends on the impedance presented
to pin 14 for R14 values of 1.0, 2.5 and 5.0kO, minimum values
of Cc are 5,10, and 25pF. Largervalues of R14 require proportionately increased values of Cc for proper phase margin.
For fastest response to a pulse, low values of R14 enabling
small Cc values should be used. If pin 14 is driven by a high
impedance such as a transistor current source, none of the
above values will suffice and the amplifier must be heavily
compensated which will decrease overall bandwidth and
slew rate For R14 = 1kO and Cc=5pF, the reference amplifier
slews at 4mA//Ls enabling a transition from IREF= 0 to IREF=
1 mA In 250ns.
Operation with pulse inputs to the reference amplifier may
be accommodated by an alternate compensation scheme.
This technique provides lowest full-scale transition times.
An internal clamp allows quick recovery of the reference
amplifier from a cutoff (IREF = 0) condition. Full-scale
transition (0 to 1mAl occurs in 62.5ns when the equivalent
impedance at pin 14 is BOOO and Cc = O. This yields a
reference slew rate of BmA//Ls which is relatively independent of RIN and VIN values.
LOGIC INPUTS
The DAC-312 design incorporates a unique logic input circuit
which enables direct interface to all popular logic families
and provides maximum noise immunity. This feature is made
possible by the large input swing capability, 40/LA logic input
current, and completely adjustable logic threshold voltage.
For V- = -15V, the logic inputs may swing between -5 and
+10V. This enables direct interface with +15V CMOS logic,
even when the DAC-312 is powered from a +5V supply. Minimum input logic swing and minimum logic threshold voltage
are given by : V- plus (IREF X 3kO) plus 1.BV. The logic
threshold may be adjusted over a wide range by placing an
appropriate voltage at the logic threshold control pin (pin 13,
VLc). The appropriate graph shows the relationship between
VLC and VTH over the temperature range, with VTH nominally
1.4 above VLC. For TTL interface, simply ground pin 13. When
interfacing ECL, an IREF:S 1mA is recommended. For interfacing other logic families, see block titled "Interfacing With
Various Logic Families". For general setup of the logic control circuit, it should be noted that pin 13 will sink 7mA typical;
external circuitry should be designed to accommodate this
current.
11-99
1/86, Rev_ A
81
-----------IIEHD
DAC-312 12-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided where '0+ iQ= I FR. Current appears atthe "true" output
when a "1" is applied to each logic input. As the binary count
increases, the sink current at pin 18 increases proportionally,
in the fashion of a "positive logic" 01 A converter. When a "0"
is applied to any input bit, that current is turned off at pin 18
and turned on at pin 19. A decreasing logic count increases iQ
as in a negative or inverted logic 01 A converter. Both outputs
may be used simultaneously. If one of the outputs is not
required it must still be connected to ground or to a point
capable of sourcing I FR; do not leave an unused output pin
open.
Both outputs have an extremely wide voltage compliance
enabling fast direct current-to-voltage conversion through a
resistor tied to ground or other voltage source. Positive compliance is 25V above V- and is independent of the positive
supply. Negative compliance is + 10V above V-.
The dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. This
feature is especially useful in cable driving, CRT deflection
and in other balanced applications such as driving centertapped coils and transformers.
POWER SUPPLIES
The OAC-312 operates over a wide range of power supply
voltages from a total supply of 20V to 36V. When operating
with V-supplies of-10Vor less, IREF:51 mA is recommended.
Low reference current operation decreases power consumption and increases negative compliance, reference amplifier
negative common-mode range, negative logic input range,
and negative logic threshold range; consult the various figures for guidance. For example, operation at -9V with 'REF =
1mA is not recommended because negative output compliance would be reduced to near zero. Operation from lower
supplies is possible, however at least 8V total must be applied
to insure turn-on of the internal bias network.
Symmetrical supplies are not required, as the OAC-312 is
quite insensitive to variations in supply voltage. Battery
operation is feasible as no ground connection is required;
however, an artificial ground may be used to insure logic
swings, etc. remain between acceptable limits.
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the
OAC-312 are guaranteed to apply over the entire rated operating temperature range. Full-Scale output current drift is
tight, typically ± 10ppmfO C, with zero-scale output current
and drift essentially negligible compared to 1/2 LSB.
The temperature coefficient of the reference resistor R14
should match and track that of the output resistor for min-
imum overall full-scale drift. Settling times of the OAC-312
decrease approximately 10% at-55° C; at+ 125 0 C an increase
of about 1S% is typical.
SETTLING TIME
The OAC-312 is capable of extremely fast settling times,
typically 2S0ns at I REF= 1.0mA. Judicious circuit design and
careful board layout must be employed to obtain full performance potential during testing and application. The logic
switch design enables propagation delays of only 2Sns for
each of the 12 bits. Settling time to within 1/2 LSB of the LSB
is therefore 2Sns, with each progressively larger bit taking
successively longer. The MSB settles in 2S0ns, thus determining the overall settling time of 2S0ns. Settling to 10-bit
accuracy requires about90 to 130ns. The output capacitance
of the OAC-312 including the package is approximately 20pF;
therefore, the output RC time constant dominates settling
time if RL > soon
Settling time and propagation delay are relatively insensitive
to logic input amplitude and rise and fall times, due to the
high gain of the logic switches. Settling time also remains
essentially constant for IREF values down to O.SmA, with
gradual increases for lower IREF values lies in the ability to
attain a given output level with lower load resistors, thus
reducing the output RC time constant.
Measurement of the settling time requires the ability to accurately resolve ± 1/2 LSB of current, which is ±SOOnA for4mA
FSR. In order to assure the measurement is of the actual
settling time and not the R.C. time of the output network, the
resistive termination on the output of the OAC must be
SOO ohms or less. This does, however, place certain limitations on the testing apparatus. At IREF values of less than
O.SmA, it is difficult to prevent RC damping of the output and
maintain adequate sensitivity. Because the OAC-312 has 8
equal current sources for the 3 most significant bits, the
major carry occurs at the code change of 000111111111 to
111000000000. The worst case settling time occurs at the zero
to full-scale transition and it requires 9.2 time constants for
the OAC output to settle to within ± 1/2 LSB (0.012S%) of its
final value.
The OAC-312 switching transients or "glitches" are on the
order of SOOmV-ns This is most evident when switching
through the major carry and may be further reduced by
adding small capacitive loads at the output with a minor
sacrifice in transition speeds.
Fastest operation can be obtained by using short leads, minimizing output capacitance and load resistor values, and by
adequate bypassing at the supply, reference, and VLC terminals. Supplies do not require large electrolytic bypass capacitors as the supply current drain is independent of input logic
states; 0.1 /LF capacitors at the supply pins provide full transient protection.
11-100
1/86, Rev. A
-----------i~ DAC-312
12-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
DIFFERENTIAL vs INTEGRAL NONLINEARITY
Integral nonlinearity. for the purposes of the discussion. refers to the "straightness" of the line drawn through the individual response pOints of a data converter. Differential nonlinearity. on the other hand. refers to the deviation of the
spacing of the adjacent points from a 1 LSB ideal spacing.
Both may be expressed as either a percentge of full-scale
output or as fractional LSBs or both. The following figures
define the manner in which these parameters are specified.
The left figure shows a portion of the transfer curve of a DAC
with 1/2 LSB INL and the (implied) DNL spec of 1 LSB. Below
this is a graphic representation of the way this would appear
on a CRT. for example. if the DI A Converter output were to be
applied to the Y input of a CRT as shown in the application
schematic titled "CRT Display Driver". On the right is a portion of the transfer curve of a DAC specified for 2 LSB INL
with 1/2 LSB DNL specified and the graphic display below it.
One of the characteristics of an R-2R DAC in standard form is
that any transition which causes a zero LSB change (i.e. the
same output for two different codes) will exhibit the same
output each time that transition occurs. The same holds true
for transitions causing a 2 LSB change. These two problem
transitions are allowable for the standard definition of monotonicity and also allow the device to be specified very tightly
for INL. The major problem arising from this error type is in
AID converter implementations. Inputs producing the same
output are now represented by ambiguous output codes for
an identical input. Also. 2 LSB gaps can cause large errors at
those input levels (assuming 1/2 LSB quantizing levels). It
can be seen from the two figures that the DNL specified DI A
converter will yield much finer grained data than the INL
specified part. thus improving the ability of the AID to resolve
changes in the analog input.
DIFFERENTIAL LINEARITY COMPARISON
D/A CONVERTER WITH
DIA CONVERTER WITH
±2 LSB INL, ±1/2 LSB DNL
±1/2 LSB INL, ±1 LSB DNL
c IDEAL OUTPUTS
• ACTUAL OUTPUTS
c IDEAL OUTPUTS
• ACTUAL OUTPUTS
SEGMENT OF l2-BIT DAe
TRANSFER CURVE FOR
I
INL = ±2lse
DNL = ±1I2 LSB
0000 0010 0100 0110 1000
0001
0011 0101
0111
1010
1001
1100 "10
1011
1101
0010 0100 0110 1000 1010
1111
0011
0101 0111 1001
1'00 1110
1011 1101
0000
1111
0001
DIGITAL INPUTS
DIGITAL INPUTS
VIDEO DEFLECTION BY DAC's
VIDEO DEFLECTION BY DAC's
-ENLARGED "POSITIONAL" OUTPUTS
ENLARGED "POSITIONAL" OUTPUTS
11-101
1/86, Rev. A
----------I~ DAC-312 12-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
DESCRIPTION OF OPERATION
The OAC-312 is divided into two major sections, an 8segment generator and a 9-bit master/slave O/A Converter.
In operation the device performs as follows (See Simplified
Schematic):
EXPANDED TRANSFER CHARACTERISTIC
SEGMENT (001 010011)
The three most significant bits (MSB's) are inputs to a 3-to-8
line decoder. The selected resistor (R5 in the figure) is connected to the master/slave 9-bit O/A Converter. All lower
order resistors (R1 through R4) are summed into the 10 line,
while all higher order resistors (RS through R8) are summed
into the TO line. The R5 current supplies 512 steps of current
(0 to 0.499mA for a 1mA reference current) which are also
summed into the 10 or TOlines depending on the bits selected.
In the figure, the code selected is: 100 110000000. Therefore,
2mA (4 X 0.5mA/segment) +0.375mA (from master/slave 0/A
Converter) are summed into 10 giving an 10 of 2.375mA. TO
has a current of 1.S25mA with this code. As the three MSB's
are incremented, each successively higher code adds 0.5mA
to 10 and subtracts 0.5mA from iQ, with the selected resistor
feeding its current to the master/slave 01 A Converter; thus
each increment of the 3 MSB's allows the current In the 9-bit
O/A Converter to be added to a pedestal consisting of the
sum of all lower order currents from the segment generator.
This configuration guarantees monotonicity.
1501
1600
1499
1001
0.99
END SEGMENT (001)
t(01000000~)-;010 111111111,J
tlo"OOOOooooo)
DIGITAL INPUT
SIMPLIFIED SCHEMATIC
V(+)
B2
.3
84
B5
86
87
98
B9
Bl0
Bl1
19
18
17
COMP
V(-)
11-102
'0
1/86, Rev. A
----------l~ DAC·312 12·BIT HIGH· SPEED MULTIPLYING DIA CONVERTER
12-BIT FAST AID CONVERTER
12-81T FAST AID CONVERTER
SERIAL
DATA OUT
CONVERSION TIME vs ACCURACY
125
CLOCK
\
\
LSB
100
(WORST CASE)\
OAe-3l2
CMP-05
!>-
075
:>
050
~
u
f---
~
REF-Ol
025
OAe-3l2
0.00
100
COMP
1\
DAC-~
CMP-05
{TVP}
200
300
\
'"
400
1\
500
600
700
800
CONVERSION TIME PER TRIAL (nS)
10000kS1
CONVERSION
TIME (ns)
NOTE
DEVICE(S) CONNECTED TO ANALOG INPUT MUST BE CAPABLE OF SOURCING 40mA
A BUFFER (eg aUF·03) MAY BE REQUIRED
TYP
WORST
CASE
SAR
33
55
CMP-05
92
125
TOTAL
375ns
680ns
X 13
4
9~s
8
8~s
II
11·103
1/86, Rev. A
DAC-888
BYTEDAC® 8-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE"
MULTIPLYING D/A CONVERTER
PreCISIOIl MUIlolithics Inc
FEATURES
•
•
•
•
•
•
•
•
•
latches may also be operated in a transparent mode by
holding both control pins low. Additionally, the DAC-888 has
a data hold time requirement of zero nanoseconds.
8-Blt Level TrIggered Latch
8-Blt p.P Compatible
Easily Interfaced to All 8-Blt Processors
nL Logic Compatible
~ and WR Inputs
High Output Impedance and Compliance
Proven DAC-08 Analog Flexibility and Reliability
Nonlinearity to ±O.1% Max
Low Power Dissipation ••.••.••••.•••••••••• 134mW
The Analog section consists of a "Field-Proven" DAC-08 01 A
Converter. Monotonic multiplying performance is attained
over a wide 20 to 1 reference current range. Matching to
within 1 LSB between reference and full-scale currents
eliminates full-scale adjustment in most applications.
DAC-888 applications include graphic display drivers, highspeed modems, AID converters, programmable waveform
generators and power supplies, analog meter drivers, audio
encoders and programmable attenuators; and other applications where low cost, high speed and buffered flexibility are
required.
ORDERING INFORMATIONt
l8-PIN HERMETIC DUAL-IN-LiNE PACKAGE
NL
'laFS
MILITARY
TEMP.
INDUSTRIAL
TEMP.
0.1
0.19
DAC888AX'
DAC888BX'
DAC888EX
DAC888FX
PIN CONNECTIONS
• For devices processed In total compliance to M I L-STO-883, add 1883 after
part number. Consult factory for 883 data sheet.
t All commercial and industrial temperature range parts are available with
burn-In For ordering Information see 1986 Data Book, Section 2
18-PIN HERMETIC
DUAL-IN-LiNE
PACKAGE
(X-Suffix)
GENERAL DESCRIPTION
The BYTEDAC@> DAC-888 is a buffered 8-bit digital-toanalog converter designed specifically for 8-bit bus oriented
systems. The data inputs are connected to level-triggered
latches. Two active-low control pins are provided for ease of
interface to virtually all available microprocessors. The
DB,
7
LSB DBO
8
FUNCTIONAL DIAGRAM
D~ DBs DBs 084 DB3
DB2 DB, DBO
MSS
LSB
....._ _ _ _ _+'4'---0 'OUT
8-BIT MULTIPLYING OAC
COMP
v-
GND
v+
Manufactured under one or more of the following patents 4,055,773,4,056,740,4,092,639
11-104
1/86, Rev. A
~ DAC-88a BYTEDACIII a-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
DAC-888 AlB ........................ -Sso C to + 12So C
DAC-888 ElF .......................... -2SO C to +8So C
DICE Junction Temperature (T)l .....•• -6So C to +150°C
Storage Temperature •....•••....•.•.. -65° C to + lS00 C
Power Dissipation .....•..•..•.•..•.....•.••.•.. 300mW
Derate above 100° C •.•..•.••••••..•.••.••.... 10mW/o C
Lead Temperature (Soldering, 60 sec) ..•..••.••... 300° C
V+ Supply to V- Supply .......................... , 18.1V
Logic Inputs ................................ OV to S.SV
Analog Current Outputs .•...•.•.••.•..•.•.•••••• -SmA
Reference Inputs (V'O to V,,) ...•.•...•.••.•.••• V- to V+
Reference Input Differential Voltage
(V1QtoV,,) •..•.•••....•••..•.•....•..•.......•.. ±lSV
Reference Input Current ...•..••.•..•.•••....•..... SmA
NOTE: Abso)ute ratings apply to both DICE and packaged parts, unless
otherwise noted
ELECTRICAL CHARACTERISTICS at V+ = +SV, V-= -12V, IREF= 2mA, TA = -SsoC to +12SoC for DAC-888A/B,
otherwise noted. TA = 25° C to +8So C apply for DAC-888E/F. Output characteristics refer to both lOUT and tc:mT.
DAC-888A1E
PARAMETER
SYMBOL
CONDITIONS
MIN
TVP
unless
MIN
TYP
MAX
UNITS
Resolution
8
Bits
Monotonicity
8
Bits
±O.,
Nonlinearity
Full-Scale Tempco
Output Voltage
Compliance
Output Impedance
TCI FS
(See note)
Voe
Full-Scale Current
Change < , /2 LSB
-5
Full Range Current
IFR
Full Range
Symmetry
I FRS
IFA14 -I FR13
Zero-Scale Current
Izs
Output Current
Range
I FSR
Reference- Bias
Current
18
Power Supply
PSSI FR +
PSSI FR-
±50
+5
±'O
-5
>20
ROUT
VREF = 5.00V
Rl1 , R,o = 2.500kO
TA=25°C
Sensitivity
±'O
'.94
2,
I REF =3mA
V+ = 4.5V to 5.5V
V-= -'O.BV to -,3 2V
IAEF= 'mA
±0.'9
%FS
±80
ppm/oC
+5
V
>20
,.99
2.04
±,
±8
,94
2.04
mA
±,
±8
~A
0.2
2.9
2.9
2.'
MO
'.99
0.2
2
~A
mA
-,
-3
-,
-3
~A
±0.0003
±0.0002
±O.O,
±O.O,
±0.OOO3
±0.OO02
±O.O,
±O.O,
%ol.IFsI%ol.V+
%ol.IFsI%ol.V-
Power Supply
Current
1+
1-
IREF= 2mA
,2
6
'6
9
,2
6
,6
9
mA
Power Dissipation
Pd
IREF= 2mA
,34
,90
,34
,90
mW
Logie Input Levels
Logic Input "0"
Logie Input "'"
V,L
V,H
Logic Input Current
Logic Input "0"
Logic Input "'"
I,L
I'H
NOTE: Guaranteed by design.
0.8
O.B
2
V,N = 0.8V
V,N =50V
-2
0.'
11-105
-,0
-2
0.'
,
-,0
~
>-4
~
DAC-8888/F
MAX
rJ)
V
~A
1/86, Rev. A
~
0
U
C)
0
~
0
~
~......
C)
......
0
II
~
DAC-aaa BYTEDAC@ a-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
ELECTRICAL CHARACTERISTICS -
A.C. PARAMETERS Vs = +5V, -12V, IREF= 2mA, TA = 25°C.
DAC-888A1E
PARAMETER
MIN
TYP
MAX
300
400
DAC-888B/F
SYMBOL
CONDITIONS
MIN
Settling Time
ts
From CE & WR Negative Level
to ±1/2LSB, All Bits Switched
ON or OFF, (See note)
Reference Input
Slew Rate
dlldt
(See Note)
4
4
Data Input Setup Time
tDs
(See note)
150
150
ns
Data Input Hold Time
tDH
(See note)
10
10
ns
Chip Enable/Write Pulse Width
tENW
(See note)
250
250
ns
TYP
MAX
300
400
8
UNITS
ns
mA/p.s
NOTE: Guaranteed by design.
DAC-888 PIN DESCRIPTION
SYMBOL
DESCRIPTION
DBo - DB7
DATA BIT - Bits 0-7 are digital. active-high Inputs DB7 IS assigned as the MSB.
PINS 1-8
TI
CHIP ENABLE - An active low input control which IS the deVice enable Input terminal.
WR
WRITE CONTROL - An active low control which enables the microprocessor to write data to the DAC.
PIN 17
lOUT. lOUT
CURRENT OUTPUT - Complementary current outputs, which when added. equal IFs
PINS 13-14
VAEF +. VREF-
VOLTAGE REFERENCE -
PINS 10-11
COMP
COMPENSATION - The reference amplifier frequency compensating terminal
PIN 16
Differential inputs that accept a negative, positive, or bipolar Input and are used to set IFs.
PIN 12
FUNCTIONAL DIAGRAM AND TIMING DIAGRAM FOR 8-BIT OPERATION
.
TO 8-BIT DATA BUS
DATA
INPUT
'~
-----------~
VALID
~tDH
I
WR.CE---------~
O-:~~~--_f.;;;;;:_--=-_;;;;;:;\---~c.:IOUT
lOUT ----------n"7.n-.
'DUT--------~-~~~
seE
NOTE~
NOTE: If Input data changes after WR • TI low, lOUT/lOUT will change.
The last data Input before WR +CE high will be latched. It is suggested. but
not mandatory, that data be valid from WR • CE low to WR + CE high.
OPERATION TABLE
CE
I
o
o
WR OUTPUT
X
NO CHANGE
I
NO CHANGE
0
UPDATE LATCHES (TRANSPARENT)
11-106
1/86, Rev. A
~ DAC-888 BYTEDAC@ 8-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
DICE CHARACTERISTICS
1. DB7 (MSB)
2.DB6
3.DB5
4.DB4
5.DB3
6.DB2
7.DB1
8. DBO (LSB)
9. GROUND
10.
11.
12.
13.
14.
15.
16.
VREF (+)
VREF (-)
COMP
lOUT
lOUT
V-
WR
17. CE
18. V+
For additional DICE information refer to
1986 Data Book, Section 2.
DIE SIZE 0.139 x 0.126 Inch; 17, 514 sq. mils
(3.53 x 3.2mm.; 11.296 sq. mm.)
WAFER TEST LIMITS
at
Vs = +5, -12V,
IREF=
2mA,
TA =
25°C,
unless otherwise noted. Output characteristics refer to both
lOUT and lOUT.
PARAMETER
SYMBOL
DAC-888N
DAC-888G
LIMIT
LIMIT
UNITS
8
Bits MIN
±01
±019
%FSMAX
CONDITIONS
Resolution
Monotomclty
Bits MIN
Nonlinearity
Output Voltage
Compliance
Voe
Full-Scale Current
Change < 1/2 LSB
ROUT> 20MO Typ.
+5
-5
+5
-5
VMAX
VMIN
Full Range Current
IFA14
VREF = 5.00V
Rl1 , R10 = 2.500kO
TA = 25°C
204
194
204
1.94
mAMAX
mAMIN
IFR14-IFR13
±8
±8
I'AMAX
2
I'AMAX
Full Range Symmetry
I FRS
Zero-Scale Current
I zs
Output Current Range
I FSR
Reference 818S Current
18
Power Supply
PSSI FR +
PSSI FR -
V+ = 4.5V to 5 5V
V-=-4 5V to -12V, IREF= 1mA
Power Supply
Current
1+
1-
Power Dissipation
Pd
Logic Input Levels
Logic Input "0"
LogiC Input "1"
V,L
V,H
Sensitivity
LogiC Input Current
21
2.1
mAMIN
-3
-3
I'AMAX
±0.01
±001
±0.01
±0.01
%MFS/%Ll.V+ MAX
%MFS/%Ll.V- MAX
IREF = 2mA
16
9
16
9
mAMAX
IREF= 2mA
190
190
mWMAX
08
0.8
V MAX
VMIN
-10
-10
1
IREF= 3mA
V,N=O 8V
V,N =50V
I,L
I'H
I'AMAX
NOTE:
Electrical tests are performed at wafer probe to the limits shown Due to vanatlons In assembly methods and normal yield loss, Yield after packaging is not
guaranteed for standard product dice Consult factory to negotiate speCificatIOns based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS V+ = +5V, -12V,
IREF =
2mA,
TA =
25° C,
unless otherwise noted.
DAC-888
PARAMETER
SYMBOL
Reference Input Slew Rate
dl/dt
CONDITIONS
From CE Negative Edge to ± 1/2 LSB,
All bits Switched ON or OFF
TYPICAL
UNITS
8.0
mAil's
Settling Time
ts
300
ns
Data Input Setup Time
t DS
100
ns
Data Input Hold Time
tDH
0
ns
Chip Enable
Write Pulse Width
tENW
200
ns
11-107
1/86, Rev. A
I
~
DAC-8aa BYTEDAC* a-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
DIGITAL INFORMATION
The BYTEDAC® DAC-888 is a monolithic microprocessor
compatible DI A converter consisting of an 8-bit level
triggered latch, control circuitry and one 8-bit multiplying
D/A converter housed in an 18-pin dual in line package (DIP).
The DAC-888 accepts 8-bit binary bytes at the data inputs.
Data access is accomplished when WR and CE are low.
During the low state of CE and WR, the latches are transparent, therefore, data should be valid from 100ns prior to WR
and"CE low until"CE or WR high. When"CE or WR goes high,
the data stored in the latches will hold the selected output
indefinitely.
ANALOG INFORMATION
BASIC POSITIVE REFERENCE OPERATION
MSB
LSB
DB7 DBe DBS 084 DB3 DBZ DBl 080
17
Rla 10
VREF+
lOUT
lOUT
IREF_
BASIC NEGATIVE REFERENCE OPERATION
,,-
RREF
REF
In positive reference applications, an external positive reference voltage current flows through R'0 into the VREF(+) terminal of the reference amplifier. Alternatively, a negative
reference may be applied to VREF(-); reference current flows
from ground through R,o into VREF(+) as in the positive reference case. This negative reference connection has the
advantage of a very high impedance presented at pin 11. The
voltage at pin 10 is equal to and tracks the voltage at pin 11
due to the high gain of the internal reference amplifier. Rll
(nominally equal to R,o) is used to cancel bias current errors;
R" may be eliminated with only a minor increase in error.
For most applications the tight relationship between IREFand
IFR will eliminate the need for trimming IREF. If required,
full-scale trimming may be accomplished by adjusting the
value of R,oor by using a potentiometer for R,o. An improved
method of full-scale trimming which eliminates potentio-
,.
+6.000V
or may vary from nearly 0 to +4.0mA. The full range output
currrent is a linear function of the reference current and is
given by:
MSB
LSB
DB7 DBS DB5 DB4 DBa Daz DB1 DBa
OAe
~'~'~--~~~~~~~[-~V_~~G~N~D~'~~~~T~-----r'~3 lOUT
R11
12
15
•.00.F
.,'~
-=
18
.'Yi
FOR FixeD REFERENCE, TTL OPERATION TYPICAL
VALUES ARE'
'FR "" +:RRee: x ~
RREF = 2.5000k
R1' = RREF
FOR ALL LOGIC STATES
14
lOUT + loUr ... IFR
REFERENCE AMPLIFIER SET-UP
lOUT
IFR=~)(.2.§§.
RREF
256
NOTE, RREF seTS IFS. R11 IS FOR BIAS CURRENT CANCELLATION
AND IS EQUAL TO RREF
The DAC-888 is a multiplying D/A converter in which the
output current is the product of a digital number and the
input reference current. The reference current may be fixed
BASIC UNIPOLAR NEGATIVE OPERATION
MSB
LSB
DB7 DBS OBS DB4 DBa Daz DB1 DBa
DB7 DBB DB5 DB4 DB3 DB2 DB, DBO lomA lemA
Eour
'REF =
2.000mA
11
HALF-SCALE + 1 LSB
HALF-SCALE
HALF-SCALE -1 LSB
Eo
'.008 0.984 -2520 -2.460
1000 0.992 -2.500 -2460
0.992 1.000 -2460 -2 SOO
1
ZERO-SCALE +1 LSB 0
ZERO-SCALE
11-108
Eo
1992 0.000 -4.980 0.000
,984 0008 -4.960 -0.020
FULL·SCALE
FULL-SCALE -, LSB
1
0
0008 , 984 -0.020 -4960
0000 1992 -0.000 -4.980
1/86, Rev. A
-m
DAC-881 BYTEDACII I-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING DlA CONVERTER
RECOMMENDED FULL-SCALE ADJUSTMENT CIRCUIT
TABLE 1. REFERENCE AMPLIFIER COMPENSATION
REF. INPUT RESISTANCE
SUGGESTED Cc
1kn
2.Skn
Skn
1SpF
37pF
7SpF
Msa
LS8
DB7 DBa DBs DB4 DB3 DBZ OS, DBO
NOTE: A 0.Q1 p.F capacitor Is suggested for fixed references.
17
For fastest response to a pulse, low values of R10, enabling
small Cc values, should be used. If pin 10 Is driven by a high
current source, none of the above values will suffice and the
amplifier must be heavily compensated which will decrease
overall bandwidth and slew rate. For R10 = 1kn and Cc =
1SpF, the reference amplifier slews at 4mA/"s, enabling a
transition from IREF = 0 to IREF = 2mA in SOOns (see Figure,
pulsed reference operation).
18
RIO
LOW T,C.
IREF+ - z.nm:!A_~4.5~lcl!!!0~_....f,;;;;,:;--.....,I;=---;;;~.-_~~14!....o
+6.000v 0
"EF
Bipolar references may be accommodated by offsetting VREF
or pin 11, as shown in Figure below. The negative commonmode range of the reference amplifier is given by VCM = Vplus (lREF X 1kn) plus 2.SV. The positive common-mode
range is V+ less 1.SV.
meter TC effects is shown in the Recommended Full Scale
Adjustment Circuit.
Using lower values of reference current reduces negative
powersupply current and increases reference amplifier negative common mode range. The recommended range for
operation with a DC reference current is +0.2mA to +4.0mA.
The reference amplifier must be compensated by using a
capacitor from pin 12 to V-. For fixed reference operation a
O.01"F capacitor is recommended. For variable reference
applications, see "Reference Amplifier Compensation for
Multiplying Applications" section.
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
AC reference applications will require the reference amplifier to be compensated using a capacitor from pin 12 to V-.
The value of this capacitor depends on the impedance presented to pin 10 (see Table 1).
When a DC reference is used, a reference bypass capacitor is
recommended. A S.OV TTL Logic supply is not recommended as a reference. If a regulated power supply is used as
a reference, R10 should be split into two resistors with the
junction bypassed to ground with a 0.1"F capacitor.
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided, where 10 + iQ = IFR. Current appears at the "true"
output when a "1" is applied to each logic input. As the binary
count increases, the sink current at pin 14 increases proportionally in the fashion of a "positive logic" D/A converter.
When a "0" is applied to any input bit, that current is turned
off at pin 14 and turned on at pin 13. A decreasing logic count
increases iO as in a negative or inverted logic D/A converter.
Both outputs may be used simultaneously. If one of the
outputs is not required it must still be connected to ground or
to a pOint capable of sourcing IFS; do not leave an unused
output pin open.
ACCOMMODATING BIPOLAR REFERENCES
MSa
LSB
Msa
DB7 DBa DII6 DB4 DB3 DB. DBI DOo
LSB
DB7 DBe DBS D84 DB3 DB2 DBl DBa
DAC
VIN
-
HIGH INPUT
IMPEDANCE
RREF - R11
+VREF MUST BE ABOVE PEAK POSITIVE SWING OF VIN
IREF ;;.. NEGATIVE SWING OF liN
11-109
---- ----------
LV- ,,;;;~R~'~'
~'~'I_~~O~R~~=::,-4V:;;;_......!G::N!2D_rn;n:~~+::IUT~_-+'::..3()
(OPTIONAL)
1/86, Rev. A
I
~
DAC-888 BYTEDAC~ 8-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING DlA CONVERTER
8080 INTERFACE
B1
B2 _ _ _ _ _"
ADDRE~
8228
><::::
___________________________________
8080
.p
><::::
DATA ___________________________________
~"'~
v- v+
ADDRESS
8US
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___J~
::~: ::::::::::,~,:::::::::::::::::::::::::::
ADDRESS
DECODER
6800,6801,6809 INTERFACE
B2
ADDRESS
RJW
"XX
.p
VMA
RIW
DATA
ADDRESS
8US
e!!
B2
lOUT
VMA
lOUT
/
'/"
'"
~
'--../
X
8085 INTERFACE
elK
"'~____________....J/
DATA _ _ _ _ _ _ _ _...JX~
808•
•p
_______________>C
"DtMEM .../
MAPP~g {
ADDRESS
BUS
I/O/~
ADDRESS
CE
'-
....Jr
~,,____________________________________
'DUT ______________________~ ~-----------------'OUT
)c~___________________
DECODER
11-110
1/86, Rev. A
~
DAC·881 BYTEDACfI> I·BIT HIGH·SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING DlA CONVERTER
PULSED REFERENCE OPERATION
Msa
LSB
DB7 DB6 DBS 084 DB3 DB2 DBl DBo
+VREF
<;>
I
16
OPTIONAL RESISTOR ~
FOR OFFSET INPUTS
~
1"
ov.rL
RIN
I
*
TYPICAL VALUES
RIN =5k
10
Rp
+VIN·1OV
NO CAP
·UNBALANCED INPUTS WILL CAUSE SLIGHT DEGRADATION OF
'FS ACCURACY DUE TO lOS OF REFERENCE AMPLIFIER
POSITIVE LOW IMPEDANCE OUTPUT OPERATION
MS8
LSB
DB7 CBs CBs D84 DB3 DB2 DB1 DBO
17
,.
10
RL
VREF+
lOUT
>--'--<> Eour
OAe
11
VREFCOMP
v-
lOUT
GNO
v+
o TO
+IFS x RL
II
'FR":: 'REF
FOR COMPLEMENTARY OUTPUT (OPERATION AS NEGATIVE LOGIC DAel.
CONNECT INVERTING INPUT OF OP AMP TO lOUT CONNECT lOUT TO
GROUND
NEGATIVE LOW IMPEDANCE OUTPUT OPERATION
Msa
LSB
DB7 CBs DB5 084 DB3 CB2 DB1 DBo
17
16
>-""--0 EOUT
10
o TO
RL
11
-IFS
x RL
IFR"~IREF
FOR COMPLEMENTARY OUTPUT (OPERATION AS NEGATIVE
LOGIC OAC,) CONNECT NQNINVERTING INPUT OF OP AMP
TO lOUT CONNECT lOUT TO GROUND
11·111
1/86, Rev. A
-WD
DAC-888 BYTEDAce 8-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING DlA CONVERTER
BASIC BIPOLAR OUTPUT OPERATION
Mse
LSB
DB7 DBs DB& 084 DB3 082 OB1 DBo
+6,ODOV
17
,.
6.DOOIen
IREF+=
2.00DmA
5.000kn
o-..2.!!10t-_-1rv;;;;;:---=-;;;;;~__-I~14~E~O:!!:UT!..J
13
11
DB7
POSITIVE FULL-SCALE
POSITIVE FULL-SCALE -1 Lse
ZERO-SCALE+1Lse
ZERO-SCALE
ZERO-SCALE -1 Lse
1
1
0
NEGATIVE FULL-SCALE +1 Lse
NEGATIVE FULL-SCALE
0
0
EOUT
DB8
DB5
DB4
DB3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DB2
DB1
DBa
Eo
Eo
1
-4.960
-4.920
5.000
4.960
-0.040
0.000
0.040
0.080
0.040
0.000
4.900
5.000
-4.920
-4.980
0
1
0
1
1
0
OFFSET BINARY OPERATION
MSS
LSB
DB7 DBS DBS DB4 DBa DB2 DBl DBo
+600av
+16V
+5V
+5V~6L-~~~_ _-r-~:--~~~~\-
VOUT
__~~-l_-t
>--4--() EOUT
REF-02
25k1l
12
15
o.01pF
-12V
DB7
-16V
18
+5V
DBI
DBS
DB4
DB3
DB2
DB1
POSITIVE FULL-SCALE
POSITIVE FULL-SCALE -1 LSe
ZERO-SCALE
NEGATIVE ZERO-SCALE +1LSe
NEGATIVE FULL-SCALE
0
0
DBD
Eo
1
0
4.980
4.920
0
0
0
0
0
0
0
0.000
0
0
0
0
0
0
0
0
0
0
0
0
1
0
-4.960
-5.000
11-112
1/86, Rev. A
~
DAC-8aa BYTEDAce a-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING DlA CONVERTER
BASIC BIPOLAR OUTPUT OPERATION
Both outputs have an extremely wide voltage compliance,
enabling fast direct current-to-voltage conversion through a
resistor tied to ground or other voltage source. Positive
compliance is 18V above V- and is independent of the
positive supply. Negative compliance is given by V- plus
(IREF X 1kO) plus 2.5V.
supplies is possible. However, at least 8V must be applied to
insure turn-on of the internal bias network.
Symmetrical supplies are not required, as the DAC-888 is
quite insensitive to variations in supply voltage.
Power consumption may be calculated as follows:
P d = (1+) (V+) + (1-) (V-).
POWER SUPPLIES
TEMPERATURE PERFORMANCE
The DAC-888 operates over a wide range of power supply
voltages from a total supply of 9V to 15V. When operating at
supplies of ±5V or less, IREF::; 1mA is recommended. Low
reference current operation decreases power consumption
and increases negative compliance, reference amplifier negative common-mode range, negative logic input range, and
negative logic threshold range; consult the various figures
for guidance. For example, operation at -4.5V with IREF =
2mA is not recommended because negative output compliance would be reduced to near zero. Operation from lower
The nonlinearity and monotonicity specifications of the
DAC-888 are guaranteed to apply over the entire rated
operating temperature range. Full-scale output current drift
is tight, typically ± 10ppm/o C, with zero scale output current
and drift essentially negligible compared to 1/2 LSB.
The temperature coefficient of the reference resistor R10
should match and track that of the output resistor for
minimum overall full-scale drift. Settling times of the DAC888 decrease approximately 10% at -55 0 C; at +1250 C an
increase of about 15% is typical.
Z-80 INTERFACE
IREF
;,;;m:;~
zso
••
/
/
\
WI;
iVii
X
DATA==::><
CE---.....
ADDRESS
BUS
,I
lOUT
;,;;m:;
I
X
lOUT
6502 INTERFACE
02
ADDRESS
IREF
RiW
6602
••
RM
DATA
CE
ADDRESS
BUS
02
lOUT
ADDRESS
rouT
DECODER
11-113
/
\
x::::::::x
'--./
><
1/86, Rev. A
~
DAC-88a BYTEDACII> a-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING DlA CONVERTER
8048 INTERFACE
DATA BUS
.p
ALE~
BUS
FLOATING
,~-----------------X
ADDRESS
X
FLOATING
X
DATA
>(E:NG
'OUT
'OUT
\
CE
\
\VA
''OUT--------------~x:x~O~O~------------------OUT _______ I I
NOTE
OAe OUTPUT MAY CHANGE
UNTIL DATA VALID
'SOFTWARE SAR' AID CONVERTER (WITH 8048 MICROPROCESSOR)
07 06 05 04 03 02 01 DO
ViR
CEW
+15V
WRITE
STROBE
+15V
1
2
3
4
5
6
7
8 16
>=--+--OVOUT
DAC-888
REF-02
001pF
-16V
'9k"
-12V
+5V
10k"
-L.
ANALOG
-:.- GROUND
DIGITAL
VI GROUND
+15V
11-114
1/86, Rev. A
--ffHD
DAC-8aa BYTEDACI!> a-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION PROGRAM
LISTING USING DAC-888 AND SYM 1 PCB WITH 6502~P WITH FLOW CHART
LOCATION
DATA
MNEMONIC
COMMENTS
500
502
504
506
508
A900
A208
9500
A980
A8
LOA #00
LOX #08
STA ,X
LOA #80
TAY
Clear
Set Index Register
Clear Memory at 08 H
Tnal Bit
TOY
LOAD INDEX WITH 8
CLEAR LOCATION 8 IN RAM
LOAD A WITH 8016
TRANSFER (Al TO Y
509
50C
50F
511
513
800010
AD 00 1C
2901
FO 01
98
STA 1000 (Cont.)
LOA 1COO
AND A, #01
BEQ'+1
TYA
Output
Read Compo
Mask It
Branch if CMP ~ 0
Get Tnal Bit
514
515
18
7500
CLC
ADC,X
517
519
51A
9500
98
4A
STA ,X
TYA
LSR
Clear Carry
Result Summed With
PrevIous Test
Save it
Get Tnal Value
Next Bit
51B
51C
51E
520
A8
1500
90 E9
4C 00 05
TAY
ORA,X
BCC '-23
JMP 500
Save it
Next Data
Continue For 8 Trials
Do Over
OUTPUT (Al TO DAG 888
READ COMPARATOR OUTPUT
MASKITWITH0116
ADD (Al TO TRIAL VALUE (LOC 6)
SAVE IT IN LOC 8
SHIFT TRIAL BIT RIGHT TO CARRY
NOTE: 32 Bytes 2601'S
CARRY
~
1
BURN-IN CIRCUIT
II
,.
17
16
15
+5V
DAC-888
"
13
-12V
o ' .. F, 50V
12
11
10
10kn
11-115
1/86, Rev. A
])JlC:-1508Jl/1408Jl
8-BIT MULTIPLYING
D/A CONVERTERS
Precision MOIlolithics Inc.
FEATURES
•
•
•
•
•
•
•
•
The R-2R ladder divides the reference current into eight
binarily-related components which are fed to the switches. A
remainder current equal to the least significant bit is always
shunted to ground, therefore the maximum output current is
255/256 of the reference amplifier input current. For example,
a full-scale output current of 1.992mA would result from a
reference input current of 2.0mA,
Improved Direct Replacement for MC1S0S/MC140S
0.19% Nonlinearity Maximum Over Temperature Range
Improved Settling Time ................... 2S0ns, Typ
Improved Power Consumption ........... 1S7mW, Typ
Compatible with TTL, CMOS Logic
Standard Supply Voltages +S.OV and -S.OV to -1SV
Output Voltage Swing ................. +O.SV to -S.OV
High-Speed Multiplying Input ............... 4.0mA/l's
The DAC-150SA/140SA is useful in a wide variety of applications, including waveform synthesizers, digitally programmable gain and attenuation blocks, CRT character generation, audio digitizing and decoding, stepping motor drives,
programmable power supplies and in building tracking and
successive approximation analog-to-digital converters.
ORDERING INFORMATIONt
IS· PIN DUAL·IN-LINE PACKAGE
RELATIVE
ACCURACY
'10 FS
±O,19'1o
±O,39'1o
±O,78'1o
HERMETIC
MILITARY
DAC1508A-80'
For significantly improved speed and applications flexibility
your attention is directed to the DAC-OS S-bit high-speed
multiplying D/A converter data sheet. For D/A converters,
which include precision voltage references on the chip,
please refer to the DAC-210 or the DAC-100 data sheet.
PLASTIC
COMMERCIAL
COMMERCIAL
DAC1408A-80
DAC1408A·70
DAC1408A-60
DAC1408A-8P
DAC1408A-7P
DAC1408A-6P
• For devices processed in total compliance to MIL-STD-883, add 1883 alter
part number Consult factory for 883 data sheet.
tAil commerCial and industrial temperature range parts are available with
burn-in For ordering Information see 1986 Data Book, Section 2.
PIN CONNECTIONS
GENERAL DESCRIPTION
The DAC-150SA/140SA are S-bit monolithic multiplying
digital-to-analog converters consisting of a reference current amplifier, R-2R ladder, and eight high-speed current
switches. For many applications, only a reference resistor
and reference voltage need be added. Improvements in
design and processing techniques provide faster settling
times combined with lower power consumption while retaining direct interchangeability with MC150S/140S devices.
16-PIN DUAL-IN-LINE
PACKAGE
HERMETIC (0)
EPOXY (P)
SIMPLIFIED SCHEMATIC
Msa
A1
A2
A3
A4
AS
A6
A7
lSB
AS
GND
VRE ,(+1
,.
0-+-_------,
VAEF(-lo-'5+---I
COMPEN
11-116
1/86, Rev. A
_ _ _ _ _ _ _ _ _---IIfMDDAC-150lAl140lA I-BIT MULTIPLYING DlA CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage
VCC ••••••••••••••••••••••••••••••••••••••••• +5.5Vdc
VEE •••••••••••••••••••••••••••••••••••••••• -16.5Vdc
Digital Input Voltage, V5 through V I 2 •••••••••• +5.5,OVdc
Applied Output Voltage ••••••••••••••••••• +0.5, -5.2Vdc
Reference Current, 114 ••••••••••••••••••••••••••••• 5mA
Power Dissipation (Package limitation), Pd
Ceramic Package (or Epoxy B Package) ••••••• l00mW
Derate above TA = +25°C •••••••••••••••••• 6.7mW/oC
ELECTRICAL CHARACTERISTICS
=
Derate above T A = + 100° C for
Epoxy B Package .......................... 5.3mW/oC
Operating Temperature Range, TA
DAC-150SA •••••••••••••••••••••••• -55°C to +125°C
DAC-140SA •••••••••••••••••••••••••••• O°C to +75°C
DICE Junction Temperature (TJ) ••••••••• -65° C to 150° C
Storage Temperature Range, T stg •••••• -65°C to + 150° C
Plastic Package Only ••••••••••••••• -65° C to + 125° C
NOTE: Ratings apply to both DICE and packaged parts. unless otherwlsa
noted.
=
=
at VCC
+5Vdc, VEE
-15Vdc, VREFlR14
2mA, -55°C S TA S +125°C for
DAC-150SA-S, 0° C S TA S + 75° C for DAC-140SA, unless otherwise noted. All digital inputs at logic high level.
PARAMETER
Relative Accuracy (error relative to
Full·Scale 10 )
DAC·1508A·B, DAC·I408A-8
DAC·140BA·7
DAC·I40BA·6
SYMBOL
DAC-1508A11408A
MIN
TVP
MAX
CONDITIONS
UNITS
~
~
~
0
±0.19
±0.39
±0.7B
Er
Settling Time to within 112 LSB
(includes tPLH)
ts
TA = +25°C, (Note I)
TA = +25°C, (Note I)
Propagation Delay Time
tpLHI tPHL
Output Full·Scale Current Drill
TCl o
Digital Input Logic Levels (MSB)
High Level, Lagle "I"
Low Level, Logic "I"
V,H
V,L
Digital Input Current (MSB)
I'H
I'L
Relerence Input Bias Current (Pin 15)
1'5
250
30
U
%IFS
100
ns
ppm/oC
±20
0
0
ns
~
0
~
0.8
High Level, V,H = 5.0V
Low Level, V,L = 0.8V
0
-0.4
Vdc
0.04
-0.8
mA
-I
-3
pA
0
0
2.0
2.0
2.1
4.2
mA
1.9
1.99
2.1
mA
0
4
pA
+0.5
+0.5
Vdc
Output Current Range
lOR
VEE =-5V
VEE =-15V
Output Current
10
VREF = 2.000V, RI4 = 10000
Output Current
101m,n)
All bits low
Output Voltage Compliance
(E,S 0.19% at TA = +25°C)
Vo
IREF = ImA
VEE =-5V
VEE =-10V
Reference Current Slew Rate
SRI REF
4
Output Current Power Supply
Sensitivity
PSSl o_
0.5
2.7
"AN
Power Supply Current
Icc
lEE
All bits low
+9
-7.5
+14
-13
mA
Power Supply Voltage
VCCR
VEER
TA=+25°C
+5
-15
+5.5
-16.5
Vdc
Pd
All bits low
VEE =-5Vdc
VEE =-15VdC
All bits high
VEE =-5Vdc
VEE =-15Vdc
82
157
135
265
Power Di88ipation
V)
-0.6
-5
+4.5
-4.5
mAIl's
mW
70
132
NOTE:
I. Guaranteed by design.
11·117
1/86, Rev. A
~
0
......
0
II
------------11EM!> DAC-1508A11408A 8-BIT MULTIPLYING DlA CONVERTERS
DICE CHARACTERISTICS
1. N.C.
2. GROUND
3. VEE
4.10
5. A1 (MSB)
6. A2
7. A3
8. A4
9. AS
10. A6
11. A7
12. A8(LSB)
13. Vce
14. VREF(+)
15. VREF(-)
16. COMP
For additional DICE information refer to
1986 Data Book, Seclion 2.
DIE SIZE 0.085 X 0.082 Inch, 5270 sq. mils
(2.16 X 1.58 mm, 3.39 sq. mm)
WAFER TEST LIMITS at V+ = 5V, V- = 15V, IREF= 2mA,
TA =
25°C, unless otherwise noted.
DAC-1408A-G
PARAMETER
SYMBOL
CONDITIONS
Resolution
Monotoniclty
LIMIT
UNITS
8
Bits MIN
8
Bits MIN
±O 19
%FSMAX
+05
-06
-5
VMAX
VMIN
VMIN
2,±0.1
mAMAX
4
IJAMAX
2.1
4.2
mAMAX
Logic "0" Input Level
0.8
V MAX
Logic "I" Input Level
2
VMIN
Nonlinearity
Full-Scale Current Change, 'REF = lmA
<1/2 LSB V-=-5V
V-=-10V
Output Voltage Compliance
Full-Scale Current
Zero-Scale Current
Output Current Range
IzS
(All Bits Low)
lOR
V-=-5V
V-=-15V
Logic Input Current
Logic "0"
Logic "1"
Low Level, Vll = -0.8V
High Level, VIH = 5V
Reference Bias Current
Output Current Power Supply
SensitiVIty
Power Supply Current
(All Bits Low)
PSSlo1+
1-
Power Supply Voltage Range
Power DiSSipation
(All Bits Low)
V-=5V
V-=-15V
±10
±10
IJAMAX
-3
IJAMAX
2.7
IJAIVMAX
+14
-13
mAMAX
+5, ±0.5
-16.5,-4.5
V MAXIMIN
135
265
mWMAX
NOTE:
Electrical tests are performed at wafer probe to the lImIts shown. Due to varlallons In assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dIce Consult factory to negotIate specIfications based on dice lot qualificallon through sample lot assembly and testing
TYPICAL ELECTRICAL CHARACTERISTICS at V+ = +5V, V-= -15V, TA = 25° C, VLcand lOUT connected to ground, and
I REF = 2mA, unless otherwise noted. Output characteristics refer to lOUT only.
DAC-1408G
PARAMETER
SYMBOL
Reference Input Slew Rate
dlldt
CONDITIONS
Propagation Delay
Any BIt
Settling Time
To ± 1/2 LSB, All Bits Switched
ONorOFF
ts
11-118
TYPICAL
UNITS
4
mNIJS
30
ns
250
ns
1/86, Rev. A
------------1~ DAC-150aAl140aA a-BIT MULTIPLYING DlA CONVERTERS
APPLICATIONS
RELATIVE ACCURACY TEST CIRCUIT
MSB
A'
A2
12 BIT
D-TO A
A3
o TO +10V
CONVERTER
A'
(to 01%
OUTPUT
--0--
ERROR MAX)
AS
A6
A7
~
5k!l
LSB A"I'
Al1A12
50kI!
VREF
<;;.
2V
~
I~*
Vee
R"
950n
-
,.
MSB
S
1
1
ERR OR
(1V = 1%)
,r;?
'3
6
7
B
8·BIT
COUNTER
OAC 150SAI
OAC 1408A
,."
~
"
12
1kn
:!:'t
--
USE WITH NEGATIVE VREF
R14
R16
A'
Ol;:
R15
A'
A2
A4
II
-
Vee-
USE WITH POSITIVE V REF
R14~
A3
3 2
A2
15
R15
.....-o--JW-.
A3
VnEFH
"Lr
1-''''4-Q----"\MR_'4_____ VREF(+)
's
...r-L
R'S
A4
AS
AS
AS
AS
A7
A7
AS
AB
RL
SEE
TEXT
FOR
SEE
TEXT
FOR
VALUES
VALUES
OFe
OF e
1/86, Rev. A
11-119
~-------
~--~-
------
-----------IIEMD DAC-150aAl140aA a-BIT MULTIPLYING DlA CONVERTERS
TRANSIENT RESPONSE AND SETTLING
TIME TEST CIRCUIT
Vee
+20Vdc
13
The compensation capacitor value must be increased with
increases in R14 to maintain proper phase margin; for R14
values of 1.0, 2.5 and 5.0kO, minimum capacitor values are 15,
37, and 75pF. The capacitor may be tied to either VEE or
ground, but using VEE increases negative supply rejection.
,.
EIN
I Io.'"F
51
... 26pF
Cc
VEE
EO FOR SETTLING TIME MEASUREMENT
(ALL BITS SWITCHED LOW TO HIGH)
USE WITH CURRENT-TO-VOLTAGE CONVERTING OP AMP
Vee
VREF" 2.OVdc
=~4 =- 6~~~ ~
, Okn
r----,
'3
MSB
r.:':::.4<>---_ _ _-'\IVv_ _~-__ VREF
A'
,.
A2
A3
R'.
AS
A8
A7
Vo
VEE
THEORETICAL Va
VO'
Yffl
(Rol
[¥+¥+'V+~+~HI+~+~J
so
ADJUST VREF R15 OR RO
THAT Va WITH ALL DIGITAL
INPUTS AT HIGH LEVEL IS EQUAL TO 9 961 VOLTS
Va = 1k
2V (5k)
=
A negative reference voltage may be used if R14 is grounded
and the reference voltage is applied to R15 as shown. A high
input impedance is the main advantage of this method.
Compensation involves a capacitor to VEE on Pin 16, using
the values of the previous paragraph. The negative reference
voltage must be at least 4.0V above the VEE supply. Bipolar
input signals may be handled by connecting R14 to a positive
reference voltage equal to the peak positive input level at
Pin 15.
When a DC reference voltage is used, capacitive bypass to
ground is recommended as a reference voltage. If a well
regulated 5.0V supply, which drives logic is to be used as the
reference, R14 should be decoupled by connecting it to
+5.0V through another resistor and bypassing the junction of
the two resistors with 0.1 p.F to ground. For reference voltages
greater than 5.0V, a clamp diode is recommended between
Pin 14 and ground.
If Pin 14 is driven by a high impedance such as a transistor
current source, none of the above compensation methods
apply and the amplifier must be heavily compensated,
decreasing the overall bandwidth.
A4
A8
Pin 14 regardless of the setup method or reference voltage
polarity. Connections for a positive voltage are shown on the
preceding page. The reference voltage source supplies the
full current 114' For bipolar reference signals, as In the
multiplying mode, R15 can be tied to a negative voltage
corresponding to the minimum input level. It is possible to
eliminate R15 with only a small sacrifice in accuracy and
temperature drift.
'2 "4 i ii 32 i4 Us +256
['+'+'+'+'+'+'
'J
1OV[~J= 9961V
OUTPUT VOLTAGE RANGE
The voltage on Pi n 4 is restricted to a range of -0.6V to +0.5V
when VEE = -5V due to the current switching methods
employed in the DAC-150SA-S.
The negative output voltage compliance of the DAC-150SA-S
is extended to -5.0V where the negative supply voltage is
more negative than -10V. Using a full-scale current of
1.992mA and load resistor of 2.5kO between Pin 4 and ground
will yield a voltage output of 256 levels between 0 and
-4.9S0V. The value of the load resistor determines the
switching time due to increased voltage swing. Values of RL
up to 5000 do not significantly affect performance but a
2.5kO load increases "worst case" settling time to 1.2p.s
(when all bits are switched on). Refer to the subsequenttext
section of Settling Time for more details on output loading.
GENERAL INFORMATION AND APPLICATION NOTES
OUTPUT CURRENT RANGE
The output current maximum rating of 4.2mA may be used
only for negative supply voltages more negative than -7.0V,
due to the increased voltage drop across the resistors in the
reference current amplifier.
REFERENCE AMPLIFIER DRIVE AND COMPENSATION
The reference amplifier provides a voltage at Pin 14 for
converti ng the reference voltage to a cu rrent, and a turnaround circuit or current mirror for feeding the ladder. The
reference amplifier input current, 114, must always flow into
11-120
1/86, Rev. A
------------t~ DAC-150aAl140aA a·BIT MULTIPLYING D/A CONVERTERS
ACCURACY
Absolute accuracy is the measure of each output current
level with respect to its intended value, and is dependent
upon relative accuracy and full-scale current drift. Relative
accuracy is the measure of each output current level as a
fraction of the full-scale current. The relative accuracy of the
DAC-150SA-S is essentially constant with temperature due to
the excellent temperature tracking of the monolithic resistor
ladder. The reference current may drift with temperature,
causing a change in the absolute accuracy of output current.
However, the DAC-150SA-S has a very low full-scale current
drift with temperature.
The DAC-150SA-S/DAC-140SA series is guaranteed accurate
to within ± 1/2 LSB at a full-scale output current of 1.992mA.
This corresponds to a reference amplifier output current
drive to the ladder network of 2.0mA, with the loss of one LSB
(S.OJLA), which is the ladder remainder shunted to ground.
The input current to Pin 14 has a guaranteed value of between
1.9 and 2.1 mA, allowing some mismatch in the NPN current
source pair. Testing relative accuracy is accomplished by the
circuit labelled "Relative Accuracy Test Circuit". The 12-bit
converter is calibrated for a full-scale output current of
1.992mA. This is an optional step since the DAC-150SA-S
accuracy is essentially the same between 1.5 and 2.5mA.
Then the DAC-150SA-S circuit's full-scale current is trimmed
to the same value with R14 so that a zero value appears at the
error amplifier output. The counter is activated and the error
band may be displayed on an oscilloscope, detected by
comparators, or stored in a peak detector.
Two S-bit D/A converters may not be used to construct a
16-bit accuracy D/A converter. 16-bit accuracy implies a
total error of±1/2 of one part in 65, 536, or±0.00076% which
is much more accurate than the ±0.19% specification provided by the DAC-150SA-S.
MULTIPLYING ACCURACY
The DAC-150SA-S may be used in the multiplying mode with
eight-bit accuracy when the reference current is varied over a
range of 256:1. If the reference current in the multiplying
mode ranges from 16JLA to 4.0mA, the additional error
contributions are less than 1.6JLA. This is well within eight-bit
accuracy when referred to full scale.
A monotonic converter is one which supplies an increase in
current for each increment in the binary word. Typically, the
DAC-150SA-S is monotonic for all values of reference current
above 0.5mA. The recommended range for operation with a
DC reference current is 0.5 to 4.0mA.
SETTLING TIME
The "worst case" switching condition occurs when all bits are
switched "ON", which corresponds to a low-to-high transition for all bits. This time is typically 250ns for settling to
within ± 1/2 LSB, for S-bit accuracy, and 200ns to 1/2 LSB for
7 and 6-bit accuracy. The turn off is typically under 100ns.
These times apply when RL::; 500n and Co::; 25pF.
The slowest single switch is the least significant bit. In
applications where the D/A converter functions in a positivegoing ramp mode, the "worst case" switching condition does
not occur, and a settling time of less than 250ns may be
realized.
Extra care must be taken in board layout since this is usually
the dominant factor in satisfactory test results when measuring settling time. Short leads, 100ilF supply bypassing for low
frequencies, and a minimum scope lead length are all
mandatory.
11·121
II
1/86, Rev. A
DAC-8012
CMOS 12-BIT MULTIPLYING
D/A CONVERTER "WITH MEMORY"
Precision Monolithics Inc.
FEATURES
•
•
•
•
•
•
•
•
•
•
feature "memory" read-write operation. Data is loaded into the
latches by a single 12-bit wide word, and can be read back on
the same data lines. The DAC-8012 can be directly connected to
12-bit and 16-bit busses.
Data Readback Capability
12-81t Resolution and Linearity
Low Gain Tempco: 2ppm/o C
Fast TTL/CMOS Compatible Data Latches
3-State Outputs TTL/CMOS Compatible
Single +5V to +15V Supply
Small 2D-Pin 0.3" DIP
LowCost
Latch-Up Resistant
Ideal for Battery-Operated Equipment
The read back function makes the DAC-8012 particularly wellsuited for applications in automatic test equipment, industrial
automation, and other multi-channel microprocessor-controlled
systems that require keeping track of the current DAC output
data without using an extra memory location for each channel.
Low power dissipation and single-supply operation from +5Vto
+15V makes the DAC-8012 an excellent choice in low-power
and remote sytems and digital systems with a large number of
analog outputs. Four-quadrant multiplying capability and 12bit linearity allows the DAC-8012 to be used in low-noise, widebandwidth, low-distortion, digitally-controlled preCision attenuator and filter applications.
ORDERING INFORMATIONt
PACKAGE: 2o-PIN'
MAXIMUM
GAIN ERROR
RELATIVE
TA = +2S'C
Vee = +SV
ACCURACY
±1/2 LSB
±1 LSB
±1 LSB
±3 LSB
MILITARY"
TEMR
-SS'C to
+12S'C
INDUSTRIAL COMMERCIAL
TEMR
TEMR
-25'C 10
+8S'C
O'Cto
DAC-8012AR
DAC-8012BR
DAC-8012ER
DAC-8012FR
DAC-8012GP
DAC-8012HP
PIN CONNECTIONS
+70'C
• Package Designation'
Suffix R Hermetic DIP
Suffix P: Plastic DIP
Consult Factory for Dice Informatton
•• For deVices processed In total compliance to MIL-STD-883. add 1883 after
2D-PIN EPOXY DIP
(P-Sufflx)
2D-PIN HERMETIC DIP
(R-Sufflx)
part number Consult factory for 883 data sheet
t All
commercial and industrial temperature range parts are ava"able with
burn-In For ordering information see 1986 Data Book. Section 2.
GENERAL DESCRIPTION
The DAC-8012 is a monolithic 12-bit CMOS Multiplying DAC
with on-board data latches and three-state output buffers that
FUNCTIONAL DIAGRAM
?
J
I
RO'WA
"FB
12-81T
MULTIPLYING
DAC
...
r-
INPUT DATA
J
os
1
LATCHES
,..
'"
I I
~J
THREE-STATE
OUTPUT BUFFERS
~
I
~
.......
OkND
AGND
J
A
'i7
J
OUTl
)
/
D
11-122
DBll ....
DBQ
1/86, Rev. A1
----------I~ DAC-8012 CMOS 12-BIT MULTIPLYING D/A CONVERTER "WITH MEMORY"
ABSOLUTE MAXIMUM RATINGS
Storage Temperature .................... -65°C to +150°C
Lead Temperature (Soldering, 60 sec) .....•....... +300° C
(TA = 25°C, unless otherwise noted.)
VDD to DGND ................................ -0.3\1, +17V
Digital Input Voltage to DGND .................. -0.3V, VDD
AGND to DGND .............................. -0.3V, VDD
VRFB , VREF to DGND .................•............. ±25V
VPIN 1 to DGND ............................... -0.3V, VDD
Power Dissipation (Any Package) to +75° C ........ 450mW
Derates Above +75°C by ...................... 6mWfOC
Operating Temperature Range
Military (AR, BR) Grades ............... -55°C to +125°C
Industrial (ER, FR) Grades .............. -25°C to +85°C
Commercial (GP, HP) Grades .............. O°C to +70°C
Dice Junction Temperature. . . . . . . . . . . . . . . . . . . . . .. +150°C
CAUTION:
Stresses above those listed under"Absolute Maximum Ratings" may cause
permanent damage to the device This Isa stress rating only and functional
operation at or above this specification IS not Implied Exposure to above
maximum ratmg conditions for extended periods may affect deVice
reliability
Do not apply voltages higher than VDO or less than GND potential on any
terminal except VAEF .
The dlQltallnputs are zener protected, however, permanent damage may
occur on unprotected units from high-energy electrostatic fields Keep
units In conductive foam at all times until ready to use Use proper antistatic handling procedures
Remove power before inserting or removing units from their sockets
=+5Vor +15V, V REF =+10V, VOUT 1 =Ov, AGND =DGND =OV; TA =-55°C to +125°C
=-25°C to +85°C apply for DAC-8012ER/FR, TA =O°C to +70°C apply for DAC-8012GP/HP, unless
ELECTRICAL CHARACTERISTICS at VDD
apply for DAC-8012AR/BR, TA
otherwise noted.
DAC-8012A/E/G
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
DAC-8012B/F/H
MAX
MIN
TYP
MAX
UNITS
STATIC ACCURACY
12
Resolution
Relative
Accuracy
12
Bits
INL
TA = Full Temp Range
±1/2
±1
LSB
DNL
TA = Full Temp Range
±1
±1
LSB
G FSE
TA = +25°C
TA = Full Temp Range
±1
±2
±3
±4
LSB
±5
±5
ppmloC
0002
0004
0002
0004
%1%
10
10
200
25
200
25
300
300
Differential
Nonlinearity
(Note 1)
Gain Error
(Notes 2, 3)
Gain Temperature
CoeffiCient
.6.Galn/.6.Temperature
TCG FS
(Notes 4. 5)
DC Supply Relectlon
aGalnl avoo (Note 4)
Output Leakage
Current at OUT 1
PSR
T = +25°C
T: = Full Temp Range(IlNoo = ±5%)
TA = +25°C, RD/WR = DS = OV,
All digital inputs = OV
ILKG
nA
TA = Full Temp Range
AlB VerSions
ElF IG/H VerSions
DYNAMIC PERFORMANCE
Propagation Delay
(Notes 4, 6, & 7)
Current Settling Time
(Notes 4. 7)
Glitch Energy
(Note 4)
tpo
TA = +25°C
(OUT 1 Load = 1000. CEXT = 13pF)
.
TA = Full Temp Range
(To 1/2 LSB)
10UT1 Load = 1000
Q
TA = Full Temp Range
VREF =AGND
TA
AC Feedthrough
at IOUT1
FT
(Notes 4. 11)
ns
/lS
=+25°C
400
500
400
500
TA = Full Temp Range
VREF = ±10V. f = 10kHz
nVs
mvp_p
REFERENCE INPUT
Input ReSistance
(Pin 19 to GND)
(Note 12)
TA = Full Temp Range
RREF
11
Input ReSistance
11-123
- -
.--~~---
15
11
15
kO
1/86, Rev. A1
III
~ DAC-8012 CMOS 12-BIT MULTIPLYING D/A CONVERTER "WITH MEMORY"
ELECTRICAL CHARACTERISTICS at VDD=+5V, VREF= +10V, VOUTI = OV, AGND = DGND = OV; TA =-55·C to +125·C apply
for DAC-8012AR/BR, TA = -25·C to +85·C apply for DAC-8012ER/FR, TA = O·C to +70·C apply for DAC-8012GP/HP, unless
otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
DAC-8012A/E/G
MIN
TYP
MAX
DAC-8012B/F/H
MIN
TYP
MAX
70
ISO
70
ISO
UNITS
ANALOG OUTPUTS
Oulput CapaCItance
(Note 4)
C OUT1
COUT
Voo =+SV or +1SV
TA =Full Temp. Range
DBO-DBI I =OV, RDIWR =OS =OV
DBO-DBI I =Voo, RD/WR =OS =OV
pF
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
VINH
VINL
TA
=Full Temp. Range
Input Current
(NoteS)
liN
TA
TA
=+2S'C
Input Capacitance
DBO-DBll
RD/WR, OS
(Note 4)
CIN
TA
=Full Temp
Output High Voltage
VOH
10
=400p.A
Output Low Voltage
VOL
10
=-1
2.4
2.4
=Full Temp. Range
Range
O.S
O.S
10
10
12
12
6
6
V
p.A
pF
DIGITAL OUTPUTS
4.0
4.0
6mA
Three-State Output
Leakage Current
SWITCHING CHARACTERISTICS
(Note 9)
See Timing Diagram
Write to Data Strobe
Setup Time
twsu
TA
TA
=+2S'C
Data Strobe to
Write Hold Time
tWH
TA
Read to Data Strobe
Setup Time
t Asu
Data Strobe to
Read Hold Time
tAH
Write Mode Data Strobe
Width
tWAS
Read Mode Data Strobe
Width
tAOS
Data Setup Time
tosu
Data Hold Time
=Full Temp. Range
TA =+2S'C
V
0.4
0.4
V
10
10
p.A
ns
0
0
=Full Temp. Range
0
0
0
0
ns
TA
TA
=+2S'C
=Full Temp. Range
0
0
0
0
ns
TA
TA
=+2S'C
Range
0
0
0
0
ns
TA
=Full Temp. Range
180
2S0
ISO
2S0
ns
220
290
220
290
ns
210
2S0
210
2S0
ns
0
0
0
0
ns
=Full Temp
TA =+2S'C
=+2S'C
=Full Temp. Range
TA =+2S'C
TA
TA
TA
=Full Temp. Range
tOH
TA
TA
=+2S'C
=Full Temp
Range
Data Strobe to
Output Valid Time
(Note 13)
tco
TA
TA
=+2S'C
=Full Temp
Range
300
400
300
400
ns
Output Active Time
from Deselection
(Note 13)
toTO
TA
TA
=+2S'C
Range
21S
37S
21S
37S
ns
100
TA =Full Temp Range
(All Digital Input. VINL or VINH )
2
mA
100
TA =Full Temp Range
(All Digital Inputs OV or Voo )
100
p.A
=Full Temp
POWER SUPPLY
Supply Current
10
11-124
100
10
1/86, Rev. A1
IfMD
DAC-S012 CMOS 12-BIT MULTIPLYING D/A CONVERTER "WITH MEMORY"
ELECTRICAL CHARACTERISTICS at V DD =+15V, V REF =+10V, VOUT1 = OV, AGND =DGND =OV; TA =-55°C to +125°C apply for
DAC-S012AR/BR, TA =-25°C to +S5°C apply for DAC-S012ER/FR, TA =O°C to +70°C apply for DAC-S012GP/HP, unless otherwise
noted.
DAC-8012A/E/G
PARAMETER
SYMBOL
CONDITIONS
MIN
Inpul High Voltage
Input Low Voltage
V,NH
V,NL
TA
Input Current
(Note B)
liN
TA =+25°C
TA =Full Temp Range
Input Capacitance
DBO-DBII
RD/WR, OS
(Note 4)
C 'N
TA =Full Temp. Range
Output High Voltage
VOH
10
Output Low Voltage
VOL
10
TYP
DAC-8012B/F/H
MAX
MIN
TYP
MAX
UNITS
DIGITAL INPUTS
13.5
=Full Temp. Range
13.5
V
1.5
1.5
10
1
10
JJ.A
12
10
12
10
pF
rJ)
~
;;.Li
~
~
DIGITAL OUTPUTS
=3mA
=-3mA
135
13.5
Three-State Output
Leakage Current
SWITCHING CHARACTERISTICS
(Note 9)
See Timing Diagram
Write to Data Strobe
Setup Time
t wsu
TA
TA
Data Strobe to
Write Hold Time
tWH
Read to Data Strobe
Setup Time
tRSU
Data Strobe to
Read Hold Time
tRH
Write Mode Data Strobe
Width
tWAS
TA = +25°C
TA =Full Temp Range
Read Mode Data Strobe
Width
tADS
Data Setup Time
15
V
10
10
JJ.A
a
TA = +25°C
TA =Full Temp. Range
a
a
a
a
TA = +25 Q C
TA =Full Temp Range
a
0
=+25°C
=Full Temp
Range
V
1.5
~
0
f:"'
~....
ns
ns
100
120
100
120
ns
TA = +25°C
TA =Full Temp Range
110
150
110
150
ns
tosu
TA = +25°C
TA =Full Temp. Range
90
120
90
120
ns
Data Hold Time
tOH
TA = +25°C
TA =Full Temp Range
a
a
a
a
ns
Data Strobe to
Output Valid Time
(Note 13)
tco
TA =+25°C
TA =Full Temp Range
lBO
220
180
220
ns
Output Active Time
for Deselectlon
(Note 13)
tOTD
TA =+25°C
TA =Full Temp Range
180
250
180
250
ns
100
TA =Full Temp Range
(All Digital Inputs V,NL or V,NH )
100
TA =Full Temp Range
(All Digital Inputs OV or Voo )
=Full Temp. Range
0
ns
a
a
TA
U
C)
ns
a
a
a
TA = +25°C
0
....C)
0
POWER SUPPLY
Supply Current
mA
10
NOTES:
12~bit monotonic over full temperature range.
Includes the effects of 5ppm max gam T.C.
Using internal RFB DAC register loaded With 1111 1111 1111 Gam error
adjustable uSing the circUIts of Figures 4 and 5
4. GUARANTEED but NOT TESTED
5 Typical value IS 2ppm/o C for Voo = +5V.
6. From digital input change to 90% of final analog output
2.
3.
8
IS
9
10
11
12
11-125
-~.~-~-~--.
100
10
100
JJ.A
All dlgltalmputs =OV to Voo , or Voo to OV
Logic mputs are MOS gates, tYPical Input current (at +25°C) IS less than
InA
Sample tested at +25 0 C to ensure com pliance
Feedthrough can further be reduced by connecting the metal lid on the
sldebraze package (Suffix R) to DGND
Resistor T C =+100ppmfOC max
CL =100pf
1/86, Rev. A 1
--
-
.-
---------l~ DAC-B012 CMOS 12-BIT MULTIPLYING D/A CONVERTER "WITH MEMORY"
DICE CHARACTERISTICS
1. OUT 1
2. AGND
3.DGND
4. DB11 (MSB)
5. DB10
6.DB9
7.DBB
B.DB7
9.DB6
10. DB5
11.
12.
13.
14.
15.
16.
17.
1B.
19.
20.
DB4
DB3
DB2
DB1
DBO (lSB)
OS
RD/WR
Voo
VREF
RFB
For additional DICE information refer 10
19B6 Dala Book. Section 2.
DIE SIZE 0.121 X 0.112 inch. 13.552 sq. mils
(3.07 X 2.B5 mm. B.75 sq. mm)
WAFER TEST LIMITS at VD D = +5V or +15V. VREF = +1aV. VOUT 1 = av. AGND = DGND = av, TA = 25°C. unless otherwise noted.
DAC-8012G
PARAMETER
SYMBOL
CONDITIONS
Relative Accuracy
INL
Endpoint Linearity Error
LIMIT
UNITS
±1/2
LSB MAX
±1
LSB MAX
±3
LSB MAX
DAC Latches Loaded with 0000 0000 0000
Pad 1
±10
nAMAX
RREF
Pad 19
6/15
kil MINI
kilMAX
Output High Voltage
VOH
VDD
40
VMIN
Output Low Voltage
VOL
VDD
04
VMAX
24
135
VMIN
0.8
15
VMAX
±1
/lA MAX
Differential Nonlinearity
DNL
Gain Error
GFSE
DAC Latches Loaded with 1111 1111 1111
Output Leakage
'LKG
Input Resistance
Digital Input
High
V1NH
Digital Input
Low
Input Current
Supply Current
DC Supply Rejection
(~Galnl ~VDD)
V 1NL
'iN
=5V. 10 =400/lA
=5V, 10 =-1 6mA
VDD =5V
VDD =15V
VDD
VDD
Y'N
=5V
=15V
=OV or VDD
All Digital Inputs V1NL or V1NH
'DD
All Digital Inputs OV or VDD
PSRR
VDD
=±5%
01
0004
mAMAX
%1% MAX
NOTE:
Electrical tests are performed at wafer probe to the limits shown Due to vanatlons in assembly methods and normal Yield loss, Yield after packaging IS not
guaranteed for standard product dice Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing
TYPICAL ELECTRICAL CHARACTERISTICS at VDD =+5Vor+15V. VREF =+1aV. VOUT1 =av; TA =25°C. unless otherwise noted.
DAC-8012G
PARAMETER
SYMBOL
Digital I nput Capacitance
CIN
CONDITIONS
COUT1
DAC Latches Loaded with 0000 0000 0000
COUT1
DAC Latches Loaded with 1111 1111 1111
TYPICAL
UNITS
12
pF
70
pF
150
pF
300
ns
Output Capacitance
Propagation Delay
VDD = 15V
VDD = 5V
11-126
1/86, Rev. A 1
---------IIEM!>
DAC-B012 CMOS 12-BIT MULTIPLYING D/A CONVERTER "WITH MEMORY"
LOAD CIRCUITS FOR SWITCHING TESTS
LOGIC INFORMATION
-u
D/A CONVERTER SECTION
FOR DATA GOING HIGH
TO DATA BIT
Figure 1 shows a simplified circuit of the D/A Gonvertersection
of the DAG-8012, and Figure 2 gives an approximate equivalent
switch circuit. R is typically 11kO.
~'00PF~3kn
The binary-weighted currents are switched between OUT 1 and
AGND by N-channel switches, thus maintaining a constant
current in each ladder leg independent of the switch state.
FOR DATA GOING LOW
The capacitance at the OUT 1 terminal, GOUT " is code
dependent and varies from 70pF (all switches to AGND) to
150pF (all switches to OUT 1). One of the current switches is
shown in Figure 2.
T3kn
TO DATA BIT
--1.
The input resistance at VREF (Figure 1) is always equal to RLDR
(RLDR is the R/2R ladder characteristics resistance and is equal
to value "R"). Since the input resistance at the VREF pin is
constant, the reference terminal can be driven by a reference
voltage or a reference current, ac or dc, of positive or negative
polarity. (If a current source is used, a low-temperaturecoefficient external RFB is recommended to define scale factor.)
~100PF
PARAMETER DEFINITIONS
RELATIVE ACCURACY
Sometimes referred to as endpoint nonlinearity, and is a
measure of the maximum deviation from a straight line passing
through the endpoints of the DAG transfer function. Relative
Accuracy is measured after the zero and full-scale points have
been adjusted, and is normally expressed in LSB or as a
percentage of full scale.
The internal feedback resistor (R FS ) has a normally closed
switch in series as shown in Figure 1. This switch improves
performance over temperature and power supply rejection;
however, when the circuit is not powered up the switch assumes
an open state.
DIFFERENTIAL NONLINEARITY
This is the difference between the measured change and the
ideal change between any two adjacent codes. A differential
nonlinearity of ±1 LSB maximum over the full operating
temperature range will ensure that a device is monotonic (the
output will not decrease for an increase in digital code applied).
BURN-IN CIRCUIT
"0
C:~,
VREF Voo
C2
~---.... +
GAIN ERROR
Gain or full scale error is the amount of output error between
the ideal output and the actual output. The ideal output is VREF
minus 1 LSB. The gain error is adjustable to zero using external
resistance.
OUT1
R"
AGND
VREF
DGND
Voo
C4
20
19
R1
1kO
18
011 (MSB)
D10
OUTPUT CAPACITANCE
The capacitance from OUT1 to AGND.
Os
D.
!lSB) DO
D8
D1
D2
PROPAGATION DELAY
07
This is measured from the digital input change to the analog
output current reaching 90% of its final value.
06
03
os
D4
10
"
13
R2
5kO
12
11
FEEDTHROUGH GLITCH ENERGY
This is a measure of the amount of charge injected to the analog
output from the digital inputs, when the digital inputs change
states. It is the area of the glitch and is specified in nVsec; it is
measured with VREF = AGND.
11-127
1/86, Rev. A1
II
---------I1fMD
DAC-8012 CMOS 12-BIT MULTIPLYING D/A CONVERTER "WITH MEMORY"
TIMING DIAGRAM
NOTES.
Yoo
Voo
=+5Y; tr =IF =20ns
=+15V, t, ::: If '" 40ns
ALL INPUT SIGNAL RISE AND
FALL TIMES MEASURED FROM
10% TO 90% OF Voo'
TIMING MEASUREMENT REFERENCE LEVEL
IS
FIGURE 1: Simplified DIA Circuit of DAC-8012
VIM 2"'"
V1L •
FIGURE 3: Digital InputlOutput Structure
,-------Ril
DB9
DB11
DBl
DBO
(lSB)
(MSB)
WR
FIGURE 2: N-Channel Current Steering Switch
TO LADDER
FROM~
0----1
INTERFACE
LOGIC
AGND
OUT 1
DIGITAL SECTION
Figure 3 shows the digital 1/0 structure for one bit. When the
data strobe (DS) and the RD/WR lines are held low, data at the
digital input is fed through the input buffers and the data latches
which control the DAC current output switches are transparent.
Data is latched when either DS or RDIWR go high. When the data
strobe DS is held low and the RDIWR line is held high, the
three-state buffer becomes active and the data from the latches is
fed through the three-state buffers to the digital input/output
lines. This is known as the Read Cycle, or data read back.
The input buffers are simple CMOS inverters designed such
that when the DAC-B012 is operated with Voo = +SV, the buffers
convert TTL input levels (2.4V and O.BV) into CMOS logic levels.
When the digital input is in the region of 1.0V to 3.0V. the input
buffers operate in their linear region and draw current from
the power supply. To minimize power supply currents, it is
recommended that the digital input voltages be as close to the
supply rails (Voo and DGNO) as is practically possible. The
DAC-B012 may be operated with any supply voltage in the range
SV SVoo SlSV. With Voo =+lSV, the input logic levels are CMOS
compatible only, i.e., 1.SV and l3.SV.
The three-state output buffers, in the active mode, provide TTLcompatible digital outputs with a fan-out of one TTL load when
the DAC-B012 is operated with +SV power supply. When
powered from +lSV, the output buffers provide output logic
levels of 1.SV and 13.SV. Three-state output leakage is typically
10nA.
11-128
1/86, Rev. Al
---------I1fMD
DAC-8012 CMOS 12-BIT MULTIPLYING D/A CONVERTER "WITH MEMORY"
FIGURE 4: Unipolar Binary Operation
TABLE I: Recommended Trim Resistor Value vs. Grades
TRIM
RESISTOR
R1
R2
HP/FR/BR
1000
330
GP/ER/AR
200
6.80
VOUT
TABLE II: Unipolar Binary Code Table for Circuit of Figure 4
BINARY NUMBER IN
DAC REGISTER
DBll-0BO
ANALOG OUTPUT
"SEE TABLE 1
BASIC APPLICATIONS
Figures 4and 5 show simple unipolar and bipolar circuits using
the DAC-8012. Resistor R1 is used to trim for full scale. The
following versions: DAC-8012AR, DAC-8012ER, DAC-8012GP,
have a guaranteed maximum gain error of ±1 LSB at +25·C and
Vee = +5V, and in many applications the gain trim resistors are
not required. Capacitor C1 provides phase compensation and
helps prevent overshoot and ringing when using high speed op
amps. The circuits of Figures 4 and 5 have constant input
impedance at the VREF terminal.
1111
1111
1111
-V1N '
1000
0000
0000
-V1N '
0000
0000
0001
-V1N '
0000
0000
0000
e
e
095
4096 }
048
4096
} = -1/2 VIN
{40~6 }
o Volts
TABLE III: 2's Complement Code Table for Circuit of Figure 5
ANALOG OUTPUT
DATA INPUT
The circuit of Figure 4 can either be used as a fixed reference
D/A converter so that it provides an analog output voltage in the
range 0 to -VIN (the inversion is introduced by the op amp); or
V1N can be an ac signal in which case the circuit behaves as an
attenuator (2-Quadrant Multiplier). V1N can be any voltage in the
range -20V :5VIN :5+20V (provided the op amp can handle such
voltages) since VREF is permitted to exceed Vee. Table II shows
the code relationship for the circuit of Figure 4.
Figure 5 and Table III illustrate the recommended circuit and
code relationship for bipolar operation. The D/A function itself
uses offset binary code, and inverter U, on the MSB line,
converts 2's-complement input code to offset binary code. The
inverter U, may be omitted if the inversion is done in software,
using an exclusive OR instruction.
01 1 1
1111
1111
+V1N ' {2047 }
2048
0000
0000
0001
+V1N '
0000
0000
0000
1111
1111
1111
-V1N '
1000
0000
0000
-VIN'
{20:8 }
o Volts
{20:8 }
e
048
2048 }
R3, R4 and R5 must match within 0.01 % and should be the same
type of resistors (preferably wire-wound or metal foil), so that
their temperature coefficients match. Mismatch of R3 value to
R4 causes both offset and full scale error. Mismatch of R5 to R4
and R3 causes full scale error.
FIGURE 5: Bipolar Operation (2's Complement Code)
DATA INPUT
11-129
1/86, Rev. A 1
~
~
~
0
U
l'i
0
~
0
~
~
l'i
......
0
II
-----------l~ OAC·BOil! CMuS i2·BiT MULTIPLYING CIA CONVERTER "WITH MEMORY"
APPLICATIONS HINTS
INTERFACING THE DAC-8012 TO MICROPROCESSORS
Output Ollset: CMOS D/A converters exhibit a code-dependent
output resistance that causes a code-dependent error voltage
at the output of the amplifier. The maximum amplitude of this
offset, which adds to the D/A converter nonlinearity, is 0.67 Vas
where Vas is the amplifier input-offset voltage. To maintain
monotonic operation, it is recommended that Vas be no greater
than 10% of 1 LSB over the temperature range of operation.
Figure 6 shows the interface configuration for the 68000 16-bit
microprocessor. No external logic is required to write data into
the DAC orto read back data from the DAC-8012 latches. Analog
circuitry has been removed for clarity.
FIGURE 6: 68000 l6-Bit Microprocessor to DAC-8012 Interface
General Ground Management: AC or transient voltages between AGND and DGND can cause noise injection into the
analog output. The simplest method of ensuring that voltages at
AGND and DGND are equal is to tie AGND and DGND together
at the DAC-8012. It is recommended that two diodes (1 N914 or
equivalent) be connected in inverse parallel between AGND
and DGND pins in complex systems where AGND and DGND
tie on the backplane.
68000
ADDRESS
CPU
BUS~l
I
ADDRESS
l
os
I DECODER I
CTACK
R/W
RD/Vim
~
DB11
DATA BUS
Digital Glitches: When RD/WR and DS are both law, the latches
are transparent and the D/A converter inputs follow the data
inputs. Some bus systems do not always have data valid for the
whole period during which RD/WR is low. This will allow invalid
data to briefly appear at the DAC inputs during the write cycle.
This can cause unwanted glitches at the DAC output. Retiming
the write pulse RD/WR, so that it only occurs when data is valid,
will eliminate the problem.
~
'1
r
DBO
FIGURE 7: 8-Bit Processor to DAC-8012 Interface
"Qo = DECODED ADDRESS FOR LATCH TO DAC OPERATIONS
01 = DECODED ADDRESS FOR DATA BUS TO INPUT LATCH OPERATION
02
DECODED ADDRESS FOR OUTPUT LATCH TO DATA sus OPERATION
=
A15
t-----------------------------'
ADDRESS BUS
Aot----,
00 '0,*
PROCESSOR
SYSTEM
~P---i=~=t=====
8-BIT DATA BUS
11·130
1/86, Rev. A1
DAC-8212
JPMI}
DUAL 12-BIT BUFFERED
MULTIPLYING CMOS D/A CONVERTER
PreCISIon Monolithics lnc.
PRELIMINARY
FEATURES
GENERAL DESCRIPTION
• lWo Matched 12-Blt DACs on One Chip
• Direct Parallel Load of All 12 Bits for High
Data Throughput
• On Chip Latches for Both DACs
• 12-Blt Endpoint Linearity (:t:1/2 LSB)
• + 5V to + 15V Single Supply Operation
• DACs Matched to 1%
• Four-Quadrant Multiplication
• Low Power Consumption
The DAC-8212 contains two 12-bit multiplying digital-to-analog
converters. Excellent DAC-to-DAC matching and tracking results from monolithic construction. The DAC-8212 consists of two
thin-film R-2R resistor-ladder networks, two 12-bit data latches,
one 12-bit input buffer, and control logic. Operation from a +5 or
+ 15 volt single power supply disSipates only 20mW of power.
Digital input data is directed into one of the DAC data latches
determined by the DAC selection control line DAC A/DAC B.
The data load cycle is similar to the write cycle of a random
acce§!..mem2!X, activated by the WR and CS control inputs.
With WR and CS lines logic low, the input latches are transparent,
allowing input digital data to flow directly to the DAC selected by
the DAC A/DAC B select input.
APPLICATIONS
•
•
•
•
•
Automatic Test Equipment
Robotics
Programmable Instrumentation Equipment
Digilal Gain/AHenuation Control
Ideal for BaHery-Operated Equipment
PIN CONNECTIONS
ORDERING INFORMATIONt
PACKAGE: 24-PIN**
RELATIVE
ACCURACY
E~:~R
±1/2LSB
±1/2LSB
±1 LSB
±6 LSB
MILITARY*
INDUSTRIAL
COMMERCIAL
TEMPERATURE TEMPERATURE TEMPERATURE
-55'C TO + 125'C -25'C TO + 85'C O'CTO +70'C
DAC8212AV
DAC8212BV
DAC8212EV
DAC8212FV
24-PIN
HERMETIC DIP
DAC8212GP
DAC8212HP
• For deVices processed In total compliance to MIL-STD-883, add 1883 after part
number. ConsuH factory for 883 data sheet
"Package deslgnabon SuffiX V Hermebc DIP, SuffiX p. Plastic DIp
t All commeraal and Industrial temperature range parts are available With burn-In.
For ordenng Information see 1986 Data Book, Section 2
FUNCTIONAL DIAGRAM
Voo
DACAl
DACB
co
Wi<
This preliminary product Information Is based on testing of a limited number of devices. Final specifications may vary. Please contact local sales
office or distributor for final data sheet.
11-131
1/86, Rev. A
III
-----t1fMi} DAC-S212 DUAL 12-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTER -
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C, unless otherwise noted.)
VDDtoAGND ....•....•......•............. OV, +17V
V DD to DGND .•...•.•...•..•....•.......... OV, +17V
Dice Junction Temperature •................... + 150°C
Storage Temperature .•...•...•.•...... -65·C to + 150·C
AGND to DGND ....•.......•.•...........•..•.. VDD
DGND to AGND ........••....•.......•......... VDD
Digital Input Voltage to DGND ...•....... -0.3V, VDD +0.3
Lead Temperature (Soldering, 60 sec) ...•..•..... +300·C
CAUTION:
I. Do not apply voltages h'gher than voo or less than GND potential on any
terminal except VREF .
2. The digital control Inputs are zener-protected; however, permanent damage
may occur on unprotected units from high-energy electroslaticfields. Keep units
in conductive foam at all times until ready to use.
3. Do not insert this device Into powered sockets; remove power before insert,on or
removal.
4. Use proper anti-static handling procedures.
5. Stresses above those listed under "Absolute Maximum Ratings' may cause
permanent damage to the device.
VPIN 2, VPIN 24 to AGND .•..•......•.... -0.3V, VDD +0.3
VREF A, VREF B to AGND ...•.•......•........... ± 25V
VRFB A, VRFB B to AGND .••......•••............ ±25V
Power Dissipation (Any Package) to + 75°C ....... 450mW
Derate Above + 75°C by .•................•.• 6mW/oC
Operating Temperature Range
AV, BV Versions .•.............••..• -55·C to + 125·C
EV, FV Versions •......•........•..•• -25·C to +85°C
GP, HP Versions ....•....••.....•..... O·C to + 70·C
at VDD = +5Vor +15V, VREF A = VREF B = +10V, OUT A = OUT B = OV; TA = -55·C
= -25·C to +85°C apply for DAC-8212EV/FV; TA = O·C to + 70·C apply for DAC-8212GP/HP,
ELECTRICAL CHARACTERISTICS
to + 125°C apply for DAC-8212AVlBV; TA
unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
MIN
TVP
MAX
UNITS
±1/2
LSB
±I
LSB
Specifications apply to both DAC A and DAC B
STATIC ACCURACY
12
Resolution
N
Relative Aocuracy
NL
Endpoint Linearity Error
Differential Nonlinearity
DNL
All Grades are Monotonic
Full Scale Gain Error
(Note I)
GFSE
Output Leakage Current
Out A (Pin 2)/Out B (Pin 24)
'LKG
Input Resistance
(VRE~' VREFB)
RREF
VREFAIVRE.e
(Input Resistance Mstch)
~VREFA,B
Bits
TA = +25'C
DAC-8212A/E/G
DAC-8212B/F/H
±I
±6
TA = Full Temp. Range
DAC-8212NE/G
DAC-8212B/F/H
±2
±7
Data In 0000 0000 0000
TA = +25'C
TA = Full Temp. Range
5
8
0.1
LSB
±50
±400
nA
15
kll
±I
%
DIGITAL INPUTS
Digital Input High
DlgHallnput Low
Input Current
Input capacrtance
(Note 2)
V'NH
V'NL
Voo= +5V
2.4
VDO = +15V
13.0
V
Voo= +5V
0.8
Voo= +15V
1.5
V
TA =+25'C
TA = Full Temp. Range
I'N
Voex = OV or Voo
C'N
DBO-DBII
CS,DACA/DAC B
WR,
11-132
.001
±I
±IO
t-""
WRITE SELECT
1---..
"ow
""'----
}
S~~~~I8I ~or ~~AI AlB, A/W
tw
M
0
U~ LOW PULSES
MINIMUM
TIME BETWEEN
DATA HOLD nME (An'ER
... HIGH)
=
WRITE CYCLE (tDSW
+ iNw)
2Onst.
180 nstDsw MIN
80nstNw
20 ne tH
280nstw
MODE SELECTION TABLE
DS1
DS2
Alii
RIW
DACA
DACB
DACC
DACD
H
H
X
X
HOLD
HOLD
HOLD
HOLD
L
H
H
L
WRITE
HOLD
HOLD
HOLD
L
L
H
L
WRITE
HOLD
WRITE
HOLD
L
H
H
H
READ
HOLD
HOLD
HOLD
L
L
H
H
HOLD
HOLD
HOLD
HOLD
L
H
L
L
HOLD
WRITE
HOLD
HOLD
L
L
L
L
L
HOLD
WRITE
HOLD
WRITE
L
H
L
H
HOLD
READ
HOLD
HOLD
L
L
L
H
HOLD
HOLD
HOLD
HOLD
H
L
H
L
HOLD
HOLD
WRITE
HOLD
H
L
H
H
HOLD
HOLD
READ
HOLD
H
L
L
L
HOLD
HOLD
HOLD
WRITE
H
L
L
H
HOLD
HOLD
HOLD
READ
= Low State
H
= High State
X
= Irrelevant
11·139
1/86, Rev. A
III
PM-S62
12-BIT MULTIPLYING CURRENT-OUTPUT
D/A CONVERTER
Pn:'ClSIOil MOllolithlcs Inc.
FEATURES
•
•
•
•
•
•
•
•
and Increased output resistance. The PM-562 Is pin compatible with the AD562.
Nonlinearity ......................... ± 1/4 LSB (Max)
Settling Time ............................ 1.5 ~s (Typ)
No Laser TrImming Used In Fabrication
Intarnal Range and Offset Scaling Resistors
Guaranteed Monotonlclty Over Temperature
TTL or CMOS Logic Input Compatibility, Pin Selectable
Low Power Consumption •. . . . . . . . . • . • .. 130mW (Typ)
Dlractly Pin Compatible with AD582
A highly stable trim method; selective shorting of zener
diodes, provides 13-bit accuracy without the need for laser
trimming. Reliability of this trimming method has been
proven in several other PMI products with many years of
reliability history. Internal scaling resistors plus an external
op amp simplifies construction In voltage output applications,
while maintaining accuracy over wide operating temperature
ranges. The PM-562Is recommended for 12-blt accuracy DlA
applications where single-chip reliability, small size and low
cost are primary considerations.
ORDERING INFORMATIONt
NONLINEARITY
@2S·C(LSB)
PMI MODEL NO.
TEMP. RANGE
±1/4
±1/2
±1/2
±1/4
±1/2
PM562AV'
PM562BV'
PM562FV
PM562GV
PM562HV
-55· C/+ 125· C
-55·C/+125·C
-25· C/+65· C
0·C/+70·C
0·C/+70·C
PIN CONNECTIONS
V+
• For devices processed in total compliance to MIL-STD-~83. add /883 after
part number. Consult factory for 883 data sheet.
fAil commercial and Industrial temperature range parts are available with
burn-In. For ordering Information see 1984 Data Book. Section 2.
GENERAL DESCRIPTION
The PM-562 Is a 12-blt monolithic multiplying dlgltal-toanalog converter consisting of a reference current amplifier,
an R-2R ladder network, range and offset scaling resistors,
and 12 high-speed current switches. Improvements provided
by the PM-562 include greater negative power supply range
TOP VIEW
24-PIN HERMETIC DIP
'Connect VLCto V+ for CMOS logic Inputs. Leave VLCopsn circuit or
grounded for TTL inputs.
EQUIVALENT CIRCUIT
V+
i,
VLC
MSB
81
2
24
B2
B3
23
B4
86
21
22
B6
20
,.
87
B8
,.
B9
17
,.
LSS
B10 811 812
16
14
,.
11
PM-582
SUM
VREF(+I
VREf(-I
IREF~
4
5
•
19'~fll
20kfI
IFS=4X IREF
~ V.....
/"
I
LOGIC INPUT SWITCH DRIVERS
L
I
I
I
I
I
I
I
I
I
'J
I
I
I
I
I
I
I
I
I
'1
"''' ,.
"'''
l-'j j l~ j l~ j l~ j~~~
•
12
20V SPAN
tOV SPAN
10
GND
(113 SHOWN)
.........
"'"
......
... ......
•
BIPOLAR OFFSET
"R" OUT
7
BIPOLAR OFFSET
9.951dl
--
"R" IN
•
V-
Manufactured under tfilo. following patent: 4.055.773.
11·140
1/86, Rev. A
_ _ _ _ _ _ _ _-IIfMi)PM-58212-BIT MULTIPLYING CURRENT-OUTPUT D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V+) •••••••••••••••••••••••••••••• + 18V
Supply Voltage (V-) •••••••••••••••••••••••••••••• -18V
V+ to V- •••••••••••••••••••••••••••••••••••••••••• 36V
Logic Inputs •••••••••••••••••••••••• V- to (V- plus 36V)
Summing Junction (Pin 4) •••••.••••••••••••••• V- to V+
CMOS/TTL Threshold (Pin 2) •••••••••••••••••• V- to V+
lOUT (Pin 9) ••••••••••••••••••••••••••••••• -5V to +18V
Span Resistors •••••••••••••••••••••••••••••••••••• 36V
Operating Temperature Range
PM-562A1B ......................... -55· C to + 125· C
PM-562F ••••••••••••••••••••••••••••• -25·Cto+85·C
PM-562G/H ••••••••••••••••••••••••••••• O· C to + 70· C
Storage Temperature Range ••••••••••• -65· C to + 150· C
Power Dissipation at TA = 125· C •••••••••••••••• 1000mW
Lead Temperature (Soldering, 60 sec) ••••••••••••• 300·C
ELECTRICAL CHARACTERISTICS atV+
=5V, V- =-15V, VREF (+) =+10.0000V, VREF(-) =OV, TA=+25·C,
~
unless otherwise noted.
PM-562A1G
MIN
TVP
MAX
PARAMETER
SYMBOL
CONDITIONS
Resolution
N
TA = Full Range
12
TA = Full Range
12
Monotonlclty
PM-562B/F/H
MIN
TVP
MAX
12
UNITS
Bits
12
Bits
~
~
0
Nonlinearity
NL
±1/4
±1/2
LSB
U
Differential Nonlinearity
DNL
±1/2
±1/2
LSB
Settling Time
Is
0
0
Output Voltage Compliance
Voc
Full-Scale Output
Current Range
IFR
Zero-Scale Current
Izs
Output Resistance
Ro
Output Capscitance
Co
Reference Input Impedance
ZIN
To ± 112 LSB, all bits
ON or OFF
1.5
1.5
- +10/-1.5
VREF (+) = +10.0000V Unipolar
Bipolar
R2=500
-1.6
±0.8
All bits OFF
I'S
V
- +10/-1.5
-2.0
±1.0
-2.4
±1.2
.005
0.05
-1.6
±0.8
-2.0
±1.0
-2.4
±1.2
mA
.005
0.05
%FS
2
Pln5
MO
30
30
pF
20
20
kO
Gain Error
I FSE
R2 = 500. (Note I)
±0.2
±0.2
%FS
Bipolar Zero-Scale Error
IBZSE
R1 = 500, (Note I)
±0.1
±0.1
%FS
Full-Scale Gain
Adjustment Range
AI FSR
R2= 1000 Trimpot. (Note I)
±0.25
±0.25
%FS
Bipolar Zero-Scale
Adjustment Range
±0.25
AlsZSR
R1 = 1000 Trimpot. (Note I)
Power Supply
Gain Sensitivity
+Pss
-P SS
V+=5VorV+=15V
V-=-15V
Supply Current
1+
l-
V+ = 4.75V to 15.8V
V- = -15V ± 10%
TTL Logic
Input Voltage
VIH
VIL
Pln2
Opsn Circuit
IIH= 100nA
IlL =-I00I'A
2.0
CMOS Voltage
Logic Input
VIH
VIL
Pln2
tied to Pin 1
IIH= l00nA
IlL =-I00I'A
70
±0.25
2
6
5
-7
11-141
%FS
2
6
18
-25
5
-7
18
-25
2.0
0.8
0.8
70
30
30
ppmFSI%
mA
V
%V+
1/86, Rev. A
~
,
0
~
~
0
0
---------I1fHD
PM-56212-BIT MULTIPLYING CURRENT-OUTPUT CIA CONVERTER
ELECTRICAL CHARACTERISTICS at V+ = 5V, V-=-15V, VREF (+) = +10.0000V, VREF (-) = OV,-55'C :STA:S+125'C for
PM-562A!B, -25' C:S TA:S +85'C for PM-562F, O'C:S TA:S +70'C for PM-562G/H, unless otherwise noted.
PM-562A/G
PARAMETER
SYMBOL
CONDITIONS
Zero-Scale Temperature
Coefficient
TCI ZS
Unipolar Leakage
Current Change (Note 2)
Bipolar Zero-Scale
Temperature Coefficient
TCl sZS
Bipolar (Note 2)
Full-Scale Gain
Temperature Coefficient
Differential Nonlinearity
Temperature Coefficient
TC ONL
MIN
TYP
PM-5628/F/H
MAX
MIN
TYP
MAX
UNITS
ppmFS/'C
4
ppmFS/'C
Excludes VREF (Note 2)
ppmFS/'C
(Note 2)
ppmFS/'C
NOTES:
1. See connection diagram.
2. Guaranteed by design.
CONNECTION DIAGRAM
+15V
VLe
MSB
81
82
83
84
85
B6
87
B8
89
810
B'1
LSB
812
11
---------jI
10
I
5k!)
PM-562
SPAN
RESISTOR
{
I
I
I
I
5k!)
I
I
I
REF AMP
SUMMING
JUNCTION
0---'-1----....- - - - - - ,
+15V
r - - - .....I
W\r--....::.f---'lM,-.....-+e-...
.....
I
I
I
I
I
I
UNIPOLAR
OFFSET
I
I
ADJUST
I
I
I
L________________________________________ Q'
_
_________________ I
I
I
I
I
BIPOLAR
-lSV
loon OFFSET ADJUST
I
~
NOTE:
Set VLC = V+ for CMOS logic inputs. Leave V LC open circuit or grounded for
TTL Inputs.
BURN-IN CONFIGURATION
PM·S62
+ 1 0 V o - - - - - - - - - -....-+----+--0 ~O~6 +10V)
v-15V
TTL DIGITAL INPUTS
NOTES:
1. Calibration Procedure First set digital inputs B, thru B'2 to digital
zero and adjust R, until VOUT = 0 OOOOV Next set digital Inputs B,
thru B'2 to digital one's and adjust R2 until VOUT = 9.9976V.
2.
Bypass V+ and V- supplies with O.01IlF in parallel with 1.uF
capacitors
Figure 2 +10V Unipolar Voltage Output
11-145
1/86, Rev. A
I
----------l1EM!) PM-56212-BIT MULTIPLYING CURRENT-OUTPUT D/A CONVERTER
-10 DODV
OUTPUT ADJ
O.OOOV
OUTPUT ADJ
VREF
"'10000V
3,12
-
> ....--oVOUT
(-10V TO +10VI
-15V
v-
TTL DIGITAL INPUTS
NOTES:
1. Calibration Procedure· Set VREF = 10.0000V. Next set dlgllallnputs
8, thru 8'2 to digital zero and adjust A, until VouT =-10.0000V. Set
digital inputs 8, thru 8'2to 100000000000 (I.e. only turn ON MSB)
Figure 3
and adjust R2 until VOUT = O.OOOOV.
Bypass V+ and V- supplies with 0.01"F
capacitors.
In
parallel with 1"F
±10V Bipolar Voltage Output
PRECISION X-Y POSITIONING SYSTEM
4-20mATRANSMITTER
lOUT
II
-15V
GND +15V
4-20mA
'-_ _-t-....V·OUT
11-146
1/86, Rev. A
---------I~ PM-5S2 12·BIT MULnPLYING CURRENT·OUTPUT D/A CONVERTER
DIGITALLY CONTROLLED R.F. OSCILLATOR
+V
I
11·147
1/86, Rev. A
PM-S6SA
COMPLETE HIGH-SPEED 12-BIT
MONOLITHIC D/A CONVERTER
Preci"'IOll Monolithics Inc.
PRELIMINARY
FEATURES
oto 10V, 0 to 5V, -5 to 5V, -10 to 10V output voltages using an
•
•
•
•
•
•
•
•
external op-amp and the internal resistors. The digital inputs are
TTL-compatible and may be driven by 5V or 15V CMOS.
Very Fast-Settling (Sample Teated) •••••••• 250ns Max
High-Stability Burled·Zener Reference on Chip
Linearity Guaranteed Over Temperature •• 1/2 LSB Max
Monotonlclty Guarenteed Over Temperature
Low Power Conaumptlon •••.•••..••.••• 345mW Max
Operation Guaranteed et :t 12V Supplies
Inputs Compatible with 5V and 15V Logic
AD565A Second·Source Pin Compatibility with Improved
Tempco, Reference Load Capability, and Trimming
Logic delay to analog output is typically only 40ns, and settling to
0.01% of full-scale is factory tested. Great attention has been
given to minimizing glitch energy and amplitude.
The subsurface zener reference Is very stable, both over temperature and time. Typical gain tempco is only 10ppm/oC. The zener
reference has less wideband noise than a typical bandgap type
and is also free from excessive low-frequency noise. The reference is trimmed to 2 LSB Typ.
ORDERING INFORMATIONt
PACKAGE
LINEARITY
OVER
FULL· SCALE
TEMPERATURE TEMPCO, MAX
RANGE
±1/2LSB
±3/4LSB
±1/2LSB
±3/4LSB
EPOXY
DIP
24-PIN
15ppm/'C
30 ppm/'C
PIN CONNECTIONS
HERMETIC
OPERATING
DIP
TEMPERATURE
24-PIN
RANGE
MIL
MIL
COM
COM
PM565AAV'
PM565ABV'
PM565AGP
PM565AHP
15ppm/'C
30 ppm/'C
• For devices processed in total compliance to MIL-STD-663, add 1883 after part
number. Consult factory for 663 data sheet.
t All commercial and Industrial temperature range parts are available with burn-In.
For ordering information see 1986 Data Book. Section 2.
GENERAL DESCRIPTION
AEFOUT
4
AEFGNO
6
AEFIN
6
BIPOLAR OFFSET
8
10VSPAN
10
20YSPAN
11
POWEAGNO
12
24·PIN
HERMETIC DIP
(V·Sufflx)
The PM-565A is a high-speed 12-bit bipolar digital-to-analog
converter which provides a trimmed reference and application resistors. The output is a 0-2mA current, which can be converted to
EQUIVALENT CIRCUIT
REF OUT
v+
BIPOLAR OFFSET
20VSPAN
10VSPAN
SkU
r--+--+-oIoUT
REFINlo-=t-"",,/\r-4-.;
BkO
FIEF GND
C>-''I--.-JVV..........
v-
81 82 83 B4 85 88 87 B8 B9 810 811 812
(MSBI-4-- DIGITAL LOGIC INPUTS ________ (LSB)
This preliminary product Information Is based on testing of a limited number of devices. Final specifications may vary. Please contact local.ales
office or distributor for final data aheet.
11-148
1/86, Rev. A
PM-7226
QUAD 8-BIT CMOS D/A CONVERTER
WITH VOLTAGE OUTPUT
Pn:CISIOIl MOJloiJthu.:s Inc.
ADVANCEPRODUCTINFO~TION
FEATURES
•
•
•
•
•
•
•
•
•
CROSS REFERENCE
Four Voltage Output DACs on a Single Chip
Microprocessor Compatible
Internal Output Buffer Amplifiers
Common 8- Bit Data Bus
AdJustment-Free .......••.•..... ±2LSB Total Error
Guaranteed Monotonlclty
Single or Dual Supply Operation
Latch-Up Resistant
Space Saving 20-Pln 0.3 Inch Wide DIP
APPLICATIONS
•
•
•
•
•
•
•
Automatic Test Equipment
Industrial Automation
Process Controls
Instrumentation Equipment
Medical Equipment
Multi-Channel Microprocessor-Controlled Systems
X-Y Graphics
PMI
ADI
TEMPERATURE
RANGE
PM7226AR
PM7226ER
PM7226GP
AD7226TD
AD7226BQ
AD7226KN
MIL
IND
COM
GENERAL DESCRIPTION
The PM-7226 places four a-bit voltage output CMOS digital-toanalog converters on a single chip. By using a single a-bit data
bus port, the device fits into a space saving 20-pin 300 mil DIP
package. The internal output buffer amplifiers can each drive up
to 5mA from either single or dual supply rails. Each DAC has
individually addressable data latches for easy microprocessor
interface.
The compact size, low power, and economical cost-per-channel,
makes the PM-7226 attractive for applications requiring multiple
D/A converters without sacrificing circuit-board space.
The PM-7226 is a direct replacement for AD7226.
ORDERING INFORMATIONt
PACKAGE: 2o-PIN""
PIN CONNECTIONS
TOTAL
COMMERCIAL
INDUSTRIAL
MILITARY"
UNADJUSTED TEMPERATURE TEMPERATURE TEMPERATURE
ERROR
±2LSB
PM7226GP
PM7226ER
PM7226AR
20-PIN HERMETIC DIP
(R-Suffix)
• For devices processed in total compliance to MIL·STD·883, add 1883 after part
number. Consult factory for 883 data sheet.
"Package Designation: SuffiX R: Hermetic DIP; Suffix P: Plasbc DIp
t All commercial and Industrial temperature range parts are available with burn·in.
For ordering Information see 1986 Data Book, Sactlon 2.
20-PIN EPOXY DIP
(P-Sufflx)
FUNCTIONAL DIAGRAM
v,""
> - _ - r2-oVOUTA
>---+-i.!.'OVQUTB
MSB
7
8-BIT
I
DATA BUS \r14!!jI_ _"'_'_U_US_--,
LSB
>-_-I"20'OVoU'<:
~ ~:
AD
17
This advance product Information describes a product In development at the time of this printing. Final specifications may vary, Please contact
local sales office or distributor for IInal data sheet.
1/86, Rev. A
11-149
II
PM-7524
CMOS 8-BIT BUFFERED MULTIPLYING
D/A CONVERTER
Precision Monolithics Inc.
FEATURES
•
•
•
•
•
•
•
•
•
•
CROSS REFERENCE
±1/8 LSB Endpoint Linearity
Microprocessor Compatible
On-Board Data Latches
Guaranteed Monotonlclty Over Full Temperature Range
Low Power Consumption " , ' , ' , " , ' , , ' , ' SmW @ +SV
+SV to +1SV Operation
Full Four Quadrant Multiplication
TTL/CMOS Compatible
Latch-Up Resistant
No Schottky Diodes Required
APPLICATIONS
•
•
•
•
•
Microprocessor Controlled Circuits
Precision AGC Circuits
Bus Structured Instruments
Function Generators
Digitally Controlled Attenuators and Power Supplies
TEMPERATURE
RANGE
PMI
ADI
PM7524AO
PM7524BO
PM7524BO
AD7524UD
AD7524TD
AD7524SD
MILITARY
PM7524EO
PM7524FO
PM7524FO
AD7524CD
AD7524BD
AD7524AD
INDUSTRIAL
PM7524GP
PM7524HP
PM7524HP
AD7524LN
AD7524KN
AD7524JN
COMMERCIAL
PIN CONNECTIONS
ORDERING INFORMATIONt
PACKAGE: 16-PIW'
NONLINEARITY
MILITARY'
TEMPERATURE
-55'C to +125'C
INDUSTRIAL
TEMPERATURE
-25'C to +85'C
COMMERCIAL
TEMPERATURE
Q'C to +7Q'C
±1/8(LSB)
±1/4(LSB)
PM7524AO
PM7524BO
PM7524EO
PM7524FO
PM7524GP
PM7524HP
16-PIN EPOXY DIP
(P-Suffix)
• For devices processed," total compliance to MIL-STD-883, add 1883 after
part number. Consult factory for 883 data sheet
"Package Designation Suffix 0 Hermetic DIP. Suffix P Epoxy DIP
tAil commercial and Industnal temperature range parts are available with
burn~jn. For ordenng information see 1986 Data Book, Section 2
GENERAL DESCRIPTION
16-PIN HERMETIC DIP
(Q-Suffix)
FUNCTIONAL DIAGRAM
The PM-7524 is an 8-bit monolithic multiplying digital-toanalog converter with input latches. It is compatible with all
popular 8-bit microprocessors including the 6800, 8080, 8085,
and Z80. It's load cycle is similar to that of a RAM's write cycle.
10kn
10kn
10kn
PMI's tightly controlled thin-film resistor processing provides
1/8 LSB linearity without laser trimming. The design incorporates a matching MOS transistor in series with the feedback
resistor to achieve a gain and linearity error tempco of
2ppm/oC.
20kn
L--++-4--I-+-+-~I--H-+---+-oOUT2
The PM-7524 exhibits excellent performance on a single +5V to
+15V power supply. It is TTL compatible at +5V and dissipates
less than 10 mW; at +15V it is CMOS compatible and dissipates
less than 30 mW.
' - i - -......+--......+---.!I--.....-:--.---~ aun
10kn
'-",fI/'r-+-QRFB
PMI's improved latch-up resistant design eliminates the need
for external protective Schottky diodes.
WR
The PM-7524 is manufactured using thin-film resistors on an
advanced oxide-isolated silicon-gate CMOS process.
OB7 (MSB)
DB.
DB'
DBO /LSBj
GND
DATA INPUTS
11·150
1/86, Rev. A
----------I~ PM-7524 CMOS 8-BIT BUFFERED MULTIPLYING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C, unless
otherwise noted)
V DD (to GND) ................................ -0.3V, +17V
V REF (to GND) ..•...•..................•.•........ ±25V
RFB (to GND) ......•......................•......• ±25V
Digital Input Voltage To GND .....•........... -0.3V to V DD
Output Voltage (Pin 1, Pin 2) .................. -0.3V to V DD
Power Dissipation (Package)
Ceramic (Suffix 0)
To +75°C ...••...•..........•..........•....•. 450mW
Derates Above +75° C By .................••... 6mW/o C
Plastic (Suffix P)
To +70°C ..................................... 670mW
Derates Above +70° C By .................... 8.3mW/o C
Operating Temperature Range
Military (AO, BO Versions) .............. -55°C to +125°C
Industrial (EO, FO Versions) ............. -25° C to +85° C
Commercial (GP, HP Versions) .•..•........ O°C to +70°C
Dice Junction Temperature .•..........•..•........ +150° C
Storage Temperature ..................... -65°C to +150°C
Lead Temperature (Soldering, 60 sec) ............... +300° C
CAUTION:
Do not apply voltages higher than VDO or less than GND potential on any
terminal except VAEF (Pin 15) and RFB (Pin 16)
4
The digital control Inputs are zener protected, however, permanent
damage may occur on unconnected units from high energy electrostatic
fields Keep units In conductive foam at all times until ready to use
Use proper anti-static handling procedures
Absolute MaXimum Ratings apply to both packaged deVices and DICE
Stresses above those listed under Absolute MaXimum Ratings may cause
permanent damage to the deVice
ELECTRICAL CHARACTERISTICS at V REF = +10V; V OUT1 = V OUT2 = OV; TA = -55°C to +125°C apply for PM-7524AO/BO;
TA = -25°C to +85°C apply for PM-7524EO/FO; TA = O°C to +70°C apply for PM-7524GP/HP, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
STATIC ACCURACY
PM-7S24A/E/G
Resolution
Relative Accuracy
(Notes 1, 2)
N
INL
PM-7S24B/F/H
Voo::: +5 or +15V
TA = Full Temp Range
Bits
Voo ::: +5V
TA ::: Full Temp Range
±02
±02
Voo=+15V
TA = Full Temp Range
±005
±01
±10
±14
±10
±14
±05
±O 6
±O 5
±O 6
%FSR
Voo ::: +5V
Gain Error
(Note 3)
G FSE
TA = +25°C
TA = Full Temp Range
%FSR
Voo ::: +15V
TA = +25°C
TA ::: Full Temp Range
Voo ::: +5V
Gain T C
(Notes 4. 5)
TCG FS
TA = Full Temp Range
±O 004
±0004
Voo::: +15V
TA ::: Full Temp Range
±0001
±OO01
%FSRrC
Voo = +5V
DC Power Supply
Rejection
AGain/A Voo
(Notes 3. 6)
TA ::: +25°C
PSR
TA = Full Temp Range
008
016
0002
001
008
016
0001
0005
002
004
0001
0005
002
004
%FSR/%
Voo = +15V
TA ::: +25°C
TA = Full Temp Range
Voo ::: +5V
TA ::: +25°C
Output Leakage
TA = Full Temp Range
(Notes 7. 8)
Current
IOUT1' IOUT2
0002
001
±50
±400
±50
±400
nA
ILKG
Voo ::: +15V
TA :::+25°C
TA = Full Temp Range
(Notes 7. 8)
11-151
±50
±200
±50
±200
1/86, Rev_ A
I
-----------1\fMD
PM-7524 CMOS 8-BIT BUFFERED MULTIPLYING D/A CONVERTER
= +1DV; VOUT1 = VOUT2 = DV; TA = -55°C to +125°C apply for PM-7524AQ/BQ;
=-25°C to +85°C apply for PM-7524EQ/FQ; TA =DOC to +7DoC apply for PM-7524GP/HP, unless otherwise noted. (Continued)
ELECTRICAL CHARACTERISTICS at VREF
TA
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
Input to 90% of
Final Analog
Output Current)
(Note 4)
PM-7524A1B
VDD = +5V
TA :::: +25°C
Propagation Delay
(From Dlgllal
tpD
PM-7524E/F/G/H
150
200
TA = Full Temp Range
(Note 9)
150
175
ns
VDD = +15V
TA = +25°C
TA = Full Temp Range
(Note 9)
65
90
65
80
PM-7524A/E/G
Output Current
Settling Time
(To 1/2 LSB)
(Note 4, 15)
ts
VDD = +5V
TA :::: +25°C
TA = Full Temp Range
(Note 9)
300
350
300
350
ns
Voo :::: +15V
TA :::: +25°C
TA = Full Temp Range
(Note 9)
Voo
AC Feedthrough
IOUT"I OUT2
PM-75248/F/H
FT
(Note 4)
200
250
200
250
025
050
0,25
050
20
20
120
30
120
30
30
120
30
120
= +5V or +15V
TA = +25°C
TA = Full Temp Range
(Note 10)
%FSR
REFERENCE INPUT
Input Resistance
(Pin 15 to GND)
(Note 11)
R'N
Von = +5V or +15V
TA = Full Temp Range
k!l
ANALOG OUTPUTS
Output Capacitance
COUT1 (Pin 1)
Voo
COUT2 (Pin 2)
Co
Voo
COUT1 (Pin t)
COUT2 (Pin 2)
= +5V or +15V
TA = Full Temp Range
(Note 4,12)
pF
= +5V or +15V
TA = Full Temp Range
(Note 4,13)
DIGITAL INPUTS
Digital Input
High
Digital Input
Low
V,H
V,L
=OV or VDO
+24
+135
+135
V
VDD = +5V
TA = Full Temp Range
+08
+08
VDD = +15V
TA = Full Temp Range
+1 5
+15
±1
±10
±1
±10
20
20
TA = +25°C
TA = Full Temp Range
C'N
TA = Full Temp Range
V ,N = OV
Voo
V
= +5V or +15V
liN
Input Capacitance
DBO-DB?
WR,CS
(Note 4)
+24
VDD = +15V
TA = Full Temp Range
Voo
Input Current
VIN
VDD = +5V
TA = Full Temp Range
JJA
= +5V or +15V
11-152
pF
1/86, Rev. A
_ _ _ _ _ _ _ _ _;~ PM-7524 CMOS a-BIT BUFFERED MULTIPLYING D/A CONVERTER
ELECTRICAL CHARACTERISTICS
TA
at VREF
= +10V;
VO UT1
= VO UT2 = OV;
TA
= -55°C to
+125°C apply for PM-7524AO/BO;
= -25°C to +85°C apply for PM-7524EO/FO; TA = OOC to +70o C apply for PM-7524GP/Hp, unless otherwise noted. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
TVP
MAX
MIN
TVP
MAX
UNITS
SWITCHING
CHARACTERISTICS
(Note 4)
PM-7524A/B
Vee = +5V
Chip Select to
Write Setup Time
(tWA = tes )
(Note 14)
TA = +25°C
tes
Ch I P Select to
Write Hold Time
PM-7524E/F/G/H
TA = Full Temp Range
170
240
170
220
Vee = +15V
TA = +25'C
TA = Full Temp Range
100
150
130
ns
100
PM-7524A/E/G
PM-7524B/F/H
PM-7524A1B
PM-7524E1F/G/H
Vee = +5V or +15V
TA = Full Temp Range
o
ns
Vee = +5V
TA = Full Temp Range
170
240
170
220
Vee = +15V
TA = +25'C
TA = Full Temp Range
100
150
100
130
Vee = +5V
TA = +25'C
TA = Full Temp Range
135
170
135
170
Vee = +15V
TA = +25'C
TA = Full Temp Range
60
100
60
BO
TA = +25°C
Write Pulse Width
(les :2: tWA' leH :2: 0)
Data Setup Time
tes
PM-7524A1E/G
Data Hold Time
Vee = +5V or +15V
TA = Full Temp. Range
ns
ns
PM-7524B/F/H
10
10
ns
II
POWER SUPPLY
Vee = +5V
Supply Current
(All Digital
TA = +25'C
TA = Full Temp. Range
Inputs = V'L or V,H )
Vee = +15V
TA = +25'C
TA = Full Temp Range
Supply Current
(All Digital
Inputs = OV or Vee)
Veo = .5V or ·15V
TA = +25'C
TA = Full Temp Range
NOTES:
1. Guaranteed monotonic over full temperature range and at Vee = +5V and
+15V
2. FSR (Full Scale Range) = VAEF - 1 LSB
3 USing Internal feedback resistor
4 Guaranteed by design and not production tested
5 Gain TC measured from +25' C to TMIN or from +25' C to T MAX
6. t!.Vee = ±10%
7. DBO-DB7 = OV; WR = CS = OV, VAEF = ±10V, for IOUT1'
B. DBO-DB7 = Vee, WR = CS = OV, VAEF = ±10V, for IOUT2
1
2
rnA
2
2
100
500
100
500
/lA
9 OUT110ad = 1000, C EXT = 13pF, WR = CS= OV, DBO-DB7=OVtoVee or
Vee to OV
10 VAEF = ±10V, f = 100kHz, DBO-DB7 = OV, WR = CS = OV
11. Temperature coeffiCient approximately equals +300ppm/'C
12 DBO-DB7 = Veo' WR = CS = OV
13 DBO-DB7 = OV, WR = CS = OV
14 See Timing Diagram
15. Extrapolated' ts (1/2 LSB) = tpe + 6.2r, where r = the measured first time
constant of the final RC decay
11-153
1/86, Rev. A
----------t1fMD
PM-7524 CMOS 8-BIT BUFFERED MULTIPLYING DIA CONVERTER
DICE CHARACTERISTICS
1.0UT1
2.0UT2
3. GND
4. DB7(MSB)
5. DB6
6. DB5
7. DB4
8. DB3
9.
10.
11.
12.
13.
14.
15.
16.
DB2
DB1
DBO (LSB)
CS
WR
Voo
VREF
RFB
For additional DICE information refer to
1986 Data Book, Section 2.
DIE SIZE 0.067 x 0.070 inch; 4690 sq. mils
(1.7 x 1.78 mm, 3.03 sq. mm)
WAFER TEST LIMITS at VREF = +10V, Voun = VOUT2 = OV; TA = +25°C.
PM-7524G
PARAMETER
SYMBOL
CONDITIONS
LIMIT
UNITS
STATIC ACCURACY
N
Vee = +5V or +15V
8
Bits MIN
Relative Accuracy
(Notes 1, 2)
INL
Vee
Vee
=+5V
=+15V
±002
±005
%of FSR MAX
Gam Error
(Note 3)
GFSE
Voe
=+5V or +15V
±005
%of FSR MAX
DC Power Supply
Rejection
aGain/aVoe
(Notes 3, 4)
Vee
=+5V
008
PSR
Voo
=+15V
002
Resolution
Output Leakage
Current
% of FSR/% MAX
ILKG
Vee =+5V or +15V
(Notes 5, 6)
±50
nAMAX
R'N
Vee
=+5V or +15V
5/20
kO MINIMAX
Digital Input
High
V,H
Voe
=+5V
V DD = +15V
+24
+135
VMIN
Digital Input
Low
V,L
Voe =+5V
Voe = +15V
+08
+15
V MAX
liN
Voo
=+5V or +15V
±1
/lAMAX
lee
Vee
Vee
=+5V
=+15V
lee
Vee
=+5V or +15V
'OUT1, 'OUT2
REFERENCE INPUT
Input Resistance
(Note 7)
DIGITAL INPUTS
Input Current
(V'N
=OV or Vee)
POWER SUPPLY
Supply Current
(V ,N =V,L or V,H)
Supply Current
(V'N
= OV or Voo)
mAMAX
100
/lAMAX
NOTES:
Guaranteed monotonic over full temperature range and at VDD = +5V and
4 ~VDD = ±10%
+15V
5 DBO-DB7 =OV, WR =CS =OV, VAEF =±10V, for IOUT1
2 FSR (Full Scale Range) =VAEF - 1 LSB
6
DBO-DB7 =Voe, WR =CS =OV, VREF =±10V, for IOUT2
3 USing Internal feedback resistor
Temperature coefficient approximately equals +300ppm/oC
Electncal tests are performed at wafer probe to the limits shown Due to vanatlons In assembly methods and normal Yield loss, Yield after packagmg IS not guaranteed
for standard product dice Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing
11-154
1/86, Rev. A
------------l\fMD
PM-7524 CMOS a-BIT BUFFERED MULTIPLYING D/A CONVERTER
DEFINITIONS
FIGURE 1: PM-7524 Functional Diagram
RESOLUTION
The resolution of a DAC is the number of states (2") that the
full-scale range (FSR) is divided (or resolved) into, where n is
equal to the number of bits. Resolution in no way implies
linearity.
VREF
20kO
RELATIVE ACCURACY
Relative accuracy or end-point nonlinearity is a measure of
the maximum deviation from a straight line passing through
the end-points of the DAC transfer function. It is measured
after adjusting for ideal zero and fUll-scale and is expressed
in % or ppm of full-scale range or (sub) multiples of 1 LSB
GAIN
Ratio of the DAC's external operational amplifier output voltage to the V REF input voltage when using the DAC's internal
feedback resistor.
2Ok"
10k"
20kn
.
2Ok"
2Ok"
QUT2
10k{l
oun
A.B
cs
iNA
PROPAGATION DELAY
The time for the output current to reach 90% of its final value
from a given digital input signal.
SETTLING TIME
Time required for the output function of the DAC to settle to
within 1/2 LSB for a given digital input stimulus, i.e., zero to
full scale.
10ks}
10kll
DB7 (MSa)
DB.
DB.
DBO (LSB)
logic are shown The switches are binarily weighted and
switch the ladder current between IOUT1 and IOUT2 bus lines;
this switching allows a constant current to be maintained in
each resistor leg regardless of the switch state.
EQUIVALENT CIRCUIT ANALYSIS
FEEDTHROUGH ERROR
Error caused by capacitive coupling from V REF to output with
all switches off.
Figure 2 shows an equivalent circuit for the PM-7524 with all
digital inputs Law. The OUT1 and OUT2 leakage current
source is the combination of surface and junction leakages to
the substrate. The 1/256 current source represents the constant 1-bit current drain through the ladder termination resistor. The situation is reversed with all digital inputs HIGH,
i.e., the current output is now switched to the OUT1 terminal.
The output capacitance is dependent upon the digital input
code, and is therefore modulated between the low and high
values.
OUTPUT CAPACITANCE
Capacitance from IOUT1 and IOUT2 terminals to ground.
FIGURE 2: PM-7524 Equivalent Circuit
(All Digital Inputs LOW)
GAIN ERROR
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. Ideal
output is equal to VREF - 1 LSB.
OUTPUT LEAKAGE CURRENT
Current which appears on IOUT1 terminal with all digital
inputs low or on IOUT2 terminal when all inputs are high.
A.B
R .... 'Okn
CIRCUIT DESCRIPTION
. - - - - -.....-~---oOUT'
CIRCUIT INFORMATION
The PM-7524 is an 8-bit multiplying CMOS digital-to-analog
converter with on-board data latches. It is fabricated using a
highly stable thin-film R-2R resistor ladder network and eight
N-channel current switches. A voltage or current reference
and an operational amplifier are all that is required in the
majority of applications.
V AE •
e>--J\II/V-_----_---......- - - - - o O U T 2
Figure 1 shows a simplified circuit of the PM-7524 converter.
The R-2R ladder, current steering switches, and interface
11-155
-~~~~~~~~~~~------~--
- - ------------
1/86, Rev. A
-----------I1fMD
PM-7524 CMOS a·BIT BUFFERED MULTIPLYING D/A CONVERTER
INTERFACE LOGIC
FIGURE 3: Supply Current vs Logic Level
MODE SELECTION
The mode selection is controlled by the CS and WR inputs.
14
1400
TA " +25°C
ALL DIGITAL INPUTS
12
WRITE MODE
The PM-7524 is in the WRITE mode when both the CS and WR
are both LOW; the input latches are transparent and the output
immediately follows the data input logic. See the MODE
SELECTION TABLE.
~
}"
TIED TOO ETHER
ooo~
1
10
Voo
-'+5V
BOO"
}
~
C
F
HOLD MODE
The MODE SELECTION TABLE shows the output results when
either CS or WR is HIGH. The output holds the value corre·
sponding to the last digital inputs prior to CS or WR assuming
the HIGH state.
1200
BOO
'i
400
~
,OO=+15V
4
o
V
o
'"
"-
........
200
i'-.
10
12
o
14
V IN (VOLTS)
MODE SELECTION TABLE
~
WR
MODE
L
L
WRITE
DAC responds to data bus
(DBO - DB7) inputs (trans·
parent)
H
X
HOLD
Data bus (DBO locked out
X
H
HOLD
DAC holds last data present
when Wl'i or~ assumes a
HIGH state
DAC RESPONSE
APPLICATIONS
FIGURE 4: Unipolar Binary Operation
(2-Quadrant Multiplication)
DB7) is
DATA
INPUTS
L = Low State, H = High State, X = Don't Care.
VOUT
cs
w-
WRITE CYCLE TIMING DIAGRAM
NOTES:
1. At AND R2 USED ONLY IF GAIN
GNO
ADJUSTMENT IS REQUIRED.
2 C1 PHASE COMPENSATION (10pF - 15pF)
MAY BE REQUIRED WHEN USING HIGH
SPEED AMPLIFIERS TO PREVENT
RINGING OR OSCILLATION.
TABLE I: Unipolar Binary Code Table
DIGITAL INPUT
MSB
LSB
DATA IN
(DBO - DB7)
-----'
ANALOG OUTPUT
-VREF
(~~ )
0 0 0 0 0 0
-VREF
( 129 )
256
0 0 0 0 0 0 0
-VREF
( 128 )
256
0
-VREF
(~~ )
0 0 0 0 0 0 0
-VREF
(2k)
0 0 0 0 0 0 0 0
-VREF
(
NOTES:
1. AU INPUT SIGNAL RISE AND FALL TIMES
MEASUREDFROM10IAlT080IIJoQFYDD Voo
=+5Y,t,"'t,= 2One; VDD"'+1~
.on..
1,=,,=
2 TlMlNGMEASUREMENTFlEFERENCELEVEL
I8VIH+VIL
2
VREF
--2-
3. tDS+tDHISAPPROXIMATELYCONSTANTAT
145n1 MIN AT +25OC, Voo '" +5Y AND
twr;;
170111 MIN THE PMa7524IB SPECIFIED FOR
A MINIMUM IIJH OF 1Dnl, HOWEVER, IN
APPlICAnONS WHERE IbH> 1Onl,
to. MAY
BE REDUCED UP TO THE LIMIT fDa " 8Sns.
tDH = 8On..
Supply current (100) versus Logic input voltage (V,N) is shown in
Figure 3. This plot shows the supply current for both Voo = +5V
and Voo =+15V.
2~6 )
=0
NOTE:
_
1LSB
11-156
= (2
8)
(VREF)
1
= 2s6
(VREF)
1/86, Rev. A
-----------l~ PM-7524 CMOS 8-BIT BUFFERED MULTIPLYING D/A CONVERTER
FIGURE 5: Bipolar (4-Quadrant) Operation
±10V
(AC OR DC)
VREF
Voo
A5
Your
DATA
INPUTS
I
LSB
11
CS
12
VA
13
OND
NOTES.
1. ADJUST Rl FOR Vo ur " OV AT CODE 10000000.
2. Cl PHASE COMPENSATION (10 - 15pF) MAY BE
REQUIRED IF A11S A HIGH SPEED AMPLIFIER.
OND
FIGURE 7: PM-7524/MC6800 Interface
TABLE II: Bipolar (Offset Binary) Code Table
DIGITAL INPUT
MSB
LSB
ANALOG OUTPUT
AO-A15
(.J£L)
128
o
0 000 0
o
000 000
VMA
o
o
-VREF
I-......----I~
6800
(1~8)
o
000 000
( 127 )
128
o
000 0 0 0 0
( ~)
128
.2t--.......,
II
DO-07
NOTE:
1LSB
1
= (2- ') (VREF) = 128
(VREF)
FIGURE 6: PM-7524/8085A Interface
11-157
1/86, Rev. A
----------I~ PM-7524 CMOS 8-BIT BUFFERED MULTIPLYING DIA CONVERTER
FIGURE 8: Power Generation Connection
FIGURE 9: Divider
(Digitally Controlled Gain)
-::::=+';;,:;;....1
OAT A 9-.....
INPUT "0" 6--+.....--+-1
cso-++-.....+-t
v,
WRo-++.....++-1
>-----<~----o VOUT
v,
EQUATIONS
-YIN
VOUT
Av::
=
----0-
-VOUT
"""'YiN
1
=:
-
0
WHERE. Av
= VOLTAGE GAIN
AND WHERE'
D=D2~7+D;6+
OBO
,.-
DBN = lorD
EXAMPLES
o
o
= 00000000, Av = - AOL (OP AMP)
= 00000001, Av = - 256
0= 10000000,Av =
o
-Ws
=:-2
= 11111111, Av = - ~
CIRCUIT EQUATIONS
V, =: - (VREF)
V2 =
(VAEF )
Vn = - (YREF)
Vn = + (VREF)
+
(D)
(02)
(Dn). n AN ODD INTEGER
(On). n AN EVEN INTEGER
WHERE
D=D:'7+D~6+
OBO
,.-
AND
DBn
= lorO
11-158
1/86, Rev. A
PM-7528
DUAL 8-BIT BUFFERED
MULTIPLYING CMOS D/A CONVERTER
Precision Monolithics Inc.
FEATURES
•
•
•
•
•
•
•
•
•
CROSS REFERENCE
On-Chip Latches For Both DACs
+5V To +15V Single Supply Operation
DACs Matched To 1%
Four-Quadrant Multiplication
TTL/CMOS Compatible
8-Bit Endpoint Linearity (±1/2 LSB)
Full Temperature Operation
Low Power Consumption
Microprocessor Compatible
PMI
TEMPERATURE
RANGE
ADI
PM7528AR
PM7528BR
PM7528BR
AD7528UD
AD7528TD
AD7528SD
MILITARY
PM7528ER
PM7528FR
PM7528FR
AD7528CO
AD7528BO
AD7528AO
INDUSTRIAL
PM7528GP
PM7528HP
PM7528HP
AD7528LN
AD7528KN
AD7528JN
COMMERCIAL
APPLICATIONS
•
•
•
•
•
•
•
Digital Gain/Attenuation Control
Digital Control Of Filter Parameters
Digitally-Controlled Audio Circuits
X-Y Graphics
Digital/Synchro Conversion
Robotics
Ideal For Battery-Operated Equipment
GENERAL DESCRIPTION
The PM-7528 contains two 8-bit multiplying digital-to-analog
converters. Excellent DAC-to-DAC matching and tracking results from monolithic construction. The PM-7528 consists of
two thin-film R-2R resistor-ladder networks, two data latches,
one input buffer, and control logic. Operation from a 5 to 15 volt
single power supply dissipates only 20mW of power.
ORDERING INFORMATIONt
PACKAGE: 20-PIN"
MILITARY'
INDUSTRIAL
COMMERCIAL
RELATIVE
GAIN TEMPERATURE TEMPERATURE TEMPERATURE
ACCURACY ERROR -55°C TO +125°C -25°C TO +85°C DOC TO +7DoC
±1/2 LSB
±1/2 LSB
±2 LSB
±1 LSB
* For devices processed
PM-7528BR
PM-7528AR
PM-7528FR
PM-7528ER
PM-7528HP
PM-7528GP
total compliance to MIL-STO-883, add /883 after
part number Consult factory for 883 data sheet
** Package designation Suffix A Hermetic DIP, Suffix P PlastiC DIp
t All commercial and industrial temperature range parts are available with
burn-In For ordering InformatIOn see 1986 Data Book, Section 2
In
Digital input data is directed into one of the DAC data latches
determined by the DAC selection control line DAC A/DAC B.
The 8-bit wide input data path provides TTL/CMOS compatibility. The data load cycle is similar to the write cycle of a
random access memory. The PM-7528 is bus compatible with
most 8-bit microprocessors, including the 6800, 8080, 8085, and
Z80.
The PM-7528 saves PC board space with the narrow 20-pin 0.3"
wide DIP. A set of internal tracking span resistors is included,
minimizing external parts.
PIN CONNECTIONS
FUNCTIONAL DIAGRAM
20-PIN EPOXY DIP
(P-Suffix)
20-PIN HERMETIC DIP
(R-Suffix)
11-159
1/86, Rev_ A
II
_ _ _ _ _ _ _ _-I~PM-7528 DUAL 8-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C, unless otherwise noted.)
VDD to AGND .................................. OV, +17V
VDD to DGND .................................. OV, +17V
AGND to DGND .............•....•................ VDD
DGND to AGND ................................... VDD
Digital Input Voltage to DGND ...••.....••....•. -0.3\/, VDD
VplN 2, VPIN 20 to AGND .............•.......... -0.3V, VDD
VREF A, VREF S to AGND ........................... ±25V
VRFB A, VRFB S to AGND ........................... ±25V
Power Dissipation (Any Package) to +75°C ........ 450mW
Derate Above +75°C by ......•.•...........•.• 6mWfOC
Operating Temperature Range
AR, SR Versions ............•••....... -55°C to +125°C
ER, FR Versions ...•.................... -25°C to +85°C
Gp, HP Versions .............•••........•• O°C to +70°C
Dice Junction Temperature ...•.•.•....•......•... +150°C
Storage Temperature .•.................. -65°C to +150°C
Lead Temperature (Soldering, 60 sec) .•........... +300°C
CAUTION:
1.
Do not apply voltages higher than VDD or less than GND potential on any
terminal except VREF
The digital control inputs are zener-protected, however, permanent damage
may occur on unprotected units from high-energy electrostatic fields
Keep Units In conductive foam at all times until ready to use
Do not insert this device into powered sockets, remove power before
insertion or removal
4
Use proper anti-static handling procedures,
5
Stresses above those listed under"Absolute Maximum Ratings" may cause
permanent damage to the device
ELECTRICAL CHARACTERISTICS at VDD =+5V, VREF A =VREF S =+10V, OUT A =OUT S =OV; TA =-55°C to +125°C apply for
PM-7528ARISR; TA =-25 0 Cto +85°C apply for PM-7528ER/FR; TA =O°C to +70°C apply for PM-7528GP/HP, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
PM-7528A/E/G
MIN
TYP
MAX
MIN
PM-7528B/F/H
TYP
MAX
UNITS
STATIC ACCURACY
(Note 1)
Resolution
Relative Accuracy
(Note 2)
Differential Nonlinearity
(Note 3)
N
NL
DNL
Full Scale
Gain Error
Bits
GFSE
(Note 4)
TA = +25°C
TA
=
Full Temp. Range
±1/2
±1/2
LSB
±1
±1
LSB
±1
±3
±2
±4
LSB
±0.007
±0.007
%IOC
±50
±400
±50
±400
nA
15
15
kO
±1
%
Gain Temperature
Coefficient
(ll.Gain/ll.Temperature)
(Notes 4, 10)
TCG FS
Output Leakage Current
Out A (Pin 2)/Out B (P," 20)
(NoteS)
'LKG
Input Resistance
(VREF A, VREF B)
(Note 6)
RREF
VREF AIVREF B
(Input Resistance Match)
ll.VREFA, B
TA = +25°C
TA = Full Temp. Range
0.1
±1
01
DIGITAL INPUTS
(Note g)
Digital Input High
V 1NH
Digital Input Low
V1Nl
Input Current
(Note 7)
lIN
Input Capacitance
(Note 10)
C,N
24
2.4
V
08
001
TA = +25°C
TA
=
Full Temp. Range
±1
±10
.001
0.8
V
±1
±10
I'A
DBO-DB7
10
10
WR, CS, DAC A/DAC B
15
15
11-160
pF
1/86, Rev. A
----
~--~-
IfMD
----
---
PM-7528 DUAL B-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTER
ELECTRICAL CHARACTERISTICS at V DD = +5V, VREF A = VREF B= +10V, OUT A
= OUT B = OV; TA = -55°C to +125°C apply for
PM-7528AR/BR; TA =-25°Cto +85°C apply for PM-7528ERlFR; TA = O°Cto +70°C apply for PM-7528GP/HP, unless otherwise noted.
(Continued)
PM-7528A/E/G
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
PM-7528B/F/H
MAX
MIN
TYP
MAX
UNITS
SWITCHING CHARACTERISTICS
(Notes 10, 11)
ChIp Select to
Write Set-Up Time
les
Chip Select to
Wrote Hold TIme
tCH
DAC Select to
Wrote Set-Up TIme
t AS
DAC Select to
Write Hold TIme
tAH
Data ValId to
Write Set-Up Time
tos
Data Valid to
Wrote Hold TIme
tOH
Write Pu Ise Width
tWR
TA
TA
=+25°C
=Full Temp. Range
TA = +25°C
=Full Temp Range
TA =+25°C
TA =Full Temp Range
TA =+25°C
TA =Full Temp. Range
TA =+25°C
TA =Full Temp. Range
TA
TA
TA
=+25°C
=Full Temp
Range
200
230
200
230
ns
20
30
20
30
ns
200
230
200
230
ns
20
30
20
30
ns
110
130
110
130
ns
0
0
ns
180
200
180
200
ns
E2
All DIgital tnputs V,NL or V,NH
mA
100
100
All DIgital Inputs OV or Voo
100
f.lA
AC PERFORMANCE
CHARACTERISTICS
(Note 13)
0
0
~
0
~
~
-
0
Q
DC Supply RejectIon
(;';;-;528 DUAL ii-BiT BUFFERED MULTIPLYING CMOS D/A CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
TOTAL UNADJUSTED ERROR
vs DIGITAL INPUT
1/4
TA ~ 25"C
FULL-SCALE GAIN ERROR
vs TEMPERATURE
RELATIVE ACCURACY
vs REFERENCE VOLTAGE
1/2 ,..-...,--,-,--,--r-""""""T-""'-'-'"
-OJA
015
Voo'" +lSV
Voo '" 1SV
VREF '" +10V
TA = 2S"C
014
1/4
-1/4
1--t--i-t---+-r---t--t-t--t--1
MAXIMUM POSITIVE ERROR
FOR THIS TYPICAL UNIT LINEARITY
TRACKS WITHIN 0 1% BETWEEN
OAe A AND OAe B
013
012
1/4
DAca
-1/4
f--t--i-t--t-I--t--t-t--t--1
64
12.
192
256
-6-4-20
DIGITAL CODE
OUTPUT
LEAKAGE CURRENT
vs TEMPERATURE
•
VAEF
-50
-25
25
50
FEEDTHROUGH vs
FREQUENCY
-10
100
R~ .I,b~~
...
'It
OP-Ol
-40
PHASE RELATIVE
TO PHASE AT 1KHz
VDD=~y
10
ffi
ew
-~
1
-75
:1
....." /~
-50
-25
25
50
75
TEMPERATURE (OC)
100
it
III~
-20
VREF(lN) '" 6
Voo'" 15V
-40
VR~~ 11111
TA '" 2SOC
OIGIT~~IIIINPUT '" 1~?llll111
-60
125
1k
10k
lOOk
~
OP-Ol
III
FREQUENCY (Hz)
11-166
1/
-80
~~~i' 'II
1M
125
VREF = 6 YAMS
RL = lOon
_60
It:on
100
Voo =' ~~U
-20
-20
":=
75
GAIN AND PHASE SHIFT
vs FREQUENCY
WITH RESISTIVE LOAD
AND OP-01 AMPLIFIER
GAIN RELATIVE TO
GAIN AT 1KHz
"~
010
-75
TEMPERATURE (oC)
=-lOV
w
10
REFERENCE VOLTAGE (VOLTS)
10
1000
"0,
~
011
AT EACH REFERENCe VOLTAGE, ALL
DIGITAL CODES WERE TESTED, THEN
THE MAXIMUM ERROR IS PLOTTED HERE
-1/4
1
"«
i""""'- r-..
"
-100
-120
10M
1k
10k
lOOk
1M
10M
FREQUENCY (Hz)
1/86, Rev. A
_ _ _ _ _ _ _ _----1~PM-7528 DUAL a-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs FREQUENCY
Voo
-20
21~~
III
ANALOG CROSSTALK
vs FREQUENCY
Vo~ ~ljM~
I
VREF = 6 VRMS
TA = 2SoC
001
I I
VREFB = 6 VRMS
-20
VOUTA
RATIO = - -
OP-Ol OUTPUT OP AMP
POWER SUPPLY REJECTION
vs TEMPERATURE
+ttHtt-+t++H+\I--+-++ftIIlI
11111~REfB
-40
-40~HH+W~++~~+~H+\I--+~ftIIlI
-60
-60
r-
-80
H-t+I-tttIt--+H:II~/++-ttttlI\t-t+t-ttllll
-
-80
-100
-120
01
10
100
0001
JJ~JlLlL AMPLIFlER~~1-ttHtIII
Voo
FREQUENCY (kHz)
lOOk
1M
-
00001
::::1:k:::::::::I:II:ilL:11111:11'0:01:::::~:::::
10k
4 75V TO 525V= ----'
r--- ~
000001
-75
10M
-50
Vao = 14V TO l6V
-I
-25
I I
25
50
75
lOa
125
TEMPERATURE (OC)
FREQUENCY (Hz)
SUPPLY CURRENT
vs TEMPERATURE
-
Voo
15V
V 1NL ""
5V
=
01
i,.....-'"
001
-75
V
-50
~
-25
....
~INH·r5V f--
25
50
75
100
II
125
TEMPERATURE (OC)
VOLTAGE SWITCHING MODE CHARACTERISTICS
RELATIVE ACCURACY
GAIN AND PHASE
vs FREQUENCY
vs REFERENCE VOLTAGE
......
-10
-20
....
-1 ~--'~;;--I--45
-90
vREF(IN) = 100mV RMS + 2Voc
voo = 15V
DIGIT~fIlIINPUT
10
10
REFERENCE VOLTAGE (VOL TS)
=
'~I~~I1111
100
1000
10000
FREQUENCY (kHz)
11-167
1/86, Rev. A
_ _ _ _ _ _ _ _--1!EMDPM-7528 DUAL 8-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTER
PARAMETER DEFINITIONS
AC FEEDTHROUGH
AC signal due to capacitive coupling from VREF to output with
all switches "off."
RELATIVE ACCURACY
Relative accuracy, or endpoint nonlinearity, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale, and is normally expressed in
LSB's or as a percentage of full scale reading.
INTERFACE LOGIC INFORMATION
DAC SELECTION
Both DAC latches share a common 8-bit input port. The control
input DAC AlDAC B selects which DAC can accept data from
the input port.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
over the operating temperature range ensures monotonicity.
MODE SELECTION
The inputs CS and WR control the operating mode of the
selected DAC. See Mode Selection Table below.
GAIN ERROR
Gain error, or full-scale error, is a measure of the output error
between an ideal DAC and the actual device output. The ideal
full-scale output is VREF minus 1 LSB. Gain error of both DAC's
in the PM-7528 Is adjustable to zero with external resistance.
WRITE MODE
When CS and WR are both low, the selected DAC is in the write
mode. The input data latches of the selected DAC are transparent and its analog output responds to the data on the data bit
lines DBO-DB7.
OUTPUT CAPACITANCE
CapaCitance from OUT A or OUT B to AGND.
HOLD MODE
The selected DAC latch retains the data which was present on
the data lines just priorto CS or WR assuming a high state. Both
analog outputs remain at the values corresponding to the data
in their respective latches.
DIGITAL CHARGE INJECTION
The amount of charge injected from the digital inputs to the
analog output when the inputs change states. This is normally
specified as the area of the glitch in either pAsecs or nVsecs,
depending upon whether the glitch is measured as a current or
voltage signal. Digital charge injection is measured with VREF A,
VREF B = AGND.
MODE SELECTION TABLE
DACAlDACB
CS
WR
DACA
PROPAGATION DELAY
This is a measure of the internal delays of the circuit. It is
defined as the time from a digital input change to the analog
output current reaching 90% of its final value.
CHANNEL-TO-CHANNEL ISOLATION
The portion of input signal from one DAC's reference input
which appears at the output of the other DAC, expressed as
a ratio in dB.
DACB
L
L
L
WRITE
HOLD
H
L
L
HOLD
WRITE
X
H
X
HOLD
HOLD
X
X
H
HOLD
HOLD
L = Low State
x =Don't Care
H = High State
CIRCUIT INFORMATION-D/A SECTION
DIGITAL CROSSTALK
The glitch energy transferred to the output of one converter,
due to a change in digital input code to the other converter,
specified in nVsec.
The PM-7528 contains two identical8-bit multiplying digital-toanalog converters, DAC A and DAC B. Each DAC includes a
stable thin-film R-2R resistor ladder and eight NMOS current
steering switches. Figure 1 shows a simplified equivalent circuit
WRITE CYCLE TIMING DIAGRAM
~S-'I'-'CH)_
CHIP SELECT - - - -....{
'AS-l-'AH
IlACA/0AC B - - - -....{
_
WRiTE
~'WR~
"--
_ _ _ _ _......
DATA IN 10BO-OB7I
VOO
_ _ VOO
~
t='os
y_-----
VOO
-I-
~TA IN STABLE
NOTES
, ALL INPUT SIGNAL RISE AND FALL
t':_H____
X
11-168
TIMES MEASURED FROM 10% TO 90%
OFV oo
Voo· +5V, tr = tf" 2On5,
voo
Voo· +15V, tr = tf = 40ns
2 TIMING MEASUREMENT REFERENCE
LEVEL IS V 1H + V1l
2
1/86, Rev. A
----------1~ PM-752a DUAL a-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTER
of either DAC. The inverted R-2R ladder takes a voltage or
current reference and divides it in a binary manner among the
eight current steering switches. The number of switches
selected to the output (OUT) add their currents together
forming an analog output current representation of the switch
selection. The DAC OUT and analog ground (AGND) should be
maintained at the same voltage for proper operation.
1 LSB of the reference current (lREF)' COUT is the parallel
combination of the NMOS current steering switches. The value
of COUT depends on the number of switches connected to the
output. The range of COUT is 50pF to 120pF maximum. The
equivalent output resistance Ro varies with input code from
O.8R to 3R, where R is the nominal ladder resistor of the R-2R
ladder.
CIRCUIT INFORMATION-DIGITAL SECTION
The digital inputs provide TTL input compatibility (VINH = 2.4,
VINL = O.8V) when the PM-7528 operates with Voo of +5V. The
digital inputs effect the amount of quiescent supply current as
shown in Figure 3. Peak supply current occurs as the digital
input (VIN) passes through the transition voltage. Maintaining
the digital input voltages as close as possible to the supplies
(Voo and DGND) minimizes supply current consumption.
When operating the PM-7528 from CMOS logic the digital
inputs are driven very close to the supply ralls, minimizing
power consumption.
2"
L+~44-r~~~t-~~-~~--oOUT
~-++-~:~~~--+~~~--~AGNO
OAC DA4A LATCHES
AND DRIVERS
Digital input protection from electrostatic discharge and electrostatic buildup occurs in the input network shown in Figure 4.
FIGURE 1: Simplified functional circuit for DAC A or DAC B.
EQUIVALENT CIRCUIT ANALYSIS
30
The equivalent circuit of DAC A shown in Figure 2 is similar to
DAC B. DAC A and DAC B both share the analog ground pin 1
(AGND). With all digital inputs high, the reference current flows
to OUT A. A small leakage current (lLEAKAGE) flows across
internal junctions, doubling every 10°C. The R-2R ladder
termination resistor generates a constant 11256 current which is
TA '" 25 Q C
ALL DIGITAL INPUTS
TIED TOGETHER
,L:r- Voo
OD
V
-----,
VREF C>--'I,/Vv-_--.......p----__ VOUT
ANALOG OUTPUT
(DAC A or DAC B)
~~~~(7)o-------+-------.
127 )
+VIN ( 128
+15V
10000001
10000000
o
01111111
00000001
127 )
-VIN ( 128
00000000
128 )
-VIN ( 128
FIGURE 7: PM-7528 in Single Supply, Voltage
Switching Mode
11-172
1/86, Rev. A
_ _ _ _ _ _ _--tIf.Mi)PM-752a DUAL a-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTER
PROGRAMMABLE WINDOW COMPARATOR
input signal range depends on the reference and polarity. that Is
the test input range is 0 to minus VREF' The A and B data latches
are programmed with the upper and lower test limits. A signal
within the programmed limits will drive the output to logic high.
A programmable window-comparator In Figure 8 will determine
if voltage inputs applied to the DAC feedback resistors are
within limits programmed Into the PM-7528 data latches. The
~~~~~:~;
<>-.,....---------,
VDD
RFBA
3
'7
1kn
DATA INPUTS
PASS/FJ!JC
OUTPUT
1 AGNO
C1-+--+---'~
WI'!_+_I-.....:.:'8+J
cro:A/DAC B-+-I---'+J
19 RFe B
FIGURE 8: Digitally Programmable Window Comparator (Upper and Lower Limit Detector).
MICROPROCESSOR INTERFACE
I
DACA}
CPU
6800
ADDRESS BUS
A8-A1S
ADDRESS BUS
AO-A15
IDACA}
CPU
8085
PM-752S·
PM-762S"
IOAe B)
8
ALE
"A
;;r
ADDR/DATA BUS
ADO-AD7
DATA BUS
.. ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY.
·ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY
.. A .. DECODED 7528 ADQR OAC A
A + 1 " DECODED 7528 ADDR OAC B
DECODED 7628 ADDR OAC A
A + , .. DECODED 7528 ADDR OAC B
NOTE
8085 INSTRUCTION SHLD (STORE H 8t L DIRECT) CAN UPDATE
BOTH DACSWITH DATA FROM HAND L REGISTERS.
FIGURE 9: PM-7528 Dual DAC to 6800 CPU Interface.
FIGURE 10: PM-7528 Dual DAC to 8085 CPU Interlace.
11-173
_.- - - - -
--------
1/86, Rev. A
_ _ _ _ _ _ _ _--1~PM-7528 DUAL B-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTER
DIGITALLY CONTROLLED SIGNAL ATTENUATOR
generate logarithmic attenuation, Table 4 was generated based
on the equation:
Digital Input = 256 X exp (-Attenuat ion (dB))
2o
Figure 11 shows the PM-7528 configured as a two-channel
programmable attenuator. Applications include stereo, audio,
and telephone signal-level control applications. In order to
Voo <>-_--"7'"
DBa
PM-7628
DB7
/ ' - - - -____
\ r - - - -.......
1+''''5--------oCll
1+'",6- - - - - - - - O W R
I+:...-..-------og~~
:1
1---r:'S:...-..--------oV rN B
VourB
AGNO
1
DGND
5
FIGURE 11: Digitally-Controlled Dual Telephone Attenuator.
TABLE 4: Attenuation vs. DAC A, DAC B Code for the Circuit of Figure 11
ATTN. dB
DAC INPUT CODE
CODE IN
DECIMAL
ATTN. dB
DAC INPUT CODE
CODE IN
DECIMAL
0
11111111
255
8.0
01100110
102
0.5
11110010
242
8.5
01100000
96
1.0
11100100
228
9.0
01011011
91
1.5
11010111
215
9.5
01010110
86
2.0
11001011
203
10.0
01010001
81
2.5
11000000
192
10.5
01001100
76
3.0
10110101
181
11.0
01001000
72
3.5
10101011
171
11.5
01000100
68
4.0
10100010
162
12.0
01000000
64
4.5
10011000
152
12.5
00111101
61
5.0
10010000
144
13.0
00111001
57
5.5
10001000
136
13.5
00110110
54
6.0
10000000
128
14.0
00110011
51
6.5
01111001
121
14.5
00110000
48
7.0
01110010
114
15.0
00101110
46
7.5
01101100
108
15.5
00101011
43
11-174
1/86, Rev. A
PM-7S33
CMOS LOW COST lO-BIT MULTIPLYING
D/A CONVERTER
PreciSIon MOl1oJ-ithics Inc.
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
The PM-7533 IS a 10-bit 4-quadrant multiplying DAC. It is
manufactured using thin film on an oxide-isolated, silicongate, monolithic CMOS wafer fabrication process. PMI's
advanced thin-film resistor processing provides true 10-bit
linearity and excellent long-term stability achieved without
laser trimming.
10-Bit Resolution
Full Four-Quadrant Multiplication
Nonlinearity: 1/2 or 1 LSB
TTL/CMOS Compatible
Improved Gain Error and Linearity Error from +5V to +15V
Low Power Consumption
Low Feedthrough Error
Low Cost
AD7520 and AD7533 Replacement
Full Temperature Operation
APPLICATIONS
•
•
•
•
•
•
•
•
•
Digital/Synchro Conversion
Programmable Gain Amplifiers
Ratiometric A/D Conversion
Function Generator
CRT Graphics Generator
Digitally-Controlled Attenuator
Digitally-Controlled Power Supplies
Digital Filters
Linear Automatic Gain Control
The PM-7533 is pin and function equivalent to the AD7520
and AD7533.
The PMI PM-7533 applications flexibility allows direct interface to TTL or CMOS circuitry and operation from +5V to
+15V power supplies. Output scaling is provided by the internal feedback resistor and an external op amp; both positive
and negative reference voltages can be accommodated.
PIN CONNECTIONS
16-PIN EPOXY DIP
(P-Suffix)
16-PIN HERMETIC DIP
(Q-Suffix)
ORDERING INFORMATIONt
PACKAGE: 16-PIN"
NONLINEARITY
±O 1% (±1 LSB)
±O 05% (±1/2 LSB)
INDUSTRIAL
COMMERCIAL
MILITARY'
TEMPERATURE TEMPERATURE TEMPERATURE
-55'C 10 +125'C -25'C 10 +85'C
D'C 10 +7D'C
PM7533BQ
PM7533AQ
PM7533FQ
PM7533EQ
PM7533HP
PM7533GP
'For deVices processed In total compliance to MIL-STD-883, add 1883 after
part number Consult factory for 883 data sheet
t All commerCial and industrial temperature range parts are available with
burn-In. For ordering information see 1986 Data Book, Section 2
"Package Designation' Suffix Q Hermetic DIP, Suffix P Epoxy DIP
FUNCTIONAL DIAGRAM
10kn
20HZ
10kn
10kn
20kn
2Ok"
20kn
20kn
CROSS REFERENCE
TEMPERATURE
RANGE
PMI
ADI
PM7533AQ
PM7533BQ
PM7533BQ
AD7533UD
AD7533TD
AD7533SD
PM7533EQ
PM7533FQ
PM7533FQ
AD7533CD
AD7533BD
AD7533AD
INDUSTRIAL
PM7533GP
PM7533HP
PM7533HP
AD7533LN
AD7533KN
AD7533JN
COMMERCIAL
L--+-+.......-hi----4.....",>--++-*----Q 'oun
'--'c--.......-+----ct-;--~~-+-;_......-:-:~-o 'OUT1
MILITARY
AFEEDBACK
BIT 1 (MSa)
BIT 2
BIT 3
BIT 10 (LSB)
DIGITAL INPUTS (OTL/TTL/CMOS COMPATIBLE)
(SWITCHES SHOWN FOR DIGITAL INPUTS "HIGH")
11-175
1/86, Rev. A
---------t1EMD
PM·7533 CMOS LOW COST 1C1·BIT MULTIPLYING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS (TA = +25°C, unless
otherwise noted)
Voo (to GND) . " ........................... -0.3V, +17V
VREF (to GND) .................................... ±25V
RFB (to GND) . " . " .•• " " . " " . " " " " " " " " . ±25V
Digital Input Voltage Range ••••••••••.••.•• -0.3V to Voo
Output Voltage (Pin 1, Pin 2) ••.••••••.••••• -0.3V to Voo
Power Dissipation (Package)
Ceramic (Suffix Q)
To +70°C ••••..••••.•.•.•••••.•..••••.•••.• 450mW
Derates Above +75°C By ••••••••..•••••••• 6mW/oC
Plastic (Suffix P)
To +70°C •...••.•••••••••••••••••••.••••••• 670mW
Derates Above +70°C By ••.•••••.••••••.. 8.3mW/oC
Operating Temperature Range
Military (AQ, BQ Versions) •••••••.••• -55°C to +125°C
Industrial (EQ, FQ Versions) ••.••..•.•. -25°C to +85°C
Commercial (GP, HP Versions) ..••..•..• O°C to +70°C
Dice Junction Temperature .•••••.•••••••••••••• +150°C
Storage Temperature •••.••••••••••••.. -65°C to +150°C
Lead Temperature (Soldering, 60 sec) •..•.•.••.•. +300°C
CAUTION
1. Do not apply voltages higher than Vee or less than GND potential on any
terminal except VAEF (Pin 1S) and RFB (Pin 16)
2. The dIgital control Inputs are zener protected. however, permanent
damage may occur on unconnected Units from high energy electrostatic
fields Keep units in conductive foam at all tImes untIl ready to use
Use proper anti-stallc handling procedures
4. Absolute MaXImum Ratings apply to both packaged deVIces and DICE
Stresses above those hsted under Absolute Maximum Ratings may cause
permanent damage to the deVIce
ELECTRICAL CHARACTERISTICS at VDD = +15V, VREF = +10V, AGND = DGND = OV, VOUT1 = VOUT2 = OV, TA = -55°C
to +125°C apply for PM·7533AQ/BQ, TA = -25°C to +85°C apply for PM-7533EQ/FQ, TA = O°C to +70°C apply for
PM-7533GP/HP, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
PM-7533A/E/G
PM-7533B/F/H
MIN
MIN
TYP
MAX
TVP
MAX
UNITS
STATIC ACCURACY
ResolutIon
10
Relative Accuracy
(Note 1)
10
BIts
±O.OS
±01
%FSR
TA =+2S'C
TA = Full Temp. Range
±1.4
±1.S
±1.4
±1S
%FS
PSRR
TA =+2S'C
TA = Full Temp. Range
O.OOS
0008
O.OOS
0.008
%/%
Output Leakage Current
loun (Pin 1) (Note 6)
ILKG1
TA =+2S'C
TA= Full Temp Range
±SO
±200
±SO
±200
nA
Output Leakage Current
IOUT2 (Pin 2) (Note 7)
I LKG2
TA = +2S'C
TA = Full Temp. Range
±SO
±200
±SO
±200
nA
ts
TA = +2S'C (Note 10)
TA = Full Temp. Range
600
800
600
800
ns
TA =+2S'C
TA = Full Temp. Range
±O.OS
±0.1
±O.OS
±01
%FSR
20
kO
Gain Error
(Notes 2, 3)
Power Supply Rejection
~
1.5
0.5
--
~
~
§ -0.'
~
.......
1.0
0.'
"
-1.0
_10~_~_~_~_-L_-L_~
o
±2
±a
±4
±S
±10
-1.6
258
0
±12
0
1024
768
10
0
VREP (VOLTS)
DIGITAL CODe (DECIMAL)
Voo (VOL TS)
GAIN ERROR vs VREF
RELATIVE ACCURACY
(NONLINEARITY) VI
DIGITAL CODE
LINEARITY ERROR va
SUPPLY VOLTAGE
1.0...--..,...--,--..,...-.....---,-.....,
TA .. +2SoC
16
2.0
1.5
TA " +25°C
Veo" +15V
Veo • +6V TO +16V
1.0
DIGITAL INPUT-,,11,,1111
~>
:i
V REF • +lav
-- --
0.6
=
u
~
:iw
>
~
-0.5
512
~
\--t--+--+--+--t---i
-0.5
=
1.5
1.0
\
0.5
-1.0
-100~-±~2-~±4-~±6---±~8--±~10~-±~'2
-1.5
o
512
256
VAEF (VOLTS)
00
1024
768
10
DIGITAl. CODE (DECIMAL)
LOGIC INPUT THRESHOLD
VOLTAGE va
SUPPLY VOLTAGE (VDD)
VREF FREQUENCY
RESPONSE
12
TA ' +~'Jl~
Veo" +15V
15
Voo (VOLTS)
16
""'
TA = +25~C
V REF =+lOV
VREF" 10V PEAK AC
DIGITAL INPUT = 1111",,11
AI. = 100n
12
-3
-6
o
-12
0001
001
0.1
10
10
o
V,NH '"
2.4Y"
V'NL •
0.8~"""""'... ...
10
15
20
Veo (VOLTS)
FREQUENCY (MHz)
11-180
1/86, Rev. A
_ _ _ _ _ _ _ _--fIfMDPM-7533 CMOS LOW COST 10-BIT MULTIPLYING D/A CONVERTER
DEFINITIONS
RESOLUTION
The resolution of a DAC is the number of states (2") that the
full-scale range (FSR) is divided (or resolved) into, where n is
equal to the number of bits. Resolution in no way implies
linearity.
RELATIVE ACCURACY
Relative accuracy or end-point (nonlinearity) is a measure of
the maximum deviation from a straight line passing through
the end-points of the DAC transfer function. It is measured
after adjusting for ideal zero and full-scale and is expressed
in % or ppm of full-scale range or (sub) multiples of 1 LSB.
controlled by CMOS inverters. Most applications require the
addition of only an operational amplifier and a current or
voltage reference.
An inverted R-2R ladder network in a simplified D/A converter circuit is shown in Figure 1. The current through each
ladder leg is switched between loun and IOUT2 under the
control of the digital inputs. This allows a constant current to
be maintained in each ladder leg regardless of the digitalinput switch states.
10kO
ZOkn
SETTLING TIME
Time required for the output function of the DAC to settle to
within 1/2 LSB for a given digital input stimulus, i.e., zero to
full scale.
OUTPUT LEAKAGE CURRENT
Current which appears on IOUT1 terminal with all digital
inputs low or on IOUT2 terminal when all inputs are high.
CIRCUIT DESCRIPTION
The PM-7533 isa 10-bit multiplying D/A converter. It consists
of a silicon-chrome thin-film R-2R resistor ladder network
and ten pairs of NMOS current steering switches, all on a
monolithic chip. The NMOS current steering switches are
20kO
20kO
20kO
'--++-......-++-.......'<'-++-......- - 0 0 'OUT2
L.....f--.......;--~:-"'*-~-...-:::-::-<> 'OUT1
RFEEDBACK
BIT 1 (MSS)
GAIN ERROR
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output.
OUTPUT CAPACITANCE
Capacitance from loun and IOUT2 terminals to ground.
20kn
810
GAIN
Ratio of the DAC's external operational amplifier output
voltage to the VREF input voltage when using the DAC's
internal feedback resistor.
FEEDTHROUGH ERROR
Error caused by capacitive coupling from VREFtO output with
all switches off.
10kO
10kSl
BIT 2
BIT 3
BIT 10 (LSB)
DIGITAL. INPUTS (OTl/TTL/CMOS COMPATIBLE)
(SWITCHES SHOWN FOR DIGITAL INPUTS "HIGH'"
FIGURE 1: SIMPLIFIED DAC CIRCUIT
Figure 2 shows one of ten digital input CMOS inverters
driving an NMOS switch. The size of devices 1, 2, and 3 are
optimized to make the digital inputs DTL/TTL/CMOS compatible over the full military temperature range. The input
stage drives the two inverters (4, 5) and (6, 7), which drives
the two NMOS switches (8 and 9). The switch "ON" resistances are binarily-scaled so that the voltage drop across
each switch is the same; that is, switch S1 in Figure 1 (8 and 9
of Figure 2) was designed foran "ON" resistance of 20 ohms,
switch S2 for40 ohms, etc. With a 10V reference input, switch
S1 current is 0.5mA, switch S2 is 0.25mA, etc. This will
maintain a constant 10mV drop across each switch. It is
essential that each switch voltage drop be equal so that the
D/A converter accuracy is maintained.
v+------...----~--...--
t TO R-2R RESISTOR LADOER
IOUT2
IOUT1
FIGURE 2: CMOS SWITCH
11-181
1/86, Rev_ A
I
----------l~
PM-7533 CMOS LOW COST 10-BIT MULTIPLYING D/A CONVERTER
EQUIVALENT CIRCUIT ANALYSIS
Figures 3 and 4 show equivalent circuits of the DAC with all
digital inputs high and low respectively. With all digital inputs
in the high state as shown in Figure 3, the reference current is
switched to the IOUT1 terminal, and the IOUT2 terminal is
open-circuited. Only the output capacitance, surface,
leakages, and junction leakages appear at the I OUT2 terminal.
The 1/1024 current source is a constant 1-bit current drain
through the termination resistor of the R-2R ladder network.
The ILEAKAGE current source represents a combination of
surface and junction leakages to the substrate. The "ON"
capacitance of the output NMOS switch is higher on the
IOUT1 terminal when all digital inputs are high (MOS transistor gate capacitance increases with applied gate voltage).
RFEEDBACK
""'10kn
o-_N'-_---.......p_---_-.....---<>'oun
V REF
r----_-----IY-_---.......
V REF
DB9-DBO
NOTES
1 R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED
2 C1 MAY BE REQUIRED WHEN USING HIGH SPEED OP AMPS
FIGURE 4: EQUIVALENT DAC CIRCUIT
(All digital Inputs LOW).
FIGURE 5: UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
11-182
1/86, Rev. A
-----------l1fHD
PM-7533 CMOS LOW COST 10-BIT MULTIPLYING D/A CONVERTER
are set to 1000000000 and adjusting R1 for a zero output
voltage (less than 10% of 1 LS8). Resistors R3, R4 and R5
must be selected for matching and tracking in order to keep
offset and full scale errors to a minimum. Resistors R1 and R2
temperature coefficients must be taken into account if they
are used C1 phase compensation capacitor may not be
needed and should be selected empirically. The digital Input
code versus analog output voltage is shown in Table II.
TABLE I: UNIPOLAR BINARY CODE TABLE
DIGITAL INPUT
MSB
LSB
NOMINAL ANALOG OUTPUT
(VOUT as shown in Figure 5)
( 1023)
1024
o
0 0 0 0 0 0 0
( 513 )
1024
o
0 0 0 0 0 0 0 0
( 512 )
1024
TABLE II: BIPOLAR (OFFSET BINARY) CODE TABLE
DIGITAL INPUT
MSB
LSB
( 511 )
1024
o
NOMINAL ANALOG OUTPUT
(VOUT as shown in Figure 6)
(~)
512
1 1 1
o
0 0 0 0 0 0 0 0
-VREF
(_1_)
o
0 0 0 0 0 0 0 0 0
-VREF
(~)
1024
1024
o
(5~2
0 0 0 0 0 0 0
o
o
00000 0 0 0 0
NOTES:
1 Nominal full scale for the CirCUit of Figure 5 IS given by
1023 )
FS ~ ~VAEF ( 1024
2 Nominal LSB magnitude for the Circuit of Figure 5
LSB
IS
o
Figure 6 shows a simple bipolar output circuit using the
PM-7533 and a PMI OP-215 dual op amp. The circuit uses
offset binary coding and a fixed DC voltage for VREF.
Digitally-controlled attenuation of an AC signal occurs when
the signal is used as the signal source at V REF . Negative
output full-scale is adj usted by setting the digital inputs to all
zeros and adjusting the value of the VREF voltage or R5. The
zero-scale output voltage is adjusted while the digital inputs
15
5~2 )
000 0 0 000
(~)
512
000 0 0 0 000 0
(~)
512
o
VIN
(
given by
~ VAEF (1~24) or VAEF (2-°)
)
NOTES:
1 Nominal full scale for the Circuit of Figure 6 IS given by
FSR
~ VAEF (~~;)
2 Nominal LSB magnitude for the
LSB
CircUit
of Figure 6
IS
given by
~ VAEF (5~2)
III
V REF
~~n
V OUT
DATA INPUT
FIGURE 6: BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)
11-183
1/86, Rev. A
---------I~ PM-7533 CMOS LOW COST 10-BIT MULTIPLYING D/A CONVERTER
The PM-7533 may be used in the voltage output operation as
shown in Figure 7. This circuit configuration will lend itself to
single-supply operation because signal inversion does not
occur. The output should be buffered due to its high output
resistance (10kfl) to prevent loading errors. The reference
voltage should be kept to +1.5 volts maximum to keep
nonlinearity errors to less than 1 LSB as shown in Figure 8.
TA = +2SoC
Vao
By connecting the DAC in the feedback of an op amp as
shown in Figure 9, the circuit behaves as a programmable
gain amplifier (analog/digital divider). The transfer function is:
-1
Vo= (~+~V: . . ~ )
2'
22
2'0
-2
=+5V
~~
o
where A, ... AlO assumes a value of 1 or O.
256
512
768
1024
DIGITAL CODe (DECIMAL)
FIGURE 8: VOLTAGE MODE
+5V
V,N
0-------.,
DIGITAL INPUT {OJ
(±10mV TO ±lOV
RANGE
DEPENDING ON
GAIN SETTING)
PM-7533
NOTES
>----.....-oVOUT =-VIN X 0210
1 V REF ";;;+1 5V TO KEEP NONLINEARITY ERRORS < 1 LSB
2 ROUT"" 10kn THIS HIGH OUTPUT RESISTANCE SHOULD
BE BUFFERED TO PREVENT LOADING ERRORS
3 THIS CIRCUIT WILL LEND ITSELF TO SINGLE SUPPLY
OPERATION
(±lOV RANGE)
o
FIGURE 7: VOLTAGE OUTPUT OPERATION
1023
512
256
GAIN TABLE
AV (VourIVIN)
-100097
-2
-4
-512
-1024
OPEN LOOP
FIGURE 9: PROGRAMMABLE GAIN AMPLIFIER
11-184
1/86, Rev. A
PM-7541
CMOS 12-BIT MONOLITHIC MULTIPLYING
D/A CONVERTER
Precision MOl1olithics Inc.
FEATURES
•
•
•
•
•
•
•
•
•
•
CROSS REFERENCE
Full Four-Quadrant Multiplication
12-Bit Endpoint Linearity (±1/2 LSB)
Pretrimmed Gain
TTL/CMOS Compatible
Low Power Consumption
Low Feedthrough Error
Direct Replacement for AD7521 and AD7541
Superior Power Supply Rejection from +5V to +15V
Low Gain and Linearity Tempcos (TYP 2ppm of FSR/°C)
Latch-Up Resistant
PMI
TEMPERATURE
RANGE
ADI
PM7541AX
PM7541BX
AD7541TD
AD7541SD
MILITARY
PM7541EX
PM7541FX
AD7541BD
AD7541AD
INDUSTRIAL
PM7541GP
PM7541HP
AD7541KN
AD7541JN
COMMERCIAL
GENERAL DESCRIPTION
The PMI PM-7541 is a 12-bit, 4-quadrant multiplying digital-toanalog converter. It is manufactured using an advanced oxideisolated, silicon-gate, monolithic CMOS technology.
APPLICATIONS
•
•
•
•
•
•
•
•
Digltal/Synchro Conversion
Programmable Amplifiers
Ratiometric AID Conversion
Function Generator
CRT Graphics Generator
Digitally-Controlled Attenuator
Digitally-Controlled Power Supplies
Digital Filters
Laser-trimmed thin-film resistors on CMOS circuitry provide
true 12-bit linearity and excellent absolute accuracy. The low
power dissipation, together with NMOS temperature-compensating switches, assures the performance over the full temperature range. It is a pin-compatible replacement for Analog
Devices AD7521 and AD7541 with equal or better performance.
PIN CONNECTIONS
ORDERING INFORMATIONt
PACKAGE: 18-PIW·
NONLINEARITY
1LSB
112 LSB
MILITARY·
INDUSTRIAL
COMMERCIAL
TEMPERATURE TEMPERATURE TEMPERATURE
-SS·C TO +12S·C -2S·C TO +8S·C O·C TO +70·C
PM7541BX
PM7541AX
PM7541FX
PM7541EX
18-PIN EPOXY DIP
(P-Suffix)
PM7541HP
PM7541GP
• For devices processed In total compliance to MIL-STD-883, add 1883 after
part number. Consult factory for 883 data sheet.
(also available in Side Braze-XB)
t All commerCial and industrial temperature range parts are available with
burn-in For ordering information see 1986 Data Book, Section 2.
** Package Designation"
Suffix X Hermetic DIP (XB - Side Braze)
Suffix P: Epoxy DIP
18-PIN HERMETIC DIP
(X-Suffix)
FUNCTIONAL DIAGRAM
20kn
20kn
20kS"!
20kn
20kH
20kn
SPOT
NMOS
SWITCHES
'--+-+.......--f-f-4---r,'--++......-H------ 'OUT!
RFEEDBACK
BIT 1 (MSB)
BIT 2
81T3
BIT 12 (LSB)
DIGITAL INPUTS (OTL/TTL/CMOS COMPATIBLE)
(SWITCHES SHOWN FOR DIGITAL INPUTS "HIGH")
11-190
1/86, Rev. A
----------I!EHD
PM-7541 CMOS 12-BIT MONOLITHIC MULTIPLYING D/A CONVERTER
FIGURE 2: CMOS SWITCH
v+------~----~--~--
+TO R-2R RESISTOR LADDER
IOUT2
One of the twelve CMOS switches is shown in Figure 2. The
digital input stage, devices 1, 2, and 3, drives the two inverters,
devices 4,5,6, and 7; these inverters in turn drive the two output
current steering switches, devices 8 and 9. Devices 1, 2, and 3
are designed such that the digital control inputs are DTL, TTL,
and CMOS compatible overthe full military temperature range.
loun
FIGURE 4: PM-7541 EQUIVALENT CIRCUIT
(ALL DIGITAL INPUTS HIGH)
RFEEDBACK
R = 10kn
The twelve output current-steering switches are in series with
the R-2R resistor ladder, and therefore, can introduce bit errors.
It is essential then, that the switch "ON" resistance be binarily
scaled so that the voltage drop across each switch remains
constant. If, for example, switch 1 of Figure 1 was designed with
an "ON" resistance of 10 ohms, switch 2 for 20 ohms, etc., then
with a 10 volt reference Input, the current through sWitch 1 IS
0.5mA, switch 2 is 0.25mA, etc., a constant 5mV drop will then
be maintained across each switch.
O--¥W~----.......- - - -.....-
.....---OIOUT1
V REF
, - - - - -. . . .- - - - _ Q 10UT2
EQUIVALENT CIRCUIT ANALYSIS
Figures 3 and 4 show the equivalent circUits for all digital Inputs
LOW and HIGH respectively. The reference current IS switched
to IOUT2 when all inputs are LOW and IOUT1 when Inputs are
HIGH. The ILEAKAGE current source IS the combination of
surface and Junction leakages to the substrate, the 1/4096
current source represents the constant 1-bit current drain
through the ladder terminating resistor. The output capacitance
is dependent upon the digital Input code, and IS therefore
modulated between the low and high values.
DYNAMIC PERFORMANCE
OUTPUT IMPEDANCE
The output resistance, as In the case of the output capacitance,
IS also modulated by the digital input code. The resistance
looking back Into the IOUT1 terminal, may be anywhere
between 10kfl (the feedback resistor alone when all digital
Inputs are low) and 7.5kfl (the feedback resistor In parallel with
approximately 30kfl of the R-2R ladder network resistance
when any single bit logiC IS high). The static accuracy and
dynamic performance will be affected by thiS modulation. The
gain and phase stability of the output amplifier, board layout,
and power supply decoupllng will all affect the dynamiC
performance of the PM-7541. The use of a compensation
capacitor may be reqUired when high-speed operational
amplifiers are used It may be connected across the amplifiers
feedback resistor to provide the necessary phase compensation
to Critically damp the output.
FIGURE 3: PM-7541 EQUIVALENT CIRCUIT
(ALL INPUTS LOW)
RFEEDBACK
R = 10kn
.....- - Q 'oun
r----~--
II
The considerations when using high-speed amplifiers are:
1. Phase Compensation (See Figures 5 and 6).
2. Power supply decoupling at the device socket and use of
proper grounding techniques.
c>--A/'o/I.--..----....- - - -.....- - - - - o I O U T 2
1/86, Rev. A
11-191
~~~~
-----
-----~-
----------
-----------l1fH!) PM-7541 CMOS 12-BIT MONOLITHIC MULTIPLYING D/A CONVERTER
APPLICATIONS INFORMATION
Unused digital inputs must always be grounded or taken to
Voo; this will prevent noise from triggering the high impedance
digital input resulting in output errors. It is also recommended
that the used digital inputs be taken to ground or Voo via a high
value (1 MO) resistor; this will prevent the accumulation of static
charge whenever the PC card is disconnected from the system.
APPLICATION TIPS
Linearity depends upon the potential of loun and IOUT2 (pins 1
and 2) being exactly equal to GND (pin 3). In most applications,
the DAC is connected to an external op amp with its non inverting input tied to ground, see Figures 5 and 6. The amplifier
selected should have a low input bias current and low drift over
temperature. The amplifier's Input offset voltage should be
nulled to less than ±200/lV (less than 10% of 1 LS8).
OUTPUT AMPLIFIER CONSIDERATIONS
For low speed or static applications, AC specifications of the
amplifier are not very critical. In high-speed applications, slew
rate, settling time, open-loop gain, and gain/phase margin
specifications of the amplifier should be selected forthe desired
performance. It has already been pOinted out that an offset can
be caused by including the usual bias current compensation
resistor in the amplifier's non inverting input-terminal. This
resistor should not be used. Instead, the amplifier should have a
bias current which is low overthe temperature range of interest.
The operational amplifiers usual bias current compensation
resistor in the non inverting input should not be used, the input
should be connected directly to ground with a low-resistance
wire. This resistor can cause a variable offset voltage contributing an error. All pins going to ground should be taken to a
common point to avoid ground loops. The Voo power supply
should have a low noise level and not have transients greater
than +17V.
FIGURE 5: UNIPOLAR BINARY OPERATION (2-QUADRANT)
-15V
FIGURE 6: UNIPOLAR BINARY OPERATION (2-QUADRANT)
R1
VREF
-lOY
BIT 1
(MSS)
r-*".....,I::-.,A FEEDBACK
1--"""'...---,-------,
R2
l1d1
'oun
BIT 12
(LSBj
-15V
11-192
1/86, Rev. A
-----------l1fMD
PM-7541 CMOS 12-BIT MONOLITHIC MULTIPLYING D/A CONVERTER
The static accuracy is affected by the variation in the DAC's
output resistance. This variation is best illustrated by using the
circuit of Figure 8 and the equation:
Error Voltage = Vos (1
+ :~B)
where Ro = function of digital code.
Ro "" 1OkO for more than 4-bits of logic 1.
Ro "" 30kO for any single bit logic 1.
Therefore, the offset gain varies as follows:
At code 001111111111: VERROR
1
=Vos
( 1 + 10kO)
10kO
UNIPOLAR BINARY OPERATION (2-QUADRANT)
The circuits of Figures 5 and 6 can either be used as a fixed
reference D/A converter, or as an attenuator with an AC input
voltage. I n the fixed reference mode, the DAC provides an
analog output voltage in the range of zero to plus or minus VREF ,
depending on VREF polarity. The reference input voltage can
range between -20V to +20V; this is due to the ability of VREF
being able to exceed VDD , the limiting factor being the op amp
voltage range. Table 1 shows the code relationship for the
circuit of Figure 6. R1 can be omitted with a resulting maximum
gain error of 0.3% of full scale.
=2 Vos
Table 1: Code Table for Circuit of Figure 6
.
_
(
10kO) _ 4 \,(
At code 010000000000. VERROR 2 - Vos 1 + 30kO -:3 os
DIGITAL INPUT
111111111111
100000000000
011111111111
000000000000
The error difference is 2/3 Vos.
Since one LSB has a weight (for VREF = +10V) of 2.5mV for the
PM-7541 DAC, it is clearly important that Vos be nulled, either
using the amplifier's nulling pins or an external network.
APPLICATIONS
Figures 5, 6, and 7 show simple unipolar and bipolar circuits
with their associated waveforms using the PM-7541 and two
PMI types of output amplifiers. A small feedback capacitor
should be used across the amplifier to help prevent overshoot
and ringing when using high-speed op amps. Resistor R1 is
used totrimforfull scale, lowtempco (approximately 50ppm/°C)
resistors or trim pots should be selected when gain adjustments
are required.
o
BIPOLAR BINARY OPERATION (FOUR-QUADRANT)
The recommended circuit and code relationship is shown in
Figure 7 and Table 2. The digital Input is offset binary coded and
multiplies VREF per Table 2. Resistors R3 and R4 should beequal
within 0.1% at all temperatures, but need not track the resistors
within the PM-7541. The network comprised of R5, R6, and R7
sums 1/2 LSB of current into IOUT2 to ensure correct coding at
zero. R1 can be adjusted to produce the outputs shown in Table
2. However, when the application permits it, R1 and R2 should
be omitted. The maximum gain error in this condition is 0.3% of
full scale. R5 may be replaced by a 1000 fixed resistor; the
maximum zero error is then 0.015% of full scale. The input offset
voltage of both amplifiers should be adjusted to less than 0.1 mV
and be better than 0.5mV over the temperature range of interest. With VREF set to 10V, R5 is adjusted so that with code
100000000000, VO UT = OV ±0.2mV. R1 is adjusted so that code
000000000000 causes VOUT to equal VREF .
FIGURE 7: BIPOLAR OPERATION (4-QUADRANT)
R1
VREF o--'W~~------------
R2
BIT 1
NOMINAL ANALOG OUTPUT
-0.99975 VREF
-0.50000 VREF
-0.49975 VREF
(MSB)
Table 2: Code Table for Circuit of Figure 7
DIGITAL INPUT
111111111111
100000000001
100000000000
010000000000
000000000000
BIT 12
(LSB)
11-193
..
_ ..._ - - - -
._-- . _ - - -
NOMINAL ANALOG OUTPUT
-0.99951 VREF
-0.00049 VREF
o
+0.50000 VREF
+1.00000 VREF
1/86, Rev. A
--_
... _ - - - -
a
----------l~ PM-7541 CMOS 12-BIT MONOLITHIC MULTIPLYING D/A CONVERTER
OFFSET ADJUSTMENT
1. Adjust VREF to approximately +10V.
2. Set R5 to zero.
3. Connect all digital inputs to "Logic 1".
4. Adjust IOUT2 amplifieroffsettrimpot forOV ±0.1 mV at IOUT2
amplifier output.
5. Connect a short circuit across R4.
6. Connect all digital inputs to "Logic 0".
7. Adjust IOUT2 amplifier offset trimpot for OV ±0.1 mV at IOUT1
amplifier output.
S. Remove short circuit across R4.
9. Connect MSB (Bit-1) to "Logic 1" and all other bits to
"Logic 0".
10. Adjust R5 for OV ±0.2mV at VOUT'
GAIN ADJUSTMENT
1. Connect all digital inputs to Voo.
2. Monitor VOUT for -VREF ( 1 - ;,,) volts reading while
adjusting Rt
FIGURE 8: SIMPLIFIED CIRCUIT
ANALOG/DIGITAL DIVISION
The transfer function for the PM-7541 connected in the multiplying mode as shown in Figure 6 is:
A1 A2 A3
A12)
Vo = -VIN ( ~ + 2> + 2> + ........ ~
where Ax assume a value of 1 for an "ON" bit and 0 for an
"OFF" bit.
The transfer function is modified when the DAC is connected in
the feedback of an operational amplifier as shown in Figure 9,
it now is:
The above transfer function is the division of an analog
voltage (VREF ) by a digital word. The amplifier goes to the rails
with all bits "OFF" since division by zero is infinity. With all bits
"ON", the gain is 1 (±1 LSB). The gain becomes 4096 with the
LSB, bit 12, "ON".
FIGURE 9: ANALOG/DIGITAL DIVIDER
BIT 12
(LSB)
o-_-",'VY_-"M""""'_'VVv---
ETC
+15V
"FB
PM-7541
"
Your
11-194
1/86, Rev. A
PM-7542
12-BIT (4-BIT BYTE INPUT)
MULTIPLYING CMOS D/A CONVERTER
Precision MOl1olithics Inc.
ADVANCEPRODUCTINFO~TION
FEATURES
± 1/2 LSB Nonlinearity Over Temperature
•
•
•
•
•
•
•
•
•
GENERAL DESCRIPTION
The PM-7542 is a 12-bit monolithic, CMOS digital-to-analog
converter. It consists of three 4-bit data registers, a 12-bit DAC
register, a 12-bit multiplying DAC, and address decoding.
Low Gain Tempco ....•............... 5ppm/oC Max
Microprocessor Compatible
Four Quadrant Multiplication
Low AC Feedthrough
Low Power Dissipation ...................... 40mW
LowCost
Small 16-Pin 0.3" DIP Package
Latch-Up Resistant
Data is accepted in three 4-bit bytes that facilitate direct interfacing to 4 or a-bit microprocessors. Data loading is similar to a
static RAM's write cycle. A CLR pin is provided to reset the DAC's
internal registers to zeros.
CROSS REFERENCE
APPLICATIONS
•
•
•
Industrial Automation
Process Controls
Instrumentation Equipment
ORDERING INFORMATIONt
PACKAGE: 16-PIN DIP"
GAIN
ERROR
MILITARY'
TEMPERATURE
INDUSTRIAL
TEMPERATURE
COMMERCIAL
TEMPERATURE
±1 LSB
±6LSB
PM7542AO
PM7542BO
PM7542EO
PM7542FO
PM7542GP
PM7542HP
• For devices processed in total compliance to MIL-STD-883, add /883 after part
number. Consult factory for 883 data sheet.
"Package Designation: Suffix Q: Hermetic DIP; SuffiX P: Epoxy DIP.
t All commercial and Industrial temperature range parts are available with burn-In.
For ordering Information see 1986 Data Book, Section 2.
PMI
ADI
TEMPERATURE
RANGE
PM7542AO
PM7542BO
PM7542BO
AD7542GTD
AD7542TD
AD7542SD
MILITARY
PM7542EO
PM7542FO
PM7542FO
AD7542GBD
AD7542BD
AD7542AD
INDUSTRIAL
PM7542GP
PM7542HP
PM7542HP
AD7542GKN
AD7542KN
AD7542JN
COMMERCIAL
FUNCTIONAL DIAGRAM
R"
OUT1
OUT2
PIN CONNECTIONS
AGND
V,,
DGND
16-PIN HERMETIC DIP
(Q-Suffix)
.0
t==~~~~DO(LSBI
16-PIN EPOXY DIP
(P-Suffix)
D1
D'
D3(MSB)
This advance producllnlormation describes a product in development al the lime 01 this prinling. Final specifications may vary. Please contact
local sales office or distributor lor final data sheet
11-195
1/86, Rev. A
III
PM-7543
12-BIT SERIAL-INPUT
MULTIPLYING CMOS D/A CONVERTER
Precision MOllolithics Inc.
ADVANCEPRODUCTINFO~TION
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
CROSS REFERENCE
± 1/2 LSB Nonlinearity Over Temp
Low Gain Tempco .•....•...•....••... 5ppm/oC Max
Serial Load on Positive or Negative Strobe
Asynchronous CLEAR Input for Initialization
Low AC Feedthrough
No Schottky Diode Output Protection Required
Four Quadrant Multiplication
Low Power Dissipation
Single Supply Operation
LowCost
Sma Ii 16·Pln 0.3" DIP
Latch·Up Resistant
PACKAGE: 16-PIN DIP"
±1/2LSB
±1/2LSB
±1 LSB
±6LSB
MILITARY'
TEMPERATURE
-SS·C to + 12S·C
PM7543AQ
PM7543BQ
INDUSTRIAL
COMMERCIAL
TEMPERATURE TEMPERATURE
-2S·C to + 8S·C
O·Clo +70·C
PM7543EQ
PM7543FQ
PM7543GP
PM7543HP
• For devices processed in total compliance to MIL-STD-883, add 1883 after part
number. Consult factory for 883 data sheet.
"Package Designation: Suffix Q: Hermetic DIP; Suffix P: Epoxy DIP.
t
ADI
TEMPERATURE
RANGE
PM7543AO
PM7543BO
PM7543BO
AD7543GTD
AD7543TD
AD7543SD
MILITARY
PM7543EO
PM7543FO
PM7543FO
AD7543GBD
AD7543BD
AD7543AD
INDUSTRIAL
PM7543GP
PM7543HP
PM7543HP
AD7543GKN
AD7543KN
AD7543JN
COMMERCIAL
GENERAL DESCRIPTION
ORDERING INFORMATIONt
RELATIVE
GAIN
ACCURACY ERROR
PMI
All commercial and industrial temperature range parts are available with burn-in.
For ordering information see 1986 Data Book, Section 2.
PIN CONNECTIONS
The PM-7543 is a monolithic, serial input, 12-bit CMOS digitalto-analog converter. It is intended for applications where serial
input data is used. Serial input reduces pin count and is, therefore, well-suited where PC board space is at a premium.
The PM-7543 contains a 12-bit serial-in parallel-out input register, a 12-bit shift register, and a 12-bit DAC. A signal at the
strobe pin clocks the serial data input on the leading or trailing
edge of the strobe signal; selection is at the user's discretion.
Data at the serial-in input register is then loaded onto the shift register with the load input controls. A CLR input pin is provided to
asynchronously reset the shift register.
The PM-7543 operates from a single +5V supply and is packaged in a small 16-pin 0.3" wide DIP.
FUNCTIONAL DIAGRAM
VREF
,.
r------......U..!..nO
0-"'+-------1
UT1
OUT 2
t---+"'-OAGND
16·PIN EPOXY DIP
(P·Suffix)
16·PIN HERMETIC DIP
(Q·Suffix)
CLR
13
Li52
9
STB1<>-"+--~r,
SRI
STB4
VDD
STB2
DGND
This advance product information describes a product in development at the time of this printing. Final specifications may vary. Please contact
local sales office or distributor for final data sheet.
1/86, Rev. A
11·196
P~-7545/P~-7645
12-BIT BUFFERED
MULTIPLYING CMOS D/A CONVERTERS
Precision Monolithics Inc
GENERAL DESCRIPTION
FEATURES
•
•
•
•
•
Preadlusted Full Scale •.• ± 1 LSB Maximum Gain Error
Low Gain Temperature Coefficient •••••••••• 2ppm/°C
Small 20-Pln 0.3" Wide DIP
PM-7545 TTL Compatible for VDD = 5V
PM·7645 TTL and 5V CMOS Compatible for VDD = 15V
The PM·7545/PM·7645 are 12·bit CMOS multiplying DACs with
internal data latches. Digital data is input in a 12·bit wide data
format, while CS and WR control inputs are active low. During
this time the latches are transparent allowing digital inputs direct
connection to the DAC. When WR is returned to logic high, the
current data word in the latch is saved.
The PM·7545 operates from 5 to 15 volt power supplies, offering
TTL logic compatibility at VDD of 5V and CMOS logic compat·
ibility at VDD of 15V. The PM·7645 is specified for operation at
VDD of 15V, offering TTL logic input compatibility.
ORDERING INFORMATIONt
PACKAGE: 2D-PIN"
MILITARY""
INDUSTRIAL COMMERCIAL
MAXIMUM TEMPERATURE TEMPERATURE TEMPERATURE
GAIN ERROR
·55°C to
·25°C to
DOC to
+7DOC
+125°C
+85°C
±1 LSB
±3LSB
±1 LSB
±3LSB
PM7545AR
PM7545BR
PM7645AR
PM7645BR
PM7545ER
PM7545FR
PM7645ER
PM7645FR
PIN CONNECTIONS
PM7545GP
PM7545HP
PM7645GP
PM7645HP
2o-PIN EPOXY DIP
(P·Sufflx)
'Package designation:
Suffix R: Hermetic DIP
Suffix P Plastic DIP
"For devices processed in total compliance to MIL-STD-883. add /883 after
part number. Consult factory for 883 data sheet.
tAli commercial and industrial temperature range parts are available with
burn-In. For ordering Information seo 1986 Data Book. Section 2.
2o-PIN HERMETIC DIP
(R·Sufflx)
CROSS REFERENCE
TEMPERATURE
RANGE
PMI
ADI
PM7545AR
PM7545BR
PM7545BR
PM7545BR
AD7545GUD
AD7545UD
AD7545TD
AD7545SD
MILITARY
PM7545ER
PM7545FR
PM7545FR
PM7545FR
AD7545GCQ
AD7545CQ
AD7545BQ
AD7545AQ
INDUSTRIAL
PM7545GP
PM7545HP
PM7545HP
PM7545HP
AD7545GLN
AD7545LN
AD7545KN
AD7545JN
COMMERCIAL
FUNCTIONAL DIAGRAM
PM-7545/PM-7645
r-------------~jl--~-oOUT
VREF 0-+------1
12-BIT
MULTIPLYING OAe
r----+-OAGNO
WRo-+----'r"-....
080-+----1..",
11-197
INPUT DATA LATCHES
DGNO
1/86, Rev. B
--------i~ PM-7545/PM-7645 12-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTERS
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted.)
VDD to DGND .•...•..•.•..•....•........••... -0.3V, +17V
Digital Input Voltage to DGND .....•.....•...•.. -0.3V, VDD
AGND to DGND ......•.•••••..•••.•.•....•... -0.3V, VDD
VRFB , VREF to DGND .•..••...•...•. . . . • . . . . . . • . . . .. ±25V
VPIN 1 to DGND ............................... -0.3V, VD D
Power Dissipation (Any Package) to +75°C ...•••.• 450mW
Derates Above +75°C by ..••.•••........•..... 6mW/oC
Operating Temperature Range
Military (AR, BR) Grades .......•....... -55°C to + 125°C
Industrial (ER, FR) Grades ••...•...•..•. -25°C to +85°C
Commercial (Gp, HP) Grades .........•.... O°C to +70°C
Dice Junction Temperature. . . • . . . •• • . . . . . . . . . . . .. +150°C
Storage Temperature ...•...•....•....•.• -65°C to +150°C
Lead Temperature (Soldering, 60 sec) .••.••....... +300°C
CAUTION:
1.
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device This IS a stress rating only and functional
operation at or above this specification is not Implied. Exposure to above
maximum rating conditions for extended periods may affect device reliability.
Do not apply voltages higher than VDD or less than GND potential on any
terminal except VREF
The digital inputs are zener protected, however, permanent damage may
occur on unprotected units from high-energy electrostatic fields. Keep units
in conductive foam at all times until ready to use, Use proper anti-static
handling procedures
Remove power before inserting or removing units from their sockets
ELECTRICAL CHARACTERISTICS atVDD = +5V, VREF = +10V, VOUT= OV, AGND = DGND =OV; TA =-55°C to +125°C apply for
PM-7545AR/BR, TA = -25° C to +85° C apply for PM-7545ER/FR, TA = 0° C to +70° C apply for PM-7545GP/HP, unless otherwise noted.
For 15V operation, see pages 4 and 5.
PARAMETER
SYMBOL
PM-7S4SA/E/G
TYP
MAX
MIN
CONDITIONS
PM-7S4SB/F/H
MIN
TYP
MAX
UNITS
STATIC ACCURACY
12
ResolutIOn
N
Relative
Accuracy
INL
TA = Full Temp. Range
±1/2
±112
LSB
Differential
Nonlinearity
DNL
TA = Full Temp Range
(Note 1)
±1
±1
LSB
G'SE
TA=+25°C
TA = Full Temp Range
±1
±2
±3
±4
LSB
TCG,s
(Note 4)
±S
ppm/'C
PSS
T = +2S'C
A
(:.V = ±S%)
TA = Full Temp Range
DD
0002
0004
0002
0004
%1%
10
10
AlB Versions
E/F/G/H VerSions
200
SO
200
SO
300
300
Gain Error
(Notes 2,3)
12
Bits
Gain Temperature
Coefficient
±2
±S
±2
.aGain/.aTemperature
DC Supply Rejection
:'Gainl:'VDD
Output Leakage
Current at OUT
TA = +2S'C. WR = CS = OV.
All Digital Inputs = OV
IlKG
nA
TA = Full Temp. Range
DYNAMIC PERFORMANCE
Propagation Delay
(Notes 4. S. 6. 7)
tpD
TA = +2S'C
(OUT Load = 100n. CEXT = 13pF)
Current Settling Time
t,
TA = Full Temp Range
(To 1/2 LSB) (Note 4)
lOUT Load = 100n
Digital Charge
Injection
AC Feedthrough
at lOUT
Q
fJS
TA=+25°C'
TA = Full Temp. Range
300
400
VRE ' = AGND (Note 4)
FT
ns
TA = Full Temp Range
VRE ' = ±10V. f = 10kHz
All Digital Inputs = OV
300
400
S
11-198
nVs
mVp~p
1/86, Rev. B
--
--------
---
\fMDPM-7545/PM-7645 12-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTERS
ELECTRICAL CHARACTERISTICS atVDD = +5V, V REF = +10V, VOUT= OV, AGND =
DGND = OV; TA = -55°C to +125°C apply for
PM-7545AR/BR, TA = -25° C to +85° C apply for PM-7545ERlFR, TA = 0° C to +70° C apply for PM-7545GP/HP, unless otherwise noted.
For 15V operation, see pages 4 and 5. (Continued)
PARAMETER
PM-7S4SA/E/G
MAX
MIN
TYP
SYMBOL
CONDITIONS
RREF
TA = Full Temp Range
Input Resistance
COUT
TA = Full Temp Range
DBO-DB11 =OV. WR =CS =OV
DBO-DB11 = Voo ' WR = CS =OV
PM-7S4SB/F/H
MIN
TYP
MAX
UNITS
REFERENCE INPUT
Input Resistance
(Pin 19 to GND)
11
15
11
15
kn
70
150
pF
ANALOG OUTPUTS
Output Capacitance
(Note 4)
COUT
70
150
~
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
DBO-DB11, WR, CS
V,NH
V 1NL
liN
C'N
TA
= Full Temp
2.4
24
Range
08
08
10
10
TA = +25°C
= Full Temp Range
TA = Full Temp Range
V,N =0 (Note 4)
TA
8
V
pA
pF
SWITCHING CHARACTERISTICS
(Notes 4, 8, 9)
See Timing Diagram
Chip Select to
Write Setup Time
tcs
TA
TA
=+25"C
= Full Temp. Range
Chip Select to
Write Hold Time
tCH
TA
= Full Temp
Range
0
Write Pulse
Width
tWR
TA
TA
=+25"C
=Full Temp
Range
250
380
175
270
250
380
175
270
ns
Data Setup
Time
tos
TA
TA
=+25"C
= Full Temp
Range
140
210
100
150
140
210
100
150
ns
Data Hold Time
tOH
TA
= Full Temp
Range
10
100
TA =Full Temp Range
(All Digital Inputs V,NL or V,NH )
100
TA =+25"C
TA = Full Temp Range
(All Digital Inputs OV or VOO )
280
380
200
270
280
380
200
270
ns
0
ns
ns
10
mA
100
100
5
100
100
pA
NOTES:
2
3
4
5
12~blt monotoniC over full temperature range
Includes the effects of 5ppm max gain TC
USing Internal RFB DAC register loaded with 1111 1111 1111 Gam error IS
adjustable uSing the Circuits of Figures 4 and 5
GUARANTEED and NOT TESTED
From digital Input change to 90% of final analog output
11-199
6
7
8
~
0
U
C)
0
~
0
~
~
C)
......
POWER SUPPLY
Supply Current
tn
~
All digital Inputs =OV to Voo , or Voo to OV
Logic Inputs are MOS gates, tYPical Input current (at +25" C) IS less than
1nA
Sample tested at +250 C to ensure compliance
Chip select CS must be COinCident or present before and/or afterwnte WR,
that IS, les 2: tWR' tCH 2: 0
1/86, Rev. B
0
II
~ PM-7545/PM-7645 12-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTERS
ELECTRICAL CHARACTERISTICS at V DD =+15V, VREF =+10V, V OUT =OV, AGND =DGND =OV; TA =-550 C to +1250 C apply for
PM-7545/PM-7645ARlBR, TA =-250 C to +850 C apply for PM-7545/PM-7645ERlFR, TA =00 C to +700 C apply for PM-7545/PM-7645GPlHp,
unless otherwise noted.
PM-7545A/E/G
PM-7645A/E/G
PARAMETER
SYMBOL
CONOITIONS
MIN
TYP
PM-7545B/F/H
PM-7645B/F/H
MAX
MIN
TYP
MAX
UNITS
STATIC ACCURACY
12
12
Bits
Resolution
N
Relat,ve
Accuracy
INL
TA
Range
±112
±1/2
LSB
Differenllal
Nonhneanty
DNL
TA = Full Temp. Range
(Note 1)
±1
±1
LSB
Gam Error
(Notes 2, 3)
G FSE
TA
TA
±1
±2
±3
±4
LSB
Gain Temperature
Coefficient
.6.Galni.6. Temperature
TCG FS
(Note 4)
±5
ppm/oC
DC Supply ReJeclion
AGa,n/AVoo
PSS
TA
TA
0002
0004
0.002
0.004
%/%
10
10
Output Leakage
Current at OUT
ILKG
=Full Temp
=+25°C
=Full Temp
Range
±2
=+25° C
(AV =±5%)
=Full Temp Range 00
TA =+25°C, WR =CS =OV,
All Dig,tal Inputs =OV
TA = Full Temp Range
±5
±2
nA
AlB Versions
ElF/G/H Vers'ons
200
50
200
50
TA =+25°C
(OUT Load
300
300
DYNAMJC PERFORMANCE
Propagat,on Delay
(Notes 4, 5.6, 7)
tpo
Current Setting Time
ts
TA =Full Temp Range
(To 1/2 LSB) (Note 4)
lOUT Load
D'g,tal Charge
Injection
AC Feedthrough
at lOUT
=1000. C EXT =13pF)
ns
ps
=1000
Q
TA =+25°C
TA = Full Temp Range
VREF =AGND (Note 4)
FT
TA =Full Temp Range
VREF =±10V, f =10kHz
All D'g,tallnputs =OV
RREF
TA =Full Temp Range
Input Res'stance
300
400
300
400
nVs
mVp_p
5
REFERENCE INPUT
Input Resistance
(Pin 19 to GND)
11
11
15
15
kO
70
150
pF
ANALOG OUTPUTS
Output Capacitance
(Note 4)
C OUT
TA = Full Temp Range
DBO-DBll = OV, WR =CS =OV
DBO-DBll = VOD' WR
COUT
70
150
=CS =OV
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
V'NH
V'NL
TA
Input High Voltage
Input Low Voltage
V'NH
V'NL
TA = Full Temp Range. PM-7645
Input Current
I'N
TA = +25°C
TA = Full Temp. Range
Input Capacitance
DBO-DB11, WR. CS
C'N
TA =Full Temp Range
V'N =0 (Note 4)
=Full Temp
Range. PM-7545
135
13.5
15
2.4
24
11-200
1.5
V
V
08
08
10
1
10
IlA
8
8
pF
1/86, Rev. B
----------t1fMD
PM-7545/PM-7645 12-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTERS
ELECTRICAL CHARACTERISTICS at V DD =+15\1, V REF =+10V, VOUT =OV, AGND =DGND =OV; TA =-55 0 C to +1250 C apply for
PM-7545/PM-7645AR/BR, TA =-250 C to +85 0 C apply for PM-7545/PM-7645ER/FR, TA =00 C to +700 C apply for PM-7545/PM-7645G P/Hp,
unless otherwise noted. (Continued)
PARAMETER
PM-7545A/E/G
PM-7645A/E/G
MIN
TYP
MAX
SYMBOL
CONDITIONS
IDD
TA = Full Temp Range
(All Digital Inputs V,NL or V,NH )
'DD
TA = +25°C
TA = Full Temp Range
(All Digital Inputs OV or VDD )
PM-7545B/F/H
PM-7645B/F/H
MIN
TYP
MAX
UNITS
POWER SUPPLY
Supply Current
SWITCHING CHARACTERISTICS
(Notes 4. 8. 9)
See Timing Diagram
Chip Select to
TA=+25°C
TA ;:;; Full Temp Range
Write Setup Time
tcs
mA
100
100
100
100
/lA
PM-7545 A/E/G
180
200
120
150
g
PM-7545 B/F/H
180
200
120
150
ns
teH
Write Pulse
Width
tWR
TA=+25°C
TA =Full Temp Range
160
240
100
170
160
240
100
170
ns
Data Setup
Time
t DS
TA=+25°C
TA = Full Temp Range
90
120
60
80
90
120
60
80
ns
Data Hold Time
tDH
TA
= Full Temp
~
0
Chip Select to
Wnte Hold Time
TA
~
>Ll
Range
ns
U
(j
=Full Temp
Range
SWITCHING CHARACTERISTICS
(Notes 4. 8, 9)
See Timing Diagram
Chip Select to
Wnte Setup Time
tes
TA =+25°C
TA = Full Temp Range
Chip Select to
Write Hold Time
teH
Write Pulse
Width
tWR
Data Setup
Time
Data Hold Time
TA
= Full Temp
10
10
PM-7645 AlE/G
150
210
ns
PM-7645 B/F/H
150
210
Range
ns
Range
150
210
150
210
ns
t DS
TA=+25°C
TA =Full Temp Range
225
300
225
300
ns
tDH
TA = Full Temp Range
10
10
ns
TA
= Full Temp
NOTES:
12-blt monotonic over full temperature range
Includes the effects of 5ppm max gain TC.
USing Internal RFB . DAC register loaded with 1111 11111111 Gain error
adjustable using the cirCUits of Figures 4 and 5.
GUARANTEED and NOT TESTED.
From digital Input change to 90% of final analog output.
IS
11-201
~
0
E:-'
~....
(j
ns
TA =+25°C
0
All digital Inputs =OV to VDD • or VDD to OV.
LogiC Inputs are MOS gates, tYPical mput current (at +25 0 C) IS less than
InA
Sample tested at +25 0 C to ensure compliance
Chip select CS must be cOincident or present before and/or afterwnte WR,
that IS, tcs :;::: tWA' tCH :;::: 0
1/86, Rev_ B
....
0
II
_ _ _ _ _ _ _-I!fMDPM-7545/PM-764512-BIT BUFFERED MULTIPLYING CMOS DIA CONVERTERS
DICE CHARACTERISTICS
1. OUT
2. AGND
3. DGND
4. DB11 (MSB)
5. DB10
6.DB9
7. DB8
8. DB7
9.DB6
10. DB5
11. DB4
12. DB3
13. DB2
14. DB1
15. DBO (LSB)
16. CS
17.WR
18. Voo
19. VREF
20. RFB
For additional DICE inlormation refer to
1986 Data Book, Section 2.
DIE SIZE 0.093 X 0.101 inch, 9.393 sq. mils
(2.36 X 2.57mm, 6.07 sq. mm)
WAFER TEST LIMITS at VDD =+5 or +15\/, VREF =+10V, VOUT =OV, AGND
=DGND =Ov.
PM-7545G/PM-7645G
PARAMETER
SYMBOL
CONDITIONS
Relative Accuracy
INL
Endpoint Linearity Error
Differential Nonlinearity
DNL
Gain Error
GFSE
DAC Latches Loaded with 1111 1111 1111
Output Leakage
ILKG
Input Resistance
LIMIT
UNITS
±1/2
LSB MAX
±1
LSB MAX
±5
LSB MAX
DAC Latches Loaded with 000000000000
Pad 1
±10
nA MAX
RREF
Pad 19
7/15
kO MIN/kO MAX
Digital Input
High
V1NH
V = 5V
OD
PM-7545 only
VOD = 15V
24
135
VMIN
Digital Input
Low
V1Nl
V = 5V
DD
PM-7545 only
VOD = 15V
08
15
V MAX
Digital Input
High
V1NH
VOD = 15V PM-7645 only
24
VMIN
Digital Input
Low
V1NL
VOD = 15V PM-7645 only
08
V MAX
Input Current
'iN
VIN
±1
fJ.AMAX
Supply Current
'
DC Supply Rejection
(aGaln/avDD )
=OV or Voo
All Digital Inputs V1NL or V1NH
DO
PSS
All Digital Inputs OV or VOD
8VOD
=±5%
01
002
mAMAX
%/% MAX
NOTE:
Electrical tests are performed at wafer probe to the limits shown Due to vanatlons In assembly methods and normal Yield loss, Yield after packaging IS not
guaranteed for standard product dice Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing
11-202
1/86, Rev. B
----------1~ PM-7545/PM-7645 12-BIT BUFFERED MULTIPLYING CMOS DIA CONVERTERS
TYPICAL ELECTRICAL CHARACTERISTICS at Voo
unless otherwise noted. (Note 1)
=+5V or +15V, AGND =DGND =OV, VREF =+10V, OUT =OV; TA =25°C,
PM-7545G/PM-7645G
PARAMETER
SYMBOL
Digital Input Capacitance
C'N
CONDITIONS
pF
50
OAC Latches Loaded with 0000 0000 0000
Output Capacitance
pF
COUT
Propagation Delay
(Notes 2, 3, 4)
UNITS
TYPICAL
110
OAC Latches Loaded with 1111 1111 1111
140
Voo = 15V
tpo
Voo = 5V
PM-7545 only
ns
230
NOTES:
1 These charactenstlcs are for design gUidance only and are not subject to test
2 From digital mput change to 90% of fmal analog output.
3. OUT load =100(1, C EXT = 13pF
4 CS = WR = O. OBO to OB11 = OV to Voo or Voo to OV
TYPICAL PERFORMANCE CHARACTERISTICS
FULL-SCALE GAIN ERROR
vs TEMPERATURE
LOGIC THRESHOLD VOLTAGE
vs SUPPLY VOLTAGE
05
04
OUTPUT LEAKAGE CURRENT
vs TEMPERATURE
15
1000
::::VREF=-lOV
Voo'" 15V
03
02
1
./
./
-0 1
J
~
-02
~
-04
-05
~
-
p~ ~
-03
~
_
~
0
•
TEMPERATURE
~
@
~
ill
PM-7645
10
/
1
15
-75
-50
-25
Voo SUPPLY VOLTAGE
(~C)
25
50
75
100
125
TEMPERATURE (OC)
SUPPLY CURRENT
vs TEMPERATURE
PM-7545
SUPPLY CURRENT
vs TEMPERATURE
PM-7645
10
Voo
= 5V
F
V,N
VDD
15V
VIN=24V -
24V
T"'I...
01
v"
/
01
VIN =
001
75
-50
-25
oav
0
25
50
75
TEMPERATURE (0C)
"
100
001
-75 -50
125
OBV..-
V
-25
25
50
75
100
125
TEMPERATURE (OC)
11-203
1/86, Rev. B
II
--------l~ PM-7545/PM-7645 12-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTERS
PARAMETER DEFINITIONS
LOGIC INFORMATION
RELATIVE ACCURACY
Sometimes referred to as endpoint nonlinearity, and is a
measure of the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. Relative
Accuracy is measured after the zero and full-scale points have
been adjusted, and is normally expressed in LSB or as a
percentage of full scale.
WRITE CYCLE TIMING DIAGRAM
----VDD
DIFFERENTIAL NONLINEARITY
This is the difference between the measured change and the
ideal change between any two adjacent codes. A differential
nonlinearity of ±1 LSB maximum over the full operating temperature range will ensure that a device is monotonic (the
output will increase for an increase in digital code applied).
DATA IN
(DBO-DBll)
------'
MODE SELECTION
WRITE MODE'
CS AND WR LOW, OAe RESPONDS
TO DATA BUS (DBO-DB11) INPUTS.
GAIN ERROR
Gain or full scale error is the amount of output error between the
ideal output and the actual output. The ideal output is VREF
minus 1 LSB. The gain error is adjustable to zero using external
resistance.
HOLD MODE:
EITHER B OR WR HIGH, DATA BUS
(DBO-OB11) IS LOCKED OUT; OAe
HOLDS LAST DATA PRESENT WHEN
WR OR ES ASSUMED HIGH STATE
NOTES:
Voo'" +5V, tr '" tf = 20ns
voo =+15V; tr = tf = 40ns
ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM
~~~I~~ ~~A~~~rBENT REFERENCE LEVEL IS VIH; VIL.
OUTPUT CAPACITANCE
The capacitance from OUT to AGND.
THE PM·7645 USES AN INPUT LOGIC HIGH OF 5 VOLTS
PROPAGATION DELAY
This is measured from the digital input change to the analog
output current reaching 90% of its final value.
D/A CONVERTER SECTION
FIGURE 1: Simplified D/A Circuit of PM-7545
DIGITAL CHARGE INJECTION
This is a measure of the amount of charge injected to the analog
output from the digital inputs, when the digital inputs change
states. It is the area of the glitch and is specified in nVsec; it is
measured with VREF = AGND.
I
I
BURN-IN CIRCUIT
OB11
(MBB)
+10
VREF
PM-7545/PM-7645
~
G
R3
L...!
RFB
~
AGND
VREF
flL
DGND
Voo
~
WR
H
OUT
100kO~ 011 (MSB)
5
~
~
~
~
~
010
cs ~
09
(LSB) DO
08
01
07
02
06
03
05
D4
~"~
Voo
Rl
tkO
5kO
14
E..!3......
J2.......
~
R2
5kO
Voo::: 15V± 5%
VREF = 10V ± 5%
Cl
080
(LBB)
Figure 1 shows a simplified circuit of the D/A Converter section
and Figure2 gives an approximate equivalent switch circuit. R is
typically 11 kQ.
The binary-weighted currents are switched between OUT
and AGND by N-channel switches, thus maintaining a constant
current in each ladder leg independent of the switch state.
R4
1L-
DB9
=C2 =47J1f
C3 = C4 = 001,uf
The capacitance at the OUT terminal, COUT, is code dependent
and varies from 70pF (all switches to AGND) to 150pF (all
switches to OUT). One of the current switches is shown in
Figure 2.
The input resistance at VREF (Figure 1) is always equal to RLDR
(RLDR is the R/2R ladder characteristics resistance and is equal
to value URn). Since the input resistance at the VREF pin is
constant, the reference terminal can be driven by a reference
voltage or a reference current, ac or dc, of positive or negative
polarity. (If a current source is used, a low-temperaturecoefficient external RFB is recommended to define scale factor.)
11-204
1/86, Rev. B
--------Im
PM·7545/PM·7645 12·BIT BUFFERED MULTIPLYING CMOS D/A CONVERTERS
The internal feedback resistor (R FS ) has a normally closed
switch in series as shown in Figure 1. This switch improves
performance over temperature and power supply rejection;
however when the circuit is not powered up the switch assumes
an open state.
FIGURE 2: N·Channel Current Steering Switch
TO LADDER
FROM~
INTERFACE ~
LOGIC~
not required. Capacitor C1 provides phase compensation and
helps prevent overshoot and ringing when using high speed op
amps. The circuits of Figures 4 and 5 have constant input
impedance at the VREF terminal.
The circuit of Figure 4 can either be used as a fixed reference
D/A converter so that it provides an analog output vOltage in the
rangeOto -VIN (the inversion is introduced by the op amp); orVIN
can be an ac signal in which case the circuit behaves as an
attenuator (2·Quadrant Multiplier). VIN can be any vOltage in the
range -20 :s VIN :s +20 volts (provided the op amp can handle
such voltages) since VREF is permitted to exceed Voo. Table 2
shows the code relationship for the circuit of Figure 4.
....
FIGURE 4: Unipolar Binary Operation
our
AGND
Voo
R2*
DIGITAL SECTION
V OUT
R1'
Figure 3 shows the digital structure for one bit. The digital
signals CONTROL and CONTROL are generated from CS
and WR.
0611-080
*SEE TABLE 1.
FIGURE 3: Digital Input Structure
. . . - - - _ T O AGNO SWITCH
TABLE I: Recommended Trim Resistor Value vs. Grades
DIGITAL
TO OUT SWITCH
INPUT
CONTROL
CONTROL
The input buffers are simple CMOS inverters designed such
that when the PM· 7545 is operated with Voo = 5V, the buffers
convert TTL input levels (2.4V and 0.8V) into CMOS logic levels.
When the digital input is in the region of 1.0volts to 6.0volts, the
input buffers operate in their linear region and draw current
from the power supply. To minimize power supply currents, it is
recommended that the digital input voltages be as close to the
supply rails (Voo and DGND) as is practically possible. The
PM·7545 may be operated with any supply voltage in the range
5:S Voo:S 15 volts. With Voo = +15V, the input logic levels are
CMOS compatible only, i.e., 1.5V and 13.5V. The PM·7645
operates with Voo = 15V only; the buffers convert TTL input
levels (2.4V and 0.8V) into CMOS logic levels.
TRIM
RESISTOR
CR
HP/FR/BR
R1
2000
1000
200
R2
680
330
6.80
GP/ER/AR
TABLE II: Unipolar Binary Code Table for Circuit of Figure 4
BINARY NUMBER IN
DAC REGISTER
ANALOG OUTPUT
1111
1111
1111
}
-VIN . { 4095
4096
1000
0000
0000
2048}
-VIN . { 4096
0000
0000
0001
-VIN • {
0000
0000
0000
-1/2VIN
40~6 }
a Volts
BASIC APPLICATIONS
Figures 4 and 5 show simple unipolar and bipolar circuits using
the PM·7545/PM·7645. Resistor R1 is used to trim for full scale.
The following versions (pM·7545AR, PM·7545ER, PM·7545GP)
have a guaranteed maximum gain error of ±1 LSB at +25°C and
Voo = +5V, and in many applications the gain trim resistors are
11·205
1/86, Rev. B
I
---------I~ PM-7545/PM-7645 12-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTERS
Figure 5 and Table 3 illustrate the recommended circuit and
code relationship for bipolar operation. The D/A function itself
uses offset binary code. The inverter U, on the MSB line,
converts 2's-complement input code to offset binary code. The
inverter U, may be omitted if the inversion is done in software.
R3, R4 and R5 must match within 0.01 % and should be the same
type of resistors (preferably wire-wound or metal foil), so that
their temperature coefficients match. Mismatch of R3 value to
R4 causes both offset and full scale error. Mismatch of R5 to R4
and R3 causes full scale error.
TABLE III: 2'8 Complement Code Table for Circuit of Figure 5
DATA INPUT
ANALOG OUTPUT
{ 2047 }
2048
0111
1111
1111
+V1N '
0000
0000
0001
+VIN . {
0000
0000
0000
1111
1111
1111
-VIN • {
1000
0000
0000
-V1N '
20~8}
APPLICATION HINTS
Output Offset: CMOS D/A converters exhibit a code-dependent
output resistance that causes a code-dependent error voltage
at the output of the amplifier. The maximum amplitude of this
offset, which adds to the D/A converter nonlinearity, is 0.67 Vas
where Vas is the amplifier input-offset voltage. To maintain
monotonic operation, it is recommended that Vas be no greater
than 10% of 1 LSB over the temperature range of operation.
General Ground Management: AC or transient voltages between AGND and DGND can cause noise injection into the
analog output. The simplest method of ensuring that voltages at
AGND and DGND are equal is to tie AGND and DGND
together at the PM-7545/PM-7645. It is recommended that two
diodes (1 N914 or equivalent) be connected in inverse parallel
between AGND and DGND pins in complex systems where
AGND and DGND tie on the backplane.
Digital Glitches: When WR and CS are both low, the latches are
transparent and the D/A converter inputs follow the data inputs.
Some bus systems do not always have data valid for the whole
period during which WR is low. This will allow invalid data to
briefly appear althe DAC inputs during the write cycle. This can
cause unwanted glitches at the DAC output. Retiming the write
pulse WR, so that it only occurs when data is valid, will eliminate
the problem.
a Volts
20~8 }
{ 2048 }
2048
FIGURE 5: Bipolar Operation (2's Complement Code)
11
ANALOG
COMMON
U,
(SEE TEXT)
'2
·SEE TABLE 1
DATA INPUT
11-206
1/86, Rev. B
_ _ _ _ _ _ _---1~PM-7545/PM-7645 12-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTERS
INTERFACING THE PM·7545/PM·7645 TO
MICROPROCESSORS
The PM-7545 can be directly interfaced to either an 8 or 16-bit
microprocessor via its 12-bit wide data latch using the CS and
WR control signals.
An 8-bit processor interface configuration is shown in Figure 6.
It uses two memory addresses, one forthe lower 8-bits and one
for the upper 4-bits of data into the DAC via the latch.
FIGURE 6: 8-Bit Processor to PM-7545/7645 Interface
Connection to an 8-bit processor with a full 16-bit wide address
bus (such as the 6800, 8080, Z80) is shown in Figure 7. The 12
lower address lines are fed directly to the PM-7545; this allows
the PM-7545 to use 4k bytes for its address location. The
address field of the instruction is organized so that the lower
12-bits contain the DAC data. Data is written into the DAC using
a single write instruction.
FIGURE 7: Connecting the PM-7545/7645 to an 8-Bit Microprocessor via the Address Bus
Vl
A15I------------------'\
ADDRESS BUS
AO
ex:
~
~
A15
16-81T ADDRESS BUS
AO
~
DBll
CPU
DBO
CPU
PM-7545!
PM-7645
ViR t:>------l
WI!
C)
WI!
0
~
DATA BUS
8-BIT DATA BUS
DO
DO
~50
U
"CS
07
071----_-'
0
'" DECODED ADDRESS FOR DAC
0
*0, = DECODED ADDRESS FOR LATCH
f-;-<
~......
C)
......
Cl
II
11-207
1/86, Rev. B
PM-7548
12-BIT 18-BIT BYTE INPUT)
MULTIPLYING CMOS D/A CONVERTER
Prl"cisiol1 Monolithics Inc.
ADVANCEPRODUCTINFO~TION
CROSS REFERENCE
FEATURES
•
•
•
•
•
•
•
•
•
•
12-BIt Resolution with an 8-Blt Data Bus
Direct Interface to Most 8-Blt Microprocessors
Selectable Input Data Format (Left or Right-Justified)
TTL/CMOS Compatible
Gain Drift •••.•..•.......••....•...•. 5ppm/oC Max
Guaranteed Monotonic Over Full Temperature Range
Single Supply Operation
Four Quadrant Multiplication
Latch-Up Resistant
Small 20-Pin 0.3" DIP Package
PMI
ADI
TEMPERATURE
RANGE
PM7548AR
PM7548BR
AD7548TD
AD7548SD
MILITARY
PM7548ER
PM7548FR
AD7548BO
AD7548AO
INDUSTRIAL
PM7548GP
PM7548HP
AD7548KN
AD7548JN
COMMERCIAL
PIN CONNECTIONS
APPLICATIONS
•
•
•
•
•
8·Bit Mlcroprocessor·Controlied Systems
Industrial Automation
Process Controls
Servo Control Systems
Programmable Filters and Amplifiers
20-PIN HERMETIC DIP
(R-Sufflx)
20-PIN EPOXY DIP
(P·Sufflx)
ORDERING INFORMATIONt
PACKAGE: 2O·PIN DIP"
RELATIVE
GAIN
ACCURACY ERROR
±1/2LSB
±1 LSB
±3LSB
±6LSB
MILITARY'
TEMPERATURE
INDUSTRIAL
COMMERCIAL
TEMPERATURE TEMPERATURE
-55"<:10 +125"<:
-25"<: 10 + 85"<:
O"C 10 + 7O"C
PM7548AR
PM7548BR
PM7548ER
PM7548FR
PM7548GP
PM7548HP
FUNCTIONAL DIAGRAM
• For deVIces processed in total compliance to MIL-STD-883, add 1883 after part
number. Consult factory lor 883 data sheet.
"Package Daslgnation: Suffix A: Hermetic DIP; Suffix P: Epoxy DIP.
t All commercial and Industrial temperature range perts are available with burn-In.
For ordering inlormation see 1986 Data Book, Section 2
VDD
18
Rn
o"",191--I(~R~-2~R~LA~D~DE:R~F=~~===~ AGND
[~~~E:=F=~Fir==f,5~ CTRL
20
GENERAL DESCRIPTION
""OF
The PM-7548 is a 12-bit monolithic, CMOS digital-to-analog
converter with an 8-bit data input bus. Simple interfacing to 8-bit
microprocessors results when using a two-step data-load operation from the 8-bit data bus. The PM-7548 allows either left or
right-justified data. This simplifies data-formatting when used
with various types of microprocessors.
OUT
DF/I5i5ii
15.() Lilli:
t+--Ir
t+--If!!17.() Wii
In multiple DAC applications, it sometimes becomes necessary to
simultaneously update the outputs. The PM-7548 is ideally
suited for this application, providing a separate LDAC control pin
that immediately updates an analog output from the input
registers.
1-_+1ll!.6o am
DGND
This advance productlnlormatlon describes a product In development at the time 01 thll printing. Final specifications may vary. Please contact
local lalel office or distributor lor final data sheet.
11·208
1/86, Rev. A
J~38510/11301/11302
JAN 8-BIT MULTIPLYING
D/A CONVERTERS
Precision Monolithics Inc.
POWER AND THERMAL CHARACTERISTICS
GENERAL DESCRIPTION
This data sheet covers the electrical requirements of the monolithic 8-bit digital-to-analog converters found in MIL-M-38510/113.
Devices supplied to this data sheet are manufactured and tested
at PMl's MIL-M-38510 certified facility and are listed in
QPL-38510.
Complete device requirements will be found in MIL-M-38510
and MIL-M-38510/113 for Class B processed devices.
Package
case oufllne
Maximum allowable
power dlsalpallon
Mexlmum
BJ - C
Maximum
BJ - A
Dual-in-hne
E
400mW at TA = 125'C
35'C/W
120'C/W
PIN CONNECTIONS & ORDERING INFORMATION
Device Types shall be as follows:
01 DI A Converter, 8 bit, 0.19% linearity
02 D/A Converter, 8 bit, 0.10% linearity
GENERIC CROSS-REFERENCE INFORMATION
This cross-reference information is presented for the convenience of the user. The Generic-Industry types listed may not
have identical operational performance characteristics across
the military temperature range or reliability factors equivalent to
the MIL-M-38510/113 devices.
Military Device Type
Generic-Industry Type
01
DAC-08
02
OAC-08A
Jan Device Type
JM38510/11301BEC
JM38510/11302BEC
JM38510/11301 BEB
JM38510/11302BEB
PMI Device Type
OAC08Q 113851 0
OAC08AQ1/38510
OAC08Q2/38510
OAC08AQ2I38510
Linearity
0.19%
0.10%
0.19%
0.10%
NOTES: Lead finish as follows
BEC" Gold Plate. side braze package
BEB: Tin Plate. CERDIP Package
CASE OUTLINE
Per MIL-M-38510, Appendix C, Case Outline 0-2 (16-Lead 1/4"x
718", dual-in-line). Package type deSignator "E".
II
SIMPLIFIED SCHEMATIC
r--t-~-+~--+~-+~-h--h_-h~_+4:"2-0- lOUT
-TOUT
VREF
(+)
0--'-"4+--.--+_ _,
VREF (_) 0--"'54-_-1"",
16
CQMP
3
-Vee
11-209
1/86, Rev. A
----------l~ JM3a510111301111302 JAN a-BIT MULTIPLYING DlA CONVERTER
ABSOLUTE MAXIMUM RATINGS
Junction Temperature ........................... 175·C
Storage Temperature ••••••••••••••••• -65· C to + 150· C
Supply Voltage [+VCC- (-VCC)] ••••••••••••••••• 36Vdc
Voltage, Digital Input to Negative Supply
[Vlogic- (-Vcc)] ........................... 0 to 36Vdc
Voltage, Logic Control (VLc) .............. -Vccto+Vcc
Reference Voltage Input [(VI4, VIS)] ........ -Vcc to +Vcc
Reference Input Current (114) ....................... 5mA
Reference Input Differential Voltage
[(VlrVls)] ................................... ±18Vdc
Lead Temperature (Soldering, 60 sec) ••••••••••••• 300·C
RECOMMENDED OPERATING CONDITIONS
Supply Voltage Range ............... ±5Vdc to ± 15Vdc"
Ambient Temperature Range .......... -55·C to +125·C
"NOTE:
A slight degradation In linearity can occur when the supply voltage Is near the
±SV end of the recommended operating range.
at ±Vcc = ±15Vdc; Source resistance = 50 ohms; IREF = 2.mA; Figure 1; Ambient
=-55· C to +125· C, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
temperature range
01 LIMITS
PARAMETER
SYMBOL
CONDITIONS
~(I)
Measure 10 , (ION-l oN-,) 2: 0 at
02 LIMITS
MIN
MAX
MIN
MAX
0
16
0
16
0
16
0
16
each major carry point
Monotontclty
~iiT
Measure
UNITS
/loA
iQ. (ION-l oN-,) 2:0at
each major carry pOint
Output Symmetry
~IFS
I FS - I FS
-8
8
-4
4
/loA
Full-Scale Current
Temperature Coefficient
To (lFS)
To (IFS)
All input bits high. Measure 10
All input bits low. Measure
-50
50
-50
50
ppm/DC
I FS
All input bits high.
194
2.04
1984
2
mA
IFS
All Input bits low,
Izs
All Input bits low
Measure 10
All Input bits high,
Measure iO
Full-Scale Current
Zero-Scale Current
~
INL+
Positive Bit Errors
INI.+
Measure iO
Measure
i;;
Measure iO
(I Negative bit errors)/iFS
~INL
Measure 10
IINL+ I-IINL-I
~Ijij[
M~ureiQ
IINL + I-IINL-I
NL+
Measure 10
IINL+ I + I ~INL I
M~ureiQ
IINL+ I + I ~I'jijL I
liil+
-1
/loA
0
019
0
0.10
-019
0
-0.10
0
-005
005
-0.03
003
0
019
0
010
%
0
019
0
010
%
%
(I Positive bit errors)/iFS
INL-
Positive Relative Accuracy
-2
Measure 10
(IPosltlve bit errors)IIFS
Measure 10
(INegatlve bit errors)IIFS
Positive and Negative
Negative Relative Accuracy
Measure Ie
INLNegative Bit Errors
Bit Error Difference
ro
NL-
Measure 10
NI.-
IINL-I + I ~INL I
Measure iQ
IIiiII.-1 + I ~IiilI.l
Bit Error
Bit error is the deviation of the analog output from its Ideal value (after
zero-scale and full-scale errors have been calibrated out) when turning on an
IndiVidual bit. This IS measured for all n bits.
Bit error (analog value) = Vn - (FSRl2 n)
Where Vn = analog output with bit n on only
FSR = full-scale range
n = number of bits
Summation Nonlinearity (INL)
Summation nonlinearity IS the sum of all positive bit errors or all negative bit
errors, whichever Is larger By summing up all the bit errors in one direction,
you obtain the worst possible nonlinearity (I e. if bit 2 lsI LSB high and bit4 is
1/2 LSB high. then bits 2 and 4 together Will be 1 1/2 LSBs high. This IS
essentially the same as Integral nonlinearity since the bit errors are superImposed on each other to give the worst case nonlinearity.
11-210
1/86, Rev. A
~
JM31510111301I11302 JAN I-BIT MULTIPLYING DlA CONVERTER
ELECTRICAL CHARACTERISTICS
temperature range = -55 0
C to + 1250 C.
at ±VCC= ±15Vdc; Source resistance = 50 ohms; IREF= 2.0mA; Figure 1; Ambient
unless otherwise noted.
01 LIMITS
PARAMETER
SYMBOL
IFSR,
IFSR,
Output Current Range
IFSR2
IFSR2
Reference BIas Current
CONDITIONS
All input bits high. Measure 10 •
-Vee =-10V. VREF =lSV
All Input bIts low. Meesure i;;:
-Vee = -10V, VREF = lSV
All input bIts hIgh, Measure 10
-Vee =-12V, VREF = 2SV
All input bits low, Measure i;;
-Vee =-12V, VREF = 2SV
UNITS
2.1
mA
4.2
4.2
0
pA
I'H
All input bits Y,N = 18V, each
Input meesured separately
-0 OS
10
-0 OS
10
,.A
I,L
All input bits Y,N = 10V, each
Input measured separately
-10
All input bits high, Measure la,
V ,O = 18V
All Input bits low, Measure
V,O = 18V
i;;:
1.90
All input bits high, Measure IOo
V,o =-10V
All Input bits low, Meesure iQ.
V,o =-10V
1.90
Low Level Input Current
IFS+
IF8+
IFs IF!>
~IFse
Change In Full Scale Current
Due to Voltage Compliance
~IFSC
PSSIF8+ 1
PSSIFS+l
PSSIFS+2
PssIFS+2
Pss I FS-l
Power Supply SensitivIty
From-Vee
MAX
-3
High Level Input Current
" Power Supply Sensitivity
From+Vee
2.1
02 LIMITS
MIN
0
All Input bits low
Full-Scale Current
At -10V Compliance
MAX
-3
I REF -
Full-Scale Current
At + 18V Compliance
MIN
Pss IFS -l
PSS IFS -2
All input bits high, Measure 10 •
2SoC S TAS 12SoC
TA =-55°C
V'a = 18V to -10V
All Input bits low, Measure i;;'
2SoC S TAS 12SoC
TA=-SSoC
V'a = 18V to -10V
All input bits high. Measure la,
+Vee= 4.SV to +5.SV, -Vee =-18V
All Input bits low, Measure i;;:
+Vee = 4.SV to +S.SV. -Vee = -18V
All input bits high, Measure la,
+Vce = 12V to 18V, -Vee = :l8V
All input bits low, Measure la,
+ Vee = 12Vto 18V, -Vee =-18V
All Input bits high, Measure la,
+Vee = 18V. -Vce = -12V to -18V
All input bits low. Meesure
+ Vee = 18V, -Vee=-12V to -18V
All Input bits high. Measure IOo
+ Vee = 18V, -Vee = -4.5V to -S.5V
IREF= lmA
208
1.94
pA
2.04
mA
2.08
1.94
2.04
mA
~
aU~
C)
~
a
-4
-8
8
-4
-8
4
8
-4
-8
4
8
-4
-8
4
8
-4
4
-4
4
-8
8
-8
8
-8
8
-8
8
-2
2
-2
2
4
~
pA
~
C)
.....
Q
pA
All Input bits low, Measure
+Vee = 18V, -Vee = -4.SV to -S.5V
IREF= lmA
11-211
~
a
ro:
10
Pss IFS-2
-10
en
1/86, Rev. A
---------I~ JM3a510/11301/11302 JAN a·BIT MULTIPLYING D/A CONVERTER
ELECTRICAL CHARACTERISTICS at ±Vcc = ± 15Vdc; Source resistance
temperature range = -55 0 C to +1250 C. unless otherwise noted.
= 50 ohms; IREF = 2.0mA; Figure 1; Ambient
>-__-+________
~K4
NOTES.
1. THE REFERENCE D/A CONVER·
TER SELECTED SHOULD HAVE
A RESOLUTION OF 8 BITS OR
MORE, AND A LINEARITY OF
0.015% OR BETTER.
2, THE VOLTAGE REFERENCE
SHOULD HAVE AN ACCURACY
OF ±O.02% OR BETTER.
3. ALL RELAYS ARE SHOWN IN
THEIR NON·ACTUATED STATE.
Figure 1. Test Circuit For Static Tests
+5V FOR VOUT
OV FOR Vi5UT
VOUT
-["J-
VIN
10V~--- - 90%
tr< 10ns
Y,N
-
-
-
10%
OV
*\.__
OV - - - - - .
\---O.5V
VOUT OR
-2V
~O~T ___il~
1.5V
-.jilt~
Figure 3. Test Circuit For Slew Rate, Device Types 01, 02
11·212
1/86, Rev. A
----------I~ JM3a510/11301111302 JAN a-BIT MULTIPLYING D/A CONVERTER
rVI. (SEE NOTE 11
I
---------.,I
OPTIONAL WITH fET PROBE
I
I
I
I
I
I
I
______ ..JI
I
I
1kll
I
O.7V
1k1l
'----
NOTES:
100k.Q
1
2kn
FOR TURN·ON VI. = 2.7V; FOR TURN-OFF VI. = D.7V
2.
MINIMIZE CAPACITANCE AT THIS NOOE BY USING
SHORT RUNS AND ADEQUATE SPACING BETWEEN
RUNS.
DIODES MUST BE SCHOTIKV TYPE (MBD 501 OR
EQUIVALENT).
BANDWIDTH OF OSCILLOSCOPE. USED FOR WAVEFORM MEASUREMENT SHOULD BE SOMHz MINIMUM; SATURATION OF PREAMP MUST BE AVOIDED.
3.
4.
-16V
_I I _
r-
----J"
:3
tr = tf
_ I
~,f
< 10n5
I
4-
---:~90%~
ov VIN
VaUT
: I
::
::
~
,
I
I
I
I
1
!-'SHL-j
:
±1/2LSB
1f{ff
'I
5°~l
~
~
tPHL
-------+---,'
~-------~
I
" 'PLH
1""":
~----~--I
T,'/2LSB '" 4mV
f.-tSLH--..t
TURN-ON
TURN-OFF
Figure 2_ Test Circuit For Propagation Delay and Settling Time, Device Types 01 and 02
III
BURN-IN
+18V
Devices supplied by PMI have been subjected to burn-in
per method 1015 of MIL-STD-883 using test condition C or
test condition F with the circuit shown in Figure 4.
C2
F
C1
16
R1
15
"
13
12
11
10
OUT.
R1=9kfl±5%
-18V
C1 "O.OOl~F. 50V
C2 = 0 01~F, 50V
Figure 4. Test Circuit, Burn-In and Operating Life Test
11-213
1/86, Rev_ A
Table of Contents 1
Ordering Information 2
Product Assurance Program 3
Industry Cross Reference 4
Operational Amplifiers 5
Instrumentation Amplifiers 6
Voltage Followers/Buffers 7
Voltage Comparators 8
Matched Transistors 9
Voltage References 10
Digital-to-Analog Converters 11
Analog-to-Digital Converters 12
Analog Switches/Multiplexers 13
Sample-and-Hold Amplifiers 14
Special Functions 15
Communications Products 16
Package Information 17
Sales Offices, Representatives and Distributors 18
AID
CONVERTERS
· .
PreCISIon
12-3
Introduction
12-3
Definitions
12-7
ADC-910
High-Speed "Microprocessor
Compatible" A/D Converter
12-19
ADC-8208
Microprocessor-Compatible 8-Bit
CMOS A/D Converter
12-2
AID
CONVERTERS
Precision Monolithics Inc.
INTRODUCTION
supply sensitivity, and noise. Proper circuit layout
and grounding are also important factors in
achieving rated performance.
Analog-to-digital converters (A DC) translate
analog input voltages into an equivalent digital
value. PMI's ADCs use the general purpose
successive approximation conversion (SAC)
technique. The basic SAC architecture consists of
a DAC, comparator, input scaling resistors, and a
successive approximation register. A clock and a
voltage reference make a complete ADC system.
PMI uses both bipolar and CMOS technologies to
optimize ADC designs. The bipolar technology
lends itself to high speed ADC conversion and
provides the complete ADC function including an
internal reference. The CMOS technology offers
ADC designs with very low power consumption
and good interface versatility at lower prices. PMl's
improved bipolar and oxide-isolated CMOS
processes offer the best conversion speeds in the
SAC architecture.
Aperture- The period of time during which an
analog input to an ADC should not change more
than 1/2 LSB. Determines maximum sampling
frequency of the ADC.
ADC-An acronym for Analog-to-Digital
Conversion, sometimes written as AID.
Binary Coding-The digital output of an ADC is
considered binary-coded when outputs start at all
zeros for a zero-scale analog input counting up to
all-ones' output code for a full-scale analog input
signal.
Bipolar Mode-An ADC configured to convert
both positive and negative input Voltages.
Bipolar Offset-The analog displacement of one
half of full scale range when the ADC operates in
the bipolar mode. The offset is generally derived
from the converter reference circuit.
A SAC ADC has inherent ratioing capability
between the input voltage and the input reference
level. The digital output is proportional to VINIVREF.
Important criteria for selection of AID converters
include accuracy, conversion speed and resolution.
Other requirements include temperature stability,
output coding, output data format, reference
stability, clock and power needs.
At the digital output many interface data formats
are available to match the wide variety of
application needs. The ADC-910 provides a very
complete microprocessor-controlled interface
which contains data registers, control registers and
hand-shaking lines. This architecture provides a
complete microprocessor compatible system that
allows total software control of all ADC functions.
For stand-alone applications the ADC-8208 offers
direct data output, start conversion and very low
power dissipation.
Bus-A parallel path of binary information signalsusually 4, 8, or 16 bits wide.
Byte-A binary digital word often 8 bits long.
Chip Select (CS)-A logic input signal activating
data or control information transfer between the
ADC and the digital circuitry. This signal is usually
active low designated by a bar over the top of (CS).
CS is used in conjunction with additional qualifying logic signals to determine the exact activities
to take place.
Clock (CK)- The operation of the successive
approximation conversion process requires a
clock. The clock sets the basic conversion rate.
Some ADCs have an internal clock, using an
external capacitor to set the frequency. Most ADCs
have an external clock input.
Code Width-The amount of input voltage change
which occurs between output code transitions
expressed in LSBs of full scale. The ideal code
width is one LSB.
DEFINITIONSANALOG-TO-DIGITAL CONVERTERS
Code Width Uncertainty-The dynamic variation
or jitter in the code width due to noise.
Accuracy-ADC total accuracy consists of the
sum of integral nonlinearity (INL) error, zero error,
gain error and reference error specifications. The
INL is the most critical specification since no
additional user calibration can be easily performed.
Additional specifications affecting ADC device
accuracy includes zero drift, gain drift, power
Coding- The format of the ADC digital output
data. Common formats include binary, offset
binary, complementary binary, two's complement,
low byte and high byte.
12-3
AID
CONVERTERS
Precision Monolithics Inc.
Command Register-An internal register of the
ADC that can be programmed by the user to select
various modes of operation. For example, unipolar
or bipolar conversion selection, range selection,
data output format, etc.
Half-Step Offset-The half-step offset is necessary
in ADCs to center the analog input voltages half
way between the output code transition pOints.
The SAC converter architecture inherently has a 1
LSB transition voltage for the first code change if a
half-step offset is not inserted.
High Byte (HB)-In ADCs with resolutions greater
than 8 bits, some products are offered in a high
byte, low byte format to simplify interface to 8-bit
microprocessor systems. The high byte contains
the most significant bit and some or all of the
upper 8 bits of the ADC output. Generally bits are
loaded in a right or left justified format. Individual
product data sheets should be consulted.
Control Lines-Digital input/output pins that
activate/monitor and control ADC operation. For
example, chip select, write, low byte, high byte,
start convert, end of conversion, conversion
complete, busy, read, etc.
Conversion Complete (CC)- This digital output
signal indicates the end of conversion. When this
signal is in the opposite state the ADC is considered
to be in the "busy" state.
Input Impedance (RIN)-Analog input resistance
of the ADC. In SAC converters input impedance is
primarily resistive, but should be buffered by an
amplifier with a low output impedance at the clock
frequency of the SAC ADC to maintain a stiff input
voltage to the ADC.
Conversion Time (tc)- The amount of time
elapsed from the start-conversion control signal
until the conversion complete signal occurs.
Differential Nonlinearity (DNL)-The worst-case
deviation of distance between transition voltages
from the ideal 1 LSB code width. The parameter
uses units of LSBs. DNL is one of an ADC's errors
which cannot be removed by user adjustments.
Input Range-The analog voltage input range
which results in a zero code to full-scale code
digital output in a natural binary-coded ADC. This
parameter is identical to full-scale range. Common
preset ranges include 0 to 10V, -10 to +10V, -5 to
+5V, etc.
Drift-See Gain Drift, Zero Drift, and Offset Drift
specifications.
End Of Conversion (EOC)-This digital output
signal flags the conversion complete and data
ready condition of an ADC.
Integral Nonlinearity (INL)- This error
specification is a measure of the straightness of
the ADC transfer function. It is measured as the
worst-case deviation in LSBs from a straight line
drawn through the center of the first and last code
widths. INL is one of the key error specifications of
an ADC which cannot be calibrated by the user.
Left Justified Data-In the byte-oriented dataoutput format, data bit sets shorter than 8 bits are
placed starting in the left side of the data output
transfer register. This could apply to the upper or
lower byte. For example, a 12-bit ADC will have 4
extra bits which could be left justified.
Full Scale (FS)-Maximum input voltage of an
ADC. A full-scale input voltage to a natural binarycoded ADC outputs the all-ones code.
Full-Scale Error- This parameter applied to ADCs
is the same as the gain error specification. See
Gain Error.
Full-Scale Range (FSR)-The difference between
maximum and minimum analog values for an ADC
input.
Gain Drift- The change in the full-scale transition
voltage measured over the operating temperature
range This parameter has units of % of full scale,
ppm of full scale, or LSB. It may also be expressed
as % of FS/oC, ppm of FS/oC, etc.
Least Significant Bit (LSB)-The binary digit with
the smallest numerical weighting, normally one
LSB equals full-scale range divided by (2 n), where
n is the number of bits of the ADC. This parameter
may be expressed in millivolts.
Gain Error- The difference between the actual
full-scale transition voltage and the ideal full-scale
transition Voltage. The units of this parameter are
in LSBs or percent of full scale.
Low Byte (LB)-In ADCs with resolutions greater
than 8 bits, some products are offered in a high
12-4
AID
CONVERTERS
Precision Monolithics Inc.
byte, low byte format to simplify interface to 8-bit
microprocessor systems. The low byte contains
the least significant bit and some or all of the low 8
bits of the ADC output. Generally bits are loaded
in a right or left justified format. Individual product
data sheets should be consulted.
the LSB of the ADC which are assigned the same
output code. The ±112 LSB limit to resolution is
known as the fundamental quantization error of an
ADC.
Major Transition-The digital output code change
between one-and-all-zeros code and zero-and-allones code. For example an 8-bit ADC major
transition occurs between the codes 1000 0000 and
01111111 (half-scale).
Reference (VREF)-Reference voltages determine
ADC system's absolute conversion accuracy at full
scale. At other voltages the INL and reference
determine absolute accuracy. References may be
internally or externally supplied.
Missing Code-As an analog input voltage is
swept from zero input to full scale, the output
digital codes should change by 1 LSB as each
transition voltage is reached. If an output code is
skipped, we have a missing code.
Most Significant Bit (MSB)-The binary digit of
the resulting ADC conversion with the largest
numerical weighting. Normally the MSB has a
weighting of one-half full-scale range.
Relative Accuracy-Relative accuracy error,
expressed in LSBs or % of full scale, is the
deviation of the analog value at any code from its
theoretical value after gain and offset is calibrated.
PMI's usage of this specification is identical to the
integral nonlinearity specification.
R-2R Ladder-A resistor network providing the
basic binary-current-division used in SAC ADCs.
Resolution-The resolution of an ADC is the
number of states (2n) that the analog input voltage
is divided (or resolved) into, where n is equal to the
number of bits.
Offset Binary Code-A digital binary code used to
represent plus or minus input polarity analog
voltages. Negative full-scale voltage is assigned allzeros code. Zero input voltage has the MSB high
(logic one) and the remaining bits at zero. Positive
full-scale voltage is assigned all-ones code.
Right Justified Data-In the byte-oriented dataoutput format, data bit sets shorter than 8 bits are
placed starting in the right side of the data output
transfer register. This could apply to the upper or
lower byte. For example, a 12-bit ADC will have 4
extra bits which could be right justified.
Sampling Frequency- The rate at which the ADC
can continuously convert analog inputs into digital
outputs. In SAC ADCs clock frequency and data
transfer overhead determines the sampling
frequency.
Short Cycling-Termination of the conversion
sequence of an ADC to less than the total number
of clock periods required for a full resolution
conversion.
Span-Sometimes used to describe the full-scale
analog input voltage. Some ADCs have resistorselectable analog input ranges.
Status Register-A register indicating current
status of the analog-to-digital conversion with a
busy signal or a conversion complete Signal.
Successive Approximation Conversion (SAC)Successive approximation converters compare an
analog input against an accurately-known binary
Offset Drift-The change with temperature of
analog zero for an ADC operating in the bipolar
mode. It is generally expressed in ppm of FSR/o C
or LSBs.
Offset Error- The error at analog zero for an ADC
operating in the bipolar mode. It has units of % of
FSR or LSBs.
Overrange-When analog input voltages exceed
the input range, an overrange condition is in effect.
Normally the digital output code stays at all ones
for positive overrange and all zeros for negative
overrange with standard binary coding.
Power Supply Sensitivity (PSS)- The change in
the full-scale transition voltage due to a change in
power supply voltage. The units are in LSB, % of
FS per % of supply voltage, or ppm of FS per % of
supply voltage.
Quantization Error-An ADC of n bits can only
identify 2n output codes; however, there exists an
infinite number of analog input values adjacent to
12·5
AID
CONVERTERS
PrCCISJ()lI MOIlOlttlllCS
Inc.
fraction of a reference input. Starting with half the
reference value (the MSB) the converter
determines whether the input is greater than or
less than this value. Next the converter divides the
remaining value in half again determining whether
the input value is in the upper or lower quarter.
This process is continued until all bits have been
tried. The digital result of each trial is a numerical
representation of the analog input.
Successive Approximation Register (SAR)-A
digital circuit that controls the operation of a
successive approximation ADC and accumulates
the output digital word in its register.
Three-State Output Buffer-A digital output circuit
that can be programmed to output a logic low,
logic high or a high output impedance state. These
devices are generally connected to digital buses.
Transition Noise-Width of the transition voltage
region.
Transition Voltage-The transition voltage is the
center of a finite band of analog input voltages
where the digital output code of the ADC toggles
between two adjacent codes.
Unipolar Mode-Operation of an ADC with zero to
full-scale voltage inputs of one polarity only.
Word-A set of binary digits that represent the
fundamental register size of the digital circuits
being used. For example, Z80, 8085, and 6800
microprocessor systems use 8-bit words, while
68000 and 80186 microprocessor systems have
16-bit words.
Zero Drift-The change with temperature of
analog zero for an ADC operating in the unipolar
mode. It is generally expressed in ppm of FS/o C,
or LSBs.
Zero Error-The error at analog zero for an ADC
operating in the unipolar mode. This is a user
adjustable parameter.
12-6
ADC-910
HIGH-SPEED "MICROPROCESSOR COMPATIBLE"
A/D CONVERTER
Precision Monolithics Inc.
PRELIMINARY
read/write inputs and 3 Chip Select inputs to control the 10
data lines is included. Interrupt enable, start conversion and
bipolar/unipolar mode selection are controlled by the data
bus. The use of high-speed Linear Differential Logic results
in fast (6/Ls) conversion time and low power dissipation.
FEATURES
•
•
•
•
•
•
•
•
Includes Clock, Reference, 3-State Buffered Outputs
Fast Conversion Time ............................ 6/Ls
Four Input Ranges .. + /-2.5V, + /-5.0V, +5.0V and + 10.0V
112 LSB INL
No Missing Codes Over Temperature
Low ESD Sensitivity Due to Rugged Bipolar Processing
Software Programmable Unipolar/Bipolar
Easily Interfaced to 8 and 16·Blt /LP Bus
PIN CONNECTIONS
ORDERING INFORMATIONt
PMI MODEL NO.
TEMP RANGE
ADC910AT"
ADC910ET
ADC910GT
-55' C/+ 125'C
-25'C/+85'C
O'C/+70'C
DIGITAL
GNO
(LSB)BO
6
• For devices processed in total compliance to MIL-STD-883, add /883 after
part number. Consult factory lor 883 data sheet.
tAil commercial and industrial temperature range parts are available with
burn-in. For ordering information see 1986 Data Book, Section 2.
21
~~~LOG
18
g~~:ET
17 V REF OUT
16 VAEF ADJUST
GENERAL DESCRIPTION
The ADC-910 is a 10-bit A/D converter designed specifically
for interfacing with microprocessors. 3-state data outputs
allow direct connection to an a-bit data bus in an MSB byte of
a bits and an LSB byte of 2 bits. A command register with
28-PIN HERMETIC DIP
(T-Sufflx)
SIMPLIFIED SCHEMATIC
MSB
LSB
89 BS 87 86 B5 B4 83 B2 B1 80
Y YY
CS3
CS2
?-
START
UNI!SIP
INE
COMMAND
ENABLE
HIGH BYTe
t
!
CLOCK
CClK
V REF IN
V AEF OUT
-
~.
~~~
~e~
--
~
I
'MSB
...........
f-<> V+
ANALOG
.~"
~yFFERS II~~"l
I~"
~- f-<>
GNO
v-
J
VINB
"~
"
R
VINA
COMP
SAR
R
-
3-STATE BUFFERS (81
2R
caMP
OFFSET
2R
REF
V REF ADJ
-
REGISTER
CSi
CLOCK IN
DIGITAL
GNO
.J,-
'\
~
10-BIT OAC
R
~
~7
U
This preliminary product Information Is based on testing of a limited number of devices. Final specifications may vary. Please contact local sales
office or distributor for final data sheet.
12-7
1/86, Rev. A
------1~ ADC-910 HIGH-SPEED "MICROPROCESSOR COMPATIBLE" AID CONVERTER -
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
ADC-910AT/BT •.••..•.•..•.•..•..••• -SS·C to +12S·C
ADC-910ET/FT ...••....•..........••. -2S·C to +8S·C
ADC-910GT/HT •.•.••••...•......•.•... O·C to +70·C
Storage Temperature Range •..•.•....• -6S·C to +1S0·C
Power Dissipation at TA = 12S·C ••...•••..•..•.. 1000mW
Lead Temperature (Soldering, 60 sec) ••...•••••••• 300·C
Supply Voltage (V+) ••••.•.••••••.•..••...•.••••.••.• 6V
ELECTRICAL CHARACTERISTICS at V+
= SV,
V-
Supply Voltage ( V-) •••••••••••••••.•.••.•••..••••..• 6V
V+ to V- ••••.•••••••••.••.•••....•••••..•.•.••.••.• 12V
Logic Inputs ..•.•.•.••••.•••••••.....•••.••• +6V, -0.3V
Logic Outputs (in 3-state) ••.••.••...•.••.•••• +6V, -0.3V
VINA ..•••••...•••...•••..•.•.•.•••.•.••.••••.•.•.• 1SV
VINB •••••..•••••••••••.••..•....•••••••.•.•.••.••. 7.SV
Reference Inputs .•...•••••.•..•••.••.•••.•••.••.•• 3.0V
Digital Ground to Analog Ground Voltage ••.••.•••.• O.SV
= -SV,
VREF
= 2.SV, fCLK = O.SMHz;
= -SS·C to +12S·C apply for
TA
ADC-910AT/BT, unless otherwise noted.
PARAMETER
Integral Nonlinearity
(Note 3)
Gain Drift
(Note 1)
ADC-910BT
MIN
TYP MAX
ADC-910AT
MIN
TYP MAX
SYMBOL
CONDITIONS
INL
TA = 25°C
TA = Full Temp. Range
TCG FS
External Reference
Internal Reference
1/2
3/4
LSB
25
40
4.75V < V+ < 5 25V
UNITS
500
30
50
ppm FS;oC
600
MVIV
Positive Supply Current
1+
30
40
30
40
mA
Negative Supply Current
I-
SO
60
50
60
mA
Reference Line RegulatIon
ELECTRICAL CHARACTERISTICS at V+
= SV,
V-
= -5V,
VREF
= 2.SV,
fCLK
= O.SMHz;
TA
= -2S·C to +8S·C
apply for
ADC-910ET/FT, unless otherwise noted.
PARAMETER
Integral Nonllneanty
(Note 3)
Gain Drift
(Note 1)
ADC-910ET
MIN
TYP MAX
SYMBOL
CONDITIONS
INL
TA =25°C
TA = Full Temp. Range
1/2
1/2
TCG FS
External Reference
Internal Reference
20
35
4 75V < V+ < 5 25V
ADC-910FT
MIN
TYP MAX
UNITS
LSB
500
25
45
ppm FS/oC
600
MVIV
Positive Supply Current
1+
30
40
30
40
mA
Negative Supply Current
I-
SO
60
50
60
mA
Reference Line RegulatIon
ELECTRICAL CHARACTERISTICS at V+
= 5V,
V-
= -SV,
VREF
= 2.SV,
fCLK
= 0.5MHz;
TA
= O·C
to +70·C apply for
ADC-910GT/HT, unless otherwise noted.
PARAMETER
Integral Nonlinearity
(Note 3)
Gain Dnft
(Note 1)
ADC-910GT
MIN
TYP MAX
ADC-910HT
MIN
TYP MAX
SYMBOL
CONDITIONS
INL
TA = 25°C
TA = Full Temp. Range
TCG FS
External Reference
Internal Reference
10
25
10
25
ppm FS/oC
4.75V < V+ < 5 25V
1/2
3/4
UNITS
LSB
300
300
MVIV
PositIVe Supply Current
1+
30
30
mA
Negative Supply Current
I-
SO
50
mA
Reference Line Regulation
12-8
1/86, Rev. A
!EM!) ADC-910 HIGH-SPEED "MICROPROCESSOR COMPATIBLE" AID CONVERTER ELECTRICAL CHARACTERISTICS at V+ =
5V, V-
PRELIMINARY
= -5V, VREF = 2.5V, fCLK = O.5MHz; TA = 25°C, unless otherwise noted.
ADC-910AT/ET/GT
CONDITIONS
Resolution
N
TA ~ Full Temp Range
10
10
Bits
TA ~ Full Temp Range (Notes 2, 3)
10
10
Bits
No MIssing Codes Guaranteed
Gain Error
Unipolar Mode
Offset Error
Bipolar Mode
Offset Error
G FSE
VRE ,
V ZSE
TA
~
~
MAX
ADC-910BT/FT/HT
SYMBOL
Resolution for which
MIN
TYP
PARAMETER
MIN
TYP
MAX
2 500V (Notes 2, 3)
UNITS
LSB
1/2
Full Temp Range
LSB
VasE
1.5
LSB
15
LSB
Bipolar Mode ZeroScale Offset Drift
TCVzs
TA ~ Full Temp Range (Note 1)
Analog Input Impedance
RINA
Pin 20
35
Analog Input Impedance
RIN B
Pin 19
175
25
35
175
25
35
kfl
Reference Input Resistance
RREF
Pin 22
175
2.5
3.5
175
25
35
kfl
Reference Voltage Output
VRE,OUT
Pin 17, Untnmmed
245
250
2.55
245
2.50
255
V
RT~
±50
Reference Voltage
Tnm Range
Reference Output
Supply Sensitivity
Negative Power
TA
+P ss
= Full
Temp Range
4.5V to 5.5V, VRE , External
mV
15
15
mV/mA
1/2
1/2
LSB
C/J
~
~
E2
~
0
U
.....l
~
,......
C)
,......
-P ss
-4.5V to -5 5V, VRE , External
Conversion Time
Tc
fCLK
~
1 MHz (Note 5)
ConverSion Time
Tc
fCLK
~
0 5MHz (Note 6)
Supply Sensitivity
kfl
±50
1mA< I < SmA,
Load Reg ulation
Positive Power
10kfl
35
Digital Input High
V 1NH
TA ~ Full Temp Range
Digital Input Low
V1NL
TA ~ Full Temp Range
1/2
LSB
~s
12
20
12
Digital Input Current
IINH
TA ~ Full Temp Range
04
IJNL
TA ~ Full Temp Range
to
Digital Output High
VOH
I OH ~ -400~A,
TA ~ Full Temp Range
Digital Output Low
VOL
10L ~ 16mA,
TA ~ Full Temp Range
Digital Output Current
10H
VOH~24V
Digital Output Current
10L
VOL ~ 04V
Three-State
Output Leakage
102
TA
24
V
08
V
20
~A
04
20
37
01
10
24
04
-400
Full Temp Range
~s
2.0
08
Digital Input Current
~
t/2
~A
37
01
V
04
-400
V
~A
16
16
mA
10
10
~A
NOTES:
Change In 25°C value from 25°C to TM,n or TMax
Tested In the 5V unipolar mode at 6~s conversion time
Tested In the ±5V bipolar mode at 12J.ts converSion time
Measured mdlvldually on V+ and V- supplies
Applies to 5V Input unipolar operation, see Figure 1 for connections
6 Applies to 10V mput unipolar operation, and ±5V/±lOV Input bipolar
operation, see Figure 1 for connections
12-9
1/86, Rev. A
Q,
0
~
C)
0
~
-<
II
------1m
ADC-910 HIGH-SPEED "MICROPROCESSOR COMPATIBLE" AID CONVERTER - PRELIMINARY
APPLICATIONS INFORMATION
CIRCUIT OPERATION (refer to the simplified schematic)
The ADC-910 uses a successive approximation type A/D
conversion routine. When a start command is received by the
command register, the SAR, DAC and comparator begin a
bit-by-bit trial against the analog input voltage. When all ten
bits have been tried, the ten data outputs of the SAR will
contain a 10-bit digital representation of the analog input
voltage.
When the conversion is complete, a read command and a
chip selection will output the data through the 3-state output
buffers. Selecting CS1 will output the eight MSBs (the high
byte) and selecting CS2 will output the two LSBs (the low
byte). Selecting both CS1 and the CS2 will cause all ten data
bits to be output through the 3-state output buffers.
When the conversion is complete, the SAR sends an end of
conversion (EOC) signal to the command register, which
turns on the interrupt output open-collector NPN transistor
(INT), providing the interrupt disable bit (lNE) is set to "0".
The EOC Signal is also multiplexed into the input of the
3-state buffer for bit 9 (B9). Also, at this time, the overrange
signal appears at the SAR output and IS multiplexed into the
input of the 3-state buffer for bit 8 (B8). These two bits of
information compnse the status register, which is multiplexed to the data bus with a read command and a selection
of CS3.
Unipolar/bipolar mode selection and the enabling/disabling
of the interrupt output is done when the start of conversion
command is entered. In the unipolar mode, the IMSBcurrent
source is turned off. For bipolar mode operation, the I MSB
current source is applied to the summing mode of the
comparator. This provides the proper offset of IMSB to do a
bipolar conversion.
BASIC CONNECTIONS (refer to Fig. 1)
Power Supply Connections: The ADC-910'is operated on ±S
volt power supplies. +S volts is applied to pin 1S and -S volts
is applied to pin 23. These lines should be bypassed near the
device with a 0.1/LF capacitor in parallel with a large value
capacitor such as 10/LF.
Analog and Digital Ground: Separate analog and digital
grounds are provided to maintain optimum noise rejection.
Care should be maintained to insure that digital switching
noise is not introduced into the analog ground line. This can
be accomplished by making the final ground point as close
(physically and electrically) as possible to the analog ground
pin of the ADC-910.
Analog Inpuls: There are two analog voltage inputs to the
ADC-910. VINA (pin 20) accepts input Signals between 0 volts
and + 10volts in the unipolar mode and between-S volts and
+S volts in the bipolar mode. V INB (pin 19) accepts input
signal levels between 0 volts and +S volts in the unipolar
mode and between -2.S volts and +2.S volts in the bipolar
mode. The input resistance is nominally Skfl forV INA and 2.Skfl
for VINB. The comparator offset pin (pin 18) is left open when
using VINA, and is tied to analog ground when using VINB.
12-10
1/86, Rev. A
-----t~ ADC-910 HIGH-SPEED "MICROPROCESSOR COMPATIBLE" AID CONVERTER -
FIGURE 1: BASIC CONNECTIONS
PRELIMINARY
*
+
Ace-91O
...!i
...E.
..E.
BS
V+
B8
V 1NA
~
B7
VINB
p!-----o VIN (5V RANGE)
....!!
B6
....!!'.
2
2
-2.
DATA
LINES
+5V
6k(l
B4
VREF OUT
B3
V REF IN
B2
B,
-2.
BO
2.
,
TO MICROPROCESSOR
2
WR OUTPUT
('
1
~
~
~
ANALOG
GND
f2---.
SWITCH OPEN FOR
O_IOV INPUT RANGE.
SWITCH CLOSED FOR
0-5V INPUT RANGE.
10kn
'i7
iNT
DIGITAL
GND
elK IN
4
t:-----a
+5V
25
CCLKn
RD
J.
_
-
~OOPF - FOR INTERNAL CLOCK
WR
CSi CS2 CS3
v-
23
~g~~:Ji~t~t2L5 ~~O~~'
-5V
~
,2Sf 3
ADDRESS BUS' \
VIN (10V RANGE)
~
VREF ADJ
AD OUTPUT
TO MICROPROCESSOR
'5
CaMP 18
OFFSET
B6
~
TO MICROPROCESSOR
rna
CBVPASS
+5V
CBYPASS
ADDRESS
DECODER
FIGURE 2: START CONVERSION AND OPERATING MODE SELECTION
(WRITE MODE WR = "LOW", CS3 = "LOW")
MSB
B9 B8
LSB
B7
B6
BS
B4
B3
B2
Interrupt) (UniPOlar/)
( Disable/
BI polar
Enable
Select
B1
BO
Start)
( Bit
,----,-I
X 1x--,---I
X --,-----,-I
X I--,---x
1 _ 0-,---0---,---------,I
1,----,X 1x--,--I
X --'----1.1
X I---,--x
1 ~--,-----,I
[EJ
[EJ
Start Conversion,
Bipolar Mode,
Interrupt Enabled.
Start Conversion,
Unipolar Mode,
Interrupt Disabled.
x = "Don't Care"
FIGURE 3: READING DATA AND STATUS
(READ MODE RD = "LOW")
LSB
B1
BO
CS1 = "Low"
Read High Byte
CS2="Low"
Read Low Byte
CS3 = "Low"
Read Status
12-11
1/86, Rev. A
------l1fMD
ADC-910 HIGH-SPEED "MICROPROCESSOR COMPATIBLE" AID CONVERTER - PRELIMINARY
FIGURE 4: ADC-910 TIMING DIAGRAMS
(a) Write Cycle
SAR/R~SEBT DATA
LATCHED
I
2ND
3RD
4TH
5TH
6TH 7TH
STATUS DATA
10TH READY
8TH 9TH
\
CLOCK
eS3
-'*, :'
---:-"'1:.-__
, '
,I[
, twc -
I
,
r-
I
, ,
,
I
tWR - :
200ns MIN
tel - 150ns TVP
tWR -lOOns MIN
tOH -OnsMAX
tos - lOOns TYP
(b) Read Cycle
"\-I-_ _ _f
I
'~--------------
~
,I
,,
:+
~--------~,-'-,
I
I
: i
I
D A T A - - - - - - - - - + : - + - ! ~~~3=-S~T~AT~E~-----------
tRI_:
tRA---.1
tAl - 1500s TYP
I
I
tRA - 200ns MAX
tRW -150ns MIN
ij
\
I
I
-I
jtRW-:
tOF _lOOns TYP
:
*--: :
I
r---tOF
i
(c) Stand-Alone
STATUS DATA
READY
\
CLOCK
,
,
,
,
,
I
I
I_I
I I
~tsc
I
I
I
,:--f:.+'------------------+'----:
CS1~
I I41-----------------~1-----WR~I
I
: -: 0-
TNT
I
I'
I
I I
I
I
I
:
I
:
I
~ lOOns....)
I MIN
I
I
I
I
i
t cw
,
I
ct::1
twr-l r-I tww
I, :\.f\...
tsc -
:
I
lOOns MIN
tew - 50ns MIN
tWI - 50ns TYP
tel - 150ns TYP
I
tCI_1
I
:
I
I
'-I
reference adjust pin (pin 16).
Voltage Reference: The voltage reference for the ADC-910 is
nominally +2.5 volts. To use this internal reference, the reference output pin (pin 17) should be tied to the reference input
pin (pin 22). Adjustment of the reference voltage may be
done by applying a 10kO trimpot between the reference output and analog ground with the center tap wiper tied to the
To use an external reference with the ADC-910, simply apply
it to the VREF input pin (pin 22). This voltage should be
bypassed to analog ground with a O.1/-1F capacitor.
12-12
1/86, Rev. A
_ _ _ _~~ ADC-910 HIGH-SPEED "MICROPROCESSOR COMPATIBLE" AID CONVERTER - PRELIMINARY
Clock: For internal clock operation, the external capacitor
(CCLK) sets the conversion rate. The conversion rate graph
provides the relationship of CCLK and temperature to conversion rate. The CCLK capacitor is connected between CCLK
(pin 25) and the V- supply (pin 23), see Figure 1. The clock
input (pin 26) is connected to the V+ supply (pin 15). Internal
clock operation exhibits a conversion time variation from
device to device for a given CCLK, due to capacitor and
internal resistor tolerances of the basic R-C oscillator. For
operation at the upper frequencies of 0.5 and 1MHz, an
external clock input is recommended.
16-bit bus, single 10-bit word reading is possible. When using
an 8-bit data bus, the "high byte" and "low byte" can be
multiplexed onto a single 8-bit bus as indicated in Fig. 5.
To read all 10 bits at once, the RD (pin 1). CSl (pin 28) and CS2
(pin 27) are all held "low". This turns on 3-state output buffers
and all data bits can be read.
To read the 8-bit "high byte", the RD (pin 1) and CSl (pin 28)
lines are held "low".
To read the 2-bit "low byte", the RD and CS2 lines are held
"low".
For external clock operation, no clock capacitor is required.
The CCLK pin (pin 25) should be tied to the -5 volt supply and
the external clock is applied to the clock input (pin 26).
1.0MHz clock maximum may be used. This will result in a 6j.Ls
conversion time. Slower clock rates will result in slower
conversion speeds.
Conversion time
Included on the ADC-910 is a 2-bit status register which is
multiplexed onto the data bus on lines B9 and B8.
To read the status register, RD (pin 1) and CS3are held "low".
End of conversion (EOC) is indicated by a "lOW" bit9 (pin 14)
and overrange (OR) is indicated by a "high" in bit 8 (pin 13).
~ 6 x -1f
CALIBRATION (10 Volt unipolar mode only)
To adjust out gain error, a trimpot may be inserted in series
with the analog input voltage input. Assuming a 2.500 volt
reference is applied at the reference input, gain error trimming is accomplished by adjusting the input trimmer so that
the final digital output code transition occurs for an input
voltage of VA = 9.985 volts (this is the transition from
1111111110 to 1111111111). When using the internal reference
or an adjustable external reference, gain error trimming may
be accomplished by adjusting the reference voltage until the
final digital output code transition occurs at VA = 9.985 volts.
CLK
40
35
~
w
:0;
30
25
;::
z
o
20
>
'5
~
8 '0
.
r----.. t-.
l""- t- t--
l"- I"- r--
C EXT - 3000pF
CEXT
=
DRIVING THE ANALOG INPUT
To insure 10-bit accuracy the input to the ADC-910 must be
driven by a source which has an output impedance of less
than 0.5 ohms at 1MHz.
1900pF
CEXT = 800pF
o
-75
-50
-25
25
50
75
100
125
INTERFACING THE ADC-910 TO THE 6502j.LP
(refer to Fig. 5)
An example of direct connection to an 8-bit data bus is shown
in Fig. 5. Notice that the two least significant bits are connected to data bits B3 and B4. This allows a 10-bit data
transfer over an 8-bit bus. In this example, a Synertek Systems SYM-l Educational Computer Board supports the
6502j.LP. The flow charts and op codes for a variety of conversion exercises are shown below.
CHIP SELECT, READ AND WRITE INPUTS (refer to Fig. 2)
Start Commands: To start a conversion the WR input (pin 2)
must be held "low" while CS3 (pin 3) is held "low" and a logic
"high" is applied to bit 2 (pin 7). Another way to start a
conversion is to hold CSl (pin 28) and WR (pin 2) "low" for a
complete clock cycle.
Operating mode selection is done when the start command is
applied. As with the start command, WR and CS3 are held
"low". A logic "high" applied to bit 4 (pin 9) disables the
interrupt and a logic "low" enables the interrupt. A logic
"high" applied to bit 3 (pin 8) selects unipolar mode and a
logic "low" selects bipolar-mode operation.
INTERFACING THE ADC-910 TO THE MC68000
(refer to Fig. 6)
An example of a direct connection to a 16-bit data bus is
shown in Fig. 6. The 10-bit output of the ADC-910 is connected directly to the 10 least significant bits of the MC68000
data bus. In this example a Motorola MC68000 Computer
Board supports the 68000j.LP. A flow chart and assembly
language program is shown below for a simplified 10-bit wide
conversion.
READING DATA AND CONVERSION STATUS
(refer to Fig. 3)
Data can be read in two ways: a Single 10-bit word or in a 8-bit
"high byte" with a 2-bit "low byte". When interfacing to a
12-13
1/86, Rev. A
-----t1£'MD
ADC-910 HIGH-SPEED "MICROPROCESSOR COMPATIBLE" AID CONVERTER - PRELIMINARY
FIGURE 5: ADC-910 INTERFACE TO 6502~P ON SYM-1 BOARD
+
~CBYPASS
ADC-910
MSB
D7
SYM-l
(6502,uPJ
+5V
DB9
D6
DB8
DS
DB7
D4
DBS
D3
DBS
D2
DB4
DI
I
DO
F
V
Skn
IRQ
~2
R/W
iii
:R>
~
V+
V'NA ~VIN(IOV RANGE)
V ,NB ~VIN(5V RANGE)
COMP
OFFSET
V REF OUT
V REF IN ~
DB3
DB2
V REF AOJ
DBl
r---:
GND ~
~7
DIGITAL
GND
CCLK~
WR
1:
V
CBVPASS~
74LS138
L
I
Y4 ~C5A
Y5 $1801
8
VS
G2
V7
*
CLOCK
AD
¢
Gl
10kn
ANALOG
DBO
CS1CS2CS3
II
SWITCH OPEN FOR
O....10V INPUT RANGe.
SWITCH CLOSED FOR
O.... 5V INPUT RANGE.
INT
Al AD
A
'1
~
r---
$1802
$1803
ADDRESS
DECODER
FIGURE 6: ADC-910 INTERFACE TO MC68000 COMPUTER BOARD
+
I':" CBYPASS
ADC-910
MSB
DO
Me6S00a
+5V
DB9
V+
08
DB8
07
D87
V'NA
V ,NB
DS
DB6
DBS
OFFSET
0,
DB'
VREF OUT
03
DB3
DB2
01
DBl
00
DBO
V REF IN ~
VREF ADJ
r---:
ANALOG
GND
r---
SWITCH OPEN FOR
o.... ,ov INPUT RANGE.
SWITCH CLOSED FOR
0 __ 5V INPUT RANGE.
10kn
~7
DIGITAL
GND
......
.....
R/W
L
_ _ ADDRESS
BUS
I
'1
~
r---
CLOCK
lMHzCLOCK
CTACK
RANGE)
Y,N (5V RANGEl
COMP
DS
D2
~VIN(10V
r-----o
V
CCLK
WR
es; CS2 CS3
1
El
f\
\
/
AD
74LS138
E3
V-
1
*
*
-5V
BYPASS
C
ADDRESS
DECODER
OR GATE
OPEN COLLECTOR
r
12-14
1/86, Rev. A
----l~ ADC-910 HIGH-SPEED "MICROPROCESSOR COMPATIBLE" AID CONVERTER -
PRELIMINARY
ADC-910 INTERFACE SOFTWARE AND FLOW CHART FOR 8502I'P (SYM-1)
Unipolar Mode, Interrupt Disabled
PC
MNEMONIC
OPCODE
COMMENT
0302
0304
0307
0308
0309
030C
030F
0312
0314
0317
LDA#$07
STA$1803
NOP
NOP
LDA$1801
STA$03AO
LDA$1802
AND#$03
STA$03A1
JMP$0302
A907
8D0318
EA
EA
AD 0118
8DA003
AD 0218
2903
8D A1 03
4C 02 03
Select Mode
Start Conversion
Wait 21'S
Wait 21'S
Read High Byte
Store High Byte
Read Low Byle
Mask Bits B7-B2
Store Low Byte
Goto 0302
1/86, Rev. A
12-15
----
-
-
-
--- -
~
~
--
-----~-
------1~ ADC-910 HIGH-SPEED "MICROPROCESSOR COMPATIBLE" AID CONVERTER -
PRELIMINARY
ADC-910 INTERFACE SOFTWARE AND FLOW CHART FOR 6502}tP (SYM-1)
Polled Mode, Overrange Test
PC
MNEMONIC OPCODE
COMMENT
0200
LDA#$OX
A90X
0202
0205
0208
020A
020C
020F
0211
0213
0216
0219
021C
021F
STA$1803
LOA$1803
ANO#$80
BNE-7
LOA$1803
AND#$40
BEQ+3
JMP$0227
LDA$1801
STA$024E
LDA$1802
AN 0#$03
800318
AD 0318
2980
DO F9
AD 0318
2940
FO 03
4C 27 02
AD 0118
80 4E 02
AD 0218
2903
0221
0224
STA$024F
JMP$0200
80 4F 02
4C 00 02
0227
022A
LDA$1800
JMP$0200
AD 00 18
4C 00 02
Select Mode: X =
1,3,5 or 7 (see below)
Start Conversion
Read Status Register
Mask for EOC Bit
Loop Until EOC
Read Status Reg ister
Mask for OR Bit
If Not OR, go to 0216
Else Go to 0227
Read High Byte
Store High Byte at 024E
Read Low Byte
Mask for 2 LSBs
(Low Byte)
Store Low Byte at 024F
Loop Back to Start
(0200)
Light LED for OR
Loop Back to Start
(0200)
High Byte
Low Byte
024E
024F
Mode
X=1:
X=3:
X=5.
X=7:
12-16
Selection:
Bipolar Mode, Interrupt Enabled
Unipolar Mode, Interrupt Enabled
Bipolar Mode, Interrupt Disabled
Unipolar Mode, Interrupt Disabled
1/86, Rev. A
------t~ ADC-910 HIGH-SPEED "MICROPROCESSOR COMPATIBLE" AID CONVERTER -
PRELIMINARY
ADC-910 INTERFACE SOFTWARE AND FLOW CHART FOR 6502",P (SYM-1)
Interrupt-Driven Conversion
INTERRUPT SERVICE ROUTINE:
PC
MNEMONIC OPCODE
0200
0202
0205
0207
020A
LOA#$02
STA$A679
LOA#$10
STA$A678
LOA#$03
A902
8079 A6
A912
80 78 A6
A903
020C
020F
STA$1803
JMP$20A
800318
4COA02
COMMENT
Set Interrupt Vector
Select Mode (Unipolar,
Interrupt Enabled)
Start Conversion
Jump to 20A
(Loop Until Interrupt)
Interrupt Service Routine
0212
0215
0218
021B
0210
0220
0222
0225
LOA$1801
STA$024E
LOA$1802
ANO#$03
STA$024F
LOA#$03
STA$1803
RTI
AD 0118
804E02
AD 0218
2903
80 4F 02
A903
800318
40
Read High Byte
Store High Byte at 024E
Read Low Byte
Mask Out Bits 9-4
Store Low Byte at 024F
Select Mode
Start Conversion
Return from Interrupt
~
~
~
0
U
~
......
0
......
Q,
0
~
0
0
~
12-17
1/86, Rev. A
-----l~ ADC-910 HIGH-SPEED "MICROPROCESSOR COMPATIBLE"
AID CONVERTER - PRELIMINARY
ADC-910 INTERFACE SOFTWARE AND FLOW CHART FOR 16-BIT/LP
MC68000 Computer Board Start Sequence
PC
MNEMONIC
COMMENT
1000
1002
1008
100A
100C
100E
1014
MOVEQ #12, DO
MOVE DO, $50000
NOP
NOP
NOP
MOVE $20000, 01
ANDI #1023, 01
Select Mode*
Start Conversion
1008
JMP $1000
Delay
Read Data
Mask out B15-Bl0
leaving B9-BO
Jump to 1000
* Loading a decimal 12 Into DO will apply the following binary word to the
command register at the start of the converSion'
89888786858483828180
0000001100
This results
In
unipolar mode selection with the Interrupt disabled.
ADC-910 INTERFACE SOFTWARE AND FLOW CHART FOR 16-BIT/LP
MC68000 Computer Board Polling Status Register
PC
MNEMONIC
COMMENT
1000
1002
1008
100E
MOVEQ#X,DO
MOVE DO, $50000
MOVE $50000,01
AND #512,01
1012
1016
101C
BNE.L $1008
MOVE $50000,02
AND #256,02
1020
1024
102A
102E
1032
1036
BEQ.L $102E
MOVE 03,$40000
JMP $1000
MOVE $20000,04
AND #1023,04
JMP $1000
Select Mode*
Start Conversion
Read Status Register into 01
Mask for EOC Bit (1000000000 =
512 Decimal)
Loop Until EOC
Read Status Register
Mask for OR Bit (0100000000 =
256 Decimal)
Branch to $102E Unless OR
Light OR Indicator
Start Over
Read and Store 10-Bit Data
Mask Unwanted 6 LSBs
Start Over
'For 81polar Mode with Interrupt Enabled· X = 4 DeCimal
For Unipolar Mode with Interrupt Enabled. X
= 12 DeCimal
For Bipolar Mode. Interrupt Disabled. X = 20 DeCimal
For Unipolar Mode, Interrupt Disabled· X = 28 Decimal
12-18
1/86, Rev. A
ADC-8208
MICROPROCESSOR- COMPATIBLE
8 -BIT CMOS AID CONVERTER
Precisioll MOllolithics Inc.
ADVANCEPRODUCTINFO~TION
FEATURES
The ADC-8208 provides an improved second-source to the
AD7574, providing a three-times faster conversion time.
• Fast Conversion Time ........................ 5f1S
• 8·Blt Accuracy ..•.............. ± 1/2 LSB Max INL
• Memory·Mapped Interface
• Low Power Dissipation ...................... 30mW
• Operates from Single + 5V
• Fits AD7574 Sockets, with Improved Conversion Time
• Space Saving 0.3 Inch Wide 18·Pin DIP
This low power device is ideal for process control, instrumentation, navigation, and general data-acquisition systems.
PIN CONNECTIONS
GENERAL DESCRIPTION
18·PIN CERDIP
(Q·Sufflx)
The ADC-8208 is an 8-bit microprocessor compatible AID converter which uses the successive-approximation conversion
technique to provide a 5f1s maximum conversion time. Control
logic and three-state data output buffers constitute the memorymapped microprocessor interface. The CS and RD control lines
reset the converter, start conversion, and read output data. The
BUSY output indicates conversion in progress.
18·PIN EPOXY DIP
(P·Sufflx)
FUNCTIONAL DIAGRAM
eLK
Vee
?
V,.
60,s
r8>
SA"
rl~1
INTERFACE
& CONTROL
LOGIC
THREESTATE
BUFFERS
DATA OUT
DBO-OB7
r
AGNO
~
b
DGNO
This advance product Information describes a product In development at the time of this printing. Final specifications may vary. Please contact
local sales olllce or distributor for IInal data sheet.
12·19
1/86, Rev. A
Table of Contents 1
Ordering Information 2
Product Assurance Program 3 ':
Industry Cross Reference 4
Operational Amplifiers 5
Instrumentation Amplifiers 6
Voltage Followers/Buffers 7
Voltage Comparators 8
Matched Transistors 9
Voltage References 10
Digital-to-Analog Converters 11
Analog-to-Digital Converters 12
Analog Switches/Multiplexers 13
Sample-and-Hold Amplifiers 14
Special Functions 15
Communications Products 16
Package Information 17
Sales Offices, Representatives and Distributors 18
ANALOG SWITCHES
MULTIPLEXERS
Precision M0l101ithics Inc.
13-3
Introduction
13-3
Definitions
13-7
SW-Ol/SW-02
Quad SPST JFET Analog'switches
13-14
SW-05
Dual SPST JFET Analog Switch
13-22
13-48 MUX-08/MUX-14
8-Channel/Dual 4-Channel JFET
Analog Multiplexers
13-59 MUX-161MUX-28
16-Channel/Dual 8-Channel JFET
Analog Multiplexers
13-69 MUX-88
8-Channel Analog Multiplexer For
PCMCODECs
SW-06
Quad SPST JFET Analog Switch
13-74
13-33 SW-201/SW-202
Quad SPST JFET Analog Switches
13-40
SW-7510/SW-7511
Quad SPST JFET Analog Switches
13-2
DMX-88
8-Channel Analog De-Multiplexer
ANALOG SWITCHES
MULTIPLEXERS
Precision Mouolithics Inc.
INTRODUCTION
Analog multiplexers and switches find applications in data acquisition, metrology, telemetry,
process control and telephony systems. Multiplexers are multiple analog switches which
share a common output. An on-chip address
decoder selects the appropriate input by means
of a binary code. All channels may be deactivated by an enable/disable control pin.
In the past multiplexers/switches have been
manufactured with hybrid, monolithic CMOS or
dielectrically isolated CMOS technologies. The
merging of ion implant techniques with the
standard bipolar process creates a fourth technological alternative - the bipolar-JFET
process. High-quality ion implanted p-channel
FET's can now be compatibly processed with
bipolar devices.
with "RON" placing fundamental limits on signal
acquisition time. Low "RON" and "COUT" insures
minimum elapsed time between the channel
select command and the acquisition of data to
within a specified error band. High cross talk
and off isolation specifications prevent unselected input signals from affecting the signal
path.
PMI offers a wide selection of single-ended and
differential multiplexers and switches. Sixteen
and eight-channel multiplexers as well as differential eight and four-channel devices are available. Dual and Quad SPST switches in normally
closed and open configurations are also available. All devices are pin-for-pin replacements for
many industry standard CMOS devices.
DEFINITIONS
The cost of hybrid devices limits their use to
applications which require the extremely low
"RON" resistance made possible by discrete
FET's. MOS technologies are inherently plagued
by SCR "latch up" problems and analog signal
overvoltage destruction. The use of buried layers and expensive dielectric isolation processing
can eliminate the SCR failure mode, but the
overvoltage blowout problems can be solved
only by adding large series input resistance with
each switch. This increases system errors since
the equivalent "RON" may typically be over
1000 ohms.
JFET switches have no SCR "latch up" tendency
and can withstand analog input overvoltages
while maintaining low "RON" resistance. In
addition, the special handling required with
CMOS devices is not necessary with JFET
switches.
In selecting analog multiplexers, attention must
be paid to several key specs. Break-before-make
switching insures no two-channel inputs are
simultaneously connected. This prevents input
sensor damage and misoperation. Acquiring
analog input signals within a specified time and
error band are primary concerns affected by
"RON" resistance and "COUT" capacitance specifications. A low "RON" insures minimum signal
attenuation and maximum accuracy. The
"COUT" capacitance forms on R-C time constant
Analog Current Range (lA, Is) - The minimum
range of currents the switch is capable of
conducting in the ON state without degrading
ON resistance. It is measured as the value of
conduction current that does not cause more
than a doubling of the RON value for the
product grade.
Analog Input Leakage Current (IS(OFF» - The
algebraic sum of diode current losses from an
OFF-channel source input to the power supplies, ground and through the channel. Specified
IO(OFF). IS(OFF) Test Condition Definitions
10 (OFF)
NOTES
,
SWITCHES TURNED "OFF" VIA ENABLE PIN OF DECODER
LOGIC FOR ID (OFF), IS (OFF) MEASUREMENTS
2
13-3
IS (OFF) IS TESTED AT EACH INPUT (SOURCE) TERMINAL
JPMI)
ANALOG SWITCHES
MULTIPLEXERS
Precision MOllolithics Inc.
Charge Transfer (a) - Charge transfer appears
as a voltage step (pedestal) on the output capacitor after switch turn OFF. The undesirable
charge AC couples directly from the logic-control
driver to the switch contact.
as an absolute value, as the direction of current
flow is not predictable.
The
algebraic sum of diode current losses from an
OFF-channel "0" output to the power supplies,
ground and through the channel. Specified as an
absolute value, as the direction of current flow is
not predictable.
Analog Output Leakage Current (IO(OFF» -
Crosstalk (CT) - The proportionate amount of
cross-coupling from an analog input channel to
another output channel, expressed in dB.
Digital Input Capacitance (COlO) - The capacitance between a digital input and ground.
Analog Output-To-Input Capacitance (COS(OFF»
- The equivalent capacitance which shunts an
open switch effectively between "S" and "0"
output.
Insertion Loss - Insertion loss measures the
amount of signal power absorbed by the switch
ON resistance at a given measurement frequency. Insertion loss is defined in decibels as a
ratio of the output-voltage amplitude (Vo) versus the input-voltage amplitude (Vs) with a
specified load impedance.
Analog Input Capacitance (CS(ON» - The capac-
itance between an analog "S" input and ground
with the channel ON.
The capacitance between an analog "S" input and ground
with the channel OFF.
Analog Input Capacitance (CS(OFF» -
Insertion Loss (dB)
Analog Output Capacitance (CO(OFF» - The
capacitance between the analog (DRAIN) output
and ground with the channel OFF. Highfrequency transmission and output settling time
characteristics are highly influenced by this
parameter in conjunction with RON.
IVol
= 20 log I vsl
At low frequencies this equation simplifies to:
Insertion Loss (dB) = 20
10g~RL:L RON)
Logic "0" Input Current (liNd - The current
flowing into a digital input when a specified lowlevel voltage is applied to that input.
Analog Output Capacitance (CO(ON» - The
capacitance between the analog "0" output and
ground with the channel ON.
Logic "0" Input Voltage Level (VINd -
The maximum (or most-positive) digital low-level input
voltage for which proper operation of the device
is guaranteed.
The range of
analog-voltage amplitudes, with-respect-to
ground, over which the analog switch operates
(ON/OFF) within the RON and leakage specifications - IS(OFF), IO(OFF) and IO(ON) + IS(ON).
Analog Voltage Range (VA) -
Logic "1" Input Voltage Level (VINH) -
The minimum (or least-positive) digital high-level input
voltage for which proper operation of the device
is guaranteed.
Break-Before-Make Delay (tOPEN) - The
elapsed time between the turn-off of one analog
input and the subsequent turn-on of another
input as determined by the appropriate instantaneous change in the digital input code for
both inputs measured between the outputs' 50%
transition points.
Negative Voltage Supply (V-) - The most negative voltage supply with respect to ground.
Positive Voltage Supply (V+) - The most positive voltage supply with respect to ground.
Channel Capacitance (CSS(OFF). COO(OFF» -
The capacitance between the O(S) terminals of
any two channels.
13·4
ANALOG SWITCHES
MULTIPLEXERS
Precision Monolithics Inc.
ON Resistance Variation (~RON) - The variation of ON resistance produced by the specified analog input voltage change with a constant
load current.
OFF Isolation (ISO(OFF}) - The proportionate
amount of a high-frequency analog input signal
which is coupled through the channel of an OFF
device. This feedthrough is transmitted through
COS(OFF) to a load comprised of CO(OFF) in
parallel with an external load. Isolation generally
decreases by 6dB/octave with increasing
frequency.
~RON(%)=
RON @ VA = -10V - RON @ VA = +10V
RON@ VA=OV
X 100%
ON Resistance (RON) - The series ON channel resistance measured between "S" input
and "D" output terminals under specified
conditions.
ON Channel Analog Leakage Current (IO(ON) + IS(ON})
Current loss (or gain) through an ON-channel
resistance creating a voltage offset across the
device. As the direction of current flow is not
predictable, only the magnitude is specified at
various temperature ranges.
ON Resistance Match (RON Match) - The
channel-to-channel matching of ON resistance when channels are operated under identical conditions.
RON Match =
Ri - RAVG
R
AVG
x
Output Enable Delay Time OFF (tOFF(EN}) Multiplexers - The time required to disconnect
the analog output from the analog input determined by the digital address input code. it is
measured from the 50% pOint of ENABLE input
logic change to the time the output reaches
10% of the initial value.
100%
where
N = # of channels in package (i.e., for MUX-08
N = 8, for MUX-16 N = 16, etc.)
Ri = Each channel's ON resistance
Output Enable Delay Time ON (tON(EN}) Mutiplexers - The time required to connect the
analog output to the analog input determined by
the digital address input code. It is measured
from the 50% pOint of the ENABLE input logic
change to the time the output is within 90%
of final value.
1 N
RAVG=
N~
Ri
i=1
Output ON Switching Time (tON) - The time
required to connect the analog output to the
analog input. The time is measured from the
50% point of the logic input change to the
time the output reaches 90% of the final
value.
I(ON} Test Condition Definitions
Output OFF Switching Time (tOFF) - The time
required to disconnect the analog output from
the analog input. The time is measured from the
50% pOint of the logic input change to the time
the output reaches 10% of the initial value.
S2 0---+----<>"
S30---+----<>"
Outpul Settling Time (Is) - The elapsed time for
the analog output to reach its final value within a
specified error band after the corresponding
digital input code has been changed. It is
measured from the 50% point of the logic input
change to the time the output reaches final
value within specified error band.
SEQUENCE EACH
SWITCH ON
NOTES
1
2
TEST IS REPEATED FOR EACH SWITCH WITH SOURCE CONNECTED TO DRAIN
VD '" +10V AND ~10V
13-5
ANALOG SWITCHES
MULTIPLEXERS
JPMI)
Precision Monolithics Inc.
Power Supply Rejection (PSRR) - The ratio of
the change in switch contact voltage (Vo) to the
change in voltage supply (V+ or V-) that causes
it.
+PSRR (dB)
= 20 log
(tNo)
AV+
-PSRR (dB)
= 20 log
( AVO)
AV-
Switching Time (tTRAN) - Multiplexers - The
time required to switch and slew from one
analog input channel to another analog input
with a full-scale differential between inputs with
a high impedance output load. The time is
measured from the 50% pOint of the logic input
change to the time the output reaches 80% of
the final value.
Total Harmonic Distortion (THO) - The ratio of
the signal power at the fundamental frequency
to the signal power of all harmonics observed at
the switch output (Vo) with a pure sinusoid
applied to the switch input (Vs).
13·6
SW-Ol/SW-02
®IPMI)
QUAD SPST JFET ANALOG SWITCHES
(TEMPERATURE COMPENSATED RONI
Precision Monolithics Inc.
FEATURES
vs. analog input signals. The junction FET construction also
reduces static discharge destruction prevalent in CMOS
devices.
•
•
•
•
•
•
•
Low RON vs Temperature ................... 0.03%I O C
Low Absolute RON .............................. 850
Low RON Variation vs Analog Signal ............... 7%
High Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 300ns
Low Leakage Current .......................... 0.2nA
Overvoltage and Supply Loss Protected
SW-01 Is Improved Pin Compatible Device for DG201,
ADG201, LF11201
• SW-02 Is Improved Pin Compatible Device for DG202,
LF11202, IH202
Low RON sensitivity to temperature and voltage is complemented by guaranteed high-speed operation and low-leakage
currents. Logic inputs may operate directly from either
CMOS or TTL logic levels and are supply voltage independent. The SW-01/02 are protected during supply voltage
power loss and against input signal overvoltages.
PIN CONNECTIONS
ORDERING INFORMATIONt
16-PIN HERMETIC DUAL-IN-LINE PACKAGE
FUNCTION
MILITARY'
INDUSTRIAL
N.C.
N.O.
SW01BO
SW02BO
SW01FO
SW02FO
* For devices processed In total compliance to M I L-STD-a83, add /883 after
part number. Consult factory for 883 data sheet
tAil commercial and Industnal temperature range parts are available with
burn-in For ordering Information see 1986 Data Book, Section 2
16-PIN DUAL-IN-LINE PACKAGE
(Q-Package)
GENERAL DESCRIPTION
The SW-01/02 are four-channel single-pole, single-throw
analog switches which offer operating characteristics unavailable in other JFET or CMOS devices. A unique circuit
design provides a nearly constant RON over the full operating
temperature span. RON drift typically runs under 300ppm/o C.
CONTROL LOGIC
SWITCH STATE
SW-02
SW-01
LOGIC
INy
a
The SW-01/02 are pin compatible with the DG201/202. An Ion
Implanted FET switch inherently exhibits low RON variations
NOTE:
ON
OFF
INy
OFF
ON
= INPUT 1-4
SIMPLIFIED SCHEMATIC DIAGRAM (TYPICAL SWITCH)
II
DIGITAL
01
INPUT
INX
13-7
1/86, Rev. A
------------I~ SW-01/SW-02 QUAD SPST JFET ANALOG SWITCHES
ABSOLUTE MAXIMUM RATINGS (TA = 25° C, unless otherwise noted).
Operating Temperature Range
SW-01/02BQ ....................... -55°C to +125°C
SW-01/02FQ ........................ -25° C to +85° C
DICE Junction Temperature (Ti ) ....... -65°C to +150°C
Storage Temperature Range . . . . . . . . . .. -65° C to + 150° C
Power Dissipation (Q-Package) ................. 900mW
Lead Temperature (Soldering, 60 sec) ............. 300°C
Maximum Junction Temperature ................. , 150° C
V+ Supply to V- Supply ........................... , 36V
V+ Supply to Ground .............................. 36V
Logic Input Voltage .........•.. (V- or -4V) to V+ Supply
Analog Input Voltage
Continuous ....... V- Supply -25V to V+ Supply +25V
ForV+=V-=O .......................•....•... ±15V
Maximum Current Through Any Pin ............... 30mA
Peak Current,
(Pulsed at 1ms, 10% Duty Cycle) .........••...... 70mA
NOTE: Absolute ratings apply to both DICE and packaged parts, unless
otherwise noted.
ELECTRICAL CHARACTERISTICS at Vs = ±15V, and TA = 25°C, unless otherwise noted.
SW-01/02B
PARAMETER
SYMBOL
CONDITIONS
MIN
"ON" Resistance
RON
-10V"VA ,,10V, 10 " 1rnA
(Note 1)
RON Match
Analog Voltage Range
VA
Full Temperature Range (Note 8)
ARoN vs VA
ARON
VA" 10V, 10 " lmA
+10
-10
SW-01/02F
TYP
MAX
TYP
MAX
85
100
85
120
n
4
10
4
10
%
10
%
+11
-15
7
MIN
+10
-10
+11
-15
10
UNITS
V
Analog CUrrent Range
IA
VA" 10V
5
5
rnA
Source CUrrent In "OFF" Condition
IS(OFf)
Vs
~
10V, Va
-10V
02
02
nA
Dram Current In "OFF" Condition
10(OFF)
VS
~
10V, Vo ~ -10V
0.2
0.2
nA
VS
~
±10V, (Note 2)
58
58
dB
Leakage Current In "ON" Condition
10(ON)+
~
nA
'S{ON)
"OFF" Isolation
ISO OFF
Test Figure 2
70
70
Crosstalk
CT
Test Figure 3
Turn-On-Tlme
TON
Test Figure, (Note 3)
300
400
300
400
ns
Turn-Off-Time
TOFF
Test Figure 1, (Note 3)
200
300
200
300
ns
Break-Betore-Make Time
TON-ToFF
Test Figure 1, (Note 7)
100
Source Capacitance
CS{OFF)
VA" 10V
dB
100
ns
pF
Drain Capacitance
CO(OFF)
VA" 10V
LogiC "1" Input Voltage
V,NH
Full Temperature Range (Note 8)
Logic "0" Input Voltage
VtNL
Full Temperature Range (Note 8)
55
55
pF
V
08
Logic "1" Input Current
',NH
2 :5V'N :515V
Logic "0" Input Current
I'Nl
0" V,N " 0.8V
Positive Supply Current
1+
(Note 5)
6.3
Negative Supply Current
1-
(NoteS)
32
Ground Current
IG
(NoteS)
3.0
08
V
~A
3
8.0
~A
6.3
9.0
mA
4.5
3.2
5.5
rnA
4.0
3.0
4.5
rnA
NOTES:
VA == OV, 10 ::::; 100.uA SpeCifIed as a percentage of RAVERAGE where
R
3
4
AVERAGE -
RON1 + RON2 + RON" RON4
4
The conditions listed specify the worst case leakage current. The leakage
currents apply equally to source or dram.
Sample tested
Parameter tested at TA = 125°C for military temperature range device
Power supply and ground currents specified for sWitch "ON" or "OFF"
The "OFF" state consumes highest power
TCR~
RON@TwRON@25'C Xl00,
R ON @25'CX(TH 25'C)
where
TH~125'CforBgrade
TH~85'CforFgrade
SWitching IS guaranteed to be break-before-make
Guaranteed by leakage currents and RON tests For normal operation
analog signal voltages should be restricted to less than (V+) - 4V
13-8
1/86, Rev. A
------------l~ SW-01/SW-02 QUAD SPST JFET ANALOG SWITCHES
ELECTRICAL CHARACTERISTICS at Vs
SW-01/02F, unless otherwise noted.
= ±15V, and -55°C:S TA:S + 125° C for SW-01/02B and -25°C:S TA:S 85°C for
SW-01/02B
MIN
PARAMETER
SYMBOL
CONDITIONS
"ON" Resistance
RON
-10V" VA" 10V, ID " 1mA
(Note 1)
RON Match
RON Temperature
TYP
SW-01/02F
MAX
MIN
TYP
120
MAX
UNITS
140
n
10
15
10
15
%
003
020
003
0.15
%/oC
TC R
VA = OV, ID = 100"A, (Note 6)
Source Current in "OFF" Condition
IS(OFF)
Vs = 10V, VD = -10V, (Note 4)
10
10
nA
Drain Current in "OFF" Condition
ID(OFF)
Vs = 10V, VD = -10V, (Note 4)
10
10
nA
Leakage Current in "ON" Condition
ID(ON)+
IS(ON)
Vs = ±10V, (Notes 2, 4)
10
10
nA
Turn-On-Time
TON
Test Figure 1, (Note 3)
500
600
500
600
ns
Turn-Oil-Time
TOFF
Test Figure 1, (Note 3)
400
500
400
500
ns
Break-Before-Make Time
TON-ToFF
Test Figure 1, (Notes 3, 7)
100
LogiC "1" Input Current
IINH
2" V,N " 15V
Logic "0" Input Current
IINL
0" V,N " O.BV
Positive Supply Current
1+
(NoteS)
11
Negative Supply Current
1-
(NoteS)
6
Ground Current
IG
(NoteS)
Coefficient - Average
100
ns
"A
"A
12
mA
mA
6
mA
AVERAGE-
::J
~
Vl
RON1 + RON2 + RON3 RONO
4
~
2. The conditions listed specify the worst case leakage current. The leakage
currents apply equally to source or drain.
3. Guaranteed by design.
4. Parameter tested at TA = 125° C for military temperature range device.
5. Power supply and ground currents specified for switch "ON" or "OFF".
The "OFF" state consumes highest power.
6. TC R=
RON@TH-RON@25°C X100;
R ON @ 25°C X (TH - 25°C)
where
~
p..
......
b
NOTES:
1. VA = OV, 10= 100!,A. Specified as a percentage of RAVERAGEwhere:
R
~
::r::
~
......
~
Vl
0
0
TH=125°CforBgrade
T H = 85°C for F grade
7. Switching is guaranteed to be break-before-make.
~
III
13-9
1/86, Re'!_ A
------------1!EMD SW-01/SW-02 QUAD SPST JFET ANALOG SWITCHES
DICE CHARACTERISTICS
SW-01
SW-02
DIE SIZE 0.100 X 0.088 Inch, 8800 Iq. mill
(2.540 X 2.438 mm, 8.183 Iq. mm)
DIE SIZE 0.100 X 0.088 Inch, 8800 Iq. mill
(2.540 X 2.438 mm, 8.183
mm)
1.
2.
3.
4.
5.
8.
7.
8.
1.
2.
3.
4.
5.
8.
7.
8.
SWITCH (1) ADDRESS (IN1)
SWITCH (1) DRAIN (Dl)
SWITCH (1) SOURCE (Sl)
NEGATIVE SUPPLY
GROUND
SWITCH (4) SOURCE (S4)
SWITCH (4) DRAIN (D4)
SWITCH (4) ADDRESS (IN4)
9.
10.
11.
12.
13.
14.
15.
16.
.q.
SWITCH (3) ADDRESS (IN3)
SWITCH (3) DRAIN (D3)
SWITCH (3) SOURCE (S3)
NO CONNECTION
POSITIVE SUPPLY
SWITCH (2) SOURCE (S2)
SWITCH (2) DRAIN (D2)
SWITCH (2) ADDRESS (IN2)
SWITCH (1) ADDRESS (IN1)
SWITCH (1) DRAIN (Dl)
SWITCH (1) SOURCE (Sl)
NEGATIVE SUPPLY
GROUND
SWITCH (4) SOURCE (S4)
SWITCH (4) DRAIN (D4)
SWITCH (4) ADDRESS (IN4)
9.
10.
11.
12.
13.
14.
15.
18.
SWITCH (3) ADDRESS (IN3)
SWITCH (3) DRAIN (D3)
SWITCH (3) SOURCE (S3)
NO CONNECTION
POSITIVE SUPPLY
SWITCH (2) SOURCE (S2)
SWITCH (2) DRAIN (D2)
SWITCH (2) ADDRESS (IN2)
For additional DICE Information refer to 1986 Data Book, Section 2.
WAFER TEST LIMITS at Vs = ±15V, TA = 25° C, unless otherwise noted.
SW-01/02N
SW-01/02G
LIMIT
LIMIT
UNITS
100
120
o MAX
VA= OV.loS 100!,A
10
10
% MAX
VAS 10V, 'DS lmA
10
10
% MAX
9
mAMAX
4.5
5.5
mAMAX
4.0
4.5
mAMAX
±10
±10
VMIN
PARAMETER
SYMBOL
CONDITIONS
"ON" Resistance
RON
-10V S VAS 10V, 'DS lmA
ARON
RON Match
ARoNvs VA
Positive Supply Current
1+
(Note 1)
Negative Supply Current
1-
(Note 1)
Ground Current
IG
Analog Voltage Range
VA
(Note2)
Logic "1" Input Voltage
V,NH
(Note2)
Lagle "0" Input Voltage
V,NL
(Note2)
Logic "0" I nput Current
ItNL
Logic "1" Input Current
I'NH
2
VMIN
0.8
VMAX
OS V,N S 0.8V
3
!'AMAX
2 S V,NS 15V
3
!'AMAX
0.8
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±15V and TA = 25° C, unless otherwise noted.
SW-01/02N
SW-01/02G
TYPICAL
TYPICAL
90
90
0
VA = 0,1 0 = 100!,A
0,03
0.03
%I'C
PARAMETER
SYMBOL
CONDITIONS
"ON" Resistance
RON
-55'C S TAS 125'C
RON Temperature Coefficient
TC R
UNITS
Turn-On-Tlme
TON
RL = lk, CL = 13pF
300
300
ns
Turn-Off-Time
TOFF
R L = lk. C L = 13pF
200
200
ns
Drain Current in "OFF"
Condition
10(OFFI
Vs = 10V. Vo
0.2
0.2
nA
"OFF" Isolation
ISO OFF
f =500kHz. RL =6800
58
58
dB
Crosstalk
CT
f
=500kHz. RL = 6800
70
70
dB
=-10V
NOTES:
1. Power supply and ground current specified for switch "ON" or "OFF".
2. Guaranteed by RON and leakage current measurements.
13-10
1/86, Rev. A
------------t!EHD SW-01/SW-02 QUAD SPST JFET ANALOG SWITCHES
TEST CIRCUITS
APPLICATIONS INFORMATION
This analog switch employs ion-implanted JFETs in a switch
configuration designed to assure break-before-make action.
The turn-off time is much faster than the turn-on time to
guarantee this feature over the full operating temperature
and input voltage range. Fabricated with Bipolar-JFET processing rather than CMOS, special handling is not necessary
to prevent damage to these switches. Because the digital
Inputs only require a 2V logic "1" Input level, powerconsuming pull-up resistors are not required for TTL compatibility to insure break-before-make switching as is most
often the case with CMOS switches. The digital inputs utilize
PNP input transistors where input current is maximum at the
logic "0" level and drops to that of a reverse-biased diode
(about 10nA) as the Input voltage Is raised above -1.4V.
LOGIC 0 • SN ON
LOGIC
INPUT
tr <.200'
3.0V
'0%
tf'" 20nl
SWITCH
INPUT
SWITCH
OUTPUT
+15V
Vo • Vs RL +
SWITCH
~~s(on)
SWITCH
INPUT
8,
Vs • -6V
O-I-------......---1~ Vo
OUTPUT
GNO
The "ON" resistance, RON, of the analog switches Is constant
over the wide input voltage range of -15V to +11V with
VSUPPLY = ± 15V. For normal operation, however, positive
input voltages should be restricted to 11V (or 4V less than the
positive supply). This assures that the Vas of an OFF switch
remains greater than its Vp, and prevents that channel from
being falsely turned ON. Individual switches are "ON" without power applied.
-15V
(REPEAT TEST FOR IN2. INa AND IN4)
INVERT LOGIC INPUT FOR SW-02
Proper switching requires the "Source" terminal to be connected to the input driving signal.
TEST FIGURE 1
PROGRAMMABLE ATTENUATOR (1 to 0.0001)
VA'" 5VRMS
AT f = 500kHz
Your
1."MSl
RL·8800
101kil
14
"OFF" ISOLATION· 20 LOG
[."~~T]
10kSl
910n
11
13
2.7,10,15
SW-01
V+
V-
TEST FIGURE 2
VA'" 5V RMS
AT f = 600kHz
VD'
(- 1 ATTENUATION WHEN ALL SWITCHES OFF)
CL'" 7pF
VD2
TEST FIGURE 3
13-11
1/86, Rev. A
--------------i~ SW-01/SW-02 QUAD SPST JFET ANALOG SWITCHES
TYPICAL PERFORMANCE CHARACTERISTICS
(SW-01/02)
OVERVOLTAGE
CHARACTERISTIC
POWER SUPPLY
LOSS CHARACTERISTIC
150
4.0
90
V+ '" +15.0V
Vi -'i.DV
=
3.0
100
-'n
I
:5
I
1'01102
2.0
1
"ON" RESISTANCE VI
ANALOG VOLTAGE (VA)
10 _
_VA
1/
Rl=oo
r
I
S
-20 -10
10
: VA
30
40
75
V+ '" +15V
v-
RL =
-5.0
-10.0
00
SWITCHING TIMES VI
TEMPERATURE
--
200
-
180
+10
RON VI TEMPERATURE
..-
~~V
250
150
+5
ANALOG INPUT VOLTAGE - VA(VOL TS)
130
300
200
-5
-10
350
220
1
65
100
SWITCHING TIME VI
ANALOG VOLTAGE
TON
= -15V
TA = 25"C _
IS = 1rnA
70
5.0
ANALOG INPUT VOLTAGE (VOLTS)
~
80
~
Fl
-50
-100
20
g
SW-Ot/02
./
.......
240
V
~
-
85
/
50
ANALOG INPUT VOLTAGE - VA (VOLTS)
- ---
260
=.l
-150
-10
-40 -30
280
V+ = V-
/"
V
...--V
120
110
1--
,./
,./v"OFF
g
100
z 90
a:
,.........
0
80
"
RON = 85n @25°C
70
100
60
TOFF
160
-10
-5
10
50
-75
40
-50
-25
0
+25
+50
+75 +100 +125
-55 -35 -15
TEMPERATURE (QC)
ANALOG INPUT VOL lAGE - VA (VOLTS)
CROSSTALK AND "OFF"
ISOLATION VI FREQUENCY
100
5
25
45
65
TEMPERATURE fOC)
85
105 125
SWITCH CAPACITANCE VI
ANALOG VOLTAGE
LEAKAGE CURRENT VI
TEMPERATURE
16
10,000
Cs (ON)
14
90
12
80
i"-...
10 (ON)
1'-,
70
60
"'"f'..
I
40
tOOk
CROSSTALK ' -
"N
1M
10
1,000
I
Nil
FREQUENCY (Hz)
(ON)
ISI~lh
I
Cs (OFF)
10 (OFF)
e- -
,/11'"
OFF1ISJAJION
50
+ IS
II
10M
100
-60
V
L rL /
./
~ 1/
-20
20
60
TEMPERATURE 1°C)
13-12
100
140
-10
-
riD (iFF)
-6
V
,.......
/
V
l-
-2
'0
ANALOG INPUT VOLTAGE -VA (VOLTS)
1/86, Rev. A
----------~!EHD SW-01/SW-02 QUAD SPST JFET ANALOG SWITCHES
The SW-01/02 designs have been optimized for low "ON"
resistance variation with temperature, signal voltage, and
supply voltage changes. Fast switching response and low
leakage currents at high temperature are also key performance improvements over older circuit designs.
and analog current near ideal signal transfer accuracy is
obtainable.
Applications needing very high analog current capability
(>SmA) or where the switch is driven from high source
impedances (>100.0.) should use the SW-201 (Pin Compatible
to SW-01) or the SW-202 (Pin Compatible to SW-02) highcurrent quad switches.
The static-electricity-resistant JFET switches and additional
overvoltage-protection circuitry make the precision switches
extremely durable in most application environments.
Although the SW-201/202 do not offer the same "ON"
resistance temperature coefficient, many other premium
characteristics are similar. In addition, the SW-201/202 offer
exceptionally low signal distortion over a wide signal voltage
and~equency range.
The SW-01/02 are well suited to applications requiring
analog currents --i---,--t---
"(;g
45
I--
ANALOG VOLTAGE (VOLTS)
V+ '" 16V
V-" -16V
"...
~
25
ilw-40
~',
-0.6
V+
a:
\\
\
---
'.
'-
~
I
IS(OFF)
-0.4
/
20
1
I~\,I
25"C
5
LEAKAGE CURRENT AT 125°C
VB ANALOG VOLTAGE
IO(OFF)
-0.2
SLOPE" 1/ RON
....... I---'"
TEMPERATURE
0.2
LOGIC INPUT CURRENT
VI VOLTAGE
15a:
-55 -35 -15
LEAKAGE CURRENT
V SD VOLTAGE ACROSS SWITCH (VOLTS)
!...
o
VI ANALOG VOLTAGE
V
-20
-2
I---'" V
ANALOG VOLTAGE (VOLTS)
L
/
II
V
20
±SUPPLY VOLTAGE (VOLTS)
SWITCH CURRENT
vsVOLTAGE
40
0
20
°0~--~--~--~--1~2-~1.~~,8
..... ......
SO
;
TA=2SOC
0
ii
VB
II
;;,:
,g
...
~
6
a:
::>
-200
-300
"~ 4
)
-100
a:
./
1+
il
./
r-
-400
-16
-10
-5
10
lOGIC INPurVOLTAGE (VOLTS)
0
"
-
..
-3'
-1.
.-
•
2.
45
TEMPERATURE
13-18
6.
fe)
8. 10.
12.
.+
.°0~--~--~--~---'~2---+'15~~'8
±SUPPLY VOLTAGE (VOL TSj
1/86, Rev. A
--------------1~ SW·OS DUAL SPST JFET ANALOG SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS
SWITCHING RESPONSE
VB
SWITCHING TIME
TEMPERATURE
SWITCHING TIME
ANALOG VOLTAGE
VB
600
600
V+ = 15V
V+"' 15V
v-
V-" -15V
TA=2IfC
RL" lkn
500
60 0
CL.·30pF
VA --5V
.
w
I200
~
IA
r- V
t!l 300
z
1i!:
t'OFF
-I'
(SEE SWITCHING TIME TEST CIRCUIT)
r- I- r-
t'OFF MEASURED TO 90%
OF Vo (SEE TEST CKT)
~11 -9 -7
tON
5 -3 -1
~ 30 0
i
........
100
INSERTION LOSS
VB FREQUENCY
....- --::::
0
~~
>=
= -15V
VA = -5V
RL = lk.l1
CL = 30pF
1
--
-
tOFF
3
5
r=
~ 200
-
......
7
:;...-:::::: :::::::
~
.:;::; ~ r-
tOFF
100
9
11
0
-55 -35 -15
5
25
45
65
85
ANALOG VOLTAGE (VOLTS)
TEMPERATURE (oC)
OFF ISOLATION AND
CROSSTALK VB FREQUENCY
DISTORTION VB
FREQUENCY
105 125
100
~ .....
a;
"::l
80
i
-2
-4
.......
UllWL
.......
~~
u 60
o
~
mrSOLATION
1l
-6
z
-8
RL = lkf2
v+ 15V
v- = -15V
=
~
tt
20
o
,
~A,', ~~~~
'Ok
40
5
VA=lVRMS
-'0
2
'M
TOOk
FREQUENCY
'OM
RL' 680nlill
VIN = lVRMS
V+ = 15V
v- = -1SV
TA=25°C
o
100M
TOOk
'Ok
(Hz)
POWER SUPPLY REJECTION
VB FREQUENCY
'00
90
"
I'-
80
70
'\
60
30
V+ = 15V
IIII I
28
~~SRR
24
I\.
..s-
20
16
RL = lkn
VIN = lVRMS
SWITCH CLOSED
12
LOG!~~
-PSRA '" 20
LOG:~~
o
'00
lk
10k
FREQUENCY (Hz)
I- v-· -,5V
=
TA 2SOC
f lMHz
=
v+ = 15V
v- = -15V
+PSRR = 20
20
----
CS(ON)
CS{OFF)
-
TOOk
OVERVOLTAGE
CHARACTERISTIC
32
llU
TA = 25°C
40
'0
CAPACITANCE VB
ANALOG VOLTAGE
-PSRR
50
10M
1M
FREQUENCY (Hz)
'M
o-11
-
:,.....V
>-f- ~OIOFFI
-9 -7 -5 -3 -1
1
3
5
7
ANALOG VOLTAGE (VOLTS)
13·19
9
11
-10
0
10
20
30
40
ANALOG VOL TAGE (VOLTS)
1/86, Rev. A
-------------Im
SW·05 DUAL SPST JFET ANALOG SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS (Single Supply Operation)
"ON" RESISTANCE
SWITCHING TIME vs
ANALOG VOLTAGE
vs SUPPLY VOLTAGE
'00
,-'--r--r-....,-....,-....,---,
v- ""
80
g
w
"z
500
RL = 4.7kn
~L='3PF
v+ = 2av
400
w
">=
~ 300
;:
::
40
~ 200
z
v- '" ov
ov
)
GND '"
.5.
60
~
~
0.4
600
OV
GND = OV
TA = 25°C
IS = lmA +-+-+_+_+~
'oN
\
\
'DO
12
16
20
24
00
28
V+ SUPPLY VOLTAGE (VOLTS)
8
12
16
20
24
~ i;:".'S(OFF)
-'"
-
t'OFF
20
0
IOIOFFI
V
lolON)
0
0
LEAKAGE CURRENT
vs ANALOG VOLTAGE
V+" 2av
v-
-0.4
-0.6 0
28
=OV
GND =
ov
TA'" 25°C
FOR IO(OFF). Vs = lOV
FOR IS(OFF). Vo = lOV
8
12
16
20
24
28
ANALOG VOL rAGE (VOL 15)
ANALOG VOLTAGE (VOLTS)
TEST CIRCUITS
OFF ISOLATION TEST CIRCUIT
CROSSTALK TEST CIRCUIT
VA = 5VRMS
AT f = 500kHz
NCo-~S'+-o~A-~rD~'~~~___V~D'
D
A--~--~--1r---oVOUT
50n
RL
"OFF" ISOLATION = 20 LOG
.
[~]
Your
50n
CROSSTALK = 20 LOG
['!.A.]
VOl
SWITCHING TIME TEST CIRCUIT
LOGIC
+15V
Vo = Vs Rl +
SWITCH
INPUT
INPUT
~ (ON)
SWITCH
OUTPUT
S,
~=~VO-+-----ai A-~-o-,--~>-oVo
tr
<
20n5
tf
<
20n5
SWITCH "ON" FOR LOGIC 0 , -_ __
3.0V
50%
50%
SWITCH
INPUT
RL
'kn
SWITCH
OUTPUT
SWITCH OUTPUT WAVEFORM SHOWN FOR Vs '" CONSTANT
WITH LOGIC INPUT WAVEFORM AS SHOWN.
Va IS THE STEADY STATE OUTPUT WITH SWITCH ON.
REPEAT TEST FOR IN2
13-20
1/86, Rev. A
_ _ _ _ _ _ _ _ _ _ _ _-;~ SW-05 DUAL SPST JFET ANALOG SWITCH
APPLICATIONS INFORMATION
The SW-05 provides a rugged J FET alternative to the industry
standard CMOS generic DG200 device. The basic differences in process (CMOS vs Bipolar-JFET) effecting switch
characteristics result from the parallel connected enhancement mode FETs used in CMOS versus the single depletion
mode JFET used by the Bipolar-JFET process. The junction
technology is far less susceptible to electrostatic damage
(ESD), and offers a higher resistance to radiation exposure.
No extensive threshold shifts take place as commonly found
in CMOS.
CMOS logic. Since the SW-05 incorporates a standard two
forward diode drop logic voltage reference, pin 7 in the metal
can and pin 12 in the DIP package were left unconnected.
This allows direct plug-in compatibility with DG200's requirmg external logic threshold adjustment to their VREF pin
when operating from supplies other than ± 15 volts. No logic
threshold adjustment is necessary with the SW-05 operating,
for example, at ± 12 volts.
The addition of a 7474 latch in front of the SW-05 (Figure 1)
results in a pulse input latching SPDT analog switch. A
positive edge of an input pulse to the TTL D type flip flop
causes the Q andQ outputs to change state. Taking advantage of the complementary outputs turns the SW-05 into a
break-before-make SPDT analog switch. The short dead time
between switch closures prevents damaging current flowing
between the two ~ow impedance sources. The photograph
illustrates the dead time when VOUT IS pulled to ground by the
1k ohm termination resistor.
The basic JFET switch design inherently results in a more
linear "ON" resistance overthe designed analog signal range
of -15 to +11 volts. The "ON" resistance is independent of
analog voltage and supply voltage, but does have a positive
temperature coefficient of O.4%/ o C. Leakage currents stay in
the low picoamps at room temperature providing very high
"OFF" ~esistance characteristics.
The logic control inputs are TTL input compatible with full
400mV noise immunity over the full operating temperature
range. The PNP input structure requires very little logic drive
current resulting in minimum output loading to both TTL and
The initialize input, connected to the D flip flop reset (clear)
input, resets Q, sending an active low to the IN, terminal of
the SW-05 closmg switch 1.
FIGURE 1: Pulse Input Latching SPOT Analog Switch
+1SV
"'V
PULSE
'4
INPUT
n
I.
V+
CHANNEL 1
Vee
,.---=.;S'¥4'--_ _ _OO+5V
SOURCE 1
f '-----4----'t.:!!!.,
01 5
3 elK1
0' 5
D FLIP FLOP
INITIALIZE 1
1/27474
1---.-oOVOUT
SW.o5
CHANNEL 2
''''
ll'lf6-......- - 4 - -.......~,
2 01
GNO
'---=1"-----0 +2V
II
SOURCE 2
PIN OUT FOR
METAL CAN PACKAGE
SHOWN
-15V
13-21
1/86, Rev. A
SW-06
QUAD SPST JFET
ANALOG SWITCH
Precision MOIlOlithics Inc.
FEATURES
GENERAL DESCRIPTION
• Two Normally Open and Two Normally Closed SPST
Switches with Disable
• Switches can be Easily Configured as a Dual SPDT or
a DPDT
• Highly Resistant to Static Discharge Destruction
• Higher Resistance to Radiation Than Analog Switches
Designed with MOS Devices
• Guaranteed RON Matching ...•....••...•...•. 10% Max
• Guaranteed Switching Speeds ....••. TON = 500ns Max
TOFF = 400ns Max
• Guaranteed Break-Before-Make Switching
• Low "ON" Resistance ...•.......•.......•.•.. 80n Max
• Low RON Variation from Analog Input Voltage ....... 5%
• Low Total Harmonic Distortion .....•......•...•. 0.01%
• Low Leakage Currents at High Temperature:
TA = 125° C ................. 100nA Max
TA = 85°C ................... 30nA Max
• Digital Inputs TT"l/CMOS Compatible and Independent
ofV+
• Improved Specifications and Pin Compatible to LF-11333/
13333
• Dual or Single Power Supply Operation
The SW-06 is a four channel single-pole, single-throw analog
switch that employs both bipolar and ion-implanted FET
devices. The SW-06 FET switches use bipolar digital logic
inputs which are more resistant to static electricity than
CMOS devices. Ruggedness and reliability are inherent in
the SW-06 design and construction technology.
Increased reliability is complemented by excellent electrical
specifications. Potential error sources are reduced by minimizing "ON" resistance and controlling leakage currents at
high temperatures. The switching FET exhibits minimal RON
variation over a 20V analog signal range and with power
supply voltage changes. Operation from a single positive
power supply voltage is possible. With V+ = 36V, V- = OV, the
analog signal range will extend from ground to +32V.
PNP logic inputs are TTL and CMOS compatible to allow the
SW-06 to upgrade existing designs. The logic "0" and logic
"1" input currents are at micro-ampere levels reducing loading on CMOS and TTL logic.
FUNCTIONAL DIAGRAM
V'
PIN CONNECTIONS
SWitches are shown
12
3
the logic "0"
mput state and DIS = "1"
In
IN 1
~Sl
O-'----jr-,
t.2...o01
TOP VIEW
LEVEL
SHIFT
IN 2
6
_~S2
0--4---<..-....
t.2....a
16-PIN DUAL-IN-LINE
PACKAGE
(Q OR P Package)
SW-06BRC/883
LCCPACKAGE
(RC-Sufflx)
IN 3
O-:'---i-ar--....
IN 4
0-:.;"'-1-<11..-....
-[~
t
15
ORDERING INFORMATIONt
PACKAGE IS
16-PIN DIP
HERMETIC
EPOXY
ORDER
PART
NUMBER
SW06BO'
SW06FO
SW06GO
SW06GP
DIS
LCC
SW06BRC/BB3
OPERATING
TEMPERATURE
RANGE
13
GND
02
S4
D4
V-
TRUTH TABLE
MIL
INO
COM
COM
SWITCH STATE
'For devices processed In total compliance to MIL-STD-BB3, add IBB3 after
part number Consult factory for BB3 data sheet
t All commercial and Industrial temperature range parts are available with
burn-In For ordering information see 19B6 Data Book, Section 2
13-22
DISABLE
INPUT
LOGIC
INPUT
CHANNELS
1&2
CHANNELS
3&4
0
10rNC
10rNC
X
0
1
OFF
OFF
ON
OFF
ON
OFF
1/86, Rev. A
---------------1~ SW-06 QUAD SPST JFET ANALOG SWITCH
ABSOLUTE MAXIMUM RATINGS (Note 1)
Operating Temperature Range
SW-06BQ, BRC ...................... -55°C to +125°C
SW-06FQ ............................ -25°C to +85°C
SW-06GP .............................. O°C to +70°C
Storage Temperature Range ........... -65°C to +150°C
Power Dissipation (Note 2)
Q Package ................................... 900mW
P Pac kage ................................... 500mW
Lead Temperature (Soldering 60 sec) ............. 300° C
Maximum Junction Temperature .................. 150°C
ELECTRICAL CHARACTERISTICS at V+
V+ Supply to V- Supply ............................ 36V
V+ Supply to Ground .............................. 36V
Logic Input Voltage ............ (-4V or V-I to V+ Supply
Analog Input Voltage Range
Continuous ............. V- Supply to V+ Supply +20V
Maximum Current Through
Any Pin Including Switch ....................... 30mA
NOTES:
Absolute ratings apply to both DICE and packaged parts. unless otherwise
noted.
2.
a Package derated 12mW/' C above 75' C, P Package derated 10mW/' C
above 25'C.
= 15V, V- = -15V and T A = 25° C,
unless otherwise noted.
SW-OS8
PARAMETER
SYMBOL
"ON" Resistance
RON Match Between
SWitches
RON Match
MAX
Vs = OV, Is= lmA
60
Vs = ±10V, Is = 1mA
65
IS = lmA (Note 8)
Is= lmA
Analog Current Range
VS =±10V
Applied
Source Current In
"OFF" Condltton
"OFF" Condition
Source Current
In
"ON" Condition
IO(OFF)
(Note 5)
Logical "1" Input
Full Temperature Range
Voltage
(Notes 6, 8)
Voltage
VIN
V1N
Logical "0" Input
Time
65
100
100
150
20
20
+10
+11
-10
-15
10
15
12
See SWitching Time
Test Circuit (Notes 6,9)
(Note 9)
mA
20
10
20
%
03
20
03
20
03
10
nA
03
20
03
20
03
10
nA
03
20
03
20
03
10
nA
20
v
20
08
08
v
10
0 8V
tON-tOFF
%
10
08
Test Circuit (Notes 6, 9)
tOFF
n
v
10
= 2 OV to 15 OV
=
UNITS
15
20
See SWitching Time
Turn-On-Time
8reak-8efore-Make
80
(Note 4)
Current
Turn-Oft-Time
150
-15
(Notes 6, 8)
Logical "1" Input
100
+11
Full Temperature Range
Logical "0" Input
100
-10
= Vo = ±lQV
Vs
MAX
60
+10
(Note 5)
IS{ON)+
TYP
80
-15
(Note 5)
IO(ON)
MIN
+11
Vs = 10V, Vo = -10V
Drain Current In
MAX
-10
Vs = 10V, Vo = -10V
IS(OFF)
SW-OSG
TYP
+10
-lOV:S Vs 'S::. lOV, Is = 1 OmA
Voltage
MIN
10
Vs = OV, Is = 100"A (Note 1)
Analog Voltage Range
~RON vs
MIN
SW-OSF
TYP
CONDITIONS
50
15
50
15
50
15
100
340
500
340
600
340
700
ns
200
400
200
400
200
500
ns
140
50
140
50
140
ns
Source Capacitance
CSIO FF)
Vs = OV (Note 5)
70
70
70
pF
Drain Capacitance
CD (OFF)
Vs = OV (Note 5)
55
55
55
pF
Channel "ON"
CD(ON)+
Vs = Vo = OV (Note 5)
15
15
15
pF
Vs = 5V RMS, RL = 6aOn,
C L = 7pF, f = 500kHz (Note 5)
58
58
58
dB
70
70
70
dB
Capacitance
"OFF" Isolation
CS{ON)
ISO (OFF)
Vs = 5V RMS, RL = 680n,
Crosstalk
PoSItive Supply
Current
Negative Supply
Current
Ground Current
C L = 7pF, f = 500kHz (Note 5)
1+
All Channels "OFF",
DIS = I l f ) (Note 5)
50
60
50
90
60
90
mA
1-
All Channels "OFF",
DIS = «0)) (Note 5)
30
50
40
70
40
70
mA
30
40
30
40
30
50
mA
All Channels "ON" or
"OFF" (Note 5)
13-23
1/86, Rev. A
-------------I~ SW-06 QUAD SPST JFET ANALOG SWITCH
ELECTRICAL CHARACTERISTICS at V+= 15V, V-=-15V, -55°C:O; TA:O;+125°C forSW-06BQ, -25°C:o; TA:O; +85°C for
SW-OSFQ and 0° C :0; TA
:0;
70° C for SW-OSGP, unless otherwise noted.
SW-06F
SW-068
PARAMETER
SYMBOL
CONDITIONS
Temperature Range
TA
Operatrng
~
Vs
"ON" Resistance
RON
RON Match Between
OV, IS ~ 10mA
Vs = ±10V, IS
~
OV, IS ~
= 10mA
100~A
Vs
Analog Voltage Range
VA
Is ~ 1 OmA (Note 8)
Is~ 1 OmA
Analog Current Range
IA
aA ON With Applied
Is~
Source Current In
IS(OFF)
"OFF" Condition
+10
-10
1 OmA
10V, Vo
~
~
MIN
125
-25
TYP
SW-06G
MAX
MIN
TYP
85
MAX
UNITS
70
'C
110
75
125
75
175
80
110
80
125
80
175
25
10
%
+11
-15
V
20
-10V:::;Vs .5+10V,
Vs
MAX
75
(Note 1)
Vs~±100V
.:1RON
Voltage
TYP
-55
RON Match
SWitches
MIN
+11
-15
+10
-10
+11
-15
+10
-10
n
12
11
11
mA
10
12
15
%
-10V,
60
30
60
nA
60
30
60
nA
100
30
60
nA
V,N ~ 2 OV to 15.0V
(Note 4)
10
10
15
~A
V,N
10
10
15
~A
TA = Max Operating Temp
(Notes 5, 7)
Vs
Drain Current In
10(OFF)
"OFF" Condition
10V, Vo
~
~
-lOV,
TA = Max Operating Temp
(Notes 5, 7)
Vs
Leakage Current In
IS(ON)+
"ON" Condition
ID(ON)
Logical "1" Input
IrNH
Current
Logical "0" Input
'INL
Current
~
Vo
~
±10V,
TA = Max Operating Temp
(Notes 5, 7)
~
0 8V
See SWitching Time
Turn-On-Time
tON
Turn-Off-Time
tOFF
Test CirCUit (Notes 2,6)
See SWltchrng Time
Break-Before-Make
tON-tOFF
TIme
Test CircUIt (Notes 2, 6)
(Note 3)
440
900
500
900
1000
ns
300
500
330
500
500
ns
70
70
50
ns
PositIve Supply Current
1+
All Channels "OFF" (Note 5)
90
13.5
135
mA
Negative Supply Current
1-
All Channels "OFF" (Note 5)
75
10.5
105
mA
6.0
75
75
mA
Ground Current
All Channels "ON" or "OFF"
IG
(Note 5)
NOTES:
1. Vs = OV, Is = 100",A Specified as a percentage of RAVERAGE where
A
2.
3.
- RONl + RON2 + RON3 + RON4
AVERAGE -
4
Guaranteed by design.
SWitch IS guaranteed to provide break-before-make operation
Current tested at V = 2.0V. ThiS IS worst case condition
SWitch being tested ON or OFF as indicated, V ,NH ~ 2 av or V ,NL ~ a.BV,
per logic truth table
Also applies to disable Pin.
Parameter tested only at TA = +125°C for military grade device.
Guaranteed by RON and leakage tests For normal operation maximum
analog Signal voltages should be restricted to less than (V+) -4V.
Sample tested
,N
5.
6.
7.
B.
9
13-24
1/86, Rev. A
_ _ _ _ _ _ _ _ _ _ _ _-j~ SW-06 QUAD SPST JFET ANALOG SWITCH
DICE CHARACTERISTICS
1. IN (1)
2. 0 (1)
3. S (1)
4. GND
5. V- (SUBSTRATE)
6. S (2)
7.0(2)
8. IN (2)
9. IN (3)
10. 0 (3)
11. S (3)
12. V+
13. DISABLE
14. S (4)
15. 0 (4)
16. IN (4)
DIE SIZE 0.100 X 0.096 inch, 9600 sq. mils
(2.540 X 2.438 mm, 6.193 sq. mm)
WAFER TEST LIMITS at V+
For additional DICE information refer to
1986 Data Book, Section 2.
=15V, V- = -15V, TA =25°C, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
"ON" Resistance
RON
-IOV"VA " 10V, Is" ImA
SW-06N
SW-06G
LIMIT
LIMIT
UNITS
80
100
nMAX
%MAX
VA = OV, Is" 100~A
IS
20
aRONvsvA
aR oN
-IOV" VA" 10V, Is" ImA
10
20
% MAX
Positive Supply Current
1+
(Note I)
60
9.0
mAMAX
Negative Supply Current
1-
(Note I)
50
70
mAMAX
Ground Current
IG
(Note I)
40
4.0
mAMAX
Analog Voltage Range
VA
Is=lmA
±IOO
±IO.O
VMIN
LogiC "1" Input Voltage
V 1NH
(Note 3)
20
2.0
VMIN
Log'c "0" Input Voltage
V 1Nl
(Note 3)
08
0.8
V MAX
LogiC "0" Input Current
IINL
OV" V'N" 0 8V
50
50
~AMAX
Logic "1" Input CUrrent
IINH
2 OV" V'N" 15V (Note 2)
Analog Current Range
IA
Vs= ±IOV
RON Match Between Switches RON Match
~AMAX
10
mAMIN
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to vanatlons In assembly methods and normal Yield loss, Yield after packaging is not
guaranteed for standard product dice. Consult factory to negotl8te specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS at V+ = 15V, V- = -15V and
TA
= 25° C, unless otherwise noted.
SW-OSN
SW-06G
TYPICAL
TYPICAL
60
60
!l
tON
340
340
ns
tOFF
200
200
ns
0.3
nA
PARAMETER
SYMBOL
CONDITIONS
"ON" ReSistance
RON
-IOV" VA" 10V, Is" ImA
Turn-On-Time
Turn-Off-Time
Dram Current In
UNITS
ID(OFF)
Vs = 10V, V D = -IOV
03
"OFF" Isolation
ISO(OFF)
f = 500kHz, RL = 680n
58
58
dB
Crosstalk
CT
f = 500kHz, RL = 680n
70
70
dB
"OFF" Condition
NOTES:
1 Power supply and ground current specified for sWitch "ON" or "OFF"
2 Current tested at VIN = 2 OV This IS worst case condition
Guaranteed by RON and leakage tests
13-25
1/86, Rev. A
--------------1~ SW-06 QUAD SPST JFET ANALOG SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS
"ON" RESISTANCE VI
POWER SUPPLY VOLTAGE
120
"ON" RESISTANCE vs
ANALOG VOLTAGE
! 25'e +---+--+--+--+---l
110
TA
100
~~==_~~~
+-+-+--+--+---1
90
z 60
ti
50
40
v+ ~ 15V
v- = -15V
70
IS= lmA
80
§
75
V+ '" +lSV
v- '" -15V
70 rTA'25'C - - - r - - - + - - - j
65~-_~
70 r-~~-+---+--~--~RON --
RON vs TEMPERATURE
75r-----~-----r----_r-----,
_ _~~_ _+-_ _- ;
I--
~ 60f=::~=t~~-lr-~--~~:::j
65
~ 55 ~--~--~~--+-----;
g 60
is
0: 55
50~--~--~~--+----;
50
45~--~--~---+----;
45
30
20
Z
... V
/~
~
V
V
±13
±14
±15
±16
±17
±18
±19
-10
___
_ _-"
~
__
~
40L-_ _
±12
~
10
-5
40
-55
10
0
-25
ANALOG INPUT VOLTAGE-VA (VOL TS)
POWER SUPPLY VOL rAGE (VOL TSI
LEAKAGE CURRENT
vs ANALOG VOLTAGE
SWITCH CURRENT
vs VOLTAGE
20
25
50
75
100
125
TEMPERATURE (OC)
LEAKAGE CURRENT
vs TEMPERATURE
-100
lOOnA
c_SUPPLY"=±15V
TA
<1
.§
>-
r--
10
V+ = 15VJ
V-=-lSV
TA=2SoC
--
V
iii
~
1/
~
"
~
/
~
~
>-
0
.......-
1
/
8:;' :r-25'~t-
IL
~
~
"w
""
"~
~~~~~~~~;~~~~~-rJDE
/
I'
t----LESS THAN 10 PI CO AMPS
-20
-2
TA =
TA
,
_Vl
!Z=
Y
II
-10
125::2
-00 1
-15
-1
V SD VOLTAGE ACROSS SWITCH
.X
-10
10pA
10
-5
-55
15
-25
SUPPLY CURRENT vs
TEMPERATURE
SUPPLY CURRENT vs
SUPPLY VOLTAGE
10
0
50
25
75
100
125
TEMPERATURE (OC)
ANALOG VOLTAGE {VOLTS}
(VOLTS)
SWITCH CAPACITANCE
vs ANALOG VOLTAGE
2
10
V+ '" 15V
TA
v- '" -15V
J25"C
v+
2.
DIS= '0'
olS= '0'
t-
f=lMHz
= 15V
V-=-15V
TA" 25°C
24
~
r- t- +-
1+
r- t--
1
~
f--+--
-55 -35 -15
20
w
1+
t-,...
~
J""..
25
45
65
TEMPERATURE (OC)
85
...
105
--
,...-
l-:'""
.-
±SUPPLY VOLTAGE (VOLTS)
13-26
16
~
12
~
s
I"- r- ~
C (ON)
s
C (OFF)
•
~
~
7
9
Co (OFF)
12
125
"~
15
,.
i i
-11 -9 -7 -5
-3 -1
1
3
5
11
ANALOG VOLTAGE (VOLTS)
1/86, Rev. A
-------------IrfHD
SW-06 QUAD SPST JFET ANALOG SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS
TON/ToFF
SWITCHING RESPONSE
V5
SWITCHING TIME
vs TEMPERATURE
SWITCHING TIME
ANALOG VOLTAGE
400
350
600
Vs
Vs = ±15V
RL = lkS2
CL = 10pF
TA=2S0C -
'-...
-0.5
300
300
-2
VO(V)
-4
tI..
250
-6
200
'50
-'0
'" --
Jy
400
I'-- ~
VO(V)
=±lSV
Rl = lkn
CL = 10pF
200
'00
TOFF
V
........V
........
--
o
-5
-55
-25
25
-2
..
80
"~
70
iij:
60
:)
75
100
125
TOTAL HARMONIC
DISTORTION
'0
'00
~
50
TEMPERATURE (OC)
CROSSTALK AND "OFF"
ISOLATION V5 FREQUENCY
"
~
g
~
...-V
~
ANALOG INPUT VOLTAGE (VOLTS)
INSERTION LOSS
V5 FREQUENCY
TL
~
~
TA = 25°C
II
v+
~ V+
= 15V
f--
+15V
l5V
VA = lV rms
TA = 25°C
%~4
'0
(;t-
0
~4~1
10,\<
18
V
:==
V-=-lSV
I~~ -lOon
r--
""-
0'
iil
~SO
........
o
40
'Ok
lOOk
'M
'M
lOOk
100M
'OM
AL = lkD.
r-....
UII
00'
'OM
lk
'00
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
POWER SUPPLY REJECTION
V5 FREQUENCY
OVERVOLTAGE
CHARACTERISTICS
90~~-r~mr-rnT~-rnT"~""~~~
~H"Idl:ttIt--t-H-t1
+PSRR = 20 log
~~~
701--f-+H-fl'IfI':--"rt..H-H
-PSRR '" 20 log
~~~
80
\
1111111
6°I--f-+Hfflrr-~+*mk-rHt~-+++~
I" +~~~~
Hr-H-I-ftlI+---I-t1-fl1lIt--H'>litltJ--l+t-I-ftlII
50
TA'" 25°C
40
V+=15V
30
V-= -lSV
i'-PSRR
20
_,~
'k
'Ok
lOOk
'M
-20
'OM
__
~
-10
__
~
__- L__
'0
~
__
20
~
__
30
~
40
ANALOG VOLTAGE-VA (VOLTS)
FREQUENCY (Hz)
13-27
1/86, Rev. A
-------------I~ SW-06 QUAD SPST JFET ANALOG SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS (OPERATING SINGLE SUPPLY)
"ON" RESISTANCE
LEAKAGE CURRENT
VI ANALOG VOLTAGE
vs VANALOG
SUPPLY CURRENT
vs SUPPLY VOLTAGE
10
01
rr-
1>-
1201--l-+-+-+---l-+--I
~
l00t-~--r-1--r-~--r-~
13
t!
;;2
60~~---+--~--t-~---+--I
~
401--+-+-+--+-+-+---1
__
~
__
~
__
12
~~
16
__
~
m
__
-02
-03
FO~ IS(OFF), V D"'12V
~
1+
-
-OS
J
-OS
V+ 28V
V-=OV
-07
TA=25°C
-08
I
12
ANALOG VOLTAGE (VOLTS)
TA=25°C
--
'OION}.../
-04
~
M
V
r- FOR ID(OFF), VS= 12V
16
20
ANALOG VOLTAGE (VOL TSj
24
t-----
GND '" 0
'-
GND~V
20~-l--+--+--+---l--+--1
o
IS~
I
-01
140 1--l--+--+--+-----,--+--1
oL-~
Jo
JO(OFF)
28
12
I--
1-
16
20
24
28
SUPPLY VOL rAGE (VOLTS)
SWITCHING TIME
vs SUPPLY VOLTAGE
1000
NOTE: These single-supply-operation characteristic curves
are valid when the negative power supply V- is tied to
the logic ground reference pin "GND". TTL input
compatibility is still maintained when "GND" is the
same potential as the TTL ground. t'OFF is measured
from 50% of logic input waveform to 0.9 Vo. The
analog voltage range extends from 0 to V+ -4V, the
switch will no longer respond to logic control when
VA is within 4 volts of V+.
900
800
1
r-
RL = 4 7K
C L '" 13pF
V+ '" 2aV
-
V- =OV
:-GND'" OV
TA = 25°C ' - -
700
w
:IE 600
~
~
500
~
~ 400
~
300
I -i--
200 1\
tON
.....
tOFF
100
12
16
20
24
28
ANALOG VOLTAGE (VOLTS)
SIMPLIFIED SCHEMATIC DIAGRAM (TYPICAL SWITCH)
DIGITAL
INPUT
IN x
13-28
1/86, Rev. A
-------------t~ SW-06 QUAD SPST JFET ANALOG SWITCH
OFF ISOLATION TEST CIRCUIT
CROSSTALK TEST CIRCUIT
VA'" 5VRMS
AT f '" 500kHz
VA = 5VRM S
AT f '" 500kHz
NC
D
81
VOl
01
Vour
CL
50n
RL
RL
52
"OFF" ISOLATION
=
20 LOG
[~J
Vaur
D2
NC
son
CROSSTALK = 20 LOG
SWITCHING TIME TEST CIRCUIT
+1SV
LOGIC
INPUT
+15V
SWITCH
INPUT
Vs=-sv
tr
tf
SWITCH
30V
< 20nS
< 20nS
OUTPUT
5,
O-+------if: ....-i--c.....-----1r----
IN 1,IN4
t
L
04
1
01
S2'S3
r
S4
~
I~ _ _~-
I~ _ _
L
;
[>-- -
OIN2,IN3
-
03
1
02
D4
DUAL DPST
o IN ',IN 2
IN3,IN4
01-IN_,:...,'N_2_ _
t
r' r'
[> _ _
t1S1'~
S2
_
01
03
~_
'S3
0~IN3,'N4[> _ J~ _r~
1
04
r r
L L
[> __~ _ _
DPDT
02
fD3
APPLICATIONS INFORMATION
t
switches, The PNP transistor inputs require such low input
current that the SW-06 approaches fan-ins of CMOS input
devices, These bipolar logic inputs exceed any CMOS input
circuit in resistance to static voltage and radiation susceptability, No damage will occur to the SW-06 if logic high voltages are present when the SW-06 power supplies are OFF,
When the V+ and V- supplies are OFF, the logic inputs
present a reverse bias diode loading to active logic inputs,
Input logic thresholds are independent of V+ and V-supplies
making single V+ supply operation possible by simply connecting GND and V- together to the logic ground supply.
This single analog switch product configures, by appropriate
pin connections, into four switch applications, As shown in
Figure 1, the SW-06 connects as a QUAD SPST, a DUAL
SPOT, a DUAL oPST, ora DPDTanalog switch, This versatility increases further when taking advantage of the disable
input (DIS) which turns all switches OFF when taken active
low,
lon-implantation of the JFETanalog switch achieves low ON
resistance and tight channel to channel matching, Combining the low ON resistance and low leakage currents results in
a worst case voltage error figure VERROR@ 125° C= IOION) X
RSOION)= 100nAX 1000= 11 microvolts, Thisamountof error
is negligible considering dissimilar-metal thermally-induced
offsets will be in the 5 to 15 microvolt range,
ANALOG VOLTAGE AND CURRENT
ANALOG VOLTAGE
These switches have constant ON resistance for analog voltages from the negative power supply (V-) to within 4 volts of
the positive power supply, This characteristic shown in the
plots results in good total harmonic distortion, especially
when compared to CMOS analog switches that have a 20 to
30 percent variation in ON resistance versus analog voltage,
Positive analog input voltages should be restricted to 4 volts
less than V+ assuring the switch remains open circuit in the
OFF state, No increase in switch ON resistance occurs when
operating at supply voltages less than ±15 volts (see plot),
Small signals have a 3dB down frequency of 70MHz (see
insertion loss versus frequency plot),
LOGIC INPUTS
The logic inputs (INx) and disable input (DIS) are referenced
to a TTL logic threshold value of two forward diode drops
(1.4V at 25°C) above the GND terminal. These inputs use
PNP transistors which draw maximum current at a logic "0"
level and drops to a leakage current of a reverse biased diode
as the logic input voltage raises above 1.4 volts, Any logic
input voltage greater than 2,0 volts becomes logic "1", less
than 0,8 volts becomes logic "0" resulting in full TTL noise
immunity not available from similar CMOS input analog
13-30
1/86, Rev. A
-------------l1fMD
SW-06 QUAD SPST JFET ANALOG SWITCH
ANALOG CURRENT
The analog switches in the ON state are JFETs biased in their
triode region and act as switches for analog current up to the
IA specification (see plot of los vs Vos). Some applications
require pulsed currents exceeding the IA spec. For example.
an integrator reset switch discharging a shunt capacitor will
produce a peak current of IA(PEAK) = VCAp/Ros)ONI' In this
application, it is best to connect the source to the most
positive end of the capacitor, thereby achieving the lowest
switch resistance and fastest reset times. The switch can
easily handle any amount of capacitor discharge current
subject only to the maximum heat dissipation of the package
and the maximum operating junction temperature from
which repetition rates can be established.
Switching transients occurring at the source and drain contacts results from AC coupling of the switching FETs gate-tosource and gate-to-drain coupling capacitance. The switch
turn ON will cause a negative going spike to occur and the
turn OFF will cause a positive spike to occur. These spikes
can be reduced by additional capacitance loading, lower
values of R L , or switching an additional switch (with its extra
contact floating) to the opposite state connected to the spike
sensitive node.
DISABLE NODE
This TTL compatible node is similar to the logic inputs IN x
but has an internal 2/JA current source pUll-Up. If disable is
left unconnected. it will assume the logic "1" state, then the
state of the switches is controlled only by the logiC inputs IN x.
SWITCHING
POWER SUPPLIES
Switching time tON and tOFF characteristics are plotted versus VANALOG and temperature. In all cases, tOFF is designed
faster than tON to insure a break-before-make interval for
SPOT and OPOT applications. The disable input (OIS) has
the same switching times (tON and tOFF) as the logic inputs
(INx)·
This product operates with power supply voltages ranging
from ± 12 to ±18 volts; however, the specifications only guarantee device parameters witl:1 ± 15 volt ±5% power supplies.
The power supply sensitive parameters have plots to indicate
effects of supply voltages other than ± 15 volts.
TYPICAL APPLICATIONS
4-CHANNEL SAMPLE HOLD AMPLIFIER
OPERATION FROM SINGLE POSITIVE POWER SUPPLY
-15V
V+ -<+36V
13
SW06
VI
V+
+15V
1/4 SW06
VOUT
V2
14
15
V3
11
10
V4
VOUT
1"
0
1000pF
DISABLE ALL
SWITCHES
13-31
1/86, Rev. A
-------------I~ SW-06 QUAD SPST JFET ANALOG SWITCH
HIGH OFF ISOLATION SELECTOR SWITCH (Shunt-Series SWitch)
+1SV
+15V
SW-06
2'
v+
2.
+15V
-15V
NC
-15V
CONTROL
INPUT
HI-CHANNEL 1 ON
LO-CHANNEL 2 ON
THIS SWITCH ARRANGEMENT IMPROVES OFF ISOLATION BY 30dS
SINGLE POLE DOUBLE THROW SELECTOR SWITCH WITH BREAK-BEFORE-MAKE INTERVAL
+15V
lOGIC IN
12
(VOLTS)
v+
~~______~11~____~~~~r7~,'_0__-1__--oVO
+4V
"
Vo
(VOLTS)
During the 88M interval the 1kfl resistor pulls the output to ground assuring
that no shorting between V, and V2 occurs,
13-32
1/86, Rev. A
SW-201/SW-202
QUAD SPST JFET
ANALOG SWITCHES
Precision MOllolithics Inc.
may be independently digitally controlled. Each SW-201
switch is normally closed (NC), whereas each SW-202 is
normally open (NO) when the corresponding digital control
input is a zero. The SW-201 and SW-202 are otherwise
identical.
FEATURES
SW-201
• Normally "ON" for Logic 0 Input
• Improved Performance and Pin Compatible With DG-201,
LF11201/13201, H1201, and IH201
SW-202
The judicious combination of bipolar and FET devices in a
single monolithic IC results in a product with performance
characteristics and ruggedness that are superior to those of a
similar circuit fabricated using CMOS technology.
• Normally "OFF" For Logic 0 Input
• Improved Performance and Pin Compatible With
LF11202/12202/13202 and IH202
Both SW-201 and SW-202
Increased reliability is complemented by excellent electrical
specifications. Potential error sources are reduced by minimizing "ON" resistance and controlling leakage currents at
high temperatures. The switching FET exhibits minimal RON
variation over a 20V analog signal range and with power
supply voltage changes. Operation from a single positive
power supply voltage is possible. With V+ = 36V, V-= OV, the
analog signal range will extend from ground to +32V.
•
•
•
•
•
•
•
Highly Resistant to Static Discharge Destruction
Guaranteed Break-Before-Make Switching (tOFF < tON)
Low "ON" Resistance ....................... 80n Max
Guaranteed RON Matching .................. 15% Max
Low RON Variation from Analog Input Voltage ..... 5%
High Analog Current Operation ............ 10mA Min
Low Leakage Currents at High Temperatures:
TA = 125°C .................. 60nA Max
TA = 85°C ................... 30nA Max
• Guaranteed Switching Speeds:
tON = 500ns Max tOFF = 400ns Max
• Digital Inputs are TTL and CMOS Compatible
• Dual or Single Supply Operation
The PNP logic inputs are TTL and CMOS compatible. Logic
input currents are at micro-ampere levels which improvescircuit
fan in.
PIN CONNECTIONS
16-PIN DUAL-IN-LINE PACKAGE
(0 or P Package)
ORDERING INFORMATIONt
DIP
PACKAGE
16-PIN HERMETIC
16-PIN HERMETIC
16-PIN EPOXY
SWITCH CONFIGURATION
NC
NO
SW201BO'
SW201FQ
SW201GP
SW202BO'
SW202FO
SW202GP
OPERATING
TEMPERATURE
RANGE
MIL
INO
COM
For devices processed In total compliance to MIL-STO-B83, add /883 after
part number Consult factory for 883 data sheet
tAil commercial and Industrial temperature range parts are available with
burn-In For ordenng Information see 1986 Data Book, Section 2
*
SW-201 CONTROL LOGIC
SWITCH
LOGIC
o
ON
GENERAL DESCRIPTION
The SW-201 and SW-202 each consist of four independent,
single-pole, single-throw (SPST) analog switches, which
SW-202 CONTROL LOGIC
LOGIC
SWITCH
o
OFF
OFF
ON
SIMPLIFIED SCHEMATIC DIAGRAM (ONE SWITCH)
010
~---...._---...._-+
__+ __+J""'"f1
ANAL.OG
,.
:IN(S)
OUT 101
DIGITAL
INPUT
Manufactured under the following patent' 4,228,367
13-33
1/86, Rev. A
-----------l~ SW·201/SW·202 QUAD SPST JFET ANALOG SWITCHES
ABSOLUTE MAXIMUM RATINGS
(Note 1)
V+ Supply to Ground •••••••••••.••••••••••••••••••
SW·201BQ, SW·202BQ ••••••••••••••
-55'C to +125'C
SW-201FQ, SW-202FQ •••••••••••••••
Continuous ••••.•••.•••
-25'C to +85'C
500llsec pulse ..... V- Supply -15V to V+ Supply +20V
Maximum Current Through Any Pin ••••••••••••••• 30mA
-65'C to +150'C
P-Suffix • • . • .. .. .. .. .. • • • • • .. .. .. ... -65' C to + 125' C
Power Dissipation (Note 2) ...................... 900mW
NOTES:
1. Absolute ratings apply to both DICE and packaged parts, unless otherwise
noted.
2. Derated 12mW/' C above 75' C.
Lead Temperature (Soldering, 60 sec) •••••••.•.••• 300'C
Maximum Junction Temperature ••••••••••••.••••• 150'C
V+ Supply to V- Supply............................ 36V
ELECTRICAL CHARACTERISTICS at
V±
= ±15V and
TA
=
25'C, unless otherwise noted.
SW-201B
SW-202B
PARAMETER
"ON" Resistance
RON Match Between
Switches
Analog Voltage Range
SYMBOL
CONDITIONS
RON
VA = OV, Is=1mA
VA = ±10V, Is = lmA
RON Match
VA = OV, 10= 100~A;
(Note 1)
VA
Is = 1.0mA (Note 6)
Is= 1.0mA
Analog Current Range
'A
Vs = ±10V
J:
90
"e-
80
RON-
60
1100
f_~)25O~
1000
r-vs= :!:.15V
900
~
700
ill
600
~
1I
~O
"'c;"
400
w
30
0
>
20
10
±15
:!:.16
:t17
:!:.18
POWER SUPPLY VOLTAGE (VOLTS)
±19
V+
I
II
28
I--
o ./
o 1
75
100
125
";0z
~
,/
~ 15~
f = 1MHz
V-=-15V
TA = 25°C
24
20
~
w
V
V
300
200
50
SWITCH CAPACITANCE vs
ANALOG VOLTAGE
32
I I I
I I I
/
25
-25
TEMPERATURE (OC)
I-- CURRENT INTO SOURCE
100
:!:.14
-55
~
40
:!:.13
10pA ' - -__l - - - '__--'-__-'---''---'-__-'
10M
800
50
±12
"
SWITCH CURRENT vs
VOLTAGE
120
70
1M
FREQUENCY (Hz)
"ON" RESISTANCE vs
POWER SUPPLY VOLTAGE
110
10
-5
ANALOG INPUT VOLTAGE (VOLTS)
~"'~~
50
-25
"" ---
....TOFF
0.\8
46
~
200
l00nAr---r-~---r--~--r--.--,
1&0
'/
40
-55
1\
150
25
-25
~~
TA '" 25"C
/'f'
z
0
250
100
65
z
V
CROSSTALK AND "OFF"
ISOLATION vs FREQUENCY
75
70
'-...
300
TEMPERATURE (OC)
RONvsTEMPERATURE
9
TOFF
o
-55
50
350
Vs = ±15V
Rl = lkn
CL '" lOpF
TA=2SoC -
I
./
ANALOG INPUT VOLTAGE-VA (VOLTS)
§
-
V
100
45~--1_--_t--_+--~
./
V V
400
~
TA - 2SCC
v+ '" +15V
SWITCHING TIME vs
ANALOG VOLTAGE
16
--
CS(ON)
12
Cs (OFF)
~
~
/'
/'
2
Co (OFF)
I I
3
4
5
6
7
8
SWITCH CURRENT (rnA)
13-37
9
10
11 12
-11 -9 -7 -5
-3
-1
1
3
5
7
9
11
ANALOG VOLTAGE (VOLTS)
1/86, Rev. A
_ _ _ _ _ _ _ _ _ _----t!lliDSW-201tSW-202 QUAD SPST JFET ANALOG SWITCHES
TYPICAL PERFORMANCE CHARACTERISTICS
SW-201
SW·202
tOWtOFF SWITCHING RESPONSE
tOWtOFF SWITCHING RESPONSE
-ov
-ov
TOP TRACE' LOGIC INPUT (5V!DIVJ
BOTTOM TRACE SWITCH OUTPUT (1V/DIV)
TOP TRACe LOGIC INPUT (5V!DIV)
BOTTOM TRACE' SWITCH OUTPUT (1V/DIV)
OFF ISOLATION TEST CIRCUIT
SW-201 WAVEFORMS
VA'"' 5V RMS
@f=500kHz
"-+--t--......--<>
VOUT
* 3.5V------_....
.on
LOGIC INPUT
50%
tr,tf<20ns
ov==========~~~=====q--~~~==
O.lVa
SW-201 OUTPUT
[~J
"OFF" ISOLATION = 20 LOG
~e============f===~~==~==~~---
VOUT
SWITCHING TIME TEST CIRCUIT
+15V
*SWITCH OUTPUT WAVEFORM SHOWN FOR Vs = CONSTANT WITH LOGIC INPUT
WAVEFORM AS SHOWN Vo IS THE STEADY STATE OUTPUT WITH SWITCH ON
R,
Vo=:Vs - - RL + ros(ON)
SWITCH
INPUT
5,
Vs =~5V
o--t------O"il
SWITCH
OUTPUT
0,
"--t-<)-~-__.-o Vo
I
____ .JI
R,
1Kn
SW-202 WAVEFORMS
LOGIC
INPUT
~15V
REPEAT TEST FOR 1N2. 1N3, AND IN4
* 35V LOGIC INPUT
ov
CROSSTALK TEST CIRCUIT
tr,tf<20ns
50%
O.lVO
SW-201 OUTPUT
.,
VA = 5V RMS
@f"500kHz
50n
09VO
Vo
j
-5V
VD'
I--'ON-
I--'OFF~
.0
*SWITCH OUTPUT WAVEFORM SHOWN FOR Vs = CONSTANT WITH LOGIC INPUT
WAVEFORM AS SHOWN Vo IS THE STEADY STATE OUTPUT WITH SWITCH ON
CAOSSTALK=20 LOG V02
V"
13-38
1/86, Rev. A
-----------l1fHD
SW-201/SW-202 QUAD SPST JFET ANALOG SWITCHES
APPLICATIONS INFORMATION
OPERATION FROM SINGLE POSITIVE POWER SUPPLY
This analog switch employs ion-implanted JFETs in a switch
configuration designed to assure break-before-make action.
The turn-off time is much faster than the turn-on time to
guarantee this feature over the full operating temperature
and input voltage range. Fabricated with Bipolar-JFET processing rather than CMOS, special handling is not necessary
to prevent damage to these switches. Because the digital
inputs only require a 2V logic "1" input level, powerconsuming pull up resistors are not required for TTL compatibility to insure break-before-make switching as is most
often the case with CMOS switches. The digital inputs utilize
PNP input transistors where input current is maximum at the
logic "0" level and drops to that of a reverse-biased diode as
the input voltage is raised above ~ 1.4V.
V+
.:s: +38V
13
v.
1/4SW201
O:-:;VANALOO:'SY+-4V
YO UT
o-----"if---if I
I
I
I
r------,
I
IL...TTL
g:T~MOS ~:-0-'1"""--'
______ ...
The "ON" resistance, RON, of the analog switches is constant
over the wide input voltage range of -15V to +11V with
VSUPPLY = ±15V. For normal operation, however, positive
input voltages should be restricted to 11V (or 4V less than the
positive supply). This assures that the VGsof an OFF switch
remains greater than its Vp, and prevents that channel from
being falsely turned ON. Individual switches are "ON" without power applied.
TYPICAL APPLICATIONS
PROGRAMMABLE GAIN NONINVERTING AMPLIFIER WITH SELECTABLE INPUTS
+15V -15V
~~-------~-~--~--~-OVOUT
+15V
+lSV
1X
18kn
99kn
999kn
~--=J--------A ~"C>-+''----+10X
~--4-------A ~"C>-+"-----f----"00X
"0-+---+---+---+ 1000X
2k"
13-39
100kn
100kn
1/86, Rev. A
S~-7510/S~-7511
®IPMI)
QUAD SPST JFET
ANALOG SWITCHES
Precision Monolithics Inc.
FEATURES
GENERAL DESCRIPTION
• Pin Complltlble with AD7510 01, AD7511 01
• JFET Switches Rllther thlln CMOS
• Highly Reslstllnt to Static Dlschllrge Dllmage
• Radiation Resistant
• No SCR Llltch-up Problems
• Low "ON" Resistance - 750 MIIX
• Superior "OFF" Isolation and Crosstalk
• Digital Inputs Compatible with TTL and CMOS
• No Pull-Up Resistors Required to Insure
Break-Before-Make Action with TTL Inputs
The SW-7510/7511 are monolithic linear devices, each containing four independently selectable SPSTanalog switches.
The SW-7510 operates normally-open with logic-low inputs.
The SW-7511 operates normally-closed with logic-low inputs.
All logic inputs are fully TTL input compatible.
Performance advantages include exceptionally high "OFF"
isolation, low leakage current and low crosstalk. Data conversion, position controllers, choppers, demodulators and
programmable-gain amplifiers are popular SW-7510/7511
circuit applications.
The PMI Bipolar-JFET process reduces susceptibility to
electrostatic destruction and offers a high resistance to
radiation exposure. Plus, total freedom from the intrinsic
SCR latch-up problems encountered in equivalently manufactured CMOS products.
ORDERING INFORMATIONt
TYPICAL
25°C
RESISTANCE
PACKAGE
HERMETIC
DIP
TEMPERATURE
RANGE
60n
SW7510AO"
SW7510EO
MIL
INO
80n
SW7510BO"
SW7510FO
MIL
INO
60n
SW7511AO"
SW7511EO
MIL
INO
80n
SW7511BO"
SW7511FO
MIL
INO
PIN CONNECTIONS
16-PIN HERMETIC DUAL-IN-LINE
(O-Sufflx)
CONTROL LOGIC:
SW-7510: Switch "ON"
for Address "HIGH"
SW-7511: Switch "ON"
for Address "LOW"
"For devices processed In total compliance to MIL-STO-883, add 18S3 after
part number. Consult factory for 883 data sheet
t All commerCial and industrial temperature range parts are available with
burn-In For ordering information see 1986 Data Book, Section 2.
SCHEMATIC DIAGRAM (Typical SW-7510 Switch)
LOGIC
INPUT
G A O U N O o - - - + - - - - - - + - - - -.....- - . . J
13-40
1/86, Rev. A
-------------l~ SW-7S10/SW-7S11 QUAD SPST JFET ANALOG SWITCH
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C, unless otherwise noted).
V+ Supply to Ground .............................. 36V
Logic Input Voltage ...•.....•.. (-2V or V-) to V+ Supply
Analog Input Voltage
Continuous ............. V- Supply to V+ Supply +20V
1% Duty Cycle and Driving
all 4 Inputs with
Operating Temperature Range,
SW-7510/7511AO, SO •...•..•.•..•.. -55°C to +125°C
SW-7510/7511 EO, FO ..•.••..••.••.•• -25°Cto+85°C
DICE Junction Temperature (Ti) ...•... -65°C to +150°C
Storage Temperature Range .•...•••..• -65°C to +150°C
Power Dissipation •..•...•••••...•••.•..•....•.. 500mW
Derate above 100°C ••.••••.•..•.•..••.•..•• 10mW/oC
500l"s pulse •..•.•. V- Supply -15V to V+ Supply +20V
Maximum Current Through Any Pin •.•...•••.•.... 25m A
Lead Temperature (Soldering, 60 sec) •.•••........ 300°c
Maximum Junction Temperature ......•.•.••.••... 150°C
V+ Supply to V- Supply ............................ 36V
ELECTRICAL CHARACTERISTICS
at Vs
NOTE: Absolute ratings apply to both DICE and packaged parts. unless
otherwise noted
= ± 15V and TA = +25° C, unless otherwise noted.
SW-7S10AlE
SW-7S11A/E
SW-7S10B/F
SW-7S11B/F
PARAMETER
SYMBOL
CONDITIONS
TYP
MAX
"ON" Resistance
RON
Vo=OV, 108= 1mA
60
75
"RON vs Vo (Vs)
"RON
VD'" 10V, ID= 1mA
15
RON Match 01 Switches
RON Match
Vo = OV, los = 1mA
1.5
Analog Voltage Range
VA
Is = 1mA (Note 5)
"OFF" Leakage Current
IS{OFF)' IO(OFF)
Vs =+10V, VD =-10V, (Note 1)
+ iOION)
"ON" Leakage Current
IS(ON)
Logic "1" Voltage
V 1NH
(NoteS)
Logic "0" Voltage
V 1NL
(NoteS)
I'NL
V,N = +O.4V
Logic "0" CUrrent
MIN
+10
-10
MIN
TYP
MAX
80
100
15
10
+11
-15
15
+10
-10
10
Vs = Va = +10V, (Note 1)
20
10
30
nA
30
nA
V
O.B
35
15
OB
V
3.5
JJ.A
Logic Input Capacitance
C DiG
V,N = +O.4V
"ON" Switching Time
tON
Vs = -5V, RL = 1kn, C L = 7pF, (Note 4)
350
450
450
550
"OFF" Switching Time
tOFF
Vs= -5V. RL = 1kn. C L = 7pF, (Note 4)
260
300
350
450
"OFF" Isolallon
ISO OFF
(Note 2)
Crosstalk
CT
(Note 3)
Analog "OFF" Capacitance
CS(OFF1' CO(OFF)
Vs= IV, Vo=O
Analog "ON" Capacitance
eS(ON)' COlON)
Vs=OV,Vo=O
Feedthrough Capacitance
COS(OFF)
Vs=OV
COOIOFF)
Vs=OV
Vs=OV
04
04
Positive Supply Current
1+
Logic Inputs at "0" or "1"
50
90
30
90
mA
Negative Supply Current
1-
LogiC Inputs at "0" or "1"
2B
50
17
5.0
mA
Channel Capacitance
CSSIOFFJ'
1.5
%
V
20
15
n
%
+11
-15
10
UNITS
1.5
pF
ns
~
p..
.......
b
::J
~
VJ
~
::r::
U
f-<
.......
ns
~
66
dB
C)
70
70
dB
0
6.5
65
pF
14
14
pF
OB
OB
pF
04
04
pF
VJ
66
NOTES:
1 The conditions listed specify the worst case leakage currents The leakage
currents apply equally to source (8) or drain(D)
OFF Isolation IS measured by drivmg the source of any OFF SWitch and
observing the voltage which appears on the drain The conditions are.
RL = 6BOn, C L = 7pF, Vs = 5V RMS ' 1= 100kHz
Crosstalk IS measured by driVing source of any OFF sWitch and obserVing
voltage which appears on any other "ON" output drain The conditions
are RL = 6BOn. C L = 7pF, Vs = 5V RMS • 1 = 100kHz
4 Sample tested
5. Guaranteed by RON and leakage tests For normal operation maximum
analog signal voltages should be restricted to less than (V+) -4V
13-41
~
1/86, Rev. A
~
II
-------------l~ SW·7510/SW·7511 QUAD SPST JFET ANALOG SWITCH
ELECTRICAL CHARACTERISTICS at Vs = ±15V, -55°C $; TA$; +125°C for SW·7510AO, SO and SW·7511AO, SO; and
-25°C $; TA $; +85° C for SW·7510EO, FO and SW·7511 EO, FO, unless otherwise noted.
SW·7510A/E
SW·7511 AlE
MIN
TYP
SW·7510B/F
SW·7511B/F
MAX
MIN
TYP
MAX
UNITS
PARAMETER
SYMBOL
CONDITIONS
"ON" Aesistance
AON
Vo= OV.IOS= 1mA
~RON VB.
"RON Drift
Vo=OV.los= 1mA
Analog Voltage Range
VA
Is= 1mA (Note 4)
"OFF" Leakage Current
IS{OFFI,ID(OFF)
"ON" Leakage Current
'SION)
Logic "1" Voltage
V,NH
(Note 4)
Logic "0" Voltage
V,NL
(Note 4)
0.8
0.8
V
Logic "0" Current
I'NL
V ,N = +0.4V
5.0
7.0
J.lA
"ON" Switching Time
tON
Vs = -5V, RL = 1kO, C L = 7pF (Note 2)
600
1000
ns
"OFF" SWitching Time
tOFF
Vs= -5V, AL = 1kO, CL = 7pF (Note 2)
500
750
ns
Positive Supply Current
1+
Logic Inputs at "0" or "1"
13
13
mA
Negative Supply Current
1-
Logic Inputs at "0" or "1"
7.5
7.5
mA
Temperature
+ 'D(ON)
100
150
0.4
+10
-10
+11
-15
+10
-10
°
0.5
%/'C
+11
-15
V
Vs = +10V. Vo = -10V. (Notes 1. 3)
90
100
nA
VS = Vo = +10V. (Notes 1. 3)
90
100
nA
2.0
2.0
V
NOTES:
1. The conditions listed specify the worst case leakage currents. The leakage
currents apply equally to source (S) ordrain(D).
2. Guaranteed by design.
3. Tested at 125'C only for "A" and "8" grades.
4. Guaranteed by RON and leakage tests.
13·42
1/86, Rev. A
-----------I1fMD
SW-7510/SW-7511 QUAD SPST JFET ANALOG SWITCH
DICE CHARACTERISTICS
SW-7510 (SWITCH ON FOR ADDRESS HIGH)
SW-7511 (SWITCH ON FOR ADDRESS LOW)
DIE SIZE 0.091 X 0.083 Inch, 7553 sq. mils
(2.311 X 2.108 mm, 1.918 sq. mm)
1.
2.
3.
4.
5.
6.
7.
8.
NEGATIVE SUPPLY (SUBSTRATE)
GROUND
ADDRESS (A1)
ADDRESS (A2)
ADDRESS (A3)
ADDRESS (A4)
DISABLE (NO CONNECT)
POSITIVE SUPPLY
9.
10.
11.
12.
13.
14.
15.
16.
DRAIN (04)
SOURCE (S4)
DRAIN (03)
SOURCE (S3)
DRAIN (02)
SOURCE (S2)
DRAIN (01)
SOURCE (S1)
1.
2.
3.
4.
5.
6.
7.
8.
NEGATIVE SUPPLY (SUBSTRATE)
GROUND
ADDRESS (A1)
ADDRESS (A2)
ADDRESS (A3)
ADDRESS (A4)
DISABLE (NO CONNECT)
POSITIVE SUPPLY
9.
10.
11.
12.
13.
14.
15.
16.
DRAIN (04)
SOURCE (S4)
DRAIN (03)
SOURCE (S3)
DRAIN (02)
SOURCE (S2)
DRAIN (01)
SOURCE (S1)
For additional DICE Information refer to 1986 Data Book, Section 2.
WAFER TEST LIMITS at V+
PARAMETER
= + 15V, V- = -15V, TA =25°C, unless otherwise noted.
SW-7510NI
SW-7511N
SW-7510GI
SW-7511G
LIMIT
LIMIT
UNITS
75
100
OMAX
SYMBOL
CONDITIONS
RON
Vo=OV.los=1mA
Logic "1" Voltage
V 1NH
(Note 1)
2.0
20
VMIN
Logic "0" Voltage
V 1NL
(Note 1)
0.8
0.8
V MAX
Logic "0" Current
I'NL
V'N= +O.4V
3.5
3.5
IJ.AMAX
Positive Supply Current
1+
Logie Inputs at "0"
9
9
mAMAX
Negative Supply Current
1-
Logie Inputs at "0"
5
mAMAX
"ON" Resistance
NOTES:
1. Guaranteed by RON and leakage tests.
Electrical tests are performed at wafer probe to the limits shown. Due to vanatlons in assembly methods and normal yield loss, Yield after packaging IS not
guaranteed for standard product dice. Consult factory to negotiate speCifications based on dice lot qualification through sample lot assembly and testing
TYPICAL ELECTRICAL CHARACTERISTICS at V+ = + 15V, V- = -15V and TA = 25°C, unless otherwise noted.
PARAMETER
SYMBOL
SW-7510GI
SW-7511G
TYPICAL
TYPICAL
Vo=OV, 10S= 1mA
60
80
0
Vo=OV, los= 1mA
0.4
0.5
%/oC
"ON" Switching Time
Vs = -5V, RL = 1kO, C L = 7pF
350
450
ns
"OFF" Switching Time
Vs = -5V, RL = 1kO, C L = 7pF
260
350
"ON" Resistance
RON vs. Temperature
RON Drift
CONDITIONS
SW-7510NI
SW-7511N
13-43
UNITS
ns
1/86, Rev. A
_ _ _ _ _ _ _ _ _ _---1!fMDSW-7510/SW-7511 QUAD SPST JFET ANALOG SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS (Apply to all models. unless otherwise noted)
LARGE-SIGNAL SWITCHING
LARGE-SIGNAL SWITCHING
-
C I:~
Ii
~- :~
,:I
I-
~
_.-
.1
rj
~
I= ~
"
[~
,.
I"
I
M
1
:VI
I
SMALL-SIGNAL SWITCHING
,
ILl
•
100m
" VI
I
-
-
[H"E~
I
-
SMALL-SIGNAL SWITCHING
WITH FILTERING
..
- --~
.,,-+-•
I,I
-~ .
[~
" ,~
1';::'1
II.
i1
"'.,::1
.
1-
.~
~-
Ir:ii
ilil 1-
1Ii:~
.
' li:J
-II
'H-+
I
II.
-
,.
II
"
1::;:.1
,= ',,~
II
Il
-
SMALL-SIGNAL SWITCHING
WITH FILTERING
t~
:
, I
~
!~
111
-
SMALL-SIGNAL SWITCHING
II
I. '
-~".
~
.1
1 ,-11:
-
II.
SMALL-SIGNAL SWITCHING
WITH FILTERING
SMALL-SIGNAL SWITCHING
NOTE:
Upper Photo Traces: Logic Control Signal Ax (5v/DIV)
Lower Photo Traces: Switch Outputs Vo
13-44
1/86, Rev. A
-----------I~ SW-7510/SW-7511 QUAD SPST JFET ANALOG SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS (Apply to all models, unless otherwise noted)
NORMALIZED RON vs
SWITCH CURRENT (Is)
"ON" RESISTANCE (RON) vs
ANALOG VOLTAGE (VA)
II
120
110
100
v+ "
r
f-------
+15V
3
V-=-lSV
TA=25°C
lOS = ±lmA
g
80
~
70
t
2 -
V+ = +15V
V-=-1SV
1 _ TA =25°C
90
t---
SW7S10!11B, F
t---
E
60
8
50
---
-
9
1,ov/
;/
/
0
Sl751L'1~
RONvsTEMPERATURE
200
180
/
=
140
12 a
/'
V
t-~'O
~'5)
v- -15V
160 t-- .loS = 1 rnA
VA = OV
§
SW7510Jl 1, B. F
100
~
V A =-10V
..... n .H-
80
60
40
40
V
.J.-1"
z
1-:::
::::: I--"
f-""SW7510/11, A, E
7
30
20
20
-10 -8
-6
-4
4
-2
6
8
o.6
-5 -4
10
-3
-2
-1
SWITCH LEAKAGE CURRENTS
VB ANALOG INPUT VOLTAGE
300
v~ -
270
v-
a
,1,5V
180
10 (ON) + IS (ION)
IJI
90
60
Ih
30
lIL
-6
-4 -2
0
2
o-
60a
.........
Cs
-s
(OFF)
I---"
3
-6 -4
-2
a
-20
I
4
B
10
-15V
TA = 25°C
SEE AC TEST
f-CIRCUIT
0:
o
r- r--;;
IINL -
30a
-
.....
10a
-60 -40 -20
55o
0
20
40
60
80 100 120 140
TEMPERATURE (OC)
40 0
~
~ -70
-90
10k
lOOk
0
,~ 0
-'SW7~1O/1;, A, I~ __
IIII~
1M
13-45
V
0<
~
V
:-'- , ""'"""'"
30
FREQUENCY (Hz)
100 120 140
SW7510!11, B, F
TON
,/'
Clilllill
'"
~I
v:
TON
350
3
~
~
50o
t/
0 20
40 60 80
TEMPERATURE (OC)
V- = -150
Vs = -5V
45 0
OFF ISOLATIO;;'
~ -60
o .... 0
20a
~±,oj'A;E
SWITCHING TIMES
vs TEMPERATURE
60 a
11111111
40 a
t-
-60 -40 -20
65 a
J, ~ l,~UIII
r-v- '"
~~~~~G~~~LL~~7~~'o"
500
...... I----.
a
2
CROSSTALK AND "OFF"
ISOLATION vs FREQUENCY
r-- -.......
1+ SW7510!11, A, E
[-t---{..J L
1
a
-10 -8
DIGITAL INPUT
CURRENT IINL
VB TEMPERATURE
r---.
-----
5
VA (VOLTS)
I
100 120 140
lON) t--"-
8
10
80
~ +,Jv
2
B
60
V+
V-=-15V
-
VA (VOLTS)
_tol"5J
40
8
C
80a
70a
0
0
~
20
SUPPLY CURRENTS
VB TEMPERATURE
2
4
0
TEMPERATURE (OC)
2
V-=-15V
90
a
-60 -40 -20
10 (OFF)
a
-10 -8
1000
4
/
120
1100
6'
,I IO~FI
IS
150
5
v+ =+1SV
v-= -15V
TA = 25°C
8_
210
4
SWITCH CAPACITANCES
vs ANALOG VOLTAGE (VA)
= -15V
TA = 25"C
240
3
IS (rnA)
VA-ANALOG INPUT VOL TAGE (VOLTS!
25
J~
,/'
V
I--- I--"
SW7510/11, A, E
TOFF
20o _ ~~~~'0/1', B, F
10M
15a
-60 -40
20
0
20
40
60
80
laO 120 140
TEMPERATURE (eC)
1/86, Rev_ A
_ _ _ _ _ _ _ _ _ _-1~SW-7510/SW-7511 QUAD SPST JFET ANALOG SWITCH
AC TEST CIRCUITS
CROSSTALK MEASUREMENT CIRCUIT
+15V
-15V
CROSSTALK'" 20 LOG
v-
0~~
1----...--,
0,
'pF
VSUPPLY = ± 15V. Higher input voltage is tolerable provided
that some form of current limiting is employed (such as that
of an op-amp output stage) to avoid exceeding junction
temperature and power dissipation requirements. For normal
operation, however, positive input voltages should be
restricted to 11V (or 4V less than the positive supply). This
assures thatthe Vas of an OFF switch remains greater than its
Vp, and prevents that channel from being falsely turned ON.
Individual switches are "ON" without power applied.
Proper switching requires the "Source" terminal be connected to the input driving signal.
'pF
LATCHING DPDT SWITCH
FOR SW-7511 REVERSE VOL rAGE TO A, & A2
+15V
AD
-a
.
a
5
PR
ISOLATION MEASUREMENT CIRCUIT
t15V
INPUT 1
'/2
-15V
v,
,.
V'
SN7474
VOFF ISOLATION
S,
~
20 LOG
~~,1
OUTPUT 1
INPUT 2
CLR
INPUT 3
SW-7510
son
0,
A,
Al
OUTPUT 2
'pF
INPUT 4
FOR SW-7S11 CONNECT A, TO +5V
SWITCHING TIME TEST CIRCUIT
+15V
Truth Table
State of Switches
-15V
Command
+~~ J"1..I"L
"v+,--,lv-'"
Ao
1
r-~--JA
o
1
SW-751'
o
After Command
82 and 83
81 and 83
same
same
on
off
off
on
INDETERMINATE
INTEGRATOR WITH ANALOG RESET AND
START/STOP CAPABILITY
APPLICATIONS INFORMATION
1/.
This analog switch employs ion-implanted JFETs in a switch
configuration designed to assure break-before-make action.
The turn-off time is much faster than the turn-on time to
guarantee this feature over the full operating temperature
and input voltage range. Because the digital inputs only
require a 2.0V logic "1" input level, power-consuming pull-up
resistors are not required for TTL compatibility to insure
break-before-make switching as is most often the case with
CMOS switches. The digital inputs utilize PNP input transistors where input current is maximum at the logic "0" level and
drops to that of a reverse-biased diode (about 10nA) as the
input voltage is raised above ~ 1.4V.
SW7510Fa
RL
r- 14
r-"W'v_T
1/.
SW7510FQ
I
~RESET
13
-,sv
+15V
Vo = llRC
.r---<~-{)
The "ON" resistance, RON, of the analog switches is constant
over the wide input voltage range of -15V to +11V with
J VINdt
NOTE: Applicallons show SW-7510. For SW-7511 applicallons the logic is
inverted.
13-46
1/86, Rev. A
------------I~ SW-7510/SW-7511 QUAD SPST JFET ANALOG SWITCH
TYPICAL APPLICATIONS
ACTIVE LOW-PASS FILTER WITH DIGITALLY SELECTED BREAK FREQUENCY
,.0
+15V
fCO
r"
fC3
,.
120
CONTROL
fC2
z
,.
"""
.0
.....
w
":;a 40
12
>
SELECT
fCl
OPEN
..... ...... OP-02
LOOP GAIN
[
SELECT
TTL
---.,
'"
~
iC4, l-fL
fCl
fC3
'C2
""'-
............... ............. ...............
............. ~ f~
"'-.....
10
SELECT
.............
.....
~ fl.,
"'-..... ................
............. ............... ...............
fO
1K
fOO
10K
100K
fM
FREQUENCY - Hz
AL (VOLTAGE GAIN BELOW BREAK FREQUENCY)
~------------------~---oVOUT
R3
Rf
~ 100 (40dB)
Ie (BREAK FREQUENCY)
~ 211"~3CX
IL (UNITY GAIN FREQUENCY)
NOTE: Applications show SW-7510. For SW-7511 applicallons the logic
inverted.
~
= 211"~'CX
IS
13-47
1/86, Rev_ A
MUX-08/MUX-24
8-CHANNEL/DUAL 4-CHANNEL JFET ANALOG MULTIPLEXERS
10VERVOLTAGE AND POWER SUPPLY LOSS PROTECTEDj
Precision Mono1ithics Inc.
break-before-make action without the need for external pullup resistors over the full operating temperature range,
FEATURES
•
•
•
•
•
•
•
•
JFET Switches Rather Than CMOS
Low "ON" Resistance ...................... 2200 Typ
Highly Resistant to Static Discharge Damage
No SCR Latch-Up Problems
Digital Inputs Compatible With TTL and CMOS
125 0 C Temperature Tested Dice Available
MUX-OS Pin Compatible With DG50S, HI-508A, IH510S,
IH6108, LF1150S/1250S/1350S, AD7506
MUX-24 Pin Compatible With DG509, HI-509A, IH520S,
IH6208, LF11509112509/13509, AD7507
For single sixteen-channel and dual eight-channel models,
refer to the MUX-16/MUX-28 data sheet.
PIN CONNECTIONS
ORDERING INFORMATIONt
PACKAGE
25'C ON
HERMETIC PLASTIC
RESISTANCE
DIP
DIP
220n
MUXOBAO'
MUXOBEO
300n
MUXOBBO'
MUXOBFO
220n
MUX24AO'
MUX24EO
LCC
16-PIN DUAL-IN-LINE PACKAGE
(Q or P Package)
MIL
INO
COM
MUXOBEP
300n
TEMPERATURE
RANGE
MUXOBBRCIBB3
MUXOBFP
MIL
INO
COM
MUX24EP
MIL
INO
COM
MUX24FP
MIL
INO
COM
MUX24BO'
MUX24FO
MUX-OSBRC/SS3
LCC
(RC-Suffix)
Mll-STO-883, add /883 after
part number Consult factory for 883 data sheet.
tAil commerCial and Industrial temperature range parts are available WIth
burn-In. For ordenng information see 1986 Data Book, Section 2
* For devices processed In total compliance to
FUNCTIONAL DIAGRAMS
GENERAL DESCRIPTION
The MUX-08 is a monolithic eight-channel analog mUltiplexer which connects a single output to one of the eight
analog inputs depending upon the state of a 3-bit binary
address.
GND
The MUX-24 is a monolithic four-channel differential analog
multiplexer configured in a double pole, four-position (plus
OFF) electronic switch array. A two-bit binary input address
connects a pair of independent analog inputs from each
four-channel input section to the corresponding pair of
independent analog outputs.
All switches in the MUX-08/MUX-24 are turned OFF by
applying logic "0" to the ENABLE pin, thereby providing a
package select function.
ENABLE
Al
AO
v.
GNO
Fabricated with Precision Monolithics' high performance
Bipolar-JFET technology, these devices offer low, constant
"ON" resistance, low leakage currents and fast settling time
with low crosstalk to satisfy a wide variety of applications.
These multiplexers do not suffer from latch-up or static
charge blow-out problems associated with similar CMOS
parts, The digital inputs are designed to operate from both
TTL and CMOS levels while always providing a definite
v-
DRAIN
A
13-48
SlA
S2A
S3A
S4A
SlB
S2B
S3B
S4B DRAIN
B
1/86, Rev. A
-------l~ Mux-oa/MUX-24 a-CHANNEL/DUAL 4-CHANNEL JFET ANALOG MULTIPLEXERS
ABSOLUTE MAXIMUM RATINGS
(Note)
Operating Temperature Range
Lead Temperature (Soldering, 60 sec) ••••••••••••• 300°C
Maximum Junction Temperature •.•••••••••••••••• 150'C
MUX-OS/24-AO, BO, BRC •.••••••.•• -55°C to +125°C
MUX-oS/24-EO, FO •••••••..••.•••••• -25° C to +S5° C
MUX-oS/24-EP, FP •••••••..••••.•••••••• 0° C to + 70° C
DICE Junction Temperature (TI ) •.•••••
Storage Temperature Range. • • • • • • • . ••
P-Suffix ••••••••••••••• • • • • • • • • • • •••
V+ Supply to V- Supply. • • • • •• • • • • • • • • • • • • • • • • • • • •. 36V
Logic Input Voltage. • • • • • • • • • •• (-4V or V-) to V+ Supply
-65°C to +150°C
Analog Input Voltage .... V-Supply-20Vto V+ Supply+20V
-65° C
-65° C
Maximum Current Through Any Pin
to + 150° C
to +
Power Dissipation ••••••••••••••.••••••••••••••• 500mW
Derate above 100° C
NOTE: Absolute rallngs apply to both DICE and packaged parts, unless
otherwise noted
•••••••••••••••••.•••••• 10mW/o C
ELECTRICAL CHARACTERISTICS
at V+ = + 15V, V- = -15V and TA = 25' C, unless otherwise noted.
MUX-08A1E
MUX-24A1E
PARAMETER
SYMBOL
CONDITIONS
"ON" Resistance
RON
Vs ';10V, Is'; 200~A
ARoN With Applied Voltage
ARoN
-10V'; Vs'; 10V, Is =
MIN
RON Match Between SWitches
VA
(Note6)
Source Current (Switch "OFF")
Is 10FF,
Vs = 10V. Vo = -10V (Note 1)
Digital Input Current
300
IO{OFF)
Vs= 10V. Vo =-10V (Note 1)
MUX-OB
MUX-24
IO(ONl
Vo = 10V (Note I)
MUX-OB
MUX-24
liN
Y,N = O.4V to 15V
'INL(EN)
VEN = 0 4V
Digital Input Capacitance
COIG
TYP
MAX
300
400
UNITS
n
%
+10 +104
-10
-15
Digital "0" Enable Currant
MIN
15
Vs = OV, Is =
+ISION,
MAX
220
200~A
RON Match
Leakage Current (Switch "ON")
TYP
MUX-OBB/F
MUX-24B/F
200~A
Analog Voltage Range
Drain Current (Switch "OFF")
•••••••.••••••• 25mA
125° C
20
+10 +10.4
-10
-15
%
V
001
10
001
20
nA
01
005
10
10
01
005
20
20
nA
01
005
10
10
0.1
0.05
20
20
nA
10
~A
10
~A
10
10
3
4
3
pF
tTRAN
1B
Output Settling Time
ts
10V Step to 0.10%
10V Step to 0 05%
10V Step to 0.02%
13
15
23
17
19
25
~s
Braak-Belore-Make Delay
tOPEN
Figure 3 (Test CorCUlt)
OB
10
~s
tON (EN)
(Note 5) Figure 2
(Test CorCUlt)
tOFF (EN)
(Note 5) Figure 2
(Test CorCUlt)
MUX-OB
MUX-24
01
02
ISO OFF
(Note 4) Figure 5
(Test CircUit)
MUX-08
MUX-24
60
66
60
66
dB
Crosstalk
CT
(Note 3) Figure 4
(Test CorCUlt)
MUX-08
MUX-24
70
76
70
76
dB
Source Capacitance
es (OFF)
SWitch "OFF",
Vs= OV, Vo= OV
MUX-08
MUX-24
25
25
Drsln Capacitance
CD(OFF)
SWitch "OFF",
Vs=OV, Vo=OV
MUX-08
MUX-24
7
4
7
4
pF
Input to Output Capacitance
COSIOFF'
(Note 4)
MUX-OB
MUX-24
03
015
03
015
pF
Positive Supply Currant
(All Digital Inputs
Logic "0" or "1 ")
1+
V+= 15V
V+=5V
10
8
12
6
5
12
Negative Supply Current
(All Digital Inputs
Logic "0" or "1 ")
1-
V+=-15V
V+ =-5V
30
25
38
20
18
38
Enable Delay "ON"
Enable Delay "OFF"
"OFF" Isolation
21
04
05
1B
02
03
21
3
p.,
.......
(Notes 2,5) Figure 1
(Test CorCUlt)
Switching Time
~
I-I-1
~s
~
~
I-I-1
::r:
U
tI)
r-<
.......
~
C)
2
~s
04
06
~s
0
~
II
pF
mA
mA
NOTES: See next page
1/86, Rev. A
13-49
~---------
._----.
-----------~-
_ _ _ _ _ _-I~MUX.oa/MUX.24 a·CHANNEL/DUAL 4-CHANNEL JFET ANALOG MULTIPLEXERS
ELECTRICAL CHARACTERISTICS at V+ = 15V, V- = -15V and -55° C:5 TA:5 125° C, unless otherwise noted,
MUX"()BAI
MUX-24A
PARAMETER
SYMBOL
CONDITIONS
"ON" Resistance
RON
Vs S 10V, Is S 200/AA
.:IoR ON With Applied Voltage
.:IoR ON
-10V S Vs S 10V, Is = 200"A
RON Match Between Switches
RON Match
Vs =OV,l s =200"A
MIN
TVP
MUX·OBBI
MUX-24B
MAX
MIN
TVP
400
MAX
500
15
UNITS
0
4,5
%
10
15
%
+10 +10.4
-10
-15
+10 +10.4
-10
-15
V
Analog Voltage Range
VA
(NoteS)
Source Current (Switch "OFF")
'SIOFFI
Vs = 10V. Vo = -10V (Notes 1, 7)
25
50
nA
'OIOFFI
Vs= 10V, Vo =-10V
(Notes 1, 7)
MUX-oa
MUX-24
100
50
500
500
nA
MUX-08
MUX-24
100
50
500
500
nA
Drein Current (Switch "OFF")
Leakage Current (Switch "ON")
1010NI
+ISIONI
Vo= 10V (Noles 1, 7)
Digital "1" Input Voltage
V 1NH
(NoteS)
Digital "0" Input Voltage
VINL
(NotaS)
0.7
0.7
V
Digital Input Current
liN
VIN = 0.4V to 15V
20
20
"A
Digital "0" Enable Current
IINLIENI
V EN = 0.4V
20
20
"A
Positive Supply Current
1+
All Digital Inputs Logic
"0"or"1"
15
15
rnA
Negative Supply Current
1-
All Digital Inputs
Logic "0" or "1"
5
5
rnA
2
V
ELECTRICAL CHARACTERISTICS at V+ = 15V, V-= -15V and -25°C:5 TA:5 +B5°C for MUX-OBEQ, FQ and
MUX-24EQ, FQ; 0° C:5 TA:5 +70°C for MUX-DBEP, FP and MUX-24EP, FP, unless otherwise noted.
MUX"()BEI
MUX-24E
PARAMETER
SYMBOL
CONDITIONS
"ON" Resistance
RON
VsS 10V,I s S 2oo"A
.:IoR ON With ApplIed Voltage
.:loR ON
-10V S Vs S 10V, Is = 200"A
RON Match Between SWItches
RON Match
Vs = OV, Is = 200"A
MIN
TVP
MUX-OBFI
MUX-24F
MAX
MIN
TVP
400
MAX
500
15
UNITS
0
4.5
%
10
15
%
+10 +10.4
-10
-15
+10 +10.4
-10
-15
V
Analog Voltage Range
VA
(Note 6)
Source Current (Switch "OFF")
ISIOFFI
Vs= 10V, V o =-10V (Notes 1, 7)
10
10
nA
Drain Current (SWitch "OFF")
'OIOFFI
Vs= 10V, Vo =-10V
(Notes 1, 7)
MUX-oS
MUX-24
100
50
100
50
nA
Leakage Current (Switch "ON")
'OIONI
+ISIONI
Vo= 10V (Notes 1, 7)
MUX-oS
MUX-24
100
50
100
50
nA
Digital "1" Input Voltage
VINH
(Note 6)
DIgital "0" Input Voltage
VINL
(NoteS)
O.S
- O.S
V
Digital Input Current
'iN
VIN = 0.4V to 15V
20
20
"A
Digital "0" Enable Current
IINLIENI
VEN =0.4V
20
20
"A
Positive Supply Current
1+
All Digital Inputs Logic
"0"or"1"
15
15
rnA
Negative Supply Current
1-
All DigItal Inputs
Logic "0" or "1"
5
5
rnA
NOTES:
1 Conditions applied to leakage tests insure worst case leakages. Exceeding 11 V on the analog input may cause an "OFF" channel to turn "ON"
2. RL = 10MO, C L = 10pF.
3. Crosstalk Is measured by driVing channel S with channel 4 "ON".
RL = 1MO, C L = 10pF, Vs = 5V RMS, I = 500kHz.
2
V
4.
"OFF" isolation is measured by driving channelS WIth ALL channels "OFF"
RL = 1kO, C L = 10pF, Vs=5V RMS, I = 500kHz. COS is computed Irom the
OFF isolation measurement.
5 Sample tested.
S Guaranteed by leakage current and RON tests.
7. Leakage tests are performed only on military temperature grades at 125'C.
13-50
1/86, Rev. A
--------1~ Mux-oa/MUX-24 a-CHANNEL/DUAL 4-CHANNEL JFET ANALOG MULTIPLEXERS
DICE CHARACTERISTICS (125°C TESTED DICE AVAILABLE)
~!!!!!!IIIIIII!!!!!!11 MUX-OB
MUX-24
DIE SIZE 0.090 x 0.061 Inch, 5490 sq. mils
(2.286 X 1.549 mm, 3542 sq. mm)
9.
10.
11.
12.
13.
14.
15.
16.
1. AO
2. ENABLE
3. Y- (SUBSTRATE)
4. S1
5. S2
6. S3
7. S4
8. DRAIN
S8
S7
S6
S5
9.
10.
11.
12.
13.
14.
15.
16.
1. AO
2. ENABLE
3. Y- (SUBSTRATE)
4. S1 A
5. S2A
6. S3A
Y+
GND
A2
A1
7. S4A
8. DRAIN A
DRAIN B
S4 B
S3 B
S2 B
S1 B
Y+
GND
A1
For additional DICE informalion refer 10
1986 Data Book, Section 2.
WAFER TEST LIMITS at V +
PARAMETER
= 15V, V - = -15V, TA = 25 ·C, unless otherwise noted. (Note 1)
SYMBOL
CONDITIONS
RON
Vs = OV,
Is = 200~A
Digital "1" Input Voltage
V,NH
(Note 2)
Digital "0" Input Voltage
V,NL
(Note 2)
Digital "0" Input Current
I'NL
V,N =04V
"ON" Resistance
Digital "0" Enable Current
ItNL(ENI
Positive Supply Current
(All Digital Inputs Logic "0")
1+
Negative Supply Current
(All Digital Inputs Logic "0")
1-
Analog Input Range
VA
V ,N =04V
MUX-OB/
MUX-24NT
MUX-OB/
MUX-24N
MUX-OB/
MUX-24G
LIMIT
LIMIT
LIMIT
300
400
300
400
O.B
O.B
O.B
10
20
10
10
TA = 125"C
10
10
TA =125"C
10
20
12
15
12
12
TA =125"C
3.B
5
38
3.B
TA = 125"C
±10
±10
±10
TA = 125"C
UNITS
nMAX
VMIN
(Note2)
V MAX
~AMAX
~AMAX
mAMAX
mAMAX
V MIN
NOTE:
Electrical tests are performed at wafer probe to the limits shown Due to variations in assembly mehtods and normal Yield loss, yield after packaging is not
guaranteed for standard product dice Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testmg.
TYPICAL ELECTRICAL CHARACTERISTICS at V+ = 15V, V-=-15V and TA = 25°Cfor MUX-08/24N & G, TA= 125°C for
MUX-08/24NT, unless otherwise noted.
MUX-OB/
MUX-24NT
MUX-OS/
MUX-24N
MUX-OS/
MUX-24G
TYPICAL
TYPICAL
TYPICAL
(Note 1)
17
13
2.1
~s
ts
10V Step to 0.1% (Note 1)
21
1.5
1.9
~s
PARAMETER
SYMBOL
CONOITIONS
Switching Time
tTRAN
Output Settling Time
UNITS
Break-Belore-Make Delay
t OPEN
(Note 1)
O.B
OB
1.0
~s
Crosstalk
CT
(Note 1)
70
70
70
dB
~RON
20
05
0.5
nA
+10.4/-15
+104/-15
+10.4/-15
V
With Applied Voltage
~RoN
-10V ,; Vs'; 10V, Is =
Leakage Current (Switch "ON")
IO{ON)
V D= 10V (Note 1)
Analog Input Range
VA
200~A
NOTES:
1. The data shown is extrapolated from measurements made on the
packaged deVices
%
2
13-51
Guaranteed by leakage current and RON tests.
1/86, Rev. A
IEMD
MUX-08/MUX-24 8-CHANNEL/DUAL 4-CHANNEL JFET ANALOG MULTIPLEXERS
MUX-08
LOGIC STATE
MUX-24
LOGIC STATE
EN
"ON"
CHANNEL
X
L
NONE
L
H
EN
"ON"
CHANNEL
Al
Ao
X
L
NONE
X
L
H
L
A2
Al
AO
X
X
L
L
L
L
H
H
2
L
H
H
2
L
H
L
H
3
H
L
H
3
L
H
H
H
4
H
H
H
4
H
L
L
H
5
H
L
H
H
6
H
H
L
H
7
H
H
H
H
8
TYPICAL PERFORMANCE CHARACTERISTICS (Applies to all grades, unless otherwise noted.)
MUX-08
BREAK-BE FORE-MAKE
SWITCHING
MUX-08
LARGE-SIGNAL SWITCHING
RL = lkn, CL = lDpF, V'f, B '" 10V
RL = lMn, C L = 10pF,
VOLTAGE = 2V/DIV
TIME = 200ns/DIV
VOLTAGE = 5V/DIV
TIME = l/-1s/0lV
MUX-08
SMALL-SIGNAL SWITCHING
WITH FILTERING
RL = lMn, CL '" 500pF, Vl '" SOOmV, Va = +500mV
VOLTAGE = SOOmV/DIV
TIME = lMS!DIV
V, = -10V, Vs '" +10V
MUX-08
SMALL-SIGNAL SWITCHING
V, = -50amV, V8 = +500rnV
Rl = lMn, Cl = 10pF,
VOLTAGE SOOmV/DIV
=
TIME'" ')"s/DIV
MUX-08
SMALL-SIGNAL SWITCHING
WITH 21's SAMPLE TIME
V, = -SOamV, Va = +500mV
MUX-08
SMALL-SIGNAL SWITCHING
WITH FILTERING AND
2.51's SAMPLE TIME
RL = lMn, CL = 10pF,
VOLTAGE'" SOOmV/DIV
VOLTAGE = SOOmV/DIV
TIME = SOOns/DIV
TIME = SOOns/Drv
AL = lMn, Cl = 500pF. V, = -SOamV, Va = +500mV
NOTE:
Top waveforms: Digital Input 5v/DIV
Bottom waveforms: Multiplexer Output
13-52
1/86, Rev_ A
-------I~ Mux-oa/MUX-24 a-CHANNEL/DUAL 4-CHANNEL JFET ANALOG MULTIPLEXERS
TYPICAL PERFORMANCE CHARACTERISTICS (Applies to all grades, unless otherwise noted.)
MUX-08 CROSSTALK AND
OFF ISOLATION PERFORMANCE
OF CHANNEL 8
MUX-08 CROSSTALK AND
OFF ISOLATION PERFORMANCE
OF CHANNEL 8
~
140
CERAMIC
(0) PACKAGE
i
100
::::
r--.
~
o
z
o
80
~
60
~
40
,iii
.,.
OL-~~~LLUill~LUUill~LU~
lk
10k
lOOk
1M
~
>
IIII~I I I
I
V(+)
=
ISOL~~ION
11111
r-l::-~t-+
~v+.: 15V
1-
~
10
11111
05
RL = 1Mn, CL = 10pF, Vs = +5V RMS
OFF-ISOLATION
RL = lkn, C l = 10pF, Vs = +5V RMS
-
a
1k
10M
1M
lOOk
10k
-50
10M
-25
25
50
75
TEMPERATURE (DC)
FREQUENCY 1Hz)
FREQUENCY (Hz)
"ON" RESISTANCE (RON)
vs ANALOG VOLTAGE (VA)
ENABLE DELAY TIMES
vs TEMPERATURE
~~~-~:~:~~
-1SV
RL = 10Mn
CL _ 10pF
_ 15
CROSSTALK
20
---=t: - -
v -
j
11:::
OFF
+1SV
V(-) = -15V
TA = 2SOC
a
2
~ W~~STH
o
>0
25
f1:""
~ 120
~
TRANSITION TIMES
VB TEMPERATURE
lOa
125
RONVS SWITCH VOLTAGE (VSD)
600
V+ = +15V
v- = -15V
VS2 - VSB = OV
RL = 1 k.l1
-,L--~---"f-7"9---/
20
MUX-OBA, E
I
VSl
='
s
w
VSl = lOV
u
MUX-OSB, F
15
f--+-+-+-+-f-+---1IS = 200j./A
2V
~~m~
10~
05~
~A.E.
f--+-+-+-+-f-+---1~~~ ~~~J
3001--+-+-+-+-f-+-+:;';:';=r---1
f----+-+-+--+-t-+-+IS '" 200iJA
~
"
0
rr."
200
S
~
f-~-+-+~-f-+--+-t-+---1
300
~o
200
TA
0
25'le
MUX-24A.E -tOFF
-50
-25
25
50
75
100
-10
125
TEMPERATURE (Oe)
,
4
-8 -6 -4 -2
VA - ANALOG INPUT VOLTAGE (VOL TS\
500
r-'
r-
v+ -
15V
v- = -15V
500 ~ TA =25°C
S
w
u
"i;;
~
400
iii
-
~
"0
"
~
"-~ ~1i's
0
300
MUX-OB8,F
MUX.24B,y
A:
,.,
./
L'
MJX-08~.E
MUX-24A,E
I
v- '" -15V
IS'" 100/J-A
VA = OV
§
w
U
"i;;
~
300
z
200
V
"
~
LJ
~1;-~
MUX-'4. ,:::;:
/~
1>;::
v
'" -15V
T A == 2SoC
1.0
13
~
01
;2
;
:/'
'"~ 001
~
100
25
50
75
TEMPERATURE (OC)
13-53
100
125
--
I=--
f--
~-
r--- r-1=
r----
~
r----
0001
-25
800
ID(OFF)
=
I-S b-.
r---50
C-
r--
~
~
100
-2000
- 1200
-400 0 400
1200
2000
-1600
-800
SOD
1600
IS - SWITCH CURRENT (,uA)
MUX-24A,E_
10
MUp!-F--
~
0
I
I
;t1~
SWITCH LEAKAGE
CURRENTSvs
ANALOG INPUT VOLTAGE
V
, / / ~ V""'-
iii
0
100-
200
I
V+ OI'5V
400
/'
100
-800 -600 -400 -200
200 400 600
Vs - SWITCH VOLTAGE (mV)
10
RON vs TEMPERATURE
RON vs SWITCH CURRENT (Is)
600
--
--
V+ '" +15V +-+~-f-+--+-t--j
V- '" -15V +-+~-+-+--+-t--I
~~~:~~~:~-
D
-
I
Z
100 f-~-+-+~-f-+--+-t-+---1
~f'
~
z
0
I
V+ '" +15V
v- = -15V
TA '" 25°C
400
i;;
o
r-r--
r-
w
u
"
f----+-+-+--+-t-+-+~~~:~~!:~
~
500
-15
--
IS(OFF)
I'.
IOION)
\
-10
-5
10
VA - ANALOG INPUT VOLTAGE (VOLTS)
15
1/86, Rev. A
_ _ _ _ _ _-t~MUX-oa/MUX-24 a-CHANNEL/DUAL 4-CHANNEL JFET ANALOG MULTIPLEXERS
TYPICAL PERFORMANCE CHARACTERISTICS (Applies to all grades, unless otherwise noted.)
SWITCH LEAKAGE CURRENTS
vs TEMPERATURE
100
125
12
12
~
11
1>-
f-10
V+ _ +15V
1
10V
r,
f---~
"u
w
10
§ 0;: ro~v
~ Vo·
~a:
f---
~
'S~NI
'?IO,,/
+
01
fT
'-!-
7
~
1+
MUX-OSB,F
MUX·24B,F
,
I--- I -
-
Vs+ - +15V
Vs- = -1SV
10
/'
001
1
M1UX.24?,F
1
TEMPERATURE (OC)
MUX-24
SMALL-SIGNAL SWITCHING
MUX-24
SMALL-SIGNAL SWITCHING
WITH FILTERING
-25
25
RL'" lMn, Cl
=
lOpF,
50
75
100
125
v, = -sqOmV,
V4 = +500mV
VOL TAGE
=
SOOmV/DIV, TIME = lj.!s/DtV
MUX-24
SMALL-SIGNAL SWITCHING
WITH FILTERING
AND 2.5JLS SAMPLE TIME
RL = lMn, Cl = 500pF,
v,
= -SOOmV,
V4 = +500mV
VOLTAGE = SOOmV/DIV, TIME = SOOns/DIV
-55
-25
c~BI
,..... . . .
100
125
v.
T
COlOr'
I
--
1
0
25
50
75
TEMPERATURE fOCi
-55
i--i--
r--
r--
MUX-OBB,F
'stOFF)
I
v-· -15V
r--
MUX·24A,E
2
I),LI
Q
MUX-OBA,E
4
I--
TA=25 C
r--
9
B I'-f':::
~
!!}
f--- r--
MUX 08A,E
MUX-24A,E
2
': 5
~
1:'
~
-;/
1+
>6
'""
"
x
- - 'OIO~
MUX-08
SWITCH CAPACITANCES
vs ANALOG INPUT VOLTAGE
SUPPLY CURRENTS
vs TEMPERATURE
1
es{OFF)
......
I
-12
-8
-4
12
VA - ANALOG INPUT VOLTAGE (VOLTS)
RL'" lMfl, CL '" 500pF, Vl '" -500mV,
V4 '" +500mV
VOLTAGE'" 500mV/DIV, TIME'" l"s!DIV
MUX-24
BREAK-BEFORE-MAKE
SWITCHING
2Y
IpS
2L
20(N
RL'" lkfl, CL '" 10pF, Vl, 4 '" lOV
VOLTAGE'" 2V!DIV, TIME'" 200ns/DIV
MUX-24
SMALL-SIGNAL SWITCHING
WITH 2JLs SAMPLE TIME
v,
RL = lMn, CL = 10pF,
= -SOOmV,
V4'" +500mV
VOLTAGE'" 500mV!DIV, TIME'" 500ns!DIV
MUX-24
LARGE-SIGNAL SWITCHING
RL eo lMfl, CL '" 10pF, Vl '" -10V, V4 '" +10V
VOLTAGE'" 5V!DIV, TIME'" l/-1s!DIV
NOTE:
Top waveforms: Digital Input 5V1DIV
Bottom waveforms: MUltiplexer Output
13-54
1/86, Rev. A
--------1~ Mux-oa/MUX-24 a-CHANNEL/DUAL 4-CHANNEL JFET ANALOG MULTIPLEXERS
TYPICAL PERFORMANCE CHARACTERISTICS (Applies to all grades, unless otherwise noted.)
DIGITAL INPUT CURRENTS
VB TEMPERATURE
l+v- ,~v
=
= -15V
MUX-24
CROSSTALK AND OFF
ISOLATION PERFORMANCE
OF CHANNEL 3A
MUX-24
SWITCH CAPACITANCES vs
ANALOG INPUT VOLTAGE
12
I
10
ALL DIGITAL
INPUTS ARE
LOGIC "0"
~ 140
~ l+ .1'5J
v-
=
"~
r---- ........... r-......
IJ/:
-M=-=
,
IINL
-55
--::
_
CS(OFF)
'tf
80
0
II
>=
~)
:l
~
~
~
J-
0
60
V+ = 15V
v- = -15V
"
20
!t
-25
0
25
50
75
TEMPERATURE (OC)
100
125
-12
-8
-4
12
III
I
f!f:VD
Cos
0
~lil~:F' "'"
N'1i~S~ATlO~
I I: I ill r--
TA=25°C
CROSSTALK
RL = lMn, CL = 10pF, Vs = 5V RMS
RON (SWITCH NO 4) = 300n
OFF ISOLATION
RL = lkrl., CL ~ 10pF, Vs = 5V RMS
40
I
>,
hlll
No
~ 100
""0
z
Co (ON)
o
i" [J~~~~TAU i
120
~
-15V
lk
lOOk
10k
VA - ANALOG INPUT VOLTAGE (VOLTS)
1M
m
10M
FREQUENCY (Hz)
A.C. TEST CIRCUITS
BREAK-BEFORE-MAKE TEST CIRCUIT
TRANSITION TIME TEST CIRCUIT
* S1S
+15V
" SlB
S2A, S2B
+1SV
S2A, S2B
S3A, S3B
S3A, S3B
S4B
S4.
v+
+5V
EN
V+
S1(SlA)
NC(DB) S1(SlA)
+10V
Ne(DB)
+5V
A2(Ne}
r----1>---+----I A1
LOGIC
INPUT
LOGIC
INPUT
son
MUX-08
(MUX 24)
I----+-..--ovo
50"
( ) DENOTES MUX-24
Figure 1
S~:~7 t--------,
A2(NC)
.----1>---+----1 A 1
-lV
S8(S4A)
EN
( ) DENOTES MUX-24
Figure 3
ENABLE DELAY TIME TEST CIRCUIT
+lSV
+15V
" S18
S2A, S28
S3A, S3B
II
CROSSTALK MEASUREMENT CIRCUIT
'" SlA, S2A
S4A
S18-S4B
CHANNEL 4(4A) IS ON
S4B, S4A
V+
V+
Ne(DB) 81 (SlA)
+5V
-lV
S1-57
EN
NC(DB)
,----1 EN
1---------,
I-I
A2(NC)
Al
Al
LOGIC
INPUT
AO
MUX-08
(MUX-24l
son
t-.....-.--oVo
son
Figure 2
( ) DENOTES MUX-24
( ) DENOTES MUX-24
Figure 4
13-55
1/86, Rev. A
--------l1fM!} Mux-oa/MUX-24 a-CHANNEL/DUAL 4-CHANNEL JFET ANALOG MULTIPLEXERS
A.C. TEST CIRCUITS
APPLICATIONS INFORMATION
These analog multiplexers employ ion-implanted JFETs in a
switch configuration designed to assure break-before-make
action. The turn-off time is much faster than the turn-on time
to guarantee this feature over the full operating temperature
and input voltage range. Fabricated with Bipolar-JFET processing, special handling as required with CMOS devices, is
not necessary to prevent damage to this multiplexer. Because
the digital inputs only require a 2.0V logiC "1" input level,
power-consuming pull-up resistors are not required for TTL
compatibility to insure break-make switching as is most often
the case with CMOS multiplexers. The digital inputs utilize
PNP input transistors where input current is maximum at the
logic "0" level and drops to that of a reverse-biased diode
(about 10nA) as the input voltage is raised above'" 1.4V.
OFF-ISOLATION MEASUREMENT CIRCUIT
+15V
• SlA. S2A
""
SlB-S4B
ALL CHANNELS
ARE OFF
+04V
v+
EN
51-87 r - - - - - - - ,
(.)
NC(DB}
A2(Ne}
III
AD
50n
(':~~:~:l
r -......-----1SB(53A)
D(DII}r-_......--<>VD
The "ON" resistance, RON, of the analog switches is constant
over the wide input voltage range of -15V to +11V with
VSUPPLY = ±15V. Higher input voltage is tolerable provided
that some form of current limiting is employed (such as that
of an op-amp output stage) to avoid exceeding junction
temperature and power dissipation requirements. For normal
operation, however, positive input voltages should be restricted to 11V (or4V less than the positive supply). This assures
that the VGS of an "OFF" switch remains greater than its Vp ,
and prevents that channel from being falsely turned "ON".
When operating with negative Input voltages, the gate-tochannel diode will be turned on if the voltage drop across
an "ON" switch exceeds -0.6V. While this condition will
cause an error in the output, it will not damage the switch. In
lab tests, the multiplexer output has been loaded with a
O.Q1I'F capacitor in the circuit of Figure 1. With V1 = -10V and
Va = +10V, the logic input was driven at a 1kHz rate. The
positive-going slew rate was 0.3V1I'S which is equivalent to a
normal loss of 3mA. The negative-going slew rate was
0.7V1l's which is equivalent to a "reverse" loss of 7mA. Note
that when switch 1 is first turned "ON" it has a drop of -20V
across its terminals. In spite of that fact, the current is limited
to approximately twice its normal loss.
( I DENOTES MUX-24
Figure 5
SWITCHING TIME WAVEFORMS
SWITCH
OUTPUT
VD
(SEE FIG 1)
SWITCH
OUTPUT
VD
(SEE FIG 2)
CROSSTALK AND OFF-ISOLATION
Crosstalk and off-isolation performance is influenced by
the type of package selected. Epoxy (P) packaged devices
typically exhibit a 12dB improvement in off-isolation
(f = 500kHz) performance when compared to ceramic (0)
packaged devices. Epoxy packaged devices typically exhibit
a 15dB improvement in crosstalk (f = 500kHz) performance
when compared to ceramic (0) packaged devices.
VD
SWITCH
OUTPUT
60%
VD
(SEE FIG 3)
3.5V
SINGLE SUPPLY OPERATION OF JFET MULTIPLEXERS
PMI's JFET multiplexers will operate from a single positive
supply voltage with the negative supply pin at ground
potential. The analog signal range will include ground.
LOGIC INPUT
..%
For complete single supply operation information, refer to
application note, AN-32.
13-56
1/86, Rev. A
-------l~ Mux·oa/MUX·24 a·CHANNEL/DUAL 4-CHANNEL JFET ANALOG MULTIPLEXERS
SIMPLIFIED MUX-08 SCHEMATIC
v'o---__~~~~~~--_+--~--------~------------_.
DRAIN
--i--4>-OOUTPUT
IVol
I
I
I
DECODING
MATRIX
r----+--+------~-----+-----
J
Be.
FOR MUX - 24 SWITCH PAIRS S, - Ss. 82 84 - Sa ARE TURNED ON BY
A REPROGRAMMED DECODING MATRIX AND ~ IS NO LONGER USED
THE COMMON ANALOG BUS IS SPLIT IN HALF TO PROVIDE lORAIN B) OUTPUT
The simplified MUX-oS/MUX-24 schematic shows that logic
trip points are determined by two forward diode drops. An
Internal clamping diode between V- and ground prevents
excessive current flow between V+ and ground in the event
that V- becomes open circuit. The decoding matrix is
accomplished by a programmed diode array. The switch cell
consists of P channel JFET's with appropriate blocking
diodes which ruggedizes the circuit's overvoltage and supply
loss characteristics.
CMRR TEST CIRCUIT
Vsup =±1SV
AO= A,=OV
EN" +5V
PIFFERENTIAL MULTIPLEXERS
Xl000
GAIN
One characteristic unique to differential multiplexers
(MUX-24) is the ability to reject common-mode signals from
becoming differential error signals. Common-mode rejection
is a parameter which defines the amount of rejection in terms
of dB. The MUX-24 exhibits a 106dB at 60Hz and 101dB at
400Hz of CMRR using the test circuit of Figure 6.
CONFIGURATION
Figure 6
13-57
CMRR = 20 log
(VO
)
1000XVj
1/86, Rev. A
-------t1fMD
Mux-oa/MUX-24 a-CHANNEL/DUAL 4-CHANNEL JFET ANALOG MULTIPLEXERS
TYPICAL PERFORMANCE CHARACTERISTICS
OVERVOLTAGE V-I
CHARACTERISTIC
OVERVOLTAGE V-I
CHARACTERISTIC
30
30
TA-25°C
DUAL·8UPPL Y
VN "+5V
VE .. -15V FOR VA>O
Ve -t1aV FOR VA <0
I
I
J
-10
-40
-20
SINGLE-SUPPL Y
fA'" 26°C
OPERATION
Vs'" ±1SV
20
POWER-LOSS V-I
CHARACTERISTIC
30
-
20
TA" 2S G C
vs(+) .. OV (GROUND)
VN'"OV
Ve--1OV
OPERATION
Vs(+) <= 1SV
VsI-J '" OV (GROUND)
VN"'t5V
VE" -10V
20
~ r--
f.-
/
20
-10
-40
40
-20
I
20
VAIVOLTSJ
40
-10
-40
-20
0
--
20
40
VAIVOlTSI
VAIVOLTSI
OVERVOLTAGEIPOWER-LOSS MEASUREMENT TEST CIRCUIT
VI+I .. +16V
-'F
VI+I
.. (S4AI
0----1 NC(OBI
MUX·08
A2INe) (MUX-24)
+60V
o----1~--;Al
SI(~~71-
_ _ _--,
AO
lMn
V(-J· -15V
( I DENOTES MUX·24
13-58
·S1A-S3A
S1B-S48
1/86, Rev. A
MUX-16/MUX-28
16-CHANNEL/DUAL 8-CHANNEL
JFET ANALOG MULTIPLEXERS (OVERVOLTAGE PROTECTED)
Precision MOllolithics Inc.
FEATURES
GENERAL DESCRIPTION
• JFET Switches Rather Than CMOS
The MUX-16 is a monolithic 16-channel analog multiplexer
which connects a single output to 1 of the 16 analog inputs
depending upon the state of a 4-bit binary address. Disconnection of the output is provided by a logical "0" at the
ENABLE input, thereby providing a package selection
function.
•
•
•
•
•
•
•
•
•
•
•
Highly Resistant To Static Discharge Damage
No SCR Latch-up Problems
Low "ON" Resistance - 2900Typlcal
Low Leakage Current
Digital Inputs Compatible With TTL and CMOS
Break-Before-Make Action
12So C Temperature-Tested Dice Available
Overvoltage Protected
Supply Loss ProteclJon
MUX-1B Pin Compatible With DGS06, HI-SOBA, AD7S0B
MUX-28 Pin Compatible With DG507, HI-507A, AD7507
ORDERING INFORMATIONt
PACKAGE
25°C
RESISTANCE
HERMETIC DIP
2900"
2900
40004000
2900"
2900
40004000
MUX16AT
MUX16ET
MUX16BT
MUX16FT
MUX28AT
MUX28ET
MUX28BT
MUX28FT
LCC
TEMPERATURE
RANGE
MUX16BTC/883
MIL
INO
MIL
INO
MIL
INO
MIL
INO
"For devices processed in total compliance to MIL-STD-883, add /883 after
part number. Consult factory for 883 data sheet
commercial and industrial temperature range parts are available With
burn-in. For ordering information see 1986 Data Book, Section 2.
t All
The MUX-28 is a monolithic 8-channel differential analog
multiplexer configured in a double pole, 8-position (piUS
OFF) electronic switch array. A 3-bit binary input address
connects a pair of independent analog inputs from each
8-channel input section to the corresponding pair of independent analog outputs. Disconnection of both inputs is
provided by a logical "0" at the ENABLE input, thereby offering a package select function.
Fabricated with Precision Monolithics' high performance
Bipolar-JFET technology, these devices offer low, constant
"ON" resistance. Performance advantages include low leakage currents and fast settling time with low crosstalk to
satisfy a wide variety of applications. These multiplexers do
not suffer from latch-up or static discharge blow-out problems associated with similar CMOS parts. The digital inputs
are deSigned to operate from both TTL and CMOS levels
while always providing a definite break-before-make action
without the need for external pull-up resistors. For single
8-channel and dual 4-channel models, refer to the
MUX-08/MUX-24 data sheet.
FUNCTIONAL DIAGRAMS
MUX-16
EN
A3
A2
~o--t~~--~~~-r~--r-~
MUX-28
V+
EN
GND
A,
v-
~~II~~~~-r~~~--~
A2
13-59
v+
GND
v-
1/86, Rev. A
-------I~
MUX-16/MUX-28 16-CHANNEL/DUAL 8-CHANNEL JFET ANALOG MULTIPLEXERS
ABSOLUTE MAXIMUM RATINGS(Ratings apply to both DICE and packaged parts, unless otherwise noted.}
Operating Temperature Range,
Lead Temperature (Soldering, 60 sec) ••••••••••••• 300°C
MUX-16/28-AT, BT, BTC •••••••••••••
MUX-16/28-ET, FT •••••••••••••••••••
Dice Junction Temperature (Tj ) ••••••
Storage Temperature Range •••••••••••
-55°C to +125°C
Maximum Junction Temperature •••••••••••••••••• 150"C
-25° C to +85° C
V+ Supply to V- Supply ••••••••••••••••••••••••••••
-65°C to +150°C
-65"C to +150"C
36V
Logic Input Voltage •••••••••••• (V- or -4V) to V+ Supply
Analog Input Voltage •.•. V-Supply-20Vto V+Supply+20V
Power Dissipation ••••••••••••••••••••••••••••• 1000mW
Maximum Current Through Any Pin
••••••••••••••• 25mA
ELECTRICAL CHARACTERISTICS at Vs= ±15V and TA = 25°C, unless otherwise noted.
MUX-16A/E
MUX-28A/E
PARAMETER
SYMBOL
CONDITIONS
"ON" Resistance
RON
Vs c5 10V. Is c5 200~A
-----------
I
J
I
FOR MUX-28 SWITCH PAIRS 5, - 59_ 52 - 5'0S8 - 5'6 ARE TURNED ON BY
A REPROGRAMMED DECODING MATRIX AND A31S NO LONGER USED
THE COMMON ANALOG BUS IS SPLIT IN HALF TO PROVIDE (DRAIN B) OUTPUT
v-
13·68
1/86, Rev. A
MUX-88
8-CHANNEL ANALOG MULTIPLEXER FOR PCM CODECS
(OVERVOLTAGE PROTECTED)
Precision Monolithics Inc.
FEATURES
GENERAL DESCRIPTION
•
The MUX-88 is a monolithic eight-channel analog multiplexer
ideally suited to shared-channel PCM CODEC systems.
One-of-eight channels is selected upon the decoding of a3 bit
binary address. An enable input (En) disables all switches
when logic low providing package select. All logic control
inputs have true TTL input compatibility eliminating the need
for pull-up resistors necessary for some CMOS equivalent
products.
Compatible with Standards for Noise and Crosstalk In
Telephony Systems
• Pin Compatible with DGS08, HI-S08A, LF11S08
• JFET Switches Rather Than CMOS
• Low "ON" Resistance - 220.0 Typical
• Low Output Leakage Current - 100nA Max
• Digital Inputs Compatible with TTL and CMOS
• Input Overvoltage and Supply Loss Protected
Fabricated with Precision Monolithics' high performance
Sipolar-JFET technology, this device offers low "ON" resistance, low leakage, fast settling time and excellent crosstalk
isolation (98dS @ 20kHz). These characteristics make this
device suitable for meeting system level communication
requirements in shared-channel PCM CODECs.
ORDERING INFORMATIONt
RON
MODEL
TEMP RANGE
400.0
520.0
MUX-88EQ
MUX-88FQ
INO
INO
tAil commercial and mdustnal temperature range parts are available with
burn-in. For ordenng information see 1986 Data Book, Section 2
Additional ruggedization results from built-in overvoltage,
supply loss, and latch-up free circuit characteristics.
PIN CONNECTIONS
FUNCTIONAL DIAGRAM
ENABLE
A2
AO
A1
TOP VIEW
16-PIN HERMETIC DUAL-IN-LiNE
(Q-Sufflx)
v+
GND
TRUTH TABLE
v-
"ON"
DRAIN
58
57
56
S5
54
53
52
51
13-69
EN
CHANNEL
X
L
NONE
L
H
L
H
H
2
H
L
H
3
A2
A1
AO
X
X
L
L
L
L
L
H
H
H
4
H
L
L
H
5
H
L
H
H
6
H
H
L
H
7
H
H
H
H
8
1/86, Rev. A
II
------------;/fMD
Mux-aa a-CHANNEL ANALOG MULTIPLEXER FOR PCM CODECS
ABSOLUTE MAXIMUM RATINGS (TA = 2SoC, unless otherwise noted)
Operating Temperature Range,
MUX-88EQ, FQ ....................... -2So C to +8So C
Storage Temperature Range. . . . . . . . . .. -6So C to + 1S0° C
Power Dissipation .............................. SOOmW
Derate above 100°C ........................ 10mW/oC
Lead Temperature (Soldering, 60 sec) ............. 300° C
V+ Supply to V- Supply. . . . . . . . . . . . . . . . . . . . . .. . . . .. 36V
V+ Supply to Ground ............................... 18V
Logic Input Voltage (Note S) ........... (V- or -4V) to V+
Analog Input Voltage .... V- Supply-20V to V+ Supply +20V
Maximum Current Through Any Pin ............... 2SmA
ELECTRICAL CHARACTERISTICS for V+ = -1SV and -2soC:5 TA:5 8SoC, unless otherwise noted.
MUX-88E
PARAMETER
SYMBOL
CONDITIONS
"ON" Aesistance
Vs = OV. Is = 200~A
t.AON With Applied Voltage
-10V:5 Vs:5 10V, Is =
MIN
TYP
MUX-88F
MAX
200~A
1.5
RON Match
Vs = OV, IS = 200~A
'SIOFF)
Vs= 10V, Vo= -10V, (Note 1)
10
Vs= 10V, Vo = -10V, (Note 1)
1010FF)
1010N)+ I SION ) Vo= 10V, (Note 1)
Digital "1" Input Voltage
V,NH
Digital "0" Input Voltage
MAX
520
4.5
RON Match Between SWitches
Drain Current (SWitch "OFF")
TYP
400
Source Current (Switch "OFF")
Leakage Current (Switch "ON")
MIN
25
UNITS
il
%
30
il
10
nA
100
100
nA
100
100
nA
0.8
0.8
V
20
20
~A
20
20
~A
15
15
mA
(Note 5)
V
(Note 5)
Digital Input Current
Digital "0" Enable Current
I)NLIEN)
Positive Supply Current
1+
All Digital Inputs Logic "0"
Negative Supply Current
1-
All Digital Inputs Logic "0"
Switching Time
trAAN
Figure 1, (Note 2)
1.8
Output Settling Time
ts
10V Step 0.10%
10V Step 0.05%
10V Step 0.02%
1.3
1.5
2.3
mA
21
2.2
2.5
~s
1.7
1.9
2.5
~s
Break-Belore-Make Delay
t OPEN
0.8
1.0
~s
Enable Delay "ON"
tONIEN)
1.0
1.2
~s
Enable Delay "OFF"
tOFFIEN)
0.2
0.2
~s
"OFF" Isolation
ISO OFF
88
88
dB
Crosstalk
dB
(Note 4)
CT
(Note 3)
98
98
Source Capacitance
CSIOFF)
Switch "OFF", Vs = OV, Vo = OV
2.5
2.5
pF
Drain Capacitance
COIOFF)
Switch "OFF", Vs= OV, Vo= OV
7
7
pF
Input to Output Capacitance
COSIOFF)
(Note 4)
0.3
0.3
pF
NOTES:
1. Condltions applied to leakage tests insure worst case leakages. Exceeding l1V on the analog input may cause an "OFF" channel to turn "ON"
2. Sample tested. The measurement conditions of Figure 1 Insure worst case
tranSition time.
3. Crosstalk is measured by driving channel 8 with channel 4 ON.
A L = lMil, C L = 1OpF, Vs = 5V AMS, I = 20kHz. (See Figure 2)
4. OFF Isolation is measured by driving channel 8 With ALL channels OFF
AL = 1kil, C L = 10pF, Vs = 5V AMS, I = 20kHz Cos is computed Irom the
OFF isolation measurement.
Guaranteed by RON and leakage current testing. For normal operatIon
maximum analog signal voltages should be restricted to less than
(V+) -4V.
DICE
For applicable DICE ,"Iormatlon see MUX-08/MUX-24 data sheet
13-70
1/86, Rev. A
----------I~ Mux-aa a-CHANNEL ANALOG MULTIPLEXER FOR PCM COOECS
TYPICAL PERFORMANCE CHARACTERISTICS
SWITCH LEAKAGE CURRENTS
VB ANALOG INPUT VOLTAGE
SWITCH LEAKAGE CURRENTS
vs TEMPERATURE
'0
'00
V+ - +15V
-15V
v+
+15V
"
1
TA
vs
+10V
'0
v- = -15V
v- - -1SV
v-
1
+2SOC
'0
i!!
a:
"'
'S(oFF)
""'"
,I
:t
-5
'O'ONI~
'0
1
'5
U
>-
~
I-'
i--' .....
.....
cO(OFF)
....
0.'
~
'S(OFFI
V
0.01
-55
-25
25
50
is(Oi F1
'OIONI-
15
100
125
-'2 -10 -8 -6 -4 -2
TEMPERATURE (OC)
VA - ANALOG INPUT VOLTAGE (VOLTS)
LARGE-SIGNAL SWITCHING
....
....
I I I.
~~
TA =+2SoC
-
~
1\
-10
'OIOFFI==
u
w
0001
-15
'0 ~VO"-'OV
::>
~~
0.01
1
V+ = +15V
iiia:
'D(OHI
0'
SWITCH CAPACITANCE vs
ANALOG INPUT VOLTAGE
0
2
4
6
8
10 12
VA - ANALOG INPUT VOLTAGE (VOLTS)
TRANSITION TIMES
VB TEMPERATURE
BREAK-BEFORE-MAKE SWITCHING
v+
= +-'6V
v- = -15V
20
RL
MUX-BB'=
10M!)
CL '" 10pF
J,.
w
i=
MUX-BBE=
'.5
10
05
'R L = 10Mil, C L = 10pF, v, = -10V, VB = +10V
Voltage = SV/Div, Ti me = 1~s/D'v, See
Transition Time CirCUit of Figure 1.
SMALL-SIGNAL SWITCHING
'Voltage= 500mVlDiv, Time= SOOns/DIV, See
Break-Before-Make Circuit of Figure 3.
-50
25
-25
50
75
100
125
TEMPERATURE (OC)
SMALL-SIGNAL SWITCHING
WITH FILTERING
ENABLE DELAY TIME
vs TEMPERATURE
2.5
r=:t===[=+=::;t:::;,:j===F=t=::::=::]
V+ +15V
MUX-88E
=
v- = -15V
20
RZ = lkn
MUX-88F
tON
VSl = +10V
VS2'" Vsa= OV
MUX-88F
VS 1
+2V
MUX-88E
tON
0.5
'R L = 1Mil, C L = 10pF, V, = -SOOmV,
Vss = +SOOmV Voltage = SOOmV/D,v,
Time = 1p.s/Div. See Transition CirCUit of
Figure 1
'RL = 1 Mil, C L = SOOpF, V, = -SOOmV,
VSB = SOOmV Voltage = SOOmV/Div,
Time
=
11ls/Div, See TransitIon Time
Circuit of Figure 1.
-50
-25
25
MUX-88E
MUX-88F
tOFF
tOFF
50
75
100
125
TEMPERATURE (DC)
NOTE:
'Top Waveforms: Digital Input 5V/Div
Bottom Waveforms: Multiplex Output
13-71
1/86, Rev. A
----------I~ Mux-aa a-CHANNEL ANALOG MULTIPLEXER FOR PCM CODECS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
OFF PERFORMANCE
OF CHANNEL 8
RON VB SWITCH VOLTAGE (Vso)
RON vs SWITCH CURRENT (Is)
600
600
500
S
w
""~
300
I
40
-t
"0
CROSSTALK
RL'" lMn, CL = 10pF, Vs '" +5V RMS,
RON (SWITCH 4) = 300n
20
~~Jo
~
1
r--
0
v- = -15V
w
MUX-88F
~
200
RL = lkrl, CL = 10pF, Vs = +5V RMS
~
- -
~
10k
lOOk
10M
1M
TA =+2SoC
300
r--
'
r--
D
MUX-88~
~~ll'
./
MUX-88E
I
"o
~
200
100
100
1k
400
~
MUX-88E
OFF ISOLATION
>~
v+ = +15V
500
1-'
400
~
"0
rV+- +15V
r-15V
r- Tv-=
A '" +2SoC
-BOO -600 -400 -200
0
200
400
600
-2000-1600-1200-800-400 0
800
400 800 1200 16002000
IS - SWITCH CURRENT blA)
V SD - SWITCH VOLTAGE (mV)
FREQUENCY (Hz)
TYPICAL APPLICATION
EIGHT-CHANNEL SHARED CODEC PCM ENCODER
SUCCESSIVE
APPROXIMATION
REGISTER (SAR)
DIGITAL
OUTPUTS
25k.l1
SIGN
-=
BIT
t 1=H:+:+=::::g 1
CHOAD
BITS
I
CHl
STEP
BITS
CH2
CH3
VREF
+10V
CH4
WAVEFORMS
All
CH5
1'-.- ;::~f
CH6
12 IREF
CHANNEL INPUT ANALOG
A12
CH7
20kn
CH8
MUX OUTPUT SIGNAL
-15V
SAMPLE/HOLD S/H COMMAND
+15V
~
CHANNEL SELECT
LOGIC
SAMPLE/HOLD OUTPUT
CROSSTALK IN PCM SYSTEMS
In PAM or PCM systems crosstalk specifications for components, such as multiplexers, are related to overall system
crosst~lk specifications in a complex manner. Component
specification must, of necessity, refer to the operation of
the multiplexer in a non-sampling mode of operation. When
rapid sequential sampling takes place, such as would be
the case with a typical shared-channel CODEC, crosstalk
will be caused by the off isolation properties of the
multiplexer as well as by storage elements on chip and PC
card stray capacitance. For example, the capacitance has
the effect of conferencing the channels and increasing
crosstalk. Thus, system crosstalk in a shared-channel PCM
CODEC is influenced by multiplexed characteristics as well
as PC card layout and the timing relationship between the
multiplexer and the sample-hold circuit.
13-72
1/86, Rev. A
----------I~ Mux-aa a-CHANNEL ANALOG MULTIPLEXER FOR PCM CODECS
A.C. TEST CIRCUITS
TRANSITION TIME
INPUT
DRIVE
CROSSTALK MEASUREMENT CIRCUIT
5V~
OV
+1SV
RL
eo
15V
lOMn
c L = lOpF
v+
EN
S1
A2
52·57
+10V
MUX·88
A1
S8
AO
D
-lOV
-v
GND
I
RL
-15V
-15V
C
L
-=-
Off ISOLATION MEASUREMENT CIRCUIT
BREAK-BEfORE-MAKE DELAY
INPUT 5V-L""""'I!
DRIVE ov-.T
"--
Figure 2
+15V
+15V
ALL CHANNELS ARE OFF
LOGIC
INPUT .n.
-15V
-15V
Figure 3
Figure 4
APPLICATIONS INFORMATION
These analog multiplexers employ ion-implanted JFETs in a
switch configuration designed to assure break-before-make
action. The turn-off time is much faster than the turn-on
time to guarantee this feature over the full operating
temperature and input voltage range. Because the digital
inputs only require a 2V logic "1" input level. power-consuming
pull-up resistors are not required for TTL compatibility to
insure break-before-make switching as is most often the case
with CMOS multiplexers. The digital inputs utilize PNP input
transistors where input current is maximum at the logic "0"
level and drops to that of a reverse-biased diode (about 10nA)
as the input voltage is raised above ~ 1.4V.
The "ON" resistance. RON. of the analog switches is constant
over the wide input voltage range of -15V to +11V with
VSUPPLY = ±15V. Higher input voltage is tolerable provided
that some form of current limiting is employed (such as that
of an op-amp output stage) to avoid exceeding junction
temperature and power dissipation requirements. For normal
operation. however. positive input voltages should be
restricted to 11V (or 4V less than the positive supply). This
assures that the VGsof an OFF switch remains greater than its
Vp • and prevents that channel from being falsely turned ON.
When operating with negative input voltages. the gate-tochannel diode will be turned on if the voltage drop across an
ON switch exceeds -0.6V. While this condition will cause an
error in the output. it will not damage the switch. In lab tests.
the multiplexer output load capacitor has increased to 0.011'F
in the Transition Time circuit. Figure 1. With VS 1 =-10V and
VS8 = + 10V. the logic input was driven at a 1kHz rate. The
positive-going slew rate was 0.3V1l'sec which is equivalent to
a normal loss of 3mA. The negative-going slew rate was
0.7V/l'sec which is equivalent to a "reverse" loss of 7mA.
Note that when switch 1 is first turned ON it has a drop of
-20V across its terminals. In spite of that fact. the current is
limited to approximately twice its normal loss.
13-73
1/86, Rev. A
DMX-88
8-CHANNEL ANALOG DE-MULTIPLEXER
(LOW CHARGE TRANSFER)
Precision Monolithics Inc.
FEATURES
• Low Charge Transfer - 1SpC Typ
• Compatible with Standards for Noise and Crosstalk In
Telephony Systems
• Pin Compatible with DG50S, HI-50SA, LF1250S/1350S
• JFET Switches Rather Than CMOS
• Low "ON" Resistance - 2200 Typ
• Low Output Leakage Current - 100nA Max
• Digital Inputs Compatible with TTL and CMOS
• No Pull-up Reslltors Required to Ensure
Break-Before-Make Action with TTL Inputs
ORDERING INFORMATIONt
MODEL
TEMP RANGE
4000
DMX88EQ
IND
5200
DMX88FQ
IND
channels. In addition, there is an ENABLE input which
permits turning OFF all channels. Using this function permits
selection of any given circuit in a system employing multiple
devices.
Fabricated with Precision Monolithics' high performance
Bipolar-JFET technology, this device offers low, constant
"ON" resistance. In addition the multiplexer has fast settling
times and low leakage currents necessary to satisfy the
reqUirements of an 8-channel PCM DECODER. This demultiplexer does not suffer from latch-up and is highly
resistant to static charge blow-out problems associated with
similar CMOS parts. The digital inputs are designed to
operate from both TTL and CMOS levels while always
providing a definite break-before-make action without the
need for external pull-up resistors.
PIN CONNECTIONS
tAli commercial and Industrial temperature range parts are available with
burn-In. For ordering Information .ee 1986 Data Book, Section 2.
GENERAL DESCRIPTION
16-PIN HERMETIC
DUAL-IN-LINE
(Q-Sufflx)
The DMX-88 is an 8-channel analog multiplexer optimized
for minimum charge transfer, approximately 4 times lower
than MUX-88 or MUX-OB. This is important when a Multiplexer is terminated in capacitive loads, as in shared-channel
PCM decoder systems. Typical crosstalk at 20kHz is 98dB.
MonOlithic construction makes possible this kind of performance while keeping the price reasonable. The DMX-88
makes use of digital logic to select one-of-eight output
FUNCTIONAL DIAGRAM & TRUTH TABLE
ENABLE
A2
A1
v-
00
00
~
L
NONE
L
H
Ao
X
X
H
H
2
H
L
H
3
L
H
H
H
4
H
L
L
H
H
ro
X
A1
GND
00
"ON"
CHANNEL
Az
v+
s
EN
AD
00
00
m
H
H
H
H
L
H
H
H
H
H
6
8
(INPUT)
"X" = DON'T CARE
13-74
1/86, Rev. A
-----------l~ DMx-aa a-CHANNEL ANALOG DE-MULTIPLEXER
ABSOLUTE MAXIMUM RATINGS
(TA = 25·C, unless otherwise noted.)
Operating Temperature Range,
DMX-88EQ, FQ ••••••••••••••••••••••
Storage Temperature Range •••••••••••
-25·C to +85·C
V+ Supply to V- Supply ............................ 36V
-65·C to +150·C
V+ Supply to Ground ............................... 18V
Logic Input Voltage ............ (-4V or V-) to V+ Supply
Power Dissipation •••••••••••••••••••••••••••••• 500mW
Derate About 100·C •••••••••••••••••••••••• 10mW/·C
Analog Input Voltage
Lead Temperature (Soldering, 60 sec) ••••••••••••• 300·C
ELECTRICAL CHARACTERISTICS for V+
DMX-88E
SYMBOL
CONDITIONS
ON Resistance
RON
Vs = OV, Is =
~RON
~RON
-10V S Vs S 10V, Is =
RON Match
Vs = OV, Is =
RON Match Between Switches
••••••••••••••• 25mA
= 15V, V- =-15V and -25·C:$ TA:$ 85·C, unless otherwise noted.
PARAMETER
With Applied Voltage
•••••• V- Supply -20V to V+ Supply
Maximum Current Through Any Pin
MIN
TYP
200~A
DMX-88F
MAX
MIN
TYP
400
200~A
520
1.5
200~A
25
10
-10
10.4
-15
MAX
+10
-10
UNITS
n
4.5
%
30
n
10.4
-15
V
Analog Voltage Range
VA
(Note 5)
Drain Current (Switch OFF)
1010FF)
Vs = 10V, Vo = -10V (Note 1)
10
10
nA
Source Current (Switch OFF)
ISIOFF)
Vs = 10V, Vo = -10V (Note 1)
100
100
nA
Charge Transfer
at
Rs = 0, C L = 200pF
VIN = 0 (Note 4)
25
pC
Leakage Current (Switch ON)
IDIONI+lsIONI Vo= 10V (Note 1)
100
nA
Digital "1" Input Voltage
V'NH
(Note 5)
Digital "0" Input Voltage
V'NL
(Note 5)
18
25
18
~
p.,
100
V
0.8
0.8
V
Digital "0" Input Current
I'NL
V'N = 0.7V
20
20
~A
Digital "0" Enable Current
IINL(EN)
VEN = 0.7V
20
20
~A
Positive Supply Current
1+
All Digital Inputs Logic "0"
15
15
mA
Negative Supply Current
1-
All Digital Inputs Logic "0"
5
mA
Switching Time
trRAN
Figure 3 CL = 10pF
0.8
1.5
~s
Output Settling Time
ts
10V Step 0.10%
10V Step 0.05%
10V Step 0.02%
1.3
1.5
2.3
1.7
1.9
2.5
~s
Break-Before-Make Delay
t OPEN
Enable Delay ON
tONIEN)
CL = 10pF (Figure 1)
Enable Delay OFF
tOFFIEN,
C L = 10pF (Figure 1)
OFF Isolation
ISO IOFF '
(Note 3)
88
88
dB
Crosstalk
CT
(Note 2)
98
98
dB
2.5
2.5
pF
0.3
0.3
0.8
0.2
Drain Capacitance
CD'OFF)
Switch OFF, Vs = OV, VD = OV
Source Capacitance
CSIOFF,
Switch OFF, Vs = OV, Vo = OV
Input to Output Capacitance
CDS(OFF)
(Note 3)
~s
1.2
~s
0.2
~s
pF
pF
NOTES:
1. Conditions applied to leakage tests insure worst case leakages. Exceeding 11V on the analog input may cause an OFF channel to turn ON.
2. Crosstalk is measured by driving channel 8 with channel 4 ON.
RL = 1Mn, C L = 10pF, Vs = 5V RMS. f = 20kHz. (see figure 2)
3. OFF isolation Is measured by monitoring channel 8 with ALL channels
OFF. RL =1kn, C L = 10pF, Vs=5V RMS, f=20kHz. Cos is computed from
the OFF isolation measurement. (see figure 4)
4. Guaranteed by design.
5. Guaranteed by leakage current and RON tests.
13-75
1/86, Rev. A
......
~
~
~
~
~
0
0
~
------------I1fHD DMx-aa a-CHANNEL ANALOG DE-MULTIPLEXER
TYPICAL PERFORMANCE CHARACTERISTICS
SWITCH LEAKAGE CURRENTS
vs ANALOG INPUT VOLTAGE
10
v+
V
TA
1
~
a:
a:
""
~
100
= +15V
-
15V
25"C
!
~
1.0
-
0.10
~
i
SWITCH LEAKAGE
CURRENTS vs TEMPERATURE
IS (DFF'=
"
0.01
-10
-5
-
-vo
IS (ON)
i
15
TA = 2SOC
10
-lOV
10
I
I
--
I"'""
,- ~ ~
I"'""
IS (OFF)
f.[,
....
.... ""
~
0.10
Co (OFF)
10 (OFF)
10
CSiD~
V+:: +15V
= -15V
v-
Vs - +10V
""
~
\
-15
12
~ ~+ :~f~v
a:
a:
10 (OFF)
0,001
SWITCH CAPACITANCE
vs ANALOG INPUT VOLTAGE
001
-55
/
-25
25
50
75
100
125
-12
TEMPERATURE (DC)
VA -ANALOG INPUT VOLTAGE (VOLTS)
....
IS (DNI'_
LARGE-SIGNAL
TRANSIENT RESPONSE
LARGE-SIGNAL
TRANSIENT RESPONSE
(THROUGH A CLOSED SWITCH)
(THROUGH A CLOSED SWITCH)
-4
-B
12
VA - ANALOG INPUT VOLTAGE (VOLTS)
SWITCHING
TIME vs TEMPERATURE
50
CL=I~ ~
4.0
3.0
/'
V
/
v+ = +15V
v- = -15V
RL'" lOMn
2.0
RL'" lMR, Cl -= 1000pF, VIN = ±10V
10
r--
CL'" 10pF
~
~
-25
+25
+50
+75
+100
TEMPERATURE {OCI
SMALL-SIGNAL
TRANSIENT RESPONSE
SMALL-SIGNAL
TRANSIENT RESPONSE
(THROUGH A CLOSED SWITCH)
(THROUGH A CLOSED SWITCH)
ENABLE DELAY
TIME vs TEMPERATURE
5.0
CL = 1000pF
4.0
3.0
~
TDN~ V
:/
I
V+ = +15V
v-
=>
-15V-
RL = 10Mn
I
20
I
1.0
CL = 10pF-
RL = lMr.!, C L = 1000pF, VIN = ±O.5V
TON (EN)
r--r
-26
I
+25
+50
+75
+100
TEMPERATURE (DC)
NOTE:
Upper Waveform Photos: Input Voltage on SOURCE
Lower Waveform Photos: Output Voltage on DRAIN
13-76
1/86, Rev. A
_ _ _ _ _ _ _ _ _ _ _-;~ DMX-81 I-CHANNEL ANALOG DE-MULTIPLEXER
TYPICAL PERFORMANCE CHARACTERISTICS
CHARGE INJECTION VB
ANALOG VOLTAGE
CROSSTALK AND OFF ISOLATION
PERFORMANCE OF CHANNEL 8
sl~.-"nrr~TTnTIm-","rnr-r,"nm
i:
~
o
r1" "0
40
Hr-H'joj.jjjp..HH++Hl-+t:
~
IIII
~ OOHr-H~~~H++Hl-++~~~H+~
!il
I
40 I-CR'-O'-SUSTllAUlLK-LR-'L-'-="",.UJM'-"--',C--'L-'=-L.l''"OP"-F-,'--'-tttttII
~ 20
Vs'" 5V AMS, RON (SWITCH #4) '" 30an
OFF ISOLATION RL"" lkO, CL '" 10pF,
0[0
VS=5VRMS
r::::: :::::
z
i5
~
600
I
::::::::
030
80
§
r---. ........
!;l
W20
I RS
........
10k
lOOk
1M
W
~
:1:
~
~
J
,fl::::t-
"'Kr---.
"'"
<.>
RS '"
a
r:::::
-6
-4
-2
2
~~'S
z
4
8
200
'DO
-2000
'0
-
z5"c
r./
--..-
300
",0
......
+lSV
-15V
DMX·88F
I
f--...
V+
TA "'
v- '"
400
~
is
I
-10 -8
FREQUENCY (Hz)
500
g
RS=25kn'
'0
'OM
_
~ 'O.~
:::::t--
!:OL....J..J..UJJ.w....w.J.W.iII......w..w.lllL....L.J...U.wJI
,.
RON V8 SWITCH CURRENT (Is)
50
ANALOG VOL lAGE (VOLTS)
~ r--
./'
DMX-88E -
-1200
-400 a 400
1200
IS - SWITCH CURRENT (pAl
2000
A.C. TEST CIRCUITS
ENABLE DELAY TIME
EN
INPUT
SWITCHING TIME
tON(EN). toFF(EN)
tTRAN
5V7L
INPur5V7L
OV
DRIVE
+lSV
OV
EN
AD
A'
+5V
+5V
A2
D81--+-+--o Your
'----'
CL
10pF
Figure 3
Figure 1
CROSSTALK MEASUREMENT CIRCUIT
OFF ISOLATION MEASUREMENT CIRCUIT
+15V
Figure 2
OFF ISOLATION", 20LOG ~
Vs
Figure 4
13-77
1/86, Rev. A
------------I~ DMX-88 8-CHANNEL ANALOG DE-MULTIPLEXER
TYPICAL APPLICATION
FOUR-CHANNEL SHARED CHANNEL PCM CODEC
MULTIPLEXER
DE·MUL TIPLEXER
AID
I
D/A
OAeSAMPLE/HOLD
88/89
ANALOG
ANALOG
CHANNELS
CHANNELS
IN
OUT
ENCODE
DECODE
SECTION
SECTION
CHARGE TRANSFER
TYPICAL CHARGE TRANSFER
OF DMX-88
TEST CIRCUIT
TYPICAL CHARGE TRANSFER
OF CONVENTIONAL JFET
SWITCH
+5,OV
VOUT
AL = 1M.I1
CL '" 1000pF
TOP TRACE. ADDRESS INPUT
TOP TRACE ADDRESS INPUT
BOTTOM TRACE- DRAIN OUTPUT
BOTTOM TRACE. DRAIN OUTPUT
APPLICATIONS INFORMATION
These de-multiplexers employ ion-implanted JFETs in a
switch configuration designed to assure break-before-make
action. The turn-off time is much faster than the turn-on time
to guarantee this feature over the full operating temperature
and input voltage range. Because the digital inputs only
require a 2.0V logic "1" input level, power-consuming pull-up
resistors are not required for TTL compatibility to insure
break-before-make switching as is most often the case with
CMOS devices. The digital inputs utilize PNP input transistors where input current is maximum at the logic "O"level and
drops to that of a reverse-biased diode (about 10nA) as the
input voltage is raised above'" 1.4V.
The ON resistance, RON, of the analog switches is constant
over the wide input voltage range of -15V to +11V with
VSUPPLY = ±15V. Higher input voltage is tolerable provided
that some form of current limiting is employed (such as that
of an op-amp output stage) to avoid exceeding junction
temperature and power dissipation requirements. For normal
operation, however, positive Input voltages should be
restricted to 11V (or 4V less than the positive supply). This
assures that the VGsof an OFF switch remains greater than its
Vp, and prevents that channel from being falsely turned ON.
When operating with negative input voltages, the gate-tochannel diode will be turned on if the voltage drop across an
ON switch exceeds -O.6V. While this condition will cause an
error in the output, it will not damage the switch.
CROSSTALK IN PCM SYSTEMS
In PAM or PCM systems crosstalk specifications for components, such as multiplexers or de-m ultiplexers, are related to
overall system crosstalk specifications in a complex manner.
Component specification must, of necessity, refer to the
operation of the multiplexer in a non-sampling mode of
operation. When rapid sequential sampling takes place, such
as would be the case with a typical shared-channel CO DEC,
crosstalk will be caused by the off isolation properties of the
multiplexer as well as by storage elements on chip and PC
card stray capacitance. For example, the capacitance has the
effect of conferencing the channels and increasing crosstalk.
Thus, system crosstalk in a shared-channel PCM CODEC is
influenced by multiplexer characteristics as well as PC card
layout and the timing relationship between the multiplexer
and the sample-hold circuit.
13-78
1/86, Rev. A
Table of Contents 1
Ordering Information 2
Product Assurance Program 3
Industry Cross Reference 4
Operational Amplifiers 5
Instrumentation Amplifiers 6
Voltage Followers/Buffers 7
Voltage Comparators 8
Matched Transistors 9
Voltage References 10
Digital-to-Analog Converters 11
Analog-to-Digital Converters 12
Analog Switches/Multiplexers 13
Sample-and-Hold Amplifiers 14
Special Functions 15
Communications Products 16
Package Information 17
Sales Offices, Representatives and Distributors 18
SAMPLE-AND-HOLD
AMPLIFIERS
Precision Monolithics Inc.
14-3
Introduction
14-3
Definitions
14-6
SMP-I0/SMP-ll
Low-Droop-Rate/Accurate Sampleand-Hold Amplifiers
14-15
SMP-81
Telecommunications Sample-andHold Amplifier
14-2
SAMPLE-AND-HOLD
AMPLIFIERS
Pn:CISHHl MOl1ot.thlCS
Inc
INTRODUCTION
Sample-and-hold amplifiers "sample" an analog
input signal and then "hold" the instantaneous
input value upon the command of a logic control signal. Basically the sample-and-hold is an
"analog memory" where a capacitor serves as
the storage element. Applications in which a
time varying input cannot be tolerated require
sample-and-hold circuits. A fast successiveapproximation analog-to-digital converter is
one application. Data acquisition, data distribution, analog delay and telephony require
sample-hold circuits to "freeze" the analog
signal for further signal processing.
temperature performance. "Super Beta"
transistors provides the high input-impedace
amplifier needed for low droop rate and minimal
signal loading.
The SMP-10 and SMP-11 have different droop
rate and settling hold mode times specifications.
The SMP-81 is characterized for the sampling
requirements found in telecommunications
applications.
In addition to precision sample-and-hold amplifiers, two products with related capabilities are
available. The GAP-01 general purpose analog
processor provides the user with two independently switched transconductance amplifiers, a
unity gain buffer and an uncommitted voltage
comparator. The GAP-Q1 is a non-dedicated
functional block which has a wide variety of
applications. The second device is the PKD-01
monolithic peak detector. This device performs
the peak detector function with accuracies
approaching those obtainable with high cost
hybrid modules at a cost approaching the low
cost, low performance discrete designs. Data
sheets for the GAP-01 and PKD-Q1 are located in
the SPECIAL FUNCTIONS SECTION of this
catalog.
PMI sample-and-hold amplifiers are functionally
identical to track-and-hold circuits. They
continously track input signals during the
sample mode. PMI circuits should not be
confused with AC controlled sample-and-holds.
When an AC controlled sample-and-hold is
commanded to sample, it will take a fast sample
and immediately return to the hold mode. It can
not continously track an input signal.
A sample-and-hold circuit consists of an amplifier, switch, and capacitor. Many specifications
are similar to those of switches and operational
amplifiers - bias currents, voltage gain, and
charge injection are examples. These and other
specifications pertaining uniquely to sampleand-hold circuits are defined below.
The SMP-10 and SMP-11 are precision sampleand-hold amplifiers with high accuracy, low
droop rate, and fast signal acquisition time.
These circuits contain a high impedance input
buffer, a diode bridge switch, a transconductance or "Super-Charger" circuit to enhance
'slewing and a high speed output amplifier. The
"Super-Charger" is capable of supplementing
the capacitor charging current whenever the
difference between input and output levels
exceeds a given threshold. Settling to final value
is under control of currents from the diode
bridge, thus minimizing overshoot and instability.
The inherent low offset voltage errors and low
charge injection allows the residual zero-scale
errors to be actively trimmed using PMI's
zener-zapping technology without degrading
DEFINITIONS
Acquisition Time (taq)- The minimum time forthe
output voltage to begin tracking the input voltage, to within a specified error band, after the
inception of the sample command. By convention, acquisition time is defined for sampling of
a DC level. For instance a circuit which is "holding" a 10V output signal, and operating with
zero input volts, is switched to the sample
mode. The acquisition time is then the time
required for the output to decrease to within a
±10mV (O.01%FS) band about ground potential
(see timing diagram).
Aperture Jitter (~ta) - The maximum amount of
deviation in aperture time from sample to sample. Errors resulting from aperture jitter increase
14-3
SAMPLE-AND-HOLD
AMPLIFIERS
PreciS101l MOJ)olithics Inc.
in proportion to the slew rate of the sampled
analog input signal. Also called aperture
uncertainty time.
Aperture Time (tap) - The time between the
inception of the hold command and the time the
circuit output ceases tracking the input signal
(see timing diagram).
be supplied without significant distortion. Full
power bandwidth Fp is related to slew rate SR
by the following equation:
SR
Fp = 21TEp
Using this equation Fp of 160kHz can be computed. This is applicable only for pulsed conditions. Power dissipation limits Fp to 100kHz for
C.W. operation.
Change In Hold Step (~VHS)- Actual hold
step less the hold step measured after sampling
V = O. A change in hold step has two components:
the first is a function of input voltage, the
second is a function of the rise time of the S/H
voltage. Note that rise time of S/H voltage
dV(SIH)fdt also effects ZERO-SCALE ERROR.
Gain Error - Voltage difference between input
and output voltage measured over a specified
voltage range, assuming the ideal gain is unity.
Hold Capacitor Charging Current (ICH) - The
current ICH which charges, or discharges, the
hold capacitor CH while the circuit is in the
sample mode.
Charge Transfer (Qt) - The amount of charge
transferred to the holding capacitor due to the
action of the switch. Charge is transferred to CH
when the circuit is switched to the hold mode.
Charge transfer causes a change in output
voltage VZS as defined by the equation:
Hold Mode Settling Time (tHm) - The time for
all output transients to settle within a specified
error band. Measured from the inception of the
hold command (see timing diagram).
V (V) = at(pC)
ZS
CH(pF)
Note that for at = 5pC and CH = 5000pF offset
error = 1mY. The SMP-10/11/81 has been factory
nulled for CH = 5000pF. For other values of CH
the zero-scale shift can be calculated from the
equation:
~VZs(V)
=
Hold Step (VHS) - Magnitude of step caused in
the output voltage by switching the circuit from
sample mode to hold mode. Hold step is sometimes called pedestal error, or sample to hold
offset (see timing diagram).
Input Bias Current (IB) - Input terminal current
with input voltage held at zero volts.
at
CH -1mV
Input Resistance (RIN) - AC impedance
measured as a ratio of input voltage VIN to input
current liN.
Droop rate dVCH/dt is
the rate of change of output voltage while the
circuit is in the hold mode. dVCH/dt is a direct
function of droop current lOR:
Droop Rate (dVCH/dt) -
Leakage (Droop) Current (lOR) - The current
which flows out of holding capacitor CH while
the circuit is operating in the hold mode. In general
droop current lOR is defined positive when its
direction is into the CH pin. This parameter is
sometimes called drift current.
dVCH _ lOR
CH
---cit -
where dVcwdt is expressed in p.V/ms, lOR in
nanoamperes and CH in microfarads (see timing
diagram).
Feedthrough Attenuation Ratio (FA) - Feedthrough attenuation is a measurement of the
off-isolation of the analog switch (specified in
dB). The parameter is a direct function of feedthrough capacitance.
Linearity Error - The maximum deviation from
an ideal straight line drawn between the output
voltage when VIN = 0 and the output voltage
when VIN = maximum analog voltage, expressed
as a percentage of the maximum analog voltage.
Output Resistance (Ro) - An AC change in output voltage as a result of an AC change in load
current.
Full Power Bandwidth (Fp) - The maximum
frequency at which rated output voltage Ep can
14-4
SAMPLE-AND-HOLD
AMPLIFIERS
Precision Monolithics Inc.
Power Supply Rejection Ratio (PSRR) - The
change in output voltage for a change in power
supply voltage when the circuit is in the sample
mode. The best power supply rejection ratio
PSRR is obtained with the power supply voltage
changing at a very low rate (DC). For essentially
DC conditions PSRR for the hold mode of operation is essentially the same as the PSRR for the
sample mode. PSRR is degraded as the frequency of the disturbance increases.
Sample Hold Current Ratio (lCWIDR) - The
ratio of the peak charging current available to
the droop current.
Signal Transfer Nonlinearity - The total input
to output, hold mode error caused by gain nonlinearity, feedthrough, thermal transient, charge
transfer and droop rate. These error terms cannot be corrected by offset and gain adjustments.
Slew Rate (SR) - The maximum possible rate
of change of the output voltage when supplying
the rated output. For a sample-and-hold circuit,
slew rate must be defined with a specified value
of holding capacitor CH. Slew rate can either be
measured by operating the circuit in the sample
mode and applying a step function to the input,
or by applying an input voltage which differs
from the output voltage, with the circuit in the
hold mode, then switching to the sample mode
and observing the rate of change of the output
voltage.
Total Error - The algebraic sum of the following
factors:
i. ZERO-SCALE ERROR
ii. Gain Error
iii. Hold Step Change versus
iv. Hold Step Change versus VIN
Voltage Gain (Av) - The ratio of the output voltage
to the input voltage with the circuit operating in the
sample mode.
Zero-Scale Error (Vzs)- The magnitude of the output voltage when the circuit is switched from sample to hold mode while holding the input at zero
volts. ZERO-SCALE ERROR Vzs is the algebraic
sum of the offset voltage and the charge transfer
hold step voltage (see timing diagram). Vzs can
be adjusted to zero (see ZERO-SCALE ERROR
null adjustment).
TIMING DIAGRAM
HOLD MODE
LOGIC"l"
VSlH
LOGIC "0"
SAMPLE MODE
APERTURE TIME
10
VOLTAGE
(VOLTS)
ACQUISITION
TIME
HOLD MODE
SETTLING
TIME
ZERO-SCALE ERROR
DETAIL
~"""'
_ _"":"_ _ _ ANALOG OUTPUT
I
,
Ov___ _ _ _ _
OFFSET ERROR
Vos......;.....;..;.~~-I-J
dV~~/H)
ZERO-SCALE
ERROR (Vzs)
_ _ _ _ _ _ _ _ _ -ANALOG INPUT
--t-
t
14·5
-------------
SMP.I0/SMP.ll
LOW-DROOP-RATE/ACCURATE
SAMPLE-AND-HOLD AMPLIFIERS
PrCC1SIOll l"lon()l~thics
Inc
FEATURES,
GENERAL DESCRIPTION
SMP·10
• Low Droop Rate ............................. 5.0"Vlml
• Low Signal Transfer Nonlinearity ...•.•..•...... 0.005%
• High Sample/Hold Current Ratio ...•......•....• 2x10'
SMp·11
• Low Droop Rate over Tempereture ..... , ...... 120"Vlml
• High Sample/Hold Current Ratio •...•.......... 1.7x108
The SMP-10/11 are precision sample-and-hold amplifiers that
provide the high accuracy, the low droop rate and the fast
acquisition time required in data acquisition and signal processing systems. Both devices are essentially noninverting
unity gain circuits consisting of two very high input impedance buffer amplifiers connected together by a diode bridge
switch.
BOTH SMP·10 AND SMp·11
• FaIt Acquilition Time, 10Y Step to 0.1% ........... 3.5,,1
• High Slew Rate.. .. .. .. .. .. . .. . .. .. .. . .. ... .... 10Vl,,1
• Low Aperture Time .............................. 50nl
• TrImmed for Minimum Zero-Scale Error ......... 0.45mY
• Feedthrough Attenuation Ratio ................... 96dB
• Low Power DI88lpatlon .........•.............. 160mW
• DTL, TTL & CMOS Compatible LogiC Input
• HA-2420, HA-2425, SHM·IC·1, and AD583 Socket
Compatible
HIGH ACCURACY AND LOW DROOP RATE
The high input impedance and the low droop rates of the
SMP-10 and the SMP-11 are achieved by using bipolar Darlington circuits and an ion implant process that creates
"super beta" transistors.
The output buffer's input stage converts to a super beta
Darlington configuration during the hold mode, which results
in a very low droop rate with no penalty in acquisition time.
The use of bipolar transistors achieves a low change in droop
rate over the operating temperature range.
ORDERING INFORMATIONt
FAST ACQUISITION
A unique super charger provides up to SOmA of charging
current to the hold capacitor, which results in smooth, fast
charging with minimum noise. As the hold capacitor voltage
nears its final value, the low current diode bridge controls the
final settling time. This unique combination of linear functions in a monolithic circuit enables the system designer to
achieve superior performance.
TA=+25°C
PACKAGE
VZI
(mV)
DROOP
RATE IN
p.Vlma
14-PIN DIP
HERMETIC
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
7.0
20
50
20
50
200
500
200
500
900
SMP10AY'
SMP10BY'
SMP10EY
SMP10FY
SMP11AY'
SMP11BY'
SMP11EY
SMP11FY
SMP11GY
LCC
SMP11BRC/883
OPERATING
TEMPERATURE
RANGE
MIL
MIL
COM
COM
MIL
MIL
COM
COM
COM
FUNCTIONAL DIAGRAM
• For devices processed In total compliance to MIL-STD-883. add 1883 after
part number. Consult factory for 883 data sheet.
tAli commerCial and industrial temperature range parts are available with
burn-in For ordering Information see 1986 Data Book, Section 2
(VLC)
LOGIC
CONTROL
PIN CONNECTIONS
OUTPUT
INPUT ,,"",--",......,
3
14·PIN DIP (Y·Sufflx)
• PinS 1 and 8 are not Internally
connected, In unity gain applications,
SMP-10 and SMP-11 can replace
HA-2425, HA-2420, SHM-IC-1 and
AD-583 directly.
4
NULL
.. SamplelHold Control
5tH
MODE
1
Sample
Hold
o
SMP-11BRC/883
LCCPACKAGE
(RC-Sufflx)
VLC = OV for TTL Input compatibility.
Manufactured under the following patents: 4.105,215 and 4.142,117.
14-6
1/86, Rev. A
--------llEMD
SMP-10/SMP-11 LOW-DROOP-RATE/ACCURATE SAMPLE-AND-HOLD AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS (Note)
Supply Voltage (V+ minus V-) ...................... 36V
Power Dissipation .............................. 500mW
Derate Above 100· C .......................... 10mW/· C
Input Voltage. . . . . . . . . . . . . . . . . .. Equal to Supply Voltage
Logic and Logic Reference
Voltage ...................... Equal to Supply Voltage
Output Short-Circuit Duration ................. Indefinite
Hold Capacitor Short-Ci rcuit Duration ............ 60 sec
Storage Temperature Range. . . . . . . . . .. -65· C to + 150· C
Lead Temperature (Soldering, 60 sec) ............. 300·C
Operating Temperature Range
SMP-10AY, BY ...................... -55·C to +125·C
SMP-10EY, FY .......................... 0·Cto+70·C
SMP-11AY, BY, BRC .................. -55·C to +125·C
SMP-11 EY, FY, GY ........................ O·C to 70·C
DICE Junction Temperature (TI ) ....•.. -65·C to +150·C
NOTE: Absolute ratmgs apply to both DICE and packaged parts. unless
otherwise noted.
ELECTRICAL CHARACTERISTICS at Vs = ±15V, CH = 0.005/,F, VLC connected to ground, TA = 25·C, unless otherwise
noted.
SMP-10AlE
SMP-11A1E
PARAMETER
Zero~Scale
Error
(Hold Mode)
SYMBOL CONDITIONS
Vzs
MIN
V'N=O
VS/H = 35V. (Note 3)
Input Bias Current
Droop Rate
TYP
MAX
0.45
35
Leakage
(Droop) Current
Dev,ce Warmed Up SMP-l0
(See Note 2)
SMP-ll
dVm/dt
Input Resistance
MIN
MAX
TYP
MAX
UNITS
1.5
0.60
3.0
1.5
70
mV
65
55
20
90
90
160
nA
30
MIN
0.25
250
20
200
5
60
SMP-11G
TYP
0.10
1.00
Device Warmed Up SMP-l0
(See Note 2)
SMP-ll
See Note 1
SMP-10B/F
SMP-11B/F
5
70
14
4.5
50
500
BO
900
nA
~V/ms
25
20
G!1
0.99963 0.99983
0.99953 0.99978
0.99940 099975
V/v
3.5
35
3.5
~s
5.0
5.0
5.0
~s
50
50
50
ns
1.5
1.5
15
5
5
10
10
50
50
Sample Mode
Voltage Gai n
Av
V'N = ±10V, RL = 5k!1
or V'N = ±5V, RL = 2.5k!1
10V step to withm 10mV
of final value (0.1%)
10V step to withm 1.0mV
offinal value (0.01%)
Acquisition Time
Aperture Time
Hold Mode
Settling T,me
Settling to lmV
of final value.
Charge Transfer
Ot
Slew Rate
SR
SMP-l0
SMP-ll
V'N= ±10V
RL = 2.5k!1
10
Hold Capacitor
Charging Current
30
Sample/Hold
Current Ratio
SMP-l0
SMP-ll
Feedthrough
Attenuation Ratio
Input = 20Vp_p 1kHz
RL = 5k!1, (Note 1)
Full Power
Bandwidth
±10Vp-p
(Dissipation Limited)
Input Voltage Range
and/or Output
Voltage Swing
RL = 2.5k!1
Output Resistance
Power Supply
RejectIOn RatiO
Power
Consumption (DC)
3Xl0.
-
20
50
2Xl0.
8Xl0' 8Xl0.
- 1.5Xl0·
17Xl0·
86
80
96
100
±11
±10.5
±115
0.15
RO
PSRR
Sample Mode
Vs= ±9V to±18V
PD
Sample Mode V'N = 0
82
77
180
160
3
14-7
mA
mA/mA
1.5Xl0·
90
90
dB
100
100
kHz
±11.5
V
±115
±10.5
015
92
NOTES:
1 Guaranteed by deSign.
2. These measurements are made with the deVices warmed-up Itean be seen
-
pC
92
170
72
210
0.15
!1
92
dB
160
240
mW
that there is a selection trade off between droop rate and hold mode
settling time.
Measured 500J,ls after hold command.
1/86, Rev. A
-------I~ SMP-10ISMP-11 LOW-DROOP-RATE/ACCURATE SAMPLE-AND-HOLD AMPLIFIERS
ELECTRICAL CHARACTERISTICS -
SMP-10 ONLY at
Vs
= ±15V, C H = O.005,..F, VLC = OV, TA = 25·C, device fUlly
warmed-up, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
SMP-10AlE
MIN
TYP
MAX
SMP-10B/F
MIN
TYP
MAX
Hold Step
VHS
V,N-O
-1.0
-3.0
linearity Error
NL
Y,N - ±10V, Rl - 5kO
Output NOise
EN(RMS)
Wideband NOise 100Hz
to 100kHz Sample Mode
ELECTRICAL CHARACTERISTICS at
Vs
+1.5
+4.0
+1.5
UNITS
+6.0
mV
0005
0.007
%ofl0V
40
50
jlV RMS
= ±15V, CH = O.005,..F, VLC connected to ground, O·C S; TA S; +70·C, unless
otherwise noted.
SMP-10E
SMP-11E
TYP
MAX
MIN
SMP-10F
SMP-11F
MIN
TYP
MAX
075
20
1.0
4.0
2.7
10
mV
50
90
BO
140
120
250
nA
0.7
5
140
1000
PARAMETER
SYMBOL CONDITIONS
Zero-Scale Error
Vzs
Y,N - 0, VSJH - 3.5V. (Note 3)
Input Bias Current
Ie
V,N-OV
lOR
Device Warmed Up SMP-l0
(See Note 2)
SMP-ll
0.05
0.5
0.25
1.B
0.080
0.6
0.65
2.B
Droop Rate
dVCH/dt
Device Warmed Up SMP-l0
(See Note 2)
SMP-"
10
100
50
360
16
120
130
Voltage Gai n
Av
Sample Mode
V,N -±10V, Rl -5kO
or Y,N - ±5V. Rl - 2.5kO
Power Supply
Relectlon Rallo
PSRR
Sample Mode
Vs -±9Vto±1BV
I lc
VlC-OV
ISJH
Sample Mode
VSJH -0.6V
Hold Mode
VSJH -50V
Leakage
(Droop) Current
Logic Control
Input Current
Logic Input
Differential Logic
Threshold
VTH
o 99955 0 99976
BO
75
SMP-11G
TYP
MAX
099930 0.99970
BO
70
UNITS
nA
jlV/ms
VIV
90
dB
-I
-2
-I
-3
-I
-4
jlA
-5
-15
-5
-15
-5
-15
jlA
0.2
0.2
O.B
560
o 99950 0 99972
90
MIN
1.3
2.0
O.B
1.3
02
2.0
O.B
1.3
nA
20
V
NOTES:
I
Guaranteed by design.
2. These measurements are made with the devices warmed-up It can be seen
that there is a selecllon trade off between droop rate and hold mode
settling time
3. Measured 500jls after hold command
14-8
1/86, Rev. A
_ _ _ _ _--j~ SMP-10/SMP-11 LOW-DROOP-RATE/ACCURATE SAMPLE-AND-HOLD AMPLIFIERS
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, CH = O.005/LF, VLC connected to ground, -55°C :'0 TA:'O + 125°C, unless
otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Zero-Scale Error
Vzs
V,N = O. VS/H = 3.5V. (Note 3)
Input Bias Current
Ie
V,N=OV
lOR
TA =-55'C
TA =+125'C
TA = Full Range
(See Note 2)
Leakage (Droop) CUrrent
Droop Rate
dVCH/dt
TA =-55'C
TA =+125'C
TA = Full Range
(See Note 2)
1.25
3.0
1.60
55
mV
90
180
160
260
nA
0.050
6
0.50
7.5
0.080
8
1.22
10
7.5
8
10
SMP-11
SMP-10
10
1200
100
1500
16
1600
250
2000
SMP-11
1200
1500
1600
2000
Av
Sample Mode
V ,N = ±10V. RL = 5kU
or V,N = ±5V. RL = 2.5kU
Power Supply
Rejection Ratio
PSRR
Sample Mode
Vs =±9Vto±18V
Logic Control Input Current
I LC
VLC = OV
ISIH
Sample Mode
VSlH = 0.6V
Hold Mode
VSlH = 5.0V
Differential Logic
Threshold
SMP-10B
SMP-11B
MIN
TYP
MAX
SMP-10
Voltage Gain
Logic Input
SMP-10A
SMP-11A
MIN
TYP
MAX
0.99950 0.99972
78
0.99940 0.99968
88
72
UNITS
nA
!,Vlms
VIV
90
dB
-1
-3
-1
-5
!,A
-5
-15
-5
-15
!,A
0.2
nA
0.2
~
VTH
0.6
1.3
20
0.6
1.3
2.0
V
3
~
p..,
~
NOTES:
1.
2.
~
~
......,
Guaranteed by design
These measurements are made with the devices warmed-up. It can be seen
that there is a selection trade off between droop rate and hold mode
settling time
Measured 500!,s after hold command.
Cl
.....:I
0
:r:
0
Cl
~
~
p..,
~
II
14-9
1/86, Rev. A
--------I1E!1D
SMP-10/SMP-11 LOW-DROOP-RATE/ACCURATE SAMPLE-AND-HOLD AMPLIFIERS
DICE CHARACTERISTICS
SMP-10
SMP-11
2. INPUT
3. NULL
4. NULL
5. NEGATIVE SUPPLY
(SUBSTRATE)
7. OUTPUT
9. POSITIVE SUPPLY
11. HOLO CAPACITOR (CH)
13. LOGIC THRESHOLO
CONTROL (VLe)
14. SAMPLE/HOLD
COMMAND
2.
3.
4.
5.
INPUT
NULL
NULL
NEGATIVE SUPPLY
(SUBSTRATE)
7. OUTPUT
9. POSITIVE SUPPLY
11. HOLD CAPACITOR (CH)
13. LOGIC THRESHOLD
CONTROL (VLe)
14. SAMPLE/HOLD
COMMAND
For additional DICE
Information refer 10 1986
Dala Book, Seellon 2.
DIE SIZE 0.081 X 0.086 Inch, 6966 Iq. mill
(2.057 X 2.184 mm, 4.772 Iq. mm)
WAFER TEST LIMITS at Vs = ±15V, CH = O.005/LF, VLC connected to ground,
PARAMETER
SYMBOL
CONDITIONS
Zero-Scale Error
Vzs
V,N=O, VslH =3.5V
Hold Mode, (Note 3)
Input Bias Current
Ie
V,N = OV
Leakage (Droop) Current
lOR
SMP-10
Device Warmed-Up SMP-11
Droop Rate
dVeH/dt
.
SMP-10
Device Warmed-Up SMP-11
Voltage Gain
Av
Sample Mode
V,N =±101/
orV ,N =±5V
Hold Capacitor
Charging Current
leH
Y,N - Vour " ±3V
Input Voltage Range and/or
Output Voltage Swing
Power Supply
Rejection Ratio
Sample Mode
Vs =±9Vto±18V
Power Consumption
Po
Sample Mode Y,N = 0
Logic Control Input Current
ILe
VLe = OV
ISJH
Sample Mode
Vs/H =0.6V
Hold Mode
VSIH = 5V
Differential Logic
Threshold
VrH
= 25°C, unless otherwise noted.
SMP-10N
SMP-11N
SMP-10G
SMP-11G
LIMIT
LIMIT
UNITS
1.5
3.0
mVMAX
60
90
nAMAX
0.10
0.25
2.5
nAMAX
20
200
50
500
poV/ms MAX
0.99963
0.99953
V/V MIN
30
20
mAMIN
±11
±10.5
VMIN
82
77
dBMIN
180
210
mWMAX
-2
-3
poAMAX
-15
-15
poAMAX
0
nAMAX
2.0
0.8
V MAX
VMIN
RL = 2.5kil
PSRR
Logic Input
TA
2.0
0.8
VLe=O
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs
= ±15V,
CH
= O.005/LF,
VLC connected to ground,
TA
= 25°C,
unless
otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Acquisition Time
taq
10V step to 0.1% of final value
Aperture Time
tap
Charge Transfer
a,
Y,N = 0, VS/H = 3.5V
Slew Rate
SR
Y,N = ± 10V, RL = 2.5kil
14-10
SMP-10N
SMP-11N
SMP-10G
SMP-11G
TYPICAL
TYPICAL
3.5
3.5
pos
50
50
ns
5
pC
10
10
V/p.S
UNITS
1/86, Rev. A
--------I~ SMP-10/SMP-11
LOW-DROOP-RATE/ACCURATE SAMPLE-AND-HOLD AMPLIFIERS
TYPICAL PERFORMANCE CHARACTERISTICS
CHANGE IN HOLD STEP
AMPLITUDE CHANGE IN
HOLD STEP va
INPUT VOLTAGE
vaS/H~
dt
-10
I'
-10
~t.VOUT
ill
In
-
30 (mV)
dV!dt (V/jJ.s)
our "'"
;;
E
~
~
w
"
Ii"
w
START WITH
IN
0
40
NEGATIVE SUPPLY
-1
- 0 VOLTS (30jJ.V)
::>
AT l00V!ps
::; -2
~
IIIII
(+lSV +lV SIN wT)
Il~t;iWIUrlr ~
Q
>-
C H - 0OO5MF
1.0
POSITIVE SUPPLY
z
-0 1
-00 1
REJECTION RATIO = 84dB
60
"~
,
111111
111111111 111111111 11111111 III;~
TYPICAL 0 C POSITIVE POWER SUPPLY
11111111 11111
90 "
3.0
dV!dt
\ 1~~lpICAL til~ NEG~~:~E pb~MM SUPPLY
REJECTION RATIO = 86dB
~
80
w
',"
01
'2
In
9
!E<1
100
'3
Ll,V
~
HOLD MODE
POWER SUPPLY REJECTION
20
" -3
II
10
-15
100
VIN'OOVHo~lgl~dDIEIIIIIII III
NORMALIZED TO
OVOLTSV 1N @25 c C
(10 MEG PARALLEL WITH CHI
-5
-10
o
.,5
.,0
.5
0
10
100
FREQUENCY (Hz)
SMP-10
DROOP RATE
va TEMPERATURE
SMP-11
DROOP RATE
va TEMPERATURE
DROOP CURRENT
VB TEMPERATURE
-1500
!
~
~ -1000
"
~
I
~
a:
g
a: -500
-:I
-55
;
V
-15
5
25
45
65
85
105
:sg
-200
Q
II kkl::t[ Ir
-35
-300
125
r-LJ
/'
100
V
V
I I
/
+111
~
;h
-(
~
lOR
ARROW INDICATES POSITIVE
lOR REGAROLESS OF CH
VOLTAGE POLARITY
-6
200
-55
-35 -15
INPUT BIAS CURRENT
vs TEMPERATURE
25
45
65
85
105
-55 -35
125
-15
80
'\
"-
20
10V STEP TO WITHIN ±10mV
OF FINAL VALUE (0 1%)
o
-100
-50
50
TEMPERATURE
100
rei
150
o
18
16
14
12
10
CH (oF. 1nF = 1000pF)
14-11
85
105
125
-2
~
-3
-
-
~u
-4
(;
-5
g
.if)
--~
SAMPLE
e
25 de
1--125o
>-
..........
-r~
1-'--+5 o
1>G
"
65
-1
~
"'- '-.
1\
40
(
RECOMMENDED HOLD
CAPACITOR IS 5000pF
60
45
LOGIC INPUT CURRENT
12
\
25
TEMPERATURE (OC)
ACQUISITION TIME
va HOLD CAPACITOR
10
N
CH
TEMPERATURE (OC)
100
~
~MP-ll
/
-100
-
1"-1-t-
I
-400
w
~
F::
:1::=::=:::11::::::1
1 1=:::11A
1M
lOOk
INPUT VOLTAGE (VOLTS)
-2000
Q
10k
lk
8tH dV!dt LOGIC INPUT SLEW RATE (V/ps)
'I
e;
I
viLe = 0 OV (PIN 13)
-6
-7
I
I
iPIN
141 vbLTAGE
o
LOGIC INPUT VOL TAGE (VOLTS)
1/86, Rev. A
--------I!mD
SMP·10/SMP·11 LOW·DROOP·RATE/ACCURATE SAMPLE·AND·HOLD AMPLIFIERS
TYPICAL PERFORMANCE CHARACTERISTICS
POWER DISSIPATION VB
INPUT FREQUENCY = Vp SIN wT
GAIN ERROR
500
+3r-----~-----r-----r----~
;;!
RL '" 2.5kn
w ~~--~~----4----=~~~~
400
~ +1~~~~----4------t----~
i
§
;t
~
O/-----+----''''''''''!.=---t----~
I
w
~ -1r-----+-----~----~~~~
liN
V+ = 15V
v- = -15V
V LC '" GND
CH = O.OO5f,!F
TA = 2S C C
SAMPLE MODE
='0
[I
V.
5V.
J
.§
2
0
;:: 300
i5 200
a:
15
I!
-
'0
1.0Vp
~
2
:>
5
r-
~
I[
g
'00
-3~----~----~----~----~
o
14
+5
+10
1\
SOUAR~
.mi'
I~SINE
v- = -15V
V LC =GND
CH = 0 005~F
~
-5
OUTPUT SWING
WAVE
V+=15) III
~ ~/_----+_----4_--~~~~~
-10
y: III
INPUT SWING
LIMITED TO ±15V
~ ~251.
~~
iii
MAXIMUM INPUT SIGNAL
AMPLITUDE VI FREQUENCY
10k
lk
1M
lOOk
~
lOOk
10k
500k 1M
2M
INPUT VOLTAGE (VOLTS)
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
OUTPUT RESISTANCE
VI FREQUENCY
OUTPUT WIDEBAND NOISE
VB BANDWIDTH (O.1Hz TO
FREQUENCY INDICATED)
HOLD CAPACITOR
CHARGING CURRENT VI
INPUT OUTPUT VOLTAGE
:0;-
10,000
R~ '~g~D Mo8~"~ R6'~l~~L' MO'~~
10M
12
+30
10
I
1,000
+20
+'0
II
HOLD MODE/
«"
100
o
SAMPLE MODE
~
10
100
lk
10k
~f-"
lOOk
1M
10
10k
1M
lOOk
INPUT FREQUENCY (Hz)
10M
BANDWIDTH (Hz)
TOTAL HARMONIC
DISTORTION VB FREQUENCY
SAMPLE MODE
POWER SUPPLY REJECTION
-
'00
.0
POWER SUPPLY CURRENT
VI POWER SUPPLY VOLTAGE
\';N'!'~ ov
r-i'
l-
~
II- l-
(+15V +1V SIN wT)
60
LLJ
T~ = +2;'C
I1mlll'illll
pW!~ls~ml
I- f-
,....slMPL~ MolE
40
I'
NEGATIVE SUPPLY
20
o
10
FREQUENCY (Hz)
(-mIljll TIIIIII!
100
lk
10k
FREQUENCY (Hz)
14·12
lOOk
1M
1
'2
15
,.
V+ OR V- (VOLTS)
1/86, Rev. A
-------I~ SMP-10/SMP-11 LOW-DROOP-RATE/ACCURATE SAMPLE-AND-HOLD AMPLIFIERS
SMp·10/SMp·11 ACQUISITION TIMES
ACQUISITION TIME
-10VtoOV
ACQUISITION TIME
+10Vto OV
S/H{
l=v•• _.
+10V
1-
I-
. .
ACQUISITION TIME
-1.0V to OV
-
:-
· 1-
=1 - -== == · .1
:== -- ==
I
OV
v
- ACQUISITION TIME
+1.0Vto OV
v
8tH {
+1.OV
.111·
lp
ACQUISITION TIME
-100mV toOV
ACQUISITION TIME
+100mV to OV
8tH {
ror
mV
I
a
OV
I
lp
.,
+100
I
I
II
---.1
Giiiiiiiiii
v
==
I
Cv
lp
I
SAMPLE
•
APPLICATIONS INFORMATION
During the null adjustment. the amplifier should be switched
continuously between the "sample" and "hold" mode. The
error should be adjusted to read zero when the unit is in the
"hold" mode. In this way. both offset voltage errors and
charge transfer errors are adjusted to zero.
As shown in the Figure. the sample/hold mode control is
accomplished by steering the current (1 1) through Q1 or Q2.
thus providing high-speed switching and a predictable logic
threshold. For TTL and DTL interface. simply ground VLc
(Pin 13). For CMOS. HTLand HNIL interface. the appropriate
ZERO-SCALE NULL ADJUSTMENT
LOGIC CONTROL
v+
v-
14
2'
StH
VLe
>--'-----0 OUTPUT
CURRENT TO CONTROL
SAMPLE/HOLD MODES
8tH
•
r----~-~_oV+
kr!
INPUT o-----~
•
VS/H TRIP POINT = V Le + 2VSE
FOR TTL COMPATIBILITY SET V LC = OV
VLC
14-13
1/86, Rev. A
--------l~ SMP-10/SMP-11 LOW-DROOP-RATE/ACCURATE SAMPLE-AND-HOLD AMPLIFIERS
threshold voltage, allowing for 2 diode drops for 01 and VeE
of Q3, should be applied to VLC.
For proper operation, the VLC (logic control) must always be
at least 3.5V below the positive supply and 2.0V above the
negative supply.
Sample-and-hold control voltage (S/H) must always be at
least 2.BV above the negative supply.
LOCAL
ANALOG
GUARDING AND GROUNDING LAYOUT
The use of a ground plane is strongly recommended to
minimize ground path resistances. Separate analog and
digital grounds should be used, and it is advisable to keep
these two ground systems isolated until they are tied back to
the common system ground. Digital currents should not flow
back to the system ground through the analog ground path.
HOLD CAPACITOR RECOMMENDATIONS
The hold capacitor (CH) acts as a memory element and also
as a compensating capacitor for the sample-and-hold
amplifier. Forstable operation, a minimum value of 2000pF is
recommended, with no limit set for the maximum value. The
devices have been internally trimmed for C H= 5000pF. Other
values of CH will cause a zero-scale shift, which can be
calculated from the following equation:
GROUND
tN
( V) = 5 (pC) X 10 3 -1
zs m
CH (pF)
The hold capacitor should have very high insulation
resistance and low dielectric absorption. For temperatures
below 85·C, polystyrene capacitors are recommended,
while teflon capacitors are recommended for higher
temperature applications.
14-14
1/86, Rev. A
SMP-81
TELECOMMUNICATIONS
SAMPLE-AND- HOLD AMPLIFIER
Precision Monolithics Inc.
FEATURES
GENERAL DESCRIPTION
• Meets System Performance Requirements In MultiChannel CODECs
• Trimmed for Minimum Zero-Scale Error ........ 0.6mV
• Low Droop Rate Over Temperature .......... 0.1I'V/l's
• Low Aperture Time ............................. SOns
• Fast Acquisition Time 10V Step to 0.1% .......... 3.51's
• High Slew Rate ............................... 10V/l's
• High Sample-Current to Hold-Current Ratio .. 1.7 X 108
• DTL, TTL & CMOS Compatible Logic Input
• HA-2425, DATEL SHM-IC-1, and AD-583 Socket
Compatible"
• Low Power Dissipation
• Low Cost
• Feedthrough Attenuation Ratio ................. 96dB
The SMP-81 precision sample-and-hold amplifier provides
the high accuracy,low droop rate and fast acquisition ideally
required for PCM encoders. The SMP-81 is a non-inverting
unity gain circuit consisting of two buffer amplifiers of very
high input impedance connected by a diode bridge switch.
HIGH ACCURACY AND LOW DROOP RATE
The high input impedance and low droop rate of the SMP-81
are achieved by PMl's ion implant super beta process. The
. high input impedance permits high source impedance applications without degrading accuracy, and low droop rate.
Other features of the SMP-81 include high accuracy, O.6mV
of combined offset voltage and step transfer error, and very
low feedthrough. A diode bridge switch design allows minimum charge transfer step. On-chip zener-zap trimming
eliminates nulling for most applications.
ORDERING INFORMATIONt
Vzs(mV)
1.6
3.5
HERMETIC
14·PIN DIP
OPERATING
TEMPERATURE
RANGE
SMP-81EY
SMP-81FY
INO
INO
FAST ACQUISITION
A unique super charger or transconductance amplifier provides up to 50mA charging current to the hold capacitor. As a
result, smooth charging of the hold capacitor is achieved
with minimum noise. The super charger, in conjunction with
the high slewing rate input and output buffer amplifiers, permits fast acquisition operation. The adjustable logic input
threshold makes the SMP-81 compatible to all logic families.
t All
commercial and industrial temperature range parts are available with
burn-in. For ordenng Information see 1986 Data Book, Section 2.
FUNCTIONAL DIAGRAM
PIN CONNECTIONS
14-PIN HERMETIC DIP
(Y-Sufflx)
OUTPUT
"Pins 1 and 8 are not mternally connected. In unity gain
applications, the SMP-81 can replace HA-2425, SHM-IC-1
and AO·583 directly
NULL
"SAMPLE/HOLO CONTROL
HIGH=HOLO
LOW = TRACK
14-15
1/86, Rev. A
I
~ SMP-81 TELECOMMUNICATIONS SAMPLE-AND-HOLD AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V+ minus V-) •••••••••••.•••••••.•• 36V
Power Dissipation •••••••.••••.••••••.•••••••••• 500mW
Output Short-Circuit Duration ••••••••••••••••• Indefinite
Hold Capacitor Short-Circuit Duration .••••••.••••• 60sec
Derate Above 100· C •••••••••••.•.•••..•••••.• 10mW/·C
Operating Temperature Range ••••••.•••
Input Voltage ••••••••••••••.•••. Equal to Supply Voltage
Logic and Logic Control Voltage .. Equal to Supply Voltage
Storage Temperature Range. • • . . . • . . ..
ELECTRICAL CHARACTERISTICS
-25·Cto+85·C
-65· C to + 150· C
Lead Temperature (Soldering, 60 sec) ••••••••••••• 300·C
at Vs ±15V, C H = O.005/LF, VLc connected to ground, -25·C :5 TA:5 +85·C, unless
otherwise noted.
SMP-81E
PARAMETER
MIN
SMP-81F
TYP
MAX
VZS
Y,N = 0, VSlH = 3.SV (SOOl'sec
after Hold Command)
0.6
SYMBOL
CONOITIONS
Zero-Scale Error (Hold Mode)
MIN
TYP
MAX
UNITS
1.6
0.9
3.S
mV
nA
Input Bias Current
Ie
V,N = 0
10S
225
120
4S0
Leakage (Droop) Current
lOR
Device Warmed·up
0.5
10
0.5
20
nA
Droop Rate
dVCH/dt
01
20
01
40
mV/msec
Input Resistance
R'N
Voltage Gain
Av
(See Note)
Sample Mode
Y,N = ± 10V, Rl = Skn
or Y,N = ±5V, Rl = 2.Skn
0.6
2.0
0.3
14
Gn
0.99960
0.99980
0.999S5
0.99978
VIV
3.5
3.S
I'S
SO
SO
nsec
10
10
VII's
10V step to within 10mV of
final value (0.1%)
Acquisition Time
taq
Aperture Time
ta~
Charge Transfer
at
V,N = 0, VSlH = 3.5V
Slew Rate
SR
V,N =±10V, Rl =2.Skn
Hold Capacitor Charging
Current
ICH
V,N-VDUT,,±3 volts
30
SO
20
50
mA
Feedthrough Attenuation
Ratio
FA
Input -20Vp_p 1kHz, Rl = SKn
(See Note)
86
96
80
90
dB
Full Power Bandwidth
Fp
±10V~_~
100
kHz
Input Voltage Range andlor
Output Voltage Swing
100
(Dissipation Limited)
±10
Rl = 2.5kn
RD
Power Supply Rejection
Ratio
PSRR
Sample Mode Vs = ±9V
to±18V
Power Consumption (DC)
Po
Sample Mode Y,N = 0
Logic Control Input Current
I lC
Logic Input Current
ISIH
Differential Logic Threshold
VTH
tHM
±10
±".S
0.15
Output Resistance
Hold Mode Settling Time
pC
80
160
-6
Sample Mode VS/H = 0.6V
Hold Mode VSlH = 5.0V
0.8
SV step to within 1mVof
180
-1S
0.6
-45
1.3
2.0
V
0.15
n
90
dB
170
-9
-3
1.S
final value
75
90
±".5
0.8
210
-3
mW
I'A
-15
0.6
-4S
I'A
nA
1.3
2.0
V
1.5
I's
NOTE: Guaranteed by design.
DICE
For applicable DICE information, see SMP-11 Data Sheet.
14-16
1/86, Rev. A
---------t~ SMP-81 TELECOMMUNICATIONS SAMPLE-AND-HOLD AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
SMP-81 ACQUISITION TIMES
ACQUISITION TIME
+10V TO OV
ACQUISITION TIME
-10V TO OV
II
iiiiiii
V '
IVI
-
-~
:=-
I
-III --
--.
,- -II
11
I
==
/
I
I
v
V
=1P
l1
I
==
1p
V
ACQUISITION TIME
-1.0V TO OV
ACQUISITION TIME
+ 1.0V TO OV
iiii
V
II
ffi.....
V
~
:!!
::l
I=l-.
I'
~
9
0
:r:
I
IJJ
-1
0
00.
00.
1pS
1Pot:
ACQUISITION TIME
-100mV TO OV
~
ACQUISITION TIME
+ 100mV TO OV
WHII
II
~
V
II
.,
~1
I
I
~
~~
I
li:Jv
1p
HOLD
SAMPLE
14-17
~
1/86, Rev. A
-----------1~ SiViP-8, TELECOMMUNiCATiONS SAMPLE-AND-HOLD AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
AMPLITUDE CHANGE
IN HOLD STEP
vs INPUT VOLTAGE
+3r---~--~--~----r---~--~
TYPICAL 0 C. NEGATIVE POWER SUPPLY
REJECTION RATIO'" B6dB
i
+2
t--+.--+--+
~
+1
f---+~~..--+--I--+----j
~
IIIIII11
~
~
~
'pOS~TIV~'SUpp~y'"
~
~
~
"
-1
40
~« ~~H+mffi-++H~~~~~~~H+~
H-++Hltlt-++tM+Hfjjjjf---f-tI'llitt-HtH1Il1
g40~H+mffi-++U~~~~++~~H+~
-2
HOLD MODE
10MEG PARALLEL
WITH CHI
o,1:-0..u=I~OO~w..u~...u..lJJlI-!l::-LJ..lJ.l!l!l:::-l.l.lJ.IlI!'M
INPUT VOL rAGE (VOL fS)
-190
0 .•
-180
0.8
-160
0.7
-140
0.6
ffi
0.5
B
POSITIVE
DIRECTION
OA
~
0.3
~
0.2
'"
~
"t'OR
:h
0.1
-<>.1
-0.2
-30 -20
J".
~
I'
0
VS=t15
SAMPLE MODE
-20
+60
TA '"
o
+10
+80 +90
-40
-20
600
25~C
~
> +1 f-'>-2'-.2'~---+---+-----1
of----~--=~~~-+---+
w
f----~---I---=>\.2"""':-=::~
~
~ -21---+---I---=+---~
-.
~
____
~
____
+40
+60
0
-20
+80
OVOLTS:
~
+.
INPUT VOLTAGE (VOLTS)
____
500
~400 I--z
o
m
mr
~
~200
ffi
100
+40
+60
+80
MAXIMUM INPUT SIGNAL
AMPLlTUDEvsFREQUENCY
I II
I/
10
"~
/
i= 300
~
~
V,N
10V Pk
(20V Pk-Pk)
I I
5V Pk
(10V Pk-Pk)
+20
TEMPERATURE ~C)
POWER DISSIPATION
vs FREQUENCY
INPUT = Vp sin wt
o
-10
+20
TEMPERATURE (OC)
~ +2~~_--j-_ _-+_M_M_P_L_E+M_O_OE_~
-3L-____
V,N
3. 0
10
0.0
+20
+40
~ +3
=
SUPPLY CURRENT
vs TEMPERATURE _
:1
1'0...
i I
+20
0
GAIN ERROR
~
.. -
0
TEMPERATURE (Gel
-1
1--
..
l
"
CH
I
7.0
~~!
ARROW INDICATES POSITIVE
lOR REGARDLESS OF CH
VOL rAGE POLARITY
0.0
SAMPLE-MODE SUPPLY
CURRENTvsTEMPERATURE
-120 ~
I'
OF lOR
FREQUENCY (Hz)
INPUT BIAS CURRENT
vs TEMPERATURE
0.10
.s
o,.LO..J..JJ..lJJllL.~llill1LL.LllllJll::-l.LJ.I!lJll.,..LWlW
FREQUENCY (Hz)
LEAKAGE (DROOP)
CURRENTvsTEMPERATURE
'~"
'"
Y,N = O.DV
20
'<
'"z2
;;J
;;J
~1~5---~10~~~~--~---~~--+1~0---+~'5
~
j
I
F··'t+FlI,,*ffi#~;;f#IIIF~.:tiitltlll
0:
;
5
1111111
(+15V +1V SIN wTI
Ot--+-+~~~
w
111111111
TYPICAL D,C. POSITIVE POWER SUPPLY
REJECTION RATIO = 84dB
80
2 60
a:
SAMPLE-MODE
POWER SUPPLY REJECTION
HOLD-MODE
POWER SUPPLY REJECTION
jfJJ.//
2.5V
1 OV Pk
(2V Pk-Pk)
Pk-PkJ
TEST CONDITIONS
SAMPLE MODE
v+ '" 15V
V- '" -15V
CH "'OOO5j.lF
INPUT CENTERED AROUND GROUND
Pk
~0
I'V
~
z
>-
-
~
+10
lk
10k
lOOk
INPUT FREQUENCY (Hz)
14-18
1M
INPUT FREQUENCY (Hz)
1/86, Rev. A
---------I~ SMP-81 TELECOMMUNICATIONS SAMPLE-AND-HOLD AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
14.0
HOLD CAPACITOR CHARGING
CURRENTvs
INPUT OUTPUT VOLTAGE
OUTPUT WIDEBAND NOISE
VB BANDWIDTH (O.1Hz
TO FREQUENCY INDICATED)
OUTPUT RESISTANCE
VB FREQUENCY
:/
10,000
RO~~'~~lL~ '~g~~ ~ ~~I~~M~Lk'~~~E
12.0
§
10.0
~
~
+2~
'000
w
+,0
ao
II
6.0
HOLD MO OE
~
~ 4.0
5
1i'~~I~IT iii'liutfi I UI'
i.'"
IIIIII[ IJ
2.0
111111 II
o
'0
,k
'00
10k
,0
lOOk
,M
1/
P"
'00
SAMPLE MODE
II,M
.....::r.'Ok
111I11
'OM
'001<
BANDWIDTH (Hz)
INPUT FREQUENCY (Hz)
ACQUISITION TIME TEST CIRCUIT
v+
+10V---,
v-
INPUT
SMP·81
INPUT
ov _____ IL._ _ _ _ __
I
OUTPUT
+lOv
t
OUTPUTov~
2ku
I
TO SCOPE
FET
SfH
PROBe
0------'
REFERENCE OV - - - - - ; . . . . - - - -
v Le
DIGITAL
GND
I
2k!1
REFERENCE
ERROR
VOLTAGE
~'
--l
r--
ov - - - - - - - -
-t -
-
-
FINAL VALUE
ACQUISITION TIME
APPLICATIONS INFORMATION
The hold capacitor should have very high insulation
resistance and low dielectric absorption. For temperatures
below 85° C, polystyrene capacitors are recommended, while
teflon capacitors are recommended for higher temperature
applications.
HOLD CAPACITOR RECOMMENDATIONS
The hold capacitor (C H) acts as a memory element and also
as a compensati ng capacitor for the sample-and-hold amplifier. For stable operation, a minimum value of 2000pF is
recommended, with no limit set for the maximum value. The
SMP-81 is internally trimmed for CH = 5000pF. Other values
of CH will cause a zero-scale shift, which can be calculated
from the following equation:
f>.V
SMP-S1 LOGIC CONTROL
The sample/hold mode control of the SMP-81 incorporates a
unique logic input circuit, which enables direct interface to
all popular logic families and provides maximum noise
immunity. As shown in Figure 1, the mode control is
accomplished by steering the current (I l ) through 01 or 02,
thus providing high speed switching and a predictable logic
threshold. For TTL and OTL interface, simply ground VLC
(pin 13). ForCMOS, HTLand HNIL interface, the appropriate
threshold voltage, allowing for 2 diode drops for 01 and VeE
of 03, should be applied to VLC.
( V) = 5 (pC) X 10 3 -1
zs m
CH (pF)
A C H of 5000pF has been empirically determined to be an
optimum value for 8-channel shared COOEC operation.
14-19
1/86, Rev. A
---------i!EMD iiiiiji-iii TELECOMMUNICATIONS SAMPLE-AND-HOLD AMPLIFIER
SAMPLE/HOLD MODE INTERFACE CIRCUITRY
V+
v-
~------------.---~w
<>----""1
INPUT
;;>-'-------0
OUTPUT
SiH
(PIN '41
0----------'
S/H
V Le
~
0--------'
V Le
(PIN 13)
I
eH' 5OOO0F
CURRENT
TO CONTROL
SAMPLE!
Figure 2
HOLD MODES
GUARDING AND GROUNDING LAYOUT
Figure 1
For proper operation, the VLC (logic control) must always be
at least 3.5V below the positive supply and 2.0V above the
negative supply.
The use of a ground plane is strongly recommended to minimize ground path resistances. Separate analog and digital
grounds should be used, and it is advisable to keep these two
ground systems isolated until they are tied back to the
common system ground. Digital currents should not flow
back to the system ground through the analog ground path.
A guard trace surrounding the hold capacitor node pin 11,
minimizes PC board leakage problems, see Figure 3.
Sample-and-hold control voltage (S/H) must always be at
least 2.8V above the negative supply.
FROM
{s/H CONTROL
LOGIC
CONTROL DIGITAL
GROUND
ANALOG
INPUT
ZERO-SCALE ERROR NULL ADJUSTMENT
During the null adjustment, the amplifier should be switched
continuously between the "sample" and "hold" mode. The
error should be adjusted to read zero when the unit is in the
"hold" mode. In this way, both offset voltage errors and
charge transfer errors are adjusted to zero. Figure 2 shows
the recommended 10kO trim pot connected to V+ if user
needs better Vzs than 1.6mV.
LOCAL
ANALOG
GROUND
V-
Figure 3
14-20
1/86, Rev. A
---------I~ SMP-81 TELECOMMUNICATIONS SAMPLE-AND-HOLD AMPLIFIER
TYPICAL APPLICATION
EIGHT-CHANNEL SHARED CODEC PCM ENCODER
DIGITAL
OUTPUTS
2.5kn
..0.
BIT
tt=a*t=~::glCHOAD
BITS
CHI
BITS
1ST"
CH2
CH3
VREF
.'OV
123456789
CH4
OU
(':=
CH5
It+-
CH6
12 IREF
0"
CH70-+------'
20kn
CH6o-t;=:;:::~-,J
CHANNEL SELECT
-15V
+15V
WAVEFORMS
LOGIC
CHANNEL INPUT ANALOG
MUX OUTPUT SIGNAL
NULL
SAMPLE/HOLD 8/H COMMAND ~
SAMPLE/HOLD OUTPUT
14-21
1/86, Rev. A
Table of Contents 1
Ordering Information 2
Product Assurance Program 3
Industry Cross Reference 4
Operational Amplifiers 5
Instrumentation Amplifiers 6
Voltage Followers/Buffers 7
Voltage Comparators 8
Matched Transistors 9
Voltage References 10
Digital-to-Analog Converters 11
Analog-to-Digital Converters 12
Analog Switches/Multiplexers 13
Sample-and-Hold Amplifiers 14
Special Functions 15
Communications Products 16
Package Information 17
Sales Offices, Representatives and Distributors 18
SPECIAL
FUNCTIONS
Precision Monolithics Inc.
15-3
Introduction
15-3
Definitions
15-4
GAP-Ol
General-Purpose Analog Signal
Processing Subsystem
15-19
PKD-Ol
Monolithic Peak Detector
15-2
SPECIAL
FUNCTIONS
Precision Monolithics Inc.
INTRODUCTION
The PKD-01 functions as an analog peak
detector. Peak detection, peak hold and reset
are all digitally-contollable. Circuit gain is set by
external resistor ratios. The PKD-01 configures
into both positive or negative peak detector
circuits.
This section includes analog subsystems made
up of standard integrated circuit building blocks
such as op amps, comparators, analog switches,
sample/hold, and buffers.
The GAP-01 is a general-purpose analog signal
processing subsystem. This precision circuit
contains circuit building blocks used to
construct synchronous demodulators, absolute
value amplifiers, window comparators, a twochannel S/H amplifier or a two-channel
multiplexer with gain.
DEFINITIONS
Refer to the sample-and-hold amplifer section of
this catalog for the GAP-01 and PKD-01 circuit
definitions.
I
15·3
GAP-Ol
GENERAL- PURPOSE ANALOG SIGNAL
PROCESSING SUBSYSTEM
Precision Monolithics Inc.
FEATURES
•
•
•
•
•
•
•
Several applications exploit the ability to select the signal
path through the GAP-Ol. As a two-channel multiplexer or
analog switch, the GAP-Ol high input impedance offers
advantages when switching high impedance signals. Gain
through the "MUX" is also possible. The GAP-Ol operates as
a sample/hold amplifier in the hold mode when both transconductance amplifiers are unselected. With the on-board
comparator, a two-channel successive approximation analogto-digital conversion (ADC) system may be constructed.
Combining a sign-magnitude, digital-to-analog (DAC) converterwith the GAP-Ol results in a four-quadrant multiplying
DAC. The GAP-Ol contains all the functional devices needed
to perform synchronous demodulation or implement the
absolute value function.
Low Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3mV
Low Zero-Scale Error ........................... 4mV
Low Droop Rate ........................... O.1mV/ms
Wide Bandwidth ............................. 400kHz
Digitally Selected Signal Path
Uncommitted Comparator On Chip
Wide Application Versatility
• Synchronous Demodulator
• Absolute Value Amplifier
• Two-Channel S/H Amplifier
• Two-Channel Multiplexer With Gain
ORDERING INFORMATIONt
Vos
(mV)
Vzs
(mV)
MILITARY
3
6
4
7
GAP01AX'
GAP01BX'
HERMETIC
PLASTIC
INDUSTRIAL COMMERCIAL
GAP01EX
GAP01FX
FUNCTIONAL DIAGRAM
GAP01EP
GAP01FP
COMPARATOR
AMPLIFIER A NULL
-INPUT +INPUT
• For devices processed In total compliance to M I L·STD-883. add 1883 after
part number. Consult factory for 883 data sheet.
tAil commercial and Industrial temperature range parts are available with
burn-in. For ordering informatIOn see 1986 Data Book, Section 2.
OUTPUT
CHANNELA''''''I-_-d
-INPUT
GENERAL DESCRIPTION
Designed as a general-purpose analog processing subsystem, the GAP-Ol combines many commonly used system
building blocks within a single integrated circuit.
VOUT
The basic circuit versatility stems from the GAP-Ol's architecture. The circuit features two differential input transconductance amplifiers, two low-glitch current mode switches,
an output voltage buffer amplifier, and a precision comparator.
CHANNEL B
0-'-1---1
GAP-In
SWITCHES SHOWN FOR
Both transconductance amplifier outputs are switched by
current-mode switches into the voltage follower output
buffer, thus providing two digitally selectable signal paths
through the device. Gain through the two channels may be
different in both sign and magnitude depending upon feedback selection. An external capacitor provides loop compensation and doubles as a hold or "memory" capacitor when the
GAP-Ol functions as a dual-channel sample/hold amplifier.
Offset voltage and charge transfer errors are trimmed
by using the "Zener-Zap" trim technique. The output buffer
features a FET input stage to reduce droop rate error in S/H
applications. A bias current cancellation circuit minimizes
droop error at high ambient temperature.
~"'O
CHANNEL B =0
CONTROL LOGIC
The inclusion of a preCision comparator on chip increases
the GAP-Ol's versatility and cost effectiveness in data
conversion applications. The output high voltage level is set
by external resistors. This scheme maximizes noise immunity and permits interface to all standard logic famil ies .
CiiA
Ch B
0
0
0
1
0
OUTPUT
to C
Channel A
Sum
Hold Last Input
Channel B
Manufactured under the following patent: 4.285.051.
15-4
1/86, Rev. A
---------1~ GAP-Ol GENERAL-PURPOSE ANALOG SIGNAL PROCESSING SUBSYSTEM
ABSOLUTE MAXIMUM RATINGS (Note 2)
Operating Temperature Range
GAP01AX, BX ...................... -55'C to + 125'C
GAP01 EX, FX ....................... -25' C to +85' C
GAP01EP, FP .......................... 0'Cto+70'C
DICE Junction Temperature (T J) ••••••• -65' C to + 150' C
Supply Voltage ................................... ± 18V
Power Dissipation .............................. 500mW
Input Voltage. . . .. . . . .. . . . . . . ... Equal to Supply Voltage
Logic and Logic Ground
Voltage ...................... Equal to Supply Voltage
Output Short-Circuit Duration ................. Indefinite
Amplifier A or B Differential Input Voltage .......... ±24V
Comparator Differential Input Voltage .............. ±24V
Comparator Output Voltage ... Equal to Positive SupplyVoltage
Hold Capacitor Short-Circuit Duration ......... Indefinite
Storage Temperature ................. -65'C to +150'C
Lead Temperature (Soldering, 60 sec) ............. 300'C
(NOTE 1)
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
IS-Pin DIP (X)
IOO'C
IOmW/'C
IS-Pm DIP (P)
50'C
IOmW/'C
NOTES:
1. Maximum package power diSSipation vs. ambient temperature.
2. Absolute rallngs apply to both DICE and packaged parts, unless otherwise
noted.
DICE CHARACTERISTICS
PIN CONNECTIONS
CHANNEL B
LOGIC
GROUND
COMPARATOR
OUTPUT
INVERTING
INPUT
NQNINVERTING
INPUT
BNULL
INVERTING
INPUT (A)
NON INVERTING
INPUT (A)
B NULL
DIE SIZE 0.090 X 0.100 Inch, 9,000 sq. mils
(2.286 X 2.54; 5.8 sq.mm)
INVERTING
INPUT (8)
NON INVERTING
INPUT (8)
1. CHANNEL (8)
2.
v+
3. Your
4.
5.
6.
7.
8.
9.
18-PIN HERMETIC DIP
(X-Suffix)
EPOXY DIP
(P-Sufflx)
CH
(A) NULL
(A) NULL
INVERTING INPUT (AI
NONINVERTING INPUT (AI
V-
10.
11.
12.
13.
14.
15.
16.
17.
18.
NON INVERTING INPUT (8)
INVERTING INPUT (8)
(81 NULL
(81 NULL
COMPARATOR NONINVERTING INPUT
COMPARATOR INVERTING INPUT
COMPARATOR OUTPUT
LOGIC GND
CHANNEL (A)
For additional DICE information refer to
1986 Data Book, Section 2.
I
15-5
1/86, Rev. A
~ GAP-O'I GENERAL-PURPOSE ANALOC SICNAL PROCESSlt~G SUBSYSTEM
ELECTRICAL CHARACTERISTICS
at
Vs = ± 15V, CH = 1000pF, TA = 25° C.
GAP01A/E
PARAMETER
SYMIOL
MIN
CONDITIONS
TVP
GAP01B/F
MAX
MIN
TVP
MAX
UNITS
"am" AMPLIFIERS A, I
Zero-Scale Error
Vzs
4
3
7
mV
Input Offset Voltage
Vos
3
3
6
mV
Input Bias Current
16
80
150
80
250
nA
Input Oflset Current
los
20
40
50
100
Voltage Gain
Ay
Open-Loop
Bandwidth
BW
Ay=1
Common-Mode
Rejection Ratio
CMRR
-IOVSVCMS+IOV
Power Supply
Rejection Ratio
18
PSRR
±9VSVsS±18V
Input Voltage Range
VCM
(Note 2)
Slew Rate
SR
Feedthrough Error
25
10
0.4
80
74
90
VlmV
0.4
MHz
80
dB
dB
86
96
76
96
±11.5
±12
±11.5
±12
V
0.5
Vlp.a
0.5
.1VIN = 20V. CHA = I. CHB = 0 (Note 2)
nA
25
66
80
Acquisition Time to
0.1 % Accuracy
taq
20V Step. AYCL = +1 (Note 2)
41
Acquisition Time to
0.01 % Accuracy
taq
20V Step. AYCL = +1 (Note 2)
45
66
70
80
41
dB
70
liS
p.a
45
COMPARATOR
Input Offset Voltage
Vos
0.5
1.5
I
3
mV
Input Bias Current
16
700
1000
700
1000
nA
Input Offset Current
los
75
300
75
300
Voltage Gain
Ay
2kO Pull-up Resistor to 5V (Note 2)
Common-Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
nA
5
7.5
3.5
7
VlmV
-IOVSVCMS+IOV
82
106
82
106
dB
PSRR
±9VSVsS±18V
76
90
76
90
dB
Input Voltage Range
VCM
(Note 2)
±11.5
±12.5
±11.5
±12.5
Low Output Voltage
VOL
ISINK S 5mA. Logic GND = OV
-0.2
0.15
04
-0.2
0.15
0.4
V
"OFF" Output
Leakage Current
IL
VOUT=5V
25
80
25
80
IIA
Output ShortCircuit Current
Isc
VOUT=5V
12
45
12
45
mA
ts
5mV Overdrive. (Note 3)
2kO Pull-up Resistor to 5V
Response TI me
7
7
ISO
V
ISO
ns
DIGITAL INPUTS-CHA, CHI (Note 3)
Logic "I" Input Voltage
VH
Logic "0" Input Voltage
VL
2
2
Logic "I" Input Current
IINH
VH= 3.5V
0.02
Logic "0" Input Current
IINL
VL =0.4V
1.6
10
0.02
0.07
V
0.8
0.8
0.02
2
V
!IA
10
/loA
0.1
mVims
MISCELLANEOUS
Droop Rate
VOR
TI = +25°C (Note I)
Output Voltage Swing.
AmplifierC
VOP
RL = 2 5k
Short-Circuit Current:
AmplifierC
Isc
±11.5
7
SWitch Aperture Time
SWitch SWitching Time
Slew Rate. Amplifier C
SR
RL = 2.5k
Power Supply Current
ISY
No Load
±12.5
IS
±II
40
7
±12
IS
V
40
mA
tap
75
75
ts
50
50
ns
2.5
2.5
VIliS
5
6
NOTES:
I. Due to limited production test times the droop current corresponds to
junction temperature (TI ).
ns
9
mA
2. Guaranteed by design.
3. Channel A = "I". Channel B = "0".
15-6
1/86, Rev. A
-
-
-
---
--
-
----
------_.-
IfMD
GAP-01 GENERAL-PURPOSE ANALOG SIGNAL PROCESSING SUBSYSTEM
ELECTRICAL CHARACTERISTICS at Vs=± 15V. CH= 1000pF. -55'C :5TA:5125'C forGAP01AX & BX; -25'C :5TA:585'C
& FX. and O' C :5 TA :5 70' C for GAP01 EP & FP.
for GAP01 EX
PARAMETER
SYMIOL
GAP01A/E
MIN
TVP
MAX
CONDITIONS
GAP01B/F
MIN
TYP
MAX
UNITS
"8m" AMPLIFIERS A. I
Zero-Scale error
Vzs
4
7
6
12
mV
Input Offset Voltage
Vos
3
6
5
10
mV
Average Input
Offset Drift
TCVos
(Note II
Input Bias Current
Ie
Input Offset Current
los
Voltage Gain
Av
Common-Mode
Rejection Ratio
CMRR
-10V:5 VCM :5 + 10V
Power Supply
Rejection Ratio
PSRR
±9V:5 Vs:5 ±18V
Input Voltage Range
VCM
(Note II
Slew Rate
SR
Acquisition Time to
0.1% Accuracy
taq
-3
-6
-5
-6
p.V/'C
160
250
leo
500
nA
30
lOa
30
150
7.5
74
82
72
nA
9
V/mV
80
dB
dB
80
90
70
90
±11
±12
±10.5
±12
V
0.4
0.4
VII's
60
60
p.S
20V Step, AVCL = + I
COMPARATOR
Input Offset Voltage
Vos
Average Input
Offset Drift
TCVos
Input Bias Current
18
Input Offset Current
los
Voltage Gain
Av
2kll Pull-up Resistor to 5V, (Note I I
Common·Mode
Rejection Ratio
2.5
(Note II
mV
-4
-6
-4
-6
p.V1'C
1000
2000
1100
2000
nA
lao
600
lOa
600
nA
4
6.5
2.5
6.5
V/mV
80
lao
80
92
dB
72
82
72
86
dB
CMRR
-10V:5 VCM :5 +10V
Power Supply
Rejection Ratio
PSRR
±9V:5 Vs:5 ±18V
Input Voltage Range
VCM
(Note II
±11
Low Output Voltage
VOL
ISINK :5 5mA, Logic GND = 5V
-0.2
"OFF" Output
Leakage Current
'L
VOUT=5V
Output ShortCircuit Current
Isc
VOUT= 5V
Response Time
ts
5mV Overdrive, (Note 31
2kll Pull-up ReSistor to 5V
6
±11
0.15
0.4
25
10
-0.2
V
V
lOa
25
leo
p.A
0
45
10
45
mA
U
ns
~
200
DIGITAL INPUTS-CHA, CHI (Note 3)
VH
Logic "0" Input Voltage
VL
Logic "1" Input Current
I'NH
VH = 3.5V
0.02
Logic "0" Input Current
I'NL
VL = 0.4V
2.5
V
0.8
0.8
0.02
15
2.5
V
p.A
15
p.A
10
mV/ms
MISCELLANEOUS
Droop Rate
VOR
Tj = Max. Operating Temp., (Note 2)
Output Voltage Swing:
AmplifierC
VOP
RL =2.5k
Short-Circuit Current:
AmplifierC
Isc
Switch Aperture Time
tap
Slew Rate: Amplifier C
SR
RL = 2.5k
Power Supply Current
ISY
No Load
10
±11
±12
12
40
75
±10.5
±12
6
12
V
40
75
mA
ns
2
5.5
VII's
8
6.5
10
mA
NOTES: See next page.
15-7
Z
0.4
200
Logic "1" Input Voltage
Vl
0.15
1/86, Rev. A
f::
~
~
U
I-LI
p..
en
---------l~ GAP-01 GENERAL-PURPOSE ANALOG SIGNAL PROCESSING SUBSYSTEM
WAFER TEST LIMITS at Vs =
±15V. CH
PARAMETER
SYMBOL
=
1000pF. TA
=
25°C.
GAP-01N
CONDITIONS
LIMIT
UNITS
"gm" AMPLIFIERS A. B
Zero-Scale Error
Vzs
Input Offset Voltage
Vos
Input Bias Current
18
2S0
Input Offset Current
los
100
nAMAX
Voltage Gain
Av
10
V/mV MIN
Common-Mode
Rejection Ratio
CMRR
-IOV"VeM,,+IOV
74
dBMIN
Power Supply
Rejection Ratio
PSRR
±9V" Vs " ±18V
76
dBMIN
Input Voltage Range
VeM
mVMAX
mVMAX
(Note I)
~V'N
Feedthrough Error
= 20V. CHA = I, CHB = 0 (Note I)
nAMAX
±II.S
VMIN
66
dBMIN
COMPARATOR
Input Offset Voltage
Vos
3
mVMAX
Input Bias Current
18
1000
nAMAX
Input Offset Current
los
300
nAMAX
Voltage Gain
Av
2kn Pull-up Resistor to SV (Note I)
3.S
V/mV MIN
Common-Mode
Rejection Ratio
CMRR
-IOV" VeM " +IOV
82
dBMIN
Power Supply
Rejection Ratio
PSRR
±9V" Vs ,,±18V
76
dBMIN
Input Voltage Range
VeM
(Note I)
Low Output Voltage
VOL
ISINK S SmA, Logic GND = SV
"OFF" Output
Leakage Current
IL
Output ShortCircuit Current
Ise
±II.S
VMIN
0.4
-02
VMAX
VMIN
VOUT=SV
80
/,AMAX
VOUT= SV
4S
7
mAMAX
mAMIN
0.8
VMAX
DIGITAL INPUTS-CHA. CHB (Note 3)
Logic "I" Input Voltage
VH
Logic "0" Input Voltage
VL
VMIN
Logic "I" Input Current
IINH
VH = 3.SV
Logic "0" Input Current
IINL
VL = 0.4V
Droop Rate
VOR
Output Voltage Swing.
Amplifier C
VOP
/'AMAX
10
/'AMAX
T = 2SoC
T~ = 2SoC(See Note 2)
0.1
0.20
mV/ms MAX
mV/ms MAX
R L =2.Sk
±II
VMIN
40
mAMAX
mAMIN
9
mAMAX
MISCELLANEOUS
Short-Circuit Current:
Amplifier C
Ise
Power Supply Current
ISY
No Load
NOTES:
I. Guaranteed by design.
2. Due to limited production test times the droop current corresponds to
junction temperature (T,). The droop current vs. time (after power-on)
curve clarifies this pOint. Since most devices (in use) are on for more than
I second, PMI specifies droop rate for ambient temperature (TA) also. The
warmed-up (TAl droop current specification is correlated to the junction
temperature (T,) value. PMI hasa droop current cancellation circuit which
minimizes droop current at high temperatures.
3. Channel A = "I", Channel B = "0".
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
15-8
1/86, Rev. A
--------l1fHD
GAP-01 GENERAL-PURPOSE ANALOG SIGNAL PROCESSING SUBSYSTEM
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±15V, CH = 1000pF, TA = 25°C.
GAP-01N
PARAMETER
SYMBOL
CONDITIONS
TYPICAL
UNITS
05
VII'S
"Um" AMPLIFIERS A, B
Slew Rate
SR
Acquisition Time to 0.1 % Accuracy
Acquisition Time to 0.01 % Accuracy
tag
20V step, AVCL = 1
41
I'S
tag
20V step, AVCL = 1
45
p.s
ts
5mV Overdrive
2kn Pull-up Resistor to +5V
150
ns
ns
COMPARATOR
Response Time
MISCELLANEOUS
Switch Aperture Time
tap
75
Switching Time
ts
50
ns
Slew Rate: Amplifier C
SR
2.5
VII's
RL = 2.5kn
TYPICAL PERFORMANCE CHARACTERISTICS
SMALL-SIGNAL OPEN-LOOP
GAIN/PHASE VI FREQUENCY
ACQUISITION TIME VI
INPUT VOLTAGE STEP SIZE
~r-----'------r----~-----,
DROOP CURRENT
VB TEMPERATURE
0
TA = 25"C
CH = 1000pF
,
45
z
""
8
'35
'80
i!:
10k
lOOk
1M
10M
1
1
1
IL
~
'O~~~~-----r-----+----~
1k
8
,
S
90
A~ OP~RATIING
UJ'TS
TEMPERATURE
40~----1------r-----+--~~
0~0----~------'~0----~'5----~20
FREQUENCY (Hz)
2
L
0
-75 -50
,/
-25
INPUT STEP (VOLTS)
AMPLIFIER CHARGE INJECTION
ERROR VI INPUT VOLTAGE
AND TEMPERATURE
HOLD-MODE POWER SUPPLY
REJECTION VI FREQUENCY
+'0
0
50
75
100 125 150
LOGIC INPUT CURRENT VB
LOGIC INPUT VOLTAGE
'00
POLARITY OF ERROR
MAY BE POSITIVE OR
TA =2S0C
VIN = OV
CH '" 1000pF_
C H "" 1000pF
TA "'2S"C
NEGATIVE
80
l-
I-r- -551c
(+15v +lV SIN wT)
-5V
+5V
+12S"C
-0.5
-, 0
-
60
NEGATIVE SUPPLY
(-15V +1V SIN w)
40
I
r- +2S"C
'" ~
......,
~
+2~C
-ss"c
ERROR (mV)
+'0v
20
+'2lC
-
-2
LOGIC 0
CHANNEL A = 1
CHANN)EL B = 0
o
'0
'00
,k
FREQUENCY (Hz)
15-9
100k
'M
-2
LOGIC GRJUND = OV
I
-3
'Ok
I
LOJ,C'
POSITIVE SUPPLY
'OV
25
TEMPERATURE fOCI
I
I
I
-1
LOGIC INPUT VOL TAGE (VOLTS)
1/86, Rev_ A
----------l!EMD
GAP-01 GENERAL-PURPOSE ANALOG SIGNAL PROCESSING SUBSYSTEM
TYPICAL PERFORMANCE CHARACTERISTICS
COMPARATOR INPUT BIAS
CURRENT VB DIFFERENTIAL
INPUT VOLTAGE
COMPARATOR OUTPUT
VOLTAGE VB OUTPUT
CURRENT AND TEMPERATURE
+3
10
;=
Vs .1±15V
i<
lNPJr CURR1ENT Muir
TA "'2SoC
i!:
'":E:w
1l
2:
+2
>-
~
"0w
"~
+1
f5
OTHER
OTHER
'"
f--INPUT
'"
"::1"
f--INPUT
ATOV
AT-1OV
OTHE
_INPUT
AT +1 OV
0
0.8
~
>
a;
02
00
>-
;;;
-02
-1
-10
-5
10
~
~
~
z
"'"
0
3
80
~
TEST CONDITION
~
w
z
z
~
"'/
0
~
~
w
z
z
w
"
"
c:>
>:="
0"
'" \
w
AMPLIFIER A (B) OFF, INPUT = 20V Pk-Pk
AMPLIFIER B (8) ON, INPUT = OV
lk
10k
lOOk
OmV
~~
1M
-5mV
-50
100M
FREQUENCY (Hz)
~
80
100
120
I
-05
0.0
05
"
10
15
20
VB
TEMPERATURE
0
C-
uV
-5mV ' - _......_ ' - - - ' ' - - ' _....._
50
100
150
200
250
300
-50
50
100
150
200
......_
250
.....
300
TIME (nsac)
COMPARATOR OUTPUT
RESPONSE TIME (2kO
PULL-UP RESISTOR, TA = 25° C)
5V
w
w
~
~
3V
OmV
>
>~
":=
2V
-5mV
i<
"0
0
"C;
~
OV
0
>
~
:=
TIME (20;,ts/DIV )
:\
-1.0
+5mV
>
"
\
4V
~
0
TO +5V
INPUT VOL TAGE (mV)
LARGE-SIGNAL
NON INVERTING RESPONSE
"C;
>-
~RL =1.0kn
TO +5V
T A '!25'C
w
0
RL "'2.0kn_
1"'; ,I'"
,
RESISTOR'" 2kO
~
ov
2
-15
140
>
>
c
"C;
60
TIME (nsac)
LARGE-SIGNAL
INVERTING RESPONSE
~w
5
5o
1/ IV
_T)5507~ 1'+125
_
OV
+5mV
o
100
2V
~
~
10
3V
CI
20
1
40
pLLL-U~
4V -
1V
~
""
~
COMPARATOR RESPONSE TIME
5V
;!
60 I--C H '" 1000pF, AMPLIFIER
A AND B CONNECTED
IN +1 GAIN
40
3
10 - OUTPUT SINK CURRENT (rnA)
T~' 25°~
100
h ~V
o
20
CHANNEL TO CHANNEL ISOLATION
VB FREQUENCY
in
w
"
~
~
V
15
=VIN
NON-INVERTING INPUT = OV
4
2:
~
~
INPUT VOLTAGE (VOL IS)
120
c:
J~
0.4
INVERTING INPUT
~
_55°C~
>
i<
-15
+25°~=-",
06
Vs = ±15V
TA =25°C
I
+1 250C
BE LIMITED TO LESS-THAN lmA
>-
e
1
>-
COMPARATOR TRANSFER
CHARACTERISTIC
>~
0
>-
;;;
lV
OV
TIME (20;,ts/DIV )
15-10
TIME (50ns/DIV )
1/86, Rev. A
--
---- - - - - - - -
--------IlfMD
GAP-01 GENERAL-PURPOSE ANALOG SIGNAL PROCESSING SUBSYSTEM
TYPICAL PERFORMANCE CHARACTERISTICS
COMPARATOR
SETTLING TIME FOR
-10V TO OV STEP INPUT
COMPARATOR
SETTLING TIME FOR
+10V TO OV STEP INPUT
COMPARATOR OUTPUT
RESPONSE TIME (2kO
PULL-UP RESISTOR, TA = 25° C)
ov
>
~
5V
w
~
~
"
OUTPUT SWING OF
COMPARATOR VI
SUPPLY VOLTAGE
,.
"
10
0:
0
:;
~
-2
0
w
"
-6
I-
-10
"
-1'
"
~
0
r--- V+ •
-
...
...
~ ... ~
0:
0:
3V
OmV
I-
2V
-6mV
-1.
~
~
0:
§"
V-
+2SoC
+125°C,_
~
"
...
~
~
-2
I!!o.
-10
16
12
SUPPLY VOLTAGE +V AND
"'-
r-
V-
"
-1.
-I
r- V~SUPPLY
-2
~
r-=-..
-10 f-- V-SUPPLY
~
12
SUPPLY VOLTAGE +V AND
.--
...-=""I
+25°C
-56'6
+2SOC
"""'=
,.
-1.
I--i-----
~120'c ~
~
-1.
'~
16
-v
...
.....::::;:~+12..C _
~
"'~
'"'l!!!I!oo.
•
(VOLTS)
12
SUPPL V VOLTAGE +V AND
15
,.
-v (VOLTSI
SUPPLY CURRENT VI
SUPPLY VOLTAGE
~
-
INPUT + RANGE ~C
0
>
~
w
w
§
II
-55°C
+25°C
+126°1::
+25°C
...
......".
~ +125'f-
-
~
,.
15
12
SUPPLY VOLTAGE +V AND
......".
-v
....
,.
•o
12
SUPPLY +V AND
(VOL TSI
15-11
15
18
-v (VOL TSI
1/86, Rev. A
--------I~ GAP-01 GENERAL-PURPOSE ANALOG SIGNAL PROCESSING SUBSYSTEM
TYPICAL PERFORMANCE CHARACTERISTICS
,.
AMPLIFIER "A" OR "B"
VOLTAGE TO CURRENT
TRANSFER FUNCTION
(VIN vs leH)
INPUT RANGE OF LOGIC
GROUND vs SUPPLY VOLTAGE
600
'4
~
I
-2
-6
-'0
"$!i!!;:,
-1-
"
~
~~i!;!,
-,.
+12 C
-400
"
'2
4
.4
-200
-~
-'4
..oi! ~
_5
r
+25°C
J I YI>'"
'5
-11/,
1..lP'
1
ACCEPTABLE GROUND
PIN POTENTIAL IS
BETWEEN SLIDE LINES
_55cC
i!!;:,
I
200
+2SOC
-55°C
-
1_55 C
+125°C
~
"" ....
r,,'' ' ' '
I
+25°C
400
II'"
~~~ dillO'
'0
~
+12SOC
iii"
~
V If
-I-' l.t:
~
"~t
8
1~!! .~
7
,.
-600
....06
-04
GAP_01
"
=~
-02
0.0
7
02
OUT
10011
04
06
VIN (VOLTS)
SUPPLY VOLTAGE +V AND -V (VOLTS)
COMPARATOR OFFSET VOLTAGE
vs TEMPERATURE
A AND B AMPLIFIERS OFFSET
VOLTAGEvsTEMPERATURE
-,
-2~-+--+--4--~--~-+--+-~
~r--+--+--4--~--~-+--+-~
TEMPERATURE fOCI
APPLICATION CIRCUITS
GAP-01 WITH POSITIVE AND NEGATIVE GAINS
GAP-01IN UNITY GAIN (+1) CONFIGURATION
CHANNELAI
CHANNEL B
0----,-------,
CHANNEL A
INPUT
R1
OUTPUT
>-1-1--+--<>
OUTPUT
CHANNEL A
INPUT
R,
CHANNEL B
INPUT
Rs
CHANNEL B
INPUT
R.
CHANNEL B
c,
.::;J; 1000pF
R,'" R3IR.
15-12
Rs= R21Rs
1/86, Rev. A
--------IIEMD
GAP-01 GENERAL-PURPOSE ANALOG SIGNAL PROCESSING SUBSYSTEM
APPLICATION CIRCUITS
ALTERNATE GAIN CONFIGURATION
R,
CHANNEL A
o----.....f - - - - - - - - ,
OUTPUT
>--.-+-*--<>
R,
A3 >2 41dl
R4>24kn
CH
CHANNEL B
l
0-------------'
1000PF
IF BOTH CHANNEL A AND CHANNEL B HAVE
THE SAME POSITIVE VOLTAGE GAIN, A SIN-
GLE VOL lAGE DIVIDER SETS THE GAIN FOR
BOTH CHANNELS
ABSOLUTE VALUE CIRCUIT WITH POLARITY PROGRAMMABLE OUTPUT
INPUT
---
+sv
27kn
4.7kn
10kn
1%
POLARITY
*
1iI:.I
II
CONTROL
SIGNAL
TRANSISTOR INCREASES COMPARATOR OAIN
Ioi:'::::'::'
L::::.I
I,i;,OI
~
'1
~
il'4
-- =-
~
TRACE 1 INPUT SIGNAL
~
I
IIIJ
1.::::.1
'
II!
~
II
TRACE 2" CHANNEL A/CHANNEL B
CONTROL SIGNAL
II-
'1 ~
:~
I·
:!'II
TRACE 3: OUTPUT POLARITY CONTROL
SIGNAL .. 0
~..
~, ~
:7'1
15-13
:!'II
:~
I! ~
~
•-
TRACE 1 INPUT SIGNAL
TRACE 2 CHANNEL AlCHANNEL B
CONTROL SIGNAL
••
TRACE 3- OUTPUT POLARITY CONTROL
SIGNAL = 1
1/86, Rev. A
--------t~ GAP-01 GENERAL·PURPOSE ANALOG SIGNAL PROCESSING SUBSYSTEM
TWO·CHANNEL SAMPLE/HOLD AMPLIFIER
00
+15Y
-15V
R,
INPUT Ao--.N>I'-+--..........!...H
,.n
INPUT B o----,MI'------"'ll-'
eH
4
,.
500PF~
CiiiNNErifCHANNEL B
13
0 - -.....--If',~'!;'0::0~
SAMPlElii0L6 0 - - - -......,.,.1.:.:'/
CHANNEL A GAIN ... -
CHANNEL B GAIN -1
~ = -10
+~ =2
TRACE 1: INPUT SIGNAL B (1V1DIY.)
TRACI! 2: INPUT SIGNAL A (O.5V/DIV.)
TRACE S. CHANNEL A/CHANNEL B
CONTROL SIGNAL (IVlDIY.)
TRACE 4' OUTPUT WITH SAMPLE/HOm
= "1" (5Y/DIY.)
TRACE l' INPUTSIQNAL B (1Y1DIV)
TRACE 2: SAMPLE/HOili (5V/DIY.)
CONTROL SIGNAL
TRACE 3' OUTPUT SIGNAL (2V1DIY)
~CHANNEL B = "1"
15-14
1/86, Rev_ A
---------I~ GAP-01 GENERAL-PURPOSE ANALOG SIGNAL PROCESSING SUBSYSTEM
APPLICATION CIRCUITS
LOGIC LEVEL TRANSLATION FOR
GAP-01 SINGLE SUPPLY OPERATION
DIGITAL GROUND CONNECTION FOR
SINGLE SUPPLY OPERATION
v+ '"
V+ - 16V
GAP-01
t----. TO
LOGIC
R" S.1kO
GAP-Ol
17
DIG
GNO
15V
R1 ., 3.3kO
CONTROL
'-
-14V
R2
OIl
3900
TT~>----+
.:s ~
.:s ~
~
R3 = 1kO
COLLECTOR
LOGIC HIGH VOLTAGE = 44V
LOGIC LOW VOLTAGE'"' 1.SSV
FOUR QUADRANT MULTIPLYING DAC
A INPUT
en
CH
Z
0
J
f::
u
Z
::J
~
81
g
8"
B INPUT
U
~
~
en
15-15
1/86, Rev. A
---------i~ GAP-01 GENERAL-PURPOSE ANALOG SIGNAL PROCESSING SUBSYSTEM
APPLICATION CIRCUITS
SYNCHRONOUS DEMODULATION OF LVDT SIGNAL
,Ol
e~
OV
Vc VOH
TRACE 2
ANALOG INPUT
NX)
l;.!s/DIV
APPLICATION INFORMATION
R1
R2
5
3.5 2.7K 6.2K
5
5.0 2.7K
.,
15
3.5 4.7K 1.5K
15
5.0 4.7K 2.4K
15
7.5 7.5K 7.5K
15
10.0 7.5K 15K
Vc
R,~--
Isink
",.",(v
c '_)
VOH
CAPACITOR RECOMMENDATIONS
The external capacitor (CH) serves as the compensation
capacitor and hold capacitor in sample/hold applications.
Stable operation requires a minimum value of 500pF. Larger
capacitors may be used to lower droop rate errors. but acquisition time will increase and bandwidth decrease.
The maximum comparator high output voltage (VOH) should
be constrained to: VO H (max) < V+ -2V
The capacitor should have very high insulation resistance
and low dielectric absorption. Fortemperatures below 85° C.
a polystyrene capacitor is recommended. while a Teflon
capacitor is recommended for high temperature environments.
CAPACITOR GUARDING AND GROUND LAYOUT
Ground planes are recommended to minimize ground path
resistance. Separate analog and digital grounds should be
used. The two ground systems are tied together only at the
Table I
15·17
1/86, Rev. A
II
--------I~ GAP-01 GENERAL-PURPOSE ANALOG SIGNAL PROCESSING SUBSYSTEM
common system ground. This avoids digital currents returning to the system ground through the analog ground
path.
r-----------.----ov+
The CHterminal (Pin 4) isa high-impedance point. To minimize gain errors and maintain the GAP-01's inherently low
droop rate, guarding Pin 4as shown in Figure 2 is recommended.
CHANNEL A
OR
CHANNEl B
DIGITAL
GROUND
,.
CURRENT TO
17
CONTROL MODES
Figure 3
16
15
ZERO-SCALE ERROR ADJUSTMENT
For sample/hold applications the zero-scale error (Vos plus
charge injection error) can be adjusted to zero. With the input
to each channel equal to zero, the GAP-01 is switched
between the sample mode (either channel A or channel 8
active) and the hold mode (channel A-1, channel 8=0). The
output is adjusted to read zero when the unit is in the hold
mode.
14
13
REPEAT ON
"COMPONENT SIDE" OF
PC BOARD IF POSSIBLE
12
11
10
The Vzs trim circuit is identical to the Vos trim circuit.
Figure 2
OFFSET VOLTAGE ERROR ADJUSTMENT Offset voltage
through either channel A or channel 8 may be nulled with an
external 100kO, potentiometer as shown below.
LOGIC CONTROL
The transconductance amplifier outputs are switched by the
digital logic signals applied at Channel A and Channel 8 pins.
Two signal paths through the GAP-01 are possible.
The logic threshold voltage is 1.4 volts when digital ground is
at zero volts. Other threshold voltages (V TH ) may be selected
by applying the formula:
v-
v-
VTH ~ 1.4V + Digital Ground Potential.
Figure 3 shows the simplified logic control circuit. For proper
operation, digital ground must always be at least 3.5V below
the positive supply and 2.5V above the negative supply. The
logic signals must always be at least 2.8V above the negative
supply.
13
A NULL
Operating the digital ground at other than zero volts does
influence the comparator output low voltage. The VOL level is
referenced to digital ground and will follow any changes in
digital ground potential:
B NULL
GAP-01
Figure 4
VOL ~ 0.2V + Digital Ground Potential.
15-18
1/86, Rev. A
PKD-Ol
MONOLITHIC PEAK DETECTOR
(WITH RESET-AND- HOLD MODE)
PrecIsion Mo])olithics Inc
FEATURES
• Monolithic Design for Reliability and Low Cost
• High Slew Rate .............................. O.5V1p.s
• Low Droop Rate
TA=25°C ............................... O.1mVlms
TA= 125°C .............................. 10mV/ms
• Low Zero-Scale Error • .. . • .. . . . . . . . .. . . .. .. . . .. .. 4mV
• Digitally Selected Hold and Reset Modes
• Reset to Positive or Negative Voltage Levels
• Logic Signals TTL and CMOS Compatible
• Uncommitted Comparator on Chip
Through the DET control pin, new peaks may either be
detected or ignored. Detected peaks are presented as pOSitive output levels. Positive or negative peaks may be detected
without additional active circuits since amplifier A can operate as an inverting or noninverting gain stage.
An uncommitted comparator provides many application
options. Status indication and logic shaping/shifting are typical examples.
PIN CONNECTIONS
ORDERING INFORMATIONt
25°C
PACKAGE
Yzs
(mY)
14-PIN DUAL-IN-LiNE PACKAGE
HERMETIC'
PLASTIC
4
7
4
7
PKD01AY'
PKD01BY'
PKD01EY
PKD01FY
4
7
PKD01EP
PKD01FP
14-PIN HERMETIC DIP
(V-Suffix)
OPERATING
TEMPERATURE
RANGE
EPOXVDIP
(P-Sufflx)
MIL
MIL
IND
IND
COM
COM
• For dev.ces processed on total compl.ance to MIL-STD-883, add /883 after
part number Consult factory for 883 data sheet
tAli commercial and Industnal temperature range parts are available With
burn-.n For orderong onformat.on see 1986 Data Book, Sect.on 2.
FUNCTIONAL DIAGRAM
+IN
-IN
OUTPUT
V+
v-
GENERAL DESCRIPTION
The PKD-Ol tracks an analog input signal until a maximum
amplitude is reached. The maximum value is then retained as
a peak voltage on a hold capacitor. Being a monolithic circuit,
the PKD-Ol offers significant performance and package density advantages over hybrid modules and discrete designs
without sacrificing system versatility. The matching characteristics attained in a monolithic circuit provide inherent
advantages when charge injection and droop rate error
reduction are primary goals.
LOGIC
13
GND
DET
OUTPUT
-'N
Innovative design techniques maximize the advantages of
monolithic technology. Transconductance (gm) amplifiers
were chosen over conventional voltage amplifier circuit
building blocks. The "gm" amplifiers simplify internal
frequency compensation, minimize acquisition time and
maximize circuit accuracy. Their outputs are easily switched
by low glitch current steering circuits. The steered outputs
are clamped to reduce charge injection errors upon entering
the hold mode or exiting the reset mode. The inherently low
zero-scale error is reduced further by active "Zener-Zap"
trimming to optimize overall accuracy.
+'N
-'N
II
+'N
RST
RST
o
The output buffer amplifier features an FET input stage to
reduce droop rate error during lengthy peak hold periods. A
bias current cancellation circuit minimizes droop error at
high ambient temperatures.
DEl OPERATIONAL MODE
0
1
1
PEAK DETECT
PEAK HOLD
RESET
o
Indeterminate
SWITCHES SHOWN FOR
RST="O", DET="O"
Manufactured under the following patent· 4,285,051
15-19
1/86, Rev. A
-------------I~ PKD-01 MONOLITHIC PEAK DETECTOR
ABSOLUTE MAXIMUM RATINGS (Note 2)
Supply Voltage ................................... ±18V
Power Dissipation .............................. 500mW
Input Voltage. . • . • • . . . •• •• •• • . •• Equal to Supply Voltage
Logic and Logic Ground
Voltage ...................... Equal to Supply Voltage
Output Short-Circuit Duration ••.•••••••••.•••• Indefinite
Amplifier A or B Differential Input Voltage •••..•••.• ±24V
Comparator Differential Input Voltage ••.•••••••••.• ±24V
Comparator Output Voltage
.. .. .. .. .. .. .. .. .... Equal to Positive Supply Voltage
Hold Capacitor Short-Circuit Duration ••.•••.•. Indefinite
Lead Temperature (Soldering, 60 sec) .••..•••...•. 300°C
Storage Temperature Range
PKD01AY, PKD01BY •..•••.•••..•••. -65°C to +150°C
PKD01 EY, PKD01 FY ................ -65° C to + 150° C
PKD01EP, PKD01FP ................ -65°Cto+125°C
ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
at Vs
Operating Temperature Range
PKD01AY, PKD01BY .•••••.•.•.••••• -55°C to +125°C
PKD01 EY, PKD01 FY ••••.••••.••••••• -25° C to +85° C
PKD01 EP, PKD01 FP .................... 0° C to + 70° C
Dice Junction Temperature •.••.••••.•. -65°C to +150°C
PACKAGE
(Note 1)
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
14-Pin DIP (Y)
80'C
10mwrc
14-Pin DIP (P)
50'C
6mwrc
NOTES:
Maximum package power dissipation vs. ambient temperature.
2. Absolute ratings apply to both packaged parts and DICE. unless
otherwise noted.
= ±15V, CH = 1000pF, TA = 25° C.
PKD01A/E
MIN
TYP
MAX
CONDITIONS
MIN
PKD01B/F
TYP
MAX
UNITS
"9 m" AMPLIFIERS A, B
Zero-Scale Error
Vzs
2
4
3
Input Offset Voltage
Vas
2
3
3
Input Bias Current
18
80
150
80
250
Input Offset Current
los
20
40
20
75
Voltage Gain
Av
Open-Loop
Bandwidth
BW
Av= 1
Common-Mode
Rejection Ratio
CMRR
-10VSVCM S+l0V
80
90
PSRR
±9VSVs S±18V
86
Input Voltage Range
VCM
(Note 1)
±115
Slew Rate
SR
Power Supply
Rejection Ratio
Feedthrough Error
Acquisition Time to
0.1 % Accuracy
AcqUisition TIme to
001% Accuracy
18
25
10
nA
nA
VlmV
0.4
MHz
74
90
dB
96
76
96
dB
±12
±115
±12
V
0.5
Vlp.s
80
dB
05
66
mV
25
04
tiV ,N = 20V. DET = 1. RST = O. (Note 1)
mV
80
taq
20V Step. AVCL = + 1. (Note 1)
41
taq
20V Step, AVCL = +1, (Note 1)
45
66
70
41
70
45
p's
p's
COMPARATOR
I nput Offset Voltage
Vas
Input Bias Current
18
Input Offset Current
los
Voltage Gain
Av
2kO Pull-up Resistor to 5V. (Note 1)
Common-Mode
Rejection Ratio
CMRR
-10V S VCM S +10V
PSRR
±9VSVs S±18V
VCM
(Note 1)
Power Supply
Rejection Ratio
Input Voltage Range
82
NOTES:
1. Guaranteed by design
2. Due to limited productIon test tImes, the droop current corresponds to
05
15
3
mV
700
1000
700
1000
nA
75
300
75
300
nA
7.5
3.5
7.5
VlmV
106
82
106
dB
76
90
76
90
dB
±115
±125
±11.5
±12.5
V
Junction temperature (TJ) The droop current vs. tIme (after power-on)
curve clanfiesthis pOInt. Since most devices (in use) are on for more than
warmed-up (TA) droop current specification IS correlated to the junction
temperature (Tl ) value PMI hasa droop current cancellation clrcUltwhich
mmimizes droop current at high temperature. AmbIent (TAJ temperature
specIfIcations are not subject to production testing.
1 second, PMI specifies droop rate for amblenttemperature (TA) also The
DET= 1, RST =0.
15-20
1/86, Rev. A
~ PKD-Cl1 MONOLITHIC PEAK DETECTOR
ELECTRICAL CHARACTERISTICS
at Vs= ±15V. CH = 1000pF. TA = 25°C. (Continued)
PKD01A/E
PARAMETER
Low Output Voltage
"OFF" Output
Leakage Current
Output ShortCircuit Current
Response Time
SYMBOL
VOL
CONDITIONS
MIN
ISINK '; 5mA, Logic GND = 5V
TYP
-0.2
PKD018/F
MAX
MIN
TYP
MAX
0.t5
0.4
-0.2
0.15
0.4
V
80
25
80
~A
45
12
45
mA
IL
VOUT= 5V
25
Isc
VOUT= 5V
12
ts
5mV Overdrive, (Note 3)
2kO Pull-up Resistor to 5V
7
150
150
UNITS
ns
DIGITAL INPUTS-RST, DET (See Note 3)
2
Logic "I" Input Voltage
VH
Logic "0" Input Voltage
VL
Logic "I" Input Current
IINH
VH = 3.5V
002
Logic "0" Input Current
IINL
VL =0.4V
1.6
10
1.6
10
p.A
Droop Rate
VOA
TJ = 25"C,
(See Note 2)
TA =25"C
0.01
002
0.07
0.15
0.Q1
0.03
0.1
0.20
mV/ms
Output Voltage Swing:
Amplifier C
VOP
DET=1
RL = 2.5k
Short-Circuit Current:
Amplifier C
Isc
2
V
0.8
0.8
0.02
V
p.A
MISCELLANEOUS
±".5
7
Switch Aperture Time
Switch Switching Time
Slew Rate: Amplifier C
SR
RL = 2.5k
Power Supply Current
ISY
No Load
±12.5
±11
15
40
±12
V
15
40
mA
taE!
75
75
ts
50
50
ns
2.5
2.5
V/~s
ns
6
9
mA
ELECTRICAL CHARACTERISTICS atVs=±15V, CH= 1000pF. -55°C:5TA :5 125°C for PKD01AY. PKD01 BY, -25°C:5TA:585°C
for PKD01 EY, PKD01 FY and O°C:5 TA:5 70°C for PKD01 EP. PKD01 FP.
V)
PKD01A/E
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
PKD018/F
MAX
MIN
TYP
MAX
6
12
mV
10
mV
UNITS
"am" AMPLIFIERS A. B
Zero-Scale Error
Vzs
4
Input Offset Voltage
Vas
3
6
Average Input
Offset Drift
TCVos
-9
-24
-9
-24
p.V/"C
Input Bias Current
Is
160
250
160
500
nA
Input Offset Current
los
30
100
30
150
nA
Voltage Gain
Av
(Note 1)
7.5
9
9
VlmV
CMRR
-10V'; VCM '; +10V
74
82
72
Power Supply
Rejection Ratio
PSRR
±9VSVs:5±18V
80
90
Input Voltage Range
VCM
(Note 1)
±11
±12
Slew Rate
SR
Acquisition Time to
0.1% Accuracy
taq
20V Step, AVCL = +1, (Note 1)
80
dB
70
90
dB
±10.5
±12
V
0.4
0.4
VII'S
60
60
p.s
COMPARATOR
Input Offset Voltage
Vas
TCVos
Input Bias Current
Is
U
Z
::J
~
~
U
~
p.,
V)
Common-Mode
Rejection Ratio
Average Input
Offset Drift
Z
0
t==
2
(Note 1)
15·21
2.5
mV
-4
-6
-4
-6
p.V/"C
1000
2000
1100
2000
nA
1/86, Rev. A
II
~ PKD-01 MONOLITHIC PEAK DETECTOR
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, C H = 1000pF, -55°C:s TA:S 125°C for PKD01 AY, PKD01 BY, -25°C:s TA:S 85°C
for PKD01 EY, PKD01 FY and O°C:s TA:S 70°C for PKD01 EP, PKD01 FP. (Continued)
PKD01A/E
PARAMETER
SYMBOL
CONDITIONS
MIN
Input Offset Current
los
Voltage Gain
Av
2kO Pull-up Resistor to 5V, (Note 1)
Common-Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
Input Voltage Range
VCM
(Note 1)
±11
Low Output Voltage
VOL
ISINKS 5mA, Logic GND = 5V
-0.2
"OFF" Output
Leakage Current
IL
Output ShortCircuit Current
Response Time
PKD01B/F
TYP
MAX
100
600
MIN
TYP
MAX
100
600
UNITS
nA
4
6.5
2.5
6.5
VlmV
-10V S VCM S + 10V
80
100
80
92
dB
±9VSVs S±18V
72
82
72
86
dB
±11
0.15
0.4
VOUT= 5V
25
100
Ise
VouT =5V
10
45
ts
5mV Overdrive,
2kO Pull-up Resistor to 5V
-0.2
6
200
V
0.15
0.4
V
100
180
p.A
10
45
mA
ns
200
DIGITAL INPUTS-RST, DET (See Note 3)
Logic "I" Input Voltage
VH
Logic "0" Input Voltage
VL
Logic "I" Input Current
IINH
VH =3.5V
0.02
IINL
VL = O.4V
2.5
15
2.5
15
p.A
Droop Rate
VOR
Tj = Max. Operating Temp
TA = Max. Operating Temp.
i5Ei' = 1. (Note 2)
1.2
10
20
3
6
15
20
mVlms
Output Voltage Swing'
AmplifierC
VoP
RL = 2.5k
Short-Circuit Current:
Amplifier C
Ise
Logic "0" Input Current
2
V
0.8
0.8
V
p.A
0.02
MISCELLANEOUS
Switch Aperture Time
tap
Slew Rate: Amplifier C
SR
Power Supply Current
ISY
2.4
±11
6
±12
12
±10.5
40
6
±12
12
V
40
mA
75
75
ns
RL =2.5k
2
2
VII's
No Load
5.5
6.5
10
mA
NOTES:
1. Guaranteed by design.
2. Due to limited production test times, the droop current corresponds to
junction temperature (TJ) The droop current vs. time (after power-on)
curve clarifies this pOint. Since most devices (in use) are on for more than
1 second, PMI specifies droop rate for ambient temperature (TA) also.
The warmed-up (TA) droop current speCifIcation is correlated to the
junction temperature (TJl value. PMI has a droop current cancellation
circuit which minimizes droop current at high temperature. Ambient (TAl
temperature specifications are not subject to production testIng.
3. DET=l, RST=O.
15-22
1/86, Rev. A
-------------IIEHD PKD·01
MONOLITHIC PEAK DETECTOR
DICE CHARACTERISTICS
1. RST (RESET CONTROL)
2. V+
3.
4.
5.
6.
7.
8.
OUTPUT
C H (HOLD CAPACITOR)
INVERTING INPUT (A)
NONINVERTING INPUT (A)
VNONINVERTING INPUT (B)
9.
10.
11.
12.
13.
14.
INVERTING INPUT (B)
COMPARATOR NONINVERTING INPUT
COMPARATOR INVERTING INPUT
COMPARATOR OUTPUT
LOGIC GROUND
DET (PEAK DETECT CONTROL)
A,B (A) NULL
C,D (B) NULL
DIE SIZE 0.090 x 0.100 Inch, 9000 sq. mils
(2.286 x 2.54mm, 5.8 sq mm)
For additional DICE Information refer to
1986 Data Book, Section 2.
WAFER TEST LIMITS at Vs = ±15V, C H = 1000pF, TA = 25°C.
PKD·01N
PARAMETER
SYMBOL
CONDITIONS
LIMIT
UNITS
"8m" AMPLIFIERS A, B
Zero-Scale Error
Vzs
Input Offset Voltage
Vos
mVMAX
Input Bias Current
6
mVMAX
250
nAMAX
Input Offset Current
lOS
75
nAMAX
Voltage Gain
Av
10
VlmV MIN
Common-Mode
Rejection Ratio
CMRR
-10V"VCM ,,+10V
74
dBMIN
Power Supply
Rejection Ratio
PSRR
±9V" Vs " ±18V
76
dBMIN
Input Voltage Range
(Note 1)
Feedthrough Error
tN'N
=20V. DET =1, RST =0, (Note 1)
±11.5
VMIN
66
dB MIN
COMPARATOR
Input Offset Voltage
Vos
Input Bias CUrrent
Input Offset Current
lOS
Voltage Gain
2kl1 Pull-up Resistor to 5V, (Note 1)
Common-Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
Z
0
~
3
mVMAX
1000
nAMAX
300
nAMAX
3.5
VlmV MIN
82
dBMIN
U
76
dB MIN
rJ)
U
Z
::J
t:l...
~
~
Input Voltage Range
±9V"Vs ,,±18V
(Note 1)
Low Output Voltage
ISINK " 5mA, Logic GND
= 5V
"OFF" Output
Leakage Current
Output ShortCircUIt Current
rJ)
ISC
NOTES:
1. Guaranteed by design.
2. Due to limited production test times, the droop current corresponds to
junction temperature (T)). The droop current vs. time (after power-on)
curve clarifies this point. Since most devices ( in use) are on formere than
1 second, PMI specifies droop rate for ambient temperature (TA) also. The
±115
VMIN
0.4
-0.2
V MAX
VMIN
80
~AMAX
45
7
mAMAX
mAMIN
warmed-up (TA) droop current specification is correlated to the junction
temperature (TJ) value. PM! hasa droop current cancellation circuit which
minimizes droop current at high temperature. Ambient (TA) temperature
specifications are not subject to prod uction testing.
3. DET = 1, RST = O.
15-23
1/86, Rev. A
Pot
I
_ _ _ _ _ _ _ _ _ _ _ _--\~ PKD-01 MONOLITHIC PEAK DETECTOR
WAFER TEST LIMITS at Vs= ±15V, CH= 1000pF, TA = 25°C. (Continued)
PKD-01N
PARAMETER
SYMBOL
LIMIT
CONDITIONS
UNITS
DIGITAL INPUTS-RST, DET (See Note 3)
Logic "1" Input Voltage
2
VMIN
Logic "0" Input Voltage
0.8
VMAX
Logic "1" Input Current
p.AMAX
VL ~ 04V
Logic "0" Input Current
10
p.AMAX
T~ ~ 25'~ (See Note 2)
25'C
01
0.20
mV/ms MAX
mV/msMAX
AL
25k
±11
VMIN
40
mAMAX
mAMIN
9
mAMAX
MISCELLANEOUS
Droop Aate
VOA
Output Voltage Swing'
Amplif,er C
VOP
Short~Circuit
T,
~
Current
AmplifierC
Power Supply Current
Ise
ISY
No l.oad
NOTES:
1, Guaranteed by design.
2, Due to limited production test times, the droop current corresponds to
junction temperature (Tl ), The droop current vs. time (after power-on)
curve clarifies this pOint. Since most devices (in use) are on for more than
1 second, PMI specifies droop rate for ambient temperature (TAJ also. The
warmed~up (TAJ droop current specification is correlated to the junctIon
temperature (TJl value. PMI has a droop current cancellation circUit which
mmimizes droop current at high temperatures. Ambient (TAJ temperature
speCifications are not subject to production testing.
DET~ 1. AST ~O
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing,
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ± 15V, CH = 1000pF, and TA = 25° C, unless otherwise noted.
PKD-01N
PARAMETER
SYMBOL
CONDITIONS
TYPICAL
UNITS
"gm" AMPLIFIERS A, B
Slew Aate
SA
0,5
VII'S
Acquisition Time
ta
0,1% Accuracy, 20V step, AVCL ~ 1. (Note 1)
41
p.s
Acquisition Time
ta
0.01% Accuracy, 20V step, AVCL ~ 1, (Note 1)
45
p.s
150
ns
COMPARATOR
5mV Overdrive,
2kn Pull-up Resistor to +5V
Response Time
MISCELLANEOUS
Switch Aperature Time
tap
75
ns
Switching Time
ts
50
ns
Buffer Slew Rate
SR
2.5
VII'S
AL ~2.5kn
15-24
1/86, Rev. A
--------------1lfMD PKD·01 MONOLITHIC PEAK DETECTOR
TYPICAL PERFORMANCE CHARACTERISTICS
~
~
-
~
....
z
-2
...
~I:o.
~
-8
a: -10 - V - SUPPLY
i[
! -14
-1.
30
-5S0C:5TA~+126°C
0
~
~
36
~NPUT + RANGE'" V+
10
a:
0
!
...
>
:}
i
+25°C
~ +125I1 C _
........
1J 20
~
-<;o'C
12
15
o
-50
18
-25
75
100
-75 -50
125
-25
0
25
50
VS ·+1SV
TA - +25 C C
-56'C
-10
-5
+5
+10
~~~~~~++~~~~
p.
VIN (VOLTS)
~
~
10
125 150
AMPLIFIER B CHARGE INJECTION
ERROR VB INPUT VOLTAGE
AND TEMPERATURE
:~I
10.,
100
+10
t=
100
75
TEMPERATURE (oCI
100
~
...
~
50
WIDEBAND NOISE
VB BANDWIDTH
E
z
25
TEMPERATURE (OC)
1000
~g
I-
10
INPUT SPOT NOISE
VB FREQUENCY
l!l0
" r-..... """t-
-4
...
4
15
-2
0
~
i'..
25
w
"
SUPPLY VOLTAGE +V AND -V (VOLTS)
~
A, BiOS vs TEMPERATURE
40
.A-"
14
:;a:
""
A AND B AMPLIFIERS OFFSET
VOLTAGE VB TEMPERATURE
A AND B INPUT RANGE
VB SUPPLY VOLTAGE
,.
-05
~
0:
iii
1.
100
10
01
10
FREQUENCY (Hz)
100
AMPLIFIER A CHARGE INJECTION
ERROR VB INPUT VOLTAGE
AND TEMPERATURE
,.
+10
C H '" 1000pF
POLAR lTV OF
ERRORMAV BE
TA " +25°C
POSITIVE OR
NEGATIVE
+05
~
0
ffi
-5
OUTPUT VOLTAGE SWING VB
SUPPLY VOLTAGE (DUAL
SUPPLY OPERATION)
t--RL
+5
f-- -,
10
f-- V+ SUPPLV
~
~
+10
"
....
10kn
14
~
0:
-10
10
1000
BANDWIDTH (kHz)
~
--=-r
--
~
....,::::;~+126'C_
~
+25°C
-6SoC
Z
+125"C
...~::>
+25°C
::>
0
VIN (VOLTS)
-05
~
-55°C
-2
...
-8
-10
ro=-..
... "'<:::
f
-6SoC
~
~V-SUPPLY
+2SoC
""=
....
~
I---
+tSOC=
-14
-1.
10
12
4
15
,.
SUPPLY VOLTAGE +V AND -V (VOLTS)
1/86, Rev. A
15·25
~~-----------~~-
-
~
--------------t!fMD PKD-G1 MONOLITHIC PEAK DETECTOR
TYPICAL PERFORMANCE CHARACTERISTICS
,.
12.
100
~
~
I-
-2 .•
~
-5.0
-7.5
-100
:>
0
+2SoC
-5S o C
"z
:>
12
II
II
10
17'
Jilll ~
2mV ERROR
1\
75
50
25
~
OUTPUT ERROR VI
FREQUENCY AND
INPUT VOLTAGE
OUTPUT VOLTAGE vs
LOAD RESISTANCE
\ 200mV ERROR
+125°C
lUI
-12.5
-15
J!!!
+25 C
-55°C
...... +12SoC
\
"'"+lj' CJ.·C
rt
L
I
10
ERROR
o
100
01
100
1k
LOAD RESISTOR TO GROUND (kill
PKD-01 SETTLING RESPONSE
-
2Jmv
-
10k
lOOk.
1M
FREQUENCY (Hz)
LARGE-SIGNAL
INVERTING RESPONSE
PKD-01 SETTLING RESPONSE
e>
+10V
.~
";:!
ov
cl
>
I-
:>
~
5
TIME (20p.s/DIV'
SETTLING TIME FOR -10V
TO OV STEP INPUT
LARGE-SIGNAL
NONINVERTING RESPONSE
ov
~
c
".
"
E
!!!
~
;:!
cl
0
>
>
I-
l-
11
~
I-
:>
0
:>
0
TIME (20ps/DIV )
~>
.
E
!!!
ov
SETTLING TIME FOR +10V
TO OV STEP INPUT
TIME (20p.s/DIV J
15-26
OV
TIME (20ps/OIV J
1/86, Rev. A
--------------II£MD PKD-01 MONOLITHIC PEAK DETECTOR
TYPICAL PERFORMANCE CHARACTERISTICS
SMALL-SIGNAL OPEN LOOP
GAIN/PHASE vs FREQUENCY
OFF ISOLATION
vs FREQUENCY
CHANNEL TO CHANNEL
ISOLATION vs FREQUENCY
100
120
90
TA =+25°C
RL = 10kU
C L = 30pF
TA = +2S"C
~
100
Z
'"
0
OD
§
j
45
e
3
!!l
80
z 30
90
":l
-'
w
z
60
135
~
Z
'"
"'""
0
40
0:
180
0:
f-
-30 1 -......_..1...._'---1.._-'-.................
10
100
lk
10k lOOk
1M
10M
FREQUENCY (Hz)
"'""
~
\
TEST CONDITION.
AMPrFIER
Z
z
20
i i
AND
60
-
A,AV=-1
CONjECTED1IN +1
1\I'J
lAIN
20
AMPLIFIER A{B} OFF, INPUT - 20V PK-PK
AMP~'FlER IB'BI O~' INPU~
=
OV I
I
o
1
10
laO
lk
10k
lOOk
o
1M
1
10M
10
100
lk
10k
lOOk
1M
10M
FREQUENCY (Hz)
ACQUISITION TIME vs EXTERNAL
HOLD CAPACITOR AND
ACQUISITION STEP
ACQUISITION TIME vs INPUT
VOLTAGE STEP SIZE
50.----,-----,----r---,
500.---,--,---,---r--,----.
T~
~
~
40
FREQUENCY (Hz)
DROOP RATE vs TIME AFTER
POWER ON
..........
~
C H = 1000pF
-'
w
A, A)= +1
.........
8,Av=±1
80
= +l'25'C'
CH = 1000pF
V
-"
w
~30f---+-
I
"z
~
~20~--~~~~~--+_--_1
ill
10 ~~~~--+--_+--~
00
9
10
TIME AFTER POWER APPLIED (MINUTES)
20
INPUT STEP (VOLTS)
HOLD CAPACITANCE (pF)
DROOP RATE
vs TEMPERATURE
ACQUISITION OF
SINEWAVE PEAK
ACQUISITION OF STEP INPUT
10000
+10V
"
-lOV
~~:~:~~TURE I
0
0
1
-100
ov
+10V
ov
.........::k':
+10V
OV
JUNCTlON-
-lOV
-lOV
TEMPERATURE~
-50
0
+50
+100
+150
TEMPERATURE (oC)
15-27
1/86, Rev. A
--------------l~ PKO-Oi MONOLITHIC PEAK DETECTOR
TYPICAL PERFORMANCE CHARACTERISTICS
COMPARATOR OUTPUT
RESPONSE TIME
(2kO PULL-UP RESISTOR, TA = +25°C)
COMPARATOR OUTPUT
RESPONSE TIME
(2kO PULL-UP RESISTOR, TA = +25°C)
INPUT LOGIC RANGE vs
SUPPLY VOLTAGE
18
~
;;
5
.§.
~
w
"~
!1
+5
3
-5
2
>-
"I!:
0"
0
~0
4
~
~
3
.,~
>
0
2
>
;;
5
~
w
~
.§.
+.
w
w
"~
0
:;
>-
,
"0
0
"1=
'4
-5
>
>-
~"
~
-2
9
-6
~
TIME (SOns/DIV.)
_55c C :5TA
FOR
:5 +125°C
L'"
w
"a:z
"
"(;
- ~VIN~V+
~
0
~
>-
TIME (SOns/DIV)
'0
........
-'0
r -5SoC
;: +2SOC
~
+126°C'-
'~ .J
-
l"~
~
V-
~~
-'4
-'8
INPUT RANGE OF LOGIC
GROUND vs SUPPLY VOLTAGE
~
•
LOGIC INPUT CURRENT vs
LOGIC INPUT VOLTAGE
'~
'5
12
SUPPLY VOL lAGE +V AND
18
-v (VOL T8)
SUPPLY CURRENT vs
SUPPLY VOLTAGE
'8
~0
~
0
Z
"0a:
"(;u
9
~
0
w
"z
:!
>-
ir
!!
,.
".
.
..-\~
~
"'"
.... 10"
..
-2
-5SoC
~
- ("
Ilo..
~~~
-'0
-,.
-'8
r
'!"S'l
_+2ScC
12
-
-2
~I"'l!
+125°(:
I
I
I
4
-1
LOGIC INPUT VOLTAGE (VOLTS)
SUPPLY VOLTAGE +V AND -V (VOLTS)
_55°C
+2SoC'
LOGIC GROUND'" OV
I
-2
18
... ~f-
I
I
LOGIC 0
'5
"j
+125°C
-3
•
,; I-"
II. ~ 1-"\
1
u
"9
+12 C
-5~OC
I
B-
PIN POTENTIAL IS
BETWEEN SLIDE LINES
+2SoC
,..._
>-
15a:
ACCEPTABLE GROUND
-550C
~E!o.
~
+12SQ C
+2SoC
0
iI'
...1-"1-'
r-r- .......
1-'
r-
LOGIC , _
I;I!"
V+
'0
I
I
~
~
o
12
SUPPLY +V AND
15
18
-v (VOLTS)
HOLD MODE POWER SUPPLY
REJECTION vs FREQUENCY
100
TA = +25°C
VIN = OV
CH = 1000pF
80
"'~"
POSITIVE SUPPLY
(+15V +lV SIN wTj
60
a:
z
0
j:: 40
lrl
~
20
CHANNEL A = 1
CHANNEL Boo 0
0
10
'00
1k
10k
100k
'M
FREQUENCY (Hz)
15-28
1/86, Rev_ A
--------------I~ PKD-01 MONOLITHIC PEAK DETECTOR
TYPICAL PERFORMANCE CHARACTERISTICS
COMPARATOR INPUT BIAS
CURRENT vs DIFFERENTIAL
INPUT VOLTAGE
COMPARATOR OFFSET VOLTAGE
vs TEMPERATURE
COMPARATOR lOS
vs TEMPERATURE
110
+3
1
1
;::
Vs = ±15V
TA = +2SQC
11
";':"'w +2
1
1
INPUT CURRENT
~~S~E:i TL~~~T;~A
'"
1DO
-
1 80
§
g"
::""
'i
;: +1
~
I-- OTHER
INPUT
OTHER
~ INPUT
""
""
:tl
AT -lOV
AT OV
...'"
-1
OTHER
11
"\
80
"'-
70
8'"
~r--+--+--+--+--+--+--+--1
INPUT
1\
"- .........
.........
60
......
AT +10V
"'
I
~1
-15
-10
-5
+5
+10
50
-75 -50
+15
INPUT VOLTAGE (VOLTS)
COMPARATOR 18
vs TEMPERATURE
1200
1000
<:
"- r--...
1
.!E 800
f'...
"
S600
~
8
400
"~"
8
""
~
"~
z
...
.........
::"
"0
200
--
-2
I
+125 O C -
,--src"""
~......a
~ 3
~+2SoC
o
<:
-25
0
25
50
75
100
125
I---- v-
+12S0 C
--
~
_
1
~_
~
,
10
U
~6 :52~n '-.
!\-
<:
...
g
I
"0w
""C;
0
RL = lkf2
TO+5V
15
10
"
05
05
10
INPUT VOLTAGE (mV)
18
1.5
1 " + 1 2 Soc--
~V
0
-5
-50
50
100
150
200
250
300
COMPARATOR RESPONSE
TIME vs TEMPERATURE
+~25°C
w
~
~~ 3r--l--l--\C\-~--+---+--j
_55°C~
DO
>~
J~
04
0.2
,,?
-02
0
IV
J~
TIME (ns)
+25°:~
>
~
>
\
!\
~!
11
~
08
0
INVERTING INPUT = VIN
NON INVERTING INPUT
= OV
I
150
+5
COMPARATOR OUTPUT VOLTAGE
vs OUTPUT CURRENT AND
TEMPERATURE
Q
I
1S
12
Vs = ±15V
TA = +2S C
I
T A "-55
SUPPLY VOLTAGE +V AND -V (VOLTS)
COMPARATOR TRANSFER
CHARACTERISTIC
125
0>
.'i'~
....
4
150
100
~/
-l~
j J
-
+2S"'C
-14
TEMPERATURE (OC)
T A =+2S"C
1
- ,.
1
RESISTiR "2k" /
-5So C
:::O:;~
-0
-10
~&;;Ii!iI'
V+,
~
-18
-75 -50
P~LL-UJ
-
~
~~
0
w
......
~~
~
...0"
75
COMPARATOR RESPONSE
TIME vs TEMPERATURE
~
-
50
OUTPUT SWING OF
COMPARATOR vs
SUPPLY VOLTAGE
14
10
25
TEMPERATURE (OC)
18
~
0
-25
TEMPERATURE fOCI
,P
h
~
~~
§
~V
2
I
w
...""
~"""
+S
~0>
...>S
11
20
10
12
10 - OUTPUT SINK CURRENT (rnA)
15-29
14
"'
-S
-SO
50
100
150
200
250
300
TIME (ns)
1/86, Rev. A
THEORY OF OPERATION
The typical peak detector uses voltage amplifiers and a diode
or an emitter follower to charge the hold capacitor, C H,
unidirectionally (Figure 1). The output impedance of A plus
0, 's dynamic impedance, rd, make up the resistance which
determines the feedback loop pole. The dynamic impedance
by providing the output buffer with an FET input stage. A
current cancellation circuit further reduces droop current
and minimizes the gate current's tendency to double for
every 10· C temperature change.
is rd=K!:.. Id is the capacitor charging current.
qld
The pole moves toward the origin of the S plane as Idgoes to
zero. The pole movement in itself will not significantly
lengthen the acquisition time since the pole is enclosed in the
system feedback loop.
When the moving pole is considered with the typical frequency compensation of voltage amplifiers there is however,
a loop stability problem. The necessary compensation can
increase the required acquisition time. PMI's approach
replaces the input voltage amplifier with a transconductance
amplifier; Figure 2.
Figure 1. Conventional Voltage Amplifier Peak Detector
The PKD-01 transfer function can be reduced to:
VOUT
1 + sC H
gm
Figure 2. Transconductance Amplifier Peak Detector
Where: gm ~ 1p.A/mV, ROUT ~ 20MO.
The diode in series with A's output (Figure 2) has no effect
because it is a resistance in series with a current source. In
addition to simplifying the system compensation, the input
transconductance amplifier output current is switched by
current steering. The steered output is clamped to reduce
and match any charge injection.
Fig.3 shows a simplified schematic of the reset "gm" amplifier, 8. In the track mode, 0, & 04 are ON and 02 & 0 3 are
OFF. A current of 21 passes through 0" I is summed at "8"
and passes through 0" and is summed with gmVIN. The
current sink can absorb only 31, thus, the current paSSing
through 02 can only be: 2K -gmVIN' The net current into the
hold capacitor node then, is gmVIN (C H=21-(21-g mV1N)' The
hold mode, 02 & 03 are ON while 0, & 04 are OFF. The net
current into the top of 0, is-I until D3turns ON. With 0, OFF,
the bottom of O2 is pulled up with a current I until 0 4 turns
ON, thus D, & D2 are reverse biased by ~0.6V and charge
injection is independent of input level.
A
~::::::t---t==:jl===---! }~~~~ROL
A> B '" PEAK DETECT
A B = PEAK DETECT
Aff~-<>VOUT
R,
VIN+
R,
VOUT
VIN
4
25kfl
poo.o,
lo'"
I
1 NULLRANGE::±Vs(';;)
C ::'.0
2MO
":'"
200
POD..,
-=
1. NULL RANGE
C =:'.0
2MO
I
NOTES:
R
1:0
eH'" 1000pF
4
-15V
R.
Vs+
-15V
NOTES'
R,
Vs-
1k0
=±Vs (~)(R1~1R3)
eH = 1000pF
As
1k0
"':'"
":'"
2. DISCONNECT ftc FROM eH AFTER AMPLIFIER A ADJUSTMENT.
3. REPEAT NULL CIRCUIT FOR RESET BUFFER AMPLIFIER B IF REQUIRED.
"':'"
2. DISCONNECT Rc FROM eH AFTER AMPLIFIER A ADJUSTMENT.
3. REPEAT NULL CIRCUIT FOR RESET BUFFER AMPLIFIER B IF REQUIRED.
RA, Ra AND Rc NOT NECESSARY FOR AMPLIFIER B ADJUSTMENT.
Figure B. Vos Null Circuit for Differential Peak Detector
Figure A. Vos Null Circuit for Unity Gain Positive Peak
Detector
Vs-
R,
GAIN=1+~
R,
R,
v,.
25kO
R,
Vs+
Vs-
>.,....-<~<>VOUT
R.
v,.
VOUT
25kO
4
POD·"
NOTES:
1. NULLRANGE:±Vs(';;)
I
POD·O,
C ::'.0
2Mn
R
1:0
CH,:dOOOpF
-:::-
4
-15V
-15V
I
NOTES'
1 NULL RANGE:
-=
±vs(~)
CH = 1000pF
C ::0,"
2MD
-:::-
R
8
1k0
-:::-
2, DISCONNECT Rc FROM CH AFTER AMPLIFIER A ADJUSTMENT
3 REPEAT NULL CIRCUIT FOR RESET BUFFER AMPLIFIER B IF REQUIRED.
2. DISCONNECT Rc FROM CH AFTER AMPLIFIER A ADJUSTMENT.
3. REPEAT NULL CIRCUIT FOR RESET BUFFER AMPLIFIER B IF REQUIRED
Figure D. Vos Null Circuit for Positive Peak Detector With
Gain
Figure C. Vos Null Circuit for Negative Peak Detector
15-31
1/86, Rev. A
I
---------------l\£MD PKD-ii'i MONOLiTHiC PEAK DETECTOR
PEAK HOLD CAPACITOR RECOMMENDATIONS
The hold capacitor (CH) serves as the peak memory element
and compensating capacitor. Stable operation requires a
minimum value of 1000pF. Larger capacitors may be used to
lower droop rate errors, but acquisition time will increase.
With the comparator in the low state (Vall, the output stage
will be required to sink a current approximately equal to
Vc /R 1'
t.V
ZS
Vc
COMPARATOR INPUT
Zero scale error is internally trimmed for CH = 1000pF. Other
CH values will cause a zero scale shift which can be approximated with the following equation.
(mV) = 1 x 103 (pC) -0.6mV
CH(nF)
The peak hold capacitor should have very high insulation
resistance and low dielectric absorption. For temperatures
below 85°C, a polystyrene capacitor is recommended, while
a Teflon capacitor is recommended for high temperature
environments.
CAPACITOR GUARDING AND GROUND LAYOUT
Ground planes are recommended to minimize ground path
resistance. Separate analog and digital grounds should be
used. The two ground systems are tied together only at the
common system ground. This avoids digital currents returning to the system ground through the analog ground path.
INVERTING
COMPARATOR INPUT
DIGITAL
v-
GNO
Figure 1
Table I.
Ve
The CH terminal (pin 4) is a high-impedance point. To
minimize gain errors and maintain the PKD-01's inherently
low droop rate, guarding Pin 4 as shown in Figure 2 is
recommended.
VOH
R1
R2
5
3.5 2.7K 6.2K
5
5.0 2.7K
15
3.5 4.7K 1.5K
15
5.0 4.7K 2.4K
15
7.5 7.5K 7.5K
15
10.0 7.5K 15K
R2~(V:
V
OH
-1
)
PEAK DETECTOR LOGIC CONTROL (RST, DET)
The transconductance amplifier outputs are controlled by
the digital logic signals RST and DET. The PKD-01 operational mode is selected by steering the current (1 1) through
01 and 02, thus providing high-speed switching and a predictable logic threshold. The logic threshold voltage is 1.4
volts when digital ground is at zero volts.
Other threshold voltages (VTH ) may be selected by applying
the formula:
VTH ~ 1.4V + Digital Ground Potential.
Figure 2. CH terminal (Pin 4) guarding. See text.
COMPARATOR
The comparator output high level (VOH ) is set by external
resistors. It's possible to optimize noise immunity while interfacing to all standard logic families - TTL, DTL, and CMOS.
Figure 1 shows the comparator output with external level
setting resistors. Table I gives typical R1 and R2 values for
common circuit conditions.
For proper operation, digital ground must always be at least
3.5V below the positive supply and 2.5V above the negative
supply. The RST or DET signal must always be at least 2.8V
above the negative supply.
Operating the digital ground at other than zero volts does
infl uence the comparator output low voltage. The VOL level is
referenced to digital ground and will follow any changes in
digital ground potential:
VOL ~ 0.2V + Digital Ground Potential.
The maximum comparator high output voltage (VOH ) should
be limited to:
VoH(maximum) < V+ -2.0V
15-32
1/86, Rev. A
_ _ _ _ _ _ _ _ _ _ _ _-\~ PKD-01 MONOLITHIC PEAK DETECTOR
PKD-01 LOGIC CONTROL
BURN-IN CIRCUIT
56kn
L
5%
, - - - - - -....- - - 0
v+
DET
~
PKD-01
2
+1BV
18kO
OR
AST
36kO
1
5%
5%
DIGITAL
-r12
-r-
4
.!!.....
~
~
GROUND
---------
J
r~
CURRENT TO
CONTROL MODES
13
3
-lav
TYPICAL CIRCUIT CONFIGURATIONS
UNITY GAIN POSITIVE PEAK DETECTOR
v-
v+
DET!RST
14
-+10V
PKO-01
INPUT
1I11111111111I
ov
INPUT
OUTPUT
+10V
-ov
OUTPUT
TIME (50.us/DIV)
CH
~1000PF
POSITIVE PEAK DETECTOR WITH GAIN
v-
v+
10kO
1%
INPUT
INPUT
14
OUTPUT
o-vv'Y'-+-+-+-I
(GAIN", +2)
4O.2kO
1%
RESET o-vv'Y'-+---'t-~
VOLTAGE= + 1V
(RESETS TO - 4V)
OUTPUT
TIME (SOMsiOlV)
OSTo--_ _ _-'
CH
,J,1000PF
15-33
1/86, Rev. A
I
--------------I~ i>KD-Ol MONOLITHIC PEAK DETECTOR
NEGATIVE PEAK DETECTOR WITH GAIN
v-
v+
DET/RST
20kn
_+2V
INPUT
1%
-ov
--5V
10kn 1%
o--NV'-+-......=t-1
INPUT
(GAIN = -2)
OUTPUT
>--t-I~-<)
-+10V
30.1kn
1%
-ov
10k01%
--4V
OUTPUT
--lOV
RESET
VOLTAGE:= -1V
TIME i50,us/DIV)
(RESETS TO - 4V)
'*'
RST
CN
1000pF
UNITY GAIN NEGATIVE PEAK DETECTOR
v+
I
I
INPUT
I I
TTl
I
I
I
10kO
1%
-ov
Y,N
v-
14
PKO-Ol
c>-'MMf-r-----'-I-I
>-..--t---<>--o VOUT
--lOV
-+10V
-ov
OUTPUT
TIME {50,us/01Vl
CN
,*1000PF
ALTERNATE GAIN CONFIGURATION
.,
.,
INPUT O-M~!-+--I
PKD-Ol
>-.-1r-~-o OUTPUT
IF BOTH INPUT SIGNAL (AMPLIFIER A INPUT) AND THE RESET
VOLTAGE (AMPLIFIER B INPUT HAVE THE SAME POSITIVE VOLTAGE GAIN THE GAIN CAN BE SET BY A SINGLE VOL rAGE DIVIDER
FOR BOTH INPUT AMPLIFIERS
..
NOTE
Rl. R2, R3 AND R4> 5kn
vo~i::~ O-M~!-+--I
15-34
1/86, Rev. A
--------------1~ PKD-01 MONOLITHIC PEAK DETECTOR
PEAK-TO-PEAK DETECTOR
PKD01
POSITive
PEAK
DETECTOR
10kO
v,"
10kO
PKD.()1
NEGATIVE
PEAK
DETECTOR
10kO
LOGIC SELECTABLE POSITIVE OR NEGATIVE PEAK DETECTOR
POS/f\iE"i'3
PEAK DETECTOR
+15V
U
105
k"
'6 /15
,.
" I,.
'3
y~~7
';7 L..
R
L-~J
I'
2
r~*
3
•
5
6
L~ OUTPUT
.......!
>----"-
SW-02
*511
'y: -y:
9
~
PKD-Ol
,!
7~
R
6,1
C
INPUT
H
I
PEAK DETECTOR
RESET
73
10aOpF
POLYSTYRENE
"::"
-15V
NOTES
1 DEVICE IS RESET TO 0 VOLTS
2 DETECTED PEAKS ARE PRESENTED AS POSITIVE OUTPUT LEVELS
3 R"'10kn
II
15-35
1/86, Rev. A
-----------------I1fM.!.) 1"1<0-01 MONOLiTHiC PEAK DETECTOR
PEAK READING AID CONVERTER
5.0V
PORT 0
2.7k.l1
pPROCESSOR
INPUT
SIGNAL
BIT 10
PORT 1
RST
RESET
VOLTAGE
POSITIVE PEAK DETECTOR WITH SELECTABLE RESET VOLTAGE
PKO..()l
VIN
0-----------+4-1
>4>--"1""---0
VOUT
ov
OV
13
OV
A1
/l2
A3o-----A4O------'
i'KI5E'f/RST o---I~~-----'
+15V
-15V
Loo
":" GND
15-36
NOTES
LOGIC
RESET VOLTAGE = -1 OV
TRACE 1 = 2V/DIV
TRACE 2 = 5V!DIV
TRACE 3 = 2V/DIV
GNO
1/86, Rev. A
-------------l~ PKD-01 MONOLITHIC PEAK DETECTOR
PROGRAMMABLE LOW FREQUENCY RAMP GENERATOR
AMPLITUDE {
SELECTION
LOGIC
>...,-.. . . . . . .
-0
BUFFERED
RAMP
OUTPUT
RAMP
AMPLITUDE
AST
RAMP
START
Jl
0------'
PULSE
AM~~~~DE
+---,--""'\.
RAMP
START
PULSE
NOTES
1 NEGATIVE SLOPE OF RAMP IS seT BV DAC-080UTPUT CURRENT
2. OAC-OSIS DIGITALLY CONTROLLED CURRENT GENERATOR
THE MAXIMUM FULL SCALE CURRENT MUST BE LESS THAN 0 SmA
15-37
1/86, Rev_ A
Table of Contents 1
Ordering Information 2
Product Assurance Program 3
Industry Cross Reference. 4
Operational Amplifiers 5
Instrumentation Amplifiers 6
Voltage Followers/Buffers 7
Voltage Comparators 8
Matched Transistors 9
Voltage References 10
Digital-to-Analog Converters 11
Analog-to-Digital Converters 12
Analog Switches/Multiplexers 13
Sample-and-Hold Amplifiers 14
Special Functions 15
Communications Products 16
Package Information 17
Sales Offices, Representatives and Distributors 18
JPMI)
COMMUNICATIONS
PRODUCTS
Precision Monolithics Inc.
16-3
Introduction
16-4
RPT-82/RPT-83
peM Repeaters
16-2
COMMUNICATIONS
PRODUCTS
PreCISion MOIlolnhlcs Inc
INTRODUCTION
The PMI repeater amplifiers, RPT-82 and RPT83, are monolithic integrated circuits that
perform all of the necessary active functions for
a PCM repeater. RPT-82 and RPT-83 are very
similar; the primary functional difference is the
incorporation of an automatic-clock-shutdown
circuit in the RPT-83. When the signal into the
RPT -83 becomes too low, the clock amplifier is
automatically shut down to prevent the
transmission of erroneous data. Both repeaters
are fully described and specified in this section
of the catalog.
PCM repeater circuits are used to regenerate
alternate-mark-inversion pulses in PCM carrier
systems operating at the 1.444-2.048 Mega-bitsper-second data rate. Information in a PCM
system is transmitted over cable pairs by the
presence or absence of pulses within specific
time slots. A repeater-circuit amplifies degraded
PCM pulses, sets an output flip-flop, and drives
an output transformer that connects to the PCM
cable pair. In addition, repeater amplifiers can
be used for clock-recovery circuits in high-datarate pulse transmission systems.
I
18-3
RPT-82/RPT-83
PCM
REPEATERS
Precision Monolithics Inc.
FEATURES
•
•
•
•
drive if the incoming signal is below the level where accurate
reconstruction is possible. This prevents noise or cross-talk
from appearing as a valid signal that would be retransmitted.
Automatic ALBO Function
Clock·Shutdown Circuit (RPT·S3)
Low·Power Operation (100mW)
Pin Compatible with XR·C277
PIN CONNECTIONS & ORDERING INFORMATION
GENERAL DESCRIPTION
ALBO
INPUT
The RPT-82/83 are integrated circuits that perform the active
functions required for regenerative PCM repeaters. They can
operate from less than 100kHz to greater than 3MHz. In PCM
systems. information is transmitted by the presence or absence
of bipolar pulses in specified time slots. The RPT-82/83 repeaters automatically adjust gain to optimize signal levels. determine if a pulse is present or not. and retransmit the reconstructed pulses.
PREAMP (
"
INPUTS
14
PREAMP (
ALBO FILTER
2
lC TANK
OSCILLATOR
CONTROL
4
OUTPUTS
RPT-82FQ
RPT-83FQ
12 ) PHASE
ANALOG GND
SHIFT
CAP
6
DIGITAL GND
7
DRIVER
B
OUTPUT
DRIVER
9
OUTPUT
16-PIN HERMETIC DUAL·IN·LINE
(O·Sufflx)
The difference between the RPT-82 and the RPT-83 is that the
RPT-83 contains a clock·shutdown circuit. This shutdown
circuit senses the incoming signal level and disables the clock
RPT-83 SIMPLIFIED SCHEMATIC
OSCILLATOR
CONTROL
LC
veel
TANK
DELAY
13
~
I)R35
01
R36
+--+--H:.~'3
1
J~40
,
QZ2AQZ2B
A3l
7~12
~
!r(Q~~~--::R:::46:--~---::R-::47:--,"",,----~--'fl~
I
R42
~7:9
~'7B
r-,?25A
~25B
~ 7[~05Q'4AQ'4B
I
R41
704
-~3
DE,\AY
12
R43
Q49
I I
R44
R45
~
R32
R34
t
R37
Yr-----t- +_-=:--,
Q1~
rtf
~
02~A-"RiV29'V-<1~R~'~7~--::::::ld-
~
1
021
050
Ra7 ~
DRIVE
QFa
OlSA 0288
010
Q30A 0308
QFBI
Q52
9
R63
Q~""'-'R86
. .~
pcp
R
_'-'
FILTER..............
1
-
Cl
0.8
1.1
V
002
015
V
005
50
p.A
~
Po.
30
50
ns
Z
10
60
ns
Output Pulse Rise-Time
Tos
(Note 2)
Output Pulse Fail-Time
Tol
(Note 2)
Output Pu Ise Width
Pw
At f
Pulse-Width Differential
PwD
(Note 2)
Bipolar Violations at Maximum Density
BV, MAX
0
Bipolar Violations with QuaSI-Random
I nput Pattern
BV A MAX
0
=1.544 MHz
U
ns
324
3
12
ns
15
p.A
V)
-
0
~
U
;
0
CLOCK CIRCUIT
=4 9V (Note 1)
Tank Emitter-Follower Base Current
ITS
Tank Input Impedance
Z,NT
Measured from pin 14to Pin 15
OSCillator Bias Current
losc
VPln 14
OSCillator Injection Current
'INJ
Delay CirCUit Resistor
Rd
Ipln 14. Vp,n 14
=3 9V (losc-I TS ) (Note 1)
Set Vp,n 4 - Vp,n 5 =± 1 4V. Vp,n 14 =3 9V
(I'NJ - losel
Measured from pin 11 or pin 12 to pin 15,
TA
=25°C
4
kO
300
10
30
50
p.A
60
160
190
p.A
3.2
40
48
kO
NOTES:
Vpm 2 =2 5V adjust VPIn 3 until Vpm 4 = Vpm 5
2 Sample tested
I
16-5
1/86, Rev. A
U
II
--------------I~ RPT-821RPT-83 PCM REPEATERS
ELECTRICAL CHARACTERISTICS at VCCI = 4.4V, VCC2 = 6.8V, -40°C:5 TA:5 +85°C, unless otherwise noted.
VPln 6 = Vpln 7 = Vpln 13 = GND. (Continued)
PARAMETER
RPT-82!RPT-83
MIN
TYP
MAX
SYMBOL
CONDITIONS
ALBa Threshold
VTA
and 5, required to activate the Peak Detector
TA = 25°C
Clock Th reshold
VTC
UNITS
MISCELLANEOUS
Differential voltage, measured between pinS 4
135
15
165
V
085
10
12
V
065
075
085
V
TA = 25°C
67
73
78
%
TA = 25°C
46
54
58
%
VOl6
Measured at pin 16,
[Vp• - V~51 = ALBa Threshold
10
17
25
V
ALBO OFF Voltage
VF16
Measured at pin 16 and pin 1
TA = 25°C (Note 1)
75
mV
Minimum ALBO Diode ReSistance
RD MIN
8
0
MaXimum ALBO Diode ReSistance
RD MAX
30
kO
48
dB
DlllerenMI voltage, measured between pins 4
and 5, required to activate the Clock Detector
TA = 25°C
Data Th reshold
VTL
Clock Threshold as % of ALBa Voltage
VTC
VTL
Data Threshold as % of ALBa Voltage
ALBa ON Voltage
ALBO Gain Range
NOTES:
DlllerenMI voltage, measured between pinS
and 5, reqUired to activate the Data Detector
TA = 25°C
4
36
(Note 3)
Am
Sample tested
3 Guaranteed by deSign
1 Vptn 2 = 2 5V, adjust Vpm 3 until VPIn 4 = Vpm 5
FUNCTIONAL DESCRIPTION
Bipolar-pulse transmission, the transmission of alternately
positive and negative pulses, is used on repeater lines to
remove the DC component present in unipolar PCM pulse
trains. This also places the principal energy components in the
0-1.544MHz band, as opposed to the 0-3,088MHz band for
unipolar pulse trains. The absence of a DC component in
bipolar pulse trains permits the repeater to be transformercoupled to the repeater line and helps prevent time-shifting of
the regenerator firing levels with variations in input pulse
density (see Figure 1),
ENERGY SPECTRA OF BIPOLAR AND UNIPOLAR PULSE TRAINS
/
PRINCIPAL FREQUENCY
PRINCIPAL FREQUENCY
COMPONENT = 1 544MHz
~
....
-' "-"'-' '- ..'
/
,
"
UNIPOLAR
PCM TRAIN
COMPONENT'" 772kHz
, ..
,
,.,............
' _'""
,
I
:b~~~:IN
AVERAGE DC
- LEVEL
722kHz
Figure 1
1544MHz
772kHz
3088MHz
FREOUENCY
1 544MHz
3088MHz
FREQUENCY
16-6
1/86, Rev. A
--------------I~ RPT-82/RPT-83 PCM REPEATERS
FUNCTIONAL BLOCK DIAGRAM
current to flow through the emitter follower and D1. In the
RPT-83, a low voltage at the ALBO filter enables the clockshutdown circuit when there is no input signal. The clockshutdown circuit turns off the clock amplifier so that neither the
regenerated clock, nor the strobe outputs, are sent to the flipflops. This prevents the RPT-83 from sending noise or crosstalk out as valid-appearing data pulses when the incoming data
level is too low.
The bipolar-PCM pulse train is transformer-coupled into the
preamplifier as shown in the functional block diagram (Figure
2). The secondary of the input transformer is loaded with the
proper terminating resistor, Rr , to match the line impedance.
One side of the transformer secondary is AC-coupled to ground
by capacitor C1; the other side of the secondary winding is in
series with resistance Rs. Resistor Rs and the RC network RA C A
are AC-coupled to the ALBO input by capacitor C2. The impedance of the ALBO (Automatic Line Build-Out) input to ground
is governed by the amount of current through the ALBO diode.
Rs , in series with RAC A, provides signal attenuation proportional to the current flowing through the ALBO diode. When
minimum current flows through the ALBO diode, C2 is effectively isolated from ground and the input signal attentuation is
minimal. The ALBO diode range of 80 to 30kO provides compensation for line losses of approximately 5dB to 41dB.
The clock detector output locks the oscillator to the input
frequency. The following amplifier stages shape the oscillator
Q
~
Po.
cJ)
Z
o.....
~
;
U
THRESHOLDS AND WAVEFORMS
The preamplifier stage amplifies the input signal and applies it
to the three comparators labeled data detector, clock detector,
and peak detector, respectively. Each comparator provides an
output whenever the signal exceeds the trip point on both
positive and negative pulses. Each comparator trips at a different threshold. The data detector is set to trip at the 54% point;
the clock detector trips at the 73% pOint; and the peak detector
trips at peak amplitude. Thresholds and waveforms are shown
in Figure 3.
~
u
::J
o
u
n
n
n n
n
n
...J LJ L-....J L
..J L...J l---J L
n
n
n
DATA DETECTOR
OUTPUT
CLOCK
DETECTOR
OUTPUT
PEAK
DETECTOR
---1L...JL--.JL. OUTPUT
Current pulses from the peak detector are integrated by the
capaCitor in the ALBO filter. This causes a relatively constant
Figure 3
16-7
1/86, Rev. A
---------------l~ RPT-82/RPT-83 PCM REPEATERS
output and shift it in time. The phase-shift capacitor is selected
to provide additional phase-shift so that the strobe pulses will
occur at the center of the incoming pulses. This provides
optimum timing for determining if a "1" or a "0" is present. A
o-to-30pF capacitor (10pF is typical at 1.544MHz) will optimize
the performance of the complete repeater.
The combination of Rs and RA, in parallel with both CA and the
series impedance ofthe ALBO diode, perform the following two
functions: 1) the automatic-gain-control function previously
described, and 2) the frequency/phase compensation for transmission-line losses.
FREQUENCY/PHASE COMPENSATION
Frequency/phase compensation is desirable for three reasons:
The delayed regenerated clock and the data-detector outputs
drive the input flip-flops and output transistors. The output
transistors are coupled to the transmission line through an
output transformer.
1.
If the bandwidth is wider than necessary, noise and crosstalk outside of the signal-frequency band will appear at the
threshold detectors. Out-of-band signals increase the probability that an incorrect logic decision will be made. These
incorrect logic decisions will increase the bit error rate.
2.
Nonlinear phase-shifts in the transmission line may cause
the signal to be distorted to the extent that bit errors occur.
Phase compensation in the repeater can partly correct for
this problem.
3.
Large phase-shifts in the preamplifier at high frequencies
can cause instability if not compensated for by the feedback network. (See Figures 4 and 5).
DETAILED DESCRIPTION
PREAMPLIFIER
The preamplifier performs two basic functions. The first is to
raise the level of the incoming signal to the correct level to trip
the comparators. The second is to provide frequency/gain
compensation to enhance the signal-to-noise ratio of the
incoming signal. The preamp is designed to be operated in a
near open-loop condition. A limited amount of feedback is used
to control the frequency response. The gain-phase relationship
of the preamp (see Figures 4 and 5) implies that the feedback
network must have 40dB attenuation or more at 20MHz and
above to ensure stability.
CLOCK DETECTOR
The clock detector drives the clock-tank circuit with a pulse
each time that the incoming signal is greater than 73% of the
average peak signal.
ALBO
To enable the preamp to operate open-loop with a wide range of
signal levels, the ALBO diode is connected between the
preamp input and ground. Since the ALBO-diode conductance
is directly proportional to the ALBO-diode current, and the
ALBO diode is driven by the peak detector, any signal in excess
of that required to trip the peak detector will be shunted to
ground through the ALBO diode. This automatic-gain-control
function maintains the signal at the optimum level to operate
the clock and data detectors.
PEAK DETECTOR
The peak detector drives the ALBO buffer and ALBO diode at
the peak of the amplified "1" bits. Whenever the preamp ACsignal-output exceeds about 1.5V peak-to-peak, the ALBO
buffer becomes forward biased and drives current into both the
ALBO diode and the ALBO filter. This closed-loop AGC action
maintains the preamp input signal at about 5mVp-p.
PREAMPLIFIER
FREQUENCY RESPONSE
so
r-
so
t-
40
~
1\
l-
t-
I+tIItI--- Iitttfft
20
10
0.1
r""
60
l-
30
o
PREAMPLIFIER
PHASE RESPONSE
~
10
100
h\ItIt- Ii111fft
300
360
0.1
1.
FREQUENCY (MHz)
1\
10
FREQUENCY (MHz)
Figure 4
100
"
Figure 5
16-8
1/86, Rev. A
- - - - - - - - - - - - - - I l m D RPT-82!RPT-83 PCM REPEATERS
RPT-82/83 IN TYPICAL 1.544MHz T1 REPEATER SYSTEM
ZD2
ZD'
R17
VCC2
6.BV
Vee1
4.4V
DELAY
CAPACITOR
T1
INPUT
TRANSFORMER
.----:-:::::---,
'3n
ALBD
SERIES
IMPEDANCE
RPT-821
RPT-83
R7
3."
C6
R11
10DpF
RB
5.10
II
RS
130U
C9
0.0039
5.5kn
NOTE'
Tl' BOURNS PIN 4260-1520
." 1
556n
T2' BOURNS PIN 4285-2007
ll' BOURNSP/N4265-1199
eOUALIZING
NETWORK
pF
c,o
Figure 6
*O"PF
When the ALBO-diode impedance is high. the ALBO series and
shunt impedances have very little effect. so the unattenuated
Signal is applied to the preamp input with only C1 affecting the
frequency response. When the ALBO-diode input impedance is
reduced by higher signal levels. more of the input signal is
shunted to ground through the ALBO shunt impedance.
APPLICATION
In a typical T1. 1.S44MHz repeater system (see Figure 6). the
repeater is placed in series with a twisted-pair transmission line
at distances of up to approximately 6000 feet. The power is
supplied by a constant current of 60mA that is sent commonmode down the transmission line. This constant current is
separated from the signal by input transformer T1 and output
transformer T2. and is converted to voltages VCC1 and VCC2 by
zener diodes ZD1 and ZD2' The signal is coupled into the input
network by T1. One end of T1 is held at AC ground by C2; and
the other end is terminated by the line-matching resistor R1.
The line-matching resistor is followed with a resistive attenuator
consisting of R2 and R3. and the ALBO series impedance R4.
The two resistors. R2 and R3, isolate the changing ALBO-diode
impedance from the transmission line such that the transmission
line is always correctly terminated. Resistor R4, in series with
the shunt ALBO-diode impedance. determines the amount of
attenuation provided at any given ALBO-diode current.
Capacitor C1 provides a shunt path to ground for signals that
are above the signal frequency.
The ALBO shunt impedance. C3 and RS. changes the input
attenuation vs. frequency such that the system has more high
frequency response at low signal levels. and less high frequency response at high signal levels. This change in bandwidth with signal level is intended to partially compensate for
the increased high-frequency losses that occur in long transmission lines.
The bias feedback components between pin 4 and pin 2. consisting of C7. R7. and C2. operate as a DC self-biasing network.
This C-R-C network prevents AC feedback and allows the
preamp to establish a balanced input-and-output DC bias of 2.S
to 2.6 volts. Resistor R11 provides the DC path for biasing
between pins Sand 3.
16-9
1/86, Rev. A
II
---------------l~ RPT-82/RPT-83 PCM REPEATERS
Resistor R11 and capacitor C6 provide an AC feedback path.
Resistors R10 and R11 act as an AC voltage divider that is
shunted by the variable impedance of the resonant circuit comprised of L2 and C9. This frequency-selective feedback path,
between pin 5 and pin 3, increases preamp gain at approximately 900kHz which further improves the system signal-tonoise ratio. The beneficial effect of the frequency-selective
network is shown in Figure 7. The lower trace is a typical input
signal (all 1's in this example) and the upper trace is the preamp output.
Figure 13 is a scope photograph of the signals as observed at
several locations in the system. All traces are DC coupled and
referenced to zero volts at the bottom graticule line. All signals,
except the output, are displayed at 1-volt-per-division. The output is shown at 2-volts-per-division. The signal is all 1's. The
phase relationships are tYPical for this type of repeater.
2.
The clock-tank at pin 14.
Figures 8 and 9 show the appearance of different preamp inputs
measured at pin 5. Figure 8 is typical of an all1's signal pattern
with very little cross-talk or noise. Figure 9 shows a normal
pattern of random 1's and O's.
3.
The phase-shifted clock at pin 11.
4.
The output signal at pin 8.
Due to the automatic-gain-control action of the ALBO circuitry,
the peak amplitude is held constant for line losses of approximately 5dB to greater than 36dB. These signals are superimposed on a DC level of approximately 2.5V.
The preamp output drives the clock detector (reference Figures
2 and 6) which drives the clock-tank circuitry (L 1, C8, and R12).
The signal at pin 14, a sine wave of 0.2 to 1.0Vp-p (depending
upon the percentage of 1-bits), drives the clock amplifier. The
phase-shift capacitor, C11, provides the additional phase shift
so that this integrated and phase-shifted Signal (Figure 10) will
strobe the output flip-flops at the optimum time to determine if a
1-bit is present. If a 1-bit is present, outputs from the data
detector and the strobe cause the flip-flops to drive alternate
output transistors. This signal is coupled through the output
transformer into the next section of transmission line (see Figure 11, all1's; and Figure 12, a random 1-0 pattern).
Figure 7
The signals shown are:
1.
The preamp output at pin 5.
R13, 14,15, and C12 control ringing and overshoot in the output
waveform.
The fault-locating winding with L3 and R16 is used in long-line
systems to determine which repeater, in a large series of repeaters, has become defective.
The RPT-82 and RPT-83 can be used in a variety of systems over
a wide range of frequencies. The low-frequency response is
limited by the difficulty in maintaining useable Q in the clocktank circuit and by transformer-coupling losses. At high frequencies, the major limitation is the output-pulse rise-and-fall
time.
The preamp is a high-gain, wide-bandwidth linear amplifier.
Analog circuits do not have the noise rejection that is common
with most digital circuits. To obtain best performance, certain
precautions should be observed.
Figure 9
Figure 8
IlfJJ.'
I
11
\ •. ,. .1,. '~I
.
,
! i.,'i
•. •.• •. i.I.,,'.\..
I
; .. ---1---:
,I·'
.•
I,~ill~jl
Figure 11
Figure 10
16-10
1/86, Rev. A
----------------I~ RPT-82/RPT-83 PCM REPEATERS
Figure 12
Figure 13
DATA THRESHOLD
The differential voltage measured between PinS 4 and 5 that is
required to activate the data detector.
Circuit layout techniques used for R F. amplifiers should be
followed. Use of double-sided boards with all unused circuitboard area made Into a ground plane is highly recommended
Keep input and output leads as far apart as possible, and signal
runs as short as possible. Locate the attenuator network and the
ALBO series impedance R4 as close to pin 2 as possible
DIFFERENTIAL OUTPUT VOLTAGE
The difference In voltage between the two outputs with a binary
"1" output of either polarity.
Power supply voltages VCC1 and VCC2 should be bypassed near
pins 10 and 15. A bypass capacitor between the VCC2 connection on T2 and pin 7 is also recommended.
EQUALIZING NETWORK
A network which compensates for the amplitude and phase
response of the cable over the operating bandwidth.
REPEATER DEFINITIONS
LINE BUILD-OUT
The attenuation added to the output of a short line to increase
the total attenuation
ALBO DIODE RESISTANCE
The small-signal resistance of the ALBO diode measured
between pins 1 and 6. The ALBO diode is a diode-connected
transistor whose current-resistance relationship is RD = 26/ID
where RD is the ALBO-diode resistance in ohms and ID is the
ALBO-diode current in mA.
MAXIMUM DENSITY
An input signal pattern consisting of all1's
MINIMUM DENSITY
A repeating signal pattern consisting of two 1's followed by
fourteen zeros
ALBO THRESHOLD
The differential voltage measured between pinS 4 and 5 that is
required to activate the internal peak detector
OUTPUT-PULSE RISE (FALL) TIME
Rise (Fall) time of regenerated pulse Measured from the 10% to
90% points.
AMI
Alternate Mark Inversion. A form of digital signal transmission
where each successive 1-bit is of opposite polarity.
OUTPUT-PULSE-WIDTH DIFFERENTIAL
In a T1 carrier system, a typical pulse width is 324nsec The
pulse-width differential is the difference in pulse width of two
successive outputs.
AUTOMATIC LINE BUILD-OUT
An automatic-gain-control circuit which operates by simulating
a line "build-out" or extension.
PREAMPLIFIER BANDWIDTH
3dB bandwidth of the preamplifier circuit.
BIPOLAR VIOLATION
The transmission of two consecutive pulses of the same polarity.
QRSS
QRSS is QuaSI-Random Signal Source: a signal consisting of
random 1's and O's.
CLOCK THRESHOLD
The differential voltage measu red between pinS 4 and 5 that is
required to activate the clock detector.
II
16-11
1/86, Rev. A
Table of Contents 1
Ordering Information 2
Product Assurance Program 3
Industry Cross Reference 4
Operational Amplifiers 5
Instrumentation Amplifiers 6
Voltage Followers/Buffers 7
Voltage Comparators 8
Matched Transistors 9
Voltage References 10
Digital-to-Analog Converters 11
Analog-to-Digital Converters 12
Analog Switches/Multiplexers 13
Sample-and-Hold Amplifiers 14
Special Functions 15
Communications Products 16
Package Information 17
Sales Offices, Representatives and Distributors 18
PACKAGE
INFORMATION
Precision Monolithics Inc.
PMI Letter
DeSignator
38510
Applicable
Configuration
Package
Description
Package Dimensions H
J
K
Z
Y
a
X
R
V
T
8-Lead
Ceramic
14-Lead
Ceramic
16-Lead
Ceramic
18-Lead
Ceramic
20-Lead
Ceramic
24-Lead
Ceramic
28-Lead
Ceramic
oB'
XB'
RB'
VB'
TB'
A1
17-3
A2
17-3
M'
MB'
04-1
17-4
F'
FB'
DH
17-4
02-1
17-5
06-1
17-5
Ceramic DIPs
DIP
Package Dimensions -
DIP
RC'
08-1
17-6
03-1
17-7
DIP
F4-1
F4-2
17-19
17-19
FH
F1-2
17-19
17-19
F5-1
F5-2
17-20
17-20
F8-1
F8-2
17-20
17-20
Leadless Chip Carriers
C-2
17-21
C-4
17-22
'Special Order Only.
17-8
DIP
14-Lead
Side-Brazed
16-Lead
Side-Brazed
18-Lead
Side-Brazed
20-Lead
Side-Brazed
24-Lead
Side-Brazed
28-Lead
Side-Brazed
Dimensioning Symbols
Side-Brazed DIPs
01-3
17-9
02-3
17-9
06-3
17-10
08-3
17-10
03-3
17-11
The symbols to be used for dimensioning case outlines will
be as listed below. To deSignate the dimension as a diameter.
the lower-case Greek letter cP(phi) will be added in front of the
dimension symbol.
DIP
DIP
A
cPb
b
c
- Body dimensions.
- Terminal lead diameters.
- Terminal lead widths.
- Terminal lead thicknesses.
cPO - Body diameters.
o - Body lengths.
E - Body widths.
e - Terminal lead spacings.
F - Flange dimensions.
k - Index dimensions. length.
L - Terminal lead lengths.
Q - Standoff height. The height from the seating
plane or a reference plane parallel to the
seating plane.
R - Radius dimensions.
S - Distance between terminal leads and the
body end.
O! - Angular dimensions.
DIP
DIP
DIP
17-12
DIP
Epoxy DIPs
8-Lead Epoxy DIP
14-Lead Epoxy DIP
16-Lead Epoxy DIP
18-Lead Epoxy DIP
20-Lead Epoxy DIP
24-Lead Epoxy DIP
17-13
17-13
17-14
17-14
17-15
17-16
Package Dimensions - Cerpacks
L
M
F
N
20-Position
Chip Carrier
28-Position
Chip Carrier
TC'
DIP
Flatpacks
10-Lead Flatpack
10-Lead Flatpack.
Bottom-Brazed
14-Lead Flatpack
14-Lead Flatpack.
Bottom-Brazed
16-Lead Flatpack
16-Lead Flatpack.
Bottom-Brazed
24-Lead Flatpack
24-Lead Flatpack.
Bottom-Brazed
N'
NB'
DIP
Package Dimensions P
P
P
P
P
P
L'
LB'
38510
Applicable
Configuration Page
Package
Description
Package Dimensions -
17-3
DIP
Package Dimensions YB'
Metal Cans
6-Lead TO-78
Metal Can
8-Lead TO-99
Metal Can
10-Lead TO-100
Metal Can
Package Dimensions -
PMI Letter
Designator
Page
10-Lead Cerpack
14-Lead Cerpack
16-Lead Cerpack
24-Lead Cerpack
17-17
17-17
17-18
17-18
Standard lead finish is matte tin/lead. Other lead finishes per
M I L-M-38510 are available on special orders. Standard 883
product meets lead finish requirements per M I L-M-38510.
17-2
PACKAGE
INFORMATION
PreCISIon
Monolithics Inc.
PACKAGE DIMENSIONS - METAL CANS
6 & 8-Lead Can Dimensions
6-Lead TO-78 Metal Can (H-Sufflx)
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.165
0.185
4.19
4.70
1/>0
0.016
0.019
0.41
0.48
0.016
0.021
0.41
0.53
0.335
0.370
8.51
9.40
0.305
0.335
7.75
8.51
0.110
0.160
2.79
4.06
e
0200 BSC
5.08 BSC
e,
0.100 BSC
2.54
L
0.027
0.034
0.69
0.027
0.045
0.69
1.14
0.500
0.750
12.70
19.05
0.250
..
4Reference Plane
n=t:~l4
0.86
Q
0.010
a
45°
",,"·ve".e_l-=_ ''<
1.27
0.045
asc
1.14
0.25
45°
asc
3
INCHES
MAX
MIN
MAX
A
0.165
0.185
4.19
4.70
0.016
0.D19
0.41
0.48
0.016
0.021
0.41
0.53
1/>0
0.335
0.370
8.51
9.40
1/>0,
0.305
0.335
7.75
8.51
0.110
0.160
2.79
4.06
0.230
0.115
10-Lead TO-100 Metal Can (K-Sufflx)
MILLIMETERB
MIN
e
asc
asc
5.84
asc
F
3
1.02
0.040
Reference Plane
0.027
0.034
0.69
0.027
0.045
0.66
1.14
0.500
0.750
12.70
19.05
"
~
L
0.050
el
V-~~
0.250
Q
a
0.010
36° BSC
NOTES
3
292 BSC
r~anae Se.llng Plane
IT fl
"'0"'01
lL +
_Q
6.35
SYMBOL
.D,
tj
2
10-Lead Can Dimensions
rtf ~slO-··,
rtf
A
3
1.02
0.050
8-Lead TO-99 Metal Can (J-Sufflx)
3
asc
0040
F
NOTES
0.66
2
1.27
6.35
0.045
0.25
36° BSC
1.14
3
NOTES:
1. (All leads) I/>b applies between L, and L2.l/>b, applies between L2
and 0.500 (12.70 mm) from the reference plane. Diameter is
uncontrolled In L, and beyond 0.500 (12.70 mm) from the
reference plane
2. Measured from the maximum diameter of the product
3. Leads haVing a maximum dlameterO.019 (0.48 mm) measured In
gaging plane 0.054 (1.37 mm) + 0.001 (0.03 mm) - 0.000
(0.00 mm) below the base plane of the product is Within 0.007
(0.18 mm) olthei r true position relative to a maxi mum width tab.
Icr=
~"'bl
17-3
PACKAGE
INFORMATION
Precision Monolithics Inc.
PACKAGE DIMENSIONS -
CERAMIC DIPS
8-Lead Ceramic Dip
14-Lead Ceramic Dip
1r
IS
see_iSJs
SI
Nole 1
-1
.
t
4
r-E
--1
r-D~
e ~bl Sf c
----7,
TQ~
tf
----1.
A~
Seating
Plane
b-:1
W
INCHES
SYMBOL
MIN
A
MAX
El---'
---Ia
I
see--\\-Note 7
MAX
b
0.014
0.023
0.36
0.58
0.030
0070
0.76
1.78
0.008
0015
0.20
0.38
0.310
E1
0.290
0320
e
0.100 S5e
L
0.125
L1
0150
Q
0.015
5
0.005
ex
0°
A
b1
0.023
036
0.070
0.76
1.78
0008
0.015
0.20
0.38
0.785
D
E
0.220
0.310
737
813
E1
0290
0.320
3.18
0.060
038
0.100 S5e
0125
508
381
L1
0150
1.52
3
Q
0.015
1.35
6
5
6
51
0005
ex
0°
0.13
0°
15°
NOTES:
1. Index area; a notch or a lead one identification mark is located
NOTES
5.08
0.014
4
0.200
MAX
0030
4
5
MILLIMETERS
MIN
0.200
7.87
2.54 S5e
15°
MAX
10.29
0.055
51
MIN
5.59
0.405
0.220
SYMBOL
NOTES
5.08
b1
E
INCHES
MILLIMETERS
MIN
0.200
D
I
058
19.94
4
5.59
7.87
4
7.37
8.13
2.54 S5e
0200
3.18
0.060
038
5
5.08
3.81
0.098
1.52
3
2.49
6
0.13
15°
0°
6
15°
4. This dimension allows for off-center lid, meniscus and glass
overrun
5. The basic lead spacing is 0100 (2.54 mm) between centerlines.
6. Applies to all four corners.
7. Lead centerwhena ISOo . E1 shall be measured at thecenterline
of the leads
adjacent to lead one and IS within the shaded area shown
2. Themlnimum IimltfordlmenSlon b 1 may be 0.023 (0.58 mm) for
all four corner leads only
3. Dimension a shall be measured from the seating plane to the
base plane.
17-4
PACKAGE
INFORMATION
Precision Monolithics Inc.
PACKAGE DIMENSIONS -
CERAMIC DIPS
16-Lead Ceramic Dip
(Q-Suffix)
INCHES
SYMBOL
MIN
MAX
MILLIMETERS
MIN
MAX
0.200
A
18-Lead Ceramic Dip
(X-Suffix)
SYMBOL
5.08
b
0.014
0.023
0.36
058
b,
0.030
0.070
0.76
1.78
c
0.008
0.015
0.20
0.38
0.840
D
INCHES
NOTES
MAX
MAX
0.200
A
2
MILLIMETERS
MIN
NOTES
5.08
b
0.014
0.023
0.36
b,
0.030
0.070
0.76
1.78
0008
0.015
0.20
0.38
0.58
24.38
4
E
0.220
0.310
5.59
7.87
E
0.220
0.310
5.59
7.87
4
E,
0.290
0.320
7.37
8.13
E,
0.290
0.320
7.37
8.13
e
0.100
e
0.100
L
0.125
L
0.125
L,
0.150
L,
0.150
Q
0.015
0.Q15
S
Bse
21.34
MIN
2.54
0.200
3.18
0.060
0.38
0.005
0<
0"
5
5.08
1.52
3
Q
2.03
6
S
6
s,
0.005
0<
0"
0.13
15"
0"
0.960
D
3.81
0.080
s,
Bse
4
15"
Bse
2.54
0.200
3.18
Bse
5.08
3.81
0.060
0.38
0.098
1.52
3
2.49
6
0.13
15"
0"
6
15"
NOTES:
4
1. Index area; a notch or a lead one identification mark is located
adjacent to lead one and IS within the shaded area shown.
2. The minimum limit lor dimension b, may be 0.023 (0.58 mm) lor
alilour corner leads only.
3. Dimension Q shali be measured Irom the seating plane to the
This dimension allows for off·center lid, meniscus and glass
overrun.
5. The basic lead spacing is 0100 (2.54 mm) between centerlines.
6. Applies to all four corners
7. Lead center when a isO°. E, shall be measured at thecenterline
01 the leads.
base plane.
17·5
I
PACKAGE
INFORMATION
Precision Monolithics Inc.
PACKAGE DIMENSIONS - CERAMIC DfPS
20-Lead Ceramic Dip
(R-Sufflx)
INCHES
SYMBOL
MIN
MAX
A
MAX
0.200
0.014
0.023
0.36
b,
0.030
0.070
0.76
1.78
c
0.008
0.015
0.20
0.38
0.58
1.060
4
0.220
0.310
5.59
7.87
0.290
0.320
7.37
8.13
0.100
0.125
L,
0.150
Q
0.015
5
sse
2.54
0.200
3.18
0.005
a
0'
5. The basic lead spacing is 0.100 (2.54 mm) between centerlines.
6. Applies to all four corners.
7. Lead center when a IsO'. E, shall be measured atthecenterline
of the leads.
sse
5.08
3.81
0.060
0.38
1.52
2.03
0.080
5,
overrun.
4
E
L
2
26.92
E,
e
NOTES
5.08
b
0
NOTES:
1. Index area; a notch or a lead one identification mark is located
adjacent to lead one and is within the shaded area shown.
2. The minimum IImitfordlmension b, may be 0.023 (0.58 mm)for
all four corner leads only.
3. Dimension Q shall be measured from the seating plane to the
base plane.
4. This dimension allows for off-center lid, meniscus and glass
MILLIMETERS
MIN
0.13
15'
0'
6
15'
17-6
------ ------
PACKAGE
INFORMATION
Precision Monolithics Inc.
PACKAGE DIMENSIONS -
CERAMIC DIPS
24-Lead Ceramic Dip
(V-Suffix)
1 r-S1
-I I-s
hnnnnnnnnnnr'11
~
13
See
Not. 1'.
I
L!:::!JL
I'
12
LJ LJ LJ LJ LJ
LJ LJ LJ LJ LJI
D
.
j-E---j
Ai...
to~~'
~ --------I +
E,--
.~f.-
INCHES
• f.-
j~" ....,,---I.E
Plane
MIN
MAX
MIN
MAX
A
-
0.225
-
5.72
0.014
0.023
0.38
0.58
b,
0030
0070
076
178
2
c
0.008
0.015
0.20
0.38
-
b
NOTES
-
1.290
-
32.77
4
E
0.500
0.610
12.70
15.49
4
E,
0.590
0.620
14.99
15.75
7
e
0.100
L
0.120
0.200
3.05
5.08
L,
0.150
-
-
3.81
-
-
Q
0.015
0.075
0.38
1.91
3
0
5
5,
a
-
-
esc
2.54
esc
5
-
2.49
6
0.005
-
0.13
-
6
O'
15'
O'
15'
-
0.098
-I\--'
NOTES:
1. Index area; a notch or a lead one identification mark Is located
adjacent to lead one and is within the shaded area shown.
2. The minimum limitfordimension b, may be 0.023 (0.58 mm) for
all four corner leads only.
3. Dimension Q shall be measured from the seating plane to the
base plane.
4. This dimension allows for off-center lid, meniscus and glass
overrun.
5. The baSic lead spacing Is 0.100 (2.54 mm) between centerlines.
6. Applies to all four corners.
7. Lead center when a Is 0'. E, shall be measured althe centerline
of the leads.
MILLIMETERS
SYMBOL
Note 7
Z
0.....
~2
Z
.....
~
~
~
~
17-7
-
- ---- --------
PACKAGE
INFORMATION
PrecIsion Monolithics Inc.
PACKAGE DIMENSIONS -
CERAMIC DIPS
28-Lead Ceramic Dip
(T-Sufflx)
-I r-
Sl
n n n n n n n n n n n n n r+j,
se~-....
is
15
l\
Note 1
t
J::!.jLJLJLJLJLJLJO 0
I'
DO D
14
o
LJ.I
r-E~
D
TQ~~
tc
----- --I ~b1---r3: L"---1
b_ll_
INCHES
SYMBOL
Seeling
Plane
-leI--
MIN
MAX
NOTES
MAX
A
-
0.225
-
5.72
b
0.014
0.023
0.36
0.58
b,
0.030
0.070
0.76
1.78
2
c
0.006
0.D15
0.20
0.38
D
-
1.490
-
-
37.85
4
-
-
E
0.500
0.610
12.70
15.49
4
E,
0.590
0.620
14.99
15.75
7
e
0.100 BSC
L
0.120
0.200
3.05
5.08
-
L,
0.150
3.81
-
-
Q
0.015
0.075
0.38
1.91
3
S
-
0.098
-
2.49
8
S,
0005
-
6
CO<
O·
15·
-
2.54 BSC
-
15·
0.13
O·
See
Note 7
-\\-e
NOTES:
1. Index area; a notch or a lead one Identification mark Is located
adJacent to lead one and Is within the shaded area shown.
2. The minimum IImltfordlmenslon b, maybeO.023 (0.58 mm) for
all four corner leads only.
3. Dimension Q shall be measured from the seating plane to the
base plane.
4. ThIS dImenSIon allows lor oil-center lId, meniscus and glass
MILLIMETERS
MIN
----{a
overrun.
5. The basic lead spacing IsO.loo (2.54 mm) between centerllnes.
6. Applies to all four corners.
7. Lead center when CO< IsO·. E, shall be measured allhecenterline
of the leads.
5
17-8
PACKAGE
INFORMATION
Precision Monolithics Inc.
PACKAGE DIMENSIONS - SIDE-BRAZED DIPS
14-Lead Side-Brazed Dip
(VB-Suffix)
INCHES
SYMBOL
MIN
A
MAX
16-Lead Side-Brazed Dip
(OB-Sufflx)
MILLIMETERS
MIN
MAX
0.200
INCHES
SYMBOL
NOTES
5.08
MIN
A
MAX
MILLIMETERS
MIN
0.200
MAX
b
0.014
0.023
0.36
0.58
b
0.014
0.023
0.36
b,
0.030
0.070
0.76
1.78
b,
0.030
0.070
0.76
1.78
0.008
0.D15
0.20
0.38
0.008
0.015
0.20
0.38
0
0.785
E
0.220
0.310
E,
0.290
0.320
0.100 BSC
0.125
L,
0.150
a
0.D15
S
5.59
7.37
2.54
0.200
3.18
0005
a
0'
4
0
7.87
4
E
0.220
0.310
E,
0.290
0.320
e
0100 BSC
8.13
esc
5.08
3.81
0.060
0.38
0.098
S,
19.94
1.52
2.49
0.13
15'
0'
0.840
L
0.125
L,
0.150
a
0015
S
6
S,
0.005
a
0'
15'
NOTES:
Index area; a notch or a lead one identification mark is located
adjacent to lead one and is within the shaded area shown.
2. The minimum limit for dimension b, may be 0.023 (0 58 mm) for
all four corner leads only.
shall be measured from the seating plane to the
3. Dimension
base plane.
4
0.58
21.34
4
5.59
7.87
4
7.37
8.13
254 BSC
0.200
3.18
5.08
3.81
0.060
0.38
0.080
6
NOTES
5.08
1.52
2.03
0.13
15'
0'
3
6
6
15'
This dimension allows for off-center lid, meniscus and glass
overrun
5 The basIc lead spacing isO.100 (2 54 mm) between centerlmes.
6. Applies to all four corners
7. Lead center when Q' isO° E1 shall be measured atthecenterline
of the leads
a
17-9
PACKAGE
INFORMATION
Precision Monolithics Inc.
PACKAGE DIMENSIONS - SIDE-BRAZED DIPS
18-Lead Side-Brazed Dip
(XB-Sufflx)
-lr
-I
Sl
r-
20-Lead Side-Brazed Dip
(RB-Sufflx)
1r
s
A
:If
rr----3 r .~~
I·
0
I-E=1
·1
'1~~"
=r-
OJ
A
c
L
0
s
"'jJj IOU; 11 iU
j~
~ JUrn J1=r=;'
~t~-r-~ Q-~~
b---l~--I
1-,,-1
INCHES
r-
NO:~iS~O~]
N~~{)D]
Q
-1
Sl
~e
_
INCHES
MILLIMETERS
bl
Sealing
Plane
--f.1
t=E=:j
c
I--E--I
1
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
SYMBOL
MIN
MAX
MIN
MAX
A
-
0.200
-
5.08
-
A
-
0.200
-
5.08
-
0.58
-
b
0.014
0.023
0.36
0.58
-
b
NOTES
b,
0.014
0.023
0.36
0.030
0.070
0.76
1.78
2
b,
0.030
0.070
0.76
1.78
2
c
0.008
0.015
0.20
0.38
-
c
0.008
0.015
0.20
0.38
4
0.960
-
24.38
4
D
1.060
-
26.92
E
0.220
0.310
5.59
7.87
4
E
0.220
0.310
5.59
7.87
4
E,
0.290
0.320
7.37
8.13
7
E,
0.290
0.320
7.37
8.13
7
e
0.100
5
e
0.100
L
0.125
5.08
-
L
0.125
5.08
L,
0.150
-
0
0.Q15
D
S
-
-
S,
0.005
ex
0'
sse
2.54
0.200
-
3.18
sse
-
3.81
-
-
L,
0.150
0.060
0.38
1.5~
3
0
0.015
0.098
-
2.49
6
S
0.13
-
6
S,
0.005
15'
-
ex
0'
15'
0'
NOTES:
1. Index area; a notch or a lead one identification mark is located
adjacent to lead one and is within the shaded area shown.
2. The minimum limit for dimension b , may be 0.023 (0.58 mm) for
all four corner leads only.
3. Dimension 0 shall be measured from the seating plane to the
base plane.
-
sse
2.54
0.200
-
3.18
sse
5
3.81
-
0.060
0.38
1.52
3
0.060
-
2.03
6
0.13
-
6
15'
-
15'
0'
4. This dimension allows for off-center lid, meniscus and glass
overrun.
5. The basic lead spacing is 0.100 (2.54 mm) between centerlines.
6. Applies to all four corners.
7. Lead center when ex is 0'. E, shall be measured atthecenterline
of the leads.
17·10
PACKAGE
INFORMATION
Precision Monolithics Inc.
PACKAGE DIMENSIONS - SIDE-BRAZED DIPS
24-Lead Side-Brazed Dip
(VB-Suffix)
INCHES
SYMBOL
MIN
MAX
b
0.014
bl
0.030
c
0.008
A
MAX
0.023
0.36
0.58
0.070
0.76
1.78
O.ot5
020
0.225
D
0.38
4
0.500
0.610
12.70
1549
0.590
0620
14.99
1575
0200
3.05
0.075
0.38
0120
Ll
0.150
a
0.015
S
esc
2.54
0.005
0<
0"
esc
5. The basIc lead spacing Is 0.100 (2.54 mm) batwean centerllnes.
6. Applies to all four corners.
Lead center when 0< IsO·. El shall be measuredatthecenterllne
of the leads.
5
5.08
3.81
0.098
SI
overrun.
4
E
0.100
a
32.77
El
e
NOTES
5.72
1.290
L
NOTES:
1. Index area; a notch or a lead one identification mark Is located
adjacent to lead one and Is within the shaded area shown.
2. The minimum lImit fordlmension bl may be 0.023 (0.58 mm) for
all four corner leads only.
3. DimenSIon shall be measured from the seating plane to the
base plane.
4. ThIS dImension allows for off-center lid, meniscus and glass
MILLIMETERS
MIN
1.91
3
6
2.49
0.13
15·
O·
6
15·
I
17-11
~
-
~~----~----
PACKAGE
INFORMATION
Precision Monolithics Inc.
PACKAGE DIMENSIONS - SIDE-BRAZED DIPS
28-Lead Side-Brazed Dip
(TB-Suffix)
Ii
I
sl
1"~:', '
D
)""<,,
See
Note
,;;~"
t.:::::J
oJ
is
15
14
'I
0
t=E=:=j
-t=.
I
~'
:::;~~~"l'
'
~El~
INCHES
SYMBOL
MIN
MIN
MAX
NOTES
0,225
-
5.72
-
b
0,014
0,023
0,36
0,58
-
b1
0,030
0,070
0,76
1.78
2
c
0,008
0.D15
0,20
0,38
-
-
37.85
4
A
D
-
-
1,490
E
0,500
0,610
12,70
15.49
4
E1
0,590
0,620
14,99
15,75
7
e
0,100 BSe
L
0,120
0,200
305
508
-
L1
0.150
Q
0.015
S
-
Sl
0.005
a
0°
NOTES:
1, Indexarea; a notch is ora lead one identification mark Is located
adjacent to lead one and is within the shaded area shown,
2, The minimum limitlor dimension b1 may be 0,023 (0,58 mm) for
all four corner leads only.
3, Dimension Q shall be measured from the seating plane to the
base plane,
4. This dimension allows for off-center lid, meniscus and glass
overrun.
5, The basic lead spacing isO,100 (2.54 mm) between centerlines,
6, Applies to all four corners,
7, Lead center when a isOo , E1 shall be measured at the centerline
of the leads,
MILLIMETERS
MAX
2,54 BSe
-
5
3.81
-
-
0.075
0.38
1.91
3
0.098
-
2.49
6
0.13
-
6
15°
-
15°
0°
17-12
PACKAGE
INFORMATION
Prt'CJSiOll Monolithics Inc
PACKAGE DIMENSIONS -
EPOXY DIPS
a-Lead Epoxy Dip
(P-Sufflx)
14-Lead Epoxy Dip
(P-Sufflx)
f4---D-----j
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.148
0.152
3.76
386
INCHES
NOTES
SYMBOL
MAX
MIN
A
MILLIMETERS
MIN
MAX
0.200
b
0.016
0.020
0.406
0.508
b
0.014
0.023
0.36
b1
0.058
0.062
1.47
1.58
b1
0.030
0.070
0.76
1.78
c
0.008
0.012
0.203
0.304
c
0.008
0.015
0.20
0.38
D
0.370
0.382
947
9.70
D
0748
0.754
18.99
19.1
I:
0.246
0.254
6.25
6.45
I:
0.220
0.310
5.59
7.87
1:1
0.298
1:1
0.290
0.320
7.37
e
0100
0.302
esc
7.57
2.54
7.67
2
esc
0.100
esc
2.54
0.58
8.13
L
0128
0132
3.25
3.35
L
0125
0.146
0.152
3.76
3.86
L1
0.150
a
0.020 TYP
a
0.015
0.060
0.38
1.52
15·
Q
O·
15·
O·
15·
Q
o·
0.508 TYP
15·
O·
NOTES:
318
2
esc
L1
0200
NOTES
5.08
5.08
3.81
NOTES:
Minor changes In dimensions may occur without advance
1. Minor changes in dimensions may occur without advance
notice.
notice.
2. DimenSion "1:1' to center of leads when formed parallel.
2. Dimension "1:1' to center of leads when formed parallel.
Z
0
~
0~
Z
~
~
~
~
II
17-13
PACKAGE
INFORMATION
PrecisioJl Monolithics Inc.
PACKAGE DIMENSIONS - EPOXY DIPS
16-Lead Epoxy Dip
(P-Sufflx)
18-Lead Epoxy Dip
(P-Suffix)
A
L
INCHES
SYMBOL
MIN
MAX
A
MILLIMETERS
MIN
MAX
0.200
INCHES
NOTES
SYMBOL
MIN
MAX
A
5.08
MILLIMETERS
MIN
MAX
0.200
b
0.014
0.023
0.38
0.58
b
0.014
0.023
0.38
b1
0.030
0.070
0.76
178
b1
0.030
0.070
0.76
1.78
c
0.008
0,015
0.20
0.38
0.008
0.015
0.20
0.38
D
0.748
0754
18.99
19.1
D
0898
0.904
2281
22.91
E
0.220
0.310
5.59
7.87
E
0.220
0.310
5.59
7.87
E1
0.290
0.320
7.37
8.13
E1
0.290
0.320
7.37
8.13
e
0.100
e
0100
esc
254
L
0.125
L1
0.150
0.200
3.18
Q
0.015
0.060
0.38
a
O·
15·
O·
2
esc
esc
2.54
0.58
L
0.125
0.150
1.52
Q
0.015
0.060
0.38
1.52
15·
a
O·
15·
O·
15·
NOTES:
1. Minor changes .n dimensions may occur without advance
notice.
2. Dimension "E( to center of leads when formed parallel.
0.200
318
2
esc
L1
5.05
3.81
NOTES
5.08
506
3.81
NOTES:
1. Minor changes in dimensions may occur without advance
notice.
2. Dimension "E( to center of leads when formed parallel.
17-14
PACKAGE
INFORMATION
Precision MODolithics Inc.
PACKAGE DIMENSIONS -
EPOXY DIPS
20-Lead Epoxy Dip
(P-Suffix)
I: :::::::::II
INCHES
SYMBOL
MIN
MAX
MAX
b
0.014
0.023
0.36
0.58
b1
0.030
0.070
0.76
1.78
0.008
0.Q15
0.20
0.38
26.24
0.255
A
1.029
1.035
26.14
E
0.220
0.310
5.59
7.87
E1
0.290
0.320
7.37
8.13
e
0.100
2.54
0.200
1. Minor changes in dimensions may occur without advance
notice.
2. Dimension "E1" to center of leads when formed parallel.
NOTES
5.08
0
esc
NOTES:
MILLIMETERS
MIN
318
z
o
esc
L
0.125
L1
0.150
Q
0.015
0.060
0.38
1.52
a
O·
15·
O·
15·
~2
508
3.81
....z
17-15
PACKAGE
INFORMATION
Precision Monolithics Inc.
PACKAGE DIMENSIONS -
EPOXY DIPS
24-Lead Epoxy Dip
(P-Sufflx)
24
13
1
~~~l
I'
0
'I
Ir=E1~
:±;~ti'-1~
INCHES
SYMBOL
MAX
MIN
A
MAX
0.225
b
0.014
0.023
0.36
0.030
0.070
0.76
1.78
0.008
0015
0.20
0.38
1.248
1254
31.7
31.8
E
0.538
0.542
13.67
13.77
E,
0.598
0.602
15.19
e
0.100
2.54
0.200
notice.
3.18
2. Dimension "E{ to center of leads when formed parallel.
0.58
0
0.125
1. Minor changes in dimensions may occur without advance
NOTES
5.08
b,
sse
NOTES:
MILLIMETERS
MIN
15.29
sse
5.08
L,
0.150
Q
O.Q1S
0.060
0.38
1.52
C/
0°
15°
0°
15°
3.81
17·16
PACKAGE
INFORMATION
Precision M01lo1ithics Inc
PACKAGE DIMENSIONS - CERPACKS
10-Lead Cerpack
(L-Sufflx)
k
14-Lead Cerpack
(M-Suffix)
S••
IT=~!~N°~·~E5f
.~~
~, ~'~601· ~~+T
~t!
Ll:
ff
AQ
I
.:rjt
~Ll:~~~~~
~F==L====;.14cI
11
~E
~c
I
I-E--I_L~l
----1·11---·-
AQ
INCHES
MIN
MAX
MIN
MAX
A
0.030
0.085
076
2.16
0.010
0,019
0.25
048
0.003
0.006
0.08
0.15
0.290
D
0.240
0.008
7.37
0.260
6.10
0.015
0.20
0.38
0.050 SSC
INCHES
MILLIMETERS
SYMBOL
E
L
1.27
NOTES
3
esc
MIN
MAX
MIN
MAX
A
0030
0085
0.76
2.16
0.010
0.019
025
048
0.003
0006
0.08
015
0.260
6.10
660
0,015
0.20
0.38
0.280
D
6.60
MILLIMETERS
SYMBOL
E
0.240
0050
4
0.008
esc
7.11
1.27
ssc
L
0.250
0.370
6.35
9.40
L
0.250
0.370
6.35
9.40
0.010
0.040
0.25
1.02
Q
0.010
0.040
0.25
1.02
1.14
S,
0005
0.13
S,
0.004
0.10
0.045
S,
0.005
0.13
5,6
NOTES:
Index Brea; a notch or a lead one identification mark IS located
adjacent to lead one and shall be located within the shaded area
shown. Alternatively, a tab (dim. k) may be used to Identify lead
one. This tab may be located on either side as shown.
2. Dimension Q shall be measured at the point of eXit of the lead
from the body.
1.
3
4
Q
S
NOTES
8
5,6
6. Dimension S, (See 40.3) may be 0.000 (0.00 mm) if corner leads
7.
bend toward the cavity of the package Within one lead's width
from the pOint of entry of the lead Into body.
Optional configuration If thiS configuration is used, no organiC
or polymeric matenals are molded to the bottom of the package
to cover the leads.
3. ThIS dimension allows for off-center lid, meniscus and glass
OptIonal, see note 1 If a lead one identification mark is used in
addition to this tab, the minimum limit of dimension k does not
overrun
apply.
4. The basic lead spacing IS 0.050 (1.27 mm) between centerlines.
5. Applies to a/l four corners
II
17-17
PACKAGE
INFORMATION
Precision MOllolithics Inc
PACKAGE DIMENSIONS - CERPACKS
24-Lead Cerpack
(N-Sufflx)
16-Lead Cerpack
(F-Suffix)
See Note
S2 L
b
~~
I
s[f
INCHES
MAX
MIN
MAX
~E-1-L-11
A
0.045
0.085
1.14
2.16
0.015
0.019
0.38
0.48
0.003
0.006
0.08
0.15
D
E
0.440
0.245
0.050
0.008
11.18
0.285
6.22
0.015
0.20
0.38
sse
1.27
0.250
0.370
6.35
9.40
0.010
0.040
0.23
1.02
S,
0.045
0.005
1.14
0.13
MIN
MAX
MIN
MAX
A
0.045
0.090
1.14
2.29
0.015
0.019
0.38
0.48
c
0.003
0.006
0.08
D
3
sse
L
MILLIMETERS
SYMBOL
7.24
Q
S
INCHES
NOTES
-.lc
I
I
tt
MILLIMETERS
MIN
1
II II
AQ
SYMBOL
1
24
1213
4
!-E-f--L--!f
=-r
III
e~'
-1c
I
1ark
0.15
10.92
0.430
E
0.245
e
0.050
0.008
0.285
6.22
0.Q15
0.20
0.38
sse
1.27
NOTES
3
7.24
sse
4
0.250
0.370
6.35
9.40
Q
0.010
0040
0.25
1.02
5
S
0.005
0.13
5,6
S2
0.004
0.10
5,6
NOTES:
1.
Index area; a notch or a lead one identification mark is located
adjacent to lead one and is located within the shaded area
shown. Alternatively, a tab (dim. k) may be used to identify lead
one. This tab may be located on either side as show~.
2. Dimension Q shall be measured at the point of exit of the lead
from the body.
3. This dimension allows for off~center lid, meniscus and glass
overrun.
4. The basic lead spaCing is 0.050 (1.27 mm) between centerlines.
6.
Dimension S, (See 40.3) may be 0.000 (0.00 mm) if corner leads
bend toward the cavity of the package within one lead's width
from the pOint of entry of the lead into body.
7.
Optional configuration. If this configuratIOn is used, no organic
or polymeric materials are molded to the bottom of the package
to cover the leads.
Optional, see note 1. If a lead one identification mark is used in
addition to this tab, the minimum limit of dimension k does not
apply.
8
5. Applies to all four corners.
17-18
PACKAGE
INFORMATION
Precision Monolithics Inc.
PACKAGE DIMENSIONS - FLATPACKS
14-Lead Flatpack (M-Suffix)
10-Lead Flatpack (L-Suffix)
See
k
NOle1':dre
L
1
sl L
7 8
t
Bottom-Brazed (MB-Suffix)
Bottom-Brazed (LB-Suffix)
LJ::_ _I~~I~
11 NoteSee7 7
1
--1.--P I---
A Q
INCHES
MIN
MAX
MIN
MAX
A
0.030
0.085
0.76
2.16
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.030
0.085
0.76
216
0.010
0.019
0.25
0.48
b
0.010
0.019
0.25
0.48
0.006
0.08
0.15
c
0.003
0.006
0.08
0.15
7.37
D
6.60
E
610
6.60
0.290
0.240
0.260
6.10
0280
E,
7.11
0.125
3.18
0.030
0.76
0.050 B5e
1.27
3
0.240
4
0.260
0.280
E,
0.20
038
8
E3
0.030
0.76
e
0050 B5e
127 B5e
0.015
L
0250
0.370
635
940
Q
0010
0.040
0.25
1.02
0.20
0.38
L
0.250
0.370
6.35
9.40
Q
0.010
0.040
0.25
1.02
1.14
5,
0.005
013
52
0.004
010
0.045
0.005
0.13
5,6
NOTES:
1. Index area; a notch or a lead one identification mark is located
adjacent to lead one and shall be located within the shaded area
shown. Alternatively, a tab (dim. k) may be used to identify lead
one. This tab may be located on Bither side as shown
2. Dimension Q shall be measured at the point of exit of the lead
from the body.
3. This dimension allows for off-center lid, meniscus and glass
overrun.
4. The basic lead spacing is 0.050 (1.27 mm) between centerlines.
5. Applies to all four corners.
4
0008
0.Q15
5
3
3
318
8
NOTES
7.11
0125
E2
esc
7.11
0280
0.008
5,
I-r
-I
0.003
D
E
NOTES
L
E3 E2 E3
INCHES
MILLIMETERS
SYMBOL
1
~
5,6
DimenSIOn 5, (See 40 3) may be 0.000 (O.OOmm) if corner leads
bend toward the cavity of the package wlthm one lead's width
from the point of entry of the lead mto body
7. Optional configuration If this configuration IS used, no organic
or polymeric matenals are molded to the bottom of the package
to cover the leads.
Optional, see note 1. If a lead one Identification mark IS used in
addition to this tab, the minimum limit of dimenSion k does not
apply.
6.
17-19
II
PACKAGE
INFORMATION
Precision Monolithics Inc.
PACKAGE DIMENSIONS - FLATPACKS
16-Lead Flatpack (F-Sufflx)
24-Lead Flatpack (N-Suffix)
See Note 1
k
See Note 1
b
=l"f
Tk
e
S2
f1
16
L
e~
D
T
~~11
9~
sL
f
=-r
L
1
s[f
BoUom-Brazed (FB-Suffix)
1
1213
Bottom-Brazed (NB-Suffix)
1r-~I-
4------+1" -----11
~-
11
See
A Q Note7
E3
INCHES
SYMBOL
A
MAX
MIN
MAX
0.045
0.085
1.14
2.16
A
b
b
0,015
0.019
0.38
0.48
c
0.003
0.006
0.08
0.15
0
E
0.440
0.245
0.285
E,
0.130
E3
0.030
0.050
6.22
SYMBOL
3
D
3
E,
E
7.24
7.75
0.76
sse
1.27
0,015
0.250
0.010
sse
MILLIMETERS
MIN
MAX
MIN
MAX
0.045
0.090
1.14
2.29
0.015
0.019
0.38
0.48
0.003
0.006
0.08
0.245
0.285
10.92
7.75
0.125
E3
0.030
0.76
sse
4
0050
8
0.008
0,015
1.27
0.370
6.35
9.40
0.040
0.25
1.02
6.35
9.40
0.250
0.23
1.02
2
Q
0.010
1.14
5
S
0.005
0.13
5,6
S2
0.004
0.10
6.
shown. Alternatively, a tab (dim. k) may be used to identify lead
one. This tab may be located on either side as shown.
2. Dimension Q shall be measured at the point of exit of the lead
from the body.
3. This dimension allows for off·center lid, meniscus and glass
7.
8
overrun.
4. The basic lead spacing is 0.050 (1.27 mm) between centerlines.
5. Applies to all four corners.
17·20
4
0.38
0.040
adjacent to lead one and is located within the shaded area
sse
0.20
0.370
NOTES:
1. Index area; a notch or a lead one identification mark is located
3
3.18
0.38
0.13
7.24
6.22
0.305
E2
NOTES
0.15
0.430
0.20
0.045
0.005
NOTES
3.30
0.008
S
S,
11.18
0.305
E2
Q
INCHES
MILLIMETERS
MIN
5,6
Dimension S, (See 40.3) may be 0.000 (0.00 mm) if corner leads
bend toward the cavity of the package within one lead's width
from the pOint of entry of the lead into body.
Optional configuration. If this configuration is used, no organic
or polymeric materials are molded to the bottom of the package
to cover the leads.
Optional, see note 1. If a lead one identification mark is used in
addition to this tab, the minimum limit of dimension k does not
apply.
PACKAGE
INFORMATION
Precision MOllolithics Inc.
PACKAGE DIMENSIONS - LEADLESS CHIP CARRIERS
20-Posltlon Chip Carrier
(RC-Sufflx)
Top View
INCHES
Side View
Bottom View
NOTES:
MILLIMETERS
1. A minimum clearance of 0.Q15" (0.381 mm) is maintained
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.064
0.100
1.63
2.54
5
Al
0.054
0.088
1.37
2.24
2. Electrical connection is required on plane 1. Metallization is
optional on plane 2. However, il plane 2 is metallized it must be
Bl
0.022
0.028
0.56
0.71
2
3. A minimum clearance of 0.020" (0.508 mm) is maintained
0
0.342
0.358
8.69
9.09
01
0.075 REF
1.91 REF
O2
0.200 REF
5.08 REF
03
0.100 REF
2.54 REF
0.358
04
05
0.150 BSe
E
0.342
between corner terminals.
electrically connected.
4.
9.09
5.
6.
3
3.81 BSe
0.358
8.69
El
0.075 REF
1.91 REF
E2
0.200 REF
5.08 REF
E3
0.100 REF
7.
9.09
1.27 BSe
0.38
~
I-Ll
9.09
0.050 BSe
Z
0
.....
0>.Lo
Z
.....
1.91 REF
0.358
E4
between overall dimensions D4 X E4 and all other features,
including metallization, chamfers and edges.
Non-electrical features for No.1 terminal identification, optical
orientation or handling purposes shall be within the shaded
area shown on plane 2.
Dimension A controls the overall package thickness.
Length of pad metallization may increase only toward package
periphery.
When space is available, the index corner may be metallized on
either or both planes 1 and 2. The package edge at the index
corner shall not be metallized.
el
0.015
Ll
0.045
0.055
1.14
L2
0.077
0.093
1.96
2.36
R
0.007
0.011
0.18
028
~
~
Poi
1.40
4
17-21
PACKAGE
INFORMATION
Precision Monolithics Inc.
PACKAGE DIMENSIONS - LEADLESS CHIP CARRIERS
28-Positlon Chip Carrier
(TC-Sufflx)
Side View
Top View
INCHES
SYMBOL
MIN
MAX
MAX
A
0.064
0.100
1.63
2.54
A1
0.054
0088
1.37
2.24
B1
0.022
0.028
0.56
0.71
0
0.442
0.458
11.23
11.63
01
0.Q75 REF
1.91 REF
O2
0.300 REF
7.62 REF
03
0.150 REF
04
0.200 BSC
optional on plane 2. However, if plane 2 is metallized it must be
electrically connected.
3. A minimum clearance of 0.020" (0.508 mm) is maintained
between overall dimensions 04 X E4 and all other features,
Including metallization, chamfers and edges.
4 Non-electrical features for No.1 terminal identification, optical
orientation or handling purposes shall be within the shaded
area shown on plane 2.
5. Dimension A controls the overall package thickness.
6. Length of pad metallization may Increase only toward package
periphery.
When space IS available, the Index corner may be metallized on
e.ther or both planes 1 and 2. The package edge at the index
corner shall not be metallized
11.63
E
0.442
0.Q75 REF
E2
0.300 REF
7.62 REF
E3
0150 REF
3.81 REF
e
1. A minimum clearance of 0.015" (0.381 mm) is maintained
between corner terminals.
2. Electrical connection is required on plane 1. Metallization is
508 BSC
E1
0.458
11.23
1163
191 REF
0.458
E4
NOTES
3.81 REF
0.458
05
NOTES:
MILLIMETERS
MIN
11.63
3
1.27
0.050
e1
0.015
L1
0.045
0055
1.14
1.40
L2
0077
0.093
1.96
2.36
R
0007
0011
0.18
028
BollomVlew
0.38
17-22
Table of Contents 1
Ordering Information 2
Product Assurance Program 3
Industry Cross Reference 4
Operational Amplifiers 5
Instrurp.entation Amplifiers .6
Voltage Followers/Buffers 7
Voltage Comparators 8
Matched Transistors 9
Voltage References 10
Digital-to-Analog Converters 11
Analog-to-Digital Converters 12
Analog Switches/Multiplexers 13
Sample-and -Hold Amplifiers 14
Special Functions 15
Communications Products 16
Package Information 17
Sales Offices, Representatives and Distributors 18
..
-
- .-. . . .
...
.--.--
~.---
SALES OFFICES
REPRESENTATIVES
PI t.'C 1 .... 1011 MOllOhtll1C ....
Inc
NORTH AMERICA
COLORADO
GEORGIA
MAINE
ATLANTA
EMA
Contact Boston. MA Office
620 ColOnial Park Or
Roswell, GA 30075-3746
MARYLAND
Santa Clar., CA 95052-8020
BOULDER
FRONT RANGE MARKETING
3100 Arapahoe Ave. SUite 404
Boulder, CO 80303-1082
(303) 443-4780 TWX 910-940-3442
(408) 727-9222 TWX 910-338-0218
TLX 172 070
LITTLETON
PMI SALES OFFICE
ALABAMA
7488 W Roxbury PI
Littleton, CO 80123-4738
CORPORATE
HEADQUARTERS
PMI
1500 Space Park Drive
P.O. Box 58020
HUNTSVILLE
EMA
309 Jordan Lane, Northwest
Huntsville, AL 35805-2621
(205) 830-4030. (800) 533-2920
TWX 810-726-2110
(303)979-8533
CONNECTICUT
UNIONVILLE
PMI SALES OFFICE
PO Box 43
SCOTTSDALE
PMI SALES OFFICE
8526 E Monterey Way
Scottsdale. AZ 85251-5926
(602) 941-1946
HAWAII
26 W Pennsylvania Ave
Baltimore, MO 21204~5058
Contact Los Angeles, CA OffIce
(301)296-2444
IDAHO
MASSACHUSETTS
Contact Bellevue, WA Office
BOSTON
PMI SALES OFFICE
209 W Central SI
CHICAGO
PMI SALES OFFICE
Natick, MA 01760-3716
(817)655-8900 TWX 710-386-0114
(203) 873-9995
1325 Remmgton Rd , SUIte "0"
Schaumburg, IL 60195~4813
MICHIGAN
DELAWARE
(312) 885-8440. (800) 323-8755
TWX 910-222-1808
DETROIT
PMI SALES OFFICE
Contact Bellevue, WA Office
ARIZONA
BALTIMORE
CONROY SALES
ILLINOIS
Unionville. CT 08085~OO43
ALASKA
(404)992-7240 TWX 810-726-2110
Contact Philadelphia. PA Office
INDIANA
DISTRICT OF COLUMBIA
Contact PhiladelphIa, PA OffIce
CARMEL
TECHNOLOGY MARKETING CORP
FLORIDA
599 Industnal Dr
Carmel, I N 46032~4207
(317) 844-8462 TWX 910-997-0194
722 Grand River Rd , SUite 6
Bnghton, MI 48116~1820
(313) 227-2190. (312) 885-8440
(800) 323-8755 TWX 910-222-1808
BRIGHTON
ELECTRONIC SOURCE. INC
8014 W Grand River, SUite 6
Brighton. MI 48118-9302
(313) 227-3598 TLX 298 269
SCOTTSDALE
SUMMIT SALES
7825 E Redfield Rd
Scottsdale, AZ 85260·3486
(602) 998-4850 TWX 910-950-1283
405 Douglas Ave
Altamonte Springs. FL 32714-2505
Ft wayne, IN 46804-2142
MINNESOTA
(305) 788-1403. (800) 223-6147
TWX 910-881-4079
(219) 432-5553 TWX 910-997-0195
ARKANSAS
MINNEAPOLIS
MEL FOSTER TECH SALES. INC
ALTAMONTE SPRINGS
IOWA
LAWRENCE ASSOCIATES. INC
711 Turnbull Ave
Altamonte Spnngs. FL 32701~6420
DAveNPORT
RUSH & WEST ASSOCIATES. INC
7611 Washington Ave, South
PO Box 35216
Edina. MN 55435-0216
Contact Ganzel Sales & Aseoe , Inc
Tulsa, OK Office
CALIFORNIA
LOS ANGELES
PMI SALES OFFICE
4025 E La Palma Ave
Anaheim, CA 92807-1716
(714) 666-0140. (213) 642-0142
TWX 910-328-6591
ALTAMONTE SPRINGS
PMI SALES OFFICE
Bldg II. SUIte 2505-5
FT. WAYNE
TECHNOLOGY MARKETING CORP
3428 W Taylor St
3 Columbia Ct , Northwest
Davenport, IA 52804~2416
(305)339-3855 TWX 510-953-7802
BOCA RATON
LAWRENCE ASSOCIATES. INC
(319) 326-3091
2151 N W 2nd, Suite 104
Boca Raton. FL 33431~7405
KANSAS
(612) 941-9790 TWX 910-578-2746
MISSISSIPPI
Contact EMA, Huntsville, AL OffIce
KANSAS CITY/WICHITA
RUSH & WEST ASSOCIATES. INC
(305) 368-7373 TWX 510-953-7802
BALLWIN
RUSH & WEST ASSOCIATES, INC
Olalhe. KS 66061-3690
(913) 764-2700 TWX 910-380-8110
720 W Manchester Rd • SUite 200
BallWin, MO 63011~3027
CLEARWATER
LAWRENCE ASSOCIATES. INC
SAN JOSE
QUAOREP INC.
2713 N First St.
San Jose, CA 95134-2099
(408)94&-4000 TWX 910-338-0207
MELBOURNE
LAWRENCE ASSOCIATES. INC
LOUISVILLE
TECHNOLOGY MARKETING CORP
1101 W HIbISCUS Blvd. SUite E115
W Melbourne, FL 32901-2745
8819 Roman Ct
(305) 724-8294 TWX 510-953-7802
LOUISVIlle, KY 40291-0147
1605 MIssourI Ave
Clearwater. FL 33516~1220
MISSOURI
107 N Chester St
SAN DIEGO
L & S ASSOCIATES
11772 Sorrento Valley Rd, SUite 235
San Diego. CA 92121-1017
(819) 455-0055 TWX 910-322-1730
(314) 394-7271 TLX 752 653
(813)584-8110 TWX 510-953-7602
KENTUCKY
PO Box 91147
(502)499-7808 TWX 810-535-3757
SANTA CLARA
PMI SALES OFFICE
4633 Old Ironsides Dr, Surte 312
LOUISIANA
Santa Clara, CA 95054-1806
(408) 727-6616 TWX 910-338-2102
TLX 172 070
Contact Houston, TX OffIce
18-2
MONTANA
Contact Littleton. CO Office
SALES OFFICES
REPRESENTATIVES
Pn:ClSlon Monolithics Inc.
NORTH AMERICA
NEBRASKA
OHIO
TENNESSEE
WISCONSIN (EASTERN)
Contact Rush & West ASSOCiates,
Davenport, IA Office
CLEVELAND
DEL STEFFEN & ASSOCIATES
69 Alpha Park
Cleveland, OH 44143-2296
(216) 461-8333 TWX 810-427-9272
DONELSON
EMA
118 Spring Valley
Donelson, TN 37214-2822
(615) 883-1414
Contact Chicago, IL Office
COLUMBUS
DEL STEFFEN & ASSOCIATES
355 W Main St
Lexington, OH 44904-9767
(419) 884-2313 TWX 810-427-9272
JONESBORO
EMA
Route 8, Dogwood Vlg
Jonesboro, TN 37659-9807
(615) 753-8081. (800) 633-2920
NEVADA
Contact Santa Clara, CA Office
NEW HAMPSHIRE
Contact Boston, MA Office
NEW JERSEY (NORTHERN)
Contact J-Square Marketing,
HickSVille, NY Office
NEW JERSEY (SOUTHERN)
TEXAS
DALLAS
PMI SALES OFFICE
11325 Pegasus St, SUite E-102
Dallas, TX 75238-3228
(214) 341-1742. (800) 223-6147
TWX 910-861-4079
OKLAHOMA
NEW MEXICO
TULSA
GENZEL SALES & ASSOC, INC
4135 S 100th East Ave, SUite 101
Tulsa, OK 7414&-3635
(918) 622-7744 TLX 312 394
HOUSTON
PMI SALES OFFICE
POBox 262423
Houston, TX 77207-2423
(713) 481-6460. (214) 341-1742
(800) 223-6147 TWX 910-861-4079
OREGON
NEW YORK
SYRACUSE
L-MAR ASSOCIATES. INC
216 Tilden Dr
East Syracuse, NY 13057-1630
(315) 437-7779
METRO NY, LONG ISLAND
J-SQUARE MARKETING. INC
161-C Levltown Pkwy
HickSVille, NY 11801-4421
(516) 935-3200 TWX 510-221-2136
ROCHESTER
L-MAR ASSOCIATES. INC
4515 Culver Rd
Rochester, NY 14622-1497
(716) 323-1000 TWX 510-253-0943
NORTH CAROLINA
PINEVILLE
EMA
8539 Glenway Ct
Pineville, NC 28134-8326
(704) 541-2628 TWX 810-726-2110
PORTLAND
NORTHWEST MARKETING
SUite 330
6975 S W Sandburg Rd
Portland, OR 97223-8010
(503) 620-0441 TWX 910-464-5157
UTAH
SALT LAKE CITY
FRONT RANGE MARKETING
2520 S State St, SUite 117
Salt Lake City, UT 84115-3110
(801) 364-6481 TWX 910-925-4117
PENNSYLVANIA
VERMONT
PHILADELPHIA
PMI SALES OFFICE
431 LakeSide Dr
Horsham, PA 19044-2320
(215) 675-7600 TWX 710-670-0021
Contact Boston, MA Office
VIRGINIA
Contact Conroy Sales,
Baltimore, MD Office
PITTSBURGH
DEL STEFFEN & ASSOCIATES
Carnegie Office Park
Bldg 1, Rm 116K
600 N. Bell Ave
Pittsburgh, PA 15106-4363
(412) 276-7366 TWX 810-427-9272
WASHINGTON
BELLEVUE
NORTHWEST MARKETING
SUite 330N
12835 Bellevue Redmond Rd
Bellevue, WA 98005-2625
(206) 455-5846 TWX 910-443-2445
SELLERSVILLE
TECH-COM MARKETING
PO Box 460
Sellersville, PA 18960-0460
(215) 453-0711
WINSTON SALEM
EMA
3463 Kernerville Rd
Winston Salem, NC 27107-1750
(919) 784-7304 TWX 810-726-2110
Contact Boston, MA Office
NORTH DAKOTA
SOUTH CAROLINA
Contact Mel FosterTech Sales. Inc ,
Edina, MN Office
Contact EMA, WInston Salem, NC
Office
WYOMING
Contact Llttfeton, CO Office
CANADA
DAYTON
DEL STEFFEN & ASSOCIATES
1201 E David Rd
Dayton, OH 45429-5701
(513) 293-3145 TWX 810-427-9272
Contact Philadelphia, PA Office
ALBUQUERQUE
BFA CORPORATION
1704 Moon, Northeast
Albuquerque, NM 87112-3936
(505) 292-1212 TWX 910-989-1157
WISCONSIN (WESTERN)
Contact Mel Foster Tech Sales, Inc,
Edina, MN Office
WEST VIRGINIA
Contact Del Steffen & Associates,
Pittsburg, PA Office
RHODE ISLAND
ALBERTA
HI-TECH SALES LIMITED
PO Box 115
339 10th Ave Southeast
Calgary. Alberta T2G OW2
(403) 239-3773
BRITISH COLUMBIA
HI-TECH SALES LIMITED
7510 B Kingsley
Burnaby, British Columbia V3N 3C2
(604) 524-2131
MANITOBA
HI-TECH SALES LIMITED
#102-902 St James St
Winnipeg, Manitoba R3G 3J7
(204) 786-3343
NEW BRUNSWICK
Contact Source Electronics Ltd,
Rexdale. Ontano Office
NEWFOUNDLAND
Contact Source Electronics Ltd.,
Rexdale. Ontario Office
NOVA SCOTIA
Contact Source Electromcs Ltd,
Rexdale, Ontario Office
ONTARIO
SOURCE ELECTRONICS LTD
PO Box 13235
Kanata, Ontario K2K 1X4
(613) 592-5392
ONTARIO
SOURCE ELECTRONICS LTD
83 Galaxy Blvd. Unit 9
Rexdale, Ontario M9W 5X6
(416) 675-6235
QUEBEC
Contact Source ElectronIcs Ltd ,
Rexdale, Ontano OffIce
SASKATCHEWAN
Contact HI-Tech Sales LImited
Winnipeg, Manitoba OffIce
SOUTH DAKOTA
Contact Mel Foster Tech Sales. Inc,
Edina, MN Office
18·3
I
AUTHORIZED
DISTRIBUTORS
1'1~l:l""l()n MOllOhthll.: ... ItH':
NORTH AMERICA
ALABAMA
HUNTSVILLE
HALL-MARK ELECTRONICS
4900 Bradford Dr
Huntsville, AL 35805-1951
(205) 837-8700 TWX 810-726-2187
CALIFORNIA continued
SACRAMENTO
BELL INDUSTRIES
500 Giuseppe Ot , SUite 6
Roseville, CA 95678-6305
(916) 969-3100
CONNECTICUT
NORWALK
PIONEER
112 Main 8t
Norwalk, CT 06851-4617
(203) 853-1515 TWX 710-488-3373
ILLINOIS
WOOD DALE
HALL-MARK ELECTRONICS
210 Mltel Dr
WOod Dale, IL 60191-1120
(312) 880-3800 TWX 910-651-0185
HUNTSVILLE
PIONEER
4825 Unrverslty Square
Huntsville. AL 35805-6041
(205) 837-9300 TWX 810-726-2197
SAN DIEGO
ANTHEM ELECTRONICS
9639 Carroll Park Dr
San D,ego, CA 92121-1406
(619) 453-9005 TWX 910-335-1515
WALLINGFORD
HALL-MARK ELECTRONICS
33 Village lane
Wlilingford, CT 06492-2428
(203) 269-0100 TLX 314-207
CHtCAGO
PIONEER
1551 Carmen Dr
Elk Grove Village, IL 60007-6581
(312) 437-9680 TWX 910-222-1834
ARIZONA
PHOENIX
HALL-MARK ELECTRONICS
4040 E Raymond
PhoenIx, AZ 85040-1983
(602) 437-1200 TWX 910-951-1325
TEMPE
ANTHEM ELECTRONICS
1727 E VVeber Dr
Tempe, AZ 85281-1841
(602) 966-6600 TWX 910-950-0110
TEMPE
BELL INDUSTRIES
1705 W 4th St
Tempe, AZ 85281-2403
(602) 966-7800 TWX 910-950-0133
CALIFORNIA
CANOGA PARK
HALL-MARK ELECTRONICS
8130 Remmel Ave
Canoga Park, CA 91304-4129
(818) 716-7300
CHATSWORTH
ANTHEM ELECTRONICS
20640 Bahama 8t
Chatsworth, CA 91311-6101
(618) 700-1000 TWX 910-493-2083
GARDEN GROVE
BELL INDUSTRIES
12322 Monarch St.
Garden Grove. CA 92641 ..2909
(714) 220-0681 TWX 910-596-2362
GARDENA
BELL INDUSTRIES
306 E Alondrs Blvd
Gardena, CA 90248-2810
(213) 515-1800 TWX 910-348-6336
IRVINE
ANTHEM ELECTRONICS
1 Oldfield Dr
Irvine. CA 9271&-2809
(714) 788-4444 TWX 910-595-1583
LOS ALAMITOS
SEMI DICE INC.
10981 Bloomfield 51.
Los Alamitos, CA 90720-2586
(213) 594-4831 TWX 910-341-7710
SAN DIEGO
BELL INDUSTRIES
7450 Ronson Rd
San Diego, CA 92111-1508
(619) 268-1277
FLORIDA
CLEARWATER
HALL-MARK ELECTRONICS
15301 Roosevelt Blvd, SUite 303
Clearwater, FL 33520-3561
(813) 530-4543
SAN DtEGO
HALL-MARK ELECTRONICS
3878 Ruffm Ad , SUite 10B
Ssn Diego, CA 92123-1849
(619) 266-1201
FT. LAUDERDALE
PIONEER
674 S MIlitary Trail
Deerfield Beach, Fl 33442-3023
(305) 428-8877 TWX 51D-955-9653
SAN JOSE
ANTHEM ELECTRONICS
1040 E Brokaw Rd
San Jose, CA 95131-2309
(408) 295-4200 TWX 910-338-2038
FT. LAUDERDALE
HALL-MARK ELECTRONICS
3161 S W 15th St
Pompano Beach, FL 33069-4806
(305) 971-9280 TWX 510-956-9720
SAN JOSE
HALL-MARK ELECTRONICS
1110 Ringwood Ct
San Jose, CA 95131-1726
(408) 946-0900 TWX 910-339-9505
ORLANDO
HALL-MARK ELECTRONICS
7648 Southland Blvd, SUite 100
Orlando, Fl32809-6993
(305) 855-4020 TWX 810-850-0105
SUNNYVALE
BELL INOUSTRIES
1161 N Falroaks Ave
Sunnyvale, CA 94089-2102
(408) 734-8570 TWX 910-339-9378
ORLANDO
PIONEER
221 N Lake Blvd
Altamonte Sprrngs, Fl 32701-4399
(305) 834-9090, (600) 432-6064
TWX 810-853-0284
THOUSAND OAKS
BELL INDUSTRIES
1829A De Havilland Dr
Thousand Oaks, CA 91320-1702
(805) 499-8821 TWX 910-321-3799
GEORGIA
NORCROSS
HALL-MARK ELECTRONICS
6410 AtlantiC Blvd, SUite 115
Norcross, GA 30071-1241
(404) 447-6000 TWX 810-786-4510
TORRANCE
HALL-MARK ELECTRONICS
19220 S Normandle
Torrance, CA 90502-1011
(213) 217-8400
NORCROSS (ATLANTA)
PIONEER
Peachtree Crossing Bus Park
5835B Peachtree Corners, East
Norcross, GA 30092-3404
(404) 448-1711 TWX 810-786-4515
TUSTIN
HALL-MARK ELECTRONICS
14831 Franklin Ave
Tustin, CA 92680-7292
(714) 889-4700 TWX 910-997-0523
COLORADO
DENVER
ANTHEM ELECTRONICS
8200 S Akron St.
Englewood, CO 80112-3505
(303) 790-4500
INDIANA
INDIANAPOLIS
HALL-MARK ELECTRONICS
4275 W 96th St
Indianapolis, IN 46268-1113
(317) 872-8875
INDIANAPOLIS
PIONEER
6408 Castleplace Dr
IndianapoliS, IN 46250-1914
(317) 849-7300 TWX 810-260-1794
KANSAS
LENEXA (KANSAS CITy)
HALL-MARK ELECTRONICS
10815 Lakeview Ave
Lenexa, KS 66219-1329
(913) 888-4747 TWX 910-749-6820
MARYLAND
BALTIMORE
HALL-MARK ELECTRONICS
10240 Old Columbia Rd.
Columbia, MO 21046-1218
(301) 986-9600 TWX 710-862-1907
GAITHERSBURG
PIONEER
9100 Gaither Rd
Gaithersburg, MD 20877-1422
(301) 921-0660 TWX 710-828-0545
MASSACHUSETTS
LEXINGTON
PIONEER
44 Hartwell Ave
LeXington, MA 02173-3103
(817) 861-9200 TWX 710-326-8817
NORWOOD
GERBER ELECTRONICS
128 Carnegie Row
Norwood, MA 02082-5010
(617) 769-6000 TWX 710-336-1987
WESTBOROUGH
FUTURE ELECTRONICS
133 Flanders Rd
Westborough, MA 01581-1005
(617) 366-2400 TWX 710-390-0374
DENVER
HALL-MARK ELECTRONICS
6950 S. Tucson Way, Suite G
Englewood, CO 80112-3922
(303) 790-1662 TWX 910-931-0472
WOBURN
HALL-MARK ELECTRONICS
6 Cook St.
Billerica, MA 01821-6036
(617) 935-9777 TLX 929 419
WHEAT RIDGE
BELL INDUSTRIES
8155 W. 48th Ave.
Wheat Rldgo, CO 80033-3199
(303) 424-1985 TWX 910-938-0393
18·4
AUTHORIZED
DISTRIBUTORS
1'1(.·<.:'..,1011 l'\'lonollthI<.:'" Inc
NORTH AMERICA
MICHIGAN
NEW MEXICO
OKLAHOMA
UTAH
LIVONIA
PIONEER
13485 Stamford
livonia, MI 48150-1598
(313)525-1800 TWX 810-242-3271
ALBUOUERQUE
BELL INDUSTRIES
11728 linn, Northeast
Albuquerque, NM 87123-2943
(505) 292-2700 TWX 910-989-0625
TULSA
HALL-MARK ELECTRONICS
5460 S 103rd East Ave
Tulsa, OK 74146-5815
(918) 685-3200 TWX 910-845-2290
SALT LAKE CITY
ANTHEM ELECTRONICS
1615 W 2200, South, Suite A
Salt Lake City, UT 84119-1456
(801)973-8555 TWX 910-925-5273
MINNESOTA
NEW YORK
OREGON
BLOOMINGTON
HALL-MARK ELECTRONICS
783812th Ave, South
Bloommgton, MN 55420-1477
(812) 854-3223 TWX 910-578-3167
BINGHAMTON
PIONEER
1806 VIstal Pkwy, East
vestal, NY 13850-1942
(607) 748-8211 TWX 510-252-0893
LAKE OSWEGO
ANTHEM ELECTRONICS, INC
15812 S W Upper Boones Ferry Rd
Lake Oswego, OR 97034-4066
(503) 884-2881
WASHINGTON
MINNEAPOLIS
MERIT ELECTRONICS CORP
warehouse SUile 210
2525 Nevada Ave , North
Minneapolis, MN 55427-3862
(812) 548-5363
FAIRPORT
PIONEER
840 Fairport Park
Fairport, NY 14450-2012
(716) 381-7070 TWX 510-253-7001
PORTLAND
BELL INDUSTRIES
8024 S W Jean Rd
lake Oswego, OR 97034-5390
(503) 241-4115 TWX 910-455-8177
REDMONO
ANTHEM ELECTRONICS
5020 148th Ave, Northeast
Redmond, WA 98052-5171
(206) 881-0850
LONG ISLAND
HALL-MARK ELECTRONICS
PENNSYLVANIA
MINNETONKA (TWIN CITIES)
PIONEER
10203 Bren Rd , East
Minnetonka, MN 55343-9072
(612) 935-5444 TWX 910-576-2738
MISSOURI
EARTH CITY
HALL-MARK ELECTRONICS
13750 Shoreline Or
Earth City, MO 63045-1224
(314) 291-5350, (800) 325-1021
TWX 910-762-0672
NEW JERSEY
FAIRFIELD
HALL-MARK ELECTRONICS
107 Fairfield Rd
Fairfield, NJ 07006-2412
(201) 575-4415 TWX 710-734-4409
FAIRFIELD
NU-HORIZONS ELECTRONICS
CORP
258 Route 46
Fairfield, NJ 07008-2324
(201) 682-8300
MT. LAUREL
HALL-MARK ELECTRONICS
1000 Mldlantlc Or
Mt Laurel, NJ 08054-1511
(609) 235-1900 TWX 710-940-0660
PINE BROOK
PIONEER
45 Route 46
Pme Brook, NJ 07058-9607
(201) 575-3510 TWX 710-734-4382
1 Comae Loop
HORSHAM
PIONEER
261 Glbralter Rd
Horsham, PA 19044-2377
(215) 874-4000 TWX 510-685-8778
Ronkonkoma, NY 11779·6816
(516) 737-0600 TWX 510-222-0162
NO, AMITYVILLE
NU-HORIZONS ELECTRONICS
CORP
6000 New HOrizons Blvd
No. AmitYVille, NY 11701-1130
(516) 226-6000, (800) 645-9222
TLX 221 228
PITTSBURGH
PIONEER
259 Kappa Or
Pittsburgh, PA 15238-2817
(412) 782-2300 TWX 710-795-3122
WOODBURY (LONG ISLAND)
PIONEER
60 Crossways Park, West
Woodbury, NY 11797-2019
(516) 921-8700 TWX 510-221-2184
SALT LAKE CITY
BELL INDUSTRIES
3639 W 2150, South
Salt Lake City, UT 84120-1286
(801)972-6989 TWX 910-925-5886
SEATTLE
BELL INDUSTRIES
1900 132nd Ave, Northwest
Bellevue, WA 98005-2288
(206) 747-1515 TWX 910-443-2482
WISCONSIN
NEW.ERLIN
HALL-MARK ELECTRONICS
16255 W Lincoln Ave.
New Berlin, WI 53151-2834
(414) 797-7844, (600) 242-5252
TLX 323 082
TEXAS
NORTH CAROLINA
AUSTIN
HALL-MARK ELECTRON ICS
12211 Technology Blvd
Austin, TX 78727-8102
(512) 258-8848 TWX 910-847-2031
CHARLOTTE
PIONEER
9801-A Southern Pine Blvd
Charlotte, Ne 28210-5562
(704) 527-8188 TWX 810-621-0366
AUSTIN
PIONEER
9901 Burnet Rd.
Austin, TX 78758-5239
(512) 835-4000 TWX 910-874-1323
RALEIGH
HALL-MARK ELECTRONICS
5237 North Blvd
Raleigh, Ne 27604-2925
(919) 872-0712 TWX 510-928-1831
DALLAl
HALL-MARK ELECTRONICS
10375 Brookwood Rd
Dallas, TX 75238-1856
(214)341-1147 TWX 910-887-4775
DALLAl
PIONEER
13710 Omega Rd.
Dallas, TX 75244-4518
(214) 388-7300, (BOO) 492-9027
TWX 910-880-5583
OHIO
CLEVELAND
PIONEER
4800 E 131.t St
Cleveland, OH 44105-7132
(216) 587-3600 TWX 810-422-2210
CANADA
ALBERTA
FUTURE ELECTRONICS, INC
5809 Macleod Trail South, Unit 109
Calgary, Alberta T2H OJ9
(403) 259-6408 TWX 610-821-1927
BRITISH COLUMBIA
FUTURE ELECTRONICS, INC
3070 Klngsway
Vancouver, British Columbia
V5R 5J7
(604) 438-5545 TWX 610-922-1688
BRITISH COLUMBIA
INTEK ELECTRONICS LTD
838551 George St -10
Vancouver, British Columbia
V5X 4P3
(604) 324-6831 TWX 610-922-5032
TLX 04-507578
ONTARIO
FUTURE ELECTRONICS, INC
Baxter Centre, 1050 Baxter Rd
Ottawa, Ontano K2C 3P2
(613) 820-8313 TWX 610-563-1697
HOUSTON
HALL-MARK ELECTRONICS
8000 Westglen
P,O. Box 42190
Houston, TX 77083-8485
(713) 781-8100 TWX 910-881-2711
DAYTON
PIONEER
4433 Interpolnl Blvd
PO Box 291
Dayton, OH 45424-5708
(513) 236-9900
TWX 810-459-162211623
ONTARIO
FUTURE ELECTRONICS, INC
82 51 RegiS Crescent N
Oownsvl8w, Ontano M3J 1Z3
(416) 638-4771 TWX 610-491-1470
HOUSTON
PIONEER
5853 POint West Or
Houston, TX 77036-2811
(713) 988-5555 TWX 910-881-1806
SOLON
HALL-MARK ELECTRONICS
5821 Harper Ad
Solon, OH 44139-1832
(216) 349-4632
QUEBEC (MONTREAL)
FUTURE ELECTRONICS, INC
237 Hymus Blvd
POinte Claire, Quebec H9R 5C7
(514) 694-7710 TWX 610-421-3251
WORTHINGTON
HALL-MARK ELECTRONICS
SUite "5"
400 e Wilson Bridge Ad
'Northington, OH 430as-.2321
(614) 888-3313
18-5
----- -
~-
~-
---~
-
~~
~-~
-
SALES OFFICES
REPRESENTATIVES
I'llll'>IOIl
\lollollthl(~'" lilt.:
INTERNATIONAL
EUROPEAN
HEADQUARTERS
BOURNSAG
ZUIII·,.t'.... 74
8340 a•• r
Swltzertand
Phone: 042-33 33 33
Telex: 888 722
ARGENTINA
NOise SAL
V Cevallos 239
(1077) Buenos Aires
ArgentIna
Phone 46-5776/0628/0864/2214
Telex 22892 NOise AR
AUSTRALIA
VICTORIA
RIFA Ply Ltd
202 Sell St
Preston, Victoria 3072
Phone (03) 480 1211
Telex AA 31001
Cable RIFMEL
NEW SOUTH WALES
RIFA Pty Ltd
2 Cross St
HurstvllJe, 2220 N S W
Phone (02) 510-6122
Telex 22515
AUSTRIA
Ing Otto Folger
Elektronlsche Geraete
Bllndengasse 36
1080 Vienna
Phone 0222-43 26 39
Telex 131 882
BENELUX
Sourns Benelux B V
Van Tuyl van Serooskerkestr 81-85
FINLAND
JAPAN
Insele ov
Kumpulantle 1
00520 HelSinki 52
Phone 90-75 06 00
Telex 122217
SPAIN
Nippon PMI Corporation
Haratetsu BUilding
4-1-11, Kudan Klta
Chlyoda-ku, Tokyo
102 Japan
Phone (03) 234-141'
Telex 781 J 27632
Selco SA
Paseo de la Habana, 190
28036 Madnd
Phone 01-40542 13
Telex 45458
FRANCE
Bourns OHMIC S A
21123 rue des Ardennes
KOREA
75019 Pans
Phone 01-42039633
Telex 230008
Yeoml & Company, Ltd
#498-5 Dapslpn-Oong
Oongdaemoon-Ku, Seoul
Phone (02) 244-1492
Telex K24123 YEONIL
GERMANY
Bourns GmbH
Postfach 1155
Brelte Strasse 2
7000 Stuttgart 1
Phone 0711-22930
Telex 721 656
Bourns GmbH
Bahnhofstrasse 4b
8057 Echlng
Phone 089-319 12 70
ISRAEL
Phone 02-986333
AVIV ElectrOnics Ltd
12, Kehllat Venecla St
PO B 24190
Tel-AVIV 61241
Phone 03-49 44 50
Telex 33572 mavlv II
Fax 3-494065
EASTERN EUROPE
Dlpl Ing
Gerhard StOlte
Nordbahnstrasse 44/15
1020 Vienna
Austria
Phone 0222-24 71 37
Telex 134 171
Dynamar International Ltd
12, Lorong Bakar Batu, #65-11
Kolam Ayer Industrial Park
Singapore 1534
Phone 747-6188
Telex RS26283 Dynama
Components Agent Ltd.
Unit 2301 C-2, Nan Fung Centre
298 Castle Peak Road, N T
Phone 0-4992688
Telex 30398 Comag HX
2880 Bagsvaerd-Copenhagen
Telex 37350
SINGAPORE
HONG KONG
SUJata Sales & Electromcs
141-A Mlltal Ct
Narlman POint
Bombay 40021
Phone 222-999
Telex 011 3855
KrogshoJV8J 51
Rua Rodrigo da Fonseca 103
Lisbon 1
Phone 19-68 60 72
Telex 42827
Germanls Co
Trade of ElectrOnic Gear
Anstotelous 51 47-49
PO Box 8209
10010 Athens
Phone 01-821 5825
Telex 219179
2270 AA Voorburg
Phone 070-87 54 04
E Frus-Mlkkelsen AlS
PORTUGAL
TeJectra S A R L
GREECE
INDIA
DENMARK
AlS Klell Bakke
Ovre Raellngsvel 20
PO Box 27
2001 Lillestrom
Phone 02-83 02 20
Telex 19407
REGIONAL OFFICE
PO Box 37
Telex 32023
NORWAY
REGIONAL OFFICES
BARCELONA
Selco SA
Gran via de las cortes catalanas,
1176 bls
080020 Barcelona
Phone 03-3147411
BILBAO
Selco SA
Rodnguez Arias, 71 bls
48013 Bilbao
Phone 04-442 46 00
SWEDEN
Bexab Elektronlk AB
PO Box 516
18325 Taeby
Phone 08-7680560
Telex 10912
SWITZERLAND
Bourns (Schwelz) AG
Zugerstrasse 74
6340 Baar
Phone 042-33 33 33
Telex 868 722
TAIWAN
Mornhan International Corporation
9F No 176 Fu-Hslng N Rd
Taipei, Taiwan, ROC
Telex (785) 20422 Mornhan
SOUTH AFRICA
JOHANNESBURG
ASSOCiated Electronics (Ply) Ltd
POBox 31094, Braamfonteln 2017
ASSOCiated House, 150 Caroline St
Bnxton, Johannesburg
Phone 011-839 18 24
Telex 425 586
DUNSWART
Allied electronic Components
(Pty) lid
PO Box6387
Dunswart 1508
Phone 52-86 61
Telex 425559
TURKEY
NEL Elektronlk
Suemer Sokak No 42/1
Yemsehlr-Ankara
Phone 041-30 15 10
Telex 42229
REGIONAL OFFICE
NEL Elektronlk
Inonu Cad Dumen Sokak 1/15
Takslm-Istanbul
Phone 01-144 06 36
Telex 24549
UNITED KINGDOM
Bourns Electronics Ltd
Hodford House
17/27 High St
Hounslow, Middlesex TW3 1TE
Phone 01-5726531
Telex 264485
ITALY
TECHNIC S r L
Via Brembo 21
20139 Milan
Phone 02-569 57 46
Telex 316651
YUGOSLAVIA
Jugomlneral
Sektor Inozemna zastupstva
1llca 34/11
PO Box376
41000 Zagreb
Phone 041-423746
Telex 21 194
REGIONAL OFFICE
TECHNIC Sr L
Via Ippomo 2
00183 Rome
Phone 06-77 83 94
18-6
AUTHORIZED
DISTRIBUTORS
I'n·CI .... I01l
l\'lonollthtcs Inc
INTERNATIONAL
BELGIUM
Aunema BelgIum
rue Brognl9zstraat 172 a
1070 Brussels
Phone 02-523 82 95
Telex' 216 48
FRANCE
MAISONS-LAFITTE
I SA Electromqu8
50/52, rue d'Acheres
78600 Mal80ns-lafltte
Phone 1-39 122452
Telex 695 877
SURESNES
ISC
International Semi-Conductor
Corp France
28/30 rue de 18 ProcesSion
B P 118
92153 Suresnes
Phone 1-45 06 42 75
Telex, 614 596
VERRIERES LE BUISSON
HYBRITECH (for dice only)
Z.I des Godets
Aoute de Bua
CE421
91374 V8meres Ie BUisson
Phone. Hl9 20 22 10
Telex 300 315
CHATILLON CEDEX
BANELEC
90. rue Pierre Semard
B P 83
92322 Chatillon Cedex
Phone 1-46 55 43 43
Telex 204 874
CLiCHY CEDEX
DIMACEL
11, rue Jean d'Asmeres
B P 280
92113 Cllchy Cedex
Phone 1-4730 15 15
Telex 610 652
BONNEUIL CEDEX
SYSCOM
Z A des Petlts-Carreaux
12, av des Coquehcots
94385 BonneUlI Cedex
Phone 1-4377 84 88
Telex. 231 568
LILLE
DIMACEL
78, rue
Boucher~de~Perthes
59800 lille
Phone 20 30 85 80
Telex 110 173
STRASBOURG
DIMACEL
17, Boulevard de Nancy
6700 Strasbourg
Phone 882207 19
Telex 880 372
FRANCE continued
GERMANY continued
BREMEN
Assmy & Bottger
Ingolstadterstrasse 1/3
2800 Bremen 1
Phone 0421-38941
Telex' 244 363
BORDEAUX CEDEX
S,C T. Toutelectrlc
80/83, qual de Queyrles
33072 Bordeaux Cedex
Phone: 58 88 50 31
Telex 550 988
SAINT PRIEST
DIMACEL
Censloz 2-Tour 5
32bls, Boulevard des Roses
69800 Saint Priest
Phone' 78 21 3721
Telex 380 010
HAMBURG
Walter Kulxen GmbH
Nordkanalstrasse 52
2000 Hamburg 1
Phone. 040-2 37 01 0
Telex, 2 162074
HANNOVER
Elkose GmbH
Vahrenwalderstr8sse 205/207
3000 Hannover 1
Phone: 0511-6 78 05 0
Telex 921 501
SAINT MARTIN d'HERES CEDEX
DIMACEL
21, rue Beal
Z I Sud
B P 155
38404 Saint Martin d'Heres Cedex
DORTMUND
Elkose GmbH
llndenhorsterstrasse 38
4600 Dortmund
Phone 0231-8 40 50
Telex, 8 227 882
LYON CEDEX
RADIALEX
74, rue Vendome
B P 6003
69411 lyon Cedex 06
Phone 78 89 45 45
Telex 300 238
DREIEleM
Spoerle ElectrOnic KG
M8x-Planck~Str8sse 1/3
6072 Drelelch
Phone 06103-3 04 0
Telex 417972
GRENOBLE
RADIALEX
6, rue Georges Jacquet
B P 866
38036 Grenoble
Phone 76 49 49 92
Telex 320 378
MOGLINGEN
Elkose GmbH
BahnhofstraS8e 44
7141 Moghngen
Phone 07141-48 70
Telex 7 264 472
TOULOUSE CEDEX
S C, T Toutelectrlc
37, av Emile Dewoltme
B P 2167
31022 Toulouse Cedex
Phone. 61 220422
Telex 530 219
STUTTGART
DACOM Electronic Vertnebs GmbH
Huttenelchenweg 10
7000 Stuttgart 80
Phone 0711-741021
Telex 7 255 309
TOULOUSE
DIMACEL
284, route de St Simon
31100 Toulouse
Phone 61 40 96 50
Telex, 521 364
MUNICH
Astronlc
Wlnzererstrasse 47 0
8000 Munchen 40
Phone 089-30 90 31
Telex 5218 187
LESMILLES
DIMACEL
64, rue Georges Claude
Z I Alx en Provence
13763 les Milies
Phone 42 39 85 50
Telex 441 569
KIRCHHEIM
MBS ElectrOnic
Benzstrasse 1
8011 Klrchhelm
Phone 089-903 85 51
Telex 5 215 555
TOULON CEDEX
DIMEL
"le MarinO"
Avenue Claude Farrere
BP 1153
83058 Toulon Cedex
Phone 94 41 49 63
Telex. 430 093
RENNES
DIMACEL
5, rue loUis Turban
35100 Rennes
Phone 99 50 25 92
Telex 950 466
GERMANY
BERLIN
Spoerle ElectrOniC KG
Gnelsenaustrasse 2
1000 Berhn 61
Phone 030-693 40 90
Telex 186 029
BORDEAUX
DIMACEL
137/139, rue Crolx-de-Seguey
33000 Bordeaux
Phone 56 81 14 40
Telex 540 579
BERLIN
Distron GmbH & Co
BehSlmstrasse 3
1000 Berlin 10
Phone 030-342 10 41 45
Telex 185 478
PUTZBRUNN
Sasco GmbH
Hermann-Oberth-Strasse 16
8011 Putzbrunn
Phone 089-461 10
Telex 529 504
NUERNBERG
Semtech GmbH
Hallerwelherstrasse 5
8500 Nuernberg 50
Phone 0911-831003
Telex 623 960
ISRAEL
AVIV ElectrOniCs ltd
12, Kehllat Veneela St
P.O Box 24190
Tel-AVIV 61241
Phone 03-49 44 50
Telex 33572
18-7
ITALY
MILAN
ComprelS,PA
Vlale F, Testl, 115
20092 Clnlsello Balsamo
Milan
Phone 02-6120641/5
Phone 02~612 66 41/5
Telex, 332 484
ROME
Comprel SPA
Via Farne8lna, 224
00194 Rome
Phone' 08-328 67 39
Phone 08-328 88 89
YICENZA
Comprel S PA
Via Paslm 18
36100 Vlcenza
Phone, 0444-3 39 12
NETHERLANDS
HAAKSBERGEN
Texlm ElectrOniCs B V
Albert Cuyptaan 4
7482 JA Haaksbergen
Phone 05427-333 33
Telex, 448 08
STADSKANAAL
Ellncomb B V
Oosterkade 33,
PO Box 248
9500 AE Stadskanaal
Phone 05990-14830
Telex 53378
SWEDEN
Elfa RadiO and TelevIsion AB
17117Solna
Phone 08-730 07 00
SWITZERLAND
Distrelec AG
Hardturmstrasse 131
8037 ZUrich
Phone 01-276 22 11
Telex 823 045
UNITED KINGDOM
CAMBRIDGE
HlwTek ElectrOnics Ltd
Ditton Walk
Cambndge CB5 8CD
Phone 0223-21 33 33
Telex 817 347
BEDFORD
RR ElectrOniCs ltd
SI MartinS Way Industrial Estate
Cambndge Road
Bedford M K42 OlF
Phone 0234-47 188
Telex 826 251
KENT
Jermyn Distribution Ltd
Vestry Estate
Sevenoaks
Kent TN 14 5EU
Phone 0732-4501 44
Telex, 95 142
ESSEX
STC Electronics Services
Edinburgh Way
Harlow
Essex CM20 2DF
Phone 0279-26 777
Telex 81525
II
Production
Team
Text Coordination and Production: Kaz Hamano
Rose Kimball
Judy Sharp
Cover Design: Kaz Hamano
Typesetting: Alana Haas
Proofreading: Sarah Baker
Project Management: Jean-Marie DeRousse
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:08:22 11:52:40-08:00 Modify Date : 2013:08:22 12:51:45-07:00 Metadata Date : 2013:08:22 12:51:45-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:def004b6-5b18-2d49-945e-ff4cd95bf958 Instance ID : uuid:2192088d-1cf4-524d-8680-6dd588e597b9 Page Layout : SinglePage Page Mode : UseNone Page Count : 899EXIF Metadata provided by EXIF.tools