1986_RCA_High_Speed_CMOS 1986 RCA High Speed CMOS
User Manual: 1986_RCA_High_Speed_CMOS
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nell
Solid
State
DATABOOK
RCA High-Speed CMOS Logic
Integrated Circuits
The RCA HC/HCT series of high-speed CMOS logic integrated circuits include an extensive line of products that are
pin compatible with many existing bipolar 54/74 LSTTL and
CMOS 4000 series of digital logic types. The new HC/HCT
series IC's provide high-speed CMOS replacements for the
most popular LSTTL devices in existing designs and also
offer low-power all-CMOS designs for new digital systems.
Key family features of the RCA HC/HCT types include:
• Speeds equivalent to LSTTL types with typical gate delays
of 8 ns.
• Fanout to 1074 LSTTL loads; 15 loads using Bus Driver
54174 types.
• Operating frequencies equivalent to LSTTL types, typically 50 MHz.
• The high voltage noise immunity characteristic of CMOS,
typically 45 percent of Vcc, a two to three times improvement over LSTTL. (HC-Series types.)
• Wide range of power supply operating voltages, 2 to 6
volts.
• CMOS low static power consumption, typically less than 1
microwatt.
With the broad line of CMOS MSI function types currently
available, together with performance offered by the RCA
HCIHCT series of high-speed CMOS integrated circuits,
the designer need not sacrifice speed for power consumption. Add the other classical advantages of CMOS, including high noise immunity and wide power supply and
temperature ranges, and the decision to use high-speed
CMOS logic is the choice for the 80's. This family provides
for the design of more cost-effective systems to serve highspeed market applications.
The RCA product line consists of CD54174HC-series types,
which feature CMOS input voltage level compatibility and
CD54/74HCT-series types, which are input voltage level
compatible with LSTTL devices. The line also includes a
limited number of single-stage, unbuffered inverter types
(CD54174HCU-series) for added versatility in oscillator and
amplifier applications.
A general information section defines the distinguishing
characteristics of each product series and providescharacteristic data and classification and selection charts.
The data pages include a description, special features, truth
tables and/or timing diagrams, and significant dynamic
electrical characteristics.
The data sections are followed by a Dimensional Outlines
section.
Product Selectors.
Technical Overview
II
High-Speed CMOS Macrocells
II
Technical Data
Preview Data
Advanced CMOS Logic
g
II
Application Notes
Dimensional Outlines
RCA Sales Offices, Authorized Distributors
and Manufacturers' Representatives
-=-
.r=-
1
Table of Contents
Page
3
4
6
9
Prod uct Selectors .
I ndex to Devices.
.. .......... ..
Product Selection Guide............
.. ......... .
Classification Chart.
.. .................. .
Technical Overview.
. ............. .
Family Description.
. ................................... .
Standardized Capacitance Power Dissipation (CPO) Test Procedure..
. ............. .
Explanation of Symbols
................... .
Standarized Maximum Ratings and Recommended Operating Conditions.
Static Electrical Characteristics.
. .............. .
Dynamic Electrical Characteristics.
Operating and Handling Considerations
Enhanced Product
RCA MIL-STD-883 Slash-Series IC's.
Nomenclature Code
................... .
.. ...........
31
32
36
37
39
39
42
42
42
High-Speed CMOS Macrocells.
43
Technical Data.
47
.. ..... 633
Preview Data ...................................................... .
Advanced CMOS Logic.
...643
Application Notes.
..645
Dimensional Outlines.
..689
RCA Sales Offices, Authorized Distributors and Manufacturer's Representatives.
Information furnished by RCA is believed to be accurate and
reliable. However, no responsibility is assumed by RCA for its
use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by
implication or otherwise under any patent rights of RCA.
When incorporating RCA Solid State Devices in equipment, it is
recommended that the designer refer to "Operating Considerations for RCA Solid State Devices," Form No.1 CE-402, available
on request from RCA Solid State Division, Box 3200, Somerville,
N.J. 08876.
Copyright 1986 by RCA Corporation
(All rights reserved under Pan-American
Copyright Convention)
2
11
12
. ................. 695
The device data shown for some types are indicated as product
preview or advance information/preliminary data. Product preview
data are intended for engineering evaluation of product under
development. The type designations and data are subject to
change or withdrawal, unless otherwise arranged. Advance
Information/preliminary data are intended for guidance purposes
in evaluating new product for equipment design. Such data are
shown for types currently being designed for inclusion in our
standard line of commercially available products. No obligations
are assumed for notice of change of these devices. For current
information on the status of product preview or advance information/preliminary data programs, please contact your local RCA
sales office.
Trademark(s)"'Registered
Marca(s) Registrada(s)
Printed in USAI1 0-86
Product Selectors
____________________________________ 3
Product Selectors
I ndex to Devices
CMOS Logic
Plastic Pkg.
CERDIP
CD74HCOOE.M
CD74HC02E,M
CD74HC03E,M
'CD74HC04E,M
CD74HC08E,M
CD54HCOOF
CD54HC02F
CD54HC03F
TTL Logic
Plastic Pkg.
CERDIP
Page
Description
Pins
CD54HC08F
CD74HCTOOE,M
CD74HCT02E,M
CD74HCT03E,M
CD74HCT04E,M
CD74HCT08E,M
CD74HC10E,M
CD74HCllE,M
CD74HC14E,M
CD74HC20E,M
CD74HC21 E,M
CD54HC10F
CD54HCllF
CD54HC14F
CD54HC20F
CD54HC21F
CD74HCT10E,M
CD74HCTllE,M
CD74HCT14E,M
CD74HCT20E,M
CD74HCT21E,M
CD54HCT10F
CD54HCTllF
CD54HCT14F
CD54HCT20F
CD54HCT21F
76
80
84
CD74HC27E,M
CD74HC30E,M
CD74HC32E,M
CD74HC42E,M
CD74HC73E,M
CD54HC27F
CD54HC30F
CD54HC32F
CD54HC42F
CD54HC73F
CD74HCT27E,M
CD74HCT30E,M
CD74HCT32E,M
CD74HCT42E,M
CD74HCT73E,M
CD54HCT27F
CD54HCT30F
CD54HCT32F
CD54HCT42F
CD54HCT73F
88
92
96
100
104
Triple 3-lnput NOR Gate
a-Input NAND Gate
Quad 2-lnput OR Gate
BCD-la-Decimal Decoder (1-to-10)
Dual J-K Flip-Flop w/RESET
14
14
14
16
14
CD74HC74E,M
CD74HC75E,M
CD74HC85E,M
CD74HC86E,M
CD74HC93E,M
CD54HC74F
CD54HC75F
CD54HC85F
CD54HC86F
CD54HC93F
CD74HCT74E,M
CD74HCT75E,M
CD74HCT85E,M
CD74HCT86E,M
CD74HCT93E,M
CD54HCT74F
CD54HCT75F
C054HCT85F
CD54HCT86F
CD54HCT93F
109
114
119
125
129
Dual 0 Flip-Flop w/SET and RESET
Dual2-Bit Bistable Transparent Latch
4-Bit Magnitude Comparator
Quad 2-lnput EXCLUSIVE-OR Gate
4-Bit Binary Ripple Counter
14
16
16
14
14
CD74HC107E,M
CD74HC109E,M
CD74HCl12E,M
CD74HC123E,M
CD74HC125E,M
CD54HC107F
CD54HC109F
CD54HCl12F
CD54HC123F
CD54HC125F
CD74HCT107E,M
CD74HCT109E,M
CD74HCTl12E,M
CD74HCT123E,M
CD74HCT125E,M
CD54HCT107F
CD54HCT109F
CD54HCTl12F
CD54HCT123F
CD54HCT125F
134
139
144
149
155
Dual J-K Flip-Flop w/RESET
Dual J-K Flip-Flop w/SET and RESET
Dual J-K Flip-Flop w/SET and RESET
Dual Retriggerable Monostable Multivibrator w/RESET
Quad 3-State Buffer
14
16
16
16
14
CD74HC126E,M
CD74HC132E,M
CD74HC137E,M
CD74HC138E,M
CD74HC139E,M
CD54HC126F
CD54HC132F
CD54HC137F
CD54HC138F
CD54HC139F
CD74HCT126E,M
CD74HCT132E,M
CD74HCT137E,M
CD74HCT138E,M
CD74HCT139E,M
CD54HCT126F
CD54HCT132F
CD54HCT137F
CD54HCT138F
CD54HCT139F
160
165
634
169
174
Quad 3-State Buffer
Quad 2-lnput NAND Schmitt Trigger
3-to-8 Line Decoder w/Latch, Inverting
3-to-8 Line Decoder/Demultiplexer, Inverting
Dual 2-of-4 Line Decoder/Demultiplexer
14
14
16
16
16
CD74HC147E,M
CD74HC151 E,M
CD74HC153E,M
CD74HC154E,M
CD74HC157E,M
CD54HC147F
CD54HC151F
CD54HC153F
CD54HC154F
CD54HC157F
CD74HCT147E,M
CD74HCT151E,M
CD74HCT153E,M
CD74HCT154E,M
CD74HCT157E,M
CD54HCT147F
CD54HCT151 F
CD54HCT153F
CD54HCT154F
CD54HCT157F
179
184
189
194
200
10-to-4 Line-Priority Encoder
8-lnput Multiplexer
Dual4-lnput Multiplexer
4-to-16-Line Decoder/Demultiplexer
Quad 2-lnput Multiplexer
16
16
16
24
16
CD74HC158E,M
CD74HC160E,M
CD74HC161E,M
CD74HC162E,M
CD74HC163E,M
CD54HC158F
CD54HC160F
CD54HC161F
CD54HC162F
CD54HCl63F
CD74HCT158E,M
CD74HCT160E,M
CD74HCT161E,M
CD74HCT162E,M
CD74HCT163E,M
CD54HCT158F
CD54HCT160F
CD54HCT161 F
CD54HCT162F
CD54HCT163F
200
205
205
205
205
Quad 2-fnput
Synchronous
Synchronous
Synchronous
Synchronous
16
16
16
16
16
CD74HC164E,M
CD74HC165E,M
CD74HC166E,M
CD74HC173E,M
CD74HC174E,M
CD54HC164F
CD54HC165F
CD54HC166F
CD54HC173F
CD54HC174F
CD74HCT164E,M
CD74HCT165E,M
CD74HCT166E,M
CD74HCT173F,M
CD74HCT174E,M
CD54HCT164F
CD54HCT165F
CD54HCT166F
CD54HCT173F
CD54HCT174F
215
220
226
232
238
8-Bit Serial-In Parallel-Out Shift Register
8-Bit Parallel-In Serial-Out S~ift Register
8-Bit Parallel-In Serial-Out Shift Register
Quad 0 Flip-Flop, 3-8tate
Hex D-Type Flip-Flop w/RESET
14
16
16
16
16
CD74HC175E,M
CD74HC181E,M
CD74HC182E,M
CD74HC190E,M
CD74HC191 E,M
CD54HC175F
CD54HC181F
CD54HC182F
CD54HC190F
CD54HC191F
CD74HCT175E,M
CD74HCT181E,M
CD74HCT182E,M
CD7 4HCT190E, M
CD74HCT191E,M
CD54HCT175F
CD54HCT181 F
CD54HCT182F
CD54HCT190F
CD54HCT191F
243
248
254
260
260
Quad D-Type Flip-Flop w/RESET
4-Bit Arithmetic Logic Unit
Look-Ahead Carry Generator
Presettable Synchronous BCD Decade Up/Down Counter
Synchronous 4-Bit Binary Up/Down Counter
16
24
16
16
16
CD74HC192E,M
CD74HC193E,M
CD74HC194E,M
CD74HC195E,M
CD74HC221E,M
CD54HC192F
CD54HC193F
CD54HC194F
CD54HC195F
CD54HC221F
CD74HCT192E,M
CD74HCT193E,M
CD7 4HCT194E, M
CD74HCT195E,M
CD74HCT221 E,M
CD54HCT192F
CD54HCT193F
CD54HCT194F
CD54HCT195F
CD54HCT221 F
269
269
279
285
291
Synchronous BCD Decade Up/Down Counter
Synchronous 4-8it Binary Up/Down Counter
4-Bit Bidirectional Universal Shift Register
4-Bit Parallel Access Shift Register
Dual Monostable Multivibrator w/RESET
16
16
16
16
16
CD74HC237E,M
CD74HC238E,M
CD74HC240E,M
CD74HC241E,M
CD74HC242E,M
CD54HC237F
CD54HC238F
CD54HC240F
CD54HC241F
CD54HC242F
CD74HCT237F,M
CD74HCT238E,M
CD74HCT240E,M
CD74HCT241 E,M
CD74HCT242E,M
CD54HCT237F
CD54HCT238F
CD54HCT240F
CD54HCT241 F
CD54HCT242F
635
169
298
298
304
3-to-8-Line Decoder/Demultiplexer w/Address Latches
3-to-8-Line Decoder/Demultiplexer
Octal Buffer Line Driver, 3-State, Inverting
Octal Buffer Line Driver, 3-5tate
Quad-Bus Transceiver, 3-State, Inverting
16
16
20
20
14
CD74HC243E,M
CD74HC244E,M
CD74HC245E,M
CD74HC251E,M
CD74HC253E,M
CD54HC243F
CD54HC244F
CD54HC245F
CD54HC251F
CD54HC253F
CD74HCT243E,M
CD74HCT244E,M
CD74HCT245E,M
CD74HCT251 E,M
CD74HCT253E,M
CD54HCT243F
CD54HCT244F
CD54HCT245F
CD54HCT251 F
CD54HCT253F
304
298
310
315
321
Quad-Bus Transceiver, 3-Stale
Octal-Buffer Line Driver, 3-51ale
Octal-Bus Transceiver, 3-51ate
8-lnput Multiplexer, 3-5tate
Dual 4-lnput Multiplexer, 3-5tate
14
20
20
16
16
CD74HC257E,M
CD74HC258E,M
CD74HC259E,M
CD74HC273E,M
CD54HC257F
CD54HC258F
CD54HC259F
CD54HC273F
CD74HCT257E,M
CD74HCT258E,M
CD74HCT259E,M
CD74HCT273E,M
CD54HCT257F
CD54HCT258F
CD54HCT259F
CD54HCT273F
326
330
335
342
Quad 2-lnput Multiplexer, 3-8tate; Non-Inverting Outputs
Quad 2-lnput Multiplexer, 3-8tale; Inverting Outputs
8-Bit Addressable Latch
Octal O-Type Flip-Flop w/RE8ET
16
16
16
20
·CD54HC04F
·CD54/74HCU04, unbuffered version also available.
4
CD54HCTOOF
CD54HCT02F
CD54HCT03F
CD54HCT04F
CD54HCT08F
48
52
56
60
64
Quad 2-lnput NAND Gate
Quad 2-lnput NOR Gate
Quad 2-lnput NAND Gate with Open Drain
Hex Inverter/Suffer
Quad 2-tnput AND Gate
14
14
14
14
14
68
Triple 3-lnput NAND Gate
Triple 3-lnput AND Gate
Hex Inverting Schmitt Trigger
Dual 4-lnput NAND Gate
Dual 4-lnput AND Gate
14
14
14
14
14
72
Multiplexer, Inverting
BCD Decade Counter, Asynchronous Reset
4-Bit Binary Counter, Asynchronous Reset
BCD Decade Counter, Synchronous Reset
4-Bit Binary Counter, Synchronous Reset
Product Selectors
Index to Devices (Cont'd)
CMOS Logic
Plastic Pkg.
TTL Logic
CERDIP
Plastic Pkg.
CERDIP
Page
Description
Pins
CD74HC280E.M
CD74HC283E.M
CD74HC297E.M
CD74HC299E,M
CD74HC354E.M
CD54HC280F
CD54HC283F
CD54HC297F
CD54HC299F
CD54HC354F
CD74HCT280E.M
CD74HCT283E.M
CD74HCT297E.M
CD74HCT299E.M
CD74HCT354E.M
CD54HCT280F
CD54HCT283F
CD54HCT297F
CD54HCT299F
CD54HCT354F
347
351
356
363
370
9-Bit Odd/Even Parity Generator/Checker
4-Bit FuJI Adder w/Fast Carry
Digital Phase-Locked Loop Filter
B-Bit Universal Shift Register, 3-State
a-Input Multiplexer/Register, 3-Slate
14
16
16
20
20
CD74HC356E.M
CD74HC365E.M
CD74HC366E.M
CD74HC367E.M
CD74HC368E.M
CD54HC356F
CD54HC365F
CD54HC366F
CD54HC367F
CD54HC368F
CD74HCT356E.M
CD74HCT365E.M
CD74HCT366E.M
CD74HCT367E.M
CD74HCT368E.M
CD54HCT356F
CD54HCT365F
CD54HCT366F
CD54HCT367F
CD54HCT368F
370
3BO
380
385
385
a-Input Multiplexer/Register, 3-State
Hex Buffer/Line Driver. 3-State
Hex Buffer/Line Driver, 3-5tate, Inverting
Hex Buffer/Line Driver, 3-State
Hex Buffer/Line Driver, 3-5Iate, Inverting
20
16
16
16
16
CD74HC373E.M
CD74HC374E.M
CD74HC377E.M
CD74HC390E.M
CD74HC393E.M
CD54HC373F
CD54HC374F
CD54HC377F
CD54HC390F
CD54HC393F
CD74HCT373E.M
CD74HCT374E.M
CD74HCT377E.M
CD74HCT390E.M
CD74HCT393E.M
CD54HCT373F
CD54HCT374F
CD54HCT377F
CD54HCT390F
CD54HCT393F
390
396
401
407
413
Octal Transparent Latch, 3-State
Octal D Flip-Flop, 3-State
Octal 0-Type Flip-Flop with Data Enable
Dual Decade Ripple Counter
Dual 4-Blt Binary Ripple Counter
20
20
20
16
14
CD74HC423E.M
CD74HC533E.M
CD74HC534E.M
CD74HC540E.M
CD74HC541E.M
CD54HC423F
CD54HC533F
CD54HC534F
CD54HC540F
CD54HC541F
CD74HCT423E.M
CD74HCT533E.M
CD74HCT534E.M
CD74HCT540E,M
CD74HCT541E,M
CD54HCT423F
CD54HCT533F
CD54HCT534F
CD54HCT540F
CD54HCT541 F
149
418
424
429
429
Dual Retriggerable Monostable Multivibrator with Reset
Octal Transparent Latch, 3-State, Inverting
Octal 0 Flip-Flop, 3-State, Inverting
Octal Buffer Line Driver, 3-State, Inverting
Octal Buffer Line Driver, 3-State
16
20
20
20
20
CD74HC563E.M
CD74HC564E.M
CD74HC573E.M
CD74HC574E.M
CD74HC583E.M
CD54HC563F
CD54HC564F
CD54HC573F
CD54HC574F
CD54HC583F
CD74HCT563E,M
CD74HCT564E,M
CD74HCT573E.M
CD74HCT574E.M
CD74HCT583E.M
CD54HCT563F
CD54HCT564F
CD54HCT573F
CD54HCT574F
CD54HCT583F
418
424
390
396
434
Octal Transparent Latch, 3-State, Inverting
Octal 0 Flip-Flop, 3-State, Inverting
Octal Transparent Latch, 3-State
Octal 0 Flip-Flop, 3-State
4-Bit BCD Full Adder w/Fast Carry
20
20
20
20
16
CD74HC597E.M
CD74HC640E.M
CD74HC643E.M
CD74HC646E.M
CD74HC648E.M
CD54HC597F
CD54HC640F
CD54HC643F
CD54HC646F
CD54HC648F
CD74HCT597E.M
CD74HCT640E.M
CD74HCT643E.M
CD74HCT646E.M
CD74HCT648E,M
CD54HCT597F
CD54HCT640F
CD54HCT643F
CD54HCT646F
CD54HCT648F
636
439
439
444
444
8-Bit Shift Register with Input Storage
Octal Bus Transceiver, 3-State, Inverting
Octal Bus Transceiver, 3-State, True/Inverting
Octal Bus Transceiver/Register, 3-State
Octal Bus Transceiver/Register, 3-State, Inverting
16
20
20
24
24
CD74HC670E.M
CD74HC688E.M
CD74HC4002E.M
CD74HC4015E,M
CD74HC4016E.M
CD54HC670F
CD54HC688F
CD54HC4002F
CD54HC4015F
CD54HC4016F
CD74HCT670E.M
CD74HCT688E,M
CD74HCT4OO2E.M
CD74HCT4015E.M
CD74HCT4016E.M
CD54HCT670F
CD54HCT688F
CD54HCT4002F
CD54HCT4015F
CD54HCT4016F
451
458
462
466
637
4 x 4 Register File, 3-State
8-Bit Magnitude Comparator
Dual4-lnput NOR Gate
Dual4-Stage Static Shift Register
Quad Bilateral Switch
16
20
14
16
14
CD74HC4017E.M
CD54HC4017F
CD74HC4020E.M
CD54HC4020F
CD74HC4024E.M
CD54HC4024F
CD74HC4040E.M
CD54HC4040F
CD74HC4046AE.M CD54HC4046AF
CD74HCT4017E.M
CD74HCT4020E.M
CD74HCT4024E.M
CD74HCT4040E.M
CD74HCT4046AE.M
CD54HCT 4017F
CD54HCT4020F
CD54HCT4024F
CD54HCT4040F
CD54HCT4046AF
472
478
483
488
493
Decade Counter/Divider with 10 Decoded Outputs
14-Stage Binary Ripple Counter
7-Stage Binary Ripple Counter
12-Bit Binary Counter
Phase-Locked Loop with veo
16
16
16
16
16
CD74HC4049E.M
CD74HC4050E.M
CD74HC4051E.M
CD74HC4052E.M
CD74HC4053E.M
CD54HC4049F
CD54HC4050F
CD54HC4051 F
CD54HC4052F
CD54HC4053F
-
CD74HCT4051E.M
CD74HCT4052E.M
CD74HCT4053E.M
CD54HCT4051F
CD54HCT 4052F
CD54HCT 4053F
510
510
514
514
514
Hex Inverting HIGH-la-LOW Level Shifter
Hex HIGH-la-LOW Level Shifter
8-Channel Analog Multiplexer/Demultiplexer
Dual 4-Channel Analog Multiplexer/Demultiplexer
Triple 2-Channel Analog Multiplexer/Demultiplexer
16
16
16
16
16
CD74HC4059E.M
CD74HC4060E.M
CD74HC4066E.M
CD74HC4067E.M
CD74HC4075E.M
CD54HC4059F
CD54HC4060F
CD54HC4066F
CD54HC4067F
CD54HC4075F
CD74HCT4059E,M
CD74HCT406OE,M
CD74HCT4066E,M
CD74HCT4067E.M
CD74HCT4075E.M
CD54HCT4059F
CD54HCT4060F
CD54HCT4066F
CD54HCT4067F
CD54HCT4075F
523
530
536
542
548
Programmable Divide by "N" Counter
14-Stage Binary Counterw/Oscillator
Quad Bilateral Switch
16-Channel Analog Multiplexer/Demultiplexer
Triple 3-lnput OR Gate
24
16
14
24
14
CD74HC4094E.M
CD74HC4316E.M
CD74HC4351E.M
CD74HC4352E.M
CD74HC4353E.M
CD54HC4094F
CD54HC4316F
CD54HC4351 F
CD54HC4352F
CD54HC4353F
CD74HCT4094E.M
CD74HCT4316E,M
CD74HCT4351E.M
CD74HCT4352E,M
CD74HCT4353E.M
CD54HCT4094F
CD54HCT4316F
CD54HCT4351F
CD54HCT 4352F
CD54HCT 4353F
552
638
638
639
639
8-Stage Shift-and-Store Bus Register
Quad Analog Switch
Analog MUX w/Latch
Analog MUX w/Latch
Analog MUX w/Latch
16
16
20
20
20
CD74HC4510E.M
CD74HC4511E.M
CD74HC4514E.M
CD74HC4515E.M
CD74HC4516E.M
CD54HC4510F
CD54HC4511F
CD54HC4514F
CD54HC4515F
CD54HC4516F
CD74HCT4510E,M
CD74HCT4511E.M
CD74HCT4514E,M
CD74HCT4515E.M
CD74HCT4516E,M
CD54HCT451OF
CD54HCT4511F
CD54HCT4514F
CD54HCT4515F
CD54HCT4516F
559
569
574
574
559
Up/Down Counter, BCD
BCD-to-7-Segment Latch/Decoder/Driver
4-to-16-Line Decoder/Demultiplexer w/lnput Latch
4-to-16-Line Decoder with Input Latches
Up/Down Counter, Binary
16
16
24
24
16
CD74HC4518E.M
CD74HC4520E,M
CD74HC4538E.M
CD74HC4543E.M
CD74HC7030E
CD54HC4518F
CD54HC4520F
CD54HC453BF
CD54HC4543F
CD74HCT4518E.M
CD74HCT4520E.M
CD74HCT4538E.M
CD74HCT4543E.M
CD74HCT7030E
CD54HCT4518F
CD54HCT4520F
CD54HCT4538F
CD54HCT4543F
580
580
586
594
640
Dual Synchronous BCD Counter
Dual 4-Bit Synchronous Binary Counter
Dual Precision Monostable Multivibrator
BCD-to-7-Segmen! Latch/Decoder/Driver for LCDs
9-Bit x 64 Word FIFO Register, 3-State
16
16
16
16
28
CD74HC7038E.M
CD74HC7046E.M
CD74HC7266E.M
CD74HC40102E,M
CD74HC40103E,M
CD54HC703BF
CD54HC7046F
CD54HC7266F
CD54HC40102F
CD54HC40103F
CD74HCT7038E.M
CD74HCT7046E.M
CD54HCT703BF
CD54HCT7046F
-
-
CD74HCT40102E,M
CD74HCT40103E,M
CD54HCT40102F
CD54HCT40103F
641
641
600
604
604
9-Bit Bus Transceiver w/Latch
Phase-Locked Loop with In-Lock Detection
Quad Exclusive NOR Gate
8-Bit Synchronous BCD Down Counter
8-Bit Binary Down Counter
24
16
14
16
16
CD74HC40104E,M
CD74HC40105E,M
CD74HCU04E.M
CD54HC40104F
CD54HC40105F
CD54HCU04F
CD74HCT40104E,M
CD74HCT40105E,M
CD54HCT40104F
CD54HCT40105F
-
-
613
619
628
4-Bit Bidrectional Universal Shift Register, 3-State
4 Bits x 16 Words FIFO Register
Hex Inverter (Unbuffered)
16
16
14
-
-
-
-
Note: Add package suffix code to part number on all orders.
E = Dual-In-Line Plastic Package - Temp. Range = -40 0 to + 85°C.
F = Dual-In-Line Frit-Seal Ceramic Package (CERDIP) - Temp. Range = _55° to + 125°C.
H = Chip - Temp. Range -55° C to 125°C.
M = Dual-In-Line Surface Mounted Package - Temp. Range = _40° to + 85° C.
=
--------------------------______________________________________ 5
Product Selectors
Product Selection Guide
Type
Function/Description
CD54fl4
Classification
Page
SSI
SSI
SSI
SSI
SSI
SSI
SSI
SSI
48
52
56
68
80
88
92
462
SSI
SS!
SSI
SSI
SSI
SSI
SSI
72
84
96
125
548
600
SSI
SSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
SSI
SSI
60
628
155
160
298
298
298
380
380
385
385
429
429
510
510
FF
FF
FF
FF
FF
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
104
109
134
139
144
232
238
243
342
396
401
424
424
396
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
215
220
226
279
285
363
636
451
466
552
640
613
619
NAND/NOR Gates
HC/HCTOO
HC/HCT02
HC/HCT03
HC/HCT10
HC/HCT20
HC/HCT27
HC/HCT30
HC/HCT4002
Quad 2-lnput NAND Gate
Quad 2-lnput NOR Gate
Quad 2-lnput NAND Gate with Open Drain
Triple 3-lnput NAND Gate
Dual 4-lnput NAND Gate
Triple 3-lnput NOR Gate
8-lnput NAND Gate
Dual 4-lnput NOR Gate
HC/HCT08
HC/HCT11
HC/HCT21
HC/HCT32
HC/HCT86
HC/HCT4075
HC7266
Quad 2-lnput AND Gate
Triple 3-lnput AND Gate
Dual 4-lnput AND Gate
Quad 2-lnput OR Gate
Quad 2-lnput EXCLUSIVE-OR Gate
Triple 3-lnput OR Gate
Quad Exclusive NOR Gate
HC/HCT04
HCU04
HC/HCT125*
HC/HCT126*
HC/HCT240*
HC/HCT241*
HC/HCT244*
HC/HCT365*
HC/HCT366*
HC/HCT367*
HC/HCT368*
HC/HCT540*
HC/HCT541*
HC4049
HC4050
Hex Inverter/Buffer
Hex Inverter (Unbuffered)
Quad 3-State Buffer
Quad 3-State Buffer
Octal Buffer/Line Driver; 3-State; Inverting
Octal Buffer/Line Driver; 3-State
Octal Buffer/Line Driver; 3-State
Hex Buffer/Line Driver; 3-State
Hex Buffer/Line Driver; 3-State Inverting
Hex Buffer/Line Driver; 3-State
Hex Buffer/Line Driver; 3-State; Inverting
Octal Buffer/Line Driver; 3-State; Inverting
Octal Buffer/Line Driver; 3-State
Hex Inverting HIGH-to-LOW Level Shifter
Hex HIGH-to-LOW Level Shifter
HC/HCT73
HC/HCT74
HC/HCT107
HC/HCT109
HC/HCT112
HC/HCT173*
HC/HCT174
HC/HCT175
HC/HCT273
HC/HCT374*
HC/HCT377
HC/HCT534*
HC/HCT564*
HC/HCT574*
Dual JK Flip-Flop with Reset; Negative-Edge Trigger
Dual D-Type Flip-Flop with Set and Reset; Positive-Edge Trigger
Dual JK Flip-Flop with Reset; Negative-Edge Trigger
Dual JK Flip-Flop with Set and Reset; Positive-Edge Trigger
Dual JK Flip-Flop with Set and Reset; Negative-Edge Trigger
Quad D-Type Flip-Flop with Set and Reset; Positive-Edge Trigger; 3-State
Hex D-Type Flip-Flop with Reset; Positive-Edge Trigger
Quad D-Type Flip-Flop with Reset; Positive-Edge Trigger
Octal D-Type Flip-Flop with Reset; Positive-Edge Trigger
Octal D-Type Flip-Flop; Positive-Edge Trigger; 3-State
Octal D-Type Flip-Flop with Data Enable; Positive-Edge Trigger
Octal D-Type Flip-Flop; Positive-Edge Trigger; 3-State; Inverting
Octal D-Type Flip-Flop; Positive-Edge Trigger; 3-State; Inverting
Octal D-Type Flip-Flop; Positive-Edge; 3-State
HC/HCT164
HC/HCT165
HC/HCT166
HC/HCT194
HC/HCT195
HC/HCT299*
HC/HCT597
HC/HCT670*
HC/HCT4015
HC/HCT4094
HC/HCT7030*
HC/HCT40104*
HC/HCT40105
8-Bit Serial-In/Parallel-Out Shift Register
8-Bit Parallel-In/Serial-Out Shift Register
8-Bit Parallel/Serial-In Serial-Out Shift Register
4-Bit Bidirectional Universal Shift Register
4-Bit Parallel Access Shift Register
8-Bit Universal Shift Register; 3-State
8-Bit Shift Register with Input Storage
4 x 4 Register File; 3-State
Dual 4-Stage Static Shift Register
8-Stage Shift-and-Store Bus Register; 3-State
9-Bit x 64 Word FIFO Register; 3-State
4-Bit Bidirectional Universal Shift Register; 3-State
4 Bits x 16 Words FIFO Register
AND/OR/EXCLUSIVE-OR Gates
64
Inverters/Buffers/Bus Drivers
Flip-Flops
Shift/FIFO Buffer/Multiport Registers
*Types with a bus driver output stage.
6
Product Selectors
Product Selection Guide (Cont'd)
Type
Classification
Page
CD54174
HC/HCT85
HC/HCT181
HC/HCT182
HC/HCT280
HC/HCT283
HC/HCT583
HC/HCT688
Arithmetic Circuits
4-Bit Magnitude Comparator
4-Bit Arithmetic Logic Unit
Look-Ahead Carry Generator
9-Bit Odd/Even Parity Generator/Checker
4-Bit Full Adder with Fast Carry
4-Bit BCD Full Adder with Fast Carry
8-Bit Magnitude Comparator
MSI
MSI
MSI
MSI
MSI
MSI
MSI
119
248
254
347
351
434
458
HC/HCT93
HC/HCT160
HC/HCT161
HC/HCT162
HC/HCT163
HC/HCT190
HC/HCT191
HC/HCT192
HC/HCT193
HC/HCT390
HC/HCT393
HC/HCT4017
HC/HCT4020
HC/HCT4024
HC/HCT4040
HC/HCT4059
HC/HCT4060
HC/HCT4510
HC/HCT4516
HC/HCT4518
HC/HCT4520
HC/HCT40102
HC/HCT40103
Counters
4-Bit Binary Ripple Counter
Presettable Synchronous BCD Decade Counter; Asynchronous Reset
Presettable Synchronous 4-Bit Binary Counter; Asynchronous Reset
Presettable Synchronous BCD Decade Counter; Synchronous Reset
Presettable Synchronous 4-Bit Binary Counter; Synchronous Reset
Presettable Synchronous BCD Decade Up/Down Counter
Presettable Synchronous 4-Bit Binary Up/Down Counter
Presettable Synchronous BCD Decade Up/Down Counter
Presettable Synchronous 4-Bit Binary Up/Down Counter
Dual Decade Ripple Counter
Dual 4-Bit Binary Ripple Counter
Decade Counter/Divider with 10 Decoded Outputs
14-Stage Binary Ripple Counter
7-Stage Binary Ripple Counter
12-Stage Binary Ripple Counter
Programmable Divide by UN" Counter
14-Stage Binary Ripple Counter with Oscillator
Up/Down Counter, BCD
Up/Down Counter, Binary
Dual Synchronous BCD Counter
Dual 4-Bit Synchronous Binary Counter
8-Bit Synchronous BCD Down Counter
8-Bit Binary Down Counter
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
129
205
205
205
205
260
260
269
269
407
413
472
478
483
488
523
530
559
559
580
580
604
604
HC/HCT151
HC/HCT153
HC/HCT157
HC/HCT158
HC/HCT251
HC/HCT253'
HC/HCT257'
HC/HCT258
HC/HCT354'
HC/HCT356'
HC/HCT4051
HC/HCT4052
HC/HCT4053
HC/HCT4067
HC/HCT4351
HC/HCT4352
HC/HCT4353
Analog and Digital Multiplexers/Demultiplexers
8-lnput Multiplexer
Dual 4-lnput Multiplexer
Quad 2-lnput Multiplexer
Quad 2-lnput Multiplexer; Inverting
8-lnput Multiplexer; 3-State
Dual 4-lnput Multiplexer; 3-State
Quad 2-lnput Multiplexer; 3-State; Non-Inverting Outputs
Quad 2-lnput Multiplexer; 3-State; Inverting Outputs
8-lnput Multiplexer/Register; 3-State
8-lnput Multiplexer/Register; 3-State
8-Channel Analog Multiplexer/Demultiplexer
Dual 4-Channel Analog Multiplexer/Demultiplexer
Triple 2-Channel Analog Multiplexer/Demultiplexer
16-Channel Analog Multiplexer/Demultiplexer
Analog Multiplexer with Latch
Analog Multiplexer with Latch
Analog Multiplexer with Latch
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
184
189
200
200
315
321
326
330
370
370
514
514
514
542
638
639
639
HC/HCT42
HC/HCT137
HC/HCT138
HC/HCT139
HC/HCT147
HC/HCT154
HC/HCT237
HC/HCT238
HC/HCT4511
HC/HCT4514
HC/HCT4515
HC/HCT4543
Decoders/Encoders
BCD to Decimal Decoder (1-01-10)
3-to-8 Line Decoder with Latch; Inverting
3-to-8 Line Decoder/Demultiplexer; Inverting
Dual 2-to-4 Line Decoder/Demultiplexer
10-to-4-Line Priority Encoder
4-to-16-Line Decoder/Demultiplexer
3-to-8-Line Decoder/Demultiplexer with Address Latches
3-to-8-Line Decoder/Demultiplexer
BCD-to-7-Seg ment Latch/Decoder/D river
4-to-16-Line Decoder/Demultiplexer with Input Latches
4-to-16-Line Decoder/Demultiplexer with Input Latches
BCD-to-7-Segment Latch/Decoder/Driver lor LCDs
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
100
634
169
174
179
194
635
169
569
574
574
594
Function/Description
'Types with a bus driver output stage.
7
Product Selectors
Product Selection Guide (Cont'd)
Function/Description
Type
Classification
Page
SSI
SSI
MSI
637
536
638
MSI
MSI
MSI
MSI
MSI
MSI
MSI
MSI
304
304
310
439
439
444
444
641
SSI
SSI
76
165
FF
MSI
MSI
MSI
MSI
MSI
114
335
390
418
418
390
MSI
MSI
MSI
,MSI
149
291
149
586
' MSI
MSI
MSI
356
493
641
Analog Switches
CD54n4
HC/HCT4016
HC/HCT4066
HC/HCT4316
Quad Bilateral Switch
Quad Bilateral Switch
Quad Analog Switch
HC/HCT242*
HC/HCT243*
HC/HCT245*
HC/HCT640*
HC/HCT643*
HC/HCT646*
HC/HCT648*
HC/HCT7038*
Quad Bus Transceiver; 3-State; Inverting
Quad Bus Transceiver; 3-State
Octal Bus Transceiver; 3-State
Octal Bus Transceiver; 3-State Inverting
Octal Bus Transceiver; 3-State True/Inverting
Octal Bus Transceiver; 3-State
Octal Bus Transceiver; 3-State; Inverting
9-Bit Bus Transceiver with Latch
HC/HCT14
HC/HCT132
Hex Inverting Schmitt Trigger
Quad 2-lnpllt NAND Schmitt Trigger
HC/HCT75
HC/HCT259
HC/HCT373*
HC/HCT533*
HC/HCT563*
HC/HCT573*
Dual 2-lnput Bistable Transparent Latch
8-Bit Addressable Latch
Octal Transparent Latch; 3-State
Octal Transparent Latch; 3-State; Inverting
Octal Transparent Latch; 3-State; Inverting
Octal Transparent Latch; 3-State
HC/HCT123
HC/HCT221
HC/HCT423
HC/HCT4538
Dual
Dual
Dual
Dual
Bus Transceivers
Schmitt Triggers
Latches
One-Shot Multivibrators
Retriggerable Monostable Multivibrator with Reset
Monostable Multivibrator with Reset
Retr-iggerable Monostable Multivibrator with Reset
Retriggerable Precision Monostable Multivibrator
Phase-Locked Loops (PLL)
HC/HCT297
HC/HCT4046A
HC/HCT7046
Digital Phase-Locked Loop Filter
Phase-Locked Loop with VCO
. Phase-Locked Loop with In-Lock Detection
*Types with a bus driver output stage.
8 _____________________________________________________________________
Product Selectors
Product Classification Chart
MULTIVIBRATORS
GATES
Single-level
Flip-Flops/Latches
Multi-level
Multl-
NOR/NAND
Bullers
Bus
function
Decoders!
Schmitt
ORlAND
line-Drivers
Drivers
ACt
Encoders
Trigger
Flip-Flops
CD54/74HC/HCT
CD54/74/HC/HCT
CD54n4HC/HCT
Latches
HC/HCT02
HC/HCTOO
HC/HCT08
HC/HCT240_
HC/HCT125
HC/HCT86
HC/HCT42
HC/HCT14
HC/HCT73
HC/HCT03,
HC/HCT1a
He/HeT11
HC/HCT241e
HC/HCT126
HC7266
HC/HCT137
HC/HCT132
HC/HCT74
HC/HCT259
HC/HCT27
HC/HCT20
HC/HCT21
HC/HCT244-
HC/HCT241
He/HeT107
HC/HCT373.
HC/HCT4002
HC/HCT30
HC/HCT32
HC/HCT36S_
HC/HCT244
HC/HCT139
HC/HCT109
HC/HCT533-
HC/HCT4075
HC/HCT36S_
HC/HCT365
HC/HCT147
HC/HCT112
HC/HCT563-
HCIHCT367_
HC/HCT366
HC/HCT154
HC/HCT173.
HC/HCT573·
HC/HCT368.
HC/HCT367
HC/HCT237
HC/HCT174
HC/HCT540.
HC/HCT368
HC/HCT238
HC/HCT175
HC/HCT541·
HC/HCT540
HC/HCT4511
HC/HCT273
Monoslable
HC/HCT541
HC/HCT4514
HC/HCT374.
HC/HCT123
HC/HCT4515
HC/HCT377
HC/HCT221
HC/HCT534·
HC/HCT423
HC/HCT4538
Level
HC/HCT138
He/HeT7S
Inverters
Shifters
HC4049
HC/HCT04
HC/HCT564·
HC4050
HCU04
HC/HCT574·
COUNTERS
REGISTERS
PHASE
DIGITAL
Binary
FIFO
Mulliporl
Shift
Buffer
Synchronous
MULTIPLEXERS
Ripple
BILATERAL
INTERFACE
SWITCHES
CIRCUITS
LOCKED
LOOPS
CD54/74HC/HCT
CD54/14HC/HCT
CD54/74HC/HCT
HC/HCT93
HC/HCT160
HC/HCT151
HC/HCT279
HC/HCT4016 ...
Bus
HC/HCT390
HC/HCT161
HC/HCT153
HC/HCT4046A
HC/HCT4066 ...
Transceivers
HC/HCT166
HC/HCT393
HC/HCT162
HC/HCT157
HC/HCT7046
HC/HCT4316 ...
HC/HCT242.
HC/HCT194
HC/HCT4020
HC/HCT163
HC/HCT158
Analog
HC/HCT243.
HC/HCT195
HC/HCT4024
HC/HCT190
HC/HCT251
Multiplexersl
HC/HCT245·
HC/HCT299.
HC/HCT4040
HC/HCT191
HC/HCT253
Demultiplexers
HC/HCT640.
HC/HCT597
HC/HCT4060
HC/HCT192
HC/HCT257·
HC/HCT4051
HC/HCT643.
HC/HCT4015
HC/HCT40103
HC/HCT193
HC/HCT258
HC/HCT4052
HC/HCT64S.
HCJHCT4094
HC/HCT4017
HC/HCT354.
HC/HCT4053
HC/HCT648.
HC/HCT40104.
HC/HCT4510
HC/HCT356.
HC/HCT4067
HC/HCT7038-
HC/HCT164
HC/HCT40105
HC/HCT165
HC/HCT7030
HC/HCT670
HC/HCT4516
HC/HCT4351
HC/HCT4518
HC/HCT4352
HC/HCT4520
HC/HCT4353
HC/HCT40102
DISPLAY DRIVERS
ARITHMETIC CIRCUITS
Addersl
ALU/Rate
Comparators
Multipliers
Parity
For
For
Generatorl
LCD
LED
Drive
Drive
Checker
CD54/74HC/HCT
HC/HCT85
HC/HCT181
HC/HCT283
HC/HCT182
CD54174HC/HCT
HC/HCT280
HC/HCT4543
HC/HCT4511
See Decodersl
Encoders
, Open Drain
A. Quad type
• With Bus Driver output stage
______
~
________________________________________________________ 9
Product Selectors
Typical Dual-In-Llne
Plastic Package
Typical Dual-In-Line
Frit-Seal Ceramic (CERDIP) Package
Typical SO (Small Outline)
Plastic Package
10 ____________________________________________________________________
Technical Overview
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 11
Technical Overview
HC/HCT Family Description
The RCA HC/HCT series of high-speed CMOS integrated
circuits (QMOS) includes a functionally complete set of
LSTTL equivalent types and selected equivalent CMOS
CD4000 series types. The CD4000 series types selected
are unique to the CMOS process. These types are readily
produced by the highly versatile CMOS technology, but
cannot be implemented by the more restrictive bipolar
technology. Each CMOS circuit function is offered in two
basic logic series, as follows:
1. CDS4174HCTXXXX-series types - feature LSTTL
input-voltage-level compatibility and provide highspeed CMOS direct drop-in replacements of LSTTL
devices.
2. CDS4174HCXXXX-series types - feature CMOS
input-voltage-level compatibility and are intended for
use in new second-generation all-CMOS systems.
In addition, RCA offers a third category, CDS4174HCUXX,
which includes unbuffered types intended for linear or
high-speed oscillator applications.
The HC/HCT family consists of a comprehensive set of
buffers, transceivers, and registers that are popular in
computer systems. A wide variety of popular logic, MUX's,
encoders/decoders, counters, arithmetic units, mulitvibrators, display drivers, and phase-lock loops complete the
family.
Shown below is a breakdown of the HC/HCT family by
logic function:
Series Features
CD54HCXXXX and CD74HCXXXX Series
• 2 to 6V operation.
• High noise immunity: N'L = 30%, N,H
Vee = 5V.
CD54HCTXXXX and CD74HCTXXXX Series
• 4.5 to 5.5V operation.
• Direct LSTTL input logic compatibility
V,L = 0.8V(max), V,H = 2.0V (min)
• CMOS input compatibility
I,L, I'H S;luA at VOL, VOH
Quantitative Comparison of HC/HCT and LSTTL
Logic Types
RCA's HC and HCT logic types have many outstanding
advantages when compared with the conventional highcurrent LSTTL logic types which these types can replace
in existing and new equipment designs that require devices operating at frequencies in the 20-30 MHz range.
Table I compares significant operating characteristics of
the HC/HCT vs. LSTTL logic families.
Table I - Quantitative Comparison of HC/HCT
and LSTTL Logic Types
Characteristic
The HC/HCT Family
Device Function
Inverters/Buffers/Bus Drivers
Flip-Flops/Latches
Bus Transceivers
Registers
Counters
Decoders/Encoders
Multiplexers (Analog & Digital)
Multivibrators
Schmitt Triggers
Phase-Lock Loops
Bilateral Switches
Arithmetic Circuits
Gates
Number of
Types
14
20
8
13
23
12
17
4
2
3
1. Quiescent Power
-per Gate
-per FF
-4 Stage Counter
-per Transceiver/Buffer
5.5mW
10mW
95mW
60mW
10MHz
Frequency
~~~~
10MHz
5.5mW 20mW
10mW 15mW
0.24mW 2.4mW 24mW
95mW
120mW
0.25mW 2.5mW 25mW
60mW
90mW
3. Operating Supply
Voltage
• Functionally and pin compatible with industry 54 and
74 LSTTL -series and CD4000B-series types.
• Fan-out (over temperature):
Standard Outputs - 10 LSTTL loads
Bus-Driver Outputs - 15 LSTTL loads
0.025mW
0.05mW
O.4mW
0.1mW
0.2mW 2mW
20mW
0.15mw 1.5mW 15mW
HC/HCT Family Features
• CMOS outputs for maximum noise margins.
74 Series
LSTTL
Frequency
O.1MHz 1MHz
NOTE: Each function is available in both an HCT and HC
version.
7
15
74 Series
HC/HCT
2. Operating Power
-per Gate
-per FF
-4 Stage
Counter
-per Transceiver/
Buffer
3
= 30% at
(HCT) 4.5V to
5.5V
(HC) 2V to 6V
4.75V to 5.25V
4. Operating
Temperature
Range
S. Noise Margin @ SV
• Wide operating temperature range:
CD74HC/HCT/HCU: -40 to +85°C
CD54HC/HCT/HCU: -55 to +125°C
LS to LS
HC to HC
HCT to HCT
f (HI/LOW)
0.7V/0.4V
1.4V/1.4V
2.9V/0.7V
• Balanced propagation and transition times.
• Significant power reduction compared to LSTTL
logic.
6. Input Switching
Voltage
Variation with Temp.
Vs± 60mV
Vs ± 200 mV
• Alternate source - Philips/Signetics
12 _______________________________________________________________________
______________________________ TechnlcalOverview
Table I - Cont'd
7. Output Drive Current
a) Source Current at
VOH= 2.4V
b) Sink Current
Std. Logic (Voe)
BUS Logic (Voe)
VoL=0.5V
74 Series
HC/HCT
74 Series
LSTTL
-SmA
-400uA
4mA (0.33V)
6mA (0.33V)
12mA
4mA (O.4V)
12mA (O.4V)
24mA
Moreover, the metal gate must overlap the source and
drain to allow for alignment tolerances. These conditions
result in higher overlap capacitances than those present in
aMOS devices. The metal-gate process also employs
deeper diffusions than those in the aMOS process and,
consequently, has larger junction capacitances.
Vcc
it:-H3-+
{c----l--l
l
8. Typ. Output
Transition Time"
6ns
6ns
hLH
trHL
9. Typical Gate Propag8tion
Sns/Sns
Delay": tPHutPLH
Vee = 5V, CL = 15pF
10. Typical FF Propagation Delay:
Vee = 5V, CL = 15pF
14ns
tPLH
14ns
tPHL
15ns
6ns
Sns/11ns
~p*
~n
Yr---- =
1:
;:!:::
I
l
92CS·37075
15ns
22ns
Fig. 1 - Parasitic capacitances in a CMOS inverter
11. Typ. Clock Rate
of an FF
50MHz
33MHz
-luA
luA
-0.4. to -O.SmA
40uA
13. 3-State Output
Leakage Current
±5uA
±20uA
14. Reliability
%/1000 hours at 60%
Confidence
.0019
(RCA Report)
.OOS
(RADC Report)
12. Input Current
I,L
I'H
"Loading coefficient = 0.055ns/pF (both HCIHCT and
LSTTL)
HC/HCT IC Structure
The high speeds and low quiescent power dissipation that
characterize the RCA HC/HCT family are made possible
by utilizing a three-micron, self-aligned silicon gate CMOS
process. The three-micron process minimizes the internal
parasitic capacitances of the circuit, which results in
increased switching speed.
The polysilicon gates of the transistors are deposited over
a thin gate oxide before the source and drain diffusions
are defined. Ion implantation is then used to form the
source and drain areas, with the polysilicon gates acting
as a mask for the implantation. The source and drain are
automatically aligned to the gate, hence the expression
"self-aligned-gate" process. In this manner, gate-to-source
and gate-to-drain capacitances are minimized. Junction
capacitances, which are proportional to the junction area,
are also reduced because of the shallower diffusions. Fig.
1 shows the paraSitic capacitances in a CMOS inverter.
In contrast, the source and drain areas in a metal-gate
CMOS process are formed before the gate is deposited.
The aMOS structure features a three-micron gate length;
the CD4000 series structure has a gate length of seven
microns. The equation for the drain current of a MOSFET
::~ = K':~~~h [ (gate voltage) - (threshold voltage) ]2
where K' is the "beta" of the MOSFET. Therefore, a shortter gate length results in higher drive capability, which in
turn increases the speed at which a transistor can charge
or discharge capacitance.
The polysilicon in a silicon-gate process is also an interconnect layer, thus, there are three levels of interconnect
(diffusion, polysilicon, and metal) instead of the two layers
(diffusion and metal) present in a metal-gate process. This
situation aids in making a more compact die. Fig. 2 compares the cross sections of the seven-micron metal-gate
CMOS siructure and the three-micron QMOS structure.
Input Characteristics
The inputs of QMOS devices are voltage-level sensitive,
and do not require current, except for input leakage. The
definitive switching characteristics for the HC and HCT
versions are illustrated in Figs. 3 and 4, respectively.
System designers require the actual MIN/MAX range of
expected input switching voltage over the temperature
range of -55°C to +125°C. This vital information is contained in the curves of Figs. 5 and 6 for the HC and HCT
families, respectively.
The unbuffered HCU04 hex inverter has one stage of
active inverting logic from input to output and, therefore,
is a special case for input switching voltage as shown in
Fig. 7.
___________________________________________________________________ 13
Technical Overview
(a) CD4000B Serle.
n-Channel
p·Channel
~~!$$<>«!r«(W$S$~$ii~~
I
n-substrate
I
~'-------------------------------120p------------------------------~'
92CM·37086
(b) aMOS
p·Channel
n·Channel
~
n+
p-
n+
~
p-
p+
p+
n·Substrate
4Sp
92CM·37086
Fig. 2 - Crossectional view of (a) the seven-micron
CD4000B Series structure and (b) threemicron OMOS structure
...
...
~
4
;o
3
~3
... 1
0,
>
=
Vee
5V
TA =2S'C
~2
.....
=>
=>
o VS'=S--!;--'--:!-2--""=-3-'-4:---05
Vee
1.4~ 3
Vss
VILIMAXl
2.5V
VIHIMINl
30%VCC 50%VcC 70%VCC
INPUT VOLTAGE
Vlb.~~l
5 Vee
VI~.~MJNI
INPUT VOLTAGE
92CS'37093Rl
Fig. 3 - Typical switching characteristics
of RCA HC series types
Vee
= 4.SV
TA
=2S'C
=
Vee = 5.5 V
TA =25'C
I
I
I
I
I
I
I
I
-60 mV :
~~;:.~I
+60"mY
I
I
I
!ATTA =-5S'C
i\..
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2.05
MIN.
+60 mV
ATTA = +12S'C
92CS-38886
Fig. 5 - Actual MiniMax switching characteristics
of RCA HC series types
I
I
I
ATTA +12S'C
I
+100mV
I ATTA =-5S"C
.. 3
;!
"
g
~
2.85
MAX.
-100 mY
~
o
'\.
I
I
>,
INPUT VOLTAGE (VII) - V
14
I
I
I
I
I
I
I
I
I
I
I
=
I
I
--~~~------~
I
-60 mY
I
ATTA -55 'CI
I
Vee = 5.5V
TA =2S'C
Vee
4.5Y
TA =2S'C
I
I
""
I
I
I
I
Fig. 4 - Typical switching characteristics of RCA HCT
series types
I
I
-100m
I
ATTA =1
I
+12S'C 1
I
I
I
I
I
+100mV
I ATTA=-55'C
I
I
I
~:
\..1
1.16
1.64
MIN.
MAX.
INPUT VOLTAGE (VI) - V
92CS- 3 •••7
Fig. 6 - Actual MiniMax switching characteristics
of RCA HCT series types
Technical Overview
>
g~4
w
~
~ 3
g
~
2
I
I
1.9 MIN.
2.5 TYPICAL
3.0 MAX.
Vee = 4.SV
TA = +125·C
Vee = 5V
TA = 25·C
Vee
TA
=
S.5V
= +125 *C
INPUT VOLTAGE (V11-V
92CS- 38888
Fig. 7 Actual MiniMax and typical switching characteristics of the HCU04 Unbuffered Hex Inverter
limited LSTTL temperature range is the only convenient
temperature range when using LSTTL characteristics.
Noise Immunity and Noise Margin
Table II shows the HC, HCT, and HCU input noise
immunity and noise margin for use in those applications
where like members of the HC, HCT, and HCU families
interface with each other at a nominal supply voltage of
5V. Output voltages are also shown.
Whenever the HCT output drives either an LS or HCT
input, there is an improvement in noise margin over the
LSTTL family driving itself or driving HCT. This improvement is especially true for noise margin high where the
superior output sourcing current of the rail-to-rail QMOS
output swing is far superior to the limited totem-pole pullup output voltage of LSTTL
Table lI(a): Noise Immunity and Noise Margin (Vee = 5V).
Vil max.
VIH min.
VOL max.
VOH min.
Noise Margin Low (VNMl)
Noise Margin High (VNMH)
HC
1.5V
3.5V
O.1V
4.9V
1.4V
1.4V
HCT
O.8V
2V
O.1V
4.9V
O.7V
2.9V
Input Current
HCU
1V
4V
O.5V
4.5V
O.5V
O.5V
Fig. 8 is a plot of typical HC/HCT device input current vs.
temperature for a Vee of 6V. This actual performance of
under 1.5nA over the temperature range of -55° C to
+125°C contrasts with maximum family and JEDEC standard input leakage current limit of 100nA for T = -55°C to
+25°C, and a limit of 1,ua at TA = 85°C and +125°C. The
reason for this difference in performance vs. ratings is
high-speed testing limitations associated with test system
resolution and the measurement of settling time. A secondary reason is that the limits are end-of-life, thus allowing
some leakage current shift due to minor externally introduced foreign material or moisture.
Table lI(b) shows noise immunity and noise margin voltages for standard HCT devices interfacing with LSTTL
logic types with a fully loaded HCT or LSTTL output at Vee
= 4.5V, and a temperature range of O°C to +70°C. This
Table lI(b) - Noise Immunity and Noise Margin for,
HCT and LS Device Interfacing
HCT
O.8V
2V
LSTTL
O.8V
2V
HCT- LS
LS- HCT
V,l MAX
VIH MIN
-
VOL MAX
VOH MIN
O.33V
4.4V
O.4V
2.7V
-
-
-
-
VNMl
VNMH
O.47V
2.4V
O.4V
O.7V
LS-LS
-
HCT-HCT
-
-
-
O.4V
O.7V
O.7V
2.4V
__________________________________________________________________ 15
TechnlcalOveNiew _____________________________________________________________
Vee
POLY
INPUT o--'VI."""'--"f---'IIVV-"1---+ LOGIC
R
Fig. 9 - Resistor-diode protection network used on inputs
of HC/HCT devices to protect device gate oxide from
electrostatic discharge damage(ESD).
?- ?
92CS-38889
Fig. 8 -Typical HC/HCT input current Vs. temperature
Vee
-yi
Input Termination
The very low HC/HCT input current and hence, high input
resistance is primarily due to low-level leakage currents of
the input ESD protection diodes shown in Fig. 9. This
'excellent input buffering characteristic of CMOS logic IC's
is fundamental to the wide range of very low power applications from pure logic to wide range RC oscillators, high
a crystal oscillators, etc. However, in no situation should
this high input resistance be left floating or unterminated.
Inputs may be tied directly to Vee or GND via resistors of
up to 1Mohm; the upper limit is only related to ac noise
immunity, i.e., pick up.
Comparing HC/HCT unused input terminations to LSTTL
logic, puts the flexibility of aMOS into a very positive light.
It is a stated LSTTL design rule that unused inputs be terminated to Vee via a 1.2kohm resistor and not tied directly
to GND or Vee nor left floating.
One additional note on HC/HCT input terminations. There
are several bidirectional (transceiver) logic types in the
aMOS family with common 110 pins. These 1/0 pins do
not have the input poly resistor (R) of Fig. 9. Hence, these
pins cannot be terminated directly to Vee or GND. A terminating resistor to Vee or GND of 10kohm is recommended.
Input/Output ESO Protection
HC/HCT device inputs have a resistor-diode protection
network, shown in Fig. 9, that protects the gate oxide from
electrostatic discharge (ESD) damage. The network provides protection to levels typically greater then 2kV in all
modes pertaining ·to the input, as shown in Fig. 10. The
2kV figure was arrived at by testing devices in the ESD test
circuil·shown .in Fig. 11 while conforming to the MIL-STD38510 requirements.
IN
='OUT
~
T
A-
A
Vee
IN
= OUT
~
IN
Vee
= OUT
- ~
~
Vee
IN
OUT
?
V .
Vee
IN
OUT
Vee
IN
OUT
=
~
Vee
IN
oUT
=
~~
V~~~~
~~
A~~~
Fig. 10 - HC/HCT ESD test modes
22M
+n-.AAA_~
HIGHVOLTAGE
SUPPLY
-I
Cw HUMAN BODY CAPACITANCE TO GROUND
Rs' BODY SOURCE RESISTANCE
The. recommended handling practices for aMOS devices
are similar to those described in RCA Application Note
ICAN-6525, "Guide to Better Handling and Operation of
. CMOS Integrated Circuits" .
92CS -37074
Fig. 11 - Test circuit used to measure electrostatic discharge (ESD) in HC/HCT circuits. The rise time at the
output terminaL should be 13 ± 2nS.
. 16 ____________________________________________________________________
________________________________ .TechnicalOverview
Input Interaction
Another effect of the input-protection network is the
imposition of a parasitic transistor between adjacent input
pins. Fig. 12 shows this transistor.
Furthermore, RCA devices, except for special cases such
as transceivers and analog switches or multiplexer signal
inputs, can reliably· operate with the ±1.SV rule without
logic errors. Beyond ±1.SV, maximum forward current
poses a second limitation with respect to the Vee and GND
rail. This aMOS and JEDEC rating is ±20mA of transient
current maximum forced into inputs or outputs.
Latch-Up
92CA·37D78R1
Fig. 12 - Parasitic transistor caused by input-protection
network.
This parasitic transistor may cause undesirable interaction
between adjacent inputs if the input level is greater than
Vee+Vdiode. RCA aMOS devices minimize the alpha
(ex: =IE/le) to less than O.OS. This feature of RCA aMOS
inputs permits· proper logic operation in the presence of
transients and also allows high-to-Iow voltage translation
via series input resistors. The typical value of ex: for aMOS
ICs is .001. Fig. 13 illustrates how control of ex: in RCA
aMOS devices provides for safe conversion of 12V control
logic levels to SV HC system logic simply by insertion of a
100k ohm resistor in each input. The only disadvantage is
that logic signals are delayed by 1-2uS and therefore, this
scheme works well only with rather slow 12V control logic
as for example, in automotive applications. When the input
diodes are used as clamps for logic level translation, the
input current should be kept to 2mA or less.
Vee
100kO
~
Definition
Latch-up within CMOS IC structures may be initiated or
triggered by voltage overshoot or undershoot at inputs,
outputs, or supply terminals. A high transient voltage or
current at anyone or combination of these terminals may
initiate turn-on of an SCR-type 4-layer diode parasitic bipolar device, as shown in the simplified diagram of Fig. 14.
This parasitic structure, when triggered on, keeps the
supply voltage below the Vee voltage and thus permits a
high supply current of several hundred mA to flow (see
Fig. 14). The resistor values of r e , rbb ' and rbb'2 are
dependent on circuit layout geometry and p+ and n+ doping levels.
0---+-------._--0 Vee
'c
PARASITIC
PNP
5V
A
12V
B
100 kO
+--
lOUT
92CS-38923
92CS-38921
II
=
1~'~:n ~ 63J1A
10 = cc II
VIL(B)
= 0.05 x 63 J.lA = 3.15 JiA
= 3.15 pA x 100 kO = 0.315 V
V1l max (spec.)=1.5 V
Noise Margln=1.5 V -0.315 V=1.2 V Approx.
Fig. 13 - 12V-to-SV logic-level conversion at HC
inputs using 100kOhm series resistors
Input-Voltage Considerations and Maximum Forward-Diode Input Current Limits
As a general rule, CMOS logic devices employing input
clamp diodes (Fig. 9) to minimize ESD effects should be
operated between the power supply rails. If the input series polysilicon resistor shown in Fig. 9 is not considered,
then the rule is:
-O.SV SV ,N S(Vee +O.SV)
This rule is the industry standard (JEDEC Std. No 7) and
is intended to keep users from damaging devices because
the devices of some HC/HCT device manufacturers the
devices do not have the built-in input series polysilicon
resistor. RCA HC/HCT data sheets continue to show the
conservative rating established by JEDEC. However, RCA
HC/HCT device inputs are capable of meeting the following rating: -1.SVSV ,NSVee +1.SV.
Fig. 14 - Simplified diagram of CMOS 4-layer diode
structure
The lower the value of these resistors, the less voltage
drop that will occur. A much higher trigger current, therefore, will be required to induce turn on of the SCR structure shown in Fig. 14.
Also important are established layout rules and process
parameters that minimize the current gain (Beta) of the
parasitic NPN and PNP transistors shown in Fig. 14.
Latch-Up Capability
The trigger current that could potentially trigger latch-up
of aMOS ICs is typically ±BOmA at any input or output
terminal. Measurements are made at all terminals (see
next section for preferred measurement technique), so
that these terminals have a minimum acceptable latch current of ±40mA. The absolute maximum rating in the
aMOS data sheet and in the industry JEDEC Standard
No.7 is ±20mA. The possibility for transient currents in
applications are more likely to appear at input terminals
where interfaces could cause voltage transients. The voltage required to induce the ±40mA measured capability
and the ±BOmA typical capability of aMOS ICs as illustrated in Fig. 1S, is established by the aMOS built-in 120
ohm minimum current-limiting polysilicon resistor at logic
inputs.
____________________________________________________________________ 17
Technical Overview
Equations:
VT = ITR
+ Va + Vee
R = 120 ohms
Va = 0.7V
Vee = 4.5V
-VT = -ITR - Va
If the quiescent value of Icc is out of specification, the
input and output structure should be electrically checked
to determine if the I/O circuitry is damaged and latch-Up
did not occur. Further device analysis may be required to
verify if latch-Up did indeed occu r.
Values:
Vee
VT = 40mA X 0.12k ohms + 0.7V + 4.5V = 10V min.
VT = SOmA X 0.12k ohms + 0.7V + 4.5V = 14.SV typo
-VT = -40mA X 0.12k ohms - 0.7V = -5.2V min.
-VT = -SOmA X 0.12k ohms -0.7V = -10.3V typo
Vee
(A)
(B)
Vee
92CS-38922
Fig. 15 Input latch transient voltage determination
As developed in Fig. 15, the minimum and typical ±VT
transient input voltages required to induce either ±40mA
or ±SOmA are relatively large, and far greater than the
transients induced in 5V systems where 2 or 3 volts of ringing transients can be induced via wiring inductance effects.
This ±40mA QMOS capability is truly a "latch-up free"
condition for operation in a 2V to 6V system. If transients
are induced in a particular application beyond +10V/-5.2V,
then the use of external series-limiting resistors are advised
to keep transient currents below ±40mA. Another consideration is unused inputs. If unused aMOS inputs are tied
to a Vee of +5.5V and the Vee of the QMOS IC is temporarily grounded, for example, in a 2-power supply system, or
when PC cards are replaced with power on, no possibility
of latch-up will exist because the input curr'ent will be
limited to ±40mA via the built-in 120-ohm polysilicon
series resistor.
Vee
OR
GND
(D)
(e)
92CS~38920
Fig. 16 - Test set-up for positive and negative trigger
current
-11'10
Measuring Latch-Up Sensitivity
Caution
The test methods that follow can damage devices if the
following precautions are not strictly observed.
• Apply currents for 1ms (min) to 5 seconds (max).
• Limit power supply currents to 200mA.
• Allow a cool-down period between successive tests
to be equal to or greater than the time that is required
to apply trigger current.
• These tests may be safely adapted to bench-testing
with meters or use of a curve tracer
1. Static Input or Output Triggering for Latch-Up
Vee supply to 200mA
For input triggering connect other inputs to Vee or GND
--i-vee MAX·I---'--------~
92CS-38919
Fig. 17 - Latch test waveforms
2. Vec Triggered Latch-Up Test by Over-Voltage on
Vee (Fig. 18)
Latch-up can occur if the voltage of the power supply is
raised above the absolute maximum supply voltage rating.
Apply a Vee overvoltage of 2X Vee max. referenced to
GND using a 100-mA limited supply.
Vee
All valid logic conditions are subject to test.
For Output Triggering (Figs. 16c/d):
• -10 - Active outputs must be set low
• +10 - Active outputs must be set high
• 3-State outputs - Also set output to highimpedance state
Vee
ANY
VALID
LOGIC
CONDITION
DEVICE
UNDER
TEST
Apply trigger current first (Fig. 17)
• Apply ±I, or ±lo(Fig. 16)
• Raise Vee to ±Vee max.
• After the trigger duration, reduce trigger current to
zero
• If Icc is less than its quiescent value, the device is not
latched.
t2CS-3egie
Figure 1S: Test set-up for Ve over-voltage latch trigger
Measure the Vee voltage. If it is less than Vee max., the part
has latched.
18 ____________________________________________________________________
________________________________________________________________ TechnicaIOverview
Output Characteristics
Vee
QMOS outputs make use of a complementary symmetry
transistor configuration, which is different from the LSTTL
totem-pole output; both outputs are shown in Fig. 19.
QMOS outputs meet the voltage-level requirements
necessary to interface to QMOS inputs, and the drive and
current requirements needed to interface to bipolar inputs;
i.e., TTL, LS, ALS, AS, FAST, etc.
+----1--0
The outputs of the QMOS devices are classified into two
categories: standard and bus drive. The two outputs
differ in the output transistor widths needed to meet
JEDEC standard drive and current requirements. Both
standard outputs and bus drive outputs may be active (2state) or 3-state with a high-impedance mode added and
where both the PMOS and NMOS transistors are off.
Another type of QMOS output is the open-drain output of
the HC/HCT 03 Quad NAND gate shown in Fig. 20. This
output has no intrinsic or added diode connected to Vee at
the output. The output of this device may be connected to
an external load terminated at up to 10V. Thus, outputs
can be pulled up above a nominal SV supply for up-level
voltage conversion.
The HC/HCT03 is the only QMOS gate type whose outputs can be used for a "wired OR" arrangement.
It~r.~S
NMOS
·Inherent diode.
92C5·37084
Fig. 21 - Inherent diodes protecting HC/HCT outputs.
Output Protection
The outputs in a QMOS device are protected from ESD
damage by diodes. Figure 21 shows these diodes. These
intrinsic diodes are effective because of the large geometries (widths) of the output transistors. These diodes are
the drain to n-substrate junction of the p device and the
drain to p-well junction of the n device. This network provides protection to voltage levels typically greater than 3kV
in all ESD discharge modes pertaining to the output (see
Fig. 9).
Output Currents
QMOS outputs are specified for both CMOS and LSTTL
loads. CMOS inputs are voltage sensitive and the only
current is leakage current. The output voltage test for
CMOS interfacing is specified for 10 at ±20uA (20 CMOS
loads). The outputs are also specified at 10 = 4mA (10
LSTTL loads) and 6mA (15 LSTTL loads) for standard and
bus-drive outputs, respectively. The corresponding VOL
(max) and VOH (min) for the outputs, are illustrated in
Table III.
rOUTPUT
~ 9.
OUTPUT
,. CMOS O"'P"
(b) LSTTL Output
92C5-31085
9205·31085
Fig. 19 - Comparison of HCIHCT (a) and LSTTL (b)
Vee
The maximum current per output pin (10) is ± 2SmA and
±3SmA for standard and bus-drive outputs, respectively.
This maximum current rating is specified when the outputs are in their active regions: -O.SV
~RL
~tf~_J
When the output voltage exceeds Vee or is below ground
by greater than SOOmV, the output protection diodes turn
on and conduct current. The maximum diode transient
current, 10K, should not exceed ±40mA to avoid latch-Up
as described earlier.
92CS- 38917
Fig. 20 - HCIHCT 03 output circuit
Table III - Output Drive Specifications
Test Conditions/Limits (Vee =4.5V)
Characteristic
10
25°C -40 to 85°C -55 to 125°C Unit
High-Level Output
Voltage, VoH(min)
-20uA
-4mA
-6mA
(Bus)
4.4
3.98
3.98
4.4
3.84
3.84
4.4
3.7
3.7
V
V
V
Low-Level Output
Voltage, VoL(max)
20uA
4mA
6mA
(Bus)
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
____________________________________________________________________ 19
TechnlcalOveNlew __________________________________________________________
Output-Current and Interfacing Capability
A comparison of the output drive capabilities for aMOS
with those of LSTTL is as follows:
LSTTL capability is usually expressed in unit loads
(ULs) where the load is specified to be an input of the
same family. This specification assures that the worst
case low and high input thresholds will be met and the
existing margins of noise immunity preserved.
aMOS capability is expressed as source/sink current at
a specified output voltage. Since aMOS requires virtually no input current, the unit load concept does not
apply.
With a specified output drive of 0.4mA at 0.4V, the aMOSto-aMOS interface capability exceeds 1000 ULs, and with
a 20uA/0.1V specification, the aMOS capability is 20ULs.
Each standard aMOS output has a drive capability of ten
LSTTL loads and maintains a VOL of O.4V over the full
temperature range. Bus driver outputs can drive 15 LSTTL
loads under the same conditions.
The output drive capabilities of aMOS expressed in
LSTTL unit loads are shown in Table IV.
Output Curves
...
w
z'"
ZE
~I....... :111111 IIIIIII
co
:0 ....
o.z
Y":l
!; I:!
3
0 ..
0:0
.. U
i1~ 2
~iii
Iii
1
92CS- 38915
40 SUPPLY VOLTAGE (II
EXPECTED MINIMUM
ATTA - 25·C
~g
~~
20
85·C
125·C
Note to Figs. 22 to 25: The expected minimum curves are
included as an aid to equipment designers, and are tested
only at the points indicated on device data sheets.
o
2
4
6
OUTPUT VOLATGE (Vol
=V
8
10
92CS-38914
SUPPLY VOLTAGE (Vccl- 6 V
2.0
T
!;
~§
) - 4.5 V
T -25
...w
H30
~I
Output current derating versus temperature is shown in
Fig. 22 and is valid for all types of output. Output source
and sink drives at Vee = 2, 4.5, and 6V are given in Figs. 23
to 26 which show output currents versus output voltages.
These curves indicate the typical output current at 25°C
and minimum output currents that can be expected at
25°C, 85°C, and +125°C, and can also serve as a design
aid in interface applications and for calculating transmission line effects on charging highly capacitive loads.
2
OUTPUT VOLTAGE (Vo) - V·
=25 ·C (TVI')
1.5
o -
~g
~ ....
;t z
:EI:!
EXPECTED MINIMUM AT TA
1.0
.. a:
0:0
zu
=25·C
85·C
125·C
5~
- a: 0.5
~o
0.0
-100
o
-50
0
50
100
2
150
4
6
OUTPUT VOLTAGE (Vo)-V
AMBIENT TEMPERATURE (TA) _·c
8
10
92CS-38913
92CS-3891G
Fig. 22: Output current derating vs. ambient temperature.
Fig. 23: Standard output n-channel sink current (Ioel for
Voc=2V, 4.5V, and 6V.
Table IV: Comparison of Output Drive Capabilities
LS Device
Output Drive
HC/HCT
Equivalent
Output
Type
Output
Drive
74LSOO
74LS138
74LS245
74LS374
4 mA 10 UL
4 mA 10 UL
12mA30UL
12mA30UL
74HCOO
74HC138
74HC245
74HC374
Standard
Standard
Bus
Bus
4mA
4mA
6mA
6mA
10 UL
10 UL
15 UL
15 UL
20 ____________________________________________________________________
Technical Overview
OUTPUT VOLTAGE (Vol - V
w
-2
0
0:
::0
0
m
..J",
-4
~ E
Zl
"'00
J:J:
-6
c.."i"
.... ;
::Oz
-8
t:~
5~
~o
-10
'Z"
C
i'!m
OUTPUT VOLTAGE (VoI-V
92CS- 38909
92CS-389IZ
OUTPUT VOLTAGE (Vol - V
'"(jjZ
..J
-10
..J",
-20
~ E
ZI
-40
9-::.
.... ;:
::0 ....
~~
::00:
00:
0:::0
:I: J:
::Oz
a. w
0::0
Co
O:w
2i~
-50
~I
"'OS
/>.,
-30
W
z'"
zE
Z::o
i'!o
mm
co
.... =-
~~
wo
>
iii:
C
"'
::0
lD
-60
OUTPUT VOLTAGE (Vol - V
92CS-38908
92CS- 38911
OUTPUT VOLTAGE (Vo-V)
4
5
'z"
(jj
z'"
",E
51
,,-::.
.... 0
::o=a. ....
.... z
::Ow
00:
0:0:
w::o
>0
iii:
C
"'
::0
lD
OUTPUT VOLTAGE (Vol - V
92CS-3891Q
Fig. 24: Standard output p-channel source current (-loH)
for Vcc=2V. 4.5V. and 6V.
92CS-38907
Fig. 25: Bus-driver output n-channel sink current (Iod for
Vcc=2V. 4.5V. and 6V.
__________________________________________________________________ 21
TechnlcalOveNlew __________________________________________________________
Dynamic Characteristics
OUTPUT VOLTAGE (vol- V
The RCA aMOS family is designed to meet the dynamic
switching speeds and operating frequency of low-power
Schottky TTL. When compared to metal-gate CD4000 and
74C series CMOS, aMOS shows a 10 to 1 improvement in
ac performance. aMOS types feature balanced propagation delays and transition times specified at conditions
similar to LSTTL at a nominal Vee =5V and CL = 15pF, so
that the user can relate to the equivalent LSTTL specification. Switching speed limits for aMOS are given at a more
realistic Vee of 4.5V and a CL of 50pF. Test waveforms for
the HC and HCT types are shown at the end of this
section.
Capacitive Load (C L) Determination
92CS-38906
The external capacitive loading (Cc) seen by a aMOS
output is required to calculate the propagation delay and
operating power dissipation of a logic function. The three
components of CL at a logic node are:
1. n C'N where n is the fan-out.
2. m COUT where m is the number of three-state
outputs on a logic bus.
3. CSTRAY which is the effective wiring and interconnect capacitance.
CL = n C,N + (m -1) COUT + CSTRAY
111
OUTPUT VOLTAGE (Vol-V
C'N is shown in Fig. 27 for typical HCT and HC type
inputs. Note that C'N has peak values at the respective
switch pOints of HCT (1.4V) and HC(2.5V). Capacitance
on either side of the peak is a summation of package,
lead-frame, reverse-biased input diode, and CMOS gateto-source/drain capacitance. The peak capacitance results
from the Miller multiplication of C gate-to-drain in the
high-gain linear-transition region. The values of C'N that
most typically represent the average loading effect are
4pF for HCT inputs and 3pF for HC inputs. C'N for HCT
inputs is higher than that for HC inputs because of the
required large gate-to-source/drain capacitance of the
large NMOS device widths.
92CS-3B905
HCT
Vee
= 5V
TA
=25"C
He
OUTPUT VOLTS (vol- V
2
3
4
INPUT VOLTAGE (VOLTS)
.2C9-3T077R1
Fig. 27: C'N as a function of V,N.
Output capacitance (COUT) is typically 10pF for both HCT
and HC-type bus-driver outputs when these versions are
in their high-impedance state, the only state where COUT
loading is a factor.
92CS-38904
Fig. 26: Bus-driver output p-channel source current (-loH)
for Vee=2V, 4.5V, and 6V.
The wiring and interconnect capacitance (CSTRAY) is determined
by estimates of interconnect capacitance and wiring capacitance. These capacitances are highly variable because
of differences in interwiring techniques. An often used
high-speed wiring technique utilizes strip line with 100ohm characteristic impedance. CSTRAY in this case, is typically 20pF per foot. Capacitances of sockets and connectors are available from their manufacturers.
22 __________________________________________________________________
_____________________________________________________________ TechnicaIOveNiew
In a bus system, CSTRAY is the largest single CL component, as the following example illustrates:
Propagation Delay Vs. Temperature
Because an increase in temperature causes a decrease in
electron and hole mobilities, a temperature increase will
cause an increase in propagation delays. Correspondingly,
ac performance improves with lower temperatures. Typically, speeds derate linearly from 25°C at about -0.3%/oC.
Bus Specification:
No. of fan-outs (n) = 10
No. of bus drivers (m) = 5
From Equation (1):
C L = 10 X 2.5pF + 4 X 10pF + 7 X 20pF
= 25pF + 40pF + 140pF = 205pF
The propagation delay, therefore, can be computed at any
temperature between -55°C and +125°C by using the following relationship:
tpo(T) = tpo(25° C) + [(T(O C)-25) (0.003ns/0 C)l
(3)
Propagation Delays
Propagation Delays Vs. Supply 'Voltage
3.0
=
CL
50 pF
T A =2S"C
The dynamic performance of a CMOS device is related to
its drain characteristics. The drain characteristics are
related to the thresholds and gate-to-source voltage
potential, Vgs. The Vgs voltage is equal to the power
supply voltage, Vee. Therefore, a reduction in Vee
adversely affects the drain characteristics which, in turn
increases the propagation delays. An increase in Vee
decreases the propagation delays.
1.0
3
4 4.5
5
SUPPLY VOLTAGE (Vee)-V
(a)
The voltage range of the HCT version is 5V ± 10%. Over
this range, the effects of propagation delays on performance are minimal. However, the voltage range recommended for the HC version is 2 to 6V. Over such a wide
range, the effects on dynamic performance of propagation
delay and operating frequency (See Fig. 28) are appreciable.
1.4
>- 1.2
0
z
UJ
::J
0
1.0
a:
"0
0.8
..
0.6
HCT
HC
UJ
Propagation Delay Vs. Capacitance
UJ
N
Propagation delay vs. capacitance for the RCA family of
HCIHCT types is similar to that of LSTTL types which
HC/HCT types may replace in present or new applications.
:::i
:;
a:
0
z
0.4
0.2
To determine a propagation delay maximum limit at any
value of capacitive loading up to 300pF, the following
equation is used:
a
3
4
5
6
SUPPLY VOLTAGE (VCC) -
7
8
9
10
V
92CS-38903
tpo (Ce) = tpo (50pF) + t(Ce) [C L
-
50pFl
(2)
Where:
Fig. 28: Typical switching speed characteristic versus
supply voltage normalized to 4.5V.
tpo(Ce) = maximum propagation delay at the desired C L
tpo(50pF) = maximum propagation delay from device
data sheet at 2V, 4.5V, or 6V (See Table V).
t(Ce) Maximum (ns/pF) multiplying factor from the following table:
Vee
2V
4.5V
6V
(b)
t(Ce) (nS/pF)
Std. Output
Bus Output
0.272
0.187
0.102
0.068
0.082
0.056
Output Transition Times
Table V shows the RCA standard and maximum ratings
for output transition times applicable to all standard and
bus-driver outputs. Typical values are approximately onehalf the maximum values. Practical unspecified minimum
values are one-fourth the limit values.
_________________________________________________________________ 23
TechnlcalOverview _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Table V - Output Transition Time Limits for C L = 50pF
Output
Vee(V)
Maximum Output
Transition Times (ns)
TA - 25°C
TA -125°C
TA=85°C
Standard
2
4.5*
6
75
15
13
95
19
16
110
22
19
Bus
Driver
2
4.5*
6
60
12
10
75
15
13
90
18
15
*Specification for CD54HCT and CD74HCT types.
Output Transition Time Vs. Capacitive Loading
To determine the maximum output transition time on any
capacitive loading up to 300pF, the following formula is
used:
h(Ce) = h(50pF)
+ t'(C
LI
[Cl - 50 pF] (4)
Where:
h(Ce) = maximum transition time at the desired Cl
h(50pF) = limit at 2V, 4.5V, or 6V(Table V)
hN(Ce) = (ns/pF) multiplying factor from the following
table:
Vee
2V
4.5V
6V
t'(Cl ) (ns/pF)
Std. Output
Bus Output
0.544
0.204
0.170
0.374
0.131
0.110
Transition Time Vs. Temperature
Transition time at HCIHCT outputs typically changes by
-0.3%/oC. Equation (3) used to compute increase in propagation delay with temperature (see above), can also be
used to compute transition time at any temperature by
simply substituting IT for tPD.
Clock Pulse Considerations
All HCIHCT flip-flops and counters contain master-slave
devices with level-sensitive clock inputs. As the voltage at
the clock input reaches the threshold level of the device,
data in the master (input) section is transferred to the
slave (output) section. The use of voltage threshold levels
for clocking is an improvement over ac-coupled clock
inputs, however, these levels make these devices somewhat sensitive to clock-edge rates. The threshold level is
typically 50% of Vee for HC devices, and 28% of Vee for
HCT devices (1.4V at Vee = 5V). Temperature has little
effect on the clock threshold levels.
When clocking occurs, the internal gates and output circuits of the device dump current to ground. This condition
results in a noise transient that is equal to the algebraic
sum of internal and external gound plane noise. When a
number of loaded outputs change at the same time, it is
possible for the chip ground reference level (and therefore, the clock reference level) to rise by as much as
500mV. If the clock input of a positive-edge triggered
device is at or near its threshold during a noise transient
period, multiple triggering can occur. To prevent this condition, the rise and fall times of the clock inputs should be
less than 500ns at Vee = 4.5V, the data sheet maximum
value.
In the HCIHCT family, several flip-flops have a Schmitttrigger circuit at their clock input. This circuit increases
the maximum permissable rise/fall time on the clock waveform. The RCA flip-flop types HCIHCT 73, 74, 107, 109
and 112, have special Schmitt-trigger circuits which
increase their tolerance to slow rise/fall times and to high
levels of ground noise.
Maximum permissible input-clock pulse-frequency ratings
on each clocked device type data sheet requ.ires a 50%
duty cycle input clock. At these rated frequencies, the
outputs will swing rail-to-rail, assuming no dc load on the
outputs. This feature is a very conservative and highly reliable method of rating clock-in put-frequency limits which
for HC/HCT devices, equal or exceed LSTTL ratings.
Power Consumption
The power consumption of a HCIHCT device is composed of two components: one static, the other dynamic.
The static component is the result of quiescent current
caused principally by reverse junction leakage. The dynamic component results from transient currents required to
charge and discharge the capacitive loads on logic elements, that is; transient currents caused by internal and
external capacitance, and transients resulting from the
overlapping of active p and n transistors. Internal chip
power consumption is represented by the value Cpo.
Two equations are used to compute the total IC power
consumption. The first equation (A) is applicable to an HC
or HCT device when the inputs are driven from GND to
Vee (rail-to-rail), as follows:
Equation (A):
P= Poe + PAC
P = leeVee + CpoVee2 f,
+ ~ Cl Vee2fo
Where:
Icc = Quiescent Current (Ref. Table VI)
Vee = Supply Voltage
f, = Input Frequency
fo = Output Frequency
Cpo = Device Equivalent Capacitance
Cl = Load Capacitance
The second equation (B) is applicable only to an HCT
device where specific input pins are driven at LSTTL levels
defined as V'N = Vee - 2.1V:
Equation (B):
P= Poe + PAC
P = leeVee + 8 leeVeeD + CpoVee2f,
+ ~ Cl Vee2 fo
Where:
8 lee = Added dc current when V'N = Vee -2.1V
(LSTTL level)
D = Duty cycle of clock (% of time HIGH)
24 ____________________________________________________________________
Technical Overview
Table VI - Temperature - Dependent Ratings
LIMIT
V,N
Ll.lee additive
dc current per
input pin
Vee
TA = 25°C
-40 to
+85°C
-55 to
+125°C
typ
max
74HCT
MAX
54HCT
MAX
Units
100
360
4S0
490
uA
4.SV
Vee 2.1V
to
S.SV
(1-Unit)
Table VII HC/HCT and LSTTL Maximum Quiescent
Current at Vee - 5V
Device
Complexity
SSI
FF
MSI
HC/HCT
Typical
25°C
2 nA
4nA
8 nA
LSTTL
12SoC
25°C
Limit
8SoC
125°C
2 uA
4 uA
8 uA
20uA
40uA
80uA
40uA
80 uA
160 uA
The temperature dependent ratings for Icc are given in the
table below:
HCT load table by type sh own on each data sheet:
Input
Unit Multiplier
Example:
All
XO.6
«
E
I
U
g
The source of the CPD or deVice equlvalent-power-dlsslpation capacitance is made up of 2 sources of internal device
power consumption:
1) Power consumed by charge and discharge of
internal device capacitance.
3
I-
z
w
II:
II:
:::>
CJ
The dynamic power due t o outputs is the su m of the ac
power at each output. The user must independently determine the CL and the average frequency at each output.
The latter requires estima ting the average freguency of
data nodes in a logic system. For example, for HC/HCT
cou nter types, each outpu t is inherently operating at different frequencies.
4.4 mA
8mA
10mA
to
9SmA
..
.
~
2
11.
:::>
01
z
w 1
CJ
01
w
:;
a
a
2
3
INPUT VOLTAGE (V,N) -
4
5
v
92CS-38902
Fig. 29: Icc Vs. V,N for RCA HC types
2) Power consumed through current switching transients.
Fig. 29 illustrates the typical Icc vs. V,N characteristic of
HC type devices Note that when V,N = 0.1V or (Vee
-0.1 V). zero current flows. Thus, no Ll.lcc component is
required for computing the power consumption of HC
device types. However, the transient switching components of an IC consume power and are a part of the
CPD value.
Fig. 30 illustrates the typical Icc vs. V,N characteristic of
HCT type devices. Again, if input voltages are 0.1V or
(Vee= -0.1 V). no Ll.lee value exists. Also for V ,N = O.4V,
Ll.lee is zero. If V,N, however, is an LSTTL logic high
level of (Vee -2.1V) or approximately 3V for Vee = SV,
then significant Ll.lcc does exit and is indicated in
equation (8) as the Ll.lcc component.
The special input design of RCA's HCT types greatly
reduces the value of Ll.lee such that the added power is
very small; for example, RCA's HCT power is minimal
compared to LSTTL power. If this special input circuitry were not used, the Ll.lcc values would be relatively
high as demonstrated by the dashed line in Fig. 30, and
the HCT type would not have very low power when
compared to LSTTL.
NOTE: The low value of Icc is due to a special input
design that provides a true low-power HCT
capability.
------------------------------------------------------~
Technical Overview
When Schmitt-trigger types HC/HCT14 and 132 are used
for either shaping up slow Signals or as Rt oscillators,
power is increased due to prolonged through-current. For
further information on oscillators and their power consumption, refer to RCA Application Note (ICAN-7337),
"Astable Multivibrator Design Using High-Speed aMOS
IC's".
The adverse effects of power transitions is another reason
to maintain input rise and fall times under the recommended limits. Longer transitions may cause oscillations
of logic circuits (and hence, logic errors) or premature
triggering depending on system Vee and GND noise,
which are amplified when input signals hover near the
switching voltages illustratep in Figs. 29 arid 30. To reduce
·the effects of slower tranSitions, the use of Schmitt trigger
types is recommended.
INPUT VOLTAGE (Y,N - V
Comparison to LSTTL Power
92CS-3B901
The dynamic power consumption of HC/HCT devices is
frequency dependent, but it should be noted that LSTTL
power consumption is also frequency dependent at frequencies greater than 1MHz. At frequencies less than
1MHz, the dynamic component is negligible compared to
the static component. The average power consumption of
HC/HCT and LSTTL equivalents is illustrated in Fig. 31 for
four device types. Because all of the functions in a multifunctional LSTTL device are biased when power is applied, the HC/HCT device characteristics are plotted for a
Single function and for the total package for the purposes
of comparison.
Fig. 30: lee vs. Y,N for HCT types
Because appreciable current flows during device input
switching as shown in Figs. 29 and 30, it is important to
maintain fast input rise and fall times. The JEDEC and
RCA recommended maximum input rise and fall times are:
1000 ns for Vee = 2V
500 ns for Vee = 4.5V
400 ns for Vee = 6V
Some observations from Fig. 31 are:
1) For SSI gate types, the HC/HCT power approaches
LSTTL power at about 1MHz.
Since maximum output transition times are 15ns for the
standard logic types and 12ns for bus drivers, a' designer
must only be concerned with exceeding the rise and fall
times shown above for interfacing or linear mode operation in applications such as RC oscillators, crystal oscillators, and amplifiers using the HCU04 types.
(0)
~
z
2) For higher complexity types such as the RCA HCI
HCT 138 3-of-8 line decoder/demultiplexer shown
in Fig. 31 (cl. HC/HCT power approaches LSTTL
power at above 1OM Hz.
(b)
100
TEST CONDITIONS
LSOO
Vce=5V
TA =2S-C
(4 GATES)
~
10.~e;l;L_=..;;50;;..P:;.;.F_ _~f::i""
I
II:
0.1
~
0.01
~
is
100
10'1---..3..._-~7/
i
~
C
if
0.1
0.01
1 M 10M 100M
FREQUENCY (Hz)
(e)
!i"
g
(dl
100
10
z
on
TEST CONDmONS
~
Vee
TA
eL
f
0.000', K
100M
0><&37000
100
2
10
L5243
!<
0.1
is
rr:
10M
1000
~
Z
0
iiii
1M
FREQUENCY (Hz)
82CS-37087
10K 100K 1M
0.100
w
~
= SOpF
10M 100M
FREQUENCY(Hz)
I
rr:
= 5V
= 25"<:
02C&37ooo
10K lOOK
1M
10M
FREQUENCY (HZ)
92C&37090
Fig. 31 - Power versus frequency graphs for the (a)
LS/HC/HCTOO, (b) LS/HC/HCT74, (c) LS/HCI
HCT138, and (d) LS/HC/HCT243.
26 _________________________________________________________________
Technical Overview
3) Fig. 31 implies continuous operation at the frequencies shown, however, most practical applications of logic in microcomputer systems have variable operation or data/address signal rates. The
average operating frequency is much below the
peak operating frequency - particularly in the
100KHz region where power savings over LSTTL
are several orders of magnitude.
FROM PRIMARY
POWER SUPPLY
BATTERY
RESISTOR
FOR
Power-Supply Considerations
Power-Supply Voltages
BATTERY
The RCA HC and HCU versions have a power supply
range of 2 to 6V; the absolute maximum voltage rating is
7V. The ability to use RCA's HC types with a 2V supply
makes these devices particularly useful in battery-operated
equipment, especially systems including memories that
feature 2V standby operation. The absolute maximum
supply or ground current, per pin, is ±50mA for types with
standard output drive, and ±70mA for types with bus
driver outputs.
The operating supply-voltage range for RCA's CD74HCT
types is 4.5V to 5.5V, 5V ± 10%. These figures indicate that
there is more tolerance in the regulation of the low-current
system supply than is the case with other technologies.
The maximum voltage indicated for HC and HCU versions
also applies to HCT versions. The advantages of using
HC/HCT/HCU with its wider voltage supply range are
illustrated in Fig. 32.
Ii ~ ~[:=}:D-D. ·.
>.
2
-----------
I~I
92CS·37078A1
Fig. 32: Power-supply ranges for CD74HCT, CD74HC and
CD74HCU versions of the RCA family of devices and 74LS
series types.
Battery Back-Up
Battery back-up can be easily implemented in systems of
RCA's HC/HCU devices. An example of this arrangement
is shown in Fig. 33. The minimum battery voltage required
is only 2V plus one diode drop.
In the example, RCA's High-to-Low Level Shifters (HC4049
or HC4050) are used to prevent the flow of positive input
currents into the system due to input voltage levels greater
than one diode drop above Vee. If the circuit design is such
that input voltages can exceed Vee, then external resistors
should be included to limit input currents to 2mA. External
resistors may also be necessary in the output circuits to
limit currents to 2mA, if the output can be pulled above
Vee or below GND. These currents are due to inherent
VedGND diodes that are present in all outputs, including
three-state outputs.
I
TRICKLE
CHARGE
HC/HCU
SYSTEM
SIGNAL
OUTPUTS
HIGH-TQ-LQW
LEVEL SHIFTER
TYPES HC4049,
HC4050
Fig. 33 - Example of an HC/HCU system with battery
back-up.
Power Supply Regulation and Oecoupling
The wide power supply range of 2 to 6V may suggest that
voltage regulation is not necessary, but it must be realized
that a changing supply voltage affects system speed, noise
immunity and power consumption. Because noise immunity, and even the correct operation of the circuit, can be
affected by noise spikes on the supply lines, therefore,
matched decoupling is always necessary in dynamic
systems.
Both HC and HCT types have the same power supply regulation and decoupling requirement. The best method of
minimizing spiking on the supply lines is by implementing
good power supply and ground bussing and having low ac
impedances from the Vee and GND pins of each device.
Because the minimum value of a decoupling capacitor
depends on the voltage spikes that can be allowed, it is a
general rule to restrict ground and Vee noise peaks to
400mV. A local voltage regulator on the printed-circuit
board can be decoupled using an electrolytic capacitor of
10 to 50 uFo
Localized decoupling of devices can be provided by a
22nF capacitor for every two to five packages, and a 1 uF
tantalum capacitor for every ten packages. The Vee line of
bus driver circuits and level sensitive devices can be effectively decoupled from instantaneous loads by a 22 nF
ceramic capacitor connected as close to the package as
possible.
A practical example of determining the value of a decoupiing capacitor is as follows: assume that a buffer output
sees a 100-ohm dynamic load and that the output low-tohigh transition is 5V, then the current demand is 50 mA
per output. For an octal buffer, the current demand would
be O.4A per package, in approximately 6 nS.
The following formula can also be used to determine the
value of a decoupling capacitor:
The term Q = CV is differentiated to obtain
Since
~~ = I, the equation becomes I = C
~Q =
~t
C
~V.
~t
!: .
Hence: C = ~t.
~V
____________________________________________________________________ 27
Technical Overview
For an octal buffer, assuming a change in Vee or GND of
O.4V, then;
C
=
0.4 A X 6 X 10-'S = 6 X 10-' F = 6 nF.
0.4 V
For further information on interfaCing, refer to RCA Application Note ICAN7325, "Interfacing HC/HCT QMOS Logic
with Other Families and Various Types of Loads."
Logic-Level Conversion
For further information on power-supply regulation and
decoupling, refer to RCA Application Note ICAN7329,
"Power-Supply Distribution and Decoupling for QMOS
High-Speed IC's."
The HC/HCT family contains logic-level conversion types
necessary to interface high-voltage logic levels (up to 15V
common in control and automation systems) to low voltage levels (down to 2V) as shown in Fig. 36.
Interfacing
Because of the characteristics of the CMOS output, the
HC/HCT family is very versatile in interfacing between different logic families. This capability including the corresponding fanout is illustrated in Fig. 34.
VCC=2VT08V
V,N=VeeT015V
AND GND
~?
o---t>---o
Yo=- Vee AND GND
QMOSHC4049
Note that the fanout to CMOS devices is limited only by
the input rise and fall times, which are dependent on the
capacitive loading, CL. This dependence can be computed
by the following relationship:
tR, tF = 2.2 RCL
(5)
A) HEX INVERTlNG
'CC=2VT06V
where R is the impedance of the output.
HCIHCT
4DOO
--EJ--.
HC
74C
nL. LS, ALS, S }
HClHCI'
::'
Fanout From:
-EJ- 7"
V,N=VCCT015V
AND GND
n1.., LS,ALS,S
HCl"
~?
o--{>--o
V =V
ANDQND
0
CC
QMOSHC40SO
HOtter
4000
To Corresponding Logic Families:
TTL LS ALS FAST SJAS 4000, 74C
HC/HCT
2
See
Standard Types 2 10 20
6
Text
Bus Drivers
3 15 30
10
3
Fig. 34 - HC/HCT interfacing capability and corresponding
fanout to other logic families
BI HEX NON-INVERTING
92eS-38898
Fig. 36 - High-to-Iow logic level conversion
The Quad open-drain NAND gate (HC/HCT03) is used to
convert from HC (2V to 6V) or HCT (TTL or CMOS) logic
levels up to 10V output logic levels as shown in Fig. 37 RL
can be a very wide range of values. For design of this output interface, use
10 Y MAX.
RCA's HC types cannot be driven from any of the TTL
families because the TTL output voltage high, VOH (min),
does not satisfy the HC input voltage high, V"i(min) specification. The HCT types can be directly interfaced to the
TTL families because the HCT input voltage high, V,H
(min) is less than the TTL output voltage high, VOH(min).
To meet minimum V,H requirements, HG types can use a
pull-up resistor as illustrated in Fig. 35.
Vee
- SLOWS SPEED DOWN
_ INCREASES POWER DISSlPAnON
.. ~ - DECREASES NOISE MARGIN
DECREASES FAN-OUT
/1"
-
ee
~
HL
Y,N
STOHe/HeT
OR LSTTL
LEVELS
92CS-38897
Fig 37 - Low-to-high logic-level conversion
the output N-MOS transistor characteristics of Fig. 23. The
minimum value of RL is that necessary to keep the output
current below the 25mA HC/HCT family maximum rat,ing .
A large value of Rl will prolong the output rise time.
System {Parallel} Clocking
LSTTL
He
92CS- . . . .
Fig 35 - Use of pull-up resistor to interface TTL and HC
devices.
However, the use of a pull-up resistor will not give optimum performance because as noted in Fig. 35, the resistor
tends to slow down system speed, increase power dissipation, decrease noise margin, and decrease fan-out.
When utilizing the HC/HCT family in synchronously
clocked systems the following guidelines should be followed. Because of variations in switching points between
devices, a slow clock edge could cause a logic error. If
data in one of the synchronously clocked circuits changes
before the switching point of the next sequential circuit is
reached, a logic error will occur. This situation is illustrated in Fig. 38.
VS1 = Switching point, device 1
VS2 = Switching point, device 2
tp = Propagation delay
28 ____________________________________________________________________
_______________________________ Technical Overview
Because of variations in input threshold voltages among
RCA's HC-version devices, the maximum clock-pulse rise·
or fall time should adhere to the following relationship:
t" t, (max) <2t p (max)
(6)
In a system where HC, HCT, and TTL-type families are
mixed, the maximum clock pulse rise or fall times should
adhere to the following relationship:
tR, tF (max) Vee
10k,Q
(b) Proposed low-power termination for CMOS STD bus
equivalents.
10 ko,
INPUT----o-~"V'Vv....,
QMOSLOGIC
Fig. 39 - Bus Terminations
92CS-38895
buses between cards in a system. It is possible for a circuit to pick up severe noise spikes or differential
voltages via the card edge-input protection circuit. Such
Fig. 40: Example of the card edge-in put-protection circuit.
30 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Technical Overview
Standardized Capacitance Power Dissipation (CPO) Test Procedure
The purpose of the CPO number is to allow the user to estimate the actual power consumption of his system. Therefore, the table has been set up to exercise each device in
the same manner as· it would usually be used. Devices
which are separable into independent sections are
measured on a "per section" basis, the remaining are measured on a "per device" basis. Each part number's unique
setup is listed in the "Pin Condition Table." The following
paragraphs describe the generic set up for each class of
devices:
Shift Registers: Switch the clock, adjust the data inputs
such that the shift register fills with alternate 1's and O's.
Transceivers: Switch one data input. For bi-directional
transceivers enable only one direction.
One Shots: TO BE DETERMINED
Parity Generators: Switch one input.
Priority Encoders: Switch the lowest priority input.
Rams: TO BE DETERMINED
Display Drivers: Switch one input such that approximately
half the outputs change state.
All part numbers: Measurements are to be made at TA =
25°C, VCC = 5V, and 3-state outputs both enabled and disabled.
Gates: Switch one input. Bias the remaining inputs such
that the output switches.
Latches: Toggle as ill' a flip-flop.
Flip-flops: Switch the clock pin while changing "0" (or
biasing "J" and "K") such that the output(s) change each
clock cycle. For part numbers with common clocks, exercise the "0", "J", or "K" inputs of only one flip-flop. Set the
inputs of the remaining flip-flops so they do not change
state.
Decoders I Demultiplexers: Switch one address pin,
which changes two outputs..
Data Selectors I Multiplexers: Switch one address input,
with the corresponding data inputs at opposite logic
levels, so that the output switches.
Counters: Switch the clock pin, with other inputs biased,
such that the device counts.
ALUs I Adders: Switch one least significant input bit, bias
the remaining inputs so that the device is alternately
adding 0000 (binary) or 0001 (binary) to 1111 (binary).
Since CPO is a measure of device power consumption, and
not that of the driven load, each output would ideally be
unloaded. However, this is impractical with automatic
testers which often have 30 to 40 pF hanging on each pin.
Therefore, each output which is switching should be
loaded with the standard 50 pF. The equivalent load capacitance, based on the number of outputs switching and
their frequency, is then subtracted from the measured
gross CPO number to obtain the device's actual CPO
value.
If a device is tested at a high enough frequency, static supply current will contribute a negligible amount to power
consumption and can be ignored. Thus, it is recommended
that power consumption be measured at 1 MHz and the
following formula be used to calculate CPO:
CPO =
(Vci~g)E6)
- (equivalent load capacitance)
- - - - - - - - - - - - - - - - - - - - - -_______________________________________ 31
TechnicalOveNiew _________________________________________________________
EXPLANATION OF SYMBOLS
Key
V
=vcc
(+5V)
Input pulses
G = ground
H = logic 1 (VCC) - inputs at VCC for HC types; 3.5 V for
HCT types
L = logic 0 (ground)
D = don't care - either H or L but not switching
C = a 50 pF load to ground
o = an open pin; 50 pF to ground is allowed
P = input pulse (see illustration)
o = half frequency pulse (see illustration)
R = 1 kn pull·up resistor to an additional 5 V supply other
than the VCC supply
B = both Rand C
pnn~I1VCC
...J
L.J
LJ· LJ
L
GNO
Pin Condition Table for CPO Tests
Pin Number
EquivHC/ alent
HCT Load
Types (pF)
2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
00
02
03
04
U04
50
50
0
50
50
P H C DDOGODD
C P L ODDGDDO
P H B DDOGODD
P C DOD 0 GOD 0
P C D o DOG 0 D 0
0
D
0
D
D
D
0
D
0
0
D
0
D
D
D
V
V
V
V
V
08
10
11
14
20
50
50
50
50
50
P H C D DOGODD
P
P
P
P
HOD DOG 0 D D
H D D DOG ODD
CDODOGODO
H 0 H HCGODD
0
D
D
D
0
0
C
C
0
D
D
H
H
D
0
V
V
V
V
V
21
27
30
32
42
50
50
50
50
100
P
P
P
P
C
H OHHCGODD
L DDDOGODD
H H H H H G COO
LCD DOG 0 D 0
COOOOOGOO
0
D
H
0
0
D
C
H
D
L
D
L
0
D
L
V
V
V
V
L
P
V
58
73
74
75
85
50
50
50
50
50
P D D D DOG 0 L L
P H H V DOD 0 0 0
HOPHCCGOOD
CODDVDDOOO
L H P HOCOGLL
L
G
0
L
H
C
D
G
L
H
C
D
P
L
V
H
V
0
L
0
L
C
V
86
93
107
109
112
50
47
50
50
50
P L
o L
H C
H H
P H
C
L
C
L
H
DDOGODD
0 VDDCCG
HOOGDDD
PHCCGOO
HCCOGO D
0
C
D
D
0
D
C
P
D·
D
0
D
H
D
0
V
P
V
D
D
D
H
V
V
123
125
126
132
137
100
50
50
50
100
L
L
H
P
P
P
C
C
C
L
COOOGDD
DDOGODD
DDOGODD
DDOGODD
LLHOGOO
D
0
R
V
D
D
D
C
D
D
D
0
0
0
0
0
0
0
V
V
V
C
C
V
H
P
P
H
L
0
-
-
-
-
-
-
-
-
-
-
-
-
32 _______________________________________________________________
Technical Overview
Pin Condition Table (Cont'd)
EquivHC/ alent
HCT Load
Types (pF)
138
139
147
151
153
154
157
158
160
161
Pin Number
2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19 20 21
50
100
50
PLLLLHOGOOOOOCCV
LP LCCOOGOO 0 0 D D D V
H H H H H 0 0 G C H P H H 0
0
V
DDLHCCLGLL P D D D D V
L L D D L H C GOD D D DP
D V
100
50
50
55
50
CCOOOOOOOO 0
GOO 0
00
PLHCLLOGOL L 0
L
L LV
PLHCLLOGOL L 0
L
L L V
HPDDDDHGHHCCCCCV
HPDDDDHGHH C C C C C V
-
55
100
100
D
D
C
D
D
D H G
D H G
C G P
D C G
LPG
H H C
H H C
H C C
COD
H D D
------
C
C
V V -
L
H
V
V
-
--
L
-
P
V
-
L L L
L
-------
L
H
H
V
-
162
163
164
165
166
50
200
50
25
H P D
H P D
0 H C
H P D
ODD
173
174
175
181
182
25
25
50
250
150
LLCOOOPGLL
HCODODOGPO
HCCODOOGPO
P H H L L H H L C C
H L H L H LOG C 0
190
191
192
193
194
60
53
60
50
100
D C C L L C C G D D H
D C C L L C C G D D H
DCCHPCCGDD H
DCCHPCCGDD H
HOD D D D D G HLP
195
221
237
238
240
125
100
100
50
H H L D D D D G H P C C C C C V L H P COO 0 G D D D O C 0
R V P L L L L HOG 0 0
0
0 0
C C V P L L L L HOG 0 0
0
0 0
C C V LPODODODOGDODODODCDV-
241
242
243
244
245
50
50
50
50
50
LPODODODOG
LOPDDDGOOO
LOPDDDGOOO
L POD 0 DOD 0 G
HPDDDDDDDG
DOD
COL
COL
DOD
0
0
0
0
DOD
V
V -0
DOD
0000
251
253B
257
258
259
100
50
50
50
25
D D L H C C L G L L
LLDDLHCGOD
P L H C D DOG 0 D
P L H C D DOG 0 D
LLLCOOOGOO
P D D
D D D
DOD
DOD
0
0 0
D D
P D
D L
D L
PH
7266
273
280
283
297
50
25
100
250
12
PLCODDGDDO
HCODOODDOG
L L 0 L C C G P L L
CHLCPHLGCC
HHHPOLCGDD
0
D D
POD
L
L
L
H L C
00 D
V
DO
V L H
H H
100
D
D
C
D
D
C
C
C
D
D
C
C
C
D
C
C
C
V
D
D
D D DOL
D O D DO
0
D D 0
0
C G C B C
C C P H L
C
C
C
C
C C
C C
C C
P
P
L
L
C
D
D
D
D
C
22 23 24 25 26 27 28
-
-
VVVC C
V -
L
H
L
V
V
V
V
V
C
H V -
C
C
D
-
V
L V
V
V
V V V0
D
V V-
-D 0
V
-
-
-
--
____________________________________________________________________ 33
Technical Overview _____________________________
Pin Condition Table (Cont'd)
HC/
HCT
Pin Number
Equivalent
Load
Types (pF)
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
299
354
356
365
366
250
100
50
50
50
HLLCCCCCHG
D D D D D D L H L G
DDDDDDDOPG
L P C DOD a GOD
LPCDODOGOD
0
L
L
a
a
PC C
L L P
L
L
L
DOD
DOD
C
L
L
L
L
C
L
L
V
367
377
50
50
25
25
25
LPCDODOGOD
LPCDODOGOD
LCODOODDOG
LCODOODDOG
LCODOODDOG
a
DOD
a
DOD
POD D
POD D
POD D
L
L
a
a
a
390
393
423
533
534
50
47
100
25
25
P L C 0 C C C G a a
P LCCCCGOOO
L P H C a a 0 GOD
LCODOODDOG
LCODOODDOG
aDO D D
ODD V 0 a
COR
POD 0 0
POD D a
540
573
50
50
25
25
25
LPDDDDDDDG a
0 a
a a
a 0 C LV
LPDDDDDDDG a
a a
a
0 a a C LV
LODDDDDDDG P a a
a
a
a 0 a C v
LODDDDDDDG PO a
a
a a a a
C v
LPDDDDDDDGHOOOOOOOCV
574
583
597
7597
640
25
250
25
25
50
LODDDDDDDG
HHHLLCCGCC
DDDDDDDGCH
DDDDDDDGCH
H P D D D D D D D G
P
643
646
50
50
50
100
50
HPDDDDDDDG
DLHPDDDDDD
DLHPDDDDDD
OOOLPCCGCC
L P L L L L L L L G
4002
4015
4016
4017
4020
50
100
4024
4040
4046A
4049
4050
48
4051
4052
4053
4059
4060
o
368
373
374
541
563
564
648
670
688
o
55
48
48
50
50
50
o
o
17
106
CD
H C
H C
L
V
C
C
v v -
V V
ODD
ODD
ODD
a
a
a
v
v
v
V
V
0
D 0
ODD
0
a
V
v
v -
P
P
a
a
H
D
D
a
a
a
a a
P
L LV
HOD V
HOD V
a
a a a
a
a
a
D
D
L
L
a
G
G
L
L
a
a
a
L
L
a
a
a a
a a
PO
L
L
0
a
a
L
CP LLLOGODD D
P COO 0 D D G DOC
o 0 0 0 D D G. 0 0 0
0
CCCCCCCGCC C
C C C C C C C G C P L
D
C
D
C
C
a
C
P
L
C
v
L
V
P
C
-
PLCCCCGOCO C
C C C C C C C G C P L
OCLOHOOGOO 0
v CPO DOD G DOD
VCPODODGDO D
C
C
0
0
a
a
C
a
a
0
v
C C
PO
D a
DO
v
v
0 0-
PO
a a
PO
H G
P L
0
a
0
H
C
0
a
a
H
a
a
a
L
v
v
v
L
C C
v
OOOOOLGGLL
OOOOOLGGLP
OOOOOLGGLL
P 0 H L L L L L L L
CCCCCCCGCC
C
a
a
a
v
L
0 V
LV
C v
0
-
-
-
-
-
--
---
--
-
----
C
-
v
-
C
L
V
C
a
a
L
L
-
D
D
-
-D V
D V
-
L
LV
a
C
a
C
C V
-
-
-
-
-
-
-
--
-
-
-
-
-
-
-
L
L
L
L
C
-V -
-
-
-
-.-
-
-
-
--
-
-
-
-
-
-
---
-
-
L
---
-
L
-
--
34 _____________________________________________________________
- - - - - - - - - - - - - - - - - - - -_________ TechnicaIOverview .
Pin Condition Table (Cont'd)
HC/
HCT
Equivalent
Load
Types
(pF)
4066
4067
4075
4094
4316
4351
4352
4353
4510
4511
0
0
50
250
0
o
o
o
55
200
100
Pin Number
2 3 4 5 6 7 8 9 10 11
OOOODDGOOO 0
OOOOOOOOOP
L
P L D D DOG L COD
H Q P C C C C G C C C
0 0 0 0 P D L G GOO
D
G
D
C
0
P
L
D
C
0
OOOOOOLHGG
OOOOOOLHGG
OOOOOOLHGG
LCD D L C C G L H
LLHHLLPGCC
H
H
H
C
0
P
P
P
D
0
L 0
L 0000 VL 000000 VL 0
L 0000 V
D C P V CO C V --
HPLOOOOOCO
HP LOOOOOCO
LCDDLCCGLH
PHCCCCLGDD
P H C C C C L G D D
C GOO
C GOO
CD D C
0 0 0
0
0 0 0
0
D
C
Q
D
C
Q
LOG
C C C
Q G L
V
V
C
o
0
0
V
4514
4515
4516
4518
4520
100
50
50
47
4538
4543
7030
7046A
40102
50
325
50
5
G R H P H C C GOO
H L L HLP L G C C
GGCPQQQQQQ
o C L 0 H 0 0 GOO
P H L L L L L G H L
40103
40104
40105
3
100
200
P H L L L L L G H L L
H Q D D D D D G HLP
L C P Q Q Q Q G L C C
100
12 13 14 15 16 17 18 19 20 21
V
L
V
C
D
P
L
H
D
0
0
P
D
D
0
0
0
V
V
-
0 0
0 0
VVV
0
0
0
0
22 23 24 25 26 27 28
0
0
V
-
-
-
-
H V
0
0
0
0
0
0
L
L
L
L
L
L
V
V
C
C
C
C
C
C
C
C
P
-
-
-
-
-
-
-
-
C
LLLCHV
L
C
C
L
C
C
C
C
C
H
C
P
V
V
V
-
_________________________________________________________________ 35
TechnlcalOve"lew __________________________________________________________
RCA Standardized Maximum Ratings and Recommended Operating
Conditions for CD54174HC, CD54174HCT, and CD54174HCU ,Integrated
Circuits
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ,,, ...... ,,,, .... , , " " " " . " " . " " " .... " . " .. " " " " " " . " " .. ,, .. ,, .. ,," -0.5 to +7 V
DC INPUT DIODE CURRENT, 10K (FOR V, < -0.5 V OR V; > Vee +0.5 V) ....•..•........•....••....•....•....••••••••.•.. ±20 rnA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V)' •... " " " ... " " .. ". " " " ...... " .... " " . ±20 rnA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5 V):
STANDARD OUTPUT ...••••..........••....••..•••••.•••••.•.•••••••..•.••••....•....•...•...•••.....••....•.•.. ±25 rnA
BUS DRIVER OUTPUT .. " ..... " ... " " " " " .... " " " •..... " ....... " ...... " " .. " ... " ...... , " " .. " " " .. ±35 rnA
DC Vee OR GROUND CURRENT, (Icc):
STANDARD OUTPUT .. " " " .. " .... " .... " " . " " " " . " ..... " " " ... ". " " .. " •. ". " .....•.. " ...... ". ". ±50 rnA
BUS DRIVER OUTPUT " •.... " .. " . " .. " . " . " •. " .. " ......... " . " " ..• "." .. " ...• " . " . " .... " . " . " . " " . ±70 rnA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60° C (PACKAGE TYPE E) " . " . " " " " " " .... " ..... " . " " ... " .. " " .. " .. " .... " ... ",," " . 500 mW
For TA = +60 to +85° C (PACKAGE TYPE E) .. " " .. " " " " " •... " " " . " . " " •.. " ... Derate Linearly at 8 .mW/o C to 300 mW
For TA = -55 to +100° C (PACKAGE TYPE F, H) ." ....... "." .. " ..... " . " ... " ... " . " . " •. " " . " " ... ",," "" 500 mW
For TA = +100 to +125° C (PACKAGE TYPE F, H) .. " •. " . " .... " " " .. " .. " .... " ... Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +60·C (PACKAGE TYPE M) . " " . " ". ". " " ....... " " " " .... " " " •. " •.. " " " . " " " , " .• "". 300 mW
For'r. = +60 to +85·C (PACKAGE TYPE M) ....... " . " •. " . " .•. " . " " ... " " ... " " Derate Linearly at 5 mW/·C to 175 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H " ........ ".: ..... " ....•.... " . " . " . " ... " " .... " .•. " ... " " ...•... ".""".,,. -55 to +125·C
PACKAGE TYPE E, M " " •.... " ... " .. " " " ........... " . " . " . " " " . " .. " .... " " ... " ....• ",, .•... ,, -40 to +85· C
STORAGE TEMPERATURE (T... ) ......... " ... " .•.... " . " . " ... " ... " ... " " " ......... " .... ".".".",,. -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING) :
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max. " " " .... " .... " " .. " " ....... " . " .. "",,. +265·C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only .. " .... " " ..• ". " .... " " .... " .. " .... " .... " ...... " ..... " " ... " " " " . +300· C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation' Is always within
the following rangel:
CHARACTERISTIC
Supply-Voltage Range (For T.=Full Package Temperature Range) Vee:'
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage V;\ V.
Operating Temperature T A:
CD74 Types
CD54 Types
Input Rise and Fall Times t"t,
at2V
at4.5 V
atS V
LIMITS
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vcc
V
V
V
-40
-55
+85
+125
·C
·C
0
0
0
1000
500
400
ns
ns
ns
'Unless otherwise specified, all voltages are referenced to Ground.
36~
_____________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TechnicaIOverview
Static Electrical Characteristics for CD74HC/CD54HC Types
(Table 1-JEDEC Standard No. 7A)
TemperatureOC
Symb
54HC/74HC
74HC
54HC
U
25
-40 to 85
- 55 to 125
n
i
Parameter
VCC
Test Conditions
t
v
High Level
Input Voltage
VIH
Low Level
VIL
min
max
min
max
min
max
2.0
1.5
1.5
1.5
4.5
3.15
3.15
3.15
v
6.0
4.2
4.2
4.2
v
v
2.0
0.3
0.3
0.3
v
4.5
0.9
0.9
0.9
v
6.0
1.2
1.2
1.2
v
Input Voltage
10
VI
STD
High Level
Output Voltage
VOH
Note 1
Low Level
VOL
2.0
1.9
1.9
1.9
v
20.0 -20.0
-20.0 -20.0
4.5
4.4
4.4
4.4
v
6.0
5.9
5.9
5.9
v
4.5
3.98
3.84
3.7
v
6.0
5.48
5.34
VIH
or
VIL
v
5.2
-20.0 -20.0
-
Unit
,.A
,.A
,.A
4.0 -
6.0
rnA
5.2 -
7.8
rnA
2.0
0.1
0.1
0.1
v
20.0
20.0
,.A
4.5
0.1
0.1
0.1
v
20.0
20.0
,.A
6.0
0.1
0.1
0.1
v
20.0
20.0
,.A
4.5
0.26
0.33
0.4
v
4.0
6.0
rnA
6.0
0.26
0.33
0.4
v
5.2
7.8
rnA
VI = VCC or GND
Output Voltage
VIH
or
VIL
Input Leakage
II
Current
6.0
±O.1
±1.0
±1.0
,.A
10Z
3·state Output
Off-State
6.0
±O.S
±5.0
± 10.0
,.A
Note 3
Current
Note 2
ICC
BUS
VI = VIH or VIL
VO=VCCorGND
Quiescent
Supply Current
551
6.0
FF
6.0
4.0
40.0
MSI
6.0
8.0
80.0
2.0
20.0
VI = VCC or GND
40.0
,.A
80.0
,.A
160.
10=0
,.A
Notes:
1. Not applicable to open drain outputs.
2. For digital 110 pins use loz limits
3. Also applicable to open drain outputs.
_________________________________________________________________ 37
TechnlcalOveNiew _____________________________________________________________
Static Electrical Characteristics for CD74HCT/CD54HCT Types
(Table 2-JEDEC Standard No. 7A)
Temperature· C
Symb
Parameter
54HCT/74HCT
74HCT
54HCT
25
-40 to 85
-55 to 125
VCC
U
n
Test Conditions
I
t
VIH
VIL
v
min
High Level
Input Voltage
4.5
to
5.5
2.0
Low Level
Input Voltage
4.5
to
5.5
max
min
max
2.0
0.8
min
max
v
2.0
0.8
0.8
v
10
VI
VOH
Note 1
VOL
.11
High Level
Output Voltage
Low Level
Output Voltage
4.5
4.4
4.4
4.4
v
4.5
3.98
3.84
3.7
v
4.5
0.1
0.1
0.1
v
4.5
0.26
0.33
0.4
v
5.5
±0.1
±1.0
±1.0
.,A
VIH
or
VIL
VIH
or
VIL
Unit
STD
BUS
DRIVER
-20.0
-20.0
.,A
-4.0
-6.0
rnA
20.0
20.0
.,A
4.0
6.0
rnA
Input Leakage
Current
VI =Vee or GND
I
Note 2
10Z
3·state Output
OfI· State
Note 3
Current
ICC
Quiescent
Supply Current
.II. Icc
5.5
±0.5
±5.0
±10.0
VI = VIH or VIL
.,A
Vo = Vee or GND
SSI
5.5
2.0
20.0
40.0
.,A
VI = Vee or GND
FF
5.5
4.0
40.0
80.0
.,A
10=0
MSI
5.5
8.0
80.0
160.
.,A
5.5
2.7
2.9
Additional Worst
Case Supply
Current Note 4
3.0
rnA
Per
Other
input-pin:
VI =2.4V
at Vee orGND
inputs:
10=0
Notes:
1.
2.
3.
4.
Not applicable to open drain outputs.
For digital 110 pins use loz limits
Also applicable to open drain outputs.
Total supply current = Icc + l:.II.lco
38 __________~---------------------------------------------------
_____________________________________________________________
TechnicalOve~iew
Dynamic Electrical Characteristics
Definitions
Limits
Min.
Max.
Characteristic
Symbol
Propagation Delay:
Outputs going high to low
Outputs going low to high
tpHL
tPLH
X
X
Output Transition Time:
Outputs going high to low
Outputs going low to high
hHL
hLH
X
X
Pulse Width-Set, Reset, Preset
Enable, Disable, Strobe, Clock
tWL or tWH
X
Notes
1
1,2
Clock Input Frequency
fCL
X
Clock Input Rise and Fall Time
t.cL, tfCL
X
Set-Up Time
tsu
X
1
Hold Time
tH
X
1
Removal Time - Set, Reset, Preset-Enable
tREM
X
1
Three State Disable Delay Times:
High level to high impedance
High impedance to low level
Low level to high impedance
High impedance to high level
tpHZ
tPZL
tpLZ
tPZH
NOTE:
X
X.
X
X
(1)
By placing a defining min. or max. in front of definition, the limits can change from min.
to max., or vice versa.
(2)
Clock input waveform should have a50% duty cycle and be such as to cause the outputs
to be switching from 10% Vee to 90% Vee in accordance with the device truth table.
OPERATING AND HANDLING CONSIDERATIONS
1.
2.
Handling
All inputs and outputs of RCA CMOS devices have a
network for electrostatic protection during handling.
Recommended handling practices for CMOS devices
are described in ICAN-6525. "Guide to Better Handling
and Operation of CMOS Integrated Circuits."
Operating
Operating Voltage
During operation near the maximum supply voltage
limit, care should be taken to avoid or suppress power
supply turn-on and turn-off transients, power supply
ripple, or ground noise; any of these conditions must
not cause Vcc - God to exceed the absolute maximum
rating.
Input Signals
To prevent damage to the input protection circuit, input
signals should never be greater than Vcc nor less than
Gnd. Input currents must not exceed 20 rnA even when
the power supply is off.
Unused Inputs
A connection must be provided at every input terminal.
All unused input terminals must be connected to either Vee or Gnd, whichever is appropriate.
Output Short Circuits
Shorting of outputs to Vcc or Gnd may damage CMOS
devices by exceeding the maximum device disSipation.
____________~------------------------------------------------------39
Technical Overview
Switching Waveforms for CD54174HC and CD54174HCU Integrated Circuits
CLOCK PULSE RISE AND FALL TIMES
--50%
CLOCK
-r ."'-::;-::.11",0",-%,--
GND
92CS-35126RI
Outputs should be switching from 10% Vcc to
90% VCC in accordance with device truth table.
For fmax • input duty cycle=50%.
Transition times and propagation delay times,
combination logic.
Clock-pulse rise and fall times and pulse width.
6ns
~------~~~4----------------VCC
I~~~----------GND
OTHER {
INPUTS
TIED HIGH
OR LOW
Ie
OUTPUT RL =Ikn jVCC "FOR tpLZ AND IpZL
WITH
3-STATE
OUTPUT
OUTPUT
DISABLE
GND FOR 'PHZ AND IpZH
~C}OPF
92CS-35129RI
92CS-35129R2
Three-state propagation delay wave shapes and test
circuit.
;--VCC
4'"'=-=-= - - - -= -
--
90 %
- - - - - -50%
------10%
GND
~4n4
DATA
INPUT
HC/HCT/HCU
~
LJ
t,u(H)
*
~-------VCC
'--+ __________J
----50%
'-----
GND
lCL
1 5 0 PF
OUTPUT
92CS- 35124RI
50"10
'----------------------------------------GND
*(HI OR (L1 OPTIONAL
92CS-35128RI
Setup times, hold times, removal time, and
propagation delay times for edge triggered
sequential logic circuits.
. 40. __________________________
~
________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Overview
,Switching Waveforms for CD54174HCT Integrated Circuits
6 ..
6ns
t,CL
CLOCK
--1.3V
""'-;';;-;.lO~.3:,:V:""_GNO
92CS-3~132RI
Outputs shou/~ be s"!itching from 10% VCC to 90% VCC in
accordance wIth devIce truth table. For fmax, input duty cycle=50%.
Transition times and propagation delay times, combi·
nation logic.
C/ock·pulse rise and fall times and pulse width.
~=-=-:=.
- -
1
--=--
3V
--2.7V
~---3V
- - --1.3V
54174 HC/HCT/HCU
GND
r-:-L
L-1
92CS~
1
150
CL
PF
35124RI
~-----------------------------------------GND
*(H) OR (Ll OPTIONAL
92CS-35133RZ
Setup times, hold times, removal time, and propagation
delay times for edge triggered sequential logic circuits.
OUTPUT
DISABLE
~-------~~~~-------3V
OTHER {
INPUTS
TIED HIGH
OR LOW
~~~------GND
OUTPUT
DISABLE
OUTPUT RL "Ikn jVCC 'FOR IpLZ AND tpZL
IC WITH
3·STATE
OUTPUT
GND FOR tpHZ AND I PZH
~C~OPF
92CS-35129RI
1.3 V
OUTPUTS
ENABLED
92CS-35130 R2
Three-state propagation delay wave shapes and test
circuit.
Note:
Open drain waveforms tpLZ and tpzl are the same as those for
three-state shown on the left. The test circuit is Output Rl =
1kr.l to Vcc, C l = 50 pF.
________________________________________________________________ 41
TechnicaIOveNiew _________________________________________________________
Enhanced Product
Screening
The need to achieve the enhanced reliability resulting from
burn-in screening must be determined by careful analysis of
system design and application.
Digital IC's (CD Types)
Suffix X
How many IC's are incorporated into the total system?
Standard Product
All Packages
How many devices on each board?
!
Is the proper device being used for the application?
What are the reliability goals?
What failure rates are being experienced without screening?
Cost-effectiveness of using enhanced CMOS can be determined by mutual analysis of the economic trade-offs made
possible by the following features of the program:
• Available in both plastic and frit-seal ceramic packages.
• Offered on the inqustry's broadest line of circuit functions.
• 0.025% AQL cumulative.
• Reduction in PC board reworking through fewer line
rejects.
• Lower warranty requirements through the elimination of
infant mortality failures.
Sample DC Tes125°C
AOLO.025%
Parametric and
Functional*
• Reduced incoming inspection cost by reduction or complete elimination of test procedures.
"X" Product
• Reduction of system failures and related service expenses and customer complaints.
'For the High-Speed CD54/74HC/HCT/HCU products. AC parameters are
tested
by selecting certain critical propagation delays (which vary from part
to part) as indicators of proper AC performance and sample tested to an
AQL of 0.025%.
RCA MIL-STD-883 Slash-Series HC/HCT ICs
RCA high-reliability slash-series products are available in
both CD54HCXXXX-series and CD54HCTXXXX-series
types. These devices are supplied in hermetic dual-in-line
frit packages. The CD54HC/HCT (Slash series) types are
provided to screening level /3 that corresponds to MILSTD-883, Method 5004, Class B requirements. This /3 is a
non-compliant part using glass die attach. Product is also
available as a level /3A which is a fully compliant part using
gold eutectic die attach.
Detailed information pertaining to the screening performed
can be found in the RCA "High-Reliability Integrated
Circuits" DATABOOK, SSD-230B.
Contact your RCA representative for specific timing and
availability.
Guide to the Reliability Class and Package of
RCA High-Reliability 54HC/HCT Integrated Circuits
CD54HCTOOF/3A
~L
I
PACKAGE
DESIGNATOR
RCA DEVICE
PART NUMBER
HC
HCU
= CMOS COMPATIBLE
= CMOS COMPATIBLE
HCT
= TTL COMPATIBLE
UNBUFFERED
F
=
DUAL-IN-LiNE
CERAMIC (CERDIP)
SEE TEXT ABOVE
I
SCREENING
LEVEL
3A= CLASS B
3
= CLASS B
J = LEAD LESS-CHIP
CARRIER CERAMIC
(FUTURE)
42 _______________________________________________________________________
High-Speed CMOS Macrocells
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 43
High-Speed CMOS Macrocells _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
High-Speed CMOS (HC/HCT)
Macro Cells for RCA Silicon
Circuit Board ASIC Design Program
RCA offers a unified Computer-Aided Engineering (CAE)
system that supports the high-speed CMOS (HC/HCT
QMOS) library of standard logic functions defined as Macro
Cells. The system provides not only automatic placement
and routing but also the interactive editing of a mixture of
CMOS standard cells and rectangular Macro Cells of different sizes.
The HCIHCT Macro Cells are equivalent in performance to
the high-speed CMOS HCIHCT series of standard devices
as specified in this DATABOOK; only the bond pads have
been removed and large drivers down-sized. The Macro
Cells are fully characterized and behaviorally described over
the operating voltage and temperature ranges. These capabilities provide the system designer a fast, predictable, integration path from a PC board designed with high-speed
CMOS or LSTTL, SSI/MSI discrete devices to a single
Application-Specific Integrated Circuit (ASIC) that meets all
criteria for PC board design.
The Silicon Circuit Board approach to ASIC design is distinctive because it allows the system engineer to develop a
circuit using large, predesigned, fully characterized Macros.
The characterization data for these Macros provide the
engineer with the performance information needed to evaluate the feasibility of differing design approaches quickly
and efficiently. The Macros have been developed to provide
the optimum performance available within a given technology and are guaranteed to meet these performance specifications over the stated voltage and temperature ranges. All
HC/HCT logic functions specified in RCA's QMOS family
are included in the Silicon Circuit Board family of logic
Macro Cells.
Features of the RCA Silicon Circuit Board
and Related User Benefits.
Features:
• Works with 137 high-speed CMOS (QMOS-HC/HCT)
standard logic Macro Cells
• Also works with RCA's new ACL standard part Macro
Cells
• Intermixes Macros and standard logic function elements
providing high-density designs
• Uses double-level metal technology with a polysilicon
level option
• Uses fully characterized Macro Cells behaviorally described over the operating voltage and temperature ranges
• Provides simulation based on performance of characterized parts
• Provides fully automatic placement and routing plus interactive editing
• Provides automatic generation of test patterns for use in
manufacture
• Integrates with RCA Semicustom FASTRACK system for
Standard Cells and Gate Arrays
Benefits:
• Provides high probability of first-time success
• Reduces design development time
• Converts existing HCMOSITTL boards to CMOS ASICs
• Reduces simulation costs
• Reduces parts costs
• Logic speed increase to x3 or more with high-speed process and ACL Macro Cells
How to Benefit from the RCA
Modular Approach to CMOS
ASIC Design and Fabrication
The RCA Silicon Circuit Board addresses the most difficult
areas in the development of ASICs. These areas are performance, development time, and costs. If the following
questions are part of your work assignment in the design of
Application-Specific Integrated Circuits, the answers given
here will be of significant interest to you.
1. Will the RCA ASIC approach work in my design?
The advantages of the RCA Silicon Circuit Board approach
in a specific application can best be determined by a nocost consultation with our technical staff. We can help you
make a reasoned decision whether the RCA modular approach will work in your design. And, if that is the route
selected, we will help you save engineering development
time and money by working with you on the entire program
through to final manufacturing and performance tests.
2. How long will the design take?
The overall development time will be equal to or less than
the time normally required for the development of SSI/MSI
designs. The RCA Silicon Circuit Board achieves a shortened development time because it incorporates into a
design a large number of cells containing from a handful to
thousands of gates. Not only is the actual design time
reduced, but simulation times also are substantially diminished by the utilization of behavioral modeling of these
larger functional levels.
3. Will it work the first time?
The Silicon Circuit Board uses tried and tested high-speed
CMOS cells that are fully characterized and behaviorally described. These cells have been developed to provide the optimum performance available within a given technology and
are guaranteed to meet those performance specifications
over the stated voltage and temperature ranges. Furthermore, RCA will provide any specialized support necessary
to assure first-time success.
4. How much will it cost?
This program, involving newly available CAE software and a
modular approach, can provide considerable cost savings
(as much as 60%) in combined development and die costs.
By providing a substantially more efficient methodology for
ASIC design, RCA's Silicon Circuit Board greatly reduces
engineering development costs. Additionally, the optimized
layout of the Macro Cells provides for a significant reduction in the cost of manufacturing the ASIC Chip.
44 ____________________________________________________- - - -
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ High-Speed CMOS Macrocells
How Do I Interface with RCA in
Designing a Silicon Circuit Board?
The interface between the RCA Silicon Circuit Board Program and the customer's system engineer is very flexible
and can be tailored to fit the specific needs, capabilities,
and resources of the customer. Regardless of where the
customer enters the system-and it can be anywhere in the
flow of the program, as shown in the chart of Fig. 1-RCA
will provide the support necessary to assure first-time success in the ASIC design. Following are examples of different
interface choices.
One choice is to supply RCA with an SSl/MSl-level schematic, a description of how your circuit works, and timing
information so that we can verify its operation in silicon and
generate test programs. RCA will handle simulation, placement, routing, mask tooling, and prototype production.
Another choice is for your systems engineer to capture the
schematic on a supported popular workstation using a
generic SSI/MSI library. Supply RCA with a copy of the
schematic, extracted net list, circuit description, and pattern
files on magnetic tape or a floppy disk. RCA will then handle the rest.
,.
ENGINEERING
WORKSTATION
(Men lor Graphics, Daisy,
Valid Logic, IBM PC)
SCHEMATIC CAPTURE
.!,
BEHAVIORAL LOGIC
SWITCH LEVEL
,...--
(MIMIC)
J.
ANALYZE RESULTS
USING WAVES
I
A fourth choice is for RCA to supply you with the RCA
ASIC Design System software tools that will enable you to
take your design through the layout step.
For more information on interfacing the RCA Silicon Circuit
Board and on the additional benefits this advanced design
technology can provide you, contact RCA ASIC Product
Marketing at (201) 685-6585 or (201) 685-7119.
LIBRARY
(GENESll)
Others in
Future
CMOS
NE.LlST
AUTOMATIC PLACEMENT
AUTOMATIC ROUTING
(VITAL)
1
VERIFICATION AND
TIMING ANALYSIS
~
I
L.
(ECAD/CONCEAT)
A third choice is for your system engineer to do all the
initial design work on RCA equipment at an RCA Design
Center utilizing the assistance and guidance of an RCA
applications engineer skilled in ASIC development. Again,
RCA will handle the rest.
RCA
SILICON
COMPILER
INTERACTIVE
EDITING
(VITAL)
I
TEST PATTERN
PATTERN
GENERATION
(AFTER)
GENERATION
~
PHOTO/MEBES
MASKS
92C3-40593
Fig. 1 - Flow Chart of RCA Silicon
Circuit Board Design Process
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 45
46 __________~____________~--~-----------------------------------
Technical Data
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 47
Technical Data ___________________________________________
CD54/74HCOO
CD54/74HCTOO
File Number
1464
High-Speed CMOS Logic
14
IA
18
Vee
48
12
IY
II
2A
Quad 2-lnput NAND Gate
4.
4Y
28
2Y
9 3A
GNO
8 3Y
Type Features:
• Buffered inputs
• Typical propagation delay = 7 ns @ Vee = 5V
C L = 15pF, TA = 25° C
92es - 38 528ft I
FUNCTIONAL DIAGRAM AND
TERMINAL ASSIGNMENT
The RCA-CD54174HCOO and CD54174HCTOO logic gates
utilize silicon-gate CMOS technology to achieve operating
speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices
have the abilityto drive 10 LSTTL loads. The 54HCT174HCT
logic family is functionally as well as pin compatible with
the standard 54LS174LS logic family.
The CD54HCOO and CD54HCTOO are supplied in 14-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HCOO and CD74HCTOO are supplied in 14-lead dualin-line plastic packages (E suffix) and in 14-lead dual-inline surface mount plastic packages (M suffix). Both types
are also available in chip form (H suffix).
nA
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCTj: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to
LSTTL Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity: N ,L =30%, MH=30% of Vee
@ Vee=5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L =0.8 V Max., V,H =2 V Min.
CMOS Input Compatibility
I, s: 1 pA @ VOL, V OH
nY
TRUTH TABLE
nB
92CS-36529RI
INPUTS
LOGIC DIAGRAM
OUTPUTS
nA
nB
nY
L
L
H
L
H
H
H
L
H
H
H
L
48 __________________________________________________________________
______________________________ Technical Data
CD54/74HCOO
CD54/74HCTOO
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground)
.... , , , , , , , , , .
,,,,,,,,,,.,,.
. ........ -0.5
DC INPUT DIODE CURRENT, 1« (FOR V, < -0.5 V OR V, > Vee +0.5V) ,." ...
DC OUTPUT DIODE CURRENT, 10K (FOR V, < -0.5 V OR V, > Vee +0.5V) '"
DC DRAIN CURRENT, PER OUTPUT (I,) (FOR -0.5 V < V, < Vee + 0.5V) ...
DC Vee OR GROUND CURRENT (Icc) ..
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60' C (PACKAGE TYPE E) ", .... .
,,,,,,
For T A = +60 to +85' C (PACKAGE TYPE E) ... , ... .
. , , , , , , , ........ , , , . , ... , . , ..... Derate Linearly at 8 mWI' C to
. ..... , , , , , , , , , , , , , . , , , . , ... , . , , , , , , , ........ , , , , , , , . , , . , , ,
For T. =-55 to +100' C (PACKAGE TYPE F, H) .... .
For T. = +100 to +125' C (PACKAGE TYPE F, H) ".
. . , , , , ................... , , , " Derate Linearly at 8 mW/' C tG
to + 7 V
±20mA
±20mA
±25mA
±50mA
500
300
500
300
mW
mW
mW
mW
For T. = -40 to +70' C (PACKAGE TYPE M) " , . " " . " " " . " .. " . " " " .. " " .. " ... " " " " " " " " " .. ,,",,.,,,,., 400 mW
For T. = +70 to +125'C (PACKAGE TYPE M) .............................................. Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H ".,', ...... , ... "., .............. ,"", ......... " .......... , ... " .. ,..
-55 to +125' C
PACKAGE TYPE E, M ........ , ... , ... ,", ...... " ........ , ... ".........
-40 to +85' C
-65 to +150'C
STORAGE TEMPERATURE (T",) "
LEAD TEMPERATURE (DURING SOLDERING):
+265'C
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ...... , ...... .
+300'C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA=Full Package Temperature Range) Vee:'
CD54174HC Types
CD54/74HCT Types
DC Input or Output Voltage V;n, Vou'
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t"t,
at 2 V
at 4,5 V
at6 V
LIMITS
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
V
V
V
-40
-55
+85
+125
°C
°C
0
0
0
1000
500
400
ns
ns
ns
'Unless otherwise specified, all voltages are referenced to Ground.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 49
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54n4HCOO
CD54n4HCTOO
STATIC ELECTRICAL CHARACTERISTICS
CD74HCOO/CD54HCOO
TEST
CDNDITIONS
14HC/54HC
TYPES
CD74HCTOO/CD54HCTOO
74HC
TYPES
54HC
TYPES
-401
-551
+85°C
+125°C
TEST
CONDITIONS
74HCT/54HCT
TYPES
74HCT
TYPES
54HCT
TYPES
-401
-551
+85°C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
V
10
mA
Vee
V
+25°C
V,
V
Vee
V
Min Typ Max Min Ma. Min Max
High-Level
Input Voltage
1.5
-
-
1.5
-
1.5
-
4.5 3.15
-
-
3.15
-
3.15
-
-
-
4.2
-
4.2
-
2
V"
6
low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
Vo"
CMOS Loads
or
-0.02
V,"
4.2
4.5
-
or
V,"
low-Level
Output Voltage
CMOS Loads
or
-5.2
0.02
V,"
2
-
-
0.5
-
0.5
-
0.5
4.5
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
Input Leakage
Current
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5 3.98
-
-
3.84
-
3.7
-
2
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
or
4.5
3.98
-
-
3.84
-
3.7
-
V
5.48
V,"
V"
4.5
-
10
5.5
-
-
5.34
-
5.2
-
2
-
-
0.1
-
0.1
-
0.1
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
4.5
-
-
0.26
-
0.33
-
0.4
6
-
-
0.26
-
0.33
-
0.4
V,"
±1
Any
Voltage
Between
6
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
04
V
5.5
-
-
±O.l
-
,1
--
,1
pA
5.5
-
-
2
-
20
-
40
pA
-
lOG
360
-
450
-
490
pA
V"
or
4
V,"
5.2
or
Vee
I,
-
V"
V"
TTL Loads
-
V"
-4
V"
Yo,
2
10
5.5
V"
TTL Loads
Min Typ Max Min Max Min Max
6
or
-
-
±O.l
-
-
±1
.-
Vee
Gnd
Quiescent
&Gnd
Vee
Vee
Device
or
Current
Gnd
Icc
0
6
-
-
2
-
-
20
or
40
Gnd
4.5
Additional
Quiescent
Device Current
per input pin:
1 unit load
I:l. Icc·
Vcc-2.1
10
5.5
"For dual-supply systems theoretical worst case (V,
=2.4 V. Vee =5.5 V) specification io 1.8 mAo
HCT Input Loading Table
Unit Loads"
1.8
1.1
nA
nB
·Unit load is Alec Umit spe~.j,fied
e.g .. 360 pA maX. @ 25° C.
50
~n
Stptic-Ch-a-ract-eristk:'Chart.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HCOO
CD54/74HCTOO
SWITCHING CHARACTERISTICS (Vee = 5 V, T. = 25°C,lnpul I" I, = 6 ns)
CHARACTERISTIC
Typical
SYMBOL
Propagation Delay, Data Input to Output Y (Fig, 1)
(C L=15 pi)
Power Dissipation Capacitance'
HC
tpLH
t pHL
Cpo
Unils
HCT
7
8
ns
25
25
pF
'CPO is used to determine the dynamic power consumption, per gate.
PD = Vee' Ii (Cpo:t- Cdwhere I,=input Irequency
C L = output load capacitance
Vcc = supply voltage.
SWITCHING CHARACTERISTICS (CL=50 pF, Inpul I" 1,=6 ns)
CHARACTERISTIC
Propagation Delay
Input to Oulput
(Figure 1)
Transition Times
(Figure 1)
Input Capacitance
-55°C 10 +125°C
_40° C 10 +85° C
25°C
54HC
54HCT UNITS
74HCT
HCT
74HC
HC
Min, Max. Min. Max. Min. Max. Min. Max. Min. Max. Min, Max.
135
115
2
90
ns
25
27
30
4,5
23
18
20
23
20
15
6
110 95
2
75
ns
19
22
22
19
15
4.5
15
19
16
13
6
SYMBOL Vcc
tPLH
tPHL
ITLH
ITHL
C,
-
-
-
-
10
-
10
-
-
-
-
10
-
-
10
-
-
10
-
10
pF
Vl:.
GNO _ - - ' - _ 7
vo
-
--90%
- - - - Vs
92CS-36755RI
INPUT LEVEL
Vs
Fig. 1 - Transition times and propagation delay times.
______
~
___________________________________________ 51
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC02
CD54/74HCT02
File Number
1647
High-Speed CMOS Logic
Quad 2-lnput NOR Gate
Type Features:
• Buffered Inputs
• Typical Propagation Delay = 7ns
@ Vee = 5v. GL= 15pF. TA =25° G
FUNCTIONAL DIAGRAM and
TERMINAL ASSIGNMENT
The RCA-CD54174HC02 and CD54/74HCT02 logic gates
utilize Silicon-gate CMOS technology to achieve operating
speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices
have the ability to drive 10 LSTTL loads. The CD54174HCT
logic family is functionally as well as pin compatible with
the standard 54LS174LS logic family.
The CD54HC02 and CD54HCT02 are supplied in 14-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC02 and CD74HCT02 are supplied in 14-lead
dual-in-line plastic packages (E suffix) and in 14-lead dualin-line surface mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
GD74HCIHGT: -40 to +85°C
• Balanced Propagation Delay and Transition
Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity: NiL = 30%. NiH = 30%
of Vcc. @ Vee = 5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max .• V,H = 2 V Min.
CMOS Input Compatibility
I, :::; 1 pA @ VOL. VOH
nA-1»-j
nB~nY
92CS-38424RI
LOGIC DIAGRAM
TRUTH TABLE
nA
nB
nY
L
L
H
H
L
H
L
H
H
L
L
L
52 ________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC02
CD54/74HCT02
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground)
.......... .
-0.5 to + 7 V
< -0.5 V OR V, > Vee +0.5V) ..
OUTPUT DIODE CURRENT. 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V)
DRAIN CURRENT, PER OUTPUT (10) (FOR -05 V < Vo < Vee + 0.5V) ..
DC INPUT DIODE CURRENT, I,. (FOR V,
±20mA
DC
DC
1:20mA
:!:25mA
DC Vee OR GROUND CURRENT (icC) ..
POWER DISSIPATION PER PACKAGE (Po):
For TA 0 -40 to +60°C (PACKAGE TYPE E)
For TA 0 +60 to +85° C (PACKAGE TYPE E) ...
For TA 0 -55 to +100°C (PACKAGE TYPE F, H)
For TA " +100 to +125°C (PACKAGE TYPE F, H)
For TA
For TA
0
0
±50mA
.......... .
...................
. ..... Derate Linearly at 8 mwr C to
..........
Derate Linearly at 8 mwr C to
-40 to +70° C (PACKAGE TYPE M) ....................................... .
+70 to +125° C (pACKAGE TYPE M) .............................. .
500
300
500
300
mW
mW
mW
mW
. ......... 400 mW
Derate Linearly at 6 mW/o C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
-55 to +125°C
-40 to +85°C
PACKAGE TYPE F, H ..
PACKAGE TYPE E, M
STORAGE TEMPERATURE (T",)
LEAD TEMPERATURE (DURING SOLDERING):
-65 to +150°C
+265°C
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead trps only ....... .
........ +300° C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vce:'
CD54174HC Types
CD54/74HCT Types
DC Input or Output Voltage Vr, Va
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t" If
at2V
at 4.5 V
at6V
LIMITS
UNITS
MIN.
MAX.
2
4.5
a
6
5.5
Vee
-40
-55
+85
+125
°C
a
a
a
1000
500
400
ns
V
V
'Unless otherwise specified, all voltages are referenced to Ground.
________________________________________________________________ 53
Technical Data _________________________________________________________
CD54/74HC02
CD54/74HCT02
ST4TIC ELECTRICAL CHARACTERISTICS
CD74HC02/CD54HC02
CD74HCT02lCD54HCT02
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
SERIES
SERIES
SERIES
CONDITIONS
SERIES
SERIES
SERIES
+25'C
-401
+85°C
-551
-401
-551
+85'C
+125'C
CHARACTERISTIC
UNITS
V,
10
V
mA
Vee
V
+25°C
+125'C
V,
V
Vee
V
Min Typ Max Min Max Min Max
High~Level
Input Voltage
V'H
Low·Level
Input Voltage
V"
High-Level
V"
Output Voltage
VOH
CMOS Loads
or
-0.02
V,"
2
1.5
-
-
4.5
3.15
-
-
6
4.2
-
1.5
-
1.5
-
3.15
-
3.15
-
-
4.2
-
4.2
-
Min Typ Max Min Max Min Max
4.5
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
Low-Level
6
-
-
1.8
-
1.8
-
1.8
Vo,
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
CMOS Loads
or
6
5.9
-
-
5.9
-
5.9
-
V'H
3.98
-
-
3.84
-
3.7
-
or
V'H
-5.2
6
5.48
-
-
5.34
-
5.2
-
V'H
2
-
-
0.1
-
0.1
-
0.1
V"
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V'H
0.02
V"
Input Leakage
I,
4
4.5
-
-
0.26
-
0.33
-
0.4
V'H
5.2
6
-
-
0.26
-
0.33
-
0.4
V'H
Any
Voltage
Between
Vee
& Gnd
or
6
-
-
±D.1
-
±1
-
±1
6
-
-
2
-
20
-
40
Gnd
Quiescent
Vee
Device
Current
or
Icc
or
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±D.1
-
±1
-
±1
pA
5.5
-
-
2
-
20
-
40
pA
-
100 360
-
450
-
490
pA
to
Vee
0
or
Gnd
Gnd
Additional
4.5
Quiescent
Device Current
per input pin:
1 unit load
2
V"
or
Vee
Current
-
V"
4.5
V'H
TTL Loads
2
V"
-4
or
-
5.5
or
V"
Output Voltage
-
4.5
-
V"
TTL Loads
2
to
5.5
Vcc-2.1
t.lcc
to
5.5
·For dual-supply systems theoretical worst case (V,
=2.4 V, Vee =5.5 V) specification is 1.8 mAo
HCT Input Loading Table
Input
All
Unit Loads'
1.5
'Unit Load is Ll.lcc limit specified in Static Characteristic
Chart, e.g., 360/lA max. @ 25° C.
54 ______________________________________~-------------------------
_____________________________________________________________ TechnicaIOata
CD54/74HC02
CD54/74HCT02
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25° C, Inpull" I. =; 6 ns)
TYPICAL
HC
HCT
Cl
(pF)
SYMBOL
Propagation Delay, Data Input to Output Y (Fig. 1)
15
t pLH
t pHL
7
8
ns
Power Dissipation Capacitance'
-
CPD
26
26
pF
CHARACTERISTIC
UNITS
·C PO is used to determine the dynamic power consumption, per gate.
PD =Vee' f, (Cpo + Cd
f, = input frequency
C L = output load capacitance
Vee = supply voltage
SWITCHING CHARACTERISTICS (Cl = 50 pF, Inpull., I. = 6 ns)
CHARACTERISTIC
Propagation Delay,
Input to Output
(Fig. 1)
Transition Times
(Fig. 1)
Input
Capacitance
SYMBOL
Vee
t plH
2
4.5
6
2
4.5
6
t PHL
hLH
hHL
_40° C 10 +85° C
25°C
-55°C 10 +125°C
54HC
74HCT
54HCT
UNITS
HC
HCT
74HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
115
135
90
32
18
21
23
27
ns
15
23
20
110
75
95
15
15
19
22
22
ns
19
19
16
13
-
I~
-
C,
10
10
10
10
10
10
pF
,INPUT
~
LEVEL
OUTPUT
'THL
92C5 -37991 RI
L
54174HC
I Input Level
I SwitchinQ Voltage, Vs
Vcc
50% Vcc
J
J
I
54174HCT
.1
3V
-'
1.3 V
I
Fig. 1 - Transition times and propagation delay times.
_______________________________________________________________________ 55
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC03
CD54/74HCT03
File Number
1832
High-Speed CMOS Logic
3
IV
18
2A
28
2V
- r - ' - -__/
Type Features:
3A
4A
4B
Quad 2-lnput NAND Gate
With Open Drain
12
13
11
•
•
•
Buffered inputs
Typical propagation delay
Output pull-up to 10 V
=8 ns @ Vee =5 V,
CL
= 15 pF,
TA
=25° C
4V
GNO -7
Vee=14
92CS-36528R2
FUNCTIONAL DIAGRAM
The RCA-CD54174HC03 and CD54/74HCT03 logic gates
utilize silicon-gate CMOS technology to achieve operating
speeds similar to LSTTL gates with the low power
consumption of standard CMOS integrated circuits. All
devices have the ability' to·drive 10 LSTTL loads. The
54HCT174HCT logic family is functionally as well as pin
compatible with the standard 54LS/74LS logic family.
These open-drain NAND gates can drive into resistive loads
to output voltages as high as 10 V. Minimum values of RL
required vs. load voltage are shown in Fig. 2.
The CD54HC03 and CD54HCT03 are supplied in 14-lead
dual-in-line frit-seal ceramic packages (F suffix). The
CD74HC03 and CD74HCT03 are supplied in 14-lead dualin-line plastic packages (E suffix) and in 14-lead dual-inline surface mount packages (M suffix). Both types are also
available in chip form (H suffix).
Family Features:
•
•
•
•
•
•
•
Fanout (over temperature range):
Standard outputs - 10 LSTTL loads
Bus driver outputs - 15 LSTTL loads
Wide operating temperature range:
CD74HCIHCT: -40 to +85°C
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL
logic ICs
Alternate source is Philips/Signetics
CD54HCICD74HC Types:
2 to 6 V Operation
High noise immunity: ML = 30%, MH = 30%
of Vee, @ Vee = 5 V
CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
·:Direct LSTTL input logic compatibility
V'L = 0.8 V max., V'H = 2 V Min.
CMOS input compatiblity
I, ::; 1 J1A @ VOL, VO H
TRUTH TABLE
nA
A
nS
92CS- 40188
LOGIC DIAGRAM
B
Y
L
L
Z#
H*
H
L
Z#
H*
L
H
Z#
H*
H
H
L
* Requires pull-up (RL to Vel
# Without pull-up (high impedance)
56 _________________________________________________________________
Technical Data
CD54/74HC03
CD54/74HCT03
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ........•..........•................................................................. -0.5 to + 7 V
DC INPUT DIODE CURRENT, 1'K (FOR V, < -0.5 V OR V, > Vee + 0.5 V) ....................................................... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -D.5 V) ........................................... '" ......................... -20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo) ............................................... , .................. -25 mA
DC Vee OR GROUND CURRENT (Icc) ................ , ....... , ............................................................. ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
ForT. = -40 to -fUO°C (PACKAGE TYPE E) ...................... : ........................................................ 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/o C to 300 mW
ForT. = -55 to +1OO°C (PACKAGE TYPE F, H) ........................................................................... 500 mW
ForT. = +100 to +125°C (PACKAGE TYPE F, H) ............................................. Derate Linearly at 8 mW/oC to 300 mW
For T. = -40 to +70°C (PACKAGE TYPE M) ............................................................................... 400 mW
For T. = +70 to +125° C (PACKAGE TYPE M) ................................................. Derale Lineary at 6 mW/o C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H ................... , ......... , ............................................................... -55 to +125° C
PACKAGE TYPE E, M ..........•.................. , ................................................................. -40 to +85° C
STORAGE TEMPERATURE (T..,) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ........................................................ +265°C
Unit inserted into a PC Board (min. thickness 1/16 in .. 1.59 mm)
with solder contacting lead tips only ................................................................................... +300° C
RECOMMENDED OPERATING CONDITIONS:
Fer maximum reliability, nominal operating conditions should be selected so that operation Is always within the
following ranges:
LIMITS
UNITS
CHARACTERISTIC
MIN,
MAX.
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vec: •
CD54174HC Types
CD54174HCT Types
2
6
V
4.5
5.5
V
DC Input Voltage V,
0
Vcc
V
DC Load Voltage VL
0
10 #
V
Operating Temperature TA:
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
ns
Input Rise and Fall Times, t" tf
at 2 V
0
1000
at 4.5 V
0
500
ns
at 6 V
0
400
ns
• Unless otherwise specified, all voltages are referenced to Ground.
# With pull-up resistor whose value limits output current to 25 mAo
'A
14 Vee
'8
13 48
'Y
12 4A
2A
"
28
10 38
2Y
9 3A
GND
B 3Y
4Y
9LCS-38303
TERMINAL ASSIGNMENT
__________________________________________________________________ 57
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC03
CD54/74HCT03
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT03/CD54HCT03
CD74HC03/CD54HC03
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85°C
+125"C
+8S o C
+125°C
UNITS
CHARACTERISTIC
+2SoC
V,
10
Vee
V
mA
V
High-Level
Input Voltage
V,"
Low-Level
Input Voltage
V"
2
1.5
-
4.5
3.15
-
6
4.2
-
2
-
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
Low-Level
Yo,
V"
or
0.02
-
-
1.8
-
1.8
Vee
V
V
-
1.5
-
1.5
3.15
-
3.15
-
4.2
-
4.2
-
-
2
-
-
0.1
-
0.1
4.5
-
0.1
-
0.1
-
0.1
V"
or
6
-
-
0.1
-
0.1
-
0.1
V,"
V,"
TTL Loads
V"
or
4
4.5
-
-
0.26
-
0.33
-
0.4
V"
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
Input Leakage
I,
Device Current
or
6
-
-
~0.1
-
±1
-
±1
or
Voltage
Between
6
-
-
2
-
20
-
40
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
pA
5.5
-
-
2
-
20
-
40
pA
-
100 360
-
450
-
490
pA
-
-
-
5
-
10
pA
to
or
Gnd
Additional
4.5
Quiescent Device
Vee -2.1
Current per input
to
5.5
alec
Vo
Output Leakage
Current
2
Vee
0
Gnd
pin: 1 unit load
-
Vee & Gnd
Vee
Icc
2
Any
Vee
Gnd
Quiescent
-
5.5
CMOS Loads
Current
-
4.5
-
1.8
0.1
2
to
5.5
0.5
1.35
Min Typ Max Min Ma. Min Ma.
4.5
-
6
Output Voltage
Min Typ Ma. Min Ma. Min Max
+25°C
V,
V"
VI = VIL
=
10V
loz
thru
6
-
-
0.5
-
5
-
10
1 KO
Vo = 10 V
thru
5.5
0.5
1 KO
*For dual-supply systems theoretical worst case (VI
=2.4 V, Vee =5.5 V) specification is 1.8 rnA.
HCT tNPUT LOADfNG TABLE
INPUT
UMIT LOADS'
• Unit load is ""tcc limit specified in Static Characteristic
Chart, e.g., 360 f.lA max. @ 25°C.
~---------------------------------------------------------
Technical Data
CD54/74HC03
CD 54/74H CT03
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Inpul I" If = 6 ns)
TYPICAL VALUES
Propagation Delay, (Fig. 1)
UNITS
CL
(pF)
HC
HCT
tpZL, tpLZ
15
8
9
ns
Cpo
-
6.4
9
pF
CHARACTERISTIC
Power Dissip Vee +0.5V) ...................................................
±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR V, < -0.5 V OR V, > Vee +0.5V) .................................................... ±20mA
DC DRAIN CURRENT, PER OUTPUT (I,) (FOR -0.5 V < V, < Vee + 0.5V) .....................
.. . ... . . . ..
±25mA
DC Vee OR GROUND CURRENT (Icc) .................................
±50mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60' C (PACKAGE TYPE E) .............................
. ........................................... 500 mW
For TA = +60 to +85'C (PACKAGE TYPE E) ................................................. Derate Linearly at 8 mW/'C to 300 mW
For TA = -55 to +100'C (PACKAGE TYPE F, H) ........................................................................... 500 mW
For TA +100 to +125°C (PACKAGE TYPE F, H) ............................................ Derate Linearly at 8 mW/'C to 300 mW
For T. = -40 to +70°C (PACKAGE TYPE M) ............................................................................ 400 mW
For T. = +70 to +125°C (PACKAGE TYPE M) ............................................... Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .............................................................................................-55 to +125'C
PACKAGE TYPE E, M ............................................................................................. -40 to +85°C
STORAGE TEMPERA TURE (T",) ................................................................................... -65 to +150° C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max. .................................................
+265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ..................................................................................... +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within the
following ranges:
LIMITS
UNITS
CHARACTERISTIC
MIN,
MAX,
CD54/74HC Types
2
6
CD54!74HCT Types
4.5
5.5
V
0
Vcc
V
Supply Voltage Range (For TA = Fuli Package Range) Vcc:"
DC Input or Output Voltage VIN, Your
V
Operating Temperature TA:
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
input Rise and Fall Times, tr, If
at 2 V
0
1000
ns
at 4.5 V
0
500
ns
at 6 V
0
400
ns
'Unless otherwise specified, all voltages are referenced to Ground,
____________________________________________________ 61
Technical Data ___________________________________________________________
CD54/74HC04
CD 54/74HCT04
STATIC ELECTRICAL CHARACTERISTICS
CD74HC04/CD54HC04
TEST
CONDITIONS
74HC/54HC
TYPES
CD74HCT04/CD54HCT04
74HC
TYPES
54HC
TYPES
-401
-551
+85°C
+125°C
TEST
CONDITIONS
74HCT/54HCT
TYPES
74HCT
TYPES
54HCT
TYPES
-401
-551
+85°C
+125°C
CHARACTERISTIC
UNITS
V,
V
+25°C
10
mA
Vee
V
+25°C
V,
V
Vee
V
Min Typ Ma. Min Ma. Min Ma.
High-Level
Input Voltage
1.5
-
-
1.5
-
1.5
-
4.5 3.15
-
-
3.15
-
3.15
-
-
-
4.2
-
4.2
-
2
V"
6
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
VO"
CMOS Loads
or
-0.02
V,"
4.2
Min Typ Ma. Min Ma. Min Ma.
4.5
Low-Level
Output Voltage
-4
V,"
-5.2
CMOS Loads
or
0.02
V,"
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
Input leakage
Current
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
V"
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5 3.98
-
-
3.84
-
3.7
-
or
-
-
5.34
-
5.2
-
V,"
2
-
-
0.1
-
0.1
-
0.1
V"
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
Current
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
to
V"
4
4.5
-
-
0.26
-
0.33
-
0.4
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
6
-
-
to.l
-
±1
-
±1
Any
Voltage
Between
Vee
&Gnd
5.5
-
-
±O.1
-
±1
-
±1
pA
6
-
-
2
-
20
-
40
Vee
or
Gnd
5.5
-
-
2
-
20
-
40
pA
-
100 360
-
450
-
490
pA
or
or
Icc
-
or
Vee
Device
2
5.5
5.48
Gnd
Quiescent
-
4.5
6
Vee
I,
2
-
V"
TTL Loads
-
V"
or
V"
Vo,
-
to
5.5
V"
TTL Loads
2
-
0
Gnd
4.5
Additional
Quiescent
Device Cu rrent
per input pin:
6 Icc
1 unit load
Vcc-2.1
to
5.5
'Fa, dual-supply systemstheo,etlcal wo,st case (V, = 2.4 V, Vee = 5.5 V) spaclflcatlon 1.1.8 mAo
HCT Input Loading Table
Input
Unit Loads'
ALL
1.2
·Unit Load is Alec limit specified in Static Characteristic Chart,
e.g .. 360 pA max. @ 25° C.
62 ________________________________________________________
~----------
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC04
CD 54/74H CT04
SWITCHING CHARACTERISTICS (Vee = 5 V, T. = 25°C, Inpul In If = 6 ns)
Typical
CHARACTERISTIC
HC
HCT
7
Propagation Delay, Data Input to Output Y (Fig. 1)
(C L = 15 pF)
t pLH
t pHL
6
Power Dissipation Capacitance"
Cpo
21
Unils
ns
pF
.. 24
·CPDI is used to determine the dynamic power consumption, per inverter where:
Po = Vee 2f (Cpo + Cl) where f = input frequency
Cl = oUlpul load capacitance
Vee = supply voltage
SWITCHING CHARACTERISTICS (C L = 50 pF, Inpul I" If = 6 ns)
LIMITS
TEST
CHARACTERISTIC
HC
·55°C to +125°C
·40° C to +85° C
25°C
CONDITION
HCT
74HCT
74HC
54HCT
54HC
UNITS
Vee
V
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay
t PLH
2
-
85
-
-
Input to Output
t PHL
4.5
-
17
-
19
14
(Fig. 1)
Input Capacitance
-
130
-
-
-
26
29
-
-
22
-
105
21
6
-
-
hLH
2
-
75
-
-
-
95
-
-
-
110
-
-
hHL
4.5
-
15
-
15
-
19
-
19
-
22
-
22
6
-
13
-
-
-
16
-
-
19
-
-
-
10
-
10
-
10
-
10
-
10
-
10
C,
ns
-
-
(Fig. 1)
Transition Ti mes
-
24
18
-
-
ns
pF
.-
INPUT
LEVEL
90%
90%
vs
OUT PUT
10"10
10%
9ZCS- 36948RI
Fig. 1 . Transition times and propagation delay times.
__________________________________________________________ 63
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD 54/74HC08
File Number 1549
CD54/74HCT08
High-Speed CMOS Logic
IA
IB
IV
2A
2B
2Y
GNO
14 Vee
\3
12
"
10
Quad 2-lnput AND Gate
4B
Type Features:
4A
• Buffered inputs
• Typical CD54/74HCOB propagation de/ay=7 ns
@ Vcc=5 V, CL=15pF, TA=25°C
4Y
3B
3A
3Y
92CS-37971
FUNCTIONAL DIAGRAM AND
TERMINAL ASSIGNMENT
T~~ RC:~-CD54174HC08
and CD54174HCT08 logic gates
utilize Slll.co.n-gate CMOS technology to achieve operating
speeds similar. to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices
have the ability to drive 10 LSTTL loads. The 54HCT174HCT
logic family is functionally as well as pin compatible with
.the standard 54LS174LS logic family.
The CD54HC08 and CD54HCTOB are supplied in 14-lead
hermetic dual-in-lineceramic packages (F suffix). The
CD74HC08 and CD74HCT08 are supplied in 14-lead dualin-line plastic packages (E suffix) and in 14~lead dual-inline. surface mount plastic package (M suffix). Both types
are also available in chip form (H suffix).
LOGIC DIAGRAMS
nA~
nB~
nY
'Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +B5°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to
LSTTL Logic ICs
• Alternate Source is Philips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity:
NoL=30%, N'H=30% of Vee @ Vcc=5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'L=O.B V Max., V'H=2 V Min.
CMOS Input Compatibility
10 :5 1 pA @ VOL. VO H
92CS-37972RI
TRUTH TABLE
CD54/74HC08
INPUTS
OUTPUTS
nA
nB
nY
L
L
L
nY
CD54/74HCTOt
L
H
L
H
L
L
H
H
H
64 ________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC08
CD54/74HCT08
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ...................................... .
. ....... -0.5 to +7 V
DC INPUT DIODE CURRENT, I,K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ... .
. .... ±20 mA
...... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V)
DC DRAIN CURRENT. PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5 V) ....
. .... ±25 mA
DC Vee OR GROUND CURRENT (lee): ............. .
. .. ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60° C (PACKAGE TYPE E) ....... .
. .. 500 mW
For TA = +60 to +85° C (PACKAGE TYPE E) ....................... .
. ... Derate Linearly at 8 mW/o C to 300 mW
For TA = -55 to +100°C (PACKAGE TYPE F, H) ...................... .
. .................... 500 mW
For T. = +100 to +125° C (PACKAGE TYPE F, H) . . . . . . . . . . . . . . . . . . .
. Derate Linearly at 8 mW/o C to 300 mW
For T. = -40 to +70°C (PACKAGE TYPE M) ., .......................... , .................................. , ............. 400 mW
For T. = +70 to +125°C (PACKAGE TYPE M) ........ " .... ,., ........ ," ....... " •.... , .... , Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F. H .......................................... .
PACKAGE TYPE E, M ......................................... .
STORAGE TEMPERATURE (T",) ................................. .
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................. .
.. ......... -55 to +125°C
. ........... -40 to +85° C
. .. -65 to +150°C
+265° C
+300° C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation Is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA-Full Package-Temperature Range) Vcc:'
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage V" Va
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t"t,
at 2 V
at 4.5 V
at 6 V
LIMITS
UNITS
MIN,
MAX.
2
4.5
a
6
5.5
Vcc
-40
-55
+85
+125
°C
a
a
a
1000
500
400
ns
V
V
. 'Unless otherwise specified, all voltages are referenced to Ground.
- - - - - - - - - - - - -________________________________ 65
TechnicaIOala,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC08
CD54/74HCT08
STATIC ELECTRICAL CHARACTERISTICS
CD74HC08/CD54HC08
TEST
CONDITIONS
74HC/54HC
TYPES
CD74HCT08/CD54HCTOIt
74HC
TYPES
54HC
TYPES
-401
-551
+85°C
+125°C
TEST
CONDITIONS
74HCT/54HCT
TYPES
74HCT
TYPES
TYPES
54HCT
-401
-551
+85°C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
V
10
mA
Vee
Y
+25°C
V,
V
Vee'
V
Min Typ Max Min Max Min Max
High-Level
Inpul Voltage
V,"
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
VOH
CMOS Loads
or
-0.02
V,"
2
1.5
-
-
1.5
-
1.5
-
4.5
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
Min Typ Max Min Max Min Max
4.5
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
or
V,"
Low-Level
Output Voltage
CMOS Loads
or
-5.2
0.02
V,"
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
or
V,"
Input Leakage
Current
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5
3.98
-
-
3.84
-
3.7
-
or
6
5.48
-
-
5.34
-
5.2
-
V'H
2
-
-
0.1
-
0.1
-
0.1
V"
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
4.5
-
-
0.26
-
0.33
-
0.4
6
-
-
5.2
0.26
-
0.33
-
0.4
V,"
Any
Voltage
Between
Vee
& Gnd
or
6
-
-
to.l
-
±1
-
±1
6
-
-
2
-
20
-
40
Gnd
Quiescent
Vee
Device
or
Current
Gnd
Icc
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±O.1
-
±1
-
!1
pA
5.5
-
-
2
-
20
-
40
pA
-
100 . 360
-
450
-
490
pA
to
5.5
V"
4
Vee
I,
2
V"
V"
TTL Loads
-
V"
-4
V"
Yo,
-
4.5
-
V"
TTL Loads
2
to
5.5
or
Vcc
0
or
&Gnd
Additional
Quiescent
Device Current
per input pin:
1 unit load
Alcc •
4.5
Vcc-2.1
to
5.5
"For dual-supply systems theoretical worst case (V,
=2.4 V, Vo< =5.5 V) specification is 1.8 mAo
HCT Input Loading Table
Input
All
Unit Loads·
0.6
·Unit Load is Alec limit specified in Static Characteristic Chart,
e.g., 360 pA max. @ 25° C.
66 _______________________________________________________________
- - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC08
CD54/74HCT08
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Inpul I. I, = 6 ns)
CHARACTERISTIC
SYMBOL
TYPICAL
HC
HCT
UNITS
Propagation Delay, Data Input to Output Y (Fig. 1)
(CL=15 pF)
tPLH
tPHL
7
10
ns
Power Dissipation Capacitance'
Cpo
37
51
pF
'CPO is used to determine the dynamic power consumption, per gate.
po= Vee' fi '(Cpo
+ Cd
where f,=input frequency
C, =output load capacitance
Vce=supply voltage
SWITCHING CHARACTERISTICS (CL = 50 pF, Inpul t., t, = 6 ns)
CHARACTERISTIC
Propagation Delay,
Input to Output
(Fig. 1)
Transition Times
(Fig.1)
Input
Capacitance
SYMBOL
tPLH
tPHL
ITLH
ITHL
VCC
2
4.5
6
2
4.5
6
-40°Clo+85°C
-55°C 10 +125°C
25°C
HCT
74HC
74HCT
54HC
54HCT
UNITS
HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
115
135
90
38
18
25
23
27
ns
31
23
20
25
110
75
95
15
15
19
19
22
22
ns
19
16
13
-
-
-
-
C,
10
10
10
10
10
10
pF
92CS-379T4RI
Input Level
Switching Voltage, Vs
I
I
I
54/74HC
Vcc
50% Vcc
I
I
I
54174HCT
3V
1.3V
I
I
I
Fig. 1 - Transition times and propagation delay times.
___________________________________________ 67
TechnicaIOala _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC10
CD 54/74H CT10
File Number 1551
High-Speed CMOS Logic
14
IA
Vce
13
18
IC
12
2A
28
10
2e
IV
Type Features:
3C
• Buffered inputs
• Typical propagation delay =8 ns
@ Vee = 5 V, C L = 15 pF, TA = 25° C
38
9
2V
Triple 3-lnput NAND Gate
3A
3V
GND
92CS- 37989
FUNCTIONAL DIAGRAM AND
TERMINAL ASSIGNMENT
T~~ RC.'~-CD54/74HC10
and CD54174HCT10 logic gates
utilize silicon-gate CMOS technology to achieve operating
speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices
have the ability to drive 10 LSTTL loads. The 54HCT /7 4HCT
logic family is functionally as well as pin compatible with
the standard 54LS174LS logic family.
The CD54HC10 and CD54HCT10 are supplied in 14-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC10 and CD74HCT10 are supplied in 14-lead dualin-line plastic packages (E suffix) and in 14-lead dual-inline surface mount plastic packages (M suffix). Both types
are also available in chip form (H suffix).
nA
n8
nV
ne
LOGIC DIAGRAM
68 ______
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85°C
• Balanced Propagation and Transition Times
• Significant Power Reduction Compared to
LSTTL Logic ICs
• Alternate Source is Philips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity:
NtL=30%, NtH=30% of Vee: @ Vee=5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
VIL=0.8 V Max., VIH=2 V Min.
CMOS Input Compatibility
II ~ 1 /lA @ VOL, VOH
TRUTH TABLE
~
INPUTS
OUTPUTS
nA
nB
nC
nY
L
L
L
H
L
L
H
H
L
H
L
H
L
H
H
H
H
L
L
H
H
L
H
H
H
H
L
H
H
H
H
L
_____________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC10
CD54/74HCT10
MAXIMUM RATINGS. Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ...................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, hK (FOR V; < -0.5 V OR V, > Vee +0.5 V) ....................................................... ±20 rnA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) ................................................... ±20 rnA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5 V) .................................................... ±25 rnA
DC Vee OR GROUND CURRENT (Icc): ..................................................................................... ±50 rnA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60° C (PACKAGE TYPE E) ............................................................................... 500 mW
For T. = +60 to +85 0 C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/o C to 300 mW
For TA = -55 to +100° C (PACKAGE TYPE F, H) ............................................................................ 500 mW
For TA = +100 to +125°C (PACKAGE TYPE F, H) .............................................. Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +70° C (PACKAGE TYPE M) ..... , .....................................................................•. 400 mW
For T. = +70 to +125°C (PACKAGE TYPE M) ................................................ Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H ............................................................................................. -55 to +125°C
PACKAGE TYPE E, M ............................................................................................. -40 to +85° C
STORAGE TEMPERATURE (T..,) .............................................................................. · ... ·· -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
. .................................................... +265° C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ..................................................................................... +300° C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability. nominal operating conditions should be selected so Ihat operation is always wilhin
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA-Fuli Package-Temperature Range) Vcc:'
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage V" Vo
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t"t,
at 2 V
at 4.5 V
at 6 V
LIMITS
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vec
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
V
V
'Unless otherwise specified, all voltages are referenced to Ground.
_______________________________________________________________ 69
Technical Data
CD54/74HC10
CD54/74HCT10
STATIC ELECTRICAL CHARACTERISTICS
CD74HC10/CD54HC10
CD74HcnO/CD54Hcno
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85'C
+125'C
+85°C
+125'C
CHARACTERISTIC
UNITS
V,
V
+25'C
10
mA
V,,
V
+25'C
V,
V
V"
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
4.5
V,"
1.5
15
3.15
3.15
3.15
10
4.2
4.2
4.2
5.5
Low-Level
Input Voltage
High-Level
Output Voltage
4.5
V"
V"
YO"
CMOS Loads
or
-0.02
4.5
V"'
Min Typ Max Min Max Min Max
1.5
4.5
0.5
0.5
0.5
1.35
1.35
1.35
to
1.8
1.8
1.8
5.5
1.9
1.9
1.9
4.4
4.4
4.4
5.9
5.9
5.9
3.98
3.84
3.7
5.48
5.34
52
4.5
Low-Level
Output Voltage
-4
V,"
-5.2
CMOS Loads
or
4.5
0.02
4.5
V,"
V,"
or
4.5
44
4.5
3.98
4.4
44
V
-
-
3.84
-
3.7
V
V,"
0.1
0.1
0.1
0.1
0.1
0.1
or
0.1
01
0.1
V,"
026
0.33
0.4
5.2
0.26
0.33
0.4
V,"
±1
Any
Voltage
Between
Veo
Current
V
V"
4.5
0.1
01
V
0.4
V
,1
,1
pA
20
40
pA
490
/lA
01
V"
4.5
or
Input Leakage
0.8
V,"
V"
TTL Loads
0.8
V"
or
V"
Yo,
0.8
V"
V"
TTL Loads
V
-
or
±O.1
±1
or
45
-
026
55
-
:to
-
1
0.33
-
Veo
Gnd
Quiescent
Veo
Device
or
Current
Gnd
lec
& Gnd
Vee
2
20
40
or
55
Gnd
AdditIOnal
Quiescent
Device Current
per input pin:
1 unit load
I:J.lcc
45
to
Vcc-2 .1
100
360
-
450
-
5.5
*For dual-supply systems theoretical worst case (VI
=2.4 V,
Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
All
Unit Loads'
0.6
*Unit Load is .6. Icc limit specified in Static Characteristic Chart,
e.g .. 360 IlA max. @ 25 0 C.
70 ______________________________________________________________
___________________________________________________________ TechnicaIData
CD54/74HC10
CD54/74HCT10
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Inpul I., If = 6 ns)
CHARACTERISTIC
SYMBOL
Propagation Delay, Data Input to Output Y (Fig. 1)
(CL=15 pF)
tPHL
Power Dissipation Capacitance'
Cpo
tPLH
TYPICAL
HC
HCT
UNITS
8
9
ns
24
28
pF
'CPO is used to determine the dynamic power consumption, per gate.
PO= Vee' fi
(Cpo
+ Cd
where f,=input frequency
CL =outputload capacitance
Vce=supply voltage
SWITCHING CHARACTERISTICS (CL
CHARACTERISTIC
Propagation Delay,
Input to Output
(Fig. 1)
Transition Times
(Fig. 1)
Input
Capacitance
SYMBOL
tPLH
tPHL
hLH
hHL
= 50 pF,
VCC
2
4.5
6
2
4.5
6
C,
Inpul I., If
= 6 ns)
_40° C 10 +85° C
-55° C 10 +125° C
25°C
UNITS
74HCT
54HCT
54HC
HCT
74HC
HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
100
125
150
20
25
36
ns
24
30
30
26
21
17
110
95
75
22
19
19
22
ns
15
15
19
16
13
10
10
10
10
10
10
pF
"NPUT
....l.-
LEVEL
OUTPUT
92CS-37991RI
Input Level
Switching Voltage, Vs
54174HC
Vee
50% Vee
Fig. 1 - Transition times and propagation delay tinws.
____________________________________________________________________ 71
Technical Data
CD54/74HC11
CD54/74HCT11
File Number
1475
High-Speed CMOS Logic
Triple 3-lnput AND Gate
Type Features:
• Buffered inputs
• Typical propagation delay = 8 ns @ Vee = 5 V, CL = 15 pF,
TA=25°C
L-_ _ _--' 92CS-36871RI
FUNCTIONAL DIAGRAM AND
TERMINAL ASSIGNMENT
The RCA-CD54/74HC11 and CD54174HCT11 logic gates
utilize silicon-gate CMOS technology to achieve operating
speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices
have the ability to drive 10 LSTTL loads. The 54HCT174HCT
logic family is functionally as well as pin compatible with
the standard 54LS/74LS logic family.
The CD54HC11 and CD54HCT11 are supplied in 14-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC11 and CD74HCT11 are supplied in 14-lead dualin-line plastic packages (E suffix) and in 14-lead dual-inline surface mount plastic packages (M suffix). Both types
are also available in chip form (H suffix).
Family Features:
• Fanout [Over Temperature Range]:
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Phillips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity: N ,L =30%, MH=30% of Vee
@ Vec=5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L =0.8 V Max., V,H =2 V Min.
CMOS Input Compatibility
I, :S 1 J1A @ VOL, V OH
TRUTH TABLE
INPUTS
OUTPUTS
nA
nA
nB
nC
nY
L
L
L
L
L
L
H
L
L
H
L
L
L
H
H
L
H
L
L
L
H
L
H
L
H
H
L
L
H
H
H
H
nY
nB
nC
92CS-36971RI
LOGIC DIAGRAM
72 _________________________________________________________________
___________________________________________________________ TechnicaIData
CD54/74HC11
CD54/74HCT11
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ..................................................................................... -{l.5 to +7 V
DC INPUT DIODE CURRENT, I'K (FOR V, <-{l.5V or V, >Vee +0.5V) ..................................
. ................. ±20 mA
DC OUTPUT CURRENT, 10K (FOR Vo <-05V OR Vo > Vee +0.5V) ........................................................... ±20 mA
DC DRAIN CURRENT. PER OUTPUT (10) (FOR -{l.5V < Vo < Vee + 0.5V) ................................................... ±25 mA
DC Vee OR GROUND CURRENT, (Icc): .................................................................................... ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60°C (PACKAGE TYPE E) ............................................................................. 500 mW
For TA = +60 to+85° C (PACKAGE TYPE E) ............................................... Derate Linearly at 8 mW/o C to 300 mW
For TA = -55 to +100°C (PACKAGE TYPE F. H) .......................................................................... 500 mW
For TA = +100 to +125°C (PACKAGE TYPE F, H) ......................................... Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +70° C (PACKAGE TYPE M) .............................................................................. 400 mW
For TA = +70 to +125°C (PACKAGE TYPE M) ................................................ Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (T A ):
PACKAGE TYPE F. H .............
.. .......................................................................... '-55 to +125°C
PACKAGE TYPE E, M ................................................... ..
. ................................... -40 to +85° C
STORAGE TEMPERATURE (T".) .........................................................................
. ... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) tram case for 10 s max ....................... .
. ......... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in .. 1.59 mm)
with solder contacting lead tips only ................................................... .
. ................. +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
LIMITS
MIN.
MAX.
UNITS
Supply-Voltage Range (For TA = Full Package Temperature Range) Vee:'
2
6
V
CD54/74HCT Types
4.5
5.5
DC Input or Output Voltage Vi". Va",
0
Vee
V
V
CD54/74HC Types
Operating Temperature TA:
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
at 2 V
0
1000
ns
at 4.5 V
0
500
ns
at 6 V
0
400
ns
Input Rise and Fall Times t •. tf
'Unless otherwise specified, all voltages are referenced to Ground.
_________________________________________________________________ 73
Technical Data ___________________________________________________________
-CD54/74HC11
CD54/74HCT11
STATIC ELECTRICAL CHARACTERISTICS
CD74HC11/CD54HC11
CD74HCT11/CD54HCT11
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CDNDITIDNS
TYPES
TYPES
TYPES
CDNDITIDNS
TYPES
TYPES
TYPES
-401
-551
-401
+85°C
+125°C
-551
+12SDC
CHARACTERISTIC
UNITS
V,
V
+25°C
10
Vo<
mA
V
+25°C
V,
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
V,"
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
YO"
CMOS Loads
or
-002
V,"
2
1.5
-
-
1.5
-
1.5
-
4.5
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
Min Typ Max Min Max Min Max
4.5
-
Low-Level
Output Voltage
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.6
-
1.6
-
1.6
CMOS Load"
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
Current
-
-
3.64
-
3.7
-
or
V,"
-5.2
6
546
-
-
5.34
-
5.2
-
V,"
V"
0.02
2
-
-
0.1
-
0.1
-
0.1
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
-
0.6
-
2
-
V
0.6
-
0.6
V
-
to
-
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.96
-
-
3.64
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±O.1
-
±1
-
±1
~A
5.5
-
-
2
-
20
-
40
~A
-
100
360
-
450
-
490
~A
V"
or
4
4.5
-
-
0.26
-
0.33
-
0.4
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
±1
Any
Voltage
Between
V"
I,
2
V"
3.96
V"
Input Leakage
-
V"
4.5
V,"
TTL Loads
-
5.5
-4
or
2
4.5
-
or
V"
Vo:.-
to
5.5
V"
TTL Loads
+85 D C
Vee
V
or
6
-
-
±O.1
-
±1
-
or
Vee
& Gnd
Gnd
Quiescent
Vee
Device
or
Current
Icc
Vee
a
6
-
-
2
-
20
-
40
or
&Gnd
Gnd
4.5
Additional
Quiescent
Device Current
per input pin:
1 unit load
I:J. Icc
Vcc 2.1
to
5.5
·For dual-supply systems theoretical worst case (V, = 2.4 V. Vee = 5.5 V) specification is1.8 rnA.
HCTlnput Loading Table
Input
Unit Loads'
ALL
0.50
'"Unit Load is .6.lcc limit specified in Static Characteristic Chart,
74 __________________________________________________________
__
e.g., 360 J.lA max. @ 25°C.
___________________________________________________________ TechnicaIData
CD54/74HC11
CD54/74HCT11
SWITCHING CHARACTERISTICS (CL =50 pF, Input t" t,
CHARACTERISTIC
SYMBOL
Propagation Delay,
Input to Output
(Fig. 1)
t pLH
Transition Times
(Fig. 1)
-
2
4.5
6
2
4.5
6
tTLH
tTHL
Input Capacitance
_40° C to +85° C
-55°C to +125°C
25°C
74HCT
54HC
54HCT
UNITS
74HC
HC
HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Vee
tpHL
=6 ns)
-
100
20
-
17
28
-
-
-
-
15
-
75
15
13
-
-
-
-
10
-
10
-
-
C,
-
125
25
21
95
19
16
-
35
-
-
-
-
19
10
-
10
-
-
-
-
150
30
26
110
22
19
-
10
-
-
-
42
-
-
-
-
22
-
10
ns
ns
pF
-
-
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Input t" t, = 6 ns)
CHARACTERISTIC
SYMBOL
Propagation Delay, Data Input to Output Y (Fig. 1)
(C L = 15 pF)
Power Dissipation Capacitance'
tpLH
t pHL
Cpo
HC
Typical
HCT
Units
8
11
ns
26
28
pF
'CPO is used to determine the dynamic power consumption. per gate.
PO Vee2 f; (Cpo +Cc) where f, input frequency
=
=
CL
= output load capacitance
V" = supply voltage
,-'NPUT
L
90%
---j ---- ~~%
I;----r-~P:-
'PLH
"""' -=J'1-=--=--=-11- =-I
tTLH
--
LEVEL
LGND
90%
::..
-tTHL
92CS-3f972R5
Fig. 1 -
Transition times and propagation delay times.
54n4HC
INPUT LEVEL
Vee
Vs
50% Vee
I
I
I
54n4HCT
3V
1.3V
I
I
I
_________________________________________________________________ 75
Technical Data
CD54/74HC14
CD54/74HCT14
File Number 1781
High-Speed CMOS logic
Hex Inverting Schmitt Trigger
Type Features:
• Unlimited input rise and fall times
• Exceptionally high noise immunity
FUNCTIONAL DIAGRAM AND
TERMINAL ASSIGNMENT
The RCA-CD54/74HC14 and CD54174HCT14 each contain
6 inverting Schmitt Triggers in one package.
The CD54HC14 and CD54HCT14 are supplied in 14-lead
ceramic dual-in-line packages (F suffix). The CD74HC14
and CD74HCT14 are supplied in 14-lead dual-in-line plastic packages (E suffix) and in 14-lead dual-in-line surface
mount plastic packages (M suffix). Both devices are also
available in chip form (H suffix).
nA
nY
LOGIC DIAGRAM
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 37%, N'H = 51% of Vee: @ Vee = 5V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
N,L = 18%, N,H = 67% of Vee @ Vee = 4.5V
CMOS Input Compatibility
I, ::S I/1A @ VOL, V OH
L-_+_+__ VI
TRUTH TABLE
Vee
VI
GND
INPUT
I
I
I
I
vee
Vo
GND
'I
OUTPUT
A
Y
I
L
H
I
H
L
r
H = High Level
L = Low Level
L..-_ _ _ _ _....
92C5-39828
Fig. 1 - Hysteresis definition, characteristic, and test setup.
76 __________________________________________________________
- - - - - - - - - - - - - - - - - - - - - - - - - - -_ _ Technical Data
CD54/74HC14
CD54/74HCT14
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ........ , , , , ... , . , , .... , , , , , .... ,
DC INPUT DIODE CURRENT, 1" (FOR V, < -0.5 V OR V, > Vee +O.5V)
-0.5 to + 7 V
±20mA
±20mA
DC OUTPUT DIODE CURRENT, 10 , (FOR Vo < -0.5 V OR Vo > Vee +O.5V) ..
DC DRA'IN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V)
±25mA
±50mA
DC Vee OR GROUND CURRENT (lee) ...... .
POWER DISSIPATION PER PACKAGE (Po):
For TA 0 -40 to +60°C (PACKAGE TYPE E) ....
. ......
Derate Linearly at 8 mwrc to
. ...
Derate Linearly at 8 mW/oC to
For TAo +60 to +85° C (PACKAGE TYPE E) .. ,'
For TA 0 -55 to +100°C (PACKAGE TYPE F, H) , ....... , .... .
For TA
For TA
For TA
0
+100 to +125°C (PACKAGE TYPE F, H) ..
-40 to +70°C (PACKAGE TYPE M) .,
0
+70 to +125°C (PACKAGE TYPE M) ....
0
.. . ..
500
300
500
300
mW
mW
mW
mW
............ 400 mW
Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H , ..
PACKAGE TYPE E, M '"
-55 to +125°C
-40 to +85°C
-65 to +150°C
STORAGE TEMPERATURE (T",)
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
+265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ".
+300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA ~ Full Package-Temperature Range) Vee:'
CD54174HC Types
CD54/74HCT Types
DC Input or Output Voltage V" Va
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t" t,
at2V
at4.5 V
at6 V
LIMITS
UNITS
MIN,
MAX,
2
4.5
0
6
5.5
Vcc
V
V
V
-40
-55
+85
+125
°C
°C
0
0
0
Unlimited
Unlimited
Unlimited
ns
ns
ns
'Unless otherwise specified, all voltages are referenced to Ground.
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 77
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC14
CD54/74HCT14
STATIC ELECTRICAL CHARACTERISTICS
CD74HC14/CD54HC14
CD74HCT14/CD54HCT14
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPE
TYPE
CONDITIONS
TYPES
TYPE
TYPE
-40/
-55/
-40/
-55/
+85°C
+125°C
+B5°C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
V
10
rnA
Input Switch
POints
V,<
V,-
V"
Min
Max
Min
Max
Min
2
0.7
1.5
0.7
1.5
0.7
1.5
~
-
-
-
-
-
4.5
1.7
3.15
1.7
3.15
1.7
3.15
4.5
1.2
1.9
1.2
1.9
1.2
1.9
6
2.1
4.2
2.1
4.2
2.1
4.2
5.5
1.4
2.1
1.4
2.1
1.4
2.1
2
0.3
1
0.3
1
0.3
1
-
-
-
-
4.5
0.9
2.2
0.9
2.2
0.9
2.2
4.5
0.5
1.2
0.5
1.2
0.5
1.2
6
1.2
3
1.2
3
1.2
3
5.5
0.6
1.4
0.6
1.4
0.6
1.4
2
0.2
1
0.2
1
0.2
1
-
-
-
-
-
4.5
0.4
1.4
0.4
1.4
0.4
1.4
4.5
0.4
1.4
0.4
1.4
0.4
1.4
6
0.6
1.6
0.6
1.6
0.6
1.6
5.5
0.4
1.5
0.4
1:5
0.4
1.5
-
-
-
-
-
4.5
4.4
-
4.4
-
4.4
-
Max
1.9
-
V,-
-
4.4
-
or
V,<
6
5.9
-
5.9
-
5.9
-
V,<
-
-
-
-
-
-
V,-
-
-
-
-
-
-
-
V,-
-
-
-
-
-
-
-
3.84
-
3.7
-
-
-
-
-
-
-
-
or
-4
4.5
3.98
-
3.84
-
3.7
-
or
V,+
-5.2
6
5.48
-
5.34
-
5.2
-
V,+
2
-
0.1
-
0.1
-
0.1
V,-
0.02
4.5
-
0.1
-
0.1
-
0.1
or
6
-
0.1
-
0.1
-
0.1
-
-
-
-
-
-
4.5
-
-
0.1
-
0.1
V,+
-
-
-
-
-
V,-
-
-
-
-
-
-
0.26
-
0.33
-
-
-
5.5
-
±O.1
5.5
--
2
4
4.5
-
0.26
-
0.33
-
0.4
or
V,+
5.2
6
-
0.26
-
0.33
-
0.4
V,+
6
-
:to. 1
-
±1
-
±1
Any
Voltage
Between
or
Gnd
-
-
-
4.5
or
V"
3.98
4.5
-
V
-
-
V,-
I,
Min
1.9
-0.02
V,+
I nput Leakage
-
Max
4.4
or
Current
Min
-
V,-
TTL Loads
Max
-
Voltage
CMOS Loads
Max
1.9
Low-Level Output
V()L
--
Min
4.4
or
TTL Loads
V"
V
2
V,-
CMOS Loads
+25°C
V,
V
4.5
High-Level Output
Voltage
YO"
V,C
V
V
V
-
V
V
0.1
V
-
-
0.4
-
-
-
-
±1
-
±1
flA
-
20
-
40
flA
-
450
-
490
flA
V
Vee and
Gnd
Quiescent
V"
Device
or
Current
Gnd
I"
Vee
0
6
-
2
-
20
-
40
or
Gnd
Additional
Quiescent
Vcc2 .1
Device Current
per input pin:
1 unit load
Alec
For dual-supply systems theoretical worst case (VI - 2.4 V, Vee - 5.5 V) specification IS 1.8 rnA.
4.5
10
Min Typ Max
-
100
360
5.5
HCT INPUT LOADING TABLE
INPUT
UNIT LOADS'
nA
0.6
'Unit load is t.lcc limit specified in Static Characteristic
Chart, e.g., 360 j1A max. @ 25° C.
78 ________
~
________________________
~
_____________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC14
CD54/74HCT14
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Inpul I" I, = 6 ns)
CL
(pF)
CHARACTERISTIC
Propagation Delay,
AtoY
Power Dissipation Capacitance'
TYPICAL
HC
HCT
15
11
-
20
tpHl,tpLH
Cpo
I
I
UNITS
16
ns
20
pF
'Cpo is used to determine the dynamic power consumption, per inverter.
Po =Vee2 f, (Cpo + Cel where: f, =input frequency
C L = output load capacitance
Vee = supply voltage
SWITCHING CHARACTERISTICS (C L =50 pF, Inpul I" I, =6 ns)
CHARACTERISTIC
Propagation Delay,
AtoY
Output
Transition Time
Input
Capacitance
Vee
t pLH
t PHL
hLH
IrHL
C,
_40° C 10 +85° C
-55°C 10 +125°C
25°C
74HCT
54HC
54HCT
UNITS
HC
HCT
74HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
-
135
27
23
75
15
13
-
10
2
4.5
6
2
4.5
6
-
-
-
-
-
-
38
-
-
170
34
29
95
19
16
-
48
-
15
-
-
10
-
10
-
-
-
19
-
-
-
205
41
35
110
22
19
10
-
10
-
-
-
-
57
22
-
-
-
10
-
-
ns
ns
pF
INPUT
LEVEL
90%
OUTPUT
Vs
'THL
'TLH
92CS-36948RI
Fig. 2 - Transition times and propagation delay times.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 79
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC20
CD54/74HCT20
File Number 1601
High-Speed CMOS Logic
14
IA
vCC
13
18
NC
IC
ID
IY
12
11
4
5
2D
NC
10 28
6
9
GND
Dual 4-lnput NAN D Gate
2C
2A
Type Features:
• Buffered inputs (HCT types)
• Typical propogation delay = 8 ns
@ Vee=5V, C l = 15 pF, TA=25°C (HC types)
2Y
92C5-38338
FUNCTIONAL DIAGRAM AND
TERMINAL ASSIGNMENT
The RCA-CD54174HC20 and CD54/74HCT20 logic gates
utilize silicon-gate CMOS technology to achieve operating
speeds similar to LSTTL gates with the low power consumptionuf standard CMOS integrated circuits. All devices
have the ability to drive 10 LSTTL loads. The 54HCT/74HCT
logic family is functionally as well as pin compatible with
the standard 54LS!74LS logic family.
The CD54HC20 and CD54HCT20 are supplied in 14-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC20 and CD74HCT20 are supplied in 14-lead dualin-line plastic packages (E suffix) and in 14-lead dual-inline surface mount plastic packages (M suffix). Both types
are also available in chip form (H suffix).
nA
n8
nY
Family Features
• Fanout (over temperature range):
.Standard outputs - 10 LSTTL loads
Bus driver outputs - 15 LSTTL loads
• Wide operating temperature range:
CD74HCIHCT: -40 to +85° C
• Balanced Propagation Delay and Transition
Times
• Significant power reduction compared to
LSTTL logic ICs
•. Alternate source is PhilipslSignetics
• CD54HC/CD74HC types:
2 to 6 V operation
High noise immunity:
Ml = 30%, N,H = 30% of Vee; @ Vee = 5V
• CD54HCTICD74HCT types:
4.5 to 5.5 V operation
Direct LSTTL input logic compatibility
V,l = 0.8 V max., V,H = 2 V min.
CMOS input compatibility
I, :S 1 JiA @ VOL, VOH
TRUTH TABLE
HC LOGIC DIAGRAM (1 GATE)
INPUTS
nA
OUTPUTS
nA
nB
nC
nO
nY
n8 -'-~>>---7
L
X
X
X
H
nC
X
L
X
X
H
X
X
L
X
H
X
X
X
L
H
H
H
H
H
L
nD
HCT LOGIC DIAGRAM (1 GATE)
X = Don't Care
L = Low Voltage Level
H = High Voltage Level
80 ______________________~------------------------------------------
- - - - - - - - -______________________ Technical Data
CD54/74HC20
CD54/74HCT20
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) .......... ,"'"
... , , , . -0.5 to +7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5 V)
... ± 20 mA
DC OUTPUT CURRENT, 10K (FOR Va < -0.5 V OR Va> Vee +O.S V) .,
± 20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -O.S V < Va < Vee +0.5 V) ..... .
± 25 mA
DC Vee OR GROUND CURRENT (Ice), ...
±SO mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60°C (PACKAGE TYPE E) ..
. .. ,.500 mW
For TA = +60 to +85°C (PACKAGE TYPE E)..
. ...... , .. ,
.. Derate Linearly at 8 mW/oC to 300 mW
For TA = -S5 to +100°C (PACKAGE TYPE F, H) .......... .
, .......... ".
.. SOO mW
For TA = +100 to +125°C (PACKAGE TYPE F, H) .... " ............. ,
.............. Derate Linearly at 8 mW/oC to 300 mW
. . , , , ...... , , , . . . . . , , , .. , , ... , ... , , .. 400 mW
For TA -40 to +70° C (PACKAGE TYPE M) " " " " ' , ........ , ....... .
For TA +70 to +125° C (PACKAGE TYPE M) ....
Derate Linearly at 6 mW/o C to 70 mW
0
0
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H ......... , . , .. , .
PACKAGE TYPE E, M .......... .
STORAGE TEMPERATURE (T"g) ...... .
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max .....
Unit inserted into a PC Board (min. thickness 1/16 in., 1.S9 mm) with solder contacting lead tips only
. ...... -S5 to +125°C
. ..... -40 to +85°C
. -65 to +150°C
.. +265°C
. +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
UNITS
MIN.
Supply-Voltage Range (For TA
MAX.
= Full Package Temperature Range) Vee:'
CD54174HC Types
CD54/74HCT Types
DC Input or Output Voltage V" Va
2
6
4,5
5.5
0
Vee
V
V
Operating Temperature TA:
CD74 Types
-40
+85
CD54 Types
-55
+125
DC
Input Rise and Fall Times, t" tf
at 2V
0
1000
at 4,5 V
0
500
at 6V
0
400
ns
'Unless otherwise specified, all voltages are referenced to Ground.
81
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC20
CD54/74HCT20
STATIC ELECTRICAL CHARACTERISTICS
CD74HC20/CD54HC20
CD74HCT20/CD54HCT20
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-40/
-55/
-40/
-55/
+85°C
+125°C
+85°C
+125°C
CHARACTERISTIC
UNITS
V,
10
Vee
V
mA
V
+25°C
V,
Vee
V
V-
Min Typ Ma. Min Ma. Min Ma.
High-Level
Input Voltage
Low-Level
Input Voltage
1.5
-
-
1.5
-
1.5
-
4.5 3.15
-
-
3.15
-
3.15
-
-
-
4.2
-
4.2
-
2
V,"
V"
High-Level
V"
Output Voltage
or
Vo"
CMOS Loads
-0.02
V,"
6
4.2
TTL Loads
Low-Level
Output Voltage
CMOS Loads
2
-
-
0.5
-
0.5
-
0.5
-
-
1.35
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
Input Leakage
2
1.9
-
-
1.9
-
1.9
-
V"
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5 3.98
-
-
3.84
-
3.7
-
2
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.4
-
-
4.4
-
4.4
-
V
4.5 3.98
-
-
3.84
-
3.7
-
V
to
or
4.5
V"
-5.2
6
5.48
-
-
5.34
-
5.2
-
V,"
2
-
-
0.1
-
0.1
-
0.1
V"
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
pA
5.5
-
-
2
-
20
-
40
pA
4.5
to
5.5
-
-
450
-
490
pA
V"
or
4
4.5
-
-
0.26
-
0.33
-
0.4
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
6
-
-
±0.1
-
±1
-
±1
Any
Voltage
Vee
I,
-
5.5
4.5
V"
Current
-
4.5
-
V,"
or
2
to
5.5
-4
V,"
TTL Loads
4.5
or
V"
Vo,
Min Typ Ma. Min Ma. Min Ma.
-
4.5
V"
+25°C
or
Between
Vee
&
Gnd
Gnd
Quiescent
Vee
Device
or
Current
Icc
Vee
0
6
-
-
2
-
20
-
40
or
Gnd
Gnd
Additional
Quiescent
Vco -2.1
Device Current
per input pin:
1 unit load .6.lcc*
100 360
-For dual-supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
Unit Loads*
All
0.15
'Unit load is ll.lcc limit specified in Static Characteristic
Chart, e.g., 360 flA max. @ 25°C.
82 _________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC20
CD54/74HCT20
SWITCHING CHARACTERISTICS (Vee = 5 V, T. = 25°C, Inpul I" I, = 6 ns)
TYPICAL
CHARACTERISTIC
SYMBOL
HC
HCT
UNITS
Propagalion Delay, Data Input to Output Y (Fig. 1)
(Cl = 15 pF)
t PLH
tpHL
8
11
ns
Power Dissipation Capacitance'
Cpo
26
38
pF
'Cpo is used to determine the dynamic power consumption, per gate.
PO
= Vee' fi
(Cpo + Cd where f,
= input frequency
Cl = output load capacitance.
Vee = supply voltage.
SWITCHING CHARACTERISTICS (Cl = 50 pF, Inpul I" I, = 6 ns)
CHARACTERISTIC
Propagalion Delay,
Input 10 Output
(Fig. 1)
Transition Times
(Fig. 1)
Input
Capacitance
SYMBOL
Vee
t PLH
2
4.5
6
tPHL
trLH
trHL
C,
25°C
-40°C 10 +85°C
-55°C 10 +125°C
54HC
54HCT
HC
HCT
74HC
74HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
-
-
2
4.5
6
-
100
20
17
-
75
15
13
-
10
-
-
-
15
-
-
-
95
19
16
-
10
-
10
28
-
"'6~'
"'6"
_-_-_ __=_
-----
INPUT
35
-
-
19
-
150
30
26
-
-
-
42
-
-
22
-
110
22
19
-
-
-
-
-
-
10
-
10
-
10
ns
ns
pF
ilNPUT
~
LEVEL
------10%
'PlH
-----
----
----
tTHL
-
_--=----=-.--=--=--:~~%
'~Pl
OUTPUT
125
25
21
LGND
---90%
----vs
---10%
IT,lH
92CS-37991
54/74HC
Input Level
Switching Voltage, Vs
54174HCT
Vee
3V
50% Vce
1.3V
Fig. 1- Transition times and propagation delay times.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 83
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC21
CD54/74HCT21
File Number 1782
High-Speed CMOS Logic
,.
,.
'Y
IC
ID
2"
10'
2B
2C
2D
2Y
12
Dual 4-lnput AND Gate
Type Features:
• Buffered inputs
• Typical propagation delay = 9ns
@ Vee =5V, C L = 15 pF, TA = 25°C (HC types)
GNO .. 7
13
Vee
~14
L -_ _ _ _----' N C' 3.11
92CS- 39565
FUNCTIONAL DIAGRAM AND
TERMINAL ASSIGNMENT
The RCA-CD54/74HC21 and CD54174HCT21 logic gates
utilize silicon-gate CMOS technology to achieve operating
speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices
have the ability to drive 10 LSTTL loads. The 54HCT/74HCT
logic family is functionally as well as pin compatible with
the standard 54LS/74LS logic family.
The CD54HC21 and CD54HCT21 are supplied in 14-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC21 and CD74HCT21 are supplied in 14-lead dualin-line plastic packages (E suffix) and in 14-lead dual-inline surface mount plastic packages (M suffix). Both types
are also available in chip form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LS TTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
N'L = 30%, N'H =30% of Vee: @ Vee = 5V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'L = 0.8 V max., V'H = 2 V Min.
CMOS Input Compatibility
I, :S 1/lA @ VOL, VOH
nA
TRUTH TABLE
nB
nD
LOGIC DIAGRAM
OUTPUTS
INPUTS
nY
nC
nA
nB
nC
nO
nY
L
X
X
X
L
X
L
X
X
L
X
X
L
X
L
X
X
X
L
L
H
H
H
H
H
x = Don't Care
L = Low Level Voltage
H = High Level Voltage
84~-----__~~------------~----------~--------------------------
_______________________________ Technical Data
CD54/74HC21
CD54/74HCT21
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ................................. .
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5V) ..
-0.5 to + 7 V
. ..... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR VD < -0.5 V OR VD > Vee +O.5V) ..... .
DC DRAIN CURRENT, PER OUTPUT (lD) (FOR -0.5 V < VD< Vee + 0.5V)
±20mA
±25mA
DC Vee OR GROUND CURRENT (lee)
POWER DISSIPATION PER PACKAGE (Po):
For TA 0 -40 to +60 D C (PACKAGE TYPE E)
For TA 0 +60 to +85 D C (PACKAGE TYPE E)
For TA 0 -55 to +100 D C (PACKAGE TYPE F, H)
±50mA
For TA
For TA
0
0
.500 mW
Derate Linearly at 8
mwr C to 300 mW
..... 500 mW
Derate Linearly at 8 mW/DC to 300 mW
+100 to +125 D C (PACKAGE TYPE F, H)
-40 to +70 D C (PACKAGE TYPE M) ............ .
.... 400 mW
Derate Linearly at 6 mW/DC to 70 mW
ForTA 0 +70to +125 D C (PACKAGE TYPE M)
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H
-55 to +125 D C
-40 to +85 D C
PACKAGE TYPE E, M ........... .
STORAGE TEMPERATURE (Telg)
LEAD TEMPERATURE (DURING SOLDERING):
-65 to +150 D C
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ....
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vee:'
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V" Va
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t " t,
at2 V
at4.5 V
at6V
LIMITS
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
-40
-55
+85
+125
DC
0
0
0
1000
500
400
ns
V
V
'Unless otherwise specified, all voltages are referenced to Ground.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 85
Technical Data
CD54/74HC21
CD54/74HCT21
STATIC ELECTRICAL CHARACTERISTICS
CD74HC21/CD54HC21
TEST
CONDITIONS
CD74HCT21/CD54HCT21
74HC/54HC
TYPES
74HC
TYPE
54HC
TYPE
-401
-551
+85"C
+125"C
TEST
CONDITIONS
74HCT154HCT
TYPES
74HCT
TYPE
54HCT
-401
-551
+85"C
+125°C
TYPE
CHARACTERISTIC
UNITS
+25°C
V,
V
10
rnA
Vee
V
+25"C
V,
V
Vee
V
Min Typ Max Min Max Min Max
I nput Voltage
V'H
Low-Level
Input Voltage
V"
High-Level
Output Voltage
1.5
-
-
1.5
-
1.5
-
4.5
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
V"
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V'H
2
High-Level
V"
VOH
CMOS Loads
or
-0.02
V'H
4.5
-
Low-Level
Output Voltage
CMOS Loads
3.98
-
-
3.84
-
3.7
-
or
V'H
-5.2
6
5.48
-
-
5.34
-
5.2
-
V'H
2
-
-
0.1
-
0.1
-
0.1
V"
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V'H
0.02
Current
or
4
4.5
-
-
0.26
-
0.33
-
0.4
V'H
5.2
6
-
-
0.26
-
0.33
-
0.4
V'H
Any
Voltage
Between
Voe
& Grid
V"
I,
or
6
-
-
±O.1
-
±1
-
±1
6
-
-
2
-
20
-
40
Gnd
Quiescent
Vee
Device
or
Current
Gnd
I"
-
-
V
-
-
0.8
-
0.8
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±O.1
-
±1
-
±1
JJA
5.5
-
-
2
-
20
-
40
JJA
-
100 360
-
450
-
490
JJA
2
to
-
V"
V"
Input Leakage
2
V"
4.5
V'H
TTL Loads
-
5.5
-4
or
-
4.5
-
or
V"
Vm
2
to
5.5
V"
TTL Loads
Min Typ Max Min Max Min Max
or
Voe
a
or
Gnd
Additional
Quiescent
Device Current
per input pin:
1 unit load
~Icc
4.5
Vcc-2.1
to
5.5
"'For dual-supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCTINPUT LOADING TABLE
INPUT
UNIT LOADS'
ALL
'Unit load is Ll.lcc limit specified in Static Characteristic
Chart, e.g., 360 pA max. @ 25° C.
86 ____________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC21
CD54/74HCT21
SWITCHING CHARACTERISTICS (Vee = 5 V, T. = 25°C, Input t" I, = 6 ns)
Propagation Delay, Data Input to Output Y (Fig. 1)
t pH , t p ,
Power Dissipation Capacitance'
TYPICAL
HCT
HC
11
9
CL
(pF)
15
CHARACTERISTIC
-
Cpo
36
UNITS
ns
42
pF
'CPO is used to determine the dynamic power consumption, per gate.
Po = Vee 2 f, (Cpo + C l ) where: f, = input frequency
C l = output load capacitance
Vee = supply voltage
SWITCHING CHARACTERISTICS{C L = 50 pF, Input t" t, = 6 ns)
CHARACTERISTIC
Propagation Delay,
Input to Output
(Fig.1)
Transition Times
(Fig.1)
Input
Capacitance
Vee
2
4.5
6
2
4.5
6
t pLH
t PHL
hlH
hHL
_40° C to +85° C
_55° C to +125° C
25°C
74HCT
HC
HCT
74HC
54HCT
UNITS
54HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
165
110 140
27
22
28
34
33
41
ns
19
24
28
75
95
110
22
15
15
19
19
22
ns
13
16
19
-
C,
10
-
10
-
10
-
10
-
10
-
10
pF
92CS- 39823
I
I Input Level
I Switching Voltage. Vs
Fig. 1 -
54/74HC
Vee
50% Vee
54/74HCT
3V
1.3 V
Transition times and propagation delay times.
87
TechnicaIOala. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC27
CD54/74HCT27
File Number
1648
High-Speed CMOS Logic
Triple 3-lnput NOR Gate
Type Features:
• Buffered Inputs
• Typical CD54/74HC27 Propagation Delay = 7ns
@ Vee = 5v, C L = 15pF, TA = 25° C
FUNCTIONAL DIAGRAM AND
TERMINAL ASSIGNMENT
The RCA-CD54174HC27 and CD54174HCT27 logic gates
utilize silicon-gate CMOS technology to achieve operating
speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices
have the ability to drive 10 LSTTL loads. The CD54174HCT
logic family is functionally as well as pin compatible with
the standard 54LS/74LS logic family.
-The CD54HC27 and CD54HCT27 are supplied in 14-lead
hermetic dual-in-line.ceramic packages (F suffix). The
CD74HC27 and CD74HCT27 are supplied in 14-lead dualin-line plastic packages (E suffix) and in 14-lead dual-in, line surface mount plastic packages (M suffix). Both types
are also available in chip·form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
•• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
, • Significant Power Reduction Compared to LSTTL
Logic ICs
• 'Alternate Source is Philips/Signeties
• CD54HCfCD74HC Types:
2 to 6 V Operation
High Noise Immunity: NiL = 30%, NiH = 30%
of Vee, @ Vee = 5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Di;ect LSTTL Input Logic Compatibility
V'L 0.8 V Max., V'H 2 V Min.
CMOS Input Compatibility
. I,:s 1 pA @ VOL, VOH
=
nY
=
nA
L
L
L
H
H
L
H
H
TRUTH TABLE
nC
nB
nY
L
L
H
L
H
L
H
L
L
L
L
L
L
L
H
H
H
L
L
H
L
H
H
L
92CS-38425
LOGIC DIAGRAM
92CS-38425
L = Low Le.el
H = High LeVel
88 _____________________----------------------~-----------------
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC27
CD54/74HCT27
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) .................................................................................. -0.5 to + 7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5V) ...................................................... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V) .................................................. ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V) ................................................... ±25mA
DC Vee OR GROUND CURRENT (lee) ................................................................................... ±50mA
POWER DISSIPATION PER PACKAGE (Po):
For T. =-40 to +60° C (PACKAGE TYPE E) ............................................................................ 500 mW
For T. =+60 to +85° C (PACKAGE TYPE E) ............................................... Derate Linearly at 8 mW/o C to 300 mW
For T. =-55 to +100°C (PACKAGE TYPE F, H) ......................................................................... 500 mW
For T. = +100 to +125°C (PACKAGE TYPE F, H) .......................................... Derate Linearly at 8 mW/oC to 300 mW
For T. = -40 to +70° C (PACKAGE TYPE M) ........................................................................... 400 mW
For T. = +70 to +125° C (PACKAGE TYPE M) .............................................. Derate Linearly at 6 mW/o C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .......................................................................................... -55 to +125°C
PACKAGE TYPE E, M.. . .. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. -40 to +85° C
STORAGE TEMPERATURE (T..,) ................................................................................. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ...................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only .................................................................................. +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA - Full Package-Temperature Range) Vcc:'
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage V" Vo
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t " tf
at2V
at 4.5 V
at6 V
LIMITS
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
V
V
'Unless otherwise specified, all voltages are referenced to Ground.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 89
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD 54/74H C27
CD54/74HCT27
STATIC ELECTRICAL CHARACTERISTICS
CD74HC27/CD54HC27
CD74HCT27/CD54HCT27
TEST
74HC/54HC
74HC
54HC
CONDITIONS
TYPES
TYPE
TYPE
-401
-551
+8So C
+125°C
TEST
CONDITIONS
74HCT/54HCT
74HCT
54HCT
TYPES
TYPE
TYPE
+25°C
-401
+85°C
-551
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
V
10
mA
Vee
V
V,
V
Vee
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
V,"
Low-Level
Input Voltage
V"
High-Level
V"
Output Voltage
or
VO "
CMOS Loads
-0.02
V,"
2
1.5
-
-
4.5
3.15
1.5
-
-
6
4.2
-
1.5
-
-
3.15
-
3.15
-
-
4.2
-
4.2
-
Min Typ Max Min Max Min Max
4.5
Low-Level
Output Voltage
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
CMOS Loads
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
V"
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
Input Leakage
-
-
3.84
-
3.7
-
or
V,"
-5.2
6
5.48
-
-
5.34
-
5.2
-
V,"
2
0.1
-
0.1
-
0.1
V"
4.5
-
-
0.02
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
.0.1
-
.1
-
.1
pA
5.5
-
-
2
-
20
-
40
IJA
-
100 360
-
450
-
490
IJA
to
V 1L
or
4
4.5
-
-
0.26
-
0.33
-
0.4
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
6
-
-
.0.1
-
.1
-
.1
Any
Voltage
Between
Vee
I,
2
V"
3.98
V"
Current
-
5.5
4.5
V,"
TTL Loads
2
4.5
-4
or
-
-
or
V"
Yo,
-
to
5.5
V"
TTL Loads
2
-
or
Vee
Gnd
Quiescent
Vee
Device
or
Current
Icc
&Gnd
Vee
0
6
-
-
2
-
20
-
or
40
Gnd
Gnd
4.5
Additional
Quiescent
Device Current
per input pin:
1 unit load
.6.lcc·
Vcc-2.1
to
5.5
"For dual-supply systems theoretical worst C8S8 (V,
=2.4 V, Va; =5.5 V) specification. is 1.8 mA.
HCT Input Loading Table
Input
All
Unit Loads'
1.5
'Unit Load is ~Icc limit specified in Static Characteristic
Chart, e.g., 360 pA max. @ 25 0 C.
9o _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
_____________________________________________________________ TechnicaIOata
CD54/74HC27
CD54/74HCT27
SWITCHING CHARACTERISTICS (Vee = 5 V, T. = 25° C, Inpul I" I, = 6 ns)
TYPICAL
HC
HCT
CL
(pF)
SYMBOL
Propagation Delay, Data Input to Output Y (Fig. 1)
15
t pLH
t pHl
7
9
ns
Power Dissipation Capacitance"
-
Cpo
26
28
pF
CHARACTERISTIC
'CPD
UNITS
is used to determine the dynamic power consumption, per gate.
PD =Vee' f, (Cpo + Cd
f, = input frequency
C L = output load capacitance
Vee =supply voltage
SWITCHING CHARACTERISTICS (CL
= 50 pF,
CHARACTERISTIC
SYMBOL
Vee
Propagation Delay,
Input to Output
(Fig. 1)
t plH
t pHL
2
4.5
6
2
4.5
6
Transition Times
(Fig. 1)
Input
Capacitance
hLH
hHL
_40° C 10 +85° C
_55° C 10 +125° C
25°C
54HCT
UNITS
54HC
HC
HCT
74HC
74HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
120
145
95
35
29
23
24
19
29
ns
20
16
25
110
75
95
15
19
22
15
19
22
ns
13
16
19
-
C,
Inpul I" I, = 6 ns)
10
10
10
"'~-l1"""'
INPUT
=_~
----
-----
t PHL
~
____ 90%
10
10
10
pF
,INPUT
~
LEVEL
------VS
------10%
tpLH
OUTPUT
92CS-37991RI
Fig. 1 - Transition times and propagation delay times.
_____________________________________________________________________ 91
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC30
CD54/74HCT30
File Number
1652
High-Speed CMOS Logic
a-Input NAND Gate
A
B
Type Features:
C
o
4
8
E
6
F
G
11
H
12
y
=ABCDEFGH
• Buffered inputs and outputs
• Typical propagation delay = 10 ns
@Vcc=5V, CL= 15pF, TA=25°C
92C$-38426
FUNCTIONAL DIAGRAM
The RCA-CD54174HC30 and CD54/74HCT30 each contain
an eight-input NAND gate in one package. They provide the
system designer with the direct implementation of the
positive logic a-input NAND function.
The CD54HC/HCT30 are supplied in 14-lead ceramic dualin-line packages (F suffix). The CD74HC/HCT30 are
supplied in 14-lead dual-in-line plastic packages (E suffix)
and in 14-lead dual-in-line surface-mount plastic packages
(M suffix). Both types are also available in chip form (H
suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Output.5 - 10 LSTTL Loads
Bus Driver Outputs - 15 LS TTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
N,L = 30%, N,H = 30% of Vee; @ Vee = 5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, ::; 1 fJA @ VOL, VO H
TRUTH TABLE
INPUTS
A
L
X
X
X
X
X
X
X
H
92CS- 384 zeRI
B
X
L
X
X
X
X
X
X
H
C
X
X
L
X
X
X
X
X
H
D
X
X
X
L
X
X
X
X
H
E
X
X
X
X
L
X
X
X
H
OUTPUT
F
X
X
X
X
X
L
X
X
H
G
X
X
X
X
X
X
L
X
H
H
X
X
X
X
X
X
X
L
H
Y
H
H
H
H
H
H
H
H
L
H = HIGH voltage level
L = LOW voltage level
X = Don't care
LOGIC DIAGRAM
92 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
- - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC30
CD 54/74H CT30
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) "',.,', .......................................................................... -0.5 to + 7 V
DC INPUT DIODE CURRENT, I,K (FOR V, < -0.5 V OR V, > Vee +0.5V) ...................................................... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V) .................................................. ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V) ................................................... ±25mA
DC Vee OR GROUND CURRENT (Icc) ................................................................................... ±50mA
POWER DISSIPATION PER PACKAGE (Po):
For TA =-40 to +60°C (PACKAGE TYPE E) ............................................................................ 500 mW
For TA =+60 to +85°C (PACKAGE TYPE E) ............................................... Derate Linearly at 8 mW/oC to 300 mW
For T A =-55 to +100° C (PACKAGE TYPE F, H) ......................................................................... 500 mW
For TA =+100 to +125°C (PACKAGE TYPE F, H) .......................................... Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) .. , ........................................................................ 400 mW
For TA = +70 to +125°C (PACKAGE TYPE M) ............................................. Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .......................................................................................... -55 to +125° C
PACKAGE TYPE E. M ........................................................................................... -40 to +85°C
STORAGE TEMPERATURE (T".) ................................................................................. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ...................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only .................................................................................. +300° C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
MIN.
MAX.
UNITS
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vce:'
CD54174HC Types
2
6
CD54174HCT Types
4.5
5.5
DC Input or Output Voltage V" Vo
0
Vce
V
V
Operating Temperature TA:
CD74 Types
-40
+85
CD54 Types
-55
+125
at2V
0
1000
at 4.5 V
0
500
at6V
0
400
°C
Input Rise and Fall Times t" tf
ns
'Unless otherwise specified, all voltages are referenced to Ground.
Vcc
A
1
14
B
2
13 N.C.
C
3
12 H
D
4
11 G
E
5
10 N.C.
F
6
9 N,C.
GND
7
8·
Y
92CS- 38427RI
TERMINAL ASSIGNMENT
______________________________________________________________ 93
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC30
CD 54/74HCT30
STATIC ELECTRICAL CHARACTERISTICS
CD74HC30/CD54HC30
TEST
CONDITIONS
CD74HCT30/CD54HCT30
74HC/54HC
TYPES
74HC
TYPE
54HC
TYPE
+25"C
-401
+85°C
-551
TEST
CONDITIONS
74HCT/54HCT
TYPES
74HCT
TYPE
54HCT
TYPE
-401
-551
+85"C
+125"C
CHARACTERISTIC
UNITS
V,
V
10
rnA
Vee
V
+25°C
+125"C
V,
V
Vee
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
V'H
Low-Level
Input Voltage
V"
High-level
V"
VOH
Output Voltage
CMOS Loads
or
-0.02
V'H
2
1.5
1.5
-
1.5
-
3.15
-
-
4.5
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
Min Typ Max Min Max Min Max
4.5
Low-Level
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
Va'
CMOS Loads
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V'H
I,
-
-
3.84
-
3.7
-
or
V'H
-5.2
6
5.48
-
-
5.34
-
5.2
-
V'H
2
-
0.1
-
0.1
-
0.1
V"
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V'H
0.02
4
4.5
-
-
0.26
-
0.33
-
0.4
V'H
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
±1
Any
Voltage
Between
or
6
-
-
±O.1
-
±1
-
Vee
or
Current
Gnd
I"
0
6
-
-
Additional
Quiescent
Device Current
per input pin:
1 unit load
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
--
0.33
-
0.4
V
5.5
-
-
±O.1
-
±1
-
±1
~A
5.5
-
-
2
-
20
-
40
~A
-
100 360
-
450
-
490
~A
to
or
V"
& Gnd
Gnd
Device
V
V"
or
Quiescent
-
V"
3.98
Vee
Current
2
V"
V"
Input Leakage
-
5.5
4.5
V'H
TTL Loads
2
4.5
-4
or
-
-
or
V"
Output Voltage
-
to
5.5
V"
TTL Loads
2
-
2
-
20
-
V"
or
Gnd
40
4.5
Vcc-2.1
to
5.5
6 1cc
·For dual-supply systems theoretical worst case (V,
=2.4 V, Vee =5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
All
Unit Loads·
0.6
'Unit Load is 61cc limit specified in Static Characteristic
Chart, e.g., 360/lA max. @ 250 C.
94 ________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC30
CD54/74HCT30
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Inpul I" I, = 6 ns)
CHARACTERISTIC
Propagation Delay, Data Input to Output
Y (Fig. 1)
Power Dissipation Capacitance'
TYPICAL
HCT
HC
CL
(pF)
SYMBOL
15
t pLH
t pHL
10
11
ns
-
Cpo
25
26
pF
UNITS
·C PD 15 used to determine the dynamic power consumption. per gate.
PO =Vee' f, (Cpo + Cc)
f, = input frequency
C L = output load capacitance
Vee = supply voltage
SWITCHING CHARACTERISTICS (CL = 50 pF, Inpul I" t, = 6 ns)
CHARACTERISTIC
SYMBOL
Vee
Propagation Delay,
Input to Output
(Fig. 1)
Transition Times
(Fig. 1)
t PLH
t pHL
2
4.5
6
2
4.5
6
Input
Capacilance
trLH
hHL
-55°C 10 +125°C
25°C
-40°C 10 +85°C
HC
HCT
74HC
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max, Min. Max, Min, Max. Min. Max, Min. Max.
195
165
130
ns
33
39
28
35
42
26
33
22
28
110
75
95
19
ns
22
15
15
19
22
13
16
19
-
C,
-
10
10
10
____
"~df ~"o'"
INPUT
=_~
----
----IpHL
~
10
10
10
pF
,INPUT
~
LEVEL
90%
------VS
------10%
tpLH
OUTPUT
'THL
92CS-37991RI
Fig. 1 - Transition times and propagation delay times.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 95
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC32
CD54/74HCT32
File Number
1643
High-Speed CMOS Logic
Quad 2-lnput OR Gate
Type Features:
•
Typical propagation delay = 7 ns
@ Vee = 5 V, C L = 15 pF, TA = 25°C (HC32)
FUNCTIONAL DIAGRAM AND
TERMINAL ASSIGNMENT
The RCA-CD54174HC32 and CD54/74HCT32 contain four
2-input OR gates in one package.
The CD54HC/HCT32 are supplied in 14-lead hermetic dualin-line ceramic packages (F suffix). The CD74HC/HCT32
are supplied in 14-lead dual-in-line plastic packages (E suffix) and in 14-lead dual-in-line surface mount plastic packages (M suffix). Both types are also available in chip form
(H suffix).
Family Features:
•
•
•
•
•
•
•
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85° C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to
LSTTL Logic ICs
Alternate Source is PhilipslSignetics
CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity: N'L = 30%, N,H = 30% of Vee
@ Vee = 5 V
CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, :S 1 J1A @ VOL, VOH
TRUTH TABLE
nA~ nY
nB
INPUTS
OUTPUT
CD54/14HC32
nA
nA~
nB
CD54/74HCT32
nY
nB
nY
L
L
L
L
H
H
H
L
H
H
H
H
92CS-38435
H = HIGH voltage level.
L = LOW voltage level.
Fig. 1 - Logic diagrams.
96 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC32
CD54/74HCT32
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE. (Vee):
(Voltages referenced to ground) .................................................................................. -0.5 to + 7 V
DC INPUT DIODE CURRENT. I'K (FOR V. < -0.5 V OR V. > Vee +0.5V) ...................................................... ±20mA
DC OUTPUT DIODE CURRENT. 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V) .................................................. ±20mA
DC DRAIN CURRENT. PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V) ................................................... ±25mA
DC Vee OR GROUND CURRENT (Icc) ................................................................................... ±50mA
POWER DISSIPATION PER PACKAGE (Po):
For T A =-40 to +60° C (PACKAGE TYPE E) ............................................................................ 500 mW
For T A = +60 to +85° C (PACKAGE TYPE E) ............................................... Derate Linearly at 8 mWI"C to 300 mW
For TA =-55 to +100°C (PACKAGE TYPE F. H) ......................................................................... 500 mW
For TA = +100 to +125°C (pACKAGE TYPE F. H) .......................................... Derate Linearly at 8 mWI"C to 300 mW
For TA = -40 to +70° C (PACKAGE TYPE M) ............................................................................ 400 mW
For TA = +70 to +125°C (PACKAGE TYPE M) .............................................. Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F. H .......................................................................................... -55 to +125°C
PACKAGE TYPE E. M .......................................................................................... -40 to +85°C
STORAGE TEMPERATURE (T".) ................................................................................. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ...................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in .. 1.59 mm)
with solder contacting lead tips only ............................................................................ .
+300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within the
following ranges:
LIMITS
UNITS
CHARACTERISTIC
MIN.
MAX.
Supply Voltage Range (For TA = Full Package Temperature Range) Vee:"
CD54174HC Types
CD54/74HCT Types
DC Input or Output Voltage V,. Vo
2
6
V
4.5
5.5
V
0
Vce
V
Operating Temperature T A:
CD74 Types
-40
+85
·C
CD54 Types
-55
+125
·C
at 2 V
0
1000
ns
at 4.5 V
0
500
ns
at 6 V
0
400
ns
Input Rise and Fall Times. t" tf
'Unless otherwise specified, all voltages are referenced to Ground.
97
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC32
CD54/74HCT32
STATIC ELECTRICAL CHARACTERISTICS
CD74HC32/CD54HC32
CD74HCT32/CD54HCT32
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125° C
CHARACTERISTICS
UNITS
+25°C
10
Vee
Vo
Vee
V
rnA
V
V
V
High-Level
Input Voltage
VO"
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
VO "
CMOS Loads
or
-0.02
VO
"
Min Typ Max Min Max Min Max
2
1.5
-
-
1.5
-
1.5
-
4.5
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
2
-
-
0.5
-
0.5
-
05
4.5
-
-
1.35
-
1.35
-
135
6
-
-
18
-
1.8
-
1.8
Low-Level
Output Voltage
CMOS Loads
2
1.9
-
-
1.9
-
1.9
-
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
VO
"
-
2
-
-
0.8
-
0.8
-
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
01
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
pA
5.5
-
-
2
-
20
-
40
pA
-
100
360
-
450
-
490
pA
-
V
to
0.8
V
V"
-
-
3.84
-
3.7
-
or
VO
"
-5.2
6
5.48
-
-
5.34
-
5.2
-
VO
"
2
-
-
0.1
-
01
-
0.1
V"
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
VO
"
V"
or
4
4.5
-
-
0.26
-
0.33
-
0.4
or
VO
"
5.2
6
-
-
0.26
-
0.33
-
0.4
VO"
Any
Input Leakage
10
Voltage
Vee
or
6
-
-
0.1
-
±1
-
±1
Gnd
Icc
Vee
Vee
or
Between
Vee and
Gnd
Quiescent Device
Current
2
V"
3.98
V"
Current
-
5.5
4.5
VO
"
TTL Loads
-
4.5
-
-4
or
2
to
5.5
or
V"
Yo,
Min Typ Max Min Max Min Max
4.5
-
4.5
V"
TTL Loads
+25°C
Vo
0
6
-
-
2
Gnd
-
20
-
40
or
Gnd
Additional
4.5
Quiescent Device
Vee -2.1
Current per
1 Unit Load
to
5.5
Input Pin"
!:lIce
*For dual-supply systems theoretical worst case (VI
=2.4 V, Vee =5.5 V) specification is 1.8 rnA.
HCT INPUT LOADING TABLE
INPUT
UNIT LOADS •
All Inputs
1.5
• Unit load is ll.lcc limit specified in Static Characteristic
Chart, e.g., 360 fJA max. @ 25° C.
98 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
_____________________________________________________________ TechnicaIData
CD54/74HC32
CD54/74HCT32
SWITCHING CHARACTERISTICS (Vee
=5 V, T. = 25° C,
Input t., t,
=6 n5)
TYPICAL VALUES
CHARACTERISTIC
UNITS
SYMBOL
CL
pF
Propagation Delay
54/74HC
54174HCT
7
9
ns
22
pF
tPLH
15
A. B to Y
t PHL
-
Power Dissipation Capacitance
22
Cpo"
" Cpo is used to determine the dynamic power consumption. per gate.
Po = f; Vee 2 (Cpo + Cc) where:
f; = input frequency.
CL = output load capacitance.
Vee = supply voltage.
SWITCHING CHARACTERISTICS (C L = 50 pF, Input t" t, = 6 n5)
_40° C to +85° C
25°C
CHARACTERISTIC
SYMBOL
HC
Vee
HCT
74HC
-55°C to +125°C
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
115
-
135
24
23
30
27
36
-
20
-
23
-
75
-
95
-
110
-
15
15
19
19
22
22
13
-
16
-
19
-
Propagation Delay
t PLH
2
90
-
A. B to Y
tPHL
4.5
18
6
15
tTLH
2
trHL
4.5
6
Figure 2
Transition Times
Figure 2
Input Capacitance
-
C,
-
10
-
10
-
10
tr= 6 ns
-
If
10
-
10
-
-
10
ns
ns
pF
= 6 ns
---90%
----vs
---10%
GND
92CS-38436
I nput Level
Switching Voltage. Vs
54174HC
54174HCT
Vee
3V
50% Vee
1.3 V
Fig. 2 - Transition times and propagation delay times.
____________________________________________________________________ 99
TechnicaIOala _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC42
CD54/74HCT42
File Number 1689.
High-Speed CMOS Logic
1
Vii
AD 15
2
Y,
A1 14
3
Vii
A2 13
4
Y3
A3 '2
5
Y4
6
Ys
7
9
V6
10
Y7
Va
11
Y9
BCD to Decimal Decoder (1-of-10)
Type Features:
• Buffered inputs and outputs
• Typical propagation delay = 12 ns @ Vee = 5V, C L = 15 pF
TA = 25°C (HC42)
92CS- 38860
FUNCTIONAL DIAGRAM
The RCA-CD54J74HC42 and CD54174HCT42 BCD-toDecimal Decoders utilize silicon-gate CMOS technology to
achieve operating speeds similar to LSTTL decoders with
the low power consumption of standard CMOS integrated
circuits. These devices have the capability of driving 10
LSTTL loads and are compatible with the standard 54LS
174LS logic family. One of ten outputs (low on select) is
selected in accordance with the BCD input. Non-valid BCD
inputs result in none of the outputs being selected (all
outputs are high).
The CD54HC42 and CD54HCT42 are supplied in 16-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC42 and CD74HCT42 are supplied in 16-lead dualin-line plastic packages (E suffix), and in 16-lead dual-inline surface mount plastic packages (M suffix). Both types
are also available in chip form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to·+85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 30%, MH = 30% O(Vee: @ Vee = 5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, ::s 1 /lA @ VOL, VO H
Yo
1
16 Vee
Y1
15 AO
Y2
14 A1
YO
13
Yo
12 A3
A2
Yo
11
Va
Yo
10
VB
GND
9Y7
TERMINAL ASSIGNMENT
Fig. 1 - Logic diagram
92CS-38B61
100 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
_______________________________ Technical Data
CD54/74HC42
CD 54/74H CT42
MAXIMUM RATINGS. Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground)
. , ...................... .
DC INPUT DIODE CURRENT, I" (FOR V, < -0.5 V OR V, > Vee +0.5V)
DC OUTPUT DIODE CURRENT, 10< (FOR Vo < -0.5 V OR Vo > Vee TO.5V)
. .. -0.5 to + 7 V
=20mA
:,:20mA
DC DRAIN CURRENT, PER OUTPUT (101 (FOR -05 V < Vo < Vee + 05VI
DC Vee OR GROUND CURRENT (Ice)
=25mA
±50mA
POWER DISSIPATION PER PACKAGE (Pol
For T. = -40 to +60° C (PACKAGE TYPE EI
.500 mW
For T. = +60 to +85° C (PACKAGE TYPE E) .
For T. = -55 to +100°C (PACKAGE TYPE F, HI
Derate Linearly at 8 mW;oC to 300 mW
... 500 mW
Derate Linearly at 8 mwrc to 300 mW
For T. = +100 to +125°C (PACKAGE TYPE F, HI
For T. = -40 to +70°C (PACKAGE TYPE MI
ForT. = +70to +125°C (PACKAGE TYPE MI.
... 400 mW
Derate Linearly at 6 mW/o C to 70 mW
OPERATING-TEMPERATURE RANGE (T.I
PACKAGE TYPE F, H ............ .
PACKAGE TYPE E, M .. .
. ......... -55 to ~125°C
. ...... -40 to ~85° C
STORAGE TEMPERATURE (T",I
LEAD TEMPERATURE (DURING SOLDERINGI
....... -65 to -150°C
At distance 1/16 ± 1/32 In. (1.59 ± 0.79 mml from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 In. 1.59 mml
..........
~265°
C
with solder contacting lead tips only
RECOMMENDED OPERATING CONDITIONS:
For maximum reliabilily. nominal operaling condilions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA - Full Package Temperature Range) Vee:'
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V" Va
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t r, tt
at 2 V
at 4,5 V
at 6 V
..
'Unless otherWise specified, all voltages are referenced to Ground.
MIN.
MAX.
2
4.5
0
6
5.5
Vee
-40
-55
+85
+125
0
0
0
1000
500
400
UNITS
V
V
°C
ns
TRUTH TABLE
Inpuls
Out puis
A3
A2
A1
AO
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YB
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
Y9
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L = Low Voltage Level
H = High Voltage Level
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 101
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD 54/74H C42
CD 54/74H CT42
STATIC ELECTRICAL CHARACTERISTICS
CD74HC421CD54HC42
TEST
CONDITIONS
CD74HCT421CD54HCT42
74HC/54HC
TYPES
74HC
TYPES
54HC
TYPES
+25'C
-40/
+85°C
-55/
TEST
CONDITIONS
74HCT/54HCT
TYPES
74HCT
TYPES
54HCT
TYPES
+25°C
-40/
+85'C
-55/
+125°C
CHARACTERISTIC
UNITS
V,
V
10
mA
Vee
V
+125°C
V,
V
Vee
V
Min Typ Max Min Max Min Max
High-Level
1.5
-
-
1.5
-
1.5
-
4.5 3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
2
Input Voltage
V'H
low-Level
Input Voltage
V"
High-level
V"
Output Voltage
VOH
CMOS Loads
or
,
-0.02
V'H
-
Low-Level
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
Yo,
6
-
-
1.8
-
1.8
-
1.8
CMOS Loads
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
Input Leakage.
or
6
5.9
-
-
5.9
-
5.9
-
V'H
4.5 3.98
-
-
3.84
-
3.7
-
or
-
-
5.34
-
5.2
-
V'H
V"
V'H
-5.2
6
2
-
-
0.1
-
0.1
-
0.1
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V'H
5.48
4
4.5
-
-
0.26
-
0.33
-
0.4
or
V'H
5.2
6
-
-
0.26
-
0.33
-
0.4
V'H
6
-
-
±O.1
-
±1
-
±1
Any
Voltage
Between
Vee
&Gnd
6
-
-
8
-
80
-
160
or
Gnd
Quiescent
Current
or
Icc
0
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±O.1
-
±1
-
±1
#A
5.5
-
-
8
-
80
-
160
#A
-
100 360
-
450
-
490
#A
to
or
Gnd
Gnd
4.5
Additional
Quiescent
Device Current
Vcc-2.1
per input pin:
1 unit load
-
Vee
Vee
Device
2
V"
or
Vee
I,
-
V"
V"
Current
2
V"
V'H
TTL Loads
-
5.5
-4
or
-
4.5
-
or
V"
Output Voltage
2
to
5.5
V"
TTL Loads
Min Typ Max Min Max Min Max
4.5
to
5.5
!1lcc·
°For dual-supply systems theonstlcal worst case (V, = 2.4 V. Vee = 5.5 V) specification is 1.8 mAo
HCT Input Loading Table
Input
ALL
Unit Loads'
. ·Unit Load is .6. Icc limit specified in Static Characteristic Chart.
e.g .• 360 #A max. @ 25' C.
102 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC42
CD 54/74HCT42
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25° C, 'Input t" t, = 6 n5)
CHARACTERISTIC
Any Input to Y
CL
(pF)
15
SYMBOL
-
Cpo
Power Dissipation Capacitance"
TYPICAL
54n4HCT
54/74HC
14
12
tPHL. tpLH
65
UNITS
ns
pF
70
"Cpo '5 used to determine the dynamic power consumption. per package,
Po = Vee' f, (Cpo + Cd where:
fi = input frequency.
C L = output load capacitance.
Vee = supply voltage.
SWITCHING CHARACTERISTICS (CL = 50 pF, Input t" t, = 6 n5)
CHARACTERISTIC
SYMBOL'
Vee
Propagation ~elay,
Any Input to Y
t PLH
t pHL
2
4.5
6
2
4.5
6
Output
Transition Time
Input
Capacitance
hHl
tTLH
C,
-40°C to +85°C
-55° C to +125° C
25°C
HCT
74HC
74HCT
UNITS
54HC
54HCT
HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
150 190 - 225 44
35
45
53
ns
30
38
38
26
33
95
110 75
15
15
19
19
22
22
ns
19
13
16
-
-
10
-
-
-
-
-
-
-
-
-
10
-
10
-
10
-
10
-
-
-
-
-
Input Level
Switching Voltage, Vs
-
10
pF
-
54n4HC
54n4HCT
Vee
3V
50% Vcc
1.3 V
92CS- 37882
Transition times and propagation delay times.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 103
Technical Data ___________________________________________________________
CD54/74HC73
CD54/74HCT73
1J
,.
"
12
'"
1 CP
13
10
1Q
,.
File Number
1721
Dual J-K Flip-Flop with Reset
Negative-Edge Trigger
Type Features:
20
2J
10
"2
iC'P
20
iR
vcc· 4
GNDz11
92CS-39417
FUNCTIONAL DIAGRAM
• Hysteresis on clock inputs for improved noise immunity and
increased input Rise and Fall times.
• Asynchronous Reset
• Complementary Outputs
• Buffered Inputs
• Typical f max = 60MHz @ Vee = 5V, C L = 15pF, TA = 25°C
The RCA-CD54174HC73 and CD54/74HCT73 utilize sili. con-gate CMOS technology to achieve operating speeds
equivalent to LSTTL parts. They exhibit the low power consumption.of standard CMOS integrated circuits, together
with the ability to drive 10 LSTTL loads.
These flip-flops have independent J, K, Reset and Clock
inputs and Q and Q outputs. They change state on the
negative.-going transition of the clock pulse. Reset is accomplished asynchronously by a low-level input. This device is functionally identical to the HC/HCT 107 but differs
in terminal assignment and in some parametric limits.
The 54HCT174HCT logic family is functionally as well as
pin-compatible with the standard 54LS/74LS logic family.
The CD54HC73 and CD54HCT73 are supplied in 14-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC73 and CD74HCT73 are supplied in 14-lead dualin-line plastic packages (E suffix) and in 14-lead dual-inline surface-mount plastic packages (M suffix). Both types
are also available in chip form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15.LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• .Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity: ML = 30%, N,H = 30% of Vee,
@ Vee = 5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility I, :s 1 pA @ VOL, VOH
TRUTH TABLE
(EACH FLIP-FLOP)
14(7)
OUTPUTS
INPUTS
Fig. 1 - Logic diagram.
R
CP
J
K
L
H
H
H
H
H
x
'-
X
L
H
L
H
X
X
L
L
H
H
X
"-
''H
a
a
L
H
No change
L
H
H
L
Toggle
No change
H = High Level (Steady State)
L = Low Level (Steady State)
X = Irrelevant
' - = High-to-Low transition
104 ____________________________________________________________________
______________________________________________________________ TechnicaIData
CD54/74HC73
CD54/74HCT73
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ............................. " ................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, 1,K (FOR V, <-0.5 V OR V,
> Vee +
0.5 V) .................................................... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Va < -0.5 V or Va > Vee +0.5 V) ................................................. ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5V < Va < Vee + 0.5 V) ................................................. ± 25mA
DC Vee OR GROUND CURRENT (lee) .................................................................................... ±50mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60"C (PACKAGE TYPE E) ........................................................................... 500 mW
For TA = +60 to +85"C (PACKAGE TYPE E) ............................................. Derate Linearly at 8 mW/"C to 300 mW
For TA = -55 to +100"C (PACKAGE TYPE F, H) ....................................................................... 500 mW
For TA = +100 to +125"C (PACKAGE TYPE F, H) ......................................... Derate Linearly at 8 mW/"C to 300 mW
For T A = -40 to + 70"C (PACKAGE TYPE M) .......................................................................... 400 mW
For TA = +70 to +125"C (PACKAGE TYPE M) ............................................. Derate Linearly at 6 mW;oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .......................................................................................... -55 to +125"C
PACKAGE TYPE E, M .......................................................................................... -40 to +85"C
STORAGE TEMPERATURE (T"g) ................................................................................. -65 to +150"C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ..................................................... +265"C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only .......................... .
.............................................. +300"C
CL
Q
92CM-39231
K
Fig. 2 - Flip-Flop detail.
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vee:'
CD54174HC Types
CD54/74HCT Types
DC Input or Output Voltage V" Va
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t" tft
at 2 V
at4.5 V
at 6 V
..
'Unless otherWise specified, all voltages are referenced to Ground .
tApplicable for all inputs except clock.
UNITS
MIN.
MAX.
2
4.5
6
5.5
V
0
Vee
V
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
______________________________________________________________________ .105
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC73
CD54/74HCT73
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT73, CD54HCT73
CD74HC73, CD54HC73
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
CHARACTERISTIC
UNITS
V,
10
Vee
V
rnA
V
+25°C
V,
Vee
V
V
Min Typ Max Min Max Min Max
Min Typ Max Min Max Min Max
High-Level
Input Voltage
2
V,"
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
Vo"
CMOS Loads
or
-0.02
V,"
1.5
-
-
-
1.5
-
3.15
-
1.5
4.5
3.15
-
-
3.15
-
6
4.2
-
-
4.2
-
4.2
Low-Level
Output Voltage
-4
V,"
-5.2
CMOS Loads
or
0.02
V,"
Input Leakage
Current
-
-
0.5
-
0.5
-
0.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.B
-
1.B
-
1.B
2
1.9
-
-
1.9
-
1.9
-
V"
4.4
-
or
V,"
4.5
4.4
-
-
4.4
6
5.9
-
-
5.9
-
5.9
-
4.5 3.9B
-
-
3.B4
-
3.7
-
or
6
5.4B
-
-
5.34
-
5.2
-
V1H
2
-
-
0.1
-
0.1
-
0.1
V"
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
-
-
0.26
-
0.33
-
0.4
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
Any
Voltage
Between
Vee
&
Gnd
or
6
-
-
±0.1
-
±1
-
±1
6
-
-
4
-
40
-
BO
Gnd
or
Current
Icc
2
-
V
-
-
O.B
-
O.B
-
O.B
V
4.4
-
-
4.4
-
4.4
-
V
4.5 3.9B
-
-
3.B4
-
3.7
-
V
4.5
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
/JA
5.5
-
-
4
-
40
-
BO
/JA
4.5
to
5.5
-
100 360
-
450
-
490
/JA
V"
4.5
Vee
-
to
4
Device
2
5.5
or
Quiescent
-
4.5
-
-
Vee
I,
-
5.5
2
V"
TTL Loads
2
to
V"
or
V"
Vo,
4.5
-
4.5
V"
TTL Loads
+25°C
or
Vee
0
Gnd
or
Gnd
Additional
Quiescent
Device Current
per input pin:
1 unit load
!::.Icc
Vee
, For dual-supply systems theoretical worst case (V,
= 2.4 V, Vee = 5.5 V)
~2.1
specification is 1.8 mAo
HCT Input Loading Table
Input
Unit Loads·
All
0.3
'Unit Load is l!.lcc limit specified in Static Characteristic
Chart, e.g., 360 pA max. @ 25°C.
106 ____________________________________________________________
___________________________________________________________ TechnicaIData
CD54/74HC73
CD 54/74HCT73
SWITCHING CHARACTERISTICS (Vee=5 V, T A =25°C, Inpul t" 1,=6 ns)
CL
SYMBOL
CHARACTERISTIC
Propagation Delay
CPtoO
(pF)
tPLH
15
TYPICAL
HC
HCT
UNITS
13
16
ns
CPtoO
13
15
ns
RtoO,O
12
14
ns
tPHL
CP Frequency
f max
15
60
60
MHz
Power Dissipation Capacitance'
Cpo
-
28
28
pF
'Cpo is used to determine the dynamic power consumption, per flip-flop.
Po = Cpo Vee2fi + L C LVee 2 fo where fi = input frequency, fo = output frequency,
C L = output load capacitance, Vee = supply voltage.
PRE-REQUISITE FOR SWITCHING FUNCTION
LIMITS
TEST
tw
R
Set-up Time
J, K to CP
Hold Time
J, K to CP
Removal Time
CP Frequency
-40°C to +85°C
-55°C 10 +125°C
UNITS
CONDITION
HCT
74HC
74HCT
54HC
54HCT
HC
Vee
V
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
CHARACTERISTIC
Pulse Width
CP
25°C
tsu
tH
IREM
f MAX
2
4.5
6
80
16
14
-
-
-
-
16
-
-
-
-
2
4.5
6
80
16
14
-
-
-
-
18
-
-
-
-
2
4.5
6
80
16
14
-
-
-
16
-
-
-
2
4.5
6
3
3
3
-
3
-
-
-
-
2
4.5
6
80
16
14
-
-
-
12
-
-
-
2
4.5
6
6
30
35
-
-
-
-
30
-
-
-
,ep
,
iR
-2ep
5
-
-
-
-
23
-
-
100
20
17
100
20
17
3
3
3
100
20
17
5
25
29
14
,J
13
iQ
"
Vee
-
-
-
12
'K
20
100
20
17
-
-
-
-
-
-
20
-
-
-
-
-
-
-
3
-
-
-
-
-
-
-
-
15
-
-
-
-
-
-
-
25
-
-
-
120
24
20
-
-
-
-
24
-
-
-
-
120
24
20
-
-
-
-
27
-
-
-
-
120
24
20
3
3
3
-
-
-
24
-
-
-
-
-
-
3
-
-
-
120
24
20
-
-
-
-
18
-
-
-
4
20
23
-
-
-
-
20
-
-
-
ns
ns
ns
ns
ns
MHz
'0
GND
'0 2K
2R
20
2J
2ci
TERMINAL ASSIGNMENT
_______________________________________________________________________ 107
TechnicaIOala ______________________________
CD 54/74HC73
CD 54/74HCT73
SWITCHING CHARACTERISTICS (Cl =-= 50 pF, Input t" tf = 6 n5)
LIMITS
TEST
-40°C to +85°C
25°C
-55°C to +125°C
CHARACTERISTIC
UNITS
CONDITION
HC
HCT
74HC
74HCT
54HC
54HCT
Vee
V
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
200 240
160 Propagation Delay
2
40
32
48
48
4.5
38
tPlH, tPHl
57
ns
CPtoO
6
34
41
28
-
-
160
32
28
-
CPtoQ
2
4.5
6
RtoO,a
2
4.5
6
-
145
29
25
-
34
2
4.5
6
-
-
75
15
13
-
15
-
10
-
10
Output Transition
Time
hLH, hHL
Input Capacitance
C,
-
36
-
-
-
-
-
220
44
38
-
110
22
19
-
-
-
-
10
-
10
-
-
-
180
36
31
-
95
19
16
-
19
10
-
-
-
-
200
40
34
-
-
45
-
-
-
240
48
41
-
-
-
-
43
-
-
-
If
-
-
54
ns
-
51
ns
-
22
ns
pF
10
INPUT
LEVEL
-GND
Q
Q OR-a-
G
'NPUT
92CS- 39232
----------------~
Vs
LEVEL
GND
92CS-39233
______,
~------~
r-_____ 'NPUT
LEVEL
J ORK
'------GND
ISU
INPUT
CP ----------""
LEVEL
92CS-39234
54174HC
Input Level
Switching Voltage, Vs
54174HCT
Vee
3V
50% Vee
1.3 V
Fig. 3 - Transition times, propagation delay times, and setup and hold times.
108 ________________________________________________
_____________________________________________________________ TechnicaIOata
CD54/74HC74
CD54/74HCT74
1476
File Number
High-Speed CMOS Logic
FiEs£T
I
OATA 2
0
'
Dual D Flip-Flop with Set and Reset
Q
Positive-Edge Trigger
6 Q
CLOCI( 3
Type Features:
R"ESEi'3
DATA 12
•
0
Q
F/F-2
CLOCK II
8 ij
CP
S
SET 10
Vee; PIN 14
GNO '" PIN 1
92CS- 3696SRI
• Hysteresis on clock inputs for improved noise immunity and increased input Rise and Fall times.
• Asynchronous Set and Reset
• Complementary Outputs
• Buffered Inputs
• Typical frna< = 50 MHz @ Vee = 5V, C L = 15 pF. TA = 25°C
FUNCTIONAL DIAGRAM
The RCA-CD54/74HC74and CD54/74HCT74 utilizesilicongate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together
with the ability to drive 10 LSTTL Loads.
This flip-flop has independent DATA, SET, RESET and
CLOCK inputs and Q and Q outputs. The logic level present
at the data input is transferred to the output during the
positive-going 'transition of the clock pulse. SET and
i"'fESIT are independent of the clock and are accomplished
by a low level at the appropriate input.
The 54HCT/74HCT logic family is functionally as well as pin
compatible with the standard 54LS/74LS logic family.
The CD54HC74 and CD54HCT74 are supplied in 14-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC74 and CD74HCT74 are supplied in 14-lead dualin-line plastic packages (E suffix) and in 14-lead dual-inline surface.mount plastic packages (M suffix). Both types
are also available in chip form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to + 85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML ~ 30%, N'H~ 30% of Vee; @ Vee~ 5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L ~ 0.8 V Max., V,H ~ 2 V Min.
CMOS Input Compatibility
I, ~ 1 fJA @ VOL. VO H
TRUTH TABLE
4(10)
INPUTS
CL
CP
D
a
a
L
H
L
H
H
H
H
L
L
H
H
H
X
X
X
X
X
X
H
L
X
H
L
H"
H
L
00
L
H
H"
L
H
...r
...r
L
00
a
92CS- 36966
Fig. 1 - Logic Diagram
RESET
H = High Level (Steady State)
L = Low Level (Steady State)
X = Don't Care
-./= Transition from Low to High level
cpo~----~~
3{11l
v- ~ v- ~ vel
OUTPUTS
SET
NOTES: 00 = the level of
before the indicated input
conditions were established.
'This configuration is nonstable, that is, it will not persist when set
and reset inputs return to their inactive (high) level.
_____________________________________________________________________ 109
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC74
CD54/74HCT74
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground)
DC INPUT DIODE CURRENT, I,K (FOR V, < -0.5 V OR V, > Vee +0.5V)
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V)
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V)
DC Vee OR GROUND CURRENT (Ieel ... , ..
POWER DISSIPATION PER PACKAGE (P D ):
For T. 0 -40 to +60 0 C (PACKAGE TYPE E)
For T.
For T.
For T.
0
0
0
-0.5 to + 7 V
±20mA
±20mA
±25mA
:,:50mA
.............
Derate Linearly at 8 mwr C to
. ....
Derate Linearly at 8 mwrc to
+60 to +85° C (PACKAGE TYPE E)
-55 to +100°C (PACKAGE TYPE F, H) ..
+100 to +125°C (PACKAGE TYPE F, H)
500
300
500
300
mW
mW
mW
mW
For T. ; -40 to +70° C (PACKAGE TYPE M) ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 400 mW
For T.; +70 to +125°C (PACKAGE TYPE M) " " ' , " " " " " " " " " ' , ....... , ..... , .. , .. Derate Linearly at 6 mW;oC to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H .. .
PACKAGE TYPE E, M .... , " ' ' ' ' ' '
STORAGE TEMPERATURE (T",) ...
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
. .. -55 to +125° C
.. ,' -40 to +85°C
with solder contacting lead tips only ",." .... ,",.,"",.,', ..... " .. " ..
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
MIN.
MAX.
UNITS
Supply-Voltage Range (For T. = Full Package Temperature Range) Vee:'
2
6
CD54/74HCT Types
4.5
5.5
V
DC Input or Output Voltage V", Vo "'
0
Vee
V
CD54/74HC Types
V
Operating Temperature T.:
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
at 2 V
0
1000
ns
at 4.5 V
0
500
ns
at 6 V
0
400
ns
Input Rise and Fall Times t" t,o
'Unless otherwise specified, all voltages are referenced to Ground.
oApplicable for all inputs except clock.
'"
10
ICP
IS
IQ
\"
13
VCC
2R
12 2D
"
2CP
10 2S
2Q
GNO
2Q
92CS- 36964
TERMINAL ASSIGNMENT
110 ________________________________________________________________
Technical Data
CD54/74HC74
CD 54/74HCT74
STATIC ELECTRICAL CHARACTERISTICS
CD74HC74/CD54HC74
TEST
CONDITIONS
74HC/54HC
TYPES
CD74HCT74/CD54HCT74
74HC
TYPES
54HC
TYPES
-401
-551
+85°C
+125°C
TEST
74HCT/54HCT
CONDITIONS
TYPES
74HCT
TYPES
54HCT
TYPES
-401
-551
+8So C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
V
10
rnA
Vee
V
+25°C
V,
V
Vee
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
1.5
1.5
1.5
4.5
4.5 3.15
3.15
3.15
to
2
V,"
6
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
YUH
CMOS Loads
or
-0.02
V,"
Min Typ Max Min Max Min Max
4.2
4.2
4.2
5.5
2
0.5
0.5
0.5
4.5
4.5
1.35
1.35
1.35
to
6
1.8
1.8
1.8
5.5
2
1.9
1.9
1.9
V,.
4.5
4.4
4.4
4.4
or
6
5.9
5.9
5.9
V,"
V"
~
TTL Loads
Low-Level
Output Voltage
or
-4
4.5
3.98
3.84
37
or
V,"
-5.2
6
5.48
5.34
5.2
V",
2
0.1
0.1
0.1
V"
0.02
4.5
0.1
0.1
0.1
or
6
0.1
0.1
0.1
CMOS Loads
V,"
4.5
0.26
0.33
0.4
or
6
0.26
0.33
0.4
V,"
:to. 1
±1
±1
Between
or
V,"
V"
V,"
Input Leakage
Vel:.
Current
or
5.2
6
-
Vee
Device
or
Current
Io.:c
4.4
0.8
4.4
V
V
,4.5 3.98
-
-
3.84
0.1
4.5
4.5
-
0.26
5.5
-
:to.l
Any
Voltage
-
3.7
0.1
V
0.1
V
-
0.4
V
±1
±1
IJA
40
80
IJA
490
IJA
0.33
-
Vee
&Gnd
Gnd
Quiescent
4.4
0.8
V"
or
TTL Loads
4.5
0.8
V"
V"
VOL
V
Vee
6
or
80
40
5.5
Gnd
Gnd
4.5
Additional
Quiescent
Device Current
per input pin:
1 unit load
ll. Icc
to
Vcc-2.1
100 360
-
450
-
5.5
'For dual-supply systems theoretical worst case (V, = 2.4 V. Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
Unit Loads'
D
0.5
0.5
0.7
0.75
R
CP
S
..
Unit Load IS llicc limit specified
e.g .. 360 IJA max. @ 25° C.
In
Static Characteristic Chart,
__________________________________________________________________ 111
Technical Data _____________________________________________________________
CD54/74HC74
CD54/74HCT74
SWITCHING CHARACTERISTICS (Vcc = 5 V, TA = 25°C, Input tr,t, = 6 ns)
CHARACTERISTIC
SYMBOL
Propagation Delay
TYPICAL
CL
(pF)
HC
HCT
14
17
17
50
25
17
17
50
30
UNITS
tPLH
tPHl
CP to Q, Q (Fig. 2)
R to Q, Q (Fig. 3)
S to Q, Q (Fig. 3)
CP Frequency
Power Dissipation Capacitance'
15
f MAX
Cpo
15
-
14
ns
MHz
pF
'CPO is used to determine the dynamic power consumption, per flip-flop.
PO Cpo Vee' f, + l: (CL Vee' fo) where: f, input frequency
=
=
fo = output frequency
C L = output load capacitance
Vee = supply voltage
PRE-REQUISITE FOR SWITCHING FUNCTION
CHARACTERISTIC
Data to CP
Set-up Time
(Fig. 4)
tsu
Hold Time
tH
(Fig. 4)
Removal Time
Fl, 5to CP
(Fig. 3)
Pulse Width
tREM
tw
R,S
(Figs. 2, 3)
Pulse Width
CP
(Figs. 2, 3)
CP Frequency
tw
fMAX
LIMITS
TEST
-40°C to +85°C
25°C
-55° C to +125° C
CONDITIONS
HC
HCT
74HC
74HCT
54HC
54HCT
UNITS
Vee (V)
Min. Max. Min. Max. Min. Max, Min. Max. Min. Max. Min. Max.
2
60
90
75
18
12
15
4.5
15
18
12
15
10
13
6
2
3
3
3
4.5
3
3
3
3
3
3
6
3
3
3
ns
2
45
30
40
4.5
9
9
6
8
8
6
6
5
7
8
120 2
100 80
16
20
24
4.5
16
20
24
17
20
6
14
120 100 2
80
18
23
24
4.5
16
20
27
20
6
14
17
4
5
2
6
MHz
20
20
16
4.5
25
25
30
23
6
35
29
SWITCHING CHARACTERISTICS (CL
=50 pF, Input t"t, =6 ns)
LIMITS
CHARA"CTERISTIC
Propagation Delay,
CPtoQ, Q
(Fig. 2)
R, S to Q, Q
VCC
(V)
tpLH
tPHl
t pHL
tPLH
(Fig. 3)
Transition Times
trLH
hHL
(Fig. 5)
Input Capacitance
C,
2
4.5
6
2
4.5
6
2
4.5
6
_40° C to +85° C
-55° C to +125° C
UNITS
HCT
74HC
74HCT
54HC
54HCT
HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
220 - 265 - 175 44
44
53
53
35
35
45
37
30
ns
250 300 - 200 60
60
40
40
50
50
43
51
34
110 75
95
19
19
22
22
15
15
.19
13
16
pF
10
10
10
10
10
10
25°C
112 ____________________________________________________________________
_____________________________________________________________ TechnicaIData
CD54/74HC74
CD54/74HCT74
92CS-36967
92C5·36968
Fig. 2 -
Clock pre-requisite and propagation delays.
Fig. 3 - Reset or Set pre-requisite and propagation delays
92CS-36970
92C5- 36969
Fig. 4 - Data pre-requisite times.
Fig. 5 -
Output transition times.
INPUT LEVEL
____________________________________________________________________ 113
Technical Data _________________________________________________________
CD 54/74HC75
CD54/74HCT75
2(6)
DO
LATCHES
E
14(8)
15(8)
3(7)
01
166.6
Dual 2-Bit Bistable Transpa·r.ent
Latch
16(10) QO
1(11)
10F2
File Number
00
Type Features:
Q1
Q1
• True and Complementary Outputs
• Buffered Inputs and Outputs
13(4)
92CS-3&552
FUNCTIONAL DIAGRAM
The RCA-CD54174HC75 and CD54/74HCT75 are dual2-bit
bistable transparent latches. Each one of the 2-bit latches is
controlled by separate Enable inputs{fEand 2E) which are
active LOW. When the Enable input is HIGH data enters the
latch and appears at the output. When the Enable input
TiE and 2E) is LOW the output is not affected.
a
The CD54HC/HCT75 are supplied in 16-lead hermetic dual- .
in-line packages (F suffix). The CD74HC/HCT75 are supplied in 16-lead dual-in-line plastiC package (E suffix) and
in 16-lead dual-in-line surface mount plastic packages (M
suffix). Both types are also available in chip form
(H suffix).
LATCH 0
16(10)
:>0----000
LE
LE
LE
LE
o
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15lSTTL Loads
• Wide Operating Temperature Range:·
CD74HCIHCTt -40 to + 85°C
• Balanced Propagation delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic IC.
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noice Immunity: NIL =30%, MH 7 30% of Vee;
@ Vee =5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
" ~ 1 uA @ VOL. VOH
Q
LATCH 1
5
OVec
92CS-38553
12
OGND
92CS-38554
Fig. 1 - Logic Diagram
Fig. 2 - Latch Detail
114 _________________________________________________________________
_____________________________________________________________ TechnicaIOata
CD54/74HC75
CD54/74HCT75
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
. ......................... -O.S to + 7 V
(Voltages referenced to ground) ,.
DC INPUT DIODE CURRENT, 1>< (FOR V, < -O.S V OR V, > Vee +O.SV) ..
~ 20 mA
:!: 20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -O.S OR Vo > Vee +O.S V) .
:': 25 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -OS V < Vo < Vee +O.S V)
:': 50 mA
DC Vee OR GROUND CURRENT (Icc)
POWER DISSIPATION PER PACKAGE (Po)
For TA ~ -40 to +60°C (PACKAGE TYPE E)
.............
...........
SOO mW
For TA ~ +60 to +8So C (PACKAGE TYPE E)
Derate Linearly al 8 mWfO C to 300 mW
For TA ~ -55 to +100°C (PACKAGE TYPE F, H)
SOO mW
For TA ~ +100 to +12SoC (PACKAGE TYPE F. H)
Derate linearly at 8 mW/oC to 300 mW
ForT.; -40 to+70°C (PACKAGE TYPE M) .. , ..... , ............ ' .......................... " .. , ... " ....... , ... , .... ,400 mW
ForT.; +70 to +12SoC (PACKAGE TYPE M) ...... " .... , ... , ............ , ........ , ....... Derate Linearly at 6 mWfOC to 70 mW
OPERATING -TEMPERATURE RANGE (TA)
PACKAGE TYPE F, H
PACKAGE TYPE E, M
STORAGE TEMPERATURE (T",)
LEAD TEMPERATUARE (DURING SOLDERING):
At distance 1/16:,: 1/32 in. (1.S9 ± 0.79 mm) from case for to s max.
Unit inserted into a PC Board (min. thickness 1/16 in., 1.S9 mm)
with solder contacting lead tips only
-SS to +12SoC
-40 to+8SoC
-65 +150°C
+300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions s,hould be selected so that operation is always within the following
ranges:
LIMITS
CHARACTERISTIC
MIN.
Supply-Voltage Range (For TA; Full Package-Temperature Range) Vee:'
CD54/74HC Types
CD54!74HCT Types
UNITS
2
4.5
6
5.5
V
0
Vee
V
-40
-55
+85
+125
°C
0
0
0
1000
500
400
DC Input or Output Voltage V, Va
Operating Temperature TA:
CD74 Types
CD54 Types
MAX.
input Rise and Fall Times I" If
at 2V
at 4.5 V
at 6V
ns
'Unless otherwise specified, all voltages are referenced to Ground.
16
15
100
1E
5
14
13
12
6
11
7
10
B
9
100
100
101
2E
Vee
200
201
201
2
3
4
101
101
GNO
200
200
201
TERMINAL ASSIGNMENT
TRUTH TABLE
Inputs
D
L
H
X
E
H
H
L
Outputs
Q
L
H
00
Q
H
L
00
H ; High Level
L; Low Level
X ; Don'l Care
00 ; The level of
a before the transition of E.
______________________________________________________________________ 115
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC75
CD54/74HCT75
STATIC ELECTRICAL CHARACTERISTICS
CD74HC75/CD54HC75
CD74HCT75/CD54HCT75
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
UNITS
CHARACTERISTIC
Vl
10
Vee
V
mA
V
+
25°C
+ 85°C
+
125°C
Vl
Vee
V
V
Min Typ Ma. Min Ma. Min Ma.
High-Level
Input Voltage
V,H
Low-Level
Input Voltage
VOL
High-Level
Output Voltage
1.5
-
-
1.5
-
1.5
-
4.5 3.15
2
VOL
VOH
or
-0.02
V,H
CMOS Loads
or
VIH
Output Voltage
or
VOL
-5.2
0.02
V,H
CMOS Loads
or
V,H
Input Leakage
-
-
3.15
-
3.15
-
-
-
4.2
-
4.2
-
2
-
-
0.5
-
0.5
-
0.5
4.5
4.5
-
-
1.35
-
1.35
-
1.35
to
6
-
-
1.8
-
1.8
-
1.8
5.5
II
2
1.9
-
-
1.9
-
1.9
-
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
VIH
4.5
3.98
-
-
3.84
-
3.7
-
or
6
5.48
-
-
5.34
-
5.2
-
V,H
2
-
-
0.1
-
0.1
-
0.1
V,L
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,H
4.5
-
-
0.26
-
0.33
-
0.4
or
6
-
-
0.26
-
0.33
-
0.4
V,H
5.2
or
6
-
-
;to.l
-
!1
-
!1
Current
or
lee
2
-
-
2
-
2
-
5.5
V
-
-
0.8
-
0.8
-
0.8
V
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
3.7
-
V
VOL
4.5
4.5 3.98
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
Any
Voltage
Between
5.5
Vee
-
-
;to.l
-
±1
-
±1
&
Gnd
Vee
Device
125°C
VIL
4
Gnd
Quiescent
to
-
4.5
Vee
Current
+
Min Typ Ma. Min Ma. Min Ma.
4.2
V,L
TTL Loads
+ 85°C
VOL
-4
V,L
Low-Level
25°C
4.5
6
VOL
TTL Loads
+
JJA
Vee
0
6
-
-
4
-
40
-
80
or
5.5
-
-
-
100 360
4
-
40
-
80
JJA
-
450
-
490
lJA
Gnd
Gnd
4.5
Additional quiescent
Device Current
per input pin:
1 unit load .o.lcc
Vee-2.1
to
5.5
"For dual-supply systemstheonstical worst ease (VI
=2.4 V, Vee; =5.5 V) specification Is 1.8 mAo
HCT Input Loading Table
Input
Unit Loads·
DO, D1
0.8
1E,2E
1.2
'Unit load is Alee limit specified in Static 'Characteristic
360 pA max. @ 25° C.
116 _ _ _ _ _ _ _ _Chart,
_ _e.g.,
__
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
___________________________________________________________ TechnicaIOata
CD54/74HC75
CD54/74HCT75
SWITCHING CHARACTERISTICS (Vee = 5 V. TA = 25°C. Inpul I" I, = 6n5)
TYPICAL
CL ;
(pF)
CHARACTERISTIC
Propagation Delay
DtoO
D to 0
Enable to 0
Enable to 0
Power Dissipation Capacitance'
SYMBOL
15
15
15
15
UNITS
HC75
HCT75
9
10
10
11
46
11
11
11
12
46
tPlH
IpHL
CPD
-
ns
ns
ns
ns
pF
'CPO is used to determine the dynamic power consumption per latch.
PD = V ee 2 Ii (Cpo + Cc)
Ii = Input Frequency
CL = Load Capacitance
Vee = Supply Voltage
PREREQUISITE FOR SWITCHING FUNCTION
LIMITS
TEST
CONDITION
Vee
V
CHARACTERISTIC
Pulse Width
Enable Input
Selup Time
D to Enable
HoldTime
Enable to D
tw
tsu
th
2
4.5
6
2
4.5
6
2
4.5
6
-40°C 10 + 85°C
25°C
HC
HCT
74HC
74HCT
-55°C 10 + 125° C
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
80
16
14
60
12
10
3
3
3
16
-
12
3
-
100
20
17
75
15
1~
3
3
3
20
-
15
-
3
-
120
24
20
90
18
15
3
3
3
24
ns
-
18
ns
-
3
ns
-
______________________________________________________________________ 117
TechnicaIOata _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC75
CD54/74HCT75
SWITCHING CHARACTERISTICS (CL = 50 pF, Input t. tf = 6 ns)
-40°C to + 85°C
25°C
HC
CHARACTERISTIC
SYMBOL
HCT
-55°C to + 125°C
74HCT
74HC
54HC
54HCT
Vee
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay
Data to Q
Propagation Delay
Data toO
Propagation Delay
Enable to Q
Propagation Delay
Enable to Q
Output Transition
Time
Input Capacitance
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
hLH
hHl
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-
-
-
-
-
C,
110
22
19
130
26
22
130
26
22
130
26
22
75
15
13
10
-
-
-
28
-
-
-
-
-
28
-
-
-
-
-
-
-
-
-
30
-
-
-
-
-
-
28
-
-
-
-
-
15
-
-
-
-
-
10
-
140
28
24
165
33
28
165
33
28
165
33
28
95
19
16
10
-
-
-
-
35
-
-
-
-
-
-
-
35
-
-
-
-
-
35
-
-
-
-
-
-
-
-
38
-
-
-
-
-
-
19
-
-
-
-
10
-
165
33
28
195
39
33
195
39
33
195
39
33
110
22
19
10
-
-
-
42
-
-
-
42
-
-
-
42
-
-
-
-
-
45
-
-
-
10
ns
ns
ns
ns
-
22
ns
pF
ENABLE
Q
~H-.::::L...I
Q
-i
~H
~
D~S
~
'w
'su
ANY
OUTPUT
ENABLE
Vs
92CS- 38!:5 7RI
92CS-38558
54174HC
Input Level
Switching Voltage, Vs
h
Vec
50% Vee
54/74HCT
3V
1.3 V
118 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
File Number
CD54/74HC85
CD54/74HCT85
1770
High-Speed CMOS Logic
A3
A2
A1
AO
(A
<
4-Bit Magnitude Comparator
15
13
12
10
{A
Blin
<
{A> Blout
83
82
81
80
Blout
{A= 8)out
(A= 8)ln
(A> 8)ln
11
9
Type Features:
• Buffered inputs and outputs
• Typical propagation delay = 13 ns (Data to Output)
@ Vee = 5V, C L =15 pF, TA = 25°C
• Serial or Parallel expansion without external gating.
FUNCTIONAL DIAGRAM
The RCA-CD54/74HC/HCT85 are high-speed magnitude
comparators that use silicon-gate CMOS technology to
achieve operating speeds similar to LSTTL with the low
power consumption of standard CMOS integrated circuits.
These 4-bit devices compare two binary, BCD, or other
monotonic codes and present the three possible magnitude
results at the outputs (A> B, A < B, and A = B). The 4-bit
input words are weighted (AO to A3 and BO to B3), where A3
and B3 are the most significant bits.
The HC/HCT85 are expandable without external gating, in
both serial and parallel fashion. The upper part of the truth
table indicates operation using a single device or devices in
a serially-expanded application. The parallel expansion
scheme is described by the last three entries in the truth
table. Circuits for serial and parallel comparison of 12 bits
are shown in figures 3 and 4, respectively.
The CD54HC/HCT85 are supplied in 16-lead ceramic dualin-line packages (F suffix). The CD74HC/HCT85 are supplied in 16-lead dual-in-line plastic packages (E suffix) and
in 16-lead dual-in-line surface mount plastic packages (M
suffix). Both types are also available in chip form (H suffix).
Family Features:
III Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT/HCU: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
II CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity:
N,L = 30%, N,H = 30% of Vee; @ Vee = 5 V
II CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility I" S 1 /JA @ VOL, VOH
16
B3
15
(A B)IN
13
4
12
(A >B)OUT
11
(A= B)OUT
10
(A< B)OUT
GND
vcc
A3
B2
A2
A1
B1
AO
BO
92C5-
398~8
TERMINAL ASSIGNMENT
,119
Technical Data-----------------------------------------------------------
CD54/74HC85
CD54/74HCT85
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) •........••...........•••.•.•••.••.........•...................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, I'K (FOR V, <-0.5 V OR V, > Vee + 0.5 V) .............................•...................... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) ....................•........................... ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5 V) ........••...•...•............................... ±25mA
DC Vee OR GROUND CURRENT (lee) ..................••..........•..••................................................. ±50mA
POWER DISSIPATION PER PACKAGE (Po):
For To = -40 to +60°C (PACKAGE TYPE E) .••...•.....................•...•.....................................•.... 500 mW
For To = +60 to +85°C (PACKAGE TYPE E) ......•.•••...............•.................. Derate Linearly at 8 mW/oC to 300 mW
For To = -55 to +100°C (PACKAGE TYPE F, H) .............................•.•...••.••....•.....•..•................. 500 mW
For To = +100 to +125°C (PACKAGE TYPE F, H) ......................................... Derate Linearly at 8 mW/oC to 300 mW
For To = -40 to +70°C (PACKAGE TYPE M) .......................................................................... 400 mW
For To = +70 to +125°C (PACKAGE TYPE M) ....••.•.•••.•..•...•...•..•.....•........... Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (To):
PACKAGE TYPE F, H .......•.•••.••...••..••....•••....•...••....•....•...••••..•••••.•.•...•••....•.......... -55 to +125°C
PACKAGE TYPE E, M •.................................................................................•..••..• -40 to +85°C
STORAGE TEMPERATURE (T...) ................................................................................. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case"for 10 s max.............••.••.....••............................ +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ....................................................................•............. +300°C
7
(A
< B)oul
4
(A>B)ln
3
(A= B)in
2
(A< B)ln
Fig. 1 - Logic diagram
120 ______________________________________________________________
___
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC85
CD54/74HCT85
TRUTH TABLE
Comparing Inputs
A3,B3
A2, B2
A3>83
A3<83
A3 = 83
A3 = 83
A3 = 83
A3 = 83
A3= 83
A3= 83
A3= 83
A3= 83
A3= 83
A3= 83
A3= 83
A3= 83
X
X
A2>82
A2<82
A2= 82
A2=82
A2=82
A2 =82
A2 =82
A2= 82
A2= 82
A2= 82
A2=82
A2 =82
A1, B1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
Cascading Inputs
AO, BO
X
X
X
X
X
X
X
X
X
>81
X
<81
= 81 AO>80
= 81 AO<80
=81 AO=80
= 81 AO=80
= 81 AO=80
= 81 AO=80
= 81 AO=80
= 81 AO=80
Outputs
A>B
AB
AB) in, (AB)out, (AB)in,(AB)out,(AB)out, t PHL
(AB)in, (AB)out, (A 8)out
Ne
(AB)ln
IA= Hlin
(A< Blln
A'
.3
:~
B'
A'
BO
AD
(A> Blln
AD -AD
-At.
A2 - A 2
LEASTSIGNIFICANT
4·BITS
OF EACH WORD
B.
A.
~
rrr-
B.
B.
-
A4
IA> alin
(A=Blln
IA Slout
AD
(A< Bli"
GND
A2
(A= Blin
(A> Blln
(A> Blin
••
AD
B.
A3
B. He/HeTBS
A2
B' (A < 8)out
A' (A= Slout
BO (A> Slaut
OUTPUTS
(A= Blin
HCT85
'---(A>B)out
(A=B)out
(AB)ln
(A=Blln
(AB)oul
GND{
I-
81 (A>Blout
B2(A=B)out t--} OUTPUTS
83 (A 8)ln
92CL- 39837
92CM-39836
Fig. 3 - Series cascading --- comparing 12-bit words.
Fig. 4 - Parallel cascading --- comparing 12-bit words.
124 ______________________________________________________________
- - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
File Number
1644
CD 54/74HC86
CD54/74HCT86
High-Speed CMOS Logic
Quad 2 - Input EXCLUSIVE - OR Gate
Type Features:
•
•
Four independent EXCLUSIVE - OR gates
Buffered inputs and outputs
Applications:
FUNCTIONAL DIAGRAM AND
TERMINAL ASSIGNMENT
•
•
•
Logical comparators
Parity generators and checkers
Adders/Subtracters
The RCA CD54/74HC86 and CD54/74HCT86 contain four
independent EXCLUSIVE-OR gates in one package. They
provide the system designer with a means for
implementation of the EXCLUSIVE-OR function.
The CD54HC/HCT86 are supplied in 14-lead cermelic dualin-line packages (F suffix). The CD74HC/HCTB6 are supplied in 14-lead plastic dual-in-line packages (E suffix) and
in 14-lead dual-in-line surface mount plastic packages (M
suffix). Both types are also available in chip form (H
suffix).
Family Features:
•
•
•
•
•
•
•
nA
nY
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85 0 C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to
LSTTL Logic ICs
Alternate Source is Philips/Signetics
CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity: ML =30%, N'H =30% of Vce
@ Vee = 5 V
CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L =0.8 V Max., V,H =2 V Min.
CMOS Input Compatibility
I, :S 1 JiA @ VOL, VOH
nB~
TRUTH TABLE
92CS-38429
OUTPUT
INPUTS
Fig. 1 - Logic diagram each gate.
nA
nB
nY
L
L
L
L
H
H
H
L
H
H
H
L
H = HIGH voltage level.
L = LOW voltage level.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 125
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC86
CD54/74HCT86
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ...................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ....................................................... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) ................................................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) .................................................... ±25 mA
DC Vee OR GROUND CURRENT (Ice): ..................................................................................... ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For T.; -40 to +60'C (PACKAGE TYPE E) ............................................................................... 500 mW
For T.; +60 to +85'C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/'C to 300 mW
ForT.; -55 to +loo'C (PACKAGE TYPE F, H) .......................................................................... 500 mW
For T. ; +100 to +125' C (PACKAGE TYPE F, H) ............................................. Derate Linearly at 8 mW/'C to 300 mW
For T.; -40 to +70'C (PACKAGE TYPE M) ............................................................................. 400 mW
For T.; +70 to +125'C (PACKAGE TYPE M) ............................................... Derate Linearly at 6 mW/'C to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H ............................................................................................. -55 to +125'C
PACKAGE TYPE E, M ...............................................................................................-40 to +85'C
STORAGE TEMPERATURE (T".) .................................................................................... -65 to +150'C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mOl) from case for 10 s max ........................................................ +265'C
Unit inserted into a PC Board (min. thickness 1/16 in .. 1.59 mm)
with solder contacting lead tips only. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . . . . . . . . . .. .. .
+300' C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within the
following ranges:
LIMITS
UNITS
CHARACTERISTIC
MIN.
MAX.
Supply-Voltage Range (For TA ; Full Package-Temperature Range) Vcc:"
2
6
V
4.5
5.5
V
0
Vcc
V
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
'C
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage V" Va
Operating Temperature TA:
I nput Rise and Fall Times, t" tf
at 2 V
0
1000
ns
at 4.5 V
0
500
ns
at 6 V
0
400
ns
'Unless otherwise specified, all voltages are referenced to Ground.
126 _______________________________________________________________
_______________________________ Technical Data
CD54/74HC86
CD54/74HCT86
STATIC ELECTRICAL CHARACTERISTICS
CD74HC88/CD54HC86
CD74HCT86/CD54HCT66
TEST
74HC/54HC
74HC
54HC
TEST
74HCTI54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
CHARACTERISTICS
UNITS
+25 D C
V,
10
Vee
V
rnA
V
High-Level
Input Voltage
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
Va"
CMOS Loads
or
-0.02
V,"
~yp Max Min Max Min Max
1.5
-
-
1.5
-
1.5
-
4.5 P.15
-
-
P.15
-
3.15
-
4.2
-
4.2
-
0.5
-
2
V,"
Min
6
4.2
-
2
-
-
0.5
4.5
-
-
1.35 -
-
6
-
-
1.8
Low-Level
Output Voltage
1.8
CMOS Loads
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
10
-
-
2
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.96
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
~0.1
-
±1
-
±1
pA
5.5
-
-
-
100 360
10
V"
V"
3.98
-
-
3.64
-
3.7
-
or
V,"
-5.2
6
5.46
-
5.34
-
5.2
-
V,"
2
-
-
0.1
-
0.1
-
0.1
V"
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
V"
I nput Leakage
Current
2
10
5.5
4.5
V,"
TTL Loads
-
-4
or
Min Typ. Max Min Max Min Max
4.5
0.5
or
V"
Va'
V
5.5
-
1.8
V
4.5
1.35
-
Vee
-
1.35 -
V"
TTL Loads
+25°C
V,
V"
or
4
4.5
-
-
0.26
-
0.33
-
0.4
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
Any
Voltage
Vee
or
6
-
-
0.1
-
±1
-
±1
Between
Vee and
Gnd
Gnd
Quiescent Device
Current
Icc
Vee
or
Vee
0
6
-
-
2
Gnd
-
20
-
40
or
2
-
20
-
40
pA
-
450
-
490
pA
Gnd
Additional
4.5
Quiescent Device
Current per
Vee -2.1
1 Unit Load
to
5.5
Input Pin:
6.lcc
*For dual-supply systems theoretical worst case (VI
=2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT INPUT LOADING TABLE
INPUT
UNIT LOADS·
All Inputs
• Unit load is .:llee limit specified in Static Characteristic
Chart, e.g., 360/lA max. @ 25°C.
___________________________________________________________________ 127
TechnicaIOala _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC86
CD 54/74HCT86
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25° C, Input t" tl = 6 ns)
TYPICAL VALUES
CHARACTERISTIC
UNITS
SYMBOL
Cl
pF
Propagation Delay, Any Input
54/74HC
54174HCT
9
13
ns
22
27
pF
-40°C 10 +85°C
-55°C 10 +125°C
t pLH
15
tPHl
-
Power Dissipation Capacitance'
Cpo
, Cpo is used to determine the dynamic power consumption, per gate.
Po = Vec2 f, (Cpo + Cel where:
f, = input frequency.
Cl = output load capacitance.
Vee = supply voltage.
SWITCHING CHARACTERISTICS (Cl = 50 pF, Inpul I" tl = 6 ns)
25°C
CHARACTERISTIC
SYMBOL
HCT
HC
Vee
74HC
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay,
tPlH
2
120
-
150
-
180
-
nA, nB to nY
tPHl
4.5
24
32
30
40
36
48
6
20
-
26
-
31
-
Output Transition
Time
Input Capacitance
ITlH
2
tTHl
4.5
6
-
CI
-
95
-
110
-
15
15
19
19
22
22
13
-
16
-
19
-
75
10
-
10
-
10
-
10
-
10
-
10
ns
ns
pF
92CS-38430R2
Input Level
Switching Voltage, Vs
54/74HC
54/74HCT
Vee
3V
50% Vee
1.3 V
Fig. 2 - Transition times and propagation delay times.
128 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
File Number
CD54/74HC93
CD54/74HCT93
1849
High-Speed CMOS Logic
4-Bit Binary Ripple Counter
Type Features:
• Can be configured to divide by 2,8, and 16
• Asynchronous Master Reset
02
m-'---.q
03
92C5-40378
FUNCTIONAL DIAGRAM
The RCA-CD54174HC93 and the CD54174HCT93 are highspeed silicon-gate CMOS devices and are pin-compatible
with low power Schottky TTL (LSTTL). These 4-bit binary
ripple counters consist of four master-slave flip-flops
internally connected to provide a divide-by-two section and
a divide-by-eight section. Each section has a separate clock
input (CPO and CP1) to initiate state changes of the counter
on the HIGH-to-LOW clock transition. State changes of the
On outputs do not occur simultaneously because of internal
ri pple delays. Therefore, decoded output sig nals are subject
to decoding spikes and should not be used for clocks or
strobes.
A gated AND asynchronous master reset (MR1 and MR2) is
provided which overrides both clocks and resets (clears) all
flip-flops.
Because the output from the divide-by-two section is not
internally connected to the succeeding stages, the device
may be operated in various counting modes.
In a 4-bit ripple counter the output 00 must be connected
externally to input CP1. The input count pulses are applied
to clock input (;PO. Simultaneous frequency divisions of 2,
4,8, and 16 are performed at the 00,01,02, and 03 outputs
as shown in the function table. As a 3-bit ripple counter the
input count pulses are applied to input CP1.
Simultaneous frequency divisions of 2, 4, and 8 are available
at the 01, 02, and 03 outputs. Independent use of the fi rst
flip-flop is available if the reset function coincides with the
reset of the 3-bit ripple-through counter.
The CD54HC93 and CD54HCT93 are supplied in 14-lead
hermetic dual-in-line frit-seal ceramic packages (F suffix).
The CD74HC93 and CD74HCT93 are supplied in 14-lead
dual-in-line plastic packages (E suffix) and in 14-lead dualin-line surface-mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
Family Features:
.. Fanout (over temperature range):
Standard outputs - 10 LSTTL loads
Bus driver outputs - 15 LSTTL loads
• Wide operating temperature range:
CD74HC/HCT: -40 to +85°C
II Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL
logic ICs
.. Alternate source is Philips/Signetics
.. CD54HC/CD74HC types:
2 to 6 V operation
High noise immunity:
ML=30%, MH=30% of Vee: @ Vee=5 V
II CD54HCT/CD74HCT types:
4.5 to 5.5 V operation
Direct LSTTL input logic compatibility
V'L=0.8 V max., V'H=2 V min.
CMOS input compatibility
1,~1 pA @ VOL, VOH
CP1
14
MRI
13
NC
MR2
12
00
CPO
NC
11
03
VCC
10
GND
NC
01
NC
02
TOPVIEW
92C5-40389
TERMINAL ASSIGNMENT
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 129
Technical Data ___________________________________________________________
CD54/74HC93
CD54/74HCT93
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) .......................................................•........................... , .. -0.5 to +7 V
DC INPUT DIODE CURRENT, h. (FOR Vi < -0.5 V OR Vi > Vee +0.5 V) ...................................................•... ±20 mA
DC OUTPUT DIODE CURRENT, 10. (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) ..............................•.................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) ......................... '" ......................... ±25 mA
DC Vee OR GROUND CURRENT (lee) .........................................................•...................... , '" .. ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For T A = -40 to +60° C (PACKAGE TYPE E) .................................•.................. , .......................... 500 mW
For TA = +60 to +85° C (PACKAGE TYPE E) ................. , ................................ Derate Linearly at 8 mW/o C to 300 mW
For TA= -55 to +100°C (PACKAGE TYPE F,H) ............................................................................ 500 mW
For TA = +100 to +125° C (PACKAGE TYPE F,H) .............................................. Derate Linearly at 8 mW/o C to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) .............................................................................. 400 mW
For TA = +70 to +125°C (PACKAGE TYPE M) ................................................. Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F,H ............................................................................................. -55 to +125° C
PACKAGE TYPE E,M .............................................................................................. -40 to +85° C
STORAGE TEMPERATURE (Tot,) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................................................................................... +300° C
FUNCTION TABLE
(aO connected to CP1)
CPO
F/f2
o
F/F3
COUNT
o
j;R
0
1
2
3
4
5
6
7
8
MR2
9
Q3
01
10
11
12
13
14
15
03
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
MODE SELECTION
92C M- 4038B
Fig. 1 - HCIHCT93 logic diagram.
OUTPUTS
01
02
L
L
L
L
H
L
H
L
L
H
L
H
H
H
H
H
L
L
L
L
H
L
H
L
L
H
L
H
H
H
H
H
00
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
RESET INPUTS
MRl
MR2
H
L
H
L
OUTPUTS
01
02
00
H
H
L
L
L
I
L
I
L
03
I
L
count
count
count
H = HIGH voltage level
L = LOW voltage level
4>~~
FFoa FF1
FF26FF3
'-----------------+-°9"M-40386
Fig. 2 - Flip-flop (0-3) lorjic detail.
130 ___________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TechnicaJ Data
CD54/74HC93
CD54/74HCT93
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT93/CD54HCT93
CD74HC93/CD54HC93
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85°C
+125"C
+B5°C
+l25"C
UNITS
CHARACTERISTIC
+25"C
V,
10
Vee
V
mA
V
V"
High-Level
Output Voltage
2
-
4.5
-
6
-
-
1.8
-
1.8
VOH
1.9
-
1.9
4.4
-
4.4
5.9
-
5.9
1.5
4.5 3.15
V,H
Low·Level
Input Vollage
Min Typ Max Min Max Min Max
-
2
High-Level
Inpul Vollage
V"
or
-0.02
6
4.2
-
1.5
-
1.5
3.15
-
3.15
4.2
-
4.2
0.5
-
0.5
-
0.5
1.35
-
1.35
-
1.35
-
1.9
-
4.4
6
5.9
-
-
-
-
3.84
-
3.7
5.34
-
5.2
0.1
-
0.1
TTL Loads
V"
or
-4
V,H
-5.2
6
V"
or
2
-
-
0.1
0.02
4.5
-
0.1
6
-
0.1
-
VOL
4.5 3.98
5.48
0.1
0.1
CMOS Loads
V,H
TTL Loads
V"
or
4
4.5
-
-
0.26
-
0.33
V,H
5.2
6
-
-
0.26
-
0.33
-
6
-
-
±0.1
-
±1
-
-
V
10
2
-
-
2
-
2
-
V
-
-
O.B
-
0.8
-
0.8
V
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
3.7
-
V
5.5
4.5
-
to
5.5
V"
or
4.5
V,H
V"
or
4.5 3.98
V,H
0.1
V,H
0.4
V"
or
0.4
V,H
±1
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
,.,A
5.5
-
-
8
-
80
-
160
,.,A
-
100 360
-
450
-
490
,.,A
Any
I,
Quiescent
Vee
or
Icc
or
Voltage
Between
Vee & Gnd
Vee
Vee
0
6
-
-
8
-
80
-
160
or
Gnd
Gnd
Additional
4.5
Quiescent Device
Vee -2.1
Current per input
pin: 1 unit load
Min Typ Max Min Max Min Max
4.5
-
V"
or
Gnd
Device Current
Vee
V
0.1
Input Leakage
Current
V,
1.8
2
V,H
Low-Level
-
4.5
CMOS Loads
Output Vollage
+25"C
to
5.5
b.lcc
·For dual-supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT INPUT LOADING TABLE
INPUT
CPO, CP1
UNIT LOADS'
0.6
MR1, MR2
0.4
·Unit Load is ~Icc limit specified in Static Characteristics
Chart, e.g. 360 pA max. @ 25 0 C.
___________________________________________________ 131
Technical Data ___________________________________________________________
CD54n4HC93
CD54n4HCT93
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA-Full Package Temperature Range)
Vee:'
CD54J74HC Types
CD54J74HCT Types
DC Input or Output Voltage, V" Vo
Operating Temperature, TA:
CD74 Types
CD54 Types
Input Rise and Fall Times, t"t,:
at2 V
at 4.5 V
at6V
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
V
V
'Unless otherwise specified, all voltages are referenced to Ground.
SWITCHING CHARACTERISTICS (Vee=5 V, TA=25°C, Inputt"t,=6 ns)
TYPICAL VALUES
HC
HCT
CL (pF)
CHARACTERISTIC
Propagation Delay:
CPO to 00 Output
tPLH
tPHL
15
CP1 to 03
MRn to an Output
Power Dissipation Capacitance'
Cpo
-
10
14
21
24
13
13
25
25
UNITS
ns
pF
'Cpo is used to determine the dynamic power consumption, per counter.
Po = Cpo Vee2 fi + I CL Vee 2 fo where f, = input frequency
fo = output frequency
CL = output load capacitance
Vee = supply voltage.
PRE-REQUISITE FOR SWITCHING FUNCTION
CHARACTERISTIC
Maximum Clock
Frequency
fMAX
Clock Pulse Width
CPO, CP1
tw
Reset Pulse Width
tw
Reset Removal Time tREM
TEST
CONDITIONS
Vee (V)
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
LIMITS
_40° C to +85° C
-55°C to +125°C
74HCT
54HC
54HCT UNITS
HCT
74HC
HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
4
5
6
MHz
24
24
20
20
30
30
24
35
28
120
100 80
24
24
16
16
20
20
14
17
20
120
80
100 16
24
24
ns
16
20
20
14
20
17
75
50
65
10
10
13
13
15
15
11
13
9
25°C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
132 _________________________________________________________________
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - Technical Data
CD54/74HC93
CD54/74HCT93
INPUT
INPUT
INPUT
----.J/
_00
INPUT LEVEL
INPUT LEVEL
SWITCHING VOLTAGE, Vs
SWITCHING VOLTAGE, Vs
92CS-38370R2
92CS-38371R2
Fig. 4 - Master-Reset pre-requisite and propagation-delay times.
Fig. 3 - Pre-requisite, propagation-delay, and output-transition
times.
SWITCHING CHARACTERISTICS (CL=50 pF, Inpul 1,,1,=6 ns)
LIMITS
_40° C 10 +85° C
-55° C 10 +125° C
UNITS
74HCT
54HC
54HCT
HC
HCT
74HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
25°C
CHARACTERISTIC
Propagation Delay
Time:
CPO to 00
VCC
tPLH
tPHL
CPl to 01
CPl to 02
CP1to 03
MR1, MR2 to On
Output Transition
Time
Input Capacitance
hHL
hLH
C,
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-
-
-
-
-
-
-
125
25
21
135
27
23
185
37
31
245
49
42
155
31
26
75
15
13
10
-
-
34
-
-
-
-
-
34
-
-
-
-
-
-
-
46
-
-
-
-
-
58
-
-
-
-
-
-
-
33
15
10
-
-
-
155
31
26
170
34
29
230
46
39
305
61
52
195
39
33
95
19
16
10
43
-
-
-
-
-
-
43
58
-
-
-
-
-
-
73
41
-
-
-
-
19
-
-
-
-
-
10
-
-
-
-
-
-
-
-
-
-
-
-
190
38
32
205
41
35
280
56
48
370
74
63
235
47
40
110
22
19
10
-
-
-
-
51
51
-
-
-
-
69
-
-
-
87
50
-
-
-
-
ns
-
22
10
pF
____________________________________________________________________ 133
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC107
CD54/74HCT107
File Number
1722
High-Speed CMOS logic
'0
1CP
12
1Fi
13
Type Features:
20
•
20
•
•
•
•
FF2
2R
10
Dual J-K Flip-Flop with Reset
. Negative-Edge Trigger
Vee =14
Hysteresis on clock inputs for improved noise immunity and increased
input Rise and Fall times.
Asynchronous Reset
Complementary Outputs
Buffered Inputs
Typical fma. = 60 MHz @ Vee = 5V, C L = 15 pF, TA = 25°C
FUNCTIONAL DIAGRAM
The RCA-CD54174HC107 and CD54174HCT107 utilize
silicon-gate CMOS technology to achieve operating speeds
equivalent to LSTTL parts. They exhibit the low power
consumption of standard CMOS integrated circuits,
together with the ability to drive 10 LSTTL loads.
These flip-flops have independent J, K, Reset and Clock
inputs and Q and Q outputs. They change state on the
negative-going transition of the clock pulse. Reset is
accomplished asynchronously by a low-level input.
This device is functionally identical to the HC/HCT73 but
differs in terminal assignment and in some parametric
limits.
The 54HCT174HCT logic family is functionally as well as
pin-compatible with the standard 54LS174LS logic family.
The CD54HC1 07 and CD54HCT1 07 are supplied in 14-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC107 and CD74HCT107 are supplied in 14-lead
dual-in-line plastic packages (E suffix) and in 14-lead dualin-line surface-mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
Family Features:
•
•
•
•
•
•
•
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85 0 C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to
LSTTL Logic ICs
Alternate Source is Philips/Signetics
CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity:
N'L = 30%, N'H = 30% of Vee: @ Vee = 5 V
CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, :S 1 IlA @ VOL, V OH
TRUTH TABLE
(EACH FLIP-FLOP)
INPUTS
CP
J
K
Q
L
X
X
X
L
'-
L
L
H
Fig. 1 - Logic diagram.
OUTPUTS
-R
Q
H
No Change
H
\.-
H
L
H
L
H
H
L
H
H
''-
L
H
H
Toggle
H
H
X
X
No Change
H = High Level (Steady State)
L = Low Level (Steady State)
X = Irrelevant
= High-to-Low
transition
~
134 __________________________________________________________
- - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC107
CD54/74HCT107
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ...................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, 10K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ....................................................... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) ................................................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) .................................................... ±25 mA
DC Vee OR GROUND CURRENT, (Icc): ..................................................................................... ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60° C (PACKAGE TYPE E) ............................................................................... 500 mW
For T. = +60 to +85°C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/o C to 300 mW
ForT. = -55 to +100°C (PACKAGE TYPE F, H) ........................................................................... 500 mW
For T. = +100 to +125° C (PACKAGE TYPE F, H) ............................................. Derate Linearly at 8 mW/o C to 300 mW
For T. -40 to +70°C (PACKAGE TYPE M) ............................................................................. 400 mW
For T. +70 to +125°C (PACKAGE TYPE M) ................................................ Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H ............................................................................................. -55 to +125° C
PACKAGE TYPE E, M ...............................................................................................-40 to +85°C
STORAGE TEMPERATURE (Tot.) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for lOs max ........................................................ +265° C
Unit inserted into a PC Board (min. thickness 1116 in., 1.59 mm)
with solder contacting lead tips only ..................................................................................... +300°C
CL
=
=
Q
92CM-39231
K
Fig. 2 - Flip-Flop detail.
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within the
following ranges:
LIMITS
UNITS
CHARACTERISTIC
MIN.
MAX.
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vee: •
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V,. Vo
2
6
V
4.5
5.5
V
0
Vee
V
Operating Temperature T A :
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
at 2 V
0
1000
ns
at 4.5 V
0
500
ns
at 6 V
0
400
ns
Input Rise and Fall Times, t" tf •
.
..
Unless otherwise specified, all voltages are referenced to Ground .
• Applicable for all inputs except clock.
__________________________________________________________ 135
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC107
CD54/74HCT107
STATIC ELECTRICAL CHARACTERISTICS
CD74HC107, CD54HC107
CD74Hcn07, CD54Hcn07
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125° C
UNITS
CHARACTERISTIC
+25°C
10
Vee
V,
Vee
V
rnA
V
V
V
High-Level
Input Voltage
V,"
Low-Level
Input Voltage
V"
High-Level
V"
Output Voltage
Vo"
CMOS Loads
+25°C
V,
or
-0.02
V,"
Min Typ Max Min Max Min Max
2
1.5
-
-
1.5
-
1.5
-
4.5
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
Low-Level
Voc
CMOS Loads
-
-
4.5
4.4
4.5
3.98
-
V
0.8
V
4.4
-
V
-
3.7
-
V
2
-
0.8
-
0.8
-
-
4.4
-
-
-
3.84
-
2
to
-
5.5
2
1.9
-
-
1.9
-
1.9
-
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
V"
V"
4.5
3.98
-
-
3.84
-
3.7
-
or
V,"
-5.2
6
5.48
-
-
5.34
-
5.2
-
V,"
2
-
-
0.1
-
0.1
V"
4.5
-
-
0.1
-
0.1
-
0.1
0.02
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
V,"
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
+0.1
-
±1
-
±1
/J A
5.5
-
-
4
-
40
-
80
/J A
-
100 360
-
450
-
490
/J A
V"
V"
TTL Loads
-
4.5
-
-4
or
2
to
5.5
or
V"
Output Voltage
4.5
-
4.5
V"
TTL Loads
Min Typ Max Min Max Min Max
or
4
4.5
-
-
0.26
-
0.33
-
0.4
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
6
-
-
0.1
-
±1
-
±1
Any
Input Leakage
I,
Current
Vee
or
Gnd
Quiescent
Icc
or
Between
Vee & Gnd
Vee
Vee
Device Current
Voltage
0
6
-
-
4
-
40
-
80
or
Gnd
Gnd
Additional
4.5
Quiescent Device
Vee -2.1
Current per input
to
5.5
pin: 1 unitload
.6.lcc· •
• For dual-supply systems theoretical worst case (VI::: 2.4 V, Vee::: 5.5 V) specification is 1.8 rnA.
14
1J
-
10
HCT Input Loading Table
Input
All
Unit Loads'
0.3
13
Vee
1R
10
"
ice
1K
"
2K
20
20
• Unit Load is fl.lcc limit specified in Static Characteristic
Chart, e.g., 360 flA max. @ 25° C.
2
GND
10
2R
2CP
2J
TERMINAL ASSIGNMENT
136 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC107
CD54/74HCT107
SWITCHING CHARACTERISTICS (Vee=5 V, T A=25°C, Inpul I" 1,=6 ns)
TYPICAL
CL
CHARACTERISTIC
(pF)
HC
HCT
UNITS
15
tPLH
tPHL
Propi!llation Delay
CPto Q
14
18
ns
CPto Q
14
17
ns
RtoQ,Q
13
16
ns
CP Frequency
fmax
15
60
56
MHz
Power Dissipation Capacitance"
Cpo
-
31
30
pF
" Cpo is used to determine the dynamic power consumption, per flip-flop.
Po = CpoVee2 f;+ 1: CL Ve e2 fo
where f; =input frequency, fo =output frequency,
CL =output load capacitance, Vee =supply voltage.
PRE-REQUISITE FOR SWITCHING FUNCTION
LIMITS
CHARACTERISTIC
TEST
CONDITION
Pulse Width
tw
CP
Set-up Time
tsu
J, K to CP
Hold Time
tH
J, K to CP
Removal Time
CP Frequency
tram
fmax
74HC
74HCT
54HC
54HCT
Min Max Min Max Min Max Min Max Min Max Min Max
-
16
6
14
2
80
4.5
16
6
14
2
100
4.5
20
6
17
-
2
3
4.5
R
HCT
80
2
_55 0 C 10 +125° C
UNITS
HC
Vee
V
_40° C to +85 0 C
25°C
100
-
-
-
120
-
-
20
-
23
-
24
-
27
-
17
-
-
-
20
-
-
-
-
100
-
-
-
120
-
-
-
20
-
30
-
24
-
36
-
17
-
-
20
-
-
150
-
-
25
-
30
-
30
-
21
-
-
-
26
-
-
3
-
-
3
-
-
3
-
5
3
-
-
-
-
-
-
18
-
-
24
-
-
-
-
-
125
20
-
25
-
-
-
-
-
-
ns
-
4.5
3
-
-
3
-
5
6
3
-
-
-
3
-
2
60
-
-
-
75
-
-
90
-
-
-
4.5
12
12
-
15
-
-
15
-
18
-
18
6
10
-
13
-
-
15
-
-
-
5
ns
2
6
-
-
-
5
-
-
4
-
-
4.5
30
-
28
-
25
-
22
-
20
-
19
-
6
35
-
-
-
29
-
-
-
23
-
-
-
ns
ns
ns
MHz
_____________________________________________________________ 137
Technical Data ___________________________________________________________
CD54/74HC107
CD54/74HCT107
SWITCHING CHARACTERISTICS (CL
= 50 pF,
Input t" If
= 6 ns)
LIMITS
TEST
CONDITION
CHARACTERISTIC
Propagation
Delay
CPto
Output
Transition
Input
54HCT
Min Max Min Max Min Max Min Max Min Max Min Max
-
-
-
215
-
-
-
255
-
43
-
43
-
54
-
51
29
-
-
37
-
-
-
43
2
170
-
-
215
-
-
-
255
4.5
-
34
-
40
-
43
-
50
-
51
-
6
-
29
-
-
37
-
-
-
43
-
2
-
155
4.5
31
6
6
-
26
-
hLH
2
-
75
-
-
hHl
4.5
-
15
-
15
6
-
13
-
-
-
-
10
-
10
-
Time
54HC
34
4.5
-RtoO,Q
74HCT
170
2
tPHL
CPtoQ
74HC
HCT
-
tPLH
a
-55° C 10 +125° C
UNITS
HC
Vee
V
_40° C to +85° C
25°C
C,
Capacitance
65
ns
-
60
ns
-
-
-
195
-
-
-
235
-
-
38
-
39
-
48
-
47
-
57
-
-
33
-
-
-
40
-
-
95
-
-
-
110
19
-
19
-
22
22
16
-
-
-
19
-
10
-
10
-
10
-
10
ns
ns
pF
INPUT
LEVEL
-GND
Q
~'NPUT
92CS- 39232
---------~
Vs
LEVEL
GND
92CS-39233
IN PUT
- - - , , - - - - , , - - - LE VEL
J OR K
"----GND
'SU
EP-----""\
INPUT
LEVEL
92CS -392 34
Input Level
Switching Voltage, V,
54/74HC
54/74HCT
Vee
3V
50% Vee
1.3 V
Fig. 3 - Transition times, propagation delay times, and setup and hold times.
138 ____________________________________________________________________
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - T e c h n i c a l Data
File Number
1667
CD54/74HC109
CD54/74HCT109
High-Speed CMOS logic
Dual J-K Flip-Flop with
Set and Reset
lS
lJ
10
lK
lCP
10
iR
Type Features:
vcc =
GND
16
= 8
92CS- 38532
• Positive-Edge triggered
• Asynchronous Set and Reset
• 60 MHz Typical Maximum Clock Frequency
@ Vee =5 V, C L = 15pF, TA = 25°C
• Typical Propagation Delay = 18 ns @ Vee = 5V, C L
• Schmitt Trigger Clock Inputs
= 15pF,
TA
= 25° C
FUNCTIONAL DIAGRAM
Family Features:
The RCA-CD54174HC109 and CD54/74HCT109 are dual
J-K flip-flops with set and reset. The flip-flop changes state
with the positive transition of Clock (lCP and 2CP).
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
• Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HCIHCT: -40 to + 85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noice Immunity: ML =30%, NIH =30% of Vee
@ Vee =5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
VIL = 0.8 V Max., V/H = 2 V Min.
CMOS Input Compatibility
I, .,,; 1 uA@ VOL VOH
The flip-flop is set and reset by active-low Sand R,
respectively. A Iowan both the set a!!d reset inputs
simultaneously will force both Q and Q outputs high.
However, both set and reset going high simultaneously
results in an unpredictable output condition.
The CD54HC109 and CD54HCT109 are supplied in l6-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC109 and CD74HCT109 are supplied in l6-lead
dual-in-line plastic packages (E suffix) and in 16-lead dualin-line surface mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
TRUTH TABLE
6(10)
J 5
FF
A
CP
16
vccO
0
0
a
7(9)
Outputs
Inputs
a
S
R
CP
J
K
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
L
H
L
H
X
X
X
X
L
L
H
H
X
-:::;:::.
~
L
Q
Q
H
L
L
H
W
W
H
L
TOGGLE
NO CHANGE
H
L
NO CHANGE
B
GNDO
'Unpredictable and unstable condition if both Sand
simultaneously.
if go
high
Fig. 1 - Logic diagram
_______________________________________________________________________ 139
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC109
CD54/74HCT109
a
s
92CM- 38536
DETAIL OF FLlp·FLOP
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY·VOL TAGE, (Vee):
(Voltages referenced to ground) ...... .
. ..... -0.5 to + 7 V
DC INPUT DIODE CURRENT, 11K (FOR V, <-0.5 V OR V, >Vee +0.5V)
.... :,:20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 OR Vo > Vee +0.5 V) .... .
±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) ... .
:': 25 mA
DC Vee OR GROUND CURRENT (Icc):
:,:50 mA
POWER DISSIPATION PER PACKAGE (Po):
............
500 mW
For TA = -40 to +60°C (PACKAGE TYPE E) ....
Derate Linearly at 8 mwrc to 300 mW
For TA = +60 to +85°C (PACKAGE TYPE E) ..
....................... 500 mW
For TA = -55 to +100°C (PACKAGE TYPE F, H)
Derate Linearly at 8 mW/oC to 300 mW
For TA = +100 to +125°C (PACKAGE TYPE F, H) ..
For T. = -40 to +70°C (PACKAGE TYPE M) .......................................................................... 400 mW
For TA = +70 to +125°C (PACKAGE TYPE M) ..... , ............. , ...................... , .. Derate Linearly at 6 mW/oC to 70 mW
OPERATING -TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H ........... .
.. ·55 to +125°C
PACKAGE TYPE E, M ................. ..
.. .. ·40 to+85°C
STORAGE TEMPERATURE (T"g) ........ .
-65 +150°C
LEAD TEMPERATUARE (DURING SOLDERING)
At distance 1/16 ± 1/32 in. (1.59:': 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only
............... .
+300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within the following
ranges:
LIMITS
CHARACTERISTIC
MIN.
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vee:'
CD54174HC Types
CD54174HCT Types
6
5.5
V
0
Vee
V
-40
-55
+85
+125
°C
at 2V
at 4.5 V
at 6V
0
0
0
1000
500
400
ns
at 2 V
at 4.5 V
at6 V
0
0
0
unlimited
us
DC Input or Output Voltage V, Vo
Input Rise and Fall Times tr, If
For CP
UNITS
2
4.5
Operating Temperature TA:
CD74 Types
CD54 Types
Input rise and Fall Times t, tf
All inputs Except CP
MAX.
'Unless otherwise specified, all voltages are referenced to Ground.
140 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC109
CD54/74HCT109
STATIC ELECTRICAL CHARACTERISTICS
CD74HC109 /
CD54HC109
CD74HCT109 /
CD54HCT109
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
, 85"C
, 125"C
+ 85°C
+ 125°C
UNITS
CHARACTERISTIC
VI
10
Vee
V
mA
V
• 25"C
VI
Vee
V
V
Min Typ Ma. Min Max Min Ma.
Min Typ Max Min Ma. Min Ma.
High-Level
Input Voltage
V,H
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
-
1.5
4.5 3.15
-
-
6
4.2
-
-
2
VIL
VOH
CMOS Loads
or
-0.02
V'H
1.5
-
1.5
-
3.15
-
3.15
-
to
4.2
-
4.2
-
5.5
4.5
Low-Level
Output Voltage
2
-
-
0.5
-
0.5
-
0.5
-
-
1.35
-
1.35
-
1.35
to
6
-
-
1.8
-
1.8
5.5
2
1.9
-
1.8
-
1.9
-
-
4.4
4.4
-
VIL
4.4
-
1.9
4.5
6
5.9
-
-
5.9
-
5.9
-
V,H
4.5 3.96
-
-
3.84
-
3.7
-
or
-4
VIH
-5.2
or
0.02
V,H
CMOS Loads
6
5.48
-
-
5.34
-
5.2
-
V,H
2
-
-
0.1
-
0.1
-
0.1
Vil
4.5
-
-
0.1
-
0.1
--
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,H
Vil
TTL Loads
Input Leakage
II
Current
2
-
V
-
-
O.B
-
0.8
-
0.8
V
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
3.7
-
V
4.5 3.98
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
Any
Voltage
Between
5.5
Vee
&
Gnd
-
-
;to.l
-
11
-
!1
VIL
-
0.26
-
0.33
-
0.4
or
VIH
5.2
6
-
-
0.26
-
0.33
-
0.4
V,H
or
6
-
-
:!;O.l
-
11
-
11
JJA
Vee
a
6
-
-
4
-
40
-
80
or
5.5
-
-
-
100 360
4
-
40
-
BO
J'A
-
450
-
490
IJA
Gnd
Gnd
4.5
Additional quiescent
Device Current
-
0.1
-
or
Icc
2
-
4.5
Vee
Device
-
-
4
Gnd
Quiescent
-
4.5
or
Vee
Current
4.5
or
2
Vil
or
Vil
VOL
4.5
4.5
VIL
TTL Loads
• 25"C
.6.lcc
Vcc-2.1
per input pin:
1 unit load
to
5.5
'For dual-supply systemslheorelleal worsl case (V, = 2.4 V, Vee = 5.5 V) speelflcallon is 1.8 mAo
HCT Input Loading Table
Input
Unit Loads'
All
0.3
'Unit Load iSAlee limit specified in Static Characteristics Chart, e.g., 360 IJA max.@25°C
________________________________________________________________ 141
Technical Data _________________________________________________________
CD54/74HC109
CD 54/74HCT109
SWITCHING CHARACTERISTICS (Vee
=5 V. TA. =25°C. Inpul 1..1, =6 nl)
Typical
CL
(pF)
CHARACTERISTIC
Propagation Delay.
54174HC
tPLH
UNITS
54174HCT
tPHL
15
14
17
ns
S~Q
tPLH
15
9
12
ns
S~Q
tPHL
15
13
19
ns
R~Q
tPHL
15
15
19
ns
tPLH
15
14
15
ns
15
60
54
MHz
-
30
33
pF
CP~Q,Q
R~Q
CP Frequency
fMAX
Cpo·
Power Dissipation Capacitance-
-Cpo is used to determine the dynamic Dower consumption, per flip-flop.
PO = Cpo Vee"fi + I Vee" CL fo where:
fi = Input Frequency
CL = Output Load Capacitance
Vee = Supply Voltage
fo = Output Frequency
PREREQUISITE FOR SWITCHING FUNCTION
LIMITS
TEST
CONDITION
CHARACTERISTIC
HC
Vee
V
Set-up Time
J, K 10 CP
Hold Time
J, KIO CP
Removal Time
R, SIO CP
PulseWidlh
CP, R,S
CP Frequency
tsu
th
tREM
tw
fMAX
_40 C to +85° C
25°C
0
HCT
74HC
74HCT
-55°C to +125°C
54HC
UNITS
54HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
-
2
4.5
6
80
16
14
18
2
4.5
6
5
5
5
3
2
4.5
6
80
16
14
18
.2
4.5
6
80
16
14
18
2
4.5
6
6
30
35
27
-
-
-
100
20
17
23
5
5
5
3
-
-
100
20
17
23
100
20
17
23
5
25
29
22
-
-
-
120
24
20
27
5
5
5
3
4
20
23
ns
-
120
24
20
120
24
20
ns
-
27
ns
27
ns
18
MHz
-
142 ____________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC109
CD54/74HCT109
SWITCHING CHARACTERISTICS (CL
CHARACTERISTIC
50 pF, Inpull.,I,
tPHL
S->O
tPLH
a
tPHl
Fi .... O
tPHL
A.... a
tPLH
Transition
Times
hLH
hHL
Input
Capacitance
175
35
30
120
24
20
155
31
26
185
37
31
170
34
29
75
15
13
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
tPHL
a
0
6 ns)
_40° C 10 + 85° C
-55° C 10 + 125° C
25°C
HCT
74HC
74HCT
54HCT
HC
54HC
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Vee
Propagation Delay,
CP .... O,
S ....
0
C,
40
-
30
-
45
-
45
-
37
-
15
-
-
220
44
37
-
150
30
26
195
39
33
230
46
39
215
43
37
95
19
16
-
265
53
45
50
-
-
180
36
31
235
47
40
280
56
48
255
51
43
110
22
19
38
-
56
-
56
-
46
-
19
60
ns
-
45
ns
-
68
ns
-
ns
68
-
ns
56
-
22
ns
-
-
-
-
-
-
-
10
10
10
10
10
10
-
-
-
-
-
-
pF
I,...----INPUT LEVEL
INPUT LEVEL
cp
-GND
'w llf max
'P~H
tpHL
_
90%
aORO
10%
tREMF-
OORO
Vs
tTLH
tTHl
CP
92CS·38533R2
Vs
_ _ _ _ _ _....J.
Fig. 2 - Clock to output delays and clock pulse width.
-
INPUT LEVEL
GNO
92CS-38534R2
Fig. 3 - Reset or Set prerequisite and propagation delays.
- - , ' , , - - - - W - - - 1 N ? U T LEVEL
J OR
K_ _
JI'~
__
JI'~
__
54/74 HC
54/74 HCT
Vee
3V
50% Vee
1.3V
CP
GND
Input Level
92CS-3853SR2
Swilching Vollage, Vs
Fig. 4 - Data set-up and hold times.
______________________________________________________________ 143
Technical Data ___________________________________________________________
CD54/74HCT112
CD54/74HCT112
File Number
1843
High-Speed CMOS Logic
15
4
IJ
IK
ICP
IQ
Dual J-K Flip-Flop with Set and Reset
1Q
Negative-Edge Trigger
;ii
rs
9
2J
Type Features:
2Q
•
2Q
2R
•
•
•
•
GNO"S
Vee"'6
92CS-40341
Hysteresis on clock inputs for improved noise immunity and increased
input rise and fall times
Asynchronous set and reset
Complementary outputs
Buffered inputs
Typical f ma, = 60 MHz @ Vee = 5 V, CL = 15 pF, TA = 25 0 C
FUNCTIONAL DIAGRAM
The RCA-CD54174HCI12 and CD54/74HCT112 utilize
silicon-gate CMOS technology to achieve operating speeds
equivalent to LSTTL parts. They exhibit the low power
consumption of standard CMOS integrated circuits,
together with the ability to drive 10 LSTTL loads.
These flip-flops have independent J, K, Set, Reset, and
Clock inputs and Q andQoutputs. They change state on
the negative-going transition of the clock pulse. Set and
Reset are accomplished asynchronously by low-level inputs.
The 54HCT174HCT logic family is functionally as well as
pin-compatible with the standard 54LS/74LS logic family.
The CD54HC112 and CD54HCT112 are supplied in 16-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC112 and CD74HCT112 are supplied in 16-lead
dual-in-line pillstic packages (E suffix) and in 16-lead dualin-line surface-mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
TRUTH TABLE
(EACH FLIP-FLOP)
INPUTS
Family Features:
•
•
•
•
•
•
•
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85 0 C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to
LSTTL Logic ICs
Alternate Source is PhilipslSignetics
CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity: ML = 30%, N,H = 30% of Vee,
@ Vee = 5 V
CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V'H = 2 V Min.
CMOS Input Compatibility
I, ::; 1 IlA @ VOL, VO H
OUTPUTS
S
-R
CP
J
K
Q
L
H
X
X
X
H
L
H
L
X
X
x
L
H
X
H'
L'
a
L
L
X
X
H
H
~
L
L
No Change
H
H
~
H
L
H
H
H
~
L
H
L
H
H
~
H
H
Toggle
H
H
H
X
X
No Change
I
L
H
• Output states unpredictable if Sand R go High
simultaneously aiter both being low at the same time.
H = High steady state.
L = Low steady state.
X = Irrelevant.
~= High-to-Low transition.
144 ____________________________________________________________________
___________________________________________________________ TechnicaIData
CD54/74HCT112
CD54/74HCT112
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE. (Vee):
(Voltages referenced to ground) ...................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT. 1,K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ....................................................... ±20 rnA
DC OUTPUT DIODE CURRENT. 10K (FOR Va < -0.5 V OR Va > Vee +0.5 V) ................................................... ±20 rnA
DC DRAIN CURRENT. PER OUTPUT (10) (FOR -0.5 V < Va < Vee +0.5 V) .................................................... ±25 rnA
DC Vee OR GROUND CURRENT. (Icc): ..................................................................................... ±50 rnA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60"C (PACKAGE TYPE E) ............................................................................... 500 mW
For TA = +60 to +85" C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/" C to 300 mW
For TA = -55 to +100"C (PACKAGE TYPE F. H) ........................................................................... 500 mW
For TA = +100 to +125"C (PACKAGE TYPE F. H) ............................................. Derate Linearly at 8 mW/"C to 300 mW
ForTA = -40 to +70" C (PACKAGE TYPE M) .............................................................................. 400 mW
For TA = +70 to +125"C (PACKAGE TYPE M) ................................................. Derate Linearly at 6 mW/"C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F. H ............................................................................................. -55 to +125"C
PACKAGE TYPE E. M .............................................. '" . .... ..... .. ........... .......... . ... ... ...
-40 to +85"C
STORAGE TEMPERATURE (T".) .................................................................................... '65 to +150"C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ........................................................ +265"C
Unit inserted into a PC board (min. thickness 1/16 in .. 1.59 mm)
with solder contacting lead tips only ................................................................................... +300"C
_t~t3)
CP
92CM-40340
CL
Cl.
Fig. 1 - Flip-flop logic diagram.
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating condillons should be selected so that operation is always within the
following ranges:
LIMITS
UNITS
CHARACTERISTIC
MIN.
MAX.
Supply-Voltage Range (For T A = Full Package-Temperature Range) Vcc:'
CD54/74HC Types
CD54174HCT Types
DC Input or Output voltage v" vo
2
6
V
4.5
5.5
V
0
vcc
V
Operating Temperature TA:
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
at 2 V
0
1000
ns
at 4.5 V
0
500
ns
at6v
0
400
ns
Input Rise and Fall Times. t" t,.
..
• Unless otherwise specified, all voltages are referenced to Ground .
____
145
•______________
Applicable for all inputs
except ________________________________________________
clock.
~
~
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HCT112
CD54/74HCT112
STATIC ELECTRICAL CHARACTERISTICS
CD74HC112, CD54HC112
CD74HCT112, CD54HCT112
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
UNITS
CHARACTERISTICS
+25°C
V,
Ic
Vee
V
mA
V
High-Level
V,"
Low-Level
Input Voltage
V"
High-Level
V"
Output Voltage
or
Vo "
CMOS Loads
-0.02
V,"
Min Typ Max Min Max Min Max
1.5
-
-
1.5
-
1.5
-
4.5 3.15
-
-
3.15
-
3.15
-
-
4.2
-
4.2
-
2
Input Voltage
+25°C
6
4.2
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
Low-Level
Voe
CMOS Loads
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
2
-
-
4.5
-
10
5.5
1.9
-
-
1.9
-
1.9
-
4.4
--
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5 3.98
-
-
3.84
-
3.7
-
or
5.34
-
5.2
-
V,"
V"
V"
V"
-5.2
6
5.48
-
-
2
-
-
0.1
-
0.1
-
0.1
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
jJA
5.5
-
-
4
-
40
-
80
jJA
-
100 360
-
450
-
490
jJA
V"
or
4
4.5
-
-
0.26
-
0.33
-
0.4
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
Input Leakage
Any
I,
Voltage
Vee
or
6
-
-
±0.1
-
±1
-
±1
Gnd
Between
Vee and
Gnd
Quiescent Device
Current
2
to
5.5
V,"
or
Min Typ Max Min Max Min Max
4.5
-
2
V"
Current
V
-4
V,"
TTL Loads
V
or
V"
Output Voltage
Vee
4.5
V"
TTL Loads
V,
Vee
Vee
Icc
or
0
6
-
-
4
-
40
-
Gnd
80
or
Gnd
Additional
Quiescent Device
4.5
Vee -2,1
Current per
to
5.5
Input Pin:
1 Unit Load
t::.1cc
'For dual-supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specification is 1.8 mAo
HCT INPUT LOADING TABLE
16
1ep
15
1K
INPUT
18,
UNIT LOADS *
1J
is
2S
0.5
10
1K,2K
0.6
1Q
fR,
2R
1J, 2J, 1CP, 2CP
0.65
2'0
1
GNO
I.
•
13
12
11
10
2R
2CP
2K
2J
2S
20
TOPVIEW
• Unit Load is fl.lcc limit specified in Static Characteristic
Vee
1R
92CS-40339
TERMINAL ASSIGNMENT
146 _Chart,
___
_360
__
__
__
e.g.,
f1A _
max.
@ 25°
C. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
______________________________ Technical Data
CD54/74HCT112
CD54/74HCT112
SWITCHING CHARACTERISTICS (Vee
=5 V, TA =25°C, Inpul I" I, =6 ns)
TYPICAL VALUES
CL
(pF)
CHARACTERISTIC
UNITS
HC
HCT
14
14
ns
13
13
ns
Propagation Delay
CPto 0,
Q
15
tPLH, tpHL
StoO,O
15
14
ns
fmBx
15
60
60
MHz
Cpo
-
12
20
pF
RtoO,O
CP Frequency
Power Dissipation Capacitance'
• Cpo is used to determine the dynamic power consumption, per flip-flop.
Po =Cpo Vee2 f; + I CL Vee 2 10 where: f; =input frequency
CL =output load capacitance
fo = output frequency
Vee = supply voltage
PRE-REQUISITE FOR SWITCHING FUNCTION
LIMITS
TEST
CHARACTERISTIC
Vee
V
tw
CP
tsu
J, K to CP
Hold Time
, tH
J, K to CP
Removal Time
tREM
R to CP
StoCP
CP Frequency
f mBx
HCT
74HC
74HCT
54HC
54HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
80
-
-
-
16
_.
16
-
6
14
80
-
-
2
2
4.5
R,S
Set-up Time
-55° C 10 +125° C
UNITS
HC
Pulse Width
-40°C 10 +85°C
25°C
CONDITION
20
120
23
24
-
27
-
-
20
-
120
-
-
-
24
24
-
24
-
20
4
-
20
16
-
18
-
-
2
80
-
-
16
-
20
-
20
-
-
-
17
-
-
-
0
-
-
3
-
0
-
3
-
20
-
-
0
-
-
-
0
-
120
6
14
2
0
4.5
0
6
0
-
-
-
20
-
17
-
100
-
24
14
16
17
100
120
6
4.5
-
-
20
-
4.5
-
-
-
-
-
-
24
-
-
100
2
80
-
-
-
100
-
-
4.5
16
20
-
20
-
25
6
14
17
-
-
6
-
-
2
-
5
-
-
4.5
30
30
-
25
-
25
6
35
-
-
-
29
-
-
0
0
20
23
-
-
-
30
-
-
-
-
-
-
-
20
-
3
-
-
ns
-
-
ns
ns
ns
ns
MHz
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 147
Technical Data
CD54/74HCT112
CD54/74HCT112
SWITCHING CHARACTERISTICS (C L = 50 pF, Inpul I" If = 6 ns)
LIMITS
TEST
CONDITION
CHARACTERISTIC
25°C
Propagation
Delay
CPto a,
54HC
54HCT
2
-
175
-
-
-
220
-
-
-
265
-
-
4.5
-
35
-
35
-
44
-
44
53
6
30
-
-
37
-
-
45
155
-
-
-
235
-
-
-
32
39
-
-
31
40
-
48
-
26
-
33
-
-
-
47
6
-
195
4.5
-
-
53
-
-
40
-
Q
2
-
180
-
-
4.5
-
36
-
37
-
225
-
-
-
270
-
-
45
-
46
-
54
-
56
38
-
-
-
46
-
-
-
95
-
-
-
110
-
-
19
19
-
22
-
-
19
-
22
16
-
10
-
10
-
10
-
10
6
-
31
-
2
75
-
-
hHL
4.5
-
15
-
15
13
-
-
-
-
10
-
10
-
Input
C,
ns
-
-
tTLH
6
Capacitance
74HCT
tPHL
stoa,5
Time
74HC
tPLH
Q
Output Transition
HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
2
Rtoa,
-55°C 10 +125°C
UNITS
HC
Vee
V
-40°C 10 +85°C
ns
ns
ns
pF
INPUT
LEVEL
StRI
-
GNO
Q tQI
QtQI
'REM~
92CS- 39232
_
~UT
Vs
LEV EL
GNO
______~ , ________~ , ______ INPUT
92CS-39233RI
LEVEL
J ORK
' - - - - - - GNO
'SU
CP ----------~
I N PUT
LEVEL
92CS-39234
Input Level
Switching Voltage, Vs
54/74HC
54174HCT
Vee
3V
50% Vee
1.3 V
Fig. 2 - Transition times, propagation delay times, and setup and hold times.
148 ______________________________________________________________
___
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - T e c h n i c a l Data
File Number
1708
CD54/74HC123, CD54/74HCT123
CD54/74HC423, CD54/74HCT423
Advance Information/
Preliminary Data
High-Speed CMOS Logic
1 C.
I ••
Vcc
,.
13
"iA
1R
2R
ro
Dual Retriggerable Monostable
Multivibrators with Resets
Type Features:
fl
2A
2.
10
20
12
10
2Q
vcc
2C.
2 ••
•
•
•
•
•
•
Overriding RESET Terminates Output Pulse
Trigge!l.!Jg From the Leading or Trailing Edge
Q and Q Buffered Outputs
Separate Resets
Wide Range of Output-Pulse Widths
Schmitt Trigger on both ;if and B inputs
FUNCTIONAL DIAGRAM
The RCA-CD54174HCT123,423 and CD54174HCT123,423
are dual monostable multivibrators with resets. They are ali
retriggerable and differ only in that the 123 types can be
triggered by a negative-to-positive reset pulse; whereas the
423 types do not have this feature. An external resistor (R.)
and an external capacitor (C.) control the timing and the
accuracy for the circuit. Adjustment of R. and C. provides a
wide range of output pulse widths from the Q and Q terminals. Pulse triggering on the A and B inputs occur at a particular voltage level and is not related to the rise and fail
times of the trigger pulses.
Once triggered, the output pulse width may be extended by
retriggering inputs A and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing-edge
triggering (A) and leading-edge triggering (B) inputs are
provided for triggering from either edge of the input pulse.
If either Mono is not used each input on the unused device
(A, B, and R) must be terminated high or low.
The minimum value of external resistance, R. is typically
500 n. The minimum value external capacitance, C., isO pF.
The calculation for the pulse width is tw = 0.45 R.C. at Vee =
5 V.
The CD54HC123,423 and CD54HCT123,423 are supplied in
16-lead hermetic dual-in-line ceramic packages (F suffix).
The CD74HC123,423 and CD74HCT123,423 are supplied in
16-lead dual-in-line plastic packages (E suffix) and in 16lead dual-in-line surface mount plastic packages (M suffix).
All types are also available in chip form (H suffix).
Family Features:
•
•
•
•
•
•
•
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to
LSTTL Logic ICs
Alternate Source is Philips/Signetics
CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML =30%, MH =30% of Vee; @ Vee =5 V
CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, ::; 1 fJA @ VOL, VOH
~
lA
18
iR
iQ
20
2Cx
2AXCx·
GND
1
16
Vcc
15 lRX
14
13
ex
1Cx
10
12 2Q
11
2R
10 2B
9
2A
TERMINAL ASSIGNMENT
____________________________________________________ 149
Technical D a t a - - . - - - - - - - - - - - - - - - - - - - - - - - - - - - -
CD54/74HC123, CD54/74HCT123
CD54/74HC423, CD54/74HCT423
STATIC ELECTRICAL CHARACTERISTICS
CD74HC123/CD54HC123
CD74HCT123/CD54HCT123
CD74HC423/CD54HC423
CD74HCT423/CD54HCT423
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+8S o C
+125°C
+85 Q C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
10
Vee
V
mA
V
High-Level
I nput Voltage
V,H
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
VOH
CMOS Loads
or
-0.02
V,H
Min Typ Max Min Max Min Max
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
1.35
6
-
1.8
-
1.8
-
-
1.9
-
1.9
-
4.4
-
4.4
-
2
1.5
4.5
3.15
6
4.2
-
1.5
-
3.15
-
3.15
4.2
-
4.2
-
1.5
2
1.9
4.5
4.4
-
6
5.9
-
-
5.9
-
5.9
-
Output Voltage
Voe
CMOS Loads
-
-
2
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5:5
-
-
±0.1
-
±1
-
±1
pA
5.5
-
-
8
-
80
-
160
pA
-
450
-
490
pA
4.5
-
to
5.5
V"
or
V,H
V"
-
3.84
-
3.7
-
or
V,H
-5.2
6
5.48
-
-
5.34
-
'5.2
-
.VIH
2
-
-
0.1
-
0.1
4.5
0.1
-
0.1
-
0:1
or
6
-
-
0.1
0.02
0.1
-
0.1
-
0.1
V,H
0.4
or
0.4
V,H
±1
V"
V"
or
4
4.5
-
-
0.26
-
0.33
V,H
5.2
6
-
-
0.26
-
0.33
-
6
-
-
±0.1
-
±1
-
Any
I,
Vee
or
Gnd
Quiescent
lee
or
Voltage
Between
Vee & Gnd
Vee
Vee
0
6
-
-
8
-
80
-
160
or
Gnd
Gnd
Additional
4.5
Quiescent Device
Vee -2.1
CUrrent per input
pin: 1 unit load
2
to
5.5
-
I nput Leakage
Device Current
-
3.98
or
Min Typ Max Min Max Min Max
4.5
4.5
V"
Current
V
-4
V,H
TTL Loads
V
or
V1L
Low-Level
Vee
1.8
V"
TTL Loads
+25"C
V,
to
-
100 360
5.5
blce
*For dual-supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT INPUT LOADING TABLE
INPUT
UNIT LOADS·
All Inputs
0.35
• Unit Load is ll.lcc limit specified in Static Characteristic
Chart, e.g., 360l1A max. @ 25° C.
150 ___________________________________________________________________
_ _ _ _ Technical Data
CD54/74HC123, CD54/74HCT123
CD54/74HC423, CD54/74HCT423
HC/HCT423 TRUTH TABLE
HC/HCT123 TRUTH TABLE
INPUTS
X
L
H
X
L
H
L
H
L
~
H
"---
H
H
JL
JL
LS
U
X
L
L
H
A
B
x
a
L
H
H
X
L
H
L
H
L
~
H
n
"---
H
H
JL
LS
U
x
X
H
X
L
H
H
H = High Level
L = Low Level
X = Irrelevant
L
f
f
L
n
a
a
a
B
OUTPUTS
R
H
R
H
A
I
INPUTS
OUTPUTS
LS
= Transition from Low to High
"--- = Transition from High to Low
JL
U
= One High Level Pulse
ReX
= One Low Level Pulse
r~--I(---,
Vee
16
0
9
-1
AxCx
Cx
15(7)
14 (6)
13 (5)
>O----{)Q
92CM- 39225RI
Fig. 1 - Logic diagram for HCIHCT123 and 423.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ...................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, I,K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ....................................................... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Va < -0.5 V OR Va > Vee +0.5 V) ................................................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Va < Vee +0.5 V) .................................................... ±25 mA
DC Vee OR GROUND CURRENT, (Icc): ..................................................................................... ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60° C (PACKAGE TYPE E) ............................................................................... 500 mW
For TA = +60 to +85° C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/o C to 300 mW
ForTA = -55 to +100°C (PACKAGE TYPE F, H) .......................... .......... .......
. ......................... 500 mW
For TA = +100 to +125° C (PACKAGE TYPE F, H) ............................................. Derate Linearly at 8 mwr C to 300 mW
For T A = -40 to +70° C (PACKAGE TYPE M)
............................................ 400 mW
For TA = +70 to +125°C (PACKAGE TYPE M) .................................................. Derate Linearly at 6 mwrc to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H ............................................................................................. -55 to +125° C
PACKAGE TYPE E, M .............................................................................................. -40 to +85°C
STORAGE TEMPERATURE (T",) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ........................................................ +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ..................................................................................... +300° C
151
Technical Data ..
'CD54/74HC123, CD54/74HCT123
CD54/74HC423, CD54/74HCT423
RECOMMENDED OPERATING CONDITIONS:
·For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
UNITS
MIN.
MAX.
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vee:'
2
6
V
4.5
5.5
V
0
Vee
V
CD74 Types
-40
+85
°C
CD54 Types
°C
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V" Vo
Operating Temperature TA:
Input Rise and Fall Times t" tf on Input R
Input Rise and Fall Times t" tf on Input B and Po.
-55
+125
at2V
0
1000
ns
at4.5V
0
500
ns
at6V
0
400
ns
at2V
0
Unlimited
ns
at4.5
0
Unlimited
ns
at6V
0
Unlimited
ns
'Unless otherwise specified, all voltages are referenced to Ground.
PREREQUISITE FOR SWITCHING FUNCTION
LIMITS
~55°CC
-40°C to+85°C
25°C
CHARACTERISTIC
to +125°C
Vee
UNITS
HC
HCT
74HC
74HCT
54HC
54HCT
Min. Max. Min. Max.· Min. Max. Min. Max. Min. Max. Min. Max.
Minimum Input
Pulse Width
2
tWL
4.5
tWH
6
2
4.5
tWL
6
2
4.5
tH
6
2
4.5
tREM
6
2
4.5
6
A
B
R
Po. & B Hold Time
Reset Removal Time
Retrigger Time #
R. = 10 KO
Output Pulse
Width QorQ
R. =10 KO, C. =10 nF
hT
tw
100
20
17
100
20
17
100
20
17
50
10
-
9
-
50
10
9
-
-
20
-
-
-
-
-
-
-
20
-
-
-
-
-
20
-
-
-
-
-
-
-
10
-
-
10
-
-
-
-
-
-
-
5
50 Typ.
50 Typ.
5
40
40
50
50
125
25
21
125
25
21
125
25
21
65
13
11
65
13
11
-
-
-
25
-
-
25
-
-
-
25
-
-
-
-
-
-
-
-
-
13
-
-
-
-
-
-
-
-
13
-
-
-
63 Typ.
-
63 Typ.
150
30
26
150
30
26
150
30
26
75
15
13
75
15
13
-
-
-
-
-
-
30
-
-
30
-
-
-
-
-
-
-
~.
_ _ _ _ _ _ _ _ _ _ _ _.
-
-
-
-
15
-
-
-
-
-
-
76 Typ.
ns
-
15
-
-
ns
-
76 Typ.
38.7 51.3 38.7 51.3 38.2 51.8 38.2 51.8
#Time to trigger depends on the values of R, and C,. The output pulse width ean only be extended when the time
between the active-going edges of the trigger input pulses meet the minimum retrigger time requirement.
152._ _
-
30
-
-
ns
-
ns
ns
ns
us
Technical Data
CD54/74HC123, CD54/74HCT123
CD54/74HC423, CD54/74HCT423
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25° C, Inpul I" If = 6 ns)
TYPICAL VALUES
CHARACTERISTIC
Cl
(pF)
54/74HC
54174HCT
UNITS
Propagation Delay
A,
B, Rto Q
tPLH
15
25
25
ns
A, B, R to Q
tPHL
15
26
27
ns
-
45
45
J1S
-
±2
±2
%
-
-
-
pF
Output Pulse Width
R, = 10 KO, C, = 10 nF
Pulse Width Match Between Circuits in the same Package
R, = 10 KO, C, = 10 nF
Power Dissipation Capacitance'
Cpo
• CPO is used to determine the dynamic power consumption, per multivibrator.
Po = (Cpo + C,) Vee 2 f, + 2: (C l Vee 2 fo) where:
f, = input frequency.
fo = output frequency.
C l = output load capacitance.
C, = external capacitance.
Vee = supply voltage.
assuming f, ~ ---'--
tw
SWITCHING CHARACTERISTICS (C l = 50 pF, Inpul I" If = 6 ns, R, = 10 KO, C, = 0)
LIMITS
CHARACTERISTIC
SYMBOL
_55° C 10 +125° C
_40° C 10 +85° C
25°C
Vee
~-----.------~------,-------~-----,-------iUNITS
HCT
HC
74HC
74HCT
54HC
54HCT
Min, Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Trigger Propagation
2
300
Delay,
4.5
60
A,
B,Rto Q
6
51
2
320
A,
B, R to
4.5
64
Q
Reset Propagation
Delay,
tPLH
Rto Q orO
Output Transition
Time
I nput Capacitance
- - -...
C,
450
375
60
75
90
75
64
400
68
80
96
-
68
215
270
4.5
43
6
37
46
55
2
75
95
110
4.5
15
6
13
10
15
19
10
------.-.-------~--------
10
ns
72
ns
22
ns
10
pF
325
60
19
65
22
19
16
-
102
82
54
2
54
ns
480
85
6
48
90
76
10
10
153
Technical Data
CD54/74HC123, CD54/74HCT123
CD54/74HC423, CD54/74HCT423
0.'
EXTERNAL CAPACITANCE (CX1:IOnF
EXTERNAL RESISTANCE (R X ) ·10 KU TO 100 Kn
AMBIENT TEMPERATURE (TA); 25 D C
0.8
0.7
0.6
'"o
HeT
~O.5
0.3
0.2
2
10
24662468246B
103
104
105
2:
10 6
4
0.1
68
10
10'
EXTERNAL CAPACITANCE (CX1-pF
DC SUPPLY VOLTAGE (Vecl-VOLTS
92:CS-39221
Fig. 3 - Typical output pulse width as a function ofC, forR, = 10kO
and 100 kO.
II
92CS-39222
Fig. 4 - Typical "K" Factor as a function of Vee.
cc l=5V
10 4 8
DC SUPPLY VOLTAGE(V
AMBIENT TEMPERATURE (TA):25 D C
6
4
2
~
..!.. 103
RX.,OKV
B
'"-'a.
6
4
>
RX" 100 KU
g
z
!2
2
102
B
I-
6
<3
0:
-~
4
~
2
V
L
,
,
10
2
2
46B
10
2
468
10 2
4
68
2
,
4
2
6B
10 4
103
A
B
-V
J\
,
I
4
68
10 5
92C5-39226
EXTERNAL CAPACITANCE (CX}-pF
Fig. 5 - Typical propagation delay as a function of External
Capacitance (C,).
Ii:
B'LOW
A.
HIGH
if
B
R
Q
-V
\
J\
I
B'LOW
A'
~ 'w
'w-
92CS- 39223
Output pulse control using reset input (R) for 123.
92CS-39224
Output pulse control using reset input
Input Level
Switching Voltage, Vs
Output pulse control using retrigger pulse for 123 and 423.
Fig. 2 - Triggering of One Shot by input A or input B for a period two
154 _ _ _ _ _._.__.
[Rj for 423.
54174HC
54/74HCT
Vee
3V
50% Vec
1.3 V
HIGH
_____________________________________________________________ TechnicaIOata
File Number
CD54/74HC125
CD54/74HCT125
1771
High-Speed CMOS Logic
Quad Buffer; 3-State
Type Features:
• Separate output enable inputs
• 3-state outputs
FUNCTIONAL DIAGRAM
The RCA-CD54/74HC125 and CD54/74HCT125 contain 4
independent 3-state buffers, each having its own output
enable input, which when "HIGH" puts the output in the
high impedance state.
The CD54HC125 and CD54HCT125 are supplied in 14-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC125 and CD74HCT125 are supplied in 14-lead dualin-line plastic packages (E suffix) and in 14-lead dual-inline surface mount plastic packages (M suffix). Both types
are also available in chip form (H suffix).
Family Features:
• Fanout (over temperature range):
Standard outputs - 10 LSTTL loads
Bus driver outputs - 15 LSTTL loads
• Wide Operating Temperature Range:
CD74HCIHCT/HCU: -40 to +85°C
• Balanced Propagation Delay and Transition Times
II Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity: NIL = 30%, N,H = 30% of Vee,
@ Vee = 5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility I" S 1 j1A @ VOL, V OH
TRUTH TABLE
Inputs
nY
nA
nA
H
L
X
nOE
92CS-39809
Fig. 1 - Logic diagram.
H=
L=
X=
Z=
l
Outputs
nOE
nY
L
L
H
H
L
Z
High Level
Low Level
Don't Care
High Impedance, OFF State
______________________________________________________________________ 155
Technical Data ______._____________________________
CD54/74HC125
CD54/74HCT125
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ................,.............................. .
DC INPUT DIODE CURRENT,
',K (FOR V, <-0.5 V OR V, >
.. ............................ -0.5 to +7 V
Vee + 0.5 V) ........... .
. ...................... , ...... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Va < -0.5 V OR Va> Vee +0.5 V) ....... .
. ..................... ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Va < Vee + 0.5 V) ................... .
. ..................... ±35mA
DC Vee OR GROUND CURRENT (lee) .................. , , .. , .............................. .
. ............ ±70mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60°C (PACKAGE TYPE E) ........................................................................... 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) ............................
For TA = -55 to +100°C (PACKAGE TYPE F, H) .......
. .............. Derate Linearly at 8 mW/oC to 300 mW
. ............................................. 500 mW
For TA = +100 to +125°C (PACKAGE TYPE F, H) ......................................... Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) .......................................................................... 400 mW
For TA = +70 to +125°C (PACKAGE TYPE M) ............................................. Derate Linearly at 6 mWI"C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .......................................................................................... -.55 to +125°C
PACKAGE TYPE E, M ............................................................... ..
....................... -40 to +85°C
STORAGE TEMPERATURE (T",) ...................................................................... .
.. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ............................................. .
..... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only .................................................................................. +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA = Full Package Temperature Range) Vee:'
CD54174HC Types
CD54/74HCT Types
MAX.
2
4.5
6
5.5
V
0
Vee
V
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
DC Input or Output Voltage V,N • VOUT
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t" tf
at 2 V
at 4.5 V
at 6 V
'Unless otherwise specified, all voltages are referenced to Ground.
14
Vee
2
13
40E
3
12
4
11
5
10
6
9
7
8
10E
1A
1Y
20E
2A
2Y
GND
4A
4Y
30E
3A
3Y
92CS-39808
TERMINAL ASSIGNMENT
156 _ _ _ _ _ __
UNITS
MIN_
_____________________________________________________________ TechnicaIData
CD54/74HC125
CD54/74HCT125
STATIC ELECTRICAL CHARACTERISTICS
CD74HC125/CD54HC125
CD74HCT125/CD54HCT125
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
CONDITIONS
TYPES
TYPE
TYPE
CONDITIONS
TYPES
-40/
-55/
+85°C
+125°C
74HCT
54HCT
TYPE_
TYPE
CHARACTERISTIC
UNITS
V,
10
Vee
V
rnA
V
+25°C
V,
Vee
V
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
-
-
1.5
-
1.5
-
-
-
3.15
-
3.15
-
-
2
V,"
Low-Level
Input Voltage
1.5
4.5 3.15
V"
High-Level
V"
Output Voltage
or
Va"
CMOS Loads
-0.02
-
4.2
4.2
-
4.2
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
V"
4.5
4.4
-
-
4.4
-
4.4
-
or
5.9
-
-
5.9
-
5.9
-
V,"
4.5 3.9B
-
-
3.84
-
3.7
-
or
-
-
5.34
-
5.2
-
V,"
V,"
-7.8
6
5.48
2
-
-
0.1
-
0.1
-
0.1
V"
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
Va'
CMOS Loads
V,"
V"
or
6
4.5
-
-
0.26
-
0.33
-
0.4
or
(Bus Driver)
V,"
7.8
6
-
-
0.26
-
0.33
-
0.4
V,"
Input Leakage
Vee
±1
160
J,
or
6
-
-
±0.1
-
±1
6
-
-
8
-
80
-
0
Gnd
Leakage
Current
1m
2
-
V
10
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
3.7
-
V
4.5 3.98
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
Voltage
Between
Vee
and
Gnd
5.5
-
-
±0.1
-
±1
-
±1
Il A
or
5.5
-
-
8
-
80
-
160
IlA
-
100 360
-
450
-
490
Il A
-
-
-
±5
-
±10
IlA
Gnd
AdditIonal
Quiescent Device
Current per
Input Pin:
1 Unit Load
Alec
3-Slale
-
Vee
Vee
or
2
Any
-
Gnd
Quiescent Device
Current
Icc
-
V"
TTL Loads
Current
-
V"
(Bus Driver)
or
2
5.5
-6
V"
10
4.5
-
or
Low-Level
+125°C
5.5
TTL Loads
Output Voltage
+85°C
4.5
6
V"
-55/
Min Typ Max Min Max Min Max
-
6
V,"
+25°C
-40/
4.5
Vee -2.1
10
5.5
V"
or
V,"
Va-Vee
or
Gnd
6
-
-
- For dual-supply syslems theoretical worst case (V,
±0.5
-
±5
-
±10
V"
or
V,"
5.5
±0.5
= 2.4 V, Vee = 5.5 V) specification is 1.B rnA.
HCT Input Loading Table
Input
Unit Loads'
nA, nOE
'Unit Load is Ll.lee limit specified in Static Characteristics
Chart, e.g., 360/lA max. @ 25°C.
____________________,_________________________________________________ 157
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC125
CD54/74HCT125
SWITCHING CHARACTERISTICS (Vee=5 V, T A =25°C, Input t" t,=6 ns)
CHARACTERISTIC
Propagation Delay Time: (Fig. 2)
nA to nY
tPHL
CL
TYPICAL
pF
HC
HCT
15
8
10
UNITS
t pLH
Output Enabling Time
tpzL, tPZH
15
10
10
Output Disabling Time
tPLZ. tpHZ
15
10
11
-
29
34
Cpo
Power Dissipation Capacitance*
ns
pF
'Cpo is used to determine the dynamic power consumption, per channel. Po=Vcc 2fi (CPO+CL) where: fi=input frequency
CL=load capacitance
Vcc=supply voltage
SWITCHING CHARACTERISTICS (CL=50 pF, Input t" t,=6 ns)
25°C
CHARACTERISTIC
SYMBOL
HC
Vee
Enable Delay
Time
(Fig. 2)
Disable Delay
Time
-
2
4.5
6
tPLH
t pHL
IpzH
tPZL
-
-
2
4.5
6
tPHZ, tPLZ
-40°C to +85°C
-55°C to +125°C
74HC
54HC
74HCT
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
V
Propagation Delay
Time nA to nY
(Fig. 2)
HCT
-
2
4.5
6
-
2
4.5
6
-
-
-
100
20
17
-
-
-
125
25
21
-
125
25
21
-
25
-
155
31
26
-
125
25
21
-
28
-
155
31
26
-
35
60
12
10
-
12
75
15
13
-
-
-
25
-
-
Output Transition
Time
hLH
hHL
Input Capacitance
C,
-
-
10
-
10
3-State Ouput
Capacitance
Co
-
-
20
-
20
-
-
-
31
-
-
-
-
-
31
-
-
15
-
-
-
-
10
-
10
-
20
-
20
-
-
t,=6:l r.
150
30
26
-
-
-
38
-
-
190
38
32
-
-
-
38
-
-
190
38
32
-
42
90
18
15
-
18
10
-
20
-
20
-
ns
-
10
pF
1("=6"'
=
~~!~:EU(t-'-PL-z-[---->r- =~8:
tr= 6ns
IN PUT -~l<-==~""
LEVEL
nA _ _~~
OUTPUT
tpZL
L--
tpHZ 1-
H,g~Vo~
-
VOL
-1--V5 VOH
tpZH
OUTPUTS --l-OUTPUTS
CONNECTED
r-
--Vs
_10o~
LOW TO OFF
1'r;::
---L--
DlSCONNEC1EO
OUTPUTS_
CONNECTED
92CS-39806
92CS-38531RI
54l74HC
Input Level
Switching Voltage, Vs
Fig. 2 -
54/74HCT
Vee
3V
50% Vee
1.3 V
Transition and propagation delay times.
158 _________________________________________________________________
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - T e c h n i c a l Data
CD54/74HC125
CD54/74HCT125
OTHER {
INPUTS
(lied
high
or low)
OUTPUT
DISABLE
Ie WITH
3-STATE
ouTPUT
OUTPUT RL : Ik
CL
I,O,F
n {vee for tpLZ and tpZL
GNO for tpHZ and IpZH
92CS-3!i130R2
Fig. 3 - Three-state propagation delay test circuit.
________________________________ 159
Technical Data _ _ _._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _._ _ _ __
CD54/74HC126
.CD54/74HCT126
File Number
1772
High-Speed CMOS Logic
Quad Buffer; 3-State
Type Features:
• Separate output enable inputs
• 3-state outputs
FUNCTIONAL DIAGRAM
The RCA CD54174HC126 and CD54174HCT126 contain
four independent 3-state buffers, each having its own output enable input, which when "low" puts the output in the
high~impedance state.
The CD54HC/HCT126 are supplied in 14-lead hermetic
dual-in-line ceramic packages (F suffix). The CD74HC/
HCT126 are supplied in 14-lead dual-in-line plastic packages (E suffix) and in 14-lead dual-in-line surface mount
plastic packages (M suffix). Both types are also available in
chip form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT/HCU: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 30%, MH = 30% of Vee; @ Vee = 5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'L = 0.8 V Max., V'H = 2 V Min.
CMOS Input Compatibility I" S 1 IJA @ VOL, VOH
TRUTH TABLE
Outputs
Inputs
nY
nAo------t
nOE
92CS'39802
Fig. 1 - Logic Diagram
nA
nOE
nY
H
L
X
H
H
L
H
L
Z
H=
L=
X=
Z=
I
High Level
Low Level
Don't Care
High Impedance (Off-State)
160 _________._______________________________________________________
_ _ _ _ _ ,______ Technical Data
CD54/74HC126
CD54/74HCT126
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, 1,K (FOR V, <-0.5 V OR V, > Vee + 0.5 V) .................................................... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Va < -0.5 V OR Va> Vee +0.5 V) ................................................ ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Va < Vee + 0.5 V) ................................................. ±35mA
DC Vee OR GROUND CURRENT (lee) .................................................................................... ±70mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60°C (PACKAGE TYPE E) ........................................................................... 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) ............................................. Derate Linearly at 8 mW/oC to 300 mW
For T A = -55 to +1 OO°C (PACKAGE TYPE F, H) ................... , ................................................... 500 mW
For TA = +100 to +125°C (PACKAGE TYPE F, H) ......................................... Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) .......................................................................... 400 mW
For TA
= +70 to +125°C (PACKAGE TYPE M) ............................................. Derate Linearly at 6 mWfOC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .......................................................................................... -55 to +125°C
PACKAGE TYPE E, M .......................................................................................... -40 to +85°C
. STORAGE TEMPERATURE (T,lg) ................................................................................. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ..................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in .. 1.59 mm)
with solder contacting lead tips only .................................................................................. +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For T. = Full Package-Temperature Range) Vee:'
CD54/74HC Types
CD54174HCT Types
DC Input or Output Voltage V" Vo
Operating Temperature T A :
CD74 Types
CD54 Types
Input Rise and Fall Times t" tf
at 2 V
at 4.5 V
at6V
UNITS
MIN.
MAX.
2
4.5
6
5.5
V
0
Vee
V
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
'Unless otherwise specified, all voltages.are referenced to Ground.
10E
1A
14
Vee
13
1<
12
40E
4A
20E
2A
"10
2Y
4Y
30E
3A
3Y
GND
9CS-38301
TERMINAL ASSIGNMENT
161
Technical Data __________________________________
CD54/74HC126
CD54/74HCT126
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT126/CD54HCT126
CD74HC126/CD54HC126 '
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPE
TYPE
CONDITIONS
TYPES
TYPE
TYPE
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
CHARACTERISTIC
UNITS
V,
10
Vee
V
mA
V
+25°C
V,
Vee
V
V
Min Typ Max Min Max Min Max
Min Typ Max Min Max Min Max
High-Level
Input Voltage
V,H
Low-Level
Input Voltage
V,L
High-Level
Output Voltage
1,5
-
-
1.5
4.5 3.15
-
-
-
-
2
V,L
VOH
CMOS Loads
or
-0.02
V,H
6
4.2
-
1.5
-
3.15
-
3.15
-
4.2
-
4.2
-
or
-6
(Bus Driver)
V,H
-7.B
Output Voltage
V,L
VOL
CMOS Loads
or
-
2
-
-
0.5
-
0.5
-
0.5
-
-
1.35
-
1".35
-
1.35
0.02
V,H
6
-
-
I.B
-
I.B
-
I.B
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,H
4.5 3.9B
-
-
3.B4
-
3.7
-
or
6
5.48
-
-
5.34
-
5.2
-
V,H
2
-
-
0.1
-
0.1
-
0.1
V,L
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,H
V,L
O.B
-
O.B
4.4
-
-
4.4
-
4.4
-
V
4.5 3.9B
-
-
3.B4
-
3.7
-
V
'V
4.5
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
/lA
5.5
-
-
8
-
80
-
180
/lA
Vee -2.1
4.5
to
5.5
-
100 360
-
450
-
490
/lA
V,L
or
V,H
5.5
-
-
-
±5
-
±10
/lA
V,L
0.4
or
(Bus Driver)
V,H
7.B
6
-
-
0.26
-
0.33
-
0.4
V,H
Input Leakage
Vee
Any
Voltage
or
6
-
-
±0.1
-
±1
-
±1
6
-
-
8
-
80
-
180
Gnd
Between
Vee
and
Gnd
Vee
0
Gnd
or
Gnd
Additional
Quiescent
Device Current
per input pin:
1 unit load
dlee
loz
-
-
-
V,L
or
V,H
O.B
0.1
0.33
3-State
Leakage
Current
-
to
-
-
iee
-
V
0.1
0.26
Current
-
-
-
or
2
-
-
Vee
-
4.5
4.5
Quiescent
2
V,L
6
Device
-
5.5
or
I,
-
4.5
-
TTL Loads
Current
2
to
5.5
V,L
TTL Loads
Low-Level
4.5
4.5
V,L
+25°C
Vo=Vcc
or
Gnd
6
-
-
• For dual-supply systems theoretical worst case (V,
±0.5
=
-
±5
2.4 V, Vee
=
-
±10
±0.5
5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
'Unit Load is Alec limit specified in Static Characteristics
Chart, e.g., 360llA max. @ 25°C.
162 ____________________________________________________________
Technical Data
CD54/74HC126
CD54/74HCT126
SWITCHING CHARACTERISTICS (Vcc=5 V, TA=25°C, Inpul I" 1,=6 ns)
TYPICAL
CL
CHARACTERISTIC
pF
SYMBOL
Propagation Delay
Data to Outputs
HCT
HC
15
t PHL ,
tpLH
8
9
Output Enabling Time
15
t pZL ,
tPZH
10
10
Output Disabling Time
15
t plZ ,
tpHZ
10
11
30
36
Power Dissipation Capacitance'
-
Cpo
UNITS
ns
pF
'CPO is used to determine the dynamic power consumption, per multiplexer.
Po=Vcc ' fi (Cpo+Cc) where: fi=input frequency
C L =Ioad capacitance
Vcc=supply voltage
SWITCHING CHARACTERISTICS (C L =50 pF, Inpul I" 1,=6 ns)
25°C
CHARACTERISTIC
SYMBOL
HCT
HC
Vee
-40°C 10 +85°C
-55°C 10 +125°C
74HC
54HC
74HCT
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay
Data to Outputs
tPLH
t PHL
Enable Delay
Times
t PZH
Disable
Delay Times
t PHZ
t PLZ
Output Transition
Time
t PZL
hLH
hHL
2
4.5
6
2
4.5
6
-
-
-
2
4.5
6
-
2
4.5
6
-
-
-
100
20
17
-
-
-
-
24
-
-
-
-
125
25
21
-
-
-
-
25
-
-
-
-
-
-
-
-
28
-
-
-
-
60
12
10
-
-
-
12
-
-
-
-
125
25
21
125
25
21
-
-
-
-
30
-
-
-
-
155
31
26
-
-
-
-
31
-
-
-
-
155
31
26
-
-
-
-
35
-
-
-
-
75
15
13
-
-
-
-
15
-
-
-
-
150
30
36
-
-
-
36
-
-
190
38
32
-
-
-
38
-
-
190
38
32
-
-
-
42
-
-
90
18
15
-
-
-
18
-
-
Input Capacitance
C,
-
-
10
-
10
-
10
-
10
-
10
-
10
3-State Output
Capacitance
Co
-
-
20
-
20
-
20
-
20
-
20
-
20
ns
pF
li'r=6ns
'f=6~SI
tr= 6 n s
-=-'=VS
OUTPUT
ENABLE
1f = 6ns
IN PUT --t--,I<-==~""
LEVEL
90%
----'10%
nA~~~of"l
OUTPUT
LOW TO OF_F-+~~,:,
92CS·3B531RI
92'CS-39801
54174HC
Input Level
Switching Voltage, Vs
Fig. 2 -
54174HCT
Vee
3V
50% Vee
1.3 V
Transition and propagation delay times.
_______________________________ 163
Technical Data __________________________________________________________
CD54/74HC126
CD54/74HCT126
OTHER
INPUTS
(tIld
!,:91~W)
OUTPUT
DISABLE
~
Ie WITH
OUTPUT RL -Ikn
3-STATE t-",---,\M.--Q
OUTPUT
CL
{v.CC for
and t
t
PLZ
PZL
GND for 'PHZ and 'PZH
ISOPF
92CS-35130R2
Fig. 3 - Three-state propagation delay test circuit.
164 _______________________________________________________________________
Technical Data
File Number
CD54/74HC132
CD54/74HCT132
1649
High-Speed CMOS Logic
Quad 2-lnput NAND Schmitt Trigger
Type Features:
• Unlimited input rise and fall times
• Exceptionally high noise immunity
FUNCTIONAL DIAGRAM AND
TERMINAL ASSIGNMENT
The RCA-CD54/74HC132 and CD54174HCT132 each contain four 2-input NAND Schmitt Triggers in one package.
The CD54HC132 and CD54HCT132 are supplied in 14-lead
ceramic dual-in-line packages (F suffix). The CD74HC132
and CD74HCT132 are supplied in 14-lead dual-in-line
plastic packages (E suffix) and in 14-lead dual-in-line
surface mount plastic packages (M suffix). Both devices are
also available in chip form (H suffix).
nY
LOGIC DIAGRAM
va
92CS-38465RI
Family Features:
• Fanout (Ovel Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source IS Philips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity:
NIL = 37%, MH = 51% of Vee: @ Vee = 5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
VIL = 0.8 V Max., V'H = 2 V Min.
CMOS Input Compatibility
I, S 1 /lA @ VOL, VO H
L-_+_+__ VI
TRUTH TABLE
INPUTS
OUTPUTS
nA
nB
nY
L
L
H
L
H
H
H
L
H
H
H
L
H ~ High level
L ~ Low level
92CM - 38466
Fig. 1 - Hysteresis definition, characteristic, and test setup.
_______________________________________________________________________ 165
Technical Data
CD54/74HC132
CD54/74HCT132
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) .
DC INPUT DIODE CURRENT, I,K (FOR V,
. .......... .
< -0.5 V OR V, > Vee +0.5V)
DC OUTPUT DIODE CURRENT, 10K (FOR V o < -0.5 V OR V o > Vee +0.5V)
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -05 V < Vo < Vee + 0.5V)
DC Vee OR GROUND CURRENT (Iee) ............................. " ........... .
POWER DISSIPATION PER PACKAGE (Po):
For T A = -40 to +60°C (PACKAGE TYPE E)
For TA = +60 to +85°C (PACKAGE TYPE E) .
For TA = -55 to +100° C (PACKAGE TYPE F. H)
For TA = ~100 to -125°C (pACKAGE TYPE F. H)
ForTA = -40 to +70°C (PACKAGE TYPE M) ....................... .
For T A = +70 to +125°C (PACKAGE TYPE M)
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .
PACKAGE TYPE E, M
. -0.5 to + 7 V
±20mA
±20mA
±25mA
. .................................... ±50mA
......... 500 mW
Derate Linearly at 8 mW/O C to 300 mW
.............. 500
Derate Linearly at 8 mWI' C to 300
.................................. 400
Derate Linearly at 6 mW;o C to 70
mW
mW
mW
mW
............ -55 to .,.125'C
.. ..... -40 to +85° C
STORAGE TEMPERATURE (T",)
LEAD TEMPERATURE (DURING SOLDERING):
..... -65 to +150°C
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in .. 1.59 mm)
with solder contacting lead tiPS only
. +265°C
...... +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA - Full Package-Toc''1perature Range) Vee:'
CD54/74HC Types
CD54174HCT Types
DC Input or Output Voltage V" Vo
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times to, I,
at 2 V
at 4.5 V
at 6 V
LIMITS
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
V
V
V
-40
-55
+85
+125
°C
°C
0
0
0
Unlimited
Unlimited
Unlimited
ns
ns
ns
'Unless otherwise specified, all voltages are referenced to Ground.
166 _________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC132
CD54/74HCT132
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT132/CD54HCT132
CD74HC132/CD54HC132
CHARACTERISTIC
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCli
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
T':PE
TYPo
TYPE
-401
-551
VI
Vee
+85°e
+125°C
V
V
VI
10
VCC
V
rnA
V
+
VT-
VH
High-Level Output
Voltage
CMOS Loads
-0.02
Low-Level Output
Voltage
CMOS Loads
1.5
4.5
17
3.15
17
3.15
1.7
315
45
12
19
1.2
19
12
19
6
21
4.2
21
4.2
2.1
4.2
5.5
1.4
2.1
14
2.1
.1 4
21
2
0.3
1
0.3
1
0.3
1
-
-
-
-
-
4.5
09
2.2
09
2.2
0.9
2.2
4.5
05
12
05
12
05
12
6
1.2
3
12
3
1.2
3
55
0.6
14
06
1.4
06
14
2
0.2
1
02
1
02
1
-
-
4.5
04
1.4
04
1.4
0.4
14
45
0.4
1.4
04
14
04
14
6
06
1.6
0.6
1.6
06
1.6
5.5
04
15
0.4
15
0.4
15
45
4.4
45
398
2
1.9
-
1.9
-
19
-
4.5
4.4
-
4.4
-
44
-
6
5.9
-
59
-
59
-
VT
-
VT
52
-
VT
-
-
-
-
-
or
6
548
2
-
0.1
-
01
-
01
VT-
002
4.5
-
01
-
0.1
-
0.1
or
6
-
01
-
0.1
-
0.1
VT
5.34
-
-
-
-
-
-
-
-
V
-
V
or
+
-
-
4.5
+
-
VT
-
or
4
45
-
0.26
-
033
-
0.4
or
VT+
5.2
6
-
0.26
-
0.33
-
0.4
VT
44
4.4
V
+
-5.2
-
37
384
-
V
VT-
VT+
VTTTL Loads
-
398
-
Max
Max
0.7
4.5
VT
Min
Min
15
-4
VT
Max
Max
07
or
or
VOL
Min
Min
15
VT+
VT-
TTL Loads
Max
Max
VT
or
VOH
+125°C
0.7
2
VT
Min
~NITS
-551
+85°e
+25°e
Min
Input SWitch
POints
+25°C
-401
45
-
+
-
384
-
-
-
-
01
--
-
-
-
-
026
3.7
-
-
-
-
0.1
-
V
-
-
01
-
-
V
-
-
-
033
-
04
V
-
-
Any
Input Leakage
Voltage
Vee
Current
'I
or
6
-
-+:01
±1
-
-
±1
Between
Gnd
Vee and
Vee
Vee
55
-
• 0.1
-
=,
-
~
1
fJA
55
-
2
-
20
-
40
fJA
-
450
-
490
fJA
Gnd
Quiescent
Device
Current
or
lee
0
6
-
2
20
-
-
40
or
Gnd
Gnd
Min
AdditlonalOules
yp Max
cent Device
45
Current per
Input Pin"
Vee- 21
1 Unit Load ~ICC'
to
-
100 360
55
*For dual-supply systems theoretical worst case (VI:' 2.4 V.
Vee
=
5.5 V) specification
IS
1 8 mA
HCT INPUT LOADING TABLE
INPUT
nA,nB
UNIT LOADS'
0.6
'Unit load is l>lcc limit specified in Static Characteristic
Chart, e.g., 360 fJA max. @ 25 0 C.
___________________________________________________________________ 167
Technical Data
CD54/74HC132
CD54/74HCT132
SWITCHING CHARACTERISTICS (Vee ~ 5 V, T A ~ 25° C, Inpull" I. = 6 ns)
CL
(pF)
CHARACTERISTIC
Propagation Delay
t pLH
A, BtoY
t PHL
Power Dissipation Capacitance
CPD
TYPICAL
HCT
HC
UNITS
15
10
13
ns
-
30
30
pF
.
·C PO is used to determine the dynamic power consumption, per gate.
Po ~VCC2 f, (Cpo + Cd where:
f, = input frequency
C L = output load capacitance
Vee = supply voltage
SWITCHING CHARACTERISTICS (CL ~ 50 pF, Inpullr,11 = 6 ns)
CHARACTERISTIC
Propagation Delay
A, B to Y
Output
Transition Time
Input Capacitance
t PLH
t pHl
hLH
hHL
C,
TEST
CONDITIONS
VCC (V)
2
4.5
6
2
4.5
6
-
_40° C to +85° C
_55° C 10 +125° C
+25°C
HC
HCT
74HC
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
125 188 156 25
31
41
33
38
50
ns
21
27
32
110 75
95
19
19
15
15
22
22
ns
13
16
19
10
10
10
10
10
10
pF
INPUT
LEVEL
90%
OUTPUT
90%
Vs
Vs
10%
10%
92CS-3694BRI
Fig. 2 - Transition times and propagation delay times.
168 _______________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
File Number
CD54/74HC138, CD54/74HCT138
CD54/74HC238, CD54/74HCT238
1477
High-Speed CMOS Logic
AO
A1
A2
;IT
E2
E3
2
3
4
5
HC/HCT HC/HCT
238
138
15
YO
YO
14
Y1
Y1
13
Y2
Yo
12
Y3
Y:i
11
Yo
Y4
10
Y5
Ys
Y6
Y6
Y7
Y'i
3-to-8 Line Decoder/Demultiplexer
Inverting and Non-Inverting
Type Features:
• Select one of eight data output [active LOW for 138,
active HIGH for 238]
• I/O port or memory selector
• 3 Enable Inputs to simplify cascading
• Typical propagation delay of 13ns @ Vee = 5 V, C L = 15 pF, TA = +25 0 C
FUNCTIONAL DIAGRAM
The RCA-CD54/74HC138,238 and CD54174HCT138,238
are high speed silicon gate CMOS decoders well suited to
memory address decoding or data routing applications.
Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable
to low power Schottky TTL logic. Both circuits have 3
binary select inputs (Ao, A" and A2). If the device is enabled
these inputs determine which one of the eight normally high
outputs of the HC/HCT138 series will go low or which of
the normally low outputs of the HC/HCT238 series will go
high.
Two active low and one active high enables (E"" E2, and E3 )
are provided to ease the cascadi ng of decoders. The decoder's outputs can drive 10 low power Schottky TTL equivalent loads.
The CD54HC138,238 and CD54HCT138,238 are supplied in
16-lead hermetic dual-in-line ceramic packages (F suffix).
The CD74HC138,238 and CD74HCT138,238 are supplied in
16-lead dual-in-line plastic packages (E suffix) and in 16lead dual-in-line surface mount plastic packages (M suffix).
Both types are also available in chip form (H suffix).
Family Features:
• Fanout [Over Temperature Range]:
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCTr -40 to +85 0 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity: N,L = 30%, N ,H =30% of Vee
@ Vee=5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L =0.8 V Max., V,H =2 V Min.
CMOS Input Compatibility
I, ~ 1 pA @ VOL, V OH
92CS- 369 12
Fig. 1 - Logic Diagram for HC/HCT 138
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 169
Technical Data
CD54/74HC138, CD54/74HCT138
CD54/74HC238, CD54/74HCT238
Fig. 2 -
Logic Diagram for HC/HCT 238
TRUTH TABLE
CD54/74HC138, CD54/74HCT138
INPUTS
ENABLE
I ADDRESS
E3
A1
AO
E2
E1 I A2
X
L
X
H
H
H
H
H
H
H
H
H
=
X
X
H
L
L
L
L
L
L
L
L
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
High level, L
= low
OUTPUTS
YO
Y1
Y2
Y3
Y4
YS
Y6
Y7
X
X
X
X
H
H
H
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
X
X
H
H
H
L
L
H
H
H
level, X
L
L
L
H
L
H
H
H
H
H
H
= don't care
TRUTH TABLE
CD54/74HC238, CD54174HCT238
INPUTS
ENABLE
ADDRESS
E3
E2
E1
Al
AO,
A2
I
I
X
L
X
H
H
H
H
H
H
H
H
H
X
X
H
X
H
L
L
L
L
L
L
L
L
X
= High
L
L
L
L
L
L
L
L
level, L
X
X
X
L
L
L
L
H
H
H
H
= low
X
X
X
X
X
X
L
L
H
H
H
L
L
H
H
level, X
L
L
H
L
H
L
H
OUTPUTS
YO
Y1
Y2
Y3
Y4
YS
Y6
Y7
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
l,
L
H
L
L
L
L
L
H
L
L
L
L
L
L
H
L
H
= don't care
170 _______________________________________________________________________
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - Technical nata
CD54/74HC138, CD54/74HCT138
CD54/74HC238, CD54/74HCT238
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground)
DC INPUT DIODE CURRENT. I" (FOR V,
-0.5 to + 7 V
±20mA
±20mA
±25mA
........... .
V, > Vee +0.5V)
< -0.5 V OR
DC OUTPUT DIODE CURRENT, 10' (FOR V, < -0.5 V OR V, > Vee +0.5V)
DC DRAIN CURRENT, PER OUTPUT (I,) (FOR -0.5 V < V, < Vee + 0.5V)
DC Vee OR GROUND CURRENT (Icc)
POWER DISSIPATION PER PACKAGE (Po)
For TA 0 -40 to +60'C (PACKAGE TYPE E)
For TA 0 +60 to +B5'C (PACKAGE TYPE E)
For TA 0 -55 to +100'C (PACKAGE TYPE F, H)
For TA
0
±50mA
..... 500 mW
Derate Linearly at 8 mWI'C to 300 mW
... 500 mW
Derate Linearly at 8 mWI'C to 300 mW
+100 to +125'C (PACKAGE TYPE F, H)
For TA ; -40 to +70'C (PACKAGE TYPE M) .......................................................................... 400 mW
For T.; +70 to +125'C (PACKAGE TYPE M) ............................................. Derate Linearly at 6 mW/'C to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F. H
.................................. .
PACKAGE TYPE E, M
-55 to +125'C
-40 to +85'C
STORAGE TEMPERATURE (T",)
LEAD TEMPERATURE (DURING SOLDERING)
At distance 1/16 ± 1/32 in. (1 59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only
-65 to +150'C
+265'C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
MIN.
MAX.
UNITS
Supply-Voltage Range (For TA = Full Package Temperature Range) Vee:'
2
6
V
CD54/74HCT Types
4.5
5.5
V
DC Input or Output Voltage V", V,"'
0
Vee
V
CD54174HC Types
Operating Temperature TA:
CD74 Types
-40
+85
'C
CD54 Types
-55
+125
'C
Input Rise and Fall Times t" t,
at 2 V
0
1000
ns
at 4.5 V
0
500
ns
at 6 V
0
400
ns
'Unless otherwise specified, all voltages are referenced to Ground.
AD
A'
A2
EJ
16 Vee
IS
Yo
14
Y,
13
Y2
12
J3
11
Y4
10 ~
GNO
9
Y6
92C5 J6!J04
TERMINAL ASSIGNMENT FOR HC/HCT138
FOR HC/HCT238 ALL Y'. ARE Y'.
_______________________________________________________________________ 171
Technical Data
CD54/74HC138, CD54/74HCT138
CD54/74HC238, CD54/74HCT238
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT138/238, CD54HCT138/238
CD74HC138/238, CD54HC138/238
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-40/
-55/
-40/
-55/
+85°C
+125° C
+85°C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
V
10
rnA
Vee
V
Min
High-Level
Input Voltage
V,"
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
VOH
CMOS Loads
or
-002
V,"
Low-Level
Output Voltage
2
1.5
-
-
1.5
-
15
-
4.5
315
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
CMOS Loads
4.5
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
45
44
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
Current
-
384
-
37
-
or
V,"
-5.2
6
548
-
-
5.2
-
V"'
002
-
5.34
2
-
-
01
-
0.1
-
0.1
4.5
-
-
01
-
0.1
-
0.1
or
6
-
-
01
-
0.1
-
01
V,"
-
08
4.5
4.4
-
-
4.4
-
4.5
398
-
-
3.84
45
-
-
0.1
45
-
-
5.5
-
5.5
-
2
-
V
to
0.8
V
4.4
-
V
-
37
-
V
-
01
-
01
V
0.26
-
0.33
-
0.4
V
-
±O 1
-
±1
-
±1
JJA
-
8
-
80
-
160
JJA
360
-
450
-
490
JJA
-
0.8
-
4.5
-
-
0.26
-
0.33
-
0.4
6
-
-
0.26
-
033
-
0.4
V,"
±1
Any
Voltage
Between
V"
V"
4
5.2
Vee
I,
-
V"
-
V"'
-
2
V,.
V"
Input Leakage
-
5.5
3.98
or
-
4.5
-
4.5
or
2
to
5.5
-4
V,"
TTL Loads
Min Typ Max Min Max Min Max
or
V"
VOl
Vee
V
Typ Max Min Max Min Max
V"
TTL Loads
+25°C
V,
V
or
6
-
-
:to. 1
-
±1
-
or
Vee
& Gnd
Gnd
Quiescent
Vee
Device
or
Current
Icc
Vee
0
6
-
-
8
-
80
-
160
or
Gnd
Gnd
Additional
Quiescent
Device Current
per input pin:
1 unit load
bloo
4.5
Vcc- 2.1
to
-
100
5.5
*For dual-supply systems theoretical worst case (VI = 2.4 V, Vee
=5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
Unit Loads'
AO-A2
1.5
1.25
1
E1,E2
E3
'Unit Load IS Alec limit specified in Static Characteristic Chart,
e.g .. 360 JJA max. @ 25° C.
172 ___________________________________________________________________
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - T e c h n i c a l Data
CD54/74HC138, CD54/74HCT138
CD54/74HC238, CD54/74HCT238
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25° C, CL = 15 pF, Inpull" I, = 6 ns)
Typical
CHARACTERISTIC
SYMBOL
Propagation Delay, Address to Output Y (C L =15 pF)
tPLH
tPHL
13
14
ns
·C po
67
67
pF
(Fig. 3)
Power Dissipation Capacitance'
Unit
HCT
HC
·CPO is used to determine the dymanic power consumption, per package,
PD=Vcc 2 1, (Cpo + Cd where I, - input frequency
CL
Vee
output load capacitance
supply voltage
SWITCHING CHARACTERISTICS (Cl = 50 pF, Input tr,11 = 6 ns)
CHARACTERISTIC
Propagation Delay
tpLH
Address to Output
tpHL
(Fig. 3)
Propagation Delay,
t PLH
Enable to Output
tpHL
(Fig, 3) HC/HCT138
Propagation Delay
t PLH
Enable to Output
tpHL
(Fig.4) HC/HCT238
Output
hLH
Transition Times
trHL
Input Capacitance
C,
TEST
CONDITIONS
VCC (V)
2
4,5
6
2
4.5
6
2
4,5
6
2
4.5
6
-
-55 0 C to +125 0 C
-40 0 C to +85 0 C
+25°C
74HCT
54HC
54HCT
UNITS
74HC
HC
HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
190 225 150 44
45
53
ns
38
30
35
38
33
26
190 225 150 44
53
ns
38
45
30
35
38
33
26
265 175 220 44
50
53
60
ns
35
40
45
37
30
110 95
75
22
19
22
ns
15
15
19
16
19
13
10
10
10
pF
10
10
10
tf = 6 ns
-
INPUT
-- -
-
-
-
90%
- - - - - - - Vs
.....-_-_-_-_-__ _'O_o_~o_ GND
EI, E2
E3
----90%
138
OUTPUT
10%
-
90%
238
OUTPUT
_ _ _ 10"/0
92CS- :57197
92CS-36974
Fig. 3 -
Transition times and propagation delay times.
INPUT LEVEL
Fig. 4 -
I
I
I
Transition times an? propagation de/ay times.
I
INPUT LEVEL
Vs
-
I
I
S4/74HC
S4/74HCT
Vee
3V
50% Vee
1.3V
I
I
J
173
Technical Data
CD54/74HC139
CD54/74HCT139
File Number
1545
High-Speed CMOS logic
Dual 2-to-4 line Decoder/Demultiplexer
AO
2 (14)
~yo
A I
3(13)
~Yi
Type Features:
~Y2
•
~Y3
•
E
I (IS)
92CS-37881RI
FUNCTIONAL DIAGRAM
Multifunction Capability
Binary to l-of-4 Decoders or
l-to-4 Line Demultiplexer
Active Low Mutually Exclusive Outputs
Applications:
•
•
•
Memory Decoding
Data Routing
Code Conversion
The RCA-CD54174HC139 and CD54174HCT139 contain
two independent binary to one-of-four decoders each
with a single active low enable input (iE, or 2E). Data on
the select inputs (1AO and 1A1 or 2AO and 2A1) cause one
of the four normally high outputs to go low.
If the enable input is high all four outputs remain high.
For demultiplexer operation the enable input is the data
input. The enable input also functions as a chip select
when these devices are cascaded. This device is
functionally the same as the CD4556B and is pin compatible
with it.
The outputs of these devices can drive 10 low power
Schottky TTL equivalent loads. The 54174HCT logic
family is functionally as well as pin equivalent to the
54174LS logic family.
The CD54HC139 and CD54HCT139 are supplied in 16lead hermetic dual-in-line ceramic packages (F suffix).
The CD74HC139 and CD74HCT139 are supplied in 16lead dual-in-line plastic packages (E suffix) and in 16-lead
dual-in-line surface-mount plastic packages (M suffix).
Both types are also available in chip form (H suffix).
r-----~~~I-'-~'-~
A 0 r'L-"","--"-'-< ~~
Family Features:
•
•
•
•
•
•
•
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85 0 C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
Alternate Source is Philips/Signetics
CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity: ML = 30%, N'H = 30% of Vee
@ Vee = 5 V
CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibilitv
I, S 1 JJA @ VOL, V OH
TRUTH TABLE
___f>yo
A I
1 (15)
E
92CS-37880
Fig. 1 - Logic diagram for the CD54/74HC/HCT139.
Inputs
Enable Select
Outputs
-Y3
-Y2
0
1
1
1
1
0
0
1
1
X
E
A1
AO
0
0
0
0
0
X = Don't Care
--
--
Y1
YO
1
1
0
1
0
1
1
0
1
1
1
0
1
1
1
X
1
1
1
1
Logic 1 = High
Logic 0 = Low
174 ______________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC139
CD54/74HCT139 .
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
...................... -0.5 to +7 V
(Voltages referenced to ground) ........................................................... .
. ...... ±20 mA
DC INPUT DIODE CURRENT, I,. (FOR V, < -05 V OR V, > Vee +0.5 V) ......................... .
....... ±20 mA
DC OUTPUT DIODE CURRENT, 10 • (FOR Vo < -0.5 V OR Vo > Vee +0.5 V). . . .
. . . . . . . . . ... . .......... .
.. ±25 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V)....
. .......... .
±50 mA
DC Vee OR GROUND CURRENT, (Icc): ............ , .................... .
POWER DISSIPATION PER PACKAGE (Po):
ForT. = -40 to +60°C (PACKAGE TYPE E) ......
. .. ,.,"",.,
. 500 mW
For T. = +60 to +85°C (PACKAGE TYPE E) .. ,. . .
,,,,,,.,,......
. .. , Derate Linearly at 8 mwrc to 300 mW
ForT. = -55 to +1OO°C (PACKAGE TYPE F, H)."
" ...... , . . . . . . . . . , .. ,.500 mW
ForT. = +100 to +125°C (PACKAGE TYPE F, H) .. " .. , ..... ,.,',.,.,..
, .......... " .... Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) ., ........................................................................... 400 mW
For TA = +70 to +125°C (PACKAGE TYPE M) ................................................ Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (T .):
.... -55 to +125°C
PACKAGE TYPE F. H . . . . . . . . . . .
. .... , .............. .
.., .. -40 to +85°C
PACKAGE TYPE E, M .................................... .
, .... -65 to +150° C
STORAGE TEMPERATURE (T",) ........... .
LEAD TEMPERATURE (DURING SOLDERING) :
+265°C
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in .. 1.59 mm)
'300°C
with solder contacting lead tips only
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within the
following ranges:
LIMITS
UNITS
CHARACTERISTIC
MIN.
MAX.
Supply-Voltage Range (For TA = Full Package Temperature Range) Vee:'
CD54174HC Types
2
6
V
CD54174HCT Types
4.5
5.5
V
a
Vcc
V
DC Input or Oulpul Vollage V" Vo
Operaling Temperalure T A:
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
a
a
1000
ns
a14.5 V
500
ns
al6 V
0
400
ns
Inpul Rise and Fall Times, I" I,
al2 V
'Unless otherwise specified, all voltages are referenced to Ground.'
IE
1
1AO
m
m
m
GND
Vee
15
2E
14 2AO
1A1
iYO
16
4
13 2Al
12
2Yci
11
m
10
m
9
2Y3
TERMINAL ASSIGNMENT
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 175
Technical Data
CD54/74HC139
CD54/74HCT139
STATIC ELECTRICAL CHARACTERISTICS
CD74HC139/CD54HC139
CD74HCT139/CD54HCT139
TEST
74HC/54HC
74HC
54HC
TEST
74HCT154HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
V
10
mA
V"
V
Min
High-Level
Input Voltage
4.5
V"
High-Level
V"
Output Voltage
or
VO "
CMOS Loads
-0.02
4.5
V,"
1.5
1.5
1.5
4.5
3.15
3.15
10
4.2
4.2'
4.2
5.5
05
0.5
0.5
1 35
1.35
1.35
to
18
1.8
1.8
5.5
Low-Level
Output Voltage
1.9
1.9
1.9
V"
4.4
4.4
or
59
5.9
5.9
V,"
3.98
3.84
3.7
or
548
5.34
5.2
V,"
-4
V,"
-5.2
CMOS Loads
or
4.5
0.02
4.5
V,"
0.1
0.1
0.1
V"
0.1
0.1
0.1
or
0.1
0.1
0.1
V,"
026
0.33
0.4
or
V,"
Input Leakage
Vee
Current
or
4.5
5.2
or
0.26
0.33
0.4
V,"
-
:1::0.1
±1
±1
Any
Voltage
Between
Vee
Device
or
Current
Icc
4.4
4.5
3.98
4.4
V
4.4
V
-
4.5
-
3.84
-
3.7
V
0.1
0.1
0.1
V
4.5
-
0.26
5.5
-
::!:0.1
-
0.4
V
±1
±1
fJA
80
160
IJA
490
fJA
0.33
-
Vee
& Gnd
Gnd
Quiescent
4.5
0.8
V"
V"
TTL Loads
0.8
0.8
V"
or
V"
Voc
V
4.5
4.4
V"
TTL Loads
Min Typ Max Min Max Min Max
3.15
4.5
V"
Vee
V
Typ Max Min Max Min Max
Low-Level
Input Voltage
+25°C
V,
V
Vee
80
0
160
or
5.5
Gnd
Gnd
4.5
Additional
Quiescent
Device Current
per input pin'
1 unit load
6. Icc
Vcc-2.1
to
100
360
450
-
55
*For dual-supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
Unit Loads'
All
0.7
·Unit Load is .6.lcc limit specified in Static Characteristic Chart,
e.g., 360,uA max. @ 25° C.
176 ___________________________________________________________________
_______________________________ Technical Data
CD54/74HC139
CD54/74HCT139
SWITCHING CHARACTERISTICS (Vee
=5 V, TA =25°C, Inpul I" If =6 ns)
ryplcal
CL
(pF)
CHARACTERISTIC
SYMBOL
Propagation Delay
UNITS
54174HC
54174HCT
12
14
t pHl
15
Select to Output
ns
t pLH
Enable to Output
15
-
Power Dissipation Capacitance'
Cpo
11
14
ns
55
59
pF
·C PD is used to determine the dynamic power consumption, per decoder/demux.
PD = Vee' f, (C PD + Cc) where:
fl = input frequency
C L = output load capacitance.
Vee = supply voltage.
SWITCHING CHARACTERISTICS (C L = 50 pF, Inpul I" If = 6 nl)
CHARACTERISTIC
SYMBOL
HC
Vee
_55° C 10 +125° C
-40° C 10 +85° C
25°C
74HC
HCT
54HC
74HCT
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay
AO, A1 to Outputs
-E to Outputs
Output Transition
Time
t pLH
2
-
145
-
-
-
180
-
-
-
220
-
-
t PHL
4.5
-
29
-
34
-
36
-
43
-
44
-
51
6
-
25
-
-
-
31
-
-
-
38
-
-
t PLH
2
-
135
-
-
-
170
-
-
-
205
-
-
tpHL
4.5
-
27
-
34
-
34
-
43
-
41
-
51
6
-
23
-
-
-
29
-
-
-
35
-
-
2
-
75
-
-
-
95
-
-
-
110
-
-
19
-
19
-
22
-
22
19
-
-
10
-
10
hLH
trHL
4.5
6
Input Capacitance
C,
-
15
-
15
-
-
13
-
-
-
16
-
-
-
-
10
-
10
-
10
-
10
-
ns
ns
ns
pF
____________________________________________________ 177
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--,-_
CD54/74HC139
CD54/74HCT139
92CS-36972R2
92CS-37B82
Transition times and propagation delay times.
Input Level
Switching Voltage, V.
54/74HC
54/74HCT
Vee
3V
50% Vee
1.3 V
178 ___________________________________________________________
--------------------------------------------------------------TechnicaIData
File Number
CD54/74HC147
CD54/74HCT147
1773
High-Speed CMOS Logic
11
i2
13
11
12
9
13
16
i7
is
i9
10-to-4-Line Priority Encoder
Vi
14
is
Yo
2
3
Type Features:
6
Y2
14
Y3
4
5
10
• Buffered inputs and outputs
• Typical CD54174HC147 propagation delay = 13ns
@ Vcc=5 V, C L =15 pF, TA=25°C
Vcc= 16
GND= 8
92C5-39631
FUNCTIONAL DIAGRAM
The RCA-CD54/74HC147 and CD54174HCT147 are highspeed silicon-gate CMOS devices and are pin-compatible
with low power Schottky TTL (LSTTL).
The CD54/74HC147 and CD54174HCT147 9-input priority
encoders accept data from nine active LOW inputs (I; to 1;,)
and provide binary representation on the four active LOW
outputs (Yo to Y3). A priority is assigned to each input so that
when two or more inputs are simultaneously active, the
input with the highest priority is represented on the output,
with input line 1;; having the highest priority.
These devices provide the 10-line to 4-line priority encoding function by use of the implied decimal "zero". The
"zero" is encoded when all nine data inputs are HIGH,
forcing all four outputs HIGH.
The CD54HC/HCT147 are supplied in 16-lead hermetic
dual-in-line ceramic packages (F suffix). The CD74HCI
HCT147 are supplied in 16-lead dual-in-line plastic packages (E suffix) and in 16-lead dual-in-line surface-mount
plastic packages (M suffix). Both types are also available in
chip form (H suffix).
i4
is
is
i7
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCTIHCU: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity: N,L = 30%, N,H = 30% of Vee,
@ Vee = 5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility I, ::; lilA @ VOL, VOH
16
2
15
3
14
4
13
is
5
12
Y2
Vi
6
11
GND
Vcc
NC
Y3
i3
12
11
10
8
9
19
Yo
92C5-39830
TERMINAL ASSIGNMENT
___________________________________________________________________ 179
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC147
CD54/74HCT147
92CM- 39833
Fig. 1 - Logic Diagram
TRUTH TABLE
Inputs
I2
I3
I4
I5
I6
I7
I8
I9
V3
V2
V,
Vo
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
L
H
Outputs
I,
L
H
L
H
H
L
H
H
H
L
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
= High Logic Level, L = Low Logic Level, X = Irrelevant.
180 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T e c h n i c a J Data
CD54/74HC147
CD54/74HCT147
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) " .. ,.
. .. , ,.. . .. ...
. ..... ,' ...
.., -0.5 to +7 V
DC INPUT DIODE CURRENT, 1,K (FOR V, <-0.5 V OR V, > Vee + 0.5 V) ....
. .. ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Va < -0.5 V OR Va> Vee +0.5 V)
... ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5V < Va < Vee + 0.5 V)
. ± 25mA
DC Vee OR GROUND CURRENT (Icc) ............. , , ... .
. , .. ±50mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60°C (PACKAGE TYPE E) .................... .
For TA = +60 to +85°C (PACKAGE TYPE E) ,......
.,.500 mW
..".,.,", .. ,'"
For TA = -55 to +100°C (PACKAGE TYPE F, H) ....... ,......
.".,' Derate Linearly at 8 mW;oC to 300 mW
. ....... ,...
. ... ,', ..... " ..... 500 mW
For TA = +100 to +125°C (PACKAGE TYPE F, H) ...
.... Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) " .. ".
..". ", ..... ,"" ..... " .... """.400 mW
. .... Derate Linearly at 6 mW/oC to 70 mW
For TA = +70 to +125°C (PACKAGE TYPE M) ........ .
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H ... , ......... .
....... , .. , ..... , ....................................... -55 to +125°C
PACKAGE TYPE E, M .......... ,", .. " ..................................... .
STORAGE TEMPERATURE (T"g)...
. ........................ -40 to +85°C
. ........ ,"", .....
. , ., , " -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ........ , .................. , ..
, .... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only, " ........... , , .................................................................. +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vcc:'
CD54174HC Types
CD54/74HCT Types
DC Input or Output Voltage V" Va
Operating Temperature T A:
CD74 Types
CD54 Types
Input Rise and Fall Times t., tf
at 2 V
at 4,5 V
at 6 V
UNITS
MIN.
MAX.
2
4,5
6
5.5
V
a
Vcc
V
-40
-55
+85
+125
°C
a
a
a
1000
500
400
ns
'Unless otherwise specified, all voltages are referenced to Ground.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 181
Technical D a t a - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _
CD54/74HC147
CD54/74HCT147
STATIC ELECTRICAL CHARACTERISTICS
CD74HC147/CD54HC147
CD74HCT147/CD54HCT147
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPE
TYPE
CONDITIONS
TYPES
TYPE
TYPE
-401
-551
-401
-551
+B5"C
+125"C
+B5"C
+125"C
CHARACTERISTIC
UNITS
V,
10
Vee
V
rnA
V
+25"C
V,
Vee
V
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
Low-Level
Input Voltage
V"
High-Level
Output Voltage
1.5
-
-
1.5
-
1.5
-
4.5 3.15
-
-
3.15
-
3.15
-
-
4.2
-
4.2
-
2
V,"
V"
Vo"
CMOS Loads
or
-0.02
V,"
6
4.2
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
Low-Level
Output Voltage
-4
V,"
-5.2
CMOS Loads
or
4.5
-
to
0.02
V,"
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5 3.98
-
-
3.84
-
3.7
-
or
6
5.48
-
-
5.34
-
5.2
-
V,"
2
-
-
0.1
-
0.1
-
0.1
V"
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
V"
to
4.5
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
3.7
-
V
4.5 3.98
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
/lA
5.5
-
-
8
-
80
-
160
/lA
4.5
to
5.5
-
100 360
.-
450
-
490
/lA
V"
4.5
-
-
0.26
-
0.33
-
0.4
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
Input Leakage
Vee
±1
Gnd
Any
Voltage
Between
Vee
and
Gnd
Vee
Vee
or
or
2
5.5
4
Qu iescent Device
Current
Icc
-
V"
or
I,
-
4.5
-
TTL Loads
Current
2
5.5
V"
or
V"
Voe
Min Typ Max Min Max Min Max
6
V"
TTL Loads
+25"C
6
0
6
-
-
-
-
±0.1
8
-
-
±1
80
-
-
160
or
or
Gnd
Gnd
Additional
Quiescent Device
Current per
Input Pin:
1 Unit Load
fllce
Vee -2.1
• For dual-supply systems theoretical worst case (V,
= 2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
Unit Loads'
I" 12 , 10, 16 , h
1.1
1.5
14 , Ts, TB, 19
'Unit Load is fllee limit specified in Static Characteristics
Chart, e.g., 360/lA max. @ 25°C.
182 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
- - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data.
CD54/74HC147
CD54/74HCT147
SWITCHING CHARACTERISTICS (Vcc=5 V, T A =25°C, Inpul I" 1,=6 ns)'
TYPICAL
CHARACTERISTIC
SYMBOL
Propagation Delay, Data Input to Output Y (Fig. 1)
(CL=15 pF)
tPLH
tPHL
Power Dissipation Capacitance"
Cpo
UNITS
HC
HCT
13
14
ns
32
42
pF
'CPO is used to determine the dynamic power consumption. per package.
PO=Vcc'fi (Cpo
+ Cd where fi= input frequency
CL =output toad capacitance
Vcc=supply voltage
SWITCHING CHARACTERISTICS (CL=50 pF, Inpul I" 1,=6 ns)
25°C
CHARACTERISTIC
SYMBOL
HC
Vcc
-40°C 10 +85°C
HCT
74HC
74HCT
-55°C 10 +125°C
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay,
Input to Output
(Fig. 1)
t PLH
Transition Times
(Fig. 1)
ITLH
ITHL
Input
Capacitance
tPHL
-
2
4.5
6
160
32
27
35
2
4.5
6
75
15
13
15
C,
10
-
200
40
34
44
19
-
95
19
16
10
10
-
-
240
48
41
53
22
-
110
22
19
10
10
10
-
ns
ns
pF
92CS-37974RI
Input Level
Switching Voltage, Vs
54174HC
54174HCT
Vcc
3V
50% Vcc
1.3 V
Fig. 1 - Transition times and propagation delay times.
_________________________________________________________ 183
Technical Data
CD54/74HC151
CD54/74HCT151
File Number
1645
High-Speed CMOS Logic
10
I,
8-lnput Multiplexer
I,
15
,.
I.
'3
17
12
So
"
13
I.
s,
'5
Y
Type Features:
•
•
10
Complementary data outputs
Buffered inputs and outputs
S,
Vee::: 16
GND:::
8
FUNCTIONAL DIAGRAM
The RCA CD54/74HC151 and CD54174HCT151 are single
B-channel digital multiplexers having three binary control
inputs, SO, Sland S2 and an active low enable (E) input. The
three binary signals select 1 of B channels. Outputs are both
inverting (Y) and non-inverting (Y).
The CD54HC/HCT151 devices are supplied in 16-lead
ceramic dual-in-line packages (F suffix). The CD74HCI
HCT151 are supplied in 16-lead dual-in-line plastic packages (E suffix) and in 16-lead dual-in-line surface mount
plastic packages (M suffix). Both types are also available in
chip form (H suffix).
Family Features:
•
•
•
•
•
•
•
Fanout (Over, Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85 0 C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to
LSTTL Logic ICs
Alternate Source is Philips/Signetics
CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity: N,L = 30%, N'H = 30% of Vee
@ Vee = 5 V
CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H =2 V Min.
CMOS Input Compatibility
I, ::; 1 /1A @ VOL, VO H
_7
Eo-~=Xr~.)o-rt----------h
16
vee O
8
GNOO
92CM-38434RI
184 _________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC151
,CD54/74HCT151
FUNCTION TABLE
OUTPUTS
INPUTS
E
S2
S,
So
10
I,
12
I,
14
15
16
h
-y
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
X
X
X
X
X
y
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H = HIGH voltage level.
L = LOW voltage level.
X = Don't care.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPL Y-VOLTAGE. (Vee):
..... -0.5 to +7 V
(Voltages referenced to ground) .................................. .
. ......... ±20 mA
DC INPUT DIODE CURRENT, "K (FOR V, < -0.5 V OR V, > Vee +0.5 V) .
. .. ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) ...................... .
..... ±25 mA
DC DRAIN CURRENT. PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V)
. .. ±50 mA
DC Vee OR GROUND CURRENT (Icc): ...... . .................... .
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60°C (PACKAGE TYPE E) ....
. .. 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) . . .
. ... Derate Linearly at 8 mW;o C to 300 mW
ForT. = -55 to +100°C (PACKAGE TYPE F. H)
. . . . . . . . . . . . . . .. 500 mW
ForT. = +100 to +125°C (PACKAGE TYPE F, H) ........
. .... Derate Linearly at 8 mW;oC to 300 mW
ForT. = -40 to +70°C (PACKAGE TYPE M) ...............
.............................................
400 mW
For T. = +70 to +125°C (PACKAGE TYPE M)
............................................... Derate Linearly at 6 mW;oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F. H ............... . .......................... .
PACKAGETYPEE,M ................................................ .
STORAGE TEMPERATURE (T",) ...................................... .
LEAD TEMPERATURE (DURING SOLDERING)
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................ .
. -55 to +125°C
. ... -40 to +85° C
. -65to+150°C
+265°C
+300° C
_________________________________________________________________ 185
Technical Data_'________________________________________________________
CD54/74HC151
CD54/74HCT151
STATIC ELECTRICAL CHARACTERISTICS'
CD74HC1S1/CD54HC1S1
CD74HCT1S1/CDS4HCT1S1
-.
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE.
-401
-SSI
-401
-SSI
+8SoC
+1ZSoC
+85°C
+12SoC
CHARACTERISTICS
UNITS
+2SoC
V,
10
Vee
V
mA
V
High-Level
Input Voltage
2
V"
6
4.2
2
-
4.5
-
6
High-Level
Output Voltage
V"
VO"
CMOS Loads
1.5
4.5 ;3.15
V,"
Low·Level
I nput Voltage
Min Typ M•• Min M•• Min M••
or
-0.02
V,"
2
1.9
4.5
4.4
6
5.9
-
0.5
1.35
1.8
1.5
3.15
4.2
-
0.5
1.5
3.15
4.2
-
'.35 -
-
Low-Level
Output Voltage
CMOS Loads
Quiescent Device
Current
I,
Icc
- -"1
-
2
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
~0.1
-
±1
-
±1
/1A
5.5
-
-
8
-
80
-
160
/1A
-
100 360
-
450
-
490
/1A.
to
-
1.8
1.9
-
4.4
-
or
5.9
-
V,"
5.5
4.4
5.9
-
-
-
3.84
-
3.7
-
or
V"
V"
-5.2
6
5.48
-
-
5.34
-
5.2
-
V,"
2
0.1
-
0.1
V"
0.1
-
0.1
or
0.1
-
0.1
-
0.1
6
-
-
4.5
-
0.1
0.02
0.1
V,"
0.33
0.4
or
0.33
-
0.4
V,"
Any
Voltage
Between
Vee and
Gnd
4.5 3.98
V"
or
4
4.5
-
-
0.26
V,"
5.2
6
-
-
0.26
-
6
-
-
±0.1
-
±1
-
±1
6
-
-
8
-
80
-
160
Vee
or
Gnd
Vee
or
Gnd
-
4.5
-
V,"
or
2
to
5.5
-
1.9
Min Typ M•• Min M•• Min M••
4.5
-
1.8
V"
Input Leakage
Current
V
-4
V,"
TTL Loads
V
or
V"
VOL
Vee
0.5
1.35
V"
TTL Loads
+25°C
V,
Vee
0
or
Gnd
Additional
4.5
Quiescent Device
Current per
Vee -2.1
1 Unit Load
to
5.5
Input Pin:
61cc
°For dual-supply systems theoretical worst case (V,
=2.4 V. Vee =5.5 V) specification is 1.8 mAo
HCT INPUT LOADING TABLE
INPUT
UNIT LOADS·
Select
1.5
Data
0.45
Enable
0.3
• Unit load is Alee limit specified in Static Characteristic
Chart, e.g., 360 pA max. @ 25 0 C.
186 ___________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC151
CD54/74HCT151
RECOMMENDED OPERATING CONDITIONS:
For maximum reliabillly, nominal operating conditions should be selecled so Ihal operation is always wilhin Ihe
following ranges:
LIMITS
UNITS
CHARACTERISTIC
MIN.
MAX.
Supply-Voltage Range (For TA = Full Package Temperature Range) Vee:'
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V" Vo
2
6
V
4.5
5.5
V
0
Vee
V
Operating' Temperature T A:
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
Input Rise and Fall Times, t" tt
at 2 V
0
1000
ns
at 4.5 V
0
500
ns
at 6 V
0
400
ns
'Unless otherwise specified, all voltages are referenced to Ground.
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Inpull" It = 6 ns)
TYPICAL VALUES
CHARACTERISTIC
Cl
pF
Propagation Delays
UNITS
SYMBOL
tPLl"~
54/74HC
54174HCT
14
16
ns
Any data input to Y
15
tpHL
Any data input to Y
15
tplH/tpHl
15
15
ns
Any select to Y
15
tplH/tpHl
15
17
ns
Any select to Y
15
tplH/tPHl
17
18
ns
ns
Enable to Y
15
tpLH/tpHL
11
12
Enable to Y
15
tPLHitPHL
12
15
ns
Cpo
59
58
pF
Power Dissipation Capacitance'
-
, Cpo is used to determine the dynamic power dissipation per device:
Po = Vee 2 Ii (Cpo + Cl ) where:
fi = input frequency.
Cl = output load capacitance.
Vee = supply voltage.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 187
Technical Data ___________________________________________________________
CD54/74HC151
CD54/74HCT151
SWITCHING CHARACTERISTICS (CL
= 50 pF,
Inpull" I, = 6 ns)
_40° C 10 +85° C
25°C
CHARACTERISTIC
SYMBOL
HCT
HC
Vee
74HC
-55°C 10 +125°C
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay,
Any Data Input to Y
Any Data I nput to V
2
170
t PHL
4.5
34
38
43
48
51
57
6
29
37
-
43
-
tplH
tpHL
Any Select to Y
Enable to Y
Enable toY
215
255
-
-
2
185
-
230
-
280
4.5
37
36
46
45
56
54
6
31
-
39
-
48
-
2
185
-
230
-
280
-
tPLH
4.5
37
41
46
51
56
62
6
31
-
39
-
48
-
2
205
-
255
-
310
tPLH
4.5
41
43
51
54
62
65
tPHL
6
35
-
43
-
53
-
2
140
-
175
-
210
-
tPLH
4.5
28
29
35
36
42
44
tPHL
6
24
30
-
36
-
2
145
-
180
-
220
t PLH
4.5
29
36
36
45
54
tPHL
6
25
31
38
-
Output Transition
trLH
2
75
-
95
-
110
-
Time
trHL
4.5
15
15
19
19
22
22
6
13
-
16
-
19
-
-
-
10
-
10
-
10
-
10
-
10
ns
ns
ns
-
44
-
C,
ns
-
-
I nput CapaCitance
ns
-
tpHL
-
Any Select to Y
-
tPLH
-
10
ns
ns
pF
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
HC/HCT151
92C5 - 38432
TERMINAL ASSIGNMENT
Input Level
Switching Voltage, V,
CD54/74HC
CD54/74HCT
V"
50% Vee
3V
1.3 V
I
I
I
Fig. 2 - Propagation delays to Y and Voutputs.
188 _______________________________________________________________________
_____________________________________________________________ TechnicaIData
CD54/74HC153
CD54/74HCT153
File Number 1774
High-Speed CMOS Logic
,.4'===:::;-1
110
II
111
5
1I~
4
Dual 4-lnput Multiplexer
'" -'-r-'----_--'
","
"
Type Features:
'
• Common select inputs
• Separate enable inputs
• Buffered inputs and outputs
FUNCTIONAL DIAGRAM
The RCA-CD54174HC153 and CD54/74HCT153 are dual 4to-1-line selector/multiplexers which select one of four
sources for each section by the common select inputs, SO
and S1. When the enable inputs (1E, iE) are HIGH, the
outputs are in the LOW state.
The CD54HC/HCT153 are supplied in 16-lead hermetic
dual-in-Iine ceramic packages (F suffix). The CD74HC/
HCT153 are supplied in 16-lead dual-in-line plastic packages (E suffix) and in 16-lead dual-in-Iine surface mount
plastic packages (M suffix). Both types are also available in
chip form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCTIHCU: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML 0 30%, N'H 0 30% of Vee; @ Vee = 5V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, :S 1 f.1A @ VOL.. V OH
TRUTH TABLE
Select
Inputs
S, So
X
X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
Data Inputs
10
X
L
H
X
X
X
X
X
X
I,
X
X
X
L
H
X
X
X
X
h
X
X
X
X
X
L
H
b
X
X
X
X
X
X
X
X
X
L
H
Enable
Output
E
H
L
L
L
L
L
L
L
L
Y
L
L
H
L
H
L
H
L
H
Select inputs A and B are common to both sections.
H 0 High Level. L 0 Low Level, X 0 Don·t Care.
LOGIC DIAGRAM
16
Vee
2
15
2E
iE
51
113
112
111
110
3
14
4
13
5
12
6
1Y
GND
11
10
B
9
SO
21 3
212
211
21 0
2Y
92C$-39825
TERMINAL ASSIGNMENT
________________________________________________________________________ 189
TechnicaIOala----------------------------
CD54/74HC153
CD54/74HCT153
16
Vee 0
8
GNOO
Fig. 1 - Logie diagram.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ................................................................................... -0.5 to + 7 V
DC INPUT DIODE CURRENT, I'K (FOR VI < -0.5 V OR VI> Vee +0.5V) ...................................................... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V) ........................ ,.......................... ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V) ....................................... ,........... ±25mA
DC Vee OR GROUND CURRENT (Ieel '. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±50mA
. POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60° C (PACKAGE ,\YPE E) ............................................................................. 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) ................................................ Derate Linearly at 8 mW/oC to 300 mW
For TA = -55 to +100°C (PACKAGE TYPE F, H) ......................................................................... 500 mW
For TA =+100to +125°C (PACKAGE TYPE F, H) ........................................... Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) ............................................................................ 400 mW
For TA =+70to +125°C (PACKAGE TYPE M) ............................................... Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .......................................................................................... -55 to +125°C
PACKAGE TYPE E, M ........................................................................................... -40 to +85° C
STORAGE TEMPERATURE (T,.. ) .................................................................................. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max....................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................................................................................... +300°C
190 __
~
_______________________________________________
Technical Data
CD54/74HC153
CD54/74HCT153
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT153/CD54HCT153
CD74HC153/CD54HC153
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPE
TYPE
CONDITIONS
TYPES
TYPE
TYPE
-40/
-55/
-40/
-55/
+85'C
+125"C
+85°C
+125'C
CHARACTERISTIC
UNITS
+25°C
V,
V
I,
rnA
Vee
V
+25°C
V,
V
Veo
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
4.5
V",
1.5
15
1.5
3.15
3.15
3.15
to
4.2
4.2
4.2
5.5
Low-Level
Input Voltage
High-Level
Output Voltage
4.5
V"
V"
V OH
CMOS Loads
or
-0.02
4.5
V,"
Min Typ Max Min Max Min Max
4.5
4.5
0.5
05
05
1.35
1.35
1.35
to
18
1.8
18
5.5
1.9
19
1.9
V"
4.4
4.4
4.4
or
5.9
5.9
59
V,"
3.98
3.84
3.7
or
548
5.34
5.2
V 1H
V"
TTL Loads
Low-Level
Output Voltage
-4
V,,<
-5.2
or
4.5
0.02
0.1
0.1
0.1
V"
0.1
01
0.1
or
0.1
0.1
0.1
V,"
4.5
0.26
0.33
0.4
or
6
0.26
0.33
0.4
V,"
6
:!.O.1
±1
±1
Any
Voltage
Between
4.5
VI~i
CMOS Loads
V"
TTL Loads
Input Leakage
5.2
Vee
Current
or
4.5
4.4
4.5
3.98
0.8
44
0.8
V
44
V
-
4.5
-
3.84
01
-
3.7
V
0.1
0.1
V
0.4
V
"1
±1
/,A
80
160
/,A
450
490
/,A
V"
or
Vlfi
08
V"
or
V"
VOL
V
4.5
-
026
5.5
-
±O.1
-
0.33
-
Vee
Gnd
Quiescent
Vee
Device
or
Current
Icc
& Gnd
Vee
80
or
160
Gnd
5.5
Gnd
Additional
Quiescent
Device Current
per input pin:
1 unit load
.6lcc·
4.5
Vcc-2 .1
to
100
360
5.5
'For dual-supply systems theoretical worst case (V, = 2.4 V, Vee = 5.5 V) specification IS 1 8 mA.
HCT Input Loading Table
Input
Unit Loads'
DATA
ENABLE
SELECT
0.45
0.6
1.35
·Unit Load is Alec limit specified in Static Characteristic
Chart, e.g., 360 pA max. @ 25'C.
______________________________________________________________________ .191
TechnicaIOata ___________________________________________________________
CD54/74HC153
CD54/74HCT153
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selecled so Ihal operation is always wilhin
Ihe following ranges:
LIMITS
CHARACTERISTIC
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
Supply-Voltage Range (For TA - Full Package-Temperature Range) Vee:'
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V" Vo
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t" tf
at2V
at4.5 V
at6V
V
V
'Unless otherwise specified, all voltages are referenced to Ground.
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Inpul I" If = 6 ns)
TYPICAL
VALUES
CL
(pF)
CHARACTERISTIC
Propagation Delay,
Select to Outputs
Data to Outputs
15
15
15
15
t pHL t pLH
t pLH
tpHL
Enable to Outputs
t pLH t pHL
Power Dissipation Capacitance'
-
CpD
HC
HCT
13
12
12
9
45
14
9
14
11
UNITS
ns
45
pF
'CPO is u~ed to determine the dynamic power consumption, per multiplexer.
PD = Vee fi (C PD + C l ) where: fi = input frequency
C l = output load capacitance
Vee = supply voltage
SWITCHING CHARACTERISTICS (C l
CHARACTERISTIC
Propagation Delay,
StoY
t pLH
t pHL
tPLH
ltoY
t pHL
EtoY
t pLH
t pHl
Input
Capacitance
50 pF, Inpul Ie, If = 6 ns)
Vee
ltoY
Output Transition
Time
=
hLH
hHL
C,
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-55°Clo+125°C
25°C
-40°C 10 +85°C
UNITS
74HC
74HCT
54HC
54HCT
HC
HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
200 - 240 160 48
51
34
40
43
32
41
27
34
220 145 180 44
36
29
24
36
30
25
31
38
ns
220 145 180 43
44
51
29
34
36
31
38
25
180 120 150 41
24
27
30
34
36
26
31
20
75
95
110 19
22
15
15
19
22
19
13
16
-
-
10
-
10
192 ____________.______________________
-
10
-
10
-
10
-
10
pF
_______________________________ Technical Data
CD54/74HC153
CD54/74HCT153
tr::; 6 ns
I OR
s---~
1"'=-==:="1"-----
OUTPUT Y
9~CS-39824
Input Level
Switching Voltage, Vs
I
I
I
54174HC
Vee
50% Vee
54/74HCT
3V
1.3 V
I
I
I
Fig. 2 - TransitioJl and propagation delay times.
____________________________________________________ 193
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC154
CD54/74HCT154
File Number
1657
High-Speed CMOS logic
4-to-16 line Decoder/Demultiplexer
AO
AI
2:3
22
Type Features:
• Two enable inputs to facilitate demultiplexing and cascading functions
Family Features:
A221
20
•
•
FUNCTIONAL DIAGRAM
•
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85 0 C
Balanced Propagation Delay and Transition Times
The RCA CD54174HC154 and CD54174HCT154 are 4-to-16
• Significant Power Reduction Compared to
LSTTL Logic ICs
line decoders/demultiplexers with two enable inputs, ET
and E2. A High on either enable input forces the output into
• Alternate Source is Philips/Signetics
the High state. The demultiplexing function is performed by
• CD54HC/CD74HC Types:
2 to 6 V Operation
~ing the four input lines, AO to A3, to select the output lines
High Noise Immunity: ML = 30%, MH = 30% of Vee
YO to Vi5", and using one enable as the data input while
holding the other enable low._
@ Vee = 5 V
The CD54HC154and CD54HCT154 are supplied in 24-lead
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
dual-in-line frit-seal ceramic packages (F suffix). The
CD74HC154 and CD74HCT154 are supplied in 24-lead
Direct LSITL Input Logic Compatibility
dual-in-line, narrow-body plastic packages (EN suffix), in
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
24-lead dual-in-line, wide-body plastic packages (E suffix).
and in 24-lead dual-in-line surface-mount plastic packages
I, :S 1 /lA @ VOL, V OH
(M suffix). Both types are also available in chip form (H
suffix).
TRUTH TABLE
INPUTS
-
E1
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
-
OUTPUTS
-
E2
A3
A2
A1
AO
YO
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
L
H
-
Y1
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
-
Y2
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Va -Y4
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
-
Y5
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
-
Y6
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
-
Y7
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
-
YB
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
-
Y9
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
-
Y10
YTi
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
m"Vi3
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
'-i
Y14
ViS
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H = High Level, L = Low Level, X = Don't Care.
194 __________________________________________________________________
_________________________________________________________ TechnicaIData
CD54/74HC154
CD54/74HCT154
12
(;NOo24
Vcco-
He INPUl
SlA~~
23
A06----{>C
[)o--XI
XI
X2
X2
22
AI~X3
21
X4.
A2~X5
X6
20
A35---{)C
X3
X4
t>o----X7
XB
X5
X6
HCT INPUT STAGE
~XI
23
AO
Y9
X2
~X3
22
AI
X4
X7
xe
~X5
A28-.
X6
~X7
20
A3
•
X8
19
EI!o--{)o-,
_18
Elo--[>o-...J
92CL- 38318
Fig. 1 - Logic diagram.
_________________________________________________________________ 195
TechnlcaIOala _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC154
CD54/74HCT154
MAXIMUM RATINGS. Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) , , , , ............................... , , .......................•......................... -0.5 to +7 V
DC INPUT DIODE CURRENT, 1,K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ....................................................... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo> Vee +0.5 V) ..........................~ ......................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) .................................................... ±25 mA
DC Vee OR GROUND CURRENT, PER PIN (lee): ............................................................................ ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60' C (PACKAGE TYPE E) ...............................................................•............... 500 mW
For T. = +60 to +85' C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/' C to 300 mW
For TA =-55 to +100' C (PACKAGE TYPE F, H) ........................................................................... 500 mW
ForT. = +100 to +125'C (PACKAGE TYPE F, H) ............................................. Derate Linearly at 8 mW/'C to 300 mW
For T. = -40 to +70'C (PACKAGE TYPE M) .............................................................................. 400 mW
For T. = +70 to +125'C (PACKAGE TYPE M) ................................................. Derate Linearly at 6 mW/'C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H ............................................................................................. -55 to +125'C
PACKAGE TYPE E, M ...............................................................................................-40 to +85'C
STORAGE TEMPERATURE (Tot,) .................................................................................... -65 to +150'C
LEAD TEMPERATURE (DURING SOLDERING)
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case lor 10 s max ........................................................ +265'C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ......................................................................... ············ +3OO'C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability. nominal operating conditions should be selected so that operation Is always within the
following ranges:
LIMITS
CHARACTERISTIC
UNITS
MIN.
MAX.
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vcc:'
CD54/74HC Types
2
6
V
CD54174HCT Types
4.5
5.5
V
0
Vcc
V
CD74 Types
-40
+85
DC
CD54 Types
-55
+125
DC
al2V
0
1000
ns
a14.5 V
0
500
ns
at 6V
0
400
ns
DC Input or Outpul Vollage V" Vo
Operating Temperature T A:
Inpul Rise and Fall Times, I.. If
'Unless otherwise specified, all voltages are referenced to Ground.
1~
______________________
~
______
~
____
_____________________________________________________________ TechnicaIData
CD54/74HC154
CD54/74HCT154
STATIC ELECTRICAL CHARACTERISTICS
CD74HC154/CD54HC154
CD74HCT154/CD54HCT154
TEST
74HC/54HC
74HC
54HC
TEST
74HCT154HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85"C
+125"C
+85"C
+125"C
UNITS
CHARACTERISTICS
+25"C
V,
10
V
mA
High-Level
Input Voltage
V,"
Low-Level
Input Voltage
V"
High-Level
V"
Output Voltage
Vo"
CMOS Loads
or
-0.02
V,"
V,
Vee
V
V
V
Min Typ Max Min Max Min Max
2
1.5
-
-
1.5
-
1.5
-
4.5
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
Low-Level
Voe
CMOS Loads
2
1.9
-
-
1.9
-
1.9
-
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
I,
Icc
-
3.84
-
3.7
-
or
V,"
-5.2
6
5.48
-
-
5.34
-
5.2
-
V,"
2
-
-
0.1
-
0.1
-
0.1
V"
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
pA
5.5
-
-
8
-
80
-
160
pA
-
100 360
-
450
-
490
pA
to
V"
or
4
4.5
-
-
0.26
-
0.33
-
0.4
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
Any
Voltage
Vee
6
-
-
~0.1
-
±1
-
±1
Between
Vee and
Gnd
Vee
Vee
or
Gnd
-
V"
-
or
Gnd
Quiescent Device
Current
2
V"
3.98
V"
Input Leakage
Current
-
5.5
4.5
V,"
TTL Loads
-
4.5
-
-4
or
2
to
5.5
or
V"
Output Voltage
Min Typ Max Min Max Min Max
4.5
-
4.5
V"
TTL Loads
+25"C
Vee
a
6
-
-
8
-
80
-
160
or
Gnd
Additional
Quiescent Dellice
4.5
Current per
Vee -2.1
Input Pin:
to
5.5
1 Unit Load
.6. Icc
-For dual-supply systems theoretical worst case (VI
=2.4 V.
Vee = 5.5 V) specification is 1.8 rnA.
24
Yo
23
Vi
HCT INPUT LOADING TABLE
INPUT
UNIT LOADS *
AO-A3
1.4
E1,E2
1.3
21
Vee
AD
A1
A2
20 A3
19 E2
Y5
E1
Yo
18
Y7
17 Y15
Yo
Y9
9
10
16 Y14
15
_11
14
12
13
YlO
*Unit Load is .6. Icc limit specified in Static Characteristic Chart
e.g., 360 pA max. @ 25°C.
'
22
Y2
Y'i
Y4
GND
m
ill
ffi
TERMINAL ASSIGNMENT
_______________________________________________________________________ 197
Technical Data ___________________________________________________________
CD54/74HC154
CD54/74HCT154
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25° C, Inpull" I, = 6 ns)
TYPICAL VALUES
CHARACTERISTIC
SYMBOL
CL
pF
Propagation Delay
E1
54174HCT
14
14
ns
14
14
ns
14
14
ns
88
84
pF
tPHL
15
Address to Output
UNITS
54174HC
tPLH
to Output
t PHL
15
tPlH
E2 to Output
tPHL
15
tPLH
-
Power Dissipation Capacitance*
Cpo
*Cpo is used to determine the dynamic power consumption, per device.
Po =Vee' f, (Cpo + Cel where: fl =input frequency.
CL = output load capacitance.
Vee = supply voltage.
SWITCHING CHARACTERISTICS (C L = 50 pF, Inpull" I, = 6 ns)
-40° C 10 +85° C
25°C
CHARACTERISTIC
SYMBOL
HCT
HC
Vee
74HC
-55°C to +125°C
54HC
74HCT
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay
Address to Outputs
E1 to Outputs
tpLH
2
-
175
-
-
-
220
-
-
-
265
-
-
tpHL
4.5
-
35
-
35
-
44
-
44
-
53
-
53
-
6
-
30
-
-
-
37
-
-
-
45
-
tPLH
2
-
175
-
-
-
220
-
-
-
265
-
-
tPHL
4.5
-
35
-
34
-
44
-
43
-
53
-
51
6
-
30
-
-
-
37
-
-
-
45
-
-
tPLH
2
-
175
-
-
-
220
-
-
-
265
-
-
E2 to Outputs
tPHL
4.5
-
35
-
34
-
44
-
43
-
53
-
51
6
-
30
-
37
-
-
-
45
-
-
hLH
2
-
75
-
-
-
Output Transition
-
95
-
-
-
110
-
-
Time
hHL
4.5
-
15
-
15
-
19
-
19
-
22
-
22
6
-
13
-
-
-
16
-
-
-
19
-
-
-
10
-
10
-
10
-
10
-
10
-
10
Input Capacitance
CI
ns
ns
ns
ns
pF
198 ____________________________________________________________________
___________________________________________________________ TechnicaIData
CD54/74HC154
CD54/74HCT154
90%
L
INPUT LEVEL
92CS-38381RI
Input Level
Switching Voltage, Vs
54174HC
54174HCT
Vee
3V
50% Vee
1.3 V
Fig. 2 - Propagation delay and transition times.
______________________________________________________________________ 199
TechnicaIOata _______________________________
. CD54/74HC157, CD54n4HCT157
CD54/74HC158" CD54/74HCT158
File Number
1642
High-Speed CMOS Logic
110
111
21 0
211
31 0
31 1
410
411
2
3
4
5
6
11
10
9
14
13
12
HC/HCT
157
HC/HCT
158
lY
iY
Quad 2-lnput Multiplexers
2Y
2Y
HC/HCT157 Non-Inverting
HC/HCT158 Inverting
3Y
3Y
4Y
4Y
Type Features:
S
E
•
•
Buffered inputs
Typical Propagation Delay (In to Output) = 10 ns (HC157) @ Vee = 5 V,
C L =15pF, TA=25°C
92CS-38445
FUNCTIONAL DIAGRAM
The RCA"CD54/74HC157, 158 and CD54174HCT157, 158
are quad 2-input multiplexers which select four bits of data
from two sources under the control of a common Select
. input (S). The Enable input (E) is active LOW. When
is
HIGH, all of the outputs in the 158, the inverting type, (1Y4Y) are forced HI@ a!!fl in the 157, the non-inverting type,
ali of the outputs (1Y-4Y) are forced LOW, regardless of all
. other input conditions.
Family Features:
•
lEi
Moving data from two groups of registers to four common
output busses is a common use of these devices. The state
of the Select input determines the particular register from
which the data comes. They can also be used as function
generators.
The CD54HC157, 158 and CD54HCT157, 158 are supplied
in 16-lead hermetic dual-in-line ceramic packages (F suffix).
The CD74HC157, ,158 and CD74HCT157, 158 are supplied
in 16-lead dual-in-line plastic packages (E suffix). The
CD74HC157, 158 and CD74HGT157, 158 are supplied in
16-lead dual-in-line surface n,ount plastic packages (M
suffix). Both types are also available in chip form (H suffix).
•
•
•
•
•
•
Fanout (Over Temperature Rangej:
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85° C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to
LSTTL Logic ICs
Alternate Source is Philips/Signetics
CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity: ML =30%, N,H =30% of Vee
@ Vee = 5 V
CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'L =0.8 V Max., V,H =2 V Min.
CMOS Input Compatibility
I, ~ 1 /1A @ VOL, VO H
FUNCTION TABLE
Output
Enable
I
Select
Input
Data
Inputs
157
158
-
E
S
10
I,
Y
H
X
X
X
L
H
L
L
L
X
L
H
L
L
H
X
H
L
L
H
X
L
L
H
L
H
X
H
H
L
Y
L _ _ _ _ _ _ _ _ _ _ _ _ _ --lI
3 CIRCUITS IDENTICAL TO CIRCUIT
IN ABOVE DASHED OUTLINE
Fig. 1 - Logic Diagram for HC/HCT1S7.
92CM-3B446
L = LOW voltage level.
H = HIGH voltage level.
X = Don't care.
200 ________________________________________________________________
___________________________________________________________ TechnicaIData
CD54/74HC157, CD54/74HCT157
CD54/74HC158, CD54/74HCT158
16
15
IIO
14
II I
-----------,
13
-TV
I
He/HeT1S8
I
I
2IO
I
I
Vee
E
41:0
4I,
'2
H,
10
*n
_______ J
4"'(-
31 0
H,
9
GND
3'Y*
92CS-3700B
3 CIRCUITS IDENTICAL TO CIRCUIT
IN ABOVE DASHED OUTLINE
• For HC/HCT157 these outputs are 1V, 2Y, 3Y, 4Y
TERMINAL ASSIGNMENT
92CS-38447
Fig. 2 - Logic Diagram for HC/HCT158.
MAXIMUM RATINGS .. Absolute-Maximum Values:
DC SUPPL Y-VOL TAGE, (Vee):
(Voltages referenced to ground) ...................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ....................................................... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V)· ................................................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) .................................................... ±25 mA
DC Vee OR GROUND CURRENT (Icc): ............................ , ........................................................ ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. =-40 to +60° C (PACKAGE TYPE E) ............................................................................... 500 mW
For T. = +60 to +85°C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/oC to 300 mW
For T. =-55 to +loo°C (PACKAGE TYPE F, H) ........................................................................... 500 mW
For T. = +100 to +125°C (PACKAGE TYPE F, H) ............................................. Derate Linearly at 8 mW/oC to 300 mW
For T. = -40 to +70°C (PACKAGE TYPE M) ............................................................................. 400 mW
For T. = +70 to +125° C (PACKAGE TYPE M) . .. . . ... . . . . . . .. . . .... . . .. . ..... . . .. . .. . . .... .. Derate Linearly at 6 mW;o C to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H ............................................................................................. -55 to +125°C
PACKAGE TYPE E, M ..............................................................................................-40 to +85°C
STORAGE TEMPERATURE (T,,,) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ........................................................ +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ..................................................................................... +300° C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within the
'ollowing ranges'
LIMITS
CHARACTERISTIC
UNITS
MIN.
MAX.
Supply-Voltage Range (For T. = Full Package Temperature Range) Vee:'
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V", V oul
2
6
V
4.5
5.5
V
0
Vee
V
Operating Temperature T.:
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
ns
Input Rise and Fall Times, t" tf
I
at 2 V
0
1000
at 4.5 V
0
500
ns
at 6 V
0
400
ns
'Unless otherwise specified, all voltages are referenced to Ground.
___________________________________________________________________ 201
Technical Data ___________________________________________________________
CD54/74HC157, CD54/74HCT157
CD54/74HC158, CD54/74HCT158
STATIC ELECTRICAL CHARACTERISTICS
CD74HC157/158/CD54HC157/158
CD74HCT157/158/CD54HCT157/158
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85°C
*125°C
*85°C
*125°C
CHARACTERISTICS
UNITS
*25°C
*25°C
V,
10
Vee
V
rnA
V
High-Level
Input Voltage
V,"
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
VO "
CMOS Loads
or
-0.02
V,"
Min Typ Max Min Max Min Max
2
1.5
-
-
15
-
1.5
-
4.5
3.15
-
-
3.15
-
315
-
6
42
-
-
4.2
-
4.2
-
Low-Level
Output Voltage
CMOS Loads
2
-
-
05
-
0.5
-
05
4.5
-
-
1.35
-
135
-
135
-
-
2
-
2
-
V
6
-
-
18
-
1.8
-
18
-
-
0.8
-
0.8
-
08
V
4.5
4.4
-
-
44
-
44
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
026
-
033
-
0.4
V
55
-
-
fiOl
-
col
-
±1
~A
55
-
-
8
-
80
-
160
~A
360
-
450
-
490
~A
4.5
-
to
5.5
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
V"
V"
3.98
-
-
3.84
-
3.7
-
or
V,"
-5.2
6
5.48
-
-
5.34
-
5.2
-
V,"
2
-
-
0.1
-
0.1
-
0.1
V"
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
V"
or
4
4.5
-
-
026
-
0.33
-
04
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
Any
Input Leakage
I,
Voltage
Vee
or
6
-
-
0.1
-
±1
-
Il
Between
Gnd
Vee and
Gnd
Quiescent Device
Current
2
to
5.5
45
or
Min Typ Max Min Max Min Max
4.5
V"
Current
V
-4
V,"
TTL Loads
V
or
V"
Vee
Vee
-
V"
TTL Loads
V,
Vee
Icc
Vee
or
0
6
-
-
8
-
80
-
or
160
Gnd
Gnd
Additional
45
QUiescent Device
Vee -2.1
Current per
1 Unit Load
-
to
100
5.5
Input Pin"
6. l cc
·For dual-supply systems theoretical worst case (VI = 2.4 V, Vee
=5.5 V) specification 151,8 mAo
INPUT LOADING TABLE
UNIT LOADS'
INPUT
HCT 157
HCT 158
I (ALL)
0.95
0.4
E
0.6
0.6
S
3
2.8
* Unit load is ll.lcc limit specified in Static Characteristic
202 ____________________________________________________________________
Chart, e.g., 360 J-IA max. @ 25° C.
__
___________________________________________________________ TechnicaIOata
CD54/74HC157, CD54/74HCT157
CD54/74HC158, CD54/74HCT158
SWITCHING CHARACTERISTICS (Vee = 5 V, CL = 15 pF, TA = 25°C,lnpul I" I, = 6 ns)
TYPICAL VALUES
CHARACTERISTIC
UNITS
SYMBOL
CL
pF
HC157
HCT157
HC158
HCT158
10
12
11
13
ns
11
12
13
15
ns
12
15
12
14
ns
62
70
35
35
pF
tPHL
Data to Output
15
tPLH
tPHL
Enable to Output
15
tPLH
tPHL
Select to Output
15
tPLH
Cpo
Power Dissipation Capacitance'
, Cpo IS used to determine the dynamic power consumption, per multiplexer.
Po = Cpo Vee' f, + L CL Vee' fo where:
f, = input frequency.
fo = output frequency.
CL = output load capacitance.
Vee = supply voltage.
SWITCHING CHARACTERISTICS (CL = 50 pF, Inpul I" I, = 6 ns)
-40° C 10 +85° C
25°C
CHARACTERISTIC
SYMBOL
HC
Vee
74HC
HCT
-55°C 10 +125°C
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay
Data to Output
tPLH
tPHL
(Figure 3) HC/HCT157
-
125
-
-
-
155
-
-
-
190
-
-
-
25
-
4.5
30
-
31
-
38
-
38
-
45
6
-
21
-
-
-
26
-
-
-
32
-
-
Propagation Delay
tPLH
2
-
135
-
-
-
170
-
-
-
205
-
-
Enable to Output
tPHL
4.5
-
27
-
30
-
34
-
38
-
41
-
45
6
-
23
-
-
-
29
-
-
-
35
-
-
-
145
-
-
-
180
-
-
-
220
-
-
(Figure 4) HC/HCT157
Propagation Delay
tPLH
2
Select to Output
tPHL
4.5
-
29
-
37
-
36
-
46
-
44
-
56
6
-
25
-
-
-
31
-
-
-
38
-
-
(Figure 3) HC/HCT157
Propagation Delay
tPLH
2
-
140
-
-
-
175
-
-
-
210
-
-
Data to Output
tPHL
4.5
-
28
-
32
-
35
-
40
-
42
-
48
6
-
-
24
-
-
-
30
-
-
-
36
-
Propagation Delay
tPLH
2
-
160
-
-
-
200
-
-
-
240
-
-
Enable to Output
tPHL
4.5
-
32
-
37
-
40
-
46
-
48
-
56
6
-
27
-
-
-
34
-
-
-
41
-
-
(Figure 3) HC/HCT158
(Figure 4) HC/HCT158
Propagation Delay
tPLH
2
-
150
-
-
-
190
-
-
-
225
-
-
Select to Output
tpHL
4.5
-
30
-
35
-
38
-
44
-
45
-
53
-
(Figure 3) f IC/HCT158
6
-
26
-
-
-
33
-
-
-
38
-
Output Transition
hLH
2
-
75
-
-
-
95
-
-
-
110
-
-
Time
hHL
4.5
-
15
-
15
-
19
-
19
-
22
-
22
6
-
13
-
-
-
16
-
-
-
19
-
-
-
10
-
10
-
10
-
10
-
10
-
10
(Figure 3 or 4)
Input Capacitance
I
2
Cin
ns
ns
ns
ns
ns
ns
ns
I
pF
___________________________________________________________________ 203
TechnicaIOala _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC157, CD54/74HCT157
CD54/74HC158, CD54/74HCT158
r----I'
- - INPUT LEVEL
In ORS
Il""-----GND
IF-----GND
IpLH
Y
HC/HCT158
Y
HC/HCT158
HC/HCT157
Y
HC/HCT157 Y
92CS-38448
Input Level
Vs
Fig. 3 - Inputs or select to output propagation delays and output
transition times.
92C5-38449
54/74HC
54174HCT
Vee
3V
50% Vee
1.3 V
Fig. 4 - Enable to output propagation delays and output transition
times.
204 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
_
~
_ _ _ _ __
__________________________________________________________ TechnicaIOata
CD54/74HC/HCT160, CD54/74HC/HCT161
CD54/74HC/HCT162, CD54/74HC/HCT163
File Number 1550
High-Speed CMOS Logic
FUNCTIONAL DIAGRAM
PO
S'PE'
CP
P2
14
2
13
12
II
PE
10
Presettable Counters
P3
9
MIl
TE
PI
15
92CS-37958
00
QI
CD54174HC/HCT160
CD54174HC/HCT161
CD54174HC/HCT162
CD54/74HC/HCT163
BCD
4-Bit
BCD
4-Bit
Decade Counter, Asynchronous Reset
Binary Counter, Asynchronous Reset
Decade Counter, Synchronous Reset
Binary Counter, Synchronous Reset
Q2
Q3
TC
Type Features:
•
•
•
•
•
Synchronous Counting and Loading
Two Count Enable Inputs for n-Bit Cascading
Asynchronous Reset (CD54/74HC/HCT160, 161)
Synchronous Reset (CD54/74HC/HCT162, 163)
Look-Ahead Carry for High-Speed Counting
The RCA-CD54174HC/HCT160, 161, 162, and 163 devices
are presettable synchronous counters that feature lookahead carry logic for use in high-speed counting applications. The CD5417 4HC/HCT160 and 161 are asynchronous
reset decade and binary counters, respectively; the
CD54/74HC/HCT162 and 163 devices are decade and
binary counters, respectively and are reset synchronously
with the clock. Counting and parallel presetting are both
accomplished synchronously with the negative-to-positive
transition of the clock.
A low level on the synchronous parallel enable input, SPE,
disables the counting operation and allows data at the PO
to P3 inputs to be loaded into the counter (provided that
the setup and hold requirements for SPE are met).
All counters are reset with a low level on the Master Reset
input, MR. In the CD54174HC/HCT162 and 163 counters
(synchronous reset types), the requirements for setup and
hold time with respect to the clock must be met.
Two count enables, PE and TE, in each counter are provided for n-bit cascading. In all counters reset action occurs
regardless of the level of the ~, PE and TE inputs (and
the clock input, CP, in the CD54/74HC/HCT160 and 161
types).
If a decade counter is preset to an illegal state or assumes
an illegal state when power is applied, it will return to the
normal sequence in one count as shown in state diagram.
The look-ahead carry feature simplifies serial cascading of
the counters. Both count enable inputs (PE and TE) must
be high to count. The TE input is gated with the Q outputs
of all four stages so that at the maximum count the terminal
count (TC) output goes high for one clock period. This TC
pulse is used to enable the next cascaded stage.
The CD54HC160through 163 and the CD54HCT160through
163 are supplied in 16-lead hermetic dual-in-line ceramic
packages (F suffix). The CD74HC160 through 163 and the
CD74HCT160 through 163 are supplied in 16-lead dual-inline plastic packages (E suffix), and in 16-lead dual-in-line
surface mount plastic packages (M suffix). All types are also
supplied in chip form (H suffix).
Family Features:
•
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85 0 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity: ML = 30%, N,H = 30%
of Vee, @ Vee = 5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, ::::; 1 IlA @ VOL, VOH
MR
16 Vee
CP
15 Te
PO
14 00
P1
13 01
P2
12 Q2
P3
11 Q3
PE
10 TE
GND
9
WE
TERMINAL ASSIGNMENT
______________________________________________________________________ 205
TechnicaIOata ____________________________________________________________
CD54/74HC/HCT160, CD54/74HC/HCT161
CD54/74HC/HCT162, CD54/74HC/HCT163
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPL Y-VOL TAGE, (Vee):
(Voltages referenced to ground) ...................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, 1,K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ....................................................... ±20 rnA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) .......................... , ......................... ±20 rnA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) ..................................................... ±25 rnA
DC Vee OR GROUND CURRENT, (Icc): ........................................................... , ......................... ±50 rnA
POWER DISSIPATION PER PACKAGE (Po):
For TA ~ -40 to +60'C (PACKAGE TYPE E) ................................................................................ 500 mW
For TA ~ +60 to +85' C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/' C to 300 mW
For TA ~ -55 to +100'C (PACKAGE TYPE F, H) ............................................................................ 500 mW
For TA ~ +100 to +125'C(PACKAGE TYPE F, H) .............................................. Derate Linearly at 8 mW/'C to 300 mW
ForT. ~ -40 to +70°C (PACKAGE TYPE M)
............................................................................ 400 mW
For T. ~ +70 to +125'C (PACKAGE TYPE M) ............................................... Derate Linearly at 6 mW/'C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .............................................................................
-55 to +125'C
PACKAGE TYPE E, M .....................................................................
-40 to +85'C
STORAGE TEMPERATURE (T",) ................................................ ..
-65 to +150'C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max. , ..................................................... . +265'C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ........................................................... , ........................ . +300'C
PE
TE
*CONNECTTOVCC FOR 162
'* CONNECT TO GNO FOR 160
12
13
14
QO
01
TC
02
03
Fig. 1 - Logic diagram for the CD54174HC/HCT160 and 162.
160,162 STATE DIAGRAM
92CS-40259RI
NOTE, ILLEGAL STATES IN BCD COUNTERS
~C~O_RR~E~C~T~E~D_I~N_O_N~E_C~O~U~N~T_.______________________________________
206 ____________________________________
___________________________________________________________ TechnicaIData
CD54/74HC/HCT160, CD54/74HC/HCT161
CD54/74HC/HCT162, CD54/74HC/HCT163
03
CP
* CONNECT TO VCC FOR 163
#
CONNECT TO GNO FOR 161
TC
92CM-37957RI
Fig. 2 - Logic diagram for the CD54/74HC/HCT161 and 163.
MODE SELECT - FUNCTION TABLE, 160, 161
INPUTS
OUTPUTS
OPERATING MODE
MR
Reset (Clear)
PE
TE
SPE
p,
Qn
TC
L
X
X
X
X
X
L
L
H
--F
X
X
I
I
L
L
H
-.r
X
X
I
h
H
(a)
H
..J"
h
h
hIe)
X
count
(a)
H
X
I(b)
X
hIe)
X
qn
(a)
X
I(b)
hIe)
X
qn
L
Parallel Load
Count
CP
Inhibit
H
X
_________________________________________________________________ 207
TechnicaIOata _ _ _ _ _ _-,-_ _ _ _ _ _ _ _ _ _- - - - - - - - - - -
CD54/74HC/HCT160,CD54/74HC/HCT161
CD54/74HC/HCT162, CD54/74HC/HCT163
MODE SELECT - FUNCTION TABLE, 162, 163
OUTPUTS
INPUTS
OPERATING MODE
MR
CP
PE
TE
SPE
Pn
an
TC
I
-'
X
X
X
X
L
L
X
X
I
I
L
L
H
(d)
Reset (Clear)
Parallel Load
Count
Inhibit
h(l)
.-r
h(l)
~
X
X
I
h
h(l)
~
h
h
h(l)
X
count
(d)
h(l)
X
I(e)
X
h(l)
X
qn
(d)
h(l)
X
X
I(e)
h(l)
X
qn
L
H = HIGH voltage level steady state.
L = LOW voltage level steady state.
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition.
I = LOW voltage level one'setup time prior to the LOW-to-HIGH clock transition.
X = Don't care.
q = Lower'case letters indicat&-the state 01 the relerenced output prior to the LOW-to-HIGH clock transition.
~= LOW-to-HIGH clock transition.
NOTES
(a) The TC output is HIGH when TE is HIGH and the counter is at Terminal Count (HHHH lor 161 and HLLH for 160).
(b) The HIGH-to-LOW transition 01 PE or TE on the 54174161 and 54174160 should only occur while CP is HIGH lor
conventional operation.
(c) The LOW-to-HIGH transition 01 SPE on the 54/74161 and 54174160 should only occur while CP is HIGH lor
conventional operation.
(d) The TC output is HIGH when TE is HIGH and the counter is at Terminal Count (HLLH lor 162 and HHHH lor 163).
(e) The HIGH-to-LOW transition 01 PE or TE on the 54174163 should only occur while CP is HIGH lor
conventional operation.
(I) The LOW-to-HIGH transition 01 SPE or MR on the 54174163 should only occur while CP is HIGH lor
conventional operation.
RECOMMENDED OPERATING CONDITIONS:
For'maxlmum reliability; nominal operating conditions should be ilelected so that operation Is always within the
following ranges:
LIMITS
UNITS
CHARACTERISTIC
MIN.
MAX.
Supply-Voltage Range (For T .. = Full Package Temperature Range) Vee:*
CD54/74HC Types
CD54174HCT Types
DC Input or Output Voltage V" Vo
2
6
V
4.5
5.5
V
0
Vee
V
Operating Temperature T..:
CD74 Types
-40
+85
CD54 Types
-55
+125
'c
'c
Input Rise and Fall Times, t., tt
at2 V
0
1000
'ns
at 4.5 V
0
500
ns
at6 V
0
400
ns
*Unless otherwise specified, all voltages are referenced to Ground.
208 ________________________________________________________
_____________________________________________________________ TechnicaIOata
CD54/74HC/HCT160, CD54/74HC/HCT161
CD54/74HC/HCT162, CD54/74HC/HCT163
STATIC ELECTRICAL CHARACTERISTICS
CD74HC160-163/CD54HC160-163
CD74HCT160-163/CD54HCT160-163
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
SERIES
SERIES
SERIES
CONDITIONS
SERIES
SERIES
SERIES
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
10
Vee
V
rnA
V
+25°C
V,
Vee
V
V
Min Typ Max Min Max Min Max
Min Typ Max Min Max Min Max
High-Level
Input Voltage
Low-Level
I nput Voltage
V"
High-Level
V"
Output Voltage
or
Vo"
CMOS Loads
-0.02
V,"
4.5
1.5
-
-
1.5
-
1.5
-
4.5 3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
5.5
2
-
0.5
-
0.5
4.5
-
1.35
-
0.5
4.5
-
1.35 -
1.35
6
-
-
1.8
-
1.8
-
1.8
2
V,"
-
low-Level
Output Voltage
2
1.9
-
-
1.9
-
1.9
4.4
-
4.4
-
4.4
-
6
5.9
-
-
5.9
-
5.9
-
4.5 3.98
-
-
3.84
3.7
-
or
-
5.34
-
CMOS Loads
5.2
-
V,"
-
0.1
-
0.1
V"
0.1
-
0.1
or
0.1
-
0.1
V,"
V,"
-5.2
6
5.48
-
2
0.1
4.5
-
-
0.02
-
0.1
6
-
-
0.1
V,"
or
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
3.7
-
V
4.5 3.98
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
pA
5.5
-
-
8
-
80
-
160
pA
4.5
10
5.5
-
100
360
-
450
-
490
pA
V"
4
4.5
-
-
0.26
-
0.33
-
0.4
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
I,
Voltage
or
6
-
-
±0.1
-
±1
-
±1
Between
Vee and
Gnd
Gnd
Vee
Vee
Device
Quiescent
Device Current
per input pin:
1 unit load
-
V,"
or
Vee
Quiescent
Current
2
Any
Input Leakage
Current
-
V"
V"
TTL Loads
-
V"
-4
or
2
5.5
4.5
or
V"
Vo,
to
-
V"
TTL Loads
to
or
Icc
a
6
-
-
8
-
80
-
160
or
Gnd
Gnd
Vee -2.1
.
"Icc
-For dual-supply systems theoretical worst case (VI = 2.4 V. Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
PO-P3
Unit Loads·
0.25
PE
0.65
CP
1.05
MR
0.8
SPE
0.5
1.05
TE
'Unit load is alee limit specified in Static Characteristic
____________________~C~h~ar~t,~e~.g~.~,3~6~0~p~A~m~ax~.~@~2~5°~C~.~________________________________ 209
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC/HCT160, CD54/74HC/HCT161.
CD54/74HC/HCT162, CD54/74HC/HCT163SWITCHING CHARACTERISTICS (Vee
=5 V, TA =25°C, Inputt" If =6ns)
CHARACTERISTIC
Propagation Delay
CPto TC
CPto On
TEto TC
I'VlR"to On (160, 161)
TYPICAL
54174HC
54174HCT
15
18
15
16
13
9
18
21
CL
(pF)
15
15
15
15
SYMBOL
tPHL
tpLH
tPHL
Power Dissipation Capacitance'
Cpo
60
• CPD IS used to determine the dynamic power consumption, per package.
Po = Cpo Vee 2 f, + 1: (CL Vee2 fo) where: fi = input frequency. fo =output frequency.
CL = output load capacitance. Vee = supply voltage.
PREREQUISITE FOR'SWITCHING FUNCTION
UNITS
ns
ns
ns
ns
63
I·····
pF
LIMITS
TEST
CONDITIONS
CHARACTERISTIC
Max. CP Freq .•
CP Width (Low)
fMAx
tWILl
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-55° C 10 +125° C
UNITS
HCT
HC
Vee
V
_40° C to +85° C
25°C
74HC
74HCT
54HC
54HCT
Min. Max. Min. Max. Min. Max. Min; Max. .Mln. Max. Min. Max.
6
30
35
80
16
14
100
20
-
-
-
-
-
16
-
5
24
28
100
20
-
-
17
-
-
25
-
30
-
-
-
-
-
24
-
-
-
20
-
4
20
24
120
24
20
150
30
26
90
18
15
75
15
13
90
18
15
100
20
17
3
3
3
0
0
0
3
3
3
0
0
0
110
-
20
-
24·
-
-
MHz
ns
125
31
38
ns
25
21
17
75
60
ns
15
13
15
12
Setup Time
10
tsu
13
10
Pn to CP
65
50
16
ns
Setup Time
13
13
10
- 20 tsu
11
PE or TE to CP
9
75
60
ns
15
18
Setup Time
12
15
12
tsu
SPE to CP
10
- 13
65
- 80
20
ns
16
16
Setup Time
13
13
tsu
14
MR to CP (162,163)
11
3
3
ns
5
Hold Time
3
5
3
5
tH
3
Pn to CP
3
0
0
ns
3
3
Hold Time
3
0
0
tH
0
TE or PE to CP
0
3
3
ns
Hold Time
3
3
160, tH
3
3
3
SPE to CP
162
3
3
0
2
0
- ns
161, tH
0
3
0
3
3
4.5
0
163
0
6
75
95
2
ns
19
22 22 Recovery Time
15
15
4.5
- 19 tREe
16
19
MR to CP
13
6
Applies to non-cascaded operation only. With cascaded counters clock totermlnal count propagation delays, count enables
(PE or TE)-to-clock set-up times, and count enables (PE or TE)-to-clock hold times determine max. clock frequency. For
example with these HC ge.vices:
= 21 MHz (min.)
f ma• (CP) 210
CP-to-TC prop. delay + TE-to-CP setup + TE-to-CP Hold
37 + 10 + 0
MR Pulse Width
.
tw
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _._ _ _ _ _ Technical Data
CD54/74HC/HCT160, CD54/74HC/HCT161
CD54/74HC/HCT162, CD54/74HC/HCT163
SWITCHING CHARACTERISTICS (Cl = 50 pF, Input t" tf = 6 n8)
LIMITS
CHARACTERISTIC
TEST
CONDITION
Propagation Delay
tPlH
CP to TC
tPHl
CPto an
tPHL
tPlH
tPlH
TE to TC
-
MR to an,
tPHl
tPHl
(160,161)
MR to TC
tPHl
Output Transition
ITlH
Time
trHl
Input Capacitance
C,N
-55°C to +125°C
UNITS
HC
Vee
V
_40° C to +85° C
25°C
74HC
HCT
54HC
74HCT
54HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
2
4.5'
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-
10
-
10
-
-
-
-
-
-
10
-
10
10
10
-
-
-
-
-
63
59
48
75
75
22
-
-
-
42
39
32
50
50
15
-
-
-
-
-
280
56
48
280
56
48
180
36
31
315
63
54
315
63
54
110
22
19
53
49
40
63
63
19
-
230
46
39
230
46
39
150
30
26
265
53
45
265
53
45
95
19
16
185
37
31
185
37
31
120
24
20
210
42
36
210
42
36
75
15
13
-
-
-
-
-
ns
ns
ns
ns
ns
ns
pF
'--r--~-r--------------~-Qn
r---------------~--_+--Qn
m ---1----j----,
"" CONNECT TO VDD FOR 163 AND 162
92CM-379!59
CP
Fig. 3 - Detail of flip-flops for all types.
_________________________________________________________________ 211
Technical Data ______________________________
CD54/74HC/HCT160, CD54/74HC/HCT161
CD54/74HC/HCT162, CD54/74HC/HCT163
Transition times, propagation delay times, setup, hold, and recovery times.
1 , . - - - INPUT LEVEL
GND
CP
ANY
OUTPUT
ANY
CP
OUTPUT
t;;-___________trvs_
I NPUT LEVEL
GND
92CS-37967
I NPUT LEVEL
MR
-INPUT
TE
GND
LEVEL
GND
INPUT LEVEL
CP
TC
'----GND
92CS - 37968RI
'TLH
92CS-379SS
INPUT
LEVEL
INPUTS
PO, PI
P2. P3
GND
INPUT
LEVEL
SPE
TE
or
GND
PE
GND
CP
GND
INPUT
LEVEL
CP
92CS-37969RI
92CS-37966R2
Input Level
V,
CD54174HC
CD54174HCT
Vee
3V
0.5 Vee
1.3 V
212 ______________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC/HCT160, CD54/74HC/HCT161
CD54/74HC/HCT162, CD54/74HC/HCT163
Timing diagrams for the CD54/74HC/HCT160 and 162.
Sequence illustrated in waveforms
1. Reset outputs to zero.
2. Preset to BCD seven.
U
MASTER RESET (160)
3. Count to eight, nine, zero, one, two, and three.
4. Inhibit.
(ASYNCHRONOUS)
I
MASTER RESET (162) ~--(:-:S~Y:-:-NC:-:H-:-:R:-:O~N-OU-S:-:-)--------------
m
U
PO..J
PRESET
DATA
INPUTS
..J
P2 ..J
PI
P3
(160)
CP
CP
COUNT
I
ENABLESL
PE
TE
00
1
---I
I
I---I"I!-_ _ _ _.....
02
I~
OUTPUTS
~
03 _
__
I
1
TC
I
01 _ _ _
I
I~------------~--------------
I
I
I
I
_____I~~I~~I~r-1~~-~~-----~
rl~!-9-0---2-.~31·------~·1
•
RESET PRESET
COUNT
INHIBIT
92CM-37963RI
________________________________________________________________ 213
TechnicaIOala----------------------------
CD54/74HC/HCT160, CD54/74HC/HCT161
CD54/74HC/HCT162, CD54/74HC/HCT163
Timing diagrams for the CD54174HCIHCT161 and 163.
Sequence Illustrated In waveforms
1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, flfleen, zero, one, and two.
4. Inhibit.
U
MASTER RESET fl61)
MASTER RESET
(ASYNCHRONOUS)
(I~)~~(-SY-N-C-HR-O-N-O-U-S)------------------------
SPE
:
LJr-------------------------------
PO ____;I-________________________________________
PRESET
DATA
INPUTS
PI
P2..J
P3-.J
CP
(161)
CP
'I
PE
COUNT {
ENABLES
I
II
TE
00___
QI
OUTPUTS
Q2- -
I
I I
-1 ~I-I--!I--------_
----I
Q3 _ _
TC
I
I
I
.;...---1- - - - - - .
I
I
1
~----J
1~
12
~-__=_::_:_:_:-:-::---
141
.....-----:-:-:-:-:_:_=__----
RESET PRESET
92CM-37962
214 ________________________________________________________
_______________________________ Technical Data
File Number
1658
CD54/74HC164
CD54/74HCT164
High-Speed CMOS Logic
OSl
01
a-Bit Serial-ln/Paraliel-Out Shift Register
6
02
03
Type Features:
10
04
11
-as
12
13
06
07
00
4
5
OS2
MR
CP-----'
VCC
~
GNO~
• Buffered Inputs
• Asynchronous Master Reset
• Typical 'MAX = 60 MHz @ Vee = 5V, C L = 15 pF, TA = 25 0 C
14
7
92CS-38499
FUNCTIONAL DIAGRAM
The RCA-CD54/74HC164 and CD54/74HCT164 are 8-bit
serial-in parallel-out shift registers with asynchronous reset.
Data is shifted on the positive edge of Clock (CP). A LOW on
the Master Reset (MR) pin resets the shift register and all
outputs go to the LOW state regardless of the input conditions.
Two Serial Data inputs (DS1 and DS2) are provided, either one
can be used as a Data Enable control.
The RCA CD54174HC164 are supplied in 14-lead ceramic
dual-in-line packages (F suffix). The CD74HC/HCT164 are
supplied in a 14-lead plastic dual-in-line plastic package
(E suffix) and in 14-lead dual-in-line surface mount plastic
packages (M suffix). The CD54/74HC/HCT164 are also
supplied in chip form (H suffix).
CP
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85 0 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
N IL =30%,N'H=30% of Vee;@ Vee=5 V
• CO 54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'L=0.8 V Max., V'H=2 V Min.
CMOS Input Compatibility
I,SI uA @ VOL, VOH
00
92CM-38501R2
Fig. 1 - Logic diagram for the CD54174HC164, C054/74HCT164
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 215
Technical Data ___________________________________________________________
CD54/74HC164
CD54/74HCT164
MODE SELECT - TRUTH TABLE
Operating
Mode
Reset (Clear)
Shift
Wi
L
H
H
H
H
Inputs
CP DS1 DS2
X
X
X
I
I
J
h
.f I
h
I
f
h
h
J
00
L
L
L
L
H
Outputs
01 L
qo qo qo qo -
-
07
L
q.
q6
q6
q6
H=HIGH voltage level.
h=HIGH voltage level one setup time prior to the LOW-to-HIGH
clock transition.
L=LOW voltage level.
I=LOW voltage level one setup time prior to the LOW-to-HIGH
clock transition.
q=Lower case letters indicate the state of the reference input
(or output) one setup time prior to the LOW-to-HIGH
clock transition.
X=Don't care.
=LOW-to-HIGH clock transition.
D
Q
R----------------------~
92CS-38500RI
FLIP FLOP DETAIL
r
MAXIMUM RATINGS. AbsOlute-Maximum Yalues:
DC SUPPLY-VOLTAGE, (Ved:
(Voltages referenced to ground) ......••..•.•......•••.•••••...•......•...•................•........•........ -0.5 to +7 V
DC INPUT DIODE CURRENT, l,dFOR V,
-0.5 V OR V,
Vee+0.5 V) .........•..•...........•..•..•........•........... ±20 rnA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo -D.5 V OR Vo
Vee +0.5 V) ........•..... , .......••.•............•...•.... ±20 rnA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V
Vo
Vee + 0.5 V) ......•.......................... , ..••....•..... ±25 rnA
DC Vee OR GROUND CURRENT (led .•...••••.......•..............•...•...•.••...•...•......•...•...•••...•..... ±50 rnA
POWER DISSIPATION PER PACKAGE (P D):
For T A = -40 to +60° C (PACKAGE TYPE E) .•••........•........•.........•••......•.....•.•........ , .•.•......... 500 mW
For TA + +60 to +85°C (PACKAGE TYPE E) .........•...•....••....•...................... Derate Linearly at 8 mW/oC to 300mW
For T A = -55 to +100° C (PACKAGE TYPE F, H) •..••...••...••...•....••...••..•••..••...••....•••••.•.•••......... 500 mW
For TA = +100 to +125°C (PACKAGE TYPE F, H) •....•............................... , ••... Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +70° C (PACKAGE TYPE M)
. .. . . . . .. . . .. . . .. . .. .. . . . . . .. .. . . .. . . . .. . . .. . . . .. . . .. . .. . . . . . .. . .. . . . . . . ... 400 mW
For TA = +70 to +125° C (PACKAGE TYPE M)
............................................. Derate Linearly at 6 mWr C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE E,. M . , .. , , .....•....•........•.....•...•..•.•......•.......................•.....• , .... -40 to +85°C
PACKAGE TYPE F, H .•....................................•..........................••................ -55 to +125°C
STORAGE TEMPERATURE (T"g) .....•....••....•...•......•..............••.....•......................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ....................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only .........•..•...•.•••....•..•.....•.....................•......•.............• +300° C
<
<
>
<
>
<
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability. nominal operating conditions shOUld be selected so that operation is always within the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA-Full Package-Temperature Range) Vee :CD54!74HC Types
CD54!74HCT Types
DC Input or Output Voltage V" Vo
Operating Temperature T A:
CD74 Types
CD54 Types
Input Rise and Fall Times t" tf
at 2 V
at 4.5 V
at 6 V
LIMITS
MIN.
2
4.5
MAX.
6
UNITS
V
a
5.5
Vee
-40
-55
+85
+125
°C
a
a
a
1000
500
400
ns
V
-Unless otherwise specified, all voltages are referenced to Ground.
216 ___________________________________________________________________
-----------------------------------------------------------TechnicaIData
CD54/74HC164
CD54/74HCT164
STATIC ELECTRICAL CHARACTERISTICS
CD74HCl641CD54HCl64
CD74HCTl641CD54HCTl64
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-55/
+85°C
+125"C
+85 D C
+l25"C
UNITS
CHARACTERISTIC
+25°C
VI
10
Vee
V
mA
V
+25D C
VI
Vee
V
V
Min Typ Ma. Min Ma. Min Ma.
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
VIL
Output Voltage
VOH
CMOS Loads
or
-0.02
VIH
2
1.5
-
-
1.5
-
1.5
-
4.5
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
-
Low-Level
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
VOL
6
-
-
1.8
-
1.8
-
1.8
CMOS Loads
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
Input Leakage
Current
or
6
5.9
-
-
5.9
-
5.9
-
VIH
-
2
-
V
-
-
O.B
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
.0.1
-
±1
-
±1
pA
5.5
-
-
8
-
80
-
160
pA
-
100
360
-
450
-
490
pA
to
VIL
4.5
3.98
-
-
3.84
-
3.7
-
or
VIH
-5.2
6
5.48
-
-
5.34
-
5.2
-
VIH
2
-
-
0.1
-
0.1
-
0.1
VIL
0.02
4.5
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
VIH
VIH
VIL
or
4
4.5
-
-
0.26
-
0.33
-
0.4
or
VIH
5.2
6
-
-
0.26
-
0.33
-
0.4
VIH
±1
Any
Voltage
between
Vee
Vee
II
2
VIL
VIL
TTL Loads
-
5.5
-4
or
-
4.5
-
ar
VIL
Output Voltage
2
to
5.5
VIL
TTL Loads
Min Typ Ma. Min Max Min Ma.
4.5
or
6
-
-
±O.1
-
±1
-
&
Gnd
Quiescent
Vee
Device
Current
Gnd
or
Ice
Vee
0
6
-
-
8
-
80
-
160
or
Gnd
Gnd
4.5
Additional
Quiescent
Vec-2.1
Device Current
to
5.5
per input pin:
1 unit load
ll.lcc
-For dual-supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT Inpul Loading Table
Inpul
Date Shift-In (1,2)
MR
Clock
Unit Loads·
0.3
0.9
0.7
·Unlt Load IS ll.lce limit specified in Static Characteristic Chart,
e.g., 360 pA max. @ 25"C.
___________________________________________________________________ 217
Technical D a t a - - - - - - - - - - - - -_________________
CD54/74HC164
CD54/74HCT164
SWITCHING CHARACTERISTICS (Vee=5 V, T A=25°C, Inpul In 1,=6 ns)
Typical
CHARACTERISTIC
SYMBOL
CL
UNITS
pF
54n4HC
54/74HCT
Maximum Clock Frequency
15
fMAX
60
54
MHz
Propagation Delay:
15
t PU-1• tPHL
14
15
ns
15
tpHL
11
16
ns
-
C,o
47
49
pF
CP to an
MA to On
Power DIssipation Capacitance
CPO is used to determine the dynamic power consumption, per device.
Po:: Cpo Vcd fl + I (CL Vcd fa) where:
f l :: input frequency.
fa:: output frequency.
CL = output load capacitance.
Vee = supply voltage.
PREREQUISITE FOR SWITCHING FUNCTION
-40° C to +85 0 C
25°C
CHARACTERISTIC
SYMBOL
Vee
HCT
HC
Min.
Max.
Min.
74HC
Max.
Min.
Max.
-55°C to +125°C
74HCT
Min.
Max.
54HC
Min.
Max.
54HCT
Min.
UNITS
Max.
Maximum Clock
Frequency
fMAX
4.5
27
30
24
MR Pulse Width
4.5
18
12
15
CP Pulse Width
4.5
16
6
14
Setup Time
20
18
4.5
15
ns
24
27
ns
18
ns
90
15
13
10
27
20
75
12
12
18
120
23
17
60
tsu
MHz
15
100
80
tw
18
90
23
13
10
20
24
75
60
tw
22
28
35
18
15
Hold Time
tH
4.5
tREM
4.5
MR to CP
Removal Time
ns
100
80
t6
16
20
14
17
DS1
DS2
00
01
02
120
20
24
24
ns
20
14 Vee
13 Q7
12
11
06
05
10 04
03
MR
GND
ep
TERMINAL ASSIGNMENT
218 _____________________________________________
_____________________________________________________________ TechnicaIOata
CD54/74HC164
CD54/74HCT164
SWITCHING CHARACTERISTICS (C l =50 pF, Inpul I" 1,= 6 ns)
-400 C to +85° C
25°C
CHARACTERISTIC
Vee
Max.
Min.
Max.
MIn.
Max.
2
-
170
-
-
-
212
-.
Max.
tpLH
-
-
-
255
-
-
tPHl
4.5
-
34
-
36
-
43
-
45
-
51
-
54
6
-
29
-
-
-
36
-
-
-
43
-
-
HC
MIn.
Propagation Delay,
CP to On
Max.
Min.
74HCT
54HC
MIn.
Max.
-
140
-
-
-
175
-
-
-
-
28
-
38
-
35
-
46
-
210
-
42
-
57
tPHl
6
-
24
-
-
-
30
-
-
-
36
-
-
2
-
75
-
-
-
95
-
-
-
110
-
-
tTLH
4.5
-
15
-
15
-
19
-
19
-
22
-
22
tTHL
6
-
13
-
-
-
16
-
-
-
19
-
-
-
-
10
-
10
-
10
-
10
-
10
-
10
C,
UNITS
54HCT
2
Qulpul
Input Capacitance
74HC
HCT
4.5
MR to an
Transition Time
_55° C 10 +125° C
SYMBOL
ns
ns
ns
pF
Transition times, propagation delay times. setup. hold times, and removal times.
052 ( 1 J
INPUT
,r---- INPUT
LEVEL
MR
LEVEL
GND
GND
tpHL
ANY
INPUT LEVEL
OUTPUT
CP
~
'----GND
92CS-38397RI
CP _ _ _ _ _ _ _ _.....ifVs _
INPUT LEVEL
GND
92CS-37967RI
OS 211 )
CP
DS 1(2)
ANY
OUTPUT
CP
'----GND
92CS-37964
92C5-38398
54/74HCT I
INPUT LEVEL
SWITCHING VOLTAGE, Vs
3V
1.3 V
I
I
______________________________________________________________________ 219
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC165
CD54/74HCT165
File Number
1672
High-Speed CMOS Logic
DO
Dl
D2
PARALLEL
DATA
INPUTS
D3
11
a-Bit Parallel-Inl Serial-Out Shift Register
12
13
14
Type Features:
D4
D5
D6
D7
DS
Pi:
CE
CP
4
5
6
9
07} SERIAL
_
OUTPUTS
07
10
vcc =
GND
=
•
•
•
•
Buffered Inputs
Asynchronous Parallel Load
Complementary Outputs
Typical 'MAX = 60 MHz @ Vee = 5\/, C L
cc
15 pF, TA ~ 25° C
16
8
92CS- 38537
FUNCTIONAL DIAGRAM
The RCA-C054/74HC165 and C054174HCT165 are 8-bit
parallel or serial-in shift registers with complementary serial
outputs (Q7 and 07) available from the last stage. When the
parallel load (PL) input is LOW, parallel data from the DO to
07 inputs are loaded into the register asynchronously.
When the PI. is HIGH, data enters the register serially at
the OS input and shifts one place to the right (QO-Q1-Q2,
etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the
Q7 output to the OS input of the succeeding device.
For predictable operation the LOW-to-HIGH transition of
CE should only take place while CP is HIGH. Also, CP and
CE should be LOW before the LOW-to-HIGH transition of
PL to prevent shifting the data when "PL goes HIGH.
The C054HC/HCT165 devices are supplied in 16-lead
hermetic dual-in-line ceramic packages (F suffix). The
C074HC/HCT165 devices are supplied in 16-lead dual-inline plastic packages (E suffix) and in 16-lead dual-in-line
surface mount plastic packages (M suffix). Both types are
also available in chip form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 30%, N,H = 30% of Vee: @ Vee = 5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
VIL = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, <:: 1 fJA @ VOL, V OH
PL
16 Vee
ep
15
D.
1.\ 03
13
D5
12
D6
GND
D2
D1
" DO
D7
-Q7
Ce
7
10
OS
07
TERMINAL ASSIGNMENT
220 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
_____________________________________________________________ TechnicaIData
CD54/74HC165
CD54/74HCT165
CL
07
07
92CM-38538R2
Fig. 1 - Logic diagram for the CD54/74HC165 and
CD54/74HCTI65.
TRUTH TABLE
Operating
Modes
Parallel Load
Serial Shift
Hold "Do
Nothing"
Inputs
On Register Outputs
PL CE CP OS 00-07 00 01-06 07 07
L-L
L
X X X
L
L
L H
H-H
H L
L
X X X
H
H
H L .F I
X
L qO-q5 q, q,
H
L
h
X
H qO-q5 q, Cj6
.r
H
H
X
X
X
qo
q,-q,
q,
q,
H = HIGH voltage level
h = HIGH voltage level one setup time prior to the LOWto-HIGH clock transition.
L = LOW voltage level.
I = LOW voltage level one setup time prior to the LOWto-HIGH clock transition.
qn ~ Lower case letters indicate the state of the referenced
output one set-up time prior to the LOW-to-HIGH clock
transition.
X ~ Don't care.
J~ LOW-to-HIGH clock transition.
___________________________________________________________________ 221
Technical Data
CD54/74HC165
CD54/74HCT165
STATIC ELECTRICAL CHARACTERISTICS
CD74HC165/CD54HC165
TEST
CONDITIONS
CD74HCT165/CD54HCT165
74HC/54HC
74HC
54HC
TYPES
TYPE
TYPE
+25°':
·401
+85°C
-551
+125°C
TEST
CONDITIONS
74HCT/54HCT
74HCT
54HCT
TYPES
TYPE
TYPE
+25°C
-401
+85°C
-551
+125°C
CHARACTERISTIC
UNITS
V,
V
10
mA
V"
V
V,
V
V,,
V
Min Typ Max Min Max Min Max
High-level
Input Voltage
4.5
V,"
1.5
1.5
1.5
3.15
3.15
3.15
to
4.2
4.2
4.2
5.5
Low-Level
Input Voltage
High-Level
Output Voltage
4.5
V"
V"
Va"
CMOS Loads
or
-0.02
4.5
V,"
4.5
0.5
0.5
0.5
1.35
1.35
1.35
to
1.8
1.8
1.8
5.5
Low-Level
Output Voltage
1.9
1.9
4.4
4.4
4.4
or
5.9
5.9
5.9
V,"
3.98
3.84
3.7
or
5.48
5.34
5.2
V,"
-4
V,"
-5.2
CMOS Loads
or
4.5
0.02
4.5
V,"
input Leakage
V"
Current
or
0.8
V
4.5
4.4
4.5
3.98
4.4
4.4
V
0.1
0.1
0.1
0.1
0.1
0.1
or
0.1
0.1
0.1
V,"
0.26
0.33
0.4
or
0.26
0.33
0.4
V,"
il
Any
Voltage
Between
-
-
3.84
-
3.7
V
V"
4.5
0.1
0.1
V
04
If
il
il
pA
80
160
pA
490
pA
0.1
V"
4.5
or
V,"
0.8
V"
V"
TTL Loads
0.8
V"
or
V"
Va'
V
4.5
1.9
V"
TTL Loads
Min Typ Max Min Max Min Max
5.2
-
:+.:0.1
il
4.5
-
0.26
5.5
-
:to.1
-
0.33
-
V"
&Gnd
Gnd
Quiescent
V"
Device
or
Current
Icc
Additional
Quiescent
Device Current
per input pin:
1 unit load
fj.lcc
Gnd
V"
80
160
or
5.5
Gnd
4.5
Vcc 2.1
to
100 360
-
450
-
5.5
·For dual-supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Unit Loads'
0.35
0.65
'Unit Load is L'.lcc limit specified in Static Characteristic
Chart, e.g., 360 pA max. @ 25 0 C.
222 _________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC165
CD54/74HCT165
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE. (Vee):
.......... -0.5 to + 7 V
(Voltages referenced to ground) ........................................................... .
±20mA
DC INPUT DIODE CURRENT. 1,K (FOR V. < -0.5 V OR V. > Vee +0.5V) ......................... .
DC OUTPUT DIODE CURRENT. 10K (FOR Vo < -0.5 V OR Vo ;'- Vee to.5V) ................................................ . ±20mA
±25mA
DC DRAIN CURRENT. PER OUTPUT (10) (FOR -0.5 V < Vo --:: Vee + 0.5V) .......... .
DC Vee OR GROUND CURRENT (Ieel .................................................................................. ±50mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60° C (PACKAGE TYPE E) ............................................................................ 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) .............................................. Derate Linearly at 8 mW/oC to 300 mW
For TA = -55 to +100°C (PACKAGE TYPE F. H) ........................................................................ 500 mW
For TA = +100 to +125°C (PACKAGE TYPE F. H) ..................•...............•....... Derate Linearly at 8 mW;oC to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) .......................................................................... 400 mW
For TA = +70 to +125°C (PACKAGE TYPE,M) ............................................. Derate Linearly at 6 mW/oC 10 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F. H ......................................................................................... -5510 +125°C
PACKAGE TYPE E. M ." ......... , ..................................................................... , . . . . . .. -4010 +85° C
STORAGE TEMPERATURE (T".) ................................................................................ -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At dislance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ..................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in .. 1.59 mm)
with solder contacting lead tips only ..................................... .
........................................ +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operaling conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA ~ Full Package-Temperature Range) Vee:'
CD54/74HC Types
CD54174HCT Types
DC Input or Output Voltage V,. Vo
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t,. tf
at2 V
at 4.5 V
at6V
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
-40
-55
+125
0
0
0
1000
500
400
ns
TYPICAL
HC
HCT
UNITS
V
V
+85
°C
'Unless otherwise specified. all voltages are referenced to Ground.
SWITCHING CHARACTERISTICS (Vee = 5 V, T A = 25° C, Input t" tf = 6 ns)
CHARACTERISTIC
CL
(pF)
SYMBOL
Propagation Delay
CPto 07
15
tPHL
13
17
ns
tPLH
14
17
ns
12
14
ns
17
24
pF
PLto 07
15
D7 to 07
15
Power Dissipation Capacitance'
·C PO is used to determine the dynamiC power consumption, per package.
Po
I,
Cpr, VCC 2
t, . !
input frequency
(CL Vee 2 fol where:
-
Cpo
to
CL
output frequency
output load capacitance.
Vee : supply voltage.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 223
Technical Data
CD54/74HC165
CD54/74HCT165
PRE-REQUISITE FOR SWITCHING FUNCTION
CHARACTERISTIC
SYMBOL
Vee
CP Pulse Width
tWL
tWH
P[ Pulse Width
tWL
Set-up Time
OS to CP
tsu
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
CE to CP
00-07 to
PL
t SUIU
tsu
Hold Time
OS to CP
orCE
tH
CE to CP
IH
Recovery Time
-PL to CP
Maximum Clock
Pulse Frequency
tREe
f MAX
25°C
HCT
HC
Min. Max. Min. Max.
80
16
18
14
80
16
20
14
80
16
20
14
80
16
20
14
80
16
20
14
35
7
7
6
0
0
0
0
100 20
20
17
6
30
27
35
~-
-40°C 10 +85°C
74HC
74HCT
Min. Max. Min. Max.
100 20
23
17
100 20
25
17
100 20
25
17
100 20
25
17
100 20
25
17
45
9
9
8
0
0
0
0
125 25
25
.21
5
24
22
28
-55° C 10 +125° C
UNITS
54HCT
54HC
Min. Max. Min. Max.
120 ns
24
27
20
120 24
30
ns
20
120
-24
ns
3D
-20
120 24
30
ns
20
120 24
30
ns
20
55
11
11
ns
9
0
ns
0
0
0
150 30
ns
30
26
4
20
MHz
18
24
-
SWITCHING CHARACTERISTICS (C L =50 pF, Input l"t,=6 nsl
CHARACTERISTIC
SYMBOL
Vee
Propagation Delay
CP or CE to
Q7 or Q7
t PLH
t PHL
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-
PL to Q7 or
t PLH
t pHL
Q7
0710 Q7 or
Q7
t PLH
tPHL
hLH
Output Transition
Time
Input Capacitance
hHL
C,
-
_40° C 10 +85° C
25°C
-55°C to +125°C
74HC
HCT
HC
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
i50 165
205
33
41
50
40
50
60
ns
43
28
35
175 220 - 265 35
40
44
ns
50
53
60
30
37
45
150 190 225 ns
44
45
30
35
38
53
26
33
38
75
110 95
15
19
15
19
22
22
ns
13
16
19
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
-
10
-
10
-
10
-
10
-
10
-
-
-
-
-
-
-
-
-
-
-
-
pF
224 ______________________________________________________________________
_____________________________________________________________ TechnicaIData
CD54/74HC165
CD54/74HCT165
PL
(a) SERIAL-SHIFT MODE
(b) PARALLEL-LOAD MODE
92CS-38539
92C$- 38540
--------INPUTLEVEL
,-----INPUT LEVEL
I-'F~----GND
INPUTS 00-07
tsu +
___-1-_
'----GND
INPUT LEVEL
PL
(e) PARALLEL-LOAD MODE
(d) PARALLEL-LOAD MODE
92C5-38542
92C5-38541
-----.Ir------'I/------INPUTLEVEL
GND
GND
(fl SERIAL-SHIFT MODE
(el SERIAL-SHIFT MODE
(d-p.-
CE INHIBITED
~N:~T LEVEL
'su
CP
/
CE
'su(LI
------INPUT LEVEL
INHIBITED
''--------GN D
(9) SERIAL-SHIFT, CLOCK-INHIBIT MODE
92CM-38543R2
Fig. 2 -
Switching waveforms for the C054174HC165 and the C054174HCT165
______________________________________________________________________ 225
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC166
CD54/74HCT166
File Number
1501
High-Speed CMOS Logic
DS
DO
D1
D2
D3
16
15
14
Vee
D7
13 Q7
12
Type Features:
D6
Cl'
11 D5
ep
10 04
GND
8-Bit Paraliel-ln/Serial-Out Shift Register
PE
•
•
Buffered inputs
Typical fMAX = 50 MHz @ Vee
=5V,
CL
= 15 pF,
TA
= 25°C
MR
92CS 36819
TERMINAL ASSIGNMENT
The RCA-CD54174HC166 and CD54/74HCT166 8-bit shift
register is fabricated with silicon gate CMOS technology. It
possesses the low power consumption of standard CMOS
integrated circuits, and can operate at speeds comparable
to the equivalent low power Schottky device.
The CD54174HCT166 is functionally as well as pin
compatible with the standard 54LS174LS166.
The 166 is an 8-bit shift register that has fully synchronous
serial or parallel data entry selected by an active LOW
Parallel Enable (PE) input. When the PE is LOW one setup
time before the LOW-to-HIGH clock transition, parallel data
is entered into the register. When PE is HIGH, data is
entered into internal bit position Qo from Serial Data Input
(DS), and the remaining bits are shifted one place to the
right (Qo - Q1 - Q2, etc.) with each positive-going clock
transition. For expansion of the register in parallel to serial
converters, the Q7 output is connected to the DS input of the
succeeding stage.
The clock input is a gated OR structure which ~ws one
input to be used as an active LOW Clock Enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The LOW-toHIGH transition of CE input should only take place while
the CP is HIGH for predictable operation.
Family Features:
•
•
•
•
•
•
•
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85° C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
Alternate Source is PhilipslSignetics
CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity: NIL = 30%, NIH = 30% of Vce;
@ Vee = 5 V
CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
VIL = O.B V Max., VIH = 2 V Min.
CMOS Input Compatibility
I, :S 1 jJA @ VOL, V OH
A LOW on the Master ResetWR) input overrides all other
inputs and clears the register asynchronously, forcing all
bit positions to a LOW state.
The CD54HC166 and CD54HCT166 are supplied in 16-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC166 and CD74HCT166 are supplied in 16-lead
dual-in-line plastic packages (E suffix) and in 16-lead dualin-line surface mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
226 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC166
CD54/74HCT166
92.CL-37095f12
Fig. 1 - Logic diagram.
00
01
02
03
04
05
06
07
MR~------------------~
92CS-37096RI
Fig. 2 - Functional diagram.
TRUTH TABLE
Inputs
Internal
Parallel
o States
Do 07
0001
Master
Reset
Parallel
Enable
Clock
Enable
Clock
L
X
X
X
X
X
L
H
X
L
L
X
X
000
H
L
L
.-r
X
a ... h
b
h
H
H
L
.-r
H
X
H
OOn
06n
H
H
L
....r
L
X
L
OOn
06n
H
.-r
X
X
000
H
I
X
Serial
a
L
010
010
Output
07
L
00
070
H = high level (steady state).
a ... h = the level of steady-state input at inputs Do thru 07, respectively.
L = low level (steady state).
000, al0, 070 = the level of 00, 01, or 07, respectively, before the indicated
X = irrelevant (any input, including transitions).
steady-state input conditions were established .
.-r =transition from low to high level.
OOn, a6n =the level of 00 or a6, respectively, before the most recent I
transition of the clock.
______________________________
~---227
Technical Data
CD54/74HC166
CD54/74HCT166
STATIC ELECTRICAL CHARACTERISTICS
CD74HCl66/CD54HC166
CD74HCT166/CD54HCT166
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85"C
+125"C
+85"C
+125"C
CHARACTERISTIC
UNITS
+25°C
V,
V
10
mA
Vee
V
+25"C
V,
V
Vee
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
4.5
V"'
1.5
1.5
1.5
3.15
3.15
3.15
to
4.2
4.2
4.2
5.5
Low-Level
Input Voltage
High-Level
Output Voltage
4.5
V"
CMOS Loads
or
-0.02
0.5
0.5
0.5
1.35
1.35
1.35
to
1.8
1.8
1.8
5.5
1.9
1.9
V"
4.4
4.4
or
5.9
5.9
5.9
V",
4.5 3.98
3.84
3.7
or
5.48
5.34
5.2
V"'
Low-Level
Output Voltage
or
-4
V,"
-5.2
6
0.02
4.5
0.1
0.1
0.1
V"
0.1
0.1
0.1
or
0.1
0.1
0.1
V,"
0.26
0.33
0.4
or
0.26
0.33
0.4
V,,,
:to.l
±1
±1
Any
Voltage
Between
V"
VOL
CMOS Loads
or
V,"
or
V,"
Input Leakage
4.5
5.2
Vcr.
Current
4.5
4.4
4.5
3.98
0.8
4.4
08
V
4.4
V
-
4.5
-
3.84
0.1
-
3.7
V
0.1
V
0·'
V
,1
,1
J1A
80
160
J1A
450
490
J1A
0.1
V"
V"
TTL Loads
0.8
V"
V"
TTL loads
V
4.5
1.9
6
V,"
4.5
4.5 "4.4
V"
V,,"
Min Typ Max Min Max Min Max
-
or
4.5
-
0.26
5.5
-
.:to 1
-
0.33
-
Vee
Quiescent
Oevice
Current
Gnd
& Gnd
V"
Vee
or
Icc
80
0
160
or
5.5
Gnd
Gnd
4.5
Additional
Quiescent
Device Current
per input pin:
fj. Icc
1 unit load
Vcc2 .1
to
100
360
-
5.5
-For dual-supply systems theoretical worst case (VI
=2.4 V, Vee = 5.5 V) specification IS 1.8 mAo
HCT Input Loading Table
Input
Unit Loads·
DS, DO-D7
0.2
0.35
0.5
0.2
PE
CP,CE
MR
*Umt Load IS .6.lcc limit specified In Static Characteristic Chart,
e.g .. 360 J1A max. @ 25" C.
228 ______________________________________________________________
~---
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC166
CD54/74HCT166
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ..................................................................................... -0.5 to + 7 V
DC INPUT DIODE CURRENT, I'K (FOR Vi < -0.5 V OR V, > Vee +0.5V) ......................................................... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V) ..................................................... ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V) ...................................................... ±25mA
DC Vee OR GROUND CURRENT (Icc) ...................................................................................... ±50mA
POWER DISSIPATION PER PACKAGE (Po):
For T A = -40 to +60° C (PACKAGE TYPE E) ................................................................................ 500 mW
For T A = +60 to +85° C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW;o C to 300 mW
. ....................................... 500 mW
For T A = -55 to +100° C (PACKAGE TYPE F, H) .................
For TA = +100 to +125°C (PACKAGE TYPE F, H) .............................................. Derate Linearly at 8 mW/oC to 300 mW
ForT. = -40 to +70°C (PACKAGE TYPE M) ......... , .................................................................... 400 mW
For T. = +70 to +125° C (PACKAGE TYPE M) ............ , .......... , ................ " ....... Derate Linearly at 6 mW/o C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .......... ,.................................................................................. -55 to +125° C
PACKAG E TYPE E, M .............................................................................................. -40 to +85° C
STORAGE TEMPERATURE (T",) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ......................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ..................................................................................... +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within the
following ranges:
LIMITS
UNITS
CHARACTERISTIC
MIN.
MAX,
Supply Voltage Range (For TA = Full Package Temperature Range) Vee:CD54174HC Types
2
6
V
CD54/74HCT Types
4.5
5.5
V
0
Vee
V
DC Input or Output Voltage VIN, VOUT
Operating Temperature TA:
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
0
1000
ns
0
500
ns
0
400
ns
Input Rise and Fall Times, tr, tf
at 2 V
at 4.5 V
at 6 V
SWITCHING CHARACTERISTICS (Vce = 5 V, T. = 25°C, Input t" t, = 6 ns)
CHARACTERISTIC
Propagation Delay-
t pLH
Clock to 0
t pHL
f MAX
Maximum Clock Frequency
Power Dissipation Capacitance'
-Cpo
IS
Cpo
Typical
Cl
pF
HC
HCT
15
13
17
ns
15
-
50
41
50
' 41
MHz
pF
Units
used to determine the dynamic power consumption, per package.
Po=Cpo Vee' f, + I (Cl Vee' fo) where:
f,=input frequency
fo=output frequency
Cl =output load capacitance
Vee=supply voltage
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 229
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC166
CD54/74HCT166
PRE-REQUISITE FOR SWITCHING FUNCTION
LIMITS
TEST
CONDITION
CHARACTERISTIC
Clock Frequency
Imax
Fig. 3
MR Pulse Width
tw
Fig. 4
Clock Pulse Width
tw
Fig. 3
Set-up Time
2
HCT
-
25
20
20
16
6
35
29
23
125
-
2
100
-
150
-
4.5
20
35
25
44
30
53
6
17
21
26
120
-
2
80
-
100
-
4.5
16
20
20
25
24
30
6
14
17
-
20
2
-
100
20
20
120
24
24
-
20
-
1
-
Clock, Fig. 5, 6
6
14
-
Fig. 5
Removal Time
tREM
MR to Clock
Fig. 4
Set-up Time
tsu
PE to CP
Fig. 6
Hold Time
tH
PE to CP or CE
Fig. 6
54HCT
25
16
tH
54HC
30
80
16
Data to Clock,
74HCT
4.5
4.5
Hold Time
74HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
5
4
6
Data and CE to
Isu
-55°C 10 +125°C
UNITS
HC
Vee
V
_40° C 10 +85° C
25°C
MHz
ns
-
2
1
-
17
1
4.5
1
0
1
0
1
0
6
1
1
1
0
-
2
0
-
0
-
4.5
0
0
0
0
0
0
6
0
0
-
0
ns
ns
ns
-
2
145
-
180
-
220
-
4.5
29
30
36
38
44
45
6
25
-
2
0
-
31
0
-
38
0
-
4.5
6
0
0
0
0
0
0
0
-
0
-
0
-
ns
ns
ns
SWITCHING CHARACTERISTICS (CL = 50 pF, Inpul I. I, = 6 nsl
LIMITS
TEST
CONDITION
CH.ARACTERISTIC
UNITS
HCT
HC
Vee
V
Propagation Delay
tPLH
Clock to Output
tPHL
Time
54HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
160
-
4.5
32
40
200
-
240
-
40
50
48
60
41
27
-
34
75
-
95
-
110
-
tTHL
4.5
15
15
19
19
22
22
6
13
-
16
-
19
-
2
160
-
200
-
240
-
4.5
32
40
40
50
48
60
6
27
-
34
-
41
-
10
10
10
10
10
10
tPHL
Fig. 4
230
54HC
2
MR to Output
Input Capacitance
74HCT
6
Fig. 3
Propagation Delay
74HC
tTLH
Fig. 3
Output Transition
2
_55° C 10 +125° C
_40° C 10 +85° C
25°C
C.
ns
ns
ns
pF
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC166
CD54/74HCT166
INPUT LEVEL
Vs
- - - - - - - - GND
INPUT LEVEL
CP
GND
1,..----
INPUT
cp----4---------~
Q7---,ij
Q7----
92CS-;'7127RI
92CS-37126RI
I
I
I
54n4HC
54n4HCT
INPUT LEVEL
Vee
3.0V
Vs
50% Vee
1.3V
I
I
I
INPUT LEVEL
Fig. 4 - Master reset pre-requisite times and propagation delays.
Fig. 3 - Clock pre-requisite times and propagation and output
transition times.
PE
RO
IT
INPUT
LEVEL
INPUT LEVE L
OATA
LEVEL
GND
INPUT LEVEL
CP
GND
CP
92CS-37129
GND
92CS - 3712BRI
I
INPUT LEVEL
Vs
INPUT LEVEL
I
I
54n4 HC
Vee
50% Vee
T 54/74 HCT l
T 3.0V I
l 1.3V I
Fig. 6 - Parallel enable or clock enable pre-requisite times.
Fig. 5 - Data pre-requisite times.
________________________________________________________________ 231
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC173
CD54/74HCT173
File Number
1641
High-Speed CMOS Logic
E1
E2
DO
01
02
03
cp
3
13
4
12
5
11
6
7
Quad D-Type Flip-Flop, 3-State
00
Positive-Edge Triggered
01
02
Type Features:
03
MR
• 3-state buffered outputs
• gated input and output enables
OEl
O E 2 - - - - - - ' 92CS-38456
FUNCTIONAL DIAGRAM
The RCA CD54/7 4HC173 and CD54/7 4HCT173 high speed
3-STATE QUAD D TYPE FLIP-FLOPS are fabricated with
silicon gate CMOS technology. They possess the low
power consumption of standard CMOS Integrated circuits,
and can operate at speeds comparable to the equivalent low
power Schottky devices. The buffered outputs can drive 15
LSTTL loads. The large output drive capability and 3STATE feature make these parts ideally suited for interfacing with bus lines in bus oriented systems.
The four D TYPE FLIP-FLOPS operate synchronously from
a common clock. The outputs are in the 3-STATE mode
when either of the two output disable pins are at the logic
"1" level. The input ENABLES allow the flip-flops to remain
in their present states without having to disrupt the clock. If
either of the 2 input ENABLES are taken to a logic "1" level,
the Q outputs are fed back to the inputs, forcing the flip
flops to remain in the same state. Reset is enabled by taking
the MASTER RESET (MR) input to a logic "1"level. The data
outputs change state on the positive going edge of the
clock.
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85 0 C
• BalancedPropagation Delay and Transition Times
• Significant Power Reduction Compared to
LSTTL Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V operation
High Noise Immunity: ML = 30%, MH = 30% of Vee
@ Vee = 5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'L = 0.8 V max .. V'H = 2 V Min.
CMOS Input Compatibility
I, ::; 1 iJA @ VOL, VOH
The CD54/74HCT173 logic family is functionally as well as
pin compatible with the standard 54LS/74LS logic family.
The CD54HC173 and CD54HCT173 are supplied in 16-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC173 and D74HCT173 are supplied in 16-lead dualin-line plastic packages (E suffix) and in 16-lead dual-in-line
surface mount plastic packages (M suffix). Both types are
also available in chip form (H suffix).
OEl
OE2
1
16 Vee
2
15 MR
00
14 DO
01
13 01
02
12 02
03
1, 03
ep
10
E2
GND
9
E1
TERMINAL ASSIGNMENT
232 ____________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC173
CD54/74HCT173
12
3 CIRCUITS IDENTICAL TO ABOVE CIRCUIT
IN DASHED ENCLOSURE
020--------1
11
030--------1
92CM-38458RI
Fig. 1 - Logic diagram for the CD54/74HC/HCT173.
92CS-38457
Flip-Flop Detail
TRUTH TABLE
Inputs
Data Enable
Data
Output
MR
CP
E1
E2
0
Q
H
L
L
L
L
L
X
L
X
X
H
X
L
L
X
X
X
H
L
L
X
X
X
X
L
H
L
00
00
00
L
H
J'"
...r~
~
When either DEt or OE2 (or both) is (are) high the output is disabled to
the high-impedance state, however, sequential operation of the flip-flops
is not affected.
H
L
= high level (steady state)
= low level (steady state)
~
=
=
X don't care (any input including transitions)
00 the level of 0 before the indicated steady-state
= low-to-high level transition
input conditions were established.
______________________________________________________ 233
Technical
Data~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC173
CD54/74HCT173
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE (Vee):
(Voltages referenced to ground) .................................................................................. -0.5 to +7 V
DC INPUT DIODE CURRENT, 1,K (FOR V, < -0.5 V OR V, > Vee +0.5 V) .................................................. ± 20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Va < -0.5 V OR Vo > Vee +0.5 V) .............................................. ± 20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Va < Vee +0.5 V) ...........................................•.... ± 35 mA
DC Vee OR GROUND CURRENT (Icc) .................................................................................. ± 70 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60°C (PACKAGE TYPE E) ........................................................................... 500 mW
For T. = +60 to +85°C (PACKAGE TYPE E) ............................................. Derate Linearly at 8 mWfOC to 300 mW
For T. -55 to +100°C (PACKAGE TYPE F, H) ....................................................................... 500 mW
For T. +100 to +125°C (PACKAGE TYPE F, H) ........................................ Derate Linearly at 8 mWfOC to 300 mW
For T A = -40 to +70° C (PACKAGE TYPE M) ............................................................................. 400 mW
ForT. = +70 to +125°C (PACKAGE TYPE M) ............................................... Derate Linearly at 6 mW;oC to 70 mW
=
=
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H ......................................................................................... -55 to +125°C
PACKAGE TYPE E, M ........................................................................................... -40 to +85°C
STORAGE TEMPERATURE (T... ) ................................................................................. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ..................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm) with solder contacting lead tips only ..................... +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within the
following ranges:
LIMITS
CHARACTERISTIC
UNITS
MIN.
MAX.
Supply-Voltage Range (For TA = Full Package Temperature Range) Vee:'
CD54174HC Types
CD54/74HCT Types
DC Input or Output Voltage V" Vo
2
6
V
4.5
5.5
V
0
Vee
V
Operating Temperature T.:
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
0
1000
ns
at 4.5 V
0
500
ns
at6V
0
400
ns
Input Rise and Fall Times, t" tf
at 2V
'Unless otherwise specified, all voltages are referenced to Ground.
234 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
- - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC173
CD54/74HCT173
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT173/CD54HCT173
CD74HC173/CD54HC173
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85'C
+125'C
+85'C
+125'C
CHARACTERISTIC
UNITS
V,
10
Vee
V
rnA
V
+25'C
V,
Vee
V
V
Min Typ Max Min Max Min Max
V,"
Low-Level
Input Voltage
V"
High-Level
Output Voltage
1.5
-
1.5
-
1.5
-
4.5 3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
2
High-Level
Input Voltage
-
V"
VO"
CMOS Loads
or
-0.02
V,"
(Bus Driver)
Low-Level
Output Voltage
-6
V,"
-7.8
CMOS Loads
or
4.5
-
0.02
V,"
2
-
-
0.5
-
0.5
-
0.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5 3.98
-
-
3.84
-
3.7
-
2
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.4
-
-
4.4
-
4.4
-
V
or
4.5 3.98
-
-
3.84
-
3.7
-
V
to
V"
5.48
-
-
5.34
-
5.2
-
V,"
2
-
-
0.1
-
0.1
-
0.1
V"
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
4.5
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±D.l
-
±1
-
±1
/lA
5.5
-
-
8
-
80
-
160
/lA
/lA
V"
6
4.5
-
-
0.26
-
0.33
-
0.4
or
(Bus Driver)
V,"
7.8
6
-
-
0.26
-
0.33
-
0.4
V,"
Input Leakage
Vee
±1
Any
Voltage
Between
Vee
I,
-
5.5
or
Current
-
4.5
-
6
V"
TTL Loads
2
to
5.5
V"
or
V"
Yo,
Min Typ Max Min Max Min Max
4.5
V"
TTL Loads
+25'C
or
6
-
-
±0.1
-
±1
-
&
Gnd
QL'iescent
Vee
Vee
Device
Current
Gnd
or
Icc
a
6
-
-
-
8
80
-
160
or
Gnd
Gnd
Additional
Quiescent
Device Current
per input pin:
1 unit load
6.lcc
3-State Leakage
Current
1o,
4.5
Vee -2.1
to
-
100 360
-
450
-
490
-
-
-
±5.0
-
±10
5.5
V"
or
V,"
Vo=Vcc
or
6
-
-
±0.5
Gnd
-For dual-supply systems theoretical worst case (VI = 2.4 V, Vee
-
±5.0
-
±lD
V"
or
V,"
5.5
.cO.5
/lA
=5.5 V) specification is 1.B rnA.
HCT Input Loading Table
Input
Unit Loads'
00-03
0.15
E1 & E2
0.15
CP
0.25
MR
0.2
OE1 & OE2
0.5
..
'Unit Load is Alec limit specified In Static Characteristic Chart, e.g., 360 /lA max. @ 25°C.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 235
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC173
CD54/74HCT173
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 2S·C, Inpul I. If = 6 ns)
CHARACTERISTIC
Propagation Delay,
tPlH
Clock toO
Propagation Delay,
tpHl
tplZ
Output Disable. and Enable to
a
tPHZ
tPZl
TYPICAL
Cl
(pF)
HC
HCT
15
17
18
ns
15
12
12
ns
15
12
14
ns
UNITS
tPZH
Maximum Clock Frequency
f max
-
60
60
MHz
Power Dissipation Capacitance'
Cpo
-
29
34
pF
'Cpo is used to determine the dynamic power consumption, per package.
Po = Cpo Vee2 f;+ I Cl Vee2 f.
where: f; = input frequency, fo = output frequency,
Cl = output load capacitance, Vee = supply voltage.
PREREQUISITE FOR SWITCHING FUNCTION
LIMITS
CHARACTERISTIC
TEST
CONDITION
25°C
Maximum Clock
Frequency
2
f max
Fig. 3
MR Pulse Width
tw
Fig.4
Clock Pulse Width tw
Fig. 3
Set-up Time
Data to Clock
Fig. 5
tsu
Set-up Time
Eto Clock
tsu
Hold Time
Data to Clock
Fig. 5
tH
Hold Time
Eto Clock
tH
Removal Time
MR to Clock
tREM
-55°C 10 +12S o C
74HC
S4HC
UNITS
HC
Vee
V
-40°C 10 +8S o C
HCT
74HCT
S4HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
5
4
6
-
-
-
4.5
30
20
24
16
20
13
6
35
-
28
-
24
-
2
80
-
100
-
120
-
4.5
16
15
20
19
24
22
6
14
-
17
-
-
-
2
80.
-
100
-
20
120
4.5
16
25
20
31
24
38
6
14
-
17
-
20
-
2
60
-
75
-
90
-
4.5
12
12
15
15
18
18
6
-
15
-
13
75
-
2
10
60
-
9Q
-
4.5
12
18
15
23
18
27
6
10
13
15
-
2
3
-
3
-
4.5
3
0
3
0
3
0
6
3
-
3
3
-
0
-
3
2
0
-
0
-
4.5
0
0
0
0
0
0
6
0
0
-
-
2
60
-
75
-
0
90
4.5
12
12
15
15
18
18
6
10
-
13
-
15
-
MHz
ns
ns
ns
ns
ns
ns
ns
236 ____________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC173
CD54/74HCT173
SWITCHING CHARACTERISTICS (VL = 50 pF, Input t" t. = 6 ns)
LIMITS
CHARACTERISTIC
TEST
CONDITION
Propagation Delay
Clock to Output
200
-
-
-
250
-
-
-
300
-
-
tPHL
40
-
50
-
54
-
60
-
65
6
-
34
-
43
-
-
43
-
-
-
51
-
-
2
-
175
-
-
-
220
-
-
-
265
-
-
4.5
-
35
-
37
-
44
-
46
-
53
-
56
6
-
30
-
-
-
37
-
-
-
45
-
-
225
-
-
45
-
45
-
tPHL
tpLZ
Capacitance
2
-
150
-
-
-
190
-
-
4.5
-
30
-
30
-
38
-
38
-
-
38
-
-
-
225
-
-
44
-
45
-
53
-
-
38
-
-
-
-
-
90
-
-
-
15
-
18
-
18
-
-
15
-
6
-
26
-
-
-
33
tPZL
2
-
150
-
-
-
190
tPZH
4.5
-
30
-
35
38
6
-
26
ITLH
2
-
60
-
75
tTHL
4.5
-
12
-
-
12
-
15
-
-
-
13
-
6
-
10
C,
-
-
10
Co
-
-
20
Fig. 3
3-State Output
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
-
Fig.6
Input Capacitance
54HCT
-
Output Enable to Q tPHZ
Time
54HC
4.5
Fig.4
Output Transition
74HCT
2
Fig. 3
Propagation Delay,
74HC
HCT
tPLH
Propagation Delay
MR to Output
-55°C to +125°C
UNITS
HC
Vee
V
-40°C to +85°C
25°C
10
-
20
33
10
-
20
10
-
20
10
-
20
-
ns
ns
ns
ns
ns
10
pF
20
pF
INPUT
LEVEL
Q---92CS-38487
Fig. 4 - Master reset pulse width. Master reset to output delay
Fig. 3 - Clock to output delays and clock pulse width.
and master reset to clock recovery time.
INPUT
LEVEL
tsU(H"'Ir-_ __
92CS- 36954RI
Fig. 5 - Data set-up and hold times.
OUTPUTS
CONNECTED
OUTPUTS
CONNECTED
92CS-38488
Fig. 6 - Transition times and propagation delay times.
_________________________________________________________________ 237
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC174
CD54/74HCT174
File Number
1608
High-Speed CMOS Logic
CP -L;>O----.----1
Hex D-Type Flip-Flop with Reset
Positive-Edge Triggered
Type Features:
• Buffered Positive-Edge- Triggered Clock
• Asynchronous Common Reset
05
92CS-38437
FUNCTIONAL DIAGRAM
The RCA-CD54174HC174 and CD54174HCT174 are edge
triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low
power and speeds comparable to low power Schottky TTL
circuits. The devices contain 6 master-slave flip-flops with a
common clock and common reset. Data on the D input
having the specified setup and hold times is transferred to
the Q output on the low to high transition of the CLOCK
input. The MR input, when low, sets all outputs to a low
state.
Each output can drive 10 low power Schottky TTL equivalent loads. The CD54174HCT174 is functionally as well as
pin compatible to the 54LS174/74LS174.
The CD54HC174 and CD54HCT174 are supplied in 16-lead
hermetic dual-in-Iine ceramic packages (F suffix). The
CD74HC174 and CD74HCT174 are supplied in 16-lead
dual-in-line plastic packages (E suffix) and in 16-lead
dual-in-line surface mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85 0 C
• Balanced Propagation and Transition Times
• Significant Power Reduction Compared to
LSTTL Logic ICs
• Alternate Source is Philips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 30%, MH = 30% of Vee;
@ Vee = 5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V max., V,H = 2 V Min.
CMOS Input Compatibility
I, ::; 1 /JA @ VOL, VO H
j---CL-----------&-----ONE.OF-SIX-F/Fi
I
I
3(4,6,11,13,14)10
~
I
I
I
I
a 12 (5,7,10,12,15)
I
I
IL__ R
Cp
_ __________________________
:>O-........- - - - - - - - - + - - T O OTHER FIVE
o--D~--------+---TO
an
I
~
F/F
OTHER FIVE F/F
Fig. 1 - Logic diagram (Flip/Flop detail)
92CM-3843BRI
238 ___________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC174
CD54/74HCT174
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) .................................................................................. -0.5 to +7 V
DC INPUT DIODE CURRENT, 1,K (FOR V, < -0.5 V OR V, > Vee +0.5 V) .................................................. ± 20 rnA
DC OUTPUT DIODE CURRENT, 10K (FOR Va < -0.5 V OR Va > Vee +0.5 V) .............................................. ± 20 rnA
DC DRAIN CURRENT, PER OUTPUT (1 0 ) (FOR -0.5 V < Vo < Vee +0.5 V) ................................................ ± 25 rnA
DC Vee OR GROUND CURRENT (lee): ................................................................................. ± 50 rnA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60°C (PACKAGE TYPE E) ........................................................................... 500 mW
For T. = +60 to +85°C (PACKAGE TYPE E) ............................................. Derate Linearly at 8 mW/oC to 300 mW
For T. -55 to +100°C (PACKAGE TYPE F, H) ....................................................................... 500 mW
For T. = +100 to +125°C (PACKAGE TYPE F, H) ......................................... Derate Linearly at 8 mW/oC to 300 mW
=
For T.: -40 to +70°C (PACKAGE TYPE M) ............................................................................. 400 mW
For T A.: +70 to +125°C (PACKAGE TYPE M) ............................................... Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H ......................................................................................... -55 to +125°C
PACKAGE TYPE E, M........................................................................................... -40 to +85°C
STORAGE TEMPERATURE (T".) ........................................................................ · .. ······ -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ..................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm) with solder contacting lead tips only ..................... +300°C
TRUTH TABLE
(EACH FLIP-FLOP)
OUTPUTS
INPUTS
RESET
CLOCK
DATA
(MR)
CP
Dn
an
L
x
X
L
H
~
H
H
H
~
L
L
H
L
X
00
H = High Level (Steady State)
L = Low Level (Steady State)
X Irrelevant
f i Transition from Low to High Level
00, Level Before the Indicated Steady-State
Input Conditions were established
=
Me
,
16 Vee
as
00
15
00
14 05
13 04
0'
12 04
A'
02
11 03
02
10 03
GND
cp
TOP VIEW
TERMINAL ASSIGNMENT
=
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within the
following ranges:
LIMITS
MIN.
MAX,
UNITS
2
4.5
6
5.5
V
DC Input or Output Voltage V" Va
0
Vee
V
Operating Temperature T A:
CD74 Types
CD54 Types
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
CHARACTERISTIC
Supply-Voltage Range (For TA
= Full Package Temperature Range) Vee:'
CD54/74HC Types
CD54/74HCT Types
Input Rise and Fall Times, t" tf
at 2V
at 4.5 V
at6V
'Unless otherwise specified, all voltages are referenced to Ground.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 239
Technical Data _________________________________
CD54n4HC174
CD54n4HCT174
STATIC ELECTRICAL CHARACTERISTICS
CD74HC174/CD54HC174
CD74HCT174/CD54HCT174
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
CHARACTERISTIC
UNITS
V,
10
Vee
V
mA
V
+25°C
V,
Vee
V
V
Min Typ Max Min Max Min Max
Min Typ Max Min Max Min Max
High-Level
Input Voltage
V,"
Low~Level
Input Voltage
V"
High-Level
Output Voltage
1.5
-
4.5 3.15
6
4.2
2
V"
VO"
CMOS Loads
or
-0.02
V,"
-
1.5
-
1.5
-
-
-
3.15
-
3.15
-
-
-
4.2
-
4.2
-
Low-Level
Output Voltage
-4
V,"
-5.2
CMOS Loads
or
0.02
V,"
Input Leakage
-
-
0.5
-
0.5
-
0.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5 3.98
-
-
3.84
-
3.7
-
or
5.48
-
-
5.34
-
5.2
-
V,"
6
Current
-
0.1
-
0.1
-
0.1
V"
4.5
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
Current
Icc
4
4.5
-
-
0.26
-
0.33
-
0.4
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
Any
Voltage
Between
Vee
&
Gnd
or
6
-
-
±0.1
-
±1
-
±1
6
-
-
8
-
80
-
160
2
-
V
to
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
'3.7
-
V
4.5 3.98
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
pA
or
5.5
-
-
8
-
80
-
160
pA
4.5
to
5.5
-
100 360
-
450
-
490
pA
Gnd
Gnd
Vee -2.1
input pin:
1 unit load
-
Vee
0
Additional
Quiescent
Device Current
p~r
2
V"
or
or
-
V"
-
Vee
Device
-
5.5
-
Gnd
Quiescent
2
4.5
-
2
Vee
I,
to
5.5
2
V"
TTL Loads
-
V"
or
V"
VOL
4.5
4.5
V"
TTL Loads
+25°C
tolee
·For dual-supply systems theoretical worst case (V,
..
=2.4 V. Vee =5.5 V) specification
is 1.8 rnA.
HCT Input Loading Table
Input
Unit Loads·
CP
0.80
0.55
0.15
MR
D
·Unit load is fl.lcc limit specified in Static Characteristic Chart. e.g .• 360 iJA max. @ 25°C.
240 ___________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC174
CD54/74HCT174
PREREQUISITE FOR SWITCHING FUNCTION
LIMITS
CHARACTERISTIC
TEST
CONDITION
Clock Pulse
Width
tw
Fig. 3
MR
Pulse Width
tw
Fig.4
Setup Time Data
to Clock
tsu
Fig.5
Hold Time Data
to Clock
tH
Fig. 5
Removal Time
MR to Clock
trem
Fig. 4
Clock Frequency
f max
-55°C \0 +125°C
74HC
54HC
UNITS
HC
Vee
V
-40°C \0 +85°C
25°C
HCT
74HCT
54HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
2
80
-
-
-
100
-
-
-
120
-
-
-
4.5
16
-
20
-
20
-
25
-
24
-
30
-
6
14
-
-
17
-
-
-
20
-
-
2
80
-
-
100
-
-
-
120
-
-
-
4.5
16
-
25
-
20
-
31
-
24
-
38
-
6
14
-
-
-
17
-
-
-
20
-
-
2
60
-
-
75
-
-
-
90
-
-
-
15
-
20
18
-
24
-
13
-
-
15
-
-
2
5
-
-
-
5
-
-
5
-
-
4.5
5
-
5
5
-
5
-
5
-
5
6
5
-
-
5
-
-
-
5
-
5
-
-
5
-
18
-
5
-
-
-
-
-
4.5
12
6
10
16
-
2
5
-
-
-
5
-
-
4.5
5
-
12
-
5
-
15
6
5
-
-
-
5
-
-
-
5
-
-
-
4
24
28
-
20
-
-
-
20
24
2
6
-
-
4.5
6
30
35
-
25
-
-
ns
ns
ns
-
ns
-
17
-
-
-
ns
MHz
SWITCHING CHARACTERISTICS (CL =50 pF, Inpul I" I, =6 ns)
LIMITS
CHARACTERISTIC
TEST
CONDITION
25°C
Propagation Delay
Clock to 0
-MRtoO
Time
74HCT
54HC
54HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tPLH
-
165
-
-
-
-
-
250
-
-
-
33
-
40
-
205
4.5
41
-
50
-
50
-
60
6
-
28
-
-
-
35
-
-
43
-
-
225
-
-
55
-
45
-
66
-
38
-
-
tPLH
2
-
150
-
-
4.5
-
30
-
44
-
190
t PHL
6
-
26
-
-
-
33
38
hLH
2
-
75
-
-
-
95
-
-
-
110
-
-
trHL
4.5
-
15
15
-
19
-
19
-
22
-
13
-
-
16
-
-
-
19
-
22
6
-
-
10
-
10
-
10
-
10
-
10
-
10
Fig.6
Input Capacitance
74HC
t PHL
Fig.4
Output Transition
HCT
2
Fig.3
Propagation Delay
-55°C 10 +125°C
UNITS
HC
Vee
V
-40°C 10 +85°C
C 'N
ns
ns
ns
pF
______________________________________________ 241
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC174
CD54/74HCT174
SWITCHING CHARACTERISTICS (Vee =5 V, T.. =25°C, Inpul I. I, =6 ns)
CHARACTERISTIC
Propagation Delay Clock to
a
HC
15
13
17
ns
15
12
18
ns
-
38
44
pF
UNITS
tPLH
Fig.3
tPHL
Propagation Delay -
tPLH
Fig. 4
t PHL
MR toO
Typical Values
HCT
CL
(pF)
Power Dissipation Capacitance'
Cpo
'Cpo is used to determine the dynamic power consumption, per flip-flop.
Po = Cpo Vee2 f; + L (CL Vee2 fo) where: f; = input frequency, fo = output frequency,
CL = output load capacitance, Vee = supply voltage
INPUT
LEVEL
INPUT
LEVEL
t rem
CP
92CS-38444
92CS-37198
Input Level
Vs
Fig. 3 - Propagation delay times and clock pulse width.
Fig. 4 - Prerequisite and propagation delay times for master reset.
INPUT
LEVEL
tsutH~'r-_ __
Q
Vs
92CS- 36954RI
92CS -38443
Input Level
Vs
I
I
1
Fig. 5 - Pre
54174HC
Vee
50% Vee
I
I
I
54/74HCT
3V
1.3 V
I
I
I
Fig. 6 -
Transition times.
242 _____________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _Technical Data
File Number
1474
CD54/74HC175
CD54/74HCT175
High-Speed CMOS Logic
Quad 0 Flip-Flop with Reset
Type Features:
•
•
•
•
•
Common Clock and Asynchronous Reset on four D- Type Flip-Flops
Positive-edge pulse triggering
Complementary Outputs
Buffered Inputs
Typical f MAX =50 MHz @ Vee =5 V, C L =15 pF, TA =25 0 C
FUNCTIONAL DIAGRAM
The RCA CD54/74HC175 and the CD54/74HCT175 are
high speed Quad D-Type Flip-Flops with individual 0inputs and Q, Q complementary outputs. The devices are
fabricated using silicon gate CMOS technology. They have
the low power consumption advantage of standard CMOS
ICs and the ability to drive 10 LSTTL devices.
Information at the 0 input is transferred to the Q and Q
outputs on the positive-going edge of the clock p·ulse. All
four Flip-Flops are controlled by a common clock (CP) and
a common reset (MR). Resetting is accomplished by a low
voltage level independent of the clock. All four Q outputs
are reset to a logic a and all four Ooutputs to a logic 1.
The CD54HC175 and CD54HCT175 are supplied in 16-lead
dual-in-line ceramic packages (F suffix) and the
CD74HC175 and CD74HCT175 are supplied in 16-lead
dual-in-line plastic packages (E suffix) and in 16-lead dualin-line surface mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
Family Features:
•
•
•
•
•
•
•
Fanout luver Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85 0 C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
Alternate Source is PhilipslSignetics
CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity: NIL =30%, NIH =30% of Vee; @
Vee = 5 V
CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
VIL = 0.8 V Max., VIH = 2 V Min.
CMOS Input Compatibility
I, ::; 1 pA @ VOL, VOH
i----------------=-ON'E=OF:f:OUR-F:F:----j
I
I
13(6,1 1 ,14)
1
Q
1
1
1
1
CL
CL
4(5,12, 13)1
o
1
I
:
I
12(7,10,15)
Q
IL _ _ R
_ _ _ _ _ _ _ _ _ _ _ _ _CP
_ _ _ _ _ _ _ _ _ _ _ _ _ _ J1
1
MRo--C> Vee +0.5V) ......................................................... ±20mA
DC. OUTPUT CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V) ............................................................ ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V) ...................................................... ±25mA
DC Vee OR GROUND CURRENT (Icc) ...................................................................................... ±50mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60°C (PACKAGE TYPE E) ................................................................................ 500 mW
For T. = +60 to +85° C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/o C to 300 mW
ForT. = -55 to +lOO°C (PACKAGE TYPE F, H) ..................... , ...................................................... 500 mW
For T. = +100 to +125°C (PACKAGE TYPE F, H) .............................................. Derate Linearly at 8 mW/OC to 300 mW
For T. = -40 to +70°C (PACKAGE TYPE M) .............................................................................. 400 mW
For T. = +70 to +125°C (PACKAGE TYPE M) ................................................. Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H ............................................................................................. -55 to +125°C
PACKAGE TYPE E, M .............................................................................................. -40 to +85° C
STORAGE TEMPERATURE (T",,) .................................................................................... -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ......................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ..................................................................................... +300° C
RECOMMENDED OPERATING CONDITIONS:
For maximum rellablllty;-nomTniifcond-ltions-should be selected so that operation Is always within the following ranges:
LIMITS
CHARACTERISTIC
UNITS
MIN.
MAX.
Supply Voltage Range (For TA = Full Package Temperature Range) Vee:"
CD54/74HC Types
2
6
V
CD54174HCT Types
4.5
5.5
V
a
Vee
V
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
a
a
a
1000
ns
500
ns
400
ns
DC Input or Output Voltage VIN, VOUT
Operating Temperature TA:
Input Rise and Fall Times, tr, It
at2V
at 4.5 V
at 6 V
.
"Unless otherwise specified, all voltages are referenced to Ground .
TRUTH TABLE
(EACH FLIP-FLOP)
.
OUTPUTS
INPUTS
MR
16 Vee
00
15 03
00
14
03
RESET
(MR)
CLOCK
CP
DATA
On
an
On
L
X
X
L
H
Qi
1102
H
..F
H
H
L
01
10 Q2
H
f
L
L
H
GND
CP
X
Qo
Qo
DO
D1
13
12
D3
D2
92CS36822
H
L
H = High Level (Steady State)
L = Low Level (Steady State)
X = Irrelevant
.r = Transition from Low to High Level
Qo, Qo = Levels Before the Indicated Steady-State
244
Input Conditions were Established
TERMINAL ASSIGNMENT
Technical Data
CD54/74HC175
CD54/74HCT175
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT175/CD54HCT175
CD74HCl 75/CD54HCl 75
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85°C
+125°C
+B5°C
+125°C
UNITS
CHARACTERISTIC
+25°C
V,
V
10
rnA
V"
V
+25°C
V,
V
Vee
V
Min
Min Typ Max Min Max Min Max
High-Level
Input Voltage
4.5
V,"
1.5
1.5
1.5
4.5
315
3.15
3.15
10
4.2
4.2
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V OH
CMOS Loads
or
0.5
4.5
1.35
1.35
1.35
to
6
1.8
1.8
1.8
5.5
V,"
1.9
19
1.9
V"
4.4
4.4
4.4
or
5.9
5.9
5.9
V,"
3.98
3.84
3.7
or
5.48
5.34
5.2
V,"
V"
TTL Loads
Low-Level
Output Voltage
-4
V,"
-5.2
CMOS Loads
or
45
0.02
4.5
V,"
0.1
0.1
0.1
0.1
0.1
0.1
or
0.1
0.1
0.1
V,"
0.26
0.33
0.4
0.26
0.33
0.4
V,"
±1
Any
Voltage
Between
V"
TTL Loads
4
V,"
5.2
Vee
Current
or
4.5
4.4
4.5
3.98
0.8
0.8
4.4
V
4.4
V
~
~
3.84
~
3.7
V
V"
4.5
0.1
0.1
0.1
V
0.4
V
±1
±1
/lA
80
160
/lA
450
490
/lA
V"
or
Input Leakage
0.8
V"
or
V"
Voc
4.5
0.5
4.5
V
5.5
0.5
V"
-0.02
4.2
Typ Max Min Max Min Max
4.5
~
::t:O.l
±1
or
4.5
5.5
~
~
0.26
:to.l
~
0.33
~
Vee
Gnd
Quiescent
Vee
DeVice
or
Current
lee
& Gnd
Vee
a
80
160
or
5.5
Gnd
Gnd
4.5
Additional
QUiescent
Device Current
per Input pin"
1 unit load
I:::.. Icc
Vcc-2.1
to
100 360
5.5
-For dual-supply systems theoretical worst case (V, = 2.4 V, Vee
=5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
Unit Loads'
MR
1.0
0.15
0.6
D
CP
Unit Load IS .6. Icc lim,t specified
e.g., 360 /lA max. @ 25°C.
In
Static Characteristic Chart,
______________________________________________________________________ 245
TechnicaIOata _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC175
CD54/74HCT175
PRE-REQUISITE FOR SWITCHING FUNCTION 54/74HC SERIES AND 54n4HCT SERIES
LIMITS
TEST
CONDITION
CHARACTERISTIC
0
UNITS
Clock Pulse
Width
tw
Fig. 3
MR Pulse Width
tw
Fig. 4
Setup Time Data
to Clock
tsu
Fig. 5
Hold Time Data
to Clock
tH
Fig. 5
Removal Time
MR to Clock
tREM
Fig. 4
Clock Frequency
S4HCT
54HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
2
80
-
-
-
100
-
-
-
120
-
16
-
20
-
20
-
25
-
- -
4.5
24
-
30
-
6
14
-
20
-
-
-
80
-
120
-
-
4.5
16
-
20
-
-
2
-
17
6
14
-
-
-
-
-
-
-
2
80
4.5
16
6
14
2
5
4.5
5
6
5
2
5
4.5
5
-
20
17
-
25
-
24
-
-
20
-
120
100
-
-
20
-
25
17
-
5
-
5
-
-
5
-
5
-
5
-
-
100
-
20
5
-
2
6
-
-
4.5
30
-
25
6
35
-
-
6
f max
74HCT
74HC
HCT
HC
Vee
V
-Ssoc to +12S oC
-40 C to +8So C
2SoC
-
-
5
5
5
-
-
-
30
24
-
20
-
30
-
5
-
5
-
-
5
-
-
-
5
-
-
5
-
5
5
5
5
-
ns
ns
ns
-
-
5
5
-
-
-
4
-
-
25
-
20
-
20
-
16
-
-
23
-
-
29
ns
-
ns
-
MHz
SWITCHING CHARACTERISTICS (CL = 50 pF, Input t. It= 6 ns)
LIMITS
TEST
CONDITION
CHARACTERISTIC
25 0 C
-55 0 C to + 125 0 C
UNITS
HC
Vee
V
-400 C to +850 C
HCT
74HC
54HC
74HCT
54HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay
tpLH
2
-
175
-
-
-
220
-
-
-
265
-
Clock to Q or Q
tpHL
4.5
35
-
33
-
44
-
41
-
53
-
50
6
-
30
-
-
-
37
-
-
-
45
-
-
Fig. 3
-
Propagation Delay
tPLH
2
-
175
-
-
-
220
-
-
-
265
-
-
(MR)toQ orO
tPHL
4.5
-
.35
-
40
-
44
-
50
53
-
60
6
-
30
-
-
-
37
-
-
-
45
-
hLH
2
75
-
-
-
95
-
-
-
110
-
hHL
4.5
-
-
15
-
15
-
19
-
19
-
22
-
22
13
-
-
-
16
-
-
-
19
-
-
-
10
-
10
-
10
-
10
-
10
-
10
Fig. 4
Output Transition
Time
Fig. 6
Input Capacitance
6
CI
ns
ns
ns
pF
246 ______________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data.
CD54/74HC175
CD54/74HCT175
SWITCHING CHARACTERISTICS (Vee = 5 V, TA
=25° C, Inpull" I, =6 ns)
Typical
CL
CHARACTERISTIC
Propagation DelayClock to Q or IT. Fig. 3
Propagation Delay
Fig. 4
MR to Q or
Power Dissipation Capacitance'
tpLH
tpHL
t pHl
t plH
a:
Unils
pF
HC
HCT
15
14
13
ns
15
14
17
ns
65
67
pF
Cpo
'CPo is used to determine the dynamic power consumption. per flip-flop.
Po = CpoVee 2fi+ L CLVee 2fo where fi = input frequency. fo = output frequency.
CL = output load capacitance. Vee = supply voltage
92CS- 36951
Fig. 3 - Propagation delay times and clock pulse width.
INPUT
LEVEL
INPUT
LEVEL
t rem
'Su IH >-
CP
~--Vs
92C5- 3G954RI
In ul Level
Vs
54/74HC
V
50% Vee
92C5- 36952
Fig. 5 - Pre-requisite for clock.
Fig. 4 - Pre-requisite and propagation delay times for master reset.
Q---':'::;""-\
92C5-36953
Fig. 6 - Transition times.
_________________________________________________________________ 247
Technical Data
CD54/74HC181
CD54/74HCT181
File Number 1829
High-Speed CMOS Logic
fUNCTION SELECT
INPUTS
4-Bit Arithmetic Logic Unit
SO 51 'S2 5)\
{
" ,
AI 23
'HORD A
A2 21
43 19
COMPARE
'"'
WORDS{:: ::
RIPPLE
CARRY OUT
93 18
::M:~i~:
C; :
"
1~
,
P
}
LOOK AHEAD
O~~r:.~/TS
'2~S_40200
Type Features:
• Full look-ahead carry for speed operations on long words
• Generates 16 logic functions of two Boolean variables
• Generates 16 arithmetic functions of two 4-bit binary words
• A = B comparator output available (open drain)
• Ripple-carry input and output available
• Available in both narrow- and wide-bodyplastic packages
FUNCTIONAL DIAGRAM
ACTIVE-HIGH DATA
The RCA CD54n4HC181 and CD54n4HCT181 are lowpower four-bit parallel arithmetic logic units (ALU) capable
of providing 16 binar.y arithmetic operations on two four-bit
words and 16 logical functions of two Boolean variables.
The mode control input M selects logical (M=High) or
arithmetic (M=Low) operation. The four select inputs (SQ,
S1, S2, and S3) select the desired logical or arithmetic
functions, which include AND, OR, NAND, NOR, and
exclusive-OR and -NOR in the logic mode, and addition,
subtraction, decrement, left-shift and straight transfer in
the arithmetic mode, according to the truth table. The
HC/HCT181 operation may be interpreted with either
active-low or active-high data at the A and B word inputs
and the function outputs, by using the appropriate truth
table.
The HC/HCT181 contains logic for full look-ahead carry
operation for fast-carry generation using the carry-generate
and carry-propagate outputs G and P forthe four bits of the
HC/HCT181. Use of the HC/HCT182 look-ahead carry
generator in-conjunction with multiple HC/HCT181 s permits
high-speed arithmetic operations on long words. A ripplecarry output C n. . is available for use in systems where
speed is not of primary importance.
Also included in these devices isa comparator output A = B,
which assumes a high level whenever the two four-bit input
words A and B are equal and the device is in the subtract
mode. A=B is an open-drain output that can be wire-AND
connected to give a comparison for more than 4 bits. In
addition, relative magnitude information may be derived
from the carry-in input Cn and ripple carry-out output C n..
by placing the unit in the subtract mode and externally
decoding using the information in the Magnitude Comparison table.
The CD54HC181 and CD54HCT181 are supplied in 24-lead
dual-in-Iine frit-seal ceramic packages (F suffix). The
CD74HC181 and CD74HCT181 are supplied in 24-lead
dual-in-line, narrow-body plastic packages (EN suffix), in
24-lead dual-in-line, wide-body plastic packages (E suffix),
and in 24-lead dual-in-line surface-mount plastic packages
(M suffix). Both types are also available in chip form (H
suffix).
Family Features:
• Fanout (over temperature range):
Standard outputs - 10 LSTTL loads
Bus driver outputs - 15 LSTTL loads
• Wide operating temperature range:
CD74HC/HCT: -40 to +85°C
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL
logiC ICs
• Alternate source is Philips/Signetics
• CD54HC/CD74HC types:
2 to 6 V operation
High noise immunity:
ML=30%, MH=30% of Vee; @ Vcc=5 V
• CD54HCT/CD74HCT types:
4.5 to 5.5 V operation
Direct LSTTL input logic compatibility
V,L=0.8 V max., V'H=2 V min.
CMOS input compatibility
I, :5 1 pA @ VOL, VOH
FUNCTION SELECT
\NPUTS
'so
5" 52 53\
Vee -24
GND=12
COMPARE
OUT
RIPPLE
CARRVOUT
CARRY IN
MODE
M
8
CONTROL
FUNCTIONAL DIAGRAM
ACTIVE-LOW DATA
248. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
______________________________ Technical Data
CD54/74HC181
CD54/74HCT181
8
M
Fig. 1 - Logic diagram.
FUNCTION TABLES
Inputl/Outputl Active High
Inputs/Outputs Active Low
Arithmetic Function
M =L
Function
Logic
Select
Function
Arithmetic Function
M=L
Function
Logic
Select
Function
~3 82 S1 SO
L L L L
M=H
C"=H (no carry)
C"=L (with carry)
A
A plus 1
L L L L
A
C"=L (no carry)
A minus 1
C"=H (with carry)
A
L L L H
A+B
A+B
(A + B) plus 1
L L L H
AB
AB minus 1
AB
S3 1S2 1S1
ISO
M=H
A
L L H L
AB
A+S
(A + S) plus 1
L L H L
A+B
AS minus 1
AS
L L H H
Logic 0
minus 1 (2's compl.)
L L H H
Logic 1
minus 1 (2's compl.)
Zero
L H L L
AB
A plus AB
Zero
A plus AS plus 1
L H L L
""'A""+"B
A plus (A + S)
A plus (A+S) plus 1
L H L H
S
(A + B) plus AS
(A+B)plusASplus1
L H L H
---.L
AB plus (A + B)
ABplus(A+S)plus1
L H H L
A0B
A minus B minus 1
A minus B
L H H L
A0B
A minus B minus 1
A minus B
L H H H
AS
AS minus 1
AS
L H H H
A+S
A+6
(A + S) plus 1
H L L L
A+B
A plus AB
A plus AB plus 1
H L L L
AB
A plus (A + B)
A plus (A+B) plus 1
H L L H
A0B
B
A plus B
(A + B) plus AB
A plus B plus 1
A0B
A plus B
A plus B plus 1
(A+S)plusABplus1
H L L H
H L H L
B
AS plus (A + B)
ASplus(A+B)plus1
H L H H
AB
AB minus 1
AB
H L H H
A+B
A+B
(A + B) plus 1
H H L L
Logic 1
A plus A"
A plus A plus 1
H H L L
Logic 0
A plus A"
A plus A plus 1
H H L H
A+S
(A + B) plus A
(A+B) plus A plus 1
H H L H
AS
AB plus A
AB plus A plus 1
H H H L
A+B
(A + S) plus A
(A+S) plus A plus 1
H H H L
AB
AS plus A
AS plus A plus 1
H H H H
A
A minus 1
A
H H H H
A
A
A plus 1
H L H L
H = High Level
-
L = Low Level
_"_E_a_ch__
b_it_is_s_h_if_te_d__
to_t_h_e_n_e_x_t_m_o_rn__
si~g_n_ifi_c_an_t~p_o_s_it_io_n_.__________________________________________________
249
TechnicaIOala _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54n4HC181
CD54/74HCT181
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) .......•...................•....................................................... " . -0.5 to +7 V
DC INPUT DIODE CURRENT,I'K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ............................................... '.' ...... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR V. < -0.5 V OR V. > Vee +0.5 V) ........•.......................................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (I.) (FOR -0.5 V < V. < Vee +0.5 V) ..................................................... ±25 mA
DC Vee OR GROUND CURRENT (Icc) ...................................................................................... ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60· C (PACKAGE TYPE E) ............................................................................... 500 mW
ForTA = +60 to +65·C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/·C to 300 mW
ForTA = -55 to +100·C (PACKAGE TYPE F,H) ............................................................................. 500 mW
ForTA= +100 to +125°C (PACKAGE TYPE F,H) .............................................. Derate Linearly at 8 mW/·C to 300 mW
For TA = -40 to +70· C (PACKAGE TYPE M) .............................................................................. 400 mW
ForTA= +70 to +125·C (PACKAGE TYPE M) ................................................. Derate Linearly at 6 mW/·C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F,H ............................................................................................. -55 to +125·C
PACKAGE TYPE E,M .............................................................................................. -40 to +85· C
STORAGE TEMPERATURE (T...) .................................................................................... -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max. . .................................................... +265·C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contscting lead tips only ................................................................................... +300· C
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation Is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA=Fuli Package Temperature Range)
Vcc:'
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage, V" Vo
Operating Temperature, T A:
CD74 Types
CD54 Types
Input Rise and Fall Times, t"t,:
at2 V
at 4.5 V
at6 V
LIMITS
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vcc
-40
-55
+85
+125
·C
0
0
0
1000
500
400
ns
V
V
'Unless otherwise specified, all voltages are referenced to Ground.
MAGNITUDE COMPARISON TABLE
Active - High Data
Active - Low Data
Input Output
Magnltuda
Cn
Cn+4
A:5B
1
1
1
0
AB
0
0
0
A~B
1- = High Level
0= Low Level
Input Output
Magnitude
Cn
Cn +4
A:5B
0
0
1
0
AB
0
1
1
A~B
BO
24
Vee
AO
23
A1
53
22
Bl
52
2'
A2
51
20
82
50
'9
A3
en
18
83
"
17
G
16
Cn +4
FO
Fl
10
15
F2
11
'4
A-8
GND
12
13
F3
TOP VIEW
92CS-40202
TERMINAL ASSIGNMENT
250 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
- - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC181
CD54/74HCT181
STATIC ELECTRICAL CHARACTERISTICS
CD74HC1.1/CD54HC1.1
CD74HCT181/CD54HCT181
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
-tt5'C
+125'C
+85°C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
10
Vee
V
rnA
V
High-Level
Input Voltage
1.5
-
-
1.5
4.5 3.15
-
-
3.15
4.2
6
low-Level
Input Voltage
V,L
2
-
4.5
-
8
High-Level
Output Voltage
VO "
CMOS Loads
V'L
or
-0.02
V,"
4.2
-
1.5
Low-Level
Output Voltage
3.15
-
4.2
1.35
0.5
-
0.5
1.35
-
1.35
1.8
-
1.8
-
1.9
CMOS Loads
Device Current
-
-
-
4.4
-
1.9
-
4.4
6
5.9
-
-
-
5.9
-
5.9
-
4.5 3.98
-
3.84
-
3.7
5.48
-
-
5.34
-
5.2
-
V,"
0.1
-
0.1
-
0.1
V,L
0.1
0.1
0.1
or
0.1
-
0.1
V,"
V,"
-5.2
6
2
-
0.02
4.5
-
6
-
-
0.1
-
V'L
or
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.4
-
-
4.4
-
4.4
-
V
4.5 3.98
-
-
3.84
-
3.7
-
V
4.5
or
4
4.5
-
-
0.26
-
0.33
-
0.4
V'L
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
6
-
-
0.1
-
±1
-
±1
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
pA
5.5
-
-
8
-
80
-
160
pA
-
450
-
490
pA
Any
Vee
or
Voltage
Between
Vee & Gnd
Vee
0
6
-
-
8
-
Gnd
80
-
180
or
Gnd
Additional
4.5
Quiescent Device
Vee -2.1
Current per input
pin: 1 unit load
-
V,"
or
or
2
to
1.9
Vee
Icc
-
5.5
4.4
Gnd
Quiescent
-
4.5
-
1.8
Input Leakage
I,
2
to
5.5
0.5
V,L
Current
-
V,L
V,"
TTL Loads
Min Typ MIX Min M•• Min MIX
4.5
2
-4
or
V
4.5
or
V,L
VOL
V
-
V,L
TTL Loads
Vee
Min Typ Max Min M•• Min M••
2
V,"
+25°C
V,
to
-
100 380
5.5
Alee
·For dual-supply systems theoretical worst case (V, = 2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
Unit Loads·
80-83
1
All A and B (Data)
0.75
0.5
M, C.
·Unit Load is .o.lcc limit specified in Static Characteristics
Chart, e.g., 360 pA max. @ 25° C.
____________________________________________________________________ 251
TechnicaIOala _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC181
CD54/74HCT181
SWITCHING CHARACTERISTICS (Vee=S V. T A =2S·C.lnput .....=6 ns)
TYPICAL VALUES
HC
HCT
CL (pF)
CHARACTERISTIC
Propagation Delay: tPLH, tPHL
An or Bn to Cn••
SUM Mode
An or Bn to G
An or Bn to P
An or Bn to Fn
An or Bn to Cn+.
An or Bn to G
DIFFERENCE Mode
An or Bn to P
An or Bn to Fn
An or Bn to A = B
LOGIC Mode
An or Bn to Fn
SUM and
Cn to Cn••
DIFFERENCE Mode
Cn to Fn
Power DissiDation Capacitance'
Cpo
19
18
14
19
20
18
14
20
21
19
13
17
120
15
15
15
15
15
15
15
15
15
15
15
15
-
UNITS
22
23
17
24
23
23
17
24
25
23
18
20
140
ns
pF
'Cpo is used to determine the dynamic power consumption, per package.
Po = Cpo Vee' I, + I CL Vee' I. where I, = input frequency
I. = output frequency
CL = output load capacitance
Vee = supply voltage.
AC Test Setup Reference (Active-Low Data)
Test Delay Times
AC Paths
Inputs
Outputs
SUM,N to SUMOUT
BO
AnyF
SUM,Nto P
AO
P
BO
Cn
Cn
G
Cn..
AnyF
Cn+4
BO
A=B
SUM'Nto G
SUM,N to Cn..
Cn to SUMo UT
Cn to Cn••
SUM,N to A = B
SUM ,N to SUMOUT
(Logic Mode)
SO
All S's
Any F
DC Data Inputs
ToGnd
ToVcC
91, B2, B3, M,
All A's
Cn
11.1, A2, A3, M,
AilS's
Cn
All A's, M, Cn B1,B2,B3
All A's, M, Cn B1,B2,83
AIIA's,M
All 13's
AllA's,M
All B's
All A's, B1,
Cn
B2,B3,M
All A's, Cn
M
Mode'
ADD
ADD
ADD
ADD
ADD
ADD
SUBTRACT
EXCLUSIVEOR
'ADD Mode: SO, S3 = Vee: Sl, S2 = Gnd.
SUBTRACT Mode: SO, S3 = Gnd: Sl, S2 = Vee.
252 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC181
CD54/74HCT181
SWITCHING CHARACTERISTICS (CL = 50 pF, Input t"tf = 6 ns)
LIMITS
CHARACTERISTIC
Propagation Delay,
SUM Mode
An or Bn to Cn..
VCC
(V)
tPLH
tPHL
An or Bn to G
An or Bn to P
An or Bn to Fn
Propagation Delay,
DIFFERENCE Mode
An or Bn to Cn+.
tPHL
tpLH
An or Bn to G
An or Bn to P
An or Bn to Fn
An or Bn to A=B
Propagation Delay,
LOGIC Mode
An or Bn to Fn
Propagation Delay,
SUM & DIFF. Modes
Cn to Cn+4
tPHL
tPLH
tPHL
tPLH
Cn to Fn
Output Transition
Time
trHL
trLH
I nput Capacitance
C,
-40°C to +85°C
_55° C to +125° C
UNITS
74HCT
54HC
54HCT
HC
HCT
74HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
25°C
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-
-
-
-
-
-
-
-
-
-
-
225
45
38
210
42
36
170
34
29
230
46
39
235
47
40
215
43
37
170
34
29
235
47
40
245
49
42
230
46
39
165
33
28
200
40
34
75
15
13
10
-
-
-
53
-
-
-
-
41
58
-
-
-
-
-
-
-
-
-
54
-
55
54
40
57
60
-
54
42
48
-
-
-
15
10
-
-
-
-
-
-
-
-
-
280
56
48
265
53
45
215
43
37
290
58
49
285
59
50
270
54
46
215
43
37
295
59
50
305
61
52
290
58
49
205
41
35
250
50
43
95
19
16
10
-
-
-
-
-
66
-
53
51
58
69
-
-
-
-
-
54
-
50
71
-
-
-
-
-
-
-
-
75
-
-
-
68
-
-
-
-
53
56
19
10
-
-
-
-
-
-
-
345
69
59
315
63
54
255
51
43
345
69
59
355
71
60
325
65
55
255
51
43
355·
71
60
370
74
63
345
69
59
250
50
43
300
60
51
110
22
19
10
-
-
-
-
80
63
62
69
83
-
-
-
-
65
60
-
-
ns
86
90
-
-
81
-
63
68
-
-
-
-
-
22
10
pF
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 253
TechnicaIData _________________________________________________________
CD54/74HC182
CD54/74HCT182
File Number
1830
High-Speed CMOS Logic
7
CARRY
P
PROP·
OUTPUT
10 CARRY
G GEN·
OUTPUT
~
Cnt x
Look-Ahead Carry Generator
Type Feature.:
• Provides carry look-ahead across a group of four ALU s
• Multi-level look-ahead for high-speed arithmetic operation over long
word length
11 Cn+y
'2
9 Cn+t
ANTICIPATED
CARRY
OUTPUTS
FUNCTIONAL DIAGRAM
The RCA-CD54174HC182 and CD54174HCT182 carry lookahead generators are high-speed silicon-gate CMOS
devices and are pin compatible with low-power Schottky
TTL (LSTTL).
Family Fe.ture.:
•
•
The CD54174HC/HCT182 accept up to four pairs of active
!:9W cl!!!y propagate (Po,P, ,p., Pa) and carry generate (Go,
G" G., G3) signals and an active HIGH carry input(C n). The
devices provide antici pated active HI G H carries (Cn+x, Cn+y,
Cn +z ) across four groups of binary adders. The HC/HCT182
also has active LOW carry propagate (P) and carry generate
(G) outputs which may be used for further levels of look
ahead.
The logic equations provided at the outputs are:
Cn+x = PoCn
C n+y = G, + P, Go + P, PoC n
Cn+z = G. + P.G, + P2 P,Go + P.P,PoCn
G = G3 + P3G. + P3P.G, + P3P.P,Go
P = P3P.P,Po
The CD54174HC/HCT182 can also be used with binary
ALUs in an active LOW or active HIGH input operand mode.
The connections to and from the ALU to the carry lookahead generator are identical in both cases.
The CD54HC182 and CD54HCT182 are supplied in 16-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC182 and CD74HCT182 are supplied in 16-lead
dual-in-line plastic packages (E suffix) and in 16-lead dualin-line surface-mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
•
•
•
•
•
Fanout (over temperature range):
Standard outputs - 10 LSTTL loads
Bus driver outputs - 15 LSTTL loads
Wide operating temperature range:
CD74HCIHCT: -40 to +85 0 C
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL
logic ICs
Alternate source is Philips/Signetics
CD54HCICD74HC Types:
2 to 6 V Operation
High noise immunity: ML = 30%, MH = 30% of Vee,
@ Vee = 5 V
CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL input logic compatibility
V'L =0.8 V max., V,H =2 V Min.
CMOS input compatiblity
" :5 1 pA @ VOL. VO H
Gl
16
Vee
PI
'5
P2
GO
PO
3
'4
G2
4
13
Cn
G3
5
'2
C n+x
P3
6
11
Cn+y
P
GND
'0
G
C n+z
TOP VIEW
92CS-40206
TERMINAL ASSIGNMENT
254 _________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC182
CD54/74HCT182
PO
G1
G2
P2
G3
P3
4
Vee -16
GND'8
92CL- 40207
Fig. 1 - Logic diagram.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ..................................................•.•.....•..........•............... -0.5 to + 7 V
DC INPUT DIODE CURRENT, 1,K (FOR V, < -0.5 V OR V, > Vee + 0.5 V) ......•...............•.......•........................ ±20 rnA
DC OUTPUT DIODE CURRENT, 10K (FOR Va < -0.5 V OR Va> Vee + 0.5 V)........ .•....... .... ....... ....•...... ..... .... .. ±20 rnA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Va < Vee + 0.5 V) ..........••.............•.•.....•......•........... ±25 rnA
DC Vee OR GROUND CURRENT (Icc) . . . . . • . . . • .. . . . . . .• . . . . . . .• . . . •. . . . . . .. .. . . . . . . . . . . . . . . . . . . • . . . .. . • . . . . . . . . . . . . . . . . .. ±50 rnA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to tilO· C (PACKAGE TYPE E) .•...•...•..........•.........................•.............•.............•.... 500 mW
For T. = tilO to +85· C (PACKAGE TYPE E) .....•.•.•..........•.....••.........•.......•...• Derate Linearly at 8 mW/· C to 300 mW
For T. = -55 to +100· C (PACKAGE TYPE F, H) ........•..•..•..................................•.........•............... 500 mW
ForT. = +100 to +125·C (PACKAGE TYPE F, H) ...................•.•.•.....•••....•........ Derate Linearly at 8 mW/·C to 300 mW
ForT. = -40 to +70·C (PACKAGE TYPE M) .....•..•..•....................•.....•...........•..••.....•....•.......•..•.. 400 mW
ForT. = +70 to +125·C (PACKAGE TYPE M) ....•..•.....••..........•.............•......... Derate Lineary at 6 mW/·C to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H •..•...•.......•.•.•.....•......•.....•••.....•...•.....•.......••...•..................•.... -55 to +125·C
PACKAGE TYPE E, M ...•...............•.........................•.........•...............•...•.•.................-40 to +85·C
STORAGE TEMPERATURE (Tat.) ...•...••............•..•..•..•..•.•...•..........•.....•.••........•.....•......... -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max .••.•.................•..••.•.......•...........•...•... +265·C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only .••........••.........•...•........•••...•..............•.........•.......•.......• +300·C
___________________________________________________________ 255
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC182
CD54/74HCT182
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation Is always within the
following ranjles:
LIMITS
UNITS
CHARACTERISTIC
MAX.
MIN.
Supply-Voltage Range (For TA = Full Package Temperature Range) Vee:"
CD54174HC Types
2
6
V
CD54174HCT Types
4.5
5.5
V
0
Vee
V
DC Input or Output Voltage V" Vo
Operating Temperature TA:
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
at2 V
0
1000
ns
at 4.5 V
0
500
ns
at6V
0
400
ns
Input Rise and Fall Times, t., t,
..
'Unless otherwise specified, all voltages are referenced to Ground.
FUNCTION TABLE
OUTPUTS
INPUTS
Cn
Go
Po
X
H
H
L
H
L
X
X
L
X
X
X
X
H
H
H
X
X
X
L
X
X
X
H
X
L
X
X
X
X
X
X
X
H
H
H
X
X
X
X
X
L
X
X
X
H
X
L
L
P,
G.
P.
G3
P3
H
H
H
L
H
X
X
L
L
X
X
H
X
L
X
X
X
X
L
L
X
X
X
X
H
H
H
X
X
X
X
X
L
X
X
X
L
X
L
X
X
X
H
Cn+y
G
C n +z
P
L
L
L
H
H
H
X
X
X
H
H
H
X
Cn +x
L
L
H
H
X
X
H
L
G,
X
X
X
H
H
H
H
H
L
X
X
X
X
L
L
L
L
L
L
L
X
X
X
X
X
H
H
H
H
X
L
X
X
X
X
L
L
X
X
X
X
H
X
X
X
X
H
X
X
H
L
L
L
X
H
H
H
H
H
H
H
H
H
L
X
X
X
X
L
L
L
X
X
X
X
X
X
H
L
I
H
H
H
H
L
L
L
L
H
H
H
H
L
X = don't care
H'= HIGH voltage level
L = LOW voltage level
256 _________________________________________________________________
_
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC182
CD54/74HCT182
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT182/CD54HCT182
CD74HC1821CD54HC182
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
UNITS
CHARACTERISTIC
+25°C
V,
V
10
mA
High-Level
Input Voltage
V,"
V"
High-Level
Vo"
V"
or
-0.02
-
0.5
-
0.5
1.35
1.35
-
1.35
1.B
-
1.B
-
1.B
1.9
4.4
5.9
-
V,"
4.2
-
2
-
-
0.5
4.5
-
-
3.15
-
1.9
4.4
6
5.9
-
-
5.9
-
4.5 3.9B
-
3.84
-
3.7
-
V"
or
5.34
-
5.2
-
V,"
-
0.1
0.1
V"
or
0.1
V,"
-
0.4
V"
or
0.4
V,"
6
5.4B
-
V"
or
2
0.1
-
0.1
4.5
-
-
0.02
-
0.1
-
0.1
-
0.1
-
0.1
-
-
0.26
-
0.33
0.26
-
0.33
CMOS Loads
V,"
TTL Loads
V"
or
4
4.5
V,"
5.2
6
6
-
2
-
V
-
-
O.B
-
O.B
-
O.B
V
V"
or
4.4
-
-
4.4
-
4.4
-
V
4.5 3.9B
-
-
3.B4
-
3.7
-
V
4.5
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
pA
5.5
-
-
B
-
BO
-
160
pA
-
100 360
-
450
-
490
pA
Any
Input Leakage
I,
Vee
or
6
-
-
±0.1
-
±1
-
±1
Gnd
Quiescent
I""
or
Voltage
Between
Vee & Gnd
Vee
Vee
0
6
-
-
B
-
BO
-
160
or
Gnd
Gnd
Additional
4.5
Quiescent Device
Vee -2.1
Current per input
pin: 1 unit load
2
to
-
-5.2
-
5.5
-
V,"
-
4.5
-
-
-
2
to
5.5
1.9
-4
Device Current
-
4.4
V"
or
Current
4.2
Min Typ Max Min Ma. Min Ma.
4.5
2
TTL Loads
Voe
1.5
4.5
V,"
Low-Level
V
V
3.15
-
6
CMOS Loads
Output Voltage
Vee
4.2
4.5 3.15
1.5
-
+25°C
V,
-
-
-
6
Output Voltage
Min Typ Ma. Min Ma. Min Ma.
1.5
2
Low-Level
Input Voltage
V""
V
to
5.5
AI""
-For dual-supply systems theoretical worst case (V,
=2.4 V, Vee =5.5 V) specification is 1.B rnA.
HCT INPUT LOADING TABLE
INPUT
UNIT LOADS·
Po. p" P2• Go. G,
P3 • G2. Cn
G3
1.25
1.5
0.3
• Unit Load is ~Icc limit specified in Static Characteristic
Chart. e.g .• 360 pA max. @ 25° C.
________________________________________________________________ 257
Technical Data ___________________________________________________________
CD54/74HC182
CD54/74HCT182
SWITCHING CHARACTERISTICS (Vee
=S V, T.. =2S·C, Input t" tf = 6 nl)
TYPICAL VALUES
UNITS
CL
(pF)
CHARACTERISTIC
HCT
HC
Propagation Delay Time:
Pn to P
tPHL. tPLH
15
9
11
17
Cn to any output
tpHL. tPLH
15
12
Pn to any output
tPHlr tpLH
15
12
13
G n to any output
tPHL. tPLH
15
11
13
Cpo
-
66
72
Power Dissipation Capacitance'
ns
pF
• Cpo is used to determine the dynamic power consumption. per package.
Po = Cpo Vee'f, + I (CL Vee·f.) where: f, = input frequency
f. = output frequency
CL =output load capacitance
Vee =supply voltage
SWITCHING CHARACTERISTICS (CL = SO pF, Input t f , tf = 6 ns)
LIMITS
TEST
CONDITIONS
CHARACTERISTIC
54HCT
-
30
35
26
-
-
-
-
190
-
-
40
-
38
-
50
45
-
60
-
-
33
-
-
-
38
-
-
-
180
-
-
-
220
-
33
-
-
36
-
41
-
36
-
50
-
-
31
-
-
-
31
-
-
-
28
-
-
-
-
26
-
145
-
24
6
-
20
tPLH
2
-
150
tpHL
4.5
30
120
150
36
-
42
31
-
-
225
-
-
180
-
tPLH
2
-
tpHL
4.5
-
29
6
-
25
-
tPLH
2
-
135
-
-
-
170
-
-
-
205
-
-
tPHL
4.5
-
27
-
32
-
34
40
-
41
-
48
6
-
23
-
-
29
-
-
35
-
-
-
95
-
-
-
19
-
110
19
-
22
-
22
16
-
-
-
19
-
-
10
-
10
-
10
-
10
6
C n to any output
Pn to any output
Transition
tTLH
2
-
75
-
-
Time
!THL
4.5
-
15
-
15
6
-
13
-
-
-
-
10
-
10
-
G n to any output
Input
Capacitance
S4HC
-
-
4.5
tpHL
74HCT
-
-
-
Pn to P
74HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
2
Propagation Delay. tPLH
-SS·C to +12S·C
UNITS
HCT
HC
Vee
V
-40·C to +8S·C
2S·C
Co
ns
pF
258 _________________________________________________________________
___________________________________________________________ TechnicaIData
CD54/74HC182
CD54/74HCT182
92CS-37974Rl
Input Level
SWitching Voltage. Vs
54/74HC
54174HCT
Vee
3V
50% Vee
1.3 V
Fig. 2 - Transition times and propagation delay times.
___________________________________________________________________ 259
Technical Data _ _ _ _ _ _--'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~_ _ __
CD54/74HC190, CD54/74HCT190
CD54n4HC191, CD54/74HCT191
File Number
1662
High-Speed CMOS Logic
BCD/BINARY
PRESET
ASYN. PARALLEL
LOAD ENABLE
11
CLOCK
14
UP/DOWN
5
COUNT
ENABLE
4
Presettable Synchronous 4-Bit
Up/Down Counters
3
2
HC/HCT190
HC/HCT191
6
12
13
01 BCD (190)
00]
02 BINARY(191)
OUTPUTS
03
TERMINAL
COUNT
RIPPLE CLOCK
92CS- 38520R2
FUNCTIONAL DIAGRAM
CD54174HC/HCT190 BCD Decade Counter
CD54174HC/HCT191 Binary Counter
Type Features:
• Synchronous counting and asynchronous loading
• Two outputs for n-bit cascading
• Look-ahead carry for high-speed counting
The RCA-CD54174HC/HCT190/191 are asynchronously
presettable BCD Decade and Binary Up/Down synchronous
counters, respectively.
Presetting the counter to the number on preset data inputs
(PO-P3) is accomplished by a Low asynchronous parallel
load inp~(PL). Counting occurs when_PL is high, Count
Enable (CE) is low, and the Up/Down (U/D) input is either
low for up-counting or high for down-counting. The counter
is incremented or decremented synchronously with the
low-to-high transition of the clock.
When an overflow or underflow of the counter occurs the
Terminal Count output (TCl. which is low during counting,
goes high and remains high for one clock cycle. This output
can be used for look-ahead carry in high-speed cascading
(see Fig. 6). The TC output also initiates the Ripple Clock.
(RC) output which, normally high, goes low and remains
low for the lOW-level portion of the clock pulse. These
counters can be cascaded using the Ripple Clock output as
shown in Fig. 7.
If a decade counter is preset to an illegal state or assumes'
an illegal state when power is applied, it will return to the
normal sequence in one or two counts as shown in state
diagrams.
The CD54HC/HCT190 and the CD54HC/HCT191 are supplied in 16-lead ceramic dual-in-line packages (F suffix).
The CD74HC/HCT190 and the CD74HC/HCT191 are supplied in a 16-lead dual-in-line plastic packages (E suffix)
and in 16-lead dual-in-line surface mount plastic packages
(M suffix). The CD54/74HC/HCT190 and the CD54174HC/
HCT191 are also supplied in chip form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85 0 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity: ML = 30%, MH = 30%
of Vee, @ Vee = 5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, ~ 1 J1A @ VOL, V OH
P1
Q1
QO
CE
UfO
Q2
Q3
GNO
2
3
4
5
6
7
8
16
VCC
15 PO
14
CP
13 RC
12
TC
11 ji[
10
P2
9_ P3
92eS-38521
HC/HCT190, HC/HCT191
TERMINAL ASSIGNMENT
260 _ _ _ _
~
_ _ _ _ _ _ ___'__ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
- - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC190, CD54/74HCT190
CD54/74HC191, CD54/74HCT191
"
CP ~',--s---,
U/D05~,_Ii----_ft_----,_--------------tr----~---------------11
~~~~ ,---~~--~---------------++-~--~---------------
,Jt=~~~-~
J__ :
CEo--{>--------4---------+---------------'"'-----------+--------
3
00
Fig. 1 - Logic diagram for HC/HCTI90 (continued on next page).
PO
15
P2
P1
1
10
r-~~~~~------------_;~--------------~------------B
,~--~------~~--------~------~r_------~--------t+--------~---c
r-~~------~--------r-~-D
,---t+--~-----+--------t+--~_f--~~----_++_~----_+~r_--E
,--+------~--+-~--+_r~--~~-+--+=+=~==~
H
Lt_f---r----------~rrt_~+_----------_+~~H-_rJ
K
~~_f--------------r_~_f------------+_~--_+------------rr~-+_f-L
'+--*-i------------+++--+t--t-
>-____~L___________~---l----------~--,--~--------~~==~:t~
Fig. 2 - Logic diagram for HC/HCT191 (continued on next page).
92Cl-38523R~
-------------------------____________________________________________ 261
TechnlcaIOala _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54n4HC190, CD54/74HCT190
CD54/74HC191, CD54n4HCT191
.
p,
P3
'0
"RC
:=========+~==============~t±~=========+_+~~
,
7
03
02
Fig. 1 - Logic diagram for HCIHCT190 (continued from previous page).
P3
9
B------r+-----------1:>--------------=~~
c------~----------------,
D------~------------~
~I~=====i~==~~·~====~:;
H
Q
CL
Q
FF3
J--------------1---~~
K---------------+---b~/
L--------------+-~----~~
:==========+=~[)
92CL-38523R3
Fig. 2 - Logic diagram for HCIHCT191. (continued from previous page).
262 __________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC190, CD54/74HCT190
CD54/7 4HC191, CD54/74HCT191
TRUTH TABLE
f-_---- Vee +0.5 V) ....................................................... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Va < -0.5 V OR Va > Vee +0.5 V) ................................................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Va < Vee +0.5 V) .................................................... ±25 mA
DC Vee OR GROUND CURRENT, (Icc) ..................................................................................... ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60°C (PACKAGE TYPE E) ............................................................................... 500 mW
For T. = +60 to +85° C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/ o C to 300 mW
ForT. =-55 to +100°C (PACKAGE TYPE F, H) ........................................................................... 500 mW
For T. = +100 to +125 0 C (PACKAGE TYPE F, H) ............................................. Derate Linearly at 8 mW/ o C to 300 mW
For T. = -40 to +70°C (PACKAGE TYPE M) ............................................................................ 400 mW
For T. = +70 to +125°C (PACKAGE TYPE M) ............................................... Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H ............................................................................................. -55 to +125°C
PACKAGE TYPE E, M ............................................................................................. -40 to +85° C
STORAGE TEMPERATURE (T".) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
+265°C
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................................................................................... +300°C
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
LIMITS
UNITS
MIN.
MAX.
2
4.5
6
5.5
V
0
Vee
V
Supply-Voltage Range (For TA=Full Package Temperature Range)
Vee:'
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage. V,. Vo
Operating Temperature, T A:
CD74 Types
CD54 Types
Input Rise and Fall Times, t"t,:
at 2 V
at 4.5 V
at 6 V
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
'Unless otherwise specified. all voltages are referenced to Ground.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 263
TechnicaIOala _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC190, CD54/74HCT190
CD54/74HC191, CD54/74HCT191
STATIC ELECTRICAL CHARACTERISTICS
CD74HC190/CD54HC190
CD74HC191/CD54HC191
CD74HCT190/CD54HCT190
CD74HCT191/CD54HCT191
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
UNITS
CHARACTERISTICS
+25°C
V,
10
Vee
V
rnA
V
High-Level
Input Voltage
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
Vo"
CMOS Loads
or
-0.02
V,"
~yp Mo. Min
r,.a.
Min
r,.a.
1.5
-
-
1.5
-
1.5
-
4.5 13.15
-
-
.15
-
13.15
-
4.2
-
4.2
-
-
0.5
-
2
V,"
Min
6
4.2
-
Low-Level
Output Voltage
CMOS Loads
-
0.5
-
1.35 -
1.35 -
1.35
6
-
1.8
-
1.8
-
1.8
-
1.9
-
4.4
-
or
5.9
-
V,"
3.7
-
or
5.2
-
V,"
V"
2
1.9
-
1.9
4.5
4.4
-
-
4.4
6
5.9
-
-
5.9
4.5 3.98
-
-
.84
-
-
5.34
-
0.5
Icc
2
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
ft01
-
±1
-
±1
iJA
5.5
-
-
8
-
80
-
160
iJA
-
450
-
490
iJA
to
5.5
V"
-5.2
6
5.48
2
-
-
0.1
-
0.1
-
0.1
0.02
4.5
-
-
0.1
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
-
0.4
or
0.4
V,"
Any
Voltage
Between
V~c and
Gnd
V"
or
4
4.5
-
-
0.26
-
0.33
V,"
5.2
6
-
-
0.26
-
0.33
Vee
or
Gnd
Vee
or
Gnd
-
V"
6
-
-
0.1
-
±1
-
±1
6
-
-
8
-
80
-
160
Quiescent Device
Current
-
4.5
-
V,"
or
2
to
5.5
-
-
Min Typ Mo. Min Mo. Min Mo.
4.5
-
-
Input Leakage
I,
V
2
V"
Current
V
-4
V,"
TTL Loads
Vee
or
V"
Voe
V,
4.5
V"
TTL Loads
+25°C
Vee
0
or
Gnd
Additional
Quiescent Device
4.5
Current per
Input Pin:
1 Unit Load
to
Vee -2.1
-
100 360
5.5
ll.lcc
*For dual-supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
PO-P3
CP
PL
TIID
CE
Unit Loads·
0.4
1.5
1.5
1.2
1.5
'Unit load is l;. Icc limit specified in Static Characteristics
Chart, e.g., 360 pA max. @ 25 0 C.
264 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC190, CD54/74HCT190
CD54/7 4HC191, CD54/74HCT191
PREREQUISITE FOR SWITCHING FUNCTION
CHARACTERISTIC
SYMBOL
HC
Vee
_55° C to +125° C
_40° C to +85° C
25°C
HCT
74HC
74HCT
54HC
54HCT.
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Setup Time
Pn to PL
CE to CP
tsu
UIO to CP
Hold Time
Pn to PL
-
CE to CP
tH
-
UfO to CP
Maximum Frequency"
Recovery Time
CP Pulse Width
Pi. Pulse Width
f MAx
tREe
tw
tw
-
-
75
12
-
15
6
10
2
60
4.5
12
6
10
2
90
-
4.5
18
-
18
6
15
2
2
-
4.5
2
6
2
2
2
4.5
2
6
2
2
60
4.5
12
12
-
2
0
-
4.5
0
-
0
6
0
-
-
2
6
4.5
30
6
35
2
60
4.5
12
6
10
2
80
4.5
16
6
14
-
2
-
-
-
-
23
-
2
-
2
-
2
15
-
-
13
75
15
13
115
23
20
2
-
2
-
2
25
--
29
75
-
-
13
-
100
16
-
20
-
-
17
-
2
-
30
12
2
100
4.5
20
-
20
6
17
-
-
0
0
0
5
125
25
21
135
-
27
-
27
23
-
-
2
-
-
-
90
15
-
18
-
-
15
-
2
2
0
25
15
-
-
-
-
15
90
18
15
-
2
-
-
2
-
-
2
-
-
2
-
2
2
18
-
-
2
-
-
0
-
4
90
-
18
-
18
15
-
30
-
20
23
-
120
24
-
-
-
-
150
25
-
30
26
-
-
18
0
0
-
20
-
20
0
20
-
-
24
-
ns
MHz
-
ns
"Applies to non-cascaded operation only. With cascaded counters clock-to-terminal count propagation delays, count enable
(CEl-ta-clock set-up times, and count enable (CEl-to-clock hold times determine max. clock frequency. For example, with
these HC devices:
--==-''--___= ____
fm .. (CP) = _ _ _ _ _ _ _
= __
1 _ = 18 MHz
CP-to-TC prop. delay + CE-to-CP setup + CE-to-CP Hold
42+12+2
__________________________________________ 265
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC190, CD54/74HCT190
CD54/74HC191 , CD54/74HCT191
SWITCHING CHARACTERISTICS (Vcc = 5 V, TA = 25°C, Inpul I" If = 6 ns)
TYPICAL VALUES
HC
SYMBOL
CHARACTERISTIC
UNITS
HCT
190
191
190
191
17
Propagation Delay (Cl = 15 pF)
pI to an
16
16
17
Pn to an
14
14
16
16
CP to an
14
14
14
14
10
10
11
11
18
18
18
18
tPlH
CPto RC
t pHL
CP to TC
UfO to RC
12
12
12
12
UfO to TC
13
13
16
16
CE to RC
10
10
11
11
59
55
78
68
Power Dissipation Capacitance
Cpo
.
'C po is used to determine the power consumption, per package.
PD=C po Vee' fi + I (Cl Vee' fo) where: f,=input frequency fo=output frequency Cl=output load capacitance
SWITCHING CHARACTERISTICS eCl
SYMBOL
pF
Vee=supply voltage
=50 pF, Inpul I" If =6 ns)
_40° C to +85° C
25°C
CHARACTERISTIC
ns
Vee
HC
HCT
74HC
-55°C 10 +125°C
74HCT
54HCT
54HC
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay
pL to
an
Pn to an
tPLH
2
-
195
tPHl
4.5
-
39
6
-
34
35
4.5
-
25
6
21
-
210
-
-
2
tPHL
4.5
6
CPto RC
170
tPHl
tPLH
35
29
125
-
-
44
-
37
-
215
-
-
43
-
44
37
-
31
-
34
-
38
26
-
-
-
32
265
-
-
-
315
53
-
53
45
-
-
54
-
225
38
-
45
-
45
38
205
-
-
250
-
-
50
-
57
43
-
190
-
38
-
41
-
-
2
4.5
42
220
-
38
tPLH
tPHl
33
175
-
-
-
2
-
-
-
40
-
tPLH
6
CPto an
30
-
-
27
tPlH
2
-
CE to RC
tpHL
4.5
-
6
-
21
-
Output Transition
hLH
2
-
75
-
-
Time
hHL
4.5
-
15
13
-
15
6
-
-
-
-
10
-
10
-
CPto TC
tPlH
2
tPHL
4.5
6
UIO to RC
tPLH
2
tPHl
4.5
6
-
UIO to TC
tPLH
2
tPHL
4.5
6
an, TC, RC
Input Capacitance
C,
245
49
155
50
48
295
59
50
265
53
45
255
51
43
190
42
-
42
36
-
150
30
-
-
26
-
165
-
33
38
-
41
-
48
-
-
35
-
-
155
-
-
27
-
31
-
34
-
26
-
32
-
110
19
-
22
16
-
-
-
95
-
-
19
-
10
-
10
-
10
-
28
125
25
30
-
-
190
38
33
19
-
-
63
-
I 60
-
57
53
41
63
ns
-
-
22
-
10
pF
266---------------------------------------------------------------
___________________________________________________________ TechnicaIData
CD54/74HC190, CD54/74HCT190
CD54/74HC191, CD54/74HCT191
TIMING DIAGRAMS
LOAD~
PARALLEL LOAD
PO
P1
PRESET
INPUT
DATA
P1
PRESET
INPUTS
P2
P2
CLOCK
CLOCK
DOWN/UP
DOWN/UP
ENABLE
CLOCKENABLE~~+_--------~
TERMINAL COUNT·-:
,
,
RIPPLE CLOCK - -
RIPPLE CLOCK - -
---'
17
8
!.j'-
9
0 12
2
2 1
0
9
a 7
COUNT UP -liNHiBiT' I-COUNT DOWN
-l
LOAD
Sequence:
(1) Load (preset) to BCD seven
I (3) Inhibit
(2) Count up to eight, nine, zero, one and INO ! (4) Counl down to one, zero, nine, eight, and seven
-
13 14 15 0
1 2
2
2 I 1
0
15 14 13
_'_"- -COUNT uP-1iNHiBiT' !--COUNT DOWN-I
-J
LOAD
Sequence:
(1) Load (preset) to binary thirteen
(3) Inhibit
(4) Count down to one, zero, fifteen,
(2) Count up 10 fourteen, 'I'teen, zero, one. and two
fourteen, and thirteen
92CM-38402
Fig. 4 - HC/HCT190 decade counters typical load, count, and
inhibit sequences.
O~A~;;~~~
Fig. 5 - HC/HCT191 binary counters typical load, count, and
inhibit sequences.
____..,.-_______-,_______,.___
92CS-38401
92C5-38400
Fig. 6 - Sychronous n-stage counter with parallel gated Terminal
Count.
Fig. 7 - Synchronous n-stage counter using ripple clock.
COUNT DOWN
COUNT UP
NOTE:
NOTE:
ILLEGAL STATES IN BCD COUNTERS
CORRECTED IN ONE COUNT.
ILLEGAL STATES IN BCD COUNTERS
CORRECTED IN ONE OR TWO COUNTS.
Fig. 8 - HCIHCT190 State Diagrams.
_________________________________________________________________ 267
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC190, CD54/74HCT190
CD54/74HC191, CD54/74HCT191
_ . , ,_ _ INPUT LEVEL
CPorCE
Wave.orm1
Waveform 2
•
~INPUTLEVEL
pn--,
~
On _ _- J
Waveform 3
Pi~ Vs
-rv;---
Waveform 4
INPUT LEVEL
~trec..J
I-tw
-!-t,eC1_tNPUT LEVEL
CP---.J
On
IJ1I
Waveform 5
Waveform 6
INPUT LEVEL
U/O
CP
I" -_ _..J I
Vs
TC
Waveform 7
Waveform 8
The shaded areas indicate when the Inpulls permitted to change lor predictable output performance
9ZC L -38403R3
54/74HC
Input Level
Switching Voltage, Vs
VCC
50%VCC
54/74HCT
3V
1.3 V
Fig. g - Transition, propagation delay, setup and hold, and recovery times.
268 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
File Number
CD54/74HC192, CD54/74HCT192
CD54/74HC193, CD54/74HCT193
1674
High-Speed CMOS Logic
BCD/BINARY PRESET
;Po
P:~:~L~L
[()"A[j
ENABLE
PC
i
P1 p2 P3'
11r-'-'-"-J..!.-.l.!:"-"'-,
~~}BCD(192)
02
MASTER
RESET
14
C3
12~
CLOCK UP
CLOCK DOWN
BINARY(193)
OUTPUTS
COUNT UP
13~
COUNTDOWN
92CS- 3S!564RI
FUNCTIONAL DIAGRAM
Presettable Synchronous 4-Bit
U p/Down Counters
CD54174HC/HCT192 BCD Decade Counter,
Asynchronous Reset
CD54174HC/HCT193 4-Bit Binary Counter,
Asynchronous Reset
Type Features:
• Synchronous counting and asynchronous loading
• Two outputs for n-bit cascading
• Look-ahead carry for high-speed counting
The RCA-CD54174HC/HCT192/193 are asynchronously
presettable BCD Decade and Binary Up/Down synchronous
counters, respectively.
Presetting the counter to the number on preset data inputs
(PO-P3) is accomplished by a LOW asynchronous parallel
load input (PL). The counter is incremented on the low-tohigh transition of the Clock-Up input (and a high level on
the Clock-Down input) and decremented on the low-tohigh transition of the Clock-Down input (and a high level on
the Clock-Up input). A high level on the MR input overrides
any other input to clear the counter to its zero state. The
Terminal Count Up (carry) goes low half a clock period
before the zero count is reached and returns to a high level
at the zero count. The Terminal Count Down (borrow) in the
count down mode likewise goes low half a clock period
before the maxi mum count (9 in the 192 and 15 in the 193)
and returns to high at the maximum count. Cascading is
effected by connecting the carry and borrow outputs of a
less significant counter to the Clock-Up and Clock-Down
inputs, respectively, of the next most significant counter.
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85 0 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity: N,L = 30%, N,H = 30%
of Vee, @ Vee = 5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, :::; 1 iJA @ VOL, VOH
If a decade counter is preset to an illegal state or assumes
an illegal state when power is applied, it will return to the
normal sequence in one count as shown in state diagram.
The CD54HC/HCT192 and the CD54HC/HCT193 are supplied in 16-lead ceramic dual-in-line packages (F suffix).
The CD74HC/HCT192 and CD74HC/HCT193 are supplied
in 16-lead plastic dual-in-line packages (E suffix) and in
16-lead dual-in-line surface mount plastic packages (M
suffix). The CD54/74HC/HCT192 and the CD54/74HCI
HCT193 are also supplied in chip form (H suffix).
P1
C1
CO
CPO
CPU
C2
C3
GND
16
15
14
13
12
11
10
8
9
vcc
PO
MR
TCD
TCU
Pi:
P2
P3
9ZCS-38565
TERMINAL ASSIGNMENT
___________________________________________________________ 269
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC192, CD54/74HCT192
CD54/74HC193, CD54/74HCT193
PO
P3
P2
PI
MRo-~»-~-r---r----~==~==1=====~==t===+=====~==t===~--~
Pi: R
a
FF 3
B
OGND
OVcc
16
01
00
03
02
92.CL - :HI!E>f>RI
Fig. 1 - Logic diagram for HC/HCTI92.
Co
01
Q2
OJ
(a) CelliUp
(b) Cell2UP
92CS-38570
Q2
OJ
(c) Cell3UP
00
(d) Cell1Dn
Q2
03
00
01
(e) Cell2Dn
02
92CM-38t569
270 _________________
________(f) Cell3Dr
_____________
Fig.__________________
2 - CARRY logic cells for CD54/74HC/HCT192
~
~
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC192, CD54/74HCT192
CD54/74HC193, CD54/74HCT193
P1
1
Pi:
P
~
a
FF
1
Ct:
a
B
o--GND
16
o--Vcc
Fig. 3 - Logic diagram for HC/HCTI93.
R
----I
FFO-FF3
r-I
P
--'-+--......-1
P---.-1-.,--0
! ~cr
cr--t--l--[>--CL
......-+--0
J
92CM -38S68
Fig. 4 - Logic diagram of flip-flops for HC/HCT1921193.
TRUTH TABLE
Clack
Up
f
Clock
Down
H
H
..F
X
X
X
X
Reset
L
L
H
L
Parallel
Load
H
H
X
L
Function
Count Up
CountDown
Reset
Load Preset
Inputs
J = low-to-high transition
x = don't care
_____________________________________________ 271
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC192, CD54/74HCT192
CD54/74HC193, CD54/74HCT193
MAXIMUM-RATINGS, Absolute-Maximum Values:
DC SUPPL Y-VOL TAGE, (Vee):
(Voltages referenced to ground) ...................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ....................................................... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) ................................................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) .................................................... ±25 mA
DC Vee OR GROUND CURRENT, (Icc) ..................................................................................... ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For T A = -40 to +60° C (PACKAGE TYPE E) ............................................................................... 500 mW
For TA = +60 to +85° C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/oC to 300 mW
For T. = -55 to +1 OQ°C (PACKAGE TYPE F, H) ........................................................................... 500 mW
For T. = +100 to +125°C (PACKAGE TYPE F. H) ......... _.................................. Derate Linearly at 8 mW/oC to 300 rnW
For TA = -40 to +70°C (PACKAGE TYPE M) .............................................................................. 400 mW
For T. = +70 to +125°C (PACKAGE TYPE M) ................................................. Derate Linearly at 6 mW/oC to 70 mW
OPERATI NG-TEMPERATURE RANGE (1.):
PACKAGE TYPE F, H ............................................................................................. -55 to +125' C
PACKAGE TYPE E, M .............................................................................................. -40 to +85°C
STORAGE TEMPERATURE (T ...) .................................................................................... -65 to +150'C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
.. ................................................... +265'C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................................................................................... +300' C
RECOMMENDED OPERATING CONDITIONS
For maximum reliability,· nominal operating condilions should be selected so thatoperallon Is always within
Ihe following ranges:
CHARACTERISTIC
LIMITS
·MIN,
MAX.
UNITS
Supply-Voltage Range (For TA-Full Package Temperature Range)
Vee:·
CD54/74HC Types
CD54174HCT Types
DC Input or Output Voltage, V" Vo
2
6
4.5
5.5
0
Vec
V
V
Operating Temperature, T A :
CD74 Types
-40
+85
CD54 Types
-55
+125
at2V
0
1000
at 4.5 V
0
500
at6V
0
400
'C
Input Rise and Fall Times, t"t,:
ns
·Unless otherwise specified, all voltages are referenced to Ground.
272 _________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC192, CD54/74HCT192
CD54/74HC193, CD54/74HCT193
STATIC ELECTRICAL CHARACTERISTICS
CD7 4H C192/193C D54HC192/193
CD7 4HCT1921193/C D54HCT192/193
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
CHARACTERISTICS
UNITS
+25°C
V,
10
Vee
V
mA
V
High-Level
Input Voltage
low-level
Input Voltage
1.5
-
-
1.5
-
1.5
-
-
3.15
-
3.15
-
-
4.2
-
High-Level
Output Voltage
V"
V o"
CMOS Loads
or
-0.02
V,"
-
-
4.2
2
-
-
0.5
-
0.5
-
0.5
1.35 -
1.35
-
1.35
-
1.8
-
1.8
-
1.8
Low-Level
Output Voltage
CMOS Loads
-
2
-
2
-
V
-
-
O.B
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
0.1
-
±1
-
±1
IlA
5.5
-
-
8
-
80
-
160
IlA
-
450
-
490
IlA
to
5.5
1.9
-
-
1.9
-
1.9
-
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5 3.98
-
-
3.84
-
3.7
-
or
5.48
-
-
5.34
-
5.2
-
V,"
V"
V"
V"
-5.2
6
2
-
-
0.1
-
0.1
-
0.1
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
V"
or
4
4.5
-
-
0.26
-
0.33
-
0.4
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
±1
Voltage
Between
Input Leakage
Quiescent Device
Current
-
4.5
-
2
V"
Current
2
to
V,"
or
Min Typ Max Min Max Min Max
5.5
-4
V,"
TTL Loads
V
or
V"
Vo,
V
4.5
V"
TTL Loads
Vee
4.5
4.2
6
V,
-
6
4.5
V"
Min Typ Max Min Max Min Max
4.5 3.15
2
V,"
+25°C
Any
I,
Icc
Vee
or
Gnd
Vee
or
Gnd
6
-
-
-
0.1
±1
-
Vee and
Gnd
Vee
0
6
-
-
-
8
80
-
160
or
Gnd
Additional
Quiescent Device
4.5
Current per
Vee -2.1
Input Pin:
1 Unit Load
to
-
100 360
5.5
Alec
*For dual-supply systems theoretical worst case (VI = 2.4 V. Vee
=5.5 V) specification
is 1.8 rnA.
HCT Input Loading Table
Input
Unit Loads'
PO-P3
0.4
1.45
0.85
1.45
MR
PL
CPU, CPO
·Unit load is ll. Icc limit specified in Static Characteristics
Chart, e.g., 360 JiA max. @ 25 C.
____________________________________________________________________
273
0
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC192, CD54/74HCT192
CD54/74HC193, CD54/74HCT193
SWITCHING CHARACTERISTICS (Vcc=5 V, T A=25° C, Input t"t,=6 ns)
SYMBOL
CHARACTERISTIC
Propagation Oelay (CL = 15 pF)
CPU to TCU and CPO to TCO
CPU; CPO to an
PL to an
MR to an
Power Oissipation Capacitance
tPLH
tpHL
.
tPHL
Cpo
TYPICAL
VALUES
HC
HCT
10
18
18
17
40
11
17
21
18
50
UNITS
ns
pF
'Cpo is used to determine the dynamic power consumption, per package.
PD=Cpo Vee' fi + I (CL Vee' fo) where:
f;=input frequency
fo=output frequency
CL =output load capacitance
Vee=supply voltage
Pre-requisite for Switching Function
CHARACTERISTIC
Pulse Width:
CPU,CPO
SYMBOL
tw
192
CPU, CPO
193
PL
tw
MR
tw
Setup Time
Pn to PL
tsu
Hold Time
Pn to PL
tH
Hold Time
CPO to CPU
or CPU to CPO
Recovery Time
PL to CPU, CPO
MR to CPU, CPO
Maximum Frequency
CPU, CPO
192
CPU, CPO
193
tH
tREG
tREC
f MAX
VCC
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
25°C
HC
HCT
Min. Max. Min. Max.
115 23
23
-'
20
100 20
23
17
80
16
16
14
100 20
20
17
80
16
15
14
0
0
0
0
80
16
16
14
80
16
15
14
5
5
5
5
5
22
22
24
5
25
22
29
_40° C to +85° C
74HC
74HCT
Min. Max. Min. Max.
145 29
29
25
125 29
25
21
100 20
20
17
-
-
125
25
21
100
20
17
0
0
0
100
20
-
-
-
-
25
-
-
-
-
-
19
-
-
-
-
-
-
0
-
-
-
-
-
-
20
-
-
17
-
-
-
100
20
17
5
5
5
4
18
21
4
20
24
-
-
-
-
19
-
-
-
-
-
-
-
5
-
-
-
-
-
-
-
18
-
-
-
-
-
-
-
-
18
-
-
-
-
_55° C to +125° C
54HC
54HCT
UNITS
Min. Max. Min. Max.
175 35
35
30
150 30
35
26
120 24
24
20
150 30
30
26
120 24
22
ns
20
0
0
0
0
120 24
24
20
120 24
22
20
5
5
5
5
3
15
15
MHz
18
3
17
15
20
-
274 _____________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC192, CD54/74HCT192
CD54/74HC193, CD54/74HCT193
SWITCHING CHARACTERISTICS (CL =50 pF, Input t"t,=6 ns)
CHARACTERISTIC
Propagation Delay
CPU toTCU
SYMBOL
tPLH
tPHL
CPD toTCD
CPU to an
CPD to an
PL to an
MR to an
Transition Time:
a, TCU, TCD
Input Capacitance
hHL
hLH
C,
VCC
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-40° C to +85° C
-55°C to +125°C
25°C
54HCT UNITS
74HCT
54HC
HCT
74HC
HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
190 155
125
34
38
41
31
25
27
32
21
26
155
190 125
31
38
25
27
34
41
26
32
21
- 325
270
220 50
65
43
40
54
60
46
55
37
- 325 270
220 40
54
65
60
43
50
55
37
46
330
220
275 ns
55
59
66
71
44
47
37
47
56
300 200
250 65
43
54
60
40
50
43
51
34
110 75
95
19
22
22
15
15
19
16
19
13
10
10
10
pF
10
10
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 275
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC192, CD54/74HCT192
CD54/74HC193, CD54/74HCT193
MASTERRESET--Il~-------------------------------------
ASVNC PARALLEL LOAO
PRESET DATA [::
P2
P3_H_~
CLOCKUP--+-t--t-r-,
CLOCKDOWN--+-t--t-r~--------------+--,
Sequences!
(1) Reset outputs to zero.
(2) Load (preset) to BCD seven.
(3) Count up to eight, nine, terminal
count up, zero, one and two.
(4) Count down to one, zero, terminal
count down, nine. eight and seven.
OUTPUTS{::~~:
02 __
I
03::: _ ~_+-!__+-'
TERMINAL COUNT UP
TERMINALCOUNTDOWN---r+--+-r--~-------------r-+-----,
11
0
9
8
71
I--COUNT DOWN---i
92CS-38573
(a) HC192 synchronous decade counters. Typical reset, preset and count sequences.
MASTERRESET--IlL--------------------------------------ASVNC PARALLEL LOAD
r++-+-i.=.= =--:.-:..:-_-~:::~_-_-_-_-_-:._=__=___-=
~
~-----------------{
RESET DATA :~--;::j:!=:j:~= ===::::::.===:::::::::_-_-_____-=--=
Sequences;
(1) Reset outputs to zero.
(2) Load (preset) to binary thirteen.
(3) Count up 10 fourteen, fifteen,
terminal count up, zero, one and
two.
P3
CLOCKUP--+-~_r_r_,
(4) Count down to one, zero, terminal
count down, fifteen. fourteen and thirteen.
CLOCKDOWN--+_t-~_r~--------------+__,
Note 1: Master reset overrides load
data and clock Inputs
Note 2: When counting up, clock-down input
must be high; when counting down,
clock-up Input must be high.
TERMINALCOUNTUP--~+__+_r--~--_,
TERMINALCOUNTDOWN--~+__+~--r_------------~~----_,
11
11
o
13
114 15 0
1
21
R~~T~COUNTUP~
1 1 0 15 14 131
I--COUNTDOWN~
92.CS- 38574
(b) HC193 synchronous binary counters. Typical reset, preset and count sequences.
Fig. 6 - Timing diagrams for the CD54/74HC/HC Tt92(a) and 193(b).
276 _________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC192, CD54/74HCT192
CD54/74HC193, CD54/74HCT193
92CM-38572
(b) Clock to terminal count delays.
(a) Clock to output delays and clock pulse width.
MR
INPUT LEVEL
INPUT LEVEL
CPU OR
CPD
_
_-:-,..._ _ _---J
INPUT
LEVEL
CPU OR CPD
---IlpLH~r--
an----..F Vs
_
I
--1IPHL{::\".V_S_ _ _ _
Qn
~
(d) Master reset pulse width, master reset to output
delay and master reset to clock recovery time.
(c) Parallel load pulse width, parallel load to output
delays, and parallel load to clock recovery time.
an
-
INPUT LEVEL
/","1:'=-_ -
INPUT LEVEL
a=p __
~~_ _ _~~a=p
.,w4-
_
92CM-38!571RI
(e) Setup and hold times data to parallel load (PL).
54174HCT
3V
1.3 V
54/74HC
Input Level
Switching Voltage, Vs
VCC
50%VCC
Fig. 5 - AC waveforms.
APPLICATION
DATA INPUT
~=:::;=:~==:-PO
UP CLOCK - - - - CPU
DOWN CLOCK - - - -
Pl
P2
P3
'-----,
PO
Pl
P2
P3
TCUp-----i CPU
TCU
CARRY
,P-----' CPD
TCD
BORROW
MR
ASYNC,PARALLELLOAD-------t--+-+--+---4-~
RESET------t--+-+--+---~---~~~~-~--~
'~---------v,--------/
OUTPUT
92CM-38575
CASCADED UP/DOWN COUNTER WITH PARALLEL LOAD
_________________________________________________________________ 277
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC192, CD54/74HCT192
CD54/74HC193, CD54/74HCT193
COUNT DOWN
COUNT UP
NOTE:
NOTE: ILLEGAL STATES IN BCD COUNTERS
CORRECTED IN ONE COUNT.
ILLEGAL STATES IN BCD COUNTERS
CORRECTED IN ONE OR TWO COUNTS.
92CM-40338
Fig. 6 - HCIHCT192 State Diagrams.
2n _________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
File Number
CD54/74HC194
CD54/74HCT194
1668
High-Speed CMOS Logic
15
00
14
01
02
13
02
03
12
Q3
DO
4
01
OSL
OSR
SO
4-Bit Bidirectional
Universal Shift Register
Type Features:
vcc =
GNO=
16
8
S1
MR
cp
•
•
•
•
Four Operating Modes: Shift Right, Shift Left, Hold and Reset
Synchronous parallel or serial operation
Typical ' MAX = 60 MHz @ Vee = 5 V, C L = 15 pF, TA = 25° C
Asynchronous Master Rese,t
92CS-38549
FUNCTIONAL DIAGRAM
The RCA-CD54/74HC194 and CD54/74HCT194 are 4-bit
shift registers with Asynchronous Master Reset (MR). In
the parallel mode (SO and S1 are high), data is loaded into
the associated flip-flop and appears at the output after the
positive transition of the clock input (CP). During parallel
loading serial data flow is inhibited. Shift left and shift right
are accomplished synchronously on the positive clock edge
with serial data entered at the shift left (DSL) serial input
for the shift right mode, and at the shift right (DSR) serial
input for the shift left mode. Clearing the regis~s accomplished by a Low applied to the Master Reset (MR) pin.
The CD54HC/HCT194 devices are supplied in 16-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC/HCT194 devices are supplied in 16-lead dual-inline plastic packages (E suffix) and in 16-lead dual-in-line
surface mount plastic packages (M suffix). Both types are
also available in chip form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 30%, MH = 30% 01 Vee: @ Vee = 5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
VIL = 0.8 V Max., V'H = 2 V Min.
CMOS Input Compatibility
I, :S 1 J1A @ VOL, V OH
16
DSR
DO
D1
D2
D3
DSL
GND
15
14
13
Vcc
QO
Q1
Q2
12 03
11
10
cp
S1
SO
92CS·36826
TERMINAL ASSIGNMENT
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 279
Technical Data
CD54n4HC194
CD54n4HCT194
Dl
4
~69~~~__~~~--------~-+~----------~lr----------~iI
B
GNDo--
Vcc~
92CM-38550RI
Fig.. 1 - Logic diagram for the CD54/74HC194 and CD54/74HCT194.
D
R--------~
______________
~
92CS-3855IRI
Fig. 2 - Detail of single Flip-Flop for the CD54174HCI94 and CD54174HCT194.
TRUTH TABLE
Oper!ltlng
Mode
Reset (clear)
Hold (do nothing)
Shift Left
Shift Right
Parallel Load
Inputs
Outputs
CP MR S1 So OSR OSL On QD
X
X
--;
J
J
...r
L
H
H
H
H
H
H
X
X
X
I(b) I(b) X
h I(b) X
h I(b) X
I(b) h
I
I(b) h
h
h
h X
X
X
I
h
X
X
X
X
X
X
X
X
X
dn
L
qO
q1
q1
L
H
dO
Q1
L
q1
q2
q2
qO
qO
d1
Q2 Q3
L
L
q2
qS
q3
L
q3
H
q1
q2
q1
q2
d2
dS
H = HIGH voltage level.
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition.
L = LOW voltage level.
I = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition.
d n (qn) = Lower case letters indicate the state of the referenced input (or output)
one setup time prior to the LOW-to-HIGH clock transition.
X = Don't care .
LOW-toCHIGH clock transition.
...r=
NOTE: b. The HIGH-to-LOW transition of the SO, and Sl inputs on the 54174194
should only take place while CP is HIGH for conventional operation.
280 ________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
,CD54/74HC194
CD54/74HCT194
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
.. -0.5 to + 7 V
(Voltages referenced to ground) ........................ .
DC INPUT DIODE CURRENT. 11K (FOR V, < -0.5 V OR V, > Vee +0.5V) ....
~ 20 mA
~ 20 mA
DC OUTPUT DIODE CURRENT. 10K (FOR Vo < '0.5 OR Vo > Vee +0.5 V) .
~ 25 mA
DC DRAIN CURRENT, PER OUTPUT (I,) (FOR ,0.5 V < Vo < Vee +0.5 V)
~ 50 mA
DC Vee OR GROUND CURRENT (Icc)
POWER DISSIPATION PER PACKAGE (Po):
...........
500 mW
For TA ,40 to +60°C (PACKAGE TYPE E)
For TA 0 +60 to +85°C (PACKAGE TYPE E)
Derate Linearly at 8 mW/oC to 300 mW
500 mW
For TA ,55 to +100°C (PACKAGE TYPE F, H) ..
Derate Linearty at 8 mW/o C to 300 mW
For TA +100 to +125° C (PACKAGE TYPE F, H)
For TA = -40 to +70°C (PACKAGE TYPE M) ............................................................................. 400 mW
For TA = +70 to +125°C (PACKAGE TYPE M) ............................................... Derate Linearly at 6 mW;oC to 70 mW
OPERATING -TEMPERATURE RANGE (TA)
PACKAGE TYPE F. H
,40 to + 85° C
PACKAGETYPEE,M ...
STORAGE TEMPERATURE (T"o)
LEAD TEMPERATUARE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in .. 1.59 mm)
with solder contacting lead tips only
0
0
0
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected-so·that operation is always within the following
ranges:
LIMITS
CHARACTERISTIC
MIN.
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vee:'
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V, Vo
Operating Temperature TA:
CD74 Types
CD54 Types
MAX.
UNITS
2
4.5
6
5.5
V
0
Vee
V
-40
-55
+85
+125
°C
0
0
0
1000
500
400
InputRiseand Fall Times t, t.
at 2V
at 4.5 V
at 6V
ns
'Unless otherwise specified, all voltages are referenced to Ground.
______________________________________________________ 281
Technical.Data
CD54/74HC194
CD54/74HCT194
STATIC- ELECTRICAL CHARACTERISTICS
~
CD74HC/54HC194
TEST
CD74HCT/54HCT194
54HC
TEST
74HCT/54HCT
74HCT
54HCT
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+ 85°C
+ 125°C
+ 85°C
+ 125°C
74HC
74HC/54HC
CONDITIONS
TYPES
UNITS
CHARACTERISTIC
V,
10
Vee
V
rnA
V
+25°C
V,
Vee
V
V
Input Voltage
2
V,H
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VIL
VOH
or
-0.02
V,H
CMOS Loads
1 ~5
4.5 3.15
-
-
1.5
-
-
3~ 15
-
1.5
-
3.15
-
4.5
to
6
4.2
-
-
4.2
-
4.2
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
to
6
1.8
-
1.8
-
1.8
5.5
2
1.9
-
1.9
-
4.4
-
1.9
4.5
-
1.35
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,H
4.5
3.98
-
-
3.84
-
3.7
-
or
-
-
5.34
-
5.2
-
V,H
VIL
-
Low-Level
Output Voltage
Input Leakage
Current
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
Any
Voltage
Between
5.5
Vee
-
-
!O.1
-
!1
-
11
VIL
6
5.48
2
-
-
0.1
-
0.1
-
0.1
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,H
4.5
-
-
0.26
-
0.33
-
0.4
or
6
-
-
0.26
-
0.33
-
0.4
V,H
V,L
4
5.2
Vee
II
or
6
-
-
:0.1
-
-
11
11
&
Gnd
Gnd
Quiescent
Vee
Device
Current
or
Icc
V
0.8
-5.2
V,H
-
-
V,H
or
2
0.8
VIL
TTL Loads
-
VIL
V,H
CMOS Loads
2
-
-4
or
-
-
or
VIL
VOL
-
2
5.5
4.5
V,L
TTL Loads
25°C
Min Typ Ma. Min Ma. Min Max
Min Typ Max Min Ma. Min Ma.
High-Level
+
JJA
Vee
0
6
- -
8
-
-
80
Gnd
160
or
5.5
-
-
-
100 360
8
-
80
-
160
JJA
-
450
-
490
JJA
Gnd
4.5
Additional quiescent
Device Current bloc
per input pin:
1 unit load
Vcc-2.1
to
5.5
..
For dual-supply systems theoretical worst case (V, = 2.4 V, Vee = 5.5 V) specification IS 1.8 rnA:
HCT Input Loading Table
Input
.
Unit Loads·
CP
0.6
MR
0.55
DSL.DSR.On
0.25
Sn
1.10
'Unit Load is Alcc limit specified in Static Characteristic
Chart. e.g .• 360 pA max. @25°C.
282 _________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC194
CD54/74HCT194
SWITCHING CHARACTERISTICS (Vee = 5 V, T A = 25° C, Inpul I" I, = 6 ns)
CHARACTERISTIC
Propagation Delay,
tPLH
Clock to Q
TYPICAL
CL
pF
HC
HCT
15
14
15
ns
UNIT
tPHL
Maximum Clock Frequency
fMAX
15
60
50
MHz
Power Dissipation Capacitance'
Cpo
-
55
60
pF
'CPO is used to determine the dynamic power consumption, per package.
Po = Cpo Vee2 fi + I (CL Vee2 fo) where:
fi = input frequency.
fo = output frequency.
CL = output load capacitance.
Vee = supply voltage.
PREREQUISITE FOR SWITCHING FUNCTION
LIMITS
TEST
Vee
CHARACTERISTIC
Max. Clock Frequency
Fig.3
MR Pulse Width
Fig.4
Clock Pulse Width
Fig.3
Set-up time
Data to Clock
Fig.5
Removal Time
MR to Clock
Fig.4
Set-up Time
S1, SO to Clock
Fig.6
Set-up Time
DSL, DSR to Clock
Fig.6
Hold Time
S1, SO to Clock
Fig.6
Hold Time
Data to Clock
Fig.5
V
fMAX
tw
tw
tsu
tREM
tsu
tsu
tH
tH
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-40°C 10 + 85°C
25°C
CONDITION
HC
HCT
74HC
-55° C 10 + 125° C
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
6
30
35
80
16
14
80
16
14
70
14
12
60
12
10
80
16
14
70
14
12
0
0
0
0
0
0
-
27
-
18
18
-
14
14
-
20
-
14
-
0
0
-
5
24
28
100
20
17
100
20
17
90
18
15
75
15
13
100
20
17
90
18
15
0
0
0
0
0
0
22
-
23
-
23
18
-
18
-
25
18
-
0
-
0
-
4
20
23
120
24
20
120
24
20
105
21
19
90
18
15
120
24
20
105
21
18
0
0
0
0
0
0
18
MHz
27
ns
-
27
ns
-
21
ns
21
ns
-
30
ns
21
ns
0
ns
-
0
ns
-
_____________________________________________________________ 283
Technical Data
CD54/74HC194
CD54/74HCT194
SWITCHING CHARACTERISTICS (Cl = 50 pF, Inpul I" I, = 6 ns)
LIMITS
TEST
CONDITION
Vee
V
CHARACTERISTIC
Propagation Delay
Clock to Output
Output Transition
Time
-
265
37
44
46
53
56
-
37
45
-
95
-
110
-
19
19
22
22
-
16
.-
19
-
-
175
210
-
35
6
30
trLH
2
75
-
hHL
4.5
15
15
6
13
2
140
MR to Output
Fig.4
54HCT
220
-
4.5
tPHL
54HC
UNITS
tPHl
-
-55°C 1o + 125°C
74HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
2
Fig.3
Propagation Delay
HCT
tPLH
Fig.3
-40°C 1o + 85°C
74HC
25°C
HC
175
-
-
4.5
28
40
35
50
42
60
6
24
-
30
-
36
-
-
10
10
10
10
10
10
ns
ns
ns
Input Capacitance
C,
MR
LEVEL
INPUT
GND
pF
GND
INPUT LEVEL
CP
Q
I
92CS-37127
92C5-38486
54/74HCT
I
3V
INPUT LEVEL
SWITCHING VOLTAGE, Vs
1.3 V
Fig. 3 - Clock pre-requisite times and propagation and output
54J74HCT I
3V
INPUT LEVEL
SWITCHING VOLTAGE, Vs
1.3V
I
Fig. 4 - Master reset pre-requisite times and propagation delays.
transition times.
INPUT LEVEL
DATA
S OR OS
INPUT
LEVEL
GNO
INPUT LEVEL
CP
GNO
LEVEL
CP
GNO
92CS - 37128RI
INPUT LEVEL
INPUT LEVEL
SWITCHING VOLTAGE, Vs
SWITCHING VOLTAGE, Vs
Fig. 5 - Data pre-requisite times.
Fig. 6 Parallel load or shilt-/eft/shilt-right pre-requisite times.
284 ___________________________________________________________________
Technical Data
File Number
CD54/74HC195
CD54/74HCT195
1482
High-Speed CMOS Logic
fiE
4-Bit Parallel Access Register
00 01 0203
J 2
CP10
K
1103
3
MA1
FUNCTIONAL DIAGRAM
Type Features:
•
•
•
•
•
•
•
Asynchronous Master Reset
J, K, (D) inputs to first stage
Fully synchronous serial or parallel data transfer
Shift right and parallel load capability
Complementary output from last stage
Buffered inputs
Typical f MAx =50 MHz @ Vee=5 V, C L =15 pF, TA=25°C
The functional characteristics of the RCA-C054174HC195
and C054/74HCT195 4-Bit Parallel Access Register are
indicated in the Logic Diagram and Function Table. The
device is useful in a wide variety of shifting, counting and
storage applications. It performs serial, parallel, serial-toparallel, or parallel-to-serial data transfers at very high
speeds.
The two modes of operation, shift right (00-01) and
parallel load, are controlled by the state of the Parallel
Enable (PE) input. Serial data enters the first flip-flop (00)
via the J and K inputs when the PE input is high, and is
shifted one bit in the direction 00-01-02-03 following
each LOW-to-HIGH clock transition. The J and K inputs
provide the flexibility of the JK-type input for special
applications and, by tying the two pins together, the simple O-type input for general applications. The device
appears as four common-clocked 0 flip-flops when the
PE input is LOW. After the LOW-to-HIGH clock transition,
data on the parallel inputs (00-03) is transferred to the
respective 00-03 outputs. Shift left operation (03-02)
can be achieved by tying the On outputs to the On-1
inputs and holding the PE input low.
All parallel and serial data transfers are synchronous,
occurring after each LOW-to-HIGH clock transition. The
HC/HCT195 series utilizes edge-triggering; therefore, there
is no restriction on the activity of the J, K Pn and PE
inputs for logic operations, other than the set-up and hold
time requirements. A LOW on the asynchronous Master
Reset (MR) input sets all 0 outputs LOW, independent of
any other input condition.
The C054HC195 and C054HCT195 are supplied in 16-lead
hermetic dual-in-line ceramic packages (F suffix). The
C074HC195 and C074HCT195 are supplied in 16-lead
dual-in-line plastic packages (E suffix) and in 16-lead dualin-line surface mount plastic package (M suffix). Both
types are also available in chip form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +B5° C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to
LSTTL Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity: ML = 30%, MH=30% of Vee
@Vee=5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'L=O.B V Max., V'H=2 V Min.
CMOS Input Compatibility
/, ::; 1 p.A @ VOL, VOH
16 Vee
15
ao
14 01
00
13 Q2
D1
12 03
D2
1103
D3
10 CP
GNO
9
L.--._-l
PE
92CS 36827
TERMINAL ASSIGNMENT
___________________________________________________________________ 285
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC195
CD54/74HCT195
_I
MR
15
QO
Function Table
QI
92CM- 37012Rt
Fig. 1 - Logic diagram.
INPUTS
PE
J
OUTPUTS
flR"
~
Asynchronous Reset
L
X
X
X
""K
X
Shift, Set first stage
H
H
H
H
H
./
./
h
h
h
h
I
I
~
h
h
I
~
h
I
~
I
X
Operating Modes
Shift, Reset first stage
Shift, Toggle first stage
Shift, Retain first stage
Parallel Load
On
00
01
02
03
L
L
L
L
H
H
qo
q,
q2
q2
L
qo
q,
q2
q2
Cio
qo
qo
q,
q2
q2
h
X
X
X
X
X
q,
q2
q2
X
dn
do
qo
d,
d2
do
00
03
H=HIGH voltage level.
L=LOW voltage level.
X=Don't care.
I=LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition.
h=HIGH voltage level one set-up time priorto the LOW-to-HIGH clock transition.
dn (qn)=Lower case letters indicate the state of the referenced input (or output) one set-up time prior
to the LOW-to-HIGH clock transition.
--.l-;LOW-to-HIGH clock transition.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE. (Vecl:
(Voltages referenced to ground) .....
DC INPUT DIODE CURRENT. I'K (FOR V, < -0.5 V OR V, > Vee +0.5V) ....
DC OUTPUT DIODE CURRENT. 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V)
DC DRAIN CURRENT. PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V)
DC Vee OR GROUND CURRENT (Icc)
.......... .
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60° C (PACKAGE TYPE E) ..
For T. = +60 to +85°C (PACKAGE TYPE E) ....
For T. = -55 to +100°C (PACKAGE TYPE F. H)
For T. = +100 to +125°C (PACKAGE TYPE F. H)
...........
.... -0.5 to + 7 V
±20mA
±20mA
±25mA
±50mA
......................
Derate Linearly at 8 mW/o C to
. .................................
Derate Linearly at 8 mW;oC to
500
300
500
300
mW
mW
mW
mW
For T. = -40 to +70°C (PACKAGE TYPE M) .......................................................................... 400 mW
ForT. = +70 to +125°C (PACKAGE TYPE M) ............................................. Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F. H .................... .
-55 to +125°C
PACKAGE TYPE E, M ................ .
-40 to +85°C
STORAGE TEMPERATURE (T",) ............. .
-65 to +150° C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
+265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ......................................... .
.. ................... +300°C
286 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Technical Data
CD54/74HC195
CD54/74HCT195
STATIC ELECTRICAL CHARACTERISTICS
CD74HC195/CD54HC195
CD74HCT195/CD54HCT195
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
V
10
rnA
V"
V
+25"C
V,
V
V"
V
Min Typ Max Min Max Min Max
1.5
1.5
.1.5
4.5
3.15
3.15
3.15
to
6
4.2
4.2
4.2
5.5
High-Level
Input Voltage
V"'
Low-Level
Input Voltage
4.5
V"
High-Level
V(j,j
CMOS Loads
or
-0.02
V".
4.5
0.5
0.5
1.35
1.35
to
1.8
1.8
1.8
5.5
1.9
19
4.5
4.4
4.4
4.4
or
6
5.9
5.9
5.9
V".
3.84
3.7
5.34
5.2
Low-Level
V"'
-4
4.5
3.98
V".
-52
6
5.48
CMOS Loads
or
~
0.02
or
0.1
0.1
0.1
0.1
0.1
or
0.1
0.1
0.1
V".
4.5
0.26
0.33
0.4
6
0.26
0.33
0.4
V".
±1
Any
Voltage
Between
4.5
5.2
or
Vee
or
Current
4.5
44
4.5
3.98
4.4
4.4
V
-
-
3.84
-
3.7
V
4.5
0.1
01
V
0.4
V
,1
±1
/i A
80
160
/i A
450
490
/i A
0.1
V"
or
V".
V
V"
V"
Input Leakage
0.8
V".
0.1
V".
TTL Loads
0.8
V"
or
V"
Output Voltage
08
V"
V"
TTL Loads
V
4.5
0.5
1.35
1.9
V"
Output Voltage
Min Typ Max Min Max Min Max
-
.:!.O.l
±1
4.5
-
0.26
5.5
-
10.1
--
0.33
-
Vee
& Gnd
Gnd
Quiescent
V"
DeVice
or
Current
In
Vee
80
160
Gnd
5.5
4.5
Additional
Quiescent
DeVice Current
per input pin"
1 unit load
or
Gnd
VCI.- 2. 1
A Icc·
to
100 360
5.5
·For dual-supply systems theoretical worst case (VI - 2.4 V, Vee - 5.5 V) specification IS 1.B rnA.
HCT Input Loading Table
Input
Unit Loads'
00-03
PE
MR
CP
J, K
0.3
-0.65
0.3
0.3
0.3
·Unit Load is .6.lcc limit specified in Static Characteristic Chart,
e.g., 360 pA max. @ 25° C.
______________________________________________________________________ 287
Technical Data
CD54/74HC195
CD54/74HCT195
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating condilions should be selecled so Ihal operalion is always wllhln
Ihe following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA=Fuil Package Temperature Range)
Vee:"
CD54/74HC Types
CD54174HCT Types
DC Input or Output Voltage V;n, You!
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fail Times t"t,
at 2 V
at 4.5 V
at6 V
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
V
V
V
-40
-55
+85
+125
°C
°C
0
0
0
1000
500
400
ns
ns
ns
"Unless otherwise specified, all voltages are referenced to Ground.
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Input I" I, = 6 ns)
CHARACTERISTIC
CP to an Propagation Delay
Typical
CL
pF
HC
HCT
15
14
14
ns
t pHl
f MAX
15
15
14
50
Cpo
-
13
50
45
ns
MHz
pF
SYMBOL
t pHL
Unils
tpLH
MR toOn
Maximum Clock Frequency
Power Dissipation Capacitance"
50
"Cpo is used to determine the dynamic power consumption, per register.
PO = Cpo Vcc' fi + I C L Vcc' fa where
fi = input frequency
fa = output frequency
CL = output load capacitance
Vcc = supply voltage.
288 ___________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC195
CD54/74HCT195
Pre-requisite for Switching Function
CHARACTERISTIC
Clock Frequency
(Figure 3)
MR Pulse Width
(Figure 3)
Clock Pulse Width
(Figure 3)
Set-up Time
PE 10 Clock
(Figure 5)
Hold Time
J.K. PE to Clock
(Figure 5)
Removal Time
MR 10 Clock
(Figure 3)
SYMBOL Vee
IM,x
tw
Iw
too
J.K.
Ih
tREM
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
_55° C 10 +125° C
-40° C 10 +85° C
25°C
54HCT
UNITS
74HCT
54HC
HCT
74HC
HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
6
30
35
80
16
14
80
16
14
100
20
17
3
3
3
80
16
14
-
25
-
-
-
-
-
20
-
-
-
-
-
20
-
-
-
-
-
-
-
20
-
-
-
-
-
-
-
-
3
-
-
-
-
16
-
-
-
-
5
25
29
100
20
17
100
20
17
125
25
21
3
3
3
100
20
17
-
-
-
20
-
-
-
-
-
-
25
-
-
-
-
-
-
25
-
-
-
-
25
-
-
-
-
3
-
-
-
-
-
-
-
20
-
-
-
-
4
20
23
120
24
20
120
24
20
150
30
26
3
3
3
120
24
20
-
16
30
-
-
-
-
30
-
-
-
-
-
30
3
-
-
-
-
-
-
-
-
-
ns
ns
ns
-
ns
-
-
-
-
-
24
-
-
-
ns
ns
SWITCHING CHARACTERISTICS (Cl =50 pF, Inpul 1,,1,=6 ns)
CHARACTERISTIC
Propagation Delay
CPto Output
(Figure 3)
Propagation Delay
MR to Output
(Figure 3)
Output Transition
Time
Input Capacitance
SYMBOL Vee
t PLH
tPHL
tPHl
tplH
hLH
hHl
C,
2
4.5
6
2
4.5
6
2
4.5
6
-40° C 10 +85° C
-55° C 10 +125° C
25°C
HCT
74HC
74HCT
54HC
54HCT UNITS
HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
-
-
175
35
30
150
30
26
75
15
13
-
10
-
-
35
35
-
-
-
-
15
-
-
-
220
44
37
190
38
33
95
19
16
-
10
-
10
-
-
-
-
-
-
-
-
-
44
-
-
-
-
44
-
-
-
19
-
-
-
-
10
-
-
-
265
53
45
225
45
38
110
22
19
-
10
-
-
53
53
-
-
-
-
22
-
-
-
10
ns
ns
ns
pF
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 289
Technical Data
CD54/74HC195
CD54/74HCT195
i r - - - - - - INPUT
-
LEVEL
GNO
INPUT LEVEL
Q
GNO
tREM~
CLOCK
Vs
_ _ _ _ _ _ _ _...1.
I NPUT LEVEL
-
G"O
92CS-37009
92CS-37QIO
Fig. 4 - Master Reset pre-requisite and propagation delays.
Fig. 3 - Clock pre-requisite and propagation delays
and output transition times.
92CS-370tl
Fig. 5 - J,
K or Parallel Enable pre-requisite
times.
HC
HCT
50%
3V
1.3V
INPUT LEVEL
290 ___________________________________________________________________
________________________________________________________________ Technical Data
File Number
CD54/74HC221
CD54/74HCT221
1670
Advance Information/
Preliminary Data
High-Speed CMOS Logic
1e,
,.,
Vee
13
fA
4
18
iR
2ii
2A
28
10
10
11
Dual Monostable Multivibrator
with Reset
Type Features:
20
10
12
2Q
Vee
2C,
2.,
nCS-38!i26RI
• Overriding RESET Terminates Output Pulse
• Triggering From the Leading or Trailing Edge
• Q and Q Buffered Outputs
• Separate Resets
• Wide Range of Output-Pulse Widths
• Schmitt Trigger on B inputs
FUNCTIONAL DIAGRAM
The ReA-eD54174He221 and eD54/74HeT221 are dual
monostable multivibrators with reset. An external resistor
(R,) and an external capacitor (e,) control the timing and
the accuracy for the circuit. Adjustment of R, and e,
provides a wide range of output pulse widths from the Q
and Qterminals. Pulse triggering on the B input occurs at a
particular voltage level and is not related to the rise and fall
time of the trigger pulse.
Once triggered, the outputs are independent of further
trigger inputs on A and B. The output pulse can be
terminated by a LOW level on the Reset (R) pin. Trailingedge triggering (A) and leading-edge-triggering (B) inputs
are provided for triggering from either edge of the input
pulse. On power up, the Ie is reset. If either Mono is not
used each input (on the unused device) must be terminated
either high or low.
The minimum value of external resistance, R" is typically
The minimum value of external capacitance, e" is 0
pF. The calculation for the pulse width is tw = 0.7 R,e, at
Vee = 4.5 V.
soon.
The eD54HC/HCT221 are supplied in 16-lead ceramic
dual-in-line packages (F suffix). The CD74HC/HCT221 are
supplied in 16-lead dual-in-line plastic packages (E suffix)
and in 16-lead dual-in-line surface mount plastic packages
(M suffix). Both types are also available in chip form (H
suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85 0 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
NIL = 30%, N,H = 30% of Vee: @ Vee = 5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, :S 1 I1A @ VOL, V OH
iA
,
vee
"
iR
iQ
2Q
2e,
2Cx Rx
GNO
lex RX
"
,e,
"
.a
5
"
2Q
6
"
'"
J
,
,
8
10 29
g
2A
TERMINAL ASSIGNMENT
_________________________________________________________________ 291
Technical Data _____________________________________________________________
CD54/74HC221
CD54/74HCT221
Vee
18
--1
I
I
I
.~
Rx~:
POWER·ON
RESET
I
I
I
I
15(7)
-
...
:
I
I
I
R3
I
ex;t,
I
I
R4
I
I
14(6)
I
_...1
QI--h---+l-+---i
OPAMP
92CL - 38525R3
Fig. 1 - Logic diagram
TRUTH TABLE
X
H
X
L
L
X
L
INPUTS
B
X
L
1{
H
H
H
H
L
f
H
X
H
~
OUTPUTS
Q
Q
L
H
L
H
I1
U
n
L
n·
1J"
H
U·
H = High Level
f
L = Low Level
= Transition from Low
to High
=Transition from High to Low
I l = One High Level Pulse
U = One Low Level Pulse
L
X = Irrelevant
"For this combination the reset input must be low and the following
sequence must be used: pin 1 (or 9) must be set high or pin 2 (or
10) set low; then pin 1 (or 9) must be low and pin 2 (or 10) set high.
Now the reset input goes from low-to-high ·and the device will be
triggered.
292 _________________________________________________________________
Technical Data
CD54/74HC221
CD54/74HCT221
STATIC ELECTRICAL CHARACTERISTICS
CD74HC221/CD54HC221
CD74HCT221/CD54HCT221
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
+25°C
-401
+85°C
-551
+125°C
+25°C
-401
+85°C
-551
CHARACTERISTIC
UNITS
V,
V
10
Vee
V
mA
V,
V
Vee
V
Min Typ Max Min Max Min Max
Min Typ Max Min Max Min Max
High-Level
Input Voltage
4.5
V,"
1.5
1.5
1.5
3.15
3.t5
3.15
to
4.2
4.2
4.2
5.5
Low-Level
Input Voltage
4.5
V"
6
High-Level
Output Voltage
VO "
CMOS Loads
or
-0.02
4.5
V,"
4.5
0.5
0.5
0.5
4.5
t.35
1.35
1.35
to
1.8
1.8
1.9
V"
1.8
Low-Level
Output Voltage
1.9
4.4
4.4
4.4
or
5.9
5.9
5.9
V,"
-4
V,"
-5.2
CMOS Loads
or
4.5
3.98
3.84
3.7
5.48
5.34
0.02
or
5.2
Input Leakage
Vee
V,"
Current
0.1
0.1
0.1
0.1
or
0.1
0.1
0.1
V,"
4.5
0.26
0.33
0.4
6
0.26
0.33
0.4
V,"
±1
±1
Any
Voltage
Between
Vee
& Gnd
80
160
4.5
Device
or
Current
I"
4.4
4.5
3.98
4.4
4.4
V
-
-
3.84
-
3.7
V
4.5
0.1
0.1
0.1
V
0.4
V
±1
±1
I1A
80
160
I1A
450
490
I1A
V"
5.2
-
or
Vee
4.5
V"
±G.l
or
Gnd
Quiescent
V
V,"
0.1
V"
or
0.8
0.8
V"
0.1
V,"
TTL Loads
O.B
V"
or
V"
Va,
V
5.5
1.9
V"
TTL Loads
+125°C
4.5
-
0.26
5.5
-
:to, 1
-
0.33
-
V"
6
or
5.5
Gnd
Gnd
Additional
4.5
Quiescent
Device Current
per input pin:
1 unit load
.6.lcc·
Vcc-2 .1
to
100
360
-
5.5
-For dual-supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specification is 1.B rnA.
HCT Input Loading Table
Input
All Inputs
Unit Loads'
0.3
'Unit Load is ll.lcc limit specified in Static Characteristic
Chart, e.g., 360 pA max. @ 25 0 C.
______________________________________________________________________ 293
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC221
CD54/74HCT221
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) .................................................................................. -0.5 to + 7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5V) ..................................................... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR V. < -0.5 V OR V" > Vee +0.5V) ................................................. ±20mA
DC DRAIN CURRENT, PER OUTPUT (I.) (FOR -0.5 V < V. < Vee + 0.5V) .................................................. ±25mA
DC Vee OR GROUND CURRENT (Icc) ................................................................................... ±50mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60·C (PACKAGE TYPE E) ............................................................................. 500 mW
For T. = +60 to +85" C (PACKAGE TYPE E) ............................................... Derate linearly at 8 mW/· C to 300 mW
For T. = -55 to +l00'C (PACKAGE TYPE F, H) ......................................................................... 500 mW
For T. = +100 to +125"C (PACKAGE TYPE F, H) ........................................... Derate linearly at 8 mW/"C to 300 mW
For TA = -40 to +70·C (PACKAGE TYPE M) .............................................................. 400 mW
For TA = +70 to +125°C (PACKAGE TYPE M) ...........•......•...•.......... Derate Linearly at6 mW/·C to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H .......................................................................................... -55 to +125·C
PACKAGE TYPE E, M ........................................................................................... -40 to +85·C
STORAGE TEMPERATURE (T...) ................................................................................. -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59± 0.79 mm) from case for 10 s max...................................................... +265"C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................................................................................ +300·C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vee:*
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V" Vo
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t" t,
on InputsAandR
at2V
at4.5V
at6V
Input Rise and Fall Times t" t,
on Input B
at2V
at4.5V
at6V
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vec
-40
-55
+85
+125
DC
0
0
0
1000
500
400
ns
ns
ns
0
0
0
Unlimited
Unlimited
Unlimited
ns
ns
ns
V
V
V
·C
*Unless otherwise specified, all voltages are referenced to Ground.
SWITCHING CHARACTERISTICS (Vee
=5 V, TA =25·C, Input t"
t,
=6 ns)
CL
(pF)
CHARACTERISTIC
TYPICAL
54n4HC
54/74HCT
UNITS
Propagation Delay
A,
B, RtoO
tpLH
15
18
18
ns
A,
B,Rtoa
tPHL
15
14
14
ns
Cpo
-
166
166
pF
Power Dissipation Capacitance*
'Cpo IS used to determtne the dynamiC power consumption, per multivibrator.
Po =(Cpo+C,) Vee' I, + ! (C, Vee' f.) where:
f, = input frequency.
f" = output frequency.
C, = output load capacitance.
Vee = supply voltage.
assuming f, ~ .J..
·tw
294 ___________________________________________________________________
_______________________________________________________________ TechnicaIData
CD54/74HC221
CD54/74HCT221
PREREQUISITE FOR SWITCHING FUNCTION
CHARACTERISTIC
Vee
Input Pulse Width
tWL
A
B
tWH
Reset
tWL
Recovery Time
R toAor B
tREe
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
25°C
-40°C to +B5°C
-55°C to +125°C
74HCT
54HC
HC
HCT
74HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
90
105 70
14
14
18
18
21
21
ns
18
12
15
105 70
90
14
18
21
21
14
18
ns
18
15
12
105 70
90
14
18
18
23
21
27
ns
15
18
12
0
0
0
0
0
ns
0
0
0
0
0
0
0
-
Output Pulse Width
o ora
C, = 0.1 /1F R, = 10k n
Output Pulse
Width OorO
C, = 28 pF, R, = 2K n
C,= 1000 pF, R, = 2Kn
C, = 1000 pF, R, = 10K n
770
770
602
798
602
798
-
-
-
-
-
-
-
ns
-
-
-
-
-
-
/1S
-
-
-
-
-
-
-
-
-
/1S
5
tw
4.5
Typical
140
Typical
140
-
tw
4.5
1.5
1.5
7
tw
4.5
630
630
tw
7
595
805
595
805
/1S
SWITCHING CHARACTERISTICS (Cc = 50 pF, Inputt" I, = 6 ns)
CHARACTERISTIC
SYMBOL
Vee
Propagation Delay,
Trigger
A, B,RtoO
t pLH
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
ft.,
B,RtoQ
Propagation Delay
RtoO
Rtoa
Outpul
Transition Time
t PHL
t pLH
t pHl
hLH
hHl
Input Capacitance
Pulse Width match
between circuits in
the same package
C,=1000 pF,R,=10Kn
Con
4.5
to
5.5
_40° C 10 +85° C
-55°C 10 +125°C
25°C
54HC
54HCT
74HC
HC
HCT
74HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
-210 - 265 315 42
42
53
53
63
ns
63
36
45
54
215 255 170 34
34
43
43
51
51
ns
29
37
43
200 - 240 160 32
38
40
48
48
57
ns
27
34
41
225 180 270 45
46
54
36
37
56
ns
31
38
46
110 75
95
19
19
22
22
ns
15
15
16
13
19
10
10
10
pF
10
10
10
-
-
Typical
±2
Typical
±2
-
-
-
-
-
-
-
-
%
______________________________________________________________________ 295
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD5.4/74HC221
CD54/74HCT221
INPUT LEVEL
R
tw = O.7Rx ex
BINPUT------------+-J
AINPUT---------------
92CS- 38555
Fig. 2 - Recovery times,
If to A or B.
Q---,,[I
ITlH
54174HC
54174HCT
3V
1.3 V
Vcc
Input Level
Switching Voltage, Vs
500f0VCC
~-------tw------~
92CS-38556
Fig. 3 - Triggering of One Shot by input A or input B for
a period two
SUPPLY VOLTAGE (Vccl-V
AMBIENT TEMPERATURE (TA)-OC
92CS-4054Q
92CS-040539
Fig. 4 - HCmCT221 Output Pulse Width vs. Temperature.
10'
vee ~ 2V
10'
'1
~
104
~~ ~
ff~ /"
~/
1
t
t03
z
b
i ,02
~
~
,0'
/
/
1
~
::,
j
102
~
~
A
L
~.:"l-r--
rF~
'"
b
10
'. £...
~
~ /'"
;/
0.1
0.1
'0
2
2 ~
"24 ~ /
110
...
,
VCC· 4 .5V
10'
~~
.'"
'0
Fig. 5 - HC/HCT221 K Factor vs. Supply Voltage.
10 2
103
10 4
105
10 6
10 7
TIMING CAPACITANCE (Cxl-pF
92CS-40541
Fig. 6 - HC221 Output Pulse Width vs. CX.
10 8
'0
10 2
tal
104
10 5
106
TIMING CAPACITANCE (C.,I-pF
10 7
108
92CS-40542
Fig. 7 - HC/HCT221 Output Pulse Width vs. Cx.
296 ___________________________________________________________________
_____________________________________________________________ Technical Data
CD54/74HC221
CD54/74HCT221
la'
Vee =6V
/
10'
10'
la'
§
4
Va':~o
/
~/:
~V/ V
~V
q..;'O~
10 2
~.
10
:f
1
0.1
TIMING CAPACITANCE (C"l-pF
Fig. 8 - HC221 Output Pulse Width vs, CX"
_________________________________________________________________ 297
Technical Data
CD54/74HC240/241 /244
CD54/74HCT240/241/244
File Number
1656
High-Speed CMOS Logic
~~
1AO
1A1
1A2
1A3
2AO
2A1
2A2
2A3
~
241
10E 10E
20E 20E
2
18
4
16
6
14
8
12
11
9
13
15
7
5
17
3
1YO 1YO
1Y1 iYi
1Y2
1Y3
ill
ffi
2VO
2YO
2Y1
2Y2
ill
2Y3
2v3
vCC
GND
0
0
ffi
20
10
92CS-38495
FUNCTIONAL DIAGRAM AND
TERMINAL ASSIGNMENT
Octal Buffer/Line Drivers, 3-State
CD54174HC/HCT240 Inverting
CD54174HC/HCT241 Non-Inverting
CD54174HC/HCT244 Non-Inverting
Type Features:
• Typical propagation delay = 8 ns
@ Vcc=5 V, C L=15 pF, h=25°C for HC240
• 3-State outputs
• Buffered inputs
• High-current bus driver outputs
The RCA-CD54/74HC240 and CD54174HCT240 are inverting
3-state buffers having two active-low output enables. The RCA
CD54174HC/HCT241 and CD54174HC/HCT244 are noninverting 3-state buffers that differ only in that the 241 has one
active-high and one active-low output enable, and the 244 has
two active-low output enables. All three types have identical
pinouts.
The CD54HC240/241/244 and CD54HCT240/241/244 are
supplied in 20-lead ceramic dual-in-line packages (F suffix). The CD74HC240/241/244 and CD74HCT240/241/244
are supplied in 20-lead dual-in-line plastic packages (E
suffix) and in 20-lead dual-in-line surface mount plastic
packages (M suffix). The CD54/74HC/HCT240/241/244 are
also supplied.in chip form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85° C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• Alternate Source is Philips/Signetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
N ll =30%,N ,H =30% of Vee: @l Vec=5 V
• CD 54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'l =0.8 V Mas., V,H =2 V Min.
CMOS Input Compatibility
I, S 1 JiA @l VOL, VO H
TRUTH TABLE
OUTPUT
INPUTS
1"O'E,2OE
A
-Y
L
L
H
L
H
L
H
X
Z
92CS-38496RI
(HC/HCT240)
Fig. 1 - CD54174HCIHCT240 logic diagram.
298 ____________________________________________________________________
Technical Data
CD54/7 4HC240/241 1244
CD54/7 4HCT240/241 1244
2A1
2A2
2A3
92C$-38497RI
Fig. 2 - CD54174HCIHCT241 logic diagram.
TRUTH TABLE
INPUTS
10E
1A
L
L
H
L
H
X
OUTPUT
1Y
L
H
Z
H=HIGH Voltage Level
L=LOW Voltage Level
X=lmmaterial
Z=HIGH Impedance
1AO
1A1
1A2
INPUTS
2A
20E
L
X
H
L
H
H
OUTPUT
2Y
Z
L
H
(HCT/HCT241)
1A3
2AO
2A2
2A1
2A3
92CS-38498RI
Fig. 3 - CD54174HCIHCT244 logic diagram.
TRUTH TABLE
INPUTS
10E 20E
L
L
H
OUTPUT
A
L
H
X
Y
L
H
Z
(HC/HCT244)
____________________________________________________________________ 299
Technical Data
CD54/74HC240/241 /244
CD54n4HCT240/241/244
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ......•....••......•••••...•.................•••...........•....•••.........•......... -0.5 to +7 V
DC INPUT DIODE CURRENT, 1,K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ...•...............•................................... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR V. < -0.5 V OR V. > Vee +0.5 V) ..........•....•..••..............•...•.....•••..•. ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < V. < Vee +0.5 V) ...............•.•...................•......•....•.. ±35 mA
DC Vee OR GROUND CURRENT, (Icc) ..•••...••......•.•••..............•........•••....••...........••......•....•....... ±70 mA
POWER DISSIPATION PER PACKAGE (Po):
ForT. = -40 to +60°C (PACKAGE TYPE E) ••.........•.•.••....••...•....................................•......•......... 500 mW
For T. = +60 to +85°C (PACKAGE TYPE E) ..........•..............•..........•....••....... Derate Linearly at 8 mW/oC to 300 mW
ForT. = -5510 +100°C (PACKAGE TYPE F, H) .....•....•......................•.......................................... 500 mW
For T. = +100 to +125°C (PACKAGE TYPE F, H) .................................•............ Derate Linearly at 8 mWfOC to 300 mW
For T. = -40 to +70° C (PACKAGE TYPE M) ..•.••.....••..•....•.•.•...•.••••••.....•.•.••.•..•.•.•••.••..••.•.•...•...•. 400 mW
For T. = +70 10 +125·C (PACKAGE TYPE M) ••.•......••....•.....•......•..••..•••.....•...• Derate Linearly at 6 mWI"C to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H ....•.........................................................•...•.........•................ -55 to +125°C
PACKAGE TYPE E, M •...•...•................................................•.................................... -40 to +85° C
STORAGE TEMPERATURE (Tsto ) •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• -6510 +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
. .•...•..•...•........•...........•..............••.. +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only .......•....................•.....•.............••..•.•..•....•.................•.. +300° C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA-Full Package-Temperature Range) Vee:·
CD54n4HC Types
CD54n4HCT Types
DC Input or Output Voltage VI, Va
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t" tf
at2V
at 4.5 V
at6V
LIMITS
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
-40
-55
+85
+125
·C
0
0
0
1000
500
400
ns
V
V
·Unless otherwise specified, all voltages are referenced to Ground.
300 ___________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/7 4HC240/241 1244
CD54/7 4HCT240/241 1244
STATIC ELECTRICAL CHARACTERISTICS
CD74HC240/241/244, CD54HC240/241/244
CD74HCT240/241/244, CD54HCT240/241/244
---,--TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
CHARACTERISTIC
UNITS
-401
-551
'85°C
'125°C
10
Vee
V
rnA
V
V,
Vee
V
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
V,H
Low-Level
Input Voltage
VIL
High-Level
V,L
Output Voltage
VOH
CMOS Loads
or
-0.02
V,H
2
1.5
-
-
1.5
-
1.5
-
4.5
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
19
-
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,H
-
3.84
-
37
-
or
(Bus Driver)
V,H
-7.8
6
5.48
-
-
5.34
-
5.2
-
V,H
2
-
-
0.1
-
0.1
-
0.1
V,L
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,H
4.5
-
-
0.26
-
0.33
-
0.4
or
6
-
-
0.26
-
0.33
-
0.4
V,H
6
-
-
±O.1
-
±1
-
±1
Any
Voltage
between
Vee
&
Gnd
6
-
-
8
-
80
-
160
V,L
V,H
VIL
or
(Bus Driver)
V,H
Input Leakage
Vee
Current
I,
7.8
Gnd
Vee
Device
or
Current
Gnd
Icc
2
-
-
0.8
-
0.8
4.5
4.4
-
-
4.4
4.5
3.98
-
-
-
V
to
-
0.8
V
-
4.4
-
V
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
::':0.1
-
±1
-
±1
/JA
5.5
-
-
8
-
80
-
160
/J A
-
100
360
-
450
-
490
/JA
±0.5
-
±5
-
±10
/JA
V,L
6
or
Quiescent
-
VIL
-
TTL Loads
2
V,L
3.98
CMOS Loads
-
5.5
4.5
or
-
4.5
-
-6
VOL
2
to
5.5
or
Output Voltage
Typ Max Min Max Min Max
4.5
-
TTL Loads
Low-Level
-551
+125°C
-'r-Min
4.5
V,L
-401
+85°C
+25°C
+25°C
V,
Vee
a
or
Gnd
Additional
45
Quiescent
Vee-2.1
Device Current
to
5.5
per input pin"
1 unit load
.6.lcc
3-state
VIL
leakage
or
or
V,H
Gnd
current
10'
Vo=Vcc
VIL
6
-
-
-
±O 5
-
±5
-
±10
or
5.5
-
-
V,H
·For dual-supply systems theoretical worst case (VI:::' 2.4 V, Vee = 5.5 V) specification is 1.8 mAo
________________________________________________________________ 301
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54n4HC240/241/244
CD54/74HCT240/241/244
HCT Input Loading Tables
CD54n4HCT240
Input
Unit Loads'
nAO-A3
1.5
0.7
tOE
0.7
201;
'Unit
CD54n4HCT241
Input
Unit Loads'
nAO-A3
0.7
10E
0.7
20E
1.5
CD54174HCT244
Input
Unit loads'"
nAO-A3
0.7
10E
0.7
20E
0.7
Load is dlee limit specified in Static Characteristic Chart, e.g., 360pA max.@25°C.
SWITCHING CHARACTERISTICS (Vee=5 V, T.=25°C, Inpul Ir, 1,=6 ns)
Typlcat Values
CHARACTERISTIC
SYMBOL
240
CL
pF
Propagation Delay
Data to Output
tpHL tpLH
Output Disable/Enable to Outputs
tPZH. tPZL. tPHZ, tPLZ
Power Dissipation Capacitance
CpD
244
241
HC
HCT
HC
HCT
UNITS
HC
HCT
15
8
9
9
10
9
10
15
12
12
12
12
12
12
ns
-
38
40
34
38
46
40
pF
ns
CPO is used to determine the dynamic power consumption per channel.
PD=Vcc'f, (CPD + CLl
f.=input frequency.
C L = output load capacitance.
Vee = supply voltage.
SWITCHING CHARACTERISTICS (C L =50 pF, Inpul 1,,1,=6 n8)
-400 C 10 +850 C
25°C
CHARACTERISTIC
SYMBOL
HC
Vee
Min.
HCT
Max.
Min.
74HC
74HCT
Max.
Min.
Max.
Min,
Max.
125
-
-
-
150
28
33
26
-
-
-
140
-
-
165
-
-
25
-
28
31
33
-
38
-
24
28
-
-
140
-
25
-
28
-
Propagation Delay,
tplH
2
-
100
-
-
tpHL
4.5
-
20
-
22
6
-
17
-
-
110
22
-
19
-
-
-
24
150
-
-
-
190
-
, 30
38
-
-
60
Data to Outputs
tplH
2
HC/HCT241
tpHL
4.5
6
Data to Outputs
tplH
2
HC/HCT244
tPHL
4.5
6
.
Output
tPZH
2
Enable and
tPZL
4.5
Disable Times
tpHZ
6
22
19
110
30
26
54HCT
Min.
Data to Outputs
HC/HCT240
54HC
Max.
Max.
Min,
_55°C to +125°C
-
-
-
-
25
21
33
-
30
-
-
-
165
-
31
-
33
-
38
-
-
28
-
-
-
225
38
-
45
-
-
-
-
38
UNITS
ns
-
ns
ns
45
ns
-
tpLZ
Output
Transition Time
2
tTLH
4.5
tTHL
6
18
15
-
-
10
-
10
pF
-
20
-
20
pF
-
-
-
15
15
10
-
-
-
13
-
-
90
12
-
75
12
-
-
-
10
-
10
-
10
-
10
-
20
-
20
-
20
-
20
18
ns
-
Input
Capacitance
e,
3-State
Output
Capacitance
Co
302 __________________________________________
~
_______________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC240/241 /244
CD54/74HCT240/241 /244
IY
-
OUTPUTS
CONNECTED
OUTPUTS
DISCONNECTED
::L
-
V
OUTSpUTS
CONNECTED
92CS-3B517RI
92C5-38516
Input Level
Switching Voltage, Vs
54/74HC
VCC
50%VCC
54/74HCT
3V
1.3 V
Fig. 2 - Transition times and propagation delay times.
OTHER {
INPUTS
TIED HIGH
OR LOW
OI~.T~~~tL
-
{
Vee FOR IpLZ AND IpZL
GND FOR IpHZ AND IpZH
OUTPUT
DISABLE
92CS- 35130 R2
Fig. 4 - Three-state propagation delay test circuit.
_______________________________________________
~03
Technical Data ___________________________________________________________
CD54/74HC242, CD54/74HCT242
CD54/74HC243, CD54/74HCT243
File Number 1488
High-Speed CMOS Logic
FUNCTIONAL DIAGRAM
Quad-Bus Transceiver with
3-State Outputs
Type Features:
Typical propagation delay (A-B) of 7 ns @ Vee = 5 V
CL =15pF, TA=25°C
• 3-state outputs
• Buffered inputs
•
CD54174HC242, HCT242
The RCA-CD54/74HC242, 243 and CD54174HCT242, 243
silicon-gate CMOS 3-state bidirectional inverting and
non-inverting buffers are intended for two-way
asynchronous communication between data buses; They
have high drive current outputs which enable high-speed
operation when driving large bus capacitances. These
circuits possess the low power dissipation of CMOS
circuits, and have speeds comparable to low power
Schottky TTL circuits. They can drive 15 LSTTL loads.
The CD54174HC242 and CD54/74HCT242 are inverting
buffers; the CD54174HC243 and CD54/74HCT243 are
non-inverting buffers.
The states of the output enables (OEB, OEA) determine
both the.direction of flow (A to B, B to AJ, and the 3-state
mode.
The CD54HC242, 243 and CD54HCT242, 243 are supplied
in 14-lead hermetic dual-in-line ceramic packages (F
suffix). The CD74HC242, 243 and CD74HCT242, 243 are
supplied in 14-lead dual-in-line plastic packages (E suffix)
and in 14-lead dual-in-line surface mount plastic packages
(M suffix). Both types are also available in chip form (H
suffix).
Family Features:
•
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to
LSTTL Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity: ML =30%, MH =30% of Vee
@ Vee = 5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
. Direct LSTTL Input Logic Compatibility
V,L = 0.8.V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, :s 1 pA @ VOL, VOH
FUNCTIONAL DIAGRAM
-=-4----++~""-
BO
--"-4----++~>-"'--BI
A3 --"-4----#<1-<'-"- B3
OEB
DEA
---._ _ _- - - '
CD54/74HC243, HCT243
304 _________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC242, CD54/74HCT242
CD54/74HC243, CD54/74HCT243
I-;NZ-OF-;O;;; I~N~C~ ~R~I~
-
-
-
-
-
-
-
--I
-
Vee
I
14
I
I
I
I
I
I
I
I
I
I
An
3(4,5,6)
I
I
I
I
I
I
I
I
I__ ~_TO OTHER THREE
CHANNELS
92CM-37897 R2
Fig. 1 - Logic diagram for the CD54/74HC/HCT242. 243.
TRUTH TABLE
HC, HCT242 Series
HC, HCT243 Series
DATA PORT
STATUS
DATA PORT
STATUS
CONTROL
INPUTS
OEB
OEA
An
H
H
L
H
H
L
L
L
Bn
Bn
An
"0
I
0
I
Z
Z
Z
Z
Z
Z
Z
Z
I
"0
I
0
H = High
L = Low
I = Input
0= Output (Same Level as Input)
= Output (Inversion of Input Level)
Z = High Impedance
cr
To prevent excess currents in the
High Z modes all I/O terminals
should be terminated with 10 kel
to 1 Mel resistors.
_________________________________________________________________ 305
Technical Data ___________________________________
CD54/74HC242, CD54/74HCT242
CD54/74HC243,CD54/74HCT243
MAXIMUM RATINGS,Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ....................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ...•......................••.•.....•...•••..•....••..•. ±20 rnA
DC OUTPUT DIODE CURRENT, 10K (FOR V. < -0.5 V OR V. > Vee +0.5 V) .......................•.............••..•.......... ±20 rnA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < V. < Vee +0.5 V) ..................................................... ±35 rnA
DC Vee OR GROUND CURRENT, (Icc): ...................................................................................... ±70 rnA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60· C (PACKAGE TYPE E) ............................................................................... 500 mW
ForT. = +60 to +85·C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/·C to 300 mW
ForT. = -55 to +100·C (PACKAGE TYPE F) .............................................................................. 500 mW
ForT. = +100 to +125·C (PACKAGE TYPE F) ................................................ Derate Linearly at 8 mW/·C to 300 mW
For TA = -40 to +70·C (PACKAGE TYPE M) ........................................................................... 400 mW
ForTA = +70 to +125·C (PACKAGE TYPE M) ................................................ Derate Linearly at 6 mW/·C to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H ............................................................................................ -55 to +125·C
PACKAGE TYPE E, M ............................................................................................. -40 to +85·C
STORAGE TEMPERATURE (T... ) .................................................................................... -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ........................................................ +265· C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ..................................................................................... +300· C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating condlt.lons should be selected so that operation Is always within the
following ranges:
LIMITS
UNITS
CHARACTERISTIC
MIN.
MAX.
Supply-Vollage Range (For TA = Full Package Temperalure Range) Vee:'
2
6
V
4.5
5.5
V
0
Vee
V
CD74 Types
-40
+85
·C
CD54 Types
-55
+125
·C
at2 V
0
1000
ns
al 4.5 V
0
500
ns
al6 V
0
400
ns
CD54174HC Types
CD54/74HCT Types
DC Inpul or OUlpul Vollage V.. VO
Operating Temperalure TA:
Inpul Rise and Fall Times, I" t,
·Unless otherwise specified, all voltages are referenced to Ground.
306 __________-----------------------------------------------------
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC242, CD54/74HCT242
CD54/74HC243, CD54/74HCT243
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT242/243/CD54HCT242/243
CD74HC242/243/CD54HC242/243
TEST
CONDITIONS
74HC
TYPE
TYPE
-401
-551
+85"C
+125"C
74HC/54HC
TYPE
54HC
TEST
CONDITIONS
74HCT/54HCT
TYPE
74HCT
TYPE
54HCT
TYPE
-401
-551
+85"C
+125"C
UNITS
CHARACTERISTIC
+25"C
V,
V
Vee
V
10
mA
+25"C
V,
V
Vee
V
Min Typ Max Min Max Min Max
Min Typ Max Min Max Min Max
High-Level
Inpul Voltage
V,"
low-Level
Input Voltage
V"
2
1.5
-
-
1.5
-
1.5
-
4.5
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
6
High-Level
V"
Output Voltage
or
VO"
CMOS Loads
-0.02
V,"
4.5
-
2
1.9
-
-
1.9
-
1.9
-
V"
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
-6
4.5
3.98
-
-
3.84
-
3.7
-
or
(Bus Driver)
V,"
-7.8
6
5.48
-
-
5.34
-
5.2
-
V,"
V"
2
-
-
0.1
-
0.1
-
0.1
V"
or
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
CMOS Loads
V,"
V"
or
6
4.5
-
-
0.26
-
0.33
-
0.4
or
(Bus Driver)
V,"
7.8
6
-
-
0.26
-
0.33
-
0.4
V,"
Current
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±O.l
-
±1
-
±1
pA
5.5
-
-
8
-
80
-
160
pA
-
100 360
-
450
-
490
pA
-
-
-
±S.O
-
±lO
pA
to
Any
Vee
I,
-
V"
TTL Loads
Input leakage
2
V"
or
Vo•
-
5.5
TTL loads
Output Voltage
-
4.5
-
4.5
V"
Low-Level
2
to
5.5
or
-
6
-
Voltage
±O.l
-
±1
-
8etween
±1
Vee
Gnd
Quiescent
& Gnd
Vee
Device
or
Current
Gnd
Icc
Vee
0
-
6
-
8
-
80
-
160
Additional
Quiescent
Device Current
per input pin:
1 unit load
8. Icc
3-State
Leakage
Current
4.5
Vcc-2.1
to
5.5
V"
or
10'
or
Gnd
V,"
Va - Vee
or
Gnd
-
6
-
±O.S
-
±S.O
-
±lO
V"
or
5.5
±O.S
V,"
-For dual-supply systems theoretical worst case (VI
=2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
An. Bn
OEA. OEB
·Unit Load is
~Icc
Unit Loads *
1.1
0.6
limit specified in Static Characteristic Chart,
e.g., 360pA max.@25"C.
___________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 307
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC242, CD54/74HCT242
CD54/74HC243, CD54/74HCT243
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Inpul I" If = 6 ns)
Typical
CHARACTERISTIC
SYMBOL
Propagation Delay
UNITS
CL
pF
HC242
HCT242
HC243
HCT243
15
7
8
7
9
ns
15
12
14
12
14
ns
14
ns
91
pF
IPHL
Data 10 Outpul
IpLH
Enable to High Z
tpHZ, tPLz
Enable from High-Z
tpZH, tPZL
Power Dissipation Capacilance'
Cpo
15
12
14
12
-
85
90
80
'Cpo is used to determine the dynamic power consumption, per channel.
Po = Vee2 f, (Cpo + Cel where:
f, = inpul frequency.
CL = output load capacitance.
Vee = supply voltage.
SWITCHING CHARACTERISTICS (CL
=50 pF, Inpul I" If =6 ns)
-40°C 10 +85°C
25°C
CHARACTERISTIC
SYMBOL
HCT
HC
Vee
74HC
-55°C 10 +125°C
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay
135
-
-
-
27
-
30
-
20
-
-
-
23
-
-
-
115
-
-
-
135
22
-
23
-
28
-
27
-
-
-
-
20
-
-
-
23
-
-
190
-
-
-
225
-
-
34
-
38
-
43
-
45
-
51
-
-
33
-
-
-
38
-
-
-
190
-
225
44
45
-
53
33
-
-
38
-
-
90
150
tPLZ
4.5
30
26
-
60
-
-
-
75
-
-
-
12
-
15
-
15
-
18
-
-
13
-
-
-
-
10
-
10
-
10
-
15
10
-
-
-
12
C,
-
10
-
10
pF
Co
-
20
-
20
-
20
-
20
-
20
-
20
pF
4.5
-
18
6
-
15
6
for HC/HCT243
15
Oulput High-Z:
tpzH
2
-
150
to High Level;
tpZL
4.5
-
30
26
to Low Level
6
ITLH
2
ITHL
4.5
6
3-State Output
Capacitance
-
25
-
90
2
tPHL
I nput CapaCitance
-
-
2
18
tpLH
Time
-
23
6
90
Data to Outputs
Output Transition
115
tPHZ
-
4.5
Propagation Delay
Output Low Level
to High-Z
-
-
-
2
tPHL
HC/HCT242
Output High Level;
-
20
-
t PLH
-
Data to Outputs
10
35
-
38
-
33
ns
ns
ns
-
18
ns
ns
308 _________________________________________________________________
___________________________________________________________ TechnicaIData
CD54/74HC242, CD54/74HCT242
CD54/74HC243, CD54/74HCT243
OTHER {
IN PUTS
TIED HIGH
OR LOW
IC WITH
3-STATE
OUTPUT
OUTPUT
ENABLE
OUTPUTRL'lk!ljVCC FOR tpLZ AND tpZL
GND FOR I PHZ AND I PZH
.I.
= CL50PF
92CS-37900RI
Fig. 2 - Three-state propagation delay test circuit.
INPUT
LEVEL -
OEA
V IN
GND
VOUT
HC/HCT242
VOUT
OUTPUTS
CONNECTED
OUTPUTS
CONNECTED
tTLH
92CS- 36988
92CS-36987
Input Level
Switching Voltage, V.
54174HC
54174HCT
Vcc
3V
50% Vce
1.3 V
Fig. 3 - Transition times and propagation delay times.
ORDERING INFORMATION
i5EB
14 Vee
NC
13 OEA
AO
12 NC
AI
A2
A3
GNO
RCA CMOS device packages are identified by letters indicated in the following chart. When ordering a CMOS
device, it is important that the appropriate suffix letter be
affixed to the type number of the device.
Package
11
BO
10 B1
B2
B3
92CS·36829
TERMINAL ASSIGNMENT
Dual-In-Line Plastic
Dual-In-Line Frit-Seal Ceramic
Dual-In-Line Surface Mount Plastic
Chip
Suffix Letter
E
F
M
H
The CD54HC/HCT series is supplied in dual-in-line frit-seal
ceramic packages (F suffix). The CD74HC/HCT series is
supplied in dual-in-line plastic packages (E suffix) and in
dual-in-line surface mount plastic packages (M suffix).
Both series are supplied in chip form (H suffix).
For example, a CD54HC242 will be identified as the
CD54HC242F. The CD74HC242 will be identified as the
CD74HC242E.
________________________________________________________________ 309
TechnicaIOata _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54n4HC245
CD54/74HCT245
File Number 1651
High-Speed CMOS Logic
AD
BO
Al
Bl
A2
B2
A3
B3
A4
B4
AS
B5
A6
B6
AT
BT
Octal-Bus Transceiver, 3-State,
Non-Inverting
Type Features:
•
•
•
•
Buffered inputs
3-State outputs
Bus line driving capability
Typical propagation delay (A+-.B)
9 ns @ Vee =5V, CL =15 pF, TA =25° C
92CS-38468
FUNCTIONAL DIAGRAM
The RCA-CD54174HC245 and CD54174HCT245 are highspeed octal 3-state bidirectional transceivers intended for
two-way asynchronous communication between data
buses. They have high drive current outputs which enable
high-speed operation while driving large bus capacitances.
They provide the low power consumption of standard
CMOS circuits with speeds and drive capabilities comparable to that of LSTTL circuits.
The CD54/74HC245 and CD54/74HCT245 allow data transmission from the A bus to the B bus or from the B bus to
the A bus. The logic level at the direction input (DIR)
determines the direction. The output enable input (OE),
when high, puts the 1/0 ports in the high-impedance state.
The HC/HCT245 is similar in operation to the HC/HCT640
and the HC/HCT643.
The CD54HC245 and CD54HCT245 are supplied in 2Q-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC245 and CD74HCT245 are supplied in 20-lead
dual-in-line plastic packages (E suffix) and in 20-lead
dual-in-line surface mount plastic packages (M suffix). Both
devices are also available in chip (H suffix) form.
r - .Q.N!...O.E.8..IR~~~~S_ I
I
-
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating TemperatureRange:
CD74HCIHCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 30%, N'H = 30% of Vee: @ Vee = 5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'L = 0.8 V Max., V'H = 2 V Min.
CMOS Input Compatibility
I, ::s 1 /.lA @ VOL. VOH
----,~~'T~'8'l' 5,
I 9
A DATA
(18,17,16,15,1
14,13, 121 1
11
I
B DATAo---t-~--t-1
TRUTH TABLE
CONTROL
INPUTS
DIR
OE
H
92CS-38469RI
LOGIC DIAGRAM
OPERATION
L
L
B DATA TO A BUS
L
H
A DATA TO B BUS
H
X
ISOLATION
=high level, L =low level, X = irrelevant
To prevent excess currents in the High-Z (Isolation) modes all 1/0 terminals should be terminated with 10KCl to 1MO resistors.
310 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
- - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC245
CD54/74HCT245
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) .................................................................................. -0.5 to + 7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5V) ..................................................... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V) ................................................. ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V) .................................................. ±35mA
DC Vee OR GROUND CURRENT (lee) ................................................................................... ± 70mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60' C (PACKAGE TYPE E) ............................................................................. 500 mW
ForT. = +60 to +65°C (PACKAGE TYPE E) ............................................... Derate Linearly at 6 mW/'C to 300 mW
ForT. = -55 to +100°C (PACKAGE TYPE F, H) ......................................................................... 500 mW
ForT. = +100 to +125°C (PACKAGE TYPE F, H) ........................................... Derate Linearly at 6 mW/'C to 300 mW
For T. = -40 to +70'C (PACKAGE TYPE M) ............................................................................. 400 mW
For T. = +70 to +125'C (PACKAGE TYPE M) ............................................... Derate Linearly at 6 mW/'C to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H .......................................................................................... -55 to +125' C
PACKAGE TYPE E, M ........................................................................................... -40 to +85' C
STORAGE TEMPERATURE (T".) ................................................................................. -65 to +150' C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1132 in. (1.59 ± 0.79 mm) from case for 10 s max...................................................... +265'C
Unit inserted into a PC Board (min. thickness 1/16 in .. 1.59 mm)
with solder contacting lead tips only .................................................................................. +300'C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA - Full Package-Temperature Range) Vee:*
CD54/74HC Types
CD54/74HCT Types
DC Input or Outpul Voltage V" Va
Operating Temperature TA:
CD74 Types
CD54 Types
Inpul Rise and Fall Times I" I,
at 2 V
at 4.5 V
at6V
UNITS
MIN.
MAX.
2
4.5
a
6
5.5
Vee
V
V
V
-40
-55
+85
+125
°C
°C
a
a
a
1000
500
400
ns
ns
ns
*Unless otherwise specified, all vollages are referenced to Ground.
OIR
20
AO
19
vce
DE
18 BO
A1
4
17 B1
A3 5
16 B2
A4 6
15 B3
AS 7
14 84
A6 8
13 B5
A7 9
12 B6
A2
GN0 10
11 B7
TERMINAL ASSIGNMENT
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 311
TechnlcaI08t8 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54n4HC245
CD54/74HCT245
SIAIlC ELECTRICAL
CHARACTERISTICS
.CD74HC245/CD54HCT24S
TEST
CONDITIONS
CD74HC245/CD54HCT245
74HC/54HC
TYPES
74HC
TYPE
54HC
TYPE
+2S"C
-401
+85°C
-551
TEST
CONDITIONS
74HCT/54HCT
TYPES
74HCT
TYPE
54HCT
TYPE
+2S"C
-401
+85°C
-551
CHARACTERISTIC
UNITS
V,
V
10
mA
Vee
V
+125"C
V,
V
Vee
V
Min Typ Max Min Max Min- Max
High-Level
input Voltage
V,"
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
Vo.
CMOS Loads
or
-0.02
V,"
2
1.5
-
-
1.5
-
1.5
-
4.S
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.B
-
1.B
-
1.B
Min Typ Max Min Max Min Max
4.5
-
2
1.9
-
-
1.9
-
1.9
-
V"
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5
3.98
-
-
3.84
-
3.7
-
or
(Bus Driver)
V,"
-7.8
6
5.48
-
-
5.34
-
5.2
-
V,"
2
-
-
0.1
-
0.1
-
0.1
V"
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
V"
CMOS Loads
V,"
V"
or
6
4.5
-
-
0.26
-
0.33
-
0.4
or
(Bus Driver)
V,"
7.8
6
-
-
0.26
-
0.33
-
0.4
V,"
6
-
-
±O.l
-
±1
-
±1
Any
Voltage
Between
Vee
&Gnd
6
-
-
B
-
80
-
160
Input Leakage
Vee
i,
or
Gnd
Quiescent
Vee
Device
or
Current
Icc
2
-
V
-
-
O.B
-
O.B
-
O.B
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.B4
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±O.l
-
±1
-
±1
pA
5.5
-
-
B
-
80
-
160
pA
-
100 360
-
450
-
490
pA
-
-
-
±5.0
-
±10
pA
to
Vee
0
or
Gnd
Gnd
Additional
Quiescent
Device Current
per input pin:
1 unit load
Alee
4.5
Vcc-2.1
to
5.5
3-State
V"
Vo = Vee
Leakage Current
or
or
V,"
Gnd
10'
-
V"
TTL Loads
Current
2
V"
-6
or
-
5.5
or
Voe
-
4.5
-
TTL Loads
Output Voltage
2
to
5.5
V"
Low-Level
+125"C
V"
6
-
-
±O.5
-
-
±S.O
..
±10
For dual-supply systems theoretical worst case (VI - 2.4 V. Vee - 5.5 V) specification
or
5.5
±O.S
V,"
IS
1.8 rnA.
HCT Input Loading Table
Unit Loads·
l'!I!.ut
An or Sn
0.4
OE
1.5
DIR
0.9
..
'Unlt Load IS Ll.lcc limit specified In Static Characteristic
Chart, e.g., 360llA max. @ 25° C.
312 ______________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC245
CD54/74HCT245
SWITCHING CHARACTERISTICS (Vee = 5 V, T A = 25° C, Inpul I. If = 6 ns)
Cl
(pF)
CHARACTERISTIC
Propagation Delay
TYPICAL
HCT
HC
UNITS
t PHL
15
9
t pLZ
15
tPlH• tpll
15
-
Data to Output
10
ns
12
12
ns
12
13
ns
53
55
pF
tPLH
Enable to High-Z
tPHZ,
Enable from High-Z
Power Dissipation Capacitance"
Cpo
·C PO determines the no-load dynamic power consumption per channel. It is obtained by the following relationship:
Po =Vee' f. (Cpo + Cd where f. = input frequency.
C L = output load capacitance. Vee = supply voltage
SWITCHING CHARACTERISTICS (Inpul I" If = 6 ns, Cl = 50 pF)
TEST
CONDITION
Vee
CHARACTERISTIC
V
Propagation Delay
Data to Output
t pLH
t pHL
Propagation Delay
Output Disable
to Output
Propagation Delay
Output Enable
to Output
Output Transition
Time
t pLZ
tpHl
tPll
tPZH
hLH
hHl
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
LIMITS
_40° C 10 +85° C
-55°C 10 +125°C
HCT
74HC
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
165 140 26
28
33
33
39
ns
24
28
190 225 45
45
ns
30
38
38
38
33
190 225 38
45
48
ns
32
40
33
.38
75
90
12
15
15
18
18
ns
13
15
-
25°C
HC
Min. Max.
110
22
19
150
30
26
150
30
26
60
12
10
Input Capacitance
C,
-
-
10
-
10
-
10
-
10
-
10
-
10
pF
3-State Output
Capacitance
Co
-
-
20
-
20
-
20
-
20
-
20
-
20
pF
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 313
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54174HC245
CD54174HCT245
OTHER {
INPUTS
TIED HIGH
Ie
WITH
3-STATE
OUTPUT
OR LOW
OUTPUT
ENABLE
OUTPUT RL =-lkG
lVCC
FOR tpLZ AND tpZL
GND FOR IpHZ AND I PZH
:.t
C}OPF
92CS-37900
Three-state propagation delay test circuit.
OUTPUTS
OUTPUTS
CONNECTED
CONNECTED
92CS-38476R1
92CS-38407
I
I Input Level
I Switching_Voltage, Vs
I
I
54174HC
Vec
50% Vee
54174HCT
3V
1.3 V
I
I
I
Fig. 1 - Transition times and propagation delay times.
314 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
File Number
CD54/74HC251
CD54/74HCT251
1489
Advance Information/
Preliminary Data
High-Speed CMOS Logic
DE
a-Input Multiplexer; 3-State
Io
I I
'2
CHANNEL
I3
INPUTS
I4
IS
I6
I7
DATA
{SO
SI
15
OUT
14
13
5
'
Y} PUTS
12
10
SE l ECT
52
Type Features:
•
•
•
•
Selects one of eight binary data inputs
3-state output capability
True and complement outputs
Typical (data to output) propagation delay of
14 ns @ Vee=5 V, CL=15 pF, TA=-f25°C
L -_ _--'92CS - 36984
FUNCTIONAL DIAGRAM
The RCA-CD54174HC251 and CD54174HCT251 are 8-channel digital multiplexers with 3-state outputs, fabricated with
high-speed silicon-gate CMOS technology. Together with
the low power consumption of standard CMOS integrated
circuits, they possess the ability to drive 10 LSTTL loads.
The 3-state feature makes them ideally suited for interfacing
with bus lines in a bus-oriented system.
This multiplexer featu res both true (Y) and complement ill
outputs as well as an output enable (OE) input. The OE
must be at a low logic level to enable this device. When the
DE input is high, both outputs are in the high-impedance
state. When enabled, address information on the data select
inputs determines which data input is routed to the Yand'?
outputs. The CD54/74HCT251 logic family is speed, function, and pin-compatible with the standard 54LS174LS251.
The CD54HC251 and CD54HCT251 are supplied in 16-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC251 and CD74HCT251 are supplied in 16-lead
dual-in-line plastic packages (E suffix) and in 16-lead dualin-line surface mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 30%, MH = 30% of Vee; @ Vee = 5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, :S 1 /lA @ VOL, VO H
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 315
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC251
CD54/74HCT251
Vee
16
so ~ so
"§O
I6
13
S I
"
ST
~
SI
10
I7
_
~S2
i'-.
52~S2
~OE
"-
OE~OE
92CM-369B3RI
Fig. 3 - Logic diagram for HC/HCT251.
TRUTH TABLE
S2
X
L
L
L
L
H
H
H
H
INPUTS
SELECT
OUTPUT
CONTROL OE
S1
SO
X
H
X
L
L
L
L
L
H
L
L
H
L
H
H
L
L
L
L
L
H
L
L
H
L
H
H
--
OUTPUTS
Y
Y
Z
Z
10
11
12
13
14
15
16
17
10
11
12
13
14
15
16
17
H ; high logic level
L ; low logic level
X ; irrelevant
Z; high impedance (off)
' 0 - '1 .... '7; the level of the respective input
316 ____________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC251
CD54/74HCT251
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ..................................................................................... -0.5 to + 7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR Vi > Vee +0.5V) ......................................................... ±20mA
DC OUTPUT CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V) ............................................................ ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V) ...................................................... ±25mA
DC Vee OR GROUND CURRENT (Icc) ...................................................................................... ±50mA
POWER DISSIPATION PER PACKAGE (Po):
For TA ~ -40 to +60° C (PACKAGE TYPE E) ................................................................................ 500 mW
For TA ~ +60 to +85°C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/oC to 300 mW
For TA ~ -55 to +100°C (PACKAGE TYPE F, H) ............................................................................ 500 mW
For TA ~ +100 to +125°C (PACKAGE TYPE F, H) .............................................. Derate Linearly at 8 mW;oC to 300 mW
For T. ~ -40 to +70°C (PACKAGE TYPE M) ........................................................................ , ..... 400 mW
For TA ~ +70 to +125°C (PACKAGE TYPE M) ....... , ... , ..................................... Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H ............................................................................................. -55 to +125°C
PACKAGE TYPE E, M .............................................................................................. -40 to +85° C
STORAGE TEMPERATURE (T",) .................................................................................... -65 to +150° C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ......................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ..................................................................................... +300° C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation Is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA-Full Package Temperature Range)
Vee:"
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage V,n , Veul
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t"I,
at 2 V
al 4.5 V
al6 V
LIMITS
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
V
V
V
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
ns
ns
ec
"Unless otherwise specified, all voltages are referenced to Ground.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 317
Technical Data
CD 54/74H C251
CD54/74HCT251
STATIC ELECTRICAL CHARACTERISTICS
CD74HC251/CD54HC251
CD74HCT251/CD54HCT251
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
+25°C
-401
+85°C
-551
+125°C
+25°C
-401
+85°C
-551
+125°C
CHARACTERISTIC
UNITS
V,
V
10
mA
Vee
V
V,
V
Vee
V
Min Typ Max Min Max Min Max
High-Level,
Input Voltage
4.5
Vir!
1.5
1.5
1.5
3.15
3.15
3.15
to
4.2
4.2
4.2
5.5
V"
High-Level
Output Voltage
0.5
0.5
0.5
1.35
1.35
1.35
to
6
1.8
1.8
1.8
5.5
V"
VO"
CMOS Loads
or
-0.02
4.5
4.5
Low-Level
Input Voltage
4.5
V,"
Low-Level
Output Voltage
1.9
1.9
1.9
4.4
4.4
or
5.9
5.9
5.9
V,"
3.98
3.84
3.7
-4
V,"
-5.2
CMOS Loads
or
4.5
5.48
5.34
0.02
or
5.2
Input Leakage
V"
V,"
0.1
0.1
0.1
0.1
or
0.1
0.1
0.1
V,"
0.26
0.33
0.4
0.26
0.33
0.4
V,"
±1
±1
Any
Voltage
Between
V"
& Gnd
80
160
4.5
5.2
-
±O.1
Gnd
Quiescent
Vee
Device
or
Current
Icc
4.5
4.4
4.5
3.98
4.4
4.4
V
-
-
3.84
-
3.7
V
V"
4.5
0.1
0.1
V
0.4
V
±1
±1
/lA
80
160
/lA
0.1
or
4.5
-
0.26
5.5
-
±O.1
-
0.33
-
V"
6
Gnd
or
5.5
Gnd
4.5
Additional
QUI8scent
Device Current
per input pin:
i:1 Icc·
1 unit load
3-State
Leakage
Current
V
V"
4.5
or
Current
0.8
V,"
0.1
V"
or
0.8
V"
0.1
V,"
TTL Loads
0.8
V"
or
V"
Va'
V
4.5
4.4
V"
TTL Loads
Min Typ Max Min Max Min Max
Vcc-2.1
to
100 360
-
450
-
490
/lA
-
-
±S.O
-
±10
/lA
5.5
V"
or
V,"
Vo = Vee
or
Gnd
6
-
±O.S
-
±S.O
-
±10
V"
or
V,"
5.5
±0.5
·For dual-supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specification is 1.8 mAo
HCT Input Loading Table
Input
Unit Loads'
80,81,82
10-17
OE
0.55
0.5
2.65
318 ___________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC251
CD54/74HCT251
SWITCHING CHARACTERISTICS (Vee
= 5 V, TA = 25°C,
Inpul I"
=I, = 6 ns)
CHARACTERISTIC
Propagation Delay
Select to Outputs
Data to Outputs
Enable to High-Z and
Enable from High-Z
Power Dissipation Capacitance'
TYPICAL
HC
HCT
CL
(pF)
SYMBOL
tpHL
t pLH
t pLZ , t pHZ
t PZL • tPZH
CpD
UNITS
15
21
18
ns
15
12
12
ns
15
11
12
ns
-
60
60
pF
'CPO is used to determine the dynamic power consumption, per package.
PO =Vee2 f, (Cpo + Cd where f, =input frequency
C L = output load capacitance
Vee = supply voltage
SWITCHING CHARACTERISTICS (C L
CHARACTERISTIC
Propagation Delay,
Select to Ouputs
Propagation Delay
Data to Outputs
Propagation Delay
Enable to High Z &
Enable From High Z
Output Transition
Time
Input Capacitance
3-State Output
Capacitance
= 50 pF, Inpul I" =I, = 6 ns)
SYMBOL
Vee
t pLH
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
t pHl
t pU !
t pHL
t plZ , t PHZ
t PZL • t PZH
hLH
trHL
_55° C to
_40° C to +85° C
25°C
HC
HCT
74HC
74HCT
54HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
370
245 305
53
42
49 61
74
63
42 52 175 220 265
35
53
35 44 44
-
C,
-
Co
-
30
140
28
24
75
15
13
10
15
-
-
-
-
-
-
-
30
-
-
-
-
-
-
-
-
15
-
-
-
-
10
-
15
-
37
175
35
30
95
19
16
10
15
-
-
-
-
-
-
-
38
-
-
-
-
-
-
-
-
19
-
-
-
-
10
-
15
-
45
210
42
36
110
22
19
10
15
+125° C
54HCT
UNITS
Min. Max.
-
-
-
63
-
-
-
-
-
53
-
-
-
-
-
45
-
-
-
-
-
22
-
-
-
ns
ns
ns
ns
10
pF
15
pF
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 319
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC251
CD54/74HCT251
,,----VOH
92CS- 36986
92CS-36985RI
Input Level
Vs
54174HC
54174HCT
Vee
50% Vee
3V
1.3 V
I
I
I
Fig. 1 - Transition times and propagation delay times.
OTHER {
I N PUTS
TIED HIGH
OR LOW
~~s~g~
OUTPUT RL olkU jVCC FOR IpLZ AND IpZL
GND FOR I PHZ AND I PZH
OUTPUT
ICL
= 50PF
OUTPUT
DISABLE
92CS-35129Rl
Fig. 2 - Three-state propagation delay test circuit.
16
I3
I2
15
II
I.
IO
•
13
12
y
Y
6
11
DE
7
10
GND
9
Vee
I'
I5
I6
I7
50
51
52
92C5-36831
TERMINAL ASSIGNMENT
320 __________________________________________________________
_____________________________________________________________ Technical Data
CD54/74HC253
CD 54/74HCT253
File Number 1673
High-Speed CMOS Logic
Dual 4-lnput Multiplexer
110
"1
112
113----,..._ _--'
Type Features:
• Common select inputs
• Separate output-enable inputs
• 3-state outputs
FUNCTIONAL DIAGRAM
The RCA-CD54174HC253 and CD54/74HCT253 are dual
4-to-1 line selector/multiplexers having 3-state outputs. One
of four sources for each section is selected by the common
select inputs, SO and Sl. When the output enable (10E or
20E) is HIGH, the output is in the high-impedance state.
The CD54HC253 and CD54HCT253 are supplied in 16-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC253 and CD74HCT253 are in 16-lead dual-in-line
plastic packages (E suffix). also in 16-lead dual-in-line
surface mount plastic packages (M suffix). These types are
also available in chip form (H suffix).
TRUTH TABLE
Select
Inputs
Output
Output
Enable
Data Inputs
10
I,
b
b
OE
y
X
X
L
H
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
H
L
L
L
L
L
L
L
L
Z
L
L
H
H
L
L
H
H
Sl
SO
X
L
L
L
L
H
H
H
H
X
X
X
X
X
X
L
H
X
X
X
X
L
H
L
H
L
H
L
H
Select Inputs SO and 81 are common to both sections.
H = high level, L= low level, X= irrelevant, Z = high impedance (off).
Family Features:
• Fanout (over temperature range):
Standard outputs - 10 LSTTL loads
Bus driver outputs - 15 LSTTL loads
• Wide operating temperature range:
CD74HCIHCT: -40 to +85 0 C
• Balanced propagation delay and
transition times
• Significant power reduction compared to
LSTTL logic ICs
• Alternate source is Philips/Signetics
• CD54H.GICD74HC types:
2 to 6 V operation
High noise immunity: ML=30%, MH=30% of Vee:
@ Vee=5 V
• CD54HCTICD74HCT types:
4.5 to 5.5 V operation
Direct LSTTL input logic compatibility
V,L =0.8 V max., V'H=2 V min.
CMOS input compatibility
I, :::; 1 I1A @ VOL, VOH
fOE
'6
vee
S,
15 mE
113
14 So
"2
'3 21 3
1"
12 212
110
6
10 210
1Y
GND
11 21,
8
9 2Y
TERMINAL ASSIGNMENT
______________________________________________________________ 321
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC253
CD54/74HCT253
~1S
YJE
20E
16
o--Vcc
8
o--GND
Fig. 1 - Logic diagram.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ...................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT. I'K (FOR Vi < -0.5 V OR Vi > Vee +0.5 V) ....................................................... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) ................................................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) .................................................... ±35 mA
DC Vee OR GROUND CURRENT, (Icc) ..................................................................................... ±70 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60° C (PACKAGE TYPE E) ................................................................................ 500 mW
For TA = +60 to +85° C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/o C to 300 mW
For TA = -55 to +100° C (PACKAGE TYPE F, H) ............................................................................ 500 mW
For TA = +100 to +125°C (PACKAGE TYPE F, H) .............................................. Derate Linearly at 8 mW;oC to 300 mW
ForTA = -40 to +70°C (PACKAGE TYPE M) ............................................................................. 400 mW
For TA = +70 to +125° C (PACKAGE TYPE M) . ... ... . . ... .. . ... . .. . . . .. . . .. . . . . . . . .. . .. . .. ... Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H ............................................................................................. -55 to +125° C
PACKAGE TYPE E, M ............................................................. . . . . . . . . . . . . .. . . . . . .. . . . .. . .. .. .. -40 to +85° C
STORAGE TEMPERATURE (T,t.) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
+265°C
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................................................................................... +300° C
322 ______________________________________________________
Technical Data
CD 54/74H C253
CD 54/74HCT253
STATIC ELECTRICAL CHARACTERISTICS
CD74HC253/CD54HC253
TEST
74HC/54HC
TYPES
CONDITIONS
CD74HCT253/CD54HCT253
74HCT/54HCT
74HC
54HC
TEST
TYPE
TYPE
CONDITIONS
-401
-551
+85 C1 C
+125'C
TYPES
74HCT
54HCT
TYPE
TYPE
-401
-551
+85'C
+125°C
CHARACTERISTIC
UNITS
+25'C
V,
10
ee
V
rnA
V
High-Level
Input Voltage
4.2
2
-
4.5
V"
6
High-Level
Output Voltage
V"
VO H
CMOS Loads
1.5
4.5 3.15
Low·Level
I nput Voltage
6
-
2
V,H
Min Typ Ma. Min Ma. Min ~a.
or
-0.02
V,H
2
1.9
-
4.5
4.4
6
5.9
-
-
-
3.15
-
3.15
4.2
-
4.2
1.35
1.5
1.5
-6
Bus Driver
V,H
-7.B
6
5.4B
2
-
0.02
4.5
-
-
-
-
4.5 3.9B
V"
VOL
CMOS Loads
or
V,H
6
6
4.5
Bus Driver
V,H
7.B
6
Quiescent Oevice
Current
lee
Vee
or
Gnd
Vee
or
Gnd
V
Min Typ Max Min Ma. Min Ma.
4.5
-
2
-
-
2
-
2
-
V
-
-
O.B
-
O.B
-
O.B
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.9B
-
-
3.B4
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
±0.1 -
±1
-
±1
pA
-
BO
-
160
pA
-
450
-
490
pA
-
±5
-
±10
pA
to
5.5
-
0.5
-
1.35
1.B
-
1.9
-
1.9
-
4.4
4.4
-
or
5.9
-
5.9
-
V,H
-
3.B4
-
3.7
-
or
5.34
-
5.2
-
V,H
0.1
0.1
-
0.1
V"
0.1
0.1
or
0.1
-
0.1
-
0.1
V,H
0.26
-
0.33
-
0.4
or
0.26
-
0.33
-
0.4
V,H
5.5
-
-
5.5
-
-
-
100 360
loB
-
0.5
4.5
"-
to
5.5
1.B
V"
0.1
V"
or
I,
V
0.5
V"
TTL Loads
Input Leakage
Current
Vee
V"
or
Low-Level
V,
1.35
V"
TTL Loads
Output Voltage
+25'C
0
6
-
-
±0.1
-
±1
-
±1
Any
Voltage
Between
Vee and
Gnd
6
-
-
B
-
BO
-
160
Vee
or
Gnd
B
Additional
4.5
Quiescent Device
Vee -2.1
Current per
1 Unit Load
Alec
3-State
Leakage
Current
to
5.5
Input Pin:
V"
or
loz
V,H
Vo=
6
Vee
-
-
±0.5 -
±5
-
±10
V"
or
5.5
-
-
±0.5
V,H
rGnd
*For dual-supply systems theoretical worst case (VI = 2.4 V, Vee
=5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
I
I
Input
Unit Loads·
110-11 3 • 210-21,
1 Eo. 2Eo. So. S,
0.4
·Unit Load is Il. Icc limit specified in Static Characteristics
___________________________________________________________________
323
Chart. e.g .• ::t1l0 p.A max. @ 25° C.
Technical Data __________________________________
CD54/74HC253
CD54/74HCT253
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operallng conditions should be selecled so that operation Is always within
the following ranges:
LIMITS
CHARACTERISTIC
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vcc
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
Supply-Voltage Range (For TA-Full Package Temperature Range)
Vee:·
CD54174HC Types
CD54/74HCT Types
DC Input or Output Voltage, V" Vo
Operating Temperature, T.:
CD74 Types
CD54 Types
Input Rise and Fall Times, t"t,:
at 2 V
at 4.5 V
at 6 V
V
V
'Unless otherwise specified, all voltages are referenced to Ground.
SWITCHING CHARACYERISTICS (Vcc=5 V, T .=25° C, Input t"I,=6 ns)
CHARACTERISTIC
Propagation Delay
Select to Outputs
Data to Outputs
Output Enabling Time
Output Disabling Time
Power Dissipation Capacitance'
CL
pF
SYMBOL
15
t pHL
TYPICAL
VALUES
HC
HCT
14
16
t pLz , t pHZ
9
12
Cpo
46
12
12
52
ns
t pLH
15
15
tPZL. tPZH
UNITS
pF
'CPO is used to determine the dynamic power consumption, per multiplexer.
Po=Vcc' fi (Cpo + Cel where: fi=input frequency
CL =Ioad capacitance
Vcc=supply voltage
SWITCHING CHARACTERISTICS (C L =50 pF, Input t"t,=6 ns)
CHARACTERISTIC
SYMBOL
VCC
Propagation Delay
Select to Outputs
t pLH
t pHL
Propagation Delay
Data to Outputs
t pLH
t pHL
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
Disable Delay
Times
tpLZ
Enable Delay
Times
t pZH
t pZL
Output Transition
Time
Input Capacitance
3-State Output
Capacitance
t pHZ
tTLH
tTHL
C
Co
-
_40° C to +85° C
25°C
-55°C 10 +125°C
HC
HCT
74HCT
54HC
54HCT
74HC
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
175 220 265 35
40
44
50
53
60
30
37
45
175 220
265
48
57
35
38
44
53
30
37
45
ns
150 190 225
30
45
30
38
38
45
26
33
38
110 140 165 22
30
28
45
ns
38
33
19
24
28
75
90
60
18
15
12
12
18
15
13
15
10
10
10
10
10
10
10
20
20
20
20
20
20
pF
324 ___________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD 54/74HC253
CD54/74HCT253
92CS-3BS31
INPUT LEVEL
SWITCHING VOLTAGE, Vs
Fig_ 2 - Transition and propagation delay times_
(OTHER {
INPUTS
tied
high
or low)
OUTPUT
DISABLE
IC WITH OUTPUT RL ·,k
{~ for I
and I
3-STATE t-+----">IV'v--D CC
PLZ
PZL
OUTPUT
CL
GND for tpHZ and tpZH
n
ISOPF
92CS-35130R2
Fig_ 3 - Three-state propagation delay test circuit.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 325
TechnicaIOata _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC257
CD54/74HCT257
File Number
1650
High-Speed CMOS Logic
2
110
5
21 0
11
31 0
4
1Y
14
41 0
111
211
31 1
411
2Y
3
9
6
12
3Y
4Y
10
13
15
Quad 2-lnput Multiplexer with
3-State Non-Inverting Outputs
Type Features:
• Buffered Inputs
• Typical Propagation Delay (In to Output) = 12 ns
@ Vee = 5v, C L = 15pF, r. = 25°C
S
OE
92CS-38419
FUNCTIONAL DIAGRAM
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity: N,L = 30%, N,H= 30% of Vee
@ Vee = 5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V'H = 2 V Min.
CMOS Input Compatibility
I, :S 1 fJA @ VOL, VOH
The RCA-CD54/74HC257 and CD54174HCT257 are quad 2input multiplexers which select four bits of data from two
sources under the control of a common Select input (S).
The Output Enable input (OE) is active LOW. When OE is
HIGH, all of the outputs (1Y-4Y) are in the high impedance
state regardless of all other input conditions.
Moving data from two groups of registers to four common
output busses is a common use of the 257. The state of the
Select input determines the particular register from which
the data comes. It can also be used as a function generator.
The CD54HC257 and CD54HCT257 are supplied in 16-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC257 and CD74HCT257 are supplied in 16-lead
dual-in-line plastic packages (E suffix) and in 16-lead dualin-line surface mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
OELr-------------q
s
1
FUNCTION TABLE
I
I
I
>--H112
1I=-o4Y
I
1
1
41 0
J
31 1
31 0
211
21 0
3Y
3 CIRCUITS IDENTICAL TO CIRCUIT
IN ABOVE DASHED ENCLOSURE
2Y
4
111
110
92C5-38421
LOGIC DIAGRAM
1Y
Output
Enable
Select
Input
.OE
S
H
X
L
L
L
L
L
H
L
H
H - High level voltage
L = Low level voltage
Z = High impedance (off) state.
X = Don't care
Data
Inputs
Output
10
11
Y
X
Z
L
H
X
X
X
X
X
L
H
L
H
L
H
326 _______________________________________________________________
___________________________________________________________ TechnicaIData
CD54/74HC257
CD54/74HCT257
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) .................................................................................. -0.5 to + 7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5V) ..................................................... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V) ................................................. ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V) .................................................. ±35mA
DC Vee OR GROUND CURRENT (lee) ................................................................................... ±70mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60°C (PACKAGE TYPE E) ........................................................................... 500 mW
For T. = +60 to +85°C (PACKAGE TYPE E) ............................................. Derate Linearly at 8 mW/oC to 300 mW
For T. = -55 to +100°C (PACKAGE TYPE F, H) ....................................................................... 500 mW
For T. = +100 to +125°C (PACKAGE TYPE F, H) ......................................... Derate Linearly at 8 mW;oC to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) ............................................................................ 400 mW
For TA = +70to +125°C (PACKAGE TYPE M) .............................................. Derate Linearly at 6 mW;oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .......................................................................................... -55 to +125°C
PACKAGE TYPE E, M.........................................................
. .......................... -40 to +85°C
STORAGE TEMPERATURE (T,,,) ................................................................................. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ...................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only .................................................................................. +300° C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operaling condilions should be selecled so Ihat operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vee:'
CD54174HC Types
CD54/74HCT Types
DC Input or Output Voltage V" Vo
Operating Temperature TA :
CD74 Types
CD54 Types
Input Rise and Fall Times t" t,
at 2 V
at 4.5 V
at6 V
UNITS
MIN,
MAX,
2
4.5
a
6
5.5
Vee
-40
-55
+85
+125
°C
a
a
a
1000
500
400
ns
V
V
'Unless otherwise specified, all voltages are referenced to Ground.
16
s
15
110
14
111
4
lY
13
12
21 0
11
211
10
2Y
GND
8
9
Vec
DE
41 0
411
4Y
31 0
31 1
3Y
92CS-3B420RI
TERMINAL ASSIGNMENT
_________________________________________________________________ 327
Technical Data
CD54/74HC257
CD54/74HCT257
STATIC ELECTRICAL CHARACTERISTICS
CD74HC257/CD54HC257
CD74HCT257/CD54HCT257
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
SERIES
SERIES
SERIES
CONDITIONS
SERIES
SERIES
SERIES
+25°C
-401
+85 Q C
-551
+125°C
-401
-551
+85°C
+125°C
CHARACTERISTIC
UNITS
Vo
10
V
mA
Vee
V
+25°C
Vo
V
Vee
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
Vo"
1.5
1.5
1.5
4.5
3.15
3.15
3.15
to
6
4.2
4.2
4.2
5.5
4.5
V"
0.5
0.5
0.5
4.5
1.35
1.35
to
6
High-Level
Output Voltage
VO"
or
-0.02
Vo"
1.8
1.8
1.8
1.9
1.9
V"
4.5
4.4
4.4
4.4
or
6
5.9
5.9
5.9
Vo"
3.84
3.7
V"
or
-6
4.5
3.98
(Bus Driver)
Vo"
-7.8
6
5.48
Output Voltage
5.34
V"
Voc
CMOS Loads
or
0.02
4.5
Vo"
or
5.2
(Bus Driver)
Vo"
0.1
0.1
V"
0.1
0.1
0.1
or
0.1
0.1
0.1
Vo"
4.5
0.26
0.33
0.4
7.8
0.26
0.33
0.4
Vo"
±1
±1
Any
Voltage
Between
Vee
&Gnd
80
160
Vee
Current
or
6
-
±D. 1
-
Gnd
Quiescent
Vee
Device
or
Current
Icc
4.5
4.4
4.5
3.98
4.4
4.4
V
-
-
3.84
-
3.7
V
4.5
0.1
0.1
0.1
V
or
-
-
0.4
V
4.5
-
0.26
5.5
-
±D.1
±1
±1
IJA
8
80
160
IJA
490
IJA
±10
IJA
0.33
or
5.5
Gnd
Gnd
4.5
Vcc-2.1
to
100 360
-
450
-
-
±5
-
5.5
3-State
V"
Vo = Vee
leakage
or
or
V o"
Gnd
loz
V
Vee
6
Additional
Quiescent
Device Current
per input pin:
1 unit load
Alec'
current
0.8
V"
or
Input Leakage
0.8
Vo"
0.1
V"
TTL Loads
0.8
V"
TTL Loads
Low-Level
V
5.5
1.9
V"
CMOS Loads
4.5
1.35
Low-level
Input Voltage
Min Typ Max Min Max Min Max
V"
6
-
±D.5
-
±5
±10
or
5.5
±D.5
Vo"
*For dual-supply systems theoreticsi worst case (V, = 2.4 V, Vee = 5.5 V) soecification is 1.8 mAo
HCT Input Loading Table
Input
Unit Loads·
Data
0.95
S
OE
0.6
3
"Unit Load IS .6.lcc limit specified In Static Characteristic Chart.
328 ______________________________________________________________
___
e.g., 360 IJA max. @ 25° C.
--------------------------_________________________________ TechnicaIData
CD54/74HC257
CD54/74HCT257
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25° C, Inpul I" I, = 6 ns)
Cl
(pF)
CHARACTERISTIC
nlO, n11' to Y
15
OEtoY
15
Sto Y
15
Power Dissipation Capacitance'
-
TYPICAL
HC
HCT
SYMBOL
t pHL
t pLH
t PZL
t PZH
tpLz
t pHZ
t pHL
t PLH
CPD
UNITS
12
13
ns
12
12
ns
14
16
ns
45
45
pF
CPD IS used to determine the dynamIc power consumptIon, per multIplexer.
PD=Vee' fi (C PD + Cd where f,=input frequency
CL = output load capacitance
Vee = supply voltage
SWITCHING CHARACTERISTICS (Cl = 50 pF, Inpul I" II = 6 ns)
CHARACTERISTIC
SYMBOL
Vce
Propagation Delay,
In to Y
(Fig. 2)
Propagation Delay
StoY
(Fig. 2)
t pLH
t pHL
2
4.5
6
2
4.5
6
Propagation Delay
OEto Y
(Fig. 3)
Output Transition
Time
(Fig. 2)
Input
Capacitance
3-State Output
Capacitance
t pLH
t pHL
t pLZ
tPZl
tPHZ
t PZH
25°C
-40°C 10 +85°C
-55°C 10 +125°C
54HC
54HCT
UNITS
HC
HCT
74HC
74HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
150 190 225 ns
33
50
30
41
45
38
33
38
26
175 220 265 57
35
44
48
53
ns
38
37
45
30
-
-
2
4.5
6
-
150
30
26
-
2
4.5
6
-
60
12
10
-
-
-
12
C,
-
10
Co
-
20
hLH
tTHL
-
225
45
38
-
45
-
-
-
18
-
90
18
15
-
-
10
-
10
-
10
pF
20
-
20
-
20
pF
-
190
38
33
-
-
-
38
-
-
-
75
15
13
-
-
-
15
-
-
-
-
-
10
-
10
-
-
20
-
20
-
-
30
-
ns
-
ns
INPUT
tf=6ns
.#'===1-,1------90% rLEVEL
====-~10%
LGND
y
OUTPUT
LOW TO OF'..;F-+...,.-_l"
OUTPUT
HIGH TO OFF
OUTPUTS _
CONNECTED
92CS-36422 RI
OUTPUTS
DISCONNECTED
OUTPUTS
CONNECTED
92CS-38423RI
I
I Input Level
I Switching Voltage, Vs
Fig. 2 - Inputs
or select to output propagation delays and output
54174HC
Vcc
50% Vcc
54/74HCT
3V
1.3 V
Fig. 3 - Output Enable
to output propagation delays.
_t_rn_n_s_i~_o_n_tl_·m_e_s_. _ _ _ _==================================_329
Technical
Data~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC258
CD54/74HCT258
File Number
1775
High-:-Speed CMOS Logic
110
21 0
11
310
'4
410
,I'
Quad 2-lnput Multiplexer with
3-State Inverting Outputs
21'
11,
31'
21,
31,
'0
41,
'3
'2
41'
GND=8
S
Vee
= 16
Type Features:
• Buffered inputs
• Typical CD54174HC258 propagation delay = 7 ns
@ Vee = 5 V, C L = 15pF, TA = 25°C
DE
92CS-39616
FUNCTIONAL DIAGRAM
The RCA-CD54/74HC258 and CD54/74HCT258 are quad 2input multiplexers which select four bits of data from two
sources under the control of a common Select input (S).
The Output Enable input (OE) is active LOW. When OE is
HIGH, all of the outputs (1Y-4Y) are in the high impedance
state regardless of all other input conditions.
Moving data from two groups of registers to four common
output busses is a common use of the 258. The state of the
Select input determines the particular register from which
the data comes. It can also be used as a function generator.
The CD54HC/HCT258 are supplied in 16-lead hermetic
dual-in-line ceramic packages (F suffix). The CD74HCI
HCT258 are supplied in 16-lead dual-in-line plastic packages (E suffix) and in 16-lead dual-in-line surface mount
plastic packages (M suffix). Both types are also available in
chip form (H suffix).
-"
0'00'
,o--C><>---.--+- S
lTO
OTHER 3
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCTIHCU: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
N'L = 30%, N'H = 30% of Vee; @ Vee = 5V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, S 1 iJA @ Val., VOH
OE
IDENTICAL CKTS.
"
0' ) TO OTHER 3
;»-r--+-- 5 IDENTICAL CKTS
'cc
...,
I
I
I
I
I
'cc
t
;4Y'-
"
"00--+---1
N
~
I
IL _________________
•
I
I
I
",
I
I
I
I
~
3 CIRCUITS IDENTICAL TO
CIRCUIT IN ASOVE CASHED
ENCLOSURE
'"
"OU----L_ _ _ _ _ _ _ _ _ _ _ _ _----'
3 CIRCUITS IDENTICAL TO
CIRCUIT IN ABOVE DASHED
ENCLOSURE
92CM-39820
CD54174HC258 Logic Diagram
CD54174HCT258 Logic Diagram
330 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
- - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC258
CD54/74HCT258
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ................................................................................... -0.5 to + 7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5V) ...................................................... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V) ................................................... ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V) ................................................... ±35mA
DC Vee OR GROUND CURRENT (Icc) ................................................................................... ±70mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60° C (PACKAGE TYPE E) ......•...................................................................... 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) ................................................ Derate Linearly at 8 mW/oC to 300 mW
For TA = -55 to +100°C (PACKAGE TYPE F, H) ......................................................................... 500 mW
For TA = +100 to +125°C (PACKAGE TYPE F, H) .•......................................... Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) ...............................................•.............•.........•.... 400 mW
For TA = +70 to +125°C (PACKAGE TYPE M) ........•.....•................•............... Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .•......•..•.............................................................................. -55 to +125°C
PACKAGE TYPE E, M ........................................................................................... -40 to +85°C
STORAGE TEMPERATURE (T".) .................................................................................. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max....................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................................................................................... +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
MIN,
UNITS
MAX,
Supply-Voltage Range (ForTA - Full Package-Temperature Range) Vcc:'
CD54/74HC Types
CD54/74HCT Types
2
6
4.5
5.5
DC Input or Output Voltage V" Vo
0
Vee
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t" tf
at2V
V
-40
+85
-55
+125
0
1000
at4.5V
0
at6V
0
500
400
V
°C
ns
'Unless otherwise specified, all voltages are referenced to Ground.
FUNCTION TABLE
Output
Enable
Select
Input
OE
H
S
L
L
L
L
X
L
L
H
H
Data
Inputs
10
X
L
H
X
X
H =High level voltage
L = Low level voltage
X = Don't care.
Z = High impedance (off) state
11
X
X
X
L
H
Output
2
15
111
3
14
1Y
4
13
110
Y
Z
H
L
H
L
16
s
21 0
211
2Y
GND
5
12
6
11
7
10
B
9
Vee
DE
410
411
4Y
31 0
31 1
3Y
,2CS-39815
TERMINAL ASSIGNMENT
331
TechnicaIOala _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC258
CD54/74HCT258
STATIC ELECTRICAL CHARACTERISTICS
CD74HC258/CD54HC258
CD74HCT258/CD54HCT258
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPE
TYPE
CONDITIONS
TYPES
TYPE
TYPE
-401
-551
+125°C
+25°C
-551
+85°C
-401
+85°C
CHARACTERISTIC
UNITS
+25°C
V,
10
V
rnA
Vee
V
V,
V
Vee
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
V'H
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
VOH
CMOS Loads
or
-0.02
V'H
2
1.5
-
-
1.5
-
1.5
-
4.5
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
Min Typ Max Min Max Min Max
4.5
-
(Bus Driver)
Low-Level
Output Voltage
-6
V'H
-7.8
CMOS Loads
or
0.02
V'H
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
(Bus Driver)
Input Leakage
Current
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
6
V'H
7.8
or
Current
Icc
6
5.9
-
-
5.9
-
5.9
4.5
3.98
-
-
3.84
-
3.7
-
or
6
5.48
-
-
5.2
-
V'H
0.1
V"
0.1
or
V'H
or
5.34
-
2
-
-
0.1
-
0.1
4.5
-
-
0.1
-
0.1
-
6
-
-
0.1
-
0.1
-
0.1
4.5
-
-
0.26
-
0.33
-
0.4
6
-
-
0.26
-
0.33
-
0.4
6
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
to
4.5
-
-
0.1
-
0.1
-
0.1
V
or
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±O.1
-
±1
-
±1
pA
5.5
-
-
8
-
80
-
160
pA
-
100 360
-
450
-
490
pA
-
±5
-
±10
pA
V'H
-
-
±O.1
-
±1
-
Between
±1
Vee
& Grid
Vee
0
6
-
-
8
-
80
-
160
Gnd
or
Gnd
4.5
Vcc-2.1
to
5.5
3-State
V"
Vo = Vee
leakage
or
or
V'H
Gnd
10'
V
V'H
Additional
Quiescent
Device Current
per input pin:
1 unit load
6. l cc*
current
-
Any
Voltage
or
Vee
2
5.5
Gnd
Device
-
V"
or
Quiescent
2
V"
Vee
I,
-
4.5
-
V"
TTL Loads
-
V"
or
V"
Yo,
2
to
5.5
V"
TTL Loads
+125°C
V"
6
-
-
±O.5
-
±5
-
±10
or
5.5
-
-
±O.5
V'H
*For dual-supply systems theoretical worst case (VI = 2.4 V. Vee = 5.5 V) specification
IS
1.8 rnA.
HCT Input Loading Table
Input
Unit Loads'
Data
0.5
1.5
1.5
S
6E
332
..
'Unit Load is blcc limit specified In Static Charactenstlc
Chart, e.g., 360l1A max. @ 25 0 C.
----------------------------------
___________________________________________________________ TechnicaIData
CD54/74HC258
CD54/74HCT258
SWITCHING CHARACTERISTICS (Vee = 5 V, T A = 25° C, Input t" t, = 6 ns)
TYPICAL
HC
HCT
CL
(pF)
CHARACTERISTIC
nl o' ni" to V
t pHL t plH
15
7
UNITS
11
ns
t pZl t pZH
15
11
11
ns
t pLZ t pHZ
15
12
12
ns
t pHL t pLH
15
11
14
ns
-
49
49
pF
OEtoY
StoY
Power Dissipation Capacitance'
Cpo
'Cpo is u~ed to determine the dynamic power consumption, per multiplexer.
PD = Vee fi (CpD + C l ) where: fi = input frequency
C l = output load capacitance
Vee = supply voltage
SWITCHING CHARACTERISTICS (C l = 50 pF, Input t" I, = 6 ns)
CHARACTERISTIC
Propagation Delay,
nlo, ni" to Y
(Fig. 2)
Propagation Delay
StoY
(Fig. 3)
Propagation Delay
OEtoY
(Fig. 4)
Propagation Delay
OEtoY
(Fig.4)
Output Transition
Time
(Fig.2)
Input
Capacitance
3-State Outpul
Capacitance
Vee
t pLH
t pHL
t plH
t pHL
t PZL
t PZH
t pLZ
tPHZ
hLH
hHL
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
_40° C to +85° C
25°C
-55° C to +125° C
HC
HCT
74HC
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
95
120 145 34
41
19
27
24
29
ns
15
20
25
140 175 210 28
34
35
43
42
51
ns
24
30
36
140 175 210 28
28
35
35
42
42
ns
24
30
36
150 190 225 30
38
45
ns
30
38
45
26
33
38
75
60
90
12
12
15
15
18
18
ns
10
13
15
-
C,
-
10
-
10
-
10
-
10
-
10
-
10
pF
Co
-
20
-
20
-
20
-
20
-
20
-
20
pF
_________________________________________________________________ 333
TeohnicaIOata _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC258
CD54n4HCT258
l rtr=6n&
1 £11=6n&
_jf---------]---90%
---Vs
OE
-----------
--~O%
OUTPUT
LOW TO O;;.;F..;.F+_ _"i
HIC~W~~U6FF
92CS-39818
OUTPUTS
CONNECTED
1~-90%
--I-
---VS
OUTPUTS
DISCONNECTED
:::.L-
OUTPUTS
CONNECTED
92CS-3981T
Fig. 2 - Select to output delays.
Fig. 4 - Output Enable to output propagation delays.
I
I Input Level
I SwitchinQ VoltaQe. Vs
54174HC
Vee
50% Vee
54174HCT
3V
1.3V
I
I
I
Fig. 3 - Select to output propagation delays.
334 ___________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC259
CD54/74HCT259
File Number 1727
High-Speed CMOS Logic
8-Bit Addressable Latch
"
" '
I-or-s
,
DECODER
LATCHES
"
LE
1<1
.-.--=t------ Vee +0.5 V) ....................................................... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Va < -0.5 V OR Va> Vee +0.5 V) ................................................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (1 0 ) (FOR -0.5 V < Va < Vee+0.5 V) ..................................................... ±25 mA
DC Vee OR GROUND CURRENT (lee) ...................................................................................... ±50'mA
POWER DISSIPATION PER PACKAGE (Po):
ForTA = -40 to +60°C (PACKAGE TYPE E) ............................................................................... 500 mW
For TA = +60 to +85 0 C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/oC to 300 mW
For TA = -55 to +1000 C (PACKAGE TYPE F, H) ........................................................................... 500 mW
For TA = +100 to +125°C (PACKAGE TYPE F, H) ............................................. Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +70'C (PACKAGE TYPE M) ............................................................................. 400 mW
For TA = +70 to +125'C (PACKAGE TYPE M) ................................................ Derate Linearly at 6 mW/'C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H ............................................................................................. -55 to +125 0 C
PACKAGE TYPE E, M .............................................................................................. -40 to +85' C
STORAGE TEMPERATURE (Tot.) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 1 0 s max.
. ................ , ..................................... 265 0 C
Unit inserted into a PC board (min. thickness 1/16 in., 1.59 mm) with solder contacting lead tips only .......................... 300'C
o
LE
AD
ao
ao-':=~===t:=~
al -T
aD
AI
or
al
A2
Q2
a2
)
a2~++~----~--.
)
iiO
al
a2
I
I
I
aD
;;0
aT
iii
a2
a2
aD
al
02
llflQI
CiT
02
Q2
iiO
aT
aD
I a2
I
I
QO
;;0
al
Q2
Q3
I
_¥,J
Q4
-f.l~ l
Q5
Q6
QT
9ZCM-39254
Fig. 1 - Logic diagram.
336 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC259
CD54/74HCT259
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within the
following ranges:
LIMITS
UNITS
CHARACTERISTIC
MIN.
MAX.
Supply Voltage Range (For TA = Full Package Temperature Range) Vee:
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage V" Va
2
6
V
4.5
5.5
V
0
Vee
V
Operating Temperature TA:
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
Input Rise and Fall Times, t" tf
at 2 V
0
1000
ns
at 4.5 V
0
500
ns
at 6 V
0
400
ns
• Unless otherwise specified, all voltages are referenced to Ground.
TRUTH TABLE
LATCH SELECTION TABLE
INPUTS
Select Inputs
MR
LE
Output of
Address Latch
H
L
D
H
H
aio
L
L
D
L
H
L
Each Other
Output
Function
OiO
Addressable
Latch
a
io
L
L
Memory
8-Line
Demultiplexer
Reset
A2
Al
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
AD
L
H
Latch
Addressed
0
1
L
2
H
3
L
4
5
6
7
H
L
H
H = High level
L = Low level
D = The level at the data input
0'0 = The level of A, (i = 0, 1... 7, as appropriate) before
the indicated steady-state input conditions were
established.
_____________________________________________________________ 337
Technical Data ___________________________________________________________
CD54/74HC259
CD54/74HCT259
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT2S9, CDS4HCT259
CD74HC2S9, CDS4HC2S9
TEST
74HC/S4HC
74HC
S4HC
TEST
74HCT/S4HCT
74HCT
S4HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-5SI
-401
-SSI
+85°C
+12SoC
+8SoC
+12SoC
UNITS
CHARACTERISTIC
+25°C
V,
10
Vee
V
mA
V
High-Level
I nput Voltage
V,"
Low-Level
I nput Voltage
VOL
High-Level
Output Voltage
VOL
Vo"
CMOS Loads
or
-0.02
V,"
2
1.5
3.15
6
4.2
2
-
4.5
-
-
-
1.5
-
1.5
-
3.15
-
3.15
-
4.2
-
4.2
-
-
0.5
-
0.5
1.35
1.35
-
1.35
1.8
-
1.8
-
1.8
0.5
Low-Level
Output Voltage
CMOS Loads
-
-
2
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
JlA
5.5
-
-
8
-
80
-
160
JlA
-
100 360
-
450
-
490
JlA
4.5
-
to
5.5
-
1.9
-
-
4.4
-
1.9
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
-
3.84
-
3.7
-
or
5.34
-
5.2
-
V,"
0.1
-
0.1
VOL
-
0.1
0.1
-
0.1
-
0.1
0.1
0.33
-
0.4
or
0.33
-
0.4
V,"
±1
-
±1
VOL
VOL
3.98
V,"
-5.2
6
5.48
2
0.02
4.5
6
-
-
0.1
or
0.1
V,"
VOL
or
4
4.5
-
-
0.26
V,"
5.2
6
-
-
0.26
-
6
-
-
±0.1
-
Any
I nput Leakage
Vee
10
or
Gnd
Quiescent
Device Current
2
to
5.5
-
VOL
Current
lee
or
Voltage
Between
Vee & Gnd
Vee
Vee
0
6
-
-
8
-
80
-
or
160
Gnd
Gnd
Additional
4.5
Quiescent Device
Vee -2.1
Current per input
pin: 1 unit load
Min Typ Max Min Max Min Max
4.5
-
1.9
4.5
V,"
TTL Loads
V
4.4
-4
or
V
2
or
VOL
Vo,
Vee
4.5
VOL
TTL Loads
V,
Min Typ Max Min Max Min Max
4.5
6
+25°C
to
5.5
.6.lcc
*For dual-supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specifi9ation is 1.8 rnA.
HCT Input Loading Table
Input
Unit Loads *
AO-A2, LE
1.5
D
1.2
MR
0.75
• Unit Load is Alee limit specified in Static Characteristic
Chart, e.g., 360 IlA max. @ 25 0 C.
338 ________________________
~
__________________
~
__________________
,______________________________ Technical Data
CD54/74HC259
CD54/74HCT259
SWITCHING CHARACTERISTICS (Vee=5 V, T A=25°C, Inpul I" 1,=6 ns)
TYPICAL
CL
CHARACTERISTIC
Propagation Delay
DtoO
(pF)
HC
HCT
UNITS
15
ns
tPLH
15
16
LE to 0
14
16
ns
A to 0
15
17
ns
tPHL
MR to 0
Power Dissipation Capacitance'
Cpo
15
13
16
ns
-
21
22
pF
• Cpo is used to determine the dynamic power consumption, per package,
Po = CpoVee 2f,+ L CLVee2fo
where f, = input frequency, fo = output frequency,
CL = output load capacitance, Vee = supply voltage.
PRE-REQUISITE FOR SWITCHING FUNCTION
LIMITS
CHARACTERISTIC
TEST
CONDITION
Pulse Width
tWL
IT
MR
tWL
Set-up Time
o to
-
tsu
LE
AtoIE
Hold Time
--
tsu
tH
o to LE
A toLE
tH
-55°C 10 +125°C
UNITS
HC
Vee
V
_40° C to +85° C
25°C
HCT
74HC
74HCT
54HC
54HCT
Min Max Min Max Min Max Min Max Min Max Min Max
2
70
-
-
-
90
-
-
-
105
-
-
4.5
14
-
18
-
18
-
23
-
21
-
27
-
6
12
-
-
-
15
-
-
-
18
-
-
-
2
70
-
-
-
90
-
-
-
105
-
-
-
4,5
14
-
18
-
18
-
23
-
21
-
27
-
6
12
-
-
-
15
-
-
-
18
-
-
-
2
80
-
-
-
100
-
-
-
120
-
-
-
4,5
16
-
17
-
20
-
21
-
24
-
26
-
6
14
-
-
-
17
-
-
-
20
-
-
-
2
80
-
-
-
100
-
-
-
120
-
-
-
4,5
16
-
17
-
20
-
21
-
24
-
26
-
6
14
-
-
-
17
-
-
-
20
-
-
-
2
0
-
-
-
0
-
-
-
0
-
-
-
4.5
0
-
0
-
0
-
0
-
0
-
0
-
6
0
-
-
-
0
-
-
-
0
-
-
-
2
0
-
-
-
0
-
-
-
0
-
-
-
4,5
0
-
0
-
0
-
0
-
0
-
0
-
6
0
-
-
-
0
-
-
-
0
-
-
-
-
ns
ns
ns
ns
ns
ns
________________________________________________________________ 339
Technical Data ___________________________________________________________
CD54/74HC259
CD54/74HCT259
SWITCHING CHARACTERISTICS (Cl
=50 pF, Input t" t, =6 ns)
LIMITS
CHARACTERISTIC
TEST
CONDITION
UNITS
HC
Vee
V
Propagation
Delay
tPHL
AtoQ
MR to Q
Output
trHL
54HC
-
-
-
46
-
54HCT
280
-
-
56
-
49
-
-
39
-
59
-
-
215
-
-
-
48
-
-
-
255
-
38
-
43
-
-
48
-
51
-
57
-
-
-
37
-
-
-
43
-
-
185
-
-
-
230
-
-
-
280
-
-
37
-
41
31
-
-
-
46
-
51
-
56
-
61
-
39
-
-
-
48
-
-
-
-
39
-
31
-
-
170
-
-
34
-
-
29
2
-
4.5
-
6
-
4.5
-
6
-
2
-
4.5
-
6
185
-
37
2
-
155
-
-
-
195
-
-
-
235
-
-
4.5
-
31
-
39
-
39
-
49
-
47
-
59
6
-
26
-
-
-
33
-
-
-
40
-
-
2
-
75
-
-
-
95
-
-
-
110
-
-
4.5
-
15
-
15
-
19
-
19
-
22
-
22
6
-
13
-
-
-
16
-
-
-
19
-
-
-
10
-
10
-
10
-
10
-
10
-
10
hLH
Transition
74HCT
230
-
-
D to Q
LE to Q
74HC
HCT
Min Max Min Max Min Max Min Max Min Max Min Max
2
tPlH
_55° C to +125° C
-40° C to +85° C
25°C
Time
ns
ns
ns
ns
ns
C,
Input
Capacitance
Dn~
on
pF
k;-
Vs
Y:;f.
Vs
Vs
PROPAGATION DELAY
DATA TO OUTPUT
LATCH ENABLE PULSE WIDTH AND
LATCH ENABLE TO OUTPUT PROPAGATION DELAY
'"~"
~
~I--jtPLHt;=
Qn
~Vs
PROPAGATION DELAY
A DDRESS TO OUTPUT
Input Level
Switching Voltage, Vs
54/74HC
54174HCT
Vee
3V
50% Vee
1.3 V
92CM-39256RI
Fig. 2 - AC Waveforms.
340 ______________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC259
CD54/74HCT259
,~_R---~-V~:P~"~~-VS--VS---
o
LE ___.....JI
DATA SETUP AND HOLD TIMES
iiii TO OUTPUT DELAY
AND ~ PULSE WIDTH
54174HC
Input Level
Switching Voltage, Vs
54/74HCT
Vee
3V
50% Vee
1.3 V
ADDRESS SETUP AND
HOLD TIMES
92CM-39259RI
Fig. 3 - AC Waveforms.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 341
TechnicaIDma _________________________________________________________
CD54/74HC273
CD54/74HCT273
File Number 1479
High-Speed CMOS Logic
Octal 0 Flip-Flop with Reset
CLOCK
CP
DATA
INPUTS
00
00
0'
02
0'
02
03
03
D.
04
05
05
06
06
07
07
RESET VR
Type Features:
DATA
OUTPUTS
•
•
•
•
Common clock and asynchronous master reset
Positive-edge triggering
Buffered inputs
Typical f m., = 60 MHz @ Vee = 5 V, C L = 15pF, TA = 25° C
92CS-36976R2
FUNCTIONAL DIAGRAM
The RCA CD54/74HC273 and the CD54174HCT273 high
speed Octal D-Type Flip-Flops with a direct clear input are
manufactured with silicon-gate CMOS technology. They
possess the low power consumption of standard CMOS
integrated circuits.
Family Features:
•
•
Information at the D input is transferred to the Q outputs on the
positive-going edge of the clock pulse. All eight Flip-Flops are
controlled by a common clock (CP) and a common reset (MR).
Resetting is accomplished by a low voltage level independent
of the clock. All eight Q outputs are reset to a logic o.
•
•
•
•
The CD54HC273 and CD54HCT273 are supplied in 20-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC273 and CD74HCT273 are supplied in 20-lead
dual-in-line plastic packages (E suffix) and in 20-lead
dual-in-line surface mount plastic packages (M suffix).
Both types are also available in chip form (H suffix).
•
00
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
Alternate Source is Philips/Signetics
CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity: ML = 30%, MH= 30% of Vee
@ Vee = 5 V
CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'L = 0.8 V Max., V'H = 2 V Min.
CMOS Input Compatibility
I, :::; 1 /JA @ VOL.. VO H
0'
Fig. 1 - Logic diagram.
342 __________________________________
~
_____________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC273
CD54/74HCT273
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ........................................ , ............................................. -0.5 to +7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5 V ........................................................ ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V .................................................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) ..................................................... ±25 mA
DC Vee OR GROUND CURRENT, PER PIN (Icc): ............................................................................ ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60° C (PACKAGE TYPE E) ................................................................................ 500 mW
For TA = +60 to +85° C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW;o C to 300 mW
For TA = -55 to +100° C (PACKAGE TYPE F, H) ............................................................................ 500 mW
For TA = +100 to +125°C (PACKAGE TYPE F, H) .............................................. Der&te Linearly at 8 mW/oC to 300 mW
For T. = -40 to +70° C (PACKAGE TYPE M) .............................................................................. 400 mW
For T. = +70 to +125°C (PACKAGE TYPE M) ................................................. Derate Linearly at6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H ............................................................................................. -55 to +125°C
PACKAGE TYPE E, M .............................................................................................. -40 to +85°C
STORAGE TEMPERATURE (T",) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ........................................................ +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ..................................................................................... +300° C
TRUTH TABLE' (EACH FLIP-FLOP)
RESET
(MR)
INPUTS
CLOCK
CP
OUTPUT
DATA
On
Q
L
X
X
L
H
-'
H
H
H
-'
L
L
H
L
X
00
H = High Level (Steady State)
L = Low Level (Steady State)
X = Irrelevant
---'= Transition from Low to High Level
00 = The Level of 0 Before the Indicated Steady-State
Input Conditions were Established
Fig. 2 - Flip-Flop detail.
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within the
following ranges:
LIMITS
UNITS
CHARACTERISTIC
MIN.
MAX.
Supply Voltage Range (For TA = Full Package Temperature Range) Vee:"
CD54174HC Types
2
6
V
CD54/74HCT Types
4.5
5.5
V
0
Vee
V
DC Input or Output Voltage VI, Vo
Operating Temperature TA:
CD74 Types
-40
+85
°c
CD54 Types
-55
+125
°C
Input Rise and Fall Times, tr, tf
at 2 V
0
1000
ns
at 4.5 V
0
500
ns
at 6 V
0
400
ns
_ _ _ otherwise
_____
____
____
_____
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 343
'Unless
specified,
all_
voltages
are_referenced
to _
Ground.
TechnicaIOala _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC273
CD 54/74H CT273
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT273/CD54HCT273
CD74HC273/CD54HC273
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85'C
+125'C
+85°C
+125'C
UNITS
CHARACTERISTIC
+25°C
V,
10
Vee
V
mA
V
+25°C
V,
Vee
V
V
. Min Typ Max Min Max Min Max
High-Level
2
I nput Voltage
6
Low-level
Input Voltage
V"
High-Level
V"
Output Voltage
Vo"
CMOS Loads
1.5
4.5 3.15
V,"
or
-0.02
V,"
4.2
.-
-
1.5
-
1.5
-
-
-
3.15
-
3.15
-
-
-
4.2
-
4.2
-
-
0.5
-
or
V,"
Low-Level
VOL
CMOS Loads
or
-5.2
0.02
V,"
2
-
-
0.5
-
-
1.35 -
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
VJH
-
-
3.84
-
3.7
-
or
V,"
V"
1.35 -
0.5
1.35
4.5 3.98
to'
5.5
5.48
-
-
5.34
-
5.2
2
-
-
0.1
-
0.1
-
0.1
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
4
4.5
-
-
0.26
-
0.33
-
0.4
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
Input Leakage
Vee
2
_.
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
3.7
-
V
0.1
-
0.1
-
0.1
V
4.5 3.98
4.5
-
-
4.5
-
-'
0.26
-
0.33
-
0.4
V
V,"
Any
Voltage
between
5.5
Vee
6
-
-
±0.1
-
±1
-
±1
or
-
-
±0.1
-
±1
-
±1
JJA
-
-
8
-
80
-
160
pA
-
100 360
-
450
-
490
iJA
or
&
Gnd
Gnd
Quiescent
Vee
Vee
Device
or
0
6
-
-
8
-
80
-
160
or
5.5
Gnd
Gnd
4.5
Vee -2.1
to
5.5
-For dual-supply systems theoretical worst case (V. = 2.4 V, Vee
HCT INPUT LOADING TABLE
INPUT
-
V"
or
Current
Icc
Additional
Quiescent
Device Current
per input pin:
dlcc·
1 unit load
-
V"
6
V"
I,
2
4.5
-
-
TTL Loads
Current
to
5.5
V"
-4
V"
Output Voltage
4.5
-
4.5
V"
TTL Loads
Min Typ Max Min Max Min Max
UNIT LOADS#
=5.5 V) specification is 1.8 rnA.
MR...!.~~VCC
co..!
t!!!. 07
t!!!. 07
00.1.
01 ~
fl!. 06
01.1.
~06
i1i 05
02.2
fli 05
Data
f!1 04
03 ~
CP
f1L 04
03.2
'Unit Load is l>lcc limit specified in Static Characteristics
Ill- cp
GNO .!Q
Chart, e.g.,.360 JlA-max. @ 25°C.
92CS·36834
344 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_
_
_
_
_
_ _ _ _ _ ___
TERMINAL ASSIGNMENT
MR
1.5
0.4
1.5
02
~
______________________________ Technical Data
CD 54/74H C273
CD54/74HCT273
PRE-REQUISITE FOR SWITCHING FUNCTION
LIMITS
TEST
CONDITION
CHARACTERISTIC
Maximum Clock
Frequency
fmax
Fig.3
MR Pulse Width
tw
Fig.4
Clock Pulse Width
tw
Fig. 3
Set-up Time
Data to Clock
Fig. 5
54HC
54HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
2
6
-
5
-
4
-
4.5
30
25
25
20
20
16
6
35
-
29
-
23
2
60
-
75
-
90
-
4.5
12
12
15
15
18
18
6
10
-
13
-
-
2
80
-
100
-
15
120
4.5
16
20
20
25
24
30
6
14
-
17
-
20
-
2
60'
12
-
75
-
70
-
4.5
12
15
15
18
18
6
10
-
13
15
-
2
3
-
3
3
3
3
3
3
3
tH
6
3
-
3
3
-
2
50
-
65
-
75
-
tREM
4.5
10
10
13
13
15
15
6
9
-
11
-
13
-
Removal Time
MHz
ns
-
4.5
Data to Clock
MR to Clock
74HCT
74HC
-
tsu
Hold Time
Fig. 5
-55°C 10 +125°C
UNITS
HCT
HC
VCC
V
_40° C 10 +85° C
25°C
3
ns
ns
ns
ns
SWITCHING CHARACTERISTICS (Vee =5 V, T A =25° C, Inpul I. II =6 ns)
CL
pF
CHARACTERISTIC
TYPICAL
HC
HCT
UNITS
Propagation Delay,
Clock to Q
t pLH
tpHL
15
12
12
ns
Maximum Clock Frequency
Power Dissipation Capacitance'
1m..
15
Cpo
-
60
25
50
25
MHz
pF
'Cpo is used to determine the dynamic power consumptIon, per flip-flop.
Po = CpoVee2 fi+ 1: C L Vee2fo where fi = input frequency. fo = output frequency,
C L = output load capacitance, Vee = supply voltage.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 345
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC273
CD54/74HCT273
SWITCHING CHARACTERISTICS (CL = 50 pF, Inpull., If = 6 ns)
LIMITS
TEST
CONDITION
CHARACTERISTIC
_55° C to +125° C
UNITS
HCT
HC
VCC
V
-40° C to +85° C
25°C
74HCT
74HC
54HC
54HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay
tpLH
2
150
-
190
-
225
-
Clock to Output
tpHL
4.5
30
30
38
38
45
45
6
26
-
30
-
38
-
2
150
-
190
-
225
-
4.5
30
32
38
40
45
48
6
26
-
33
-
38
-
hlH
2
75
-
95
-
110
-
hHL
4.5
15
15
19
19
22
22
6
13
10
-
16
10
-
19
10
-
Fig.3
Propagation Delay
MR to Output
tPHL
Fig.4
Output Transition
Time
Fig.6
Input Capacitance
-
C;
10
10
10
ns
ns
ns
pF
INPUT
LEVEL
INPUT
LEVEL
_----JI
Fig. 3 - Clock to output delays and clock pulse width.
Fig. 4 - Master reset pulse width. Master reset to output delay and
master reset to clock recovery time.
INPUT
LEVEL
Vee - - --1--;:,90"',::-,---,1
'5U tH ' -
90%
~---
92CS- 36954RI
92CS-3BOB!i
54 74HC
Inpullevel
s
Vee
54/74HCT
3
v
CC
Fig. 5 - Data set-up and hold times.
Fig. 6 - Transition times.
346 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
File Number
CD54/74HC280
CD 54/74HCT280
1669
High-Speed CMOS Logic
FUNCTIONAL DIAGRAM
10
II
12
8
9
10
]]
I3
14
15
12
I
EVEN
:E
ODD
13
16
17
18
4
NC-3
Vcc -14
GND· 7
92CS-38411
9-Bit Odd/Even Parity
Generator/Checker
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85°C
• Balanced Propagation and
Transition Times
• Typical propagation delay = 17ns
• Significant Power Reduction Compared to
@ Vee = 5 V, CL= 15pF, TA= 25°C
LSTTL Logic ICs
• Replaces 74LS180 types
• Alternate Source is Philips/Signetics
• Easily cascadable
• CD54HC/CD74HC Types:
Family Features:
2 to 6 V Operation
• Fanout (Over Temperature Range):
High Noise Immunity: NIL cc 30%, Vee.
Standard Outputs - 10 LSTTL Loads
N,H = 30% of Vee: @ Vee = 5 V
Bus Driver Outputs - 15 LS,,TTL Loads
Type Features:
The RCA-CD54/74HC280 and CD54/74HCT280 are 9-bit
odd/even parity, generator checker devices. Both even and
odd parity outputs are available for checking or generating
parity forwards up to nine bits long. Even parity is indicated
(IE output is high) when an even number of data Inputs IS
high. Odd parity is indicated (IO output is high) when an
odd number of data inputs is high. Parity checking for
words larger than 9 bits can be accomplished by tying the
IE output to any input of an additional HC/HCT280 parity
checker.
The CD54HC280 and CD54HCT280 are supplied in 14-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC280 and CD74HCT280 are supplied in 14-lead
dual-in-line plastic packages (E suffix) and in 14-lead dualin-line surface mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
I
I
I
I
L ________________
Fig. 1 -
I
I
.J
~o
92CL-3B368RI
Logic Diagram
_________________________________________________________ 347
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC280
CD54/74HCT280
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ............................ , . , . , " " " " ' , .......................... , ... , ... , .. , -0.5 to + 7 V
±20mA
DC INPUT DIODE CURRENT, I,. (FOR V, < -0.5 V OR V, ',Vee +0.5V)
,,20mA
DC OUTPUT DIODE CURRENT, 10. (FOR V, < -0.5 V OR V, > Vee +0.5V) .,""",.,.
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < V,
< Vee + O.SV)
For TA
For TA
For TA
0
0
0
±2SmA
±50mA
............. , " " " , ......... .
DC Vee OR GROUND CURRENT (Icc) ............. .
POWER DISSIPATION PER PACKAGE (Po):
For TAo -40 to +60' C (PACKAGE TYPE E) """",.,....
. .. , , , , , , , , , , , , , ................................ SOD mW
+60 to +8S'C (PACKAGE TYPE E) .......
..,', .... " .. ,', .......... ,""" Derate Linearly at 8 mW/oC to 300 mW
-55 to +100'C (PACKAGE TYPE F, H)
., .................. , " " " " " , . , ............................ SOO mW
+100 to +12SoC (PACKAGE TYPE F, H) ............. , .... " .... ,', ............. ,' Derate Linearly at 8 mWI'C to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) •...........••..•......••.....•••••......•...•...•..•.•.••...•••••••..•••. 400 mW
ForTA = +70 to +125°C (PACKAGE TYPE M) ....•.....••..•••......•......•.••.••........ Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H
......................................................................... . -SS to +12SoC
-40 to +85°C
PACKAGE TYPE E, M
-65 to +150'C
STORAG'E TEMPERATURE (T",) ................... ,.,"',.,",.
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16:!: 1/32 in. (1.59:!: 0.79 mm) from case for 10 s max . . . ,',.,',." ......... " . " . , " " , .. "., ..... .
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ... , ............. , , , ... , , , , , , , .......... , , , , , , , , , , , .............. , , , , , , . , ..
+265'C
+300'C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA - Full Package-Temperature Range) Vee:·
CD54n4HC Types
CD54n4HCT Types
DC Input or Output Voltage V'N, VOUT
Operating Temperature TA :
CD74 Types
CD54 Types
Input Rise and Fall Times t" t,
at2V
at4.5V
at6V
LIMITS
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
-40
-55
+85
+125
·C
0
0
0
1000
500
400
ns
V
V
·Unless otherwise specified, all voltages are referenced to Ground.
348 ________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD 54/74HC280
CD 54/74HCT280
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT280/CD54HCT280
CD74HC280/CD54HC280
TEST
CONDITIONS
74HC/54HC
SERIES
74HC
SERIES
54HC
SERIES
-401
-551
+85°C
+125°C
TEST
CONDITIONS
74HCT/54HCT
SERIES
74HCT
SERIES
54HCT
SERIES
-401
-551
+85°C
+125°C
UNITS
CHARACTERISTIC
+25°C
V,
V
10
mA
V"'
1.5
-
-
1.5
-
1.5
-
4.5 3.15
-
-
3.15
-
3.15
-
4.2
-
-
4.2
-
4.2
-
6
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
VO "
CMOS Loads
or
V,
V
-0.02
V,"
Min Typ Max Min Max Min Max
4.5
-
Low-Level
Output Voltage
-4
V".
-5.2
CMOS Loads
or
0.02
V,"
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
Input Leakage
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
19
-
V"
4.4
-
-
4.4
-
4.4
or
6
5.9
-
-
5.9
-
5.9
-
4.5 3.98
-
-
3.84
-
3.7
-
or
6
5.48
-
-
5.34
-
5.2
-
V,"
2
-
-
0.1
-
0.1
-
0.1
V"
4.5
-
-
01
-
01
-
0.1
or
6
-
-
0.1
-
0.1
-
01
V,"
4.5
-
-
0.26
-
0.33
-
0.4
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
6
-
-
,0 I
-
,I
-
±1
Any
Voltage
Between
or
or
Current
Icc
2
-
V
to
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
3.7
-
V
4.5 3.98
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
!D.l
-
±1
-
,I
/JA
5.5
-
-
8
-
80
-
160
/J A
-
100 360
-
450
-
490
/JA
Vee
& Gnd
Gnd
Vee
-
V"
4
Quiescent
2
V,"
or
Device
-
5.5
4.5
Vr.r
I,
Current
-
4.5
-
V"
TTL Loads
2
V"
or
v."
Vm
to
5.5
V"
TTL Loads
Vee
V
Min Typ Max Min Max Min Max
2
High-Level
Input Voltage
Vee
V
+25°C
Vee
0
6
-
-
8
-
80
-
160
or
Gnd
Gnd
4.5
Additional
Quiescent
Device Current
per input pin:
Alec
1 unit load
Vcc-2.1
to
5.5
'For dual-supply systemstheorellcal worst case (V, = 2.4 V, Vee = S.S VI specification is 1.B mAo
HCT Input Loading Table
Input
Unit Loads·
ALL
'Unit Load is Ll.lcc limit specified in Static Characteristic
Chart, e.g., 360 tJA max. @ 25° C.
________________________________________________________________ 349
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC280
CD54/74HCT280
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Input t"t,=6 ns)
CL
(pF)
CHARACTERISTIC
Propagation Delay
Any Input to LO
15
LE
15
Any Input to
SYMBOL
tpHl
tPLH
tPHL
tpLH
-
Power Dissipation Capacitance'
TYPICAL
HC
HCT
Cpo
UNITS
17
19
ns
17
18
ns
58
58
pF
'C PD is used to determine the dynamic power consumption, per package.
PO =Vee' f, (C PD + Cd where fi = input frequency,
C L = output load capacitance.
Vee = supply voltage
SWITCHING CHARACTERISTICS (CL = 50 pF, Inpul 1,,1,=6 ns)
CHARACTERISTIC
SYMBOL
Vec
Propagation Delay,
Any Input to LO
tpLH
2
4.5
6
2
4.5
6
2
4.5
6
Any Input to
LE
Output Transition
Time
Input Capacitance
tPHL
tpLH
tPHL
hlH
hHL
C,
_40° C to +85° C
-55°C 10 +125°C
25°C
UNITS
HCT
74HC
74HCT
54HC
54HCT
HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
-
200
40
34
200
40
34
75
15
13
-
10
-
-
45
42
-
-
-
-
-
15
-
-
250
50
43
250
50
43
95
19
16
-
10
-
10
-
-
-
-
-
56
-
-
-
-
53
-
-
-
-
-
19
-
-
300
60
51
300
60
51
110
22
19
-
10
-
10
-
-
68
63
22
-
-
10
-
ns
pF
L~~'R--+±----------:.t..
I,
I6~
av
2
n-
av---4-~-~~~----~~~
I8
EE~
LO
rE
13
12
NC
ra
I.
"
10
Vee
~5
~.
13
I2
I'
ro
GNO
av--'-'-'-,",/
92CS-3S835RI
92CS-38412RI
TERMINAL ASSIGNMENT
I INPUT LEVEL
~TCHING VOL TAGE, Vs
Fig. 2 - Propagation delay and transition times.
350 ___________________________________________
~
_________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
File Number
CD54/74HC283
CD54/74HCT283
1848
High-Speed CMOS Logic
so
AO
4-Bit Binary· Full Adder With Fast Carry
BO
51
AI
B'
A2 14
B2
A3
13
S2
15
'2
10
53
COUT
~---~ Vee .. 16
GNOE 8
92(5-40392
Type Features:
•
•
•
•
Adds two binary numbers
Full internallookahead
Fast ripple carry for economical expansion
Operates with both positive and negative logic
FUNCTIONAL DIAGRAM
The RCA-CD54174HC283 and CD54174HCT283 are binaryfull adders that add two 4-bit binary numbers and generate
a carry-out bit if the sum exceeds 15.
Because of the symmetry of the add function, this device
can be used with either all active-High operands (positive·
logic) or with all active-Low operands (negative logic).
When using positive logic the carry-in input must be tied
low if there is no carry-in.
The CD54HC/HCT283 are supplied in 16-lead hermetic
dual-in-line frit seal ceramic packages (F suffix). The
CD74HC/HCT283 are supplied in 16-lead dual-in-line plastiC
packages (E suffix) and in 16-lead dual-in-line surface
mount plastic packages (M suffix). Both types are also
available in chip form (H suffix).
Family Features:
•
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85 0 C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to
LSTTL Logic ICs
Alternate Source is PhilipslSignetics
CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity: ML =30%, MH =30% of Vee,
@ Vee = 5 V
CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'L = 0.8 V Max., V'H = 2 V Min.
CMOS Input Compatibility
I, :S 1 pA @ VOL, VOH
•
•
•
•
•
•
51
16
Bl
15
Vcc
B2
13
"
52
12
A3
"
53
A'
50
AO
BO
6
C'N
10
GND
A2
B3
C OUT
TOP V,EW
92CS-40391
TERMINAL ASSIGNMENT
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 351
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC283
CD54/74HCT283
e'N
7
"
GNOO
8
VeeO
16
52
51
"*
53
INVERTERS ARE CONNECTED IN THE HCT VERSION (----HCT)
**
CIRCUIT CONNECTIONS FOR He VERSION
t-· - .
-He)
92C L-40393
Fig. 1 . Logic diagram for HCIHCr types.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ...................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, I,K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ....................................................... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) ................................................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) .................................................... ±25 mA
DC Vee OR GROUND CURRENT, (Ieel: ..................................................................................... ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. ~ -40 to +60° C (PACKAGE TYPE E) ............................................................................... 500 mW
For T. ~ +60 to +85°C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/oC to 300 mW
For T. ~ -55 to +100°C (PACKAGE TYPE F, H) ........................................................................... 500 mW
For T. ~ +100 to +125°C (PACKAGE TYPE F, H) ............................................. Derate Linearly at 8 mW/oC to 300 mW
For T. ~ -40 to +70°C (PACKAGE TYPE M) ............................................................................... 400 mW
For T. ~ +70 to +125°C (PACKAGE TYPE M) ................................................. Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H ............................................................................................. -55 to +125°C
PACKAGE TYPE E, M ...............................................................................................-40 to +85° C
STORAGE TEMPERATURE (T".) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ........................................................ +265°C
Unit inserted into a PC board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................................................................................... +300° C
352 ____________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC283
CD54/74HCT283
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT2B3/CD54HCT2B3
CD74HC2B3/CD54HC283
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+B5°C
+125° C
+85°C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
10
Vee
V,
Vee
V
mA
V
V
V
High-Level
Input Voltage
Low-Level
V"
1.5
-
-
1.5
-
1.5
-
-
-
3.15
-
3.15
-
-
-
4.2
-
4.2
-
High-Level
Vo"
V"
or
-0.02
4.2
-
-
0.5
-
0.5
-
0.5
-
-
1.35
1.35
-
1.35
1.8
-
1.8
-
1.8
-
2
1.9
4.5
4.4
6
5.9
4.5 3.98
-
to
to
1.9
-
1.9
-
4.4
4.4
-
V"
or
5.9
-
5.9
-
V,"
-
3.84
-
3.7
-
V"
or
TTL Loads
V"
or
-4
V,"
-5.2
6
5.48
-
-
5.34
-
5.2
-
V,"
V"
or
2
-
-
0.1
-
0.1
-
0.1
0.02
4.5
-
0.1
-
0.1
-
0.1
V"
or
6
-
-
0.1
-
0.1
-
0.1
V,"
0.4
V"
or
0.4
V,"
±1
Vo,
CMOS Loads
V,"
TTL Loads
V"
or
4
4.5
-
-
0.26
-
0.33
V,"
5.2
6
-
-
0.26
-
0.33
-
6
-
-
±0.1
-
±1
-
I,
Vee
or
Voltage
Device Current
or
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
3.7
-
V
4.5 3.98
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±O.l
-
±1
-
±1
/lA
5.5
-
-
B
-
80
-
160
/lA
-
100 360
-
450
-
490
/lA
Vee
0
6
-
-
8
-
Gnd
80
-
160
or
Gnd
Additional
4.5
Quiescent Device
Vee -2.1
Current per input
pin: 1 unit load
-
Vee & Gnd
Vee
Icc
4.5
Between
Gnd
Quiescent
2
Any
Input Leakage
Current
-
5.5
V,"
Output Voltage
-
4.5
-
CMOS Loads
Low-Level
2
5.5
2
-
Min Typ Max Min Max Min Max
4.5
-
4.5
6
Output Voltage
Min Typ Max Min Max Min Max
4.5 3.15
2
V,"
6
Input Voltage
+2S"C
to
5.5
/lIce
*For dual-supply systems theoretical worst case (VI
= 2.4 V, Vee = 5.5 V)
specification is 1.8 rnA.
HCT INPUT LOADING TABLE
INPUT
UNIT LOADS'
C 'N
1.5
B1,A1,AO
1
BO
0.4
B3,A3,A2,B2
0.5
• Unit Load is bolee limit specified in Static Characteristics
Chart, e.g., 360 /JA max. @ 25°C.
_________________________________________________________________ 353
Technical Data
CD54/74HC283
CD54/74HCT283
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always.within the
following ranges:
LIMITS
CHARACTERISTIC
UNITS
MIN.
MAX.
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vee:"
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V,. Vo
2
6
V
4.5
5.5
V
0
Vee
V
Operating Temperature TA:
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
Input Rise and Fall Times. t,. tf
at 2 V
0
1000
ns
at 4.5 V
0
500
ns
at 6 V
0
400
ns
" Unless otherwise specified. all voltages are referenced to Ground.
SWITCHING CHARACTERISTICS (Vee
= 5 V, TA = 25°C, Input t"
tf
= 6 ns)
TYPICAL VALUES
CHARACTERISTIC
UNITS
CL
(pF)
HC
HCT
Propagation Delay.
C,N to SO
tPlH. tPHl
15
13
13
C,N to S1
tPLHI tPHL
15
15
18
C,N to S2
tPLH, tPHL
15
16
19
C,N to COUT
tPlH. tPHl
15
16
19
C,N to S3
tPHL, tPLH
15
19
22
An. Sn to COUT
tPHl, tPLH
15
16
20
An. Sn to Sn
tPHL, tPLH
15
18
21
-
70
82
Power Dissi pation Capacitance;
Cpo
ns
pF
" Cpo is used to determine the dynamic power consumption. per package.
Po = Vee 2 f; (Cpo + Cc) where: f; = input frequency
Cl = output load capacitance
Vee = supply voltage
354 ___________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC283
CD54/74HCT283
SWITCHING CHARACTERISTICS (C L = 50 pF, Input t" I, = 6 ns)
LIMITS
TEST
CONDITION
CHARACTERISTIC
UNITS
Propagation
Delay
-
-
270
-
-
54
-
54
-
65
-
-
46
-
-
-
295
58
-
59
69
200
-
-
-
40
-
39
6
-
27
-
-
-
34
-
180
-
-
-
225
4.5
-
36
-
43
-
45
6
-
31
-
-
38
-
-
2
"
tPlH
2
-
195
-
-
245
4.5
-
39
-
46
-
49
6
-
33
-
42
-
230
-
-
-
2
-
290
4.5
-
46
-
53
-
tPHL
6
-
39
tPLH
2
-
195
tPHL
4.5
-
39
6
-
33
tPLH
2
-
210
tPHl
4.5
-
42
58
-
-
-
50
-
-
-
345
-
-
66
-
69
80
-
-
295
-
-
-
-
49
-
-
245
48
-
49
-
60
-
59
-
72
-
-
42
-
50
-
-
265
-
-
315
-
-
49
-
53
61
-
63
-
74
-
-
-
59
-
6
-
36
-
-
-
45
54
-
hLH
2
-
75
-
-
95
-
-
-
110
-
-
hHL
4.5
-
15
15
-
19
-
22
-
22
-
13
-
-
19
6
-
16
-
-
-
19
-
-
-
10
-
10
-
10
-
10
-
10
-
10
G,
Gapacitance
Input Level
Switching Voltage, Vs
ns
-
-
Time
Input
41
-
-
31
tPHL
Transition
47
-
-
G,N to GOUT
Output
-
-
-
32
G,N to S2,
An, Bn to Sn
-
48
160
-
-
An, Bn to GOUT
240
-
tPLH
54HCT
-
2
4.5
tPHL
54HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tPHL
tPLH
G,N to S3
74HCT
tplH
G,N to SO
G,Nto Sl
74HC
HCT
HC
Vee
V
_55° C to +125° C
_40° C 10 +85° C
25°C
-
54174HC
54174HCT
Vee
3V
50% Vee
1.3 V
pF
92CS-36948RI
Fig. 2 - Transition and propagation delay times.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 355
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC297
CD54n4HCT297
File Number 1852
High-Speed CMOS Logic
B
16
vcc
A
15
C
ENCTR
kcp
IIDCp
DIU
14
D
4
13
~A2
5
12
ECPDOUT
6
"
XORPDOUT
liD OUT
7
10
~B
GND
8
9
~Al
TOP VIEW
92CS-40447
TERMINAL ASSIGNMENT
Digital Phase-Locked-Loop Filter
Type Features:
• Digital design avoids analog compensation errors
• Easily cascadable for higher order loops
• Useful frequency range:
DC to 55 MHz typical (k-clock)
DC to 35 MHz typical (I/D-clock)
• Dynamically variable bandwidth
• Very narrow bandwidth attainable
• Power-on reset
• Output capability:
Standard - XORPDouT, ECPDouT
Bus driver - I/DouT
The RCA-CD54174HC/HCT297 are high-speed silicon-gate
CMOS devices that are pin-compatible with low power
Schottky TTL (LSTTL).
These devices are deSigned to provide a simple, costeffective solution to high-accuracy, digital. phase-Iockedloop applications. They contain all the necessary circuits.
with the exception ofthedivide-by-N counter, to build firstorder phase-locked-loops.
Both EXCLUSIVE-OR (XORPD) and edge-controlled phase
detectors (ECPD) are provided for maximum flexibility. The
input signals for the EXCLUSIVE-OR phase detector must
have a 50% duty factor to obtain the maximum lock-range.
Proper partitioning of the loop function, with many of the
building blocks external to the package. makes it easy for
the designer to incorporate ripple cancellation (see Fig. 2)
or to cascade to higher order phase-locked-loops.
The length of the up/down K-counter is digitally
programmable according to the K-counter function table.
With A. B. C and D all LOW. the K-co!Jnter is disabled. With
A HIGH and B, C and D LOW. the K-counter is only three
stages long, which widens the bandwidth or capture range
and shortens the lock time of the loop. When A. B. C and D
are all programmed HIGH, the K-counter becomes
seventeen stages long. which narrows the bandwidth or
capture range and lengths the lock time. Real-time control
of loop bandwidth by manipulating the A to D inputs can
maximum the overall performance of the digital
phase-locked-loop.
The CD54174HC/HCT297 can perform the classic firstorder phase-locked-loop function without using analog
components. The accuracy of the digital phase-Iockedloop (DPLL) is not affected by VCC arid temperature
variations but depends solely on accuracies of the K-clock
and loop propagation delays.
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to
LSTTL LogiclCs
• Alternate Source is Philips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 30%, MH = 30% of Vee: @ Vee = 5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L =0.8 V Max., V,H =2 V Min.
CMOS Input Compatibility
I, :5 1 i1A @ VOL. VOH
D
C
B
A
4
KCp
DIU
CARRY
6
MODULO- K
COUNTER
BORRO.W
liD
CKT.
ENCTR
7
I/DOUT
IIDCp
9
"
4>Al
10
Q
4>B
12
ECPDOUT
F/F
13
4>A2
XORPDOUT
K
92CS-40448
FUNCTIONAL DIAGRAM
~6
______________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC297
CD54/74HCT297
The phase detector generates an error signal waveform
that, at zero phase error, is a 50% duty factor square wave.
At the limits of linear operation, the phase detector output
will be either HIGH or LOW all of the time depending on the
direction of the phase error (¢IN - ¢OUT). Within these
limits the phase detector output varies linearly with the
input phase error according to the gain Kd, which is
expressed in terms of phase detector output per cycle or
phase error. The phase detector output can be defined to
vary between ± 1 according to the relation:
%HIGH - %LOW
phase detector output =
100
The output of the phase detector will be Kd¢e, where the
phase error
¢e = ¢IN - ¢OUT.
EXCLUSIVE-OR phase detectors (XORPD) and edgecontrolled phase detectors (ECPD) are commonly used
digital types. The ECPD is more complex than the XORPD
logic function but can be described generally as a circuit
that changes states on one of the transitions of its inputs.
The gain (Kd) for an XORPD is4 because its output remains
HIGH (XORPDoUT = 1) for a phase error of v.. cycle.
Similarly, Kd for the ECPD is 2 since its output remains
HIGH for a phase error of V, cycle. The type of phase
detector will determine the zero-phase-error point, i.e., the
phase separation of the phase detector inputs for a ¢e
defined to be zero. Forthe basic DPLL system of Fig. 3, ¢e =
o when the phase detector output is a square wave.
The phase detector output controls the up/down input to
the K-counter. The counter is clocked by input frequency
Mfe which is a multiple M of the loop center frequency fe.
When the K-counter recycles up, it generates a carry pulse.
Recycling while counting down generates a borrow pulse. If
the carry and the borrow outputs are conceptually combined
into one output that is positive for a carry and negative for a
borrow, and if the K-counter is considered as a frequency
divider with the ratio Mfc/K, the output of the K-counter will
equal the input frequency multiplied by the division ratio.
Thus the output from the K-counter is (Kd¢eMfe)/K.
The carry and borrow pulses go to the incremenVdecrement
(liD) circuit which, in the absence of any carry or borrow
pulses has an output that is Y, of the input clock (IIDcp). The
input clock is just a multiple, 2N, of the loop center
frequency. In response to a carry of borrow pulse, the liD
circuit will either add or delete a pulse at I/DouT. Thus the
output of the liD circuit will be Nfe + (Kd¢eMfe)/2K.
The output of the N-counter (or the output of the phaselocked-loop) is thus:
fo = fe + (Kd¢eMfe)/2KN.
If this result is compared to the equation for a first-order
analog phase-locked-loop, the digital equivalent of the gain
of the VCO is just Mfe/2KN or fe/K for M = 2N.
Thus, the simple first-order phase-locked-loop with an
adj ustable K-counter is the equivalent of an analog phaselocked-loop with a programmable VCO gain.
The XORPD inputs are v.. cycle out-of-phase for zero phase
error. For the ECPD, ¢e = 0 when the inputs are Y, cycle out
of phase.
The CD54HC297 and CD54HCT297 are supplied in 16-lead
hermetic dual-in-line frit-seal ceramic packages (F suffix).
The CD74HC297 and CD74HCT297 are supplied in 16-lead
dual-in-line plastic packages (E suffix) and in 16-lead dualin-line surface-mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
K COUNTER FUNCTION TABLE
(DIGITAL CONTROL)
FUNCTION TABLE
EXCLUSIVE-OR PHASE DETECTOR
¢A,
D
C
B
A
MODULO (K)
L
L
L
L
Inhibited
L
L
L
L
L
L
H
L
H
H
L
L
H
L
23
24
H
L
H
L
L
H
H
H
H
L
L
H
L
L
L
H
L
H
27
L
H
H
L
28
2"
2'0
¢A2
¢B
ECPD OUT
H or L
'-
H
~
H or L
H or L
L
~
No Change
H or L
No Change
25
26
L
H
H
H
H
L
L
L
H
L
L
H
H
L
H
L
2"
212
H
L
H
H
213
H
H
L
L
2'4
H
H
L
H
2'5
H
H
H
L
2'6
H
H
H
H
217
¢B
XORPD OUT
FUNCTION TABLE
EDGE-CONTROLLED PHASE DETECTOR
---.r-
H = steady-state high level
L = steady-state low level
L = transition from high to low
= transition from low to high
-.r
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 357
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC297
CD54/74HCT297
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT297/CD54HCT297
CD74HC297/CD54HC297
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
UNITS
CHARACTERISTIC
+25°C
V,
10
Vee
V
rnA
V
Input Voltage
Low-Level
V"
High-Level
VOH
V"
or
-0.02
CMOS Loads
V,"
TTL Loads
Bus Driver and
V"
or
-4
Standard Output
V,"
-5.2
Low-Level
Output Voltage VOL
-
1.5
4.5 3.15
V,"
Input Voltage
Output Voltage
Min Typ Ma. Min Ma. Min Ma.
2
High-Level
#
V"
or
I liD
I -6
I -7.8
0.02
CMOS Loads
V,"
TTL Loads
V"
#
8us Driver and
or
4
Standard Output
V,"
5.2
I
I
+25°C
-
-
3.15
-
3.15
-
4.2
-
4.2
-
1.5
1.5
V
-
2
1.9
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
4.4
-
V"
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5 3.98
-
-
3.84
3.7
-
or
-
5.34
-
5.2
-
V,"
-
0.1
-
0.1
0.1
-
0.1
V"
or
4.2
2
-
4.5
-
6
-
Min Typ Ma. Min Ma. Min Ma.
4.5
to
2
-
-
2
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
3.7
-
V
5.5
0.5
-
0.5
-
0.5
1.35
-
1.35
-
1.35
1.8
-
1.8
-
1.8
4.5
-
to
5.5
4.5
V"
6
5.48
2
6
-
4.5
0.1
0.1
-
-
0.1
-
0.1
-
0.1
V,"
-
-
0.26
0.33
-
0.4
V"
or
6
-
-
0.26
-
0.33
-
0.4
V,"
6
-
-
±0.1
-
±1
-
±1
4.5 3.98
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
IlA
5.5
-
-
8
-
80
-
160
IlA
-
100 360
-
450
-
490
IlA
Any
Input Leakage
Current
V
-
liD
I 7.8
Vee
-
6
4.5
6
V,
..
Vee
or
Gnd
Quiescent
Vee
Device Current Icc
or
Voltage
Between
Vee & Gnd
Vee
0
6
-
-
8
-
80
-
160
or
Gnd
Gnd
Additional
4.5
Quiescent Device
Vee -2.1
CUrrent per input
to
5.5
pin: 1 unit load 61cc
*For dual-supply systems theoretical worst case (VI
=2.4 V, Vee = 5.5 V) specification
is 1.8 rnA.
# XORPD, ECPD
HCT INPUT LOADING TABLE
INPUT
UNIT LOADS'
-
ENcT", DIU
A, B, C, 0, Kcp, t/JA2
0.3
I/Dcp, t/JA" t/JB
1.5
0.6
• Unit Load is h.lcc limit specified in Static Characteristics
Chart, e.g., 360 pA max. @ 25 0 C.
358 __________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC297
CD54/74HCT297
PRE-REQUISITE FOR SWITCHING FUNCTION
LIMITS
_40° C to +85° C
25°C
CHARACTERISTIC
Vee
HC
HCT
74HC
_55° C to +125° C
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
2
6
-
-
-
5
-
-
-
4
-
-
4.5
30
-
30
-
24
-
24
-
20
-
20
6
35
-
28
-
24
-
3
-
-
4
-
-
2
-
-
2
-
-
4.5
20
20
-
16
-
16
-
13
-
13
6
24
-
-
-
-
19
-
-
-
15
-
-
2
80
-
-
-
100
-
-
-
120
-
-
-
4.5
16
-
16
20
20
-
24
24
-
6
14
-
-
-
-
-
20
-
-
-
Maximum Clock
Frequency
f MAX
Kcp
l/Dcp
Clock Pulse Width
tw
2
125
-
155
-
-
~90
-
-
-
4.5
25
-
25
-
31
-
31
-
38
-
38
ns
6
21
-
-
-
26
-
-
32
2
100
-
-
-
125
-
-
4.5
20
20
25
30
30
-
ns
17
-
21
-
25
6
-
-
-
-
-
-
26
-
-
-
Setup Time
DIU. ENcTR to Kcp
tsu
tH
17
2
0
-
4.5
0
-
0
-
0
6
0
-
-
-
0
Hold Time
DIU. ENcTR to Kcp
MHz
-
Kcp
1IDcp
MHz
0
-
150
-
-
0
-
-
-
0
-
0
-
0
-
-
-
-
0
ns
ns
SWITCHING CHARACTERISTICS (Cl = 50 pF, Inpul I" I, = 6 ns)
LIMITS
_40° C to +85° C
25°C
CHARACTERISTIC
Vec
HC
HCT
74HC
-55°C to +125°C
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay,
tplH
2
-
-
-
220
-
-
-
265
-
-
tpHL
4.5
-
175
IIDep to I/DouT
35
-
35
-
44
-
44
-
53
-
53
6
-
30
-
-
-
34
-
-
-
43
-
-
2
-
150
-
-
-
190
-
-
-
225
-
-
4.5
30
-
30
-
38
-
38
-
45
-
45
6
-
26
-
-
-
33
-
-
-
38
-
-
2
-
200
-
250
300
-
40
40
50
-
-
-
-
-
4.5
50
-
60
-
60
34
-
-
-
-
43
-
-
-
51
-
-
-
B0----1>-----1
CO:-:-----1>-----f4
CONTROL CIRCUIT
Do---C>----~_~O~------------------~14~~~~~~~~~~~~~~J_~~
4
KCp
OD-----1------,
DIU
ENCTR
CARRY
INCREMENTI DECREMENT CIRCUIT
5
IIDCp
I/DOUT
D
Q
CP
FF
Q
CP
Q
FF
Q
Q
CP
FF
Q
D
CP
Q
FF
Q
CP
a
EXCLUSIVE-OR PHASE DETECTOR
11
)----------------------I:>--~JXORPDOUT
EDGE- CONTROLLED PHASE DETECTOR
12
~~~-------------_1~--~ECPDOUT
92CL-4045B
Fig. 1 - Logic diagram.
360 ________________________________________________________________
___________________________________________________________ TechnicaIData
CD54/74HC297
CD54/74HCT297
MfC
---i~----~~--r_------------~
MfC
_~____tK~CfP__~------------~
DIVIDE-BY-K
COUNTER
DIVIDE-8Y-K
COUNTER
2NfC
1/DOUT
_-+-__
fO UT ....
92C5-40456
oj>OUT
Fig. 2 - OPLL using both phase detectors in a ripple-cancel/ation
scheme.
CARRY PULSE
(INTERNAL SIGNAL!
BORROW PULSE
(INTERNAL SIGNAL!
I/O cp INPUT
Fig. 3 - OPLL using EXCLUSIVE-OR phase detection.
r---1
----------illr------------J1
IL_ _ __
r--1
--------'
~:I-I---------------
~
I/DOUTOUTPUT~~
92C5-40449
Fig. 4 - Timing diagram: I/OouT in-lock condition.
.pB INPUT
oj>" INPUT
oj>A2 INPUT
oj> A I INPUT
ECPDOUT OUTPUT
XORPDOUT OUTPUT
92C5-40450
Fig. 5 - Timing diagram: edge-control/ed phase comparator
waveforms.
92C5-40451
Fig. 6- Timing diagram: EXLUSIVE-OR phase detector
waveforms.
361
TechnicaIData ___________________________________________________________
CD54/74HC297
CD54/74HCT297
4>BINPUT
92CS- 40454
Fig. 7 - Waveforms showing the clock (I/0ep) to output (IIDOUT)
propagation delays, clock pulse width, output transition
times and maximum clock pulse frequency.
Fig. 8 - Waveforms showing the phase input (CPS, CPA,) to output
(XORPOOUT) propagation delays and output transition
times.
4>B INPUT
O/U,ENCTR
INPUT
ECPD OUT
OUTPUT
92C5-40453
92CS- 40455
NOTE:
Fig. 9 - Waveforms showing the phase input (CPS, CPA,) to output
(ECPO ouT ) propagation delays and output transition times.
I nput Level
Switching Voltage, Vs
THE SHADED AREAS INDICATE WHEN THE
INPUT IS PERMITTED TO CHANGE FOR
PREDICTABLE OUTPUT PERFORMANCE.
Fig. 10 - Waveforms showing the clock (Kep) pulse width and
maximum clock pulse frequency, and the input (O/V,
ENeTR) to clock (Kep) set-up and hold times.
54174HC
54174HCT
Vee
3V
50% Vee
1.3 V
362 ___________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC299
CD54/74HCT299
File Number 1485
High-Speed CMOS Logic
so
20
OE1
19
S1
OE2
18
DS7
1/°6
17
Q7
1/°4
16
1/0 7
Type Features:
"°2
15
1/0 5
liDO
14
1/0 3
QO
13
1/0~
MR
12
cp
11
DSO
• Four Operation Modes: Shift Left, Shift Right, Load and Store
• Can be cascaded for N-bit word lengths
• 110 0 -110 7 bus drive capability and 3-state for
bus oriented applications
• Buffered inputs
• Typical f MAX =50 MHz @ Vee=5 V, C L =15 pF, TA=25°C
GND
10
Vcc
92C5-36837
a-Bit Universal Shift Register; 3-State
TERMINAL ASSIGNMENT
The RCA-C054/74HC299 and C054/74HCT299 are a-bit
shift/storage registers with 3-state bus interface capability.
The register has four synchronous-operating modes controlled by the two select inputs as shown in the mode select
(SO, S1) table. The mode select, the serial data (OSO, OS7)
and the parallel data (1/0 0 -1/0 7 ) respond only to the low-tohigh transition of the clock (CP) pulse. SO, S1 and data
inputs must be one set-up time prior to the clock positive
transition.
The Master Reset (MR) is an asynchronous active low input.
When MR output is low, the register is cleared regardless of
the status of all other inputs. The register can be expanded
by cascading same units by tying the serial output (00) to
the serial data (OS7) input of the preceding register, and
tying the serial output (07) to the serial data (OSO) input of
the following register. Recirculating the (n x 8) bits is accomplished by tying the Q7 of the last stage to the OSO of the
first stage.
The 3-state input/output 1(/0) port has three modes of
operation:
1. Both output enable (OE1 and OE2) inputs are low and
SO or S1 or both are low, the data in the register is
presented at the eight outputs.
2. When both SO and S1 are high, 1/0 terminals are in the
high impedance state but being input ports, ready for
parallel data to be loaded into eight registers with one
clocl< transition regardless of the status of OE1 and
OE2.
3. Either one of the two output enable inputs being high
will force 1/0 terminals to be in the off-state. It is noted
that each 1/0 terminal is a 3-state output and an CMOS
buffer input.
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to
LSTTL Logic ICs
• Alternate Source is Philips/Signetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
N ,L =30%, MH=30% of Vee: @ Vcc=5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'L =0.8 V Max., V,H =2 V Min.
CMOS Input Compatibility
I, S; 1 IlA @ VOL, V OH
The C054HC299 and C054HCT299 are supplied in 20-lead
hermetic dual-in-line ceramic packages (F suffix). The
C074HC299 and C074HCT299 are supplied in 20-lead
dual-in-line plastic packages (E suffix) and in 20-lead dualin-line surface mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
________________________________________________________________ 363
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC299
CD54/74HCT299
MAXIMUM RATINGS. Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) .................................................................................. -O.S to -r 7 V
DC INPUT DIODE CURRENT, I'K (FOR V; < -O.S V OR V, > Vee +O.SV) ..................................................... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR V. < -O.S V OR V. > Vee +O.SV) ................................................. ±20mA
DC DRAIN CURRENT, PER OUTPUT (I.) (FOR -O.S V < V. < Vee + O.SV)
For Outputs ...................................................................................................... ±2SmA
For 1/0 Outputs ..................................................................................................... ±3SmA
DC Vee OR GROUND CURRENT (Icc) .................•........••.......................•...............••..•.....••.•... ±70mA
a
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60· C (PACKAGE TYPE E) ........................................................................... SOO mW
For T. = +60 to +8S·C (PACKAGE TYPE E) .............................................. Derate Linearly at 8 mW/·C to 300 mW
For T. = -SS to +100·C (PACKAGE TYPE F, H) ........................................................................ SOO mW
For T. +40 to +12S·C (PACKAGE TYPE F, H) ........................................ Derate Linearly at 8 mW/·C to 300 mW
For T.; -40 to +70·C (PACKAGE TYPE M) ............................................................................ 400 mW
ForT.; +70 to +12S·C (PACKAGE TYPE M) .............................................. Derate Linearly at 6 mW/·C to 70 mW
OPERATING TEMPERATURE RANGE (T.)
PACKAGE TYPE F, H .......................................................................................... -55 to +125·C
PACKAGE TYPE E, M .......................................................................................... -40 to +8S·C
STORAGE TEMPERATURE (T",) ................................................................................. -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1132 in. (1.59 ± 0.79 mm) from case for 10 s max ...................................................... +265·C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only .................................................................................. +3oo·C
=
RECOMMENDED OPERATING CONDITIONS
For maximum reliability. nominal operating conditions should be selected so that operation Is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA-Full Package Temperature Range)
Vcc:'
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage, V" Vo
Operating Temperature, T A:
CD74 Types
CD54 Types
Input Rise and Fall Times, t.,t,:
at 2 V
at 4.5 V
at 6V
.,
, Unless otherwIse specIfIed,
all voltages are referenced to Ground.
DEi
CP
12
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vcc
-40
-55
+85
+125
·C
0
0
0
1000
500
400
ns
V
V
OE2
2
3
20
Vcc
/oo :
BUS LINE
OUTPUTS
r
1102
5
SHIFT
REGISTER
IIO
3-STATE
OUTPUTS
14
13 110
3
15
BUS LINE
OUTPUTS
1105
110 4
4
16
8
17
1106
STANDARD OUTPUT QO
~
1101
1./0
3-STATE
OUTPUTS
0--1----------'
L--------If--Q
1/07
Q7
STANDARD OUTPUT
19
I
~-----r-~SI
SO~_I~----_I
92CM-36996RI
18
DSO
OS?
364 __________________________________~F~~~._1~-~F~u~n_c_ti_o_n_d_~~g~~~m~.~___________________________________
------------------______________________________________ TechnicaIData
CD54/74HC299
CD 54/74H CT299
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT299/CD54HCT299
CD74HC299/CD54HC299
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85"C
+125°C
+85 Q C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
10
~ee
V
mA
V
High-Level
Input Voltage
V'H
Low-Level
Input Voltage
VOL
High-Level
VOL
Output Voltage VOH
or
CMOS Loads
-0.02
V'H
TTL Loads
VOL
Min Typ M •• Min M •• Min M . .
-
-
1.35
-
-
I.B
-
1.9
-
4.4
-
5.9
-
2
1.5
4.5
3.15
6
4.2
2
4.5
6
2
1.9
4.5
4.4
6
5.9
-
0.5
1.5
-
-
3.15
-
4.2
-
1.35
-
1.35
I.B
-
I.B
-
1.9
-
-
4.4
-
or
-
5.9
-
V'H
3.B4
-
3.7
5.34
-
5.2
-
V'H
0.1
0.1
VOL
0.1
-
4.2
-
0.5
3.9B
-
Standard Outpul
V'H
-5.2
-7.B
6
5.4B
-
Low-Level
VOL
2
-
0.1
4.5
-
6
-
-
0.1
-
4.5
-
-
0.26
-
0.33
-
0.4
-
0.26
-
0.33
-
0.4
V'H
TTL Loads
VOL
an
liOn
Bus Driver and
or
4
6
V'H
5.2
7.8
Standard Output
Input Leakage
Current
I,
0.1
0.1
-
2
-
2
-
V
-
-
O.B
-
O.B
-
O.B
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.9B
-
-
3.B4
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
/JA
5.5
-
-
8
-
80
-
160
/JA
-
100 360
-
450
-
490
/JA
-
±5
-
±10
/JA
to
5.5
VOL
or
or
0.1
V'H
VOL
6
or
V'H
Any
Voltage
Vee
or
Vee
or
Gnd
-
4.5
-
0.1
6
-
-
±0.1 -
±1
-
±1
Between
Vee and
Gnd
Gnd
Quiescent Device
Current
lee
2
to
5.5
VOL
4.5
CMOS Loads
Min Typ M •• Min M .. Min M ••
4.5
-
0.5
-6
0.02
V
-
an liOn
or
V
1.5
-4
Output Voltage Va'
Vee
3.15
or
Bus Driver and
+25"C
V,
0
6
-
-
8
-
BO
-
160
Vee
or
Gnd
Additional
Quiescent Device
4.5
Current per
Vee -2.1
1 Unit Load
3-State
to
5.5
Input Pin:
"'lee
Leakage
VOL
or
Current
V'H
Vo=
Vee
6
-
orGnd
'For dual-supply systems theoretical worst case (V,
-
±0.5
-
±5
-
±10
VOL
or
5.5
-
-
±0.5
V'H
=2.4 V, Vee =5.5 V) specification is I.B mAo
HCT Input Loading Table
Input
Unit Loads·
S1, MR
0.25
1/00-1/07
0,25
OSO,OS7
0.25
SO, CP
0,6
OE1, OE2
0.3
'Unit load is t. Icc limit specified in Static Characteristics
- -______________________________________________________________
Chart, e.g., 360 pA max. @ 250 C.
365
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC299
CD54/74HCT299
STANDARD
OUTPUT
SI
fol.----BUS
LINE
OUTPUTS-----~~I
1/0 7
Q7
~20
Vee
9
Mil
f-I.O-------BUS LINE OUTPUTS-------<.--il
Fig. 2 - Logic diagram.
STANDARD
OUTPUT
92CL~
37003R2
a
CL
o
)o-~----Q
R
CL
92CS- 38782
Fig. 3 - Flip-Flop detail (00-07).
MODE SELECT-FUNCTiON TABLE
REGISTER OPERATING MODES
FUNCTION
INPUTS
REGISTER OUTPUTS
Sl DSO DS7 liOn 00 01
06 07
X
X
X
X
L
L
L
L
I
I
X
X
L
qo - q.
q.
I
h
X
X
H
qo - q. 06
q,
h
X
I
X
q2
L
q7
q,
h
X
h
X
q2
H
- q7
I
X
X
X
qo q,
- q. q7
X
h
I
L
L
X
- L
L
h
X
X
h
H
H
H
H
-- - -H
H
Shift Left
H
--H
-Hold (do nothing)
H
- Parallel Load
H
-H
--366 ___________________________________________
_
Reset (Clear)
Shift Right
MR
L
CP
X
SO
X
~
h
~
h
I
I
~.
I
.../' h
h
-------
Technical Data
CD54/74HC299
CD54/74HCT299
MODE-SELECT FUNCTION TABLE
3-STATE I/O PORT OPERATING MODE
FUNCTION
Read Register
OE1
L
L
L
L
OE2
L
L
L
L
SO
L
L
X
X
H
X
H
H
X
Load Register
Disable 110
X
INPUTS
S1
X
X
L
L
H
X
X
X
X
Qn(Regisler)
L
H
L
H
an = I/On
INPUTS/OUTPUTS
1/00 - - - 1/07
L
H
L
H
liOn = Inputs
X
X
(Z)
(Z)
X
X = Voltage level on logic status don't care.
H = Input voltage high level.
Z = Output in high impedance state.
h = Input voltage high one set-up time prior clock transition.
...,,- = Low-to-high clock transition.
L = Input voltage low level.
I = Input voltge low one set-up time prior clock transition.
qn = Lower case letter indicates the state of the referenced output one set-up time prior clock transition.
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C,lnpul I" If = 6 ns)
Propagation Delay
Clock to I/O Outputs (Fig. 4)
TYPICAL VALUES
HC
HCT
Cl
(pF)
SYMBOL
CHARACTERISTIC
UNITS
tPLH
t PHL
15
17
19
t pHL
15
17
19
15
10,13,15
10,13,15
150
170
ns
Clock 00 or 07 (Fig. 4)
MR to Outputs (Fig. 5)
tPZl, tPZH
Output Enable and Disable Times (Fig. 6 & 7)
tpLZ, tPHZ
-
Cpo'
Power Dissipation Capacitance
'CPD is used to determine the dynamic power consumption, per
PD=CPD Vee' fi + I (Cl Vee' fo) where:
f;=input frequency
Cl =output load capacitance
fo=output frequency
Vee=supply voltage
pF
regist~r.
Pre-requisite for Swllchlng Function
CHARACTERISTIC
SYMBOL Vee
Maximum Clock
Frequency
f"AX
IIlR" Pulse Width
tw
(Fig. 5)
Clock Pulse Width
(Fig. 4)
tw
Setup Time
080, D87, liOn 10 Clock
(Fig. 8)
Hold Time
DSO, DS7, liOn, SO, S1
to Clock (Fig. 8)
Recovery Time
MR 10 Clock
(Fig. 5)
Setup Time
S1, SO to Clock
Isu
IH
IREC
tsu
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
_40° C 10 +85° C
25°C
HC
HCT
74HC
74HCT
Min. Max. Min. Max. Min. Max. Min. Max.
5
6
25
20
30
25
35
29
50
65
15
10
13
19
9
11
100
80
20
25
20
16
17
14
125 100 25
20
25
20
21
17
0
0
0
0
0
0
0
0
5
5
5
5
5
5
5
5
150 120 34
27
30
24
26
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-55°C to +12SoC
54HC
54HCT UNITS
Min. Max. Min. Max.
4
20
16
MHz
23
75
22
15
13
120 30
24
-
20
150
30
26
0
0
0
5
5
5
180
36
31
-
-
30
-
-
-
0
-
-
-
-
-
-
5
-
41
-
ns
-
_________________________________________________________________ 367
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC299
CD54/74HCT299
SWITCHING CHARACTERISTICS (C L =50 pF, Inputt"t,=6 ns)
CHARACTERISTIC
SYMBOL
Vee
Propagation Delay
Clock to 1/0 Output
(Fig. 4)
Clock to 00 and 07
(Fig. 4)
t pLH
t pHL
Propagation Delay
MR to Output
(Fig. 5)
Output High-Z to
High Level
(Fig. 6)
Output High Level
to High-Z
(Fig. 6)
Output Low Level
to High-Z
(Fig. 7)
Output High-Z
to Low Level
(Fig. 7)
Output Transition Time
t pHl
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
00,07
t PZH
t pHZ
t pLZ
t PZL
hLH
hHL
(Fig. 9)
1/0 0 to 1/07
(Fig. 9)
Input Capacitance
3-State Output
Capacitance
C,
Co
-
-40°C to +85°C
-55°C to +125°C
25°C
54HC
74HC
74HCT
54HCT
UNITS
HC
HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
250 300
- 200 40
50
56
60
68
45
43
51
34
250 300 200 40
45
50
56
60
68
43
51
34
250 300 200 40
46
50
58
60
69
43
34
51
195 235
ns
155 40
47
48
31
32
39
33
40
26
185 230 280 37
37
46
46
56
56
48
31
39
195 235
155 47
31
32
39
40
48
40
26
33
130 165 195 26
33
38
39
45
30
22
28
33
110 75
95
15
15
19
19
22
22
13
19
16
75
90
60
12
12
15
15
18
18
15
10
13
10
10
10
10
10
10
20
20
20
20
20
20
pF
368 _________________________________________________________________
Technical Data
CD54/74HC299
CD54/74HCT299
INPUT LEVEL
M"R
I rec
CP
'-_---'::.-_---'_ _-"''''--_ _- - ' 92C5-36998
92C5- 36997
Fig. 4 - Clock pre-requisite and propagation delays.
ALL OTHER INPUTS
TlEO HIGH OR LOW
Fig. 5 - Master Reset pre-requisite and propagation delays.
o"~:~,:r{ J~
ALL OTHER INPUTS
TIED HIGH OR LOW
tpLZ
OEI
OR
OE2
74/54 HC
INPUT LEVEL
Vs
I
Vw
I/o n
Vw
74/54 HCT
3V
VCC
50%VCC
1.3 V
...."". o\icc
~
90% VCC
Vt
!llJ".
74/54 HC
INPUT
LEVEL
Vs
VI
Vw
CC
VCC
50 %VCC
50% Vee
10% Vce
I
IHp-JOV\f\r-vce
OEI
OR
OE2
74/54 HCr
3V
1.3 V
1.3V
10%VCC
92CS-36999RI
92CS-37000RI
Fig. 6 - 3-state propagation delays.
Fig. 7 - 3-state propagation delays.
INPUT LEVEL
OSO, DS7 OR ItOn
ep
92C5 - 31002
92CS-37001RI
Fig. B - Data pre-requisite times.
Fig. g - Outputtransilion times.
_______________________________________________________________ 369
TechnicaIData ___________________________________________________________
CD54/74HC354, CD54/74HCT354
CD54/74HC356, CD54/74HCT356
File Number
1690
High-Speed CMOS Logic
SO
51
52
00
01
02
a-Input Multiplexer/Register, 3-State
19 y
CD54/74HC/HCT354 - Transparent Data & Select Latches
CD54/74HC/HCT356 - Edge-Triggered Data Flip-Flops
Transparent Select Latches
18 Y
Type Features:
OS
LE
00
.E: FOR '354
OE2 _ _ _--'-"l
CP FOR '356
OE3----'-"
FUNCTIONAL DIAGRAM
•
•
•
•
Buffered inputs
3-State Complementary Outputs
Bus Line Driving Capability
Typical propagation delay: Vee = 5V, C L = 15 pF, TA = 25°C
Data to Output (354) = 18 ns
Clock to Output (356) = 22 ns
The RCA-CD54/74HC/HCT354 and CD54/74HC/HCT356
are data selectors/multiplexers that select one of eight
sources. In both the HC/HCT354 and HC/HCT356 the data
select bits SO, S1, and S2 are stored in transparent latches
that are enabled by a low latch enable input, LE.
In the HC/HCT354 the data enable input, E, controls
transparent latches that pass data to the outputs when E is
high and latches in new data whenE is low.
In the HC/HCT356 the data is stored in edge-triggered flipflops that are triggered by a low-to-high clock transition.
I n both types the three-state outputs are controlled by
three output-enable inputs OE1, OE2, and OE3.
The CD54HC/HCT354/356 are supplied in 20-lead ceramic
dual-in-line packages (F suffix). The CD74HC/HCT354/356
are supplied in 20-lead plastic dual-in-line plastic packages
(E suffix). The CD54/74HC/HCT354/356 are also supplied
in chip form (H suffix). The CD74HC/HCT354/356 are also
available in plastic surface mounted packages (M suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
NIL = 30%, N'H = 30% of Vee: @ Vee = 5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
VIL = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, :s 1 vA @ VOL, V OH
20
07
Vee
19 Y
06
18
05
Y
17 OE3
04
16
03
15
02
"
01
13
DO
0E2
DEi
SO
51
12 52
GND
10
11
LE
*E for 354
CP for 356
TERMINAL ASSIGNMENT
370 ________________________~-----------------------------------------
Technical Data
CD54/74HC354, CD54/74HCT354
CD54/74HC356, CD54/74HCT356
15
0E1 0-------,
_E HC/HCT354 \
CP HC/HCT356
9
8
DO o-----+-----j
010-----+-----j
6
o
A
T
A
020---
030-----+4
040-----1-
o
F
8
R
E
G
I
S
E
L
S
E
E
C
R
S·
o
T
05O----~
T
R
060-----+07
BUFFERS
·'354 B-LATCHES
'3568-F/Fs
o-----I-l
Block Diagram
TRUTH TABLE
Inputs
Select #
Enable
Data
'HC354
'HCT354
Clock
'HC356
'HCT356
Output
Enables
OE1 OE2 OE3
y
y
Z
Z
Z
Z
Z
Z
DO
DO,
D1
D1,
D2
D2,
D3
D3,
D4
D4,
D5
D5,
D6
D6,
D7
D7,
S2
S1
SO
E
CP
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
f'
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
~
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H or L
-'
H or L
-'
H or L
-'
H or L
..-r
H or L
..-r
H or L
~
H or L
..-r
H or L
X
Outputs
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
i50
DO,
51
D1,
52
D2,
D3
03,
D4
D4,
05
05,
D6
156,
D7
07,
Noles
H ::: high level (steady state)
L = low level (steady state)
X = irrelevant (any input, including transitions)
Z::: high-impedance state (off state)
~ transition from low to high level
DO .,' 07 =the level of steady-state inputs at inputs DO through 07,
respectively, at the time of the low-ta-high clock transition in
the case of HC356
DOn ... D7n =the level of steady state inputs DO through 07, respectively,
before the most recent low-ta-high transition of data control
or clock
_
# This column shows the input address setup with LE low
______________________________________________________________ 371
Technical Data __________________________________________________________
CD54/74HC354, CD54/74HCT354
CD54/74HC356, CD54/74HCT356
15
F
000-------1
16
mO--------i,>O---==i
cc
P
I 1 OF 8 LATCHES
I
E
I
I
I 8(7,6,5,4,3,2,1)
I
I
I
:
I
18
Y
r------------------~
N
-=-
GND
I
I
I
_
l E E
l:d.-t~~~:,::-LATCHES
t
19
VCC Y
N
SELO
I
I
:
OTHER 7
LATCH OUTPUTS
CONNECT HERE
-=-
GND
TO OTHER 7 lATCHES
S~LO I'S-E-L-l-S-E-L-2-S-E-L-3-,I_S-E-L-4-S-E-L-S-S-E-L-6-S-E-L~7\
20
O---VCC
10
O---GND
LE
LE
LE
LE
92CL-38SB4
HC(HCT354 Logic Diagram
372 _________________________________________________________________
Technical Data
CD54/74HC354, CD54/74HCT354
CD54/74HC356, CD54/74HCT356
E
ee
p
18
Y
N
= GND
DO
,
SELO
I
I
SELO / SEL1
TO 7 OTHER F/Fs
,
SEL2
SEL3
SEL4
SEL5
SEL6
SEL7 \
20
o--Vee
10
o--GND
LE
SLO
LE
LE
LE
92CL-38885
11
LE
CE
CE o--[>--!>-l--j). LE
HCIHCT356 Logic Diagram
____________________________________________________________ 373
Technical Data ___________________________________________________________
CD54/74HC354, CD54/74HCT354
CD54/74HC356, CD54/74HCT356
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (V,e)
(Voltages referenced to ground) ................................................................................. . -0.5 to +7V
±20mA
DC INPUT DIODE CURRENT, I.. (FOR V, < -0.5 V OR V, > Vee + 0.5V) ..
±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR V, < -0.5 V OR V, > 0.5 V +Vee)
..... ±35mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Va < Vee + 0.5V)
±70mA
DC Vee OR GROUND CURRENT (Icc) ............... .
POWER DISSIPATION PER PACKAGE (Po):
For T A = -40 to +60° C (PACKAGE TYPE E) .......... .. ........ .
For TA = +60 to +85° C (PACKAGE TYPE E)
For TA = -55 to +100°C (PACKAGE TYPE F, H) ..
For TA = +100 to +125°C (PACKAGE TYPE F, H) ............
......
Derate Linearly at 8 mWrC to
....
Derate Linearly at 8 mWrC to
...........
500
300
500
300
mW
mW
mW
mW
For T. = -40 to +70°C (PACKAGE TYPE M) .......................................................................... 400 mW
For T. = +70 to +125° C (PACKAGE TYPE M) ............................................. Derate Linearly at 6 mW/o C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
.. -55 to +125°C
PACKAGE TYPE F. H ........ .
.. -40 to +85°C
PACKAGE TYPE E, M ...... ..
. -65 to +150°C
STORAGE TEMPERATURE (T"g)
.......... .
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in .. 1.59 mm)
with solder contacting lead tips only .................................. .
+265°C
.. +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA - Full Package Temperature Range)
CD54/74HC Types
CD54174HCT Types
DC Input or Output Voltage V" Vo
Operating Temperature T A:
CD74 Types
CD54 Types
Input Rise and Fall Times t" t,
at 2 V
at 4.5 V
at 6 V
LIMITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
-40
-55
+85
+125
0
0
0
1000
500
400
UNITS
V
V
°C
ns
'Unless otherwise specified, all voltages are referenced to Ground.
374 ________________________________________________________________
Technical Data
CD54/74HC354, CD54/74HCT354
CD54/74HC356, CD54/74HCT356
STATIC ELECTRICAL CHARACTERISTICS
CD74HC354/356/CD54HC354/356
CD74HCT354/356/CD54HCT3541356
TEST
74HCI54HC
74HC
54HC
TEST
74HCTI54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+B5"C
+125°C
+85°C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
V
10
mA
V"
V
+25°C
V,
V
Vee
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
4.5
V,"
1.5
1.5
1.5
3.15
3.15
3.15
to
4.2
4.2
42
5.5
Low-Level
Input Voltage
High-Level
Output Voltage
4.5
V"
V"
Va"
CMOS Loads
or
-0.02
4.5
V,"
45
0.5
0.5
0.5
1.35
1.35
1.35
to
1.8
1.8
1.8
5.5
1.9
1.9
1.9
V"
4.4
4.4
or
5.9
5.9
5.9
V,"
3.98
3.84
3.7
or
5.48
5.34
5.2
VH •
or
-6
(Bus Driver)
V,"
-7.8
4.5
V"
Va'
CMOS Loads
or
0.02
4.5
V,"
0.1
0.1
0.1
V"
0.1
0.1
0.1
or
0.1
0.1
0.1
V"
0.26
0.33
0.4
or
(Bus Driver)
V,"
Input Leakage
Vee
CUrrent
or
4.5
4.4
4.5
3.98
0.8
4.4
0.8
V
4.4
V
or
0.26
0.33
0.4
V,"
±0.1
±1
±1
Any
Voltage
Between
-
-
3.84
0.1
4.5
-
3.7
V
0.1
0.1
V
0.4
V
±1
±1
fJA
80
160
fJA
V"
V"
TTL Loads
0.8
V"
TTL Loads
Output Voltage
V
4.5
4.4
V"
Low-Level
Min Typ Max Min Max Min Max
4.5
7.8
-
4.5
-
0.26
5.5
-
±0.1
-
0.33
-
Vee
& Gnd
Gnd
Quiescent
Vee
Device
or
Current
Additional
Quiescent
Device Current
per input pin:
1 unit load
~
Icc
160
Gnd
or
5.5
Gnd
4.5
Vcc-2.1
V"
leakage
or
10'
to
100 360
-
450
-
490
fJA
-
-
±S.O
-
±1O
fJA
5.5
Icc
3-State
Current
Vee
80
V,"
Va - Vee
or
Gnd
-
:to.S
-
:':5.0
-
±1O
V"
or
5.5
00.5
V,"
*For dual-supply systems theoretical worst case (VI = 2.4 V. Vee = 5.5 V) specification is 1.8 rnA.
______________________________________________________________________ 375
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC354, CD54/74HCT354
CD54/74HC356, CD54/74HCT356
HCT354 Input Loading Table
HCT356 Input Loading Table
Input
Unit Loads·
Input
Unit Loads·
00-07
SO,S1,S3
0.50
0.70
0.80
0.25
0.25
0.60
00-07
SO,S1,S3
OE1, OE2
OE3
LE
CP
0.50
0.70
0.80
0.25
0.25
0.60
00, <'m!
OE3
LE
E
'Unit Load is ll.lcc limit specified in Static Characteristic
Chart, e.g., 360JlA max. @25°C.
'Unit Load is ll.lcc limit specified in Static Characteristic
Chart, e.g., 360 JlA max. @ 25° C.
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Input t" tf = 6 ns) -
HC/HCT354
TYPICAL
54174HC
54174HCT
CHARACTERISTIC
CL
(pF)
SYMBOL
Propagation Delay
Dn-V,V
15
t pLH • t pHL
18
20
ns
UNITS
E-V,V
15
t pLH • t pHL
21
23
ns
Sn-V, V
15
t PlH , t pHL
22
25
ns
LE -V, V
15
t PLH , t pHL
24
25
ns
Output Disabling Time
15
t pLZ ,
13
13,16
ns
Output Enabling Time
15
t pZL • t PZH
12,13
14
ns
CPD
90
92
pF
-
Power Dissipation Capacitance'
tpHz
'C PD is used to determine the dynamic power consumption, per device.
Po =Vce' f, (C PD + Cd where:
f; = input frequency,
C L = output load capacitance.
Vee = supply voltage
PREREQUISITE FOR SWITCHING FUNCTION - HC/HCT354
CHARACTERISTIC
E pulse width
SYMBOL
t plH
t pHL
LE pulse width
t pLH
t pHl
Set Up Times
Dn-E"
tsu
Sn-LE
tsu
Hold Times
Dn-E"
tH
Sn-LE
tH
Vee
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-40°C to +85°C
-55°C to +125°C
25°C
54HC
UNITS
HC
HCT
74HC
74HCT
54HCT
Min. Max. Min. Max. Min. Max. Min, Max. Min. Max. Min. Max.
120 80
100 24
24
ns
16
16
20
20
20
14
17
100 120 80
ns
16
20
20
24
24
16
14
17
20
50
65
75
ns
10
13
13
15
15
10
11
13
9
75
65
50
10
13
15
15
ns
10
13
11
13
9
70
45
55
14
11
11
14
ns
9
9
12
9
8
70
45
55
11
11
14
14
ns
9
9
12
9
8
-
376 ______________________________________________________
Technical Data
CD54/74HC354, CD54/74HCT354
CD54/74HC356, CD54/74HCT356
SWITCHING CHARACTERISTICS (CL = 50 pF, Input t" t, = 6 ns) -
CHARACTERISTIC
Propagation Delay.
Dn-Y, Y
E-Y,Y
Sn_y,Y
SYMBOL
Vee
t Pl.H
2
45
6
2
45
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
t PHL
t pLH
t pHL
t pLH
tPHL
LE -Y, Y
Output Disabling
Time
OEn to Y, Y
t plH
t pHL
t PLZ
tPHz
OE3 to Y, Y
Output Enabling
Time
OEn to Y, Y
t PZl
t PZH
OE3 to Y,Y
Output
Transition Time
hLH
tTHL
HC/HCT354
-55°C to
25°C
-40° C to +85° C
HCT
54HC
HC
74HC
74HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
315
210
265
_. 47 59
42
53
63
45
54
36
315
250
375
54
63
68
75
50
-54
64
43
325
390
260
65
74
78
52
59
-44
55
66
- 365 435
290
73
79
87
58
63
-62
74
49
195
235
155
41
39
47
33
31
33
40
26
195 235
155
39
47
31
49
39
33
40
26
190 225
150 43
45
34
38
30
38
33
26
240
200
160 48
40
43
34
32
41
34
27
90
75
60
18
15
15
12
12
15
13
10
+125°C
UNITS
54HCT
Min. Max.
-
-
-
-
-
71
-
-
-
-
-
81
-
-
-
-
-
89
-
-
-
-
-
94
-
-
-
-
-
50
.-
-
-
-
-
59
-
-
-
-
-
51
-
--
-
-
-
51
ns
ns
ns
ns
ns
ns
-
-
-
18
ns
Input
Capacitance
C,
-
10
-
10
-
10
-
10
-
10
-
10
pF
3-state
Output
Co
-
20
-
20
-
20
-
20
-
20
-
20
pF
Capacitance
SWITCHING CHARACTERISTICS (Vee
= 5 V, TA = 25°C,
Input t" t,
= 6 ns) -
HC/HCT356
TYPICAL
54174HC
54174HCT
CHARACTERISTIC
CL
(pF)
SYMBOL
Propagation ~Iay
CP -Y, Y
15
t plH , t pHL
22
22
ns
Sn-Y,Y
15
t plH • t pHL
22
25
ns
LE -Y, Y
15
t pLH • t pHL
24
25
ns
Output Disabling Time
15
t PLZ , t pHZ
13
13,15
ns
Output Enabling Time
15
t PZL • t PZH
12,13
14
ns
Power Dissipation Capacitance'
-
Cpo
51
52
pF
UNITS
*C PD is used to determine the dynamic power consumption, per device.
P D = Vee' I,(C PD + Cd where:
f, = input frequency.
C L = output load capacitance.
Vee = supply voltage.
____________________________________________________________________ 377
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC354; CD54/74HCT354
CD54/74HC356, CD54/74HCT356
PREREQUISITE FOR SWITCHING FUNCTION - HC/HCT356
CHARACTERISTIC
CP Pulse Width
LE Pulse Width
SYMBOL
t pLH
t pHl
t plH
t pHL
Set Up Times
Dn-CP
tsu
Sn -LE
tsu
Hold Times
Dn-CP
Sn -LE
th
th
Vee
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
SWITCHING CHARACTERISTICS (C L
CHARACTERISTIC
Propagation Delay:
CP -V, V
Sn-V,Y
LE -V,Y
Output Disabling
Time
OE1,OE2toV,Y
OE3to V, V
Output Enabling
Time
OE1, OE2 to V, Y
OE3toV, V
Oulpul
Transition Time
Input
Capacitance
3-state
Output
Capacitance
SYMBOL
t pLH
t PHL
t PLH
t pHL
t plH
t pHL
tPLZ
t pHZ
tPZl
t plH
IrLH
IrHL
0
_40° C 10 +85° C
-55°C 10 +125°C
25°C
74HC
HC
HCT
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
80
100 120 16
20
20
25
24
ns
30
14
17
20
100 80
120 16
20
20
25
24
30
ns
14
17
20
5
5
5
11
5
7
5
9
5
ns
5
5
5
5
5
5
5
7
5
9
5
11
ns
5
5
5
70
45
55
11
11
14
14
ns
9
9
9
12
8
60
75
90
12
12
15
15
18
18
ns
10
13
15
-
50 pF, Inpull .. I, = 6 ns) - HC/HCT356
Vee
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4,5
6
-55°C 10 +125°C
25°C
-40°C 10 +85°C
HC
54HCT
UNITS
54HC
74HCT
HCT
74HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
385
- 255 - 320 ns
77
77
51
51
64
64
43
54
65
260 325 390
89
ns
74
78
52
59
65
44
55
66
365 435
290 94
ns
87
73
79
58
63
74
62
49
195 235 - 155 47
50
39
41
31
33
40
33
26
ns
235 195 - 155 56
46
47
37
39
31
40
33
26
225
190 150 51
45
43
34
38
30
38
33
26
ns
- 240 200 160 51
48
40
43
34
32
41
34
27
90
60
i5
15
18
12
18
ns
12
15
_. 15
10
13
-
-
-
-
-
-
-
-
-
-
-
C,
-
10
-
I 10
-
10
-
10
-
10
-
10
pF
Co
-
20
-
20
-
20
-
20
-
20
-
20
pF
37.8 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Technical Data
CD54/74HC354, CD54/74HCT354
CD54/74HC356, CD54/74HCT356
r.=~""",,+----INPUT
LEVEL
92CS- 36986RI
92CS-36985R2
54174HC
54/74HCT
Input Level
Vee
3V
Vs
50% Vee
1.3 V
Fig. 1 - Transition times and propagation delay times.
OTHER {
IN PUTS
TIED HIGH
OR LOW
I.e
OUTPUT RL =Ikn ~Vcc FOR tpLZ AND 'pZL
WITH
3-STATE
OUTPUT
lGND FOR IpHZ AND I PZH
.;;);
OUTPUT
C~OPF
DISABLE
92CS-35129RI
Fig. 2 -
Three~state
propagation delay test circuit.
_________________________________________________________________ 379
Technical Data ___________________________________________________________
CD54/74HC365, CD54/74HCT365
CD54/74HC366, CD54/74HCT366
File Number 1539
High-Speed CMOS Logic
FUNCTIONAL DIAGRAM
AND TERMINAL ASSIGNMENT
-,
0"
Hex Buffer/Line Driver, 3-State
Non-Inverting and Inverting
,A
6A
Type Features:
• Buffered Inputs
• High Current Bus Driver Outputs
• Typical Propagation Delay tPLH, tpHL = 8 ns @ Vee = 5 V,
T,,=25°C
.
12 !lA
'0
9
4Y
CL
= 15 pF,
92C5-37699
cD54n4LH~C~3-6",5--',HCT365
The RCA-CD54174HC365/366 and CD54174HCT365/366
silicon gate CMOS 3-STATE buffers are general purpose
high speed non-inverting and inverting buffers. They have
high drive current outputs which enable high speed
operation even when driving large bus capacitances. These
circuits possess the low power dissipation of CMOS
circuitry, yet have speedscomparableto low power Schottky
TTL circuits. Both circuits are capable of driving up to 15
low power Schottky inputs.
Family Features:
•
•
•
•
The CD54174HC, HCT365 are non-inverting buffers,
whereas the CD54174HC, HCT366 are inverting buffers.
These devices have two 3-State control inputs (OE1 and
OE2) which are NORed together to control all six gates.
•
•
The CD54174HCT365 and CD54174HCT366 logic families
are speed, function, and pin compatible with the standard
54LS174LS logic family.
•
The CD54HC365/366 and CD54HCT365/366 are supplied
in 16-lead hermetic dual-in-line packages (F suffix). The
CD74HC365/366 and CD74HCT365/366 are supplied in 16lead dual-in-line plastic packages (E suffix) and in 16-lead
dual-in-line surface mount plastic packages (M suffix).
Both types are also available in chip form (H suffix).
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85 0 C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to
LSTTL Logic ICs
Alternate Source is PhilipslSignetics
CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 30%, MH = 30%; @ Vee = 5 V
CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, :5 1 pA @ VOL, VOH
FUNCTIONAL DIAGRAM
AND TERMINAL ASSIGNMENT
CD54/74HC366, HCT366
380 ___________________________________________________________________
_____________________________________________________________ TechnicaIOata
CD54/74HC365, CD54/74HCT365
CD54/74HC366, CD54/74HCT366
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ............. , ........................................................................ -0.5 to +7 V
DC INPUT DIODE CURRENT, 11K (FOR VI < -0.5 V OR VI > Vee +0.5 V) ...................................................... ±20 rnA
DC OUTPUT CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) .......................................................... ±20 rnA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vce +0.5 V) .................................................... ±35 rnA
DC Vee OR GROUND CURRENT, PER PIN (Icc): ........................................................................... ±70 rnA
POWER DISSIPATION PER PACKAGE (Po):
For TA; -40 to +60°C (PACKAGE TYPE E) ............................................................................... 500 mW
ForTA; +60 to +B5°C (PACKAGE TYPE E) .................................................. Derate Linearly at B mWrC to 300 mW
For TA; -55 to +100° C (PACKAGE TYPE F, H) ........................................................................... 500 mW
For TA; +100 to +125°C (PACKAGE TYPE F, H) ............................................ Derate Linearly at B mW/oC to 300 mW
ForT.; -40 to +70°C (PACKAGE TYPE M) .............................................................................. 400 mW
For T. ; +70 to +125° C (PACKAGE TYPE M) ................................................. Derate Linearly at 6 mW/o C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F. H ............................................................................................. -55 to +125°C
PACKAGE TYPE E. M ............................................................................................. -40 to +B5°C
STORAGE TEMPERATURE (Tstg) ................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ........................................................ +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ..................................................................................... +300° C
TRUTH TABLES
r - - ONEoFsiX iDENTICAL CIRCUITS -
I
Inputs
Outputs
---
-OE2
A
Y
L
L
L
H
X
L
L
H
H
X
L
H
Z
Z
OE1
X
X
I A (}----,'r----i
, __ ,
I
>-';--~-I_____
IV
OE I 0-<[:>-1'
4
2A0---f' - - - - -
CD54/74HC, HCT365
--~2Y
_ _ _ _ _ _ _ ..J
3A6--r -- -----W3Y
..---L ______ -1
Inputs
r-------,
~
9
4 Au---<________ J~4V
Outputs
~
r-- -----,
"
_______ ...I~5V
OE1
OE2
A
Y
5A~
L
L
L
H
H
X
H
L
Z
Z
6A
X
L
L
H
X
X
O-r- - - - - - ---'~6Y
----------.!
* INVERTER
92CM-3770IRI
NOT I NCLUDEO IN
HC/HCT365
CD54/74HC, HCT366
L = LOW voltage level
H = HIGH voltage level
X = Don't Care
Z = High impedance (off) state
Fig. 1 - Logic diagram for the HC/HCT365 and HC/HCT366.
(Outputs for HC/HCT365 are complements of those shown,
i.e., lY, 2Yetc.)
_______________________________________________________________________ 381
Technical Data ___________________________________________________________
CD54/74HC365, CD54/74HCT365
CD54/74HC366, CD54/74HCT366
STATIC ELECTRICAL CHARACTERISTICS
CD74HC365/366/CD54HC365/366
TEST
74HC/54HC
CONDITIONS
TYPE
CD74HCT365/366/CD54HCT365/366
74HC
TYPE
54HC
TEST
74HCT154HCT
74HCT
TYPE
CONDITIONS
TYPE
TYPE
-401
-551
+125°C
+25°C
-401
+85°C
54HCT
TYPE
CHARACTERISTIC
UNITS
+25°C
V,
V
10
mA
+85 D C
V"
V
V,
V
Vee
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
V,"
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
YO"
CMOS Loads
or
-0.02
V,"
2
1.5
-
-
1.5
-
1.5
4.5
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
4.5
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
-
-
3.84
-
3.7
-
or
(Bus Driver)
V,"
-7.8
6
5.48
-
-
5.34
-
5.2
-
V,"
2
-
-
0.1
-
0.1
-
0.1
V"
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
V"
V,"
V"
or
6
4.5
-
-
0.26
-
0.33
-
0.4
or
(Bus Driver)
VI~i
7.8
6
-
-
0.26
-
0.33
-
0.4
V,"
6
-
-
±O.1
-
±1
-
±1
Voltage
Between
Vee
I,
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
033
-
0.4
V
5.5
-
-
±O.1
-
±1
-
±1
/lA
5.5
-
-
8
-
80
-
160
/lA
to
V"
TTL Loads
Input Leakage
-
V"
3.98
Current
2
V"
4.5
CMOS Loads
-
5.5
-6
or
-
4.5
-
or
Voe
2
to
5.5
V"
Output Voltage
+125°C
Min Typ Max Min Max Min Max
-
TTL Loads
Low-Level
-551
Any
or
Vee
Gnd
Quiescent
Vee
Device
or
Current
Icc
& Gnd
Vee
0
6
-
-
8
-
80
-
160
or
Gnd
Gnd
Additional
4.5
Quiescent
Device Current
per input pin:
1 unit load
fl Icc
3-State
Leakage
Current
10'
Vc c- 2.1
to
-
100
360
-
450
-
490
/lA
-
-
:to.S
-
±5.0
-
±10
/lA
5.5
V"
Vo - Vee
or
or
Gnd
V,"
6
-
-
:to.S
-
±S.O
-
V"
±10
or
5.5
V,"
"For dual·supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
Unit Loads *
OE1
All Others
0.6
0.55
*Unlt Load IS .6. Icc limit specified
In
StatIc Characteristic Chart,
382 __________________________e_.9_,_.3_6_0_/l_A_m_a_x_,_@_2_5_oC__, ____________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC365, CD54/74HCT365
CD54/74HC366, CD54/74HCT366
RECOMMENDED OPERATING CONDITIONS:
For maximum reliabilily, nominal operating conditions should be selected so Ihal operation is always wilhin
Ihe following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA - Full Package-Temperature Range) Vee:"
CD54/74HC Types
CD54174HCT Types
DC Input or Output Voltaqe V" Va
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t" tf
at2V
at 4.5 V
at6V
..
"Unless otherwise specified, all voltages are referenced to Ground.
SWITCHING CHARACTERISTICS (vee =5 V, Cl =15 pF, TA =25°C, Inpul Ir, If
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
V
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
V
=6 ns)
TYPICAL
CHARACTERISTIC
SYMBOL
365
Propagation Delay
366
HC
HCT
HC
HCT
8
9
9
11
tPHL
tpLH
Data to Output
Output Enable and Disable to Outputs
tPZH, tpZL. tPHZ. tPLZ
Cpo
Power Dissipation Capacitance"
SWITCHING CHARACTERISTICS (Cl
12
14
12
14
ns
42
40
42
pF
=supply voltage.
Vee
=50 pF, Inpul Ir, II =6 ns)
_40° C 10 +85° C
25°C
SYMBOL
ns
40
" Cpo is used to determine the dynamic power consumption, per buffer.
Po = Vee'fi (Cpo + CL) where: fi = input frequency. CL =output load capacitance.
CHARACTERISTIC
UNITS
Vee
HC
74HC
HCT
-55° C 10 +125° C
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay
Data to Outputs
105
4.5
-
18
-
110
-
22
60
-
6
-
26
IrLH
2
-
trHL
4.5
-
12
-
12
6
-
10
-
C,
-
10
-
Co
-
20
-
tpLH
2
tPHL
4.5
HC/HCT365
6
Propagation Delay
tPLH
2
Data to Outputs
tpHL
4.5
HC/HCT366
6
Propagation Delay
tpZH ,
tPZL.
Output Enable and
Disable to Outputs
Output Transition
Time
Input Capacitance
3-State Output
Capacitance
2
21
19
150
30
tPHZ, tpLZ
-
25
-
-
130
-
-
-
160
26
31
-
32
22
-
-
-
44
-
-
140
27
-
28
-
-
24
-
-
190
35
-
38
-
-
33
-
10
-
20
-
-
34
-
-
-
225
-
45
27
165
33
28
38
ns
-
41
ns
-
-
53
38
-
-
90
-
-
18
-
18
-
-
15
ns
75
-
-
15
15
-
-
10
-
10
-
10
-
10
pF
20
-
20
-
20
-
20
pF
13
ns
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 383
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC365, CD54/74HCT365
CD54/74HC366, CD54/74HCT366
OUTPUTS
CONNECTED
OUTPUTS
CONNECTED
92CS- 37703
92CS-37702
54/74HC
54/74HCT
Vee
3V
50% Vee
1.3 V
Input Level
SWitching Voltage. Vs
Fig. 2 - Transition times and propagation delay times.
OTHER {
IN PUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
Ie
WITH
OUTPUT RL "Ikn jVCC FOR I PLZ AND tpZL
GND FOR t PHZ AND I PZH
3-STATE
OUTPUT
.;tC}OPF
92CS-37034RI'
Fig. 3 - Three-stage propagation delay test circuit.
384 __________________________________________________
____________________________________________________________ TechnicaIOata
File Number
CD54/74HC367, CD54/74HCT367
CD54/74HC368, CD54/74HCT368
1538
Advance Information!
Preliminary Data
High-Speed CMOS logic
FUNCTIONAL DIAGRAM
Hex Buffer/Line Driver, 3-State
15
6"E2
13
6'1'
Type Features:
I 2.
~A
II
5'1'
10
4A
•
•
•
•
Non-Inverting and Inverting
Buffered inputs
High current bus driver outputs
Two independent 3-state enable controls
Typical propagation delay t pHl. t plH =8 ns @ Vee =5 V, CL = 15 pF
9 "
CD54174HC367, HCT367
The RCA-CD54174HC367, 368 and CD54174HCT367, 368
silicon gate CMOS 3-state buffers are general-purpose
high-speed non-inverting and inverting buffers. They have
high drive current outputs which enable high-speed operation even when driving large bus capacitances. These
circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky
TTL circuits. Both circuits are capable of driving up to 15
low power Schottky inputs.
The CD54174HC, HCT367 are non-inverting buffers, whereas the CD54174HC, HCT368 are inverting buffers. These
devices have two output enables, one enable (OE1) controls
4 gates and the other (OE2) controls the remaining 2 gates.
The CD54174HCT367 and CD54174HCT368 logic families
are speed, function, and pin compatible with the standard
54LS174LS logic family.
The CD54HC367 and CD54HCT367 are supplied in 16-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC367 and CD74HCT367 are in 16-lead dual-in-line
plastic packages (E suffix), also in 16-lead dual-in-line
surface mount plastic packages (M suffix). Both types are
also available in chip form (H suffix).
Family Features:
•
•
•
•
•
•
•
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85 0 C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to
LSTTL Logic ICs
Alternate Source is Philips/Signetics
CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 30%, MH = 30%; @ Vee = 5 V
CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LS TTL Input Logic Compatibility
V'L = 0.8 V Max., V'H = 2 V Min.
CMOS Input Compatibility
I,c, I'H :S 1 I1A @ VOL, VOH
FUNCTIONAL DIAGRAM
""
"
" "
""
"
9
.,
CD54174HC368, HCT368
_________________________________________________________________ 385
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC367, CD54/74HCT367
CD54/74HC368, CD54/74HCT368
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground)
" -0.5 to + 7 V
DC INPUT DIODE CURRENT, 11K (FOR V, < -0.5 V OR V, > Vee +0.5V)
..... ±20mA
DC OUTPUT DIODE CURRENT, 10' (FOR Ve < -0.5 V OR Ve > Vee +0.5V)
±20mA
DC DRAIN CURRENT, PER OUTPUT (Ie) (FOR -0.5 V < Ve < Vee + 0.5V)
±35mA
DC Vee OR GROUND CURRENT (Ieel
±70mA
POWER DISSIPATION PER PACKAGE (Po):
For T A = -40 to +60 eC (PACKAGE TYPE E)
... 500 mW
For TA = +60 to +85 e C (PACKAGE TYPE E)
Derate Linearly at 8 mWI"C to 300 mW
For TA = -55 to +100 eC (PACKAGE TYPE F, H)
...... 500 mW
For T, = +100 to-125'C (PACKAGe TYPE F. H)
............
Derate Linearly at 8 mw,ec to 300 mW
For TA = -40 to +70 e C (PACKAGE TYPE M) ............. , ........................................................... 400 mW
For TA
= +70 to +125' C
(PACKAGE TYPE M) ............................................. Derate Linearly at 6 mW/' C to 70 mW
OPERATING TEMPERATURE RANGE (TA)
PACKAGE TYPE F. H .
PACKAGE TYPE E. M
STORAGE TEMPERATURE (T,,,)
............................ .
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in .. 1.59 mm) with solder contacting lead tips only
. -55 to +125 eC
.. -40 to +85' C
-65 to +150 eC
.. +265'C
. ..... +300'C
r - - ON EOFSiX iDENTICAL CIRCUITS:
1---1
IAr....._~-'..J1
TRUTH TABLES
I
1
1
Inputs
OE
L
L
H
I
I
Outputs
3
+--..-0 17
Y
A
L
H
L
H
(Z)
X
CD54174HC, HCT367
Inputs
OE
L
L
H
Outputs
A
L
H
X
CD54174HC, HCT368
Y
H
L
(Z)
L = LOW voltage level.
H = HIGH voltage level.
X = Don't care.
(Z) = High impedance (off) state.
NOT INCLUDED IN
* INVERTER
He/ H CT 367
Fig.
92CS-37706
- Logic diagram for HC/HCT367 and HCIHCT368.
(Outputs for HC/HCT367 are complements of those
shown, i.e., 1 Y, 2Y, etc.).
386 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
___________________________________________________________ TechnicaIData
CD54/74HC367, CD54/74HCT367
CD54/74HC368, CD54/74HCT368
STATIC ELECTRICAL CHARACTERISTICS
CD74HC367/368/CD54HC367/368
CD74HCT367/368/CD54HCT367/368
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
UNITS
CHARACTERISTICS
+25°C
V,
10
V
mA
"ee
V
High-Level
Input Voltage
Low-Level
Input Voltage
1.5
-
High-Level
V"
Vo"
CMOS Loads
or
-0.02
V,"
1.5
-
1.5
3.15
-
3.15
-
4.2
-
4.2
-
-
0.5
1.35
-
1.35
1.8
-
1.8
4.2
2
-
-
0.5
-
1.35
-
1.8
6
Output Voltage
-
6
4.5
V"
Min Typ Ma. Min Max Min Ma.
4.5 3.15
2
V,"
+25°C
V,
Vee
V
V
4.5
-
0.5
-
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5 3.98
-
-
3.84
-
3.7
-
or
-
5.2
-
V,"
V"
V,"
-7.8
6
5.48
-
-
5.34
2
-
-
0.1
-
0.1
-
0.1
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
.-
-
0.1
-
0.1
-
0.1
V,"
V"
V,"
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
IJA
5.5
-
-
8
-
80
-
160
IJA
-
450
-
490
IJA
±0.5 -
±5
-
±10
IJA
to
V"
V"
TTL Loads
or
6
4.5
-
-
0.26
-
0.33
-
0.4
or
(Bus Driver)
V,"
7.8
6
-
-
0.26
-
0.33
-
0.4
V,"
±1
Voltage
Between
Vee and
Any
Input Leakage
Current
-
V"
(Bus Driver)
CMOS Loads
2
V"
-6
or
-
5.5
or
Vo,
-
4.5
V"
Output Voltage
2
to
5.5
TTL Loads
Low-Level
Min Typ Max Min MOl Min Max
"
Vee
or
Gnd
6
-
-
±0.1 -
±1
-
Gnd
Quiescent Device
Current
lee
Vee
or
Gnd
0
6
-
-
8
-
80
-
Vee
or
Gnd
160
Additional
4.5
Quiescent Device
Vee -2.1
Current per
Input Pin:
1 Unit Load
-
5.5
-
100 360
Alec
3-State
Leakage
Current
to
5.5
loz
Va=
V"
or
Vee
V,"
rGnd
6
-
-
±0.5 -
±5
-
±10
V"
or
-
V,"
-For dual-supply systems theoretical worst CBse (VI = 2.4 V. Vee = 5.5 V) specification is 1.8 rnA.
HCT INPUT LOADING TABLE
INPUT
OE1
ALL OTHERS
UNIT LOADS·
0.6
0.55
'Unit Load is Ll.lcc limit specified in Static Characteristic
Chart, e.g., 360llA max. @ 25 0 C.
_________________________________________________________________ 387
Technical Data ______________________________________________________________
CD54/74HC367, CD54/74HCT367
CD54/74HC368, CD54/74HCT368
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation Is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA-Full Package Temperature Range)
Vee:'
CD54/74HC Types
CD54174HCT Types
DC Input or Output Voltage V,. Vo
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t,.t,
at 2 V
at 4.5 V
at 6 V
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vec
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
V
V
'Unless otherwise specified. all voltages are referenced to Ground.
SWITCHING CHARACTERISTICS (Vcc=5 V, CL=15 pF, TA=25°C, Input t"t,=6 ns)
TYPICAL
CHARACTERISTIC
SYMBOL
367
Propagation Delay
HCT
HC
HCT
8
9
9
11
ns
12
14
12
14
ns
40
42
40
42
pF
tPlH
Output Enable and Disable to Outputs
tPZH. tPZL. bHZ, tpLZ
Power Dissi pation Capacitance'
IS
HC
tpHL
Data to Output
·C PD
UNITS
368
Cpo
used to determine the dynamic power consumption, per buffer.
PD =Vec' f, (Cpo + CLl where:
fl = input frequency
CL = output load capacitance
Vee = supply voltage
SWITCHING CHARACTERISTICS (CL=50 pF, Input t"t,=6 ns)
CHARACTERISTIC
Propagation Delay
Data to Outputs
HC/HCT367
Propagation Delay
Data to Outputs
HC/HCT368
Propagation Delay
Output Enable & Disable
to Outputs
Output Transition
Time
I nput Capacitance
3-State Output
Capacitance
SYMBOL Vce
tPLH
tPHl
tPLH
tPHL
tPZH.
t pZL ,
tPHZ, tpLZ
tTLH
trHl
C,
Co
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
_40° C to +85° C
-55° C to +125°C
25°C
74HCT
54HC
54HCT UNITS
HC
HCT
74HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
105 130 160 ns
21
25
26
31
32
38
24
18
27
105 160 130 30
38
ns
26
45
21
32
24
18
27
190 225 150 ns
44
35
38
45
30
53
26
33
38
75
90
60
ns
15
18
12
12
15
18
13
15
10
pF
10
10
10
10
10
10
-
20
-
20
-
20
-
20
-
20
-
20
pF
388 _________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC367, CD54/74HCT367
CD54/74HC368, CD54/74HCT368
If =6n5
-
-
90%
--Vs
-----
---10%
90%
OUTPUTS
CONNECTED
OUTPUTS
CONNECTED
92C5-37708
92CS-37707
Input Level
Switching Voltage, Vs
Fig. 2 - Transition times and propagation delay times.
OTHER {
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
Ie
OUTPUT RL=lkn
WITH
3-STATE
OUTPUT
lVCC
FOR IPLZ AND tpZL
GNO FOR t PHZ AND I PZH
~C}OPF
92CS-37034RI
Fig. 3 - Three-state propagation delay test circuit.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 389
Technical Data
CD54/74HC373, CD54/74HCT373
CD54/74HC573, CD54/74HCT573
File Number
1679
HighuSpeed CMOS Logic
00
QO
01
QI
02
Q2
03
Q3
04
Q4
05
Q5
06
Q6
07
Q7
IT
liE
Octal Transparent Latch, 3 State Output
n
Type Features:
•
•
•
•
•
•
92CS- 38583
Common latch enable control
Common 3-state output enable control
Buffered inputs
3-State outputs
Bus line driving capacity
Typical propagation delay =12 ns @ Vee = 5V, C L = 15 pF, TA = 25 0 C
(Data to Output for HC373)
FUNCTIONAL DIAGRAM
The RCA CD54174HC373/573 and CD54/74HCT373/573
are high speed Octal Transparent Latches manufactured
with silicon gate CMOS technology. They possess the low
power consumption of standard CMOS integrated circuits,
as well as the ability to drive 15 LSTTL devices. The
CD54174HCT373/573 are functionally as well as pin
compatible with the standard 54174LS373 and 573.
The outputs are transparent to the inputs when the latch
enable (LE) is high. When the latch enable (LE) goes low the
data is latched. The output enable (OE) controls the 3-state
outputs. When the output enable (OE) is high the outputs
are in the high impedance state. The latch operation is
independent to the state of the output enable. The 373 and
573 are identical in function and differ only in their pinout
arrangements.
The CD54HC/HCT373/573 are supplied in 20 lead ceramic
dual-in-line packages (F suffix). The CD74HC/HCT373/573
are supplied in a 20-lead plastic dual-in-line plastic package
(E suffix) and in 20-lead surface mount plastic packages
(M suffix). Both types are also available in chip form
(H suffix).
Vee
1 of 8 Identical Circuits
0,
Q,
Common Controls
LE
Vss
IT
LE~
OE~
OE
Fig. 1 - Logic diagram.
DE
92CS-38584RI
Family Features:
•
•
•
•
•
•
•
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85 0 C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to
LSTTL Logic ICs
Alternate Source is PhilipslSignetics
CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity: N,L = 30%, N'H = 30% of Vee;
@ Vee = 5 V
CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, S 1 pA @ VOL, VO H
TRUTH TABLE
Output
Enable
Latch
Enable
Data
Output
L
H
H
H
L
H
L
L
L
L
I
L
L
L
h
H
H
X
X
Z
Note:
X = Don't Care
L = Low voltage level
_ .
Z - High Impedance State
H = High voltage level
I = Low voltage level one set-up time prior to the high to
low latch enable transition
h = High voltage level one set-up time prior to the high
to low latch enable transition
390 _________________________________________________________________
___________________________________________________________ TechnicaIOata
CD54/74HC373; CD54/74HCT373
CD54/74HC573, CD54/74HCT573
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ...................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ....................................................... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo> Vee +0.5 V) ................................................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) .................................................... ±35 mA
DC Vee OR GROUND CURRENT, (Icc):. '" ................................................................................. ±70 mA
POWER DISSIPATION PER PACKAGE (Po):
ForT. =-40 to +60°C (PACKAGE TYPE E) ............................................................................... 500 mW
ForT. = +60 to +85°C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/oC to 300 mW
For T. = -55 to +100°C (PACKAGE TYPE F, H) ........................................................................... 500 mW
ForTA = +100 to +125°C (PACKAGE TYPE F, H) ............................................. Derate Linearly at 8 mWfOC to 300 mW
For T. = -40 to +70°C (PACKAGE TYPE M) .............................................................................. 400 mW
For T. = +70 to +125°C (PACKAGE TYPE M) ................................................. Derate Linearly at 6 mW/'C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H ............................................................................................. -55 to +125°C
PACKAGE TYPE E, M ...............................................................................................-40 to +85°C
STORAGE TEMPERATURE (ToO,) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1132 in. (1.59 ± 0.79 mm) from case for 10 s max ........................................................ +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ..................................................................................... +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within the
following ranges:
LIMITS
CHARACTERISTIC
UNITS
MAX.
MIN.
Supply-Voltage Range (For T. = Full Package-Temperature Range) Vcc:'
CD54114HC Types
CD54114HCT Types
DC Input or Output Voltage V" Vo
2
6
V
4.5
5.5
V
0
Vcc
V
Operating Temperature T.:
CD74 Types
-40
+85
'C
CD54 Types
-55
+125
°C
Input Rise and Fall Times, t" tf
at2 V
0
1000
ns
at 4.5 V
0
500
ns
at6V
0
400
ns
'Unless otherwise specified, all voltages are referenced to Ground.
DE
00
,
20 Vee
2
19 07
DO
18 07
Dl
17 06
01
16 06
02
15 05
D2
14 05
D3
13 D4
03
12 Q4
GND 10
11
C'E
CD54174HC373, CD54/74HCT373
TERMINAL ASSIGNMENT
0.
1
DO
20 Vee
19 00
Dl
18 01
D2
17 02
D3
16 03
D4
15 04
D.
14
D6
13 06
D7
12 07
GNO 10
11
as
LE
CD54174HC573, CD54174HCT573
TERMINAL ASSIGNMENT
_________________________________________________________________ 391
Technical Data
CD54/74HC373, CD54/74HCT373
CD54/74HC573, CD54/74HCT573
STATIC ELECTRICAL CHARACTERISTICS
CD74HC373/CD54HC373
CD74HC573/CD54HC573
CD74HCT373/CD54HCT373
CD74HCT573/CD54HCT573
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
CHARACTERISTICS
UNITS
+25°C
V,
10
V
mA
High-Level
Input Voltage
Vee
V
1.5
-
-
1.5
4.5 3.15
-
-
13.15
2
V,"
6
Low-Level
Input Voltage
V"
Output Voltage
V"
VO"
CMOS Loads
or
-0.02
V,"
4.2
-
4.2
-
2
-
-
0.5
4.5
-
1.35 -
2
1.9
4.5
4.4
-
6
5.9
6
High-Level
Min Typ Max Min
-
1.B
~ax Min· Max
0.5
1.5
3.15
4.2
-
-
V,
Vee
V
V
1.35
1.8
1.8
1.9
-
1.9
-
V"
-
4.4
-
4.4
or
-
-
5.9
-
5.9
-
4.5 ~.98
-
-
3.84
-
3.7
-
or
5.2
-
V,"
V"
V,"
-7.8
6
~.48
-
-
5.34
-
2
0.1
-
0.1
-
0.1
4.5
-
-
0.02
-
0.1
-
0.1
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
-
0.26
-
0.33
-
0.4
or
0.26
-
0.33
-
0.4
V,"
V"
CMOS Loads
V,"
V"
2
-
V
-
-
O.B
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1 -
±1
-
±1
pA
5.5
-
-
-
80
-
160
pA
-
100 360
-
450
-
490
pA
±0.5 -
±5
-
±10
pA
to
V"
TTL Loads
or
6
4.5
-
(Bus Driver)
V,"
7.8
6
-
Input Leakage
Current
-
V"
(Bus Driver)
or
2
V,"
-6
VOL
-
5.5
or
Output Voltage
-
4.5
-
TTL Loads
Low-Level
2
to
5.5
-
V"
Min Typ Max Min Max Min Max
4.5
-
0.5
1.35 -
-
+25°C
Any
I,
Voltage
Vee
or
Gnd
6
-
-
6
-
-
±0.1 -
±1
-
±1
-
80
-
160
Between
Vee and
Gnd
Quiescent Device
Current
Icc
Vee
or
Gnd
a
8
Vee
or
Gnd
8
Additional
4.5
Quiescent Device
Current per
Vee -2.1
1 Unit Load
3-State
to
5.5
Input Pin:
.6.lcc
Leakage
or
Vo=Vc
or
Current
V,"
Gnd
V"
6
-
-
±0.5
-
V"
±5
-
±10
or
5.5
-
-
V,"
=5.SV) specification is 1.8 rnA.
HCT INPUT LOADING TABLE
·For dual-supply systems theoretical worst case (VI:' 2.4 V. Vee
INPUT
UNIT LOADS'
HCT373
HCT573
OE
1.5
1.25
0.4
0.3
I'E
0.6
0.65
• Unit Load is ~Icc limit specified in Static
Characteristics Chart, e.g., 360 fJA max. @ 250 C.
On
392 ____________________________________________________________________
___________________________________________________________ TechnicaIData
CD54/74HC373, CD54/74HCT373
CD54/74HC573, CD54/74HCT573
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25° C, Inpul I" If = 6 ns)
TYPICAL VALUES
CHARACTERISTIC
UNITS
CL
(pF)
HC
HCT
15
12
13
ns
15
14
17
ns
15
14
14
ns
15
12
14
ns
15
12
14
ns
-
51
53
pF
Propagation Delay
Data to an Output (HC/HCT373)
tPLH
(Fig. 3)
tPHL
Data to an Output (HC/HCT573)
tPLH
(Fig. 3)
tPHL
LE to an Output
tPLH
(Fig. 4)
tPHL
Output Enabling Time
tPZL
(Fig. 6, 7)
tPZH
Output Disabling Time
tpLl
(Fig. 6, 7)
tpHZ
Power Dissipation Capacitance (HC/HCT573, 373)
Cpo"
'C po determines the no-load dynamic power consumption per latch. It is obtained by the following relationship;
Po (total power per latch) =Vee' f, (Cpo + Cc) where f, =input frequency,
C L =output load capacitance, Vee = supply voltage
PRE-REQUISITE FOR SWITCHING FUNCTION
LIMITS
CHARACTERISTIC
TEST
CONDITIONS
IT Pulse Width
-55°C to +125°C
UNITS
HC
Vee
V
-40° C to +85° C
25°C
HCT
74HC
74HCT
54HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Set-up Time
tsu
2
50
-
-
-
65
-
Data to LE
573
4.5
10
-
13
-
13
-
16
-
6
9
-
-
-
11
-
-
-
13
-
-
-
65
-
-
-
75
-
13
-
13
16
-
15
-
11
-
-
13
tw
(Fig. 3)
(Fig. 4)
54HCT
2
80
4.5
16
6
14
-
-
-
100
-
-
16
-
20
-
20
-
-
17
-
-
120
-
-
-
24
-
24
-
20
-
-
75
15
-
-
20
-
-
-
-
-
Set-up Time
tsu
2
50
Data to LE
(Fig. 4)
373
4.5
10
-
6
9
-
tH
2
40
-
-
-
50
-
-
-
60
573
4.5
8
-
10
-
10
-
13
-
12
-
6
7
-
-
9
-
-
-
10
-
-
tH
2
5
-
-
-
5
-
-
5
-
-
373
4.5
5
-
10
-
5
-
13
5
-
15
-
6
5
-
-
-
5
-
-
-
5
-
-
-
Hold Time
Data to LE
(Fig. 4)
Hold Time
Data to LE
(Fig. 4)
20
-
-
-
-
-
15
ns
ns
ns
ns
ns
___________________________________________________________________ 393
TechnicaIOata _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC373, CD54/74HCT373
CD54/74HC573, CD54/74HCT573
SWITCHING CHARACTERISTICS (Inpull" I, = 6 ns, CL = 50 pF)
LIMITS
UNITS
HC
Vee
V
_55°C to +125°C
-40°C to +85°C
25°C
TEST
CONDITIONS
CHARACTERISTIC
74HC
HCT
74HCT
54HC
54HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tPLH
2
-
150
-
-
-
190
-
-
-
225
-
-
tPHL
4.5
-
30
-
32
-
38
-
40
-
45
-
48
(Fig. 2) HC/HCT373
6
-
26
-
-
-
33
-
-
-
38
-
-
Data to an
tPLH
2
-
175
-
-
-
220
-
-
-
265
-
-
(Fig. 2)
tPHL
4.5
-
35
-
40
-
44
-
50
-
53
-
60
6
-
30
-
-
-
37
-
-
-
45
-
-
tPLH
2
-
175
-
-
-
220
-
-
-
265
-
-
tPHL
4.5
-
35
-
35
-
44
-
44
-
53
-
53
6
-
30
-
-
-
37
-
-
-
45
-
-
-
190
-
-
-
225
-
-
Propagation Delay
Data to an
HC/HCT573
LE to an
(Fig. 3)
Output Enabling
tPZL
2
-
150
-
-
Time
tPZH
4.5
-
30
-
35
-
38
-
44
-
45
-
53
6
-
26
-
-
-
33
-
-
-
38
-
-
(Figs. 5 & 6)
Output Disabling
tPLZ
2
-
150
-
-
-
190
-
-
-
225
-
-
Time
tPHz
4.5
-
30
-
35
-
38
-
44
-
45
-
53
26
-
-
-
33
-
-
-
38
-
-
-
Time
ns
ns
6
2
-
60
-
-
-
75
-
-
-
90
-
tTHL
4.5
-
12
-
12
-
15
-
15
-
18
-
18
6
-
10
-
-
-
13
-
-
-
15
-
-
C,
-
-
10
-
10
-
10
-
10
-
10
-
10
pF
Co
-
-
20
-
20
-
20
-
20
-
20
-
20
pF
3-State Output
Capacitance
ns
ITLH
(Fig. 2)
Input Capacitance
ns
-
(Figs. 5 & 6)
Output Transition
ns
ns
394 ______________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC373, CD54/74HCT373
CD54/74HC573, CD54/74HCT573
INPUT
92CS-37132
92C5-37133
Input Level
Vs
54174HC
54/74HCT
Vee
3V
50% Vee
1.3 V
54/74HC
54174HCT
Vee
3V
50% Vee
1.3 V
Input Level
Vs
Fig. 2 - Data to On output propagation delays and output
transition times.
Fig. 3 - Latch enable propagation delays.
INPUT
INPUT
LEVEL~
DE
V5
Vs
tpZH
Q"
All Other Inputs
Tied High
tpHZ
r-----~Vw
~Low
OE
INPUT
Q;;""---II
92CS-37135
92C$- 37134
I nput Level
Vs
Input Level
54174HC
54/74HCT
Vee
3V
54174HC
54/74HCT
Vee
3V
Vs
50% Vee
1.3 V
50% Vee
1.3 V
V,
50% Vee
1.3 V
Vw
90% Vee
90% Vee
Fig. 4 - Latch enable prerequisite times.
Fig. 5 - Three-state propagation delays.
OUTPUT
Q
INPUT LEVEL
"
IK
All Other l n p u U F S Vee
Tied High
or Low
50 pF
OE
I.
-=-
OE
INPUT
92CS - 3713 6
54/74HC
54/74HCT
Vee
3V
Vs
50% Vee
1.3 V
V,
50% Vee
1.3 V
Vw
10% Vee
10% Vee
I nput Level
Fig. 6 - Three-state propagation delays.
_____________________________________________________________
395
Technical Data
CD54/74HC374, CD54/74HCT374
CD54/74HC574, CD54/74HCT574
File Number
1663
High-Speed CMOS Logic
DO
00
01
01
02
02
03
03
Octal D-Type Flip-Flop, 3-State
Positive-Edge Triggered
04
04
05
05
Type Features:
06
06
07
07
OE
VCC =20
GND= 10
•
•
•
•
•
CP
92CS -38560
Common 3-State Output Enable Control
Buffered Inputs
3-State Outputs
Bus Line Driving Capability
Typical Propagation Delay (Clock to Q) = 15 ns @ Vee = 5 V, C L = 15 pF,
TA = 25°C
FUNCTIONAL DIAGRAM
The RCA CD54/74HC374/574 and CD54/74HCT374/574
are Octal 0-Type Flip-Flops with 3-State Outputs and the
capability to drive 15 LSTTL loads. The eight edge-triggered
flip-flops enter data into their registers on the LOW to
HIGH transition of clock (CP). The Output Enable (0 E)
controls the 3-state outputs and is independent of the register operation. When Output Enable (OE) is HIGH the outputs will be in the high impedance state. The 374 and 574
are identical in function and differ only in their pinout
arrangements.
The CD54HC/HCT374/574 are supplied in 20-lead ceramic
dual-in-line packages (F suffix). The CD54HC/HCT374/574
are supplied in a 20-lead plastic dual-in-line plastic package (E suffix) and in 20-lead plastic dual-in-line surface
mount plastic packages (M suffix). The CD54HCI
HCT374/574 are also supplied in chip form (H suffix).
Family Features:
•
•
•
•
•
•
•
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85° C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to
LSTTL Logic ICs
Alternate Source is PhilipslSignetics
CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 30%, MH = 30% of Vee; @ Vee = 5 V
CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
VIL =0.8 V Max., VIH =2 V Min.
CMOS Input Compatibility
II:S 1 /JA @ VOL, VOH
HC/HCT574 nOFSIDENTICALCIRcUlTS--- - - - - - - (2, 3, 4, 5, 6, I
CL
CL
7,8,9)
I
-
-- -
---
00-07
HC/HCT374
(3,4,7,8,13,
14,17,18)
I
I
CL
00-07
L _ _ _ _ _ _ _ .,
I
INN
c~ ________CI
L__
I
__ ~_o~ _____ J
HC/HCT374
(2,5,6,9,12,
15,16,19)
TO 7 OTHER FLIP-FLOPS
1_1
r-.....
i'..
Y t
10
i'..
CP~
~
r---....._
r---....._~6E
92CM-38561RI
6E~ OE
Fig. 1- Logic diagram.
396 ____________________________________________________________
Technical Data
CD54/74HC374, CD54/74HCT374
CD54/74HC574, CD54/74HCT574
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) .................................................................................. -0.5 to + 7 V
DC INPUT DIODE CURRENT, 1,. (FOR V, < -0.5 V OR V, > Vee +0.5V) ..................................................... ±20mA
DC OUTPUT DIODE CURRENT, 10 • (FOR Vo < -0.5 V OR Vo > Vee +0.5V) ................................................. ±20mA
DC DRAIN CURRENT. PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V) .................................................. ±35mA
DC Vee OR GROUND CURRENT, PER PIN (Icc) .......................................................................... ±70mA
POWER DISSIPATION PER PACKAGE (Po):
For T A = -40 to +60° C (PACKAGE TYPE E) ........................................................................... 500 mW
For T. = +60 to +85°C (PACKAGE TYPE E) .............................................. Derate Linearly at 8 mW/oC to 300 mW
For T A = -55 to +100° C (PACKAGE TYPE F, H) ........................................................................ 500 mW
For T. - '100 to ' 125°C (PACKAGE TYPE F, H) .......................................... Derate Linearly at 8 mW/oC to 300 mW
For T. = -40 to +70°C (PACKAGE TYPE M) .......................................................................... 400 mW
For T. = +70 to +125°C (PACKAGE TYPE M) .............................................. Derate Linearly at 6 mWI"C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .......................................................................................... -55 to +125°C
PACKAGE TYPE E, M ........................................................................................... -40 to +85°C
STORAGE TEMPERATURE (T..,) ................................................................................. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ...................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in .. 1.59 mm)
with solder contacting lead tips only .................................................................................. +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
MIN.
MAX.
UNITS
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vcc:'
CD54174HC Types
2
6
CD54/74HCT Types
4.5
5.5
DC Input or Output Voltage V" Vo
Operating Temperature TA:
CD74 Types
0
Vcc
CD54 Types
Input Rise and Fall Times t" tf
at 2V
-40
+85
-55
+125
0
1000
at 4.5 V
0
at6V
0
500
400
V
V
·C
ns
'Unless otherwise specified, all voltages are referenced to Ground.
TRUTH TABLE
INPUTS
OUTPUTS
OE
CP
Dn
an
L
L
L
H
.f
H
L
X
H
00
X
Z
.f
L
X
L
H = high level (steady state)
l = low level (steady state)
X =don't care
~ = transition from low to high level
00 =the level of before the
indicated steady-state input
conditions were established.
Z = high impedance
a
HC/HCT374,574
_________________________________________________________________ 397
Technical Data
CD54n4HC374, CD54/74HCT374
CD54/74HC574, CD54/74HCT574
STATIC ELECTRICAL CHARACTERISTICS
CD74HC374/CD54HC374
CD74HCT374/CD54HCT374
CD74HC574/CD54HC574
CD74HCT574/CD54HCT574
TEST
74HC/54HC
74HC
54HC
CONDITIONS
SERIES
SERIES
SERIES
-401
-551
+85°C
+125°C
TEST
CONDITIONS
74HCT/54HCT
74HCT
54HCT
SERIES
SERIES
SERIES
-401
-551
+85°C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
V
10
Vee
V
mA
+25°C
V,
V
Vee
V
Min Typ Max Min Max Min Max
Min Typ Max Min Max Min Max
High-Level
Input Voltage
4.5
V,"
1.5
1.5
1.5
3.15
3.15
3.15
to
4.2
4.2
4.2
5.5
Low-Level
Input Voltage
4.5
V"
High-Level
V"
Output Voltage
or
Vo"
CMOS loads
-002
4.5
V,"
4.5
0.5
0.5
0.5
1.35
1.35
1.35
to
1.8
1.8
1.8
5.5
4.5
1.9
1.9
1.9
V"
4.4
4.4
4.4
or
5.9
5.9
5.9
V,"
3.98
3.84
3.7
or
5.48
5.34
5.2
V,"
TTL Loads
or
-6
(Bus Driver)
V,"
-7.8
Low-Level
4.5
V"
Voe
CMOS loads
or
4.5
0.02
V,"
0.1
0.1
0.1
V"
0.1
0.1
0.1
or
0.1
0.1
0.1
V,"
0.26
0.33
0.4
or
(Bus Driver)
V,"
Input Leakage
4.5
7.8
or
0.26
0.33
0.4
V,"
±O.1
±1
±1
Between
V"
-
or
Vee
Device
or
Current
I"
3.98
4.4
V
-
4.5
-
3.84
0.1
-
3.7
V
0.1
01
V
04
V
4.5
-
0.26
-
0.33
-
5.5
-
±O.1
-
±1
±1
JJA
80
160
JJA
V"
80
6
or
160
5.5
Gnd
Gnd
4.5
Additional
Quiescent
Vcc2.1
Device Current
per input pin:
1 unit load
4.5
4.4
& Gnd
Gnd
Quiescent
4.4
V
Any
Voltage
V"
'Current
4.5
0.8
0.8
V"
V"
TTL loads
0.8
V"
V"
Output Voltage
V
to
100
360
-
450
-
490
JJA
-
±O 5
-
is 0
-
,10
JJA
5.5
1>1"
3-State
V"
Vo = Vee
Leakage Current
or
or
V,
Gnd
V"
-
±O.S
-
±S.O
-
±10
or
5.5
V,"
*For dual-supply systems theoretical worst case (VI - 2.4 V. Vee - 5.5 V) specification IS 1.8 rnA.
HCT Input Loading Table
Unit Loads'
HCT574
HCT374
0.4
0.3
DO-D7
0.75
0.9
CP
0.6
OE
.. 1.3
Unit Load IS t.lcc limit specified In Static Characteristic
Chart, e.g., 360 fJA max. @ 25°C.
Input
.
398
--------------------~--~---------------------------------------
Technical Data
CD54/7 4HC37 4,. CD.54/7 4HCT374
CD54/74HC574, CD54/74HCT574
SWITCHING CHARACTERISTICS (Vee = 5 V, T. = 25° C, Input t" t, = 6 ns)
CHARACTERISTIC
Propagation Delay
Clock to Q
t PlH
TYPICAL
CL
(pF)
HC
HCT
15
15
15
ns
15
11
11
ns
15
12
12
ns
15
60
60
MHz
-
39
47
pF
UNITS
tpHL
Propagation Delay
Output Disable to Q
tpLZ
tpHZ
Propagation Delay
Output Enable to Q
tPZH
Max Clock Frequency
f max
tPZL
Power Dissipation Capacitance
Cpo
.
'C PO is used to determine the dynamic power consumption, per package.
P D = CPD VCC2 1, + "LVcc2 fo C L where
f, = input frequency,
fo = output frequency,
C L = output load capacitance
Vee = supply voltage
PREREQUISITE FOR SWITCHING FUNCTION
CHARACTERISTIC
Maximum Clock
Frequency
Clock Pulse Width
Fig.2
Set-up Time
Data to Clock
Fig. 3
Hold Time
Data to Clock
Fiq.3
f MAX
tw
tsu
tH
Vec
V
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
25°C
-40°C to +85°C
-55°C to
HCT
74HCT
HC
74HC
54HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
4
5
6
30
25
20
30
25
35
29
23
80
100 120 20
16
20
24
16
17
20
14
60
75
90
12
15
18
12
15
10
13
15
5
5
5
5
5
5
5
5
5
5
5
+125°C
54HCT
UNITS
Min. Max.
-
-
20
-
-
-
-
24
-
-
-
-
-
18
-
-
-
5
-
-
-
MHz
ns
ns
ns
___________________________________________________________________ 399
Technical Data
CD54/74HC374, CD54/74HCT374
CD54/74HC574, CD54/74HCT574
SWITCHING CHARACTERISTICS (C L = 50 pF, Input t" tt = 6 ns)
CHARACTERISTIC
Propagation Delay
Clock to Output
Fig. 2
Propagation Delay
Output Disable to Q
Fig.4
Propagation Delay
Output Enable to Q
Fig.4
Output Transition
Time
Fig.2
t pLH
t pHL
t pLZ
t pHZ
t PZL
t PZH
trLH
hHL
Input Capacitance
3-State Output
Capacitance
Vee
V
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
_40° C to +85° C
-55°C to +125°C
25°C
HCT
74HC
74HCT
54HC
54HCT
UNITS
HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
205 165 250 41
41
50
33
50
ns
33
35
28
43
170 205 135 34
28
27
35
41
42
ns
29
35
23
150 190 225 30
38
38
45
45
ns
30
33
38
26
75
90
60
12
15
15
18
12
18
ns
13
15
10
-
C,
-
-
Co
-
-
10
-
10
-
10
-
10
-
10
-
10
pF
20
-
20
-
20
-
20
-
20
-
20
pF
: N PUT
LEVEL
INPUT
LEVEL
'SUIHi--. , - - - -
Vs
92CS - 36954RI
tTHL
54!74HC
Vee
'------'
50% Vee
Fig. 3 - Oata set-up and hold times.
92C5-38404
Fig. 2 - Clock to output delays and clock pulse width.
tr
=6
ns
OE
1
00
DO
01
01
02
02
03
03
GND 10
OUTPUTS
~
DISCONNECTED
OUTPUTS
CONNECTED
92CS-385E;2
54/74HC
Input.Level
Switching Voltage, Vs
Fig. 4 -
VCC
50%VCC
20
19
18
17
16
15
14
13
12
11
Vee
OE
07
DO
07
01
06
02
06
03
05
D'
19
1B
17
16
15
05
05
D'
06
a.
07
CP
GND
CD54/74HC, HCT374 Types
TERMINAL ASSIGNMENT
20
14
13
12
10
11
Vee
00
01
a2
03
a.
05
06
07
CP
CD54174HC, HCT574 Types
TERMINAL ASSIGNMENT
54/74HCT
3V
1.3 V
Transition times and propagation delay times.
400 _______________________________________________________________________
Technical Data
File Number
CD54/74HC377
CD54/74HCT377
1675
High-Speed CMOS Logic
2
DO
01
4
05
06
07
01
Octal D-Type Flip-Flop with Data Enable
6
02
03
04
QO
5
02
9 03
12 04
15
05
16
06
19
07
8
13
14
17
18
CP
VCC"20
E
GNO"O
Type Features:
• Buffered common clock
• Buffered inputs
• Typical propagation delay = 17ns @ CL = 15pF, Vee = 5 V, fA = 25° C
• 60 MHz typical maximum clock frequency
@ Vee = 5 V, CL = 15pF, TA = 25°C
92CS-38471RI
FUNCTIONAL DIAGRAM
The RCA-CD54174HC377 and CD54174HCT377 are octal
D-type flip-flops with a buffered clock (CP) common to all
eight flip-flops. All the flip-flops are loaded simultaneously
on the positive edge of the clock (CP) when the Data
Enable (E) is LOW.
The CD54HC377 and CD54HCT377 are supplied in 20-lead
ceramic dual-in-line packages (F suffix). The CD74HC377
and CD74HCT377 are supplied in 20-lead dual-in-line
plastic packages (E suffix) and in 20-lead dual-in-line
surface mount plastic packages (M suffix). Both types are
also available in chip form (H suffix).
TRUTH TABLE
OPERATING MODE
Load "1"
Load "0"
Hold (do nothing)
CP
~
~
~
X
INPUTS
E
I
I
h
H
Dn
h
I
X
X
H = HIGH voltage level steady state.
h = HIGH voltage level one setup time prior to the LOWto-HIGH clock transition.
L = LOW voltage level steady state
I = LOW voltage level one setup time prior to the LOWto-HIGH clock transition.
X = Don't care .
.J= LOW-to-HIGH clock transition.
OUTPUTS
an
H
L
no change
no change
Family Features:
• Fanout (over temperature range):
Standard outputs - 10 LSTTL loads
Bus driver outputs - 15 LSTTL loads
• Wide operating temperature range:
CD74HCIHCT: -40 to +85° C
• Balanced propagation delay and
transition times
• Significant power reduction compared to
LSTTL logic ICs
• Alternate source is PhilipslSignetics
• CD54HCICD74HC types:
2 to 6 V operation
High noise immunity: ML = 30%, MH=30% of Vee
@ Vee=5 V
• CD54HCTICD74HCT types:
4.5 to 5.5 V operation
Direct LSTTL input logic compatibility
V,L=0.8 V max., V,H=2 V min.
CMOS input compatibility
I, :S 1 IlA @ VOL, V OH
20
00
DO
Vee
19 07
18 07
01
17 06
01
16 06
02
15 05
02
03
03
GND 10
14 IJ5
13 04
12
11
O.
ep
TERMINAL ASSIGNMENT
401
Technical Data
CD54/74HC377
CD54/74HCT377
Cp
00
01
02
03
04
05
06
07
cL
CL
>0---..--0
o
92CL-3857SR1
cL
CL
Flip-Flop Detail
Fig. 1 - Logic diagram.
402 ______________________________________________________________________
Technical Data
CD54/74HC377
CD54/74HCT377
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) .............
. ........... .
DC INPUT DIODE Cl!RRENT, !,K (FOR V, < -0.5 V OR V, > Vee +0.5V)
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V)
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 05V) ...
DC Vee OR GROUND CURRENT (Icc)
POWER DISSIPATION PER PACKAGE (Po):
For T, = -40 to +60°C (PACKAGE TYPE E)
For T, = +60 to +85° C (PACKAGE TYPE E) ..
For T, = -55 to +100° C (PACKAGE TYPE F, H) ........ .
For T, = +100 to +125°C (PACKAGE TYPE F, H)
.. -0.5 to + 7 V
±20mA
±20mA
±25mA
±SOmA
...
Derate Linearly at 8 mW;o C to
. .......
. . . . . .. Derate Linearly at 8 mW;o C to
For T. = -40 to +70°C (PACKAGE TYPE M)
For T. = +70 to +12SoC (PACKAGE TYPE M) ..... .
SOO
300
SOO
300
mW
mW
mW
mW
................ 400 mW
Derate Linearly at 6 mW/o C to 70 mW
OPERATING-TEMPERATURE RANGE (T,):
PACKAGE TYPE F, H ......
. .......... .
PACKAGE TYPE E, M ............ .
STORAGE TEMPERATURE (T".) .......... .
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.S9 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only
... -55 to +125°C
. . . . ... -40 to +85° C
. -65 to +1S0°C
.................... +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vee:*
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V" Vo
Openting Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t" tf
at 2 V
at 4.5 V
at6 V
LIMITS
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
V
V
*Unless otherwise specified, all voltages are referenced to Ground.
--_________________________________________________________________ 403
Technical Data
CD54/74HC377
CD54/74HCT377
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT377/CD54HCT377
CD74HC377/CD54HC377
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPE
TYPE
CONDITIONS
TYPES
TYPE
TYPE
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
V
10
mA
Vee
V
+25°C
V,
V
Vee
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
V"
Low-Level
Input Voltage
V"
High-Level
V"
Output Voltage
or
Va"
CMOS Loads
-0.02
V,"
2
1.5
-
-
1.5
-
1.5
-
4.5
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
Min Typ Max Min Max Min Max
4.5
-
2
-
-
0.5
-
0.5
-
0.5
4:5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
V"
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
3.98
-
-
3.84
-
3.7
-
or
V,"
-5.2
6
5.48
-
-
5.34
-
5.2
-
V,"
2
-
-
0.1
-
0.1
-
0.1
V"
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
or
Vee
CMOS Loads
V,"
V"
TTL Loads
Input Leakage
Current
4
4.5
-
-
0.26
-
0.33
-
0.4
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
6
-
-
±O.1
-
±1
-
±1
Any
Voltage
Between
or
Quiescent
Vee
or
Current
Icc
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
:to. 1
-
±1
-
±1
~A
5.5
-
-
8
-
80
-
160
~A
-
100 360
-
450
-
490
~A
to
& Gnd
Vee
0
6
-
-
8
-
80
-
or
160
Gnd
Gnd
4.5
Additional
Quiescent
Device Current
per input pin:
1 unit load
-
V"
Gnd
Device
2
V"
or
V"
I,
-
V"
4.5
V"
2
5.5
-4
Low-Level
-
4.5
-
or
Output Voltage
-
5.5
V"
TTL Loads
2
to
Vcc-2 .1
to
5.5
Alec
-For dual-supply systems theoretical worst case (VI = 2.4 V. Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
E
CP
All On Inputs
Unit Loads'
1.5
0.5
0.25
'Unit Load is ll.lcc limit specified in Static Characteristic
Chart, e.g., 360 f.1A max. @ 25° C.
404
Technical Data
CD54/74HC377
CD54/74HCT377
SWITCHING CHARACTERISTICS (Vee
=5 V, TA =25°C, Inpul I" I, =6 ns)
Cl
(pF)
CHARACTERISTIC
Maximum Clock Frequency
15
Propagation Delay
CP-.Q
15
Power Dissipation Capacitance'
-
TYPICAL
HC
HCT
SYMBOL
f m .,
t plH
t pHL
Cpo
UNITS
60
50
MHz
14
16
ns
31
35
pF
'CPO is used to determine the dynamic power consumption. per flip flop.
P D =CPD Vee' f, +:l: (C L Vee' fo) where:
f, = input frequency
f, = output frequency
C L = output load capacitance.
Vee = supply voltage.
PREREQUISITE FOR SWITCHING FUNCTION
CHARACTERISTIC
Maximum Clock
Frequency
Clock Pulse
width
Set-up Time
E. Data to CP
Vee
f max
tw
tsu
Hold Time,
Data to CP
tH
Hold Time
EtoCP
tH
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
SWITCHING CHARACTERISTICS (C l
CHARACTERISTIC
Propagation Delay.
CPto Q
Output
Transition Time
hLH
hHL
Input
Capacitance
= 50 pF,
Vee
t pLH
t pHL
C,
25°C
-40°C 10 +85'C
-55'C 10 +125°C
HCT
HC
74HC
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
6
4
5
25
25
30
20
20
16
MHz
29
35
23
80
100 120 16
20
20
25
24
30
ns
14
20
17
60
75
90
12
12
15
15
18
18
ns
13
10
15
3
3
3
3
3
3
3
3
3
ns
3
3
3
5
5
5
5
5
5
5
5
5
ns
5
5
5
-
2
4.5
6
2
4.5
6
Inpul I" I, = 6 ns)
25°C
-40°C 10 +85°C
-55°C 10 +125°C
HC
HCT
74HC
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
175 220 - 265 44
53
ns
35
38
48
57
45
30
37
75
95
110 15
19
15
19
22
22
ns
13
16
19
~-
-
10
-
10
-
10
-
10
-
10
-
10
pF
_________________________________________________________________ 405
Technical Data
CD54/74HC377
CD54/74HCT377
INPUT LEVE
On
On
INPUT LEVEL----..
E
CP
CP
I Input Level
I Switching Voltage, Vs
I
I
I
54174HC
Vee
50% Vee
54174HCT
3V
1.3 V
I
I
I
Fig. 2 - Setup and hold times and propagation delay times.
406 ________________________________________________________________
Technical Data
File Number
CD54/74HC390
CD 54/74HCT390
1838
High-Speed CMOS Logic
Dual Decade Ripple Counter
3(13) nOO
5(11) nOl
S(10)n02
7(9) n03
Type Features:
• Two BCD decade or bi-quinary counters
• One package can be configured to divide-by-2, 4, 5,
10,20,25,50 or 100
• Two master reset inputs to clear each decade
counter individually
FUNCTIONAL DIAGRAM
The RCA-CDS4/74HC390 and CDS4174HCT390 dual4-bit
decade ripple counters are high-speed silicon-gate CMOS
devices and are pin compatible with low-power Schottky
TTL (LSTTL). These devices are divided into fourseparately
clocked sections. The counters have two divide-by-2
sections and two divide-by-S sections. These sections are
normally used in a BCD decade or bi-quinary configuration,
since they share a common master reset (nMR). If the two
master reset inputs (1 MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of
counting configurations are~sible within one package.
The separate clock inputs (nCPO and nCP1) of each section
allow ripple counter or frequency division applications of
divide-by-2, 4, S, 10, 20, 2S, SO or 100. Each section is
triggeredk the HIGH-to-LOW transition of the input
pulses (nCPO and nCP1).
For BCD decade operation, the nOO output is connected to
the nCP1 input of the divide-by-S section. For bi-qui~
decade operation, the n03 output is connected to the nCPO
input and nOO becomes the decade output.
The master reset inputs (1 MR and 2MR) are active-HIGH
asynchronous inputs to each decade counter which operates
on the portion of the counter identified by the "1" and "2"
prefixes in the pin configuration. A HIGH level on the nMR
input overrides the clock and sets the four outputs LOW.
The CDS4HC390 and CDS4HCT390 are supplied in 16-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC390 and CD74HCT390 are supplied in 16-lead
dual-in-line plastic packages (E suffix) and in 16-lead dualin-line surface-mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity: Ml = 30%, MH = 30% of Vee,
@ Vee =5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'l = 0.8 V Max., V'H = 2 V Min.
CMOS Input Compatibility
I, ~ 1 pA @ VOL, VO H
1CPO
'S
Vee
lMR
15
2CPci
lQO
14
2MR
1CP-i
13
200
12
2CP1
6
"10
201
8
9
101
102
103
GNO
202
203
TOP VIEW
92CS-40210
TERMINAL ASSIGNMENT
__________________________________________________________ 407
Technical Data
CD54/74HC390
CD54/74HCT390
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ......................................................................................-0.5 to +7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee + 0.5 V) ....................................................... ±20 rnA
DC OUTPUT DIODE CURRENT, 10K (FOR V. < -0.5 V OR V. > Vee + 0.5 V) ................................................... ±20 rnA
DC DRAIN CURRENT, PER OUTPUT (I.) (FOR -0.5 V < V. < Vee + 0.5 V) .................................................... ±25 rnA
DC Vee OR GROUND CURRENT (lee) ...................................................................................... ±50 rnA
POWER DISSIPATION PER PACKAGE (PD):
For T. = -40 to +SO°C (PACKAGE TYPE E) ............................................................................... 500 mW
For T. = +60 to +85° C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/"C to 300 mW
ForTA = -55 to +100·C (PACKAGE TYPE F, H) ........................................................................... 500 mW
For T. = +100 to +125·C (PACKAGE TYPE F, H) ............................................. Derate Linearly at 8 mW/·C to 300 mW
For T.= -40 to +70° C (PACKAGE TYPE M) ............................................................................... 400 mW
For T.= +70 to +125°C (PACKAGE TYPE M) .................................................. Derate Linearly at 6 mW/·C to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H ............................................................................................. -55 to +125·C
PACKAGE TYPE E, M .............................................................................................. -40 to +85· C
STORAGE TEMPERATURE (T...) .................................................................................... -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 108 max.
.. ................................................... +265·C
Unit inserted into a PC Board (min. thickness 1116 in., 1.59 mm)
with solder contacting lead tips only ..................................................................................... +300·C
4(121
nCP1
Fig. 1 - Logic diagram, one-half of HC/HCT390.
R
L -________________________________
~Q
92CS-40212
Fig. 2 - Flip-flop logic detail.
408 _________________________________________________________________
Technical Data
CD54/74HC390
CD54/74HCT390
RECOMMENDED OPERATING CONDITIONS
For maximum reliability. nominal operating conditions should be selected so that operation Is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA-Full Package Temperature Range)
Vcc:'
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage, V" Va
Operating Temperature, TA:
CD74 Types
CD54 Types
Input Rise and Fall Times, t.,t,:
at 2V
at 4.5 V
at6V
UNITS
MIN.
MAX.
2
4.5
a
6
5.5
Vcc
-40
-55
+85
+125
°C
a
1000
500
400
ns
0
0
V
V
'Unless otherwise specified, all voltages are referenced to Ground.
TRUTH TABLE
INPUTS
ACTION
CP
MR
J
L
NO CHANGE
'--
L
COUNT
X
H
ALL as LOW
H = HIGH voltage level
L = LOW voltage level
X = Don't Care
= LOW-to-HIGH I/> transition
= HIGH-to-LOW I/> transition
BCD COUNT SEQUENCE FOR
1/2 THE "390"
COUNT
0
1
2
3
4
5
6
7
8
9
QO
L
H
L
H
L
H
L
H
L
H
OUTPUTS
Q1
Q2
L
L
L
L
L
H
L
H
L
H
L
H
H
H
H
H
L
L
L
L
Note:
Output nOO connected to nCPl with
counter input on nCPO.
BI-QUINARY COUNT SEQUENCE FOR
1/2 THE "390"
Q3
L
L
L
L
L
L
L
L
H
H
COUNT
0
1
2
3
4
5
6
7
8
9
QO
L
L
L
L
L
H
H
H
H
H
OUTPUTS
Q1
Q2
L
L
H
L
L
H
H
H
L
L
L
L
H
L
L
H
H
H
L
L
Q3
L
L
L
L
H
L
L
L
L
H
Note:
Output n03 connected to nCPO with
counter input on nCP1.
___________________________________________________________________ 409
Technical Data
CD54/74HC390
CD54/74HCT390
STATIC ELECTRICAL CHARACTERISTICS
CD74HC390/CD54HC390
CD74HCT390/CD54HCT390
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CDNDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85'C
+12S'C
+85°C
+125'C
CHARACTERISTIC
UNITS
+25°C
10
Vee
V,
Vee
V
mA
V
V
V
High-Level
Input Voltage
2
V,H
4.2
2
-
4.5
V,L
High-Level
V,L
VOH
CMOS Loads
1.5
6
6
Output Voltage
Min Typ Max Min Max Min Max
4.5 3.15
Low-Level
Input Voltage
or
-0.02
V,H
2
1.9
4.5
4.4
6
5.9
-
-
3.15
-
4.2
-
1.5
-
-
0.5
-
1.35
-
4.4
-
3.84
-
5.34
0.1
-
0.1
0.33
1.8
1.9
5.9
0.5
1.35
1.8
-
1.5
3.15
4.2
1.9
4.4
5.9
-
Low-Level
Output Voltage
-4
V,H
-5.2
6
5.48
2
0.02
4.5
-
-
CMOS Loads
-
0.26
0.26
-
-
±0.1
-
or
V,H
4.5 3.98
6
0.1
0.1
-
-
2
-
V
to
-
-
O.B
-
O.B
-
O.B
V
or
4.5
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
3.7
-
V
V,H
0.1
V,L
0.4
or
0.33
-
0.4
V,H
±1
-
±1
0.1
or
0.1
or
0.1
V,H
4.5 3.98
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
/JA
5.5
-
-
8
-
80
-
160
/JA
-
100 360
-
450
-
490
/JA
VOL
or
4
4.5
V,H
5.2
6
-
6
-
Any
I,
Quiescent
Vee
or
Icc
or
Voltage
Between
Vee & Gnd
Vee
Vee
0
6
-
-
8
-
80
-
160
or
Gnd
Gnd
Additional
4.5
Quiescent Device
Vee -2.1
Current per input
pin: 1 unit load
2
V,L
-
0.1
Gnd
Device Current
-
5.5
V,H
5.2
Input Leakage
Current
-
4.5
-
-
3.7
V,L
TTL Loads
2
V,L
or
V,L
VOL
to
5.5
1.B
-
Min Typ Max Min Max Min Max
4.5
-
0.5
1.35
V,L
TTL Loads
+25°C
V,
to
5.5
Alec·
*For dual-supply systems theoretical worst case (VI
=2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
nCPO
nCP1, MR
Unit Loads·
0.45
0.6
'Unit Load is Alec limit specified in Static Characteristics
Chart, e.g., 360 pA max. @ 25°C.
410 ________________________________________________________________
Technical Data
CD 54/74H C390
CD 54/74H CT390
SWITCHING CHARACTERISTICS (VCC
=5 V, TA =25°C,lnput tr,t, =6 n8)
TYPICAL
CL
(pF)
CHARACTERISTIC
Propagation Delay
HC
HCT
14
15
16
28
17
18
18
32
UNITS
tPLH
tPHL
--
nCPO to 00 Output
nCP1 to 03
MR to an Output
Power Dissipation Capacitance"
15
tPHL
Cpo
-
ns
pF
"Cpo is used to determine the dynamic power consumption. per counter.
PD = Cpo Vee2 fi + 1: (C L Vee' fo> where: fi = input frequency
fo = output frequency
CL = output load capacitance
Vee = supply voltage
PRE-REQUISITE FOR SWITCHING FUNCTION
CHARACTERISTIC
Maximum Clock
Frequency
Clock Pulse Width
nCPO. nCP1
fMAX
tw
Reset Removal Time tREM
Reset Pulse Width
tw
TEST
CONDITIONS
Vec (V)
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
LIMITS
-40° C to +85° C
-55° C to +125° C
UNITS
HCT
74HC
74HCT
54HC
54HCT
HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
5
6
4
27
24
22
20
18
30
28
24
35
100 120 80
19
20
24
24
29
16
14
17
20
ns
105 70
90
19
21
22
15
18
14
18
12
15
75
65
50
16
15
20
13
13
10
11
13
9
25°C
-
-
-
-
-
tpHL
-
-
-
-
-
-
INPUT
92CS-3B370RI
INPUT LEVEL
SWITCHING VOLTAGE, Vs
Fig. 3 - Input pulse pre-requisite. propagation-delay. and
output-transition times.
Fig. 4 - Master-Reset pre-requisite and propagation-delay times.
__________________________________________
~
_____________________ 411
TechnicalOata ____________________________________________________________
CD54/74HC390
CD54/74HCT390
SWITCHING CHARACTERISTICS (Cl
=50 pF, Inpull"t, =6 ns)
LIMITS
CHARACTERISTIC
Propagation Delay.
Time:
nCPO to nOD
VCC
(V)
tPlH
tPHL
--
nCP1 to n01
nCP1 to n02
-
nCP1 to n03
nCPO to n02
(nO~ connected to nCP1}
MR to On
Output Transition
Time
ITlH
Input Capacitance
C,
hHL
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-
25°C
HC
Min. Max.
175
35
30
185
37
31
245
49
42
180
36
31
365
73
62
190
38
32
75
15
13
10
-40°C 10 +85°C
-55° C to +125° C
UNITS
74HCT
HCT
74HC
54HC
54HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
220 265 40
44
50
53
60
37
45
230 280 51
43
46
56
65
48
39
305 370 61
69
74
55
83
52
63
225 270 42
45
53
54
63
ns
38
46
455 550 84
91
105 110 126
94
77
285 240 42
53
57
63
48
41
48
110 95
19
22
22
15
19
16
19
10
10
10
pF
10
10
412 ______________________________________________________________________
Technical Data
File Number
CD 54/74H C393
1653
CD54/74HCT393
High-Speed CMOS Logic
2- 1aO
.2..-<
1MR
.1-
,!lr<
2MR
E.
BINARY
COUNTER
~ 1a 1
~ 1a3
Type Features:
•
•
•
•
•
~
BINARY
COUNTER
Dual 4-Stage Binary Counter
r2- 1a2
~
r-2-
~
Fully static operation
Buffered inputs
Common reset
Negative-edge clocking
TypicalfMAx = 60 MHz@ Vee = 5V, C L = 15 pF, TA = 25°C
GND '7
VCC=14
92CS-38367R2
FUNCTIONAL blAGRAM
The RCA-CD54174HC393 and CD54/74HCT393 are4-slage
ripple-carry binary counters. All counter stages are masterslave flip-flops. The state of the stage advances one count
on the negative transition of each clock pulse; a high
voltage level on the MR line resets all counters to their zero
state. All inputs and outputs are buffered.
The CD54HC393 and CD54HCT393 are supplied in 14-lead
hermetic dual-in-line ceramic packages (F suffix). The
CD74HC393 and CD74HCT393 are supplied in 14-lead
dual-in-line plastic package (E suffix) and in 14-lead dualin-line surface mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
.----1 ~
Family Features:
• Fanout (over temperature range):
Standard outputs - 10 LSTTL loads
Bus driver outputs - 15 LSTTL loads
• Wide operating temperature range:
CD74HCIHCT: -40 to +85' C
• Balanced propagation delay and
transition times
• Significant power reduction compared to
LSTTL logic ICs
• Alternate source is PhilipslSignetics
• CD54HCICD74HC types:
2 to 6 V operation
High noise immunity: N'L = 30%, MH=30% of Vee
@ Vcc=5 V
• CD54HCTICD74HCT types:
4.5 to 5.5 V operation
Direct LSTTL input logic compatibility
V,L =0.8 V max., V'H=2 V min.
CMOS input compatibility
I,N:s 1 /lA @ VOL.. VO H
a 1--......- - ~
a t--~-__; ~
00
01
af---_---j ~
Q
4(10)
Fig. 1 - Logic diagram, one-half of HCIHCT393.
92CM-3836BR3
______________________________________________________________________ 413
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _......,....
CD54/74HC393
CD54/74HCT393
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOL TAGE, (Vee):
(Voltages referenced to ground) , .................... '.' ............................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ....................................................... ±20 rnA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) ................................................... ±20 rnA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) .................................................... ±25 rnA
DC Vee OR GROUND CURRENT, (lee) ..................................................................................... ±50 rnA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60°C (PACKAGE TYPE E) ............................................................................... 500 mW
.For T. = +60 to +85°C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/oC to 300 mW
For T. =-55 to +100°C (PACKAGE TYPE F, H) ........................................................................... 500 mW
For T. = +100 to +125°C (PACKAGE TYPE F, H) ............................................. Derate Linearly at 8 mW/oC to 300 mW
............................................................................. 400 mW
For T. = -40 to +70° C (PACKAGE TYPE M)
For T. = +70 to +125°C (PACKAGE TYPE M)
............................................... Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H ............................................................................................. -55 to +125°C
PACKAGE TYPE E, M ......... '" .................................................................................. C40 to +85° C
STORAGE TEMPERATURE (T".) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
+265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
iNith solder contacting lead tips only ................................................................................... +300° C
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
MIN.
MAX.
UNITS
Supply-Voltage Range (For TA=Full Package Temperature Range)
Vee:*
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage, V" Vo
2
6
4.5
5.5
0
Vcc
V
V
Operating Temperature, T A:
CD74 Types
-40
+85
CD54 Types
-55
+125
at 2 V
0
1000
at 4.5 V
0
500
6V
0
400
°C.
Input Rise and Fall Times, t"t,:
at
'Unless otherwise specified, all voltages are referenced to Ground.
1'CP
14
vce
IMR
13
2CP
IQO
lQI
4
IQ2
lQ3
GND
6
12
2MR
11
2QO
10
2Ql
9
2Q2
2Q3
92CS-38376R3
TERMINAL ASSIGNMENT
414
ns
Technical Data
CD54/74HC393
CD54/74HCT393
STATIC ELECTRICAL CHARACTERISTICS
CD74HC393/CD54HC393
CD74HCT393/CD54HCT393
TEST
74HC/54HC
74HC
54HC
TEST
74t:CT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-40/
-55/
-40/
-55/
-B5°C
+125°C
-B5°C
-125°C
CHARACTERISTIC
UNITS
+25°C
V,
10
Vee
V
rnA
V
High-Level
Input Voltage
V,"
Low-Level
Input Voltage
2
1.5
3.15
~
~
6
4.2
~
~
2
6
High-Level
Output Voltage
V"
Vo"
CMOS Loads
or
-0.02
V,"
~ax Min Max Min Max
4.5
4.5
V"
Min Typ
~
~
~
~
~
~
~
2
1.9
4.5
4.4
6
5.9
~
0.5
1.35
1.8
~
~
~
~
~
~
1.5
~
1.5
~
3.15
~
4.2
~
4.2
~
~
~
1.9
0.5
1.35
1.8
~
4.4
~
5.9
~
~
~
~
19
4.4
5.9
Low-Level
Output Voltage
CMOS Loads
~
~
~
~
2
~
2
~
V
to
~
~
0.8
~
0.8
~
0.8
~
4.4
~
37
~
V
55
V"
or
4.5
4.4
~
~
4.4
4.5
3.98
~
~
3.84
V
V,"
V"
3.98
V,"
-5.2
6
5.48
2
~
~
0.1
~
0.1
~
0.1
V"
0.02
4.5
~
~
0.1
~
0.1
~
0.1
or
~
0.1
~
0.1
~
0.1
V,"
or
2
4.5
~
4.5
6
~
~
~
~
~
3.84
5.34
~
~
3.7
5.2
~
~
V"
or
~
V
V,"
4.5
~
~
0.1
4.5
~
~
0.26
~
~
~
±O.1
~
±1
~
~
8
~
80
360
~
~
0.1
~
0.1
V
~
04
V
~
±1
J1A
160
J1A
490
J1A
V"
or
4
4.5
V,"
5.2
6
~
~
~
0.26
~
0.33
~
0.4
or
~
0.26
~
0.33
~
0.4
V,"
0.1
~
Input Leakage
Current
to
5.5
1.8
~
Min Typ Max Min Max Min Max
4.5
~
-4
V,"
TTL Loads
V
or
V"
Yo,
V
0.5
1.35
V"
TTL Loads
Vee
~
3.15
~
+25°C
V,
0.33
Any
I,
Voltage
Vee
or
6
~
~
±1
~
±1
Gnd
Between
5.5
Vee and
Gnd
Quiescent Device
Current
Icc
Vee
Vee
or
0
6
~
~
8
Gnd
~
80
~
160
or
5.5
~
Gnd
Additional
Quiescent Device
4.5
Current per
Vee -2.1
Input Pin:
1 Unit Load
to
~
100
450
~
5.5
Ll1cc*
-For dual-supply systems theoretical worst case (VI
=2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
Unit Loads'
nCP
nMR
0.4
'Unit load is !lIce limit specified in Static Characteristics
Chart, e.g., 360 JiA max. @ 25° C.
____________________________________________________________________ 415
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD 54/74HC393
CD54/74HCT393
TRUTH TABLES
CP
OUNT
0
"¥
Q
4>
Q
~
Ii"
92CS-38369R2
~
Fig. 2 - Flip-flop logic detail.
OUTPUTS
Q2
Q1
L
L
L
L
L
H
L
H
H
L
L
H
H
H
H
H
L
L
L
L
H
L
H
L
L
H
L
H
H
H
H
H
Q3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
2
3
4
5
6
7
8
9
10
11
12
13
14
15
QO
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
CP
MR
OUTPUT
J
L
NO CHANGE
~
L
COUNT
X
H
L L L L
X = Don't Care
SWITCHING CHARACTERISTICS (Vee
=5 V, TA =25°C, Input t" tf =6 ns)
CHARACTERISTIC
SYMBOL
t PlH
Propagation Delay nCP to nOO Output
t pHL
t pLH
Propagation Delay On to On + 1
HC
15
12
Typical
HCT
Units
13
15
4
4
ns
"t pHL
15
Cpo
-
11
20
13
21
pF
t PHl
Propagation Delay MR to On Output
Power Dissipation Capacitance'
Cl
pF
'CPO is used to determine the power consumption.
PD=Cpo Vee' fi + 1: (Cl Vee' filM) where: M=2' ,2',2',2"
, C l =output load capacitance'
fi=input frequency
Pre-requisite for Switching Function
CHARACTERISTIC
Maximum Clock
Frequency
Clock Pulse Width
Reset Recovery Time
Reset Pulse Width
SYMBOL
fMAX
tw
tREC
tw
VCC
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
25°C
-40°C to +85°C
-55°C to +125°C
HC
HCT
74HC
74HCT
54HC
54HCT UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
4
6
5
MHz
27
24
22
20
18
30
24
35
28
- 100 120 80
16
19
20
24
24
29
14
17
20
5
5
5
ns
5
5
5
5
5
5
5
5
5
120
100
80
-'
24
16
16
20
20
24
20
14
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
416 _ _-~------------------------------
Technical Data
CD54/74HC393
CD54/74HCT393
SWITCHING CHARACTERISTICS (C l =50 pF, Inpul 1,,1,=6 ns )
CHARACTERISTIC
SYMBOL
Propagation Delay
Time:
Qn to Qn+1
t PLH
tPHL
tPLH
nCP to nQO
tPHL
nCP to nQ1
t pHL
tPLH
tPLH
nCP to nQ2
tPHL
nCP to nQ3
t pHL
tpLH
tPLH
MR to Qn
Output Transition
Time
I nput Capacitance
tPHL
hHL
trLH
C,
VCC
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-
-55° C 10 +125° C
25°C
-40°C 10 +85°C
HC
HCT
74HCT
UNITS
74HC
54HC
54HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
45
55
70
12
14
9
11
15
18
12
8
9
150
190
225
26
32
40
45
48
38
26
33
38
195 - 245 - 295 32
49
55
38
59
66
33
42
50
240 300 360 50
48
60
70
72
84
ns
61
41
51
285 430 355
62
57
71
85
86
102
48
60
73
205
135
170
32
40
48
27
41
24
23
35
29
75
- 110 95
15
15
19
19
22
22
19
13
16
10
pF
10
10
10
10
10
INPUT LEVEL
=--~CP
Vs
INPUT
t REC
INPUT
_QO
_ _ _ _- ' /
INPUT LEVEL
INPUT LEVEL
SWITCHING VOLTAGE, Vs
92CS-38370R2
SWITCHING VOLTAGE, Vs
92CS-38371R2
Fig. 3 - Clock pre-requisite, propagation-delay, and
output-transition times.
Fig. 4 - Master-Reset pre-requisite and propagation-delay times.
_____________________________________________________________________ 417
Technical Data
CD54n4HC533, CD54n4HCT533
CD54n4HC563, CD54n4HCT563
File Number
1599
High-Speed CMOS Logic
..
.,'"
..,
Qo
DO
n
D2
Q4
D,
IT
OE
Octal Inverting Transparent Latch,
3-State Outputs
92C5-38341
FUNCTIONAL DIAGRAM
Type Features:
• Common latch-enable control
• Common 3-state output-enable control
• Buffered inputs
• 3-State outputs
• Bus line driving capacity
• Typical propagation delay = 13 ns@ Vee = 5 V, CL
(Data to Output)
The RCA C054174HC/HCT533/563 are high-speed Octal
Transparent Latches manufactured with silicon gate CMOS
technology. They possess the low power consumption of
standard CMOS integrated circuits, as well as the ability to
drive 15 LSTTL devices.
The ou!E!!!s are transparent to the inputs when the latch
enable (LE) is high. When the latch enable (LE) goes low the
data is latched. The output enable (OE) controls the 3-state
outputs. When the output enable (OEj is high the outputs
will be in the high impedance state. The latch operation is
independent of the state of the output enable.
The CD54/74HC533 and C054174HCT533 are identical in
function to the C054/74HC563 and CD54/74HCT563 but
have different pinouts. The C054/74HC533 and CD541
74HCT533 are similar to the C054174HC373 and C0541
74HCT373; the latter are non-inverting ·types.
The CD54HC/HCT533/563 are supplied in 2D-lead hermetic
dual-in-line ceramic packages (F suffix). The C074HCI
HCT533/563 are supplied in 20-lead dual-in-line plastic
packages (E suffix) and in 20-lead dual-in-line surface
mount plastic packages (M suffix). Both types are also
available in chip form (H suffix).
= 15 pF,
TA
= 25°C
Family Features
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +B5°C
• Balanced Propagation and Transition Times
• Significant Power Reduction Compared to
LSTTL Logic ICs
• Alternate Source is Philips/Signetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 30%, MH = 30% of Vee:
@ Vee=5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = O.B V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, ::; 1 pA @ VOL, V OH
VCC
,-----------------------------I
I OF 8 IDENTICAL CIRCUITS
I
On
I
I
OTTOH~R I
CIRCUITS'
I
L _______________ _
LOGIC DIAGRAM
TO 7 OTHER
CIRCUITS
92CM-38342
418 ________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC533, CD54/74HCT533
CD54/74HC563, CD54/74HCT563
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ........... . . . ..... . . ... . ...... . . .. . ..... . ....
. ............ -0.5 to + 7 V
DC INPUT DIODE CURRENT, I,. (FOR V, < -0.5 V OR V, > Vee +0.5 V) .....................
± 20 mA
DC OUTPUT DIODE CURRENT. 10K (FOR Va < -0.5 V OR Va> Vee +0.5 V) ..... _. _
............
± 20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Va < Vee +0.5 V) .
. ... '" ... ...
. ............ ± 35 mA
DC Vee OR GROUND CURRENT (Icc): ................................................................................. ± 70 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60°C (PACKAGE TYPE E) ..........
For TA = +60 to +85°C (PACKAGE TYPE E).
For TA = -55 to +100°C (PACKAGE TYPE F, H) ...
For TA = +100 to +125°C (PACKAGE TYPE F, H)..
. ............. .
. ..
. __ ..... Derate Linearly at 8 mW/oC to
............
. ..
. .. Derate linearly at 8 mW/oC to
500
300
500
300
mW
mW
mW
mW
For TA = -40 to +70°C (PACKAGE TYPE M) ............................................................................. 400 mW
ForTA = +70 to +125°C (PACKAGE TYPE M) ............................................... Derate Linearly at 6 mwrc to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .......... .
PACKAGE TYPE E, M ......... .
STORAGE TEMPERATURE (T",) ......... .
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm) with solder contacting lead tips only
. ... -55 to +125°C
. .. -40 to +85°C
_.... -65 to +150°C
. .. +265°C
....... +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
UNITS
MIN.
MAX.
Supply-Vollage Range (For TA = Full Package Temperalure Range) Vee:'
CD54174HC Types
CD54/74HCT Types
DC Inpul or OUlpul Voltage V ,N , VOUT
2
6
V
4.5
5.5
V
0
Vee
V
Operaling Temperalure T A :
CD74 Types
-40
+85
DC
CD54 Types
-55
+125
DC
al 2 V
0
1000
ns
a14.5 V
0
500
ns
al6 V
0
400
ns
Inpul Rise and Fall Times, I" I,
'Unless olherwise specified, all voltages are referenced 10 Ground.
-
I
00
2
OE
00
02
5
6
16
15
14
02
13
D3
12
OJ
GND
,.
19
17
Dl
Qi
-
20
10
11
Vee
DE
07
DO
D7
D1
D6
D2
06
Os
D3
D5
D5
D4
D6
20
19
,. Qi
D4
04
D7
LE
GND
Vee
00
17
Q2
16
Q3
15
Q4
14
06
13 06
12
10
11
Q7
-LE
CD54174HC533, CD54174HCT533
CD54174HC563, CD54174HCT563
TERMINAL ASSIGNMENT
TERMINAL ASSIGNMENT
____________________________________________________________________ 419
Technical Data
CD54/74HC533, CD54/74HCT533
CD54/74HC563, CD54/74HCT563
STATIC ELECTRICAL CHARACTERISTICS
CD74HC533/CD54HC533
CD74HC563/CD54HC563
CD74HCT533/CD54HCT533
CD74HCT563/CD54HCT563
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85'C
+125'C
+85°C
+125'C
CHARACTERISTIC
UNITS
V,
10
Vee
V
rnA
V
+25'C
V,
Vee
V
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
V,"
Low-Level
Input Voltage
2
1.5
4.5
3.15
~
~
6
4.2
~
~
2
4.5
V"
6
High-Level
Output Voltage
2
V"
Vo"
CMOS Loads
or
-002
V,"
~
~
~
~
~
~
~
~
1.9
4.5
4.4
6
5.9
0.5
1.35
1.8
~
~
~
~
~
~
~
~
~
1.5
3.15
4.2
~
~
~
1.9
~
~
~
0.5
1.35
1.8
~
1.5
3.15
4.2
~
~
~
~
44
~
~
3.84
~
3.7
5.34
~
5.2
~
(Bus Driver)
Low-Level
Output Voltage
or
-6
4.5
3.98
V,"
-7.8
6
5.48
~
~
~
2
V"
Voe
CMOS Loads
or
0.02
4.5
6
V,"
0.1
~
0.1
~
~
0.1
~
0.1
~
~
0.1
~
0.1
~
~
0.26
~
0.33
~
~
0.26
~
0.33
~
~
~
~
~
2
~
2
~
V
to
~
~
45
4.4
~
4.5
3.98
0.8
~
08
~
08
V
5.5
or
~
44
~
44
~
3.7
~
V
V,"
or
~
~
3.84
~
V
V,"
V"
0.1
or
0.1
V,"
4.5
0.1
~
0.1
~
~
~
~
0.26
~
0.33
~
~
±0.1
~
±1
~
~
8
~
0.1
V
0.4
V
±1
pA
160
pA
490
I'A
V"
or
6
4.5
(Bus Driver)
V,"
7.8
6
Input Leakage
Vee
I,
~
V"
0.1
V"
TTL Loads
Current
~
V"
V"
TTL Loads
2
4.5
~
1.8
1.9
to
5.5
0.5
1.35
5.9
5.9
4.5
~
~
~
4.4
Min Typ Max Min Max Min Max
~
~
+25'C
or
6
~
~
±0.1
~
±1
~
~
~
04
or
0.4
V,"
±1
Any
Voltage
Between
Vee
4.5
5.5
~
~
&
Gnd
Gnd
Quiescent
Vee
Device
Current
or
Icc
0
6
~
8
~
~
80
~
160
Vee
or
Gnd
5.5
~
80
~
450
~
±5.0
~
Gnd
Additional
Quiescent
Oevice Current
per input pin:
1 unit load Lllcc·
3-State Leakage
Current
10'
V"
or
V,"
Vo~Vcc
or
Gnd
6
~
-For dual-supply systems theoretical worst case (VI
~
±0.5
~
±5.0
~
±10
Vee -2.1
4.5
to
5.5
V"
or
V'H
5.5
~
100 360
~
I'A
~
~
±0.5
~
±10
=2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
Unit Loads'
0.15
0.30
OE
0.55
..
'Unit load is Alec limit specified in Static Characteristic
Chart, e.g., 360llA max. @ 25°C.
DO-D7
IT
420 ______________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC533, CD54/74HCT533
CD54/74HC563, CD54/74HCT563
SWITCHING
CH~RACTERISTICS
(Vee=5 V, TA=25°C, Input t"t,=6 nB)
TYPICAL VALUES
HC
HCT
533
563
533
563
Cl
(pF)
CHARACTERISTIC
Propagation Delay Data to Qn Output
Fig.3
Propagation Delay LE to Qn Output
Fig.4
Output High Z to High Level, Fig. 6
Output High Z to Low Level, Fig.7
Output High Level to High Z, Fig. 6
Output Low Level to High Z, Fig. 7
Power Dissipation Capacitance
tPlH
tPHl
tPlH
tpHl
tPZH
tPZl
tPHZ
tPlZ
Cpo
13
15
.
12
14
12
15
14
13
16
14
15
15
15
15
12
12
12
12
42
12
12
12
12
42
14
14
12
12
42
14
14
14
14
42
-
UNITS
ns
pF
'Cpo determines the no-load dynamic power consumption per latch. It is obtained by the following relationship:
Po (total power per latch) = Cpo Vee 2 fi + 1: Cl Vee2 fo where f; = input frequency
to = output frequency
Cl = output load capacitance
Vee = supply voltage.
PRE-REQUISITE FOR SWITCHING FUNCTION
LIMITS
TEST
CONDITION
CHARACTERISTIC
Vee
V
LE Pulse Width
tw
(Fig. 4)
Set-up Time
Data to LE
(Fig. 5)
tsu
Hold Time
Data to LE
(Fig. 5)
tH
533
563
_55° to +125° C
-40° C to +85° C
25°C
HCT
HC
74HC
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
-
2
4.5
6
80
16
14
2
4.5
6
50
10
9
2
4.5
6
35
7
6
2
4.5
6
4
4
4
-
16
-
-
-
-
-
-
-
10
-
-
-
-
-
8
-
-
-
-
-
-
-
5
-
-
-
-
100
20
17
-
65
13
11
-
-
-
-
13
-
45
9
8
4
4
4
20
-
-
-
-
-
-
-
10
-
-
5
-
-
-
-
120
24
20
-
-
-
75
15
13
-
-
-
-
15
-
-
-
55
11
7
-
12
-
-
-
4
4
4
-
-
-
-
5
-
-
-
-
-
24
ns
ns
ns
ns
TRUTH TABLE
a
Output
Enable
Latch
Enable
Data
Output
L
H
H
L
L
H
L
H
L
L
I
H
L
L
h
L
H
X
X
Z
Note:
L = Low voltage level
H = High voltage level
I Low vOltage level one set-up time
prior to the high to low latch enable transition
h High voltage level one set-up time
prior to the high to low latch enable transition
X = Don't care
Z = High impedance state
=
=
___________________________________________________ 421
Technical Data
CD54/74HC533, CD54/74HCT533
CD54/74HC563, CD54/74HCT563
SWITCHING CHARACTERISTICS (CL
=50 pF, Inpullr,l, =6 ns)
TEST
CHARACTERISTIC
CONDITIONS
VCC (V)
Propagation Delay
2
tPlH
Data to an
4.5
tPHl
533
6
tplH
2
LE to an
4.5
tPHl
533
6
Enable Times
tpZH
2
tpzl
4.5
533
6
Disable Times
2
tPHZ
tPlZ
4.5
533
6
Propagation Delay
2
tplH
Data to an
4.5
tPHl
563
6
tpLH
2
LEto an
4.5
tPHL
563
6
2
Enable and
tpZH, tPZl
4.5
Disable Times tpHZ. tPlZ
563
6
I nput Capacitance
C,
3-State Output
Co
Capacitance
LIMITS
_55° C to +125° C
-40°Cto+85°C
54HCT UNITS
HCT
74HC
74HCT
54HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
205 250 ns
41
43
50
34
51
35
43
265 220 38
44
53
ns
48
57
37
45
190 225 44
45
53
ns
35
38
33
38
190 225 38
38
45
45
ns
30
33
38
225 190 ns
45
30
38
38
45
33
38
205 250 ns
41
44
50
53
35
43
35
225 190 ns
44
45
53
35
38
38
33
10
pF
10
10
10
10
-
+25°C
HC
Min. Max.
165
33
28
175
35
30
150
30
26
150
30
26
150
30
26
165
33
28
150
30
26
10
-
20
-
20
-
20
-
20
-
20
-
20
pF
422 _______________________________________________________________________
Technical Data
CD54/74HC533, CD54/74HCT533
CD54/74HC563, CD54/74HCT563
INPUT
LEVEL
INPUT
'.
tPHL~r-
--I
~
~Vs
Qn
92CS - 38343
92CS-38344
Fig. 4 - Latch enable propagation delays.
Fig. 3 - Oata to On output propagation delays and
output transition times.
INPUT
LEVEL----
INPUTLEVEL~
DE
Vs
Vs
All Other Inputs
Qn
OUTPUT
rK
Tied High
"'PZH
tpHZ
r---~-,Vw
or Low
DE
INPUT
Q::."---'1
92CS- 37135
92CS-3B345
54174HC
54/74HCT
Input Level
Veo
3V
V,
50% Vee
1.3V
V,
50% Vee
1.3 V
V.
90% Vee
4.15 V
Fig. 6 - 3-state propagation delays.
Fig. 5 - Latch enable pre-requisite times.
INPUT LEVEL
OE
Q" - - - -....
92CS-37136
54174HC
54174HCT
Input Level
Veo
3V
V,
50% Vee
1.3 V
V,
50% Vee
1.3 V
V.
10% Vee
0.45 V
Fig. 7 - 3-state propagation delays.
_________________________________________________________________ 423
Technical Data __________________________________
CD54/74HC534, CD54n4HCT534
CD54n4HC564, CD54n4HCT564
File Number
1640
High-Speed CMOS Logic
DO
iiO
01
Q1
02
Q2
03
Os
ii4
04
05
as
06
06
07
07
Octal D-Type Flip-Flop, 3-State, Inverting
Positive-Edge Triggered
CP
OE
92CS-38414
FUNCTIONAL DIAGRAM
Type Features:
• Common 3-state output-enable control
• Buffered inputs
• 3-State outputs
• Bus line driving capability
• Typical propagation delay = 13 ns @ Vee
(clock to output)
. The RCA-CD54174HC534, 564 and CD54174HCT534, 564
are high speed OCTAL D-TYPE FLIP-FLOPS manufactured
with silicon gate CMOS technology. They.possess the low
power consumption of standard CMOS integrated circuits,
as well as the ability to drive 15 LSTTL loads. Due to the
large output drive capability and the 3-STATE feature, these
devices are ideally suited for inter.facing with bus lines in a
bus organized system. The two types are functionally identical and differ only in their pinout arrangements.
The CD54/74HC534, 564 and CD54174HCT534, 564 are
positive edge triggered flip-flops. Data at the D inputs,
meeting the setup and hold time requirements, are inverted
and transferred to the Q outputs on the positive going transition of the CLOCK input. When a high logic level is applied
to the OUTPUT ENABLE input, all outputs go to a high
impedance state, regardless of what signals are present at
the other inputs and the state of the storage elements.
The CD54/74HCT logic family is speed, function, and pin
compatible with the standard 54LS174LS logic family.
= 5111, CL = 15 pF,
TA
= 25°C
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Laads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +B5° C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to
LSTTL Logic ICs
• Alternate Source is Philips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High NOise Immunity:
ML=30%, MH=30% of Vee; @ Vee=5V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'L=O.B V Max., V'H=2 V Min.
CMOS Input Compatibility
I, :5 1 p.A @ VOL, VO H
The CD54HC and CD54HCT devices are supplied in
20-lead hermetic dual-in-line ceramic packages (F suffix).
The CD74HC and CD74HCT devices are supplied in
20-lead dual-in-line plastic packages (E suffix) and in
20-lead dual-in-line surface mount plastic packages (M
suffix). Both types are also available in chip form (H suffix).
1 OF 8 IDENTICAL CIRCUITS
I---------------~-------------------l
~
CP
I
CL 00"_ _-,-1~
CL
I
TO~ER
FLIP_FLOP:E
~
DE
OE
~
TO 7 OTHER
I
CL
CL
P
P
I
-
L _______C..!::
N
CL
CL
L _____________ ~~~ _______
Fig. 1 - Logic diagram.
Ii
I
I
I
FLIP-FLOPS
vcc
I
I
I
.J
92CM-38413
424 ________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54n4HC534, CD54/74HCT534
CD54n4HC564, CD54n4HCT564
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE (Vee):
(Voltages referenced to ground) .................................................................................. -0.5 to +7 V
DC INPUT DIODE CURRENT, 1,K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ................................................... ± 20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Va < -0.5 V OR Va > V"c 1-0.5 V) ............................................... ± 20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Va < Vee 1-0.5 V) ................................................ ± 35 mA
DC Vee OR GROUND CURRENT (Icc): " .................................................... ,"', ..................... , ± 70 mA
POWER DISSIPATION PER PACKAGE (po):
For TA = -40 to +60°C (PACKAGE TYPE E) ........................................................................... 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) .............................................. Derate Linearly at 8 mW/oC to 300 mW
For TA = -55 to +100°C (PACKAGE TYPE F, H) ........................................................................ 500 mW
For TA = +100 to +125°C (PACKAGE TYPE F, H) ......................................... Derate Linearly at 8 mwrc to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) ............................................................................ 400 mW
For TA = +70 to +125°C (PACKAGE TYPE M) .............................................. Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .......................................................................................... -55 to +125°C
PACKAGE TYPE E, M .......................................................................................... -40 to +85'C
STORAGE TEMPERATURE (T..,) ......................................... ', ... , .. , ." ... ,., ................. , , ... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1/32 in. (1.59 ± 0,79 mm) from case for 10 s max, , ............................... ' .. , , ",. " , ... , .. ,. , +265°C
Unit inserted into a PC Board (min, thickness 1/16 in,. 1,59 mm)
with solder contacting lead tips only .......... , ........................ ' , , ... , ... ' , , ... , , , ............................ +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within the
following ranges:
LIMITS
UNITS
CHARACTERISTIC
MIN.
MAX.
Supply-Voltage Range (For TA = Full Package Temperature Range) Vce:'
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage V" Vo
2
6
V
4.5
5.5
V
0
Vee
V
Operating Temperature TA:
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
Input Rise and Fall Times, t., tf
at2V
0
1000
ns
at 4.5 V
0
500
ns
at6V
0
400
ns
..
'Unless otherWise specified, all voltages are referenced to Ground.
TRUTH TABLE
Inputs
Output
OE
00
1
,
20 Vee
OE
19 Q7
DO
OE
CP
Dn
On
00
18 07
Dl
L
L
L
H
-f'"
H
L
X
X
L
H
No Change
Z
Dl
17 06
D'
Qi
C2
16 Q6
D3
Os
D4
..r
L
X
Note:
X=Don't care
Z=High impedance state
../'=Low-to-H igh transition
6
15
20 Vee
19
Qo
18
51
17
02
16
OJ
1S
Q4
Os
Os
07
14 05
D5
14
D3
13 04
DS
13
OJ
12
54
11
-ep
D'
GNO 10
Top View
CD54174HC, HCT534 Types
TERMINAL ASSIGNMENT
12
D7
GND
10
11
ep
Top View
CD54/74HC,HCT564 Types
TERMINAL ASSIGNMENT
425
Technical Data
CD54n4HC534, CD54/74HCT534
CD54/74HC564, CD54n4HCT564
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT534/CD54HCT534
CD74HCT564/CD54HCT564
CD74HC534/CD54HC534
CD74HC564/CD54HC564
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
UNITS
CHARACTERISTIC
V,
10
Vee
V
rnA
V
+25°C
V,
Vee
V
V
Min Typ Max Min Max Min Max
Min Typ Max Min Max Min Max
1.5
-
-
1.5
-
1.5
-
4.5 3.15
-
-
3.15
-
3.15
-
-
-
4.2
-
4.2
-
-
0.5
-
0.5
1.35
-
1.35
2
High-Level
Input Voltage
V,"
6
Low-Level
Input Voltage
V"
Higt:-Level
Output Voltage
V"
Vo "
CMOS Loads
or
-0.02
V,"
4.2
2
-
-
0.5
4.5
-
-
1.35
-6
(Bus Driver)
V,"
-7.8
Low-Level
V"
Yo,
CMOS Loads
or
to
0.02
V,"
-
-
1.8
-
1.8
-
1.8
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5 3.98
-
-
3.84
-
3.7
-
or
6
5.48
-
-
5.34
-
5.2
-
V,"
2
-
-
0.1
-
0.1
-
0.1
V"
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
-
-
0.26
-
0.33
-
0.4
(Bus Driver)
V,"
7.8
6
-
-
0.26
-
0.33
-
0.4
V,"
Input Leakage
Vee
Any
Voltage
Between
Vee
&
Gnd
or
6
-
-
±0.1
-
±1
-
±1
6
-
-
8
-
80
-
160
Gnd
Current
Additional
Quiescent
Device Current
per input pin"
1 unit load
3-State Leakage
Current
or
Ice
2
-
V
to
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
3.7
-
V
4.5 3.98
4.5
-
-
0.1
-
0.1
-
0.1
V
or
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
/lA
5.5
-
-
8
-
80
-
160
/lA
-
450
-
490
/lA
-
±5.0
-
±10
/lA
Vee
Vee
Device
-
V"
4.5
Quiescent
2
5.5
6
I,
-
V"
or
Current
-
4.5
-
2
V"
TTL Loads
2
5.5
V"
or
Output Voltage
4.5
-
6
V"
TTL Loads
+25°C
0
or
Gnd
Gnd
4.5
Vee -2.1
to
-
100 360
5.5
~Icc
1o,
V"
or
V,"
Vo~V"
or
Gnd
6
-
-
±0.5
-For dual-supply systems theoretical worst case (VI = 2.4 V, Vee
-
±5.0
-
±10
V"
or
V,"
5.5
-
-
±0.5
=5.5 V) specification is 1.8 rnA.'
HCT Input Loading Table
Input
Unit Loads·
0 0 - 07
CP
0.15
0.30
0.55
OE
'Unit Load is ll.lcc limit specified in Static Characteristic Chart, e.g., 360/lA max. @ 25°C.
426
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54n4HC534, CD54/74HCT534
CD54/74HC564, CD54/74HCT564
SWITCHING CHARACTERISTICS (Vee = 5 V, TA
=25°C, Inpul I"
I, = 6 ns)
TYPICAL
CL
UNITS
CHARACTERISTIC
Propagation Delay
Clock to Q
tPLH
tPHL
Propagation Delay
Output Disable to Q
t PHZ
Propagation Delay
Output Enable to Q
tPZH
tPLZ
tPZl
(pF)
HC
HCT
15
13
14
ns
15
12
12
ns
15
12
14
ns
Maximum Clock Frequency
f max
15
60
50
MHz
Power Dissipation Capacitance'
Cpo
-
32
36
pF
'Cpo is used to determine the dynamic power consumption, per package.
Po = Cpo Vee 2 f, + L CL Vee2 fo where: F, = input frequency fo = output frequency,
CL = output load capacitance, Vee = supply voltage.
PREREQUISITE FOR SWITCHING FUNCTION
LIMITS
TEST
CHARACTERISTIC
Maximum Clock
Frequency
f max
Clock Pulse Width
Fig.2
Set-up Time
Data to Clock
Fig.3
Hold Time
Data 10 Clock
Fig.3
tw
lsu
534
IH
564
tH
____________
~
25° C
-40° C 10 +85° C
-55' C to +125° C
CONDITION
UNITS
54HC
HC
HCT
74HC
74HCT
54HCT
Vee
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
V
2
6
5 4 4.5
25
30
25 20
20 16
MHz
6
35
29 23 2
80
100 120 4.5
16
20
20 25
24 30
ns
14
6
17 20 2
60
75 90 4.5
12
20
15 25
18 ns
30
10
6
13 15 2
5
5
5
4.5
5
5
5
5
5
5
ns
6
5
5
5 2
5
5
5 5
4.5
3
3
3
ns
5
5 5
6
5
5 -
______________________________
~--------------427
Technical Data
CD54n4HC534, CD54n4HCT534
CD54n4HC564, CD54/74HCT564
SWITCHING CHARACTERISTICS (C L
= 50 pF, Input t" tf = 6 ns)
TEST
CONDITION
25°C
CHARACTERISTIC
HC
Vee
V
Propagation Delay
Clock to Output
Fig. 2
Propagation Delay
Output Disable
to
534
Fig.4
a
Propagation Delay
Output Disable
to
Fig. 4
564
a
Propagation Delay
Output Enable
toO
Fig. 4
Output Transition
Time
Fig.2
t PLH
t PHL
tPLZ
t PHZ
tpLZ
tPHZ
tPZL
tPZH
hLH
hHl
HCT
-40°C to +85°C
-55°C to +125°C
74HC
54HC
74HCT
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
2
4.5
6
-
-
-
165
33
28
150
30
26
2
4.5
6
2
4.5
6
-
2
4.5
6
-
35
-
-
250
50
43
-
-
-
53
-
-
38
-
-
45
-
-
225
45
38
-
-
-
-
-
45
-
-
53
-
205
41
35
-
44
-
-
-
30
-
-
-
-
190
38
33
135
27
23
-
-
-
170
34
29
-
-
150
30
26
--
35
-
190
38
33
-
44
-
-
2
4.5
6
-
-
12
-
-
75
15
13
-
15
-
60
12
10
-
-
30
-
-
-
-
38
-
-
-
205
41
35
-
-
225
45
38
-
-
90
18
15
-
-
Input Capacitance
C,
-
-
10
-
10
-
10
-
10
-
3-State Output
Capacitance
Co
-
-
20
-
20
-
20
-
20
-
ns
-
ns
ns
-
ns
-
18
ns
10
-
10
pF
20
-
20
pF
INPUT
LEVEL
'32CS- 36954
92CS-38442
54/74HC
54/74HCT
50% Vee
1.3 V
3V
Input Level
v,
Fig. 2- Clock to output delays and clock pulse width.
OUTPUTS
CONNECTED
Fig. 3-0ata set-up and hold times.
OUTPUTS
CONNECTED
92CS-38407
Fig. 4 - Transition times and propagation delay times.
428 ___________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
File Number
CD54/74HC540, CD54/74HCT540
CD54/74HC541, CD54/74HCT541
1659
High-Speed CMOS logic
18
AO
17
A1
A2
A3
4
16
5
15
14
A4
13
A5
A6
A7
8
12
9
11
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
92e5-38502
FUNCTIONAL DIAGRAM
Octal Buffer and line Drivers,
3-State
Type Features:
•
•
•
•
•
•
540 Inverting
541 Non-Inverting
Buffered Inputs
3-State Outputs
Bus Line Driving Capability
Typical Propagation Delay = 9 ns
@ Vee = 5 V, C L = 15pF, TA = 25° C
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85 0 C
.. Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is PhilipslSignetics
a CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity:
N'L = 30%, N,H = 30% of Vee; @ Vee = 5 V
• CD54HCTlCD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max .. V,H = 2 V Min.
CMOS Input Compatibility
I, ::; 1 /lA @ VOL. V OH
The RCA-CD54174HC540 and CD54/74HCT540 are Inverting Octal Buffers and Line Drivers with 3-State Outputs
and the capability to drive 15 LSTTL loads. The RCACD54/74HC541 and CD54/74HCT541 are Non-Inverting
Octal Buffers and Line Drivers with 3-State Outputs that
can drive 15 LSTTL loads. The Output Enables (OE1) and
(OE2) control the 3-State Outputs. If either OE1 or OE2 is
HIGH the outputs wil~n the high impedance state. For
data output OE1 and OE2 both must be LOW.
The CD54HC and CD54HCT devices are supplied in
20-lead ceramic dual-in-line packages (F suffix). The
CD74HC and CD74HCT devices are supplied in 20-lead
dual-in-line plastic packages (E suffix) and in 20-lead
dual-in-line surface mount plastic packages (M suffix). Both
types are also available in Cllip form (H suffix).
TRUTH TABLE
INPUTS
OE1
OE2
An
L
L
H
X
X
H
H
X
X
L
L
L
OUTPUTS
HC/
HC/
HCT540 HCT541
L
H
Z
Z
Z
Z
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
___________________________________________________________ 429
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54n4HC540, CD54n4HCT540
CD54/74HC541, CD54n4HCT541
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
............. -0.5 to + 7 V
±20mA
(Voltages referenced to ground)
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee -0.5V)
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V)
DC DRAIN CURRENT. PER OUTPUT (10) (FOR -0.5 V < Vo < Vee - 0.5V)
DC Vee OR GROUND CURRENT, PER PIN (Ice) ................ .
POWER DISSIPATION PER PACKAGE (Po)
±20mA
±35mA
±70mA
For TA = -40 to +60° C (PACKAGE TYPE E) ..
For TA = +60 to +85° C (PACKAGE TYPE E)
For TA
For TA
. ..... 500 mW
Derate Linearly at 8 mW/oC to 300 mW
= -55 to +100°C (PACKAGE TYPE F. H)
= +100 to +125°C (PACKAGE TYPE F. H)
... 500 mW
Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M)
For TA = +70 to +125°C (PACKAGE TYPE M) ..
........ 400 mW
Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .
PACKAGE TYPE E, M ..
................... -55 to, 125°C
-40 to t85°C
... -65 to '150°C
STORAGE TEMPERATURE (T"g)
LEAD TEMPERATURE (DURING SOLDERING)
At distance 1/16 ± 1/32 in. (1.59 j, 0.79 mm) from case for 10 s max
Unit inserted into a PC Board (min. thickness 1/16 In .. 1.59 mm)
......... +265°C
............. +300°C
with solder contacting lead tips only
HC/HCT
HC/HCT
541
540
e
e
e
18
VCC
VO
GND
17
V1
CC
GND
16
V2
CC
e
GND
15
V3
CC
e
GND
14
CC
V4
e
GND
13
CC
V5
GND
C~2
e
V6
GND
GND
~
VCC
~10 ~20
L
V7
GND
9lcs-38504R3
Fig. 1 -
Logic diagram for the CD54174HCIHCT 540 & 541
43o ________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC540, CD54/74HCT540
CD54/74HC541, CD54/74HCT541
STATIC ELECTRICAL CHARACTERISTICS
CD74HC540/CD54HC540
CD74HC541/CD54HC541
TEST
CONDITIONS
CD74HCT540/CD54HCT540
CD74HCT541/CD54HCT541
74HC/54HC
TYPES
74HC
TYPE
54HC
TYPE
-40/
-55/
+85°C
+125°C
TEST
CONDITIONS
741-:CTl54HCT
TYPES
74HCT
TYPE
54HCT
TYPE
+25°C
-40/
+85"C
-55/
CHARACTERISTIC
UNITS
+25°C
V,
V
I,
rnA
V"
V
Min
High-Level
Input Voltage
V",
Input Voltage
V"
High-Level
V"
Output Voltage
or
V""
CMOS Loads
-002
V"'
2
1.5
-
-
1.5
-
1.5
-
3.15
-
-
3.15
-
315
-
6
4.2
-
-
42
-
4.2
-
--
-
0.5
-
0.5
-
0.5
45
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
4.5
-
2
19
-
-
19
-
1.9
-
V"
4A
-
-
4A
-
44
-
or
6
5.9
-
-
59
-
59
-
V",
398
-
-
3.84
-
3.7
-
or
(Bus Driver)
V,,,
-7.8
6
5A8
-
-
534
-
5.2
-
V,,,
2
-
-
01
-
01
-
01
V,
002
45
-
-
01
-
01
-
01
or
6
-
-
01
-
0.1
-
01
V"'
V",
V",
TTL Loads
or
6
4.5
-
-
026
-
033
-
04
or
(Bus Driver)
V"'
78
6
-
-
026
-
033
-
04
V",
6
-
-
+01
-
,1
-
,1
Any
Voltage
Between
Vu
& Gnd
6
-
-
8
-
80
-
160
Input Leakage
Vee
I.
or
Gnd
QUiescent
V
DeVice
or
Current
I"
Gnd
or
10
-
-
08
-
0.8
V
4.5
4A
-
-
44
-
44
-
V
45
398
-
-
3.84
-
3.7
-
"
45
-
-
01
-
01
-
0.1
V
4.5
-
-
026
-
033
-
OA
V
55
-
-
,01
-
·1
-
·1
pA
5.5
-
-
8
-
80
-
160
pA
45
Vcc 21
10
-
100
360
-
450
-
490
pA
-
-
·0 5
-
'50
-
'10
pA
55
V
V - V.,
Leakage Current
or
or
V"
Gnd
V
6
-
-
,05
-
·50
-
:!10
or
55
V",
For dual-supply systems theoretical worst case (VI
Ao-A7
OE2
OE1
-
V
Gnd
3-State
Inpul
08
-
V"
0
Additional
QUiescent
DeVice Current
per Input pin
1 unit load
6lcc·
I"
2
V,.
V"
Current
-
V,.
45
CMOS Loads
2
-
55
-6
or
-
4.5
-
or
V"
2
10
5.5
45
V"
Output Voltage
+125° C
Min Typ Max Min Max Min Max
TTL Loads
Low-Level
V"
V
Typ Max Min Max Min Max
4.5
2
Low-Level
V,
V
=2.4 V. Vee = 5.5 V) specification IS 1.8 rnA.
HCT Inpul Loading Tables
CD54/74 HCT 540
Unil Loads'
Inpul
1
0.75
1.15
'Unlt Load IS 61cc limit specified In Static Characteristic
Chart, e.g., 360 JJA max. @ 25°C.
Ao-A7
OE2
OE1
CD54/74 HCT 541
Unil Loads'
0.4
0.75
1.15
431
Technical Data _______________________________
CD54n4HC540, CD54n4HCT540
CD54/74HC541, CD54n4HCT541
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vee:'
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V'N. VOUT
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t" t,
at2 V
at4.5V
at6V
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
V
V
V
-40
-55
+85
+125
°C
°C
0
0
0
1000
500
400
ns
ns
ns
'Unless otherwise specified, all voltages are referenced to Ground.
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Input t"t,=6 ns)
TYPICAL
CL
(pF)
CHARACTERISTIC
Propagation Delay
Data to Output
Output Enable and Disable to Outputs
Power Dissipation Capacitance'
t PHL t pLH
t pZH , t PZL • t pHZ , t pLZ
540
UNITS
HCT
HC
HCT
15
9
9
9
11
ns
15
13
50
14
55
14
48
14
55
ns
pF
-
CPD
541
HC
'C PD is used to determine the dynamic power consumption per channel.
PD "Vee' f, (CPD + Cel
f, " input frequency,
C L " output load capacitance
Vee" supply voltage
SWITCHING CHARACTERISTICS (CL =50 pF, Input t"t,=6 ns)
CHARACTERISTIC
Propagation Delay
Data to Outputs
HC/HCT 540
Propagation Delay
Data to Outputs
HC/HCT541
Propagation Delay
Output Enable and
Disable to Outputs
Output Transition
Time
Input Capacitance
3-State Output
Capacitance
SYMBOL
Vee
t pLH
t pHL
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
t pLH
t pHL
t PZH • tpZL,
t pHZ ,
t pLZ
-40°C to +85°C
-55°C to
25°C
HC
HCT
74HC
74HCT
54HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
110 140 165
24
28
30
22
33
19
24
28
115 145 175
23
29
28
35
35
20
25
30
160 200 240
32
40
48
44
35
27
34
41
-
-
C,
-
60
12
10
10
Co
-
20
hLH
hHL
-
-
-
-
-
12
-
-
-
-
-
15
-
-
-
-
-
75
15
13
10
-
10
-
90
18
15
10
-
-
-
-
10
-
20
-
20
-
20
-
20
+125°C
54HCT
UNITS
Min. Max.
-
-
-
36
-
-
-
-
-
42
-
-
ns
ns
-
-
-
53
-
-
-
-
-
18
-
-
-
10
pF
-
20
pF
ns
ns
432 _______________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC540, CD54/74HCT540
CD54/74HC541, CD54/74HCT541
INPUT
A
OUTPUT
Y
OUTPUT
Y
-O-U-T-P-U-T-S--~
......
OUTPUTS
CONNECTED
DISCONNECTED
-
-
V
au TSp U TS
CONNECTED
92CS-3l708
92CS-38394RI
Input Level
Switching Voltage, Vs
Fig. 3 -
OTHER
INPUTS
TIED HIGH OR LOW
Transition times and propagation delay times.
1
Ie WITH
OUTPUT RL = Ik n {v
for t
and t
3-STATE 1-.....~.fV'~-{J
CC
PLZ
PZL
OUTPUT
CL
GND for tpHZ and IpZH
.r
OUTPUT
DISABLE
Fig. 4 -
20
00
AO
92CS-35130R3
Three-state propagation delay test circuit.
Vee
OE1
19 OE2
AO
18
A1
50 pF
Yo
A1
18 YO
17
A3
A4
15
Y3
A4
A5
14 _
Y4
A5
A6
A7
GND
10
13
Y5
12
Y6
11
Y7
CD54174HC, HCT540 Types
TERMINAL ASSIGNMENT
Vee
19 OE2
A2
17 _
Y1
16 _
Y2
A2
20
16
A3
15
14
Y3
Y4
13 Y5
A6
12 Y6
A7
GND
Y1
Y2
10
11 Y7
CD54174HC, HCT541 Types
TERMINAL ASSIGNMENT
_____________________________________________________________ 433
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD 54/74H C583
CD54/74HC583
File Number
1828
High-Speed CMOS Logic
AO
13
12
80-At
14
81
A2
11
10
15
50
51
52
Type Features:
S3
•
•
•
82
4
A3 - 3
83
Cn
9
6
Vee
4-Bit BCD Full Adder With Fast Carry
Adds two decimal numbers
Full internallookahead
Fast ripple carry for economical expansion
C n +4
= 16
GND=8
FUNCTIONAL DIAGRAM
The RCA-CD54/74HC583 and CD54174HCT583 are binarycoded-decimal (BCD) full adders that add two 4-bit BCD
numbers and generate a carry-out bit if the sum exceeds 9.
The CD54HC/HCT583 are supplied in 16-lead hermetic
dual-in-line frit seal ceramic packages (F suffix). The
CD74HC/HCT583 are supplied in 16-lead dual-in-line plastic
packages (E suffix) and in 16-lead dual-in-line surface
mount plastic packages (M suffix). Both types are also
available in chip form (H suffix).
Family Features:
•
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
Alternate Source is Philips/Signe'tics
CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity: N,L = 30%, N,H = 30%
of Vee, @ Vee = 5 V
CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, ~ 1 f1A @ VOL, VOH
•
•
•
•
•
•
81
16
Vce
B2
15
A2
83
14
A1
A3
13
AO
Cn
12
BO
Cn + 4
11
50
10
51
52
53
GNO
TOP VIEW
TERMINAL ASSIGNMENT
434 ________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC583
CD54/74HC583
4
A3 o---r:::"""--l>~-"-1
2
B2o--C,.,..,-I>~-=-j
15
A2o--C~-L>~---j
14
A1o--1).o+J>o-"-I
'0
"-1''''-''--''51
12
BOo--1)~f>o-::-J
13
AOn----J''''"''..J,,~_''_i
11
~----------------oso
BUG
8
A
A
_
A(l)B
A@8
A®~.l. =
c~:=
A®S
Fig. 1 - Logic diagram.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ., .................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT. I'K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ....................................................... ±20 mA
DC OUTPUT DIODE CURRENT. 10K (FOR Vo < - Vee +0.5 V) ................................................... ±20 mA
DC DRAIN CURRENT. PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5 V) ................ , ................................... ±25 mA
DC Vee OR GROUND CURRENT (lee) .......... , ........................................................................... ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60' C (PACKAGE TYPE E) ........ , ...................................................................... 500 mW
For T. = +60 to +85'C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/'C to 300 mW
For TA = -55 to +1OO'C (PACKAGE TYPE F. H) ........................................................................... 500 mW
For T. = +100 to +125'C (PACKAGE TYPE F. H) ............................................. Derate Linearly at 8 mW/'C to 300 mW
ForTA = -40 to +70'C (PACKAGE TYPE M) ............................................................................... 400 mW
ForTA = +70 to +125'C (PACKAGE TYPE M) ................................................. Derate Linearly at 6 mW/'C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F. H ............................................................................................. -55 to +125'C
PACKAGE TYPE E. M ............................................................................................... -40 to +85'C
STORAGE TEMPERATURE (Tot,) .................................................................................... ~5 to +150'C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ............................................... '" ...... +265' C
Unit inserted into a PC Board (min. thickness 1/16 in .• 1.59 mm)
with solder contacting lead tips only ..................................................................................... +300'C
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 435
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC583
CD54/74HC583
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability. nominal operating conditions should be selected so that operation I, always within
the following ranges:
LIMITS
UNITS
CHARACTERISTIC
MIN.
MAX.
2
4.5
0
6
5.5
Vee
V
V
V
-40
-55
+85
+125
·C
·C
0
0
0
1000
500
400
ns
ns
ns
Supply-Vollage Range (For TA - Full Package-Temperalure Range) Vee:'
CD54174HC Types
CD54174HCT Types
DC Inpul or Oulpul Vollage V.. Vo
Operaling Temperalure TA:
CD74 Types
CD54 Types
Inpul Rise and Fall Times, I" I,
al2V
a14.5 V
al6V
'Unless otherwise specified, all voltages are referenced to Ground.
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT583/CD54HCT583
CD74HC583/CD54HC583
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
·401
·551
-401
·551
+85°C
+125°C
+8S°C
+125°C
UNITS
CHARACTERISTIC
+25°C
V,
I.
Vee
V
mA
V
High-Level
Input Voltage
2
1.9
4.5
4.4
-
6
5.9
-
2
6
4.2
2
-
4.5
V"
6
High-Level
Output Voltage
1.5
4.5 3.15
V'H
Low·Level
Input Voltage
Min Typ Max Min Max Min Ma.
VOH
V"
or
~.02
-
1.5
-
3.15
-
4.2
-
1.5
3.15
4.2
-
0.5
-
0.5
1.35
-
1.35
-
1.35
1.B
-
1.8
-
1.9
-
4.4
4.4
-
5.9
-
1.9
-
-
3.84
-
3.7
5.34
-
5.2
-
V,
Vee
V
V
V"
or
V"
or
-4
V,H
-5.2
6
5.4B
-
V"
or
2
-
-
0.1
-
0.1
4.5
-
0.1
0.02
0.1
-
0.1
-
0.1
V"
or
0.1
-
0.1
-
0.1
V,H
-
-
0.26
-
0.33
0.4
V"
or
0.2B
-
0.33
-
0.4
V,H
Output Voltage
VOL
CMOS Loads
V,H
TTL Loads
V"
or
4
4.5
V,H
5.2
6
Input Leakage
Current
6
or
6
-
-
0.1
-
±1
-
±1
Gnd
Quiescent
Device Current
or
Gnd
-
2
-
V
to
-
-
O.B
-
O.B
-
O.B
V
4.5
4.4
-
-
4.4
-
4.4
-
V
-
-
3.B4
-
3.7
-
V
V,H
V"
or
4.5 3.9B
V,H
Voltage
Between
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
pA
5.5
-
-
8
-
BO
-
160
pA
-
100 360
-
450
-
490
pA
Vee
0
6
-
-
8
-
BO
-
160
or
Gnd
Additional
4.5
Quiescent Oevice
Current per Input
pin: 1 unit load
2
Vee & Gnd
Vee
lee
-
Any
Vee
I,
-
5.5
1.B
TTL Loads
Low-Level
2
4.5
-
V,H
-
to
5.5
0.5
-
Min Typ Ma. Min Ma. Min Ma.
4.5
-
CMOS Loads
4.5 3.9B
5.9
+25°C
Alee
.
Vee-2.1
to
5.5
436 ___________Fo_r_d_u~al~-s~u~p~PI~y~sy~s~te~m~s~th~e~o~~~tl~Ca~l~w~0~rs~tc~a=s~e~(V~I_-~2.~4~V~,V~e=e_=~5=.5~V~)~Sp~e=c~lfl=ca=t='o~n~ls~I~.8~m~A~.~___________________
- - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC583
CD54/74HC583
HCT INPUT LOADING TABLE
INPUT
UNIT LOADS·
All
1.5
• Unit Load is 81ee limit specified in Static Characteristic
Chart, e.g., 360 pA max. @ 25° C.
SWITCHING CHARACTERISTICS (Vee = 5 V, T. = 25°C, Inpul I" If = 6 n8)
TYPICAL VALUES
CHARACTERISTIC
UNITS
CL
(pF)
HC
HCT
Propagation Delay,
Cn to Sn
tPHL, tPLH
15
24
24
An or Bn to Sn
tPHL, tPLH
15
23
29
Cn to Cn + 4
tPHL, tPLH
15
15
18
An or Bn to Cn + 4
tPHL, tpLH
15
16
22
-
50
54
Power Dissipation Capacitance·
Cpo
ns
pF
·CPD is used to determine the dynamic power consumption, per package
Po =Vee2 f; (Cpo + Cc) where: f, =input frequency
CL = output load capacitance
Vee = supply voltage
SWITCHING CHARACTERISTICS (CL = 50 pF, Inpul I" If
=6 n8)
LIMITS
TEST
CONDITIONS
CHARACTERISTIC
25°C
UNITS
HCT
HC
Vee
V
Propagation Delay, tpLH
tPHL
54HC
54HCT
Min. Max. Min. Max. Min. Man, Min. Max. Min. Max. Min. Max.
2
-
290
-
-
-
365
4.5
-
58
-
58
-
.~
-
-
-
435
-
73
-
87
-
87
-
49
-
-
-
62
-
-
-
74
-
-
2
-
280
-
-
-
350
-
-
-
420
-
-
tPHL
4.5
-
56
-
68
-
70
-
85
-
84
-
6
-
48
-
-
-
60
-
-
-
71
-
tpLH
2
-
180
-
-
-
225
-
-
-
270
-
-
tPHL
4.5
-
36
-
42
-
45
-
53
-
54
-
63
6
-
31
-
-
-
38
-
-
-
46
-
-
tpLH
2
-
195
-
-
-
245
-
-
-
295
-
-
tPHL
4.5
-
39
-
51
-
49
-
64
-
59
-
77
6
-
33
-
-
-
42
-
-
-
50
-
-
lrLH
2
-
75
-
-
-
95
-
-
-
110
-
-
hHL
4.5
-
15
-
15
-
19
-
19
-
22
-
22
6
-
13
-
-
-
16
-
-
-
19
-
-
-
10
-
10
-
10
-
10
-
10
-
10
Cn to Cn + 4
An or Bn to Cn + 4
Input
Capacitance
74HCT
6
An or Bn to Sn
Time
74HC
tPLH
Cn to Sn
Transition
_55° C 10 +125° C
-40°C 10 +85°C
C,
102
ns
pF
- - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 437
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC583
CD54/74HC583
INPUT
LEVEL
90%
90%
OUT PUT
Vs
100/0
10%.
92CS-36948RI
Input Level
Switching Voltage, Vs
54174HC
54174HCT
Vee
3V
50% Vee
1.3 V
Fig. 2 - Transition and propagation delay times.
Application
In an application where a binary number whose decimal
value is greater than 9 is to be added to a BCD number (0-9),
this device can be used to convert the binary number to a
BCD number and a carry. The resultant BCD + carry can
then be added to the other BCD operand to complete the
operation. The conversion from binary to BCD is
accomplished by adding the binary number to BCD "0"
(binary number on AO-A3 and 0000 on BO-B3).
438 _________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
File Number
CD54/74HC640, CD54/74HCT640
CD54/74HC643, CD54/74HCT643
1677
High-Speed CMOS Logic
cfl -'I
R=+,
Alo -~,>----+,-+-,
A1
T~:U
I
:
I
I
I
I
1
I
I
:
I
I
I
I
t
:
I
Blo
81
T~:U
I
A7
B7
OE
DIR
92CS-
Octal 3-State Bus Transceivers
Inverting (HC/HCT640)
True/Inverting (HC/HCT643)
Type Features:
• 3-state outputs
• Buffered inputs
• Applications in multiple-data-bus architecture
~B7BO
The RCA-CD54174HC640, 643 and CD54174HCT640, 643
silicon-gate CMOS 3-state bidirectional inverting and noninverting buffers are intended for two-way asynchronous
communication between data buses. They have high drive
current outputs which enable high-speed operation when
driving large bus capacitances. These circuits possess the
low power dissipation of CMOS circuits, and have speeds
comparable to low power Schottky TTL circuits. They can
drive 15 LSTTL loads.
Family Features:
• Fanout (over temperature range):
Standard outputs - 10 LSTTL loads
Bus driver outputs - 15 LSTTL loads
• Wide operating temperature range:
CD74HC/HCT: -40 to +85 0 C
• Balanced propagation delay and
transition times
• Significant power reduction compared to
LSTTL logic ICs
• Alternate source is Philips/Signetics
• CD54HC/CD74HC types:
2 to 6 V operation
High noise immunity: Ml= 30%, MH=30% of Vee
@ Vee=5 V
• CD54HCT/CD74HCT types:
4.5 to 5.5 V operation
Direct LS TTL input logic compatibility
V,l=0.8 V max., V'H=2 V min.
CMOS input compatibility
I, :S 1 I1A @ VOL, V OH
The CD54/74HC640 and CD54174HCT640 are inverting
buffers; the CD54174HC643 and CD54/74HCT643 are
true/inverting buffers.
The direction of data flow (A to B, B to A) is controlled by the
DIR input.
~uts
are enabled by a low on the Output Enable input
(OE); a high OE puts these devices in the high impedance
mode.
The CD54HC640, 643 and the CD54HCT640, 643 are supplied in 20-lead hermetic dual-in-line ceramic packages
(Fsuffix). The CD74HC640, 643 and CD74HCT640, 643 are
supplied in 20-lead dual-in-line plastic packages (E suffix)
and in 20-lead dual-in-line surface mount plastic packages
(M suffix). These devices are also supplied in chip form
(H suffix).
roNEo'F BIDENTiCAi CIRCUITS -
-I
I
I ~_--I
I
I
2(3,4,5,6,7,8,9>1
(
I
I
1'8('7,'6,'5,'4,'3,'2,"
A
)
B
I
I
I
I
I
I
___________ ...J1
92CM-36369RI
'--_ _ _ _ _ _ _ _ _ _---' "INVERTER ONLY IN HC/HCT643
Fig. 1 - Logic diagram.
________________________________________________________________ 439
T~chnical
Oata _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC64Q, CD54/74HCT640
CD54/74HC643, CD54/74HCT643
TRUTH TABLE
AO
80
A1
81
A2
82
A3
83
A4
84
A5
85
A6
86
A7
87
OE
CONTROL
INPUTS
HC, HCT643 Series
DATA PORT
STATUS
DATA PORT
STATUS
OE
DIR
An
Bn
An
Bn
L
H
H
L
L
H
L
H
0
I
Z
Z
0
0
Z
Z
I
I
Z
Z
Z
Z
I
0
To prevent excess currents in the High-Z modes all I/O terminals should
be terminated with 10KO to 1MO resistors.
VCC=20
GND=10
DIR
HC, HCT640 Series
9tCS-38484
FUNCTIONAL DIAGRAM
TRUE/INVERTING HC/HCT643
H = High
L= Low
I = Input
o = Output (Same Level as Input)
0= Output (Inversion of Input Level)
Z = High Impedance
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) •.••..•...••••................•....•.....•..........•.....••.......................... -0.5 to +7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5 V) •...•....•••........••..•.........................•.... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR V. < -0.5 V OR V. > Vee +0.5 If) •...•.........•••••.•.............................. ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < V. < Vee +0.5 'y j .....•..........•.•....••.........................•. ±35 mA
DC Vee OR GROUND CURRENT, (Icc) •..•.............•.... , ..•.....•...•.••.......•.•.......••......... : ...............•• ±70 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60·C (PACKAGE TYPE E) .•....•••..............•....••..••••..........•.••.............. c.......•....•. 500 mW
For T. = +60 ,to +85·C (PACKAGE TYPE E) .•....................•...•.••..•••.............•. Derate Linearly at 8 mW;oC to 300 mW
Ford. = -55 to +100·C (PACKAGE TYPE F, H) ....................................... , .................................. 500 mW
ForT. = +100 to +125·C (PACKAGE TYPE F, H) ..................... " ....•........ " ....... Derate Linearly at 8 mW/oC If) 300 mW
ForTA = -40 to +70· C (PACKAGE TYPE M) ........ , ......... , .... , .................... , ............. , ... , ...... ' ..... 400 mW
For TA = +70 to +125· C (PACKAGE TYPE M)
...................... , ................... , ... I Derate Linearly at 6 mW/o C to 70 mW
OPERATING-TEMPERATURE RANGE (T .):
PACKAGE TYPE F, H.................................... ',' ........................................ , ..'.... , ... , .. -55 to +125·C
PACKAGE TYPE E, M ............................................................................................. -40 to +85· C
STORAGE TEMPERATURE (T...) .................................................................................... -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1,59 ± 0.79 mm) from case for 10 s max,
...................... , .............................. +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................................................................................... +3OO·C
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation Is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA-Full Package Temperature Range)
Vee:·
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage, V" Va
Operating Temperature, T A:
CD74 Types
CD54 Types
Input Rise and Fall Times, t"t,:
at 2 V
at4.5V
at 6 V
LIMITS
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vce
-40
-55
+85
+125
·C
0
0
0
1000
500
400
ns
V
V
.
·Unless otherwise speCified, all voltages are referenced to Ground.
440 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC640, CD54/74HCT640
CD54/74HC643, CD54/74HCT643
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT640/643/CD54HCT640/643
CD74HC640/643/CD54HC640/643
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85 Q C
+l25'C
+85'C
+125'C
UNITS
CHARACTERISTICS
+25'C
V,
10
Vee
V
rnA
V
High-Level
Input Voltage
V'H
Low-Level
Input Voltage
2
1.5
3.15
6
4.2
2
-
6
High-Level
Output Voltage
V"
VOH
CMOS Loads
or
-O.O~
V,H
Min Typ Ma. Min Ma. Min Ma.
4.5
4.5
V"
+25°C
2
1.9
4.5
4.4
6
5.9
-
-
1.5
-
1.5
3.15
-
3.15
4.2
-
4.2
0.5
1.35
1.8
-
-
-
4.4
-
5.9
-
3.64
-
5.34
0.1
0.5
1.35
1.9
1.8
-
-
-6
4.5
3.98
Bus Driver
V,H
-7.8
6
5.48
2
0.02
4.5
-
-
-
-
V"
VOL
CMOS Loads
or
V,H
6
1.9
4.4
5.9
-
Min Typ Ma. Min Ma. Min Ma.
4.5
2
-
-
2
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
pA
5.5
-
-
8
-
80
-
160
pA
-
450
-
490
pA
-
±5
-
±10
pA
-
to
5.5
4.5
-
to
5.5
V"
or
V,H
0.1
0.1
-
3.7
-
0.1
0.1
-
-
0.33
-
0.4
or
0.33
-
0.4
V,H
±1
Any
Voltage
Between
0.1
5.2
-
V,H
0.1
V"
or
0.1
or
0.1
V,H
V"
or
6
4.5
Bus Driver
V,H
7.8
6
10
V
1.8
V"
TTL Loads
Input Leakage
Current
V
V"
or
Output Voltage
Vee
0.5
1.35
V"
TTL Loads
Low-Level
V,
Vcc
or
Gnd
6
-
0.26
0.26
-
±0.1
-
±1
-
Vee and
Gnd
Quiescent Device
Current
tee
Vee
or
Gnd
0
6
-
-
8
-
80
-
160
Additional
Quiescent Device
Current per
Vee
or
Gnd
4.5
1 Unit Load
V"
or
tOl
-
100 360
5.5
.!I Icc' ,
3-State
Leakage
Current
to
Vee -2.1
Input Pin:
V,H
Vo:
Vee
rGnd
6
-
'For dual-suppty systems theoretical worst case (V,
-
±0.5
-
±5
-
±10
V"
or
5.5
-
-
±0.5
V,H
..
=2.4 V. Vee: 5.5 V) specIfication
IS 1.8 mAo
HCT INPUT LOADING TABLE
UNIT LOADS·
INPUT
HCT640
HCT643
DIR
0.9
1.5
1.5
0.9
1.5
0.4
OE.A
B
• Unit load is .ll.lcc limit specified in Static Characteristic
Chart. e.g .• 360 IlA max. @ 25° C.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 441
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC640, CD54/74HCT640
CD54/74HC643, CD54/74HCT643
SWITCHING CHARACTERISTICS (Vee = 5 V, T A = 25 0 C, Inpull" I, = 6 ns)
TYPICAL VALUES
CHARACTERISTIC
UNITS
SYMBOL
CL
pF
HC640
HCT640
HC643
HCT643
Propagation Delay
A-B,B-A
tPHl. tPlH
B-A
15
7
9
7
9
-
-
9
10
Enable to High Z
tPHZ, tpLZ
12
12
12
12
Enable from High Z
tpZH, tPZL
12
12
12
13
Cpo
38
41
45
55
Power Dissipation
Capacitance
-
.
• Cpo is used to determine the dynamic power consumption per channel.
Po = Vee2 f; (Cpo + Ce). where: f; = input frequency.
C l = output load capacitance.
ns
pF
Vee = supply voltage.
SWITCHING CHARACTERISTICS (Cl = 50 pF, Input I" I, = 6 ns)
_40 0 C 10 +85° C
25°C
CHARACTERISTIC
SYMBOL
HC
Vee
HCT
74HC
-55° C 10 +125 0 C
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay
tPLH
2
-
90
-
-
-
115
-
-
-
135
A-S
tPHl
4.5
18
-
22
-
23
-
28
-
27
-
33
-
20
-
-
-
23
-
-
-
140
-
-
-
165
-
-
39
640/643
tPZH
2
-
tPZL
4.5
-
6
-
26
-
33
-
t pHZ
2
-
150
-
-
190
t PLZ
4.5
-
30
-
30
-
38
6
-
26
-
-
-
33
t PZH
2
-
150
-
-
4.5
-
30
33
6
-
26
-
-
190
t PZL
-
-
33
-
t pHZ
2
-
150
-
-
-
190
-
-
-
225
t pLZ
4.5
-
30
-
30
-
38
-
45
-
26
-
-
-
33
-
38
6
-
-
38
B-A
6
643
B-A
tPlH
2
tPHl
4.5
6
Output High-Z:
To High Level,
640
To Low Level
Output High Level,
Output Low Level
640
to High Z
Output High Z:
To High Level
643
To Low Level
Output High Level,
Output Low Level
643
to High Z
-
15
-
110
-
-
22
-
26
-
28
-
33
-
33
19
-
-
-
24
-
-
-
28
-
150
-
-
-
190
-
-
-
225
-
-
30
-
30
-
38
-
38
-
45
-
45
-
-
-
38
-
-
-
-
225
-
-
38
-
45
-
45
-
-
38
-
-
-
225
-
-
45
-
50
-
-
38
41
38
ns
ns
-
ns
ns
ns
-
45
ns
-
Output Transition
tTLH
2
-
60
-
-
-
75
-
-
-
90
-
-
Time
hHL
4.5
-
12
12
-
15
-
15
-
18
-
18
6
-
10
-
13
-
-
-
15
-
-
Cin
-
10
-
10
-
10
-
10
-
10
-
10
pF
Co
-
20
-
20
-
20
-
20
-
20
-
20
pF
Input Capacitance
3-State Output
Capacitance
-
~
ns
442 ______________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC640, CD54/74HCT640
CD54/74HC643, CD54/74HCT643
OTHER {
I N PUTS
TIED HIGH
OUTPUT RL=lkn ~Vcc FOR 'PLZ
~~s~~i~
OR LOW
OUTPUT
OUTPUT
1GND
AND IpZL
FOR t PHZ AND I PZH
~ C~OPF
ENABLE
92CS-37900
Fig. 2 - Three-state propagation delay test circuit.
If =6ns
-
Bn
GNO
-----
90%
- - Vs
---10%
90%
An
An
OUTPUTS
CONNECTED
OUTPUTS
CONNECTED
92CS-38482
92CS-38482
54174HC
54174HCT
Vee
3V
50% Vee
1.3 V
I nput Level
Switching Voltage, Vs
Fig. 3 - Transition times and progagation delay times.
20
DIR
19
AO
18
A1
17
A2
16
A3
15
A4
14
A5
13
A6
12
A7
GND
10
11
vee
BE
BO
B1
B2
B3
B4
B5
B6
67
92CS 361330
TERMINAL ASSIGNMENT
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 443
Technical Data ___________________________________________________________
CD54/74HC646, CD54/74HCT646
CD54/74HC648, CD54/74HCT648
File Number
1664
Advance Information/
Preliminary Data
High-Speed CMOS logic
B'
BOl
B'
83 OfTA
: : PORT
B6
B7
Octal Bus Transceiver/Register,
3-State
Type Features:
FUNCTIONAL DIAGRAM
• Independent Registers for
A and B Buses
• CD54174HCIHCT646 Non-Inverting
CD54174HCIHCT648 Inverting
• 3-State Outputs
• Drives 15LSTTL loads
• Typical Propagation Delay ~ 12ns (A
@ Vee~5 V, CL~ 15pF, TA~25°C
The RCA-CD54/74HC646 and CD54174HCT646 are octal
bus transceivers/registers with 3-state non-inverting outputs. The RCA-CD54174HC648 and CD54/74HCT648 are
octal bus transceivers/registers with 3-state inverting
outputs. These devices are bus transceivers with D-type
flip-flops which act as internal storage registers. Data on
the A bus or the B bus can be clocked into the registers on
the LOW-to-HIGH transition of either CAB or CBA clock
inputs. Output enable (OE) and direction (DIR) inputs
control the transceiver functions. Data present at the high
impedance output can be stored in either register or both
but only one of the two buses can be enabled as outputs at
anyone time. The select controls (SAB and SBA) can
multiplex stored and transparent (real time) data. The
direction control determines which data bus will receive
data when the output enable (OE) is LOW. In the high
impedance mode (output enable HIGH). A data can be
stored in one register and B data can be stored in the other
register. The clocks are not gated with the direction (DIR)
and output enable (OEj terminals; data at the A or B
terminals can be clocked into the storage flip-flops at any
time.
The CD54HC646, 648 and CD54HCT646, 648 are supplied
in 24-lead dual-in-line frit-seal ceramic packages (F suffix).
The CD74HC646, 648 and CD74HCT646, 648 are supplied
in 24-lead dual-in-line, narrow-body plastic packages (EN
suffix), in 24-lead dual-in-line, wide-body plastic packages
(E suffix). and in 24-lead dual-in-line surface-mount plastic
packages (M suffix). Both types are also available in chip
form (H suffix).
-'-~B)
Family Features:
•
•
•
•
•
•
•
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85 0 C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to
LSTTL Logic ICs
Alternate Source is Philips/Signetics
CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 30%, MH = 30% of Vee; @ Vee = 5 V
CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V'L = 0.8 V Max., V'H = 2 V Min.
CMOS Input Compatibility
I, S 1 IlA @ VOL, VOH
24 Vee
23
CBA
22
SBA
21
eAB
SAB
DIR
DE
AD
20
AI
19
A2
18
A3
17
A4
16
A5
A6
A7
GND
BO
Bl
B2
B3
B4
10
15 85
11
14 86
13
B7
12
TERMINAL ASSIGNMENT
444 ____________________________________________________________________
_____________________________________________________________ TechnicaIData
CD54/74HC646, CD54/74HCT646
CD54/74HC648, CD54/74HCT648
0------1
OE
OIR
SAB
ToeHANNELS
2T08
----..,I
,---------I
I
I
I
eBA
I
I
I
I
I
I
F/F
I
I
4,(5,6,7,8,
9,10,11)
I
I
I
I
648
[--------:
Vee
~~~-------~
646
AU---r-~-;
I
I
I
I
I
I
Vee
I
I
I
I
I
I
I
B
I
I
I
GNO
I
24
I
9 ______ ,
I
I
______ ,
~
I
L--l
o--vee
12
o--GNO
I
:
:
I
I
II
I
rl~
:
I
I F/F
L ________________________
:
~
I
L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~N=_O~E':H~I~E~I_=_A~:_e~~~s~
92CL - 38530RI
Fig. 1 - Logic Diagram.
____________________________________________________________________ 445
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC646, CD54/74HCT646
CD54/74HC648, CD54/74HCT648
FUNCTION TABLE
INPUTS
OPERATION OR FUNCTION
DATA 1/0 II
OE
DIR
CAB
CBA
SAB
SBA
AD THRUA7
BOTHRU B7
X
X
X
...r
x
X
X
Input
Not specified
Not specified
Input
Store A, B unspecified
Store B, A unspecified
Store A. B unspecified
H
H
X
...r
x
...r
...r
X
H or L
H or L
X
X
Input
Input
Store A and B Data
Isolation, hold storage
Store A and B Data
Isolation, hold storage
L
L
X
X
X
L
X
H or L
X
H
Input
Real-Time B Data to A Bus
L
Output
Real-Time B Data to A Bus
L
L
H
X
X
L
X
L
H
H or L
X
H
X
Input
Output
X
X
X
X
X
646
648
Store B, A unspecified
8 Data to A Bus
Stored B Data to A Bus
Stored
Real-Time A Data to B Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
Stored
A Data to
B Bus
# The data output functions may be enabled or disabled by various signals at the nE and DIR inputs. Data input functions are always
enabled, i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.
To prevent excess currents in the High-Z modes all 1/0 terminals should be terminated with 10KO resistors.
MAXIMUM RATINGS. Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground)
DC INPUT DIODE CURRENT, I'K (FOR V. < -0.5 V OR V, > Vee ·0.5V)
DC OUTPUT DIODE CURRENT, 10K (FOR V, < -0.5 V OR V, > Vee -'-0.5V)
DC DRAIN CURRENT, PER OUTPUT (I,) (FOR -0.5 V < V, < Vee T 0.5V)
DC Vee OR GROUND CURRENT (Icc)
POWER DISSIPATION PER PACKAGE (Po):
For T, ~ -40 to +60' C (PACKAGE TYPE E)
For T, ~ T60 to +85' C (PACKAGE TYPE E)
For T, = -55 to -100'C (PACKAGE TYPE F, H)
For TA = -100 to -125'C (PACKAGE TYPE F, H)
.... -0.5 to + 7 V
±20mA
±20mA
±35mA
:o70mA
..... 500
Derate linearly at 8 mWI' C to 300
.500
Derate linearly at 8 mW/'C to 300
mW
mW
mW
mW
For TA = -40 to +70'C (PACKAGE TYPE M) 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mW
For TA = +70 to +125°C (PACKAGE TYPE M) .............................................. Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (T,):
-40 to -85' C
.. .......... -55 to -125'C
...... -65 to '-150'C
PACKAGE TYPE E, M.
PACKAGE TYPE F, H .'
STORAGE TEMPERATURE (T",)
LEAD TEMPERATURE (DURING SOLDERING)
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in .. 1.59 mm)
with solder contacting lead tips only
.............. " -265' C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability. nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA
= Full
LIMITS
MIN.
MAX.
UNITS
Package-Temperature Range) Vee:'
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V ,N , V OUT
2
6
4.5
5.5
a
Vee
V
V
Operating Temperature T A:
CD74 Types
-40
+85
CD54 Types
-55
+125
a
a
a
1000
°C
Input Rise and Fall Times t" t,
at 2 V
at 4.5 V
at 6 V
500
ns
400
'Unless otherwise specified, all voltages are referenced to Ground.
446 ________________________________________________
- - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC646, CD54/74HCT646
CD54/74HC648, CD54/74HCT648
STATIC ELECTRICAL CHARACTERISTICS
CD74HC646/CD54HC646
CD74HC648/CD54HC648
CD74HCT646/CD54HCT646
CD74HCT648/CD54HCT648
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
V
10
rnA
V"
V
+25°C
V,
V
V"
V
Min Typ Max Min Max Min Max
Min Typ Max Min Max Min Max
High-Level
Input Voltage
V,,,
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
Vo ,;
CMOS Loads
or
-0.02
V"'
2
1.5
-
-
1.5
-
1.5
-
4.5
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
4.5
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
6
--
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
V"
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V",
4.5
3.98
-
-
3.84
-
3.7
-
or
(Bus Driver)
V",
-7.8
6
548
-
-
5.34
-
5.2
-
V",
2
-
-
0.1
-
01
-
0.1
V"
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V",
Vm
CMOS Loads
V",
V"
or
6
4.5
-
-
0.26
-
0.33
-
0.4
or
(Bus Driver)
V,"
7.8
6
-
-
0.26
-
0.33
-
0.4
V",
6
-
-
:to.l
-
,1
-
,1
Any
Voltage
Between
Vcr.
& Gnd
6
-
-
8
-
80
-
160
Input Leakage
Vo
I,
or
Gnd
Quiescent
Vee
Device
or
Current
I"
-
V
-
-
4.5
4.4
4.5
398
to
0.8
-
0.8
-
0.8
V
-
-
4.4
-
4.4
.-
V
-
-
3.84
-
37
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
45
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
:to.l
-
,1
-
,1
JJA
5.5
-
-
8
-
80
-
160
JJA
-
100
360
-
450
-
490
vA
-
-
,0.5
-
±5.0
-
±10
JJA
V"
TTL Loads
Current
2
5.5
-6
or
-
4.5
-
or
V"
2
-
V"
V"
Output Voltage
-
5.5
TTL Loads
Low-Level
2
to
Vo
0
or
Gnd
Gnd
4.5
Additional
Quiescent
Vcc-2. ,
Device Current
per input pin:
1 unit load
.6.lcc*
3-State
V"
Leakage Current
or
or
V,"
Gnd
1m
to
5.5
V"
= Vee
V"
6
-
-
~.5
-
.:t5.0
-
:t10
or
5.5
V,"
-For dual-supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specification is 1.8 mA.
HCT Input Loading Table
Input
OE
DIR
Clock A-B, B-A
Select A, Select B
Inputs AO-A7, BO-B7
Unit Loads'
1.3
0.75
0.6
0.45
0.3
'Unit Load is AI cc limit specified in Static Characteristi c
Chart, e.g., 360 {lA max. @ 25° C.
447
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC646, CD54/74HCT646
CD54/74HC648, CD54/74HCT648
SWITCHING CHARACTERISTICS (Vee
= 5 V, TA =25°C,
Inpull" I,
=6 ns)
TYPICAL
CL
(pF)
HC
HCT
15
18
18
ns
t pLH • t pHL
15
18
18
ns
Store A Data to B Bus (648)
tPLH. tpHL
15
20
23
ns
Store B Data to A Bus (648)
t pLH • t PHL
15
20
23
ns
A Data to B Bus (646)
t PLH • t pHL
15
12
15
ns
CHARACTERISTIC
Propagation Delays
Store A Data to B Bus (646)
tpLH.
t PHL
Store B Data to A Bus (646)
UNITS
B Data to A Bus (646)
t pLH • t pHL
15
12
15
ns
A Data to B Bus (648)
tpLH. tpHL
15
12
15
ns
B Data to A Bus (648)
t plH , t PHL
15
12
15
ns
Select to Data (646)
tPLH, tPHL
15
14
19
ns
Select to Data (648)
tPLH. tPHL
15
16
19
ns
3-State Disabling Time
t pLZ • t pHZ
15
14
14
ns
3-State Enabling Time
tPZL. tPZH
15
14
19
ns
Max Frequency
f mall
15
60
45
MHz
Power Dissipation Capacitance'
Cpo
-
52
52
pF
'C PO is used to determine the dynamic power consumption, per package.
Po = V CC 2 Cpo f, + L VCC 2 C L fo where:
C L = output load capacitance
Vee = supply voltage
f, = input frequency
fo = output frequency
PREREQUISITE FOR SWITCHING FUNCTION
CHARACTERISTIC
Maximum Frequency
Set Up Time
Data to Clock
Vce
f MAX
tsu
Hold Time
Data to Clock
tH
Clock Pulse Width
tw
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-55° C to
25°C
-40°C to +85°C
HC
HCT
74HCT
54HC
74HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
4
6
5
25
20
20
25
30
23
29
35
60
75
90
15
15
18
12
12
15
13
10
35
55
45
11
7
9
5
5
9
8
6
120 80
100 16
24
25
20
31
17
20
14
-
448 ________________________________________
+125° C
54HCT
UNITS
Min. Max.
17
-
-
MHZ
-
18
-
-
-
-
-
5
-
-
-
38
-
-
-
ns
ns
ns
~--------------
- - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical, Data
CD54/74HC646, CD54/74HCT646
CD54/74HC648, CD54/74HCT648
SWITCHING CHARACTERISTICS (CL = 50 pF, Inpul In I, = 6 n5)
CHARACTERISTIC
Propagation Delay,
Store A data to B bus
Store B data to B bus (646)
Store A data to B bus
Store B data to A Bus
(648)
A data to B bus
B data to A Bus
(646)
A data to B bus
B data to A Bus
(648)
Select to Data
(646)
Select to Data
(648)
3-State Disabling Time
Bus to Output or
Register to Output
3-State Enabling Time
Bus to Output or
ReQister to Output
Output Transition Time
Vee
t pLH
t pHL
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
tPLH
tpHL
2
4.5
6
t pLH
t pHL
t pLH
t pHL
t pLH
t pHl
t plH
t pHL
2
4.5
6
2
4.5
6
2
4.5
6
t pLZ
t pHZ
t PZl
t PZH
trLH
hHL
3-State Output
Capacitance
Input Capacitance
-
Co
C,
I
-
25°C
-40° C 10 +85° C
-55°C 10 +125° C
HC
HCT
74HC
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
220 - 275 - 330 44
44
55
55
66
66
ns
37
47
5.6
240 300 360 81
68
72
60
54
48
ns
51
61
41
135 170 205 27
34
46
41
56
ns
37
23
29 35
225 190 150 ns
30
38
45
37
46
56
26
38
33
215 255 170 34
ns
46
51
43
58
69
29
37
43
240 285 190
48
58
69
ns
38
46
57
32
39
48
-
-
-
-
-
-
175
35
30
175
35
30
60
12
10
-
-
-
20
-
10
-
-
-
-
-
-
-
-
-
I
-
35
-
-
45
-
-
-
-
-
-
12
-
20
10
-
220
44
37
220
44
37
75
15
13
20
10
-
-
-
-
-
-
-
-
-
56
-
-
44
-
-
15
-
-
-
-
265
53
45
265
53
45
90
18
15
-
-
20
-
20
-
-
-
10
-
10
-
-
-
-
53
ns
-
-
68
ns
18
ns
-
20
pF
10
pF
92CS-38405
Fig. 2 - Data setup and hold times.
__________________________________________________________ 449
TechnicaIOala _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC646, CD54/74HCT646
CD54/74HC648, CD54/74HCT648
A(81 VI
GND
""----......,
8(Al Vo
OUTPUTS
OUTPUTS
CONNECTED
'TLH
CONNECTED
92CS-38406
Input Level
Switching Voltage. Vs
92CS-38407
54n4HC
54n4HCT
Vee
50% Vee
3V
1.3 V
I
I
Fig. 3 - Transition times and propagation delay times.
450 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
_ ___
File Number
CD54/74HC670
CD54/74HCT670
1660
High-Speed CMOS Logic
DO
01
02
15
190 aD
al
2
3
03
_12
WE
11
6
a2
a3
ifE
RAI
RAO
WAD
WAI
92CS-38505
4 x 4 Register File
Type Features:
• Simultaneous and Independent Read and
Write Operations
• Expandable to 512 Words of n-Bits
• 3-State Outputs
• Organized as 4 Words x 4 Bits Wide
• Typical read time: 16 ns for HC670 at Vee
• Buffered inputs
=5 V,
CL
=15 pF,
TA
=25
0
C
FUNCTIONAL DIAGRAM
The RCA-CD54/74HC67D and CD54/74HCT670 are 16-bit
register files organized as 4 words x 4 bits each. Read and
write address and enable inputs allow simultaneous writing
into one location while reading another. Four data inputs
are provided to store the 4-bit word. The write address
inputs (WAD and WA 1) determine the location of the stored
word in the register. When write enable (WE) is low the
word is entered into the address location and it remains
transparent to the data. The outputs will reflect the true
form of the input data. When (WE) is high data and
address inputs are inhibited. Data acquisition from the four
registers is made possible by the read address inputs (RA 1
and RAO). The addressed word appears a\ the output when
the read enable (RE) is low. The output is in the high
inpedance state when the (RE) is high. Outputs can be tied
together to increase the word capacity to 512 x 4 bits.
The RCA CD54HC/HCT670 are supplied in 16-lead ceramic dual-in-line packages (F suffix). The CD74HC/HCT670
are supplied in a 16-lead dual-in-line plastic package (E
suffix) and in 16-lead dual-in-line surface mount plastic
packages (M suffix). Both types are also available in chip
form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCr· -40 to +85 0 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 30%, N'H = 30% of Vee: @ Vee = 5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I,:s 1 pA @ VOL, VOH
DI
16 Vee
D2
15 DO
D3
RAI
WAD
13
WAI
RAD
12
WE
03
11
RE
02
10
ao
GND
9 01
TERMINAL ASSIGNMENT
451
TechnicaIOata _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC670
CD54/74HCT670
c
Q
~
XI
X2
c
92C5 - 38785
Latch Detail
Fig. 1 - Logic Diagram.
452 _________________________________________________________________
___________________________________________________________ TechnicaIData
CD54/74HC670
CD54/74HCT670
READ MODE SELECT TABLE
WRITE MODE SELECT TABLE
OPERATING
MODE
Write Data
Data
Latched
INPUTS
WE
L
DN
L
L
H
H
INTERNAL
LATCHES!-)
X
MODE
L
H
Read
no change
NOTE:
a. The Write Address (WAO and WA1) to the "internallatches" must be stable while WE is LOW for
conventional operation.
INPUTS
OPERATING
Disabled
OUTPUT
INTERNAL
LATCHES!b)
RE
ON
L
L
L
L
H
H
H
X
(Z)
NOTE:
b. The selection of the "internal latches" by Read
Address (RAO and RA 1) are not constrained by
WE or RE operation
H = HIGH voltage level
L = LOW voltage level
X = Don't care
Z = HIGH impedance "off" state.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE. (Vee):
(Voltages referenced to ground) ................................................................................. -O.S
DC INPUT DIODE CURRENT, I'K (FOR V, < -O.S V OR V, > Vee +O.SV) ....................................................
DC OUTPUT DIODE CURRENT, 10K (FOR V. < -O.S V OR V. > Vee +O.SV) ..................................................
DC DRAIN CURRENT. PER OUTPUT (I.) (FOR -O.S V < V. < Vee + O.SV) ..................................................
DC Vee OR GROUND CURRENT (Icc) ..................................................................................
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60· C (PACKAGE TYPE E) ...........................................................................
For T. = +60 to +8S· C (PACKAGE TYPE E) ............................................. Derate Linearly at 8 mW/· C to
For T. = -SS to +100·C (PACKAGE TYPE F. H) .......................................................................
For T. = tl00 to +12SoC (PACKAGE TYPE F. H) ........................................ Derate Linearly at 8 mW/·C to
to + 7 V
±20mA
±20mA
±35 rnA
±70 rnA
SOO
300
SOO
300
mW
mW
mW
mW
For T. = -40 to +70°C (PACKAGE TYPE M) .......................................................................... 400 mW
ForT. = +70 to +12soq (PACKAGE TYPE M) ........................................... Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F. H ......................................................................................... -55 to +12SoC
PACKAGE TYPE E, M ................ : ......................................................................... -40 to +8So C
STORAGE TEMPERATURE (T",) ................................................................................ -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max. . ................................................... +26S·C
Unit inserted into a PC Board (min. thickness 1/16 in .. 1.59 mm)
with solder contacting lead tips only . ................................................................................. +300· C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
LIMITS
MIN.
MAX.
UNITS
Supply-Voltage Range (For TA - Full Package-Temperature Range) Vce:'
2
6
CD54174HCT Types
4.5
5.5
DC Input or Output Voltage V" Vo
a
Vee
CD54174HC Types
V
V
Operating Temperature TA:
CD74 Types
-40
+85
CD54 Types
-55
+125
a
a
a
1000
°C
Input Rise and Fall Times t" t,
at2V
at4.5V
at6V
500
ns
400
'Unless otherwise specified, all voltages are referenced to Ground.
_________________________________________________________________ 453
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC670
CD54/74HCT670
STATIC ELECTRICAL CHARACTERISTICS
CD74HC670/CD54HC670
CD74HCT670/CD54HCT670
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
SERIES
SERIES
SERIES
CONDITIONS
SERIES
SERIES
SERIES
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
V
10
rnA
Vee
V
+25°C
V,
V
Vee
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
1.5
-
-
1.5
-
1.5
4.5 3.15
-
-
3.15
3.15
-
4.2
-
-
4.2
-
4.2
-
2
V,"
6
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
YO"
CMOS Loads
or
-0.02
V,"
Bus Driver
Low-Level
Output Voltage
-6
V,"
-7.8
CMOS Loads
or
0.02
V,"
2
-
-
0.5
-
0.5
-
0.5
-
1.35
-
1.35
-
1.8
-
1.8
-
1.35
6
-
Bus Driver
Input Leakage
Current
2
1.9
-
-
1.9
-
1.9
-
V"
4.5
4.4
-
-
4.4
4.4
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5 3.98
-
-
3.84
-
3.7
-
or
5.34
-
5.2
-
V,"
0.1
V"
0.1
or
V,"
6
5.48
2
-
0.1
-
0.1
4.5
-
-
0.1
-
0.1
-
6
-
-
0.1
-
0.1
-
0.1
-
0.33
-
0.4
0.33
-
0.4
6
4.5
-
-
0.26
V,"
7.8
6
-
-
0.26
or
Quiescent
Vee
or
Current
tee
2
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.4
-
-
4.4
-
4.4
-
V
4.5 3.98
-
-
3.84
-
3.7
-
V
to
5.5
or
4.5
4.5
-
-
0.1
-
0.1
-
0.1
V
6
-
-
±D.l
-
±1
-
or
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
_.
-
±D.l
-
±1
-
±1
VA
5.5
-
-
8
-
80
-
160
VA
-
100 360
-
450
-
490
vA
-
-
-
±5
-
!10
vA
V,"
Any
Voltage
±1
Between
Vee
& Gnd
Gnd
Device
-
V"
or
Vee
t,
-
4.5
-
1.8
V"
TTL Loads
2
to
5.5
V"
or
V"
Voe
4.5
-
4.5
V"
TTL Loads
Min Typ Max Min Max Min Max
Vee
0
6
-
-
8
-
80
-
160
Gnd
or
Gnd
Additional
Quiescent
Device Current
per input pin:
1 unit load
l>lcc
4.5
Vcc-2.1
to
5.5
3-State
V"
leakage
or
or
current
V,"
Gnd
Vo
= Vee
V"
6
-
-
±D.5
-
±5
-
±10
or
5.5
±D.5
V,"
·For dual-supply systems theoretical worst case (V, = 2.4 V, Vee = 5.5 V) specllication is 1.8 rnA.
454 ______________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC670
CD54/74HCT670
HCT Input Loading Table
Input
WE
WAO
WA1
RE
DATA
RAO
RA1
Unit Loads'
0:3
0.2
0.4
1.5
0.15
0.4
0.7
'Unit Load is Ll.lee limit specified in Static Characteristic
Chart, e.g., 360llA max. @ 25°C.
SWITCHING CHARACTERISTICS (Vee = 5 V, T A = 25° C, Input t" t, = 6 ns)
CL
(pF)
CHARACTERISTIC
Propagation Delay
Reading any word
SYMBOL
t pLH
15
Write Enable to Output
15
Data to Output
15
Output Disable Time
15
Output Enable Time
15
t PHL
t PLH
t pHL
tPLH
t pHL
t PLz
t pHZ
tPZL
TYPICAL
HC
HCT
UNITS
16
17
ns
21
21
ns
21
21
ns
12
14
ns
12
16
ns
59
66
pF
tPZH
Power Dissipation Capacitance'
Cpo
-
'CPO IS used to determine the dynamic power consumption, per output.
PO:::: CPD VCC2 f, + L C L V CC 2 fo where f l :: input frequency,
fo:: output frequency,
C L ::: output load capacitance
Vee
=
supply voltage
PREREQUISITE FOR SWITCHING FUNCTION
CHARACTERISTIC
SYMBOL
Set-up time
Data to WE
t,u
Hold time
Data to WE
th
Set-up time
Write toWE
t~HJ
Hold time
Write to WE
th
WE
Pulsewidth
tw
Latch time
WE to RAO, RA 1
tLATCH
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
25°C
-40° C to +85° C
-55°C to +125°C
54HC
54HCT
UNITS
74HC
HCT
74HCT
HC
Min. Max. Min. Max. Min, Max, Min, Max. Min. MaJ(, Min, MaJ(,
90
60
75
14
18
18
21
ns
12
15
15
10
13
5
5
5
5
5
ns
5
5
5
5
5
5
5
75
90
60
18
27
ns
12
18
15
23
10
15
13
5
5
5
5
5
ns
5
5
5
5
5
5
5
100 80
120 16
20
20
ns
25
24
30
14
17
20
-
2
4.5
6
100
20
17
Vee
-
25
-
-
125
25
21
-
-
-
31
-
-
150
30
26
-
-
-
38
-
-
ns
_ _ _ _ _ _ _ _ _ _ _ _ 455
TechnicaIOata _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD 54/74HC670
CD54/74HCT670
SWITCHING CHARACTERISTICS (CL = 50 pF, Inpul I. I, = 6 ns, )
CHARACTERISTIC
SYMBOL
Vee
2
4.5
Propagation Delay
Reading any word
74HC
74HCT
54HC
54HCT
UNITS
HC
HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
195 245 295
39
40
49
50
59
60
ns
.~~~~----_+--~--+-~6--~-__r33
Write Enable
to Output
t pLH
t pHL
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
Data to Output
Output Disable Time
Output Enable Time
Output Transition
Time
3-State Output
Capacitance
Co
Input Capacitance
C,
-
-
-
~42~----~-~----~5~0~--_+----~--_1
250 315 375
50
50
63
63
75
-43---54---64
256 315
375
50
50
63
63
75
-43---54---64
150 190 225
30
35
38
44
45
26
33
38
150 190 225
30
38
38
48
45
26
33
38
75
95
110
15
15
19
19
22
13
10
.19
10
10
10
10
10
75
ns
75
ns
53
ns
57
ns
22
ns
20
pF
10
pF
INPUT
~------ LEVEL
I-
INPUT
LEVEL
\
o
Vs
~
92CS-38786
Fig. 3 - Propagation delay. Read Address to Output
Fig. 2 - Propagation Delay. Wnte Enable and Data to Output
tf= 6 ns
===-====90 %
*------vs
~~~~
~~~~~~10%
On
OUTPUT
LOW TO OFF
-+-,---'"1
an
OUTPUT H I G H - - - - J . .
TO OFF
OUTPUTS
CONNECTED
---90%
RAOOR R A 1 - - - - - - - - - - - - - j " -....Y~1O%
92CS- 38509RI
456
Fig. 4 - Setup and Hold Times. Write Address and Data
to Write Enable
OUTPUTS
CONNECTED
92CS-38510RI
Fig. 5 - 3-State Enable and Disable Times
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC670
CD54/74HCT670
I
I Input Level
I Switching Voltage, Vs
I
I
I
54n4HC
Vee
50% Vee
54n4HCT
3V
1.3V
92CS- 38511
Fig. 6 - Setup and Hold times, Read Address to Read Enable
__________________________________________ 457
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC688
CD54/74HCT688
File Number 1646
High-Speed CMOS Logic
AO
A1
A2
A3
A4
A5
A6
A7
BO
B1
B2
B3
2
4
6
8-Bit Magnitude Comparator
1~
13
15
17
3
5
7
9
12
Type Features:
• Cascadable
19 Y
84 14
85 16
~~
18
E
92C5-38415
FUNCTIONAL DIAGRAM
The RCA-CD54174HC688 and CD54/74HCT688 are 8-bit
magnitude comparators designed for use in computer and
logic applications that require the comparison of two 8-bit
binary words. When the compared words are equal the
output (Y) is low and can be used as the enabling input for
the next device in a cascaded application.
The CD54HC688 and CD54HCT688 are supplied in 20-lead
ceramic dual-in-line packages (F suffix). The CD74HC688
and CD74HCT688 are supplied in 20-lead dual-in-line
plastic packages (E suffix) and in 20-lead dual-in-line
surface-mount plastic packages (M suffix). Both types are
also available in chip form (H suffix).
Family Features:
• Fanout (over temperature range):
Standard outputs -10 LSTTL loads
Bus driver outputs - 15 LSTTL loads
• Wide operating temperature range:
CD74HCIHCT: -40 to +85 0 C
• Balanced propagation delay and
transition times
• Significant power reduction compared to
LSTTL logic ICs
• Alternate source is PhilipslSignetics
• CD54HCICD74HC types:
2 to 6 V operation
High noise immunity: ML= 30%,N'H=30% of Vee:
@ Vee=5 V
• CD54HCTICD74HCT types:
4.5 to 5.5 V operation
Direct LSTTL input logic compatibility
V'L =0.8 V max., V'H=2 V min.
CMOS input compatibility
I,~ 1 pA @ VOL, VOH
TRUTH TABLE
100GND
92C5 -38417RI
200 vcc
y
Il1Q,uts
OutDuts
A B
E
Y
A=B
A#B
X
L
L
H
L
H
H
x = Don't care
L = Low level
H = High level
Fig. 1 - Logic diagram.
458 _________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC688
CD 54/74HCT688
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ...................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, ',K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ....................................................... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) ................................................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) .................................................... ±25 mA
DC Vee OR GROUND CURRENT, (Icc) ..................................................................................... ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
ForT. = -40 to +60°C (PACKAGE TYPE E) ............................................................................... 500 mW
ForT. = +60 to +85°C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/oC to 300 mW
ForT. = -55 to +100°C (PACKAGE TYPE F. H) ........................................................................... 500 mW
ForT. = +100 to +125°C (PACKAGE TYPE F, H) .......................•..................... Derate Linearly at 8 mW/oC to 300 mW
For T. = -40 to +70° C (PACKAGE TYPE M)
. .. .. .. .. .. .. .. .. . .. . .. .. . . .. . . . . .. . .. .. .. . . . . .. .. .. .. .. .. . . . .. .. .. . .. . . ... 400 mW
............................................. Derate Linearly at 6 mW/o C to 70 mW
For T. = +70 to +125° C (PACKAGE TYPE M)
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F. H ............................................................................................ -55 to +125° C
PACKAGE TYPE E, M ............................................................................................. -40 to +85°C
STORAGE TEMPERATURE (T••• ) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
. .................................................... +265°0
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................................................................................... +300° C
RECOMMENDED OPERATING CONDITIONS
For maximum reliability. nominal operating conditions should be selected so that operation Is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA=Full Package Temperature Range)
Vee:'
CD54/74HC Types
CD54174HCT Types
DC Input or Output Voltage, V" Vo
Operating Temperature, TA:
CD74 Types
CD54 Types
Input Rise and Fall Times, t"t,:
at 2 V
at4.5V
at6V
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
V
V
'Unless otherwise specified, all voltages are referenced to Ground.
E
1
AO
BO
Al
Bl
A2
B2
20 Vee
19 y
3
18 B7
4
17 A7
5
16 B6
6
15 A6
7
14 B5
8
13 AS
9
. 12 B4
GND 10
11 A4
A3
B3
92C5-38418
TERMINAL ASSIGNMENT
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 459
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
CD54/74HC688
CD54/74HCT688
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT688/CD54HCT688
CD74HC688/CD54HC688
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85 D C
+125°C
+85·C
+125·C
UNITS'
CHARACTERISTICS
+25·C
V,
10
Vee
V
mA
V
High-Level
Input Voltage
V,"
Low-Level
Input Voltage
VIC
High-Level
Output Voltage
VIC
Vo"
CMOS Loads
or
-0.02
V,"
+25°C
Min Typ MI. Min MI. Min MI.
Low-Level
Output Voltage
CMOS Loads
1.5
-
1.5
3.t5
-
3.15
-
-
-
4.2
-
-
-
0.5
-
0.5
-
0.5
1.35
1.35
-
1.8
-
1.35
-
-
-
1.9
-
1.9
-
-
4.4
4.4
-
or
5.9
-
5.9
-
V,"
3.7
-
or
5.2
-
V,"
VIC
1.5
3.15
-
6
4.2
2
4.5
6
4.2
2
1.9
4.5
4.4
6
5.9
-
4.5 3.98
-
-
3.84
1.8
Quiescent Device
Current
Icc
-
1.8
-
2
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
iJA
5.5
-
-
8
-
80
-
160
iJA
-
100 360
-
450
-
490
iJA
to
5.5
VIC
VIC
V,"
-5.2
6
5.48
-
-
5.34
2
-
-
0.1
-
0.1
-
0.1
0.02
4.5
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
~
0.1
V,"
VIC
or
4
4.5
-
-
0.26
-
0.33
-
0.4
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
Any
Voltage
Between
Vee and
Gnd
Vee
or
Gnd
Vee
or
Gnd
-
4.5
Input Leakage
..
2
to
5.5
-
or
Min Typ MI. Min MI. Min MI'
4.5
-
VIC
Current
V
-4
V,"
TTL Loads
V
or
VIC
Vo,
Vee
-
2
4.5
VIC
TTL Loads
V,
6
-
-
±0.1
-
±1
-
±1
6
-
-
8
-
80
-
160
v..c
0
or
Gnd
Additional
Quiescent Device
4.5
Current per
Vee -2.1
Input Pin:
1 Unit Load
to
5.5
Alec
·For dual-supply systems theoretical worst case (VI
=2.4 V, Vee = 5.5 V) specification
is 1.8 rnA.
HCT Input Loading Table
'Unit Load is alec limit
specified in Static
Characteristics Chart,
e.g., 360 pA max.@25°C.
460 _______________________________________________________________
_____________________________________________________________ TechnicaIOata
CD54/74HC688
CD 54/74H CT688
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25° C, Inpull.. I, = 6 ns)
TYPICAL VALUES
SYMBOL
CHARACTERISTIC
Propagation Delay A and B Data to Output
UNITS
CL
pF
HC
HCT
15
14
14
15
9
9
-
22
22
tPLH
tPHL
Propagation Delay Enable to Output
tPLH
ns
tPHL
Cpo
Power Dissipation Capacitance"
pF
'CPO is used to determine the power consumption, per device.
PD=Vcc2 fi (Cpo + Cc) where f;=input frequency
C, =output load capacitance
Vce=supply voltage
SWITCHING CHARACTERISTICS (CL=50 pF, Inpull"I,=6 ns)
CHARACTERISTIC
Propagation Delay
An to Output
Bn to Output
SYMBOL
tpLH
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
tpHL
IPLH
tPHL
tPLH
"Eto Output
tpHL
Output Transition
Time
!THL
Input Capacitance
C,
VCC
hLH
-55°C 10 +125°C
-40° C 10 +85° C
25°C
54HCT
UNITS
74HCT
54HC
HC
HCT
74HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
255 170 210 42
51
51
ns
34
34
42
36
43
29
255
170 210 42
51
ns
34
34
42
.51
43
29
36
180 150 120 36
ns
36
24
24
30
30
20
26
30
110 75
95
19
22
22
ns
15
15
19
19
16
13
-
-
10
-
10
-
tr = 6 ns
If
ANYtNPUT
AOR B
-
10
=6
10
-
10
-
10
pF
ns
____ 90 % INPUT LEVEL
-I-t---Vs
--JE:'
----10% GND
OUTPUT
Y
-----'Jt~~"~-
I_PLH
92C5-38416
Inpul Level
Swilching Vollage, Vs
I
I
I
54/74HC
VCC
50%VCC
I
I
I
54/74HCT
3V
1.3 V
Fig. 2 - Propagation delay and transition times.
I
I
I
_______________________________________________________________________ 461
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4002
CD54/74HCT4002
File Number
1776
High-Speed CMOS Logic
,.
Dual 4-lnput NOR Gate
1A
1Y
1C
1D
2A
2.
13
2C
Type Features:
• Typical CDS4/74HC4002 Propagation Delay = 8ns
@ Vcc = SV, C L = ISpF, TA = 2SoC
2Y
Vee = 14
GND=7
NC = 8,8
2D
92CS-3677IR2
FUNCTIONAL DIAGRAM
The RCA-CD54/74HC4002 and CD54/74HCT4002 logic
gates utilize silicon-gate CMOS technology to achieve
operating speeds similar to LSTTL gates with the low power
consumption of standard CMOS integrated circuits. All
devices have the ability to drive 10 LSTTL loads. The
CD54174HCT logic family is functionally as well as pin
compatible with the standard 54LS/74LS logic family.
The CD54HC/HCT4002 are supplied in 14-lead ceramic
dual-in-line packages (F suffix). The CD74HC/HCT4002
are supplied in 14-lead dual-in-line plastic packages (E suffix) and in 14-lead dual-in-line surface-mount plastic
packages (M suffix). Both types are also available in chip
form (H suffix).
nA
nS
nY
nC
Family Features:
• Fanout (over temperattJ(e range):
Standard Outputs - 10 LSTTL loads
Bus driver outputs - IS LSTTL loads
• Wide Operating temperature range:
CD74HC/HCT: -40 to +8SoC
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL
logic ICs
• Alternate source is PhilipslSignetics
• CDS4HC/CD74HC Types:
2 to 6 V Operation
High noise immunity: N,L = 30%, N'H = 30% of Vee,
@ Vee = SV
• CDS4HCTICD74HCT Types:
4.S to S.S V Operation
Direct LSTTL input logic compatibility
V,L = 0.8 V max., V,H = 2 V Min.
(;MOS input compatibility
I, :::; 1 flA @ VOL, VO H
nO
Fig. 1 - LOGIC DIAGRAM (One Gate) for HC4002.
TRUTH TABLE
nA
INPUTS
nS
nY
nC
OUTPUT
nA
nB
nC
nO
nY
L
L
L
L
H
H
X
H
X
X
X
X
H
X
X
X
X
H
L
L
L
L
X
X
X
H = High Level
L = Low Level
X = Don'! Care.
nO
Fig. 2 - LOGIC DIAGRAM for HCT4002.
462 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
_____________________________________________________________ TechnicaIData
CD 54/74HC4002
CD54/74HCT4002
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ................................................................................... -0.5
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5V) ................................................
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V) ...................................................
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V) ..................................................
DC Vee OR GROUND CURRENT (Ieel ..................................................
. .............................
to + 7 V
±20mA
±20mA
±25mA
±50mA
POWER DISSIPATION PER PACKAGE (Po):
............... 500mW
For TA = -40 to +60°C (PACKAGE TYPE E) .............................................. .
For T A = +60 to +85 0C (PACKAGE TYPE E) ...................
. . .. . . .. .. . . .. . . . . .. . . . . .. Derate Linearly at 8 mwr C to 300 mW
For TA = -55 to +100 0C (PACKAGE TYPE F, H) ......................................................................... 500 mW
For TA = +100 to +125°C (PACKAGE TYPE F, H) ........................................... Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) ............................................................................ 400 mW
For T A = +70 to +125 0C (PACKAGE TYPE M) ............................................... Derate Linearly at 6 mwr C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .......................................................................................... -55 to +125 0C
PACKAGE TYPE E, M ........................................................................................... -40 to +85°C
STORAGE TEMPERATURE (T",) .................................................................................. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ........ .
Unit inserted into a PC Board (min. thickness 1/16 in .. 1.59 mm)
with solder contacting lead tips only ................................................................................. .
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (ForTA = Full Package-Temperature Range) Vcc:'
CD54/74HC Types
CD54/74HCT Types
DC Inputor Output Voltage V" Vo
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t" tf
at 2 V
at 4.5 V
at6 V
UNITS
MIN.
MAX.
2
4.5
a
6
5.5
Vee
V
V
V
-40
-55
+85
+125
DC
a
a
a
1000
500
400
ns
'Unless otherwise specified, all voltages are referenced to Ground.
14
1Y
1A
1B
1C
10
NC
GNO
2
13
3
12
4
11
5
10
6
9
7
8
VCC
2Y
20
2C
2B
2A
NC
92C5-39798
TERMINAL ASSIGNMENT
___________________________________________________________________ 463
Technical Data
CD 54/74HC4002
CD54/74HCT4002
STATIC ELECTRICAL CHARACTERISTICS
CD74HC4002/CD54HC4002
TEST
CONDITIONS
CD74HCT4002/CD54HCT4002
74HC/54HC
TYPES
74HC
TYPE
54HC
TYPE
TEST
CONDITIONS
+25'C
-401
+85'C
-551
+125°C
74HCT/54HCT
TYPES
74HCT
TYPE
54HCT
TYPE
+25°C
-401
+85°C
-551
+125'C
·CHARACTERISTIC
UNITS
V,
V
10
rnA
Vee
V
V,
V
Vee
V
Min" Typ Max Min Max Min Max
1.5
1.5
1.5
4.5
3.15
3.15
3.15
to
6
4.2
4.2
4.2
5.5
High-Level
Input Voltage
V"
Low-Level
Input Voltage
High-Level
Output Voltage
4.5
V"
V"
YO"
CMOS Loads
or
-0.02
4.5
V,"
4.5
0.5
0.5
0.5
1.35
1.35
1.35
to
1.8
1.8
1.8
5.5
Low-Level
Output Voltage
1.9
1.9
1.9
V"
4.4
4.4
4.4
or
5.9
5.9
5.9
V,"
3.98
3.84
3.7
or
5.48
5.34
5.2
V,"
-4
V,"
-5.2
CMOS Loads
or
4.5
0.02
0.1
0.1
0.1
V"
0.1
0.1
0.1
or
0.1
0.1
0.1
V,"
4.5
0.26
0.33
0.4
or
6
0.26
0.33
0.4
V,"
±1
Any
Voltage
Between
4.5
V,"
V"
TTL Loads
Input Leakage
5.2
Vee
-
or
Current
±O.l
±1
Quiescent
Vee
or
Current
I....
4.4
4.5
3.98
4.4
0.8
V
4.4
V
-
4.5
-
3.84
0.1
-
3.7
V
0.1
0.1
V
4.5
-
0.26
5.5
-
±O.l
-
0.4
V
±1
±1
pA
20
40
pA
490
pA
0.33
-
Vee
Gnd
Device
4.5
0.8
V"
or
V,"
0.8
V"
or
V"
Voc
V
4.5
V"
TTL Loads
Min Typ Max Min Max Min Max
& Grid
V"
6
20
40
Gnd
or
5.5
Gnd
Additional
Quiescent
Device Current
per input pin:
1 unit load
""Icc·
4.5
V,r2.1
to
100 360
450
-
5.5
'For dual-supply systems theoretical worst case (V,:: 2.4 V, V.... - 5.5 V) specification
IS
1.8 mA
HCT INPUT LOADING TABLE
INPUT
UNIT LOADS'
All
0.45
·Unit Load is ""Icc limit specified in Static Characteristic
Chart. e.g., 360 pA max. @l25' C.
464 _________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4002
CD 54/74HCT4002
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Inpul I" If = 6 ns)
TYPICAL
HC
HCT
9
8
12
8
22
22
CL
(pFJ
CHARACTERISTIC
Propagation Delay Time:
nA, nS, nC, nD to nY (Fig. 3)
Power Dissipation Capacitance'
tpLH
tPHL
Cpo
15
-
UNITS
ns
pF
'Cpo is used to determine the dynamic power consumption, per gate.
Po = Vee2f; (Cpo + Cel where: f; = input frequency
CL = output load capacitance
Vee = supply voltage .
SWITCHING CHARACTERISTICS (CL =50 pF, Inpul I" If =6 ns)
CHARACTERISTIC
Propagation Delay,
nA, nS, nC, nD
to nY (Fig. 3)
tpLH
tpHL
Transition Time
(Fig. 3)
Input
Capacitance
_40° C 10 +85° C
25°C
-55°C 10 +125°C
HC
HCT
74HC
74HCT
54HC
54HCT
UNITS
Min. Max, Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
100 125
150
20
22
28
25
30
33
17
21
26
100
125 150 20
29
25
36
30
44
ns
17
21
26
75
95
110 15
15
19
19
22
22
13
16
19
-
Vee
hLH
hHL
2
4.5
6
2
4.5
6
2
4.5
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
-
-
10
-
-
C,
10
-
-
10
'. ~ =¥1"".
INPUT
=_~
--------
IpHL
10
____
------vs
~
90%
10
pF
,INPUT
~
LEVEL
------10%
IpLH
OUTPUT
tTHL
92CS-37991
e,Vs
54174HC
Vee
50% Vee
54/74HCT
3V
1.3 V
Fig. 3 - Transition times and propagation delay times.
___________________________________________________________________ 465
Technical Vee +0.5 V) ....................................................... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR V. < -0.5 V OR V. > Vee +0.5 V) ................................................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < V. < Vee +0.5 V) .................................................... ±25 mA
DC Vee OR GROUND CURRENT, (Icc) ..................................................................................... ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For T A = -40 to +60· C (PACKAGE TYPE E) ............................................................................... 500 mW
For T. = +60 to +85· C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/· C to 300 mW
For T. = -55 to +100· C (PACKAGE TYPE F, H) .. , ........................................................................ 500 mW
ForT. = +100 to +125°C (PACKAGE TYPE F, H) ............................................. Derate Linearly at8 mW;oC to 300 mW
.................... 400 mW
For T. = -40 to +70°C (PACKAGE TYPE M)
For T. = +70 to +125°C (PACKAGE TYPE M)....
...........
................ Derate Linearly at6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (T A ):
PACKAGE TYPE F, H ............................................................................................. -55 to +125° C
PACKAGE TYPE E, M .............................................................................................. -40 to +85°C
STORAGE TEMPERATURE (T...) .................................................................................... -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
. .................................................... +265°C
Unit inserted into a PC Board (min. thickness 1116 in., 1.59 mm)
with solder contacting lead tips only ................................................................................... +300°C
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation Is always within
the 'ollowlng ranges:
CHARACTERISTIC
Supply-Voltage Range (For T A-Full Package Temperature Range)
Vee:'"
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage, V" Vo
Operating Temperature, TA:
CD74 Types
CD54 Types
Inpul Rise and Fall Times, t"I,:
al 2 V
al 4.5 V
al 6 V
LIMITS
UNITS
MIN.
MAX.
2
4,5
0
6
5.5
Vcc
-40
+85
+125
·C
1000
500
400
ns
-55
0
0
0
V
V
'Unless otherwise specified, all voltages are referenced to Ground.
468 ______________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4015
CD54/74HCT4015
STATIC ELECTRICAL CHARACTERISTICS
CD74HC4015/CD54HC4015
CD74HCT4015/CD54HCT4015
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+BSoC
+125°C
+85°C
'125°C
CHARACTERISTICS
UNITS
+25°C
V,
10
Vee
V
mA
V
High-Level
Input Voltage
Low-Level
Input Voltage
V"
High-Level
Output Voltage
1.5
-
-
1.5
-
1.5
4.5 3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
-
0.5
-
2
V,"
V"
Vo"
CMOS Loads
or
-0.02
V,"
Min Typ Max Min Ma. Min Ma.
2
-
-
0.5
4.5
-
-
1.35 -
1.35 -
6
-
-
1.B
-
1.8
Low-Level
Oulput Voltage
CMOS Loads
-
l.B
2
-
-
2
-
2
-
V
-
-
O.B
-
O.B
-
O.B
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
i±o. I -
±1
-
±1
I1A
5.5
-
-
-
80
-
160
I1A
-
100 360
-
450
-
490
I1A
to
5.5
4.5
-
to
5.5
2
1.9
-
-
1.9
-
1.9
-
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5 3.98
-
-
3.84
-
3.7
-
or
V"
V"
V,"
-5.2
6
5.48
-
-
5.34
-
5.2
-
V,"
2
-
V"
0.1
0.1
-
0.1
-
-
0.1
4.5
-
0.1
0.02
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
or
Min Typ Max Min Ma. Min Ma.
4.5
-
4.5
V"
V"
or
4
4.5
-
-
0.26
-
0.33
-
0.4
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
6
-
-
0.1
-
±1
-
Input Leakage
Current
V
-4
V,"
TTL Loads
V
or
V"
Voe
Vee
0.5
1.35
V"
TTL Loads
'25°C
V,
Any
I,
Voltage
Vee
or
Gnd
±1
Between
Vee and
Gnd
Quiescent Device
Current
Icc
Vee
or
Gnd
0
6
-
-
8
-
BO
-
160
Vee
or
Gnd
8
Additional
4.5
Quiescent Oevice
Vee -2.1
Current per
Input Pin:
1 Unit Load
to
5.5
.6.lce·
·For dual-supply systems theoretical worst case (VI
= 2.4 V, Vee = 5.5 V)
specification is 1.8 rnA.
HCT Input Loading Table
Input
DATA
CP
MR
Unit Loads'
0.15
0.45
0.15
'Unit load is I!J. Icc limit specified in Static Characteristics
Chart, e.g., 360 pA max. @ 25° C.
____________________________________________________________________ 469
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4015
CD54/74HCT4015
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Inpul In I, = 6 ns)
CHARACTERISTIC
Propagation Delay
CP to On
MR to On
Maximum Clock Frequency
Power Dissipation Capacitance'
Typical
CL
pF
HC
HCT
15
14
14
t pHl
I MAX
15
15
CPD
-
25
60
43
25
60
43
SYMBOL
t pHL
Unils
ns
tpLH
.
MHz
pF
'C po is used to determine the dynamic power consumption, per shift register.
PD=C PO Vee' Ii + L CL Vee' 10 where: li=input Irequency, lo=output Irequency
CL =Ioad capacitance
Vee=supply voltage
PREREQUISITE FOR SWITCHING FUNCTION
CHARACTERISTIC
Maximum Clock
Frequency
(See Fig. 3)
Clock Pulse
Width
(See Fig. 3)
MR Pulse Width
(See Fig. 4)
MR Recovery
Time
(See Fig. 4)
Setup Time
Data-In to'CP
(See Figs. 5 & 6)
Hold Time:
Data-I n to CP
(See Figs. 5 & 6)
SYMBOL
fMAX
tw
tw
tREe
tSuL
tSUH
tH
VCC
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
_40° C 10 +85° C
25°C
-55° C 10 +125° C
74HC
74HCT
54HC
54HCT UNITS
HC
HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
5
6
4
24
20
MHz
30
30
24
20
28
35
24
120 80
100 20
24
24
16
20
16
14
17
20
225 150 190 38
45
45
30
30
38
38
26
33
75
50
65
15
10
15
13
19
22
ns
13
11
9
75
90
60
20
24
16
15
18
12
13
15
10
-
0
-
0
-
0
-
0
-
0
-
0
-
SWITCHING CHARACTERISTICS (CL=50 pF, Input t"t,=6 ns)
CHARACTERISTIC
SYMBOL
Propagation Delay
Clock to On
MR to an
(Clock High)
MR to an
(Clock Low)
Output Transition
Time
I nput Capacitance
tPLH
tPHL
hLH
hHL
C,
VCC
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-
_40° C to +85° C
25°C
-55° C to +125° C
74HCT
54HC
54HCT UNITS
74HC
HC
HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
220 270 175 54
35
44
44
54
35
37
30
- 46 415 275 345 90
60
83
55
64
- 75 71
47
- 54 325 400 490 98
ns
65
65
81
81
98
55
83
- 69 75
110 95
15
15
19
19
22
- 22 13
16
19
- 10
10
10
pF
10
- 10 - 10 -
470 ________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4015
CD54/74HCT4015
INPUT LEVEL
I'----GND
MR
CP
ANY
OUTPUT
ANY
OUTPUT
CP
92CS~3B477
~
_ _ _ _ _ _ _ _-',1V S _
INPUT LEVEL
GND
92CS-38478
Fig. 3 - Clock-to-output delays and clock pulse width.
Fig. 4 - Master Reset pulse width. Master Reset to output.
delay and clock recovery times.
INPUT LEVEL
DATA
GND
CP
CP
'----GND
'----GND
92CS- 38480RI
92CS-38479RI
Fig. 6 - Data set-up and hold times.
Fig. 5 - Data set-up and hold times.
Input Level
Switching Voltage, Vs
54/74HC
VCC
50%VCC
54/74HCT
3V
1.3 V
I
I
I
___________~-------__- - - - - - - - - - - - - - - - - - -__--471
TechnicaIOata _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54l74HC4017
CD54l74HCT4017
File Number 1639
High-Speed CMOS Logic
3
CLOCK
14
0
1
I-
3
....
«
:Il
4
(;
4
CLOCK
ENABLE
13
7
10
MASTER 15
RESET
5
6
9
11
::>
0
IU
5
0
6
IU
7
0
B
.Decade CounterlDivider with
10 Decoded Outputs
Q
Q
Type Features:
• Fully static operation
• Buffered inputs
• Common reset
• Positive edge clocking
• Typical f MAX = 50 MHz @ Vee = 5 V, CL = 15 pF, TA = 25 0 C
U
IU
Q
9
12 TERMINAL
COUNT
92CS-38460
FUNCTIONAL DIAGRAM
CD54174HC4017, CD54/74HCT4017
The RCA-CD54/74HC4017 and CD54174HCT4017 are high
speed silicon gate CMOS 5-stageJohnson counters with 10
decoded outputs. Each of the decoded outputs is normally
low and sequentially goes high on the low to high transition
of the CLOCK (CP) input. Each output'stays high for one
·clock period of the 10 clock period cycle. The CARRY (TC)
output transitions low to high after OUTPUT 10 goes low,
and can be used in conjunction with the CLOCK ENABLE
(CE) to cascade several stages. The CLOCK ENABLE input
disables counting when in the high state. A RESET (MR)
input is also provided which when taken high sets all the
decoded outputs, except "0", low.
The device can drive up to 10 low power Schottky equiva. lent loads. The CD54174HCT4017 is an enhanced version of
equivalent CMOS types.
The CD54HC4017 and CD54HCT4017 are supplied in
16-lead ·hermetic dual-in-line ceramic packages (F suffix).
The CD74HC4017 and CD74HCT4017 are supplied in
16-lead dual-in-line plastic packages (E suffix) and in
16-lead dual-in-line surface mount .plastic packages
(M suffix). Both types are also available in chip form
(Hsuffix).
Family Features:
• Fanout (Over. Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85 0 C
• Balanced Propagation Delay and Transition Times
.• Significant Power Reduction Compared to
LSTTL Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity: ML = 30%, N'H = 30% of Vee
@ Vee = 5V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, :S 1/lA @ VOL, V OH
5
16
vcc
15
MR
TRUTH TABLE
CP
CE
MR
Output State"
L
X
X
X
H
X
L
X
./
L
L
H
L
L
L
L
No Change
No Change
"O"=H, "1 "-"9"=L
Increments Counter
No Change
No Change
Increments Counter
..r
'X
H
'-
H = High Level
L = Low Level
' - = High-to-Low Transition
/ = Low-to-High Transition
X=Don't Care
'If n<5 TC=H,Otherwise=L
14
CP
4
13
CE
5
12
6
11
0
6
10
3
GNO
6
TC
9
4
B
92CS- 38459
TERMINAL ASSIGNMENT
472 ___________________________________________
______ Technical Data
CD54/74HC4017
CD54/74HCT4017
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE (Vee)
(Voltages referenced to ground)
DC INPUT DIODE CURRENT. I,. (FOR V, < -0.5 V OR V, > Vee +05 V) .
DC OUTPUT DIODE CURRENT. 10K (FOR Va < -0.5 V OR Va > Vee +0.5 V)_
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Va < Vee +0.5 V) .
DC Vee OR GROUND CURRENT, (Ice) ....
POWER DISSIPATION PER PACKAGE (Po)
For TA = -40 to +60°C (PACKAGE TYPE E)
For TA = +60 to +85°C (PACKAGE TYPE E) ....
For TA = -55 to +100°C (PACKAGE TYPE F, H).
For TA = +100 to +125°C (PACKAGE TYPE F, H)
For T. ; -40 to +70° C (PACKAGE TYPE M) ...... .
For T.; +70 to +125°C (PACKAGE TYPE M)
........................ -0.5 to +7 V
± 20 mA
±20 mA
± 25 mA
±50 mA
......... 500 mW
_. Derate Linearly at 8 mW/oC to 300 mW
. ............... 500 mW
. . Derate Linearlv at 8 mwrc to ~no mW
.................. .......
400 mW
Derate Linearly at 6 mW/o C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H ..... .
PACKAGE TYPE E, M.
STORAGE TEMPERATURE (T",) ..
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only
"0"
"1"
"2"
"4"
..... -55 to +125°C
. ......... -40 to +85°C
. _-65 to +150°C
...................... +265°C
........ +300°C
"7"
"a"
"9'1
TC
6()
MR
CE
14
CP()----------------------~
92CL-36461Rt
Fig. 1 - Logic diagram for the CD54/74HC/HCT 4017
_____________________________________________________ 473
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4017
CD54/74HCT4017
.
STATIC ELECTRICAL CHARACTERISTICS
CD74HC4017/CD54HC4017
C D74HCT4017/C D54HCT4017
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/S4HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+8SoC
+125°C
CHARACTERISTIC
UNITS
Vo
10
Vee
V
mA
V
+2SoC
+85°C
+125°C
Vo
Vee
V
V
Min Typ Ma. Min Ma. Min Ma.
High-Level
Input Voltage
Vo"
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
Vo"
CMOS Loads
or
-0.02
V o"
2
1.5
-
-
1.5
-
1.5
-
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
5.5
-
0.5
-
0.5
4.5
1.35
-
1.35
1.8
-
1.8
2
-
-
0.5
-
-
1.35
6
-
-
1.8
Low-Level
Output 'Voltage
CMOS Loads
2
1.9
-
-
1.9
-
1.9
-
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
VO"
-
-
3.84
-
3.7
-
or
VO"
-5.2
6
5.48
-
-
5.34
-
5.2
-
VO
"
2
-
-
0.1
-
0.1
-
0.1
V"
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
VO
"
10
4
4.5
-
-
0.26
-
0.33
-
0.4
or
VO"
5.2
6
-
-
0.26
-
0.33
-
0.4
VO"
or
Quiescent
Vee
or
Current
Icc
.-
0.8
-
0.8
V
-
4.4
~
4.4
-
V
-
-
3.84
-
3.7
-
V
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
pA
5.5
-
-
8
-
80
-
160
pA
4.5
to
5.5
-
100 360
-
450
-
490
pA
-
-
0.8
4.5
4.4
-
4.5
3.98
4.5
to
Any
Voltage
6
-
-
±0.1
-
±1
-
±1
6
-
-
8
-
80
-
160
Gnd
Device
V
2
V"
or
Vee
Current
-
-
V"
3.98
V"
Input Leakage
2
-
V"
4.5
or
-
2
to
5.5
-4
VO
"
TTL Loads
-
or
V"
Yo,
4.5
-
4.5
V"
TTL Loads
Min Typ Ma. Min Ma. Min Ma.
4.5
4.5
+25°C
Between
Vee
&
Gnd
Vee
0
or
Gnd
Gnd
Additional
Quiescent
Device Current
per input pin:
1 unit load
6lcc'
Vee -2.1
"For dual-supply systems theoretical worst case (Vo = 2.4 V, Vee = 5.5 V) specification is 1.8 mAo
HCT Input Loading Table
Input
Unit Loads·
-CP
CE
0.15
MR
0.3
0.25
'Unit load is t.lcc limit specified in Static Characteristic Chart, e.g., 360 pA max. @ 25°C.
474 ________________________________________________________________
__
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4017
CD54/74HCT4017
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within the
following ranges:
LIMITS
CHARACTERISTIC
UNITS
MIN.
Supply-Voltage Range (For TA
MAX.
= Full Package Temperature Range) Vee:'
CD54/74HC Types
CD54174HCT Types
DC Input or Output Voltage V" Vo
2
6
V
4.5
5.5
V
a
Vee
V
Operating Temperature TA:
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
a
a
a
1000
ns
500
ns
400
ns
Input Rise and Fall Times, t" tf
at 2V
at 4.5 V
at 6V
..
'Unless otherwise specified, all voltages are referenced to Ground .
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Inpul I, If = 6 ns)
CHARACTERISTIC
Propagation Delay
CP to Oul
CP to TC
SYMBOL
t pLH
t pHL
t PLH
CL
Typical Values
UNITS
(pF)
HC
HCT
15
19
19
ns
15
19
19
ns
15
21
21
ns
15
21
21
ns
tPHL
CE to Out
t PLH
t pHL
-
t pLH
CE to TC
tpHL
MR to Out
t pLH
t pHL
15
19
19
ns
MR to TC
t pLH
t pHL
15
19
19
ns
Max. CP Frequency
fMAx
15
60
50
MHz
Power Dissipation Capacitance'
C PD
-
39
39
pF
'CPD is used to determine the dynamic power consumption, per package.
PD = CPD Vee 2 fi + I C L V ee 2 fo where fi = input frequency.
fo = output frequency.
C L = output load capacitance.
Vee = supply voltage.
________________________________________ 475
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4017
CD54/74HCT4017
PREREQUISITE FOR SWITCHING FUNCTION
LIMITS
TEST
CONDITION
CHARACTERISTIC
Vee
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
tw
MR Pulse Width
tw
Max. Clock Freq. fCl (max.)
CEto CP
Setup Time
tsu
CE to CP
Hold Time
tH
MR Removal Time
tREM
74HC
HCT
-55°C to +125°C
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
v
CP Pulse Width
-40°C to +85°C
25°C
HC
80
16
14
80
16
14
6
30
35
75
15
13
0
0
0
5
5
5
-
16
-
-
-
-
16
-
-
-
-
25
15
-
-
-
-
-
-
-
0
5
-
-
100
20
17
100
20
17
5
35
49
95
19
16
0
0
0
5
5
5
-
-
20
-
-
-
-
-
20
-
-
-
-
20
-
-
-
-
19
0
-
5
-
-
-
-
-
120
24
20
120
24
20
4
20
23
110
22
19
0
0
0
5
5
5
-
-
24
-
-
-
-
-
-
24
-
17
-
-
-
-
22
0
-
-
-
-
5
-
-
-
ns
ns
MHz
ns
ns
ns
SWITCHING CHARACTERISTICS (Cl = 50 pF, Input t" If = 6 ns)
CHARACTERISTIC
SYMBOL
Vee
tPLH
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
Propagation Delay
CPto any
Dec. Out
t PHL
CPto TC
t PHL
tPLH
-
CE to any
Dec. Out
CE to TC
MR to any
Dec. Out
MR to TC
Transition Time
TC, Dec. Out
Input Capacitance
tpl.H
tPHL
tPlH
t pHL
t PLH
tPHL
tPlH
t PHL
hHL
hLH
C,N
25°C
-40°C to +85°C
-55°C 10 +125°C
HC
HCT
74HC
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
-
-
-
-
-
-
-
46
46
-
-
-
-
230
46
39
230
46
39
250
50
43
250
50
43
230
46
39
230
46
39
75
15
13
-
10
-
-
-
-
-
-
-
-
-
-
15
-
-
290
58
49
290
58
49
315
63
54
315
63
54
290
58
49
290
58
49
95
19
16
-
10
-
10
-
-
-
-
-
-
50
-
-
-
-
-
50
-
-
-
-
-
46
46
-
-
-
-
-
-
-
58
58
-
-
-
-
-
-
-
-
-
64
-
-
375
75
-
-
-
-
-
64
75
-
-
-
63
63
58
-
345
69
59
345
69
59
375
75
-
-
-
58
-
-
-
-
-
-
-
19
-
-
345
69
59
345
69
59
110
22
19
-
10
-
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
69
ns
-
69
-
ns
-
75
ns
-
ns
-
69
ns
-
69
-
ns
-
-
-
ns
-
22
-
-
10
pF
476 _______________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4017
CD54/74HCT4017
INPUTLEVEL
1
!MAX
tPLH.....j
~ltPHL
tPLH---I
NPUTLEVEL
tpLH
tw
tpHL GND
DECODED~
GtPHL
OUTPUT
~_...J1
r.:-vstPLH
_ __
"O",TC
"--
CLOCK ~S INPUT LEVEL
ENABLE
Vs
~
GND
1
GND
~rtPHL
~vs'
~
OUTPUT
"1"-"9"
Vs
GND
DECODED~VS
RESET
~
tw
CLOCK
CLOCK
,r-------INPUT LEVEL
vs
--GND
CLOCK
ENABLE
~INPUTLEVEL
Vs
- - INPUT LEVEL
CLOCK
---GND
'----GND
tp~r-J ~
TC
~
92CL-38462RI
CLOCK
RESET
''-----+---- GND
CLOCK
ENABLE _ _ _ _ _ _~
r----=.:....- INPUT LEVEL
---GND
Transition times and propagation delay times,
CLOCK
MASTER
RESET-,~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
------------------------~~
"I"
""m'--_____________f2L
"2" _ _ _
"3" _ _ _ _--1(3"\\.._ _ _ _ _ _ _ _ _ _ _ _ _ __
____________
___________
"6" ________________
___________________
"4"' _ _ _ _ _--Jm~
"5"' _ _ _ _ _ _--Jm~
~m~
"7"
R-------------~~----~
FF DETAIL
"8"
f71~
_________
f"'ii'l~
_____________
92CS-40490
"9"
f9l
TERMINAL::::::::::::::::::~----------~
~::::::::::::::
COUNT
92CM-38463
Timing diagram for the CD54174HCIHCT4017
__________________________________________________________________ 477
TechnicaIOata _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD 54/74HC4020
CD54/74HCT4020
File Number 1484
High-Speed CMOS Logic
II
9
INPUT
PULSES
14-Stage Binary Counter
01'
7 0<
•4 o.
••
07
a
13 Q8
11.1
6
..... UAGE
RIPPLE
COUNTER
::
~~o ~
'5 011
I
012
! .'4
Q!3
MASTER RESET
"----rc--'
GNO
Type Features:
• Fully static operation
• Buffered inputs
• Common reset
• Negative edge pulsing
.
• Typical fMAX = 50 MHz @ Vee = 5 V, CL = 15, T.. = 250 C
FUNCTIONAL DIAGRAM
The RCA-CD54174HC4020 and CD54/74HCT4020 are 14stage ripple-carry binary counters. All counter stages are
master-slave flip-flops. The state of the stage advances one
count on the negative transition of each input pulse; a high
voltage level on the MR line resets all counters to their zero
state. All inputs and outputs are buffered.
The CD54HC4020 and CD54HCT4020 are supplied in 16lead hermetic dual-in-line ceramic packages (F suffix). The
CD74HC4020 and CD74HCT4020 are supplied in 16-lead
dual-in-line plastic packages (E·suffix) and in 16-lead dualin-,Iine surface mount plastic package (M suffix). Both
types are also available in chip form (H suffix).
TRUTH TABLE
rfJ
MR
Output State
f
L
No Change
..............
L
Advance to next state
H
All Outputs are low
X
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85 0 C
• Balancad Propagation Delay and Transition Times
• Significant Power Reduction Compared to
LSTTL Logic ICs
• Alternate Source is Philips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity: NoL = 30%, NoH=30% of Vee;
@Vee=5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L=0.8 V Max., V'H=2 V Min.
CMOS Input Compatibility
I, :5 1 pA @ VOL, VOH
H = high level (steady state)
L = low level (steady state)
X = don't eare
9ZCL-37019A3
Fig. 1 - Logic block diagram.
478 ______________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4020
CD54/74HCT4020
MAXIMUM RATINGS. Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground)
.... -0.5 to + 7 V
±20mA
±20rnA
......................... .
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5V) ................ .
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V)
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V) .'
±25mA
±50mA
DC Vee OR GROUND CURRENT (lcel ..
POWER DISSIPATION PER PACKAGE (P D ):
For TA = -40 to +60° C (pACKAGE TYPE E)
For TA = +60 to +85°C (PACKAGE TYPE E)
.500 mW
Derate Linearly at 8 mW;oC to 300 mW
For TA = -5510 +100'C (PACKAGE TYPE F, H) ......
For TA = +100 to +125'C (PACKAGE TYPE F, H)
. .... 500 mW
Derate Linearly at 8 mW;oC to 300 mW
ForTA =-40to+70'C(PACKAGETYPEM) ......................................................................... 400mW
For TA = +70 to 125°C (PACKAGE TYPE M) ............................................. Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA)
PACKAGE TYPE F, H ...
PACKAGE TYPE E, M
-55 to +125'C
-40 to +85'C
....... -65 to +150'C
STORAGE TEMPERATURE (T",)
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in., ".59 mm)
with solder contacting lead tips only
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability. nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TrFu11 Package Temperature Range)
Vcc:'
CD54/74HC Types
CD54174HCT Types
DC Input or Output Voltage Vin , Va",
Operating Temperature T A:
CD74 Types
CD54 Types
Input Rise and Fall Times t"t,
at 2 V
at 4.5 V
at 6 V
LIMITS
UNITS
MIN.
MAX.
2
4.5
a
6
5.5
Vcc
V
V
V
-40
-55
+85
+125
°C
°C
a
a
a
1000
500
400
ns
ns
ns
'Unless otherwise specified. all voltages are referenced to Ground.
F/F10NLY
>O---+-~Q'
Fig. 2 - Detail for flip-flops 1. 2, 3, 5, 6, 8,10, 11, 13 & 14.
Fig. 3 - Detail for flip-flops 4, 7, 9 & 12.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 479
Technical.Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD 54/74HC4020
CD54/74HCT4020.
STATIC ELECTRICAL CHARACTERISTICS
CD74HC4020/CD54HC4020
TEST
CONDITIONS
74HC/54HC
TYPES
CD74HCT4020/CD54HCT4020
74HC
TYPES
54HC
TYPES
-401
+85°C
-551
+125'C
TEST
74HCTI54HCT
CONDITIONS
TYPES
74HCT
TYPES
54HCT
-401
+85'C
-551
+125'C
TYPES
CHARACTERISTIC
UNITS
+25°C
V,
10
V
mA
Vee
V
+25'C
V,
V
Vee
V
Min TyP Max Min Max Min Max
High-Level
1.5
-
-
1.5
-
1.5
-
4.5 3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
2
Input Voltage
V'H
Low-Level
Input Voltage
V"
High-Level
V"
Output Vollage
VOH
CMOS Loads
or
-0.02
V'H
Low-Level
Voe
-4
V'H
-5.2
CMOS Loads
or
0.02
V'H
2
-
-
0.5
-
0.5
-
0.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V'H
4.5 3.98
-
-
3.84
-
3.7
-
or
6
5.48
-
-
5.34
-
5.2
-
V'H
2
-
-
0.1
-
0.1
-
0.1
V"
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V'H
V"
TTL Loads
Input Leakage
I,
-
0.26
-
0.33
-
0.4
V'H
5.2
6
-
-
0.26
-
0.33
-
0.4
V'H
Any
Voltage
Between
Vee
&Gnd
or
6
-
-
to.1
-
±1
-
±1
6
-
-
8
-
80
-
160
Gnd
or
Current
Icc
2
-
2
-
V
to
-
-
0.8
-
0,8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
3.7
-
V
4.5 3.98
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
to.1
-
±1
-
±1
IlA
5.5
-
-
8
-
80
-
160
IlA
-
100 360
-
450
-
490
IlA
V"
-
Vee
-
V"
4.5
Device
-
5.5.
4
Quiescent
2
4.5
-
or
Vee
Current
to
5.5
V"
or
V"
Output Vollage
4.5
-
4.5
V"
TTL Loads
Min Typ Max Min Max Min Max
or
Vee
0
or
Gnd
Gnd
Additional
Quiescent
Device Current
per input pin:
dlee
1 unit load
4.5
Vcc-2 .1
to
5.5
°Fordual-oupply syotemotheoretlcal worst case (V, = 2.4 V, Vee = 5.5 V) opeclflcatlon is 1.8 mA.
-HCT Input Loading Table
Input
MR
0
Unit Loads'
0.65
0.5
*Unit Load is 81cc limit specified in Static Characteristic Chart,
e.g., 360/lA max. @ 25' C.
4~
CO2
" Vee
COl
15
CO<
14 010
a"
co
13 08
co
12 09
C7
11 MR
'"
"'"
GNO
9 Q1'
TERMINAL ASSIGNMENT
____________________________________________________________________
__
- - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4020
CD54/74HCT4020
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Inpul I" I, = 6 ns)
CHARACTERISTIC
CL
pF
HC
HCT
t pLH
t pHl
15
11
17
Propagation Delay ¢ to 01' Output
an to an.
Delay MR to an
Propagation Delay
Typical
SYMBOL
t plH
1
t pHL
t pHl
Propagation
Power Dissipation Capacitance'
ns
15
6
6
ns
15
14
30
17
30
MHz
pF
-
Cpo
Unils
'CPO is used to determine the power consumption, per package.
PD = Cpo Vcc 2 fi + I (C L Vcc 2 filM) where:
M = 2', 2', 2' ... 2"
CL = output load capacitance
fi = input frequency
Pre-requlslle for Swllchlng Funcllon
CHARACTERISTIC
Maximum Input Pulse
Frequency
Input Pulse Width
(Figure 4)
Reset Removal Time
(Figure 5)
Reset Pulse Width
(Figure 5)
SYMBOL Vcc
'MAX
tw
tREM
tw
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
_55° C 10 +125° C
_40° C 10 +85° C
25°C
54HCT
UNITS
74HC
74HCT
54HC
HC
HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
4
5
6
16
MHz
20
20
30
25
25
35
29
24
120 100 80
25
24
30
ns
16
20
20
17
20
14
65
75
50
15
15
ns
10
10
13
13
13
9
11
120 100 80
25
24
30
ns
16
20
20
20
17
14
-
SWITCHING CHARACTERISTICS (CL=50 pF, Inpul 1,,1,=6 ns)
CHARACTERISTIC
Propagation Delay
¢ to 01' Output
(Figure 4)
Propagation Delay
an to On+1
(Figure 4)
Propagation Delay
MR to an
(Figure 5)
Output Transition
Time
(Figure 4)
Input Capacitance
SYMBOL Vec
tpLH
tPHL
t PLH
tPHL
tPHL
hLH
hHL
C,
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
_55° C 10 +125° C
-40° C 10 +85° C
25°C
HCT
74HC
74HCT
54HC
54HCT
UNITS
HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
140 175
210 28
35
40
50
42
60
ns
24
36
30
75
95
110 ns
15
19
22
15
22
19
13
16
19
170 215 255 50
34
40
ns
51
60
43
43
29
37
75
95
110 15
15
19
19
22
ns
22
13
16
19
-
10
-
10
-
10
-
10
-
10
-
10
pF
________________________________________________________________ 481
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4020
CD54/74HCT4020
INPUT
INPUT
INPUT
92C$-3702IRl
_Q"~/
92CS-37022R2
INPUT LEVEL
Fig. 4 -1nput pulse pre-requisite times, propagation
delays and output transition times.
INPUT LEVEL
Fig. 5 - Master Reset pre-requisite and propagation delays.
482 ________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
File Number
CD54/74HC4024
CD54/74HCT4024
1683
High-Speed CMOS Logic
12
01'
11 02
9
6
MR. 2
5
4
3
7-Stage Binary Ripple Counter
03
04
05
06
07
Type Features:
• Fully static operation:
• Buffered inputs:
• Common reset
• Typical fMAX = 50 MHz@ Vee = 5 V, CL = 15 pF, TA = 25°C
92es-38450RI
CD54n4HC4024, HCT4024
FUNCTIONAL DIAGRAM
The RCA-CD54174HC4024 and CD54175HCT4024 are 7stage ripple-carry binary counters. All counter stages are
master-slave flip-flops. The state of the stage advances one
count on the negative transition of each input pulse; a high
voltage level on the MR line resets all counters to their zero
state. All inputs and outputs are buffered.
The CD54HC4024 and CD54HCT4024 are supplied in 16lead hermetic dual-in-line ceramic packages (F suffix). The
CD74HC4024 and CD74HCT4024 are supplied in 16-lead
dual-in-line plastic packages (E suffix) and in 16-lead dualin-line surface mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
Family Features:
• Fanout (over temperature range):
Standard outputs - 10 LSTTL loads
Bus driver outputs - 15 LSTTL loads
• Wide operating temperature range:
CD74HC/HCT: -40 to +850 C
• Balanced propagation delay and
transition times
• Significant power reduction compared to
LSTTL logic ICs
• Alternate source is Philips/Signetics
• CD54HC/CD74HC types:
2 to 6 V operation
High noise immunity: ML= 30%, MH=30% of Vee
@ Vee =5 V
• CD54HCT/CD74HCT types:
4.5 to 5.5 V operation
Direct LSTTL input logic compatibility
V,L=0.8 V max., V'H=2 V min.
CMOS input compatibility
1,:0; 1 JiA @Vo L, VO H
TRUTH TABLE
¢
MR
OUTPUT STATE
L
No Change
~
L
Advance to Next State
X
H
All Outputs are Low
_r
H = high level (steady state)
L = low level (steady state)
X = don't care
92CM-'B'I:)IR3
Fig. 1 - Logic diagram for the CD54/74HC/HCT4024.
_____________________________________________________________ 483
TechnicaIOata _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4024
CD54/74HCT4024
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ...................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, 1,K (FOR V, < -0.5 V OR V, > Vee +O.S V) ....................................................... ±20 rnA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -O.S V OR Vo > Vee +O.S V) ................................................... ±20 rnA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -O.S V < Vo < Vee +0.5 V) .................................................... ±2S rnA
DC Vee OR GROUND CURRENT, (Icc) ..................................................................................... ±SO rnA
POWER DISSIPATION PER PACKAGE (Po):
For T. =-40 to +60° C (PACKAGE TYPE E) ............................................................................... SOO mW
For T. =+60 to +85° C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW;o C to 300 mW
For T. =-S5 to +1 OO°C (PACKAGE TYPE F, H) .................................. , ........................................ SOO mW
ForT. =+100 to +12SoC (PACKAGE TYPE F, H) ............................................. Derate Linearly at 8 mW/oC to 300 mW
For TA =-40 to +70°C (PACKAGE TYPE M) ............................................................................. 400 mW
For TA = +70 to +12SoC (PACKAGE TYPE M) ............................................... Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H ............................................................................................. -55 to +12SoC
PACKAGE TYPE E, M .............................................................................................. -40 to +8So C
STORAGE TEMPERATURE (Tot.) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
+265°C
Unit inserted into a PC Board (min. thickness 1116 in., 1.S9 mm)
with solder contacting lead tips only ................................................................................... +300° C
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation Is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For T A-Full Package Temperature Range)
Vee:"
CD54/74HC Types
CD54/74HCT Types
DC Inpul or Output Voltage, V" Vo
Operating Temperature, TA:
CD74 Types
CD54 Types
Inpul Rise and Fall Times, t"I,:
at 2 V
at 4.5 V
at 6 V
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
V
V
'Unless otherwise specified, all voltages are referenced to Ground .
.>0----01'
Q
0
92CS- 40280
FLlP.FLOP DETAIL
92CM-38452RI
Fig. 2 - Flip-flop No.1 detail.
Fig. 3 - Detail for flip-flops 2 through 7.
484 _______________________________________________________
- - - - - - - - - - - - - - - - - - -___________ Technical Data
CD54/74HC4024
CD 54/74HCT4024
STATIC ELECTRICAL CHARACTERISTICS
CD74HC4024/CD54HC4024
CD74HCT4024/CD54HCT4024
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
UNITS
CHARACTERISTICS
+25°C
V,
10
Vee
V
mA
V
2
High-Level
Input Voltage
6
Low-Level
2
I nput Voltage
4.5
V"
6
High-Level
Vo"
CMOS Loads
4.2 - -- 1.9 1.5
or
-0.02
V,"
-
1.5
-
1.5
3.15
-
3.15
-
4.2
-
4.2
0.5
-
0.5
-
0.5
1.35
-
1.35
-
1.35
1.8
1.8
Low-Level
Vo,
CMOS Loads
2
-
-
2
-
2
-
V
-
-
O.B
-
O.B
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
ft 01 -
±1
-
±1
pA
5.5
-
-
-
80
-
160
pA
-
450
-
490
pA
to
5.5
4.5
-
1.8
to
5.5
-
1.9
-
1.9
4.4
-
-
4.4
-
4.4
6
5.9
-
-
5.9
-
5.9
-
4.5 3.98
-
3.84
-
or
-
5.34
-
3.7
5.48
-
5.2
-
V,"
V"
V"
or
V,"
V"
V,"
-5.2
6
2
-
0.1
-
0.1
-
0.1
0.02
4.5
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
-
0.26
-
0.33
-
0.4
or
0.26
-
0.33
-
0.4
V,"
or
Min Typ MIX Min Mo. Min Ma.
4.5
-4
V,"
V"
TTL Loads
V
or
V"
Output Voltage
V
-
V"
TTL Loads
Vee
4.5
2
V"
Output Voltage
Min Typ Mil Min MIX Min Mo.
4.5 3.15
V,"
+25°C
V,
V"
or
4
4.5
-
V,"
5.2
6
-
Input Leakage
Any
Current
I,
Quiescent Device
Current
lee
Vee
or
Gnd
Vee
or
Gnd
6
-
-
±0.1
-
±1
-
±1
6
-
-
8
-
BO
-
160
Voltage
Between
Vee and
Gnd
Vee
0
or
8
Gnd
Additional
Quiescent Device
4.5
Current per
Vee -2.1
Input Pin:
1 Unit Load
to
-
100 360
5.5
I:l.lcc
*For dual-supply system', theoretical worst case (VI
HCT Input Loading Table
=2.4 V, Vee =5.5 V) specification
is 1.8 mA.
14
¢
07
06
OS
'Unit Load is Ll.lcc limit
specified in Static
Characteristics Chart,
e.g., 360 JlA max.@25°C.
04
Vcc
13 NC
12 01'
MR
4
11
S
10
6
02
NC
03
8
GND
NC
TOPVIEW
92CS-38453RI
TERMINAL ASSIGNMENT
485
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4024
CD54/74HCT4024
SWITCHING CHARACTERISTICS (Vee=5 V, TA=25°C, Input t"t,=6 ns)
CHARACTERISTIC
Propagation Delay
¢ to 01'
SYMBOL
tPHL
C L (pF)
15
TYPICAL VALUES
HC
HCT
17
11
UNITS
tpLH
tPHL
On to On+l
t pLH
MR to On
tPlH
tPHL
Power Dissipation Capacitance"
Cpo
15
6
6
15
14
17
-
30
30
ns
pF
"Cpo is used to determine the dynamic power consumption, per package.
Po = Cpo Vee 2 fi + I (CL Vee 2 filM) where:
M=2' ,22,23,24,25,26,27
C L =output load capacitance
fi=input frequency
Prerequisile lor Switching Function
CHARACTERISTIC
Maximum Input
Pulse Frequency
Input Pulse Width
Reset Removal Time
Reset Pulse Width
SYMBOL
f MAX
tw
tREM
tw
VCC
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-55"C to -I:125°C
25°C
-40°C to +85°C
HC
54HC
54HCT
UNITS
HCT
74HC
74HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
6
5
4
30
25
24
20
20
16
MHz
35
24
29
80
100
120
16
20
20
25
24
30
14
17
20
50
65
75
10
10
13
13
15
15
ns
9
11
13
100 120 80
16
20
20
25
24
30
14
17
20
-
SWITCHING CHARACTERISTICS (C L =50 pF, InplJI 1,,1, =6 ns)
CHARACTERISTIC
Propagation Delay,
¢ 10 01' Output
Propagation Delay
Qn to On+l
Propagation Delay
MRtoQn
Output Transition
Time
Input Capacitance
SYMBOL
tPLH
tPHL
tPLH
tPHL
tPHl
hLH
trHL
C,
VCC
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-
25°C
-40°C to +85°C
-55"C to -I:125°C
HC
HCT
74HC
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
140
175
210
28
40
35
50
42
60
ns
24
30
36
110
75
95
15
19
22
15
ns
19
22
13
13
19
170
255
215
34
40
51
60
ns
43
50
29
43
27
75
95
110
15
15
19
19
22
22
ns
13
16
19
10
10
10
10
10
10
pF
-
486 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4024
CD54/74HCT4024'
tr1rl~tf
INPUTLEVEL~---
Vs
fNPUTLEVEL-~--
4>
tw
Vs
Vs
Vs
'rem
tpLH
tpHL
Ql'
92CS-38454RI
92CS-38455R2
Input Level
Switching Voltage, Vs
Fig, 4 - Input Pulse pre-requisite times, propagation delays
and output transition times.
I
I
I
54174HC
VCC
50% Vee
54174HCT
3V
1.3 V
J
I
I
Fig. 5 - Master Reset pre-requisite and propagation delays.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 487
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4040
CD54/74HCT4040
File Number
1483
High-Speed CMOS Logic
,.
Vee
~~fl~
'0
INPUT
PULSES
504
3 05
is
,:~; J~
12-STAGE
RIPPLE
COUNTE.R
09
4010
15 011
i
N
-
I 012
MASTER RESET
L----,;:--'
Gnd
12-Stage Binary .Counter
~
92CS-29066R2
Type Features:
•
•
•
•
•
Fully static operation
Buffered inputs
Common reset
Negative edge pulsing
Typical fMAX =50 MHz @ Vee
=5 V,
CL
= 15 pF,
TA
=25
0
C
FUNCTIONAL DIAGRAM
The RCA-CD54/74HC4040 and CD54/74HCT4040 are 12stage ripple-carry binary counters. Ali counter stages are
. master-slave flip"flops. The state. of the stage advances one
count on the negative transition of each input pulse; a high
voltage level on the MR line resets ali stages to their zero
state. Ali inputs and outputs are buffered.
The CD54HC4040 and CD54HCT4040 are supplied in 16lead hermetic dual-in-line ceramic packages (F suffix). The
CD74HC4040 and CD74HCT4040 are supplied in 16-lead
dual-in-line plastic packages (E suffix) and in 16-lead dualin-line surface mount plastic package (M suffix). Both
types are also available in chip form (H suffix).
TRUTH TABLE
~
MR
Output State
....r
L
No Change
'-
L
Advance to next state
X
H
Ali Outputs are low
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
.• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +850 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to
LSTTL Logic ICs
• Alternate Source is PhilipslSignetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity: ·ML=30%,MH=30% of Vee
@ Vee=5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L=0.8 V Max., V'H=2 V Min.
CMOS Input Compatibility
I, :S 1 pA @ VOL. VO H
H = high level (steady state)
L = low level (steady state)
X = don't care
Fig; 1 - Logic block diagram.
488 .
~
92CL-37015R3
_____________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4040
CD54/74HCT4040
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground)
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5V)
DC OUTPUT DIODE CURRENT, 10K (FOR V" < -0.5 V OR V" > Vee +O.SV)
DC DRAIN CURRENT, PER OUTPUT (I") (FOR -0.5 V < V" < Vee + 0.5V)
.... -0.5 to + 7 V
...... ±20mA
±20mA
±25mA
±50mA
DC Vee OR GROUND CURRENT (Icc) ....
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60"C (PACKAGE TYPE E)
.500mW
Derate linearly at 8 mWI" C to 300 mW
............................ 500mW
For T A = +60 to +85" C (PACKAGE TYPE E) ...
For TA = -55 to +100"C (PACKAGE TYPE F, H)
For TA = +100 to +125"C (PACKAGE TYPE F, H) ..........................
. .... Derate Linearly at 8 mW/"C to 300 mW
For TA = -40 to +70" C (PACKAGE TYPE M) ......................................................................... 400 mW
For TA = +70 to +12S o C (PACKAGE TYPE M)............................................ Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H ...... ..
PACKAGE TYPE E, M ................. .
STORAGE TEMPERATURE (T",) .................................... .
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only
-55 to +125"C
-40 to +85"C
-65 to +150"C
+265"C
+300"C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation Is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA=Full Package Temperature Range)
Vcc :CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage Vin , Vou,
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t,,!,
at 2 V
at 4.5 V
at 6 V
LIMITS
UNITS
MIN,
MAX.
2
4.5
0
6
5.5
Vcc
V
V
V
-40
-55
+85
+125
°C
°C
0
0
0
1000
500
400
ns
ns
ns
·Unless otherwise specified, ali voltages are referenced to Ground.
F/F10NLY
,><>--+---0
:><>--'-+-0
92CS - 402 eo
Fig. 2 - Detail for flip-flops 1, 2, 4, 5, 7, B, 10 & 11.
Fig. 3 - Detail for flip-flops 3, 6,9& 12.
__________________________________________________________________ 489
TechnicaIOala ______________________________
CD54/74HC4040
CD54/74HCT4040
STATIC ELECTRICAL CHARACTERISTICS
CD74HC4040/CD54HC4040
TEST
CONDITIONS
CD74HCT4040/CD54HCT4040
74HC/54HC
TYPES
74HC
TYPES
54HC
TYPES
+25°C
-401
+85"C
-551
+125"C
TEST
CONDITIONS
74HCT/54HCT
TYPES
74HCT
TYPES
54HCT
TYPES
+25°C
-401
+85°C
-551
+l25°C
CHARACTERISTIC
UNITS
V,
V
10
mA
Vee
V
V,
V
Vee
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
V,"
Low-level
Input Voltage
V"
High-Level
V"
Output Voltage
or
Vo"
CMOS Loads
-0.02
V,"
2
1.5
-
-
1.5
-
1.5
-
4.5
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
low-level
Yo,
CMOS Loads
2
1.9
-
-
1.9
-
1.9
-
V"
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
Input Leakage
-
-
3.84
-
3.7
-
or
V,"
-5.2
6
5.48
-
5.34
-
5.2
-
V,"
2
-
0.02
4.5
-
6
-
-
0.1
-
0.1
-
0.1
V"
0.1
-
0.1
0.1
or
0.1
-
0.1
-
0.1
V,"
-
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
--
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
to
V"
4.5
-
-
0.26
-
0.33
-
0.4
or
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
6
-
-
±O.l
-
±1
-
±1
Any
Voltage
Between
Vee
& Gnd
5.5
-
-
:to. 1
-
±1
-
±1
fJA
6
-
-
8
-
80
-
160
Vee
or
Gnd
5.5
-
-
8
-
80
-
160
fJA
-
100 360
-
450
-
490
/lA
or
Quiescent
Vee
Device
or
Icc
2
4
Gnd
Current
-
or
Vee
I,
2
V"
3.98
V"
Current
-
5.5
4.5
V,"
TTL Loads
-
4.5
-
-4
or
2
to
5.5
or
V"
Output Voltage
4.5
-
4.5
V"
TTL Loads
Min Typ Max Min Max Min Max
0
Gnd
Additional
Quiescent
Device Current
per input pin:
Il. Icc'
1 unit load
4.5
Vcc-2.1
to
5.5
"For dual-supply systems theoretical worst case (V,
=2.4 V, Vee =5.5 V) specification is 1.8 mAo
16 Vee
HCT Input Loading Table
Input
MR
tf>
Unit Loads·
0.65
0.5
·Unit Load is Alec limit specified in Static Characteristic Chart,
e.g., 360/lA max.@25"C.
06
15 all
05
14 010
07
13 08
O.
12 09
03
11 MR
02
"4>
GND
9
a,'
TERMINAL ASSIGNMENT
49o _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ ____
--------------------------------------_____________________ TechnicaIData
CD54/74HC4040
CD54/74HCT4040
SWITCHING CHARACTERISTICS (Vee = 5 V, T. = 25°C, Input t" t, = 6 ns)
CHARACTERISTIC
Propagation Delay a, to a"
HC
HCT
Units
15
11
17
ns
15
4
4
ns
t pHL
15
-
14
40
17
Cpo
ns
pF
t plH
Propagation Delay ¢ to a1' Output
Typical
CL
pF
SYMBOL
t pHl
t pHL
1
tpHL
Propagation Delay to MR to a,
Power Dissipation Capacitance-
45
-CPO is used to determine the power consumption, per package.
PO = Cpo Vee 2 fi + I (C L Vcc 2 filM) where:
M =2\ 2 2 , 2 3 , . . 21i
CL = output load capacitance
fi = input frequency
Pre-requisite for Switching Function
CHARACTERISTIC
Maximum Input Pulse
Frequency
Input Pulse Width
(Figure 4)
Reset Removal Time
(Figure 5)
Reset Pulse Width
(Figure 5)
SYMBOL Vce
I MAX
tw
tREM
tw
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
_40° C to +85° C
25°C
-55° C to +125° C
74HC
74HCT
54HC
54HCT
UNITS
HC
HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
4
5
6
MHz
25
25
20
20
16
39
35
29
24
120 80
100 16
25
24
30
ns
20
- 20 14
17
20
75
50
65
10
10
13
13
15
15
ns
11
13
9
120 80
100 16
20
25
24
30
ns
20
14
17
20
~
SWITCHING CHARACTERISTICS (C L =50 pF, Input t"I,=6 ns)
CHARACTERISTIC
Propagation Delay
¢ to a1' Output
(Figure 4)
SYMBOL Vee
tpLH
tPHL
Propagation Delay
a, to an+1
(Figure 4)
tpLH
Propa£,tion Delay
MR to a,
(Figure 5)
Output Transition
Time
(Figure 4)
t pHL
Input Capacitance
tPHL
trLH
trHL
C,
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
_40° C 10 +85° C
-55° C 10 +125° C
25°C
74HCT
54HC
54HCT
UNITS
HCT
74HC
HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
175 140 210 50
60
ns
28
40
42
35
24
36
30
95
75
110 ns
19
22
15
19
22
15
13
19
16
255 215 170 51
34
40
ns
43
60
50
29
43
37
- 110 75
95
-- 22
ns
19
22
15
15
19
16
19
13
-
-
10
-
10
-
10
-
10
.-
10
-
10
pF
___________________________________________________________________ 491
TechnlcaIOala _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4040
CD54/74HCT4040
',--
INPUT LEVEL
-~.
if>
Vs
INPUT LEVEL -.~
t rem
(QI')
INPUT LEVEL
--1,..---.. 1
MR
_Qn_--I/
'THL
INPUT LEVEL
Vs
Vs
Vee
50%
54174HCT
3V
1·3V
92CS-37017
Fig. 4 - Input pulse pre-requisite times, propagation
delays and output transition times.
54174 HC
INPUT LEVEL
Vs
V, C
50%VCC
54174 HC
3V
1·3V
92CS-37018RI
Fig. 5 - Master Reset pre-requisite and propagation delays.
492 ___________________________________________________________________
Technical Data
File Number
CD54/74HC 4046A
CD54/74HCT 4046A
1854
Advance Information/
Preliminary Data
High-Speed CMOS Logic
PC1 OUT
COMP1N
15
0
SIGIN
14
13
PC30UT
PC20UT
PCPOUT
elA
elB
11
"1
"2
VCOIN
VCOOUT
veo
12
10
OEMOUT
INH
92CS-40592
FUNCTIONAL DIAGRAM
Phase-Locked-Loop with VCO
Features:
• Operating frequency range of up to
18 MHz (typ.) at Vee = 5 V
• Choice of three phase comparators:
EXCLUSIVE-OR:
edge-triggered JK flip-flop;
edge-triggered RS flip-flop
• Excel/ent VCO frequency linearity
• VCO-inhibit control for ON/OFF keying
and for low standby power
consumption
• Minimal frequency drift
The RCA CD54/74 HC/HCT4046A are high-speed Si-gate
CMOS devices that are pin compatible with the CD4046B of
the "4000B" series. They are specified in compliance with
JEDEC standard no. 7
The HC/HCT4046A are phase-locked-loop ci rcuits that contain a linear voltage-controlled oscillator (VCO) and three
different phase comparators (PC1, PC2 and PC3). A signal
input and a comparator input are common to each
comparator.
The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to
small voltage signals. A self-bias input circuit keeps small
voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 4046A forms a
second-order loop PLL. The excellent VCO linearity is
achieved by the use of linear op-amp techniques.
The CD54HC4046A and CD54HCT4046A are supplied in
16-lead ceramic dual-in-line packages (F suffix). The
CD74HC4046A and CD74HCT4046A are supplied in 16-lead
plastic dual-in-line packages (E suffix), and in 16-lead surface mount plastic dual-in-line packages (M suffix). The
CD54/74HC/HCT4046A are also supplied in chip form (H
suffix).
• Operating power supply voltage range:
VCO section 3 V to 6 V;
digital section 2 V to 6 V
Applications:
• FM modulation and demodulation
• Frequency synthesis and
multiplication
• Frequency discrimination
• Tone decoding
• Data synchronization and conditioning
• Voltage-to-frequency conversion
• Motor-speed control
Family Features:
• Fanout (Over Temperature Range);
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT/HCU: -40 to +85 0 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to
LSTTL Logic ICs
• Alternate Source is Philips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity: N'L =30%, N'H = 30% of Vee
@ Vee = 5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
' , ::;1 J.1A @ VOL, VOH
16
PCPOUT
15
PC10UT
14
COMPIN
VCOOUT
13
4046A
12
elA
el B
GND
11
10
Vee
PC30UT
SIGIN
PC 2 0UT
R2
"1
DEMOUT
VCO'N
92C5-40591
TERMINAL ASSIGNMENT
______________________________________________________________________ 493
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
CD54/74HC4046A
CD54/74HCT4046A
MAXIMUM RATINGS, Absolute-Maximum Values
DC SUPPLY-VOLTAGE (Vee):
(Voltages referenced to ground) ..................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, I'K (for V, < -0.5 V or V, > Vee + 0.5 V) ........................................ ±20 mA
DC OUTPUT DIODE CURRENT, 10K (for Va < -0.5 V or Va > Vee + 0.5 V) ..................................... ±20 mA
DC DRAIN CURRENT, PEfl OUTPUT (10) (for -0.5 V < Vo < Vee + 0.5 V) .................................... ±25 mA
DC Vee OR GOUND CURRENT (Icc): ..................................................................... ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60°C (PACKAGE TYPE E) .............................................................. 500 mW
For T A = +60 to +85 0 C (PACKAGE TYPE E) ................................. Derate Linearly at 8 mw;a C to 300 mW
For T A = -55 to +100 0 C (PACKAGE TYPE F, H) .......................................................... 500 mW
For TA = +100 to +125°C (pACKAGE TYPE F, H) ............................ Derate Linearly at 8 mW/oC to 300 mW
ForTA = -40 to +70°C (PACKAGE TYPE M) .............................................................. 400 mW
O~~~~~~Nci?Tt~~~~~~~:~~~~~~~~A~:M) ................................ Derate Linearly at 6 mw;ac to 70 mY"
PACKAGE TYPE F, H ............................................................................. -55 to +125 0 C
PACKAGE TYPE E, M ., ............................................................................ -40 to +85"C
STORAGE TEMPERATURE (T,tg) ........ , ........................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0,79 mm) from case for 10 s max. . ..................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ..................................................................... +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always with the
following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (for T A = Full Package-Temperature Range) Vee:'
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage V" Vo
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times, t,. tf
at 2 V
at 4.5 V
at 6 V
UNITS
MIN.
MAX.
2
4.5
6
5.5
V
V
0
Vee
V
-40
-55
+85
+125
°C
°C
0
0
0
1000
500
400
ns
ns
ns
'Unless otherwise specified, all voltages are referenced to Ground.
494 ________________________________________________________________
________________________________________________________________ Technical Data
CD54/74HC4046A
CD54/74HCT4046A
PIN DESCRIPTION
PIN NO.
1
SYMBOL
PCPOUT
NAME AND FUNCTION
phase comparator pulsE: output
2
PC1 0UT
phase comparator 1 output
3
COMP 'N
comparator input
VCO output
4
VCOOUT
5
INH
inhibit input
6
C1 A
capacitor C1 connection A
7
C1s
capacitor C1 connection B
8
GND
ground (0 V)
9
VCO ,N
VCO input
DEMouT
demodulator output
10
11
R,
resistor R1 connection
12
R2
resistor R2 connection
13
PC20UT
phase comparator 2 output
14
SIG 'N
signal input
15
PC30UT
phase comparator 3 o:.Jtput
16
Vee
positive supply voltage
GENERAL DESCRIPTION
Phase Comparators
VCO
The signal input (SIG ,N) can be directly coupled to the selfbiasing amplifier at pin 14, provided that the signal swing is
between the standard HC family input logic levels. Capacitive coupling is required for signals with smaller swings.
The VCO requires one external capacitor C1 (between Ch
and C1s) and one external resistor R1 (between R, and
GND) or two external resistors R1 and R2 (between R, and
GND, and R2 and GND). Resistor R1 and capacitor C1
determine the frequency range of the VCO. Resistor R2
enables the VCO to have a frequency offset if required. See
logic diagram, Fig. 1.
The high input impedance of the VCO simplifies the design
of low-pass filters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is provided at pin 10 (DEMouT). In contrast to conventional techniques where the DEMouT voltage is one threshold voltage
lower than the VCO input voltage, here the DEMouT voltage
equals that of the VCO input. If DEMouT is used, a load resistor (Rs) should be connected from DEMouT to GND; if
unused, DEMouT should be left open. The VCO output
(VCOOUT) can be connected directly to the comparator input
(COMP,N), or connected via a frequency-divider. The VCO
output signal has a guaranteed duty factor of 50%. A LOW
level at the inhibit input (INH) enables the VCO and
demodulator, while a HIGH level turns both off to minimize
standby power consumption.
Phase comparator 1 (PC1)
This is an Exclusive-OR network. The signal and comparator input frequencies (f,) must have a 50% duty factor to
obtain the maximum locking range. The transfer characteristic of PC1, assuming ripple (f, = 2f,) is suppressed, is:
VOEMOUT = (Vee/TT) (_____________p_e3_0_~__~'5 I
I
veo
I I
\ I
11
\ I
R.
R.
Vee
Vee
_ UP
0
ep
\I
\I
II
\I
II.
Q
Ro
Vee
INH
veolN
92CL-40547
Fig, 1 - Logic diagram.
The frequency capture range (2fe) is defined as the frequency
range of .input signals on which the PLL will lock if it was
initiallyout-of-Iock. The frequency lock range (2fL) is defined
as the frequency range of input signals on which the loop will
stay locked if it was initially in lock. The capture range is
smaller or equal to the lock range,
Vee
With PC1, the capture range depends on the low-pass filter
characteristics and can be made as large as the lock range,
This configuration retains lock behavior even with very noisy
input signals. Typical of this type of phase comparator is that
it can lock to input frequencies close to the harmonics of the
VCO center frequency.
--------
COMP 1N
VCO OUT
PC10UT
Fig. 2 - Phase comparator 1: average
output voltage versus input
phase difference:
VOEMOUT = VPC10UT =
(Vee/TT) (
~
600
%
/'
0
I
Z
·500
;;
~ 400
/'
~
0.300
/'
Z
;
200
100
;-biasop,.ratingpOmt
a
v,
SUPPLYVQLTAGE (Vee) - v
Fig. 8 - Typical input resistance
curve at SIG/N• COMP/N'
Fig. 9-HCIHCT4046A RI (min) or R2 (min) vs supply voltage (Vee).
106
107~---+~--~~--+-----~~-T----~
'2468
2488
10
'2488
102
'2468
103
'2468
104
CAPACITANCE (el) -
'2488
105
Fig. IO-HCT4046A typical center frequency vs RI, CI (Vee=4.5 V).
r---
106
107
~
~
>
U
~
105
~
I Vee =
R2
10'
w 103
~
2
U 10
1
i
'2468
102
,
.
, .,
103
,I
,
1.1
104
.
86
105
10 5
1=---/""'---f""'---f""'"
~
~
~
u
466
2468
10
106
'2488
102
'24(1B
103
140
~
R1_1.5M
~~ ...........
80
/
,p':.....
40
102
103
'2488
104
CAPACITANCE (el) -
pF
105
'2488
/:.......
/ / ....
/ ......... .
60
~
'2486
106
r-__~----_r----t_7,·~!~
0
'2468
24(18
105
120r-_C_'_",5_0_P_F__
~
'2468
4(1B
pF
Fig. 13-HCT4046A typical center frequency vs RI, Cl (Vee=4.5 V).
N 100
10~---+----~----+-----~~~----~
2
104
CAPACITANCE (Cl) -
VCOIN=O.5VCC
vee = 5.5 V
10
106
w
Fig. 12-HC4046A typical center frequency vs RI, CI
(Vee=3 V, R2=open).
468
'2468
105
104~---+~~-f~--~~
CAPACITANCE (Cl)- pF
:2
24GB
104
>
:>
~~
10
10
'2466
103
Fig. II-HC4046A typical center frequency vs Rl, CI (Vee=6 V).
~
~~0
~
2468
'2469
102
CAPACITANCE (el) - pF
~ 106~---t~--~~~~__~-----t----~
' ,
~ ~
·s"
" 0"
~
'2468
10
3.0 V
= OPEN
r--....~ ~ ~,,~
"- f'....~
~~
:>
466
! VC01N = 0.5 Vee
~~
106
:2
106
92CS~40S71
pF
-Vce=3V
20 1----lif,""--_r----+-----1
- - - Vee = 4.5 V
"""Vec=6V
I
106
92CS-4057Q
Fig. 14-HCT4046A typical center frequency vs RI, CI
(Vee=5.5 V).
VCOIN (V)
nCS-4C5f.7
Fig. 15-HC4046A typical VCO frequency vs VCO'N
(RI=I.5 MO, Cl=50 pF).
502 ___________________________________________________________________
________________________________________________________________ TechnicaIData
CD54/74HC4046A
CD54/74HCT4046A
90
Rl
Cl
80
800
= 1.5 M
~
30
0
JJF
....•.
-- ··-1... ···..."
60
50
=0.1
700
7Oc--
"~"
Rl-150K
Cl
= O.lIJF
,,'
----- -
40
---~-
'0
-VCC=3V
- V c c - 3V
10
- - - Vee
•••••• Vee
I
=4.5 V
=6 V
100
---Vee= 4.5 v
...... Vee
3
Fig. 16-HC4046A typical VCO frequency vs VCO,N
(Rl=I.5 MO, Cl=O.1 pF).
,B
VCOIN (V)
Fig. 17-HC4046A typical VCO frequency vs VCO,N
(Rl=150 kCl, Cl=O.1 pF).
1400
R1 _ 5.6 K
16~C~I~=-To.~I~"-F~-----r---~+_----~--~
14
. ./. .
~r,'
-
i ::---~~J .?.:> . .
=
50 pF
..
I
...
~
8~---+----~~~~~~----~--~
6
--Z~::.~
,~:. .•,.
Rl=150K
Cl
1200~---,~--_r----+_--~~--_+--~~
1000 f----+----~----+_--~----_+.,.:..--_1
>
8
=6 V
3
92CS-40~62
VCOIN (V)
~ 800f----+----~----+_--~-/~..~..-..·+_--_1
~
/
./~ ...
~ 600f----+----~____,
/~~-,,-j,.""
..."'..'"'-+----+----1
400f----t--__~"'~,""~···-··+_--~-----L----~
,d!f-:: ....
-:;.'
-VCC=3V
---VCC=4.5V
...... vcc = 6 V
'00~-----:lft2"---_r----+_--~
I
-
Vee
---
Vee
=3 v
=4.5 V
...... vCF =6 V
3
92CS-40563
VCOIN(V)
Fig. lB-HC4046A typical VCO frequency vs VCO,N
(Rl=5.6 kO, Cl=O.1 pF).
'4
Al
Cl
Fig. 19-HC4046A typical VCO frequency vs VCO,N
(Rl=150 kCl, Cl=50 pF).
=5.6 K
=
50 pF
,O~---T----_r----t_-~_4----_t~f_4
i:
VCOIN(V)
.... .'
16---
u;
~ 12~---+----_r----+-~'~··q·----_+----4
0
/-;".~~ .•
~
B---_+----~~--+_--~-----+----~
,
l-
'4
'0
16
..::.,
~--~~~-~~-"-·r_--_+----~---vce=3v
f
"z~
~
u
~
~
0
---Vee=4.5V
•••••• Vee = 6 V
=
8
4
r--....
'0
::w
12
."
z
:r
u
>
U
15
"
~
VCOIN = 0.5 VCC
Cl = 50 pF. VCC = 4.5 V
A2 = OPEN
-4
-8
u
> -12
75
V/
VV
1/
50
~
/-"
•,>"
~o
~~
0
r--
-4
0
u -8
>
-12
75
,/
50
V
/'"
V
r--
.. f----
I
~
w
."
15
"
~2:2K
~
0
50
f----
,,~
. 7°i" r--
'5
50
I
100
75
12
125
150
8
75
100
125
:f
4
0
150
AMBIENT TlMPEAATIiRf (TAl -'C 92CS-40579
Fig. 22-HC4046A typical change in VCO frequency vs
ambient temperature as a function of Rl (Vcc=4.5 V).
-;/
-4
-8
- 75
J~
..
q..... 9F-- r -
~
z
:r
u
>
u
u
>
25
~
16 VCOIN = 0.5 VCC
C1 = 50 pF, VCC = 6.0 V
A2 = OPEN
-12
25
'5
I
.........
.4
,'~ f----
Fig. 21-HC4046A typical change in VCO frequency v.
ambient temperature a. a function of Rl (Vcc=3 V).
~
'1-'
4
V
Y
0"
r-
AMBIENTTEMPERATUAE(TA1-"C '92CS-40578
V
ffi::>
0
:il
-4
il:
V-
0
u
-8
>
/
:ii!
=
3 K
-75
Fig. 24-HCT4046A typical change in VCO frequency vs
ambient temperature as a function of Rl.
108
g
t--
106
r-.... ........... I"--.
10 5
g
~
104
il:
~
10 3
10
1
,
2488
........
~
.
~<~
I(
~'"
~:"
108
106
104
tu
~
0
-8
fiB
2
4116
:I:
u
~
<~
«01(
10 2
- 50
1~
10 5
r----"'" r----""'r---- ~<~
~ "'" . . . . N ~«I(
~~
<.<
~~~ "'-
103
V
V
-12
75
~
I~
:::::----..
>
~
-4
,I
1"--. ..........
~
~
~
!
2.2 K
At
V
o
Fig. 26-HC4046A offset frequency vs R2, Cl (Vcc=4.5 V).
107
V
/
-
1;:-
,~
r----~<~
CAPACITANCE (Clj- pF
10 5
~
a
-
-
,~
"'
10 2
10
g
4
-
108
V
~k
10 2
0
o.svcc
= 4.5
Vee
1'---"'" r---- . . . . "'"
>
~
I VCOIN
107
...
",,,,0_
~
~
25
50
75
100 125 150
AMBIENT TEMPERATURE (TA)-'C
92CS-40590
II
~
0
~
- 50 - 25
-12
~
Ai
'"
",'
= OPEN
8
u
At
R2
"
w
/' ..
~
U
,.
..,
~...
'
w
u
~~~I~O-p~·.SV:~C= 4.5 v
20
g
I
...~w
"'-
~
o
~
10
1
2
<188
2
<168
:I:
VCOIN
= 2.25 V
2
>-
"'z~ -,
0
:::;
-.
-.
-8
, K
--/
,
C1 = 50 pF
c/"
=
=
±1Y
~
/
t--VCOIN
'/
6_ VCC=3V
R2
'OK
--------+-------~------~
= 2.25 V±O.4S v
I
L
."
= OPEN
-4~------~------~--------+_------~
-6~------~------~--------+_-------
"lOOK
,
-8
"'OM
R1 (OHMS)
I K
"'0 K
."
100 K
R1
" 1M
."
10M
iOI-!MS~
92CS-40561
Fig. 35-HC4046A VCO linearity vs Rl (Vcc=4.5 V).
Fig. 36-HC4046A VCO linearity vs Rl (Vee=3 V).
505
Technical Data
.CD54/74HC4046A
CD54/74HCT4046A
8
8
C1 =50pF
R2
= OPEN
4
l
~
VCOIN
=3 V±1.S
2
~
0
~
-2
Cl=50pF
R2
OPEN
=
Vee= 6 v
8
y
/
~
/.-- r------.,.
;.l
/'
-4
/f
/
-B
-8
1 K
"-
"-
l
2
~
~
o~------i-~~~~'
t-----.-i--o
~ -2~--~~~------+_------+_------,
VCOIN=3V±O.6~
-4~--~~+-------+_------J-------,
, ~, "
, ,
10 K
..
100 K
, , "
, , "
10M
1 M
-8
"68
1 K
"68
10 K
Fig. 37-HC4046A VCO linearity vs Rl (Vcc=6 V).
2
"68
100 K
R1 (OHMS)
R1(OHM5)
~
- - - VCC=5.5V
VCC=4.5V
-.t-~~--+-------4
"8B
1 M
10 M
92CS-40580
Fig. 38-HCT4046A VCO Iinearity.VB Rl (Vcc=4.5 V. Vcc=5.5 V).
6 VCOIN - 0.5 Vee
~
I
C
;
6 VCOIN - 0.5 Vee
R1 = R2 = OPEN
•••••
10~~---------k~~----~~--------~
~<:. . . ....
i'
~ 10:~--------~----~'~~~,~.~-.-----1
~
~
~ 10"r---------~--------~~--------~
-VCC=3V
- - - VCC=4.5V
...... Vee
6 V
=
1K
, " 10K
, " 100 K
~Q
o
~
"
,
, " 1M
1 K
-VCC=3V
---VCC=4.5V
..
,
10 K
Fig. 39-HC4046A demodulator power dissipation vs RS (typ.)
(Vcc=3 V; 4.5 V; 6 V).
•••• .. VCC=6V
, "
100 K
RS (OHMS)
92CS-40589
RS (OHMS)
..
1M
92CS-40584
Fig. 40-HCT4046A demodulator power dissipation vs RS (typ.)
(Vcc=3 V; 4.5 V; 6 V).
;;:
0.
VCOIN =OV{ATFMIN)
CL =lt50pF
R1 = RS= OPEN
,
~ 10:1:-----;-''''-<::-1:
!':.
z
o
;::
'
,
~ 10~~--------~~~,~-,~,~d----------4
C1 =1 ~F
/
C1 = 1 ~F
(/j
~
w
:z
o
'
.............. ...
............ ...
.......... ...
~ 10!r---------~--------_1----------~
~
,
1 K
,.
Fig. 41-HC4046A VCO power dissipation vs Rl (Cl=50pF; 1 fJF).
VCOIN = o.s Vee
R2=RS=OPEN
~
I 10S~---------h~~~----~--------~
g :
z
o
;::
~ 10!~----~~~~~~----~--------4
::lQ
'
'"w
.
~ 10!r----------r----------~--~----~
~
o
- V e e = 5.5 V
~
,
102
1 K
,
1M
---VCC=4.5V
, " 100 K
Rt (OHMS}
1K
92CS-40565
R1 (OHMS)
,.
10K
=
- - - Vec
4.5 V
-VCC=6V
, ,.
,
lOOK
R2 (OHMS)
92CS-40~87
Fig. 42-HCT4046A VCO power dissipation vs R2 (Cl =50 pF; 1 JJF).
~
~10~~---.~~~---------4----------,
!':.
z
~
'
:z
~10~r-----~~~~~~~~~~~----~
::lQ
ffi
''
o
'
~ 10~r----------r------~~~"~----4
~
,
1 M
92CS-40566
Fig. 43-HCT4046A VCO power dissipation vs Rl (Cl=50 pF; 1 fJF).
,.
1M
,
1K
R2{OHMS)
..
1M
; 92CS-40586
Fig. 44-HC4046A VCO power dissipation vs R2 (Cl=50 pF. 1 fJF).
506 _________________________________________________________________
--------------------------------------__________________________ TechnicaIData
CD54/74HC4046A
CD54/74HCT4046A
HC/HCT 4046A
HC
HCT
COMPARATOR 1
48
50
COMPARATORS 2 & 3
39
48
VCO
61
53
CHIP SECTION
APPLICATION INFORMATION
This information is a guide for the approximation of values
of external components to be used with the 74HCI
HCT4046A in a phase-lock-loop system.
References should be made to Figs.10 through 14 as indicated in the table.
SUBJECT
CpD
PHASE
COMPARATOR
UNIT
pF
Values of the selected components should be within the following ranges.
R1
R2
R1
C1
between 3 kG and 300 kG;
between 3 kG and 300 kG;
parallel value> 2.7 kG;
greater than 40 pF.
+ R2
DESIGN CONSIDERATIONS
VCO Frequency characteristic
VCO frequency
without extra
offset
PC1, PC2 or PC3
With R2 = 00 'and R1 within the range 3 kG < R1 < 300 kG, the
characteristics of the VCO operation will be as shown in Figs. 10-14.
(Due to R1, C1 time constant a small offset remains when R2 = 00.)
il
fyeo
I
2f L
:I
-1-_ _ _ _--1---'-
fmm "'--_ _ _ _
1/2 Vee
VVCOIN
max.
Fig. 45- Frequency characteristic of VCO
operating without offset: 10 ~ center
frequency: 21L ~ frequency lock range.
Selection of R1 and C1
PC1
Given fa, determine the values of R1 and C1 using Figs. 10-14.
PC2 or PC3
Given f m . , and fa, determine the values of R1 and C1 using Fig. 30.
Use Fig. 31 to obtain 2fL and then use this to calculate f m ,".
VCO frequency characteristic
VCO frequency
with extra
offset
PC1, PC2 or PC3
With R1 and R2 within the ranges 3 kG < R1 < 300 kG, 3 kG, < R2 <
300 kG, the characteristics of the VCO operation will be as shown in
Figs. 26-29.
'm"ZL--------lt
I I
+--'
I
'vco
to
'm,"
----
-
-
-
-
12fL
I
---t - - - - I
I
I
I
I
I
1/2 Vee
<=ig. 46 -
V V C01N
max.
Frequency characteristic of VCO
operating with offset: fa ~ center
frequency; 2fL ~ frequency lock range.
----------------------------------_________________________________ 507
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4046A
CD54/74HCT4046A
APPLICATION INFORMATION (Cont'd.)
SUBJECT
PHASE
COMPARATOR
DESIGN CONSIDERATIONS
Selection of Rl, R2 and Cl
VCO frequency
with offset
(continued)
PLL conditions with
no signal at the
SIG 'N input
PLL Frequency
capture range
PC1, PC2 or PC3
Given fo and fl, determine the value of product RICl by using Figs.26-29.
Calculate foil from equation fall = fco = fl.
Obtain the values of Cl and R2 by using Figs. 26-29.
Calculate the value of Rl from the value of Cl and the product R1Cl.
PCl
VCO adjusts to fa with 2f~ = lhT (27rl LIr.)'/2
Fig. 47 - Simple loop filter for PLL without offset.
I~
-" = ::£1 '"'""' I' '~ __ R3
-
---"'- ---:;;;;-:;)
_
m
1/r 3
(a)
T,
T2
T3
1'T2
= R3 x C2;
(b) amplitude characteristic
= R4 x C2;
=. (R3 + R4) x C2
R3+R4
~
w
(e) pole-zero diagram
Fig. 48 - Simple loop filter for PLL with offset.
508 __________________________________________________________________
Technical Data
CD54/74HC4046A
CD54/74HCT4046A
SUBJECT
PLL locks on harmonics
at center frequency
noise rejection at
signal input
AC ripple content
when PLL is locked
PHASE
COMPARATOR
DESIGN CONSIDERATIONS
PC1 or PC3
yes
PC2
no
PC1
high
PC2 or PC3
low
PC1
f,
= 2fi, large ripple content at ---- Y
. 3
2y
HC4049
4
13
12
2A
3y
A
14
IA
o-----!)o--V---
oj
92CS-37797
LOGIC DIAGRAMS
10
3A
GND
HC4050
II
6
8
9
NC
6y
6A
NC
5y
5A
4y
4A
92CS-37798
CD54/74HC4050
510 ___________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4049
CD54/74HC4050'
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee) , ......................................................................................... -0.5 to +7 V
DC INPUT VOLTAGE, (V,)
(Voltages referenced to ground) .....................................................................................-0.5 to +16 V
DC INPUT DIODE CURRENT, I,K (FOR V, < -0.5 V) .......................................................................... -20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) .................................................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) .................................................... ±25 mA
DC Vee OR GROUND CURRENT (Icc) ...................................................................................... ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60°C (PACKAGE TYPE E)
......................................................................... 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E)
............................. Derate Linearly at 8 mW/o C to 300 mW
For TA = -55 to +100°C (PACKAGE TYPE F, H)
............................................................ 500 mW
............................... Derate Linearly at 8 mW/oC to 300 mW
For TA = +100 to +125°C (PACKAGE TYPE F, H)
................................................................. 400 mW
For TA = -40 to +70° C (PACKAGE TYPE M) .... .
ForTA = +70 to +125°C (PACKAGE TYPE M) .... .
Derate Linearly at 6 mW/o C to 70 mW
OPERATING-TEMPERATURE RANGE (TA)
PACKAGE TYPE F, H ............................................................................................ -55 to +125°C
PACKAGE TYPE E, M ............................................................................................. -40 to +85°C
STORAGE TEMPERATURE (T",) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING) :
At distance 1116 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
. .................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ...... '" ............................................................................ +300° C
Vee
~
Voltage Relationships:
(Maximum Positive Limits)
7V
92CS-37799RI
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA-Full Package Temperature Range)
Vee:*
CD54/74HC Types
DC Output Voltage, Vo
DC Inpul Vollage (V,)
Operaling Temperalure, TA:
CD74 Types
CD54 Types
Inpul Rise and Fall Times, 1,,1,:
al2 V
al 4.5 V
al6 V
LIMITS
MIN,
MAX,
UNITS
a
a
6
Vee
15
V
V
V
-40
-55
+85
+125
°C
a
a
a
1000
500
400
ns
2
'Unless otherwise specified, all voltages are referenced to Ground.
___________________________________________________________________ 511
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4049
CD54/74HC4050
STATIC ELECTRICAL CHARACTERISTICS
'CD54174HC4049, CD54174HC4050
74HC/54HC
74HC
TEST
SERIES
SERIES
CONDITIONS
CHARACTERISTIC
10
mA
VI
V
VCC
V
2
High-Level Input Voltage
V,H
Low-Level Input Voltage
V,L
High-Level Output Voltage
CMOS Loads
TTL Loads
(Standard Output)
V,L
or
V,H
V,L or
V,H
V,L
or
V,H
V,L or
V,H
Vee or
Gnd
15
15 or
Gnd
VOH
Low-Level Output Voltage
CMOS Loads
TTL Loads
(Standard Output)
VOL
I nput Leakage Current
I,
Quiescent Device Current
Icc
4.5
6
2
4.5
6
2
4.5
6
4.5
6
2
4.5
6
4.5
6
-0.02
-4
-5.2
0.02
4
5.2
+85°C
Min. Typ. Max. Min. Max.
1.5
1.5
3.15
3.15 4.2
4.2 0.5
0.5 - 1.35
1.35
1.8 1.8
1.9
1.9
4.4
4.4
5.9
5.9
3.98 3.84
- 5.34
5.48
0.1
0.1
0.1
0.1
0.1
0.1
0.26
0.33
0.26
0.33
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±0.1 -
±1
6
-
-
±0.5
6
-
-
2
-
~
UNITS
-551
-
6
0
-401
+25°C
-
54HC
SERIES
+125°C
Min. Max.
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4" 5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
-
-
V
V
V
-
V
-
±5
-
±5
20
-
,40
±1
V
V
IIA
IIA
SWITCHING CHARACTERISTICS (VCC=5 V, TA=25° C, Input tr,tl=6 nB)
CHARACTERISTIC
SYMBOL
Propagation Delay, Data Input to Output
(CL = 15 pF)
Power Dissipation Capacitance'
HC4049
HC4050
tPLH. tPHL
Cpo
54HC AND 74HC
UNITS
TYPICAL
6
ns
35
pF
'Cpo is used to determine the dynamic power consumption, per inverter
Po = Vee' f,(Cpo +Cd where: f, = input frequency
CL = output load capacitance
Vee = supply voltage
SWITCHING CHARACTERISTICS (CL = 50 pF, Input tr,t, = 6 ns)
CHARACTERISTIC
SYMBOL
Propagation Delay
nA to nY HC4049
nA to nY HC4050
Transition Time
tPLH, tpHL
tTLH, trHl
Input Capacitance
512 _____________
C,
~
VCC
2
4.5
6
2
4.5
6
-
25°C
HC
Max.
Min.
85
17
14
75
15
13
10
-
-40° C to +85° C 55°Cto+125°C
.UNITS
74HC
54HC
Max.
Min.
Min.
Max.
130
105
26
21
ns
18
22
95
110
19
22
ns
16
19
10
10
'pF
-
-
-
-
-
____________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54J74HC4049
CD54/74HC4050·
Vee
VI
OV
V OH
VA
HC4049
OV
tTHL
VOH
va
HC4050
ov
92CS-35124R2
Fig. 1 - Transition times and propagation delay
times, combination logic.
____________________________________________________ 513
Technical Data
CD54/74HC4051, CD54/74HCT4051
CD54/74HC4052, CD54n4HCT4052
CD54/74HC4053, CD54/74HCT4053
File Number
1676
High-Speed CMOS Logic
16 Vee
CHANNEL
IN/OUT
: AS 2
1'"
COM OUTIIN A
3
t'
CHANNEL
IN/OUT
AS
E
·"j
14
1\1
13 AO
5
12 A3
6
so
VEE
10 61
OND
52
CHANNEL
liN/OUT
Analog Multiplexers/
Demultiplexers
Type Features:
CD54n4HC/HCT4051
TERMINAL ASSIGNMENT
• Wide analog input voltage range: ± 5 V max.
• Low "on" resistance:
70 n typ (Vee-VEE = 4.5 V)
40 n typ (Vee-VEE = 9 V)
• Low crosstalk between switches
• Fast switching and propagation speeds
• "Break-before-make" switching
The RCA CD54/74HC/HCT4051, 4052, and 4053 are digitally controlled analog switches which utilize Silicon-gate
CMOS technology to achieve operating speeds similar to
LSTTL with the low power consumption of standard CMOS
integrated circuits.
These analog multiplexers/demultiplexers control analog
voltages that may vary across the voltage supply range (i.e.
Vee to VEE). They' are bidirectional switches thus allowing
any analog input to be used as an output and visa-versa.
The switches have low "on" resistance and low "off"
leakages. I n addition, all three devices have an enable
control which when, high, disables all switches to their
"off" state.
Family Features:
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +B5°C
• Alternate Source is PhilipslSignetics
• CD54HCICD74HC Types:
2 to 6 V Operation, control; 0 to 10 V, switch
High Noise Immunity:
N'L = 30%, N'H = 30% of Vee; @ Vee = 5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation, control; 0 to 10 V, switch
Direct LSTTL Input Logic Compatibility
V'L = O.B V Max., V'H = 2 V Min.
CMOS Input Compatibility
I, S 1 /JA @ VOL, VOH
The CD54HC/HCT4051, 4052, and 4053 are supplied in
16-lead hermetic dual-in-line ceramic packages (F suffix).
The CD74HC/HCT 4051, 4052, and 4053 are supplied in
16-lead plastic packages (E suffix) and in 16-lead surface
mount plastic packages (M suffix). All devices are also
available in chip form (H suffix).
,6
TRUTH TABLE
CD54/74HC/HCT4051
INPUT STATES
ENABLE 52
5,
L
L
L
'0
BINARY
lOGIC
LEVEL
CONvERSION
A
COMMON
TO
I OF 8
DECODER
WITH
ENABLE
OUTIIN
92CS-200B5R3
OND
Fig. 1 - Functional diagram of HCIHCT4051.
x
L
L
L
L
H
H
H
H
"ON"
51
SO
CHANNELS
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
AD
A1
A2
A3
A4
A5
A6
A7
X
NONE
L
L
L
L
L
X
H
X
= Don't Care
514 _________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4051, CD54/74HCT4051
CD54/74HC4052, CD54/74HCT4052
CD54/74HC4053, CD54/74HCT4053
A CHANNELS IN lOUT
Vee
'6
16 Vee
CHANNEL{BO
IN/OUT
13 COMMON A
'0
BINARY
TO
LOGIC
LEVEL
15 A2} CHANNEL
'4 Al IN/OUT
OUTIIN
COM QUTflN Bn
COMMON B
OUTIIN
I OF 4
DECODER
CONVERSION
"
B2
13 An COM DUTtlN
CHANNEL{Bl
WITH
INICUT
ENABLE
12 AO} CHANNEL.
BI
E
11
6
INIOUT
A3
10
GNO
SO
• 51
92CS-200B6R3
7
GNO
B CHANNELS IN/OUT
VEE
CD54n4HC/HCT4052
TERMINAL ASSIGNMENT
Fig. 2 - Functional diagram of HCIHCT4052.
Vee
A COMMON
OUTIIN
BI 1
16 Vee
CHANNEL. {
INlOur
so
2
15 Bn COM OUTIIN
el
3
COM QUTflN
en
B COMMON
5,
OUTIIN
52
C COMMON
curliN
14 An COM OUT/IN
13
AI} CHANNEL
12 AO
INIOUT CO
tNIOUT
so
to
VEE
uNO
92CS-38412RI
GND
51
52
VEE
CD54n4HC/HCT4053
TERMINAL ASSIGNMENT
Fig. 3 - Functional diagram of HCIHCT4053.
TRUTH TABLES (Continued)
CD54174HC/HCT4052
INPUT STATES
CD54174HC/HCT4053
INPUT STATES
"ON" CHANNELS
ENABLE
Sl
SO
"ON" CHANNELS
ENABLE
S2
Sl
SO
L
L
L
L
L
H
H
L
H
L
H
AO,BO
L
L
L
L
AD
BO
CO
A1, B1
L
L
L
H
AD
BO
C1
A2,B2
L
L
H
L
AD
B1
CO
A3.B3
L
L
H
H
AD
B1
C1
H
X
X = Don: Care
X
NONE
L
H
L
:..
A1
BO
CO
L
L
H
L
H
A1
BO
C1
H
H
L
A1
B1
CO
L
H
H
H
A1
B1
C1
H
X
X
X
,
I---'-
NONE
x = Don't Care
________________________________________________________ 515
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4051, CD54/74HCT4051
CD54/74HC4052, CD54/74HCT4052
CD54/74HC4053, CD54/74HCT4053
MAXIMUM RATINGS, Absolute-Maximum Values: (All voltages referenced to Gnd unless otherwise shown)
DC SUPPLY-VOLTAGE (Vee-VEE) .......••...••........•....••..•.......................••........•........••....•....• -0.5 to 11 V
DC SUPPLY-VOLTAGE (Vee) ..............................•...•....•....•....•..............•........•.•..•...........• -0.5 to +7 V
DC SUPPLY-VOLTAGE (VEE) ....••.........•............•....•.............•..•.•...•••.....•..•...................•..• +0.5 to -7 V
DC INPUT DIODE CURRENT, 1,K (FOR V, < -0.5 V OR V, > Vee + 0.5 V) ....................................................... ±20 mA
DC SWITCH DIODE CURRENT, 10K (FOR V, < VEE -0.5 V OR V, > Vee + 0.5 V) ................................................ ±20 mA
• DC SWITCH CURRENT (FOR V, > VEE -0.5 V OR V, < Vee + 0.5 V) ...........................•....•....•......•.......••.•... +25 mA
DC Vee OR GROUND CURRENT (lee) ...................................................................................... ±50 mA
DC VEE CURRENT (lEE) ....................................................................................................-20 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60° C (PACKAGE TYPE E) .............•............••.•......•..•.......•............................•.. 500 mW
ForT. = +60 to +85°C (PACKAGE TYPE E) .................................................. Derate Linearly at B mW/oC to 300 mW
For T. = -55 to +100° C (PACKAGE TYPE F, H) ........................................................................... 500 mW
ForT. = +100 to +125°C (PACKAGE TYPE F, H) ............................................. Derate Linearly at 8 mW/oC to 300 mW
For T. = -40 to +70° C (PACKAGE TYPE M) •........•.......•............................••...........•.................. 400 mW
For T. = +70 to +125°C (PACKAGE TYPE M) ............................................... Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H ............................................................................................. -55 to +125°C
PACKAGE TYPE E, M .............................................................................................. -40 to +85° C
STORAGE TEMPERATURE (T ...) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case forl0 s max.
+265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ..................................................................................... +300° C
• In certain applications, the external load-resistor current may include both Vee and signal-line components. To
avoid drawing Vee current when switch current flows into the transmission gate inputs, the voltage drop across the
bidirectional switch must not exceed 0.6 volt (calculated from RON values shown in Electrical Characteristics chart).
No Vee current will flow through RL if the switch current flows into terminal 3 on the HC/HCT4051; terminals.3 and
13 on the HC/HCT4052; terminals 4,14 and 15 on the HC/HCT4053.
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For T. = Full Package-Temperature Range) Vee:'
CD54/74HC Types
CD54/74HCT Types
Supply-Voltage Range (For T. = Full Package-Temperature Range) Vee-VEE
See Fig. 4
CD54/74HC Types
CD54/74HCT Types
Supply-Voltage Range (ForT. = Full Package-Temperature Range) VEE:'
See Fig. 5
CD54/74HC Types
CD54174HCT Types
DC Input Contrpl Voltage, V,
Analog Switch 1/0 Voltage, V's
CD74 Types
Operating Temperature T.:
CD54 Types
Input Rise and Fall Times t" t, at2V
at4.5V
at6V
UNITS
MIN.
MAX.
2
4.5
6
5.5
V
V
2
10
V
0
-6
V
Gnd
VEE
-40
-55
Vee
Vee
+85
+125
V
V
0
0
0
1000
°C
°C
ns
ns
500
400
ns
'Unless otherwise specified, all voltages are referenced to Ground.
Recommended Operating Area as a Function of Supply Voltages.
8
61-T-r-77':
vee GND 4 ~~>4''''''''~
(V)
°O~~~~4~-'6-L~8-L~IO~~12
Vce - VEE (V)
92CS-393!57
Fig. 4
o'~~~~--~----
o
-2 -4
-6
V'EE-GND (V)
Fig. 5
-8
92e$-3935.
516 _________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4051, CD54/74HCT4051
CD54/74HC4052, CD54/74HCT4052
CD54/74HC4053, CD54/74HCT4053
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT/CD54HCT4051.4052.4053
CD74HC/C054HC4D51,4052,4053
TEST
74HC/54HC
ACTERISTIC
-40/
v"
VI
VEE
v
v
v
Input
4.5
Input
+125°C
Min
VIH
Typ
"On"
V"
or
-4.5
Vee
-4.5
V"
Maximum "On"
Resistance
-4.5
54HCT
OFF:
Current
(~
4 Channels
Vos = Vee
For Switch
(4051)
or
-5
V,"
-5
of VIS & Vas
Voltage Levels
V
to
4.2
5.5
0.5
0.5
0.5
1.35
1.35
1.35
to
1.8
1.8
1.8
5.5
70
160
200
240
4.5
60
140
175
210
4.5
40
120
150
180
4.5
4.5
90
180
225
270
4.5
45
130
162
Min
Typ
Max
-55/
+125°C
Min
Ma.
Min
Mil.
4.5
3.15
195
10
v
4.5
0.8
0.8
0.8
70
160
200
240
40
120
150
180
90
180
225
270
V
Cl
-4.5
4.5
Same
as
as
He
HC
-+__~__~__+-__~~~~
~~~-+__
-4.5
4.5
45
4.5
10
130
162
Cl
195
Cl
-4.5
4.5
-5
Control Input
4.5
±0.1
±1
±1
±O.l
±1
±1
±0.1
±1
±1
±0.2
±2
±2
±0.2
±2
±2
±0.4
±4
±4
±0.1
±1
±1
80
160
-5
-5
-5
±O.1
±1
±1
±0.1
±1
±1
±O.l
±1
±1
±0.2
±2
±2
±0.2
±2
±2
±0.4
±4
±4
±0.1
±1
±1
80
160
pA
Vee
Leakage
-
ilL
Quiescent
v
4.2
ON:
All Applicable
(~ Combinations
8 Channels
v
-401
+85°C
For Switch
When VIS=VCC
Vos = VEE;
When VIS=V EE,
5.5
-
pA
Gnd
When
Device
V",
Current
74HCT
8.5
leakage
1&2 Channels
v
3.15
4.5
ARon
I.z
Ma.
+2S200
-2.25
2.25
-4.5
4.5
-2.25
2.25
(TBE)
(TBE)
-4.5
4.5
(TBE)
(TBE)
-2.25
-4.5
2.25
4.5
0.035
0.018
-2.25
2.25
(TBE)
-4.5
4.5
(TBE)
-2.25
2.25
UNITS
pF
MHz
N/A
N/A
dB
%
mV
-4.5
4.5
-73
-65
-64
-75
-67
-66
dB
Notes:
1. Adjust input voltage to obtain OdBm @ Vos for fin = 1 MHz.
2. V's is centered at (Vee - VEE)/2.
3. Adjust input for OdBm.
4. Not applicable for HC/HCT4051.
___________________________________________________________________ 519
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4051, CD54/74HCT4051
CD54/74HC4052, CD54/74HCT4052
CD54/74HC4053, CD54/74HCT4053
Vee
O.1I1 F
vos~
VCC/ 2
R
-----l1f---'VVV--'1
10pF
INPUT
I "~~
Vcc/2
',S=1 MHzSINEWAVE
R=50n
c = 10 pF
Vee
92CS-39354
Fig. 6 - Frequency response test circuit.
92CS-39355
Fig. 7 - Crosstalk between two switches test circuit.
Vee
Vce
SINE
WAVE
v,s---l
SWITCH
ALTERNATING
. ONANDOFF
10..-F
VCC/2
Il-_~"""_~;::::;':;;::::::;I-+-'
t r • tf,:Sa ns
'CONT=1 MHz
50 % DUTY
CYCLE
f1S=1 kHzT010kHz
92CS - 393 56RI
~2CS-
39352
Fig. 9 - Contro/-to-switch feedthrough noise test circuit.
Fig. 8 - Sine wave distortion test circuit.
Vee
tIS ~ 1 MHz SINE WAVE
e
T
Vcc/2
Vcc/2
-:::::='"
VO$SR~~~~F
dB
METER
92CS-39353
Fig. 10 - Switch off signal feedthrough.
520 _____________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4051, CD54/74HCT4051
CD54/74HC4052, CD54/74HCT4052
CD54/74HC4053, CD54/74HCT4053
OdS
OdB
-I
V
Vee::: 4.~V
-ZdS
GNO·-4.5V
VEE ·-4.5V
~
\'
/
RL' 50n
PINI2T03
V
-4dS
-20dB
!
-
-40dS
-
RL' 50n
PIN IZ TO 3
-aOdB
1M
FREQUENCY (I)-Hz
10M
100M
92CS-39349
-2dS
~~
-IOOdB
10K
~
\
I
-4dS
lOOK
-
-BdS
I I II
1M
FREQUENCY (I) -Hz
1M
. FREQUENCY(! I-Hz
10M
100M
92CS- 393~O
II
VCc" 2.Z5V
GNO·-Z.Z5V
VEE·-Z.Z5V
RL·.50n
PIN 4 T03
-ZOdB
\
~?
-GOdB
~
100M
10M
-IOOdS
10K
P
k:;:::::=
ff'
\
Vcc·4.5V
GNO ·-4.5V
VEE ·-4.5V
RL'50n
PIN 4T03
#~
-BOdB
lOOK
-
PIN 12 T03
-40dB
RL' son
PIN 4 TO 3
-IOdS
10K
-
RL,50n
VCC ·Z.Z5V
GNO·-2.2SV VEE·- Z. 2SV
-6dS
-
Fig. 12 - Channel off feedthrough (HCIHCT4051).
/
RV 50n
PIN 4T03
VCc' 4.5V
GND= -4.5V
VEE ·-4.5V
OdB
,/P"
I
VCC·4.SV
GNO·-4.SV
VEE ·-4.5V
~
~~
Fig. 11 - Channel on bandwidth (HCIHCT4051).
OdS
~F
~
-60dB
-adS
lOOK
./
rfV
RL ' 50n
PINI2T03
-
VEC-Z.Z~V
-IOdS
10K
II
VCC '2.25V
GNO'-2.25 V
VEE '-2.25 V
VCc· Z •Z5V
GNO·-Z·Z5V
-6dS
II
~
j-
I
1
~
rr-
loIJ
lOOK
92CS-39351
1M
FREQUENCY (I)-Hz
100M
10M
92CS-39348
Fig. 14 - Channel off feedthrough (HCIHCT4052).
Fig. 13 - Channel on bandwidth (HCIHCT4052).
II
OdS
r--
vCc' Z.Z5V
(--
Vcc ·4.SV
-ldB
GNO'-4 SV
VEC-4.5V
RL-
son
PIN 5T04
-2dS
1 I),
VCc' 2.25V
-3dB
r--
RL' 50n
PINST04
r--
I
10 K
I
1M.
FREQUENCY (!I- Hz
r--
GNO·-2.25 V
VE E ·-2.25 v
-4dB
OK
~
-ZOd B
GNO·-Z.2SV
vEE·-Z.Z5 V
-40dB
\
~
-GOdS
'?"
-BOdB
I I I
I
M
100M
92CS- 39429
Fig. 15 - Channel on bandwidth (HCIHCT4053).
-IOOdS
10K
~v
1:7:::::
RL '50n
PIN5T04
Iu.
-r
lOOK
1-t1V"
F(
\
VCC ·4.5 V
GNO·-4.5 V
VEE"- 4.5 V
RL' 50n
PIN5T04
rr-
1M
10M
100M
FREQUENCY (1)- Hz
92CS-39430
Fig. 16 - Channel off feedthrough (HCIHCT4053).
521
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4051, CD54/74HCT4051
CD54/74HC4052, CD54/74HCT4052
CD54/74HC4053, CD54/74HCT4053
130
~
120
5I 110
100
Z
~
90
w
o
z
Vee -VEE
~
=4.5 V
Vee -VEE
iii
:!i
30
Z
20
?
10
=6V
----------______------VCC- VEE=9V
INPUT SIGNAL VOLTAGE (VIS) -
v
92CS-39563
Fig. 17 - Typical ON resistance vs. input signal voltage.
605
}----~~L_+-------VCC
rVcc
/1<-'''-'''--_ _ _ _ _ GND
90%
SWITCH INPUT
50%
10%
PLH
~
LVEE
tpHL
SWITCH OUTPUT
I
-
---- --
-- -
----
--
90%
50%
10%
92CS-36972R4
92C5-39359
HC4051, 4052, 4053
6ns
~~~-----------GND
92CS-39360
HCT4051, 4052, 4053
Fig. 18 - Switch propagation delay, turn-on, turn-off times.
IN~OUT
VEE for tpLZ and tpZl
1
Vee for 'PHZ and tpZH
J
IN
~RL:'kn
TG
OUT
I-=-
) Vee for tpLZ and tpZL
VEE for tpHZ and 'PZH
l
50PF
92C5-3B635
CL
SOPF
92C5-38836
Fig. 19 - Switch on/off propagation delay test circuit.
522~
.I
Fig. 20 - Switch In to Switch Out
Propagation delay test circuit.
_____________________________________________________________
_____________________________________________________________ TechnicaIOata
File Number
CD54/74HC4059
CD54/74HCT4059
1853
High-Speed CMOS Logic
CMOS Programmable
Divide-by-"N" Counter
CP
Kc
'IN
Q~(-J
N
LE
92C5-40495
FUNCTIONAL DIAGRAM
Type Features:
• Synchronous programmable + N counter:
N = 3 to 9999 or 15999
• Presettable down-counter
• Fully static operation
• Mode-select control of initial decade
counting function (+ 10, 8, 5, 4, 2)
• Master preset initialization
• Latchable + N output
The RCA-CD54174HC4059 and the CD54/74HCT4059 are
high-speed silicon-gate devices that are pin-compatible
with the CD4059B devices of the CD4000B series. These
devices are divide-by-N down-counters that can be programmed to divide an input frequency by any number "N"
from 3 to 15,999. The output"signal is a pulse one clock
cycle wide occurring at a rate equal to the input frequency
divided by N. The down-counter is preset by means of 16
jam inputs.
The three Mode-Select Inputs Ka, Kb, and Kc determine the
modulus ("divide-by" number) of the first and last counting
sections in accordance with the truth table shown in Table I.
Every time the first (fastest) counting section goes through
one cycle, it reduces by 1 the number that has been preset
(jammed) into the three decades of the intermediate
counting section and into the last counting section, which
consists of flip-flops that are not needed for operating the
first counting section. For example, in the + 2 mode, only
one flip-flop is needed in the first counting section.
Therefore the last counting section has three flip-flops that
can be preset to a maximum count of seven with a place
value of thousands. If + 10 is desired for the first section, Ka
is set "high", Kb "high" and Kc "low". Jam inputs J1, J2, J3,
and J4 are used to preset the first counting section and
there is no last counting section. The intermediate counting
section consists of three cascaded BCD decade (+ 10)
counters presettable by means of Jam Inputs J5 through
J16.
The Mode-Select Inputs permit frequency-synthesizer
channel separations of 10,12.5,20,25, or 50 parts. These
inputs set the maximum value of N at 9999 (when the first
counting section divides by 5 or 10) or 15,999 (when the first
counting section divides by B, 4, or 2).
Family Features:
• Fanout (over temperature range):
Standard outputs - 10 LS TTL loads
Bus driver outputs - 15 LS TTL loads
• Wide operating temperature range:
CD74HC/HCT: -40 to +85 c C
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL
logic ICs
• Alternate source is Philips/Signetics
• CD54HC/CD74HC types:
2 to 6 V operation
High noise immunity:
N'L = 30%, N'H = 30% of Vee: @ Vee = 5 V
• CD54HCT/CD74HCT types:
4.5 to 5.5 V operation
Direct LSTTL input logic compatibility
V'L = 0.8 V max., V'H = 2 V min.
CMOS input compatibility
I, :S 1 JiA @ VOL, VOH
Applications:
• Communications digital frequency
synthesizers: VHF, UHF, FM, AM, etc.
• Fixed or programmable frequency division
• "Time out" timer for consumer-application
industrial controls
• Companion Application Note, ICAN-6374, "Application
of the CMOS CD4059A Programmable Divide-by-N
Counter in FM and Citizens Band Transceiver Digital
Tuners"
The three decades of the intermediate counter can be
preset to a binary 15 instead of a binary 9, while their place
values are still 1, 10, and 100, multiplied by the number of
the + N mode. For example, in the + B mode, the number
___________________________________________________________________ 523
Technical Data
CD54/74HC4059
CD54/74HCT4059
from which counting down begins can be preset to:
3rd decade:
1500
2nd decade:
150
1st decade:
15
Last counting section 1000
The total of these numbers (2665) times 8 equals 21,320.
The first counting section can be preset to 7. Therefore,
21,327 is the maximum possible count in the -7 8 mode.
The highest count of the various modes is shown in the
column entitled Extended Counter Range of Table I. Control
inputs Kb and Kc can be used to initiate and lock the
counter in the "master preset" state. In this condition the
flip-flops in the counter are preset in accordance with the
jam inputs and the counter remains in that state as long as
Kb and Kc both remain low. The counter begins to count
down from the preset state when a counting mode other
than the master preset mode is selected.
The counter should always be put in the master preset
mode before the -7 5 mode is selected. Whenever the master
preset mode is used, control signals Kb = "low" and Kc =
"low" must be applied for at least 3 full clock pulses.
After the Master Preset Mode inputs have been changed to
one of the -7 modes, the next positive-going clock transition
changes an internal flip-flop so that the countdown can
begin at the second positive-going clock transition. Thus,
after an MP (Master Preset) mode, there is always one extra
count before the output goes high. Fig. 1 illustrates a total
cou nt of 3 (-7 8 mode). I f the Master Preset mode is started
two clock cycles or less before an output pulse, the output
pulse will appear at the time due. If the Master Preset Mode
is not used, the counter jumps back to the "Jam" count
when the output pulse appears.
A "high" on the Latch Enable input will cause the counter
output to remain high once an output pulse occurs, and to
remain in the high state until the latch input returns to "low".
If the Latch Enable is "low", the output pulse will remain
high for only 1 cycle of the clock-input signal.
The C054HC4059 and C054HCT4059 are supplied in 24lead dual-in-line frit-seal ceramic packages (F suffix). The
C074HC4059 and C074HCT4059 are supplied in 24-lead
dual-in-line, narrow-body plastic packages (EN suffix), in
24-lead dual-in-line, wide-body plastic packages (E suffix),
and in 24-lead dual-in-line surface-mount plastic packages
(M suffix). Both types are also available in chip form (H
suffix).
Table I
Mode
Select
Input
Last Counting
Section
First Counting
Section
Can be
Can be
preset
OiKa Kb Kc Oito a
to a
JamJaminputs
vides max.
inputs
vides max.
by:
of:
used:
by:
of:
used:
7
J2,J3,J4
2
1
J1
8
H H H
L H H
4
J1,J2
4
3
J3,J4
3
1
J4
4
J1,J2,J3
2
H L H 5#
J1,J2,J3
2
1
J4
L L H
8
7
10
0
J1,J2,J3,J4 1
H H L
9
X
L L
Master Preset
Master Preset
~o~ preset
x = Don't Care
0J1 = Least significant bit.
J4 = Most significant bit.
Counter
Range
Design Extended
Mo9,!
Max.
15,999
15,999
9,999
15,999
9,999
-
Max.
17,331
18,663
13,329
21,327
16,659
-
#Operation in the -;- 5 mode (1st counting section) requires
going through the Master Presei mode prior to going into
the -;- 5 mode. At power turn-on, Kc must be "low" for a period
of 3 input clock pulses after Vee reaches a minimum of 3 volts.
cp
2'
LE
23
Q
J1
22
J5
J2
21
J6
J3
20
J7
J'
19
J8
J16
18
J9
J15
17
J10
16
J1.
J13
10
Vcc
'5
J"
J12
Kb
Kc
11
,.
GND
'2
'3
K.
TOP VIEW
92CS-40496
TERMINAL ASSIGNMENT
524 ___________________________________________________________________
____________________________________________________________ TechnicaIOata
CD54/74HC4059
CD 54/74H CT4059
How to Preset the CD54/74HC/HCT4059 to Desired -;- N
The value N is determined as follows:
N = (MODE") (1000 x Decade 5 Preset + 100 x Decade 4 Preset + 10 x Decade 3 Preset +
1 x Decade 2 Preset) + Decade 1 Preset
(1 )
"MODE = First counting section divider (10,8,5,4, or 2)
To calculate preset values for any N count, divide the N count by the Mode. The resultant is the corresponding
preset values of the 5th through 2nd decade with the remainder being equal to the 1st decade value.
N
Preset Value = _ _ _
Mode
(2)
Example:
N
=8479, Mode =5
r--..
~
1695+4
5
I
Mode Select = 5
Ka Kb Kc
H
L
H
Preset Values
8479
t \
Mode
N
Program Jam Inputs (BCD)
4
5
~J1
J2
J3
J4
L
L
H
J5
J6
J7
J8
H
L
H
L
H
6
9
/'.
r
"
"....
r
"
.......
r
J9
J10
J11
J12
J13
J14
J15
J16
H
L
L
H
L
H
H
L
"
To verify the results, use Equation 1:
N = 5 (1000 x 1 + 100 x 6 + 10 x 9 + 1 x 5) + 4
N = 8479
PROGRAM JAM INPUTS (BCD)
12
GND
Vee
024
0-
CLOCK
INPUT
P. E.
FIRST
LAST
COUNTt NG
SECTION
COUNT ING
SECTION
-:-10,8,5,4,2
-:-1,2,2,4,8
-:- 10
I I
I
________ J II
___________ J
DIVI DE -BY - N
OUTPUT
92CM-22213RI
Fig. 1 - Functional block diagram.
___________________________________________________________________ 525
Technical Data
CD54/74HC4059
CD54/74HCT4059
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, 1,K (FOR V, < -0.5 V OR V, > Vee +0.5 V) .................................................... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) ................................................ ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) .................................................. ±25 mA
DC Vee OR GROUND CURRENT (Icc) ........................................... , .....•.........................•....... ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60°C (PACKAGE TYPE E) ............................................................................ 500 mW
For T. = +60 to +85°C (PACKAGE TYPE E) ............................................... Derate Linearly at 8 mW/oC to 300 mW
For T. = -55 to +100' C (PACKAGE TYPE F,H) ......................................................................... 500 mW
For T. = +100 to +125' C (PACKAGE TYPE F,H) .......................................... Derate Linearly at 8 mW/oC to 300 mW
ForT. = -40 to +70°C (PACKAGE TYPE M) ........................................................................... 400 mW
For T. = +70 to +125° C (PACKAGE TYPE M) .............................................. Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F,H .......................................................................................... -55 to +125'C
PACKAGE TYPE E,M ........................................................................................... -40 to +85' C
STORAGE TEMPERATURE (Tot,) ................................................................................. -65 to +150'C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
. ................................................. +265'C
Unit inserted into a PC Board (min. thickness 1116 in., 1.59 mm)
with solder contacting lead tips only ................................................................................ +300'C
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation Is always within
the following ranges:
CHARACTERISTIC
LIMITS
UNITS
MIN_
MAX.
2
4.5
0
6
5.5
Vcc
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
Supply-Voltage Range (For T.-Full Package Temperature Range)
Vee:*
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage, V" Va
Operating Temperature, T.:
CD74 Types
CD54 Types
Input Rise and Fall Times,.t"t,:
at 2 V
at 4.5 V
at 6 V
V
V
'Unless otherwise specified, all voltages are referenced to Ground.
526 ___________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4059
CD54/7 4HCT 4059
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT4059/CD54HCT4059
CD74HC4059/CD54HC4059
I
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
TYPES
TYPES
TYPES
CONOITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85°C
+125" C
+85"C
+125°C
CONDITIONS
UNITS
CHARACTERISTIC
+25°C
V,
10
Vee
V
rnA
V
High-Level
Input Voltage
V'H
low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
VOH
CMOS Loads
or
-0.02
V'H
+25°C
Min Typ Max Min Max Min Max
2
1.5
-
-
1.5
-
1.5
-
4.5
3.15
6
4.2
-
-
3.15
-
3.15
-
-
-
4.2
-
4.2
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
Low-Level
Output Voltage
CMOS Loads
-
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
V"
or
6
5.9
-
-
5.9
-
5.9
-
V'H
4.5 3.98
-
-
3.84
-
3.7
-
-
-
2
-
2
-
V
to
-
-
0.8
-
0.8
-
0.8
V
or
5.48
-
-
5.34
-
5.2
-
V'H
4.5
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
3.7
-
V
V"
-5.2
6
2
-
-
0.1
-
0.1
-
0.1
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V"
or
6
-
-
0.1
-
0.1
-
0.1
V'H
4.5 3.98
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
J1A
5.5
-
-
8
-
80
-
160
J1A
-
100 360
-
450
-
490
J1A
V"
or
4
4.5
-
-
0.26
-
0.33
-
0.4
or
V'H
5.2
6
-
-
0.26
-
0.33
-
0.4
V'H
6
-
-
±0.1
-
±1
-
±1
Any
I,
Vee
or
Gnd
Quiescent
Voltage
Between
Vee & Gnd
Vee
Vee
Icc
or
a
6
-
-
8
-
80
-
or
160
Gnd
Gnd
Additional
4.5
Quiescent Device
Vee -2.1
Current per input
pin: 1 unit load
2
5.5
Input Leakage
Device Current
to
4.5
-
V'H
or
Min Typ Max Min Max Min Max
5.5
V"
Current
V
-4
V'H
TTL Loads
V
or
V"
Voe
Vee
4.5
V"
TTL Loads
V,
to
5.5
Dolce
*For dual-supply systems theoretical worst case (VI:::: 2.4 V, Vee:::: 5.5 V) specification is 1.8
mAo
HCT Input Loading Table
Input
All J Inputs
CP
LE
Ka
Kb
Kc
Unit Loads'
0.5
0.65
1.65
1
1.5
0.85
'Unil Load is t.lcc limit specified in Static Characteristics
Chart, e.g., 360 JiA max. @ 25 0 C.
____________________________________________________________ 527
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4059
CD 54/74HCT4059
SWITCHING CHARACTERISTICS (Vee=5 V, TA=25°C, Inpul 1,,1,=6 ns)
CL (pF)
CHARACTERISTIC
Propagation Delay:
CPtoQ
LEtoQ
CP Frequency
Power Dissipation Capacitance*
tPLH
tPHL
fMAX
Cpo
TYPICAL VALUES
HC
HCT
15
17
19
15
14
54
36
19
50
36
-
UNITS
ns
MHz
pF
*CPO is used to determine the dynamic power consumption, per package.
Po = Cpo Vee 2 fi + I CL Vee 2 fo where. f; = input frequency
fo = output .frequency
CL = output load capacitance
Vee = supply voltage.
PRE-REQUISITE FOR SWITCHING FUNCTION
CHARACTERISTIC
Pulse Width
CP
tw
Setup Time
Kb, Kcto CP
tsu
CP Frequency
fMAX
TEST
CONDITIONS
Vee (V)
2
4.5
6
2
4.5
6
2
4.5
6
LIMITS
_40° C 10 +85° C
-55°Clo+125°C
74HCT
HC
HCT
74HC
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
90
- 115 135 18
20
23
25
27
30
15
20
23
ns
75
95
110 15
19
19
22
22
15
13
16
19
4
5
4
27
25
22
20
18
17
MHz
32
26
21
25°C
-
528~---------------------------------
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD 54/74H C4059
CD 54/74HCT4059
SWITCHING CHARACTERISTICS (C L =50 pF, Inpul 1,,1,=6 ns)
LIMITS
-55° C 10 +125° C
-40° C 10 +85° C
54HCT
UNITS
HC
HCT
74HCT
54HC
74HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
25°C
CHARACTERISTIC
VCC
(V)
Propagation Delay
tPLH
tPHL
CP to Q
LE to Q
Output Transition
Time
Input Capacitance
tTLH
hHL
C,
2
4.5
6
2
4.5
6
2
4.5
6
-
200
40
34
175
35
30
75
15
13
10
-
-
-
-
-
-
-
46
46
15
10
-
-
-
250
50
43
220
44
37
95
19
16
10
-
58
-
-
-
58
19
10
-
-
-
-
-
300
60
51
265
53
45
110
22
19
10
-
-
-
69
69
22
ns
-
10
pF
INPUT
LEVEL
CP
GND
Kb OR Kc
GND
'su
INPUT
LEVEL
CP
Q
GND
92CS-40494
92C5-40493
Input Level
Switching Voltage, Vs
Fig. 2 - Transition times, propagation delay times, and setup times.
_______________________________________________ 529
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4060
CD54/74HCT4060
File Number
1654
High-Speed CMOS Logic
04
05
MR
'2
RIPPLE
COUNTER
AND
~I
"
OSCILLATOR
14-Stage Binary Counter with Oscillator
06
14-STAGE
07
'4
13
,
'5
OS
09
010
0'2
013
0'4
Type Features:
•
•
•
•
Onboard oscillator
Common reset
Negative edge clocking
Typical fMAX = 50 MHz @ Vee = 5 V, CL = 15 pF, h = 25 0 C
FUNCTIONAL DIAGRAM
Family Features:
The RCA-CD54/74HC4060 and CD54174HCT4060 each
consists of an oscillator section and 14 ripple-carry binary
counter stages. The oscillator configuration allows design
of either RC or crystal oscillator circuits. A Master Reset
input is provided which resets the counter to the all-O's state
and disables the oscillator. A high level on the MR line
accomplishes the reset function. All counter stages are
master-slave flip-flops. The state of the counter is advanced
one step in binary order on the negative transition of tPl (and
tPo). All inputs and outputs are buffered. Schmitt trigger
action on the input-pulse line permits unlimited rise and fall
times.
•
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85 0 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to
LSTTL Logic ICs
• Alternate Source is Philips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 30%, MH = 30% of Vee; @ Vee = 5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L =0.8 V Max., V,H =2 V Min.
CMOS Input Compatibility
I, S 1 pA @ VOL, V OH
In orderto achieve a symmetrical waveform in the oscillator
section the HCT4060 input pulse switch points are the same
as in the HC4060; only the MR input in the HCT4060 has
TTL switching levels.
The CD54HC4060 and CD54HCT4060 are supplied in 16lead hermetic dual-in-line ceramic packages (F suffix). The
CD74HC4060 and CD74HCT4060 are supplied in 16-lead
dual-in-line plastic packages (E suffix) and in 16-lead dualin-line surface mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
,----1
9
1
01 -
4
04
5
013
I
FFI
,
MA
4'i
FF4
01
R
-
4'4_
A
04
14 014
I
1 FF5-FFI3 I
1_I
5
013
14 014
ii
A
J
FFI4
'2
I
5,4,6.14,13,15.1
05- 010. 012
Fig. 1 - Logic block diagram.
92CS - 38494A,
530 ____________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4060
CD54/74HCT4060
TRUTH TABLE
if>
"'I
MR
OUTPUT STATE
...r
L
No Change
'-
L
Advance to Next State
X
H
All Outputs are Low
92CS-3B493
Fig. 2 - Flip-flop detail.
H = high level (sieady slale)
L = low level (sleady slale)
X = don'l care
MAXIMUM RATINGS. Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Vollages referenced 10 ground) ......................................................................................-0.5 10 +7 V
DC INPUT DIODE CURRENT,!,. (FOR V, < -0.5 V OR V, > Vee +0.5 V) •.••.......•....•..•..•........•................••••... ±20 rnA
DC OUTPUT DIODE CURRENT, 10. (FOR Va < -0.5 V OR Va > Vee +0.5 V) .•........••.•.••••.....................•.••....... ±20 rnA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Va < Vee +0.5 V) .................................................... ±25 rnA
DC Vee OR GROUND CURRENT, (lee) ..................................................................................... ±50 rnA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 10 +60· C (PACKAGE TYPE E) ............................................................................... 500 mW
For T. = +6010 +85aC (PACKAGE TYPE E) .................................................. Derale Linearly al8 mW/·C 10 300 mW
ForT. = -5510 +1OO·C (PACKAGE TYPE F, H) ........................................................................... 500 mW
For T. = +100 10 +125·C (PACKAGE TYPE F, "'.
. ........................................ Derale Linearly al8 mW/·C 10300 mW
For T. = -40 10 +70aC (PACKAGE TYPE M) .............................................................................. 400 mW
For T. = +7010 +125aC (PACKAGE TYPE M) ................................................. Derale Linearly al6 mW/·C 10 70 mW
OPERATING-TEMPERATURE RANGE (1.):
PACKAGE TYPE F, H.............................................................................................. -5510 +125· C
PACKAGE TYPE E, M .............................................................................................. -4010 +85· C
STORAGE TEMPERATURE (T... ) .................................................................................... -6510 +150·C
LEAD TEMPERATURE (DURING SOLDERING):
AI distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
. .................................................... +265·C
Unit inserted into a PC Board (min. thickness 1/16 in" 1.59 mm)
with solder contacling lead tips only ............................................. ...................................... +3oo·C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation Is always within the following ranges:
CHARACTERISTIC
. Supply-Voltage Range (For TA-Full Package-Temperature Range) Vee:·
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V" Va
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t r, tf
at2V
at4.5V
at6V
LIMITS
UNITS
MIN •
MAX.
2
4.5
0
6
5.5
Vee
-40
-55
+85
+125
ac
0
0
0
1000
500
400
ns
V
V
·Unless otherwise specified, all voltages are referenced to Ground.
________________________________________________________________ 531
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4060
CD54/74HCT4060
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT~.CD54HCT~
CD74HC4060. CD54HC4060
TEST
74HC/54HC
CONDITIONS
TYPES
74HC
TYPE
54HC
TYPE
TEST
74HCT/54HCT
CONDITIONS
TYPES
74HCT
54HCT
TYPE
TYPE
CHARACTERISTIC
UNITS
+25°C
V,
10
Vee
V
mA
V
-401
-551
+85°C
+125°C
Vee
V
V
Min Typ MI' Min Max Min Max
High-Level
Inpul Voltage
V'H
Low-Level
Input Voltage
V'L
2
1.5
-
-
1.5
-
1.5
-
4.5
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
1.35
1.8
-
1.8
-
-
6
High-Level
Outpul Voltage
Q Output.
VIL
VOH
CMOS Loads
High-Level
Output Voltage
Q Outputs
TTL Loads
Low-Level
Output Voltage
Q Outputs
or
-0.02
V'H
2
1.9
4.5
4.4
6
5.9
-
1.9
-
4.4
-
5.9
1.9
4.4
5.9
VOH
-
VIL "
-
or
CMOS Loads
Low-Level
Output Voltage VOL
Q Outputs
TTL Loads
-
3.7
-
or
5.2
-
V'H
-
-
0.1
-
0.1
-
0.1
VIL "
-
-
0.1
-
0.1
-
0.1
or
-
0.1
-
0.1
-
0.1
V'H
2
4.5
6
V'H
VIL
VIL
or
4
4.5
V'H
5.2
6
-
-
2
-
V
-
-
O.B
-
O.B
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
..
-
0.02
or
V'H
5.34
5.48
2
to
3.84
3.98
6
-
5.5
-
4.5
-
4.5
-
-
-4
-5.2
2
to
5.5
-
or
VIL
VOL
4.5
-
V'L
V'H
-551
+l25°C
Min Typ Max Min M.. Min MI'
1.8
V'L
-401
+85°C
+25°C
V,
-
0.26
-
0.33
-
0.4
or
-
0.26
-
0.33
-
0.4
V'H
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
..
··For Pin 11 VIH=3.15 V. VIL =0.9 V.
532 _______________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4060
CD54/74HCT 4060
STATIC ELECTRICAL CHARACTERISTICS (Confd)
CD74HCT4060, CD54HCT4060
CD74HC4060, CD54HC4060
TEST
74HC/54HC
CONDITIONS
TYPES
TEST
74HCT/54HCT
CONDITIONS
TYPES
54HC
74HC
TYPE
TYPE
-401
-55/
+85°C
+12SoC
74HCT
54HCT
TYPE
TYPE
UNITS
CHARACTERISTIC
+25°C
V,
10
Vee
V
rnA
V
Vee
V
V
High-Level
VOH
Output Voltage
q)O Output (Pin 10)
TTL Loads
Vee
or
1.9
-
-
4.5
4.4
-
6
5.9
-
2
-0.02
Gnd
1.9
-
-
4.4
-
or
-
5.9
-
Gnd
1.9
-
-
4.4
-
5.9
Vee
or
-2.6
4.5
3.98
-
-
3.84
-
3.7
-
or
0
Gnd
-3.3
6
5.48
-
-
5.34
-
5.2
-
Gnd
Low-Level
Output Voltage
VOL
q)O Output (Pin 10)
CMOS Loads
Vee
2
-
-
0.1
-
0.1
-
0.1
Vee
0.02
4.5
-
-
0.1
-
0.1
-
0.1
6
-
-
0.1
-
0.1
-
0.1
Low-Level
Output Voltage
VOL
q, 0 Output (Pin 10)
TTL Loads
Gnd
4.5
-
-
0.26
-
0.33
-
0.4
or
Gnd
3.3
6
-
-
0.26
-
0.33
-
0.4
Gnd
or
-3.2
4.5
3.98
-
-
3.84
-
3.7
-
Input Leakage
or
V,H
-4.2
6
5.48
-
-
5.34
-
5.2
-
V,H
Quiescent
Current
or
3.2
4.5
-
-
0.26
-
0.33
-
0.4
or
V,H
4.2
6
-
-
0.26
-
0.33
-
0.4
V,H
Any
Voltage
between
Vee
&
Gnd
or
6
-
-
±D. 1
-
±1
-
±1
6
-
-
8
-
80
-
160
Gnd
Vee
or
Device
Icc
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
4.5
3.98
-
-
3.84
-
3.7
-
V
V 1L ••
V,L
Vee
"
-
V 1L ••
VIL
Low-Level
VOL
Output Voltage
'" 0 Output (Pin 9)
TTL Loads
-
Vee
2.6
'" 0 Output (Pin 9)
TTL Loads
4.4
Gnd
or
VOH
Output Voltage
Current
or
-
Vee
High-Level
4.5
Vee
Vee
or
-55/
+125°C
Min Typ Max Min Max Min Max
Min Typ Max Min Max Min Max
High-Level
VOH
Oulpul Voltage
~o Output (Pin 10)
CMOS Loads
-40/
+85°C
+25°C
V,
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±D.1
-
±1
-
±1
pA
5.5
-
-
8
-
80
-
160
pA
-
100
360
-
450
-
490
pA
Vee
a
Gnd
or
Gnd
Additional
4.5
Quiescent
Vcc-2.1
Device Current
to
5.5
per input pin:
1 unit load
1l.lcc
For dual supply systems theoretical worst case (VI - 2.4 V, Vee - 5.5 V) specification IS 1.8 rnA.
0"
"Pin II VIL::: O.9V, VIH::: 3.15V
" Vee
15 Q10
(>Umits not valid when pin 12 (instead of pin 11) is used as control input.
0"
14 08
13 09
HCT INPUT LOADING
INPUT
MR
'Unit load is t:. Icc limit specified in
Static Characteristics Chart,
e.g., 360 pA max. @ 25° C.
UNIT LOADS·
0.35
05
12 MR
0'
w-,0
11 ~"I
GND
9",
TERMINAL ASSIGNMENT
______________________________________________________________________ 533
TechnicaIOala _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4060
CD54/74HCT4060'
SWITCHING CHARACTERISTICS (Vcc=5 V, T A=25°C,lnput t" 1,=6 nl)
Typical
CHARACTERISTIC
UNITS
CL
Propagation Delay ~ I to O.
tpLH
pF
HC
HCT
15
25
25
ns
15
6
6
ns
tPHL
Propagation Delay On to On+1
tpLH
tpHL
Propagation Delay MR to On Output
tpHL
15
14
17
ns
Propagation Dissipation capacitance·
CPO
-
40
40
pF
Cpo is used to determine the dynamic power consumption, per package.
PO
=Cpo Vee? II +
I (CL Vee? I;IM) wher.:
M = 2\ 22. 23, .. 21•
CL =output load capacitance
fi = input frequency
Prerequisite for Switching Function
25°C
CHARACTERISTIC
SYMBOL
Vee
HC
Min.
Maximum Input Pulse
Frequency
Input Pulse Width
"Max.
tMAX
4.5
30
6
35
30
4.5
16
6
14
4.5
4.5
SYMBOL
Propagation Delay
tplH
~I
tpHl
(Figure 4)
Propagation Delay
tplH
On to Q n+1
tpHl
(Figure 4)
26
Vee
tTLH
tTHL
(Figur.4)
C,'
24
ns
26
39
ns
38
ns
--
120
31
24
17
HC
20
-4Q°C to +85°C
74HC
HCT
Max.
Min.
Max.
60
6
51
16
6
14
15
6
13
Max.
75
20
44
16
Min.
UNITS
Max.
90
100
ns
24
24
ns
66
ns
22
ns
20
265
55
53
45
95
19
54HCT
Max.
120
20
37
15
Min.
78
220
44
54HC
450
83
17
75
4.5
Min.
100
16
175
35
Max.
64
80
4.5
Min.
-55°C to +125°C
74HCT
375
66
30
Time
-
:--
20
300
4.5
Output Transition
30
33
100
4.5
tpHL
an
24
150
25
25
MHZ
20
21
16
20
= 50 pF, Input t. tf = 6n5)
(Figure 5)
534
UNITS
Max.
120
20
125
20
Min.
'TBO
Min.
23
25°C
Input Capacitance
54HCT
Max.
20
17
80
tw
SWITCHING CHARACTERISTICS (CL
MR to
Min.
25
20
14
Propagation Delay
54HC
Max.
100
16
100
tREM
(Figure 5)
1004
Min.
29
17
CHARACTERISTIC
Max.
25
80
Iw
(Figure 5)
Reset Pulse Width
Min.
6
(Figure 4)
Reset Removal Time
--
Min.
74HCT
74HC
HCT
Max.
110
19
22
19
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4060
CD54/74HCT 4060
TYPICAL LIMIT VALUES FOR Rx AND Cx
CHARACTERISTIC
Rx Min.
Rx Max.
ex Min.
Maximum Astable
Oscillator Frequency
TEST CONDITIONS
VOLTAGE
e x >1000pF
e x >10pF
ex> 10 pF
e x >10pF
e x >10pF
ex> 10 pF
Rx> 10 KO
Rx> 10 KO
Rx> 10 KO
Rx = 1 KO
Rx = 1 KO
Rx = 1 KO
ex = 1000 pF, Rx - 1 KO
ex = 100 pF, Rx = 1 KO
e x =100pF,R x =1KO
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
TYPICAL
MAXIMUM
LIMITS
1 KO
20MO
10 pF
1000 pF
10 pF
10 pF
0.5 MHz'
3 MHz'
3 MHz'
• At very high frequencies f = 1/2.2 Rxex no longer gives an accurate approximation .
...
""
I
X
,
U 10-2:
,
10-3
~
,
10-4 :
92C5- 38395
10-5
468
:2
10 2
10
468
:2
468
103
2
468
104
Fig. 4 -Input pulse pre-requisite times, propagation delays
and output transition times for both He and HCT types.
2
10 5
10 6
OSCILLATOR FREQUENCY Hz
92C5- 384 92RI
osc FREQUENCY = 1/2.2 RXeX
FOR 1 MO
> RX > 1 KQ,
CX>tOpF,f<1 MHZ
Fig. 3 - Frequency of on-board oscillator as a function of Cx and Rx.
VCC-~.
0/>1
50"1.
t rem
INPUT LEVEL - -
MR
r----,I
vs
54174HC
MR Input Level
Switching Voltage, Vs
VCC
SO%VCC
54174HCT
3V
1.3 V
92CS-38399RI
Fig. 5 - Master Reset pre-requisite and propagation delays.
__________________________________________ 535
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4066
CD54/74HCT4066
File No.
1777
High-Speed CMOS Logic
,.
13
1Y
1Z
2'
2Y
3'
3Y
Quad Bilateral Switch
2Z
3Z
4.
12
11
10
4Y
4Z
Vee = 14
GNO = 7
92CS-39851
Type Features:
•
•
•
•
Wide analog-input-voltage range: 0-10 V
Low "ON" resistance: 25 0 @ Vee = 4.5 V
150 @ Vee = 9 V
Fast switching and propagation delay times
Low "OFF" leakage current
FUNCTIONAL DIAGRAM
The RCA CD54174 HC/HCT4066 contains four independent
digitally controlled analog switches that use. silicon-gate
. CMOS technology to achieve operating sl'leeds similar to
LSTTL with the low power consumption of standard CMOS
integrated circuits.
These switches feature the characteristic linear "ON"resistance of the metal-gate CD4066B. Each switch is
turned on by a high-level voltage on its control input.
The CD54HC4066 and CD54HCT4066 are supplied in 14lead hermetic dual-in-line ceramic packages (F suffix).The
CD74HC4066 and CD74HCT4066 are supplied in 14-lead
dual-in-line plastic-packages (E suffix) and in 14-lead dualin-line surface mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
Family Features:
•
•
•
•
Alternate Source: Philips/Signetics
Wide operating temperature range:
CD74HC/HCT: -40 to +85 0 C
CD54HC/CD74HC types:
2 V to 10 V operation
High noise immunity:
ML = 30%, MH = 30% of Vee; @Vee = 5 V & 10 V
CD54HCT/CD74HCT types:
Direct LSTTL input logic compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS input compatiblity
I, :::; 1 pA @ VOL, VOH
nY
TRUTH TABLE
n.
INPUT
nE
SWITCH
L
off
H
on
H = HIGH Level
L = LOW Level
92C$-39859
Fig. 1 - Logic diagram (one switch).
536 ____________________________________________________________
- - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical.Data
CD54/74HC4066
CD54/74HCT4066
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground)
HCT Types .......................................................................................................... -0.5 to +7 V
HC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. -0.5 to +10.5 V
DC INPUT DIODE CURRENT, 1,K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ....................................................... ±20 mA
DC SWITCH DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) .................................................... ±20 mA
e, DC SWITCH CURRENT, 10, (FOR V, > -0.5 V OR V, < Vee + 0.5 V) ............................................................ ±25 mA
DC Vee OR GROUND CURRENT (Icc) ......•... , ........................................................................... ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For T A = -40 to +60° C (PACKAGE TYPE E) ............................................................................... 500 mW
For TA = +60 to +85° C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/o C to 300 mW
ForTA = -55 to +100°C (PACKAGE TYPE F, H) ........................................................................... 500 mW
For TA = +100 to +125°C (PACKAGE TYPE F, H) ..............•.............................. Derate Linearly at 8 mW;o C to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) ............................................................................... 400 mW
For TA = +70 to +125°C (PACKAGE TYPE M) ................................................. Derate Linearly at 6 mW;o C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H ............................................................................................. -55 to +125°C
PACKAGE TYPE E, M ...............................................................................................-40 to +85°C
STORAGE TEMPERATURE (T",) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for lOs max ........................................................ +265° C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................................................................................... +300° C
e In certain applications, the external load-resistor current may include both Vee and signal-line components. To avoid drawing Vee current
when switch current flows into the transmission gate inputs, (terminals 1,4,8 and 11) the voltage drop across the pidirectional switch must
not exceed 0.6 volt (calculated from Roo values shown in the Electrical Characteristics Chart). No Vee current will flow through RL ifthe switch
current flows into terminals 2, 3, 9 and 10.
1Y
1Z
2Z
2Y
2.
14
13
12
11
10
vee
,.
4.
4Y
4Z
3.
3Z
GND
3Y
92CS-39852
TERMINAL ASSIGNMENT
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 537
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4066
CD54/74HCT4066
RECOMMENDED OPERATING CONDITIONS: For maximum reliability, nominal operating conditions should be selected so
that operation is always within the following ranges'
LIMITS
UNITS
CHARACTERISTIC
MIN.
MAX.
Supply-Voltage Range (For TA - Full Package-Temperature Range) Vee:'
10
2
CD54/74HC Types
4.5
V
5.5
CD54174HCT Types
0
DC Input Voltage. Vc, and Analog Switch Voltage, V'/O
Vcc
Operating Temperature T A:
+85
-40
CD74 Types
°C
-55
+125
CD54 Types
Input Rise and Fall Times t" tf (Control Inputs)
at 2 V
at 4.5 V
at 9 V
'Unless otherwise specified, all voltages are referenced to Ground.
STATIC ELECTRICAL CHARACTERISTICS
CD74HC4066/CD54HC4066
CHARACTERISTIC
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
CON-
sw-
TROL
ITCH
Vee
V,
V's
V
V
V
-
-
Low-Level
Input Voltage
V"
CD74HCT4066/CD74HCT4066
TEST
+25°C
-
-
-401
-551
CON-
sw-
+85°C
+125°C
TROL
ITCH
Vee
V,
V's
V
V
V
-
-
Min Typ Max Min Max Min Max
1.5
-
-
1.5
-
1.5
-
4.5 3.15
-
-
3.15
-
3.15
-
2
V,"
ns
CONDITIONS
High-Level
Input Voltage
1000
500
250
0
0
0
4.5
to
6.3
-
-
6.3
-
6.3
-
5.5
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
9
-
-
2.7
-
2.7
-
2.7
Input Leakage
-551
+125°C
Min Typ Max Min Max Min Max
9
4.5
-401
+85°C
+2So.C
-
-
to
2
-
-
2
-
2
V
-
-
O.B
-
O.B
-
O.B
-
-
±0.1
-
±1
-
±1
5.5
Any
Current
Voltage
Vee
(Any Control)
1"
or
-
10
-
-
i±0.1
-
±1
-
±1
Gnd
Between
-
5.5
Vee &
/JA
Gnd
Off-Switch
V"
Current
I,
Vee
10 = 1 mA
(Fig. 2)
or
Roo
Vee
Vee
or
lee
±0.1
-
±1
-
±1
V"
-
±0.1
-
±1
-
±1
-
25
80
-
106
-
-
-
-
-
12B
-
5.5
-
Vee
4.5
or
-
or
Gnd
4.5
-
25
BO
-
106
-
12B
6
-
20
75
-
94
-
113
Gnd
9
-
15
60
-
7B
-
95
Gnd
-
-
-
-
-
-
-
-
Vee
4.5
-
35
95
-
11B
-
142
Vee
4.5
-
35
95
11B
-
142
to
6
-
24
B4
-
105
-
126
to
-
-
-
-
9
-
16
70
-
BB
-
105
Gnd
-
-
-
-
-
-
-
Gnd
-
-
4.5
-
1
-
-
-
-
-
4.5
-
1
-
-
-
-
-
6
-
0.75
-
-
-
-
-
-
-
-
-
-
-
-
-
9
-
0.5
-
-
-
-
-
-
-
-
6
-
-
2
-
20
-
40
10
-
-
16
-
160
-
320
5.5
-
-
2
-
20
-
40
-
100 360
-
450
-
490
-
Vee
Device
-
or
t.Roo
Quiescent
-
Vee
"On" Resistance
Between Any Two
10
Gnd
"On"
Resistance
Current
Vee
Vee
Leakage
Switches
UNITS
-
Gnd
Vee
Vee
Vee
-
-
(l
-
Vee
or
-
Gnd
Additional
Quiescent Device
-
-
-
-
-
-
-
-
-
Vcc-2.1
Input Pin:
1 Unit Load
*
/JA
4.5
-
Current per
-
to
5.5
dice
For dual-supply systems theoretical worst case (VI = 2.4 V, Vee
=
5.5 V) specification is 1.8 mAo
538 ____________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4066
CD54/74HCT4066
HCT Inpul Loading Table
Unll Loads *
Inpul
All
, Unit load is fl.lee limit specified in Static Characteristic
Chart, e.g., 360 /lA max. @ 25°C.
SWITCHING CHARACTERISTICS (Vee
=5 V, T A =25° C, Inpul I" If = 6 ns)
TYPICAL
CHARACTERISTIC
Propagation Delay Time:
UNITS
CL
pF
HC
HCT
15
4
4
tpHL
Switch In to Out
tPLH
Switch Turn Off
tPHZ, tpLZ
15
12
14
Switch Turn On
tPZH. tPZL
15
8
9
-
25
38
ns
Power Dissipation Capacitance'
Cpo
, Cpo is used to determine the dynamic power consumption, per package.
Po = Cpo Vee 2 f, + ! (CL + Cs) Vee 2 fo where: f, = input frequency
CL = load capacitance
Vee = supply voltage
pF
fo = output frequency
Cs = switch capacitance
SWITCHING CHAARACTERISTICS (CL = 50 pF, Input t" tf = 6 ns)
25°C
CHARACTERISTIC
HC
Vee
-55°C to +125°C
-40° C to +85° C
HCT
74HC
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay Time
Switch In to Out
Switch Turn On Delay
tpLH
2
-
60
-
-
-
75
-
-
-
90
-
tPHL
4.5
-
12
-
12
-
15
-
15
-
18
-
18
9
-
8
-
-
-
11
-
-
-
13
-
-
tPZH
2
-
100
-
-
-
125
-
-
-
150
-
-
tPZL
4.5
-
20
-
24
-
25
-
30
-
30
-
36
9
-
12
-
-
-
15
-
-
-
18
-
-
-Switch Turn Off Delay
t PHZ , t pLZ
2
-
150
-
-
-
190
-
-
-
225
-
-
4.5
-
30
-
35
-
38
-
44
-
45
-
53
9
-
24
-
-
-
30
-
-
-
36
-
-
-
-
10
-
10
-
10
-
10
-
10
-
10
ns
Input (Control)
Capacitance
C,
pF
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 539
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54n4HC4066
CD54/74HCT4066
ANALOG CHANNEL CHARACTERISTICS - Typical Values at Te = 25°C
CHARACTERISTIC
TEST CONDITIONS
Switch Frequency Response Bandwidth
at -3 dB
Vee
V
HC
HCT
UNITS
4.5
200
200
MHz
4.5
-72
-72
dB
Fig.3
(Fig. 12)
Notes 1 & 2
Cross Talk Between Any Two Switches
Fig.4
(Fig. 13)
Notes 2 & 3
Total Harmonic Distortion
Control to Switch Feedthrough
1 KHz.
I
V's = 4 Vpp
4.5
0.022
0.023
Fig.5
I
V's = 8 Vpp
9
0.008
NIA
4.5
TBE
TBE
9
TBE
TBE
4.5
-72
-72
dB
5
pF
%
Fig.6
mV
Noise
Switch "OFF" Signal Feedthrough
Fig.7
(Fig. 13)
Notes 2 & 3
-
Switch Input Capacitance
Cs
Notes: 1. Adjust mput level lor 0 dBm at output. 1= 1 MHz.
-
5
2. V's IS centered at Vee/•.
3. Adjust input lor 0 dBm at V's.
Q
I
Z40
~
w
~
_ _ _ _ _VCC=4.5V.P'N1TO.
U
~
..
iii
Vee= BY, PIN 1 T03
I
~
10
o
4
4.5
5
8
7
9
INPUT SIGNAL VOLTAGE (V1s}-Y
10
92CS-39 aDa
Fig. 2 - Typieal "ON" resistance vs. input signal voltage.
vee
ANALOG TEST CIRCUITS
Vcc/2
r~_T_"eRI
O.1J.1F
R
1-....--..---VOS1
--It--''WV+i
INPUT
Vee
VCC/2
Fig. 3 - Frequency response test circuit.
Vee
'IS=1 MHz SINE WAVE
R=50Q
C:=10pF
.O~
Slt.. E
WAVE
V'8--1
10pF
~
Vee/.
Fig. 4 - Crosstalk between two switches teit circuit.
'IS=1 kHzT010kHz
Vee
'IS ~ 1MHz SINE WAVE
VOS~R~~~F
Vcc12 ·
tr.tf~8n.
'CONT=1 MHz
50 'Ib DUTY
cYCLE
dB
METER
92CM:'39840
- Control-to-switch
feedthrough
test_
circuit.
- Switch
off_
signal
MOFIg.
_6_
_____
_ _ _noise
__
_ _ _ _ _ _ _Fig.
_7_
__
_ feedthrough.
_ _ _ _ _ _ __
_____________________________________________________________ TechnicaIData
I, = 6
CD 54/74H C4066
CD 54/74HCT4066
r
nS1
l
rl~;U~ ~~VEL
--90%
~
--- Vs
- - - - - - - - - - - ----10
E
%
IpLZ-t----1
OUTPUT
LOW TO O:.;F'-F'-t-____.. - - - - l 0 %
IpHZ -+----1
V--
'K:--- 90 %
I ""'--
OUTPUT
HIGH TO OFF
/,'----50 %
92CS-39935
SWITCH ON---L-SWITCH
OFF~SWITCH
ON
92CS-39936
Fig. 9 - Switch turn-on and turn-off propagation delay times
waveforms.
Fig. 8 - Switch propagation - delay times waveforms.
Input Level
Switching Voltage, Vs
54174HC
54174HCT
Vee
3V
50% Vee
1.3 V
RL = 1 kn
{
GND FOR IpLZ AND IPZL} IN~OUT VCC FOR IpLZ AND IpZL
VCC FOR IpHZ AND IpZH
'--' 1-~
GND FOR IpHZ AND IpZH
rCL50 pF
____-
-=
92CS-39937
Fig. 10 - Switch on/off propagation delay time test circuit.
IN o - - - B - - c 0 U T
r
50PF
92C5-38835
Fig. 11 - Switch-in to switch-out propagation delay time test circuit.
CL-l0pF
Vee= 4.5 vllll--I---I-++I-IIII-----c---l-++I-IIII--H++fIIlI-I
RL. = son
;:N:;~ ;cttir--i-+tHitIt---i~tttffir-H++rtffif-l
m
I
z
~
c
I
\
z
c
I
CL=10pF
Vee= 4.5 v
RL :::
son
TA ::: 25'C
PIN4T03
4
68
105
2
4
66
2
4
66
106
FReQUENCY (f) -
107
, "108
Hz
[AI
, " 105
46824662466
106
FREQUENCY (I) -
101
108
H2:
92CS-39850
Fig. 12 - Switch frequency response, Vee
= 4.5
V.
Fig. 13 - Switch-off signal feedthrough and crosstalk vs. frequency,
Vee = 4.5 V.
541
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4067
CD54/74HCT4067
File Number 1783
Advance Information/
Preliminary Data
High-Speed CMOS Logic
COMMON
INPUT/OUTPUT
1
24 Vee
17
23 18
I.
22 19
15
21 110
I.
20 111
I.
19 112
13
18 113
17 114
16 115
"
10
So
GND
E
10
15
,.
14 52
51 11
13 53
' - - - - - - ' 92CS-39909
TOP VIEW
TERMINAL ASSIGNMENT
16-Channel Analog
Multiplexer/Demultiplexer
Type Features:
• Wide analog input voltage range:
• Low "on" resistance:
70 Q typ (Vee = 4.5V)
60 Q typ (Vee = 6V)
• Fast switching and propagation speeds
• "Break-before-make" switching: (6 ns typ @ 4.5V)
• Available in both narrow and wide-body plastic packages
The RCA-CD54/74HC/HCT4067 are digitally controlled
analog switches which utilize Silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the
low power consumption of standard CMOS integrated
circuits.
These analog multiplexers/demultiplexers control analog
voltages that may vary across the voltage supply range.
They are bidirectional switches thus allowing any analog
input to be used as an output and visa-versa. The switches
have low "on" resistance and low "off" leakages. I n addition, these devices have an enable control which when high
will disable all switches to their "off" state.
The CD54HC4067 and CD54HCT4067 are supplied in 24lead dual-in-line frit-seal ceramic packages (F suffix). The
CD74HC4067 and CD74HCT4067 are supplied in 24-lead
dual-in-line, narrow-body plastic packages (EN suffix), in
24-lead dual-in-line, wide-body plastic packages (E suffix),
and in 24-lead dual-in-line surface-mount plastic packages
(M suffix). Both types are also available in chip form (H
suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• CD54/74HC Types:
2 to 6 V Operation
High Noise Immunity:
N'L = 30%, N'H = 30% of Vee.' @ Vee = 5V
• CD54/74HCT Types:'
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V ,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, S 1 IlA @ VOL, V OH
TRUTH TABLE
Selected
BINARY
10F16
DeCODER
Sn = 5 STAGES
E= 4 STAGES·
1
COMMON
INPUT/OUTPUT
15
50
51
52
53
E
Channel
X
0
1
0
X
X
0
0
0
X
0
0
0
1
0
0
0
None
0
0
1
1
0
1
0
1
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
3
4
5
6
1
0
1
0
1
1
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
8
9
10
11
0
1
0
1
0
0
1
1
1
1
1
1
0
0
0
0
12
13
14
15
1
1
1
1
1
0
1
2
7
9~CS-3991IR\
Fig. 1 - Functional diagram.
1 = High Level
0= Low Level
X =Don't Care.
542 ________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4067
CD54/74HCT4067
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) .............
. ........................................................... -0.5 to + 7 V
±20mA
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5V) ..
±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR V, < -0.5 V OR V, > Vee +0.5V) ........................... .
±25mA
DC DRAIN CURRENT, PER OUTPUT (I,) (FOR -0.5 V < V, < Vee + 0.5V)
............ .
±50mA
DC Vee OR GROUND CURRENT (Icc) ............................ .
POWER DISSIPATION PER PACKAGE (Po):
............... 500 mW
For TA = -40 to +60' C (PACKAGE TYPE E) .................. .
For T A = +60 to +85' C (PACKAGE TYPE E) ..
.............
.. Derate Linearly at 8 mWI' C to 300 mW
For T A = -55 to +100' C (PACKAGE TYPE F, H) ........
. ..................................................... 500 mW
For T A = +100 to +125'C (PACKAGE TYPE F, H) ........................................... Derate Linearly at 8 mW/' C to 300 mW
For TA = -40 to +70'C (PACKAGE TYPE M) ....................... . .................................................. 400 mW
For T A = +70 to +125' C (PACKAGE TYPE M) ............................................... Derate Linearly at 6 mW/' C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .......................................................................................... -55 to +125'C
PACKAGE TYPE E, M ...........................
. . . . . . ... . . . ... . . . . . . .. . . . .
. .. . . . ... . . . . . . ... . . .. . .. . . .. -40 to +85'C
-65 to +150'C
STORAGE TEMPERATURE (T"g) ......................................... .
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................. .
+265'C
+300'C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vee:"
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V,N, VauT
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t" tf (Control Inputs)
at 2 V
at4.5 V
at6 V
LIMITS
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
V
V
V
-40
-55
+85
+125
DC
DC
0
0
0
1000
500
400
ns
'Unless otherwise specified, all voltages are referenced to Ground.
_________________________________________________________ 543
TechnicaIData ___________________________________________________________
CD54/74HC4067
CD54/74HCT4067
STATIC ELECTRICAL CHARACTERISTICS
CD74HC/CD54HC4067
TEST
CONDITIONS
CD74HCT/CD54HCT4067
74HC/54HC
TYPES
74HC
TYPE
54HC
TYPE
TEST
CONDITIONS
-40/
-55/
LOGIC SWITCH
+85°C
+125"C
74HCT/54HCT
74HCT
54HCT
TYPES
TYPE
TYPE
+25"C
-40/
+85"C
-55/
+125"C
CHARACTERISTIC
UNITS
LOGIC
SWITCH
V,
V"
Vee
V
V
V
+25"C
V,
V
V"
V
Min Typ Max Min Max Min Max
High-Level
Input Valtage
4.5
Vo<
1.5
1.5
1.5
3.15
3.15
3.15
4.2
4.2
Min Typ Max Min Max Min Max
4.2
V
Low-Level
Input Voltage
Maximum "On"
Resistance
4.5
V"
RON
10= IrnA
Vee
ar
Gnd
Vee
ar
Gnd
4.5
Vee
Vee
to
Gnd
4.5
to
Gnd
Maximum "On"
resistance between
any two switches .6.RON
Switch "Off"
Leakage Current
16 Channels
I"
4.5
0.5
0.5
0.5
1.35
1.35
1.35
1.8
1.8
1.8
70
160
200
240
60
140
175
210
90
180
225
270
80
160
200
240
0.8
0.8
0.8
Vee
ar
Gnd
Vee
ar
Gnd
70
160
200
240
Vee
to
Gnd
Vee
to
Gnd
90
180
225
270
0
10
10
8.5
E:::: Vee
Vee
ar
Gnd
±o.s
±S
±8
±1
±1
E:::: Vee
Vee
ar
Gnd
-
±O.8
-
±O.l
-
±8
±8
±1
±1
Vee
Logic
-
ar
Input Leakage
Current
Gnd
Quiescent
Vee
±O.l
-
JJA
ar
Device Current
10: OmA
Vee
Icc
80
160
Gnd
ar
80
160
Gnd
Additional
Quiescent
Device Current
per input pin:
.6. Icc·
1 unit load
-
·For dual-supply systems theoretical worst case (VI
"Any Voltage Between Vee & Gnd.
Vcc-2.1
100 360
-
450
-
490
=2.4 V, Vee = 5.5 V) specification is 1.8 rnA
HCT INPUT LOADING TABLE
INPUT
UNIT LOADS'
So - S3
0.5
0.3
E
'Unit Load is Ll.lcc limit specified in Static Characteristic
Chart, e.g., 360 JJA max. @25"C.
544 ______________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4067
CD54/74HCT4067
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Inpul I" I, = 6 ns)
TYPICAL
HC
HCT
CL
(pF)
CHARACTERISTIC
Propagalion Delay Time:
Switch In to Switch Out
Switc;h Turn Off
E to Out
Sn to Out
Switch Turn On
E to Out
Sn to Out
t pLH , t pHl
t pLZ ,t pHZ
t pLZ ,t pHZ
t pZL ' t pZH
t pZL ,tpZH
Power Dissipation Capacitance'
15
6
6
15
23
21
23
21
15
23
25
25
25
-
93
96
Cpo
UNITS
ns
pF
'Cpo is used to determine the dynamic power consumption, per package.
fo= output frequency
Po = Cpo Vee' f, +:L (C l + C s) Vee' fo where: f, = input frequency
C l = load capacitance
Cs = switch capacitance
Vee = supply voltage
SWITCHING CHARACTERISTICS (C l = 50 pF, Inpul I" I, = 6 ns)
CHARACTERISTIC
Propagation Delay Time
Switch In to Out
t PLH
t PHL
Switch Turn-On
Eto Out
t PZL
t PZH
Sn to Out
Switch Turn-Off
Eto Out
tpLZ
Sn to Out
t PHZ
Input (Control)
Capacitance
C,
Vee
V
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-
. -40°.C 10 +85 0 C
25°C
-55° C to +125°C
HC
HCT
7.4HC
74HCT
54HC
UNITS
54HCT
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
95
75
110 19
19
15
15
22
22
13
16
19
275
345
415
55
60
69
75
83
90
47
59
71
300 375
450 60
60
75
75
90
90
ns
51
64
76
275
345
415 55
55
69
69
83
83
47
59
71
365 435 290 73
87
58
58
73
87
74
49
62
-
10
-
10
-
-
10
10
-
10
-
10
pF
ANALOG CHANNEL CHARACTERISTICS - Typical Values a\ T A = 25° C
TEST CONDITION
CHARACTERISTICS
Switch Frequency Response
at-3dB (Fig. 12)
Sine Wave Distortion
Feedthrough Noise:
E to Switch
S to Switch
Switch "OFF" Signal Feedthrough
(Fig. 13)
Switch Input Capacitance
Common Capacitance
NOTES: 1. Adlust mput level lor 0 dBm at output, I = 1 kHz.
2. V's is centered at V,,/2.
3. Adjust input lor 0 dBm. at V's
Vee
HC/HCT
UNITS
4.5
89
MHz
4.5
0.051
%
Fig.5
Notes 2 & 3
4.5
TBE
TBE
mV
Fig. 6
4.5
-75
dB
-
5
50
pF
Fig. 3
Notes 1 & 2
Fig. 4
Cs
-
CCOM
-
V
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 545
Technical Data_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD.54/74HC4067· .
CD54/74HCT4067
140
c::
I
Z
g
TA= 25"C
GND=O V
120
100
w
U
z
~
VCC=4.5 V
iii
w
a::
40
z
~
20
o
2
3
4
5
7
6
INPUT SIGNAL VOLTAGE (V'S) -
9
8
V
10
92CS-39910
Fig. 2 - Typical "ON" resistance versus input signal voltage.
VCC
VCC
VOS~
10pF
I
VCcJ2
.~'
SINE
WAVE
V,S--l
10"F
VCC/2
'is = 1 kHzTO 10kHz
92CS-39940
92CS-39939
Fig. 4 - Sine wave distortion test circuit.
Fig. 3 - Frequency response test circuit.
VCC
'IS ~ 1 MHz SINE WAVE
Vee
600n
--'''''''---1
SWITCH
ALTERNATING
ON AND OFF
V0J-,
-r;~
t r ,t,S-6ns
'CONT=1 MHz
50 % DUTY
CYCLE
R=50Q
e=10pF
~
-
VCC/2
Vee/2
f?
92CM-: 39840
92C8-39941
Fig. 5 - Control-to-switch feedthrough noise test circuit.
Vee/2
Fig. 6 - Switch off signal feedthrough test circuit.
6ns
Ir= 6
nSl r-
1£1'= 6
----
JI-----j
~------~~L-+--------------vcc
ns
-------90 %.
I~~-----------GNO
0----]:....------50 %
SWITCH INPUT
IpLH
SWITCH OUTPUT
---l \;
.
-------10.%
r
tpHL
1------~----50 %
92CS-39359
92C8--39914
Fig. 7 - Switch propagation-delay times wave forms.
Fig. 8 - Switch turn-on and turn-off propagation
delay times wareforms, for HC types.
546 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
___________________________________________________________ TechnicaIData
CD54/74HC4067
CD54/74HCT 4067
6ns
~~~-----------GND
92CS-39360
Fig. g - Switch turn-on and turn-off propagation
delay times waveforms for He T Types.
GND FOR tpLZ AND t PZL}
Vee FOR tpHZ AND tpZH
IN~OUT
RL= 1 kn
{
IN~OUT
Vee FOR tpLZ AND tpZL
-
~
1-____
~_-
GND FOR tpHZ AND tpZH
r
IeL~50 pF
-=-
92CS·39916RI
50PF
-=-
92C5-38835
Fig. 11 - Switch In to Switch Out Propagation
delay time test circuit.
Fig. 10 - Switch on/off propagation delay time test circuit.
0
o VCC= 4.S V
= son
'"I -10 RL
-1
."
-2
a
TA
=2S'C
-20
I
:;)
~
-3
'"
."
-4
l-
i
ew
-40
u.
-'
-so
~
-60
w
I
en -S
~
-30
:I:
l-
«
-6
,./
iii
u. -70
u.
0
± -BO
-7
-8
-9
-10
10s
V
0
I-
VCC=4.S V
RL = son
TA = 2S 'c
4 68
V
~ -90
en
-100
468
2468
107
106
FREQUENCY (I) -
Hz
Fig. 12 - Typical switch frequency response.
4 68
10B
4 68
tJN.~
10 S
4
68
4 68
106
FREQUENCY (I) -
107
Hz
4 68
2
loB
92CS-39912
Fig. 13 - Typical switch-off signal feed through vs. frequency.
_________________________________________________________________ 547
TechnicaIOata _____________________________________________________________
CD54/74HC4075
CD54/74HCT4075
File Number
1778
High-Speed CMOS Logic
Triple 3-lnput OR Gate
lC
Type Features:
• Buffered inputs
• Typical CD54174HC4075 Propagation Delay
@ Vee ~ 5V, C L ~ 15pF, TA ~ 25°C
2.
2C
• 3C
~
8ns
GND'" 7
Vee'" 14
FUNCTIONAL DIAGRAM
The RCA-CD54/74HC4075 and CD54!74HCT4075 logic
gates utilize silicon-gate CMOS technology to achieve
operating speeds similar to LSTTL gates with the low
power consumption of standard CMOS integrated circuits.
All devices have the ability to drive 10 LSTTL loads. The
CD54174HCT logic family is functionally as well as pin
compatible with the standard 54LS!74LS logic family.
The CD54HC4075 and CD54HCT4075 are supplied in 14lead hermetic dual-in-line ceramic packages (F suffix). The
CD74HC4075 and CD74HCT4075 are supplied in 14-lead
dual-in-line plastic packages (E suffix) and in 14-lead dualin-line surface-mount plastic packages (M suffix). Both
types are also available in chip form (H suffix).
Family Features:
• Fanout (over temperature range):
Standard Outputs - ·10 LSTTL loads
Bus driver outputs - 15 LS TTL loads
• Wide Operating temperature range:
CD74HC!HC T: -40 to +85° C
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL
logic ICs
• Alternate source is Philips!Signetics
• CD54HC!CD74HC Types:
2 to 6 V Operation
High noise immunity: N'L ~ 30%. N'H ~ 30% of Vee;
@ Vee ~ 5V
• CD54HCT!CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL input logic compatibility
V'L ~ 0.8 V max., V'H ~ 2 V Min.
CMOS input compatibility
I, S I/lA @ VOL, VOH
TRUTH TABLE
nA
nY
nB
nC
nA
nB
nC
L
L
L
nY
L
H
X
X
H
X
H
X
H
X
X
H
H
L ~ Low voltage Level
H 0 High voltage Level
X 0 Don't Care
LOGIC DIAGRAM
548 ___________________________________________________________________
___________________________________________________________ TechnicaIData
CD54/74HC4075
CD 54/74HCT4075
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ................................................................................... -0.5 to + 7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +0.5V) ...................................................... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Va < -0.5 V OR Va> Vee +0.5V) ................................................... ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Va < Vee + 0.5V) ................................................... ±25mA
DC Vee OR GROUND CURRENT (Icc) ................................................................................... ±50mA
POWER DISSIPATION PER PACKAGE (Po):
For TA ; -40 to +60' C (PACKAGE TYPE E) ............................................................................. 500 mW
For TA; +60 to +85°C (PACKAGE TYPE E) ................................................ Derate Linearly at 8 mW/'C to 300 mW
For TA ; -55 to +100' C (PACKAGE TYPE F, H) ......................................................................... 500 mW
For TA; +100 to +125'C (PACKAGE TYPE F, H) ........................................... Derate Linearly at 8 mW/'C to 300 mW
ForTA;-40to+70'C (PACKAGETYPEM) ............................................................................ 400mW
For TA; +70 to +125°C (PACKAGE TYPE M) ............................................... Derate Linearly at 6 mW/'C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .......................................................................................... -55 to +125' C
PACKAGE TYPE E, M ........................................................................................... -40 to +85'C
STORAGE TEMPERATURE (T",) .................................................................................. -65 to +150' C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ....................................................... +265' C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................................................................................... +300' C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA ; Full Package-Temperature Range) Vce:'
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage V" Vo
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t" tf
at2V
at4.5V
at6V
UNITS
MIN.
MAX.
2
4.5
a
6
5.5
Vcc
V
V
V
-40
-55
+85
+125
DC
a
a
a
1000
500
400
ns
'Unless otherwise specified, all voltages are referenced to Ground.
14
2A
28
1A
18
1C
1Y
GND
2
13
3
12
4
11
5
10
VCC
3C
38
3A
3Y
6
9
2Y
7
8
2C
TOP VIEW
92CS-39B13
TERMINAL ASSIGNMENT
________________________________________________________________ 549
TechnicaIOam ________________________________________________________
CD54/74HC4075
CD54/74HCT4075
STATIC ELECTRICAL CHARACTERISTICS
CD74HC4075/CD54HC4075
TEST
CONDITIONS
74HC/54HC
CD74HCT4075/CD54HCT4075
74HC
TYPE
54HC
TYPE
-401
+85°C
-551
+125°C
TYPES
TEST
CONDITIONS
74HCT/54HCT
TYPES
74HCT
TYPE
54HCT
TYPE
-401
+85°C
-55/
+l25°C
CHARACTERISTIC
UNITS
+25°C
Vo
V
I.
rnA
Vee
V
+25°C
Vo
V
Vee
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
V,"
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
VOH
or
-0.02
VOH
CMOS Loads
2
1.5
-
-
1.5
-
1.5
-
4.5
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
5.5
2
-
-
0.5
-
0.5
-
0.5
4.5
4.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
Low-Level
Output Voltage
CMOS Loads
2
1.9
-
-
1.9
-
1.9
-
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
VOH
Input Leakage
-
-
3.84
-
3.7
-
or
VOH
-5.2
6
5.48
-
-
5.34
-
5.2
-
VOH
2
-
-
0.1
-
0.1
-
0.1
V"
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V'H
4
4.5
-
-
0.26
-
0.33
-
0.4
or
V'H
5.2
6
-
-
0.26
-
0.33
-
0.4
V'H
6
-
-
±O.1
-
±1
-
±1
Any
Voltage
Between
Vee
& Grid
6
-
-
2
-
20
-
40
or
Gnd
Quiescent
Vee
Device
or
Current
Icc
2
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.4
-
-
4.4
-
4.4
-
V
4.5 3.98
-
-
3.84
-
3.7
-
V
to
4.5
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±O.1
-
±1
-
±1
pA
5.5
-
-
2
-
20
-
40
pA
-
100 360
-
450
-
490
pA
V"
or
Vee
I,
-
V"
3.98
V"
Current
-
V"
4.5
or
2
to
5.5
-4
V'H
TTL Loads
-
or
V"
Voe
4.5
-
4.5
V"
TTL Loads
Min Typ Max Min Max Min Max
Vee
0
Gnd
or
Gnd
Additional
Quiescent
Device Current
per input pin:
1 unit load
lIlce
4.5
Vcc-2.1
to
5.5
*For dual-supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specification is 1.8 mAo
HCT INPUT LOADING TABLE
INPUT
UNIT LOADS·
All
1.6
·Unit Load is lIlee limit specified in Static Characteristic
Chart, e.g., 360 pA max. @2So C.
550 ___________________________________________________________________
___________________________________________________________ TechnicaIData
CD54/74HC4075
CD54/74HCT4075
SWITCHING CHARACTERISTICS (Vee = 5 V, TA = 25°C, Inpul I" If = 6 ns)
TYPICAL
HC
HCT
CL
(pF)
CHARACTERISTIC
Propagation Delay, Data Input to Output Y (Fig. 1)
t pLH ,
Power Dissipation Capacitance'
UNITS
tpHL
15
8
9
ns
Cpo
-
26
28
pF
'C po is used to determine the dynamic power consumption, per gate.
Po = Vee 2 fi (Cpo + C L ) where: fi = input frequency
C L = load capacitance
Vee = supply voltage
SWITCHING CHARACTERISTICS (C L
CHARACTERISTIC
Propagation Delay,
Input to Output
(Fig.1)
Transition Times
(Fig.1)
Input
Capacitance
=50 pF, Inpul 1"lf =6 ns)
Vee
t pLH
t pHL
tTLH
hHL
2
4.5
6
2
4.5
6
C,
_40° C 10 +85° C
-55°C 10 +125°C
25°C
74HCT
54HC
54HCT
UNITS
HC
HCT
74HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
100 125
150
ns
20
24
25
30
30
36
17
21
26
110 75
95
15
15
19
19
22
22
ns
13
16
19
-
10
-
10
-
10
-
10
-
10
-
10
pF
INPUT
~VEL
92CS-39811
I Input Level
I Switching Voltage, Vs
54/74HC
I
Vee
50% Vee
I
54174HCT
3V
1.3 V
Fig. 1 - Transition times and propagation delay times.
551
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54n4HC4094"
File Number
1779
CD54n4HCT4094 '
High-Speed CMOS Logic
·,.
.~
~
· .,
~
o
..
••
tS
..
os
11
Q1
,
L -_ _- - '
~
~
a-Stage Shift-and-Store'
Bus Register - 3-State
Type Features:
• Buffered inputs
• Separate serial outpats synchronous to both positive and negative
clock edges for cascading.
~
GND=I
Vcc~I.
FUNCTIONAL DIAGRAM
The RCA-CD54174HC4094 and CD54174HCT4094 are 8stage serial shift registers having a storage latch associated
with each stage for strobing data from the serial input to
parallel buffered3-state outputs. The parallel outputs may
be connected directly to common bus lines. Data is shifted
on positive'clock transitions. The data in each shift register
stage is transferred to the storage register when the Strobe
input is high. Data in the storage register appears at the
outputs whenever the Output-Enable signal is high.
Two serial outputs are available for cascading a number of
these devices. Data is available at the aS1 serial output
terminal on positive clock edges to allow for high-speed
operation in cascaded systems in which the clock rise time
is fast. The same serial information, available at the aS2
terminal on the next negative clock edge, provides a means
for cascading these devices when the clock' rise time is
slow.
The CD54HC4094 and CD54HCT4094 are supplied in 16lead hermetic dual-in-line ceramic packages (F suffix). The
CD74HC4094 and CD74HCT4094 are supplied in 16-lead
dual-in-line plastic packages (E suffix) and in 16-lead dualin-line surface-mount plastiC packages (M suffix). Both
types are also available in chip form (H suffix).
18
STROBE
DATA
cp
QO
01
Q2
03
GND
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10LSTTLLoads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating -Temperature Range:
CD74HC/HCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• CD54HC/CD74HG Types:
2 to 6 V Operation
High Noise Immunity: NoL = 30%, NoH = 30% of Vee.
@ Vee=5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic C9mpatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I" :5 1 pA @ VOL, VOH
2
15
3
14
4
13
5
12
8
11
7
10
8
8
Vcc
OE
04
os
Q8
07
Oil:!
081
92CS- 39843
TERMINAL ASSIGNMENT
552 _______________________________________________________________
Technical Data
CD 54/74HC4094
CD54/74HCT4094
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) .................................................................................. -0,5 to +7 V
DC INPUT DIODE CURRENT, I'K (FOR V, <-0.5 V OR V, > Vee + 0.5 V) .......................................•....•......• ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Va < -0.5 V OR Vo > Vee +0.5 V) .............................•.....•....•....... ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5 V) ................................................. ±25mA
DC Vee OR GROUND CURRENT (lee) .................................................................................... ±50mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60°C (PACKAGE TYPE E) ........................................................................... 500 mW
For T. = +60 to +85°C (PACKAGE TYPE E) ............................................. Derate Linearly at 8 mW/oC to 300 mW
For T. = -55 to +100°C (PACKAGE TYPE F, H) ....................................................................... 500 mW
For T. = +100 to +125°C (PACKAGE TYPE F, H) ......................................... Derate Linearly at 8 mW/oC to 300 mW
For T. = -40 to +70°C (PACKAGE TYPE M) ....................................................................•..... 400 mW
For T. = +70 to +125°C (PACKAGE TYPE M) ............................................. Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H .......................................................................................... -55 to +125°C
PACKAGE TYPE E, M .......................................................................................... -40 to +85°C
STORAGE TEMPERATURE (T...) ...................•...............•...........•................................. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ...................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ........... : ...................................................................... +300°C
92CL-39846
Fig. 1 - Logic diagram.
_________________________________________________________________ 553
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4094
CD54/74HCT4094
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
UNITS
MIN.
MAX.
Supply-Voltage Range (For TA = Full Package Temperature Range) Vee:*
CD54/74HC Types
CD54/74HCT Types
2
4.5
5.5
V
V
DC Input or Output Voltage V" Va
,0
Vee
V
Operating Temperature T A:
CD74 Types
CD54 Types
-40
-55
+85
+125
°C
a
a
a
1000
500
400
ns
Input Rise and Fall Times t" tf
at2 V
at4.5 V
at 6 V
6
'Unless otherwise specified, all voltages are referenced to .Ground.
FUNCTION TABLE
PARALLEL
OUTPUTS
INPUTS
SERIAL
OUTPUTS
CP
OE
STR
D
00
an
051'
052
~
L
L
H
H
H
H
X
X
L
H
H
H
X
X
X
L
H
H
Z
Z
Z
Z
NC
L
H
NC
NC
On-1
On-1
NC
0'6
NC
0'6
0'6
0'6
NC
NC
07
NC
NC
NC
07
~
~
~
~
~
H = HIGH voltage level
L = LOW voltage level
X = don't care
NC = No Change
Z = HIGH impedance OFF-state
J = LOW-to-HIGH CP transition
" - = HIGH-to-LOW CP transition
0'6 = the information in the seventh register stage
'At the positive clock edge the information in the 7th register stage is transferred to the 8th register
stage and OS1 output.
554 ___________________________________________
Technical Data
CD54/74HC4094
CD54/74HCT4094
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT4094/CD54HCT4094
CD74HC4094/CD54HC4094
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPE
TYPE
CONDITIONS
TYPES
TYPE
TYPE
-401
-551
-401
-551
+B5°C
+125°C
+B5°C
+125°C
CHARACTERISTIC
UNITS
V,
10
Vee
V
rnA
V
+25°C
V,
Vee
V
V
Min Typ Max Min Max Min Max
High-Level
Input Voltage
V,"
Low-Level
Input Voltage
V"
High-Level
V"
Output Voltage
or
Vo"
CMOS Loads
-0.02
V,"
2
1.5
-
-
1.5
-
1.5
-
4.5
3.15
-
-
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
Low-Level
Output Voltage
-4
V,"
-5.2
CMOS Loads
or
0.02
V,"
Input Leakage
I,
-
-
1.9
-
1.9
-
V"
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5 3.98
-
-
3.84
-
3.7
-
or
6
5.48
-
-
5.34
-
5.2
-
V,"
2
-
-
0.1
-
0.1
-
0.1
V"
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
4.5
-
-
0.26
-
0.33
-
0.4
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
Current
Ice
6
-
-
±0.1
-
±1
-
±1
6
-
-
8
-
80
-
160
1m
V
-
-
0.8
-
0.8
-
0.8
V
4.4
-
-
4.4
-
4.4
-
V
4.5 3.98
-
-
3.84
-
3.7
-
V
to
4.5
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
pA
5.5
-
-
8
-
80
-
160
pA
Vee -2.1
4.5
to
5.5
-
100 360
-
450
-
490
pA
V"
or
V,"
5.5
-
-
-
±5
-
±10
pA
or
V,"
Between
Vee
and
Gnd
or
Gnd
Gnd
V"
or
V,"
-
Vee
0
Additional
Quiescent
Device Current
per input pin:
1 unit load
ll.lcc
3-State
Leakage
Current
2
Any
Gnd
or
-
Voltage
or
Vee
2
V"
4
Device
-
5.5
1.9
or
Quiescent
-
4.5
-
4.4
Vee
Current
2
to
5.5
2
V"
TTL Loads
4.5
-
V"
or
V"
VOL
Min Typ Max Min Max Min Max
4.5
V"
TTL Loads
+25°C
Voc;::::.Vcc
or
Gnd
6
-
-
±0.5
• For dual-supply systems theoretical worst case (V,
-
±5
-
±10
±0.5
= 2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
Unit Loads'
D
0.40
1.50
1.0
CP,OE
STR
'Unit load is ll.lcc limit specified in Static Characteristics
Chart, e.g., 360/lA max. @ 25°C.
555
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4094
CD54/74HCT4094
SWITCHING CHARACTERISTICS (Vee=5 V, T A =25°C, Input I" t,=6 ns)
TYPICAL
CL
CHARACTERISTIC
SYMBOL
(pF)
Propagation Delay
CPto Qn
IPLH
IPHL
15
HC
HCT
16
18
CPlo QS1
12
16
CPlo QS2
11
15
14
14
10
14
tPZH
Output Enabling Time
t pzL
IpHz
Output Disabling Time
t pLZ
Max. CP Frequency
f MAX
Power Dissipation Capacitance'
Cpo
-
UNITS
ns
60
60
MHz
90
110
pF
'CPD is used to determine the dynamic power consumption, per register.
PD=CPD Vee' fi + L (C L Vee' fo) where:
fi=input frequency
C L =output load capacitance
fo=output frequency
Vee=supply voltage
SWITCHING CHARACTERISTICS (CL = 50 pF, Inpul I" I, = 6 ns)
25°C
CHARACTERISTIC
HC
Vce
-40°C 10 +85°C
HCT
74HC
-55°C to +125°C
74HCT
54HC
54HCT
UNITS
Min, Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Propagation Delay
-
CP 10 QS1
2
4.5
6
-
CPlo QS2
2
4.5
6
-
CPlo Qn
2
4.5
6
STR to Qn
2
4.5
6
-
180
36
31
2
4.5
6
-
175
35
30
2
4.5
6
-
-
125
25
21
2
4.5
6
-
75
15
13
tPLH
t PHL
Outpul Enable
to Qn
Output Disable
to Qn
Output Transition
Time
tpzH
IpzL
t pHz
t pLZ
hHL
hLH
-
-
-
-
-
150
30
26
135
27
23
195
39
33
-
-
-
-
39
-
-
-
-
190
38
33
-
36
-
-
-
170
34
29
-
-
-
43
-
-
-
-
245
49
42
-
-
-
-
-
225
45
38
-
-
-
-
49
-
-
-
-
-
270
54
46
-
-
-
-
35
44
-
220
44
37
-
-
-
-
-
-
265
53
45
-
155
31
26
-
-
-
-
44
-
190
38
32
95
19
16
-
-
-
-
19
-
-
-
-
-
39
-
-
-
35
-
-
-
15
-
-
-
49
-
-
-
225
45
38
-
-
205
41
35
-
-
54
-
295
59
50
-
45
-
-
-
-
-
-
59
-
-
-
-
-
54
-
-
-
65
ns
ns
-
-
-
-
59
-
-
-
53
ns
ns
ns
-
-
-
-
53
110
22
19
-
-
-
-
ns
22
ns
Input Capacilance
C,
-
10
-
10
-
10
-
10
-
10
-
10
pF
3-Slate Output
Capacitance
Co
-
15
-
15
-
15
-
15
-
15
-
15
pF
556 ___________________________________________________________
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4094
CD54/74HCT4094
t
6nsl
:1
~6ns
INPUT LEVEL
r--------.~-___ -90%
¥
---Vs
CLOCK-----'
---10%
tw---t----
tH~
rrtsu
INPUT LEVEL
~--~------------+--J----4_----GND
SERIALIN
,--------r------------"-----r---VOH
Vs
On,OSl-------'
'-----r---VOL
j--
tpLH
j-- tPHL
)t;S--------------------~~VOH
~VOL
OS2-----------------------J,
92CS-39845
Fig, 3 - Data propagation delays, setup and hold times,
=x >e
INPUT LEVEL
t,= 6ns
SERIAL IN
,------~
j--tSU
Ir
CLOCK
Vs
tH
r---
GND
Vs
--GND
On
tpLH, tpHL
L
VOL
~~VOH
1
r
-------t---X
1 r--
tf =6ns
-------
IrlNPUT LEVEL
~VOH
STROBE
OE
OUTPUT
LOW TO O;.;F-,F+_ _,
I'
,.Tv
I
S
OUTPUTS --lOUTPUTS
-l-- OUTPUTS
CONNECTED
DISCONNECTED
CONNECTED
OUTPUT
HIGH TO OFF
~VOL
K-90%
92CS-398!56
92 CS- 39857
Fig, 5 - Enable and Disable Times,
Fig, 4 - Strobe propagation delays, and setup and hold times,
54174HC
Input Level
Switching Voltage, Vs
90 %
---Vs
-----10%
54/74HCT
Vee
3V
50% Vee
1,3 V
558 _________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
File Number
CD54/74HC4510, CD54/74HCT4510
CD54/74HC4516, CD54/74HCT4516
1823
High-Speed CMOS Logic
PRESET
ENABLE
PO
00
PI
0'
P2
"
CLOCK
UP/OOWN
CARRY IN
03
15
'0
7
~
Vee: 16
MASTER
RESET
GNDs·8
FUNCTIONAL DIAGRAM
Presettable Synchronous 4-Bit
Up/Down Counters
CD54/74HC/HCT4510 BCD Decade Counter,
Asynchronous Reset
CD54/74HC/HCT4516 4-Bit Binary Counter,
Asynchronous Reset
Type Features:
• Synchronous counting and asynchronous loading
• Look-ahead carry for high-speed counting
The RCA CD54/74HC/HCT451 0 presettable BCD up/down
counter and the CD54174HC/HCT4516 presettable binary
up/down counter consist of four synchronously clocked
D-type flip-flops (with a gating structure to provide T-type
flip-flop capability) connected as counters. These counters
can be cleared by a high level on the Master Reset line, and
can be preset to any binary number present on the preset
inputs by a high level on the Preset Enable line. The 4510
will count out of non-BCD counter states in a maximum of
two clocl< pulses in the up mode, and a maximum of four
clock pulses in the down mode.
If the Carry-I n input is held low, the counter advances up or
down on each pOSitive-going clock transition. Synchronous
cascading is accomplished by connecting all clock inputs
in parallel and connecting the Carry-Out of a less significant
stage to the Carry-In of a more significant stage.
The 4510 and 4516 can be cascaded in the ripple mode by
connecting the Carry-Out to the clock of the next stage. If
the Up/Down input changes during a terminal count, the
Carry-Out must be gated with the clock, and the Up/Down
input must change while the clock is high. This method
provides a clean clock signal to the subsequent counting
stage. (See Fig. 5.)
The CD54HC/HCT4510 and the CD54HC/HCT4516 are
supplilld in 16-lead ceramic dual-in-line frit-seal packages
(F suffix). The CD74HC/HCT4510 and the CD74HC/HCT4516 are supplied in 16-lead dual-in-line plastic packages
(E suffix) and in 16-lead dual-in-line surface-mount plastic
packages (M suffix). Both types are also available in chip
form (H suffix).
Family Features:
• Fanout (over temperature range):
Standard outputs - 10 LSTTL loads
Bus driver outputs - 15 LSTTL loads
• Wide operating temperature range:
CD74HCIHCT: -40 to +85°C
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL
logic ICs
• Alternate source is PhilipslSignetics
• CD54HCICD74HC types:
2 to 6 V operation
High noise immunity:
N,L=30%, N'H=30% of Vee; @ Vee=5 V
• CD54HCTICD74HCT types:
4.5 to 5.5 V operation
Direct LSTTL input logic compatibility
V'L=0.8 V max., V'H=2 V min.
CMOS input compatibility
kS1 fJA @ VOL, VOH
PRESET
ENABLE
03
P3
PO
4
t6
vee
15
CLOCK
'4
a2
13
P2
CARRY IN
12
P'
aD
11
cit
'0
UPI DOWN
MASTER
CARRY OUT
GNO
RESET
TOP VIEW
TERMINAL ASSIGNMENT
________________________________________________________________ 559
Technical Data
CD54/74HC4510, CD54/74HCT4510
CD54/74HC4516, CD54/74HCT4516
PE
PE:u'f
CL
CL
Q
Q1
0
01
CL
liZ
PE
pE" a
CL
CL
OUT
1l
'1ll
a
03
02
T R
T R
R
R
U/D
00
_5
CI
:>O----R
PE
CL
92CL-40076
Fig. 1 ··Logic diagram for HCIHCT4510.
TRUTH TABLE
CL
CI
UfO
PE
MR
ACTION
X
H
X
L
L
NO COUNT
..r
L
H
L
L
COUNT UP
J
L
L
L
L
COUNT DOWN
X
X
X
H
L
PRESET
X
X
X
X
H
RESET
X = Don't Care
H = High Voltage Level
L = Low Voltage Level
560 __________________________________________
~-----------------------
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4510, CD54/74HCT4510
CD54/74HC4516, CD54/74HCT4516
PE
00
Cl
PE
P
a
OUT
CL
00
Q
Q2
0
02
T R
UfO
PE
PE
CL
CL
P
a
OUT
Ci
0
Q3
03
T R
U/D
Fig. 2 - Logic diagram for HCIHCT4516.
ClI
T
PE--{>-rl>- :
v
CL
CL2
~PE
CL2
Fig. 3 - Logic diagram of flip-flops for HCIHCT451014516.
561
Technical Data
CD54/74HC4510, CD54/74HCT4510
CD54/74HC4516, CD54/74HCT4516
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ...................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, I,. (FOR V, < -0.5 V OR V, > Vee +0.5 V) ....................................................... ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ................................................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (I,) (FOR -0.5 V < V, < Vee +0.5 V) ..................................................... ±25 mA
DC Vee OR GROUND CURRENT (Icc) ............................................. , ........................................ ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
ForT. = -40 to +60'C (PACKAGE TYPE E) ............................................................................... 500 mW
ForT. = +60 to +85'C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/'C to 300 mW
For T. = -55 to +100' C (PACKAGE TYPE F,H) ....... , .. , .................. , .............................................. 500 mW
ForT. = +100 to +125'C (PACKAGE TYPE F,H) .............................................. Derate Linearly at 8 mW/'C to 300 mW
ForT. = -40 to +70'C (PACKAGE TYPE M) .............................................................................. 400 mW
ForT. = +70 to +125'C (PACKAGE TYPE M) ................................................. Derate Linearly at 6 mW/'C to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F,H ............................................................................................. -55 to +125'C
PACKAGE TYPE E,M .............................................................................................. -40 to +85' C
STORAGE TEMPERATURE (T ..,) .................................................................................... -65 to +150'C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
. .................................................... +265'C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................................................................................... +300'C
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation Is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For T.=Full Package Temperature Range)
Vee:'
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage, V" Vo
Operating Temperature, T.:
CD74 Types
CD54 Types
Input Rise and Fall Times, t"t,:
at 2 V
at 4.5 V
at 6 V
LIMITS
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vcc
-40
-55
+85
+125
'C
0
0
0
1000
500
400
ns
V
V
'Unless otherwise specified, all voltages are referenced to Ground.
562 ____________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4510, CD54/74HCT4510
CD54/74HC4516, CD54/74HCT4516
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT4510/4516/CD54HCT4510/4516
CD74HC4510/4518/CD54HC4510/4516
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+B5'C
+125'C
+85°C
+125'C
UNITS
CHARACTERISTIC
+25°C
V,
10
Vee
V
mA
V
High-Level
Input Voltage
Low-Level
Input Voltage
V"
High-Level
Output Voltage
VOH
V"
or
-0.02
Min Typ Ma. Min Ma. Min Ma.
1.5
-
-
1.5
-
1.5
4.5 3.15
-
-
3.15
-
3.15
-
-
4.2
-
4.2
-
2
V'H
6
4.2
-
V
-
0.5
-
0.5
-
0.5
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
-
1.9
-
1.9
-
4.4
4.4
-
V"
or
5.9
-
5.9
-
V,"
3.7
-
V"
or
5.2
-
V'H
V"
2
1.9
-
4.4
-
6
5.9
-
V"
or
-4
V,"
-5.2
6
5.48
V"
or
2
0.02
4.5
-
3.84
-
5.34
-
-
-
0.1
-
0.1
-
0.1
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
V,"
TTL Loads
V"
or
4
4.5
-
-
0.26
-
0.33
-
0.4
V"
or
V'H
5.2
6
-
-
0.26
-
0.33
-
0.4
V'H
6
-
-
±0.1
-
±1
-
±1
Current
or
Gnd
Quiescent
Device Current
or
-
2
-
V
to
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
3.7
-
V
4.5 3.98
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
Voltage
Between
5.5
-
-
±0.1
-
±1
-
±1
pA
5.5
-
-
8
-
80
-
160
pA
-
100 360
-
450
-
490
pA
Vee
0
6
-
-
8
Gnd
-
80
-
160
or
Gnd
Additional
4.5
Quiescent Device
Vee -2.1
Current per input
pin: 1 unit load
2
Vee & Gnd
Vee
Icc
-
Any
Vee
10
-
5.5
CMOS Loads
Input Leakage
2
4.5
-
-
4.5 3.98
to
5.5
-
4.5
Min Typ Ma. Min Ma. Min Ma.
4.5
-
-
TTL Loads
Voe
Vee
V
2
V,"
Low-Level
V,
4.5
CMOS Loads
Output Voltage
+25°C
to
5.5
6. Icc
*For dual-supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specification is 1.8 mA.
HCT Input Loading Table
Input
PO-P3
MR
UfD, PE, CT
CP
Unit Loads'
0.75
1.5
1
1.25
'Unit Load is t.lee limit specified in Static Characteristics
Chart, e.g., 360 J1A max. @ 25' C.
563
Technical Data ______________________________
CD54/74HC4510, CD54/74HCT4510
CD54/74HC4516, CD54/74HCT4516
SWITCHING CHARACTERISTICS (Vee=5 V. T A=25° C. Inpul 1,,1,=6 ns)
CHARACTERISTIC
Propagation Delay:
CP to an
CP to CO
PE to an
PE to CO
MR to an
MR to CO
CltoCO
Power Dissipation Capacitance
CL (pF)
tPLH, tpHL
tPlH, tPHL
tpLH. tPHL
tpLH. tPHL
t PHL
tPLH
.
tPLH. tPHL
Cpo
15
15
15
15
15
15
15
TYPICAL VALUES
4516
4510
HCT
HCT
HC
HC
18
22
21
25
18
20
10
59
21
24
22
28
18
20
13
65
18
22
21
25
18
20
10
68
21
24
22
28
18
20
13
72
UNITS
ns
pF
'C po is used to determine the dynamic power consumption, per package.
Po = Cpo Vee2 fi + L (CL Vee 2 fo) where fi = input frequency
fo = output frequency
CL = output load capacitance
Vee = supply voltage.
PRE-REQUISITE FOR SWITCHING FUNCTION
CHARACTERISTIC
Pulse Width:
CP
tw
MR
tw
PE
tw
Setup Time,
Pn to PE,
CT to CP
Hold Time,
Pn to PE
tsu
CI to CP
tH
UfO to CP
tH
Removal Time:
MR to CP
tH
tREM
Maximum Frequency
CP
fMAx
TEST
CONDITIONS
Vee (V)
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
LIMITS
-40° C 10 +85° C
74HCT
HCT
74HC
HC
Min, Max. Min. Max. Min. Max. Min. Max.
100 80
16
20
20
16
14
17
125 100 20
25
25
20
17
21
100 80
16
16
20
20
17
14
100 125 25
25
20
20
21
17
3
3
3
3
3
3
3
3
5
5
5
5
5
5
5
5
0
0
0
0
0
0
0
0
100 80
20
20
16
16
17
14
5
6
24
24
30
30
28
35
25°C
_55° C 10 +125° C
54HC
54HCT
UNITS
Min. Max. Min. Max.
120 24
24
20
150 30
30
26
120 24
24
20
150 30
30
ns
26
3
3
3
3
5
5
5
5
0
0
0
0
120 24
24
20
4
MHz
20
20
24
-
564 _____________________________________________________
- - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4510, CD54/74HCT4510
CD54/74HC4516, CD54/74HCT4516
SWITCHING CHARACTERISTICS (Cl=50 pF, Input 1,,1,=6 n8)
LIMITS
-40° C 10 +85° C
-55° C to +125° C
74HCT
54HCT
UNITS
HCT
74HC
54HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
275
330 63
50
55
66
75
47
56
390 325 58
65
73
78
87
66
55
315 375 53
63
66
75
80
54
64
450 375 85
90
102
68
75
76
64
ns
315 265 42
53
63
63
53
54
45
355 295 71
71
47
59
59
50
60
190 155 47
31
31
39
38
32
26
95
- 110 19
22
22
15
19
19
16
10
10
pF
10
10
10
-
25°C
VCC
(V)
CHARACTERISTIC
Propagation Delay:
CP to an
tPlH
tPHL
CP to CO
tPlH
tPHl
PE to an
tPlH
tPHl
-
tpLH
PE to CO
tPHl
MR to an
t pHL
MR to CO
t pLH
-
-
CI toCO
Transition Time:
an, CO
I nput Capacitance
tPLH
tpHl
trHL
hlH
C,
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
HC
Min. Max.
220
44
37
260
52
44
250
50
43
300
60
51
210
42
36
235
47
40
125
25
21
75
15
13
10
-
- - - - - - - - - - - - - - - - - - - -____________________ 565
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4510, CD54/74HCT4510
CD54/74HC4516, CD54/74HCT4516
CP
92CM - 40080
(a) Clock to output delays and clock pulse width.
r------"\ P n --'.
(b) Clock to carry out delays.
INPUT LEVEL
~--'"'t-- INPUT LEVEL
,,,--
tw
MR
IW
PE
INPUT LEVEL
CP
Q n _ _ _-J
-------'I
(c) Preset Enable pulse width and Preset Enable to output delays.
(d) Master reset pulse width, master reset to output
delay and master reset to clock removal time.
92CM-40081
(e) Setup and hold times data to Preset Enable (PE).
/
/1 nput Level
I Switching Voltage, Vs
54/74HC
Vee
50% Vee
54/74HCT
3V
1.3 V
Fig. 4 - AC waveforms.
566 _______________________________________________________________
- - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4510, CD54/74HCT4510
CD54/74HC4516, CD54/74HCT4516
CLOCK
CARRY
L rL [L L rL
iN
r-t- IL fL fL Il.. L fL fl- L
iL L iL Il.. iL IL IL IL
Ir-h
UP/DOWN
r-
l - t-
r-
MASTER RESET
PE
h
h
t-
PO
,
r- - I r- -r-
2
3
ao
a,
a2
a3
I--
f-
I - '--
f-
~ '-- '-L--
lI-
I--
~ l -I -
I--
rl- ItlII - ~ L-f- ~
f--
r-
-
u
o
,
2
3
4
5
6
7
81
9
8
7
6
4
5
3
2
;-
~ -~
rf-
CARRY OUT
COUNT
f-
, a ,'-a
-'-~
f- ; - -
9
6
7
a
Fig. 5 - Timing diagram for CD54/74HC/HCT4510.
CLOCK
CARRY
iN
ILIL tL tL IL iL IL- tL tL tL tL ILILILILIL IL tL tL tL fL /L IL·
l.r JL- r--
UP/DOWN
M ASTER RESET
PE
h
h
PO
Vee
P'
GNO
P2
P3
ao f--
a'
a2
f-f-f-f-f-- l Ilf-f-lf-f-f-lf-f-f-r-r-r-- t-f-- f-r-- +f-- r-f-- +r-- r-lf-f-- f-l - f-l - t-l - t--
CARRY OUT
COUNT
r-r--
l - t--
a3
jr
t-5
6
7
8
9
10
II
12
13
14
15
9
8
7
6
5
4
3
2
I
0
r- l - r o
0
15 I
!
92CM-4QI09
Fig. 6 - Timing diagram for CD54/74HC/HCT4516.
--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 567
Technical Data
'CD54/74HC4510, CD54n4HCT4510
CD54/74HC4516, CD54n4HCT4516
UP/OOWN
>-----~~--------------------~--------------------_.----------------~
PRESETENABLE>-------+--1~------------------~~~------------------~~~------------_.
U/D
CI
45tO/t6
C.O.
p.----..o CI
PE PO Pt P2 P3
45tO/t6
C.O.P.----.qCI
45tO/t6
c.o.
*
MR
~LOCK>-----~--~------------------f_~~----------------_+--~------------~
MASTER RESET>-------'-----------------------~----------------------~----------------_.
* CARAY OUT LINES AT THE 2ND, 3RC, ETC., STAGES MAY HAVE A NEGATIVE-GOING
GLITCH PULSE RESULliNG FROM DIFFERENTIAL DELAYS OF DIFFERENT 4510/161C'5.
THESE NEGATIVE-GOING GLITCHES DO NOT AFFECT PROPER 4510/16 OPERATION.
HOWEVER, IF THE CARAY OUT SIGNALS ARE USEe TO'TRIGGER OTHER EDGESENSITIVE LOGIC DEVICES, SUCH AS FF'S OR COUNTERS, THE CARRY OUT SIGNALS
SHOULD BE GATED WITH THE CLOCK SIGNAL USING A 2-INPUT OR GATE SUCH AS
HC/HCT02.
(a) Parallel clocking.
UP/DOWN
PRESET
>-----~~--------------------~--------------------_.----------------~
ENABLE>-------+--1~------------------1_~~--------------~--1_~~------------~
U/D
U/D
CI
R
>--------11-....-------------1
RESET>-----~~~::::::::::::::::::::1:::::::::::::::~~----!_----------------~
C~OCK
MASTER
RIPPLE CLOCKING MODE:
THE UP/DOWN CONTROL CAN BE CHANGED AT ANY COUNT. TiiE ONLY RESTRICTION ON
CHANGING THE UP/DOWN CONTROL IS THAT THE CLOCK INPUTTO THE FIRST COUNTING
STAGE MUST BE "HIGH".
FOR CASCADING COUNTERS OPERATING IN A FIXED UP-COUNT OR DOWN-COUNT
IS CONNECTED
MODE, THE OR GATES ARE NOT REQUIRED BETWEEN STAGES.-AND
DIRECTLY TO THE CL INPUT OFTHE NEXT STAGE WITH CiGROUNDED.
co
(b) Ripple clocking.
Fig. 7 - Cascading counter packages.
COUNT UP
NOTE: ILLEGAL STATES IN BCD COUNTERS
'CORRECTED IN ONE COUNT.
COUNT DOWN
NOTE: ILLEGAL STATES IN BCD COUNTERS
CORRECTED IN ONE OR TWO COUNTS.
92cM-40491
Fig. 8 - HCIHCT4510 State Diagrams.
568 __________________________________________________________________
_
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4511
CD54/74HCT4511
File Number 1786
High-Speed CMOS Logic
BCO
BCD-to-7 Segment Latch/
Decoder/Drivers
INPUTS
I
{ ~~ ~
o
o
6
ct
5
OISPLAY
'b
o
o
~
2
E
o
R
4
iii
VSS·B
VOO"16
92CS-39896
FUNCTIONAL DIAGRAM
234
These devices have standard-size output transistors but are
capable of sourcing (at standard VO H levels) up to 7.5 mA at
4.5 V. The HC types can supply up to 10 mA at 6 V.
The CD54HC/HCT4511 are supplied in 16-lead ceramic
'dual-in-line packages (F suffix). The CD74HC/HCT4511
are supplied in 16-lead dual-in-line plastic packages (E
suffix) and in 16-lead dual-in-line surface-mount plastic
packages (M suffix). Both types are also available in chip
form (H suffix).
TRUTH TABLE
X
X
X
LT D3 D2 D1 DO abc d e Ig Display
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
x =Don't Care.
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
,L
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X,
X
X
X
6
7
9
,
d
92CS-2~087
Type Features:
• High-output sourcing capability-7.5 mA @ 4.5 V,
10 mA @6 V (HC4511)
• Input latches for BCD code storage
• Lamp test and blanking capability
The RCA CD54/74HC4511 and CD54174HCT4511 are
BCD-to-7segment latch/decoder/drivers having four
address inputs (Do-D3). active "Low" blanking and lamp test
inputs, and a latch 'enable input which, when "High",
enables the latches to store the BCD inputs. When Latch
Enable is "Low", the latches are disabled, making the
outputs transparent to the BCD inputs.
LE BI
.
ial/iC'i3il.fislb111Bl'l1 .8
o
E
C
Family Features:
• Fanout (over temperature range):
Standard outputs - 10 LSTTL loads
Bus driver outputs - 15' LSTTL loads
• Wide operating temperature range:
CD74HC/HCT: -40 to +B5°C
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL
logic ICs
• Alternate source is Philips/Signetics
• CD54HC/CD74HC types:
2 to 6 V operation
High nOise immunity:
ML=30%, MH=30% of Vee: @ Vee=5 V
• CD54HCT/CD74HCT types:
4.5 to 5.5 V operation
Direct LSTTL input logic compatibility
VIL =O.B V max., VIH =2 V min.
CMOS input compatibility
161 pA @ VOL, V OH
8
X H H H H H H H
X L L L L L L L Blank
L H H H H H H L
0
1
L H H L L L L
2
H H L H H L H
H H H H L L H
3
LHHLLHH
4
H L H H L H H
5
L L H H H H H
6
7
H H H L L L L
H H H H H H H
8
H H H L L H H
9
L L L L L' L L Blank
L L L L L L L Blank
L L L L L L L Blank
L L L L L L L Blank
L L L L L L L Blank
L L L L L L L Blank
*Depends on BCD code previously appied when LE = L.
Note: Display is blank for all illegal input codes (BCD> HLLH).
BCD
INPUTS
I
D1
D2
Ii'
BCD
INPU
~
I.
Vee
U
}-....~
ii
,.
LE
I.
D3
"
DO
I.
10
b OUTPUTS
c
.
d
92CS-59897
TERMINAL ASSIGNMENT
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 569
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD 54/74H C45t1
CD54/74HCT4511
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ..•...•..•.•...•......••........•.........••...••...•..•.•••..•••....••.•••.•.•..•.... -0.5 to +7 V
DC INPUT DIODE CURRENT, hK (FOR V, < -0.5 V OR V, > Vee +0.5 V) ...••..•••••.••••.••..••••...••....•••••..•••.••..•.••. ±20 rnA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) ...•..••..•••.•..•.••..•.••....••••••.•••.••..•.••. ±20 rnA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) ..•••..•..•..••..•••..•..•.•••.•.•...••...•...•...... ±25 rnA
DC Vee OR GROUND CURRENT (Icc) •.•.....•.•••...••.......•....••..• , .............••...••...••.....•..•....•..• , ..•.... ±50 rnA
POWER DISSIPATION PER PACKAGE (Po):
ForTA = -40 to +60°C (PACKAGE TYPE E) •.....••....•...••••....•..••....•.•..••........•..........•.•••...••.••..•.••. 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) .••...•...•..•....•....••.•......•.•..••..•....••. Derate Linearly at B mW/oC to 300 mW
For TA = -55 to +100°C (PACKAGE TYPE F,H) ....•.......................................•.............•..•...•.•••.••••• 500 mW
For TA = +100 to +125° C (PACKAGE TYPE F,H) .......•........•...•....•.....•...•.•..••..•• Derate Linearly at B mW/o C to 300 mW
ForTA = -40 to +70°C (PACKAGE TYPE M) ...•••.....••....•••..••..••......•..••..••...••...•••.•.......•...•..••...•.• 400 mW
For TA = +70 to +125° C (PACKAGE TYPE M) •...•....•......•..............•.....•.......•.•. Derate Linearly at 6 mW/o C to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F,H ••.....•............................................•........•...•...................•..•••.• -55 to +125° C
PACKAGE TYPE E,M •..•.......•..............•...•.•..•................••..........•...•.......•......••...•.•... -40 to +B5°C
STORAGE TEMPERATURE (Tot.) .................•....••......••.................................................... -65 to +150 0 C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
. ..•..•.....................•....•......•...••.••.••.• +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ..•...•..••..•.••.......•..•.....•..••..•.•.••..••...•.•..•••.......••...•...•..•.• +300°C
6
ii
Q
LATCH
LE
a
LE
Ii
ii
Q
a
LATCH
LE
LE
IE
IE Ii
"Ii
Q
LATCH
7
LE
LE
LE
U:
~
ii
Q
92CL-3989.
Fig. 1 - Logic diagram.
570 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
_____________________________________________________________TechnicaIData
CD54/74HC4511
CD54/74HCT4511
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT4511/CD54HCT4511
CD74HC4511/CD54HC4511
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85°C
+125 c C
+85°C
+125°C
UNITS
CHARACTERISTIC
+25°C
V,
10
Vee
V
mA
V
High-Level
I nput Voltage
V,"
Low-Level
I nput Voltage
V"
High-Level
Output Voltage
V"
Va"
or
-0.02
+25°C
Min Typ Max Min Max Min Max
2
1.5
-
-
1.5
-
3.15
-
-
1.5
4.5
3.15
-
3.15
-
6
4.2
-
-
4.2
-
4.2
-
V,
Vee
V
V
4.5
-
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
2
1.9
1.9
-
1.9
-
4.4
-
-
4.5
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
-
-
3.84
-
3.7
-
or
-
5.34
-
5.2
-
V,"
V"
V"
or
-7.5
4.5
3.98
V,"
-10
6
5.48
2
-
-
0.1
-
0.1
-
0.1
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
CMOS Loads
V,"
V"
or
4
4.5
-
-
0.26
-
0.33
-
0.4
or
Standard Output
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
I nput Leakage
I,
or
Device Current
6
-
-
±0.1
-
±1
-
±1
or
V
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.84
-
3.7
-
V
to
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
Voltage
Between
5.5
-
-
±0.1
-
±1
-
±1
fJA
5.5
-
-
8
-
80
-
160
fJA
360
-
450
-
490
fJA
Vee & Gnd
Vee
Icc
-
Any
Vee
Gnd
Quiescent
2
V"
TTL Loads
Current
-
V"
V"
or
2
V"
Non-Standard
Va'
-
5.5
TTL Loads
Output Voltage
-
4.5
-
V,"
Low-Level
2
to
5.5
CMOS Loads
Output
Min Typ Max Min Max Min Max
Vee
0
6
-
-
8
-
80
-
160
Gnd
or
Gnd
Additional
4.5
Quiescent Device
Vee -2.1
Current per input
pin: 1 unit load
to
-
100
5.5
.6lcc·
"For dual-supply systems theoretical worst case (Vl = 2.4 V, Vee
=5.5 V) specification
is1.8 mA.
HCT Input Loading Table
InDut
LT,LE
BT. Dn
Unit Loads'
1.5
0.3
·Unit Load is ll.lcc limit specified in Static Characteristics
Chart, e.g., 360 IlA max. @ 25° C.
571
TechnicaIData _____________________________________________________________
CD54/74HC4511
CD54/74HCT4511
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
Supply-Voltage Range (For TA-Full Package Temperature Range)
Vee:'
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage, V" Vo
Operating Temperature, TA:
CD74 Types
CD54 Types
Input Rise and Fall Times, t"t,:
at 2V
at 4.5 V
at 6 V
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
V
V
'Unless otherwise specified, all voltages are referenced to Ground.
SWITCHING CHARACTERISTICS (Vee=5 V, TA=25° C, Input t"I,=6 ns)
CL (pF)
CHARACTERISTIC
Propagation Delay:
On to Output
tPLH
15
25
25
15
23
23
15
18
18
15
13
13
114
110
UNITS
tPHL
tPLH
LE to Output
-BI
TYPICAL VALUES
HC
HCT
tPHL
tPLH
to Output
ns
tPHL
tPLH
--
LTto Output
Power Dissipation Capacitance'
tPHL
Cpo
-
pF
'Cpo is used to determine the dynamic power consumption, per package.
Po = Cpo Vee 2 fi + L CL Vee 2 fo where fi = input frequency
fo = output frequency
CL = output load capacitance
Vee = supply voltage.
PRE-REQUISITE FOR SWITCHING FUNCTION
CHARACTERISTIC
Setup Time,
On to LE
tsu
Hold Time,
On toTE
tH
Latch Enable
Pulse Width,
tw
TEST
CONDITIONS
Vee (V)
2
4.5
6
2
4.5
6
2
4.5
6
LIMITS
-40° C 10 +85° C
-55° C 10 +125° C
74HCT
54HCT
UNITS
HC
HCT
74HC
54HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
120 100 80
24
24
16
16
20
20
20
14
17
ns
3
3
3
5
3
5
3
5
3
3
3
3
120 80
100 20
20
24
24
MHz
16
16
20
14
17
25°C
572 ___________________________________________________________________
_____________________________________________________ TechnicaIData
CD54/74HC4511
CD54/74HCT4511
SWITCHING CHARACTERISTICS (CL=50 pF, Inpul 1,,1,=6 ns)
LIMITS
_40° C 10 +85° C
-55° C 10 +125° C
54HC
54HCT
HCT
74HC
74HCT
UNITS
HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
25°C
CHARACTERISTIC
Propagation Delay,
Dn to Output
VCC
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
tPLH
tPHL
tPLH
LE to Output
tPHL
tPLH
-
BI to Output
tPHL
tpLH
--
LT to Output
tPHL
hHL
Transition Time
hLH
I n put Capacitance
-
-
-
-
-
C,
300
60
51
270
54
46
220
44
37
160
32
27
75
15
13
10
-
-
-
-
60
-
-
-
-
-
-
54
-
-
-
-
-
-
-
44
33
-
-
-
-
-
-
15
-
-
-
-
-
10
-
-
t:E
375
75
64
340
68
58
275
55
47
200
40
34
95
19
16
10
-
-
-
-
75
-
-
-
-
68
-
-
-
450
90
77
405
81
69
330
66
56
240
48
41
110
22
19
10
-
-
-
-
-
55
-
-
-
-
-
-
41
-
-
-
19
-
-
-
-
10
-
-
SEGMENT
OUTPUT
OUTPUT
-
-
-
-
-
81
-
-
-
-
-
66
-
-
-
-
50
-
-
-
-
-
22
-
-
-
10
ns
ns
ns
ns
ns
pF
~
tpLH
v~ -
I
- - --
-90%
----;
~~=.
(bl
Inpul (On, IT) to output propagatlon
delays and output transition limes
iii
90
---- -
'THL
tTHL
(Q
-
-
INPUT
PHL'
SEGMENT
-
Input (IE) to output propagation
delays and latch enable pulse width
INPU~\
...V_S_ _ _ __
--.j'.PHL
SEGMENT
OUTPUT
(dl
Note
'TLH
The shaded areas indicate when the input Is
permitted to change for predictable output
performance.
(e)
Input {Ol) to output propagation
delays.
Waveforms showing the data set-up and
hold times for On Input to LE input.
54/74HC
Input Level
Switching Voltage, Vs
Vee
50% Vee
54174HCT
3V
1.3 V
92CM-39899
Fig. 2 - AC waveforms.
___________________________________________________________________ 573
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54n4HC4514, CD54n4HCT4514
CD54n4HC4515, CD54n4HCT4515
File Number 1597
High-Speed CMOS Logic
"'CC~24
,
GNO-12
'0
.,
.,
AO
4
4 TO 16
DECODER
'2
4515
YO
VI
YO
Yf
YO
Y3
Yz
Y4
Y4
Y3
YO
n
Y.
Yo
4-to-16 Line Decoder/Demultiplexer
with Input Latches
"
" "" VB
,.
L7
20
L.E
4514
'4
,.
L>
L5
YO
VlO
YLL
Vl2
VI>
Y!4
YL5
E 23
'"ViOYTi
Vii
ill
Yi4
m
Type Features:
• Multifunction capability:
Binary to 1-of-16 decoder
1-to-16/ine demultiplexer
9ZCS-38n ...
FUNCTIONAL DIAGRAM
The RCA CD54174HC4514, 4515 and CD54174HCT4514,
4515 are high-speed silicon gate devices consisting of a
4-bit strolled latch and a 4-to-16 line decoder. The selected
2..utput is enabled by a lowon theenable input (El. A high on
E inhibits selection of a~ output. Demultiplexing is accomplished by using the E input as the data input and the
select inputs (AO-A3) as addresses. This Einput also serves
as a chip select when these devices are cascaded.
When Latch Enable (LE) is high the o~ut follows changes
in the inputs (see truth table). When LE is low the output is
isolated from changes in the input and remains at the level
(high forthe 4514,lowforthe4515) it had before the latches
were enabled. These devices, enhanced versions of the
equivalent CMOS types, can drive 10 LSTTL loads.
The CD54HC4514, 4515 and CD54HCT4514, 4515 are
supplied in 24-lead dual-in-line frit-seal ceramic packages
(F suffix). The CD74HC4514, 4515 and CD74HCT4514, are
supplied in 24-lead dual-in-line, narrow-body plastic packages (EN suffix), in 24-lead dual-in-line, wide-body plastic
packages (E suffix), and in 24-lead dual-in-line surfacemount plastic packages (M suffix). Both types are also
available in chip form (H suffix).
Family Features
• Fanout (over temperature range):
Standard outputs - 10 LSTTL loads
Bus driver outputs - 15 LSTTL loads
• Wide operating temperature range:
CD74HCIHCT: -40 to +85°C
• Balanced propagation delay and
transition times
• Significant power reduction compared to
LSTTL logic ICs
• Alternate source is PhilipslSignetics
• CD54HC/CD74HC types:
2 to 6 V operation
High noise immunity: ML = 30%, MH = 30%;
@ Vcc=5V
• CD54HCT/CD74HCT types:
4.5 to 5.5 V operation
Direct LSTTL input logic compatibility
V'L = 0.8 V max., V'H = 2 V min.
CMOS input compatibility
'1, ::; 1 IlA @ VOL, VOH
24 Vee
IE
23
AO
E
22
A1
V5
A3
21 A2
20
V10
19 '(11
V,
18 Y8
V7
V6
17 '(9
V3
16 Y14
V1
V2
VO
GNO
10
15 1(15
11
14 Y12
12
13 Y13
TERMINAL ASSIGNMENT
574 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
_____________________________________________________________ Technical Data
CD54/74HC4514, CD54/74HCT4514
CD54/74HC4515, CD54/74HCT4515
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE (Vee):
. ... -05to+7V
(Voltages referenced to ground) . . . . .. . .. . . .. .. .. .
. ......... .
±20mA
DC INPUT DIODE CURRENT, 11K (FOR V, < -0.5 V OR V, > Vee +0.5 V) .. .
± 20mA
DC OUTPUT CURRENT, 10K (FOR Va < -05 V OR Va> Vee +0.5 V) .
± 25 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Va < Vee +0.5 V) .
± 50 mA
DC Vee OR GROUND CURRENT, PER PIN (Icc)
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60°C (PACKAGE TYPE E) ...
.500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) ,..
Derate Linearly at 8 mW/oC to 300 mW
For TA = -55 to +100'C (PACKAGE TYPE F, H)
. '" . 500 mW
For TA = +100 to +125°C (PACKAGE TYPE F, H) .......... ,.,....
.. Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) .......................................
. ............................. 400 mW
For TA = +70 to +125°C (PACKAGE TYPE M) ...................
. ................. ,. Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TA):
. .. -55 to +125°C
PACKAGE TYPE F, HI.
. -40 to +85°C
PACKAGE TYPE E, M
-65 to +150°C
STORAGE TEMPERATURE (T",) ..
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max .....
. ...... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in .. 1.59 mm) with solder contacting lead tips only .....
. .... +3000C
~§;.\'CT
I
HClHCT
4515
YO
YO
YI
Vi
YZ
Yz
Y3
Y3
Y4
Y4
Y5
'is
Y6
Y6
Y7
Y7
YB Y8
Y9
Y9
YIO YIO
YII
Yii
YIZ
Yi2
YI3m
YI4 YI4
YI5 YI5
Fig. -
Logic diagram for CD54/74HC4514, 4515 and CD54/74HCT4514, 4515.
575
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4514, CD54/74HCT4514
CD54/74HC4515, CD54/74HCT4515
DECODE TRUTH TABLE (LE = 1)
DECODER
INPUTS
ENABLE
A3 A2 A1
ADDRESSED OUTPUT
4514 = Logic 1 (High)
AD
4515 = Logic 0 (Low)
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
1
1
a
1
1
1
1
a
a
a
1
1
1
1
1
1
1
1
a
a
a
a
a
a
1
1
a
1
1
1
1
a
a
a
1
1
a
1
X
X
X
X
x- DontCare
1
1
a
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
1
1
1
O.
1
a
YB
Y9
Y10
Y11
Y12
Y13
Y14
Y15
1
1
1
1
All Outputs = 0,4514
All Outputs = 1,4515
Lagle 1 = High
LogiC 0 = Low
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that .operation is always within
the following ranges:
LIMITS
UNITS
CHARACTERISTIC
MIN,
MAX.
Supply-Voltage Range (For T A = Full Package Temperature Range) Vee:'
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V" Va
2
6
V
4.5
5.5
V
0
Vee
V
Operating Temperature T A:
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
at 2V
0
1000
ns
at 4.5 V
0
500
ns
at 6V
0
400
ns
Input Rise and Fall Times, t" tf
'Unless otherwise specified, all voltages are referenced to Ground.
576 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Technical Data
CD54/74HC4514, CD54/74HCT4514
CD54/74HC4515, CD54/74HCT4515
STATIC ELECTRICAL CHARACTERISTICS
CD74HC4514/CD54HC4515
CD74HCT4514/CD54HCT4515
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
CHARACTERISTIC
UNITS
V,
10
Vee
V
mA
V
+25°C
V,
Vee
V
V
Min Typ Ma. Min Ma. Min Mu
High-Level
Input Voltage
1.5
-
-
1.5
-
1.5
-
4.5 3.15
-
-
3.15
-
3.15
-
4.2
-
4.2
-
4.2
-
0.5
-
0.5
1.35 -
1.35
1.35
2
V,"
Low-Level
Input Voltage
V"
High-Level
Output Voltage
V"
Vo"
CMOS Loads
or
-0.02
V,"
4.5
-
2
-
4.5
-
6
-
-
1.8
-
1.8
-
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5 3.98
-
-
3.84
-
3.7
6
5.48
-
-
5.34
-
5.2
-
Low-Level
V'H
2
-
-
0.1
-
0.1
-
0.1
Output Voltage
-4
V,"
-5.2
CMOS Loads
or
V"
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V'H
0.02
V'H
4.5
-
-
0.26
-
0.33
-
0.4
6
-
-
0.26
-
0.33
-
Input Leakage
0.4
V'H
Any
Voltage
Between
Vee
&
Gnd
Current
4
V,"
5.2
or
Vee
or
Current
lee
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
4.4
-
-
4.4
-
4.4
-
V
4.5 3.98
-
-
3.84
-
3.7
-
V
to
5.5
V"
or
or
6
-
-
±0.1
-
±1
-
±1
6
-
-
8
-
80
-
160
Gnd
Device
2
4.5
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
/JA
5.5
-
-
8
-
80
-
160
/JA
-
450
-
490
/JA
V"
or
Quiescent
-
1.8
Vee
I,
-
4.5
0.5
V"
TTL Loads
-
V"
or
V"
Vo,
2
to
5.5
V"
TTL Loads
Min Typ Max Min Max Min Max
-
6
+25°C
V"
0
or
Gnd
Gnd
Additional
Quiescent
Device Current
per input pin:
4.5
Vee -2.1
to
5.5
-
100 360
1 unit load .6.lcc·
-For dual-supply systems theoretical worst case (V,
= 2.4 V,
Vee
=5.5 V) specification
is 1.8 rnA.
HCT Input Loading Table
Input
Unit Loads·
AO-A3
LE
0.15
0.85
0.3
E
'Unit load is .o.lcc limit specified in Static Characteristic
Chart, e.g., 360 /lA max. @ 25°C.
____________________________________________________________________
577
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4514, CD54/74HCT4514
CD54/74HC4515, CD54/74HCT4515
SWITCHING CHARACTERISTICS (Vee = 5 V, T A 25°C, Inpul I" If = 6 ns)
Propagation Delay
Select to Output
Typical Values
Cl
SYMBOL
CHARACTERISTIC
UNITS
(pF)
HC
HCT
15
23
25
ns
15
19
21
ns
15
14
17
ns
-
70
75
pF
tPHl
tPlH
tpHl
LE to Output
tPLH
tPHl
"Eto Output
tPlH
Cpo
Power Dissipation Capacitance'
'Cpo is used to determine the dynamiC power consumption. per package.
PO =Vee' f, (Cpo + Cd where:
f, = input frequency.
C L = output load capacitance
Vee = supply voltage
PREREQUISITE FOR SWITCHING FUNCTION
-40°C 10 +85°C
-55°C 10 +125°C
25°C
74HC
74HCT
HC
HCT
54HC
54HCT UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
CHARACTERISTIC
SYMBOL
Vcc
LE Pulse Width
tw
2
4.5
6
75
15
13
2
4.5
6
100
20
17
2
4.5
6
0
0
0
Select to LE
Set-up time
Select to LE
Hold Time
t,u
tH
-
-
-
-
30
-
-
-
20
-
-
-
-
-
-
-
-
5
-
-
-
95
19
16
125
25
21
0
0
0
-
-
-
38
25
-
5
-
-
110
22
19
150
30
26
0
0
0
-
-
-
45
-
-
-
-
-
-
30
5
-
ns
ns
-
ns
SWITCHING CHARACTERISTICS (Cl = 50 pF, Input I" If = 6 ns)
CHARACTERISTIC
SYMBOL
Propagation Delay
Select to Outputs
tPHl
tpLH
tPLH
LE to Outputs
E to Outputs
Output Transition
Time
Input Capacitance
t pHL
t PLH
t pHL
hLH
hHl
Vcc
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
C,
578 _ _ _ _ _ _ _ _ _
~
25°C
-40°C to +85°C
-55°C 10 +125°C
HCT
74HC
74HCT
54HC
54HCT
UNITS
HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
345 115 - 275 ns
55
69
83
55
69
83
47
59
71
-
-
-
-
-
225
45
38
-
175
35
30
-
-
-
15
-
-
-
75
15
13
-
10
-
-
50
-
-
-
-
-
-
-
40
-
10
280
56
48
-
63
-
-
220
44
37
-
-
-
95
19
16
-
19
-
-
10
-
10
-
340
68
58
-
-
-
-
-
265
53
45
-
50
-
60
-
-
110
22
19
10
75
ns
-
22
ns
ns
10
pF
_____________________________________________
______________________________ Technical Data
CD54/74HC4514, CD54/74HCT4514
CD54/74HC4515, CD54/74HCT4515
I 116 ns
f
-=-=~,.-'-
- - -
-- -
-
-.
t
INPUT LEVEL
90"10-
Vs
IO%-LGND
tpHL
92CS- 38346RI
Propagation delay times and transition times for HC/HCT4515.
_______________________________________________________________________ 579
Technical Data
CD54/74HC4518, CD54/74HCT4518
CD54/74HC4520, CD54/74HCT4520
Fi Ie Number
1665
High-Speed CMOS Logic
100
4
5
101
102
103
12
13
14
Dual Synchronous Counters
CD54/74HC/HCT4518 -
BCD
CD54/74HC/HCT4520 -
Binary
200
20 I
202
203
Type Features:
• Positive or Negative Edge Triggering
• Synchronous Internal Carry Propagation
Vee =16
2MR 15
92C5 - 38409RI
GND=8
FUNCTIONAL DIAGRAM
The RCA CD54/74HC4518 and CD54/74HCT4518 are dual
BCD up-counters. The RCA CD54!74HC4520 and
CD54/74HCT4520 are dual binary up-counters. Each device
consists of two independent internally synchronous 4-stage
counters. The counter stages are D-type flip-flops having
interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or the negative-going
transition of CLOCK. The counters are cleared by high
levels on the MASTER RESET lines. The counter can be
cascaded in the ripple mode by connecting 03 to the
ENABLE input of the subsequent counter while the CLOCK
input of the latter is held low.
The CD54HC/HCT4518 and CD54HC/HCT4520 are
supplied in 16-lead ceramic dual-in-line packages (F suffix).
The CD74HC/HCT4518 and CD74HC/HCT4520 are
supplied in a 16-lead plastic dual-in-line packages (E
suffix), and in 16-lead surface mount plastic dual-in-line
packages (M suffix). The CD54!74HC/HCT4518/4520 are
also supplied in chip form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LS TTL Loads
• Wide Operating Temperature Range:
CD74HCIHCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 30%, N,H = 30% of Vee: @ Vee = 5 V
• CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, -S 11lA @ VOL, VO H
ICP
16
IE
15
2 MR
100
14
203
13
202
10 I
I Q2
103
IMR
4
Vce
12
2QI
"
2QO
10
2E
2CP
G ND
92C$ -38 4 08
TERMINAL ASSIGNMENT
580 ________________________________________________________________
______________________________________________________________ TechnicaIData
CD54/74HC4518, CD54/74HCT4518
CD54/74HC4520, CD54/74HCT4520
8
GN0o--
92.CM-38548R2
Fig. 1 -
CD54174HCIHCT4518 Logic Diagram
16
VCCo--
8
GNOo--
Fig. 2 - CD54174HC/HCT4520 Logic Diagram
TRUTH TABLE
CL
CL
A ---------------
CP
E
~
H
MR
L
Increment Counter
L
'--
L
Increment Counter
'--
X
L
No Change
X
...r
L
No Change
-..r-
L
No Change
H
'-
L
L
X
X
X = Don't Care
92C5- 38546Rl
Fig. 3 - Detail of each 0 Flip-Flop
~=
H
ACTION
No Change
00 thru 03 0 L
H = High State
L
= Low State
law-to-high transition
" -= high-to-law transition
581
TechnicaIOata _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - - - - - - - - -
CD54/74HC4518, CD54/74HCT4518
CD54/74HC4520, CD54/74HCT4520
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) "", .............................................................. , .............. -0.5 to + 7 V
DC INPUT DIODE CURRENT, 1,K (FOR V, < -0.5 V OR V, > Vee +0.5V) ..................................................... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo> Vee +0.5V) ................................................. ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo< Vee + 0.5V) .................................................. ±25mA
DC Vee OR GROUND CURRENT, PER PIN (Icc) ......................................................•................... ±50mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60° C (PACKAGE TYPE E) ............................................................................ 500 mW
For T. = +60 to +85°C (PACKAGE TYPE E) .....................................•......... Derate Linearly at 8 mW/oC to 300 mW
For T. = -55 to +100°C (PACKAGE TYPE F, H) ......................................................................... 500 mW
For T. = +100 to +125°C (PACKAGE TYPE F, H) .......................................... Derate Linearly at 8 mW/oC to 300 mW
For T. = -40 to +70° C (PACKAGE TYPE M) ..........................•................................................ 400 mW
For T. = +70 to +125° C (PACKAGE TYPE M) .............................................. Derate Linearly at 6 mW/o C to 70 mW
OPERATING-TEMPERATURE RANGE IT.):
PACKAGE TYPE F, H .......................................................................................... -55 to +125°C
PACKAGE TYPE E, M .......................................................................................... -40 to +85° C
STORAGE TEMPERATURE (T".) .................................................................................. -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1132 in. (1.59 ± 0.79 mm) from case for 10 s max ...................................................... +265·C
Unit inserted into a PC Board (min. thickness 1116 in., 1.59 mm)
+300·C
with solder contacting lead tips only ....................... .
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vee:"
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V ,N, Vour
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t" tf
at2 V
at4.5V
at6 V
LIMITS
UNITS
MIN.
MAX.
2
4.5
6
5.5
a
Vee
V
V
V
-40
-55
+85
+125
·C
·C
a
a
a
1000
ns
ns
ns
500
400
"Unless otherwise specified, all voltages are referenced to Ground.
582 ________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4518, CD54/74HCT4518
CD54/74HC4520, CD54/74HCT4520
STATIC ELECTRICAL CHARACTERISTICS
CD74HC4518/CD54HC4518
CD74HC4520/CD54HC4520
CC'74HCT4518/CD54HCT4518
CD74HCT4520/CD54HCT4520
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
SERIES
SERIES
SERIES
CONDITIONS
SERIES
SERIES
SERIES
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
V
10
rnA
V"
V
Min
High-Level
Input Voltage
V"'
Low-Level
Input Voltage
V"
High-Level
V"
Output Voltage
or
VOt<
CMOS Loads
-0.02
V"'
+25°C
V,
V
Typ Max Min Max Min Max
2
1.5
-
-
4.5
3.15
-
-
6
4.2
-
1.5
-
1.5
-
315
-
3.15
-
-
42
-
4.2
-
Min
2
-
-
0.5
-
0.5
-
0.5
45
-
-
1.35
-
1.35
-
1.35
6
-
-
1.8
-
1.8
-
1.8
2
1.9
-
-
1.9
-
1.9
-
V"
4.5
4.4
-
-
4.4
-
4.4
-
or
6
59
-
-
5.9
-
5.9
-
V'H
Vm
CMOS Loads
-
-
3.84
-
37
-
or
V,"
-52
6
5.48
-
-
5.34
-
5.2
-
V,"
2
-
-
0.1
-
0.1
-
0.1
V"
0.02
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
V,"
V"
TTL Loads
Input Leakage
Current
-
-
0.8
--
4.5
44
-
-
4.4
-
4.4
-
V
45
3.98
-
-
384
-
3.7
-
V
2
-
V
-
0.8
V
-
to
08
4.5
-
-
0.1
-
0.1
-
01
V
4.5
-
-
0.26
-
0.33
-
0.4
V
55
-
-
±O 1
_.
±1
-
±1
iJA
5.5
-
-
8
-
80
-
160
iJA
360
-
450
-
490
iJA
V"
or
4
4.5
-
-
0.26
-
0.33
-
04
or
VII <
5.2
6
-
-
0.26
-
0.33
-
0.4
V'H
6
-
-
±O.1
-
±1
-
±1
Any
Voltage
Between
Vee
I,
2
V"
3.98
or
-
55
45
V"
-
45
-
-4
Low-Level
2
to
55
or
Output Voltage
Typ Max Min Max Min Max
4;
-
V"
TTL Loads
V"
V
or
Vcr;
& Gnd
Gnd
Quiescent
V"
Device
or
Current
I"
Vee
0
6
-
8
-
Gnd
-
80
-
160
or
Gnd
Additional
Quiescent
Device Current
per input pin
.6.lcc·
1 unit load
4.5
Vc c-2.1
to
-
100
5.5
-For dual-supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
MR
CP
ENABLE
Unit Loads·
1.2
0.25
0.5
'Unit Load is Ll.lcc limit specified in Static Characteristic
Chart, e.g., 360l'A max. @ 25 0 c.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 583
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4518, CD54/74HCT4518
CD54/74HC4520, CD54/74HCT4520
SWITCHING CHARACTERISTICS (Vcc = 5 V, TA = 25°C, Input t. t, = 6 ns)
CL
(pF)
CHARACTERISTIC
I
I
Maximum Clock Frequency
15
Propagation Delay
CP to an
SYMBOL
I
t PLH
t PHl
15
t pLH
15
Enable to an
MR to an
-
I
I
UNITS
I
50
MHz
20
22
ns
60
20
23
ns
t pLH
t pHL
12
14
ns
CPD
33
33
pF
tPHL
15
I Power Dissipation Capacitance'
f MAX
TYPICAL
HC
HCT
f. - output frequency,
CL = output load capacitance
Vee = supply voltage
'CPD ,s used to determine the dynamic power consumption, per counter.
Pc = Gpo Vee? 1,-+ I C L Vee? 10 where
f, = input frequency,
PREREQUISITE FOR SWITCHING FUNCTION
CHARACTERISTIC
SYMBOL
Vcc
2
4.5
6
2
Clock Pulse Width
tw
4.5
6
2
MR Pulse Width
tw
4.5
6
2
Setup Time
4.5
tsu
Enable to CP
6
2
Removal Time
4.5
tREM
MR to CP
6
2
Setup Time
4.5
tsu
CPlo Enable
6
2
Removal Time
4.5
tREM
MR to Enable
6
SWITCHING CHARACTERISTICS (C L =
Maximum Clock
Frequency
fMAX
CHARACTERISTIC
SYMBOL
Vcc
Propagation Delay,
CPto an
tPlH
t pHl
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
Enable to an
t pLH
t pHL
MR to an
tpHL
Output
Transition Time
Input CapacitancE,
hHL
trLH
C,
25°C
HC
HCT
Min. 'Max. Min. Max.
6
30
25
35
80
20
16
14
100 20
20
17
80
16
16
14
0
0
0
0
80
16
16
14
0
0
0
0
50 pF, Inpul 1,,1, = 6 ns)
_40' C to +85° C
-55°C to +125°C
UNITS
74HC
74HCT
54HC
54HCT
Min. Max. Min. Max. Min. Max, Min. Max.
5
4
24
20
17
20
MHz
28
24
100 120 2.5
30
ns
24
20
20
17
125 150 30
ns
25
25
30
26
21
100 120 24
20
20
ns
24
17
20
0
0
0
ns
0
0
0
0
0
100 120 24
20
20
ns
24
17
20
0
0
0
0
0
0
ns
0
0
-
_40° C to +85° C
25°C
-55° C 10 +125° C
HC
HCT
54HCT
UNITS
74HC
74HCT
54HC
Min. Max. Min. Max. Min. Max. Min, Max. Min. Max. Min. Max.
360 300 240 80
72
ns
66
53
60
48
61
41
51
360 300 240 . 60
83
69
72
ns
-- 48 55
61
51
41
190 225 150 53
ns
44
35
38
45
30
26
33
38
95
110 75
ns
19
15
19
22
22
15
16
13
19
10
10
pF
10
10
10
10
-
I
I
584 ________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4518, CD54/74HCT4518
CD54/74HC4520, CD54/74HCT4520
1
CLOCK
ENABLE
2
3
5
4
7
6
8
9
10 II
- ~ il~ 1~ rl Il~ iL n
12 13 14 15 16 17 18
JLf W- II LflJ W"J f---
MASTER RESET
I
02 -
tiC/HCT451B
2
f-
3
ff-
01
4
r---
5
-
7
6
r-f-
8
r-
9
I
rr-
2
r
I-
3
4
5
f'-
7
6
r
l-
8
fff- f-
r-f-
'-
9
0
n-
f--
f--
f-
0
f'-
~
03
-f-
riL-
04
l
HC/HCT452Q
01
-
02
-
-
-
2
3
-
4
5
6
7
8
9
10 II 12 13 14 15 0
I
2
r- f- fr- r- f'r- f- fr- f- f- ' f- r--rr-f- frr
f-f- ff-r
-+-
-
n3 4
n-
03
04
92CM-38410RI
Fig. 4 -
INPUT
LEVEL
Timing Diagrams for CD54174HCIHCT451814520.
Vs
CPTO E
ETOCP
~vs
INPU~
LE~EL
Vs
CP
ISU(H)~
J1
E - - + - - - -..........
cP _ _ _ _
vs
---=J ~)
CP
~
92CS - 3S859Rl
Q----92CS-38544
Fig. 5 -
Master reset pulse width. Master reset to output delay and
master reser co clOck recovery
Fig. 6 - Setup Times: E to CP and CP to E.
Tlm~;;,.
Input Level
Switching Voltage, Vs
_____________________________
~
______________ 585
Technical Data
CD54/74HC4538
CD54/74HCT4538
File Number
1671
High-Speed CMOS Logic
1 e,
'",
Vee
6
"
tB
'"2"
10
7
10
13
2.
12
Te
11
10
20
9_
20
Vee
2e,
2",
FUNCTIONAL DIAGRAM
Dual Retriggerable Precision
Monostable Multivibrator
Type Features:
• Retriggerable/resettable capability
Trigger and Reset propagation delays
independent of R" G,
Trigge0:!g from the leading or trailing edge
Q and Q Buffered Outputs available
• Separate Resets
• Wide Range of Output-Pulse Widths
• Schmitt Trigger input on A and B inputs
Retrigger Time is independent of G,.
•
•
•
•
The RCA-CD54174HC4538 and CD54/74HCT4538 are dual
retriggerable/resettable monostable precision multivibrators
for fixed voltage timing applications. An external resistor
(R,) and an external capacitor (C,) control the timing and
the accuracy for the circuit. Adjustment of R, and C,
provides a wide range of output pulse widths from the Q and
'tr terminals. The propagation delay from trigger input-tooutput transition and the propagation delay from reset
input-to-output transition are independent of R, and C,.
Leading-edge triggering (A) and trailing edge triggering
(8) inputs are provided for triggering from either edge of
the input pulse. An unused "A" input should be tied to Gnd
and an unused 8 should be tied to Vee. On power up the IC
is reset. Unused resets and sections must be terminated. In
normal operation the ci rcuit retriggers on the application
of each new trigger pulse. To operate in the non-retriggerable mode Qis connected to 8 when leading edge triggering (A) is used or Q is connected to A when trailing edge
triggering (8) is used. The period (T) can be calculated from
T = (0.7) R, C,; Rmin is 5k ohms. Cm'n is 0 pF.
The CD54HC/HCT4538 are supplied in 16-lead ceramic
dual-in-line packages (F suffix). The CD74HC/HCT4538
are supplied in 16-lead dual-in-line plastic packages (E
suffix), also in 16-lead dual-in-line surface mount plastic
packages (M suffix): The CD54/74HC/HCT4538 are also
available in chip form (H suffix).
Family Features:
• Fanollt (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity:
ML = 30%, MH = 30% of Vee: @ Vee = 5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, :S 1 f.JA @ VOL, VOH
lex
16 Vee
1RXCX
15 2Cx
iR
14 2RxCx
lA
13
iii
12 2A
2A
28
10
11
iQ
10 2Q
GND
9
2Q
92CS-36465
TERMINAL ASSIGNMENT
586 ______________________________________________________________________
Technical Data
CD54/74HC4538
CD54/74HCT4538
16
~VCC
RI
R2
A
92CM-!B447R2
Fig. 1 - Logic diagram (1 mono).
TRUTH TABLE
OUTPUTS
INPUTS
R
A
B
Q
Q
L
X
X
X
H
X
X
L
L
L
H
H
L
---.......
.n
H
H
H
u
~
H
Il
U
X
L
H = High Level
L
=Low Level
~
FF DETAIL
Transition from Low to High
""'-:= Transition from High to Low
CL
CL
.n.= One High Level Pulse
92CM-3B447R2
U =One Low Level Pulse
X
=Irrelevant
HC!HCT4538 FUNCTIONAL TERMINAL CONNECTIONS
GndTO
INPUT PULSE
Vee TO
OTHER
TERM. NO.
CONNECTIONS
TERM. NO.
FUNCTION
MONO,
MONO.
11,13
4
12
3
13
4
12
3
13
5
11
3
13
5
11
MONO,
MONO.
Leading-Edge Trigger!
Retriggerable
3,5
Leading-Edge Trigger!
Non-Retriggerable
Trailinlo ~dge Trigger!
Retriggerable
Trailing-Ed{;e Trigger!
Non-Retriggerable
MONO,
4
MONO.
TO TERM. NO.
12
MONO,
MONO.
5-7
11-9
4-6
12-10
INPUT PULSE TRAIN
NOTES:
1. A RETRIGGERABLE ONE-SHOT MULTIVIBRATOR HAS AN
OUTPUT PULSE WIDTH WHICH IS EXTENDED ONE FULL
TIME PERIOD (T) AFTER APPLICATION OF THE LAST
TRIGGER PULSE.
2. A NON-RETRIGGERABLE ONE-SHOT MULTlVIBRATOR
HAS A TIME PERIOD (T) REFERENCED FROM THE APPLICATION OF THE FIRST TRIGGER PULSE.
RETRIGGERABLE MODE PULSE
WIDTH (A MODE)
NON-RETRIGGERABLE MODE
PULSE WIDTH
(A MODE)
.
________________________________________________________________ 587
Technical Data
CD54/74HC4538
C o54/74H CT4538
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) " ................................................................................ -0.5 to + 7 V
"DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee + 0.5 V) ..................................................... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5V) ................................................. ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V) ..................................•............... ±25mA
DC Vee OR GROUND CURRENT (Icc) ....................................................•.............................. ±50mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60° C (PACKAGE TYPE E) ........................................................................... 500 mW
For TA +60 to +85° C (PACKAGE TYPE E) .............................................. Derate Linearly at 8 mW/o C to 300 mW
For TA = -55 to +100°C (PACKAGE TYPE F, H) ....................................................... ..........
500 mW
For T. ~ -t 100 to +125° C (PACKAGE TYPE F, H) ......................................... Derate Linearly at 8 mW/o C to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) ............................................................................ 400 mW
For TA = +70 to +125°C (PACKAGE TYPE M) .............................................. Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (TAl:
PACKAGE TYPE F, H .......................................................................................... -55 to +125°C
PACKAGE TYPE E, M .......................................................................................... -40 to +85°C
STORAGE TEMPERATURE (T".) ................................................................................. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ...................................................... +265°C
Unit inserted into a PC Board (min. thickness 1116 in., 1.59 mm)
with solder contacting lead tips only .................................................................................. +300° C
"DC INPUT CURRENT FOR Cx Rx PIN = 30 mA
=
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA = Full Package-Temperature Range)Vee:*
CD54/74HC Types
CD54/74HCT Types
DC Input or Output Voltage V" Va
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t" tf
Reset Input
at2V
at 4.5 V
at6 V
Trigger Inputs
AorB
at2V
at4.5V
at6 V
External Timing Resistor, R,
External Timing Capacitor, Cx
LIMITS
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
-40
-55
+85
+125
·C
0
ns
0
1000
500
400
0
0
0
Unlimited
Unlimited
Unlimited
ns
5kO
#
0
#
6
V
V
*Unless otherwise specified, all voltages are referenced to Ground.
#The maximum allowable values of Rx and Cx are a function of leakage of capacitor
Cx, the leakage of the HC4538, and leakage due to board layout and surface resistance.
Values of Rx and C, should be chosen so that the maximum cu"rrent into pin 2 or pin 14 is
30 mA. Susceptibility to externally induced noise signals may occur for Rx > 1 MO.
50 _______________________________________________________________
Technical Data
CD54/74HC4538
CD54/74HCT4538
STATIC ELECTRICAL CHARACTERISTICS
CD74HC4538/CD54HC4538
CD74HCT4538/CD54HCT4538
TEST
74HC/54HC
74HC
CONDITIONS
TYPE
TYPE
54HC
TYPE
-401
-551
+85°C
+125°C
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
+85°C
+125°C
CHARACTERISTIC
UNITS
+25°C
V,
V
10
rnA
V"
V
+25°C
V,
V
V"
V
Min Typ Max Min Max Min M..
High-Level
Input Voltage
V,"
Low-Level
Input Voltage
V"
High-Level
V"
Output Voltage
VO "
CMOS Loads
or
-0.02
V,"
2
1.5
-
-
1.5
-
1.5
-
4.5
3.15
-
-
3.15
-
315
-
6
4.2
-
-
42
-
4.2
-
4.5
-
Low-Level
2
-
-
0.5
-
0.5
-
0.5
4.5
-
-
1.35
-
135
-
135
Voc
6
-
-
1.8
-
1.8
-
1.8
CMOS Loads
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
-
2
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5
44
-
-
44
-
4.4
-
V
45
398
-
-
3.84
-
3.7
-
V
45
-
-
0,1
-
0.1
-
0.1
V
4.5
-
-
026
-
0.33
--
0.4
V
-
-
,01
-
±1
-
±1
IJA
±O.5
-
..to.S
IJA
10
V"
V"
4.5
3.98
-
-
384
-
3.7
-
or
V,"
-5.2
6
5.48
-
-
5.34
-
5.2
-
V,"
2
-
-
0.1
-
0.1
-
0.1
V"
4.5
-
-
0.1
-
0.1
-
0.1
or
6
-
-
01
-
0.1
-
0.1
V,"
0.02
V,"
V"
V"
TTL Loads
or
4
45
-
-
0.26
-
0.33
-
0.4
or
Standard Output
V,"
5.2
6
-
-
0.26
-
0.33
-
0.4
V,"
6
-
-
±O.1
-
±1
-
±1
5.5
6
-
-
±0,05
-
Any
Voltage
Between
::to 5
-
.to.5
Vee
5.5
Input Leakag~
Current A, B. R
.
-
5.5
-4
or
-
45
-
or
V"
Output Voltage
2
10
55
V"
TTL Loads
Min Typ Ma, Min Max Min Max
Vee
I,
or
Input Leakage
Current
I,
R;.:C;<.
Gnd
Quiescent
Vee
Device
or
Current
Icc
Active Oevice
Current
Q = High&Pins 2&14
@ Vccl4
ICC
Additional
Quiescent
Device Current
per input pin:
1 unilload
&Gnd
Vee
0
6
-
-
8
-
80
-
160
or
5.5
-
-
8
-
80
-
160
IJA
5,5
-
-
0.6
-
0.8
-
1
rnA
100 360
-
450
-
490
IJA
Gnd
Gnd
Vee
or
!Q,Q5
Vee
0
6
-
-
0,6
-
0.8
-
1
or
Gnd
Gnd
4.5
Vcc-2 .1
10
-
5.5
~Icc
• For dual-supply systems theoretical worst case (VI - 2.4 V, Vee - 5.5 V) specification IS 1.8 rnA.
o When testing IlL the Q output must be high. If Q is low (device not triggered) the pull-up P device will be ON and the low resistance path from Vee to the
test pin will cause a current far exceeding the specification.
HCT Input Loading Table
Input
All
Unit Loads'
0.5
'Unit Load is "'Icc limit specified in Static Characteristic
Chart, e.g., 360 JiA max. @ 25 0 C.
------------------------~--~----~-------------------------------
589
Technical Data
CD54/74HC4538
CD 54/74HCT4538
SWITCHING CHARACTERISTICS (Vee =5 V, T A
=25 0 C, Inpul I. If =6 ns)
CL
(pF)
CHARACTERISTIC
TYPICAL
54n4HC
54/74HCT
UNITS
Propagation Delay
A,SloQ
tPLH
15
21
23
ns
A,StoQ
IpHl
15
21
23
ns
RtoQ
tPHl
15
21
17
ns
RtoQ
tPLH
15
21
21
ns
Cpo
-
136
134
pF
.
Power Dissipation Capacitance
'Cpo is used to determine the dynamic power consumption, per one shot.
Po = (Cpo + C.) Vee2 Ii + I (Cl Vee' 10 ) where:
I, = input Irequency.
10 = output Irequency.
C L = output load capacitance.
Vee = supply voltage.
assuming I, <{
f
PREREQUISITE FOR SWITCHING FUNCTION
LIMITS
_40 0 C to +85 0 C
_55 0 C to
HC
HCT
74HCT
54HC
74HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
80
120
100
16
16
20
20
24
14
17
20
80
100 120 16
20
20
25
24
14
17
20
5
5
5
5
5
5
5
5
5
5
5
Typical
25 0 C
CHARACTERISTIC
Input Pulse Widths
A,S
R
tWH
tWl
tWl
Reset Recovery
Time
Retrigger Time
(See Fig. 5)
5~
SYMBOL
tREC
t"
Vee
2
4.5
6
2
4.5
6
2
4.5
6
5
-
-
175
-
-
-
+125 0 C
UNITS
54HCT
Min. Max.
24
-
-
-
-
30
-
-
-
-
5
-
-
ns
ns
ns
ns
________________________________________________________________
Technical Data
CD54/74HC4538
CD54/74HCT4538
SWITCHING CHARACTERISTICS (CL = 50 pF, Inpul I. I, = 6 ns)
CHARACTERISTIC
SYMBOL
Vee
Propagation Delay,
A,Btoa
t pLH
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
A,Btoa
tpHL
Rtoa
tPHL
Rtoa
t plH
Output
Transition Time
hLH
tTHL
Output Pulse
Width
Rx=10n. Cx=0.1 /IF
_40° C 10 +85° C
25°C
-55°C 10 +125°C
HC
HCT
74HC
74HCT
54HC
54HCT
UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
315 250 - 375 63
69
83
50
55
75
ns
64
43
54
- 250 - 375 - 315 75
50
63
69
ns
55
83
43
54
64
250 - 315 - 375 75
63
50
50
40
60
ns
64
43
54
- 250 - 315 - 375 50
50
63
63
75
75
ns
43
54
64
75
- 110 95
15
15
19
19
22
22
ns
13
16
19
0.64 0.78 0.612 0.812 0.605 0.819 0.63 0.77 0.63 0.77 0.602 0.798 0.602 0.798 0.595 0.805 0.595 0.805
3
5
T
Output Pulse Width
Match, Same Pkg.
ms
Typ ± 1%
Input Capacitance
C;
-
10
-
10
-
10
HC4538 - TA1164&C
TA 2S·C
-
10
10
-
-
10
pF
HCT4538 - TA13646C
TA
2S"C
0.70
0.70
10Kn,10nF
0.69
II:
10Kn,100nF
100Kn,100nF
~
~
" 0.68
100Kn,10nF
0.67
u.
3
4
4.5
5
5.5
DC SUPPLY VOLTAGE (Vee) -
2
6 V
v
DC SUPPLY VOLTAGE (Vee) - v
Fig. 2 - K Factor Vs DC Supply Voltage (vccl-V.
1.3
1.2
1.1
1.0
0..
" 0.8
0.7
0.6
10
;1:
Fig. 3 - K Factor Vs DC Supply Voltage (vccl-V.
HC/HCT4538
Vee 5 V, TA= 2S"C
=
I
~
t
I
II:
~
0
.
~ 103··~111111*11
"
j:
"-
•
II:
\
W
.....
2KQ
"-
10Ka
100Kn
III
~
Vee .... 4.5 V
...
Z
iii
a:
~
104
TIMING CAPACITANCE (ex) - pF
b-'l
W
II:
•
10
102
II
8
103 '
4
II II
104
TIMING CAPACITANCE (Cld- pF
Fig. 4 - K Factor Vs Cx.
Fig. 5 - Minimum Retrigger Time Vs Timing Capacitance.
591
Technical Data
CD54/74HC4538
CD 54/74H CT4538
INPUT LEVE::.L_ _ __
B
INPUT
GND
r - - - - I N P U T LEVEL
A
INPUT
'C'=O. 1RX CX
GND
Q
92CS-384~9Rt
A"
l,=-:1 t=F-="===0ri90'""%--------
~~~~~~~~1~0~%~____~--------
Vee
GND
r---Vee
'--~'----
GND
Vee
.
Vs
Q
'THLi
r
'PLH
;:::~:~~-T+-'-rr:::===-=-_=_-l
(RETRIGGERED PULSE)
1-1
I
-=90%".......----,\
Q~t-- -----~=~--==-=-
X",.;;.;::-=..:=.=!-'- -
- - - 10 %
Input Level
Switching Voltage, Vs
'1..._ _ _ _ _ _ _- ' .
54174HC
54174HCT
Vcc
3V
1.3 V
500f0VCC
Fig. 6 - Switching Waveforms
592 __________________________________________________________
Technical Data
CD54/74HC4538
CD54/74HCT4538
Power-Down Mode
During a rapid power-down condition, as would occur with a
power-supply stJor! circuit or with a poorly filtered· power supply,
the energy stored in ex could discharge into Pin 2 or 14. To
avoid possible device damage in this mode, when ex is 2: 0.5
microfarad, a protection diode with a 1-ampere or higher rating
(1 N5395 or equivalent) and a separate ground return for ex
'should be provided as shown in Fig. 7.
vcc
EQ~~~:::NT r:
L ."'-_. . =!.~
2(14)
16
1(15)
8
UCS-4OD12
Fig. 7 - Rapid power-down protection circuit.
An alternate protection method is shown in Fig. 8, where a 51ohm current-limiting resistor is inserted in series with eX. Note
that a small pulse width decrease will occur however, and Rx
must be appropriately increased to obtain the originally desired
pulse width.
vcc
RX
2(14)
16
1(15)
8
cx
~O.5JJF
nCB-4ODtt
Fig. 8 - Alternate rapid power-down protection circuit.
_________________________________________________________________ 593
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4543
CD54/74HCT4543
File Number
1822
High-Speed CMOS Logic
BCD
7-SEGMENT
IN PUTS
I
PH
.
I
9~
5
f
O~~ ~
~
02
03 4
BCD-to-7 Segment Latch/
Decoder/Driver for LCDs
OUTPUTS
o
E
C
10 b
11
o
R
~E ~~ ed
R
R
E
8'
,
DISPLAY
c
a
o
~1/1.?131..,15IbI1IBlql
o
15 f .
14.
4
7
,
9
,
b
d
92CS-250B7
LO
Type Features:
• Input latches for BCD code storage
• Blanking capability
• Phase input for complementing outputs
Vec=IS
FUNCTIONAL DIAGRAM
The RCA CD54/74HC4543 and CD54174HCT4543 highspeed Silicon-gate devices are BCD-to-7 segment latch/decoder/drivers designed primarily for directly driving liquidcrystal displays. They have an active-high disable input
(LD), an active high blanking input (BI) and a phase input
(PH) to which a square wave is applied for liquid-crystal
applications. This square wave is also applied to the
backplane of the liquid-crystal display.
Thesedevices can also be used, in conjunction with current
amplifying devices, for driving LEDs, incandescent, fluorescent, and gas-discharge displays. For these applications
the phase input provides a means for obtaining active-high
or active-low segment outputs. (See FunctionTable.)
The CD54HC/HCT4543 are supplied in 16-lead ceramic
dual-in-line frit-seal packages (F suffix). The CD74HC/HCT4543 are supplied in 16-lead dual-in-line plastic packages
(E suffix) and in 16-lead dual-in-line surface-mount plastic
packages (M suffix). Both types are also available in chip
form (H suffix).
LD
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
.,
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
as above
Family Features:
• Fanout (over temperature range):
Standard outputs - 10 LSTTL loads
Bus driver outputs - 15 LSTTL loads
• Wide operating temperature range:
CD74HC/HCT: -40 to +85 0 C
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL
logiC ICs
• Alternate source is Philips/Signetics
• CD54HC/CD74HC types:
2 to 6 V operation
High noise immunity:
ML=30%, MH=30% of Vce; @ Vee=5 V
• CD54HCT/CD74HCT types:
4.5 to 5.5 V operation
Direct LSTTL input logic compatibility
VIL =0.8 V max., V'H=2 V min.
CMOS input compatibility
/,::;;1 pA @ VOL, VOH
FUNCTION TABLE
INPUTS
PH D3 02 D1
L
X
X
X
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
L
H
L
L
L
L
L
H
H
L
L
H
H
L
H
L
L
L
H
L
L
L
H
L
H
L
H
L
H
L
H
H
L
L
H
H
L
L
H
H
H
L
H
H
H
L
X
X
X
H
as above
DO
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
a
b
L
H
L
H
H
H
H
H
L
H
H
L
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
L
,OUTPUTS
d
e
L
H
H
L
H
H
H
H
H
H
H
L
L
L
L
L
L
I
9
L
H
L
H
L
H
L
L
L
H
H
L
H
H
L
H
H
L
L
L
L
L
L
L
H
L
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
H
H
H
L
H
H
L
L
L
L
L
L
L
H
H
H
H
H
L
H
H
L
L
L
L
L
L
DISPLAY
Blank
0
1
2
3
4
5
6
7
8
9
Blank
Blank
Blank
Blank
Blank
Blank
"
..
inverse of above
as above
r
16
LD
BCD
INPUTS
15
vcc
,
14
01
03
13
DO
12
PH
BI
11
7-SEGMENT
OUTPUTS
10
GN 0
9
TOP VIEW
TERMINAL ASSIGNMENT
"Depends upon the BCD code previously applied when lD = High
594 ______________________________________________________________
___________________________________________________________ TechnicaIData
CD54/74HC4543
CD54/74HCT4543
BI
iili
QO
LATCH
LO
LO
to
CO
ii1
01
iili
Q1
LATCH
LO
LO
La
CO
Qi"
Cn
~
Q2
LATCH
LO
LD
Lo
LaQ2
53
Q3
LATCH
LD
Di
LD _
Th
Q3
1
LO~~
LD
Fig. 1 - Logic diagram.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) •..•...•.•..••••.•.....•.•..••.••..••.•.•.•.....•.•...•••..•.....••.•.•..•.......•.... -0.5 to +7 V
DC INPUT DIODE CURRENT, 1,K (FOR V, < -0.5 V OR V, > Vee +0.5 V) •...•...............••.•••......•..........•....••.•..• ±20 mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) ....•.•....•.....••.•.......••.•.••............•... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) .........••......••.....•.•.•••..•.•.•.........••••.• ±25 mA
DC Vee OR GROUND CURRENT (lee) .•.•...••••••.•.•...•..•...•...•..••..•...• , •.• , ... , .......•..••.•. , •• , ••..•••.••.••.. ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60° C (PACKAGE TYPE E) •.....••.•.....••......••.....•.•....•..•..•••.....•••.•.........•. , .••..••..•• 500 mW
ForT. = +60 to +85°C (PACKAGE TYPE E) ..•••••..•......•.••...••..•..••.........•••.•..•. Derate Linearly at 8 mW/oC to 300 mW
ForT. = -55 to +100°C (PACKAGE TYPE F,H) •..•.....•..•..•••.••......•..••••.•..•......••••••.••••..••.••.•••..•...... 500 mW
For T. = +100 to +125°C (PACKAGE TYPE F,H) .•.........•...•••.••.•••...••..•••..•.•••.... Derate Linearly at 8 mW/oC to 300 mW
For T. = -40 to +70· C (PACKAGE TYPE M) ••..••.......••...••..•...•...•..••.•...••.••....••••••.••..••••.••.•...•..... 400 mW
For T. = +70 to +125· C (PACKAGE TYPE M) •.•.......•....••.•.••.•.•...•..••.•..•••...•.••• Derate Linearly at 6 mW/o C to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F,H •.....•...••..••.•......•.•.......••....••••...••..••.•.•••.•••.••........••.•.....•••.•.••.. -55 to +125°C
PACKAGE TYPE E,M ••.....••..••.•.•••..•.........••.•.••...•.•...•••.......•..••..•...••..••...•.....•......•... -40 to +85° C
STORAGE TEMPERATURE (T...) ..........•....•..••.•.•••..•...•.•.•......•.•..•...•..•..•.......•.•...•....•....•. -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for lOs max.
• ....•.•••...••.....••••••..••......••..••.•.•.•.•.•• +265° C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ..•••..••...••••. , .••.•.. , ..•.•......••••..•......•••.......••..••••.•.•.•.•...••.• +300° C
_________________________________________________________________ 595
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4543
CD54/74HCT4543
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation Is always within
the following ranges:
LIMITS
CHARACTERISTIC
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
Supply-Voltage Range (For TA=Full Package Temperature Range)
Vee:'"
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage, V" Vo
Operating Temperature, TA:
CD74 Types
CD54 Types
Input Rise and Fall Times, t,,1t:
at 2 V
at 4.5 V
at 6 V
V
V
'Unless otherwise specified, all voltages are referenced to Ground.
SWITCHING CHARACTERISTICS (Vee=5 V, T A =25°C, Inpul 1,,1,=6 ns)
CL (pF)
CHARACTERISTIC
Propagation Delay:
Dn to Output
tpLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Cpo
LD to Output
81 to Output
PH to Output
Power Dissipation Capacitance'
TYPICAL VALUES
HCT
He
15
28
33
15
31
32
15
22
27
15
17
27
-
52
54
UNITS
ns
pF
'Cpo is used to determine the dynamic power consumption, per package.
Po = Cpo Vee 2 fi + I CL Vee 2 fo where f, = input frequency
fo = output frequency
CL = output load capacitance
Vee = supply voltage.
PRE-REQUISITE FOR SWITCHING FUNCTION
CHARACTERISTIC
Setup Time,
Dn to LD
tsu
Hold Time,
Dn to LD
tH
Latch Disable
Pulse Width,
tw
TEST
CONDITIONS
Vee (V)
2
4.5
6
2
4.5
6
2
4.5
6
LIMITS
-40°C to +85°C
-55°C to +125°C
74HCT
54HC
54HCT UNITS
HCT
74HC
HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
60
75
- gO 18
18
12
15
15
12
15
10
13
45
30
40
9
ns
10
12
8
6
8
8
5
7
75
50
65
13
15
10
10
13
- 15 13
9
11
25°C
596 ______________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC4543
CD54/74HCT4543
STATIC ELECTRICAL CHARACTERISTICS
CD74HCT4543/CD54HCT4543
CD74HC4543/CD54HC4543
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85°C
+125°C
+85°C
+125'C
UNITS
CHARACTERISTIC
+25°C
V,
10
Vee
V
mA
V
High-Level
Input Voltage
Low-Level
Input Voltage
V"
High-Level
Output Voltage
Va"
V"
or
-0.02
Min Typ Max Min Max Min Max
1.5
-
4.5 3.15
-
2
V,"
+25°C
2
-
4.5
-
-
6
-
-
6
4.2
-
1.5
-
1.5
3.15
-
3.15
-
4.2
-
4.2
-
0.5
-
0.5
-
0.5
1.35
-
1.35
-
1.35
1.8
-
1.8
-
1.8
V,
Vee
V
V
-
2
1.9
-
-
1.9
-
1.9
-
4.5
4.4
-
-
4.4
-
4.4
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5 3.98
-
-
3.84
3.7
-
V"
or
5.48
-
-
5.34
-
5.2
-
V,"
V"
or
V"
or
-1
Non-Standard Output
V,"
-1.3
6
V"
or
2
-
-
0.1
-
0.1
4.5
-
0.1
-
0.1
0.1
V"
or
6
-
-
-
0.1
0.02
0.1
-
0.1
-
0.1
V,"
-
0.26
-
0.33
0.4
V"
or
0.26
-
0.33
-
0.4
V,"
CMOS Loads
V,"
TTL Loads
V"
or
1
4.5
-
Non-Standard Output
V,"
1.3
6
-
Input Leakage
Current
I,
Device Current
or
6
-
-
1"0.1
-
±1
-
±1
or
-
2
-
V
to
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
3.7
-
V
4.5 3.98
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
Voltage
Between
5.5
-
-
±0.1
-
±1
-
±1
/JA
5.5
-
-
8
-
80
-
160
/JA
-
450
-
490
/JA
Vee
0
6
-
-
8
Gnd
-
80
-
160
or
Gnd
Additional
4.5
Quiescent Device
Vee -2.1
Current per input
pin: 1 unit load
2
Vee & Gnd
Vee
Icc
-
Any
Vee
Gnd
Quiescent
-
5.5
TTL Loads
Voe
2
4.5
-
V,"
Low-Level
to
5.5
CMOS Loads
Output Voltage
Min Typ Max Min Max Min Max
4.5
to
-
100 360
5.5
.Alec
·For dual-supply systems theoretical worst case (VL = 2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Inpul
00,01,02
03,81
PH
LO
Unit Loads·
1
0.5
1.25
1.5
·Unit Load is t.lcc limit specified in Static Characteristics
Chart, e.g., 360 /lA max. @25'C.
__________________________________________ 597
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC4543
CD54n4HCT4543
SWITCHING CHARACTERISTICS (CL=50 pF, Input t"t,=6 nl)
LIMITS
-40°C to +85°C
-55°C to +125°C
HCT
74HC
74HCT
54HC
54HCT UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
425
510 102
ns
85
- 100
120
80
87
72
- 555 465
93
111 116
ns
77
96
94
79
400
330 83
80
99
ns
66
66
56
68
300
250 60
ns
50
83
99
66
43
51
- 315 375
63
75
75
ns
50
63
54
64
10
pF
10
10
10
10
25°C
CHARACTERISTIC
Propagation Delay,
On to Output
VCC
LD to Output
tPLH
tPHL
BI to Output
tPLH
tPHL
PH to Output
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
tPLH
tPHL
tPLH
tpHL
IrLH
IrHL
Transition Time
Input Capacitance
HC
Min. Max.
340
68
58
370
74
63
265
53
45
200
40
34
- 250
50
43
10
-
-
-
C,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LD INPUT
onlNPudvs
ORBI INPUT
I PHL
SEGMENT
OUTPUT
90%
SEGM ENT
OUTPUT
t THL
la)
(a)
(b) WAVEFORMS
WAVEFORMS SHOWING THE ADDRESS AND
BLANKING (On' BI) TO OUTPUT PROPAGATION
DELAYS AND THE OUTPUT TRANSITION TIMES.
SHOWING THE LATCH DISABLE
INPUT (LD) TO OUTPUT PROPAGATION
DELAYS AND THE OUTPUT TRANSITION TIMES.
I
L 0 INPUTVS
f
Ie)
NOTE:
THE SHADED AREAS INDICATE WHEN THE
INPUT IS PERMITTED TO CHANGE FOR
PREDICTABLE OUTPUT PERFORMANCE.
(e) WAVEFORMS
SHOWING THE ADDRESS (Dnl
TO LATCH DISABLE (LD) INPUT SET-UP AND
HOLD TIMES.
I
I Input Level
I Switching Voltage, Vs
54/74HC
Vee
50% Vee
54/74HCT
3V
1.3 V
Fig. 2· AC waveforms.
598 _______________________________________________________________
___________________________________________________________ TechnicaIData
CD54/74HC4543
CD54/74HCT4543
APPLICATION CIRCUITS
APPROPRIATE
VOLTAGE
He IHCT4543
ONE OF SEVEN
OUTPUT
f-----./ SEGMENTS
=~
COMMON
BACK-PLANE
HC/HCT4543
OUTPUT '--"Vv--t-I
PH
GND
Fig. 3 - Connection to liquid-crystal (LCD) display readout.
Fig. 4 - Connection to incandescent display readout.
APPROPRIATE
VOLTAGE
He/HeT 4543
OUTPUT
He/HeT 45 43
OUT PUT
PH
>-~\.A ,,,-
_-+--<
TO FILAMENT
SUPPLY
GND
GND OR APPROPRIATE
PH
-=- VOI,TAGE BELOW GND
GND
Fig. 5 - Connection to gas-discharge display readout.
Fig. 6 - Connection to fluorescent display readout.
______________________________________________________________________ 599
TechnicaIOata _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54n4HC7266
File Number
1780
High-Speed CMOS Logic
,_
1A
1Y
..A
Quad 2-lnput Exclusive-NOR Gate
,Y
3A
10
3_
4A
11
4_
3Y
4Y
GND=7
L---:::
••::-,,::-_-::
..::-••~.
Vee
=14
FUNCTIONAL DIAGRAM
Type Features:
• Four independent Exclusive-NOR gates
• Buffered inputs and outputs
Applications
• Logical comparators
• Parity generators and checkers
• Adders/Subtracters
The RCA CD54174HC7266 contains four independent EXCLUSIVE~NOR gates in one package. They provide the
system designer with a means for implementation of the
EXCLUSIVE-NOR function.
This device is functionally the same as the TTL226. They
differ in that the HC7266 has active high and low outputswhereas the 226 has open collector outputs.
The CD54HC7266 is supplied in 14-lead ceramic dual-inline packages (F suffix). The CD74HC7266 is supplied in
14-lead plastic dual-in-line package (E suffix), in a 14-lead
dual-in-line surface-mount plastic package (M-suffix), and
is also available in chip form (H suffix).
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs -.10 LSTTL Loads
Bus Driver Outputs -15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• 2 to 6 V Operation
High Noise Immunity: ML = 30%, MH = 30% of Vee,
@ Vee=5 V
• CMOS Input Compatibility
I" :5 1 /lA @ VOL, VOH
TRUTH TABLE
nA
INPUTS
nY
nB
Fig. 1 - Logic diagram each gate.
OUTPUT
nA
nB
nY
L
L
H
H
L
H
L
H
H
L
L
H
H = HIGH voltage level.
L = LOW voltage level.
600 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
_____________________________________________________________ TechnicaIData
CD54/74HC7266
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to gr0und) .................................................................................. -0.5 to +7 V
DC INPUT DIODE CURRENT, I'K (FOR V, <-0.5 V OR V, > Vee + 0.5 V) .................................................... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Va < -0.5 V OR Va> Vee +0.5 V) ................................................ ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Va < Vee + 0.5 V) ................................................. ±25mA
DC Vee OR GROUND CURRENT (Icc) .................................................................................... ±50mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60°C (PACKAGE TYPE E) ........................................ , .................................. 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) ............................................. Derate Linearly at 8 mW;oC to 300 mW
For TA = -55 to +100°C (PACKAGE TYPE F, H) ....................................................................... 500 mW
For TA = +100 to +125°C (PACKAGE TYPE F, H) ......................................... Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) .......................................................................... 400 mW
............... Derate Linearly at 6 mW;oC to 70 mW
For TA = +70 to +125°C (PACKAGE TYPE M) .................. .
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE F, H .......................................................................................... -55 to +125°C
PACKAGE TYPE E, M .......................................................................................... -40 to +85°C
STORAGE TEMPERATURE (T"g) ................................................................................. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ..................................................... +265°C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only .................................................................................. +300°C
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
MIN.
MAX.
UNITS
Supply-Voltage Range (For TA = Full Package-Temperature Range) Vee:'
2
6
V
DC Input or Output Voltage V" Va
a
Vee
V
-40
-55
+85
+125
°C
a
a
a
1000
500
400
ns
Operating Temperature TA:
CD74 Types
CD54 Types
Input Rise and Fall Times t" tf
at 2 V
at 4.5 V
at 6 V
'Unless otherwise specified, all voltages are referenced to Ground.
14
1A
13
1B
1Y
2Y
2A
2B
GND
3
12
4
11
5
10
9
8
vcc
4B
4A
4Y
3Y
3B
3A
TOP VIEW"
TERMINAL ASSIGNMENT
92CS-39841
______________________________________________________________________
601
TERMINAL ASSIGNMENT
Technical Data __________________________________________________________
CD54/74HC7266
STATIC ELECTRIC CHARACTERISTICS
CD54/74HC7266
CHARACTERISTIC
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
TEST
CONDITIONS
+25°C
-401
+85°C
-551
+125°C
1.5
-
-
1.5
3.15
-
-
3.15
6
4.2
-
-
4.2
2
-
4.5
-
6
2
-
-
1.9
-
4.5
4.4
-
6
5.9
-
-
5.9
-
4.2
0.5
-
0.5
1.35
-
1.35
1.8
-
1.8
-
1.9
-
4.4
-4
4.5
3.98
-
-
3.84
V,H
-5.2
5.48
-
-
5.34
V'L
or
6
2
-
-
0.1
-
0.1
0.02
4.5
-
-
0.1
-
0.1
6
-
-
0.1
-
0.1
V,L or
4
4.5
-
-
0.26
V,H
5.2
6
6
-
0.26
±0.1
2
Vee or
Gnd
Vee or
Gnd
-
-
-
6
-
-
0
~
-
-
-
1.5
3.15
V,L or
-0.02
UNITS
Min. Typ. Max. Min. Max. Min. Max.
2
V,H
Icc
54HC
TYPE
-
VOL
I,
74HC
TYPE
4.5
V,H
TTL Loads
SWITCHING CHARACTERISTICS (Vee
V
V'L
or
VOH
CMOS Loads
Quiescent Device Current
Vee
mA
V'L
TTL Loads
Input Leakage Current
10
V
V,H
CMOS Loads
Low-Level Output Voltage
V,
74HC/54HC
TYPES
-
V
0.5
1.35
-
1.9
4.4
5.9
3.7
5.2
-
V
V
0.1
0.1
0.33
-
0.4
0.4
40
-
-
-
20
-
±1
V
0.1
0.33
-
V
1.8
V
±1
/1 A
/1 A
= 5 V, TA = 25°C, Inpul If, If = 6 ns)
CHARACTERISTIC
Propagation Delay, Any Input
t PLH
CL
pF
TYPICAL VALUES
54174HC
UNITS
15
9
ns
-
33
pF
tPHL
Power Dissipation Capacitance'
Cpo
'C po is used to determine the dynamic power consumption. per gate.
Po = Vee' fi (CPO+CL) where:
f, = input frequency.
CL = output load capacitance.
Vee = supply voltage.
SWITCHING CHARACTERISTICS (CL = 50 pF, Inpul I" If
= 6 ns)
25°C
CHARACTERISTIC
Propagation Delay
Output Transition Time
Input Capacitance
t PLH , t pHL
hLH, hHL
C,
-40°C 10 +85°C -55°C 10 +125°C
HC
Vcc
74HC
54HC
Min.
Max.
Min.
Max.
2
4.5
6
-
-
145
29
25
-
-
115
23
30
2
4.5
6
-
75
15
13
-
-
-
95
19
16
-
-
10
-
10
-
Min.
UNITS
Max.
150
35
30
ns
ns
-
110
22
19
-
10
pF
-
602 _________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC7266
92CS-38430R2
Fig. 2 - Transition times and propagation delay times.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 603
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC40102, CD54/74HCT40102
CD54/74HC40103, CD54/74HCT40103
File Number
1596
High-Speed CMOS Logic
PE _ _ _,
PL
TI
8-Stage Synchronous Down Counters
MR
PO
40102 - 2-Decade BCD Type
40103 - 8-Bit Binary Type
,
PARALLEL i
(LOAD)
DATA
P7
I
Type Features:
TC
CP
•
•
Synchronous or asynchronous preset
Cascadable in synchronous or ripple mode
92CS-38323
FUNCTIONAL DIAGRAM
The RCA-CD54/74HC401 02, 401 03 and CD5417 4HCT 40102,
40103 are manufactured with high speed silicon gate
technology and consist of an 8-stage synchronous down
counter with a single output which is active when the
internal count is zero. The 40102 is configured as two
cascaded 4-bit BCD counters, and the 40103 contains a
single 8-bit binary counter. Each type has control inputs for
enabling or disabling the clock, for clearing the counter to
its maximum count, and for presetting the counter either
synchronously or asynchronously. All control inputs and
the TC output are active-low logic.
In normal operation, the counter is decremented by one
count on each positive transition of the CLOCK (CP).
Counting is inhibited when the TE input is high ....I):1e TC
output goes low when the count reaches zero ifthe TE input
is low, and remains low for one full clock period.
When the PE input is low, data at the PO-P7 inputs are
clocked into the counter on the next positive clock transition
regardless of the state of the"ITinpul. When theP[ input is
low, data at the PO-P7 inputs are asynchronously forced
into the counter regardless of the state of the PE, TE, or
CLOCK inputs. Input PO-P7 represent two 4-bit BCD words
for the 40102 and a single 8-bit binary word for the 40103.
When the MR input is low, the counter is asynchronously
cleared to its maximum count (99,0 for the 40102 and 22510
for the 401 03) regardless of the state of any other input. The
precedence relationship between control inputs is indicated
in the truth table.
If all control inputs except TE are high at the time of zero
count, the counters will jump to the maxim um count, giving
a counting sequence of 100 or 256 clock pulses long.
The 40102 and 40103 may be cascaded using the TEinput
and the TC output, in either a synchronous or ripple mode.
Family Features:
•
•
•
•
•
•
•
Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85 0 C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
Alternate Source is Philips/Signetics
CD54HCICD74HC Types:
2 to 6 V Operation
High Noise Immunity: ML ~ 30%, N,H ~ 30% of Vee;
@ Vee ~ 5 V
CD54HCTICD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L ~ 0.8 V Max., V ,H ~ 2 V Min.
CMOS Input Compatibility
I, <:: 1 flA @ VOL, VO H
These circuits possess the low power consumption usually
associated with CMOS circuitry, yet have speeds
comparable to low power Schottky TTL circuits and can
drive up to 10 LSTTL loads.
The CD54HC40102, 40103, and CD54HCT40102, 40103 are
supplied in 16-lead hermetic dual-in-line ceramic packages
(F suffix). The CD74HC40102, 40103 and CD74HCT40102,
40103 are supplied in 16-lead dual-in-line plastic packages
(E suffix) and in 16-lead dual-in-line surface mount plastic
packages (M suffix). Both types are also available in chip
form (H suffix).
604 ____________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC40102, CD54/74HCT40102
CD54/74HC40103, CD54/74HCT40103
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) .................................................................................. -0.5 to + 7 V
DC INPUT DIODE CURRENT, I'K (FOR V, < -0.5 V OR V, > Vee +O.SV) ...................................................... ±20mA
DC OUTPUT DIODE CURRENT, 10K (FOR Vo < -0.5 V OR Vo > Vee +O.SV) .................................................. ±20mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee + 0.5V) ................................................... ±25mA
DC Vee OR GROUND CURRENT (leel ................................................................................... ±50mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60°C (PACKAGE TYPE E) ............................................................................ 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) ............................................... Derate Linearly at 8 mW;oC to 300 mW
For TA = -55 to +100° C (PACKAGE TYPE F, H) ......................................................................... 500 mW
For T. = +100 to +125°C (PACKAGE TYPE F, H) .......................................... Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +70°C (PACKAGE TYPE M) ......................................................................... 400 mW
For T. = +70 to +125°C (PACKAGE TYPE M) ................ ,..........................
Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H .......................................................................................... -55 to +125°C
PACKAGE TYPE E, M .......................................................................................... -40 to +85° C
STORAGE TEMPERATURE (T",) ................................................................................. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ...................................................... +265°C
Unil inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacling lead tips only ....................... .
RECOMMENDED OPERATING CONDITIONS:
For maximum reliability, nominal operating condilions should be selected so that operation is always wilhin the
following ranges:
LIMITS
CHARACTERISTIC
UNITS
MIN.
MAX.
Supply-Voltage Range (For TA = Full Package Temperature Range) Vee:'
CD54/74HC Types
CD54174HCT Types
DC Input or Output Voltage VI, Vo
2
6
V
4.5
5.5
V
a
VCC
V
Operating Temperature TA:
CD74 Types
-40
+85
°C
CD54 Types
-55
+125
°C
a
a
a
1000
ns
500
ns
400
ns
Input Rise and Fall Times, tr, If
at 2 V
at 4.5 V
at 6 V
..
'Unless otherWise specified, all voltages are referenced to Ground.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 605
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC40102, CD54/74HCT40102
CD54/74HC40103, CD54/74HCT40103
----------TO OTHER?
FLIP FLOPS
Fig. 1 - Logic diagram for the CD54/74HC/HCT40102.
TRUTH TABLE
CONTROL INPUTS
PRESET
MODE
-MR
-PL
-PE
1
1
1
1
Inhibit Counter
1
1
1
0
Count Down
1
1
0
X
1
0
X
X
0
X
X
X
-TE
ACTION
Synchronous
Preset On Next Positive
Clock Transition
Preset Asynchronously
Asynchronously
Notes:
1. 0 = Low Level
1 = High Level
X = Don't Care
2. Clock Connected to
Clock Input.
3.
4.
Clear to Maximum Count
Synchronous operation: Changes Occur on
Negative-to-Positive Clock Transitions.
Load Inputs: 40102 BCD: MSD = P7, P6, P5, P4 (P7 is MSB)
LSD = P3, P2, P1, PO (P3 is MSB)
40103 Binary: MSB =P7, LSB =PO
606-----------------------------------------------------------
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC40102, CD54/74HCT40102
CD54/74HC40103', CD54/74HCT40103
-------------
TO OTHER 7
FLIP FLOPS
8~
~
16V--
92CL-3832!:>RI
Fig. 2 - Logic diagram for the CD54/74HC/HCT40103.
J
J
CP
-
PL
Tl
PE
TE
EL
R
R
_
r.--CL
cp~CL
PE~PE
Flip-Flop detail.
________________________________________________________ 607
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54n4HC40102, CD54n4HCT40102
CD54/74HC40103, CD54/74HCT40103
STATIC ELECTRICAL CHARACTERISTICS
CD7 4HC401 02-401 03/CD54HC401 02-401 03
CD74HCT40102-40103/CD54HCT40102-40103
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85°C
+125°C
+85"C
+125"C
CHARACTERISTICS
UNITS
+25°C
V,
10
Vee
V
mA
V
High-Level
Input Voltage
V,"
Low-Level
Input Voltage
V"
High-level
Output Voltage
V"
Va"
CMOS Loads
or
-0.02
V,"
Min Typ Max Min Max Min Max
2
1.5
-
4.5
3.15
-
6
4.2
-
-
1.5
-
1.5
-
3.15
-
3.15
-
4.2
-
4.2
-
0.5
-
-
Low-Level
Output Voltage
CMOS Loads
2
-
-
0.5
4.5
-
-
1.35 -
1.35 -
1.35
6
-
-
1.8
-
1.8
-
1.8
1.9
-
-
1.9
-
-
-
4.4
-
1.9
4,4
4.4
-
-
2
-
V
-
-
0.8
-
0.8
-
0.8
V
or
6
5.9
-
-
5.9
-
5.9
-
V,"
4.5
4.4
-
.-
4.4
-
4.4
-
V
V,"
4.5
3.98
-
-
3.84
-
3.7
-
V
V"
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
0.1
-
±1
-
±1
pA
5.5
-
-
8
-
80
-
160
pA
-
100 360
-
450
-
490
pA
V"
V"
-
-
3.84
-
3.7
V,"
-5.2
6
5.48
-
-
5.34
-
5.2
-
2
0.1
-
0.1
-
0.1
4.5
-
-
0.02
-
0.1
-
0.1
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V,"
-
0.26
-
0.33
-
0.4
or
0.33
-
0.4
V,"
cr
V"
or
4
4.5
-
V,"
5.2
6
-
0.26
Any
Voltage
Vee
Vee
or
Gnd
2
to
3.98
or
Icc
-
5.5
2
6
-
-
~01
-
±1
-
±1
Between
Vee and
Gnd
Gnd
Quiescent Device
Current
-
4.5
-
4.5
Input Leakage
I,
2
to
5.5
4.5
or
Min Typ Max Min Max Min Ma.
4.5
-
0.5
V"
Current
V
-4
V,"
TTL Loads
V
or
V"
Vo,
Vee
~
V"
TTL Loads
+25"C
V,
Vee
0
6
-
-
8
-
80
-
160
or
Gnd
Additional
Quiescent Device
4.5
Current per
Vee -2.1
Input Pin:
1 Unit Load
to
5.5
ll.lcc
-
-
For Vee +0.5 V) ........................................................ ±20 rnA
DC OUTPUT DIODE CURRENT. 10K (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) ................................................... ±20 rnA
DC DRAIN CURRENT. PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) ..................................................... ±35 rnA
DC Vee OR GROUND CURRENT. (lee) .......................•..............................................•.............• ±70 rnA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60·C (PACKAGE TYPE E) ............................................................................... 500 mW
For T. = +60 to +85·C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/·C to 300 mW
For T. = -55 to +100· C (PACKAGE TYPE F. H) ........................................................................... 500 mW
ForT. = +100 to +125·C (PACKAGE TYPE F. H) ............................................. Derate Linearly at 8 mW/·C to 300 mW
ForT. = -40 to +70·C (PACKAGE TYPE M) ............................................................................... 400 mW
For T. = +70 to +125·C (PACKAGE TYPE M) ................................................. Derate Linearly at 6 mW/·C to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F. H ............................................................................................. -55 to +125·C
PACKAGE TYPE E. M ............................................................................................. -65 to +150·C
STORAGE TEMPERATURE (T."') .................................................................................... -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ........................................................ +265·C
Unit inserted into a PC Board (min. thickness 1/16 in .• 1.59 mm)
with solder contacting lead tips only ................................................................................... +300· C
RECOMMENDED OPERATING CONDITIONS
For maximum reliability. nominal' operating conditions should be selected so that operation is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For TA-Full Package Temperature Range)
Vcc:·
CD54174HC Types
CD54/74HCT Types
DC Input or Output Voltage. V,. Vo
Operating Temperature. T A:
CD74 Types
CD54 Types
Input Rise and Fall Times. t,.t,:
at 2 V
at 4.5 V
at 6 V
LIMITS
UNITS
MIN.
MAX.
2
4.5
6
5.5
V
Vce
V
0
-40
-55
+85
+125
0
0
0
1000
500
400
·C
ns
·Unless otherwise specified. all voltages are referenced to Ground.
________________________________________________________________ 615
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC40104
CD54/14HCT40104
STATIC ELECTRICAL CHARACTERISTICS
CD74HC40104/CD54HC40104
CD74HCT40104/CD54HCT40104
TEST
74HC/54HC
74HC
54HC
TEST
74HCT/54HCT
74HCT
54HCT
CONDITIONS
TYPE
TYPE
TYPE
CONDITIONS
TYPE
TYPE
TYPE
-401
-551
-401
-551
+85°C
+125'C
+85°C
+125'C
CHARACTERISTICS
UNITS
+2SoC
V,
10
Wee
V
rnA
V
High-Level
Input Voltage
V"
High-Level
Output Voltage
yp ~a •. Min ~a. Min
1.5
-
4.5 \:l,15
-
V"
Vo"
CMOS Loads
or
-0.02
V,"
~
..
6
4.2
-
2
-
-
4.5
6
-
-
- 1.5 - 1.5 - tJ, 15 - tJ, 15 - 4.2 - 4.2 0.5 0.5 0.5
1.35 1.35 1.35
1.8 1.8 1.8
1.9 1.9 - 4.4 - 4.4 5.9 5.9 -
2
V,"
Low-Level
Input Voltage
Min
-
@usDriver)
Low-Level
Output Voltage
CMOS Loads
5.9
4.5 3.98
-
-
p.B4
-
3.7
-
or
-
-
5.34
-
5.2
-
V,"
0.1
-
0.1
-
0.1
V"
-
0.1
-
0.1
-
0.1
or
-
0.1
-
0.1
-
0.1
V,"
-
0.26
-
0.33
-
0.4
or
0.33
-
. 0.4
V,"
V,"
-7.8
6
.48
2
0.02
4.5
6
-
2
-
2
-
V
-
-
O.B
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
4.5
3.98
-
-
3.B4
-
3.7
-
V
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
pA
5.5
-
-
8
-
BO
-
160
pA
-
100 360
-
450
-
490
/JA
-
-
±0.5 -
±5
-
±10
/J A
to
V"
or
V,"
V"
6
4.5
-
(Bus Driver)
V,"
7.B
6
-
0.26
Input Leakage
Any
Voltage
Vee
or
Gnd
6
-
-
±0.1
-
±1
-
±1
Between
Vee and
Gnd
Vee
or
Gnd
-
5.5
6
or
Icc
-
4.5
-
-
V"
Quiescent Device
Current
2
to
5.5
V"
V,"
I,
Min Typ Ma. Min Max Min Max
4.5
-
1.9
TTL Loads
Current
V
4.4
-6
or
Vee
V
2
or
V"
Yo,
V,
4.5
V"
TTL Loads
+25'C
0
6
-
-
8
-
BO
-
160
Vee
or
Gnd
Additional
Quiescent Device
4.5
Current per
Vee -2.1
Input Pin:
1 Unit Load
3-State
to
5.5
Alec·
V"
Leakage
or
Current
V,"
Vo=
Vee
rGnd
6
-
-
±0.5
-
V"
±5
-
±10
or
5.5
V,"
·For dual-supply systems theoretical worst case (VI = 2.4 V. Vee = 5.5 V) .specification is 1.8 mA.
616 _______________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC40104
CD54/74HCT40104
HCT Input Loading Table
Input
OE
DSR, DSL, DO-D3
S1,S2
CP
Unit Loads'
1.4
0.3
0.7
0.3
·Unit load is t. Icc limit specified in Static Characteristics
Chart, e.g., 360 fJA max. @ 25° C.
SWITCHING CHARACTERISTICS (Vcc=5 V, TA=25° C, Input t"t,=6 ns)
CHARACTERISTIC
SYMBOL
Maximum Frequency (Cl = 15 pF)
Propagation Delay: (Cl = 15 pF)
CP to an
fMAX
tpLH
tPHl
tpLl
Output Disable Time
TYPICAL
VALUES
HC
HCT
50
56
17
18
14
18
12
12
84
85
UNITS
MHz
ns
tPHZ
tPZl
tPZH
Cpo
Output Enable Time
.
Power Dissipation Capacitance
pF
·C PO is used to determine the dynamic power consumption, per device.
PD=C PD Vee' fi +:1: (C L Vee' fo) where: f;=input frequency
fo=output frequency
C l =output load capacitance
Vee=supply voltage
Pre-requisite for Switching Function
CHARACTERISTIC
Maximum Clock
Frequency
Clock Pulse
Width
Setup Times Dn,
DSL, D8R, 81,
and SO to Clock
Hold Times Dn,
D80, D81, 81,
and 80 to Clock
SYMBOL
fMAX
tw
tsu
tH
VCC
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-55° C to +125° C
25°C
-40° C to +85° C
HC
HCT
74HCT
54HC
.54HCT
UNITS
74HC
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
4
6
5
17
MHz
25
20
19
28
22
22
33
26
120 80
100 16
20
20
24
24
16
14
17
20
80
100 120 16
ns
20
30
25
24
20
20 14
17
2
2
2
2
2
2
2
2
2
2
2
2
-
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 617
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC40104
CD54/74HCT40104
SWITCHING CHARACTERISTICS CCL=50 pF, Inpull,;i,=6, ns)
CHARACTERISTIC
Propagation Delay
CPtoQn
SYMBOL
tpLH
tPHL
Output Disable
Time
tpLl
tPHZ
Output Enable
Time
tPZL
tPZH
Output Transition
Time
3-State Output
Capacitance
Input Capacitance
trLH
tTHL
VCC
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
25°C
-40° C 10 +85° C
-55°C 10 +125°C
74HC
74HCT
54HC
HC
HCT
54HCT UNITS
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max_
200 - 250 300 40
42
50
53
60
63
34
43
51
- 219 - 263
175 35
44
44
55
53
66
37
45
30
ns
150 188 225 30
30
38
38
45
45
26
32
38
75
60
90
12
12
15
15
18
1!!
10
13
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Co
-
20
-
20
-
20
-
20
-
20
-
20
C,
-
10
-
10
-
10
-
10
-
10
-.
10
INPUT
LEVEL
00-03,OSL,
OSR,Sl,S2
1'-_ _--'1
Vs
~S
Vs
~tH(H)
tHIL)
CP
pF
tsulH)
\
Vs
92CS-3B515RI
92CS- 38514
Fig. 2 - Output enable and disable times.
Input Level
Switching Voltage, Vs
Fig. 3 - Setup and hold times.
I
I
I
54n4HC
VCC
50%VCC
I
I
I
54/74HCT
3V
1.3V
618 ________________________________________________________________
Technical Data
File Number
CD54/74HC40105
1834
CD54/74HCT40105
High-Speed CMOS Logic
,----'-'--,,3
QO
DO
01
12
03
SHIFT IN
~15
QI
Q2
D2
10
14
Q3
DATA-OUT
READY
DATA-IN
READY
VCC=IS
GND""B
92CS-27262R3
FUNCTIONAL DIAGRAM
4-Bit x 16-Word FIFO Register
Type Features:
• Independent asynchronous inputs
and outputs
• Expandable in either direction
• Reset capability
• Status indicators on inputs
and outputs
• 3-state outputs
• Shift-out independent of
3-state control
The RCA-CD54174HC40105 and CD54174HCT40105 are
high-speed silicon-gate CMOS devices that are compatible,
except for "shift-out" circuitry, with the RCA-CD40105B.
They are low-powerfirst-in-first-out (FIFO) "elastic" storage
registers that can stofe 16 four-bit words. The 40105 is
capable of handling input and output data at different
shifting rates. This feature makes it particularly useful as a
buffer between asynchronous systems.
Each word position in the register is clocked by a control
flip-flop, which stores a marker bit. A "1" signifies that the
position's data is filled and a "0" denotes a vacancy in that
position. The control flip-flop detects the state of the
preceding flip-flop and communicates its own status to the
succeeding flip-flop. When a control flip-flop is in the "0"
state and sees a "1" in the preceding flip-flop, it generates a
clock pulse that transfers data from the preceding fourdata
latches into its own four data latches and resets the
preceding flip-flop to "0". The first and last control flip-flops
have buffered outputs. Since all empty locations "bubble"
automatically to the input end, and all valid data ripple
through to the output end, the status of the first control
flip-flop (DATA-IN READY) indicates if the FIFO is full, and
the status of the last flip-flop (DATA-OUT READY) indicates
if the FI FO contains data. As the earliest data are removed
from the bottom of the data stack (the output end), all data
entered later will automatically propagate (ripple) toward
the output.
Loading Data
Data can be entered whenever the DATA-IN READY (DIR)
flag is high, by a lowto high transition on the SHIFT-IN (SI)
input. This input must go low momentarily before the next
word is accepted by the FIFO. The DIR flag will go low
momentarily, until the data have been transferred to the
second location. The flag will remain low when all 16-word
locations are filled with valid data, and further pulses on the
SI input will be ignored until DIR goes high.
Applications:
• Bit-rate smoothing
• CPU/terminal buffering
• Data communications
• Peripheral buffering
• Line printer input buffers
• Auto-dialers
• CRT buffer memories
• Radar data acquisition
Family Features:
• Fanout (Over Temperature Range):
Standard Outputs - 10 LSTTL Loads
Bus Driver Outputs - 15 LSTTL Loads
• Wide Operating Temperature Range:
CD74HC/HCT: -40 to +85°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• CD54HC/CD74HC Types:
2 to 6 V Operation
High Noise Immunity: ML = 30%, MH = 30% of Vee,
@ Vee = 5 V
• CD54HCT/CD74HCT Types:
4.5 to 5.5 V Operation
Direct LSTTL Input Logic Compatibility
V,L = 0.8 V Max., V,H = 2 V Min.
CMOS Input Compatibility
I, :S 1 pA @ VOL, VOH
Unloading Data
As soon as the first word has rippled to the output, the
data-out ready output (DOR) goes HIGH and data of the
first word is available on the outputs. Data of other words
can be removed by a negative-going transition on the shiftout input (SO). This negative-going transition causes the
DOR signal to go LOW while the next word moves to the
output. As long as valid data is available in the FIFO, the
DOR signal will go high again, signifying that the next word
is ready at the output. When the FIFO is empty, DOR will
remain LOW, and any further commands will be ignored
until a "1" marker ripples down to the last control register
and DOR goes HIGH.
___________________________________________________________________ 619
Technical Data
CD54/74HC40105
CD54/74HCT40105
If during unloading SI is HIGH, data on the data inputofthe
FIFO is entered in the first location.
Master Reset
A high on the MASTER RESET (MR) sets all the control
logic marker bits to "0". DOR goes low and DIR goes high.
The contents of the data register are not changed, only
declared invalid, and will be superseded when the first word
is loaded. Thus, MR does not clear data within the register
but only the control logic. If the shift-in flag (SI) is HIGH
during the master reset pulse, data present at the input (DO
to 03) are immediately moved into the first location upon
completion of the reset process.
3-State Outputs
I n order to facilitate data busing, 3-state outputs (00 to 03)
are provided on the data output lines, while the load
condition of the register can be detected by the state of the
DOR output:-6. HIGH on the 3-state control flag (output
enable input OE) forces the outputs into the high-impedance
OFF-state mode. Notethatthe shift-out signal, unlike that in
the RCA-CD40105B, is independent of the 3-state output
control. In the CD40105B, the 3-state control must not be
shifted from High to Low when the shift-oulsignal is Low
(data loss would occur). In the high-speed CMOS version
this restriction has been eliminated.
Cascading
The 40105 can be cascaded to form longer registers simply
by connecting the DIR to SO and DOR to SI. In the
cascaded mode, a MASTER RESET pulse must be applied
after the supply voltage is turned on. For words wider than
four bits, the DIR and the DOR outputs must be gated
together with AND gates. Their outputs drive the SI and SO
inputs in parallel, if expanding is done in both directions
(see Figs. 3 and 4).
The CD54HC40105 and CD54HCT40105 are supplied in
16-lead hermetic dual-in-line frit-seal ceramic packages (F
suffix). The CD74HC40105 and CD74HCT40105 are supplied in 16-lead dual-in-line plastic packages (E suffix) and
in 16-lead dual-in-Iine surface-mount plastic packages (M
suffix). Both types are also available in chip form (H suffix).
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to'ground) ......................................................................................-0.5 to +7 V
DC INPUT DIODE CURRENT, ho (FOR V, < -0.5 V OR V, > Vee +0.5 V) ....................................................... ±20 mA
DC OUTPUT DIODE CURRENT, 100 (FOR Vo < -0.5 V OR Vo > Vee +0.5 V) ................................................... ±20 mA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < Vo < Vee +0.5 V) ..................................................... ±25 mA
DC Vee OR GROUND CURRENT (Icc) ...................................................................................... ±50 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 tei +60° C (PACKAGE TYPE E) ............................................................................... 500 mW
For T. = +60 to +85° C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/o C to 300 mW
For T. = -55 to +IOO°C (PACKAGE TYPE F, H) ........................................................................... 500 mW
For T. = +100 to +125°C (PACKAGE TYPE F, H) ............................................. Derate Linearly at 8 mW/oC to 300 mW
For T. = -40 to +70° C (PACKAGE TYPE M) .............................................................................. 400 mW
For T. = +70 to +125°C (PACKAGE TYPE M) ................................................. Derate Linearly at 6 mW/oC to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H ............................................................................................. -55 to +125°C
PACKAGE TYPE E, M .............................................................................................. -40 to +85° C
STORAGE TEMPERATURE (T".) .................................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for lOs max. . .................................................... +265° C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................................................................................... +300·C
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation Is always within
the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For T.=Full Package Temperature Range)
Vee:"
CD54174HC Types
CD54174HCT Types
DC Input or Output Voltage, V" Vo
Operating Temperature, T.:
CD74 Types
CD54 Types
Input Rise and Fall Times, t"t,:
at 2V
at 4.5 V
at 6 V
LIMITS
UNITS
MIN.
MAX.
2
4.5
0
6
5.5
Vee
-40
-55
+85
+125
°C
0
0
0
1000
500
400
ns
V
V
·Unless otherwise specified, all voltages are referenced to Ground.
620 ___________________________________________________________________
Technical Data
CD54/74HC40105
CD54/74HCT40105
INPUT
BUFFERS
,--------,
OUTPUT
BUFFERS
DE
01 R
51
DO
01
02
03
16
15
14
13
12
4
5
11
10
9
GNO
Vee
so
DOR
ao
a,
a2
a3
MR
TOP VIEW
92CS-27286R2
MASTER
RESET
IMR)
TERMINAL ASSIGNMENT
Fig. 1 - Functional block diagram.
*
a
*
5
a
ao
4
> ______..,LATCHES~----------------____1
LA~~~~S~---------------1LATtHE ~-----------1guS;:~~
~----------------~14KL1 r-------------~ Ll.
Ll
POSITIONS 2-15
POSITION 1
POSITION 16
BuFFERS
12
01
11
02
10
03
* "s" OVERRIDES"R"
** "R" OVERRIDES "s"
Fig. 2 - Logic diagram.
___________________________________________________________________ 621
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC40105
CD 54/74H CT40105
STATIC ELECTRICAL CHARACTERISTICS
CD74HC4010s/CDs4HC4010s
CD74HCT40105/CDs4HCT401os
TEST
74HC/S4HC
74HC
s4HC
TEST
74HCT/s4HCT
74HCT
s4HCT
CONDITIONS
TYPES
TYPES
TYPES
CONDITIONS
TYPES
TYPES
TYPES
-401
-551
-401
-551
+85°C
+12S·C
+8S·C
+12S·C
CHARACTERISTIC
UNITS
+25°C
V,
10
Vee
V
mA
V
High-Level
Input Voltage
Low-Level
Input Voltage
VOL
High-Level
Output Voltage
1.5
-
4.5 3.15
-
2
V'H
VOL
VOH
CMOS Loads
or
-0.02
V'H
Min Typ Ma. Min MI' Min MI.
6
4.2
2
4.5
-
6
-
2
1.9
4.5
4.4
-
6
5.9
Low-Level
Output Voltage
CMOS Loads
-
3.15
4.2
-
4.2
0.5
-
0.5
-
0.5
1.35
-
1.35
-
1.35
1.8
-
1.8
1.9
-
1.9
-
4.4
4.4
-
or
5.9
-
V'H
V'H
VOL
1.8
-
-
5.9
-
1.5
2
-
2
-
V
to
-
-
0.8
-
0.8
-
0.8
V
4.5
4.4
-
-
4.4
-
4.4
-
V
-
-
3.84
-
3.7
-
V
VOL
3.84
-
3.7
V'H
-5.2
6
5.48
-
-
5.34
-
5.2
-
2
0.1
-
0.1
-
0.1
4.5
-
-
0.02
-
0.1
-
0.1
-
0.1
or
6
-
-
0.1
-
0.1
-
0.1
V'H
or
4.5 3.98
4.5
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.26
-
0.33
-
0.4
V
5.5
-
-
±0.1
-
±1
-
±1
pA
5.5
-
-
8
-
80
-
160
pA
-
100 360
-
450
-
490
pA
-
±5
-
±10
pA
VOL
or
4
4.5
-
-
0.26
-
0.33
-
0.4
or
V'H
5.2
6
-
-
0.26
-
0.33
-
0.4
V'H
6
-
-
±0.1
-
±1
-
±1
Any
I,
Vee
Gnd
Quiescent
lee
or
Voltage
Between
Vee & Gnd
Vee
Vee
0
6
-
-
8
-
80
-
160
or
Gnd
Gnd
Additional
4.5
Quiescent Device
Vee -2.1
Current per input
to
5.5
t.lee
3-State Leakage
Current
-
VOL
-
or
pin: 1 unit load
-
5.5
-
Input Leakage
Device Current
2
4.5
-
3.98
VOL
Current
to
5.5
4.5
or
Min Typ Ma. Min Ma. Min Ma.
4.5
-
-4
V'H
TTL Loads
V
or
VOL
VOL
V
3.15
VOL
TTL Loads
Vee
-
1.5
-
+25°C
V,
10'
VOL
Vo=Vcc
or'
or
. VIH
VOL
6
-
-
±0.5
Gnd
-
±5
-
±10
or
5.5
-
-
±0.5
V'H
*For dual-supply systems theoretical worst case (VI = 2.4 V, Vee = 5.5 V) specification is 1.8 rnA.
HCT Input Loading Table
Input
Unit Loads"
OE
SI, SO
On
0.75
0.4
0.3
1.5
MR
·Unit Load is alec limit specified in Static Characteristics
Chart, e.g., 360/lA max. @ 25° C.
622 ______________________________________________________________
__
_________.____________ Technical Data
CD54/74HC40105
CD54/74HCT40105
SWITCHING CHARACTERISTICS (VCC = 5 V, TA = 25°C, Input tr,t, = 6 ns)
SYMBOL
CHARACTERISTIC
Propagation Delay
CL
(pF)
TYPICAL
HC
HCT
15
35
18
18
32
83
15
35
18
18
32
83
UNITS
tPLH
tPHL
MR to DIR, DaR
so to an
15
SI to DIR
so to DaR
Maximum SI, SO Frequency
Power Dissipation Capacitance"
tPHL
f max •
Cpo
15
-
ns
MHz
pF
"Cpo is used to determine the dynamic power consumption, per package.
PD Cpo Vee' f, + L (CL Vee' fo) where: f, input frequency
=
=
fo = output frequency
CL = output load capacitance
Vee
=
supply voltage
PRE-REQUISITE FOR SWITCHING FUNCTION
CHARACTERISTIC
SI Pulse Width:
HIGH or LOW
tw
Fig. 6
SO Pulse Width
HIGH or LOW
tw
Fig. 7
DIR Pulse Width
HIGH or LOW
tw
Fig.6
DaR Pulse Width
HIGH or LOW
tw
Fig. 7
MR Pulse Width
HIGH
tw
Fig. 5
Removal Time
MR to SI
tREM
Fig. 12
Setup Time
On to SI
tsu
Fig. 13
Hold Time
On to SI
tH
Fig. 13
Maximum Pulse
fMAX
Frequency
Figs. 6, 7
SI, SO
TEST
CONDITIONS
Vcc (V)
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
LIMITS
-40° C to +85° C
HC
HCT
74HC
74HCT
Min. Max. Min. Max. Min. Max. Min. Max.
80
100 16
20
20
16
14
17
120 150 24
16
20
30
20
26
200 250 40
50
40
50
34
43
200 - 250 40
40
50
50
43
34
120 150 24
30
30
24
20
26
50
65
10
15
13
19
9
11
5
5
5
0
0
5
5
5
125 155 31
25
25
31
21
26
3
2
15
15
12
12
18
14
25°C
-55° C to +125° C
UNITS
54HC
54HCT
Min. Max. Min. Max.
120 24
24
20
180 24
36
31
300 60
60
51
300 ns
60
60
51
180 36
36
31
75
15
22
13
5
0
5
5
190 38
38
32
2
10
10
MHz
12
-
________________________________________________ 623
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HC40105
CD54/74HCT40105
SWITCHING CHARACTERISTICS (CL
=50 pF, Input t"t, =6 n8)
LIMITS
CHARACTERISTIC
Propagation Delay,
MR to DIR DOR
Propagation Delay,
tPHL
tPLH
FiQ.5
tpHL
SI to DIR
Propagation Delay,
FiQ.6
tPHL
-
SO to DOR
Propagation belay,
SO to an
Propagation Delay!
Ripple thru Delay
SI to DOR
Propagation Delay!
Ripple thru Delay
SO to DIR
Propagation Delay!
Ripple thru Delay
SI to an
3-State Output
Enable
OE to an
3-State Output
Disable
OE to an
Output Transition
Time
Fig. 7
tpHL
tpLH
Fig. 8
tpLH
Fig. 9
t plH
FiQ.10
tPHL
tPLH
tPZH
tPlL
Fig.11
tpHl
tPLl
Fig. 11
IrHL
ITLH
Fig. 8
Input Capacitance
C,
3-State Output Capacitance
Co
VCC
(V)
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
-
25°C
HC
HCT
Min. Max. Min. Max.
175 35
- 36
30
210 42
42
36
210 42
- 42
36
400 80
80
68
2000 400 400
340 2500 500 500
- 425 1500 300 300
260 150 30
- 35
26
140 28
30
24
75
15
15
13
10
10
15
15
-
-40°C II
74HC
Min. Max.
220
- 44
- 37
265
- 53
45
265
53
- 45
500
100
85
2500
500
- 425
- 3125
625
532
1900
380
330
190
38
33
175
35
30
- 95
19
16
10
15
+8_5°C
-55° C to +125° C
UNITS
74HCT
54HC
54HCT
Min. Max. Min. Max. Min. Max.
265 53
54
- 45 45
315 63
63
- 53 54
315 53
63
63
54
600 100 120 120
102 3000 - 500 - 600 - 600
510 ns
3750 625 750 750
638 2250 380 450 450
380 225 44
45
53
38
210 38
42
45
- 36 110 19
22
- 22 19
10
10
10
pF
15
15
15
-
-
#--------+---------------~
#MASTER RESET pulse must be applied when
cascading by 16 N bits.
92C5-40243
Fig. 3 - Expansion, 4-bits wide by 16 N-bits long.
624 _____________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CD54/74HC40105
CD54/74HCT40105
DATA OUT
READY
B BI T
DATA
B BIT
DATA
DATA'IN
READY
#~~~~~R+-------------~~--~--------~--~
#Pulse must be applied for cascading by 16 N bits.
92CM-28346RI
Fig. 4 - Expansion, B-bits wide by 16 N-bits long using HC/HCT40105.
AC WAVEFORMS
DOR OUTPUT
Vs
92CS-40252
92CS-4025t
Fig. 5 - Waveforms showing the MR input to DIR,
DaR output propagation delays and the
MR pulse width.
Fig. 6 - Waveforms showing the SI input to DIR output
propagation delay. The SI, DIR pulse widths
and SI maximum pulse frequency.
92CS-40254
Fig. 7 - Waveforms showing the So input to DaR
output propagation delay. The SO, DaR
Fig. B - Waveforms showing SO input to On
output propagation delays and
pulse widths and SO maximum
time.
frequency.
_ _ _ _pulse
__
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _output
_ _transition
___
______
625
Technical Data
CD54/74HC40105
CD54/74HCT40105
AC WAVEFORMS (Conl'd)
51 INPUT
r::-'t
so
~~
-r--
INPU~VS
~~
D'ROUTP~VS
DOROUT~VS
92C5-40246
92C5-40241
Fig. 9 - Waveforms showing the SI input to DOR
output propagation/ripple-through delay.
Fig. 10 - Waveforms showing the So input to DIR
output propagation/ripple-through delay.
-rt.vs
~7
OE
MR INPUT
INPUT
51 INPUT
VOL
Vs
VOH
92C5-40249
OUTPUTS
ENABLED
Fig. 12 - Waveforms showing the MR input to SI
input removal time.
92C5-40248
Fig. 11 - Waveforms showing the 3-state enable
and disable times for input OE.
NOTE
THE SHADED AREAS INDICATE WHEN THEINPUT
IS PERMITTED TO CHANGE FOR PREDICTABLE
OUTPUT PERFORMANCE.
92C5-40250
Fig. 13 - Waveforms showing hold and set-up
times for Do input to SI input.
Input Levek
Switching Voltage, Vs
54174HC
Vee
50% Vee
54174HCT
3V
1.3 V
I
I
I
626 ________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Technical Data
CDS4/74HC4010S
CDS4/74HCT4010S
• DATA VALID GOES TO HIGH LEVEL IN ADVANCE OF THE DATA OUT
BY A MAXIMUM OF 38 ns AT Vee = 4.5 V, FOR CL =50 pF ANDTA = 25~C
INPUTS
I
(g~+~~~;:) --fl~_________________________________________________~
SHIFT OUT
I
N PUT READY •
CLEAR OUT)
OUTPUTS OUTPUT READY
(DATA VALID)
~++-++-+~j.I
:l~~~:
1~~I&~~)~------------------------------~--+-+-~~~~-+--~
INPU)
DATA OUTe
*..
(UNKNOWN)
AT VCC = 4.5 V - RIPPLE TIME FROM POSITION 1 TO POSITION 16•
AT Vee =4.5 V· RIPPLE TIME FROM POSITION 16 TO POSITION 1.
92CS- 29233 RI
Fig. 14 - Timing diagram for the CD54/74HC/HCT40105.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 627
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HCU04
File Number 1655
High-Speed CMOS Logic
Hex Inverter
Type Features:
• Typical propagation delay=6 ns @ Vee=5 V
CL=15 pF, TA =25°C, fastest part in QMOS line
• Wide operating temperature range:
CD74HCU04: -40° t to +85° C
• Balanced Propagation Delay and Transition Times
• Significant power reduction compared to LSTTL logic ICs
• Alternate source is Philips/Signetics
3A
3Y
FUNCTIONAL DIAGRAM
AND TERMINAL ASSIGNMENT
The RCA-CD54/74HCU04 unbuffered hex inverter utilizes
silicon-gate CMOS technology to aChieve operating speeds
similar to LSTTL gates with the low power consumption of
standard CMOS integrated circuits. These devices are
especially useful in crystal oscillator and analog applications. Figs. 4 and 5 are supplied as design information for
the above applications.
• CD54HCU04/CD74HCU04 types:
2 to 6 V operation
High noise immunity: ML=20%,
MH=30% of Vee; @ Vee=5 V
• CMOS input compatibility
I, :5 1 p.A @ VOL, VO H
The CD54HCU04 is supplied in 14-lead hermetic dualin-line ceramic P!lckages (F suffix). The CD74HCU04 is
supplied in 14-lead dual-in-line plastic packages (E suffix).
The CD74HCU04 is supplied in 14-lead dual-in-line surface
mount plastic packages (M suffix). These types are also
available in chip form (H suffix).
nA
---t>--
nY
92CS-3"8387RI
92CS-38375RI
Fig. 2 - Inverter schematic.
Fig. 1 - Logic diagram.
628 ___________________
~
__________________________________________
_____________________________________________________________ TechnicaIData
CD54/74HCU04
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE, (Vee):
(Voltages referenced to ground) ...................................................................................... -0.5 to +7 V
DC INPUT DIODE CURRENT, 1,K (FOR V, < -0.5 V OR V, > Vee +0.5 V) ............•.......................................... ±20 rnA
DC OUTPUT DIODE CURRENT, 10K (FOR V. < -0.5 V OR V. > Vee +0.5 V) ................................................•.. ±20 rnA
DC DRAIN CURRENT, PER OUTPUT (10) (FOR -0.5 V < V. < Vee +0.5 V) .•...............................................•.. ±25 rnA
DC Vee OR GROUND CURRENT, (lee) •..•.......................................................•...................•..... ±50 rnA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60· C (PACKAGE TYPE E) .................................................... , .......................... 500 mW
For T. = +60 to +85· C (PACKAGE TYPE E) .................................................. Derate Linearly at 8 mW/· C to 300 mW
For T. = -55 to +100· C (PACKAGE TYPE F, H) ........................................................................... 500 mW
ForT. = +100 to +125·C (PACKAGE TYPE F, H) ............................................. Derate Linearly at 8 mW/·C to 300 mW
For T. = -40 to +70· C (PACKAGE TYPE M) ............................................................................. 400 mW
For T. = +70 to +125·C (PACKAGE TYPE M) ................................................ Derate Linearly at 6 mW/·C to 70 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE F, H .......•.••.•............................................................................... -55 to +125·C
PACKAGE TYPE E. M .............................................................................................. -40 to +85·C
STORAGE TEMPERATURE (T... ) .................................................................................... -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ........................................................ +265·C
Unit inserted into a PC Board (min. thickness 1/16 in., 1.59 mm)
with solder contacting lead tips only ................................................................................... +300·C
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation Is always within
the following ranges:
LIMITS
CHARACTERISTIC
UNITS
MIN,
MAX.
2
0
6
Vee
V
V
-40
-55
+85
+125
·C
0
0
0
1000
500
400
ns
Supply-Voltage Range (For TA-Full Package Temperature Range)
Vee:·
DC Input or Output Voltage, V" Vo
Operating Temperature, TA:
CD74 Types
CD54 Types
Input Rise and Fall Times, t"t,:
at2 V
at 4.5 V
at 6 V
·Unless otherwise specified, all voltages are
referp~ced
to Ground.
_________________________________________________________________ 629
Technical Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54/74HCU04
STATIC ELECTRICAL CHARACTERISTICS
CHARACTERISTIC
High-Level
Input Volt"ge
V'H
Low-Level
Input Voltage
V'L
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
VOL
Input Leakage
Current
I,
Quiescent
Device
Current
Icc
CD54HCU04
CD74HCU04
+25°C
Min.
Max.
1.7
3.6
4.8
0.3
0.8
1.1
1.8
4
5.5
3.98
.5.48
0.2
0.5
0.5
0.26
0.26
TEST CONDITIONS
VI
10
VCC
V
mA
V
2
4.5
6
2
4.5
6
2
V'L
or
-0.02
4.5
6
V'H
-4
Vee or
4.5
Gnd
-5.2
6
2
V'L
or
0.02
4.5
6
V'H
4
4.5
Vee or
Gnd
5.2
6
Vee
or
6
Gnd
Vee
or
0
6
Gnd
-
-
-
-
-
-
-
-
-
CD74HCU04
CD54HCU04
_40° C to +85° C 55°C to +125°C UNITS
Max.
Min.
Max.
Min.
1.7
1.7
3.6
3.6
4.8
4.8
0.3
0.3
0.8
0.8
1.1
1.1
1.8
1.8
4
4
V
5.5
5.5
3.7
3.84
5.34
5.2
0.2
0.2
0.5
0.5
0.5
0.5
0.33
0.4
0.4
0.33
±0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
±1
±1
IlA
-
-
2
-
20
40
SWITCHING CHARACTERISTICS (Vee = 5 V, T A = 25° C, Input ·t" t, = 6 n5)
CHARACTERISTIC
SYMBOL
TYPICAL
VALUES
CD54/74U04
UNITS
Propagation Delay, Data Input to Output Y (Fig. 3)
(CL=15 pF)
tPLH
tpHL
5
ns
Power Dissipation Capacitance"
CPD
14
pF
"CPO is used to determine the dynamic power consumption, per inverter when:
Po=Vcc· fi (Cpo + Cd where f,=input frequency
CL=output load capacitance
Vcc=supply voltage
SWITCHING CHARACTERISTICS (CL =50 pF, Input t"t,=6 ns)
CHARACTERISTIC
SYMBOL
VCC
Propagation Delay
I nput to Output
(See Fig. 3)
Transition Times
(Fig. 3)
tPLH
tpHL
2
4.5
6
2
4.5
6
Input Capacitance
bLH
hHL
C,
-
25°C
CD54174HCU04
Min.
Max.
70
14
12
-
-
-
75
15
13
_40° C to +85° C
CD74HCU04
Max.
Min.
90
18
15
95
19
16
See Fig. 5
-
-
-55° C to +125° C
CD54HCU04
Min.
Max.
105
21
18
110
22
19
UNITS
-
-
ns
-
630 _________________________________________________________________
_____________________________________________________________ TechnicaIData
CD54/74HCU04
92CS-38377
Fig. 3 - Propagation delay and transition times.
DESIGN INFORMATION FOR CRYSTAL OSCILLATOR
AND ANALOG APPLICATIONS
25
,
22.5
AMBIENT tEMPERATURE I fA j- 2S·C
'
20
~
11.5
~
15
~
AMIBIENT TEMPERATURE (TAl o Z5°C
65
f
~
.
~
[!]
[!]
50
V,
0-2 V
VOO'3V, V,
0-3\1
v, v,
v, VI
v,
0-4 V
VOO=2 V,
ill
VOD'4
45
ill
VOO'S
~
40
[i]
VOO'6
~
10
INPUT PIN 5 CONDITIONS
55
z
u
~ 12.5
60
v,
35
30
~
z
,0
15
10
2.5
4
INPUT VOLTAGE (VII-V
Fig. 4 - Typical inverter supply current as
a function of input voltage.
INPUT VOLTAGE (VIN)-II
Fig. 5 - Input capacitance as a function of input voltage.
___________________________________________________________________ 631
632 ___________________________________________________________________
Preview Data.
The types shown in the Preview Data section contain information on a product under
development. RCA reserves the right to change or discontinue this product without
notice.
____________________________________________________________________ 633
Preview Data
CD54HC137/74HC137
CD54HCT137/74HCT137
AO
16
AI
15
A2
LE
4
OEI
OEO
6
14
Y,
13
Y2
12
Y3
"
10
Y7
GND
Vee
Yo
9
Y4
"5V6
92C5-38293
TERMINAL ASSIGNMENT
3 to 8 Decoder/Demultiplexer,
with Address Latch
TRUTH TABLE
INPUTS
OUTPUTS
LE OEo OE,
Y,
A2 A1
Ao
Yo
Y2
Y3
Y4
Ys
Y6
Y7
X
X
X
X
X
H
H
H
H
H
H
H
H
H
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
L
H
H
H
H
L
L
H
H
H
H
H
L
L
L
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
H
H
L
H
L
L
H
H
H
L
H
H
H
H
H
L
H
L
H
L
L
H
H
H
L
H
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
L
H
H
H
H
H
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
L
H
L
H
H
L
X
H
X
X
H
L
*
• = Depends upon the address previously applied while LE was at a
logic low.
Typical Switching Characteristics (VCC
CHARACTERISTICS
Propagation Delay Time
A to Y
OE, to Y
OEo to Y
LE to Y
tPHL
tPLH
tPHL
tPLH
tpHL
tPLH
tPHL
tpLH
= 5V, GND = OV, tr = tf = 6ns)
15pF
50pF
54174HC/HCT
20
14
15
11
16
12
21
14
54174HC/HCT
23
16
18
12
18
14
24
17
UNITS
ns
634 ______________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Preview Data
3-to-8 Line Decoder/Demultiplexer
with Address-Latches
CD54/74HC237
CD54/74HCT237
TRUTH TABLE
INPUTS
AO
AI
A2
LE
4
OEI
CEo
Y7
S
GND
IS
IS
14
13
12
II
10
9
LE
vee
Yo
YI
Y2
Y3
Y4
Ys
Ys
92CS-38295
X
X
L
L
L
L
L
L
L
L
H
OEo OEl
X
L
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
H
L
OUTPUTS
A2
Al
Ao
Vo
Vl
V2
V3
V4
X
X
L
L
L
L
X
X
L
L
X
X
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
H
H
H
H
L
L
L
H
H
H
L
H
L
H
L
H
X
X
X
.
Vs
L
L
L
L
L
L
L
H
L
L
v.
L
L
L
L
L
L
L
L
H
L
V7
L
L
L
L
L
L
L
L
L
H
• = Depends upon the address previously.
TERMINAL ASSIGNMENT
applied while LE was at a logic low.
Typical Switching Characteristics (VCC
CHARACTERISTICS
=5V, GND = OV, tr = tf = 6ns)
15pF
50pF
54/74HC/HCT
54114HC/HCT
Propagation Delay Time
A to Y
tPHL
tPLH
15
20
18
22
OE l toY
tPHL
tPLH
12
17
14
19
OEo to Y
tPHL
tpLH
16
17
18
19
LEto Y
tPHL
tPLH
16
21
18
24
UNITS
ns
______________________________________________________________ 635
Preview Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD54HC597/74HC597
CD54HCT597/74HCT597
B
16
e
15
A
14
SA
SERIAL SHIFT!
13
12
7
GNO
e
Vee
PARALLEL LOAD
STORAGE CLOCK
11
SHIFT CLOCK
10
RESET
'--------'
8-Bit Serial- or Parallel
Input/Serial-Output Shift
Register with Input Storage
QH
92C5-38310
TERMINAL ASSIGNMENT
Typical Switching Characteristics (VCC
=5V, GND = OV, tr = tf = 6ns)
15pF
50pF
54174HC/HCT
54/74HC/HCT
UNITS
CHARACTERISTICS
Propagation Delay Time
Shift Clock to QH
tPHL. tPLH
14
17
Storage Clock to QH
tPHL. tPLH
21
24
Parallel Load to QH
tPHL. tPLH
14
17
ns
636 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
Preview Data
CD54/74HC4016, CD54/74HCT4016
14
IN/OUT
SIG A
13
QUTilN
12
OUTIIN
SIG B
11
IN/OUT
Quad Bilateral Switch
Vee
CONT A
CONT 0
IN/OUT
SIG D
CO NT B
10 OUTIIN
CONTC
OUTIIN
GND
IN/OUT
StG C
92CS36667
TERMINAL ASSIGNMENT
Dynamic Electrical Characteristics @ TA =25°C, VCC =5 V, t r, tf =6 ns
Symbol
tPHLltPLH
RON
Test Conditions
Typical
Units
Propagation Delay:
Sw. Input to Output
CL = 15 pF
CL = 50 pF
3
5
ns
ns
Turn·On Delay
and Turn·Off Delay·
CL = 15 pF
CL = 50 pF
6
8
ns
ns
200
Q
Parameter
On·State Resistance
RL = 1 KQ
CL = 50 pF
:
·Turn·On measured 50% to 50%, Turn·Off measured 50% to 10%.
___________________________________________________________________ 637
Preview Data _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Quad Analog Switch/Multiplexer/
CD54HC4316/74HC4316
CD54HCT4316/74HCT4316 Demultiplexer with Separate
Analog and Digital Power Supplies
X.
I.
y.
IS
YB
Vee
A ONIOFF
CONTROL
DON/OFF
XB
13
"
CONTROL
Xo
8 ONIOFF
CONTROL
12
Yo
~8~f2~r
11
Ye
ENA B LE
10
Xc
GNO
VEE
92C$-38311
TERMINAL ASSIGNMENT
Typical Switching Characteristics (VCC
= 5V, GND = 0, tr = tf = 6ns)
15pF
50pF
54174HC/HCT
54/74HC/HCT
CHARACTERISTICS
UNITS
Propagation Delay Time
Switch "Turn-ON"
tpZL. tpZH
12
14
Switch "Turn-OFF"
tPHZ. tPLZ
12
14
ns
CD54HC4351/74HC4351
CD54HCT4351/74HCT4351
20 Vec
Y.
Y7
FUNCTION TABLE
19 Y2
Y6
NC
a-Channel Analog Multiplexer/
Demultiplexer with Address Latch
3
18 Yl
4
17 Yo
Control Inputs
16 Y3
Y5
E1
E2
7
8
9
VEE
GND 10
15 50
14 NC
13 5
12 1
52
11 IT
Enable 1 Enable 2
H
l
H
l
H
l
H
l
l
92CS-40544
TERMINAL ASSIGNMENT
L
l
l
H
Select
ON Switches
(LE= HI*
l
YO
Yl
Y2
Y3
rc-e---A
l
H
H
H
H
l
l
l
l
H
H
H
H
l
X X X
l H
H l
H H
L
L
H
H
l
H
l
H
Y4
Y5
Y6
Y7
None
X = Don't Care
·When Latch Enable is low, the Channel-Select
data is latched. and the switches do not change
state.
638 ____________________________________________
~
___
Preview Data
CD54HC4352/74HC4352.
Dua14-Channel Analog Multiplexerl
CD54HCT4352/74HCT4352 Demultiplexer with Address Latch·
FUNCTION TABLE
2Yo
20 Vee
2Y2
19 1Y2
NC
18 IY,
2Z
4
17 lZ
2Y3
5
16 1Yo
Select
Enable 1 Enable 2
~:
2Yl
1Y3
NC
13 So
EI
E2
12 51
11 IT
VEE
GND
Control Inputs
10
B
A
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
L
X
X
ON Switches
(LE=HI*
lYO
1Y1
2YO
2Yl
1Y2
1Y3
2Y2
2Y3
None
~-~
X= Don't Car.
• When Latch Enable is low, the Channel-Select
92CS-40545
data is latched, and the. switc/ies do' nol
change state:
TERMINAL ASSIGNMENT
CD54 HC4353/74HC4353
CD54HCT4353/74HCT4353
Triple 2-Channel'Analog
MultiplexerIDemultiplexer
with Latch
TRUTH TABLE
INPUTS
20 Vee
19 2Z
18
IZ
2Y1
2Yo
NC
E1
E2
CHARACTERISTICS
Propagation Delay Time
Switch Input to Output
Switch Turn "ON"
(RL = 1k )
Switch Turn "OFF"
LE
82 S1
X
X
X
X
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
X
L
j
X
SV, GND
CONDITIONS
H
X
17 1Y,
3Yl
X
L
16 IYO
3Z
H
L
15 So
3Yo
L
H
14 NC
Ej"
8
L
H
13 SI
E2
9
H
L
12 S2
VEE
10
H
L
II IT
GND
L
H
92CS-40546
L
H
L
H
L
H
TERMINAL ASSIGNMENT
X
X
Typical Switching Characteristics (VCC 4
tPHL, tPLH
VEE
(V)
GND
-5
tPHL. tPLH
GND
-5
tPHL. tpLH
GND
-5
ON CHANNELS
80
NONE
X
X
X
X
1Yo
3Yo
L
2Yo
L
3Y,
1Yo
2Yo
L
H
2Y 1
3Yo
L
H
1Yo
3Y,
2Y,
H
H
1Yo
1Y,
L
3Yo
L
2Yo
1Y,
3Y,
L
H
2Yo
1Y,
H
L
2Y,
3Yo
1Y,
3Y,
H
2Y,
H
X
Last Channels "On"
X
X
X Selected Channels Latched
- OV, tr - tf - 6ns)
1SpF
SOpF
UNITS
S4174HC/HCT
54174HC/HCT
3
2
14
14
17
14
5
4
17
17
19
17
ns
--------------------------------------------------------_________ 639
Preview Data - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9-Bit X 64-Word FIFO
Register; 3-State
GNo
GNo
olR
SI
DO
01
02
03
04
Os
06
07
1
CD54/74HC7030
. CD54/74.HCT7030
28 Vee
27 MR
2
3
4
26 so
25 00R
5
24 Qo
6
7
8
~~
9
20 Q3
Q4
QI
21 Q2
10
11
:: Qs
12
17 Q6
13
08
GNo 14
16 Q7
Q8
15 OE
92CS-40537
TERMINAL ASSIGNMENT
•. Dynamic Electrical Characteristics @ T A
Symbol
Parameter
Propagation Delay:
tpHL/tpLH
SI. SO to DIR. DOR
f max
.
Maximum Clock Frequency
=25° C, VCC =5 V, t r, tf =6 ns
Typical
Test' Conditions
Units
HC
HCT
= 15pF
CL = 50 pF
14
16
ns
17
19
ns
=15 pF
40
40
MHz
CL
CL
. 640 ____-------------------------------------------------------------
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Preview Data
..9-Bit Bus Transceiver
with latch
CD54/74HC7038
, CD54/74HCT7038
LE
23 DEIB-Al
22 80
AO
AI
A2
A3
A4
Features:
• 48 mA Sink Current
• Inverting and Non-Inverting Data Paths
24 Vee
DEIA-Bl
4
21 81
5
20 B2
19
B3
lB
B4
17
85
16
86
15 B7
14 8B
6
7
AS
9
A6
A7 10
AS 11
GND 12
13 POLARITY
92CS-40538
TERMINAL ASSIGNMENT
TRUTH TABLE
CONTROL INPUTS
OPERATION
OECA-B)
OECB-A)
POLARITY
L
H
H
On to On
L
H
L
H
L
H
On to On
B data to A
H
L
L
B data to A
H
H
X
Isolation
Dynamic Electrical Characteristics @ TA = 25°C, VCC = 4.5 V, tr, tf = 6 ns
Symbol
tpZL/tpLZ
tpHL/tpLH
' Parameter
AorA- B
B orB-A
CD54/74HC7046
CD54/74HCT7046
Typical
Test Conditions
Units
HC
HCT
CL = 15 pF
23
23
ns
CL = 50 pF
26
26
ns
CL = 15 pF
10
10
ns
CL = 50 pF
13
13
ns
Phase-locked loop with VCO
and In-lock Detector
(Voltage Controlled Oscillator)
Feature:
• 11 MHz typ, @ Vcc=5 V (output signal)
Vee
It.! LOCK
SIGNAL
PHASE caMP
I OUT
,.
Vcc
~
COMP IN
I.
SIGNAL IN
veo
OUT
13
PHASE COMP
OUT
INHIBIT
12
RZ TO GND
Clll)
"
RITOGND
C1(21
10
n
DEMODULATOR
OUT
veo
GND
IN
92C5-)8938
CI
r.....,---+<~-------4 ~~;s
FILTER
*C3
TERMINAL ASSIGNMENT
92C$-39036
Phase-locked loop with In-lock detector block diagram.
_______________________________________________________________________ 641
642 __________~-------------------------------------------------------
Advanced CMOS Logic
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 643
Advanced CMOS Logic _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Advanced CMOS Logic, ACL, is the next step forward in the
evolution of CMOS logic. It matches bipolar FASr in speed,
performance and logic type output drive, but at CMOS
power levels.
Just as HCIHCT high-speed CMOS logic became an industry standard competing with LSTTL, ACL is expected to
become an industry standard offered by a number of the
leading CMOS logic suppliers. A JEDEC committee is currently working on specifications for a standardization of
54/74 AC/ACT devices.
Featuring < 3-ns gate propagation delays, ACL is the fastest
CMOS logic yet available. (By contrast, the standard propa-
gation delay for CMOS logic is 95 ns, and for high-speed
CMOS logic, 9 ns.) ACL can operate at more than 150 MHz.
Output drive capability is 24 mA, compared with 6 mA for
HC/HCT. This capability enables ACL to drive transmission
lines, yet still generate the voltages necessary to operate the
receiving logic devices safely.
Because of its low power consumption, ACL is potentially
more reliable than bipolar logic. This quality should make
ACL the technology of choice in a number of applications,
including computers, peripherals, and telecommunications,
and in portable and military equipment.
'FAST is a trademark of Fairchild Semiconductor Corp.
ACL TYPES.
PLASTIC'
CD74AC/ACTOOE,M
CD74AC/ACT02E,M
CD74AC/ACT04E,M
CD74AC/ACT05E,M
CD74AC/ACT08E,M
CD74AC/ACT10E,M
CD74AC/ACT20E,M
CD74AC/ACT32E,M
CD74AC/ACT74E,M
CD74AC/ACT86E,M
CD74ACIACT1 09E,M
CD74ACI ACT112E,M
CD74ACIACT138E,M
CD74ACIACT139E,M
CD74AC/ACT151E,M
CD74AC/ACT153E,M
CD74ACI ACT157E,M
CD74ACI ACT158E,M
CD74ACI ACT161 E,M
CD74ACI ACT163E,M
CD74ACIACT164E,M
CD74AC/ACT174E,M
CD74ACIACT175E,M
CD74AC/ACT191E,M
CD74AC/ACT193E,M
CD74AC/ACT238E,M
CD74AC/ACT240E,M
CD74AC/ACT241 E,M
CD74AC/ACT244E,M
CD74AC/ACT245E,M
CD74AC/ACT251 E,M
CD74AC/ACT253E,M
CD74AC/ACT257E,M
CD74AC/ACT258E,M
CD74AC/ACT273E,M
CD74AC/ACT280E,M
CD74AC/ACT283E,M
CD74AC/ACT299E,M
CD74AC/ACT323E,M
CD74AC/ACT373E,M
CD7 4ACI ACT37 4E, M
CD74AC/ACT533E,M
CD74AC/ACT534E,M
CD74AC/ACT540E,M
CD74AC/ACT541 E,M
CD74AC/ACT573E,M
CD74AC/ACT574E,M
CD7 4ACI ACT646E, M
CD74AC/ACT648E,M
CD74AC/ACT7060E,M
CD7 4ACI ACT7202E, M
CD74AC/ACT7402E,M
CERDIP'
CD54ACI ACTOOF
CD54ACIACT02F
CD54ACIACT04F
CD54ACI ACT05F
CD54ACI ACT08F
CD54ACI ACT1 OF
CD54ACI ACT20F
CD54ACI ACT32F
CD54AC/ACT74F
CD54ACI ACT86F
CD54ACI ACT1 09F
CD54ACI ACT112F
CD54ACI ACT138F
CD54ACI ACT139F
CD54ACI ACT151 F
CD54ACIACT153F
CD54ACI ACT157F
CD54ACI ACT158F
CD54ACI ACT161 F
CD54ACI ACT163F
CD54ACI ACT164F
CD54ACI ACT17 4F
CD54AC/ACT175F
CD54AC/ACT191F
CD54ACI ACT193F
CD54ACI ACT238F
CD54AC/ACT240F
CD54ACI ACT241 F
CD54ACI ACT244F
CD54ACI ACT245F
CD54ACI ACT251 F
CD54ACI ACT253F
CD54AC/ACT257F
CD54ACI ACT258F
CD54ACIACT273F
CD54ACIACT280F
CD54ACIACT283F
CD54AC/ACT299F
CD54AC/ACT323F
CD54AC/ACT373F
CD54AC/ACT374F
CD54AC/ACT533F
CD54AC/ACT534F
CD54ACI ACT540F
CD54ACIACT541 F
CD54ACIACT573F
CD54AC/ACT574F
CD54ACI ACT646F
CD54ACIACT648F
CD54ACIACT7060F
CD54AC/ACT7202F
CD54AC/ACT7402F
• Consult your local Sales Office for availability
time frame and other details.
DESCRIPTION
PINS
Quad 2-lnput NAND Gate
Quad 2-lnput NOR Gate
Hex Inverter/Buffer
Hex Inverter/Buffer with Open-Drain Outputs
Quad 2-lnput AND Gate
Triple 3-lnput NAND Gate
Dual 4-lnput NAND Gate
Quad 2-lnput OR Gate
Dual D-Type Flip-Flop w/SET and RESET
Quad 2-lnput EXCLUSIVE-OR Gate
Dual J-K Flip-Flop w/SET and RESET
Dual J-K Flip-Flop w/SET and RESET
3-to-8 Line Decoder/Demultiplexer, Inverting
Dual 2-of-4 Line Decoder/Demultiplexer
8-lnput Multiplexer
Dual 4-lnput Multiplexer
Quad 2-lnput Multiplexer
Quad 2-lnput Multiplexer, Inverting
Synchronous 4-Bit Binary Counter, Asynchronous Reset
Synchronous 4-Bit Binary Counter, Synchronous Reset
8-Bit Serial-In Parallel-Out Shift Register
Hex D-Type Flip-Flop w/RESET
Quad D-Type Flip-Flop w/RESET
Synchronous 4-Bit Binary Up/Down Counter
Synchronous 4-Bit Binary Up/Down Counter
3-to-8 Line Decoder/Demultiplexer
Octal Buffer Line Driver, 3-State, Inverting
Octal Buffer Line Driver, 3-State
Octal Buffer Line Driver, 3-State
Octal Bus Transceiver, 3-State
8-lnput Multiplexer, 3-State
Dual 4-lnput Multiplexer, 3-State
Quad 2-input Multiplexer, 3-State
Quad 2-Line to 4-Line Data Selector
Octal 0- Type Flip-Flop w/RESET
8-Bit Odd/Even Parity Generator/Checker
4-Bit Full Adder w/Fast Carry
8-Bit Universal Shift Register, 3-State
8-Bit Universal Shift Register, 3-State (with Synchronous Reset)
Octal Transparent Latch, 3-State
Octal 0- Type Flip-Flop, 3-State
Octal Transparent Latch, 3-State, Inverting
Octal D-Type Flip-Flop, 3-State, Inverting
Octal Buffer Line Driver, 3-State, Inverting
Octal Buffer Line Driver, 3-State
Octal Transparent Latch, 3-State
Octal 0- Type Flip-Flop, 3-State
Octal Bus Transceiver/Register, 3-State
Octal Bus Transceiver/Register, 3-State, Inverting
14-Stage Counter with Oscillator
1024 x 9-Bit Parallel In-Out FIFO
65 x 5-Bit FI Fa
14
14
14
14
14
14
14
14
14
14
16
16
16
16
16
16
16
16
16
16
14
16
16
16
16
16
20
20
20
20
16
16
16
16
20
14
16
20
20
20
20
20
20
20
20
20
20
24
24
20
28
18
'Package Suffix:
E - Dual-in-Line Plastic
F - Dual-in-Line Frit-Seal Ceramic
M - Surface Mount
644 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Application Notes
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 645
Application Notes _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Power Consumption in
QMOS Logic Circuits
aMOS, RCA's high-speed CMOS-logic technology, offers
users the best features of both CMOS and TTL technologies:
the low-power consumption of CMOS and the fast speeds
associated with LSTTL. This Application Note focuses on
the primary aMOS feature, low power consumption. The
causes of quiescent and dynamic power dissipation in HC
and HCT aMOS devices are discussed. The formulas
needed to compute the power dissipation in aMOS devices
are presented along with sample calculations. A comparison
is made of aMOS, LS, and ALS logic types relative to power
dissipation.
The significant reduction in power consumption provided
by a aMOS logic system compared with the equivalent
LSTTL or ALSTTL counterpart design is the primary reason
that aMOS is destined to be chosen for new designs and to
replace LSTTL or ALSTTL parts in many existing designs.
The replacement of LSTTL devices with HCT aMOS types 1
achieves power savings in existing designs where decreased
power consumption and dissipation are a distinct advantage.
In new designs, only aMOS logic lends itself to batteryoperated portable equipment, such as portable (lap-held)
personal computers, and the switch to aMOS is the major
trend in PCs using all-CMOS RAMs, ROMs, and peripherals.
Ali-aMOS designs can be powered down to 2-volts standby,
increasing battery life. In nonportable designs, aMOS and
CMOS LSI logic are also preferred to significantly reduce,
in order of priority, cost, size, and weight. Cost reduction is
the result of savings in the cost of supply regulators, the
elimination of cooling fans and heat sinks, etc.
An equally powerful motivating force behind the use of
logic components that dissipate lower power, such as
aMOS, is the proven component and equipment reliability
enhancement. The junction temperature of the ICs, as well
by R. Funk and B. Heinze
as the temperature of other equipment components
(resistors and capacitors), is much reduced, thereby
lengthening life. aMOS failure rates are currently measured
at .0015%/1000 hours at 60% UCL for operation at +55°C.
Power consumption in a logic IC must be considered in
both of the IC's operating modes, i.e., under static and
dynamic conditions. aMOS devices consume only minute
amounts of power under static (quiescent) conditions,
making power consumed in the dynamic state the major
contributor to total power consumption. TTL devices, on
the other hand, consume significant amounts of power in
the quiescent state, so much in fact, that power consumption
in the dynamic state can be masked at frequencies as high
as 20 MHz, depending on device complexity. At higher
frequencies, the power consumed by TTL devices increases
proportionately. Since integrated circuits typically spend a
significant percentage of their time either in the quiescent
state or operating at average frequencies below 2 MHz,
aMOS devices can provide significant and often dramatic
power savings.
QUIESCENT POWER CONSUMPTION
The quiescent power consumption of a logic IC is measured
when the system input voltage, V'N, equals the device
supply voltage, Vee, or is at ground potential. Fig. 1 (a) is
used to illustrate this discussion. In tt.) quiescent state,
either the PMOS or NMOS transistor is fully off, and ideally
no direct MOS transistor-channel path exists between Vee
and ground. In reality, however, thermally generated
minority-charge carriers present in all reverse-biased diode
junctions, Fig. 1 (b), allow a very small power-supply leakage
current to flow between Vee and ground. In aMOS data
sheets, this quiescent leakage current is specified as Icc.
OUTPUT
INPUT
(0 )
*
I NHERENT IN MANUFACTURING
PROCESS
(b)
92CS-38289
Fig. 1 - (a) Simple QMOS inverter circuit, (b) simple QMOS inverter circuit with input and output ESD protective diodes.
ICAN-7315
646 _________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Appllcatlon Notes
Three factors affect the value of Icc and, therefore, the
power dissipation of a device:
Temperature:-Increasing temperature causes an increase
in Icc because the minority charge carriers in the reversebiased diode junctions of QMOS devices are thermally
generated.
.1 ICC
OF He
Device Complexity:-MSI devices will consume more power
than SSI devices because there exists a proportionally
greater reverse-biased diode-junction area.
Vcc:-The minority-charge carriers are linearly related to
reverse junction voltage.
Table I shows the JEDEC industry standards for 54/74
HC/HCT high-speed CMOS devices, and illustrates the
effect of temperature and device complexity on Icc at the
maximum recommended HC operating voltage, Vee: 6 V. At
Vee: 2 V, Icc is approximately 1/3 the val ue shown at Vee: 6
V. Typical Icc values are well under the maximum specified
values.
Another factor that may add to quiescent, or dc, power
consumption is the through current caused by both the
PMOS and NMOS transistors of the input stage, Fig. 1 (a),
being on, at least to some degree, at the same time. For HC
devices,' where the switching transition occurs at a nominal
Vecl2 (see Fig. 2(a)). there is no through current and, hence,
no added dc power consumption. That is, with V,L and V,H
voltage levels (low-level and high-level input voltages,
respectively) at the inputs, either the PMOS or the NMOS
transistor of the HC input stage is completely off. However,
for HCT devices, where the switching transition occurs at a
nominal 1.3 volts, Fig. 2(b), there is a through-current
component when an input high-voltage level of under 4
volts is applied to an input. With this amount of voltage
applied, the NMOS transistor is fully on and the PMOS
transistor not fully off. This is the situation in an HCT device
when, in a QMOS/TTL interface, the input voltage of the
QMOS device isthe VOH(high-level output voltage) of a TTL
family device. The 3.5-volt typical VOH output voltage will
fully turn-on the QMOS input NMOS transistor (Fig. 1) but
not fully turn-off the PMOS transistor. The current flow that
results is specified as fl.lee in QMOS HCT data sheets.
Computing HC Quiescent-Power Consumption
Quiescent power consumption in an HC device is extremely
low, typically under 10 microwatts. The fl.lee plays no part
because HC I/O levels are completely compatible: VOL and
VOH worst-case specifications are 0.1 and Vee - 0.1 volt, very
close to ground and Vee, respectively. Fig. 2(a) illustrates
that no Icc will flow with these VOL and VOH voltage levels
imposed, However, if inputs are driven beyond V,L and V,H
toward the switching voltage (centered typically at 2.3
volts), appreciable Icc will flow. Such a high-current situation
exists when an attempt is made to drive an HC input with a
.6 ICC
VOLTS
OF Her
(bI
Fig. 2 - (a) HC input, CMOS interface, (b) HCT input,
TTL interface.
TTL output. For example, with a TTL VOH level of 3 volts
driving an HC input, not only would a logic error exist, but
several milliamperes of Icc would flow. To overcome this
problem, an external pull-up resistor could be used, as
shown in Fig. 3, but the resistor would cause significant
additional system power consumption because it would
have to be kept small in value in order to keep system speed
high. RCA HCT QMOS devices are the preferred solution
when interfacing CMOS with TTL logic.
In power-critical applications, such as portable batteryoperated equipment or equipment operating in a batterypowered stand-by mode, HC quiescent power consumption
may be a significant component of battery drain. The
following formula is used to compute HC quiescent power
consumption:
Pde
:
Veclee
(1)
where Vee is dependent upon the particular application, and
Icc is obtained from the data sheet of the particular device
for a Vee of 6 volts (HC types). The data sheet value given is
also valid within the nominal 5 V ± 10% supply-voltage
range of HCT types. The value of Icc at Vee: 6 V can be
linearly reduced for any desired Vee voltage; e.g., at Vee: 2
V, use 1/3 of the limits shown in Table I.
Table I - 54174HC Family Characteristics
Symbol
Parameter
Vee
(V)
Icc
Quiescent
Supply Current
SSI
FF
MSI
6
6
6
Temt erature {O C
54HC174HC
74HC
54HC
25
-40 to 85 -55 to 125
Min.
Max. Min. Max. Min. Max.
-
2
4
8
-
20
40
80
-
40
80
160
Units
Test Conditions
f.JA
f.JA
f.JA
V, : Vee or GND
10: 0
___________________________________________________________________ 647
Application Notes _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Vee
Therefore:
SLOWS SPEED
INCREASES POWER DISSIPATION
LSTTL
HCMOS
Pdc = (5 V)(2/lA) + (1.3 mAl '" 6.5 mW
Note that if all of the inputs of an HCTdevice are driven by
HC or equivalent CMOS output levels, only equation (1)
need be used to calculate its static power dissipation. Note
also that if a 50% duty cycle is assumed for input signals, the
average dc power is 3.25 milliwatts for the HCT type. This
figure compares with 35 milliwatts for a 74LS10 IC, and
shows that the HCT device still provides a big savings in
power, even in the worst-case application.
92CS-38285
Fig. 3 - Use of pull-up resistor in LSTTL/HC interface.
Computing HCT Quiescent Power Consumption
Because HCT devices can be substituted for LSTTL devices
and/or mixed with LS, ALS, AS, or FAST-TTL-family ICs in
a system, their consumption of larger amounts of dc power
than HC types is not significant. TTL worst-case output
voltages are: VOL = 0.4 V(max) and VOH = Vcc - 2.1 V(min).
The VOH (or logic 1) voltages result in the Alec current flow
illustrated in Fig. 2(b) and already described above. Note
that only a logic-1 input causes appreciable quiescent
leakage-current flow; a logic-O input (0.4 V(max» is close
enough to ground to turn the NMOS transistor fully off. The
total HCT -device quiescent power consumption is a function
of the number of logic-1 inputs applied at the V,H voltage
level.
QMOS HCT data sheets specify Alec at the worst-case input
voltage of Vec - 2.1 V for Vee ranging from 4.5 volts to 5.5
volts, with normalized limits as shown in Table II. Alec is
further specified on a per-input-pin basis. This method of
specification allows more accurate calculations if all the
functions within a device are not being used or are being
used at different input levels. Forexample, assume that two
gates of an HCT10, a triple 3-input NAND Gate, are being
driven by a TTL device with a 50% duty cycle. Given the
information in Table II, quiescent power dissipation is
calculated as follows:
P dc = Veelee + VceAlee(percent duty cycle high)
(2)
where Alec is calculated on a unit-load basis as follows:
Icc = (360 /lA/unit load) x (0.6 unit loads/input
pin) x (6 input pins)
= 1.3 mA
(3)
DYNAMIC POWER CONSUMPTION
Three factors affect QMOS dynamic power consumption:
Load capacitance - dissipation of output state, Fig. 4.
Internal circuit capacitance
Switching transition currents (when complementary
transistors used in switching are both momentarily
on)
Vec
PMOS
INPUT
NMOS
J
~
1
ICL
92CS-38288
Fig. 4 - Simple QMOS inverter circuit driving a capacitive load.
For power calculation purposes, the load caused by internal
device capacitance and switching transition currents is
represented in one effective capacitance defined and
specified as the C Pd , power dissipation capacitance, the
effective internal device capacitance used for operating-
Table II - QMOS HC/HCT10 Static Electrical Characteristics and HCT Input Loading Table
Characteristic
Test
Conditions
V,
10 Vee
(V) (mA) (V)
QuiVee
escent
or
0
6
Device Gnd
Current
Icc
Quiescent Device
Device Cu rrent
per input pin:
1 unit load
Alec
CD74HC1 O/CD54HC1 0
74HC/54HC
74HC
Series
Series
+25°C
-40/+85°C
54HC
Series
-55/
+125°C
Min. Typ. Max. Min. Max. Min. Max.
-
-
2
-
20
-
40
Test
Conditions
V,
Vce
CD74HCT10/CD54HCT10
74HCT/54HCT
74HCT
Series
Series
+25°C
-40/+85°C
54HCT
Series
-55/
+125°C
Min. Typ. Max. Min. Max. Min. Max.
Vee
or
Gnd
5.5
-
-
Vee-2.1
4.5
to
5.5
-
100
Units
2
-
20
-
40
/lA
360
-
450
-
490
/lA
'For dual-supply systems theoretical worst case (V, = 2.4 V, Vee = 5.5 V) speCification is 1.4 mAo
HCT Input Loading Table
Input
All
Unit Loads·
0.6
'Unit Load is l>lce limit specified in Static Characteristics Chart, e.g., 360 /lA max. at 25 0 C.
648 ____
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ApplleatlonNotes
power calculations. Each of the above power-consuming
factors, along with Cpd , are explained in further detail below.
condition creates a momentary low-resistance path between
Vee and ground, Fig. 6(b). In this transient state, a momentary
dc supply current flows and power is consumed. This lowresistance path is obviously a function of the number of
transitions the device makes as well as the input-signal rise
and fall time. In other words, power loss resulting from
internal device switching is proportional to the input
frequency (as is power loss due to internal capacitance).
Unlike quiescent power consumption, dynamic, or operating-power, consumption is computed in the same way for
both HC and HCT devices. Therefore, throughout this
section, all equations presented are applicable to both HC
and HCT devices.
Internal Capacitance
Power-Dissipation Capacitance
Inherent in any active semiconductor is internal parasitic
capacitance, i.e., capacitance present in diode junctions,
MOS transistor structures, and metal and polysilicon
interconnections. This internal capacitance produces the
same effect on internal active circuits as external capacitive
loads, and varies from one device to another depending on
the complexity of the device.
Since power losses resulting from both net internal device
capacitance and switching transient currents are frequency
dependent, one term representing both factors is used for
practical power-consumption calculations. This term is
specified as Cpd, the no-load power dissi pation capacitance!
C pd is defined for each aMOS device in each data sheet.
Further, it is specified per logic function, that is, for each
gate or flip-flop within a device. This method allows for
more accurate power consumption calculations when logic
functions are operating at different frequencies.
aMOS devices are fabricated by means of a self-aligned
polysilicon gate process (3-micron gate length) to reduce
this internal capacitance. This process minimizes gate-tosource and gate-to-drain capacitances. Junction capacitances, which are proportional to the junction area, are also
reduced because shallower diffusions are utilized.
Since Cpd encompasses both internal capacitance and
switching loads, the internal device operating power per
logic function is:
Fig.5 illustrates the device parasitic capacitance present in
a CMOS inverter.
Ppd = CpdVee2 f
Vee
COMPUTING HC'AND HCTTOTAL POWER DISSIPATION
~----l--1
The formulas for total aMOS power dissipation are a
combination of both static and dynamic power-consuming
states. For HC devices:
it!: -H~
1" ;l:;:
I
(4)
where f is the operating frequency of the function.
(5)
Total HCT power dissipation, when driven by TTL logic, is
computed as follOWS:
+
+
Ptotal = Veclee ll.lccVeeD CpNcc2 f;"
Where D = Percent duty cycle High
I
Yr---- =
+ ClVee2 fout
(6)
For HCT devices driven by HC devices, or at equivalent 1/0
voltage levels, equation (5) is used because the input
voltage is essentially at Vee, not at Vee - 2.1 V.
92CS-3707SR1
Fig. 5 - Parasitic capacitances in a CMOS inverter.
QMOS VERSUS LS AND ALS POWER CONSUMPTION
In any integrated circuit, there exists a balance between
speed and power consumption. LSTTL logic is relatively
fast, but the bipolar circuitry used consumes considerable
amounts of dc power. ALSTTL improves upon LSTTL by
utilizing advanced finer-line geometry designs and ap-
Switching Transients
When the basic aMOS inverter circuit, Fig. 6(a). is switching
states, either from a logic 1 to a logic 0 or vice-versa, both
transistors will be on for a short period of time. This
vcc
VCC
J
INPUT: "VCC/2 F
HC{ R
"1.3v FOR HCT
J+
IC
( 0)
1
( b)
92C5-38390
Fig. 6 - (a) Simple QMOS inverter circuit, (b) equivalent schematic of a QMOS inverter whose
transistors represent a low resistance path between Vee and ground.
~
_____________________________________________________________ 649
Application Notes
propriately finer fabrication techniques. These improvements both increase speed and decrease dc power consumption by about 50% total for both factors.
figure, a 2-input NAND gate is used to illustrate the dc
power consumption versus the typical propagation delay
for a number of technologies.
CMOS devices consume minute amounts of quiescent
power compared to any given TTL bipolar-logic-family
device. However, until the development of the aMOS line of
logic devices, CMOS devices were relatively slow. Now,
aMOS types, by utilizing finer-line design and fabrication
techniques, not only consume the minute amounts of dc
and operating power of a CMOS device (depending on
operating frequency, as previously defined in equations (5)
and (6», but are fast, as described below.
Table III is a compilation of speed/power products, in
picojoules, for two CMOS-logic families and four TTL
bipolar-logic families. In the table, SSI and MSI-complexity
devices and those with complex flip-flop arrangements are
used to illustrate speed/power differences. The major
advantages of the new high-speed aMOS (HCIHCT) logic
families are apparent:
- CMOS logic families have a 103 speed/power advantage
over TTL logic families.
- Maximum dc power savings using CMOS are far greater
for the more complex MSI logic functions. As shown, a
TTLAS160 device consumes 5 x 103 times more dc
power than an HC160.
- aMOS (HC) logic is approximately 10 times faster than
equivalent CMOS devices; but retains the ultra-low dc
power consumption of CMOS.
A popular way to illustrate the differences between IC logic
families and their technologies is shown in Fig. 7. In the
4000B
VCC
CMOS
Cl
HC/HCT
=5 V
= 15 pF
Fig. 8 illustrates the operating power consumption for SSI
through MSI, aMOS, and LS devices. Note from the figures
that CMOS devices realize their true power savings, from dc
to several MHz, depending on device type and complexity .
aMOS devices consume significant power only when
switching, not when idling. TTL's continuous power consumption is the result of the many active bipolar transistors
that must be continuously biased.
• lSTTl
aMOS
AlS
•
3
2
FAST
10 KH
S ECl
• AS•••
10KHECl
0.001 0.1
2
3
5
10
20
AVERAGE de POWER DISSIPATION (mW)
Fig. 7 - Speed/power spectrum for the popular logic technologies.
Fig. 8 also shows that as device complexity increases, the
frequency at which CMOS and TTL devices consume the
same amount of power increases, as would be expected.
Table III - Speed Power Comparison - Major TTL and CMOS Logic Families
Generic
Type
Logic
Family
Max. Prop.
Delay' (ns)
Max. Power
Disslpation 2 (mW)
Speed/Power
Product' (pi)
Gate
CMOS HCOO
CD4011
TTL ALSOO
LSOO
ASOO
FASTOO
18
250
13
15 (15 pF)
4
5
.01
.001
16.5
24
95.7
51
.18
.25
215
363
283
255
FF
CMOS HC74
CD4013
TTL ALS74
LS74
AS74
FAST74
32
300
40 (15 pF)
8.5
8
.022
.006
22
44
88
88
.70
1.8
374
1760
748
704
CMOS HC160
CD40160
TTL ASL160
LS160
AS160
FASl'160
35
400
17
27 (15 pF)
6
10
.044
.028
116
176
220
275
1.5
11.2
1964
4752
1320
2750
MSI
Counters
17
1. Vee = 5 V. C, = 50 pF (15 pF for lS), TA = 25'C, max. high or low state.
2. Vee = 5.5 V - max. dc high or low output conditions.
3. Product of max. prop. delay and max. power dissipation.
650 _________________________________________________________________
Application Notes
(.)
QUAD 2 INPUT NAND GATE
DUAL FLIP· FLOP
(b)
100
100
~
g
Z
~
g
10
Z
0
0
~
~
~
c
'"~
~
10
;::
~
c
0.1
'"~
0.1
TEST CONDITIONS
Vee = 5 V
TA = 25°C
CL
50 pF
(a & a OUTPUTS)
~
0.01
=
0.01
100
lK
10K
lOOK
1M
10M
100M
100
FAEQUENCY (Hz)
lK
10K
10M
1M
100K
FREQUENCY (Hz)
92C5·37087
{'I
92C5·37088
QUAD BUS TRANSCEIVER
(d)
100
1000
10
~
~
z
0
Z
~
0
~
~
~
TEST CONDITIONS
Vee = SV
0.01
'"~
= 25
TA
DC
= 50pF
CL
10
~
0
0.1
C
'"~
100
g
g
~
TEST CONDITIONS
0.100
Vcc=5 V
0.001
TA
=25 0
CL
:SOpF
1M
10M
0.010
0.0001
lK
10K
lOOK
1M
10M
100M
FREQUENCY (Hz)
100
10K
lOOK
100M
FREQUENCY (Hz)
92C5·37088
92C5·37090
Fig. 8 - Power versus supply graphs for the (a) LSIHCOO, (b) LSIHC74, (c) LSIHCT138, and (d) LSIHC243.
aMOS devices also consume more quiescent power as
device complexity increases, but the leakage currents that
cause the power consumption are of such small magnitude
that they can (in most cases) be ignored (see Table I).
The subject figures also illustrate the operating power
differences for one function or n functions in an IC package
operating at the frequencies shown.
The power-consumption characteristics of these different
logic families are easily translated into total system power.
Fig. 9 illustrates the power consumed by the different logic
families in a small logic system (one gate and two flipflops). The figure shows that aMOS substantially outperforms TTL in power consumption at both the device and
the system level.
SOD
B
LS
ALS
i
E
50
B
z
~
....<1
"-
iiic
c:
'"0
;<
"-
REFERENCES
1. The aMOS family consists mainly of two series, the HC,
which features CMOS input-voltage-level compatibility,
and the HCT, which features LSTTL input-voltage-level
compatibility. For a review of these series, see QMOS
High-Speed CMOS Logic ICs, RCA Solid State
DATABOOK SSD-290.
2. See ref. 1 under "Description of aMOS Product Line" for
discussion of C pd •
0·5
a
468
{·o
468
4
{o.o
G B
100
FREQUENCY (MHz)
92CS-38290
Fig. 9
Power consumed by different logic families in a
small logic system.
___________________________________________________________________ 651
Application Notes
Modification of LSTTL Test Programs to Test HCT
High-Speed-CMOS Logic ICs
by R. Funk
The aMOS HCT family of high-speed logic ICs is designed
and specified not only to replace LSTTL devices having the
same type numbers, but to interface with all TTL, CD4000B
CMOS, and aMOS HC logic families. As such, it is indeed
one of the more, and perhaps the most, interface-flexible
logic family. In existing and new-equipment designs where
LSTTL devices are, or could be, used, these devices are
easily replaced by RCA's HCT logic family because of the
several advantages its aMOS technology has over LSTTL:
- Much lower dc and operating-power requirements
- Improved dc noise margin
- Better balance in output current drive and switching
speed
- Much lower input current and three-state output
leakage current in high-impedance state
- Improved reliability because of lower junction temperature
- Wider 74-family operating temperature (-40°C to
+85°C, not LSTTL's O°C to 70°C)
But the switch from LSTTL to aMOS has made it necessary
for test personnel to switch from the testing of LSTTL
functions to the testing of the identical HCT functions; this
Note has been written to make that switch as easy as
possible. The widely used Teradyne J283 test system is
used as a basic frame of reference in this Note; however, the
test information given is applicable to most other test
equipment and bench-test situations.
A few tests (depending on device tested) in the LSTTL test
programs designed to test dc and function on the J283
system are invalid for use with HCT devices, and will
consistently produce erroneous results. These tests are
easily modified and made valid for aMOS general-logiC
types. A few additional tests require modification if bus
drivers and transceivers are to be tested.
Input Clamp Voltage
The HCT input-protection network incorporates a series
resistor that will cause the input clamp voltage (with an
input current of -18 milliamperes) to be much lower than
the -1.5 volts specified for LSTTL. Since the input clamp
voltage is not specified for HC circuits, this test could be
omitted, or changed to have a conservative limit of -5 volts.
This limit assumes a 200-ohm poly-resistor at the input plus
-1.5 volts of diode-to-ground potential.
Output Short-CIrcuIt Current
As shown in Appendix I, an LS02 has an los (short-circuit
output current) of -20 to -100 milliamperes. Test one output
at a time and do not exceed a one-second test-time
duration. For aMOS, make the following current-limit
changes:
Standard Logic Types: -20 mA to -70 mA
Bus Driver Types: -40 mA to -90 mA
Note that the los test is nonstandard for aMOS HC or HCT
types. The standard specified trLH and trHL (transition times,
low-to-high and high-to-Iow) values in aMOS specifications
are a preferred method of directly measuring output speed.
The los limits are considered to be an indirect (and
inaccurate) method of measuring the output sink and
source speed characteristics for a given value of load
capacitance.
HysteresIs (Bus DrIver Types)
Many LSTTL bus-driver types undergo a AV T test using a
0.2-volt-minimum hysteresis limit. For aMOS HC and HCT,
change this minimum to zero volts or bypass this test.
Output-Voltage-Low Test Current (Bus-Driver Types)
LSTTL bus drivers have two specifications for VOL (low-level
output voltage) test current which must be modified as
shown below for aMOS types:
10L
VOL MaxImum
Input Current at V, = 7 V (AppendIx I)
0.4 V
12 mA
0.5 V
24 mA
"Specified on aMOS data sheets
Unlike the LSTTL circuit shown in Fig. 1 (a), HCT circuits
incorporate an input protection network, as shown in Fig.
1 (b). Because of this network, input current will flow if the
input voltage exceeds Vee. Therefore, when testing HCT
types, change the input voltage from 7 volts to Vee. To test
for the exact HCT low-level input leakage current, modify
the input-voltage setting according to the dc characteristics
for 54/74HCT circuits given in Appendix II of this Note.
LSTTL
HC/HCT ModificatIon
LSTTL TESTS REQUIRED TO BE MODIFIED FOR QMOS
6mA"
SmA
It appears from the table above that aMOS low-level output
current is inferior to that of LS, i.e., 24 milliamperes versus
only 8 milliamperes. However, the los current and output
trHL of aMOS are similar to those of LS. The real significance
of the 24 milliamperes is the ability of an LSTTL bus driver to
directly drive a dc termination, as shown in Fig. 2(a). But
ICAN-7323
652 ______________________________________________________________________
Application Notes
Vee
20 K
8 K
INPUT
OUTPUT
INPUT
Vee
GND~--~---+----------~~--------~----~
::::: 50
INPUT::::: 150
~50
INPUT
:::::150
GND
\b)
92CM-38391
Fig. 1 - Comparison of LSTTL and HCT QMOS circuit structures: (a) two-input LSTTL NAND gate (1/4 54/74LSOO), (b) two-input HCT
QMOS NOR gate (114 CD54/74HCT02).
5V
220
330
Continuity Tests
Keep in mind that the aMOS input structure, Fig. 1 (b). has a
150-ohm resistor in series with clamp diodes. Therefore, it
is important to keep input current to ±20 milliamperes
maximum during continuity testing. With this amount of
current, the test voltage is ±5.5 volts maximum.
lal
Vee OR GND
750
MORE COMPLETE TESTING OF HC OR HCT QMOS
To test HC or HCT aMOS ICs for low-power aMOS datasheet specifications, several tests other than those listed
above may be modiiied. These modifications to existing
LSTTL test limits or conditions are described below.
Quiescent Supply Current (Appendix II)
(bl
92CS-38392
Fig. 2 - 100-ohm-line output termination: (a) LSTTL,
0.25 watt per output, (b) QMOS low-power
alternative.
this ability represents a power dissipation of 0.25 watts per
output section, and 2 watts per octal. For much lower power
dissipation, use a aMOS type and a capacitively coupled
220-ohm resistor as shown in Fig. 2(b). The value of C in the
figure depends on data rate.
Setting su pply cu rrent, Icc, for the output-low cond ition test
for HC circuits is no problem, but setting it for the outputhigh condition is more complicated. If the Teradyne J283
hardware has not been modified to handle CMOS, a
comparator should be connected to each of the outputs of
the HC circuit when it is placed under test. These comparators cause an extra load current of about 7 microamperes per output; the precise amount of current depends
on the specific piece of test equipment. The extra load
currents imposed are negligible compared with the Icc of
LSTTL circuits, and can be ignored when testing them.
653
Application Notes
However, these currents can be very significant compared
with the total Icc of an HC type, and must be taken into
account when testing HC aMOS types. A solution to this
problem is to connect the high outputs of the HC type to Vee
so that they are excluded from the Icc measuring path. This
connection can be made with the Teradyne J283 MTEST
VCCt ABC D, where A, B, C, and D are the outputs in the
high state.
High-Impedance (Off-State) Current For Types Having
Three-State Outputs
The high-impedance (off-state) LSTTL tests can be run for
aMOS types, but only with much tighter limits, as shown
below:
aMOS
LSTTL
20/lA
5/lA
loz
where loz is three-state output off-state current.
FUNCTION TESTING
aMOS and LSTTL types with the same type numbers have
identical truth tables. High level (VoH), low level (VOL), and
three-state (= 1.5 volts using LS load circuit) conditions are
met when HCT devices are used in place of LS. If ac
parameters are measured as part of function testing, LS
speed limits are almost always met or improved upon.
Test personnel should be aware that actual ac specifications
for HC and HCT aMOS logic ICs are much more realistic
than for LS, asshown in the ac test-specification comparison
in Table 1. Therefore, anyone wishing to test ac parameters
should use the specifications and waveform definitions
found in the prime source of aMOS information, the aMOS
DATABOOK.'
Table I - AC Test-Specification Comparison
Input Leakage Current (All aMOS Types)
Input-leakage-current LSTTL tests can also be run for
aMOS devices but, again, with much tighter limits imposed,
as shown below:
hL
hH
LSTTL
aMOS
-400 or -800 /lA
+20/lA or +40 /lA
-1 /lA
+1 /lA
Parameter
LSTTL
HCTaMOS
CL
Vee
Temperature
15/45 pF
5V
25°C
50 pF
4.5 V
25°C,
74 (-40 to +85° C)
54 (-55 to +125° C)
REFERENCE
where hL is low-level input current and hH is high-level input
current.
1. aMOS High-Speed CMOS Logic ICs, RCA Solid State
DATABOOK SSD-290.
Appendix I - DC Characteristics for LSTTL Circuits
These figures are for positive-logic NAND gates and inverters with totem-pole outputs. Forthe characteristics of other types,
refer to published data for LSTTL circuits.
Voltages are referenced to GND (ground =0 V).
74LS
54LS
Conditions
Symbol Min. Typ. Max. Min. Typ. Max. Units
Parameter
Vee
Operating temperature
High-level input voltage
Low-level input voltage
I nput clamp voltage
High-level output voltage
Low-level output voltage
Low-level output voltage
Input current at V, = 7 V
High-level input current
Low-level input current
Short-circuit output current
Tamb
min.
min.
min.
min.
max.
max.
max.
max.
V'H
V'L
V'K
VOH
VOL
VOL
-55
2
70
0
2
0.8
-1.5
0.8
-1.5
2.5
3.4
0.25
2.7
3.4
0.4
0.25
I,
hH
I'L
los
125
-20
0.1
20
-0.4
-100 -20
0.4
0.5
0.1
20
-0.4
-100
°c
V
V
V
V
V
V
mA
/lA
mA
mA
h = -18 mA
V'L = max., 10H = -400 /lA
V'H = 2 V, 10L = 4 mA
V'H = 2 V. 10L = 8 mA
V'H = 2.7 V
V'L = 0.4 V
'Over Vee range.
Notes:
For 54LS, Vee = 4.5 V to 5.5 V; for 74LS, Vee = 4.75 V to 5.25 V.
All typical values are at Vee = 5 V. Tamb = 25° C.
For short-circuit output current, only one output must be shorted, and for not more than one second
654 _________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Application Notes
Appendix II - DC Characteristics for the CD54174HCT Family of Circuits
Voltages are referenced to GND (ground
= 0 V)
Tamb (OC)
CD54HCT/74HCT CD74HCT CD54HCT
-40 to +85 -55 to +125
+25
Parameter
High-level input voltage
Low-level input voltage
High-level output voltage
all outputs
High-level output voltage
standard outputs
High-level output voltage
bus-driver outputs
Low-level output voltage
all outputs
Low-level output voltage
standard outputs
Low-level output voltage
bus-driver outputs
Input leakage current
Analog switch off-state
current per channel
3-state output off-state
current
Quiescent supply current
SSI
Flip-flops
MSI
'Vo
Vee
(V)
Symbol
4.5-5.5
4.5-5.5
4.5
V,H
V'L
VOH
4.4
4.5
VOH
4.5
VOH
4.5
VOL
Min. Typ. Max. Min. Max. Min. Max.
Units V,
Conditions
Other
4.4
4.4
V
V
V
3.98
3.84
3.7
V
V,H or V,L
3.98
3.84
3.7
2
2
4.5
0
2
0.8
0.8
0.8
=20 JiA
-10 =4 mA
V,H or V'L -10
V
V,H or V,L -10
V
V,H or V,L
=6
mA
0.1
0.1
0.1
10
=20 JiA
0.4
V
V,H or V,L
10
=4 mA
0.4
V
V,H or V,L
10
=6 mA
pA
JiA
V,H or V'L
V,H or V'L
Vs
=Vee
4.5
VOL
0.26
0.33
4.5
VOL
0.26
0.33
5.5
5.5
±I,
±Is
0.1
0.1
5.5
±Ioz
0.5
5
10
pA
V,H or V'L
Vo'
5.5
5.5
5.5
Icc
Icc
Icc
2
4
8
20
40
80
40
80
160
JiA
Vee or
GND
10
10
10
pA
JiA
=0
=0
=0
=Vee or GND per input pin; other inputs at Vee or GND; 10 =O.
_______________________________________________________________ 655
Application Notes
Interfacing HC/HCT QMOS Logic with Other Families and
Various Types of Loads
by R. Funk
The demand for smaller, lighter, electronic equipment that
consumes little power is constant. And today's logic
designers want these qualities matched by digital logic with
high operating speeds. However, speed and power, while
perhaps paramount in the initial choice of a logic family, are
not the only basis for decision. Another very important
factor is interface flexibility: the inherent capacity of a
family to interface with other logic families and to drive
various loads.
This Application Note describes the interface capability of
the new high-speed CMOS CD54174 HC/HCT logicfamilies,
probably.the most interface-capable families yet devised.
Fig. 1 illustrates the low dc power consumption and high
speed of the HC/HCT families, both prime qualities for
interfacing flexibility. Table I lists other important qualities.
All of these characteristics, along with HC/HCT-family
static and dynamic noise immunity, are discussed in this
Note. The Note describes in detail HC/HCTinterfaces with
LSTTL, CMOS CD4000B-series, NMOS, and ECL devices,
and interfaces with terminated buses, displays, and relay or
stepping-motor coils, including interfaces with nonstandard
output levels.
INTERFACE CONSIDERATIONS
Fig. 1 shows that the speeds of the HC, HCT, and LSTTL
logic families are equivalent. In fact, the HCT family is a
low-power replacement for the LSTTL family, and is interface compatible with all TTL families. The HC family is a
low-power, high-noise-immunityalternative to the LSTTL
family, and like the HCT family, will drive all TTL and CMOS
families directly at various fanouts, depending on family.
40008
z
o
CMOS
~
30
0..~
10
0..:5
WW
(!l C
HCIHCT
= 5V
= 15 pF
AS
S
• LSTTL
aMOS
ALS
5
•
c(
a:
W
>
c(
VCC
CL
3
2
FAST
•
~~~H
• ••
10KHECL
0.001 0.1
AVERAGE
1
2
3
5
10
20
de POWER DISSIPATION (mW)
Fig. 1 - Logic-family speed-power chart.
Table II is a tabulation of interface techniques used between
various popular logic families; the superiority of the HCT
over the TTL family is evident. For example, the table shows
there are4.of6 possible direct interfaces from HCT and only
2 of 6 for TTL.
CMOS and TTL Output Configurations
The typical output structure of an HC/HCT CMOS IC is
shown in Fig. 2(a). When the output is high or low (VOH or
VOL). its level is very close to Vee or ground, respectively. In
contrast, the high-level output voltage for the standard TTL
Table I - HC/HCT Family Characteristics
Characteristic
HC
HCT
Supply Voltage
2 V to 6 V
4.5 V to 5.5 V rated
2 V to 6 V capability
-400 C to +85 0 C
-40 0 C to +85 0 C
2.5 V
1 V to 3.5 V
1.4 V
0.8 V to 2 V
(same as TTL families)
GND to Vee
0.4 V (10-15 LSTTL loads)
3.7V
GND to Vee
0.4 V (10-15 LSTTL loads)
3.7V
7 ns (balanced)
7 ns (balanced)
10 pA
10 pA
Temperature (74 family)
Input Switching Voltage
For Vee=5 V: Typical
Worst Case
Output Voltage:
Driving other CMOS Logic
Driving TTL (Voe)
(VOH)
Typ. Output Transition
for Cl = 50 pF
Input Current (typ.)
ICAN-7325
656 ___________________________________________________________________
Application Notes
Table II - Interfacing HC/HCT QMOS to Other Lagle Families
TO:
HC
5V
Supply
HCT
5V
Supply
CD5000B
5V
Supply
CD4000B
6-15 V
Supply
TTL"
5V
Supply
ECL10K
C04504"
C04504"
C04504"
direct
C04504"
transistor
direct
direct
direct
4049 or 4050
direct
10124
10124
10124
10124
transistor
10124
direct
FROM:
HC-5 V supply
HCT-5 V supply
C04000B-5 V supply
C04000B 6-15 V supply
TTL'-5 V supply
ECL-10K/KH
direct
direct
direct
direct
direct
direct
direct
direct
direct
4049 or 4050 4049 or 4050 4049 or 4050
pull-up resistor
pull-up resistor
direct
10125
10125
10125
'Includes LS, S, STD, FAST, ALS, and AS.
•• An alternative is a pull-up resistor and the CD401 09 type.
vcc
vcc
OUTPUT
01
FROM
LOGIC
GND
GND
~)
(~
~)
Fig. 2 - Typical output configurations of: (a) He/He T devices
- D1 and D2 are the inherent diodes of the p-drain and
the n-drain, respectively, (b) standard TTL, and (c)
low-power Schottky TTL (LSTTL).
circuit shown in Fig. 2(b) is limited by the VBE of 01 plus the
voltage drop across 01, resulting in a maximum VOH of 3.5
volts at a "Vee of 5 volts. Further, if a collector current is
flowing, R1 will cause an additional voltage drop, and the
worst-case VOH minimum specified for TTL, 2.4 volts (at 10H
maximum) over the full temperature and power supply
range, may be realized. The lOW-level output voltage for
TTL is the collector/emitter saturation voltage of 02, and
VOL will range from 0.2 volt to 0.5 volt maximum depending
on the fanout and, hence, total sink current.
In the output structure for the LSTTL device of Fig. 2(c), VOH
is limited by the VBE of both 01 and 03 (the diode is not
considered a part of the LSTTL output structure) and is
typically 3.4 volts. LSTTL specifications quote VoH(min) as
2.7 volts over the full temperature range with a Vee(min) of
4.75 volts. The maximum value of VOL forLSTTL can, again,
range from 0.2 to 0.5 volt depending on application and
temperature conditions.
CMOS Input Structures
The input structure for HC/HCT devices is shown in Fig.
3(a). Under normal operating conditions, the input voltage
should swing within the supply voltage limits of Vee and
ground, since exceeding these limits can cause a current to
flow through the input protection diodes, 01 and 02. The
maximum transient current permitted through these diodes
is 20 milliamperes; if this limit is exceeded, the functionality
of the circuit could be impaired. As the MOS transistors 01
and 02 are electrically identical, the typical input switching
voltage of the HC device is Vee/2.
The input configuration forHCT devices is similar to that for
HC circuits, but with the addition of a level-shifting diode,
03 between PMOS transistor01 and Vee. This configuration
is ~hown in Fig. 3(b). The effect of 03, combined with the
large NMOS transistor 02, which has a higher gain than
PMOS transistor 01, is to reduce the input switching level
to, typically, 1.4 volts.
vcc
01
02
92CNI - 38636
POLYSI LICON
RESISTOR
INPUT 150
01
Q2
GND
:::;OJ
PMO~
vcc
{~;~~"
::J
GND
PROTECTION NETWORK INTRINSIC
TO BOTH HC AND HCT CIRCUITS
(A)
(B)
92C5- 38639
Fig. 3 - Typical input structures of: (a) He devices, and (b)
HeT devices.
__________________________________________________________ 657
Application Notes
The advantage of diode D3 is that it reduces power
dissipation when a high input from a TTL output is applied.
This high level can be as low as 2.4 volts, and although it will
be recognized as a logic 1, the PMOS transistor Q1 will not
be fully cut off, allowing a flowthrough current between Vee
and ground. However, D3, and the influence of the backgate (substrate) connection of Q1 to Vee, dramatically
reduces the flowthrough current and, therefore, reduces
the power dissipation in the input stage while maintaining
device input switching levels compatible with LSTTL.
HC/HCT INTERFACES
When HCT and LSTTL devices operate from the same
supply, the quiescent flowthrough current, Ie, at V,H = 2.4 V
and Vee = 4.5 V is typically only 100 microamperes. This
means that the HCT input structure provides low CMOStype power dissipation, even when driven from TTL. If Vee is
increased to 5.5 volts, the minimum high-level output
voltage also rises 1 volt to 3.4 volts.
When interfacing LSTTL with HC/HCT devices in a dualsupply-voltage system, the following worst-case conditions
apply:
VoH(min) for TTL = 2.4 V
VoH(min) for LSTTL = 2.7 V
and
V,H(min) for HC devices = 3.85 V (70% of Vee)
V,H(min) for HCT devices = 2 V
where Vee = 4.75 V for TTL and 5.5 V for HC devices overthe
full operating temperature range.
It is clear from the above figures that the worst-case TTL
high-level output voltage is less than the minimum highlevel input voltage for HC devices, and that some special
interface technique is required. A solution is provided in the
circuit in Fig. 4(a). where pull-up resistor R1 pulls the output
GND
(A)
HC/HCT
LSTTL
(B)
92CS-38635
Fig. 4 - Techniques for interfacing: (a) LSTTL with HC devices,
and (b) LSTTL with HCT devices, and HC/HCT with
LS TTL devices.
voltage of the LSTTL against Vee. However, this technique
is not recommended because the time-constant formed by
the pull~up resistor and the stray capacitance (Cs). plus the
load capacitance (C l ). will increase the propagation delay.
Furthermore, with this set-up, the propagation time is less
predictable because it relies on both active and passive RC
time-constants.
Although a low value for R1 will reduce the propagation
delay, it will lead to extra power consumption and reduce
the noise-margin-Iow (discussed further below under Noise
Immunity) due to the active load. Both of these unwanted
occurrences conflict with the purpose of using HC family
devices. In addition, the pull-up resistor requires board
space and insertion time, thus increasing production costs.
Therefore, the pull-up resistor interface should be used
only if unavoidable. The practical solution is to use HCT
devices (all types in the CD54174 family are available in both
HC and HCT versions). which interface directly with LSTTL,
as shown in Fig. 4(b).
Driving LSTTL
Since the output of HC devices swings between Vee and
ground, they are TTL-input compatible, and the interface is
a direct connection, Fig. 4(b).
When an HCT device is the driving source for an LSTTL
device, the speed can be accurately predicted because the
LSTTL logic-switching threshold of 1.3 volts is the same as
that for HCT ICs. For HC driving sources, the speed
difference introduced by the HC logic switching threshold
of, typically, Vee/2 can be calculated from the specified
output transition times (obtained from the appropriate Data
Sheets).
Table III gives the driving capability (fanout) of HC/HCT
devices for the various TTL families.
Table III - Maximum Fanout for HC/HCT Driving TTL
Receiving
Input
Standard
Output
TTL
LSTTL
STTL
FAST
2
10
Bus-Driver
Output
3
15
3
10
2
6
CD4000 B-Serles CMOS
HC/HCT devices can be coupled directly to standard
CD4000B-series CMOS ICs if they operate from the same
supply voltage. However. if the circuits have different
supply voltages, level shifting is necessary. The configuration shown in Fig. 5(a) illustrates the circuit for HC/HCT to
CD4000B interfaces using the CD4504 low-to-high level
shifter. Note that this IC is capable of interfacing either TTL
output logic levels or CMOS logic levels to a higher outputvoltage level. The reader is reminded that the CD4000B
CMOS logic family may be operated up to 18 volts; the
HC/HCT family operates at up to a 6-volt supply-voltage
level, but also down as low as 2 volts.
Fig. 5(b) shows how to interface the CD4000B series with
HC/HCT ICs using the CD4049/4050B or HC4049/4050
buffer ICs. These buffers do not have an input clamping
diode to Vee, so that the maximum input level is 15 volts. The
logic-level switching threshold remains referenced to Vee2;
therefore. the noise-margin-Iow will be the same as for the
5-volt specification.
VWJVDDJ l r r u
~
HC/HCT
C~~Og~B
CD4504
FOR HC:
FOR HCT:
VCCI = 2 V TO x V
VCC2 = x V TO 15 V
WHERE 2< x<6
VCCI = 4.5 V TO 5.5 V
VCC2 = VCCI TO 15 V
CD4000B CD4049B/HC4049
CMOS
CD4050B/HC4050
HC/HCT
FOR HC:
FOR HCT:
VCCI =xVTOI5V
VCC2
2 VTO xV
WHERE 2< x < 6
VCCI = 6 V TO 15 V
VCC2
4.5 V TO 5.5 V
=
FOR CD SERVICES: VCC (min) = 3 V
(A)
(B)
=
92CS-38620
Fig. 5 - Techniques for interfacing: (a) HC/HCT devices with
CD4000B series CMOS. and (b) CD4000B series CMOS
with HC/HCT devices.
658 ____________________________________________________________________
Application Notes
NMOS
The rules for interfacing TTL apply when interfacing
HC/HCT devices with NMOS devices (microprocessors,
memories, etc.) since NMOS ICs generally have TTlcompatible inputs and outputs. Exceptions are NMOS ICs
with open-drain outputs, where a pull-up resistor must be
used to load the output. The HCT device inputs directly
accept active NMOS output-voltage levels.
I" ))))
--{:>o 1
BUS DRIVER
330
Eel 10K
BUS LINE
HC/HCT
TTL
BUS DRIVER
330
GND
To interface HCIHCT ICs with ECl 10K-series logic, the
10124 TTl-to-ECl and the 10125 ECl-to-TTl translator
ICs (for HC/HCT-to-ECl and ECl-to-HC/HCT interfaces,
respectively) are used. Note that these devices operate at
TTL levels. When employing the 10125 for interfacing HC
circuits, the pull-up resistor, Rl, must be used in accordance
with the instructions for driving HC devices from TTL. The
circuit configurations are shown in Figs. 6(a) and 6(b). Note
that if an HCT device is used in the ECl interface (the
definite preference) the pull-up resistor of Fig. 6(a) is
eliminated.
(A)
(B)
HC/HCT
10124
92CS - 38621
Fig. 6 - Techniques for interfacing: (a) ECL 10K logic with
HCIHCTcircuits - Rl is only required when driving HC
types, and (b) HCIHCT devices with ECL 10K logic.
Terminated Buses
Buses are used chiefly in industrial applications. The harsh
environments found in these applications impose several
requirements on microprocessor-based systems; electrical-noise immunity and the need for battery back-up are
two examples. The CMOS technology provides the ideal
solutior to these requirements. The HC CMOS devices
offer supc;ior noise immunity, similar operating speed, and
lower power dissipation over a wider temperature and
supply-voltage range in comparison with lSTTl ICs. The
noise immunity in the low logic state is the same for HCT
devices as for lSTTl.
The development of a new bus standard for CMOS systems
should be based on the performance of the devices available
with bus-driver outputs, for example, the CD54/74HC245
transceiver. Figs. 7(a) and 7(b) show examples of conventional TTL and HC/HCT bus terminations, respectively.
(A)
GND
(B)
9lCS-38637
Fig. 7 - Examples of bus terminations used in: (a)conventional
bipolar (TTL) technologies and (b) HC/HCT systems.
The particular disadvantage to the theveninized 120-ohm
termination of Fig. 7(a). the conventional TTL bus termination, is the 0.25 watt dissipated continuously by the
combination of the output driver and the 120-ohm load.
This dissipation represents 2 watts for an octal buffer.
The HC/HCT-family bus drivers have a 6-milliampere sink
current, not the 12 milliamperes of lSTTl, and are not
designed to directly drive the 120-ohm load of Fig. 7(a) for
two reasons: first, 2 watts dissipation does not represent a
low-power solution, and second, HC/HCT outputs could be
deSigned to match the very high 2-watt-dissipation application of Fig. 7(a). but would also generate much higher
switChing-current transients, which would push up EMI to
inappropriately high levels. Therefore, the interface of Fig.
7(b) is preferred for its much lower power consumption and
lower EMI. The value of C in Fig. 7(b) is carefully selected
for the range of frequencies (data rates) on the bus.
HC/HCT devices do not generally have input hystereSis, so
that Schmitt-trigger circuits should be used if slow, noisy
bus rise and fall voltages call for hysteresis in the receiver.
The CD54174HC/HCT14 and 132 are two ICs that can be
used for noise-tolerant systems. Five devices in the flip-flop
series (CD54174HC/HCT73, 74, 107, 109, and 112) also have
Schmitt triggers in the cloCk input. Note that HC devices are
preferred over HCT devices as bus receivers because of
their high low-level-input noise margin (typically 2 volts).
Nonstandard levels
In many applications, CD54/74 high-speed CMOS ICs will
have to interface with nonstandard input and output levels,
for example, with industrial or automotive systems operating
from a 12 to 24-volt supply. The circuits in Figs. 8(a) and
8(b) show the basic deSign rules for these interfaces. Fig.
8(c) illustrates an example of a user-edge input circuit for
interfaci ng with in put levels greater than Vec. The config u ration for HCIHCT devices driving loads from an external
power supply is given in Fig. 9(a). Figs. 9(b) and 9(c) show
HC/HCT devices driving loads (for example, a relay) on the
same supply voltage.
Fig. 10(a) is an interesting low-cost but also lower-speed
high-to-Iow interface: 12 to 5-volt logic levels using only
1~O-kilohm resistors in series with each input. Fig. 10(b)
shows why this interface is reliable with good noise margins;
RCA HC/HCT designs guarantee that forced input current
into Vee will result in less than 0.05 of this current flowing
into ground. In Fig. lOeb). VIL at B is less than 0.34 volt, well
under the specified VIL of I-volt maximum. Other high-tolow voltage-interface combinations with different resistor
values may be determined with knowledge of the 0.05 value
of current gain (a) between adjacent inputs.
___________________________________________________________________ 659
Application Notes
5 VTO 48 V
GND
(A)
(A)
12VT024V
R2
12VT024V
CIRCUIT
VCC
GND
(81
(8)
LOAD
LOAD
(C)
(C)
92 CS- 38638
Fig. 8 - Technique for interfacing: (a) nonstandard logic levels
with HC/HCT circuits - values of Rl and R2depend on
the output voltage of the driving circuit and Cl depends
on the noise and speed, (b) HCIHC T devices with
nonstandard logic levels - values of Rl and R2 depend
on supply voltage and transistor type, and (c) a useredge input circuit configuration for interfacing with
input voltages greater than Vee.
92CS-38627
Fig. 9 - Interfacing loaded HC/HC T devices: (a) an external
power supply via a transistor, (b) the same power
supply via a transistor, (c) the interfacing of HCIHCT
directly with loads on the same power supply.
--
Vcc
liN
VCC=5V±10%
100K
12 V
100 K
HC
100 K
GND == LOGIC 0 \
+12V", LOGIC 1 1U-~'VV-1
100K
CMOS
100 K
--
HC
~Jv\r'v---i
TYPE
8
lOUT
lOUT'::::: 0.05 liN
VIL < 0.34 V
(8)
(AI
92C5-38628
92CS-38629
Fig. 10 - Low-cost, low-speed 12-volt-logic t05-volt-logic interfaces.
The typical value of alpha (a) for the bipolar parasitic input
transistor is 0.001. The low value of alpha is an important
feature of the RCA HC/HCT family because it eliminates
transient logic errors in the presence of transient voltages
exceeding Vee at any input.
Dlspfays
is just as ideal for HC/HCT family devices driving LCD
displays as it has been for CD4000B-series devices. Fig.
11 (a) illustrates the basic BCD-to-7-segment LCD interface
(HC/HCT4543) plus the single-segment LCD interface
using the HC/HCT 86 type. The popular 4511 type is carried
into the HCIHCT family for the basic LED BCD-to-7segment interface, as illustrated in Fig. 11 (b).
The CMOS technology, with its rail-to-rail output switching,
660 ______________________________________________________________________
Application Notes
LCD SEGMENT
D
u
LDC
DRIVER
~NCtUTS
•
{
B
1
16 Vee
c
2 CD74HC/
15 t
HCT4511
LT
3
6L
4
PE
5
0
6
A
7
GND
8
BCD-TO-7-SEGMENT
BP
FREO_
BCD
{
INPUTS
14 9
,.
"
b
"
d
SEGMENT
OUTPUTS
BP DRIVE
SEGMENT (DECIMAL) DRIVE
CD74HC/HCT86
(8)
(A)
92.C5-3B624
10 V (max)
10 V (max)
LED
VCC
(OPTIONAL)
(D)
(C)
92CS-38SZ5
92CS-38626
Fig. 11 - Display interfacing: (a) LCD, (b) and (c) LED, (d) lamp.
For single-segment LED interface, the open drain 74HC/
HCT03 type is ideal, Fig. 11 (c). Since the 03 type does not
have an output-to-Vccforward diode in its output circuit, the
LED may be supplied by up to 10 volts. R may be useful in
limiting current and reducing power. This same03 type can
also be used for driving an indicator lamp, as shown in Fig.
11 (d).
~
JAD
I-+--L2 MOS FET
~
Relay or Stepping Motor Colis
Another application of the open drain HC/HCT03 type is the
relay or stepping motor interface shown in Fig. 12. The
external diode across the coil absorbs the back emf of the
coil.
L 2 MOSFET Power Transistor
RCA logic level (L 2) MOS power transistors, Fig. 13, are
ideally driven by any HC/HCT output. Higher switching
speeds, 200 nanoseconds, are achieved using the bus-drive
output types. HC/HCT outputs will reliably switch these
new L2 MOS power devices using only a 5-volt supply for
Vee; this is truly a breakthrough in power-transistor-interface
applications cost.
HC/HCT03
Fig. 12 - Coil driver.
92C5-38634
Fig. 13 - L 2 MOSFET power-transistor drive.
NOISE IMMUNITY IN THE HC/HCT FAMILY
General
The noise-immunity characteristics of logic devices can be
divided into two categories, static and dynamic. Static noise
immunity can be divided further into static noise-immunitylow, the difference between the V,c(max) of the receiving
circuit and the VOL(max) from the driving current, and static
noise-immunity-high, the difference between the VoH(min)
from the driving circuit and the V'H(min) of the receiving
circuit.
The guaranteed static noise-immunity characteristics for
LSTTL and HC/HCT devices are shown in Table IV. If the
static noise margins for LSTTL are assumed to be unity, (for
both the high and low states), a direct comparison of LSTTL
and HC/HCT static noise margins can be made by taking
the ratio shown in Table V. These results are particularly
impressive when the extended ambient temperature range
and the lower supply voltage of the HC/HCT family is
considered.
____________________________________________________________________ 661
Application Notes
Table IV - Stallc Noise Margins for LSTTL at Vee=4.75 V
and HC/HCT Systems at Vee=4.5 V
LsnL
HCT
VoH(min)
V'H(min)
Noise-Margin-High
2.7V
2V
0.7 V
HC
4.4 V
3.15 V
1.25 V
4.4
2
2.4 V
V,dmax)
VOL(max)
Noise-Margin-Low
0.8 V
0.4V
0.4V
0.9 V
0.1 V
0.8 V
0.8 V
0.1 V
0.7V
Table V - Ratio of Static Noise Margins, LSTTL to HC/HCT
converse is not true (since VoH(min) for LSTTL is less than
VOH(min) for HC; there is no overlap in the noise-marginhigh regions). Therefore, the noise-margin-high for LSTTL
driving HC devices is said to be negative, which explains the
reason for the problematical external pull-up resistor
interface described in Fig. 4(a).
In a mixed-technology system with fully loaded HCT
outputs driving LSTTL inputs, the static noise-Il)argin-Iow
is equal for both families, and the HCT devices exhibit an
excellent static noise-margin-high that encompasses that
displayed by LSTTL. This situation is illustrated by the
graph in Fig. 14(b), which shows that HCT and LSTTL
devices are fully interchangeable in a mixed-technology
system.
Dynamic noise Immunity
HC
LSTTL
Dynamic noise immunityforHC/HCTcircuits also falls into
two categories, high and low. The dynamic noise-marginlow is, again, the smaller of the two, and is, therefore, the
parameter considered here.
Ambient Temperature
0 to +70°C r40 to +85°C -40 to +85° C To plot the dynamic noise-margin-Iow for HC/HCT devices,
Range (Tamb)
4.5 V a pulse of known magnitude, Vp , is applied to the input of a
Supply Voltage (Vee)
4.75 V
4.5 V
device; its width, tw, is then increased until the device just
begins to switch. The input level on which Vp is based is
The graph in Fig. 14(a) compares the static noise margins
equal to the switching voltage minus the worst-case static
for HC devices with those for LSTTL. The graph illustrates
noise-margin-Iow. Pulse width, tw, is measured at half pulse
that while HC circuits can drive LSTTL (as VOH(min) for an
height, Vp /2, and the rise and fall times, t, and It, are 0.6
HC device is greater than V'H(min) for an LSTTL device), the
nanosecond. Vp is reduced in increments and the tw for
DHC
~LSTTL
each new value ascertained. The test is repeated over a
(J) 6
series of varying supply voltages (Vee between 2 and 6 volts
Ifor HC and at 5 volts for HCT) and output currents, 10.
'5
1.75
2
Noise-Margin-High
Noise-Margin-Low
HCT
3.4
1.75
> 5
The resulting graphs in Figs. 15(a) and 15(b) illustrate the
I
'0
6
~4
(J)
..J
!:i
~
g
~ 3 V,H
~
"_======,,,,",VOH
/!:2
:::>
_V'H
g
!;
~
IX vcc
10
6V
20 ~A
6V 5.2mA
c 4.5V 20~A
d 4.5V 4mA
e
2V
20~A
tr = t, - 0.6 ns
5
•b
I 4
'i!.
>
j:'3
l:
1
20 %
vcc
VIL _ _
~IL
oVOL~OL
4.5V
5.5V
"iii
l:
2
w
~ 1
:::>
-------------
Q,
0
0
SUPPLY VOLTAGE (Vccl - VOLTS
(A)
92CS~3B630
2
4
6
8
PULSE WIDTH (tW) -
10
12
14
16
nanoseconds
(lW) MEASURED AT 50 % Vp
(A)
92CS-38622
(J)
!:i
g
5
I 4
'i!.
>
j:' 3
l:
"iii
l:
W
2
~
V,LV,L
VOL~VOL
4.5 V
5.5
SUPPLY VOLTAGE (Vcc) - VOLTS
~
0'0~--~2---J4--~6--~8--~1~0--~1~2---14L--J16
PULSE WIDTH (tW) - nanoseconds
tw MEASURED AT 50 %
Vp
(8)
(B)
92CS-38631
Fig. 14 - Static noise margins for: (a) He devices compared with
LSTTL, and (b) HeT devices compared with LSTTL in
a mixed technology system.
92CS-3B623
Fig. 15 - Dynamic noise immunity characteristics (worst-case,
fully loaded driver) for: (a) He devices and (b) HeT
devices.
662 _________________________________________________________________
Application Notes
dynamic noise immunity characteristics of HC and HCT
circuits, respectively. Note that an increase in 10 lowers the
curve and reduces the dynamic noise immunity. As these
curves illustrate for the worst-case conditions with fully
loaded HC/HCT devices, a system using only HC or HCT
circuits will demonstrate an increase in dynamic noise
immunity, shifting the c~rves up 0.3 volt.
Derived from the typical input switching threshold levels of
1.3 and 2.5 volts for HC and HCT, respectively, the noise
immunity characteristics will show a typical improvement·
of 0.8 volt in HCT systems and 1.2 volts in HC systems.
________________________________________________________ 663
Application Notes
,Power-Supply Distribution and Oecoupling
For QMOS High-Speed-Logic les
by R. Funk
The HCand HCT 'high-speed OMOS IC logic families
available from RCA offer the user many advantages over
TTL logic families. These advantages include much lower
power consumption, better noise margin (mainly in the HC
devices), wider. operating-voltage range, wider operatingtemp.erature range, lower input current, lower three-state
current, superior high-to-Iow and low-to-high output
transition time and propagation delay balance, and better
reliability. However, HC/HCT CMOS does share one
common liability with LSTTL: switching transients generated on the ground and supply rails can dangerously
reduce logic noise margin if not compensated.
Higher speeds, faster edges, and higher output-drive
currents cause higher-frequency current transients to be
imposed on ground and Vee rails of an IC. The familiar L
di/dt voltage transient is developed, its value depending on
the inductance in the ground OrVee connection from chip to
IC lead. For octal bus-driver types, one volt of L di/dt is
possible depending on inductance, device decoupling, and
power-supply decoupling. This Note focuses on powersupply distribution and decoupling to reduce switching
noise. One source of this noise, an important system factor
relative to IC switching, is rf radiated noise, noise that can
interfere with communications in the local area. Some
general ways to reduce L di/dt rf noise, i.e., voltage
generation on ground and supply lines, are described
below.
POWER DISTRIBUTION
Before decoupling can provide any noise reduction, there
must first be a good power-distribution network. A good
ground connection is vital, and so a good connection
pattern is required.
The commonly accepted ground pattern shown in Fig. 1
can cause problems. In the figure, an output from device 1
drives an input to device 2, and an output from device 3
drives an inputto device4: Since the signal path 1 to 2 and 3
to 4 are not coupled, there should be no crosstalk. However,
devices 1 and 3 share the crosshatched part of the ground
line, as shown, and switching of the output of device 1 could
produce a spike on the ground of device 3, causing the input
to device 4 to switch. It is, therefore, advisable to reduce the
single ground path on a double-sided board by using links,
as shown in Fig. 2. This advice is especially true for boards
92C5-38834
Fig. 2 - 'Reducing ground paths on two-sided board.
where high currents are switched. Avoid using jumpers like
the one ·shown in Fig. 3 for ground and power line (Vee)
connections. Jumpers are unlikely to be used in production
p~inted-circuit boards, but they should,also be avoided on
prototype and single boards becauseithe inductance they
introduce into the lines permits coupling between outputs.
Printed-circuit boards equipped with premanufactured
ground connections or copper strips to connect the pins to
ground should be used.
BAD PRACTICE
92CS-38830
9ZCS-3S833
Fig. 1 - Common ground path on two-sided board.
Fig. 3 - Ground connection on
8
logic board.
ICAN-7329
664 _________________________________________________________________
Application Notes
An even better solution is to use multilayer printed-circuit
boards, where different layers can be used for the supply
rails and the copper interconnections. The capacitive
coupling between ground and Vee is essential for highfrequency noise-pulse reduction. The capacitive coupling
has the distinct advantage of being free from the inductive
effects of the interconnections and, therefore, acts like a
discrete decoupling capacitor.
Even with double-sided boards, it is advisable to have the
Vee and ground lines on opposite sides of the board
wherever possible. A less expensive alternative to multilayer
boards is the multiwire board, which offers the same highfrequency noise characteristics.
No matter what type of board is used, it is recommended
that it have at least five ground pins per connector to assure
ground-current distribution. The precautions taken with
ground lines also apply to the Vee line. Power-line stability is
a must, a difference of only 0.5 V between Vee lines can
produce unwanted effects. It is advisable to provide separate
power stabilization for each board to isolate noise sources
and to eliminate large stabilizer circuits with their heavygauge (low-impedance) wiring to each board. However,
care must betaken in designing power stabilization because
a fault on a board's stabilizer circuit may be transmitted via
the HC/HCT input structure to other boards, possibly
causing damage.
L
0_-------00
-.o
TOO MUCH INDUCTANCE
OC_ _ _....;L;...._ _
NO EFFECT
L 12
COe;;""""""~~""''''''=:3CO
BEST SOLUTION
92CS-3883J
Fig. 4 - Comparison of decoupling tracks.
The capacitors to 'be used should be carefully selected.
Many capacitors are produced with leads bent, as shown in
Fig. 5(a); these may introduce unwanted inductance, The
best capacitors are those with leads shaped as in Fig. 5(b).
In tests, good decoupling was obtained by using a minimum
of:
- one 47 pF bulk capacitor per standard IC card
- one 1 pF tantalum capacitor per 10 packages of SSllogic
- one 22 nF ceramic capacitor for each octal bus-driver
circuit-and for each counter/shift register (MSI logic)
- one 22 nF ceramic capacitor per four packages of SSI
logic
DECOUPLING
No matter how good the Vee and ground connections, all
line-inductance effects cannot be avoided. This is where
decoupling plays its part. Ceramic capacitors are the
. nearest approximation to ideal decoupling capacitors since
they have almost no series inductance. But the advantage of
using inductance-free capacitors is lost if long connections
to the capacitor are used. These over-long connections can
result in a tuned LC-circuitwith a very high Q factor. The
oscillations produced would have a worse effect on the
circuit than if there were no decoupling at all. If it is not
possible to make the decoupling connections shorter than
20 mm, place tracks in parallel, with a separation of at least
one track width, as shown in Fig. 4. Making the connections
thicker will have almost no effect.
(0"'"
(AI
A-,'NeH
PREFERRED
IBI
92CS-3BB32
Fig. 5 - Optimum capacitor lead shape.
_________________________________________________________________ 665
Application Notes
Replacing LSTTL with QMOS High-Speed Logic'les
by J. Nadolski
Until the development of RCA HC and HCT high-speedCMOS logic ICs, high-speed logic devices were available
only in the high-power-consuming bipolar technology. The
HC/HCT QMOS family features LSTTL speed along with
many performance features superior to LSTTL. HCT CMOS
ICs have TTL-compatible input-voltage levels and are
intended to be CMOS substitutes for bipolar LSTTL logic
ICs of the same type. HC CMOS ICs have CMOS voltagelevel input compatibility and feature high noise immunity in
all-CMOS system designs.
Replacement of an LSTTL IC with an HCT IC provides the
identical logic function, same pin out, same speed, and
same general-purpose logic fanout of 10 LSTTL loads, but
with much less power dissipation. LSTTL bus-driver types
can drive 100-ohm transmission-line terminations, but at a
huge sacrifice in system power consumption. Techniques,
that can be used to terminate 100-ohm lines, and other
types of low-power terminations involving LSTTL and
QMOS ICs. are presented in this Note.
LSTTL, an inherent circuit advantage compared to the
LSTTL diode input design with its temperature sensitivity.
This HCT advantage provides better noise margin over the
device operating-temperature range and better stability of
RC astable multivibrators with temperature variation when
these circuits employ HCT ICs.
Output Drive Current-HC/HCT CMOS has better source
current than LSTTL and sufficient sink current for LSTTL
interfacing requirements. Sink current is lower than in
LSTTL; this characteristic minimizes current spiking and
EMI generation in RCA QMOS devices. This Note will delve
into line terminations relative to sink current, the one area
where differences in'equipment design may exist depending
on the high-speed logic family used.
Timing-The HC/HCT output-stage PMOS/NMOS transistors are designed for balance at saturation in order to
provide balanced output transition times. All logic stages
employ PMOS/NMOS'transistor sizing, Fig. 1, to balance
propagation delays, Fig. 2_
PERFORMANCE COMPARISON
Of paramount importance-in the comparison of LSTTL and
QMOS (HCT) performance are the identical input-voltage
specifications of the two technologies:
V'L(max) =0.8 V
V'H(min) = 2 V
Table I is a comparison of all applications-related parameters. It is evident from this table that not only does HCT
QMOS substitute easily for LSTTL, but system performance
is enhanced through such characteristics as better signal
transition time and propagation delay balance, better noise
margin, and lower supply and signal-line currents. The
comparisons below follow the organization of Table I.
Power Consumptlon-(de)-HCT power consumption is
essentially zero in comparison to LSTTL. ae (operatlng)HCT power is frequency dependent and comparable to
LSTTL at continuously high operating frequencies. Generally, HCT power is much lower because average logic data
rates are under 1 MHz.'
V DD
GMDS
VSS
SINK AND SOURCE· 4 mA (STANDARDlIOLSTTLLOADS
CURRENT. 6mA (BUSl 15 LSTTL LOADS
92CS-38673
Fig. 1 - Logic stage PMOS and NMOS transistor sizing to
balance propagation delays.
lOS
Voltage-HC/HCT CMOS requires much less voltage
regulation than LSTTL. HCT devices can actually operate at
2 to 6 volts, although they are specified for 4.5 to 5.5 volts.
Temperature-Commercial-grade HC/HCT CMOS is more
realistically rated than LSTTL, -40· C to +85· C, not the very
limiting 0 to +70· C of most LSTTL 74 families.
Noise Margln-HCT interfacing with HCT or with LSTTL
provides improved noise margin, particularly at the high
end of the operating range where outputs swing to 5 volts.
Stability-The CMOS input PMOS/NMOS pair has less
switching-voltage shift with temperature variation than
5V
VDS
92CS-38674
Fig. 2 - Balanced outputlransition time and propagation delay.
ICAN-7330
666 ________________________________________________________--------------
Application Notes
Table I - Comparison of Characteristics of HCT and LSTTL Circuits
Characteristic
Quiescent Power
Per Gate
Per Flip-Flop
4-Stage Counter
Per Transceiver/Buffer
Operating Power
Per Gate
Per Flip-Flop
4-Stage Counter
Per Transceiver/Buffer
74LSTTLXXXX
0.025 mW
0.05 mW
0.4 mW
0.1 mW
5.5mW
10mW
95 mW
60 mW
Frequency In
Frequency In
0.1 MHz 1 MHz 10 MHz 0.1-1 MHz 10 MHz
0.2 mW
2 mW
20 mW
5.5 mW
=-20 mW
0.15mW 1.5mW 15mW
10 mW
=-15 mW
0.24 mW 2.4 mW 24 mW
95 mW =-120 mW
0.25 mW 2.5 mW 25 mW
60 mW
=-90 mW
Operating Supply Voltage
Operating Temperature Range
Noise Margin
LS to LS
}
HC to HC
HCTto HCT
QMOS CD74HCTXXXX
(HCT) 4.5 V to 5.5 V
(HC) 2 Vto 6 V
4.75 V to 5.25 V
-40°C to +85°C
O°C to +70°C
0.7 V/O.4 V
(High/Low)
1.4 V/0.9 V
2.9 V/0.47 V
Input Switching Voltage Stability over Temp.
Output Drive Current
Source Current at VOH=2.4 V
Sink Current
Std. Logic VOL =0.4 V
Bus Logic VOL=O.4 V
VoL=0.5 V
Output Transition Time'
TTLH
TTHL
Typical Gate Propagation Delay:'
tPHL/tPLH
Vcc=5 V, CL=15 pF
Typical Flip-Flop Propagation Delay:
Vcc=5 V, CL=15 pF
tpLH
tPHL
Typical Clock Rate of a Flip-Flop
Vs ±60 mV
Vs ± 200 mV
-8 mA
-400 pA
4 mA
6mA
12 mA
4mA
12 mA
24 mA
6 ns
6 ns
15 ns
6 ns
8 ns/8 ns
8 ns/11 ns
14 ns
14 ns
15 ns
22 ns
50 MHz
33 MHz
Input Current
I,L
I'H
-1 pA
1 pA
-0.4 to -0.8 mA
40 pA
3-State Output Leakage Current
±5 pA
±20pA
0.0019 (RCA Report)
0.008 (RADC Report)
Reliability
%/1000 Hours at 60% Confidence
'Temperature Coefficient = 0.04 ns/pF for both OMOS and LSTTL.
Frequency-QMOS clock rates are often higher than LSTTL
clock rates.
Input Current-A big difference between the two technologies is the relatively large continuous dc current that
flows in LSTTL interconnect wiring. Essentially no dc input
current flows in HC/HCT CMOS. Typically, a few picoamperes of input back-diode current flows. This HCT
advantage means better buffering and a wider frequency
range in RC oscillators.
Leakage Current-Bus designs are enhanced by a fourtimes-lower high-Z output leakage current in HC/HCT
CMOS as compared to LSTTL. For low-power designs,
larger values of terminating resistors can be used.
Reliability-Reliability at 85°C junction temperature is four
times improved with HC/HCT CMOS ICs. In fact, since the
higher internal IC dissipation of LSTTL raises junction
temperature an average of 10°C per IC, reliability improvement is even greater than the .four-times improvement
indicated.
_________________________________________________________________ 667
Application Notes
INPUT/BUS/TRANSMISSION-LINE TERMINATION
Termination at inputs and outputs may be different for HCT
and LSTTL devices. It is good design practice to properly
terminate all unused LSTTL inputs. HCT devices can then
be substituted directly, provided the unused input is returned
to Vee, ground or through a 1.2 kilohm or higher pull-up
resistor. Output terminations are handled differently.
A discussion of termination follows. It is primarily in I/O
terminations that differences in circuit design could exist
and, hence, require design changes when HCT is substituted
for LSTTL.
INPUT TERMINATION
The termination of unused inputs in LSTTL is not absolutely
necessary because of the internal pull-up of 1.2 kilohms;
however, it is good design practice to terminate all unused
inputs to prevent linear operation of input circuitry. Such
operation causes the circuitry to draw more power than it
would under normal operation. The typical resistor values
used for pull-up in termination of LSTTl. are between 220
ohms and 1.2 kilohms; typical pull-down values are between
680 ohms and 1 kilohm. Unlike the case with LSTTL
devices, unused HCT inputs must be terminated since the
input is a very high impedance and, if left open, could cause
the input circuitry to float into a linear mode of operation,
thus drawing excessive current orcausing oscillation. HCT
devices mUll be terminated to Vee or ground or with a
pull-up or pull-down resistor with a value of 1 kilohm to 1
megohm, as shown in Fig. 3. The large-value resistors
reduce the power dissipation of the driving devices.
vcc
IK
IN-=
RC
92eS-3a8S3
(a)
10-6
10-5
RC
92CS-3B848
(a)
l!lz
810-4
RC
III
S2eS-3aBS2-
I
(b)
E10-5
c
o
Fig. 2 - Time period(T) as a function ofRC using equation (1)
for (a) HC04 type and (b) HCT04 type.
a:
,.1=w~
10-6
10-7
Using the HC04 type, equation (2) can be simplified if the
valid assumption that VTR = 0.5 Vcc is made. Then:
T = 2.2 RC
(3)
Fig. 3 illustrates how little the choice of either equation (1)
or (3) affects results in a practical case .
.,c
z
,
10-8
10-5
10-4
10-3
RC
92CS-38849
(b)
'
.
810-48
W
•
.,
I
,
E'0- 5
g
a:
~ 10-6
w
,.
1=
10-8
• ;~_6z
• &1~_5Z
RC
4'8
10-4
24'8
24'1
10-3
10-2
RC
92eS-3aS51
Fig. 3 - Time period as a function of RC using theoretical
approach of equation (1) versus equation (3) for type
HC04.
92CS-38850
(c)
Fig. 4 - Measured versus calculated T as a function of RC for
(a) HC04 type, (b) HCU04 type, and (c) HCT04 type.
_______________________________________________________________________ 673
Application Notes
Fig.5 identifies the area of validity of Rand C for equations
(1) and (3). Measu rements were made with the ti me constant
as a parameter. The pOints on the chart are ratios of
measured to calculated time period. The design guidelines
used to keep the ratio of measured T to calculated T close to
one, as shown in Fig. 5, follow.
VDD
R
K
4.5V
8.2 K
•
~20HC~1nF
i~
MAXCURYE
19
U
:Il.8
I
E' 7
~
MIN CURVE
~ 16
IE
w ••
:Il
;::
-40
-20
o
20
40
60
80
100
120
140
180
TEMPERATURE rCI
92CS-38842
(a)
Voo
4.51
R
B.2K
K
•
en
C
680pF
~ 15 HCU04
a
u
~ 14
R-OHMS
51
92CS-38880
U
i
Fig. 5 - Area of theoretical equation validity. Points are ratios
of measured to calculated T.
13
MAX CURVE
I
E ••
g
~
Rs in Fig. 1 must not be made too large, as the multivibrator
time constant and phase shift is influenced by this resistance
(as well as by stray wiring and breadboard capacitance). A
large value of Rs will change the time period and cause
spurious oscillations and glitches.
In the oscillator circuit, C should be greater than orequal to
100 pF to eliminate probe and stray capacitance interference. R should be greater than or equal to 100 ohms to
support the function of Rs. However, to avoid parasitic
oscillation, R must not be made too large. Appropriate
values of Rand C depend upon circuit design and layout.
Equation (3) is valid forR~50 kilohmsand C~1000 pF; use
equation (1) forR <50 kilohms, and C< 1000 pF. However,
note that, as implied above, if C is less than 1000 pF, stray
capacitance will affect the entire system.
CMOS multivibrator designs have long been known to be
temperature insensitive. Thevariation of the inputswitching
voltage (Vs) with temperature in a aMOS device is only ±60
mVover a range of -55° C to +125° C; in contrast, the LSTTL
Vs varies ±200 mV over the same temperature range. Figs.
6(a) and 6(b) reflect the minor change in period T,less than
3% for HC and 10% for HCU devices over a 150°C
temperature range, resulting from the small variation in
aMOS Vs.
MIN CURVE
11
w
:Il.o
;::
_
_
0
w
~
00
M
.00
'W
.~
'00
TEMPERATURE (OC)
(b)
92CS-38843
Fig. 6 - Time period as a function of temperature for (a) HC04
type and (b) HCU04 type.
POWER CONSUMPTION
One of the major advantages of the CMOS technology and,
hence, aMOS ICs, is the low power dissipation. The power
consumed by the RC oscillator of Fig. 7, using the HCT04 is:
~=~+~
~
PA and P8 = (Cpo + C/2)V'f
(5)
where
Cpo is a capacitive value used to represent internal inverter
power consumption. Cpo is rated at36 pF on the HC/HCT04
Data Sheet. The C in equation (5) is the RC oscillator
capacitance seen as a load that is shared by inverters A and
B of Fig. 7.
Table I contains parameters, data, and calculations for five
operating frequencies. Fig. 8 shows plots of the measured
Table I - Measured YS Calculated RC-Oscillator Power Dissipation (YCC=5.5 Y)
RC
4.710-8
4.710-7
4.710-'
4.710-3
4.710-'
'R
(ohms)
470
4700
47,000
47,000
22,100
C
(F)
10-. 0
10-. 0
10-10-7
2.210-8
T
T/C
(s/F)
166 ns 1.66103
1.4 ps 1.4010'
116ps 1.1610·
12.6 ms 1.2610·
12.4 ms 1.2410'
f
6.024 MHz
714 kHz
8.62 kHz
79.36 Hz
80.64 Hz
I
meas'rd
(mA)
11.066
2.998
0.9082
0.644
0.707
YI
P
meas'rd
(mW)
60.863
16.489
4.995
3.542
3.888
72 pF + C)Y'
2.2RC
P
2.2 RC
calculated
T
(mW)
(ms)
50.32
0.1034 ps
1.034 ps
5.032
0.2946
0.1034
0.2926
10.34
0.622
106.964
2.2R
T/C
(s/F)
1.034103
1.03410'
1.03410·
1.03410·
4.36210'
674 _________________________________________________________________
Application Notes
voo
voo
R
RS
c
c
RS
92CS-38879
Fig. 7 - RC oscillator circuit.
92CS-38841
Fig. 9 - Common method of reducing QMOS RC-oscillator
power consumption.
The effect of resistor R, in Fig. 9 is to decrease the output
charging current of CMOS inverter (B) into capacitor C,
hence the increased charging time of C. The impact of R,on
frequency when large values of resistor R are used is
minimal; there is a 2% frequency decrease for HC and a
2.5% decrease for HCU when R is 47 kilohms, C is 1000 pF,
and R, is 1 kilohm. Figs. 10(a) and 10(b) plot power
consumption against the value of R, for the HC04 and
HCU04 types, respectively.
He04
R
47 K
C
1000 pF
92CS-3Ba81
Fig. 8 - Power dissipation in oscillator (using an HCT04) as a
function of TIC ratio (Vee = 5.5 V).
versus calculated power. Table I and Fig. 8 illustrate two key
pOints concerning RC oscillator power:
1. Power is heavily dependent on the value of C.
2. Calculations are valid only at higher frequencies,
generally above 1 MHz.
Because of the dependence of power on both the frequency
and value of C, power is plotted (Fig. 8) as a function of the
TIC ratio. Fig. 9 illustrates a common method of reducing
aMOS RC-oscillator power consumption. In the circuit,
small-valued, current-limiting resistors, R" are placed in
series with the circuit dc supply voltage, Vee, and with the
ground terminals. This arrangement reduces the CMOS
flowthrough current during slow switching transitions,
when both the PMOS and NMOS transistors conduct
transient current from Vee to ground.
I n addition to reducing power consumption, resistor R, also
decreases the RC operating frequency. The pOWE/r reduction
is more pronounced with HCU devices, for which the
spiking-current component is larger. In these devices, the
switch from the low level to the high level and vice versa
begins at an' input-switching voltage lower in the groundto-Vee range than in other aMOS types. HC devices do not
see a significant reduction in power unless the operating
frequency is very high. There is a 20% power reduction at 6
MHz with a 50-ohm R" while there is no improvement at all
at 10 kHz with the same resistance. In the case of HCU
devices, the power benefit from the introduction of the
50-ohm R, is 60% at 5 MHz, but only 20% at 10 kHz for a Vee
of 4.5 V. At low frequency in any aMOS device, the spiking
current losses become negligible compared to the power
dissipated in the external components.
o
100
200
300
400
500
600
700
BOO
CURRENT~UMITING ReSISTANCE (Rd -
900 1000
OHMS
9ZCS-38846
(a)
HCU04
R
4.7 K
C
R
47 K
C
R
22.1 K C
100pF
103 pF
20
CURRENT·UMITING RESISTANCE CRrI
- OHMS
9ZCS- 38844
(b)
Fig. 10 - Power dissipation in an oscillator as a function of R,.
In (a) the oscillator employs an HC04, in (b) an
HCU04.
_______________________________________________________________________ 675
Application Notes
RC OSCILLATOR USING THE HC/HCT132
SCHMITT TRIGGER
The RCA HC/HCT132 can be used in an astable multivibrator, as shown in Fig. 11. The equation used to calculate
the period Tis:
~
E
I
z
o
T = RC In
+ RC In
(7)
Vcc-V p
~
iii
'"E
)----{)Vcc
~
VCCo----I-'~-~~--~
(a)
92CS-38838
Fig. 11 - The HCIHCT132 in an astable multivibrator circuit.
Fig. 12 plots measured T versus RC for the HC132. Also
plotted in Fig. 12 are calculated values ofT versus RC using
equation (7). Fig. 13 is a plot of measured T versus RC for
the HCT132. Figs. 14(a) and 14(b) show measured power
dissipation as a function of time-constant RC in oscillators
employing the HC132 and HCT132, respectively.
~
E
I
z
o
;::
11
~
E
~
1.0
'E"I
E
92CS-38855
c
0
(b)
~w
Fig. 14 - Measured power dissipated as a lunctional TIC, (a) in
an oscillating HC132 and (b) in an HCT132.
"
;::
0.0001
REFERENCES
0.00001
10-8
1. For more information on CMOS circuits in oscillators
and other timing applications, see:
10-5
RC
92CS-38837
Fig. 12 - Measured and calculated time period 01 oscillating
HC132 as a lunction 01 time constant RC.
"Astable and Monostable Oscillators Using RCA CMOS
Digital Integrated Circuits," RCA Solid State Application
Note ICAN-6466.
"Using the CD4047A in CMOS Timing Applications,"
RCA Solid State Application Note ICAN-6230.
II
"Simplified Design of Astable RC Oscillators Using the
CD4060B or Two CMOS Inverters," RCA Solid State
Application Note ICAN-6883.
'"E
I
2. For a discussion of Cpo, see QMOS High-Speed CMOS
Logic ICs, RCA Solid State DATABOOK SSD-290, under
"Description of aMOS product Line."
E
c
0
.
a:w
w
;::
"
92CS-3aa57'
Fig. 13 - Measured time period 01 oscillating HCT132 as a
lunction 01 time constant RC.
676 ______________________________________~----------------------------
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Application Notes
Linear Application of the
CD54/74HCU04 QMOS Hex Inverter
Because the CD54174HCU04, Unbuffered Hex Inverter,' is
a QMOS device based on a 3-micron process, it is an
excellent high-speed digital switch. Its linear characteristics
feature low capacitance and high current drive. A high
transconductance associated with the high current drive is
contributed by pairs of complementary NMOS and PMOS
transistors, which form relatively simple inverting amplifiers.
There are six of these transistor-pair amplifiers in the
HCU04; each has a common Vee and ground. A variety of
application circuits are included in this Note to illustrate the
many uses of the HCU04 amplifier.
~=:cr~~~~vi~~~i~ ~i~~~~~11 ~~fpWt~e~~~r :~~pcp~;~~~t~rg~g: ~
in linear applications (a knowledge of linear-feedback"
circuit theory is assumed). Fig. 1 shows the internal "5
functional diagram and the circuit schematic of each,;'
inverter.
14
'A
1Y
'3
by W. Austin
PMOS AND NMOS DEVICE CHARACTERISTICS
As mentioned above, each pair of PMOS and NMOS devices
in the HCU04 make a relatively simple inverting amplifier;
one feedback resistor provides static bias. The amplifier
transfer characteristic of each unbuffered inverter has a
dynamic range of up to three volts, peak-to-peak, with good
linearity in the center one volt, peak-to-peak, region. The
transfer characteristic of the HCU04 is shown in Fig. 2.
5
4
-l=--_:::--,,_-=:' - - -..." \
'\
\
\
\
\
\
\
Vee
\
"-
6A
2A
6Y
2Y
5A
1.9 MIN.
3A
5Y
3Y
4A
GND
4Y
Vee
TA
0
4.5 v
+125 c C
2.5 TYPICAL
Vee 75 V
TA' 2S'C
"-
"- "-
....
3.0 MAX.
Vee
TA
5.5 v
+125"C
INPUT VOL TAGE· Vin IN VOL TS
92C~-B736
(a)
(b)
Fig. 2 - Min./max. and typical switching transfercharacterstics of
the HUC04 Unbuffer Hex Inverter.
The characteristics desired in any high-quality amplifier are
high gain, good linearity, and wide bandwidth. The wide
bandwidth of the HCU04 is inherent in the QMOS process,
but its gain and linearity are a function of the transfer
parameters.
92CS-38375RI
The slope of the transfer curve is determined by the
transition of the PMOS and NMOS devices; this slope can
be evaluated with a sweep at the gate input. On a positive,
increasing voltage, the p channel is pinched off near the
positive Vee level. The n-channel drain current is enhanced
as the voltage increases from ground toward the Vee level.
In reverse, the p-channel current is increased with negativegoing input voltage, while the n-channel current is
decreased.
Fig. 1 - The HCU04 Hex Inverter: (a) functional diagram, (b)
internal schematic.
ICAN-7367
______________________________________________________________ 677
Application Notes "'---_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Families of curves showing typical drain characteristics for
both the PMOS and NMOS devices are shown in Fig. 3. The
characteristics are standard for nand p enhancement-type
devices. The drain currents in the p and n devices are
balanced by device design: the typical n-channel width is
800 microns; the typical p-channel width is 1800 microns.
This dimension compensates for the lower PMOS-channel
hole mobility.
3·5 V
25
characteristics may cause a deviation in peak drain current,
and produce a crossover offset in the transfer characteristic.
Typically, the offset is less than ±5% of the Vee range. This
figure represents what is called the "offset tolerance."
LOAD LINE CHARACTERISTICS
To better show how the HCU04 functions in its linear
transitions of the input-voltage range, the PMOS and
NMOS drain loadlines have been plotted, as the gate
voltage, V", is stepped, at incremental points of operation;
Fig. 4. The figure incl udes a 75-ohm loadline at Vec/2 = 2.5 V
as a poi nt of reference.
PMOS DRAIN VOLTAGE (Vd ) - VOLTS
(REFERENCE TO Vee= 5 VI
-r5______~4r-----_T3---~2f·5~,-r2-------~I------~
3V
"
E
z.!.
~t!
-5
;g 10
~~
OW
2.5 V
:0;0'
n.~
u
"
Z
UJ
'"
0
OUTPUT
S Ie ",AL
Q'JIi.SCEfil
CPE.~A11~r
PL II\jT
il
I·
INPLJl
:
~
~
SluNAL
o~-------------------·~~--------
o
"
__
I NPUT VOLTAGE - Vin
92CS-39735
Fig. 5 - Amplifier transfer characteristics of the HCU04 amplifiers.
LINEAR-AMPLIFIER MODEL
A linear-amplifier model of the HCU04 includes the inverting
amplifier and its associated input, output, and feedback
capacitance, as shown in Fig. 6. An external feedback
resistor, R" provides bias stability.
If the input coupling capacitor, C e , is sufficiently large, the
op-amp closed-loop gain is given by:
Ao '
A'b = _____________
_
1 +(1/8)(1 - Ao;)
where A o' is the open-loop gain, and 8 = R,/R., the feedback
resistor ratio.
Fig. 7 - Cireuilequivalent olthe HCU04 with two source generators
and no feedback.
Since the Vo ", node equation for the two generator equivalent
circuit is:
-gmp(V,,) - gm,(V,,) = Vou ,(1/R d , + 1/R dP + 1/Rc)
and
AOI
= Vout/Vin
-(gmp + gm,)
= _____________________
(1/R d, + 1/R dP + 1/Rc)
The source-generator and parallel conductances of the
NMOS and PMOS equivalent models may be simply added
into one equivalent.
___________________________________________________ 679
Application Notes
A single-generator model has no restrictions, provided the
equivalent circuit is a Teasonable linear approximation. A
simplified model of the circuit of Fig. 6, with associated
capacitance and biasing, is'shown .in Fig. 8. The singlemodel equivalent-current generator and effective source
impedance may be determined from the separate device
models, and is equal to:
gm
= gmp +
gmn
Determination of the gm and Rd parameters is based on
either direct evaluation from the drain family characteristics
of Fig. 3 or measu red data. From the curves of Fig. 3, gm is
l>ld/l> Vi', and Rd is the tangential l> Vd/l>ld slope on the V"
bias line at the point of operation. The simplest way to
determine gm is to measure A - Aoi when Rt is very large and
R. is small, e.g., 100 kilohm and 50 ohms, respectively.
When RL is much less than Rd:
Rd = Rdp Rd,/(RdP + Rd,)
A - -gm RL, and gm - A/RL
Vout
The gain is then measuredunderthe same conditions with
RL removed (open) and Rd as the effective load. For this
condition,
. A - -gmRd, and Rd - A/g m
I
I
A variety of amplifier gain conditions have been measured
for the circuit of Fig. 9 and, in some cases, calculations have
been made for gm and Rd. A tabulation of the results is
shown in Table I.
I
I
I
___________ J
R,
92CS-39739
Fig. 8· Simplified HCU04 circuit model with associated
capacitance and biasing.
All further references to gm and Rd imply a single-generator
model. It should be noted, however, that use of the twogenerator equivalent model does have practical merit in the
analysis of abnormal input-signal conditions or when
considering the effects of Vee and ground-terminal
impedance.
Vout
T
Fig. 9 - Simplified amplifier circuit configuration used to measure
gain and equivalent model characteristics. Table I shows
results.
Table I - Measured Amplifier-Gain Conditions for the Circuit of Fig. 9.
A.
Conditions:
Vee =
± 2.5 V. Icc - 6 mA
Measurement
Measurement
No.
AC/Oirect
(input)
R,
(kO)
Rt
(kO)
RL
(ohms)
Vout!Vin
(gain)
1
Direct
Direct
Direct
Direct
AC
AC
1
1
1
0.5
0.05
0.05
3
3
3
3
1000
none
75
75
75
none
2
2.4
2
3
4
5'
62
Calculated:
100
100
0.75
1.0
1.4
25
1. gm - A/RL - (1.4/75) = 0.0187 mhos
2. Rd - A/g m - (25/0.0187) = 1340 ohms
B.
Conditions:
Vee = ±3 V, Icc - 10 mA
Measurement
Measurement
No.
AC/Oirect
(input)
R,
(kO)
Rt
(kO)
RL
(ohms)
VoutlVin
l'
22
3
4
AC
Direct
Direct
AC
1
0.5
1
100
100
100
16
1.5
3
3
none
75
75
none
Calculated:
1. Rd - A/g m
-
(gain)
1.45
0.86
(16/0.02) = 800 ohms
680 ______________________________________________________________
2. gm - A/RL - (1.5/75) = 0.02 mhos
__
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Application Notes
general approximations. However, a simplified method of
determining HCU04amplifier performance in an open-loop
condition is possible, and useful, in many applications. A
basic open-loop equivalent-circuit model of the HCU04 is
shown in Fig. 11. This circuit is based on the equivalentcurrent-generator model of Fig. 8 with Rs = O. A large value
is used for the static bias resistor, RI, a value much larger
than the input source resistance.
Operation of the HCU04 in a multiple output configuration
is practical. A circuit using all six amplifiers in parallel is
shown in Fig. 10. The table of gain results for a variety of
conditions is shown in Table 11.
OPEN-LOOP GAIN
Unlike op-amp gain, HCU04 amplifier gain is not sufficiently
high or the output impedance low enough to allow simple
r-fE3~-O
V
7511
CAS L E
",
75
I
y- _~C,!£4J
o
92C5-39741
-vee
Fig. 10 - Six amplifiers of HCU04 in paralielline driver. Table II shows results.
Table II - Measured Results for Multiple Parallel Amplifier of Fig. 10
Conditions:
Vee = ±2.5 V, Icc - 32 mA
Measurement
Measurement
No.
R,
(kO)
RI
(kO)
RL
(ohms)
Vout/Vln
(gain)
1
2'
32
1
1
0.05
1
100
100
none
none
75
0.9
18
6.0
Calculated:
1. Rd - (A/gm) - (18/0.08) = 225 ohms
2. gm - A/RL - (6/75) = 0.08 mhos
}---'-~v"v\r----.---.--- Vout
92C5-39742
Fig. 11 - Basic equivalent circuit model for simplified gain, Z," and
Zoul calc ulations.
____________________________________________________________________ 681
Application Notes _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Using voltage-node equations with an assumed current
drive input, Ji" the matrix determinant for the circuit of Fig.
11 is:
I
(Vi+V,)
t" = (gm - V,)
(-V,)
(Vd + V,)
I
Vin '
Zin' = _ __
J in
where:
(V,)
The open-loop gain equation is:
A
Voul
V, - gm
Vin'
Vd + V,
(Vd + V,)
V·'
on -
= ___ = _____
Vd + V,
Therefore:
(Vd + V,)
The admittance terms include frequency, f, where w = 2m.
The complex terms are:
V, = (1/R,) + jwC,
Vi = jwCi
Vd = (1/Ad) + jwCo
For the low-frequency case, the gain is approximately:
A = - gm Rd II R,
where RdllR, is Rd in parallel with R,. The Rd term may be
modified to include Ad in parallel with external load RL.
In the case where there is no external RL and Rd«R" the
gain solution simplifies to:
A - -gm Rd
In the case where RL«R d , the gain solution simplifies to:
A - -gm RL
t"
Expanding the determinant and reordering the above
equation yields:
1
Zin' = _ _ _ _ _ _ __
Vi + V,(I-A)
The Zio' equation is a statement of all input impedances in
parallel at the input. It is important to note that the V,(I-A) is
the classic Miller-effect feedback factor. Since V,(I-A) can
be expanded to [(I-A)/R,] + jwC,(1-A), the effective Rin
becomes:
Rin = (I-A)/R,
and the effective Cin becomes:
Cin = [(I-A)C, + Cil
Both of these simplified expressions provide reasonably
accurate values of gm and Rd, and were used to obtain the
val ues in Table I. As the table shows, when the gain (A) was
measured as 16 times for the ± 3-volt Vee condition with no
load, and 1.5 times with a 75-ohm load, the solutions were
readily determined to be gm = 0.02 mhos and Rd = 800 ohms.
Lower signal levels and smaller values of RL will contribute
to better accuracy.
When the signal-source input has a high impedance (Rg or
R,), the input network configuration is equivalent to that
shown in Fig. 12. The RL network has an input corner-rolloff
frequency response, fi" of:
When the admittance term (Vd + V,) of the gain equation is
expanded, there is an output rolloff corner frequency, fool,
of:
where Ri,IIR, is Rin in parallel with R,.
21T(Rinll R,)Cin
The complete input-impedance equation for the network of
Fig. 12 is:
f out =
21T(C, + Cout) Rdll R,
RS
where, again, Rdll R, is Rd in parallel in A,.
It is important to note that the significance of this rolloff
corner will depend on the degree of feedback used and the
magnitude of Rg or R,. In the true open-loop condition,
where R, = 0 ohms, R, is large, and Rg is a line or generator
source of 50 or 75 ohms, the fout corner frequency is the
primary bandwidth-limiting factor. Where capacitance Cout
is equal to (C i + Co), as in the case of cascaded HCU04
stages:
C, + Cout = C, + Ci + Co = (1.8 + 6.0 + 4.5) pF = 12.3 pF
Rdll R, - Rd - 800 ohms
and
fout = 16.17 MHz
INPUT IMPEDANCE:
The input impedance of the HCU04 may be determined by
using an input driving point solution with a Ji, current
generator at the input node. The input impedance IS:
z'
in----
Vi in
(Ri, ~ ~
I+A
92C5- 39 745
Fig. 72 - Miller-feedback equivalent input circuit of the HCU04.
OUTPUT IMPEDANCE
The output-impedance of the HCU04 may be calculated by
using a current generator to drive the output terminal. The
resulting calculation should include the correct input
network termination.
In the open-loop condition, when R, or Rg is much less than
R" the output impedance is simply Rd in parallel with R,.
However, with R, terminated through Ag at the input, the
output impedance may be calculated for the general
682 ___________________________________________________________
Application Notes
3K
feedback condition. The second-order determinant was
used forthe input-impedance calculation and simply adding
R. at the input after finding Z'n'. The output impedance can
be calculated similarly, using the second order determinant,
by including the V. admittance term (or V. + Vo) in the y11
term of the matrix determinant; Le.:
/:;.= \(V.+V,+V')
(-V,)
75
I
I
O.II-'F
r----l
:
Rg
= J o (y11! /:;.)
I
Eg
~
50 I
When the output node is driven by a current (J o ):
VOU!
I
3K
(V, +Vd)
(gm - V,)
+ 3·5V
IHCU04
rv
1_ _ _
and
J
I
I
- 3.5 V
92C,,- )-')'44
ZOU!
V. + V, + V,
= _ _ _ _ _ _ _ _ _ _ __
(Vd + V,)[V. + V, + V,(1 - A)]
This equation may be reduced to a simple form for low
frequencies:
RdllR,
Zout =
Fig. 13 - Amplifier circuit for gain-bandwidth measurements.
This value is in good agreement with the measured gainbandwidth (GBW) response curve shown in Fig. 14. In
addition, as noted above, the high-frequency GBW response
includes the input corner-rolloff frequency resulting from
the Miller-effect RC input network of Fig. 12.
1 - A(R.!(R. + R,))
where Rdll R, is Rd in parallel with R,.
---x--- CALCULATED
f-
~MEASURED
0-
FEEDBACK EQUATIONS AND GAIN-BANDWIDTHCIRCUIT MEASUREMENTS
The preceding equations will be very useful in applying the
HCU04, particularly in low-frequency applications.
However, it is important that the user does not over-simplify
solutions and drop terms before evaluating their
significance. The general purpose of this Note is to provide
fully useful equations and to impress on the user that the
standard op-amp equations, for the most part, do not apply
well to the HCU04 amplifier.
Because some degree of feedback is desired for good
linearity, the need to consider performance with feedback is
necessary. An essential consideration is the wideband
amplifier performance. The gain-bandwidth response and
phase considerations are important, and are treated, with
examples, in the following section.
-,~--------------------------~"X,
-21-
'"~ -, lI
~ -4 -
- 3 dB
PO INT
"?4.2
",H,
W
W
DO
'"o
W
0r-~~~~~--------------
The slight peaking noted at 10 MHz is not unusual in
wideband circuits with feedback. In the range of 10 MHz
and beyond, peaking or ripple effects are commonly present
in the GBW response because of lead inductance and stray
capacitance both in the signal links and in the filtering
components. Care must be exercised in circuit layout and in
component specification, as an excess of peaking will
cause undesired overshoots and ringing on pulse edges.
___
~ -45
- 90" AT
MHz
2.4.2.~
II
100
IK
10K
lOOK
FREQU(r
'"
10M
100M
'~'(- H~
92CS-39746
Fig. 15 - Phase measurement showing phase shift for the circuit of
Fig. 13.
Additional gain-bandwidth curves are shown in Fig. 16.
Note that the high frequency rolloff is a furiction of load and
feedback, but is typically 6-dB per octave. The bandwidth
can be extended at a sacrifice of gain. Bandwidth extending
may be done with loading or peaking. Both RC and RLC can
be used to peak the input signal.
684 ______________________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Application Notes
20~--------------------~--~~
"0
I
Z
«10
'"
o
-5L-~~-4~~6~8~--~--~4~6~8~--~~4~6~8~--~~4~6~B~
lOOK
10K
1M
10M
100M
BANDWIDTH (BW), FREQUENCY-Hz
CURVE
RS
a
1K
1K
250
R,
1M
1M
1M
7.SK
1.5K
RL
1K
1K
1K
75
92C5-39917
Fig. 16 - Linear-amplifier gain/bandwidth curves.
GENERAL APPLICATIONS OF THE 74HCU04
Video Switch
An example of a video-switching video-amplifier is shown
in Fig. 17. The CD74HC4052 is a QMOS dual4-input analog
multiplex switch that is used to direct one of four inputs to
the HCU04 video amplifier. An LED indicator shows which
channel has been selected. One amplifier of the HCU04 is
used as a buffer amplifier that drives four other amplifiers in
parallel. These four amplifiers, in turn, drive a 75-ohm cable
and load.
The low output impedance and video-bandwidth capability
of the HCU04 suggest a wide variety of applications in linear
signal amplifiers. Line-driver capability may be achieved by
paralleling output amplifiers and applying feedback to
assure low output impedance. The HCU04 may be used for
both linear and digital data transfer. Real-time feedback
conditions may be modified by using transmission-gate
switching with such devices as the QMOS CD74HC4016 or
CD74HC4052.
OM OS CD74HC4052 CD74HCU04 VIDEO SWITCH CIRCUIT
0.1
100 K
-P
lOOK
voo
+4.5V
y+
33
. ONE BUFFER AMP. WITH 2X GAIN
.. PARALLELED AMP, TO DRIVE 7S 0 LINE
J. 0.1~F
TYPICAL DATA
•
•
•
•
+4.5V)'
r-
-l--l
t---O A
,-DB
INPUT TO
1 OF 4
CHANNELS
SHOWN
1--0 IN H
l--l-----o--<>
;;:~
l
-I
• OIFF. GAIN
• DIFF. PHASE
.100
20 mA
• GAIN
2X
2 \(t 08 Vpp
0.75 (C!. 0.8 Vpp
22~p}
75 n
CABLE
=75
I
r-=- -
l~
L
8 W, (-3 dB) 50 MHz
FEEDTHRQUGH -57 dB
CROSSTALK
-56 dB
NOISE -55 dB
3 K
~--~----~
I
• DUAL 4 TO 1 SWITCH WITH VIDEO AT ONE OUTPUT & LED INDICATOR
AT PAlAEO OUTPUT
• CD74HC4052 Ti'lANSMISSIDN GATE SWITCH
• CD74HCU04 UNBUFFERED HEX INVERTER
330
- 4.5 V
VEE
v+
1------"v'V\~() y-
33
- 4.5 V
92CM· 40005
Fig. 17 - Video-switch circuit employing QMOS CD74HC4052 and
___________________________________________________________________
HCU04.
685
Application Notes _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Bandwidth peaking is accomplished in the first video
amplifier by the trimmer capacitor. One amplifier remains
open for use as a parallel-signal amplifier, e.g., for audio
signals. However, any unused amplifier should have the
input returned to v+ (Vee) or v- (GND) to eliminate current
drain. The peaking circuits provide for an exceptional 50MHz gain-bandwidth capability at 2X gain. Other typical
data is shown in the table accompanying the figure.
Audio/Tone Amplifier
The circuit of Fig. 18 is an audio or tone driver for highefficiency, 32-ohm speakers or a headset. Although the
power output is limited by the 5-volt supply, the use of the
HCU04 as a tone amplifier or beeper is practical with this
type of circuit.
t- Vee" 5·0V
7.5 K
'----1
i
;HCU04
~
~
150
LED
=
(0)
92CS-39926
Fig. 19 - (a) LED driver.
Note: For circuits (a) through (e), +Vee = 5 V, -Vee =
ground.
+
7·5 K
- vee: GND
600 mA T'I'PICAL
2Nt.10~ Oh E.QLJIV·
3"..:::iL
HEA[,5E.TOR
SF-EAKER
Jin:= 0-4 Vpp
FOR MAX. Ll NEAR
MAX. Vout
3.0 Vpp
OUTPUT
(b)
"
PARALLEL
92.CJ- 399'25
Fig. 18 - Audio/tone amplifier.
Other Linear Applications
92C5-39927
Fig. 19 - (b) Lamp, solenoid, or relay driver.
+
The circuits of Fig. 19(a) through 19(h) are general
applications of the HCU04 in both the linear and switching
modes. With 25 mA of drive capability, the HCU04 amplifier
can directly drive LED indicators or provide high-current
base drive for a transistor lamp, solenoid, or relay driver, as
shown in Figs. 19a and 19b.
Fig. 19(c) shows a possible use of the HCU04 with photocells
or thermistors in a sensor amplifier application for light or
heat control.
9ZCS - 39928
The circuit of Fig. 19(d) shows an HCU04 driving a TTL
2-input NAND gate. This circuit is employed where a TTL
interface is needed.
Fig. 19(e). the simplest form of a low-pass filter, shows a
capacitor-feedback arrangement in use with the HCU04
amplifier. Additional poles may be added with additional
filter stages. I n the example shown, the gain is unity and the
3-dB rolloff frequency is 5 kHz.
An emitter-follower may be coupled to the output and
included in the feedback loop of the HCU04 amplifier, as
shown in Fig. 19(f). The use of positive and negative powersupply voltages is optional. As another option, the output
may be changed to a complementary-symmetry drive. With
the emitter follower shown, the base-emitter offset of 0.7
volts reduces the linear dynamic range of the output drfve
signal.
Fig. 19 - (c) Photocell or thermistor driver.
1---1
TTL
~
HCU041
1
I
I
I
240
-Q
Id 1
92es- 39929
Fig. 19 - (d) TTL driver.
The circuit of Fig. 19(9) is an adjustable current sink in
which the current, Ie, in the outputtransistor, is approximately
equal to 2.5/R. Fig. 19(h) shows a more general circuit for
adjusting both voltage and current.
92CS - 39930
Fig. 19 - (e) Unity gain low-pass filter: 3-dB rolloff - 5 kHz.
686 _________________________________________________________
Application Notes
Vee" +2·5V
2N2102
OR
EQtJIV·
The VCO circuits of Figs. 20(c) and 20(d) are simpler,
higher-frequency-range circuits with oscillator capability
up to 25 MHz. The circuit of Fig. 20(d) shows a method of
compensating effects of power-supply frequency change
by adding some of the VCO change into the VCO input. At a
center frequency of 5 MHz, for V,n = 0 V, the power-supply
change is effectively cancelled for changes of ±1 0% Vee.
4.7M
V\1\r~r---V
V ou 1
DC VOLT AGE
(II
-V CC =-2.5V
92C5-39922
Fig. 19 - (f) Low
ZOUT
amplifier.
+ vee" + 2.5V
")O--'-......~t--{)Jl
I K
~~:::;rl=:[
/~~~H'
I
VAR~CTOR
BIA.;:- TO
~~~.\~o
1-
IUpF
-=-\~
-=-
OPTIONAL
VARACTOR
VARACTQR
47PF
veo
CONTR OL
CONT"' ..... L
(0)
Fig. 20 - (a) 3.58-MHz clock or VCO circuit.
2N~I02
OR
Note: For all Fig. 20 circuits, +Vee = 5 V,
- Vee = ground.
EQl..J IV
Q·0033p.F
,--If---..----------<--.'
(91
-VCc c
-
RAMP OUT
" - " ' - - - " PULSE OUT
25V
92C5-39~.::3
I N914
Fig. 19 - (g) Fixed-current-source driver.
+
vCC=+2 5V
lN914
{ bl
POSITIVE RAMP AND PULSE
92(5- 39918
LOW AOJ RANGE
110KHzATOV
VIN: -2 TO 2 V
FREO: 180 KHz TO 15 KHz
100 K
NEGATIVE RAMP AND PULSE
HIGH AOJ RANGE
100KHzAT5V
VIN: 2.6 V TO 7 V
FREQ: 15 KHz TO 180 KHz
Fig. 20 - (b) VCO pulse and ramp generator.
-VCC=-2.5V
20 pF
92C5-39924
Fig. 19 - (h) Adjustable
sink.
IOW-ZOUT
n-
dc source or adjustable current
JL-o
__II--
Oscillator Applications
The circuit of Fig. 20(a) is a 3.58 MHz clock generator that
may be VCO controlled by replacing the 10 pF capacitor
with a varactor.
Uniformity of balance in the HCU04 leads to better
frequency-range control in applications where the
frequency is crossover dependent. The circuit of Fig. 20(b)
can be changed in polarity of pulse and ramp output by
changing the polarity of the 1N914 diode. The result is a -2V
to +2V adjustable VCO with positive ramp and pulse outputs
in the low switch position. In the high position, negati .. e
ramp and pulses are generated with a 2.6 V to 7 V control
voltage. In both switch positions, the frequency range is 15
kHz to 180 kHz.
4 SV
.
20 ns
IN914
veo
RANGE
FhEQ: 5 TO 25 MHz
Vin; 2.5 T06V
{el
92CS-39920
Fig. 20 - (c) High-frequency VCO pulse generator.
___________________________________________________________________ 687
Application Notes _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
><>--1~- v ou•
IK
IK
IN914
veo RANGE
fREQ.; 1·7 TO 10·5 MHz
V in ="'1·5 TO-5V
AT V In =OV,FREQ=4.8MHz
(dl
92C5-39921
Fig. 20 - (d) Vee -compensated VCO.
SUMMARY
The characterization and applications of the HCU04 shown
illustrate how simple, high"speed CMOS device can be
more· widely used in both linear and digital circuits. Many
applications require linear interface for buffer amplifiers,
sensors, gain amplifiers, and multiple-line inverter circuits.
The power gain of the HCU04 is very. high, although the
voltage gain is typically less than 20. This feature makes the
HCU04 an excellent driver for bipolar transistors driving
lamps, relays, and solenoids.
REFERENCES
State File No. 1655. The notation CD54/74HCU04
denotes two devices, the CD54HCU04F, the Hex Inverter
in a ceramic package, and the CD74HCU04E, the Hex
I nverter in a plastic package. Both devices are
electrically identical. The riotation HCU04 used in this
Note refers to either device.
ACKNOWLEDGMENTS
Substantial portions of the gain-bandwidth technical
characterization' and related circuits in this Note were
provided by J. Nadolski;· HCU04 device-parameter
Information was provided by B. Petryna and R. Funk.
1. 'CD54174HCU04, Hex Inverter Data Sheet; RCA Solid
688 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
_ _ _ _ _ _ _ _ _ _ _ ___
Dimensional Outlines
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 689
Dimensional Outlines _______________________-,-_ _ _ _ __
. lfiw'mr ·
L
Dual-In-Line Plastic Packages
,~.
I
U
~
:LfA1
SEATING PLANE
?i
. n1-l
&
INDEX AREA
c
I
B
1
J
~I-.
,,3 4
:.J
BOTTOM
'I'~ --------,-t
EJTfTII
e--
81
~
T
VIEW
(E) Suffix (JEDEC MS-001-AC)
14-Lead Dual-In-Llne Plastic Package·
~YMBOL
INCHES
MIN.
MAX.
0.210
0.015
0.115
0.195
0.014
0.022
0.045
0.070
0.008
0.015
0.725
0.795
0.005
0.300
0.325
-
A
A1
A2
B
B1
C
D
-
-
D1
E
E1
e
eA
eB
L
0.240
0.280
0.100 BSC
0.300 BSC
0.430
0.115
0.160
-
N
I14
MILLIMETERS
MIN.
-
MAX.
5.33
0.39
-
2.93
0.356
1.15
4.95
0.558
1.77
0.204
18.42
0.13
7.62
0.381
NOTES
9
9
3
4
12
5
20.19
8.25
6.10
7.11
2.54 BSC
7.62 BSC
2.93
I
14
6,7
8
9
10
9
10.92
4.06
11
Noles:
1. Reier 10 JEDEC Publication No. 95JEDEC Reglslered and
Siandard Outlines lor Solid Slate Products, lor rules and
general Inlormallon concerning registered and slandard
oullines, In Secllon.2.2.
2. Prolruslons (flash) on Ihe base plane surface shall not
exceed 0.010 In. (0.25 mm).
3. The dimension shown Is lor lull leads. "Hall" leads are
optional allead posilions
N N
1,N, 2 2+1•
4. Dimension D does nol Include mold flash or prolruslons.
Mold flash or prolruslons shall nol exceed 0.010 In. (0.25
mm).
5. E Is Ihe dimension to Ihe outside 01 Ihe leads and Is
measured wllh Ihe leads perpendicular to the base plane
(zero lead spread).
6. Dimension E1 does nollnclude mold flash or prolruslons.
7. Package body and leads shall be symmelrlcal around
cenler line shown In end view.
8. Lead spacing, e shall be non-cumulallve and shall be
measured allhe lead lip. This measuremenl shall be made
belore Insertion Inlo gauges, boards or sockels.
9. This Is a basic Installed dimension. Measurement shall be
made wllh Ihe device Inslalled In Ihe sealing plane gauge
(JEDEC Outline No. GS-3, seating plane gauge). Leads
shall be In Irue posilion wllhln 0.010 In. (0.25 mm) dlameler
lor dimension eA'
10. eB Is Ihe dimension 10 Ihe outside 01 Ihe leads and Is
measured al Ihe lead tips belore Ihe device Is Installed.
Negallve lead spread Is nol permilled.
11. N Islhe maximum number 01 lead posilions.
12. Dimension D1 al Ihe lell end 01 Ihe package musl equal
dimension D1 allhe right end ollhe package wllhln 0.030
In. (0.76 mm).
13. Polnled or rounded lead lips are prelerred to ease Inserllon.
14. For aulomallc Insertion, any raised Irregularlly on Ihe lop
surface (slep, mesa, elc.) shall be symmelrlcal aboullhe
laleral and longlludlnal package cenlerllnes.
92CS-39901
(E) Suffix (JEDEC MS-001-AE)
20-Lead Dual-In-Llne Plastic Package
(E) Suffix (JEDEC MS-001-AA)
16-Lead Dual-In-Llne Plastic Package
~YMBOL
INCHES
MIN.
MAX.
A
-
0.210
A1
A2
B
0.015
0.115
-
B1
C
D
D1
E
E1
e
eA
eB
L
N
0.195
0.022
0.070
0.015
0.840
0.014
0.045
0.008
0.745
-
0.005
0.300
0.240
0.325
0.280
0.100 BSC
0.300 BSC
0.430
0.115
0.160
-
I
16
MILLIMETERS
MIN.
MAX.
-
5.33
-
0.39
2.93
0.356
1.15
0.204
18.93
0.13
7.62
6.10
NOTES
SYMBOL
9
9
A
4.95
0.558
1.77
0.381
21.33
-
3
4
8.25
7.11
12
5
6,7
2.54BSC
7.62 BSC
10.92
2.93
4.06
'8
9
10
9
16
11
-
I
A1
A2
B
B1
C
D
INCHES
MAX.
MIN.
0.21'0
-
-
0.015
0.115
0.014
0.045
0.008
0.195
0.022
0.070
0.015
E1
e
eA
0.925
0.005
0.300
0.240
0.100
0.300
eB
L
0.115
D1
E
N
-
1.060
0.325
0.280
BSC
BSC
0.430
0.160
I20
92CS-39900
6~
_____________________________________________
MILLIMETERS
MIN.
MAX.
-
0.39
2.93
0.356
1.15
0.204
9
-
9
4.95
0.558
1.77
0.381
26.9
23.5
0.13
8.25
7.62
7.11
6.10
2.54BSC
7.62BSC
10.92
4.06
2.93
-
-
NOTES
5.33
I
20
3
4
12
5
6,7
8
9
10
9
11
92CS-39997
~-------------------
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - D i m e n s i o n a l Outlines
Dual-In-line Plastic Packages
Notes:
1. ReIer to JEDEC Publlcallon No. 95 JEDEC Registered and
Standard Oulllneslor Solid State Products, lor rules and
general Inlormallon concerning registered and standard
oulllnes, In Secllon 2.2.
2. Protrusions (Ilash) on the base plane surface shall not
exceed 0.010 In. (0.25 mm).
3. The dimension shown Is lor lull leads. "Hall" leads are
opllonal at lead posillons
N N
1, N,
(EN) Suffix (JEDEC MS-001-AF)
24-Lead Dual-In-Llne Plastic Package
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN.
MAX.
MIN.
MAX.
A
-
0.210
-
5.33
9
Al
0.015
-
0.39
-
9
A2
B
0.115
0.195
2.93
4.95
0.014
0.022
0.356
0.558
Bl
C
0.045
0.070
1.15
1.77
0.008
0.015
0.204
0.381
3
0
1.125
1.275
28.6
32.3
4
01
0.005
-
0.13
-
12
E
0.300
0.325
7.62
8.25
5
El
e
0.240
0.280
6.10
7.11
6,7
eA
eB
L
0.100 BSC
0.300 BSC
0.115
N
I24
2.54 BSC
7.62 BSC
0.430
-
0.160
2.93
8
9
10.92
I
4.06
24
10
9
11
2 2+ 1.
4. Dimension 0 does not Include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 In. (0.25
mm).
5. E Is the dimension to the outside 01 the leads and Is
measured with the leads perpendicular to the base plane
(zero lead spread).
6. Dimension El does not Include mold flash or protrusions.
7. Package body and leads shall be symmetrical around
center line shown In end view.
8. Lead spacing e shall be non-cumulallve and shall be
measured at the lead lip. This measurement shall be made
belore Insertion Into gauges, boards or sockets.
9. This Is a basic Installed dimension. Measurement shall be
made with the device Installed In the sealing plane gauge
(JEDEC Oulllne No. GS-3, sealing plane gauge). Leads
shall be In true posillon within 0.010 In. (0.25 mm) diameter
lor dimension eA.
10. eB Is the dimension to the outside 01 the leads and Is
measured at the lead lips belore the device Is Installed.
Negallve lead spread Is not permitted.
11. N Is the maximum number 01 lead posillons.
12. Dimension 01 at the left end 01 the package must equal
dimension 01 at the right end 01 the package within 0.030
In. (0.76 mm).
13. Pointed or rounded lead tips are prelerred to ease Insertion.
14. For automatic Insertion, any raised Irregularity on the top
surface (step, mesa, etc.) shall be symmetrical about the
lateral and longitudinal package centerllnes.
92CS-39943
(E) Suffix (JEDEC MS-011-AB)
28-Lead Dual-In-Llne Plastic Package
(E) Suffix (JEDEC MS-011-AA)
24-Lead Dual-In-Llne Plastic Package
~YMBOL
INCHES
MIN.
MAX.
0.250
MILLIMETERS
MIN.
MAX.
-
NOTES
SYMBOL
INCHES
MIN.
MAX.
0.250
MILLIMETERS
MIN.
MAX.
-
NOTES
A
-
6.35
9
A
6.35
9
0.015
-
0.39
-
-
Al
9
A1
0.015
-
0.39
-
9
A2
B
0.125
0.195
3.18
4.95
0.125
0.195
3.18
4.95
0.014
0.022
0.356
0.558
A2
B
0.014
0.022
0.356
0.558
B1
C
0.030
0.008
0.070
0.77
0.070
0.77
1.77
0.204
Bl
C
0.030
0.D15
1.77
0.381
0.008
0.015
0.204
0.381
35.1
3
3
0
1.150
1.290
29.3
32.7
4
0
1.380
1.565
39.7
4
01
E
0.005
-
0.13
-
12
01
0.005
-
0.13
-
12
0.600
0.625
15.24
15.87
5
E
0.600
0.625
15.24
15.87
5
El
e
0.485
0.580
12.32
14.73
6,7
El
e
0.485
0.580
12.32
14.73
6,7
eA
eB
L
N
0.100 BSC
0.600 BSC
0.115
I
24
2.54 BSC
15.24 BSC
0.700
-
0.200
2.93
I
24
8
9
eA
17.78
10
5.08
9
eB
L
11
N
92CS-40000
0.100 BSC
0.600 BSC
0.115
I
28
2.54 BSC
15.24 BSC
0.700
-
0.200
2.93
17.78
I
28
5.08
8
9
10
9
11
92CS-40001
___________________________________________________________________ 691
Dimensional Outlines
NOTES:
Refer to JEDEC Publication No. 95 for Rules for Dimensioning
Axial Lead Product Outlines.
1. When this device Is supplied solder-dipped, the maximum
lead thickness (narrow portion) will not exceed 0.013 In. (0.33
mm).
2. Leads within 0.005 In. (0.127 mm) radius of True Position (TP)
at gauge plane with maximum material condition.
3. eA applies In zone L2 when unit Is Installed.
4. Applies to spread leads prior to Installation.
5. N Is the maximum quantity of lead pOSitions.
6. N1 Is the quantity of allowable missing leads.
(F) Suffix (JEDEC MO-001-AB)
14-Lead Dual-In-Line Frit-Seal Ceramic Package
~YMBOL
A
A1
B
B1
C
D
E
E1
e1
eA
L
L2
a
N
N1
°1
S
INCHES
MIN.
MAX.
0.155
0.200
0.020
0.050
0.014
0.020
0.050
0.065
0.008
0.012
0.745
0.770
0.300
0.325
0.240
0.260
0.100 TP
0.300 TP
0.150
125
0.
0.000 1 0.030
0'
15'
14
0
0.075
0.040
0.065
0.090
I
MILLIMETERS
NOTES
MIN.
MAX.
3.94
5.08
0.51
1.27
0.356
0.508
1.27
1.65
0.204
0.304
1
18.93
19.55
7.62
8.25
6.10
6.60
2
2.54 TP
7.62 TP
2,3
3.18
3.81
0.00
0.76
4
0'
15'
1
14
5
6
0
1.90
1.02
1.66
2.28
92SS-4296R3
I
(F) Suffix
20-Lead Dual-In-Line Frit-Seal Ceramic Package
INCHES
MIN.
MAX.
0.120
0.250
0.020
0.070
0.016
0.020
0.028
0.070
0.008
0.012
0.942
0.990
0.300
0.325
0.240
0.280
0.100 TP
0.300 TP
0.200
0.100 1
0.000
0.030
O'C
1S'C
20
0
(F) Suffix (JEDEC MO-001-AC)
16-Lead Dual-In-Line Frit-Seal Ceramic Package
~YMBOL
A
A1
B
B1
C
D
E
E1
e1
eA
L
L2
a
N
N1
°1
S
INCHES
MIN.
MAX.
0.155
0.200
0.020
0.050
0.014
0.020
0.065
0.035
0.012
0.008
0.785
0.745
0.300
0.325
0.240
0.260
0.100 TP
0.300 TP
0.150
125
0.
0.000 1 0.030
15'
0'
16
0
0.075
0.040
0.015
0.060
I
MILLIMETERS
NOTES
MIN.
MAX.
5.08
3.94
1.27
0.51
0.508
0.356
0.69
1.65
0.304
1
0.204
19.93
18.93
7.62
8.25
6.10
6.60
2.54 TP
2
7.62TP
2,3
3.18
3.81
0.00
0.76
0'
15'
4
1
16
5
0
6
1.90
1.02
1.52
0.39
1
92CM-15967R4
(F) Suffix (JEDEC MO-01S-AA)
24-Lead Dual-In-Line Frit-Seal Ceramic Package
INCHES
MILLIMETERS
MILLIMETERS
NOTES
NOTES
~YMBOL
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
A
A
0.120
6.30
3.10
6.30
0.250
3.10
0.070
1.77
1.77
0.020
0.51
0.51
A1
A1
B
B
0.407
0.016
0.020
0.407
0.508
0.508
0.72
0.028
0.070
0.72
1.77
1.77
B1
B1
C
0.008
0.012
0.304
C
1
1
0.204
0.304
0.204
D
D
23.93
1.200
1.290
30.48
32.76
25.15
E
E
7.62
0.600
0.625
15.24
15.87
8.25
14.73
6.10
7.11
0.515
0.580
13.09
E1
E1
2.54 TP
2
0.100 TP
2.54 TP
81
2
e1
7.62 TP
2,3
0.600 TP
15.24 TP
2,3
eA
eA
L
2.54
5.00
L
0.200
2.54
5.00
100
0.
0.00
0.76
0.000 1
0.030
0.76
0.00
L2
L2
a
O'C
4
a
O'C
15'C
O'C
4
1 15'C
1 15'C
N
20
5
N
24
24
5
6
0
6
0
0
N1
N1
1.90
1.02
0.075
0.040 1 0.075
1.02
1 1.90
°1
°1
0. 040 1
S
0.040
0.100
1.02
S
0.040
0.100
1.02
2.54
1 2.54
92CS-26938R3_
92CM-35137R1
692 __________________________________________________________________
SYMBOL
_______________________________ Dimensional Outlines
Dual-In-Line Surface Mount Plastic Packages
NOTES:
---iT
E
..
1. Refer to applicable symbollisl.
2. Dimensioning
.-
~
------I
D
.
7
/
--j
c
i
.r-----,
T
B
(M) Suffix (JEDEC MS-012-AB)
14-Lead Dual-In-Line Surface-Mount Plastic Package
SYMBOL
INCHES
MiN.
MAX.
per
ANSI
shall not exceed .15mm (.006 in.).
~_~I~L.l[
1-.
.0c!~
-
tolerancing
3. "T" is a reference datum.
4. "0" and "E" are reference datums and do not include
mold flash or protrusions. Mold flash or protrusions
I
SEATING PLANE
1-
and
Y14.5M-1982.
MILLIMETERS
MIN.
MAX.
NOTES
5. The chamfer on the body is optional. If it is not present. a visual index feature must be located within the
cross hatched area.
6. "L" is the length of terminal for soldering to a
substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Controlling dimensions: MILLIMETERS.
(M) Suffix (JEDEC-MS-012-AC)
16-Lead Dual-In-Line Surface-Mount Plastic Package
INCHES
~YMBOL
MILLIMETERS
MIN.
MAX.
MIN.
MAX.
NOTES
A
0.0532
0.0688
1.35
1.75
A
0.0532
0.0688
1.35
1.75
A1
B
0.0040
0.0138
0.0098
0.0192
0.10
A1
B
0.0040
0.0098
0.10
0.25
0.35
0.25
0.49
0.35
0.49
0.0075
0.0098
0.19
0.25
C
0.0138
0.0075
0.0192
C
0.0098
0.19
0.25
0
0.3367
0.3444
8.55
8.75
4
0
0.3859
0.3937
9.60
10.00
4
E
0.1497
0.1574
3.80
4.00
4
E
0.1497
0.1574
3.80
4.00
4
0.050 BSC
e
H
h
2284
0.
0.0099
L
0.016
0.2440
1
N
"
0.0196
5.80
0.25
0.050
0.40
114
0'
1.27 BSC
8'
0'
e
6.20
1
1j
0.50
5
H
h
2284
0.
0.0099
1.27
6
L
0.016
7
N
Noles: 1,2,3,8,9
92CS-38924R1
(M) Suffix (JEDEC-MS-013-AC)
20-Lead Dual-In-Line Surface-Mount Plastic Package
~YMBOL
INCHES
MIN.
MAX.
MILLIMETERS
MAX.
MIN.
NOTES
0.2440
5.80
0.0196
0.25
0.050
0:40
1
16
1
0"
ex
8'
1.27 BSC
0.050 BSC
8"
6.20
1
5
1.27
6
7
1i
0°
0.50
8°
Notes: 1, 2, 3, 8, 9
92CS-38925R1
(M) Suffix (JEDEC MS-013-AD)
24-Lead Dual-In-Line Surface-Mount Plastic Package
~YMBOL
IN HES
MAX.
MIN.
MILLIMETERS
MIN.
MAX.
NOTES
A
0.0926
0.1043
2.35
2.65
A
0.0926
0.1043
2.35
2.65
A1
B
0.0040
0.0138
0.0118
0.10
0.30
0.0040
0.0118
0.10
0.30
0.0192
0.35
0.49
A1
B
0.0138
0.0192
0.35
0.49
C
0.0091
0.0125
0.23
0.32
C
0.0091
0.0125
0.23
0.32
0
E
e
H
h
L
0.4961
0.5118
12.60
13.00
4
0
0.5985
0.6141
15.20
15.60
4
0.2914
0.2992
7.60
7.40
1.27 BSC
4
E
0.2914
0.2992
7.40
7.60
4
0.050 BSC
0.394
0.419
10.00
0.010
0.029
0.25
0.050
0.40
0.016
N
ex:
0'
Notes: 1,2,3,8,9
1
20
1
8'
0'
1
2f
e
0.050 BSC
1.27 SSC
10.65
0.75
H
0.394
0.419
10.00
5
h
0.010
0.25
1.27
6
L
0.016
0.029
0.050
7
N
8'
92CS-38926R1
ex:
0'
Notes: 1, 2, 3, 8, 9
1
124
8'
0.40
0'
10.65
1
2f
0.75
5
1.27
6
7
8'
92CS-39037R1
___________________________________________________________________ 693
694 _________________________________________________________________
RCA Sales Offices, Authorized
Distributors, and Manufacturers'
Representatives
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 695
Sales Offices, Distributors, and .Representatives _____________________
Sales Offices
EUROPE
UNITED STATES
Alabama
RCA
Park Plaza
303 Williams Avenue
Suite 133
Huntsville, AL 35801-6001
Tel: (205) 533-5200
TACNET: 8-721-1110
Kansas
RCA
Suite 208
8575 West 11 Oth Street
Overla nd Park, KS 66210-2620
Tel: (913) 345-2224
TACNET: 8-422-6371
Arizona
RCA
6900 E. Camelback Road
Suite 460
Scottsdale, AZ 85251-2441
Tel: (602) 947-7235
Massachusetts
RCA
Suite 101
One Newton Exec. Park
Newton, MA 02162-1435
Tel: (617) 969-0141
TACNET: 8-341-1210
California
RCA
3150 De La Cruz Blvd.
Bldg. D, Suite 206
Santa Clara, CA95054-2486
Tel: (408) 748-0933
TACNET: 8-528-1605
Michigan
RCA
30400 Telegraph Road
Birmingham, MI48010-3095
Tel: (313) 644-1151
TACNET: 8-438-1281
RCA
Suite 420
4827 No. Sepulveda Blvd.
Sherman Oaks, CA 91403-1993
Tel: (818) 783-3955
TACNET: 8-522-4200
Minnesota
RCA
3600 West 80th Street
Suite 515
Minneapolis, MN 55431-1070
Tel: (612) 835-2004
RCA
17731 Irvine Blvd., Suite 104
Magnolia Plaza Bldg.
Tustin, CA 92680-3235
Tel: (714) 832-5302
TACNET: 8-542-1120
New Jersey
RCA
485B Route 1, South
Iselin, NJ 08830-3013
Tel: (201) 750-9000
TACNET: 8-325-6090
Colorado
RCA Corp.
6767 So. Spruce Street
Englewood, CO 80112-1284
Tel: (303) 740-8441
Florida
RCA
P.O. Box 12247
Lake Park, FL 33403-0247
Tel: (305) 626-6350
TACNET: 8-722-1291
Georgia
RCA
Suite 304
2872 Woodcock Blvd.
Atlanta, GA 30341-4002
Tel: (404) 452-2355
TACNET: 8-727-2344
Illinois
RCA
One Pierce Place
Suite 325, West Tower
Itasca, IL 60143-2681
Tel: (312) 250-0070
TACNET: 8-439-6160
Indiana
RCA
Mark I - Suite 660
11611 N. Meridian Street
Carmel, IN 46032-9487
Tel: (317) 267-6375
TACNET: 8-422-6375
RCA
700 E. Gate Drive
Mt. Laurel, NJ 08054
Tel: (609) 338-5042
TACNET: 8-222-4473
New York
RCA
160 Perinton Hill Office Park
Fairport, NY 14450-3665
Tel: (716) 223-5240
North Carolina
RCA
2000 Regency Parkway
Suite 150
Cary, NC 27511-8506
Tel: (919) 481-4221
RCA
17000 Dallas Parkway
Suite 100
Dallas, TX 75248-1921
Tel: (214) 733-0800
TACNET: 8-639-1260
Belgium
RCA, s.a.
Mercure Centre
Rue de la Fusee 100
1130 Brussels
Tel: 021720.89.80
Virginia
RCA
1901 N. Moore Street
Arlington, VA 22209-1766
Tel: (703) 558-4161
TACNET: 8-232-4162
France
RCA,s.a.
2-4, Avenue de L'Europe
78140 Velizy
Tel: 33-1-39.46.56.56
CANADA
Ontario
RCA Inc.
411 Roosevelt Avenue
Suite 203A
Ottawa, Ontario K2A 3X9
Tel: (613) 728-0031
Germany
RCA GmbH
Ridlerstrasse 35A
8000 Munchen 2
West Germany
Tel: 089/5026014
RCA GmbH
Justus-von-Liebig-Ring 10
2085 Quickborn
West Germany
Tel: 04106/613-0
ASIA PACIFIC
Hong Kong
RCA International, Ltd.
13th Floor, Fourseas Bldg.
208-212 Nathan Road
Tsimshatsui, Kowloon
Tel: 3-7236339
RCA GmbH
Zeppelinstrasse 35
7302 Ostfildern 4
West Germany
Tel: 0711/454001
Singapore
RCA International, Ltd.
24-15 International Plaza
10 Anson Road
Singapore 0207
Tel: 2224156
Italy
RCA SpA
Viale Milanofiori L 1
20089 Rozzano (MI)
Tel: (02) 8242006
Taiwan
RCASSD
Room 1103, No. 600
Ming Chuan East Road
Taipei
Tel: (02) 7169310
Spain
RCA S.A.
Monte Esquinza 28
28010 Mad rid 4
Tel: 01/44211 00
LATIN AMERICA
Sweden
RCA International Ltd
P.O. Box 3047
Hagalundsgatan 8
17103 Solna 3
Tel: 08/834225
Ohio
RCA
3700 Corporate Drive
Suite 101
Columbus, OH 43229-1739
Tel: (614) 899-9009
TACNET: 8-448-1210
Argentina
Ramlro E. Podettl Reps.
Casilla de Correo 4622
1000 Buenos Ai res
Tel: (01) 393-3919
Texas
RCA
Waterloo Executive Suites
12710 Research Blvd., Suite 240
Austin, TX 78759
Tel: (512) 335-1602
Mexico
RCA S.A. de C.V'/SSD
Avenida Cuitlahuac 2519
Apartado Postal 17-570
Mexico City, D.F. 11410
Tel: (905) 396-8934
U.K.
RCA Ltd
Lincoln Way, Windmill Road
Sunbury-on-Thames
Middlesex TW16 7HW
Tel: 093 27 85511
696 ___________________________________________________________________
Sales Offices, Distributors, and Representatives
RCA Authorized Distributors
u.s. and Canada
ALABAMA
Hamilton Avnet Etectronlcs
4940 Research Drive
Huntsville, AL 35805
Tel: (205)837-7210
ARIZONA
Hamilton Avnet Electronics
505 South Madison Drive
Tempe, AZ 85281
Tel: (602)231-5100
Klerulff Electronics, Inc.
4134 East Wood Street
Phoenix, AZ 85040
Tel: (602)243-4101
Schweber Electronics Corp.
11049 N. 23rd Drive, Suite 1100
Phoenix, AZ 85029
Tel: (602)997-4874
Sterling Electronics, Inc.
3501 E. Broadway Road
Phoenix, AZ 85040
Tel: (602)268-2121
Wyle Electronics Marketing Group
17855 N. Black Canyon Highway
Phoenix, AZ 85023
Tel: (602)249-2232
CALIFORNIA
Arrow Electronics, Inc.
19748 Dearborn Street
North Ridge Business Center
Chatsworth, CA 91311
Tel: (213)701-7500
Arrow Electronics, Inc.
1502 Crocker Avenue
Hayward, CA 94544
Tel: (415)487-4600
Arrow Electronics, Inc.
9511 Ridge Haven Court
San Diego, CA 92123
Tel: (619)741-3411
Arrow Electronics, Inc.
521 Weddell Drive
Sunnyvale, CA 94086
Tel: (408)745-6600
Arrow Electronics, Inc.
2961 Dow Avenue
Tustin, CA 92680
Tel: (714)838-5422
Avnet Electronics
20501 Plummer Street
Chatsworth, CA 91311
Tel: (818)700-2600
Avnet Electronics
350 McCormick Avenue
Costa Mesa, CA 92626
Tel: (714)754-6051
Hamilton Avnet Electronics
1361-B W. 190th Street
Gardena, CA 90248
Tel: (213)615-3900
Hamilton Avnet Electronics
3002 E.G. Street
Ontario, CA 91764
Tel: (714)989-4602
Hamilton Avnet Electronics
4103 Northgate Boulevard
Sacramento, CA 95834
Tel: (916)920-3150
Hamilton Avnet Electronics
4545 Viewridge Avenue
San Diego, CA 92123
Tel: (714)571-7510
Hamilton Avnet Electronics
1175 Bordeaux Drive
Sunnyvale, CA 94086
Tel: (408)743-3300
Hamilton Electro Sales
9650 Desoto Avenue
Chatsworth, CA 91311
Tel: (818)700-1222
Hamilton Electro Sales
3170 Pullman Street
Costa Mesa, CA 92626
Tel: (714)641-4107
Hamilton Electro Sales
10912 W. Washington Boulevard
Culver City, CA 90230
Tel: (213)558-2121
Klerulff Electronics, Inc.
10824 Hope Street
Cypress, CA 90630
Tel: (714)220-6300
Klerulff Electronics, Inc.
5650 Jillson Street
Los Angeles, CA 90040
Tel: (213)725-0325
Klerulff Electronics, Inc.
8797 Balboa Avenue
San Diego, CA 92123
Tel: (714)278-2112
Klerulff Electronics, Inc.
1180 Murphy Avenue
San Jose, CA 95131
Tel: (408)971-2600
Klerulff Electronics, Inc.
14101 Franklin Avenue
Tustin, CA 92680
Tel: (714)731-5711
Schweber Electronics Corp.
21139 Victory Boulevard
Canoga Park, CA 91303
Tel: (818)999-4702
Schweber Electronics Corp.
17822 Gillette Avenue
Irvine, CA 92714
Tel: (714)863-0200
Schweber Electronics Corp.
6730 Nancyridge Drive
San Diego, CA 92121
Tel: (619)450-0454
Schweber Electronics Corp.
90 East Tasman Drive
San Jose,CA 95134
Tel: (408)946-7171
Wyle Electronics Marketing Group
26677 Agoura Road
Calabasas, CA 91302
Tel: (818)880-9001
Wyle Electronics Marketing Group
124 Maryland Avenue
EI Segundo, CA 90245
Tel: (213)322-8100
Wyle Electronics Marketing Group
17872 Cowan Avenue
Irvine, CA 92714
Tel: (714)863-9953
Wyle Electronics Marketing Group
1151 Sun Center Drive
Rancho Cordova, CA 95670
Tel: (916)638-5282
Wyle Electronics Marketing Group
9525 Chesapeake Drive
San Diego, CA 92123
Tel: (714)565-9171
Wyle Electronics Marketing Group
3000 Bowers Avenue
Santa Clara, CA 95052
Tel: (408)727-2500
COLORADO
Arrow Electronics Inc.
1390 So. Potomac Street
Suite 136
Aurora, CO 80012
Tel: (303)696-1111
Hamilton Avnet Electronics
8765 E. Orchard Road
Suite 708, Englewood, CO 80111
Tel: (303)740-1000
Klerulff Electronics, Inc.
7060 So. Tucson Way
Englewood, CO 80112
Tel: (303)790-4444
Schweber Electronics Corp.
8955 E. Nichols Avenue
Englewood, CO 80112
Tel: (303)799-0258
Wyle Electronics Marketing Group
451 East 124th Avenue
Thornton, CO 80241
Tel: (303)457-9953
CONNECTICUT
Arrow Electronics, Inc.
12 Beaumont Road
Wallingford, CT 06492
Tel: (203)265-7741
Hamilton Avnet Electronics
Commerce Drive
Commerce Industrial Park
Danbury, CT 06810
Tel: (203)797-2800
Klerulff Electronics, Inc.
10 Capital Drive
Wallingford, CT 06492
Tel: (203)265-1115
Mllgray Electronics, Inc.
378 Boston Post Road
Orange, CT 06477
Tel: (203)795-0711
Schweber Electronics Corp.
Finance Drive
Commerce Industrial Park
Danbury, CT 06810
Tel: (203)748-7080
FLORIDA
Arrow Electronics, Inc.
350 Fairway Drive
Deerfield, FL 33441
Tel: (305)429-8200
Arrow Electronics, Inc.
1530 Bottlebush Drive
Palm Bay, FL 32905
Tel: (305)725-1480
·Chlp Supply
7725 No. Orange Blossom Trail
Orlando, FL 32810
Tel: (305)298-7100
'Chip eistributor only.
_________________________________________________________________ 697
Sales Offices, Distributors, and Representatives ____________________
RCA Authorized Distributors
u.s. and Canada (Cont'd)
FLORIDA
Hamilton Avnet Electronics
6801 NW 15th Way
Ft. Lauderdale, FL 33309
Tel: (305)971-2900
Hamilton Avnet Electronics
3197 Tech Drive, No.
St. Petersburg, FL 33702
Tel: (813)576-3930
Hamilton Avnet Electronics
6947 University Boulevard
Winter Park, FL 32792
Tel: (305)628-3888
Klerulff Electronics, Inc.
5410 N. W. 33rd Avenue
Ft. Lauderdale, FL 33309-6316
Tel: (305)486-4004
Klerulff Electronics, Inc.
3247 Tech Drive
St. Petersburg, FL 33702
Tel: (813)576-1966
Mligray Electronics, Inc.
1850 Lee World Center
Suite 104
Winter Park, FL 32789
Tel: (305)647-5747
Schweber Electronics Corp.
2830 North 28th Terrace
Hollywood, FL 33020
Tel: (305)927-0511
GEORGIA
Arrow Electronics, Inc.
3155 Northwood Parkway
Suite A
Norcross, GA 30071
Tel: (404)449-8252
Hamilton Avnet Electronics
5825D Peachtree Corners
Norcross, GA 30092
Tel: (404)447-7503
Kierulfl Electronics, Inc.
5824 Peachtree Corners East
Norcross, GA 30092
Tel: (404)447-5252
Schweber Electronics Corp.
303 Research Drive
Suite 210
Norcross, GA 30092
Tel: (404)449-9170
ILLINOIS
Arrow Electronics, Inc.
2000 Algonquis Road
Schaumburg, IL 60193
Tel: (312)397-3440
Hainllton Avnet Electronics
1130 Thorndale Avenue
Bensenville, IL 60106
Tel: (312)860-7700
Klerulff Electronics, Inc.
1140 West Thorndale
Itasca, IL 60143
Tel: (312)640-0200
Newark Electronics
4801 N. Ravenswood
Chicago, IL 60640-4496
Tel: (312)784-5100
Schweber Electronics Corp.
904 Cambridge Drive
Elk Grove Village, I L 60007
Tel: (312)364-3750
INDIANA
Arrow Electronics, Inc.
2495 Directors Row, Suite H
Indianapolis, iN 46241
Tel: (317)243-9353
Graham Electronics Supply, Inc.
133 S. Pennsylvania Street
IndianapOlis, IN 46204
Tel: (317)634-8202
Hamilton Avnet Electronics, Inc.
485 Gradle Drive
Carmel, IN 46032
Tel: (317)844-9333
IOWA
Hamilton!Avnet Electronics
915 33rd Avenue, S.W.
Cedar Rapids, IA 52404
Tel: (319)362-4757
KANSAS
Hamilton Avnet Electronics
9219 Quivi ra Road
Overland Park, KS 66215
Tel: (913)888-8900
Mligray Electronics, Inc.
6901 W. 63rd Street
Overland Park, KS 66202
Tel: (913)236-8800
MARYLAND
Arrow Electronics, Inc.
8300 Guildford Road
Columbus, MD 21046
Tel: (301)995-0003
Hamilton Avnet Electronics
6822 Oakhill Lane
Columbia, MD 21045
Tel: (301)995-3500
Kierulfl Electronics, Inc.
825D Hammons Ferry Road
Linthicum, MD 21090
Tel: (301)636-5800
Schweber Electronics Corp.
9330 Gaithers Road
Gaithersburg, MD 20877
Tel: (301)840-5900
MASSACHUSETTS
Arrow Electronics, Inc.
Arrow Drive
Woburn, MA 01801
Tel: (617)933-8130
Hamilton Avnet Electronics
10D Centennial Drive
Peabody, MA 01960
Tel: (617)531-7430
*Hybrid Components Inc.
72 Cherry Hill Drive
Beverly, MA 01915
Tel: (617)927-5820
Kierulff Electronics, Inc.
13 Fortune Drive
Billerica, MA 01821
Tel: (617)667-8331
A. W. Mayer Co.
34 Linnell Circie
Billerica, MA 01821
Tel: (617)229-2255
Schweber Electronics Corp.
25 Wiggins Avenue
Bedford, MA 01710
Tel: (617)275-5100
*SerTech
lOB Centennial Drive
Peabody, MA 01960
Tel: (617)531-8673
Sterling Electronics, Inc.
15D Constitution Way
Woburn, MA 01801
Tel: (617)938-6200
MICHIGAN
Arrow Electronics, Inc.
755 Phoenix Drive
Ann Arbor, M I 48104
Tel: (313)971-8220
Hamilton Avnet Electronics
2215 29th Street
Grand Rapids, MI 49503
Tel: (616)243-8805
Hamilton Avnet Electronics
32487 Schoolcraft Road
Livonia, MI 48150
Tel: (313)522-4700
Schweber Electronics Corp.
12060 Hubbard Avenue
Livonia, MI 48150
Tel: (313)525-8100
MINNESOTA
Arrow Electronics, Inc.
5230 West 73rd Street
Edina, MN 55435
Tel: (612)830-1800
Hamilton Avnet Electronics
10300 Bren Road, East
Minnetonka, MN 55343
Tel: (612)932-0600
Kierulff Electronics, Inc.
7667 Cahill Road
Edina, MN 55435
Tel: (612)941-7500
Schweber Electronics Corp.
7424 W. 78th Street
Edina, MN 55435
Tel: (612)941-5280
MISSOURI
Arrow Electronics, Inc.
2380 Schultz Road
St. Louis, MO 63141
Tel: (314)567-6888
Hamilton Avnet Electronics
13743 Shoreline Court East
Earth City, MO 63045
Tel: (314)344-1200
Kierulff Electronics, Inc.
2608 Metro Park Boulevard
Maryland Heights, MO 63043
Tel: (314)739-0855
NEW HAMPSHIRE
Arrow Electronics, Inc.
One Perimeter Drive
Manchester, NH 03103
Tel: (603)668-6968
Hamilton Avnet Electronics
444 E. Industrial Park Drive
Manchester, NH 03103
Tel: (603)624-9400
'Chip distributor only.
698 ___________________________________________________________________
Sales Offices, Distributors, and Representatives
RCA Authorized Distributors
u.s. and Canada (Cont'd)
NEW JERSEY
Arrow Electronics, Inc.
6000 Lincoln Drive East
Marlton, NJ 08053
Tel: (609)596-8000
Arrow Electronics, Inc.
Two Industrial Road
Fairfield, NJ 07006
Tel: (201)575-5300
Hamilton Avnet Electronics
Ten Industrial Road
Fairfield, NJ 07006
Tel: (201)575-3390
Hamilton Avnet Electronics
One Keystone Avenue
Cherry Hill, NJ 08003
Tel: (609)424-0110
Klerulf' Electronics, Inc.
37 Kulick Road
Fairfield, NJ 07006
Tel: (201)575-6750
Klerulfl Electronics, Inc.
520 Fellowship Road
Mt. Laurel, NJ 08054
Tel: (609)235-1444
Schweber Electronics Corp.
18 Madison Road
Fairfield, NJ 07006
Tel: (201)227-7880
NEW MEXICO
Arrow Electronics, Inc.
2460 Alamo, SE
Albuquerque, NM 87106
Tel: (505)243-4566
Hamilton Avnet Electronics
2524 Baylor S.E.
Albuquerque, NM 87106
Tel: (505)765-1500
Sterling Electronics, Inc.
3540 Pan American
Freeway, N.E.
Albuquerque, NM 87107
Tel: (505)884-1900
NEW YORK
Arrow Electronics, Inc.
20 Oser Avenue
Hauppauge, L.I., NY 11788
Tel: (516)231-1000
Arrow Electronics, Inc.
7705 Maltlage Drive
Liverpool, NY 13088
Tel: (315)652-1000
Arrow Electronics, Inc.
25 Hub Drive
Melville, L.I., NY 11747
Tel: (516)391-1300
Arrow Electronics, Inc.
3375 Brighton Henrietta Towline Rd.
Rochester, NY 14623
Tel: (716)427-0300
Hamilton Avnet Electronics
933 Motor Parkway
Hauppauge, L.I., NY 11788
Tel: (516)231-9800
Hamilton Avnet Electronics
333 Metro Park
Rochester, NY 14623
Tel: (716)475-9130
Hamilton Avnet Electronics
103 Twin Oaks Drive
Syracuse, NY 13206-1200
Tel: (315)437-2641
Mllgray Electronics, Inc.
77 Schmitt Boulevard
Farmingdale, L.I., NY 11735
Tel: (516)420-9800
Schweber Electronics Corp.
Two Townline Circle
Rochester, NY 14623
Tel: (716)424-2222
Schweber Electronics Corp,
Jericho Turnpike
Westbury, L.I., NY 11590
Tel: (516)334-7474
Summit Distributors, Inc.
916 Main Street
Buffalo, NY 14202
Tel: (716)884-3450
NORTH CAROLINA
Arrow Electronics, Inc.
5240 Greensdairy Road
Raleigh, NC 27604
Tel: (919)876-3132
Hamilton Avnet Electronics
3510 Spring Forest Road
Raleigh, NC 27604
Tel: (919)878-0810
Klerulf' Electronics Inc.
One North Commerce Center
5249 North Boulevard
Raleigh, NC 27604
Tel: (919)872-8410
Schweber Electronics Corp.
5285 North Boulevard
Raleigh, NC 27604
Tel: (919)876-0000
OHIO
Arrow Electronics, Inc.
7620 McEwen Road
Centerville, OH 45459
Tel: (513)435-5563
Arrow Electronics, Inc,
6238 Cochran Road
Solon, OH 44139
Tel: (216)248-3990
Hamilton Avnet Electronics
4588 Emery Industrial Parkway
Warrensville Hts., OH 44128
Tel: (216)831-3500
Hamilton Avnet Electronics
954 Senate Drive
Dayton, OH 45459
Tel: (513)433-0610
Hamilton Avnet Electronics
777 Brooksedge Boulevard
Westerville, OH 43081
Tel: (614)882-7004
Hughes-Peters, Inc.
481 East Eleventh Avenue
Columbus, OH 43211
Tel: (614)294-5351
Klerulf' Electronics, Inc.
23060 Miles Road
Cleveland, OH 44128
Tel: (216)587-6558
Mllgray ElectroniCS, Inc,
6155 Rockside Road
Cleveland, OH 44131
Tel: (216)447-1520
Schweber Electronics Corp.
23880 Commerce Park Road
Beachwood, OH 44122
Tel: (216)464-2970
OKLAHOMA
Klerulf' ElectroniCS, Inc.
'1"tro Park 12318 East 60th
Tulsa, OK 74145
Tel: (918)252-7537
Sterling ElectroniCS, Inc,
5119 So. 10th E. Avenue
Tulsa, OK 74146
Tel: (918)663-2410
OREGON
Arrow Electronics, Inc.
10260 S.W. Nimbus Ave., Suite M-3
Portland, OR 97223
Tel: (503)684-1690
Hamilton Avnet Electronics
6024 S.W. Jean Road
Bldg. C, Suite 10
Lake Oswego, OR 97034
Tel: (503)635-8157
Wyle Electronics Marketing Group
5289 N.E. Ezram Young Parkway
Hillsboro, OR 97123
Tel: (503)640-6000
PENNSYLVANIA
Arrow Electronics, Inc.
650 Seco Road
Monroeville, PA 15146
Tel: (412)856-7000
Hamilton Avnet Electronics
2800 Liberty Avenue, Bldg. E
Pittsburgh, PA 15222
Tel: (412)281-4150
Herbach & Rademan, Inc.
401 East Erie Avenue
Philadelphia, PA 19134
Tel: (215)426-1700
Schweber Electronics Corp.
231 Gibralter Road
Horsham, PA 19044
Tel: (215)441-0600
TEXAS
Arrow Electronics, Inc.
22227 West Breaker Lane
Austin, TX 78758
Tel: (512)835-4180
Arrow Electronics, Inc.
3220 Commander Drive
Carrollton, TX 75006
Tel: (214)380-6464
Arrow Electronics, Inc.
10899 Kinghurst Dr., Suite 100
Houston, TX 77099
Tel: (713)530-4700
Hamilton Avnet Electronics
1807 A W. Braker Lane, #A
Austin, TX 78758-3605
Tel: (512)837-8911
Hamilton Avnet Electronics
2111 West Walnut Hill Lane
Irving, TX 75060
Tel: (214)659-4111
____________________________________________________________________ 699
Sales Offices, Distributors, and Representatives _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
RCA Authorized Distributors
u.s. and Canada (Co nt' d)
TEXAS
Hamilton Avnet Electronics
4850 Wright Road, Suite 190
Stafford, TX 77477
Tel: (713)240-7898
Klerulfl Electronics, Inc.
3007 Longhorn Blvd., Suite 105
Austin, TX 78758
Tel: (512)835-2090
Klerulfl Electronics, Inc.
9610 Skillman Avenue
Dallas. TX 75243
Tel: (214)343-2400
Klerulfl Electronics, Inc.
10415 Landsbury Drive, Suite 210
Houston, TX 77099
Tel: (713)530-7030
Schweber Electronics Corp.
4202 Beltway
Dallas, TX 75234
Tel: (214)661-5010
Schweber Electronics Corp.
10625 Richmond Ste. 100
Houston, TX 77042
Tel: (713)784-3600
Stertlng Electronics, Inc.
2335A Kramer Lane, Suite A
Austin, TX 78758
Tel: (512)836-1341
Stertlng Electronics, Inc.
11090 Stemmons Freeway
Stem mons at Southwell
Dallas, TX 75229
Tel: (214)243-1600
Stertlng Electronics, Inc.
4201 Southwest Freeway
Houston, TX 77027
Tel: (713)627-9800
Wyle Electronics Marketing Group
1840 Greenville Avenue
Richardson, TX 75081
Tel: (214)235-9953
UTAH
Hamilton Avnet Electronics
1585 West 2100 South
Salt Lake City, UT 84119
Tel: (801)972-2800
Klerulfl Electronics, Inc.
2121 S. 3600 West Street
Salt Lake City, UT 84119
Tel: (801)973-6913
Wyle Electronics Marketing Group
1959 South 4130 West Unit B
Salt Lake City, UT 84104
Tel: (801)974-9953
WASHINGTON
Arrow Electronics, Inc.
14320 N.E. 21st Street
Bellevue, WA 98005
Tel: (206)643-4800
Hamilton Avnet Electronics
14212 N.E. 21st Street
Bellevue, WA 98005
Tel: (206)453-5874
Klerulfl Electronics, Inc.
19450 68th Avenue
South Kent, WA 98032
Tel: (206)575-4420
Priebe Electronics, Inc.
12908 N.E. 125th Way
Kirkland, WA 98034
Tel: (206)821-4695
Wyle Electronics Marketing Group
1750 132nd Avenue, N.E.
Bellevue, WA 98005
Tel: (206)453-8300
WISCONSIN
Arrow Electronics, Inc.
200 No. Patrick Boulevard
Brookfield, WI 53005
Tel: (414)792-0150
Hamilton Avnet Electronics
2975 South Moorland Road
New Berlin, WI 53151
Tel: (414)784-4510
Klerulfl Electronics, Inc.
2238 E.w. Bluemound Road
Waukesha, WI 53186-2916
Tel: (414)784-8160
Taylor Electrtc Company
1000 W; Donges Bay Road
Mequon, WI 53092
Tel: (414)241-4321
Canada
ALBERTA
Hamllton/Avnet (Canada) Ltd.
2816 21st St. N.E.
Calgary, Alberta T2E 6Z2
Tel: (403)230-3586
L. A. Varah, Ltd.
6420 6A Street SE
Calgary, Alberta T2H ZB7
Tel: (403)255-9550
BRITISH COLUMBIA
L. A. Varah, Ltd.
2077 Alberta Street
Vancouver, B.C. V5Y 1C4
Tel: (604)873-3211
R.A.E. Industrial Electronics, Ltd.
3455 Gardner Court
Burnaby, B.C. V5G 4J7
Tel: (604)291-8866
MANITOBA
L. A. Varah, Ltd.
#12 1832 King Edward Street
Winnipeg, Manitoba R2R ON1
Tel: (204)633-6190
ONTARIO
Arrow/Cesco
24 Martin Ross Road
Downsview, Ontario M3J 2K9
Tel: (416)661-0220
Arrow/Cesco
148 Colonnade Road
Nepean, Ontario K2E 7J5
Hamilton Avnet (Canada) Ltd.
6845 Rexwood Drive
Units 3,4,5
Mississauga, Ontario L4V 1M5
Tel: (416)677-7432
Hamilton Avnet (Canada) Ltd.
210 Colonnade Street
Nepean, Ontario K2E 7L5
Tel: (613)226-1700
L. A. Varah, Ltd.
504A Iroquois Shore Drive
Ontario L6H 3K4
Tel: (416)561-9311
QUEBEC
Arrow/Cesco
4050 Jean Talon Street, West
Montreal, Quebec H4P 1W1
Tel: (514)735-5511
Hamilton Avnet (Canada) Ltd.
2670 Sabourin Street
SI. Laurent, Quebec H4S 1M2
Tel: (514)331-6443
Europe, Middle East, and Africa
AUSTRIA
TVG
Transistor Vertrlebsgesellschaft
mbH&CoKG
Auhofstrasse 41A
1130Vienna
Tel: 022218294510
BELGIUM
Inelco Belgium S.A.
Avenue des Croix de Guerre 94
1120 Brussels
Tel: 02/216 01 60
DENMARK
Tage Olsen AlS
P.O. Box 225
2750 Ballerup
Tel: 02/658111
EGYPT
Sakrco Enterprises
P.O. Box 1133
37 Kasr EI Nil Street, Apt. 5
Cairo
Tel: 744440
ETHIOPIA
General Trading Agency
P.O. Box 1684
Addis Ababa
Tel: 132718-137275
FINLAND
Telercas OY
P.O. Box 33
04201 Kerava
Tel: 0/248.055
FRANCE
Almex
48, rue de l'Aubepine
92160 Antony
Tel: (1)46.66.21.12
*Hybrttech
Route de Bua
ZAC des Godets
91370 Verrieres-Le-Buisson
Tel: (1)69.20.22.10
Radio Equlpements
Antares S.A.
9, rue Ernest Cognacq
92301 Levallois Perret
Tel: (1)47.58.11.11
Radio Television Francais
9, rue D'Arcueil
94250 Gentilly
Tel: (1)46.64.11.01
·Chip Distributor only.
700 ________________________________________________________________
Sales Offices, Distributors, and Representatives
RCA Authorized Distributors
Europe, Middle East, and Africa (Cont'd)
FRANCE
Tekelec Alrlronlc S.A.
Cite des Bruyeres
Rue Carle Vernet
92310 Sevres
Tel: (1)45.34.75.35
GERMANY
Alfred Neye Enatechnlk GmbH
Schillerstrasse 14
2085 Quickborn
West Germany
Tel: 04106/6120
_Asternetlcs GmbH
Lindenring 3
8021 Taufkirchen
Tel: 089/61 21007
ECS Hilmar Frehsdorf GmbH
Electronic Components Service
Carl-Zeiss-Strasse 3
2085 Quickborn
West Germany
Tel: 04106/70 050
ELECTRONIC 2000
Stahlgruberring 12
8000 Munchen 82
Tel: 089/42 001-0
ElkoseGmbH
Bahnhofstrasse 44
7141 Moeglingen
West Germany
Tel: 07141/487-1
SascoGmbH
Hermann-Oberth-Strasse 16
8011 Putzbrunn bei Munchen
West Germany
Tel: 089/46111
Spoerle Electronic KG
Max-Planck-Strasse 1-3
6072 Dreieich bei Frankfurt
West Germany
Tel: 06103/3041
GREECE
Semlcon Co.
104 Aeolou Str.
TT 131 Athens
Tel: 3253626
HUNGARY
Hungagent
P,O. Box 542
1374 Budapest
Tel: 01/669-385
ICELAND
Georg Amundason
P,O, Box 698, Reykjavik
Tel: 81180
ISRAEL
Aviv Electronics
Kehilat Venezia Street 12
69010 Tel-Aviv
Tel: 03-494450
ITALY
Eledra SpA
Via G. Watt, 37
20143 Milano
Tel: (02)818221
IDAC Elellronlca SpA
Via Verona 8
35010 Busa di Vigonza
Tel: (049)72.56.99
LASI Elellronlca SpA
Viale Fulvio Testi 126
20092 Cinisello Balsamo (MI)
Tel: (02)24 40 012
Sliverstar Ltd.
Via dei Gracchi 20
20146 Milano
Tel: (02)49 96
KUWAIT
Morad Yousuf Behbehanl
P.O. Box 146
Kuwait
MOROCCO
Societe d'Equlpement Mecanlque
et Electrlque SA (S.E.M.E.)
rue Ibn Batouta 29
Casablanca
Tel: (212)22.08.65
THE NETHERLANDS
Koning en Hartman
Elektrotechnlek BV
Postbus 125
2600 AC Delft
Tel: (15)60 99 06
Vekano BV
Postbus 6115
5600 HC Eindhoven
Tel: (40)8298 98
NORWAY
National Elektro AlS
P.O, Box 53, Ulvenveien 75
Okern, Oslo 5
Tel: (472)644970
PORTUGAL
Crlstalonlca
Componentes de Radio
e Televlsao, Lda
Rua Bernardim Ribeiro, 25
1100 Lisbon
Tel: (019)534631
SOUTH AFRICA
Allied Electronic
Components (PTY) Ltd.
P,O. Box 6387
Dunswart 1508
Tel: (011)528-661
SPAIN
'Diode Espana S.A.
Edifico Iberia Mart
Avda, de Brasil,S, 1
28020 Mad rid
Tel: 1/45536 86
Kontron S.A.
Salvatierra 4
Madrid 34
Tel: 11729.11.55
SWEDEN
Ferner Electronics AB
Snormakarvagen 35
P,O. Box 125
16126 Bromma Stockholm
Tel: 08/80 25 40
Nordlsk Elektronlk AB
P,O. Box 1409
17127 Solna
Tel: 081734 97 70
SWITZERLAND
Baerlocher AG
Forrli buckstrasse 110
8005 Zurich
Tel: (01)42.99.00
TURKEY
Zer Kollektlf Stl
Guniz Sokak 17
Kavaklidere
Ankara
Tel: (41)67.08.39
U.K.
ACCESS Electronic Components Ltd.
Jubilee House, Jubilee Road
Letchworth, Hertfordshire SGS 1QH
Tel: Letchworth (0462)68 2333
Gothic Crellon Electronics Ltd.
3 The Business Centre
Molly Millars Lane
Wokingham, Berkshire RG11 2EY
Tel: (0734)78 7848
Jermyn Distribution
Vestry Industri,al Estate
Olford Road
Sevenoaks, Kent TN14 5EU
Tel: Sevenoaks (0732)450144
Macro Marketing Ltd.
Burnham Lane
Slough, Berkshire SL 1 6LN
Tel: Burnham (06286)4422
Mlcromark ElectroniCS, Ltd.
Boyn Valley Road
Maidenhead, Berks SLS 4DT
Tel: (0628)76 176
STC Electronics Services
Edinburgh Way
Harlow, Essex, CM20 2DF
Tel: Harlow (0279)26777
VSI Electronics Ltd.
Roydonbury Industrial Park
Horsecroft Road
Harlow, Essex CM19 5BY
Tel: Harlow (0279)29666
YUGOSLAVIA
Avtotehna
P,O, Box 593, Celovska 175
61000 Ljubljana
Tel: (061)552341
ZAMBIA
African Technical Associates Ltd.
Stand 5196 Luanshya Road
Lusaka
ZIMBABWE
BAK Electrical Holdings (Pvt) Ltd.
30 Pioneer Street
Harare
_High-Rei Specialist
______________________________________________________________________ 701
Sales Offices, Distributors, and Representatives _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
RCA Authorized Distributors
Asia Pacific
AUSTRALIA
AWA (Aust.) Ltd.
North Ryde Division
Corner Lane Cove & Talavera Roads
Macquarie Park
North Ryde, N.S.W. 2113
Amtron Tyree Pty. Ltd.
176 Cope Street
Waterloo, N.S.W. 2017
BANGLADESH
Electronic Engineers &
Consultants Ltd.
103 Elephant Road, 1st Floor
Dacca 5
HONG KONG
Glbb Livingston & Co., Ltd.
13/F., Tai Yau Building
181 Johnston Road
Wanchai
Hong Kong Electronic
Components Co.
Flat A Yun Kai Bldg. 1/F1
466-472 Nathan Road
Kowloon
INDIA
Photophone Ltd.
179-5 Second Cross Road
Lower Palace Orchards
Bangalore 560 003
INDONESIA
NVPD Soedarpo Corp.
Samudera Indonesia Building
JL Letlen, Jen. S
Parman No. 35 Slipi
Jakarta Barat
JAPAN
Okura & Company Ltd.
3-6 Ginza, Nichome, Chuo-Ku
Tokyo 104
KOREA
Panwest Company, Ltd.
Room 1202 Sam Heung Bldg.
32 Eulchi-ro 1-ka, Chung-Ku
Seoul, Republic of South Korea
Shln-A Trading Company
Room 406, Koryo Bldg.
88-7 Nonhyon-Dong
Kangnam-ku
Seoul, Republic of South Korea
NEPAL
Continental Commercial
Distributors
Phohara Durbar
Durbarmarga
Kathmandu
NEW ZEALAND
AWA NZ Ltd.
N.Z. P.O. Box 50-248
Porirua
PHILIPPINES
Philippine Electronics Inc.
P.O. Box 498
3rd Floor, Rose
Industrial Bldg., 11 Pioneer SI.
Pasig, Metro Manila
Semltronlcs Philippines
P.O. Box 445 Greenhills
San Juan 3113
Metro Manila
SINGAPORE
Device Electronics Pte. Ltd.
101 Kitchener Road No. 02-04
Singapore 0820
Mlcrotronlcs Assoc. Pte. Ltd.
8 Lorong Bakar Batu, No. 03-01
Kolam Ayer Industrial Park
Singapore 1334
SRI LANKA
C.W. Mackie & Co. Ltd.
36 D.R. Wijewardena Mawatha
Colombo 10
TAIWAN
Delta Engineering Ltd.
No. 42 Hsu Chang Street
8th Floor, Taipei
Sertek International Inc.
No. 315, Fu Shin North Road
Taipei 104
Teco Enterprise Co. Ltd.
2nd Floor, No. 120, Sec. 2
Chung Hsiao East Road
Taipei
THAILAND
Better Pro Co. Ltd.
71 Chakkawat Road
Wat Tuk, Bangkok
Latin America
ARGENTINA
Eneka S.A.I.C.F.I.
Tucuman 299
1049 Buenos Aires
Tel: 31-3363
Radlocom S.A.
Conesa 1003
1426 Buenos Aires
Tel: 551-2780
Tecnos S.R.L.
Independencia 1861
1225 Buenos Aires
Tel: 37-0239
BRAZIL
Commercial Bezerra Ltda.
Rua Costa Azevedo, 139
CEP-69.000 Manaus/AM
Tel: 322-5363
CHILE
Industria de Radio y
Television S.A. (IRT)
Vic. Mac Kenna 3333
Casilla 170-0, Santiago
Tel: 510081
COLOMBIA
Electronlca Moderna
Carrera 9A, NRO 19-52
Apartado Aereo 5361
Bogota, D. E.1
Tel: 282286
ECUADOR
Elecom, S.A.
Junin 618 y Boyaca
P.O. Box 9611, Guayaquil
Tel: 307786
MEXICO
Dlcopel, S.A.
Tochtli No. 368 Fracc.
San Antonio Azcapotzalco
02760 Mexico, D.F.
Electronlca Remberg, S.A.
deC.V.
Rep. Del Salvador No. 30-101
Mexico City 1, D.F.
Tel: 510-47-49
PERU
Arven S.A.
PSJ Adan Mejia 103, OF. 33
Lima 11
Tel: 716229
URUGUAY
American Products S.A.
(APSA)
Casilla de Correo 1438
Canelones 1133
Montevideo
Tel: 902735
VENEZUELA
P. Benavides, P., S.R.L.
Residencies Camarat, Local 7
La Candelaria, Caracas
MAIL ADDRESS: Apartado
Postal 20.249
San Martin, Caracas
Tel: 571-21-46
702 ___________________________________________________________________
Sales Offices, Distributors, and Representatives
RCA Manufacturers' Representatives
United States
ALABAMA
Electronic Sales, Inc. (ESI)
303 Williams Avenue
Suite 422
Huntsville. AL 35801
Tel: (205)533-1735
CALIFORNIA
CK Associates
8333 Clairemont Mesa Blvd.
Suite 102
San Diego, CA 92111
Tel: (619)279-0420
Pinnacle Sales
275 Saratoga Avenue
Suite 200
Santa Clara, CA 95050
Tel: (408)249-7400
CONNECTICUT
COM-SALE, Inc.
5 Shire Drive
P.O. Box 946
Wallingford, CT 06492
Tel: (203)269-7964
FLORIDA
G.F. Bohman Assoc., Inc.
130 N. Park Avenue
Apopka, FL 32703
Tel: (305)886-1882
G.F. Bohman Assoc., Inc.
2020 W. McNab Road
Ft. Lauderdale, FL 33309
Tel: (305)979-0008
GEORGIA
Electronic Sales, Inc. (ESI)
3103A Medlock Bridge Road
Norcross, GA 30071
Tel: (404)448-6554
INDIANA
Electronic Mktg. Consultants, Inc.
(EMCI)
5259 No. Tacoma Avenue
Suite 8
Indianapolis, IN 46220
Tel: (317)253-1668
IOWA
REP Associates Corp.
4905 Lakeside Drive. NE
Cedar Rapids, IA 52402
Tel: (319)373-0152
KANSAS
Electrl-Rep Inc.
7050 W. 107th Street
Suite 210
Overland Park. KS 66212
Tel: (913)649-2168
MASSACHUSETTS
COM-SALE, Inc.
105 Chestnut Street
Needham, MA 02192
Tel: (617)444-8071
MICHIGAN
Rathsburg Assocs., Inc.
16621 E. Warren Avenue
Detroit, M I 48224
Tel: (313)882-1717
OREGON
Vantage Corp.
7100 S.w, Hampton Street
Suite 205
Tigard, OR 97223
Tel: (503)620-3280
MINNESOTA
Comprehensive Technical Sales
(COM-TEK)
8053 Bloomington Freeway
Suite 138
Minneapolis, MN 55420
Tel: (612)888-7011
UTAH
Simpson Assocs.
7324 So. 1300 E.
Suite 350
Midvale, UT 84047
Tel: (801)566-3691
MISSOURI
Electrl-Rep Inc.
2300 Westport Plaza Drive
Suite 303
st. Louis, MO 63146
Tel: (314)878-8209
WASHINGTON
Vantage Corp.
300 120th Avenue N.E.
Bldg. 7, Suite 207
Bellevue, WA 98005
Tel: (206)455-3460
NEW HAMPSHIRE
COM-SALE, Inc.
101 High Street
Exeter, NH 03833
Tel: (603)772-3300
NEW JERSEY
Astrorep, Inc.
717 Convery Boulevard
Perth Amboy, NJ 08861
Tel: (201)826-8050
Trltek Sales, Inc.
21 East Euclid Avenue
Haddonfield, NJ 08033
Tel: (609)429-1551
NEW YORK
Astrorep, Inc.
103 Cooper Street
Babylon, L.I., NY 11702
Tel: (516)422-2500
Foster & Wager, Inc.
2507 Browncraft Blvd.
Rochester, NY 14625
Tel: (716)385-7744
NORTH CAROLINA
Electronic Sales, Inc. (ESI)
315 No. Academy Street
Suite 206
Cary, NC 27511
Tel: (919)467-8486
OHIO
Lyons Corporation
4812 Frederick Road
Suite 101
Dayton. OH 45414
Tel: (513)278-0714
Lyons Corporation
4615 W. Streetsboro Road
Richfield, OH 44286
Tel: (216)659-9224
Canada
ALBERTA
HI-Tech Sales, Ltd.
Box 115
339-10 Avenue, S.E.
Calgary, Alberta T2G OW2
Tel: (403)229-6990
BRITISH COLUMBIA
HI-Tech Sales, Ltd.
7510B Kingsway
Burnaby, B.C. V3N 3C2
Tel: (604)524-2131
MANITOBA
HI-Tech Sales, Ltd.
102-902 St. James Street
Winnepeg, Manitoba R3G 3J7
Tel: (204)786-3343
ONTARIO
Bytewlde Marketing, Inc.
7528 Bath Road
Mississauga, Ontario L4T 4Cl
Tel: (416)675-1868
QUEBEC
Bylewlde Marketing, Inc.
5020 Fairway Avenue
Suite 226
Lachine. Quebec H8T 1B8
Tel: (514)636-4121
___________________________________________________________________ 703
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