1986_RCA_Linear_Integrated_Circuits 1986 RCA Linear Integrated Circuits

User Manual: 1986_RCA_Linear_Integrated_Circuits

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Lin~

r

Integrated
Circuits

RCA
Linear Integrated Circuits
This DATABOOK contains complete
technical information on the full line
of RCA standard commercial linear integrated circuits and MOS field-effect
transistors for both industrial and consumer applications. An Index to
Devices provides a complete listing of
types, together with an indication of
package options available for each of
them.
The pages immediately following the
Index to Devices include photographs
of the packages used for RCA linear
integrated circuits and MOS/FET's, a
product-classification chart, recommended operating and handling considerations, a list of special terms and
symbols used in the characterization of
RCA linear integrated circuits and
MOS/FET's, and a cross-reference
directory that indicates RCA types
recommended as direct replacements
for other manufacturers' types.
Three separate data sections provide
definitive ratings and electrical
characteristics for (1) Linear Integrated
Circuits for Industrial Applications,
(2) Linear Integrated Circuits for
Consumer Applications, and (3) MOS
Field-Effect Transistors (MOSI
FET's). Data pages for individual
devices are included as nearly as possible in alpha-numerical sequence of
type numbers. Because some devices
are grouped together to show similarity
of function or data, individual type
numbers may be out of sequence. If
you don't find the data on a specific
type where you expect it to be, check
the Index to Devices.
The DAT ABOOK also includes dimensional outlines for all currently
available packages and selected RCA
Application Notes on RCA Linear Integrated Circuits and MOS/FET's.

Table of Contents
Index to Devices .................................................. .
Packages ........................................................ .
Product Classification Chart ........................................ .
Operating and Handling Considerations .............................. .
Terms and Symbols ............................................... .
Cross-Reference Directory .......................................... .
Linear Integrated Circuits for Industrial Applications-Technical Data .... .
Linear Integrated Circuits for Consumer Applications-Technical Data " ..
MOS Field-Effect Transistors-Technical Data ........................ .
Dimensional Outlines .............................................. .
Application Notes ................................................. .
RCA Sales Offices, Manufacturers' Representatives, and
Authorized Distributors ........................................ .

ROil SOlidi
!

State

Page
3
5
7
8
10
12

17
291
433
475
483
559

Brussels' Buenos Aires' Hamburg' Madrid' Mexico City· Milan
Montreal' Pari •• Sao Paulo' Somerville NJ • Stockholm
Sunbury-on·Thames • Taipei' Tehran' Tokyo

Infonnation furnished by RCA is believed· to be accurate and reliable.
However, no responsibility is assumed by RCA for its use; nor for any
infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any
patent or patent rights of RCA.

The device data shown for some types are indicated as preliminary.
Preliminary data are intended for gUidance purposes in evaluating devices
for equipment design. Such data are shown for types currently being
designed for inclusion in our standard line of commercially available
products. For current information on the status of preliminary programs,
please contact your local RCA sales office.

Copyright 1978 by RCA Corporation
(All rights reserved under Pan·American
Copyright Convention)

®

Trademark(s) Registered
Marca(s) Registrada(s)

Printed in USA/ll·78

2 ______________________________________________________________________

Index to Devices -

Type
Number

CA101
CA101A
CA107
CA111
CA124
CA139
CA139A
CA158
CA158A
CA201
CA201A
:;A207
CA211
CA224
CA239
CA239A
CA258
CA258A
CA270
CA301A
CA307
CA311
CA324
CA339
CA339A
CA358
CA358A
CA555
CA555C
CA723
CA723C
CA741
CA741C
CA747
CA747C
CA748
CA748C
CA758
CA810
CA810A
CA920
CAl190
CA1310
CA1352
CA1391
CA1394
CA1398
CA1458
CA1541
CA1558
CA2002
CA2004
CA2111A
CA2904
CA3000
CA3001
CA3002
CA3004
CA3005
CA3006

Package
Suffix

-

T
T
T
T

S
S
S
S

E
E
E

G
G
G

T
T
T

S
S
S

-

T
T
T

S
S
S

G
G
G

E
E
E

G
G
G

-

T
T

S
S

G
G

W

-

-

G
G
G

-

-

G
G

-

-

-

-

-

-

-

-

-

-

-

G

H

-

S

E·

T
T

S
S

E·
E·

E
E
E

G
G
G

H
H

G
G
GH
GH

-

-

-

T
T
T
T
T

S
S
S
S
E

G
G

H

GH

-

E·
E·

G
G

-

T
T
T
T
T
T
T

E
S
S
E
E
S
S

E

-

T

a
a

OM
OM

E

-

a

E
E
E·
E·
E
T

-

H

E·
E·
G
G

E·
E·

-

-

-

-

-

-

-

-

-

G
G

-

H
G
G

-

-

!lJ
!lJ

M
M

-

-

•
••
••

a

-

H
H
H
H
H

-

-

-

-

-

-

-

-

-

-

-

GH

-

H

GH

-

-

-

H

G

•

-

G

-

-

GH

-

-

-

-

L
H

-

E·

-

-

-

H

-

-

E·

S

-

-

-

S

-

-

T

G

H

-

-

0

E

H

-

-

-

-

-

-

-

-

-

-

-

-

GH

-

-

-

-

Data
Bulletin
File No.

Page

786
786
785
797
796
795
795
1019
1019
786

18
18
22
25
29
32
32
35
35
18

CA3007
CA3008
CA3008A
CA3010
CA3010A
CA3011
CA3012
CA3013
CA3014
CA3015

786
785
797
796
795
795
1019
1019
879E
786

18
22
25
29
32
32
35
35
292
18

CA3015A
CA3016
CA3016A
CA3018
CA3018A
CA3019
CA3020
CA3020A
CA3021
CA3022

785
797
796
795
795
1019
1019
834
834
788

22
25
29
32
32
35
35
42
42
46

CA3023
CA3026
CA3028A
CA3028B
CA3029
CA3029A
CA3030
CA3030A
CA3035
CA3036

788
531
531
531
531
531
531
760
1154
1154

46
50
50
50
50
50
50
295
298
298

CA3037
CA3037A
CA3038
CA3038A
CA3039
CA3040
CA3041
CA3042
CA3043
CA3044

1132
1155
761
961
981
981
686
531
536
531

301
303
306
309
310
310
312
50
54
50

CA3045
CA3046
CA3048
CA3049
CA3050
CA3051
CA3052
CA3053
CA3054
CA3058

1156
1105
612
1019
121
122
123
124
125
125

314
317
57
35
59
61
64
66
69

CA3059
CA3060
CA3060A
CA3060B
CA3064
CA3065
CA3066
CA3067
CA3068
CA3070

69

Type
Number

Linear Ie's

Package
Suffix

•

i.
i.

•
•
•
•
•
•
•
•

i.
i.

-

-

L

H

-

-

-

-

-

-

-

-

H

-

-

-

-

• -L -H -• H - •
• -H -- -•
• -- -- -•
• HH -- -• S L • S - •• - - •
•

-

•
•

-

-

-

-

•

t
t
t
t

-

VI

-

-

• -L
••• --H
• VI
•
t
t

•

T

t

•
•
••
t
•

0
0
0
E

••
•
••

F

L
S

L

-

H

-

H

-

-

-

-

L

H

H
H

H

E

H

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

H

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Data
Bulletin
File No.

Paoe

126
316
310
316
310
128
128
129
129
316

72
74
78
74
78
82
82
84
84
74

310
316
310
338
338
236
339
339
243
243

78
74
78
87
87
90
92
92
96
96

243
338
382
382
316
310
316
310
I 274
I 275

96
99
103
103
74
78
74
78
319
108

316
310
316
310
343
363
318
319
331
340

74
78
74
78
109
111
320
323
326
328

341
341
377
611
361
361
387
382
388
490

114
114
117
120
124
124
331
103
99
127

490
537
537
537
396
412
466
466
467
468

127
132
132
132
335
337
340
340
343
345

_____________________________________________________________ 3

Index to Devices - Linear IC's
Type
Number

Dati
BulieUn
File No.

Package
Suffix

•
•

CA30n
CA3072
CA3075
H
CA3076
H
CA3078
T
S
CA3078A T
S
CA3079
CA3080
E*
CA3080A
E*
CA3081
F
CA3082
F
CA3083
F
CA3084
L
E*
CA3085
CA3085A
S
CA3085B
S
CA3086
F
CA3088
CA3089
E
CA3090A a
CA3091
D
H
CA3093
E
H
CA3094
T
S
CA3094A T
S
CA3094B T
S
CA3095
H
E
CA3096
H
E
CA3098A E
CA3096C E
CA3097
E
H
CA3098
T
S
CA3099
H
E
CA31 00
T
S
CA3102
E
H
CA3118
T
H
CA3118A T
.~.~IL. ~-CA3121
E
CA3123
E
CA3125
E
CA3126
a
CA3127
E
CA3128
a
CA3130
T
S
CA3130A T
S
CA3130B T
S
CA3131 EM
CA3132 EM
CA3134
G GM
CA3135
G

,

~

-

•

-

---

-

S
S

H
H
L
H

S

E*

-

E*
E*

-

E*
F
-

-

E*

-

-

E*

--

GaM

• No designated suffix letter for
.... No designated suffix letter for
• No designated suffix letter for
package
t No designated suffix letter for
package

H
H
H
L
H
H
H
-

H
-

H
-

--

-

-

-

---

468
468
429
430
535
535
490
475
475
480
480
481
482
491
491
491
483
560
561
684
534
533
598
598
598
591
595
595
595
633
896
620
625
611
532
532
907
688
631
685
860
662
1161
817
817
817
1157
1157
1097
1021

Page

345
345
138
140
142
142
127
146
146
152
152
154
156
159
159
159
162
352
354
357
164
170
173
173
173
181
186
186
186
193
199
203
206
120
210
210
359

=
369
370
215
372
218
218
218
373
373
374
378

this type in TO-5-style package
this type in ceramic flat package
this type in dual-in-line plastic
this type in dual-in-line ceramic

Type
Number

CA3136
CA3137
CA3138
CA3138A
CA3139
CA3140
CA3140A
CA3140B
CA3141
_CA3142
CA3r4'3
CA3144
CA3146
CA3146A
CA3151
CA3153
CA3159
CA3160
CA3160A
CA3160B
CA3161
CA3162
CA3163
CA3164
CA3166
CA3168
CA3170
CA3172
CA3183
CA3183A
CA3189
CA3221
CA3240
CA3240A
CA3290
CA3290A
CA3290B
CA3401
CA3600
CA3724
CA3725
CA6078A
CA6741

Package
Suffix

E
E
G
G

E
T
T
T
E
E
E

GH
a

S
S
S

-.- G

E
E
G
G
G

T
T
T
E
E
G

E
E
E
E
G

E
E
E
G

H
S
S
S

H
-

E*
E*
T
T
T
E
E

El§
El§

G

GH

G
T
T

GH

S
S
S

G

-

S
S

-

E*
E*

-

~

E*
E*

-

E*
E*

H
-

-H
-

- - - - - H
- - - ""'-""- ...=....
- - - - - - H
- - - - - - - - - - - - - - -- -El§ El§ - GH
- - - - - -

-

---

--

-

._----

Dati
BulleUn
File No.

Peae

1158
970
1131
1131
905
957
957
957
906
907
1138
1137
532
532
1160
1142
1136
976
976
976
1079
1080
1092
1139
1110
1140
1129
1130
532
532
1046
1057
1050
1050
1049
1049
1049
630
619
884
884
592
592

383
386
228
228
390
230
230
230
242
359
393
395
210
210
399
402
408
244
244
244
256
258
410
262
412
415
417
420
210
210
422
427
265
265
274
274
274
280
282
287
287
289
289

--

, No designated suffix letter for this type in quad-in-line plastic
package
* In 8-lead dual-in-line Mini-DIP package
§ In 14-lead dual-in-line plastic package
Ell No designated suffix letter for this typa in TO-220-style package
with vertical-mount lead form

4 ________________________________________________

~-----------------

Index to Devices lype
Number

3N128
3N138
3N139
3N140
3N141
3N142
3N143
3N152
3N153
3N154
3N159
3N187
3N200
3N204
3N205
3N206
3N211

Package

Data
Bulletin
File No.

Page

lype
Number

lO·72
lO·72
lO·72
lO·72
lO·72
TO·72
TO· 72
lO·72
TO·72
lO·72
TO· 72
TO·72
TO·72
TO·72
TO·72
TO·72
lO·72

309
283
284
285
285
286
309
314
320
335
336
326
436
959
959
959
875

434
436
437
438
438
441
434
442
443
444
459
446
450
453
453
453
458

3N212
3N213
40467A
40468A
40559A
40600
40601
40602
40603
40604
40673
40819
40820
40821
40822
40823
40841

Package

TO· 72
TO· 72
TO· 72
TO·72
TO· 72
TO· 72
TO·72
TO· 72
TO·72
TQ·72
TO·72
TO· 72
TO· 72
TO·72
TO·72
TO·72
TO·72

MOS/FET's

Data
Bulletin
File No.

Page

875
875
324
323
323
333
333
333
334
334
381
463
464
464
465
465
489

458
458
462
463
463
464
464
464
465
465
466
467
468
468
470
470
471

Packages

D Suffix
Dual·ln·Line Welded·Seal
Ceramic Package

E Suffix
Dual·ln·Line Plastic Package

E Suffix
Power Stud Plastic
Dual·ln·Llne Package

~

~.

...~
..t•.•. • .....
.

.~)
•.
···········1'1.

H~817

\

1

!

H1828

14 and 16·lead versions

8, 14, and 16·lead versions

CA3134E only

EM Suffix
Modified 16·lead Dual·
In·Llne Plastic Package

EM Suffix
Modified 16·lead Dual·
In·Line Plastic Package

F Suffix
Dual·ln·Line Frit·Seal
Ceramic Package

H1827

CA3134EM only

CA3131EM, CA3132EM only

14 and 16·lead versions

5

Packages

Q Suffix
Quad·in·Line Plastic
Package (QUIP)

Q Suffix
Modified 16·lead

"~
.~'

VERSA·V TO·220 Style
Plastic Package
with Vertical·Mount
Lead Form

<~

•.;•.' ".....•........Q.U
. . IP..... ' "

~,"

.'/ t ; '
H1825

14 and 16·lead versions
K Suffix
Ceramic Flat Package

CA810Q, CA810AQ,
and CA1190Q only
(A flat wing. tab version, QM
suffix is also available for the
CA810, CA810A).
S Suffix
TO·5 Style Package with
Dual·ln·Line Formed
Leads (DIL·CAN)

CA2002, CA2004 only
(Versions with Horizontal·Mount
Lead Form-CA2002M and CA2004M
are also available)
T Suffix
TO·5 Style Package
with Straight Leads

H1787
H1463

14 ·Iead version
V1 Suffix
TO·5 Style Package
with Radial Formed Leads

8·lead version

8, 10, and 12·lead versions

L Suffix
Beam·Lead

H Suffix
Chip

H1561
92CS·22137

8, 10, and 12·lead versions
JEDECTO·72

Notes:
1. Some types may have an additional "M" suffix
following the package desi9,nation suffix, i.e.,
CA3131 EM. The additional 'M" suffix simply indicates
that the device is a mechanical variant of the basic
package type.

H1299

MOS/FET's only

2. RCA Linear integrated circuits are provided in chip
form to allow customer design of special and complex
circuits to suit individual needs. Linear chips are
electrically identical to and offer the features of their
counterparts, sealed in ceramic, TO-5, and plastic
packages.

6 _________________________________________________________________________

Product Classification Chart
Industrial Circuits
OPERATIONAL AMPLIFIERS

General Purpose
Single Unit
CA10l
CA107
CA201
CA207
CA301
CA307
CA741
CA74B
CA6741·

VOLTAGE
REGULATORS
CA723
CA3OB5

Dual Unit
CA158
CA25B
CA35B
CA747
CAl45B
CA155B
CA2904
Quad Unit
CA124
CA224
CA324
CA3401

ERO-VOLTAGE
SWITCHES
CA305B
CA3059
CA3079

General Purpose
Wideband
Single Unit
CA3008
CA3010
CA3015
CA3016
CA3029
CA3030
CA3037
CA3038
CA3100'
CA3130'
CA3140'
CA3160'
Dual Unit
CA3240'

Amplifier/
Diode

Variable
High Current
CA3094

CA3000
CA3001
CA3004
CA3005
CA3006
CA3007
CA3026
CA302B
CA3049
CA3050
CA3051
CA3053
CA3054
CA3102

Micropower

CA3060
CA3078
CA30BO
CA607B e

VOLTAGE
COMPARATORS
Single Unit
CAlll
CA211
CA311
CA309B+
CA3099+
Dual Unit
CA3290*
Quad Unit
CA139
CA239
CA339

ARRAYS

DIFFERENTIAL
AMPLIFIERS

Amplifier
CA3026
CA3035
CA304B
CA3049
CA3052
CA3054
CA3060
CA3102
Diode
CA3019
CA3039
CA3141

SPECIAL-FUNCTION
CIRCUITS
A/D Converter
CA3162
BCD-to-7-Segment Decoder/Driver
CA3161
Memory Sense Amplifier
CA1541
Four-Quadrant Multiplier
CA3091
Timer

Transistor
CA3018
CA3036
CA3045
CA3046
CA3050
CA3051
CA30Bl
CA3OB2
CA30B3
CA30B4
CA30B6
CA3093

CA3095
CA3096
CA3097
CA311B
CA3127
CA3138
CA3146
CA31B3
CA3600·
CA3724
CA3725

MOS/FET's
Single Gate
3N12B
3Nl38
3N139
3N142
3N143
3N152
3N153
3N154

Dual Gate
3N140
3N141
3N159
Dual Gate
Protected
3N1B7
3N200
40B19

CA555
Programmable Schmitt Trigger
CA309B

Consumer Circuits
BROADBAND
AM/FM
(VIDEO)
COMMUNICATIONS
AMPLIFIERS
CIRCUITS
CA3002
CA1352
CA3020
CA3021
CA3022
CA3023
CA3040
MULTIPLEX
DECODERS
CA758
C1310
CA3090A

CA2111A
CA3011
CA3012
CA3013
CA3014
CA3043
CA3075
CA3076
CA30BB
CA30B9
CA3123
CA3163
CA3189

• Low-noise versions of CA741 and CA307B

AUDIO
CIRCUITS
Preamplifiers

CA3036
CA3052
Drivers

CA3094
Power Ampl ifiers
CA810
CA2002
CA2004
CA3131
CA3132

• BiMOS types

FM IF
CIRCUITS
Subsystems
CA2111A
CA3013
CA3014
CA3043
CA3075
CA30B9
CA31B9
Gain Blocks
CA3011
CA3012
CA3076

·CMOS type

TV RECEIVER
CIRCUITS
Tuning
CA3163
CA3166
CA316B
AFT
CA3044
CA3064
CA3139
Sound IF
CAl190
CA2111A
CA3041
CA3042
CA3065
CA3134
PIX IF
CA270
CAl352
CA306B
CA3136
Remote Control
CA3035
"Jungle" Circuits
CA3120
CA3142

Chroma Systems
CA139B
CA3066
CA3067
CA3070
CA3071
CA3072
CA3121
CA3125
CA3126
CA3128
CA3151
CA3170
Luminance

Processors
CA3135
CA3143
CA3144
Horizontal
Systems
CA1391
CA1394
CA920A
CA3159
CA3172

MOS/FET's
Single Gate
40467A
4046BA
40559A
Dual Gate
40600
40601
40602
40603
40604

Dual Gate
Protected
3N204
3N205
3N206
3N211
3N212
3N213
40673
40820
40821
40822
40823
40841

+ Programmable

7

Operating and Handling Considerations
Solid state devices are being designed into an increasing
variety of electronic equipment because of their high
standards of reliability and performance. However, it is
essential that equipment designers be mindful of good
engineering practices in the use of these devices to achieve
the desired performan ce.
This Note summarizes important operating recommendations and precautions which should be followed in the
interest of maintaining the high standards of performance of
linear integrated circuits and MaS field-effect transistors.
The ratings included in RCA data bulletins are based
on the Absolute Maximum Rating System, which is.
defined by the following Industry Standard (JEDEC)
statement:
Absolute-Maximum Ratings are limiting values of operating and environmental conditions applicable to any electron
device of a specified type as defined by its published data,
and should not be exceeded under the worst probable
conditions.
The device manufacturer chooses these values to provide
acceptable serviceability of the device, taking no responsibility for equipment variations, environmental variations, and
the effects of changes in operating conditions due to
variations in device characteristics.
The equipment manufacturer should design so that
initially and throughout life no absolute-maximum value for
the intended service is exceeded with any device under the
worst probable operating conditions with respect to supplyvoltage variation, equipment component variation, equipment control adjustment, load variation, signal variation,
environmental conditions, and variations in device characteristics.
It is recommended that equipment manufacturers consult
RCA whenever device applications involve unusual electrical,
mechanical or environmental operating conditions.
GENERAL CONSIDERATIONS
Th0 design flexibility provided by integrated circuits and
MaS/FET's makes possible their use in a broad range of
applications and under many different operating conditions.
When incorporating these devices in equipment, designers
should anticipate the rare possibility of device failure and
make certain that no safety hazard would result from such
an occurrence.
The small size of these devices provides obvious advantages to the designers of electronic equipment. However, it should be recognized that these compact devices
usually provide only relatively small insulation area between
adjacent leads and the metal envelope. When these devices
are used in moist or contaminated atmospheres, therefore,
supplelTlental protection must be provided to preven t the
development of electrical conductive paths across the
relatively small insulating surfaces.

Devices should not be connected into or disconnected
from circuits with the power on because high transient
voltages may cause permanent damage to the devices.

iESTING PRECAUTIONS

[n common with many electronic components, solid-state
devices should be operated and tested in circuits which have
reasonable values of current limiting resistance, or other
forms of effective current overload protection. Failure to
observe these precautions can cause excessive internal heating
of the device resulting in destruction and/or possible
shattering of the enclosure.
MOUNTING

Integrated circuits arc normally supplied with lead·tin
plated leads to facilitate soldering into circuit boards. In
those relatively few applications requiring welding of the
device leads. rather than soldering. the devices may be
obtained with gold or nickel plated Kovar leads' It should be
recognized that this type of plating will not provide complete
protection against lead corrosion in the presence of high
humidity and mechanical stress. The aluminum-foil-Iined
cardboard "sandwich pack" employed for static protection
of the !lat-pack also provides some additional protection
against lead corrosion, and it is recommended that the
devices be stored in this package until used.
When integrated circuits are welded onto printed circuit
boards or equipment, the presence of moisture between the
closely spaced terminals can result in conductive paths that
may impair device performance in high-impedance appli·
cations. It is therefore recommended that conformal coatings
or potting be provided as an added measure of protection
against moisture penetration.
In any method of mounting integrated circuits which
involves bending or forming of the device leads, it is
extremely important that the lead be supported and clamped
between the bend and the package seal, and that bending be
done with care to avoid damage to lead plating. [n no case
should the radius of the bend be less than the diameter of the
lead, or in the case of rectangular leads, such as those used in
RCA 14-lead and I6·lead flat·packages, less than the lead
thickness. It is also extremely important that the ends of the
bent leads be straight to assure proper insertion through the
holes in the printed-circuit board.

MOS FiElD-EFFECT TRANSISTORS
Insulated-Gate Metal Oxide-Semiconductor Field-Effect
Transistors (MOS FETs), like bipolar high-frequency
transistors, are susceptible to gate insulation damage by the
electrostatic discharge of energy through the devices.
Electrostatic discharges can occur in an MaS FET if a type
with an unprotected gate is picked up and the static charge,
built in the handler's body capacitance, is discharged through
the device. With proper handling and applications
procedures, however, MOS transistors are currently being
extensively used in production by numerous equipment
manufacturers in military, industrial, and consumer applica-

* MIL-38510A,

paragraph 3.5.6.1(a), lead material.

8---------------------------------------------------------

Operating and Handling Considerations
tions, with virtually no problems of damage due to
electrostatic discharge.
In some MOS FETs, diodes are electrically connected
between each insulated gate and the transistor's source.
These diodes offer protection against static discharge and
in-circuit transients without the need for external shorting
mechanisms. MOS FETs which do not include gateprotection diodes can be handled safely if the following basic
precautions are taken:
I. Prior to assembly into a circuit, all leads should be kept
shorted together either by the use of metal shorting
springs attached to the device by the vendor, or by the
insertion into conductive material such as "ECCOSORB*
LD26" or equivalent.
(NOTE: Polystyrene insulating "SNOW" is not sufficiently conductive and should not be used.)
2. When devices are removed by hand from their carriers,
the hand being used should be grounded by any suitable
means, for example, with a metallic wristband.
3. Tips of soldering irons should be grounded.
4. Devices should never be inserted into or removed from
circuits with power on.

*Trade Mark: Emerson and Cumming, Inc.

SOLID STATE CHIPS

Solid state chips, unlike packaged devices, are nonhermetic devices, normally fragile and small in physical size,
and therefore, require special handling considerations as
follows:
I. Chips must be stored under proper conditions to insure
that they are not subjected to a moist and/or contaminated atmosphere that could alter their electrical,
physical, or mechanical characteristics. After the shipping
container is opened, the chip must be stored under the
following conditions:
A. Storage temperature, 40 0 C max.
B. Relative humidity, 50% max.
C. Clean, dust-free environment.
2. The user must exercise proper care when handling chips
to prevent even the slightest physical damage to the chip.
3. During mounting and lead bonding of chips the user must
use proper assembly techniques to obtain proper electrical, thermal, and mechanical performance.
4. After the chip has been mounted and bonded, any
necessary procedure must be followed by the user to
insure that these non-hermetic chips are not subjected to
moist or contaminated atmosphere which might cause
the development of electrical conductive paths across the
relatively small insulating surfaces. In addition, proper
consideration must be given to the protection of these
devices from other harmful environments which could
conceivably adversely affect their proper performance.

_________________________________________________________________ 9

Terms and Symbols
A
AAF

~gbFF
AFC
AFT
AGC
AMR
AOl
AV
b fs

b is

bos

brs

BW
BWOl
CBI
CCB
C EB
C EXT
C FB
C,
Cios
Cis
C iss
C I _O
CMMR
Co
Cos
Coss
CQP

e rss
ei
EN
eN

eN(total)

e01 /e 02
EON
fCl
f max
fp
ft

~P

Gm
hFE
h fe
1+
1-

10

closed-loop voltage gain
audio amplifier gain
differential vOltage gain
automa~ic chroma control
automatic frequency control
automatic fine tuning
auto matic gai n co ntrol
am rejection
open-loop voltage gain
amplifier voltage gain

IA
I ABC
II AGC
liB
IIC
IICBO
I CEO
ICEIOFF)
10
.IO(ON)
small·signal,-common-source.
10ARK
forward transfer susceptance
10F
(imaginary part of corresponding 1000
admittance; see Yfs)
~mall-s,lgnal, common-source,
lOS
Input susceptance (imaginary
part of corresponding admittance;
lOSS
see Yis)
small-signal, common-source,
IF
output susceptance (imaginary
IG
part of corresponding admittance
seeyos)
,
IGR
small-signal, common~source,
reverse transfer susceptance
IGS
(imaginary part of corresponding
admittance, see y )
IG1S
bandwidth

(unitv'~ain)

open-loop bandwidth
base-to-substrate capacitance
collector-to-base capacitance
emitter-to-base capacitance
external capacitance
feedback capacitance
input capacitance
small-signal output capacitance
small-signal input capacitance
small-signal, common-source
~hort-circuit ,input capacitance
Input-to-output capacitance;
data in/out capacitance
common-mode rejection ratio
output capacitance
feedthrough capacitance
small-signal, common-source
short-circuit output capacitance
charge-pump capacitance
small-signal, common-source
short-circuit, reverse transfer
capacitance
input sensitivity
IIF noise voltage
low-frequency noise voltage;
equivalent short-circuit input
noise voltage (p.V ,(Hz)
wideband noise voltage
referenced to· input
channel separation
broadband output noise voltage
clock input frequency
maximum operating frequency
charge-pump input-pulse frequency
unity-gain crossover frequency;
gain-bandwidth product
input·pulse frequency
power gain
forward transconductance
(large-signal)
static forward-current transfer
ratio (beta)
small-signal forward-current
transfer ratio
dc su ppl y current
dc supply current

/

I G2S
I GSSF

IG1SSF

IG2SSF

I GSSR

IG1SSR

IG2SSR

IGT
II
liB
IIBC
110
0< 110
"IIOI"T
ILiM
IMTR
IN
iN
10
10(0IFF)
100

amplifier supply current
amplifier bias current
AGC source current

10M
1I0Mi

base current

10M

collector current
collector cutoff current
collector cutoff current
output leakage current
drain current

de on-state drain current
dark current
diode forward current
supply current for drain supply
voltage (V 0)
zero-gate
drain current
(dual-gate types)

(~ias)

zero-gate ibias) drain current
(single-gate types)
forward current
channel (input) gate lead
current
channel (input) gate reverse
current
gate terminal current (singlegate types)
gate-No.1 terminal current
dual-gate types
gate-No.2 terminal current
dual-gate types
gate-to-source forward leakage
current, all other terminals
shorted to source (dual-gate
types).
gate-No.1 source forward leakage
current, all other terminals
shorted to source (dual-gate
types).
gate-No. 2-to-source forward
leakage current, all other
terminals shorted to source
(dual-gate types).
gate-to-s.ource reverse leakage
current, all other terminals
shorted to source (single-gate
types).
gate-No. l-to-source reverse
leakage current, all other
terminals shorted to source
(dual-gate types).
gate-No.2-to-source reverse
leakage current, all other
terminals shorted to source
(dual-gate types).
gate trigger current; gate
terminal current
input current
input bias current
internal bias current
input offset current
average temperature coefficient
of input offset current
temperature coefficient of input
offset current (drift)
short-circuit limiting current
current-mirror transfer ratio
I/F noise current
equivalent open-circuit noise
current (pAl
output current

J"HZ)

differential output current
(sink)
output offset current
output leakage current, low

+

10MIp
I p _p
IQ
I QPl
IR
I REFO
ISSO
ISXO
ITH
ITOTAL
kN
MAG
MUG
NF
Po
Po
PSRR
rds(off)
rds(on)
RGS
RO
Ro
ro
ross

RI
ri
riss
Ri
RON

"RON

SIN
SR
TA
td
tOR
tf
tf
THO
toff
ton
tr
tR
trr
ts
t STG
tw
V+
VV ABC
V BS
V BE

peak output current
magnitude of peak output
current
maxi mum output current
(source)
maximum output current
(sink)
photo current
peak-to-peak output current
total quiescent current
charge-pump input current
dc reverse (leakage) current
supply current for reference
supply voltage
strobe load current
voltage (V SS )
supply current for supply
voltage
threshold current
total supply current
normalized faclOr (k N = k/k r )

maximum available power gain
maximum useable power gain
(unneutralized)
noise factor
power output
device dissipation
power supply rejection ratio
small-signal drain-to-source
off-state resistance
static drain-to-source on-state
resistance
gate leakage-current resistance
output resistance
low-frequency output resistance
small-signal output resistance
small-signal, short-circuit,
common-source output
resistance
differential input resistance
small-signal input resistance
small-signal, short-circuit,
common-source input resistance
low-frequency input resistance
ON resistance; the ON-state.
resistance of an analog switch
at specified input and load
conditions.
L'l.ON resistance; the difference
in ON-state resistance between
a.ny ~ analog switches at specifled Input and load conditions
signal-to-noise ratio
.
slew rate
ambient temperature
delay time
differential recovery time
fall time
input-pulse rise time
total harmonic distortion
turn-off time
turn-on time
rise time
input-pulse rise time
reverse recovery time
setup time
storage ti me
pulse width

DC positive supply voltage
OC negative supply voltage
amplifier bias voltage
substrate voltage
base-to-emitter voltage

Terms and Symbols
VBE(sat)
V(BR)CBO
V(BR)CES
V(BR)OI
V(BR)R
V(BR)EBO
V(BR)GSSF

base-ta-emitter saturation
voltage
collector-to-base breakdown
voltage

V G2S

collector-ta-emitter break-

VI
Vl(lim)
VICR

down voltage
dc breakdown voltage between diode and substrate
dc reverse breakdown voltage
emitter-to·base breakdown
voltage
de gate-ta-source forward
breakdown voltage, all other
terminals shorted to source

V(BR)G1SSF

(single-gate types)
dc gate-No.l-to-source
forward breakdown voltage,

V G2S (0ff)

V il
V IH
VIO
IVIOI
"VIOit.T

t.VlOit.T

dc gate No.2-to-source forward

breakdown voltage, all other

t.VlOi"V-

terminals shorted to source

(dual-gate types)
V(BR)GSSR

aVIO

dc gate-ta-source reverse

source (single-gate types)
dc gate-No.2-to-source
reverse breakdown voltage,
all other terminals shorted

to source (dual-gate types)
VCBO
VCC

collector-to-base voltage

drain supply voltage
used as a second positive

supply voltage. It is';;;V OO
and referenced to V SS
VCO
VCEO
VCEO(sus)
VCIO
VCP
VOO

VOG
V OG1
V OG2
VOIO
V OR
VOS
VEE

voltage controlled oscillator
collector-to-emitter voltage
collector-to-emitter
sustaining voltage
collector-to-substrate voltage

charge pump voltage
drain supply voltage (the most
positive supply voltage;
always referenced to ground)
drain-to-gate voltage (singlegate types)
drain-to-gate-No.l voltage
(dual-gate types)
drain-to-gate-No.2 voltage
(single-gate types)
diode-ta-substrate voltage
diode reverse voltage
drain-to-source voltage

source voltage (the most
negative supply voltage in

VF
6 V F i 6T

a

3-supply voltage system)
dc forward voltage
temperature coefficient of

forward voltage drop
VGH

channel gate input voltage,

V Gl

channel gate input voltage,

high level

VGS(Off)

gate-ta-source vol tage
gate-to-source threshold
voltage
gate-to-source cutoff vOltage

temperature coefficient of


e!>
1]

e!>·l

angle of reverse transadmittance, common-source
circuit
input impedance

output impedance
zener impedance
phase angle
phase margi n

efficiency
open-loop phase lag

positive input-offset-voltage
sensitivity
negative input-offset-voltage
sensitivity
average temperature

input limiting voltage (knee)

VN
Vo
6V O i 6 Vi:>VOit. V+
VO(rms)

output noise voltage

VG1S

gate-No.1-to-source voltage

VG1S (Offl

gate-No.1-to-source cutoff

protective diode knee

voltage (protected gate types)

"Vo
V Op _p
VO(al)
VOL

output voltage
dc supply voltage sensitivity
dc supply voltage sensitivity

open-loop output voltage
swing
output voltage temperature
coefficient
output voltage swing
recovered af voltage

output voltage, low level;
the voltage level at an output
when the input logic
conditions have been set to

VOO
VOH

establish logic lOW output.
output offset voltage
output voltage, high level;
the voltage level at an output
when the input logic conditions
have been set to establish a

logic HIGH output.

V OM +
V OM -

maximum output voltage
maximum output voltage

VOP
VOPl

charge pump voltage
charge pump input voltage,
low level
charge-pump input voltage,
high level

V OPH
V REF
V REG
V RR

reference voltage

regulated supply voltage
supply voltage rejection
ratio

VTH
Vz
Yfs

Vis

(single-gate types)

input threshold voltage
zener voltage

magnitude of small-signal,
common-source, shortcircuit forward transfer
admittance (transadmittance)
small-signal, common-source,
short-circuit, input-admittance
(conductance, rea I part of
admittance; susceptance,

imaginary part of admittance)

(dual-gate type)
voltage (dual-gate types)

voltage
temperature coefficient of
magnitude of input offset
voltage

Vi(Lim)
V knee

low level
VGS
VGSITH)

magnitude of input offset

magnitude of small-signal,
common-source, short-circuit,

coefficient of input-offset
voltage

breakdown voltage, all
ather terminals shorted to

V(BR)G2SSR

input·voltage, low level
input-voltage, high level
input offset voltage

lYrsl

input offset voltage drift
t. V lO i6 V+

Source (dual-gate types)

input limiting voltage
common-mode input voltage

range

all other terminals shorted to

V(BR)G2SSF

gate-No.2-to-source voltage
(dual-gate types)
gate-No.2-to-source cutoff
voltage (dual-gate types)
input voltage

Yos

small-signal, common-source,
short-circuit, output
admittance

11

Cross-Reference Directory for Linear Integrated Circuits
Industry
Type

RCA
Replacement
Type

Industry
Type

RCA
Replacement
Type

Industry
Type

RCA
Replacement
Type

AD101AH
AD101AN
AD201AH
AD201AN
AD301AH

CA101AT
CA101AG,CA101AE
CA201AT
CA201AG,CA201AE
CA301 AT

HA2·2720
ITI1352N
ITI3064C
ITI3064N
ITI3065N

CA3078E
CA1352E
CA3064T
CA3064E
CA3065E

LM201AP
LM201AT
LM201AV
LM201 0
LM201F

CA201AG,CA201AE
CA201AT
CA201AG, CA201AE
CA201G
CA201G

AD301AN
AD741H
AD741N
AD741CH
AD741CN

CA301AG,CA301AE
CA741T
CA741G,CA741E
CA741CT
CA741CG,CA741CE

L4001M9
LM100
LM101AD
LM101ADE
LM101AF

2N5756
CA3085E
CA101AG
CA101AG
CA101AG

LM201H
LM201J
LM201N
LM201N·14
LM201T

CA201T
CA201G
CA201G, CA201 E
CA201G,CA201 E
CA201T

AD2020
AMLM101AD
AMLM101AH
AMLM101H
AMLM107D

CA3162E
CA101AG
CA101AT
CA101T
CA107G

LM101AH
LM101AJ
LM101AJG
LM101AL
LM101AN

CA101AT
CA101AG
CA101AG
CA101AT
CA101AG,CA101AE

LM207D
LM207F
LM207H
LM207J
LM207N

CA207G
CA207G
CA207T
CA207G
CA207G, CA207E

AMLM107H
AMLM111D
AMLM111H
AMLM201AD
AMLM201AH

CA107T
CA111G
CA111T
CA201AG
CA201AT

LM101AP
LM101AT
LM101D
LM101F
LM101H

CA101AG, CA101AE
CA101AT
CA101G
CA101G
CA101T

LM207T
LM211D
LM211H
LM211N
LM211T

CA207T
CA211G
CA211T
CA211G, CA211E
CA211T

AMLM201D
AMLM201H
AMLM207D
AMLM207H
AMLM211D

CA201G
CA201T
CA207G
CA207T
CA2111G

LM101J
LM101N
LM101T
LM107D
LM107DE

CA101G
CA101G, CA101E
CA101T
CA107G
CA107G

LM224A
LM224D
LM224F
LM224N
LM224T

CA224G,CA224E
CA224G
CA224G
CA224G,CA224E
CA224G

AMLM211H
AMLM301AD
AMLM301AH
AMLM301H
AMLM307D

CA2111T
CA301AG
CA301 AT
CA301T
CA307G

LM107F
LM107H
LM111JG
LM107N
LM111P

CA107G
CA107T
CA111G
CA107G, CA107E
CA111G, CA111E

LM239AD
LM239AF
LM239AJ
LM239AN
LM239A

CA239AG
CA239AG
CA239AG
CA239AG, CA239AE
CA239G, CA239E

AMLM307H
AMLM311D
AMLM311H
AM723HC
AM723HM

CA307T
CA311G
CA311T
CA723CT
CA723T

LM107T
LM111D
LM111H
LM111L
LM111N

CA107T
CA111G
CA111T
CA111T
CA111G, CA111E

LM239D
LM239F
LM239J
LM239N
LM258AH

CA239G
CA239G
CA239G
LM239G, CA239E
CA258AT

AM741DC
AM741DM
AM741HC
AM741HM
AM747DC

CA741CG
CA741G
CA741CT
CA741T
CA747CG

LM111T
LM111V
LM124D
LM124F
LM124J

CA111T
CA111G,CA111E
CA124G
CA124G
CA124G

LM258AN
LM258AT
LM258AJ
LM258JG
LM258H

CA258AG, CA258AE
CA258AT
CA258AG
CA258G
CA258T

AM747DM
AM747HC
AM747HM
AM748DC
AM748HC

CA747G
CA747CT
CA747T
CA748CG
CA748CT

LM124N
LM139AD
LM139AF
LM139AJ
LM139AN

CA124G, CA124E
CA139AG
CA139AG
CA139AG
CA139AG, CA139AE

LM258L
LM258N
LM258P
LM258T
LM301AD

CA258T
CA258G, CA258E
CA258G, CA258E
CA258T
CA301AG

AM748DM
AM1458H
AM1558H
DH3724CN
DH3725CN

CA748G
CA1458T
CA1558T
CA3724G
CA3725F

LM139A
LM139D
LM139F
LM139J
LM139N

CA139G,CA139E
CA139G
CA139G
CA139G
CA139G, CA139E

LM301AH
LM301AF
LM301AJ
LM301AJG
LM301AL

CA301 AT
CA301AG
CA301AG
CA301AG
CA301 AT

FPQ3724
FPQ3725
HA1·2111·2
HA1·2211-4
HA1·2311·5

CA3724G
CA3725G
CA111G
CA211G
CA311G

LMl58AH
LM158AN
LM158AT
LM158JG
LM158L

CA158AT
CA158AG, CA158AE
CA158AT
CA158G
CA158T

LM301AN
LM301AP
LM301AT
LM301AV
LM301T

CA301AG, CA301AE
CA301AG, CA301AE
CA301AT
CA301AG, CA301AE
CA301T

HA1·2630
HA1·2650
HA1·2655
HA1·2720
HA2·2111·2

CA3020
CA1558G, CA1558E
CA1458G, CA1458E
CA6078
CA111T

LM158N
LM158P
LM158T
LM201AD
LM201AF

CA158G, CA158E
CA158G, CA158E
CA158T
CA201AG
CA201G

LM307DE
LM307D
LM307F
LM307H
LM307N

CA307G
CA307G
CA307G
CA307T
CA307G, CA307E

HA2·2111·4
HA2·2311·5
HA2·2520
HA2·2650
HA2·2655

CA211T
CA311T
CA3100T
CA1558T
CA1458T

LM201AH
LM201AJ
LM201AJG
LM201AL
LM201AN

CA201AT
CA201AG
CA201AG
CA201AT
CA201AG, CA201AE

LM307T
LM311D
LM311F
LM311H
LM311JG

CA307T
CA311G
CA311G
CA311T
CA311G

12

Cross-Reference Directory for Linear Integrated Circuits
Industry
Type

RCA
Replacement
Type

Industry
Type

RCA
Replacement
Type

Industry
Type

RCA
Replacement
Type

LM3llL
LM3llN
LM3llN-14
LM3llP
LM3llT

CA3llT
CA3llG, CA3llE
CA3llG,CA3llE
CA3llG, CA3llE
CA3llT

LM1558H
LM1558J
LM1558N
LM1800N
LM1820N

CA1558T
CA1558G
CA1558G, CA1558E
CA758E
CA3l23E

MC1558P
MC1558Pl
MC1558T
MCl558U
MC1723CG

CA1558G, CA1558E
CA1558G, CA1558E
CA1558T
CA1558G
CA723CT

LM3l8H
LM324AD
LM324AN
LM324D
LM324F

CA3l30T
CA324AG
CA324AG, CA324AF
CA324G
CA324G

LM1845N
LM2lllN
LM2901N
LM2904N
LM2904P

CA3l20E
CA2lllAE
CA339G
CA2904G
CA2904G

MC1723CP
MC1723G
MC1741CG
MC1741CL
MC1741CPl

CA723CE
CA723T
CA741CT
CA741CG
CA741CG, CA741CE

LM324J
LM324N
LM339AD
LM339AF
LM339AJ

CA324G
CA324G, CA324E
CA339AG
CA339AG
CA339AG

LM3011H
LM3018H
LM30l8AH
LM3019H
LM3026H

CA30ll
CA3018
CA3018A
CA3019
CA3028

MC1741CP2
MC1741G
MC1741L
MC1741U
MC1747CG

CA741CG,CA741CE
CA741T
CA741G
CA741G
CA747CT

LM339AN
LM339A
LM339D
LM339F
LM339J

CA339AG, CA339AE
CA339G, CA339E
CA339G
CA339G
CA339G

LM3028AH
LM30288
LM3039H
LM3045D
LM3046N

CA3026A
CA30268
CA3039
CA3045
CA3046

MC1747CL
MC1747G
MC1747L
MC1748CG
MC1748CPl

CA747CG
CA747T
CA747G
CA748CT
CA748CG, CA748CE

LM339N
LM358AH
LM358AN
LM358AT
LM358JG

CA339G, CA339E
CA358AT
CA358AG, CA358AE
CA358AT
CA358G

LM3053H
LM3054N
LM3084H
LM3084N
LM3065N

CA3053
CA3054
CA3084T
CA3084E
CA3065

MC1748CU
MC1748G
MC1748U
MC3346P
MC3386P

CA748CG
CA748T
CA748G
CA3048
CA3086

LM358H
LM358L
LM358N
LM358P
LM358T

CA358
CA358T
CA358G, CA358E
CA358G, CA358E
CA358T

LM3086N
LM3067N
LM3070N
LM3071N
LM3075N

CA3066
CA3067
CA3070
CA3071
CA3075

MC3401L
MC3401P
MLM101AG
MLM101AU
MLM107G

CA3401G
CA3401E
CA101AT
CA101AG
CA101T

LM393N
LM555CH
LM555CN
LM555H
LM555N

CA3290E
CA555CT
CA555CG, CA555CE
CA555T
CA555G, CA555E

LM3086N
LM3089N
LM3128N
LM3l46AN
LM3401N

CA30B6
CA3089E, CA3189E
CA3126E
CA3l46AE
CA3401G, CA3401 E

MLM107U
MLMll1G
MLM111U
MLM124L
MLM139AL

CA101G
CA111T
CAlllG
CA124G
CA139AG

LM723CD
LM723CH
LM723CN
LM723D
LM723H

CA723CE
CA723CT
CA723CE
CA723E
CA723T

MC13l0P
MC1352P
MC1357P
MC1357PQ
MC1358P

CA1310E
CA1352E
CA2111AE
CA2lllAQ
CA3065

MLM139L
MLMl58G
MLMl58Pl
MLMl58U
MLM201AG

CA139G
CAl58T
CAl58G, CAl58E
CAl58G
CA201AT

LM723N
LM741CH
LM741CJ
LM741CN
LM741H

CA723E
CA741CT
CA741CG
CA741CG, CA741CE
CA741T

MC1384G
MC1384P
MC13Z0P
MC1371P
MC1375P

CA3084T
CA3084E
CA3070
CA3071
CA3075

MLM201APl
MLM201AU
MLM207G
MLM207U
MLM211G

CA201AG, CA201AE
CA201AG
CA207T
CA207G
CA211T

LM741N
LM746N
LM747CD
LM747CH
LM747CJ

CA741G, CA741E
CA3072
CA747CG
CA747CT
CA747CG

MCl389P
MC1391P
MC1394P
MC1398P
MC1455G

CA3069E, CA3189E
CA1391E
CA1394E
CA1398E
CA555CT

MLM2llU
MLM224L
MLM224P
MLM239AL
MLM239AP

CA2llG
CA224G
CA224G, CA224E
CA239AG
CA239AG, CA239AE

LM747CN
LM747D
LM747H
LM747J
LM748CH

CA747CG, CA747CE
CA747G
CA747T
CA747G
CA748CT

MC1455Pl
MC1455U
MCl458JG
MC1458G
MC1458L

CA555CG, CA555CE
CA555CG
CA1458G
CA1458T
CA1458T

MLM239L
MLM239P
MLM258G
MLM258U
MLM301AD

CA239G
CA239G,CA239E
CA258T
CA258G
CA301AG

LM748CJ
LM748CN
LM748H
LM748J
LM13l0N

CA748CG
CA748CG, CA748CE
CA748T
CA748G
CA13l0E

MC1458P
MC1458Pl
MC1458T
MC1541L
MC1555G

CA1458G, CA1458E
CA1458G, CA1458E
CA1458T
CAl541D
CA555T

MLM301AG
MLM301APl
MLM301AU
MLM307G
MLM307Pl

CA301AT
CA301AG, CA301AE
CA301AG
CA307T
CA307G, CA307E

LM1391N
LM1394N
LM1458H
LM1458J
LM1458N

CA1391E
CA1394E
CA1458T
CA1458G
CA1458G, CA1458E

MC1555Pl
MCl555U
MCl558JG
MC1558G
MC1558L

CA555CG, CA555CE
CA555G
CA1558T
CA1558T
CA1558T

MLM307U
MLM3llG
MLM3llPl
MLM311U
MLM324L

CA307G
CA3llT
CA311G, CA3l1E
CA3llG
CA324G, CA324E

13

Cross-Reference Directory for Linear Integrated Circuits
Industry
Type

RCA
Replacement
Type

Industry
Type

RCA
Replacement
Type

Industry
Type

RCA
Replacement
Type

MLM324Pl
MLM339AL
MLM339AP
MLM339L
MLM339P

CA324G
CA339AG
CA339AG, CA339AE
CA339G
CA339G, CA339E

SFC2207
SFC2211
SFC2301A
SFC2301ADC
SFC2307

CA207T
CA211T
CA301AT
CA301AE
CA307T

SG3082J
SG3083J
SG3401N
SN52101AJ
SN52101AL

CA3082F
CA3083F
CA3401G, CA3401E
CA101AG
CA101AT

MLM358G
MLM358Pl
MLM358U
MPQ3724
MPQ3725

CA358T
CA358G, CA358E
CA358G
CA3724G
CA3725G

SFC2311
SFC2741C
SFC2741M
SFC2748DC
SFC2748C

CA311T
CA741CT
CA741T
CA748CE
CA748CT

SN52101AN
SN52101AP
SN52107L
SN52107P
SN52111L

CA101AG
CA101AG, CA101AE
CA107T
CA107G, CA107E
CAlllT

NE555JG
NE555P
NE555L
NE555T
NE555V

CA555CG
CA555CG,CA555CE
CA555T
CA555CT
CA555CG, CA555CE

SG101AD
SG101D
SG107D
SGlllD
SGlllM

CA101AG
CA101G
CA107G
CAlllG
CAlllG, CAlllE

SN5211P
SN52555L
SN52555P
SN52558L
SN52558P

CAlllG, CAlllE
CA555T
CA555G, CA555E
CA1558T
CA1558G, CA1558E

PM741J
PM741CJ
PM741Y
PM741CY
PM747K

CA741T
CA741CT
CA741G
CA741CG
CA747T

SGll1T
SG201AD
SG201AM
SG201N
SG201M

CAll1T
CA201AG
CA201AG
CA201G, CA201E
CA201G, CA201E

SN52723N
SN52723L
SN52741J
SN52741L
SN52741N

CA723E
CA723T
CA741CG
CA741CT
CA741CG,CA741CE

PM747CK
PM747Y
PM747CY
Q2T3725
RC555DE

CA747CT
CA747G
CA747CG
CA3725G
CA555CG

SG207D
SG207N
SG207T
SG211D
SG211M

CA207G
CA207G, CA207E
CA207T
CA211G
CA211G, CA211E

SN52741P
SN52747L
SN52747N
SN52748J
SN52748L

CA741CG, CA741CE
CA747T
CA747G, CA747E
CA748G
CA748T

RC555NB
RC555T
RC723DB
RC723T
RCl458DE

CA555CG, CA555CE
CA555CT
CA723CE
CA723CT
CA1458G

SG211T
SG301AM
SG301AT
SG301N
SG301T

CA211T
CA301AG, CA301AE
CA301AT
CA301G, CA301E
CA301T

SN52748N
SN52748P
SN 72301 AJ
SN72301AL
SN72301AN

CA748G,CA748E
CA748G, CA748E
CA301AG
CA301AT
CA301AG,CA301AE

RC1458NB
RC1458T
RC3401DB
RC741DB
RC741DC

CA1458G, CAl458E
CA1458T
CA3401G, CA3401E
CA741CG,CA741CE
CA741CG

SG307D
SG307N
SG307T
SG311D
SG311M

CA307G
CA307G, CA307E
CA307T
CA311G
CA311G, CA311E

SN72301AP
SN72307L
SN72307N
SN72307P
SN72311L

CA301AG
CA307T
CA307G,CA307E
CA307G, CA307E
CA311T

RC741DE
RC741NB
RC741T
RC747DC
RC747DB

CA741CG
CA741CG, CA741CE
CA741T
CA747CG
CA747CG, CA747CE

SG311T
SG723CN
SG723CT
SG723T
SG741CD

CA311T
CA723CE
CA723CT
CA723T
CA741CG

SN72311P
SN72555L
SN72555P
SN72558L
SN72558P

CA311G, CA311E
CA555CT
CA555CG, CA555CE
CA1458T
CA1458G, CA1458E

RC747T
RM555DE
RM555T
RM723T
RM741DC

CA747T
CA555G
CA555T
CA723T
CA741G

SG741CM
SG741CN
SG741CT
SG741D
SG741T

CA741CG
CA741CG,CA741CE
CA741CT
CA741G
CA741T

SN72723N
SN72723L
SN72741J
SN72741L
SN72741N

CA723CE
CA723CT
CA741CG
CA741CT
CA741CG,CA741CE

RM741DE
RM741T
RM747DC
RM747T
RM1558DE

CA741G
CA741T
CA747G
CA747T
CA1558G

SG747CD
SG747CN
SG747CT
SG747D
SG747T

CA747CG
CA747CG, CA747CE
CA747CT
CA747G
CA747T

SN72741P
SN72747J
SN72747L
SN72747N
SN72748J

CA741CG, CA741CE
CA747CG
CA747CT
CA747CG, CA747CE
CA748CG

RM1558T
SE555JG
SE555L
SE555N
SE555P

CA1558T
CA555G
CA555T
CA555G, CA555E
CA555G, CA555E

SG748CM
SG748CN
SG748CT
SG748T
SG1458M

CA748CG
CA748CG, CA748CE
CA748CT
CA748T
CA1458G, CA1458E

SN72748L
SN72748N
SN72748P
SN76115N
SN76116N

CA748CT
CA748CG,CA748CE
CA748CG, CA748CE
CA1310E
CA758E

SE555T
SE9300
SE9301
SE9302
SE9303

CA555T
RCA120
RCA121
RCA122
2N6384

SG1458T
SG1558T
SG3018T
SG3018AT
SG3058J

CA1458T
CA1558T
CA3018
CA3018A
CA3058D

SN76242N
SN76243AN
SN76264N
SN76266N
SN76267N

CA3070
CA3071
CA3072
CA3066
CA3067

SE9304
SFC2101A
SFC2107M
SFC211M
SFC2201A

2N6385
CA101AT
CA107T
CAll1T
CA201AT

SG3059J
SG3079J
SG3081N
SG3061J
SG3082N

CA3059D
CA3079D'
CA3081E
CA3081F
CA3082E

SN76298N
SN76564N
SN76565N
SN76635N
SN76650N

CA1398E
CA3064
CA3064E
CA3123E
CA1352E

14

Cross-Reference Directory for Linear Integrated Circuits
Industry
Type

RCA
Replacement
Type

Industry
Type

RCA
Replacement
Type

Industry
Type

RCA
Replacement
Type

SN76666N
SN76675N
SN76676P
SN76689N
SP3724

CA3065
CA3075
CA3076
CA3069E, CA3189E
CA3724G

~101H
~107H
~lllH
~lllR
~201AD

CA101T
CA107T
CAll1T
CAlllG
CA201AG

~748CJ
~74ecL
~74ecN
~47ecP
~748CT

CA748CG
CA748T
CA748G,CA748E
CA748G,CA748E
CA748CT

SP3725
SSS101AJ
SSS101AP
SSS107J
SSS107P

CA3725G
CA101AT
CA101AG, CA101AE
CA107T
CA107G, CA107E

~201AH
~201D
~201H
~207H

~748DC

~301AD

CA201AT
CA201G
CA201AT
CA207T
CA301AG

CA748CG
CA748G, CA748E
CA748CT
CA748T
CA748G

SSS201AJ
SSS201AP
SSS207J
SSS301AJ
SSS301AP

CA201AT
CA201AG, CA201AE
CA207T
CA301AT
CA301AG, CA301AE

~301AH
~307H
~307T
~301AT
~311H

CA301AT
CA307T
CA307G, CA307E
CA301AG, CA301AE
CA311T

~748MJ

SSS741CJ
SSS1458J
SSS1558J
TBA81OS
TBA810AS

CA741CT
CA1458T
CA1558T
CA810Q
CA810QM

~311R

CA311G
CA311G, CA311E
CA555CT
CA555T
CA555CG, CA555CE

~748TC

~758PC
~780PC
~781PC
~787PC

CA748CG, CA748CE
CA758E
CA3070
CA3071
CA3126Q

TDA2002V
TDA2002H
TBB0747
TBB0748
TBB0748B

CA2002
CA2002M
CA747CT
CA748CT
CA748CE

~720PC
~723CA

CA3123E
CA723CE
CA723CT
CA723CT
CA723CE

~1391T
~1394T
~1458HC
~1458Rl
~1458HC

CA1391E
CA1394E
CA1458T
CA1458G
CA1458G, CAl458E

TBB1458B
TBC0747
TCA270
TDA3081N
TDA3062N

CAl458E
CA747T
CA270
CA3061
CA3082

~723DM
~723HC

~723HM
~723K
~723MN

CA723E
CA723CT
CA723T
CA723T
CA723E

~1558HM
~3018HM
~3018AHM
~3019HM
~3026HM

CA1558T
CA3018
CA3018A
CA3019
CA3026

TDA3083N
TDB0723
TDB0723A
TDC0723
U5B7741312

CA3083
CA723CT
CA723CE
CA723T
CA741T

~723ML
~723PC
~741CJG
~741CJ
~741CN

CA723T
CA723CE
CA741CG
CA741CG
CA741CG,CA741CE

~3036HM
~3039HM
~3045DM
~3048DC
~3064HC

CA3036
CA3039
CA3045
CA3046
CA3064T

U5B7741383
U5B7748312
U5B7748383
U5R7723312
U5R7723393

CA741CT
CA748T
CA748CT
CA723T
CA723CT

~741CL
~741CP
~741CT
~741DC
~741DM

CA741T
CA741CG, CA741CE
CA741CT
CA741G
CA741G

~3064PC
~3065PC
~3066PC

CA3064E
CA3065
CA3066
CA3075
CA3066F

U6A7723393
U9T7758393
U9T7741393
ULN2111A
ULN2111N

CA723CG, CA723CE
CA1458G
CA741CG, CA741CE
CA2111AE
CA2111AQ

~741HC
~741HM
~741MJG

CA741CT
CA741T
CA741G
CA741G
CA741T

"PC151A
"PC151C
"PC157A

CA3069E, CA3189E
CA3401 G, CA3401 E
CA741CT
CA741CG, CA741CE
CA301 AT

ULN2114A
ULN2124A
ULN2125A
ULN2127A
ULN2129A

CA3072
CA3070
CA3120E
CA3071
CA3075

~741MN
~741MP
~741PC

~748PC
~747CA

CA741G,CA741E
CA741G, CA741E
CA741G, CA741E
CA3072
CA747CE

"PC157C
"PC251A
"PC251C
"PC301AC
"PC311C

CA301AG, CA301AE
CA747CT
CA1458G, CA1458E
CA301AG, CA301AE
CA311G, CA311E

ULN2137A
ULN2165A
ULN2210A
ULN2212B
ULN2262A

CA3123E
CA3065
CA1310E
CA3012
CA3126Q

~747CJ
~747CK
~747CL
~747CN
~747DC

CA747CG
CA747CT
CA747CT
CA747CG, CA747CE
CA747CG

"PC324C
"PC339C
"PC741C
"PC145BC

CA324G, CA324E
CA339G, CA339E
CA741CG, CA741CE
CA1458G, CAl458E

ULN2264A
ULN2266A
ULN2267A
ULN2269A
ULN2289A

CA3064
CA3066
CA3067
CA3121E
CA3089E, CA3189E

~747DM

CA747G
CA747CT
CA747T
CA747G
CA747T

ULN2298A
ULX2244A

CA1398E
CA758E
CA101AT
CA101AG
CA101G

~747MN

~101AH

~101AD
~101D

~311T
~555HC
~555HM
~555TC

~723CK
~723CL
~723CN

~741MJ
~741ML

~747HC
~747HM
~747MJ
~747ML

~747PC
~747A
~747K
~748CJG

~748DM
~748HC
~748HM
~748MJG

~748ML
~748MN
~748MP
~748T

~3075PC

~3066DC
~3089E
~3401P

CA748G
CA748T
CA748G,CA748E
CA746G, CA748E
CA748T

CA747G, CA747E
CA747G, CA747E
CA747E
CA747T
CA748G

15

16 ________________

~

______________________________________________

Linear Integrated Circuits
for Industrial Applications
Technical Data

_ _ _ _ _ _ _ _ _ _ _ _ _ 17

CA101, CA201, CA301 Types

Operational Amplifiers
For Commercial, Industrial, and Military Applications
RCA-CA10l, CA101A, CA201, CA201A,
and CA301 A are general-purpose, high-gain
operational amplifiers for use in military,
industrial, and commercial applications.
These types, which are externally phase
compensated, permit a choice of operation
for optimum high-frequency performance at
a selected gain; unity-gain compensation can
be obtained with a single 30-pF capacitor.
Types CA101A and CA201A have all the
desirable features and characteristics of the

CA 101 and CA201, respectively, plus superior
input-offset characteristics, and improved
noise performance.
All types are available in hermetic gold-CHIP
dual-in-line plastic packages (G suffix), 8-lead
TO-5 style packages with standard leads (T
suffix), and with dual-in-line formed leads
("DIL-CAN", S suffix). The CA301 A is also
available in the 8-lead dual-in-line plastic
package ("MINI-DIP", E suffix), and in chip
form (H suffix).

Maximum Ratings, Absolute·Maximum Values at TA = 2f50c
DC SUPPLY VOLTAGE (between V+ and V- terminal,I:
CA 101, CA 101 A, CA201, CA201 A.

44

CA301A

36

V

±15

V

±30

V

DC INPUT VOLTAGE _

V

(For supply voltage Jess than ± 15 V, the
Input Voltage rating is equal to the DC Supply Voltage)
DIFFERENTIAL INPUT VOLTAGE
OUTPUT SHORT-CIRCUIT DURATION

. Indefinite*

DEVICE DISSIPATION:
Up to T A = 75°C.
Above T A

500

= 75°C.

mW

derate linearly at 6.67 mW/oC

"G" Suffix Types-Hermetic Gold·CHIP
Dual·ln·Line Plastic Package
"E" Suffix Types-Standard Dual·ln·Line
Plastic Package
"T" and "s" Suffix Types-TO-5 Style Package

Features:
•

Short·circuit protection and latch·free

•

Unity·gain phase compensation with a
single 30·pF capacitor
Replacement for industry types 101,
101A,201,201A,301A

operation

•

Applications:
•

Long·interval integrator

•
•
•
•
•
•
•
•
•
•

Timers
Sample and hold circuits
Summing amplifiers
Multivibrators
Comparators
Instrumentation
AC/DC converters
I nverting amplifiers
Sine· & square·wave generators
Capacitance multipliers &
simulated inductors

AMBIENT TEMPERATURE RANGE:

Operating CAW1, CA101A

-55 to +125 °c

CA201A .

-25 to +85 °c

CA201 , CA301 A

Oto +70 °c

Storage (All types)

-65 to +150 °c

LEAD TEMPERATURE (During Solderingl:
At a distance 1/16"

± 1/32" (1.59 ± 0.79 mml

from case for 10 seconds max. .

*

At T A
TA
TA

+265 0 C

<;;; 70°C and T C <;;; 125°C (CA 1011;
<;;; 75°C and TC <;;; 125°C (CA10l A, CA201AI;
<;;; 55°C and T C <;;; 70°C (CA201, CA301 AI.
v'
7

vNOTE: PIN 4 IS CONNECTED TO CASE
TOP VIEW

a - TO-5 style package for all types

T·Suffix
S·Suffix

v,

PHASE
COMPENSATION

a

OFFSET NULL

'NV
INPUT

5 OFFSET
NULL

CAIOI, CAIOlA
CA201, CA20lA
CA30lA

TOP VIEW

R.

650n

IOHl

b - Plastic package for CA301A

G·Suffix
E·Suffix
Fig.2 - Functional diagrams.

Fig. 1 - Schematic diagram.

18 _________________________________________________________________

CA101, CA201, CA301 Types
ELECTRICAL CHARACTERISTICS
LIMITS

TEST CONDITIONs"
CHARACTER ISTICS Supply Voltage (V±)
= 5 to 15V

CA101

CA201

Min. Typ. Max. Min. Typ. Max.
I nput Offset Voltage
Via

I

-

1

5

-

2

7.5

I RSO(50kQ

-

-

-

-

-

-

RSo(10kQ
RSO(50kQ

-

-

-

-

10
-

RSO(10kQ
RSO(50Q

-

6

-

-

10

-

-

-

-

6

-

-

3
-

--

-

-

-

-55°C to +25 0 C
DoC to +25 0 C
+25 0 C to + 70°C

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Input Offset Current

+25 0 C to + 125°C
T A=OoC

-

-

-

-

-

-

-

-

-

-

150

750

-

-

-

TA-250C

-

40

200

-

100 500

1.5

10

-

3

50

TA=700C

-

-

-

-

50

400

-

-

-

-

110

-

-

-

-

T A=1250C

-

10

200

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

20

-

-

70

TA=-550C

-

100

500

-

-

-

-

-

-

-

-

Input Bias Current

-

TA=-550C

-

0.28

1.5

-

-

-

-

-

-

-

-

-

liB

TA-OoC

-

-

0.32

2

-

-

-

-

T A=25OC

-

0.12

0.5

-

0.25

1.5

-

-

-

--

-

-

-

-

Supply Current

-

-

-

-

-

-

-

-

-

1.8

3

-

1.8

3

-

-

1.2

2.5

-

-

-

50

160

20

150

-

TA=250C
I'

I V±=15V
I V±=20V

T A = 125°C V±=20V
Open-Loop Differen· T A=250C
tial Voltage Gain
VO=±lOV

V±=15V
RL~2kS2

V±=15V

AOL
VO=±lOV

RL~2kS2

-

-

-

25

-

0.3

-

15

-

-

0.1

0.4

-

-

±12

±14

-

±10 ±13

-

±10

±13

-

V±=15V
Common-Mode
I nput- Voltage
V±=20V
Range
VICR

±12

-

-

±12

-

-

-

-

-

-

-

-

Common-Mode
Rejection Ratio
CMRR

RSO(10krl 70

90

-

65

90

-

RSO(50krl

-

-

-

-

-

-

Supply- Voltage
Rejection Ratio
PSRR

RSO(10kn

70

90

-

70

90

-

RSO(50kQ

-

-

-

-

-

-

A

pV/oC

nA/oC

nA

pA

mA

-

0.8

RL=2kl!

mV

-

-

-

-

-

-

0.7

-

-

2
-

-

2
-

7.5
-

-

3

-

10

-

-

-

-

-

-

-

-

-

-

3

15

-

6

30

-

0.0
-

0.2
-

-

-

-

-

-

-

-

-

0.01 0.1

-

0.03 0.075

-

-

-

-

-

0.02 0.6
0.01 0.3

MQ
V

V

dB

dB

mV

pV/oC

nA/oC

-

0.07 0.25

0.1

-

-

-

-

1.8

3

1.8

3

-

-

-

-

1.2

2.5

-

-

-

50

160

-

25

160

-

25

-

-

15

-

-

2

nA

pA

0.3

V/mV

RL =10kU ±12 ±14

Input Resistance RI TA=25OC
V±=15V
Output Voltage
Swing
VOPP V±=15V

-

6
-

UNITS

Min. Typ. Max. Min. Typ. Max.

T A =25 0 C RS";;10kQ

Average Temperature
Coefficient of Input
Offset Voltage eNIO
Average Temperature
Coefficient of Input
Offset Current
[diO

LIMITS
CA101A
CA301A
CA201A

UNITS

mA

V/mV

-

1.5

4

-

0.5

±12

±14

-

±12 ±14

-

±10

±13

-

±10

±13

-

-

-

-

-

-

-

±12

t15

-

-

-

-

-

-

-

-

80

96

-

70

90

-

-

-

-

-

-

-

80

96

-

70

90

-

MQ
V

V

dB

dB

Characteristics applicable over operating temperature range (TAl as shown below, unless otherwise specified:
CA101, CA101A: -55 to +125 0 C; CA201A: -25 to +85 0 C; CA201, CA301A: 0 to 70°C

1

CA101A

CA201A

CA301A

5

7.5

2

2

7.5

200

500

10

10

50

nA

Min. AOL

50

20

50

50

25

V/mV

TA Range

-55 to
+125

o to
+70

-55to
+125

-25to
+85

010
+70

-

-

10

10

10

Max. VIO
Max. '10

TA

CA10l
~

25°C

(Operating)

Slew Rate
(Summing ampl.)

CA201

mV

°c

V//.lS

_____________________________________________________________________ 19

CA101, CA201, CA301 Types
TYPICAL STATIC CHARACTERISTICS
Type CA101

Types CA101. CA101A. and CA201A

'H: ,j!:!

• 00

...
1 zoot
I

,Hi] W!
Ii. t.l;:!!
off miii

.

...

:!!:

... I:

I

""

:

... ....

.... ..

: I'"
:!::

I!n:

I!!l
,,,

.... :::1

!i!

.... .. l!:: 1m 111
".,

:: :

...

I:;:

!;!

fli!lli 1

,1:
'00

I:~

:i: ~
,.,.

tl:

W
I"

50

50

125

12'

100

. lit!

15

AMBIENT TEMPERATURE ITA I-·C

Fig.3 -Input current (I/O, 'IS) vs. temperature.

Fig.4 - Input bias current vs. supply Voltage.

!~1iH,

<

I

;

•

~

~

., . 1~~:~.::
...... ,.

§ • ::;1

·
.",

·.0

I

."

"

'io

"

;

.. ".

.;::~

, .,..1
iii:

'1:

Fl:li •

~

~

IP,

*4- til ,"

~

..... 50;

.
"d·

..

.
.
, .!:!] "":
~

.....
.... , .,

. so:!i
u

ii

20i
50

'00

AMBIENT TEMPERATURE (TAI--C

•

'"

Fig. 5 -Inpurcurrent (1,0, ',B) vs. temperature
(CAIOlA and CA20lA only).

I

J

~+>

I to.

..
I

\

=
~

80 ••••

....
... ....

::: : : : : :: :
::: :
:: :

..

5
LO
15
SUPPLY II(lLTAGE (yi,_V

5
10
15
SUPPLY VOLTAGEIV!I-V

Fig. 7 - Supply characteristics.

Fig.6 - Voltage gain vs. supplV voltage.

i

~

..
Fig.8

~

d

::d
•20

... .SO

OUTPUT CURRENT (101-",...

~

Output characteristics.

TYPICAL DYNAMIC CHARACTERISTICS
AND TEST CIRCUITS FOR TYPES
CA101A AND CA201A
Single.Pole Compensation

TypeCA301A

'0

lill

..

RI Cs
CI ~Ri+"'R"2
tlO

tiS

:t:20

us

:1:;,0

is'

:t40

:1:45

OUTPUT CURRENT iIol-IIIA

TIME 111-,.5

Fig. 9 - Output characteristics,

Q

10'

I

~'OI

ar

10°

~

10'1

5

10'2

U

CS']OpF

Fig. 10 - Test circuit employing single·po/e
compensation.

Fig. 11-Valtage follower (VI, VOl pulse response.

- "L.'L••'Lu".J I.", .,1,v
""-"'"

V

!

'--'

/'

/'

V

:~r~:Tc~~~:A~~~~·r~A~~25.C
CAPACITANCE tCII'lOpF

SINGLE-jLE COMP:rATION

10"

'00
FREOUENCY Ill-HI

FREQuENCY III-HI

Fig. 12 -Closed-loop output impedance vs. frequency.

20 ______________

~

Fig. 13 - Voltage gain and phase lag vs. frequency.

FREQUENCY III-HI

Fig. 14 - Output voltage swing vs. frequency.

_____________________________________________________

CA101, CA201, CA301 Types
Two-Pole Compensation

-,,

RI Cs

CI;?~

Cs·)O

VOLTAGE SUPPLY IV! l'l~v
"N
.. ENT TEMPERAtURE IT"I'2"C
CIoPACITI.NCE: tell, )()pF

(IF

C2' lOCI

IC21')()OpF
TWO·POLE COMPENSATION

I.
Fig.

nMEIII-1'1

16 - Test circuit employing two-pale
compensation.

Fig. 15 - Supply voltage rejection ratio vs. frequency.

17 -

Fig.

Voltage follower pulse response.

Feed-Forward Compensation

'.
\

I\,.
'00.

Fig. 20 - Test circuit employing
feed forward compensation.

FREOuENCY (II-Hz

Fig. 18 - Voltage gain and phase lag vs. frequency.

Fig. 19 - Output voltage swing vs_ frequency,

".

OUT""

\

'"

'\

"

10~
FR[QUE~CY

TIME (1)-,,1

Fig. 21 - Inverter pulse response.

I\.

..

VOLTAGE SUPf>LY IV:tI'I~V
AMBIENT TUIPERATUAE I TAl' 2"C
FEEOFOAWARO COMPENSATION

Fig.

22 -

Voltage gain and phase lag vs. frequency.

I\.

.

....

1101
ItI-Ht

VOLTAGE SUPPLY tV:t"I!iV
AMBIENT TEhiPERATUAE I T A" 2"C
FEEDFORWARD CONPENSATIOtt

1\

f'\
..........

FREQuENCY (II-HI

Fig. 23 -Output voltage swing vs. frequency.

CA101A AND CA201A

, ".

~

__

SOUACE RESISTANCE IRS"IItR

1100 '.'''.'IE.,,"';;.t~~:+- +-S f--I---~
"<"
~ 1---1<'~
~

..
..

<.~

..

~

"/0"

§

I"

,~

2.

10'

2

4

&

'102

2

4 S'IO'

2

4 e'104

2

FR[QUE~CY

FREQUENCY (iI-HI

Fig. 24 - Ilf noise voltage vs. frequency.

Fig.

25 -

>-=
tlV

4 G'IO!

I If noise current vs. frequency.

Fig.

26 -

(II-H.

Common-mode rejection ratio vs. frequency.

___________________________________________________________________ 21

CA107, CA207, CA307 Types
"G" Suffix Types-Hermetic Gold-CHIP in
Dual-I n-Line Plastic Package
"E" Suffix Types-Standard Dual-In-Line
Plastic Package
"T" and "S" Suffix Types-TO-S Style Package

Operational Amplifiers
For Military, Industrial, and Commercial Applications
RGA-CA107, CA207, CA307 are generalpurpose operational amplifiers intended for
use in military, industrial, and com mercia I applications. A 30-pF on-chip capacitor
provides internal frequency compensation.
Low input current over tempe"iture range
(100 nA max.) for the GA107 and CA207
make these types especially well suited for
applications such as long interval timers and
sample-and-hold circuits.
All types are available in hermetic gold-CHIP
dual-in-line plastic packages (G suffix), 8-lead

~
Type

CA107

TO-5 style packages with standard leads (T
suffix), and with dual-in-line formed leads
("01 L-GAN", S suffix). The CA307 is also
available in the 8-lead dual-in-line plastic
package ("MINI-DIP", E suffix), and in chip
form (H suffix).

Applications:
• Long-interval integrators
• Timers
• Sample-and·hold circuits
• Summing amplifiers
• Multivibrators

The CAl 07, CA207, and CA307 are direct
replacements for industry types 107~ 207,
and 307 in packages with similar terminal
arrangements.

Temp_
Range ITA)

Max. VIO
(mV)

Max. 110
(nA)

Max. liB
(nA)

3

20

100

-55to+125

Package
(Suffix)

TOP VIEW

°c

GA207

3

20

100

-2510 +85*

CA307

10

70

300

o to +7!J.A

Functional diagram for plastic package.

G,S, T
G, S, T
G, E, S, T

*Types CA207G, S, and T can be operated over the temperature range of -55 to +12SoC, although the
published limits for certain electrical specifications apply only over the temp. range of -25 to +8SoC.
"'Types CA307G, E, 5, and T can be operated over the temperature range of -55 to +125°C,alt~ough the
published limits for certain electrical specifications apply onlv over the temp. range of 0 to 70 C.

vNOTE: PIN 4 IS CONNECTED TO CASE
TOP VIEW

Functional diagram for TO-5 sw'e packages.

v·
7

2.'

.

v.

2!I'C

o
Fig.

'101

fI
10
Ifl
SUPPLY VOLTAGE (ViI_V

2 - Supply current vs. supply voltage_

110

;~

- .. 'C

,zs-c

t

Fig. I - Schematic diagram of CA 107, CA207, and CA307.

'0o

S
10
I~
SUPPLY VOLTAGE (\It,_ v

20

Fig. 3 - Open..Joop differential voltage gain vs.

supply voltage.

22 ______________________________________________________________

CA107, CA207, CA307 Types

I

;

Maximum Ratings, Absolute-Maximum Values at TA = 25° c:
DC SUPPLY VOLTAGE (Between V+ and V- Terminals):
CA107. CA207
CA307
DC INPUT VOLTAGE
(For supply voltages less than ±15 V, the absOlute maximum input voltage is equal
to the supply voltage)

44

V

36

V

±15

V

±30
V
Indefinite
500
mW
6.67mWtC

DIFFERENTIAL INPUT VOLTAGE.
OUTPUT SHORT-CI RCUIT DURATION'
DEVICE DISSIPA110N UP TO T A c, lOoC
Above T A'" 70 C Derate linearly at
AMBIENT TEMPERATURE RANGE:
Operating - CA 107.

AMBIENT TEMPERATURE l TAI-"C

Fig. 4 - Input offset and input bias currents vs.
ambient temperature.

-5S0C to +12S o C
_25 0 C to +8S0C A

CA20l .

aOc to +70 0C t
-6SoC to +150 oC

CA307.
Storage - All Types.

LEAD TEMPERATURE (During Soldering):

"".PPLY I~L7:~ElV~~·t~v :111 i) . I;:
:tI IfiIlWII"iI: ... J ;1:: ;

± 1/32 inch (1.59 ± 0.79 mm) from case for 10 seconds max.

At distance 1J16

*For type CA307 continuous short circuit is allowed for Case Temperature to +70o C and ambient temperature
to +5SoC.

·Types CA207G, S, and T can be operated over the temperature range of -55 to +125° C,although the published
limits for certain electrical specifications apply only over the cemperature range of -25 to +8S oC.

I,

tTypes CA307G, E. S, and T can be operated over the temperature range of -55 to +1 2SoC, alth~ugh the published limits for certain electrical specifications apply only over the temperature range of 0 to 70 C.

OUTPUT CURRENT (101-m'"

Fig. 5 - Output voltage swing vs. output current.

.-f

:If '
101

2

4

6 e l02

l

•

6 810~

2

•

6 8104

FREQUENCY (II-HI

Fig. 6 - 1If noise current vs. frequency.

AMBIENT TEMPERATURE (TAI-"C

~

'0

o

I~

10

Fig. 7 - Supply current vs. supply voltage.

:1:10

:!:I~

tZO

:tZ~

:t30

~

10

SUPPLY VOLTAGE (V1:1-V

1:l~

dl

OUTPUT CURRENT (101-mA

Fig. 9 - Input offset and input bias current vs.
ambient temperature.

~

SUPPLY VOLTAGE (V:I:I-V

Fig. 10 - Output voltage swing vs. output current.

Fig. 8 - Open-loop differential voltage gain vs.
supply voltage.

101

2

•

6 8 102

2

4 6

elo '

2

•

6 8 10 •

2

•

6 8105

FREQUENCY (fl-Hr

Fig. 11 - 1If noise current vs. frequency.

_________________________________________________________________________ 23

CA107, CA207, CA307 Types
ELECTRICAL CHARACTERISTICS
TEST CONDITIONs"
CHARACTERISTIC

Input Offset Voltage,
Via
Average Temperature
Coefficient of Input
Offset Voltage,

.-

LIMITS

CA107
Supply Voltage (V±) =
CA307
CA207
5Vto15V(CA307)
5 Vto 20 V (CA107.CA207) Min. Typ. Max. Min. Typ. Max.

UNITS

-

0.7

2

mV

-

3

-

3

15

TA = 25°C, RS .. 50kn
RS" 50 kn

-

2

7.5

-

10

-"

6

30

I
! .~I~~~~++~-+Hr+-~

~

/-IV;oC

"

101

-

-

20

-

-

70

TA = 25°C

-

1.5

10

-

3

50

See Note 1

-

0.01

0.1

-

0.01

0.3

See Note 2

-

0.02

0.2

-

0.02

0.6

-

-

100

-

-

300

TA = 25°C

30

75

-

70

250

1.2 2.5

-

-

-

Input Offset Current,
110
Average Temperature
Coefficient of Input

Offset Current i
CIlia
Input Bias Current,

liB
Supply Current,
I±

vt = 20 V
T A = 25°C, vt = 20 V,

T A = +125°C,

(CA307 V±= 15 V)
Open-Loop Differential
Voltage Gain,
AOL

Input Resistance,
RI
Output Voltage Swing,

V±=15V,
VO=±10V,RL;;'2kSl
V±=15V,VO=±10V
RL;;'2kH,TA=25°C
T A = 25°C

25

1.8
-

50

160

1.5

4

±12 ±14

VOpp

V±=15V,RL =2kn

±10 ±13

Input Voltage Range,

V±-20V,
(CA307 v± = 15 V)

±15

Supply-Voltage
Rejection Ratio,
PSRR

.. , '10 2

2

.. I

'to'

2

..

$

'10 4 2

. . . '10 5

3
-

15

1.8
-

Fig. 12 - 1If noise voltage vs. frequency.

nA

120 AMBIENT TEMPERATURE (TA)oZS'C
~PLY VOLTAGE (V;t}ol!5V

nAtC

i

nA

rnA

3

~

j
~~

~

~

-

-

-

25

-

0.5

-

±12

-

±12

'0

2

-

MH

±14

-

V

-

V

40

~

20

0

,

~

'"

0

. .

,

1\,

,

Fig. 13 - Open·Joop differential voltage gain vs.
frequency.

;tIS AM9IENT TEMPERATURE (TAloZS·C
SUPPLY VOLTAGE {V;tlol!5V

I

1

\
;tIZI---+--+--\c-t+--+----j--t-t---'

\\

~

•~

RS" 50 kn

80

96

-

70

90

-

dB

RS" 50 kn

80

96

-

70

96

-

dB

1,\
103

Note 1: For: CA 101, +25, to +12SoC; For CA207, +25 to +8SoC: For CA307. +25 to 70°C.
Note 2: For CA107, -55 10 +2SoC; For CA207, -25 to +2SoC: For CA307, 0 to +2SoC .

~

FREQUENCY (fl-HI

-

-

~

.0

-20

160

±10 ±13

100

~

V/mV

V±=15V,Re1Okn

VICR
Common-Mode
Rejection Ratio,
CMRR

2

FREQUENCY ( f ! - Hz

ClVIO

iii

'10.

FREQUENCY (f)-HI

iii

iii

10"

9ZC,,·Z3996

Fig. 14 - Output voltage swing vs. frequency.

.. Characteristics applicable over operating ter1J.perature range as shown below unless otherwise specified.
CAt07 - TA

=-55 to +t2~

C

CA207 - T A = -25 to +85 C
CA307 - T A = 0 to 70°C

TIME

{tJ-,..s
92CS-23997

Fig. 15 - Voltage follower pulse response.

24 ________________~--__------__------------------------------------

CA111, CA211, CA311 Types

Voltage Comparators

v+
7 OUTPUT

For Commercial and Industrial Applications

6 I NPUT OFFSET!
STROBE

"G" Suffix Types-Hermetjc Gold-CHIP in
Dual-In-Line Plastic Package
"E" Suffix Types-Standard Dual-In-Line
Plastic Package
"T" and "s" Suffix Types-TO-5 Style Package

Applications
•
•
•
•
•

Multivibrators
Positive and negative peak detectors
Crystal oscillators
Zero-crossing detectors
Solenoid, relay, and lamp drivers

5 INPUT OFFSET

Functional diagram for plastic package.
vNOTE: PIN 4 IS CONNECTED TO CASE

Functional diagram for TO·S· style package.

~
Type

Features
•
•
•
•

Single- or dual-supply operation
Power consumption -135 mW at ±15 V
Strobe capability
Low input-offset current:
CAlll, CA211 - 4 nAltyp.)
CA311 - 6 nA(typ.)
• Differential input-voltage range· - ±30 V
• Directly interchangeable with National
Semiconductor LMlll, LM211, and
LM311 Series types

The RCA-CA 111, CA211, and CA311 are
monolithic voltage comparators that operate
from dual supplies up to ±15 V, or from
single supplies down to 5 V. This singlesupply capability makes the outputs of these
devices compatible with RTL, DTL, TTL,
and MOS circuits. In addition, they can drive
lamps or relays, and switch voltages up to
50 V (CA311, 40 V) at currents as high as
50mA.
The inputs and the outputs of the CA 111,
CA211, and CA311 can be isolated from
system ground, allowing the output to
drive loads referred to ground, V+, or V-.
All types are available in hermetic gold-CHIP
dual-in-line plastic packages (G suffix), 8·
lead TO-5 style packages with standard leads
(T suffix). and with dual-in-line formed leads
("DIL-CAN", S suffix). The CA311 is also
available in the 8-lead dual-in-line plastic
package ("MINI- DIP",E suffix). and in chip
form (H suffix).

CAlll
CA211
CA311

Max. VIO
(mV)

Max. 110
(nA)

Max. liB
(nA)

Temp.
Range (TA)
°c

Package

3
3
7.5

10
10
50

100
100
250

-55 to +125
-25 to +856
o to +70t

G,S,T
G,S,T
G,E,S,T

(Suffix)

MAXIMUM RATINGS, Absolute Maximum Values at TA ; 25°C
OC SUPPLY VOLTAGE (between V+ and V- terminal.) . • . . . . . . . • • . • • . • • . • • • . . . . . 36 V
DC INPUT VOLTAGE' . • . . . • . . . . . • . • . • • • . . . . . . . . . . . . . . . . . • . . . • . • • • ±l5 V
DIFFERENTIAL INPUT VOLTAGE . • . . • . . . • • • • • • • . . • . . • • . . • • • . . • • • • • . • ±:lo V
OUTPUT TO NEGATIVE SUPPLY VOLTAGE (V 7 -4):
CAlll.CA211 . • • . • . . . . . . . . • . . . . . • . . • • • . . . . . . . . • • • . • • . . . • • . . . . 50V
CA311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 V
GROUND TO NEGATIVE SUPPLY VOLTAGE (V l -4). . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
OUTPUT SHORT-CIRCUIT DURATION . . • • . . • . . • • • . . . . . . . . . . . . • . . . . . . . • . . 10 s
DEVICE DISSIPATION:
Up to T A = 25°; . . . . . . . . . . . . . . . . . . . . . . . .
AboveT A =25 C . . • . . . • . . . . • • , . . . • • • . . • .
AMBIENT TEMPERATURE RANGE:

. . • . • . . . . . . . • . . . • 500mW

. . . . derate linearly at 6.67 mW/oC

Operating:
CA111 . . • . _ . . . • . . . • . • . . . . . • . . . . . . . • . . . • . . . . . . . . . . . . .-55to+1250C
CA211 . . . • . . . . . . . . • . . . • . . • • • . . . • . . . . . . . . • . . . . . . . . . . .-25 to +85 0C.
CA311 . . . . • • . . . . . . . . • . • . . . . . . . • . . . . • . . . . . • . . • . . . . . . . . 0 to +70 0 C t
Storage, all types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,-65 to +150 oC
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. 0.59 ±0.79 mm)

from case for 10 seconds max. . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . ..

+26SoC

-This rating applies for ±t 5 V supplies. The positive input-voltage limit is 30 V above the negative supply.
The negative input·voltage limit is equal to the negative supply voltage or 30 V below the positive supply.
The negative input-voltage limit is equal to the negative supply voltage or 30 V below the positive supply,
whichever is less.

• Types CA211G,S. and T can be operated over the temperature range of -55 to +125°C,
although the published limits for certain electrical specifications apply only over the temper·
ature range of -25 to +85°C.
Types CA311G,E,S and T can be operated over the temperature range of -55 to +125°C,
although the published limits for certain electrical specifications apply only over the temperature range of 0 to 70°C.

_________________________________________________________________________ 25

CA111, CA211, CA311 Types
TYPICAL CHARACTERISTICS - All TYPES

INPUT
OFFSETI

INPUT

STROBE

OFFSET

TIME (t)-J'-I

Fig. 1 -

Response time for various input

overdrive voltages-positive input.

>

i
!'
';iNC

Fig. 3 - Schematic diagram for CA 111, CA21', and CA311.

TIME (11- ....

Fig. 2 - Response time for various input

overdrive voltages-negative input.

POWER DISSIPATION (Pol

'00

.

O.2~
SHORT-CIRCUIT CURRENT IIsel

Fig. 4 -

Response time for various input

0.0

TI .. £(I)-....

TIME HI- ....

Fig. 5 -

overdrive voltages-positive input.

OUTPUT VOLTAGE IVai-V

Response time for various input

overdrive voltages-negative input.

Fig.' 6 - Output limiting characteristics.

TYPICAL CHARACTERISTCS -CA111, CA211
SUPPLY VOLTAGE (Vtlal5V
TERMINALS 5,6, AND 8 SHQRTED

SUPPLY VOLTAGE {vt)al'"
TERMINALS 5,6, AND 8 SHORTED
!j

'0

POSITIVE SUPPLYOUTPUT LOW

400
POSITIVE AND NEGATIVE SUPPLY-

OUTPUT HIGH

20

'00
200

'0

'00
10152025
SUPPLY VOLTAGE (V+)-V

NORMAL

o

o

-75

-50

-25

0

25

50

75

AMBIENT TEMPERATURE (TAJ _·C

'"

..,~

-!SO.

-te

0

25

so

75

100

125

AMBIENT TEMPERATURE (TA)-·C

Fig. 7 - Supply current V5. supply voltage.

Fig. 8 - Input bias current vs. ambient
temperature.

Fig. 9 - Input offset current vs. ambient
temperature.

26 __________________________________________________________________

CA111, CA211, CA311 Types
ELECTRICAL CHARACTERISTICS
TEST CONDITIONS

8~m

SUPPLY VOLTAGE (V±)-15V

CHARACTERISTICS

UNLESS OTHERWISE SPECIFIED
Input Offset
Voltage. V IO

Rs .;; 5 k

n . Note 2

CA311

UNITS

0.7

3

2

7.5

-

4

-

10

VI = -5 mV.lo = 50 mA
(For CA311, V I ';;-10 mV)

T A =2SoC

0.75

1.5

V+ ;;'4.5 V, V =0, VI';; -6 mV,
ISINK .;; 8 mA
(For CA311, VI .;; -10 mV)

Note 1

0.23

0.4

-

-

Note 1

±14

-

±14

-

I

mV

::~~TV:::O~I~fl"_~III~AI-211-C

'

~
'00

V

o
-I~

Input Voltage
Range, VIPP

Input Offset
Current, 110

Note 2

Input Bias
Current, liB

Note 2

V

~oC

4

10

6

50

Note 1

-

20

-

70

TA=25OC

60

100

100

250

Note 1

-

150

-

300

5.1

6

5.1

7.5

mA

nA

TA = 25°C
TA=250C

4.1

5

4.1

5

mA

TA=25OC

0.2

10

-

0.1

0.5

-

-

I.IA

VI;;'5 mV. Va = 35 V
(For CA311, VI;;' -10 mVI

Output Leakage
Current

Note 1

nA

Strobe On Current

TA=2S u C

3

-

3

-

mA

Voltage Gain, A

TA=25OC

200

-

200

-

V/mV

100 mV Input Step with
5 mV overdrive voltage

TA=25°C

200

-

REFERRED TO SUPPLY VOLTAGES

v'

Negative Supply
Current ,-

,+

0
~
10
OIFFERENTIAL INPUT VOLTAGE.lVro)-V

Fig. 10 - Input characteristcs.

nA

Positive Supply
Current,

Response Time

175

1

TYP. MAX. TYP. MAX.

T A =25OC
Note 1

Saturation Voltage

TYPICAL CHARACTERISTICS - CA111,
CA211 (CONT'D)

LIMITS

-

200

ns

-!IO
-2'
0
2~!iO
AMBIENT TEMPERATURE (TAl,--C

100

12~

Fig. 11 - Common-mode voltage range limits
vs. ambient temperature.
AMBIENT T£;MPERATURE ITAl·~·C
SUPPLY VOLTAGE IV+)' 30 Y

Note 1: Ambient temperature ITA) over applicable operating temperature range as shown
below.

NORMAL OUTPUT
LOAD RESISTANCE (RLl·1 kll
V1_4

CAllI
-55 to +125°C

CA211
-25 to +B5°C

·~o

V

EMITTER - FOLLOWER
OUTPUT
30 RL "600 n

CA311
o to +70 oC

Note 2: The input offset characteristics given are the values required to drive the output to
within 1 V of either supply with a l-mA load. These characteristics define an error
band which takes into account the worst-case effects of voltage gain and input
impedance. The input offset voltage, input offset current, and input bias current
specifications apply for any supply voltage from a 5 V single supply up to a ±15 V
dual supply.

'0

o

-,

-0.'

0

0.'

DIFfERENTIAL INPUT VOLTAGE (VIOl-mY

Fig. 12 - Transfer function.

Jl) i~ ~;::I:
'r' H~ :: ~: ::::
:I: n ::: I i~ j ~

SUPPLY VOLTAGE I" 1"15 V

POSITIVE AHO NEGATIVE SUPPLY-

~T~ITri~~ r InT! n

o
-75
OUTPUT CURRENT IIOI- ....

Fig. 13 - Output saturatjon voltage vs.

output current.

-50

rTTTr.

-25
AMSIENT TEIIIPEAATURf (T.l.I-"C

Fig. 14 - Supply current vs. ambient

temperature.

2'

4'

~

AMBIENT TEMPERATURE lTAl-"C

Fig. 15 -Input and output leakage current
vs. ambient temperature.

________________________________________________________________________ 27

CA111, CA211, CA311 Types
TYPICAL CHARACTERISTICS - CA311

100. AMSIENT tEMPERATURE ITAI.2~.C

SUPPLY VOLTAGE ('1)-15'1
TERMINALS 5,6.ANO 8 SHORTED

SUPPLY VOLTAGE IV·'OIS V
TEllIIIJIALS 5,6, AND 8 SHORTED

RAISED

4.00

RAISED

NORMAL

NO/nUL.

" • '100.:

" . '1M

"

. lfOM

INPUT RESISTANCE IRII- 0

10

2050

40

50

60

1tl80

A..,IOIIT TEMPERATURE (T.. I-·C

Fig. 16 - Offset error.

Fig. 17 -Inputb;ascurrent VS, ambient
temperature.

~

REfERREO TO SUPPLT VOLTAGES

~

~

~

i

I

AMBIENT TEMPERATURE ITAloeS"C
SUPPLY VOLTAGE !V+Jo30V

v'

~

I

Fig. 18 - Input offset current vs. ambient
temperature.

IV+'-0.5

NORMAL OUTPUT
LOAO RESISTANCE IRLlol U1
V7_4 040V

(V+I-I

11/+1-1.5
1'1-1+0.4
1'1")+0,2

v1020
5040
50
601010
AMBIENT TEMPERATURE (TAI-"C

o

Fig. 19 - Input characteristics.

Fig. 20. - Common-mode yoltage range limits ys.
ambient temperature.

Fig. 21 - Transfer function.

,

10' 8 SUPPLY VOLTAGE IV!I'I~ V

SUPPLY VOLTAGE IV jolSV

0.7 AMBIEHT TEMPERATURE

O.S

OIFFERENTIAL INPUT VOLTAGE (VIol-II'!V

DIFFERENTIAL INPUT VOLTAGE 1'1101-\1

0.6

I
l

,

V
!\-JO'·~ V

10-38
~-Jo\..,~G

,0

,.....-POSITIVE SUPPLY -OUTPUT LOW
POSITIVE AND NEGATIVE SUPPLY

OUTPUT HIGH

10"'8

,
,

10-5

20
30
40
so
OUTPUT CURRENT IIol-mA

Fig. 22 - Output saturation voltage vs.
output current.

AMBIENT TEMPERATURE ITAI-*C

Fig. 23 - Supply current ys. ambient
temperature.

00

--

GE.~-J~-J

\~~
3~

I

----

4!>

AMBIENT TEMPERATURE ITA1-·C

Fig. 24 - Input and output leakage current
vs. ambient temperature.

100 8 AMBIENT TEMPERATURE ITA'· 25"C

>

i

"~

f-- 6 8 100k

2

6

8 1M

INPUT RESISTANCE IAZI-.o.

Fig. 25 - Offset error.

28 ________________________________________________________

~------

CA124, CA224, CA324 Types
"E" Suffix Types: Standard Dual-In-Line
Plastic Package
"G" Suffix Types: Hermetic Gold-Chip
Dual-In-Line Plastic Package

Quad Operational Amplifiers
For Commercial, Industrial, and Military Applications
The RCA-CA124, -CA224, and -CA324 consist of four independent, high-gain operational amplifiers on a single monolithic
substrate_ An on-chip capacitor in each of the
amplifiers provides frequency compensation
for unity gain. These devices are designed
specifically to operate from either single or
dual supplies, and the differential voltage
range is equal to the power-supply voltage.
Low power drain and an input commonmode voltage range of from 0 V to V+ -1.5 V

(single-supply operation) make the CA 124,
CA224, and CA324 suitable for battery
operation.
The CA124, CA224, and CA324 are supplied
in a 14-lead dual-in-line plastic package (E
suffix), or in a hermetic gold-chip 14-lead
dual-in-line plastic package (G suffix) to provide true hermetic performance. The CA324
is also available in chip form (H suffix), and
as a hermetic gold-chip (HG suffix).

Features:
•
•
•
•
•
•

Operation from single or dual supplies
Unity-gain bandwidth . . . . . _ 1 MHz (typ.)
DC voltage gain . . . . . . 100 dB (typ.)
Inpllt bias current.
45 nA (typ.)
Input offset voltage
2 mV (typ.)
Input offset current
5 nA (typ.)
tor CA224, CA324
3 nA (typ.) for CA124
• Replacement for industry types 124,224,324

MAXIMUM RATINGS, Absolute-Maximum Values at TA = 2fiOC

Applications

SUPPLY VOLTAGE
DIFFERENTIAL INPUT VOLTAGE.
INPUT VOLTAGE . . . . . .
INPUT CURRENT (VI <-0.3 Vlt .

32Vor±16V
±32 V
-0.3 V to +32 V
SOmA

• Oscillators

OUTPUT SHORT CIRCUIT TO GROUND
(v+ ";15 VI'
DEVICE DISSIPATION:

Up to T A

=

Continuous

55°C

Above T A = 55°C

• Summing amplifiers
• Mu/tivibrators
• Transducer amplifiers
• DC gain blocks

750mW

derate linearly at 6.67 mW/oC

.

AMBIENT TEMPERATURE RANGE:

-55 to +125 0 C
-65 to +150 0 C

Operating.
Storage
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1/16 ± 1/32 in. (1.59 ±0.79 mml

NEG

from case for 10 seconds max.

INPUT I

pos
INPUT I

liThe maximum output current is approximately 40 rnA independent of the magnitude of V+. Continuous

>

short circuits at V+ 15 V can cause excessive power dissipation and eventual destruction. Short circuits
from the output to V+ can cause overheating and eventual destruction of the device.

POS
INPUT 2

tThis input current will only exist when the voltage at any of the input leads is driven negative. This current
is due to the collector-base junction of the input p-n-p transistors becoming forward biased and thereby
acting as input diode clamps. In addition to this diode action, there is also lateral n-p-n parasitic transistor
action on the Ie chip. This transistor action can cause the output voltages of the amplifiers to go to the
V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative.
This transistor action is not destructive and normal output states will re-establish when the input voltage,
which was negative, again returns to a value greater than -0.3 V dc.

92CS'24204

TOP VIEW

Fig. 1 - Functional diagram.

~

.

2

(6

-

,

'.
:[;r
4

4

" -

Fig. 2-Schematic diagram-one of four operational amplifiers.

______________________________________________________________________ 29

CA124, CA224, CA324 Types
ELECTRICAL CHARACTERISTICS (Values apply for each operational amplifier)

TEST CONDITIONS
CHARACTERISTIC

Supply Voltage (V+) = 5 V
Unless Otherwise Specified

CA224. CA324
LIMITS

CA124
LIMITS

UNITS
Min.

Typ.

Max.

Min. Typ.

Max.

TA - 250 C
Input Offset Voltage. VIO

Note 3

-

2

-

2

7

mV

Output Voltage Swing. VOpp

RL - 2 kfl

0

-

V+-1.5 0

-

V+ -1.5

V

Input Common·Mode
Voltage Range, V ICR

Note 2, V+=30 V

0

-

V+-l.5 0

-

V+-1.5

V

11+ -II

-

3

30

50

nA

11+ or II ' Note 1
V I +=+l V, VI =0 V,
V+=15 V

-

45

150

-

5
45

250

nA

40

-

mA
mA

Input Offset Current, 110
Input Bias Current, liB
Output Current (Source), 10

5

20

20

40

-

VI+=O V,VI =1 V,V+=15 V 10

20

-

10

20

-

VI+=O V,VI =1 V,
VO=200 mV

12

50

-

12

50

p.A

94

100

-

88

100

-

Common·Mode Rejection Ratio,
DC
CMRR

70

85

-

65

70

-

dB

Power Supply Rejection Ratio,
PSRR

DC

65

100

-

65

100

-

dB

Amplifier·to·Amplifier
Coupling

f=l to 20 kHz (Input reo
ferred)

-

-120

-

-

-120

-

dB

Output Current (Sink), 10

Large·Signal Voltage Gain, A

RL;;'2 kfl,v+=15 V
(For large Vo swing)

dB

TA =-40 to +85 0 C (CA224),
T A = -55 to +125 0 C

T A = 0 to 70 0 C (CA324)

-

mV

7

-

!lV/oC

-

150

nA

10

-

pA/oC

-

500

nA

-

0.8

2

mA

V+-2

0

-

V+-2

V

-

-

83

-

-

dB

26

-

-

27

28

-

Temperature Coefficient of
Input Offset Voltage,aVIO

Rs = 0

-

7

-

-

Input Offset Current, 110

11+ - II

-

-

100

-

-

10

-

-

Input Bias Current, liB

11+ or II

-

-

300

-

Supply Current, 1+

RL

-

0.8

2

Input Common·Mode
Voltage Range, V ICR

V+ = 30 V

0

-

Large·Signal Voltage Gain, A

RL;;'2 kfl,V+=15 V
(For large Vo swing)

88

Input Offset Voltage, VIO

Temperature Coefficient of
Input Offset Current, aiiO
-~On

All Amp!.

-

7

Output Voltage Swing:
High·Level, VOH
Low·Level, VOL

-

9

Note 3

-

RL =2 kn,V+=30 V

26

-

RL=10kn

27

28

-

RL=10 kn

~

5

20

_.

5

20

mV

-

10

20

-

mA

V

Output Current:
Source, 10

VI+=l VDC,VI-=O,
V+=15 V

10

20

Sink,lO

VI =1 VDC,VI+=O,
V+=15 V

5

8

-

5

8

-

mA

-

V+

-

-

V+

V

Differential Input Voltage

Note 2

-

]

NOTE 1: Due to the p-n·p input stage the direction of the input current is out of the IC. No loading
change exists on the input lines because this current is essentially constant. independent of
the state of the output.
NOTE 2: The input signal voltages and the input common-mode voltage should not be allowed to go
negative by more than 0.3 V. The positive limit of the common-mode voltage range is
V+ - 1.5 V, but either or both inputs can go to +32 V without damage.
NOTE 3: Va = 1.4 VOC' As = 0 n with V+ from 5 V to 30 V; and over the full input commonmode voltage range (0 V to V+ - 1.5 V)'

30 ___________________________________________________________________

CA124, CA224, CA324 Types
TYPICAL CHARACTeRISTICS CURVES

"

i

c

•I

a

"~

z

z

t!

!

~ 4

~

I-

~

3

B2
~
~

~

AMBIENT TEMPERATURE ITA)-

o TO +125·C

~~

"
,

1\'

il

I

,

1)1152021530
SUPPLY VOLTAGE IY+I-Y

AMBIENT TEMPERATURE ITAI-ec

Fig. 4-Supply current drain

Fig. 3-lnput current vs. ambient temperature.

~

VI.

-75

!>-do

'\
,

..I---.. , . ..
'00'

:I

.~o

~

12'

i

100

LOAD IIIESISTANCE IlIIiJ. 20 lit!:

2IIQ

I"
-50

-n

"

,.

"

"'"E"T nMPEIIIATUIIIE ITAI.JC

Fig.

' -

Fig. 5-Large-slgnal frequency response.

supply voltage.

'"
,

•

. ..

..n

FREOUENCY Itl-H,

.
I
~

"' .. ~ >:
~

AMlIENT TEMPERATURE
_iCT,I.Z~·C:,_

6-0u~ut

current

VI.

"

.flCS·2UOI

SUPPLY VOLTAGE IV+I-V

Fig. 7-lnput current

ambient tst1Jperature.

VI.

supply voltage.

,.

Fig. 8- Voltag. gain vs. supply voltag••

AM.lENT TEMPERATURE (TAI-25-cl

sUPPLY

VOLTAGE (Y+I-30Y

>

•I...,

~

i :I---+--+" ~~:-r-'---'--1
~ ..I--I--t--+----"'~
III

1011

10011

fltEQUENCY III-H,

Fig. 9-Opsn-/oop frequency response.

., "b

•

~4OC

VI

~

s

i "'r---r---r---r---r-~~
"

~y

~~ ...

.I.

,.
INPUT

.. !....

OUTPIIT

0

"M

~pF

0

I

..,

;

:

":1
1~

• • • • •
TIMEItJ-,..

Fig. IO-Voltags follower pulse response

•
Fig. 11- Voltags folloWer pulse respons••

(small Signal).

_________________________________________________________________ 31

CA139, CA239, CA339 Types
"E" Suffix Types: Standard Dual-In-Line
Plastic Package
"G" Suffix Types: Hermetic Gold-Chip
Dual-In-Line Plastic Package

Quad Voltage Comparators
For Industrial, Commercial, and Military Applications
The RCA-CA 139, -CA239, -CA339, -CA139A,
-CA239A, and -CA339A types consist of four
independent single- or dual-supply voltage
comparators on a single monolithic substrate.
The common·mode input voltage range includes ground even when operated from a
single supply, and the low power supply current drain makes these comparators suitable
for battery operation. These types were designed to directly interface· with TTL and
and CMOS.

Types CA139A, CA239A, and CA339A
have all the features and characteristics of
their prototype counter parts CA 139. CA239,
and CA339 plus an even lower input-offsetvoltage characteristic. These devices are supplied in a 14-lead dual-in-line plastic package
(E suffix), or in a 14·lead dual-in-line plastic
package with a hermetic chip (G suffix!' to
provide true hermetic performance. The
CA339 is also available in chip form (H
suffix), and as a hermetic chip (HG suffix).

MAXIMUM RATINGS,Absolute·Maximum Values at TA =2SOC:
DC SUPPLY VOLTAGE ............................. .
36Vor±18V
DC DIFFERENTIAL INPUT VOLTAGE ......•..........
±36V
INPUT VOLTAGE •.................................
-0.3 V to +36 V
INPUT CURRENT (VI < -0.3 V)' ..................... .
50mA
OUTPUT SHORT CIRCUIT TO GROUND·
(Single Supply) .................................. .
Continuous
DEVICE DISSIPATION:
750mW
Up to T A = 55°C ............................... .
Above T A = 55 0 C ................................ derate linearly at 6.67 mW/oC
AMBIENT TEMPERATURE RANGE:
Operating ................... , .................. .
-55 to + 125°C
Storage ........................................ .
-65 to +1500 C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm)
from case for 10 seconds max.

Features:
• Operation from single or dual supplies
• Common-mode input-voltage range to ground
• Output voltage compatible with TTL, DTl,
ECl, MOS, and CMOS
• Differential input-voltage range equal to the
supply voltage
• Maximum input-offset voltage (VIO):
CA139A, CA239A, CA339A - 2 mV
CA139, CA239, CA339 -5 mV
• Replacement fQr industry types 139,239
339, 139A, 239A, and 339A

Applications:
• Square-wave generators
• Time-delay generators
• Pulse generators
• Multivibrators
• High-voltage digital logic gates
• AID converters
• MOS clock timers

* Inputs must not go more negative than -0.3 V.
"'Short circuits from the output to V+ can cause excessive heating and eventual destruction.
The maximum output current independent of V+ is approximately 20 rnA.

+------ 15 V can cause excessive power dissipation and eventual destruction. Short circuits

many other conventional op amp circuits
which can benefit from the single power
supply capability.
The CA158, CA158A, CA258, CA258A,
CA358 and CA358A types are supplied in
hermetic gold·CHIP 8·lead dual·in·line plastic
packages (G suffix), 8·lead TO·5 style pack·
ages with standard leads (T suffix). and
with dual·in·line formed leads (01 L·CAN, S
suffix). The CA2904 is supplied only in the
gold·CHIP plastic package (G suffix).
The CA 158, CA 158A, CA258, CA258A,
CA358, CA358A, and CA2904 types are an
equivalent to or a replacement for the in·
dustry types 158, 158A, 258, 258A, 358,
358A, and 2904.

TOP VIEW

from the output to V+ can cause overheating and eventual destruction of the device. DestructivE! dissipation can result from simultaneous short circuits on both amplifiers.

r---~---------1~--~--~--~--~r-_T02

INV.
INPUTIB)

~
+

2

6

1

Fig.2 - Functional diagram for CA 158, CA258,
and CA358 S· and T·suffix types.

-

I Vo

Fig.3 - Functional diagram for CA 158, CA258,
Fig. 1- Schematic diagram - one of two operational amplifiers.

CA358. and CA2904 G·suffix types.

________________________________________________________________________ 35

CA158, CA158A, CA258, CA258A, CA358, CA358A, CA2904 Types
ELECTRICAL CHARACTERISTICS (Values Apply For Each Operational Amplifier)

LIMITS
CA158A (G. T. SI

TEST CONDITIONS
CHARACTERISTIC
Supply Voltage (V+) = 5 V
Unless Otherwise Specified

Min_

Typ_

Max_

UNITS

I~
IiIg

I

I~

TA = 25°C
Input Offset Voltage, Via

Note 3

-

1

2

mV

Output Voltage Swing, VOpp

RL = 2 kQ

0

-

V+ -1.5

V

Inp·ut Common-Mode
Voltage Range, VICR

Note 2, V+ = 30 V

0

-

V+ -1.5

V

Input Offset Current, 110

11+-11

-

2

10

nA

20

50

nA

20

40

-

mA

I

Input Bias Current, liB

11+ or II ,Note 1

Output Current (Source!. 10

VI+=+l V, VI-=O V,
V+= 15 V
VI+=O V, VI-= 1 V, V+=15 V

SUPPLY VOLTAGE (V+l-v

FigA - Input voltage range as a function of
supply voltage.

10

20

-

mA

12

50

-

/lA

I i

VI+=O V, VI-= 1 V,
Vo=200mV

Short Circuit Output Current

R L = 0 (to Ground) Note 4

-

40

60

mA

Large Signal Voltage Gain, AOL

RL>2 kQ, V+= 15 V
(For large Va swing)

50

100

-

V/mV

ia

70

85

-

dB

Power Supply Rejection
Ratio, PSRP

DC

65

100

-

dB

Amplifier-to-Amplifier
Coupling

f= 1 t020 kHz (Input referred)

-

-120

-

dB

~-.

__ •

~

rv-+}.,o v·

'rHt

+

:j-I

:~ t

t

'tIt

1:: '

itl

1

+T

I.V

_

~

5V~

~ 20
10

o

DC

:

SUPPLY VOLTAGE

,-

40

~

Common-Mode Rejection
Ratio, CMRR

il!t

-r

T

50 :

H

Output Current (Sink!. 10

n
g. -:

tt

INPUT COMMON-MODE YOLTAGEj.lf
RANGE (VIeR)' 0 v



a TO

+125 D C

I

_5S0 C

5

10

15

20

25

30

SUPPLY VOLTAGE (V+)-V

Fig.6 - SupplV current drain as a function of
supply voltage.

.
I

!
Q

120

II

I III I IIII I ITI

100

.0

~

~

~
~

i

60

40

20
0
100
INPUT FREQUENCY iflNJ- HI

Fig. 7 - Common mode rejection ratio as a
function of input frequency.

36 _________________________________________________________________

CA158, CA158A, CA258, CA258A, CA358, CA358A, CA2904 Types
AMBIENT TEMPERATURE !TAI'250C

ELECTRICAL CHARACTERISTICS (Values Apply for Each Operational Amplifier)

LOAD RESISTANCE tRd' ZOkn

TEST CONDITIONS
CHARACTERISTIC
Supply Voltage (V+I = 5 V
Unless Otherwise Specified

LIMITS
CA258A (G, T, SI

tit

an

UNITS

"

Min.

Typ.

Max.

TA = 25 0 C
Input Offset Voltage. VIO

Note 3

-

1

3

mV

Output Voltage Swing, VOpp

RL = 2 kQ

0

-

V+ -1.5

V

Input Common-Mode
Voltage Range, VICR

Note 2, V+ =30 V

0

-

V+ -1.5

V

Input Offset Current, 110

11+-11

-

2

15

nA

Input Bias Current, liB

11+ or II ,Note 1

-

40

80

nA

20

40

-

rnA

10

20

-

rnA

12

50

-

pA

-

40

60

mA
V/mV

Output Current (Source),lo

VI+=+lV,VI-=OV,
V+= 15 V
VI+=O V, VI-= 1 V, V+=15 V

Output Current (Sink), 10

VI+=O V, VI-= 1 V,
Vo=200mV

Short Circuit Output Current

R L = 0 (to Ground) Note 4

Large Signal Voltage Gain, AOL

RL>2 kQ, V+= 15 V
(For large Vo swing)

50

100

-

Common-Mode Rejection
Ratio, CMRR

DC

70

85

-

dB

Power' Supply Rejection
Ratio, PSRP

DC

65

100

-

dB

Amplifier-to-Amplifier
Coupling

f = 1 to 20 kHz (Input referred)

-

-120

-

d8

Input Offset Voltage, VIO

Note 3

-

-

4

mV

Temperature Coefficient of
Input Offset Voltage,o:VIO

Rs = 0

-

7

15

pV/oC

Input Offset Current, 110

11+ -11-

-

-

30

nA

-

10

200

pA/oC

'0
SUPPLY VOLTAGE (vtJ_V

Fig.S - Voltage gain as a function of
supply voltage.

,of--t--+--+--f-"""l-..:

FREQUENCY Ill-HI

Fig.9 - Open-loop frequency response.

AMBIENT TEMPERATURE (TA)'25'C'
SUPPLY VOLTAGE Ivt)'15V
LOAD RESISTANCE IRL)·Zkn

T A = -25 to +85 0 C

Temperature Coefficient of
Input Offset Current, 0:110
Input Bias Current, liB

II+or 11-

-

40

100

nA

Input Com(Tlon-Mode
Voltage Range, VICR

V+ = 30 V, Note 2

0

-

V+-2

V

RL = 00 On Ali Amp!.

-

0.7

1.2

RL = 00, V+ = 30 V

-

1.5

3

20

30

40

TlME(tJ-,..
~'-l"lI3

Supply Current, 1+

Fig. 10- Voltage follower pulse response.

rnA
AMBIENT TEMPERATURE (TAI-zsec
SUPPLY VOLTAGE (V+,_ 30 V

NOTE 1: Due tD the p-n-p input stage the direction of the input current is out of the IC. No loading change exists
on the input lines because this current is essentially constant, independent of the state of the output.
NOTE 2: The input signal voltages and the input common-mode voltage should not be allowed to go negative by
more than 0.3 V. The positive limit of the common-mode voltage range is V+ - 1.5 V, but either or both
inputs can go the + 32 V without damage.

,

>

1500

f

~45C

S

NOTE 3: Va = 1.4 VOC. Rs = 0 n with V+ from 5 V to 30 V. and over the full input common-mode voltage range
(0 V to V+ - 1.5 VI.

~4OC

NOTE 4: The maximum output current is approximately 40 mA independent of the magnitude of Vi. Continuous
short circuits at V+ >15 V can cause excessive power dissipation and eventual destruction. Short circuits
from the output to V+ can cause overheating and eventual destruction of thedevice. Destructive dissipation can result from simultaneous short circuits on both amplifiers.

~350

t'C

300
250

o

~
3
•
TIME

5

('1-,.,

Fig. 11 - Voltage follower pulse response
(small signal).

______________________________________________________________________ 37

CA158, CA158A, CA258, CA258A, CA358, CA358A, CA2904 Types
o

ELECTRICAL CHARACTERISTICS (Values Apply for Each Operational Amplifier)

LIMITS
CA358A (G, T, S)

TEST CONDITIONS
CHARACTERISTIC
Supply Voltage (V+) = 5 V
Unless Otherwise Specified

Min. Typ.

l? "
UNITS

Input Offset Voltage, VIO

Note 3

-

2

3

mV

Output Voltage Swing, VOpp

RL = 2 kQ

0

-

V+ -1.5

V

Note 2, V+ = 30 V

Input Offset Current, 110

11+ -II

I~put

11+ or II ,Note 1 .

Bias Current, liB

Output Current (Source), 10

VI+=+lV,VI-=OV,
V+ = 15 V
VI+=O V, VI-= 1 V, V+=15 V

Output Current (Sink), 10

Large Signal Voltage Gain, AOL

R L = 0 (to Ground) Note 4
RL>2H~,V+=15V

(For large Vo swing)

!

,

"

-

5

30

nA

45

100

nA

20

40

-

rnA

10

20

-

rnA

-l.

12

50

-

I1A

a

-

40

60

rnA

25

100

-

V/mV

V

HV

",

'.k

,

: _

_ "n·

.r-.... , . .. ,.
'OOk

FREQUENCY (f)-Hz

92CS-H510

Fig. 12 - Large-signal frequency response.

AMBIENT TEMPERATURE (TAl- 25·C

"
1
~

~~

~

Common-Mode Rejection
Ratio, CMRR

DC

65

85

-

dB

Power' Supply Rejection
Ratio, PSRR

DC

65

100

-

dB

Amplifier-to-Amplifier
Coupling

f = 1 to 20 kHz (I nput referred)

-

-120

-

dB

:!!:

25

,.

·

20

..

30

: SUPPL.Y VOLTAGE !V·I-V

92C$-242!O

Fig. 13 -Input current as a fUnction of

supply voltage.

•

TA = 0 to +70oc

1

Input Offset Voltage, VIO

Note 3

-

-

5

mV

Temperature Coefficient of
Input Offset Voltage,aVIO

Rs = 0

-

7

20

I1V / oC

I nput Offset Current, 110

11+- 11-

-

-

75

nA

10

300

pA/oC

Input Bias Current, liB

II+or 11-

-

40

200

nA

Input Common-Mode
Voltage Range, VICR

V+ = 30 V, Note 2

0

-

V+-2

V

RL = 00 On All.Ampl.

-

0.7

1.2

1.5

3

i. •
~~

~~
~ II!
i$
~!5

Temperature Coefficient of
Input Offset Current, aiiO

Supply Current, 1+

· . ,.

-

V+ -1.5

1\'

,

0

VI+ = 0 V, VI- = 1 V,
Vo=200mV

Short Circuit Output Current

:~
IOn

~VI

,.

~

~

Max.

TA=250 C

Input Common-Mode
Voltage Range, VICR

IOOkfi

AMBIENT TEMPERATURE

I-- ..-(TAI-2S-C, _

5

If-

~

.v+/2

+

_I

_

10·

, r- - INOEPE~NT

OF

,

v'"

TA··20·C

•

,

II

2
I
0.001

....

.,

V-

,.

I

100

OUTPUT SOURCE CURRENT (Iol-mA

9lts-uu:

Fig. 14 - Output source current characteristics.

R L = 00, V+ = 30 V

rnA
I.

NOTE 1: Due to the p-n-p input stage the direction of the input current is out of the IC. No loading change exists
on the input lines because this current is essentially constant, independent of the state of the output,
NOTE 2: The input signal voltages and the input common-mode voltage should not be allowed to go negative by
more than 0,3 V, The positive limit of the common-mode voltage range is V+ - 1,5 V, but either or both
inputs can go the + 32 V without damage.
NOTE 3: Va = 1.4 VDC. Rs = 0 n with V+ from 5 V to 30 V, and over the full input common-mode voltage range
(0 V to V+ - 1.5 VI.
NOTE 4: The maximum output current is approximately 40 mA independent of the magnitude of V+, Continuous
short circuits at V+ >15 V can cause excessive power dissipation and eventual destruction, Short circuits
from the output to V+ can cause overheating and eventual destruction of thedevice. Destructive dissipation can result from simultaneous short circuits on both amplifiers,

V··.5

Voc ffio=ottfl-tti

H-t-ttH-t-ttH, ~:::: ~ H±=fi.'l+tti

001

0.001

0.01

.,

10

100

OUTPUT SINK CURRENT (Iol-mA

Fig. 15 - Output sink current characteristics.

38 ___________________________________________________________________

CA158, CA158A, CA258, CA258A, CA358, CA358A, CA2904 Types
ELECTRICAL CHARACTERISTICS (Values Apply for Each Operational Amplifier)
LIMITS
CA158 (G, T, S)
CA258 (G, T, S)

TEST CONDITIONS
CHARACTERISTIC
Supply Vol1age (V+) = 5 V
Unless Otherwise Specified

Min. Typ.

1
I

~

UNITS

Max.

~
~
~

TA = 250 C
Input Offset Voltage, VIO

Note 3

-

2

5

mV

Output Voltage Swing, VOpp

RL = 2 kil

0

-

V+ -1.5

V

Input Common·Mode
Voltage Range, VICR

Note 2, V+ = 30 V

0

-

V+ -1.5

V

Input Offset Current, 110

11+-11

-

3

30

nA

Input Bias Current, liB

II+or II • Note 1

-

45

150

nA

Output Current (Source). 10

VI+=+l V, VI-=O V,
V+= 15 V

20

40

-

mA

VI+=O V, VI-= 1 V. V+=15 V

10

20

-

mA

12

50

-

/lA

Output Current (Sink l. 10

VI+=O V, VI-= 1 V,
Vo=200mV

I
~

60
'0
.0
>0

"
'0
0

-"

·00

."

0

"

'0

".

AMBIENT TEMPERATURE ITA I--c.

'00

'"

,2CS·l.ZCI

Fig. 16 - Output current as a function of

Short Circuit Output Current

RL = 0 (to Ground) Note 4

-

40

60

mA

Large Signal Voltage Gain, AOL

RL;;' 2 kil, V+= 15 V
(For large Vo swing)

50

100

-

V/mV

Common·Mode Rejection
Ratio, CMRR

DC

70

85

-

dB

Power' Supply Rejection
Ratio, PSRR

DC

65

100

-

dB

Amplifier·to·Amplifier
Coupling

f = 1 to 20 kHz (Input referred)

-

-120

-

dB

ambient temperature.

TA = -55 to + 125°C (CA15B); TA = -25 to +B50C (CA25B)
Input Offset Voltage, VIO

Note 3

-

-

7

mV

Temperature Coefficient of
Input Offset Voltage,exVIO

Rs = 0

-

7

-

/lV/oC

Input Offset Current, 110

11+-11-

-

-

100

nA

-

10

-

pA/oC

Temperature Coefficient of
Input Offset Current, exiiO
Input Bias Current, liB

11+ or II

-

40

300

nA

Input Common·Mode
Voltage Range, VICR

V+ = 30 V, Note 2

0

-

V+-2

V

RL = 00 On All Ampl.

-

0.7

1.2

RL=oo, V+= 30V

-

1.5

3

Supply Current, 1+

mA

NOTE 1: Due to the p-n-p input stage the direction of the input current is out of the IC. No loading change exists
on the input lines because this current is essentially constant, independent of the state of the output.
NOTE 2: The input signal voltages and the input common-mode voltage should not be allowed to go negative by
more than 0.3 V. The positive limit of the common-mode voltage range is V+ -1.5 V, but either or both
inputs can go the + 32 V without damage.
NOTE 3: Va = 1.4 VOC, As = 0 n with V+ from 5 V to 30
and over the full input common-mode voltage range

V,

(0 V to V+ - 1.5 V).

NOTE 4: The maximum output current is approximately 40 mA independent of the magnitude of V... Continuous
short circuits at V+ 15 V can cause excessive power dissipation and eventual destruction. Short circuits
from the output to V+ can cause overheating and eventual destruction of thedevice. Destructive dissipation can result from simultaneous short circuits on both amplifiers.

>

______________________________________________________________________ 39

CA158, CA158A, CA258, CA258A, CA358, CA358A, CA2904 Types
ELECTRICAL CHARACTERISTICS (Values Apply for Each Operational Amplifier)

LIMITS
CA368 (G, T, S)

TEST CONDITIONS
CHARACTERISTIC
Supply Voltage (V+) = 5 V
Unless Otherwise Specified

Min.

Typ.

UNITS

Max.

TA=250 C
Input Offset Voltage, VIO

Note 3

-

2

7

mV

Output Voltage Swing, VOpp

RL = 2 kn.

0

-

V+ -1.5

V

Input Common·Mode
Voltage Ranae, VICR

Note 2, V+ = 30 V

0

-

V+ -1.5

V

Input Offset Current, 110

11+-11

50

nA

11+ or II ' Note 1

-

5

Input Bias Current, liB

45

250

nA

20

40

-

mA

10

20

-

mA

12

50

-

!lA

Output Current (Source). 10

VI+=+1 V, VI -=0 V,
V+ = 15 V
VI+=OV, VI-= 1 V, V+=15 V

Output Current (Sink). 10

VI+=O V, VI-= 1 V,
Vo=200mV

Short Circuit Output Current

R L = 0 (to Ground) Note 4

-

40

60

mA

Large Signal Voltage Gain, AOL

R L ;;. 2 kn., V+: 15 V
(For large Vo swing)

25

100

-

V/mV

Common·Mode Rejection
Ratio, CMRR

DC

65

70

-

dB

Power' Supply Rejection
Ratio, PSRR

DC

65

100

-

dB

Ampl ifier·to·Ampl ifier
Coupling

f = 1 to 20 kHz (Input referred)

-

-120

-

dB

Input Offset Voltage, VIO

Note 3

-

-

9

mV

Temperature Coefficient of
Input Offset Voltage,o:VIO

Rs = 0

-

7

-

!lV/oC

Input Offset Current, 110

11+ -11-

-

-

150

nA

-

pA/oC

11+ or 11-

-

10

Input Bias Current, liB

40

500

nA

Input Common·Mode
Voltage Range, VICR

V+ = 30 V, Note 2

0

-

V+-2

V

R L = ~ On All Amp!.

-

0.7

1.2

RL =~, V+ = 30 V

-

1.5

3

TA = 0 to +700 C

Temperature Coefficient of
Input Offset Current, 0:110

Supply Current, 1+

mA

NOTE 1: Due to the p-n-p input stage the direction of the input current is out of the IC. No loading change exists
on thp input lines because this current is essentially constant, independent of the state of the output,
NOTE 2: The input signal voltages and the input common-mode voltage should not be allowed to go negative by
more than 0.3 V. -The positive limit of the common-mode voltage range is V+ - 1.5 V, but either or both
inputs can go the + 32 V without damage.
NOTE 3: VO;;' 1.4 VDC. Rs =: 0 n with V+ from 5 V to 30 V, and over the full input common-mode voltage range
(0 Vto V+ -1.5 VI.
NOTE 4: The maximum output current is approximately 40 rnA independent of the magnitude of Vi-. Continuous
short circuits at V+
15 V can cause excessive power dissipation and eventual destruction. Short circuits
from the output to V+ can cause overheating and eventual destruction of thedevice. Destructive dissipation can result from simultaneous short circuits on both amplifiers.

>

40 ____

~

________________________________________________________________

CA158, CA158A, CA258, CA258A, CA358, CA358A, CA2904 Types
ELECTRICAL CHARACTERISTICS (Values Apply for Each Operational Amplifier)

LIMITS
CA2904G

TEST CONDITIONS
CHARACTERISTIC
Supply Voltage (V+) ~ 5 V
Unle•• Otherwise Specified

Min. Typ.

UNITS

Mme.

TA ~ 25°C
Input Offset Voltage, Via

Note 3

-

2

7

mV

Output Voltage Swing, VOpp

RL~

0

-

V+ -1.5

V

Input Common·Mode
Voltage Range, VICR

Note 2, V+ = 30 V

0

-

V+ -1.5

V

10 k!1

Input Offset Current, 110

11+-11

-

5

50

nA

Input Bias Current, liB

11+ or II ,Note 1

-

45

250

nA

Output Current (Source},lo

V,+=+1 V, VI
V+= 15 V

20

40

-

rnA

Output Current (Sink), 10

VI+=O V, VI-= 1 V, V+=15 V

10

20

-

rnA

Short Circuit Output Current

RL = 0 (to Ground) Note 4

-

40

60

mA

-

100

-

V/mV

Large Signal Voltage Gain, AOL

=OV,

RL~ 2 k!1, V+= 15 V

(For large Va swing)

Common-Mode Rejection
Ratio, CMRR

DC

50

70

-

dB

Power· Supply Rejection
Ratio, PSRR

DC

50

100

-

dB

Amplifier-to-Amplifier
Coupling

f = 1 to 20 kHz (Input referred)

-

-120

-

dB

Input Offset Voltage, VIO

Note 3

-

-

10

mV

Temperature Coefficient of
Input Offset Voltage,o:VIO

Rs = 0

-

7

-

jJV/oC

Input Offset Current, 110

11+-11-

-

45

200

nA
pAloC

TA = -40 to + 85°C

Temperature Coefficient of
Input Offset Current, 0:110

-

10

-

Input Bias Current, liB

II+or II

-

40

500

nA

Input Common·Mode
Voltage Range, VICR

V+ = 30 V, Note 2

0

-

V+-2

V

RL = co On All Ampl.

-

0.7

1.2

RL = co, V+= 30V

-

1.5

3

Supply Current, 1+

mA

NOTE 1: Due to the p-n-p input stage the direction of the input current is out of the IC. No loading change exists

on the input lines because this current is essentially constant, independent of the state of the output.
NOTE 2: The input signal voltages and the input common-mode voltage should not be allowed to go negative bV
more than 0.3 V. The positive limit of the common-mode voltage range is V+ - 1.5 V, but either or both

inputs can go the + 32 V without damage.
NOTE 3< Vo = 1.4 VOC, R, = 0 n with V+ from 5 V to 30 V, and over the full input common·mode voltage range
10 V to V+ - 1.5 V).
NOTE 4: The maximum output current is approximately 40 rnA independent of the magnitude of V+. Continuous

>-

short circuits at V+ 15 V can cause excessive power dissipation and eventual destruction. Short circuits
from the output to V+ can cause overheating and eventual destruction of the device. Destructive dissipation can result from simultaneous short circuits on both amplifiers.

_____________________________________________________________________ 41

CA555, CA555C Types·

Timers

CA555G, CA555CG:

For Timing Delays & Oscillator Applications in
Commercial, Industrial, and Military Equipment

CA555T, CA655CT:

The RCA·CA666 and CA666C are highly
stable timers for use in precision timing and
oscillator applications.
As timers, these
monolithic integrated circuits are capable of
producing accurate time !;Ielays for periods
ranging from microseconds through hours.
These devices are also useful for astable ascii·
lator operation and can maintain an accurate·
Iy controlled free·running frequency and
duty cycle with only two external resistors
and one capacitor.
The circuits of the CA666 and CA666C may
be triggered by the falling edge of the wave·
form signal, and the output of these circuits
can source or sink up to a 200·milliampere
current or drive TTL circuits.

Hermetic Gold·CHIP a·Lead Dual·ln·Line
Plastic Package (MINI·DIP)
Standard a·Lead TO·5 Style Package

The CA555 and CA665C are supplied in
hermetic IC Gold-<:HIP a·lead dual·in·line
plastic packages (G Suffix), standard a·lead
TO·5 style packages (T suffix), a·lead TO·5
style packages with dual·in·line formed leads
(DIL-cAN, S suffix), a·lead dual·in·line plas·
tic packages (MINI·DIP, E suffix), and in
chip form (H suffix). These types are direct
replacements for industry types in packages
with similar terminal arrangements e.g.SE555
and NE555, MC1655 and MC1456, respec·
tively. The CA555 type circuits are intended
for applications requiring premium electrical
performance. The CA655C type circuits are
intended for applications requiring less strin·
gent electrical characteristics.

MAXIMUM RATINGS, Ab.oluts·Muimum V./UBS:
DCSUPPLYVOLTAGE . . ,
18
V
DEVICE DISSIPATION:
UptoTA " 55°C . . . . . SOO
mW
Above TA • 55 0 C Derate linearly
5 mW!"C
AMBIENT TEMPERATURE RANGE (All Typesl:
Operating
CA555
. • -55 to +125 °c
CA555C
.
0 to 70°C
Storage
. . -S5 to +1 ~O °c
LEAD TEMPERATURE lOuring Solderlngl:
At distance IllS":!: 1/32"
11.59 ±O.79 mm) from cas.
for 10 seconds max.
. +265

v'

I",.,,,

I
I
I

I
I
THRESI'IOI..O

I
I
I

830

..·n.

CA556E, CA555CE:
a·Lead Dual·1 n·Line Plastic Package
(MINI·DIP)

Features:
•
•
•
•
•
•
•
•

Accurate timing from microseconds
through hours
Astable and monostable operation
Adjustable duty cycle
Output capable of sourcing or sinking
up to 200mA
Output capable of driving TTL devices
Normally ON arid OFF outputs
High·temperature stability -O.OO6%fOC
Directly interchangeable with SE555,
NE555, MC1555, and MC1455

Applications:

Fig. 7 - Functional diagram of the CA555

series.

j - J:i:~---T---:OM"i~~~ ---T----;:,~F:-Of>--- - -,- I

CA555S, CA655CS:
Standard a·Lead TO·5 Style Package
With Formed Leads (DIL·CAN)

•
•
•
•
•
•

Precision timing
Sequential timing
Time·delay generation
Pulse generation
Pulse·width and position modulation
Pulse detactor

~T-;u;l

I

I
6.Bk

I

I

::::::E]'
,
: :,:CHARGE

I
I
I

OUTPUT

I

)

RESET ..

,

. '

THRESHOLD

~~U:8f

roPY,EW

a. MINI·DIP plastic package
TO-6 Itvle packag. with formed Ie...,
CONTROL
VOL.TAG!

•

TRIGGER

RESET
DISCHARGE

I

o·r-~---r--~~,oYo----------------------------~

~_ _ _ _ ~S~~G.!..J

RESISTANCE VALUES ARE IN OHMS

Fig. 2 - Schematic diagram of the CA555 and CA555C.

RESET

TOP IIIEW

b. TO-6 styla package

Fig. 3 - Terminal assignment diagrams.

42 _____________________________________________________________________

CA555, CA555C Types
ELECTRICAL CHARACTERISTICS, At TA = 2f1JC,

vf = 5 to

15 V unless otherwise specified
"0

LIMITS
CHARACTERISTIC TEST CONDITIONS
Min.
DC Supply Voltage,
V+
DC Supply Current
(Low State) *, 1+

V+ = 5 V,
RL = 00
V+=15V,
RL =00

CA555
CA555C
UNITS
Typ. Max. Min.
Typ. Max.

4.5

-

18

4.5

-

16

V

-

3

5

-

3

6

rnA
MINI~~M

-

10

12

-

10

15

rnA

-

(2/3)V+

-

(2/3)V+

1.67
5

1.9
5.2

-

V

1.45
4.8

-

Trigger Current
Threshold Current.,
ITH

-

0.5

-

-

-

0.1

0.25

Reset Voltage
Reset Current

0.4

1.0

-

0.7
0.1

-

-

V+=5V
V+ = 15 V

2.9
9.6

3.33
10

3.8
10.4

V+= 5V
ISINK = 5 rnA

-

-

Threshold Voltage,
VTH
Trigger Voltage

Control Voltage
Level

Output Voltage
Drop:
Low State, VOL

V+= 5V
V+ = 15 V

0.5

IIA

-

0.1

0.25

IIA

0.4

1.0

-

V
rnA

2.6
9

0.7
0.1
3.33
10

4
11

V
V

-

-

0.25

0.35

0.1

0.25

-

-

-

-

0.1

0.15

-

0.1

0.25

-

0.4

0.5

0:75

2.0

2.2

-

0.4

ISINK= 100 rnA

2.0

2.5

ISINK = 200 rnA

-

2.5

-

-

2.5

-

3.0

3.3

-

2.75

3.3

-

ISINK = 8 rnA
V+ = 15 V
ISINK = lOrnA
ISINK = 50 rnA

ISOURCE = 100 rnA

-

Timing Error
(Monostable) :
Initial Accuracy
Frequency
Drift with
Temperature
Drift with Supply
Voltage
Output Rise Time, tr
Output Fall Time, tf

RI, R2
= I to lookn
C=O.l J.lF
Tested at
V+ = 5 V,
V+ = 15 V

-

0.5

2

12.75

-

13.3
12.5

-

I

V

-

-

%
p/m/
°C

-

0:1

-

%/V

100

-

ns

100

-

ns

-

100

-

J+~

l

5!1.c

-r~~

.25-C

~

j.---

0.8

0.'

. J, I'

SIUPPLY VOLTAGE

0

,

•

I

~vtl'5V~ Voj..: 15V

"-,,
,
, .

I

SOURCE CURRENT (:I:SOURCEI- rnA

-

-

1,Tll ..

TEMJERALAE

~

i

50

0.2

~

~

-

100

AMBI~NT

.. 6

~

100

0.05

:

~

~

30

-

r

; ,.,

-

Fig. 4 - Minimum pulse width vs. minimum
trigger voltage.

Fig. 5 - Supply current v•••upply voltage.

V
13.3
12.5

0.4

"'WHERE. IS THE DECIMAL MU ...TIPL.IER OF THE SUPPLTVOLTAGE

V

V+ = 15 V
ISOURCE = 100mA 13.0
ISOURCE = 200 rnA

~lULSEl VOLT2G~ !lvtl *

V

-

V+ =5V
High State, VOH

1.67
5

tmlllH

TRIGGER

Fig. 6 - Output voltage drop (high .tatel v•.
source current.

• When the output is in a high state, the dc supply current is typically 1 mA less than the
low·state value.
• The threshold current will determine the sum of the values of R 1 and R2 to be used in
Fig. 16 (astable operation): the maximum total Rl + R2 = 20 Mn.

-

....-

-

r--

--:-

------t--j",---t-1

'0

-J-.

SINK CURRENT IISINK1-mA

Fig. 7 - Output I/Oitage-Iow state VI. sink current

at 11'"=5 V.

___________________________________________________________________ 43

CA555, CA555C Types
10:

SUPPLY VOLTAGE (v+)' 10 V

000

I

SINK CURRENT (15INIII-",A

51NII CURRE'-IT C1SINK)-mA

Fig.8 - Output voltage-low state vs. sink
current at v+ = 10 V.

Fig.9 - Output voltage-low state
at II' = 75 V.

."
~

5

1005

SUPPLY 'JOLTAGE {Vtl-V

sink current

Fig. to - Delay time vs. supply voltage.
v+

,

."

VS.

1-1:

:lIJ1i !

It

',11 ji!i

'00
250

T;~

""~.

200
AMBIENT

1E"~

ER","\lI\E~.c:.

"0

!iii

5V

.,

6IlOn

!

11.

>--Q)--+----~--~.-

{1}~:F·!C

'00

.,

I
I

RELAY
COIL

I

IOkfi

+12s"C

.L

T
I

I
I

680n

0.985

-'1'5

-!XI

-25

25

50

75

* WHERE.

AMBIENT TEMPERATURE ITA1-"C

Fig.lt - Delay time vs. temperature.
:5 V SWITCH 51·0PEN·
INPUT (TERMINAL 21
VOLTAGE
0-- S.!I!.C!:!. !!!. :£.LO-.!i~':"

U

5Y--------

IS THE DECIMAL MULTIPLIER OF THE SUPPLY VOLTAGE

Fig. 12 - Propagation delay time vs. trigger voltage.

Fig. 13 - Reset timer (monostable opsration}.

v+

..
2

~

CAP~ll~OR - - - - - - - - ./'1
VOLTAG~ (TERMINALS 6,7)"
/ .I
..~==~~~

SI
START

10~--~----~---+.~--t7~-+'~--4

,

!.

2

i;

I

,v

.,

r--+---.
.2

--1
I

10-1

I

I
I

OUTPUT

I

VOLTAGE
(TERMINAL 3)

I

T

10
TIME OELAY Ito)-S

Fig. 74 - Typical waveforms for reset timer.

TYPICAL APPLICATIONS
Reset Timer (Monostable Operation)
Fig.13 shows the CA555 connected as a reset
timer. I n this mode of operation capacitor
CT is initially held discharged by a transistor
on the integrated circuit. Upon closing the
"start" switch, or applying a negative trigger
pulse to terminal 2, the integral timer flip·
flop is "set" and releases the short circuit
across CT which drives the output voltage
"high" (relay energized). The action allows
the voltage across the capacitor to increase
exponentially with the time constant t =
RICT. When the voltage across the capacitor
equals 2/3 V+, the comparator resets the
flip·flop which in turn discharges the capaci·
tor rapidly and drives the output to its
low state.

Fig. 15 - Time delay

YS.

resistance and capacitance.

Fig.'6 - Repeat cycle timer (astable operation).

Since the charge rate and threshold level of
the comparator are both directly propor·
tional to V+, the timing interval is relatively
independent of supply voltage variations.
Typically, the timing varies only 0.05% for
a 1 volt change in V+.

Repeat Cycle Timer (Astable Operation)
Fig.16 shows the CA555 connected as a
repeat cycle timer. I n this mode of oper·
ation, the total period is a function of both
Rl and R2;

Applying a negative pulse simultaneously to
the reset terminal (4) and the trigger terminal
(2) during,the timing cycle dischargesCT and
causes the timing cycle to restart. Momen·
tarily closing only the reset switch during the
timing interval discharges CT, but the timing
cycle does not restart.

where tl = 0.693(R 1 + R2) CT
and t2=0.693(R2)CT
The duty cycle is:
t2
R2
tl+ t 2=Rl+ 2R 2

Fig.1"4 shows the typical waveforms gener·
ated during this mode of operation, and
Fig.15 gives the family of time delay curves
with variations in R 1 and CT.

T =0.693(RI + 2R2)CT =tl + t2

Typical waveforms generated during
mode of operation are shown in Fig.
Fig. 18 gives the family of curves of
running frequency with variations in
value of (Rl + 2R2) and CT.

this
17.
free
the

44 ________________________________________________________________________

CA555, CA555C Types

.v

~

u

o
3.3V

'.7 v

I, .!lI

I
I

I
I

I
I

I
I

-'

-'

I-'

I
I
.....
~

-

B

\

_ •.:JI

\

\

1\

\

\

~

u

z

;!

~
~

2

OD~~---t----~~-f~--~---f~--1

Top Trace: Output voltage 12V/div. and
0.5 ms/div.)
Bottom Trace: Capacitor voltage (1 VI
div. and 0.5 ms/div.)
Fig. 17 - Typical waveforms for repeat
cycle timer.

,
2

0.00

124682
10- 1
I

Fig. IS - Free funning frequency ofrepeatcyc/e timer
with variation in capacitance and refinance.

_____________________________________________________________________ 45

CA723 Types
Features:

Voltage Regulators

• Up to 150 mA output current
• Positive and negative voltage regulation
• Regulation in excess of 10A with suitable
pass transistors

For Regulated Output Voltages Adjustable from
2 V to 37 V at Output Currents up to 150 rnA
Without External Pass Transistors
RCA-CA723 and CA723C are silicon monolithic integrated circuits designed for service
as voltage regulators at output voltages
ranging from 2 to 37 volts at currents up to
150 milliamperes.
Each type includes 11 temperature-compensated reference amplifier, an error amplifier,
a power series pass transistor, and a currentlimiting circuit. They also provide independently accessible inputs for adjustable
current limiting and remote shutdown and,
in addition, feature low standby current
drain, low temperature drift, and high ripple
rejection.
The CA723 and CA723C may be used with
positive and negative power supplies in a

wide variety of series, shunt, switching, and
floating regulator applications_ They can
provide regulation at load currents greater
than 150 milliamperes and in excess of
10 amperes with the use of su itable n-p-n
or p-n-p external pass transistors.
The CA 723 and CA 723C are supplied in the
1O-Iead TO-5-style ceramic package (T suffix),
and the 14-lead dual-in-line plastic package
(E suffix). and are direct replacements for
industry types 723, 723C, JlA723, and
JlA723C in packages with similar terminal
arrangements. They are also available in
chip form ("H" suffix).

• Input and output short-circuit protection
• Load and line regulation: 0.03%
• Direct replacement for 723 and 723C
industry types
• Adjustable output voltage: 2 to 37 V

Applications:
•
•
•
•
•

Series and shunt voltage regulator
Floating regulator
SWitching voltage regulator
High-current voltage regulator
Temperature controller

All types are rated for operation over the
full military-temperature range of -55°C
to +125°C.

MAXIMUM RATINGS,Absolute-Maximum Values:
DC SUPPLY VOLTAGE
(Between V+ and V- Terminals)
PULSE VOLTAGE FOR 50-ms
PULSE WIDTH
IBetween v+ and V- Terminals)
DIFFERENTIAL INPUT-OUTPUT
VOLTAGE
DIFFERENTIAL INPUT
VOLTAGE:
Between Inverting and NonInverting Inputs ...........
Between Non·lnverting

.................

Input and V-

.. . . .. . . .. . .

CURRENT FROM ZENER DIODE
TERMINAL (VZ)
CURRENT FROM VOLTAGE
REFERENCE TERMINAL
(VREF) ................ _ ...

............

40

V

50

V

40

V

is

V

8

V

25

mA

15

mA

DEVICE DISSIPATION:
Up to T A = 25°C CA723T, CA723CT .••... _ •. 800
mW
CA723E, CA~23CE .••.. __ .. 1000
mW
AboveTA=25 cCA723T, CA723CT
Derate linearly ........... . 6.3
CA723E, CA723CE
Derate linearly ...•....... 8.3 mW/C
AMBIENT TEMPERATURE
RANGE (All Types):
Operating ............... -55 to +125
Storage ........... _.. _. -65 to +150
LEAD TEMPERATURE

Fig. 1 - Functional diagram of the CA723 and CA723C.

(During Soldering):

At a distance 1/16" ± 1/32"
(1.59 ± 0.79 mml from case for

10 seconds max.

+265

°c

"
Fig. 2 - Terminal arrangement of the CA723T and
CA723CT in the TO-5 style package.

NotHNVEFlTlNG
INPUT

'r

INVEFHING
INPUT

Fig. 4 - Equivalent schematic diagram of the CA723 and CA723C.

Fig. 3 - Terminal arrangement of the CA723E and
CA723CE in the dua/~in·line plastic package.

46 ______________________________________________________________

CA723 Types
v+ -

TYPICAL CHARACTERISTICS
CURVES FOR TYPE CA723

ELECTRICAL CHARACTERISTICS at TA - 25 C,
Vc - VI -12 V, V- - 0, Vo - 5 V,
IL - 1 mA, C1 - 100 pF, CREF - 0, RSCp - 0, unl,. otherwl...peclfled. Divider
Impedence R1R2 R1+R2 at non-Inverting Input, Term. &, - 10 kn (_ Fig. 23).

hlAX. JUNCTION TEMP ITJ '-!SO·C
THERMAL RESISTANCE "150·C/W

LIMITS
CHARACTERISTIC
Quiescent Regulator
Current. 10

TEST
CONDITIONS
IL = 0,
VI = 30 V

Input Voltage
Range, VI
Output Voltage I
Range. Vo

CA723
Min. Typ.

CA723C
Max.

Min. Typ.

-

2.3

3.5

-

9.5

-

40

9.5

2

-

37

2

"0

UNITS
Max.

2.3

QUIESCENT DISSIPATION (Pg 1060 mW
INO HEAT SINKJ

"

4

mA

-

40

V

-

37

V

OIl(

..
~
,

.0

~

0

Dillerential Input·
Output Voltage,

0

20

'0

'"

40

DI1'EA[NTIAL INPUT-OUTPUT VOLTAG[ I'll-Va I-V

3

VI-VO

-

38

3

-

38

V

FIg. 5 - Max. load current

Relerence Voltage,

output volta/Jtl.

VREF

6.95

7.15

7.35

6.8

7.15

7.5

-

0.02

0.2

-

0.1

0.5

-

0.01

0.1

-

0.01

0.1

.s

differential input·

V

=

VI 12
10'40 V

=

VI 12
to 15 V

Line Regulation
(See Note I)

VI = 12
to 15 V,
TA -55 to
+125°C

%VO

=

-

-

0.3

-

-

-

VI 12
to 15 V,
TA = 0 to
70°C

-

-

-

-

-

0.3

IL = 1
to 50 mA

-

IL - 1
to 50 mA,
TA = -55 to
+125°C

-

IL = 1
to 50 mAo
TA = 0
to 70°C

-

TA = -55
to +125°C

-

TA = 0
to 70°C

-

-

-

-

0.003

1= 50 Hz
to 10 kHz

-

74

-

-

74

=

Load Regulation
(See Note 1)

Output· Voltage
Temp. Coefficient,
AVO

Ripple Rejection
(See Nat~ 2)

0.15

-

-

0.6

-

-

-

-

-

-

-

0.6

-

-

-

0.03

0.002

0.Q15

0.03

0.2

OUTPUT CURRENT 11 0 1-111.

dB

-

65

-

-

65

-

Equivalent Noise RMS CREF = 0
Output Voltage, VN
BW = 100 Hz
(See Note 2)
10 kHz.

-

20

-

-

20

-

CREF = 5 J.LF

-

2.5

-

-

2.5

-

= n.

-

86

Fig. 7 - Load regulation with current limiting.

-

-

RSCp 10
Vo = 0

%VO

-

B6

ILIM

Fig. 6 - Load regulation without current limiting.

0.Q15

-

=51'F

I"I o l-IIIA

%fc

1=50 Hzto
10 kHz,
CREF

Short-Circuit
Limiting Current,

OUTPUT CURRENT

mA

BW 100 Hz
to 10 kHz.
J.LV

Note 1: Une and load regulation specifications are given for condition of a constant chip

temperature. For high·dissipation conditions, temperature drifts must be sepaNote 2: For eREF. see Fig. 23.
rately taken into account.

OUTPUT CURRENT Il o l-IIIA

Fig. 8 - Load regulation with current limiting.

_____________________________________________________________________ 47

CA723 Types
MAli.· JUNCTION TEMP ITJ I-"O·C

OUTIJUT VOLTAGE I '10 ,-"EFERENCE
VOLTAGE IV,'!p)

t

LOAD CURRENT IILI.O

THERMAL RESISTANCE ",5O"C/W
QUIESCENT DISSIPATION I'O*IIIW
TO-!!! STY!.E PACKAGE WITH NO
HEAT SINK

150

1

...... \t.MT TEMPERATURE IT",· ..

"'"<:

2S"C

125·C

10

..

40

..

IN,." VOL'AGE lVII-V

OUTPUT CURRENT IXO'-mA

lO

'0

40

DIFFERENTIAL INPUT-OUTPUT VOLTAGE IVr'lo I-V

tlCS-14IU

S2CS-24166

FIg. 70 - Oui__nt current VB. Input voll1lga

FIg. 9 - Current limiting chllracteri.tiCl.

. ...
~

Fig. 7 7 - Max. load current v. diffenmtial input·
output voll1l/lB CA723CT.

TYPICAL CHARACTERISTICS CURVES FOR TYPE CA723C
IIIQ. JUNCTION TEMP. (TJ 1"125·C

THERMAL RESIST"""-'Z5"C/.

QUIESCENT DISSIPATION IPO)llOm•

DUAl-IN-LiNE PLASTIC PACKAGe:
WITH NO HUT l"ftC

i
~

10

20

40

50

DIFFERENTIAL INPUT·OUTPUT VOLTAGE (y,..yOI-V
NCS·,4ISf

Fig. 72 - M~. losd current vs differential inputoutput voIl1Il1B for CA723CE.

OUTPUT CuRRENT IIOI-IIIA

OUTPUT CURRENT IIOI-IIIA

'US-;!41&1

FIg. 73 - Loed regulation without current limiting.

OUTPUT CURRENT 110 1-11'11.

Fig. 74 - LDBd regulation with current limiting.

DIFFERENTIAL INPUT-OUTPUT IIOLTAGE IV1-VO I-II

FIg. 75 - Current llmitlnll c"._lnICl.

FIg. 76 - Oul__nt current VB. Input vo/lllga
FIg. 77 - Losd regulation
output voltaf/B.

VB.

differential Input-

TYPICAL CHARACTERISTICS CURVES FOR TYPES CA723 AND CA723C

. DI"UENTIAL INPUT-OUTPUT VOLTAGE tYrVo I-V

TIM! tU-pl

t2CI·,41'rJ

FIg. 78 - Line rtlgullltion
output voItllga

VB.

differential Input-

FIg. 79 - Line treml.nt rtI'ponSB.

JUNCTION TEMPERATURE ITJ I-·C

12e!-2417~

Fig. 20 - Current limiting characteristic• ...
junction tamperature.

@------------------------------------------~--------------------

CA723 Types
'0,

0.01

,

tOO 2

.. , 'Ik

TIME 111-,..

I •

" 6 a'Xlk 1

1!

..

6 aiM

9~CS-24117

FREOUENCY ttl-HI

Fig. 27 - Load transient response.

Fig. 22 - Output impedance VI. frequency.

TYPICAL APPLICATION CIRCUITS
Vo

'SOP

f,C~U'~'~EN~T-o""''''''·R6~¥~OtED

"

CA123
CA1nc

l.IM.

,.V

tNV .

• 0.

INPUT

R2

INPUT

CIRCUIT PERFORMANCE DATA:

CIRCUIT PERFORMANCE DATA:

REGULATED OUTPUT VOLTAGE • , . 6 v
LlNEREGULAT10N(6V,-3YI. , . . 0.5 mY

REGULATED OUTPUT VOLTAGE • • • 15 V
LINE REGULATION (t.V,- 3 VI , • • • 1.5 rrlV

LOAD REGULATION IA'L. 50 mAl. , • U

LOAD REGULATION 1t>.IL-SOmAI

NIJtiI: RI.

:!.::

mY

for 1II1nI_ ........11... *ift

Fig. 23 - Lo_oltage regulstor circuit IV0 = 2
to 7volnl.

Notl: R3.

CIRCUIT PERFORMANCE DATA:
REGULATED OUTPUT VOLTAGE
.• -15 V
LINE REGULATION !.aVI-3VI ••••
LOAD REGULATION !AIL - 100 mAl ••
2 m\/
Not.: Fill' lPPIictollDns_ploying INTO·S.tyle..-:k1ll
........ VZilfequi..... .., .......16.2·voIl

.4.5 mY

:~+:~ for minimulll ....,pIr.lure drift

R31TWft.llinllnltldfwmlnlmumcompo,*",count.

921:5-24119

Fig. 24 - High·voltage regulator circuit IV0 = 7
to 37 voltsl.

_diodethOl.lId be canMCtllll in urift with

VOrr.."inII8I.

Fig. 25 - Negative·voltage regulator circuit

V<

CURRENT
LIM.

,.

56kn

'2

CIRCUIT 'ERFORMANCE OATA:
REGULATEDOU'flIUTVOLTAQI ••• '1 Y
LINE RlGULATIONI.6.V.-IVI • • • • 1.1 mY
LOAD REGULATION I6IL. 'AI. . . • '1 mY

'ICS-.!!.'' ' I

Fig. 26 - Po.itive-voltage-regulator circuit (with
""tarnal ".~n "... transi.torl.

CIRCUIT PERfORMANCE DATA:
REGULATEDOUTPUTVOLTAOE ••• Ii v
LINEREGULATION!AV,_3VI • • • • 0.5 mV
LOAD REGULATION (.aIL - 1 AI. • •• Ii mV

Fig. 27 - Positive voltage-ragulator circuit (with
externsl p-n·p pass transistor).

CIRCUIT PIRFORMANCE DATA:
REGULATEOOUTPUTYOLTAGE • •• II V
LINI REGULATION !AVI- 3VI • • • • 0.& mV
LOADRIGULATIONCb,IL-10mAl. •• 1 mY
SHORT.(:IRCUIT CURRENT • • • • • • 20 mA

Fig. 28 - Foldback current-limiting circuit.

CIRCUIT PERfORMANCE DATA:
REGULATEOOUTPUTVOLTAOE ••• 60 V
LINE REGULATION IlIVI" 20 VI ••• l' mV
LOAD REGULATION (AIL-60mAI ••• 20 mV

Fig. 29 - Positive-floating regulator circuit

______________________________________________________________________ 49

CA741, CA747, CA748, CA1458, CA1558 Types
"G" Suffix Types-Hermetic Gold-CHIP in
Dual-In-Line Plastic Package
"E" Suffix Types-Standard Dual-In-Line
Plastic Package
"T" a'nd "S" Suffix Types-TO-5 Style Package

Operational Amplifiers
High-Gain Single and Dual Operational Amplifiers
For Military, Industrial and Commercial Applications
The RCA-CA1458, CA1558 (dual types);
CA741 C, CA741 (single-types); CA747C,
CA747 (dual types); and CA748C, CA748
(single types) are general-purpose, high-gain
operational amplifiers for use in military,
industrial, and commercial applications.
These monolithic silicon integrated·circuit
devices provide output short-circuit protection and latch-free operation. These types
also feature wide common-mode and differential-mode signal ranges and have low-offset
voltage nulling capability when used with an
appropriately valued potentiometer. A 5megohm potentiometer is used for offset
nulling types CA748C, CA748 (See Fig. 10);
a 10-kilohm potentiometer is used for offset
nulling types CA741 C, CA741, CA747CE,
CA747CG, CA747E, CA747G (See Fig. 9);
and types CA1458, CA1558, CA747CT,
have no specific terminals for offset nUlling.
Each type consists of a differential-input
amplifier that effectively drives a gain and
level-shifting stage having a complementary
emitter-follower output.

This operational amplifier line also offers the
circuit designer the option of operation with
internal or external phase compensation.

Types CA748C and CA748, which are externally phase compensated (terminals 1
and 8) permit a choice of operation for
improved bandwidth and slew-rate capabilities. Unity gain with external phase
compensation can be obtained with a single
30-pF capacitor. All the other types are
internally phase-compensated.

RCA's manufacturing process makes it possible to produce IC operational amplifiers with
low-burst ("popcorn") noise characteristics,
Type CA6741, a low-noise version of the
CA741, gives limit specifications for burst
noise in the data bulletin, File No, 530.
Contact your RCA Sales Representative for
information pertinent to other operational
amplifier types that meet low-burst noise
specifications.

Features:
• Input bias current (all types): 500 nA max.
.Input offset current (all types): 200 nA max.

Applications:
•
•
•
•
•
•

Comparator
DC amplifier
Integrator or differentia tor
Multivibrator
Narrow-band or band-pass filter
Summing amplifier

la.-CA741CS,CA747CT,CA747S, &

CA741 T with internal phase
compensation.

MAXIMUM RATINGS, Absolute-Maximum Values at TA =2~C:
DC Supply Voltage (between V+ and V- terminals):

CA741C, CA747C·, CA748C, CA145S".
CA741, CA747", CA74S, CA155S"
Differential Input Voltage.
DC Input Voltage* .
Output Short·Circuit Duration.
Device Dissipation:
Up to 70°C ICA741C, CA74SC)
Up to 75°C ICA741, CA74S)
Up to 30°C ICA 747)
Up to 25°C ICA747C)
Up to 30°C ICA 1558)
Up to 25°C ICA145S)
For Temperatures Indicated Above
Voltage between Offset Null and V- ICA741C, CA741 , CA747CE, CA747CG).

Ambient Temperature Range:
Operating - CA741, CA747E, CA74S, CA155S.

CA741C, CA747C, CA74SC, CA1458.
Storage

Lead Temperature (During Soldering):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mml from case for 10 seconds max.
III

36V

44V
±30V

±15 V
Indefinite

500mW
500mW
SOOmW
SOOmW
680mW
. . . ..
680mW
Derate linearlv 6.67 mWloC

y-

7b.-CA747CT and CA747T with

internal phase compensation.

±a.5 V
TOP VIEW

-55 to +125 °c

o to +70 Oct
°c

-65 to +150
.

265°C

If Supply Voltage is less than ± 15 volts, the Absolute Maximum Input Voltage is equal to the Supply Volt·
age .

.. Voltage values apply for each of the dual operational amplifiers.

t All types in any package style can be operated over the temperature range of -55 to +12So C, although the

y-

NOTE: PIN 4 IS CONNECTED TO CASE

published limits for certain electrical specifications apply only over the temperature range of 0 to +70 0 C.

7c .. -CA748CS, CA748CT,CA748S,

and CA748T with external
phase compensation.
Fig. 7 - Functional diagrams.

50 ________________________________________________________________

CA741, CA747, CA748, CA1458, CA1558 Types
TOP VIEW

RCA
Type No.

No. of

Phase

Ampl.

Compo

Null

AOL

CA1458
CA1558
CA741C
CA741
CA747C
CA747
CA748C
CA748

dual
dual

into
into

single

int.

single

into
into

no
no
yes
yes
yes·
yes·
yes

20k
50k
20k
50k
20k

dual
dual

into

single

ext.
ext.

single

Offset Voltage

Min.

a to +70'"
-55 to +125
o to +70'"

6
5
6
5
6
5
6
5

50k
20k
50k

yes

Operating-Temperature
Range (oC)

Max. VIO
(mV)

'N'

-55 to +125
o to +70·

INPUT!BI

8'

ld.-CA 1458S,CA 1458T,CA 1558S,

-55 to +125
o to +70·

and CA 1558T and internal
phase compensation.

-55 to +125

*In the 14·lead dual-in-line plastic package only.
·AII types in any package style can be operated over the temperature range of -55 to +125 0 C,

OFFSET NULL

although the published limits for certain electrical specifications apply only over the temperature range of 0 to +70 o C.

-

7 V"

NON -INV. 3
INPUT

+

6 OUTPUT

v-

ORDERING INFORMATION

NC

1~~~T2

5 O~JCCT

4
TOP VIEW

When ordering any of these types, it is important that the appropriate suffix letter for the
package required be affixed to the type number. For example: If a CA1458 in a straight·
lead TO·5 style package is desired, order CA 1458T.

le.-CA741 CE.CA741 CG.CA741 E.

and CA741G with internal
phase compensation.

PACKAGE TYPE AND SUFFIX LETTER
TOP VIEW

TO-5
STYLE

Type No.

PLASTIC

10L OIL-CAN

GoldGold·CHIP
CHIP
PLASTIC
CHIP

8L

14L 8L

CA1458

T

S

E

G

CA1558

T

S

E

G

CA741C

T

S

E

G

CA741

T

S

E

G

8L

E

T

CA747C

H

GH

T

S

E

G

CA748

T

S

E

G

ld, lh
ld,lh

H

GH
L

la, Ie

OffSE T
NlIlLtBI

la, Ie

NOH-INV
INPUT (BI
INPUT!BI

H

GH

lb, 1f

H

GH

lc,lg

lb, 1f

G

CA748C

FIG. No.

14L

G

E

T

CA747

BEAM·
LEAD

lc, 19

OUTPUT

IB'

,.,

OffSET
NULL \91

8'

If.-CA747CE.CA747CG,CA747E.

and CA747G with internal
phase compensation.

~U~:SET
PHASE
COM.

COMP
PHASE

1~~~T2

-

7V+

NON -)NV. 3
INPUT

+

6 OUTPUT

y-

4

50t~ccT
TOP VIEW

Ig.-CA748CE.CA748CG.CA748E.

and CA748G with external
phase compensation.

1h. -CA 1458E.CA 1458G.CA 1558E,

Fig.2-Schematic diagram of operational amplifier with external phase
compensation for CA748C and CA748.

and CA 1558G with internal
phase compensation.
Fig. 1 - Functional Diagrams (Cont'd)

___________________________________________________________________ 51

CA741, CA747, CA748, CA1458, CA1558 Types
AMBIENT TEMPERATURE (TA,-25·C

"

.

'"

20

DC SUPPLY VOLTS I"'+,Y-)

Fig.4-0pen·/oop voltage gain vs. supply voltage for
all types except CA748 and CA748C.

92CM-I,433

Jf SEE FUNCTIONAL DIAGRAM FDA TERMINAL
NUMBERS OF RESPECTIVE TYPE NUMBERS

.,

Fig.3-Schematic diagram of operational amplifiers with internal phase compensation for CA741C,
CA747, and for each amplifier of the CA747C, CA747, CA 7458, and CA 7558.

"

ELECTRICAL CHARACTERISTICS
For Equipment Design

CHARACTERISTIC

TEST CONDITIONS
Supply Voltage,
V+=15V,
V-=-15V
Ambient
Temperature, TA

Typ.

Max.

-

1

5'

-55 to +125 °c

-

1

6

25°C

25°C

80

500

-

300

1500

+125°C

-

30

500

0.3

2

Mn

20

200

85

500

7

200
nA

25°C

VO=±10V

-55 to +125 °c

25,000

-

-

-55 to +125 °c

±12

±13

-

V

-

dB

50,000 200,000

Common·Mode
Rejection Ratio, CMRR

RS"; 10kn

-55to+125°C

70

90

Supply Voltage
Rejection Ratio, PSR R

RS"; 10 kn

-55 to +125 °c

-

30

RL;;>10kn

-55 to +125 °c

±12

±14

-

RL;;>2kn

-55 to +125 °c

±10

±13

-

25°C

-

1.7

2.8

-

2

3.3

+125°C

-

1.5

2.5

_55°C
+125°C

* Values apply for each section of the dual' amplifiers.

52 ______________________________

~

'"

50

85

60

100

45

75

20

DC SUPPLY VOLTSCV+.''''-'

150 p.V/V

-55°C
25°C

Device Dissipation, PD

nA

RL;;>2kn

Common·Mode Input
Voltage Range, VICR

Supply Current, I±

mV

-55°C

Input Resistance, RI

Output Voltage
Swing, VOPP

Fig.5-0pen-loop voltage gain vs. frequency for all
types except CA748 and CA748C.

-

+125°C

Open· Loop Differential
Voltage Gain, AOL

FREQUENC't'II)--th

Min.

-55°C

Input Bias Current, liB

UNITS

25°C

Input Offset Voltage, VIO RS =..; 10kn

Input Offset Current, 110

LIMITS
CA741
CA747*
CA748
CA1558*

Fig.6-Common-mode input voltage range vs. supply
voltage for all types.

i:
~

"

,.

AMBIENT TEMPERATURE ITA'·U·C
LOAD RESISTANCE IRLI :t 2. n

~

V

~ ;,0

~

i"
mA

mW
Fig.7-Peak-to-peak output voltage vs. supply voltage for all types except CA 148 and CA 148C.

___________________________________

CA741, CA747, CA748, CA1458, CA1558 Types
ELECTRICAL CHARACTERISTICS
For Equipment Design
LIMITS

CHARACTERISTIC

Input Offset Voltage,

TEST CONDITIONS
Supply Voltage,
V+~ 15 V,
Ambient
V- ~ -15 V
Temperature, T A

RS ~ « 1 0

25°C

k~

o to 70°C

VIO

25°C

Input Offset Current,
110

Oto70°C
25°C

Input Bias Current,
liB

Oto'70°C

Input Resist,nce, RI
Open-Loop Differential
Voltage Gain, AOL

RL?> 2 k~
VO=±10V

Min.

Typ.

-

2

6

-

-

7.5

-

20

200

mV

-

80

500

-

-

800

0.3

2

-

20,000

200,000

TIME-,..

nA

300

M~

-

25 °c

±12

±13

-

V

70

90

-

dB

25°C

Supply-Voltage
Rejection Ratio, PSRR

RS« 10 k~

25°C

-

30

RL?>10k~

25°C

±12

±14

Fig.8-0utput voltage vs. transient response time for
CA14TC and CAl4T.

nA

15,000

o to 70°C

RS«10k~

VOPP

Max.

-

Common-Mode
Rejection Ratio, CMRR

Output Voltage Swing,

UNITS

-

25°C

Common-Mode Input
Voltage Range, VICR

CA741C
CA747C*
CA748C
CA1458*

INVERTING
INPUT

NON-INVERTING
INPUT

92CS-19<124A2

150 /lVIV

Fig.9- Voltage-offset null circuit for CA741C. CA741,

CA141CE, CA141CG, CA147E, and CA747G.

25°C
RL?>2 k~

o to 70°C

±10

±13

±10

±13

-

V

Supply Current, I±

25°C

-

L7

2.8

mA

Device Dissipation, PD

25°C

-

50

85

mW

* Values apply for each section of

INVERTING
INPUT
OUTPUT

the dual amplifiers.

ELECTRICAL CHARACTERISTICS
Typical Values Intended Only for Design Guidance
CHARACTERISTIC

TEST
CONDITIONS
V± ~ ±15 V

TYP.
VALUES
ALL TYPES

Fig. 10- Voltage-offset null circuit for CA748C and

UNITS

Input Capacitance, CI

1.4

pF

Offset Voltage
Adjustment Range

±15

mV

Output Resistance, RO

75

~

Output Short-Circuit Current

25

mA

Transient Response:
Rise Time, tr
Overshoot

Slew Rate, SR:
Closed-loop

Unity gain
VI ~ 20 mV
RL ~ 2 k~
C L « 100 pF

RL?> 2 k~

Open-loop'"

0_3

/ls

5

%

CA748_

>-G~_r----.:VOUT

92CS-15746

0.5

Fig.11- Transient response test circuit for all types.

V//ls

40

... Open-loop slew rate applies only for types CA748C and CA748.

___________________________________________________________________ 53

CA1541D
Features

Dual-Input Memory Sen.eAmplifier
RCA-CA1541D ,a monolithic silicon integrated circuit, is a
dual-input memory sense amplifier intended for core memory
applications.
The sense amplifier, consisting of two differential input
amplifiers, a common second stage amplifier, and an output
logic gate (See Fig. 1 L converts tow-level core-memory"'"
pulses to saturated logic-level output pulses. Either one of
the input amplifiers may be gated ON with a saturated
logic signal so that an incoming "," pulse of positive or

•

Complete dual input core memory sense amplifier

•

Two available outputs: -Saturated logic output
-Linear output (positive output for
either polarity input)

The CA1541D features an external switching threshold
adjustment, plus its gate and strobe inputs are compatible

with saturated logic levels. The sense amplifier is suitable for
operation with core memories having cycle times equal to or
greater than 0.4 /J.S and is unilaterally interchangeable with
industry types 1541Land 1441.
TheCA1541D is supplied in 14-lead dual-in-line ceramic
package and is rated for operation over the full military
temperature range of -55 0 C to + 125 0 C.

negative polarity can be detected from either of two sense

• Nominal threshold voltage: 17 mV
• Adjustable threshold: 10 to 35 mV
•

Low .threshold uncertainty range: ±.3 mV

•

Fast overload recovery time: -Differential-Mode: 15 ns typo
-Common-Mode: 30 ns typ_

•

Independent channel gate and strobe terminals compatible
with saturated logic levels

• Suitable for core memories having cycle times>: 0.4 f.J. s

lines.

•

Input offset voltage: 6 mV max.

MAXIMUM RATINGS, Absolute Maximum Valu., at TA - 250C

Except for Differential Input Voltage, all voltages are measured with respect to ground (Term.8).
DC Supply Voltage:
V+ (Term. 2)
V· (Term. 7)

+10
-10
±.5
±.5
V· to

Differential Input Voltage
Common·Mode Input Voltage
"A" or "S"·Gate Input Voltage' .
Strobe Terminal Voltage . -. . . •

V
V
V
V
V+

V· to .+6V
±25mA

Output Terminal Load Current

Device Dissipation:
750mW

Up to T A = 75°C
Above T A = 75°C

. Derate Linearly 8 mW/oC

Ambient Temperature Range:
Operating
Storage

-55 to +125 °C
-65 to +150 °C

.-I NPUT SIGNAL

Lead Temperature (during soldering):
At distance not less than 1/32 inch (0.79 mm) from
case for 10 seconds max.

* Note:

Fig. 1- Functional block diagram of the CAI541D.

The "A" or "S"·Gate Input Voltage is also referred to, as the Channel·Gate Input Voltage.

T
1

CHANNEL
G
I NPUT

.'"

MPLIFIER

0 UTPUT

2:V10lV

'"

,..
"

1,7~k

smoeE INPUT

\

V

SENSE
AMPLIFIER
OUTPUT AT
OGle GATE
OUTPUT

,

'-t--'

Fig. 3 - Typical operational wave forms_

ERQ,~--t::::j:====t=:;-l-I--:-I-Ii.:
@--H--,

"A" AMPLIFI
OIFFERENTIAL
INPUT

"e"AMPUFIER 6
OIFFEFIENTIAL
INPUT

"e" INPUT
GATE

AESISTANct: VALUES ARE
IN OHMS
SUBSTRATE CONNECTEO TO
tERMINAl 7IV-)

Fig. 2 - Schematic diagram of the CA 1541 D.

Fig. 4 -Input bias (lIB) and input·offSfJt current (I/O)

test circuit.

54 ___________________________________________________________________

CA1541D
ELECTRICAL CHARACTERISTICS

v·,

5V

TEST CONDITIONS

510A

CHARACTERISTICS

SYMBOLS

5V
V .•' . V · T
VTH ADJ.
T A- • 250C
-6V i ,"'.
lunl•••
fTlrm. 131
indiCllld

CEXT - O.OIIo1F

otherwi ..1

VOH

LIMITS

MIN.

TYP.

UNITS

MAX.

Stille IDCI Ch• •..,IItICl
PaMr Dillipation

PD

Input Ofh., CU"lnt

',0

Input BI •• Currlnt:
TA-25DC
TA. -S5De

I,S

Output VolIlIIl:
High'
LowTA-2SoC
TA" 12SOC

VOH

I~O

~A

25
V5 •

V ••

V3 •

V ••

~A

50

10M" 200~A

V
350

\1,4.5 V.

mV

VOL

Ig-l0mA

'00

'S

\'/12 -0

1.5

'SR

\'/12" 5\1

Input G,i.1' Laadeurr.n,

'G

V'O"

InpulGal. Aeve, .. Currlnt:
TA-25 aC
TA·,2SoC

'GR

V,O·V" -5\1

Strobl LOld Currant

mW

ISO

Fig. 5 - Test circuit for mllJsurement of/ow (VoLI and
high (VOHI output voltagele.el£

mA

Strobe Rey'rse Currlnt:

TA-250C

~A

25

TA·12!iI.JC

V"

2.5

0

OU"PUT4.• V~
PULSE
AT TERM.' 0 . 3 ' ' 1 - - -

..

Input Tnreshold Vollage:

VTH

12

InpuIOIf." Vollage

17

20

17

22

mV

High

Low

',.

mV

V'O

InpulGe'. Voltage:

lI THRESHOLD
WAVEFORMS

~A

25

Switc:tlinllChlracl.riltiCI

TA-250C
TA--5510125 C

mA

VGH

\13

VGL

\14" V6" 0

3

AMPLIFIER
OUTPUT

A:T:;';u~

0.7

Common·Mod. Range:

!1.5

Inpula.,eHlgh

V

VeM

VDH

Input Glle Low

•

50%

PAOPAGATION
DELAY
WAVEFORMS

V-v

oV _ _ __

!1.5

Input G'te Low
Dlfferentlal-Mode Flange:
Input Gale High

'."~":~.
'IA

I .•

VS· 25 mV,

VOL

!.600

mV

!.1.S

V

'PropagahOn Delay:

25 mV (pulsedJ,

10

I.

20

30

I.

20

Input to Ampufler Output

"A

V3

Input to Output

"0

V12" 2V

Strobe to Output

'SO

V3- V4- v5- vSV 12 .. 2V (pulilldl

Gltll Input to Amphfier Output

'GA

VII • 2V (pulsldl

10

15

'G'

V3- 25mV

3D

3.

Gate (nputto Amplifier Input
Common·Mode ReCXIvery Time:
Input Gila High
Input Glle Low

tCMR

Dlfferentill·Modi
Recovery Time:
Input Glte HIgh

z

a.

15

3D

15

3D

V3· Vs ·1.SV

NOTEI:VTH.~
NOTE 2: !IIN '",'"

3D
'DR

WHEN 5, IN ","
SZIN""·

V3- VS- 400mV

WHEN SIIN .,,-

Input Glle Low

Fig. 6 - TIImhold propagation dslav, gats and input-o'fIo,
tort circuit with associatsd pulse ""'" forms.

f

DC SUPPL.Y VDL.TAGIE I'i+,vwl •• a V
AMBIENT TEMPERATURIE CTAloU·C

n

~

~'O
~

~

/L
~+-+-~/~~-1--~

a laf--I--t-/-Y'-f--t--t-+--j
~

~ '01--171'/'-+--+-+-+-+--1--;

i
"

-150

-115

0

la

aD

."

AMBIENT TEMPERATURE tTAI-"C

Fig. 7. -Input VTH.s. TA.

100

II'

THRESHOL.D ADJUST VOLTAOE[VTHIADJI].-'V
ZI AMBIENT TEMPERATURE IT I'Z'·C

I
~

20

;:

19

~

~

t--

'I

..I.

~'~'IV;::.::-ot-c-s-upt-p,-,-ll-+-I---I
~;V11r--

~"'.!lv

t-- _ _

"f-+-if---+~i=""+....!=+-I-+-I
-r--,---::P"'""t
'v
$a 1151-+-1-+--'1-+---1,.-+-;'Q

i~ '~~l:tt:ti~~t~;;:~~
14~
'.h

-3

-3.15

w4

-4.'

-a

-,.,

-IS

-I.'

THRESHOL.D ADJUST VOLTAOE [vTH IADUJ-V

Fig. lb - Input VTH.s. VTH (AOJ.~

-.,

nel-Inll

"
-4.'

-,

-,.,

NEGATIVE DC SUPPLY VOLTS tV·)

Fig. le -Input VTH lIS V-.

________________________________________________________________

~55

CA1541D
Ve.

OUTPUT (FOR INPUT
LESS THAN COMMON-

NODE INPUT R;;;";:.:G:.;"_-+"-___-I-<~~=
200ns
OUTPUT IFOR INPUT

GRE...T[ATHA~NCOMMON.

MODE INPUT RANGEl

---.L.

~IOO"''''

100
1:'0
200
INPUT PULSE WIDTH 11,.1-",

250

'00

Fig. ld - Input VTH vs. input pulse width.

'Fig. 8 - Common-mode input range test circuit with
associated pulse wave forms.

OC SUPPLY VOLTAGE (..,+ ,V-]-:to!) 1/
THRESHOLD AQJUST VOLTAGE [VTH (ADJ,)] .-!)

v

5 AMBIENT TEMPERATURE ITp,I'2S-C

t
~

4~-I---+-1-r---r--~t-t---~~

~
~

! 2~~L

__.-+-r-r__-r__

~

-30

~~t-__r-~
'-I--

-20

-10

0

10

20

INPUT VOLTAGE lelNI-mV

Fig. 9 - Differential-mode input range and recovery test circuit with

Fig. 10 - Input-output transfer characteristics.

associated pulse wave forms.

AMPLIFIER
OUTPUT

TO StOP[

r-\
L-

.utPl.1F'IER
OUTP~
(TERM.1l

Fig. II - Strobe to output test circuit with associated
pulse waw.forms.

NOTt: $2 IN "G" POSITION WHEN 5, IN £JTHER "0" POSITION
S2 IN fit/' POSITION WHEN SI IN EITHER "II" POSITION

Fig. 12 - Gate input to amplifier input (tGli tast circuit
with associated pulse wave forms.

Fig. 13 - Gate input to amplifi.,output (tGAi with
associated pulse were forms.

56 _____________________________________________________________________

CA2111 AE, CA2111 AQ
Features:

FM IF Amplifier:-Limiter and
Quadrature Detector

• Direct replacement for ULN2111A.nd MC1367
• Good sensitivity: Input limiting voltage (knee) (400
jlV IYP. at 10.7 MHz; 250 jlV typo at 4.5 MHz
.nd 5.5 MHz I

For FM I F and TV Sound I F Applications
The CA2111 A, on a single monolithic chip, provides a multistage wideband amplifier-limiter, a quadrature detector, and an
emitter-follower output stage. This device is designed for use
in FM receivers and in the sound IF sections of TV receivers.
In addition, an output terminal is pro\lided which allows the
use of the amplifier-limiter as a straight ,GO-dB wide band
amplifier.

•

Excellent AM rejection (45 dB tYp.1t 10.7 MHz)

•

Provision for output from J..stage IF amplifier section

Low harmonic distortion
• Ouadrature detection permits simplified single-coil tuning

•

•

Extremely low AFC voltage drift over full
operatlng-tempe-,atuii range

•

Minimum number of 8xternal pam required
Fig_ I-Block diIJ9rIJm of CA2" lA IJnd
JluocilJr.ti ourbDIJrd compontlnfl_

The amplifier-limiter features the excellent limiting characteristics of 3 cascaded differential amplifiers.
The quadrature detector requires only one coil in the associated outboard circuit and therefore, tuning is a simple
procedure_

MAXIMUM RATINGS, Absoluttl-MJlJCimum Vol/UtlS 

e

I

1

..

2

.1

"

INPUT SIGNAL VOL.TAGE IVjl-mv[rllllll

DYNAMIC ELECTRICAL CHARACTERISTICS .. TA - 25"C

FM Modulation Frequency· 400 Hz, Source Resistance ..

son
Fig. 2 I-AM njttction vs input ,,0It.g6 {4_5 MHz/.
TEST CONDITIONS

CHARACTERISTIC

fo: 10.7 MHz
± 75 KHz

SYMBOL

flf;;

v+;; 12V

v+: 8V

4_5 MHz

10

;;

flf

= ± 25
v+

KHz

= 12V

fo: 5.5 MHz
flf

= :t

50 KHz

v+ = 12V

TESTCIR·
CUlT OR
CHARAC·
UNITS
TERISTIC
CURVES
FIG. NO.
$0 SUPPL.Y VOlTAGE IV 'o12V

REF. SIGNAL

AMSIENT TEMPERATURE ITA'025"(.

LIMITS

100%,.1, ;W"1.AM

t-INT\ ITERN IO,!..

50 '0 ·'.'UHf

TYP.

MAX.

TYP.

MAX.

TYP.

MAX.

400

600

400

600

250

400

TYP.

'l-

MAX.
40

AMPL-LiMITER

Vi(lim)

AM Rejection*- ..

AMRlll

45

AVIlOI

55

Amp!. Voltage Gain.

250

400

141

-

37
55

-

36

-

40

60

-

60

-

V
IRMSI

7,6.8.9

dB

2,7,5,6

dB

'0

I V

t
.. .

20

DETECTOR

"- ~

i

r- .
t--

7

V /1

~ t-~ ~
..

Input Limiting
Threshold Voltage

1--

_.. j j

,

..

1,

H
Vi

L

F"'-;- REf.E~i '

.

S'1"5iiAi.-t

rlFII
•

6 I

Z"

~

INPUT VOLTAGE IVjl-mv[rm.1

Recovered Audio*
Output Voltage

VolAFI
111

0.48

Total Harmonic*
Distortion

THOlll

1

-

-

.Vi ,50IlV (rms)

0.3

1

-

-

0.72

1.5

-

-

1.2

3

-

V
IRMSI

%

6,7,8,9

Fig. 3 -AM r6jtICtion V$ input volt. {5_5 MHzJ.
7

·100% FM, 30% AM

___________________________________________________________________ 57

CA2111 AE, CA2111 AQ
~~hlB1ENT TEMPERATURE {TA1'2SoC
IOO%FM,30".AM
10 010.1 101Hz

• '0

t

T

~3oL

."
~

f-

/'

~-l-t-

,

-j

-

'v.l I I

-

I

,I

H-HT/f----+-rrr--r-+-r++--r-~

~~

Fig. 4 -Circuit sch.mlltfc-CA2"IA

~

0.'i-"1-+t--+-+-t-t+---j~++t+-t--l
0
4

COMPONENT VALUES
C,

CZ

80.1

4

6

B I

6

e 10

CHARACTERISTICS

"

C,

C,

,F

,F

UPPER

LOWER

PEAK

,F

KII

120

20

'"

0.003

100

20

30

0.003

120

6

INPUT VOLTAGE IVi)-mV [,m,)

DETECTOR TRANSFER

,..

'.7

"

·Fig. 6 '-Det«tad .udio output vs Input VO/tllgfl (4.5 MHz/.

MH.

....
5.37

5.63

0.01

10,5

10.9

~

I

~

0.9

NOTE:

~ o.e

Input to the quadrature coil tan be from
either terminal 9 or terminel10. Terminal
9 is normally used because it leuenl the
possibility of overloads during tuning.
Tho use of terminal 10 increases the
limiting sensitivity signifiamtly end has
been used successfully in these tests.

6 0,7r----:-++-+--+-f-+-+
o
~

0.6

~

0.'

g

0,4

~ 0.3
4

6

8 I

4

6

8 10

INPUT VOLTAGE IVil-mV[,ms]

Fig. 7 -Tsstcircuit.

Fig. 8-D"tllCt"d .udio output vs Input volt~ (5.5 MHz).

SUPPLY VOLTAGE ['.I t }·e

AMBIENT TEMPERATURE (TA)'25'C
MODULATION fREQUENCY 01 kHz

v

eo

~--

-+ -,--'--r+--f--r-'H-I

+
, +'
+

;1,1;t

INPUT SIGNAL VOLTAGE IVII-IOIv[rlM]

Fig. 9-Dttt.ctsd lIudio output

~·Ofl.

vs input IIOIt._ (to, 1 MHz)

·'o

·2'

°

2'

'0

75

100

H;

INPUT VOLTAGE 1Vi)-mV[,ms]

AMBIENT TEMPERATURE (TA l_oC

Fig. 70-AFC voltage vs ambient temp.

Fig. 11-Sign.'·to·naise ,.tia vs input volt3f1e.

58 __________________________________________________________________

CA3000

DC Amplifier

HIGHLIGHTS
Input IlIPedance • • • • • • • •• 195 ItO
Yoltage Glln. • • • • • • • • •• 30 d8
to-an-Node Rejection Ratio. ••
98 dB
Input Ofhet Yoltage. • • • • •• 1.1l IIIV
PUlh-Pull Input and Output
Frequency Capabil ity
DC to 30 MHz (with external C and R)
• Wide "'OC Range. • • • • • • • ••
90 dB

•
•
•
•
•
•

• Designed for use in Communication, Telemetry, Instrumentatioo, and
Data-Process i ng Equ i pment
• Balanced differential-amplifier configuration with controlled

constant-current source to pray ide outstanding versat i 1 ity
• Bu i It- i n temperature stab iii ty for operat i on from -5SoC to tl2SOC

typo
typo
typo
typo

typo

• Compan i on App I i cat i on Note, I CAN S030 "App I i cat ions of RCA CA3000

Integrated Circuit DC Ampl ifier" coverscharacteristics of different
ope rat ing modes I frequency cons iderat ions, 10 MHz narrow band
tuned amplifier design, crystal oscillator design, and many other
appl ieatian aids

APPLICATIONS
• Sch.itt Trillger
• RC ..Coupled Feedback ....pllfier

• lO·Lead hermetic TO-5 style package

• Mixer
• Coeparator

ABSOLUTE·MAXIMUM VOLTAGE LIMITS

±a V

MAXIMUM POWER SUPPLY VOLTAGE ···160r

at TFA = 25°C
OPERATING·TEMPEAATURE RANGE

_550C to +1250C

MAXIMUM SINGLE·ENDED INPUT·SIGNAL VOLTAGE

.±4v

STORAGE·TEMPERATURE RANGE

-6SoC to +1500C

MAXIMUM COMMON·MODE INPUT·SIGNAL VOLTAGE
MAXIMUM DeVICE DISSIPATION:

• ±:l V

LEAD·TEMPERATURE (DUring Soldering):

From -55°C to BSoC.
Above8SoC •

At distance 1/16 ± 1/32 inch 11.59 ±O.79 mmJ
from case for 10 seconds max. . .

• Modulator
• Crystal Olcllhtor
• Sense "'IIIPlifler

4S0mW

:

:

:

·ee;ate 5 mW/oC

ELECTRICAL CHARACTERISTICS, at TfA = 25"<:. Va: = +6V, VfE = -6V, unless otherwise specified
·LlMITS
SPECIAL TEST COIiolTIOliS
CHARACTER I ST I CS

Terminals "o.~ & "0.5 Not
Connected Unless Specified

SYMBOLS

TEST
CIRCUITS
Fig.

TYPICAL
CIlARACTEll ISTICS
CIRVES

TYPE
CA3000
Min.

I Typ.

-

23

36

Max.

Units

I.ij

5

oV

2

1.2

10

'"

2

Fig"

STATIC CHARACTERISTICS
Input Offset Voltage

VJo

Input Offset Current

JJo

lIB

Input Bias Current

'"

TERMIHALS
Quiescent Operating
Vol tage

Device Dissipation

VB

or
VIO

Po

ij
HC
HC.
VEE
VEE

5
HC
VEE
HC
VEE

HC

HC

-

2.6
ij.2
-1.5
0.6
30

DYNAMIC CHARACTER I ST ICS
Differential Voltage Gain
Single-Ended Input

Single-Ended Output f • I kHz
Oouble-Ended Output f - I kHz

AD IFF

6
6

2B

-

32
38

3

- V
- VV
- V
- ...
- d8dB
-

IIOIIE

kHz

7

-

V(P_P)

IIOIIE

dB

8

n

10

12

4
4
4
4

5
5

VOUT(P-P)

f • I kHz

6

-

CMRR

f • I kHz

9

70

98

Single-Ended Input
Impedance

Z IN

f • I kHz

11

70K

I95K

Single-Ended Output
Impedance

ZOUT

f • I kHz

13

5.5K

BK

10.5K

n

Total Harmonic Oistortion

THO

-

0.2

5

%

lij

80

90

-

dB

NOlIE

Bandwidth at -3 dB Point

Max imum Output Vol tage
Swing
Coman-Mode Rejection
Ratio

AGe Range (Max i mum Vo I tage
Gain to Complete Cutoff)

8W

VI::: 10mV, R.s= 1 kn

RS=lkn f ., I kHz VO=42Vp'F

AGe

f " I 1kHz

15

650
6. I~

ReshfanCI valu •• al"l irl ohm.

Flg.1 SCHEMATIC DIAGRAM

-

STATIC CHARACTERISTICS FOR TYPECA3000
IHPUT OFFSET VOLTAGE AND CURRENT vs TEMPERATURE

.>

" ,

POSITIVE OC SUPPLY VCLTS tVccl. +6
NEGATIVE DC SUPPLY VOLTS (VEEI" -8

INPUT BIAS CURRENT

V$

QU I ESCENT OPERATI NO VOLTAGE vs TEMPERATURE

TEMPERATURE

POSITIVE DC SUPPLY VOLTS {vccl. +6
NEGATivE DC SUPPLY VOLTS ("IE 1·

PCSITIVE DC SUPPLY vOLTS ('''ccl' +(
NEGATIvE DC SVPPLY VOLTS {VEE}' -6

II
'0'0

.-~~

~~2.5

z.

2

0"

ot

o

"

AMBIENT TEMPERATURE: (TA I-'C

-15

-50

-25

25

50

15

AMBIENT TEMPERATlJRE {TA !-"C

100

125

-"

"

75

roo

125

AMBIENT TEMPERATURE IT A 1-"(;

Fig.~

Fig.2
Fig.3
________________________________________________________________________
59

CA3000
DYNAMIC CHARACTERISTICS AND TEST CIRCUIT FOR TYPE CA3000
DIFFERENTIAL VOLTAGE GAIN vs TEMPERATURE

OUBLE-

III

POSITIVE OC SUPPLY VOLTS (Vee). +6
NEGATIVE DC SUPPLY VOLTS tVEE)' - 6

Vee

+6 V

ED OUTP

SINGI,;E_ HDED

.-,.

BANDWIDTH AT -3 dB POINT vs TEMPERATURE

DIFFERENTIAL VOLTAGE GAIN AND MAXIMUM OUTPUT
VOLTAGE ~WING TEST CIRCUIT

L
L
CC. +
NEbATIV£ DC SUPPLY VOLTS tV'EE:'o -6
fREQUENC't(tJ' .ke/.

nsti!iT'lv

TP.Ut

-6V
VEE

AOIFF. • 20 LOG'O VeUl

-25
25
50
7S
AMBIENT TEMPERATURE (T ... I--C

"N

2

0,01

",

466

0.1

2

468

"

FREQUENCY (f)-MHl

Fig.6

Fig.S

Fig.7

COMMON-MODE REJECTION RATIO TEsr CIRCUIT
SINGLE-ENDED I NPUT IMPEDANCE vs TEMPERATURE

COMMON-MODE REJECTION RATIO vs TEMPERATURE

PDSITIVE DC UPPLY VOLTS Vee' +6
NEGATIVE DC SUPPLY VOLTS (VEEI'-6
FREOUENCY \ f). 1kHz

POSITIVE DC SUPPLY VOLTStVeel- +6
NEGATIVE DC SUPPLY VOL.TS \VEE'- -fi
fA
N Y ' Ik

~§

.< .

~!c94

8

93

-50

o

-6V

-2~

-75

VEE

AMBIENT TEMPERATURE

IT A I_"C
CClUMON-MOOE

Flg.8

REJECTI~

AATIO(CMRlo 20 log

-50

"

AMBIENT TEMPERATURE IT A l-"C

!Ai!~31

'"
92CS-13:>J16

- .... SINGLE-ENOED VOLTAGE GAIN AS MEASURED
IN CIRCUIT SHOWN IN FIG. 68

Fig.IO

Fig.9
SINGLE-ENDED INPUT IMPEDANCE TEST CIRCUIT

SINGLE-ENDED OUTPUT IMPEDANCE vs TEMPERATURE

Vee
+6V

(Vee)'

CI

POSITIVE OC SUPPL.Y YOLTS

j ,

NEGATIVE DC SUPPLY VOLTS !VEE'- -6
FREQUENCY f • I io.

!

I!

8

-15

Fi g.1I

SINGLE-ENDED OUTPUT IMPEDANCE TEST CIRCUIT

+11

-50

-25

" '"

AMBIENT TEMPERATURE (T A I_oc

'00

'"
F i g.13

Fig.12
TOTAL HARMONIC DISTORTION

v.

TEMPERATURE

AGC RANGE TEST CIRCUIT

POSITIVE DC SUPPLY VOLTS 1Vcc • +6
HEGATlV[ DC SUPPL.Y VOLTS (VEE)' -6
FREOUENCY C f). I kHz

Vee
+6V

~O.7

~
~

0.5

n..
-75

-50

-25

..

'"

100

125

AMBIENT TEMPERATtJRE IT .. I-'C

Fig~ 15

Fig.I"

60 ________________________________

~

___________________________________

CA3001

Video and Wideband Amplifier

HIGHLIGHTS
• Pu.h.Pull Input & Output
_AGe Rang.
60 dB typo
• Bandwidth . . . . . . • . . . .
29MHt
o Input R•• I.fance .•...• ISO k[] Iyp.
eOutput Reai.tonc ••.•••
typo
• Voltog. Goin ••.••••.. 19 dB typo
_Input Off ... Voltog •••.. 1.5 mV typo

-D.,lgned for u•• in Video 5ystHl' and Coramunlca.lon Equipment
• Balanced dlff.rentlal amplifier configuration with cORtroll.d conl'ont'curren' sourc.
provld •• outstanding versatility

.S []

_Built·ln temp.ratur•• tability for op.ration from ·SSGC to +125°C
• Emitter

~Iow.,

input & output

APPLICATIONS

eCompanion Application Hot. ICANS038 ·Application of the RCA.CA3001 IntegratedCircuit Video Ampllfle,", co ..... n diff.ren, operating mod ••• goin control. diatonion,

.winll capability, 3

e DC, IF. 5.
Video
Amplifi.,

e Schmitt Tri!il!il.r

"0,. amplifi., de.i,II,and a Schmitt tri".r .tud.,.

eMiu.
eModulator

·12-Lead Hermetic TO-S Style Package
ABSOLUTE-MAXIMUM VOLTAGE AND CURRENT LIMITS .t TA = 25°C

Indicated voltale or current limits for each taminal can be applied under the specified conditions for other termiDala.
All Voltages are with respect to ground (common tenninal of Positive and Negative DC Supplies).

TERMINAL

1

VOLTAGE OR
CURRENT LIMITS
POSITIVE

TERMINAL

VOLTAGE

-2.5

+2.5

2.6
3,10
9

,.;

·8.5

0

·10

0

5

6

·8.5

0

..

0

-2.5

+2.5

Fig.' _ Schematic Diag,am.

TERMINAL

VOLTAGE

1.2,6,10

..

3

3,10
9

0
,.;

9
1,2,6
9
10
1,2,6
3.10
9

9

0
,.;

10

D

·lD

'lD

1,2,6,10
3

D

1,2,6
3
9

11

25 mA

,.;

D

0

O;:-"s~.,.

,.;

VO("'4G~
OFFSET
-~

CONNECTED BETWEEN
TERMINALSNa.l0&Na.U

0

,.;

CASE

CIJRREf~r

2:i
~
75
AMSIENT TEMPERATURE (TA)-OC

-25

0

Fig.2 -Input offset valtoge and current vs. temperature.

INTERNAL CONNECTION
DO NOT USE

12

INTERNAL CONNECTION
DO NOT USE

..
..
..

1,2.6.10
D
3
,.;
9
200·0 RESISTOR

0

1.2
3,10

POSITIVE DC SUPPLY VOLTS (VCC)0+6
tiEGATIVE DC SUPPLY VOLTS (VEE)·-6

CONNECTED BETWEEN
TERMINALSNo.8 & No.1

..
..
..
..

0

,.;
9
200·0 RESISTOR

25 mA

8

0
·S.5
,.;

9
7

POSITIVE

0

10

4

NEGATIVE

..

1,2,6
3

CONDITIONS

TERMINAL

NEGATIVE

1.6
2

'"
'" Intetna( ConnecUDfI - DO NOT USE

VOLTAGE OR
CURRENT LIMITS

CONDITIONS

INTERNALLY CONNECTED TO TERMINAL NO.3
(SUBSTRATE)

DO NOT GROUND

OPERATING TEMPERATURE RANGE ..

·55 0 C to +125 0 C

STORAGE TEMPERATURE RANGE

·65 0 C to +ISOoC

I

POSITIVI:: DC SUPPLY VOLTS IVCC)0+6
NEGATIVE DC SUPPLY VOLTS (VEE)0-6

LEAD TEMPERATURE (During Soldering):
At distance 1/16 ± 1/32 inch (1.59 ± O.79mm)
+26S o C

from case for 10 seconds max.

MAXIMUM SINGLE·ENDED INPUT·SIGNAL VOLTAGE

±4V

MAXIMUM COMMON·MODE INPUT-SIGNAL VOLTAGE

±2.5 V

MAXIMUM DEVICE DISSIPATION:

o
-1!\

·55 to 85°C
Above 85°C

Derate linearly S mW fOe

POSITIVE DC SUPPLY. VOLTS ("CC)· ... 6

-25
0
2~
~
1!\
AMSIEtiT TEMPERATURE ITA1-"C

fig.3 - Input bias current vs. temperature.

POSITIVE DC SUPPLY VOLTS ("<:C)'+6
tiEQATIVE DC SUPPLY VOLTSiVEE1- 6

NEGATIVE DC SUPPLY VOLTS (VEE)·-6

> 80

l

-500

450mW

MODE
MOOE A

~

70

MODE C

MODE 0

~

~ 90

MODE C

u'"

MODE 0

~

MODE A
MODE B

7~

AM8IENT

100

125

TEW[RATiJR[ ITA )-"C

Fig. 4 - Output oHset valtage vs. temperature.

- 50

-2~

AM8IENT TEMPERATURE ITA) -'C

Fig. 5 - Quiescent operating voltage vs. temperature.

-~

-2~

0

100

125

AMBIENT TEMPERATURE (TA1--C

Fig. 6 . Device dissipation vs. temperature.

_________________________________________________________________________ 61

CA3001
ELECTRICAL CHARACTERISTICS, AT TA = 25°C, VCC = +6 V, VEE = -6 V

CHARACTERISTICS

SPECIAL TEST CONDITIONS

(See Page 2 for

Terminals No.4 and No.5

SYMBOLS

POSITIVE DC SUPPLY VOLTS (vccl·+S
NEGATIVE DC SUPPLY VOLTS (VEElo-S
FREQUENCY (11-1.75 MMz

LIMITS

TYPICAL

TYPE CA3001

TERISTICS
CURVES

CHARAC~

TEST

CIRCUITS

Not Connected
Unless Specified

Definitions of Terms)

Fig.

Min.

Typ.

Max.

Units

Fig.

mV

2

~ 18.!i

STATIC CHARACTERISTICS:

Input Offset Vollage

VIO

12

Input Offset Current

"0

13

,

10

"A

2

13

16

36

"A

3

54

300

mV

4

Input 8i as CUllen!
"

Output Offset Voltage

1.5

AS'" 1 HZ

VOO

TERMNALS
4

5

A

NC

NC

V

5

B

NC

VEE

4.B

V

5

C

VEE

NC

2.7

V

5

0

VEE

VEE

4

V

5

3,B

OR

Voltage'

V11

Device Dissipation

PD

-"

Fig. 7 - Dif/erential voltage gain ys. temperature.

MODE
VB

QUiescent Operating

18.2

4,4

5

A

NC

NC

mW

6

B

NC

VEE

71

mW

6

C

VEE

NC

110

mW

6

D

VEE

VEE

B6

mW

6

60

7B

120

POSITIVE DC SUPPLY VOLTS (vcclo+6
NEGATIVE DC SUPPLY VOLTS (VEElo-6
AMBIENT TEMPERATURE (TAloZ5'C

DYNAMIC CHARACTERISTICS:
Differential Voltage Gain
(Single-ended Input

~d

f

AOIFF

output)

Bandwidth at -3 dB Point

f

BW

Maximum Output Voltage Swing

VOUT{P,P)

1.75 MHz
20 MHz

16
10

19
14

dB

son

16

29

MHz

NONE

Vp.p

NONE

AS -

As"'-SOflf==1.75MHz

5

f

1.75 MHz, RS

lKi:

11

f

11.7 MHz, RS

1

K~':

11

5

7, B

dB

8

~

ISf--.+--+-f++_·

3 ,,~ -++++-+-+H1~I-H'tt--+-t+H

dB

NF

Noise Figure
Common-Mode Rejection RatiO

7.7

dB

9

CMRR

f

1 KHz

70

BB

dB

10

R'N

f

1.75 MHz

50

140

KO

11

Input Impedance Components;

~

~

~

6 8

4

6 8

10

Parallel Input ReSistance
Parallel Input Capacitance
Output Resistance
AGe Range

(Maximu~

voltage

e'N

f

1.75 MHz

3.4

7

OF

ROUT

f

1.75 MHz

45

70

\I

NONE

AGC

f

1.75 MHz

dB

NONE

55

60

11

FREQUENCY If) -

?

•

e

6

100

1000

MHz

Fig. 8 • Differential yoltag. gain ys. frequency.

gain to complete cutoff)

POSITIVE DC SUPPLY VOLTS (VCClo+6
NEGATIVE DC SUPPLY VOLTS (VEE)o-6
FREQUENCY If). I kHz

,
SOURCE RESISTANCE (Rst-A

Fig. 9· Noise figure ys. source resistance ant! frequency.

-!i0

75
-25
AMBIENT TEMPERATURE (TAI-OC

Fig. 10· Common.mode re;ection ratio

YS.

POSITIVE DC SUPPLY VOLTS (VCcl- +s
NEGATIVE DC SUPPLY VOLTS (VEEI'-6
AMUlEt-IT TEMPERATURE (TA)02!i'C

100

125

oI

I

10

100

FREQUENCY ( f ) - MHz

temperature.

Fig. 11. Input impedance components ys. frequency.

62 ______________________________________________________

~

_____________

CA3001

.,
'cc

• Separate tuned input circuits are used fOI 1.75 MHz and 11.7 MHz.
Source-resistance matching taps adjusted with circuit tuned to
resonance and with SO-ohm lesistor connected to simulate
noise diode.

112CS-!3581

I. AdJ".t Vit lor VOUT(DC) 00

± 0.1

~

lnput oIl ..t ¥oIl ••• (Vro) In mV •• ,

2.11 ••• 111'. VI: and r.l;:ord
Va:
VlO·iQOo

Fig. 13 • Input oHut eurrenf ana input bias curren'
tnt

e;rcuif~

Fig. 14 • Noise figure t.sf circuit.

Fig. 12 • Input oHset voltage test eireuit.

37-Z50·

"

OSCILLOSCOPE
WITff ffIGff-GAIN
OIFFERENTIAL
INPUT
(TEKTRONIX TYPE
530. 5"0. OR 580
~-1!'r-""'" WITH TYPEO PLUG-IN
TEKTRONIX TYPE 502,

"

EOUIVALENTl

COMMON- MODE REJECTION RATIO
CMR. ZO LOG IO

tA~1~~::~'131

"A' SINGLE -ENDED VOLTAGE
GAIN

AGe RANGE' ZO LOG

A WITH S IN POSITION X
10 A 'WITH S IN POSITION 'f

Fig. 15 - Common·moJe rejection rotio test circuit.
Fig. 16 _ AGe ram]" t"sf circuit.

._ _ _ _ _ 63

CA3002
HIGHLIGHTS

IF Amplifier

• Input Resistance. . . . .. 100 kD typo
• Output Resistance. • • .•
70 n typo
• Voltago GaIn .. 24 dB typo @1.75 MHz
• Push· Pull Input, Slntl.-Ended Output

• Designed for use in Communication Equipment

• Balanced differential amplifier configuration with controlled cons.an•• curren. sourCe
provides outstanding nrsa,lIity

• .3 dB Bandwidth •••.•• 11 MHz typo
• AGC Rang.. • • . • . • . .• 80 dB typo
• Useful Frequency Ronqe DC to •• 15 MHz

• 10·Lead hermetic TO·5 style package
• Built-in temperature stability for operation from ·SSGC to +12SOC

eCompanion Application Hot.ICAH·5036 -Application of the RCA.3002Integrat.d.Circuit
IF Amplifier· covers different operating mod.s, cross modulation, gain control, .c. stage

APPLICATIONS

amplifier design, and an envelope and product detector analysis.

ABSOLUTE·MAXIMUM VOLTAGE AND CURRENT LIMITS,

atTA

=25°C

• Product Detector

• AM Detector

.IF & Video
Amplifier

• Schmitt Trigger

COMMON·MODE INPUT SIGNAL VOLTAGE. .. . . . . . . . .. .. ±2 V
MAXIMUM POWER SUPPLY VOLTAGE ............ 16 V or ±8 V
OPERATlNG·TEMPERATURE RANGE

'"

·SSoC to +12Soc

STORAGE·TEMPERATURE RANGE

-6SoC to +ISOoC

LEAD TEMPERATURE (During Soldering):
At distance 1/16 ± 1/32 inch,(1.59 ± O.79mm)

+26SoC

from case for 10 seconds max.

MAXIMUM INPUT·SIGNAL VOLTAGE

±4V

MAXIMUM DEVICE DISSIPATION:
.SS to 8SoC

4S0mW

Above 8SoC

Derate linearly S mW/oC
*TERMINAL No 6 IS AN
INTERNAL CONNECTION

A,

500

00 NOT USE

A"

OK

CASE AND SUBSTRATE
ALL RESISTORS ARE

STATIC CHARACTERISTICS AND TEST CIRCUITS

POSITIVE DC SUPPLY VOI..TS (Vec)' +6
NEGATIVE DC SUPPLY VOLTS (VEEI'-6

POSITIVE DC SUPPLY VOLTS (Veel- +6
NEGATIVE DC SUPPLY VOLTS (VEE)- -6

POSITIVE DC SUPPLY VOLTS (VCcl- +6
NEGATIVE DC SUPPLY VOLTS WEEl--6

92CS-12953R2

IN OHMS

Fig. 1 - Schematic diagram.

o :e
MODE A

°

·n

50
AMBIENT

7'5

100

TEMPERATURE tTAI-·C

°

125

-75

'IS

-~

-25
At.EIENT

92C:5-13341

Fiq.2 - Input unbalance voltage & current

temperature.

°

-75

'00

-~

Fiq.3 -Input bias current

'IS

temperature.

-25

2~

0

!l0

70

AMBIENT T[MP[R4TVR£ (TA I-·C

TEMPERATURE (TA}-·C

Fig.4 - Quiescent operating voltoqe vs temperature.

STATIC CHARACTERISTICS AND TEST CIRCUITS

+.

POSITIVE DC SUPPLY VOLTS (Vecl- +6
NEGATIVE DC SUPPLY VOLTS WEEI6

POSITIVE DC SUPPI..Y VOLTS (VCC)NEGATIVE DC SUPPLY VOLTS {VEE}- -6
AMBIENT TEMPERATURE tTA) -25'C

FREQUENCY If I .1.75 MHz

• 2ol--+-t-H-t--+-H-+F'-"'."t--j--j-H

~

~ I~I--+-t-H-j-.-+-H-+t-f-,,"H-ti

~
"-n

l°l--+--I-I+-I-+-H+f-+-Hrn

. '"

'00
AMBIENT

TEMPERATURE ITA I-'C

Fig. 58 - Differential voltage gain

'IS

temperature.

FREOUENCY It)-M,".

'0

. '"

Fig. 5b- Dilferential voltoqe gain vs frequeney.

64 ____________________________

~

,o0

.; trttt Iii+'

,
-75

-50

-25

0

25

75

'00

AMBIENT TEMPERATURE (TA l-·C

Fig. 6 _ Bone/width at -3 clB point vs temperature.

_____________________________________

CA3002
+,

ELECTRICAL CHARACTERISTICS, at T A =2SoC, VCC = +6 V, VEE =·6 V

POSITIVE OC SUPPLY VOLTS (VcclNEGATIVE DC SUPPLY \lOlTS (VEE)' - I

AMBIENT TEMPERATURE (TA}·2;$·C
FREQUENCY [t) • I,T5 IoIHI

LIMITS

SYMBOLS

CHARACTERISTICS

SPECIAL TEST CONDITIONS
TERMINALS No.3 &No.4
NOT CONNECTED
UNLESS OTHERWISE NOTED

TEST
CIRCUITS
Fig.

TYPICAL
CHARAC·
TERISTICS
CURVES
Fig.
Typ. ~ Ma'-l Units
CA3002

Min.

10

STATIC CHARACTERISTICS:
Input Offset Voltage

VIO

Input Unbalance Current

IlU
II

Input Bias Cunent

MODE

2 I

I

A

VEE

~A

2

20

36

~A

3

.'

B

VEEI

2000

'00

4

SOURCE RESISTANCE (R.)-n

NC

2.8

V

4

VEE

3.9

V

•

55

mW

PT

Device Dissipation

OYNAMIC

2

10

TERMINAL

Quiescent Operatlna:
Voltaal!

mV

2.2

2.2

4

Fig_ 7" Holse ligure vs source resistance.

Non.

Vee

"v

CHARACTER~TICS:

Differential Voltaae Gain

VIN "10mV

(Slna1e-Ended Input

AOIFF

f" 1.75 MHz
As_ SOn

BW

AS· 50n, VIN - 10 mV

and Output)

Bandwidth at ·3 dB Point

Maximum Output Voltaae Swing

24

19

VouTlP'P)

Noise figure

NF

f

=1.75 MHz RS .. 1 kO

dB

11

MH,

6

5.5

Vp.p

None

dB

1

8

4

8

5 &.5

Input Impedance Components:

Parallel Input Resistance

RIN

''" 1.75 MHz

Nan.

lOOk

n

None

Parallel Input Capacitance

.elN

, .. 1.75 MHz

None

pF

None

ROUT

f '" 1.75 MHz

I.

•

n

9a& 9b

Output Resistance
AGe Ranee (Maximum Voltaae
Gain to Complete Cutoff

AGC

'''1.7SMHz

POSITIVE oc SUPPL.Y VOL.TS (Vcc)· +6
NEGATIVE DC SUPPL.Y VOL.TS \VEE)' -6
FREQUENCY If) • 1.15 ""HI

10

13

60

dB

SO

VEE
-.v

•!rfu

S t~~ ~~~~t-:o ~s~~°:r!:: !~de;~edM~r.I\I:!d~
connected to simulate the noise diode.

~~~e~~s~o'

Fig. 8 - Nois. I;gllre.

12

.a

.1

POSITIVE DC SUPPLY VOLTS (Vee)NEGATIVE OC SUPPLY VOLTSIV[£)' - ,

POSITIVE DC SUPPLY VOLTS tVcel'
NEGATIVE DC SUPPLY VOLTS tVIEIE)' -6
AMBIENT TElllptRATUfiE [TA I'Z5'C

FREQUENCY tn • I.~ MHI
INPUT AOJUSTED FOR 3,d OROER ,H"RIoIONIC 1
'Ode eELOw 'UNDAMENTAl.

IN Llr,

OUT U

~~20

~

1

J
J

i

~ 10

!;;
'0
ANBIE'H

TEhiPERAlURE IT"l-"C

Fig.9a - Output resistance vs temperature.

10

15

20

25

30

FREOUENCY tt)-MHI

AMBIENT TE,M'ERATURE ITAI-·C1

Fig. 9b· Output ruisfance vs "equency.

fig. 10 - Input level for - 30 dB intermodulation

w. temperature

Vee

+.v
OSITIVE OC SUPPLY VOLTS tVccl • • ,
NEGATIVE DC SUPPLY VOLTS {VIEIE}.-I
"IIIIIENT l(M'[1I:ATUft[ (T")'25-C

11 Incre_ both input-signal tones until th. 2f2·f1 Ind 21,-12 outputsignll voltlgas arll 30 dB below th.
Ind f2 autpuHlp voltlgu_

f,

21' Mll$Ur. rms values of the input .nd output signal "olt'get.

3) Th. m..surlld input signel volt. i, thlt vllu. when th. 3rd-h.r·
monic intermodulatio" products are 30 dB below the fund.mentel outputs.

Fig_ 11 - Intermodufation Test Circuit.

1) Set attenultor at 80 dB attenuation.
101520~30

FR!QU[NCVUI-NHI

Fig. 12- AGe ranve

VI

Irequency.

~)

Set variable de supply voltap at 0 v.

3) Incrt.sealpal InputvoltJpuntil RF V.T.V.M. indicates 5 mV

output.
.) Set v.lable de supply volta,_ at 006 V.
5) Adjust sttenu.tor until RF V.T.V.M. aaain Indicates 5 mV autput.
6) Chan •• in attenuator "ttin. in dB Is total AGC Ranae.

Fig. 13· AGe range.

---------------------------------------------------------------~

CA3004
RF Amplifier
• I)esigned for use in Communications Equipment

• Balanced Differential-Amplifier Configuration with Controlled Canstant-Current
Saurce Provides Unexcelled Versatility
• Built-in Temperature Stability for Operatian from _SSa C to +1250 C
• Similar ta RCA CAlOOs and CA3006, plus Emitter-Degeneration Resistors
to Provide More Linear Transfer Characteristic and Increased Input-Signal
Handling Capability

•

Push.Pull Input and Output

•

Wid. and Marrow-Band Amplifier

•

AGC

•

Detector

•

Oporatio. fro .. DC to 100 Me/o

•

Mix.,

•

Limit.r

•

Modulator

•

RF. IF. and Video Frequency
CopobJlily

• Companion Application Note ICAN 5022 .. Applicatian of RCA CA3004, CA300s,
and CA3006 Integrated Circuit RF Amplifiers", covers characteristics of
different operating modes, noise performance, cross-modulation, mixer, AGe,

SCHEMATIC DIAGRAM FOR CA3004

limiter, d.tector, and amplifier design considerations.

• 12·Lead Hermetic TO-5 Style Package

ABSOLUTE·MAXIMUM VOLTAGE LIMITS, .t TFA • 25°C
Voltage limits shown for each terminal can be applied under the indioated circuit conditione tor other terminals.
AU voltages are with respect to GROUND (common terminal or Positive and Negative DC Supplies)

TERMINAL

I

CONOITIONS
VOLTAGE LIMITS
NEGATIVE POSITIVE TERMINAL VOLTAGE

TERMINAL

NO CONNECTION

I

2

3

4

5

6

·9.5

·12

·12

..
-3.5

0

0

0

0

.3.5

6
12
3
9
10
II
2
6
9
10
II
12
2
6
9
10
11
12
2.6.12
3
9
10
11
2
3
9
10
11
12

VOLTAGE LIMITS

",

o.

8

9

10

11

12

CASE

2
0
-.6
3
6
0
.12
0
<6
10
<6
\I
0
12
0
2
-6
3
0
6
.12
0
9
<6
<6
\I
0
12
0
2
-6
3
0
6
<12
0
<6
10
<6
II
12
0
0
2
-6
3
0
6
.3.5
·3.5
<6
9
10
<6
.s
11
INTERNALLY CONNECTEO TO TERMINAL
NO.3 (SUBSTRATE) DO NOT GROUNO

".

"z

NO CONNECTION
NO CONNECTION

7
0
0
-9.5
<6
<6
<6
0
0
<6
<6
<6
0
0
0
<6
<6
<6
0
0
-6
<6
<6
<6
0
-6
<6
<6
<6
0

CONOITIONS

NEGATIVE POSITIVE TERMINAL VOLTAGE

NOTEI Connect Tormlnal No.10 to
pOlltl<,. dc auppl, volta,. u .... for
circuit.

,".1'

FI,.l

TYPICAL STATIC CHARACTERISTICS AND
TEST CI RCUITS FOR TYPE CA3004

(Figs. 2 to 8)
IIIPUT OFFSET VOLTAGE AND CURRENT
VS TEMPERATURE
POSITIVE DC SUPPlY VOl.TS{VCC'-

+,

NEGATIVE'DC SUPPLY VOl.TS tVEE). -I

OfF.:

~~

-25

25

50

75

100

12!!

FREE-AIR TEMPERATURE ITFA)-·C

Flg.2
INPUT BIAS CURRENT VS TEMPERATURE

OPERATING·TEMPERATURE RANGE

..55°(' to +I :!soc

STORAGE·TEMPERATURE RANGE

. ·os°('

to +150oC

POSITIVE DC SUPPLY VOLTS 'Vee). +t
NEG ..TIVI DC SUPPI.Y VOlTS (VEE). -I

LEAD TEMPERATURE (During Soldering)
AI distance 1116 t 1/32 inch (1,59 :t: O.79mm)

from case for 10 seconds max.

. +265°(,

MAXIMUM SINGLE·ENDED INPUT·
SIGNAL VOLTAGE

. ±3.S V

MAXIMUM COMMON·MODE INPUT·

SIGNAL VOLTAGE

MAXIMUM DEVICE DISSIPATION

. . . . . . . ·2.5 V, +3.5, V

..........•.

. 300 mW

Flg.3

66 _________________________________________________________________

CA3004
INPUT OFFSET VOLT AGE TEST CIRCUIT

ELECTRICAL CHARACTERISTICS, at TFA = 250 e, Vee = nt, and impedance.
• All types are electrically identical within their voltage groups
• Designed for use in Telemetry, Data-Processing, Instrumentation, and

70
103
10
1

60
94

Open-Loop Voltage Gain. _
Common·Mode- Reje-ction Ratio.
Input Impedonce
Input Offset Voltage
Input Offset Current.
Input Bios Current.
Static Power Drain at 12V.
at . 6 V
at . 3 V .

20
0.9

0.3
2.5

Communication EQuiplTI('nt

0.5

4.7
175

30

30

7

7

dB typo
dB typo
k typo
mV typo
A.typ.
A typo
mW typo
mW typo
mW typo

APPLICATIONS

d Built-in temperature stability from -55°C to 11250C for Flatpack, TO-5
style, and ceramic dual in-line packages; oOC to +70 oC fCl' plastic dual

• Narrow- Band and Bandpass Ampli!ier
• Operational Functions
• Feedback Amplifier
• DC and Video Ampli!ier
• Multivibrator

in-I in(> package

• Companion Application Ndes ICAN-5290. "In({>gratl~d CircuitOpE:ralional
Amplifiers"; ICAN-S213. "Application of the RCA-CA3015, CA3016 Integrated Circuit Operational Amplifiers"; and ICAN-50IS, "Application
of the RCA-CA1008, CA30l0 Integrated Circuit Operational Amplifiers"
covet 80::\(.' characteristics, phas~ compensation, fn~quenc.v shaping, and
amplifier design.

ELECTRICAL CHARACTERISTICS at TA

•
•
•
•
•

Oscillator
COlnparotor
Servo Driver
Scaling Adder
Balanced
Modulator-Driver

25°C

0

Special Test Conditions

Characteristics

Symbols

Terminal No.8 (CA3008A.
CA3008A
Test
CA3016A, CA3019A, CA3030A, Cir·
CA30l0A
CA3037A, CA3038A),
CA3019A
cuit
Terminal No.5 (CA3010A,
CA3037A
CA3015A) Not Connected
Unless Otherwise Specified
Fig. Min. Typ.1 Max. Min.

Typical

CA30l6A
CA3015A
CA3030A
CA3038A

Units

Charac·
teristic
Curves

~

Typ. Max.

STATIC CHARACTERISTICS:
Input Offset Voltage

CAJ008A
CA3016A
CAJ029A
CAJOJOA
CAJOJ7A
CAJ038A

Input Offset Current
Input Bias Current

VIO

VCC

0

~

",V,
+12V

" +6V

110

o .l1V
" +6V

liB

o

.l1V

Input Offset Voltage
Sensitivity:
Positive

-'.VIO :NCC

" t6V

Negative

!lVIO !lVEE

" +6V
" tl2V

o

VEE 0 -6V
o -t1V
- -6V
o -11V
o -6V
o -11V
- -6V
- -11V
o .6V
o .11V

.11V

0·6 V
" -11V
VCC - .6V
Device Dissipation
Po
5:shorted to j
VEE 0 ·6V
VCC 0 .11V.
8 shorted to 12
VEE 0 ·11V
DYNAMIC CHARACTERISTICS: All lest, al f 0 I kHz excepl BWOl

4

0.9

1

5

0.3

1.5

5

1.5

4

0.10

I

0.16

I

4

- +6 V

AOl

Open·Loop Bandwidth
at ·3 dB Point

BW Ol

Slew Rate
Common·Mode Rejection
Ratio
Maximum Output·Voltage
SWing
Input Impedance

SR
CMR

VCC 0 .6V.
- ·11V
- t6V
o

" +12V

VCC

0

.6V
o '6V
" .11V
o .6V
o .11V

ZOUT

Common·Mode
Input·Voltage Range

VICR

+6V

o -6V

o d2V

o -11V

==

+12V

Noise Figure

NF

8

57

8

200

II

LEAD TEMPERATURE (During Soldering):
At distance 1/16 ± 1/32 inch (1.59 ± O.79mm)
from case for 10 seconds max.

0 -3VJ:
0 ·6V R,o
0 -9V I kil
o-11V

6

0.096

0.5

0.156

0.5

60
66
100

310

3
7
70

94

8

4

6.75

14

IS

10

80

103

11

14

7.5

10

160

IS

18

70

300

-_.

11

VCC 0 .3V , VEE
o .6V
o .9V
".12V

4.7

1

~

1

~

3

mV/V

none

mW

none

500

FIII·l

SCHEMATIC DIAGRAMS

1.6

101

-6V vi R, " none
- -11V I kn
VEE 0 -6V
- ·11V

0.5

mV

175
4

c

o -6V
o -11V
o -6V
o -11V
o -6V
o -11V

==

ZIN

·6V
.l1V

VOWP)

Output Impedance

.l1V

VCC 0 '6V VEE

VEE" -6V
·11V
o .6V
- -11V

1

40

- d1V

Open· Loop [)ifferential
Voltage Gain

I

85
'0.5
-4

dB

6& 7

kHz

6&7

V·~

none

dB

11

Vp_p

9 & 10

kil

13

II

16

V

none

dB

17



LOAD "[SlSTANCE 1"1..1-1( OHMS
(b)

tfCII.l414t

Flg.9

(0)

MAXIMUM PEAK·TO-PEAK' OUTPUT VOLTAGE

'\If.

LOAD RESISTANCE

FOR CA3029A AND CA3030A
E'
~

POSITIY£

oe SUPPLY

VOLTS

I~ TERMINAl. No.1 OPtN

~"

..

rr

I

Nee'

HE. aA:nv[ DC SUPPLY VOI.TS tVU:1

~

~ ,.

.ua£NT TEMPE"ATI.It£ {TA" O·C

.
I,.

+2S'C

t~'C

~

a

o.t5

o.so

1.2.5

0.7$

L50

Lf5

(0)

.

..

LOAO RESISTANCE {RLI-K OHMS

LOAO RESlSTAHCf ''''...I-KG

F1t·10

2.

(b)

COMMON·MODE REJECTION RATIO AND COMMON.MOOE
INPUT ·VOL TAGE·RANGE TEST CIRCUIT
V 20 MHz

• supplied in the hermetic 10·lead
TO·5 style package
ABSOLUTE·MAXIMUM VOLTAGE LIMITS AT TA ~ 25° C
Indicated yoltage limits for each t.nnlnal can be applied under'th •• peclfled yoltoge
condition. for other tennlnal •. All yoltag •• ar. with , •• pect to ground (Terminal 8).

NOTE: TERMINALS 6, 7, ANO 9 OF RCAoCA3011 ANO CA3012 ARE USEO FOR INTERNAL
CONNECTIONS. 00 NOT APPLY VOLTAGES OR MAKE EXTERNAL CONNECTIONS TO
THESE TERMINALS.
CAlO11
TERMINAL
I
1
3
4
5
8
10

VOLTAGE LIMITS

I

.3
.3
.3
.7.5
.10
.7.5
.10

·3
·3
·3
.1.5
0
·3
0

CASE

S.me as 1
·310·3
·31,,3
·310.3
·310.a
·310+3

*

VOLTAGE CONDITIONS AT OTHER TERMINALS
2
4
5
8
3
.7.5
Ground
S.me.s I
.2.510.7.5
.7.5
.1.510.7.5
Ground
~~
.7.5
Ground'
S.me as I
.1.5'10.7.5
~~
.7,5
S.me.s I
Ground
o
S.me as I '" E
.1.510.7.5
Ground
~;B
.7,5
S.me.s I
.1.510.7.5
Ground

-

~

-

Same as 1

+2.Sto+7.S

+7.5

Ground

RESISTANCE """~UESAIIE IN O",MS
rNT£RNAL CONNECTION·OO Nor US£

Fig. 1 - Schematic diagram for CA3011

10
.7.5
.7.5
.7.5
.7.5
+7.5
.7.5

andCA3012.

INPUT·IMPEDANCE COMPONENTS
VS FREQUENCY

~

-

I

INTERNALLY CONNECTEO TO TERMINAL NO.8 (GROUND TERMINAL)

"IN
CAlO12
TERMINAL

.

VOL TAGE CONDITIONS AT OTHER TERMINALS
1
3
4
5
8
.1.510.10
+10
Ground
S.me.s I
.1.510 .10
.10
Ground

VOLTAGE LIMITS

10
+3
.10
I
·3
+3
S.me.s1
.10
1
·3
+3
·3 to +3
Same as 1
+2.510 +10
+10
Ground
-+10
3
·3
~--~--~--~--~~~~~~~~~,~~ < > ~~~~~~~~~~r-~~
+1.5
4
f-_-'-_-t_..c.::"--t
__·10:::_-t-_-.:.3.:::IO:...+::.3-t-,S:::.m:::e..:'::.'.:.I~ ~ "ii
.10
Ground
.10
.13
0
5
f-_..:...._-t-_-'_-t_-"'_-t-_
...:.3..:.lo_•..:.3-t-'s..:..m""..:•..:.'.:..1-1 8: ~
+2.5 to +10
Ground
+10
+10
·310.3
S.me" I
.1.510.10.10
Ground
.10
8
·3
-+;13
·3 to +3
Same as 1
+2.5 to +10
+10
Ground
10
a
INTERNALLY CONNECTED TO TERMINAL NO.8 (GROUND TERMINAL)
CASE

i

.5510.1150 C
·6510 .1~oC

OPERATING-TEMPERATURE RANGE
STORAGE· TEMPERATURE RANGE

_IN

,.

'II[QU[NCY Itl- Nell

Fig. 2

f

"

DUTPUT·IMPEOANCE COMPONENTS
VS FREQUENCY
DC !IlJIfIIJ' YOlTl (Ycc' - 'U

I .ueENT 1'DF£L'lAT\JRE

IT.-J - ZS·C

Example .1 Us. 01 LIMITS TABLE,
For RCA·3011,' maximum volt.ge of ±3 volt, m.y beapplied
to Terminal 1 under the follOWing conditions:

LEAD TEMPERATURE (DUring Solderingl:
At distance 1/16 ± 1/32 inch (: .59 ± O.79mml
from case for 10 seconds max.

Terminal 4 is at any de potential between +2.5 and +10 volts

MAXIMUM INPUT-SIGNAL VOLTAGE:

Terminal 5 is at a de potential of +10 volts

Terminal 2 is althe same de potential as Terminal 1
Terminal 3:

Between Terminals 1 and 2 .

±3 V

MAXIMUM DEVICE DISSIPATION.
. . 300 mil
RECOMMENDED MINIMUM DC SUPPLY VOLTAGE (V,,) .. 5.5 V

do not apply external voltage

ROUT
,

10

"

P'REQl.OCY (f)-Nell

Terminals 6,7, and 9 .re.1 0 de polenli.1 (NOT USED)

Fig. 3

Terminal 8 is al de ground potential

Terminal 10 is at a de potential of +10 volts
VOLTAGE GAIN AND INPUT LIMITING VOLTAGE

VS FREQUENCY
BLOCK DIAGRAM OF TYPICAL FM RECEIVER USING RCA·CA3C11 OR ( .. 30l2
INTEGRATED CIRCUIT WIDE· BAND AMPLIFIER

r-----------,

I

+vcc

_.I(NT TtMPEftATUR( CtA,-e·c

DC ........VYl1TSlvceJ·U
IOUR'CtraasTANC%IRS)-SOC

1-'::...
:;:;..;=s""""""=;="''"'''',.,·,:::;··;-,-,_+--+-++1--I700 =t

I

n

II

~

VOLTAGE GAIN

eoo

t
0

.£

~ &8~-+_-l-t-IH-_tl-,'-r--l-IfI---j:soo!
I
1

1

I
1

1

~

~

e

"f--+--l--l-H--t--t-\l\ft-t---i400 !

~
g~ 64f--t--t--HH---t--i.<-t-\t-t--I500
INPUT LIMITING VOLTAGE V

.,

1

1=L: _________
I 11=
Fig. 4

I

~

•

II

"I
2
•
FREQUENCY (fJ-Nc/.

,

'10

Fig. 5

82 ______________________________________________________________________

CA3011, CA3012
ELECTRICAL CHARACTERISTICS
CHARACTERISTICS

DISSIPATION TEST SETUP

TEST CONDITIONS
LIMITS
DC
AMBIENT
SETUP
RCA
FREQUENCY SUPPLY TEMPERA·
RCA
SYMBOL
&
CA3011
VOLTAGE TURE
CA30n
PROCEOURE
f
VCC
TA
Volt,
Fig.
Mcl,
°c Min. Typ. Max. Min. Typ. Max.
·55
80
66 80 135
.15
6
60 90 133 66 90 111
.115
70 - 65 70 111
·55
130
97 130 190
PT
6
.15
7.5
95 110 187 97 110 167
.115
95 100167
- 100
·55
150 110175
.15
10
- - - 150 190 155
.115
150 160 155
- ·55
55
50 55 .15
9
60 66 - 60 66
1
6
.115
50 61 - 61
·55
- 59 - 55 59 .15
9
65 70
65 70 1
7.5
A
.115
55 65 - 65
·55
- - - 55 61
.15
9
10
1
- - - 65 71 .115
55 66
.15
4.5
7.5
60 67 - 60 67 9
.15
10.7
55 61 - 55 61 7.5

-

-

Total
Device
Dissipation'

Voltage Gain"

-

- -

-

-

-

- -

Inpui-lmpedance
Components:
Paraliellnput
Resistance
ParaHellnput

·'tc

TYPICAL
CHARAC·
TERISTICS
UNITS CURVES

IMPUT-IMPEDANCE COMPONENTS
TEST SETUP

"'cc

5

4.5

1.5

.15

-

3

-

-

3

-

kI1

2

CIM

'7

4.5

7.5

.15

-

7

-

-

7

-

pF

2

ROUT

8

4.5

7.5

.15

-

31.5

-

- 31.5

-

kI1

3

Capacitance

COUT

8

4.5

7.5

.15

-

4.1

-

-

4.1

-

pF

3

Noise Figure

NF

10

4.5

7.5

.15

-

8.7

-

-

8.7

-

dB

Input Limiting
Voltage (Knee)

Vi(tim)

9

4.5

7.5

.15

-

300 450

-

300 40(

p.V

Resistance

ParallelOulput

• The total current dilin may be determined b'/ dlvldina PT tPj

Vee.

~I
Fig. 6

7

Capacitance

Q

~
mW
mW
mW
mW
mW
mW
mW
mW
mW
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB

RIN

Output Impedance
Components:
ParalielOulput

'"

Fig. 7

OUTPUT-IMPEDANCE COMPONENTS
TEST SETUP

Fig. 8

•• Recommended minimum de supply voltaae(Vccl is 5.5 V. Nominal

load cullent flowlnalnto terminalS Is 1.S rnA at 7.5 V,

NOISE FIGURE TEST SETUP

+Vcc

VOL TAGE· GAIN TEST SETUP
PROCEDURES

A· Voltaie Gain:

1) Set Input ftequency at desired value,
VI :: 100 ~V Ims.

2) Record vo'
3l Calculate Voltaae Gain A from
A =20 10BIO vaNi
4) Repeat Steps 1, 2. and 3 for each
frequency and/or for temperature desired.
B· Input Limltlni Voltap (Knee):
1) Repeat Steps Al and A2, using

vI=lOOmV
2) Decrease VI to the level at which '10
is 3 dB below its value fOI vI'" 100 mV.
3) Record v, as Input L.lmltlng Voltage
(Knee).

Fig. 9

Ll

= 82...ti,

center-tapped

l2 = 2,36 i41
Cl,C2 = Arco Type 423 padder, or equivalent

Fig. 10

________________________________________________________________ 83

CA3013, CA3014

Wideband Amplifier-Discriminators
BLOCK DIAGRAM OF TYPICAL TELEVISION RECEIVER USING RCA INTEGRATEDCIRCUIT SOUND-IF AMPLIFIER AHD DETECTOR SECTION

SCHE....TIC DIAGRMt FOR (A3013 AND CAJ014

'"

'"
Fig. 2

Fig. 1
ABSOLUTE-MAXIMUM VOLTAGE LIMITS AT T A

= 25°

C

Indicated voltage limits for each terminal can be applied un,der t~e specified v-alta",e
conditions for other terminals. All voltages are with respect to ground (Terminal 8).

FEATURES & APPLICATIONS,
• exceptionally high gain:
power gain at 4.S MHz -

=

• ncelliltn. AM rejection: > 50 dB
at 4.5 14Hz
• high audio. voltage recove,y _
220 mV typo at 4.5 MHz

2S kHz deviation
• wid. ,"quaney capability· _ 100 kHz
to

CA30!3

7S dB typo

• excellent limiting characteriltics _
input limiting 'foltoge (ltn . . )
JOOjolV typo at 4.SMHz

> 20 MHz

TERMINAL

·3
·3
·3

4

+2.5

5

0
.2.5
+2.5

7
8

• comprehensive circuit functions:

if amplifier, AM and noi.e limlt.,_
FM detector, audio preompllfle,

- supplied in the hermetic 10-lead TO,!;
style package

9
10

+'l:c

1
2
3
4

5
6
7
8

9
10
TOTAL DEVICE DISSIPATION IPr'-"ceI

·3
0
0

.3
.3
.3
.7.5
.10
.7.5
.7.5
.7.5
+7.5
+10

1

2

3

Same as 1
Sameas2

·3 to +3
·3 to .3
·3 to +3
·310.3
·310.3
·3 to +3
·3 to .3

Same as 1
Same as 1
Same as I
Same as 1

~

g

1.:s
~

!5:

Same as 1

J6E.\"

, , III , ,
68 0,1

III

"I

,

E!.IITTER CURRENT (IEI-mA

0
6610

.

~

eASE CVRRENT 1101'0

0,8

~
,0

10'

!

i;).

~c.

~.f/

~ 1011

",0'

,

i I:,
~

fl.J,,-

~.

........

. .o"'~~-

~,~

,

'Z

ocr'

:
,
10":

/.

//

-/

I·' 0

~
~

'"

100

f ,
11

11

~
I

,

~ 10-le

£

i

"

,

~

~

",~

10

§

COL.L.ECTOR-TO-ENITTER VOL.TAGE (VCE'-3V

,

~

7~ 0'

~

and Q4 vs Emitter Current.

Il

e ..~

..II

,

lor Dorlington-connpcted Transisters QJ

,

0,6

,

Fig. 4. Typical Static Forward Current - Transler Ratio

Ratio and Beta Ratio for Transistors Q,
and Q2 vs Emitter Current.

i
."

'"

AMIIIENT TEMPERATURE ITA )_·C

V

EMITTER CURRENT (IE1-mA

0,8 COLLECTOR-TO-EMITTER VOLTAGE (VCE'03V
AMBIENT TEhiPERATURE (TA1·2~·C

"

Fig.2 - Typical Collector- To-Base Cutoff Current vs
Ambient Temperatur. lor Each Transistor •

COLLECTOR-lO-EMITTER VOLTAGE (VCEI-3V
AMBIENl TEMPERATURE (TA)- 2'·C

100

,,
92'5-23111

I

'000

ENITTER CURRENT (IE)-mA

Fig. 3 _ Typical Static Forward Current- Transfer

/"/
~/V

""1,

./

~:;

.,

80

:V

"-

§: ~OOO

I

01$'-$'//
'/

10' :

.......

V

7000

Vf

;;;:~

,0'

0

O~

".,..J.
~-

,0.:

,

'0

1.1

~
':\.~

....:",c.fb

~9'~Y;
,,0'

10'1

.The collector of each ttanatator of the CA30lS and CA3018A
Is isolated from the substrate by an Inteifal diode. The

(VCEr!V

,
!
,

. . . . . . . . . +26S o r

from caie for 10 seconds max.

[NITTER CURRENT II 100

10':

substrate (tenninal 10) must be connected to the most ne8clive point in the external circuit
maintain i.olation between tran.i.tors and to provide for normal tran.istor action.

i

1. 5ch.mafic Diagram for CAJOr8 and CAJOJ8A

STATIC CHARACTERISTICS

The {ollowlna; ratings apply {or eacb tranliltor in the device:
CA30la
CA3018A
Collector-te-Emitter Voltaa;!!, VCEO' 15
15
V
Collector-to-Baae VoUap, VCBO •• 20
30
V
Collector-to-Substrate Valts,e, VCIO • 20
40
V
Emitter-to-Saae Volta,e, VEBO •••
5
5
V
Colloctor Current, Ie .......... 50
50
mA

• General un in signal proeeninlJ syltems in DC
through VHF ranIJe

~~;E~;T~~;:~R~~~~~~~:lov2~~6AO!

3

suaSTRATE

CA3018
CA3018A
Power DIlBipeUon. P:
Anyone tranli6tor • . . . . • • . •
300
300
mW
Total packaa;e . • . • . • . . . . • .
450
450
mW
Derate at 5 mW;oC for TA >S50C
Temperature Range:
Operating. • . . . . • . . • • . • •• -55 to + 125 -55 to + 125°C

well suited to a wide yariety of applications in low-

120

'toil

7

Maldmum Ratings, Absolut.-Maxlmum Valu .. , ot T ... ·2SOC

The transistors of the CA3018 and the CA3018A are

•

L

~)

• Matched monolithic general purpose translston

0.•

-.

"

'"

"

100

"

Fig. 7 - Typical Collector- To-Emmlter CuJoIl Current vs
Ambient Temperature (or Each Transistor.

-~

-2'
ANOIENT TEMPERATURE ITA)-·C

92C5-23119

F;g. 5 - Typical Static Base-fo-Emitter Voltage
Characteristic and Input Off... e' Voltage lor
Q, and Q2 vs Emitter Current.

F;g. 6 - Typical Base. To-Emitt.r Voltage Chorocteristlc
for Each Transistor vs Ambient remperatur.

_____________________________________________________________________ 87

CA3018, CA3018A
CluJracleristics apply for each transislor in lhe CA3018 and CA30l8A as specified.

COI..LECTOR-TO-EMITTER VOLTAGE IVCE).3Vt:t:l

>

E

ELECTRICAL
CHARACTERISTICS
at TA • 25°C

CA30la
LIMITS

SYMBOLS SPECIAL TEST CONDITIONS
Min.

STATIC CHARACTERISTICS
Collector-Cutolf Current

ICBO

Collector·Cutoff Current

Typ.

CA3018A
LIMITS

CHARAC·
TERISTiCS
CURVES

Unils

Ma••

Min.

T".

Mall.

100

0.002

80

See Curve

4

I

r---Fi.

.\11\"

VCB,IOY.IE,O

-

ICED

VCE.lOY·IB'O

-

SeeCulVe

5

ICEOD

VCE,IOY,IB'O

-

-

-

-

VIBR~ED

IC~lIlA,IB=O

IS

21

-

IS

28

VIBRiC80 IC,III-

11.&

1/

~~

c!:'·5
W4

1/
j;

<,11.4

VI-./

"
66,
" 'elO
EMITTER CURRENT 'Ie)-mA

0.,

M

TemperatlleCoefficienl:
Malnilude oIlnpul·Offset Yo_

~BE"VBEJ
M

1.60
1.50

- -

4.1

-

mv/oc

10

-

10

-

JJ.V/oc

-

1.16
IJ2

-

VCE,,3V,IE=iIllA

-

1.4

VCC=t6V,VEE=-6V,
ICI,ICI·lmA

-

10

IE'llhA

'E= lmA

-

-

1.10

-

SlCS-luel

Fig.9 • Typical Static Inplll Voltage Choraelerlstlc

'01'

Emitter tu"ent

1.46
1.32

--

VCE,3V

V

V

O.,lInglon P.i, (03 and 04)vs

-

-

VBED
(V9-I)

-

5,8

mV

2

O.8B

·1.9

.1.9

VCE·3V,IE·I.A

-

5

0.18

-

liT

jt>VBE~

-

VCE·3V,IE,lmA

."

Fig.S - Typical OH•• , Voltage ClUIfGct.tlst/e vs

i

Input DffsetVollaae

50

TEMf'ERATI.ItE IT,tJ-"C

6

mv/oc

COLLECTQR-TQ-EMITTlR VOlTAGE (IICE)-311

v'

9

4

_

~

0

e

~

~

~

AMBIENT TEMPERATURf ITAI--C

~

HeS-n.,.,

Fig. 70 - Typical Static Input Voltage CharGcter;stlc lor
Darlington Pair (Q3 and Q4) vs
Ambient Temperature.

COLLECTOR-TO-EMITTE" VOLTAGE IVell-sv

'0

r

SOURCE RESISTANCE (~sl·5004
AMBIENT TEMPERATURE ,TAI'25-<:

"

,I,..,

,~

j.--

,

~~

.,,,
, . ..
. . .., ·tr
....,,~

10

o.~

yf

~\,,'

COLL.ECTOR CURRENT (leI-iliA

.,CI-U7.4

FI,.lJ(G). Noise Figure vs CoUector Current,

..
i
i

SOURCE REStaTANCE IRsl' looo.a
AMIIENT TEMP£RA'URE: (TAI'2PC

.l

..#

III

,

V

,

. ..

.O'~

~o~

III

I• ro
i

1.1

COLLECTOR-TO-EM'TT" YOLT"E IYco""

,,I]

~

~

~

V:L

I.---

,

~
. ..

COLLECTOfII CURRENT IIcl-III"

.2eS-21115

30 COLLECTOR-TO-EMITTER VOLTAGE (VCE"3V
SOURCE RESISTANCE IRS'-IOUI
AMBIENT TEMPERATURE CTAI'2!I'"C

-l.~/V

.
"
"

,

0
0.01

1,...Y

I

"

I~

~~

;c.~<<'J'

V
,

- .,
I-

l/

,~./
~

V
J---V
,

0.'
COL.LECTOR CURRENT IIcl-mA

. ..
nel-I!?88

Fig.l J(c) - Ho;se Figure vs Colleclor Curre""

RS = 10 Kn.
Flg.He"), Hoi •• Figure VI Collector Current, RS = J KO.
soon,
88 ________________________________________________________________
RS=

CA3018, CA3018A
ELECTRICAL CHARACTERISTICS. (COHT'D)

~. COLLECTOR-TO-EMITTER VOLTAGE tVCE'-]V

OYNAMIC CHARACTERISTICS

CA30IBA

3.25

3.25

1,1 KHz,VCp3V,IC.10!I-'
ScuCllesistance"lKO

NF

Lor Flequency Noise Fialll'l

CA30IB

oil

I

dB

j·
0,

~

ShOft·Circuit Input Impedance
Open·Circuit Output

I

'I,
~ie

Impedan~

Open·Circuit Revelse
Vollaae-Transfer Ratio

'.

f=lkHz,V CE =3V,I C=lmA

I

hIe

1\0

1\0
3.5

3.5

KO

12

15.6

15.6

"",0

12

l.SxllH

-

~

12

~

12

l.SxUt4

I

0.01

1

'" "',

H-

F=f '00

V

/ _",.
K4~

~

,;-

~

hr,·188.IO-41111It1A,_
hOl·I~6 ... mhll

-

,
,

··,

III

'.,·000
h,.·21Ul

' - t--.....

I\lb)

Low·FfeQUflocy,SmlII·$iana l
Equivalent-tircui!
Charactefistics:
Foard Currenl-Transfer Ralio

fREOUEptCYI!l'lkHI
AMBIENT TEMPERATLJlEiTAlo2S'C

I-

.,. , ., ,
0,1

I

N,
, ,1,

.

COLLECTOR CUARENT (lcl-mA

Admiltance Characte!istics:
FOfWard Transfer Admittaru

I

VI,

InlXll Admittance

V"

Output Admittance

V",

Reverse Transfer Admittance

V"

-

f =lMHz,V CE =3V ,IC:lmA

3Hl.5

31,;1.5

mmho

13

O.3.jO.04

O.3ljO.04

mrj,o

\4

O.OOltjO.03

mmho

IS

$eeCl,lve

mmho

16

11

O.OOl+jO.03

I

-

~Curve

Gain·Bal1iwidth Pralucl

IT

VCE =3V,I C=3mA

sao

MHz

Emitter·lo-Base Capacitance

VES =3V,I E=O

0.6

0.6

pF

ColleclOf·lo-Base Capacitance

eEa
eea

Vca=.3'v,lc=O

o.sa

o.sa

pF

CollectOf·to-SLbstrate Capacitance

eel

VCI =3V,I C"O

2.8

2.a

pF

300

300

sao

~~=:':-~~UJI:Afu~EUNA~~·~NPUT

.
:Ii '"

COLLECTOFI-TO-EMITTER VOLTAGE (VCE)']II
COLLECTOR CURRENT (IC"lmA

"'

AMSIENT TEMPERATURE iTAJ.2S 0 c IN
COLLECTOR-TO-EMITTER VOLTAGE (VCEI'311
COLLECTOl' CURRENT iICI'1 mA
+-++l+-+--1

~

~~ '1-~+4~-+-+~+-+~~~~

t---

!,~J 4r-+-~++~+-++l+-~-++~~~'~~

g~ "r-+-+H1--~+-I4+~--r++++4~

no

~~-~

~~=-~':~Jf:Ai~~I(Tt:I~~~·rT
~g~t:g:-~~:~T;~:C~!~GE lVeEI·]V -l-t+il-+-I

~

~~
~120
§f 10
~~ -<0

6

Fig. 12 - ForwarJ Current· Transf.r Rafio (hie)' ShorfCircuit Input ImpeJance (hie)' Open.Circuit
Output ImpeJance (ltoe )' and Open·Circuit
Revern Voltage.Transf.r Ratio (hr.)
VI Collector Current

h

i~ 2r-+-~-++~+-++4+-+-+-h~-+--1

r- !J.

."

I

,

...

§~~ '~~~~44~~~~~~~
/
~

.........

,

0

fREQUENCY if)-MHz

,

"

2

I

Fig. '3 - Forward Transfer Admittance (Yf.)

=~~-~~I~~~~A~~~~~~:t.~~o~PUT

~

Q,.

~E::ATL~A:T~~~~ENC1ES

0

'"

"'"

~!-o.

-I

~(5
t!

-,2

,

0.1

100

.,,

,

., ,

...

V
I
10
FREOUENCYill-MHr

Fig.J5 - Output Admittance (Y oe)

COLLECTOR-TO-ENITTER \lOLTAGf (\lCEl o3\1
AMBIENT TEMPERATUftE ITAJo2~'C

I I

1tI"

~i
Iri -,

II

10

Fig.14 -Input Admittance (Y ie )

COLLECTOR-TO-EMITTER 'v'OLTAGE (VCEI']II
COLLECTOR CORRENT (Icl'l
I

~iI

468

FR(OVENCY lIl-MHz

-:-

I
II

Ie],,, '

J'!

,[:V·.': "11:[:.

.1,,'·'" '1":'1,":
I.,.·'~"I

•.. ,• •i""Ht.~.

10
FREOUENCY{f}-MHr

COLL.ECTOR CURRENT ('Icl-mA ucs-nnz

Fig, 16 - Reverse Transfer Ae/mittonce (Y re)

Fig. 17 • Typical Gain·Brlne/wiJth Proe/uct (IT)

vs

Collector Current

___________________________________________________________________ 89

CA3019

Ultra-Fast Low-Capacitance
Matched Diodes

Features:
•
•
•
•

For Applications in Communications
and Switching Systems
The RCA-CA3019 consists of six ultra-fast,
low capacitance diodes on a common monolithic substrate. Integrated circuit construction assures excellent static and dynamic
matching of the diodes, making the array extremely useful for a wide variety of applications in communication and switching
systems.
Four of the diodes are internally connected
as a "quad" and two are independently accessible. The substrate is internally connected
to the 10-Iead TO-5-style case.
For applications such as balanced modulators
or ring modulators where capacitive balance
is important, the substrate should be returned
to a DC potential which is significantly more
negative (with respect to the active diodes)
than the peak signal applied.

Excellent Diode Match
Low Leakage Current
Low Pedestal Voltage when Gating
Companion Application Note, ICAN-5299:
"Application of the RCA-CA3019 Inte·
grated-Circu it Diode Array"

Applications:
• Analog Switch
• Modulator
• Diode Gate for
• Mixer
Chopper-Modulator
• Balanced Modulator
Applications
92CS·14254

·Connect to most negative circuit potential.

Absolute-Maximum Ratings:
DISSIPATION:

Fig. 1 - Schematic Diagram.

Anyone diode unit .

Total for device .
TEMPERATURE RANGE:
Storage .
Operating
DC Forward Current, IF
Peak Recurrent Forward
Current, If
Peak Forward Surge
Current, If ,(surge)

ELECTRICAL CHARACTERISTICS, at TA = 25°C

20 max.
120 max.

mW
mW

-65 to +200 °C
-55 to +125 °c
25

rnA

100

rnA

100

rnA

VOLTAGE: See Table

Characteristics Apply for Each Diode Unit, Unless Otherwise Specified

LI"""TS
CHARACTERISTICS

SPECIAL TEST CONDITIONS

TYPE CA3019
Min.

DC Forward Voltage Drop

DC Forward Current (I F) = 1 mA

-

Typ.

Max. Units

0.73 0.78

V

DC Reverse Breakdown Voltage DC Reverse Current (I R) = -10 IlA

4

6

-

V

DC Reverse Breakdown Vol tag
Between any Diode Unit and
Substrate

DC Reverse Current (IR)= -101lA

25

80

-

V

DC Reverse (Leakage) Current

DC Reverse Voltage (VR) =-4 V

-

0.0055

10

IlA

DC Reverse (Leakage) Current
Between any Diode Unit and
Substrate

DC Reverse Voltage (VR) = -4 V

-

0.010

10

IlA

Magnitude of Diode Offset
Voltage (Difference in DC
Forward Voltage Drops of
any Two Diode Units)

DC Forward Current (I F)= 1 mA

-

1

Frequency (f) = 1 MHz
DC Reverse Voltage (VR) = -2V

-

1.8

-

pF

-

4.4

-

pF

2.7

-

10

-

mV

Single Diode Capacitance

Diode Q·uad-to-Substrate
Capacitance

TERM.
1
2
3
4
5
6
7

5

mV

Frequency (f) = 1 MHz
DC Reverse Voltage (VR)
between Terminal 2,5,6, or 8 of
Diode Quad and Terminal 7
(Substrate) = -2 V
Terminal 2 or 6 to Terminal 7
Terminal 5 or 8 to Terminal 7

Series Gate Switching
Pedestal Voltage

Absolute-Maximum Voltage Limits:

8
9
10
CASE

VOLTAGE
LIMITS
CONDITIONS
POS. TERM. VOLT.
NEG.
-3
+12
7
-6
-3
+12
-6
7
-3
+12
-6
7
-3
+12
-6
7
-3
+12
-6
7
-3
+12
-6
7
1,2,
-18
3,6,
0
0
8
-3
+12
-6
7
-3
+12
-6
7
NO CONNECTION
INTERNALL Y CONNECTED
TO TERMINAL 7
DO NOT GROUND

pF

90 ________________________________________________________________

CA3019
DC RE\lERSE VOL.TS IVRI ACROSS DIOOE"-'"

DC FORWARD CURRENT (IF) "ImA

~

AM81ENT TEMPERATURE
fREQUENCY (Fl_iMHr

TA "25"C

• '0

I"

I

~0.9

I
~ZO

~

~ 0.8

n.

-«.I

-1!i
"

'"

1!i

Fig. 2 - DC forward voltage drop (any diode) as
a function of temperature.

AMBIENT TEMPERATURE (TAl" 25"C
FREQUENCY (f) " I MHz

I

2

;,

-Z!)

0

Z!)

~

,

1!)

,

,

DC RE\lERSE VOL.TS {\IRI ACROSS DIODE

AAotIIENT TEIIWERATURE tTA1-"C

AMBIENT TEW'ERAoTURE (T",I-"C

Fig. 3 - Reverse (leakage) current (any diode)
as a function of temperature.

Fig. 4 - Diode capacitance (any diode) as a function
of reverse voltage.

AMBIENT nMPERATURE (TAl" 2!)"C
FREQUENCY (f) • I MHI

..

DC !tfVERS£ YOUS (VRI BETWEEN TERMINAL. 2 OR £,
AND SUBSTRATE (TERMINAL. 1'1

Fig. 5 - Diode quad*to-substrate capacitance as a
function of reverse Voltage.

I

2

:5

4

DC REVERSE VOL.TS IVRI BETWEEN TERMINAL.S 5 OR 8
AND SUBSTRATE {TERMINAL TI

Fig. 6 - Diode quad-to-substrate capacitance as a
function of reverse voltage.

Fig. 7 - Series gate switching test setup.

____________________________________________________________

~

_______ 91

CA3020,CA3020A

Multi-Purpose Wideband
Power Amplifiers

SCHEMATIC DIAGRAM FOR CA3020 AND CA3020A

Far, Miliary, Industrial,
and Commercial Eqaipmeat
at Freaueacies up to 8 MHz

The RCA-CA3020 and CA3020A. are Integrated-Cucuit.
Multistage. Multipurpose, Wide--Band Power Amplifiers
on a single monolithic silicon chip. They employ a
highly versatile and stable direcl..coupled circuit configuration featuring wide frequency range, high voltage
and power gain. and high power output. These features
plus inherefat stability over a wide temperature range

The CA3020' and CA3020A are particularly suited for
service as Class B power amplifiers. The CA3020A
can provide a maximum power output of 1 watl from a
12-volt DC supply with a typical power gain of 75 dB.
The CAJ020 provides 0.5 watt power output from a
9-volt supply with the same power gain.

make the CA3020 and CA3020A extremely useful for a
wide variety of applications in military, industrial, and
commercial equipment.

'"
0,

These types are supplied in hermetically sealed, TO·5
style 12·lead packages.

ABSOLUTE-MAXIMUM RATINGS:

DI~:PT"::O~~OC •.••...•.• ~I~~~~~ ~~~~ ~I~~ •.••..

Fig.l

.w~~~ ~~~~ ~I~~ . . . . . . ,

1 WIAITC = 250C
Above TA = 25°C ..•••....••.. derate linearly 6.7 mWI'C At TC = 25°C to TC
Above TC

2W
= 55°C . . . . . . . . . 2 W

= 55°C .. derate linearly 16.7mW/oC

TEMPERATURE RANGE:
Operating ..••••••..........•••••••••... -55°C to +125°C
Storage. . . . • • • . . • • • • . . • • • • . . . • • . . • . • . . . .6SoC to +iSOoC

The resistlllnce ... Blues included on the schematic dia.
gllllm have been supplied as III convenience to assist
Equipment MllinufactUTers
in optimizing the selection
or "Dutbollird" components of equipment designs. The
values
shown may very as much illS ± 30,.•.
RCA reserves the right to make any changes in the Re.
sistance Values provided such changes do not ad.
versely affect the published performance characteristics of the device.

LEAD TEMPERATURE (During Soldering):
AI distance 1/16 ± 1/32 inch (1.59 ± O.79mm)
from case for 10 seconds max. . . . . . . . . . . . . . . . • • • . . . . . +26S oC
MAXIMUM VOLTAGE RATINGS .t T A = 2S·C
The following chart gives the range of voltages which can be applied to the terminals
listed vertically with respect to the terminals listed horizontally. For example, the
voltage range of the vertical terminal 1 with respect to terminal 12 is 0 to +10 volts.
TERMINAL
No.

I

2

3

~

5

6

7

9

10

II

2

3

5

7

Note 3

9

II

Note I: Tbis voltage is established by the maximum current
rating.

2:

~~: ~~I\~;S s~f~fr ~:::o~t r:~t~:r r;::::~drst.o ~~r~::;

into terminal No.9 sbould not be exceeded and the
total device dissipation should not be exceeded.
Note 3: Terminal No.8 may be connected to terminals Nos.9,
11, or 12.

• Wide frequency range -Up to 8 MHZ with resistive loads

-2
·2

3

+18/+25
0

4

Nole 2

'3

5

300

'3

Nole 2

6

300

+18/+25
0

7

·

Note 3
0

8

"0
0

Note 1 +10/+12
0
0

9

20

• Lamp.control amplifiers

10

1

• Power multi vibrator

11

20

20

• High power gain ................ 75d" typo
.Single pOwer supply for class B operation
with transformer -CA3020 .................. 3 to 9V
C~OWA

................. 3hl~

- Built·in temperature·trad:ing 'flIlfage
regulator provides sla"l. operation over
.55°C to +125D C temperature range

300

APPLICATIONS
• AF power amplifiers for porto "Ie and fixed sound and
communications systems
• Servo·control amplifiers
-Wide.band linear mixers
300

• Video power amplifiers
- Tronsmission·line driver amplifiers (balanced and
unbalanced)
• Fan·in and fan-out amplifiers for computer logic
circuits
-Motor·control amplifiers

'10
0

.

REF.
SUBTRATE

12

• High power output· clan B aillplifi., -CA3020 ...• 0.5 watt typo of VCC = + 9V
CA3020A ••. 1.0 watt typo at VCC = + 12V

2

·

10

'g~T

-2
·2

.'

8

I'N

rnA

FEATURES

1

0
·18}-25

6

TERM·
INAL
No.

-10
0

+18.'+25
0

4

12

. . · · ·
·
.
. · · · · · ·
. · ·· ·· · · .
· .· · · · ·
· · .
· · ·
• 0
-3
·10/·12 Notel

1

Note

8

MAXIMUM
CURRENT RATINGS

• Power switches
• Companion Application No"', ICAH 5766 "Application
of CA3020 ond CA3020A Integrated Circuit Multi.
purpose Wide.Band Power A...pUflen!':

12

* Voltages are not normally applied between these tenninals.
Voltages appearing between these tenninals will be safe if
the specified limits between all other tenninals are not
exceeded.
.. Higher value is (or CA3020A.

92 __________________________________~-----------------------------

CA3020, CA3020A
ELECTRICAL. CHARACTERISTICS AT T A = 2SoC

CHARACTERI STI CS

SYMBOLS

Collecill-to-Emitter
Breakdown Voltage, 06 & Q7
aiiO rnA
CollecllX-lo-Emitier

TEST CaNOl TI ONS
CI RCUI T
DC
ANa
SUPPLY
PROCEDURE
VOLTAGE
FIG.
VC CI
VCC1

V1BR)CER

BreakdowrJ Voltage, Q1
at 0.1 rnA

LIMITS
CA30l0
MIN.

VIBRICEO

MAX.

MIN.

TYP.

UNITS
MAX.

18

15

V

10

10

V

2,

14 IDLE
I)IOLE
14PK

Idle Cutrents, 06 &Q7

TYP.

LIMITS
CAl010A

4

9.0

1.0

4

9.0

1.0

14 CUTOFF
I) CUTOFF

4

9.0

1.0

1.0

rnA

CUf/enl Drain
Tolal Currenl Drain

ICCI

4

9.0

9.0

6.3

9.4

11.5

6.3

9.4

11.5

rnA

ICCI +
ICC1

4

9.0

9.0

8.0

21.5

35.0

14.0

21.5

30.0

rnA

Differential Amplifier
Input Terminal Voltages

V1
V3

4

9.0

1.0

Lli

1.11

Regulator Terminal Voltage

V11

4

9.0

1.0

1.35

1.35

Q, Cutoff (leakage) Currents:
Collector·to-Emiller

ICEO

Peak Output Currents,
Cutoff Currents,

Q6& Q)
Oiflerelial Amplifier

5.5
180

Collector-la-Base
Forward CUlrenlTransfer
Ralio, QI al3 rnA

lEBO
ICBO
hFE!

6.0

Bandwidth at ·3 dB Point

BW

6.0
6.0
9.0
9.0

6.0
6.0
9.0
11.0
9.0
11.0

35'

1000

30

POIMAX)

6

Sensitivity for POUT =400 mW

'IN
'IN

6
6

9.0
9.0

Input Resistance-·Terminal 3 to Groofld

RIN3

9

6.0

6.0

JlJIlclioo·to·Case
Thelmal ResistaRce

&J.C

-

-

-

fOI

POUT = 800 mW

100
400

75

30

8
300'

100
400
800

550a

vCC2

V
100
0.1
0.1

-

0.1
0.1

,_M',----.VCCI

V

100

Maximum Power Output

Sensitivity

rnA

1.0

10.0
3.0
3.0

Emitter·la-Base

rnA
a. Coliector·tCHmitt... br..kdown voluge lOs &: 0 7 1 circuit

I]PK

Q6 &Q)

5.5
140

"A

75
MHz

8
300'

rnW

550'
lOOOb

55

b. TVpiul audio amplifier cin:uit utiliZing

tn.

I.:A3U20 or
CA3020A u an audio prumplifi.r and d_ B pow... •
ampUfi.,

mY

SOb

100

Fig.2

mV

n

1000
60

60

oCIW
TYPICAL TRANSFER CHARACTERISTICS

a Rec" 1300
bR CC "2000

TYPICAL PERFORMANCE DATA
An External Radiator is Recommended for High Ambient Temperature O".,a,lon

CHARACTERISTICS
Power Supply Vollage

SYMBOLS

CA3020

CA3020A

UNITS

VCC
VCC2
-I eel

9.0
9.0

9.0
11.0

V

IS
24

rnA
rnA

a. Teat Setup

leC2

IS
24

Dill. Ampl.
Maximum Signal Cunent
Output Ampl.

ICC
leC1

16
115

16.6
140

Maximum Power Oulput al THO" 10%

Po

550

1000

mW

Sensitivity

elN

35

45

mV

Power Gain

Gp

75

75

dB

Input Resistance

RIN

55

55

kD

Efficiency

T]

45

55

%

Signal-lo-Noise Ratio

SIN

70

66

dB

Zelo Signal Current

Dill. Ampl.
Output Ampl.

THO at 150 mW I,vel
Test Sigllal Frequency from 6000 Generator
Equivalent Coliector-to·Coliector Load Resistance

Ree

3.1

3.3

%

1000

1000

Hz

130

200

D

-2~

~

2~

0
0

-2:5

I4·0N'+ Il'ONOIfFERENTIAL AMPLIFIER

INPUTIroULLIVOLTStV23'

92CS-('ZZG

b. Choracteristic:. with R 10 .hort.d out

Flg.J

_____________________________________________________________________ 93

CA3020, CA3020A
STATIC CURRENT AND VOLTAGE TEST CIRCUIT

CURRENTS OR
VOLTAGES

CURRENTS OR
VOLTAGES

SI

52

open

open

open

open

open

open

SI

52

'4-'DLE

open

open

'CCI

'HOLE

open

open

'Ce2

'4-PEAK

open

close

V2 ,

close

open

V3

open

open

'7.PEAK

close

open

VII

open

open

open

ctose

'4--CUTOFF
'7-CI,;TOFF

Fig.4
MEASUREMENT OF BANDWIDTH AT -3 dB POINTS

PROCEDURES:

1. Apply desIred value of V CC

and

Vee

2.

:~~Y (r~:f2l

3.

~:fe~~~~~e v~~~~~ting value of e OUT in

4.

input signal

add

adjust

CII.

fJr

T elt Setup

e IN

dB

~a~~Jin:ndt-~;~~~J :::~~::~r~s k:~~!~ga~l/ib~f:;tin~;~
at whi(.h e OUT decreases 3 dB below reference value.

t!>OO
Flg.S
MEASUREMENTS OF ZERO.SIGNAL DC CURRENT DRAIN, MAXIMUM·SIGNAL DC CURRENT DRAIN,
MAXIMUM POWER OUTPUT, CIRCUIT EFFICIENCY, SENSITIVITY, AND TRANSDUCER POWER GAIN
Max~mum.Signal
DC Current Drain, Moximum Power
Output, Circuit Efficiency, Sensitivity, and Transducer
Power Gain

1. Apply desired value of Vee

and Vce

and adjust

e IN to the value at which thelTotal HarJonic Distortion in

the

output

of the

amplifier

=

10"!.

2. Record resulting value of ICC ,and ICC in rnA as
Maxim.um-Signal DC Current D~ain
2
3. Determine resulting amplifier power output in watts
50

and record as Maximum Power Output (POUT)
4. Calculate Circuit Efficiency
in "!~ as follows:

PROCEDURES:

25

-25

Fig.,

6. Calculate Transducer Power Gain (Gp ) in dB as

Zero·Signal DC Current Drain

follows:.

1. ~;:~~ g~sired Value of Vee 1 and V ee2 and reduce

~:~o:~o.;~:~~ii';,ge ~~lr~:~t ~~ai!~e I

0

DIFFERENTIAL AMPLIFIER INPUTMILLIVOLTS(V2~

V eel1cc 1+V CC 2 Iec 2
where POUT is in watts, V CC and V CC
are in
volts, and ICC
and ICC are l in ampere1s.
S. Record value olt eIN in mif (rms) required in Step 1
as
Sensitivity (e IN )

'T: Pooh_Poll Outpull'onof.,,,,.,; load
R... Uonu Of~l .hould b••• I.--+

'20

~ 40

~~~,:ftj:::j::::;:

+= ':: :;:::: Jr~

;Tr

.

~:;::

n+ iii- ~;:::::

o

DC SUPPl.'I" VOLTS (Veel

Flg.3(b)

"

"

20

Itt
oc SUPPLY

VOL.TS !vcc!

Flg.3(c)

"

AMBIENT TEMPERATURE (TA)-·C
tlC5-14!88

Flg,3td)

96 ____________________________________________________________________

CA3021, CA3022, CA3023
ELECTRICAL CHARACTERISTICS, at TA" 25°

c, Vee'" +6V,

unless otherwise specified

TEST CONDITIONS

CHARACTERISTIC

FEEDBACK
TEST SETUP RESISTANCE
CAW11
FRE·
SYMBOl
AND
(R~) BETWEEN
(TA5119)
PROCEDURE TERMINALS QUENCY
I
.
3 AND 7

11

Fig.
Device
Dissipation

Quiescent
Output
Voltage
AGC Source
Current

Voltage Gain

Bandwidth at
·3 dB Point

Input
ItlputResistance
Impedance
CompoInpul
nellis
Capaci·
tance
Output
Resistance

Noise Figure

MHz

ro

1

PT

ro

-

ro

-

39k
1

Vo

-

10k

-

4.7k
4

IAGC

VAGC =+6V

5

A

BW

5

7

RIN

CIN

7

8

ROUT

9

NF

Maximum
Output Voltage
(RMS Value)

AGC

10

5

vou!

SOURCE CURRENT

I

4

-

-

-

-

-

1.1

-

-

-

0.8

560k

0.5

50

56

39k

0.8

40

46

39k

1.5

10k

3

- - - - -

18k

5

4.7k

10

39k
10k

-

4.7k

-

39k

1

10k

5

4.7k

10

CAW11
(TA5136)

TYPICAL
CHARAC·
UNITS TERISTIC
CURVE

CA3013
(TA5118)

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. UnHs

0.8

1.4

- - - 4000
- - -

39k

I

-

10k

5

4.7k

10

- - -

39k

1

-

10k

5

- - -

11

300

4.7k

10

39k

1

-

10k

1

4.7k

I

- - -

-

5

-

-

10

-

-

4.1

33

1
AGC Range

TEST SETUP FOR MEASUREMENT OF AGC

LIMJTS

39k

I

-

10k

5

4.7k

10

- -

0.6

-

5 11.5 14

-

- -

- -

14

35

48

rnW

-

- -

V

-

8

-

-

-

-

- - 1.9 - - - - - - - 0.8 - - - - - - - - - 50 57 - 40 44 - - - - - 50
- - - - 40
- - - - - 3 7.5 - - - - - 10
- - - - - - 1300 - - - - - - - - - 18 - - - - - - - - - - - 110 - - - - - - - 8.5 - - 4.4 8,5 - - - - - - - - 33 - - - - - - - - - - - 0.7 - - - - - -

3a d

rnW

3b.d
3c,d

-

V

0.8

-

rnA

Fig."

-

dB

6a

- -

dB

6a,d

dB

6b

dB

6b,d

dB

6c

dB

6c,d

MHz

6a

MHz

6b

MHz

6c

- - 13
- - 100 - - -

pF

8,5

dB

- - -

dB

-

dB

- 0.5 -

-

(]

(]

33

TEST SETUP FOR MEASUREMENTS OF VOL TAGE·GA.IN, .3dB
BANDWIDTH, AND MAXIMUM OUTPUT VOL TAGE

v"

+6V

(]

300

6.5

IAGC IS THE CURRENT FLOWING INTO TERMINAL 2.

-

V

-

53 44 - 16
- - -

VAGC "+8V

Fi .

rnW

1.3

Vee
+6V

PROCEDURES
Voltage Gain:
(a) Set ein "0.5 mVat frequency specified, read eout Voltage Gain

'out

-

pF
pF

11

-

(]

(Al '" 20 Log IO -

Bandwidth:
ein
(al Set eout to a ccnvenienlreference voltage at f " 100 kHz and
record corresponding value of ein.

~~~cr~~~~I~~~~~j:~:' keeping ein constant until eout drops
Fig.5

(]

dB

VOL T AGE GAIN VS FREQUEHCY FOR CA3021

-

dB

AM81ENT TEMPERATURE (TA)"2~·C
DC SUPPLY VDLTS(Vcc1" +6
TERMINALS NO.IO,II,ANO 12: CONNECTED TO GROUND

70

-

dB
V rms

K
50

39K

;- 40

-

V(rrns)

~

60 FEEDBACKBESI! ANC

i

LOK

g
•

V(rrns)

5.6K

30

~g. '0
LO

,

•

L

6

a 10

FREQUENCY ( f ] - MHz

Fig.6(a)

VOL TAGE GAIN VS TEMPERATURE FOR CA3021.
VOL TAGE GAIN VS FREQUENCY FOR CA3022

CA3022, AN 0 CA30 23

VOL TAGE GAIN VS FREQUENCY FOR CA3023
A'-IBIENT TEMPERATURE (TAl' 2:5"C
DC SUPPLY VOLTS (Vccl "+6
TERMINALS No.IO,II, AND 12: CONNECTED TO GROUND

FEED8ACK RESISTANCE (RRl
CONNECTED BETWEEN TERMINALS No 3 ANO 1

FEED ACK RE

1ST NCE

8K

, L-l--i-+-

4.?

'"

2K

I--W-

~

1
•

~g
2

4

6 e 10

FRECUENCY(' 1- MHz

Fig.6(b)

4 6 8 100

4

6

8 I

4

6

FRECUENCY (II - MHz

Flg.6(c}

TYPE
C.3021 39
CA302:2
CA3023 4.7

.0

10

'0

"z"
~

LK

560

6 1:1 I

*~

FEEDBACI( RESISTANCE (R~) CONNECTED
BETWEEN TERMINALS No.3 AND No.1

70
60

OC SUPPLY VOLTS (Vcd" + 6
TERMINALS NO,IO,)I, AND 12 CONNECTED
TO GROUNO

810

40

3~

-75

-!'>Q

-25

"

50

100

IZi

Fig.6(d)

_________________________________________________________________ 97

CA3021, CA3022, CA3023
TEST SETUP FOR MEASUREMENT OF INPUT·

TEST SETUP FOR MEASUREMENT OF OUTPUT

IMPEDANCE COMPONENTS

RESIST ANeE

..

,

Vee

..

TEST SETUP FOR MEASUREMENT OF NOISE FIGURE

,

'cc

leur

I-MHZ
TANK CIRCUIT

..,

Vee'

j

• ein

:~

CA3021

!9

CA3022

10

CA3023 ".7

£ 10 mV
Fig.7
Flg.S

CA3021· Aj3 ::: 39 kD

TEST SETUP FOR MEA.SUREMENT OF AGe RAHGE

CA3022· Rj3 '" 10 kD

CA3023 - Rj3 = 4.7 kO
Fig.9

+6V .O.TV

A WITH 5 IN POSITION 1
AGe RANGE" 20 LOG lO A WITH S IN POSITION 2
fA = VOLTAGE GAIN)

~
MHz

CA3021

1

CA3D22

5

CA3023

10

Fig.IO

98 ______________________________________________________________

CA3026,CA3054

Dual Independent
Differential Amplifiers

For Low-Power Applications
at Frequencies from DC

The CA3026 and CA3fli4 each consists of two independent

to 120 MHz

differential amplifiers with associated constant-eurrent
transistors on a common monolithic substrate. The six
n:p-a transistors which comprise the amplifiers are
general purpose devices which exhibit low 1If noise and
a value of IT in excess of 300 MHz. These features

FEATURES
II

Two differential amplifiers on a common lubstrate

• Independently aCCII5Iibl. inputs and outputs
• Maximum input offset yoltage .- t 5 mV
• Full militory t.mp.rature range capability ••• 5so C to
+12SoC

• Limit.d temperatura range __ ooe to 85a C for CA30s.c

APPLICATIONS

• The CA3054 is available in a sealed-junction
Beam-Lead version (CA3054LI_ For further
information see File No_ 515, "Beam-Lead
Devices for Hybrid Circuit Applications"_

• DUGI sense amplifier.
• Dual Schmitt higgen

make thcCA.1006andCA:l054 useful from de to 120 MUz.
Bias and load resistors have been omitted to provide
maximum application ncxibility.
The monolithic construction of the CA3026 and CA:J054

• Multifunction combination,·· RF 'Mileer, O,cillator;
Converter/IF
• Product detecta",

• CA3026-Hermetic 12-lead TO-5 package

providcsciosc electrical and UK!rmal matching of the
amplifiers. This f("ature makes these devices particularly
useful in dual channel applications where matched performance of the two channels is required.

• Oaubly balanced madulaton and demadulatau

• CA3054-14-lead dual-in-lina plastic package

.IF cllnplilien (differentiol ond ar COloCode)

• Balanced quadrature detector'
• Ca,cade limite"
.Synchranau,delecta"
• Pain 01 bolanced lIIillen
• Synthesize, lIIiaen
• Bolanced (pu,h.pull) co,code alllplifiers

MAXIMUM RATINGS, ABSOLUTE-MAXIMUM VALUES, AT TA = 2SoC

Fig.la - Schematic Diaglam (01 CA3026.

The following rsUngB apply fot each transistor in the device:

power Dissipation. P:
CAl026
CA305<4
Aty ODe trans ist.e.- . .• •• 300
•• • •
300
Total packa,e .•••.••• 600
.••.
750
ForTA > 55°C •••• Derate at.5....
6.67
Temperature Ran,e:
.
Operating .••••.•• • ... ,. -55 t.o + 125
Storage ...••.•• ' ••• , .• ~5 t.o + 150

mW
mW
mW/OC

Collect.or-t.o-Emitter Voltage, VCEO' • • • • • ••
CollectOl'-to-Base Voltage, VCBO' • • • • • • • ••

°c

°c

15

V

20

V

Collector-tOo8ubstrate Voltage. V CIO .' . • • • •.
Emitter-to-Base Voltage, V EBO ' . . •• • • • • ••

20

5

V
V

Collector Current, IC' • • • • • • • • • • . • . • • ••

50

mA

"~~.,,,

~
0,

SUI~AT(

4

Lead Temperature (During Soldering):

Fig.11l _ Schematic DiaglOm (OT CA30s4.

At distance' 1/16 ± 1/32 inch (1.59 ± 0.79mm)
. . , +265
from case for 10 seconds max.

°c

CAUTION: Substrate MUST be maintained negative with

... The colledor of e8ch transistor of the CA3026 and CA3054 Is
Isolated from the substrata by an Intell'al diode. The substrate mutt
be connected to Q voltage rdiich ia II'IOIe neBOtive than an.y collector
IJ(Jltagl! in otdilr to rJl]intain isolation between uansistoNr and provide

(or nonnal transistor action. The substrate should be maintained at
signal lAC) ground ~ JrEan8 0{ a suitable grolIIdin& capacitor, to avoid

resjEct to all collector tenninals of this deviO!. See
Maximum Voltage Ratings chart. .

undesired coupling between transistors.

TYPICAL STATIC CHARACTERISTICS
10!

EMITTER CURA[NT t1: 1.0

Maximum Voltage Ratings

The following chart gives the range of voltages which can be applied to the terminals
listed vertically with respect to the terminals listed hOrizontally. For example, the
voltage range between vertical terminal 1 t and horizootal terminal 3 t is +15 to -5
volts.

t

CA3OS",
TERMINAL No.

For CA3026jcorresponding terminals for CA3054 are vertical
terminal 2 alid horizontal tennina14.

-

13

14

I

10

II

12

eA302~

TERMINAL

No.

13

14

lOT

0
·20

II

12

.20
0

7

8

,

4

5

6

7

II

Maximum
Current Ratings

12

,

Note I

I
'5
·5

6

,

Note I

.15
·5
'20
0

'20
0

_20
0

-20
0

CA30S4
TERMINAL
No,.

CA3026
TERMINAL
N'.

"N

lOUT

rnA

rnA

0.1

13

10

14

II

50

0.1

12

50

0.1

-15

.,

0.1

·5

0.1
0
·20

_5
·5

_15

0.1

·5

_20
0

_20
0

50

0.1

_'0
0

50

0.1

-15

12

2~

-I

.,

·5

00

75

,

100

AMBIENT TEMPERATURE ITA I-ec -

For CA3054: use data from

•

ric to 850C only

Flg.2 - Co".ctw-fo-base cufollc.,,.nf ys amhlentfemp.rotu,. 10, e"clt fran.isfor.

...

H

0.1

·5
II

·50

.

,~'~----~----~----r-----r---~

0.1

·5

II

..,

12

0.1
0.1

50

Sub·

strate

• Voltagell ore not normally apphed bet..,;{"cn these termmal~.
Volta,e8 appeann. between these tcrminals ....:ilI be sare Ir
!~~e:S:d.iried limitll bet ..... een all othe r terminals are not
Not. 1: In the CA3026 terminal No.9 iBconnecledto the emitter

:'~d ~~ re::re'::J~~~tra+~:~~r!!'i~aclage·~~i~::ei~:aO~~

appear in the volt.,e ratin, chart because It IS a compollite
charHorboththe CA3026 and the CA3054 .. Wherever an IIsterisk
ill shown in one column 9 and a ralin, II shown in the other
column 9. the alterisk should be i,nared.

• Tel'll1inal No.IO of CA3054

III

not used

:v
0.'

/.
4

6

a

I

2

a

s

10

COLLECTOR MILLIAMPERES crel

Fig.3 - Inpuf 6ios current choraderisfic vs coll.clor
current lor each fron.isfor.

________________________________________________________________ 99

CA3026,CA3054
COLLECTOR TO-SASE VOLTSIVCa!'3

ELECTRICAL CHARACTERISTICS at T A = 2Sa C

CH ARACTERISTIC.S

SYMBOLS

TEST CONDITIONS

CA3026
CA3054
LIMITS

TEST
CIR·
CUlT
FIG.

MIN.

TYP.

MAX.

TYPICAL
CHARAC·
TERISTICS
I CURVES
UNITS
FIG.

STATIC CHARACTERISTICS
For Each Differential Amplifier
Input-Offset Voltage

Y,n

0.45

5

mV

6

Input Offset Current

'10
I,

0.3
10

1
24

pA
pA

3

Input Bias Current
Quiescent Operating
Current Ratio
Temperature Coefficient
Magmtude of Input·Offset Voltage

VCB

0

3V

C(Q}lor C(1;5)

1~il11
1

6 VIOl

-7'0

3
~V/oC

U

/'iT

0'

Emiller Voltage

Temperature Coefficient of Baselo·Emltter Voltage
ColleclOl·Culoff Current

Collector·lo-Emitter

VSE
6VBE

t;T
ICBO

VCB dV

VCB

0

3 V.

~~~

I

10 rnA

'c

1 rnA

0

VCB~10V.IEoO

1 rnA. 'B

Breakdown Voltage

V,BRICEO

CollectOl-lo·Base
Breakdown Voltage

VI BRICBO

'e=

10J,JA,IE=O

Collector ·to-Substrate
Breakdown Voltage

VI BRICIO

IC=

IO~A.ICI

0

0

0

V

6

·1.9

JJV/oc

4

0.001

nA

2

100

15

14

V

20

60

V

20

60

V

1'3

.
j

0.7'

~O-'O
~

-

o

VIBR EBO

100
12:'
92CS-I~leelil

Fig.4 - Base-to.emiffe, voltage charaeteristic lor each
transistor vs ambient temperature.

COLLECTOR-TO-BASEVOlJS IV

0.700
0.800
0.850
0.900

0.630
OJ15
0.750
0.800

;'c o 50pA

'C

Emiller·lo·Base Breakdown Voltage

T'

5

For Each Transistor

DC Forwald Base·to-

0

AMBIENT TEMPEAATUREIT"l-.C'"

0.9810
1.01

'E(Q3( IE(Q4)= 2 rnA

I~,"I

7

=0

'E = 10~A.IC= 0

5

7

V

100

dB

~

0

~

~

~

~

ANSIENT TEMPERATURE (TAI--"C'"

92CS-I~181A1

Fig.S . Ollset voltage characteristic vs ambient temper.
oture lor dif/erential pairs.

DYNAMIC CHARACTERISTICS
Common-Mode Rejection RallO
For Each Amplifier

CMR

AGC Rang., One SI'g.

AGC

Voltage Gain, Single Stage
Double-Ended Output

AGe Range, Two Stage
Voltage Gain, Two $tage
Double-Ended Output

A
AGC

8,
VCC~12V

9,

75

dB

9b

VEE' ·6 V
V, ~ ·3.3 V
I 1 kHz

S'

32

dB

Sb

10,

105

dB

lOb

10,

60

dB

lOb

0

A

• For CA3054; use data from DoC to 8SoC only

8b

0.8 COLLECTOR-TO-SASE VOLTS IVeel.]
AMBIENT TEMPERATURE (TAJ'25,,(

Low-Frequency, Smail-SIgnal
Equivalent·Circuit Characteristics:
(For Single Transistor)

Forward Curren I-Transfer Ratio

V

W 0.7

~
~

Shorl-Circuit Input Impedance
Open·Circuit Output Impedance

hoe

Open-Circuit Reverse VollageTransfer Ratio

hre

3.5

krl

11
11

15.6

J,tmho

11

110

'

1 kHz. VCE
'C 1 rnA
0

0

3 V.

1.8,10' 4

0

~

~ 0-5
~

11

,

DYNAMIC CHARACTERISTICS CONTD

~~
II
" ,

,

INPUT OFFSET VOLTAGE. \\leE.1

no
o. ,

2

I III ,I
680-1

£

(j'

2

~

i

'0

~

/"

~ 0.6

h"
hi,

,

~V

!

2

0
6 e 10

"

~
~
~

EMITTER MILLIAMPERES(IEI

1/1 Noise Figure
(FOI Si~le TlansislOl)

NF

I = I kHz, VCE = 3 V

-

3.25

dB

Gain·Bandwidlh Ploduc!
(FOI Single TlansislOl)

IT

VCE = 3 V, IC

-

550

MHz

12

Forward Transfer Admittance

y"

Yn

VCB = 3 V
Eath Collec!OI

13,

Input Admiltance
Output Adrniltance

Y22
Y,?

= 3 mA

Fig.6 - Static bose-to-emitter voltage characteristic and
input ollnt voltage lor differential pairs vs emi"er
current.

Admittance Characteristics;
Differential Circuit Configuration:

(For Each Ampliliel)

Reverse Transrer Admittance

'C~1.25mA

,0 I MHz

-

·20+jO

mmho

0.22+jO.l

mmho

13b

O.Ol+jO

mmho

13c

·0.003 +jO

mmho

13<1

Admittance CharacteJistics;
Cascode Circuit Configuration:

(Fo, Each Amplifielj
Forward Transfer Admittance

Y?l

Inpul Admittance

Yu

Oulput Admittance
Reverse Transfer Admittance

y"
Y12
NF

Noise Figure

VCB = 3 V
Total St'ge
'C~ 2.5 m~
I d MHz
I = 100 MHz

-

68·jO

mmho

148

0.55+jO

mmho

14b

O+jO.02

mmho

14c

0.004-jO.005

I"Ilho

14<1

8

dB

0.01

..

6 9 0 .1

4

6

e

I

COLLECTOR MILliAMPERES IIcl

4

6 '10

92CS-I~216RI

Fig.7 - Input ellset current fer matched dillerentiaf
pairs vs colfector current.

100 __________________________________________________________________

CA3026,CA3054
TYPICAL DYNAMIC CHARACTERISTICS
COMMON MODE REJECTION RA TIO
T.'lIIlnal Hu",b.r. In Circle. are
for C.43026

POSITIVE DC St.f'PLY VOLTS IVCCI • +12

!r~r;;(,U~Os."r. In Square BCNI"

I

N£GATIV£ DC SUPP!.Y VOLTS IVE£"-6

110

f'REClUENCY If I' I kHl

I
2

Ii

f

~ 100

~

VIN,Q3Vlr..1I

j

Flg.S

(0) T•• t ••tup

-I
-2
-3
-4
DC 81AS VOLTS ON TERWlNAL@ [[] IV.I UCS-I5ZSI1t1

(b) Charact.ristic

SINGLE-STAGE VDLTAGE GA/N_ _---,-,-_ _,....,._
T:.'C~;t~UIn"" In Clrel••

aN

T.'lIIlnal NUMb. . In Squa,.

aoxe.

ate

'Of' CA305.

(D)

r •• , setup

Flg.9

TWO·STAGE VOL
T ...... lnal Num_,. In Clrcl•• are
lor CA3026
T.,,,,lnal Numb.r. In Squa,. Boxa.

I,.'

ar.'or CA30s.t

I.'

'.'.p

Fig. 10
TYPICAL DYNAMIC CHARACTERISTICS FOR EACH TRANSISTOR

(o) T•• t

~. COLI.Ec;TOR-TO-8ASEVOLTS IVcal.,
FREQU£NCYU!·.kH;r
• AMBIENT TEMP£R"1\RElTAI'2~'"G

,

I

ii ·
10

-:::- :---..

-

"0,,15.6,.111110

01
~

"

/
/

-

,

",

~

~

1

·,

f--

I I

r-.....

i,
~

I

'.,'"0
)
";.':5.5ICO
"r"I."IIO-4aIIfllA~

. .. . . ..
~

'"'0,
N

I

COLLECTOR MILLIAMPERES IIel

,

. ..I

~

'2CS-I'I90R.

Fig. rJ • Forw",J cu,renf-l'Gnsfe, '''';0 (II'e}' shOt'·circui,
Inpu' i",,,.Jonce (II,.}, open.circui' ou'put ;mpeJonce
("".', "nJ open.clrcul, rewerse volfrJ,e.,ransfer r"flo
(h,.} vs colledor cu,rent 'or eoell flansislor.

COLLECTOR MILLIAMPER£S tICI

Fig.12 • Gain-6onJwid,h product (IT) vs collec'or

curren'.

____________________________________________________________________ 101

CA3026, CA3054
TYPICAL DYNAMIC CHARACTERISTICS FOR EACH DIFFERENTIAL AMPLIFIER
I
N
L
N I
I
COLLECTOR-TO-8AS( VOLTS tVee}"

COLLECTOR-TO-!ASE VOLTS l\lcel"

COLLECTOR CURRENTIICIOF EACH TRUlSISTOR .. I.2S ...

COLLECTOR CI,/ARENT IIel OF EACIi TRANSISTOR "1.2:50 rnA
20

A~BIENT

TEMPERATURE !TA}·250·

_

S AMBIENT TEMPERATURE \TAI·25·

921

2

4

6 8 I

'"

6 8 10

2

" 6 8 100

" 6',

2

'" 6'10

"

FREQUENCY Ifl-MHI

FREQUENC'I'\I)-MHz

Fig.13(a) - Forwordtransferoclmittonc:e (Y21)vS frequency.

&'100

2

')2(.S-I'249111

Fig.J3(b) "npu' admittance (y,,).

0.01
6 8 J

'"

'"

6 810

2

4

6

eloo

2

2

"68 I

10

2

"6 '00 Z

Fig.13(c) - Output oc/mittance (Y22) vs frequency.

" 6,800
,}2CS-I~n6.'

FREQUENCY (n-MHz

FREQUENCY (f)-MHz

Fig.J3(cI) - Reverse fronsferoclmittance(YJ2Jvs frequency.

TYPICAL DYNAMIC CHARACTERISTICS FOR EACH CASCODE AMPLIFIER

~i ~r-i--f-+tt--r-~+++--+-4-+++~

:~ :r-i--f-+tt-'r-~+++--+-4-+~I~/
U

w

~~

~: 2r-i--+-+tt~~~++t.,","L~74-+++-4

~i lr-i--+-+tt~r-1=p+~~~~~"L-~+++-~
I
'" 6 ':0
FREQUENCY (I)-MH:

I
FREQUENCY

Fig.J4(o) - Forworatrons/eroJmittonce (Y2J }vs f,equency.

{, II I

2

'"

6 8 10

z

FREQUENCY tn-MHl

Fig.14(c) • Output oJmiftonce (Y22) vs frequency.

10

IO-MH~

Fig.14(b) • Input admittance (YJ

QOO~
"

... ...

0.'

,~

.

6 15 I

4

100 200

t2CS'15UOItI

J' v.Frequency.

15 '10

FAEQUENCY-M",

Fig.14(J} • Reverse transler aJmittance (YJ2}vS Frequency.

102 ______________________________________________-----------------------

CA3028A, CA3028B, CA3053 Types

DIFFERENTIAL/CASCO DE
AMPLIFIERS

APPl/C A TlON 5

FEATURES

• RF and IF Amplifien <'biH.renlial or Cascade)

• Controlled for Input Offset Voltage,
Input Offset Current, and Input Bias

• DC, Audio, and Sense Amplifiers

Curront (CA3028BI

• Con ... erler in the- Commercial FM Band

FDr CDmmunicatiuns and
Industrial Equipment at
Frequencies frDm DC to 120 MHz

• MililU

• Uscillator

The CA3028A and CA302BB are differential/cascade amplifiers designed for use in communications and industrial equipment operating at frequencies from de to 120 MHz.

• Balanced Differential Amplifier
Configuration with Controlled
Constant·Current Source to Provide
Unexcelled Versatility

• Limiter

• Companion Application Note, ICAN 5337 "Application
of the RCA CA3028 Integrated Circuit Amplifier in the
HF ond VHF Ronges." This note co... ers choracteris.
tics of different operating modes, noise- performance,
mixer, limiter, and amplifier design considerations.

• Single· and Dual-Ended Operation
• Operation from DC to 120 MHz
• Balanced·AGC Capability
• Wide Operating-Current Range

The CA3028B is like the CA3028A but is capable of premium
performance particularly in critical de and differential ampli·
fier applications requiring tight controls for input offset voltage,

shown below. When orderingthesa devices, it is important to add the

input offset current, and input bias current.

appropriate suffix

Tha CA3028A, CA302BB, and CA3053 ara availabla in tha packages

The CA30S3 is similar to the CA3028A and CA3028B but is
recommended far IF amplifier applications.

ABSOLUTE MAXIMUM RATINGS AT T A

= 250C

Suffix

TO-5

T

.J

.J

.J

At TA up to 55°C

S

.J

(CA3028AF, CA30288F,

.J

.J

750 mW

At TA> 5SoC

Beam-Laad

L

Chip

H

.J
.J

CA3028A

Letter

With Dual-ln·Line
Formed Leads
(OIL-CANI

DISSIPATION:

CA3053FI. . • . . • . • . . . . . . . . . • .

I,tter to the device.

Packaga
8-LaadTO-5

(CA3028AF, CA30288F,

CA3053F) .............•• Derate linearly 6.67mWfOC

At T A up to 85°C
(CA3028A, CA3028B, CA30531 ••...•..•.•. 450 mW

At TA > 85°C
(CA3028A, CAJ0288, CA3053) ,Derate linearly 5 mWI DC

CA3028B

CA3053

o
MAXIMUM
r:;MA=X".IM_U_M-,--V_O_L....T_A_GTE_R_A"Tn_N...,GS_ot_T
....A_=T2_5_C..-_-:::-:--,-..,-,--.,,_ _----, CURRENT RATINGS
1~~~
No.

AM8IENT-TEMPERATURE RANGE:

Operating .... . . . . . . . . . . . . . . . . . . .
-550 C to +1250 C
Storage......... ....... ... .. .. ..
_65 0 C to +150 0 C
LEAD TEMPERATURE (During Soldering):
At distance 1/16 ± 1/32" (1.59 ± 0.79 mm)
+2650 C
from case for 10 seconds max. ...............

•
-\~.

0

-\~

.,

.

10

·11

0

... 201&

'5

.\~.

10

10

-5

0

10

~~5'

-I
"0

0
.IS

'5

10

.IS
10

+30-

to
0

10

0

0

This chart gi yeS the range
of vollages which can be applied
to the terminals listed h«izonlally
with respect to the terminals
listed vertically. Fer example,
the voltage range of the horizontal
termlOal4 with reslEct to terminal

0
.15

'30

10

10

0

2is·lto+5volls.

0

t

.15
10

0

*

-t.~oe
10

0

Terminal 113 IS connected to the sub·
strate and case.
Valtaaes are not normall~ applied be·
tween these terminals. Voltaaes
appear ina between these terminals
wi II be safe, it the specified volt·
age limits between all OtlZ!f telminals are not exceeded.

Umit IS ·12V for CAlOS3
is tl5V fOI CA3053
Umit IS tl2V for CAJ053
Limit is t24V lor CA3028A Ind
-t18V tor CA3053
Limit

•

ELECTRICAL CHARACTERISTICS 01 TA

CHARACTERISTIC

L~

CI RSYMBOL CUlT

• Schematic diagram (01 CA3023A, CA30288 and CA3053.

Vee

Input Offset Voltage

Vro

Input Offset Current

1I0

Input Bias Cunent

Quiescent Operating

Current

1r

I&

3.

AGe Bias Current
(lntoConstant,Culrent
SourceTerminalNo.7j
InputCullent(Termlnal

No.7)

3b

3.

or

Is

Fig.2 - Input ollset voltage tes' circuit for CA3028B.

mA

mA

I

0.6

0.1

lOUT

2

•

0.1

3

0.1

23

•

2•

0.1

5

0.6

•. 1

6

2.

.0.1

7

•

•• 1

•

20

0.1

SPECIAL TEST
CONDITIONS

LIMITS
LIMITS
LIMITS
TYPE CA3028A TYPE CA3028B TYPE CA3OS3
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

.s~

CHARACUNITS TERISTICS
CURVES
Fig .

STATIC CHARACTERISTICS

3.

'AI!justRIIGIVOUT
·R.~ .. d '"~'" Ollse! VoU, •.

liN

No.

= 2so C

Fig.

Fig.'

TERMIHAL

17

3'

••

I7
3.

DeviceDissipatlon

PT

3'

+Vee

,V EE

6V
I2V
6V
I2V
6V
I2V
,V
I2V
6V
12V
,V
I2V

6V
I2V
6V
I2V
6V
I2V

I2V
I2V

VAGC "'+9
VAGC '" +12

,V
I2V
6V
12V
6V
12V

'v

I2V

0.98

rnV

0.89
0.56
1.06

16.6 70
36 106

16.6

36

~A

.0
80
2.
36

6V
I2V

0.'
2

1.25
3.3

I
2.5

1.28
1.65

1.25
3.3

85
125

1.5

•

1.2
2.0

mA
2.2
3.3

3.5
5.•

1.2.
1.65
mA

1.15
1.55
6V
12V
6V
I2V

0.5
I

24
120

0.85 I
1.65 2.1

36

175

~A

54
260

0.5
I

0.85
I'
1.65 2.1
36
'2
120 175 220

-

5.
5'
6.
7

~

••

,---

rnA

24

mW

~

.0
ISO

•
r--103

CA3028A, CA3028B, CA3053 Types
ELECTRICAL CHARACTERISTICS at TA = 25a C (canl'd)

CHARACTERISTIC

TEST
CIR·
SYMBOL CUlT

LIMITS

SPECIAL TEST
CONDITIONS

t-FIg.

TYPICAL

LIMITS

CHARAC-

TEaA~TJCS

I---rTY_P_E_C_A_30_28_A.--+--"TY_P_E_C_A_3_0-,2.,B--f UNITS
Min.

I

Typ,

IMaxl Min.

Typ.

n.

Mall.

DYNAMIC CHARACTERISTICS

lOa

,

~

f

lro

Power Gam

Gp

lla
NF

Noise Figure
Input Admittance

Yll

lOa

~

100 MHz

Vee

(Untuned)

f

~

t-:-

lO.7MHz

+9V

f

2Ia

Yee -+9V

22a

f

10.7 MHz

10.7 MHz

Vec

23

RL

0

~::::~::

rnmho

I~

.99, ·,i,l08.
3
5

:~.e

t+,:;~~:~f~~~'~~;=P'j

2of--+-+---t-t--H-+++++f'>1

II FOR POWER GAIN TEST
.. FOR NOISE FlGLf£ TES T

"0
-75

-50

-2!i
0
2~
15
AMBIENT TEMPERATURE lTAI-"C

Fig.9 . Device dissipation vs. temperature lor CA302BA

Fig. lOa . Power gain and noise figure test circuit (cascade
configuration) for CA302BA. CA302B8 and CA30S3*.

*

10.7 MHz power Goin Tost Only.

and CA3028B.

CASCODE CONFIGURATION
AMBIENT TEMPERATURE (TA
FREOUENCY If) '100 MHz

J"2~"C

"

S

6

7

II

9100

Fig. JOb • Powergo;n vs. Irequency(coscocle configuration)
/0' CA3028A and CA3028B.

TYPICAL HOISE FIGURE AHD POWER GAIH TEST CIRCUITS AHD CHARACTERISTICS

Fig.Jia. Powergoin and noise figlJre test circuit (differ.
ential.amp/ifier configlJration and terminal No.7 connected

10
II
12
DC COlLECTOR SUPP\.Y VOLTS ('tcl

Fig.lOc . 100 MHz. noise liglJre 'liS. collector supply
volts (cascade conliguration) for CAJ02BA and CA3028B.

3

FREQUENCY (f) -MHz

to Vcci /0' CA3028A, CA3028B and CA30S3*.
•
..

FOR POWER GAIN TEST
FOR NOISE FIGURE TEST

* 10.7 MHz: Power Gain Tost Only.

____________________________________________________________________ 105

CA3028A, CA3028B, CA3053 Types
Oi/'FERENTIAL~AMPLIFIER

CON IGURATIO
AMBIENT TEW'£RATURE {TA '·25·C
FREQUENCY (f).IOOMHz

O'FFE~ENTlAL-AMPL!FIER

CONFIGURATION
AMBIENT TEMPERATURE ITA) ·2~·C
40

J

"'=== t--CO

lE"Ct;

o , '~flfJ

'"
J"

....;: "(y

~
I

"0(1"$

r::::~ J·~/~
"

20

~

"

i

"

~

"

w

,

~ 7

1O

,

00

."

, ,

,

fAEQJENCY (0- MHl

Fig.l1b • Power go;n vs. frequency (c1ifferentja/~
amplifier configuration) for CA3028A oncl CA3028B.

10
II
DC COLLECTOR SUPPLY VOLTS

12

{Vcc'

JII

..

Fig.l1c - 100 MHz noise ligure vs. collector supply
voltage (dillerential.ampli(;er conliguration) for CA3028A

FOR POWER GAIN TEST
FOR NOISE FIGURE TEST

Fig.lld - Power gain and noise figure test circuit (dilferentio/-amplifier configuration lor CA3028A and CA30288.

and CA3028B.
TYPICAL ADMITTANCE PARAMETERS
CASCOOE CONFIGURATION
AMBIENT TEMPERATURE (TA' :2~·C
STAGE co'.LECTOR MILLIAMPERES [te{STAGE)] '4.5
COLLECTOR SUPPLY VOLTS (V I ~+9

:51

11 2~ +--r~+f++H----+~~~*+~
~¥
o~

~~
~~

6 B 10
2
FREQUENCY (II-MHz

Fig.11e - 100 MHz noise figure ana power gain YS. bas.fo-em;tt.r bios (terminal No.7) for CA3028A and CA3028B.

CASCODE CONFIGURATION

[Ie TAC".Ell

'4,5

buV'

~--+--r~+f++H----t~I71_+tT~

"::::::::V'"

B 100

Fig.12 - Input admittance (Yn) vs. freqvency (cascaae
configuration) lor CA302BA, CA302BB and CA30S3.

QIFFERENTIAL-AMPLIFIER CONFIGURATION
AMBIENT TEMPERATURE ITA): 25·C

AMBIENT TEMPERATURE ITA )'25-C

~,

-1

.5

I

,

1O
FREQ.,ENCY (f1-MHz

I,

Fig.17 - Forwara transaamittance (Yn) vs_ frequency
(differential-ampfifiercon(;gurat;on) for CA3028A, CA30288
andCAJOS3.

I

'100
2

3

"

~ Ii 7 B ~IO
2
FREOUENCY If}-MHl

Fig.18 . Output aamittance (Y22) vs. frequency (coscode
configuration) for CA3028A, CA302BB ana CA30S3.

"

Ii
'10
2
FflEOUENCY (f }-MHz

, 100

Fig.19 - Output aamittance (Y22) vs. frequency (aifferential-amplifier configuration) for CA302BA, CA3028S

anJ CA30S3.

106 __________________________________________________________________

CA3028A, CA3028B, CA3053 Types
TYPICAL TEST CIRCUITS AHD CHARACTERISTICS
or:F£f£NTIAL-AMPLIFI!ER CONfIGURATION
CCWSTANT POWER N'UT0ZIlW
AMBIENT TEMPERATURE IT. I' 25-<:
I,

':.
I

~o

i:;;

.,

~,~c~-+:.

"

'""

r-

"

~~~--~~~o~n

'}~

'It

to",

1'\ 'i-"~

,

-

i1--r-...

§

I1\."-

I

FI,.20a • OUlpUI p.w.r , ••, elrcull I.r CA3028A ••d
CA30288.

R'

VOLTMETER

'r,

100

10

mEQUENCY (!)-MHI

Fig.20b - Output powe, .,•. I,equlncy _ 50 n inpu, anJ

Fig.2la • AGC range tes' circui' (Jilleren,ial amplifier,

oulpu' (Jilf.ren,io/.amplilier conllguratlon)' lor
CA3028A ••d CA30288.

I.r CA3028A ••d CA30288.

SO n

10

DC lIAS veaTS 0lI TDtttINAl.. ....7

12t1-..5CII
HCS-..soeflll

FI,.2Ih. AGCch.racler/.,/c. 'orCA3028A •• d CA30288.

F/,.22a • Trande, charact.risfic (vo/'og. gain) t.sf
circuit (10.7 MHz) co,cod, conllguratlon lor CA3028A,

Fig.22b - Transler characteris'ics (cascod. conligura,ion)

10. CA3028A, CA30288 •• d CA3053.

CA30288 ..d C 103053.
Vee
OSCILLOSCOPE
WITH HIGH-GAIN
DIFFERENTIAL
INPUT
(TEKTRONIX TYPE
530, 540, OR 5eo
WITH TYPE 0 P!...UG-IN
TEKTRONIX TYPE 502,

10

OR
EQUIVALENTI

VEE

'For R'" 1.6 kf2 - (Vce = 12V. Vee'" J2V)
Fm R =2kf2 - (Vee = 6V, Vee = ·6V)

INPUT va.'S l.w
UCS-M5Q1

FI,.22c - TtfIIIsl., choracte,ls"c (yol,o,. flG;n) 'IS'
circuli (10.7 MHz) d "/ore.,/.I••mp"'i.r con",u,""",

Fi,.22J - Trans'" characteristics (Jill.renlia/.amplifier
con/i,ur."•• ) I.r CA3028A, CA30288.nd CA3053.

Fig.2l - DIII.rentiol vo/tag. gain, maximum peale.'a-peale
output voltage, anJ bandwid,h 'es' circui, lor CAl0288.

lor CAl02U, CAl0288 ••d CA3053.
OSCILLOSCOPE
WITH HIGH-GAIN
DIFFERENTIAL
INPUT
(TEKTRONIX TYPE

530. 540, OR 510
WITH TYPE 0 PLUG-IN
T£t(TRONII{ TYP£ !502,
OR
EQUIVALENTI

Fer CMR test: 51 to IIround
For Input common...,ode yolt. ranlle test: 51 to Vx
Common mode rejection ,atio =20 101110 (A') (2) (0.3)
VD1FF(RMS)"
• A '" Slrlille-ended Yoltalle lIaln.

F/g.24 • Comman-moJe rejection ratio anJ common-moJ.
inpuf-vo/tage range test clrcui, lor CAl028B.

______________________________________________________

~

________ 107

CA3036

DUAL DARLINGTON ARRAY
-Two independent low-noise wide-bond amplifier channels
eParticularly useful for preamplifier and low-level amplifier applications in singlechonnel and stereo systems

• Wide application in low-noise industrial instrumentation amplifiers
eHermetically seoled. oil-welded 10·lead TO-S-style metol package

ELECTRICAL CHARACTERISTICS, .t TA = 25·C

For Each
Transistor
(QI. Q2. Q3. Q4)

Fig,.1 - Schem.tic Diagram for CA3038.

CHARACTERISTICS

SYMBOLS

Colleclor·Culoff Currenl
Colleclor·Cutoff Current
Collector·ta-Emitter Breakdown Voltage
Collector·to·Base Breakdown Voltage
Emitter·ta-Base Breakdown Vollage

ICBO
ICED
V(BR)CEO
V(BR)CBO
V(BR)EBO

For Either Input
Transistnr (QI or Q3) Static Forward Current-Transfer Ratio
For Eilher
Dartingten Pair
(QI. Q2 or Q3. Q4)

For Each
Input Transistor

(QI or Q3)

hFE

Emitter-to-Base Breadkown Voltage

LIMITS
TEST
TYPE CA3036
UNITS
CONDITIONS
Min.
Typ.
Max.
j'A
VCB =5V, IE-O 0.5
j'A
VCE -10 V.IB5
IC -I rnA. IB =0 IS
V
20
V
Jc-IO!"A.IE-O 30
44
IE -10 j'A, IC-O 5
V
6

-

hFE(D)

Short-Circuit Forward Current-Transfer Ratio

hfe

Short·Circuit lopullmpedance
Open-Circuit Oulpul Admittance

hie

Open-Circuit Reverse Voltage-Transfer Ratio
Short-Circuit Forward Current-Transfer Ratio

hoe
hre

ICI or IC3 =1 rnA
-1O~

ICLo~ IC2

Darlington Pair

Voltage Gain

A(D)

IC3 + IC4j

(QI. Q2 or Q3. Q4)

Power Gain

For Either

For Either
Input Transistor

(QI or Q3)
For eilher
Darlington Pair
(QI. Q2 or Q3. Q4)

EN

Forward Transfer Admittance

Yf.

Inpul Admiltanc. (Oulput Short·Circuited)
Oulpul Admittance (Inpul Shorl·Circuited)

Yoe

Reverse Transfer Admittance

(Inpul Short·Circuited)
Inpul Admittance (Oulpul Shorl,Circuited)
Outpul Admittance (Inpul Short·Circuited)
Gain·Bandwidlh Producl

Yie

f = I kHz

t

-

V

-

-

-

oO

I rnA

f -100 Hz
f = I kHz
f-lOkHz

oO

-

-

-

oo

f=50MHz
ICI or IC3 =2 rnA

Yre
Yie(D)
Yoe(D)
fr(O)

- -

12.6

-

G~D)

Noise Voltage
See Fig.3 for Tesl Circuit

82

10

oO

f =1 kHz
IClor1C3=lmA

Open-Circuit Reverse Voltage-Transfer Ratio

Open-Circuit Output Admittance

30

ICI + IC2l
or
=1 rnA 1000
IC3 + Icd

hfe(D)
hie(D)
hoe(D)
hre(O)

Short-Circuit Input Impedance

-

HIGHLIGHTS
_Matched tronsistors with emitter.follow.r outputs
_ Low·noi.e performonc.
_200·MHI goin.bond.idth product
eOpe-ration from

-55°C to . 125°C

oO

V(BR)EBO(D) IE20r IE4

Static Forward Current-Transfer Ratio

-

oO

oO

f-50MHz

82
2.6K
7
9.8 x 10·5
1300
82K
lOS
2.7 x 10-3
26
47
0.2
0.05
0.012
0.68 +j 7.9
4.14 + j 5.95
1.94 + j 2.64
Negligible

1.71 +j 2.8
3.96 + j 2.6
ISO
200
oO

IClo~ IC2t2mA IC3 + IC4j

4540

-

n
!"mho

APPUCATIOHS
_Ste,.o phonograph preamplifiers

e~:;i:~i::I.~:~r::

and .in,le c,honnel@

• Low-noi.e, .miHer.follower diHerentiol amplifiers
eO,erotlOllol amplifier drive"

-

- n
- dB
- dB
oo

~ho

oO

3
!"V(rms)
0.3
0.1

~

-

mmho
mmho
mmho

oO

mmho

-

mmho
mmho
MHz

MAXIMUM RATINGS, AbIoIutHlltlalmum Valu.:
POWER DISSIPATION, P:

Anyone transistot

.

3OOmu. mW

.

600 max. rriW

Total for array
TEMPeRATURE RANGE:
.

.

. -66 to +126

°e

Storage. . . . . . . . . . •
LEAD TEMPERATURE lOuring Sold.rlng):

•

. -65 to +160

°c

At distance 1/16 ± 1/32 inch 11.59 ±O.79mm)
from case for 10 second. max. . . . . .
+265
The following ratings apply for each transiltor in the .rray:

°c

16 max.
30 max.

V
V

5 max.
50 max.

rnA

0_atin9 .

.

.

•

.

.

.

.

Collector·ta-Emitter Vbftllge. VCEO
Co1lector·to·Bua Voltage, VCBO
Emitter·ta-Base VOltage, VeBO
Collector Current, Ie

.

V

~}
c

Fig.Z. Block Diagram of Stereo Syste-m using CAJOJ6
as Phono Preamplifier.

we$-I •• "

Fig.3 - Noise Voltag. r.,t C'reu't 101 CA3036_

108 _____________________________________________________________________

CA3039

Diode Array

APPL/CA TlQNS

Cjl

• Ring modulators

ULTRA·FAST
LOW·CAPACITANCE
MATCHED DIODES

For Applications in
Communications and
Switching Systems

o.

5So C
TEMPERATURE RANGE:
Operating
-55 to +12S o C
Storage •
-65 to +150 o C
LEAD TEMPERATURE (During Soldering};
At distance 1116 ± 1/32 inch (1.59 ± 0.79 mm}
+ 265°C
from case for 10 seconds max.
5V
PEAK INVERSE VOLTAGE, PIV for: 01-05.
O.SV
D6· •
PEAK DIOOE-TO·SUBSTRATE VOLTAGE, VOl
+20,-1 V
for 01-05 (term. 1,4,5,8 or 12 to term. 10) ,
DC FORWARD CURRENT, IF . • . • •
2SmA
PEAK RECURRENT FORWARD CURRENT, If
l00mA
PEAK FORWARD SURGE CURRENT, Ifburge)
100mA

• Low diode capacitance_
Co = 0.65 pF typical at VR " - 2 V

Five of the diodes are independently accessible, the
sixth shares a common tennina1 with the substrate,

• The CA3039 is available in a sealed·junction
Beam-Lead version (CA3039L). For further
information see File No. 515, "Beam-lead
Devices for Hybrid Circuit Applications",

For applications such as balanced modulators or ring
modulators where capacitive balance is important. the
substrate should be returned to a DC potential which is
significantly more negative (with respect to the active
diodes) than the peak signal applied.

TYPICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS, at TA = 25° C
Charae:teri$tie$ apply lor each diode unit, un leu otherwiu specilifld.

CHARAC·
TERISTIC
UNITS CURVES

LiMns
CHARACTERISTICS

SYMBOLS

SPECIAL TEST CONDITIONS
MIN.

DC Forward Voltage Drop

DC Reverse

Breakdow~

-

V(BR)R

IR=-10;

001

f

~

2

~

0.7

~

0.1

-r:-:---- -'--- '--- r-=---

,
00'
AMBIENT

oe

:J

0.'

"

.-"

-~

-2~

AIo'BIENT TEMPERATURE (TA)-'C

TEMPERATURE ITAI-'C

Fig. 4 - DC reverse (leakage) current between diodes
(l,2,3,4,5) and substrate vs temperature

Fig. 5 - Diode offset voltage (any diode) vs temperature

-"

"

75

100

125

Fig. 6 - DC forward voltage drop {any Jjode} v:o
temperature

.

.

AMBIENT TEMPERATURE (T... '-25·C
DC FORWARD CURRENT (IflaO

AMBIENT TEMPERATURE (TAI.2!!·C
DC FORWARD CURRENT I:rF).O

r

~4

o

"
I
DC FORWARD MILLIAMPERES

U~

Fig. 7· Diode resistance (any dioae)
forward Cllrren'

2

,

DC REVERSE VOLTS (VR) ACROSS DIODE

I

o
I
2
3
4
DC REVERSE VOLTS IVRI BETWEEN TERMINALS I, 4, !!,'.oR 12
AND SUBSTRATE (TERMINAL 101

V$

DC

Fig. 8· Diode eapacitance (diodes '12,3,4,5) vs
reverse voltoge

Fig. 9· DioJ.-to-substrate eapoeitonee
reve-rs. vo/toge

YS

110 _______________________________________________________________________

CA3040

Video and Wideband
Amplifier

FEATURES
• High Diff.r.ntial Pu.h·Pull Voltage Gain ••••.• 37 dB
Slngl •• Ended Voltag. Gain.................... 31 dB
Wide (3d B) Bandwidth................................ 55 M.Hz
Balanced Input and Output
High Input R.llitance ............................... 150 kn
Low Output R•• I.tonc ............................... 125 n
Bia. Option I for Temperature Comp.nlotion:
BiOI Made A: "Canllant" Voltage
BIOI Made B: "Conltant" Gain

•
•
•
•
•

For Industrial lid
Commercial Equipment at
Frequencies up to 200 MHz

typo
typo
typo
typo
typo

• Supplied in the hermetic 12-lead TO-S style
package

The RCA CA3040 is • monolithic silicon integrated
circuit designed to meet the requirements of a wide
variety of applicat\ons requiring high gain and wide bandwidth. The cascode-cOMected differential amplifier
achieves a double-ended gainof37dBwithatypical3dB
bandwidth of 55 MHz. Emitte.... Follower input lind output
stages provide the desirable high input impedance and
low output impedance for coupling to other circuits.
The CA3040 includes two biasing options. allowing the
user to optimize his design over the entire military
temperature range of -55 to +125OC. Bla. Mad. A yields
a substantially constant voltage at the output tenninals
for applications using DC coupling to succeeding stages
or requiring maximum dynamic range over the temperature
range. DC output voltage varies less than 0.1 volt (typically) over the entire temperature range while gain varies
±2 dB. Bias Mod. 8 provides extremely stable gain
over the temperature range. Gain variation is 0 dB (typically) in this Bias Mode. DC variation is to.S volt.
Provisions are also made for stabilizing the operating
point for either si?,le or split power supplies.

APPLICA TIONS
.Mlxe,

• Modulator
• IF Amplifl.r

• Videa Amplifier
• Schmitt Trigge,

• DC Amplifi.r

.S.nl. Amplifl.r

ABSOLUTE·MAXIMUM RATINGS

DISSIPATION' • • • . . • . • . . . . . . . . • . •• 450 mW
Derating factor for TA > 85°C ••.•..•.. 5 mW/oC
TEMPERATURE RANGE:
Operating • • . . . . • . . . . . . • • . . _55°C to +125°C
Storage .•....••.•..•.•.••. -650C to +150oC
LEAD TEMPERATURE (During Soldering):

ALL RfSISTANC£ VALUE.S IN KIl'S.

Fig. 1 • Sen.mafic Diagram for CAl040

At distance 1/16 ± 1/32 inch (1.59 ± O.79mm)
from case for 10 seconds max. ., • • • • . • • •• +26S oC

*

Limitation imposed by the thermal resistance of package.

MAXIMUM VOLTAGE RATINGS at TA = 25°C
The following chart gives the range of voltages which can be applied to the terminals
listed vertically with respect to the terminals listed horizontally. For example. the
voltage range of the vertical terminal 2 with respect to terminal 11 is 0 to +14 volts.

MAXIMUM
CURRENT RATINGS
STATIC CHARACTERISTICS TEST CIRCUITS

TERM-

5'

tNAL

No.

0
·1'

10

+14
0

'1'
0

12

.1.
0

+10
-10

'1'
0

II'

+1'
0

'1'
0

"+14

0

.,

+,
·-3

-3

'3
-3

'1'
0

TERM-

INAL
No. ~

liN

lOUT

rnA

rnA

1

5

5

2

-

-

3

5

5

4

I

0.1

5

-

-

6

1

0.1

7

5

5

8

5

5

9

I

0.1

Fig.2(a) . Bia. MaJ. A
>10
-3

-,'3

0
Note

1

Va:

.10
.,J

.3
-3

.,
-3

10

10

II'

11

-

12

-

12
• Rcff.'I"N1Ct' Substrllw
Nut.e I: Extf.'I'IIl11 cCllUll'cticn required frr Jroper opc'rntion. "

.•• I"

to

-

Fig.2(h) . Bias MoJ. B

10

* Voltages

are not nonnally applied between these terminals.
Voltages appearing between these terminals will be safe if
the specified limits between all other terminal8 are not
exceeded.

___________________________________________________________________ 111

CA3040
DYNAMIC CHARACTERISTICS TEST CIRCUITS

ELECTRICAL CHARACTERISTICS AT TA = 2SOC Unl... Otherwise Specified
Limit.

Tn'
Symbol.

Characteristics

Clte,!I'. Special T••, Conditions

i-Fig.

STATIC CHARACTERISTICS

I

Typ.

"

I Max.

Vee" +6V, VEE = -6V

output \10 Itare

2(,)
2(b)

VIO " VI2

2(,)
Base Bias VOltage

V9
2(b)

Input Bias Reference VOltage

2(,)
2(b)
2(a)
2(b)
2(0)
2(b)

VI

Input Bias Oment

14. 16

Input UnbalMce Current

116.141
12 or

2(a)

15 +111
12 or

Power Supply Current Drain

2(b)

15 +18+111
Vee

DYNAMIC CHARACTERISTICS
Single-Ended Input
Differential Output

SinR'e--Ended Input
and Output

a..dwidth

Differential Voltage Gain Balmce

0'

"
1.4

3.7

2.7

-

-

·1.7
-1.1

-

·1

+1

V

0.1

V
0001

(I~TIONAl)

V
V

-

15

45

"A

-

-

6

"A

4.7

8.5

15.5

mA

."

ALL RESISTORS IN OHMS
ALL CAPACITORS IN MICROFARADS IUNlESS OTHERWISE
INDICATED)
BIAS MODE A IS AS DEFINED IN FIG 2(0)

Fig.l(a) . Bia. MoJ. A

+6V

R!: ~MnZ

34

37

ADIFF(SE)
BW

3(a)

R'

~ ~M~Z

28

31

3(a)

R,

40

55

3(a)

= 50 n
f = 1 MHz

-

0

+1

dB

~oMnz

-

0.5

-

VRMS

7.5

9

dB

150
2.2
125

-

1<\1
PF
II

RMS

3(a)

Noise Figufe

NF

3(a)

Parallel Input Resistalce
Parallel Input Capacitance
Output Reslstmce

R,

3(a)
3(a)
3(a)

C,
Ro

R! :

(Note 11f - 30MHz

R,
f

= 400 n
= 1 MHz

'cc

"VARIABLE CAPACITANCE (05-1.0I>FJ ADJUSTMENT FOR
EQUAL leta BANDWIOHI AT AMPLIFIER (lU--:"PUTS.
TERMINALS 10 AND 12

3(a)

Va or V10

VIO
OUTPUT

ADIFF(DE)

AOIFF(SE)IO
-ADI FF(SE)"

Output Voltage Swing

Bias Mode Switch
A B: Closed
Bias Mode A
Switch Closed
Slas Mode B
Switch Closed
Bias Mode SWitch
Aor B: Open
Bias MOde Switch
A or B: Closed
Bias Mode Switch
A or 8: Closed
Mode A
Switch open or closed
Mode B
Switch open or closed

= +12V. VEE = 0, Split Voltage Supply (Optional) ""

Differential Voltage Gain

·3 dB

']i0"
'''OO''UT

Unit.

Min.

·1

-

dB
dB
MHz

TEMPERATURE DEPENDENT CHARACTERISTICS

Temperature coefficients for ambient temperatllle: -55°C 
06
RMS OUTF'uT VOLTS 11110 ORVI~}

temperature extremes.

Fig.7 ·3dB Bandwidth vs Single·Ended Output Voltage

Power Supply Considerations

I

tt

, '-~t;I
~:;J :f! i j~::rc;:c "':~
----+--.--·t:-:J:..i: I't~'· [Tr·t~
,'-d±:~ ,~ '5i ' t

-+

Mode A.

,

Figures 2 Wld 3 illustrate the use of the CA3040
with balanced dual supplies and single power supplies,
respectively. Both figures demonstrate that the inputs
may be directly referenced to the center point of the
supply (ground in Fig.2) by closing the included switch.
This is the natural connection in Fig.2. This connection
is optional, however, and need not be made. Use of this
connection in Fig.3 implies the presence of another
DC supply or a "stiff' bleeder. If such a source is
present its use is suggested in order to maintain maximum corrunon mode range. Dynamic performance and
dynamic range of the output circuit are unaffected by the
choice of biasing scheme used so that in most cases
direct connection of Terminal No.1 to the center point
of the supply is not required. Where direct connection
is not used, Terminals No.4 and No.6 must be biased
from Terminal No.1 for proper operation.

'"

'"

'00

'"

"'"

SQURCE RESISTANCE (Flsl-OHMS

Fig.8 -Noise Figure (NF) vs Source Impedance

AMSIENT TEMPERATURE (TA}·Z:i·C
MOCE A,SWITCH OPEN, I'IG. 3(Q)

COLLECTOR SUF'P\.Y VOLTS (VCc)'''6
EMITTER SUPP\.Y VOLTS lVEE;}·-6
MODE AOR8, FIG.2.(Q)ORZlbl

VIOOR VI2 (SWITCH OPEN OR CLOSED)
MODE A

VI {SWITCH OPEN,MOOES A OR B}

High.Frequency Considerotions

Stable high-frequency operation requires that proper
high-frequency construction techniques be followed.
The photograph of Fig.6 illustrates the precautions
taken in the construction of the test circuit of Fig.3.

-:i0

S
9
10
11
IZ
COLLECTOR SUPPLY VOLTS (Vec)

-2!>
0
AMBIENT TEMF'ERATUFlEITA}-'C

Fig.l0 . Collector Supply Current Drain (/2)
vs Collector Supply Voltage (Vee)

Fig.9 - Output Volts ar Input Bios Reference Volts
Ambient Temperature

vs

Extreme caution is required because of the extended
gain bandwidth capability of the device. Oscjllations
have been observed in the 400-to_BOO MHz range when
precautions were not taken. ~In addition to normal considerations of shielding, parts layo':!t, and isolation,
the following specific suggestions are made:

1. Use sockets only when necessary. Sockets, when
used, must provide shielding within the
The socket shown in the chassis of
Barnes MG-1201, or equivalent, modified
a lIBH hole in the center and inserting
brass pin.

pin circle.
Fig.6 is a
by drilling
a grounded

COLLECTOR SUPPLY VOLTS (VCC}'+IZ
MaOEA,SWITCHCI.OSED,FIG3IQj

T

:;

i

2. Do not bypass Terminal No.9 in normal operation.
Fig.3 shows the" use of neutralization between
Terminal No.9 and one output to balance the amplifier
at high frequencies. Experience shows that stable
operation, while possible. is difficult to achieve
if Tenninal No.9 is bypassed to ground.
3. In DC testing, 1 kD, 114 W carbon resistors should
be soldered directly to the socket Tenninals No.4
and No.6 to suppress parasitic oscillations. All
current carrying connections are made at the other
end of the resistors. Direct sensing of Terminal
No.4 or No.6 voltage should not be attempted.

30

MODES

-2!>
AMBIENT TEMPERATURE (TAI-'C

Fig. J 1 - Collector Supply Current Drain (/2)
vs Ambient Temperature

2:i
7!>
100
0
AMBIENTTEJoIPERATURElTA}-'C

IZ:i

Fig. J2 - Single.Ended Differential Voltage Gain
vs Ambient Temperature

________________________________________________________________________ 113

CA3045, CA3046 Types
General-Purpose Transistor Arrays

THREE ISOLATED TRANSISTORS
AND ONE DIFFERENTIALLY -CONNECTED
TRANSISTOR PAIR
The CA3045 and CA3046 each consist of five general-purpose
silicon n-p-n transistors on a common monolithic substrate.
Two of the transistors are internally connected to form a

For Low-Power Applications at Frequencies
from DC through the VHF Range

differentially-connected pair.

through VHF range. They may be used as discrete transistors
in conventional circuits. However, in addition, they provide
the very significant inherent integrated circuit advantages of

7

9

10

12

13

SUB-

STRATE

92(5 ·'5206

Fig.' - Sdlltmafic: diagram.

• Two motche-d pairs of tronsistors
VSE matched -t 5 mV

ABSOLUTE MAXIMUM RATINGS AT TA' 250C

CA3045

Each
Transistor

Power Dissipation:
TA up to 5SoC

CA3045F, CA3046

Toul
Package

Each
Transistor

> 55°C

TA> 7SoC - ... -.

.5 general purpose- monolithic transistors

mW

750

Derate at 6.67
300

Input offset current 2 pA max. at Ie '" 1 mA

Totll
Package

300

T A up to 7SoC

• Operotion from DC to 120 MHz.

mWfOC

750

• Wide operating current range

mW

Derate at 8

mW/oC

• Low 'noise figure.· 3.2 dB typo at 1 kHz.
• Full military temperature range for CA3045

Collector-to·Emitter Voltage, VCEO

15

15

V

Collector-to-Base Voltage, VCBO .

20

20

V

Collector-to-Substrate Voltage, VCIO *

20

20

V

Emitter-to-Base Voltage, VEBO

-55 t. +I 250 C
• The CA3045 is available in a sealed·junction
Beam·Lead version (CA3045L). For further
information see File No_ 515, "Beam·Lead

V

Temperature Range:
Operating
Storage ..
Lead Temperature (During Soldering):
At distance 1/16 ±1/32" (1.59 ±O.79 mm)
from case for 10 seconds max: ...
* The collector of each transistor of the CA3045 and
CA3046 is isolated from the substrate by an integral
diode. The sub~lrale (terminal 131 must be connected
01

-55 to +125
-65 to +150

-55 to +125
-65 to +150

+265

+265

Devices for Hybrid Circuit Applications"_

APPLICA TlONS

to the most ne~ative point in the ederna' ci~(,uit to
maintain isolation between t~8ns;~tOrs and to provide
(or normallransi~to, Betlon.

• General use in all types of signal processing systems
operating anywhere in the frequency range from
DC 10 VH~

TA = 25·C

• Custom design.l differential amplifiers

Characteristics apply for each transistor in the CAJ045 ana CAJ046 os speci/iecl

CHARACTERISTICS

6

FEATURES

close electrical and thermal matching.

ELECTRICAL CHARACTERISTICS,

}

The CA3046 is electrically identical to the CA3045 but is
supplied in a dual-in-line plastic package for applications
requiring only a limited temperature range.

The transistors of the CA3045 and CA3046 are well suited to
a wide variety of applications in low power systems in the DC

TA

41drlrl

The CA3045 is supplied in a 14·lead dual-in-line hermetic
(welded-seal) ceramic package and the CA3045F in a 14-lead
dual-in-line hermetic (frit-seall ceramic package.

SYMBOLS

• Temperature compensated amplifiers

LIMITS
Type CAl045
Type CAl046

SPECIAL TEST CONDITIONS
MIN.

TYP.
60
14
60
7
0.e:J1

UNITS

• See RCA Application Note, ICAH·5296 "Application
of the RCA·CA3018 Integrated.Circuit Transistor
Array" for suggest.d applications.

MAX.

STATIC CHARACTERISTICS
Collector-Io-Base Breakdown Voltage

V,BRlr.Rn

Ir. -lDIIA,1 ·0

10

Collector-to-Emitter Breakdown Voltage

Y,RRlrm

'C • I mA, 'B • 0

COllector-la-Substrate Breakdown Voltage

V,BR CIO
V,BR EBO

15
10
5

Emitter-to-Base Breakdown Voltage
Coliector·CutoH Current

'CBn

Colleclor-Cutoff Current

'CEO

Static Forward CUlrenl-Transfer RallO
jSlaliC Beta)

hFE

Input Offset Currenl for Matched Pair

Q, and 01,

1i '01 - 11011

Base-lo·Emltter Voltage

VeE

'C • 10pA, ICI ·0
' E 'lOpA,IC ·0
VCB_; 10 V,IE ·0
VCE .10 V, Ie ·0
fC -10 mA
VCE • 1 V IC' I mA
'C • 10 11A

See curve

40

40
0.5

V
V
V
nA
IIA

O.l

VCE • 1 V{'E • I mA
.1 .10 mA

0.715
0.800

VCE = 3 V,IC = I mA

enlIOI Palf IVBE I - VBE1 1

VCE • 3 V, 'C -I mA

pA

0.45

Collector-to-Emitter Saturallon Voltage
Temperature Coefficient:
Magnitude of Input·Offset Vollage

114

l>VBE

5

mV

5

mV

~

:i

"riZLL

•

,

IVID

·,,
i

§

"f)

o,,,z.,·

/'
~C-oq:.

~ IO-~

liT

-xr

4:"

~

10-

g
0.45

o'&'41J.

·

~

~

~.

,
I:

~

V

/.

.LL

10

U

Iv BE4 · VBE5I,lvBE5' VBEl
Temperalure Coefficient of
Base-to-Emltter Voltage

.f ·!

EMITTER CURRENT II )-0

,

z

1

Magnitude of Input Offset Voltage for Differ-

Magnitude of Input Offset Voltage for Iso·
lated Transistors IVSE3 . VBE41,

IO~~

l"

100
100
54

VCE· 3V,I C ·lmA

STATIC CHARACTERISTICS

V

°

"

'0

75

100

AMBIENT TEMPERATURE (TA)-"C

'"

Fig. 2 - Typical collector-to-base cutoff current

vs ambient temperature for each
transistor.

CA3045, CA3046 Types
ELECTRICAL CHARACTERISTICS, .t TA = 25°C

STATIC CHARACTERISTICS

Characteristics apply lor each transistor in the CA3045 and CA3046 as sped/ied
LIMITS
CHARACTERISTICS

SVMBDLS

Type CA304S
Type CA3046

SPECIAL TEST CONDITIONS
MIN.

TVP

UNITS
MAX.

DVNAMIC CHARACTERISTICS

f= 1 kHz, VeE= 3V,le= 10D"A
Source Resistance::: 1 kn

NF

Low-Frenuellcy NOise Figure

3.25

dB

Low-Frequency, Smail-Signal
EQulvalent-ClfclIlt Characteristics:
Forward Current· Transfer RatiO
Short·Clfcult InpLlllmpedance

hie
h

~IMtOutputlmpedance

hoe

Open-Cuclln Reverse

110
I ~

1
1 kHz. VCE 3 v. IC

~

1 mA

j

hre

Voltage-Transfer RatiO

~

3.5

~.

15.6

",mho

1.8,10. 4

Admittance Characteristics:
Forward Transfer Admittance

VI

Input Admittance

Olliput Adrnillance

V"
Vo,

Reverse Traflsfer Admittance

Vre

Gam-Bandwidth Product

31'11.5

1

f = 1 MHz. VCE~3V. IC

~

See curve

IC ~ 3 rnA

550

300

Emltter-Io-Base Capacitance

CEB

VEB~3V. IE ~ 0

0.6

Collector-la-Base Capacitance

CCB

VCB~3V. IC ~ 0

0.58

pF

Collectol-lo·Substrate Capacltallce

CCI

VCS~3V.IC~0

2.8

pF

10e

6

TEMPERATURE ITAI_oC

Fig.3 . Typical collector-to·emitter cutoff current vs
ambient temperature lor each transistor.

0.001'10.03

j
VCE~3V.

IT

AMBIENT

0.3'1004

1 mA

pF

COLL(C'TOR-TO-(MITT[R VOLTS {VCEI-3
Ar.1BIENT TEr.1PERATURE (TJ\)·25"C

r--r--r-H-t---j~

-t-t-,,--;--

'~r--r-.-

~

~

~

+Ht-+-1-+++0.
4

& 8 01

4

6

B I

46

a OI

4

f,

B,

4

6

EMITTER MILLIAMPERES (IEI

COLLECTOR MILLIAMPERES lICI

Fig.4 • Typical static lorward current.trans/er ratio and
beta ratio lor transistors Q, and Q2 vs emitter current.

Fig.5 . Typical input ollset current (or matched
translstor pair Q,Q2 vs collector current.

COLLECTOR-TO-EMITTER VOLTS

B,O
'EMITTER MILLIAMPERES(IEI

Fig,6 - Typjcal static base.to·emitter voltage character.
istic and input olfset voltage (or djfferential pair and
paired isolated trans istors vs emitter current.

COLLECTOR-TO-EMITTER VOLTS (VCE1'3

(VCEI~3

~

0.75

~ 050

-25

0.1

25

AMBIENT TEMPERATURE (TA1-OC

Fig. 7 - Tvpical base-to-emitter voltage charac·
teristics vs ambient temperature for
each transistor.

100

125

AMBIENT TEMPERATURE (TAI-oC

Fig. 8 - Typical input offset voltage characteristics
for differential pair and paired isolated
transistors vs ambient temperature.

_____________________________________________________________________ 115

CA3045, CA3046 Types
DYNAMIC CHARACTERISTICS FOR EACH TRANSISTOR
COLL[CTOR-TO-Et,lITTER VOLTS (litE'"
SOURCE RESISTANCE OHMS (Rsl'~OO
AMBIENT TEMPERATURE (TAl'2S'e

20

Ii

I

..sJ

;"
~

~....~~

10

,b:::::--

"

i-'

- ..

,

~

I

/'

I

V-

I

p-

.
I

,

Fig.9{a) - Typical noise figure vs collector current.

'" AMBIENT TEMPERATUREITA,125"C

I

I

-

8 0.1

2:

Fig.9(b) - Typical noise ligllre vs collector cllrrent.

Fig.9(c} - Typical noise 'igllre vs collector current.

III

11.1

,I-r---+-r-.....-+-+-++-- ~:ee:21~~t1

6

COLLECTOR MILLIAMPERES IIel

COMMON-EMITTER CIRCUIT,BASE INPUT

100 co..LECTOR-TO-[MITTER VOLTSIVCE 1.5V
6 FREQUENCY (fJ'lkHz

10

4

0.01
COLLECTOR MILLIAMPERES IIel

COLLECTOR PtlILLIAMPERES (lei

1

h.1

hrl'IS8J110-4o'lmA._

01

hoe '156 ... mho

:

I

0.01

4

6 '0.1

2

4

6 8 I

4 6 8 10

COLLECTOR MILL.IAMPERES IIel

Fig.FO. Typical normalized lorworrl current.transfer
ratio, short.eireuit input impedance, open-circuit
Oufput impedance, and open-circuit reverse voltage-transfer ratio vs coller:::tor current,

0.1

4

68 1

2

4

68 10

2

2:

469,

QI

10

FREQUENCY !f1-MHz

FREQUENCY (f)- MHz

Fig. rl . Typical forwarrl transfer admittance
vs frequency.

Fig.J2 - Typical input admitta,!ce vs Irequency.

~~~~-~I~~~~AW~~1f:I~~·:fPUT
COLLECTOR-TO-EMITTER WLTS (VCEI-'V
COLLECTOR MILLIAMPERES n 101

I

.

,.:

I

1

~

£' BOO ::'1·

]~ 51---I--+-I-~-+-~-K-t--r+t~~~

t;

~ 700

~~ 41--+--1-~+--I-~-1-++~~+-rrr~~'#---1

IE

i1
g~ 31--+--1-~+--1-~-+++~r-+-rrr+~--1

600

I

II

L

••• :.':' ..

:,:

I'

§!n~

~~ 21--+--+~+--+~-+++~r-+-rYr-~--1
~~

lL

e~ II--+--+~+--+~-+++-r~~~~.~=i--i

.....-:
0-1

'" 6 8 1

10

4 6 8 100

FREQUENCYIfI-MHz

Fig.J3 - Typical output admittance vs frequency.

810

2

8100

FREQUENCY(f I-MHz

Fig.14 - Typical reverse transfer oJmittance
vs Irequency.

I

2

3

-4

5

6

7

8

•

10

COLLECTOR MILLIAMPERES IICI

Fig.lS . Typ;cal ga/n-banJwiJ,h product
collector current.

V$

116 ____________________________________________________________________

CA3048

Amplifier Array

Fur Luw-Nuise and
General AC Applications
In Industrial Service

FOUR INDEPENDENT
Ae AMPLIFIERS

. .0

"'.

The RCA CA304R is a silicon monolithic integrated
circuit consisting of four independent identical AC
amplifiers which can operate from a single-ended power
supply.

Each high gain amplifier has II high impedance noninverting input. and a lower imln'-stabilizcd operation. Tht'Y may
be used in a wide variety of' AC' applications in which
operational amplifiers have previously been USl>d.

Thl' CA:I04H is supplied in u II).-Il'iul dutll-in-lint·

Fig. J • Sloele Jiogrom

plastit· Ilnl·kuge.

'0' CAl048.

FEATURES
• Four AC amplifiers on a common substrate

ABSOLUTE-MAXIMUM RATINGS at TA

= 2S"C:

• Inll.,.nd.ntl), accenible inputs and outputs

DISSIPATION:
At TA = Ss"C •••..........••.••.••••••••••..••.••.•• 7S0mW

• Operates Ham single.ended supply
EACH AMPLIFIER

Above TA = 55°C .••••••.•.........•.•.• Derate linearly at 7.7 mW/oC

• Nain figure at 1kHz .......................... 2 dB t)'p.

TEMPERATURE RANGE:

• High ¥Oltage gaiR .............................. 53 dB min •

. Operating • • • • • • • • • .. • .. • • • • • • • • • • • • • • • • • • • • •• ... _40°C to +sSOC
Storage. • • • • • . • • • • • • • • • • • • • • • • • • • •• • • • . • • • • •• _65°C to +l50oC

• High Input Nsl.tonce ......................... 90 k~l typo
• Unllistarted output voltage ................... 2 V rms min.

LEAD TEMPERATURE (During Soldering)
At distance 1/16 ± 1/32 inch (1.59 ±0.79mm)

rrom case ror 10 seconds max. .

• Output Impedanclf .............................. llr.\: typo
• Open.laop bandwidth .......................... 300 Ir.Hz '),p.

• •••.•••••••••••••••••••••••••••• +26SoC

APPUCA TlONS

POWER SUPPLY VOLTAGE • . . . • . . . . . . • . . . . . . . . . . . . . . . • . • • • _ +16 V
AC INPUT VOLTAGE • • • • . . . . . • . . • • • . . . • • . . • . . . . . . . . .• 0.5 V nns

• Multi.channel or cascade operation
• Law·level preamplifiers.

MAXIMUM VOL TAGE RATINGS
The following chart gives the range of voltages which can be applied to the terminal.
listed vertically with respect to the terminals listed horlJ:ontally. For example. the
voltage ranse between vertical tenninal 2 and horizontal termlna14 is +2to-3.6 volt••

• Equalizers
• Lin.ar signal mixers
• Tone g.neratars
• Multlvibratars

TERM-

7

INAL
No.

10

11

12

13

14

15

16

• AC integrators

o

+16

o

-16
+2

-3.6

~~.6

-3.6

+2
-3.6

-3.6

+16

o

+2
-3.6

+16

+16
0

'2
-3.6

+16
0

o

0

-16

+5

-5

4

;-3.6

-2

o

-16

+2

0
-16

0
-16

'5
-5

'5
-5

10
11
12

13

o

-Vee

-16

+5

·~CT

-5

Fig.2 - T•• , circuit lor measurement 01 collector
.upply vollage anJ currenls.

14
15

TO .... IOPIIfAT~TER.IINAL. TO RUDYOLTAGE

+16

o

16
• Voltages are not normally appUed between these terminsls.
Voltages appearing belween theae terminals will be safe if the
specified limits between aU other terminals are not exceeded.

___________________________________________________________________ 117

CA3048

DC SUPPLY VOLTS IVce'

Fig.4 • Typical DC supply current vs supply vo/tag •.

COLLECTOR SUPPLY VOLTS IVee '-+12

~

13

l'Iote: All resistor values are in ohms

Fig.J - Schematic c/iagram lor CA3048.

ELECTRICAL CHARACTERISTICS •• TA = 25°C

CHARACTERISTICS

SYMBOLS

TEST CONDITIONS

TEST
CIR·
CUlT

LIMITS
CA304S

UNITS

I TYP.

MAX.

9.5

13.5

17.5

rnA

6.1

6.9

8.1

V

FIG.

MIN.

TYPICAL
CHARAC'
TERISTICS
CURVES

000
AMBIENT TEMPERATURE (TAI-·C

Fig.S - Typical DC supply current vs ambient
tempetatute.

FIG.

STATIC
current drain per amplifier pair

112 or 115

Vee" +12V

DC
at
DC
at
DC
at

VI,

Vee:: +12V

1
1

Vee:: +12v

1

1.7

2.0

2.3

V

= +12V

1

2.2

2.5

2.8

V

53

58

-

dB

kHz

9

%

10

kil

Voltage
Output Terminals
Voltage
Feedback Terminals
Voltage
Input Terminals

V6,

Vll. V16
V3,

V7,

VIO. Y14
V4,
V9,

V8,
V13

Vee

4,5

DYNAMIC (Characteristics given are for each amplifier with no AC feedback)
Open-Loop Gain

Output Voltage Swing

Yf,C

~

AOL

Vee" +12V
f :: 1 kHz

VO(rms)

Open-Loop -3dB Bandwidth

BW

Total Harmonic Distortion

THO

~;~tV
, 10kHz

THO:: 5%
VCC-+12V
EIN

=2mV

vee - +12V, f-lkHz
Eour"2Vrms

..t"
E,

~

6

6

2.0

2.4

6

250

300

6

-

0.65

-

-

90

-

V

7,8

-

OPEN LOOP

Terminals 3, 7, 10,
Input Resistance

R'N

Input Capacitance

C'N

Output Resistance

ROUT

Output Capacitance

COUT

Feedback Capacitance
(Output to noninverting Input)
Broad-Band Output
Noise Voltage

and 14 are bypassed to ground
f
1 kHz
f

=
= IMHz

Terminals 3, 7, 10
and 14 are bypassed to ground

f

= IMHz

Vec '" -t12V
f IMHz

=

CFB

-

-

<0.1

-

'I

-

0.3

1

V~C
EN

; ~d~~
lO40dB

-

Equivalent
Noise BW
50kHz

9
1
18

pF
kil
pF
pF

rnV

=

Output Noise Voltage
"Weighted"

12

EN(WT)
10 H z

Noise Figure

NF
(R S " 5 kn)

100 Hz

f

0

1 kHz
10 kHz
100 kHz

Intel-Amplifier Capacitance
(Any amplifier output to
any other amplifier input)

=
=
=+12V

vec
-+ 12V
f ::: 1kHz
o dB 0.78V

Inter·Amplifier Audio
Separation "Cross Talk"

C

Vee
f ::: IMHz

.
-

-

'3

-

-

-

--

0.5

2.2

<·45

-

<0.02

-

'0
5.8
2
1.1
0.6

rnV
dB
dB
dB
dB
dB
dB

pF

-

-

• Sig Gen should be a low distortion type (0.2% THO or less)
HP206A or equivalent.
.
• Adjustment of Eg to 2 wits will make Es =2mV.
Test Circuit shows Amplifier 111 under test,
or 4; Connect terminals as shown in Table.

MtPLIFIER

1
2
3
4

to test Amplifiers 2, 3,

TERMINALS
OUTPUT

INPUT

1
6

8

11
16

4
9
13

BYPASS
3
7
10
14

Fig.6 - Test circuit for meosutement of Jistottion, openloop go;n onJ banclwiclth characteristics.

118 _____________________________________________________________________

CA3048
': 60

INPUT SIGNAL VOLTAGE (E IN )' ImV "loiS
OPERATING FREOUENCY III' I kHI
AMBIENT TEMPERATURE{TAl·2~·C

COLLECTOR SUPPLY VOLTS (Vec)' _12
RIiS rNPUT SICHALliILLlVOLTS(EINl' I
OPER),TING FREOUENCT
'lkN,

I

~
~

40

DC SUPPLY VOLTS {VCCl

-·w

COLLECTOR SUPPLY YOLTS IVccl • '12
A.IIillENT TEMPERATURE IT"I • 2S~C

·
·
·
·
·

"

~

-

f ::
i

i

I

- -

.

t,

I

1[\1

'\

. i

I

I

l

I

I

11,,[
III

I

10,000

FREOUENCYIIl_kN,

A.IIillENT TE.IIPERATURE{t"I··C

Fig.7 • Typical amplifier gain vs DC supply voltage.

Fig.8 - Typieal open· loop goin vs ambient temperature.

Flg.9 • Typical open· loop gain vs frequency.

c, •

-~tf
t

+J::t -':,........

o

_

25

::~_ .~

~

50

AIoiBIENT TEIoIPERATURE ITAI··C
TVcc

Fig. 10 • Typical total harmonic distortion
vs ambient temperature.

• RESISTORS ARE METALFILM TYPE,I"!,

• Ll-2.5 millihenry inductor, dc resistance 0.3 ohms or less.
To lest Amplifiers 1, 2, 3, or 4, connect terminals as shown in
Table.
AMPLIFIER

1

TERMINALS
OUTPUT
INPUT
BYPASS
I
4
3

2

6
11
16

3
4

8
9

1
2
3
4

7

10
14

13

"''''''' '""" """'ce' .. ] I .!
D

,
,

.
",

f'" ""
U

T

I I II

[~

•

"""

CfH
r.lkH,

-

-.F

RFIl

i'

I

.I I! I

OO~.F

-.,-,""~",,,

N PTYPE
.000
(OR EQUIY)

I I' : I

1'l
,

i

I

i

!t-

IO,ODO
RESISTANCE IN FEEDBACK CIRCUIT(RFB1_0HII\

1. Adjust Signal Generator for 0 dB output at reference terminal.
2. Read voltage at other output terminals (Figure shows terminal 1t1
used as reference).

Fig. 13 - rut circuit for measurement of inter-amplifier
audio separation "cross talk" characteristic.

To test anplifiers, connect

TERMINALS
OUTPUT
INPUT
BYPASS

1
6

4
8

11
16

9
13

3
7
10
14

Fig.12 . Test circuit for measurement of "weighted"
output noise voltag. characteristic,

OPERATING CONSIDERATIONS
Economical Gain Control

The CA3048 is designed to permit flexibility in the
methods by which runplifier gain can be controlled.
Fig.14 shows a curve of the gain of an amplifier when
the internal resistive feedback of the device is used in
conjunction with' an external resistor. Although meas~
ured gain of various runplifiers will not be unifonn,
because of tolerances of internal resistances, this
method is very economical and easy to apply.
Stability

100,000

.. V.T.V.M.· Hewlett·Packard Model 4000 or equivalent.

Procedure:

~~~il~t~t; a~et=~o~~n ~~~fe.l%.
AMPLIFIER

Fig.l1 • Test circuit for measlJrement of broadband
noise characteristic.

OPERATIH(;FRECUENCYIII_ I kHz

'"

Fig. 14 . Typical amplifier gain vs feedback resistance.

The CA3048, as in other devices having high gain-bandwidth product, requires some attention to circuit layout,
design, and construction to achieve stability,
Should the CA3048 be left untenninated, socket capaci~
tance alone will provide sufficient feedback to cause
high frequency oscillations; therefore, all test circuits
in this data bulletin include loading networks that provide stability under all conditions.

______________________________________________________________________ 119

CA3049T, CA3102E
Applications

DUAL HIGH- FREQUENCY
DIFFERENTIAL AMPLIFIERS

• VHF amplifien
• VHF mixers
• Multifunction
combinations RF/Mixer/Oscillator;
Converter II F
• 1F amplifiers (differential and/or cascode)

For Low-Power Applications at Frequencies
up to 500 MHz

Features:
• Power Gain 23 dB (typJ at 200 MHz

• Product detectors
• Doubly balanced modulators and demodulators

• Noise Figure 4.6 dB hvpJ at 200 MHz

• Balanced quadrature detectOR

• Two differential amplifiers on a common substrate

• Cascade limiters
• Synchronous detectors

• Independently accessible inputs and outputs
• Full military-temperature-range capability- (_55°C to + 12SoC)
for the CA3102E and for the CA3049T

• The CA3049 is available in a sealed-junction
Beam-Lead version (CA3049L)_ For further
information see File No. 515. "Beam-Lead

Devices for Hybrid Circuit Applications".
RCA-CA3049T and CA3102E

consist of two independent

differential amplifiers with associated constant-current transistors on a common monolithic substrate. The six transistors
which comprise the amplifiers are general-purpose devices
which exhibit low I/f noise and a value of fT in excess of 1
GHz. These features make the CA3049T and CA3102E use·
ful from dc to 500 MHz. Bias and load resistors have been
omitted to provide maximum application flexibility.

Schematic Diagram for CA3049T

• Balanced mixers
• Synthesizers
• Balanced (push-pull) cascode amplifiers
• Sense amplifiers

" , I'

MAXIMUM RATINGS. ABSOLUTE-MAXIMUM VALUES,
ATTA -25'C
Power Dissipation, P:
Anyone transistor .... , .
Total package... ... . .. .
For TA> 55°C Derate at:

.::C::.;A::::304=9.:.T...,.---,C",A.::3"I.::;02o.:E=300
300
mW
600

SUBSTRATE ~

750
mW
6.67 mWf,c

Temperature Range:
Operating ............. -55 to + 125 -55 to + 125 DC
Storage .............. -65 to + 150 -65 to + 150 DC

The monolithic construction of the CA3049T and CA31 02E
provides close electrical and thermal matching of the amplifiers. This feature makes these devices particularly useful in
dual-channel applications where matched performance of the
two channels is required.

Lead Temperature (During Soldering):
At distance 1/16 ± 1/32 inch (1.59 ± O.79mml
from case for 10 seconds max ..

The CA3102E is like the CA3049T except that it has a
separate substrate connection for greater design flexibility.
The CA3049T is supplied in the 12·lead TO·5 package; the
CA3102E, in the 14-lead plastic dual-in-line package.

Collector·to-EmitterVoltage, VCEO . . . . . . . 15

V

Collector-to-Base Voltage, VeBO •........ 20
Collector·to·Substrate Voltage, VCIO· ..... 20
Emitter-to-Base Voltage, VEBO . . . . . . . . . .
Collector Current, Ie ................. 50

V
V
V
mA

Schematic Diagram for CA3102E

Typical Characteristics for CA3049T and CA3102E

The following ratings apply for each transistor in the devices

-The eollector of each trafl""o, 01 ttle CA3049T and CA3102E. I,
l.olated from the sublVate by afl Intagral diode. The lubitrata
(terminal 9) mutt be connected to the molt negative point In the
external clrcutt to maintain 1.ol81lon between tran,lrtori and to
provide for normal trafltlrtor action.

,

0.1

,

1

6

8

EMITTER CURRENT (I3.lgl-mA

Fig. 4-lnput affSiJt lIoltlfge liS. emitter current

"
"
"

A~

"

~

~

.0

v- (-6V)

•

<

~/

10

, "

~

Fig. t-Static characteristics test circuit for CA3,02E.

,,~

~\.;.

60

~

~.

~il " ~~~
.~
• " ~~

.f.>

'b~of.>_

"1,,'' 0:.

-

I

I

~ 1.0

",..

,.

-l-

NOTES:
.001
I. NUMBERS IN PARENTHESES REFER TO OTHER
HALF OF THE CA3049T OR CA3102E
2. BRACKETED NUMBERS REFER TO CA3102E; UNBRACKETED
NUMBERS REFER TO CA3049T

9zCS-20793

"

,.,

o.

L1' L2 - Approx. 1/2 Turn #18 Tinned Copper Wire, 5/8" Dia.
C1' C2 - 15 pF Variable Capacitors (Hammarlund, MAC-15; or
Equivalentl

"

04

060,8

,

.
o

6080 10

EMITTER CURRENT(13.19)-mA

Fig. 5-fnput biss current

liS.

emitter current.

All Capacitors in p.F Unless Otherwise Indicated
Fig.2-AGC range and lIoitagf1 gain rest circuit for CA3102E.

All Resistors in Ohms Unless Otherwise Indicated
Fig.3-200 MHz cascade power gain and noise figure rest circuit.

120 __________________________________________________________________

10

CA3049T, CA3102E

ELECTRICAL CHARACTERISTICS.t TA • 215"C

CHARACTERISTICS

TEST CONDITIONS

SYMBOLS

TYPICAL

TEST
CIR·
CUlT

CHAJIAC.
TER_
CUllY"
"0,

CA3IMIT LIMITS

FIG.

MIN.

I

TYP.

MAX.

UNITS

STATIC CHARACTERISTICS

-.

Far Each Dlffe,.ntla' Am Uti.,
Input Ott_. Volt.ge

V'O

Input Off._ Current

"0

InpL.lt BI•• Curr.nt

0.25

Tlmperet",n! Collfflc .. nt Mag"Itud. of Input·Off... Volblg.

For Each Trln,lltor
DC Forwltd a....oTemp....t"'n! CoeHlclent of
B. . .to·Emln., Volt...
Coll.ctot·Cutoff Curr.nt

~T

Coilictor-to-Emlmr

a,.. kdown Voit-ul

CB~~::~O;~~-~~~""

Ie·' mA

Vca· 10 V. IE· 0

V(BRICED

Ie" I moO., IS" 0

V(BRleSD

Ie'" ,allA,le = 0

2.

V(BRleIO

Ie = 10,..A,IS '" 0, Ie = 0

2.

V!BRIESO

IE"

IT

Vce '" 6 V, IC

Collector·B ... Capacltanca

CCB

IC" 0

Vca" 51,1

CC'

IC" 0

VCI = 51,1

Input Admittanc.

Forward Tranrfer Admittlnce

Output Admittance

~~-

v'2

v 21

··
- ,
~ ·
,
~ ':
·,
,
·
!0.:,
·,

nA

2.

••
••

2

~

5 mA

,."

dB

1.35

GH,

0.28
0.2B
1.65

pF
pF
pF

'00

dB
dB

22

dB

23
4.S

dB
dB

,

.. 19" 2mA
Bia. Voltage" -61,1
Bia. Volta.,. .. -4.21,1
1"10MHz
f .. 200 MHz
Cascode
Cascad.
VCC = 121,1
For C..cod.
Cascod.
Configuration
'3= 19" 2mA Dill. Amp.
For Diff.
Amp,ifi.r
Configuration
13""9 - 4mA
(.ach
collector
Ic:::2mA)

V22

j(~

;

IC" 0

I" 100 KH3' RS" 500 u
IC= 1 mA

V"

R""er. Trans'.r Admittance

10~A,

F;" 6-B.,..ttHlmittor I/O/tlllltl .... collector cufftlnr.
mV/oC
100

0,0013

'"

COLlECT(R O,RRENT tlcl- rnA

mV

-0,9

VCE = 6 V, Ie - 1 moO.

leRo

CM"
AGC

,

0'

Coilictol-to-Subnrit.
Breakdown Volt...
Emitter-,o-S_ Br•• kdown
VolUoDYNAMIC
CHARACTERISTICS
l/f N01. FlguretFor
Single Tren,iltor)
Geln·Bandwldth Product
(For Single Tran,il10ri

Coliector,SUbltrna Capacitance
For each Differentia'
Am lilier
Common·Mode Rejection Ratio
A C Rano-, One St.oVolta. Gain, Singl .. endltd
Ou u'
I nMnlan Pow.r Gain
Noi .. Figure

.A
IAVloC

".

VCE· 6 V

.4VeE
~T

33

,.,

14VIOI

VBE

Emitt.,Volt..,.

.A

•• 3
13.5

13- 19- 2mA

"B

7"

12

9,10

F
I+-

ff

~

r;
h
ljP

.~,

-,00

14,16,1B

1.5 + i 2.45
mmhO

0.878 +11.3

i

~
~

~J

e;~~l=
EE
&11

il

"

~

t!

ff

~

~

~

e

0

~

~

~

AMBIENT TEMPERATURE {TA1--C

15,17,19

S2CS-20'I"M

Fig. l-Colltlctor-cutoff current vs. temptU"ru,..

Catcod.

O-;O.OOB

Diff.Amp.

0-; 0.013

mmho

Cascoda

17.9 -j 30.7

Dift.Amp.

-10.5 + j 13

Cascode
Ditf.Amp.

- 0.503 -J 15
0.071 + i 0.62

26,28.30

mmho

27,29,31
20.22.24

nU"no

21,23.25

-T... minal" • '., or 7 • 8. ICA3102E) , • 12 or 6 • 7 (CA3049TI
--T_minal,'381., or 6 & " . ICA3102E)10 & 11 or .. &. 51CA3049TI

:2~'~1F=f=Rg==f~=fff~==tj:H--t-i-t-1

AMBIENT TEMPERATURE IT... 1'25·C

~2o'r-i--tlH+--t~-t+t~--t44+~~~4-~

~ .~'r-i--r,,+--r~-r+t~--~4+--~~~-+~
1\

~

~ lD'r--r-t-rH--t~r+++~--~HH--+-~~

\

0.01

to-v

DC BIAS VCUAGE ON'TEIIIMALS 2 AND

ItCI-IOIOI

2

2
4 '81
2
FREQUENCY IfI- MHz

Fig, 10- Volmge gain vs. frequency,

FI,. 9- VoItllfll"'n n. de bi.lIOItqe.
DC B'AS VOLTAGE (val-v

3D

V

V

l-'
/

./

~

~V

V
4

Fig. 1 1-G.irl-NndWidth product liS. COlleCtor cummt,

~"

I----'
6

aO.1

V

20

V

-......::::::~
tlCS-lO_

j¢'

/'

'0......-

COllECTOR OJRR£NT (lci-rnA

'0

l~

2O

bf

AMBIENT TEMPERATURE(TAI·2~·C
RSOURCE'I Kg,

AMBIENT TEMPERATURE ITA'-25·C
RSOURCE • 500n

~
\OO}(~l

V

4

6

a

I

I--

V V
'.1--

V

l7~"f' I.

V
/'"

loo~

V
V

V

1~

~
,0

. .. ---. . I
V

,

y

COl-lECTOR CURRENT IYc l-mA

10Ot(HI..____

"

!l2CB;2080B

COllECTOR CURRENT Ilcl-rnA

Fig. 12- 1h noise figure ..s. co/lector current.

Fig. 13-' h noise figure ..s. collector current.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -__________________________ 121

CA3049T, CA3102E
ELECTRICAL CHARACTERISTICS at TA a 2S'C
TEST
CIR·
CUlT

TEST CONDITIONS

SYMBOLS

CHARACTERISTICS

IFIG.
STATIC CHARACTERISTICS
For E.c:n Dlff.rlnUI' Am IIn'r
Input Off .. , VOItIIl'

DC Forward a''''0-

I

TVP.

IMAX.

UNITS

FIG.

~

6VeE

OT

'c

mv

0.25

V,O

V ••

Eminer Volt,g'

MIN.

-

I "PU' Of hi I Curr.nt
"0
Input BI,. Currlnt
'I.
16VIOI
Temp.r.tur. Co,fflel,nt Mill
"itude of Input-OffMI Volt,gl
OT
For eleh Trlnsl.'0T

Temp.r.'ur. COlfflcllnt of
S ....,a·Emltt.r Volt'gII
Collec,or-Cuioff Curr.nt
CoUIc;:lor·,o·E mitt.,
B,.kdow" Volt.g.
ColI.ctor·to·B.se
Br•• kdt.lwn Vall •
ColI.cIO'·lo·Subltrlt.
Br•• kdown VolI.g.
Emil1.r·to·B.se Br ..kdown
Vol1.ga

TYPICAL
CHARAC·
TERISTICS
CURVES

CA3102E LIMITS

0.3
13.5

'3"'g"'2mA

,.,

VeE

K

6 V

.

VCB""0V,le=O

0

ViBA)CEO

Ic=lmA,le=O

VIBAICBO

Ie

VIBRICIO

Ic=10j.lA,l e =O,Ie"'O

vlBRIEeO

'e=10j.lA,I C =O

NF

f _ 100 KH3' AS - 500
Ie = I mA

E

.74

'II

6
10

'00

60

20

60

'lO l
(f

fi'103

J -

MHz

"A

Fig. 14-lnput "dmirtance (Y II' vs. frequency.

24

20

6
fREQUENCY

0.0013

"

..

10 j.l.A, Ie "0

mV

mV/oC

-O,g

VeE" 6 V, Ie = 1 rnA

~

"A

IlV/oC

774

674

Ie" 1 rnA

~

"A

33

V

PYNAMIC
CHARACTERISTICS

lIt Noise figur.lfor
Singl. Tr.nlinor)
Glin·B.ndwidth PrOduct
(for Singl. Tr.n,ittor)
COII.etor·B ... C.paeit ....

n
.

vCE - BV. IC - SmA

e.

For E.eh Diff ...... tl ••
Am lifi.r
Common·Mod. R.j.etion Ratio
....g•• One Su"
Volte" G.ln. Singl.-Ended
Out ut
I .... llr~ion Po ....... G.I...

le· O

vCB

Ie'"' 0

VCI

dB

GH,

.

015

pF
pF
pF

22

d.

0.28

5V

...

5V

13 ~ Ig - 2 mA
B." Volt.g. - -BV
Bi .. Volt.IJtI" 4.2V
I ~ 10MH:
f = 200 MHz
encode
e ..code
Vec'" 12V

CMA

I nt!ut Admitt.nce

..

dB
dB

2

23
4.6

...

~,

-"~

for encode
Configvration

C.,code

1.5 .. i 2.45

13"19~2mA

Diff.Amp

0.878" j 1.3

Cascode

a-iO.OOB

13~lg~4mA

O.H Amp
easeode

",

..

Dill Amp

- 10.5"

i

810 2

FREQUENCY

15.17.19

If I -

MHz

.---"

17.9 - j 30.7

...

6

Fig. IS-Input .dmlttlJJ1CtI (Y 11' V$. frequency.

a - i 0.013
...

26, 28, 30
27.29.31

13

-0.S03-it5
0.071 .. j 0.62

encode
Ditf.Amp.

Y 22

9.10

dB
dB
14.16. 18

for Dif!
Amplifier
Configuration
(each
collecto'
IC::: 2mA)

Output Adminenee

~

~

"
1.35

rP mho

20.22.24
21,23.25

CASCODE AMPLIFIER
EMITTER MILLIAMPERES \l3'~1'2
OPERATING FREOUEt.iCY 10' 200 MHz
AMBIENT

.T.rmi....I., & U. or 7 & 8. (CAJ102E) 1 & 12 or 6 & 7 \CAJ049T)
•• 1 .. mi ....I.,3 & 4. or 6 & 11. ICA3102El 10 & liar 4 & 51CA3049TI

t r.:-

TE~:URE t~~> ~S~~_. :i~:

-..-+-"'••-

~+ ~~

'0

40

COLLECTOR SUPPLY VOLTAGE (Vccl-V

Fig. 16-Input IJdmirtllnce IY II' V$, collector supply voftllge.

IFf"ERENTlAl AMPLIFIER
MITTER MILLIANP[RS (13)19''.

3

CASCOO£ AMPLIFIER

:::::

~~i:~~N~:::~~!~~!Elfl~A~~~

-i

OPERATING FRECUENCV!fl: 200 MHz
S AM8/ENTTEMPERATURE(TAI'25°

r.~:=----::::::'::::i

..;:t::r::: ±:C·

."

~?4

~~ ,

",

,

i~

~

-::;- i

1·~.:·:­

:::: rE~

t:t:::;r:+..:.:.:.•.•. --

~ i t · , · · ;~; ::j::C;

.•

~;-:

cc l'+12 c:- ~.=-

COLLECTOR SUPPLY VOLTS(V

~r.::.:

:;}+

DIFFERENTIAL AMPLIflER
COLLECTOR SuPPLY VOLTS {Vcc1- +12
OPERATM FREQUECY [fJ > 200 101Hz
AMBIENT TEMPERATURE (TAlo2S"C

~~. ~r
f::F:
t ,..

'II

'"

",
10

20

30

COLLECTOR SUPPLY "VOlTAGE (VCC1-V

Fig. 17-lnput admittllJ1CtI (Y,,) V$. colltICtor rupply volt.,..

EMITTER CURRENT U3,lgl-mA

EMITTER CURRENT 1l3,lgl-mA

'0

Fig. 19-1nput tJdmlttllnCtl IY t 1) V$. emlttercurrtmt.

122 _____________________________________________________________________

CA3049T, CA3102E
Typical Output Admittance Chal1lCterlstics for CA3049T and CA3102E

~~

-. ,I
N'

~j

"'" ",
bZi'
'\

-,
-,

-.

~,

~;

-.

1\

..

-8

10'

10

(I)-MHz

FREQUENCY

~~

'22

~~

'"

u~

V

·aa

. .I.'

-2

I.

1&

. ',..

1102

FREQUENCY

(I) -

MHz

FE····:: ....
. .:::

~38E

10
20
COL.L.ECTOR SUPPL.Y VOLTAGE

o

30
(Vccl~V

Fig. 22-Outpur IIdmittlJncB (Y2i VI. collector supply IID/tage.

CASCODe: A""'LIFIER
COLLECTOR SUPPLY VOLTS l'Icc'·.12
OPERATING FREQUENCY tlj' 200 MHz
AMBIENT TEr.FEAATURE ITA j_ 25-C

DIFFERENTIAL AMPLIFIER
I
COL.LECTOR SUPPLY VOL.TS (Vce J •• 12
, OPERATING FREOUENr:Y!I!'200MHz
AMBIENT TEMPERATURE (TA I • 2~'C

'2,'

'22

'22

'22

10

,

ZO

-I

2? VI. colfsctcr IUpply IIOltagll.

Fig. 23-0utput admittance (Y

Fig. '.f-OutputlldmittM1U (Y2

i

'0
'US-3''''

o

EMITTER QJRRENT 1I3.I"gl- inA

COLL.ECTOR SUPPL.Y lJOLTAGE (VCC)~V

EMITTER CURRENT

(I"3.19 J-InA

vs. lItTIittercurrent.

Typicll Forw.d Too.mr Ch._.ristlco for CA3049T I.d CA3102E
CASCQDE AIIiPltFlEIt

~~~:O~J~:~~R~Li~ :~1~11':1~

ji

AMBIENT TEMPERATURE ITA I '

g

2'·C

¥

I'i
;~
~

il'

~74

.~I

20

~u

1\
0

-10
-'0
10

..t--!!'

I'

10'

FREQUENCY

'21

On

10

ue

20

10

CASCOOE ANPuFlER
EMITTER MLUAt.FERES 113'191'2
OPERATING FREOUENCY m.zooMHz
AMBiENT Taf'ERATURE ITA!- 25-C

AMBIENT TEMF'£RATURE (TA I - 2'·C

u'

30

I
~

A....L.IFIER

~;~MI~~:~~ER~LT1I(;:1!i :~

Ri

I~ ..U
;~

40

DIFFERENTiAl

~

..

0

~

i~

!3

~a -20

-20 •

I-~

10'

(II-MHz

~~

i

-10

-,
10

K.

..

10'

FREQUENCY

I---

'.

.

10

'10'

(II-MHI

20

50

40

COLLECTOR SU'PLY VOLTAGE (Vecl-V

Fig. 28-Forwani tramf.r admittlJnclI (Y21J VI. colltlCtor supply
lIoltllgll.

......
.. :.;. t.,.

•• >

b21

;

...

:C~~~ ~~;; ~+~~2f:h':::

--: ~

IFFERENTIAL AMPLIFIER
COlLECTQA SUPPL.Y 'IOLTS 113 - Ig"4
OPERATING FREQUENCY If I' 200 MHz
AMBIENT TEMPERATURE ITA 1_2,'C

.::..g-

:~;

021

-,.
COLLECTOR SUPPLY VOLTAGE IVcel-V

....

Fig. 29-ForwMrd 'ramftlr IIdmitt.nr:e (Y21J VI. collector supply volt-

EMITTER CURRENT 113.tgl-InA

.....,..,

o

"

.8

EMITTER CURRENT U3.lgj-mA

Fig. 31-ForWlJT(/ traM"r adm/tu"" (Y21J VI. tlt1Iltur current•

____________________________________________________________________ 123

CA3050, CA3051
Dual Differential Amplifiers

TWO DARUNGTON· CONNECTm IFFERENlIAl AlPLInERS WITH DIODE BIAS STRING
Far Law·Pawer Applicalials II FrequlCilS rr. DC te 20 1Hz
The CA3OS0 and CA3OS1 each consists of two differential amplifiers with associ8ted constant current tran-

APPLICA, TIONS
• Matched dual ampllflar.

siators on a common substrate. Each amplifier is driven

.Duol .an... amplifier.

by Oarlington-connected emitter follower inputs to provide. hiSh input impedance. low bias current, and low
offset dment. A string of diodes is i.ncluded to provide

• Dual Schmitt triggar.
Fig.1 • Schematic diagram.

.Ouallllultiviinator.

temperature-compensated bias to the constant current

• Daubl, balanced detector. and modulators

transistors and a low impedance bis$ point for lite inputs
to the differential amplifiers when a single power supply
is used.

• Balanced quadrature detector.

• S,ftthe,I ••r mlx.r.

FEATURES

• Product detector.

• Input offset current . . • • • . . . . . . . . • 70 nA max.
• Ineul bias current ...••.••.•..•• 500 nA max.

e Input offset voltage . . . • . . . . . . . . .•

MAXIMUM RATINGS, ABSOLUTE.MAXIMUM VALUES, AT TA = 25"<:
CA3050

CA3051

P')w,r Dissipation, P:
Anyone translator • • • • • • •
ISO
150
Total pecka... • • • • • • • • • •
900
For T A > 55°C. 'Derate at ••
Temperature Ranp:
OperaUnl •••••••••••.••••• -55 to +125
Storage ••••••••••••••••••• -65 to +150
LEAD TEMPERATURE (Durinl Solderinsl'

I

...,
·c

·c

AI disllIn.:e Illb t I/.l~ Inl:h 11.5') 1 OJ"mm)
from .:ase for 10 ~unds max .••••••••••••••••• +~65"c

e Input impttdonce . . . . . • . • . . . . . . •

elndependently accessibl. inputs and outputs

The loUawili1 ratlnp appl, ror each trIIa81ator In the device:

CollectQr.to-£miUer Volta"" VCEO ••••••••.••
Collector-to-Baa. Volta.e, VC80 ••; ••• '.' •.••
Collector-to-Subatrete Voltap, V00 .•. '.' ••••.
Emltte .... to-Bau Volt.p, VEBO' ••..•..•.••••
eonector Carrellt,

Ie .................... .

IS
20
20

5

5 mV max.

460 len typo

V
V

V
V

SO .....

The CA3050 is supplied in the 14-lead dual-inline ceramic package and the CA3051 is supplied
in the 14-lead dual·in:line plastic package.

'" The collector 01 eacb translator of the CA3OS0 IIlId CA3051
1_ iao'-ted from the substrate by an inteFat diode. The
aubat,.,. (tennlrutl14) mu.' be more negative than all co,·
'ettora to maintain isolation between trans I. tors and to
provide lor notm.ll Iran. I. tor sction.

TVPICAL STATIC CNARACTERISTICS

MAXIMUM VOLTAGE RATINGS
The following chart gives the range of voltages which can be Ipplled to thl tmninols
listed vertically with respect to the terml ...lll1sted horizontllly. For .xample. the
voltage range between vertical tmnlnal 2 Ind horizontlll tmninal3 is +Ii to -2 volts.

MAXIMUM
CURRENT RATINGS

TERM·

INAL

to

No.

11

t2

13

14

TERMINAL
No.

liN
mA

+1

0.1

-6

+5
·2

+14

+14

+2.6

+2.5

·14
·14
Note1 Nate1

+1
·1

50

+3
·1

50

+20

·2.5
-2.5
Note3 Note4

lOUT
mA

50

..

I

:5 COLLECTOR SUPPLY VOLTS (VccI-+8
AMBIENT TEMPERATURE(T,I_25-C

2."

~

i
~
i

~

2

r'---r-

I.'
1

a"

50

·1

~I

. . .. . . . ..
I

I

•

QUIESCENT BIAS MILLIAMPERES

+10
·10

+1
·20

+18
·1

+14

0.1

+20

·2.5
+14

+20

·2.5
Note 2

+18
·1

20
+20

·1

+20

·1
+10
·10

50

·1

~:

10

0.1

+18
·1

11

0.1

12

+20

12

"

+1

11

Note 3

+2.5
·14 •
No.. 4

·1

14

-6

50

13

0.1

Ref.

S....
......

YJ

0.1

+20

+18
·1

10

Flg.2(a) - 7ypico' input oH~.t yoltage
quiescent hlas current.

50

·1

+1

UCS-IMI3

50

·1

Note 2

~oo

~

tI,)

14

100

NOTE 1: This rating 1.lmpor1lnt only when termlnll 5 I, more
positive than terminal 8.

NOTE 4: This rating it imPortsnt only when terminal 11 is mar.
positi .. thin' "mlnal 10.

NOTE 2: This rating i. important only whIn terminal. i. more
positive thin terminal 5.
NOTE 3: Thi' nting is important only whll1 terminal 101. men
positive than terminal 11.

-Vol"l11 are not normally applied betwk'" th•• termlnah. Voltages appearing
betwewI th_ termini.. will bI ..fe If the ,pedfled limits between all othar
termini" an not eXCleded.

.

AIIBENT TEMPERATURE ITAI--c

Flg.2(h, - T"lcal input .11••,

y./ra,. y.

amhlent temperat..... ,

124 ______________________________________________________________

CA3050, CA3051
ELECTRICAL CHARACTERISTICS at T A = 2SoC

CHARACTERISTICS

SYMBOLS

60 AMBIDH TEMPERATIJRE ITA"25'C

TEST CONDITIONS

TEST
CIR·
CUlT

LIMITS
CA3050!CA3051

FIG.

MIN. 1 TYP. 1 MAX.

TYPICAL
CHARAC'
TERISTICS
CURVES

UNITS

-; 50r---t--t-t-t-t--t--t-t-t-t-+-t-f+-l

~

STATIC

--

Amplifier Characteristics

Inpul Offsel Vollage

VIO

Input Offsel Current

110
liS

Input Bias Current

-

I(14~:12) I

Quiescent Operating Current Ratio

(16.17)
-1-3-

DC Forward Base-Io-Emitter Vqltage

500

0.9

1.00

1.13

mV
nA
nA
-

5
70

2a,b
3a,b
4a,b

'j

. ,. '00

I
.. 6 8 10
QUIESCENT BIAS MILLIAMPERES (131

5a,b

Fig.3(a) . Typical input ollset current
quiescent bias current.

V "3V
CE

6V BE

Emilter Voltage

1.5
7
200

VCC " + 6 V, 13" 2 rnA

VBE

Telf1lE!rature Coefficient of Base-to-

-

LiT

{'C" 50"A
ImA
3 rnA
lOrnA

-

VCE" 3V, IC" I rnA

-

VCB"IOV,IE"O
IC " I rnA, IB " 0
IC" 10~,IE"0

-

-

0.645 0.700
0.725 0.800
0.760 0.850
0.805 0.900
·1.9

-

mV!oC

V

6

liS

COlLECTOR SUPPLY VOLTS (VCC)"6

"0
7

Transistor Characteristics

Collector-CutoH Current

ICBO

Collector-la-Emitter Breakdown Voltage
Collector-la-Base Breakdown Voltage
Collector-la-Substrate Breakdown Voltage
Emitter-la-Base Breakdown Voltage
DYNAMIC

VWIllCEO
V(BR)CBO
V(BRlCIO
V(BR)EBO

-

IC " 10~, ICI " 0
IF" 10 pA, IC " 0

-

0.002

100

nA

8

IS
20

24
60

V
V

20
5

ro

-

7

-

-

V
V

-"

'0

100

12:5

AMBIENT TEMPERATURE !TAI-'C

Transistor Characteristics

Emitler-lo-Base Capacitance

1

-

I

CEB
CCR

1 VER" 3 V, IE " 0

CollectoHo-Base Capacitance

I VCR"3V,IC"0

- I - I

-

Collector-Io-Substrate Capacitance

1

CCI

1 VCS"3V,IC"0

0.78

-

0.471

- 1 - 1 1.92 1

-

pF
pF
pF

9
9
9

I
1

Fig.3(b) . Typical input offset cu".nt vs
amb ient temperature.

Amplifier Characteristics

Gain-Bandwidlh Prcxlucl
(For Single Transistor)

Forward Transadmittance
(Wilh single-ended input and oulput)
Bandwidth al·3 dB Point

fT

VCE "5V,IC"3rnA

-

-

600

-

MHz

10

IY2d

VCC" 10V, 13" 2mA
f" I MHz

11

7

9

11

mmho

11

BW

VCC" IOV,13"2mA

11

-

4.3

-

MHz

11

Input Impedance

ZI

VCC" IOV,13"2mA
f" I KHz

12

-

460

-

ill

12

Oulput Impedance

Zo
CMR

13 " 2 rnA, f " I KHz
I "2 rnA, f " I KHz

13

-

-

170
65

-

Common-Male Rejection Ratio

ill
dB

13
-

AGC Range

AGC

~e:m;na~N!.i ~r~~~ed

11

-

60

dB

-

-

10e OLLECTOR SUPPLY VOLTS (Vec'- t6
6 1oI81ENT TEMPERATURE (TA'-25-C

INPUT EliAS NANOAMPERES (Ill

Fig.4(o) - Typieol quieseent bias eurrent vs
input bias eurrent.

f

COLLECTOR SUPP!.Y VOLTS (VCC)·+6

QUIESCENT BIAS CURRENT RANGE

O.l~I3S.lomA

t;;~I,t

~H'

o

~

AMBIENT TEMPERATURE (TA)'25'C
COLLECTOR SUPPLY VOL.TS (VCC)· ... S

1.1f-+-+-+++-t-++f-t----1-+-tM
1--

f---

g
&

~

.,.
o

,,.

O.8f-+--+-+++-t-++f-t----1-+-t+1

~
4

~

a 0.1

4

6

e

I

4

6

QUIESCENT BIAS MILLIAMPERES tI31

Fig.4(b) - Typical normalized input bias current vs
ambient temperature.

Fig,S(a) . Typif;OI quiescent operating current
rotio "oS quiescent bios current.

a 10

0.8
-75

~

-50

-25

AMBIENT TEMPERATURE (TAI- 6 C

Fig.5(b) - Typic::al quiescent operating current
ratio vs ambient temperature.

_______________________________________________________________________ 125

CA3050, CA3051
10

COLLECTOR-lO-EMITTER VOLTS IV CE )'+3

w
:'

-~
':::0.8

V

~01~

~

0°70

~

>0.7

~~0.6

/'"

!

/'

,:,

~ O.6~ -r-.- --b1fTj-+-++++-+-++H--+-i

,":,0.5

~

/V
Z

466

"

EMITTER CURRENT UEI·Q

V

II

;;; 0aof--+--+-H+-+-iH-++-1-t-crP1F-t-i

"g

!

·0'-75

,

-50

·25
0
75
AMBIENT TEMPERATURE tTAI_oc

EMllTER MILLIAMPERES U:EI

Fig.6 . Typical static bon-to-emitter voltage

Fig.7 - Typical base-to·emitter voltage characteristic
vs ambient temperature lor each transistor.

characteristic vs emitter current for all transistors and forward cljoc/e voltage drops.

AM6IENT TEMPERATURE ITAI-'C

92CS-15195

Fig.8. Typieol collectoi-to-bose cutoff current vs
ambient temperoture for each transistor.
VCC-IOV

r

COLLECTOfI-TO-£MlTTER VOLTS lVa'o.!!
AMBIENT TDlP£RATURE IT.t.I·~~C

O

£!!OOr-+-t-rHr-i--t7rrr-+-t--j-~>i

i~ 'OOf--+-+-H-t--cl.'/'-t-+t+-+--++++-+I\
)
~300f--+-+~~~--~~r-+-+4-H-~

i2oo.~~-+>f~-4--+-~~~-+4-H--1
~

100

:/

Fig.9. Typical capacitance for each transistor.

50,.r
4

6 SQI

8 I

I.
RESISTORS ARE
IN OHMS

~:ri~~~e~i~le,~nn~i!? ~-~:Ij;ii~;~n 1

EMITTER MlLLIAMPERESiIEI

Fig. JO - Typical gain-bonelwjdth proJuct (IT) lor
each transistor vs emitter current.

position 2 fOI Othel diffelential

amplifiel,

vcc- IOV

Fig. J J(a) - Test circuit lor lorward transaelmiHance,
·3 dB bandwidth, and AGe range.
10000
6

4

2468

0.001

2.,,8

0.01

24GB

0.1

2469

I

COLLECTOR SUPPLY VOLTS(VCC'-+lO
QUIESCENT BIAS CURRENT CI3'-2ff1A
AMBIENT TEMP£RATUREtTA'o25.C

2468

10

100

FREQUENCY Ifl-lIItll

Fig. JJ(b) - Typical rliHerential amplifier forward t,ons-

admittance with single-ended output vs frequency.

'0
1246810

VEE-ADJUST FOR :r~;-~~4~!I

Fig.J2(o}. Test circuit lor input impeelonce.

Q

(fI-kH~

Fig.'2(b) - Typical input impedance YS Irequency
with output shorf.circuited.

1000 COLLECTOR SUPPLY VOLTS (Vccl'.'iO
6 QUIESCENT BIAS CURRENTII3"2mA
4 AMBIENT TEMPERATURE"ITAI_ 25'C

1
~

2468100246100024610000

FREOUENCY

r--

goo'auED
(30K.IOK1~
lOUT'V2

\it (30K+IOK)-IOK

Fig.J3(o'. Test circuit for output impeclonee.

10

2
46e
2
100
FREQUENCY (II-kHz

468
2
1000

466
10000

Fig.13(b) - Typical output impedance vs frequency
with input short-circuited.

126 __________________________________________________________________

CA3058, CA3059, CA3079

Zero-Voltage Switches
For 50/60 and 400 Hz Thyristor Control
Applications
The RCA·CA3058, CA3059, and CA3079
zero·voltage switches are monolithic silicon
integrated circuits designed to control a
thyristor in a variety of AC power switching
applications for AC input voltages of 24 V,
120 V, 208/230 V, and 277 V at 50/60 and
400 Hz. Each of the zero·voltage switches
incorporates 4 functional blocks (see Fig. 1 )
as follows:
1. Limiter·Power Supply-Permits operation
directly from an AC line.
2. Differential On/Off Sensing AmplifierTests the condition of external sensors or
command signals. Hysteresis or propor·
tional-control capability may easily be im·
plemented in this section.
3. Zero·Crossing Detector-Synchronizes the
output pulses of the circuit at the time
when the AC cycle is at zero voltage point;
thereby eliminating radio·frequency inter·
ference (RFI) when used with resistive
loads.
4. Triac Gating Circuit-Provides high·current
pulses to the gate of the power controlling
thyristor.
In addition, the CA3058 and CA3059 pro·
vide the following important auxiliary func·
tions (see Fig. 1):
1. A built-in protection circuit that may be
actuated to remove drive from the triac if
the sensor opens or shorts.
2. Thyristor firing may be inhibited through
the action of an internal diode gate con·
nected to Terminal 1.
3. High·power de comparator operation is
provided by overriding the action of the
zero-crossing detector. This is accompl ished
by connecting Terminal 12 to Terminal 7.
Gate current to the thyristor is continuous
when Terminal 13 is positive with respect
to Terminal 9.
For an explanation of these functions see
Operating Considerations.
For de·
tailed application information, see companion
Application Note,ICAN·6182, "Features and
Appl ications of RCA Integrated-Circuit Zero·
Voltage Switches (CA3058, CA3059, and
CA3079)".
The CA3058 is supplied in a hermetic 14·lead
dual·in·line ceramic package. Types CA3059
and CA3079 are supplied in 14·lead dual·in·
line plastic packages.

NEGATIVE TEMPERATURE COEFFICIENT

AC Input Voltage
150/60 or 400 Hz)
VAC

Input Series
Resistor (RS)

Dissipation Rating
for RS

U2

NOTE:
Circuitry, within shaded areas, not included in

CA3079

W

• See chart

24
120
208/230
277

0.5
2
4
5

2
10
20
25

.. Ie

= Internal

Connection· . 00 NOT USE
(Terminal Restriction applies only

to CA30791.

Fig. I-Functional block diagram of CA3058, CA3059. and CA3079.

Features

CA305B

- 24V, 120V, 20B/230V, 277V at 50 6O,or
400 Hz operation . ................... .
•

_
•

•
•
_

V
V

Differential Input ................... .
low Balance Input Current (max.l·fJA .... .
Built-in Protection Circuit for
opened or shorted sensor (Term. 141 ....•
Sensor Range (Rxl· kn ............. .
DC Mode (Term 121 ..•..........•..••.
External Trigger (Term. 61 .......•...•••
External Inhibit (Term. 11 .••...•...••..

V
V

CA3079

V
V
2

V

V

2to 100

V
V
V
14

- DC Supply Volts (max.! .•.••.....•...•
_ Operating Temperatur. Range· oC •...•••

MAXIMUM RATINGS,
Absolute-Maximum Values at TA

~

= 250 C

DC SUPPLY VOLTAGE (BETWEEN TERMS. 2
AND71:
CA3058, CA3059 •...•...•...•...... 14 V
CA3079 ••........•.••..•...•...... 10 V
DC SUPPLY VOLTAGE IBETWEEN TERMS. 2
ANDBI:
CA3058, CA3059. • . . . . . . . . . . . . . . . .. 14 V
CA3079 •.•...............•........ 10 V
PEAK SUPPLY CURRENT ITERMS. 5 AND 7)
.........•...........•.. :!SO mA
OUTPUT PULSE CURRENT ITERM. 41
150mA

2to 100

2t050

V
V
V
14
-55 to +125

10

POWER DISSIPATION:
Up to T A =75 0 C - CA3058 ....•..... 700 mW
Up to T A =55 0 C - CA3059,CA3079 ... 700 mW
Above T A =75 0 C - CA3058
......... " Derate Linearly 8 mW/oC
Above T A=550C - CA3059,CA3079
. . • . . . . •• Derate linearly 6.67 mW/oC
AMBIENT TEMPERATURE RANGE:
Operating . ................ '. -55 to +125 0 C
Storage ..............•..... -66 to +150 0 C
LEAD TEMPERATURE (DURING SOLDERING):
At a distance 1/16" ± 1/32" (1.59 ±0.79 mm)
from case for 10 seconds max . .. , ... +265 o C
IZO-V RWS, ~"O-HI OPERATION
INPUT RESISTANCE !RS!'IO kll
NO £ItTERNAL LOAD

Applications:
-

Relay control
- Heater control
Valve control
- Lamp control
Synchronous switching of flashing lights
On-off motor switching
Differential comparator with self-contained
power supply for industrial applications
- Photosensitive control
- Power one-shot control

100,F

Fig. 2(a)-DC supply voltage test circuit for
CA3058, CA3059, andCA3079.

"I

Fig. 2(b)-DC supply voltage vs. ambient
temperature for CA3058, CA3059
andCA3079.

________________________________________________________________ 127

CA3058, CA3059, CA3079
M"XIMUM VOL T"GE R"TlNGS atT"
TERM·
INAL
NO.

~ite
3

1
Note 3

2

3

4

5

.. ..

6

Not Not
1
3

7

15 10
0 -2

MAXIMUM
CURRENT
RATINGS

= 25°C
8

10 11 12 13

9

Note
3

·.

,

0 0 2 0 oA 0 4 0 0 0
-15 -15 -14 -14 -14 -14 -14 -14 -14

2

0
-15

3

.
. . ··
7
-7

5
Note 1

14
0

6

Note 3

7

·
·

14
0

20
0

10
0

8
9

2,3

.

10
11
12
Note 3

13

liN

lOUT

rnA

rnA

10

0.1

0 0 150
-14 -14

.···

2
-10

4

14

Notel

120 v R.U. SOI6I).H. OPERATIOIoI
AlIBIENT TEIiPERATURE (TAl' 2,. C

10

·

0,1

150

50

10

EXTERN~L

-current for CA3058, CA3059, and
CA3079.

·· · ·
· ·

'.... CP.

2.5 14 6
2.5 0 -6

0,1

,'1;;:;11'"

2

·· ·
· ··
· ···
·
·· ·

14

LOAD CURRENT (Ill _ .. A

Fig. 2(c)-DC supply voltage vs, external load

50

50

2·

2

in!
!;~

GATE TRIGGER VOl TS (YGTI
!ISH1\8

Fig. 3-Gate trigger current vs. gate trigger
voltage for CA3058, CA3059, and CA3079.

Note 3

This chart gives the range of voltages which can be applied to the terminals Iisted horizontally
with respect to the terminals listed vertically. For example, the voltage range of horizontal
Terminal 6 to vertical Terminal 4 is 2 to -10 volts.

Note 1 - Resistance should be inserted between Terminal 5 and external supply or line voltage for limiting current into Terminal 5 to less than 50 rnA.

OSOLLOSCOPE

WITH

Note 2 - Resistance should be inserted between Terminal 14 and external supply for limiting
current into Terminal 14 to less than 2 rnA.

HIGH-GAlM
IMPUT

Note 3 - For the CA3079 indicated terminal is internally connected and, therefore, should
not be used.
AFar CA3079 (0 to -10 V).

*Voltages are not normally applied between these terminals; however, voltages appearing
between these terminals are safe, if the specified voltage limits between all other terminals
are not exceeded.
100 _,

ALL RESISTANCE VALUES ARE IN OHlilS

Fig, 5 (a)-Peak output (pulsed) and gate trigger

"

current with internal power supply

LIN[
INPUT

test circuit for CA3058, CA3059,
andCA3079,

0,

, 0,

i

0,
,~

'''''::IIU';(O
IJol{DIIIV[

I,

..'"

I

3

~IOO

,l ____________ _
ALL R[SISTolNCE VALU(S.IIfIE 1I\I0",,,,s

FAIL-SUE
,~,

INHI8IT
INPUT

lie.

NOTE,CIRCUITIIY WITHIN 5HAOEO A~(~S
NOT INCLUD£O IN C~3079

'lC, ~~~~:I~~'~NC~~:~'~~'~~LY-~' ~~7S;1 n(A""N~L

Fig, 4- Schematic diagram of CA3058, CA3059, and CA3079,

0"
.'"

-15

-50

-25

0

25

50

15

100'

125

AM81EM1 TEMPERA1URE ITAI-·C

.2C'-lao..

Fig, 5(b)-Peak output current (pulsed) vs,

ambient temperature for CA3058,
CA3059, and CA3079.

128 _______________________________________________________________________

CA3058, CA3059, CA3079
y+

ELECTRICAL CHARACTERISTICS (For all types, unless indicated otherwise)
All voltages are measured with respect to Terminal 7.

CHARACTERISTIC

TEST CONDITIONS
TA = 25 0 C
(Unless Indicated Otherwise)

LIMITS
Min.

Typ.

UNITS

Max.

For Operating at 120 V rms, 50·60 Hz (AC Line Voltage)DC Supply Voltage, Vs
Inhibit Mode
At 50/60 Hz
At 400 Hz
At 50/60 Hz
Pulse Mode
At 50/60 Hz
At 400 Hz
At 50/60 Hz
At 50/60 Hz (CA3058)
See Fig. 2

Gate Trigger Current, IGT(4)
See Figs. 3,5(a)

Peak Output Current (Pulsed),
IOM(4)
With Internal Power Supply

AS = 8 kn, I L = 0

6.1

6.5

7

V

RS-10kn,IL =0
RS-5kn,IL 2mA

-

6.S
6.4

-

V
V

RS=8kn,IL =0
RS-10kn,IL -0
RS-5kn,IL -2mA
RS 8kn,IL 0
T A = -55 to +125 0 C

6

7

-

6.4
6.7
6.3

-

V
V
V

5.5

-

7.5

V

-

105

-

mA

50

84

-

mA

90

124

-

mA

-

170

-

mA

-

240

-

mA

Terms. 3 and 2 connected,
VGT = 1 V
Term. 3 open, Gate Trigger
Voltage (VGT) = 0
Terms. 3 and 2 connected,
Gate Trigger Voltage (VGT)=O

Term. 3 open, V -12 V, VGT-O
With External Power Supply Terms. 3 and 2 connected,
V+=12V.VGT=0

-

See Figs. 5, 6

Inhibit Input Ratio, V91V2
All Types
CA3058

Voltage Ratio of Term. 9 to 2
T A - -55 to +125 0 C

0.465 0.485 0.520
0.520
0.450
-

AlL RESISTANCE
VALU!S ARE
INDtUlS

Fig. 6(a)-Peak output current (pulsed) with~*R1
external power supply test circuit for

CA3058 and CA3059.
120 v RIiS, 50/60-+1. OPfRATIOM

"'MBIEHl TEMPERATURe: (TAl. 2S"C
GATE TRIGGfR VOl TAG! IV T). DV

10
IS
S
EKTEIU.... L POWER SUPPLY VOL lS IV +)

Fig. 6(b)-Peak output current (pulssd) vs.
external power supply voltage
for CA3058 and CA3059.

-

See Fig. 7

Total Gate Pulse Duration: *
For positive dv/dt, tp
50·60 Hz
400 Hz
For negative dv/dt, tN
50·60 Hz
400 Hz

70

100
12

140

JlS
J.1S

70

100
10

140

J.1s
J.1s

CEXT=O
REXT = 00

-

50
60

-

J.1S
J.1S

-

0.001

T A - -55 to +125 0 C

-

10
20

J.1A
J.1A

-

220
220

1000
2000

nA
nA

CEXT =0
CEXT - 0, REXT -

00

CEXT= 0
CEXT - 0, REXT -

00

See Fig. 8

Pulse Duration After Zero
Crossing (50-60 Hz):
For positive dv/dt, tp1
For negative dv/dt, tN 1
See Fig. 8

Output Leakage Current, 14
I nh ibit Mode:
All Types
CA3058
See Fig. 9

I nput Bias Current, II
CA3058, CA3059
CA3079
See Fig. 10

nC""18064

Fig. 6(c)-Peak output current (pulsed) vs.
ambient temperature for CA3058

and CA3059.

_____________________________________________________________________ 129

CA3058,CA3059, CA3079
ELECTRICAL CHARACTERISTICS (For all types, unless indicated otherwise)
All voltages are measured with respect to Terminal 7.
TEST CONDITIONS
TA-25o C
(Unless Indicated Otherwise)

CHARACTERISTIC

(Cont'd)

LIMITS

RS
10k

UNITS

120 V RMS

Min.

60 H%

TVp. \Max.

For Operating at 120 V rms, 50·60 Hz (AC Line Voltage)Common· Mode Input
Terms. 9 and 13 connected
Voltage Range, VeMR

-

1.5 to 5

-

V

Sensitivity, t:N13*
(Pulse Mode)

-

6

-

mV

Term. 12 open

ALL RESISTANCE VALUES L---it----'
ARE IN OHM.S
10011 F

See Figs. 5(a), 12
*Required voltage change at Term. 13 to either turn OFF the triac when ON or turn ON the triac when OFF.
* Pulse duration in 50 Hz applications is approximately 15% longer than shown in Fig. 8{bl.
• The values given in the Electrical Characteristics Chart at 120 V also applv for operation at input voltages
of 24 V. 208/230 V. and 277 V. except for Pulse Duration. However. the series resistor (RS) must have
the indicated value, shown in the chart in Fig. 1, for the specified input voltage.

92ss-mB

Fig. 7(a}-lnput inhibit voltage ratio test
circuit for CA3058, CA3059, and
CA3079.

120-V RMS, 50-60 HI OPERATION

120 yRIIS. !In/60. .+hOPERAYION
AIIBJENTTEIIPERATUREITAI_ 2S o C

t

!
o

i

~O.50

gO.45

•"~O,40
."

-50

-25

0

25

~

75

100

J.LLIIESIHAHCEVJ.LUES

'25

AMBIENT TEMPERATURE (TAI-·C

tlOTE CIRCUITRYWITHltlSflJ.OEtlJ.REJ.
NOT INCtUDED INCAl019

MI

M2

0.0l

0.04

O.OJ

006

EXTERMALCAPACITANCE[CiExnl ..... F

Fig. 7(b}-lnput inhibit voltage ratio vs. ambient
temperature for CA3058, CA3059,
andCA3079.

1lOV RIIS5Q/6Q.H1QPERATION
AllIIENTTEliPEitATUIIE(TAI'2s<'C

Fig. 8(bJ- Total gate pulse dUration vs. external

Fig. 8(a}-Gate pulse duration test circuit with
associated waveform for CA3058,

capacitance for CA3058, CA3059,
and CA3079.

CA3059, and CA3079.

....::

100,

'" r------ 120 Y IIIIS, 400-H, OPERATION

120V RMS so/eO-H, OPERATION

A/liBIENTTEIiPERATURE(TA,)·2SoC

1/
I

0.2

O.oJ

G.O'

O.OS

006

e.G7

o.oa

0.09

0.1

."

-t-t•

EnEitHALCAPAOTANCE(GEnl)-·F

EkTERIUl.RESISTAHCE[R(EXTI)_kn

Fig. 8(c}-Pulse duration after zero crossing vs.
external capacitance for CA3058,

Fig. 8(dJ-Total gate pulse duration vs . . external

CA3059, and CA3079.

resistance for CA3058 and CA3059.

100

RHfim

~m·

0.'
-80 -60 -40 -20

/

0

20

40

60

80

100

120

140

AMBIENT TEMPERATURE (TA1-· C

Fig. 9-0utput leakage current {inhibit mode} vs.
ambient temperature for CA3058, CA3059,
andCA3079.

130 _____________________________________________________________________

CA3058,CA3059, CA3079
220V RMS
~0/60·Hl OPERATION

V"· 6V

600

2:2:0 V RMS, ~O/GO-Hz OPERATION
INpUT RESISTANCE \RS}'20 kl'l

400

---

I

)00 INPUT RESISTANCE (RS}'IOk,Q

.,.

'00
,-,---,~---,

,
--,

b;:::= ~

g. :::::::: F~

f - I--

f-- I---:
CURVE

004

,

:.--

c

,

FREOUENCY

-

A
B .Iro
60H,
H'} 'p""
TIVEdv/dt)_
po" .

g
0.02-

- J=--

~g ~:} 'N\~~:E NdEv~:;}

0"

0'"

EXTERNALCAPACITANCE-I'F

0.02

0.06

0.04

"

O.OB

Ibl

EXTER~ALCAPACITANCE-f4F

lal
Fig. to-Input bias current test circuit for CA3058.
CA3059, and CA3079.

220VR'-IS

~0'60- Hr OPERATION
r.OOINPUTRESISTANCE
IRS}·20.n

220 II FlMS. ~0/60-Hl OPERATION
INPUTRESISTANCEIRS)'IOldl

SENSOR RESISTANCE~'

~i
~~

k.o.

~~

400

~~

TERNS. 7 AND 12 COMHECTED

DC GATE CURRENT

!)8 ",",0

"'ODUC"'~

...-J.

C"''!I~\

~g~~} 'NIIF~:/~'(IG.nI~(

t~ ~~} 'PI IFd~~~?SITI~(
EXTER~AL

CAPACITANCE-"f

(XTERNALCAPAC,rANCE-I'F

Idl

lei

Fig. "-Relative pulse width and location of zero crossing for 220-volt operation for CA3058. CA3059,
andCA3079.
•~

-50

-25

0

25

50

75

100

AMSIEHT TEMPERATUM IT,I-"C

Fig. 12-SensitivitV vs. ambient temperature
for CA3058, CA3059, and CA3079.

AdIf)4TTElilPIERATURIE_O(

Fig. t3-0perating regions for built-in protection
circuit for CA3058 and CA3059.

125

OPERATING CONSIDERATIONS
Power Supply Considerations for CA3058,
CA3059, and CA3079
The CA3058, CA3059, and CA3079 are in·
tended for operation as self·powered circuits
with the power supplied from an AC line
through a dropping resistor. The internal
supply is designed to allow for some current
to be drawn by the auxil iary power circuits.
Typical power supply characteristics are given
in Figs. 3(b) and 3(c).
Power Supply Considerations for CA3058
and CA3059
The output current available from the internal
supply may not be adequate for higher power
applications. In such applications an external
power supply with a higher voltage should be
used with a resulting increase in the output
level. (See Fig. 5 for the peak output current
characteristics). When an external power
supply is used, Terminal 5 should be can·
nected to Terminal 7 and the synchronizing
voltage applied to Terminal 12 as illustrated
in Fig. 5(a).
Operation of Built-in Protection for the
CA3058, CA3059
A special feature of the CA3058 and CA3059
is the inclusion of a protection circuit which,
when connected, removes power from the
load if the sensor either shorts or opens. The
protection circuit is activated by connecting
Terminal 14 to Terminal 13 as shown in
Fig. 1. To assure proper operation of the pro·
tection circuit the following conditions
should be observed:
1. Use the internal supply and limit the ex·
ternal load current to 2 mA Nith a 5 kn
dropping resistor.

2. Set the value of Rp and sensor resistance
(RX) between 2 kn and 100 kn.
3. The ratio of RX to Rp, typically, should
be greater than 0.33 and less than 3. If
either of these ratios is not met with an
unmodified sensor over the entire anticipated temperature range, then either a
series or shunt resistor must be added to
avoid undesired activation of the circuit.
If operation of the protection circuit is de·
sired under conditions other than those
specified above, then apply the data given
in Fig. 13.
External Inhibit Function for the CA3058
and CA3059
A priority inhibit command may be applied
to Terminal 1. The presence of at least +1.2 V
at 10 J1A will remove drive from the thyristor.
This required level is compatible with DTL
or T2L logic. A logical 1 activates the inhibit
function.
DC Gate Current Mode for the CA3058
and CA3059
Connecting Terminals 7 and 12 disables the
zero·crossing detector and permits the flow
of gate current on demand from the differ·
ential sensing amplifier. This mode of opera·
tion is useful when comparator operation is
desired or when inductive loads are switched.
Care must be exercised to avoid overloading
the internal power supply when operating
in this mode. A sensitive gate thyristor
should be used with a resistor placed between
Terminal 4 and the gate in order to limit the
gate current.

________________________________________________________________________ 131

CA3060, CA3060A Types
Operational Transconductance
Amplifier Arrays
APPLICA TlONS
•

• Active filters
• Gyrators

• Multiplexers
• Multipliers
• Strobing and gating functions

• Mixers

• Sampte and hold functions

•

Generic applications of the OTA are described in ICAN6668, Applications of the CA3080 and CA3080A High·
Performan'?8 Operational Transconductance Amplifiers.

For low power conventional operational amplifier
applications

Comparators

The CA3060AD, CA3060BD, and CA3060D are supplied in
a hermetic 16·lead dual-in-line ceramic package which can be
operated over the full military temperature range, ·550 C to
+1250C. The CA3060E is supplied in a 16-lead dual-in-line
plastic package and is operational from -400C to +85o C.

• Modulators

FEATURES
• Low power consumption - as Iowa. l00p.W per amplifier

MAXIMUM RATINGS, AllsD/UN Maximum Va/11ft at TA - 2SOC

• Independent biasing for each amplifier

DC Suppfy Voltage lbetl/\/een V+ and V' terminals):

Fig.1-Functional block diBt/f"Bm for NCb type in the
CA3060 family.

Device Dissipation:

CA306DAD, CA3060BD, CA3000E . . . .. . . . .. . .. 36V 1±18V)
CA3060D . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .... 14 V (±7V)

• High forward transconductance

• Programmable fange of input characteristics
• Low input bias and input offIet current
• High input and outpUt impedince
No effect on daviee under output short-circuit conditions

Differential Input Voltage leach amplifier!:
CA3060AD, CA3060BD, CA3000E . . . . . . . .
CA3060D • • . • . . . . . . . . . . . • • . . . . . . . . . . . . . .

. .... ±Sv
. .... ±Sv

DC Input Voltage .•.....•....•..•.........

. . V+ to V-

Input Signal Current leach amplifier of each type); • .

• Zener diode bias regulator

. ...

±I

Total Package of each type up to T A'" 750C .......... 490 rnW
Above T A'" 7SoC ..•.. : ......... Derate linearly 6.67 mW/oC
Temperature Range:
Operating CA3060E ................ .
Sto)age CA3060AD, CA3060BD. CA3000D.
CA3060E ....•

mA

Amplifier Bia$ Current (each amplifier of each type) ...•..... 2 mA

RCA-CA3060AD. CA3060BD. CA3060D. and CA3060E.
monolithic integrated circuits, are arrays of three independent Operational Transconductance Amplifiers. This type of
amplifier is a new circuit concept that has the generic
characteristics of an operational voltage amplifier with the
exception that the forward gain characteristic is best
described by transconductance rather than voltage gain
(open~loop voltage gain is the product of the transcon·
. ductance and the load resistance,9mR L)' When operated into a
suitable load resistor and with provisions fC?r feedback, these
amplifiers are well suited for a wide variety of operationalamplifier and related applications. In addition, the extremely
high output impedance makes these types particularly well
suited for service in active filters.

Bias Regulator Input Current .....•........
Output Short-Circuit Duration- ..

. ·55 to +125 0 C
.. ·40 to +85 0 C

CA3060AD. CA3060BD. CA3060D .

.••...• ·5mA

. .. ·65 to +lS()DC

Lead Temperature lOuring Soldering):
At distance 1/16 ±1/32 in. (1.59 ""!:O.79 mm)
from case for lOs max.......
. .......... +300oC

............ No limitation

·Short circuit may be applied to ground or to either supply.

r-------,

ZENER BIAS REGUlATOR

I

..

,

v•

I

I'

2 SUPPLY VOLTAGE:V -6V,V-'-6V
V+.I!iV,V-·-I!iV

I
I

I
I

I [,)-----+~+-----,
L _______ --'

The

three amplifiers in the CA3060 family are identical
push·pull Class A types which can be independently biased to
achieve a wide range of characteristics for specific applica'
tions. The electrical characteristics of each amplifier are a
function of the amplifier bias current (I ABC). This feature
offers the system designer maximum flexibility with regard
to output current capability, power consumPtion, slew rate,
input resistance, input bias current, and input. offset current.
The linear variation of the parameters with respect to bias
and the ability to maintain a constant dc level between input
and output of each amplifier also makes the CA3060 suitable
for a variety of non·linear applications such as mixers.
multipliers, and modulators.
In addition; the types in the CA3060 family incorporate a
unique Zener diode regulator system that permits current
regulation below supply voltages normally associated with
such systems.

vB

A INVERTING INPUT OF AMPLIFIERS I, 2. ANO 31S ON TERMINAL
Nos. 13, 12 AND 4, RESPECTIVELY
NON·INVERTING INPUT OF AMPLIFIERS 1; 2, AND 3 IS
TERMINAL Nos. 14, II, AND 5, RESPECTIVELY
• OUTPUT OF AMPLifiERS " 2, AND 31S ON TERMINAL Nos. 16.9,
AND 7, RESPECTIVELY
o AMPLIFIER BIAS CURRENT OF AMPLIFIERS 1,2, ANO 3 IS ON
TERMINAL Nos. 15. 10, AND 6, RESPECTIVELY

o

..

..

"10

..

88100

AMPI.IFIER BIAS CURRENT I.lABel

-,.A

,

1000

I2tS-.-II!

Fig.3-lnput ofhllt voltage w. amplifier bias cummt.

92tS-I~860"'1

Fig.2-Simp/ified schematic diagram showing bias regulator and
one operational transconductance amplifier for
each type of the CA3060 family.

10. AMBIENT TEMPERATURE (T A}o 25·C
•

...

10
100
1000
AMPLIFIER BIAS CURRENT IIABCt-IlA tICS-IMI'

Fig.4-lnput offlst current vs. amplifier bi. cummt .

0-0.

SUPPLY VOLTAOE: V .... 6V.V-.-8V

.. ...

10
100
AMPLIFIER BIAS CURRENT (lABCI-IlA

Fig.5a-lnput biBl curtent
biasculTtll1t

lIS.

.. .81000
NCS·"".

amplifier

0.0'

-20

"

"

AMBIENT TDoI>ERATUREITAl--c
I1C$-IIIO ..

Fig.5b-lnput biBs cu"ent vs. amb;tIfIt
temperature.

132 ___________________________________________________________________

CA3060, CA3060A Types
ELECTRICAL CHARACTERISTICS (CA3060D)
Fo,eachamplifie, atTA - 250C, Y+-6V, V·-. V

CHARACTERISTIC

TYPICAL

LIMITS

CHARACTER·

Amplifier . . CUl'Nnt

'::e"ES 1--1-A8C---I-pA---iI':::::':::Aac::="'='=O~pA=':':::"r-II-A-BC-'-'''-pA-IUNITS

SYMBOL

F"

STATIC CHARACTERISTICS
Input Off•• VoitIgII

VIC

Input Off•• Current

'10

cIOOO, AMBIENT TEMPERATURE ITAI'2!t·C

MIN. TYP. MAX.

MIN. TVP. MAX.

MIN. TYP. MAX.

mV

50."
60."

Input Bias Current

Peak Output Current

33
1.3

Puk Output Volt.,.:

14

3D

I. .

70

3DD

550

2.3

250

-

1000

nA

2500 5000 nA

'5

26

150

240

u

u

u

U

IIA
4

«

Positive
Negative

VOM·

Amplifier Supply
Current (each amplifier)

So."

IA

8.5

14

85

120

850

1.45

10

14.5

mW

120

INN

3D

120

&1

'0

4

100

&.

1000

AMPLIFIER BIAS CURAE'4T IIA8Ci-,.A

1-~5.~81-'.~95~-~~'~
.•~5~.9~5+--~~5=.7~=5S~-~V

Fig.6a-Peak output current vs. amplifier bias current.

1200 pA

Power Consumption

leac:hamplifierl

-

0.10 0.11

Input OHlln·Volt.
/!;.Vlol/!;,V+

Positive
Neptive

Amplifier Bias Volt..,-

VABC

9

-

1.5

120

20

'20

120

20
-

0.54

120

0.60

-

0.66

V

••

30

102

mmho

110

10

90

dB

4.310 ·5 min.
4.6 10 ·5.2 typo

V

DYNAMIC CHARACTERISTICS I.. 1 kHz unl ....pecili ... otherwisel
Forward Transconductance
Uarge signal)

921

lOa,b

0.3

1.55

70

110

CMRR

Ratio

70

4.3 te ·5 min.
4.6 to -5.2 tyP.

4.4 10 ·5.1 min.
4.1 to -5.3 typo

Common·Mode Input·
VoltagaRlnge

Slew Rate ITest ckl ..
Fig. 13

0.'

SR

Open·Loop tg211
Bandwidth

"

Input Impedance
Components:

R.sistance

RI

Capacitance at 1 MHz

CI

AMBIENT nMPERATUREITA)-·C '2CS-I"O'

20

12

"0

45

""500

90

170

.0

20

2.7

2.7

Fig.6b-Peak output current vs. ambient
temperature.

pF

2.7

Output Impedance
Components:
Resistance

RO

Cepacitance at 1 MHz

Co

'4

200

20

4.'

4.5

Mil
pF

4.5

ZENER BIAS REGULATOR CHARACTERISTICS latTA' 250C, '2. 0.1 mAl
MIN. TYP. MAX.

Vz
Zz

Voltage

,_"'"
•

T.mp. Coefl.· 3 mV/oC

'5

T.m....ature-Coaflicient; ·2.2 mV/DC (II VABC· 0.54 V,IABC·
, IJA: ·2.1 mV/oC (at VABC • 0.060 V. 'ABC· 10 I'A.: ·1.9
mV/oC lat VABC· a.66V.IAIC· 100llAI
Conditions for Input Off.., Volt. and Supply s.nsilivitY:
tal Bi. current derived from - thl re~lator with an appropriate
l'ISistor confllCtftl from terminal No. 1 to thl b ... termiNi on
the amplifier under tat -

I

6.2

6.1

I 7.9

Iv

V+ is reducad to 5 velU lor y+ sensitivity
V· is ntduced to ·5 volu for V· sensitivity

Ibl y+ sensitivitY in INN" Vollset· Veflse. f;::I~ V and -6 V supplies
V. sensitivitY in INN. Voltset· Veffset f:~~t V and +6 V supPlies

A"PLlnER liAS CURRENT

10

10

... . ..

..... PLlfIER alAS CURRENT

1000

100

tr...ael-ILA

.ZCI·'HI:I

Fig.8a-Amplifi",. supply curren' IlIIICh
amplifier) w. amplifier billl cur·

_."

-50

'2!t

0

2

tr...ac' -100

Fig.7-Peak output voltage vs. amplifier
bias current.

A

.j••• -~

50

."

100

""ENT TEMP£RA1lJRE (TAI--C: nCS-ItIOS

Fig.8b-Amp/ifiar supply curren' INCh
amplifier) vs. ambient temperature.

I~

4

10

&. '00

46.

1000

AMPLIFIER 8,AS CURRENT CIABC1-,.,A

92CS'196,7

FIg.9-Amplifier bias voltaflll
fier bias current.

vs.

ampli-

ren,.
___________________________________________________________________ 133

CA3060, CA3060A Types
ELECTRICAL CHARACTERISTICS ICA3060AD, CA3060BD, CA3060E)
For each amplifier at T A = 250C, V+ '" 15 V, v- = -15 V

TYPICAL
CHARACTER·
CHARACTERISTIC

SYMBOL

LIMITS
Amplifi.r Hi•• Cur,.,.,
IABC· 10 tJA

'ABC· , pA
MIN. TVP, MAX.

MIN. TVP. MAX.

ISTles

CURVE
Fig.

'AIC-'OO,....

MIN. TVP. MAX.
CA3060AD
CA30608D

CA3080BD

UNITS

CA30&OE

STATIC CHARACTERISTICS
Input Ofhet Voltage

V,O

Input Offset Current

"a

".

Input Bias Current
Peak Output Current

mV

,.
Sa,b

7.

33

",-

'OM

1.3

2.3

Peak Output Voltage:

Positive

VOM+

12

13.6

Negative

YOM'

12

14.7

-

30

100

30.

.SO

"

26

'2
12

13.6

250

. ..

'000 nA

2.00 5000 nA
150

240

- ,....

10

..

100

."PLI"U I'.S CURIIENT

tr....cl-,. ..

..

1000

_lel'IMIi

14.7

-

12

13.6

12

14.7

Fig.IOa-Fo,ward tranu:onductance
amplifier bilJ$ current.

V

VI.

Amplifier Supply

'A

Current feach ampllflerl

Ba,b

feachamphflerl
InpulOffset·Voltage
SenSitIVity.:
POSitive

Negative
Amplifier Bias Vollage"

"

85

12.

850

0.26

0.42

2.6

3.6

26

36

30

150

0.66

-

..,),VIQ'.lv+

1.5

150

.lVIO/.lV·

20

150

V ABC

9

1200 IJA

8.'

Power Consumption

150
20

0.54

mW

150

150

0.60

INN

V

DYNAMIC CHARACTERISTICS (at 1 kHz unleu specified otherwise)
Forward Transconductance
lIargesl9naii

,,,

0.3

1.55

Common·Mode Relecllon
RallO

CMRR

70

110

Common·Mode Inpul
Vollage Range

VICR

~12to ·12 min.
+1310 ·14tvp.

51ewRaie ITeslckl ..
Fig. 13 t

SR

Open· Loop 19211
BandWidth

aWOL

11

ReSistance

R,

12

Capacitance al 1 MHz

C,

10a,b

-- f---

70

18

30

102

-

mmho

110

70

90

-

dB

+1210 ·12 min.
f1310·14typ.

+1210 ·'2 min.
+13 to ·'4 tvP.

-

VIll<

110

-

k~z

20

-

kn

-

Mn

0.1
45

20

-~

-25
0
25
50
75
100
'25
AMIIENT TEMPER"TURE IT.. I--C _:tes-I.'OS

V

Fig.IOb-ForwanI tranllCOlJductance VI.
ambitmt ttlmptJl'Bture.

Inpllllmpedance
Componen!$'

800

1600

90

170

-

10

2.7

2.7

2.7

pF

Output Impedance
Components'
Resistance

RO

Capacitance at 1 1101Hz

Co

14

200

20

4.5

4.5

4.'

pF

ZENER.BIAS REGULATOR CHARACTERISTiCS lat TA=250 C,12' 0.1 mAl
MIN. TYP. MAX.

Voltage

I

Impedance

Vz

I

Zz

Tllmp.Coefi.= 3mV/OC

"

1

Temperature·Coelilclent; ·2.2 mV/oC Cat VASC ~ 0.&4 V.IABC =
1 IJA; ·2.1 mV/oC lat VASe ~ 0.060 V, IABC - 10 ",AI; ·1.9
mVloC Cat VASC ~ 0.66 V,IASC"" l001JA1
Conditions for Input Offset Voltage and Supply SenSitivity:
lal Bias current derived from the regulator With an apprOpt'iate
resistor connected from terminal No.1 to the bias terminal on
the amplifier under test •..

•

I.
I

7.9

V

1 200300

In

6.2_1 6.7

V+ IS reduced to 13 volts for V+ sensitivity
V· 15 reduced to -13volts for V- sensitivity

D.OOI

0.01

(b) V+ senSitivity mlJ,ViV _ Vollse!· VoUset f::;1!3 V and -15 V supplies

0.1
I
FR£QUENCY It 1 - MHI

10

100

Fig.ll -Forward transconductBnctI vs.
freqUBIICY,

V' sensitiVity in p.VJV" Voffset· Voffset f::o~113 V .nd +15 V supplies

.,
10.000, AMBIENT TEMPERATURE ITA 1 ~25-C

.

I SUPPLY VOLTAGE: Y+'6V, Y"-6V
Y+.,S Y. Y-'-15V
.. FREQUENCY ttl,aHz

~

.

~IOOO,

OUT'., liF·"

""

..

TYPICAL SLEW RATE TEST CIRCUIT PARAMETERS
I,

I'N..
418

10
AMPLIFIER BIAS CURRENT

100

4

"

'ABC

Vz is measured between terminals 1 and 8.
'000

tlABcl-~A

n.eS-IUII

Fig. 12-lnput resistance 'T. amplifier bias
current.

Supply Vottage: for both ±6 V and ±16 V •

VABC is measured between terminals 15 and 8.

SLEW
RATE

"

RABC I

As

IRF IRB IRe

,....

V/ll<

,....

'00

B

200

10

1

200

620'

1

0.1

2

8.2M 1'0M L'OM Is.1MI ~

IfJ'

ohms

82"

I 100' 1'00' I 5"1'00

I

1M

I

1M IS10' I

Cc

0.02

,. 0.005
0

Fig. 13-Slew rate test circuit for amplifier No. I of CA3060.

134 _____________________________________________________________________

CA3060, CA3060A Types
1

V I '!5V, V-'15V
FREQUENY

Itl'I~Hr

! 'ki'---r--r-rrt--r--r-rrt--r--r-rH
~,oo'E~ttt~mS~ffi

:::~

~~:~~~~,:~L~:~~~:~~:)i~~~:~~~~;yG!tii:
I ' II

I~;:',:::'

::; ,

1IIIILl-;::;;~:'

'''I LkPt"'T:' I ,"
II
I
L"'"
FI, I I :
LE:' ,:;"":'::;
1'1

i

I"

HH:':;"

I'r'

1'::.11":: :"

..c:""

I.......,
4

"

10
100
AMPLIFIER BIAS CURRENT IIABCI-},A

4

Ie

1000

=

100118 kn

~

5.5 mmho

(RL = 20 kG in parallel with 200 kn
::!

18kn)

2. Selection of suitable amplifier bias current.
The amplifier bias current is selected from the minimum
value curve of transconductance (Fig. lOa) to assure that
the amplifier will provide sufficient gain. For the required
921 of 5.5 mmho an amplifier bias current IABC of 20,uA
is suitable.

'00

.2CS-III20

Fig. 14-0utput resistance vs. amplmer bias current.

921 = AOLIRL

BIAS REGLLATOR CURRENT UZI}'A

Fig. 15-Bias regulator voltage vs. bias regulator current.

3. Determination of Output Swing Capability.
For a loop gain of 10 the output swing is±0.5 V and the
peak load current 25 ,uA. However, the amplifier must
also supply the necessary current through the feedback
resistor and for AS = 20 kn than AF =200 kn if AOL =
10. Therefore, the feedback loading'" 0.5/200 kn = 2.5jJA.
The total amplifier current output requirements are,
therefore, ±27.5 jJA. Referring to the data given in Fig. 6a
we see that for an amplifier bias current of 20 jJA the
amplifier output current is ±40 jJA. This is obviously
adequate and it is not necessary to change the amplifier
bias current IABC.
4. Calculation of bias resistance.
For minimum supply current drain the amplifier bias current
IABC should be fed directly from the supplies and not
from the bias regulator. The value of the resistor RABC
may be directly calculated using Ohm's law.
R

_ VSUP - VABC
A8C I A8C

COMPLETE OTA CIRCUIT

= 568.5 kn or ::! 560 kn

Fig. 16 - Complete schematic diagram showing one of the three operational transconductance amplifiers.
OPERATING CONSIDERATIONS

The CA3060 consists of three operational amplifiers similar
in form and application to conventional operational ampli·
fiers but sufficiently different from the standard operational
amplifier (op·amp) to justify some explanation of their
characteristics. The amplifiers incorporated in the CA3060
are best described by the term Operational Transconductance
Amplifier (OTA). The characteristics of an ideal OTA are
similar to those of an ideal op·amp except that the OTA has
an extremely high output i~r:edance. Because of this
inherent characteristic the output signal is best defined in
terms of current which is proportional to the difference
between the voltages of the two input terminals. Thus, the
transfer characteristic is best described in terms of transcon·
ductance rather than voltage gain. Other than the difference
given above, the characteristics tabulated on pages 3 and 4 of
this data bulletin are similar to those of any typical op·amp.
The OTA circuitry incorporated in the CA3060 (See Fig. 16)
provides the equipment designer with a wider variety of
circuit arrangements than does the standard op·amp; because
as the curves in the data bulletin indicate, the user may select
the optimum circuit conditions for a specific application
simply by varying the bias conditions of each amplifier. If
low power consumption, low bias, and low offset current, or
high input impedance are primary design requirements, then
low current operating conditions may be selected. On the
other hand, if operation into a moderate load impedance is
the primary consideration, then higher levels of bias may be
used.
Bias Considerations for Op-Amp Applications
The operational transconductance amplifiers allow the circuit
designer to select and control the operating conditions of the
circuit merely by the adjustment of the input bias current
IABC' This enables the designer to have complete control
over transconductance, peak output current and total power
consumption independent of supply voltage.

In addition, the high output impedance makes these
amplifiers ideal for applications where current summing is
involved.
Thedesign of a typical operational amplifier circuit (See Fig.
17) would proceed as follows:

5. Calculation of offset adju~tment circuit.
In order to reduce the loading effect of the offset
..djustment circuit on the power supply, the offset control
should be arranged to provide the necessary offset
current. The source resistance of the non-inverting input is
made equal to the source resistance of the inverting input.
i.e.

20 x 200)( 106 ohms::.. 18 kG
220 x 103

Because the maximum offset voltage, is 5 mV and an
additional increment due to the offset current (Fig. 4)
flowing through the source resistance
(i.e. 200 x 10. 9 x 18)( 103 volts ).therefore,
the Offset Voltage Range '" 5 mV + 3.6 mV:: :t8.6 mV
The current necessary to provide this offset is
B.6 x 10. 3 or 0.481JA
18 x 103
Fig. 17-20-dB amplifier using the CA3060.
Circuit Requirements
Closed loop voltage gain = 10 (20 dB)
Offset voltage adjustable to zero
Current drain as low as possible
Supply voltage = ±6 V
Maximum input voltage = ±50 mV
Input resistance = 20 kn
Load resistance = 20 kn
Device: CA3060
Calculation
1. Required transconductance 921.
Assume that the open loop gain AOL must be at teast ten
times the closed loop gain. Therefore. the forward
transconductance required is given by

With a supply voltage of ±6 V. this current can be provided
by a 10 M!l resistor, However, the stability of such a n,sistor
is often questionable and a more realistic value of 2.2 Mn
was used in the final circuit.
OTHER CONSIDERATIONS

Capacitance Effects
The CA3060 is designed to operate at such low power levels
that high impedance circuits must be employed. In designing
such circuits, particularly feedback amplifiers, stray circuit
..::apacitance must always be considered because of its adverse
effect on frequency response and stability. For example a
10-kn load with a stray capacitance of 15 pF has a time
constant of 1 MHz. Fig. 18 illustrates how a 10·kn 15-pF
load modifies the frequency characteristic.

_____________________________________________________________

1~

CA3060, CA3060A Types
0

~

-20

i

~,.'o.n

Circuit Description

Acti~

Fig. 20 shows the block diagram of a tri·level comparator
using the CA3060. Two of the three amplifiers are used to
compare the input signal with the upper·limit and lower·

The high output impedance of the OTAs makes the CA3060
ideally suited for use as a gyrator in active filter applications.
Fig. 22 shows two OTAs of the CA3060 connected as a
gyrator in an active filter circuit. The OTAs in this circuit can
make a 3·,uF capacitor function as a floating 10·ki!ohenry
inductor across Terminals A and B. The measured a of 13 (at
a frequency of 1 Hzl of this inductor compares favorably
with a calculated a of 16, The 20·kilohm to 2·megohm
attenuators in this circuit extend the dynamic range of the
OTA by a factor of 100. The 100·kilohm potentiometer,
across V+ and V', tunes the inductor by varying the g21 of
the OTAs, thereby changing the gyration resistance.

v'

CL'O

~ ~40

'L"~~ I~

"~

UPPER LIMIT

REFERENCE VOLTAGE

e;.'15pF'

-60

,

-'0

om

0'

~

'0

'00

INPUT SIGNAL
INTERMEDIATE-LIMIT
REFERENCE VOLTAG.E
LOWER LIMIT

Filters - Using the CA3060 as a Gyrator

REFERENCE VOLTAGE

Fig. 18-Effect of capacitive load;ng on frequency response.

vFig.20-Functionaf block diagram of a tri·level comparator.

Capacitive loading also has an effect on slew rate; because the
peak output current is established by the amplifier bias
current, 'ABC (see Fig. 6al. the maximum slew Tate is limited
to the maximum rate at which the capacitance can be
charged by the 'OM' Therefore.

SR = dV/dt = IOM/CL
where CL is the total load capacitance including strays. This
relationship is shown graphically in Fig. 19. When measuring

slew rate for this data bulletin, care was taken to keep the
total capacitive loading to 13 pF.
Phase Compensation

In many applications phase compensation will not be
required for the amplifiers of the CA3060. When needed,
compensation may easily be accomplished by a simple RC

network at the input of the amplifier as shown in Fig. 13.
The values given in Fig. 13 provide stable operation for the
critical unity gain condition, assuming that capacitive loading
on the output is 13 pF or less. Input phase compensation is
recommended in order to maintain the highest possible slew
rate.
In applications such as integrators, two OTAs may be
cascaded to improve current gain. Compensation is best
accpmplished in this case with a shunt capacitor at the
output of the first amplifier. The high gain following
compensation assures a high slew rate.

APPLICATIONS
Having determined the operating points of the' CA3060
amplifiers, they can now function in the same manner as
conventional op-amps, and thus, are well suited for most
Dp-amp applications, including inverting and non·inverting
amplifiers, integrators, differentiators, summing amplifiers
etc.

limit reference voltages. The' third amplifier is used to
compare the input signal with a selected value of inter·
mediate·limit reference voltage. By appropriate selection or
resistance ratios this intermediate-limit m~y be set to any
voltage between the upper·limit and lower·limit values. The
output of the upper·limit and lower·limit comparator sets the
corresponding upper or lower·limit flip-flop. The activated
flip·flop retains its state until the third comparator (inter·
mediate·limit) in the CA3060 initiates a reset function,
thereby indicating that the signal voltage has returned to the
intermediate·limit selected. The flip·flops employ two
CA3086 transistor·array IC's, with circuitry to provide
separate "SET" and "POSITIVE OUTPUT" terminals.
The circuit diagram of a tri·level ~mparator appears in Fig.
21. Power is provided for the CA3060 via terminals 3 and 8
by ±6·volt supplies and the built·in regulator provides
amplifier·bias·current (lABe) to the three amplifiers via
terminal 1. Lower·limit and upper·limit reference voltages are
selected by appropriate adjustment of potentiometers Rl
and R2, respectively. When resistors R3 and R4 are equal in
value (as shown), the intermediate·limit reference voltage is
automatically established at a value midway between the
lower·limit and upper·limit values. Appropriate variation of
resistors R3 and R4 permits selection of other values of
intermediate·limit voltages. Input signal (ESI is applied to the
three comparators via terminals 5. 12. and 14. The "SET"
output lines trigger the appropriate flip·flop whenever the
input signal reaches a limit value. When the input signal
returns to an intermediate--value, the common flip-flop
"RESET" line is energized. The loads in the circuits, shown
in Fig. 21 are S-V, 25·mA lamps.

!V+!

+6V

Fig.22- Two operational transconductance amplifiers of the
CA3060 connected as a gyrator in an active filter
circuit.

TRI-LEVEL COMPARATOR
Tri·level comparator circuits are an ideal application for the
CA3060 since it contains th.e requisite three amplifiers. A
tri·level comparator has three adjustable limits. If either the
upper or lower limit is exceeded, the appropriate output is
activated until the input signal returns to a selected
intermediate limit. Tri·level comparators are particularly
suited to many industrial control applications.
IJPPERLlt.llT
FLIP-FLOP

.,"
""'.'0""-·---··---------\
REFERHICE LIMIT
IS REACHED
EIJ-EL~

CA3086

-2-

v

0.01

WI-IENLOWER LIMIT
IS EXCEEOEO

I

4 ' 'O.j

2

NOTE2 ES>EU'QI(ON),Oz.(QFF")
SLEW RATEtV/,.11

Fig. 19-Effect of load capacitance on slew rate.

LOWER LIMIT
REFERENCE
VOLTAGE

ES< Eu;EL '01(OFF),Q210FFI
ESr s('etioll with
a Zener regulated power suppl.v, WI PM detector shiRt',
and an AF preamplifier sectioll. A typical appli<"<1tioll
of the CA3075. in FM r(>{'eivcr circuits, is shown in thp
block diagram (FiR. D,

The three-stage, emittc.... follnwC'r-{·()upl<.,ci iF amplifil'r
section provides a 6O-dR typo \'ollagt' gain at lUI opt.'rating frequency of to,7 ~Hz and f(,utures, I)(-'C~lUS(, of its
trWlslslor t'ollslant-current sink, WI output stagl' with
exceptional I..,.. good limiting <,·haracteristi('s.

MAXIMUM RATINGS, A6•• I.t.·Ma.im.m Va/.u at TA = 25·C

Dc

Supply VoltaBe [between Terminals 5 (V+) and 3 (V-)]

DC Current (into Terminal 5) •••••••••••••••••••

12.5

V

30

mA

Device Diuipation:
Up to TA =50oC ••• ~ •••••••••••••••••••••
Above T A '" 50 o e ........................ .

760
mW
derate linearly 7.6 mW/oC

Ambient Temperature Range:
Operating ••••••••.•••••••••••••••••••••
Storage ••••••••••• , ••••••••••••••••••••
Lead Temperature (During soldering for 10 s max.) ••.••

- 55 tot 125
-65to+150
+265

°c
°c
°c

The PM detcctm l'Icction, whi<,'h utiliz('s a diffC'I"('ntiulpt·ak-detection circuit. rl'Quir('l'I only a sin~dt, (.'oil in the
associated outboard dett-'ctnt ein'uit: hC'nel', tuning thl'
dt-'leetor ('ireuit is n simple procl'dure.

The audio preamplifier eir<"uit provides a 21-dB voitngt'
gain with low impedan(,l' output for driving suhsl'qtll'nt
audio amplifier stages.
The CA.1075 utilizes a 14-lead dual-in-lint' plnsti<: package with It'ads ·in n special quad-formed arrangement.

,'-

....LUI 4505 til !~UUIIT
••• jHnOllSUC"ULvt to
AOJUnOOP'C?lLtOJS

Fig. 2· Ten Circuit for input limiting voltage. recovered
AF Yoltage. and total harmonic distortion

1~

Fig,3 - Schematic diagram of CA3075

______________________________________________________________

CA3075
ELECTRICAL CHARACTERISTICS .t TA = 250 C

LIMITS
CHARACTERISTIC

SYMBOL

TEST CONOITIONS

MIN.

TYP. MAX.

UNITS

TEST
CIRCUIT
FIG. NO.

Static Charact.r;sties

OC Volt'ge:
At Terminal 7
At Terminal 8

AI Terminal 11

-

VI
VB
Vll

V" 1l.1V

DC Current (into Terminal 5):
At V' ,B.5V

At V·, 11.1 V
At V·, 11.5 V

-

V
V
V

6

6

-

15
17.5
19

19

rnA
rnA
rnA

-

150

600

p.V

3

-

55

-

dB

5

8.5

-

15

6.1
5.4
5.1

-

Dynamic Characteristics at V+ = 11.2

~
Input Limiting Voltage

VI (lim)

(knee, - 3dB point)
PM Rejection

Input Impedance Components:
Parallel Resistance

Parallel Capacitance
DETECTOR
~F Voltage (at
Terminal 11)
Total Harmonic Distortion

10' 10.IMHz
I(Modulation),4ooHz
Deviation'" ±75kHz

AMR

10' 10.7 MHz
I(Moduiation) ,400 Hz
FM: Deviation' tl5 kHz
AM: Modul'tioo ,30%
10,10.1 MHz
VIN ' IOmV RMS

RI
CI

VO(AF)
THO

.

10 =10.7 MHz
I(Modul'tion) = 400Hz
Deviation

=

±75kHz

\.~ETAUOIOCEMfUTORFOAVI'

2. READVO

-

4.5
4.5

-

-

1.5
1

-

-

11

-

1.5

-

-

1

lOhVA.1

1,lfTAUOIOCE"EAATORFORVO·2VR.1
2. RfAOOllTOliTIOfIIH',

I,CAI", 10 LOCIO YO/Y!

kfl
pF

-

V

3

Fig..4 - Test circuit for audio preamplifier voltage gain
and total harmonic distortion

%

AUDIO PREAMPLIFIER
Voltage Gain

A(AF)

VIN = lOOmV, 10 =400Hz

Total Harmonic Distortion

THO

VOUT = lV,IO =400Hz

5

dB

4

%

4

~i-

lEHPROCEDURf
l.CONI 20MHz

The CA3076 utilizes an henneticaUy-sealed 8-1ead 1'0-5
package.

MAXtMUM RATINGS, Absolute Maximum·Valu.s at TA = 2SoC
DC Supply

~oltage

[between Terminals 7 (V+) and 3 (VI]

15
35

DC Current (into Terminal 7) •••••••••••••••••••

V

rnA

RFCENERUOII

(10.7_HoI
HEWLETT.

PACKARO
lOaC 0"1
EQUIVALENT

Device Dissipation:

500
rnW
derate linearly 5 mW/oC

Up to T A = 50° C ••••••••••••••••••••••••
Above TA = 50 0 e ....................... .
Ambient Temperature Range:

A

Storage ••••••
Lead Temperature (During Soldering):

••••••••••

0

- 55 to + 125

°c

-65 to + 150°C

••••••••••••

At distance 1/32 in (3.17 rnm) from seating plane
for lOs max ••••••••••••••••••••••••••••

HEWLfTT.

PACKARD
••'AOR
EQUIVALENT

ATTENUATOIt

Operating ••••••••••.•.•••.••.••.••••••
0

RI!I'!RI!NCE INPUT ___----:-jVOLT_nER
VECTOft
1 - - -_ _=;::::7;";:.:.:.

(40iB)

~~I::ENT l-·j'("-',.-0-1

+ 265

ELECTRICAL CHARACTERISTICS at TA = 2SoC

CHARACTERISTIC

SYMBOL

TEST
CONDITIONS

LIMITS
MIN. TYP. MAX.

UNITS

Fig. 2 .. Forward transler admittance (Y21J
t.st circuit

Static Chorocte,bt;cs - V+ = 8.S V

OC Currenl (inlo TOIm. 7)

17

Quiescent Operating Current

14

(into Term. 4)

-

15

24

rnA

-

0.65

-

rnA

-

50

200

I'V

12

mV

10

Dynamic Characteristics - V+ = 8.5 V, '0 = 10.1 MHz

Inpul Limiting Vollage (knee.
- 3dB poinl)

VI (lim.)

Oulpul Voltage

Vo

VI "20I'V

Output Noise Voltage

VN

VI" 0

-

I

-

IY2J!

VI"
IOI'V

-

6
80

-

degrees

-

0.1
- 90

-

,umho
degrees

7.5
4

-

kG

-

-

kG

-

4

mV

Forward Trlllsfer Admittance:

Magnitude
Phase

e21

mho

Reverse Transfer Admittance:

Magnilude
Phase

!YI2!
812

-

Input-impedlllce Components:
Parallel Resistance
Parallel Capacitance

RI
CI

-

Output·lmpedance Components:
Parallel Resistance
Parallel Capacitance

RO
Co

-

-

50

-

1.7

pF

pF

Fig. 3· Te.t circuit lor DC current (1ermlnoI7'
and operoting Current (1erminoI4}.

140 _____________________________________________________________________

CA3076

lenninal Ho. 5 wjr.·connecl.d 10 'he cos••
Terminals No.3 and 6 which or. conn.c'ed to the substrate
should b. connec••d to ,h. most "egoti". point in Ih. circuit.
Th. resistance 'l'olues included on the schemotic diagram
hOYe b•• n supplied os II COIIunience to assist Equipment
Manufacturer's in oplimizin, the selection 01 "outboard"

Th. yolues shown mor
vary as much as !.30",
RCA ,.,e'",s the fi,hl to mak. an, chon,es in th. Resisl.
once Volues pro"id,d such changn do not adv.rul, affect
componenls of equipment IInigns.

Ihe publishI'd performance characteristics of .... d."ice.

c...

'OK

Fig. 4 .. Schematic dIagram 01 CA3076 •

.IIlUR4U,FllTER

TYPICALYALUES

ItIM • ROUT ,

non

IH5ERTIOMLon·6dBTYP.

B4NOWIOTH IAT .ldB) •

2.a~H.

OUTPUTYOLTAGE:
I. SET ATTEMUATORTOO.a
2.se:TRP'GENERATORTQZG,.yCW
l.RI!AOVOIN .. V

OUTPUt NOISE 'IOlTAG!·
1. SET ATT£NUATOR T06UII
2. REAOVOIN .. y

Fig. 5 ·10.7 MHz voltage ,ain anJ noise test circuit

________________________________________________________________ 141

CA3078, CA3078A Types

Micropower Operational Ampl ifier
Applications:

Features:
The RCA CA3078T
and CA3078AT
are high·gain
monolithic operational amplifiers which can deliver milli·
amperes of current yet only consume microwatts of standby

power. Their operating points are externally adjustable and

The CA3078 and CA3078A are supplied in either the
standard 8-lead TO-5 package ("T" suffix), or in the
8·lead dual-tn-line formed-lead "OIL-CAN" package ("5"
suffix).

•
•
•

frequency compensation may De accomplished with one

external capacitor. The CA3078T and CA3078AT provide
the designer with the opportunity to tailor the frequency
response and improve the slew rate without sacrificing
power. Operation with a single 1.5-\1011 battery IS a practical
reality with these devices.

The CA3078f"T is a premium ~evice having a supply vOlt~ge
range of V- ,"' O.75V to V- = 15V and an operating
temperature range of _~50C to +1250C. The CA3078T has

the same lower supply voltage limit but the upper limit is V+
+6V and V-=-6V. The operating temperature range IS from
OOC to +700 C.

Low standby power: as low as 700 nW
Wide supply voltage range: ±O.75 to ±15 V
High peak output current: 6_5 mA min.
Adjustable quiescent current
Output short·circuit protecti0f!.

MAXIMUM RATINGS, Absolure Max/mum Values ar T A "" 2~C

CA3078AT

DC Supply Voltage Ibetween V+ and V- terminal.
Differential Input Voltage .. __ . . . . . . .
DC Input Voltage . . . . . .
Input Signal Current . . . .
Qutpuf Short-Circuit Duration·
- Device DISSipation ..
Temperature Range
Operating •.
Storage
Lead TemperalUre (Dunng Soldering)
At distance 1/16 ±1/32 In. (1.59 ±o.79 mm)
from case for lOs max

- Portable electronics
,- Medical electronics
- Instrumentation
- Telemetry

CAJ078T
,4V

36V

±SV

±Sv
V+ 10V0.1 mA
No Limitation
50 mW (up to 1250 CI

V+toV0.1 mA
No Limitation
Soo mW (up to 70°C)

·55 to +12SoC
-65 to +150°C

o to +700C ..
-65 to +lSOoC

'Short CirCUIt may be applied to ground or to e'ther supply

ELECTRICAL CHARACTERISTICS
For Equipmen1 Design

... Types CA3078S and T can be operated over the temperature range of -55 to +125<1 C, although
the published limits for certain electrical specifications apply only over the temperature range of
a to 70° C

SYMBOLS

Input Offset Voltage
Input uffset Current

VIO

Input 81as Current

liB

CONDITIONS
V+

RSET

=

Total QUiescent Current

AOL
10

PD

DeVice DISSipation
MaXimum Output Voltage

V OM

Common-Mode In)Jut Voltage

&

RS

RL

Kll

Kll

TA = 25°C
MIN TYP MAX MIN

~10

"'10

88

MaXimum Output Current

1.3

4.5

6
60

32
, 70

.10 '5 ,

6

92

86

V ICR

.. '0

to

CMRR

"";10

'58
110

80

'2
22

....1VIOI.:W I

MAX

-

92

-

~

-

..

65

2.5

5.0

nA

'2

50

7

25
300

80

30

to
•5 8
115
,2

45
540
±5

-

nA
dB

90

-5,5

'5

S
mV

3.5

'00
20
240

-

U
N
I
T

4.5

0.70
0.50

5 1 !5.3

5
to

-

= 20"A

TA = 25°C
125°C
MIN TYP MAX MIN MAX

'50
1800
'5

'53
-5.5

10M or 10M

Negative

MH.la

TA =-55 to

5
40

Input Offset Voltage Sensitivity
POSitive

= 5,1

RSET

200

'00
'30
1200 1560

Range
Common-Mode ReJer.llon RatiO

·100 IJA

=

v·

1

1 MH.I

TA 0 to
70°C

110

Open-Loop Olff. Voltage Gain

CA3078AT LIMITS

CA3078T LIMITS

TEST
CHARACTERISTICS

-

"A

"VV
V

-5

-

to
+5

-

V

-

-

-

d8

-

6.5

,50

-

6

'50

'50

-

6

'50

30

rnA

-

-

VIV
'0

-'VIOI-'V

22

-

RSET'" 13 Mf!, '0 == 20pA
Input Offset Voltage
Open· Loop 0111 VoltdC;!t'
Total QUiescent Current

VIO
GdlO)

Device DISSipation
MaXimum OUIjJut Vollage
Common-Mode Rejection Rutlo

AOL
10

i

10
10

15

-

PD
V OM
CMRR

Input Bias Current

II B

Input Offset Current

110

j

OPERATING CONSIDERATIONS

Compensation Techniques
The CA3078AT and CA3078T can be phase-compensated
with one or two external components depending upon the
closed-loop gain, power consumption, and speed desired. The
recommended compensation is a resistor in series with a
capacitor connected from terminal 1 to terminal 8. Values of
the resistor and capacitor required for compensation as a
function of closed loop gain are shown in Figs. 24 and 25.
These curves represent the compensation necessary at
quiescent currents of 20 J..I.A and 100 J..I.A, respectively, for a
transient response with 10% overshoot. Figs. 21 and 22 show
the slew rates that can be obtained with the two different
compensation techniques, Higher speeds can be achieved
with input compensation, but this increases noise output.

-'10

'4
'00
20
600

-

10

-

-

92

-

-

35

30
750

'06
7
0.50

'4
27

4.:

rnV

-

dB
50

'350

± 13.5

±13.7 ±14.1

80

88

-

IJA
iNJ
V

55

dB
nA

5.5

nA

Compensation can also be accomplished with a single
capacitor connected from terminal 1 to terminal 8, with
speed being sacrificed for simplicity. Table 1 gives an
indication of slew rates that can be obtained with various
compensation techniques at quiescent currents of 20 IlA and
HlO"A.
Single Supply Operation
The CA3078AT and CA3078T can operate from a single
supply with a minimum total supply voltage of 1.5 volts.
Figs. 27 and 28 show the CA3078AT or CA3078T in
inverting and non-inverting 20-dB amplifier configurations
utilizing a t .5-volt type "AN' cell for a supply. The total
power consumption for either circuit is approximately 675
nanowatts. The output voltage swing in this configuration is
300 mV pop With a 20 kU load.

Fig. 1 - Functional diagram of the CA3078T
and CA3078A T.

142 __________________________________________________________________

CA3078, CA3078A Types
SUPPLY VOLTS y+. +6. Y-'-6
AMBIENT TEMPERATURE IT A I'2!1-C
SOURCE RESISTANCE IRst ~ 10 IW

. ..

...

10
100
TOTAL QUIESCENT MICROAMPERES IIal

1000

Fig.3 - Input offset lIoltage liS. total quiescent current.

SUPPLY YOI..TS Y+'+6, Y-'-6
AMBIENT T[MP[R"TUR[IT"I'2~

Fig.2·Schematic diagram of the CA3078T and CA3078A T.

~>o:'m_~
r=R
,.,01.""''
:'lib"

c.."' ' o

'r--

:P14
':'--~

Typical Values Intended Only for Design Guidance at TA" 250C and V+ .. +6 V, V- .. 6 V
CA3018AT
CHARACTERISTICS

TEST
SYMBOLS CONDITIONS RSET =- 5.1 M!1

Input Offset Voltage Dnll
Input Offset Current Dnft
upen-Loop Bandwidth
lew Flate'
Unity Gain
Comparator

Kn

5
63

t.VI OIt.T He; -......10
AVIO' TA AS ',10 K••
BWOL

SA

JdB pI

See Figs.
20.21
10"., to 90"y
R,S(.' Time

TransIent Response
Input Resistance
Output Resistance
Equiv. Input NOise Voltage

eN t1OHz ) AS

a

Equlv. Input NOise Current

INI10HzI AS

lM!l

CA3018T

RS ET ' 1 MrI RSET ' 1 MrI
' 0 ' 100 iJA
' 0 ' 100 iJA

' 0 ' 20iJA

A
An

6
70

U.J

6
70
2

0027

0.04

0.04

UNITS

~VloC

:2 " I '
2
10
.
100
1000
TOTAL OUI[SCENT fIoIICRO .... fIoIPER[S ItOI

pA/oC
kH,

Fig.4 - Input offset currenr liS. total quiescent current.

1.5

1.5

3
7.4
1

25
1.7

2.5
0.87
0.8
25

nV/yHz

1

pAlyH,

40

-

025

"I'
2
10000

VII'S

05

0.8

c..'"

I'S

Ml!
KII

ELECTRICAL CHARACTERISTICS, at TA • 250C
Typical Values Intended Only for Design Guidance
z

TYPICAL VALUES

CHARACTERISTiCS
SYMBOLS

v+ '" +1.3V,
V-=-1.3V
RSET

=2 Mf!

'0' 10iJA

0,7

V,O
',0
18

v.o

AOL

84

'0
0
VOpp
VieR

CMRR
10M!

6.vIOIl:l.V!

J.

v+ ; +0.1SV.

V···0.75V
RSET'" 10Mrl
10 c 1 j./A

0.9

= 2 MD

RSET

' 0 ' 10iJA
1.3

U.VO·

U 4'

6S

80

.

lU

lU

LG

CA3Q78T
V+" +1.3V.
v+ '" O.15V.
V-<:. -1.3V
V-"-0.15V

14

1.5
0.3

14

-0.8

-0.2

-0.8

RSET" 10

Mn

"(>,,

2" I'
2" ,.
:2'"
100
1000

10

TOTA~

a

10000

QUIESCENT fIoIICRQAMP[RES 1101

Fig.5 - Input bias current liS. total quiescent current.

UNITS

'O·'iJA

1.5

II1V

0.5
1.3
GO
1

nA
nA

.f--+-+-t1+--+--i--+++--i-+-I-H~

dO

;

,,

iJA
~W

0.3
-0.2

V
V

to

to

to

to

+1.1

+0.5

+1.1

+0.5

100
12

90
05

100

12

90
0.5

d8
mA

20

50

20

50

IJ.V··V

126.....--

~
+1+-+--i-+ H---t---t--t-tt'"

...

10
100
TOTAL QUIESCENT fIoIlCROAfIoIPERESIIQI

...

1000

Fig.6 - Open·loop lIo/r.ge gain liS. total quiescent current.

__________________________________________________________________ 143

CA3078, CA3078A Types

f
2
I

}
~
i

~

"hoLLJ,,)50A"'~;ci:::,:,':":,II-':-'-:.=-+:+1"•

'-'-;i-.
'-I.

~

1251-:.-:-':-+-:--:-+-:--:-+'.-:-.-:-::-t~-:::.,"':"':I-::-:-c.

,!"OOI17F.TI

~ 1-:-4--+--+'--+---b:~:~fJi~

r:fC.-'-·'"+.'-'-'1.;,.",::"'·f~:':·':"~

Al078T

I

1-'-'-'-+:"":-+:"":-1-":':"'-3-

10

:CfPC.:
:",.c.:

~

"OO~A

A3078AT
'20~A

0251-:-4--+'--'-+'--+'--'-+-'-'-'+-'--'--+-'-"+-'-'-'-1

°'

Fig. 1".- Output and common·mode voltage vs. supply voltage.
-15

-50

-Z5

0

-50

AMBIENT TEMPERATUflE!TA I-·C

-25
0
75
A'-tBIENT TEMPERATURE(TA'-OC

Fig. 14 - Input offset current vs. temperature.

Fig. 73 - Input offset voltage v•. temperature.

SUPPLY VOLTS: V +. +6, V-.-6

SUPfl~Y YOLTS; y+ -+-6, Y-·-6

SUPflLY VOLTS: V+-· +&, V-·-6

I
I

,J

CA30TaAT

tQ.20~A

~

150 ~

to~
,,03

2.'

-50

-25

0

25

50

75

AMBIENT TEMPERATURE {TAI-·C

Fig. 15 - Input bias current vs. temperature.

".

'"-75

-50

-25

0

25

50

100

AMBIENT TEMPERATURE( TAI-"C

Fig.'6 - Open·loop voltage gain vS'. temperature.

'"

~
12.°

g

"

AMBIENT TEMPERATURE (TAI-"C

Fig.1? - Tota, quiescent current VS. temperature.

144 ________________________________________________________________

CA3078, CA3078A Types

6

_

JulJLY

~ ,'~,

C~RRElt) (JQ~' 2!A

2~

B

'f'

.

0.'

~

'r--

~

'r·

~ 'r-~

~

6 8 ,02

2

•

6 B,oS

Z

•

6 8'0~

2

•

6 8 105

S

0.01

Qo1 (RI CI BETWEEN
TERMINALS 1881

5

Q3

~

SUPPl)" CLIlRENT !lOI·IOO,..

,

fI..

, ,

-,

ZO"A -

r-

~- c-

~-

1

,,

10

.~

...II , ..

1

~

"

SUPPLYVO~rs.

.

r--

10'

t.

y"

". v ••

:~~~~~N;E~~~:~~~;~:;;I~~: c

r- ~--L

~~:;~:;:~~~;~A::i; I':F ~:'"aC,l~:oo .F
OUTPUTVOlTA~E

IVoppl- '"V

;~s~~~~';~T[~ ,~~Ro'v~~~~~~;
OIOA1COmVourrUTSIONAL
IR,.C"U.,o-61

1J203040:;06070ao
CLOSED-LOOP NON-INVERTING VOLTAGE GAIN

68 1ri'

dB

o 6CLOSED-LQOPLNVERTINGVOLTAGEGAIN-dB
19J
z!i7
010
50
60
10

Fig.20 - Slew fare liS. closed·loop gain
for 10 = 100 IJA - CA3078T.

~~~~sA:-crroR

-

oj

IREsSTtm-CAPACITOR
COMPENSATION
!R,-C, BETWEEN
T RMINALS 16BI

Fig. 19 - Equillalent input nois~ curnnr "'. fntquency.

Fig.f8 - Equillalent input nOise ,Ioltage liS. frequenc'l.

...• 0'

p....,r--.

l"-.

"

itrrnfff"C

FREOUENCYlfI-Hz

FREOLi.ENCYtll-Hz

I5i

I

~

IIIOOJA. __

z

SUPPLY VOLTAGE: '1',6'1,'1-'-6'1

I:

, ,

~

CAPACITOR
COMPENSATION
(BETWEEN TERMINAt,S 16S1
IU""~VVOLTI'

v' ••1, V"_ •
OUIUCU'TCURRENTIIIl"!O~'"

a'

A_ENTTEMPERATUREIlAI-Zli'C
LClADIWEDANCE. R~-'GIIUI.CL-'OOgf

,UIlIlAeKRUI$TANefIRFI·Q.,MU
IlUTPUTYOLTAGEIVOppl-'GV

a~~~:~~:!~:f.~~~~
'R,.C,_2.,a-51

102030010506010
CLOSED-lOOP NON-INVERTING VOLTAGE GAIN

06

291040

19J

30

AI
IOPTIQNAl
RZ-CZ fCOMP

dB
~

6070

ClOSED-LOOP INVERTING VOLTAGE GAIN -

dB

Fig.22 - Transient response and slew-rate,
unity gain (inverting) test circuit.

Fig.21 - Slew rare vs. closed-loop gain
for /Q =- 20 JlA - CA307BA T.

T.~.

Fig.23 - Slew, rare, unity gain (non·inverting) test circuit.

I . UnitY1IIIin Ilew FIIt8 VI. compensation - CA3078T and CA3078A T

SUPPL V VOLTS: y+ .. 6, V' "" -8

TRANSIENT RESPONSE: 10% OVeRSHOOT FOR AN OUTPUT
VOLTAGE of 100mV
AMBIENT TEMPERATURE ITAI" 2SoC

OUTPUT VOLTAGE IVOI .. ±Sv
LOAD RESISTANCE IRL' .. 10 kn

TECHNIQUE

.,

CA3018T - la .. 100 IJA

kn

COMPENSATION

"\. 1
~

~

~

~

I

1

1\1
~

ro

~

~

CLOSED-lOOP NONINVERTING VOLTAGE GAIN- dB

o

6

19.1

29.1

40

~O

60

70

a.OSED-LOOP INVERTING VOLTAGE -

Single Capacitor
Resistor&Ca citor

dB

Fig.24 - Phase compensation capacitance
1If. closed·loop gain - CA3078T.

UNITY GAIN (INVERTING) Fig. 22

3.5

C1

.2

C2

pF

kn

pr

750
350

Inpu~

CA307BAT- l a=201JA
Single capacitor
Resistor & Capacitor
In ut

,.

0

VII"

0.25

0.306

0.0085
0.04
0 7

0.644

0.156

0.0096
0.027
0.29

300

100
0

RATE

.,

SLEW

UNITY GAIN (NON.INVERTING) Fig. 23
SLEW

C1

.2

C2

kn

pF

kn

pr

VII"

5.3

1500
500
0.31

0.45

0.0095
0.024
0.67

0.'

0.003
0.02
0.'

0
34

RATE

BOO
125
0

0.77

,."

·8,J~iLL:
.,
.'

'"

"AA" CELL

R,
CLOSED-LOOP NONINVERTING VOLTAGE GAIN- dB

o

6

19:1

29.1

40

~O

60

CLOSEO-LOOP INVERTING VOLTAGE -

70

SO

dB

Fig.25 - Phase compensation capacitance
vs. closed·loop gain - CA3078A T.

Fig.21- Inverting 2O-dB amplifier circuit.

Fig.28 - Non·inverting 20-d8 ampJifier circuit.

_____________________________________________________________________ 145

CA3080, CA3080A Types

Operational Transconductance
Amplifiers (OTA's)

Features:
• Slew rate (unity gain. compensated): SOV//ls
• Adjustable power consumption: 10/lW to 30 mW
• Flexible supply voltage range: ± 2 V to ± 1S V

Gatable-Gain Blocks
The RCA·CA3080 and CA3080A types are
Gatable·Gain Blocks which utilize the unique
operati onal·transconductance·ampl ifier(OTA)
concept described in Application Note ICAN,
6668, "Applications of the CA3080 and
CA3080A High·Performance Operational
Transconductance Amplifiers".
The CA3080 and CA3080A types have
differential input and a single'ended, push·
pull, class A output. In addition, these
types have an amplifier bias input which
may be used either for gating or for linear
gain control. These types also have a high
output impedance and their transconduc·
tance (gm) is directly proportional to the
amplifier bias current (IABC).
The CA3080 and CA3080A types are not·
able for their excellent slew rate (50 V//ls),
which makes them especially useful for
multiplex and fast unity'gain voltage fol·
lowers. These types are especially applicable
for multiplex applications because power

is consumed only when the devices are in
the "ON" channel state.
The CA3080A is rated for operation over
the full military·temperature range (-55 to
+1250 C) and its characteristics are specifi·
cally controlled for applications such as
sample·hold, gain·control, multiplex, etc.
Operational transconductance amplifiers are
also useful in programmable power·switch
applications, e.g., as described in Application
Note ICAN·6048, "Some Applications of a
Programmable PowerSwitch/Amplifier" (CA·
3094, CA3094A, CA3094B).
These types are supplied in the 8·lead TO·5
style package (CA3080, CA3080A), and in
the 8·lead TO·5 style package with dual·in·
line formed leads ("OIL-CAN", CA308OS,
CA3080AS). The CA3080 is also supplied
in the 8·lead dual·in·line plastic (MINI·DIP")
package (CA3080E), and in chip form
(CA3080H).

• Fully adjustable gain: 0 to gmR L limit
• Tight gm spread: CA30aO (2:1). CA3080A (1.6:1)
•

Extended gm linearity: 3 decades

Applications:
• Sample and hold
• Multiplex
• Voltage follower
• Multiplier
• Comparator

INV
INPUT

vNOTE PIN 4 IS CONNECTED TO CASE

MAXIMUM RATINGS, Absolute·Maximum Values:

TOP VIEW

DC SUPPL Y VOLTAGE IBetween V+ and V- terminals) .
DI FFERENTIAL INPUT VOLTAGE
DC INPUT VOLTAGE.
INPUT SIGNAL CURRENT .
AMPLIFIER BIAS CURRENT.
OUTPUT SHORT·CIRCUIT DURATION*
DEVICE DISSIPATION
TEMPERATURE RANGE:

TO-5 Style Package

36 V

±SV
V+to VI mA
2mA
Indefinite
125mW

Operating

~

o to + 70 °c
-55 to + 125 °c
-65 to + 150 °c

CA3080, CA3080E, CA3080S
CA3080A, CA3080AS .

Storage.

AMPLIFIER
BIAS INPUT

TOP VIEW

LEAD TEMPERATURE (During Soldering):
At distance 1/16 ± 1/32 in. (1.59 ±0.79 mm)
from case for 105 max. .

Plastic Package (CA30aOE)
Fig. 1 - Functional diagrams.

* Short circuit may be applied to ground or to either supply,

TYPICAL CHARACTERISTICS CURVES AND TEST CIRCUITS FOR THE CA3080 AND CA30aOA
SUPPLY VOLTS;V '+15, V- --115
10 3: SUPPLY VOLTS:V+~+I!I.V-'-I!I

+12!1'C

~ lol
~

:

,
4 II

0.1

2

I

10

100

4 'I
1000

AIilPLIFIER BIAS MICROAMPERES {lABel

0,01
2

0.1

I



./

5

10M

Peak Output Voltage:
Positive

IABC= 5/lA

~
~
~

IABC = 5/lA

Peak Output Current

Slew Rate:
Maximum (uncompensated)
Unity Gain (compensated)

110
13.6 to
-14.6

mV

IABC = 500 /lA to
16V lol IABC = 5/lA

Differential I nput Current

80
12 to
-12

/l.v;V

0.2

Input Offset Voltage Change

Amplifier Bias Voltage

150
150

mV

VIO

Magnitude of Leakage Current

-

-

0.3

I nput Offset Voltage

V OM

-

-

10

ELECTRICAL CHARACTERISTICS
Typical Values I ntended Only for Design Guidance

Negative

10~

~

Common-Mode Rejection Ratio CMRR

VICR

r-=

«l102

6VIO/6V-

Common·Mode Input·Voltage
Range

V

2

468

468

I
10
100
1000
AMPLIFIER BIAS MICROAMPERES (IAB1~cS'175'3

Fig. 8 - Amplifier supply current as a function of
amplifier bias current.

_____________________________________________________________________ 147

CA3080, CA3080A Types
ELECTRICAL CHARACTERISTICS
For Equipment Design
TEST CONDITIONS
V+=15V,V =-15V
IABC= 500j.tA
TA - 250C
(unless indicated
otherwise)

CHARACTERISTIC

Input Offset Voltage

ItlVlol

Input Offset Current

110
II

Peak Output Current
Peak Output Voltage:
Positive
Negative
Positive
Negative
Amplifier Supply Current

gm

Ii0MI

V+OM
V OM
V+OM
V OM

Typ.

-

0.3

TA = -55 to+ 1250 C

-

-

Max.
2
2
5

IABC = 500 IIA to
IABC= 511A

-

0.1

3

mV

0.12

0.6

IIA

2

TA = -55 to + 125 0 C

-

5
8

7700
4000

9600

0.4

TAo -55 to + 125 0 C
IABC - 5 IIA, Rl - 0

Input Resistance

Amplifier Bias Voltage

5

7

Rl - O,TA - -55to +125 0 C

300

-

650
-

IABC 511A
Rlo=

12
-12

13.8

-

-14.5

-

-12

13.5
-14.4

0.8

1

1.2

mA

24

30

36

mW

-

-

IABC = 0, VTP - 0

-

0.08

150
150
5

IABC = 0, VTP = 36 V

-

0.3

5

IABC = 0, VDlFF = 4 V

-

0.008
110
13.6 to
-14.6
26

5
--

nA

80
12 to
-12
10

-

V

0

12

Rl ==

VICR
RI

0.71

VABC

BWOl
CI

f = 1 MHz

Output Capacitance

Co

f = 1 MHz

Output Resistance

RO

Input·to·Output Capacitance

CI-O

f - 1 MHz

15
0.024

SR

6VI0/6T

-

IABC = 100llA,
TA=-55to+1250 C

3

~

6.

4

•

10

68

100

1000

92CS-17594

Fig.9 - Total power dissipation
amplifier bias current.

85

a function of

IIA

V

-

IIV/v

Fig.

to - Leakage current test circuit.

nA

dB

,

•

SUPPlY VOLTS:V·>+15, V-·'I!)

·,
,
·,,
,
·,
,
·,,

./

,0

-

kn

CA3OBOA
CA3080AS

75
50
2
3.6
5.6

Input Offset Voltage
Temperature Drift

12000
IImho
-

500

ELECTRICAL CHARACTERISTICS
Typical Values Intended Only for Design Guidance

Slew Rate:
Maximum (uncompensated)
Unity Gain (compensated)
Open·loop Bandwidth
Input Capacitance

IIA

350

Common-Mode Rejection Ratio CMRR

Common·Mode Input·Voltage
Range

-

,,
AMPLIFIER BIAS MICROAMPERES IIABel

Rl=O

Device Dissipation
Po
Input Offset Voltage Sensitivity:
I
Positive
6V10/6V+
Negative
6VI0/6V

Differential Input Current

-

mV

3

IA

Magnitude of leakage Current

UNITS

LIMITS
Min.

Forward Transconductance

(large signal)

CA3080A
CA3080AS

IABC = 5/.LA
VIO

Input Offset Voltage Change

Input 8ias Current

TYPICAL CHARACTERISTICS CURVES AND
TEST CI RCUITS (Cont'd)

./

OJ

V

V/j.ts
MHz
pF
pF
Mn
pF

~~

."'~

.4.";)

"'
/
V
./

./
./

.,j,

Q

/'

./
/'

"

AMBIENT TEMPERATURE (TAl-C·

'"

Fig.tt - Leakage current as a function of temperature.

IIV/oC

Fig. 12 - Differential input current test circuit.

148 _____________________________________________________________________

CA3080, CA3080A Types
TYPICAL CHARACTERISTICS CURVES AND TEST CIRCUITS (Cont'd)
SUPPLY VOLTS: \1 ... +15 .... -· -15

.,

10 5, SUPPLY VOLTS: \/-1-'+15, "'-'-15
~

~

10'

SUPPLY VOLTS:V"'+'5,V .-15

i

-, ,
I 10"

,

100,

/

~ :'
,

/

~

IO;~F=+125.C

10

,

~

10

I

;

I

/

,

.

,

,
001
..

INPUT DIFFERENTIAL VOLTS

(; II

0.1

..

I

10

2:

6 II

100

lOCO

AMPLIFIER BIAG t,lICRQAMPERES (IABe)

.. , .

.. 6 I
I
10
100
1000
AMPLIFIER BIAS MICROAMPERES (IAB~!CS_111500

92CS-175"

Fig. 13 - Input current as a function of

Fig.1S - Input resistance as a function of
amplifier bias current.

Fig. 14 - Transconductance as a function of
amplifier bias current.

input differential voltage.

T SUPPLY VOLTS:V ....... I:i.V-.-I:i
AMalENT TEhlPERATURE ITA I' Z:i'C
FREOUENCY 1I1'IMHz

v
£ 300

r-

! 200f-I--+-++ft-+-+-++-I-++-+++-+--r-f-I-I
,
2

0.1

..

2:

6 II

I

2:

"II I

10

..

6 It

l

100

..

I

, II

2

4

1000

AMPLIFIER BIAS MICROAMPERES (IABC~12CS_11601

~

8

r

2

4

~,

2

4

6 8

10

2

~

100

2

6 8

4

1000

AMPLIFIER BIAS MICROAhlPERES \lABel

10.

AMBIENT TEMPERATURE ITA,02:5'C

...

FREQUENCY (I). I MHz

~O.06

2

468

1000

Fig. 18 - Output resistance as a function of
amplifier,bias current.

Fig. 17 - Input and output capacitance as a
function of amplifier bias current.

Fig. 16 - Amplifier bias voltage as a function of
amplifier bias current.

68
I
10
100
AhlPLIFI[R BrAS MICROAMPERES (IABC'

;::;o.o~

~

;:; 0.04

§

•

... 0.03

5

90.oz

~

~ 0.01

SUPPLY

Fig. 19 - Input-to-output capacitance test circuit.

,'.",

VOLTS-\V~

V-I

Fig.20 - Input-to-output capacitance as a
function of supply voltage.

APPLICATIONS

LOAD
(SCOPE PROBEI

g
,.n}--J

TIr,~E-G.II'-S/c.IV.

.DDI ... F

92C5-24034

Fig.21 - Schematic diagram of the CA3080 and CA30BOA in a unity-gain voltage follower
configuration and associated waveform_

149

CA3080, CA3080A Types

SLEW RATfllN SAMPLE MOOE}" 1.3 VI,...
ACOUISITION TIME-031'1

• TIME REOUIRED FOR OUTPUT TO SEnLE
WITHIN

.!3mv OF A 4- VOLT STEP

">K.
SAW'lE OVlf
I«JLD

-I~V

Y--15V

(a) - Two-tone output signal from the function
generator. A square·wave signal modulates
the external sweeping input to produce
1 Hz and 1 MHz, showing the 1,000,00011
frequency range of the function generator.

Fig.22 - Schematic diagram of the CA3080A in a sample-hold configuration.

20pF

G·ZKtl;

BUfFER
VOLTAGE FOLLOWER

+1.5\1

CENTERING

THRESttOlO
DETECTOR

IOOKn

75V

92C5-28586

(b) - Triple-trace of the function generator sweeping to 1 MHz. The bottom trace is the sweep·
ing signal and the top trace is the actual generator output. The center trace disr1ays the
1 MHz signal via delayed oscilloscope triggering of the upper swept output signal.

Fig.23- 1,000,000/1 single-control function generator- 1 MHz to 1 Hz.

Fig.24 - Function generator dynamic characteristics
waveforms.

°l
-15

n

rSAMPLE

UU

HOLD

",.n

'.6

.n

INPUT-'M-~}}-j

2k.
OJI'F

+-----:----!

SIMULATED lOAO--: 30 pF
NOT REQUIRED

-.b-

LARGE-SIGNAL RESPONSE
SETTLING TIME
TOP TRACE; OUTPUT SIGNAL

AND

15 V/Dlv. AND 2~s/DIV.1
BOTTOM TRACE: INPUT SIGNAL
15V/OIV. AND 2~s/DIY,1
CENTER TRACE:OIFFERENCE OF INPUT AND OUTPUT
SIGNALS THROUGH TEKTRON IX
AMPLIFIER 7AI3
(5mY/OIV.AND 2,.,../0I\l'.)

SAMPLING RESPONSE
TOP TRACE: SYSTEM OUTPUT
! 100 mll/OIIl. ANO 500 n,/OIII·)
BOTTOM TRACE: SAMPLING SIGNAL
t 20 11/0111. AND 500 nt/OlV.)
92CS-2188~

Fig.25 - Sample- and hold circuit.

150

Fig.26 - Large·signal response and settling time
for circuit shown in Fig.25.

Fig.27 - Sampling response for circuit
shown in Fig. 25.

CA3080,CA3080A Types

ALL RESISTORS 1/2 WATT
UNLESS OTHERWISE SPECIFIED

TOP TRACE ~ OUTPUT
(SOmV/OIV. AND 200nI/DlV.)
BOTTOM TRACE~ INPUT
(50 mV/DlV. AND 200 nl/DlV.1

92CS-22119RI
!UCS-27883

Fig.28 - Input and output response for
circuit shown in Fig. 25.

Fig.29 - Thermocouple temperature control with CA3079 zero voltege switch
the output amplifier.

lIS

+7.5
+7.5

.,
INPUT

2 K

~

SAMPLE O V l f _
STROBE 115 K
HOLD

-7.5

Fig.30 - Schematic diagram of the CA3080A in a IBmplehold circuit with BiMas output amplifier.

TOP TRACE: OUTPUT-e VlDIV. a 2,../DIV.
CENTER TRACE: DIFFERENTIAL COMPARISON OF
INPUT a OUTPUT-2mV/DIV. 8 Z ,..../OIV.
BOTTOM TRACE: INPUT-!SV/OIY. a 2 ""I/OIV.

Fig.31 - Large-signal response for circuit shown
in Fig. 30.

TOP TRACE: OUTPUT-20mVlOIV. 8100n1/01Y.
BOTTOM TRACE: INPUT-ZOOmVlDIY. 8100na/DIY.

Fig.32 - Small-signal response for circuit shown
in Fig. 30.

_____________________________________________________________________ 151

CA3081, CA3082 Types
General-Purpose High-Current
N-P-N Transistor Arrays
CA3081-Common-Emitter Array

CA3082 -Common-Collector Array
Directly Drive 7-Segment Incandescent Displays
and Light-Emitting-Diode (LED) Displays

Features
• 7 transistors permit a wide range of applications in either a common-emitter
(CA30811 or common-collector (CA3082t configuration
- HigblC: 100 mA max_
- LowVCE ... (,'50mAI: O_4Vtyp_

Applications
• Drivers for:
- Incandescent display devices Ce.g. RCA NUMITRON DR2000Seriesand lamps'
- LED (e_9- RCA-lIG1002 GoAl High-Efficiency Emitting Oi....1
~

Relay con~rol

- Thyristor firi",

RCA-CA30a,· -and CA3082- consist of seven high·current
(to 100 mAl silicon n-p-" transistors on a common monolithic substrate. The CA3081 is connected in a common·
emitter configuration and the CA3082 is connected in a

I.'

COMMON~EMITTER

I"

COMMON-COL.L.ECTOR CONFIGURATION

CONFIGURATION

common-collector configuration.

The CA3081 and CA3082 are capable of directly driving

Fig. , -Functional diagrams of types CA308 1 and CA3082.

seven-segment displays, such as the RCA NUMITRON
devices (DR2000 and DR20101. and light-emitting di()de
(LED) displays. These types are also well·suited for a variety
of other driver applications. including relay control and
thyristor firing.
The CA3081 and CA3082 are supplied in a 16·lead dual-inline plastic package, and the CA3081 F and CA3082F in a
l6-lead dual-in-line frit·seal ceramic package, which includes
a separate substrate connection for maximum flexibility in
circuit design.

MAXIMUM RATINGS, ~Iute-Maximum Values at T A '" 2SoC

Power Dissipation:
Total
-~------------------------,---------------,-package ________________ , _____ , _ _ _ _ _ _ _ _ _ __ __ _ _ _ _ __ __ _

Above 550C
TYPICAL STATIC CHARACTERISTICS FOR EACH
TRANSISTOR OF TYPES CA3081 AND CA3082

..
'00

i
iI
~

Y~

g

~ rrrTTEj

I, ,It.
~'~ [::::v

60

!-

0'<_ I--

~V
V

.,-, .
'0

'III

2

Ambient Temperature Range:

At distance 1/16" ±1132" (1.59 mm to.79 mm)

(IvyJ']

tlq~;:;-c.

1--1-TO

VOLY

mW
mW
mWf'C

Operating ................................................ -65 to +125
Storage .................................................. -65 to + 150
Lead Temperature (During Soldering):

iIIL~~r- r-....

eo

li!.

~

COLLECTOR

750
~

••••...•...••••.••..•..•.••.•......•.•.. Derate linearly 6.67

from case for 10 seconds max. • .•...•........•.•...•..•.....
The following ratings apply for each transistor in the device:

265

Coliector·ta·Emitter Voltage (VCEOI ........................... .

16

Collector·to-Base Voltage IV CBO) .............................. .

20

V

Collector·to·Substrate Voltage (V CIO )-................... .

20

V

Emitter-ta·Base Voltage (VEBOI ............................... .

5

Collector Current (lC) ........................... " ........... .

100

mA

Base Current lIel ........................................... .

20

mA

• The collector of each transistor of the CA3081 and CA3082 is
i~leted from the substrate bv an integral diode. The subtlrate must
be connected to I voltage which is mOn! negative than any collector
vattllg' in order to maintlin i~lation between transistors and

4 ' 8 10

COLLECTOR MILLIAMPERES IIc I

v

V

provide normal trensistor action. To avoid undesired coupling
between transistors, the substrate terminal (51 should be maintained
at either DC or signal IACI ground. A suitable bypass capacitor can
be used 10 astablish a signa' ground.

Fig_2-hFE "'_ Ie

,

1.0 SET DC fORWARO~CURRENT TRANSfER RATIO '''fE''IO

,AMeIENT TEMPERATURE ITA,025·C

~ o.9}--t--+--+-++--+---l-if--H

~

0.'

vV'
~jo.el---t--+--+-++/""";4---l~t-+-l

~

.-.....----------i O.7'\"-~1---+--I-++--+--1-1+-t-I

~~ 0,.

'h

,.~~

,

a_

I

~~

I

~ io.6

~

8

0.'
0

4

"10

COLLECTOR WILLIAMPERES IIC'

Fig.3-VSEsarVl'·'c

•

'100

.
SETOC rOl'lWARO'CURRENT TRANSfER RATIOI"rEI'IO
AMBIENI TEMPERrUREITAI.25.C

I

i

z
2

I~.",~•

~~0'1--+--+-+-Hl---+v-+L-+v7'l-/-H

/

*~
~u:

//1

- -Pft:J
, . 10

2

II

~~;o.el--+--+-t-t+--t--jf-t-H
II

/
I

4

/

•

8 tOO

0,'

2

= ~C.

"",

1YPICAL:

4

..

~

.---

,

10

,

'100

COLLECTOR MILLIAMPERES 'IC'

COLLECTOR MILLIAMPERES IICI

Fig.4-VCEl8t w. ICat TA

~

•••

0.' -::::::~
,I"""

Fig.5-VCElllt vs. leat TA -ld'e.

152 __________________________________________________

~--------------

CA3081, CA3082 Types
ELECTRICAL CHARACTERISTICS •• T A ' 25°C
For Equipment Design
LIMITS

TEST CONDITIONS
Typ.
Char.

SYMBOL

CHARACTERISTIC

~
Fig. No.

UNITS
Min.

Typ.

Max.

-

IC· 500/lA, 'E· 0

-

20

60

Collector-ta-Substrate Breakdown Voltage VIBRICIO

ICI" 500/lA, 'E· O,IB· 0

-

20

60

Collector-ta-Emitter Breakdown Voltage

V BRICEO

Ie - 1 rnA, Is - 0

24

VIBRIEBO

IC - 500/lA

-

16

Emitter-ta-Base Breakdown Voltage

5

6.9

-

VCE' 0.5 V, IC· 30 mA

-

30

68

-

VCE· 0.8 V, IC· 50 mA

-

40

70

-

IC-30mA, IS'" 1 rnA

3

-

O,B7

1.0

Collector-ta-Base Breakdown Voltage

VIBRICES

DC Forward-Current Transfer Ratio

Base-ta-Emitter Saturation Voltage

hFE

Vse

sat

V
V
V
V

V

Collector-ta-Emitter Saturation Voltage:

CA30B1, CA3082
VeE sat

CA3081
CA30B2

Ie'" 30 rnA. Is = 1 rnA

-

-

0.27

0.5

Ie'" 50 rnA, IS'" 5 rnA

4

-

0.4

0,7

IC- 50mA,'s = 5 rnA

4

-

0.4

0.8

-

-

10

"A

1

"A

= 10 v,

Collector-Culoff·Current

ICED

Vee

IS = a

-

Collector-Cutoff Current

ICBO

VCB·10V,IE·0

-

V

"4"
J'.

TYPICAL READ·OUT DRIVER APPLICATIONS

I CO,"" '"'ON COLLECTOR!

~
mo'," ~'O::~~,:~~m"
""EG"," 0'

"

LIGHT· EMITTING

DIODE (LEOI

INCANDESCENT OISPLA."
IRCA-DR2000 SERIES
OR EQUIVALENT)

FROM

1/1 CA3061

-THE RESISTANCE

r~

R IS OETERMINEO 8Y THE RELATIONSHIP
wtlERE: VP'~~L~~b~LSE

Vr' b~~:Afc?R~fiV'~l
DlODE

Fig.6-Schematic diagram showing one transistor of
the CA3081 driving one segment of an incandescent display.

Fig.7-Schematic diagram showing one transistor of
the CA3082 driving a light-emitting diode
(LED),

__________________________________________________________________ 153

CA3083
General-Purpose High-Current
N-P-N Transistor Array
RCA-CA30B3 is a versatile array of five high-current (to
lOOmA) n-p-n transistors on a common monolithic substrate.
In addition, two of these transistors (Q1 and Q2! are
matched at low currents (i.e. lmAl for applications in which

offset parameters are of special importance.
Independent connections for each transistor plus a separate
terminal for the substrate permit maximum flexibility in
circuit design. The CA3083 is supplied in a 16-lead dual-inline plastic package, and the CA3083F in a 16-lead dual-inline frit-seal ceramic package.

Features
•

High Ie: 100mA max.

•

Low Vcesat (at SOmAl: O.7V max.

•

Matched pair (01 and Q21VIO (V SE mate"hed): ± 5 mV max.

110 (at , mAl: 2.5 ~A max.

• 5 independent transiston plus separate substrate connection
• The CA3083 is e"".bl. in I sul.d-lunction
&elm·L..d version ICA3083LJ. For furth..

File No. 516, "a..m-Lead
Devices for Hybrid Circuit Application....

inforrnltion _

Fig. I-Functional d;agram of the CA3083.

Applications

• Signal processing and switching systems operating from DC to VHF
•

Lamp and relay driver

• Differential amplifier
ELECTRICAL CHARACTERISTICS ~t T A::: 25 0 C
For Equipment Design

• Temperature-compensated amplifier
• Thyristor firing

TEST CONDITIONS

• See RCA Application Note, ICAN-5296 "Application of the RCA·CA3018
Circuit Transistor Array" for suggested applications

CHARACTERISTICS

LIMITS

Typ.
Char.
Min.
Curve
Fig. No.

SYMBOL

Typ.

MAXIMUM RATINGS. Absolute-Maximum Values at T A = 2So C

For Each Transistor:

Power Dissipation:

Collector·to·Sase
Breakdown Voltage

V(BR)CBO

Ie'" 100}JA,IE" 0

20

60

Collector· to· emitter
Sreakdown Voltage

V(BR)CeO

Ie" lmA, IS '" 0

15

24

Collector·to-Substrate
Breakdown Voltage

V(BRICIO

20

60

Emitter·to·Base
Breakdown Voltage

Anyone transistor .
Total package .
Above 55°C

mW
mW

500
750
....... Derate linearly 6.67

mWioC

.. -·5510 +125
6510+150

°c
°c

Ambient Temperatule Range:
Operating.
Storage .
Lead Temperature lOuring Soldering):
At distance 1/1S"
from case

fOI

~1/32"

(1.59 mm ±0.79 mml

10 seconds max.

"c

265

The foHowing ratings apply for each transistor in the device'

V(SRIEBO

IE" 500pA, IC" 0

6.9

Iceo

Vce" 10V, IS::: 0

Collector·Cutoff·Current

ICBO

VCS ::: 10V, Ie" 0

-

"FE

Vce'" 3V

V BE

Vce'" 3V, 'C" lOrnA

VCEsat

Ie" SOmA, IS" SmA

Colleclor·to·Emitter Voltage fVceol .

15

V

Collector·to·Base Voltage (VCBOI.

20

V

Sase·to·Emitter Voltage

Coliector·to·Substrate Voltage IV CIOI-..

20

V
V

Collector· to· e mit fer
Saturation Voltage

40

IC" 10mA

J

IC" 50mA

ColIl!ctor Current (lei.

100

mA

For Transiston 01 and 02 (As a Differential Amplifier):

:35e Current IIBI.

20

rnA

Absolute Input Offset
Voltage

Iv,oI

Absolute Input Offset
Current

1' 101

The colleClor 01 e~ch lfa"'1'510r of Ihe CA3083 is i~olaled from the substrate by an i... tegral dIode. The substrate
must be co ...... ected 10 avollil.ge ..... hich;s more ... e9ilUv.c tha ... a ... y coile<;tor .voflage i.... order 10 mai ... ,~i ... isolatio ...
bet ..... ee ... Iran~'Slors a ... dprov,de ... ormalua... s,stor act'o .... To avo,d u ... deslfed couplmg bet .....ee ... tra ... slstors, the
substrate terminal (5) should be maintained at either DC 01 s'gnallACI ground. A suitable bypas$ capac, tor C(ln
be used 10 euabli~h H~,g ... al grou ... d.

UNITS

V

Ie" 0

Collector ·Cutoff ·Cu rren I

DC Forward·Current
Transfer Ratio

Emitter·lo·Base Voltage (VEBOI .

lei" 100pA, IB '" 0,

Max.

V
10

~A

1

pA

76

40

75

0.65

0.74 0.8:3

V

0.40 0.70

V

1.2

5

mV

0.7

2.5

pA

Vce '" 3V, IC" lmA

TYPICAL STATIC CHARACTERISTICS
FOR EACH TRANSISTOR
!~~I~~;~~~~~~~;~~~E(~:):R2A5N.S:ER RATIO (~FE)'IO

I

~

0.'

cr

~ 0.6

":::k

~~
~g

0.'

'2CS-I11'"

Ie

Fig.3- VSE vs

Ie

-

°

COllECTOR MILL.tAMPERES (IC)

Fig_2- hFE vs

/

04

~
g"

. .. ,

1/

f--

/

/

V

~ (t~

~"

f....--- ---

,

,

.~ . .
'0

,

,

COLLECTOR MILLIAMPERES lIe)

FigA- VCEsatVSlcat2sOC

154 ____________________________________________________________________

CA3083

!
!

! SET DC F'ORWARD-CURAENT TRANSFER RATIO IlIrEI'IO'
AMBIENT TEMPERATURE ITAI '25·C

,--,---t---t-1

0.91------ t-:--r- -

/
/

v

/
/

,.

,.

COLLECTOR MILLIAMPERES 11C'

COLLECTOR IoIllUAt.IIPERES(IC'

Fig.5- VCEsat

VS

'cat 7tPC

Fig.6 - VBElllt V$' JC

TYPICAL STATIC CHARACTERISTICS FOR OIFFERENTIAL AMPLIFIER
E

" .".,

6 COLLECTOR-tO-EMITTER VOLT IVCE" 3"

~ :=~~l""""
~

~ 'r--- --~ -.
; 'f--f-

i •I COLLEt OfI-TO-tMITYERVDLTSlvCE";'V
AMBIENT TEMPERATURE ,TA "

-0

V

:

V

5 2.~-+---r~-+-r---+~--t~~~9

~

v/

:1
.~ '±:===E==~==f;~~==~==~~~

V

~

i

~

~

:

I

~

.. ,

2,)"C

'~-+---r~-+-r--+--r-i-~

~
,

•

10

COLLECTOR MllLlAMP[R[SIXC.

Fig.7 - V 10 vs Ie (transistors Ot and 02asa differential
amplifierJ.

4-r--+!-~--;~~+-r--+---r-t-t~

2V

V

,
COLLECTOR MILLIAMPERES Ue l 921:5-11119

Fig.8-I ,O VS Ie (transistors 01 and Q211$8 differential
amplifier).

_____________________________________________________________________ 155

CA3084
General-Purpose P-N-P
Transistor Array

FEATURES
• Matched transistor pair (Q1 and Q2)
VIO (V BE matched): ± 6mV max.

110 lat 100 ~A): ± 0.6 ~A
RCA-CA3084 is a general-purpose silicon p-n-p transistor
array incorporating two independent transistors. a Darlington
circuit, and a current-mirror pair with a shared diode.

• Wide operating current range
•

Low noise figure - - 3.2 dB typo at 1 kHz

• The CA3084 is available in a sealed-junction
Beam-Lead version (CA3084L). For further
information see File No. 515, "Beam-Lead
Devices for Hybrid Circuit Applications".

The two independent transistors in the array may be used in

a variety of circuit applications. The Darlington pair may be
employed as the equivalent of a single high-beta transistor.
The current-mirror pair is well suited for constant-current
applications and can also be used as the active loads in a
differential amplifier which uses n-p-n transistors.

APPLICA TlONS

The total array is especially useful for a wide range of
applications in systems having low-power and low-frequency
requirements. Although the transistors may be used as
discrete units in conventional circuits, they offer the
advantages inherent in integrated·circuit construction, that is,
to provide close electrical and thermal matching.

•

The CA3084 utilizes the 14·lead dual·in·line plastic package.

• Complementary uses with RCA n-p-n transistor arrays

• General use in signal processing systems having low·power
and low·frequency requirements
Fig. 1- Functional diagram of the CA3084.

• Differential amplifiers
• Temperature compensated amplifiers
Active loads for differential amplifiers using
n-p-n transistors

STATIC CHARACTERISTICS FOR EACH TRANSISTOR

10

EMITTER CURRENT lIE}' 0

/'L
MAXIMUM RATINGS, Absolute-Maximum Values at TA'" 25°C
Dissipation:
Anyone transistor .

mW'

200

Total package ................ .

750

mW

derate linearly6.67

mW;oC

-55 to +125
-65 to +150

°c
°c

+265

°c

Coliector·to·Emitter Voltage IV CEO) .

-40

V

Collector·to-Base Voltage IV CBO)

-40

V

40

V

Above T A '"

550 C

.......................... .

Ambient Temperature Range:
Operating.
Storage
lead Temperature (During Solderingl~
At distance 1/16 ± 1/32 inch (1.59 ± 0.79mml
from case for 10 seconds max ............. " ................ " ..

o
AM81ENT TEMPERATURE (TAl -

9Zt5'1796fi

The following ratings apply for each transistor in the device:

Base·to·Substrate Voltage IV BIO ) * .
Emitter·to·Base Voltage IV EBO) .
Collector Current

(lei

-40

V

-10

mA

DC

Fig.2-I CBO vs TA ·

BASE CURRENT !leI' 0

·T.he base of each transistor of the CA3084 is isolated from the substratc by an integral diode. The substrate must be connecled to 

50

45

0.'
%t"C

25V. '50mAStep

V'IN = 25V. I

~

o

"

AMBIENT TEMPERATURE (TAI-OC

0.8

08

1 kHl, 1V Step

O'

tOFF

# 30V ICA30S51. 40VICA3085AI, 50VICA30B5BI
• RSCP, Short·clrcull protection .es;~lance

• load Regulation -

~

X

VOUT(mltlall

1~

Fig.6-No,malized 'quiescent vs. TA •

- Bandwidth DC to 10 MHz.

t! ~:T~~/~~~~~:~~!~IO~~~:-~

~~-•. ~~

t1=

lOa INPUT VOLTS (V+INJ-21V'

6 AMBIEN~
I' 25_C+-+-+++-+--V-Hi
.~4,~~j.~~1~4+w~+m
I

,-;:C-r-'

AMBIENT TEMPERATURE ITA 1-

0

TEMPERATURE ITA

r:;;. :;;t~ ~C;:::~::::: +~

2

'c

4

6

a

2

I

4

6

e

10

2

4

r. e

100

2

4

6

a

1000

-25

0

25

50

15

AMBIEioH rEM-PERArURE ITAI-oC

F"REOUENCY Ifl-kl-lZ

Fig.7-Line regulation temperature characteristics.

Fig.B-ro vs. f.

Fig.9-Normalized

'0

V$.

TA.

REFERENCE VOLTS IVREF1·+1.6Y IAT TA"25"CI

LOAO

CURRE~T

IILI'O

ZZ

~~-O.I

~~

33·0,"-

loopF

00

"

AMBIENT TEMPERATURE ITAI-"C

"

AMBIENT TEMPERATURE ITAI-"C

Fig. 11- Temperature coefficient of VREF and VOUT.

Fig. 12- Test circuit for noise voltage.

160 ________________________________________________________________________

CA3085, CA3085A, CA3085B Types
TEST 'ROCEDURU FOR TEST CIRCUIT fOR
AI"i.E REJECTION ANDOUTIlUT RESIITANCE
CMpuI R"luance
III~'

I.

lOOpF

.25V,CAEF • D,S_lEI

2, SetEn.tlkH,tolhIlE2" .. II .....

:) flf", "OUT on. VT\lM. l\lel! as. H.wI,n·Plck'fd.
HP.OOOo"Qu, ... I'"1

"J]

•. Calc...." ROUT I'DmAOUT • "OUT IIALIE2 I

Ri .... R.jtctk»n -I
I

VIN" -:lSI/.CREf • D,ShortE2

2. St.

f$l II hHr 14 Ihiol I!! • )V .....

3. A..d '-'OUT 0'1' VTVM. luch II. HIIWItIII.PUIl.,d, HPoIOOO

"~>------------cc~

O'teI",,,,I...,

to Clte"I,,,

A,~.

1'I.I.CI'On ....... 2(11 ... (E'''''OUTI

Rippl. AtjKtion - II

Fig. 13- Test circuit for ripple re/flCtion and output resistance.

VOUT

.n·

'0'"

',,,

-

--

--

,

mY em

~-~-

-

YPULSE
GEM.

- __ t

l,us/cm

92CS-I'9001

YOUT' I~Y

Fig. 14- Turn-on and turn-off recovery time test circuit with

'THE LUIITINCCIJIIREHT IS
IHVUSElYPADPORTlOliALTO

aswciated waveforms,

RSCp(SHORT·CIRCUITPROTECTiOtOIIESISUltCEI

Fig. 15- Test circuit for VREF, 'quiescent, Vour(max.}.
Vour(min.}.

Fig. 16- Test circuit for limiting current

TVPICAL REGULATOR CIRCUITS USING THE CA3085 SERIES

"

SUIICO"TPl

0-4

.,," j
_HITE

~,,1111

3

"
GREEN

"""

"m

.n.

0,

v,.

VOJT
OUTPUT

10

6UCKRED

'L

'.'
'"
O.OOIJloF
ALLIIUIHAHCE""'LUfSAREIHOH.d

VOUT·ISV'.lOV(OT090 .....1
RfGlILATIOH·02'1(lINeAHDlo ... ol
RIPPle <:~.s ..v AT FULL LO"'D

_

OIIlU.IMllU"'OII!QlJIYALt:NT
QIIlCA·ZlUlnOIlEQULY ... lENT

'111. 11.1 II (.... )!;.)

Fig. 77-ApplicBtion of the CA3085 Series in II rypiu/ POWflf'

supply.

Fig. 18- Typical switching regulator circuit.

'.lOUT

(~"

ALLRHllhIlCEY.l.LUEI ... REH.QNMI
OIIlCA·1N1I01QREQUIY"'UIIT

01 AII'PNPIILlCONHIUlIIHOR
iR( ... 1!oI~)21 Oll EQUIV"'LENTI

OJ

roo.... :!~"!lA
Ql

O.OOlJloF

"

AMTN'NIIl!CQNUAldIlTOIl
Tt!AtC"'NKUlDLeA1A
LOAD CUIIAEMT ~UCI4 A~
II(A IN)lnOIl EOVIVALfll'

ANYNPII\ILICONTRAN\IHOII'T"UCA"
K... NOLETI4EOBIIIEDLO"'O(UlI'lIfIlT
IRCAlNlrll011 EOUIVALENTI

..,)

oVOUT',-.,'IiSCp

IHOIIT·(IKUIT

PIIOTECTIQNIIElIUUlC!

Fig.21- Combination positive and negative voltage r.gulatof

circuit.

Fig_2D- Typical current regulator circuit.
Fig. 19- Typica' high-current voltage regulator circuit.

___________________________________________________________________ 161

CA3086
General-Purpose N-P-N Transistor Array

Applications

•

Three Isolated Transistors and One Differentially- Connected Transistor Pair

General-purpose use in signal processing systems operating
in the DC to 120-MHz range

• Temperature compensated amplifiers

For Low-Power Applications from DC to 120MHz

• See RCA Application Note,ICAN·5296 "Application of the

transistors in conventional circuits. However, they also
provide the very significant inlii!ient adllantages unique to
integrated circuits, such as compactness, ease of physical

RCA-CA3086 consists of five general-purpose silicon M-P-"

transistors on a common monolithic substrate. Two of the
transistors are internally connected to form a
differentially·connected pair.

handling and thermal matching.

The transistors of the CA3086 are well suited to a wide

The CA3086 is supplied in a 14·lead dual-in line plastic
package. The CA3086F is supplied in a 14-lead dual-in-line
hermetic (frit-seal! ceramic package.

variety of applications in low-power systems at frequencies
from DC to 120 MHz. They may be used as discrete

RCA-CA3018 Integrated-Circuit Transistor Array" for
suggested applications.
SUBSTRATE

MAXIMUM RATINGS, Absolull-Mlxlmum Vllues It TA" 25°C
DISSIPATION:
Anyone transistor.
Total package up to T A'" 55°C
Abolle T A = 550 C

300
750
derate linearly 6.67

AMBIENT TEMPERATURE RANGE:
Operating ...
Storage

-55 to + 125
-65 to + 150

LEAO TEMPERATURE lOuring soldering):
At distance 1/16 ± 1/32 inch 11.59 ± O.79mml
From case for 10 seconds malt.....

+ 265

DC

COLLECTOR-TO-EMITTER VOLTAGE, VCEO ....

15

v

COLLECTOR-TO-BASE VOLTAGE, VCBO

20

V

COLLECTOR-TO-SUBSTRATE VOLTAGE, VCIO •.

20

V

Fig. 1 - Functional diagram of the CA3086,

The following ratings apply for each transistor in the device:

EMITTER-TO-BASE VOLTAGE, VEBO.,

TYPICAL STATIC CHARACTERISTICS
FOR EACH TRANSISTOR

V

COLLECTOR CURRENT, IC ....
mA
50
• The collector of each transistor In tha CA3086 Is Isolated from the substrate by an Integral diode. The substrata
(terminal 13) must be connected to the mOlt negative point In the external circuit to maintain isolation between
transistoJland to provide for normal transistor action. To avoid undasirable coupling between transistors, the substrati (terminal 13) should be maintained at either DC or signal (AC) ground. A suitable bypass capacitor can be
used to establish a signal ground.

10!

EMITTER CIJRRENT (I

J'0

ELECTRICAL CHARACTERISTICS at TA - 25°C
For Equipment Design

TEST CONDITIONS
Typ.
CharacLIMITS
UNITS
teriltic
Curves Min. Typ. Max.
Fig. No.

SYMBOLS

CHARACTERISTICS

Collector-to-Base Breakdown Voltage

VIBRICBO IC' IOIlA,I E =

a

-

20

60

-

V

,-

15

24

-

V

-

20

60

-

V

Collector-to-Emitter Breakdown Voltage

VIBRICEO

Ic =

Collector-to-Substrate Breakdown Voltage

VIBRICIO

IC= 101tA, ICI = 0

Emitter-to-Base Breakdown Voltage

VIBRIEBO IE = lOItA,IC= 0

-

5

Collector-Cutoff Current

ICBO

VCB = 10V, IE = 0

2

-

0.002 100

nA

Collector-Cutoff Current

ICEO

VCE = 10V, IB = 0

3

-

See
Curve

itA

DC Forward-Current Transfer Ratio

hFE

VCE = 3V,IC= lmA

4

40

100

120 COLLECTOR-TO-EMITTER VOLTstvCEI'3
AMelENT TEMPERATURE (TAl o 25'C

1 mA, IB = 0

7

5

,.,.,,~----~----~----~----~--~

"

V

-

'0
AMBIENT TEMPERATlJRE (TA J-'C

Fig.2- 'eBO vs TA'

10!

BASE CI.JRRENT(IaJ·Q

0.8 COLLECTOR-TO-EMITTER VOLTS(VcE)'3
AMBIENT TEMPERATURf(TAJ'Z5'C

./

07f-+-+-H+-+-l7l<'ft--l---H-Hf--l
~./

O.•b-"'fv--j-+++-t--H-t+-l--H-++----i

60

"

V

0.01

o'f-+--+-H+--+-I-+++--I---HH-I---I

~
2

4

6 '0.1

4

6 I! I

EMITTER MILLIAMPERES (lEI

4 6 8 10

O. I

2

4

680.1

4

6

e

I

EMITTER MllLIAMptRESIIEJ

46'10

'0

,,

AMBIENT TEMPERATURE (TA1--C

162 ______________________~--------~----~--------~----------~----

CA3086
ELECTRICAL CHARACTERISTICS at TA = ~50C Typical Values Intended Only for Design Guida~ce

TYPICAL STATIC CHARACTERISTICS FOR EACH

TRANSISTO~

TEST CONOITIONS
Typ.
CHARACTERISTICS

Chara·
teristics
Curves
Fig. No.

SYMBOL

DC Forward·Current
Transfer Ratio

hFE

Base·to·Emitter Voltage

V BE

VeE" 3 V

IC: 10mA

100

10llA

54

Ie
VeE" 3V

IE" lmA

10mA

IE

veE Temperature Coefficient

COLLECTOR-lO-BASE VOLTSlVcal"

TYPICAL
VALUES

UNITS

:tl!

;;;o.e

~

0.715

V

O.BOO

v

> "'

~
~

-1.9

Collector·to·Emitter
Saturation Voltage

V CEsat

v

0.23

IB" lmA, 'e" 10mA

06

~ o.~

,.

0.'

-"

100

IZi5

AMBIENT TEMPERATURE IT"I-·C

Noise Figure lIow frequency)

f" lkHz,V eE " 3V,

NF

3.25

Ie" l00IlA, RS" 1k n

dB

Low· Frequency, Small·Signal
Equivalent·Circuit Characteristics:
Forward Current·Transfer Ratio

hfe

100

_Sh_o_r'_.e_ir_c_Ui_'_I"_P_U'_I_m_p_ed_a_"C_"_ _+h.;.:i"_ _--lf = 1kHz, VCE

Open·Circuit Output Impedance

=

hoe

100 COLLECTOR-TO-EMITTER .... OLTSI'ICE J.3

3.5

kn

15.6

JJmho

3V, Ie = 1mA

Open·Circuit Reverse·Voltage
Transfer Ratio

I.B X 10-4

Admittance Characteristics:
Forward Transfer Admittance

8

_1"_pu_'_A_d_m_i'_'a_"_c"_ _ _ _ _ _t-y~i"--__tf::: 1MHz, VCE = 3V. Ie"" 1mA

31 -j1.5

mmho

0.3 + jO.04
mmho
1-_--/_____
\-_--/
0.001 + jO.03

Output Admittance

Yoe

10

Reverse Transfer Admittance

Yr "

11

See Curve

12

550

Gain·Bandwidth Product

VeE - 3V, Ie - 3mA

mmho

4

MHz

Emitter·to·Base Capacitance

0.6

pF

Collector·to·Base Capacitance

0.58

pF

Collector·to·Substrate Capacitance

2.8

of

6 8 0 .1

4

6 8 I

4

6 810

COLLECTOR MILLlAIoIPERES IIel

COU.ECTOR-TO-EMITTER VOLTS{vtEI-3

COLLECTOR MILLIAMPERES(Icl·1

~ 6·1-+-~~~--rt+r-r-t-Ht-~

4

l~
J=4m~tw~tt:~=1
~i
f'

;! 5~4--+~+--+-+-rH--t~-rtT.b~..

8!,o'~+-~++r-+-~rHr-r-~~~i~
ffi~

~~ 3'~~-t~+--r-+-rH--t~-tttt1--

j--

~J 4~~-+~+-~-+-rH--t~-ttt~l:...
i;;1H

i

1!"0'~+-+44+-+-+~~~~-+++~~~-1
~~nl

468

nl
FREQUENCY {f)-MHz

Fig.8- Vfe vsf.

e,. ~E::Ai~A:T~~~:ENCIES

I~~"

68

100

2

_

......
4

0.1

68.

Z
68 10
FREQUENcvtfl-MHz

68100

',:':::::!:::::::::::'"

...

'OO!'-,·;·bFFFFB+.;c..+."...+,~::t::~::t:;0;::+::~::+::g::;
700"'·-+++"'.+-..""::+-'''':::+-i.''+::'''':;:+.~...+.~::+::~::+::0;::+::0;::+:;:;;;j:::

~

0

:::h;·;·kj~!t:p:t:p$$·$'~:::*'~;:W::j: 4:;;;~+~;8~
""".,.":,':':.' .......... ,:::::;: ... .

.' ""I'" ,::.:: ,": , : , :, : : ,: : ';~
200 " '
.....

:::Ii~

-I

:i-l
~

I
10
FREQl£NCY Ifl-MHz

2

I

COLLECTOR-lO-EMITTER 'vOL.TS (VeEI·'
COLLECTOR MILI..IAMPERES(I 1·1

~

~!I

468

Fig.9- Yie _VS_f.-r___________ ____ r=="F"l Fig. 10- Yoe VS f.
r

=~'}-~~~~:A~~~iW:l~·CNPUT

~~

2

-.

,

. ..

,

. ..

~EQUENCY(t I-101Hz

,

.

:I:'::!: ::' .

I

2.

34

....

...

": ::;; :.:~ ~jj; ~;~: ;~;: ::;. ;";;

l::: ::;:

56

COLLECTOR MILLIAMPERES lIel

Fig.I'-vre vsf.

Fig.'2-f r vslc ·

________________________________________________________________ 163

CA30910

Analog Multiplier
RCA·CA3091D, a monolithic silicon integrated circuit. is a
four-quadrant multiplier that provides an output voltage that
is the product of two input Ix and Vi voltages.
This device functions as a multiplier, divider. squarer, square
rooter, and power· series approximator. In addition, this
device is useful in applications such as ideal full·wave
rectifiers, automatic level controllers., RMS converters, frequency discriminators, and voltage-controlled filters and
oscillators.

• FROM 15 -VOLT
REGUL.ATED SUPPL.Y
.FROM-IS-vt)LT
REOLl-ATED SUfPlY
•• ADJUST IS PERfORMED BY
VARYING THIS RESISTOR
RESISTANCE VAL.UES ARE
IN OHMS

The CA3091D comprises five basic circuits (See Fig. 1 I,
including: a multiplier block. two linearity compensators, a
rurrent converter, a current source for biasing, and a
regulator (reference voltage). A brief description of the
operation, functions and typical applications is given in the
section "Operating Considerations". In addition there is a
separate sectiol) on "Symbols, Terms, and Definitions" that
defines the terms and symbols used throughout the data
bulletin.
The CA3091D is supplied in 14·lead dual·in·line ceramic
package and operates over the full military temperature range
of-550C to +125 0 C.

*

Fig.1-Functional block diagram of CA3091D with typical multiplieroutboard(Peripherai)circuitry,

MAXIMUM RATINGroAbsoJute-Max;mum V.luesat TA c2SOC
DC SupplV Voltages:
., .. ,." ...... +18
Between Terms, 12and1 , ..... , .. , ... ,.,., ............• ,...
v
.. -18
Between Terms. 4 and 1 ..........................•...................
V
DC Supply Currents:
At Term. 12 with DC Supl:IIV Voltage'" +15 V ...••.•..• , .....•••.•••...• '" ......•••....
4
rnA
At Term. 4 with DC Supply Voltage = -16 V .......................................... .
16
rnA
Bias Current (At Term. 31. . . . . . . . . . . .
. ...•.. , ...•........... , ... , .. , . . . .. . ....... .
rnA
Input Current .................. , ................. , ... " ..... , .... , ........... , .... .
±1
rnA
Output Short·Circuit Duration ............ , .. , ...................... , ...... .
No limitation
Voltage Reference Current ., ....... ,., ................. , ........................... .
10
rnA
Linearitv Correction Currents:
At Terminals 7 and 8 , •...
10
rnA
Device Dissipation (Up to 1250 CI
200
rnW
Ambient Temperature Range:
. .... , , ....•.. , ............... ,. , .... , , .. -55 to +125
Operating .... ,., . . . .. . . . . . .
oc
Storage ....................... , ........................ , .. , ........ , .. , .. ,. -65 to +150
OC
Lead Temperature (during soldering):
At distance not less than 1/32 inch (0.79 mm) from case for 10 seconds max. . ..
+265

* Ellternal

Features: •
•

"Accuracy": ±4% (max,)

•

"lIneerity": 3.0% (max.)
Fe.dthrough: 9 mV p-p hyp.)

•

• 3-db bandwidth: 4.4 MHz
•

Low power operation capability: :l:6.0 V. 4 mW drain

•

Low power-supply sensiti"ity: 36 mVlV typo

• Smooth o".rload characteristics - no foldbadt if fullscale input signal is exceeded
•

Negligibl • •rm·up drift

•

Broadband operation capebility Iflat to 1 MHz) - both
inputs ha". simillr chlracteridics for reduced high·
frequency phase shift between the inputs

•

Low-Ie"ellineerity correction circuitry minimizes low·

level fetdthrough for improved smal'-signalaccur8Cy
All multiplication is performed with wideband circuitry this permits two signals of frequencies much higher than
the -3 db frequency of the multiplier to produce a difference frequency that is within the multiplieR. bandwidth

•

resistance is raQuired to limit the current to the indicated I l mA value.

~------------~~--~--~----~~----t=----~~----~'V+

•

High immunity to parasitic oscillation.

•

Essentially free from exce.s peaking - provides improyed
frequency response

•

Requires no level shifting at the output - current·source
operation at the output permits output signal to be referenced to ground or other levels within the output "oltage
swing apabilities of the multiplier

-

Internel bill regulator

Applications:
•

Multiplier

_ Divider' - Squarer

- Squa,. Rooter

• Power...ries approximator

RESISTANCE VALW,'b.:w: IN OHMS

Fig.2-Schematic diagram of the CA3091 D.

.,-

• Full-wa"e rectifier
- Automatic level controller
•
•

RMS converter
Frequency discriminator
Voitage-controlled filters and oscillators

164 __________________________________________________________________

TUTPROC(OUA(
.......-"-=---=-L-"_-'---'-,IO'["·S:.lOJUSTVJ
TOS(TVO,4V
ZCLOS('S'AOJUSf~

TO S(TVo'ZV.

R[CORO"b

c..,_-,-,--=-r,-,-,--r-:-.-"

Fig.5- Tesr circuir for measurement of inpur resistance.

0[111"'( "0 'ROM

RO("AI':~,

Fig.6- Test circuir for measurement of output resistance.

Fig.7- Test circuit for measurement of maximum slew rate.

"A'-W1.LU.

• ""ON' " . " • .,""
~
rloTAl tOAD RESISTANCE \l''-' .\ .. n

o

IO.Il'~

~~I\

i -,
~
~ -"

~

'i~l\
1\

-"
-,.

-,

. .. . . .. . . ..
FR[OU(NCY U I -

Fig.B- Test circuit for measurement of frequency response.

H~

Fig.9- y-inpur frequency response characrerisric curve with associated test circuit.

_____________________________________________________________________ 100

CA30910
ELECTRICAL CHARACTERISTICS, Typical Valuellntandad Only for Iletign Guidanca

.,·
..,

TEST CONDITIONS
CHARACTERISTICS

SYMBOL

TA -26OC,IIB-0.s mA
v+ - 16 V, V- --16 V

,'·:l J...J. 1. ~~~
~~l\\

• AMltENT TfMPERATI.ItEITA
E
TOTAL LOAD 1t£SISTAMC".;...

Circuit
and/or
Chor.

TYPICAL
VALUES

UNITS

CSTA TIC CHARACTERISTICS

~

.~\

."

INPUT CIRCUIT
Input Resistance:

hxl~0.2mA

Atx Input

RI

At V Input

6

Ilyl~0.2mA

1.3
0.5

kll

5.B
5.B

OF
OF

1.0
4.0

Mil
of

26

mV/V

36

mV/V

."
.,.

.•.

kll

Input Capacitance:
At x Input
At y Input

-

at 1 MHz

CI

.

•

&11001<

,

. .... , .

6110I0Il

FREQUENCY Ifl-Hr

OUTPUT CIRCUIT
Output Resistance

RO

Output Capacitance:

Co

DC Supply Voltage Sensitivity:
At Term. 4

6
at 1 MHz

tNO

IJ.V-

DYNAMIC CHARACTERISTICS

Fig. 10" x-input frequency response characteristic

Bandwidth (At -3d8 pOint):
Through )( Input
BW

Through V Input

curve with associated test circuit,

B,10

4.B

MHz

B,9

4.4

MHz

SYMBOLS, TERMS AND DEFINITIONS

360
310

kHz
kHz

Output Offset Current
The multiplier output current produced when both of the
multiplier input signals are in the zero state.

27

V/~,

30 Error Frequency:
Throu~

x Input

-

Through y Input

Maximum Slew Rate

SR

7pF in parallel with 10 MO load

IJ.IOO/IlT

x8iy"'O

IIIIC/IlT

x -0
y·O

7

Temperature Coefficients:

Output Offset Current
x-Input Balance Current
v-Input Balance Current
Normalized k Factor!k N "" ~l

ELECTRONICS

11

IJ.VO
IJ.V+

At Term. 12

aooNTON

C RF PROlEttl-12Dl·
OR EOU\lAL.ENT

-

kN

Accuracy
Linearity

-0.021
-0.063
-0.063

~AfOC

~AfOC
~A/OC

-

-0.76

""'fOC

0.11
0.06

%/OC
%/OC

-

5.6
5.7

Feedthrou~:

Atx=O
Aty-O

Output Zero
Sets the output at the zero level when the x and V inputs are
in the zero state. (It is implied that all other zeroing
adjustments have been effected. I

mV/OC
mV/OC

Input Resistance - Converts the input voltage to an input
current.

RL
Output (Load) Resistance - Converts the output current to a
voltage.

RO
Output Resistance - See Va and 10 for the equations
associated with these properties.
Regulator Diode
A temperatura compensated Zener diode, included in the
multiplier circuit, to provide a stable liB.

Scale Factor or k factor (k)
Represents the basic gain of the multiplier as expressed in the
equation Va"" kVxVy

TEST PROCEOURES FOR MEASUREMENT

OF POWER-SUPPLY SENSITIVITY
L

~Ic~r/~A';-~~~I~V, MEASURE Vo

2. AT V+'IOV,V-'-15\1,MEASURE Vo

RECORD AS Vo2.
POS POWtR SUPPLY SENSITIVITY'

-,,-'
V02 - YOI

3. AT V t '15V,V"--IOV,MEASUltE Vo
R(CORD AS Yo3
NEG. POWER SUPPLY SENSITIVITY'

-,-.-'
V03-VOI

liE II FACTOR
II,S O.I'REFERENCE OR
ADJUSTED II FACTOR
ItN' .,!t,'O.IVo'
NORMALIZED II FACTOR
".,.IIIt",IF ~ 'Vy.VO'101
OUTPUT CURRENT IIIIAI [AT
A CURRENT OF 0·2 IftA AT
80TH INPUTS). VO/3H.n
OUTPUT VALUES olAf AVER"
AGED FOR'" COMBIItATIONS
Va/RL

OF I"PUTSlltI'~'
Vo/3:nn

10.2110- 3 12

•

r

The equation indicates the ideal transfer function for the
multiplier, The normalized k factor is expressed by kN .. klkre1
where kref is the ideal or reference k factor, The ideal factor,
kref is the value at which the k factor is set when the k·factor
adjust control is trimmed. Optimum operation of the
CA30910 is achieved when the k·factor is 0.1.

VIM
The maximum ae sine-wave voltage to be applied to the
multiplier; a 20-volt p-p sine wave is the nominal maximum
swing voltage recommended for use with SO·kilohm input
resistors.

VMID
An ac or dc voltage that approximately satisfies the equation

VMID • VIM/12.'
r-BALANCE

OUTPUT
ZERO
BALANCE

LOW-LEVEL
LINEARITY
BALANCE

RESISTORS HAVE A TOlERANCE OF
5"1.. UN..ESS OTHERWISE INDICATED

Fip. 11- Test circuit for measurement of current gain and power-supply sensWvity.

Vo
The output product voltage derived from the expression

(kV.Vy • Vol

166 __________________________________________________________________

CA30910
Vref.
Temperature compensated zener connected to the -15 volt
supply to provide a reference voltage as an aid in setting up a
stable 'lB.

~

Vx.Vy
The input voltages to be multiplied.

/I

x-Balanca Circuit
Sets the output to the zero level when the x·input is in
the zero state.

~

y-Balance Circuit
Sets the output to the zero level when the y·input is in the
zero state.

I_

A contour map provides a true indication of multiplier
performance in each of the four quadrants. Each CA3091 D is
comprehensively tested and must provide the specified
accuracy in the four quadrants.
Current Converter
This portion of the IC combines the multiplier's differential·
amplifier output currents and converts them to a singleended output current.
Current Sources
These circuits provide the biasing currents for the various
circuits in the IC, The liB terminal provides the control
current for the current·source circuit.
Feedthrough
Feedthrough oa::urs when an output signal is produced even
though one of the input signals is zero. Con5eC..luently,
feedthrough signal characteristics constitute a source of error
in the operation of a multiplier. In the CA3091D, for
example, the feedthrough signal output is specified to be less
than 20 mV p.p when either terminal is set at 20 V p.p and
the other terminal is set to zero.
liB

I

~,o·r

o\\J

l~

~

llV V V:~

i'

i'..

I·)'

V

Terms and Oefini·
tions"Section.

ii--

f-::
lI-

\6.V.
11.[;'j ~/VIV
1111II ,r~!lr
llll\1\ Jl·t'I·~,

~~

~
'l

Linearity Adjust
An external circuit to provide vernier adjustment for
optimum linearity. This control should be adjusted before
adjusting the y-balance control.
Linearity Balance Circuit (Low-Levell
This circuit makes the mUltiplier's transfer function linear for
low-level x·input signals.
Linearity Compensator
Internal circuitry that converts input current into a nonlinear voltage, a requisite for producing a linear output in the
differential amplifiers of the mUltiplier circuit,
Multiplier Circuitry
Provides the product of the two

inp~t

voltages.

Multiplier Transfer Function
This function mathematically describes the interaction of the
·two inputs and the resulting output signal. The basic transfer
function for a multiplier is
klV x + Vxel IVy + Vyel '" Va

+ Voe

'0"

"

The basic multiplier, shown in Fig. 14a, is a two· quadrant
multiplier. The input signal IV x ) may have either a positive
or negative polarity whereas. the external gain-controlling
signal (Vy) must be positive and greater than the base-to·
emitter voltage lFig. 14bl. The output current 111-121 of the
differential amplifier, comprised of transi.stars 01 and Q2, is
related to both the input signal (V x ) and the current source
(I). Since the current source (I) is related to the gain
controlling sig"lal IVy) the output current 111-12), therefore,
is related to both Vx and Vy.

the desired value of the product output signal

Vxe • Vye :::: the "effective" errors that occur at the inputs
of the multiplier and cause an output signal
when either input is in a zero state.
Voe

'" the error voltage that develops at the output of
the multiplier

DC correction factors are added to the multiplier inputs and
output to compensate for the errors and offset variations. A
complex linearitv error term appears in the transfer function;
however, this term is not included in the above equation for
the purpose of clarity.

OPERATING CONSIDERATIONS

'.',

Fig. 13-Gain-controlled amplifier.

where: k :::: k factor and represents the basic gain of the
multiplier
:::: the external inputs to be mUltiplied

Linearity
"Linearity" indicates the degree of mUltiplier error Ii.e.
deviation from "straight· line" characteristicsl along each of
the four boundaries of the input x, y field. These boundaries
are formed when one input is held at one of the two
maximum values 110 volts or -10 volts) and the other input
is swept through the voltage range, ISee Contour Map for
additional information.1

Note: See "Contour
Map'· in "Symbols.

,-"'lIfYOLTAGltV.I-W

:::I

k.adjust
Scale·Factor Adjustment.

tt-

Fig. 12-Conrour mapping of mulriplier accuracy (plorred on isomers) and linearity.

Vx , Vy

kl
Current Scale Factor (kl) '" IR? / RUk.

i'<~

:-

"- r-.

II
~

"~

I'-

,\1\ 1\
~
~

":,,

\

\ \

Va

Ix.ly
Input currents to be multiplied.
k
Voltage Scale Factor Idetermines the gain of the multiplier).

V

~I-

'to\

-.::::::::
,Ii' (

I
\

t"

IIC
See 10C.

loe.IIC
Compensatory input and output currents required to correct
unlinearity along the x axis.IOptional for low-level si!Jlal use.)

I
J

r-.

Circuit biasing control current.

10
Output product current (kllxly :::: 10), where kl "" kR~ / RL

"..

r·"

J-

Accuracy
Accuracy defines the degree of error encountered in the
operation of the multiplier. It is portrayed on a contour map
by isomers (contour linesl. Isomers with the highest values
indicate "Iess·accurate" openition of the multiplier. ISee
illustrative Contour Map in Fig. 12.1
Contour Map
The contour map, shown in Fig. 12, is a graphical portrayal
of the multiplier errors in the x, y input plane. Each contour
line, termed "isomer", connects those points whose error
values (in millivolts) are equal in magnitude. For example, a
-20 mV contour line with points at Vx = 5V and Vy :::: -3V
indicates that the output voltage is 20 mV less than the
theoretical output product (kVxVyl. This err'or voltage,
presented in percent of fu·lI·scale input (± 10 VI. defines the
"accuracy" of the device. Thus, a 20·mV error voltage
represents an "accuracy" of 0.2% as derived from the
equation:
Accuracy:::: 20 mV/10 x 100% = 0.2%.

/':i--" I"II
\

VI

':3f"
Qz

OJ

,

v'I

=

'"

Q)

'0'
a) Basic circuir.

b) Multiplier functional
only in shaded region,

Fig, 14- Two·quadrant multiplier.
This relationship is essentially non·linear; thus an appr.o·
priata linearization circuit must be provided in the input
stage to achieve the following linear relationship:

Operation of a Multiplier
11-12=k'V x V y
A multiplier is, essentially. a gain·controlled amplifier (See
Fig. 13) that mUltiplies the input signal (V x ) with the
external gain controlling signal (Vy) to produce the resultant
output IV 0), The gain is externally adjustable by a coefficient (kl, Stated simply, a mUltiplier produces an output
voltage that is the linear product of two input voltages.

(Eq. I)

where k' is a constant

_____________________________________________________________________ 167

CA30910
Figure 16 .hows a typical orrangement of three dlfferentl.1
ampll.,... to form a four-quadrant multiplier. This arrange.
Ment Incorporates the operating principles of the two·
quadrant multiplier. but, In addition, it permits both of the
input signals (V x and Vy) to have positive or negative
polarities (or zero'. When either Input is zero, the output
current (1,-i2) must, thaoreticallv. be zero 8S is shown by
the following:

TYPICAL OPERATING CONSIOERATIONS
The RCA·CA30910, shown in Fig. 2, is a four·quadrant
multiplier that incorporates the basic multiplier principle,
prev)ously discussed in "Operation of a MUltiplier". Because
the design of this multiplier is based on the multiplication of
two input currents to produce an output current it is
necessary to convert the input voltages to input rurrents and
the output current to an output voltage by inserting resistors
at both input and output terminals. Fig. 1 shows the
four·quadrant multiplier with its peripheral circuitry for
nulling current unbalances.

1. Assume Vx " 0,
then 11 =i2 and 13" i4
therefore i1+14 = '2+i3.

Since 11 .. i1+i4 and 12 ""'2+13.
then 11 = '2.

10V. This limitation is necessary in order to prevent the
output voltage (Vol from latching to the negative output
saturation voltage of the operational amplifier. Table" de·
scribes the divider alignment procedure.
.-BALANCE
SOk

V+'15V

The Bias Current (lIB) at Term. 3 sets the operating current
level for the entire multiplier circuit by means of a
current·source circuit. Therefore. it is essential that this bias
current level remain constant under all operating conditions.
To maintain this steady state, a temperature compensated
zener diode is providect on the chip and connected to the
Reference Voltage (Term.S).

This equality is independent of Vy
2. Now Issume Vy = 0,
then is = is.
Sine is = i1 +12 and i6 = i3+i4.
then i1 +i2 = i:J+i4.
Since i1 = i3 and i2 = i4
then 1,+i4 = i3+i2.
Therefor. II =
This equality is independent of Vx .

Linearity of the differential amplifier transconductance
function is accomplished by linearity compensators as shown
in Fig. 1. To correct low·level signal unbalances that may
occur between Differential Amplifiers A and B. an external
potentiometer is connected to Terminals 7 and 8 (See Fig.
11. The Current Converter circuit, which consists of a set of
current mirrors, supplies the output current (11 -12). It is
important that circuit unbalances be corrected prior to
operation. Tabie I describes the alignment procedures for
correcting these unbalances.

'2.

A multifunctional circuit board (Figs. 16 and 17) is available
for performing the four basic applications, such as. multi·
plying, dividing, squaring and taking the SQuare root.

When the CA30910 is used as a multiplier (Fig. 18) or as a
squarer (Fig. 181 only the basic pheripheral cirooitry on the
multifunctional circuit board is utilized and the general·
purpose operational amplifier (CA3741T) is disabled from
operation. Follow the ac aliL'lment procedures for these two
applications before operating the circuit.

Fig. 16- Typical multifunction circuit arrangement utilizing
the CA3091Dand CA3741 T.

When the CA3091D is used as a divider (Fig. 20), the
operational amplifier is required in order to provide the
proper negative feedback. The limitations for operation as a
divider are that O-l

"

v,

·SEE FIG·II FOR
PERIPHERAL
CIRCUITRY

8) Circuit arrangement for divider operation,

aJ Circuit arrangement for square·rooter operation.

b) Terminal connections for divider operation,

b) Terminal connections for square-rooter operation.

Fig.20-Multifunction circuit-board arrangement with ter·
minal connections for divider operation.

Fig.21-Multifunction circuit-board arrangement with ter·
minal connections for square·rooter operation.

_____________________________________________________________________ 169

CA3093E
Features,'

General-Purpose High-Current N·P·N TransistorZener Diode - Diode Array
RCA CA3093E· Is

I

versatile

.rr.v

• 8 Ind'pindln, devlcel plul "Plr•• lubl,r.,. conn.ctlon
• Camplnlltlng tlmpiflture coefflcl.ntl - VaE end VD1
VS.VZ
Trlnsllton

of three hlgh·current

Ito 100mA) NPN tranliltors, two 10"·tol,r.ocl Zener diodes
end one conventional diode. all on a common monolithic
substrete. Two of the translltors 10, and 02) .re matched
at 1 rnA for applicltionl in which offat parameters Ire of
Ipecl.llmponanclt. The combination of positivI Zener voltage

Independent connections for elch transistor and diode plus
s separate term Ina' for the substrate permit maximum fllxi·

• High Ie l100mA ml.1
• Motehlll polr (01 1& Q21
VIO - ± 6mV mix",
I _ 1mA
110 - 2.6~A mix]
C

I'

billty In circuit design.
·Formtrlv d,vllopm,ntal type TAB1 19
aZ,. Z2 Ind Dl are transistor' iriltrnally conn.cted alshown balow.

tlVloltlT- 5~Vl'etyp

temperature coefficients and negative forward baR-emitter

voltage temperature coefficients provides a unique temper•.
ture compensation capability.

• hFE -40 mln.lc - 10mA
. or&OmA

• Law VCESlt .• , 0.7V m.x I' 60mA
Zenar Diodes
• Two 1'4W Zener,
• VZ' 7V, 10%
• 'Z-15Iltyp

MAXIMUM RATINGS. Abloluto-M.xlmum V.lu.ut TA - 25'C
Power Dissipation:

Diode

mW
mW
mW
mWtC

500
Anyone transistor ..•.........•••..•......•.....•.........................
Anyone Zener Diode .•..•••...... , ....•.........••... , •...... ,............
250
Total packags ...........................................................
750
6.67
Above 2SoC .•....•.. , ......•..• , •.. , ...........•........... Derate linearlv
Ambient Temperature Aange:
Operating ..............................................................
-55 to +125
Storaga ........ . .. .. .. . . . . . . . . .. .. .. . .. .. . . .. . . . . . .. . . . . . . . . . . .. .. .. .. -66 to + 150

• Cia.. far~ard volt... match to VBE'S of Q1 Ind Q2

• VPIV - 5.5V min.

Applications

'C
'C

• Signal praceaing and switching systems operating from
DC to VHF
• Lamp and relay driver
• Differential amplifier
• Temperature·compensated amplifier
• Thyristor firing
• Temperature-compensated shunt regulator
• Temperature-compensated series regulator
• Lavel shifting
• Voltage-level clamping
• Current regulator
• Voltage clamping
• Simple off·llne regulated supply
• See RCA Application Not•• ICAN·5296 "Application of
the ACA·CA3018 Circuit Translltor.Array"for applications
in addition to those given on pages 6 & 6 of this bulletin.

Lead Temperature (During Soldering):
At distance 1/16:t 1/32 inch U.69 ± O.79mml
from case for 10 seconds max.

• ...•••...•. , . , , ... , .. , •.. , .. , .•. , , . , ......... , ..

+265

The following maximum ratings apply for each transistor
Coliector·to·Emltter Voltage (VCEOI ........................................... .
Coliector·to·B ... Voltage (VCBOI ............................................ ..
ColieCtor·to·Substrate Voltage (VCIOI' ......................................... .
Emitter-to-Base Voltage (VEBOI ...... , . , .......... , .. , ...... , ................ .
Collector Current lie) ..... , . , ......................... , ......... , ... , ...... .
Basa Current (lBI .......................................................... .

V
V
V

15
20
20
5.5
100
35

mA
mA

35
20
50
5.5
20

mA
V
mA
V
V

V

The following maximum ratings apply for each Zener Diode or Diode
Zener Diode dc Current Ozl ................................................. .
Zener Dlode·to·Substrate Voltage (VzIOI' ..................................... ..
Diode (011 Forward Current (IDFI ............................................ .
Diode (011 Reverse Voltage (VORl ............................................ .
Diode (0 lI·to·Substr.t. VollIgs (VOIOI' ....................................... .
-Th' collector of each transistot. the c.thoc:\e of each Zen.' diode.
.nd th. anode of the dlod. ara isol.ted from th. substrate by an
Intern.1 diode. Th. tubstr.te must be connected to a voltage which
II more nlVltlva th.n .ny of these Isolated tarmlnals in order to

malnt.ln isolation between devices and provide norm.1 transistor
action. To avoid undesired coupling batwe.n dlYiees, the substrata
terminal (5) should be maintained at either dc or signallacl ground.
A suitable bypass capacitor can be used to establish a Signal ground.

Fig. 1- Functlon.1 d l _ of the CA3093E lbottom vI.w)
TYPICAL STATIC CHARACTERISTICS
I

I

~

II
~~
-~
II'! \..k~.j~~
~ho' po,.r- '10"'
0.0

_I-U~Q' I-~ ~ Q'

~

4

., I

2

IId10.6

~~
~I!?

~

O.
100
(IcCII'

IDI'

~~

0"

!

o.
0

--

,

II
/
/

,f

V

. . . .r . . .i .

I--

~

10

100

COLLECTOR MILLIAMPERES(ICI

4 ' '10

COLLECTOR MILLIAMPERES IIcl

Fig. 2- hFE vslC

~~

r--

"

2

~

V

f..- ....... ~

J

I

~ o.

0.'
I
0.1
TRANSISTOR COLLECTOA OR DtODf' MILLIAttFERES
0.1

:~~t~~;OT~~Ap~~~~~~~ErT:,~~A5N~c'ER RATIO (I!FE,oIO

TRANSISTOR tOLILii"-TO-IEMITTtR VOLTS (VCE'O'

0.'

Fig. 3- VSE VI !Cand VOt I/I/Dt

Fig. 4- VCE$IItVS/CSf2"C

170 __________________________________________________________________.....

CA3093E
ELECTRICAL CHARACTERISTICS., TA • 25°C
For Equipment Design
TeST CONDITIONS
CHARACTERISTICS

LIMITS

SYMBOL

Min.

Typ.

20

60

UNITS

MilK.

For Each Transistor:

Collector-la-Base
Breakdown Voltage

V(BRICBO

Ie '" 100j..LA, Ie = 0

ColJectOr-1o·Emitter
Breakdown Voltage

V(BAICEO

Ie '" 1rnA, Is '" 0

15

24

Collector-to-Substrate
Breakdown Voltage

V(BAICIO

lei '" l00J.CA, Is '" 0,

20

60

v

Emitter-to-Base
Breakdown Voltage

V(BRIEBO

Ie ,. SOO/AA, Ie = 0

5.5

6.9

v

Collector·Cutaff-Current

'CEO

veE" lOV, 'e

Collector-Cutoff-Current

leBO

Vea = lOV, Ie = a

'0
COLLECTOR MILLIAMPERES IICI

Ie '" a

.pc

10

0

=

I

40

76

SOmA

40

75

0.65

0.74

veE'" 3V

Forward Base-ta-Emitter Voltage

veE" 3V, Ie : fOmA

lie

;

"lOrnA

DC Forward Current
Transfer Ratio

to

SET DcrORWARD-CURRENT TRANSFER RATIO I~FEI '10
AM alENT TEMPERATURE ITAl '2S·C - - '_ _

'-'+_+-

O"r-- - - r--

Collector·to-Emitter
Saluration Voltage

Ie '" SOmA, 18 = SmA

0.40

Forward Base-la-Emitter

Ie = lOrnA

-1.9

---p- v

0.85

O,r---t----r-i-i-t,~~----r-+_~

v

0.70

o.,p..--=t-~---i-H--t----t---i-t--H

Temp. Coefficient

For Tran5istors al and Q2 (As a Differential Amplifier)·
mV

Absolute Input Offset Voltage
Absolute Input Olhet Current

hlO (

Temp. Coefficient of Ollset Voltage

I.1V IO/.1TI

veE = 3V,IC" 1rnA

f--+------j--+----j
0.7

2.5

'0

COLLECTOR MILLIAMPERES !Icl

IJV/QC

Fig. 6 - VBEsat vs

For Each Zener Oiode
Zener Voltage

Vz

IZ '" lOrnA

Zener Impedance

'z

IZ " lOrnA, fool kHz

Zener Reverse Current

'ZR

Vz = +5V

6.3

7.7

v

25

n

6 COLLECTOR-TO-EMITTER VOLTS (veE 1- :3v

~

Zener Voltage Temp. Coefficient

l:.VZ/.1T

IZ'" 10mA

Zener·to·Substrate BreakdoWfl
Voltage

V(BAIZIO

IZ = l00J.lA
(Terminah 7 & 91

Dissipation

15

20

['

---t---t--t-t---t---r-i-t""

v

v

't--- - ---t-r-t---r-----t--Vt-Tr---H

250

mW

,r----r-----t-t--t---t--+-v',£-f-/-+--+-'

0.85

v

60

Refer to EXample in
Application "a"

AMBIENT TEMPERATURE ITAI' 25'C

5~-~

-0

+3.6
+.05

Ie

For Diode (ot!
Diode Forward Voltage

IC

=

10mA, VCE

=

3V

0.65

0.74

Diode Forward Current

mA

50

6.9

v

'Diode = 100",A
(Terminal 101

60

v

'OF'" SmA

-1.9

mvfc

Diode Reverse·Breakdown Voltage

V{BRIOR

lOR = 500,uA

Oiode·to-Sub.trate
Breakdown Voltage

V(BRIOIO

Diode FOfwtrcj.Voltage
Temp. Coefficient

5.5

, , ,
COLLEcTOR MILLIAMPERES !Icl

Fig. 7 - VIO vs Ie (transistors 01 and 02 asa
differential amplifier)

A"'aIENT TEMPERATURE (T/I,I-25"C
FREDUENCY(f)'IKH:

t •

• COLLECOR-10·£UlTl[RVOLTS(v([I.)v
""'81(IH T(MP(IIAlURE !T"I·:?')·C

~

"j

,

.£

g,
~

i
"
COllECTOR MILLIAMPERESll,1 ~l~$. '11U

Fig. 8 - '10 vs Ie (rrans;stO($ A' andQ2asa
differential amplifier)

.
,

I

A1LT
I
r-

11
JMPERJUJ

1!.

II .~

50

70"C

c...:::::;

_2~·C

o"c

,
ZENER MILLIAMPERES UZI

Fig. 9 - Typ;caJ Zener breakdown voltage vs current

10

1':1

20

ZENER MILLIAMPERES (lZI

Fig. 10- Typical Zener impedance vscurrent

_____________________________________________________________________ 171

CA3093E
TYPICAL APPLICATIONS

al t.7V RegulatOr supplying CA3093E Transistors plus an externa'

b) 14V Regulator for 01. 02. 03

c) B.8V Temp.-Compensated Shunt Regulator

load.

r ___ E!-!..09,!E _ _ _ -,

I
I
I

I

-I'UfllREG;o--'VV~+----------_....J
01

:

"_..J
Sample Computation for Determining Permissible Zener Dissipation
at +25°C.
CA3093E Ratings at TA ., +2SoC
Total Diu. Max '" 750 mW (Derate@6.67mWtC above 25°C)

Each Zener Oiss. Max .. 250 mW

Typical line Regulation

Typical Load Regulation
forlL-Ot025mA

Typical Temperature Characteri$tic@R L = 330n

.6.EL/EL x 100"-6%
(no load to full load!

.o.EL/E L

Max, Zener Current .. 35 rnA

(lZ1 + IZ21 max ..

4~~W

x 100 •

1;

0.OO7%1"C

~T

Assume CA3093E Transistor/Diode Load Dissipation .. 350 mW then
max. tOlal Zener Diu... (PZ, + PZ2) = 750·350 .. 400 mW

TVPical Temperature Characteristic

.. 57 rnA

'L '" 0 to 40 rnA

Typical Loed Regulation

(AEL/EL! II 100=-3% (no load to fuilioadl
Typical Lina RegulatiOfi at RL =·330n
aELfEL

INote; Max. current rating on each Zener is 35 mAl

.o.E unreg.

dl Temp.-Compensated Series Voltlllle Regulator

x l00"! 0.55%fV

el Off· Line 7V Regulator
orr· LINE

Tv REGULATOR
PART

''0'

RECT

"

rlC'ZW

RZ
620Mr",

CA3~93(
r-l

1

I,
1
rOOJVIO

I

-

0.4

5

mV

-

7

mV

-

1

8

mV

TA

-

0.02

0.2

JlA

TA

-

-

0.3

JlA

-

0.2

0.50

JlA

-

-

0.70

JlA

TA

= 25 0 C

TA

= 0 to 70 0 C

Change in VIO
Between I ABC

= 100 JlA

Fig. 1 - Schematic di~gram of CA3094.

and IABC = 5 JlA

= 25 0 C
= 0 to 70 0 C
TA = 25 0 C
II
TA = 0 to 70 0 C

Input Offset Current

110

Input Bias Current
Device Dissipation

PD

lout = 0

Common·Mode Rejection Ratio CMRR
V+ = 30 V
VICR

10

12

mW

110

dB

27

28.8

-

SUPPLY VOLTS:'" -+15, "'-'-15

0.5

-

V

+12

+13.8

-

V

V- = 15 V

-14 -14.5

-

V

-

MHz

1.0

TYPICAL CHARACTERISTICS CURVES

V

V+ = 15 V

Common·Mode InputVoltage Range

High
low

8
70

IC = 7.5 rnA
Unity Gain·Bandwidth

VCE = 15 V

-

30

·,;~t-tt~-r-rtH-i-i-H+-+-tt~

IC = 7.5 rnA

Open' loop Bandwidth

-

4

-

PD = 220 mW

-

0.4

-

PD = 600 mW

-

1.4

-

-

0.68

-

BWOl VCE=15V

At -3 dB Point

0.1

kHz

IABC = 500 JlA
Total Harmonic Distortion
(Class A Operation)

THD

Amplifier Bias Voltage

VABC
(Terminal (No.5 to Terminal No.4)

b.VIOjb.T
Temperature Coefficient

Power·Supply Rejection

b.Vlojb.V
f = 10 Hz

1/F Noise Voltage

1/F Noise Current

EN

IABC = 50JlA
f

IN

Differential Input Resistance

RI

Differential I nput Capacitance

C,

= 10 Hz

IABC = 50 JlA
IABC = 20JlA
f

= 1 MHz

V+=30V

-

4

-

-

15

150

-

18

-

1.8

-

...

,."

I
,~"

I
10
100
AMPLIFIER BIAS MICROAMPERES ~ hecl

1000

Fig.2 - Input offset voltage vs. amplifier bias
current (lASe; terminaf No.5).

V

,

...-:

. ; 10 2

JlV /oC
JlV;V

T/vjJHi

.
~

~

...-:
,

'0

',,,-.

__

;.£ -

~

,,
0.'

-

,

%

."

Input Offset Voltage

~

., J

IABC = 500 JlA

.~'J.r:..

~c

.'

.\'J..,z.,

-

JL

,

pAWz
0,01

0.50

-

1

-

Mn

2.6

-

pF

2
46'
468
I
10
100
1000
AMPLIFIER BIAS "'ICAQAMPERES (IA~Ris_17~19

Fig.3 - Input offset current vs. amplifier bias
current (lASO terminal No.5).

174 __________________________________________________________________

CA3094, CA3094A, CA3094B Types
TYPICAL CHARACT.ERISTICS CURVES
(Cont'd)

ELECTRICAL CHARACTERISTICS It TA • 26°C For Equipment Design
TEST CONDITIONS

LIMITS

Single Supply v+ =30 V
Dual Supply v+ a 15 V.
V- = 15 V

CHARACTERISTIC

Min,

Typ,

10: SUPPLY VOLTS:V

Max,

·+III.V~hlll

UNITS

IABC = 100!J.A
Unless Otherwise
Specified
OUTPUT PARAMETERS (Differential Input Voltage = 1 V)
Peak Output Voltage:
(Terminal No, 6)
V+OM
With 013 "ON"
With 013 "OFF" V-OM
Peak Output Voltage:
(Terminal No.6)
V+OM
Positive
V-OM
Negative
Peak Output Voltage:
(Terminal No.8)
V+OM
With 013 "ON"
With 013 "OFF" V-OM
Peak Output Voltage:
(Terminal No.8)
V+OM
Positive
V-OM
Negative
Collector·to·Emitter
Saturation Voltage
(Terminal No.8) VCE(sat)
Output Leakage Current
(Terminal No.6 to
Terminal No.4)
Composite Small·Signal
Current Transfer Ratio (Beta)
(d12 and 013)
hfe
Output Capacitance:
Terminal No.6
Co
Terminal No. B

0.,

V+ = 30 V

4 II

RL = 2 kn to ground

26

-

27
0.01

V+ = +15 V, V- = -15 V
RL

= 2 kH to

-15 V

+11

V+

= 30 V

RL

= 2 kn to

+12
-14.99

0.05
0.5
-14.95

V
V

-

V
V

-

+14.99
14.96

-

V
V

V+ - 30 V
IC = 50 rnA
Terminal No.6 grounded I

-

0.17

0.80

V

V+

-

29.95

30 V

-

V+ = 15 V, V- = - 15 V
RL=2knto+15V

+14.95

30 V

V+ = 30 V
VCE = 5 V
IC = 50 rnA
f = 1 MHz
All Remaining
Terminals Tied to
Terminal NO.4

,

4,.

0111'4 I
10
100
AMPLIFIER BIAS MICROAMPERES t lABel

lOCO

FigA - Input bias current vs. amplifier bias
current (lASe. terminal No.5),

V
V

29.99
0.040

=

.
0.1

468

0.1

I
AMPLIFIER BIAS

4681

10

100

1000

CURRE~TUAecl-f'A

Fig.S - Device dissipation vs. amplifier biss
current (lASe. terminal No.5).

2

10

!J.A
H+l+25.C~

+125.C':;~

16,000

100,000

-

-

5.5
17

-

pF
pF

20,000

100,000

-

V/V

86

100

-

dB

1650

2200

2750

IABC= 500 !J.A
RL= a n

-

500
50

-

IABC = 500!J.A
RL =2 kn

-

0.7

-

I

TRANSFER PARAMETERS

Voltage Gain

A

Forward Transconductance
gm
To Terminal No.1
Slew Rate:
Open Loop:
Positive Slope
Negative Slope
Unity Gain
(Non·lnverting.
Compensated)

V+ = 30 V
IABC = 100 !J. A
i1V ou t = 20 V
RL = 2 kH

-

a

4 II
I
10
100
AMPL.IFIER BIAS CURRENT (1'48cl-,..4

2:

4 I.
1000

Fig.6 - Amplifier supply current vs. amplifier
bias current (lASe. terminal No.5).

!J.mhos

V/!J.s
V/us
V/!J.s

i

."F-+-+-I+I--l-I-+-I-l--+--++l+-+-+++I

13.!5~.j....j...H-+--l-l-I-l-I-l-I--l--l-l.j...+-+l+I

i
8-14,51-.l-.!-I~-I-II-++I--+--++l.t.::.'·:£!!··!!.-1-JJ
II
2

-4611

Z

4

'IS

2

4

,.

t
to
100
AMPLIFIER BIAS CURRENTIlABCI-,..A

Z

468

lOCO

Fig. 7 - Common mode input voltage vs. amplifier
bias current (lABe, terminal No.5).

__________________________________________________________________ 175

CA3094, CA3094A, CA3094B Types
~

..

I~' ~ ~:T~~l;;~~~"-I'\I

SUPPLY VOlTAGlI\I·I·.I5V.IV~I·-15V
SOUItCE RESlsrAHc£ IRS'oOO

~

~
~
~

~

i

,

r IO.~ ~""

i

."
i I:~
~

.

i:;

20

.

'0

..

~,

8' 102

FREOUENCY

(f

:~

,

It"

=

'0

II
".41, ClIIt:

r'·'·'(~1 ·500......

l-

..,

00••

.

• '0

",'

COLLECTOR CURRENT IIclomA

Fig. 10 - Collector·emitter saturation voltage
vs. collector current of output tran·
sistor Q13.

Fig.9 - IIF Noise current VI. frequency,

Fig.S - IIF Noise voltage vs. frequency.

COLLECTOR-TO'EM'TTER VOLTAGE IVe£'-IOV
AMBIENT TEMPERATURE It... '025·C

FORCED BETA 010

FAEOUENCl'lfl-KI

)-HI

SUPPLY VOt.TAG[ 1\I+'-20V

~QOIJIJt

AMBIENT TEMP(R ...TUft[ CT... ).iI!'~
f'OIIt TEST CIItCUIT, HE FIG. 21

4

AMlI[NT TEMptRATUR[ 11,'025·C
fOIl TEST CIRelllt, SEE FIG. 21

,

=

.

10 15 SUPPLYVOLTS:V+'+15,V-'-I'

~IO.2
j :

,

~

! !OJ. '

I:

2
4 ••
Z
4.'
I
10
100
1000
AMPLifiER 91AS IIIIICROAMPEI'IES I IA8C;2CS_lun

.",

'0
COlLECTOR ..'lL..... P[JI[S Ilel-IIIA
.lCS-lOU'

Fig. 11 - Composite de beta vs. collector current

Fig. 12 - Open-loop voltage gain vs. frequency.

Fig. 13 - Forward transconductance vs
amplifier bias current.

of Darlington-connected output transistors (012, °131.

• A"'I,.IFIEIl II ...S CURRENT " ....CI.'oo" ...
" .... IIENT n"PUATUIII£ IT,,1 02'·C
fOil TEST CI!H:UIT 5[E FIG. 24 ~

-tI 1°,'==1____

.i

~-

.... -~
- "-7

- f---

f-+--+-+t-+-:."'-t-t-l-H---- --

~

.--L-~~~~~~,0,-1-~.~.~.~~~~,,-4rt1~~

-t---t--r~--+---t--t--r~--;

0.'
20

AMPLifiER lIAS CURRENT

11A8cl-.'"

40

eo

to

CLOSED-LOOP VOLTAGE GAIN C"cLI- d8

w

'00

Fig. 14 - Slew rate vs amplifier bias current.

Fig. 15 - Slew rate vs closad·loop voltage gain.

OPERATING CONSIDERATIONS
The "Sink" Output (terminal No.8) and the
"Drive" Output (terminal No.6) of the
CA3094 are not inherently current (or power)
limited. Therefore, if a load is connected
between terminal No.6 and terminal No.4
(V- or ground), it is important to connect a
current-limiting resistor between terminal
8 and terminal No.7 (V+) to protect transistor Q13 under shorted load conditions.
Similarly, if a load is connected between
terminal No.8and terminal No.7, the current·
limiting resistor should be connected be·
tween terminal No.6 and terminal No.4 or
ground. In circuit applications where the
emitter of the output transistor is not con·
nected to the most negative potential in
the system, it is recommended that a 100ohm current·limiting resistor be inserted be·
tween terminal No.7 and the V+ supply.

TEST CIRCUITS
IIF Noise Measurement Circuit
When using the CA3094, A, or B audio amp·
lifier circuits, it is frequently necessary to
consider the noise performance of the de·
vice. Noise measurements are made in the
circuit shown in Fig.21. This circuit is a
30·dB, non·inverting amplifier with emitter·
follower output and phase compensation
from terminal No.2 to groUnd. Source reo
sistors (Rs) are set to o.n or 1 Mn for
E noise and I noise measurements, respec·
tively. These measurements are made at
frequencies of 10, Hz, 100 Hz, and 1 kHz
with a l-Hz measurement bandwidth. Typi·
cal values for 1/f noise at 10 Hz and 50 p.A
IABC are En = 18 nV!JFf1. and IN = 1.8
pA/.jR't-

w

~

~

40

~

CLOSED-LOQP VOLTAGE GAINIACLI-d8

Fig. 16 - Phase compensation capacitance and
resistance vs closed·loop voltage gain.

+>Oy

fOftl'O'llllll'UJ'PLY
AUECTIONTEIT:

(1/VAltYV·'Y-lVOLT1:
TKENlzIVAA"V-I"
.ZVOLTI
EQUATIONS:
ItlV·A'.I£CTIONE90UT~hOUT

...

IlIV-RUECTION£POUT - IzOUT
II'OWER"""'L"AE.lECTIOII

EOUT

l"I.20LOOV~ECTION.
"MAXIMUM IIEAOINOO~

fTEP10RSTEP2

+1'11

nov

Fig. 17 - Input offset voltage and power·supply

rejection test Circuit.

176 ________________________________________________________________

CA3094, CA3094A, CA3094B Types
TEST CIRCUITS (Cant'd)
IOKn

,.n

150

I

~fI

(our

CMRR'I~
[20Ul-[IOUT

----L---t=~-J

I

INPUT VOLTAGE RANGE fOR CNRR'( TO 2.7v
CMRR(daj·20L.OG

I~
[ 20UT- E IOI)T

I

"OISSI"ATION,(vtlIII
[OUT

OFFSET CuRRENT Ios'

{, VOL.TS

Fig;20 - Common-mode range and rejection ratio
test circuit.

Fig. 19 .- Input bias current test circuit.

At.ii>'S

10

Fig. 18 - Input offset current test circuit.

tl5'o'

rABe

j

ooon

lAse
.A

~£I 0----'

-r----I

® 0~
TIME' 1 HR.

Re" 1.5Kil

S2 SET TO R4

* TOPOTENTIOMETER
REQUIRED FOR INITIAL TIME SET
PERMIT DEVICE INTERCONNECTING TIME VARIATION
WITH TEMPERATURE < 0.3 % lOCo

Fig.24 - Slew fate vs. non-inverting unity gain

test circuit.

TYPICAL APPLICATIONS
For Additional Application Information, refer to Application Note ICAN-6048 "Some
Applications of a Programmable Power!
Switch Amplifier IC"_
Design Considerations
The selection of the optimum amplifier bias
current (IABC) depends on 1. The Desired Sensitivity - the higher the

Fig.25 - Phase compensation test circuit.

IABC, the higher the sensitivity - i.e., a
greater·drive current capability at the output for a specific voltage change at
the input.
2. Required I nput Resistance - the lower
the IABC, the higher the input resistance.
If the desired sensitivity and requred input
resistance are not known and are to be experimentally determined, or the anticipated

Fig.26 - Presettable analog timer.

equipment design is sufficiently flexible to
tolerate a wide range of these parameters, it
is recommended that the equipment designer
begin his calculations with an IABC of 100
fJ.A, since the CA3094 is characterized at
this value of amplifier bias current.
The CA3094 is extremely versatile and can
be used in a wide variety of applications.

________________________________________________________________________ 177

CA3094, CA3094A, CA3094B Types
TYPICAL APPLICATIONS (Cont'd)

"

80VTP~

"N

"

1

"N

WHERE

,,"

IN A NON~INVEATIN!,j MODE
AS A FO~LOWER

WHERE EOUT-EIN

:~~T. f I ~I DEPENOS ON THE

*IN SINGLE - ENDED OUTPUT OPERATION, THE CA3094
MAV REQUIRE A PULL UP OR PULL DOWN RESISTOR

CHARACTERISTICS OF ZI AND Z2
to).

(0)

9ZCS-Z0383RI

OR

 II OUTPUT

MA)(, LINE,

t:. "OUT

raJ

6 WITH NO INPUT SIGNAL TERMINAL 8 lOUT PUT) AT + ~6 ~OLTS

-~~r:lt~Le~Tt:~N
IADJUSTA8LE WITH
RTAlpl

;o[,-"o"'u<-'-'-"-IT-"~'~~'-'-IN

~ 100' 0075 % I II

\

GROUND FAULT
SIGNAL 60l-h

"~O-"~"':"'~'N~IT~'A~'~) .100'0_075"1.. VOUT
ILL FROMIT050mA)

Fig.36 - Dual-voltage tracking regulator.

Fig.37 - Ground fault interrupter (GFO and
waveform pertinent to ground fault
detector.

_____________________________________________________________ 179

CA3094, CA3094A, CA3094B Types

,..

o.-o.IN5391

0.01

820a,

~H'
\Hov
STANcaR

NO p·e609

56000

Zf)

~rF~~~~Ar--~~r----+--~J~u.irp~E.~----~

o.

020VAC TOO:6.~riTE~~

FOR STANDARD INPUT: SHORT C2' RI • 2~O ICn
CI s0047"F; REMOVE RZ
FOR CERAMIC CARTRIDGE INPUT: CI=ooo·nJolf
R 1'2 ~ MA, REMOVE JUMPER FROU C2; LEAVE RZ

TYPICAL PERFORMANCE DATA
For 12·W Audio Amplifier Circuit
Power Output fan load, Tone Control set al "Flat'"
Musie lat 5% THO. regulated supply)
Continuous fat 0.2% IMD. 60 Hz & 2 kHz mixed In a 4: 1 raila,
unregulated supply I See Flg:-'B In ICAN·6048.

'5

W

'2

W

Total Harmonic Dlstoratton
O.OS
0.51
40
B3

At 1 W. unregulated supply ..
AI '2 W. unregulated supply ..
Voltage Gain ..
Hum and NOise IBelow continuous Power OUlputl .

250

Input Resistance .
Tone Conlrol Range

%
%

dB
dB
kS!

See Fig. 9 In ICAN·6048

Fig.38 - 12·watt amplifier circuit featuring true complementary-symmetry

output .tage with CA3094 in driver .tage.

180 __________________________________________________________________

CA3095E
Super-Beta Transistor Array

Features
• Two super-beta n-pon transistors - hFE

Differential Cascode Amplifier Plus 3 I ndependent Transistors
RCA·CA309SE is a monolithic array of transistors con·
nected as a super-beta diHerential cascade amplifier with
three independent n-p-n transistors. (Refer to Fig. 1 for
following description.)

• Operation possible at liB down to

The exceptionally high-beta characteristics of Ql and 02,
plus the large signal·voltage swing capability of Q3 and Q4,
make the composite differential cascade amplifier an excel·
lent choice for a broad range of small-signal, high-inputimpedance amplifier applications including low-noise video
amplifiers. This amplifier is also recommended for use in
long·interval timers. oscillators, and long-duration one·shot
applications.

The differential cascade amplifier incorporates two cascade
amplifiers consisting of transistors Q1, 03 and Q2. Q4,
respectively, plus a voltage-limiting circuit, consisting of
diodes 01, 02 and p-n-p transistor 05. Two of these
transistors, 01 and 02, are super-beta types that have an
hFE > 1000 and are capable of operating over a wide current
range of 1 f,lA to 2 rnA. Each of these types comprises the
input section of its respective cascade amplifier. The output
section of each cascode amplifier employs a conventional
n-p-n transistor, 03, 04, respectively. The output signal is
obtained at the collectors of these transistors. See Operating
Considerations for bias considerations of the differential
cascade amplifier.

> 1000

• Voltage-limiting circuitry (01, 02, 051

< 1 nA

• Matched pair (01 and 021 Via'" 5 mV max. at IC '" 100 p.A dc
110 = 20 nA max. at IC '" 100 p.A dc
• Wide current range -

< 1p.A to 2 mA

Independent Transistors:
• hFE;: 300 typo for each transistor

The independent transistors, 06, 07 and 08, are high-voltage
silicon n·p·n conventional types for general use in signal
processing systems in the frequency range from dc through
vhf. Separate terminals for each of these transistors permit
maximum flexibility in circuit design.

• Wide current range -

< 1 p.A to 10 rnA

• Matched general·purpose transistors
• High voltage - VCBO '" 45 V max.

Applications

The CA3095E is supplied in a 16-lead dual-in· line plastic
package and operates over the ambient temperature range of
_55°C to +125°C

Differential Cascode Amplifier:
• Super-beta pre-amplifier for op-amp
• High-impedance dc meter amplifier
• Low-noise video amplifier
• Piezoelectric transducer amplifier

MAXIMUM RATINGS, Absolute-Maximum Values at TA ~ 25°C

Power Dissipation:
Any One Transistor
300
Total Packag~­
Upto25 C .
750
Above 25°C
. derate linearly
6.67
Ambient Temperature Range:
Operating
-55 to +125
Storage
-55 to +150
Lead Temperature (During Solderingl:
At distance not less than 1/J2" (0.79 mml
from case for 10 seconds max ..
+265
Voltage and Current Ratings Apply for Each
Specified Transistor:
Super-Beta Transistors (0 t, 021Collector-to-Base Voltage (VCBO) .
Emitter-to-Base Voltage (VEBOI
Collector-to-Substrate Voltage (VCIQ)'" .
45
Collector Current IICI
50
Base Current (18)
20

rnW
rnW

mW/oC

°c
°c

Conventional N-P-N Transistors (OJ, 04, 06
07,OB)'
Collector-to-Base Voltage (VcsOl .
Collector-to-Emitter Voltage (VCEOI
Emitter-to-Base Voltage (VEBOI ....
Collector-to-Substrate Voltage (VCIQI"'.
Collector Current (lCl
Base Current (I sl
Conventional P-N-P Transistor (051Collector-to-Base Voltage (VCBO)
Collector-to·Emitter Voltage (VCEOI
Limiting Circuit Current (IPin 11)

°c

V
V
V
mA
mA

V

45
35
6
45
50
20

mA

-45
-35
20

rnA

v
V
V
rnA

V

• Long-interval timer
• Long-duration one-shot multivibrator
• Comparator with high-input impedance
• Long-time-constant integrator
• Photocell amplifier
• Low-noise amplifier-for operation from high-source
impedances
Independent Transistors:
• General use in signal processing systems in dc through vhf range

V

* The collector of each transistor is isolated from the substrate by
an integral diode. The substrate must be connected to a voltage
which is more negative than any collector voltage in order to
maintain isolation between transistors and provide normal transistor
action. To avoid undesired coupling between transistors. the
substrate terminal should be maintained at either dc or signal (ac)
ground. A suitable bypass capacitor can be used to establish a signal
ground.

SHADED TRANSISTORS ARE
SUPER BETA TYPES

STATIC CHARACTERISTICS
Fig. 7-Functiond/ didgram.

Test Conditions

Characteristics

Symbol

Test Circuits for Measurement of Super-Beta

Units
Min.

Typ.

Max.

Cascade Amplifier Characteristics

Characteristics Apply for Each Super-Beta Cascode Amplifier Transistor
Pair (01, OJI and 102, Q41. Unless Indicated Otherwise
Collector-Io-Base Breakdown Voltage

V(BRICBO Ie" 10 p.A, IE "0 See Note 1

Emitter·lo·Base Breakdown Voltage
(Applies only to 01 & Q2)

V

Collector-to·Substrate Breakdown Voltage

45

Vs-sor VlO.-S= 10V,Ill '" 100IJA

Collector Cutoff Current

RBE'" 100

hFE

V6~8"

100

Mn

V10_8- 5V
DC Forward-Curre'nt Transfer Ratio

V

I

5V

Ie'" tOOp.A 1000 2000 5000

I IC = 10p.A

Base·ta-Emltter Voltage
(Applies only to 01 & 021

VBE

Ie = 100 p.A,

Saturation Voltage

VS3t

IsarllO" 1 mA,I" - 100pA.
170r19= 100pA

V6~8

nA

1500

IIC'" 1 mA

or V10-S""' 5 V

Fig.2-VfBRJCBO t"eS"fcircuit.

1500
0.50 0.59
0.22

0.68

V

0.7

V

For Cascode Amplifiers as a Differential Matched Pair
Magn!tude of Input-Offset Voltage
Magn!tude of Input-Offset Current
Magn!tude of Input·Offset Voltage Drift
(Temp. CoefU
Magnitude of Input-Offset Current Dflft
(Temp. eoeff'!

1,01
11101
IlIv,ol

Ie = 100p.A
V6 8 = Vl0 .8

rnV
~

5V

t.T

"A

3.3

p.V/'C

0.05

nA/C

1111101

---ziT

Note 1: Terminal No.9 to terminals to and 11 connected or termmal No.7 to terminals Sand 11 connected.

~

20

Fig.3-ICER test circuit

________________________________________________________________ 181

CA3095E
STATIC CHARACTERlmCS lCont'dl

Test Circuits for Measurement of Super-Beta
Cascode Amplifier Characteristics

limits
Units

Symbo'

Min.

Typ.

Ma.,

For Each Convention" n-p-n Transistor (Q3. Q4, 06, Q1, 011
Coliector-to·Base Breakdown Voltage

. VISR,cao Ie'" 10 ",A, Ie ~ 0

45

95

V

Collector-la-Emitter Breakdown Voltage

VIBRICEO Ie = 1 mAo 'S - 0

35

50

V

Emitter-la-Base Breakdown Voltage

V,BRIEBO 'E' lOO.A, 'C' 0

S

8

V

Collector-to-Substrate Breakdown Voltage

VCBRICIO lei = 100",A,la = Ie '" 0

45

95

Collector Cutoff Current

'CEO

VeE = 10 V. 10 - 0

Collector Cutoff Current

'CBO

Ves'" 10V,le-O

L 'C"OmA
DC Forward·Current Transfer Ratio

"FE

I'c"

Vee = 5V

1
Base·to·Emitter Voltage

VBE

Ie = 1 rnA, VeE = 6 V

Collectar-to-Emitter Saturation Volt8ge

VeEfsatl

Ie = 10 rnA, Is· 1 rnA

mA

V
100

nA

10

nA

210
150

300

500

180

'C=IO.A

O.SO 0.S9

-

0.22

0.78

V

0.7

V

Dynamic Characteristics
T. . eoixHtiona

ChafKteristics

Limits

T A -2SoC

Symbol

Min.

Typ.

Units

Mo •.

Chafae'arisla Appty for Each Super·Beta Cascode Amplifier Transistor
Pair (01. 031. Unless Indicated Otherwise

Fig.5-

Gain·Bandwidth Product

'T

Ie'" 100jlA, V6-S '" V10-B '" 5 V,

78

MHz

Noise Voltage (Referred to Inputl

eN

IC =.50",A,1 -10Hz

13

nV/JHi

v.r telt circuit 10, wper-berll ClUl:ode ptJin.

For Differential Amplifier Operation

JHz

Noise Current (Referred to Inputl
Fur Differential Amplifier Operation

IN

Ie "'S",A,'" 10Hz

0.12

Collector·to-Base Capacitance

CeB

VS_7" V10-9" 5 V.le- 0

0.3

pF

Collector·to-Substrate Capacitance

CCIO

VS-5' V'0_5' 5 V, 'S

3.0

pF

=0

-

pAl

For each Conventional Transistor (Q3throUlh OB)

'T

Gain-Bandwidth Product
Noise Voltage (Referred to Input)

EN

IC" 100 ",A. VCE" 5 V

100

IC '" 3 mA, VCE .. 5 V

320

MHz

nWJHz

IC'" 100 ",A. VCE· 5V,f· 10Hz

Noise Current (Referred to Inputl

IN

IC'- 10",A, VCE" 5 v. f .. 10 Hz

O.S

Coliector·lo·Base Capacitance

CCB

Vce • 5 V, Ie • 0

0.4

Coliector·to·Substrate Capacitance

CCIO

Vel" 5 V, Ie '" 0

pAl 1HZ

..

pF

pF

AMIIENT TEMPERATI,II[ ITA)-·C

* Curve plotted 10rICEO characteristic.

Fig.6-CQ/lecror cur·off current w ilmbitmt .
ttHnpB,.ru,. for ,upe,.betll ClllCOdtl
(JIlin.

i"'" tNTTEMP.(TAl·+8'·

i

I-

r
K

I'

i

!~

g

II-

'00

0

-

1:i
l.J

--

>

~0.1I

'!

PIN IO-TO-PIN8VOLTAGE (VICl--al-!lV

~~N~ J:JJ. "."'-.0.. I- i"""

::::t:

~ ...
~

I~

r.t

ei 0.' -I-

. ... . ... ... . ...
100

1000

COL.LECTOR CURRENT IICI-".A

Fig.l-hFE

~

IC fa, each super-t.,. cucode

1Imp/If;'r t"",'lto, 'psI, (Q,. 031."d

102,04/.

10,000

i*0'

0

~

./

Fif.B- VBE

~~
,~

!
•

II
IOQOO

ftC8-205S7

w. Ic for uch ,upe,.t.rs r,.n·

,i,ro, (0' lind 021.

~TI
.....

~""Q4

. ... . ... . ... .
'000
'00
COLLECTOR CURRENT tIc) -,..A

LLlJLLlUJ..L

;~

1-1-

I""'"

10

0'

Ir0.6
.1

,/

+2S·C

-l-

10

ill JJil

fIIN I-TO-PiN I VOLTAGE (Y6-e'. 5V OR

PIN a-TO·PIN I VOLTAGE !Ye.I'.$Y OR
PIN JO-TO-PIN I YOI.TAGE tv _ '.I5V

~g

~V

Of

I

....

I

....

I:

100

'0

....

I

1000

....

'QOOO

COLLECTOR CURRENT IIC)- "A

Fig.9-VCE(s.t} .... lC far uch Rlper-IMt.
CIIscodfl

.".pli~r

tTMIsi'lfN ptJi, (01.

03} IIfJt/ (02, 04J.

182: ____________________________________________________

~

__________

CA3095E
000

'00

·•

'00

~
~

S
~
a

l'
. tr'L
..I !J -2000

I I I I

!

.e"$t,~
1. CU""llt'\' ~te"

IUD"'"

.1

f-

'JOn"

• 0

~j 100 i-~

, all.

1,11

.~

!lOll'
10nA

100

PI'""

;
-,~

;1.1200

"'7. ::::r:=;r.'
'1.10""
•

.00

'loa

~

450llA

....

1/
V

400
0

0.4

1.2

0.8

0.4

1.2
I.'
YOL.TAGE ACROSS 'INS • AltO IIVI_IICIt 'INS toANO I

I.'

VOLTAGE ACROSS PINS 6 AND a !Y6-al OR PINS 10 AHO 8
("10_8 1- 11

0.'

!VIO_II-V
.....IENT TEMPERATURt IT"I-'C

Ff,."-I·V ch.m:rwrl.,ics for tM su".,."',.
cucM'{MIrs.

Fig. 'O-I·V ch""tfriltic. for the IUIMr-bet.
CIJlCodl/Mifl.

,IC."IOIIO

FI,. 12-C/JII«:,or cutIJff currtnf '" .mbt"n
tlmt»rwWrt for rill c""".ntltJIMt
(VCE· 5 V. 10 VI.

".",/,f(J"

I

COLLECTOR·ro·!MITUR

w
VOLTAO! IVcl!l-5V
:400
g

~."'N~ ~..!.~'TU.LT.,) ~~

i
;

...

,/

-i
~

,,/

-75

-50

a

-25

~

!l0

75

100

~

~

Fig. 13-Co/lfctor cutoff current .... ambient
mnptlratu,. for the cOflllMtionsl
tr8mi,ton (Ves - 5 V, 10 V. 76 VI,

~o.e

0.1
1.0
COlLECTOR CURRENT IXcI- mA

Fig. 14-hFE vs.

Ie

.;;:
~

•
Q

!

0
:II

"

••

100

curr,nt

for

the

..

I

~ :·.....
~ ·
I• ··
··

-

t

I'~

il

,OCO

II

'0

I

--

COLLECTOR CURRENT

0.'

. ..

.

,

0.01

2000

'0

I!~.IO ~A

'.'

... . . .. . ...
'00

1000

fREQUENCY 111- HI

10.000

'It'-IOIM

FI,. II-IN ".. ( (or . .ch 'Upltr-b'I1I CMCOtH
.rnpllf;" tr.mi.tlJr {Mlr (01, 031.nd
(02,0"1.

IIcl·!I~A

I'

1000

FREQUENCY (fl-HI

Fig. 19-EN 'Is. f for pch ,u/HIt·bet. cascode
amplifier transistor psir 107, 03) and
(02,Q4J.

•

AMBIENT TEMPERATUR( ITAlo25·C

COLLECTOR CURRENT

100

.

•

,h.

/

.

I

.... lENT TEMPERATURE IT.. loZS'C

,h.

AMBIENT TEMPERATURE IT...I.25·C

II

'00

/'"

.

0.1
I
COLLECTOR CURRENT lIe l-mA

,~

FI,. , l-G.in IMnriwJdth product va coll«f(Jr
curren' for
sup,,-b.I1I c.,CIJd.
fJIIin.

conventional

transistors.

..

0.01

COLLECTOR CUMtNT I%CI-,., ...

12"-20515

Fig. 16-VCE f,stJ as • function 01 collector

10

100

i V
~

10

,

OA

Fi,. '5-VBE'" (unction o( C/Jlltlctor curltlllt
for
convention.1 tr.m/.ton.

U'e:

...... I-

a

I

O.

'0

~= ~o.~~·!~~ ~ ~~~~ li~~o~~i!:VOR
AMBIENT TEMPERATURE ITA ,.

1:;200

COLLECTOR CURRENT Ilel-IIIA

i

for NCh con"."tlOfYI

1

. ..

~

~~

I--

".ns/s,or (06. Ol. OBI.

:t 3OO

0.1

V~

0.7

ffi

-4O-C

. ... . ..• ...

00'

AMIIENT TEMPERATURE IT"I-"C

,. ,

~

r-.....
I""--r-.,

'00

g

C:~~~R~EC:;::R~~U:I!~~~::,:c

I o.

-- .....
I-I

>00

~

0.,

>

...

101>00

~
10
15
Cou.ECTOR-TO·B"SE VOLTAGE 1Vcaol-V

Fig.20-CCB l"$. VCBO for Nch supel'obtlt.
Cll5t:od• •mp/m.r ,r"".i.tor fJIIir (0',
031 lind (02, Q4J.

o

5
10
I'
COl.LECTOA·TO-SuaSfRA,TE VOLT..GE tVcIol-V

F;,.21-CCI III.

VCID faT NCh lUper-beta

CIIlCOd• •mpl/filt ,,.,,.i,,or ".;r (Ot,

031.nd (02, O"J.

__________________________________________________________________ 183

CA3095E
.00

i

COLI.ECTOft-TO-[MITTEN VOLTAGE
AMlIENT TtMP£""TURE ITA'-25-C

COLL£CTOR~TO-£MITTER VOLTAGE IVCEI.~V
AMBIENT TEMPERATURE ITA ,- 25·C

--

,,-

I

~300

~

~

I! V

I

,/

·,
~..
?·

'0,

"D

COLLECTOR CURft£HT (lC'-IO,l&A

~

,

6

•

1.0

2

II

.'0

. ... . ... . ... . ...

'0

COLLECTOR CURRENTIICI-mA

I

,

~

l

'00

'2CS-20H,

'000
'''EQUE"CY Ifl-HI:

10,000

~

o

1.4f-+-f-+-f-+-f-+-I---t------j

~~

1.21r-+-l-+-l-+--l-+-l-+--i
\
I ~ (WITTER-TO-BASE -+-+--+-+--1

i::::

!.u

~o..
::::

:~

*il

IIII1 I II

r"'-

COLLECTOR CURRENT !IC)'iOO J6A

.....
10.

,

I
I

,

tOO

1000

10.000

FREQUENCY iI)-HZ

'2C'-20sn

Fig.24-1N ...s. f for esch conventionsl transistor (06, Q7, DB).

(CES'

.....i--J
! l

O.6P""'-:c-l-+-I-+-t-+-t--t---l
04

G
~:

"" CAPACITANCE

=

I II

· ... ... . ... . ...

0.01

transistors.

al

I II

.

Fig,23-Nalse voItagtt I'f fnquMCY far the
convent/o".1 rf8"sistan.

Fig.22-Gain bandwidth product V,f collector
current for the cOllventiona'

COLLECTOR-YO-EMITTER vaUAOE (VCE)'5 v
AMBIENT TEMPERATIME (TA)·25·C

~ OJ.
u
,

"

100

0

r=

1111 I 1111
I II 1111

~.

/V'

f200

·
; ·
··
~ ,
~ ·
·

!Vetlas ...

.....................

~LECTOfI'TO'BAS[ C"'''CITANC[ iCcel

I
,

I

0.2

,0

iI 1-

.,

6

BIAS VOLTAG£- V

~

7

r-- r--

.

f--

,

'0

BIAS VOLTAGE-V

Fig.25-Coflector·ro·bare and emitter-to-base
CB;McitMictlJ III bias lIoft.fIII for the

Fig.26-CollectoNO-$ubsUate capacitance vs bias voltage
for the conventional transistors.

conventional tranliston.

TYPICAL APPLICATIONS

"
Operating Considerations

Operation Considerations for the Super·Beta Differential
Cascode Amplifier
An internal voltage-limiting network (diodes 01, 02 and
p-n-p transistor 05) incorporated in the differential cascode amplifier, assures that the applied collector-to-emitter
voltage of each super-beta unit is maintained below two
volts. Fig, 27 shows a t\o'pical bias arrangement of the
super·beta differential cascade amplifier.
Bias current for this network must be supplied by an
external source. This bias current can be obtained by
simply connecting a resistor from Pin 11 to the positive
supply 01 the differential amplifier, The return path for
most of the bias current is through the substrate, Pin 5,
rather than through the common emitter, Pin 8, This
arrall'gement provides superior common-mode and powersupply rejection. As a general rule-of-thumb, the current
supplied into Pin 11 should be approximately 0,04 to 0,1
times the value of the quiescent current of Pin 8.

Fig.27-BiaJ .rra"(JtIm~nt far o~rat;on o( the super-bela
difftlreflti., Cliscode smp/ifier,

Fig.2B-Super-bgta Op·Amp with diode drive network.

184 __________________________________________________________________

CA3095E
TYPICAL APPLICATIONS (Cont'd)

l'~

......
,,,,.,

"J:::-~rcrl!)-l
NOTE TOTAl,.

Fig.30-High-input-impedance. Jaw-noise amplifier circuit.

'®---'-----1"'~

Fig.29-SufNjr·beta Op·Amp with resistor drive network.

SUPPl.~

CURR(NT_300,.A

Fig.31- Typical high.input·imfNjd;Jnce dc voltmeter circuit.

OUTPUT

o TO 9ry

Fig.32-Long-deJay monostable multivibrator circuit.

V"'5V

Fig.33-Low input·bias current comparator circuit.

I~

f

§

~
~

~
~

"\

"i~

• 2o-t

I
Fig.34-CA3095E wideblJlld amplifier.

Ii Ilr

\+ 0

'j'.

+."

I

111
j

'

' I:

I,

II

If'

lif

I

"

,1,

II

-

.-

,.

..

RS .20 K

+

-iT
I~'-

~

U

,1.l,Jon ~ l'

4685

1

A-l-A .A,

FREOUENCY (tJ-Ht

Fig.35-Equivafent input noise voltage 'Is. frequency
for circuit of figure 34.

_____________________________________________________________________ 185

CA3096, CA3096A, CA3096C
N-P-N/P-N-P Transistor-Array

Applications:

Five-Independent Transistors: Three n-p-n and Two p-n-p

• DC Amplifiers
• Sense Amplifiers
• Level Shifters

'" Differential Am plifiers

RCA-CA3096CE, CA3096E, and CA3096AE
are general-purpose high-voltage silicon transistor arrays_ Each array consists of five
independent transistors (two p-n-p and three
n-p-n types) on a common substrate, which
has a separate connection. Independent connections for each transistor permit maximum
flexibility in circuit design.

Types CA3096AE, CA3096E, and CA3096CE
are identical, except that the CA3096AE
specifications include parameter matching
and greater stringency in ICBO, ICEO, and
VCE(SAT). The CA3096CE is a relaxed
version of the CA3096E.
The CA3096CE, CA3096E, and CA3096AE
are supplied in 16-lead dual-in-line plastic
packages.

• Timers
• Lamp and Relay Drivers
• Thyristor Firing Circuits
• Temperature-Compensated Amplifiers
• Operational Amplifiers

MAXIMUM RATINGS, Absolute-Maximum Values:

COLLECTOR-TO-EMITTER VOLTAGE, V CEO :
CA3096AE, CA3096E .
CA3096CE .
COLLECTOR-TO·BASE VOLTAGE, V CBO :
CA3096AE, CA3096E .
CA3096CE .
COLLECTOR-TO·SUBSTRATE VOLTAGE, VCIO:
CA3096AE, CA3096E .
CA3096CE .
EMITTER-TO-SUBSTRATE VOLTAGE, VEIO:
CA3096AE, CA3096E .
CA3096CE .
EMITTER-TO·BASE VOLTAGE, V EBO :
CA3096E, CA3096E
CA3096CE .
COLLECTOR CURRENT, 'C (All Typesl
POWER DISSIPA1'0N, Po:
Up to T A = 55 C:
Device (Total)
Each Transistor. . . . .
Above T A =: 55°C derate linearly at
AMBIENT-TEMPERATURE RANGE, T A :
Operating.

EACH

EACH

N-P-N

P-N-P

35
24

-40
-24

V
V

45
30

-40
-24

V
V

45
30

V
V
(i6)SUBSTAATE

6
6
50

750
200
6.67

-40
-24

V
V

-40
-24
-10

V
V
mA

mW
mW

mW/oC

~

Schematic Diagram

CA3096AE, CA3096E, CA3096CE
ESSENTIAL DIFFERENCES
CHARACTERISTIC

-55 to +125°C
-65 to +150oC

Storage
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mml
from case for lOs max.

265°C

Min.

·

,

I 1
I

~I

,

1

I

I I

~IO-I

~

10'2

,

- -1,.,

1Irl

I 111 !
r--1-~-:- H-----t-I

35

24

-40

-24

n-p-n

45

45

30

p-n-p

-40

-40

-24

@

1 mA
n-p-n

150-500

150-500

100-670

p-n-p

20-150

20·150

15-200

40-200

40-200

30-300

---+

'CBO (nAI

~VZ1

'CEO (nAI

p-n-p

Max.

!+ 4j
e.,

n-p-n

40

tOO

100

p-n-p

-40

-100

-100

n-p-n

100

1000

1000

p-n-p

-100

-1000

-1000

VCE(SATI (VI
Max.
p-n-p

0.5

0.7

0.7

-

-

Max.

-lin ~-Hf

IV,ol (mVI

Max.

,

ZENER VOLTAGE IVZ)-V
92C!-20510

Fig. 1 - Base·co-emitter zener characteristic
(n-p·n).

35
-40

hFE@100pA

y
,

n-p-n

p-n-p

V(BRICBO (VI

hFE

· ··
·
· ··
:
··

CA3096AE CA3096E CA3096CE

V(BRICEO (VI

Min.

,u.

ncs- 20308

Fig. 2 - Collectorcut·offcurrent (ICED) asa
function of temperature (n-p-n).

"'0' (pAl

Max.

n-p-n

5

p-n-p

5

n-p-n

0.6

-

-

p-n-p

0.25

-

-

186 ____________________________________________________________________

CA3096, CA3096A, CA3096C
STATIC ELECTRICAL CHARACTERISTICS at T A = 2S"C
For Equipment Design

'0

LIMITS

CHARAC·
TEST
TERISTIC CONDITIONS

CA3096E

CA3096AE

Max. Min. Typ.

Min. Typ.

CA3096CE

UNITS

Max Min. Typ.

Max.

For Each n·p·n Transistor
ICSO

VCS=10V,
IE = 0

-

0.001

40

-

0.001

100

-

0.001

100

nA

ICED

VCE= 10V,
IS = 0

-

0.006

100

-

0.006

1000

-

0.006 1000

nA

V(SRICEO IC= 1 rnA,
IS = 0

35

50

-

35

50

-

24

35

-

V

V(SR)CSO IC= 101lA,
IE = 0

45

100

-

45

100

-

30

SO

-

V

V(SRICIO ICI = 101lA,
IB=IE=O

45

100

-

45

100

-

30

80

-

V

V(SRIEBO IE = 101lA,
IC = 0

q

8

-

6

8

-

6

8

-

V

IZ = 10llA

6

Vz

VCE(SATI IC= lOrnA,
IB= 1 rnA

--- ---r--"
TE/oIPERATURE-"C

7.9

9.8

-

0.24

0.7

-

0.78

0.6

0.69

0.78

0.6

0.69 0.78

390

500

150

390

500

100

390

1.9

-

-

1,9

-

-

1.9

7.9

9.8

-

0.24

0.5

0.6

0.69

150
-

6

6

Fig. 3 - Collector cur-off current (I CBO) as a
function of temperature (n-p-n).

'00
400

IHJ. ,1JJ
~.;;\Te.

\l~E."'W.~=---+2::;·C

1,~...··'
V

7.9

9.8

V

,ooV

0.24

0.7

V

V
200

VBE
hFE

IC= 1 rnA,
VCE = 5 V

ILWBE/llTI IC= 1 rnA,
VCE=5V

V

'00
0

670
-

-

mVlC

-

,

. ..

r---.',

I

--

-

Q,!)

~~I
"f-~

l0

~ 04

~
~

~

J\

II

f\-

02

i

z
;';

.1'--- ~

0'

z

;

0

., ,

,

,I

V

I,,

COLLECTOR CURRENT IIc)-mtt.

liil

10~

I

• f\

.~ ~~'l'b
,..C;

i

41--

,I ,

,I

FREOUENCY(f)-hHt

Fig. 15 - Magnitude of input offset voltage

I

viol as a function of collector
current for p-n-p transistor Q4- Q 8

Fig. 16 - Noise figure as a function of frequencv for n-p-n transistors.

,-

'1"1 ,..~

2-

oor
nCS.20524

II

~ R,..
~

.,......

"

I

I

II I ,

RSOURCE"KD

J6r\,< .
-1'.

61-- -

.~

~ ~~-

0
00'

,

~

i
i

~'
'.

t-.

r-

.. . , , ..

!!

-I

I\

III :;OU"C["OO'O
..'6~<_J
-K~-Ht~r.=r[_·',"nO·_-_-,-_--j-H

--...

..... --

COLLECTOR -TO-EMITTER VOLTAGE (VeE)' 5V

=---t-- VV
1

F~lt~, '_+~t=tl-_-I- t:- +-!+H-H

t

t

400

200--

j

l

~

-~

-

_.

-t
,

~

0.01

2

/

--++Id--......-1'''''I+I+-+-+-I+t

..

.. -

4~

..

,

8 ,

_

..

I;

110.1

Z

IOO'-·-~

H-If-'"r'-t""",,",,_=_l::r::::l-_-t-H

, 8

2

..

68

2

..

1----

-

..

_.

_.-

··f-

0

6 Bjoo

..
&
8 10
2
COLLECTOR CURRENT {Iel-mA

0'

Fig. 19 - Noise figure as a function of frequenc y for n-p-n transistors.

n-p-n transistors.

'0

6

810

Fig. 20 - Gain-bandwidth product as a function
of col/ector current (n-p-nJ.

1000, FREQUENCY 1I}-lkHz

~

r-

'2CS-203U

Fig. 18 -:- Noise as a function of frequency for

,.or--..

1-- r::~

V

FREQUENCY ItJ-KHI

'.'I---+-+---+--j--+-+

r-

f"

ro~A

..

FREQUENCY tfl-I(Hr

/

-.

FREQUENCY If)'1 IoHI

-

COLLECTOR-TO-SUBSTRATE

"1---+_1"-od_+c
_,_",c_,,_,0,c_,_(~.c~

__ _

...............

- f - - --t-f"'......."'_:::.t-_--t-r-.-. --

2.0

"1---1---'--'---'---'-_-+
---1--1-==+-==1===1
EMITTER·TO-BASE
1.0........

CAPACITANCE (CEBI

o.~ --~CTOR-TO.BASE

CAPACITANCE

...

ICcal

I
'0

0.01

0.1
I
COLLECTOR CURRENT I IC l-mA

BIAS VOLTAGE-V

voltage In-p-nl.

..
~~

J

~~
~~

0U

'0

~~

!!

0

;;

-'0

~~

-20

. . .,

,i

,

..
..~~
:3 ~

Fig.

24 -

I"

0

,

201--

~I'~

~

,

~'"

-

...II , ...
0.'

~V

100

ucs-lOln

Fig. 26 - Output admittance as a function of
frequency.

40

~ I kn

IIII

~~~

-~

0.01

RSOURCE

1"-

• -FI"

10
FREQUENCY III-MHI

FREQUENCY (I)- MHI

30

<&~

~ '0

~

'0

Fig. 25 - Input admittance as a function of
frequency.

'°l"lnoon

~?'

:"P,-

. . . • . . ..

0

100

Forward transconductance as a

". ,Jjl
., .~~
.~" rt-,~O.u4

o§c~~

I

"

function of frequency_

'0

~

i"

~ ~O.'
cc

.'~'-'"
..

FRtQUENCYIfI-MHr

,ei
~
P Iv
~

~~1.5

IOO~A

,

I,~

!~ 2 -

-r--~·~

cc

1

II

I",

...

I " • 1 10

"0.1

COLLECTOR CURRENT I Ie )-mA

1i.z.5
EE

~J
~~

20l-t .

..

00'

Fig. 23 - Output resistance as a function of
collector current.

I

COl!0

- .--

0
11"2

.. -

-

-

,0

20

11-12>0

FREQUENCY DEVIATION (l!.I)-IIHl

S2CS -20,.,RI

Fig, 33 - Line-operated level switch using CA3096AE or CA3096E,

Fig. 34 - Frequency comparator characteristics,
V+

Vr':!:

RL

I~6RL

11<0

'0

+VTTffiTI

IF 10' I mA
ANORL'IK.Q
VT' ! 36 mV

VIN

t

-VT

':-00 C,
Fig, 35 - One-minute timer using CA3096AE
and a MOS/FET.

Fig. 36 - CA3096AE small-signal zero·voltage detector having noise immunity,

'0
60
~

I

'0

,.-

-,

--j-

t--

z

~ 40 -

,-

~-

~

"'--:-."
--

r20f-+-+-H+--+,0
•

112C5-20346

"

(SU8STRATE)

6

8 10
'2
• • '100
FREouENCY (II-_HI

2

• • '1000

-

Fig, 37 - Ten-second timer operated form 1.5-volt
supply using CA3096E.

Fig. 38 - Gain-frequency characteristics,

__________________________________________________________________ 191

CA3096,CA3096A, CA3096C

Features:
1. Can be operated with either dual
supply or single supply.
2. Wide-input common-mode range
+5 V to -5 V.
3_ Low bias current:

< 1 /lA.

Fig. 39 - Cascade of differential amplifiers using CA3096AE.

92CS· 22147

CA3096CH
The photographs and dimensions represent a chip
Dimensions in parentheses are in millimeters and

•

are derived from the basic inch dimensions as indicated, Grid graduations are in mils (10- 3 inch).

when it is part of the wafer. When the wafer is cut
into chips, the cleavage angles are 57° instead of

900 with respect to the fac8 of the chip. Therefore.
the isolated chip is actua/lv 7 mils (0_ 71 mm)

larger in both dimensions .

t

192 ______________

~

______________

~

________

~

_____________

CA3097E
Features:

Thyristor/Transistor Array

•

Complete isolation between elements

•

n·p-n transistor - V CEO "" 30 V (min.)
IC'IOOmA (m.x.)

For Military, Commercial, and Industrial Applications
•
RCA-CA3097E"' Thyristor/Transistor Array is a monolithic in-

tegrated circuit that enables circuit designers to further integrate control systems. The CA3097E consists of five independent and completely isolated elements on one chip: an
n-p-n transistor. a p-n·p/n-p-n transistor pair. a zener diode,
a programmable unijunction transistor (PUT), and a sensitivegate silicon controlled rectifier (SeR)'
The CA3097 is supplied in either the 16-tead dual-in-line
plastic package ("E" ~uffixl or the chip version ("H" suffix).
and operates over the full military-temperature range of
-55 to +1250 C,

Includes:
• Uncommitted "-PO" Transistor

•

• Sensitive-Gata Silicon Controlled Rec:tifier

• Programmabfe Unijunction Tranlistor (PUTI
• p-n·p/n·p-n Transistor Pair
• Zener Diode
• Separate Substrate Connection

MAXIMUM RATINGS. Absolute-Maximum Values at TA =25"C

+50 V
Isolation Voltage. any terminal to substrate"
Dissipation. Total Package:
750mW
Up to T A = 55°C .... - .
...... _ ... _. . . .. . . . . . . .. derate linearly at 6.67 mW/oC
Above T A = 55°C ..... .
Ambient Temperature Range:
-55 to +125 0 C
Operating ....... .
-65 to +150oC
Storage .. _ . _ ........................... .
Lead Temperature (During Soldering):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 seconds max .....
Each n-p-n Transistor (03,OS)
The following ratings apply with terminals 6 & 9 connected together.
30V
Collector-ta·Emitter Voltage (VCEO) ...
50 V
Collector-ta-Base Voltage (VCBO) ..
5V
Emitter-to-Base Voltage (VEBO).' _ .
l00mA
Collector Current (lC)
Base Current (IS) . _ .. .
20mA
500mW
~issipation (PO) ..... ,., ..... .
p-n-p Transistor (04)
The following ratings apply with terminals 7 & 8 connected together,
Collector·to-Emitter Voltage (VCEO)' ... , , , . , ............. ' , , ... , , ...... , ....... , .......... .
-40 V
Coliector-to·Base Voltage (VCBO) " .. ,.
. ., ,. , ... , ... , . ' , ,. , . , , , . ' ....... , ... , . , . , .. ,
-50 V
" , , .......... , , . , ... " , ....... , , , , ' , ,
-<10 V
Emitter-to-Base Voltage (VEBO) ....
Collector Current IIcl, , .. , , , , , .. ..
. .. , , , .. , . ' , , . , , ,. , , ................. , ...... , , .
-lamA
Base Current (Ie), ... , .' .. , ...• , • ' ., , . , . , ...•.• ,. , •.•.....•.•.• , ..•.•.•.....•.•.. , •.••.•
-3mA
Dissipation (Pol .......... "..
, , , .... , , , ... , , ,
. , , .. , ......... ,
200mW
p-n-p/n-p-n Transistor Pair (03,041
~issipation (PO' ...... , , , , , , . , .. ,. ., .. , ...... , .. ,"',.....
. ................ .
500mW
Programmable Unijunction Transistor, PUT (01)
Gate-to-Cathode Positive Voltage (V GK)- . , , , , , .. , , ' ........ , , ' ........ , , .... , , , , .. , .
30V
Gate·to-Cathode Negative Voltage IV GKR)' , . , .. , , . , .......... ' , .. , . , .. , . ' • ' . , .... , .. , ....... .
5V
Gate-to-Anode Negative Voltage (V GA' .... , ... , ..... , . , .... , . , .... , ...... , . , ' , .....•.. , .... .
30V
Anode-to-Cathode Voltage IV AK) ... " ' .. , ... , .... ,",., ... " ............ , ...... , .. , ...... .
±30V
DC Anode Current " ..... , ... , ',' , ... , . ' , , , ..... , , . ' ....... , ......... " _ . _ .... _ ... , ...... ,
150mA
Peak Anode Non-Recurrent Forward (On-State) Current flO p.s pulse) ,." .... ,',.,., ..... , ..... ,.,'
2A
Total Average Dissipation, , , , . , , , ... , .. ' , ' .... , . , . , ..... ' . ' . , , ........ , , , . , , , .. .
300mW
Silicon Controlled Rectifier, SeR (02)
Repetitive Peak Reverse Voltage IVRRXM), RGK "" 1 K!'2 .. ,., ..... , .. , .... ,"., .• ,., ....... , .. ,"
30V
Repetitive Peak Off-State Voltage (VORXM). RGK '" 1 kO . " , . , ..... , ........... , . , .... , , ...... ,
30V
DC On-State Current IlTDC)' , , .. , .. , , .. , .. , ....... , . , .... ,. , .. ,. , .. _ .. , , ... , , ... , ....... , '
150mA
Peak Surge INon·Repetitive) On-State Current (10 J-IS pulse) , ......... , ........ , ... , .. , ..... , .... .
2A
Forward Peak Gate Current (lGFMI ' . ' .. , ....... , . , , '. , ... , ....... ,. , .... , ..... , .. , ... , .... .
20mA
Peak Gate-to-Cathode Reverse Voltage (VGRM)' .... , , , ...... ' .......... , ... , .. , ...... , , ... _., ,
5V
Total Average Dissipation ............. , . , , . , .... , , , , ... , ' , . ' .......... , _ , . , . , , ......... , . _
300mW
Zener Diol;le, (Zl)
DC Current Hz) .. , ..... , ........ ' '. ,. , . , .... _., ,. , ... ' .... , , ..... '. , , , ... , .... , .. , ... _.
25mA
Dissipation (POl ., '.' , , ..... , , , , ........... , .. , ... , . , . , ' ... , ' . , , .... _ .... , ....• , . , . , . , .. .
250mW

p-n·p/n·p-n transistor pair - beta
::: 8000 (typ.1 @IC = 10 rnA. individ",al p·n·p, "-p-n,
or transistor pair operation
Programmable unijunction transistor
(PUTI - peak-point current -15 nA
(typ.) at RG • 1 Mil; VAK' ±30 V

• (PUT) Extremely long RC time constants
with low value of external cap.citor
• Sensitive-gate silicon controlled rectifier (SCRI 160 rnA forward current (max.)
•

Zener-diode impedance (Z21 - 150
(typ.) at 10 mA

Applications .•
•

Timers
Light dimmers/motor controls

• OIeiU,ton
• "On.shot" multivibrators
•

Voltage,regulators

•

Comparators, Schmitt triggers

•

Constant-current sources

•
•

AmpUfien
Logic circuits

SCR triggering
• Pulse Circuits

•

"~2-~-~''-n-::-r--:

1-1"'-M!

POT

I
L__

ZI

sua~TRATE

SCR

_

,
_____

_

:

_ __ ...JI

11~IG

3438

Fig. 1 - Sch"matic diagram of CA3097E,

TYPICAL CHARACTERISTICS

~

6 8 I

"

6 8 10

COLLECTOR CURRENT tIcl-mA

Fi(J.2 - &Js".to-mnitt.r saturation '1olta~ 'Is, col/ector currtJnr for
rran,isron 03 & 05.

"-p-"

• One or more of the terminals of each element of the CA3097E is isolated from the substrate by a junction diode. In order to
maintain electrical isolation between elements, the substrate terminal must be connected to a voltage which is no more positive than that of any other terminal. To avoid undesirable coupling between elements, the substrate terminal (terminal 10)
should be maintained at either dc or signal (ac) ground.

.!

"MSIEHT TEMPERATURE IT,,)--C
UCS-21'O)

F/(J.3 - BM.to-.,,-,itt.r voitallfl
03 &

,,,,,siston

as.

V6,

ambient remfH""'''' for

"'P-"

_____________________________________________________________________ 193

CA3097E
TYPICAL CHARACTERISTICS ICONT'D)

ELECTRICAL CHARACTERISTICS
TEST CONOITIONS
Ambient Temperature
ITA)- 25°C
Unless Otherwise Specified

SYMBOL

CHARACTERISTIC

FIG.

UNITS

LIMITS

NO.
Min.

Typ.

-

-

Max.

n·p-n TRANSISTORS 03,05ITERMINALS 6 and 9 CONNECTEO)
COLLECTOR CUTOFF CURRENT

ICBO

VCB = 10 V, IE = 0

COLLECTOR CUTOFF CURRENT

ICEO

VCE= 10V,IB=0

COLLECTOR·TO·EMITTER
BREAKOOWN VOLTAGE

VIBR)CEO

IC = 100~A, IB = 0

COLLECTOR·TCJ.BASE
BREAKDOWN VOLTAGE

VIBR)CBO

IC =

COLLECTOR·TO·SUBSTRATE
BREAKDOWN VOLTAGE

VIBR)CIO

EMITTER·TO·BASE
BREAKDOWN VOLTAGE

VIBR)EBO

-

-

V

50

-

-

V

ICI = 100~A, IB = 0, IE = 0

50

-

-

V

IE = 10~A, IC = 0

5

7.5

10

V

l00~A,

IE = 0

5

-

IS '= lmA

2

-

0.76

-

V

VCE = 3V, IC = 10mA

3

0.65

0.73

0.B5

V

VCE = 3V, IC = lOmA

4

100

130

-

80

120

-

-

-

VCEISAT)

Ie'" 50mA, IS = SmA
Ie-lOrnA, 'B-1 rnA

BASE·TO·EMITTER
SATURATION VOLTAGE

VBEISAT)

Ie

BASE·TO·EMITTER
VOLTAGE

VBE

TRANSFER RATIO

hFE

~A
~A

30

COLLECTOR·TO·EMITTER
SATURATION VOLTAGE

DC FORWARD·CURRENT

1
10

=lOrnA,

VCE - 3V, IC - 50mA

-

0.65

0.10

ICBO

VCB =-10 V. IE = 0

COLLECTOR CUTOFF CURRENT

ICEO

VCE=-10V,IB=0

COLLECTOR· TO· EMITTER
BREAKDOWN VOLTAGE

VIBR)CEO

IC

COLLECTOR·TO·BASE
BREAKDOWN VOLTAGE

=-lOO~A,

-40

IB = 0

IC =-10~A, IE = 0

VIBR)CBO

-50

-

FORCED-CURRENT TRANSFER RATIO IIc/Ial>IO
TERMINALS 6 AND 9 CONNECTED TOGETHER

~ .,
s .,

I

~

I II

~A

-10

~A

-

V

it:,
~

0

g

I

I I

, I

0
0.'

V

I

-J,- -I 1..-:::: ::::.-'»1

AMBIENT TEMPERATURE IT...

0.'

I
I,

'I

---1--'-

f--

fj

I

J II

i"

-1

-

'lCS·Z"04

V

p·n·p TRANSISTOR 041TERMINALS 7 and 8 CONNECTED)
COLLECTOR CUTOFF CURRENT

COLLECTOR CURRENT (lc» mA

Fig.4 - DC forward-current transfer ratio VI. collector current
for n-p-n transistors 03 & 05.

..

7~C

2:5-C

1_ I

.. '.

, i I

II

,

COLLECTOR CURRENTllcl-mA

EMITTER·TO·SUBSTRATE
BREAKDOWN VOLTAGE

VIBR)EIO

lEI = 10~A, IB = 0, IE = 0

-50

-

-

V

EMITTER·TO·BASE
BREAKDOWN VOLTAGE

VIBR)EBO

IE = -10~A,IC = 0

-40

-

-

V

COLLECTOR· TO· EMITTER
SATURATION VOLTAGE

VCEISAT)

IC =-lmA, I B = -100~A

-

-

-0.33

BASE·TO·EMITTER
SATURATION VOLTAGE

VBEISAT)

Ie =-lmA. Is::: -l00J,lA·

7

-

-0.7

-

V

BASE·TO·EMITTER
VOLTAGE

VBE

VCE =-3 V,IC = -l00~A

B

-0.5

-0.6

-0,7

V

DC FORWARD·CURRENT
TRANSFER RATIO

VCE' - 3 V,IC = -lOO~A

hFE

VCE=-3V,IC=-1 mA

6

9

30

60

40

-

Fig.5 - Collector-to-flmitt.r Slltur.tion IIOltBf/8 VS'. colltICtor
for n-pn- transistors 03 & 05.

V

hFE

1 VCE In·p·nl = 3V, IC = 10mA 1 10 1
1 VCE In·p·n) - 3V, IC - 50mA 1 10 1

-

180001

-

1 6500 1

~~~~!~ZSC~~~EDN~ ~~~~i~~:DR~~~E(;~~~B)·,D

~

;

g

-

n·p-n/p-n·p TRANSISTOR PAIR 03,04
DC FORWARD·CURRENT
TRANSFER RATIO

1.
9ZCS-Z"OS

-

~

Q3

~

~~

a:]o.z

rf:.,

r---L-+-tttf
I
r------,;;~BIEN1

-- - -

I E.R~1UIl~,,,

1E."'''

j-P L

~
~

g
0
0.'

,

. ..

, ,

..

'0

COLLECTOR CURRENTlIcl-mA

Fig.6 - CoIllICtor-to-tNflitt8r uturstion voltaf/8 VI. collf!JCtor
CUfflInt for p-n-p trsnslstor 04.

/l U8IENT TEMF'ERATURE (TA"2S·C
DC FORWARD-CURRENT TRANSFER RATIO (hFE"IO

~

._-

o.9f--· --

~

~

~

t

i

0.111-- _._ ..

~.

15 it
:: ~ 0-7f-+-H+f-+-bl4-f-+-j-i--H
~-

*~ o'r-::/p'
COLLECTOR CURREt.T IIcl-mA

COLLECTOR CURRENT (IC"mA

Fig. 7 - Bastl"to-emitter saturation vo/taga v.!. collector
current for p-n-p transistor 04.

Fig.8 - /Jase-ro-emitte( voltage VI, ambient temp~roture for
P'''-P transistor Q4.

Fig.9 - DC forWtlrdcurrenf transfer ratio vs. collector current
for p-n-p transistor 04.

194 __________________________________________________________________

CA3097E
TYPICAL CHARACTERISTICS (CONT'O)

ELECTRICAL CHARACTERISTICS (Cont'd.)
TEST CONDITIONS

FIG.

Ambient Temperature
(TA)' 250 C
Unless Otherwise Specified

NO.

SYMBOL

CHARACTERISTIC

UNITS

LIMITS

Min.

~600a . -

Typ. Max.

PROGRAMMABLE UNIJUNCTION TRANSISTOR (PUn, 0)
VS' 10V, RG
OFFSET VOLTAGE

VT

ANODE·TO·CATHODE
VF

ON·STATE VOLTAGE

0

10kS1

11.223

0.2

Vs - 10V. RG - lMn

IF

=

SOmA

IF

=

lOOmA

VOM

PEAK·POINT CURRENT

Ip

VALLEY·POINT CUR RENT

IV

Anode Supply Voltage = 20V

0.7

0.90

1.5

1

-

13,23

-

10

-

-

0.55

1

0.015

0,15

40

VS' 10V. RG ' 10kS1

14,22 a

-

Vs - 10V, RG - 10kll

17,15

4

16

-

0

0.7

-

Vs - 10V, RG - lMIl

Vs' 10V, RG

~6000

-

12

C ' 0.22pF
PEAK OUTPUT VOLTAGE

0.2

lMIl

-

V

ro-~
V
~2000

V

COLLECTOR CURRENT (IC),.,A

JJA

-

pA

Fig. 10 - DC forward-current transfer ratio vs.. collector current
fOf transistor pair 03, 04.

25

GATE REVERSE CURRENT

IGAO

VS,30V

22c

-

0.02

GATE REVERSE CURRENT

'GKS

~~O~e_'To.Cathode Short, VS.

22d

-

0,2

-

nA

OUTPUT PULSE RISE TIME

I,

Anode-Supply Voltage - 20V

23

-

60

-

m

-

-

2

-

0.90

1.5

33

100

50

-

nA

~:t

t:Jt+

C = 0.22 t./F

SILICON CONTROLLEO RECTIFIER (SCR), 02

t

PEAK OFF·STATE CURRENT'
FORWARD

IOXM

VORXM '" 30V, RGK" lkn

24

REVERSE

IRXM

VRRXM

30V, RGK=-lkn

24

VT

IT - 50 rnA

FORWARD DC VOLTAGE DROP
GATE·TO·SOURCE

'GS

TRIGGER CURRENT

0

lB

T A" 2S DC

26

TA" -55 D C

26

DC GATE·TRIGGER VOLTAGE

VGT

V L '" lOV, RL = lOOn

HOLDING CURRENT

IHO

RGK - lkll

CRITICAL RATE·OF·RISE
dv/dt

OF OFF·STATE VOLTAGE

19

pA

2

~

V

V

20,24

-

1,2

-

mA

25

-

150

-

V/lls

33

-

50

-

m

33

-

10

-

p,

EXPONENTIAL RISE.

0.2

o 0.1

pA

0.55 0.75

-

04

<"
~

Fig. 1 1 - Offset voltage

RGK' lkll, VDRXM ' 30V

GATE·CONTROLLED

'0'

TURN·ON TIME

See Fig. 33

CIRCUIT·COMMUTATED
See Fig. 33

Iq

TURN·OFF TIME

~

~~

ZENER OIODE, ZI
ZENER VOLTAGE

Vz

IZ

=

7,2

21

lOmA

B

ZENER IMPEDANCE

Zz

-

15

ZENER VOLTAGE

(IOVZNZI!IOT IZ'" lOrnA

~

-+{),Q5

TEMPERATURE COEFFICIENT

IOVZ!IOT

-

t4

50

BO

ZENE R· TO·SUBSTRATE

IZ - lOrnA, f - 1kHz

IZ"00pA
V(BRIZIO

BREAKDOWN VOLTAGE

TERM. 5 TO SUBSTRATE

B.B

V
Il

Z5

-

%/DC

mV/DC
V

~

~

I

ambient temperature for 01 (PUT).

AMBIENT TEMPERATURE ITA)'2S'C
GATE-TO-SOURCE VOLTAGE (V5)-IOV
EQUIVALENT GATE RESISTANCE IRG)·I "'0

I

}
~

vs.

"
,

1

,

i

,--_

..

-

--

~rT

I
~

1--

./
0.'

l-

O.6~ 1-0.'

1---

ii
Ii

1
I

i

I

-

I

I

I
" a 100 z

(, 6 1000

ANODE-TO-CATHODE ON-STATE CURRENT (IFI-mA

Fig. 12 - Anode·to-cathode on·stare voltage vs. anode·to-cathode
on·state current for 01 (PUT).
CURVE Ill): AMBIENT TE~PERATURE lTA)-25°C
EQUIVALENT GATE RESISTANCE (RGI-IO Kn
I CURVE (8): EQUIVALENT GATE VOLTAGE (VSI'IQ

AMBIENT TEMPERATURE ITA 1'2S'C
fOR TEST CIRUIT,SE[ FIG 23

r.:n

:;:::.

V::::

l,

EQUIVALENT GATE RESISTANCE

.1.~?I'IO

KO

\f

H:I
C·0.22 ~f,R'2 MQ
FROM 5UPPL Y TO

. ,

H+H~E.

~'lmtttjl:t

fttT!.f+
t'"

nl

°

°

10

C-IOOO pf, R'2 MQ
<-FROM SUPPLY TO

J . .r"f=

fiF

~t-i-~~°i',Ei r r nIT IT

t

20

II
K . I ' •••• '

,I
"o1

I
Iii.

h..',

"O'

,

r,,;';r ..•..•••

.~

" ' ' ' .• ''

11TT?U:" , ' Y
IS

30

20

EOUIV,ALENT GIATE~SOURCE ,VOLTAGE (Vs)-V

ANODE SUPPLY VOLTAGE (VAAl-V

75

-so

25

0

25

50

75

100 125

AMBIENT TEMPERATURE (TA)-OC

Fig. 13 - Peak output vo/rage vs. anode supply voltage for
.01 (PUT).

Fig. 14 - Peak-point current vs. gate-source voltage and ambient
temperature fOf at (PUT).

Fig. 15 - ValleY'point current vs. gate-source voltage for
01 (PUT).

------------------------------------_________________________________ 195

CA3097E
TYPICAL CHARACTERISTICS (CONT'D)

AMBIENT TEMPEFIATURE fTA)·25"C

...

l-t'T

I

t

r

r-

-y

I

-;C '
~

k.l:'
: ::::

1:,,:71:

::::':::!:"''' .. ,

::'::

1':"

I.

::::':":::[7[7:':I.:':':'i:i",,·,,·.,oo,,·
5

10

10 Ii:: .". :::~ jii! i!:i ; :: ::;; =J!W iff! li:l :;;: !jj: ;, ..

15

EQUIVALENT GATE· SOURCE VOLTAGE (VSI-;~S_2191'
Fi~ 16

- Valley-point cummt vs. gatfNource tlo/tags
for
(PUT).

RESIS~Ar~C~~_RL I_lOon

f

-:;06

I:;

+v~~

l!;i 05

,0

Ig
II:

'L

0.4

I~5 "to,~

J-"

t

"
~

.~
-25

II

ti'

t

ffl:
[Ig:

1.-. _.

,

0

"

mY

50

"

m(puTJ.

F'ORWARD DC ON-STATE VOLTAGE (VT)- v

Fig. 18 - ~o;;;~~fC on·state current vs. on·state voltage for

-u

~t

!

J

.

tttl

VG:'~
- :.
13
-50

v

..

75 100 125
AMBIENT TEMPERATURE (TAI--C

Fig. 17 - VafJev-point current vs. ambient temperature for

at

REPETITIVE PEAl( OFF-STATE VOLTAGE (VL )-10

0.7 LOAD

-75 -50 ·25

+
>00

AMBIENT TEMPERATURE (TA l-"C

",
ZENER CURRENT (IZI-rnA

Fig. 19 - Gate-trigger lIolrage vs, ambient temperature for
02 (SeR).

Fig.20 - Typical DC holding current vs. gate·to-cathode
resistance for Q2 (SeR).

Fill.21 - Zener voltage vs. zener current for Zt.

OPERATING CONSIDERATIONS FOR CA3097E

1. Composite p.n-p/n·p-n Transistors OJ, Q4 (See Fig. 3)
To use 03 as an individual n-p·n transistor, join terminals

no. 6 and no. 9 to disable p-n-p transistor 04.
The appropriate terminal connections are then:
Collector ........... terminal 9

Base ..
Emitter ..

. terminal 7
. ... terminal 8

To use 04 as an individual p·n·p transistor, join terminals
no. 7 and no. 8 to disable n·p·n transistor 03.
The appropriate terminal connections are then:
Collector. .
. ..... terminal 7
Base. . .
. ....... terminal 6
Emitter. . .
. terminal 9
To use 03 and 04 as a composite use terminals 6, 7, 8, and
9 as required.
2. Programmable Unijunction Transistor 01 (PUT)
The programmable unijunction transistor is essentially an
anode·gate SCA. The volt-ampere characteristic of the de·
vice is shown in Fig. 22. When an equivalent Thevenin source
(VS. RGl. as shown in Fig. 22. is applied to the gate terminal
the device will be "off" if the anode·voltage is negative with
respect to the gate voltage. Under this condition. any current
flow is exclusively leakage current. When the anode voltage be·
comes more positive than the gate voltage by an increment
equal to the threshold voltage NT = 0.4 V typ.), the device
can turn "on" only if the current available at the anode termi·
nal is greater than the specified peak·point current. The PUT
will then switch through its negative-resistance region to the
"on" state (low anode·to·gate voltage). It should be noted

that Ip is not the maximum current allowed through the
device. but is the current required at the peak of t~e V·I
curve. Ip is typically a very low value of current.
After the PUT has switched to its low·impedance state, the
device will remain "on" if the anode·current (tAl exceeds
the valleY'point current (IV). If IAIV, the
PUT will remain "on". A method for turning the PUT off is
by shunting current away from the anode until IA0
S;;'E I N>4

3
2

12
12

EIN>S
S;;'E IN >4
4;;'E IN >0

o

Fig. 4 .- Resultant output states of the CA3098.
shown in Fig. 3 as a function of various
input signal levels.

Fig. 3 - Basic hysteresis switch (Schmitt trigger).

TYPICAL CHARACTERISTIC CURVES
+4

AMBIENT TEMPERATURE (TA)' 25"C
SUPPLY VOLTAGE ( v+ 1 .12 V
"HIGH" REFERENCE VOLTAGE ("HRI'6V
"LOW' REFERENCE VOLTAGE {"t..RI-av

>e
I

~

§

-j--H-t-t---t--t--H-1

!.3 VIOIHR),>

4Ce-(V~I-J

Unity-Gain
Crossover Frequency, fT

.-

CC' 0, VO' 03 V IP·P)

-

38

MHz

"$110V

'.MHz Open-Loop
Voltage Gain,AOL

Follower Mode
Power Bandwidth, PBW":
20-dB Amplifier

=1 MHz, Cc =0, VO: 10 V IP.P)

36

42

-

AV; 10, Cc.: O. VI;:' 1 V (Pulse)

50

70

-

AV = 1. Cc

-

25

'"

I

Slew Rate, SR:
20-dB Amplifier

~

10 pF, VI' 10 V IPulse)

dB

0.8

1.2

-

-

0.4

-

Open-Loop Differential
Input Impedance, 2,

F = , MHz

-

30

-

Kn

Open· Loop
Output Impedance, Zo

F·l MHz

-

110

-

n

Wideband Noise Voltage Rejerred to Input, eNITatall

BW = 1 MHz, RS = 1

-

8

-

IJVRMS

-

0.6

-

IJs

AV= 10, CC' 0, VO: 18 V (P·PI

19.1

CLOSEO-LOOPGAIN(ACLI-dB

V/lJs

AV= I,CC: 10pF, Vo -18V IP·PI

Follower Mode

10
NONINVERTING GAIN-dB
o
6
INVERTING GAIN-dB

Fig. 5 - Required compensation capacitance vs.
closed·loop gain.

MHz

~~:~E~~S~~~~~;~~~~~~~1'25'C

:::: ::::

LOADCAPACITANC£ICLI'20pF

.:;: :::: ::::

:;:~ ::~:LL

....

:::H/ ::::

i

KU

Settling Time, ts

[TO Within ± 50 mV of 9 V

RL· 2 KH. CL = 20 pF

Output Swing
10

15

20

25

COMPENSATION CAPACITANCE (CC I PINS I TO B -

.. Power Bandwidth "" Slew Rate
1TVO (p·P)

" 300

pF

• Low-frequency dynamic characteristic
Fig. 6 - Slew rate vs. compensation capacitance.

AMBIENT TEMPERATURE ITA)'25"C
SUPPLY VOLTAGE\v',V-)'15V

30 AMDI£NT TEMP£RATUREITA)'25'C
BANDWIOTH \BWI AT 6dB'IMHz

1

~

~~200

.0f----------+--j--t-+---t-.-+--+--H
HEWLETT
PACKARD
VECTOR
IMPEDANCE
METER 4815A

'0
FREQUENCY (I)-MHI

Fig. 7 - Typical open' loop output impedance vs.
frequency.

01
SOURCE RESISTANCE IRsl-n

Fig. 8 - Wideband input noise voltage vs. source
resistance.

2

~

6 P I

4

{;

8 10

l

4

{; 8100

FREQUENCYllj-MHz

Fig. 9 - Typical open-loop differential input
impedance vs. frequency.

_____________________________________________________________________ 207

.~

CA3100 Type.
A,.8IENT TEMPERATUll:E IT"I'U·C

i

i

1 20.~t==rtt~~~~~--~++-+~~~

11"
E

ig

1!S,f-+-+t-Hf-!-+\i-+t+r-

~

i
g

1O'f-+-+t-t-t-:--+-I*f-

IIU

-!

~

g

'0

~

'f-+-+t-Hf-~-+~-H~-

~

!2.5

0.00

!oS

t:7.5

tlO

t12.5

tiS

tI~

tZO

:U.s

SUPPlY VOL.TAG! IY·,\I-)-V

t.s

Fig. 10 - Maximum output voltage swing .....
frequency.

!7.5

tID

t12.$

tl5

'!'17.$·

:!:20

SUPPLY VOlTAGE I,,","-I-V

FREQUENCY Iti-MHI

FIg. I I - Common·mode input voltage rllnge .....
supply voltage.

FIg. 12- Maximum output voltage VI. supply
voltage.

tlO

.

1

1

12.5

~

10

iG 7.5
~

~

5
2.'

,u.s

U

!:1!1
ito tIZ.S t:l5
SUPPLY VOt..TACI( I"·,\I-'-Y

ttl'

SUPPlY VOL.TAGE CY·,V-I-V

Fig. 14 -Input bias current ... supply volt_

Fig. 13 - Su.o.oIy rum."t '" zupply fI(J/tage.

TEST CIRCUITS
y'

",=

WJTH "I,OADAIST
POTENTIOMETl" (Rxl
TO GivE vo.O! 0 •• v.e

fO~·o.l'"
NULL ADJUST
POTtHTIOM[TER

AT f1ItEQUEHC'f'>I IItHI VI.
MEASUAED WITH HPl4Q5A
YIECTOft \fOLTMETP

'to

y-

y-

ncs-2""

FIg. 15 - Open·loop voltage gain te.t circuit

FIg. IS - Slew rate in lOX amplifier telt circuit.

Fig. 17 - Followersiew rate test circuit.

."

.....

ttL' 250Q FOR 10M TEST

Fig. 18 - Wideband input noise voltage test
circuit.

~

Fi(J. 19 - Output voltBge.wlng (VO~' output
current .wing (10M felt CIrcuit

Fig. 20 - Settling time test t?;rcuit.

208 __________________________________________________________________

CA3100 Types
TYPICAL APPLICATIONS

ldB

BANDWIDTH'I~MHI

CLG'20dB

INPUT

~,~

OUTPUT TO

TERMINATED

,on

TRANSMISSION
LINE

DELIVERS FOLLOWING PEAl<
VOLTAGES TO 500 LINE.

-ldB

BA'IDWID"H"'20~HI

TOTAL INPUT NOISE

~

~~~;
:~~:

VOLTAGE REFERRED TO INPUT

",

::<:5~i>VRMS

I
I ~~

5\'
GAIN'20dS

Fig. 22 - 20 dB video line driver.

Fig. 21 - 20 dB video amplifier.

ZERO
ADJUST

200n

INPUT IMPEDANCE

::::!50Kn
TEST

LEADS

'=FULL SCALE

CALIBRATION

ADJuST

Fig. 23 - Fast positive peak detector.

Fig. 24 - 1 MHz meter·driver amplifier.

Chip Dimensions and Pad Layout

The photographs and dimensions represent a chip
when it is part of the wafer. When the wafer is cut

into chips, the cleavage angles are 57° instead of
sao with respect to the face of the chip. Therefore,
the isolated chip is actually 7 mils (0.17 mm) larger
in both dimensions.

Dimensions in paren theses are in millimeters and
are derived from the basic inch dimensions as in·
d,cated. Grid graduations are in mils (10- 3 inch).

CA3100H Chip

__________________________________________________________________ 209

CA3118, CA3146, CA3183 Types
High-Voltage Transistor Arrays
RCA·CA3118AT, CA3118T, CA3146AE, CA3146E, CA·
3183AE, and CA3183E are general-purpose high-yoltage

silicon n·p-n transistor arrays on a common monolithic
substrate.
Types CA3118AT and CA311BT consist of four transistors

with two of the transistors connected in a Darlington con·
figuration. These types are well suited for a wide variety of
applications in low-power systems in the DC through VHF
range. Both types are supplied in a hermetically sealed 12·
lead TO·S type package and operate over the full military
temperature range. (CA311BAT and CA3118T are high·
vottage versions of the popular predecessor type CA30la.

Types CA3146AE and CA3146E consist of five transistors
with two of the transistors connected to form a di' fereiltially·
connected pair. These types are recommended for low· power
applications in the DC through VHF range.

pre

'e

VCEO

Types CA3183AE and CA3183E consist of five high·current

transistors with independent connections for, each transistor.
In addition two of these transistors (01 and Q2) are matched
at low· current (i.e. 1mA) for applications where offset para·
meters are of special importance. A special substrate terminal
is also included for greater flexibility in circuit design.

The types with an "A" suffix are premium versions of their
non·" A" counterparts and feature tighter control of break·
down voltages making them more suitable for higher voltage
applications.
For detaifed application information, see companion Appli·
cation Note, ICAN·5296 "Application of the RCA CA3018
Integrated Circuit Transistor Array."

',0

VCEsat.
at10mA

"FE
atlmA.

male,
V

typo

&VCE"SV

50
40
50
40
50
40

0.33
0,33
0.33
0.33
0.16
0.16

V

typ.

95
95
95
95
75
75

max.
mV
~5
~5
~5
~5
~5

~5

Applications
• General use in signal processing systems in DC through
VHF range
• Custom designed differential amplifiers
- Temperature compansated amplifiers
• Lamp and relay drivers (CA3183AE, E)
• Thyristor firing (CA3183AE, E)

TA Range

V,O
Diff. Pair at lmA

VCBO

TYPE
male.
male.
max.
mW
mA
V
VALUES APPLY FOR EACH TRANSISTOR
CA3118AT
300
50
40
CA3118T
50
30
300
CA3146AE
50
40
300
CA3146E
300
50
30
CA3183AE
50.
75
40
CA31B3E
50.
75
30

Features
• Matched general·purpose transistors
• VBE matched ±'5mV max.
• Operation from DC to 120 MHz (CA3118AT, T;
CA3146AE, E)
• Low-noise figure: 3.2dB typo at 1kHz (CA31 18AT, T;
CA3146AE, E)
• High lC: 75mA rna •. (CA3183AE, E)

0.

IOperatingl

male.

°e

I'A
2
2
2
2
2.5
2.5

-55-+125

1

FQ2,

°',

• Caution on Total Package Power biss;pation: The m8)Cimum total PiCkage dissipation rating for tha CAllIS Series circuits is 450 mW at
tamperatures up to +85 0C, then dlrate linearly It 5 mWOC. Tha maximum total peCkag8 dissipation rating for the CA3146 Ind CA3183
Serlas circuits Is 760 mWat temperatures up to +55 0 C. then derate linearly at 6.67 mWOC.

SUBSTRATE

00

MAXIMUM RATINGS, Absolute-Maximum Values at TA = 25 0 C
Power Dissipation:
Anyone transistor CA3118AT, CA3118T, CA3146AE, CA3146E •.•••.••...•
300
500
CA3183AE, CA3183E . • . . . • . • • • • • . . • . . • . • • . • . . . . •
Total package Upt0850C(CA3118AT,CA3118T) .. , . . . . . . . . . . . . . . . . .
450
Up to 550C (CA3146AE, CA3146E, CA3183AE, CA3183E) . . . . • .
750
Above 850 C (CA3118AT, CA3118T). . . . . . . . . . . . . . . . . . . . derate linearly 5
Above 550 C (CA3146AE, CA3146E,CA3183AE. CA3183E). , . . . . derate linearly 6.67

CA3118AT, CA3118T

mW
mW
mW
mW
mW/oC
mW/oC

Ambient Temperature Range:
Operating -

.. , . • . . . . . • . . , . • • . • . • . . , ••

Storage (all types)

-55 to +125

Lead Temperature (During Soldering):
At distance 1/16 ± 1/32 inch (1.59 ± O.79mm)
from case for 10 seconds max. . ..
The fOUowing ratings apply for each transistor in the device:
COllector-to·Emitter Voltage (VCEO):
CA3118AT, CA3146AE, CA3183AE . . . • • . . • . . . . • • . . . . . . .
CA3118T, CA3146E, CA3183E . . . . . • . . . • . . • . . . • . . . • . .
Collector·to·Base Voltage (VCSO):
CA3118AT, CA3146AE, CA3183AE
CA3118T, CA3146E, CA3183E
CollectoHo·Substrate Voltage (VCIO):CA3118AT, CA3146AE,CA3183AE
CA3118T, CA3146E, CA3183E ..
~mitter-to·Base Voltage (Vesol all types
Collector CurrentCA3118AT, CA3118T, CA3146AE, CA3146E . . . • • . . • . . .
CA3183AE, CA3183E
...........•....••......
Base Current (lB) - CA3183AE, CA3183E

vnnrl
3

-65 to +150

+265

6

7

'9

10

12

13

SUBSTRATE

°c

40

v

30

V

50
40

V

50
40

V
V
V

50
75
20

mA

CA3146AE, CA3146E

V

mA

mA

rlJ \'rtrl'rl'
15

3

4

6

e
0

10

II

13

12

sueSTRATE

• The collector of each transistor is Isolated from the substrate by an integral diode, The substrate
must be connected to a voltage tNhich is more negative than any collector voltage in order to
maintain isolation between transistors and provide normal transistor action. To avoid undesired
coupling between transistors, the substrate terminal should be maintained at either DC or signal (AC) ground. A suitable bypass capacitor can be used to establish a signal ground.

5

CA3183AE, CA3183E

Fig. I - Schematic diagrams of high· voltage arrays.
The CA3146AE and CA3146E are supplied in
the 14-lead dualMin-line plastic package; the
CA3183AE and CA3183E are supplied in the
16-lead dual-in-line plastic package.

210 ________________________________________________

~----------------

CA3118, CA3146, CA3183 Types
COMPARISON OF RELATED PREDECESSOR TYPE WITH TYPES IN THis DATA BULLETIN
DATA

FILE
NO.
CAJOle

338

CA3018A

338

VCEO

veBO
min.

tv~~~

Ie

"1"'C':';"'''O-=m"'A+'':c~"l"'m"'A..-imilx. rnA

CCB

typo pF

15

20

0.23

0.715

50

0.58

15

20
50

0.23
0.33

0.715
0.730

50
50

0.58

0.730

40

CA3118AT

~~:. ~t.

0.37

30

40

50

0.37

15

20

0.23

0.715

50

0.58

CA3146AE

40

0.33

0.730

50

CA3146E

30

50
40

0.730

50

0.37
0.37

CA3118T

0.33
Ic=10mA

341

CA3046

0.33
Ie-SOmA

15

20

CA3183AE

40

CA3183E

30

50
40

481

CA3083

0.4
1.7
1.7

CCI

CE8

typo pF

typo pF

2.8
2.8
2.2
2.2

0 .•

2.8
2.2
2.2

0.6

TYPICAL STATIC CHARACTERISTICS CURVESCA3118 and CA3146 SERIES (cont'd Fig.2 to 12)
BASE CURflENT{lBI'O

/,

0.6
0.7
0.7

Ic=lmA

0.7
0.7

Ic"10mA

0.74
0.75
0.75

100
75
75

STATIC ELECTRICAL CHARACTERISTICS - CA3118 and CA3146 Series
TEST CONDITIONS
CHARACTERISTICS

LIMITS
I-CA_3_1_1,8A_T..,;,,-C_A,3_146A
__E-jlI-CA_3_1_18TT..:.,_C_A_3,.146_E--lUNITS

SYMBOL

Min.

Typ.

Max.

Min.

Typ.

o

Max.

For Each Transistor:

10!

Coilector-lo-Base:
Breakdown Voltage

Collector·to-Emitter
Breakdown Voltage

72

40

72

v

le= lmA,la=O

40

56

30

56

v

ICI - lOpA, IB = 0
Ie = 0

50

72

40

72

v

IC=10$lA,le-"'O

VIBRICEO
VIBRICIO

Collector·to·Substrate
BreakdOwn Voltage

50

VIBRICBO

Emitter-to·Base
VIBRleso

Ie = lOpA. IC = 0

Coliector·Cutoff Current

ICEO

Vce = 10V,IB = 0

Collector'Cutoff Current

ICBO

Vcs" 10V. Ie

Breakdown Voltage

DC Forward,Current
Transfer Ratio

Vce"5V

Base·to·Emitter Voltage

=

Vce =3V.IC" lmA

Collector-to·emitter
Saturation Voltage

IC = lOmA.IB

VCEsat

I

~

AMBIENT TEMPERATURE {TAJ-'C

V>:

TA for any transistor.

I

EMITTER CURRENT IX J.o

v

0

'C""'mA
IC"'0J.lA

"

Fig. 2 - 'CEO

0.002

30

85
(00

0.63

0.73

100

0.002

30

100

0.63

0.73

"A

90

90

lmA

100

85

0.83

0.S3

v

,,.

v

0.33

0.33

2~

50

7~

100

AMBIENt TEMPERAtURE ITAJ-'C

For transistors Q3 and Q4 (D.,ington Configerateonl:
Coliector·Cutoff
Current
DC Forward.Current

CA3" SAT
and
CA3l18T

Transfer Ratio

Fig. 3 - 'COO
'CEO

VCE" lOV, '8"" 0

1--+--------1--+--1---+--+--1--+----1
hFE

only

VeE" SV. IC" 1 mA

l iE" lOrnA

'-'e

VCE=SV

103 to Q4)

Emitter Temperature
Coefficient
For trMlistors Q1

~d

9000

1500

9000

16:~E I

=lmA

1.46

1.46

1.32

1.32

v

Ii;

4.4

~

~

-

Vce =

sv, Ie '" 1mA

0.48

0.48

mV

I ,.
~

Coefficient
Magnitude of VIO

I

IVSE 1 - VSE2) TemperatureCoefficient

Vce '" 5V,
ICl .. IC2 = 1mA
VCE = SV,
IE=1mA

VCE =5V,

0.9

1.0

1.1

0.9

1.0

.....,

II

""-

l.!c

-

II
U

eo

0.01

CA3l1SATand
CA3118T only

Magnitude of Base-to·
Emitter Temperature

1',0'.'1021

eo

... . ... . . ..
-50"

II

40

IVlol

IVBE1" VBE21

Magnitude of
InputOl'set
Current

120

1100

4.4

VCE = SV, Ie = 1 mA

Q2 (AS. Ojff.r.ntial Amplifierl:

Offset Voltage

I

ffi

V

AMBIENT TEMP£RATURE (T AJ"25·C

S

Magnitude of Input

Magnitude of
hFE Ratio

;160

TA for any transistor.

140

Base·to·Emitter

Magnitude of Base·to·

1500

V>:

ccu..ECTOR-TO-D1ITTER VOLtAGE {VCE'"

,

.....

II

I
COLLECTOR CURRENT (IC}-rnA

I.

1.1

Fig. 4-hFEV>: 'C for any transistor, I
1.9

1.9

mV/oC

COLLECTOR-tO-EMITTER VOLTAGE

IVCEJ.~V

0.9

1.1

'Cl·'C2'" 1 rnA

CA3146AE

"d

CA3146E
only

VCE·5V.

0.3

0.3

'C,·'C2""mA
0 .•

0..
0.'

-7'

-so

-2'
0
2S
50
7S
100
AMBIENT TEMPERATURE tTA}--C

125

92C$-l9fi44

Fig. 5 - VOEvs. TA for any transistor.

__________________________________________________________________ 211

CA3118, CA3146, CA3183 Types
DYNAMIC ELECTRICAL CHARACTERISTICS - CA3118 and CA3146 Series

TYPICAL STATIC CHARACTERISTICS CURVESCA3118 and CA3146 SERIES (conl'd Fig.2 10 12)

TEST CONDITIONS
SYM-

CHARACTERISTICS

TA

BOL

250 C

z

CA3118T

CA3118AT

Max.

Typ.

UNITS

CA3146E

CA3146AE
Min.

Typ.

Min.

AMBIENT TEMPERATUREITA'_25°C

Max.

f=lkHz,VCE =5V,

low Frequency Noise Figure

Ie = l00~A. Source
H!Slstance"1 kQ

dB

3.25

S25

Low-Frequency, Smail-Signal
Equillalent·Circuit
CharacteristiCS:
Foward·Current Transfer
R.tIO

f'" 1kHz,
hie

Open-Circuit Output
Impedance

ho ,

Open-eire\... ! Reverse_
Voltage Transfer RatiO

h"

100

100

hf,

Short-Circuit 'nput
lfTfJ)8dence

Vee

=

5V,

le= 1rnA

2.7

3.5

k!1

15.6

15.6

,umho

1.8)(10-4

1.8)(10.4

ro

10

Foward Tnmsf" Admittance

VI,

I nput Admittance

V"

f = lMHz, VeE = 5V,

Output Admittance

V"

Ie"" lrnA

Aeverse Transfer Admittance

0.001+jO.03

mmho

See curve

mmho

Gall"t-Bandwldth Product

IT

Vce

~5V,

500

MH'

Emllter·to·BaseC!lpacilance

C'B

VeB

~

5V, Ie" 0

0.70

0.70

pF

Collector· to-Base Capacitance

CCB

VCB" 5V, IC = 0

0.37

0.37

pF

Collector·to-Substrate
Capacllance

CCI

VCI " 5V, IC "0

2.2

22

pF

SOO

IC = 3mA

300

500

mA

Fig. 6- VCE sat ",.ICforany

O.3+jO.04

See curve

V"

mmho

31·,'.5

31·jl.5
0.35+)0.04

0.OOH,0.03

40

~

COLLECTOR C1.ImENT (Ie' -

AdmittanceCharacteflSlICS:

transistor.
COLLECTOR-TO-EMITTER VOLTAGE (VCEJ o5V

STATIC ELECTRICAL CHARACTERISTICS - CA3183 Series
TEST CONDITIONS
CHARACTERISTICS

SYMBOL

LIMITS
CA3183AE

TA=25 0 C
Min.

For Each

Typ.

UNITS

CA3183E

M;n.

Max.

I

Typ.l Max.
4

Tr~sistor:

II

001

•

01

I

COLLECTOR CUflRENT (Icl -

Collector·IO-Base
Breakdown Voltage
Collector-lo·Em,tter
Breakdown Voltage

VIBRICBO

IC=lDOpA,IE"O

50

40

VtBRICEO

IC-ImA, 'B-O

40

30

50

40

Collector-lo·Substrate
Breakdown Voltage

ICI'-l00,uA,IB=O.
V(BRICIO

Emitter'lo-Base
Breakdown Voltage

V(BRIEBO

Ie" 0

1.7 COLLECTOR-TO-EMITTER VOLTS(VCE}.!j V
At.lBlENT TEMPERATURE (TAI.2~·C

~

ICEO

VCE

Collector,Cutoff Current

ICBO

VCB" IOV, Ie" 0

Transler RatiO

10

10V, IB" 0

VCE" 5V. IC" 50mA

Base-to·Emltter Voltage

VB'

VCE

CollectOr'lo-Emitter
Saluration Voltage

·VC£sat

IC

~

K

3V, IC" IOmA

50mA, 18

~

10

"A
"A

Vce" 3 v, IC" lOrnA
hFE

Fig. 1- hFEVS. IC for Darlington pair (03and04)
for types CA3TT8A T and CA3TI8T.

IE" 500,uA, IC" 0

Collector·Cutoff Current

DC Forward·Current

e.10

mA 92CS-1964~

SmA

40

40

40

0.65

40

0.75

0.85

1.7

3.0

0.65

075

0.85

1.7

30

for Tramittor. Q1 Irtd aliAs. Differential Amplifier):
Absolute InpuIOlfset

0.47

IVlol

Voltage

0.47

II

VCE" 3V, IC = 'mA
0.78

1'101

Current
A IT'IIIIlCimum diSSipation

01

5 transistors

II

150mW" 750mW

IS

25

0.78

2.5

a

10

06 COLLECTOR-TO-EiC!ITTER VOLTAGE (VeE" 5V

COLLECTOR-TO-EMITTER VOLTS (VCEI'5 V

AI>IBIENTTEMPrRATURE(TA)·25°C

/

~07~~-+~~-+~~++--r-~HH

,

11.75

~
~

1.50

vf-'"

0

~

"
::125

0.1

~

~.

6

Fig. 8- VeEvs. lEfor Darlington
pair (03 and 04).

2

~

4

pA

pOSSible for a particular application

COLLECTOR-TO-EMITTER VOLTS (VeEI'S V

~

I

EMITTER MILLIAMPERES lIE)

Absolute Input Offset

~~-+~~-+--~++--r-4+~

~

I

~ 075

o

-75

-75
AMBIENT TEMPERATURE (TAJ-oC

Fig. 9 - VBE VS. TA for Darlington
pair (03 and 04).

nCS-I~11I7RI

-25

'00
~BIENT

TEMPERATURE (TA!_oC

Fig. TO- VlOvs. TAforOTand02.

~~

INPUT OFFSET 'v'OLTAGE=\'lSE\
0 ..

-50

~

g~ as,~+-+++t--~..

II aeuI

4

6

4

IaI

6

I

,

,~

EMITTER MILlIAMPERESIIEJ

Fig. 11- VeEandV/Ovs.IEforOTand02.

212 ____________________________________________________________________

CA3118, CA3146, CA3183 Types
TYPICAL DYNAMIC CHARACTERISTICS CURVES
(FOR ANY TRANSISTOR)-CA3118.CA3146 SERIES (Fig. 13 to 22)

TYPICAL STATIC CHARACTERISTICS CURVESCA3118 and CA3146 SERIES (Fig.2 to 12)

COlLECTOO-lO-EMITTER VOllS (YcE"5'1
SOlflCE RESISTANCE OHMS (Rsl.50Q
A.MBIENT TEMPERATURE IT,v,25'C

"

o~

,~

"'I

(;

BO.!

4

(;

./

,

8 I

,

r--

,

COLLECTOR MILLIAMPERES

,

,

./

~

V

. , . ---, - .
f.!9-

.

,

COLLECTOR MILLIAMPERES IICI

Fig. 14- NFvs.IC@RS=lkn.

1,./v

f...--1

, , 0.'

Ifl-:=-

~~~f:>

r

"
,

COMMON-EMITTER CIRCUIT, BASE INPUT

.~ ~+=~**~~,~~~~~=+~~=t~

i~ ~1-f--+---1-+++-t--H-++-""'-'1"-;:-t~H--+---1

r....

~~

°

V

I

;;:

~

~

Fig. 13- NFvs.IC@RS=500n.

/
1,#1
»,,,,
1"
,.,0 l
. .i?
/
"
vf V1' ,ov
,
~

~
"

1,,4J

~
~~I-v

T"

COLLECTOR MILLIAMPERES (leI

Fig. 12 - 110 VS. Ie (01 and Q2) for types CA3146AE
and CA3146E.

::

./"

,

COLLECTOR MILLlA~PERES lIel

30 COLLE.:::rOR -TO-EMITTER VOLTS (VeE)- ~
SOURCE RESISTANCE OH~S (RS)'IOOOO
AMBIENT TEMPERATURE (TA)'25"C

~

f.c~~a

#

"

2

~

<"

"

0.01

'0

.I~

COLLECTOR-TO-EMITTER VOLTS (VeE).:I V
SOURCE RESISTANCE OHMS (Rsl.IOOO
AMBIENT TEMPERATURE (TAI"2S-C

~12:0~+-~+++-4--I--+++-4-"~~H--I-~

V
/

af IO~+-4-+++-4--+-+++-4--+-rN--I-~
~~
•• 0~+-~~r-~-+-+++-4--+-rH-~~~
'-.!t.
15~

-'"

i~~o'~+-4-++t--r-+-++~~-+-r~7I-~

, ,

4

8 0 .1

6

I

4

Ia

(;

~~_~I--r-+4-++-+~-HH-~~~~~-I--t
10

COLLECTOR MILLIAMPERES llel

IIel

461 1
2
4 6 8 10
2
FREQUENCY {f)-MHz

Fig. 15 - NFvs. IC@RS= IOkn.

Fig. 17 - Y,. vs.

4 6 8 100

2

t

IAMsIENlrTE~PERATGREUIrA):2::I~CIN

u
COLLECTOR-TO-EMITTER VOLTS (VCE)-?'
COLLECTOR MILLIAMPERES(I )-1

00

~~ 5~4--+~4--+~-+++~--+-hH~+4

-.:J

:~ 4~4--+~4--+~-+++~--+-HH~'~"~
:i~

/,

~~ '~4--+~4--+~-+++~--+-hH~~
Zz

8~

g"

~~ 2~4--+~_1_-+~-+++~__~~~+~
• '~+--r++r-+--r++r-~;:~+++-~
,

.

"

o

i! ~~+-~+++-~-+~+--+-+4-H.-+~
-

'"

~I

~J

bOI

4~+-~+++-~-+~+-~-+4-H-~~

i~ 3~+-~+++--r-+~+-~-+4-Hf-t~
~~ 2~+-~+++-~-+~+--+-+4-~-+~

~3
a:
~

'\--+-+H1--f--H-tf--f-./..,f''H*,'f::-1--1

'0

Fig. 18 - Yi. vs.

.....

•

FREaUENCy(fl-~Hl

"00

00

10

FREOIJENCY(fl-MHz

t

Fig. 19 - Yo. vs.

BOO

FREOUENCY(t )-MHz

t

Fig. 20- Yr. vs. f.

I AM'"'' "MPERATURE '

~-+-·~~f-~f-~i~••••*i~.~·
. ·.•+.·4···
.

I

J II···

COLLECTOR MILLIAMPERES IIcl

Fig. 21-lps. 10

BIAS VOLTAGE-V

Fig. 22 - CEO. Cco, CCI vs. bias voltag.

____________________________________________________________________ 213

CA3118, CA3146, CA3183 Types
TYPICAL STATIC CHARACTERISTICS CURVES-CA3183 SERIES
(Fig. 23 to 30)
COLLECTOR-tO-BASE IIOLTAGE (Vca'-1011

COLLECTOR-fO-EMITTER VOLTAGE IVCE'·311

~

75

~
'7

50

i

~ 25

g

-'0

-20

0

2'

100

"

50

AMBIENT TEMPERATVRE 11AI--C

-50

AMBIENT TEMPERATURE ITA'iZ!I"C

~
: 90

J

~ 80
~

I

CO\..\.~~10.

.v

E"I,,!1EI\

I--

~

g

6

60

g

'0

,

. ..

0.7

~ 0.6

~

~ '0

0

·50

0

25

50

75

100

AMBIENT TEMPERATUREITAI--t

Fig. 25 - hFEVS. TA foranytransistor.

...-::;:.
_IE.M"

n:."f'E~A.~ ~r·2~·

. ~-.'

70

;

100

50

0.9

~

"\

1

2'

24 -ICBO "" TA for any transistor.

;0.8

~,.'O
~\.."/l.Gi.\"C

~

Fig.

I

I,

0

AMBIENT TEMPERATURE {TA}-OC

Fig. 23-ICEO "" TA for any transistor.

=
100
0

-2'

i-"""'
,..... ./'

r-

~'i--

~-I-

0.5

!
,

: 0.4

..

1.0
COLLECTOR CURRENT !lel-mA

0.'

to

Fig.26-hFPs.ICforanytransistor.

,
Fig.

. ..

,

. ..

I
COLLECTOR CURRENT {Ic l -

mA

,

10

Fig. 29

I

COLLECTOR CURRENT (lC I-rnA

-I VIOl

COLLECTOR CURRENT tIel -

21- VBEvs.ICforanytransistor.

4 COLLECTOR-TO-EMITTER VOLTAGE ("CE'o, II

0.'

.

n.C~-I'fI'"

vs. I C for differential amplifier (a land 02.'.

mA

Fig. 28- VCE sat vs.lcforanytransistor.

COLLECTOR-lO-EMITTER VOLTAGEI"CE'. 311
AMBIENT TEMPERATURE( TAl- 2'·C

01

I

10

COLLECTOR CURREHT(IC)-mA

Fig. 30-11101 "" Icfor differantial amplifier (Oland 021.

214 ____________________________________________________________________

CA3127E
Features:

High-Frequency N-P-N
Transistor Array

•
•
•
•

For Low·Power Applications at Frequencies up to
500 MHz
RCA·CA3127E* consists of five general·
purpose silicon n·p·n transistors on a common
monolithic substrate. Each of the completely
isolated transistors exhibits low 1If noise and
a value of fT in excess of 1. GHz, making the
CA3127E useful from dc to 500 MHz.
Access is provided to each of the terminals
for the individual transistors and a separate
substrate connection has been provided for
maximum application flexibility. The mono·
lithic construction of the CA3127E provides
close electrical and thermal matching of the
five transistors.
The CA3127E issupplied in a 16·lead dual·in·
line plastic package and operates over the full
military temperature range of -55 to +125"C.
• Formerly RCA Dev. No. TA6206.

MAXIMUM RATINGS,

85 mW

Total Package: 0
For T A up too 75 C

425 mW

For T A> 75 C Derate

linearly at.

6.67 mW/oC

AMBIENT TEMPERATURE RANGE:
°
Operating
. -55. to +125 0 C

. -65 to + 125 C

Storage
LEAD TEMPERATURE
lOURING SOLDERING):

At distance 1/16 ± 1/32 inch

11.59 ± 0.79 mm) from case
for 10 seconds max.
The following ratings apply for each transistor in

the device:
Collector-ta-Emitter Voltage, V CEO .
Collector-ta-Base Voltage, Vcso .
Collector-ta-Substrate Voltage, VCIO*

Ie

20 rnA

A.'''", ,,"""AT'" ",1,,,·,
~
COLLECTOR-TO-EMITTER VOLTAGE IVCE1'l,iV
~
"""""".""on
~~' ~
<~

/"

20

/'

"
~

s

/

'0

~

..........

:==::.

•
•
•
•
•

VHF mixers
I F Converter
I F amplifiers
Synthesizers
Cascade
amplifiers

92CS~22214

Fig. 1 - Schematic diagram of CA3127E.

STATIC ELECTRICAL CHARACTERISTICS at TA = 250 C
CHARACTERISTICS

LIMITS

TEST CONDITIONS

UNITS

/v

Coliector·to·Base
Breakdown VoltaQe

IC = 10 /lA, IE = 0

20

32

-

V

Collector· to· Emitter
Breakdown Voltage

IC=lmA,IB=O

15

24

-

V

Co II ector·to·Substrate
Breakdown Voltage

IC1=10/lA,IB=O,IE=0

20

60

-

V

Emitter·to·Base
Breakdown Voltage"

IE = 10/lA,IC = 0

4

5.7

-

V

Coil ector ·Cutoff·Curren t

VCE=10V,IB=0

-

-

0.5

/lA

Collector·Cutoff·Current

VCB = 10 V, IE = 0

-

-

40

nA

35

88

-

DC Forward·Current
Transfer Ratio

IC = 5 mA
VCE

=6 V

15 V
20 V
20 V

*The collector of each transistor of the CA3127E
is isolated from the substrate by an integral diode.
The substrate (terminal 5) must be connected to
the most negative point in the external circuit to
maintain isolation between transistors and to
provide for normal transistor action.

i
~

• VHF amplifiers
• Multifunction combinationsR FImixer !oscil! ator
• Sense amplifiers
• Synchronous detectors

For Each Transistor:

POWER DISSIPATION, PD:
Anyone transistor.

JO

App!ications:

Min. Typ. Max.

Absolute·Maximum Values:

Collector Current,

Gain·Bandwidth Product (fT) > 1 GHz
Power Gain = 30 dB (typ.) at 100 MHz
Noise Figure = 3.5 dB (typ.) at 100 MHz
Five independent transistors on a common substrate

~

~

Base·to·Emitter Voltage

Coil ector -to· Emitter
Saturation Voltage
Magnitude of Difference
in VBE
Magnitude of Difference
in IB

VCE = 6 V

IC= 1 mA

40

90

IC =0.1 mA

35

85

IC = 5 mA

.0.71 0.81 0.91

IC= 1 mA

0.66 0.76 0.86

IC=O.1 mA

0.60 0.70 0.80

V

IC = 10 mA, IB = 1 mA

-

01 & 02 Matched

-

0.5

5

mV

VCE = 6 V, IC = 1 mA

-

0.2

3

/lA

0.26 0.50

V

·When used as a zener for reference voltage, the device must not be subjected to more than 0.1 millijoule of
energy from any possible capacitance or electrostatic discharge in order to prevent degradation of the
junction. Maximum operating zener current should be less than 10 rnA..

~~
.,
-fj-"y..\

_/

°

10011.1'11

COLLECTOR CURRENT UC1-mA

Fig. 2 - 1If noise figure as a function of collector
current at RSOURCE::::: 500 n.

__________________________________________________________________ 215

CA3127E
DYNAMIC CHARACTERISTICS at T A = 25°C
CHARACTERISTICS

LIMITS

TEST CONDITIONS

UNITS

Min. Typ. Max.
IIF Noise Figure

f= 100kHz, RS= 500n, IC= 1 mA

-

1.8
1.15

-

GHz

See

-

pF

Collector·to·Base
Capacitance

VCB = 6 V, f = 1 MHz

Collector·to·Substrate
Capacitance

VCI = 6 V, f = 1 MHz

-

Fig.

-

pF

Emitter·to·Base
Capacitance

VBE = 4 V, f = 1 MHz

-

5

-

pF

Voltage Gain

VCE=6V,f= 10MHz
RL = 1 kn, IC = 1 mA

-

28

-

dB

Power Gain

Cascode Configuration
f= 100 MHz, V+= 12 V

27

30

-

dB

3.5

-

dB

Noise Figure

IC=l mA

Input Resistance

Common·Emitter

-

Input Capacitance

VCE = 6 V

Output Capacitance

IC=l mA

-

Magnitude of forward
Transadmittance

f = 200 MHz

-

Output Resistance

Configuration

400
4.6

24

3.7

a.'

COl..L£CTOR CURRENT IIC1-mA

Fig. 3 - 1H noise figure as a function of collector
current at RSOURCE = I HI.

n
kn
pF

-

2

'ol---+-++,"",-+-I-"A'l--I--l

dB

-

Gain·Bandwidth Product VCE = 6 V, IC = 5 mA

pF
mmho
Fig. 4 - Gain-bandwidth product as a function of

collector current.

,
i

0.9

~

...
~
~

-

0.7

~ ...
~

= ...
~

0.'

J.

l.l~ ,,J...~

r-~~'"

--

+--

--- -

...c

~

-~

CajIKitencelpFJ

-

. . .. . .

cc.

v._... ....

T•• nllnor

a,
a,
a3
a.

.,

'"

COLLU:TOR CURAENTIIcI-MA

Fig. 5 - Base-to-emitter voltage as a function of

Fig. 6(al - Capacitance as a function of bias
voltage for 0;2-

col/ector current.

5

~

i

Ql;;:,....

......I

~ '0
~

i

,:;-....

.0

'0

I
I

~

t--

oil

Fig. 7 - Voltage gain as a function of frequency
at RL = lOOn.

6 '10

"".

Totlll

....

Ce,

c"

6V

10tii

oY

"".
-

0.190 0.090 0.125 0.366

0.610 0.415

1.0;

0.170 0.225 D.2&; 0.130

0,360 0.085

'.200 0.215 0.240 0.360

0.625 0.210

1."
1.40

0 ....

0.190 0.225 0.270 0.3m

0.6'0 0.085

1.25

0.010

D.HD 0.095 0.115 0.140

0,31ii 0.090

O.o!5

100 .... alENT T£MPER..TUR£IT,l_2S-C
COlL£CTOR-TO-£IIIITttR VOLTAG£ 1"e£I-ev

"I---~P
.0

701--+--+--+-++--+----jf-.-+-+-I

, 601---1--1-+-f-+-+--+-+-+l

if

ool--+--+-I-++--+--I-+-+-I

u

FREQUENCY UJ- Mtj,z

Totll

Fig. 6(bl - Tvpical capacitance values at f = I MHz.
Three terminal measurement. Guard
all terminals except those under test.

~

.i .

0.025

Ce.

'"

6 '100

2

'"

'1'1000

FREOUENCY Ifl-III",

Fig. 8 - Voltage gain as a function of frequency
atRL = I HI.

a

"

0.'

.. ,

COLLECTOR CURRENT1ICI-m"

. '"

Fig. 9 - DC forward-current tran.sfer ratio as a
function of collector current.

216 ________~-----------------------------------------------------

CA3127E

,
FREQUENCVllj-NHI

T' '1000
FREQUlHCV(lJ-MHI

COLLECTOR CURRENT (le)-rnA

Fig. 10 - Input admittance (Y ,,) as a function of
frequency.

Fig. 11 - Input admittance (Y 11) as a function of
collector current.

Fig. 12 - Output admittance (Y22) as a function of
frequency.
AMBIENT TEMPERATURE(TA)'25"C
CQLLECT().R-TO-EMITTER VOLTACiE (Vcr)'GV
COLLECTOR CURRENT\!C)'lrnA

,,
1

g

T

8 '1000

FAECUENCY(fl-MHI
COLLECTOR CURRENT(!C)-mA

COLLECTOR CURRENT(!C)-rnA

Fig. 13 - Output admittance (Y22) as a function of
collector current.

Fig. 14 - Forward transadmittance (Y 21) as a
function of collector current.

Fig. 15 - Forward transadmittance (Y21' as a
function of frequency.

'"""

7

e

91000

•

FREOUENCV(fl-MHr

COLLECTORCURRENT(ICHrnA

Fig. 16 - Reverse transadmittance (Y 12) as a
function of collector current.

Fig. 17 - Reverse transadmittance (Y 12) as a
function of frequency.

Fig. 18 - Voltage-gain test circuit using currentmirror biasing for 02'

1!i'Bp,vo

1000 TEST
£!.. POINT

I

I
I
,I

This circuit was chosen because it conveniently
represents a close approximation in performance to
a properly unilateralized single transistor of this
type. The use of 03 in a current-mirror configuration facilitates simplified biasing. The use of the
cascade circuit in no way implies that the transistors cannot be used individually.

~I

I

IO~~

.J

I

~

I*
-l

E , JOHNSON Ng 160-104-1
OREQUIVALE",T

Fig. 20 - Block diagrams of power·gain and noiseFig. 19 - 100-MHz power-gain and noise-figure test circuit.

figure test set-ups.

217

CA3130, CA3130A, CA3130B Types

BiMOS
Operational Amplifiers

Features:

• MOS/FET input stage provides:
very high ZI = 1_5 Tn 11_5 x 10 12 nl typ_
very low II = 5 pA typo at 15-V operation
With MOS/FET Input, COS/MOS Output
2 pA typo at 5-V operation
• Common-mode input-voltage range includes
RCA-CA3130T, CA3130E, CA313OS, CAnegative supply rail; input terminals can
3130AT ,CA3130AS,CA3130AE,CA3130BT,
Ideal for
and CA3130BS are integrated-circuit operbe swung 0_5 V below negative supply rail ( single-supply
ational amplifiers that combine the advanapplications
• COS/MOS output stage permits signal swing
tages of both COS/MOS and bipolar tranto either (or both I supply rai Is
sistors on a monolithic chip_
• Low VIO: 2 mV max_ (CA3130BI
Gate-protected p-channel MOS/FET (PMOS)
• Wide BW: 15 MHz typ_ (unity-gain crossoved
transistors are used in the input circuit to
• High SR: 10 Vllls typo (unity-gain follower)
provide very-high-input impedance, very-Iowrequiring offset-null capability. Terminal pro- • High output current 1101: 20 mA typo
input current, and exceptional speed pervisions
are
also
made
to
permit
strobing
of
formance_ The use of PMOS field-effect
• High AOL: 320,000 (110 dBI typo
the output stage.
transistors in the input stage results in
• Compensation with single external capacitor
common-mode input-voltage capability down
The CA3130 Series is supplied in standard
Applications:
to 0.5 volt below the negative-supply tera-lead TO-5 style packages (T suffix), a-lead
minal, an important attribute in single-supply
• Ground-referenced single-supply amplifiers
dual-in-line formed lead TO-5 style "DI Lapplications.
CAN" packages (S suffix)_ The CA3130 is
• Fast sample-hold amplifiers
available in chip form (H suffix). The
A complementary-symmetry MOS (COS!
• Long-duration timers/monostables
CA3130 and CA3130A are also available
MOS) transistor-pair, capable of swinging the
• High-input-impedance comparators
in the Mini-DI P a-lead dual-in-line plastic
output voltage to within 10' millivolts of
(ideal interface with digital COSIMOSI
package (E suffix)_ All types operate over
either supply-voltage terminal (at very high
• High-input-impedance wideband amplifiers
the full military-temperature range of -55 0 C
values of load impedance). is employed as
to +125 0 C_ The CA3130B is intended
• Voltage followers
the output circuit.
for applications requiring premium-grade
(e.g_, follower for single-supply 01 A
specifications and with limits established
The CA3130 Series circuits operate at supply
converterl
for: input current, temperature coefficient
voltages ranging from 5 to 16 volts, or ±2_5
• Voltage regulators
of input-offset Voltage, and gain over the
to ±a volts when using split supplies. They
(permits control of output voltage
can be phase compensated with a single exrange of -55 0 C to +1250 C. The CA3130A
offers superior input characteristics over
ternal capacitor, and have terminals for
down to zero volts I
adjustment of offset voltage for applications
those of the CA3130.
• Peak detectors
• Single-supply full-wave precision rectifiers
r------, , - - - - - - - - - ,
• Photo-diode sensor amplifiers
I BIAS CIRCUIT
I I CURRENT SOURCE FOR Q6 AND 07 I
I

I
I

I
I
I
I
I
I

I
I

ZI
B.3V

Q'

RI
40Ul

I I
I I

R2

L ___ -=~
NON-tNV.
INPUT

I I
II I SECOND

r-I4-~""'---,.*~h II II

STAGE

TOP VIEW

Sand T Suffixes

II
I I
n-~-----1----+---~1 I

II
II

OF.fut~T88 'TI OI (

QII

tNV. INPUT 2

-

NON.
INV. INPUT 3

V-

7

v+

6 OUTPUT

4

5

O~~~fT

TOP VIEW
NOTE:
ClODES 05 THROUGH 08 PROVIDE GATE-OXIDE PROTECTION

FOR MOS/FET INPUT STAGE.

E Suffix

92CM-24714RI

Fig. 2 - Functional diagrams for the CA3130 series.

Fig. T - Schematic diagram of the CA3130 Serie•.

218 ________________________________________

~

__________

~------------

CA3130, CA3130A, CA3130B Types
rc. .3i'O---------------------,

MAXIMUM RATINGS, Absolute-Maximum Values
DC SUPPLY VOLTAGE
(Between V+ and V- Terminalsl . . . . . . .. 16 V
DIFFERENTIAL-MODE
INPUTVOLTAGE ................. _ ±8V
COMMON-MODE DC
INPUT VOLTAGE ... (V+ +8 VI to (V- -0.5 VI
INPUT-TERMINAL CURRENT ......... 1 mA
DEVICE DISSIPATION:
WITHOUT HEAT SINK UP TO 55 0 C .. . . . . . . . . . . . . . . . .. 630 mW
ABOVE 55 0 C .... Derate linearly 6.67 mWf'C
WITH HEAT SINKAT 1250 C ......... _ . • . . . . . . . .. 418 mW
BELOW 1250 C
. Derate linearly 16.7 mW/oC

I

v+
1

I

2001'.1.

I

TEMPERATURE RANGE:
OPERATI NG (all typesl • . • .. -55 to + 12SoC
STORAGE (all typesl ..•.••.. -55 to + 150?C
OUTPUT SHORT-CIRCUIT
DURATION ~ . . . . . . . . . . . .
INDEFINITE
LEAD TEMPERATURE
(DURING SOLDERINGI:
AT DISTANCE 1/16 ± 1/32 INCH
(1.59 ± 0.79 mml FROM CASE
FOR 10 SECONDS MAX_ . . . .
+26SoC

I
I

I
I

·Short circuit may be applidd to ground or to either
supply.

OffSET

"'''

TOTAL SUPPI..Y VOLTAGf: (FOR INDICATED VOLTAGE GAINS)""

V

·WITH INPUT TERMINALS BIASED SO THAT TERM 6 POTENTIAL

ELECTRICAL CHARACTERISTICS at T A-25°C, V+-15 V, V- - 0 V (Unless otherwil8 specified) .~,;~"~::'O;;E'::,='~'''''"
CHARACTERISTIC

CA3130B (T,S)
Min_ Typ. Max_

LIMITS
CA3130A (T,S,E)
CA3130 (T,S,E) Units
Min_ Typ_ Max_ Min_ Typ_ Max

Input Offset Voltage,
IVloI, V±=±7.5 V

0.8

2

2

5

8

15

mV

Input Offset Current,
11101, V±=±7.5 V

0.5

10

0_5

20

0.5

30

pA

5

20

5

30

5

50

Input Current, II
V±=±7_5 V

lOOk 320k
Large-Signal Voltage
Gain, AOL
110
VO=10 V p _p ' RL =2 kQ 100
Common-Mode
86
100
Rejection Ratio,CMRR
-0_5
Common-Mode Inputo
to
Voltage Range, V ICR
12
Power-Supply Rejection
32
Ratio, !WIO/6.V±
V±=±7.5 V

50 k 320 k

10

10 " " ' " " ' ' ' ' " " .

Fig_ 3 - Block diagram of the CA3130 Series.

pA

50 k

320 k

VN

94

110

94

110

dB

80

90

70

90

dB

FREQUENCY U1- HI'

o

-0.5
to
12

10

o

-0.5
to
12

v

Fig. 4 - Open-loop voltage gsin snd phsse shift
vs. frequency for various values of
CL , CC,and R L .

32

150

100

32

10

320 I1VN

110 LOAD RESlsrANC£ IRL.I- 2: kll

Maximum Output
Voltage:
12
VO..M+

14.99

13.3
0.002

12
0.01

14.99

15

o

0.01

22

45

13.3
0.002 0.01

12

14.99

15

o

0.01

22

45

20

45

13.3
0.002 0.Q1
15

o

V

10M

Va

(Sink)@
= 15 V

110

~ 100

0.01

ioo

Maximum Output
Current:
10M+ (Source)@

Va = ov

i

-100

12
12

12

12

22

45

12

20

45

15

10

15

3

2

3

20

45

10

15

10
2

Fig.12

3
15

Fig.12

Fig.12

5

15

10

10

12

mA

-'"

0

50

100

AMBIENT TEWERATURE ITAJ - °c
(nCS-2"YI7
Fig. 5 - Open-loop gain vs. temperature.

Supply Current, I :
VO=7.5V,RL=~

2

Input Current, II'
Input Offset Voltage
Temp. Orift,
6.VIO/llT·
Large-Signal Voltage
Gain, AOL'

mA
nA

50 k

320 k

320 k

320 k

v/V

94

110

110

110

dB

2.5

!I

1.15

10

li.15

I!!

11.!!

20

2Z.15

GATE VOLTAGE (VG) [TERMS" 80 e]-v
nCS-2"111
F,g. 6 - Voltage transfer characteristics of

COS/MaS output stage.

_______________________________________________________________ 219

CA3130, CA3130A, CA3130B Types
TYPICAL VALUES INTENDED ONL Y FOR DESIGN GUIDANCE
TEST
CONDITIONS

CHARACTERISTIC

Input Offset Voltage
Adjustment Range

v+ =+7.5 V
V- =-7.5 V
TA =25°C
(Unless Other·
wi se Specified)

CA3130B
(T,S)

CA3130A
(T,S,E)

CA3130
(T,S,E)

UNITS

10 kn across
Terms. 4 and 5
or 4 and 1

±22

±22

±22

mV

1.5

1.5

1.5

Tn

Input Capacitance, CI

f = 1 MHz

4.3

4.3

4.3

pF

Equivalent Input Noise
Voltage, en

BW - 0.2 MHz
RS=IMn*

23

23

23

/1V

Unity Gain Crossover

CC= 0

15

15

15

Cc = 47 pF

4

4

4

CC=O

30

30

30

CC=56pF

10

10

10

0.09

0.09

0.09

/1s

10

10

10

%

Input Resistance, RI

Frequency, fT
Slew Rate, SR:
Open Loop
Closeci Loop
Transient Response:
Rise Time, tr
Overshoot
Settling Time (4 V p.p
Input to <0.1 %)

Cc = 56 pF
CL = 25 pF
RL=2kn
(Voltage
Follower)

Fig. 7 - Quiescent supply current vs. supply voltage.

I

E 12'

4

1.2

1.2

1.2

92CS-241'20

at several temperatures.

/1S

,

I

i~Vi

0 I

~

CA3130B
(T,S)

CA3130A
(T,S,E)

CA3130
(T,S,E)

UNITS

,

o

~~

"
'

OOI!

,,,'

,~

.'

~,~~

.f>v

i:?~q¢
",~ O.OOIZ

0.001

mV

1

2

Input Offset Current, 110

0.1

0.1

0.1

pA

2

2

2

pA

RL=5kn

i>
"/
5_

~::

Input Offset Voltage, VIO

Gain, AOL
Common·Mode Input
Voltage Range, V ICR

~

NEGATIVE SUPPLY 'IOl.TAGE (V-)- 0 II
AMBIENT TEMPERATURE (TAl. 25"C

1O!

II :,
:
8

Vo = 4 V p .p

6
8
10
Ii'!
14
TOTAL SUPPLY VOLTAGE 1\1+-'-11

Fig. 8 - Quiescent supply current vs. supply voltage

TEST
CONDITIONS

Large·Signal Voltage

!

V//1S

up to 10 Mil.

Common· Mode Rejection
Ratio, CMRR

~

MHz

OQ

Input Current, II

t

It:

Ift!'~ ,I::

~

CHARACTERISTIC

~

v-· 0

}

* Although a 1·Mn source is used for this test, the equivalent input noise remains constant for values of RS

V+=5 V
V-=OV
TA = 25°C
(Unless Other·
wise Specified)

H t; 1

141 OUTPUT VOL rAGE (Vol .Y+/z

oct

100

90

80

dB

100 k

100 k

lOOk

V/V

100

100

100

dB

o to 2.8

o to 2.8

o to 2.8

V

300

300

300

500

500

500

2

4,.
241.
0.01
0.1

24'1

1

1:

4"

MAGNITUDE OF LOAD CURRENT (ILl -

10

1:

4"

100

mA
92CS-24T21

Fig. 9 - Voltage across PMOS output transistor
(08) vs. load current.

Vo = 5 V,
Supply Current, 1+

Power Supply Rejection
Ratio, t:NIO/b.V+

RL = 00
Vo - 2.5 V,
RL = 00

/1 A
0001

1:

4',

001

1:

4 ••

01

1:

41.

I

1:

4"

MAGNITUDE Of Lc»D CURRENT (ILl -

10

1:

411

100

mA
92CS-1:41U

200

200

200

/1V/V

Fig. 10 - Voltage across NMOS output transistor
(012) VS. load current.

220 ______________________________________________________----------

CA3130, CA3130A, CA3130B Types
CIRCUIT DESCRIPTION
Fig. 3 is a block diagram of the CA3130
Series COS/MOS Operational Amplifiers. The
input terminals may be operated down to
0.5 V below the negative supply rail, and the
output can be swung very close to either
supply rail in many applications. Conse·
quently, the CA3130 Series circuits are ideal
for single·supply operation. Three Class A
amplifier stages, having the individual gain
capability and current consumption shown
in Fig. 3, provide the total gain of the
CA3130. A biasing circuit provides two
potentials for common use in the first and
second stages. Term. 8 can be used both for
phase compensation and to strobe the output
stage into quiescence. When Term. 8 is tied
to the negative supply rail (Term. 4) by
mechanical or electrical means, the output
potential at Term. 6 essentially rises to the
positive supply·rail potential at Term. 7.
This condition of essentially zero current
drain in the output stage under the strobed
"OFF" condition can only be achieved when
the ohmic load resistance presented to the
amplifier is very high (e.g., when the amplifier
output is used to drive COS/MOS digital
circuits in comparator applications).

Input Stages-The circuit of the CA3130 is
shown in Fig. 1. It consists of a differential·
input stage using PMOS field-effect transistors (06, 07) working into a mirror-pair
of bipolar transistors (09, 010) functioning
as load resistors together with resistors R3
through R6. The mirror'pair transistors also
function as a differential-to-single-ended converter to provide base drive to the secondstage bipolar transistor (011). Offset nulling,
when desired, can be effected by connecting
a 100,OOO'ohm potentiometer across Terms.
1 and 5 and the potentiometer slider arm to
Term. 4. Cascade-connected PMOS transistors
02, 04 are the constant-current source for
the input stage. The biasing circuit for the
constant-LUrrent source is subsequently described. The small diodes D5 through D8
provide gate-oxide protection against high·
voltage transients, e.g., including static elec·
tricity during handl ing for 06 and 07.
Second·Stage-Most of the voltage gain in the
CA3130 is provided by the second amplifier
stage, consisting of bipolar transistor 011
and its cascade-connected load resistance
provided by PMOS transistors 03 and 05.
The source of bias potentials for these PMOS
transistors is subsequently described. MillerEffect compensation (roll-off) is accomplished by simply connecting a small capacitor between Terms. 1 and 8. A 47'picofarad
capacitor provides sufficient compensation
for stable unity·gain operation in most
applications.
Bias-Source Circuit-At total supply voltages,
somewhat above 8.3 volts, resistor R2 and
zener diode Zl serve to establish a voltage of
8.3 volts across the series-connected circuit,
consisting of resistor Rl, diodes Dl through
D4, and PMOS transistor 01. A tap at the
junction of resistor Rl and diode D4 provides
a gate-bias potential of about 4.5 volts for

PMOS transistors 04 and 05 with respect to
Term. 7. A potential of about 2.2 volts is
developed across diode·connected PMOS transistor 01 with respect to Term. 7 to provide
gate bias for PMOS transistors 02 and 03. It
should be noted that 01 is "mirror-connected"t to both 02 and 03. Since transistors 01, 02, 03 are designed to be identical, the approximately 200-microampere
current in 01 establishes a similar current in
02 and 03 as constant-current sources for
both the first and second amplifier stages,
respectively.
At total supply voltages somewhat less than
8.3 volts, zener diode Zl becomes nonconductive and the potential, developed
across series-connected Rl, Dl-D4, and 01,
varies directly with variations in supply
voltage, Consequently, the gate bias for 04,
05 and 02, 03 varies in accordance with
supply-voltage variations. This variation results in deterioration of the power-supplyrejection ratio (PSRR) at total supply voltages below 8.3 volts. Operation at total supply voltages below about 4.5 volts results in
seriously degraded performance.
Output Stage-The output stage consists of a
drain-loaded inverting amplifier using cost
MOS transistors operating in the Class A
mode. When operating into very high resistance loads, the output can be swung within
millivolts of either supply rail. Because the
output stage is a drain-loaded amplifier, its
gain is dependent upon the load impedance.
The transfer characteristics of the output
stage for a load returned to the negative
supply rail are shown in Fig. 6. Typical opamp loads are readily driven by the output
stage. Because large-signal excursiorrs are nonlinear, requiring feedback for good waveform
reproduction, transient delays may be encountered. As a voltage follower, the amplifier can achieve 0.01 per cent accuracy levels,
including the negative supply rail.
I nput Current Variation with CommonMode Input Voltage
As shown in the Table of Electrical Charac·
(eristics, the input current for the CA3130
Series Op-Amps is typically 5 pA at T A=2S o C
when terminals 2 and 3 are at a commonmode potential of +7.S volts with respect to
negative supply Terminal 4. Fig.ll contains
data showing the variation of input current
as a function of common-mode input voltage
at T A = 2S o C. These data show that circuit
designers can advantageo~sly exploit these
characteristics to design circuits which typically require an input current of less than 1
pA, provided the common-mode input voltage does not exceed 2 volts. As previously
noted, the input current is essentially the
result of the leakage current through the

gate'protection diodes in the input circuit
and, therefore, a function of the applied

INPUT CURRENT lIT 1- pA

Fig.tt - Input current vs. common-mode voltage.

Voltage. Although the finite resistance of the
glass terminal-to-case insulator of the TO-S
package also contributes an increment of
leakage current, there are useful compensating factors. Because the gate-protection network functions as if it is connected to
Terminal 4 potential, and the TO·S case of
the CA3130 is also internally tied to Terminal4. input terminal 3 is essentially "guarded"
from spurious leakage currents.
Offset Nulling
Offset-voltage nulling is usually accomplished
with a 100,OOO'ohm potentiometer connected across Terms. 1 and S and with the
potentiometer slider arm connected to Term.
4. A fine offset-null adjustment usually can
be effected with the slider arm positioned in
the mid-point of the potentiometer's total
range.
Input-Current Variation with Temperature
The input current of the CA3130 Series circuits is typically S pA at 2S o C. The major
portion of this input current is due to leakage
current through the gate-protective diodes in
the input circuit. As with any semiconductorjunction device, including op amps with a
junction·FET input stage, the leakage current approximately doubles for every 100C
increase in temperature. Fig.12 provides data
on the typical variation of input bias current
as a function of temperature in the CA3130.

I

-60

-60

-40

-20

L

0

20

40

60

eo

100

120

140

AMBIENT TEMPERATURE (TAI-·C

tFor general information on the characteristics

of COS/MOS transistor-pairs in linear-circuit
applications, see File No. 619, data bulletin on

CA3600E "COS/MaS Transistor Array".

Fig. 12 - Input current vs. ambient temperature.

In applications requiring the lowest practical
input current and incremental increases in

_____________________________________________________________________ 221

CA3130, CA3130A, CA3130B Types
current because of "warm-up" effects, it is
suggested that an appropriate heat sink be
used with the CA3130_ In addition, when
"sinking" or "sourcing" significant output
. current the chip temperature increases,
causing an increase in the input current. In
such cases, heat-sinking can also very markedly reduce and stabilize input current
variations.

•

Input-Offset-Voltage (VIO) Variation with
DC Bias vs_ Device Operating Life
It is well known that the characteristics of a
MOS/FET device can change slightly when a
dc gate-source bias potential is applied to the
.device for extended time periods. The magni-tude of the change is increased at high temperatures. Users of the CA3130 should be
alert to the possible impacts of this effect if
the application of the device involves extended operation at high temperatures with a
significant differential dc bias voltage applied
across Terms. 2 and 3. Fig.13 shows typical
data pertinent to shifts in offset voltage
encountered with CA3130 devices (TO-5
package) during life testing. At lower temperatures (TO-5 and plastic), for example
at 85 0 C, this change in voltage is corisiderably less.
In typical linear applications where the differential voltage is small
and symmetrical, these incremental changes
are of about the same magnitude as those
encountered in an operational amplifier em'ploying a bipolar transistor input stage. The
two-volt dc differential voltage example represents conditions when the amplifier output
stage is "toggled", e.g., as in comparator
applications.
1,

AMBIEN~

TEMPERATURE IT",oI2S"C

f

~

5

~

i!i

4

~
g

3

~

DIFFERENTIAL DC VOLTAGE

a

(ACROSS TERMS. 2
31-0 II
OUTPUT VOLTAGE. V+j2
~

1000

I~

2000 2500 3000

TIME

ItJ~

3SOO 4000

HOURS

Fig. 13 - TVpical incremental offset-voltage shift
VI.

operating life.

Power-Supply Considerations
8ecause the CA3130 is very useful in singlesupply applications, it is pertinent to review
some considerations relating to power-supply
current consumption under both single- and
dual-supply service. Figs_ 14a and 14b show
the CA3130 connected for both dual- and
single-supply operation.
Dual-supply operation: When the output
voltage at Term. 6 is zero-volts, the currents
suppl ied by the two power supplies are equal.
When the gate terminals of 08 and 012 are
driven increasingly positive with respect to
ground, current flow through 012 (from the

-~

negative supply) to the load is increased and
current flow through 08 (from the positive
supply) decreases correspondingly. When the
gate terminals of 08 and 012 are driven increasingly negative with respect to ground,
current flow through 08 is increased and
current flow through 012 is decreased
accordingly.
Single-supply operation: Initially, let it be
assumed that the value of R L is very high
(or disconnected), and that the input-terminal
bias (Terms. 2 and 3) is such that the output terminal (No.6) voltage is at V+/2, i.e.,
the voltage-drops across 08 and 012 are of
equal magnitude. Fig. 7 shows typical quiescent supply-current vs. supply-voltage for the
CA3130 operated under these conditions.
Since the output stage is operating as a
Class A amplifier, the supply-current will
remain constant under dynamic operating
conditions as long as the transistors are
operated in the linear portion of their
voltage-transfer characteristics (see Fig. 6).
If either 08 or 012 are swung out of their
linear regions toward cut-off (a non-linear
region). there will be a corresponding reduction in supply-current. In the extreme
case, e.g., with Term. 8 swung down to
ground potential (or tied to ground). NMOS
transistor 012 is completely cut off and the
supply-current to series-connected transistors
08, 012 goes essentiany to zero. The two
preceding stages in the CA3130, however,
continue to draw modest supply-current (see
the lower curve in Fig. 7) even though the
output stage is strobed off. Fig. 14a shows a
dual-supply arrangement for the output stage
that can also be strobed off, assuming RL =00,
by pulling the potential of Term. 8 down to
that of Term. 4.
Let it now be assumed that a load-resistance
of nominal value (e.g., 2 kilohms) is connected between Term. 6 and ground in the
circuit of Fig.14b. Let it further be assumed
again that the input-terminal bias (Terms. 2
and 3) is such that the output terminal (No.
6) voltage is a V+/2. Since PMOS transistor
08 must now supply quiescent current to
both R L and transistor 012, it should be
apparent that under these conditions the
supply-current \'lust increase as an inverse
function of the RL magnitude. Fig. 9 shows
the voltage-drop across PMOS transistor 08
as a function of load current at several supplyvoltages. Fig. 6 shows the voltage-transfer
characteristics of the output stage for several
values of load resistance_
Wide band Noise
From the standpoint of low-noise performance considerations, the use of the CA3130
is most advantageous in appl ications' where
in the source resistance of the input signal is
in the order of 1 meg'ohm or more_ In this
case, the total input-referred noise voltage
is typically only 23 I1V when the test-circuit
amplifier of Fig. 15 is operated at a total
supply voltage of 15 volts. This value of
total input-referred noise remains essentially
constant, even though the value of source

.

-r POSITIVE

1

10J

sUPPt.Y

DUAL POWER-SUPPLY OPERATION

Ibl SINGLE

POWER~SUPPlY

OPERATION

Fig_74 - CA3730 output stage in dual and single
power-supply operation.

+1.5 II

BWI-3dB)-200

~HI

TOTAL. NOISE VOLTAGE (REFERRED

IOn

TO INPUn-23,.V TYP.

Fig. 75 - Test-t:ircuit amplifier (30-dB gain) used

for wideband noise measurements.

resistance is raised by an order of magnitude.
This characteristic is due to the fact that
reactance of the input capacitance becomes a
significant factor in _ shunting the source
resistance: It should be noted, however, that
for values of source resistance very much
greater than 1 megohm, the total noise
voltage generated can be dominated by the
thermal noise contributions of both the
feedback and source resistors_
TYPICAL APPLICATIONS
Voltage Followers
Operational amplifiers with very high input
resistances, like the CA3130, are particularly

222 _____________________________________________________________________

CA3130, CA3130A, CA3130B Types
suited to service as voltage followers. Fig. 16
shows the circuit of a classical voltage
follower, together with pertinent waveforms
using the CA3130 in a split·supply configuration.
A voltage folloVloer, operated from a single
supply, is shown in Fig. 17, together with
related waveforms. This follower circuit is
linear over a wide dynamic range, as illustrated by the reproduction of the output
+1~

V

10 kO

waveform in
Fig. 17a with input-signal
ramping. The waveforms in Fig. 17b show
that the follower does not lose its input-tooutput phase-sense, even though the input is
being swung 7.5 volts below ground potential.
This unique characteristic is an important
attribute in both operational ampl ifier and
comparator appl ications. Fig. 17b also shows
the manner in which the COS/MaS output
stage permits the output signal to swing down
to the negative supply-rail potential (i.e.,
ground in the case shown). The digital-toanalog converter (DAC) circuit, described in
the following section, illustrates the practical
use of the CA3130 in a single-supply voltagefollower application_

10114

BW!-3dBI-4MHz
SR=tOVlp'

OI,w.F

9-Bit COS/MaS DAC
A typical circuit of a 9-bit Digital-to·Analog
Converter (DAC)* is shown in Fig.18 This
system combines the concepts of multipleswitch COS/MaS IC's, a low-cost ladder
network of discrete metal-oxide-film resistors,
a CA3130 op amp connected as a follower,
and an inexpensive monolithic regulator in a
simple single power·supply arrangement. An
additional feature of the DAC is that it is
readily interfaced with COS/MaS input logic,
e.g., 10-volt logic levels are used in the circuit
of Fig.18.
The circuit uses an R/2R voltage-ladder
network, with the output potential obtained
directly by terminating the ladder arms at
either the positive or the negative powersupply.terminal. Each CD4007A contains
three "inverters", each "inverter" functioning as a single-pole double-throw switch to
terminate an arm of the R/2 R network at
either the positive or negative power-supply
terminal. The resistor ladder is an assembly
of one per cent tolerance metal.-oxide film
resistors. The five arms requiring the highest
accuracy are assembled with series and
parallel combinations of 806,OOO-ohm res.istors from the same manufacturing lot.
A single 15-volt supply provides a positive
bus for the CA3130 follower amplifier and
feeds the CA3085 voltage regulator. A
"scale-adjust" function Is provided by the
regulator output control, set to a nominal
10-volt level in this s'f'stem. The line-voltage
regulation (approximately 0.2%) permits a
9-bit accuracy to be maintained with varia- .
tions of several volts in the supply. The
flexibility afforded by the COS/MaS building
blocks simpl ifies the design of DAC systems
tailored to particular needs.

Top Trace: Output
Bottom Trace: Input

ov

(a) Small-signal response (50 mV/div.
and ~OO ns/div.)
(a) Output-waveform with input-signal ramping

(2 VIdiv. and 500 jls/div.)

Top Trace: Output signal (2 VIdiv.
and 5 jls/div.)

92CS-24739

Center Trace: Difference signal (5 mV idiv.

and 5 jls/div.)
Bottom Trace: Input signal 12 V/div.
and 5 jls/div.)
(b) Input-output difference signal showing
settling time (Meas.urement made with

Tektronix 7 A 13 differential amplifier)
Fig. 16 - Split-supply voltage follower with
associated waveforms.

92CS- 24728RI
Top Trace: Output (5 V/div. and 200 jls/div.)
Bottom Trace: Input (5 V/div. and 200 jls/div.)
(b) Output-waveform with ground-reference

Single-Supply, Absolute-Value, Ideal FullWave Rectifier
The absolute-value circuit using the CA3130
is shown in Fig. 19_ During positive excursions, the input signal is fed through me
feedback network directly to the output.
Simultaneously, the positive excursion of the
input signal also drives the output terminal (No.6) of the inverting amplifier in a
negative-going excursion such that the 1 N914
diode effectively disconnects the amplifier
from the signal path. During a negative-going
excursion of the input signal, the CA3130
functions as a normal inverting amplifier with
a gain equal to -R2/Rl. When the equality
of the two equations shown in Fig. 19 is
satisfied, the full-wave output is symmetrical.
Peak Detectors
Peak-detector circuits are easily implemented
with the CA3130, as illustrated in Fig. 20
for both the peak-positive and the peaknegative circuit. It should be noted that with
large-signal inputs, the bandwidth of the

sine-wave input
Fig. 17 - Single-supply voltage-follower with
associated waveforms. (e.g., for use
in single·supply D/A converter.. see

Fig.9 in ICAN-6080).

*"Digital.to.Analog Conversion Using the
RCA-CD4007A COS/MOS IC", Application
Note ICAN-6080.

________________________________________________________----------223

CA3130, CA3130A, CA3130B Types
10 V LOGIC INPUTS
!

ill

REQUIRED
RATIO- MATCH

I

STANDARD

2

to.I%

3

to,2,".

4

to,4%

5

to.a%

6-9

t 1% ABS

ALL RESISTANCES IN OHMS

p"ak-negative circuit is much less than that of
the peak-positive circuit. The second stage
of the CA3130 limits the bandwidth in this
case. Negative-going output-signal excursion
requires a positive-going signal excursion at
the collector of transistor 011, which is
loaded by the intrinsic capacitance of the
associated circuitry in this mode. On the
other hand, during a negative-going signal
excursion at the collector of 011, the
transistor functions in an active "pull-down"
mode so that the intrinsic capacitance can be.
discharged more expeditiously.
6 "p_p I~PUTl
eW(-3 4B) • 1.3 101Hz

!
PARALLELED
RESISTORS

+DC
OUTI'UT

(0) PEAK POSITIVE DETECTOR CIRCUIT

6 Vp _ p INPUT;

REGULATED

aW(-3

VOLTAGE

~BI·

360 tH,

ADJ

OOOI,..F
383 K
1%

-DC

2 K

OUTPUT

IN91~

.~.

2.n
Fig. 18 - 9-bit DAC using COS/MaS digital switches and CA3130.
(b) PEAl( NEGATIVE DETECTOR CIRCUIT

Fig.20 - Peak-detector circuits.

.2

.!

~

.. n

GAIN'
R3-RI

'if ·x-

AI+:;+R3

(~)
! -x

FOR X·O.5,

!:~.*

R3' 4 kn (°07; ). 6 kn
20 v pop INPUT: BW(-3dB)- 230 kHz, DC OUTPUT (AVO,j. 3,2 V
(VOLT p-pINPUT
BW{-3dB)'130kHz,OCOUTPUT(AVG)'160mV

92CS- 24 738RI

Top Trace: Output signal (2 V Idiv.)
Bottom Trace: Input signal (10 V/div.1
Time base on both traces: 0.2 ms/div.

Fig. 19 -' Single-supply, absolute-value, ideal full-wave
rectifier with associated waveforms.

Error-Amplifier in Regulated-Power Supplies
The CA3130 is an ideal choice for erroramplifier service in regulated power supplies
since it can function as an error-amplifier
when the regulated output voltage is required to approach zero. Fig. 21 shows the
schematic diagram of a 40-mA power supply
capable of providing regulated output voltage by continuous adjustment over the range
from 0 to 13 volts. 03 and 04 in IC2 (a
CA3086 transistor-array IC) function as
zeners . to provide supply-voltage for the
CA3130 comparator (lC1). 01, 02, and
05 in IC2 are configured as a low impedance,
temperature-compensated source of adjustable reference voltage for the error amplifier.
Transistors 01, 02, 03, and 04 in IC3
(another CA3086 transistor-array IC) are
connected in parallel as the series-pass element. Transistor 05 in IC3 functions as a
current-limiting device by diverting base
drive from the series-pass transistors, in
accordance with the adjustment of resistor
R2.
Fig. 22 contains the schematic diagram of a
regulated power-supply capable of providing
regulated output voltage by continuous ad-

224 ____________________________________________________________________

CA3130, CA3130A, CA3130B Types
CURRENT

justment over the range from 0.1 to 50 volts
and currents up to 1 ampere. The error
amplifier (lCl) and circuitry associated with
IC2 function as previously described, al·
though the output of ICl is boosted by a
discrete transistor (04) to provide adequate
base drive for the Darlington·connected series·
pass transistors 01, 02. Transistor 03 func·
tions in the previously described current·
limiting circuit.

LIMIT

30

.""

02
100
lC3

[tiro••

-- --

3--'

I
I

I
I

141
I

I
I

L_

--1

I

+

Multivibrators
The exceptionally high input resistance pre·
sented by the CA3130 is an attractive feature
for multivibrator circuit design because it
permits the use of timing circuits with high
RIC ratios. The circuit diagram of a pulse
generator (astable multivibrator). with pro·
visions for independent control of the "on"
and "off" periods, is shown in Fig. 23.
Resistors R1 and R2 are used to bias the
CA3130 to the mid·point of the supply·volt·
age and R3 is the feedback resistor. The
pulse repetition rate is selected by position·
ing Sl to the desired position and the rate
remains essentially constant when the resistors which determine "on-period" and
"off-period" are adjusted .
Function Generator
Fig. 24 contains a schematic diagram of a
function generator using the CA3130 in the
integrator and threshold detector functions.
This circuit generates a triangular or squarewave output that can be swept over a
1,000,000:1 range (0.1 Hz to 100 kHz) by
means of a single control, R1. A voltagecontrol input is also available for remote
sweep-control.

2011.0.

3900

OUTPUT
OTO 13V

"0

AT

40 mA

2.2kD

0.01

-,
I
I

+20Y
INPUT

I

.,

141
100 '0

u

82kQ

REGULATION (NO LOAD TO FULL LOAD): c 0.01"-

INPUT REGULATION:

o.oz%,y

HUll AND NOISE OUTPUT: c 2!S,..V UP TO 100 kHz
92CM-24732

Fig.21- Voltage regulatorcircuir (0 to 13 Vat 40ma).

+~~------------------.-------~

4.3kn
IW

1000 pF

43kn
-

100

"F

OUTPUT:
0.1 TO 00 V
AT I A

The heart of the frequency-determining system is an operational-transconductance-amplifier (OTA)', IC1, operated as a voltage-controlled current-source. The output, la, is a
current applied directly to the integrating
capacitor, Cl, in the feedback loop of the
integrator IC2, using a CA3130, to provide
the triangular-wave output. Potentiometer
R2 is used to adjust the circuit for slope
symmetry of positive·going and negativegoing signal excursions.
Another CA3130, IC3, is used as a controlled
switch to set the excursion limits of the
triangular output from the integrator circuit.
Capacitor C2 is a "peaking adjustment" to
optimize the high-frequency square-wave
performance of the circuit.
Potentiometer R3 is adjustable to perfect the
"amplitude symmetry" of the square-wave
output signals. Output from the threshold
detector is fed back via resistor R4 to the
input of ICI so as to toggle the current
source from pi us to minus in generating the
linear triangular wave.

REGULATION INO LOAD TO FULL LOAD): 

~~6
-!!

~:kio
..
~- .

I
u

~

t-

e

rutm.

02
0.1

~ I.i~~: C~1f'it,.,.
t-...

2

.

III
IIII

IC· 100 mA

IIII
2

4

6

alb

2

4

~

0.41f--+-+--f-++--+-+-H--i---t-..J-+-6I

~ 02'r-4--+~~~--+-~}--b~~~

z

2

4 6 'Ix,o

..

,

2

..

,

8

2

..

68

100

1000

COLLECTOR CURRENT II l-mA

9ZCS-28481

Fig. 3 - V.at .slC

IS

lIS

8

10

BASE CURRENT« LB I-rnA

Fig. 2 - VCE(sat!

~

}-- VeE ISATI Zc/Xa -40

68,bo

: AMB'ENT TEMPERATURE {TAI-2S-C

I I

468

2

10

4

68

100

1000

COLLECTOR CURRENT 11 C I-rnA
92CS-28483

0.1

4

68,

'8,

..

V

20
25

V
V

EMITTER-TO-BASE
V
VOLTAGE ........... ..
5
With ColieClor Open IV EBOI
A
COLLECTOR CURRENT IICI
POWER DISSIPA!ION (POl:
At T A up to 25 C:
For Each Transistor ... .
1
W
Total Package 0 ....... .
2
W
At T A above 25 C derate
mWIOC
linearly ............. .
20
AMBIENT TEMPERATURE
RANGE:
°c
Operating ............. -55 to +125
°c
Storage .............. -65 to +150
LEAD TEMPERATURE
lOURING SOLDERINGI:
At distance 1116 ± 1/32 inch
(1.59 ± 0.79 mm) from case
for 10 seconds max. .....

4

15

265

°c

'8,~

REVERSE VOLTAGEIYRI-V
92CS-26484

228 ______________________________________________________________

CA3138G, CA3138AG Types
ELECTRICAL CHARACTERISTICS at T A = 2S"C
LIMITS

Characteristic

CA3138G

Test Conditions

CA3138AG

Units

Min. Typ. Max. Min. Typ. Max.
Collector-ta-Emitter Sustaining

Voltage, VCEO(susl*
Collector-ta-Emitter Breakdown

Voltage, V(BRICES
Collector-ta-Base Breakdown

Voltage, V(BRICBO
Emitter-ta-Base Breakdown

Voltage, V(BRIEBO
Base-ta-Emitter Saturation.

Voltage, VBE(satl*
Collector-ta-Emitter Saturation

Current

15

20

-

15

20

-

V

IC = 10 /lA

20

55

-

25

60

-

V

IC= 10/lA,IE=0

20

55

-

25

60

-

V

IE = 10 /lA, IC = 0

5

7.2

-

5

7.2

-

V

IC = 500 rnA, I B = 12.5 rnA 0.7

0.81

1.1

0.7

0.81

1.1

V

0.4

-

0.26

0.4

V

0.1

IC=500 rnA, IB = 12.5 rnA

-

0.26

ICBO

VCB=15V

-

0.03

-

0.02

ICEO

VCE=10V

-

0.5

-

-

0.3

1.0

VEB = 4 V

-

0.01

-

-

0.01

0.1

le10 rnA, VCE = 5 V

-

-

-

35

140

-

Voltage, VCE(satl'

Collector-Cutoff

IC = 1 rnA. I B = 0

lEBO

I =100mA,VCE=5V
Static Forward-Current Transfer C
Ratio (Betal, hFE*
I C = 500 rnA, V C E = 5 V
IC=lA,VCE=5V
Small·Signal Forward Current

Transfer

~atio.

hfe

IC=50mA,VCE=10V.
f= 100MHz

1

80

160 450

80

160 450

95

170

500

95

170 500

40

170

-

40

170

-

-

-

2

-

-

2

/lA

Collector-ta-Base
Capacitance, CCB

VCB = 10 V, IE = 0

-

18

-

-

18

-

pF

Emitter-ta-Base
Capacitance, CEB

VEB = 0.5 V, IC = 0

-

77

-

-

77

-

pF

Rise Time (See Test Ckt.
Fig.61,t,

IC = 570 rnA

-

6

-

-

6

-

ns

Fall Time (See Test Ckt.
Fig. 61, tf

I B1 =30mA

-

100

-

-

100

-

ns

Delay Time (See Test Ckt.
Fig. 61, td

IB2= 0

-

7.5

-

-

7.5

-

ns

-

850

-

-

850

-

ns

Sto,age Time (See Test Ckt.
Fig. 61, ts
*Pulse Conditions: width:: 300,us; duty cycle'" 1%.

+ 6V

+~VJlL CV~l~-V~~~
60 ~s ON
40 f'S OFF

Fig. 6 - Switching time test circuit and waveforms.

____________________________________________________________________ 229

CA3140, CA3140A, CA3140B Types

BiMOS Operational Amplifiers

Features:

With MOS/FET Input, Bipolar Output
The CA3140B, CA3l40A, and CA3140 are
integrated-circuit operational amplifiers that
combine the advantages of high-voltage PMOS
transistors with high-voltage bipolar transistors on a single monolithic chip_ Because
of this unique combination of technologies,
this device can now provide designers, for
the first time, with the special performance
features of the CA3130 COS/MaS operational amplifiers and the versatility of the
741 series of industry-standard operational
amplifiers_
The CA3140,CA3140A, and CA3140 BiMOS
operational amplifiers feature gate-protected
MOS/FET (PMOS) transistors in the input
circuit to provide very-high-input impedance,
very-low-input current, and high-speed performance. The CA3140B operates at supply
voltages from 4 to 44 volts; the CA3140A
and CA3140 from 4 to 36 volts (either single
or dual supply) _ These operational amplifiers
are internally phase-compensated to achieve
stable operation in unity-gain follower operation, and, additionally, have access terminals for a supplementary external capacitor
if additional frequency roll-off is desired_
Terminals are also provided for use in applications requiring input offset-voltage nulling_
The use of PMOS field-effect transistors in
the input stage results in common-mode input-voltage capability down to 0_5 volt below

the negative-supply terminal, an important
attribute for single-supply applications_ The
output stage uses bipolar transistors and includes built-in protection against damage
from load-terminal short-circuiting to either
supply-rail or to ground_
The CA3140 Series has the same 8-lead terminal pin-out used for the "741" and other
industry-standard operational ampl ifiers. They
are supplied in either the standard 8-lead
TO-5 style package (T suffix), or in the 8lead dual-in-line formed-lead TO-5 style package "DIL-CAN" (S suffix). The CA3140 is
available in chip form (H suffix)_ The
CA3140A and CA3140 are also available in
an 8-lead dual-in-line plastic package (MiniDIP-E suffix)' The CA3140B is intended for
operation at supply voltages ranging from 4
to 44 volts, for applications requiring premium-grade specifications and with electrical
limits established for operations over the
range from _55°C to +125°C_ The CA3l40A
and CA3l40 are for operation at supply voltages up to 36 volts (±18volts)_ TheCA3l40
ages up to 36 volts (±18 volts). All types can
be operated safely over the temperature range
from -55°C to +125°C.

- MOS/FET Input Stage
(a) Very high input impedance (ZIN) - 1.5 Tn typo
(b) Very low input current (II) - 10 pA typo at ± 15'
(c) Low input-offset voltage (VIO) - to 2 mV max.
(d) Wide common·mode input·voltage range (VICR)can be swung 0.5 volt below negative
supply·voltage rail
(e) Output swing complements input common· mode
range
(f) Rugged input stage - bipolar diode protected
- Directly replaces industry type 741 in
most applications
- Includes numerous industry operational
amplifier categories such as general·pur·
pose, F ET input, wideband (high slew rate)
- Operation from 4·to·44 volts
Single or Dual supplies
- Internally compensated
- Characterized for ± 15·volt operation
and for TTL supply systems with
operation down to 4 volts
- Wide bandwidth - 4.5 MHz unity
gain at ± 15 Vor 30 V; 3.7 MHzat5 V
- High voltage·follower slew rate - 9 VI/J-s
- Fast settling time - 1.4 /J-S typo
to 10 mV with a 10·Vp . p signal
- Output swings to within 0.2 volt
of negative supply
- Strobable output stage

MAXIMUM RATINGS,Absolute-Maximum Values:
CA3140, CA3140A
DC SUPPLY VOLTAGE
(BETWEEN v+ AND V- TERMINALS)
01 FFERENTIAL-MODE INPUT VOLTAGE
COMMON-MODE DC INPUT VOLTAGE
INPUT-TERMINAL CURRENT
DEVICE DISSIPATION:
WITHOUT HEAT SINKUP TO 550C_
ABOVE 55°C _
WITH HEAT SINK Up to 55°C.

CA3140B

36 V

44 V

±B V

±a V

(V+ +8 V) to (V- -0_5 V)
1 mA

630mW
Derate linearly 6.67 mW/oC
1W
Derate linearly 16.7 mW/oC

Above 55°C.
TEMPERATURE RANGE:
OPERATING (ALL TYPES)
STORAGE (ALL TYPES) _
OUTPUT SHORT-CIRCUIT DURATION"
LEAD TEMPERATURE (DURING SOLDERING):
AT DISTANCE 1/16 ± 1/32 INCH (1.59 ±O.79 MM)
FROM CASE FOR 10 SECONDS MAX_ .

-55 to + 125°C
. -6Sto+1S0oC
INDEFINITE

Applications:
- Ground·referenced single·supply amplifiers
in automobile and portable instrumentation
- Sample and hold amplifiers
- Long-duration timers/multivibrators
(microseconds-minutes-hours)
- Photocurrent instrumentation
- Peak deteC10rs
- Active filters
- Comparators
- Interface in 5 V TTL systems & other
low·supply voltage systems
- All standard operational amplifier applications
- Function generators - Tone controls
- Power supplies
- Portable instruments
_ I ntrusion alarm systems

• Short circuit may be applied to ground or to either supply,

OFFSET
NULL

OFFSET
NULL

TOP VIEW

Sand T Suffixes

Fig. 1 - Functional diagrams of the
CA3140 series.

230 ____________________________________________________________________

CA3140, CA3140A, CA3140B Types
TYPICAL ELECTRICAL CHARACTERISTICS
TEST
CONDITIONS
V+=+lSV
V-= -15V
TA = 2SoC

CHA RACTE R ISTI C

CIRCUIT DESCRIPTION

CA3140B CA3140A CA3140
(T,S)
(T,S,E) (T,S,E)

UNITS

Typ.Value 01 Re·
sistor Between

Input Ollset Voltage

Term. 4 and 5 or
4 and 1 to Adjust
Max. VIO

Adjustment Resistor

43

18

4.7

kD.

Input Resistance

Rl

1.5

1.5

1.5

Tn

Input Capacitance

CI

4

4

4

pF

Output Resistance

RO

60

60

60

n

48

48

48

IlV

40
12

40
12

40

40
18

40
18

40
18

mA
mA

Equivalent Wide band

Input Noise Voltage
(See Fig. 39)

en

Equivalent Input
Noise Voltage
ISee Fig.l 01

en

BW=140kHz
RS = 1 Mn
1= 1 kHz

I RS =

1= 10 kHz 1100 n

12

nV/..!Hz

Short-Circuit Current to

Opposite Supply Source IOM+
Sink
IOMGain·Bandwidth
Product, (See Figs. 5 &18)

IT

4.5

4.5

4.5

MHz

Slew Rate.ISee Fig.6)

SR

9

9

9

V/lls

220

220

220

IlA

0.08
10

0.08
10

0.08
10

IlS
%

4.5
1.4

4.5
1.4

4.5
1.4

IlS

Sink Current From Terminal 8
To Terminal 4 to Swing
Output Low
Transient Response:
Rise Time
Overshoot (See Fig. 37)

Settling Time
at 10 Vp. P.
(See F ig.17)

1 mV
10mV

tr
ts

RL=2kD.
CL=100pF
RL=2kn
CL = 100 pF
Voltage Follower

----------------,
2mA

4mA

,...--;:d~~---I--r7 v+

OFFSET
NULL

Fig. 2 - Block diagram of CA3140 series.

Fig.2 is a block diagram of the CA3140
Series PMOS Operational Amplifiers. The
input terminals may be operated down to
0.5 V below the negative supply rail. Two
class A amplifier stages provide the voltage
gain, and a unique class AS amplifier stage
provides the current gain necessary to drive
low·impedance loads.
A biasing circuit provides control of cascaded
constant-current flow circuits in the first and
second stages. The CA3140 includes an onchip phase-compensating capacitor that is
sufficient for the unity gain voltage-follower configuration.
Input Stages - The schematic circuit diagram
of the CA3140 is shown in Fig.3. It consists of a differential-input stage using PMOS
field-effect :transistors (Q9, Q1O) working
into a mirror pair! of bipolar transistors (Qll,
Q12) functioning as load resistors together
with 'csisturs R2 through R5. The mirrorpair transistors also function as a differ"~­
tial-to-single-ended converter to provide basecurrent drive to the second-stage bipolar
transistor (Q13). Offset nulling, when desired, can be effected with a 10.kD. potentiometer connected across terminals 1 and
5 and with its slider arm connected to terminal 4. Cascade-connected bipolar transistors
Q2, Q5 are the constant-current source for
the input stage. The base-biasing circuit for
the constant-current source is described subsequently. The small diodes 03, 04, 05 provide gate·oxide protection against high-voltage transients, e.g., static electricity.
Second Stage - Most of the voltage gain in
the CA3140 is provided by the second amplifier stage, consisting of bipolar transistor
Q 13 and its cascade-connected load resistance provided by pipolar transistors Q3, Q4.
On-chip phase compensation, sufficient for
a majority of the applications is provided by
Cl. Additional Miller-Effect compensation
(roll-off) can be accomplished, when desired, by simply connecting a small capacitor between terminals 1 and 8. Terminal
8 is also used to strobe the output stage into
quiescence. When terminal 8 is tied to the
negative supply rail (terminal 4) by mechanicalor electrical means. the output terminal 6
swings low, i.e., approximately to terminal
4 potential.
Output Stage - The CA3140 Series circuits
employ a broadband output stage that can
sink loads to the negative supply to complement the capability of the PMOS input stage
when operating near the negative rail. Quiescent current in the emitter-follower cascade
circuit (Q17, Q18) is established by transistors (Q14, Q15) whose base-currents are
"mirrored" to current flowing through diode
02 in the bias circuit section. When the
CA3140 is operating such that output terminal 6 is sourcing current, transistor Q18
functions as an emitter-fOllower to source
current from the V+ bus (terminal 7), via
07, R9, and R 11. Under these conditions,
the collector potential of Q13 is sufficiently high to permit the necessary flow of
base current to emitter follower Q17 which,
in turn, drives Q18.

231

CA3140, CA3140A, CA3140B Types
ELECTRICAL CHARACTERISTICS FOR EQUIPMENT DESIGN
At

v+ = 15 V, v- = 15 V, TA = 25°C Unless Otherwise Specified
LIMITS

CHARACTERISTIC

Input Offset Voltage. IVlol
Input Offset Current.

11101

Input Current. II
Large·Signal
Voltage Gain. AOL •
(See Figs. 4.18)
Common·Mode
Rejection Ratio. CMR R
(See Fig.9)
Common·Mode
Input·Voltage
Range. VICR
(See Fig.20)

CA3140B
CA3140A
Min. Typ. Max. Min. Typ. Max.

CA3140
Min. Typ. Max.

UNllS

-

0.8

2

-

2

5

-

5

15

mV

-

0.5

10

-

0.5

20

-

0.5

30

pA

-

10

30

-

10

40

-

10

50

pA

50 k
94

100 k
100

-

-

20
94

50

-

-

70

12

-15

86

-

20 k 100 k
100
86

-15.5
-15

to

+12.5

-

20 k 100 k
86
100

-

V/V

-

d8

320

-

-

70

-15.5
to
+12.5

12

-15

-15.5
to
+12.5

11

V

32
90

32
90

320 IlV/V
d8
-

Power·Supply
-

32

100

-

100

150

-

100

150

IlV/V

80

90

-

76

80

-

76

80

-

dB

+12
-14

13
-14.4

-

-

4

6

-

4

6

-

4

6

rnA

-

120

180

-

120

180

-

120

180

mW

-

10

30

-

10

-

-

10

-

nA

Input Offset
Voltage IVlol'"

-

1.3

3

-

3

-

-

10

-

mV

Input Offset Voltage
Temp. Drift, LW IOILH

-

5

-

-

6

-

-

8

-

Il vtc

Large·Signal
Voltage Gain. AOL '"
(See Figs.4,18)

20 k
86

100 k
100

-

-

-

V/V

-

-

100 k
100

-

-

100 k
100

-

-

-

dB

Max. Output
Voltage,*

+19.5
-21.4

-

-

-

-

-

-

-

-

-

-

-

VOM

+19
-21

-

-

Large·Signal
Voltage Gain, AOL '*

20 k
86

50 k
94

-

-

-

-

-

-

-

-

-

-

-

-

-

Rejection

IWI0/6V

Ratio. PSR R
ISee Fig.ll)
Max. Output
Voltage-

VOM+

(See Figs.13.20) VOM
Supply Current. 1+
(See Fig.7 )
Device Dissipation,

Po

Input Current. II'"
(See F ig.19)

VOM+

-

• At Vo = 26Vp.p, +12V, -14V and RL -- 2 kn.

+12
13
-14 -14.4

-

+12
13
-14 -14.4

-

V

V

v/v
dB

When the CA3140 is operating such that
output terminal 6 is sinking current to the
V- bus, transistor Q16 is the current-sinking
element. Transistor Q16 is mirror-connected
to D6, R7, with current fed by way of Q21,
R 12, and Q20. Transistor Q20, in turn, is
biased by current-flow through R 13, zener
D8, and R 14, The dynamic current-sink
is controlled by voltage-level sensing. For
purposes of explanation, it is assumed that
output terminal 6 is quiescently established
at the potential mid-point between the V+
and V-supply rails. When output-current
sinking-mode operation is required, the collector potential of transistor Q13 is driven
below its quiescent level, thereby causing
Q17, Q18 to decrease the output voltage at
terminal 6. Thus, the gate terminal of PMOS
transistor Q21 is displaced toward the V- bus,
thereby reducing the channel resistance of
Q21. As a consequence. there is an incremental increase in current flow through
Q20, R12, Q21, D6, R7, and the base of
Q16. As a result, Q16 sinks current from
terminal 6 in direct response to the incremental change in output voltage caused by
Q18. This sink cunent flows regardless of
load; any excess current is internally supplied
by the emitter-follower Q18. Short·circuit
protection of the output circu it is provided
by Q19, which is driven into conduction by
the high voltage drop developed across R 11
under output short-circuit conditions. Under
these conditions, the collector of Q19 diverts current from Q4 so as to reduce the
base-current drive from Q17. thereby limiting current flow in Q18 to the short-circuited load terminal.
Bias Circuit - Quiescent current in all stages
(except the dynamic current sink) of the
CA3140 is dependent upon bias current
flow in R 1. The function of the bias circuit is to establish and maintain constantcurrent flow through Dl, Q6, Q8 and D2.
Dl is a diode-connected transistor mirrorconnected in parallel with the base-emitter
junctions of Ql. Q2. and Q3. Dl may be
considered as a current-sampling diode that
senses the emitter current of Q6 and automatically adjusts the base current of Q6
(via Ql) to maintain a constant current
through Q6, Q8. D2. The base-currents in
Q2. Q3 are also determined by constantcurrent flow Dl. Furthermore, current in
diode-connected transistor D2 establishes the
currents in transistors Q14 and Q15.

• At RL = 2 kn.
kn.
* At V+ = 22 V, V- = 22 V.

'" At TA = -55 0 C to +125 0 C, V+ = 15 V. V- = 15 V, Vo = 26Vp.p, RL = 2
, At Va = +19 V, -21 V, and RL = 2 kn.

232 ____________________________________________________________________

CA3140, CA3140A, CA3140B Types
BIAS CIRCUIT

INPUT STAGE

1----'1----I
II
,----1+---1------,
I 01

LOAD RESISTANCE {RL>· 2 kn

I

~

I

~ 125
AMBIENT TEMPERATURE (TA,I--Moe

~IOO

I
I
I
I 8kRI

~ 75

g
~
~

50

"
5

I
I

10
15
20
SUPPLY VOLTAGE {V+, 'rl-voLTS

Fig.4 - Open-loop voltage gain vs supply voltage
and temperature.

L __ _

20

LOAD RESISTANCE (ALl- 2 kfi
LOAD CAPACITANCE (CL) ~~

>

rs~~
i.
TEMPERATURE(TAI~
f-. .-

--

AMBIENT

-55"C
25"C

~

OfFSET NULL

STROBE

ALL RESISTANCE VALUES ARE IN OHMS.

5

10

15

20

SUPPLY VOLTAGE (V·, V-)- VOi..TS

Fig.3 - Schematic diagram of CA3140 series.

Fig.5 - Gain-bandwidth product vs supply voltage
and temperature.

TYPICAL ELECTRICAL CHARACTERISTICS FOR DESIGN GUIDANCE
At V+= 5 V, V-= 0 V, TA = 25°C
CHARACTERISTIC

20 LOAD RESISTANCE (RL)-2 kfi
LOAD CAPACITANCE (CL) -100 pF

CA3140B
(T,S)

CA3140A
(T,S,E)

CA3140
(T,S,E)

2

UNITS
mV

Input Offset Voltage

IVlol

0.8

Input Offset Current

1'101

0.1

0.1

5
0.1

II

2

2

2

pA

1

1

1

Tn

11

100 k

100 k

100 k

VIV

it

100

100

100

dB

I nput Current

Input Resistance
Large-Signal Voltage Gain

AOL

(See Figs.4,18)
CMRR

Common-Mode Rejection Ratio,

Common-Mode Input·Voltage Range

VICR

(See F i9.2O)
Power-Supply Rejection Ratio

t,VIOlt,V+

pA

20

32

32

pVIV

94

90

90

dB

-0.5

-0.5

-0.5

2.6

2.6

2.6

5

lill tt

riCr

10
15
20
SUPPLY VOLTAGE (v"', V-l- veLTS

Fig.6 - Slew rate vs supply voltage andtemperature.

32

100

100

pVIV

80

80

dB

VOM+

3

3

3

VOM-

0.13

0.13

0.13

Source

10M+

10

10

10

Sink

10M-

1

1

1

(See Figs.13,20)

L

V

90
Maximum Output Voltage

tm :f:h
~rt j r

LOAD RESISTANCE (RLI ·ID

~ 7

V

I

Maximum Output Current:
rnA

7

7

7

Vips

Gain·Bandwidth Product (See Fig.5)

IT

3.7

3.7

3.7

MHz

Supply Current (See Fig.7)

1+

1.6

1.6

1.6

rnA
mW

Slew Rate (See Fig.6)

Dev:ce Dissipation

Po

8

8

8

200

200

200

r

10

15

20

25

SUPPLY VOLTAGE (V ..., V-I - VOL T5

Sink Current from Term, 8 to
Term. 4 to Swing Output Low

I1A

Fig.? - Quiescent supply current vs supply voltage
and temperature.

____________________________________________________________________ 233

CA3140,CA3140A, CA3140B Types
APPLICATIONS CONSIDERA nONS

AMBIENT TEMPERATURE (TA) • 25"C

>
I

SUPPLY VOL rAGE! V+·15 V,' V-'-15 V

1 25

\

?

;;;20

~

!
~

\

"

1\

10

\

"-

5

~

.'"-----,

..

,

0

lOOK

10 K

FREQUENCY (f)-Ht

'"

Fig.8 - Maximum output voltage swing
vs frequency.

~

Wide dynamic range of input and output
characteristics with the most desirable high
input-impedance characteristic is achieved in
the CA3140 by the use of an unique design
based upon the PMOS-Bipolar process. Inputcommon-mode voltage range and outputswing capabilities are complementary, allowing operation with the single supply down
to four volts.
The wide dynamic range of these parameters
also means that this device is suitable for
many single-supply applications, such as,
for example, where one input is driven below the potential of terminal 4 and the
phase sense of the output signal must be
maintained - a most important consideration in comparator applications.

Fig.16 show some typical configurations.
Note that a series resistor, R L. is used in both
cases to limit the drive available to the driven
device. Moreover, it is recommended that a
series diode and shunt diode be used at the
thyristor input to prevent large negative
transient surges that can appear at the gate of
thyristors, from damaging the integrated
circuit.

120 SUPPLY VOL TAGE: v+~ 15 V, V- '-15 II
AMBIENT TEMPERATURE {TAl -25"C

OUTPUT CIRCUIT CONSIDERATIONS

I
~IOO

I

~
~ 80

Excellent interfacing with TTL circuitry is
easily achieved with a single 6.2-volt zener
diode connected to terminal 8 as shown in
Fig.12. This connection assures that the
maximum output signal swing will not go
more positive than the zener voltage minus
two base·to-emitter voltage drops within the
CA3140. These voltages are independent
of the operating supply voltage.

I

)ioLW
c:"
q,

z

:I,.~'1:

~ 60

I,J'/vd'

~w 40

~

I
I

I':
10

r"

,

,

10

10

I

I'

.

,

10
10
FREOUENCY (f)- Hz

.

10

,

v+

10

5T036V

Fig.9 - Common-mode rejection ratio
V$

frequency.

Fig. 12 - Zener clamping diode connected to
terminals 8 and 4 to limit CA3140
output swing to TTL levels.

10

102

103

10'

10'

FREQUENCY (f) - Hz

Fig.

to - Equivalent input noise voltage
vs frequency.

Fig.13 shows output current·sinking capabilities of the CA3140 at various supply
voltages. Output voltage swing to the negative·supply rail permits this device to operate both power transistors and thyristors
directly without the need for level-shifting
circuitry usually associated with the 741
series of operational amplifiers.
8 SUPPLY VOLTAGE (V-)-O V

1.0

0.01
10

103
104
FREQUENCY (f) -

10'
Hz

10'

Fig. 11 - Power supply rejection ratio
vs frequency.

10'

0.)

..

),0 .

LOAD (SINKING) CURRENT -

10

mA

TIME {ll- HOURS

Fig. 14 - Typical incremental offset-voltage
shift vs operating life.

OFFSET-VOLTAGE NULLING

The input-offset voltage can be nulled by
connecting a 10·kQ potentiometer between
terminals 1 and 5 and returning its wiper arm
to terminal· 4, see Fig.15a. This technique,
however, gives more adjustment range than
required and therefore, a considerable portion of the potentiometer rotation is not
fully utilized. Typical values of series resistors that may be placed at either end of
the potentiometer, see Fig.15b, to optimize
its utilization range are given in the table
"Typical Electrical Characteristics" shown
in this bulletin.
An alternate system is shown in Fig.15c. This
circuit uses only one additional resistor of
approximately the value shown in the table.
For potentiometers, in which the resistance
does not drop to zero ohms at either end of
rotation, a value of resistance 10% lower
than the values shown in the table should
be used.
LOW-VOLTAGE OPERATION

Operation at total supply voltages as low as
4 volts is possible with the CA3140. A current regulator based upon the PMOS threshold voltage maintains reasonable constant
operating current and hence consistent performance down to these lower voltages.
The low-voltage limitation occurs when the
upper extreme of the input common-mode
voltage range extends down to the voltage at
terminal 4. This limit is reached at a total
supply voltage just below 4 volts. The output voltage range also begins to extend down
to the negative supply rail, but is slightly
higher than that of the input. Fig.20 shows
these characteristics and shows that with
2-volt dual supplies, the lower extreme of the
input common-mode voltage range is below
ground potential.

Fig. 13 - Voltage across output transistors 015
and 016 vs load current.

234 _________________________________________________________________

CA3140, CA3140A, CA3140B Types

o

BASIC

b

c

IMPROVED
RESOLUTION

load current, device dissipation will increase,
raising the chip temperature and resulting in
increased input current. Fig.19 shows typical input-terminal current versus ambient
temperature for the CA3140.
It is well known that MOS/FET devices can
exhibit slight changes in characteristics (for
example, small changes in input offset voltage) due to the application of large differential input voltages that are sustained over
long periods at elevated temperatures.
Both applied voltage and temperature accelerate these changes. The process is reversible and offset voltage shifts of the opposite
polarity reverse the offset. F ig.14 shows the
typical offset voltage change as a function of
various stress voltages at the maximum rating
of 125°C (for TO-5); at lower temperatures
(TO-5 and plastic), for eXilmple, at 85°C,
this change in voltage is considerably less .
In typical linear applications, where the
differential voltage is small and symmetircal,
these incremental changes are of about the
same magnitude as those encountered in an
operational amplifier employing a bipolar a
transistor input stage.

SIMPLER
IMPRovED
RESOLUTION

Fig. 15 - Three offset-voltage nulling methods.
SUF'f>L.Y VOL.TAGE: V+·15 V; V-. 15 V
AMBIENT TEMPERATURE (TAI.Z5"C

FOLLOWER
- - - INVERTING

.

'0

>

I

8

4

~

~

~

,
°
-,
-4

-.-.

-'0

0.1

SUPER SWEEP FUNCTION GENERATOR
A function generator having a wide tuning
ranQe is shown in Fig.21. The 1,000,000/1
adjustment range is accomplished by a single
variable potentiometer or by an auxiliary
sweeping signal. The CA3140 functions as a
non-inverting read-out amplifier of the tri-

,
LO
(Gl SETTLING TIME -

.1'"

FOLLOWER

SUPPLY VOLTAGE, V+·+15 \/; V-. -15 V
AMBIENT TEMPERATURE (TAl. 25"C

Fig. 16 - Methods of utilizing the VCE($at) sinkingcurrent capability of the CA3140 series.

~

I

z

For those cases where bandwidth reduction
is desired, for example, broadband noise reduction, an external capacitor connected between terminals 1 and 8 can reduce the openloop -3 dB bandwidth_ The slew rate will,
however, also be proportionally reduced by
using this additional capacitor_ Thus, a 20%
reduction in bandwidth by this technique
will also reduce the slew rate by about 20%.
Fig.17 shows the typical settling time required to reach 1 mV or 10 mV of the final
value for var.ious levels of large signal inputs for the voltage-follower and inverting
unity-gain amplifiers. The exceptionally
fast settling time characteristics shown in
Fig.18 are largely due to the high combination of high gain and wide bandwidth of
the CA3140.
INPUT CIRCUIT CONSIDERATIONS
As mentioned previously, the amplifier inputs can be driven below the terminal 4
potential, but a series current-limiting resistor is recommended to limit the maximum
input terminal current to less than 1 rnA to
prevent damage to the input protection
circuitry.
Moreover, some current-limiting resistance
should be provided between the inverting
input and the output when the CA3140 is
used as a unity-gain voltage follower. This
resistance prevents the possibility of ex-

~

•

?0
<.

'Q

~
840

-

~

,

'<°<10

C'~<}l':

11~~rc

i2.0

INVERTING

0

to...

~.I~~

~60

-

t." -F.

~.~IJl
-;'1-~

:!80

BANDWIDTH AND SLEW RATE

~

'?

'°.0 III I

~

~!t

0",

III

100

I 1J1l,:"o

• kO

'0

'0'

'0'

III~

10

""

FREQUENCY (t) -

1()6

'0

Hr

SIMULATED

LOAD

Fig, 18 - Open-loop va/taga gain and phase lag
vs frequency_

>-r-'

00

PF~ ~2
I ~

kG

"."
5.llkQ -t.:

10

K:

SUPPLY VOLTAGE: V+·+15 V. V-.-15 V

/

!F
~ "'~~===$~~*~~~
I

(bl TEST CIRCUITS

-

Fig. 17 - Input voltage vs settling time_

tremely large input-signal transients from
forcing a signal through the input-protection
network and directly driving the internal
constant-current source which could result
in positive feedback via the output terminal.
A 3.9-kD. resistor is sufficient.
The typical input current is in the order of
10 pA when the inputs are centered at nominal device dissipation. As the output supplies

-60

-20

0

20

40

60

eo

100

120

1"'0

AMBIENT TEMPERATURE (TAl -"C

Fig. 19 -Input current vs ambient
temperature.

__________________________________________________________________ 235

CA3140, CA3140A, CA3140B Types
angular signal developed across the integrating capacitor network connected to the
output of the CA3080A current source.
Buffered triangular output signals are then
applied to a second CA3080 functioning as
a high-speed hysteresis switch. Output from
the switch is returned directly back to the

THIS NETWORK IS USED WHEN THE
OPTIONAL BUFFER CIRCUIT IS NOT
USED.

raj Circuit

FREQUENCY
ADJUSTMENT

.
~~

2.5

-VOUT FOR TA· -!!5"C TO +12!!-t
TOP TRACE; OUTPUT AT JUNCTION OF

VIeR AT TA a I25"C

2,7n AND !SIn RESISTORS

!S V/OIV AND !SOD ms/OIV
CENTER TRACE: EXTERNAL OUTPUT OF
TRIANGULAR FUNCTION

GENERATOR
2 VlOIV AND 500 ms/DIY

~

~

BOTTOM TRACE: OUTPUT OF "LOG"
GENERATOR
10 VIDIY ANO 500 ms/DIV

-2.5
!5

10
15
20
SUPPLY VOLTAGE (V·, v~J-VOLTS

(b 1) Function generator sweeping

Pig.20 - Output-voltage-swing capability and
common-mode input-voltage range

vs supply voltage and temperature.

input of the CA3080A current source, there·
by, completing the positive feedback loop.
The triangular output level is determined by
the four 1N914 level-limiting diodes of the
second CA3080 and the resistor-divider network connected to terminal No.2 (input) of
the CA3080. These diodes establish the input trip level to this switching stage and,
therefore, indirectly determine the amplitude of the output triangle.
Compensation for propagation delays around
the entire loop is provided by one adjustment on the input of the CA3080. Th is
adjustment, which provides for a constant
generator amplitude output, is most easily
made while the generator is sweeping. Highfrequency ramp linearity is adjusted by the
single 7-to-60 pF capacitor in the output of
the CA3080A.
It must be emphasized that only the CA3080A is characterized for maximum output
linearity in the current-generator function.
METER DRIVER AND
BUFFER AMPLIFIER
Fig. 22 shows the CA3140 connected as a
meter driver and buffer amplifier. Low
driving impedance is required of the CA3080A current source to assure smooth
operation of the Frequency Adjustment

fe) Interconnections

92C5-279:31

lV/DIV and 1 sec/DIV
Three tone test signals, highest frequency;;'
0.5 MHz. Note the slight assymmetry at the
three-second/cycle signal. This assymmetry
is due to slightly different positive and negative integration from the CA3080A and from
the pc board and component leakages at the
100-pA level.

(b2) Function generator with fixed frequencies
Fig.21 - Function generator.

Control.
This low-driving impedance requirement is easily met by using a CA3140
connected as a voltage follower. More·
over, a meter may be placed across the
input to the CA30BOA to give a logarithmic
analog indication of the function generators
frequency.
Analog frequency readout is readily accom·
plished by the means described above be·
cause the output current of the CA3080A
varies approximately one decade for each
60-mV change in the applied voltage, VABC
(voltage between terminals 5 and 4 of the
CA3080A of the function generator). Therefore, six decades represent 360·mV change
in VABC.
Now, only the reference voltage must be
established to set the lower limit on the
meter. The three rem?ining transistors from

the CA3086 Array used in the sweep generator are used for this reference voltage. In
addition, this reference generator arrangement tends to track ambient temperature
variations, and thus compensates for the effects of the normal negative temperature
coefficient of the CA3080A VABC termi·
nal voltage.
Another output voltage from the reference
generator is used to insure temperature
tracking of the lower end of the Frequency
Adjustment Potentiometer. A large series
resistance simulates a current source, assuring
similar temperature coefficients at both ends
of the Frequency Adjustment Control.
To calibrate this circuit, set the Frequency
Adjustment Potentiometer at its low end.
Then adjust the Minimum Frequency Calibration Control for the lowest frequency. To

236 ____________________________________________________________________

CA3140, CA3140A, CA3140B Types

5.1 kn

620

n
100 kG

FREQUENCY
CALIBRATION

-15 V

MINIMUM

I
I

I

I
CA3019 05

~O~~E_~~A~ __

I

J

Fig. 23 - Sine-wave shapero
-15 V

potentiometer connected between terminals
2 and 6 of the CA3140 and the 9.1-kQ resistor and 10-kQ potentiometer from terminal 2 to ground. Two break points are established by diodes 01 through 04. Positive
feedback via 05 and 06 establishes the zero
slope at the maximum and minimum levels
of the sine wave. This technique is necessary because the voltage-follower configuration approaches unity gain rather than the
zero gain required to shape the sine wave at
the two extremes.

Fig. 22 - Meter driver and buffer amplifier.
750llfi

100 kn

100 kG

FINE
RATE

B.2 kG

+1511

SAWTOOTH AND
RAMP

LOW'LEVEL SET
(-)4.5 V)

75 kfi

SIUl

10 kO

GATE

>--(6)-+--'V'I'v-~ PULSE
OUTPUT

This circuit can be adjusted most easily with
a distortion analyzer, but a good first approximation can be made by comparing the output
signal with that of a sine-wave generator. The
initial slope is adjusted with the potentiometer R 1, followed by an adjustment of
R2. The final slope is established by adjusting R3, thereby adding addition a! segments that are contributed by these diodes.
Because there is some interaction among
these controls, repetition of the adjustment
procedure may be necessarv

(7)--+------1~----r_{) +15V

SWEEPING GENERATOR
IOka

N:

-----,
I

;t;v:

TRANSISTORS \
FROM
I

~AR3ROAB'(6

loon

AM

I

IL ______________
3
JI

TRIANGLE
SAWTOOTH

"LOG"

Fig. 24 - Sweeping generator.

establish the upper frequency limit, set the
Frequency Adjustment Potentiometer to its
upper end and then adjust the Maximum
Frequency Calibration Control for the maximum frequency.
Because there is interaction among these controls, repetition of

the adjustment procedure may be necesary.
Two adjustments are used for the meter.
The meter sensitivity control sets the meterscale width of each decade, while the meter
position control adjusts the pointer on the
scale with negligible effect on the sensitivity
adjustment. Thus, the meter sensitivity ad-

justment control calibrates the meter so
that it deflects 1. 6 of full scale for each decade change in frequency.
SINE-WAVE SHAPER

The circuit shown in Fig. 23 uses a CA3140
as a voltage follower in combination with
diodes from the CA3019 Array to convert
the triangular signal from the function generator to a sine-wave output signal having typically less than 2% THO. The basic zerocrossing slope is established by the 10-kQ

Fig. 24 shows a sweeping generator. Three
CA3140's are used in this circuit. One
CA3140 is used as an integrator, a second
device is used as a hysteresis switch that
determines the starting and stopping points
of the sweep. A third CA3140 is used as a
logarithmic shaping network for the log
function. Rates and slopes, as well as sawtooth, triangle, and logarithmic sweeps are
generated by this circuit.

WIDEBANO OUTPUT AMPLIFIER

Fig. 25 shows a high-slew-rate, wide band amplifier suitable for use as a 50-ohm transmission-line driver. This circuit, when used
in conjunction with the function generator
and sine-wave shaper circuits shown in Figs.
21 and 23 provides 18 volts peak-to-peak
output open-circuited, or 9 volts peak-to-peak
output when terminated in 50 ohms. The
slew rate required of this amplifier is 28
volts/J1s (18 volts peak-to-peak x 1T x 0.5
MHz).

_____________________________________________________________ 237

CA3140, CA3140A, CA3140B Types
+1!5V

In spite of those limitations, the current
limiting point can easily be adjusted over
the range from 1 0 mA to 1 ampere with a
single adjustment potentiometer.
If the
temperature stability of the current-limiting
"FOLDBACK"
CURRENT
LIMITER

-15 V

NOMINAL BANDWIDTH' 10 MHI
tr= 35 ns

Fig. 25 - Wideband output amplifier.

POWER SUPPLIES
High input-impedance, common-mode capability down to the negative supply and high
output-drive current capability are key factors in the design of wide-range output-voltage supplies that use a single input voltage
to provide a regulated output voltage that
can be adjusted from essentially 0 to 24 volts_
Unlike many regulator systems using comparators having a bipolar transistor-input
stage, a high-impedance reference-voltage divider from a single supply can be used in connection with the CA3140 (see Fig. 26).

HUM AND NOISE OUTPUT

< 200 iJ.V RMS
(MEASUREMENT BANDWIDTH -10 MHz)
LINE REGULATION

LOAD REGULATION
(NO LOAD TO FULL LOAD)
< 002-/0

O.I%/VOLT

Fig. 28 - Regulated power supply with
"foldback" current limiting.

HUM AND NOISE OUTPUT

(200 IJ-V RMS
(MEASUREMENT BANDWIDTH -10 MHz)
LINE REGULATION

LOAD REGULATION
(NO LOAD TO FULL lOAD)

<0,02%

D_I"o/VOlT

Fig. 27 - Regulated power supply.
showing voltage-follower configuration.

Essentially, the regulators, shown in Figs.
27 and 28, are connected as non-inverting
power operational amplifiers with a gain of
3.2.
An 8-volt reference input yields a
maximum output voltage slightly greater
than 25 volts. As a voltage follower, when
the reference input goes to 0 volts the
output will be 0 volts. Because the offset voltage is also multiplied by the 3.2
gain factor, a potentiometer is needed to
null the offset Voltage.
Series pass transistors with high ICBO levels
will also prevent the output voltage from
reaching zero because there is a finite voltage
drop (VCpat) across the output of the
CA3140 (see Fig.13). This saturation voltage level may indeed set the lowest voltage obtainable.
The high impedance presented by terminal
8 is advantageous in effecting current limiting. Thus, only a small signal transistor is

la)
SUPPLY TURN-ON AND TURN-OFF
CHARACTERISTICS
(5 VOLTS IDIV AND -I s/DIV.J
nCS-27eS2

Fig. 26 - Basic single·supply voltage regulator

required for the current-limit sensing amplifier. Resistive decoupling is provided for
this transistor to minimize damage to it or
the CA3140 in the event of unusual input or
output transients on the supply-rail.
Figs. 27 and 28, show circuits in which a
D2201 high-speed diode is used for the
current sensor. This diode was chosen for its
slightly higher forward-voltage drop characteristic thus giving greater sensitivity. It must
be emphasized that heat sinking of this
diode is essential to minimize variation of the
current trip point due to internal heating of
the diode. That is, 1 ampere at 1 volt
forward drop represents one watt which
can result in significant regenerative changes
in the current trip point as the diode temperature rises. Placing the small-signal reference amplifier in the proximity of the current-sensing diode also helps minimize the
variability in the trip level due to the negative temperature coefficient of the diode.

Ib)
TRANSIENT RESPONSE
TOP TRACE; OUTPUT VOLTAGE
(200 mY/DIY AND 5~'/OIY)

BOTTOM TRACE: COLLECTOR OF LOAD
SWITCHING TRANSISTOR,
LOAD' I AMPERE
(5 YOLTS/OIY AND5~'/OIYI

Fig. 29 - Waveforms of dynamic characteristics
of power supply currents shown
in Figs. 29 and 30.

238 ____________________________________________________________________

CA3140, CA3140A, CA3140B Types
system is a serious consideration, the more
usual current-sam pi ing resistor-type of circuitry should be employed.

FOR SINGLE SUPPLY
20 dB FLAT POSITION GAIN
± I!I dB BASS AND TREBLE BOOST AND

+30 "

CUT AT 100 Hz AND 10 kHz, RESPECTIVELY
25 VOLTS p.p OUTPUT AT 20 kHz
- 3 d8 AT 24 kHz FROM I kHz REFERENCE

A power Darlington transistor (in a heat
sink TO-3 case), is used as the series-pass
element for the conventional current·limiting
system, Fig. 27, because high-power Darlington dissipation will be encountered at
low output voltage and high currents.

FOR DUAL SUPPLIES

+15

A small heat-sink VERSAWATT transistor is
used as the series·pass element in the foldback current system, Fig.28, since dissipation levels will only approach 10 watts.
In this system, the D2201 diode is used for
current sampling. Foldback is provided by
the 3 k!1 and 100 k!1 divider network connected to the base of the current·sensing
transistor.

v

2.2 MQ

,,,
,
~

'Both regulators, Figs. 27 and 28, provide
better than 0.02% load regulation. Because
there is constant loop gain at all voltage settings, the regulation also remains constant.
Line regulation is 0.1% per volt. Hum and
noise voltage is less than 200 JlV as read
with a meter having a 10·MHz bandwidth.
Fig.31 (a) shows the turn ON and turn OFF
characteristics of both regulators. The slow
turn-on rise is due to the slow rate of rise
of the reference voltage. Fig. 29 (b) shows
the transient response of the regulator with
the switching of a 20-!1load at 20 volts output.

.

___T2~E_ ~0.!4!~~L_ f!E}!'E~K___ J

Fig. 30 - Tone control circuit using C43130 series

(20·dB midband gain I.

lator output. A FET channel resistance, a
thermistor, a lamp bulb, or other device
whose resistance is made to increase as the
output amplitude is increased are a few of
the elements often utilized.
C2

.tIS dB BASS AND TREBLE BOOST
AND CUT AT 100 Hz AND 10 kHZ,

51 kn
I

5 Mn 51 kO
(LINEAR)

BOOST TREBLE CUT

RESPECTIVELY.
25 VOLTS p-p ouTPUT AT 20 kHz.
: R~FdEBR:~C~O kHz FROM 1kHz

OUTPUT

~~~E_C~~_N5!,,!~~j 0 dB FLAT POSITION GAIN.
CI

fOR DUAL SUPPLIES

TONE CONTROL CIRCUITS
High-slew-rate, wide-bandwidth, high·output
voltage capability and high input impedance
are all characteristics required of tone-con'
trol amplifiers. Two tone control circuits
that exploit these characteristics of the
CA3140 are shown in Figs. 30 and 31.
The first circuit, shown in Fig. 31, is the
Baxandall tone-control circuit.which provides
unity gain at midband and uses standard
linear potentiometers. The high input impedance of the CA3140 makes possible the
use of low-cost, low-value, small·size capacitors, as well as reduced load of the driving
stage.
·Bass treble boost and cut are ± 15 dB at
100 Hz and 10 kHz, respectively.
Full
peak-to-peak output is available up to at
least 20 kHz due to the high slew rate of the
CA3140. The amplifier gain is -3 dB down
from its "flat" position at 70 kHz.
Fig. 30 shows another tone-control circuit
with similar boost and cut specifications.
The wideband gain of this circuit is equal to
the ultimate boost or cut plus one, which in
this case is a gain of eleven. For 20-dB
boost and cut, the input loading of this cir·
cuit is essentially equal to the value of the
resistance from terminal No.3 to ground.
A detailed analy~is of this circuit is given in
"An IC Operational Transconductance Amplifier (OTA) With Power Capability" by
L, Kaplan and H. Wittlinger, IEEE "Transactions on Broadcast and Television Receivers, Vol. BTR-18, No.3, August, 1972.

Fig. 31 - Baxandall tone contra! circuit using
CA3140series.

WIEN BRIDGE OSCILLATOR
Another application of the CA3140 that
makes excellent use of its high input-impedance, high·slew-rate, and high-voltage qualities is the Wien Bridge sine-wave oscillator.
A basic Wi en Bridge oscillator is shown in
Fig. 32. When R1 ; R2; Rand C1 ; C2; C,
the frequency equation reduces to the familiar f ; 1/21T RC and the gain requirerl for
oscillation, AOSC is equal to 3. Note that
if C2 is increased by a factor of four and R2
is reduced by a factor of four, the gain reo
quired for oscillation becomes 1.5, thus permitting a potentially higher operating frequency closer to the gain·bandwidth pro·
duct of the CA3140.
Oscillator stabilization takes on many forms.
It must be precisely set, otherwise the amplitude will either diminish or reach some
form of limiting with high levels of distor·
tion. The element, R s , is commonly reo
placed with some variable resistance element.
Thus, through some control means, the value
of Rs is adjusted to maintain constant ascii·

R.

Fig. 32 - Basic Wien bridge oscillator circuit
using an operational amplifier.

Fig. 33 shows another means of stabilizing
the oscillator with a zener diode shunting
the feedback resistor (Rf of Fig. 32). As
the output signal amplitude increases, the
zener diode impedance decreases resulting
in more feedback with consequent reduction
in gain; thus stabilizing the amplitude of the
. output signal. Furthermore, this combina·
tion of a monolithic zener diode and bridge
rectifier circuit tends to provide a zero tern·
perature coefficient for this regulating sys·
tern. Because this bridge rectifier system
has no time constant, i.e., thermal time constant for the lamp bulb, and RC time constant for filters often used in detector net·
works, there is no lower frequency limit.
For example, with 1'/lF polycarbonate capacitors and 22 M!1 for the frequency determining network, the operating frequency is
0.007 Hz.
As the frequency is increased, the output
amplitude must be reduced to prevent the
output signal from becoming slew-rate limited. An output frequency of 180 kHz will
reach a slew ra-te of approximately 9 volts/
Jls when its amplitude is 16 volts peak-topeak.

__________________________________________________________________ 239

CA3140, CA3140A, CA3140B Types
will decrease to 0.085 J).V lJ).s, but the slew rate
would decrease to 0.25 V/J).s. The parallel
diode network connected between terminal
3 of the CA3080A and terminal 6 of the
CA3140 prevents large input·signal feed·
through across the input terminals of the
CA3080A to the 200 pF storage capacitor
when the CA3080A is strobed off. Fig. 35
shows dynamic characteristic waveforms of
this sample·and-hold system.

,--------,--<) ~UJ~~ TO 22 II p-p
THO < D.! %

RI

R."RzaR

L-,-o.,--,----r=====-=:!

Igg~~: ~: U~~

3.6 Ul

IOkHz",R- 16kQ
30 kHz, R-S.I rd1

5000

I kHz, R

~

160 kG

Fig. 33 - Wien bridge oscillator circuit using
CA3140 series.

The dotted components show a method of
decoupling the circuit from the effects of
high output-load capacitance and the poten·
tial oscillation in this situation. Essentially,
the necessary high·frequency feedback is
provided by the capacitor with the dotted
series resistor providing load decoupling.

SIMPLE SAMPLE-AND-HOLD SYSTEM

Fig_ 34 shows a very simple sample-and-hold
system using the CA3140 as the readout
amplifier for the storage capacitor. The
CA3080A serves as both input buffer amplifier and low feed·through transmission
switch.' System offset nulling is accomplished with the CA3140 via its offset
nulling terminals. A typical simulated load
of 2 kQ and 30 pF is shown in the schematic.

CURRENT AMPLIFIER
The low input-terminal current needed to
drive the CA3140 makes it ideal for use in
current-amplifier applications such as the one
shown in Fig. 36.- I n this circuit, low cur·
rent is supplied at the input potential as the
power supply to load resistor R L. This load
current is increased by the multiplication
factor R 2/R 1, when the load current is
monitored by the power supply meter M.
Thus, if ·the load current is 100 nA, with
values shown, the load current presented
to the supply will be 100 J).A; a much easier
current to measure in many systems.
Note that the input and output voltages are
transferred at the same potential and only
the output current is multiplied by the
scale factor.

{50 mV/DIV. AND 200nsl DIY. I
BOTTOM TRACE INPUT
(50 mV/DIV. AND 200 nsl DI V.I

I n this circuit, the storage compensation
capacitance (Cl) is only 200 pF. Larger
value capacitors provide longer "hold" periods
but with slower slew rates. The slew rate
dv
i
dt
0.5 mA/200 pF
2.5 V/J).s.

=7=

=

Fig. 36 - Basic Current amplifier for low-current
measurement systems.

• ICAN-6668 "Applications of the CA3080
and CA3080A High-Performance Oper·
ational Transconductance Amplifiers".
LARGE-SIGNAL RESPONSE

°l
-15

n

UU

AND

SETTLING TIME

rSAMPlE

TOP TRACE: OUTPUT SIGNAL
HOLD

(5 V/DI'o'. ANO 2,u.s/DIV.J

BOTTOM TRACE: INPUT SIGNAL
15V/01V. AND 21-'$/0IV.1

30 kil

CENTER TRACE'.DIFFERENCE OF INPUT AND OUTPUT
SIGNALS THROUGH TEKTRONIX
AMPLIFIER 7AI3
(5mV IDIV. AND 2,..s/D IV.)

,.
kO

O.lJotF

- "Operational Amplifiers Design and Ap·
plications", J. G. Graeme, McGraw-Hili
Book Company, page 308 - "Negative
I mmittance Converter Circuits".

+-·---T----:r

~h~u~~~5PR~gAO -1~

Fig. 37 shows a single·supply, absolute-value,
ideal full-wave rectifier with associated waveforms. During positive excursions, the input
signal is fed through the feedback network
directly to the output. Simultaneously, the
positive excursion of the input signal also
drives the output terminal (No.6) of the inverting amplifier in a negative·going excur·
sion such that the,IN914 diode effectively
disconnects the amplifier from the signal
path. During a negative·going excursion of
the input signal, the CA3140 functions as a
normal inverting amplifier with a gain equal
to -R2/R1. When the equality of the two
equations shown in Fig. 37 is satisfied, the
full·wave output is symmetrical.

pF -

Fig. 34 - Sample- and hold circuit.
SAMPLING RESPONSE
TOP TRACE: SYSTEM OUTPUT
(IOOmV/DIV. AND 500 ns/DIV·)

Pulse "droop" during the hold interval is
170 pA/200 pF which is = 0.85 ,.NIJ).s;
(i.e., 170 pA/200 pF). In this case, 170 pA
represents the typical leakage current of
the CA3080A when strobed off. If C 1 were
increased to 2000 pF. the "hold-droop" rate

BOTTOM TRACE

SAMPLING SIGNAL
(20 V IDIV. AND 500 n51 OIv.1
g2CS-2788!l

Fig. 35 - Sample- and hold system dynamic
characteristics waveforms_

240 __________________________________________________________________

CA3140, CA3140A, CA3140B Types

Rj. HI

.!ijf.x R,+~h'li
(~ ~ ~2)

fOR ~·o~
R3 ·KHn
20 v p-p INPUT

I~:~'*

(°07;') ·,~~n

92CS-27887RI

eWI-3dB)'290 Hil. DC QU1PUr (11'1(;1-32 "

Fig. 37 - Single-supply. absolute-value, ideal full-wave rectifier with associated waveforms.

SIMULATED
LOAD

>-.,.--"

, >

IOOPFt~*
, ,
l..,..J

--:::TOP TRACE .OUTPUT
(50 mV IDIV AND 200 ns/DI 'II

BWI-3dB)'4.5 MHz

SR'9

VI,..,

0051'F

92CS-27818

BOTTOM TRACE: INPUT
(50 m'llDIVAND 200 nsf DIV)
(01 SMALL- SIGNAL RESPONSE

(50mV/DIV AND 200nS/DIV)

TOP TRACE :OUTPUT SIGNAL
(5 VlDIV. AND 5f1.s/DIV.)
CENTER TRACE: DIFFERENCE SIGNAL
15m VlDIY· AND 5~$/OIY.)
BOTTOM TRACE '. INPUT SIGNAL
\5V1DIY. AND 511-s/DIYI
{blINPUT- OUTPUT DIFFERENCE SIGNAL
SHOWING SETTLING TIME (MEASUREMENT
MADE WITH TEKTRONIX 1AI3 DIFFERENTIAL
AMPLIFIER)

92CS-278BO

Fig. 38 - Splir·supply voltage4ollower test circuit and associated waveforms.

l

+ 15\1

54-62

11.372-1

BW(-3dB)- 140 kHz
TOTAL NOISE VOLTAGE (REFERRED

~141

Ikn

TO INPUT}-46 ~v TYP.

92CS-HeBe

Fig. 39 - rest circuit amplifier (30·dB gain) used
for wideband noise measurement.

CA3140H Chip

The photographs and dimensions represent
a chip when it is part of the wafer. When the
wafer is cut into chips, the cfeavage angles
are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated
chip is actuallv 7 mils (0.17 mm) larger
in both dimensions.

Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10- 3 inch).

_______________________________________________________________________ 241

CA3141E
Applications:

High-Voltage Diode Array
For Commercial, Industrial, and Military Applications

• Balanced modulators or demodulators

Features:

• Analog switches
• High-voltage diode gates
• Current ratio detectors

• Matched monolithic construction - V F for each diode pair
matched to within 0_55 mV (typ.) at IF = 1 rnA
92CS-27173

• Low diode capacitance - 0.3 pF .(typ.) at VR = 2 V
• High diode-to-substrate breakdown 'voltage - 30 V (min.)

Fig. 1 - Terminal BGSignment.

• Low reverse (leakage) current - 100 nA (max.)
The RCA-CA3141E High-Voltage Diode Array consists of ten general-purpose highreverse-breakdown diodes. Six diodes are
internally connected to form three commoncathode diode pairs, and the remaining four
diodes are internally connected to form two
common-anode diode pairs. Integrated .cir·
cuit construction assures excellent static' and
dynamic matching of the diodes, making the
CA3141 E extremely useful for a wide variety
of applications in communications and
switching systems.
The CA3141 E is supplied in the 16·lead
dual-in-line plastic package (E suffix), and in
chip form (H suffix).
ELECTRICAL CHARACTERISTICS at T A

MAXIMUM RATINGS, Absolute Maximum Values
PEAK INVERSE VOLTAGE IPIV) .
PEAK DIODE-TO-SUBSTRATE VOLTAGE
PEAK FORWARD SURGE CURRENT [IF (SURGE))
DC FORWARD CURRENT (I F)
DISSIPATION:
Anv one diode unit.
Total Package:
Up to 55°C . •
For TA
55°C
AMBIENT TEMPERATURE RANGE:
Operating
• • • • •
Storage • • • • • .
LEAD TEMPERATURE (During Soldering):
At distance 1/16± 1/32 inch (1.59 ±O.79 mm) from esse for 10. ma ••

>

I

IF (Anode)
DC Forward Voltage Drop, VF

100llA
1 rnA
lOrnA

Min.

-

LIMITS
Typ. Max.

UNIT

-

0.7
0.78
0.93

0.9
1
1.2

V

30

50

-

V

DC Breakdown Voltage Between
Any Diode and Substrate,

IDI=lOIlA

30

50

-

V

..
"~
..!Z

0.8

-55 to +125°C
-65 to +150oC
•

• +265°C

Q

0.6

20V

-

-

100

nA

VOl = 20 V

-

-

100

nA

Magnitude of Diode Offset
Voltage Between Diode Pairs

VOl - 20 V
IFA = 1 rnA

-

0.55

-

mV

Temperature Coefficient of
Forward Voltage Drop,
tNF/!J.T

IF = 1 rnA

-

-1.5

-

mV/oC

Reverse Recovery Time, trr

IF=2mA,IR=2mA

-

50

-

!

I

!! II

r--

I-'"

I

I--

r--I--P

0.4'

I

~

~ d .•

I!.

0

0.1

DC Reverse (Leakage) Current
Between Any Diode and
Substrate, 101

2

•

2 4 ••

2

4'8

4 ••

I
10
10 2
F'ORWatD CURRENT (.I.,)- pA

10'

2

46.

10<

,aCS-I?I?

Fig. 2 - DC forward volt8ge drop "'forward current.

ns

Diode Capacitance, CD

See Fig. 5

pF

Diode Anode-to-Substrate
Capacitance, COAl

See Fig. 6

pF

Diode Cathode-to-Substrate
Capacitance, CDCI

See Fig. 7

pF

Magnitude of Cathode-to-Anode
Current Ratio, IIFC/IFAI

I

I

~

IF=-10,uA

VF -

• • • • • • • 650mW
Derate linearly Bt 6.67 mW/oC

A"Tr TEMPERATURE ITA I· •• ·c

>
~

t;

DC Reverse Breakdown
Voltage, V(BR)R

V(BR)OI
DC Reverse (Leakage) Current,lR

50mW

=25°C

TEST
CONDITIONS

CHARACTERISTIC

30 V
30 V
100mA
25mA

Fig. 3 - OC forward volt8ge drop VI.

ambient temperature.

IFA=l mA,VDS=10V

0.9

0.96

-

242 ______________________________________________________

~----------

CA3141E

•
~ 2.5

I
~ 2

AMBIENT TEMPERATURE (TA)-2S-C

IVFl-VF2I.IV,.-VF.I. ~,,-VF61
IVF7-VFal'IVF9-V'OI

~

g
I-

iii

'"

.~ ,
Q

~

1I

a"
a

2 .. 68

2.

10

468

10 2

Z

.6. . 6.
Z

la'

104

2

.. 68

IO!!

MAGNITUDE OF ANODE CURRENT (IFAI-,.A

6
CATHODE-to-ANODE DC REVERSE VOLTAGE (VR)-V

92C$-27176

Fig. 4 - Diode offset voltage vs. magnitude of

anode current.

7

10

ANOD[-TO-SUBSTRATE DC REVERSE VOLTAGE (Vw-V

92CS-27177

92C5-27178

Fig. 6 - Diode anode-ta-substrate capacitance
vs, reverse voltage.

Fig. 5 - Diode capacitance liS. cathode-toanode reverse voltage.

'0

~
2

~I04~
~ 2r---

.

DIODE -TO- SUBSTRATE
LEAKAGE CURRENT

ZIO]

..

6

~

~

U lO2
..

•
10

u
Q

0.01 2

4 680.1

2

4 68 I

Z

4 681'0

Z

4 6

e

FORWARD IANODEI CURRENT U:F 1- mA

1/

2

3
,

,

l'y V

2

6

o
~

a.'

V

V

:

.
2

6

2

-'00

-

..... ~

JL: V

K

DIODE REVERSE

(LEAKAGDCURRENT

'00

50
AMBIENT TEMPERATURE ITAI--C

150

CATHODE-TO- SUBSTRATE DC REVERSE VOLTAGE (VRI-V
92C$-27179

Fig. 7 - Diode cathode-ta-substrate capacitance liS.
cathode-ta-substrate DC reverse voltage.

Fig. 8 - Forward (cathode) current vs. forward
(anode) current

Fig. 9 - DC leakage current vs. ambient
temperature.

----------------__________________________________________________ 243

CA3160, CA3160A, CA3160B Types

BiMOS Operational Amplifiers
With MOS/FET Input, COS/MaS Output
The RCA-CA3160T, CA3160S, CA3160E;
CA3160AT, CA3160AS, CA3160AE; and
CA3160BT, CA3160BS are integrated-circuit operational amplifiers that combine the
advantages of both COS/MOS and bipolar
transistors on a monolithic chip_ The CA3160
series circuits are frequency-compensated
versions of the popular CA3130 series.
Gate-protected p·channel MOS/FET (PMOS)
transistors are used in the input circuit to
provide very·high·input impedance, very-Iowinput Current, and exceptional speed per·
formance. The use of PMOS field·effect
transistors in the input stage results in
common-mode input-voltage capability down

to 0.5 volt below the negative-supply terminal, an important attribute in single-supply
applications.
A complementary-symmetry MOS (COSI
MOS) transistor'pair, capable of swinging
the output voltage to within 10 millivolts
of either supply-voltage terminal (at very
high values of load impedance), is employed
as the output circuit.
The CA3160 Series circuits operate at supply
voltages ranging from 5 to 16 volts, or +2.5
to +8 volts when using split supplies, and have
terminals for adjustment of offset voltage
for applications requiring offset·null capa·

Features:
• Similar to CA3130 but has internal compensation
• MOS/FET input stage provides:
very high 21 = 1.5 Tn (1.5 x 10 12 n) typo
very low II = 5 pA typo at 15·V operation
2 pA typo at 5·V operation
• Common-mode input·voltage range includes
negative supply rail; input terminals can
Ideal for
be swung 0.5 V below negative supply rail
\ single-supply
applications
• COS/MOS output stage permits signal swing
to either (or both) supply rails

bility. Terminal provisions are also made to
permit strobing of the output stage.
The CA3160 series is supplied in standard
8·lead TO·5-style packages (T suffix) and
8·lead dual-in-line formed-lead TO-5 style
"D I L-CAN" packages (S suffix). The CA3160
is available in chip form (H suffix!.
The CA3160A and CA3160 are also available
in the 8-lead dual-in·line plastic package
(Mini-DIP-E suffix). All types operate over
the full military-temperature range of _55°C
to +125°C. The CA3160B is intended for
applications requiring preminium-grade speci·
fications and with limits established for:
input current, temperature coefficient of
input-offset voltage, and gain over the range
of _55°C to +125°C. The CA3160A offers
superior input characteristics over those of
the CA3160.

•
•
•
•
•
•

Applications:
•
•
•
•
•
•

•

•
•
•

,-----,
,- I
I I
BIAS CIRCUIT

- - - - - - -...,

CURRENT SOURCE FOR QS AND 07

I

CI"CU;';E-;T:-;O;;;;C~

7

Low VIO: 2 mV max. (CA3160B)
Wide BW: 4 MHz typo (unity·gain crossover)
High SR: 10 V/MS typo (unity·gain follower)
High output current (10): 20 mA typo
High AOL: 320,000 (110 dB) typo
Internal phase compensation for unity gain
(With terminal access for supplementary external phase compensation network if desired)

Ground-referenced single·supply amplifiers
Fast sample-hold amplifiers
Long-duration timers/monostables
Ideal interface with digital COS/MOS
High-input-impedance wideband amplifiers
Voltage followers
(e.g., follower for single-supply D/A
converter)
Voltage regulators
(permits control of output voltage
down to zero volts)
Wien-Bridge oscillators
Voltage-controlled oscillators
Photo-diode sensor amplifiers

v+

LOAD" FOR all

I

I
I

SUPPLEMENTARY
COMPENSATION

I
I
I

TOP VIEW

Sand T Suffixes

TOP VIEW

E Suffix
NOTE

DIODES 05 THROUGH 08 PROVltJE GATE -OXIDE PROTECTION
FOR MOS/FET INPUT STAGE

Fig. 1- Schematic diagram of the CA3160 Series.

CA3160 Series devices have an on-chip frequencycompensation network. Supplementary phasecompensation or frequency roll-off (if desired) can
be connected externally between terminals 1 and 8.
Fig.2 - Functional diagrams of the CA3160 Series.

244 ____________________________________________________________________

CA3160, CA3160A, CA3160B Types
MAXIMUM RATINGS, Absolute·Maximum Values
DC SUPPLY VOLTAGE
(Between V+ and V- Terminals) ..
16 V
DIFFERENTIAL·MODE
INPUTVOLTAGE .............. .
±8 V
COMMON·MODE DC
INPUT VOLTAGE ... IV+ +8 VI to IV- -0.5 VI
INPUT·TERMINAL CURRE~IT
1 mA
DEVICE DISSIPATION:
WITHOUT HEAT SINKUP TO 55°C. . . . . . . . . . . . . . . . . .. 630 mW
ABOVE 55°C, ... Derate linearly 6.67 mW/oC
WITH HEAT SINK AT 125°C.......... . .......... 418 mW
BELOW 125°C ... Derate linearly 16.7 mW/oC

CIRCUIT DESCRIPTION

TEMPERATURE RANGE:
OPERATING IAII Types).
-55 to +125°C
STORAGE IAII Typesl ...
-65 to +150oC
OUTPUT SHORT·CIRCUIT
DURATION* .......... .
... INDEFINITE
LEAD TEMPERATUR E
lOURING SOLDERINGI:
AT DISTANCE 1/16± 1/32 INCH
11.59 ± 0.79 MMI FROM CASE
FOR10SECONDSMAX ....
.... +265°C

*Short circuit may be applied to ground or to either
supply.

ELECTRICAL CHARACTERISTICS at TA=25 0 C, V+=15 V, V- = 0 V (Unless otherwise specified)
CA3160B (T, S)

CHARACTERISTIC

Min.

LIMITS
CA3160A (T, S, E)

Typ.

Max.

Min.

Typ.

CA3160 (T, S, E)

Max. Min.

Typ.

Max.

Units

Input Offset Voltage,
IVloI, V±=±7.5 V

-

0.8

2

-

2

5

-

6

15

mV

Input Offset Current,
11101, V±=±7.5 V

-

0.5

10

-

0.5

20

-

0.5

30

pA

Input Current, I I
V±=±7.5 V

-

5

20

-

5

30

-

5

50

pA

-

V/V

320 k

-

50 k

320 k

-

50 k

320 k

110

-

94

110

-

94

110

-

dB

86

100

-

80

95

-

70

90

-

dB

0

-0.5
to
12

10

0

-0.5
to
12

10

0

-0.5
to
12

10

V

32

100

-

32

150

-

32

320

pV/V

13.3
0.002

-

12

001

-

100 k
Large·Signal Voltage
Gain, AOL
VO=10Vp.p, RL=2k12 100
Common· Mode
Rejection Ratio,CM R R
Common·Mode Input·
Voltage Range, VICR
Power·Supply Rejection
Ratio, teN 1011W±
V±=±7.5 V

-

Maximum Output
Voltage:
At R L=2 kl2

VOM
VO M

+

12

-

13.3
0.002 0.01

12

-

13.3
0.002 0.01

VO M + 14.99
VOM
Maximum Output
Current:
10M + (Source) @
12
Vo = 0 V

15
0

-

14.99

0.01

22

45

10M- (Sink) @
VO=15V

12

20

45

12

20

45

12

20

45

-

10

15

15

15

2

3

-

10

3

2

3

Flg.ll

15

-

10

2

Flg.l1

-

Input Offset Voltage
Temp. Drift,
6VIOIl',T'

-

5

15

-

6

-

-

Large·Signal Voltage

50 k

320 k

94

110

-

-

-

-

At R L= =

Supply Current, I
VO=7.5V,RL==
VO=OV,R L ==
Input Current, II'

Gain, AOL

0.01

14.99

-

15
0

12

22

45

-

-

15
0

0.01

12

22

45

V

mA

nA

Fig.ll

320 k
110

mA

8

-

320 k
110

pV/oC

V/V

-

dB

Fig.3 is a block diagram of the CA3160
series COS/MOS Operational Amplifiers. The
input terminals may be operated down to
0.5 V below the negative supply rail, and
the output can be swung very close to
either supply rail in many applications. Can·
sequently, the CA3160 series circuits are ideal
for single·supply operation. Three class A
amplifier stages, having the individual gain
capability and current consumption shown
in F ig.3, provide the total gain of the CA3160.
A biasing circuit provides two potentials for
common use in the first and second stages.
Terminals 8 and 1 can be used to supplement
the internal phase compensation network if
additional phase compensation or frequency
roll·off is desired. Terminals 8 and 4 can also
be used to strobe the output stage into a low
quiescent current state. When Terminal 8 is
tied to the negative supply rail (Terminal 41
by mechanical or electrical means, the out·
put potential at Terminal 6 essentially rises
to the positive supply·rail potential at Ter·
minal 7. This condition of essentially zero
current drain in the output stage under the
strobed "OFF" condition can only be a·
chieved when the ohmic load resistance presented to the amplifier is very high (e.g.,
when the amplifier output is used to drive
COS/MOS digital circuits in comparator
applications) .
Input Stages - The circuit of the CA316U is
shown in Fig.l. It consists of a differential·
input stage using PMOS field·effect tran·
sistors (06, 07) working into a mirror'pair
of bipolar transistors (09, 010) functioning
as load resistors together with resistors R3
through R6. The mirror'pair transistors also
function as a differential·to·single·ended can·
verter to provide base drive to the second·
stage bipolar transistor (011). Offset nulling,
when desired, can be effected by connecting
a 100,OOO·ohm potentiometer across Terms.
1 and 5 and the potentiometer slider arm to
Term. 4. Cascode·connected PMOS tran·
sistors 02, 04, are the constant·current source
for the input stage. The biasing circuit for the
constant·current source is subsequently de·
scribed. The small diodes 05 through D7
provide gate·oxide protection against high·
voltage transients, e.g., including static elec·
tricity during handling for 06 and 07.
Second·Stage - Most of the voltage gain in
the CA3160 is provided by the second am·
plifier stage, consisting of bipolar transistor
011 and its cascode·connected load resistance
provided by PMOS transistors 03 and 05.
The source of bias potentials for these PMOS
transistors is described later. Miller Effect
compensation (roll offl is accomplished by
means of the 30·pF capacitor and 2·k12
resistor connected between the base and
collector of transistor 011. These internal
components provide sufficient compensation
for unity gain operation in most applications.
However, additional compensation, if desired,
may be used between Terminals 1 and 8.
Bias·Source Circuit - At total supply volt·
ages, somewhat above 8.3 volts, resistor R2
and zener diode Zl serve to establish a volt·
age of 8.3 volts across the series·connected

__________________________________________________________________ 245

CA3160, CA3160A, CA3160B Types
CIRCUIT DESCRIPTION (cont'd)

TYPICAL VALUES INTENDED ONLY FOR DESIGN GUIDANCE
TEST
CONDITIONS

CHARACTERISTIC

Input Offset Voltage
Adjustment Range

V+=+7.5V
V- = -7.5 V
TA = 25°C
(Unless Other·
wise Specified)

CA3160B
(T, S)

CA3160A
(T,S, E)

CA3160
(T,S, E)

UNITS

10 kQ across
Terms. 4 and 5
or 4 and 1

±22

±22

'±:22

mV

Input Resistance, RI
Input Capacitance, CI

f - 1 MHz

Equivalent Input Noise
Voltage, en

RS=l MQ
BW=
0.2 MHz RS~lOMQ

Equivalent Input Noise
Voltage, en

RS=
100 Q

1 kHz
10 kHz

Unity Gain Crossover

1.5

1.5

1.5

Hl

4.3

4.3

4.3

pF

40
50

40
50

40
50

IN

72
30

72
30

72
30

nVv'HZ

4

4

4

MHz

10

10

10

Vips

0.09

0.09

0.09

ps

10

10

10

%

1.8

1.8

1.8

ps

CA3160B
(T, S)

CA3160A
(T, s, E)

CA3160
(T,S, E)

Frequency, fT
Slew Rate, SR:
Transient Response:
Rise Time, tr

Overshoot
Settling Time 14 V p.p
Input to <0.1 %)

CL = 25 pF
RL=2kSl
IVoltage
Followe, )

TEST
CONDITIONS

CHARACTERISTIC

V+=5 V
V- =OV
TA = 25 0 C
(Unless Other·
wise Specified)

UNITS

1

2

6

mV

Input Offset Current, 110

0.1

0.1

0.1

pA

2

2

2

pA

Common-Mode Rejection
Ratio, CMRR
Large·Signal Voltage

Vo = 4 V p . p

Gain, AOL
Common-Mode Input
Voltage Range, V ICR

R L =5kQ

100

90

80

dB

100 k

100 k

lOOk

VN

100

100

100

dB

o to 2.8

o to 2.8

o to 2.8

V

300

300

300

500

500

500

200

200

200

Vo = 5 V,
Supply Current, 1+

Power Supply Rejection
Ratio,6VI0/6V+

RL ==
"0 - 2.5 V,
RL = 00

Output Stage - The output stage consists of
a drain·loaded inverting amplifier using COSI
MaS transistors operating in the Class A
mode. When operating into very high reo
sistance loads, the output can be swung
within millivolts of either supply rail. Because the output stage is a drain-loaded
amplifier, its gain is dependent upon the
load impedance.
The transfer characteristics of the output stage for a load reo
turned to the negative supply rail are shown
in Fig.6_ Typical op-amp loads are readily
driven by the output stage. Because large·
signal excursions are non-linear, requiring

Input Offset Voltage, VIO
Input Current, II

circuit, consisting of resistor R 1, diodes D 1
through D4, and PMOS transistor Ql. A
tap at the junction of resistor R 1 and diode
04 provides a gate-bias potential of about
4_5 vofts for PMOS transistors Q4 and Q5
with respect to Terminal 7. A potential of
about 2.2 volts is developed across diode·
connected PMOS transistor Ql with respect
to Terminal 7 to provide gate bias for PMOS
transistors Q2 and Q3. It should be noted
that Ql is "mirror·connected"t to both Q2
and Q3. Since transistors Ql, Q2, Q3 are
designed to be identical, the approximately
200-microampere current in Ql establishes
a similar current in Q2 and Q3 as constant·
current sources for both the first and second amplifier stages, respectively.
At total supply voltages somewhat less than
8.3 volts, zener diode Zl becomes non·
conductive and the potential, developed
across series·connected Rl, 01·D4, and Ql,
varies directly with variations in supply
voltage. Consequently, the gate bias for
Q4, Q5 and Q2, Q3 varies in accordance
with supply-voltage variations. This varia·
tion results in deterioration of the power·
supply·rejection ratio (PSRR) at total supply
Operation at
voltages below 8.3 volts.
total supply voltages below about 4.5 volts
results in seriously degraded performance.

feedback for good waveform reproduction,
transient delays may be encountered. As a
voltage follower, the amplifier can achieve
0.01 per cent accuracy levels, including the
negative supply rail.
Offset Nulling
Offset·voltage nulling is usually accomplished
with a 100,000'ohm potentiometer can·
nected across Terminals 1 and 5 and with the
potentiometer slider arm connected to Term·
inal 4. A fine offset-null adjustment usually
can be effected with the slider arm positioned
in the mid·point of the potentiometer's total
range.

pA

t

For general information on the characteristics of

COS/MOS transistor-pairs in linear-circuit appli-

pVN

cations, see File No. 619, data bulletin on
CA3600E "COS/MaS Transistor Array".

246 __________________________________________________________________

CA3160, CA3160A, CA3160B Types
r---------------------I

I

I

200!-'A

I
I
I
I
I

SmA*
OmA#

I

v+
7

I
I
I
I
I

102

10

103

104

106

I'

I'

FREQUENCY If I-H:

OFFSET

92CS·28'38

NULL
TOTAL SUPPLY VOLTAGE {FOR INDICATED VOLTAGE GAINS]

.,~

v

·WITH INPUT TERMINALS BIASED SO THAT TERM 6 POTENTIAL
IS +75V ABOVE TERM 4

92CS-28~7J

Fig.4 - Open-loop voltage gain and phase shift
vs. frequency for various values of CL
and RL.

"WITH OUTPUT TERMINAL DRIVEN TO EITHER SUPPLY RAil

Fig. 3 - Block diagram of the CA3160 Series.

It t

I~ LOAORES1STANCE (Rll'ZkG

~

140

'

Ilil

-<

t~~

-

I

Iii

j

1

'30

~

~

ill

I

I'

120

lor.··;;C··PP~iPP~~F.

3 ::;:

.-

~ 7'r.;:~:·t=F'F-r
110

"~ ,r...

~ 100

~

~4·~···0····+4~$ili~~§Ff4

~

~

~

12'

;

;;c.H~,"":3'.

g

g25

90

'"

-100

-00

o·

I 100

0

AMBIENT TEr.FERATURE (TAl -

Fig.5 - Open·loop gain

VS.

Oc

GATE VOLTAGE (VG I [TERMS 4

temperature.

e

BJ-V

Fig.6 - Voltage transfer characteristics of
COS/MaS output stage.

0.001

TOTAL SUPPLY VOLTAG£ IV+I-v

24',
Z
0,01

41'
0.1

24"

I

Z

4"

10

•

4"

Fig.7 - Ouiescent supply current vs. supply voltage.

100

0.001

Z

MAGNITUOE Of LOAD CURRENT I ILI- mA

Fig.S - Quiescent supply current vs. supply voltage
at several temperatures.

411
24"
001
0I

2

4'1

Z

I

4 &.
10

24&1
100

MAGNITUDE OF LOAO CURRENT IILI- mA
nCS-Z472Z

Fig.9 - Voltage across PMOS output transistor
(aS) vs. load current.

Fig. 10 - Voltage across NMOS output transistor
(Q72) vs. load current.

··
z

100:

L'

~

~

'0,
G

2t=~-+--t=~ft~--t--r~--t-~
2:

"

68

'0

2

,02

"68

2:

4 68

,03

2

FREQUENCY (t}-H~

468

104

2:

468

92CS·Z.a515

Fig. 11 - Equivalent noise voltage vs. frequency.

1/

I

-so

105
INPUT CURRENT U:T 1- pA

Fig. 12 - Input current vs. common-mode voltage.

-60

-40 -20

0

20

40

60

80

100

120

140

AMBIENT TEMPERATURE (TA)-OC

Fig. 13 - Input current vs. ambient temperature.

________________________________________________________________ 247

CA3160, CA3160A, CA3160B Types
Input Current Variation with CommonMode Input Voltage
As shown in the Table of Electrical Characteristics, the input current for the CA3160
Series Op-Amps is typically 5 pA at T A=25 0 C
when Terminals 2 and 3 are at a commonmode potential of +7.5 volts with respect to
negative supply Terminal 4. Fig. 12 contains
data showing the variation of input current
as a function of common-mode input voltage
at T A=25 0 C. These data show that circuit
designers can advantageously exploit these
characteristics to design circuits which typically require an input current of less than 1
pA, provided the common-mode input voltage does not exceed 2 volts. As previously
noted, the input current is essentially the
result of the leakage current through the
gate-protection diodes in the input circuit
and, therefore, a function of the applied
Voltage. Although the finite resistance of the
glass terminal-to·case insulator of the TO-5
package also contributes an increment of
leakage current, there are useful compensating factors. Because the gate-protection network functions as if it is connected to
Terminal 4 potential, and the TO-5 case of
the CA3160 is also internally tied to Terminal4, input terminal 3 is essentially "guarded"
from spurious leakage currents.
Input-Current Variation with Temperature
The input current of the CA3160 Series circuits is typically 5 pA at 25 0 C. The major
portion of this input current is due to leakage
current through the gate-protective diodes in
the input circuit. As with any semiconductorjunction device, including op amps with a
junction-FET input stage, the leakage current approximately doubles for every 100C
increase in temperature. Fig. 13 provides data
on the typical variation of input bias current
as a function of temperature· in the CA3160.
In applications requiring the lowest practical
input curnmt and incremental increases in
current because of "warm-up" effects, it is
suggested that an appropriate heat sink be
used with the CA3160. In addition, when
"sinking" or "sourcing" significant output
curreni the chi p te'mperature increases, causi ng
an increase in the input current. In such
cases, heat-sinking can also very markedly
reduce and stabilize input .current variations.
Input-Offset-Voltage (V IO ) Variation with
DC Bias vs. Device Operating Life
It is well known that the characteristics of a
MOS/FET device can change slightly when a
de gate-source bias potential is applied to the
device for extended time periods. The magnitude of the change is increased at high temperatures. Users of the CA3160 should be alert
to the possible impacts of this effect if the
application of the device involves extended
operation at high temperatures with a significant differential de bias voltage applied
across Terminals 2 and 3. Fig. 14 shows typical data pertinent to shifts in offset voltage
encountered with CA3160 devices in TO-5
packages during life testing. At lower temperatures (TO-5 and plastic) for example at
85°C, this change in voltage is consider-

ably less. In typical linear applications where
the differential voltage is small and symmetrical, these incremental changes are of
about the same magnitude as th ose en·
AMBlE NT TEMPERATURE

f

•

r'
."
~

~
~

(TA).12~·C

Am

IJ

I!

11

1

6

.,

t •,

"~(;\,,

tt~~~~~()

-J>~~"" ",fP.

.

1:\
"

l~ I

~~~"'~i,.~,,~

:

1

,
!

~~$~

DIFFERENTIAL DC VOLTAGE

~AC:::U;EVROMl~A~E8. ~~~ ~

"'"

0

'000

'000

2000

.000

>000

3500 4000

TIME (tl- HOURS

Fig. 14 - Typical incremental offset-voltage shift
vs. operating life.

countered in an operational amplifier em·
ploying a bipolar transistor input stage. The
two-volt dc differential voltage example
represents conditions when the ampl ifier out·
put state is "toggled", e.g., as in comparator
applications.
Power-Supply Considerations
Because the CA3160 is very useful in single·
supply applications, it is pertinent to review
some considerations relating to power·supply
current consumption under both single· and
dual·supply service. Figs. 15(a) and 15(b)
show the CA3160 connected for both dual·
and single-supply operation.

-G
-r
l

POSITIVE

SUPPLY

+

(01

DUAL POWER-SUPPLY OPERATION

{bl SINGLE POWER-SUPPLY OPERATION

Fig. 15 - CA3160 output stage in dual and
single power-supplV operation.

Dual-supply operation: When the output
voltage at Terminal 6 is zero-volts, the cur·
rents supplied by the two power supplies are
equal. When the gate terminals of 08 and

012 are driven increasingly positive with
respect to ground, current flow through 012
(from the negative supply) to the load is in·
creased and current flow through 08 (from
the positive supply) decreases correspondingly. When the gate terminals of 08 and
012 are driven increasingly negative with
respect to ground, current flow through 08
is increased and current flow through 012 is
decreased accordingly .
Single·supply operation: Initially, let it be
assumed that the value of R L is very high
(or disconnected), and that the input·terminal
bias (Terminals 2 and 3) is such that the out·
put terminal (No.6) voltage is at V+/2, i.e.,
the voltage·drops across 08 and 012 are of
equal magnitude. Fig. 7 shows typical quies·
cent supply·current 'Is. supply·voltage for the
CA3160 operated under these conditions.
Since the output stage is operating as a Class
A amplifier, the supply-current will remain
constant under dynamic operating conditions
as long as the transistors are operated in the
linear portion of their voltage-transfer characteristics (see Fig. 6). If either 08 or 012 are
swung out of their linear regions toward cutoff (a non·l.inear region l. there will be a corresponding reduction in supply-current. In
the extreme case, e.g., with Terminal 8 swung
down to ground potential (or tied to ground),
NMOS transistor 012 is completely cut off
and the supply·current to series·connected
transistors 08, 012 goes essentially to zero.
The two preceding stages in the CA3160,
however, continue to draw modest supplycurrent (see the lower curve in Fig. 7) even
though the output stage is strobed off. Fig.
15 (a) shows a dual·supply arrangement for
the output stage that can also be strobed off,
assuming RL==, by pulling the potential of
Terminal 8 down to that of Terminal 4.
Let it now be assumed that a load·resistance
of nominal value (e.g., 2 kilohms) is can·
nected between Terminal 6 and ground in
the circuit of Fig. 15(b). Let it further be
assumed again that the input·terminal bias
(Terminals 2 and 3) is such that the output
terminal (No.6) voltage is a V+ /2. Since
PMOS transistor OB must now supply quiescent current to both R L and transistor 012,
it should be apparent that under these condi·
tions the supply·current must increase as an
inverse function of the R L magnitude. Fig. 9
shows the voltage-drop across PMOS tran·
sistor 08 as a function of load current at
several supply voltages. Fig. 6 shows the
voltage·transfer characteristics of the output
stage for several values of load resistance.
Wideband Noise
From the standpoint of low·noise perform·
ance considerations, the use of the CA3160
is most advantageous in applications where
in the source resistance of the input signal is
in the order of 1 megohm or more. In this
case, the total Input·referred noise. voltage
is typically only 40 flV when the test-circuit
amplifier of F ig.16 is operated at a total
supply voltage of 15 volts. This value of
total input·referred noise remains essentially
constant, even though the value of source
resistance is raised by an order of magnitude.

248 ____________________________________________________________________

CA3160, CA3160A, CA3160B Types
This characteristic is due to the fact that
reactance of the input capacitance becomes a
significant factor in shunting the source
resistance. I t should be noted, however, that
for values of source resistance very much
greater than 1 megohm, the total noise
voltage generated can be dominated by the
thermal noise contributions of both the
feedback and source resistors.

TYPICAL APPLICATIONS
Voltage Followers
Operational amplifiers with very high input
resistances, like the CA3l60, are particularly
suited to service as voltage followers. Fig.17
shows thE: circuit of a classical voltage
follower, together with pertinent waveforms
using the CA3160 in a split·supply config·
uration.
A voltage follower, operated from a single·
supply, is shown in Fig.18 together with
related waveforms. This follower circuit is
linear over a wide dynamic range, as illustrated by the reproduction of the output
waveform in Fig.1Sb with input·signal ramp·
ing. The waveforms in Fig.1Sc show that
the follower does not lose its input·to·
output phase·sense. even though the input is
being swung 7.5 volts below ground poten·
tial. This unique characteristic is an important
attribute in both operational amplifier and
comparator applications. Fig.1Sc also shows
the manner in which the COS/MaS output
stage permits the output signal to swing down
to the negative supply·rail potential li.e.,
ground in the case shown). The digital·to·
analog converter IDAC) circuit, described in
the following section, illustrates the practical
use oi the CA3160 in a single·supply voltage·
follower application.

+7,5 V

BW(-3d8)=200 kHz

Ikfi

TOTAL NOISE VOLTAGE (REFERRED
TO INPUT)=40j1V T,(P

Fig. 16 - Test-circuit amplifier (30-dB gain) used
for wideband noise measurements.

+75 V

10 kn

I
I

2 k.!1

I
I

-75 V

::-'r: 25 pF
-=- CAPACITANCE

.....L SIMULATED LOAD

2

.n

BW(-3dB)=4MHz
SR = 10 V/f-Ls

OJp.F

9-8it COS/MaS DAC
A typical circuit of a 9·bit Digital·to·Analog
Converter IDAC)* is shown in Fig.19. This
system combines the concepts of multiple·
switch COS/MOS IC's, a low·cost ladder
network of discrete metal-ox ide-film resistors, a CA3160 op amp connected as a
follower, and an inexpensive monolithic regu·
lator in a simple single power·supply arrange·
ment. An additional feature of the DAC is
that it is readily interfaced with COS/MaS
input logic, e.g., lO·volt logic levels are used
in the circuit of Fig.19.
The circuit uses an R/2R voltage·ladder net·
work, with the output·potential obtained
directly by terminating the ladder arms at
either the positive or the negative powersupply terminal. Each CD4007A contains
three "inverters", each "inverter" function·
ing as a single·pole double·throw switch to
terminate an arm of the R/2R network at
either the positive or negative power·supply
terminal. The resistor ladder is an assembly
of one per cent tolerance metal·oxide film
resistors. The five arms requiring the highest
accuracy are assembled with series and para·
lIel combinations of S06,000·ohm resistors
from the same manufacturing lot.
A single 15·volt supply provides a positive
bus for the CA3l60 follower amplifier and
feeds the CA30S5 voltage regulator. A
"scale·adjust" function is provided by the
regulator output control, set to a nominal
lO·volt level in this system. The line·voltage
regulation lapproximately 0.2%) permits a
9·bit accuracy to be maintained with varia·
tions of several volts in the supply. The
flexibility afforded by the COS/MaS building
blocks simplifies the design of DAC systems
tailored to particular needs.
Error-Amplifier in Regulated Power Supplies
The CA3160 is an ideal choice for error·
amplifier service in regulated pow"r supplies
since it can function as an error-amplifier
when the regulated output voltage is reo
quired to approach zero.

ra)

The circuit shown in Fig.20 uses a CA3l60
as an error amplifier in a continuously ad·
justable l·ampere power supply. One of the
key features of this circuit is its ability to
regulate down to the vicinity of zero volts
with only one de power supply input.
An RC network, connected between the base
of the output drive transistor and the input
voltage, prevents "turn·on overshoot", a
condition typical of many operational·ampli·
fier regulator circuits. As the amplifier be·
comes operational, this RC network ceases
to have any influence on the regulator per·
formance.
(b) Small Signal Response

Top Trace: Output
Bottom Trace: Input

(e) Input-Output Difference Signal Showing
Settling Time
Top Trace: Output Signal
Center Trace: Difference Signal 5 mV/div
Bottom Trace: Input Signal

Fig. 17 - Split-supplV voltage follower with associated waveforms.

*

"Digital-to-Analog Conversion Using the RCACD4007A COS/MaS IC", Application Note
ICAN·60BO.

______________________________________________________________ 249

CA3160, CA3160A, CA3160B Types

10 k!l

o
(b) Output signal with input-signal
ramping_

92CS-28580

(a)

Fig.1S - Single-supply voltage-follower with associated
waveforms. (e.g., for use in single-supply DIA

converter: see Fig.9 in ICAN·60aO,)

o

o

92CS-28581 R1
(e) Output-Waveform with Ground-Reference

Sine-Wave Input
Top Trace: Output
Bottom Trace: Input

10 V LOGIC INPUTS
I

,

~

2
3
4

5

6-'

REQUIRED
RATIO- MATCH

STANDARD
to.I%

to.2%
to.4%
to.S"!.
tl% ABS.

ALL RESISTANCES IN OHMS

PARA~LELED

B06K

,%

RESISTORS

REGULATED
VOLTAGE
AOJ.

O.OOI",F
3.83K

,%

2K

O.If£F
92CM-28582

Fig. 19 - 9-bit DAC using COS/MOS digital switches and CA3160.

250 __________________________________________________________________

CA3160, CA3160A, CA3160B Types
INPUT
+ 40\1
OUTPUT
ov .. 3!!1V
...T I ..... PERE

0.2,.F
TURN
2.41(0
IW

OH

DELAY

4'",
!!I6pF

...",
HU" AND NOISE OUTPUT'" 250 ".V MIS:
REGULATION (NO LOAD TO FULL LOAD)
<0.005 ,%;
INPUT REGULATION < 0·01 %/V

50."
621(Q

100ICQ

Fig.20 - Voltage regulator circuit (0.1 to 35 Vat 7 A).

Precision Voltage-Controlled Oscillator
The circuit diagram of a precision voltagecontrolled oscillator is shown in Fig.21. The
oscillator operates with a tracking error in the
order of 0.02 percent and a temperature coefficient of O.Ol%/oC.
A multivibrator
(Al) generates pulses of constant amplitude
(V) and width (T21.
Since the output
(terminal 6) of Al (a CA3130) can swing
within about 10 millivolts of either supply·
rail, the output pulse amplitude (V) is
essentially equal to V+. The average output
voltage (Eavg.= V T2/T 1) is applied to the
non-inverting Input terminal of comparator
A2 via an integrating network R3, C2.
Comparator A2 operates to establish circuit
conditions such that Eavg = Vl. This circuit

condition is accomplished by feeding an output signal from terminal 6 of A2 through R4,
D4 to the inverting terminal (terminal 2)
of A 1. thereby adjusting the multivibrator
interval, T3.

signal, the circuit consumes somewhat less
than 500 microamperes plus the meter cur·
rent required to indicate a given voltage.
Thus, at full·scale input, the total supply
current rises to slightly more than 1500
microamperes.

Voltmeter With High Input Resistance
The voltmeter circuit shown in Fig.22 illustrates an application in which a number
of the CA3160 characteristics are exploited.
Range-switch SWl is ganged between input
and output circuitry to permit selection of
the proper output voltage for feedback to
Terminal 2 via 10 Krl current-limiting reo
sistor. The circuit is powered by a single
8.4·volt mercury battery. With zero input

Function Generator
A function generator having a wide tuning
range is shown in Fig.23. The adjustment
range, in excess of 1,000,000/1, is accom·
plished by a single potentiometer. Three
operational amplifiers are utilized: a CA3160
as a voltage follower, a CA3080 as a highspeed comparator, and a second CA3080A
as a programmable current source. Three
variable capacitors C1, C2, and C3 shape
the triangular signal between 500 kHz and
1 MHz. Capacitors C4, C5, and the trimmer
potentiometer in series with C5 maintain
essentially constant (±10%) amplitude up
to 1 MHz.

?

\lCO CONTROL VOLTAGE (Vi)
(O-IOV)

~ (SENsrTIVITY~lkHzIIIOLn

1M

Staircase Generator
Fig.24 shows a staircase generator circuit
utilizing three COS/MaS operational ampli·
fiers. Two CA3130's are used; one as a
multivibrator, the other as a hysteresis switch.
The third amplifier, a CA3160, is used as a
linear staircase generator.

RS
100 K

R6

lOOK

0'
182 K

10.

04
01 - 05

~

IN914

3K

Fig.21 - Voltage-controlled oscillator.

Picoammeter Circuit
Fig. 25 is a current·to·voltage converter con·
figuration utilizing a CA3160 and CA3140
to provide a picoampere meter for ±3 pA full·
scale meter deflection. By placing Terminals
2 and 4 of the CA3160 at ground potential,

___________________________________________________________________ 251

CA3160, CA3160A. CA3160B Types
BATTERY
TEST

[B
OFF

300 V

300V

L

9.9 Kn

.... -

,

ON

r=;::;;,-:;;;;;POSI;;;;;;TION===========:;-i
_...J--:

,--l,J

T-

SLIDE SWITCH

I

BA~V

~

BATTERY

92CM-28585R 1

Fig.22 - High';nput-resistance DC voltmeter.

THRESHOLD
DETECTOR

'on
,on

7. 5V

o---',IlY.1""n-o
MAX.FREQ

+-1. ~ V o-~~TlJvlh-~WIr-.JV)~'-O -7.5 V
I Kn

6.2K'n

2Kn

500n

FREQ
ADJUST

ra)

92(101- Z:858&RI

92CS·28588

(b) - Two-tone output signal from the function

generator. A square-wave signal modulates
the external sweeping input to produce
I Hz and I MHz, showing the 1,000,0001/
frequency range of the function generator.

(c) - Triple-trace of the function generator

sweeping to 1 MHz. The bottom trace
is the sweeping signal and the top trace
is the actual generator output. The
center trace displays the 1 MHz signal
via delayed oscilloscope triggering of
the upper swept output signal.

Fig. 23 - 1,000,000/1 single-control function generator - 1 MHz to 1 Hz.

252 ________________________________________________________________

CA3160, CA3160A, CA3160B Types
'.IKn

IN914

output (Terminal 6) near ground, thus markedly reducing the dissipation by reducing
the supply current to the device.
The CA3140 stage serves as a Xl 00 gain
stage to provide the required plus and minus
output swing for the meter and feedback
network_ A 100-to-' voltage divider network
consisting of a 9.9-KQ resistor in series with
a 100-ohm resistor sets the voltage at the
10-KMQ resistor (in series with Terminal 3) to
±30 mV full-scale deflection. This 30-mV
signal results from ±3 volts appearing at the
top of the voltage divider network which
also drives the meter circuitry.

100
KO

+15mVTO+l0V

fa)

92C5-28596

(b) - Staircase Generator Waveform
Top Trace: Staircase Output
2 Volt Steps
Center Trace: Comparator
Bottom Trace: Oscillator

Fig_ 24 - Staircase generator.

100 len

By utilizing a switching technique in the
meter circuit and in the 9_9 KQ and 100-ohm
network similar to that used in voltmeter
circuit shown in Fig_ 22, a current range of
3 pA to 1 nA full scale can be handled with
the single' 0- KMQ resistor.
Single-Supply Sample-and-Hold System
Fig. 26 shows a single-supply sample-and-hold
system using a CA3160 to provide a high
input impedance and an input-voltage range
of 0 to 10 volts. The output from the input
buffer integrator network is coupled to a
CA3080A_ The CA3080A functions as a
strobeable current source for the CA3140
output integrator and storage capacitor. The
CA3140 was chosen because of its low output impedance and constant gain-bandwidth
product. Pulse "droop" during the hold
interval can be reduced to zero by adjusting
the 100- KQ bias-voltage potentiometer on
the positive input of the CA3080A. This
zero adjustment sets the CA3080A output
voltage at its zero current position. In this
sample-and·hold circuit it is essential that the
amplifier bias current be reduced to zero to
minimize output signal current during the
hold mode. Even with 320 mV at the amplifier bias circuit terminal (5) at least ± 100 pA
of output current will be available.
Wien Bridge Oscillator
A simple, single-supply Wien Bridge oscillator using a CA3160 is shown in Fig. 27.
A pair of parallel-connected 1 N914 diodes
comprise the gain-setting network which
standardizes the output voltage at approximately 1.1 volts. The 500-ohm potentiometer
is adjusted so that the oscillator will always
start and the oscillation will be maintajned.
Increasing the amplitude of the voltage may
lower the threshold level for starting and for
sustaining the oscillation, but will introduce
more distortion.

Fig.25 - Current-to-voltage converter to provide a picoammeter
with ± 3 pA full-scale deflection.

Operation with Output-Stage Power· Booster
The current sourcing and sinking capability
of the CA3160 output stage is easily supplemented to provide power·boost capability.
In the circuit of Fig.28, three COS/MOS
transistor-pairs in a single CA3600 IC array
are shown parallel-connected with the output
stage in the CA3160. In the Class A mode of
CA3600E shown, a typical device consumes

____________________________________________________________________ 253

CA3160, CA3160A, CA3160B Types
+ 15 V

IMn

STROBE INPUT

2 Kn

SAM:~CDI~~

Lr
92CM- 28590

(a)

fe) - Sample-and-hold waveform.

(b) - Sample-and-hold waveform.

Top Trace: Sampled Output
Center Trace: Input
Bottom Trace: Sampling Pulse

Top Trace: Sampled Output
Center Trace: Input Signal
Bottom Trace: Sampling Pulses

Fig. 26 - Single-supply sample-and-hold system-input 0-to-1O volts.

the CA3160 input is operated in the "guarded
mode". Under this operating condition, even
slight leakage resistance present between
Terminals 3 and 2 or between Terminals 3
and 4 would result in zero voltage across this
leakage resistance, thus substantially reducing
the leakage current.

100 kG

If the CA3160 is operated with the same
voltage on input Terminals 3 and 2 as on

100 KO

.,

!5IK.Q

.2

Terminal 4, a further reduction in the input

current to the less than one picoampere level
can be achieved as shown in Fig. 12.
To further enhance the stability of this circuit, the CA3160 can be operated with its
20 mA of supply current at 15·V operation.
This arrangement boosts the current·handling
capability of the CA3160 output stage by
about 2.5X.

L..--------10.01I'F

l,::
92CS - 28$91RI

Fig.27 - Single-supply WI'en Bridge oscillator.

The amplifier circuit in Fig. 28 employs
feedback to establish a closed·loop gain of
20 dB. The typical large·signal·bandwidth
1-3dBI is 190 kHz.

254 __________________________________________________________________

CA3160, CA3160A, CA3160B Types
+I~

V

'"0

H1

IN

"'
1

1--'VVv--1""-{

'"'

.on

500

100 mW

-=- AT

10"'. THO.

A.20 dB
LARGE SIGNAL
awt-3 dB.190 KHz

20 Kn

* SEE

NOTE:

FILE NO. 619

TRANSISTORS pi, p2, p3 AND 111, n2, 113 ARE
PARALLEL-CONNECTED WITH 08 AND 012,
RESPECTIVELY, OF THE CA3160

92CM- 28592

Fig.28 - COS/MaS transistor array (CA3600EJ connected as power
booster in the output stage of the CA3160.

55-63
(1.397-1.6001

t---------11,"676:~~819)--------

J

I

••1

Dimensions in parentheses are in; millimeters and

The photograph and dimensions represent a chip

~~~iC~~;~e~,,~o9n:ad~~i:::~rei7nc~i~·7t;!.17~c~j.

into chips the cleavage angles are 571 instead of

when it is part of the wafer. When the wafer is cut
gOO with respect to the face of the chip. Therefore,

the isolated chip is actually 7 mils (0.17 mm)
larger in both dimensions.

_____________________________________________________________________ 255

CA3161E

BCD-to-Seven-Segment Decoder IDriver
The RCA·CA3161 E is a monolithic inte·
grated circuit that performs the BCD·to·
seven·segment decoding function and features
constant·current segment drivers. When used
with the CA3162E AID Converter* the

Features:

CA3161 E provides a complete digital readout

- TTL·compatible input logic levels

system with a minimum number of external
parts.
* The CA3162E is described in RCA data bulletin

• Eliminates need for output current·limiting resistors

File No. 1080.

- 25-mA (typ.) constant·current segment outputs

- Pin compatible with other industry standard decoders
• Low standby power dissipation - 18 mW (typ.)

MAXIMUM RATINGS, Absolute·Maximum Values:
DC SUPPL Y VOLTAGE (between terminals 1 and 101.
I NPUT VOLTAGE (terminals 1,2,6,71 .
OUTPUT VOLTAGE:

+7 V

+5.5 V
BCD {21
22

I

INPUTS

+7 V
+10 V

Output "Off"

Output "On" (See note 1)
DEVICE DISSIPATION:

NC

: }SEGMENT

NC

b

NC

.

Up to T A = +55°oC
Above T A = +55 C
AMBIENT TEMPERATURE RANGE:
Operating

.

.

.

.

..

lW

derate linearly at 10.5

mwtc

. Oto+7SoC
-65 to +150°C

Storage
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 seconds max.

BCD
INPUTS

{2'

20

GND

v'

3

6

c

.

DRIVER
OUTPUTS

d

92CS'30345RI

TERMINAL ASSIGNMENT
CA3161E

NOTE1: This is the maximum output voltage for any single output. The output voltage must be consistent
with the maximum dissipation and derating curve for worst-case conditions. Example: All segments
"on", 100% duty cycle.

~ fSEG.ENT

CONSTANT
CURRENT
SEG MENT
DRIVERS

DRIVER
OUTPUTS

•

I

•

a '.

,

~SEG"ENT

f~jb

..... l

.j

SEGMENT
IDENTIFICATION
92CM-30346RI

SEGMENT DRIVER

Fig. 1 - Functional block diagram of the CA3161E.
92CM-31009

ELECTRICAL CHARACTERISTICS at T A = 25°C
LIMITS

CHARACTERISTIC

UNITS

Min. Typ. Max.
4.5
5 5.25

Supply Voltage Operating Range, V+
Supply Current, 1+ (all inputs high)

-

V

3.5

8

mA

Output Current Low (V 0

= 2 V)

18

25

32

mA

Output Current High (VO

= 5.5 V)

-

-

250

pA

-

-

V

-

-

0.8

V

-

pA

Input Voltage High (logic "1" level)
Input Voltage Low (logic

2

"a" level)

Input Current High (logic "1 ")

2V

-30

Input Current Low (logic "0")

OV

-40

-

tpHL

-

2.6

-

tpLH

-

1.4

-

Propagation Delay Time

The photographs and dimensions represent
a chip when it is part of the wafer. When the
wafer ~ ~ut into chip~. t~e cleavage angles
are 57 Instead of 90 with respect to the
face of the chip. Therefore, the isolated
chip is actually 7 mils 10. 17 mm) larger
in both dimensions.
Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10- 3 inch).

f.1A
f.1s

256 _______________________________________________________________________

CA3161E
TRUTH TABLE
BINARY
STATE

INPUTS

OUTPUTS

DISPLAY

:zO

a

b

L

L

L

L

L

L

L

L

H

L

L

H

H

L

L

H

H

H

H

L

L

H

L

L

L

H

L

L

H

L

3

L

L

H

H

L

L

L

L

H

H

L

4

L

H

L

L

H

L

L

H

H

L

L

5

L

H

L

H

L

H

L

L

H

L

L

6

L

H

H

L

L

H

L

L

L

L

L

7

L

H

H

H

L

L

L

H

H

H

H

8

H

L

L

L

L

L

L

L

L

L

L

9

H

L

L

H

L

L

L

L

H

L

L

10

H

L

H

L

H

H

H

H

H

H

L

11

H

L

H

H

L

H

H

L

L

L

L

12

H

H

L

L

H

L

L

H

L

L

L

13

H

H

L

H

H

H

H

L

L

L

H

14

H

H

H

L

L

L

H

H

L

L

L

15

H

H

H

H

H

H

H

H

H

H

H

23

22

21

0

L

L

1

L

2

c

d

e

f

9

0
I
2
3

Y
5
6

1
B
9
-

E
H
L
P
BLANK

__________________________________________________________________ 257

CA3162E

AID Converter for 3-Digit
Digital Readout System

Features:
Dual-slope AID conversion
Ultra-stable internal band-gap voltage reference
Capable of reading 99 mV below ground with single supply
Differential input
Internal timing - no external clock required
Choice of low-speed (4-Hz) or high-speed (96-Hz)
conversion rate
.
. .
.uHold" inhibits conversion but maintains display
• Multipl£xed operation for high efficiency
• Overrange indication - "EEE" for reading greater.than
+999 mV, " __ -," for reading more negative than -99 mV
when used with CA3161 E BCD-to-Seven Segment Decoderl
Driver
•
•
•
•
•
•

The CA3162E is a monolithic integrated
circuit that comprises the AID converter
section of a 3-digit digital readout system.
It is used with the CA3161E BCD-to·Seven'
Segment Decoder/Driver* and a minimum
of external parts to implement a complete
system.
* The

CA3161E is described in RCA data bulletin
File No. 1079.

TERMINAL ASSIGNMENT
CA3162E
ELECTRICAL CHARACTERISTICS at TA = 25°C, V+
gain pot = 2.4 kf! unless otherwise stated
CHARACTERISTIC

= 5 V, Zero pot centered,
LIMITS

TEST CONDITIONS
Min.
4.5
100 kf! to V+ on terms. 3.4,5

Input Impedance, ZI
Input Bias Current, lIB

Typ.

UNITS
Max.

DIGIT
SElECT
OUTPUTS

I

l

2'
20

,
2

NSD 3
MSD 4
LSD 5

HOLD/BYPASS 6

16

2

'!

BCD
OUTPUTS

2'

I

GAIN ADJ
INTEGRATING CAP

II

HIGH INPUT
LOW INPUT

Operating Supply
Voltage Range, V+
Supply Current, 1+

BCD
OUTPUTS

Terms. 10 and 11.

Unadjusted Zero Offset V ll-V 10 = OV, read decoded
output

5

5.5

V

-

-

17

mA

100

-

Mf!

-

-80

-

nA

-12

-

+12

mV

846

-

954

mV

-

Circuit Description

Unadjusted Gain

V 11--:V 10 =900 m V, read decoded
output

Linearity

See Notes 1 and 2

-1

Conversion Rate:
Slow Mode

Term. 6 = open or gnd

-

4

-

-

96

-

0.8

1.2

1.6

V

+0.2

V

Fast Mode
Term. 6 = 5 V
Conversion Control
Voltage (Hold Mode) at
Terminal 6
Common·Mode Input
See Note 3
Voltage Range, VICR

-0.2

BCD Sink Current at
terms. 1,2,15,16

VBCD';; 0.5 V, at logic zero state

Digit Select Sink Cur·
rent at terms. 3.4,5

V Digit Select

Zero Temperature
Coefficient

V I=OV, zero pot centered

Gain Temperature
Coefficient

VI

= 4V at logic zero state

=900 mV, gain pot =2.4 kf!

+1 Count

-

Hz

0.4

1.6

-

mA

1.6

2.5

-

mA

-

10

-

jJvl"c

-

0.005

-

%fC

NOTES:

1. Apply zero volts across V l l to V10' Adjust zero potentiometer to give 000 mV reading. Apply 900 mV
to input and adiust gain potentiometer to give 900 mV reading.
2. Linearity is measured as a difference from a straight line drawn through zero and positive full scale.
Limits do not include ±o.5 count bit digitizing error.

3. For applications where negative terminal 10 is not operated at terminal 7 potential, a return path of
not more than 100 kSl resistance must be provided for input bias currents.

The functional block diagram of the CA3162E
is shown in Fig. 1. The heart of the system
is the VII converter and reference-current
generator, The V II converter converts the
input voltage applied between terminals 10
and 11 to a current that charges the integrating capacitor on terminal 12 for a pre·
determined time interval. At the end of the
charging interval, the VII converter is disconnected from the integrating capacitor,
and a band-gap reference constant-current
source of opposite polarity is connected. The
number of clock counts that elapse before
the charge is restored to its original value is a
direct measure of the signal induced current.
The restoration is sensed by the comparator,
which in turn latches the counter. The
count is then multiplexed to the BCD
outputs.
The timing for the circuit is derived from a
786-kHz ring oscillator. The oscillator frequency is divided by 2048 to provide the
multiplex rate of 384 Hz. This rate is
further divided by 96 to obtain the slowspeed conversion rate of 4 Hz (terminal 6
open or grounded). When the "hold" terminal (terminal 6) is biased to ±1.2 V, conversion ceases, but multiplex continues and
the reading is held and displayed con·
tinuously.
When terminal 6 is biased at +5 V; a portion
of the divide-by-96 circuitry is disabled so
that the conversion rate increases to 24 times
the slow-speed rate (4 x 24 = 96 Hz). Note

258 __________________________________________________________________

CA3162E
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY VOLTAGE (between terminals 7 and 141_
INPUT VOLTAGE (terminal 10 or 11 to groundl
DEVICE DISSIPATION:
Up to T A = +55°C
Above T A = +55°C
AMBIENT TEMPERATURE RANGE:

. +7 V
±15V
. . . ..
750mW
derate linearly at 7.9 mwtOc

Operating.
Storage

. 0 to +7S:C
-65 to +150 C

LEAD TEMPERATURE (DURING SOLD.ERINGI:
At distance 1/16 ± 1/32 inch (1.59 ±0/79 mm) from case for 10 seconds max.

v+

+265°C

BCD OUTPUTS

I

that the multiplex rate is unchanged. Fig. 3
shows the timing of conversion and digit
select pulses for the high-speed mode. Note
that the basic AID conversion process requires
approximately 5 ms in both modes.
The ··EEE" or " ___ " displays indicate that
the range of the system has been exceeded in
the positive or negative direction, respectively. Negative voltages to -99 mV are displayed with the minus sign in the MSD. The
BCD code is 1010 for a negative overrange
(___ ) and 1011 for a positive overrange
(EEE).

System Application
Fig. 2 is the block diagram of a basic system
using the CA3162E and the CA3161E. An
actual-size PC board layout for this circuit
is shown in Fig. 4. The BCD outputs of the
CA3162E drive the BCD inputs of the
CA3161 E BCD-to-7-segment decoder di rectly.
The seven-segment outputs are multiplexed
to the three LED displays. The digits are
selected by terminals 3, 4, and 5 (CA3162E),
which provide base current to the external
p-n-p transistors. The p-n-p's, in turn, provide
current to the anodes of the display. Adjustment procedures for the gain and zero
potentiometers are given in Note 1 of the
Electrical Characteristics chart.

HIGH INPUT II

6

•

CONVERSION
CONTROL

1 GNO

MSO-NOST SIGNIFICANT DIGIT
NSO- NEXT SiGNIFICANT DIGIT

9ZCM-30414RI

LSD- LEAST SIGNI FICANT DIGIT
GAIN
ADJ

Fig. 1 - Functional block diagram of the CA3162E.

-

• 5V

TERM
No·
12
POWER

2N2907
OR
EOUIV

,......,

.........

S(LSDI

200""

i-41MODI

L

-U

OOOmV

~ OOOmV

...J

i

3111 ..I

HOLD:

r:}!,ao ...v

Vs- 12 V

2,ftl/DlvrSION
I2C,·JQ4IIfU

Fig. 3 - High speed mode timing diagram.

RI
150n.
CA3162E
TERMINALS

FNQ507 OR EQUIVALENT

R'1.(U1

92:tL- 30416RI

1.2·"·I6.CD

~ ~
'.4·~Kn

* FAIRCH~LD

CA3162E
TERMINALS

R2
I!SOn.

DIGIT
=ORIVER

SEGMENT
DRIVERS

Fig. 2 - Basic digital readout system using the CA3162E and
the CA3161E.

_____________________________________________________________________ 259

CA3162E
+5 V

GND

TERM. 3 OF READOUT (FND-507
OR EQUIVALENT)
RI,R2,R3 '" 150n
CI=O.27I'F
QI,Q2,Q3=2N2907
C2=O.II'F

LOW SPEED MODE :GNDOROPEN
HOLD: 1.2 V
HIGH SPEED MODE;5 V
Fig. 4 -

92CS-31017

Component side of p.C. board

Dimensions and pad layout for

the CA3162H Chip.

92CS-3101~

Fig. 5 - P.C. board layout for a basic digital readout system
using the CA3162E and CA3161E.

The photographs and dimensions of each Linear
chip represent a chip .when it is parr of the wafer.
When the wafer is cut into chips, the cleavage

angles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip is
actually 7 mils (0.17 mm) larger in both dimensions.

Dimensions. in parentheses are in milHmerers and
are derived from the basic inch dimensions as in-

dicated. Grid graduations are in mils 00- 3 inch).
92CM-30412

260 __________________________________________________________________

CA3162E
+ov

I.

CA3162E Liquid Crystal Display (LCD)
Application
Fig. 6 shows the CA3162E in a typical LCD
application. LCD's may be used in favor of
LED displays in applications requiring lower
power dissipation, such as battery·operated
equipment, or when visibility in high·ambient·
light conditions is desired.

C040568

I.
CA3162E

+5v

1.~==~=;::+-=---l-jJ~~
•2
151-'2~'--1"+-'

}"'"

C040568

.'

OF LCD

20

10

I.

GAIN
IOKn

Inverters Gl and G2 are used as an astable
multi vibrator to provide the ac drive to the
LCD backplane. Inverters G3, G4, and G5 are
the digit·select inverters and require pull-up
resistors to interface the open'collector out·
puts of the CA3162E to COS/MaS logic.
The BCD outputs of the CA3162E may be
connected directly to the corresponding
CD4056B inputs (using pull·up resistors). In
this arrangement, the CD4056B decodes the
negative sign (-) as an "L" and the positive
overload indicator (E) as an "H".

The additional logic shown within the dotted
area of Fig. 7 restores the negative sign (-),
allowing the di,play of negative numbers as
low as -99 mV. Negative overrange is indicated by a negative sign (-) in the MSD
position. The rest of the display is blanked.
During a positive overrange, only segment b of
the MSD is displayed.

OF LCD

•

7

Multiplexing of LCD digits is not practical,
since LCD's must be driven by an ac signal
and the average voltage across each segment is
zero. Three CD4056B liquid·crystal decoderl
drivers are therefore used. Each CD4056B
contains an input latch so that the BCD data
for each digit may be latched into the decoder
using the inverted digit·select outputs of the
CA3162E as strobes.

CA3162E Common-Cathode, LED Display
Application
Fig. 7 shows the CA3162E connected to a
CD4511 B decoder/driver to operate a common-cathode LED display.
Unlike the
CA3161 E, the CD4511 B remains blank for
all BCD codes greater than nine. After
999 mV the display blanks rather than displaying EEE, as with the CA3161 E. When
displaying negative voltage, the first digit remains blank instead of (-), and during a
negative overrange the display blanks.

}"-

•2

•4
•

+5V

+5v

C040568

3

GI~G6.C04049UB

5 7

HEX INVERTER
G7·G8:CD401IU8
QUAD 2-INPUT NAND

t""'
OF LCD

TO lCO

BAC)(PLANE

92CL- 31016

Fig. 6 - Typical LCD application.

, - - - - - - - - - - - - - -;';-"";;;'-;1
I
116C04049UI
I

I

I

I

:

L_

_________

~

v·

v·

INPUT

92CL-JI0I8

Fig. 7 - Tvpical common-cathode LED application.

____________________________________________________________________ 261

CA3164E

Preliminary Data

BiMOS Single-Chip Smoke Detector

TERMINAL ASSIGNMENT

For Fire Detection Systems
CHAMBER IN Z

either the chamber input or horn output
terminals. The CA3164E can also be used
with photoelectric chambers by the addition
of several external components.

v+

13

~~~~~~~~HOTO csc.

12 INTERCONNECT

CHAMBER ADJ. 3

The RCA·CA3164E is a monolithic BiMOS
integrated circuit designed to meet the
stringent system requirements of a battery· or
line·operated smoke detector circuit. When
used with an ionization chamber and electromechanical horn, it provides a one-chip
approach to smoke detection. No external
active devices are required to interface with

14

II ALARM CSC. ENABLE
LOW BATTERY ADJ. 5

10 NO CONNECTION

PHOJ3~~5~ 6

9

GROUND (v-) 7

v+

OR OUTPUT ENABLE

8 MECH. HORN DRIVER
TOP VIEW

The CA3164E was designed to comply with
U.L. 217 and is supplied in the 14-lead dualin·line plastic package.

92CS- 31019

Features:
• Interfaces directly with ionization chamber no external buffer FET required
• Low input current: 1 pA max.
• Gate·protected input terminals
• On·chip beep oscillator for low battery
indication - requires one external capacitor
• Output capable of driving a conventional horn
• Self·contained low-battery-voltage detection circuit
(al Fixed or adjustable trip point available
(bl Dynamic battery test when filter capacitor = 2/lF
• Chamber trigger voltage independent of
battery supply voltage (less than 150 mV
over temperature and supply variationsl
• Designed to comply with U.L217
• Reference source current available = 5 /lA
(typ.1
• Low standby battery current = 8 /lA (typ.1
• Can be used with photoelectric sensors by
using a minimum of external passive
components in combination with the
RCA-CA3078 micropower op-amp
• Multiple-unit interconnect terminal controls
a common annunciator circuit
(al A fault to ground doesn't prevent
local operation.
(bl The low battery alarm signal
triggers only the local unit.
• LED output indicates status of smokedetector circuit
• Operates from 11 V (max.1 supply (either
battery or linel
• Battery reversal protection feature

REFERENCE
VOLTAGE

FROM

IO~~~~T~~~C2~---f" ~>--"""""'---,:::l
CHAMBER ADJ. 3 » - - - " " 1 /

nCM<5t020

Fig. 1 - Simplified functional diagram for CA3164E.

MAXIMUM RATINGS, Absolute-Maximum Values:
+11 V

DC SUPPLY VOLTAGE, V+
DEVICE DISSIPAJION, PD :

. 600mW
6.7 mWt"C

Up to T A "25 C
. .
Above T A = 25°C derate linearly at

AMBIENT TEMPERATURE RANGE:
Operating
Storage
LEAD TEMPERATURE IDURING SOLDERING):

. 0 to +50°C
-65 to +150o C

At distance 1/16 ± 1/32 inch 11.59 ± 0.79 mm) from
case for 10 seconds max,

+9V

NOTES,
I. CONTINUOUS HORN ON

ALARM
2

CAP. CI ADJUSTS LOW
BATTERY BEEP AND

LED BLINK RATE

'* POLVCARBQNATE OR EQUIVALENT

92CS- 31021

INSULATION RESISTANCE >10 Gtl
APPROX. I nA LEAKAGE

Fig. 2 - Basic ionization detector with electro-mechanical horn.

I. TERMINAL II CONNE;CTEO TO GND. CONTINUOUS HORN
2. CI SETS TIMING FOR IRE DIODE

92CM-310U

Fig. 3 - Typical photoelectric system using CA3164E.

262 __________________________________________________________________

CA3164E
ELECTRICAL CHARACTERISTICS at T A = 25°C, V+ = 9 V
CHARACTERISTIC

LIMITS
UNITS
Min. Typ.
Max.
7
9
11
V

TEST CONDITIONS

Operating Voltage
Common·Mode Input
Voltage Range, VICR
Low·Battery Trigger
Voltage
Horn Driver

Connections for Optional Functions

(V+ -2 V) = 7 V

0

External adjust
(increase only)
Term.8= 100mA
Term. 8 = 300 rnA

VCE(SAT)
Reference Voltage
Input Leakage
Current, IL

Sink
Low·Battery Adjust, Term.5
Input Current
Timing Current
LED Blink Period
LED Pulse Width
Remote Fan·Out

7.7

7.9

V

0.5
1

-

V

6.2

6.6
1
2.5
50
12

V

-

-

8*

-

18

-

-

13

-

pA

J-I.A

5
40

-

ISink = 10 J-I.A typo

-

2.8

-

rnA

ISource - 1.3 rnA typo

-

50

-

J-I.A

50

70

100

nA

50
1

-

nA
PPM
ms

-

%
sec.

Term. 13
Adjustable
Fixed

10

-

-

50

-

30

20

-

On·time
On·time = 95%
Off·time 5%

Alarm Pulse Duty Cycle
(4.7 MQ from Term. II
to gnd

V

5.8

Reference Source Current
LED Driver Sink Current
Interconnect Current
Source

7

7.3

Term. 2
Term. 2 at 50 C
Term. 3
No LED connected
LED connected-20 rnA
for 30 ms every 60s
Photoelectric operation LED photocurrent = 0.6 A
.i5 sec. rate.!.

Standby Current (13 MQ
from Term. 4 to gnd)

-

95
0.5
0.026

-

J-I.A
rnA

• Adjustable to 5 p.A

Condition
Normal
Low Battery
Smoke In Chamber

No
No
Ves

No
Ves

External I nput A1
From Remote Unit

No

No

X

Alarm
Enable
Pulser
11

System
Interconnect
12

Remote
Unit
Status

Blink Off
X
Blink Beep
X
On
Pulsed* Resistor
to ground

Low
Low
High

Off
Off
On

Blink On**

High

On

Alarm
Horn
8

High

= Don't

Care

Blink & Beep

= 30 msec (fixed)

v+~

~

2. Sounder Operating Mode
Continuous sound on alarm - connect
terminal 11 to V+.
Pulsed sound on alarm - connect resistor
between terminal and ground.
3. Remote (Interconnect)
Connect terminal 12 to same terminal on
all other units (fan out = 20 unitsL When
interconnecting units for the remote·alarm
function, the extremely low currents in·
valved make it extremely important that
a provision be made for Iimiting externally
induced transients into the remote termi·
a!. For example, inadvertent contact with
external power sources or electrical storm
activity may cause triggering of the remote
alarm function. The circuit below will reo
duce the possibility of such occurences.

TO OTHER
DETECTORS

92CS-310Z3

O:LTAGE AT TERMS

410Ul

ov

~
lLEO

20mA

j I-'m.

•• Alarm Horn follows mode programmed for internal system input. For example, if terminal 11 has
resistor connected to ground, horn will beep. If terminal 11 is connected to V+. horn will be "on,"
X

Add diodes as shown below to increase the
the low·battery trigger point.

4. LED On·Time Adjustment
Option 1: The CA3164E is designed to
provide a fixed LED on·time of approxi·
mately 30 ms. For applications requiring
a reduction in on·time the following cir·
cuit is recommended:

OPERATING MODES TRUTH TABLE
Smoke
Low Led
Ionization Battery 6
Chamber

1. Low Battery Adjustment - Terminal 5

'Xr-.--+ TO MECH. HORN
92CS-310Z4

every 50 sec

(ADJ)

Pulsed ::: 95% "on" time - Period is determined by resistor from terminal 11 to ground-5% Off Time
• Horn "Continuous" if terminal 11 is connected to V+

This circuit reduces the LED on·time but
does not affect the horn on·time of 30 ms.
When using this configuration during the
continuous·alarm mode (smoke in cham·
ber) the LED will be off instead of on, as
shown in the truth table. If the horn is
pulsed d·uring the alarm mode, the LED
will blink at the pulse rate.

__________________________________________________________________ 263

CA3164E
Option 2: A chip design change can be
implemented to generate a 10 ms LED
on-time_ The sounder would also be pulsed
for only 10 ms_ A further reduction in
this time may result in faulty operation
of the sounder_
5. Cleaning Procedure
To insure leakage currents of less than
1 pA the following procedure is recommended:
(a) degrease in trichlorethylene
(b) rinse in de-ionized water

An operational ampl ifier configuration is
used for the ionization chamber input.
P-channel MOS field effect transistors are
used on this input in the bootstrap configuration shown in Fig. 4 to drive the
protection diodes and maintain the subpioampere input current.

Circuit Description
Basic Functions - The CA3164E is designed
to interface directly with an ionizationchamber type of smoke detector. Upon being
triggered by a decreasing voltage at the ionization-chamber output. the IC operates a
mechanical transducer_In addition to this
basic smoke-detector function, another circuit monitors and compares the battery voltage to an internal reference-voltage source_
Once the battery voltage drops below a defined level, a short 30-ms beep sound is
produced in synchronism with an LED indicator every 50 seconds_ This rate is determined by a programming resistor connected between terminal 4 and ground and
an external 0_1 /IF capacitor connected between terminal 13 and ground.
A buffered output voltage is available from
the reference supply that may be used to
operate the ionization chamber. This,voltage
helps maintain constant sensitivity with decreasing supply voltage_

When terminal 11 is returned to V+, the alarm
sounds continuously. However, it terminal 11
is returned to ground through a programming
resistor as shown in the block diagram, the
alarm pulses. The pulse rate is determined by
the sum of the current through the, programming resistor connected to terminal 11
and the current from the basic timer current
source. Thus, when the detector goes into the
alarm mode, the nominal 50-second timer is
increased to a nominal 0.5-second period.
This second 0.5-second rate is a function of
the external 4.3-M n programming resistor.

92CS-31024

Fig. 4 - Schematic of ;onjzatjon~hamber amplifier.

The first alarm mode is the customary continuous sound. The second alarm mode is an
interrupted or pulsed sound.

A conventional bipolar amplifier is used for
the battery monitor circuit. The zener diode
is biased at about 3 /lA. This zener voltage
is raised one V AK and then applied to the
base of an emitter-follower transistor to
buffer and reflect the zener voltage to the
outside reference terminal. By providing an
additional input terminal (terminal 5), where
three level-shifting diodes are available, an
additional external means is provided to raise
the voltage level at which the CA3164E goes
into the low-voltage alarm mode.
An integrating type of timer is used to
generate the one-minute LED power-monitor
and battery-function indicator pulse. Fig, 5
shows the system. A constant-current source
charges the external O.I-/lF timing amplifier
PI, which subsequently triggers the 30-ms
one-shot multivibrator composed of n-channel
MOS transistor N3 and n-p-n transistor 01.

Operation - The CA3164E is current programmable by placing a resistor .from terminal
4 to ground. This resistor establish'es the
operating current levels for all the current
sources within the IC including the timing
circuits.

N3 is then cut off and its drain climbs to the
supply rail, linearly charging capacitor CPo
When the drain of N3 reaches the supply rail,
the charging current ceases, cutting off the
base current of N3 and discharging the
capacitor.

There are two alarm modes and two conditions that will' sound the alarm. The first
alarm condition is the normal smoke in the
ionization chamber; the other condition is a
high level to the remote input/output terminal of the IC.

An open-collector n-p-n transistor is used to
drive the OPtional external LED power
monitor and battery condition indicator.

264 __________________________________________

Fig. 5 - Schematic of timer and one-shot multivibrator,

A large n-p·n transistor at terminal 8 is
capable of operating the typical mechanical
interrupter type sounders. An active pull-up
transistor is also incorporated in this circuit.
Terminal 9 must be returned directly to V+.
Terminal 12, the interconnect terminal, is
both an input and output for the circuit.
When connected by two wires to other units,
alarm in anyone unit will activate the other
units. A small sinking current of only 10 /lA
keeps the line impedance down while a
sourcing current of over 2 mA is available in
the alarm mode. This current is more than
sufficient to trigger over 20 additional units.

~------------------------

CA3240, CA3240A Types

Dual BiMOS Operational Amplifiers

TOP VIEW

IN~~¥'(AI

With MOS/FET Input, Bipolar Output

1:~~j?i'1,::-2"

~S[Cll,

The RCA-CA3240A and CA3240 are dual
versions of the popular CA3140-series integrated circuit operational amplifiers_ They
combine the advantages of MOS and bipolar
transistors on the same monolithic chip. The
gate-protected MOS/FET (PMOS) input transistors provide high input impedance and a
wide common-mode input voltage range
(typically to 0.5 V below the negative supply
rail). The bipolar output transistors allow a
wide output voltage swing and provide a high
output current capability.
The CA3240A and CA3240 are supplied in
the 8-lead dual-in-line plastic package (MiniDIP, E suffix), and in the 14-lead dual-in-line
plastic package (E1 suffix). They are pincompatible with the industry standard 747
and 1458 operational amplifiers in similar
packages. The CA3240A and CA3240 have
an operating-temperature range of -40 to
+85 0 C. The offset null feature is available
only when these types are supplied in the
14-lead dual-in-line plastic package (El suffix).

I

+1

3

Features:

N°J.ISfJ, 5
Ii Dual version of CA3140
'~~~T\NBVi 6,~-,--,.....,
- Internally compensated
INpl~riBl,"7)-,-~
- MOS/FET input stage
(al Very high input impedance (ZINI- 1.5 Tn typo
*PINS 9 AND 13 INTERNALLY
CONNECTED THROUGH APPROJt
(bl Very low input current (III - 10 pA typo at ± 15 V
.n
(cl Wide common-mode input-voltage range (VICRIEl Suffix
can be swung 0.5 volt below negative supplyPin compatible with the
voltage rail
industry-standard 747
(dl Rugged input stage - bipolar diode protected
- Directly replaces industry types 747 and 1458 in
most applications
OUTPUT (Al I
- Operation from 4-to-36 volts
single or dual supplies
- Characterized for ± 15-volt operation and for
TTL supply systems with operation down to 4
volts
- Wide bandwidth - 4.5 MHz unity gain at
± 15 Vor 30 V
- High voltage-follower slew rate - 9 V I/J.s
- Output swings to within 0.5 volt of
negative supply at V+ = 5 V, V- = 0

7 OUTPUT IB)

IN".
6

INPUT (8)

TOP VIEW

E Suffix
Pin compatible with the
industry-standard 1458
Fig. 1 - Functional diagrams.

STAGE
,BIAS-CIRCUIT
- - - , r -INPUT
--I
II

Applications:
- Ground-referenced single-supply amplifiers
in automobile and portable instrumentation
- Sample and hold amplifiers
- Long-duration timers/multivibrators
(microseconds-minutes-hoursl
- Photocurrent instrumentation
- Active filters - Intrusion alarm systems
- Comparators - Instrumentation amplifiers
- Function generators - Power supplies

~~--~-~-:--~--~

I
I
I
I

I
I .,

8'

Circuit Description

OFFSET NULL
ALL RESISTANCE VALUES ARE IN OHMS.

*ONLY AVAILABLE WITH 14-LEAD DIP (EI SUFFDO

Fig. 2 - Schematic..diagram of one-half CA3240 series.

v92CL.-30014

The schematic diagram of one amplifier
section of the CA3240 is shown in Fig. 2. It
consists of a differential amplifier stage using
PMOS transistors Q9 and 010 with gate-tosource protection against static discharge
damage provided by zener diodes 03, 04,
and D5. Constant current bias is applied to
the differential amplifier from transistors Q2
and as connected as a constant-current
source. This assures a high common-mode
rejection ratio. The output of the differential
amplifier is coupled to the base of gain stage
transistor 013 by means of an n-p-n current
mirror that supplies the required differentialto-single-ended conversion. Provision for offset null for types in the 14-lead plastic
package (E1 suffixl is provided through the
use of this current mirror.

______________________________________________________________

2~

CA3240, CA3240A Types
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY VOLTAGE
IBElWEEN v+ AND V- TERMINALS)
OPERATING VOLTAGE RANGE

36V
4 to 36 V
or ±2 to ±IS V
. . . .
±B V
IV+ +B VI to IV- -0.5 V)

DIFFERENTIAL-MODE INPUT VOLTAGE
COMMON-MODE DC INPUT VOLTAGE
INPUT-TERMINAL CURRENT
DEVICE DISSIPATION:
UP TO 55°C
ABOVE 55°C
TEMPERATURE RANGE:
OPERATING
STORAGE
•.•.•..
OUTPUT SHORT·CIRCUIT DURATIONLEAD TEMPERATURE IDURING SOLDERING):
AT DISTANCE 1/16 ± 1/32 INCH 11.59 ± 0.79 MM)
FROM CASE FOR 10 SECONDS MAX.

1 mA

630mW
Derate linearlv 6.67 mWJOC
• -40 to +B50C

. -65 to +1500 C
UNLIMITED

• Short circuit may be applied to ground or to either supply. Temperatures and/or supply voltages must
be limited to keep dissipation within maximum rating.

ELECTRICAL CHARACTERISTICS FOR EQUIPMENT DESIGN
At V+ = 15 V, V- = 15 V, T A = 25 0 C Unless Otherwise Specified
LIMITS
CA3240A
CA3240
Min. Typ. Max. Min. Typ. Max.

CHARACTERISTIC
Input Offset Voltage,
Input Offset Current,
Input Current,
Large-Signal
Voltage Gain.
(See Figs. 4, 19)

IVlol

-

2

5

-

5

15

mV

Piol

-

0.5

20

-

0.5

30

pA

II

-

10

40

-

10

50

pA

-

V/V

-

20 k lOOk
86

100

-

86

100

-

dB

-

32

320

-

32

320

/-J.V/V

70

90

-

70

90

-

dB

-15

-15.5
to
+12.5

-

12

-15

-15.5
to
+12.5

11

V

VICR

Maximum Output
Voltage,-

- At Vo

= 26 Vp _p '

*

150

-

100

150

/-J.VIV

80

-

76

80

-

dB

13

-

+12

13

VOM- -14 -14.4

-14 -14.4

-

V

VOM- 0.4

0.13

-

0.4

0.13

-

V

8

12

-

8

12

mA

240

360

-

240

360

mW

VOM+ +12

(See Figs. 22,16)

L-~----~----------~---KJvOFFSET
NUL.L

100

Power-Su pply
!'N10/6V
Rejection Ratio,
PSRR
(See Fig. 11 )
76

Total Device
Dissipation,

20 k lOOk

CMRR

Common-Mode
Input-Voltage
Range,
(See Fig. 16)

Supply Current,
(See Fig. 7)
For Both Amps.

-

AOL

Common-Mode
Rejection Ratio,
(See Fig. 9)

Maximum Output
Voltage, t

UNITS

The gain stage transistor Q13 has a highimpedance active load (OJ and 04) to provide maximum open-loop gain. The collector
of 013 directly drives the base of the compound emitter-follower output stage. Pulldown for the output stage is provided by
two independent circuits: (1) constant·
current-connected transistors Q14 and 015
and (2) dynamic current-sink transistor 016
and its associated circuitry. The level of pulldown current is constant at about 1 mA for
015 and varies from 0 to 18 mA for 016
depending on the magnitude of the voltage
between the output terminal and 0'. The
dynamic current sink becomes active whenever the output terminal is more negative
than V+ by about 15 V. When this condition
exists, transistors 021 and 016 are turned on
causing Q16 to sink current from the output
terminal to V-. This current always flows
when the output is in the linear region, either
from the load resistor or from the emitter of
018 if no load resistor is present. The purpose
of this dynamic sink is to permit the output
to go within 0.2 V (VCE(sat)) of V- with a
2-kn load to ground. When the load is
returned to 0', it may be necessary to supplement the 1 mA of current from 015 in order
to turn on the dynamic current sink (016).
This may be accomplished by placing a
resistor (approx. 2 kn) between the output
and V-.

92CS-!QOI!

Fig. 3 - Block diagram of one-half CA324D seri...

1+

-

Po

-

+12 V, -14 V and RL

= 2 k!l.

-At RL =2kl1.

I

SUPPLY VOLTAGE Iv-t; V·I-YOLTS
92CS-30015

tAt V+ = 5 V. V- = GND.ISink = 200 ",A.
Fig. 4 - Open-loop voltage gain as a function of
supply volta9t1. and temperature.

266 _______________________________________________________________

CA3240, CA3240A Types
TYPICAL ELECTRICAL CHARACTERISTICS

CHARA{;TERISTIC

LOAD RESISTANCE (RLI' 2: kn
LOAD CAPACITANCE (eLl- 100 pF

20

r---------.--.~

TEST
CONDITIONS
V+ = +15 V
V-=-15V
TA = 25°C

TYPICAL VALUES
CA3240A CA3240

~

~

UNITS

I
g

~

--

10.~~~~~~9~~~E~~E~~~
~

aj----

AMBIENT TEhlPERATURE(TA)-

-24,~·CC

~

Typ. Value of
Resistor Between
Terms. 4 and
3(5) or Between
4 and 14(8) to
Adjust Max.

Input Offset Voltage
Adjustment Resistor
(El Package Only)

:;

!

kn

4.7

18

~

~

10

15

SUPPLY VOLTAGE tV+, '1-) -

20

25

VOLTS
92CS-30016

VIO

Fig. 5 - Gain-bandwidth product as a function

Input Resistance

Rl

1.5

1.5

Tn

Input Capacitance

CI

4

4

pF

Output Resistance

RO

60

60

n

Equivalent Wideband
Input Noise Voltage
(See Fig. 21)

en

48

48

/1V

BW=140 kHz
RS= 1 Mn

of supply voltage and temperature.
20 LOAD RESISTANCE (RLI. 2 kn
LOAD CAPACITANCE (ClI· 100 pF f

t

I

~

~ 10

Equivalent Input
Noise Voltage
(See Fig. 10)

1= 1 kHz

40

40

12

12

40

40

10M

11

11

IT

4.5

4.5

MHz

9

9

V//1s

0.08

0.08

10

10

4.5

4.5

1.4

1.4

120

120

en

RS=

nV/VHZ
1=10 kHz lOOn

Short-Ci rcuit Current to
Opposite Supply Source 10M +
Sink
Gain-Bandwidth
Product
(See Figs. 5 and 19)
Slew Rate
(See Fig. 6)

Settling Time
at 10 V p . p .
(See Fig. 17)

tr

1 mV
~ts

CL =100 pF
RL=2 kn
CL=100 pF
Voltage Follower
f = 1 kHz

Crosstalk

10

15

~

W

SUPPLY VOLTAGE (V+, V-I-VOLTS

Fig. 6 - Slew rate as a function of supply
voltage and temperature.
LOAD RESISTANCE {RLI-Ill

RL =2 kn

Overshoot (See Fig. 20)

5

92CS-30017

SR

Transient Response:
Rise Time

mA

/1s

%
/1S

10

dB
2

o

"

20

Fig. 7 - Quiescent supply current as a
function of supply voltage and
temperature.
AMBIENT TE:WfRATURE (TA1·~·C
SUPPLY VOLTAGE: '1+-10 V, '1-.-&'1

>
I

1

1\

25

?

i
g

20

i

\

"

1\\

10

i,
11

r

,

0
10K

. ..

lOOK

,

."..I............,

FREQUENCY If}-Hl

Fig. 8 - Maximum output voltage swing
as a function of frequency.

.M

10

10'

103

10·

FREQUENCY (I) -

10'

10'

H!

Fig. 9 - Common-mode rejection ratio
as a function of frequency.

10'

10

102

lol

fREQUENCY (f) -

10'

10'

Hz
92CS-30020

Fig. 10 - Equivalent input noise voltage
as a function of frequency.

____________________________________________________________________ 267

CA3240, CA3240ATypes
ELECTRICAL CHARACTERISTICS FOR EQUIPMENT DESIGN
At V+ = 15 V. V- = 15 V. T A = -40 to +85 0 C Unless Otherwise Specified
TYPICAL VALUES
CA3240A
CA3240

CHARACTERISTIC
Input Offset Voltage.

IVlol

Input Offset Current.'

11101
II

Input Current.'
Large·Signal
Voltage Gain.
(See Figs. 4, 19)

•

POWER SUPPLY
Rf.lECTION RATIO

SUPPLY VOLTAGE: V... ·IS V; V-··15 V

~

AMBIENT TEMPERATURE ITAl- 25- C

(PSRRI-,aVIO/4V

1 ,00

i
:
;;80

UNITS

3

10

mV

32

32

pA

640

640

pA

63 k

63 k

V/V

~
~60

L

96

dB

32

32

INN

90

90

dB

-15
to
+12.3

-15
to
+12.3

V

150

150

INN

76

76

dB

lII..ooS".,.,;"

~

~

~20
~

AOL

96

'A.r~

:<

10'

10

10"

I~

10'

FREQUENCY (II - Hz

Common·Mode
Rejection Ratio,
(See Fig. 9)

CMRR

Common·Mode
Input· Voltage Range,
(See Fig. 16)

VICR

Power·Supply'Rejection
Ratio,
(See Fig. 11)
Maximum Output
Voltage,·

t,vIO/t,v
PSRR

VOM+

(See Figs. 16, 22)

VOM
1+
Supply Current,
(See Fig. 7) For Both Amps.
Total Device Dissipation,

Po

12.4

12.4

-14.2

-14.2

Fig. 11 - Power supply rejection ratio
as a function of frequency.

V

8.4

8.4

mA

252

252

mW

15

15

I1 VfDC

Temperature Coefficient
of Input Offset Voltage, LlVIO/LlT

I'

92CS- 3002:1

Fig. 12 - Output sink current as a function

• At Va = 26 Vp . p . +12 V. -14 V and RL = 2 kll.

of output voltage.

• At RL =2 klL
• At T A = 8SoC

.

• SUPPLY VOLTAGE (V-I-O V
6 AMBIENT TEMPERATURE (TA '-25·C

~

.;

§~

E

2

I KlO

I!w

~~
:~
~~

=F'

4

1-- _.

~ I-- --

---

f~;'

IL

-!'V

"

,?~q,q,"V

10

r;rt
~I

~l'f...¥~"

•1--1-I

:~

1-0:

r.-:--

I .
--

V
~/

~~ !

--r-

~

5

,
1.0

0.01'
OUTPUT VOLTAGE (Vol-V

0.1

2:

4

69

2:"

6 810

2

4

8 810 2 2:

4

68 103

FREQUENCY {f)-kHz
'32es· 300Z4

Fig. 13 - Supply current as a function of

output voltage.

Fig. 14 - Crosstalk as a function of frequency.

,

,

.

,

,

.

,

0.1
1.0
LOAD (SINKINGl CURRENT - rnA

..

10

F;g. 15 - Voltage across output transistors
015 and 016 as a function of
load current.

268 ____________________________________________________________________

CA3240, CA3240A Types
TYPICAL ELECTRICAL CHARACTERISTICS FOR DESIGN GUIDANCE
At V+ = 5 V, V- = 0 V, T A = 25°C

LOAO RESISTANCE I RL I-a!

~

TYPICAL VALUES
CA3240A
CA3240

CHARACTERISTIC

UNITS

IVlol

2

5

mV

11101

0.1

0.1

pA

2

2

pA

1

1

H1

100 k
100

100 k
100

VN
dB

32
90

32
90

INN
dB

-0.5

-0.5

2.6

2.6

31.6
90

31.6
90

II

Input Resistance
Large-Signal Voltage Gain,
ISee Figs. 4,191

AOL

Common-Mode Rejection Ratio, CMRR
Common-Mode Input-Voltage
Range,
ISee Fig_ 221

VICR

Power-Supply Rejection Ratio,

PSRR

Maximum Output Voltage,

VOM

ISee Figs. 16,221
Maximum Output Current:
Source,

Sink

+

3

3

0.3

0.3

+

20

20

::

TA • 2!1*'C

"

±:I

~"L!
~'2

TEMPERA~URE

r:AM9IENT
.

0_,
a

1

1

/lVN
dB
V

Slew Rate ISee Fig_ 61

mA

7

7

V//lS

Gain-Bandwidth Product,
ISee Fig. 5)

IT

4.5

4.5

MHz

Supply Current,
ISee Fig. 71

1+

4

4

mA

Po

20

20

mW

Fig. 16 - Output-voltage-swing capability and
common-mode input-voltage range
as a function of supply voltage and
temperature.

101<: SUPPLY VOLTAGE,

SUfPL.YVOLTAGE;
·IOYIV~.-",V
...... [NT TEMPER.lTl.lRE (TA)-2&"C

10

>

,

~

4

I

~

•

~

0

;

-.

-

,,;'t,. .
....

-2

~-

/

- -

lHVfRTIiIG

I

~ RESISTANCE 1I\)"Zk.Il
LOAD CAFW:ITANCE

r--,

{~J·IOO

I

,
I--'~. , \
""~ ~

-60

~.

~.,

-,

,

-10

. ..

1\ "\

,

..

\.

ID

0.1

V, V-·-I:\ V

.ou.OWER
-

."

-s

v+. H:\

~;X- ~~r/' '

/ ......
,.-

2

-40

a

20
20
40
60
AMBIENT TEMPERATURE (TAl

!

10

.

INVERTING

FOLLOWER

,

kfi

SUPPLntlLTAGE,y+·+"y,y-.-"y
AMBIENT TEMPERATURE (TA)-25"C

I

SIMULATED

~.r;.r~:

~

SIMULATED
' - LOAD

~2 kn
100

-.t..-

PF~ ~2
I ~

5.11 kC

0.05 ,..F

~

120

140

"."
-.t.oo

02

~

'b.q."

"<>,

40

l'-~"

~20

JJJ!l:·0

10

IN914

.~~

f~

-

0.,0c.,.

~
kQ

~?

""~..I+
~.f,,?<

~60

',r-'

t. \

I

44-C'~

z

_....>-tl:.~D

JJl(. 't

."-~;'

I;_~_a

Input Offset Voltage,
Input Offset Current,
Input Current,

0

-0" E'-t1--COMMON-MOOE INPUTVOLTAGEI+VLCW

LIJ

~

,

10

I'

10

,~ 10,

FREQUENCY (t) -

Hz

92:C5-3002:6

(b) 1I;$T CIRCUITS

Fig. T7 - Input voltage as a function of settling time.

Fig. 19 - Open-loop voltage gain and phase lag
as a function of frequency.

____________________________________________________________________ 269

CA3240, CA3240A Types
+15 V

+ 15V
TOP TRACE: INPUT
(50 mV/DIV, 200 ns/O!V)
BOTTOM TRACE: OUTPUT
(50 mV/OIII ',200 ns/DIV)

SIMULATED

LOAD

>-.,...-,
I

>

r--t--o V~+~~E
OUTPUT

(0) SMALL SIGNAL RESPONSE

.1.. 2K ...

'OOPFT n~

30.1 kn

L"""1""J
-.:7

TOP TRACE: INPUT
(5V/OIV i

r J.0.2 SECIDIII (UNCAL)

92CS-30033

Fig. 31 - Typical electrocardiogram waveform.

CA3240H Dimensions and Pad Layout

The photographs and dimensions represent a chip
when it is part of the wafer. When the wafer is cut
into chips, the cleavage angles are 5,0 instead of
900 with respect to the face of the chip. Therefore,
the isolated chip is actually 7 mils (0.17 mm)
larger in both dimensions.

Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10- 3 inch).

NOTE

NOS IN PADS ARE FOR 14-LEAD DIP

NOS. OUTSIDE OF CHIP ARE FOR

92CM-30Q35

e- LEAD DIP

____________________________________________________________________ 273

CA3290, CA3290A, CA3290B
Features:

SiMOS Dual Voltage
Comparators
With MOS/FET Input, Bipolar Output
The RCA-CA3290B, CA3290A, and CA3290
types consist of a dual voltage-comparator
on a single monolithic chip. The commonmode input voltage range includes ground
when operated from a single supply. The
low supply-current drain makes these comparators suitable for battery operation; their
extremely low input currents allow their use
in applications that employ sensors with
extremely high source impedances. Package
options are shown in the table below_

(e) No phase reversal of output signal for input

Package & Suffix
Characteristic
Plastic
TO-5
Max. Max. Min. V+
DIL- 8- 14VIC II
(V)
(mV (pA) AOL
Std_ CAN Ld_ Ld_

CA3290B

6

30

5DK

44 T

S

- -

36 T
36 T

S

E

El

S

E

El

CA3290A

10

40

25K

CA3290

20

50

25K

v·

OU(~~T

I

'NV
INPUT 2

7 OUTPUT
(A21

(AI)

INV

6 INPUT
(A2)
~

NON~INV

INPUT
(A21

TOP VIEW

signals down to 5 V below negative supply·
voltage rail
(f) MOSIFET input stage - zener diode protected
(g) Virtually eliminates errors due to flow of
input currents

SELECTION CHART

Selection

TERMINAL ASSIGNMENTS

• MOSIFET input stage:
(a) Very high input impedance (ZIN) - 1.7 Tn typo
(b) Very low input current· 3.5 pA typo at
-15 V supply voltage
(c) low input·offset voltage (V 10) . to 6 mV max.
(CA3290B)
(d) Wide common·mode input·voltage range (VICR)can be swung 1.5 V (typ.) below negative
supply·voltage rail

E SUFFIX

TOP VIEW

• Wide supply·voltage range:
Single supply - 4 to 36 V dc
+3.5
Dual·supply - -0.5 to ±18 V dc
(B-types up to 44 or ±22 V dc)
• Very low supply-current drain - 0.8 mA
at -15 V
• Differential input-voltage range - up to ±36 V
• low output saturation voltage - 120 mV
at4mA
• Output voltage compatible with TTL,
DTl, ECl, MOS, and CMOS logic systems
• All types are rated for operation over the
range of -55 to +125 0 C
• Stable VIO vs. time due to source-follower
inputs

-TIE TO GROUND OR Y· FOR BEST
INPUT/OUTPUT ISOL~TION.

EI SUFFIX

TOP VIEW
INY.
INPUT (AI)

Applications:

Fig. 1 - Basic CA3290 comparator.

• High-source-impedance voltage
comparators
• long time delay circuits
• Square-wave generators
• AID converters
• Window comparators

INY.
INPUT (A21
UCI-500t.

Sand T SUFFIX

MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY VOLTAGE:
Single Supply:
CA3290B
CA3290A, CA3290
Dual Supply:
CA3290B
CA3290A, CA3290
DIFFERENTIAL INPUT VOLTAGE
COMMON-MODE INPUT VOLTAGE
DEVICE DISSIPATION:
Upt0550C
Above 55°C
OUTPUT-TO-V- SHORT CIRCUIT DURATION·
TEMPERATURE RANGE, ALL TYPES:
Operating
Storage

INPUT TERMINAL CURRENT
LEAD TEMPERATURE (DURING SOLDERING):
AT DISTANCE 1/16± 1/32 INCH (1.59 ±0.79 MM)
FROM CASE FOR 10 SECONDS MAX_

*Short circuits from the output to V+ can cause excessive heating and
eventual destruction of the device.

CIRCUIT DESCRIPTION

+44 V
+36 V
±22V
• • • • . • ±18V
± 36 V or ± [(V+-V-)+5 Vl
(whichever is less)
V++5VtoV--5V
.
630mW
Derate linearly at 6.67 mWf'C
CONTINUOUS
-55 to +1250 C

-65 to +1500 C
1 mA

The Basic Comparator
Fig. 1 shows the basic circuit diagram for
one of the two comparators in the CA3290.
It is generically similar to the industry-type
"139" comparators, with PMOS transistors
replacing p-n-p transistors as input stage
elements. TransistQl's 01 through 04 comprise the differential input stage, with 05
and 06 serving as a mirror·connected active
load and differential-to·single-ended converter. The differential input at 01 and 04 is
amplified so as to toggle 06 in accordance
with' the input-signal polarity. For example,
if +VIN is greater than -VIN, 01, 02, and
current mirror transistors 06 and 06 will be
turned off; transistors 03, 04, and 07 will
be turne!! on, causing Q8 to be turned off.
The output is pulled positive when a load
resistor is connected between the output and
V+.

274 __________________________________________________________________

CA3290, CA3290A, CA3290B
ELECTRICAL CHARACTERISTICS at T A = -55 to
CHARACTERISTIC

TEST
CONDITIONS
V+
VIC=l.4 V 5V
VO=l.4 V
VIC-O V,
±15 V
VO=O V

Input Offset
Voltage, V 10

Temp. Coefficient
of Input Offset
Voltage/WIO/in
Input Offset

Input Current, IIA
Supply Current, 1+

.

Voltage Gain, AOL
Saturation
Voltage

VALUES
CA3290B
Typ. Max.

5V

VIC-O V

±15 V

VIC=l.4V

5V
±15 V
5V
30 V

VIC-O V
RL = ~

R L=15 kn ±15 V
V+=5 V,
4mA,
+VI=O V,
-VI=l V

-

4.5

-

8.5

3.5

-

8.5

-

8.5

8

-

8

-

32

-

mV

2
7

-

22

2

22

7

28
28

2
7

2.8

32

2.8

45

2.8

13

32

13

45

13

55
55

0.85

L6

0.85

1

0.85

1.6

1.62

3.5

1.62

3

1.62

3.5

150

-

150

-

150

-

103

-

103

-

103

-

0.7

0.22

-

0.1

-

65
130

-

65

-

1k

130

lk

+125 0 C 0.22
-55 0 C

CA3290A CA3290 UNITS
Typ. Max. Typ. Max.

3.5

8
VIC=l.4V

Current, 110

+125 0 C

0.1

Output Leakage

15 V

65

-

Current, 10L

36 V

130

lk

0.7 0.22
0.1

32

0.7
-

IN/oC

nA

nA
mA
V/mV
dB
V

01 and 04 are operated with a constant cur·
rent load, their gate·to·source voltage drops
will be effectively constant as long as the
input voltages are within the common·mode
range. As a result, the input offset voltage
(VGS(Ol) + VBE(02)-VBE(03)-VGS(04))
will not be degraded when a large differential
dc voltage is applied to the device for ex·
tended periods of time at high temperatures.
Additional voltage gain following the first
stage is provided by transistors 07 and 08.
The collector of 08 is open, offering the user
a wide variety of options in applications. An
additional discrete transistor can be added if
it becomes necessary to boost the output
sink·current capability.
The detailed schematic diagram for one com·
parator and the common current·source
biasing is shown in Fig. 2. PMOS transistors
09 through 012 are the current·source
elements identified in Fig. 1 as 11 through 14,
respectively. Their gate·source potentials
(VGS) are supplied by a common bus from
the biasing circuit shown in the right·hand
portion of the Fig. 2. The currents supplied
by 010 and 012 are twice those supplied by
09 and 011. The transistor geometries are
appropriately scaled to provide the requisite
currents with common VGS applied to 09
through 012.

nA
4.0

LOAD RESISTANCE (RLI.

(0

3.'

AAt T A = +125 0 C
• At T A = -55°C

3.0
2.S

2.0

1.0

os
o

o

10
I~
20
25
30
35
TOTAL SUPPLY VOLTAGE (V+j -1/

40

45

Fig. 3 - Supply current as a function
of supply voltage (both amplifiers).

Fig. 2 - Schematic diagram of CA3290
(only one is shown).

In essence, 01 and 04 function as source·
followers to drive 02 and 03, respectively,
with zener diodes Dl through D4 providing
gate·oxide protection against input voltage

transients (e.g., static electricity). The cur·
rent flow in 01 and 02 is established at
approximately 50 microamperes by constant·
current sources 11 and 13, respectively. Since

INPUT COMMON - MODE VOLTAGE (VIC j - V

Fig. 4 - Input current as a function

of input common·mode voltage.

_______________________________________________________________________ 275

CA3290, CA3290A, CA3290B
ELECTRICAL CHARACTERISTICS AT TA = 25°C

U
CHARACTERISTIC

TEST
CONDo
V+

Input Offset Voltage,
VIC=1.4 V
VIO
VO=l.4 V
VIC=O V
VO=OV
Input Current, II
VIC=1.4 V
VIC=O V
Input Offset Current, 110
VIC=1.4 V
VIC-O V

N

LIMITS
CA3290B

CA3290A

Min.

Typ.

Max.

Min.

Typ.

Max

5V

-

3

6

-

4

10

±15 V

-

3

6

-

4

10

5V

-

3.5

30

-

3.5

40

12

30

12

40

5V

-

-

20

-

2
7

25

-

2
7

20

±15 V

V+-3.5
VV+-3.8
V-

V+-3.1
V--l.5
V+-3.4
V--1.6

-

-

1.35

3

0.8

1.4

I
T
S

mV

±15 V

-

25

INPUT COMMON MODE VOLTAGE (VIcl-V

pA
Fig. 5 - Input current alII function
of input common·mode voltage.

pA

Common·Mode Input·
Voltage Range, V ICR
VO=1.4 V
VO=OV
Supply Current, 1+
RL = 00
Voltage Gain, AOL
RL=15 kn
Output Sink Current
VO=l.4 V
Saturation Voltage
+VI=O V,
-VI=l V,
4mA

5V

V+-3.5
V-

±15 V

V+-3.8
V-

30 V

-

1.35

3

5V

-

0.8

1.4

50

800

25

800

-

V/mV

94

118

-

88

118

-

dB

5V

6

30

-

6

30

-

rnA

5V

-

0.12

0.4

-

0.12

-

-

100

-

500

-

-

-

1.2
200

-

44

562

100

562

316 IlVN

±15 V

V+-3.1
V--1.5
V+-3.4
V--1.6

-

15 V

-

100

36 V

-

500

....
15 V

1.2

-

200

±15 V

-

44

316

5V

100

316

-

Power·Supply Rejection
Ratio, PSRR

±15 V

-

15

316

-

15

Large·Signal Response
Time
RL=5.1kn

15 V
5V

-

500
400

-

-

500
400

Output Leakage Current,
10L
RespOnse Ti me
RL=5.1kn Rising Edge
Falling Edge
Common·Mode Rejection
Ratio, CMRR

-

-

V

rnA
I
SUPPLY VOLTAGE (Y·'- V

Fig. 6 - Positive common-mode input 1/O/taIJe
rtlnge BS B function of supply""'• •

0.4 V

-

pA

Ils
ns

IlVN

SUPPLY VOLTAGE IV·) -

V

Fig. 7 - Negative common·mode input voltJIgB
rtlnge as a function of supply vol• •

./

IO~

~~:~::~ Z -

·

ns

.,,'0 r/

! I~.
~

::!

./

r-:~~

=

40
10
eo
100
120
AMBIENT n:II1PERATURE(TA)--C

140

•

VCm-1.4Y_

IE •

,;'

1101\
il

~~

:

·
··

./

./

/
./

'~

./
ZO

./

Fig. B - Input current as • function of ambient
temp.Tlltutfl.

276 ____________________________________________________________________

CA3290, CA3290A, CA3290B
ELECTRICAL CHARACTERISTICS AT TA = 25 0 C

CHARACTERISTIC

TEST
CONDo
V+

Input Omet Voltage,
VIC=l.4 V
Via
VO=l.4 V
VIC-O V
Vo=O V
Input Curr~nt, II
VIC=l.4 V
VIC=O V
Input Offset Current, 110
VIC=l.4V
VIC-O V

r

LIMITS
CA3290
Min.

·,

~ ~~r:;

10V

Typ.

UNITS

l

IV

,

-

7.5

mV
±15 V

-

7.5

,

S

20

•
§

20

-

I mV

IO,u.A

5V

-

3.5

50

±15 V

-

5V

-

2

30

±15 V

-

7

30

V+-3.5
V-

V+-3.1
V--1.5

-

V+-3.8
V-

V+-3.4
V--l.6

-

30 V

-

1.35

3

5V

-

0.8

1.4

12

50

pA

~

+125-C

·, ~:-~;rc

en 10m"l

5

~

~

;IOOmV

5V

~

:

'w

~

Max.

~

or

ilL

,

... , ... , ... , ..
IOO,u.A

I rnA

IOmA

OUTPUT SINK CURRENT-rnA
9:-CS-~OO~O

Fig. 9 - Output saturation voltage as a
function of output sink current.

pA

Common·Mode Input·
Voltage Range, V ICR
VO=l.4 V
VO=OV
Supply Current, 1+
RL = 00
Voltage Gain, AOL
R L =15kD.
Output Sink Current
VO=l.4 V
Saturation Voltage
+VI=O V,
-VI=l V,
4mA
Output Leakage Current,
10L
Response Time
RL =5.1 kD. Rising Edge
Falling Edge
Common· Mode Rejection
Ratio, CMRR
Power·Supply Rejection
Ratio, PSRR
Large·Signal Response
Time
RL =5.1 kD.

5V
±15 V

TO XIQ SCOPE

PROBE

V

mA

25

800

-

V/mV

88

118

-

dB

5V

6

30

-

mA

5V

-

0.12

0.4

V

15 V

-

100

-

36 V

-

500

-

±15 V

WITH Cc

TOP TRACE"" 4.5 mV/DIV- "lIN
BOTTOM TRACE -IOVlDIY· YouT
H .5,..,/01"1

pA

-

1.2

-

Ils

-

200

-

ns

44

562

5V

-

100

562

±15 V

-

15

316

15 V
±15 V

IlVN
IlVN

WITHOUT Cc

TOP TRACE 1::1 4.5 mVlOIV
BOTTOM TRACE· 10V/DIV

15 V

-

500

-

5V

-

400

-

ns
92CM-300~9

Fig. 10 - Parasitic-oscillations test circuit
and associated waveforms.

_______________________________________________________________________ 277

CA3290, CA3290A, CA3290B
The CA3290A and CA3290 are also supplied
in a 14-lead dual-in-line plastic package_ To
minimize the possibility of parasitic oscillations the input and output terminals are
positioned on opposite sides of the package.
In addition, there are two leads between the
output terminal of each comparator and its
corresponding inverting input terminal, reducing the input/output coupling significantly. These leads (8,9,13,14) should be
tied to either the V+ or V- supply rail. If
either comparator is unused, its input terminals should also be tied to either the V+
or V- supply rail.
TYPICAL APPLICATIONS

I

100 mV
OVERDRIVE

,

'----5 mV

20mV
avERDRtVE

OVERDRIVE

",

100 mV

OVERDRIVE

"-5 mV

OVERDRIVE

OVERDRIVE

92CM

92CM-30057

Fig. 11 - Non-inverting comparator response-time
test circuit and waveforms,

20mV

-300~8

Fig. , ~ - In verting comparator response-time
test circuit and waveforms.

OPERATING CONSIDERATIONS
Input Circuit
The use of MOS transistors in the input stage
of the CA3290 series circuits provides the
user with the following features for comparator applications;
1. Ultra-high input impedance (~1.7 Tn);
2. The availability of common-mode rejection for input signals at potentials
below that of the negative powersupply rail;
3. Retention of the in-phase relationship
of the i~put .and output signals for
input signals below the negative rail.
Although the CA3290 employs rugged bipolar (zener) diodes for protection of the
input circuit, the input-terminal currents
should not exceed 1 mA_ Appropriate seriesconnected limiting resistors should be used in
circuits where greater current flows might
exist, allowing the signal input voltage to be
greater than the supply voltage without
damaging the circuit_
Output Circuit

Parasitic Oscillations
The ideal comparator has, among other
features, ultra-high input impedance, high
gain, and wide bandwidth. These desirable
characteristics may, however, produce parasitic oscillations unless certain precautions
are observed to minimize the stray capacitive
ooupling between the input and output
terminals. Parasitic oscillations manifest themselves during the output voltage transition
intervals as the comparator switches states.
For high source impedances, stray capacitance
, can induce paraSItIC oscillations. TheadclHfon
of a small amount (1 to 10 mV) of positive
feedback (hysteresis) produces a faster transition, thereby reducing the likelihood of
parasitic oscillations_ Furthermore, if the
input signal is a pulse waveform, with relatively rapid rise and fall times, parasitic
tendencies are reduced.
When dual comparators, like the CA3290,
are packaged in an 8-lead configuration, the
output terminal of each comparator is adjacent to an input terminal. The lead-to-Iead
capacitance is approximately 1 pF, which
may be sufficient to cause undesirable feedback effects in certain applications. Circuit
factors such as impedance levels, supply
voltage, toggling rate, etc_, may increase the
possibility of parasitic oscillations. To minimize this potential oscillatory condition, it
is recommended that for source impedances
greater than 1 kn a capacitor (~ 1-2 pF) be
connected between the appropriate input
terminal and the output terminal. (See Fig.
10.)

Light-Controlled One-Shot TImer
In Fig. 13 one comparator (A 1) of the
CA3290 is used to sense a change in photo
diode current. The other comparator (A2)
is configured as a one-shot timer and is
triggered by the output of A 1. The output
of the circuit wi II switch to a low state for
approximately 60 seconds after the light
source to the photo diode has been interrupted. The circuit operates at normal room
lighting levels. The sensitivity of the circuit
may be adjusted by changing the values of
R1 and R2_ The ratio of R1 to R2 should be
oonstant to insure constant reverse voltage
bias on the photo diode.
Low- Frequency Multivibrator
In this application, one-half of the CA3290
is used as a conventional multivibrator circuit. Because of the extremely high input
impedance -of this device, large values of
timing resistor (R1) may be used for long
time delays with relatively small leakage
timing capacitors_ The seoond half of Ithe
CA3290 is used as an output buffer to insure
that the multivibrator frequency will not be
affected by output loading_
Window Comparator
Both halves of the CA3290 can be used in a
high input-impedance window comparator
as shown in Fig. 15_ The LED will be
turned "on" whenever the input signal is
above the lower limit (VL) but below the
upper limit (Vul. as determined by the
Rl/R2/R3 resistor divider.

LED Bar Graph Driver
The circuit in Fig. 16 demonstrates the use
of the CA3290 in a bar graph display. The
non-inverting inputs of both comparators
are tied to the voltage divider reference and
the input signal is applied to both of the
inverting inputs. The LED for a particular
comparator will be turned "on" when the
input voltage reaches the voltage on the
resistor divider reference_ The CA3290 is
ideal for this application where input-signal
loading is critical even though many comparator inputs are driven in parallel.

The output of the CA3290 is the open collector of an n-p-n transistor, a feature providing
flexibility in a broad range of comparator
applications_ An output ORing function can
be implemented by parallel-connection of
the open collectors. An output pull-up resistor can be connected to a power supply
having a voltage range within the rating of
the particular CA3290 in use; the magnitude
of this voltage may be set at a value which is
independent of that applied to the V+
terminal
of the CA3290.
278 ______________________________________________________________________
_

CA3290, CA3290A, CA3290B
+115 'Y
1.15 MEG

+115 'Y

+Iev

:5.:5K

10K

+115V
I MEG
'3.'3 K

.'--+~--K3)-j
IMEG
I MEG

Fig. 14 - Low-frequency multivibrator.

Fig. 13 - Light.-controlled one-shot timer.

lOOK

LEO
+1!i'Y

.,

47K

670n

INPUT
47 K

.2
lOOK

Fig. 15 - Window comparator.

I MEG

0-10 V
INPUT

Fig. 16 _I LED bsr-grsph drivsr.

The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face of the chip. Therefore, the isolated chip is
actually 7 mils (0. 17 mm) larger in both dimensions.

Dimensions in parentheses are in millim8tBrs .nd
are derived from the basic inch dimensions ., indicated. Grid graduations are in mils {Io-3 inch}.
NOTE: .. as. IN PADS ARE FOR a-LEAD DIP AND TO-i5
NOS. DUTSIDEOFCHIP ARE FOR 14-LEAD DIP
9ZCM-30091

Dimensions and pad layout for the CA3290H.

_____________________________________________________________________ 279

CA3401E, CA3401G
Features:

Quad Single-Supply
Operational Amplifier

•
•

Single-supply operation - +5 V to +18 Vdc
I nternally compensated

For Automotive Electronics and Industrial
Control Systems

•
•
•

Wide unity-gain bandwidth - 5 MHz typo
Low input bias current - 50 nA typo
High open-loop gain - 2000 V IV typ,

"G" Suffix Types - Hermetic Gold-CHIP in
Dual-In-Line Plastic Package
"E" Suffix Types - Standard Dual-In-Line
Plastic Package
The RCA-CA3401 is a high-gain monolithic
quad operational amplifier designed specifically for applications using a single positive
power supply. No external compensation
is necessary. Closed-loop stability in each of
the four independent amplifiers is maintained by a 3-pF on-chip capacitor. The
CA3401 is ideally suited for applications in
industrial control systems, automotive electronics, and general purpose amplifiers, e.g.
oscillators, tachometers, active filters, and
multichannel amplifiers.
The CA3401 is supplied in a 14-lead dual-inline plastic package (E suffix), a hermetic
gold-chip in 14-lead dual-in-line plastic package (G suffix), in chip form (H suffix). and
as a hermetic gold-chip (HG suffix).
It
is a direct replacement for the Motorola
MC3401 P, and is pin-compatible with the
Motorola MC3301 P and the National Semiconductor LM3900N. The CA3401 can be
operated over the temperature range of
-55 to +125 0 C, although the limit values of
certain specified electrical characteristics apply only over the range of 0 to + 75 0 C.

Applications:
•
•
•
•
•
•
•
•
•
•

Automotive
Constant-Current Sources
Multivibrators
Sample and Hold
Square-Wave Generator
Oscillators
Tachometers
Active Filters
Multi-Channel Amplifiers
Summing Amplifiers

CA3401
92CS-2.H95

Fig. 1 - Block diagram of CA3401.

MAXIMUM RATINGS, Absolute-Maximum

Values at TA = 25°C
DC SUPPLY VOLTAGE
+18
V
INPUT SIGNAL CURRENT
5
mA
DEVICE DISSIPATION:
Up to TA = 25 0 C .
. . 625 mW
Above TA = 2SoC. . Derate linearly 5 mW/oC
AMBIENT TEMPERATURE RANGE:
Operating .
-55 to + 12SoC
Storage .
-65 to + 150°C
LEAD TEMPERATURE (During soldering):

At distance 1/16 ± 1/32 inch
(1 .59 ± 0.79 mm) from case
for 10 seconds max.

300

Fig.2 - Open-loop voltage gain vs. frequency.

IOK e

AMBIENT TEMPERATURE (T A I-25-C

H-++l-kl-++Jjc~:~L~E~PNMcEE cr~~ i!~ ~n

DC

.00

~

-

~
No.3

13

9

Z

..

68

~

Z"" 8

~

Z"" B

~

2

4" 9

~

~

4 6 B

~

fREQUENCY (fl-Hz

Fig.3 - Output resistance vs. frequency.

+

...MeIENT TEMPERATURE (T A l-2S-C
lOAP RESISTANCE (Rll- SI(Q
.
,fOR TEST CIRCUIT SEE fiGURE 1

TO AMPLIFIERS

2,3,4

"
~
No.2

I

5

+

92CM-21630
10
IS
SUPPlT VOLTAGE (\It)- \I

FigA - Schematic diagram of CA34Dl.

280

Fig.5 - Open-loop voltage gain vs. supply voltage

CA3401E, CA3401G
ELECTRICAL CHARACTERISTICS AT TA; 25 0 C, V+; 15 V (Unless Indicated Otherwise}

1:

OJ .. MBIEHT TEMPERATURE ITAl025"C
FOR TEST CIRCUIT SEE FIGURE 4 _

~

B

qt:

LIMITS
CHARACTERISTIC

TEST CONDITIONS

Min.

Typ. Max.

13.5

-

14.2
0.03

0.1

10

13.5

-

5
0.5

10
1

-

Noninverting inputs open

-

6.9

10

Noninverting inputs grounded

-

7.8

14

-

50

300

-

500

UNITS

STATIC
Output Voltage:
High, VOH
Low, VOL
Max. Undistorted Output Swing,
VOP-P

OOC

I

~

VIO

g

V9

0.

~

;;: 3

OL-__________________

~--~_

HOR. SCAN

TIME-,.,.s

Fig. 5- Typical waveforms for video outputs.

180

IOO~F

n
> 12

loon

...I
ii'

AGe TO
RF AMPL.

Ikn

v+

9

~

o 6

12 V

1.2 kG

AGe TO

u

IF AMPL.

"

.. 3

Fig. 4- Test circuit for CA270AW, CA270BW, and CA270CW.
FREQUENCY- MHz

ELECTRICAL CHARACTERISTICS at TA = 25 0 C, Supply Voltage (V+) = 12 V,
and Referenced to Test Circuit (Fig. 4).
CHARACTERISTIC
Supply Voltage, V+
Supply Current, 1+
(See Fig. 2)
Video o,aracteristics:
DC Output Voltage,
Term.9 (See Fig. 5)
DC Output Voltage,
Term.l0 (See Fig. 5)
Sync Tip Output
Voltage, Term.9
AC Input Voltage,
Terms. 1,2
Input Res.,Term.l
Input Res., Term.2
Video Bandwidth,
Term.9
Differential Gain
Differential Phase
Intermod. Products:
Beat Freq.,l.6 MHz
Beat Freq.,2.8 MHz
Rejection at Carrier
Freq., Terms.9, 10, 11
Rejection,Twice Carrier
Freq.,Terms.9, 10, 11
AGC Characteristics:
Sat.Voltage, Term.4
Sat. Voltage, Term.5

TEST CONDITIONS

MIN.

V+=12 V
V+=12 V

10.2

22

5.7
5.8
5.5
5.6
5:7
5.5

13.8
56

6.3
6.2
6.5
6.4
6.3
6.5

-

V

Output=AGC thres·
hold (non·gated)

-

Input for output=
AGC threshold

50

70

100

mV

3.3

-

3.3
5

-

Kn
Kn

At output = -3 dB

-

MHz

See Note 1
See Note 1

-

-

10
10

%
deg

See Note 1 (95% sat.
blue colour bar)

-

-60
-67

-

dB
dB
dB

-

dB

Zero Signal

CA270AW
CA270BW
CA270CW
CA270AW
CA270BW
CA270CW

V
mA

12
40

6
6
6
6
6
6
3

Zero Signal

Fig. 6- Typical AFC characteristic.

TYP. MAX. UNITS

V

>

12

I

~ 9

V

§

6

u

"

.. 3

E=====~70~~-----------------SIGNAL INPUT-mV

92CS-26933

F=Video Carrier;VIN
for Term.9(dc)=3.7V
F=2X Video Carrier;
V IN for Term.9(dc)
=3.7 V

-40

-

-40

-

Zero Sig.; 14 = 10 mA
Zero Sig.; 15 = 10 mA

-

Fig. 7-Typical AGCcharacteristics.

12

V9

O'L---------------~I~OO~-­
SIGNAL INPUT-mV
nCS-26934

Fig. 8- Typical transfer characteristics.

0.7

-

0.3

V

1.2

V

_____________________________________________________________________ 293

CA270 Types
ELECTRICAL CHARACTERISTICS at T A = 250 C, Supply Voltage (V+) = 12 V,
and Referenced to Test Circuit (Fig. 4).
CHARACTERISTIC

TEST CONDITIONS

MIN.

Breakdown Voltage.
Terms. 4,5

14 or 15=1 mA (sink)

14

(Cont'd)

TYP. MAX. UNITS

-

-

V

10

-

-

6

-

0.5

dB

-

V

V

1.8

-

Kn

-

-

-

Positive noise pulses

-

6.6

-

V

Inversion Threshold,
Term. 9

Negative noise pulses

-

2.2

-

V

Noise Inversion
Sensitivity,Term.9

Signal inversion threshold
for complete inversion

-

10

-

mV

-

-

-

0.2
0.1
0.3

V

Control Current,
Terms. 4,5
Current Ratio 14/15
Input Signal Increase
with resp. to AGC
Threshold (See Fig.7)

15 = 1 mA
AGC from threshold
to max.

-

AGC Gating Pulse Input, Pulse voltage-V to 0;
Term. 7 (optional)
See Note 2

2

-

Input Res.,Term.7
AFC Characteristics:
(See Fig. 6)
Output Voltage,
Term. 11
Output Voltage,
Term. 11
DC Offset Voltage,
Term. 11
Noise Inverter
Characteristics:
Inversion Threshold,
Term. 9

CA270AW
CA270BW
CA270CW

f = fa ± 0.2 MHz

CA270AW
CA270BW
CA270CW

f = fa ± 1.2 MHz
Zero Sig.; measured
across RL =
50 Knto +6 V

CA270AW
CA270BW
CA270CW

10
10

10
10

-1.7
-1

mA

-

1.7
1

Vp .p

Vp . p

V

-

Video Inversion

Characteristics:
Video Inversion,
Term. 9 (at
low carrier levels)

Carrier increase

from 0 to 5 mV
(appx.8% carrier)

CA270AW
CA270BW
CA270CW

Note 1: CCIR modulation system, peak white = 10% carrier.
Note 2: Maximum pulse amplitude must never exceed the supply voltage (V+1.

APPLICATIONS
The diagram shown in Fig. 3 is typical of the
type of circuit used in a practical application
of the CA270 series devices.
Video Detector
The if input signal may be applied push·pull
to terminals 1 and 2, or single-ended to either
terminal 1 as shown, or to terminal 2. These
input terminals are internally biased.
The detector tank circuit can be tuned by
applying a 50 mV cw signal of video if frequency to the input and adjusting the inductor L1 for maximum differential output
between terminals 9 and 10. The input signal is then reduced to 25 mV and L1 is readjusted for maximum output.

AFC Detector
The afc quadrature tank circuit should be
tuned only after the detector adjustment has
been made. Using the same input signal, inductor L2 should be adjusted for 6 V dc
output at terminal 11_ The 0.5-pl' quadrature
phase-shift coupling capacitors can affect
symmetry and actual values will depend on
the layout used_ When L1 and L2 are properly
tuned, the output swing at terminal 11 will
be 10 volts minimum for frequencies of
±0.2 MHz to ±1.2 MHz about the if carrier
frequency.

AG C Detector
The agc threshold, corresponding to sync tip
level, is approximately 3 volts at terminal 9.
Full age potential will be developed if the
input signal increases by 0.5 dB maximum
with respect to the th reshold val ue. The agc
control at terminal 4 is intended for tuner
control. The age control at terminal 5 is for
forward age control of n-p-n transistors in the
if amplifier. When sinking 10 mA, the zerosignal agc voltage at terminal 4 is 0.3 volt
maximum; at terminal 5, it is 1.2 volts maximum.
The design of the device is such that the sink
current at terminal 4 is a minimum of 6 times
that at terminal 5. The rf age sink current begins to decrease when the if sink current is
about one-sixth of that required to saturate
the rf agc output at terminal 4. The rf agc
delay may be adjusted by means of a variable
resistor between terminal 5 and ground. This
adjustment modifies the if system gain, thus
affecting the rf delay threshold. At maximum
gain the current into terminalS is large compared to the current in the variable resistor
and adjustment is ineffective. As the signal
increases and rf agc is applied, the terminal 5
sink current approaches zero and the if agc is
determined by the value of the variable resistor.
A horizontal gating pulse may be applied to
terminal 7 to gate the agc detector. The
agc threshold (sync tip) decreases approxi·
mately 0.3 volt at terminal 9 when gating is
used. The gating pulses must be negativegoing with a recommended minimum amplitude of 3 volts. They may be ac or dc coupled,
but the maximum peak value must not exceed the dc supply voltage at terminal 3. If
dc coupling is used, the potential during flyback should be less than 0.5 volt and during
scan, greater than 1.5 volts.
. Noise Inverter
Noise pulses in excess of 6.6 volts at terminal
9, which would result in "white spots", are
processed in the device by inverting and
clamping them to near black level (approx.
3.6 V). Noise pulses at levels of less than 2.2
volts at terminal 9 which would result in
sync noise interference, are inverted and
returned to black level.
Complete inversion occurs for signals 1'0 mV
above the inversion threshold.

294 _____________________________________________________________________

CA758E
RC Phase-Locked-Loop Stereo Decoder

Features:
• low distortion (THO): 0.4% (typ.)
• Excellent SeA rejection: 70 dB typo

For FM MUltiplex Systems

ACA·CA758E is a monolithic silicon integrated circuit RC
phase-lock loop stereo decoder intended for FM solid·state
stereo multiplex: systems.

The decoder uses a minimum of external components, and
requires one adjustment (oscillator frequency) for complete
alignment. In addition, the CA758E provides automatic monostereo mode switching and energizes a stereo indicator lamp.

The CA758E is pin compatible and electrically equivalent to
industry types J.lA758. MC1311P, LM1800. and ULX2244.

FILTER

Power supply range: 10 to 16 V de
Requires only one adjustment for complete ali""ment

• Stereo indicator lamp drive: 150 mA typo

F~~tR t~R~

SWITCH

RC oscillator
High-audio-channel separation: 45 dB

• Low-impedance outputs

The CA758E is supplied in a 16-lead dual-in-line plastic
package and operates over an ambient temperature range of
-40 to +85 0 C.

The CA758E decodes the multiplexed stereo input signal into
left and right channel audio output signals. The decoder also
suppresses SeA (storecast) transmissions when present in the
composite stereo signal.
MAXIMUM RATINGS, Absolute-Maximum Values at TA

•
•
•
•

RC N~iioRK

,

=2!PC

OC Supply Voltage.
DC SupplV Voltage (for <:a 1S-second period) .
DC Voltage at Term. 7 (Lamp Driver Circuit with lamp "OFF"'I.

+18 V
+22 V
+22 V

DO\Iice Dissipation:
730mW

Up to T A " 70°C

9.1 mW/oC

Above T A = 70 0 C derate linearly
Ambient Temperature Range:

-40 to +B50C

Operating.

. -65 to +150 o C

Storage
lead Temperature (During soldering):

L

+ ____+-_________

_____

It·_HI

4--_--t-(lll1 TEST SIGNAL

At a distance not less than 1/32"' to.79 mm)
from case for lOs max.

,
L.EFT RIGHT
CHANNEL.
OE-EMPHASIS

Fig. , - Functional block diagram of the CA 7S8E.

ELECTRICAL CHARACTERISTICS

CHARACTERISTIC

TEST CONDITIONS
(Reflll'enced to Fig 7 unless oth_ise specified)
V -12V,T A "25.oC
Multiplex Input Signal (L-R, pilot "OFF")
"'lOO mV RMS
19-kHz Pilot Leval .. 30 mV RMS
f (modulation 1 .. 400 Hz or 1 kHz

LIMITS

Min.

UNITS

Typ.

M".

26

35

Static Characteristics
Total Current

Lamp "OFF"

Maximum Available Lamp Current

75
~

DC Voltage at Term. 7 (Lamp Driver!

I (lamp)

50 mA

DC Voltage Shift at either Term. 4
or 5 (Output)

Stereo· to-Mono Operation

1.3
30

mA
mA

150
1.8
150

V
mV

Dynamic Charact.-istics
Power Supply Ripple Rejection

For a 200·Hz, 200·mV RMS Signal

Input Resistance

45

20

35

0.9

Output Resistance
Channel Separation (Stereo)

35

Atf=100Hz
f = 400 Hz
f·

30

At f '" 1 kHz

2.0

40

d8

45

d8
dB

45

10 kHz

Channel Balance (Monaural)
Voltage Gain

1.3

dB

0.5

kn

0.3

1.5

d8

0.9

1.4

V/V

Pilot Input level:

IS

20

19·kHz Input

Lamp "ON"

19·kHz Input

Lamp "OFF"

2.0

7.0

Hysteresis

Lamp "OFF"

3.0

7.0

±2.0

±4.0

±6.0

0.4

1.0

Capture Range (Deviation from
76·kHz Center FreQu~~ncy)
Total Harmonic Distortion

Multiplex Input Signal., 600 mV RMS
Pilot "OFF")

25

19·kHz Rejection

25

38·kHz Reiection
SCA (Storecast) Rejection

Measured Composite Signal; 80% Stereo,
10% Pilot, 10% SCA

Voltage-Controlled Oscillator (VCO)
Tuning Resistance

Total Resistance (Term. 15 to 81
required to set
fRI=F = 19kHz ± 10Hz (Term. 111

Voltage-Controlled Oscillator

0 0 on is eVidenced by a shift in bias voltage at Term. 2
Maintain this potentiometer setting for all the dynamIC tests.

312 __________________________________________________________________

CA1398E

I

I

I
I
I
I
<1531

I

I

I
I

I
I

I

Fig. 3 - Schematic diagram of the CA 1398E.

TEST SET-UP PROCEOURE FOR OSCILLATOR
Remove the horizontal keying and chroma inputs and adjust
eX to obtain a free-running oscillator frequency of 3.579545

MHz ±10 Hz. Under the same Test Conditions described in the
Electrical Characteristics Chart for Oscillator Lock·Up. vary II
(approx. 20 ~Hl and/or Cl (approx. 1000 pF) to obtain the
initial conditions for amplitude and phase oscillator lock-up.

CHROIolA GAIN
CONTROL

'-":1,':,".--'YoI'v-----r---rO.05

-I
CHRQIIoIA
OUTPUT

UNLESS INDICATED OTHERWISE
CAPACITANCE VALUES ARE IN

hllCROfARAOS

Fig. 4 - rVpical SUllie and dynamic characteristics test circuit fDr the CA 1398E.

________________________________________________________________ 313

Preliminary Data

CA2002, CA2002M

8-Watt Audio Power Amplifier
For Automobile Radios

4

OUTPUT

:3

GROUND

2:

INVERTING INPUT
NON INVERTIN' INPUT

~'

Features:

TOP VIEW

• Load dump voltage surge protection

• Hermetic Gold·CHIP encapsulated in a 5·lead plastic
T0-220-style package (Versa;V)
• Output short-circuit and thermal overload protection
• Drives load impedance as low as 1.6

'IIV.

IO II

n

The RCA·CA2002 is a monolithic silicon
class B audio power amplifier designed for
driving loads as low as 1.6 n. It provides a
high output current capability (up to 3.5A),
very low harmonic and cross·over distortion,
and load·dump voltage·surge protection.

TERMINAL ASSIGNMENT

• Output current capability of up to 3.5A
• Fewexternalcompdnents
• Versa· V power transistor package· requires
no electrical insulation

MAXIMUM RA TI NGS, Absolute·Maximum Values:
PEAK 'SUPPL Y VOLTAGE 150 ms)
DC SUPPLY VOLTAGE
OPERATING SUPPLY VOLTAGE
OUTPUT PEAK CURRENT:
REPETITIVE
.
NON·REPETITIVE .
POWER OISSIPATION, Po at TA = 90°C
THERMAL RESISTANCE, JUNCTION TO CASE
AMBIENT·TEMPERATURE RANGE:
OPERATING.
STORAGE
LEAD TEMPERATURE lOURING SOLDERING):
At distance 1/16 ± 1/32 inch 11.59 ± 0.79 mm)
from case for 125 max.

The CA2002 is supplied in a hermetic trio
metal Gold·CHIP encapsulated in the 5·lead
plastic TO·220·style Versa·V package. All
leads (except term. 3) are electrically in·
sulated from the mounting flange, elimi·
nating the need for insulating hardware.
The VERSA·V package is available with two
lead configurations. The CA2002 has a vertical·
mount lead form, and the CA2002M has a
horizontal-mount lead form.

40 V
28 V
18V
3.5 A

4.5 A
15W
4°C/W
See Figure 16

-40 to +150oC

260°C

r-----,--QV·
,oonF

1

R2
2.2n

'V

,.

Fig. 2 - Test circuit.

NOTES:
IS SIGNAL GROUND

SUPPLY VOLTAGE (V+)-V

-+

ALL RESISTANCES ARE IN OHMS

1 - Schematic diagram.

Fig. 3

Typical quiescent output voltage as a
function of supply voltage.

314 _______________________________________________________________

CA2002, CA2002M
ELECTRICAL CHARACTERISTICS at TA = 25°C, V+ = 14.4 V
Unless otherwise specified (See Figure 2)

10

LIMITS

TEST CONDITIONS

CHARACTERISTIC

60

UNITS

Min. Typ. Max.
-

18

6.4

7.2

8

-

45

80

4.8

5.2

-

8

8

Supply Voltage. V+
Quiescent Output Voltage, Vo

Measure at Term. 4

Quiescent Drain Current, 10

Measure at Term. 5

Output Power,PO

THO = 10%, A = 40 dB,
f = 1 KHz
RL =Hl

-

10

400

-

PO =0.5W, RL =4n

-

15

-

PO =0.5W,RL =2n

-

11

-

PO=5.2W,RL =4n

-

55

-

PO=8W, RL = 2n

-

50

-

RL = 2 n
RL = 4 n
RL = 2 n

Input Saturation Voltage, VI(RMS)

V

7

-

6.5

SUPPLY VOLTAGE

W

Frequency Response (-3 dB)

R L = 4 n, Cx = 39 n F,

40 to 15000

(V~l-V

Fig. 4 - Typical quiescent drain current as a
function of supply voltage.

AMBIENT TEMPERATURE (TA)' 25"C.
Ao040dB, 1·1 kH,. THOoIO%

mV

A-40 dB, f-1 KHz

Input Sensitivity, el

20

mA

20

-

V+= 14.4V
V+= 16V

V

·
r

g

mV

20

~ 10

40

o~

,

Hz

R X = 39 n (See Figs. 15,20)
10

Input Resistance, R I (Term. 1)

f = 1 KHz

70 150

-

Kn

Open-Loop Voltage Gain, AOL

RL-4n,f-1KHz

-

80

-

dB

Closed-Loop Voltage Gain, A

RL -4n, f= 1 KHz

39.5

40

40.5

dB

Input Noise Voltage, eN

Freq. Resp. = 40 to
15,000 Hz (-3 dB)

-

4

-

Il V

Input Noise Current, iN

Freq. Resp. = 40 to
15,000 Hz (-3 dB)

-

60

-

pA

PO =5.2W,R L =4n

-

:
68

-

PO=8W,RL=2n

-

58

-

30

35

-

A=40 dB, f= 1 KHz
Efficiency,

7)

Power Supply Rejection Ratio, PSRR

RI:=4n,A=40dB,
Rg= 10Kn, fripple= 100Hz,
V ripple = 0.5 V

SUPPLY VOLTAGE

Fig. 5 -

15

(v·,-v

Typical output power as a function of
supply voltage.

AMBIENT TEMPERATURE(TA,)o25"C.
A-40dB, ,., kHz, THO-IO%

•I
?

·
~

%

dB

10

.v
10
l!i
LOAD fiESISTANCE (RLI-ll

Fig. 6 -

CLOSED-LOOP VOLTAGE GAIN (A)

CLOSED-LOOP VOLTAGE GAIN (A)

Fig. 7 -

Typical input voltage as a function of
closed·loop voltage gain.

Fig. 8 -

Typical input voltage as a function of

closed-loop voltage gain.

20

Typical output power as a function of
load resistance.

CLOSEO-LOPP VOLTAGE GAIN CA)-(!8

Fig. 9 - Typical power supply. rejection ratio as a
function of closed-loop voltage gain.

315

CA2002, CA2002M
o

11

1 -10

it

AMBIENT TE~RATURE ITAI- 2S·C

~t- :r:~:'~:5Y
A,-lOkO

Ii

~-20~t-

A-40dB

Ii

!i -1IO

!i

~

~
RZ-Z.20

v.
I--

rJ.•. ,.

t'\.

i

-7<

00

v II

. ... . ... . I . ..,
102

• o•

10'

POWER lPoI-W

10'

OUTPUT POWER (Po)-W'

FREQUENCY In-Hz

Fig. 10 - Typical power supply rejection ratio as a
function of frequency.

Fig. 11 - Typical power dissipation and efficiency
as a function of output power.

I

supp\..y VOLTAGE (Y+)-V

AMBIENT TEMPERATURE ITAI--c

Fig. 13 - Maximum power dissipation as 8 function
of supply voltage (sine-wave operation).

.i

80

~
~

a function of ambient temperature.

Fig. 15 - Typical values of capacitor eX (see test
circuit, figure 20) for different values
of frequency response..

" I'--j-...

~ eo

~

CLOSED-LOOP VOLTAGE GAIN IA)

Fig. 14 - Maximum allowable power dis;;;~;i;~ as

100 AMBIENT TEMPERATURE ITA'-2S-C

~
1/

Fig. 12 - Typical power dissipation and efficiency as
a function of output power.

I'--

40

"t----

V~·14.4V

20

0

. .. . ... . .

10

10

10'

FAEQUENCY If)-Hz

Fig. 16 - Open.foop voltage gain as a function of
frequency.

CASE TEt.I'ERATURE ITcl-·C

Fig. 17 - Output power and drain current as a
function of case temperature.

316 __________________________________________________________

Preliminary Data

CA2004, CA2004M

12-Watt Audio Power Amplifier

Features:

plastic TO·220·style VERSA·V package. All
leads (except term. 3) are electrically in·
sulated from the mounting flange, elimi·
nating the need for insulating hardware. The
VERSA·V package is available with two
lead configurations.
The CA2004 has a
vertical·mount lead form, and the CA2004M
has a horizontal·mount lead form.

The RCA·CA2004 is a monolithic silicon
class B audio power amplifier designed for
driving loads as low as 3.2 n. It provides a
high output current capability (up to 3.5 A),
and very low harmonic and cross·over dis·
tortion.
The CA2004 is supplied in a hermetic trio
metal Gold·CHIP encapsulated in the 5·lead

• Hermetic Gold·CHIP encapsulated in a 5·lead
plastic TO·220·style package (VERSA·V)
• Thermal overload protection
• Drives load impedance as low as 3.2 S2
• Deflection amplifier capability
• Output current capability of up to 3.5 A
• Few external components
• VERSA·V power transistor package·requires no
electrical insulation

MAXI MUM RATI NGS, Absolute·Maximum Values:
DC SUPPL Y VDLTAGE
OPERATING SUPPLY VOLTAGE
OUTPUT PEAK CURRENT:
REPETITIVE
NON·REPETITIVE. . . . . .
POWER DISSIPATION, PD at T A ~ 90°C
THERMAL RESISTANCE, JUNCTION TO CASE
AMBIENT·TERMPERATURE RANGE:
OPERATING
STORAGE
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1/16 ± 1/32 Inch (1.59 ± 0.79 mm) from case for 12

28 V
26 V
3.5 A
4.5 A
15 W

4°C/W
OtO+12S:C
-40 to +150 C
5

v'
OUTPUT
GROUND

t

INVERTING INPUT
NON' INVERTING

INPUT

TOP VIEW
9ZCS -2922lRI

TERMINAL ASSIGNMENT

max.

, - - - - - T - - oV +
,oonF

r

Thermal Shut·Down
IOOOl"f

25 V

Thermal shut·down occurs if the output
overloads (temporary or permanent), the
ambient temperature is excessive, or the
junction temperature is excessive. None of
these conditions results in device damage.
They merely cause a temporary automatic
reduction of output power and drain cur·
rent.

.2

470l"F

22n

3V

5%

470l"F

92CS-JOB59

Fig. 2 - Typical application.
Fig. 1 - Test circuit.

C.

02
01

22n

33nF

IOO~F

3V

20n

C8

07

0'

ISnF

390£1
08
3900

06

3900

2.20

Fig. 3 - 25 W circuit-bridge application.

_____________________________________________________________ 317

CA2004, CA2004M
ELECTRICAL CHARACTERISTICS at T A
Unless otherwise specified (See Figure 1)
CHARACTERISTIC

=2SoC, V+ =24 V
LIMITS

TEST CONDITIONS

UNITS

Min. Typ. Max.

-

26

V

Measure at Term. 4

11

12

13

V

Measure at Term, 5

-

40

100

mA

I RL = 4 n

10

12

-

W

I RL = 8 n

-

8

-

Supply Voltage, V+
Quiescent Output Voltage, Vo
Quiescent Drain Current, I D

Output Power, Po

8

THD = 10%, A = 40 d8,
f = 1 KHz

Input Saturation Voltage,
400

VI(RMS)
Input Resistance, RI (Term. 1)

-

-

mV

f = 1 KHz

70 150

-

Kn

RL=8n,f=IKHz

-

80

-

d8

RL=8n,f=IKHz

39.5

40

40.5

d8

Freq. Resp. = 40 to
15,000 Hz (-3 dB)

-

4

-

JJ.V

35

-

dB

Open· Loop Voltage Gain,
AOL
Closed· Loop Voltage Gain,
A
Input Noise Voltage, eN

RL =4n, A=40dB,
Power Supply Rejection Ratio,
Rg = 10 Kn, f ripple = 100 Hz,
PSRR
V ripple = 0.5 V

30

318 ____________________________________________________________________

CA3035, CA3035V1

Ultra-High-Gain Wide-Band Amplifier Array

SCHEMATIC DIAGRAM FOR CA303S AND CA303SVl
IA,.iPi:~1

I

I
I
I,

• Three Individual General-Purpose Amplifiers
• Ideal for urvice in Remote-Control Amplifiers - - e.g., TV Receivers
• Available in two electrically identical versions: CA3035 with straight

leads; CA3035Vl with formed leads
I

HIGHLIGHTS

I

• Thr•• separate amplili.r' goin and bandwidth lor eoch amplifi.r can be adjusted
with luitabl. external circuitry

L.
I~

• Wid. operating temperotur. range .55°C to +125°C

• Amplifiers operabl. independently or in cascade
• eMceptionally high (encad. voltage goin_
129 dB typo at 40 kHz
• Low noi •• performance

• All amplifiers lingle.end.d only one power supply requir.d

I

• Built·in temperature compensotion
• Hermetically sealed. oll·w.ld.d lO·t.od TO-5-.tyl.

• Wid.·bond ,e'ponn

m.tal pacltag. with .traight or farm.d I.ad •

I

GNO"

L' __

ABSOLUTE·MAXIMUM RATINGS:

Operating Temperature Range
Storage Temperature Range
Device Dissipation
Input Voltage
Supply Voltage
Lead Temperature (During Soldering):
At distance 1/16 ± 1/32 inch (1.59 ± O.79mm)
from case for 10 seconds max.

.. ·SSoC to +125°C
·65 o C to +1 50°C
300mW

TYPICA.L REMOTE CONTROL SYSTEM

...... IVp.p
... +15V

ELECTRICAL CHARACTERISTICS AT TA = 25·C

CHARACTER I ST I CS

SPEC I AL TEST
CONDITIONS

SYMBOLS

TEST
CIRCUITS
AND
CHARACTER I STiCS
CURVES

Mi n.

-

L I MI TS
CA3D35,

CA3D35V I

Typ.

UN I TS

I Max.

STATIC CHARACTERISTICS

Quiescent Ope rat i ng
Voltage

V3
v5
V7

vee = +9v

Fi g. 3

Tota I Current Ora i n

Id

VCC = +9V,
RL3 = 5Kfl

Fig.3

-

2
1.9
4.9

--

V
V
V
rnA

3.5

5

7.5

40
40
38

44

-

DYNAMIC CHARACTER I STICS

Voltage Gain:
Amp! ifier No.1
AmRo! ifier No.2
Amp! ifier No.3
Output Va I tage Swi ng

Input Res i stance:
Amplifier No.1
Ampl ifier No.2
Ampl ifier No.3
Output Res i st ance

AI
A2
A3

Vout
V lout
V20ut
V3 0ut

f

= 40 kHz,
Vce = +9V

RLI = J DKfl
RL2 = 10Kfl
RL3 = 5Kfl
5i nusoi da I
Output,
Vce = +9V

R lin
R2 i n
R3 i n

f

= 40 kHz

R \ out
R2 0ut
R3 0ut

f

= 40 kHz

Bandwi dth at
-3dB po i nt:
Amplifier No.1
Amp\ ifier No.2
Amp! ifier No.3

BWI
BW2
BW3

VCC = +9V

No i se F i gu re
Ampl i fier No.1

NF I

f

Sens i t i v i ty

= I kHz,
RS = I Kn

VCC = + 13 V
Relay IKII
Cu rrent = 7.5 rnA

46
42

-

2
2.6

-

50K
2K
670

-

8

270
170
lOOK

-

-

dB
dB
dB
Vp-p
Vp-p
Vp-p

'Icc'

+~'I

n
n
n
n
n
n

Fig.3

NOISE FIGURE TEST CIRCUIT

-

500
2.5
2.5

-

kHz
MHz
MHz

Fi g. 4

-

6

7

dB

Fi g. 2

-

100

150

!LV

F g.5
F g.6
F g.7

Flg.2

STATIC CHARACTERISTICS TEST CIRCUIT

QUAN TECH
LA80RATORIES
IroIOOEL No. 311
NOISE ANALYZER
(SEE NOTEI

NOTE: SET ALL INTERNAL POWER SUPPLIES ON QUAN TECH
NOISE ANALYZER TO ZERO VOLTS.
Fig."

__________________________________________________________________ 319

CA3041

Wideband Amplifier, FM Detector, AF Preamplifier/Driver
FEATURES
ehigh-sensitivity -

input limiting voltage (knee)

=

150 p.V typo at 4.5 MHz

For Sound Sections of TV Receivers Using
Tube-Type AF, Output Amplifiers

• internal Zener.diode-regulated voltage supply
.'ow harmonic radiation

.Iarge audio drive voltage capability

.wid. frequency capability -

eexco;,ilent AM rejection - 58 dB typo at 4.5 MHz

<100 kHz to> 20 MHz

.'ow harmonic di stortion

• inherent high stability - internolly shielded
RCA Integrated Circuit Type CA3041 provides, in a single monolithic silicon chip. a
major subsystem for the sound sections of TV receivers. As shown in the Schematic Diagram

g

-

~

ill

'"w


!:
0

2:-

I-

~

l-

0
W

ffi ~

-'

'-'

>

~

I-

11

t;

i;j

'-'

0

0

II

r"
::J
~

~ -

~

-'
-'

~

-'

~

l-

'-'

~

~

~I- W

g
-'

~

I
I-

~

'"w'"

~

l-

~

I-

~

~

I-

~



'"e;

l",-,

~

-

0

g
l-



tc !:
'w" '" > OJ
Iw

0

'-'
0

-'

~
W

g

~

~

0

'-'

I-

 '100

Flg,4 - Typical IF-amplifier voltage gain and
input.limiting voltage (knee) characteristics.

-

dB
dB

kO
kO

400

~

-

-

5

il

600 >

X
FREQUENCY UI-MHl

58
67

-

~

.00 ~

,,!!

~

56

2

150 200 (rms)

45

-

1. At FM-Detector Output

AF·Driver Voltage Gain

mW
mW
mW

10.5 11.2 '12.3

Ro
Co

AF.Amplilier Input Resistance
AF·Amplilier Output Resistance

120 145 170
115 150 175
130 155 180

0.15 0.63

Parallel Output Capacitance

Parallel Output Resistance

Min. Typ.

~

..."

1000 Gj

" .J-

..

~

~
Max. Units
Fig.

-

V14

Quiescent Operating Current
(into Terminal 11)

TYPE
CA3041

SPECIAL CONDITIONS

11

TYPICAL
CHARAC·
TERIS·
TICS

64

.

ot

IJ

I

3:
LIMITS

OOC
TA = • 150C
.85 C

"00

ITAI·Z5"C

," vtJTIJ

TEST CONDITIONS
CHARACTERISTICS

IEjErtURE

"

PROCEDURE:
A • Voltoge Gain:

11 Set input frequency at desired value, Vi - 100 J.t V ntIs.
2) Record va'
3) Calculate Voltage Gain A from A· 20 IOi10 vo/vi
4) Repeat Stepe 1.2, and 3 for each frequency and/or
for temperature desired.

Fig.S - Test ""tup 'or measurement a/IF-amplifier
yo/fog. gain.

8

PROCEDURES:
Recovered AF Voltage:

1. Set Input Signal Generator as followe:
Output frequency· 4.5 MHz
~~ei~~it~~g. r,;~e~H~ 1 kHz
Output levp.l for Vin • 100 mV nns
2. Set volume control for maximum
af output.
3. Measure af output voltage and record
as Recovered AF Voltage.

..

Fig.6 • Test setup for measurement of
AF.omplifier vo/toge gain.

Total Harmonic Diltorti!;)n:

1. Adjuet volume control for an af output

.
..

voltage of 300 mV nne.

BOONTON
TYPE 207H
U'IINERTER
OR e=~~~ENT

I

.,...00047

?

0:-

TYPE 202H

I'F

2. Measure Total Hannonic Dietortion of

the output signal in accordance. with
the- Operating Instructions for the Die·
tortion Analyzer.

Input Limiting Voltoge (Kne.):

AM-FM

GENERATOR
OR EQUIVALENT

1. Decreaee Vin until the af output voltage
i8 3 dB lee8 than the value eet in Step 1
of the procedure for measurement of
Total Harmonic Dietortion
(300 mV. 3 dB .. 210 mV)
2. Measure resulting value of Vin and re·
cord se Input Limiting Voltage (Knee).

..

,

r-...

T )a
3

•

~ )6

I ,~

1\
\

"
"

• TRW ElectroniCS. Des Plaines, Illinois. Palt No. E023874, 01 equivalent.

AIroI8IENT TEMPERATUIlE ITAI·Z5·C

2

~

6 8 I

S 8 10

... , .,

~oo

fREOUENCY tll-kHI

Fig.7 _ Test setup lor m.asurem.nf 01 input limiting yo/tage (Kn.e),

recover.d AF yoltag., and total harmonic distortion.

Fig.8. Typical AF.driver voltoge-g"in ch"rocteristic

________________________________________________________________ 321

CA3041
PROCEDURES,

1. Set FM Sianal Generator as tollows:
Output frequency· 4.5 MHz
~~eh!:~~' ~;eki'i~" 1000
Output level for Vin .. 100 mV rms
2. Set AM Siplll Generator aa follows:
Output frequency .. 4.5 MHz
Modulating frequency" 1000 Hz
Per· cent modulation" 30
Output Jevel for Vin .. 10 mV rma

.

Hz

3. ~~hV~\~~!::~i~~:nr::~7F~;. Out·
4. ~!hV~\~~!:~t~~~~rdm::'tU;A~;' Out-

SOONTON
TYPE 202M
AM-fM
GENERATOR

5. Determine AM Rejection from
AMR" Vo(FM)/VoCAMl

OR EOUIVALENT

Fig.9 ~ Typical AM reiection characteristics

.. TRW Electronics. Des Plaines, Illinois, Palt No. E023874,

01

equivalent.

lor CA3041.
Fig. 10 _ Test ntup frw m"asurement 01 AM rei.cIion.

+140V

PROCEDURES,
Totol Device D, .. lpotionl
1. Close 810 open 822. Measure and record V14 and IT.
3. Determine Total Device Di88ipationfrom P'i'- VI4IT.
Qul •• cent Operatln; Current Into Terminal 1 h

1. Close SI. open 82.
2. ~~~si~r;;, 11!~r:a{el~~rd

88

Quiescent Operatinl Cur-

9.Volt Current Dralnl

1. Open SI. close S2'
2. Measure 114 and record as 9...Volt Current Drain.

Fig."" Test setup lor total din/pation, quiescent operating curren'
Into t.rminol Ho.1', and 9.vo/t current drain.

B.

\....." I
TRAHSF.

I
\

I

o.OI,..F

'----~-_t----'

L ___ ='MCJ

• TRW Electronics, Des Plaines, Illinois. Part No. E023874. or equivalent.

Fig. 12 • Block diagram 01 typical TV receiver using CA304J.

322 __________

~

______________________________________________________

Wideband Amplifier, FM Detector,
AF Preamplifier/Driver

CA3042
FEATURES

• high sensitivity - input limiting voltage (kneel :::
150 IJ.V typo at 4.5 MHz
• 6-mA audio drive capability
• excellent AM rejection - 58 dB typo at 4.5 MHz
• inherent high stability - internally shielded

For Sound Sections of TV Receivers Using Transistor·
Type AF Output Amplifiers

RCA Integrated Circuit TyPl' Ct\:1042 provides. in a singll' munolithic silicon chip. a
major sub-system for the sound st.'clions of TV reccivl·rs. As shuwn in the Sl'hematiC' Diagram (Fig.ll and the TV Receiver Block Diagrams Wjgs.2A and 2H) the CA:3042 contains a
multistage wide-band if-amplifil'r Hedinn, an FM-dctcctor stuge. u Zener-dinde-rL·guluted
power-supply se<.'lion. and an af-amplifier section specifically designed to drive dircdly an
n-p-n audio output transistor or a high-~ain audio output pentodl' tube.
In FM receivers. the CA:1042 l'an be usro tu provide ir amplificalion and limiling. FM
detection, and af pre amplification.
The CA3042 provides exceptional vcrslltility of circuit dl!sign because tht' if-amplifit·rl
limiter seelion, fo'M detector section. and uf-prl'nmplificr/drivl'r s(,'(.'tion l'an Ix' USt'20 MHz
low harmonic distortion

MAX I MUM RATI NGS, Absolute·Max imum Values:
OPERATING-TEMPERATURE RANGE,.", _, _, _",., ...... ,. _ --40° to +85°C
STORAGE·TEMPERATURE RANGE ....................••.... _65" to +150"C
LEAD TEMPERATURE (During Soldering):
At distance 1/16 ± 1/32 inch 0,59 ± 0.79 mm)
from case for 10 seconds max. _.. , .. , .. ". _, _.,'.,., ....... , _ _ +265°C
MAXIMUM INPUT·SIGNAL VOLTAGE:
Between Terminals 1 and 3 , ..•.•••. ,' _ , . , , . , •• , • , • , , , • , _, _ . _, .•• ,. ±3 V
MAXIMUM DEVICE DISSIPATION:
p to +2SoC ...... , .. ,'., ..... ,.,.,.,.' ........... 950 mW
At Ambient
Temperatures above +25°C ., _,., ..... , ....... ,', .... Derate at 10.8 mWfC

ju

The CA3042 utilizes a 14-ll'ad duul-ill-Jim.' plm;til' puekagt' with Icarls sl)('ci~lI.v formed
to facilitate automatic insertion or thc dt'vic(' in suitably punehl'rl print('(I-l'irl'uil boards.

'.

-------11

Fig.' - Schematic: Jiagram.
• For XFMR Details see Fig.2(a)

Fig.2(b) - B/oc:k diogram 01 typical TV receiver utilizing
tire CA3042 and 0 12F XS, 6EHS, or equivalent.
G.2kO

.W

I
I
I

PROCEDURES:
Total Device Dissipotlonl

lYPE

+Z70 V

JN3195

1. Set switch S in position A
2. Measure and record Vl4 and 114'
3. Detennine Total Device Dissipation from PT = V14114
Quiescent Operating Current into Terminal 11:

1. Tum switch S to position B
2. ~::t~::to 11!r:i~aref1.rd as Quiescent Operating Cur9.Vo lt Current Drain:

Fig. 2(a) • Block diagram of typical TV receiver utilizing
transistor RCA-40313.

I. Set switch S in position B
2. Measure 114 and record as 9-Volt Current Drain.

F;g3 _ Test setup lor measurement 01 total device dissipation, quiescent curr.tnt into terminal No.1l. and
9-vo/t current Jra;n_

323

CA3042
ABSOLUTE-MAXIMUM VOLTAGE AND CURRENT LIMITS AT TA = 25°C
Indicated voltcs6 or ClQ7"ent limit. (or each terminal may be applied under the spec ified voltage
eonditioM for other terminal•• AlllJoltages are with respect to ,,-ollnd fTenninal 4),

VOLTAGE CONDITIONS AT OTHER TERMINALS
VOLTAGE OR
CURRENT LIMITS

TERMINAL

I

2

3

4

·5

7

6

8

9

10

11

~

S-

...J
<
;!;

...J
<
;!;

a

ill
UJ

o:
UJ
t-

ii!UJ

t-

12

13

14

-

1

-3V

+3 V

2

-3V

+3 V -310+3

3

-3V

+3 V -3 to+3

4

GROUNO (VOLTAGE -310+3
REFERENCE TERMINAL)

...J
<
2

~

-310 +3

20 rnA

5

~

0:

UJ
t-

...J

~

NO CONNECTION

6

-310+3

7

10 rnA

-310+3

8

lOrnA

-310+3

~

"'t-UJ

:o!
UJ
to

""~
0
>

U

0

-3 to +3

10 rnA

9

~

!;<

11

-310+3

10 rnA

10

fil

:::;
11.
11.

<

::;

...J
<

"'t-UJ
UJ
u
z
UJ

~
~

UJ
to
<

~

~
~

0
...J
<
2
UJ

"'~

+IOV -310+3

+2.5 V

~

2

UJ

12

<

liE

L0-

sa

<
2

ii!UJ

ffi
t-

~

51

sa

:::;

"'UJ
"''"0z "'UJUJ
5

U

+IOV -310+3

+2 V

0
t-

;:!

t-

~

:c
t-

:::;

:::;

...J
;:!

0

~

:>
0
to

"'

'"
t-

t0
t-

0
t0
...JUJ

0

~

~i2

11.

...JQ.

~Q.

"'<

~=:i

2
0

;::

«

~j

ffi
t-

z

~~

!;:!:
>-;0

...Jco
...Jo

~::
00

2UJ
t- O
0 2
2:>

sCi! 1rl
ll.'" 22 ~~ !a~
UJto
!:i!5
~~ toUJ
oz U0
ffil5 ~ 'i'i >2
~sa ~:i
f§!a
UJ
u...J
"-UJ

<~
~
0
>

to
<

~

0
>

c.>

U

...J
;:!

...J
;:!

0

"'UJ
~

0

'"
\';:

~

...J

~§

0<
t-to
0 2

tt-

...J
;:!

~

fu

tUJ

~

~

~
...J
;:!

~
...J
<
2

~

.ft;
~

:;;

xu

:;;

~

~
UJ
t-

0:

51t0
t0
UJ

:::;

~

11.
11.

~
...J
;:!

>...J

~

"'t-UJ "'t-UJ "'t-UJ

<

...J

~
~

t-

~

~

~

~

UJ
to
<

UJ
to

sa

",UJ
UJt-

c.>

g

0
>
u

~
0
>

UJt'"
-

~

O;:!

~~

~!;;:

~fu

~
UJ

~
~
0
UJ

!;<

~

~
~

'"
UJ

UJ

~

~

!;<

!;;:

UJ
to
<

c.>
0

...J

~
UJ

Fig.4 • r ypical Jisslpation characteristic.

a

.:;!
2

l\,

6.ZIIO

~ ~~
tt"'
c:
ft;

U

x

~
~
...J
;:!

~

"'t-UJ
!;<
UJ

;!:
.,;

'"

to
:>
0

"''"tu
0
>

~

~ '"
hi
0
t-

0
>

,w

O.lpF.:;J;

Fig.S • Test setup lor measuremen' 01 Inpu'.impedance
components.

UJ

c.>
0

~

2
2
0

U

!;;:

~

::Ec.>

ffi~

UJ

t-

to

z:

13
14

~
~

+10 V -310+3

OV
50 rnA

-310+3
PROCEDURE Voltage Gal":
1. Set input frequency Ht desired value. Vi '" 100 IJ-V rms.
2. Record vo'
3. Calculate Voltage GRin A from A = 2010110 vo/vi'
4. Repeat Steps 1.2. and 3 for each frequency and/or for
tempernture desired.

• Ally other comb.neUc." of DC Supply Voltage and Series Resistance which will not cause the Maximum
Device DiaaipIUon Limit or any of the Maximum Voltage or Current LImits fo, the CA3042 to be exceeded
may be used.

Fig.' .. res' setup lor measurement 01 IF amplilier

PROCEDURES~

1. Set FM Signal Generator as follows:
Output FreQUency 4.5 MHz
Modulatina: frequency '" ~OOO Hz
Deviation'" ±25 kHz
Output level for Vin" 100 mV rms
2. Set AM Sianal Generator aa follows:
Output frequency::; 4.5 MHz
Modulatinl frequency'" 1000 Hz
Per cent modulation 30
OutPUt level for V in '" 10 m V rma
3. With 81 in Position A measure AF Output
Voltage and record aa Vo(FloU.
4. With 8, in Position B meaaure AF Output
Volta,e and record 8S Vo(AN).
VoIFM)
5. Delennine AM Rejection from AMR
VolAMl

voltage gain.

=

=

BOONTON
TYPE 20ZH
AM-fM
GENERATOR
OR EQUIVALENT

=--

Z40114

I~
,*,0.0022

".F

• TRW Electronics, Dea Plainea, Illinois.
Part No. E023874, or equivalent.

Fig.7 • rest setup 101 measurement 01 AM re/ec,/on.

7ti

..." viTArI]
~ .0
~

~

~

..
. , . ", .
52

...."

~

I-..

&4

1
'\

200

i

S

400

AMBjNT IEiEtt~E (TA}OZ'·C

,i

,-

I

... .,
800 ~

~

I~

~ !=

dl

400

~

...

zoo

I,
i

100

FREQUENCy!tI-MHz

Flg.8· Typ;callF amp'Wer voltage gain anJ inpu,
limiting voltage (lenee' characteristics.

~4

________________________________________________________________

CA3042

ELECTRICAL CHARACTERISTICS,

at an Ambien£ Temperature, TA. of 25°C. and a DC Supply
Voltage. Vee. of t>i40 Volts applied to Tenninal14 through a resistance of 6.2 kil. unless othel"wise indicated. Any other combination of DC Supply Voltage and Series Resi8t(llU!e which will
not cause the Maximum Dissipation Limit or any of the Maximum Voltage or Current Limits {or
the CA3042 to be exceeded may be used.

LIMITS

TEST CONDITIONS
SETUP
CHARACTERISTICS
AND
SYMBOLS
(See Page 7 for Definitions ofTenns)
PROCEDURE
Fig.
Total Device Oissipation

PT

Zener Regulaling Voltage (OC Supply Voltage at Tenninal14)
Quiescent Operating Current

(into Terminal 11)
9-Volt Cunent Orain (Quiescent Operating Current into Terminal 14)
Input41mpedance Components:
Parallel Input Resistance

-

10.5 11.2 12.3

V

In

3

0.25 0.63

1

rnA

114

3

18

rnA

Parallel Output Capacitance

Ro
Co

-

Input Limiting Voltage (Knee)

Vi(lim)

II

Amplitude-Modulation Rejection

AMR

7

IF·Amplifier Voltage Gain
Recovered AF Voltage:

A(IF)
Vo(a!)

6

1. At FM-Detector Output

VCC •• 9 V applied directly
to Tenninal14

2. At AF·Driver Output

45

-

I·
4.5 MHz

I

II

in Test Setup

61'

3. At AF·Driver Output in

2A or 2B

TV-Receiver Sound System

.25 kHz

THO

1. In Test Setup
2. In TV Receiver Sound System
FM-Detector Output Resistance
AF-Driver Input Resistance

AF·Driver Output Resistance
AF·Driver Voltage Gain

II

2A or 2B
Ro(det)
RI(a!)
Rota!)

-

Aal

9

8

-

II

Total Harmonic Distortion:

200 230 260
210 240 270
220 250 2BO

V14

5
5

Parallel Input CapaCitance

Min. Typ. Max.

DoC
TA' • 25°C
+ 85°C

3

RI
CI

Output-Impedance Components:
Parallel Output Resistance

TYPE
CA3042

SPECIAL CONDITIONS

"TYPICAL
CHARAC·
TERIS·
TICS
I CURVES
Units
Fig.
mW
4
mW
mW

t

I

RL' 50 kO
THO· 0.7% (typ.)

11
5
100
4

Vo(a!)' 1.3 V(rms)

Rs' 500,Cl'0

-

kO
pF
kO
pF
~V

-

250

-

Vo(a!)' 500 mV (nns

-

150 200
(rms)
58
dB
dB
67

RL' 3220
500 800
THO < 5%
RL c 150 kO
3
THO· 1.5% (typ.)

I·
1 kHz

I

-

12

1.5
1
10
100
250
30

-

AMBIENT TEMPERATURE (TA1'Zj"C

I

'0

I

I

I

II

III
Rs '5O II
C."O

R!.'~'"

25

Cli50Pf
20

Rs·IOKQ
C.-50pF

'0

,

TI

i\.

"

8

.
10

I~

I

10

2

I

~

\
I

I

r,

Rs·IO Kll
CI'O

~

10

FREQUENCY(f!- kH~

5

%

-

-

voltage gain.

8

-

-

Fig.9. Test setup for measurement of AF amplifier

-

mV
(rms)
mV
(nns)
V
(rms)

-

240B

Vi'lomVRMS

A' 201091O*

%

kO
kO
0
dB

Fig. 10

'0'

- Typical AF amplifier voltage gain
characteristics.

10

PROCEDURES:
Rer;overed AF Voltage:

1. Set Input Signal Generator as follows:
Output frequency" 4.5 MHz
Modulating frequency = 1 kHz
Deviation::: f 25 kHz
Output level for Vin = 100 mV rms
2. Set volume control for maximum uf output

OOONTOO
TYPE 207M
IJolIVERTER

3. Measure af output voltage and record as Recovered
AF Voltage.

Oft EQUIVALENT
SOONTON
TYPE 202H
AM-FM
GE:NERATOR
OR EQUIVALENT

Totol Hormonir; D•• tortionl

1. Adjust volume control for an af output voltage of
500 mV nns.
2. Measure Total Hamonic Distortion of the output
signal in accordance with the Operating Instructions
for the Distortion Analyzer.
Input Limiting Voltage (Knee):

1.

Pe~c:~~:~ t~!nv~l~~ls!~eina~t:~tf~tf ~h~t~~c~dU! ~o~
measurement of Total Harmonic Distortion (SOOmV.

3 dB ::: 350 mY)

2. Measure resulting value of Vin and record a8 Input
Limiting Voltage {Kneel.

Fig. J1

4

Test setup For measurement of input limiting voltage (knee),
recovered AF voltage, and total harmonic distortion.

__________________________________________________________________ 325

CA3043

Special-Function Subsystem
For FM IF Amplifier Applicatiens
in CommunicatilllS Receivers IIId
High·Fidelity FM Receivers up to 20 MHz

HIGH·GAIN IF AMPLIFIER,
LIMITER, FM DETECTOR, AND
AF PREAMPLIFIER/DRIVER
FEATURES

a internal Zener_diode regulated voltoge supply

• high ..nll.lvl., - - Input limiting voltage (kn . .)
50 IJ. Y typo at 10.7 MHz

a low harmonic radiation

• exceUent AM rejection __ 58

• Inh.rent hlVh

Ita~lIily

cia typo at

e wid. frequancy capaillility __ <100 kHz to >20 MHz

10.7 MH&

• low harmonic distortion

__ int.rnally ,hieleled

• harmetic 12·lead TO·5 stvle package

RCA Integrated Circuit Type CA3043 provides in a single monolithic silicon chip. a major sub-system for the
IF sections of Communications and high-fidelity FM
receivers. As shown in the Schematic Diagram (Fig.2)
and the FM Receiver Block Diagram (Fig.1), the CA3043
contains a multistage if-amplifier/limiter section, an
FM-detector stage, a Zener-diode regulated power-supply

'n

ELECTRICAL CHARACTERISTICS at TA = 25°C

section. and an af-amplifier section. In FM receivers,
the CA3043 can be used to provide if amplification and
limiting, FM detection, and a£ preamplification. The
CA3043 provides exceptional versatility of circuit design
because the if-amplifier/limiter section, FM detector
section, and af-preamplifier/driver section can be used
independently of each other.
The four stage emitter-follower-coupled if amplifier
section provides 8().dB voltage gain at 10.7 MHz, and
features an output stage with exceptionally good limiting
characteristics because of its transistor constantcurrent sink.
The FM detector section is distinguished by circuitry
which provides forward bias to the detector diodes, 02
and 03. and also provides a reference voltage for AFC.

The audio amplJfier provides a low-impedance drive for
subsequent audio amplifiers.
The power supply section provides zener-regulated.
decoupled voltages for the IF amplifier, detector, and
audio amplifier sections.

ABSOLUTE·MAXIMUM RATINGS at TA = 25"C

DISSIPATION:

CIIARACTERISTICS

TEST CIR·
CUlT AND
PROCEDURE

SPECIAL TEST
CONDITIONS

SYMBOLS

Fig.

LIMITS
TYPE CA3043
Min.

Typ.

Max.

Current Drain at 6V
into Pin No.ll

III

Regulator Voltage Pin No.11

VIl

Total Device Dissipation

PT

Quiescent Operating Current
into Pin No.6

16

DYNAMIC CHARACTERISTICS al VCC
Voltage Gain

VCC

= +6V

VCC = +lOV,
RS = 750 D

3

10

16

20

3

6.9

7.4

8

V

3

200

225

260

mW

3

Operating. • . . • . . • . • . .. • . -Moe to + 125°C

Staage ...... • .. .. .. .. . ~50C to + 15O"c

mA

rnA

0.65

= +30V, RS =750 n, I = 10.7 MHz·

Input Limiting Voltage (knee)

vi(lim)

Limitmg Current frofl.1 Pin No.6

160im)

80

dB

6

50

,,~

4

0.42

mA
(RMS)

4

A.
'voe af) at -3 dB poi nt

Recovered AF Voltage

vo(af)

Vi = 1 mV (RMS)
f (modulating) '" 1 kHz
Deviation = ~ 75 kHz

Amplitude-Moduiation Rejection

AMR

Vi = 10 mV
f (modulating) = 1 kHz
% modulation = 50%

Total Harmonic Distortion

THO

.i

= 1 mV (RMS)

72

75

110

150

mV

6

8

58

6

0.3

'"
kll
pF

Input Impedance Comp~nents:

TEMPERATURE RANGE:

UNITS

STATIC CHARACTERISTICS

At TA = 25°C to TA = SSoC •••••••••• 450 mW
Above T A = SSOC ..••• Derate linearly 5 mW/oC
LEAD TEMPERATlJRE (During Soldering):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 min)
-from case for 10 seconds max • • • • • _ t 26SoC

o. ° ",,"-,oin

FI,J • Typlcvl.ppllc.'ion of ,,,_ CA.3043
IIm,ter, ...pllfl.r.detector
on FM Nce'.,.r.

Parallel Input Resistance

RI

7

Parallel Input Capacitance

CI

5

(RMS)

dB

TOO. A
+!lOV_--"""'......

Switch in Position A lor:

Not.s:
S " Substrate

Replalor-VoUege, QuiescentOpereUnc-Current. and Device
Dissipation Test
Switch in Poaition B for Cummt
into Pin No.ll

'"
F;g.2. Sc,",mvt;c J;vgram.

Terminal No.3 wire-connected to the CBSe.
Tenninal No.IO cOftllf\&'ted to the case throuBh the substrate

Terminals No.3 and 10 which are connected to the substrate
should be connected to the most nelaUve point in the circuit.
Diodes D4 and DS, act as capacitor'll and are used to balance
the detector l11.\bstrate capacitances.

F/g.3 • Regulator vollage, device J/sslpat/on, quie.sunt
operating current, ami curr.nt a' 6 yolts into Pin No. ll.

326 __________________________________________________________________

CA3043
MAXIMUM VOLTAGE RATlHGS
The following chart gives the range of voltages which can be applied to the terminals
listed horizontally with respect to the terminals listed vertically. For example, the
voltage range between horizontal terminalS and vertical terminal 3 is 1-6 to 0 volts.
TERM·

10

INAL

MAXIMUM
CURREHT RATIHGS
TERM-

12

11

No.

.,

0

·4

·5

0
·5

o

lOUT

'iN
mA

INAL

No.

mA

Nole(l)

0

·3

·3
'6

o

+6

o

+15

.,

'6

o

'6

Note(21

'6

o

o

.,.,

'3

0.1

0

..
..

Voltage Gain" 20 10glO 100 ~
'i

0

C b - Bypass Capacitor, Q.l p,F electrolytic in pllrallel with 0.01 JI-F

0

I6 (1im)

'6
0

.,

"i~'

vi" 100 mV(RMS)

'" Output circuit should be completely shielded from the input
circuit at the socket.

·15

Fig.4 - Voltoge go;n fest circuit.

..
0

Nole{l)

.

100 VCC'''3Ov

0

RL'7~on

90 TA' Z~·C

..
0

20
Note(2)

.3

10

0.1

'"

11

11

40

0.1

12

12

10

0

0

i

1"'0

Note 1: These terminals should be connected through a de

resistance to any terminal which does not exceed
100 ohms.
Note 2: Pin 11 may be connected to any positi'w voltage
source through

II

suitable resistor provided its cur-

rent rating is not exceeded.

I

'" Voltages are not normally applied between these terminals.
Voltllges appearing between these terminals will be safe if
the specified limits between all other terminals are not
exceeded.

.68

10

.6

e

100

FREOUENCY(I)-MHz

Fig.S - Voltage gain vs frequency,

zoo Vec'" 30 V
RL·1~on

TA • Z~'c

~ 160'~-+--+-~+--+--~~r-~~-+-H

't

~ 120'~-+--t-rtt--+--~~r-~~-+-r
0>:

Illi!YElill.!l

/

BOONTON

v

TYPE: 207(
OR EQUIVALENT 005
AM-fhl
Vi

:~~:~g::

OR EOUIVALENT

l-

51

~

,

. ..

'0

...

'REQUENCV (I)-MHl

'00

PROCEDURE:

1. Recovered Audio Voltage Vo(aO Set input frequency to 10,7 MHz,

Fig.7 -Input limiting voltog. (kneel at _3dS point
vs frequency.

Vi = 1 mV(RMS), modulati.ng frequency" I kHz
Deviation'" ±75 kHz
Re~~r:l:'o liS measured on the Distortion Analyzer meter

Thls is the recovered Audio Voltage Vo(aO
2. 3 dB Limiting Sensitivity Vi(lim) Reduce Vi until Vo(aO drops 3 dB.
Record this value of Vi as vi(1im)

TI~

"Di Li"

3. Total Harmonic Distortion THD -

Re:~n:ir~~t~~~~~:?r:cnt~o~~e~:t~~isS~:¥'HD~naIYZer

per

'" See Fig.9 for details on Discrlminator Transformer.

Coil Form, Outside Diameter'" 7/32 11
Can" 1/211 square X 1-1/8" long

PROCEDURE:
A. Connect FM Generator to CA3043 input.
Set frequencv to 10.7 MHz. Vi " to mV. modulating frequency" 1 kHz
Deviation" ±75 kHz.
Tune Wave Analyzer to peak reading at 1 kHz and record
recovered Audio Voltage Vo(aOFM.
B. Disconnect FM Generator and Connect AM.. Generator to
CA3043 input.
Set frequency to 10.7 MHz, Vi " 10 mV, modulating frequen·
cy " 1 kHz, percent modulation" 50%.
Tune Wave Analyzer to peak reading and record recovered

:~;~it:o~~a::d:~~:~~MRejection Ratio" 20 10glO vo(aOFM
vo(aOAM

Slugs - Radio Industries Type MP34/MPI00 Material

Fig.6 -Input limiHng voltage (knee), recovered AF
voltage, and total harmonic distortion test circuit.

Ll & L3 " 20 Tums 5·44 litz wire universal wound

Fig.8. Amplitude mocJulatJ"on rejection test circuit.

L2 " 10 Turns 5-44 lit~ wire wound bifilar with Ll
1..1 & L3 coupling adjusted to 520 kHz peak to peak separation
on S curve when operated in circuit shown in Fig.5.

Fig.9 - JO.7-MHz discriminator transformer for CA3043.

__________________________________________________________________ 327

CA3044, CA3044V1

Special-Function Subsystem
FEATURES

WIDE·BAND AMPURER/PHASE DETECTOR
WITH ZENER DIODE VOLTAGE REGULATOR

.. Primarily inteneled for AFe (automatic frequ ... c),
control} Applications
• Intemal Zener Diode Volta,e Regulator
• Differentiallnpu. Ampilfier/Lillli ••,

For AFC IAutamatic
Frequenc, Control) Ap_ications

• Full.Wove Diode Brhl,. Detector
• Dlf~tial O"put Voltagll Amplifier
• Avail.ble in Two Eleetrically Identical Venians
of the 10-lead TO·5 style package,

The RCA CA3044 and CA3044VI represent a second
generation of integrated circuits designed primarily for
AFC (Automatic-Frequency-Control) applications.

CAJ0404 With Straight Leads;

CA3044Vf With Formed Leads
• Wiel. Operating T IImp.ratu,. Range; .55 to +125 0 C

F/,.', Bloele Ji09rDm 01 Typicol Av'omofic Fine T""ln,
(AFT] A"licof;on ",'n9 CA30.f.f or CAlO.f4VI In
Color-TV Recei".,.

The CA3044VI is electrically identical to the CA3044 but
is supplied with fOfllled leads for easier PC board design
and construction.

ABSOLUTE·MAXIMUM RATINGS
DISSIPATION:
At T A • 25°C.. ••••••••••••••• •••• ••• •••••••• 830 mW
Above TA • 25°C •••••••••••••• '.' ••• Derate linearly 5.6 mW/oC
TEMPERATURE RANGE:
Operating ••. • • • • • • • • • • • • • • • • • • • • • • • • •• _55°C to +l25°C
Storage ••••••••.••••••••••••...•.•.• ; -6S°C to t J sooe

LEAD TEMPERATURE (During Soldering):
At distance 1/16± 1/32 inch (1.59 ± O.79mm)
from case for 10 seconds max. • • • • • • • • • • • • • + 26SC

~

.

OlOOrtOlatlODILACTASCAI"ACITClR5ANO.'IU5I!OTO
'''''ANCET"I Dt:TlCTGIIWIISTflAYI CAI"AClTolNaS

MAXIMUM VOLTAGE RATINGS •• TA • 2S·C
F/9.2. Sclre.otlc eli",,.,,,, CAJO.f4. CA30....V'

The following chart gives the range of voltages which can be applied to the tenninals
listed vertically with respect to the terminals listed horizontally. For example, the
voltage range between vertical tenninal 2 and horizontal terminal 6 is +20 to 0 volts.
TERM·
INAL

No.

TERM·

9

10

I

9
10
I

2

3

MAXIMUM
CURRENT RATINGS

2

3

4

5

liN
mA

lOUT

10

50

50

+6
0

I

5

5

+20
0

+20
0

2

20

20

+'6
-6

+6
0

3

5

5

+12
0

6

1

8

+20
0

+20
0

•

+6
-6

NO INTERNAL CONNECTION

+20
0

+20
·10

.

+20
0

+20
0

+20
0

· ·
. · ·

<12
·12

IHAL

No,

rnA

9

·
·
· · ·
· .. ·
·

4

5

5

+12
0

5

5

5

+5
0

6

5

5

1

+8
-5

1

5

5

8

STRATE

8

50

50

4
5

+5
-5

6

Fig.l. Test setup: Meosurement 01 to'al JeY/ce Jiss;·
pation, Zener r.gu/at/ng yo/tag., quiescent operating
curren' (termino/2).

I.!5Ul

, - -....-'IIItv-- +30 v

_,F

REF.

SUB-

.. Terminal No. 10 may be connected to any positive voltage
source through a suitable dropping resistor-provided the
dissipation rating is not exceeded.

~8

... Voltages EIre not normally applied between these terminals.
Voltages appearing between these terminals will be ,"afe- if
the specified limits be-tween all other tt'rrninals me not
exceeded.

LI'TR.PARTNo.1l1U
OR EQUIVALENT

F;g.4 • Input limiting sens/,',,'ty 'es' circuit.

________________________________________________________________

CA3044, CA3044V1
ELECTRICAL CHARACTERISTICS at T A' 25°C, Unl ... Oth ..wl •• Sp.clfl.d

CHARACTERISTICS

TEST
SYMBOLS CIRCUITS
t-----FIG.

TEST
CONDITIONS

LIMITS
CA3041 and CA304IVI
MIN·1

TYP.

MAX.

120

150

UNITS

I

CHARAC·
TERISTiC
CURVES
FIG.

STATIC CHARACTERISTICS
DeVice Dissipation

PT

3

VCC dO V
RS" 1.5 Kn
TA "·550 C

90

llO

140

170

mW

130

160

190

mW

Device DissipatIOn

PT

3

VCC" 30V
RS" 1.5 kO
TA " 25°C

Device Dissipation

PT

3

VCC" 30V
RS" 1.5Kn
T "t1250C
V "9V

9-Volt Current Drain
Zener Regulating Voltage-

DC Supply Voltage al Terminal 10
Quiescent Operating Current into
Terminal 2

IT

3

VIO

3

I,

3

QUiescent Operating Voltage at
Terminal 4
Quiescent Operating Voltage at
TerminalS
Output Offset Voltage between
Terminals 4 and 5

V4.5

4

5.5

rnA

ll.2

ll.9

V

I

2

4

rnA

V4

5.0

6.5

8.0

V

V5

I

5.0

6.5

8.0

V

·1.5

0

1.5

V

Vi
limiting

Input Admittance

111

Reverse Transfer Admiltarlce

Yi2

I

f .. 45.75 MHz

121
Ouiplit Admittance
112
OUTPUT vs FREQUENCY DEVIATiON - AFC

V
corr.
(4)

Rs' 1.5 kO

5

75

mV

0.5'11.1
3.B.j3.4
·11.7.10.1
0.071'jO.9

mmho

f=45.75 MHz

vee" 30 v

Forward Transfer Admittance

Correction-Control Valtage at
Terminal 4

2.5
10.5

VCC "30V
RS" 1.5 kO

DYNAMIC CHARACTERISTICS (AS RF AMPLIFIER)
Input limiting Voltage (Knee)

1

V
corr.
(5)

5

Figure 6 and 7 show the control voltages generated at terminals 4 and 5 of the Integrated Circuit as a
function of the frequency deviation from the nominal
center frequency. Figure 6 shows the region within
25 KHz of the center frequency while Figure 7 covers
the entire bandwidth of the system. The horizontal
reference lines on the figures are generated by a voltage divider connected between the power supply voltage on Terminal 10 and ground. The dynamic control
voltages are compared with these references according
to the Output 'IS Frequency Deviation Table. For example: when the frequency deviation is -25 KHz the
control voltage at Terminal 4 is greater than the reference A voltage; the control voltage at TerminalS is
less than the reference B voltage.
The shape of the correction voltage characteristics is dependent to a large degree upon transformer
characteristics and the parts layout.
In order to
closely duplicate the curves shown, the printed circuit
board shown in Figure 8 and the parts layout shown
in Figure 9 should be followed as closely as possible.

mmno
I.SilO
r----+30V

mmho

VCC . . 30 V
Vi, " 200 mV RMS

%of

%of

VIO

VIO

45.750·0.025
45.750.0.025

B5

45.750·0.900

75

33

45.750·1.500
45.750.1.500
45.750·0.025
45.750.0.025
45.750·0.900
45.750.0.900
45.750·1.500
45.750.1.500

The CA3044 and CA3044VI are specifically intended for use in the AFT system of color television
receivers. Each device is tested so that the control
voltages generated by the circuit meet the critical requirements of the system. Figure 5 is the schematic
diagram of the test circuit.

,.mho

'0" MHz as
Indicated

43
85

45.7501"0.900

COHection-Control Voltage at
TerminalS

mW

DYNAMIC CONTROL VOL TAGE
CHARACTERISTICS

33
33
85
43
75
33
85

V
V
V

6,7

V

V
V
V
V
V
V
V
V

7

6,7
LI

I~ ALlGIIED FOR ~YII ... ETRICAL BAIIDWIDTH 011
EITHER SlOE OF 45 710 ~H,

L 2 B~\:i~~lIi~R~PIIRAC\e~~~JF :~~~::I~~ f5~T:~,T

LI

TRW PART ~o 23754
OR EQUIVALEI'IT

L 2 oJ~~~i~~l~pm

7
Fig.5- Correction voltage test circuit for
CA3044 and CA3044VI.

DEFINITIONS OF TERMS

Input limiting Voltage (Knee) [vl(lim)]
The input signal voltage which will cause the output signsl to
decrease 3 dB from its maximum level.

Total Device DiSlipotlon (P T )
The total power drain of the device with no signal applied and
no external load current.
Quiescent Operating Voltage
The de voltage at the output terminal, with respect to ground,
with no signal applied.

Quiescent Operating Currenl
The average (de) value of the current in either output, terminal,
with no signal applied.

,
INPUT

FREQUENCY

OEVIAT10N-~H~

INPUT FREQUENCY DE'IIATION-MHI

Fiv.6 - Typical narrow-hand dynamiC control yo/tave
characteristics.

Output Offset Voltage
The de voltage between output terminals with no signal applied.

Fig.7 - Typical wide-hanel clynamie control voltage
characteristics.

Control Voltage
The dc voltage at either output terminal with respect to ground
with an RF signal of specified frequency applied.

_____________________________________________________________________ 329

CA3044, CA3044 V1

aJ Top view

b) Bottom vi ew

Fig.8 - Printed Circuit Board for Test Circuit-Full Size

Fig.9 - Top view of wired test board.

~O

________________________________________________________________

CA3052

Four Independent AC Amplifiers

APPLICA TlONS

Special-Function Sub-System for Stereo Preamplifiers,
Magnetic Pickups, Tape Heads, etc.

• Full-function stereo preamplifiers
• Tape recorder and playback preamplifiers
• Tone Generators

FEATURES

ABSOLUTE-MAXIMUM RATING at TA = 250 C:

• Four AC amplifiers on a common substrate
• Independently accessible inputs and outputs
• Operates from single-ended supply

AC INPUT VOLTAGE • • . • . . • . . • . . • . • . . • . . . . . . • . . . . . . . . . . . . . . . . • •

High voltage gain .
High input resistance
Undistorted output voltage
Output Impedance .
Open-loop bandwidth

. . . . ... . . . . . . . . . ... .. .. .. .. .. .. . .. •. . ..

+16V

0.5 V rm.

DISSIPATION:

EACH AMPLIFIER
•
•
•
•
•

POWER SUPPLY VOLTAGE

53dB min.
90 k11typ.
2V rms min.
1 k 11 typo
300 kHz typo

The RCA·CA3052 is a silicon monolithic
integrated circuit designed specifically for
stereo preamplifier service. The circuit consists of four independent ac amplifiers which
can operate from a single·ended supply.
The CA3052 can operate as an equalizer
amplifier in tape recorders, magnetic cartridge phonograph applications, and tone
control amplifiers. It can provide all of the
amplification necessarY for a. full-function
stereo preamplifier.
The CA3052 is supplied in a l6-lead dualin-line plastic package.

Up to T A = 55·C

.•....••..•.••..•...••..........•.....•..•..

Above T A = 55·C

. • • . • . . . . • . . • . . . • . . . . . . . • . . . . . . . . Deratelineerlv at 7.7 mW/·C

TEMPERATURE RANGE:
Operating

• • • • . • . . . . • • . • • • . . . . . • • . . • . • • . • . • • . • . . • • . . • . -40·C to +85·C

Storage

. . . . .. -65·C to +150·C

LEAD TEMPERATURE lOuring Solderingl:
At distance 1/16 ±1/32 inch 11.59 to.79 mm)
from case for 10 seconds max.

• . . • • . • . . . . • . • +265·C

MAXIMUM VOLTAGE RATINGS

The following chart gives the range of voltages which can be applied to the terminals
listed vertically with respect to the terminals listed horizontally. For example, the
voltage fange between vertical tenninal 2 and horizontal tennina14 is +2to-3.6 volts.
TERMiNAL
No.

1
2

RCA·CA3052 is schematically identical with
the CA3048 Amplifier Array (File No. 377).
Each amplifier of the CA3048 is ti!tltly
specified for equivalent output noise under
a variety of test methods. The CA3052 is
specified using RIAA test methods for equivalent input noise using one test method for
amplifiers 1 and 4, and an appropriately
different method for amplifiers 2 and 3.

750 mW

3
4
5
6

7
8

9

1

2
"+16
0

3

4

5

6

7

. . . · ·
.
·
. · ··
· ·
·
·
+2
-3.6

0

+5
-5

+3.6
-2

0
-16

9

8

10

11

12

13

14

15

16

· · · · · · · ·
· ·
·
· · · · · · · · ·
0

-i6

+2
-3.6

+2

+16

0

-3.6

· · · ·
·
· · · ·
· · ·
· · ·
·

+2
-3.6

+2
-3.6

+5
-5

10

11
12
13

·
·
·
·
·
· ·
·

0
-16

+5
-5

+16
0

+2
-3.6

+16

0

0

-16

· · · ·
· ·
· · ·
· · · ·
· · · ·
· ·· ·
· · · ·
· · · ·
· · ·
· ·

+2
-3.6

+16
0

0
-16

0

-16

+5
-5

14

· ·

15

+16

0

16
Fig. , - Block diagram of .tefflO pfflamp/ifier
IJ$/ng CA3052.

• Voltallea are not nonnally applied between tbese terminals.
Voltaces appearinK between these lenninats will be sare if the
specified limits between .11 other terminal. are not exceeded.

__________________________________________________________________ 331

CA3052
ELECTRICAL CHARACTERISTICS at T A = 25°C

CHARACTERISTICS

SYMBOLS

LIMITS
CA3052

TEST CONDITIONS

UNITS

MIN.

TYP.

MAX.

STATIC
Current dr ain per amplifier pair

112 or liS

VCC=+12V

9.5

13.5

17.5

rnA

DC Voltage
at Output Terminals

VI' V6'
V U ' VI6

VCC =+12V

6.1

6.9

8.1

V

DC Voltage
at Feedback Terminals

V3 , V7 ,
VIO' VI4

VCC=+12V

1.7

2.0

2.3

V

DC Voltage
at Input Terminals

V4, V8'
V9, VI3

VCC = +12V

2.2

2.5

2.8

V

DYNAMIC each amplifier with no AC feedback unless otherwise noted-terminals 3, 7, 10, & 14 bypassed to ground
AoL

VCC = +12V
EIN = 2mV
f = 10kHz

53

58

-

dB

VO(rms)

VCC=+12V
f = I kHz
THO = 5%

2.0

2.4

-

V

BW

VCC = +12V
EIN = 2mV

-

300

-

kHz

THO

VCC = +12V, f = 1kHz
EOUT = 2V rms

-

0.65

-

%

Input Resistance

RI

VCC = +12V, f= 1kHz

-

90

-

kfl

Input Capacitance

CI

VCC = +12V, f= IMHz

-

9

-

pF

Output Resistance

RO

VCC=+12V,f=lkHz

-

I

-

kfl

Feedback Capacitance
(Output to noninverting Input)

CFB

VCC=+12V
f = IMHz

-

<0.1

-

pF

Equivalent Input
Noise Voltage
(Amplifiers 1&4),
"c" Fi Iter at Outpul*

ENI*

VCC=+IOV
RS = 5kfl
A =45dB

-

1.7

6.4

/-LV

Equivalent Input
Noise Voltage
(Amplifiers 2 & 3)
RIAA Compensated*

EN2*

VCC = +IOV
RS = 5k fl
A =64dB (1kHz)

-

4

15.0

/-LV

VCC = +12V
f = 1kHz
OdB = 0.78 V

-

<-45

-

dB

VCC = +12V
f = IMHz

-

< 0.02

-

pF

Open-Loop Gain

Open-Loop
Output Voltage Swing
Open-Loop - 3 dB Bandwidth
Open-Loop
Total Harmonic Distortion

Inter-Amplifier Audio
Separation "Cross Talk ll '
Inter-Amplifier Capacitance
(Any amplifier output to
any other amplifier input)

C

·Per IHF Standard Methods of Measurement for Audio Amplifiers IHF-A-20I, 1966

*ac feedback included in test circuit

~2

_____________________________________________________________

CA3052

.Vcc
:ONNECT TO APP~OP~IATE TER~IHAl TO REAO VOL TACf

Fig. 3 - Test circuit for measurement of collector
supply voltage and currents.

"
'"

'SIC;

NOTE ALL RESISTOR VALUES ARE IN OHMS

Fig. 2 -

Schematic diagram for CA3052.

.Vcc
'" 'Sig Gen should be a low distortion type (O.2% THO or less)
HP206A or equivalent •
• Adjustment 01 Eg to 2 volts will make Es ;: 2mv'.
OCSUPPLYVOLTSIVCC)

Fig. 4 - Typical DC supply current vs supply
voltage.

AMSIEtiTTEMPERATIJr:tEITAI-'C

Test Circuit shows Amplifier III undel test, to lest Amplifiers 2, 3,
01 4; Connect terminals as shown in Table.

Fig. 5 - Typical DC supply current vs ambient
temperature.

AMPLIFIER

1
2

TERMINALS
INPUT

1

4
8

7

9

10

13

14

6
11
16

3
4

BYPASS

OUTPUT

3

Fig. 6 - Test circuit for measurement of
distortion; open-loop gain, and
bandwidth characteristics.

,

COLLECTOR ~UPPLY VOL Tl1VCCI' • 11
A_BIE~T TE_PERATURE (TAl' 2jOC

,
,

,
,
DCSuPPLYVOLTSIVCC I

Fig. 7 - Typical amplifier gain vs DC supply
voltage.

Fig. 8 - Typical open-loop gain vs ambient
temperature.

,

... i
-

rr

till

-

l I
1

I!

i

I

:l\~ K tt'i
I
I
llll
-I II :II rill LI .' I
,
,
)1,

I

I

I

10000

Fig. 9 - Typical open-loop gain vs frequency.

__________________________________________________________________ 333

CA3052
~

VTVI,HPiI\IDO

COllECTOR SUPPLY VOLTS '+12
RillS OUTPUT VOLTS 1[0"2
;, OPERATING FREQUENcr U).lkH

~
~!

- -_. .,."

COUECTORS"","OCTScvccI •• 12
OPERATINGFREQUENCYlf)"lkHa

l5OGP'l
II

,

•

S

I! '

...,

14

GEN
'''"''
f=lkH%

AMBIENT TEMPERATURE

.

(TAI~'C

1

Fig. 10 - Typical total harmonic distortion vs
ambient temperature.

_"'oo"oo"
~
S

-

l!D

-

6V

•

'¥cc
.Resistors are low noise precision, (1%) Metal Film type.
Resistor values are in ohms; capacitance values are
in microfarads, unlesa otherwiae specified.

Fig. "-Testcircuit for measurement of equivalent
input noise voltage of amplifiers 1 and 4.

OPERATING CONSIDERATIONS
Economical Gain Control
The CA3052 is deSigned to permit flexibility
in the methods by which amplifier gain can
be controlled. Fig. 15 shows a curve of the
gain of al) amplifier when the internal reo
sistive feedback of the device is used in con·
junction with an external resistor. Although
measured gain of various amplifiers will not
*Resilltors are low noise precision

H..f'TYPE
VTV."
(GOD
(OREQUI'l)

':"

i'

I'r-10
10.
100
IG,OOO
RESISTANCE IN FEEDBACK CIRCUITIRFBl- OHMS

100,DOO

Fig. 12- Typical amplifier gain vs feedback
resistance.

"

15V.

-

-} . 'pF
"
RF8

'"
75

I III

OGSpF

r~

':"

2~

!~VM

...,

UI,J.l111

(1%)

be uniform, because of tolerances of internal
resistances, this method is very economical
and easy to apply.
Stability
The CA3052, as in other devices having high
gain·band·width product, requires some at·
tention to circuit layout, design, and con·
struction to achieve stability.
ShOUld the CA3052 be left unterminated,
socket capacitance alone will provide suffi·
cient feedback to cause high frequency oscil·
lations; therefore, all test circuits in this data
bulletin include loading networks that pro·
vide stability under all conditions.

Metal Film type.

Fig. 13 - Test circuit for equivalent input noise
voltage measurement, RIAA
compensated.

+VccH4 VOLTS)

270

1- .F

+ 1000

Rv-5o.000 OHMS
TAPPED AT
12,000 OHMS

Performance Data
Gain at 100kHz. reference
Boost at 100 Hz
Boost ~t 10 kHz
Cut at 100 Hz
Cut at 10 kHz
·V.T.VN..· Hewlett-Packard Model 4000 or equivalent.
Procedure:
1. AdjustSianal Generator for DdS output at reference terminal.

2. Read voltage at other Qutput terminals (Figule shows terminal #1
used as reference).

Fig. 14 - Test circuit for measurement of interamplifier audio separation lIeross talk"

characteristic.

47

dB

11.5 dB
11.5 dB
10 dB

9

dB

Noise:
At maximum yolume (input shorted) > 70 dB below 1 yolt
At minimum yolume
> 80 dB below 1 yolt
Total harmonic distortion (at 100kHz reference
and an output of 1 yolt)
< 0.3 per cent
92CM-2930!:\

Fig. 15 - Schematic of one channel of a complete
stereo preamplifier.

334 ________________________________~----------__--------------------

CA3064, CA3064E
TV Automatic Fine Tuning Circuit
RCA·CA3064 and CA3064E represent the third generation of
integrated circuits designed primarily for AFC (AutomaticFrequency·Controll applications. Thev. provide all of the
signal'processing components needed (with the exception of

the tuned-phase-detector transformer) to derive the AFT cor·
rection signals from the output of the video-if amplifier. The

CA3064 is supplied in the 10·farmed·lead TO·5 style pack.
age, and the CA3064E in the 14·lead dual·in·line plastic
package.

Both types operate over the temperature range of

-55 to +t2S oC.

'ROM

1121

~IDE°--lH-QHH

The CA3064 and CA3064E are functionally similar to the
CA3044 and CA3044V1 but embody a higher-gain input
amplifier which provides a 2D·dB improvement in sensi·

'M'

~~N'J['lrS AND

__L._-_-_-_-_-_-_-_-_-_-_--'J ~~:~~~tt~~Mgt:~-\~!t.:iN:~~:~~C,\R[
PACKAGt
Fig.' - Block

di~r.m

01 typic.' oparu/", circuit utlllzin, tIM CA30tU IIfId CA3064E.

ELECTRICAL CHARACTERISTICS., TA = 2SoC. Un Ie .. Olherwl .. Specified

Features:
Cascade type high-gain amplifier (18 mV Inpu1 for ra1ed outpud
Intemal yoltaQl regulator
Differential detector
For UII with either color or monochrome
Differential amplifier
Bipolar OU1pUb
Wide operating-temperature range; -65 to +1260 C

CHARACTERISTICS

TEST
SYMBOLS CIRCUITS

~

LIMITS
CAlCB4. CA30B4E

TEST
CONDITIONS

UNITS

TYP.

MAX.

135

150

t25 DC 130

140

150

tS5 0C

145

150

MIN.

~
-25°C

DEVICE DISSIPATION:
UptoTA-25o C. .

Above TA- 25oe.

•

.

•

•

•

. • • ••
•

•

.

•

3

-66 to -t1250C
-65 to HSOOC

•

LEAD TEMPERATURE IDurlng Solderlngl:
At distance 1/16" ± 1/32"

11.59 mm to.79mml
from case for 10 I max.. • • . • •

266°C

'T

3

V'OII) = 10.5 V

4

6.5

9.5

V,OI,I

3

II.S

12.S

V

12131

3

I

10.9
1

2

4

rnA

5

6.9

B

V

I

5

6.9

B

V

V4-!i
·1
15·81
DYNAMIC CHARACTERISTICS lAS RF AMPLIFIER IN TO·5 STYLE PACKAGEI

0

1

V

Currenl Drain ., 10.5 Volls
Zener Regulated Voltage DC
Supply Voltage at terminal 10(1)*
Quiescent Operating Current into
Terminal 2(3)

Quiescent Operating Voltage at
TerminaIS(S)

V+=30V
RS·1.5kn

V4151
V51BI

Output Offset Voltage between
Terminals 4 and 5(5 and 8)

Input Voltage Sensitivity
Input Admittance

Fig.2 - TtJlmin.' auifJfImenr disgrams.

sensYtlvity

FOfward Transfer Admittance

Yll
Y12
Y21

Outpul Admittance

Y22

Reverse Transler AdmlUance
(b) CA3064E

r---

l.SkO

Quiescent Operating Voltage at
Terminal 4151

fa) CA3D64

rnW

RS'
700

AMBIENT TEMPERATURE RANGE:
Operating . • • • • • • •
•

Po

mW
derate linearly 6.6 mW/oC

•

5

V-t '" +30 V

rnA

Correction Voltage Output
as shown in table below.

V,=18mV

mmho

0.41 + jl.O
0+j3.4
24.5-j29
0.04 + jO.9

1=45.75MHz
V+=30V
RS = I.Hn

"",ho
mmho
mmho

OUTPUT" FREQUENCY DEVIATION - AFC
V+ =+30 V

V, = 18 mV RMS %,1
V,D
II)

fa" MHzas
indicated
Correction·Control Voltage at
Terminal 4(5)

Correction·Cantrol Voltage at
Terminal SIS)

Fig. 3 - Test setup: Measurement of total device
dissipation, zener regulating voltage,
quiescent operating current at
terminal 2 (3).

~
FIG.

I----c

30V
Device DiSSipation

MAXIMUM RATINGS. Absolum·Ma.lmum V.lu....

CHARAC'
TERISTIC

STATIC CHARACTERISTICS

V+ =

Storage.

UM'

I III nn
I .SEt FIG -6(bIFOR COIL DATA

tivity. The increased sensitivitY extends the application of
a proven AFT system to the low·level if·amplifier stages
in TV receivers.
Because the CA3064 and CA3064E Bre functionally similar to
the CA3044 and CA3044V1, refer to Application Note
ICAN·6B31. "ApPlication 01 the RCA CA3044 and CA3044VI
Integrated Circuits in Automatic Fine-Tuning Systems" for
general application information.

•
•
•
•
•
•
•

tDAAtCTIONVOLTAG[

/-'''-+tIJ
-S

6

1

1

>13

7

1

1

8

O.S

6

9

1

1

1

0.1

o

g
0

"

.,
o
.,

10
11
12

-S
INTERNAL CONNECTION

11

DO NOT USE

.4
-1

DO NOT USE
O.S

1J

1

2

"

14

1

0.1

'S
-S

1

1

0.1

'4
-S

2

1

0.1

J

0.1

SO

-S
'S
-S

INT, CONN.

12

1J
14

10

6

Note 1: Terminal No.5 may be connected to allY pOSitive
voltage through a suitable resistor provided that
the current and diSSipation ratings of the CA306S
are not exceeded.
·Voltages ale not normally applied between these terminals.
Voltages appearing between these termlllais will be safe it
specified limits betweel1 all other terminals are 110t ellceeded.

337

CA3065
The reSistance values included on the schematic diagram have been
suppl~ed as a convenience to assist Equipment Manufacturers in
optl.mrzing Ihe selection of "outboard" components of equipment
desls.ns. The values shown may vary as much as '30 00.
RCA reserves the right to make any changes in the Resistance
Values provided such changes do nol adversely affect the published
performance characteristics of the device.

'co

140'1

BOONTON
TYPE207'M
UNIV[RT(R
OAEOUIVAL(NT
BOONTON
TYPE20ZH
At.!-H4
GEN£RATOR
011 EQUIVALENT
ALL RESISTANce VALUES Alit IN OHMS

11CII-IIIIIII

LI·IS,..Io4NOMINAL
Q(UNLOAO[OI'6S TO 85

Fig. 2·S.hemotl. diagram 01 CA3065

ELECTRICAL CHARACTERISTICS at TA = 250 e, Vee = + 140 V applioJ t. Tormlnal 5 thr.u,n
RS = 3.9 k and DC V./umo eantrol (R.)
.. = 0 un/o...thorwl .. Indlcatod.

n.

CHARACTERISTIC

SYMBOL

SPECIAL TEST CONDITIONS

I

I

Min.

LIMITS
Typ.

Malt,

UNITS

Vee

Static Charact.rlstlc,

140 V

Z;.~~~~~,u~~I.I~g Voltage

V5

Current into TerminalS

I

Tolal Device Olssipahon
Terminal Voltages:

TERMINALS 11,12.13,14 NO CONNECTION

Fig, 3 • Input limiting vo/to'le, AM re/.cHon, reo
eover.a aua/o, total harmonic alstartlon, maxi.
mum att.nuat/on, maximum "p/oy.through"
test circuit.

I
6
7
9
II

Connect TerminalS to ,9V

PT
VI
V6
V7
V9
VII

10.3

11.1

11./

V

10

16
370

14
400

rnA

-

4

1
4.8
6.1
3.7
5.1

5.8

-

100

400

40

50

-

dB

-

500

-

mmho

-

46
'0.01

-

degrees

-

of

343

-

-

-

mW

V

-

-

Dynamic Charact.ristics

IF AMPLIFIER
Input lImitmg Voltage

10 . 4.5 MHz. 1m ·400 Hz.
V1(lImJ

DeViation - '25 kHz;

AMR

Amplitude Modulation

lat -3 dB point)
AM ReJection

Transcooductance
Magnitude
Phase Angle

Feedback Capacilance
Input Impedance Components:

Parallellnpul Resistance
Paraliellnput Capacitance
Output Impedance Components:
Parallel Output Resistance
Parallel Output Capacitance

IGmlllFI

I . 4.5 MHz

I· 4.5 MHz
IF Input Terminals: 2,1
IF Output Terminals: 9, 3

Clb

f . I MHz; Terminals 2 and 9

-

RiIlF)

Measured between
Terml[lal Nos. I afld 2

-

17

-

kn

C,IIF)

I" 4.5 MHz

-

4

-

pF

-

3.15

-

kn

7.5

0.5

0.75

-

V(rms)

-

0.9

1

%

-

7.5
• 300

-

kO

-

dB
mV

Measured between
Terminal NO.9 and gnd

CoOF)

1'4.5 MHz

Recovered AF Vollage

Vol'l)

Total Harmonic Distortion

THO

I 45 MHz: V)
:1 '25 kHz
1m 400 Hz

Output ReSistance:
Terminal 7
Terminal

Po

a

.ax.

100 mV

-

ay·In,ougn· 'ollage·

RX .., a:>
RX -0:/1

60

-

80
0.075

1

n

Alai)

VI ",0.1 Vrrms).

17.5

10

Total Harmonic Distortion

THO

Vo 1 Vi,ms). I "400 Hz
THO ~ 5°0, f - 400 Hi

2

1.5
1.5

-

I" 400 Hz
1.400 Hz

-

70
270

-

Output Resistance

Rital)
Rol'l)

f

400 Hz

."Playmrough" voltage is the unwanted signal, measured at TerminalS, when the volume control Is set for minimum output.
~8

3.9kfl

TOOIOOE
OETECTOR&
OSCILLOSCOPE

(a) Test circuit

--

•~ sn~--4----+--~~--~----+-~~
,

'<
~

~ ~ r---~---+--r-r+--~----+--r-r1

ffi

Voltage Gam

Input Resistance

F";g. 4 ·Audio vo/tog. gain (undjstorted output)
test circuit.

~ ~or---~---+--r-r+--~----+--r-r1

AUDIO AMPLIFIER

Undistorted Output Voltage

TERMINALS 7,8,11,13 NO CONNECTION
ALL RESISTANCE VALUES ARE IN OHt.!S

pF

See Fig. 7

~
Mall:, Attenuation

"V

··/IF,

Roll F)

DETECTOR

30',

dB
%
V(lms)

kn

n

~ wi----+_--~·~·-t+_--4_--~_+~
~ IO~--4----+--r-r+--~r---+-~~

FREQUENCY (n_Mth

(b) Responu curve
Fig. 5. Frequency response 01 IF.amplilier section 01 CA3065

____________________________________________________________________

CA3065
OPERATING CONSIDERATIONS

AMBIE:NTTE:IoIP[RATURE ITA).Z:'"C

--

.,
o
g~

~~ eo

The CA3065 may be used to drive a video output
transistor or a high-transconductance output tube•

§;60~~--r-r+r--+r/'-+~++--+--+~~
~~

~240'~~--r-r+t,f+--+-~+--+--+-~

~~ 20~~--r-f--j,f-/--+--+~++--+--+~~
I~

(a) Test circuit

"
20

468

10K
lOOK
RESISTANCE: IRKl FROM TERMINAL 6 TO GNO-OHMS

4615

IMEG

Fig. 7· Gain reduction vs. resistance
(terminal 6 to gntl)

I"-

"

As in all TV receivers, precaution should be
taken to prevent destruction of the CA3065 in the event
of cascade arcs originatirlg in the picture tube or in the
output tube. In the case of arcing in the output tube a
resistor of 150k in series with tenninal No. 12 and the
grid of the tube is usually sufficient protection.
To prevent damage from picture tube arcs, a careful
analysis of board layout and coupling modes (electrostatic or magnetic) may be necessary to suggest alter-nate layouts or appropriate locations for the placement
of spark gaps to absorb the high energy discharge.

'\

10

5

"01

FREQUENCY_MH.

(h) Response curve

Fig. 6 - Frequency response of of'ompliFier
section of CA3065

9255-44~S

(a) Printed circuit boortl - bottom view*

(b) Parts layout - top view*

Fig. 8· Recommended parts layout lor TV receiver
sound strip using CA3065.

* A 200 mil square grid was used in the layout of passive components on the
printed circuit board. The Quad-in-line formed leads conform to a standard
grid spacing of 100 mil centers.
.

__________________________________________________________________ 339

CA3066, CA3067
System Features

Television Chroma System
CA3066

The RCA CA3066 and CA3067 are monolithic silicon
integrated circuits that constitute a complete chroma system
for color television receivers. The CA3066 provides
subcarrier regeneration and total chroma signal processing
prior to demodulation; the CA3067 performs the
demodulation and tint control functions. Each device utilizes
a 16·lead quad·in·line plastic package.

• Complete Color Sync Circuit

CA3066 CHROMA SIGNAL PROCESSOR
The CA3066 contains substantially all the color processing
circuitry exclusive of the tint control and demodulating

circuits. The chroma amplifier sections of the CA3066
consist of the chroma and bandpass amplifiers. The chroma
amplifier receives the chroma input signal at terminal No. 1.

• Balanced Chroma Demodulators
• Color Difference Matrix

• Chroma Band-Pass Amplifier
• Low Output Impedance Chroma Driver

• DC Tint Control
• Three Low Output Impedance Drivers for Direct Coupling

• ACC Detector-Amplifier
• Killer Detector-Amplifier

• Reference Subcarrier Limiter
• Zener Diode for Regulated Voltage

• DC Chroma Gain Control
• Zener Diode for Regulated Voltage Reference
• Short-Circuit Protection on All Terminals

• Internal RF Filtering

ELECTRICAL CHARACTERISTICS at TA

::

CHARACTERISTICS

(ACe) detector-amplifier. The chroma signal is

internally coupled from the output of the chroma amplifier
to the input of the chroma bandpass amplifier and burst
separator amplifier. The horizontal keying pulse (+8V) is
used to gate the burst portion of the chroma signal from the
input of the bandpass amplifier to the input of the burst
separator amplif~r. The bandpass amplifier is gain controlled
by the dc chroma gain control and can also be controlled by
the killer detector-amplifier. The bandpass amplifier output
is internally coupled to the chroma output amplifier stage of
the CA3066. The coils of the chroma amplifier and the
bandpass amplifier are stagger-tuned to provide a combined
typical. bandpass of 3.08 to 4.08 MHz. The burst separator
amplifier injects the burst signal into the 3.58 MHz oscillator.
The oscillator amplitude is dependent on the terminal No.9
impedance to ground and is also responsive to the burst
signal amplitude at terminal No. 11. The ACC detector and
killer detector sense the burst level or absence of burst,
respectively, by monitoring the oscillators response to the
burst injection level. The thresholds for the ACC and killer
are independently adjusted by resistors R2 and Rl at
terminals No.9 and No.4, respectively. The chroma output
is at terminal No. 14 and the oscillator output is at terminal
No.8. Terminal No.6 is a zener diode for use as a regulated
voltage reference at 11.9 volts. When the zener reference
element is not used, the power supply voltage should be
maintained at 1.1.2 ± 0.5 volts.

• Blanked Chroma Amplifier

~eference

CA3066

This amplifier is gain controlled by the automatic chroma
control

CA3067
CHROMA OEMOOULATOR

CHROMA SIGNAL PROCESSOR

2SoC and V+:: 11.2 V
SYMBOL TEST CONDITIONS MIN

.1

L~M~MAX

J.

VPJ.

UNITS
.

TEST FIG.
AND
CURVES

Stltic Characteristics
Voltages:
Ace Reference
Burst-Chroma AmpL Bias Current Term.
Killer Reference
Zener Reg. Reference
Oscillator Input
Oscillator Output
Balance (ACC Control)
Chroma Output
Currents:
Total Supply
Burst Separator Output
Band·Pass Amp!. Output
Chroma Ampl. Output

0.5
2.9
1.0

10.6 11.9
1.4

12.6

v

Vs
V9

'.0

V,4

15
I,l

14

24

33

65
4.S

5, Closed

13

',6

mA

Dynamic Characteristics
Oscillator Output

v8

V1 ~ 0 vp .p
V1'" 1.25 vp.p

0.8

V1 '" 1.25 vQ.:Q.
V1 '" 0.025 vp.p
Vl '" 1.25 vp.p

0.5

1.2
2.5

3.5

Vp_p

4

Vp.p

3.4

v

4

Chroma Output:
100%

Killed
Ace Detector Output

v14

v2

1.0
12

0.9

50
2.4

250

CA3066
MAXIMUM RATlNGS,Absolute·Maximum Values at
TA ~25"C
Supply Voltages and Currents (see charts below)
Device Dissipation:
UptoTA=700 C _ . . . .
. .. 600
mW
Above T A=- 70 0 e
.. derate linearly 7.7 mW;oC
Ambient Temperature Range:
Operating
.. -40 to +85 uC
Storage
.. -65 to +150 °C
Lead Temperature (During soldering for
lOs max. at not less than 1/32" from package) . . . +265 °e
Voltage with respect to
Terminal No 5
Terminal
No.

Vmin.
(volts)

Current
Vrna.ll.

Ivoltsl

Terminal
No.

See Note Nt

mA
20

'0

mA
0.1
0.1
2

0.1
.0

11
12
13
14
15
1.

5.0
0.0
0.0
0.0

N2
18.0
12.0
15.0

10

0.0
0.0
5.0

N2
15.0
5.0

15
1.

11
12
13

14

0.1
10
50
10
0.1

0.1
0.1

Nl

Fig. 1 - CA3066 schematic diagram.

N2

0.1
2
20

Terminal No. 6 IS connected to a zener reference
element, that, if used, should be biased by a positive
voltage through a resistor that limits the current to a
value which is less than the maximum current rating of
terminal No.6.
The upper voltage limit cannot exceed the power
supply input voltage at terminal 12.

340 __________________________________________________________________

CA3066, CA3067

CI1ROMA
OUTPUT

'--'V'."v--+--.. +20V

"

o----j

CI1ROMA
INPUT

Fig. 2 - Static characteristics test circuit for CA3Cl66.

All RESI\TANCE VALUES ARE IN

OH~~

OSCILLATOR

UIILEBOTHEIIWI~E INDICATED.
ALL CAPACIUNCE VALUH
lnlTHAN 10ARE IIIMICROFARAD\
I OOR GREATER ARE 11-1 PICOFARAOS

OUTPUT

ALlCOILSHUEAClou~JO

Fig. 4 . Dynamic characteristics test circuit for CA3066.
DYNAMIC CHARACTERISTICS TEST PROCEDURE

Steps 1, 2. and 3 are performed with no Chroma input
IV1 = 0)

1.
2.
3.
4.

CHROMA INPUT-PERCENT

Fig. 3 - Typical ACe characteristic of chroma output vs
Chroma input for CA3066.

5.

Adjust ACC potentiometer for V2 = +O.65V.
Adjust Killer potentiometer for V4 = +1.2V.
Adjust capacitor Cx (crystal trimmer) so that
frequency of oscillator is 3.579545 MHz.
Unless otherwise noted, the chroma gain control is at
maximum gain (fully clockwise).
The chroma input test signal is a 52.5 !Js "line" at
subcarrier frequency. and 10 cycles of burst at 46.5%

6.

7.

of the "line" amplitude. The chroma input (v1) is in
peak·ta-peak volts of "line" amplitude.
The chroma output (v14) is the same as the chroma
input (vl) except that the burst is removed and keying
overshoot occurs in the retrace period. The chroma
output is in peak·to·peak volts of "line" amplitude.
The oscillator output (va) is the CW output at terminal
No.8 and is in peak·to·peak volts. Some modulation
of oscillation dampening between burst injection is
visible.

CA3067 CHROMA DEMODULATOR
The CA3067 contains the separate functional systems of a
de tint control and a demodulator. The phase shift of the tint

amplifier system is accomplished by functional control of the
fixed phase signal from the CA3066 oscillator output. This
regenerated reference subcarrier is applied to terminal No.3
and driven differentially into phase shift circuits. The tint
adjustment controls the vector addition of phase shifted
signals after which a limiting amplifier removes any remain-

ing amplitude modulation. The output of the tint amplifier
at terminal No. 1 is phase separated for the required
reference subcarrier phase at terminal No. 6 and No. 12
(terminal No. 12 lags terminal No.6 by approximately 760 ).
These terminals are inputs to the demodulator drive amp·
lifiers. The demodulators consist of two sets of balanced
detectors which receive their reference subcarrier from the
demodulator drive amplifiers. The chroma signal input from
the CA3066 is applied to terminal No. 14. The chroma signal
differentially drives the demodulators. The demodulation
components are matrixed and dc·shifted in voltage to give
A-V, G-Y, and B-V color difference components with
close dc balance and proper amplitude ratios. The output
amplifiers of the CA3067 are specially designed to meet the
low·impedance driving source requirements of the high-level
color output amplifiers. A special feature of the CA3067 is
A-C filtering of high frequency demodulation components.
Terminal NO.4 is a zener diode for use as a regulated voltage
reference at 11.9V. When the zener reference element is not
used, the power supply should be maintained at +11.2 ±O.5
volts.

*0,

,.tz~

NOTE 037 THROVC;H

O~I

ARE EMITTER FOLLOWERS

ALL RESIST.IINCE VALUES AREIN 0"1015
ALL CA~ACITANCE VALUES AREIHpF

'----~M;:._--..+20V
HCS-17~03

Fig. 5· Static characteristics test circuit for CA3067.

Fig. 6 - CA3067 schematic diagram.

341

CA3066,CA3067
CA3067
MAXIMUM RATINGS,Absolute-Maximum Values at

ELECTRICAL CHARACTERISTICS alTA' 25°C and V' = 11.2 V
LIMITS

I

CHARACTER ISTIC

SYMBOL TEST CONDITIONS MIN.

TYP. MAX.

UNITS

TEST
FIG. AND
CURVES

V

9

Static Characteristics
Voltages:
Tint Control Input

V2

Reference Subcarrier

V3

12 = 0.25 mA

-

3.5
11.9

-

5.7

V7. Vll

-

5.0

VB.9.10

4.2

5.0

5.B

-

0.3

V4
V6. V,2

Balance (S-V, R-V)

B-Y, G-Y, R-V Outputs

i>VB.LWg,
-0.3

i>VlO

Chroma Inputs

12-6

10.6

Zener Regulator Ref.

B-Y, A-V Oscillator Ref. Inputs

Difference Outputs"

-

2.1

V,4. V,5

3.0

V,6

4.7

Tint Ampl. Balance

-

'9.11.12"

r----

TA = 25"C
Supply Voltages and Currents (see charts below)
Device Dissipation:
Up to TA == 700 e
.. 600
mW
Above T A = 700 e
. derate linearly 7.7 mwfOe
Ambient Temperature Range:
.. -40 to +85 °C
Operating
Storage
. . . -65 to +150 °C
Lead Temperature (During soldering for
lOs max. at not less than 1/32" from package).. +265 °C
Voltlge with respect to
Terminal No 5
Current
Terminal
No.

6

7

9

a
9
10
11
12
13
14
15
16
1
2
3
4

Currents:
Tint Ampl. Output (min.)

11im;n.)

Total Supply

11

V,6

=

BV

+1,3

0.16
15

0.37

-

24

33

160

250

-

mA

Dynamic Characteristics
Tint Amplifier Output

V3 = 7 mV IRMS)

Sensitivity
Limiting Knee
Limiting

V3 35mV IRMS)
V3 - 350mV IRMS)

~6

V3 - 70mV IRMS)

185

220

235

deg.

l:>~6

V3 - 70mV IRMS)

90

105

-

deg.

Tint Ampl. Phase Ref."
Tint Ampl. Phase Shiftt
Demodulated Chroma Output:
R-Y

VlO

Ratio of G- Y to R-Y

V9/VlO

Ratio of 8-V to A-Y

Va/v 10

V3 = 70mV IRMS)
V,4 = 35m V IRMS)

300

mV

V,

IRMS)
3BO

Nl

-

150

250

0.2B

0.36

0.44

1.0

1.2

1.4

450

550

-

VIRMS)
10

Color Difference Output

BWOiff.

BW at 3.3 dB

kHz

Color Difference Outputs (max. input signals):

N2
N3

R-Y

'10

G-Y

'9

a-Y

'B

V3 = 70mV IRMS)
V,4 = 212mV IRMS)

-

-

vp _p

550
22

-

n

5

-

3.0
1.1
3.6

-

Vmin.
(yoltsl

V max.
(volts)

Terminal
No.

Ii
(rnA)

10
(mAl

0
0
0
0
0
0
0
0
3
0
N3
0
0
0

N2
N2
N2
N2
N2
N2
N2
12
N2
N2
N3
15
N2
5

6
7
B
9
10
11
12
13
14
15
16
1
2
3
4

3
3
20
20
20
3
3
60
1
6
N3
3
3
3
20

3
3
20
20
20
3
3
1
0.1
2
N3
3
0.1
3
0.1

Nl

Terminal No. 4 is connected to a zener reference
element, that, if used, should be biased by a positive
voltage through a resistor that limits the current to a
value which is less than the maximum current rating of
terminal No.4.
The upper voltage limit cannot exceed the power
supply input voltage at terminal 13.
Terminal No. 16 should be bypassed for normal
operation.

Small Signal Input Resistance
Terminal No.3
Terminal Nos. 6& 12

r;

-

'0

-

Small Signal Output Resistance
Terminal Nos. 8, 9, & 10
-lWe

• VB{B'V:'Vl,."V9'V9_~B +V~+Vl~"VIO'VIO{~

Terminal No.3 !s phase reference
read phase shift as tint control is varied

*

oil.

TOV·

O.C SUPPLY VOLTS !Vl31

Fig. 8· DC voltage at calor-difference outputs vs supply
voltage for CA3067.

Al~ R£\I\1A~C£

VALUE\

A~£

IW

O~.\

UNLf\\CTHERWI\E 'No,eAHO ALL C.PACIT.~a ~"LUEI
LEI\",.N '.AREIN.'CIIOFU"D\

I ORCP£ATERUEINP((OfAUDI

REG

Fig. 7 Dynamic characteristics test circuit lor CA3067.

REF

DYNAMIC CHARACTERISTICS TEST PROCEDURE

1.
2.
3.

The reference subcarrier input (v31 15 a 3.58 MHz CW
signal from a 50n source.
The chroma input (v141 is a 3.53 MHz CW signal from
a 50n source.
Phase and amplitude at terminal Nos. 1,3.6 and 12

4.

5.

are measured with a vector voltmeter (HP8405A or
equivalentl.
Signals at terminal Nos. 8,9, and 10 are measured with
an ac voltmeter (HP400E or equivalent! or an oscillo'
scope.
Unlm otherwise noted the Tint control is at max·
imum resistance.

AMBIENT TEMPERATURE-*C

Fig. 9· Temperature drift of DC voltage at calor-difference
outputs for CA3067.

342 ____________________________________________________________________

CA3068
Television Video IF System
RCA·CA3068 is a monolithic integrated circuit that in·
corporates an entire video TV·[ F subsystem on a single chip.
Innovations in integrated circuit design, in addition to the
many active devices and closely matched components uti·
lized in the circuit. make the CA3068 ideally suited for use
in color and black·and-white TV receivers.
The primary functions performed by the I F subsystem are
video IF amplification, linear detection, video output amplification, AGe from a keyed supply, AGe delay for tuner,
sound carrier detection. sound carrier amplification. and a
buffered AFT output. The advanced circuit design of the
CA3068 also Includes secondary functions for improved

FEATURES:

noise immunity and minimal airplane flutter. An isolated
zener reference diode, incorporated in the IC, provides a
conllenient and economical means for controlling the regu·
lated voltage supply. The inherent wide bandwidth capability
00·70 MHz) and high overall gain (87 dB) make the CA3068
suitable for other AM IF applications whose frequencies
range within this bandwidth.
The CA3068 utilizes a unique 20·lead quad·in·line plastic
package. This package also includes a wrap·around shield
that serves to minimize interleed capacitances.

•
•
•
•
•
•
•
•

High'gain wide·band IF amplifier: 75 dB typo at 45 MHz
Gain reduction with excellent stability: 50 dB typo at 45 MHz
Video detector with linear characteristics
Video amplifier: 12 dB gain
Impull8 noise limiter
Keyed AGC with noise immunity circuits
Delayed AGC for tuner
Buffered AFT output
• Sepante sound IF intef'C8rriar
amplification
• Sound carrier detector
• 4.5 MHz sound carrier amplifier

• Iwhlted zan ar reference diode for
regulated voltage supply

• See ICAN·6303, ",. Single IC for
the Complete PIX·IF System In

TV Receivers" for Schematic Diagram

MAXIMUM RATINGS,Absalute Maximum Values, at TA' 25"C
DC Supply Voltage:
Between Terminals 15 and 6*
Terminal 7 (Collector to ground) ..
Terminal 9 (Collector to ground)
DC Current (into Terminal 18) .••• , .......•..

11.3
20
20

0

0

••

0

•••••••••••

V
V
V

2

mA

600

mW

Device Dissipation:

Up'oTA"60'C

derate linearly 6.7 mW/oC

Above TA" SO°C
Ambient Temperature Range:
Operating ............... .
Storage ......
0

•••••••••••

Lead Temperature (During soldering):
At distance not less than 1/32" (0.79 mm) from case for 10 seconds max.

*

-40 to +85
- 65 to +150

'C

+265

'C

'C

Thll ruing doel not applV when uling tha internal zener reference in
conjunction with the pass transistor.

"~I'f-°O--+-VV~""'~'H
-

,OO~

RI ' 50 KO POTENTIOMETER
LI'2.2,.H:ADJUST No. OF TURNS FOR AL1G/iMENT
LZ·1.~ ,.H:ADJUST No· Of TURNS FOR ALIGNMENT
C ;; 1 pF' ADJUST FOR PROPER ALIGNMENT
ALL RESISTANCE VALUES ARE IN 01'11015
UNLESS OTHERWISE INDICATED, ALL CAPACITANCE VALUES;
LESS THAN 1.0 ARE IN MICROFARADS
1.0 OR GREATER ARE IN PICOFARADS

Fig. 1 Functional block diagram of the CA3068.

(a) Test setup for measurement of video sensitivity, sync. tip level, delay bias, AFT drive voltage.

'0

_,~.'.,r'0
b·
ko. .,--j

,

CAl06S

ALL RESISTANCE VALUES ARE IN OHMS

.....OJUST LEVEL ',' TO GI ....E
fide AnENuATION OF MillER

so THAT
THE STEP (os-b( AT .... IOEO
OUTPUT TERM, IS 3 VOLTS
APPLY ONLY 45.75 MHI TO
ADJUST STEP WAVEFORM,

2 - ADJuST LE ....EL 'b'

(b) Test setup for measurement of sound and chroma outputs.

Fig. 2 -

Test circuit for measurement of white level (V19) and terminal 2 voltage (V2).

Fig. 3 - Typical dynamic test circuit diagrams.

________________________________________________________________ M3

CA3068
ELECTRICAL CHARACTERISTICS at T A • 25'C
TEST CONOITIONS
CHARACTERISTIC

LIMITS
UNITS

SYMBOL
Min.

Typ.

Max.

15

-

45

mA
V
V

Static IDC) Characteristics
Quiescent Circuit Current

DC Voltages:
Terminal 2 !Sound)
Termi{lal 3 (Keying Input)

',5
V2

-

-

6

-

V3

-

6.4

-

10

-

'6

-

21

-

1

-

-

8.5

Terminal 7 (1) {AGel

V7

Terminal 7 (2) (AGe)

V7

Terminal 8 (AGe Delay)

Va

Terminal 9 (Cascode Collector)

V9

Terminal 16 tBiasl

V16

Terminal 18 (Zener)

V,8

Terminal 19.(White LeveH

V,9

V
V
V

4

VS"'V17 =OV,11s=lmA

-

V

1.'

-

2.3

V

10.6

11.9

13.2

V

6

-

,0

V

40

,00

200

pV

0.4

0.8

1.6

V

-

15

-

mV

-

CAJ068

Dynamic Characteristics
ALL RES1STA"CE VALUES ARE I" OHMS

Video Sensitivity

'I

Sync. Tip Level Voltage

V'9

Automatic Fine Tuning (AFT)

V,4

fa:: 45.75 MHz, Mod. (AM) '" 85%
at 400 Hz; Adjust e, for 4 Vp .p at
Term. 19
fa'" 45.75 MHz, ellCWI

= 10 mV

Fig. 4 - Test circuit for measurement of quiescent current
(1,5), keying terminal voltage (V3), bias voltage (V,6), AGC
terminal voltage 1 (V,), and cascade collector voltage (Vg)

Drive Level Voltage

Delay Bias Voltage:
At el" 10mV
At

ej ::

V7
fa = 45.75 MHz. ejICW):: 20 mY;

30 mV

3.58 MHz Chroma Output

Voltage

4.5·MHz Sound Output Voltage

Parallel Input Impedance:
Resistance at Term. 6

16

-

-

V

0.5

-

2

V

fa:: 45.75 MHz, ej(step mod.l "
10mV;
f1 = 42.17 MHz, el(step mod.! =
3.33mV

0.5

0.8

-

V

fa = 45.75 MHz, ej(step mod.) 10mV;
f2 = 41.25 MHz, el(step mod.) ""
2.5mV

50

200

-

mV

4

2

fa = 45.75 MHz

-

kn

-

4.5

-

kn

Adjust Rl for V7
V'9

V2

Capacitance at Term. 6

AI_6
CI_6

Resistance at Term. 12

AI-12

Capacitance at Term. 12

C'-12

Resistance at Term. 13

R,·13

Capacitance at Term .. 13

CI-13

Parallel Output Impedance:
Resistance at Term. 9

=

14 V

CA3068

pF

-

4

-

pF

5

-

kfZ

4

-

pF

RO-9

30

-

-

3

-

kn

CO-9

Cascade Transfer Characteristics:
Magnitude of Forward
Transadmittance

IVII

-

50

-

mmho

Reverse Transfer Capacitance

C,

0.00'

-

pF

Capacitance at Term. 9

~4

Impedance and Admittance
measured at biasconditions
as developed by circuit
shown in Fig. 7

V+·11.3V

-

pF

ALL RESISTANCE VALUES
ARE m OI'MS

Fig. 5 - Test circuit for measurement of AGC terminal
voltage 2 (V,) and terminal 8 voltage (VB).

_____________________________________________________________

CA3070, CA3071, CA3072 Types
Television Chroma System
The RCA CA3070, CA3Q71, and CA3072 are monolithic

silicon integrated circuits that constitute a complete chroma
system for color television receivers. The CA3070 is il
complete subcarrier regeneration system featuring a new
concept of phase control applied to the oscillator circuit. The
CA3071 is a chroma amplifier system and the CA30n

SYSTEM FEATURES

~

performs the demodulation function.

• Voltage Controlled Oscillator

The CA3070 utilizes the 16·lead plastic dual·in-line package;
the CA3071 and CAJ072 are supplied 14·lead plastic
dual·in-line packages.

• Keyed APC 8.. ACC Detectors
• DC Hue Control
• Shunt Regulator

CAJ071
• ACC Controlled Chroma Amplifier
• DC Chroma Gain Control

CA3070
Chroma Signal Processor

kiLLER
AD,JUSf

• Color Killer

C:"

• Amplifier Short·Circuit Protection

COfrIfROl

CA30n
• Synchronous Detector with Color Difference Matrix

The CA3070 is a complete $ubcarrier regeneration system
with automatic phase control applied to the oscillator. An
amplified chroma. signal from the CA3071 is applied to
terminals No. 13 and No. 14, which are the automatic phase
control (APe) and the automatic chroma control (ACe) in·
puts. APC and Ace detection is keyed by the horizontal
pulse which also inhibits the oscillator output amplifier
during the burst interval.

• Emitter-Follower Output Amplifiers with Short-Circuit
Protection

The ACC system uses a synchronous detector to develop a
correction voltage at the differential output terminal Nos. 15
& 16. This control siglal is applied to the input terminal Nos.

1 & 14 of the CA3071. The APC system also uses a synchronous detector. The APC error voltage is internally coupled to
the 3.58 MHz oscillator at balance; the phase of the siglal at
terminal No. 13 is in quadrature with the oscillator.
To accomplish phasing requirements, an RC phase shift
network is used between the chroma input and terminal Nos.
13 and 14. The feedback loop of the oscillator is from
terminal Nos. 7 and 8 back to No.6. The same oscillator
signal is available at terminal Nos. 7 and 8, but the dc output
of the APe detector controls the relative signal levels at
terminal Nos. 7 or 8. Because the output at terminal No.8
is shifted in phase compared to the output at terminal No, 7,
which is applied directly to the crystal circuit, control of the
relative amplitudes at termina,l Nos. 7 and 8 alters the phase
in the feedback loop, thereby changing the frequency of the
crystal oscillator. Balance adjustments of dc offsets are
provided to establish an initial no·signal offset control in the
ACC output, and a no-signal, on-frequency adjustment
through the APC detector-amplifier circuit which controls
the oscillator frequency. The oscillator outpu1 stage is
differentially controlled at terminal Nos. 2 and 3 by the hue
control input to terminal No. 1. The hue phase shift is
accomplished by the external R, L, and C components that
couple the oscillator output to the demodulator input
terminals_ The CA3070 includes a shunt regulator to establish
a 12-voltdc supply.

Fig. 1 - Simplified block diagram of TV chroma system.

L6

L'

Maximum Voltage and Current Ratings at T A = +25°C
Voltage.6.
Terminal
fila.

1
2

Current

Min.

Max.

Terminal

II

10

Volts

Volts

No.

mA

mA

1
2

20

1

-

-

0
0

+16
+16

3

0

3

-

4

-5

N2

4

20

1

6

-

-

10

N3

1

7

-

-

11

8

-

12

-

-

10

0

N3

13

20

1

11

0

N1

14

20

1

12

0

N1

13

0

N1

14

0

N1

15

0

+16

16

0

+16

• With respect to terminal
No.5 and with terminal
No. 10 connected through
470n. to +24 V.
Nl Regulated voltage at termi
nal No. 10.
N2 Controlled by max. Input
current
N3.Umited by dissipation.

lLLRESLSTANCE VALUES ARE LHOHNS

Fig. 2 - Schematic diagram CA3010.

______________________________________________________________

~5

CA3070, CA3071, CA3072 Types
MAXIMUM RATINGS,Absolute Maximum-Values at TA

=25"C

Device Dissipation:
UptoTA=+70°C ................
530
mW
AboveTA = +70°C ... Derate Lil')earlyat 6.7 mwtC.
Ambient Temperature Range:

Operating ............ ".......

-40 to +85

Cc

Storage ...................... -65 to +150
·C
Lead Temperature (During Soldering):
At distance 1/32 in .. (3.17 mm) from seating plane
for 10 s max. ............
+265·C

4700

vt·_'W_--~

ELECTRICAL CHARACTERISTICS, at T A'" 2SoC and V+ '" +24 V unless otherwise specified

CHARACTERISTICS

SYMBOLS

LIMITS
CA3070

SPECIAL TEST CONDITIONS

UNITS

MIN.

I Typ.1

6.9

7.7

8.6

-

2.8
6.5

-

11

12.3

13.5

MAX.

TEST
CIRCUITS
FIG.

StatiC Characteristics

Voltage:
Hue Control

Switch in position 2

VI

Oscillator Input

V6

APe Input

V13

Regulator

VIO

Regulator Change
Horizontal Key Input

= 21 V
V+ = 27 V
V+

VIO

14--10~A

V4

Currents:
Osci-llator Output
APe Output

111,112
115,116

V

3a

+0.2

--,

5

-

12

Ace Output

-0.2

3c

--

5.8

I

-

1.45

-

1.45

-

mA

I

3c

I
I
I

3b

I

Dynamic Characteristics
Oscillator Outputs:
Terminal No.2

V2

5, in position'

0.75

1.0

-

Terminal No.3

V3

51 in position 2

0.75

1.0

-

vp.p

ACC Detected Output

V16-V15

51 in position'

115

150

-

mV

4

±400

-

Hz

4

Oscillator Pull·ln Range

-

-

4

Fig. 3 - Static characteristics test circuits.
Dynamic Test Initial Adjustments
4.~,IOS

1. APC ADJUST: With S2 in "OFF" position adjust the
"APC ADJ" potentiometer to set oscillator frequency at
3.579545MHz ±25 Hz. With 51 in position 1 measure
frequency at terminal NO.2 output. using crystal' probe"
shown in Fig. 6.

+4V

PEAl( PULSE
DELAY ADJ. TO
CIENTER PULSE
ON THE BURST

}ACC 00rP",

2. ACe ADJUST: With 52 in "OFF" position adjust "ACC
ADJ" potentiometer to give an ACC output reading of
a ±2 mV.
Procedure to Pull·in Range Measurement

"ACC ADJ"
20X

1. Set Sl in position 1 and connect the crystal probe to
terminal No.2.

l50
"x
I.e M

PF

2. Turn $2 to "OFF" and set "A PC ADJ." arm to ground.
3. Turn S2 to "ON" and gradually adjust "APe ADJ" until
oscillator "locks" as witnessed by a sharp increase in ACC
output voltage between terminal Nos. 15 and 16.
4. Turn 52 to "OFF" and adjust capacitor Cp of crystal
probe for maximum deflection on Ballantine Meter.

"

5. Switch Ballantine meter to "Amplifier" position and read
oscillator frequency on counter.
6. Repeat steps 2 - 5 with "APC ADJ" arm set to terminal
No. 10 instead of to ground.

MOTES:
I.

All. RESISTANCES IN OHMS.

2. UNLESS OTHERWISE SPECIFIED ALL CAPACITANCES
ARIE IN MICROFARAOS.

3. \12 Ii v] MEAS'O WITH LOW-CAPACITY SCOPE
PRoeE s 20 pF.

Fig. 4 - CA3070 Dynamic test circuit.

Fig. 5" Crystal probe for frequency measurements.

M6 __________________________________________________________________

CA3070, CA3071, CA3072 Types
CA3071 Chroma Amplifier
The CA3071 is a combined two-stage chroma amplifier and
functional control circuit. The input signal is received from
the video amplifier and applied to terminal No.2 of the
input amplifier stage. The first amplifier stage is part of the
ACe system and is controlled by differential adjustment
from the ACe input terminal Nos. 1 and 14. The output of
the 1st amplifier is directed to terminal No. 6 from where
the signal may be applied to the ACe detection system of
the CA3070 or an equivalent circuit. The output at terminal
No.6 is also applied to terminal NO.7 which is the input to
the 2nd amplifier stage. Another output of the 1st amplifier
at terminal No. 13 is directed to the killer adjustment circuit.

MAXIMUM RATINGS, Amalu'" Maximum- Valuf/$ at TA = 2ftC

The de voltage level at terminal No. 13 rises as the ACe
differential voltage decreases with a reduction In the burst
amplitude. At a pre·set condition determined by the killer
adjustment resistor the killer circuit is activated: and causes
the 2nd chroma amplifier stage to be cut off. The 2nd
chroma amplifier stage is also gain controlled by the
adjustment of de voltage at terminal No. 10. The output of
the 2nd chroma amplifier stage is available at terminal No.9.
The typical output termination circuit that
is shown,
provides differential chroma drive signal to the demodulator
circuit. 80th amplifier outputs utilize emltter·followerlwith
short-circuit protection.

DC Supply Voltage II erminal 8
to Terminal 4)
30
VDC
Device Dissipation:
mW
Up to TA' +70·C ................ 530
Above TA = +70°C , ... Derate Linearly at 6.7 mWfC
Ambient T.emper~ure Range:
0c
Operating . . . . . . . . . •. .. . . . -40 to +85
Storage ..... '........ • . . . . -65 to +150
°c
Lead Temperature (During Soldering):
At distance 1132 in (3.17 mm)
Irom seating plano lor 10 s max. . . . . . •

+265

·C

Maximum Vol'llllland Currlflt Ratings. TA • +26°C
Vol'll,,Current

'"

3.71(
'"

3.'1(

T.mlnll

II

10

No,

mA

mA

'"

lotI(

0,

Rl1

~.\III

R12:

~2:

Z,

MAX
VOLTS

MIN

1

5

1.0

1

-6

+15

5

1.0

2

-6

+6

3
6

10
1.0

10

3
6

0
0

+24
+5

20

+2

7

5

7

-5

9

1.0

20

8

0

+30

12

1.0

5

9

0

+24

10

0

+24

11

0

+24

12

0

+20

13

0

+20

14

-6

+15

1.0

1.0
6
• With reference to
terminal No.4 and
with + 24 V on terminal
No.8 except for the'
rating given for terminal
No.8.

".51(

VOLTS

2

14

'"

TlI'mlnal
No.

O.

,

ALL AESISTANCE VALUES "R'IN o~ .. s

Fig. 6 -SchfllJlatic diagram for CA3071.

ELECTRICAL CHARACTERISTICS,

a.

T A • 250 C

SP£CIAL TlST CONDITIONS

Volllljlet
8'ilt Relerence Term,nill
AmpL No I Chroml
Inul

UnballnCed

Ampl No.2 Chromi

~i

V"
V,
V,
V,

'"

5, Open, 520Pl=n

'",.

5, Open. 52 Open
5, Open, 52 Open

v,

S, Open. S2 Open

V,

51 Clo$8d. 52 Open

'T

5, Open, Sl Open

Fig. 7 - Static characteri'tics

"S

51 Open, 52 Cloled

re't circuit-CA30n.

20'
17

24.S

J1

mA

OynimICChlflC:llnsllC:1
Ampllher No 1 Voltage Giilln

AVI

E,

JOmVRMS M••,1.Ir.v6

Ampllf,er No 2Voltagl
GI,n

AV'

V,

1 0 V I RM51 M.,11.Ir. v7

Mi~

ChromlOutpul
Vollagl
Chroma GIIn ContrOl
Reference VOltage

Oulpul VollIgI!!. Chroma all
BandWIdth
AmplifoerNo I
Amplifier No 2
Ampl No.1 Input
lfl'l9ldanc.
Ampt. NO.1 Oulpul
Impedance
AmpLNo 21npul
Impedance
Ampl.No 20ulput
ImptdarlCl

14

.,

1~

Output Vollaljle. KIn ... Oil

d.
d.

14

Va-Vl0

..

..

BW

,,'

VRMS

... ,.

Ell SO mVRMS, adlust Chloml
Ga,n Conlrol 10 Chlngll!
10% 01 M.. ,rnum Chroma
Output
51 ,n POI,tlon 2
I: g . SO mVRMS, adlust "KIller
Adiu""'olanlbl'upldec,H,e
inVg

2.1

3.B

,,'

.,'
'.'

11

-p'

'.B

B
mV

"

Eg < SO mVRMS. adJust Chroml
conllollo mm Chro~ Output

"

"
3.

,

.,'

'.'

B

RMS

.,.,

mV

"MS

MH,

NOTES,

"1

I.

pF

BS

II

"

kll

JS
BS

"

9,10
SWITCH S. IN POSITION I UNUSS OTN£"W.SE NOTEO
IN TAILE OF' DYNAMIC CHARACTER'STICS

2. CHIIOMA GAIN CONTIIOL sn TO GROUND UNLESS OTHEIIWISE
NOTED IN TAiLE OF DYNAMIC CHAIIACTEIIISTICS

B

3. ALL IIESISTANCES IN OHMS

p'

II

Fig, 8 - Dynamic characteristics circuit-CA3071.

___________________________________________________________

~7

CA3070, CA3071, CA3072 Types
.(O"'....u•• , ... ,.,.·,
.......
0"" •• ,0«.001. .....""0'.10" ..
"'.'.'O<>£""HlJPfOtOMM •. Nn"O/tK
'.I'(~'

'Q"~I.I

" ......... , 'H 6·7>

I

.....U.I~..( . . ' N _
__ IS 0 . . . . . . _w,n .... ,

I

II

I

Fig.l0- Frequency response for
wideband amplifier CA30n.

co""",,,,.., ..

Fig. 9 '- CA3071 Wideband amplifier
circuit.

Fig. 11 - Typical CA3071 wideband
amplifier linearity

:bb

CA3072 Chroma Demodulator

" ,,.

The CA3072 has two sets of synchronous detectors with
matrix circuits to achieve the A·Y, G·Y, and B·Y color

1~lk

difference output signals. The chroma input signal is applied

'"

'"

I

I

'I"

to terminal Nos. 3 and 4 while the oscillator injection signal
is applied to terminal Nos. 6 and 7. The color difference
signals. after matrix, have a fixed relationship of amplitude

I

and phase nominally equal de voltage levels. The outputs
of the CA3012 are suitable for driving high level color
difference or R, G, B output amplifiers. Emitter·follower
output stages used to drive the high level color amplifiers
have short·circuit protection.

'"
','
'"

CHROI.IA

MAXIMUM RATINGS, Absolute Maximum·Values at TA - 250 C

DC Supply Voltage (Terminal 8 to Terminal 14).. . .
. .. 27
V
Reference Input Voltage.
. ...... 5 vp-p
Chroma Input Voltage.
. .... 5 vp-p
Device Dissipation:
Up to TA '" +70 0 c..
530 mW
Above T A'" +7()OC ...
.... Derate linearly at 6.7 mW/oC
Ambient Temperature Range:
Operating.
-40 to +85oC
Storage .. _
.ffi to +150oC
Lead Temperature (During Soldering):
At distance 1/32 in (3.17 mm) from seating plane
for lOs max ...
+2ffioC

All RESISTORS IN OHMS
AllCAPA,CITOItSINpF

H

,

C~ItOI.l.l

Fig.

12 -

Schematic diagram for CA3072.

ELECTRICAL CHARACTERISTICS at TA = 25 0 C and V+ = +24 V unless otherwise specified
LIMITS

Ma.imum Voltage and Current Ratings

CHARACTERISTICS

SYMBOLS

SPECIAL TEST CONDITIONS

TEST
UNITS CIRCUITS

CAJ072

I

etTA =+25o C

FiG-:-

MIN. TYP·IMAX.

Statte Characteristics

Voltage·

Current

TermiRIII

MIN

MAX

TerminI!

No.

VOLTS

VOLTS

No.

3

0

4

0

....

6

0

7

0

."

•

0

m

9

0

·20

11

0

13

0

·20
·20

10
mA

mA

Supply Current
With Output Loads

1.0

20

11

1.0

20

13

1.0

20

"With reference to terminal No. 14 and
With the voltage between terminal No.8
and terminal No. 14 B,t +24 V except as
given in rating for terminal No.8.

$1 Closed

S, 0 pen

16.5

-

-

9

26.5

V9. Vll, Vl3

$, Closed

13.2

14.7

15.8

Chroma Inputs

V3. V4

S1 0 pen

-

3.3

-

Referenc~

V6. V7

$, Open

-

6.2

-

G·Y, R-Y, B-Y Outputs

."

IT

With No Output Loads

Subcarr,ier

mA
13
V

DynamIC Characteristics
Demodulator Unbalance
Maximum Co:or Difference
Output Voltage

v9.v11,vi3
v11

~ensjtivity

V3" V4 "0.6 Vp.p

5.5
1.2

v3

Relative R·Y Output

vll

Relative G- Y Output

v9

vp.p

8.0

v9

Chroma Input

0.8

V3=V4=O

v13

vp_p
0.2

Adjust ec for 5.0 vp_ p @ term

No.13lB·YI

0.35

3.5

4.2

0.75

1.25

IVgl-IVIII

VOC Difference Between
any two Output Terminals

IVgl-IVI31

0.6

ec "0

V

14

IV lll-I V I31

Input Impedance
Reference $ubcarrier Inputs
Input Impedance at
Chroma Inputs

fi6,7

ri3 ,4

pF
0.95

-

180

-

Output Resistance

Static characteristics test circuit-CA3072.

k!l
pF

Ci3,4

r09, roll.

Fig. 13 -

k!l

1.7

Ci6.7

!l

10 13

348 __________________________________________________________________

CA3070, CA3071, CA3072 Types

,.,

"'"""

IIIIT~'

ALL CAMCITOIt5G1IVDlIM.F
IMLI:UanEJtW\lf.NOTE[l
ALL MII.TMCD IN CHili.

Fig. 14· . Dynamic characteristics test circuit for CA3012.

Application Information
TYPICAL APPLICATION CIRCUIT FOR THE CHROMA
SYSTEM

12 UNIVtllSAL WIIIII.MQS,IIcI.s.5WIItE
.1I .... AIt,.: 11 lUllfIIS. Lon II~H,Q.40
SlCOIII[lAII"')4 T..-"CT.L·'~H.Q'2Q

The circuit of Fig.15: is a complete signal processing system
for color TV. The RCA types CA3070. CA3071 and CAJ072
monolithic integrated circuits are respectively used as the
subcarrier regenerator, chroma amplifier, and chroma
demodulator.
The input to the system is the chroma signal which may be
taken from the first or second video stage and is coupled into
the CA3071 chroma amplifier throus;. a bandpass filter. The
outputs from the system are the color difference signals
which are intended to drive high level amplifiers. Luminance
mixing may be external to the picture tube or, the difference
signals may be amplified and applied to the picture tube grid
or cathode, where they are internally mixed with the
luminance signal.
Other input requirements to the system 'are the power supply
voltage of +24 volts and the horizontal keying pulse. The
power supply voltage should be maintained within ±3 volts
of the recommended value of +24 volts. The total current for
the system is approximately 70 milliamperes. The horizontal
keying pulse input to the subcarriar regenerator is approxi·
mately +4 volts peak and centered on the burst as seen at
terminal Nos. 13 and 14 of the CA3070. The pulse width
should be maintained as close as possible to the recom·
mended value of 4.5 microseconds.
CA3070 Circuit Operation

......EylT...cr ....ur....... _.

•.

~~~~:I~~ ;:.-:=.cIT_r.~n
2~O

K

""

Fig. 15

~

Typical chroma system for color· TV receivers utilizing RCA·CA3010. CA30n, and CA3072.

oscillator transistor (0171. when the oscillator output ampli·
fier transistors (02 & 03) are cutoff. The chroma signal is
applied to terminal Nos. 13 and 14. There is oscillator
current drive to the APC and ACC detectors during the
keying interval; burst separation is effectively accomplished
by the gating action of the detectors. A further advantage of
the keying action is the high gain made possible as a result of
the low average current flow of the APC and ACC detectors.
High resistor values of 62 kilohms at the detector output
terminals provide proper detector bias consistent with the
duty factor of the keying pulse. For a wider keying pulse. it
is necessary that smaller values of detector load resistors be
used.

The CA3070 circuit as shown in Fig. 2, consists of an
oscillator, automatic phase control (APC) detector. auto·
matic chroma control (ACe) detector. gated oscillator
output amplifier and a shunt regulator. The shunt regulator
provides the necessary bias stability for the 3.579545 MHz
oscillator, as weU as the bias to all fuOl;tions of the CA3070
circuit. The tegUlation voltage is nominally +12 volts as
measured at terminal No. 10.

In the absence of the keying pulse (line period), the resistor,
A2Q. biases the oscillator's output amplifier transistors (02 &
03) on by keeping their emitters at a higher potential than
the base bias voltages of 05, 06. 09. and 010. The 3.58
MHz signal is now present at terminal Nos. 2 &: 3.
Photographs of oscilloscope traces for one line period at the
terminal Nos. 1, 2, and 3 are shown in Fig. 16. The effect of
the keying pulse is shown in Fig.16a, and the cutoff of the
oscillator output amplifier is shown in Fig.16(b) and 16c.

The APC and ACC detectors are synchronous detectors
which are keyed by the horizontal input pulse. This form of
detection eliminates the need for a burst separator as lin
individual amplifier stage. When a positive pulse is present at
terminal No.4, the oscillator output is cutoff and the
oscillator drive signal is diverted to the APC and ACC
detectors. Referring to Fig. 2, the APC detector (09 & 010)
and the ACC detector (05 & Os) are eminer driven from the

The oscillator section of the CA3070 consists of the loop
formed by 018 and the eminer driven differential pair. 0'3
&: 014. The signal output from terminal Nos. 7 & 8 is
ooupled through the series tuned a-ystal circuit back through
terminal No.6 to 016 & 017. The collector of 017 drives
the oscillator output amplifier and the APe & ACC de·
tectors. 017 is emitter coupled to transistor 018. The
oscillator frequency and phase control is accomplished by

the differential drive from the APC detector to transistors
& 015 which control the balance of 013 & 014. The
resulting phase of the feedback loop is determined by the
relative amplitudes of the oscillator output signal at terminal
Nos. 7 and 8. The 65 pF capacitor between terminal No.7
and 8 provides the phase shifting component.as the balance
of 013 and 014 is varied, In this way the APC detector
controls the crystal frequency at which the phase shift is
cancelled in the feedback loop.

an

The controls for the CA3070 subcarrier regenerator circuit
are the APC balance, the ACe balance, and the hue control.
The hue control is a dc balance adjustment of the oscillator
output amplifier transistors 02 & 03. A phase delay network
between the output terminals Nos. 2 & 3 determines the
range of the hue control, which for the value shown in Fig.
15, is approximately goo.
The ACe adjustment sets the initial balance of the ACC drive
to the input of the CA3071 in Fig. 15(terminal Nos. 1 and
14 of the CA3a71). The APe is a frequency adjustment of
the oscillator through the balance control of the APC
detector.
As a setup adjustment, for both the Ace and APC, switch 51
is opened and 52 is closed. The chroma input to the system is
removed and the dc voltage at terminal No.6 of the CA3071
is noted. The switch 52 is then opened and the ACC adjusted
to set the voltage at terminal No.6 to that previously noted.
Alternatively, the differential dc voltage at terminal Nos. 15
& 16 of the CA3070 may be set to 0 mV (±2 mV) when 51
and 52 are open. and the CA3071 is removed· from the
circuit .

•••
Fig. 16(a) - CA3010 terminal No.1

Fig. 16(b) -CA3010 terminal No.2, 3.5 Vp.p oscillator

Fig. 16(c) - CA3070 terminal No.3, 2.0 Vp_p oscillator

7.5 Voscillator "gate off'; pulse.

output; one horizontal line. (gated off during burst).

output: o"e horizontal line. (gated off during burst).

____________________________________________________________

~9

CA3070, CA3071, CA3072 Types
With the chroma signal still removed, the APe adjustment
sets the frequency of the oscillator to 3.579545 MHz. Due to
the gated off interval, a counter will not accurately record
the frequency at the oscillator output amplifier terminals.
Two simple and accurate methods are as follows: (1) a
buffered crystal filter circuit. connected to the oscillator
output amplifier terminals will continue to ring and fill

the gated off window providing the proper interface to a
counter; (2) the other method involves monitoring the
demodulated output at the color difference output terminals
of the CA3072. A zero beat signal, at the color difference
outputs may be seen on an oscilloscope.

When these adjustments are made, similar oscilloscope traces
should be seen as shown in Fig. 17.

CA3071 CIRCUIT OPERATION

rs

The CA3071
the basic amplifier and control circuit of the
chroma sv.'stem. It contains the gain control functions of the
ACC loop, the color killer, and the dc chroma gain control.
The CA3071 is a wide band amplifier having two stages of
voltage gain. Curves of frequency-response and linearity are
shown in Figs. 10& 11 for the wideband circuits shown in
Fig. 9. This is the same basic amplifier as the one in the
system shown in Fig. 15 except for the omission of the tuned
circuits and the ACC loop connection. The amplifiers have
bandwidths of greater than 10 MHz, and are usable well
beyond 30 MHz. The signal swing of the wide band amplifier
is in eKcess of 5 Vpop' even with the typical load coupling as
shown in Fig.15. Fig. 18 (a, b and c) show the oscilloscope
traces for an NTSC signal at the chroma input_ The overall
frequency-response curves are shown in Fig.19.
CA3071 operation is as follows (Refer to Figs. 6 &15). The
'inp~t chroma signal is applied to terminal No.2. This signal
is amplified in a cascade differential circuit from 010 to 012
and the output is an emitter follower. 014 (Terminal No.
6.) The signal is divided in the 09 &·012 differential
amplifier, depending on the applied ACC error signal ampli·
tude at termina.1 Nos. 1 & 14. The ACC error signal is de·
rived from terminal Nos. 15 & 16 of the CA3070 and after
filtering, is applied to terminal No~. 1 & 14 of the CA3071.
At low signal drive, the 390 kilohm resistl;)r at switch S1
(normally closed) unbalances the differential amplifier for
high signal gain through a'2. As the burst level at the
chroma input increases, the ACC drive ~hanges differentially
in a positive direction at terminal No. 14 and a negative
direction at terminal· No. 14 and a negative direction
at terminal No. 1. At strong signal levels the gain is
redUr.•-ed by diverting the balance of ac current in the
differential amplifier from 012 to Og, which is shunted to
ac ground at terminal Nos. 12 and 13. The ACC loop is
completed through the chromi31 signal at terminal NO.6 of
the CA3071 to terminal No. 14 (input) of the CA3070. A
typical ACe characteristic is shown in Fig. 23.
The chroma signal is buffer connected from terminal No.
to terminal No.7 of the CA3071 and is amplified in the 2nd
stage of voltage gain. Both the color killer adjustment and the
de chroma gain control are applied to the 2nd stage to
control the chroma output at terminal No.9. The color killer
section of the CA3071 is a Schmitt trigger & amplifier circuit
consisting of transistors Ql, 02 and 03. Under maximum
chroma output conditions, the diode 02 is reversed biased,
and the signal path is through 015, 04 and 05 to terminal
No.9. When the oolor killer circuit is actuated, or the
chroma gain control is adjusted to a higher positive voltage at
terminal No. 10, the anode voltage of diode 02 is increased
to draw current from the signal ·Path at the emitter of Q4.
This decreases the chroma gain as the potential at terminal
No. 10 is increased. When the potential at terminal No. 10
is the same a~ terminal No.8, the chroma output at terminal
.
9 is cutoff.
The colo~ killer circuit provides an abrupt voltage swing at
the anode of 02 to cutoff the chroma output when the
Schmitt trigger circuit is forward biased at terminal No. 13.
In the circuit of Fig. 18, the color killer adjustment is a
resistance divider circuit which establishes the threshold of
burst level at which the killer operates the chroma amplifier.
~O

CI!.3072 CIRCUIT OPERATION

The CA3072 is a chroma demodulator having full color
difference signal demodulation capability. The chroma signal
is applied to terminal Nos. 3 & 4 and the reference subcarrier
signal is applied to terminals Nos. 6 & 7 of the CA3072.
The output color difference signals are S·y at terminal
No. 13. R·Y at terminal No. 11, and G-Y at terminal No.9.
The typical level of differential chroma drive required at
terminal Nos. 3 & 4 is 400 mVp. p . The amplitude of
chroma at terminal No.6 & 7 is approximately 1.0 volt at Fig. 181a) - CA3071 chroma input 1.25 Vp-p;onehorizontal
104° relative phase difference which results in a S·y output
Une of NTSC input signal.
amplitude of 5V p_p . The voltages of the R·Y & G·Y outputs
are at 3.8 and 1.0 Vp.p respectively, when there is 5V p.p
output at B· Y. These comparative signals are based upon a
complete phase rotation of the chroma relative to the
subcarrier signal reference. The relative demodulation phase
and amplitude ratios of the Fig.15 circuit are shown in the
oscilloscope trace photographs
Fig. 21. Using the hue
control setting for S·Y phase at the S·Y output, the G·Y
color·difference signal is approximately _104 0 and the R·Y
color·difference signal is approximately +106°. Since the
Fig. 181b) -CA30n terminal No. 6; ampUfier No. 1 chroma
amplitude ratios are a function of the applied signal phase
output 2.J Vp.p: one horizontaf line for 1.25Vp-p chroma
relationship, the NTSC color difference output signals are
input
shown here primarily for phase reference conditions.

0'

CHROMA SYSTEM CONSTRUCTION

Fig. 25 shows the complete CA3070. CA3Q71 and CA3072
chroma system in the Fig. 1B circuit. Table I lists the de
terminal voltages for the system. The chroma gain and hue
controls. as well as the switches S1 and 52 are removed. The
template circuit board layout is also shown for duplication
purposes. It should be noted that a few component values are
modified in Fig. 18 from the dynamic circuit values of the
data sheet. These are necessary for system matching and
overall filter requi~ements.

Fig. 181C) -CAJOn terminaf No.9; amplifier No. 2chroma
output 5.5 Vp-p.· one horizontal line for 1.25Vp _p chroma
input

Fig. 171a) - CA3070 terminaf No.6, osciffator waveform
1.1 Vp .p 3.58 MHz.
Fig. 19(a) - Frequency response sweep curve between
terminal Nos. 2 & 6 for CA30n. f :: 250 KHz/div.

Fig. 17(b) - CAJ070 (erminal No.7. oscillator waveform
1.4 Vp _p 3_58 MHz_

Fig. 191b) - Frequency response sweep curve between
terminal No. 2 of CAJOn and termins/ No. 3 of CA3012.
f = 250 KHz/div.

'i>

~I~

~

jl250

>

~IOOO

*
Fig. 17(e) . CA30JO terminal No. 8;
1.6 Vp _p 3.58 MHz.
.

14

~

oscill~tor waveform
250

500

750

1000

1250

1500

NTSC CHROMA INPUT SIGNAL-IIIVp-p

Fig. 20·- Typical ACe characteristics for chroma system
of Fig. 18

__________________________________________________________________

CA3070, CA3071, CA3072 Types

-

- "'"

'-

Fig. 21 fa) . CA3072 . terminal No. 3 or 4, chroma input
signllf,220 mVp.p.one horizontal line

Fig. 21(b)' CA3072· terminal No.6 or 7. reference
subcarrier 1.2Vp 'p' one horizontal line

Fig. 21(c) • CA3012 termina' No. 13.4.8 vp.p B·Y ourpu~
one hor;zoritalline

-

,-

"""

..r -

Fig. 21(d)· CA3012· termina' No. 11.5.2 vp.p R·Youtput,
one horizontal line

____________

~

Fig. 21(e) • CA3012· termina' No.9, 1.2 vp-p G·Y output,
one horizontal line

____________________________________________________

~1

CA3088E
AM Receiver Subsystem

MAXIMUM RATINGS, Absolute MBx;mum VaJlltls, S1 TA .. 2SOC
DC SUPPL V VOLTAGE:

Includes: AM Converter, I F Amplifiers, Detector and Audio Preamplifier
For Applications in'a Variety of AM Broadcast and Communications
Receivers and Applications Requiring an Array of Amplifiers

Across Term. 5 and Terms. 3,

v

e, 13. 16. respectively

OCCURRENT:
At Terms. 3, 6,13,16, respectively

10
30

At Term. 10 •..............
DEVICE DISSIPATION:
UptoTA=500c ... " ..•....
Above TA. 5QOC .•. , ..

•

•
•

•
•

760

mW

derate line.arlv 7.6

mW/OC

AMBIENT TEMPERATURE RANGE:

Features:
•

mA
mA

Operallng •..•.•••.......•...
Storage ......••............•.

Excellent overload characteristics
AGe for I F amplifier
Buffered output signal for tuning
meter
Internal Zener diode provides voltage regulation
Two IF amplifier stages
Low·noise converter and first IF amplifier

-55 to +125
. .........•••..........

-65 to +150

LEAD TEMPERATURE (During soldering):

At distance not less than t/32" (O.79mml from case for 10 seconds max.

+266

"C

The CA3088E is supplied in the 16-lead dual- in-line plastic package,

• Low harmonic distortion (THOI
• Delayed AGe for.RF amplifier
• Terminals for optional inclusion

of tone control
•

Operates from wid. range of power supplies: V+ '" 6 to
16 volts
• Optio,",al AC and lor DC feedback on wide-band amplifier
• A;ray of amplifiers for general-purpose applications
• Suitable for use with optional external RF stage, either
MOS or bipolar

RCA-CA3088E·, a monolithic integrated circuit,

TO DETIECTOR
FILTER ANDALIlIO
(OPTIONAL TONIE CONTROl..
MAY BE SHUNTEO FROM
T£AMlNAL 9 TO GROUND)

an AM
subsystem that provides the converter, IF ampHfier, detector,
and audio preamplifier stages for an AM receiver.
IS

The CA3088E also provides internal AGC for the first IF
amplifier stage, delayed AGC for an OPtional external RF
amplifier, a buffer stage to drive a tuning meter. and
terminals facilitating the optional use of a tone control.
Fig. 2 is a functional diagram of the CAJ088E. The signal
from the low·noise converter is applied to the first IF
amplifier and is then coupled to the second IF amplifier.
This I F signal is then detected and externally filtered. The
resultant audio signal is applied to an audio preamplifier.
Optionally. a tone control circuit may be connected at the
junction of the detector circuit and the audio preamplifier.
The gain of the first IF amplifier stage is controlled by an
internal AGC circuit. The CA3088E supplies a delaYed
AGC signal output for use with an external R F amplifier. A
buffered output signal is also available for driving a tuning
meter. A DC voltage, internally regulated by a Zener diode,
supplies the second IF amplifier, the AGC and tunlOg meter
circuits and may also be used with any other stage.

r--t--t-,--t-----<~-;::==-----+_{i14

FROM DETIECTOR FILTER

AGC

~F~-",,-.~,-

;}-----OV+.9V

Fig.2-Functional block diagram of the CA30BBE.

The CA3088E features four independent transistor amp·
lifiers. each incorporating i..,ternal biasing for temperature
tracking. These amplifiers are particularly useful in general·
purpose amplifier, oscillator, and detector applications in a
wide variety of equipment designs.
-Formerly O@\lelopmentalTvpeTA5842.

Fig. , - Test circuit for DC characteristics.
Fig.3-Schematic diagram of the CA308BE.

~2

__________________________________________________________________

CA3088E
TYPICAL ELECTRICAL CHARACTERISTICS

CHARACTERISTIC

TEST CONDITIONS
TA·250C
V+-12V

I
TYPICAL
VALUES

UNITS

Vl.4,9.11

0.1

V

V2. 7,8
VlO

'.4
5.6
0
3.5

V
V
V
V

0.35
1.0
20
0
1.2

mA
mA
mA
mA
mA

SYMBOL

TEST
CIRCUIT
FIG. NO.

Static (DCI Chlrlcttfistics
DC Voltages;

Terms.l,4,9,11
Terms. 2, 7.8
Term. 10
Term. 12
TMm.15

DC Current:
Term. 3

Term. 6

Term. to
Term. 13
Term. 16

,

V'2
V'5
13
16
110

1

1'3
1'6

Dynamic Charaderistics
Detector Output
Audio Amplifier Gain

30% Moduliltion

AAF

Audio Distortion
Sensitivity:
At Converter Stage Input
At RF Stage Input

fiN

THD

Input Resistance:
At Transistor 01
At Transistor 05

RI

Input Capacitance:

CI

30% Modulation

At Transistor 01

Input signal frequency

At Transistor as

15
30
0.2

dB

2
4

200

~V1m

100

IlVJm

4

1.0

%

3500

!l
!l

2000

NoAGC,

(fiN)

'2

=, MHz

mVRMS

4
4
4

=1 MHz

Signal·to-Noise Ratio (SIN) " 20 dB

Total Harmonic Distortion

Feedback Capacitance:
At Transistor 01
At Transistor 05

f - 1 kHz
VOUT'" lOOmV

'1

%

pF
pF

CFB

The tYPical characteristics for the CAJ08BE are Intended for 9uldance purposes

'.5

1.5
In

pF
pF

evaluatmg this deYlCe for equipment design.

·0

AC4 .0,.1 IOU4l GATE-PAOUCTEO "OS"ETI
ARE ' .. O""S
ALL caPACITANCE VALUES "liE IN NICRor""AOS
ALL RESIST ... tE VALUIS

Fig.4- Typical AM broadcast receiver using the CA3088E with optional R F amplifier stage,

353

CA3089E
FM IF System

ALL RESI$TANCf IIALUES ARE IN O>lMS
TUNES WITH 100 pF te) AT 107 MI-ll

~ l

00 ~ 7~ IG·l. EX22741 OR EOUIIiAlOH-1

Includes---I F Amplifier, Quadrature Detector,
AF Preamplifier, and Specific Circuits for AGC,
AFC, Muting (Squelch), and Tuning Meter
For FM I F Amplifier Applications in High-Fidelity
Automotive, and Communications Receivers

Features:
• Exceptional limiting sensitivity:
12 #J.V typo at -3 dB point
• Low distortion: 0.1% typo
{with double-tuned «Xliii
• Single·coil tuning capability

Block diagram of the CA3089E.

The CA3089E is supplied in the 16-Iead dual-in-line plastic package_

• High recovered audio:
400 mV typo

• Provides specific signal for
control of interchannel muting

(.quelchl

~r-------r--+-"A"

• Provides specific signal for
direct drive of a tuning metsr

• Provides delayed AGe voltage lor RF amplifier
• Provides a specific circuit for flexible AFC
-Internal supply-voltage regulators

".

'27

RCA·CA3089E is a monolithic integrated circuit that provides
all the functions of a comprehensive FM·IF system. Fig. 1 is
a block diagram showing the CA3089E features, which include
a three-stage FM·IF amplifier/limiter configuration with level
detectors for each stage, a doubly-balanced quadrature FM
detector and an audio amplifier that features the oPtional use
of a muting (squelch) circuit.
TIw advanced circuit design of the I F system includes
desirable deluxe features such as delayed AGC for the RF
tuner, an AFC drive circuit, and an output signal to drive a
tuning meter andlor provide stereo switching logic. In
addition, internal power supply regulators maintain a nearly
constant current drain over the voltage supply range of +8.5
to +16 volts.

,,.

'21

~T"''VV-,---C"

The CA3089E is ideal for high·fidelity operation. Distortion
in a CA3089E FM·IF System is primarily a function of the
phase linearity characteristic of the uutboard detector coil.

",-

L---t--"'"

ALL RESISTANCE VALUES ARE IN OHMS
• WALLER 4SN3rIC OR EQUIVALENl
•• "'-JRAlA SFG J07MA OR EQUIVALENT

• t,TIJIIESWITHIOOpFICIATIO.TMHI
00 UNlOAOE017~ IG,l EX227.1 OR EQUIVALENT)

Performance data at fo .. 98 MHz, 'MOO "" 400 Hz,
Deviation" .175 kHz:
·3dB limiting Sensitivity
2JJV (Antenna Level)
20dB Quieting Sensitivity . . • . . 1,uV (Antenna Level)
lOdS Quieting Sensitivity . . . . 15,uV (Antenna Level)

.....- - - - -.....--------t----t---'"

~---AGe FOR
RF AMPL

LEVEL DETECTOR

a METER

CIRCUIT

Fig.,2·Schematic diagram of the CA3089E.

Fig. 1· Typical FM tuner using the CA3089E with asing/e·tuned
detector coil.

~4

_________________________________________________________________

CA3089E
MAxiMUM 'RAt)NG$~ Absolute Maximum Values, at TA
DC Supply Voltage:
SetMen Terminals 11 and 4
B~tween Terminals 11 and 14.
DC Current (out of Terminal 15)
Device Dissipation:
Up to TA = sooe
Above TA = OOOe
AmbientTemperature Range:
Operating . . .
Storage . .
. ...... .
Lead Temperature (During Soldering):
At distance not less than 1132" (O.79mml fl't)Jn

= 2d'C

v

16
16

V
rnA

600

rnW

derate linearly 6,7 mWfC

-55to+125
·65 to +150
q 1.6V TO ACTIVATE STEREO
V4< 0.9 V TO DEACTIVATE STEREO

Fig. 4 - Test circuit for use with

st~r~o def~atlenabJe.

Fig. 5 - Test circuit for use without stereo defeatienabill.

_______________________________________________________________

~7

CA3090AQ
ELECTRICAL CHARACTERISTICS
TEST CONDITIONS
TERMINAL
MEASURED
AND
SYMBOL

T A _ 25°C
V+. 12 V (unless
specified otherwise'

Total Current (Terms. 9,10.11)

Itotal

Lamp OFF

DC Voltage:
Term. 1

V,

V9& 10

CHARACTERISTIC

LIMITS

Min.

Typ. Max.

UNITS
(CONDITIONS
SUFFICIENT
FOR 19- kHI
PilOT-TONE TO
PHASE-LOCK

Static Chlr8Cteristies

22

27

mA

1.6

2.3

3.1

V

2.1

3.6

V

4.7

6.4

8.4

V

Term. 6 (Indicator lamp OFF)
Terms. 9 and 10

Term. 12 !Indicator LampOFF)

y+ = 16 V

12.7

Voltage Differential (Term. 2- Term. 1)
Current al Term. 12 (In actual use external circuit
resistance (e.g. lamp should limit Term. 12 to the

VIN (at f = 19 kHzl

=:

18 mY

75

V
0

0.1

V

100

-

mA

maximum rated value ot 100 rnA.)

1;~:PJ~oRf ")

6"

72

76

84

VOLTAGE -CONTROLLED OSCILLATOR (veo) FREQUENCY
(NOPII..OT TONE APPLlEO)-kHr

Fig. 7 - Pilot-tone voltage level vs. VCO frequency wirh no
pilot·tone applifd.

~~:~;NETR i~~:~~AV~UL;:~~A\~t~;!~ v

::~~ 1~E :i~~ ~;l

.~~~OT VOLTAG': !_AT I~ "H, )'18 mv R~~ ::.:.. :~~i: 5~:f[ffi

Input Impedance

50k

Channel Separation (L + A Reference)'"

25

Channel Balance (Monaural!
Monaural Gain

VIN = 180 mV

40
0.3
til.3

Indicator Lamp - Turn-ON Voltage

19·kHz pilot·tone@ Term. 1

Capture Range (Deviation from 76-kHz center
frequency)

19·kHz pilot-tone
voltage = 18 mV

"" ~~" "'~ :,,' "'~ ~T~td:": ,:i· r,,~i ,'.. ii:' ~;.
';:, :::: ':~FIf,:]iHjf;~

,i:';" :'::

d8
d8
d8

6

Stereo/Monaural Gain Ratio·

Distortion (75-/-1$ de-emphasis):
2nd Harmonic

n

-

±3

d8

mV
"'.6

±1O

%

0.2

VIN = 240 mV

3rd. 4th. and 5th Harmonic

<0.1

19-k Hz Rejection

%
64

-

%

35
48
70

38-kHz Rejection
SCA (storecastl Rejection
Stereo Defeat Voltage (V 4)

1.2

Stereo Enable Voltage IV 4)

>1.6 1.2

~

n

~

60

S4

~

VOLTAGE-CONTFWLI..(O OSCILlATOR{VCO! FREQUENCY
(NO PILOT TONE APPlIE01-kHl

-

•

..!!...

0---02'

.r.

Figs. 2 and 8.

~02
Fig.7 - Test condition values for associated switches 1 through 20 (switches 6, 7, and 10 are omitted).
Refer to Figs. 2 end 8 for test circuit and test-condition selector'switch arrangements.

~

~

MEASURE VOLTAGE

2

~
SVI

18

I

MEASURE VOL rAGE

2
0 - - - 0 MEASURE VOLTAGE

~

~

TUNER

~I

DELAVfllAS
~·6.

o'

H

~

•
0-----0 MEASURE VOLTAGE

~~

I

":"

~
2

-

l!J

~24V
.Ollil

NOTE: The Italicized numbers in the IqUilre boxes ref.
to the 17 .witchet I.witchet 6, 7, and 10 ant
omined) of the test circuit end corr.pond to
those given in Figs. 2 ~nd 7.
CAUTION: Remove power before selecting or adjusting switches
R[',ISTANCEVALU[S
ARE ''''O,"MS

"SYNC

Fill,8 - Tolf condition ..'octor :~==:':rK==-=;===i 7."MA:;:;;;;- II

AMPL.

No.2 a
CHROMA
GAIN

BIAS

CONTROL

R7

RO

RI3

270

2.7 K

390

RI7
540

023

CIRCUllR
RIO

1.21<

R2>
5.6K

R-Y

DEMOD.

R32
6.8 K

92CL-20848Rt

Fig. 4 - Schematic diagram of the CA3121G .

Fig. 5 - Simplified functional diagram of a two-package TV chroma system utilizing

the CA3121G and CA3010 or CA3110.

__________________________________________________________________ 365

CA3121G
~2~.7~M~~oH·o_'~________________~__________~r-r-

__~O+24V

TO TERM.6

~o.o.

470

I
I
I
I
I
I
I
I

0'°4

CA3121G

I
I

I
I
I

I
IL ___ _

I

--A:-~F-o.o~

3

0,01

8.2 K

--1-1--....]

+24 V

68Q

=

100

6

100
1.8 M

12

47

470

470

5K
CHROMA
GAIN CONT.

+ 24

50

V

390 K
680

1.2 M

20 K
APC
ADJ

20 K

62.

410ltW

2.7 K

62<

62 K

62K

ACC
ADJ

50

3"
IK

HORIZ. KEY PULSE

+4V,4.5J's

INPUT

RESISTANCE VALUfS ARE IN OHMS.
UNLESS OTHERWISE INDICATED, ALL CAPACITANCE
VALUES LESS THAN I ARE IN MICROFARADS,
lOR GREATER ARE IN PICOFARADS.

Fig. 6 - Outboard circuitry of a typical two-package chroma system for
color- TV receivers utilizing the CA3121 G and CA3170.

366 _______________________________________________________________

CA3123E
AM Radio Receiver Subsystem

Features:
• Low-noise,low-Rb' rf stage in cascade connection-

Includes R F Amplifier, I F Amplifier, Mixer,
Oscillator, AGe Detector, and Voltage Regulator

eliminates Miller·Effect regeneration and allows con-

L3

RFOUTPUT

v· ,

trolled power rise by the choice of external components
• Mixer-oscillator stage with internal feedback eliminates need for tapped or multi-winding

The CA3123E- is a monolithic silicon integrated circuit
that provides an rl amplifier. if amplifier. mixer, oscili3tor.
AGC detector, and voltage regulator on a single chip. It is
intended for use in super·heterodyne AM radio receiver

MIXER INP"'UT_-'1--_ _ _ _-o(iiiiEiil--+""-'...o"""IXER OUTPUT
eSCLLL.ATOA TANK 2

MLXER BYPASS

..

AGe ORL"'VE'--"'+-_=_-G>GCJ~_t"O!!...!'''GC CAPACLTOR

oscillator coils
• Cascade if amplifier with controlled output impedance

IF LNPU",,---,,'t-_-"--'

and negligible Miller Effect -

9

RF GROUNO

8

Su8STRATE AND
IF A MPL.. GROUNO

eliminates regeneration and selectivity skewing

applications particularly in automobiles. The CA3123E is
supplied in a 14·lead dual·jn·line plastic package and operates
over the temperature range of -550 to 125 0 C.

• Frequancy-counter AGe circuit allows control of AGe response by selection of the
coupling capacitor

• Formerly RCA Dev. No. TA6155

TfJfminal assignment diagram.

• Integral regulation with built·in surge protection
• Separately accessible amplifiers
MAXIMUM RATINQS,Absolute·Muimum Values:
DC SUPPl.Y VOLTAGE:
At Terminal No.3 (V+j .......
9V
At Terminal No.6 (I F Output I
40 V
20 V
At Terminal No. 13(RF Outputl .
At Terminal No. 14 (Mixer Output!
20 V
DC CURRENT:
InlO Terminal No.3 IV+' . .
35 mA
DEVICE DISSIPATION:
Up to TA • 55 0C.........
750 mW
AboyltT A. 550C ................. derate linearly 6.67 mW/oC

ELECTRICAL CHARACTER ISTICS at TA ~ 25°C
CHARACTERISTIC

SYMBOL

TEST CONDITIONS

I
I

LIMITS
Min.

I

Typ.

I

Mu.

I
I

UNITS

Swtlc Ch.racte,llticlln Circuit af Fig, 3
DC Voltage:
At Terminal11, 4

6,8

At Terminal 5

0.25

At Terminal 6

'2

At Terminal 7

0.76

v
v

0.71

v
v
v

At Terminals 8,9
At Terminals 10, 11
At Terminal 12

0.71

V'2

At Terminal 13

4,0

Into Terminals 1, 4, 5, 7

'1,1 4 ,1 5 .1 7 ,

8.9,10,11,12

mA
mA
mA
mA
mA

1.2

'5

I nto Terminal 3

4,3

'6

4,5

Into Terminal 13
Into Terminal 14

"4

0.170

f---+---j--+-+----l\- o.:~~~\/mv

a~ ~l~**~~
f==
,~-+_-+_-_r-_+-_+-\~----

Pirformanci Ch.racteristics In Ci,cuit of Fig. 3
Input Signal to Dummy
Antenna at 'IN"" MHz,
Sensitivity

TYPICAL CHARACTERISTICS

mA

18 ,'9,'10.1,1,1 ,2

Into Terminal 2
Into Terminal 6

-55 to +125 oC
-65 to +15oDc

v
v
v
v

4,7

At Terminals 2, 3,14

AMBIENT TEMPERATURE RANGE:
Operating ...................... .
Storage ........................ .
l.EAD TEMPERATURE IDuringSoldering):
At distance '/16" ± 1/3"
f1.59 mm ± 0.79 mml
from case for 10 s mex ......... .

,0

2,3

30% AM Modulation at
'MOo"'400 Hz, lor 11 mV

o

\

200

300

INPUT VOL.TAGE

output al Vo

400

~O

600

ItLN1-mVRMS

FIll- , - Control of RF stage by signal into Terminal No.5.

Ratio 01 Output at Vo
with Modulation ON and ttlen

SIN

Signal·to·Noise Ratio

OFF,lnputSignalclOO~V.

d8

34

43

160000

400000

30% AM Modulation at
f MOD =400 Hz
Input Signal set at
1 MHz. 90% AM
Modulation, Distortion
atV o must be

Overload Distortion

Vo
+12V

< '0%
Dynamic Characteristics For Indic.tlld St,", In Circuit of Fig. 3

PII"IIII C.PlCitlncl

S....

Input
pF

RF Amplifier

80

IF Amplifier

35

Mixer

Output
pF

3:5

Par,U.1 Resistance
Input

Output

750

"

2 x 106 min.

"

140000

950

ul"

80000

2000

2)t 106 min.

""1 ·

:;e"'' :'

2500 (Mixer!
3000 (Amplifier)

Fig. 2- Test circuit for Fig. ,.

__________________________________________________________________ 367

CA3123E

·27 pF CAPACITOR IN SERifS WITH INPUT GENERATOR
REPRESENTS A DUMMY ·WINOSHIELo"~TYpe ANTENNA

Transformer

Symbol

First IF:
Primary

Frequency

Inductance

Capacitance

Q

.uh(~

pF(~

I""

2840

130

60

2840

130

60

or 30:1
31:1

262 kHz

T2
Second IF:

262 kHz

~
Secondary

T3

Antenna:
Primary

1 MHz

Total Turns To
rap Turns Ratio

2840

130

60

8.5:1

2840

130

60

8.5:1

195

Je, l-t30

65

Coupling

critical
:::::O.017~1/a

critical
:::::0.017:::::1/0

Adjusted to an impedance of 75 n. with primary resonant at 1 MHz. Coupling should be as tight as practical.
Wir. should be wound around end of coil away from tuning core.

Secondary

7.9 MHz
Coil.

50

55
41

1 MHz

1.262 MHz

50

40

FI,. 3- Sch.",atic diagram of AM radio rtICei~tlr using CA3123E•

.,

INPUT

er:ss @---r-t-"

I:U:::::®--.. . .--______+-__________

~I_+_---'I-......- - - '

Fig. ,,- Schsmlltic dill9fllm af CA3123E.

PERFORMANCE CHARACTERISTICS IN CIRCUIT OF FIG_ 3

.10 AMBIENT TEMPERATURE {T,Al"ZS"C:

I

1111

I

1111

I II I Jl

~

I

OUTPUT VOLTAGE (VoI.eSmV

o ~J I L~ . .
-~
-20

.-~,~~ I iT~H-+tI-'+-H-tt-+-HtI
lQ'" u.t MOO\J\..ATIOti AT
t""OO·"'OOHI

,--i

NOTE: AMPLIFIER CIRCUIT IS tDENTICAL FOR
BOTH TYPES EXCEPT FOR IN\!. INPUT ANO
FEEDBACK LOOP (lNCLUOING Rt AND R21
THESE CIRCUIT AODIT10NS. SHOWN WITH DDT
TED LINES. APPLY ONLY TO TYPE CA3131EM

v-

'"

BIAS
SOURCE

INPUT
OJTPUT
COMPENSATION

Fig. 2-Schematic diagram of types CA3131EM and CA3132EM.

v-

'"

"

"

O.I .. F

1
1000* ..

"I
,
!
.. A 1000-pF capacitor is required it input has an open circuit .
.. External resistors Rl and R2 are used onlv with the CA3132EM. When testing the CA3131EM.
omit Rl and R2 and connect the (... ) termination of C5 to Terminal 16.

Fig. 3- Test circuit for types CA3131EM and CA3132EM.

Fig. 4-Printed-circuit board (actual size) containing
the test circuit, shown in Fig. 3, for the
CA3131£M

_____________________________________________________________

~3

CA3134G, CA3134GM, CA3134GQM

TV Sound IF and Audio Output Subsystems
The RCA·CA3134 combines the sound if
and audio output subsystems on a single
monolithic integrated circuit to provide a
television sound system for color or black
and white applications. Each device includes
a mUltistage if amplifier·limiter, and fm
detector, and an audio power amplifier that
is designed to drive an 8·, 16·, or 32·ohm
speaker.
The CA3134 is supplied in the hermetic
Gold·CHIP, which is of the sealed·junction
type designed to provide protection against
the deteriorating effects of humidity and
other surface contaminants without the need
for a hermetic package enclosure. This
hermetic chip is encapsulated in a 16·lead
plastic "power stud" dual·in·line package,
which has an inherently low junction·to·case
(stud) thermal resistance. This package lends
itself to a wide variety of heat·sink methods,
depending on the application requirements.
The CA3134G is supplied in the 16·lead
plastic "power stud" dual·in·line package.
The CA3134GM and CA3134GOM are simi·
lar to the CA3134G except that they in·
corporate a tin·plated copper·strap heat sink.
The CA3134GOM also has quad·formed leads.

MAXIMUM RATINGS. Absolute·Maximum Values:

CA3134GM.
CA3134GOM

CA3134G
OC SUPPLY VOLTAGE (Between Term. I,
V+ and Terms.4. audio-output ground and
13, substrate) .
INPUT SIGNAL VOLTAGE (Between
Terms. 14 and 15) .
OEVICE DISSIPATION:
With Infinite Heat SinkUp to T A = 7000C .
derate linearly
Above T A = 70 C

33

V

33

±3
6.5
83.3

mwi"c

With no Heat SinkUp to T A = 2S ooC •
AboveT A ~ 25 C
With Copper·Strap Heat SinkSoldered to PC Board
Up to T A = 2500C
AboveT A =25C

dera~e

linearly

1.4

w

11.1

mWi"C

w

derate linearly

3.9
31.2

mW/C

derate linearly

2.5
20

mWi"C

Unsoldered
Up to T A = 25 0 C
Above T A = 25°C
THERMAL RESISTANCE

Junction to Stud

12

,

w

12

AMBIENT TEMPERATURE RANGE:

Operating
Storage •

-40 to +85
_ _ _ _ -65 to +150

LEAD TEMPERATURE (During Soldering):
At. distance 1/16 in. ±1/32 in. (1.59 :10.79 mm)

from case for 10 seconds max ..

_ _ _ _ _ +265

OPTIONAL
r-~--t----O UNATTENUATEO

I
'>
136k <

I
...LOO?.
F

,I < .,. . ,.

Features:

<

• Output power 3W (typ.) at V+ =24V, R L =16!2
• Power amplifier with current limiting and
thermal shutdown
• Wide power·supply range: 12V to 33V
• Low quiescent current: 30 rnA typo
• 5·kHz deviation sensitivity: 1W output typo
• 3·dB limiting sensitivity: 200 J-lV typo
• Excellent AM rejection: 50 dB typo
• Differential peak detector-requires one tuned coil
• Electronic volume control with improved taper
• Optional unattenuated audio output
• Optional power·supply ripple by·pass
• Hermetic Gold·CHIP

~

AUDIO OUTPUT
(IF NOT USED,
GROUND TERM. BJ

I

~

VOLUME CONTROL
16 FOR ELECTRONIC
ATTENUATOR

15\ RF INPUTS
"

~~~I~N~MPUFIER 4

I

SUBSTRATE GROUND

NO CONNECTION 5

12

~~~~~~OCNOI~~?VE~°tfATOR

POWER SUPPLY

6

RIPPLE BY- PASS

II \FM DETECTOR

~~~J~ AMPLIFIER 7

10

~~~I~T~~~~~iD

9

B

TUNING

ALTERNATE
VOLUME - CONTROL
CIRCUIT

AUDIO OUTPUT FROM
ELECTRONIC
ATTENUATQR
92CS-256:WRI

Fig. I - Terminal diagram of the CA3134G,
CA3134GM, and CA3134GQM.

92CS-241!5A3

Fig. 2 - Block diagram of the CA3134 in a typical circuit application.

374 _________________________________________________________________

CA3134G, CA3134GM, CA3134GQM
ELECTRICAL CHARACTERISTICS
Test Conditions: TA· 25°C. V+· +30 V (applied to Term. 1). DC Volume ContrQI.
RX· 75 kn. RL • 16 n. unless otherwisa Indicated. Refer'to Fig.2.
CHARACTERISTIC

SPECIAL TEST
CONDITIONS

,

I

UNITS

··f

Min. Typ. Max.

PO=O

15

30

45

>,;+t"-,"'" ~"
""- >,~

-,Y

• .co:

... b-

~

1

•

Static Characteristics
Current into Term. 1. 11

I-=.

·•

~

0

LIMITS

I

10,

OJ,;

~

~.,.~J,;

rnA

Dynamic Characteristics
IF AMPLIFIER:
Input Limiting Voltage,
V15(1im)
(at -3 dB point)
AM Rejection.

AMR

2
04
I
a 10
2
. . . '100
EFFECTIVE l.OAD RESISTANCE IAl.l-nucs.so,:se

fO = 45 MHz
fm = 400 Hz
f).f = ±25 kHz

-

fO = 4.5 MHz, fm = 400 Hz.
Modulation Index = 0.3,
V15=20mV

40

200

50

V1S=3SmV

-

25

Input Capacitance, CI

V15=35mV

-

3

Total Harmonic Distortion,
ITHD)
Output Resistance, RO
ATTENUATOR:
Maximum Attenuation
UNATTENUATED AUDIO:
Recovered af Voltage
(Term. 8), VOla!)
Total Harmonic Distortion (THD)
AUDIO POWER AMPLIFIER:
Voltage Gain, A(af)

p.V

Fig. 3 - Maximum output power as a function of

effective load resistance.

Input Resistance, RI

DETECTOR:
Recovered af Voltage
(Term. 9), VO(af)

400

-

dB

-

kn

,c'"

-

700

-

0.8

-

7.5

RX =0

-

10

fO = 4.5 MHz, fm = 400 Hz,
f).f = ±25 kHz, V 15 = 100mV

-

At Term. 9

-

mV
3

%

r---

H

..-:::
·a .•:..-8

kn

15

mV

600

-

mV

-

0.8

-

%

-

35

-

dB

-

1.5

-

et\.

~\.

,. ¢~

.\.~

C} ~-

r 0";"'"

.c·>'~

-"--I-

."...

"

~ , -t-.

., ,

,

10
0.1

-

1 ';:',.c\·

tS\o;,~I-~~

- co•o';';--:

';:100

~

fO = 4.5 MHz, fm = 400 Hz,
f).f = ±25 kHz, V15 = 100 mV

"I'" '"'

·f ·~..
2

pF

T'"':'!" ',L~2

I
I

A3.

A3'

loon

10K

2.2K

042
1.21(

I
I GAIN CONTROLLER
L _______ _

--0
I

VOLTAGE
AEF

AUTOMATIC
BRIGHTNESS
LIMITER

(ABll

GND
OA
OPTIONAL
ABL

CHROMINANCE
INPUT

tZCt.-21079R2:

Fig. 2 - Schematic diagram

of sync or video signals. Term. 12 is a highimpedance point, and the emitter·follower
026 is used to bring the signal out to term.ll.
The signal voltage at term. 11 is directly
coupled through a resistor to term. B, generating a current in term. B. This current is
amplified 10 times by the current mirror
051, 052, and 053. Blanking during the
vertical retrace interval is accomplished at
050 via term. 7. Term. 7 is normally high
enough to keep 049 in saturation. A negative pulse from the vertical circuit cuts
049 off, allowing some of the current
through R51 to saturate 050. When 050
sinks the term. B input current, there is no
output from term. 9 - as if the signal were
blacker-than·black. The output current from
term. 9 is used to drive the receiver's RGB
matrix and the amplifiers that drive the
picture tube.
The chrominance signal is taken from· the
first chroma amplifier following the auto·
~O

matic chroma control (ACC) and coupled
through a capacitor to term. 4. The signal is
attenuated by R38 and R37 and applied to
an emitter·follower amplifier which drives
the emitter of 043. The current is steered
through 040 and 041 depending on the
gain·control conditions to the load resistors.
An emitter-follower 046 feeds term. 6, and
R46 and 045 provide short·circuit protec'
tion. The chroma amplifier is also blanked
via the input at term .. 7. The negative pulse
at term. 7 allows the current through R51
to feed the base of 044 (as well as the base
of the video blanker, 050). When 044 satu·
rates, the current is cut off in 043 to disable
the amplifier.
The combined gain control for the video
and chroma sections is operated by vary·
ing the voltage on term. 16 between ground
and the positive supply. Term. 16 has an
emitter-follower 031 loaded by a current
source 032. The voltage on term. 16 then
determines whether the flow of current in

R31 goes through 036 or through 033 to
the resistors R24 and R26. The current on
the 033 side, a portion of the total current,
is varied linearly by the control voltage. The
gain-control amplifiers are slaves which follow
the linear current control. The transistors
034 and 035 are driven as Darlington stages
to reduce base-current effects in the control
circuit. The normal gain·control function
causes a change in the voltage on the base of
034 with respect to the reference voltage at
the base of 035. The gain can al.so be
changed by altering this reference voltage.
This change in reference voltage is also used
for "brightness limiting": The picture·tube
current is sensed, and, when it exceeds some
predetermined level, a voltage applied to
term. 2 turns 038 ON to reduce the refer·
ence voltage, thereby reducing the gain.
Under these conditions, there is a closed
feedback loop; the gain is set at a point
such th,at the picture·tube current is just
sufficient to cause a little conduction in 038.

_____________________________________________________________

CA3135G
BUFFERED
CLAMPED

LUMINANCE
OUTPUT
13

CLAMP

VIDEO
II

HORIZ

PULSE INPUT
10

A---

RZO

10'
RI.
RI.

glon
RI'

47.

ozz

RZI

I

I
I
,L- ____ _
"

8 PIX
PEAKING

------~~~~---+~~---------+-,-I

I
I

ILU:INANCE

I

I

I

OUTPUT

I

I
I

I

I
I
I
UI---'\J'VV--;

R~:5

R••

I.

R47

I.

KXla

RM

I·SK

I
Ion I

RS'

I
I

R••
8.ZK

BLANKER

--~

L --':'D£O ___I
ALL RESISTANCES ARE IHOHMS

\lERT.

GND

PUL.SE

INPUT

9lCL.-ZI07'tRZ

Fig. 2 - Schematic diagram

+ 12 V

o--.-----..-------1~-_,

Fig. 3 - Static characteristics test circuit.

_____________________________________________________________________

~1

CA3135G
+IIV

SUPPLY VOLTAGEIV+I-VOC

92CS-30614

Fig. 5 - Typical chroma amplifier maximum
linear voltage as a function of

Fig. 4 - Dynamic characteristics test circuit.

supply voltage.

30 AMBIENT TEMPERATURE (TAI=2.S-C
INPUT AT TERM.4-S30mIJRMS
FREQUENCY I fI = 3.58 MHr

10
SUPPL.Y VOLTAGE (V+, -

Voe

Fig. 6 - Typical maximum linear luminance voltage at terminal 15 as a function of supply

"

10

92C5-30812

"

. 92CS -30873

Fig. 7 - Typical chroma amplifier phase shift as a
function of supply voltage.

lIo/tage.

f' 6 AMBIENT TEMPERATURE (TAl- 2.5-C
,:SUPPLY VOLTAGE IV+)'12 V
I 5.5 LUMINANCE INPUT (TERM 15)- 0.2Vp _ p

I

15
"

SUPPLY VOLTAGE IV+I-"oc

OUTPUT AT TERM. 9 -

Vp _ p

92CS-10815

Fig. 8 - Input voltage as a function of output
1I0ltage.

:---

;;

~ .~--+---+---+---+---+-~
~

S 4.5~--+---+---+---+---+-~

S
o

~

.
I----t-::l:=:!:=:!:::::t---j OIREF)
I

/

j3.~II----+t~+---+---+---~~ -I d8

~

1\
\
,----+----+----+----+--+:1

311---"""*
1----+----+----+----+---1.-1 -2"

82.~11----H
•

2

"

100
IK
10K lOOK
F"AEOUENCY (f)-Hz

I

1M

-3d8
-4d8
-5dB

10M

NeS·lOI"S

Fig. 9 - Tvpical gain-bandwidth response.

~2

_______________________________________________________________

CA3136E

Preliminary Data
Features:

TV Video IF
Phase-Locked-Loop
Synchronous Detector
for Color TV Receivers
The RCA-CA3136E is a linear IC synchronous detector employing a phase-locked
oscillator to demodulate the 45.75·MHz
video if signals in color-TV receivers. The
CA3136E features AFT voltage for dc control of the tuner; an adjustment for the
zero-carrier dc level at the video output

• PLL carrier oscillator with wide pull-in and hold-in range
• Excellent low-level detector linearity

• Automatic Fine Tuning (AFT) Detector

• Noise inversion at video output

• Separate output for sound take-off

• Wide range, variable zero-carrier

• 12-volt power supnly

level adjustment
terminal; an amplifier arrangement for inverting noise impulses toward the black
level; and a separate output terminal (noninverting) for the sound if.

LIMITER
TUNING
LIMITER
TUNING
GROUND tV-)

The CA3136E is supplied in a 16-lead
plastic "power-stud" dual-in-line package.

APe FILTER 5

MAXIMUM RATINGS,Absolute-Maximum Values:
Power Supply Current
Input Signal VoltageDevice Dissipation:
With no Heat Sink:
Up to T A = 2Soe
Above T A = 25 0 e
With Infinite Heat Sink:
Up to T A = 70 0 e
Above T A = 70 0 e .
Thermal Resistance:

1.4 W
derate linearly at 11.1 mW/oC

ReJS (Junction to Stud)

. 12 0 e1W

GOING SYNC.)

fA~~~gFF

9ZCS-2S845

TERMINAL DIAGRAM

6.SW

SUGGESTED GENERAL ALIGNMENT
PROCEDURE

derate linearly at 83.3 mW/oC

Fig. 1 shows a block diagram of the CA3136
in a typical circuit indicating the internal
functions as well as the external circuitry
and signals. A 45.75-MHz, 100-mVrms (50ohm) signal is applied to the VIDEO IF INPUT (Terminal 4). While monitoring the
VIDEO OUTPUT (Terminal 10), make the
following adjustments in the indicated sequence; (1) adjust the VCO TUNING coil
for a dc signal (lock). (2) Adjust the LIMITER
TUNING coil for a minimum dc voltage on
Terminal 10. (3) Adjust the VCO TUNING

Lead Temperature (During Soldering):
(1.59

± 0.79

mm) from case

for 10 seconds max.

AFT OUTPUT

VO~

.001

coil for 5.2 Vdc on Terminal 5 (with 12 volt
supply on Terminal 8). (4) Close the AFT
DEFEAT switch and note the dc voltage at
the AFT OUTPUT (Terminal 12). (5) Return
the AFT DEFEAT switch to its open position, and adjust the AFT TUNING coil
for the same de voltage noted when the
AFT DEFEAT switch was closed. (6) Remove the rf input and adjust the ZERO
CARRIER BIAS potentiometer for 7 volts
dc on the VIDEO OUTPUT (Terminal 10).
This final adjustment completes the alignment
procedure.

r-----I
I

I
AFT TUNING

(~~~~~,~r!,UT

10

9

-40 to +85 0 e
-65 to +150 0 e

[0= Je' ,4

TUNING 7

OUTPUT

Operating

AFT OEFEAT

yeo

6

TOP VIEW

Storage

± 1/32 in.

TUNING

1 Vrms

Ambient Temperature Range:

At a distance 1/16 in.

yeo

. 15 V
100 mA

Power Supply Voltage

3

YIDEO IF
INPUT

I
I
lNV. AMPL·

-----------------------u--ALL RESISTANCES IN OHMS

GND

GND

3

13

VIDEO IF INPUT

---r
V'N

7

v --J'c---I.

,v

ov

150 mVrms
(MODULATION
ENVELOPE)

~

92CM-ze84S

Fig. 1 - Block diagram of the CA3136 in a typical circuit application.

Fig. 2 - Typical detector output linearity.

________________________________________________________________

~3

CA3136E
AFT DEFEAT

~

r- - _.- - - ---- -- --- - _______ T i4
AFT PHASE DETECTOR

---- ----

An

AFT OUTPUT

----V11

V16-S00 mV p-p@3.5SMHz

Tint Control"
Range

£>11

V16-S00 mV P·P.
Term.l = 1.2 VDC

Ratio G·Y to R-Y

V7IV6

V16=400 mV Pop.

Ratio B·Y to R-Y

VSIV6

Demodulated Chroma
Output R-Y

Ve

Color Difference Output
(Bandwidth at 3 dB)

V6

G·Y

V7

B·Y

Vs

"Flesh Detector"

3S

%

V3=40 mV Pop

108

120

132

%

VI6=400mVp-p.
V3=40mVp-p

350

550

-

mV p.p

-

900

-

kHz

V p_p

V16=400 mV Pop.
V3 = 300 mVp-p

Amplitude

1.6

2.65

-

Reference
Set-Up

0

-

Degrees

275

-

%

-

0

-

Degrees

100

ro

-

50

-

n

-

3

ri

2.5

-

kn

11

Small-Signal Input
Resistance:
Term.3
Terms.9&10

-

-

VII

Small-Signal Output
Resistance (Terms.6.7.8)

2.2
0.7

-

11

Same Set-up except SI open

VII

"Flesh Detector":
Phase

1.5
0.42

Set-Up:
Term.2 = 1.6 V
Term.l = 11.2 V
Term.16=400 mV Pop
@Oo Reference Angle
Term.3= 40mV Pop
@ 100 Reference Angle
SI Closed (Term.15 at GND)

Reference:

Amplitude

Degrees

33

V3=40 mV Pop

Maximum Color Difference Outputs:
R-Y

"Flesh Detector":
Phase

-80

2S

Same Set-up except
Term.3 at 1900 angle

%

" Phase angle of term. 11 referenced to term. 16 phase angle .
.. Phase angle of term. 11 with term. 1 = 1.2 V minus phase angle of term. 11 with term. 1 = 11.2 V.

____________________________________________________________________

~7

CA3137E

RF
BYPASS

CARRIER
flllEf{

14 ___

iI~"
'--+--->VV\rl-~'\I,~I ,~ ~
CARRIERU

I~'I

~I

i

I

I

I
TINT

CONTROL

1/

~F~

I

-:_t;r'-----3--

---

:'FL2 y".
'14

I:

li 4

301<

"FLESH CQARECTOR"
DISABLE

J

"

f6

y

~06

RI1

----,

Z2

F9
RIB

~V2~'0~-2-'0-_t-~---

r;.~-,~-~~+-------+--~--t-~O"- i ~.~;~ "
~

'1-c-'-,

r,

.o0

0l

l

J,,, l

o~

21

I.'.;.V:.'.·.I ~
L:.JL00
~~

J

"

'"

3.BK

~

01"-l

,to

3.8K

'"

'00

ALL RESISTANCE VALUES ARE IN OHMS
F DENOTES FOLLOWER TYPE

..,

~Q15
It..

057'1

.., I

'""

",0

",I

900

'"

10

I PHASE
SHIFT

NETWORK

Fig.4 - CA3137E Schematic diagram.

~8

____________

~

______________________________________________________

CA3137E

-------------~------------------~ -28Z9R
92C~

Fig.4 - CA3137E Schematic diagram.

____________________________________________________________________

~9

CA3139E, CA3139Q

TV Automatic Fine Tuning
Circuit
With I ntercarrier Mixer/Amplifier
For Color and Monochrome Receivers

Features:
- Cascode-type high-gain amplifier (l5-mV input for rated
output)
- AFT differential peak detector
- Differential amplifier
- Bi polar outputs
- Fiv&-stage intercarrier mixer!
amplifier
- Internal voltage regulator
- For use in either color or
monochrome receivers
The RCA-CA3139 is a monolithic TV Automatic Fine Tuning (AFT) circuit that provides an AFT voltage and an amplified
4_5-MHz intercarrier sound signal. When connected to an output of an I F amplifier the
CA3139 provides the~ignal processing (amplification arid detection) necessary to generate
the AFT correction signals required by the
TV tuner_ It also mixes the video and sound
IF carriers and amplifies the resultant
4_5-MHz intercarrier sound signal. This sound
output may then be connected to an FM
detector such as the RCA-CA3134 "TV
Sound IF and Audio Output Subsystem",or
the RCA-CA3065 "FM Detector and Audio
Driver",
The AFT portion of the CA3139 is similar to
the RCA-CA3064 AFT circuit with the
following exceptions: (a) the AFT filter
capacitors are external and user selectable,
allowing the detector to operate as a peak
detector and resulting in a higher effective
gain for the TV signal; (b) the detector bias
resistor is external and user selectable, allowing the gain of the AFT and intercarrier
signals to be adjusted; (c) the dynamic resistance of the shunt regulator has been
decreased.
The CA3139 is supplied in a 14-lead dual-inline plastic package (CA3139E) or a 14-lead
plastic package with quad-formed leads
(CA3139Q),
MAXIMUM RATINGS,
Absolute-Maximum Values:
DEVICE DISSIPATION:
Up to T A = 25°C. . . . . . . . . . . . . . . . .. 630 mW
Above T A = 2S°C. .... derate linearly 6.7 mW/oC
AMBIENT TEMPERATURE:

Fig. 1 - Block diagram and typical application of CA3139.

MAXIMUM VOLTAGE RATINGS at TA = 25°C
The following chart gives the range of voltages which can be applied
to the terminals listed vertically with respect to the terminals listed
horizontally. For example, the voltage range between vertical terminal
3 and horizontal terminal 12 is +8 to -1.5 volts.
Terminal
No.

(1.59 mm ± 0.79 mml
from case for 10 s max. . . . . . . . . . . . .. 265 0 C

3

4-

5

1,2'
3

45

6

7"

8

9

10

11

12

13

14

liN,
lOUT
mA

NO INTERNAL CONNECTION
+10 +9
+8
-0 -1.5 -1.5
+0
-2

+0
+8
+8
+8
+8
+8
+8
+8
-10 -1.5 -1.5 -1.5 -1.5 -1.5 -1.5 -1.5

10

+0
-3

+0
+0
-11 -3

+0
-3

50

+0

+0

+2
-14 -5

+1
-5

+2

+2

+2

+1

-5

-5

-5

-8

+1
-8

+0
+2
-14 -2

+0
-2

+2
-2

+1

+1
-3

+0

+0

-3

-10 -10

-5
6

+0

-3

+0
-3

+0

-3

+0
+0
--11 -11

+15 +13 +15 +13 +13 +10 +10
-0 -0 -0 -0 -0 -0 -0

7·

+1
-5

2
50

+1
-5

+0
+0
-14 -14

2

9

+10 +8
-2 -2

+8
-2

+0
+0
-10 -10

10

10

+1
-5

+5
-5

+1
+1
-10 -10

2

11

+5
-5

1

+5
-5

8

*

12

*

2

*

2

+14
-14

2

*
*

13
14
•

2
Termmal number 7 may be connected to any

positive voltage source greater than the internal
zener regulating voltage through a suitable
dropping resistor - provided the dissipation
rating is not exceeded.

Operating. . . . . . . . . . . . . . . . .. -40 to +8SoC
Storage ............... , .... -65 to +150o C
LEAD TEMPERATURE lOuring Solderingl:
At distance 1/16" ±)f32"

1,2'

MAXIMUM
CURRENT RATINGS

•

This terminal should be connected to the most
negative potential of the complete circuit.

•

Voltages are not normally applied
these terminals. Voltages appearing
these terminals will be safe if the
limits between all other terminals
exceeded.

between
between
specified
are not

It is recommended that unused terminals 1 and
2 be grounded to act as shields.

390 ________________________________________________________________

CA3139E, CA3139Q
ELECTRICAL CHARACTERISTICS at T A = 250 C, V+ = 28 V (Unless Otherwise Specified)

CIRCUIT DESCRIPTION

See Test Circuit, Fig. 2
UNITS

The CA3139 consists of five functional cir·
cuits as shown in the block diagram, Fig. 1
(see Fig. 5 for schematic diagram).

mA

1) Cascade Amplifier - Consists of emitter·
follower Q1, common·emitter amplifier
Q2, and common·base amplifier Q3.

CHARACTERISTIC

LIMITS

TEST CONDITIONS

Min.

Max.

NO SIGNAL INPUT
Supply Current, 1+
Low Voltage at Term. 7'

V+

15

20

11

14.5

V

12

14.5

V

4.5

10

V

6

B.5

V

-0.8

+O.B

V

1.4

2.6

V

MHz
MHz
MHz
MHz

2.2
1.2
9.6
9.1

4.7
4.4
13.8
12.1

V

MHz
MHz
MHz
MHz

9.1
9.6
1.2
2.2

12.1
13.8
4.4
4.7

50

200

= 20.B V

Shunt Reg. Voltage
Quiescent Voltage at Term. 3
Quiescent Voltage 2 at Terms.
13 and 14

Term. 13 connected to Term. 14

Quiescent Difference Voltage,
Terms. 13to 14
Quiescent Voltage at Term. 6
SIGNAL INPUT

= 15 mVRMS

(Unless Otherwise Specified), Note 3

= 44.65
= 45.69
= 45.B1
= 46.85
f = 44.65
f = 45.69
f = 45.B1
f = 46.85

f
f
f
f

Correction Voltage at
Term. 13

Correction Voltage at
Term. 14

Two·Tone Input
f1 = 45.75 MHz at 15 mV
f2 = 41.25 MHz at 5 mV

4.5 MHz Output

V

mVRMS

NOTES: 1. 17 = 12 mA maximum at V7 = 11 V.
2. V13

= 0.55

Vz ± 0.7 V

3. Resistor from term. 6 to term. 7 = 9.09 KS2. Crossover steepens and "bow tie"
width increases when resistor is decreased in value. Total peak swing decreases
slightly.
y'

NOTES:

'0 UMl0 Kfl IlOlrtlOn

R"~tor~t DC
Yah",.. Prot. T'P Wn.n M"'"9
DC "'--'IMnU.

2. Typic..! No·SlgNl DC Paltnhall Ar,

Sho_.
3.80 .... R.prnent TfS'I Po,nu

L1

RCA P.N 122206

L2' RCAPN.'4'33
4\l.i Turm _Z2 Wlr., 0.0 ... 0.25" (TypJ

RCA P.N. 140507
3'h Turn. (Center hppld) j/2O Wlfl,
0.0. -036" (Typ.)
(Unloadedl .. 140 IMln.!

a !UnloMMdl .. 100 (Min.)

a

f .. 4'.2SMH,
Indueuncl" O.lBj.lh (Typ.)

ln6uctanoJ .. O.lB",h (Typ.)

Fig. 2 - Test circuir.

I- 45.75 MHz

2) Bias Circuit - Consists of Q4 and resistors
R 1, R4, R5, and an external resistor (user
selectable) connected to the voltage regu·
lator, terminal 7. The nominal value of
the external resistor is 9.1 kn. Reduced
values will raise the gain of the cascade
amplifier chain, and higher values will
reduce the gain. If the gain is increased,
the AFT "Bow Tie" width will increase
and the crossover slope will increase
(become steeper). The input transistor
Q1 is internally biased, so AC coupling
is normally used to the input terminal 5.
3) Intercarrier Mixer/Amplifier - The out·
put of the cascade amplifier at terminal 9
is also internally connected to the inter·
carrier mixer/amplifier chain consisting
of transistors Q13 through Q17 and as·
sociated components. The video I F carrier
at 45.75·MHz and the FM sound IF
carrier at 41.25·MHz are down·converted
to a 4.5·MHz FM signal by Q14. A low'pass
filter removes the carriers and upper can·
version signal components. The 4.5·MHz
FM signal is further amplified and filtered
by Q16 and C3. The FM sound output
signal is at terminal 3. The gain with
respect to a 5·mV sound carrier (tested
with a 15·mV video carrier) input signal
at terminal 5 is 10 to 40 when the resistor
is connected between terminals 6 and 7
is 9.09 kn.
4) AFT Detector and DC Amplifier - Can·
sists of Q6 through Q12 and related com·
ponents. The detector inputs at terminals
8 and 10 are connected to the external
discriminator transformer and
biased
through the transformer at terminal·6
potential. The total current through tran·
sistors Q7 and Q8 is held constant by the
current·mirror transistors Q10, Q11, and
Q12. External filter capacitors connected
to terminals 11 and 12 assure that peak
detection is accomplished. Tho AFT out·
put voltages are shown in the Electrical
Characteristics chart, and a graphical repre·
sentation is shown in Fig. 4.
5) Voltage Regulator - An active shunt
regulator, consisting of 01, 02, Zl, Z2,
and Q5, is included to reduce the dynamic
resistance.

_____________________________________________________________________ 391

CA3139E, CA3139Q

SUBSTRATE
IF'INPUT

INPUT FREQUENCY DEVIATION-MHz
92<:5-27127

Fig. 3 - Terminal assignment.
Fig. 4 - Dynamic control-voltage characteristics.

CA3139

J
92C,.-27129

Fig. 5 - Schematic diagram of CA3139.

Fig. 1 - Temp/ate of CA31390 circuit board
(actual size. bottom view).

~2

Fig. 6 - Typical tuner connection.

Fig. 8 - CA37390 circuit board with

components.

_____________________________________________________________

CA3143E

TV Luminance Processor
The CA3143E is a monolithic silicon integrated circuit that performs the luminance
processing functions of amplification; contrast, brightness and peaking control; blanking; and black-level clamping_
This device, when used in conjunction with

Features:

the CA31260 chroma processor and the
CA3137E chroma demodulator, will provide a luminance/chrominance system having excellent tracking of controls. The
CA3143E is supplied in a 14-lead dualin-line plastic package.

•
•

Black-level clamping
Linear de controls for brightness,
contrast, and peaking

•
•

Horizontal and vertical blanking
Operates with standard or tapped delay line

CIRCUIT DESCRIPTION

t 30 \I

\/IDEO INPUT

POSITIVE

HORIZONTAL
PULSE

POSITIVE

vERTICAL
PULSE

'"
50kn~----'

Fig. 1 - Functional block diagram.

NOTE: ATTENUATION AT 50 kHl MUST
BE AT LEAST 66dB GREATER THAN
THE ATTENUATION AT I MHz

Fig.2 - Test circuit.

Fig. 1 is a block diagram of the CA3143E
indicating the internal functions as well as
external circuitry and signals. The video
input signal with positive-going sync is ap·
plied to the input of the tapped delay line.
Signals from fixed taps of the delay line
are applied to terminals 1, 2 and 3 of the
CA3143E. In referring to Fig.4, the signal
from the delay line tap A is applied to the
video input at terminal 1. The signals from
taps Band C are summed where VA + VB
~ Vsum . The signal (V sum ) is then applied
to the parallel connection of the peaking
input terminals, 2 and 3. The videO input
signal is applied to a non-inverting input of
the peaking amplifier while the peaking input
signal (V sum ) is applied to an inverting input of the peaking amplifier.
Low-frequency video components are unattenuated, while high-frequency components are attenuated as a function of the
delay-line tap points. The peaking amplifier
is a differential amplifier, so that the output
is proportional to VI minus V sum' At low
frequencies, the signal at terminals 2 and
3 is unattenuated, and the peaking amplifier produces no output at these frequencies. However, at high frequencies the signal
at terminals 2 and 3 is attenuated thus, the
peaking amplifier output consists of high-frequency video. The peaking control setting
determines the amplitude of the peaking signal which is then fed to the video amplifier,
where it is added to the video input signal
and amplified. The setting of the peaking
control does not substantially affect the dc
quiescent voltage at terminal 4.
The low-impedance video amplifier output
is at terminal 4. The signal is fed through an
external coupling capacitor to terminal 6, the
black-level clamp input. The action of the
black-level clamp is such that it clamps to
the black level rather than to the sync level.
Refer to the circuit diagram in Fig.3. Consider the situation where no signal is applied
to terminal 12. Terminal 6 is biased through
diode 02. The signal at terminal 6 will
clamp its most negative excursion (sync
pulse) to the anode voltage of 02. However, if a positive pulse is applied to terminal 12 during the sync interval, the anode
of 02 is forced to ground due to saturation
of 017. The clamp is thus disabled, and
terminal 6 will clamp to the next lower
signal level, the black level.

_________________________________________________________________ 393

CA3143E

,r----------------.,0

7.11(

I
I

I

I

IL

•• 7
•••
500n
L-+-__
__________
"
___________
_
~

SHUNT REGULATOR

_+----------------~A2N~0~.='A~S-----H
~

VIDEO
AMPLIFIER

'IBLANt4---~

loS V

"'tn

nov
12.3 VOLTS

REGULATOR
VOLTAGE
92CM-28108

Fig. 1 - Functional block diagram.

10 Kn

NOTE

ATTENUATION AT SO kHI MUST
BE AT LEAST 66 dB GREATER THAN
THE ATTENUATION AT 1101Hz

92CL-281091'l1

Fig. 2- Test circuit.

_________________________________________________________

~7

CA3144G
PEAKING
CONTROL

"

i-viOEoINPUrAMP- -~PEAKINGAMP8CONTROL - - - - - - - - []ViOEOAMP - - - :

~~~:~I
I
I

:
I
t"R'
I

I~2
;... ~

I

RB

I

R6

2.2K

IN~T I

"VT
:

PEAkiNG

INPUT

Q)

I t)"

Rll

R23

51<

51<

:.~I~

rt

:~~

QZ5

I
I

RZS

5K

.oon

:~~
..

n,

I
II

08

t-~~I90/)r,n+--

E

~~"K

R34
31<

Q26

3580.0
R27

I r.t-7
HI ! t-- R30

51<

~

II<

t--c

RII
7.1.

I

R29

~23 R26 Q~
R25

R3

47K

06

I ,-\---;-:;1---1.

,K

~

08

J

II l"-

I

,~

r-

'I

I!-

I
I

O'

475.0

o~

t-LYoZI

RIO

:

R9

I

I- - - - PEAKING I ~h

~

04

I
I

R7

7.35K

'OBon II
f-l.

l J
.-Y03

I

lOKI

I

*

I~~on

N~OI
I

F

~

~27

09 [,
R32

""

.oon

2504

~________~~~__~~~~~~~~~~.
-

-,

....J.

l

~

~~L-i-'Jo~H!.3--~~R-?-tK--------t--------t:-----------+L-_-_-_--------+r----tr'-r-.: RI3
I 1:;~
~g~~~~~T
I
+--+~L+-_.-_!
3.41<

034

I
I

~\OK

: r"
I
I

I
I
I

I

Q3~f-<......,~-+_'_3_

I
R43

;

R42

970.0

:

R41

!Soon

6K

~H~~A\ REGULATOR

•

r; "'4

03~ R,".:'

~~-+---_ _ _ _-T,__________~l__·~L

L _ _ _ _ _ _ _ _ _ _ _ _ _ L _________________ •
92CL-28106RI

Fig. 3 - Schematic diagram

CIRCUIT DESCRIPTION
Fig. 1 is a block diagram of the CA3144G
indicating the internal functions as well as
external circuitry and signals. The video
input signal with negative·going sync is ap·
plied to the input of the tapped delay line.
Signals from fixed taps of the delay line are
applied to terminals 1, 2, and 3 of the CA·
CA3144G
TERMINALS

92CS-28HO

Fig. 4- Tapped delay line.

~8

3144G. In referring to Fig. 4, the signal
from the delay line tap A is applied to the
video input at terminal 1. The signals from
taps Band C are summed where V A + VB =
Vsum . The signal (V sum ) is then applied to
the parallel connection of the peaking input
terminals, 2 and 3. The video input signal is
applied to a non·inverting input of the
peaking amplifier while the peaking input
signal (V sum ) is applied to an inverting input
of the peaking amplifier.
Low·frequency video components are un·
attenuated, while high·frequency components
are attenuated as a function of the delay·line
tap points. The peaking amplifier is a dif·
ferential amplifier, so that the output is pro·
portional to V1 minus Vsum . At low fre·
quencies, the signal at terminals 2 and 3 is
unattenuated, and the peaking amplifier pro·
duces no output at these frequencies. How·
ever, at high frequencies the signal at ter·

________________________________~-----------------------------

CA3144G
CLAMP INHIBIT INPUT

--------------1
1
1

.3.

01

I.~K

r- - - - - I

~----+----.-,

BUFFER AMP

aR~'t'1"NNK1~i' a

I

.47
2.4K

1

1
1
012

1

I

I

:.- ______ -L _

CLAMP

I

_ _ _ _ ..J

.46

2.4K

J

I
1

r---------1 Q3.

I
I
1

.44
9.6K

Oil

M-

------------------~--------~
~ SUBSTRATE

13 SHUNT REGULATOR
a BIAS
ALL. RESISTANCES ARE INOHMS
92CL.-28L06

Fig. 3- Schematic diagram

minals 2 and 3 is attenuated thus, the peaking
amplifier output consists of high-frequency
video. The peaking control setting determines
the amplitude of the peaking signal which is
then fed to the video amplifier, where it is
added to the video input signal and amplified.
The setting of the peaking control does not
substantially affect the dc quiescent voltage
at terminal 4.
The low-impedance video amplifier output
is at terminal 4. The signal is fed through an
external coupling capacitor to terminal 6,
the black-level clamp input. The action of
the black-level clamp is such that it clamps
to the black level rather than to the sync
level. Refer to the circuit diagram in Fig. 1.
Consider the situation where no signal is
applied to terminal 12. Terminal6 is biased
through diode 03. The signal at terminal 6
will clamp its most negative excursion (sync
pulse) to the anode voltage of 03. However,
if a positive pulse is applied to terminal 12

during the sync interval, the anode of 03 is
forced to ground due to saturation of 013.
The clamp is thus disabled, and terminal 6
will clamp to the next lower signal level, the
black level.
The clamped video signal at terminal 6 is
amplified and inverted at terminal 7. Blanking
is accomplished by applying horizontal and
vertical sync pulses to terminal 8. The pulses
turn ON p-n-p transistor 018 which shorts
the base of transistor 020 to the terminal 13
supply voltage. The brightness control function is accomplished by varying the voltage
on terminal 9. The gain of the inverter stage
remains constant, but the dc reference voltage
follows the terminal 8 voltage. The contrast
control function is accomplished by varying
the voltage of terminal 10. Increasing the
voltage on terminal 10 lowers the· gain of the
video amplifier. This reduction in gain does
not substantially affect the dc quiescent
voltage at terminal 4.

____________________________________________________________________ 399

CA3151G

Preliminary Data

Single Chip TV Chroma
ProcessorIDemodulator

ELECTRICAL CHARACTERISTICS at T A

TYPICAL
VALUE

UNITS

Supply Current, IT

42

mA

R- Y, G-Y, B-Y, Outputs, VSVg.VlO

5.3

Oscillator Reference
Inputs, V 11 ,V 12

3.7

Chroma Demodulator Input, V 13

2.9

Chroma Processor
Input, Vl

2.2

CHARACTERISTIC

"G" Suffix Type - Hermetic Gold-CHIP in
STATIC (See Fig. 11
Dual-In-Line Plastic Package

System Features:
• All chroma processing and demodulating
circuitry on a single chip in a 24-lead
plastic package
• Phase-locked subcarrier regeneration
utilizing sample-and-hold techniques
• Supplementary ACC with overload detector
to prevent over saturation of the picture tube
• Linear dc controls for chroma gain and tint
• Dynamic "flesh correction" - corrects
purple and green flesh colors without
affecting primary colors
• Balanced chroma demodulators with low
output impedance for direct coupling

S;z

sa Chroma In

Minimum Oscillator
Pull-In Range*,V12

2 1 1

Oscillator Level, V12

2 1 1

Minimum Gain
Control, V 13

• Low system dissipation-nominal 0_5 IN

The RCA-CA3151G is a monolithic silicon
integrated circuit that performs the complete chroma processor and demodulating
functions for color TV. The single chip contains all the features of the CA3126 chroma
processor and the CA3137 chroma demodulator.

V17

I

Vdc

Hz

0.6

Vp _p

1

273mV p _p

I---

1 1 1

11.6 V

20

6V

50

I---

200 Percent
ACC.V13

1 1 1

546 mV p . p

100

20 Percent
ACC, V13

1 1 1

54.6 Vp. p

100

Overload De·
tector (OLD),
V13

4 mV p •p

1 1 1 54.6
mV p_p

7V

mV p. p

% of
100%
ACC
Value

20
mV p _p

30 mV p _p

400

1 1 1

1 1 2546mV p _p

1
Vp _p

R-Y Sensitivity,
VlO Eg= 282
mV p_p ' 3.53 MHz

1 2 1

R-Y Ratio B-Y/R-Y.
V8**

1 2 1

G-Y Ratio G-Y/R-Y,
V9**

Values:

±300

1 1 1

Minimum Unkill
Output, V13

MAXiMUM RATINGS,Absolute-Maximum

1.5 V
0.8
273 mV p _p

0

120
%

1 2 1

33

1 2 1

3

Max. R-Y
Output, VlO

13.2 V

Ef 2Vp -p'
3. 3 MHz

.825 mW

Derate81.i;:~jo"~

Minimum Tint
Control Range,
1{l13

AMBIENT TEMPERATURE RANGE:

Operating. . . . . . . -40 to +8S oC
Storage . . . . . . . -65 to +150·C
LEAD TEMPERATURE (DuringSolderingl:
At distance 1/16 ± 1/32 inch
(1.59 ± 0.79 mml from case
for 10 seconds max.. . . . . . +26S Q C

V4

50 Percent Gain
Control, V13

Maximum Kill
Output, V13

The CA3151G is supplied in the hermetic
Gold-CHIP 24-lead dual-in-line plastic package (G suffix). The transistor chips used in
the hermetic Gold-CH IP plastic packages
are of the sealed -junction type designed to
provide protection against the deteriorating
effects of humidity and other surface contaminants without the need for a hermetic
package enclosure. The semiconductor junctions are sealed by utilizing a silicon nitride
passivation layer. A multi-layered, highly
corrosion-resistant, terminal-connection system of unique design is employed.

.

Burst In

1.5V

100 Percent ACC, V13 1 1 1

• Requires few external components

Above T A = 55 C

S1

DYNAMIC (See Fig. 2)

• Internal rf filtering

DC SUPPLY VOLTAGE:
Between Terms. 18 and 7
DEVICE DISSIPATION:
Up toT A = 55·~

=2SoC. V+· 11.6 V

TEST CONDITIONS

•

*.

Vp_p

o V to
1 1 1

..

273 mV p_p

..

11.6 V

80

Degrees

Tune C 2 to 3,579,845 Hz WIth Sl In pOSItIon 2. Put Sl In pOSllJon 1, and check for pull In. Repeat for
frequency tuned to 3,579.245 Hz. For other tests, frequency tuned to 3,579,545 ± 10 Hz.
All input levels up to 2 V pop'

400 ____________________________________________________________________

CA3151G
20
10

+0
j

CA3151G

-10
-20

VCHROMA AT Pl3 ~ 400 mVp_p
NOTE

TINT CONTROL ADJUSTED

SO THAT WITH A +1
SIGNAL INTO TERM. I,
THE OSCILLATOR AT TERM
12 AND THE CHROMA AT
TERM. 13 ARE IN PHASE

+II,SV

10'

Fig. 2 - "Flesh" correction of oscillator phase angle
as a function of chroma input phase angle.

TERMINAL DIAGRAM

5~~,:90P~!, ~
XTAl
3579545 MHz
ON
ALL RESISTANCE VALUES ARE IN OHMS

TINT

CAPACITANCE VALUES ARE IN MICROFARADS

100 pF

UNLESS OTHERWISE INDICATED

CONTROL

OFF

":1-

FLESH

\ _

75 pF

62 pF

(.;t-mOMA INPUT

I

SAT CONTROL

4

24 HORrz, KEY PULSE INPUT

OVERLOAD OET
AND KILLER FILTER

...L

-=-

PROCESSOR SECTION 6
CHROMA OUTPUT

a

OVERLOAD

GROUND 7

DISABLE

17 TINT CONTROL

Fig. 1 - Functional diagram, static test circuit, and typical application circuit.

16 CARRIER FILTER

15 "FLESH CORRECTOR"
CARRIER OUTPUT

14 "FLESH CORRECTOR" AND
OVERLOAD DETECTOR DISABLE

13 DEMODULATOR CHROMA
INPUT
TOP VIEW

Vee
+(1,6

C2

IK

~
I

XTAL

3,579545 MHz c:::J

12 ,

001

--= 2,23.us~ r-635JLS

-~

~ 3 579545 MHz ~JVCHROMA
-T -

100 pF

BU,
----i

82 pF

:'-4,27/ls

VBURST .

~VPEAK(MINI

-

'"

f-

5!,s CENTERED
ON BURST

KEY PULSE

2.2 K

PULSE

52]2

o~

270pF

51<
9.45 V

ALL RESISTANCE VALUES ARE IN OHMS
92CL-29236

Fig. 3 - Dynamic test circuit.

________________________________________________________________________ 401

CA3153G
System Features:

Television Video I F System

•

UG" Suffix Type -- Hermetic GoldCHIP in Dual-In-Line Plastic Package
The RCA·CA3l53G is a monolithic silion
integrated circuit designed to perform if
amplification, video detection, and video·
amplifier functions in color and monochrome
TV receivers. The signal·to·noise performance
has been improved compared to the RCA·
CA306S*. The AGC performance has also
been improved through the use of a sample
and hold keyed system. The RCA-CA3l53G
is designed to interface with the RCA·
CA3l39# Automatic Fine Tuning (aft) cir·
cuit, and intercarrier amplifier.

The CA3l53G is supplied in the hermetic
Gold·CHIP l6·lead dual-in~line plastic pack·
age (G suffix). The transistor chips used in
the hermetic Gold·CH IP plastic packages
are of the sealed·junction type designed toprovide protection against the deteriorating
effects of humidity and other surface con·
taminants without the need for a hermetic
package enclosure. The semiconductor junctions are sealed by utilizing a silicon nitride
passivation layer. A multi·layered, highly
corrosion-resistant, terminal·connection sys·
tem of unique design is employed.

•
•
•
•
•
•
•
•
•

Improved agc
Fast response
Sample and hold keyed
High gain wideband IF amplifiers
Delayed age output for tuner
Gain reduction with excellent stability
Linear video detector
Video amplifier
Low noise
Internlif shunt regulator
for color or monochrome
Gold-chip metalization

TERMINAL DIAGRAM
KEY PULSE INPUT

•

The CA3068 is described in RCA data bulletin
File No. 467.

#

The CA3139 is described in RCA data bulletin
File No. 905.

I

AGC FILTER 2

I
CLAMP CAPACITOR 5
AI OUTPUT. A2 INPUT 6
AGC DELAY 7

DET.BIAS
+VSI SHUNT REG.

II

A~

INPUT 8 DET.

TUNER AGe
9 A2 OUTPUT
'ZCS~~IO'2

FROM
TUNER

21< TYp.
TUNER AGC
NO SIO. +U5 Y TYP.
HIGH SIG.

+I

Y TYP.

16

I(

TYP.

92CL-31066

< - - -....-<+15 V

Fig. 7 - Function.1 block diagram of the IF amplifier·svstem of CA37S3G with typical peripheral circuitry.

~2

________________________

~

____________________________________

CA3153G
MAXIMUM RATI NGS, Absolute-Maximum Values_'
DC SUPPLY VOLTAGE:
Between Terms. 15 and 4 . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . 16 V
Between 470 n connected to.Term. 12 and 4 . . . . . . . . . . . . . . . . . . . . . . . . . . , .35 V
DC SUPPLY CURRENT:
At Term. 15 . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
At Term. 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , .. , .. , .30 mA
DEVICE DISSIPATION:
Up to T A ~ +55' C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , .. , ......... 750 mW
Above TA ~ +55' C . . . . . . . . . . . . . . . . . . . . . . . . . . . . Derate linearly at 7.9 mwr C
AMBIENT TEMPERATURE RANGE:
Operating ..... , ............................. ,............... -40 to +85' C
Storage ....... , ............................................. -65 to +150' C
LEAD TEMPERATURE (During Soldering):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 seconds max ..... +265' C

ELECTRICAL CHARACTERISTICS at T A ~ 25°C
CHARACTERISTIC
Operating Supply
Voltage, V15

LIMITS
Min.
Max.

TEST CONDITIONS
See Note 1

12

14.2

V

3

15

mA

10.9

13

V

Supply Current, 115
Shunt Regulator
Voltage, V12
Shunt Regulator
Current, 112

UNITS

V12

~

10.5 V
6

20

mA

Tuner AGC High
Voltage, V 10

18.5

21

V

Tuner AGC Low
Voltage, V 10

0.3

1.3

V

AGC Current, 12

Non·Keyed

80

500

pA

AGC Current (Peak), 12

Keyed Source Current

0.7

3

rnA

AGC Current (Peak), 12

Keyed Sink Current

150

680

pA

Horizontal Key Input

Through 100 kn
connected to Term. 1

25

35

V

Video Output High
Voltage, V 16

At Zero Carrier
7

10

V

Video Output Low
Voltage, V 16

At 30 mV Input
0.9

2

V

Sensitivity Voltage, V 16

At 400 pV Input

Noise
Chroma

45.75 MHz, 10 mY;
42.17 MHz, 3 mV

0.9

5

V

-

12

mV(RMS)

0.7

1.6

V (RMS)

35

85

mV(RMS)

Distortion

50 kHz, 80% Modulated,
Sync TIP Equiv. 30
mV(RMS)

-

10

%

Delay Voltage

Through 15kn connected
to Term. 7. See note 2

0

V15

V

AFT Drive

Note 1: V15 MIN. should be at least 0.6 V above Terminal 12 potential. Lower voltage may cause some
"white" compression.
Note 2: Zero voltage corresponds to maximum delay at signal input

= 30

mV IRMS).

_______________________________________________________________________ 403

CA3153G

~-+--~--+-~--~----~------~--r-rr--------~---------A
R27
740

016
C2
19
pF

01

R28
690

R22
15K

R21
32K

R30
6K

700

R3
5K

Ril

500n

RI2 I
54KI

I
I
I
I

500

RI3
42K

R20
31K

RI9
4K

IF AMPLIFIER AND AGe OUTPUT SYSTEM

!01-0151
Q3,6,7,8, 12,13, AND 015 ARE EMITTER FOLLOWERS

SUBST

-=-

14
92Cl-31067

Fig. 2 - Schematic diagram for the CA31536.

AGC System (See Fig. 3)
The AGC system employs a sample·and·hold
system to allow a fast·acting agc and reduce
the effect of the vertical synchronizing signal
on the video output stage. An override path
is provided to allow a lower-gain agc system
when the key pulse is not locked to the sync
signal (for example, during channel selection).
The negative·going sync signal at the video
output, Terminal 16, is applied to transistor
041 through resistors R51 and R52 which

~4

act as current·limiting and filtering compo·
nents. The sync signal is inverted and ampli·
fied by transistor 041. The video portion of
the signal is cutoff by the saturation voltage
of 041. When the TV system is in synchroni·
zation, the positive sync pulse at the collector
of 041 is coincident with the key input at
Terminal I, Transistor 042 is turned off by
the key pulse. Capacitor C13 is charged by
the positive sync pulse through diode D9.
The amplitude of the potential at C13 is pro·
portional to the video-signal ampl itude. The
voltage is transfered through transistors 040,

___________________________________________________________

CA3153G
THIRD IF-AMPLIFIER STAGE,DETECTOR,
AND VIDEO-AMPLIFIER SYSTEMS
1016-0311
016,17,19,21,22,25,27,30, AND 03t ARE EMITTER FOLLOWERS

13

R36

R39
I 5K

2.9 K

R4'

'Z2

112 K

021

~7
95pF

~

leB

23pF R40

IK

"J

R34

1 ..

4K

{

C6

20
pF

~

"

R47
105

R42
100

F
09

R.4
IK

~

RSI

I

18pF

032

I

Q33

I

R4B
40

I
I
I
I
I
I
I

R52
75 K
CI2

15']

R54
10 K

--"

--~------------

DB

~

R5.
900

.. i J~~A-rJ

05

R38
100

Q~

I

026

R35
130

..y

IK
R50

r

O~

Z4

IPF
'R49

I
I

029
R44

K~

04

G

r:;

t-

I---------.J
IK

.1,,3

I

r--- -~

1,4 K

R41
11K

r--

R37
2K

R3I
270

Z3

025

R32
5K

R55
15 K

R46
75K

r

R33

~

I
R53
100

"

c
- { ! 6 gF

I
I

R45
16 K

R61

~~
041

6,1 K

I.

~
R60

"7'"~ rf
16 K

160

R59

pF

I.4K

~43

R63

I ~;~

OK

I

NOISE-GATE AND AGe SYSTEMS

1034 -

043 1

032,33,35, AND 036 ARE EMITTER FOLLOWERS
92CL -

~I06

r

J

Fig. 2 - Schematic diagram for the CA3153G.

038, 036, and 035 to resistor R57 to form
the charge current for the external agc filter
capacitor at Terminal 2.
A constant·current discharge path for the
capacitor at Terminal 2 is provided by cur·
rent mirror components 07 and 037 during
the key·pulse duration. Thus the external
agc filter capacitor is charged or discharged
during the key·pulse interval only by the dif·
ference in current between the charge· and
discharge currents. At the end of the key·
pulse duration, CI3 is discharged, and the

charge and discharge current paths at Ter·
minal 2 are turned off. Diode 08 provides a
lower·gain age path for turn·on during chan·
nel acquisition.
Noise-Gate System (See Fig. 3}
The circuit components, CII, R54, 032,
033, and 043 perform the function of a sta·
tistical system to reduce age gain during
"spike" noise. The noise gate turns on for
large amplitude fast signals and reduces the
age loop gain.

__________________________________________________________________ 405

CA3153G

VIDEO
OUTPUT

.JV

r-

I

I
I
I
I
I
I
I
I
I
I
I
I
I
I

TO OUTPUT

{IF

I

:~:~~!Nol
I

AGe OUTPUT

S~~:!~SI

I
I
I
I

I

I

101(

I

KEY

L ______ ~ _ _=_ ___r~~~ I
Q32.,33,35,ANO 036 ARE
EMITTER FOLLOWERS

--AGe--

I
I
__ --.J

FIL.TER

1I0K

'J2CY"I063

Fig. 3 - Noise·gateand AGC system of CA3153G (034 -+043).

+15

10

T~~~R

--,
I
I
I
I
I
I

RIO
440

I
I
I
I
I
I
I

I
I
I
I

Rtl

42<

I
L~

3.11<

___

02
~

______________________________ _
Q3,6,7,B,12,13,ANO QI5ARE EMITTER FOLLOWERS
92CL- 31064

Fig. 4 - IF amplifier and AGC output system of CA3153G (01-+015).

406 __________________________________________________________________

CA3153G
+VSI

1- -v:;--- -- ---- - f~~ -v~ -- 12-':~~':..-_ --- - - - ----~

m

I
I

n:

Z3

C2
1.91l F

I
I

I
I

'4
R64

I

,,'

031

IK

R~J I
100 1

I

I
I

I
IO~I~~~T
16

I

I
I
I

CII
7

I

"1
R48

40

R3I

~1~11
~

~;~

I
I
I

0'

270

~gg

R43

I
I
I

I

-=-

___ ~ __ =-_____________________________ J
11.2K

-="

016,17,19,21,22,25,27,30 AND 031 ARE EMITTER FOLLOWERS

92CL' 3106:1

Fig. 5 - Third IF-amplifier stage. detector, and video-amplifier systems of CA3153G (016 -+ 031 J.

__________________________________________________________________ 407

CA3159G

Preliminary Data

Horizontal Processor and AGC Detector
The CA3159G is a monolithic integrated circuit designed for use as a horizontal processor
and AGC detector in color or black-and-white
TV receivers. It performs the functions of
AGC, sync separation, and noise immunity,
and a 31.5 kHz oscillator is provided for use
with vertical-countdown circuits.

Features:

The CA3159G issupplied in a 16-lead dual-inline plastic package with a hermetic "GoldCHIP" (G suffixl. These chips are of the
sealed-junction type designed to provide protection against the deteriorating effects of
humidity and other surface contaminants
without the need for a hermetic package
enclosure.

• A GC voltage
• Separated sync
.31.5 kHz oscillator
• Gates AGC and sync for noise immunity

MAXIMUM RATINGS, Absolute-Maximum Values:
+30V
30mA

DC SUPPLY VOLTAGE
DC SUPPLY CURRENT
DEVICE DISSIPATION:
Up to T A = 55 0oC
Above T A = 55 C
AMBIENT TEMPERATURE RANGE:

. . . ..
750 mW
Derate linearly at 7.9 mW/C

. -40 to +85:C
. -65 to +150 C

Operating.
Storage

CA3159G
TERMINAL ASSIGNMENT

LEAD TEMPERATURE (DURING SOLDERING):

At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm)
from case for las max.

ELECTRICAL CHARACTERISTICS at T A = 25°C, V+
otherwise specified. (See Fig. 21

= 28 V, all

switches open unless

TERM_ TYPICAL
MEAS. VALUES

CHARACTERISTIC

TEST CONDITIONS

AGC Voltage

Sl, S9 closed

1

1.85

V

Noise Inverter 1

S2, S9 cI osed

1

0.7

V

Shift Threshold l

S2, S3 cI osed

1

20

V

Sync Level

Sl, S9 closed

4

18

V

Positive Pulse 2

S5 closed

7

25

V

Positive Sawtooth 3

S5, S6 closed

8

3

V

Sync Low

S3, S4 cI osed

6

1.5

V

16

20

mA
kHz

.---

Supply Current
Free-Running Freq.4

S7,S8,S9 closed

15

31.5

Duty Cycle

S7,S8,S9 closed

15

48

1. A = 3 V, B = 1.2 V, - 1 mA to term. I
2. C= 0.2 mA

UNITS

92CS-31036

%

3. C = 0.2 mA, D = 5 mA
4. Adjust LI, V+ = 20 V

9.!CM-)IO'5

Fig. 1 - Functiorial block diagram of CA3159G.

Fig. 2 - DC test circuit.

408 ____________________________________________________________________

CA3159G
6. which drives the outboard diode phase
detector. Second, the negative pulse cuts off
the current through Q36, which otherwise
holds Q35 in saturation, thus enabling a
current in R41 to turn Q34 on and thereby
shift the noise threshold voltage.
Terminal 7 receives a positive flyback pulse
thatsuppliesR41 with the signal to complete
the coincidence gate that alters the noise
threshold when sync and flyback pulses are
in phase. The buffered and clipped flyback
pulse also turns Q43 on, which, in conjunction with an external integrating ca·
pacitor, forms a sawtooth waveform. This
sawtooth (at flyback rate) is phase compared
with the sync pulse that was separated from
the video input.
The phase detector works against an internal
bias point brought out to terminal 10, and
the phase detector output applied to terminal
11 is slightly positive or negative relative to
terminal 10. This voltage differential with
terminal 10 determines the division of current

F;g. 3 - Schematic diagram of the CA3159G.

Circuit Description

The negative sync video input at terminal 3
is the detected video if. This video signal is
buffered and Vbe compensated by emitterfollowers Q28, Q27, and Q26. The buffered
video signal is applied between the base
of Q21 and a temperature·stable 2-V reference. Q21 is normally in saturation, and the
negative sync pulse imparts a positive swi ng
to the base of Q20. Q20 is used as a peak
rectifier driving a capacitor at terminal 1.
The voltage at terminal 1 is the AGC control
voltage that sets the if gain such that the sync
pulses drop to just below the 2 V level, driving
Q21 out of saturation.
The above description is for a normal video
signal; the presence of noise pulses more
negative than the sync tip level would lower
the gain to that level, thus disturbing the
picture. A gated noise·inversion threshold
is provide at the base of Q32 to compensate
for these noise pulses. The threshold is about
1.5 V during trace time, but is reduced to
about 1 V during coincidence of the sync
and flyback pulses. When the video signal
is more negative than the noise threshold,
Q32 conducts and pulls the base and emitter
of Q30 low. Without noise, Q23 conducts
0.5 mA with its collector at 7 V, which holds

Q22 in cutoff. Q29 has an emitter load
provided by an external 1 krl resistor and a
series capacitor: when its base is switched
low, its collector switches high. The resulting
flow of current in Q23 overrides the normal
negative-going pulse in the direct signal path
and holds Q21 in saturation.
The video input to terminal 3 also operates
the sync channel, beginning with Q31. Be·
cause Q32 is normally cut off, Q31 acts as an
amplifer with a moderate gain to its collector,
and a positive sync signal appears at terminal 4.
If the noise pulse is more negative than the
noise threshold at the base of Q32, the base of
Q30 is pulled down as discussed above. In
addition to operating the AGC noise inverter,
the Q30 current passes through Q25 to the
amplifier load resistor, R35, and cancels the
potentially positive pulse at that point.

between Q9 and Ql0, which are part of the
voltage controlled oscillator. The oscillator
consists of the current source Qll, differential amplifier Q12 and Q13, and differential amplifier Q9 and Ql0. The frequency
is determined primarily by a series LC circuit
connected between terminals 13 and 14
(terminals 12 and 13 have resistor loads to
the positive supply). If the entire oscillator
current passes through Ql0 to terminal 13,
the oscillator operates at the frequency at
which the phase shift in the LC circuit is
zero. If the current is sent through Q9 to
terminal 12, however, it must go through an
external capacitor between terminals 12 and
13 and then through the original LC circuit
and the circuit is tuned differently. Intermediate proportions of current division will
produce intermediate oscillator frequencies.
The oscillator current output from Q12
provides base drive for the 31.5 kHz output
at terminal 15.

The positive sync signal at terminal 4 is
coupled through an RC network to terminal
5 for sync separation. In essence, the network
permits Q38 to clamp the positive peaks, so
the most positive part of the signal is amplified by Q38 while the rest is beyond cutoff.
The separated sync, a negative pulse at the
collector of Q38, follows two paths. First,
the sync operates an output driver to terminal

____________________________________________________________________ 409

CA3163G

Preliminary Data

VHF IUHF Prescaler

Features:
• Broadband operation - 90 to 1000 MHz

The RCA-CA3163G* is an integrated-circuit
prescaler intended for use in TV frequency
synthesis tuning systems over an input frequency range of 90 to 1000 MHz_ It performs division by 256 in the uhf mode and
division by 64 in the vhf mode_
The mode of operation can be sel.ected by
means of the bandswitch and the separate
uhf and vhf input terminals provided. The
output is a complementary emitter-coupled
stage with controlled slew rate for harmonic suppression.
All input terminals should be ac coupled to
the appropriate input signal source. Because
of high sensitivity, unbuffered coupling from
the local oscillator is possible in most cases.
In the uhf mode, which is activated by
applying a high level to the bandswitch
input terminal, all eight divider stages are
operative, resulting in division by 256. In

the. vhf mode, activated by a low level at
the vhf input terminal, two divider stages
are bypassed, resulting in division by 64. As
a result, approximately the same range of
output frequencies are generated for both
the uhf and vhf TV bands. An internal
amplifier/multiplexer provides this control
while isolating both inputs and amplifying
the vhf signal. In addition, harmonic output
is reduced above 40 MHz by limiting output
signal rise and fall times and maintaining a
balanced load.

• High sensitivity
• Standard 5 V power supply
• Dual mode operation - VHF/UHF
• Complementary ECl outputs
• Independent VHF & UHF input terminals
• Hermetic Gold-CHI P construction

The CA3163G is supplied in the 14·lead
dual-in-line hermetic Gold-CHIP package.
The chips used are of the sealed-junction
type designed to provide protection against
the deteriorating effects of humidity and
other surface contaminants without the
need for a hermetic package enclosure.

* Formerly

TERMINAL DIAGRAM
v' ,
V'2

VHF INPUT

VHFliiPUT

2

BANDSWITCH
INPUT
OUTPUT

"

1mT1'lJT 0
Nle

RCA Developmental No.TA1053S.

v- ,

Nle
Nle
UHF INPUT

9~

6

8 V-2

7
TOP VIEW

92CS-30417

N/e· NO CONNECTION

MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY VOLTAGE
DC BANDSWITCH VOLTAGE
RMS INPUT VOLTAGE
DEVICE DISSIPATION:
UP TO T A = 70o~ .
ABOVE T A = 70 C .
AMBI ENT TEMPERATURE RANGE:
OPERATING.
STORAGE
LEAD TEMPERATURE lOURING SOLDERING):
AT DISTANCE 1116± 1132 INCH 11.59 ±0.79 MM)
FROM CASE FOR 10 SECONDS MAX.

5.5
20
0.5

V
V
V

600
7.5

mW
mWt"C

o to 70
-55 to +150

°c
°c

+265

°c

derate linearly at

v+

CRO

UHF
GEN.

L +O-'VVIr--1K'

*
'1-

,2;CI-50411

y+

va

'1-

* OF
INCLUDES CAPACITANCE
TEST PROaE

INCLUDES CAPACITANCE OFTEST PAOIIE

Fig. 1 - DC characteristics test circuit.

.aCI-304't

Fig. 2 - A C characteristics test circuit.

410 ___________________________________________________________________

CA3163G
ELECTRICAL CHARACTERISTICS At T A = 25°C. V+ = 5 VDC. V- = 0 VDC; see Figs. 1 & 2
ctiARACTERISTIC

liMITS

TEST CONDITIONS

UNITS

Min. Typ. Max.

90

Supply Current, 1+

Terms. (1+2). Fig. 1

30

60

UHF Bandswitch Input Voltage, VBH

High level

2.4

-

VHF Bandswitch Input Voltage, VBl

low level

-

-

O.B

V

UHF Bandswitch Input Current, IBH

-

-

0.5

mA

-

-

-1

mA

-

-

80

mVRMS

VH F Sensitivity level Input
Voltage, VIN(V)

=20 VDC, Fig. 1
VBl =0 VDC, Fig. 1
fiN = 450 to 950 MHz,
fOUT =fIN/256. Fig. 2
fl N =90 to 275 MHz,
fOUT =f I N/64, Fig. 2

-

-

40

mVRMS

Output Voltage, Va

Terms. 4 or 5, Fig. 2

1

-

Vp•p

70

-

ns

VH F Bandswitch Input Current, ISl
UHF Sensitivity level Input
Voltage, VIN(U)

Output Voltage Rise of Fall
Time, t"tf

VBH

0.65

-

mA
V

__________________________________________________________________ 411

Preliminary Data

CA3166E

Features:

Operational Amplifier Bandswitch

• Three independent functions - input operationaf
amplifier, AFT mode switch, and band-select switch
• Input operational amplifier has internal biasing
circuitry and high·impedance PMOS input transistors
• Internal diode clipper limiting at operational amplifie
. inputs and short·circuit protection at the outputs
• Static charge protection for both PMOS and CMOS
circuit components

BiMOS input operational amplifier, frequency bandselect switch, and AFT mode switch
For Frequency-Synthesizer Televi.sion Tuning Systems
The RCA·CA3166E incorporates bipolar,
PMOS, and CMOS processes on a single
monolithic chip to provide three functional
blocks for use in frequency·synthesizer type
TV tuners. Included are an input operational
amplifier, a band·select switch, and an AFT
mode switch.
.
The operational amplifier features internal
bias and phase compensation, high·impedance
PMOS input transistors, diode ·clipper input
limiting, output short·circuit protection, and
static charge protection. The operational
amplifier is used to amplify an error signal
that is proportional to the detected phase

difference between the desired channel fre·
quency and an internally generated reference
~i!inal.

The band·select switch has two logic inputs,
a control voltage input, and three outputs
(UHF, V·HF Low, VHF High) with a drive
capability of gO mA each, for controlling
the tuner varactor diodes.
The AFT mode switch is a CMOS trans·
mission gate with static charge protection
and an enable logic input for selecting the
"AFT ON" or "AFT DEFEAT" mode.
The CA3166E is supplied in the 14-lead
dual·in·line plastic package.

• AFT mode switch utilizes CMOS transmission gate and enable logic inputs control
AFT mode
• Logic·controlled band·select switch
• Three band·select-switch outputs, each with
gO·mA drive capability (typ.) at input
voltage up to 28 V dc
• High voltage·rating for wide dynamic
control range of error signals and switch
functions

MAXIMUM RATINGS, Absolute·Maximum Values:
DC SUPPLY·VOLTAGE RANGE, v+
DIFFERENTIAL INPUT VOLTAGE.
DC SUPPLY CURRENT 1+
BAND·SELECT SWITCH INPUT VOL TAGE RANGE. VBS
DEVICE DISSIPATION:
Up to +70ooC
Above +10 C.
AMBIENT TEMPERATURE RANGE:
Operating.
Storage
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1116 ± 1/32 inch (1.59 ± 0.19 mml from cas. for
10 seconds max.

Bandswitch Truth Table

+29.5 to +35 V
±1.5 V
20mA
o to +28 V
.

.

.

.

..

LOGIC
INPUTS

600mW

Derate linearly at 11.1 mW/oC

o to +10°C
-55 to +1 50°C

OUTPUTS

A

B

UHF

VHF
LOW

VHF
HIGH

0
0
1
1

0
1
0
1

0
0
0
1

0
1
0
0

0
0
1
0

+265°C

CA3166E TERMINAL ASSIGNMENT
OP. AMP. OUTPUT

INY. op, AMP. INPUT

I

LOGIC INPUT,

:5 NON·INV. OP. AMP. INPUT

AFT ENABLE

v+

AFT OUTPUT 3

II LOGIC -8" BANDSWfTCH INPUT
LOGIC -A- BANDSWITCH INPUT
6

~~~D~I~~TB~HNgUTPUT.

BANDS~~~C~IG~TPUT. 6

7

~~~D~ri'~~~~~UTPUT,

BAHDSWITCH OUTPUT
VHF LOW

'o-,.,..r---..;9 ~~~OSWITCH OUTPUT,

9 BANDSWITCH OUTPUT, UHF

7

B BANDSWITCH INPUT
TOP VIEW

Fig. 7 - CA3766E Block diagram.

412 __________________________________________________________________

CA3166E
Operational Amplifier (See Fig. 2)
Electrical Characteristics at TA = 25"C. V± = 32.5 V. VBS = 1S V. Terms 4 & 5 grounded
CHARACTERISTIC

TEST CONDITIONS

TYPICAL
UNITS
VALUES

Input Bias Voltage. V 13

113 = 4 rnA. Feedback = 1 MQ

2.5

VOC

Input Bias Voltage. V13

113 = 6 rnA. Feedback = 1 MQ

2.6

VOC

Input Bias Voltaae, V 14

114 = 4 rnA. Feedback = 1 MQ

3.3

VOC

Oiode Voltage
(term. 14toterm. 13)

114 = 4 mA, Term. 13 = Reference

O.S

VOC

Oiode Voltage
(term. 13toterm. 14)

113=4mA, Term. 14= Reference

0.8

VDC

Output Voltage
Low, VOL

114 = 4 mA, Resistance between
Terms. 1 and 12 = 10 kQ

0.2

VOC

Output Voltage
High, VOH

V 14 = 0 V,I 13 =4 mA, Resistance
between Terms. 1 and 12 = 10kn

28

VOC

Input Offset Voltage, VIO

V13=OV,Term.l connected to Term. 14

10

mV

Supply Current, 1+

V4 = 1 V, Feedback (Terms. 1 to 14) = 1 Mn

14

mA

OutpufSink Current, IOL

114 =4mA, VI =32.5V

Output Source Current, IOH 113 = 4 mA, VI = V14 = OV
V 13 = a V, Term. 1
connected to Term. 14

Input Bias
Current. II B (term. 14)
Common·Mode
Rejection Ration, CM R R
Power Supply Rejection
Ratio, PSRR
Open· Loop Voltage
Gain, AOL

25

mA

-15

mA

0.5

nA

65

dB

75

dB

80

dB

Band·Select Switch (See Fig. 3)
Electrical Characteristics at T A = 25°C. V+ = 32.5 V. VBS = 18 V. Terms. 4 & 5 grounded
Terms. 6. 7. 9 = 100 kn to ground
CHARACTERISTIC

TEST CONDITIONS

Logic Inputs "A" & "B"
Sink Current

100

Il A

-5

Il A

2

Il A

19= -90mA, VIO=Vl1 =2.4 V

0.6

V

Term. 9

19 = -60mA, VIO = V ll = 24 V

0.3

V

Term. 7

17 = -90 mAo V 10 = 0 V, VII = 24 V

0.6

V

Term. 7

17 = -60 mAo V 10 = 0 V. VII = 2.4 V

0.3

V

Logic Inputs "A" & "B"
Source Current

19 = -90 mA, V 10 = VII = 2.4 V

Output Leakage Current.
Terms. 6, 7. 9
Output Saturation Voltage:
Term. 9

~

TYPICAL
UNITS
VALUES

Term. 6

16= -90 mA, VIO=2.4 V, VII =OV

0.6

V

Term. 6

16=-60mA,VIO=24V,Vl1 =OV

0.3

V

________________________________________________________________ 413

CA3166E
AFT Mode Switch
Electrical Characteristics at TA = 25°C, V+ = 32.5 V, VBS = 18 V, Terms. 5,10,11 grounded
CHARACTERISTIC

TYPICAL
UNITS
VALUES

TEST CONDITIONS

Logic Input Current Low

V 2 = 0 V, RTERM. 3 = 10 MQ. V4 = 13.5 V

Logic Input Current High

-100

Il A

V2 = 2.4 V, RTERMS. 3 = lkQ, V4 ~ 1 V

2

IlA

Input Current

V2 =OV, RTERM. 3 = 10 MQ, V4 = 13.5 V

2

Il A

Output Leakage Current

V 2 =0.6V. V3=B V. V4=OV

1

nA

Output Si nk Current

V2 = 2.4 V, V3= 1.8, V4=OV

2

mA

Output Offset Voltage

V2=2.4V. V4 =3V

0.1

V

Output Voltage. "ON"

V2=2.4V, RTERM. 3= 1 kQ, V4= 1 V

0.8

V

Output Voltage, "ON"

V2 = 2.4 V, RTERM. 3 = 1 kQ, V4 = 13.5 V

10

V

VO,

CMRR

CONDITIONS (V)

TeST

VeM

Vss

35

0

18

V02

J3
29,5

V04

35

2010g N01 . V02)
200

v'

V03

=

Fig. 3 - Bandswitch test circuit.

VREF

PSRR '" 20109 (VOl' V03)

-15

550
AOL = -20109 (VOl - V04)

1000

10 k{l

-15 VDC

50n

Fig. 2 - Operational amplifier test circuit for CMRR, PSRR, and A OL "
Fig. 4 - Block diagram of a typical digital tuning system.

Turner Operation
Fig. 4 shows a typical digital TV tuning
system employing the CA3166E. This system
consists of a phase-locked loop (PLL) and a
programmable divider to generate a tuner
local-oscillator frequency that is an integral
multiple of a reference-oscillator frequency.
The output of the local oscillator is connected toa prescaler (CA3163) which divides
the frequency to values that can be processed by a programmable divider. The amount
of division is established by the control logic
and depends on the desired channel to be
viewed. This signal and areference signal are
combined in a phase detector to produce an
error signal proportio'nal to the frequency

separation. The error signal is then amplified
by the CA3166E and filtered to provide a dc
voltage to the varactors of the tuner voltagecontrolled oscillator (VCO). The VCO frequency is thus corrected to reduce its
difference with the reference.
Logic-control signals are applied to terminals
10 and 11 (band-select switch) of the
CA3166E. and the proper varactor circuits
for UHF, low-band VHF, or high-band VHF
are selected. The truth table for the selection
logic is shown on page 3.
An analog switch for AFT operation IS included in the CA3166E for automatic correction of frequency transmission errors.

414 __________________________________

~

________________________________

Preliminary Data

CA3168E

2-Dig it BCD-to-7 -Segment
Decoder IDriver

Features:
• Separate BCD inputs and segment outputs for
each digit

For Common-Anode LED Displays
The RCA-CA3168E is a monolithic integrated
circuit intended for 2-digit display such as
"numbers" for TV and "CB" channel selection, and other 0-99 numerical or counting
for consumer or industrial indicator applications. It consists of two independent
BCD-to-7-segment decoder/drivers. Two sets
of BCD inputs are buffered with p-n-p
differential amplifier stages internally referenced to 1.7 V. Each of the eight input
terminals draws less than 15 J1A and is provided with an internal protection circuit.

Decoding is accomplished with 12L ROM's.
The fourteen output terminals are buffered
with Darlington pairs driving common-emitter
output transistors. Each output is capable of
sinking 25 mA for an LED common-anode
display device. The supply-voltage range
(VCC) is intended to be 4.5 V to 6 V. The
output voltage (VO) must not exceed 12 V,
wh ich provides for a wide range of commonanode voltage sources.

•
•
•
•
•
•
•

Input loading less than 15 J1A
12L logic with buffered inputs and outputs
Internal input overrange protection circuit
5-V supply operation
I nternal biasing circuits
Output drive capability of 25 mA per segment
Open collector outputs drive indicators directly

CA3168E
TERMINAL ASSIGNMENT

The CA3168E is supplied in the 24-lead
dual-in-line plastic package.

MAXI MUM RA TI NGS, Absolute-Maximum Values:
. 6V
-O.3/V CC V
±10 rnA
12 V

SUPPLY-VOLTAGE. VCC'
INPUT-VOLTAGE (MIN.lMAX.1 .
INPUT CURRENT (PROTECTION CIRCUITI
OUTPUT VOL TAGE, Vo
OUTPUT SEGMENT CURRENT. IDISPLAY

25 rnA

AMBIENT TEMPERATURE RANGE:
Operating

MSO SEGMENT
OUTPUTS

Oto+700C
-5510 +1s0o C

Storage
POWER DISSIPATION:
Up to +70 00C .

TOP VIEW

. . . . . . 400mW
derate linearly at 8.7 mW/oC

Above +70 C
LEAD TEMPERATURE IDURING SOLDERINGI:
At distance 1/16

± 1/32 inch (1.59 ± 0.79 mm) from case for

10 seconds max.

MSO SEGMENT
OUTPUTS
CA 3168E

~

~~

OUTPUT
BUFFERS

INPUT

BUFFERS

G

-"
g
-7~BM

S!AM

~

~

~

N (iiCM
W

~

~

!OM

%w

"SO
ROM I
ADDRESS
DECODER

"SO
ROM 2

W

!

~~

ADDRESS
DECODER

I

~-

~

N!::
; ~A~

:r-,-_J

~

§

..!!o..~

~zB~

c1

T

~

~ Cu

~

.. %

~""~o~
OW

~S

I

GNO

Vee
13
VOISPLAY

vee

DISPLAY SEGMENT

NOTE: Functional diagram for least significant digit is identical
to functional diagram used for MSD with the exception
of Terminal Assignments (see Terminal Assignment diaIDENTIFICATION
gram). A separate LSD Bias circuit, and % of the Output
Bias Circuit is used for LSD.
Fig. 1 - Functional diagram for Most Significant Digit (MSD).

GNO

(DISPLAY SUPPLY)

92CS-JI03J

NOTE: See truth table for test sequence of input/output logic tests and
Minimum RLOAD = VDISPLAY - VOL For each of the 14 segment
Max.IDISPLAY
drive output terminals. (LED is not used in test circuit)
Fig. 2 - Test circuit.

__________________________________________________________________ 415

CA3168E
TYPICAL ELECTRICAL CHARACTERISTICS at VCC = 5 V, V1 = GND,
VDISP. = 12 V, and TA = 25°C, See Fig. 2
Unless Otherwise Specified
CHARACTERISTIC

LIMITS

TES, CONDITIONS

UNITS

Min. Typ. Max.
Input Voltage High, VIH

2.4

5

VCC

Input Voltage Low, VIL

0

-

0.6

V

15

p.A

-

p.A

1

V

Input Current High, IIH

All BCD Inputs = 5 V

Input Current Low, IlL
On·State Output Voltage, VOL

10(Sink) = 25 rnA

-

VCC = 6 V

-

All BCD inputs = 0 V

Off·State Output Current, 10H
Power Supply Drain Current,lcC
Input Capacitance, CI

-

-10

V

5

50

p.A

17

25

rnA

5

-

pF

TRUTH TABLES
Least Significant Digit (LSD)

Most Significant Digit (MSD)
INPUTS

OUTPUTS

DISPLAY

INPUTS

OUTPUTS

DISPLAY

AB C D

abc d e f g

A B C D

abc d e f g

0 0 0 0

0 0 0 0 0 0 I

0

0 0 0 0

0 0 0 0 0 0 I

I

I 0 0 I I I I

I

0 0 0 I

I 0 0 I I I I

0 0 I 0

0 0 I 0 0 I 0

2

0 0 I 0

0 0 I 0 0 I 0

2

0 0 I

0 0 0 0 I I 0

j

0 0 I I

0 0 0 0 I I 0

j

4
5
5
1

0 0

o

I

0 I 0 0

I 0 0 I I 0 0

y

0 I 0 0

I 0 0 I I 0 0

0 I 0 I

0 I 0 0 I 0 0

0 I 0 I

0 I 0 0 I 0 0

0 I

I 0

0 I 0 0 0 0 0

o

0 I 0 0 0 0 0

0 I

I I

0 0 0 I I I I

I 0 0 0

0 0 0 0 0 0 0

I 0 0 I

0 0 0 0 I 0 0

5
5
1
B
9

I 0 I 0

0 I I 0 0 0 I

I 0 I I

0 0 0 I 0 0 0

I I 0 0

0 0 I

I I 0

,

0

I I

0 0 0 I I I I

I 0 0 0

0 0 0 0 0 0 0

B

I 0 0 I

0 0 0 0 I 0 0

9

[

I 0 I 0

I 0 0 I 0 0 0

H

I 0 I I

I 0 0 0 0 I I

J

I 0 0 0

R
P

I I 0 0

I I I 0 0 0 I

l

I I 0 I

0 I I 0 0 0 0

E

I I 0 I

0 I

F

I I I 0

I I I I I I 0

I I I 0

I I I I I I 0

I I I I

I I I I I I I BLANK

I I I I

I I I I I I I BLANK

-

0 I

I I 0 0 0

-

416 __________________________________________________________________

CA3170G
Features:

TV Chroma System

•
•
•
•

"G" Suffix Type-Hermetic Gold-CHIP in.
Dual-In-Line Plastic Package
The RCA-CA3170G is a monolithic silicon
integrated circuit that performs the functions of subcarrier regeneration, ACC and
APC detection, and tint control in color television receivers. It is designed to function
compatibly with the CA3121 E TV Chroma
Amplifier/Demodulator
in a 2·package
chroma system.

The CA3170G is a TV Chroma System of
advanced design that incorporates all the features of the CA3070E but with the added'
advantage of the mod ified Hue Control Characteristic. With the CA3170G, the designer
can provide a front panel hue control that
functions linearly over its entire range,
particularly desirable consumer feature.

MAXIMUM RATINGS, Absolute-Maximum:
DEVICE DISSIPATION:'
Up IoTA = 55°C . . . • • . • • . . , . • • . • • . • . • . . • . • • . . • . . • . • • . • • . . • . • . . . . . . 750mW
Above TA = 55°C . . . . • . . . . . . . • . . • • . • . . • . • • . • . . • . . . . . . • • • derale linearlv 7.9 mW/oC
AMBIENT-TEMPERATURE RANGE:
. . • • . . . • . • • • . . • • . . • -40 10 +B50C
Operating . . . . . . . . , . . • . . . . • . . . . . .
. . . . • • • • • . • • . • • • . • •-6510 +150oC
Storage . . . . . . . . . . . . . . . . . . . • . . . . .
LEAD TEMPERATURE IDuring soldering):
AI distance 1/16 ±1/32 inch 11.59 ±0.79 mm)
. • . • • . • • . • • • • • . • • . . . . • . • • • • +265 0 C

from case for las max.
Ace OUTPUT

v~. 2:4 Y

180

180

"

I-7---€HID--Wv-Mf--+-{> o}~-".N~-{) R-Y OUTPUT

R[FERENCE

>-+{9}~--"N_--{)G-Y OUTPUT

SUBCAARIER 41

~~~~~r0+H----.
820

UtlLUSQTKU_IS!U"OI(AaO

~~CAP.CI1 ... n'.LUE\

LfUl ...... I~UEI ... ICIlOFU.O\
ICORC;lIhTU.&.R(IHI"'(Of.l.UDI

Fig. 1 - Functional diagram of RCA-CA3172.

Fig. 2 - Schematic diagram for CA3172.

a-y
OUTPUT

+24V

NOTE:
ALL CAPACITORS GIVEN IN pF
UNLESS OTHERWISE NOTED.
ALL RESISTANCES IN OHMS.

Fig. 3 - Static characteristics test circuit.

Fig. 4 - Dvnamic characteristics test circuit.

____________________________________________________________________ 421

CA3189E

FM IF System

Features:

I ncludes I F Amplifier, Quadrature Detector, AF
Preamplifier, and Specific Circuits for AGC, AFC,
Tuning Meter, Deviation-Noise Muting, and ON
Channel Detector

• Exceptional limiting sensitivity:
12jLV typo at -3 dB point
• Low distortion: 0.1% typo (with double·tuned coil)
• Single-coil tuning capability
• Improved S + N/N Ratio

For FM I F Amplifier Applications in HighFidelity, Automotive, and Communications
Receivers

internal power·supply regulators maintain a
nearly constant current drain over the volt·
age supply range of +8.5 to +16 volts.

The RCA·CA3189E* is a monolithic inte·
grated circuit that provides all the functions
of a comprehensive FM·I F system. Fig. 1
shows a block diagram of the CA3189E,
which includes a three·stage FM·I F ampli·
fier/limiter configuration with level de·
tectors for each stage, a doubly·balanced
quadrature FM detector and an audio ampli·
fier that features the optional use of a
muting (squelch) circuit.

The CA3189E is ideal for high·fidelity operation. Distortion in a CA3189E FM-IF
System is primarily a function of the phase
linearity characteristic of the outboard detector coil.
The CA3189E has all the features of the
CA3089E plus additions. See CA3189E
features compared to the CA3089E in
Table I.
The CA3189E utilizes the 16-lead dual-inline plastic package and can operate over
the ambient temperature range of -40 0 C to
+85 0 C.

The advanced circuit design of the IF
system includes desirable deluxe features
such as programmable delayed AGC for the
RF tuner, an AFC drive circuit, and an
output signal to drive a tuning meter and/or
provide stereo switching logic. In addition,

• Externally programmable recovered audio
level
• Provides specific signal for control of interchannel muting (squelch)
• Provides specific signal for direct drive of
a tuning meter
• On channel step for search control
• Provides programmable AGe voltage for
R F amplifier
• Provides a specific circuit for flexible audio
output
• Internal supply-voltage regulators
• Externally programmable "on" channel
step width, and deviation at which muting
occurs

* Formerly Developmental Type No. TA10038.

MAXIMUM RATINGS, Absolute-Maximum Values at TA = 2fiOC:
16V
16V
2mA

DC SUPPL Y VOLTAGE (between Terms. 11 and 4)

(between Terms. 11 and 14)
DC CURRENT (Out of Term. 15)
DEVICE DISSIPATION:
Up to T A = 85°oC
AboveT A =85 C
AM8IENT-TEMPERATURE RANGE:

.....

640mW

derate linearly at 9.9 mW/C

Operating.
Storage

.

-40 to +85 0 C
-65 to +150 0 C

LEAD TEMPERATURE (During soldering):

At distance not less than 1/32 inch (O.79 mm) from case for lOs max.

ALL RESISTANCE VALUES ARE IN 01011.15
It

L TUNES WITH 100 Dr (el AT 101 MHI

00 ::; 7~ (TOKO No. KACS
EQUIVALENT,)

K~a6HM

OR

"

~~~A;l~ -r\''/''.;c...~
RF AMPL

U

ON CHANNEL
INOICATOR

Fig. 1 - Block diagram of the CA3189E.

422 ____________________________________________________________________

CA3189E
ELECTRICAL CHARACTERISTICS, at TA = 25°C, V+ = 12 Volts
TEST CONDITIONS
CHARAC·
TERISTIC

LIMITS

UNITS
Circuit
Min. Typ. Max.
or
Fig. No.

SYMBOL

Static (DC) Characteristics
Quiescent Circuit
Current
DC Voltages:
Terminal 1 (I F Input)

20

111

31

40

rnA

V1

1.2

1.9

2.4

V

1.2

1.9

2.4

V

Terminal 2 (AC
Return to Input)

V2

Terminal 3 (DC
Bias to Input)

V3

1.2

1.9

2.4

V

Terminal 15
(RF AGC)

V15

7.5

9.5

11

V

VlO

5

Terminal 10 (DC
Reference)

5.

c....

:Xw---+-AUDIO

OUTPUT

1
470

2,6

No signal input,
Non muted

ALL RESISTANCE VAL.UES ARE IN OHMS

ttT: PRI.-Qo(UNlOAOE010l75(TUNES WITH 100 pF(CI) lOt OF 34. ON

7132" CIA. FORM

5.6

V

6

SEC. -Qo(UNLOAOEOl_75 (TUNES WITH 100 pF (e2) 201 OF 34, ON
7132" OIA FORM
kQ(PER CENT OF CRITICAL COUPLING} 0170"/.
(ADJUSTED FOR COIL VOLTAGE VC)~150 mV

Dynamic Characteristics

ABOVE VALUES PERMIT PROPER OPERATION OF MUTE (SQUELCH) CIRCUIT

Input Limiting Volt·
age (-3 dB point)
AM Rejection
(Term. 6)
Recovered AF
Voltage (Term. 6)
Total Harmonic
Distortion:*
Single Tuned (Term.
6)
Double Tuned
(Term. 6)

"E~ TYPE SLUGS,SPACING 4rnm

VI(1im)

AMR
VO(AF)

THD

VIN =
0.1 V

S + N/N

Deviation Mute
Frequency

fDEV.

2,6
fO=10.7
MHz,

fmod' =
400 Hz,

Deviation
±75 kHz

THO

Signal plus Noise to
Noise Ratio
(Term. 6)

R F AGC Threshold

VIN =
0.1 V,
AM Mod.
= 30%

-

12

25

IlV

45

55

-

dB

325

500 650

mV

%

6

-

0.5

2

-

0.1

-

%

2,6

65

72

-

dB

1

.. *C- 0.01 ~F FOR 50;.0.5 DEEMPHASIS (EUROPE)
oO.015;.o.F FOR 75;.o.s DEEMPHASIS (USA)

Fig. 2 - Test circuit for CA3189E using a doubletuned detector coil.

10

100

Ik

10k

lOOk

INPUT SIGNAL-,.V

fmod. =0

V16

On Channel Step
V12

VIN =
0.1 V

4,6,7

-

±40

-

kHz

2,6

-

1.25

-

V

Fig. 3 - Muting action, tuner A GC, and tuning
meter output as a function of input
signal voltage.

6

-

0

-

V

DC POWER SUPPLY ('1+)012 V
AMBIENT TEMPERATURE (TAI·25"C
200 SEE TEST CIRCUIT .. FIG. 3

<

fDEV.
±40 kHz

fDEV. >
±40 kHz

~~

-

5.6

-

* THO characteristics are essentially a function of the phase characteristics of the network connected
between terminals 8, 9, and 10.

~

15

5 kll

I'A

t ..

....

~ 100

>

~
~

50

·50

-loa
-150
-100

50
-'0
CHANGE IN FREOUENCY (.:lfl-kHz

100

150

Fig. 4 - AFC charactedstics (current at Term. 7
as a function of change in frequency).

__________________________________________________________________ 423

CA3189E

LEVEL DETECTOR

a METER CIRCUIT

Fig. 5 - Schematic diagram of the CA3189E

TABLE I - CA3189E Features Compared to CA3089E
FEATURES

CA3189E

CA3089E

Low Limiting Sensitivity (12 MV typ.)

Yes

Yes

Low Distortion

Yes

Yes

Single·coil Tuning Capability

Yes

Yes

Programmable Audio Level

Yes

No

SIN Mute

Yes

Yes

Deviation Mute

Yes

No

Flexible AFC .

Yes

Yes

Yes

No

Yes

No

Yes

No

Yes

No

Programmable AGC Threshold and Voltage
Typical S + NIN

> 70 dB

Meter Drive Voltage Depressed at VeryLow Signal Levels
On-Channel Step Control Voltage

424 _____________________________________________________________________

CA3189E

DEVIATION MUTE DETECTOR
ANO AFC AMPU.

Fig. 5 - Schematic diagram of the CA3789E

ALL RESISTANCE VALUES ARE IN OHMS
*L TUNES WITH IOOpF eel AT 10.7 MHz
00IUNLOADEO);l75 (TOKa No. KACS K586HM OR EQUIVALENT)

"·C-O.OIIiF FOR 5O,..s DEEMPHASIS (EUROPE I
-0.01511F FOR

75,...

OEEMPHASIS (USA)

Fig. 6 - Test circuit for CA3189E us;nga sing/e·
tuned detector coil.

__________________________________________________________________ 425

CA3189E
DC SUPPLY VOLTAGE ('1+)"12'1
AMBIENT TEMPERATURE (TAl' 25

~
~

°c

+12V

1,8 k

"

120

3.3k

5

ili

390

I'O.F

3.3k

390

470

100

!

IOOpF

10K

~ 80

i

AFT

~ 60

"

~ 40
~
20

0

,

10
20
LOAD RESISTANCE(BETWEEN TERM 7 AND TERM.IOI-kG

"

"

Fig. 7 - Deviation mute threshold as a function
of load resistance (between Term. 7
and Term. 10).

12k

~OR::·Hl

\

TUNER

InF

AUDIO

2,2 k

.,10

470

2.2k

ALL. RESISTANCE VALUES ARE IN OHMS
CF: CERAMIC FILTERS, TOKO CSFE OR EQUIVALENT

CD -20

*1. TUNES WITH 100 pF (e) AT 10.7 MHz

l'
~
g -40

00 (UNL.OADED)I:I 75 (TOKO No. KACS K~B6 HM
OR eQUIVALENT)

-30

g~

-50

-60f.....--+-'~"'VY--+--+---j

RF AGe

-'0
-'0

ov

Fig. 9 - Complete FM (F system for high-quality receivers.

10

SIGNAL LEVEL-,.V

Fig. 8 - Typical limiting and noise characteristics.

AUDIO
OUTPUT

A.F.T.

0V

+12V

COMPLETE FM I F SYSTEM
FOR HIGH·QUALITY TUNERS
The circuit, Fig, 9, provides a

complete FM I F system for a
high-quality receiver. Either one
Or two stages of amplification
and bandpass filtering may be

TUNING
METER

A.F.
A.G.C.

10.7 MHz
INPUT

ov

desired, depending on the receiver
requirements. Figure 8 shows

typical limiting and noise
characteristics for each circuit
configuration which can be
compared to the CA3189E alone.

Fig. 10 - Printed circuit-board and component layout for circuit shown in Fig. 9.

426 ____________________________________________________________________

CA3221G
Features:

TV Chroma Amplifier I
Demodulator
Provides Complete System for Processing Chroma
When Used with RCA-CA3070 or CA3170
"G" Suffix Type-Hermetic Gold-CHIP in·
Dual-In-Line Plastic Package
The RCA-CA3221 G is a monolithic silicon
integrated circuit.chroma amplifier/demodulator with ACC, saturation control, and killer
control for use in NTSC color TV receivers.
It is designed to function compatibly with
the CA3070 or CA3170 in a 2-package
chroma system. The CA3221G is functionally
identical to the industry standard CA3121,
but has a modified saturation control as
well as a modified color difference matrix.
The CA3221 G is supplied in the 16-lead
dual-in-line plastic package with a hermetic

• Excellent linearity in dc chroma gain-controlled circuit
• Improved filtering resulting in reduced 7_2-MHz output
from the color demodulators
• Current limiting for short-circuit protection
• Good tolerance to B+ supply variations
• Good temperature coefficient stability
• Gold-CHIP for increased reliability

Gold-CHIP (G suffix). The transistor chips
. used in the hermetic· Gold-CHIP plastic
packages are of the sealed-junction type
designed to provide protection against the
deteriorating effects of humidity and other
surface contaminants without the need for a
hermetic package enclosure. The semiconductor junctions are sealed by utilizing a
silicon nitride passivation layer. A multilayered, highly corrosion-resistant, terminalconnection system of unique design is
employed.

MAXIMUM RATINGS at TA = 25·C
Supplv Voltage ._

.

.30V

Device Dissipation:
UptoT A ~ SS·C

Above TA = SS·C
Operating Temperature Range.

Stores. Temperature Range

. . . . • . • lW
derate linearly 10.S mW/·C
.. -40 to +8S·C
. -65 to +IS0·C

1500

~

..

~

1000

,

L.ad Temperature (During Solderingl
At distance 1/1S" ±1/32" (I.S9 :10.79 mml from ca.. for 10 s max.

100

200

!OO

400

eoo

100

700

N1SC CHROMA INPUT SIGNAL(TERM2)-!"V,_p

Fig. 2 - Typical ACC plot for the CA3221G when
used with the CA3070.

:I T. ' ...

AMI''''T

!;

,

·el

,... CoN·

,oil

~~',~~

I~

CHROMA
INPUT

II
TERMINAL IS VOLTABE-Vdc

92CS-30158

Fig. 3 - Saturation control characteristic.
Fig. 1 - Functional block diagram of the CA3221 G.

__________________________________________________

~

________________ 427

CA3221G
ELECTRICAL CHARACTERISTICS at TA = 26°C and Referenced to Test Circuit (Fig.7J
CHARACTERISTIC.
TERMINAL MEASURED.
ANDSVMBOL

LIMITS

TEST CONDITIONS

UNITS

Min. Typ. Max.

-

Supply Current, IT

-

40

50

mA

Input Sensitivity, V2

Vary Eg; set Ii 11 for 2 V RMS
53= 1

4

12

20 mVRMS

Second·Stage Sensitivity, V4

Vary Eg; set VII for 2 V RMS
53= 1

30

53

75 mVRMS

-

-

70 mVRM5

Output Voltage (Killer off)
Saturation Control
Characteristics:
• VII
50% Gain
0% Gain

Switch Positions: 51 =2, 52=2,
S3= 1 Adjust killer potentiometer
until output drops
Vary Eg; set V11 for 2 V RMS
with S3 = 1. Set 53 = 2
measure VII
Same as above, S3 = 3

Demodulator Characteristics:
Output Voltages,

0.71 0.95 1.16

-

-

VRMS

20 mVRM5

V9, Vl0' VII

-

13.5 14.5 15.5

V

DC Output Balance
(Between any 2
outputs)

-

-0.6

-

+0.6

V

-

-

0.8

Vp-p

1.75 1.85 1.95

VRMS

Unbalance,
Vg. V'0' V,I

Eg=O; Switch Position: 51=1,
S2=I, S3= 1

Relative OutputsR-V, VIO

Vary Eg; set V 11 for 2 V RMS,
53= 1

0.6

0.7

0.8

VRMS

90
244

Eg= 750 mV

2.8

-

-

degrees

with V 11 as reference

-

G-V, V9
Relative Phase R-V. V,0
G-V, Vg
Max. Output Voltage. V,I

Vary Eg; set V 11 for 2 V RMS;
read phase of V 10 and V9

. .

degrees
VRMS

*See Fig. 3 for saturation control characteristic .

CIRCUIT OPERATION
the demodulator input (Terminal 13). The
The CA3221 G consists of three basic circuit
demodulator also receives the R· V and B· V
sections: (1) amplifier No. I, (2) amplifier
demodulator subcarrier signals (Terminals 7
No.2, and (3) demodulator. Amplifier
and 8) from the oscillator output of the
No. 1 contains the circuitry for automatic
chroma signal processor. The R-V and B-V
chroma control (ACC) and color·killer sensing.
demodulators and the matrix network conThe output of amplifier No.1 (Terminal 3)
tained in the demodulator section of the
is coupled to the Chroma Signal Processor
CA3221G reconstruct the G-V signal to
(CA3070 or equivalent) for ACC and autoachieve the R-V. G-V, and B·V color differmatic phase control (APC) operation and to
ence signals. These high-level outputs signals
the input of amplifier No. 2 (Terminal 4)
with low impedance outputs are suitable for
containing the chroma gain control circuitry.
driving high-level R, G. B output amplifiers.
The signal from the color-killer circuit in
Internal capacitors are included on each outamplifier No. 1 acts upon amplifier No.2 to
put to filter out unwanted harmonics. For
greatly reduce its gain under weak signal
additional operating information and signal
conditions.
waveforms, refer to Television Chroma
The output from amplifier No.2 (Terminal
System (utilizing RCA-CA3070, CA3071 ,
14) is applied, through a Bandpass Filter. to
CA3072). File No. 468.
~8,

_____________________________________________________________

CA3221G

KILLER AOJ.

v·

CA3070

I

L ___

CA~r70

--1---'0
AMPLIFIED CHROMA

92CM-30142

Fig. 4 - Simplified functional diagram of a two-package TV chroma

system utilizing the CA3221G and CA3070 or CA3170.

Fig. 5 - Schematic diagram of CA3221G.

__________________________________________________________________ 429

CA3221G
2.7M

0.01

o-~~--j~~----------------4r------------~~----O·"V

TO TERM.6

410

CHROMA
INPUT

~

41

I

0'°4

CA3221G

I
I
I
I
I

I

IL ___ _

~~Jt~F

3

1

8.2'

=-

100

=-

100
1.8 M

12

CHROMA

GAIN CONT.

50

+24 V

390 K

680

1.2 M

20.

APC
ADJ

20.

62.

470/lW

2.1K

62.

ACC
AoJ

62 K

621(

410

50

36 K

"

HORIZ. KEY PULSE
+4\1,4.'5,.s
INPUT

RESISTANCE VALUES ARE IN OHMS.

UNLESS OTHERWISE INDICATED, ALL CAPACITANCE
VALUES LESS THAN t ARE IN MtCROrARADS,

92CL-30'4'

lOR GREATER ARE IN PICOFARADS.

Fig. 6 - Outboard circuitry of B typical two-package chroma system for color-TV
receivers utilizing the CA3221G and CA3170.

430 __________________________________________________________

~------

CA3221G
TO
TERM. 6

I-Y

OUTPUT
KILLER

10011

470

S2CK-30IS.
NOTE:

2.2-114 LOADS ONLY FOR TEST PURPOSE, 3.5-110 LOADS RECOMMENDED FOR APPLICATIONS.

RESISTANCE VALUES ARE IN OHMS.

CAPACITANCE VALUES ARE IN MJCROFARADS UNLESS OTHERWISE INDICATED.

Fig. 1- Typical characteristics test circuit for the CA3221G.

__________________________________________________________________ 431

432

MOS Field-Effect
Transistors
Technical Data

_ _ _ _ _ _ _ _ _ _ _ _ _ _ 433

3N128, 3N143
Silicon MOS Transistors

Performance Features

N-Channel Depletion Types

•
•
•
•
•

For Amplifier, Mixer, & Oscillator Applications in Military &
Industrial VHF Communications Equipment Operating up to 250 MHz
RCA·3NI28 and 3N143 are N-channel depletion-type silicon
insulated·gate field-effect transistors utilizing the MOS·
construction. The 3NI28 is intended primarily for VHF

MlJdmum Ratings, Absolut.·Muimum

Values .r TA

amplifier service in military and industrial applications. It

Continuous dc . . . . . . . . .

also is extremely well suited for use in de and low.frequency

V
V

. +1.·8

V

± 15

,V
rnA

Peakae . . . . . . .
·DRAIN CURRENT. ID

amplifier applications requiring a transistor having high
power gain, very high input impedance, and low gate leakage.

c:

• 25°

·DRAIN·TO·SOURCE VOLTAGE, VDS . . . .
. . +20
·DRAIN·TO-GATE VOLTAGE, VDG . . . . . . . . . . . +20
·GATE·TO·SOURCE VOLTAGE. VGS:

. ,SO

~RANS~STOR DISSIPoATION, PT :

The 3Nl43 is designed for use as a VHF mixer and oscillator.

At Ambient up to 25 C . . • . . . ,
. 330 rnW
Temperatures above 25° • • . . . . . . . . . . , Derate 2.2 mwtc

Because of their improved transfer characteristic and in·
creased dynamic range the 3NI28 and 3N143 provide
substantially better cross·modulation performance in linear
amplifier applications than conventional (bipolar) transistors
and are free from diode-current loading common to junction
type FET's. These transistors are hermetically sealed in

t

"c

ELECTRICAL CHARACTERISTICS: (A. TA = 25° C)
Measured with Substrate Connected to Source Unless Otherwise Specified.

Gate Leakage Current
Zero·Bias Drain Current

lOSS

Orain-Io-Source Culoll Currenl

Io(off) VOS' 20V, VGS' -8 V

Gale-Io-Source Culoff Vollage

gls

Drain·ta-Source Channel Resistance

15

25

- -

50

-

-3

-8

0.5

15

5

30

mA

-

50

p.A

-3

-8

Y

VOS' 15V,I0 .50p.A

-0.5

VOS' 15V,I0 .5mA,I. 1kHz

5,0007,500 12,00 5,00 7,500 12,00 /Allho

rOs(on) VOS' 0, VGS = 0, f· 1kHz

Reverse Transfer Capac,Hance"

ClSs
Ciss

Low noise figure (3N128) - 3.5 dB typo at 200 MHz
High VHF amplifier gain (3N128) -16 dB typo at 200 MHz
Low input capacitance - 5.5 pF typo
High transconductance - 7500 J.tmho typo
High input resistance - 1014 n typo
High conversion gain (3N143. mixer) - 13.5 dB typo at
200 MHz

-

• VH F amplifiers, mixers, converters and if·amplifiers in
communication receivers.
• High-impedance timing circuits
• 0 etectors. oscillators. frequency multiplien, phase
splitters. pulse stretchers and current Ihnittrs
• Electrom'eter amplifiers
• Voltage-controlled attenuators
• High impedance differential amplifiers

-

-

200

-

-

200

TERMINAL OIAGRAM

n

-

Small-Signal Shorl-Circuit
Small-Signal Short-Circuillnpul Capacilance

··
·
·
·

LIMITS
3NI43
3NI28
NITS
MIN. TYP • MAX. MIN. TYP. MAx.
0.1 1000
pA
- 0.1 50
5 - 200 nA
5

VOS' 15V, VGS'O

VG~off)

Forward Transconductance

·

CONDITIONS
VOS "0, VGS' -8 VTA' 25 0C
VOS ·0, VGS .. 8V TA' 1250 C

IGSS

•
•
•
•
•
•

AppliC8tions

LEAD TEMPERATURE (DUling soldering):
At distances not closer than 1132 Ineh to
seating surface for 10 seconds maximum .' . . . . . 265

tin accordance with Jedec Registration Data Format JS9·RDF'ltB,

SYMBOL

Device Features

• AMBIENT TEMPERATURE RANGE:
Storage and Operating . • • . . . . .

JEDEC TO·72 metal packages.

CHARACTERISTIC

Large dynamic range
Greatly reduC8$ spurious responses in rceiver front ends
Permits use of vacuum·tube biasing techniques
Excellent thermal stability
Superior crossmodulation capability

Drain
2 . Source

pF
pF

VOS' 15V,10'5mA,I.0.llo IMHz 0.15 0.25 0,35 0.12 0.25 0.38
7 - 5.5
7
VOS -15V,10 '5mA,f'0.llo IMHz
- 5.5

3 . Insulated Gate
4 . Bulk (Substrate)

Coml11on·Source Configuration

Inpul Admillance

Vis

Forward Transfer Admittance

Yss
Yos

Oulput Admillance
Maximum Available Power Gain
Insertion Power Gain (Fixed Neutralization)

and Case

- 0.4 +J7.3
- 7 -,n
- 0.28 +Jl.8

1·2DOMHz
Vas' 15 Volls
10' SmA

GpS

Power Gain (Conversion

VOS' 15 V,IO - ImA,fin • 200 MHz
Gps(c)
loul- 30MHz

ISee Fig. 3)
Noise FiglJrelSee Fig. 1&2)

NF

VOS' 15V,ID ·5mA, 1·200MHz

-

-

21

-

-

-

-

dB

13_5

16

-

-

-

-

dB

-

-

-

lO

13.5

-

dB

-

3.5

5

-

-

-

-

MAG VOS' 15V,10' 5mA,f. 200MHz

See Fig. I

-

- - - -

rnmho
mmho
rnmho

"'Inaccordance with JEDEC Registration Data Format JS9·RDF·UB.
"Three-Terminal Measurement: Source Returned to Guard Terminal.
~-------------i------------l

I

o.~·

CI

I

I

I

I

'

I

Fig. 2·No;se ligure measurement setup lor 3N128

C5 OUTPUT

I

~on

I

LOAO

,

I
I
I

I
14,71\

I

I

I

I

C l , C2: ~r~~~ar:~~able air capacitor: E. F. Johnson Type 160·102

C3:

J~~o.::O~i~;~~~g~5~~ri~~i:~~e~(acitor: JFD Type VAM-OIO,

C4'cs: ~'~if~r P~:~i~;t~~ variable air capacitor:

Roanwell Type

I

I

I

El(TERI'lAL~

:
I

SHIELO

~;"ttTE

TYPE

Z23~OFl EOUIV,I

I

1
I
:

L ____ ~£-----L--_-_-- ~--'--.J

Ll:

;i=~ Sill;~;~!fl~~a~'~t~: ~:C!ln~i~7g~.~.0~.~25!,i;dew~~~f;~
length approx.

of wind ina

0.65~.

Tapped at 1·1(2 turns from Cl end

15p.H

7;?r 2~~O ~

L2: Same .., Ll except winding length approx. 0.7-; no tap.
Lt =4Turnsl/4"dia.,3/S"long

-=-

-=-

-=-

No, 22 Bare·Tinned Wire

",1111 .. ,,,.,. 'n

.~m.

ood I 4'

""I.ua'k" ..... p.. ,I,.d
.1.11 CoPt""" '" pF

• TUIlULiFlCEIIUIC
'OISCCEIIUIC

Fig. 1· T8St circuit used to mfNIsure 2O().MHz maximum
"sable power lJiIin and noise figure for 3N128

Q'" 3N143

VOO'lo

v

Fig. 3· Conversion power gain test circuit for3N143

434 __________________________________________________________________

3N128, 3N143
SOURCE AND SUBSTRATE GROUNDED
AMBIENT TEMPERATURE (TA1°2.,·C

o

"

~ 2.0

,

10

-,

15
GATE-TO-SOURCE VOLTS (Vos)

DRAIN·TO- SOURCE VOLTS (VOS'

Fig. 4 -Drain current vs. drain-ta-source voltage

GATE-TO-SOURCE VOLTS IV os '

Fig. S -Drain current vs. gate-to-source voltage (Ves)

Fig. 6 - Forward transconductance Ys. gate bias yo/tage

5
4

10

,.1.±±±

15

ORAIN-TO-SOURCE VOLTS (VOS)

•

DRAIN MILLIAMPERES CIol

Fig. 7 - Forward transconductanu vs. drain current

Fig. 8 ·/nput admittance vs. drain current

Fig. 9 -Input admittance ys. drain·to·source Yolta,e

•

'ra IS NEGLIGI.BLE AT THIS

1rl".

FREQUENC~-r±::t ~+-t­
-r'-t

.

-1.0

o

,

10

15

DRAIN-TO-SOURCE VOLTS (VOS)

ORA.N MILLIAMPERES IIOI

Fig. IO-Reverse transadm;tfance vs. drain current

Fig. 11-Reyerse tronsorlmitfonce vs. droin·to-source
yoltage

Fig. 12- Forward transadmittonce vs. drain current

r.oI

Ii:•
~

l

COMMON-SOURCE CIRCUIT
SOURCE AND SUBSTRATE GROUNDED
AMBIENT TEMPERATURE ITAI'25·
fREQUENCY 111'200 MHI
DRAIN MILLIAMPERES tIplo'

~on

g~

.

...!~ 2

'

~=

.2

'"
,
10

~

.,

W

DRAIN-TO-SQURC(. VOLTS I YOS)

20

DRAIN-TD-SOURCE VOLTS IVOSI

Fig. J3-Forward transadmitfance vs. drain.to-source
voltage

Fig. 14· Output admittance vs. drain current

Fig. IS· Output admittance vs. drain.fa.saurce yoltage

_______________________________________________________________ 435

3N138

SlUCON INSUlATED-GATE FIELD-EFFECT TRANSISTOR
For Critical Chopper Appficalions and Muniplex Service in
Instrumentation and Control Circuits

TERMINAL DIAGRAM

~
~

RCA-3N138 is a silicon, insulated-gate fieldeffect transistor of thl' N-chanm·J dt'pIl·ti"on tYPl'.

utilizing the MOS'" construction. It is intended pri.
marily for critical chopper and multiplex applications up to 60MHz.
The insulated gate provides a very high value of
input resistance (IOU ohms typ.) which is relatively
insensitive to temperature and is independent of

Features
N-Channel Depletion Type

1 - Drain
2 - Source
3 - Insulated Gate
4 - Bulk (SubSTraTe)
and Cose

Applications
Servo Amplifiers
Telemetry Amplifiers
Computer Operational Amplifiers
Sampling Circuits
Electrometer Amplifiers

ORAIN-TO-SOURCE VOLTS 'I~
AMSIENT TEMPERATUR'E (TAI·25·C

gate-bias conditions (positive. negative, or zero
bias). The 3N138 also reatures extremely low feed-

excellent thermal stability
zero inherent offset voltage
low leokage current: 10 pA max.
low "on" resistance1I,~lon) = 240n typo (VOl! ::..: OV)
high "0"" reslstanceR,,~loffJ
10 11l0.yp.
low feedback capacitance C...
O.18pF typo
low input capacitance C...
3pF typo

through capacitance W.1HpF typ.> and zero inherent
offset voltagl·.

The 3N138 is hermetically sealed in the JEDEC
TO·72 package and features a gate metallization that
covers the entire source-ta-drain channel.

~

• Metal-Oxide-Semiconductor.

IS

z

~ 10

Maximum Ratings, Ahsolu,e-Maximum Value.:
V

•-.

· 35, -0.3 max.

v

Fig. 1 - Drain Current VB Gate-to-Source Voltage

· 35, -0.3

\'

{SlIbHt/'uf(' "'III/H't'f"" til HII/I/'(:,' /nl/('1IB (Jth,'/'1('i8t 8p/'c:i/ied)

DRAIN:TO·SOURCE
VOLTAGE, "liS
DRAIN-TO-SUBSTFlATE
VOLTAGE, \'1I1!
SOURCE·TO·SUBSTHATE
VOLTAGE, VSB
DC GATE-TO-sOUnCE
\'OLTAGE, V,;s

-35 max.

n18X,

GATE-YO-SOURCE VOLTS (vGS J

· 14 max.
PEAK VOLTAGE, GATE-TO-ALL
OTHER TERMINALS: Vc;s, VI;[J.
Vial" non-repetitive
- 45 max.
DRAIN CURRENT. In (Pulae duration
~

O,ID1 ••• ,. _ •• ,.

Fig. 3 -

Drain Current vs Gate-to-Source Voltage

\'

v

50 max. rnA

TRANSISTOR DISSIPATION, p"
AI ambient temperalure~ up to 250C ,
above 25°(' " , " , " " " , . , ' ..

-I

GATE-TO-SOURCE VOLTSIVGsJ

v

·-IOmax.

P~:b~TGAAGTE~-'{,?~SOURCE

alms,dutyfactcr

-2

330 max, mW
Delate linearly at2,2'mW/OC

AMBIENT TEMPERATURE
RANGE,
-65 to +150
Storage
Operating
-65 to .... 125
LEAD TEMPERATURE
(During Soldering) :
At distances ~ 1/32" to seating surface for Ip seconds max.
265 max,

'C
'C

ORAIN-TO-SOURCE VOLTS ('lobs J

'C

·Fig. 2 -

Drain Current VI Drain Voltage

ELECTRICAL CHARACTERISTICS, at TA = 25° C, Un'e.. Otherwise Specified. Substrate Connected to Source.
CHARACTERISTICS

SYMBOLS

LIMITS
Type3NI38

TEST CONOITIONS

Gate·LeakageCurrent

Iw'-'l

Max.

VIlS == flO. Villi = 0, T" == 2ScC
V,u" = ± 10, VII" == 0, T., = 12ScC

0.1
20

10
200

pA
pA

240
135
350

35.

""
"

Drain·to-Source "ON" Resistance

rlm(on)

Vml = 0, VIlli == 0, f = 1 KHz, l, = 2ScC
VOM = +10, VIJIoI .. 0, f = 1 KHz, T., = 2ScC
V':11 = 0, VUIl = 0, f "" 1 KHz, T., = 12Se C

Drain·to-Source"OFF" Resistance

R,,,.(.H)

V,al

Drain·to·Source Culoff Current

lu(off)

Fig. 4 -

2X loa

= -10. VI"" = +1

V,a~ =
VOIl =

-10, VIlli = +1, II = 2S cC
-10, V'IM = +1, l, : : : 12ScC

Small·Signal, Shorl·CirclIit, Reverse
TransferCapacibnce

Coo

V,:11 = -10, VI'll

Small·Signal, Short·Circuit, Input
Capacitance

C...

VI;"

lera·Gate·Bias Forward Transconductance

g,.

VI,,;= 12.

OffsetV~ltage

V"

V,:,. = ±IO, VJll'o

=

0, I = I MHz

Low·Level Ora;n Current VI
Drain· la-Source Vo/loge

UNITS

Typ.

Min.

10 111
0.01
0.01

0.5

nA
,A

0.25

0.4

pF

5

'.'I-+-+-I-+--+--If--+-+--1-t-+--i
'.'I-+-+-I-+-+--If--+-+--1-+-+--i
'.'1-+-+-1-+-+-1-++--1-+-+--1
'.'J-+-t-J--H--t-J-i--t--1I-i--r-;

= -10, VI"; ==

0, f

= I

10'"' SmA

• In measurements of Offset Voltage, thermocouple effects and contact
potentials in the m~surement setup may cause erroneous readings of 1
microvolt or more. There erm" may be minimized by the use of solder

=0

MHz

pF

6000

",mho

O·

having a low thermal e,ni.f. such as Leeds & Northrup NO.1D7·1,O.1.
or equivalent.

'.'J-+-t-J--tt-t-J-i--t--1I--t--r-;

'.'J-+-t-J-+~"' which is relatively insensitive to temperature and is independent of gate-bias conditions (positive,
negative, or zero bias>. The 3N139 also has a high
transconductance, a low value of input capacitance
(3 pF typ.), and a very low feedback capacitance
(0.19 pF typJ.

Maximum Ratings, Absolute-Maximum Values:

Crss "" 0.2 pF typo

DRAIN-TO-SOURCE VOLTAGE. VDS ' • •
DRAIN-TO-SUB3TRATE VOLTAGE, VOB +35,
SOURCE-TO-SUBSTRATE
VOLTAGE, VSB ••••.•••••••.•• "'35,
DC GATE-TO-SOURCE VOLTAGE. VGS'
PEAK GATE-TO-SOURCE VOLTAGE, Vas
PEAK VOLTAGE. GATE-TO-ALL OTHER
TERMINALS; Ves, VGD, VGB, nonrepetitive, •• , . , • • • • • • • • • • • • •
DRAIN CURRENT, ID ••••••• ,....

"'35 max.
-0.3 max.

V
V

elow got. leokage current
IGSS = 0.1 nA 'yp.

-0.3 max.
flO max.
114 max.

V
V
V

ehigh drain.to-source yoltage: +35 max. V

±42 max.
V
50 max. rnA

TRANSISTOR DISSIPA TIOI'. PT:
At ambient temperatures up to 25°C. , , .
330
mW
above 25°C. . .
. ..... Derate linearly at 2.2 mW/oC
AMBIENT TEMPERATURE RANGE:
Storage •• , •.•••••••••••• , • ••
-65 to +175°C
Operating, ••••• , • • • • • • • • • • ••
-65 to + 175°C
LEAD TEMPERATURE (During Soldering):
At distance not c10aer than 1132 inch to
seating surface for 10 seconds max•••
265 max. °c

The 3N139 is hermetically sealed in the standard
4-lead JEDEC T0-72 package.

• Meta[·Qxide-Semiconductor

TERMINAL ARRANGEMENT

~
~

1 _ Drain

2 • Source
3· InsulaTed Gale
4· Bulk (SubstraTe)
and Case

ELECTRICAL CHARACTERISTICS, at TA = 25 0 C Unleu Otherwise Specified. Bulk (Substrate) Conneded to Source
TEST CONDITIONS
FREQUENCY
CHARACTERISTICS

SYMBOLS
f

DC

DRAIN·TO·
SOURCE
VOLTAGE
Voo

DC

DC

GATE·TO·
SOURCE
VOLTAGE
VGf'

DRAIN
CURRENT

mA

LIMITS
UNITS

I,

V

V

Min.

Typ.

'oIOFF)

15

-8

-

-

50

,A

Zero·Bias Drain Current*

lOSS

15

0

5

15

25

mA

T.\ = 2S"C

0

±lO

-

I

,A

IGSS

-

Gate Reverse Current

T... = 100°C

0

±lO

-

-

100

,A

·-6

V

pF

MHz

Orain·to·Source Cutoff Current

Gate·to·Source Cutoff Voltage

VGSIOFF)

Small'Signal, Short·Circuit
Aeverse·T ransfer Capacitance
(Orain·to·Gate)

Crss

II

0.05

-2

-.

I

II

5

0.05

0.2

0.4

"

-

kn

3

10

pF

6

-

kn

I..

-

pF

-

mmho

Input Resistance

tis

100

II

5

Input Capacitance

Ciss

100

II

5

Outptrt Resistance

'"

100

II

5

Output Capacitance

Ces,

100

II

5

II

5

Forward Transconductance

OI,

1 kHz

.-

-

5

DRAIN-TO-SOURCE VOLTS (Vos)

--

Fig. 1 - Drain Current vs Drain Voltage

GATE-TO-SOURCE VOLTS (VGS I

DRAIN MILLIAMPERES (10 I

GATE-TO-SDURCE VOLTS (VGS)

Fig. 2 - Drain Current vs Gate·to-Source Voltage

Max.

Fig. 3 -

1 I<. Hz forward transconductance vs drain current

Fig. 4 -

1KHz forward transconductance

V$

gate-to-source

voltage

____________________________________________________________________ 437

3N140, 3N141

SILICON DUAL INSULATED·GATE FIELD· EFFECT TRANSISTORS

N-Channel Depletion Types

APPLICA 1/0NS

For Amplifier and Miler Applications Up to 300 MHz

• RF amplifier and mixer in military and industrial
communications equipment

Maximum Ratings, Absolute-Maximum Values, at T A .: 25 Q C

RCA.3N140 and 3N141* are n-channel silicon, depletion
type, dual insulated-gate, field-effect transistors utilizing the MOS** construction. They have exceptional
characteristics for rf-amplifier and mixer applications at
frequencies up to 300 MHz. These transistors feature a
series arrangement of two separate channels, each
channel having an independent control gate.

DRAIN-TQ-SOURCE VOLTAGE, VDS • .

0 to +20

V

• aircraft and marine vehicular receivers

Continuous (dc) • , . . • . . . • . . . • .

-8 to + 1

V

• CATV and MATV equipment

Peak ac • . . • • . . . • • . . • • . • . • .

-8 to +20

V

GATE No.I-TO-SOURCE VOLTAGE, VGlS:

GATE No.2-TO-SOURCE VOLTAGE, VG2S:
Continuous (dc) . . . . • . • . . . . . . . -8 to 40'7. of VDS
Peak ac • • . . . • . . • . . . . . . . . ..
_8 to +20

The 3N140, used in a common-source configuration in
which gate No.2 is ae grounded, reduces oscillator feedthrough to the antenna thereby minimizing oscillator
radiation. The 3NI41 provides excellent isolation between the oscillator and rf signals because each of the
two signal frequencies being mixed has its own control
element.

V
V

DRAIN-TO-GATE VOLTAGE.
VDGl OR VDG2 • . • . . . • • . . . . . .

+20

DRAIN CURRENT. ID
(Pulsed): Pulse duration < 20 ms.
duty factor 0.15 . . • . . :-•.••..•

50

rnA

TRANSISTOR DISSIPATION, ?T:
At ambient l up to 25°C ••.•••..

400

rnW

V

• telemetry and multiplex equipment

PERFORMANCE FEA TURES
• wide dYflamic range permits large_signal handling
before overload
• dual-gate permits simplified agc circuitry

5.

• Virtually no agc power required
• greatly reduces spurious responses in 1m receivers

The mixing function performed by the 3N141 is unique in
that the signal applied to gate No.2 is used to modulate
the input-gate (gate No.1) transfer characteristic. This
technique is superior to conventional "square law"
mixing, which can only be accomplished in the nonlinear region of the. device transfer characteristic.

temperatures ~ above 25°C • • . . . . .
derate linearly at
2.67 rnW/oC
AMBIENT TEMPERATURE RANGE:
Storage and Operating. • • . . . . • .. -65 to +175°C
LEAD TEMPERATURE (During soldering):
At distances> 1/32 inch (rom
seating surface for 10 seconds max. •
265
°c

The use of the 3N141 as described provides high useful
conversion gains at all vhf frequencies, and the reduction in spurious responses. is substantial and easily..
obtainable in simple circuits.

The 3N140 and 3N141 are hermetically sealed in metal
JEDEC TO-72 packages.

DEVICE FEATURES

*

• low gate leakage currents __
IG ISS & IG2SS = 1 nA max. at T A = 25°C

Fonnerly Dev. Nos. TA2644 and TA7274. respectively.

** Metal-Oxide-Semiconductor.

• permits use of vacuum-tube biasing techniques
• excellent thermal stability
• superior cross.modulation performance ond greater
dynamic range than bipolar or single.gate FET's

• high forward transconductance - gfs = 6000 ~mho min.

ELECTRIC·AL CHARACTERISTICS, at TA = 25°C Unless Otherwise SpeCified. Common.Source Circuit.
LIMITS
CHARACTERISTICS

SYMBOLS

TYPE 3N140
RF AMPLIFIER

TEST CONOITIONS

.MIN.
Gate No.l·to-Source Cutoff Voltage

Ves'" +16V, 10" 200 iJ.A
VG2S = +4V

Gate No.2·to·Source Cutoff Voltage

VOS" t16V, Ie = 200I/-A

TYP.

.,
.,

TYPE 3Nl41
MIXER

MAX.

MIN.

UNITS

TYP.

MAX.

·4

.,

·4

·4

.,

·4

• high unneutralized RF power gain - Gp ,
16 dB min. at 200 MHz

=

• low VHF noise figure __ 4.5 dB max. at 200 MHz

TERMINAL DIAGRAM

~
'

VGlS = 0
VGlS '" -lOV,

vG2S '" 0

nA

Ves '" 0, T A :: 25°C

'o,ss

Gale NO.1 Leakage CUffent

I

nA

4

,--------:- VGlS '" -lOV, VG2S " 0
VOS:: 0, TA ~ 125°C

0.'

0.2

I

i

nA

Gate No.2 Leakage Current

IG2SS

V G2S '" tlV

LEAD 1 • DRAIN
LEAO 2 - GATE No.2
LEAD 3 - GATE No.1
LEAD 4 • SOURCE, SUBSTRATE
ANO CASE
~

-- -

~-

-- -

'

--I

I

~

~~

I
I

nA

Ves" 0, VGlS" 0, TA '" 2S oC
I

VG2S "-20V, VG1S :: 0

0.2

12711

0.2

I

Ves = 0, TA '" 125°C

f

ZelO-Blas Drain Current

lOSS

Voo = + 14V, VGlS '" 0,

lB

30

10000

18000

lB

30

rnA

10000

18000

"mho

V G2S " +4

I
I
f

Forward Transconductance

'f,

(Gate No.1 to Oraln)
Cutoff Forward Transconductance
(Gate No.1 to Drain)
Small-Signal, Short-Circuit

ifS(ofO

CISS

Input Capacitance'
Small-Signal. Short,Clfcul! Reverse
Transfer Capacitance (Drain to

C rss

Gate No.1)'"
Small-Sq/:nal Short-Circuit

Cos s

Output Capacitance

Veo '" +14V,

to

=

10 rnA

6000

6000

VG2S ::' t4V. f " I kHz
Voo:: t14V, VGIS:: -O.SV

100

..:mho

VG2S ::' ·2V, f" 1 kHz
VOS" +13V, 10" 10 mA
VG2S = t4V, f - 1 MHz
VOS '" t13V, 10" 10 rnA
VG2S " t4V, f " 1 MHz

5.5

r

pF

5.5

O-+----'V>N-Q(~~gl

VAGCJ;:

0.01

VOS" t13V, 10 " 10 mA
VG21i = t4V, f 1 MHz

0.02

0.03

0.01

0.02

2.2

'.2

0.03

pF

pF

Q "3Nl40.
.. D,sc ceramic.

All resistors In ohms

• Tubular celamic.

All capaCitors In pF

/I Ferule bead (l.'2 used); Indiana General NO.H1742C-(A-147),

0-

F-llS7-1·H

Power Gain (See Flg.1

Gp,

for Measurement CUCUlt)

Voo'" tlSV. RS" 270\1

IG

,8

lB

f" 200 MHz, RG " 500
Voo" +15V, RS" 1200,

Conversion Power GaIn
(See Fig.2 for Measurement CirCUIt)

Gpsc

fiN" 200 MHz, fOUT " 30 MHz
OSCIllator injection voltage·

13

17

,8

" 2.sV(rms)
Measured Noise Figure
(See Flg.l for Pfleasurement CirCUIt)

NF

Voo" + 15 V, RS - 270.\1

3.5

4.5

,8

f" 200 MHz, RG " 500

Ct.

Ci ~;S;~u~:a~:~:.able

all capaCItor: E.F. Johnson Type 160·102

C 3: 1-10 pF piston-type varrabte air capacitor:
01O,JohansonType433s,or eqUivalent.

JFD Type VAM-

C4: 0.3-3 pF pis.ton-type variable all capacitor: Roanwel! Type
MH·13 or eqUIvalent.
L 1: 5 tufOS silver-plated O.02~ thick, 0.07 '!0.08" Wide copper
ribbon.
Internal diameter of winding = 0.25"; winding
length approx.0.6S'! Tapped at 1-1/2 turns from Cl endof
Winding.
L 2: Same as Ll except winding length approx. 0.7"; no tap •

.. Pusle test. Pulse dUIa'tlon

<

20 ms, duty factor < 0.15.

• Capacitance between Gate No.1 and all other

ter~na!s.

... Thlee- TermInal Measurement With Gale No.2 and Source Returned to
Guard Terminal.
• Measured flom gate No.2 to source.

Fig. J _ 200 MHz power gain and noise ligure test circuit
lor type 3NJ40 .

438 _________________________________________________________________

3N140, 3N141
Q = 3N141.

----------l

ceramic.

'DISC

'Tubular ceramic.
All,eslstors irl ohms

All capaCitors In pF

Ct _ C2: ~;5;~u~:aIV:~Lable 311 capaCitor: E.F, Johnson Type 160·102

C3: Ji~~ Jo~a~i;at~nT~:ee 4~315~~',e e~l~i;:{)e~~:tor: J FD Type VAMC4: ~'~:i3 ~re~i~i~:I~~~.e variable air capacitor: Roanwell Type

L1:

~ib~~I;S S\~Vt~~~~~t~~a~'~!; t~:C~in~f:g '!O~080:2si~e w~~~j;~
length appcox.

O.65~

Tapped at 1.1/2 turns from Cl endaf

winding.
GATE No 2- TO-SOURCE VOLTS (V02s1

L 2: Ohmi!e Z·144 RF choke or equivalent.

L3: J,W. Miller Co, 114580 0,1 JJ.H RF choke or equivalent.

2701<

Note: If 500 meter Is used in place of sweep detecto', a low pass
filter must be provided to eliminate local oscillator voltage

Fig.3 • IIF

YS

VG2S'

from toad.

Fig.2 • Conversion power gain test circuit
lor type 3N14J.

,
OSCILLATOR INJECTION VQl.TAGE At GATE No 2 (VLol-VOLtS (rms)

Fig.S. GpS

Fig.4 - HF vs 'D'

YS

V G2S (Fo, 311140).

COMMON-SOURCE CIRCUIT,GATE NO.1 INPUTt:;B '
AMBIENT TEMPERATURE \TAI'2~·C~
[
OAAIN-TO-SOURCE VOLTS (VOS ('13
GATE NO,I-VOLTAGE ("tIS 1 IS AOJUSTEO
FOR 10 '10",A WHEN VG25'4 V
GATE No,2 AT AC-GROUND POTENTIAL

~

~

Fig.6. GpS(C)

YS

V LO (Fo, 311141).

COMMOH-SOURCE CIRCUT
AM81ENT TEMPERATURE (TAI'2:5'C
F"R[QUENCY If). 200 MHz
OiliAIN MILLIAMPERES (ZO)'S
GATE No. 2-Ta-SOURCE VOLTS ("t2SJ·-t4

",

10

'"

75

i

GAlE No,2-l0-SO~CE
'lOLlS lVG2Sl --(

°-2

i=rt

J=h

t,

~~1

:ti

-I
0
I
GATE No 1- TO-SOURCE VOLTS IVOlsl

Fig.7 "0

Ys

......

2

°-,

-3

-2

-I

a

I

2

3

GATE No.2-TO-SOURCE VOloTS ('0'025'

V G1S '

Fig.S "0

Y' VG2S'

5

I~

10

DRAIN-tO-SOURCE VOLTS (VOS)

Fig.9 - Yjs vs VDS'

CQNMON-SOURCE CIRCUIT
AIIIISIENT TEMPERATURE (TAI'2"C
fREQUENCYII)'2:aaMH,
DRAIN MILLIAMPERESIIOI.S
GATE No.2-tO-SOURCE VOLTS{VG2S1·4

,0' _ __

Hi-t

-'0

a

6
1
8
9
10 II
IZ
ORAIN-TO-SOURCE VOLTS (VOS'

Fig.JO. Yos vs Y DS '

I~

14 IS

5
10
DRAIN-TO-SOURCE VOLTS(VOS)

Fig.1J - y(s vs YDS'

,

'0

DRAIN-TO-SOURCE VOLTS (Vosl

Fig.J2 - Yrs vs VOS'

_____________________________________________________________________ 439

3N140, 3N141
-i~~~EON\-~~~RNR~i~~~'1TA1'25'C
FREQUENCY (t J. 200 MHz
ORAIN-TO-SOURCE VOLTS IYOS)-15

GATE NO. 2-10-S0URCE VOLTS I"G2S}'4

o

±:±±±±::±

b"

0.'

~

10

DRAIN MilLIAMPERES (ICI

i

of-

·00

15

o

•

'0

DRAIN MilLIAMPERES lIe)

DRAIN t.lILLIAMPERESIIOI

Fig. 13 • Yis vs 'D-

Fig.14 -

YOS 'IS

Fig.1S - r(s vs 'D'

'D'

COMMON-SOURCE CtRCUIT
AMBIENT TEhlPERATURE lTA)'2S'C

FREOUENCY IIl'200MHl
DRAIN-TO-SOURCE VOLTS (VOS}-15

GA~E No 2-TO~50URCE ~LTS ;"G251'4

'"
'"
I ~
. . . 1"0 5

}
•
00
DRAIN MILLIAMPERES IIOI

Fig.16 • rrs

'1$

,

GATE NO.Z-TO-SOURCE VOLTS (V GZS '

'D-

Fig.17 - ris

'IS

V G2S '

Fig.18 -

Yos vs

VG2S '

COhlNON-SOURCE CIRCUIT

i :::~~~~CYIfl'200 MH~·'"
E """"

DRAIN-TO-SOURCE VOLTS

·c

(vas)' 15

GATE No.I-TO-SOURCE VOLTS (VGIS}·-D.6

,",BIENT TEMPERATURE (TAl' 2S"C
FREQUENCY If). zoo MHz
.ORAIN-TO-SOURCE VOLTS Iv OS! - 15
GATE NO.I-TO-SOURCE VOLTS (vGIS!- -0.6

",

o

Fig.19. Y(,

y, VG2S'

F;g.20 - Yu vs VG2S'

,

"

I!
i
GATE No.I-TO-SOURCE VOLTS (VG1S)

Fig.22. g(S ys VG1S '

•

GATE No Z-TO-SOURCE VOLTS ('tZS!

GATE No.2-TO-SOURCE \lOLTS (VGlSI

GATE NO. 2-TO-SOURCE VOLTS (V G2S '

Fig.21 . g(s and'O

YS

VC2S'

,
~'R

,,~

~ .,

,

JR"

',0"' _,~:' ,

.~ ~~'~):
..

-

,0,1,"'~

E--I

GATE HO. Z'TO-SOURCE VOLTS IVGZSI

F;g.23 • g(,2

y,

VG2S'

MO _______________________________________________________________

3N142
Silicon MOS Transistor

Performance Features

N·Cha,n.'D•• Ie".,T,••

• Large dynamic range
• Enhanced signal-handling capability for low
cross-modulation
• Dual-polarity gate permits positive and negative
swing without degradation of input impedance
• Reduced spurious responses in FM receivers
• Permih use of vacuum·tube biasing techniques
• Excellent thermal stability for critical oscillator
designs

For Industrial and Military Applications to 175 MHz
The-3N142 is a silicon. insulated-gate ficld-cffect
transistor of thl' X:-channel depletion t,VPl' utilizing the
MOS· construction.
The-3N142 is intended primarily for use as thC' rf
amplifier in FM receiv('rs and general ampiifi("r applications at frequencies up to 175 MHz.

MOllimum ROlings, Abso'u'~·Mollimum \'alun Gil

* DRAIN·TO-SQURCF.
VOLTAGE.

"w.

·20

,. DRAIN· TO·GA TE
VOLTAGE, VU!;

·20

Device Features

VOLTAGE, "f;!>:
Continuous ... ,

mcx:lulation effects in AM receivers and .minimizes the
generation of spurious fC!sponses in FM receivers.

PI'lik Ill'

,.

. . . . . . +1 to-8
'15

•••••••

,. DRAIN CURRENT. lu

........

50

\"

High input resistance - 1000 megohms
Low feedback capacitance - 0.35 pF max.
Low noise figure - 2.5 dB typo
High useful power gain neutralized - 16 dB min. at 100 MHz
• Hermetically sealed TO - 72 metal packago

•
•
•
•

mA

*TRANSISTOR DISSIPATION, PI':
At ambient 1 up to 25'C • . . . . . aao
mW
temperatures / above 25~C ...•.. Derate at 2.2mW/"C

Applications

*AMBIENT TEMPERATURE
RANGE:
Storage . . . . • . . , •..•... , •. -li5 to +175
Operating ...... , , .. , '
-li5 to + 175

• RF amplifier, Mixer, and Oscillator in:
CB and Mobile Communication Receivers
Aircraft and Marine Receivers

CATV and MATV Equipment
•
•
•
•
•

,.
,.

* GATE·TO·SOURCE

The wide dynamic range of the 3N142 reduces l'ross-

• ~tal-Oxidc-Semiconduclor

r .. = 2SGlC

TERMINAL DIAGRAM

~
~

.C
"C

'" LEAD TEMPERATURE

(During Soldering):
At distances ~ 1132" from seating
surface for 10 seconds max. • • .• 265

Industrial Control Circuits
Variable Attenuatars
Current Limiters
Instrumentation Equipment
High-Im,pedance Timing Circuits

~C

* In accordance with JEDEC RegiAlrEltion Datu r~ormnt JB-9
RDFIl-8

LEAD \LEAD '1.
LEAD 3·
LEAD4.

ELECTRICAL CHARACTERISTICS, (At TA ·25· C)

..

Measured uith Suhstrate Connf'dC'll to Sourct' L'nil'ss Olh('fldsf'

DRAIN
SOURCE
INSULATED GATE
BULK (SUBSTRA1El AND CASE

~rC'i{i('cl

LIMITS
CHARACTERISTI CS

SYMBOLS

CONDITIONS

UNITS
Mm,

Gale Leakage CUrlen!

VOS ° O. VGS " ·6 V. TA - 15° C
VOS,O. VGso·6V. Trl150C
.VOS - O. VGS . d. TA -15° C
VOS -0. VGS -'1. TA -115° C
VOS - 15 V. VGS - a
VOS 10 V. VGS ··6 V

IGSS

Zero·Bias Drain Current··

T,p.
0.0001
0.0001

Max,

I
100
I
100

15

nA
nA
nA
nA
rnA

50

J-'A

5

15

VOS 15 V. 10 50 .. A
VOS - 15 V. 10 5 rnA. I I kHz
VOS - O. VGS . O. I·· I kHz

·0.5
5000

·3
1500
200

·8
11.000

Crss

VOS' 15 V. 10" 5 rnA. I 00.110 I MHz

0.10

0.22

0.35

CISS

VOS - 15 V.ID 5 rnA. I . 0.1 10 I MHz

5.5

1

Input Admitlance

Vis

Common Source ConfiglJ'ation

Forward Transfer Admittance

Yls
Yas

lOSS

Drain·to-Source Cutoff Current

101011\
VGS(ofO

Gale-to·Source Cutoff Voltage
Forward Transconductance
Drain-to-Source Channel ReSistance

ils
rOs(onl

Shorl·Circuit
t
Reverse Transfer Capacltcrrce
Small,Slgnal Shorl,Clrcultlnpul Capacitance
~mall·Signal

Output Admiltance

I" 100 MHz
VOS" 15V
10" 5 rnA

(Fixed Neuhali"li,.,)

Int~i~~ :e:r~rli~:;r;)

Gps

NF

pF

0.21< JO.9

mmho

·I
· I'

I.
I.

mmho

dB

11

dB

16
VOS" 15 V. 10 "5 rnA. f -100 MHz

pF

mmho

VOS - 15 V. 10 . 5 rnA. 1-100 MHz

Noise Figure ....

4mho
II

• 1 0.155.J3.451 •
1.5-JO.9

~
MUG

Maximum Available Power Gain
Maximum Usable Power Gain

V
r

2.5

4

dB

t

* In accordance with JEDEC Registration Data Formal JS-9 RDF-llB

Three-Terminat Measurement: Source Returned to Guard Terminal
**See Fig. 1

r--- - --- ---- -- -~EXTEANALsHiilO--~-----l
I

I
II

:

NI
HZ

Cz

I
I

N, .OOHfOUTPUT
500 LOAD

•

I

,

,

T
I
I

I
I
I

,

L ____________ ...J ________

~e!---..J

Tt Nt = 6 Turns.20 Tinned CopparWire;}f,"
Co = 205, Nl/N2 = 4.85

I.D.~"

Long

T2 N1 + N4 = 6:Ko Turnsw,zO Tinned Copper Wire %," 1.0.'1 lijLong
Co= 190N,JN2= 1.9 N,/Na",2,3 Nl/N4=B
C, = 10 pF Variable Air Capacitor IHammarlund Mac·tO or Equivalent!
C2" 5 pF Variable Air Capacitor IHammarlund Mac-5 or Equivalent)
g3: ~~;~~F Piston-Tvpe Variable Air Capacitor IErie 535e or Equivalentl

+16V
92CS-17034

Fig. 1 - Test Set Up for 100 MHz Insertion Power Gain and
Noise Figure

For characteristics curves, refer to types 3N128 and 3N143.
_____________________________________________________________________
441

3N152
Silicon MOS Transistor

Features

N-ChaMel Depletion Type

• low gate leakage current -

IGSS • 0.' pA typo

For Low·Noise R F Applications in Military &
Industrial VH F Communications Equ ipment
Operating up to 250 MHz

• low feedback capacitance Crss '" 0,25 pF typ,
• High forward transconductance gfs '" 7500 pmho typo

RCA·3NI52 is an N-channel depletion-type silicon insulated
gale field-effect transistor utilizing the MOS· oonstruction.1t
is intended primarily for VHF amplifier applications up to
250 MHz in military and industrial equipment.

• High vhf power gain GpS'" 16 dB typo at 200 MHz
MaKimum Ratioi5, Ab$olut~Maximum Values at TA'" 25°C:

Because of its improved transfer characteristic and exceptionally wide dynamic range, the JN152 with the
better cross-modulation performance in linear amplifier
applications than conventional bipolar transistors. The insulated gale with its extremely low reverse (leakage) current
eliminates the problem of diode-current loading of the input
circuit under sirong 'input conditions, which is common to
junction·type FEr's. These features in ::Iddilion to low
feedback capacitance permit the design of circuils providing
superior high-frequency operation and high gain without
neutralization. The 3NI52 utilizes full·gate construction and
is hermetically sealed in a JEDEC TO-72 metal package.

,. DRAIN·TO-SOURCE VOLTAGE. VOS
+20 max.
V
*DRAIN·TO-GATE VOLTAGE. VOG
+20
V
*GATE·TO-SOURCE VOLTAGE, VGS:
.... +1,·8max.
V
CONTINUOUS (del
±IS max.
V
PEAK al.:
50max. rnA
• DRAIN ('URRENT, ID .
TRANSISTOR DISSIPATION:
At ambient {up to 25°('
........
330 max. mW
tempcratureshbove 25°C .............. derate at 2.2 mW/oC
*AMBIENT TEMPERATURE RANGE:
·6510+175 0 C
Storage ...
-6510+175 0 C
Operating ..
LEAD TEMPERATURE (During Soldering):
At distances not elmer than 1/]2 inch to
265 max. °c
seating surface for 10 seconds ma.ximum

• Melal-O\ide·Semiconductor.

* In accordance with Jedec Registration Data Fonna! J5-9 RDF II·B .

substrate in the reversed nias mode call provide substantially

• Low vhf noise figure NF '" 2.5 dB typo at 200 MHz
• Exceptionally good cross-modulation characteristics

*

*

Performance
• Large dynamic range
• Greatly reduced spurious responses
• Permits use of vacuum-tube biasing techniques
• Excellent thermal stability
• Superior cross-modulation performance and greater
dynamic range than bipolar transistors

ELECTRICAL CHARACTERISTICS AT TA· 25°C
Measured with Substrate Connected to Source Unless Otherwise Specified

CHARACTERISTICS

*

LIMITS

I!

SYMBOLS

r-~;::;::::]~E'~5~2::::~

CONOITIONS

Tvp

Max

200

*

Zero-Bias Drain Current
Drain-t~-Source

Gate-to-Source-Cutoff Vottage

-II

Forward Transconductance

15

1VOS'15V,VGS'O

lOSS

Cutoff Current

*

TERMINAL ARRANGEMENT

UNITS

0.0001

G.lte Leakage Current

30

VOS ':;0 v. VGS' ·8V

Vos

Drain·to-Source Channel Resistance

15V,IO'5ml>.,l·lkHz

5000

7500

0.15

0.25

5 rnA. I

VOS . 15 V.IO

Small-Signal Short-Circuit Input Capacitance

C'H

VOS

__

Output Admiltance

Ya~

Power Gain
Maximum Available Gain

Cammon

MAG

10

01 to 1 MHz

Sau.c~

0.35

55

15 V, 10' 5 rnA, I - 0 1 to 1 MHz

~'~"P~"~tA~d~m~it_,,~",_,~~~____-+~y~,,~ ~1 100MHI
"F:-O_'W.:'..:'d.:T..:".:",.:".:'"Ad:..m...".:".:"'_'____-+-:y.:','--__-! VOS 15 V.

12,000

"mho

200

VOS - O. VGS - 0, I - 1 kHz

.. Small-Signal Shon-Circuit
Reverse Transfer Capacitance""

"I>.

·0.5

~50"A

VOS ·15 V.IO

Of,

50

~
~

1 ·O.a,n

2·

Sour<::e

3-

In~ujoted Gate

4 - Bulk (SubsrrOle)
ond Ccse

OF

Can"9\.1rat,o"
0.4 • J73
7·J1

0.<'8 ' Jl.8

5 rnA

21

10

Insertion Power Gain (Fixed
Neutral~zationl See Fig.1

Vos

15 V.

5 rnA.

Noise Figure (See Figs. 1 & 2)

Vos

15 V. 10

I :200

5 rnA. I

MH(

14.5

d8

'6

:200 MHz

"

.. Three·Terminal Measurement. Source Returned to Guard Terminal .
• In accordance with JEDEC Registration Data Format JS·9 RDF-, 1 B.

r-------------j------------i
Fig, 2 - Noise figure measurement setup.

l

JPI 05*

I

I

I

:
:

1

\

Q I

'

C5 OUTPUT

CgA~

=
LI

,
I
I

c.

INPUT
100"
50!!$--!
GEN ~

I

I
I
I

T 41K
I

Cl. C2:
C3:

I

I

I
I
I

~6~MITE TYPE

I

:
Z235 OR EQUt" 1 :

~XTERNAL-1

,L __ _

SHIELD
I
I
~-- __ -L------- ~ ____ ~

C4, C5:

L,·

L2:

1.5-5 pF variable air capacitor: E. F. JohnSOn Tvpe 160-102
or equivalent
'-10 pF piston·type variable air capacitor: JFO Type
VAM.()10. Johanson Type 4335, or equivalent
0.3-3 pF piston-type variable air capacitor: Roanwel1 Type
MH·13 or eQuivalent
5 turns silver·plated 0.02" thick, 0.07"-0.08" wide copper
ribbon. Internal diameter of winding = 0.25"; winding
length approx. 0.65". Tapped at 1·,/2 turns from C1 end
of winding
Same as L1 except winding length approx. 0.7"; no tap

Q.3H1SA

Anlh.;.'"ni.ohlMo"", \'4W
",,1.nolh""'''''lOCi''.~

All Co,.IV

10 (011 )

VGSo-BV,VOs c dV,TA 0 15 0 C
VGF·BV,VOSodV, TA cl1S oC

0.1
0.1

Crss

VGS c·6V, VOS oOV, 101 MHz
VOS clSV, 10 oS rnA, I c 1 MHz

Ciss

VGS

IGSS

Cds

10 9

, - Drain

2 - Source

3 - Insulated Gate
4 - Bulk (Substrate)
and Case

n

lola

SUBSTRATE cOHNEcrEO TO SOURCE
AMBIENT TEMPERATURE ITA 1'2~'C

=·BV, Vas ° OV,

I ° 1 MHz

1
1

nA
"A

0.34

O.S

0.25

0.38

pF
pF

6

B

pF

Vas cOY, VGS c·BV, 101 MHz

3

pF

••

:! 20

~

"

i

10

~

2

-,

•,
Z

·~2

-.-,

~

gls

VGS c OV, VOS c d5V

Va

VGS c '6,BV; Vas oOV

10,000

J-l.mho
!I

10

DRAiN-TO-SOURCE VOlTS

011501 Voltage

O'

V

I!I

20

!Vos'
UCS-1494S

Fig.' - Drain current vs. Jrain-fo-source voltage .

... In measurements of Offset Voltage, thermocouple effects and contact poten.tials in the measurement setup may cause erroneous readings of
1 micr~volt or more. These errors may be minimized by the use of solder haVing a low thermal e.m.f., such as Leeds & Northrup No.107-1.0.1,
or eqUivalent.
SUBSTRATE CONNECTED TO SOURCE
DRAIN-TO-SOURCE VOLTS (VOS'''·I
AMBIENT TEMPERATURE !TA)';ZS'C

DRAIN-TO-SOURCE MILLIVOLTS (Vos'

Fig.2 - Low-level drain current
vs. drain-fa-source voltage.

Fig.3 - Drain-fo-source static resistance
vs. gate-fa-source voltage.

_____________________________________________________________________ 443

3N154
Silicon MOS Transistor

Device Feature:

N-Channel Depletion Type

For Critical Amplifier Applications in Military & Industrial
VH F Communications Equipment Operating up to 250 MHz
RCA 3N154 is an n-channel depletion-type silicon
insulated-gate field-effect transistor utilizing the MOS·
construction. It is intended primarily for vhf amplifier
applications up to 250 MHz in military and industrial
equipment.

Because of its improved transfer characteristic and
exceptionallywidedynarnic range, the 3N154 can provide
substantially better cross modulation performance in
linear amplifier applications than conventional bipolar
transistors. The extremely low gate leakage current
eliminates diode-current loading of tile input circuit
under strong signal conditions, a problem which is common
to junction-type FET's. These features, in addition to
low feedback capacit.ance. permit the design of circuits
providing superior high-frequency operation and high gain
without neutralization. The 3Nl54· utilizes full-gate
construction and is hermetically sealed in a JEDEC
TO-72 metal package.
• Metal'Dxide-SemiconductOl

Mo)(imum Rolings, Absolute-.\Iaximum Values at T A

= 2.5°C:

v

'20

.DRAI~-TO-SOVRCE

VOLTAGE. VDS ' ..••
.DRAlN-TO-GATE VOLTAGE. Voo·
.GATE-TO-SOURCE VOLTAGE, Vas:
•
CONTINUOUS (del •..••...•••••••
•
PEAK ac • • • • • • • • . • • • . . • • . . . . .

t

.20

v

1,-8

v

± 15

V

.DRAIN CURRENT. '0'" . . . . . . . . . . . . . .
50
rnA
*TRA~SISTOR DISSIPATION:
At ambient
up to 2SoC • • • . . . • • • . •
330
roW
temperaturesf above 25°C •.••.••• derate at 2.2 mW/uC
.. AMBIENT TEMPERATURE RANGE:
Storage. • . . • • • . • • • • • • • • . • • • • •• ~5 to + 175°C
Operating • • • • • • . • • . • • • • • . • • • •• -65 to t 175°C
LEAD TEMPERATURE (During Soldering):

t

Z!a~t~~a~~~:a~~tf~;~Oe~!~~~d~~~~~~~o •

265

IGSS

Zero-Bias Drain Current

lOSS
10(off)

Gat~to·Source

Cutoff Voltage

VGs(ofO

Forward Transsconductance

gfs
'oS 1/32 inch from seating
surface fOf lOseconds max. . . . • . . . . . . . . . ..

• aircraft, marine ond vehicular receivers

• CATV and MATV equipment

• high forward transconductance - gh :::: 7000 ~mho min.
• high unneutratized RF power gain - Gps = 16 dB min. at 200 MHz
• low vhf noise fjgur. - -

NF = 3.5 dB max_ at 200 MHz

°c

TERMINAL DIAGRAM
265 0 C

~

• telemetry and multiplex equipment

ELECTRICAL CHARACTERISTICS, at T A = 250 C unless otherwise specified
liMITS
CHARACTERISTICS

SYMBOLS

TEST CONOITIONS
Min.

Gale-No.Ho-Sour" Culoff Vollage
Gale·No.2-lo·Source Culoff Vollage

Gate-No.1-Leakage Current

Gate·No.2-Leakage Current

Zero· Bias Drain Currerlt
Forward Transconductance

(Gale-No.1 ·Io-Orain)
Cutoff Forward Transconductance

(Gale-No.!-Io-Ora in)
Small-Signal, Shorl-Circuit
Input Capacitance'
Small-Sigrlat, Short·Circuit, Reverse Transfer
Capacitance (Drain·to-Gate No.1)'

Small-Signal; Shorl-Circuil
Output Capacitance
Maximum Usable Power Gain

(See Fig.! for Measurement Circuil)
Measured Noise Figure
(See Fig.! for Measurement Circuit)

VG1S(Offi
VG2S(off)

IGlSS

IG2SS

.

lOSS
gfs

gls(off)

VOS" .16V, 10 " 200 "A
VG2s " .4V
VOS" d6V, 10 " 200 "A
VGIS" 0
VGIS "-20V, VG2S "0
VOS" 0, TA" 25°C
VG1S " tlV, VG2S "0
VOS" 0, TA " 25 0 C
VG1S "·20V, VG2S "0
VOS" 0, TA" l25 0 C
VG2S "·20V, VG1J "0
Vns " 0, T "25 C
VG2S "tI,VOS"0
VG1S " 0, TA " 25 0 C
VG2S "·20V, VG1S "0
VOS" 0, TA" l25 0 C
VOO " .14V, VG1S "0
VG2S" t4V
VOO" d4V, 10 "10 rnA
VG2S " t4V, f "I kHz
VOO" .14V, VGIS " -0.5V
VG2S " ·2V, f" 1 kHz
VOS " t13V, 10 "10 rnA
VG2S " .4V, f" 1 MHz

3NI59
Typ.

UNITS

-2

-4

V

LEAD
LEAD
LEAD
LEAD

-2

-4

V

I

Max.

1

nA

1

nA

0.2

"A

1

nA

'

,

r

,
I

,,
~---~.Q-.l---1:_------J

1

nA

0.2

"A
;:- o"----V':'"""'O(~~51

5

18

30

rnA

7000

10,000

18,000

,umho

100

p.mho

5.5

7

pF

0.01

0.02

0.03

pF

MUG

VOO " t15V, RS "270D
RG "SOD, f" 200 MHz

16

NF

VOO" t15V, RS" 270D
I " 200 MHz, RG " SOD

Cos s

1"--------:-- -- - - - - -- - - 1

I

3

Crss

M

DRAIN
GATE No.2
GATE No.1
SOURCE, SUBSTRATE AND CASE

I

VOS" ,13V, 10 "10 rnA
VG1S " .4V, f "I MHz
VOS "tI3V, 10 " 10 rnA
VG2S " '4V, f " I MHz

Ciss

12'
34-

VAGC~

• Tubularceramic
,. Disc ceramic
/I Ferrite bead (1/2 used): Indiana General No. H 1742C-{A'147) or
F1l57-1·H or equivalent.
t VHF plug In socket Jettron CD72·148and C072149(part No.7977·1)
01 equivalent.
Cl'

pF

2.2
18

22

dB

2.5

3.5

dB

CZ:

1.5·5pF variable air capacitor: E. F. Johnson Type 160·102
or eQuivalent.
Cr 1'10 pF piston·type variable all capacllor: JFO Type
VAM·OlO. Johanson Type 4335, or Equivalent.
Cf 0.3-3 pF piston·type vallallie air capaCitor: Roanwell Type
MH·13 01 equivalent.
L}: 5 turns sllver·plaled 0.02" thick. 0.07"·0.08" wide copper
ribbon. Internal diameter of wiooing = 0.25": wmdmg
length approx. 0.65". Tapped at 1·1 2 turns from CI end
of winding.
Lz: Same as Ll excepl wlndmg length approx. 0.7": no tap .

• Pulse Test: pulse duration < 20 ms, duty factor < 0.15 •
.. Capacitance between Gate N;l and all other termi-;;als.
• Three-Terminal Measurement with Gate No.2 and Source Returned to Guard Terrrinal.

For characteristics curves refer to types 3N 140, 3N141.

Fig.1 - 200-MHz power gain and noise-ligure test
circuit lor type 3NJ 59.

__________________________________________________________________ 445

3N187
Silicon Dual Insulated· Gate Field· Effect Transistor
N-Channel Depletion Type

Device Features
• Back-to-back diodes protect each gate against handl i ng and in-ci rcuit transients
• High forward transconductance - 9fs = 12,000 ",mho (typ.)

With Integrated Gate-Protection Circuits
For Military and Industrial Applications up to 300 MHz

RCA-3N187 is an n-channel silicon, depletion type,
dual insulated-gate field-effect transistor.
Special back-t<>-back diodes are diffused directly into
the MOS· pellet and are electrically connected between
each insulated gate and the FET's source. The diodes
effectively bypass any voltage transients which exceed
approximately flO volts. This protects the gates against
damage in all normal handling and usage.
A feature of the back-lo-back diode configuration is
that it allows the aNlS7 to retain the wide input signal
dynamic range inherent in the MOSFET. In addition, the
junction capacitance of these diodes adds little to the
total capacitancc shunting the siJ:::nal gate.
The excellent overall performance characteristics of
the RCA-3N187 make it useful for a wide variety of rfamplifier applications at frequencies up to 300 MHz.
The two serially-connected channels with independent
control gates make possible a greater dynamic range
and lower cross-modulation than is normally achieved
using devices having only a single control element.
The two-gate arrangement of the 3N187 also makes
possible a desirable reduction in feedback capacitance
by operating in the common-source configuration and acgrounding Gate No.2. The reduced capacitance allows

~~~ ~~n:~t~f!~Z~i~U~: ~o;.~r d~~t~;)~\~~O 1JH~B(tyP.)

:

operation at maximum gain withoul nellfra/io:alion; and,
of special importance in rf-amplifiers, it reduces local
oscillator feedthrough to the antenna.
The 3N187 is hermetically sealed in the metal JEDEC
T{}-72 package.
.6

Metal-Oxide-Semiconductor

Maximum Ratings,

:1 bsolu.le-Maximum ralues, at T A :::2So C
DRAIN-TO-SOURCE VOLTAGE. VDS' ... --0.2 to +20
GATE No. I-TO-SOURCE VOLTAGE, Y CIS :
Continuous (dc) •••••.•.••••.••• -6 to +3
Peak EtC • • • • • • • • • • • • • • • • • • • • • -6 to +6
GATE No. 2-To-SOURCE VOLTAGE. VG2S !
Continuous (dc) ••.•.••••••.• -6 to 30% of V DS

P_oc . . . . . . . . . . . . . . . . . . . . .

~~M

v

Applications
• RF amplifier, mixer, and IF amplifier in military, and
industrial communications equipment
• Aircraft and marine vehicular receivers
• CATV and MATV equipment
• Telemetry and multiplex equipment
Performance Features
• Superior cross-modulation performance and greater
dynamic range than bipolar or single-gate FET's
• Wide dynamic range permits large-signal handling
before overload
• Virtually no agc power required
• Greatly reduces spurious responses in FM receivers

v

TERMINAL DIAGRAM

v
V

... DRAIN-TO-GATE VOLTAGE.
V
V Dm OR VDG2 ••••.••.•••..•• +20
DRAIN CURRENT, ID • • • • . • • • • . • •• 50
rnA
>I: TRANSISTOR DISSIPATION P T !
rnW
At ambient }u p to 25°C .•.•••.•• 330
temperatures nbove 25°C •.••••• derute linearly nt
2.2 mW/oC
>I: AMBIENT TEMPERATURE RANGE:
Storage and Operating
-65 to +175
... LEAD TEMPERATURE (During Soldering);
At distances? 1132 inch from
seating surface for 10 seconds max.
265
°C

~

>I:

>I:

M

In accordance with JEDEC Registration Dutu Format
,18--9 RDF-}9A

-"C"),_'_,'O",),,., ",.'·Ca;~~;:~eJ:~.

~ DI;~l~:lamlt

at 200 MHz

LEAD
LEAD
LEAD
LEAD

l·DRAtN
2·GATE No.2
3·GATE No.1
4.S0URCE. SUBSTRATE
AND CASE

.

• Tubular ceramic.

GATE No. 2- TO-SOURCE VOLTS (vG2S)

Fig. 2_ NF vs. VG2S

Fiq. 1- 200-MHz Power gain and noise.figure test circuit

CO'-l"'ON SOURCE CIRCUll
AMBIENT TE'-IPERATURE (TA1'2!i-C

E~,r:~~~~~!~~~~i:t\;!~~f~:;:~~.+4

'0

'00
DRAIN MILLIAMPERES {lof

Fig. 3 - NF vs. I D

200

'00

000

FREQUENCY (f)-Mit'

Fig. 4- GpS

VS.

VG2S

Fig. 5- MAG. vs. f

446,_______________________________________________________________________

3N187
ELECTRICAL CHARACTERISTICS, at TA ;; 250 C unless otherwise specified

CHARACTERISTICS

SYMBOL

• Gate No. l-to-Source Cutoff Voltage

VGIS(oll)

• Gate No. 2-to-Source Cutoff Voltage

VG1S(011)

• Gate No. I-Terminal Forward Current

IGISSF

• Gate NO.1· Terminal Reverse Current

IGISSR

• Gate NO.2-Terminal Forward Current

IG2SSF

• Gate No.2-Terminal Reverse Current

IG1SSR

• Zero-Bias Drain Current

lOS

Forward Transconductance

ils

(Gate No. l·t,.Orain)

• Small-Signal, Short-Circuit Input Capacitance! Ciss
• Small-Signal, Slort-Circuil,
Reverse Transfer Capacitance
Crss

(Orain·t,.Gale No. I).

• Small-Signal, Sholt·Circuit Output Capaci lane
Power Gain (see Fig. I)
Maximum Available Power Gain
Maximum Usable Power Gain (unneutralized)

LIMITS
Min. Typ. Max.

TEST CONDITIONS
VOS" ,IS V. 10 "50 "A
VG1S ",4V
VOS" ,IS V. 10" 50 "A
VGIS "0
T "15 0 C
VGIS",IV
VG1S" VOS-O TA " 100 C
TA"150 C
VGIS "·6 V
VG1S "VOS"O TA"IOOoC
VG1S",6V
TA"150 C
VGIS - VOS-O TA-100"C
TA "150 C
VG1S-·6V
VGIS "VOS"O TA-100 C
VOS - ,IS V
VG2S",4V
VGIS "0
VOS",15V,lo"lOrnA
VG2S " ,4 V, I" 1kHz

NF
IYlsl

Phase Angle of Forward Transadmiltance

{!

Magnitude of Reverse Transadmiltance

IY"I

Angle of Re\lerse Transadmitlance

A"

Input Resistance

'iss

Output Resistance

ross

-4

V

-0.5 -1

-4

V

-

-

-

-.

-

-

-

-

IS

50
5
50
5
50
5

VOS " ,15 V.IO" 10 rnA
VG1S - ,4 V, I -I MHz

6.0

0.005 0.01

-

1.0
IS
10
20-

16

-

-

VOS " >15 V, 10 "10 rnA
VG2S"'4V,I"100MHz

3.5
12,000
-35
15
-15
1.0
2.S

Forward B",kdown Voltage:
Gate No. I

I'ullillitSSF
v(BR)G1SSF

Gate No. I
Gate No.2

IitBR)GISSR
v(BR)G1SSR

Gate-Io-Source
Reverse Breakdown Voltage:

"Limited only by practical deSign consldelatlons.
t Capacitance between Gate No.1 and all other terminals
• Three·terminal measurement with Gate No.2 and
Source returned to ifound terminal.
• In accordance with JEDEC Registration Data Format JS.9 RDF·}9A

IGISSF "IG1SSF " 100 "A

6.5

IGISSR "tG1SSR "·100 "A

-6.5 -10

nA

50
5

nA
"A.
nA
"A

30

rnA

S.5

pF

0.03

pF

-

pF

22

dB
dB
dB

4.5

dB

-

.umho

-

kO

10

-I
0
I
GATE No. 1- TO-SOURCE VOLTS IVGlS'

Fig. 6. 'D vs. VGIS

o

!i

'0

l!i

ORAIN-lO-SOURCE VOLTS Nosl

Fig. 8- r;s vs. VDS

DRAIN-YO-SOURCE VOLTS IVosl
92CS-'47a~RI

Fig. 9 - ros vs. VDS

Degrees
,u.mho
Degrees

COMMI)tt-SOURCE CIRCUIT
AN,IENT TEMPERATURE ITAI'2S'C

kO

-

V

-

V

COMMON-SOURCE CIRCUIT,GATE No.1 INPUl
AMBIENT TEMPERATURE ITAJ'25-C
{)flAIN-TO-SOURCE VOLTS (VOS,"IS
GATE No.1-VOLTAGE ("GIS' IS AQJUSTED
FOR 10 -IO,.,A WHEN VG2So. V
GATE No.2 AT AC GROUND POTENTIAL

1$

~:~~N~~~~~~~~~~iJ~t~~TS

(VG2S js + 4

to
15
DRAIN-TO-SOURCE VOLTS IVosl

Fig. 10. rls vs. VDS

COlUl()l'.$OUJlCf aRCUIT
AMIIENTTOPfRAnlREfTAI 0 25· C
I'RfQUEMCl In 0 100 MHI
DlAlH ItIWAMPERES no! • 10
GATf NO. no-SOURCE VOLTS ('(02po'

...

.g ,

o
-2

06

OPERATING CONSIDERATIONS

~

No.2-l0-SOURCE
VOLTS lIJG2S)--1

, 0:

nA
"A

flexible leads of the 3N 187 are usually soldered to the
circuit elements. As in the case of any high.frequency
semiconductor device, the tips of soldering irons MUST
be grounded.

. '"

GATE

J'

The

AMBIENT TEMPERATURE ITA'025 °c
ORAIN-TO-SOURCE VOLTS (VOS'o!!!

"

10

"A

Gate-Io-Source

Gate No.2

~ ~"!I

CONMON SOURCE CIRCUIT
AMBIENT TEMPERATURE ITA~025°C
FR[OUENC'( (1)-200 MHr
ORAIN IoIILLIAMPERES 11010 10
taTE No 2-TO-SOURCE VOLTS IVGzsI' .. 4

1.2

7000 11,000 IS,OOO ,u.mho
4.0

Coss

Noise Figure (see Fig. 1)

-0.5 -1

5

GpS
MAG
MUG

Magnitude of Forward Transadmiltance

UNITS

-3

-2

-I

0

I

2

3

GATE No.2-l0-S0URCE VOLTS IVG25'

Fig. 7·'D vs. VG2S

,
ORt.lM-TO-SOURCE VOLTS IVop

Fig. J 1 - rrs

V$.

VDS

_____________________________________________________________________ 447

3N187
COMMON SOURCE CIRCUIT
AMBIENT TE"IPERATURE (TA"2!1eC
FREQUENCY(U'200 MHI
0 1.2 DRAIN-TO-SOURCE VOLTS (Vosl'IS
GATE NO.2-TO-SOURCE VOLTS NGzsl'+4

In

I

COMMON-SOURCE CIRCUIT
AMBIENT TEMPERATURE ITA}-2S·C
FREQUENCY 111'200 MHz
ORAIN-TO-SOURCE VOLTS NosI-IS
GATE NO 2 -TO-SOURCE VOLTS IVGZS}'4

t

i
j

!..

o

fO

i

lO

3 0 .8

0.'

o

10

15
hjILLIAMPERES- (IOI

ORAl'" MILLIANPERES (:tOI

DRAIN MILUAMPERESlIo)

fig. 12. Yis vs. '0

E
I

...~

o.ol

Fig. J3· Yos

COMIlOtOotJRCE CI~CUtT
J..IIBIENT TEIlPER"TURE(T.I.)' 150C
FREQUENCY(f). 2OOIIH,
DR.l.IN.TO.SOURCE VOLTS (VOSJ • 15

VS.

Fig. 14. Yis

10

COMIIIION-SOURCE CIRCUIT
AMBIENT TEMPERATURE ITA)' 25" C
1.2

GATE NO.l-TO-SOURCE VOLn(V

6~~~~~~8~s'dJR2l~LfsHi VOS)

-15
GATE NO,L -TO-SOURCE VOLTS I VGlS)·-06

' ..

12

10

~
>

j 0.5

~

1.. 0.4

YS.

'0

COhiMON-SOURCE CIRCUIT
AMBIENT TEMPERATURE {TAl' 25'C
FREQUENCY (fl· 200 MHz
DRAIN-TO-SOURCE VOLTS(VOS)·15
GATE 1II0.I-TO-SOURCE \,OLTSIVGU )·-0.6

i

'"

~o

tl

a~
Ii
i

'"

6"

0.3

'"

0.2

0,1

§
DR"'I'"

Fig.

~ILlI"IIIPERfS(lD)

,
GATE NO, 2-TO-SOURCE VOlTS (VG2 s1

GATE NO.2-TO-SOURCE VOLTS (VIiZ')

15- Yrs vs. '0

Fig. 17.

Fig. 16. Y;s vs. VG2S

COMMOtl·SO'JRCE CIRCUIT
AIIBIEIHTEIIPERATURE ITA)' 25°C
FREQUEtiCY (f). 200 MH.
ORAltI·TO·SOURCE VOLTS(VOS)' 15
SET Vcm FOR 10 _ 10 mA AT VC2S' 4 V

COMMON' SOURCE CIRCUIT
AMBIENT TEMPERATURE (TAl' 25'C
FREOUENCY {f} • 200 MHz

15 DRAIN-YO-SOURCE VOLTS (Vos) • 15
GATE NO I-TO-SOURCE VOLTS \ VOI,}'-Q,6

YO$ YS.

VG2S

.,
1.
:i

10.04

•

;

10 ~

4

'"

0,03

~

~ 0.02

6"

~ 0.01

.,
~

"'"
GATE tiD. 2-10_$OURCE VOLTS (VClS)

GATE NO.2-YO-SOURCE VOLTS I VGU I

Fig. J9. Yrs

Fig, ,18- Yis vs. VG2S

COMMON

YS.

Fig. 20·y;s vs.lrequency

VG2S

COIIIION SOURCE CIRCUIT
.t.IIBIEtiT TEMPER.t.1VRE(T.t.). 25"C
DRAIN· TO· SOURCE VOLT! (Vo~' IS

SOURCE CIRCUIT

AMBIENT TEMPERATURE (TA)'2S'C
DRAIN-YO-SOURCE VOLTS (IIOS'-15
CRAIN MILLIAMPERES (10,-10

200

FREQUENCY (tl- 111Hz

.

O,l

GATE NO.2-YO-SOURCE VOLTS !VG2sl'-+4

~:~~N ~~~~':'ci::.~g~l;O~~S(VC2S)"~

'"
'0

,o

8 0.2
~

,

'0

0.1

400
FREQUENCY

Fig. 27 -

Y05

(1)- "4Hz

vs. frequency

400

200
FREQlJENCY (t) -111Hz

Fig. 22 - Yfs

VS.

frequency

FREQUENCY (MH.)

Fig. 23.· rrs

YS.

frequency

448 __________________________________________________________________

3N187
COM.. ON SOURCE CIRCUIT
......IENT n"PUATURE IT...I-lS-C
FREQUENCY (fJ-lIctu

DR"'IN-lO-SOUlteE VOLTS (VOSle'5
GATE NQ2-TO-SOURCE VOlTS V.

1-+4

.,
.,

;::iOOI

~~

:.,

.,

000'

G... TE NO 2-TO-SOURCE VOLTS 1VOUI

Fig. 24· gl. anJ'D v.. VG2S

OATE NO.I-fO-SOURCE VOLTS (VGtS)

Fig. 25.• gl• • s. VGIS

GATE NO.2-TO-SOURCE VOLTS I"GZSI

Fig. 26. 91'2 ••. VG2S

__________________________________________________________________ 449

3N200
Silicon Dual Insulated· Gate Field· Effect Transistor
N-Channel Depletion Types

Applications

With Integrated Gate-Protection Circuits

e RF amplifier, mixer, and IF amplifier In military and industrial
communications equipment
• Aircraft and marine vehicular receivers
• CATV and MATV equipment
• Telemetry and multiplex equipment

For Military and Industrial Applications up to 500 MHz
RCA-3N200 is an n~hannel silicon, depletion type, dual
insulated-gate field~ffect transistor.
Special back-ta-back diodes are djffused directly into the
MOS peliet and are electrically connected between each
insulated gate and the FET's source. The diodes effectively
bypass any voltage transients which exceed approximately
:!:1Q volts. This protects the sates against damage in all
normal handling and usage.
A feature of the back-ta-back diode configuration is that it
allows the 3N200 to retain the wide input signal dynamic
range inherent in the MOSFET. In addition, the low junction
capacitance of these diodes adds little to the total
capacitance shunting the signal gate.

The excellent overall performance characteristics of the

applications at frequencies up .to 500 MHz. The two
serially-connected channels with independent control gates
make possible a greater dynamic range and lower crossmodulation than is normally achieved using devices having
only a single control element.
.

TERMINAL DIAGRAM

~
~

The two--gate arrangement of the 3N200 also makes possible a
desirable reduction In feedback capacitance by operating in
the common-source configuration and ac-grounding Gate No.
2. The reduced capacitance allows operation at maximum
gain without
neutralization;
and, of special importance in rf.amplifiers, it reduces local oscillator
feedthrough to the antenna.
The 3N200 is hermetically sealed in the metal JEDEC TO·72
package.

LEAD
LEAD
LEAD
LEAD

RCA-3N200make it useful for a wide variety ofrf-amplifier
Maximum RatinlP,Absolute·Maximum Values, at T A

=- 250C

v

CRAIN·TO·SOURCE VOLTAGE, VCS....
·0.2 to +20
GATE No.1·TO..sOURCE VOLTAGE, VG1S:
Continuous !de) .
·6 to +3
Peakac ........••..............
.s to +6
GATE NO.2·TO·SOURCE VOLTAGE, VG2S:
Continuous (dc). . . . . .. ... ..... ·6 to 30% of VCS
~k~................

* DRAIN·TO·GATE VOLTAGE,
VoG1 OR VDG2

........ .

:~~:~~I~~~=ED~~sl~ATION: p,.;'
~;;~~~:~:es ~~~ ~~~~

}

v

v

.sto~

+20
50

mA

330

mW

V

derate Ilnearlyat
2.2 mW/oC

* AMBIENT TEMPERATURE

RANGE:
Storage and Operating ..........
65 to +175
(During soldering):
At distances~1/32 inch from
seating surface for 10 $econd$ mall.
265

oc

* LEAD TEMPERATURE

oC

*In accordance with JEDEC registration data format (J5-9 ROF·19Aj

y and s Parameters

Performance

• Superior cross-modulation performance and greater
dynamiC range than bipolar or single-gate FET s
• Wide dynamiC range permits large-signal handling
before overload
• Dual-gate permits simplified agc circuitry
• Virtually no agc power required
• Greatly reduces spurious responses i(1 FM receivers

Device Features
• Back-la-back diodes protect each gate against
handling and In-circuit transients
• High forward transconductance -

~i~; u~~'2~~a~I~~~ ~P'~ower gain -

•

~ 1~'~~~tJ~na~o60~~~z

G ps
• Low VHF noise figure - 3.9 dB (typ.) at 400 MHz

3.0 dB (typ.) at 200 MHz

VS.

Frequency

=

SYMBOL

Maximum Available Power Gain
Maximum Usable Power Gain (Unneutralized)'
Y Parameters

MAG
MUG

Input Conductance
Inpul Susceplance
Magnitude of Forward Transadmittance
Angle of Forward Transadmittance
Outpul Conductance
Outpul Susceptance
Magnilude of Reverse Transadmittance
Angle of Reverse Transadmittance
SParameters

gis
b,s
I Yfsl
LYfs
gos
bas
I Yrsl
LYrs

Magnilude of Input Refleclion Coell.
Angle of Inpul Reflection Coell.
Magnitude of Forward Transmission Coell.
Angle of Forward Transmission Coell.
Mangilude 01 Oulput Reflection Coell.
Angle 01 Oulput Reflection Coefl.
Magnilude of Reverse Transmission Coefl.
Angle of Reverse Transmission Coefl.

sisl
LSis
_I sfsl
LSfs
ISosl
LSos

----

-LImited only by practical desrgn conSiderations

I

ISrsl
LS rs

4-S0URCE, SUBSTRATE
AND CASE

Features

TEST CONDITIONS: Draln.to-Saurce Yo Its (YDS)
15, Dlaln Milliamperes (10)
Gate No. 2-to·Source Volts (V G2S) = 4

CHARACTERISTICS

1 -DRAIN
2-GATE No.2
3-GATE No.1

All resistances in ohms
All capacitances in pF

=10,

FREQUENCY (MHz)
400
300

C l , C2: 1.3-5.4 pF valiable air capacitor:

UNITS
500

100

100

31
32

24
24

17.5
17.5

13
13

10
10

O.B
5.B
15.3
-15
0.3
2.7
0.025
- 25

2.0
B.5
15.4
-35
0.5
3.6
0.06
0

3.6
11.1
15.5
-47
O.B
4.15
0.14
14

6.2
15.5
16.3
-60
1.1
5.0
0.26
20

0.25
3.4
15.3
-15
0.15
1.5
0.012
-60
0.97
-10
1.50
153
0.9B5
-7.5
0.001
100

0.90
-32
1.40
133
0.95
-16
0.0015
115

0.B4
-55
1.15

111
0.93
-12
0.005
141

O.7B
-6B
1.1
90
0.92
- 2B
0.010
150

0.70
-B2
0.9
70
0.91
- 34
0.0165
142

dB
dB
mmho

mmho
mmho
degrees
mmho

Hammerland Mac 5 type or
equivalent
1.~l3.8 pF va.iable air capacito.:
Hammerland Mac 15 type or
equivalent
C4: Approx. 300 pF 'capacitance form·
ed between socket cover & chassis
CS: 0.8-4.S pF piston type variable
air capacitor: Erie 560-013 or
equivalent
L 1,L2: Inductance to tune cilcuit
C3:

Fig, '1 - 400 MHz power gain and noise figure test

circuit

AII8!ENTTEIIPU.IoTUREfTA)-2S"<
DRAlN·TO·\OIJRCE VOLTS(VOS1·1S

mmho

mmho
degrees

degrees
degrees
degrees
degrees
fig. 2-ID

YS.

VGIS

450 ____________________________________________________________________

3N200
ELECTRICAL CHARACTERISTICS
rA = 25°C

LIMITS
SYMBOLS

of

TEST CONDITIONS

un/•• , o.tIt.rw;s. specified

Max.

VGI~oln

VOS· + 15 V, 10 = 5Ol"A
VG2S=.+4V

-0.1

-I

-3

Gate No. 2-to-Source Cutoff Voltage

VG2~01n

VOS = +15 V, 10 =5Ol"A
VGIS = 0

-0.1

-I

-3

IGiSSF

TA =25°C
VGlS=+IV
VG2S = VOS" 0 TA= JOOoC

IGlSSR

VGIS=-6V TA = 25°C
VG2S=VOS=0 TA = 100°C

-

IG2SSF

TA = 25°C
VG2S = +6V
VGIS =VOS =0 TA = 100°C

Gate No.2-Terminal Reverse Current

IG2SSR

TA = 25°C
VG2S=-6V
VGlS = VOS =0 TA= 100°C

-

-

Zero-Bias Drain Current

lOS

VOS = + t5 V. VGIS =0
VG2S=+4V

0.5

5.0

Gate No. I·Terminal Reverse Current
Gate No. 2·Terminal Forward Current

Forward Transconductance
(Gate No. I·to-Orain)
Small·Signat, Short·Circuit Input
Capacitance 1

-

Reverse Transfer Capacitance

erss

Small-Signal, Short·Circuit Output
Capacitance

Coss

Power Gain (see Fig. I)

GpS

Noise Figure (see Fig. I)

NF

Bandwidth
Gat..to-Source Forward
Breakdown Voltage

BW

VOS=+15V
10 = 10mA
VG2S=+4V

f = I MHz

V(BR)GISSF

tGISSF =
tG1SSF = VG1S = VOS' 0

Gate No.1

V(BR)G1SSF

loo~A

Gate No. I

V(BR)GISSR

tGISSR =
tG1SSR = VG1S=VOS=0

Gate No.1

V(BR)G1SSR

-'n .tICCCrdM1Ce with JEOEC rf:llSt,atlOn data lorm.!
(JS.gRDf-19~1

loo~A

.UBIE~TTEIIPERATURE(TA)'
C;AI~IC;p.l· OdS

25"C

ux. POIliER

V
V
nA
~A

50
5

~A

nA
AUTOIIATIC

C;AI~ CO~TROL

VOLTS (V.l.CC)

nA

50
5

~A

50
5

~A

12

mA

nA
~81ENT TEIIPERATURE (TAl. 25"C
FREQUEHCY (f). 400IlH.
DRAIN IiILUAMPERES (101· 10
CATE 110. 2·fO.loOURCE VOLTS (Vcn)'

~

j.Lmho

4.0

6.0

8.5

pF

0.005

0.02

0.03

pF

-

2.0

-

pF

10

11.5

-

dB

-

3.9

6.0

dB

28

-

38

MHz

6.5

-

13

V

-6.5

-

-13

V

f =400 MHz

Gate No. I

UNITS

50
5

10,000 15,000 20,00

Ciss

(Draio-to-Gat..No. I)'

Gate-to-Source Reverse
Breakdown Voltage

I = I kHz

gls

Small·Signat, Short-Circuit,

·

Typ.

Gate No. I·to-Source Cutoff Voltage

Gate No. I-Terminal Forward Current

·
··

Min.

'"

DRAIN·TO·SOURCE VOLTS (VoS>

Fig. 6·Yis vs. VOS

VGIS = VOS =0

VGlS = VOS =0

tCapatrtance between Gate No.1 and all olher terminals.
'Three-terminal measurement With Gate No.2 and
Source returned to luald term.nal,

DRAIN·lO-SOURCE VOlTS (VDY

Fig. 7·yos vs. YOS

AItlBIENT TEjj,PERATURE(T;.)' 2S·C

c/o TE NO. 2·lD·SOURCE VOL n

(VClSI • 4

.... III.BIENTTEIiPERATURE(T AI·25"C
fREQUENCY In • ~OOIiH.
DR .... IIIMILLIAIoIPERESIIol·ID
CATEIIO. '.TO·SOURCE VOLT5IVG1S)"

..'
.t.IISIE,HTEII.PfR.l.TURE(TA)·2S"C
DRAIN·lO·SOURCE VOLTS(Vosl' IS

.,
.

CATE NO. Z.la-SOURCE VOL n (VClS)

DRAitHO·SOLRCE VOLtS IVoSI

Fig. 4 - JD vs. VDS

Fig. B-Yfs

VS.

VOS

____________________________________________________________________

~1

3N200
4M8IEHTTEIiPERAruREltAl":U'C
FR~ENCY'~ .. 4ODMH.

:~~:~~~T~J~¥ll(;'Gl:sl· •

~

.3

Lr"

•
•j

'"

,~
,~

£

..

:,

.
YS.

ORAINIdLLI".PERES(lo)

VDS

Fig- 10. fis

I."'="''';';'.,
"".allTf!III'EItA'I\IIlE{T",. ZI'C
"ECIleMCYCI)·alHl

YS.

,,

,
"

10

DlllAlN-ro.SOURCE VOl.TS (VlIsl

Fig. 9')'rs

, i!

D."

'0

Fig.

n .. Yo s

vs. 'D

"IIBlEMTUIiPERATUA£ly"l· 2S"'C
FltEQUEtfCYIII" aMlto

Alllf)ltTEIiPElU.1URE(T",·ZSOC
FIlEQUEMCTCII" OMIt.

:~:·!!t~~r:1J:11~~t:r

DRI.IN·Y().SOURCf VOLTS ['IDs)" IS
GAUMQ.2·TO-SOURCE ylll.n ....Glv ••

l:GlS ~ 4V

..

I

\

!r

L ..

1~1O
~f •

,

I

10

12

Fig. 12·YI•••• 10

Fig. 13. Yrs

YS.

,

"

DRAIHMlWAl&PEJIHflD!

_AIM MILUMPfltES(1oJ

'D

GATE NO. 2-10·SOUIICE YOLTS(Vc;zsl

.•

.s. VG2S

Fig. 14. Yis

~.

,k

• 2.1

I

Z

GATE NO. nO-SOURCE VOLTS (Vonl

.

Fig. 16· YI• • s. VG2S

Fig. IS· Yo • ••• VG2S

.

•., taTe NO. 2·ta·SOURCE VOLTS Nczs)

GATE NO.

~·TO-SCUIIC:E

YClLTSrYGJSI

Fig. 17. Yrs ••• VG2S

".IIENTTEIIP£JlATUIlEIT"l·Z.PC

AII8IEMTTEIlPE'ItA1URE(T... J o 2SOC
DRAIN.TC).SOURCEYOLTSCVDSI" IS

FREOUENCY F._1M.

sIi "

NOISEI'lGUI!".D4

.12.5

...

~

....

"

.,.
La

,

_20

Fig. lB· g .... .... VG2S

~2

_17.5

GE"~ATOII:

GATE MO. M'().SOURCE VOLTS (Vonl

Fig. 19· gl• ••• VGIS

-IS
_ll.S
_10
_7.5
SOURCE SUSCEPTANCE_IIIWIIHOS

_u

Fig. 20 - Noise figure vs. generator source "Jmittance

_______________________________________________________________

3N204, 3N205, 3N206
Features:

Silicon Dual-Insulated-Gate
Field-Effect Transistors
With Integrated Gate-Protection Circuits
For VH F TV Applications

•
•
•

Low Crss - 0.03 pF max.
High IVfsl- 14 mmho typo for 3N204 and 3N205
Integrated gate-protection diodes

MAXIMUM RATINGS,
Absolute Maximum Values at TA = 2!JlC
• DRAIN-TO·GATE No.1 VOLTAGE

3N204 - R F Amplifier
3N205 - Mixer
3N206 - TV I F Amplifier

* DRAIN-TO·GATE No.2 VOLTAGE

.
• DRAIN-TO·SOURCE VOLTAGE
• GATE NO.1·TERMINAL FORWARD CURRENT.
GATE NO.2·TERMINAL FORWARD CURRENT·
• GATE NO.1·TERMINAL REVERSE CURRENT
• GATE NO.2·TERMINAL REVERSE CURRENT
• CONTINUOUS DRAIN CURRENT
DEVICE DISSIPATION:
Up to T A = 25°C .
Above T A = 25°C derate linearly
Up to TC = 25°C

*

The RCA·3N204, 3N205, and 3N206 are
n'channel silicon, depletion type, dual·insulated gate, field·effect transistors intended
for vhf TV applications. Integrated backto· back diodes protect the gates from ex·
cessive input voltages.
The 3N204 is intended for use in vhf rf
amplifiers and delivers linear, low·noise ampli·
fication. Its extremely low feedback capaci·
tance allows high·gain stable operation with·
out neutralization. The 3N205 is specified for
low noise vhf mixer applications. The 3N206
is intended for use in tuned high·frequency
amplifiers such as TV if strips.

*

Above T C = 25°C derate linearly

.

30
30
25

V
V
V

10
10
-10
-10
50

rnA
rnA
rnA
rnA
rnA

360
2.4
1.2

rnW
rnW/oC
W
rnW/oC

8

* AMBIENT TEMPERATURE RANGE:
Operating .
Storage.

* LEAD TEMPERATURE (DURING SOLDERING):

-65 to +175
-65 to +200

°c
°c

+300

°c

At distance 1/16 ± 1/32 inch (1.59 ±0.79 rnrn)
from case for 10 seconds max. .

... Forward gate-terminal current is the current into a gate terminal with a forward-gate-to-source voltage applied.
This voltage is of such polarity that an increase in its magnitude causes the channel resistance to decrease.
* In accordance with JEDEC registration data format (JS·9 RDF·19B)

OPERATING CHARACTERISTICS at TA = 25 0 C

CHARACTERISTIC

TEST CONOITIONS

3N204
Common·Source Spot Noise
Figure, NF

• Small·Signal Common·Source
Insertion Power Gain, G ps

VDO;18 V, VGG;7 V,
f;200MHz,See Fig.13

Bandwidth, BW
Gain·Control Gate·Supply
Voltage, VGG(GC)

VOO;18 V, ,l',G ps;-30dB,1
f;200 MHz, See Fig. 13

Common·Source Spot Noise
Figure, N F

VO;15 V, VG2S = 4 V,
f; 450 MHz, 10; 10 rnA,
Smail·Signal Common Source
See Figs. 15 and 16
Insertion Power Gain, G ps

Min.

LIMITS
UNITS
Typ. Max.

-

-

3.5

20

-

28

dB

7

-

12

MHz

0

-

-2

V

-

-

5

dB

14

-

-

dB

dB

Bandwidth, BW
3N206
Common·Source Spot Noise
Figure, NF

VOO;18 V, fLO;245 MHz,3
fRF=200 MHz, See Fig.17

-

28

dB

4

7

MHz

dB

17

-

-

4

• Small·Signal Common-Source VOO;24 V, VGG;6 V,
Insertion Power Gain, G ps
f;45 MH Z, See Fig. 14

25

dB

3

-

35

* Bandwidth, BW

6

MHz

-1.6

-

0.6

* Gain·Control Gate-5upply
Voltage, VGG(GC)

Fig. 1 - Drain current vs. drain-to-source volts
(pulse-tested with pulse duration =
300 I-IS, duty cycle ";;;'2%).

3N205
Small·Signal Conversion
Power Gain, G ps (conv)

ORAIN-TO·SOURCE VOLTS (Vosl

VOO;24 V, ,l',G ps;-30dB,2
f;45 MH z, See Fig. 14

V
GATE No_I_TO_SOURCE VOLTS (VGIS'

*In accordance with JEOEC registration data format IJS-9 RDF-19Bl.
1 . .6.G ps is defined as the change in G ps from the value at VGG = 7V.
2. ~Gps is defined as the change in G ps from the value at VGG = 6V.
3. Amplitude at input from local oscillator is 3 V

RMS.

Fig.2 - Drain current vs_ gate·No.1·to·source volts
(pulse-tested with pulse duration = 300 i-J.S,
duty cycle";;;' 2%).

__________________________________________________________________ 453

3N204,3N205,3N206
ELECTRICAL CHARACTERISTICS, At T A = 25°C (unless otherwise specified)
CHARACTERISTIC

*

Orain-to-Source Breakdown
Voltage, V(BR)OS

*

Gate No.l-to-Source Forward
Breakdown Voltage, V(BR)G1SSFl

*

Gate No. l-to-Source Reverse
Breakdown Voltage, V(BR)G1SSRl

*

Gate No.2·to·Source Forward
Breakdown Voltage, V (BR)G2SSFl

*

Gate No.2-to-Source Reverse
Breakdown Voltage, V(BR)G2SSR1

*

TEST CONDITIONS
10 = 10J.lA,
VG1S=VG2S= -5V

*

*

*

IG1= -lOrnA, VG2S=VOS=0

-6

-30

V

30

V

IG2= -lOrnA, VG1S=VOS=0

-6

-30

V

VG1S=5V, VG2S=VOS=O

-

10

nA

-

-10

nA

-

-10

J.lA

-

10

nA

-10

nA

-10

J.lA
mA

3

30
30
15

-0.5

-4

V

-0.2

-4

V

Gate NO.2-Terminal Forward
VG2S=5V, VG1S=VOS=0
VG2S= -5V,

T A=25 u C

-

Current, I G2SSR

VG1S=VOS=0

TA=150'C

-

Zero-Gate No.1·Voltdge

V OS= 15V, VGIS=O,

Orain Current, IOS2

VG2S=4V

6
6

3N204
3N205
3N206

e

100

GATE No.2-TO- SOURCE VOLTS IVG2S1

Fig.4 - Yis

VS_

V G2S

20

VOS=15V,
VG2S=4V,
IO=20J.lA

VOS=15V,
VG1S=0,
10=20J.lA

Small-Signal Common·Source

VOS=15V,

3N204

10

22

Forward Transfer Admittance,

VG1S=0,

3N205

10

22

7

17

IVfs l3

6

Fig.3 - Yis vs. f

6

IG2=10mA, VG1S=VOS=0

T A=150°C

Voltage, V G2S(off)

10

FREQUENCY (II-MHz

T A=25°C

Gate No.2-to·Source Cutoff

*

V

VG2S=VOS=0

Voltage, VG1S(offl

*

30

VG1S= -5V,

Gate NO.l·IO-Source Cutoff

*

6

IG1=10mA, VG2S=VOS=0

Current, IGl SSR

Gate NO.2-Terminal Reverse

*

V

Gate No.1- Terminal Reverse

Current, I G2SSF

*

UNITS

-

25

Gate NO.1-Terminal Forward
Current,IG1SSF

LIMITS
MIN. MAX.

VG2S=4V,
f= 1 kHz

FREQUENCY H)-MHz

3N206

mmho

Fig.5 - Y fs

VS_

92CS·27951

f

Small·Signal Common-Source
Reverse Transfer Capacitance,
Crss

VOS=15V, VG2S=4V,
10= 10mA,f= 1 MHz

0.005

0.03

pF

*In accordance wi.th JEDEC registration data format (JS-9 RDF-198l.

1; All gate breakdown voltages are measured while the device

IS conducting rated gate current.
This ensures that the gate-voltage-limiting network is functioning properly.

2. This characteristic must be measured using pulse techniques (t w = 300JJ5, duty cycle ~ 2%).

3. This characteristic must be measured with bias voltages applied for less than 5 seconds to
avoid overheating. The signal is applied to gate No.1 with gate No.2 at ac ground.

GATE No·2-TQ-SOURCE VOLTS {VG2S'
9lCS-279~2

Fig.6 - Y fs

~4

VS_

V G2S

_____________________________________________________________

3N204, 3N205, 3N206
COtMON-SOURCE CIRCUIT
AMBIENT TEM?ERATURE (TAlo 25"C
DRAIN-TO-SOURCE VOLTS ('0'051015

6

~~:~NNoCG:~~;:;U~lC;I~~~:SA(VG2SI'4

COMMON- SOURCE CIRCUIT
AM81ENT TEMPERATURE (TAl 0 25"C

---l-"-+-

FREQUENCY (1)0200 MHI
35 ORAl N-TO-SOURCE VOLTS 1'0'051015
GATE No I-TO-SOURCE VOLTS {VOISloO

0·01

10

Fig.8 -

Fig. 7 - Yos vs. f

r,

GATE No.2-l0-S0URCE VOLTS (\lG2S1

GATE No 2-TO- SOURCE VOLTS [VG251

COMMON- SOURCE CIRCUIT
AMBIENT TEMPERATURE (TAlo 25"C
FREQUENCY Hlol MHz
DRAIN-TO-SOURCE VOLTS ('0'051015
GATE No I-TO-SOURCE VOLTS (VG 15)00

YOS VS.

F;g_9 - Ciss

VG2S

VS.

VG2S

470

,-----i
I

3

I

';2.5
~

~

pF

I

--,
I

ri

I--">~-I-~"?''''-_"""O--j~d'f

~-,

I

10kS!

II

CI

I

,-.JyVV_____~-t-~.........J

TO 50

\

FROM 50.n~·OOII'F
SOURCE

LOAD

n

I

I--............./Y)M.-~~+:-\J

I

I

o
-4

-3

27

l_~l

-2
GATE No.2-TO-SOURCE VOLTS (vG2S1
92C$-21956

Fig. 10 - Coss vs. V G2S

NOTE:
CI, C2, a C3: LEADLESS DISC CERAMIC, 0.001 J4F
C4: ARCO 462,5-90 pF, OR EQUIVALENT
LI: '3 TURNS No IS WIRE, 3116 INCH-DIA. ALUMINUM SLUG
L2:9 TURNS No. 20 WIRE, 3/16 INCH-OIA. ALUMINUM SLUG

__

I

J

Fig. 12 - 20D-MHz power gain, gain-control vol rage, and noise-figure test circuit for 3N204*.

* In accordance with JEOEC registration data format (JS-9 ROF-19B).

VDD

470

GAIN- CONTROL GATE SUPPLY VOLTAGE[VGG(GC~-V

I
I
I

Fig. 11 - /':, Gps vs. V GGIGC)

30

SEE FIG.l3
AOJUST VGG FOR 10

8.2
Mil

56

--)~P~l
IOkO

I

Mn

I
I
I

I

COMMON- SOURCE CIRCUIT
AMBIENT TEMPERATURE (TA1·25"C

b~i?~_~~dtl;lEo~g~~ {V05)018

470

,--~i ~

FROM 500
SOURCE

ctH

'PF

I
I
I

10

L __

NOTE:
CI: LEAOLESS DISC
C2: LEADLESS CISC
LI:S TURNS No. 28
L2:9 TURNS No.28

·10

·20

CERAMIC, 0.001 J4F
CERAMIC, 0.01 flF
WIRE, 5/32 INCH-OIA. FORM, TYPE "J"SLUG
WIRE, 5/32 INCH-CIA. FORM, TYPE "J" SLUG
92CM-27959

DRAIN CURRENT ~o-rnA

Fig. 13- Gpsvs,'O

Fig. 14 - -45-MHz power-gain and noise-figure test circuit for 3N206*.
* In accordance With JEDEC registration data format (JS-9 RDF-19B).

____________________________________________________________________

~5

3N204, 3N205, 3N206
I
I

+,

.,...+---

6.32 TAP FOR NYLON SCREWS

¥

'"+--RF CONNECTOR

1

I

ok

114.211

UG~2901U

1'37'~
134.931

!..0.500
112.701/

·50

rflZ.70

0375

ui.53)

L__ I

I
I

L __ +
C6

C7,ca
C9

0.125

CIO

~r§cl'~gJ~

(3.181

~r---~--------~
0"'[;[" -

(9"£'

o:rr;

r9~
0.500

-

-

+

No.IO DRIL.L

4 EA.

+ ----- +

_+
I

:
I

"L+__--'-____--'-_~
VIEW A

~I~16:;I-1

rT 0.".",,,
[9531: 1
III:L LI : (I"
0.750

0

I

0.875

·c·

(BEFORE BENDING)

NOTES:

A. Dimensions in parentheses are in millimeters and are derived from
the basic inch dimensions, as indicated.
B. The removable top of test fixture is not shown.
C. For clarity, the 62 kn resistor, the source and gate-2 socket pins,
and insulating stand-off terminals (lSOT) soldered into the fold of
L 1 and L2 respectively for mechanical support, ar.e not shown in
viewA.
D. Cl and C2 (C3 and C4) consist of shim brass and the "C" portion of
L 1 (L2) separated by air and the mylar tape covering the. "C" portion
of L 1 (L2).
E. The four views surrounding the center view are as they would appear
before the metal is bent up to form the sides.
Fig. 15 - -450 MHz power-gain and noise-figure test fixture*.

*

In accordance with JEDEC registration data format (JS-9 RDF·19Bl.

456 _________________________________________________________________

3N204, 3N205, 3N206

NOTE:
FOR TEST FIXTURE. SEE PICTORAL DRAWING IN FIGURE 16

CI THflU C4 : SEE FIGLI'E 18, NOTE 0
C': 0.001,.., LEADLESS DISC CAPACITOR
C6 THRU Cia, ALLEN-BRADLEY F5Au 0.001 ". F FEED-lliROUGH CAPACITORS,OR EQUIVALENT

LI

a U:SEE

FIGURE 16
gZeM-2T9&'

Fig. 16 - -450-MHz power-gain and noise-figure test circuit for 3N204*.

*

In accordance with JEDEC registration data format (JS-9 RDF-19B).

110

..OMH'l 1 a
ooa
l ..

3Yrms

•.•• F

1

Iron

3N205

t--='-r-----.~

'11

T:55~~l

T

-=

LOAD

-=

to

00
C\

C2

},OOl""
NOTE:
C1: AReo 462, 5-80 pF. or EQUIVALENT
C2: AReO 460,1.5-15 pF. OR eaUIVALENT
L1: 4 TURNS No.14 WIRE. 114 INCH INSIDE CIA.

gZeN-27963

Tl: PAl: 16 TURNS No.30WIRE CLOSE WOUND
ON 1/4 INCH CIA. FOAM, TYPE "J" SLUG
SEC: 5 TURNS No';30 WIRE CENTERED
OVER PRIMARY

Fig. 17 - -200 MHz-to45-MHz circuit for conversion power gain for 3N205*.
'" In accordance with JEDEC registration data format (JS-9 ROF-19B).

_____________________________________________________________

~7

3N211, 3N212, 3N213

Silicon Dual-Insulated-Gate Field-Effect Transistors
N-Channel Depletion Types

The RCA·3N211, 3N212, and 3N213 are
n-channel silicon, depletion type, dual·insu·
lated gate, field-effect transistor's intended
for VH F TV applications. Integrated back·
to·back diodes protect the gates from ex·
cessive input voltages.

Features:

3N211 - R F Amplifiers
3N212 - Mixers
3N213 - TV I F Strips

With Integrated Gate-Protection Circuits
For VHF TV Applications

• Low Crss - O.OS pF max.
• High IYfsl- 30 mmho typo for 3N211 and 3N212
• Integrated gate·protection diodes

The 3N211 is intended for use in VHF R F
amplifiers and delivers Iinear,low'noise ampli·
fication. Its extremely low feedback capaci·
tance allows high·gain stable operation with·
out neutralization. The 3N212 is specified for
low·noise VHF mixer applications. The
3N213 is intended for use in tuned high·
frequency amplifiers such as TV I F strips.

MAXIMUM RATINGS,
Absolute Maximum Values at TA = 25' C

*

3N213

3N211,3N212

DRAIN·TO·GATE No.1 VOLTAGE ......... .
DRAIN·TO·GATE No.2 VOLTAGE ......•...
DRAIN·TO·SOURCE VOLTAGE .......... .
GATE No.l·TERMINAL FORWARD CURRENT'"
GATE No.2·TERMINAL FORWARD CURRENT'"
GATE NO.l·TERMINAL REVERSE CURRENT .
GATE No.2·TERMINALREVERSECURRENT.
CONTINUOUS DRAIN CURRENT .......... .
DEVICE DISSIPATION:
UptoTA=2S'C ..................... .
Above TA = 2S'C derate linearly •.........
UptoTC=2SoC ..................... .
Above TC = 2SoC derate linearly ........ .
AMBIENT TEMPERATURE RANGE:
Operating ......... , ......... , ...... "
Storage .................. , .......... .
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.S9 ± 0.79 mm)
from case for 10 seconds max.

40
40
35

35
35
27

TERMINAL DIAGRAM
J
8ottom View

~
I

LEAD 1 LEAD 2 LEAD 3LEAD 4 -

4

DRAIN
GATE No.2
GATE No.1
SOURCE,
SUBSTRATE AND CASE

V
V
V
rnA
rnA
rnA
rnA
rnA

10
10
-10
----10
50

---360--mW
2.4 - - - mW!"C
mW
- - - - 1.2
8
mW!"C

AMBIENT TEMPERATURE IT",.ZII·C
CAAIN~TO-SOtJRCE VOlTAGE IVDslol!5V

"
1

.v

I

"!:!

'v

10

i

- - -65 to +175 - - - -6Sto+200--

OV
-O.IIY
-I~

- - - +300 - - - -

-1.25

-I

-On!

-05

-0.211

·,v

0

GATE NoJ-TO-SOURC£ IIOLTAGE(VG1S1-V
IlCS-11I70

Forward gate~terminal current is the current into a gate terminal with a forward gate·to-source voltage applied.
This voltage is of such polarity that an increase in its magnitude causes the channel resistance to decrease.

87.:1 AMltENT TEMPI!RATURE (TAl- ZS·C
DRAIN-TO-SOURCE VOLTAGE 1"05)-"10'

Fig.3-Drain current vs. gate No. t·to-source
voltage for all types.

AMBIENT TEMPE:RATURE (TA'. 2S·C

,.

."

"

('los""'"

I

;

II

~RAIN-TO'SOURCE VOLTAGE

to

E

I~'

,v

!

~

DV

,u
DRAIN-TO-SOURCE VOLTAGE

o
-,

I

IVosl-v

-IV

-2

-I

0

I

2

..

GATE NO.I-lO-SOURCE VOLTAGE ('10151-'1

-o.8V

II

-.-;t
o

Sics-ttl"

ireS-ZIt'"

Fig.2-0rain current vs. gate No. T-to-source

Fig.4-Drain current vs. gate No. 2·to-sDurce

92CS-21168

Fig. '-Drain current VI. drain-fa-source voltage
for all types.

3

-Q4'"

!

voltage for all types.

voltage for a/l types.

(Figures 1 - 4 are pulse tested. Pulse duration = 300 J.IS. duty cycle 0;;;2%.)

458 __________________________________________________________________

3N211,3N212,3N213
ELECTRICAL CHARACTERISTICS, At T A ~ 25°C (unless otherwise specified)
CHARACTE R ISTI C

*

Orain·to·Source Breakdown
Voltage, V(BR)OS

TEST CONDITIONS

LIMITS

3N211
10 ~ 10llA,
VGl S~VG2S~ -4V 3N212
3N213

*

Gate No.l·to·Source Forward
Breakdown Voltage, V(BR)G1SSFl

IG1~10mA, VG2S~VOS~0

*

Gate NO.l·to·Source Reverse
Breakdown Voltage, V(BR)G1SSRl

IG1~

*

Gate No.2·to·Source Forward
Breakdown Voltage, V (BR)G2SSFl

IG2~10mA, VG1S~VDS~0

*

Gate NO.2·to·Source Reverse
Breakdown Voltage, V (BR)G2SSR 1

IG2~

UNITS

MIN. MAX.

-10mA, VG2S~VDS~0

-

27
27
35

-

6

-

V

-6

-

V

6

-

V

-6

-

V

-

V
-05V

°.,

•• -~

j-'->'

-'1-'.:' ....

,

,

GATE No.2-TO-SOURCE VOLTAGE (VG2S)-V

Fig. 5 - IYfsl vs. V G2S for 3N211 and 3N212.

*

Gate NO.l·Terminal Forward

*

VG1S~VDS~0

10

-

-10

nA

-10

IlA

VG2S~5V, VG1S=VDS~0

-

10

nA

Gate NO.2·Terminal Reverse

VG2S~

T A=25°C

-

-10

nA

Current, IG2SSR

VG1S~VDS=0

TA=150°C

-

-10

IlA

40

mA

Gate NO.l·Terminal Reverse
Current,IG1SSR
Gate NO.2·Terminal Forward
Current, IG2SSF

AMBIENT TEMPERATURE (TA)o2!!-C
OAAIN TO-SOURCE VOLTAGE (VOS)ol!! V
FREQUENCY (fiolkHt

!

-

Current,IG1SSF

*

-10mA,

VG1S~5V, VG2S~VDS~0
VG1S~

-5V,

VG2S=VDS~0

TA~25°C
TA~150°C

'Onti

.

nA

GATE No. 2-TO-SOURCE VOLTAGE (VG2S1-V

*
*
*

*

Zero·Gate No.l·Volt"ge
Drain Current, IDS2
Gate No.l·to·Source Cutoff
Voltage, VG1S(off)

Gate No.2·to·Source Cutoff
Voltage, V G2S(off)

* Small·Signal Common·Source
Forward Transfer Admittance,
1Vfsl3

-5V,

VDS=15V, VG1S=O,

VDS=15V,
VG2S=4V,
ID~20IlA

Small·Signal Common·Source
Reverse Transfer Capacitance,
Crss

3N211

-0.5 -5.5

3N212

-0.5

3N213

-0.5 -5.5

-4

3N211

-0.2 -2.5

VG1S~O,

3N212

-0.2

-4

ID~20IlA

3N213

-0.2

-4

VDS=15V,

V DS=15V,

3N211

17

40

VG1S~O,

3N212

17

40

VG2S=4V,
kHz

3N213

15

35

0.005

0.05

f~l

*

6

VG2S~4V

VDS~15V,
ID~lmA,

VG2S=4V,
f=lMHz

*In accordance with JEDEC registration data format (JS·g RDF-19BI.

1. All gate breakdown voltages are measured while the device is conducting rated gate current.
This ensures that the gate-voltage-limiting network is functioning properly.

Fig. 6 - IYfsl vs. V G2S for 3N213.

V

V

r

i '
e°

-2

ov
-c.!! V
-I.!!
-O!l
0
O!!
1
I.!!
GATE No.I-TO-SOURCE VOLTAGE IVGIS1-V

mmho
Fig. 7 - IYfslvs. V G1S far3N211,and3N212.

pF'

~::II~~~O~~~~~~:T~riCT~~A~ ~~~;l~ I!! V

I

f
~

~

30 FREQUENCY (f}_1 kHr

2!!

GATE-No 2-TO-SCURCE
VOLTAGE IVG2S1-"'"

20

~

2. This characteristic must be measured using pulse techniques (tw = 300j.ls, duty cycle ~ 2%).
3. This characteristic must be measured with bias voltages applied for less than 5 seconds to
avoid '"'N.9"fleating. The signal is applied to gate No.1 with gate No.2 at ae ground.
-O.!!V
-I!l
-I
-(l~
0
O.!!
1
I.!!
GATE NO.1-TO-SOURCE VOLTAGE (VGIS)-V

Fig. 8-IYfslvs. V G1S far3N213.

- -_______________________________________________________________

~9

3N211, 3N212, 3N213
OPERATING CHARACTERISTICS at TA = 25°C
LIMITS
CHARACTERISTIC

UNITS

TEST CONDITIONS

Min. Typ. Max.

3N211

*

..
.

Common·Source Spot Noise
Figure, F
Small·Signal Common·Source
Insertion Power Gain, Gps
Bandwidth, B

*

Gain·Control Gate·Supply
Voltage, VGG(GC)

*

Common·Source Spot Noise
Figure, F

.
..
.
.

VOO=24V, VGG=6V,
f=4SMHz, See Fig.10

-

-

3.5

24

-

35

dB

5

-

12

MHz

0

-

-2

V

-

-

4

dB

29

37

dB

dB

3.5

-

VOO=24V, /lG ps = -30dB,2
f=45MHz, See Fig.10

-

-

±1

V

VOO=1 BV, fLO=245MHz,3
fRF=200MHz, See Fig.11

21

-

2B

dB

4

-

7

MHz

- -

4

dB

27

-

35

dB

3.5

-.

6

-

-

±1

Bandwidth, B
Gain·Control Gate·Supply
Voltage, VGG(GC)

MHz

6

3N212
Small·Signal Conversion
Power Gain, Gps (conv)
Bandwidth, B

.

3N213

.*

VOO=1BV,/lGps= -30dB,1
f=200MHz, See Fig.9

Small·Signal Common·Source
Insertion Power Gain, Gps

*

.

VOO=1BV, VGG=7V,
f = 200M Hz, See Fig.9

Common·Source Spot Noise
Figure, F
Small·Signal Common·Source
Insertion Power Gain, Gps

VOO=24V, VGG=6V,
f=45MHz, See Fig.9

Bandwidth, B
Gain·Control Gate·Supply
Voltage, VGG(GC)

MHz

VOO=24V, /lGps= -30dB,2
f=45MHz, See Fig.9

V

*In accordance with JEDEC registration data format IJS·9 RDF·19BI. 2. OOps is defined as the change in Gps from the value at VGG = 6V.
OOps is defined as the change in Gps from the ,value at VGG = 7V. 3. Amplitude at input from local oscillator is adjusted for maximum

1.

vGG

Gps(conv'·

VDD

470

.pF

-,

r-------~ ~-...,

I
I

I
I
I

I
IDkR

:

I

1-~~~__~~__~~~~lro50R

Clrj

LOAD

FROM 50 R ~Ol ~F
SOURCE

11-............
I

...

_"7"'---_--~

27

: PFI
L__

NOTE'
CI, C2, a C3' LEADLESS DISC CERAMIC, 0.001 ~F
C4: ARCD 462, 5-80 pF, OR EQUIVALENT
LI: 3 TORNS No. 18 WIRE. 3116 INCH-OIA. ALUMINUM SLUG
L2,a TURNS No. 20 WIRE, 3/16 INCH-DIA. ALUMINUM SLUG

I
I

I
I

I

__J

* RELEASE
JEDEC REGISTERED DATA - - JEDEC
No. 6438.
92CM-26176

Fig.9-200 MHz pOWflr gain, gain control voltaf/ll, and noise figure test circuit for 3N211*.

460 _____________________________________________________________

3N211, 3N212, 3N213
470

I--~-l

I
I
I
I
FROM 50n

SOURCE

470
pF

470
pF

r -H- l

82

5.6

MO

MO

10 kfl

I

I
I

390n

3N211

OR
3N212

I

L2

12~T050n

t-~2.~2vMvO~_~_~1-~-'~ ~~.-~-~--~\

IV

Gate Leakage Current

IGSS

a

Zero-Bias Drain Current

lOSS

15

VGS - 0

5

15

~

-8V

Max.
-8

V

1

nA

1

nA

30

rnA

Small-Signal. Shorl-Circuit
Forward Transconductance

Ifs

1 KHz

15

5

4000

7500

Smail-Signal, Short-Circuit
Reverse-Transfer Capacitance

Crss

1

15

5

0.12

0.25

15

5

(Drain·lo·Gale)
Small Signal Shorl-Circuit
Input Capac itance

Ciss

1

Input Admittance

Yis

Common Source Configuration

Forward Transfer Admittance

Yls

VDS ~ 15V

Output Admittance

Yas

10

Maximum Avai lable Power Gain

MAG

100

15

5

Maximum Usable Power Gain
(unneulfalized)

MUG

100

15

5

MUG

100

15

5

NF

200

15

5

Maximum Usable Power Gain
(neutralization)

Noise Figure

0_35

5_5

pF
pF

0.4 + j7.3

1~100rnHz

~

.umho

7-Jl
0.18 ,J1.8

5 rnA

12

21

dB

12

dB

16

dB

3.5

5

dB

For characteristics curves, refer to types 3N128 and 3N143,

462 _______________________________________________________________

40468A, 40559A
MOS Silicon Transistors

Device Features:

N-Channel Depletion Types

For R F Amplifier and Mixer Applications
in FM and AM/FM Receivers

• high forward transconductance - gfs • 7500 Jotmho typ_ for 40468A

Performance Features:

RCA~40468A

and 40559A are silicon insulated-gate
field-effect transistors of the n-channel depletion type
utilizing the MOS· construction. They are intended
primarily for use as the rf amplifier and mixer, respectively, in FM receivers covering the 88 to 108 MHz
band, but can be used for general amplifier applications
at frequencies up to 125 MHz. For circuit design and
typical performance data refer to RCA Application Note
AN3535 "An FM Tuner Using Single-Gate MOS FieldEffect Transistors as RF Amplifier and Mixer".

The wide dynamic range of these transistors reduces cross-modulation effects in AM receivers and
minimizes the generation of spurious responses in
FM receivers.
Operating as a neutralized ampl ifier at 100 MHz, the
40468A can provide a power gain of 17 dB (tyP.). A
power gain of 14 dB (typ.) can be realized without
neutralization.

• low feedback capacitance - •
Cru - 0.35 pF max. for 40468A
0.38 pF max. for 40559A

• reduced spurious responses in FM tuners
• reverse bias on substrate improves linearity

• high useful power gains - neutralized - 17 dB typo
unneutralized - 14 dB typo

• reduced cross-modulation effects in AM receivers

• hermetically sealed in TO-12 metal package

Maximum Roting5, Absolute-.~taximum Values at T A '" 25°C;
DRAIN-T~SOURCE VOLTAGE, Yns '
DRAIN-To-GATE VOLTAGE, V IlG
GATE-To-SOURCE VOLTAGE, Vas:

+20

CONTINUOUS (del.
PEAK ue, • , , , .

.20

v

+1. -8
i 15

V
V

25

DRAIN CURRENT, 10
TRANSISTOR DISSIPATION:
At ambient } up to 25°C ...
temperatures above 25°C ..

TERMINAL DIAGRAM

~
~

rnA

330
mW
. . nerlile ut 2.2 mW/oC

AMBIENT TEMPERATURE RANGE:
Storoge. • . .
-65 to + 175°C
Operating . . .
. . . . . . . . ..
-65 to + 175 °c
LEAD TEMPERATURE (During Soldering):
At distances not closer than 1/32 inch to
seating surface for 10 seconds mnximum .
265
'c

LEAD
LEAD
LEAD
LEAD

1 - DRAIN
2 - SOURCE
3 - INSULATED GATE
4 - BULK (SUBSTRATE) AND CASE

... Met'al-Oxide-Semiconductor.

ELECTRICAL CHARACTERISTICS, .t TA = 25°C
With Bulk (Substrate) Connected to Source Unle .. Otherwise Specified

TEST CONDITIONS
DC
DC
Symbols

Characteristics

Drain-la-Source Cutoff Current

FreqLlency

Drain-toSource

Drain
Current

I
MHz

VDS
V
12

10
rnA

10(011)

Gate Leakage Current

0
0
15

IGSS

Zero-Bias Drain Current

lOSS

Small·Signal, Shorl·Circuil

VGS
VGS
VGS
VGS

LIMITS
RCA·40468A
RF Amplilier
Min.

Max.

15

100
I
I
30

5

ils

I kHz

15

5

7500

Crss

I

15

5

0.25

Ciss

15

ils(e)
MAG

I
RF IMi,er
100 MHz
100 MHZ
100,1 10 . 7
MH' MHz
I kHz
100

Maximum Usable Power Gain
(Unneulralized)

MUG

Maximum Usable Power Gain

FOIward Transcondllctanee
Small-Signal, Short-Clrellit
Reverse-Transfer Capacitance

Mixer

Typ.

=·8V
=·8V
= +IV
=0

RCA·40559A

Min.

5

Typ.

Max.

15

500
I
I
30

Units

j'A

nA
nA
rnA
fJllIho

0.35

0.25

0.38

pF

(Orain·to·Gale)
Input Cajl3citance
Admittance
Input Admittance
Forward Transfer Admittance
Output Admittance
Forward Conversion Transconductance
Maximum Available Power Gain

INeulralized)
Maximum Available Conversion
Gain
Noise Figure

*

Bulk

YIS
Yls
Yos

5.5

5.5

-

0.155.j3.45
7.4 +' 0.9
0.21 • j 0.9

pF

-

0.14+j3.38

mmho
mmho

0.076 + j 0.153

mmho

2800'
26

fJllIho
dB

15
15

3
5

100

15

5

-

14

dB

MUG

100

15

5

14

17

dB

MAGe

lin = 10,0
lout =10.7
100

15

3

15

5

NF

(Sub~tlate)-to-Soulee

15
15
15

5
RF Mixer
5
3
5
3
5
3

22
3.5

5

dB
dB

Volts (VBS) = -3.

For characteristics curves, refer to types 3N128 and 3N143.

__________________________________________________________________ 463

40600, 40601, 40602

SILICON DUAL INSULATED·GATE FIELD·EFFECT TRANSISTORS
N·Channel Depletion Types
For VHF TV Receiver Applications

DEVICE FEA TURE S
• extremely low feedback capacitance
ens = 0.02 pF typo
• high power gain

MUG. = 20 dB typo I•• 40600
MAG = 35 dB typo lor 40602
MAGe = 14 dB typo la. 40601

RCA 40600, 40601, and 40602 are n-channel depletion type, dual-insulated-gate. field-effect transistors
utilizing the MOSconstruction. These devices have characteristics which make them highly desirable for If-amplifier applications (40600), mixer applications (40601),
and first-ii-amplifier applications (40602) in vhf TV receivers and other types of commercial equipment operating at frequencies up to approximately 250 MHz.

40600, and 35 dB typo at 44 MHz for the 40602. The
gain of the rf and if stages can be controlled by applying agc voltage to gate No.2 and agc delay is easily obtained. Virtually no agc power is required for full gain
reduction.
Types 40600, 40601, and 40602 are hermetically
sealed in metal JEDEC TO-72 packages.

TERMINAL DIAGRAM

3

~

leod 1 - Drain
L~d 2 Gore No. 2
leod 3 - Gole No. 1
leod ,,_ 50..'(8, $ubllrole ond COle

These transistors feature a series arrangement of

two separate channels, each channel having an independent control gate. In amplifier applications the40600
and 40602 with their wide dynamic fange provide substantially better cross-modulation performance than is
obtainable with bipolar or single~gate field-effect transistors, In mixer applications the 40601 provides excellent isolation between the oscillator and rf signals
because each of the two signal frequencies being mixed
has its own control element. The wide dynamic range
of the 40601 minimizes cross-modulation which is generally encountered in mixer stages.

Provision of two insulated gates also results in
extremely low feedback capacitances (0.02 pF typ.), a
feature which enables the 40600 and 40602 to provide
high maximum useable power gains in unneutralized
circuits - for example, 20 dB at 200 MHz typ: for the

APPLICA TlONS

I

• VHF TV Receive-f
40600 for rf amplifier applications
40601 for mixer applications
40602 for first·if·amplifier applications

MOJlimum Ratings, Absolute-Maximum Values at TA = 25°C:
DRAIN-TO-SQURCE VOLTAGE, Vns • ,
GATE No,l-T0-SOURCE VOLTAGE, VGlS:
Continuous (de) .

PER FORMANCE FEA TURE S

Peak ae . '

• superior crass-modulation performance and greater
dynamic range than bipolar and single·gate field.effect
transistors

GATE No,2·T0-S0URCE VOLTAGE, VG2S:

• permits use of vGcuU'm-tube biasing techniques

DRAIN-TO-GATE VOLTAGE, VnGl or VDG2.
DRAIN CURRENT, 10 (Pulsed):

• excellent thermal stability

40600,40601,40602

TEST CONDITIONS

Min.
Gate No,l·to·Source Cutoff Voltage

VGlS(off)

VOS = +15V, 10 = 200 MA

VOS = +15V,

Gate No.2·to-Source Cutoff Voltage

UNITS

tn = 200!J.A

IGISS

oA

VGlS =·20V, VG2S =0, VOS =0

oA

IG2SS

VG2S =-20V, VGIS =0, VOS =0

Orain Current

lOSS

VOS '" +I3V, VGIS - 0, VG2S = +4V

Forward Transconductance

g"

VOS = +13V, 10 = 10 rnA
VG2S = +4V, f = 1 kHz

v

-8to40'7~ofVnS

V

V

-8 to +20

V

'20

v

50

rnA

400
mW
, .derate linearly at
2,67 mW/oC

1&

mA

10000

Mmho

I

°c

I

I '
I

Gate No.2 Leakage Current

V

i-------l---·- - - - - - - --I

·2

VGIS = 0

. . . ,.

"20

+1 to -8
+20 to-8

AMBIENT TEMPERATURE RANGE:
Storage and Operating . . . .

I

Gate No,1 Leakage CUffen!

.. "

...... , . , . ' '.

o to

., -65 to +175
LEAD TEMPERATURE (During soldering):
At distances> 1/32" from seating
Surface for 10seconds max. , •. ' .••.
265

Mall.

Typ.

·2

VG2S = +4V

Peak ae

TRANSISTOR DISSIPATION, PT:
At ambient l up to 25°C
temperatures f above 25°C

LIMITS
SYMBOLS

Continuous (de) . . . ,. "

~:tl:~a~~~~tfo.4l0.~S: .. , , .. '

ELECTRICAL CHARACTERISTICS, at TA = 25a C

CHARACTERISTICS

4

I

Q~

OUTPUT

I
I

TYPICAL PERFORMANCE CHARACTERISTICS, at TA = 25·C
40600
RF AMPLIFIER
f = 200 MHz
CHARACTERISTICS

Small-Signal, Short Cucui!
Reverse-Transfer Capacitance
(Oram·to·Gate No,l) at f "1 MHz

40601
MIXER
f = 200 MHz
Local-oscillator injection
Voltage on
Gate No.2 =750 mV
VOS =lSV
VG2S = +0.6V
VG1S = O.7SV

SYMBOLS

UNITS

0.02typ.

O,02typ,

Crss

0.02typ,

0.03 max,

0.03 max,

0.03 max,

Output Capacitance

Cos s

2.2

2.2

2.2 at f = 44 MHz

pF

Input Capacitance

Crss

5.5

5.5

5.5

pF

pF

Input ReSistance

r iss

1.2

10

1.2

Kl1

Output Resistance

ross

2.8

12

12 at f '" 44 MHz

Kl1

Magnitude of Forward Transadmittance

IY"I

11000

11000

2700*

Mmho

Phase Angle of Forward
Transadmittance

/R

·46

·11

MAG

·20

Maximum Available Power Gain
Maximum Usable Power Gain
(Unneutralized)
Power Gam
See Fig.l for measurement Circuit
Noise Figure
•

40602
IF AMPLIFIER
f = 44 MHz

MUGu

20'

GpS

17,5

NF

Magnitude of forward conversion lIansadmlttance

degrees

35

14**

Cl,C2: 1.5-5 pF variable air capacitor: E. F. Johnson Type IGO-Ir",
or equivalent.
C3:

}~~~~:O~~~~~-~:fi5~:ri~~:~le~~~acitor:

JFD Type VAM-OIO,

C4: 0.3-3 pF piston·type variable air capacitor: Roanwell Type
MH-13,.or equivalent.

dB

L 1: 5 turns silver-plated 0.02" thick, 0.07"- O.OS"wide copper

1 Stage 28

dB
dB
dB

2 Stages 25
3 Stages 24

dB

5 max,

** Mallimum available conversion gain

• Tubular ceramic.
~ Disk ceramic.
# Fellite bead (ih used); Indiana General No. H1742C-(A-I47)
Df F1l57-1-H j or equivalent.

dB
&

Limited by practical deslfUI conSiderations

l~~~~~' a~~~~~~aJ.~~~,~ei~p~~d~~di~f/; t~~~;1 ir~~n~~~nd
of winding.

L 2: Same as Ll except winding length approx. 0.7"; no lap.

Fig,l - 200 MHz Power Gain and Noise Figure Test Circui1
fa. 40600 and 40602

For characteristics curves, refer to type 3N140.

464 _____________________________________________________________________

40603,40604

SILICON DUAL INSULATED·GA TE FIELD· EFFECT TRANSISTORS
"-Channel Depletion Types
For FM Tuner Applications

PERFORMANCE FEATURES
• large dynamic range permits large-signal handling before overloild
• dual gates allow product mixing with extremely law
harmonic generation
• greatly reduces spurious responses in FM recei ... ers

RCA 40603 and 40604 are n-channel silicon, depletion type, dual insulated-gate, field-effect transistors
utilizing the MOS construction.
These devices have exceptional characteristics for
rf-amplifier (40603) and mixer applications (40604) in
FM tuners and other commercial equipment operating
at frequencies up to approximately 150 MHz. These tran-

• permits use of vacuum-tube biasing techniques
• excellent thermal stability
• superior cross-modulation performance and greater dynamic range than bipolar and single-gate field-effect
transistors

Maximum Ratings, Absolute-Maximum Values at TA " 2SoC:

sistors feature a series arrangement of two separate

channels, each channel having an independent control
gate. For amplifier applications the 40603 with its wide
dynamic range provides substantially better cross-modulation performance and relative freedom from spurious
responses than is obtainable with bipolar or single-gate
field-effect transistors. The mixing function performed
by the 40604 is unique in that the signal applied to gate
No.2 is used to modulate the input-gate (gate No.1)
trans fer characteristic. This technique is superior to
conventional I'squtue law" mixing, which can only be
accomplished in the non-linear region of the device transfer characteristic.
Because of the low feedback capacitance (0.02 typo
pF) the 40603 can provide a power gain of 25 dB (typ.)
at 100 MHz in an unneutralized amplifier circuit.
The gain of the rf stage can be controlled by applying agc voltage to gate No.2. Virtually no agc power is
required for full gain reduction.
The 40603 and 40604 are hermetically sealed in
JEDEC TO-72 packages.

DRAIN-TO-SOURCE VOLTAGE. VDS . . . .

010 +20

GATE No.I-To-SOURCE VOLTAGE. VGlS:
Continuous (de) ..
Peak ac ..

V

-810 +1

V

-810 +20

V

GATE No.2-To-SOURCE VOLTAGE, VG2S:
Continuous (de) ..
. -8Io40'7oofVDS V
Peak ac . . .
-8 to +20
V
DRAIN-TO-GATE VOLTAGE,
VPGl or VDG2 . . . .
DRAIN CURRENT. ID (Pulsed):

DEVICE FEA TURES
• extremely low feedback capacitance
C rss = 0.02 pF typo
• high unneutralized RF power gain

MUG = 25 dB (typ.) /., 40603

v

• low noise figure

~:ll;~a~~~~I~~.~s2.0.~S: .

NF = 2.SdB typo ,., 40603
50

rnA

TRANSISTOR DISSIPATION, PT:
At ambient l up to 25°C . . . . . . . , '
400
mW
temperatures { above 25°C . . . . . . . . . derate linearly at
2.67 mW/oC
AMBIENT TEMPERATURE RANGE:
Storage and Operating, . . . . . . . . .
-65 to +175 °c
LEAD TEMPERATURE (During soldering):
At distances> 1/32" from seating
surface for lC1seconds max,

265

·c

TERMINAL DIAGRAM

~

M

l ...d I_Drain

lead 2 lead 3 h'od .. -

Gat, No.2
Go'e No. I
Source, S",bllrale gnd Cal.

ELECTRICAL CHARACTERISTICS, at T A = 25·C

LIMITS
40603
CHARACTERISTICS

SYMBOLS

TEST CONDITIONS

Typ.
Gate No.1-to-Source Cutoff
Voltage
Gale No.2-la-Source Cutol!
Voltage

VGlSloff)

Vas'" t15 V, 10 " 200 J.crleCurrcnt

Gate No. 2·T".mlnal Reverse CU[fenl

Mm

-3

Ves" +15V,IO-200"A,VG1S-0
Voll~------ -

lAGC'_4TOti~TERNALsH'ELD--

I

---------l
C4
OUT~UT

ti"F!!rrite bead (4~; Pyroferric Co.
"Carbonyl J" 0.09 in aD; 0.03
in ID. 0.063 in thickness

\1000

I
I
I

,----r"m~---+'---,

0=40820
" Disc ceramic.
• Tubular ceramic

All resistors in ohms
All c-_~50S
Fig.2 -

C,·

1.8 - 8.7 pF variable air capacitor
Type 160·104, or equivalent.

C2:

1.5 - 5 pF variableaircapacilor: E. F. Johnson Type
160·102, or equivalent.

E. F. Johnson

C3

1 - 10 pF piston·type variable air capacitor: JFD
Type VAM·Ol0; Johanson Type 4335, or eqUivalent.

C4·

0.8 - 4.5 pF piston type variable air capacitor: Erie
560·013 or equivalent.

L,·

4 turns silver·plated 0.02·in thick, 0.075·0.085 in
wide, copper ribbon. Internal diameter of winding =
0.25 in, winding length appro/(. 0.80 in.

L2·

4·112 turns silver· plated 0.02 in thick, 0.085·0.095
in wide, 5/16·in; ID Coil ::::0.90 in. long.

nCS-I7455

200 MHz power gain and noise figure test circuit for type 40820.

Table 1 - y parameters vs. frequency
CHARACTERISTICS

SYMBOL

FREQUENCY (MHz)
50

100

200

250

UNITS

Y Parameters
(nput Conductance

gis

O.OB

0.33

1.0

1.6

mmho

Input Susceptance

bis

1.B

3.6

7.5

9.B

mmho

Magnitude Forward Transadmittance

IV!sl

12

12

12

12.3

Angle of Forward Transadmittance



6. N,IS the quantity of allowable mlssmg leads.

DUAL-IN-LiNE PLASTIC AND FRIT-SEAL CERAMIC PACKAGES
(E), (F), and (G) Suffixes
(E, (F) and (G) Suffixes
(JEDEC MO-001-AC) 16-Leaa
(JEDEC MO-001-AB) 14-Lead

(E) and (G) Suffixes (JEDEC MO-001-ANI
8-Lead Plastic (Mini-Dfp)
INCHES
MIN. MAX.

SYMBOL

A

NOTE

0.155 0.200
0.020 0.050

Al

3.94
0.508

0.014 0.020
0.035 0.065

B
81
0

5.08
1.27

0.356
0.889

0.008 0.012·
0.370 0.400

C

MILLIMETERS
MIN.
MAX.

1

0.508
1.65

0.203
9.40

0.304
10.16

7.62
6.10

8.25
6.60

El

0.300 0.325
0.240 0.260

el

0.100 TP

2

2.54 TP

eA

0.300 TP

2.3

7.62 TP

L
L2

0.125 0.150
0.000 0.030

E

15

0

a

3.18
0.000

N
Nl

8
0

01
S

0.040 0.075
0.Q15 0.060

4

3.81
0.762
15<

0
8
0

5
6
1.02
0.381

SYMBOL
A
AI
B
Bl
C
0

E
El
·1
eA
L
L2
a

N
Nl
01
S

INCHES
MIN.
MAX.
0.155
0.200
0.020
0.050
0.014
0.020
0}J65
0.050
0.008
0.012
0.745
0.770
0.300
0.325
0.240
0.260
0.100TP
0.300 TP
0.125
0.150
0.030
0.000
GO 1150
14
0
0.040
0.075
0.065
0.090

NOTE

1

2

MILLIMETERS

MIN.
3.94
0.51
0.356
1.27

MAX.

5.08

0.204

A,
8

19.55
8.25
6.60
TP

8,
C

D

E
E,

3.18
0.000
GO

I

3.81
0.76
150

14
0
1.02
1.66

1.90
2.28

INCHES
MIN.
MAX.
0.200
0.'55
0.020
0.050
0.014
0.Q35

0.020
0.065

0.008
0.745
0.300
0.240

0.0'2
0.785
0.325
0.260

NOTE

,

0.356
0.89

0.508
1.65

0.204

0.304
19.93
8.25
6.60

18.93
7.62
6.'0

e,

0.'00 TP

2

2.54 TP

0.300 TP

2.3

7.62 TP

L

0.125

0.150

3.18

3.el

L2

0.000

0.030

0.000

0.76

a
N
N,

0°

15°
16
0

4
5
6

go

'5°
'6
0

1.90

0,

0.040

0.075

1.02

1.90

1.52

S

0.0'5

0.060

0.39

1.52

92CM-1596'7R4

92CS'24026RI
TERM1M

MILLIMETERS
MIN.
MAX.
3.94
5.08
0.51
1.27

eA

7.62 TP

2.3

4
5
6

A

1.27

0.508
1.65
0.304

18.93
7.62
6.10
2.54

SYMBOL

'L " •

CERAMIC FLAT PACKS
(K) Suffix
(JEDEC MO-OO4-AF) 14-Lead

- -

N

,II
I
I
I
I

,

i'INDEX
AREA

-

I
,
1-'

r-

~

llll
,-

-~

- - ,
,,,
,,,
,
1

- -

I I I
2

"

- • 1--

for Axial Lead Product Outlines.
2. Leads within .005" t12 mm) radius of True Position (TP) at
maximum material condition.
3. N is the maximum quantity of lead positions.
4. Z and Z, determine a zone within which all body and lead
irregularities lie.

B
C
e

0.003
0.006
0.050 TP

E
H

0.200
0.600

L

0.'50

NOTES,

r--

0

0.005

S

0.000

Z
Z,

0.300
1.000

I

NOTE

~_MIL_~IME~E_~
MIN.

1

038'
1 ··TO.077
0.152
1.27 TP . __
2
5.1
7.6
i
15.3
3.9
0.13
0.00
4
4

25.4

.I. 8.8
14

3
0.050
0.050

0.300
0.400

MAX.
2.54
0.482

0.2'

0.350

14

N

1

-11-.

1. Refer to Rules for Dimensioning (JEDEC Publication No. 95)

A

INCHES
MIN.
MAX.
0.008
0.100
0.Q15
0.019

SYMBOL

1.27
1.27
7.62
10.16
92SS 4300R3

476 _______________________________________________________________

Dimensional Outlines
TO-5STYLEPACKAGES
(T) Suffix (JEDEC MO-002-ALl8-Lead TO-5 Style
SYMBOL

I

MIN.

MAX.

0.200 TP

a
A,

0,010

0.050

0.'65

0.'85
0.0'9

0.0'6
0.'25

NOTE

MILLIMETERS

I

MIN.

0.407

0.482
4.06

3

3.'8
0.407

0.0'6
0.335

0.02'
0.370

00,

0.305

F,

0.020

J
k

0.028

0.034

0.029

0.045

4

L,

0.000

0.050

3

0.00

L2
L3

0.250

0.500

6.4

0.500

0.562

3
3

0.533
9.39

0.335

8.5'
7.75

0.040

0.5'

'.0'
0.863

45 TP
8

N

'.27
4.69

3

0.'60

3

N,

MAX.

0.26
4.20

00

.

(S) Suffix 8-Lead TO-5 Style with
Dual-In-Line Formed Leads (DIL-CAN)

5.88 TP

2

A2
06
oB,
oB 2

92CS-19431R2

INCHES

8.50

0.7'2
0.74

'27

i~~gl:9~;g~
OIA.
.185

.30!>-.33~

'.'4
'.27

'4.27
45 TP

6

8

5

3

.IOO± .010

12.54:t.254)
.300:t.010
1762 1 .254)
NON CUMULATIVE

NOTES
Refer to JEDEC Publication No 95 for Rules for Olmensioning

Measure from Max. 4>0

92CS-2Q296R3

AXial Lead Product Outlines
5.

Leads at giluge plane within 0,007" 10.178 mmJ radium of True
maximum material condition
~

MAX.

12.7

13 SPACES)

Position (TP)

(4.70)

t 50 )
.1 .070-.150
.015-.050
0.78- 3.81)
• I .39-1.27)LT=~"m!t~C=:-.J"
17.750I

at

Nt IS the quantity of allowable miSSing leads.
N

IS

the maximum quantity of lead pOSitions

L2.1~B2

applies between L2 and
0.500" 112.70 mm) from seating plane. Diameter IS uncontrolled
In II and beyond 0.500" (12.70 mm)
B applies between L 1 and

IT) Suffix (JEDEC MO-OO6-AF) H).. Lead TO-5 Style

SYMBOL

(V) Suffix
10 Formed Leads Radially
Arranged TO-5 Type
INCHES

A,
A2
,6
06,
,62

MIN.
0.230
0
0.165
0.016
0
0.016

,0

0.335

,

,0,
F,

J
k

L,
L2
L3
a

N
N,

MAX.

NOTE

TP

2

0
0.185
0.019

3

MAX.
5.84 TP

0

0
3

0.000

0.045
0.050

0.260
0.500

0.500
0.562

4
3
3
3

0.020
0.028
0.029

MIN.

,

0
0.533
9.39

8.50

1.01
0.863
1.14
1.27

0.5'
0.712
0.74

0.00
6.4

12.7
14.27

12.7

92CS -14638 R2

360TP

,

6
5

'0

1. Refer to Rules for Dimensioning Axial Lead Product Out·
lines.

4. Measure from Max. ¢O.

2. Leads at gauge plane within 0.007" (0.'78 mm) radius of

6. N is the maximum quantity of lead positions.

True Position (TP) at maximum material condition.

4.70
0.482

0.407
0
0.407
B.S1
7.75

360 TP

'0

0

4.19

0.021
0.370
0.335
0.040
0.034

0.305

MILLIMETERS

5. N, is the quantity of allowable missing leads.

3. 4IB appties between L1 and L2. ¢lB2 applies between l2
and 0.500" (12.70 mm) from seating plane. Diameter is

uncontrolled in II and beyond 0.500" 112.70 mm).

92CS-15835

__________________________________________________________________ 477

Dimensional Outlines
TO-5 STYLE PACKAGE (Cont'd)
(T) SuffixlJEDEC MO-006-AG h2-Lead TO-5 Style
SYMBOL

INCHES
MIN.
MAX.

I

NOTE

MILLIMETERS
MIN.
MAX.

•

0.230

2

5.84 TP'

1. Refer to Rules for Dimensioning Axial Lead Product Out-

linlS.

0

0

2. Leads at gauge plane within 0.007" (0.178 mm) radius of
True Position (TP) at maximum material condition.

3

4.19
0.407

4.70
0.482

3. 1t18 applies between L1 and L2. t/>B2 applies between L2

3

0
0.407

0
0.533

0.370
0.335

8.51
7.75

9.39
8.50

L,

0.020
0.028
0.029
0.000

0.040
0.034
0.045
0.050

4
3

0.51
0.712
0.74
0.00

1.01
0.863
1.14
1.27

L2
L3

0.250
0.500

0.500
0.562

3
3

6.4
12.7

12.7
14.27

Al

0

0

A2
OB
oB,
oB2

0.165
0.016

0.185
0.019

0
0.016

0
0.021

00

0.335
0.305

F,

"0,
j
k

92CS-19774

NOTES:

·
N

N,

30' TP
12
1

and 0.500" (12.70 mm) from seating plane. Diameter is
uncontrolled in L1 and bayond O.5~" (12.70 mm).

4. Measure from Max. tl>D.
5. N1 ts the quantity of allowable missing leads.
6. N is the maximum quantity of lead positions.

30 TP
12
1

6
5

JEDEC TO-72 PACKAGE::

INCHES

MILLIMETERS

...0
.0,
·,
A

""2

"h

,
k

·
"'2

BOTTOM
VIEW

Note 1 IFou.leadsJ M"lmum number Iuds omitted In U'1I10utline.
"none" 101 The number Ind position 01 Iuds 1C1\MIlly Pl"eMnt are
Indicated In the product rfl!JI,lratlQn Outline deslgnlilOn Mttf
mined bv the location and minimum INJUlir or linNr tPlC1ruj of Iny
two adlacent leads

NOTES

SYMBOL

MIN.

MAX.

MIN.

0.170

0.210

4.32
0.406
0.406
5.31
4.52
2.54
1.27

0016
0.021
0.016
0.019
0.209
0.230
0.178
0.195
a.lOOT.p.
0.050 T.P.
0.030
0.036
0.046
0.048
0.028
0.500
0.050
0.250
45 0 T.P.

0.914
0.111
12.10

MAX.

5.33
0.533
0.483
5.84
4.95
T.P.
T.P.
0.762
1.17
1.22
1.27

6.35
45 0 T.P.

2
2

Nole 2 IAlileadsJ Ob",applles between I, and I", Ob applies
between I", and 500" 112 70 mml from Rating plane Drame!er II
uncormofted In " and beyond 500·' 112 70 mmJ tram seating plane

4
4

Note 3 Meuured Irom mlxlmum dIameter of the product
Not. 4· Lflad,t'ta""l'Ig maximum d.ametet' Dig" 1483 mmlll"lN$Ured.n
gagmg plane 054" 11 37 mml • 001" t 025 mrot! - 000" I 000 mmJ
below the seatmg plane of the product sNiIi be WIthin 001" 1178 mml
ollne .. true pln.tlon relat.",. to a ma.,mum wldlt't tab

3
2
2
2
4.6

Not. 5' The product mav be measured by dlfect methods or bv ~
Not. 6; Tab cenlerllne

92CS-17444 RI

QUAD-IN-LiNE PLASTIC PACKAGES
(Q) Suffix 14-Lead Staggered
Recommended Mounting - Hole
Dimensions and Spacing

!-A+~~~E4- 4(~+'+ -+

'7A~:+L~~!~

!400

(10.16)

TYP.

.008-0.013

1

1--(0.204-0.330)

L

d~8)

--{<2.54)
TYP

TOP vIEW

(IN CIRCUIT BOARD)
92C5-14813

92CS-14812R2

1. Body width is measured 0.040"",02 mm) from toP. surface.
2. Seating plane defined as the junction of the angle with the
narrow portion of the lead.
Dimensions in parentheses are millimeter
equivalents of the basic inch dimensions.

~8

___________________________________________________________

Dimensional Outlines
QUAD IN-LINE PACKAGES (Cont'd)

(W) Suffix 16-LeBd Staggered

In;

.02~(.64IR. 16 15

.745-.785
118.93-19.931

14

13

12

II

10

9

MECHAI~g~i

, -

\!

INDEX
AREA

Recommended Mounting - Hole
Dimensions and Spacing

~

.240-.260
1.610-.6601

~

4

2

6
TOP
VIEW

.155-.200
(3.94-5.081

laCS-Hts.
NOTES:
1. Body width is measured 0.040" (1.02 mmJ from top surface.

2. Seating plane defined as the junction of the angla with the
narrow portion of the lead.

Dimensions in parentheses are millimeter
equivalents of the basic inch dimensions.

92CM-2e9nRI

(Q) Suffix 16-Lead

.7B5 (19.93)
.745
18.93
.025(.64) •.[;";" "

~:::~~~~

,. 12

J

.300
(7.62)
TVP

i

J~

Recommended Mounting - Hole
Dimensions and Spacing

10 •

::::::J~:

1254&

. 200
(~~:'I

"

171

1

a:g)

--t~060
.I
.Ol~ (1.90)
.39
---.l

t-

.050 1.27
.020(.51)

I

TERMLNAL No.1

, C:D-$-$-$___
I $-L!-$-

.200 (5.0B)
.155 3.94

,~

(2.54)
MIN.

_ _ _ _ _ _ _ _ _ _ _ _ TOP VIEW

JL~ ~:;(1.65)

(2.54)
TYP.

.035
.020 (,508)
. 014 .3!56

I

.B9

92CS -17S33RI

~
I~
:
~

.L.
.100-.120
(2.~4-3.04)

.990 25.15

r-

.030 (.761 OIA •

T'yP'

(IN

c:~~8,~EioAROI
92CS'17~80

Dimensions in parentheses are millimeter
equivalents of the basic inch dimensions.

(.203-.3~.0)

1.010 (25.65)

I (2'~~)

1. BodV width is measured 0.040"11.02 mml from top surfaca .
2. Seating plalle defined as the junction 01 the angle 'With the
narrow portion 01 the lead.

.00B-.013

20-Lead Shielded

-t

NOTES:

~

.790 (20.06)
.770 19.56
17 16 15 14 13

n
u

12

Recommended Mounting - Hole
Dimensions and Spacing

.030-.040
(.76-1.0il

~

~--~--$--$--$--

.260 (6.60)
~\6.'O

(;'.~,!,
r

I a,
'"
'"
'"
----+'j'--'P-'P-'P-

;4{.----------

.200

/

15.081

TERMINAL No.1

TOP VIEW

~ ~9--$--$--$-­

/ -(!/--! $-ffi--$-$-

~10'1
13..581
-i
TYP,

II-ll.541
.100
TYP

~0301.7610IA
18 HOLES

(IN CIRCUIT BOARDI
92CS-17~8'

J~L

.200
(5.0BI
TVP.
. 300
(7.62)

.008 _ .013
NOTE: TERMINALS II AND 20 ARE OMITTED.

(.204 - .3301

TYP.

J

NOTES:
1. Body width is measured 0.040"11.02 mm) from top surface.
2. Seating plane defined as the junction of the angle 'With the
narrow portion of the Iud .

Dimensions in parentheses are millimeter
equivalents of the basic inch dimensions.

92CS-I1!587RI
____________________________________________________________________
479

Dimensional Outlines
DUAL-IN-LINE AND QUAD-IN-LiNE PLASTIC PACKAGES
(Power Stud and Heat-Sink Types)
(E) Suffix
16-Lead "Power-Stud" Package

(EM) Suffix
Modified 16-Lead with Integral Heat Sink

",,"::::":~,1::
°1I§:~, ..
~ ~ 0::
~
jt

; Q Q lJ

Q

0.035(0.89)
0.0650.65)

MILLIMETERS AND ARE DERIVED
FROM THE BASIC INCH DIMENSIONS
AS INDICATED.

0.10412.642)
0.10712.717)DIA.
0.0400.02

~

0.014(0.356)
0.020(0.508)

DIMENSIONS IN PARENTHESES ARE IN

0.116 (2.947)10.075(1.90)
0.12213.099)

,-

g~~~\;~~)Jl~~~o-r.~~o-~-rH

002~~

-

-

~

00500.27)

B50

0.125(3.18)
0.15013.81)
(7.62)
--'j~0'300
0-15°

0.000
1
0015(039)
::\:
0.030(0.76)
00601(52)
GAUGE PLANE
0100 (2.54) TYP.
0.008(0.204)
0.013(0.330)
DIMENSIONS IN PARENTHESES ARE MILLIMETER
EQUIVALENTS OF THE BASIC INCH DIMENSIONS

** STUD
CENTERL INE
CENTERLINE WITHIN

(21.59)
MAX.

~~

92CS- 24134R3

(t) COINCIDES WITH BODY

±0.015

(Q) Suffix
Modified 16-Lead with Integral Bent Down Wing-Tab Heat Sink

fo~~~;~~r~51--~"
MECHANICAL ____.
INDEX
INDEX AREA

~-O'260
I-t

I

1

L

~~~,

I

:

-4 (6.38) f-0.145-0.1B5
(18.93-19.93)

10.150-0.160

;

! (3.810-4.064)

I J l?g~'i-9 ?l?

0.015-0,060

i!

LJ

(0.39-\.52) -,--

~O.035-0.065
(0.89-1.65)

(l0 161

0
?~~~~~9)

0020-0.070
(Q.51-1.771

I

PLANE

?o~i~:. ?·g:lo

II

-.

~

~

.. ?20~~:~~gl

JJ

-11,0014·0.023

T

1{0.356-0.584)

f

I-f6~~i:I~60515

0300
(762)

17040-00)75
----.l102-190

'

Lr::;:1
/
T
LSEATING

TYP

810~4.064)

I-

[

looT

TYP.

0400

0.150-0.160

3..

0.100 (2.54)
1

TYP.

lf

?2;~~)--

0.230 {5B421
[

~O.lOO (2.54)

0.650
(16.51)

r=

0745-0785
-{IB93-1993l

(102-190)

T

I

'

f21~~~~~/36111/ ~(~~~IL.
L

2 HOLES

0

I

~l~

/""'&'1

~0040-0075

(1.35)

~e-j-'
II
~

0.240-0.260
(6.10-6.60)

I

J

~ 0.053 DIA.

LSEATING 1*'11"":0014-0023
PLANE
I{O.356-0'58~

MECHANICAL
INDEX

INDEXAREA

C 0.230 (5.842)

/

0.0530IA.
(1.35)
2 HOLES

(6.10-6.60)

'

'

'I

(QM) Suffix
Modified 16-Lead with Integral Flat Wing-Tab Heat Sink

TYP

"I

I

I,I

I

.

IL L--i--1

I

0.10012.541 TYP.

0200 {5.0BI TYP.
0.008-0.013

(0.204-0.330)
92CM-25045R3

DIMENSIONS IN PARENTHESES ARE MILLIMETER
EQUIVALENTS OF THE BASIC INCH DIMENSIONS

DIMENSIONS IN PARENTHESES ARE MILLIMETER
EQUIVALENTS OF THE BASIC INCH DIMENSIONS

480 _________________________________________________________________

Dimensional Outlines
DUAL-IN-LiNE AND QUAD-IN-LINE PLASTIC PACKAGES
(Power Stud a d Heat-Sink Types)
(EM) Suffix
16-Lead with Integral Strap Heat Sink

(OM) Suffix
H)· Lead Staggered with Integral Strap Heat Sink
END ALIGNMENT OF HEAT SINK
END ALIGNMENT OF HEAT SINK
TO CENTER OF PLASTIC BODY

TO CENTER OF PLASTIC BODY

L _ _++-~_ gi:8~li~b ~~~A~N(2)
0.030-0·036
--(0.76-0.91 )

CONDUCTIVE EPOXY

EPOXY 12 DABS)

0,155-0.200

I

{394~

0.300

'~ :I
125-0150

a

100 (2.54)TYP

I

~

(318-3.81)

I~o
00

J~'300

(1.621 TYP.
CENTER OF LEAD

J

0.020- 0.050T
(0.51-1.27)

f1

I

-..LII
I

0·350

:

(8.89)

~L'25-~

0.100 (2.54)TYP.

"o

J~'~8)TYP'

D.IS-3.BI)

La.cls-c.OGO

CENTER OF LEAD

(0.39-1.52)

0.008-0,013
(0.204-0.330)

0.008-0.013

(0.204-0.330)

TO-220-STYLE (VERSA-V) PLASTIC PACKAGE
HORIZONTAL MOUNT

VERTICAL MOUNT

SYMBOL

INCHES
MIN.

MILLIMETERS

SYMBOL

MAX.

A

0.876 0.896 22.25

22.75

A

B

0.396
0.173
0.604
0.263
0.168
0.100

10.36
4.622
15.72
6.934
4.775

B

C

0
E

F
G
H

J

K
L
M

0.408 10.06
0.182
4.395
0.619 15.35
0.273 6.681
0.188 4.268
0.104 2.540
0.320 0.340 8.128
0.246 0.254 6.249
1.169
0.046 0.054
0.496 0.508 12.60
0.140 0.150 3.556

F

J
K

H

L

3.810

M

P
R

0.381

Q

0.033 0.040

0.839

0.406
1.016

R

0.129 0.139

3.277
0.600 0.630 15.24
0.680 0.710 17.27

3.530
16.00
18.03

T

E

6.451
1.371

5
0.015 0.020

S

D

G

P

N

C

2.641
8.638

"12.90""
5

INCHES
MIN.

MAX. MIN.

N
Q

(M Suffix)

MILLIMETERS

MAX. MIN.

MAX.

18.94

0.726 0.746 18.44
0.396 0.408 10.06
4.395
0.173 0.182

10.36
4.622
15.72
6.934
6.375
2.641
4.140
6.451
1.371
12.90
3.810

0.619 15.35
0.273 6.681
5.614
0.251
2.540
0.104
3.633
0.163
0.254
6.249
1.169
0.054
0.496 0.508 12.60
3.556
0.140 0.150

0.604
0.263
0.221
0.100
0.143
0.246
0.046

5
0.015 0.020
0.033 0.040
0.129 0.139

5
0.381

0.406

0.839

1.016
3.530

3.277

____________________________________________________________________ 481

482 ____________________________________________________________________

Application Notes

_ _ _ _ _ _ _ _ _ _ _ _ 483

AN·4431
RF Applications of the
Dual-Gate MOS FET up to 500 MHz
by L. S. Baar
The RCA dual-gate protected, metal-oxide silicon,
field-effect transistor (MOS FET) is especially useful for
high·frequency applications in RF amplifier circuits. The

dual-gate feature permits the design of simple AGe circuitry
requiring very low power. The integrated diodes protect the

gates against damage due to static discharge that may develop
during handling and usage. This Note describes the use of the
RCA·3N200 dual1!3te MOS FET in RF application,. The
3N200 has good power gain and a low noise factor at
frequencies up to 500 MHz, offers especially good crossmodulation performance, and has a wide dynamic range; its
low·feedback capacitance provides stable performance
without neutralization.

where:
~IDS is the current range given in the 3N2oo technical

bulletin
.6.IDQ is the desired range of operating current
gfs(min.) is the minimum forward transconductance
at 1000 Hz

~
~

LEAD' . DRAIN
LEAD 2· GATE NO.2
LEAD 3· GATE NO.1
LEAD 4 • SOURCE. SUBSTRATE,
AND CASE

Rs

Opontin9 Conditions
Typical two·port characteristics at 400 MHz including
both "y" and "s" parameters, are given for the 3N200 in the
RCA technical bulletin, File No. 437. This note makes use of
the "y" parameters; however, designers who prefer the
alternate method can, by parallel ana1ysis, make use of the
"s" parameters.
A recommended operating drain current (ID) for the
3N200 is approximately 10 milliamperes with Gate No.2
sufficiently forward biased such that a change in the bias
voltage does not greatly affect the drain current. An
adequate Gate No. 2-to-source voltage (VG2S) is approximately +4 volts. The forward transadmittance (YfS> increases
with drain current. but saturates at higher current levels. The
increase in RF performance at drain currents above 10
milliamperes is achieved only with less efficient use of input
power.
To establish the optimum operating conditions for a
type, consideration must be given to the range of variations
in characteristics values encountered in production quantities
of the type.2 One important measure of type variation is the
range of zero bias drain current (IDS). The current range
given in the 3N200 technica1 bulletin for IDS is from 0.5 rnA
to 12 rnA. A fIXed bias condition intended to center the
range of drain current at the desired level, still wiD produce
an operating drain current range of 115 milliamperes with a
resultant wide range of forward transconductance (gfsl. The
drain current can be regulated by applying dc feedback with
a bypassed source resistor (Rs). A good approximation of Rs
(where IDQ ~ los/2) can be calculated by the uae of the
following formula-, assuming that VGlS ¥s. IDS is linear
over the current range under consideration:

RS'"

( I)
--

gf,(min.)

-See Appendix
~4

(

aIDS -1\
AIDQ

')

= --:..-~--

I I

Eq.2

Yrs (I

Eq.S

+ cos 0 )

where:

8

IDQ -IDS

=LYfs + LYrs

K = skew factor

Eq.3

Lyrs

gf,(avg.)

= angle

of reverse transadmittance

Lns = angle of forward transadmittance

where:
gfs(avg.) is the average forward transconductance
To establish the Gate·No. 2 Voltage (VG2), follow the
same procedure described for calculating the Gate·No. 1
Voltage, except that a fixed VG2S of approximately 4 volts
is adequate.
If gain control is desired. apply a negative·going voltage
to Gate No.2. Because Gate No.2 has little control in the
voltage range of +2 to +5 volts, this characteristic may be
used to effect AGe delay of the device in order to maintain
the low noise figure until the RF signal is out of the noise·level
range.

The skew factor, introduced in this equation, is a safety
measure that establishes an arbitrary degree of skewing in the
frequency response which may be introduced by regenera·
tion. A value of 0.2 for K has been established on the basis of
past experience. The value of MUG calculated at 400 MHz is
13.8 dB. This value of MUG is greater than the value of
MAG, again indicating unconditional stability, since MAG,
ignoring inherent feedback, is the conjugately matched gain.
Therefore, neutralization or circuit loading is not required to
insure stable performance, and the gain can approach MAG.
limited only by circuit losses.
Reverse transadmittance (Yrs) is composed of several
components, but the major ones are feedback capacitance

(C ISs) and source-lead inductance (LS). Therefore. care must
be exercised in the application of the Yrs values, shown in

Typical ''y'' parameter data as a function of frequency
are given in Table 1. Maximum available gain (MAG) cal·
cuJated from these data are also included to indicate ideal
gain performance {i.e., yrs =0). The ability of the MOS FET
to approach these gain levels depends on the device maintaining stable performance at the required operating fre·
quency.
There are several methods which may be used to test for
gain vs. stability. One of these methods, the linvill Criteria
(C). is defined by the equation:
C=

Imi

2K

MUG

VGI = VGIS + IDQ

Stability Considerations

Fig. 1 - Terminal diagram for the 3N200.

The follOWing equation for Maximum Usable Gain
(MUG)3 is:

With the value of Rs established, then the Gate·No.
Voltage (VG}) can be calculated from the equation

where VGIS is estimated by:

Gn.Protection Diodes
Fig. 1 shows the terminal diagram for the 3N200.
Gate No. 1 is the input signal electrode and Gate No.2
is normally used to obtain gain control. The back-to-back
diodes are connected from each of the gates to the
source terminal, lead No.4. If short duration pulses
greater than :1:10 volts, generated for example by static
discharge. are inadvertently applied to either gate, the
protective diodes limit these voltages and shunt the current
to the source termina1. Thus the gates, under normal
operating conditions. are protected against the effects of
overload voltages.•

A value for C which is less than I indicates uncondi·
tional stability. Applying the 4oo·MHz values taken from
Table I to the Linvill Criteria yields a value of C = 0.615;
substantially less than the value indicating unconditional
stability_.

Yrs Yfs
2gi , So, - Re (Y" Yf,)

Eq.4

CHARACTERISTICS

Table 1, at the upper end of the usable frequency range. The
3N200 utilizes a JEDEC TO·72 package that has 4 leads. The
data in Table 1 was compiled with the use of a socket which
contacts the leads of the 3N200 as close as possible to the
bottom of the package as specified by the JEDEC Standard
Proposal SP·102S "Measurement of VHF·UHF "y" Parameters". The leads are shielded from each other to eliminate
stray capacitance between the leads. but some lead induct·
ance is inevitable. If the device is soldered directly to the
circuit components using commercial production techniques
rather than by precise laboratory methods, then additional
source lead inductance can be expected. Also, some
additional capacitive coupling may result if the input and
output circuits are not completely isolated from each other.

FREQUENCY (MHz)

SYMBOL

UNITS

100

200

300

400

500

0.25

0.8

2.0

3.6

6.2

mmho
mmho

V Parameters

Input Conductance

9is

Input Susceptance

bis

Magnitude of Forward Transadmittance

IVI, I

Angle of Forward Transadmittance

/:!..t,

3.4

5.8

8.5

11.2

15.5

15.3

15.3

15.4

15.5

16.3

mmho

·15.0

·25.0

-35.0

·47.0

·60.0

degrees

Output Conductance

9o,

0.15

0.3

0.5

0.8

1.1

mmho

Output Susceptance

bo,

1.5

2.7

3.6

4.25

5.4

mmho

0.025

0.06

Magnitude of Reverse Transadmittance

IVrs I

Angle of Reverse Transadmittance

/:!.rs

0.012
-60.0

·25.0

0

32.0

24.0

17.5

0.14

0.26

mmho

14.0

20.0

degrees

13

10.0

dB

Eq.1
Maximum Available Gain

MAG

Table 1 - "y" Parameters from 100 to 500 MHz

_______________________________________________________________

AN-4431
Because the published Yrs value for the 3N200 is very
small. the circuit Yrs values may differ significantly from the
Yrs values shown in Table I and hence, may result in an
unstable operating condition. It is impossible 10 provide data
for all possible mounting combinations, therefore. a recommended mounting arrangement is shown in Fig. 2. The
source and substrate in the TO-72 package of the 3N200 are
internally connected to lead No. 4 and the case. The
source·lead inductance can be reduced. if the case is used as
the source connection. Fig. 2 illustrates a partial component
layout in which tilt: case is held by a clamp or other fingered
device. The clamp is soldered tll a feed through capacitor to
provide an effective. very-low inductance bypass to RF
signals. This mounting arrangement still permits the use of a
source resistor for DC stability. and enables the case to
provide isolation between the input and output circuit in
addition to the isulation afforded by the shield.

When receiver sensitivity is an important consideration
in the design of an RF amplifier. a compromise must be
made in the circuit power gain to achieve a lower noise
factor. A contour plot of noise figure as a function of
generator source admittance is shown in Fig. 4. Each contour
is a plot of noise figure as a function of the generator source
conductance and susceptance. Data for the noise figure were
obtained from a test amplifier designed with very low
feedback. Even though the area of very low-noise figure in
the curves in Fig.4 cover a broad range of source admittance,
impedance.matching for maximum power gain could result in

gain, especiaUy in an RF amplifier intended for the input
stage of a receiver.
In addition to the protection afforded in nonnal
handling. the diodes also provide in-circuit protection against
events such as: static discharge due to contact with the
antenna, delay in transmit-receive switching. or connection
of an antenna with an accumulated charge to the receiver.
Crossmodulation
Crossmodulation is an important consideration because
it is an inherent device characteristic where circuit considerations are secondary. Crossmodulation is the transfer of
modulation from an undesired signal on a desired signal
caused by the non-linear characteristics of a device.
Crossmodulation is proportional to the third-order term
of the expansion of the 10 - Ves curve. It is normally
specified as the undesired signal voltage required to produce
a crossmodulation factor of 0.01. The crossmodulation
factor is defined as the percent modulation on a desired
carrier by the modulated undesired signal divided by the
percent modulation of the undesired signal. 4
Inspection of the In - VGJS curve of Fig. 5 offen an
insight to the possible crossmodulation as a function of
gain-reduction performance. When both channels of the
3N200 are fully conducting current. as shown by the VG2S =
4-volt curve, the device approximately roDows a square·law
characteristic. If the 10 - VGlS curve was ideal. the
third-order term would be zero; but in practical cases, the
third-order tenn and crossmodulation have some low values.

Fig. 4 - Noiss factor vs. generator source (input) admittance

TOP VIEW

(Yi.J

SHIELD

TUN"G~

CAPACITOR C2

O,AMP
FEEDTHROUGH
CAPACITOR (7

SIDE VIEW

Fig. 2 - Partial component layout of 4OD-MHz amplifier
circuit

The reduction of source-lead inductance provides in
addition to greater stability, a lower input and output
conductance. Table 2 shows the differences in ''y'' parameter
V'•.tIues at 400 MHz when measured with the source connection made to lead No. 4 (in accordance with. the
published data for the 3N200) and when measured with the
case connected directly to the ground plane of the test jig.
The magnitude of reverse transadmittance is halved with a
significant change in its phase angle. The input conductance
is reduced by 30%. and the output conductance is reduced by
13%. A recalculation of the expressions for MAG, MUG. and
Unvill Criteria (C) shows a significant improvement in gain
and circuit stability.
While it is difl'icult to provide accurate information on
the effects of shielding between the input and output
circuits. its effect can be demonstrated when all other
feedback components have been reduced to negligible values.
The circuit. shown in Fig. 3 (for component layout see Fig.
2). was measured both with and without a shield. The
maximum gain. without the shield, averaged 0.8 dB lower
than with the use of the shield.

Maximum Available Power Gain

c,
c,

,,:sOOPF....

"00

Fig. 3 - 4DO-MHz amp/if;",. circuit

~

til

..

I-- r-..J

l///

~

.• f-- - I : -I

.3-1

Fig. 5 - Drain cummt (IOJ .... I/Bte No. 7·lfHDu,..
(VG7SJ

SYMBOL

FREQUENCY III .400 MHz

I/O"

UNITS

Case
Grounded

13.0

15.7

dB

Maximum Usable Power Gain (unneutralized)

MUG

13.8

19.4

dB

Linvill Stability Factor, C

C

0.615

0

,

,

0
0.0
GATE No.l-lO-SOURCE VOLTAGEIVGIS}-V

MAG

0.335

mmho

"y" Parameters

Input Conductance

9is

3.6

2.5

mmho

Input Susceptance

bis

11.2

11.7

mmho

Magnitude of Forward Transadmittance

I Vis I

15.5

15.5

mmho

Angle of Forward Transadmittance

I:!.fs

·47.0

-40.0

degrees

!!os

0.8

0.65

mmho

bas

4.25

4.25

mmho

Output Susceptance
MaWlitude of Reverse Transadmittance

1.5-i5.4pF

",

/

{/

Normal
Connection

Output Conductance

L,

1/

'0

The diodes incorporated into RCA dual·gate MOS
FETs. for gate protection, have been designed to minimize
RF loading on the input circuits. The small amount of RF
loading results in \only a fraction of a dB loss in power gain
and a negligible increase in the noise figure_ The advantages
of diode protection, greatly outweigh the slight loss in power
CHARACTERISTICS

AMBIENT TEMPEAATlJREITA,-2S-C
OAAIN-TO-SOURCE VOLTS IYDsl-"

12

0.18 ProI8ction Diad..

+1i5V

c,

.i "..

a relatively poor noise figure. As shown in Table 2, the input
conductance (giS> with the case grounded is 2.S mmho. With
the reactive portion tuned out. the noise factor at power
matched conditions is almost I dB higher than the optimum
noise figure. However. matching to 5.0 mmho results
in a near optimum noise factor with a loss of only 0.5 dB in
gain. In addition, impedance matching to high conductance
also benefits crossmodulation performance, as will be discussed in a later section.

Angle of Reverse Transadmittance

I Vrs I
/:!..rs

0.14
14.0

0.07
49.0

mmho
degrees

Table 2 - '.y'. Parameters at 400 MHz with source connection to lead No.4 and with case connected to tJ'OUnd plane
ot test jig

485

AN-4431
When the gain is reduced, by the application of bias to Gate
No.2. the square-law characteristic changes to a curve with a
knee. Sharp curvatures usually result in larger hi&h-order
terms and poorer crossmodulation performance can be
expected at lower gain conditions. If in Fig. 6. Cirfmit A. we
assume a fIXed bias (VGlS) of approximately +0.4 volt, then
the expected variation in erossmodulation is determined at
the points where the ordinate at VGtS = +0.4 volt crosses
the curves. Crossmodulation performance at values ofVG2S
= +4 volts to cutoff is as follows: good (low crossmodulation) at +4 volts. poorer at +2 volts. poorest at +1 volt. and
again improves from zero volts to cutoff.
vD•

VDD

,

AOC
VOLTS

The typical COMS in Fig. A2 show drain current ...
Gate No. I-to-Source Voltage as a function of lOS level.
These curves are almost linear when the typical operatinS
drain current is in the IO.milliampere region. For the
remainder of the analysis a linear relationship will be
assumed for the required range of quiescent current. The
assumption of linearity dictates that Sfs is a constant.
The required range of drain current is ID2 ~ IDI
where:
gf. VGI
lOS (max.)
ID2 = - - - + - - - l+gf.RS
l+gf,RS

Summ.-y

GATE

GATE.

GATE

NO.2

NO.2

CIRCUIT A

the Gate No. 2 curves where the curvature is less severe,
indicating as shown by Fig. 7, Curve C an improvement in
crossmodulation pedormance. A further slight improvement
is po.sible by the use of a higher initial operating drain
cunent, which effectively moves the intercepts to the ript
on each cum. This improvement is indicated in Fig. 7.
Curve D.
The curves in Fig. 1 establish that the biasing
arrangement which provides optimum crossmodulation
performance is the one in which Gate No. I forward bias
increases as Gate No.2 controls the gain. This biasing
anangement is easlly accomplished by the use of a faxed Gate
No. I voltage and a source resistor. As the Gate No.2 bias
voltage .reduces the drain current, there is also a decrease in
source voltage and an increase in the Gate No. I-to-80urce
voltage. The sate-to-source voltage ratings must not be
exceeded under any circumstances.

CIRCUIT B

NO.2

CIRCUIT C

Fig. 6 - Biasing circuits uting the 3N2fX)

Curve A. Fig. 7 shows a curve of the undesired signal
with a crossmodulation factor of 0.01 as a function of gain

reduction. The curve indicates perfonnance is poorest when
gain reduction is in the 3~ to IS-dB region; this region repre~
sents a Gate No.2-voltage range of approximately 0.5 volt to
2 volts. The exception to the poor crossmodulation pedonnDESIRED SIGNALII O,056MHI

An RF amplifier, ideally, should provide high gain, a
low-noise figure. and low crossmodulation. The 3N200 offers
a good compromise in providing these three features. As
indicated. in the section on "Stability Considerations" a
mismatch at the circuit input to a higher conductance level,
provides an improved noise figure. The same mismatch
condition also improves crossmodulation performance. The
input signal at the gate of the device. when mismatched as
indicated above, is lower than if it is power matched. The
same ratio applies to any undesired signal and, thus, reduces
the possibUity of crossmodulation interference.

LIlD=ID2- 1D1 =

IDS (max.) -lOS (min.)
1+ gf.

Rs

LlIDS
= --1+ gf, RS

Solving the above equation (or RS gives
(LlIDS/LlID)-1
RS=--gf.
where:
Ifs is equal to the expected minimum value at the
required ID

Appendix
The drain current of a device is established by the
relationship

•
•

where:
lOS =drain current

{r 1- 7l

Vos-+IIIY
Yo2S .. +4Y

",I!I

0

•

at:

.1---,....-

VGlS = 0, VG2S = +4 volt•.

•
-

If a source resistor is used. as shown in Fig. AI. the gate
No. I-to-source voltage is

0

VGlS=VGl-IDRS

/;
il7 7
, / /

Ii/ / //

-I

0

J
I

GAT£ Na.1-TQ· SOURC£ VOLTAGE IVGISI-V

then

ID=8f.(VGI-ID Rs)+IOS

'D~O--~~~~--~~--'4~O--~~~~~~7'O
GAIN REOUCTION I.BI

Fig. 7 - Crossmodul,tion vs. gain tflduction using b_ng
circuits shown in Fig. 6

8fs VGI
ID=--- +
1+8f,Rs

Fig. A2 - Drain current VI- flBte No. '-to·source vol.

or

IDS
1+8f,Rs

Referenoes:
I.

ance in this range is the sharp peak which occurs at the S-dB
level and is due to a curve inversion that takes place just prior
to the knee. Beyond the lS-dB level, crossmodulation
generally shows an improvement.
If Gate No. 1 is also reverse biased in conjunction with
Gate No.2 in the manner shown in Fig_ 6. Circuit B. then the
overall performance is poorer because the Gate No. 1 voltage
will tend to follow the knee of each curve. This occunence is
evident in Fig. 7. Curve B. If Gate No. 1 is biased as shown in
Fig. 6. Circuit C, the Gate No. I-to-Source voltage intercepts

486

2.
3.

4.

Fig. AI - Bias circuit using the 3N200

L. A. Jacobus and S. Reich. "Design of Gate-Protected
MOS Field-Effect Transistors", RCA Application Note
AN4018
S. Reich. uField~E(fect Transistor Biasing Techniques",
EEE, Sept. 1970
R. A. Santilli, "RF and IF Amplifier Design Considentions". IEEE Transactions on Broadeait and TV
ReceiveR. Nov. 1967
H. Thanos. ''Crossmodulation on Transistorized 'IV
TuneD". IEEE Transactions on Broadcast and 1V
Receivers, Vol. 9 No.3, Nov. 1963

ICAN-6048

Some Applications of a Programmable
Power/Switch Amplifier
by L. R. Campbell and H. A. Wittlinger
The RCA·CA3094 unique monolithic programmable power

switl..:h/amplifier Ie consists of a high-gain preamplifier drivin~
a power-output amplifier stage. It can deliver average power ot
3 watts or peak power of 10 watts to an external load. and
can be operated from either a single or dual power supply.
This Note briet1y describes the characteristics of the CA3094.

and illustrates its use in the following circuit applications:

Class A instrumentations and power amplifiers
Class A driver-amplifier for complementary power Iran·
sistors

Wide·frequency-range power multivibrators

Current- or voltage-controlled oscillators
Comparators (threshold detectors)
Voltage regulators
Analog timers (long time delays)
Alarm systems
Motor.speed controllers
Thyristor·firing circuits
Battery·charger regulator circuits
Ground·fault-interrupter circuits

Circuit Description
The CA3094 series of devices offers a unique combination
of circuit flexibility and power-handling capability. Although
. these monolithic IC's dissipate only a few miclOwatts when
quiescent. they have a high current-output capability (100
milliamperes average. 300 milliamperes peak) in the active
state, and the premium·grade devices can operate at supply
voltages up to 44 volts.
Fig. I shows a schematic diagram of the CA3094. The portion of the circuit preceding transistors Qll and QI3 is the
preamplifier section and is generically similar to that of
the RCA-CA3080 Operational Transconductance Amplifier
{OTA).1.2 The CA3094 circuits can be gain-programmed by
either digital and/or analog signals applied to a separate
Amplifier.Bias.Currenl (IABC) terminal (No.5 in Fig. I) to
control circuit sensitivity. Response of the amplifier is es·
sentially linear as a function of the current at terminal 5.
This additional signal input "pori" provides added Oexibility'
in many applications. Thus. the lIutput of the amplil1er is a
function of input signals applied differentially at terminals :!
and 3 and/or in a single-ended configuration at terminalS. The
output portion of the 1Il0nolithk circuit in the CA30Q4 con·
sists of a Darlington·connected transiswr pair with ac..:ess provided to hoth the ..:ullectur and emitter terminals to provide
capability to "sink" and/or "source" CUTrenl.

r-----.....,,,r-r----8.4 v

The CA3094 series of circuits consists of six types that dif·
fer only in voltage·handling capability and package opt.ions. as
shown belOW; other electrical characteristics are identical.
Package Options

Maximum Voltage Rating

CA3094S; CAJ094T
CA3094AS; CA3094AT
CA3094BS; CA3094BT

24V
36V
44V

The sufflx. "S" indicates circuits packaged in TO·S enclosures
with leads formed to an 8·lead dual-in-line configuration (0.'"
pin spacing). The suffix "T" indicates circuits packaged in 8lead TO-5 enclosures with straight leads. The generic CA3094
type designation is used throughout this Note.
Class A Instrumentation Amplifiers
One of the more difficult instrumentation problems fre·
quently encountered is the conversion of a differential input
signal to a single-ended output signal. Although this conver·
sion can be accomplished in a straightforward design through
the use of classical op-amps, the stringent matching require·
ments of resistor ratios in feedback networks make the can·
v.ersion particularly difficult from a practical standpOint.
Because the gain of the preamplifier section in the CA3094
can be defined as the product of the transconductance
and the load resistance (gm RL). feedback is not needed to
obtain predictable open-loop gain performance. Fig. 1 shows
the CA3094 in this basic type of circuit.

'2tS·,OU,

Fig.3-Single·supply dlfferential·bridge amplifier.

'04

44001
-10 V

PRE-AMP GAIN 1Av1o II", RL ·t~JUO-31{36I(1031'180
(OUTPUT AT TERMINAL I)

r:~;I~;::oO)(~~ATIOH: DIFFERENTIAL INPUT

F;g.4-Singill'supply amplifier for MermDCaupie si",.I••

::1 H6 ",vl

DEVIATION FROM
LINEARITY)
OUTPUT VOLTAGE CEO J 'AV It 'ditl) • U80H126 ",v,·:t 4.7 V
OUTPUT CURRENT, to.~

I

• B.3~ ",A
"

nCSlO?&&

Fig.2-0pen·/aop instrumentation amplifier with differential
input and singlfl·ended output.

The gain of the preamplifier section (to terminal No.1) is
(5 x 10-3 ) (36 x 103)
180. The !ranscon·
ductance gm is a function of the current inlo terminal No.5,
IABC. the amplifier-bias-currenl. In this circuit an IABC of
260 microamperes results in a 8m of 5 millimhos. The operating point of the output stage is controlled by the 2-kilohm
potentiometer. With no differential input signal (ediff = 0).
this potentiometer is adjusted to obtain a qUiescent output
current 10 of 12 milliamperes. This output current is estab·
lished by the S60-ohm emitter resistor. RE. as follows:

gm RL

=

=

10'"

The CAJ094 is attractive for power.amplifier service be·
cause the output transistor can control current up to'IOO
milliamperes (300 milliamperes peak), the premium devices
.'J1.le c~mponents of the RC network are chosen so that

., IIIrnRl U , chll)

o

",'an A Power Amplifiers

2'~C ~2MHz.
(CAJ094B) can operate at supply voltages up to 44 volts. and
the TO-5 package can dissipate power up to 1.6 watts when
equipped with a suitable heat sink that limits the ~ase temperature to 55°C.
Fig. 5 shows a Class A amplifier circuit using the C AJ094A
that is capable of delivering ;!80 mllliwatts to a 3S0-ohm reo
sistive load. This circuit has a voltage gain of 60 dB and a
IRI
10lCS·20408

Fig. T2-Astable power multiribrator with prorisions for
varying duty cycle.

Fig. 13 shows a drcuit incorporating independent controls
(RON and RoFFl to establish the "on" and "off" periods of
the current supplied to the LED. The network between points
"A" and "B" is analogous in function to that of the 100kilohm resistor R in Fig. 12.

Ii

:;J::
:

LOWER THRESHOLD'

:1':::' :["
IlL'

H:::::::H~,:'::

'1:"/1'::::::::

:;:1':[:::1::::::
:::~::::F::::"
100

200

AM~LIFIER

JOO
-4(
00
BIAS CURRENT ~rA8C)-fl-A

Ib) SINGLE SUPPLY

Fig.1B-Comparllwrs (threshold det(JCtors) - dUIJ/- and single·supply
types.

Fig. 19 shows a dual-limit threshold detector cirCUit in
which the high-level limit IS established by potentiometer RI

Fig. '6-Frequency as a function of 'ABC for C='OOO pF
for circuit in Fig. 15.

92C$-20555

Fig. 13-Astable power multiribrator With provisions for
independent control of LED "on·off" periods.

ate resistor (R) in series with terminal 5 in Fig. 15 converts the
circuit into a voltage-controlled oscillator. Linearity with respect to either current or voltage control is within I per cent
over the middle half of the characteristics. However, variation
in the symmetry of the output pulses as a function of frequency is an inherent characteristic of the circuit in Fig. 15,
and leads to distortion when this circuit is used to drive the
phase detector in phase.locked-Ioop applications. This type of
distortion can be eliminated by interposing an appropriate
flip-flop between the output of the oscillator and the phaselocked discriminator circuits.

---HIGH
DEAD
} ZONE

--cow

e

TIle AJ094 is also suitable for use in monos table multlvibrators. as shown in Fig. 14.ln essem:e, this cirCUIt is a pulse
counter in which the duration of the output pulses is inde·
pendent of trigger-pulse duration. The meter reading is a function of the pulse repetition rate which can be monitored with
the speaker.

Fig. '9-Dual·l,mit threshold detector.

and the low-level limIt b ~et by potentiometer R2 to actuate
the C AJ080 low·limit detct.:tor. 1,2 A positive output signal IS
delivered by the C A3094 whenever the input Signal exceeds
either the hlgh·limil or the low·limit values established by the
appropriate potentiometer settings. TIlis output voltage is approximately I ~ volts with the wt.:uit shown.
The high current-handling caP'1bility of the C AJ094 makes
It useful In Sdllllltt power·trigger circuits such as that shown
in Fig. 20. In thIS cirt.:uit, a relay coil is switt.:bed whenever the

100
200
AMPLIFIER BIAS CURRENT IrABCI-fl-A
1l2CS-20284

Fig. 17-Frequency asa function of 'ABC far C-l00pF
for circuit in Fig. 15.

InIOOpF"

,

>--I

TRIGGER

INPUT. *FULL.SCAL[

DErL[CT1ON.npULS[S/S~C

Fig. ,4-Power monostable mu/tivibrator.

Current- or Voltage-Controlled Oscillators
Because the transconductance of the CA3094 varies linearly as a function of the amplifier bias current (lASC) supplied to terminal 5, the design of a current- or voltage-controlled oscillator is straightforward, as shown in Fig. 15.
Fig. 16 and 17 show oscillator frequency as a function of
IABC for a current-controlled oscillator for two different
values of capacitor C in Fig. 15. The addition of an appropri-

Comparators (Threshold Detectors)
Comparator circuits are easily implemented with the
CA3094, as shown by the circuits in Fig. 18. The circuit of
Fig. 18(a) is arranged for dual-supply operation; the input voltage exceeds the positive threshold, the output voltage swings
essentially to the negative supply-voltage rail (it is assumed
that there is negligible resistive loading on the output terminal). An input voltage that exceeds the negative threshold
value results in a positive voltage output essentially equal to
the positive supply voltage. The circuit in Fig. 18(b), connected for single-supply operation, functions similarly.

IOOKfI

LOWER TRIP POINTII(30-0

OZ6R~R:;R3

Fig.2V-PreclsiOn Schmitt power·trigger cirCUit.

_____________________________________________________________________ 489

ICAN-6048
input signal traverses a prescribed upper or lower trip poin!. as

"

r.JOy'\lV--,

defined by the following expressions:

r -_ _ _ _ _ _ _ _ _ _ _ _ _ _~"""''\_'W\r't8I11.Q

Upper Trip Point = 30 ( RI + ~ + R3)
Lower Trip Point

~ (30

----..?

:+'0011

tNINE UI,UI. FlESISTOFlSIN SEFlIESl

- O.026RI) R:! ~3 R3

"'"

The circuit is applicable, for example, to automatic ranging.
With the vaJues shown in Fig. 20. the relay coil is energized
when the input exceeds approximately 5.9 volts and remains
energized until the input signal drops below approximately
5.5 volts.
Power·Supply Regulators
The CA3094 is an ideal companion device to the CA3085

series regulator circuits4 in dual-voltage tracking regulators

.""

that handle currents up to 100 milliamperes. In the circuit of

Fig. ~I. the magnitude of the regulated positive voltage pro·
vided by the CA3085A is adjusted by potentiometer R. A
sample of this positive regulated voltage supplies the power
for the CA3094A negative regulator and also supplies a refer·

Fig.22-Rtlgufllred high·voftagtllupply.

least I volt at terminal 2 to insure operation within the
common-mode-input range of the device. The diode limits the
maximum differential input voltage to 5 volts. Gross changes
in time·range selection are made' with switch S2, and vernier
trimming adjustments are made ..,ith potentiometer ~.

.V+-'NPUT A...... GE·"tO 50 v '--"'VV'.c---'
~i)~ ,~v

i)ur""lT

•• V-''''PUT " ........[·_IE

ro·,ov

~u

,1"'['

lUX ,0.0.0'

40529 TURNS·OF"'" AFTER
EXPIFlATION OF TIME DELAY

TI~E

RI.o.eIMQ~~.

[\{:UuTrIiNITI.~IJ4VI'" "OO'OOl'~/V
:~OTU;'N'TI"'U '~O.OOT~'IIo
Il~ '~MI

VOUT

TQ50 ......

R2"5.IW.a -301011"1.
","22 MD. • 2H"S.
R4'44Mll· 4HRS.

R5 "2.7 I I mA

Fig. 9-

Oscilloscope photograph of the CA3080 transfer

characteristic as applied to the circuit of Fig. 6.

linearity of the transfer characteristk. Reduced input
impedance does result from this shunl connection. Similar
tedlniques could be used un the OTA output. but then the
output signal would be reduced and the correction circuitry
further removed from the source of non-linearity. It must be

emphasized Ihal the input circuitry is differential.
Simplified Differential·lnput to Single·Ended
Output Conversion
One of Ihe nIllre exacling configurations for operational
amplifiers is the differential·to·single·ended conversion
circuit. Fig. 10 shows some of the basic circuits Ihat are
usually employed. The ralios of Ihe resistors must be
precisely matched to assure the desired common·mode
rejection. Fig. II shows another system using Ihe CA3080 to
obtain this conversion without the use of precision resistors.
Differential input signals must be kept under ±26·millivoIIS
for better than 5·percent non·linearity. The common·mode
range is that of the CA3080 differential amplifier. In

DIFFERENTIAL [
INPuT
_AA.,_...fi'..J

A'
@

Gin 1'1 L
')(;"J IJ.A •

"'" "" ,{ mmhos
:. A ' IOrnmhO$' I\.. K

Fig. 11- A differential·to·single-ended conversion circuit
without precision resistors.

A complete power amplifier using the CA3094 and three
additional transistors is shown schematically in Fig. 14. The
amplifier is shown in a single·channel configuration, but
power-supply values are designed to support a minimum of
two channels. The output section comprises QI and Q2,
complementary epitaxial units connected in the familiar
"bootstrap" arrangement. Capacitor C3 provides added base
drive for QI during positive excursions of the output. The
circuit can be operated from a single power supply as well as
from a split supply llS shown in Fig. 15. The changes required
for 14.4·volt operation with a 3.2-ohm speaker are also
indicated in the diagram.
The amplifier may also be modified to accept input from
ceramic phonograph cartridges. For standard inputs
(equalizer preamplifiers, tuners, etc.) CI is 0.047, Rl is 250
kilohms. and R2 and C2 are omitted. For ceramic-cartridge
inputs. CI is 0.0047, RI is 2.5 megohms, and the jumper
across C2 is removed.
Output Biasing
Instead of the usual two-diode arrangement for establish·
ing idling currents in 01 and Q2, a "Vbe Multiplier",
transistor Q3, is used. This method of biasing establishes the
voltage between the base or QI and the base of 02 at a
constant multiple or the base-to-emitter voltage of a single
transistor while maintaining a low variational impedance
between its collector and emitter (see Appendix A). If
transistor Q3 is mounted in intimate thermal contact with
the output units, the operating temperature of the heat sink
rorces the Vbe of Q3 up and down inversely with heat·sink
temperature. The voltage bias between the bases of QI and
02 varies inversely with heat-sink tempera'ture and tends to
keep the idling current in Q I and 02 constant.
A bias arrangement that can be accomplished at lower
cost than those already described replaces the Vbe multiplier
with a I N5391 diode in series with an 8.2-ohm resistor. This
arrangement does not provide the degree of bias stability of
the Vbe multiplier, but is adequate for many applications.
Tone-Controls
The tone controls, the essential elements of the feedback
system, are located in two sets of parallel paths. The bass

494 ____________________________________________________________________

ICAN-6077
EG""VOLTS

A TOTAL' SOda

------'l

'0

,

- · - - · 9 9 0 A T M A X .... CL
En 403 ,O·:!.
En -0 5 mil AT MIN

"[o.,,c.
c"

"
"0

~OL

Fig. 13- A system in which tone controls are implicit in the feedback circuit of the
power amplifier.

Fig. 12- Block diagram of a system using a "Iosser"-tvpe tone-control circuit.
D,

.,

C,

~600

0.001

,.

220

+-""'-r-""""""""1,--o'o

c,

'50-1

4

6

a

8 10 1

FMOiJENCY-HI

Fig. 16- The measured response of the amplifier at extremes of tone-control rotation.

'2
,.o,---,---,----r--~---,--_.=_,

~~

N~

o,~-+_-~-~--+_-~--t~~

·
·
%

0. , f--+--+--j--t--+----ft"&,-----1
JUMPER

Fig. 14- A complete power amplifier using the CA3094 and three additional transistors.

D.' f--+--+--j--t--+---ttf-___1

"z
~ O.8~-+_-~-~--+_-~-_+t-~

'r:,
2:20..:

c.s f--+--+--j--t--+--tft-___1

~

~

~
aO.4
f--+--+--i--+--+--ttt-___1

'~DO""O

m

".,

"

0<7

z

~0

3

gO.2f--+---t------j--+--+-H-___1
~

.. ,"t..--I---':

0.' f--+---t-""~H-Z+'''-''q'--.-.".,.t,-t;i''''.,'--t----1

2201<

5"1.

" '/.v.1.

02
25",1'

II<

~/:VCC

POWER OUTPUT -

Fig. 15- A power amplifier operated {rom a single supply.

R7, R8. R9. RIO. C7. C8. C9. and CIO. Resistors R7 and R9

when there are tape recorders nearby. The cut limit aids the
stability of the amplifier by cutting the loop gain at higher
frequencies where phase shifts become significant.
In cases in which absolute stability under all load
conditions is required, it may be necessary to insert a small
inductor in the output lead to isolate the drcuit from
capacitive loads. A 3·microhenry inductor (I ampere) in
parallel with a 22·ohm resislor is adequate. The derivation of
circuit constants is shown in Appendix B. Curves of control
adiun versus electrical rotation are also given.

limit the maximum available cui and boost, respectively. The
boost limit is useful in curtailing heating due to finite
turn·off time in the output units. The limit is also desirable

Performance
Fig. 16 i~ a plut of the measured response of the

network includes R3, R4, Rs, C4. and CS. C6 blocks the dc
from the feedback network so that the dc gain from input to
the feedback takeoff point is unity. The residual dc-outputRII +R12
voltage at the speaker terminals is then IASC R} ~
where RJ is the source resistance. The input bias current is
then

IABC

U

=-

(Vee - Vb,)

~.

.

The treble network conSISts of

WATTS

Fig. 17- Total harmonic distortion of the amplifier with an
unregulated power supply.

r.:omplete amplifier al the extremes of tone·control wlation.
A t.:olllparison of Fig.)6 with the computed curves of
Fig. B4 (Appendix B) shows good agreement. The tutal
harmonic distortion of the amplifier with an unregulated
power supply is shown in Fig. 17; 1M distortion is plotted in
Fig. 18. Hum and noise are typically 700 microvolts at the
output. or 83·dB down.

COMPANION RIAA PREAMPLIFIER
Many available preamplifiers are capable of providing the
drive for the power amplifier of Fig. 14. Yet the unique
r.:harar.:teristics of the amplifier
its power supply. input
impedance. and gain - make possible the design of an RIAA

__________________________________________________________________ 495

IO~

ICAN-G077
preamplifier that can exploit these qualities. Since the input

impedance of the amplifier is essentially equal to the value of
the volume-control resistance (250 kiJoluns), the preamplifier
need not have high output-cwrent capability. Beatuse the
gain of the power amplifier is high (40 dB) the preamplifier
gain only has to be approximately 30 dB at the reference
frequency (I kHz) to provide optimum system gain.
Fig. 19 shows the schematic diagram of a CA3080
preamplifier. The CA3080, a low-cost OTA, provides
sufficient open-loop gain for all the bass boost necessary in
RJAA compensation. For example, a 8m of 10,000

micromhos with a load resistance of 250 kilohms provides an

APPENDtX A - Vbe MULTtPLtER
The equivalent circuit for the Vbe multiplier is shown
in Fig. A I. The voltage E I is given by:
(AI)

The value of Vbe is itself dependent on the emilter
current of the transistor, which is, in turn, dependent on
the input current I since:

'.0

(A2)

•

The derivative of Eq. A I with respect to I yields the
incremental impedance of the Vbe multiplier:

•

Note that the expressions for high-frequency gain are
identical for both bass circuits, while the expressions for
Illw-frequency gain are identical for the treble circuits_
Fig_ B2 shows cut and boost bass and treble controls
that have the characteristics of the circuits of Fig. B1_
The value REFF in the treble l."Ontrols of Fig_ B1 is
derived from the parallel combination of R I and R2 of
Fig. 82 when the control is rotated to its maximum
counterclockwise position_ When the control is rotated to
its maximum clockwise position. the value is equal to
RI.
To compute the circuit constants, it is necessary to
decide in advance the amounts of boost and cut desired.
TIle gain expressions of Fig. B I indicate that the slope of
the amplitude versus frequency curve in each case will be
6 dB per octave (20 dB per decade). If the ratios of
boosted and cui gain are set at 10, Le_:
Bass circuit:

(A3)

AMid
ALow (Cut) =10

IA

where K3 is a constant of the transistor 01 and can be
found from:

•

Vbe = K31nle - K2
0

•

o.

•

o.

o. 2

I~HZ8 2 KHZ

-

Bass circuit:

Treble circuit:
Fig. A 1-Equivalent circuit for the Vbe multiplier.

T KHZ

POWER -

RI = 10 R2

CI = IOC4

12

I.

WATTS

Fig. 18- 1M distortion of the amplifier with an unregulated
supply.

open-loop gain of 68 dB, thus allowing at least 18 dB of loop
gain at the lowest frequency. The CA3080 can be operated
from the same power supply as the main amplifier with only
minimal decoupling because of the high power·supply
rejection inherent in the device circuitry. In addition. the
high voltage-swing capability at the output enables the
CA3080 preamplifier to handle badly over·modulated (over.
cut) recordings without overloading. The accuracy of
equalization is within ± 1 dB of the RlAA curve, and
distortion is virtually unmeasurable by classical methods.
Overload occurs at an output of 7.5 volts, which allows for
undistorted inputs of up to 186 millivolts (260 millivolts
peak).

I. qVbe

)

(AS)

Ie = Is ,e KT -- I

Using the values shown in Fig. 14 plus data on the
2NS494 (a typical transistor that could be used in the

circuit), the dynamic impedance of the circuit at a total
current of 40 milliamperes is found to be 4.6 ohms. In
the actual deSign of the Vbe multiplier, the value of IR2
must be greater than Vbe or the transistor will never
become forward biased.
APPENDIX B - TONE CONTROLS
Fig_ Bf shows four operational-amplifier circuit configurations and the gain expressions for each. The asymptotic low-frequency gain is obtained by letting S approach
zero in each case:
Bass Boost:

ALow = R (+:;+R3

Bass Cut:

ALow=

Treble Boost:

ALow= CI;;4

Treble Cut:

ALow = C~;4

The unaffected portion of the gain (A high for the bass
control and A low for the treble cOntrol) is 11 in each
case.
To make the controls work symmetrically. the lowand high. frequency break paints must be equal for both
boost and cut.
Thus:
Bass Control:

CI R3 (RI+R2) _ C2 R2R3
RI +R2+R3 - R2+R3

and

CI R3 = C2 R3 (RI+R2)
RI+R2+R3

since

R3

~

Treble Control:

RI

(CIC4ii~!+CIC3)
=

RI+R2+R3
R2+R3

The asymptotic high-frequency gain is obtained by letting
S increase without limit in each expression:

__________

~

R~2R2

Bass boost;

AHigh =

Bass cut:

RI+R2
AHigh=-,u-

Treble boost:

(C3+C4)
AHigh = I + CI \ C3C4

Treble cut:
Fig. 19- A CA3080/HNmplifier.
~6

1~~4

C2 =

Eq. A4 is but another form of the diode equation: 4
10

EQUIVALENT SINE- WAVI!:

10 AMid
AHigh(Cut) = --10then the follOWing relationships result:

I
a

AHigh (Boost) = 10 AMid

R3=99R2

10 Hza 12 KHZ

60HZ

Treble Circuit:

(A4)

,----,----.,.-0.,

I
1/

•

ALow(Boost) = 10 AMid

R2+R3,

C2 = lOCI

:1~~2 (Cl+C2)

and

R2C3 jRIR2 \(C1C4+C2C4+CIC2)
VtI+R2}
(CI+C4)

since

CI

~ 100C2, C2 = C3 and CI
= IOC4, RI =9R2

. To make the controls work in the circuit of Fig. 14,
breaks were set at 1000 Hz:
for Ihe base control

0.1 C I R3 = 2"": 000

and for the treble control

RIC3 = 211'x:OOO

Response and Control Rotation
In a practical design, it is desirable to make "flat"
response correspond to the 50-percent rotation position
of the control, and to have an aural sensation of smooth
variation of response on either side of the mechanical
center. It is easy to show that the "flat" position of the
bass control occurs when the wiper arm is advanced to

___________________________________________________

ICAN-6077
C2

'0

(a)

'0

'0

'0

C"C 4
AlOWFREa'~

BASS 900ST
"lOWfA[Q

1l,,1l2,Al
AlOWFR{a~

(d) TREBLE CUT

Ie) TREBLE BOOST
(bIElASSCUT

Fig. 81- Four operational-amplifier circuit configurations and the gain expressions for each.

ceo

R2

!lASS

CONTROL

I"

TREBLE CONTROL

I"
Fig. 83- A plot of the response of the circuit of Fig. 14 with i:,;;:~ ~nd treble tone

Fig. B2- Cut and boost bass and treble controls that have the

controls combined at various settings of both controls.

characteristics of the circuits of Fig. 81.

,
0

0

,

,

°

0

,

,

L

1000 HZ

I0

"j

",0

./"
./

1KHZ

0

k,,~

V

l~

b

IOO·lIz plot for the bass control and the to·kHz response
for the treble control. The mechanical center ~hould
occur at the crossover point in each case.

lA

References·

~ I---V""

l/

l~
"

91·perccnt of its total resistance. The amplitude response
of the treble control is, however, never completely "Oat";
a ..:omputcr was used to generate response curves as
connols were varied.
Fig. B3 is a plot of the response with bass and treble
tone controls combined at various settings of both con·
trois. The values shown are the practical ones used in the
actual design. Fig. B4 shows the information of Fig. 83
replotted as a function of electrical rotation. The ideal
taper for each control would be the complement of the

k;:: ~

1. "Applications of the CA3080 and CA3080A High·
Performance Operational Transconductance Ampli·
fiers," H. A. Wittlinger, RCA Application Note ICAN·
6668

"fl

"II

V
,/

~~

,

V

.2
ELECTRICAL ROTATION OF BASS CONTROL

LO

2. "A New Wide·band Amplifier Technique," B. Gilbert,
IEEE Journal of Solid State Circuits, Vol. SC·3, No.
4, December, 1968.
3. "Trackability," James A. Kogar, Audio, December
1966
4. RCA Linear Integrated Circuits Manual, RCA Tech·
nical Series IC-42

ELECTRICAL ROTATION OF TREBLE CONTROL

Fig. 84- The information of Fig. 83 plotted as a function of electrical rotation.

*RCA publications available through RCA Solid State
Division, Box 3200, Somerville, N.J., 08876.

__________________________________________________________________ 497

ICAN-8157
Applications of the CA3085-Series
Monolithic IC Voltage Regulators
by A. C. N. Sheng and L. R. Avery

The RCA-CA308S, CA308SA, and CA308SB monolithic
IC's are positive-voltage regulators capable of providlns output
currents up to 100 milUamperes over the temperature range
from -55 0 to +12S oC. They are supplied in 8·lead TO·S type
packages; their characteristics and ratings are given in RCA
Data File No. 491. The following tabulation shows some key
characteristics and salient differences between devices in the
CA308S Series.
Type

Max.
Max. Load
VIN6

the value of V ref varies from being slightly more positive than
Vrer' when OJ is conducting, to being slightly more negative
than V rer' when D I is conducting. The voltage and current
waveforms arc shown in fig. l7(b), (c), and (d).

A switching-regulator circuit using the CA3085 is shown in
Fig. 18. The values of Land C (1.5 millihenries and 50 microfarads. respectively) are commercially available components
having values approximately equal to the computed values in
the previous design example.

Design Example: The following specifications are used in de·
computations for a s~itching regulator:

VI = 30 V, YO = 5 V, 10 = 500 mA,
switching frequency = 20 kHz,
output ripple = tOO mY.
If it is assumed that transistor 0 I is in steady-state saturated
operation with a low voltage-drop, the current in the inductor
is given by Eq. 10. as follows:

o 00IIl-F

'"

RLl/rlllT

·,.i·~L(t.lAXI

'10 -VREF (R';,R2)

Fig. 16- High.voltage regulator incorporating current "snap-back"
protection.

Fig.

.

Switching Regulator

IL

When large input-to-.iL 'off
/1,
(elINOUCTOR CURRENT III

Substitution for

REO',

V'RE:

i

LI

C=

(dlOUTPUT VOLTAGE

Fig.

'he(::u~ ~O~ :~~(E~O\, yields

The total period T

VI

f

J 'off

(16)

/1,

=toff t

=f. Therefore,

ton' and T

'7- Switching regulator and associated waveforms.

(17)

UNREG
NEG·'I1t-lo-_-+-,,.,....._ _ _ _ _--'
HIGHecURRENT REGULATOR

either a saturated or cut-off condition to minimize dissipation.
When transistor QI .is conductive, diode 01 is reverse-biased
and current in the inductance Ll increases in accordance with
the following relationship:

For optimum efficiency ton should be

,,(~\,,(~\J.

(18)

vd r

Vd

Substitution for ton in Eq. 18 yields

.

1

'1

IL =1: fVd.

• ff=-L
o
r

(10)

'n
where V is the voltage across the inductance Ll. The current
through the inductance charges the capacitor CI and supplies
current to the load. The output voltage rises until it slightly exceeds the reference voltage Vref' At this point the op·amp removes base drive to 01 and the unregulated input voltage VI is
"switched off'. The energy stored in the inductor LI now
causes the voltage at Vx to swing in the negative direction and
current flows through diode 0 I, while continuing to supply
current into the load RL' As the current in the inductor falls
below the load current, the capacitor CI begins to discharge
and Vodecreases. When Vofaiis slightly below the value of

(~\L1.
(1 _VIVO\i
VJ/ r r

(19)

1

(V -VO)
L1

01.,

Vo
VI

r

Vrer

o..l.

(I _

Vo)
VI

f

Substitution of numerical values in Eq. 20 produces the
follOWing value for C:

30 - 5

c=~o

1

Wxi03

5
0

3Q'
10- 1

Fig. 19(b) shows a high-current regulator using the CA3085 in
conjunction with an external n-p-n transistor to regulate currents up to 3 amperes. In this circuit the qUiescent regulator
current does not flow through the load and the output current
can be directly programmed by RI , i.e.,

Reg1L =TJ

Substitution for toffin Eq. 16 yields

c=

9lCS-2,S39

Fig. 19- Constant current regulators.

1

Wxi03

0

With this regulator currents between 1 milliampere and 3
amperes can be programmed directly. At currents below
1 milliampere inaccuracies may occur as a result of leakage in
the external transistor.
A Dual-Tracking Voltage Regulator
A dual-tracking voltage regulator using a CA3085 and a
CA3094A" is shown in Fig. 20. The CA3094A is basically an
op-amp capable of supplying 100 milliamperes 9f output current.

_______________________________________________________________ 501

ICAN·6157
.. AX: .lOUT " It; 100 mA

5,10

0.03,."

~I!I\I

'-.---\--4-<)11£6.

OUTPUT

. ,.

"""'INPUT RANGE-19 TO 30 V ' - - - - " N \ ; - - - - - '
1011;0
FOR 15 V OUTPUT
".V-'NPUT RANGEo_16 TO-30 V
FOfH5 V OUTPUT

The basic circuit of Fig. 20 can be modified to regulate dis·
similar positive and negative voltages (e.g., +15 V, -5 V) by
appropriate selection of resistor ratios in the voltage·divider
network discussed previous1y. As an ex.ample. to provide
tracking of the +15 V and -5 V regulated voltages with the
circuit of Fig. 20, it is only necessary to replace the 10·kilohm
resistor connected between terminals 3 and 8 of the (' A3094A
with a 3.3-kilohm resistor.
Regulators With High Ripple Rejection
When the reference-voltage source in the ('A30!'!5 is adequately mtered, the typical ripple rejection provided by the
circuit is 56 dB. It is possible to achieve higher ripple·rejection
performance by cascading two stages of the CA3085. as shown
in Fig. 21. The voltage·regulator circuit in Fig. 21 (a) provides
90 dB of ripple rejection. The output voltage is adjustable over
the range from 1.8 to 30 volts by appropriate adjustment of
resistors RI and R2. Higher regulated output currents up to
·,1 ampere can be obtained with this circuit by adding an external
n-p·n transistor as shown in Fig. 21 (b).
'1

MAX. LINE· A "'OUT

e:[Vc"OU"'T'":.II:::.':::T''''''L''~;-:''''V'-N lIOO a O.075'" IV
A VOUT

;:'VO'"'UT"""II."'T"""""L"-J _100_0,07,-. VOUT
tIL FROM I TO 50 mAJ

,,'
90dS RIPPLE REJECTION
LINE REG <00001"1.1'11
LOAD REG jIGHT

SPRAGUE
IIZI2
(OR EQUIV,)

54E-1421
(OR (QUIV I

Fig. 24 - The zero-voltage switch and thytisfor as an interface.

gate will immediately cease. Therefore, the load will be turned
off when the triac commutates off as the sine-wave load
current goes through zero. In this manner, both the turn-on
and turn-off conditions for the load are controlled.
When electrical isolation between the logic circuit and the
load is necessary. the isolated-input technique shown in
Fig. 25(b) is used. In the technique shown, optical coupling is
used to achieve the necessary isolation. The logic output
transistor switches the light-source portion of the isolator. The
light-sensor portion changes from a high impedance to a low
impedance when the logic output transistor is switched from

• fORMERLY RCA 40691

Fig. 26 - Zero· voltage switch, on-off controller with an isolated sensor.

'--±------+--llf---+---'
O,I,.F

fa)

Fig. 27 - A line-isola red temperature controller for use with inductive or
resistive loads; rhis controller does not Include zero-voltage switching.

and that the load is a heater thermally coupled to the sensor,
the object being to maintain the thermal-coupling medium at a
desired reference temperature. Assume initially that the temperature at the coupling medium is low.

fb)

Fig. 25 - Basic interfacing techniques: fa} direct input; fb} isolated
input.

off to on. The light sensor is connected to the differential
amplifier input of the zero-voltage switch, which senses the
change of impedance at a threshold level and switches the load
on as in Fig. 25(a).
Sensor Isolation
In many applications, electrical isolation of the sensor from
the ac input line is desirable. Several isolation techniques
are shown in Figs. 26, 27, and 28.
Transfonner Isolation - In Fig. 26, a pulse transformer
is used to provide electrical isolation of the sensor from
incoming ac power lines.'The pulse transformer TI isolates the
sensor from terminal No.1 of the triac Y I. and transformer
12 isolates the CA3058 or CA3059 from the power lines.
Capacitor C 1 shifts the phase of the output pulse at terminal
No.4 in order to retard the gate pulse deHvered to triac Y 1 to
compensate for the small phase-shift introduced by
transformer T 1Many applications require line isolation but not zero-voltage
switching. A line·isolated temperature controller, for use with
inductive or resistive loads that does not include zero-voltage
switching is shown in Fig. 27.
In temperature monitoring or control applications the sensor
may be a temperature-dependent element such as a resistor.
thermistor, or diode. The load may be a lamp, bell, horn, recorder or other appropriate device connected in a feedback relationship to the sensor.
For the purpose of the following explanation, assume that
the sensor is a resistor having a negative temperature coefficient

*R20ETERMIMES MIVE TO TRIAC
**SNUBBER fOR LIGHT INOUCTIVE LOADS

The operating potentials applied to the bridge circuit produce a common-mode potential, VeM, at the input terminals
of the CA3094. Assuming the bridge to have been initially
balanced (by adjustment of R4), the potential at point A will
increase when temperature is low since it was assumed that the
sensor has a negative temperature coefficient. The potential at
the non inverting terminal, being greater than that at the inverting terminal at the amplifier. causes the multivibrator'to
oscillate at approximately 10 kHz. The oscillations are transformer-coupled through a current-limiting resistor to the gate
of the thyris~or, and trigger it into conduction.
When the thyristor conducts, the load receives ac input
power, which tends to increase the temperature of the sensor.
This temperature increase decreases the -potential at point A

to a value below that at point B and the muitivibrator
is disabled, which action, in turn, turns off the thyristor.
The temperature is thus controlled in an o~-off fashion.
Capacitor C1 is used to provide a low impedance path to
ground for feedback-induced signals at terminal No.5 while
blocking the direct current bias provided by resistor RI. Resistor R2 provides current limiting. Resistor R3 limits the
secondary current of the transformer to prevent excessive
current flow to the control terminal of the CA3094.
Pbotocoupler Isolation - In Fig. 28, a photocoupler
provides electrical isolation of the sensor logic from the
incoming ac power lines. When a logic "1" is applied at the
input of the photocoupler. the triac controlling the load will
be turned on whenever the line voltage passes through zero.
When a logic "0" is applied to the photocoupler. the triac will
turn off and remain off until a logic "1" appears at ,the input
of the photocoupler.

"
120VAC

60H:

PHOTO
COUPLED

,"PU)--

ISOLATOR

l

I ~
I
I ___ --lI

Fig. 28 - Zero·l/Olrage switch, on-off controller with photocoupler.

508 __________________________________________________________________

ICAN-6182
lag the incoming line voltage. The motors, however. are
switched by the triacs at zero current, as shown in F.ig. 34(b).

TEMPERATURE CONTROLLERS

Fig. 29

shows

a

triac

used

in

an

on-off

temperature-controller configuration. The triac is turned on at
zero voltage whenever the voltage V s exceeds the reference

""

'0%

POWER

POWER

"

The problem of driving inductive loads such.as these motors
by the narrow pulses generated by the zero-voltage switch is
solved by use of the sensitive-gate RCA4Q526 triac. The high
sensitivity of this device (3 milliamperes maximum) and low
latching current (approximately 9 milliamperes) pennit
synchronous operation of the temperature-controller circuit.
In Fig. 34(a), it is apparent that, though the gate pulse V g of
triac Y I has elapsed, triac Y 2 is switched on by the current
through RL 1. The low latching current of the RCA40526
triac results in dissipation of only 2 watts in RL I, as opposed
to 10 to 20 watts when devices that have high latching
currents are used.

.

POWER

POWER

,

,

,

0_5.1\

Fig. 31 - Principles of proportional control.

'AG

thermal system and the closed-loop type of control. In the
circuit shown in Fig. 32, the ramp voltage is generated when
the capacitor CI charges through resistors RO and RI' The
time base of the ramp is determined by resistors R2 and R3,
capacitor C2, and the breakover voltage of the D3202U* diac.
Fig. 29 - CA3058 or CA3059 on-off temperature controller.
TYPE
IN3193

TO PIN 2

r-----;~_0

voltage Vr- The transfer characteristic of this system, shown in
Fig. 30(a), indicates significant thermal overshoots and
undershoots, a well·known characteristic of such a system. The
differential or hysteresis of this system, however, can be
further increased, if desired, by the addition of positive
feedback.

VCC+6V

ON

O.l,...f

TO PIN 1

200V

~~--~--~----~----~--o
"fORMERLY RCA 4541Z

ALL RESISTORS 112 WATT
UNLESS OTHERWISE SPEClflE:.D

PIN CONNECTIONS REFER TO
RCA CA3058 OR CA30!59

DIFFERENTIAL
< :l:O.5"C.
.FORMERLY RCA 40526

Fig. 32 - Ramp generator.

(a)

(b)

Fig. 30 - Transfer characteristics of (a) on-off and (b) proportional

control systems.

For
precise
temperature-control
applications, the
proportional-control technique with synchronous switching is
employed. The transfer curve for this type of controller is
shown in Fig. 30(b). In this case, the duty cycle of the power
supplied to the load is varied with the demand for heat
required and the thermal time constant (inertia) of the system.
For example, when the temperature setting is increased in an
on·off type of controller, full power (100 per cent duty cycle)
is supplied to the system. This effect results in significant
temperature excursions because there is no anticipatory circuit
to reduce the power gradually before the actual set
temperature is achieved. However, in a proportional control

When the voltage across C2 reaches approximately 32 volts,
the diac switches and turns on the 2N697S transistor and
IN914 diodes. The capacitor C 1 then discharges through the
collector-to-emitter junction of the transistor. This discharge
time is the retrace or flyback time of the ramp. The circuit
shown can generate ramp times ranging from 0.3 to
2.0 seconds through adjustment of R2. For precise
temperature regulation, the time base of the ramp should be
shorter than the thermal time constant of the system, but long
with respect to the period of the 60-Hz line voltage. Fig. 33
shows a triac connected for the proportional mode.

,,)

fbI
Fig. 34 - Dual output, over-under temperature controller (a} circuit,
(b) voltage and current waVllforms.

)OK

'W

technique, less power is supplied to the load (reduced duty
cycle) as the error signal is reduced (sensed temperature
approaches the set temperature).
Before such a system is implemented, a time base is chosen
so that the on·time of the triac is varied within this time base.
The ratio of the on-to-off time of the triac within this time
interval depends on the thermal time constant of the system
and the selected temperature setting. Fig. 31 illustrates the
principle of proportional control. For this operation, power is
supplied to the load until the ramp voltage reaches a value
greater than the de control signal supplied to tne opposite side
of the differential amplifier. The triac then remains off for the
remainder of the time-base period. As a result, power is
"proportioned" to the load in a direct relation to the heat
demanded by the system.
For this application, a simple ramp generator can be
realized with a minimum number of active and passive
components. A ramp having good linearity is not required for
proportional operation because of the nonlinearity 'Jf the

* Formerly RCA 45412

Fig. 33 - CA3058 or CA3059 proportional temperature controller.

Fig. 34(a) shows a dual.autput temperature controller that
drives two triacs. When the voltage Vs developed across the
temperature-sensing network exceeds the reference voltage
V R I, motor No. I turns on. When the voltage across the
network drops below the reference voltage VR2. motor No.2
turns on. Because the motors are inductive, the currents 1M 1

Electric-Heat Application
For electric·heating applications, the RCA-2N5444
40-ampere triac and the zero·voltage switch constitute an
optimum pair. Such a combination proVides synchronous
switching and effectively replaces the heavy-duty contactors
which easily degrade as a result of pitting and wearout from

___________________________________________________________________ 509

ICAN-6182
included in the oven to provide a closed-loop system for
accurate control of the oven temperature.

f,
120VAC

60

H~

ALL RESISTORS 1/2 WATT
UNLESS OTHERWISE SPECIFIED

TRANSISTORS 01 ,Q2ANO 04

ARE PART OF RCA -CA3096E
INTEGRATED-CIRCUIT N-P-N/P-H-P
TRANSISTOR ARRAY

Fig. 35 - Synchronous-switching hear-staging controller using a series
of zero-voltage switches.

the switching transients. The salient features of the 2N5444
40-ampere triac are as follows:
(I) 300-ampere single-surge capability (for operation at
60-Hz),
(2) a typical gate sensitivity of 20 milliamperes in the 1(+)
and 111(+) modes.
(3) low on-state voltage of 1.5 volts maximum at
40 amperes, and
(4) available VOROM equal to 600 volts.

is, the closing of the thermostat would not switch in all the
heating elements within a short time interval, which inevitably
results in undesired temperature excursions, but would switch
in only the number of heating elements required to satisfy the
actual heat load.
Oven/Broiler Control
Zero-voltage switching is demonstrated in the oven control
circuit shown in Fig. 37. In this circuit. a sensor element is

Fig. 35
shows
the
circuit
diagram
of
a
synchronous-switching heat-staging controller that is used for
electric heating systems. Loads as heavy as 5 kilowatts are'
switched sequentially at zero voltage to eliminate RFI and
prevent a dip in line voltage that would occur if the full
25 kilowatts were to be switched simultaneously.
Transistor Ql and Q4 are used as a constant-current source
to charge capacitor C in a linear manner. Transistor 02 acts as a
buffer stage. When the thermostat is closed, a ramp voltage is
provided at output Eo. At approximately 3-second intervals,
each 5-kilowatt heating element is switched onto the power
system by its respective triac. When there is no further demand
for heat, the thermostat opens, and capacitor C discharges
through RI and R2 to cause each triac to turn off in the
reverse heating sequence. It should be noted that some
half·cycling occurs before the heating element is switched fully
on. This condition can be attributed to the inherent
dissymmetry of the triac and is further aggravated by the
slow'rising ramp voltage applied to one of the inputs. The
timing diagram in Fig. 36 shows the turn-on and turn·off
sequence of the heating system being controlled.

220 V

AC

L

I. ~

L26-------~--------------------~

Fig. 37- SchematiC diagram of basic oven control.

''''

15VDC

As shown in Fig. 37, the temperature of the oven can be
adjusted by means of potentiometer R I, which acts, together
with the sensor, as a voltage divider at terminal 13. The voltage
at terminal 13 is compared to the fixed bias at terminal 9
which is set by internal resistors R4 and Rs. When the oven is
cold and the resistance of the sensor is high, transistors Q2 and
Q4 are off, a pulse of gate current is applied to the triac, and
heat is applied to the oven. Conversely, as the desired
temperature is reached, the bias at terminal 13 turns the triac
off. The closed-loop feature then cycles the oven element on
and off to maintain the desired temperature to approximately
±2°C of the set value. Also, as has been noted, external
resistors between terminals 13 and 8, and 7 and 8, can be used
to vary this temperature and provide hysteresis. In Fig. II, a
circuit that. provides approximately lO-per-cent hysteresiS is
demonstrated.
In addition to allowing the selection of a hysteresis value,
the flexibility of the control circuit permits incorporation of
other features. A PTC sensor is readily used by interchanging
terminals 9 and 13 of the circuit shown in Fig. 37 and
substituting the PTC for the NTC sensor. In both cases, the
sensor element is directly returned to the system ground or
common, as is often desired. Terminal 9 can be connected by
external resistors to provide for a variety of biasing, e.g., to
match a lower-resistance sensor for which the SWitching-point
voltage has been reduced to maintain the same sensor current.
To accommodate the self·deaning feature, external
switching, which enables both broiler and oven units to be
paralleled, can easily be incorporated in the design. Of course,
the potentiometer must be capable of a setting such that the
sensor, which must be characterized for the high, self-clean
temperature, can monitor and establish control of the
high-temperature, self-clean mode. The ease with which this
self-clean mode can be added makes the over-all solid-state
systems cost·competitive with electromechanical systems of
comparable capability. In addition, the system incorporates
solid-state reliability while being neater, more easily calibrated,
and containing less-costly system wiring.
Integral-Cycle Temperature Controller (No half-cycling)
If a temperature controller which is completely devoid of
half-cycling and hysteresis is required, then the circuit shown
in Fig. 38 may be used. This type of circuit is essential for
applications in which half-cycling and the resultant dc
component could cause overheating of a power transformer on
the utility lines.
In the integral-cycle controller, when the temperature being
controlled is low. the resistance of the thermistor is high, and
an output signal at terminal 4 of zero volts is obtained. The
SCR (yd, therefore, is turned off. The triac (Y2) is then
triggered directly from the line on positive cycles of the ac
voltage. When Y2 is triggered and supplies power to the load
RL, capacitor C is charged to the peak of the input voltage,

+

120VAC

60"'

'I:·
".

LOAO
HEAtERI

o 5,.F
200VDC

'c

C

Fig. 36 - Ramp·vo/tage waveform for the heaNtaging controller.

Seemingly, the basic nlethod shown in Fig. 35 could be
modified to provide proportional control in which the number
of heating elements switched into the system, under any given
thermal load, would be a function of the BTU's required by
the system or the temperature differential between an indoor
and outdoor sensor within the total system environment. That

*

FOR PROPORTIONAL OPERATiON OPEN TERMINALS 10,11, AND 13, ANO CONNECT POSITIVE RAMP VOLTAGE TO TERMINAL 13

.. ". SELECTED FOR IGT=6 rnA MAXIMUM

• FORMERLY RCA ....003
• FORMERLY RCA 406~'5

Fig. 38 - Inregral-cycle temperature concroller (n which half-cycfing effect is elimlnaffJd.

510 ____________________________________________________________________

ICAN-6182
system. Many types of automatic eqUipment are not complex
enough or large enough to justify the cost of a flexible logic
system. A special circuit, designed only to meet the control
requirements of a particular machine, may prove more
economical. For example, consider the simple machine shown
in Fig. 42; for each revolution of the motor, the belt is
advanced a prescribed distance, and the strip is then punched.
The machine also has variable speed capability,

IZOVAC

60",

I
O.~"F

200'0' DC

C

Fig. 42 - Step'6nd-punch machine.

*'

FOR PROPORTIONAL OPERATION OPEN TERMINALS 9,10 Atoll) II AND CONNECT POSTlvt RA,",P VOLTAGE TO TER~INAI. 9
IIIIStLECTEO FOR lOT"GInA MAXIMUM

IIFORMERL'I' RCA 44003
.FORMERL'I'

RCA 40655

Fig, 39 - CA3058 or CA3059 integraJ-cycle tflmperature controller
that (eatures a protection circuit and no hal(-cycling effect.

When the ac line swings negative, capacitor C discharges
through the triac gate to trigger the triac on the 'negative
half-cycle. The diode-resistor-capacitor "slaving network"
triggers the triac on negative half-cycle to provide only integral
cycles of ac power to the load.
When the temperature being controlled reaches the desired
value, as determined by the thermistor, then a positive voltage
level appears at terminal 4 of the zero-voltage switch. The SCR
then starts to conduct at the beginning of the positive input
cycle to shunt the trigger current away from the gate of the
triac. The triac is then turned off. The cycle repeats when the
SCR is again turned OFF by the zero·voltage switch.
The circuit shown in Fig. 39 is similar to the configuration
in Fig. 38 except that the protection circuit incorporated in
the zero-voltage switch can be used. In this new circuit, the
NTC sensor is connected between terminals 7 and 13, and
transistor Qo inverts the signal output at terminal 4 to nullify
the phase reversal introduced by the SCR (Y t). The internal
power supply of the zero-voltage switch supplies bias current
to transistor Qo .
Of course, the circuit shown in Fig. 39 can readily be
converted to a true proportional integrai-cycle temperature
controUer simply by connection of a positive-going ramp
voltage to terminal9 (with terminals 10 and 11 open), as
previously discussed in this Note.

Thermocouple Temperature Control
Fig. 40 shows the CA3080A operating as a pre·amplifier for
the zero-voltage switch to form a zero·voltage switching circuit
for use with thermocouple sensors.

ALL RESISTORS 112 WATT
UNLESS OTHERWISE SPECIFIED

Fig. 40 - Thermocouple
switching.

temperature

control

with

zero-voltage

Thermocouple Temperature Control with Zero-Voltage Load
Switching
Fig. 41 shows the circuit di:Jgram of:J thermocouple temp·
erature control system using zero·voltage load switching. It
should be noted that one terminal of the thermocouple is connected to one leg of the supply line. Consequently, the thermo·
couple can be "ground·referenced", provided the appropriate

leg of the ac line is maintained at ground. The comparator, Al
(a CA3130), is powered from a 6.4-voit source of potential
provided by the zero-voltage-switch (ZVS) circuit ~a CA307?).
The ZVS. in turn, is powered off·line through a senes-droppmg
resistor R6. Terminal 4 of the ZVS provides trigger·pulses to
the gate of the load-switching triac in response to an appropriate control signal at terminal 9.

"

."'"

The typical electromechanical control circuit for such a
machine might consist of a mechanical cam bank driven by a
separate variable speed motor, a time delay relay, and a few
logic and power relays. Assuming use of industrial-grade
controls, the control system could get quite costly and large.
Of greater importance is the necessity to eliminate transients
generated each time a relay or switch energizes and deenergizes
the solenoid and motor. Fig. 43 shows such transients, which
might not affect the operation of this machine, but could
affect the more sensitive solid·state equipment operating in the
area.
A more desirable system would use triacs and zero-voltage
switching to incorporate the following advantages:
Increased reliability and long life' inherent in
solid-state devices as opposed to moving parts and
contacts associated with relays.

<-L.;"_r.Ll

VOLTAGE
ADJUST

""'
92CM·:29961

Fig. 41 - Thermocouple temperature control with zero·voltage
switching.

The CA3130 is an ideal choice for the type of comparator
circuit shown in Fig. 41 because it can "compare"!ow voltages
(such as those generated by a thermocouple) in the proximity
of the negative supply r~iI. Adjustment'of potentiometer RI
drives the voltage-divider netl,l(ork R3, R4 so that reference
voltages over the range of 0 to 20 millivolts can be applied to
noninverting terminal 3 of the comparator. Whenever the
voltage developed by the thermocouple at terminal 2 is more
positive than the reference voltage applied at terminal 3, the
comparator output is toggled so as to sink current from terminal 9 of the ZVS; gate pulses are then no longer applied to
the triac. As shown in Fig. 41!, the circuit is provided with a
control-point "hysteresis" of 1.25 millivolts.
Nulling of the comparator is performed by means of the
following procedure: Set RI at the low end of its range and
short the thermocouple output signal appropriately. If the
triac is in the conductive mode under these conditions. adjust
nulling potentiometer R5 to the point at which triac conduction is interrupted. On the other hand. if the triac is in the nonconductive mode under the conditions above, adjust R5 to the
point al which triac conduction commences. The thermocouple output signal should then be unshorted, and RI can be
set to the voltage threshold desired for control-circuit operation.

Fig. 43 - Transients generated by relay-contact bounce and non-zero
turn-off of inductive load.

b.
c.

d.

Minimized generation of EMl/RFI using zero-voltage
switching techniques in conjunction with thyristors.
Elimination of higlHoitage transients generated by
relay-contact bounce and contacts breaking inductive
loads, as shown in Fig, 42.
Compactness of the control system.

The entire control system could be on one printed-circuit
board, and an over-all cost advantage would be achieved ..
Fig, 44 is a timing diagram for the proposed solid·state

SOLENOID
OP[ltATION

MACHINE CONTROL ANO AUTOMATION
The earlier section on interfacing techniques indicated
several techniques of controlling ac loads through a logic

Fig. 44 - Timing diagram (or proposed solid-state machine control.

____________________________________________________________________ 511

ICAN-6182
machine control, and Fig. 45 is the corresponding control
schematic. A variable·speed machine repetition rate pulse is set
up using either a unijunction oscillator or a transistor astable
multivibrator in conjunction with a IO-millisecond one-shot
multivihrator. The first zero-voltage switch in Fig. 45 is used
to synchronize the entire system to zero-voltage crossing. Its
output is inverted to simplify adaptation to the rest of the
circuit. The center zero-voltage switch is used as an interface
for the photo-cell, to control one revolution of the motor. The
gate drive to the motor triac is continuous dc, starting at zero
voltage crossing. The motor is initiated when both the machine
rate pulse and the zero-voltage sync are at low voltage. The
bottom zero-voltage switch acts as a time-delay for pulsing the
solenoid. The inhibit input, terminal I, is used to assure that
the solenoid will not be operated while the motor is running.
The time delay can be adjusted by varying the reference level
(SDK potentiometer) at terminal 13 relative to the capacitor
charging to that level on terminal 9. The capacitor is reset by
the SCR during the motor operation. The gate drive to the
solenoid triac is direct current. Direct current is used to trigger
both the motor and solenoid triacs because it is the most
desirable means of switching a triac into an inductive load. The
output of the zero-voltage switch will be continuous de by
connecting terminal 12 to common. The output under dc
operation should be limited to 20 milliamperes. The motor

b.

Lighting controls for instrument panels and cabin
illumination
c.
Motor controls
d. Solenoid controls
e.
Power·supply switches
Lamp dimming is a simple triac application that
demonstrates an advantage of 400-Hz power over 60-Hz
power. Fig. 46 shows the adjustment of lamp intensity by
phase control of the 60-Hz line voltage. RFI is generated by
the step functions of power each half cycle. requiring
extensive filtering. Fig. 47 shows a means of controlling power
to the lamp by the zero-voltage·switching technique. Use of
400-Hz power makes possible the elimination of complete or
half cycles within a period (typically 17.5 milliseconds)

"-"~
"""

'A:)LTAGE

I

:

-

:

:

iI6.67~'--=----:

LAMPi
OUTPUT,

~

I

~

---

:

:
:

j

~

:
I

W

Fig. 46 - Wavoforms for 50-Hz phase-controlled lamp dimmer.

without noticeable flicker. Fourteen different levels of lamp
intensity can be obtained in this manner. A line·synced ramp is
set up with the desired period and applied to terminal No.9 of
the differential amplifier within the zero-voltage switch, as
shown in Fig. 48. The other side of the differential amplifier
(terminal No. 13) uses a variable reference level, set by the
SOK potentiometer. A change of the potentiometer setting
changes the lamp intensity.

Fig. 41- Wavefarms far 4oo-Hz zera-voltage-switched lamp dimmer.

In 400-Hz applications it may be necessary to widen and
shift the zero-voltage switch output pulse (which is typlcally
12 microseconds wide and centered on zero voltage crossing),
to assure that sufficient latching current is available. The 4K
resistor
(terminal
No. 12
to
common) and
the
O.OIS-microfarad capacitor (terminal No.5 to common) are
used for this adjustment.

Fig. 45 - Schematic of proposed solid-srate machine contro'_

triac is synchronized to zero crossing because it is a
high-crurent inductive load and there is a chance of generating
RFI. The solenoid is a very low current inductive load. so
there would be little chance of generating RFI: therefore, the
initial triac turn-on can be random, which Simplifies the
circuitry.
This example shows the versatility and advantages of the
RCA zero·voltage switch used in conjunction with triacs as
interfacing and control elements for machine control.
400·Hz TRIAC APPLICATIONS
The increased complexity of aircraft control systems, and
the need for greater reliability than electromechanical
switching can offer, has led to the use of solid-state power
switching in aircraft. Because 400·Hz power is used almost
universally in aircraft systems, RCA offers a complete line of
triacs rated for 400-Hz applications. Use of the RCA
zero-voltage switch in conjunction with these 400-Hz triacs
results in a minimum of RFI, which is especially important in
aircraft.
Areas of application for 400-Hz triacs in aircraft include:
a.
Heater controls for food-warming ovens and for
windshield defrosters.

SOLID-STATE TRAFFIC FLASHER
Another application which illustrates the versatility of the
zero·voltage switch, when used with RCA thyristors, involves
SWitching traffic-controllamps. In tWs type of application, it is
essential that a triac withstand a current surge of the lamp load

~~

11 I,,J

II~

v

/OF

.00
•

H,

LlNESYNCED
RAMP

Fig.

'R

I

48 - Circuit diagram for 4OO·Hz zero·voltsge-switchfti lamp
dimmer.

on a continuous basis. This surge results from the difference
between the cold and hot resistance of the tungsten mament.
If it is assumed that triac turn-on is at 90 degrees from the
zero-voltage crossing, the first current-surge peak is
approximately ten times the peak steady-state value or fifteen
times the steady-state rms value. The second current·surge
peak is approximately four times the steady-state rms value.
When the triac randomly switches the lamp, the rate of
current rise di/dt is limited only by the source inductance. The
triac di/dt rating may be exceeded in some power systems. In
many cases, exceeding the rating results in excessive current
concentrations in a small area of the device which may
produce a hot spot and lead to device failure. Critical
applications of this nature require adequate drive to the triac
gate for fast turn-on. In this case, some inductance may be
required in the load circuit to reduce the initial magnitude of
the load current when the triac is passing through the active
region. Another method may be used which involves the
switching of the triac at zero line voltage. This method
involves the supply of pulses to the triac gate only during the
presence of zero voltage on the ac line.
Fig. 49 shows a circuit in which the lamp loads are switched
at zero line voltage. This apl'roach reduces the initial di/dt,
decreases the required triac surge-current ratings, increases the
operating lamp life, and eliminates RFI problems. This circuit
consists of two triacs, a flip-flop (FF·I), the zero-voltage
switch, and a diac pulse generator. The flashing rate in this
circuit is controlled by potentiometer R, which provides
between 10 and 120 flashes per minute. The state of FF-l
determines the triggering of triacs Y 1 or Y2 by the output
pulses at terminal 4 generated by the zero-crossing circuit.
Transistors Ql and Q2 inhibit these pulses to the gates of the
triacs until the triacs turn on by the logical ul" (Vee high)
state of the flip-flop.
The arrangement described can also be used for a
synchronous. sequential traffic-controller system by addition
of one triac. one gating transistor, a "divide-by-three" logic
circuit, and modification in the design of the diac pulse
generator. Such a system can control the familiar red. amber,
and green traffic signals that are found at many intersections.

• FORMERLY RCA4~412
• FORMERLY RCA40668

Fig. 49 - Sync:hronous-switching traffic: flasher.

512 ____________________________________________________________________

ICAN·6182
SYNCHRONOUS LIGHT FLASHER

Fig. 50
shows
a
simplified
version
of
the
synchronous-switching traffic light flasher shown in Fig. 49.

'20

O.Ijl.F
25VOC

::T .',

,-

I

VA<

,.

'OK

6010

I

"

TZ30IB·

.',

15 .... OC+

,.

IZOIJAC
6OH,

1/2W

I

OI,.F
IOVDC
O.I".F
'00
V OC
ON

Fig. 50 -Synchronous light flasher.

Flash rate is set by use of the curve shown in Fig• .16. If a more
precise flash rate is required, the ramp generator described
previous1y may be used. In this circuit, ZVSl is the master
control unit and ZVS2 is slaved to the output of ZVSl

*IF Yz, FOA E)cAMPLE, IS A 20j.lS

90ns

*4.5 Vat<4 rnA

3.2 Vat .. 5.0 mA

• Refer to Fig. 20; RX equals 5000 ohms.

POWER ONEoSHOT CONTROL
Fig. 54 shows a circuit which triggers a triac for one complete
half-cycle of either the positive or negative alternation of the
ac line voltage. In this circuit, triggering is initiated by the
push button PB-I, which produces triggering of the triac near
zero voltage even though the button is randomly depressed
during the ac cycle. The triac does not trigger again until the
button is released and again depressed. This type of logic is
required for the solenoid drive of electrically operated stapling
guns, impulse hammers, and the like, where load-current flow
is required for only one complete half-cycle. Such logic can
also be adapted to keyboard conso)eli in which contact bounce
produces transmission of erroneous information.
In the circuit of Fig. 54, before the button is depressed,
both flip.flop outputs are in the "zero" state. Transistor Qo is
biased on by the output of flip-flop FF-1. The differential
comparator whic~ is part of the zero·voltage switch is initially

FI,. 55 - Circuit d~m fo, "'" POMl' one-shot control.

VOLTAGE

r

PIN @OfZEROSW

1..E:.!.

PIN 2

TlN£-_

Fig. 66 - Timing diagrsm for the paws, one-shot control.

113CD4007A
• FORMERLY RCA 40$91

Fig. 54 - Block diagrsm 01 a paws, o"..,hot control u,'ng a
zero-voltage .witch.

biased to inhibit output pulses. When the push button is
depressed, pulses are generated, but the state of Qo
determines the requirement for their supply to the triac gate.
The first pulse generated serves as a "framing pulse" and does
not trigger the triac but toggles FF·J. Transistor QG is then
turned off. The second pulse triggers the triac and FF-I which,
in turn, toggles the second flip-flop FF-2. The output of FF-2
turns on transistor QJ, as shown in Fig. 55, which inhibits all
further output pUlses. When the pushbutton is released, the
circuit resets itself until the process is repeated with the
button. Fig. 56 shows the timing diagram for the described
operating sequence.

PHASE CONTROL CIRCUIT
Fig. 57 shows a circuit using a CAlOS8 or CAlOS9
zero-voltase
swilch together
with
two
CAl086
lntegrated-circuit transistor arrays to . form a phase-control
circult. This circuit i. specifically designed for speed control of
Be induction motors", but may also be used as a light dimmer.

The circuit, which can be operated from a line frequency of the CA30S9 and .associated positive feedback circuitry (51·
SO-Hz to 4oo-Hz, consists of a zero-voltage detector I a kilohm resistor and 36·kllohm/'l2·kllohm voltage divider).
line-synchronized ramp generator, a zero-current detector, and When the pulse occurs at terminal No. I, the triac is turned off
a line·derived control circuit (i.e., the zero~voltage switch). The and held off in a similar manner. Note that power for the
zero-voltage detector (part of CAJ086 No. I) and the ramp CA3240E is derived from the CA30S9 internal power supply .
senerator (CA3086 No.2) provide a line..ynchronized . The advantage of u.lng the CA3240E In this circuit i. that it
ramp-voltage output to terminal 13 of the zero-voltage switch. can sense the small currents associated with skin· conduction
The ramp voltage; which has a starting voltage of 1.8 volts, While maintaining sufficiently high circuit impedance to prostarts to rise after the line voltage passes the zero pOint. The tect against electrical shock.
ramp generator has an oscillation frequency of twice the
TRIAC POWER CONTROLS FOR
incoming line frequency. The slope of the ramp voltage can be
THREE·PHASE SYSTEMS
adjusted by variation of the resistance of the I-megohm
ramp-control potentiometer. The output phase can be
This section describes recommended configurations for
controlled easily to provide 1800 firing of the triac by power-control circuits intended for use with both inductive
programming the voltage at terminal9 of the zero-voltage and resistive balanced Ihree:phase loads. The specific design
switch. The basic operation of the zero-voltage switch driving a reqUirements for each type of loading condition are discussed.
thyristor with an inductive load was explained previously in
described,
the
In
the
power-control
circuits
the discussion on switching of inductive loads.
integrated-circuit zero-voltage switch is used as. the trigger
circuit for the power triacs. The following conditions are also
imposed in the design of the. triac control circuits:
ON/OFF TOUCH SWITCH
I. The load shOUld be connected in a three.wire
The on/off touch switch shown in Fig. 58 uses the CA3240E
configl!-ration with the triacs placed external to the load;
to sense small currents flowing between two contact points on
eiter delta or wye arrangements may be used. Four-wire
a touch plate consisting of a PC board metallization "grid".
loads in wye configurations can be handled as three
When the on plate is touched, current flows between the two
independent Single-phase systems. Delta configurations in
halves of the grid, causing a positive shift in the output voltage
which a triac is connected within each phase rather than
(terminal 7) of the CA3240E. These positive transitions are fed
in the incoming lines can also be handled as three
into the CA3059, which is used as a latching circuit and zeroindependent single-phase systems.
crossing triac driver. When a positive pulse occurs at terminal
2. Only one lo~c command signal is available for the
No.7 of the CA3240E, the triac Js turned on and held on by

514 _______________________________________________________________

ICAN·6182
ZERO

LINE I;!.OVAC
INPUT 60 HI

VOLTAGE
DETECTOR

LOAD

Fig. 57 - Phsu Control circuit using II CA3058 or CA3059 IIfId two
CA3086 integrated-circuits.

..

,

,-Wlr----t"-o I~Y
60HI

3. Two phases must be turned on for initial starting of the
system. These two phases form a single·phase circuit
which is out of phase with both of its component phases.
The single·phase circuit leads one phase by 30 degrees
and lags the other phase by 30 degrees.
These conditions indicate that in order to maintain a
system in which no appreciable RFI is generated by the
switching action from initial starting through the steady--state
operating condition, the system must first be turned on, by
zero·voltage SWitching, as a single·phase circuit and then must
revert to synchronous three-phase operation.
Fig, 60 shows a Simplified circuit configuration of a
three-phase heater control that employs zero·voltage
synctuonous switching in the steady--state operating condition,
with random starting. In this system, the logic command to
turn on the system is given when heat is required, and the
command to turn off the system is given when heat is not
required, Time proportioning heat control is also possible
through the use of logic commands.
The three pboto-coupled inputs to the three zero·yoltage
switches change state simultaneously in response to a "logic
command", The zero-voltage switches then provide a positiye
pulse, approximately 100 microseconds in duration, only at a
zero·voltage crossing relative to their particular phase. A
balanced three·phase sensing circuit is set up with the three
zero-yoltage switches each connected to a particular phase on
their common side (terminal 7) and referenced at their high
side (terminal 5). through the current-limiting resistors R4,
RS, and R6, to an established artificial neutral point. This
artificial neutral point is electrically equivalent to the
inaccessible neutral point of the wye type of three·wire load
and. therefore, is used to establish the desired phase
relationships. The same artificial neutral point is also used ~o
establish the proper phase relationships for a delta type of
three·wire load. Because only one triac is pulsed on at a time,
the diodes (01. D2, and 03) are necessary to trigger the
opposite-polarity triac, and, in this way, to assure initial
latching-on of the system. The three resistors (Rt. R2, and
R3) are used for current limiting of the gate drive when the
opposite-polarity triac is triggered on by the line voltage.
In critical applications that require suppression of all
generated RFI, the circuit shown in Fig. 61 may be used. In
addition to synchronous steady..state operating conditions, this
circuit also incorporates a zero·yoltage starting circuit. The
start-up condition is ," A:ero.yoltage synchronized to a
single-phase, 2·wire, line~to-line circuit. comprised of phases A
and B. The logic comm~d engages the single-phase start-up
switch
and
three.phase
photo~oupled
zero-voltage
isolators OCI3, OCl4, OCIS through the photo-coupled

IN914

IN914

llOOt>f

I&YDC

•• M

Fig. 58 - On-o" much swiU:h.

control circuits. This signal must be electrically isolated
from the three.phase power system.
3. Three separate triac gating signals are required.
4. For operation with resistive loads, the zero·yoltage
sWitching technique should be used to minimize any
radio.frequency interference (RFI) that may be
generated.
1 _ of DC LotIIc CIrcuitry

As explained earlier under Spec'" Applicatloa
CoaoIdontIou, isolation of the de losic circuitry' from the ac
line, the triac, and the load circuit is often desirable even in
many linsIe.phase power-control applications. In control
circuits for polyphase power systems, howewr, this type of
idation is essential, because the common point of the dc logic
circuitry cannot be referenced to a cornman line in all phases.
• The de Josie circuitry provides the Iow-lcvcl electrical signal that
dictates the state of the load, For tempenture controls, the de Ioaic
circuitry Includes • tempusture tensor for feedback. 1he RCA
inlep'.ted-circuit zero.voJtqe switch. when operated in the dc mode
with lORIe addJtiOll.al drcuitry. can replace the dc IoJic circuitry for
temperature controls.

In the three·phase circuits described in this section,
photo-optic techniques (i.e., photo-coupled isolators) are used
to provide the electrical isolation of the de logic command
signal from the ac circuits and the load. The photo-coupled
isolators consist of an infrared light-emitting diode aimed at a
silicon photo transistor, coupled in a common package. The
Iight-emitting diode is the input section, and the photo
transistor is the output section. The two components provide a
voltage isolation typically of 1500 volts. Other isolation
techniques, such as pulse transformers, magnetoresistors, or
reed relays, can also be used with some circuit modifications.

(a)

Resistive Loads
Fig. 59 illustrates the basic phase relationships of a
balanced three.phase resistive. load, such as may be used in
heater applications. in which the application of load power is
(b)

controUed by .ero-..,Itage switching. The following conditions
are inherent in this type of application:
1. The phases are 120 degrees apart; consequently, all three
phases cannot be switched on simultaneously at zero
..,Itage.
2. A single phase of a wye configuration type of three·wire
"system cannot be turned on.

Fig. 59 - VoItIIfI" p/we rei.tJomhlp fo, 11 thTH·plwl1 resistive lOild
wilen the lIpp1ication of 10ild paM' ;s controlled by
Bro·volt.,. switching: fill volt. WllIIfIfo,ms, (b} 10000-circuit
orientlltion o~ voItIIges. (The dashed lines indlCllttJ thfl no""'"
Nl/ationship of the phllffll und., stNdy..stlltfl conditions, Th8
dewlltion lit Itllrt-up lind tum.,," should bII nottld.J

__________________________________________________________________ 515

ICAN·6182
isolators OC11 and OC12. The single-phase- - zero-voltage
switch, which is synchronized to phases A and B, starts the
system at zero voltage. As soon as start-up is accomplished, the
three photo-coupled isolators OC13, OCl4, and OClS take
control, and three-phase synchronization begins. When the
"logic command" is turned off. all control is ended, and the
triaes automatically tum off when the sine-wave current
decreases to zero. Once the first phase turns off, the other two
will turn off simultaneously, 90° later, as a single-phase
line-to-line circuit, as is apparent from Fig. 59.

3' INPUT

r

\

(' ~

3-PHASE
RESISTIVE LOAD

\

tOEUA OR WYEI

• FORMERLY RCA 44003
• FORMERLY RCA 40108

Fig. 60 - Simplified diagram of a thrfIfJ·phase heater control that
employs zero-yoltage synchronous switching in the

steady-state opelating conditions,

'.

:5 PHASE
RESISTIVE
LOAD
(DELTA OR WYE)

Inductive L~.
For inductive loads, zero-voltage turn-on is not generally
required because the inductive current cannot increase
instantaneously; therefore, the amount of RFI generated is
usually negligible. Also, because of the lagging nature of the
inductive current, the triacs cannot be pulse-fired at zero
voltage. There are several ways in which the zero-voltage
switch may be interfaced to a triac for inductive-load
applications. The most direct approach is to use the
zero-voltage switch in the dc mode, Le., to provide a
continuous dc output instead of pulses at pOints of
zero-voltage crossing. This mode of operation is accomplished
by connection of terminal 12 to terminal 7, as shown in
Fig. 62. The output of the zero-voltage switch should also be
limited to approximately 5 milliamperes in the dc mode by the
750-ohm series resistor. Use of a triac stfch as the T230ID* is
recommended for this application. Terminal 3 is connected to
terminal 2 to limit the steady-state power dissipation within
the zero·voltage switch. For most three-phase inductive load
applications, the current-handling capability of the 40692 triac
(2.5 amperes) is not sufficient. There(ore, the 40692 is used as
a trigger triac to turn on any other currently available power
triac that may be used. The trigger triac is used only to provide
trigger pulses to the gate of the power triac (one pulse per half
cycle); the power dissipation in this device, therefore, will be
minimal.
Simplified circuits using pulse transformers and reed relays
will also work quite satisfactorily in this type of application.
The RC networks across the three power triacs are used for
suppression of the commutating dv/dt when the circuit
operates into inductive loads ..
The specific integrated·circuits, triacs. SCR's, and rectifiers
included in circuit diagrams shown in this Application Note are
listed below. Additional information on these devices can be
obtained by requesting the applicable RCA data-bulletin file
number.

Type No.
CA3058, CA3059, and CA3079
CA3099E
CA3086
CA3080
CD4007A,CD4013A
2N5444
T2800B (40668)
T2300B (40526)
T230lB (40691), T23010 (40692)
T64170 (40708)
S26000 (40655)
0120IB(44003)
D3202U (45412)

FileNo.
490
620
483
475
479
456
364
470
431
406
496
495
577

NC?te: Numbers in parenthesis (e.g. 40668) are former
RCA type numbers .
• FORMERLY RCA 4""003
efORMERU ACA 40708

Fig. 61 - Th,ee-phllSfI

power

control

that

employs

zero:voltage

• Formerly RCA 40692

synchronous switching both for steady-statB operation and
for starting.

516 ___________________________________________________________________

ICAN·6182

Fig. 62 - Triac three-phase control circuit for an inductive load, i.e.,

three·ph;ue motor.

517

ICAN-6222
at terminal I] to avoid exceeding the VeBa rating of super·
beta transistors O} and Q2' This factor is normally a design
consideration only when one or both of the input-stage transistors is to be biased off.

DESIGNING WITH AN Ie TRANSISTOR ARRAY
CONTAINING MATCHED
SUPER-BETA TRANSISTORS

low-Frequency Operation

by T. J. Robe
Many small-signal, low-frequency. and video-frequency applications require an amplifying device with a very high input
impedance, low input-bias current, and low-noise characteristics
that can maintain low de offset voltage and drift. Examples of
such applications include:
Small-signal instrumentation - chart recorders, meters, etc.
Pre-amps for op-amps.
Magnetic tape-head and phono-cartridge amplifiers.
Oplo-electric amplifiers.
Medical electronics.
Devices suitable for such applications are also generally
applicable in circuits having tong time constants, such as
timers, integrators, monos table oscillators, comparators. and
low-frequency oscillators. Matched super-beta transistors arc
well suited for use in these applications.
Super-beta transistors are similar to conventional bipolar
transistors except that they have betas in the range of 1000 to
5000; the beta range of a conventional bipolar transistor is
from 50 to 400. Since super·beta transistors are commonly
used in high·souree-impedance applications that require high
input impedance and low-noise characteristics, it is equally
important that they exhibit super·beta performance at operating
currents of a few microamperes. On the other hand, to achieve
broadband characteristics in Video-amplifier applications, super·
beta performance must be maintained with collector currents
of I milliampere ormore. This Note describes the RCA-CA3095
super-beta transistor array and discusses its operation in some
typical applications.
A TRANSISTOR·ARRAY Ie CONTAINING SUPER·BETA
TRANSISTORS

Fig.1 shows the schematic diagram of the RCA-CA3095E, a
monolithic ICI containing an array of n·p-n transistors of
which QI and Q2 have super-beta characteristics. Q} and 02
are connected, in conjunction with transistors 03 and 04, in a
differcntial-cascode-amplifier configuration. Since the superbeta transistors in this IC have a collector-emitter breakdown
voltage V(BR)CEO of about 2 volts, it is necessary to limit the
collector-emitter voltage accordingly. Limiting is accomplished

input base-bias currents. Implicit in this performance are high
input impedance, low'noise, and low de offset-error effects.
Transistors OS' 06, and 07 are conventional n-p-n types
with betas in the range of 150 to 400 at collector currents in
the range of I microampere to 10 milliamperes, These Iran·
sistors also have a minimum colleclor-emitter breakdown voltage V(BR)CEO of 35 volts.
Operating the Super-Beta, Differential-Cascode Amplifier
Application of the differential-cascode amplifier in the
CA309SE is similar to that of the classical differential-cascode
amplifier; differential input signals are applied at terminals 7
and 9 with balanced collector loads connected from terminrus
6 and 10 to the positive supply voltage. The common emitter
connection, terminal 8, may be made directly or through a
"current source" (e.g.• a transistor or resistor) to the negative
supply voltage. The circuit in Fig. 2 illustrates the use of
"mirrored" transistors (07' 08) as a constant-current source
to provide high emitter impedance for the differential-cascode
amplifier. As an alternative, a resistor may be used as a
"current source" (as illustrated by the circuit in Figs. 8,9,
and II). The Ie substrate (terminalS) is usually connected directly to the negative supply terminal, as shown in Fig, 2, be~
cause it must be maintained at the most negative potential of
all elements on the CA3095E chip.
The only additional requirement for CA3095E operation is
for bias current into terminal 11 to forward-bias the network
composed of I?l, D2 and OS, and to supply base-bias cur~
rent for transistors 03 and 04. This base-bias current can
be provided by connecting a dropping resistor between termi·
nal II and the positive supply voltage; this arrangement is
illustrated by the use of resistor RBlAS in Fig. 2. As an
alternative, this current can be supplied from the positive
supply to terminal J I through a p-n-p constant-current-source
transistor to maximize common-mode and power-supply rejection characteristics. In most applications, however, such a
v·

06

14

07
2 1&

,

oa

e

.3

13

lid =26 mV X the number ofp-n junctions in the input stage
lIB (in nA)

15

Mn

where liB is the input·stage base-bias current. Consequently,
the input bias current (lIB) must be quite low if a high input
impedance is to be established. The characteristics of the
super-beta transistors in the CA309SE are well suited for use

Vi

*llll·~~~~O:r~C~I~~~~I~;l AND (7}
Fig. 3 - Input cin::uit for tM diffe,.,,,,tilllsmplifier.

in dc amplifiers requhing high input impedance. For example,
with the super-beta transistors operating at input-stage emitter
currents of I microampere and an HFE of 2000, the basebias current is only 0.5 nanoampere. Under these conditions.
lid =' 26

1i1
4

When an amplifier is to operate at very low frequencies, or
as a dc amplifier, the signal source must be directly coupled to
the amplifier input. This coupling requires the use of an
amplifying device with a very low input de offset error and
low offset-error drift with temperature variations. A matched
differential-cascode amplifier, like the one used in the
CA3095E, is particularly well suited to this requirement, not
only because of it~ low input offset voltage (VIO = I mV,
typical), but also because of its low input offset current (10 =
4 nA. typical, at IC = 100 IJA). When the input signal is pro~
vided from a high-impedance source (Ri), both of these
characteristics assume importance because the total effective
input-offset-voltage error is the sum of their effects:
Total Offset Error = VIO + IIORs
The differential input impedance in megohms (lid in Fig. 3)
of an amplifier operating at low frequenCies is given by:

~~ ~

2

= 104 megohms

Impedance levels of this order can also be realized by wing
negative feedback in connection with devices havbIg higher
input bias currents, as iUustrated ~y the circuit shown in
Fig. 4. In this arrangement, the use of the feedback network
effectively multiplies the differential input impedance. Unfortunately, this arrangement does not avoid the inpUI-1....,r-l~TPUT

L-.......

+Vcc
(TO PINI2)
MANUAL
CHROMA
GAIN
CONTROL

I
I
I

I
I
I
I
.50
I"

ROO
2K

_
.,NTERNAL

I

~!!!.L~D~~!2!' _ _ _ _ J _ ~A':..J

F1,. 6- Chromll outpUt st. .

collector of Q25 to the emitten of Q6S and Q24' The diode
D3 compensates the base to emitter potential of the transistor
Q25'
Since the bias resistors R.w. ~l' and R.t7,"and also the
amplifier load resistor R43, are loeated on the same IC chip,
the resistance ratio of these components is accurately controlled. Thus, the gain of the second chroma amplifier
determined by these components is very predictable. and is a
function of the bias potential applied to the base of transistor
Q67 only.

The interfacing of IC's with external control circuits usually
presents problems due to the large tolerances associated with
both components. The circuit used here overcomes these
difficulties. The transistor follower Q67 exhibits negligible
loading on the bias set by the manual chroma control. Thus,
the gain of the second chroma amplifier is uniquely determined by the rotation of the gain control potentiometer and is
relatively independent of its resistance value.
The killer operation is also performed on the second chroma
amplifier. The amplified output from the ACC-killer detector
is applied to the killer switch Q20' In the presence of a burst
signal, transistor Q20 is off and the chroma amplifier remains
undisturbed. In the absence of a burst Signal, the collector current in Q20 reduces the potential on the base of the transistor
Q67 so as to cut off the second chroma amplifier.
The Overload Detector

The ACe and the manually operated saturation control
provide the essential means to maintain the proper chrominance level to the picture tube. Under certain conditions,
however, the presence of the ACC is detrimental. As previously stated, the ACC servo loop maintains a constant output level of the burst signal regardless of the chroma information. Transmitter variations in burst-to-chroma ratios are im·
properly corrected by the ACC action and, on signals with low
burst-to-chroma ratios, the excessively amplified chroma can
exceed the dynamic range of the picture tube.

Similar overload problems are experienced when receiving

weak signals. The Synchronous ACC detector produces a control signal proportional to the average value of the burst interval signal, and noise does not contribute to the output. Although this type of nolJe4mmune detection Is neceswy for
reliable operation of the kDJer circuits, It Is I... desirable for
the ACC action because the nolse-peaks plus slgIlol tend to produce undesirable over-saturation effects_
The overload detector operating on the second chroma
stage eliminates both these overload problems. The chroma
signal from the output terminal of the second chroma amplifier is coupled, by means of the coupling capacitor Cfb to overload detector Q22. Transistor Q22 is biased by means of an
internal bias supply to 0.5 V, and remains off untiJ its base
potential is raised to approximately 0.7 V. Thus, detection
takes place whenever the chroma signal plus de bias is equal to
or exceeds 0.7 V. The detected and filtered signal lowers the
bias potential on the base of transistor Q67 and reduces the
gain of the output stage.

KEYING CIRCUITS
Deta!!s of the keying circuit and of the internal bias circuits are shown in the complete diagram of the CA3126Q in
Fig. 7. A positive horizontal .rate keying pulse applied to
terminal 9 activates the keying circuit. This circuit maintains
the AFPC and ACC detectors, with the corresponding sampleand-hold circuit, in the ON position during the keying interval.
and disables the chroma output stage at the same time.
CONCLUSION
The new chroma processing circuit improves the performance of a color television receiver. The use of synchronous detection and sampling results in excellent signal
stability and fewer external components and adjustments. An
overload detector prevents, over-satuntion of the picture
tube, and the improved manual control simplifies the adjustment of the chroma level.

524 __________________________________________________________- - - - -

ICAN-6247

RF BY PASS

AFPC FILTER

CARRIER

XTAL FILTER

4
'0
GJ' 'ev
0'
oUCit
1-----1----,---,---- ,---,------,
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071 I

AMPLIFIER

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2.1 K

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2.2K

5:10

- CHROMA
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AMPLifiER
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I

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VOLTAGE REFERENCES !

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RESIS lANCE VALUE ARE IN OHMS

Fig. 7- Complere circuit diagram showing details of the keying circuit
and internal bias circuits.

__________________________________________________________________ 525

ICAN-6257
Application of the CA3089E FM-IF Subsystem
by l. S. Baar
The RCA·CA3089E, shown in Fig. I, is an FM·IF
subsystem intended for use in FM receiver applications. In

addition to the amplifier-limiter and quadrature detector
sections, the CA3089E provides such auxiliary functions as
mule, AFC output, tuning-meter output, and delayed
rf·AGe l This Note briefly descrihes each drcuil section

approximately 8 volts over a temperature range of -400C to
+JOOOC while maintaining the performance of the device
virtually unchanged. The typicaJ curves in Figs. 3 through 7
illustrate these characteristics. A reference voltage brought
out to pin 10 may be used in conjunction with the AFC, if
desired.

and discusses practical aspects of designing with this device.
Circuit Description
The three-stage direct-coupled amplifier·limiter uses a
cascade input stage to reduce input noise and provide better
stability. The peak.lo-peak swing of approximately 300

Stability Considerations
Because the CA3089E is a very high gain device, the
external circuit must be laid out carefully to eliminate or
reduce any feedback path. 2 Fig. 8 shows a ID.7-MHz

~

i~

~~

."
23

22

~o

•~i
~~

~

400

-I-- V

~~1

FT~'

-

RECOVEREO AUOIO

\-- \--

300 f--....- - -

L'O...-.

;i~

."~~ "t/ffi~

",

\--

.. -

"

3-dt
,

l

LIMll1 NG

"

"

"

.

,

"

fig. 3- Supply current, recoVtJred audio, and input limiting III a
function of $upply lIolttJgB.

RF-AGC VOL1S AT 'in

I

~

.10 mV

,~-+--+-.--~-+-~-+--~~

"
~

METER OUTPUT AT 'in ·!'jOO~V

f-+---t-+

SUPPLY

"'OLTAGE~V

"

Fig. 4- Referem.:e voltags. rf·AGC, and meter output as 8 function of
$upply voltage.

........
Fig. 1- Schematic diagram of the CA3089E.

millivolts is developed across the 390-0hm resistor, R31, at
pin 8. The operating· point stability is provided by dc
feedback to the input stage. The input voltage for an output
3 dB below limiting is typically J 2 microvolts rms.
The detector is a doubly balanced circuit driven
symmetrically by the output of the if amplifier. The voltage
at pin 8 is coupled through a reactance to the tuned circuit at
pin 9. The detector output is taken from both sides and
combined differentially to produce an audio output and
automatic·frequency·control voltage. The audio output may
be attenuated by a current driving pin 5. The current is

printed·circuit·board layout of the circuit in Fig. 9(a). The
ground-plane layout was devised to prevent large rf currents
at the output terminals from returning to the input grounds.
Bypass-capacitor grounds also were selected to achieve the
same purpose. It is recommended that bypass capacitors be
placed on terminals of the auxiliary functions since most of

"i=I--........,-!-.....,...,L=+_-F"'-::::j~_---il--_---1

~o

,~~.+_-+

~~
~i

3dB LIMITING

__-+__ +____~_~_~

20

'"

TENPERATURE-·C

FifJ. 5- Input: limitinll lind rtlCOVllred audio

normally provided by the mute drive, which reduces the level
by more than 50 dB. Fig. 2 shows the detector and
audio-AFC translator circuits redrawn to illustrate the
balanced circuitry. The audio output is developed across a
S,OOO·ohm resistor. R49, Fig. I. The AFC output can be used
either as a current or voltage source.
The meter output and rf-AGe circuits are driven by three
level detectors which detect the output levels of each of the
if amplifier stages. The tuning-meter circuit sums these levels
and provides a voltage which is a function of the input signal.
Th,e rf-AGe circuit is driven by the level detector connected
to the output of the first amplifier stage, which provides the
delay, The mute logic output is developed from the output
of the third limiter. With a large signal, the if envelope is
detected, and drives the mute logic voltage low. As the
signal· to-noise ratio deteriorates, "holes" are created in the
envelope; these "holes" are detected, and provide the voltage
to drive pin 5.
The bias supply maintains the device current drain
virtually constant from a supply voltage of 16 volts to

lh.

function of

~~ratuf'fl,

Pin 10 AEFERENCE "'O~TAGE

Fig. 2- Detector, audio, and AFC circuits.

them are connected to rectifier circuits which are not
completely filtered within the device. Capacitors of the disc
ceramic type with a 0.01- to 0.02·microfarad value are
usually good bypass capacitors at 10.7 MHz. Larger values
may exhibit a self-resonance below 10.7 MHz, and actually

METER OUTPUT AT 'in ·500 ... '"

TEMPERATURE-OC

Fig. -6- Rl1ft1ffl"r:£'j(J1tags~ rf,AGC, lind meter output a$ a function of
temperatuf'fl.

526 ______________________~----__------____--------~------------------

ICAN·8257
'! ..
8
~
~

IS

~

U~

SUPPLY CIHfRtNT

2Z

~

~~
~6

-

f--l.

'-.20

r-- r--

---

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f-- --_ ..

0

AfC

VlTAGE- Tr~ 1-10 TROSS .sO~~

~~ -20
-00

·20

•

T O'~i

2.

40

••

r---....

eo

linearity Improves as the bandwidth Incre.... ; however,
recovered audio decreases. A satisfactory compromise for
most PM·receiver appUcations is reflected in the circuit of
FiS. 9(1). This circuit typically provide. 400 mllIivolts on. of
recovered audio with less than D,S'percent distortion.
Because a double· tuned circuit has better phase linearity over
a wider bandwidth, distortion fisure. oness than O.l-percent
are attainable with the network used in the circuit of Fig.
9(b). Proper alignment and coupling adjustment of the
double-tuned circuit are most easily accomplished whlle
viewing the resulting S curve. Initial adjustment of the
primary tuning slug to the proper crossover is made with the
secondary ,IuS removed_ The secondary tunins sluS is then

100

measurins distortion. The coupling may be varied by either
moving the coils or by changing the value of the secondary
load resistor.
Various circuit values can be used to obtain the same
recovered audio, but the basic conditions of circuit
bandwidth and phase linearity must be maintained. The
detector circuit also sets up conditions which are required for
proper operation of the mute circuit. The rf voltage on pin 9
must be held at approximately 17S millivolts rms, ±25
millivolts. The reason for this requirement is discussed
subsequently in cOMection with the mute logic circuit. The
approximate voltage at pin 9 is determined from the
equivalent circuit shown in Fig. 10.
The peak·ta-peak voltage on pin 9 is:

IV91"IV81~

TEhlP£RATURE-·C

Fifo 1- Supply cumnt lind AFC

rot,.",.,

II

function of ftI~tu,..

exhibit inductive reactance at their terminals. The nominal
input Impedance of the CA3089E is approximately 9,000
oluns, and it is not recommended that an impedance match

where R 1 is the total parallel resistance and V8 is
approximately 300 millivolts, peak.te>peak.

SIGNAl..

be attempted. Most commercial receivers use ceramic-mtcr
"""'''''''''~r- AUDIO

frequency-selective elements that normally have source
impedances of SOD ohms or less. When these fllters are
properly terminated with loading resistors, the typical source
impedance is further decreased to 250 ohms or less. Higher
levels of source impedance are possible with very careful

OUTPUT

circuit layout; however. the maintenance of stability could
be difficult.
The CA3089E has a frequency response that is typically
flat to 20 MHz; consequently, the device can provide useful
gain weD above that frequency. If the device is used at tower
frequencies, the larger.value bypass capacitors required may
not be adequate to bypass the higher frequencies. Double

AI.L RESISTANCE VALUES ARIE IN OHMS

-I.. TUNES WITH 100pF lei AT 10.7 MHz

00IUNLOADEO'-7!r1 IG.J. AUTOMATIC M'G. DIV. IEU274' OR EOUIYAl.ENTI

bypaslinS with lower-value clpaclton can overcome such 1
problem. Another means of aIIeviatlns the problem is to
externally reduce the frequency response by using a small
capacitan<:e across the output load of the device.

The Q of the tuned circuit between pins 9 and 10 may be
affected by the effective Q of the choke between pins 8 and
9 and the series resistor R31 in the CA3089E. All of the
above factors should be considered in selecting circuit values.
Table I lists some typical combinations of component values
under various conditions.
A choke is normally selected to equalize delays in the
signal path and in the limiter-quadrature path. It also
reduces t~e if harmonic content across the quadrature
circuit. In some cases, such as in narrow· band applications, it
may become necessary to use a capacitor as the coupling
component where large values of inductance with high Q's
are difficult to obtain. Ifa capacitor is used, the phase of the
recovered audio and AFC voltage will be reversed, some
asymmetry of the S curve may result, and the distortion may
be adversely affected to a small degree.
As indicated above, the inductance between pins 8 and 9
tends to equalize delays in the detector signal paths. The
matching of elements of the IC in the balanced detector

lal

r--,

I :!II( I
i,oopl'" I

~

i

'lJ~J"

Fig. ID-EqullMltlnt circuit wed to tMrermln".pproxim.r. ron.,. on
pin 9 of the CA308SE In FI,. 9.
"'''"''~-- AUDIO

OUTPUT

II)

Bortom viflW of printtld-c;rcu;r board.

ALL RESISTANCE VALUES ARE IN OHMS

-T: PRI.-00(UNLOADEDI1I7SITUNES WITH 100 pF (CII 201 OF 34, ON 7152" OIA. FORM
s£c.-QoCUNLOADEOI1l7SITUNES WITH IOOpFIC21 20t OF 34, OJ,! 7/32"DIA. FeRM
kQCPERCENT OF CRITICAL COUPLlNG'_ 70%
.IAD~USTE()

FOR COIL VOLTAGEVCI·ISOrrN

A80VE VALUES PERMIT PROPER OPERATION OF MUTE (SQUELCHl ORCUtT
"E" T'toPE SLUGS,SPACING 4mlll,

b) Component side - top view.

Ib)

Fig.B.-.CA3al9E MId tJIItbfMnl co,..,."rsmounflldDIJ.

pr/nr.d circuit botIrd.

Iluadntu... o.r- Circulll
The quadrature-detector tuned circuit is connected
between pins 9 and 10. The sisnal volta&" at pin 8 is
normally coupled to pin 9 throush a choke. The circuit
values for the detector network are determined by several
factors, the primary one being distortion at a particular level
of recovered audio. Distortion is determined by the phase
linearity of the quadrature network and is not influenced by
the device unless excessive, recovered audio overdrives the
audio circuit. With a single tuned network, the phase

Fig. 9- (s) TNt circuit for th. CA3089E rning a s;n~.·tuned dtlftlctor
.coil, (b) test circuit for the CA3089E using II double-rUMd
dtttector coil.

adjusted until '8 slight "ripple" is observed moving along the
S curve. If the ripple is excessive (enough to distort the S
curve) the coupling is too tight. If no ripple is observed, the
coupling is too loose. As the ripple moves through the
crossover point, it will be observed that the S curve becomes
more linear near the center frequency. Slight readjustment of
both slugs may be necessary for fmal alignment. The best
performance can then be achieved by slight adjustment while

circuit results in an AFC output with a very smaU offset
when referred to the voltage at pin 10. For most
applications, the inherent offset variation is weD within
tolerances, and does not affect circuit performance. In some
narrow·band applications, however, the offset becomes more
critical because of the very narrow bandwidth. In such
situations, the combination of normal production variations
of the device and the external circuit components results in
receiver detuning when the AFC loop is closed. This detuning
results in an increased distortion of the recovered audio. This
distortion can be corrected with the addition of a variable
capacitor from pin 8 to ground to provide phase
compensation. The capacitor can be adjusted to provide zero
AFC offset with minimum distortion. Generally, the offset is
in one direction for'3 given set of conditions .. The addition of
a fixed capacitor wUl minimize variations sufficiently to
satisfy many applications. A value of 5 picofarads is an
effective value for the circuit of Fig. 9(a) with the
recommended PC·board layout. Conversely, the offset
created by using a capacitor between pins 8 and 9, as
mentioned earlier, may be compensated by placing an
inductance between pins 8 and 10.
Audio and AFC Circuib
The audio and AFC circuits are very similar, and both
develop the same audio signal at their respective output
tenninals. The audio output voltage on pin 6 is developed
across an internal. nominal. S.OOO·ohm resistor (R49)
connected to the S.6-volt reference. In addition, the audio
signal level .can be attenuated by providing' a direct current
into pin'S without any shift in its dc level. The audio output,

____________________________________________________________________ 527

ICAN-6257
TABLE I - FIG. 10 COMPONENT VALUES AND CHARACTERISTICS AS A FUNCTION OF FREQUENCV

-....

QL,

L,

C,

~

J!!L

~

"'

X (pin 8 to pin 91

(~I

10.7M

2.21J

75

100

3900

2211H

10.7M

2.21J.

120

100

10.7M

2.2/J.

120

100

455k

a.1m

65

1000

I MHz when measured in the circuit shown.
The AFC output at pin 7 is a current source and. if
terminated with 5,000 ohms, win provide an audio output
identical to that at pin 6. The AFC output may be referenced
to a wide range of voltages, from near ground potential to

Recowr.dAudio

fmVI

~
±75

400

12011H

is

280

1.3pF

is

290

lmH

is

400

68.

as shown in Fig. II, is uniform to a frequency of more than

..........

.,

DC VOI.TAGE SUPPLY II 012'1
,,"81ENT TtMPP..TURE nA 1_+2!"C
TEST CIRCUIT - SEE FIG.'''')

are suggested ones, and may be altered to suit the uller. Curve
A in Fig. 12 showS the change in audio output level as a
function of input signal with the mute-threshold control
circuit (also shown in Fig. 12) at its maximum-voltage
setting. Because of the more shallow slope and the larger
circuit time constant mvolve,p."\~~'

~~\"!Io.~oG

-- ~

~,

,I

100
IK
INPUT SIGNAL-p.V

/

Dc'

10K

R3

;ook "'0

o.

0.'

,

rf-AGe voltase is driven by the level detector connected to
the first if stage. As a result, no output is detected until the
input signal is large enough to drive the peak detector; the
result is a delayed AGe action. The curve of rf-AGe voltage
as a function of input signal is also shown in Fig. 13.

-20

o

5011
SO.

~

I---

I
I

Fig. 13- Tuner AGe IIIId tuning-mettlr output .. • function of Input
IIgna/I/O/"""

,

·'0

~

~g

I

TUNER AGC DC VOLTAGE ..T ..........
TERM1NAL Nol5
1

10

;t

!/

..i
0

§

I

but also harmonics developed when successive stages go into
limiting and eventuaUy form a square wave. The result is a
logarithmic de output as a function of input signal, as shown
by the curve in Fig. 13. The circuit developing the delayed

cu,..,

Curves Band C illustrate the chanse in the curves resulting
from adjustment of the values of the threshold control
circuit. These latter circuits provide a faster acting mute. The
fixed resistor, RI, in addition to controlling the slope of the
mute characteristic, limits the voitage appearing at pin S. The
use of this resistor is recommended to prevent a latch.up at
the attenuating circuit, which, if it occurs, maintains the
circuit in muted condition until the supply voltage is
removed.
The curves in Fig. 12 show that the muting action cannot
be initiated under any condition until some ·noise is present
in the output signal. In this respect, the mute perfonnance of
the CA3089E diffen from that of some other systems which
are activated by signal leveL Such systems can be adjusted to
allow noise-free signals to be processed further. When the
CA3089E circuit operates under small-signal conditions,
noise may be audible. before muting action occurs. The
threshold-level adjustment only permits more or less noise to
appear at the output; a listener can use the control to adjust
the interstation hiss to the level of his preference.
Tuning Mete. and RF·AGC a ....it
The tuning-meter circuit sums the output of three peak
detectors connected to successive stages of the if
amplifier-limiter. These circuits detect not only the carrier,

IF Amplilior/Dotacta. System II1d Stano Docodor
Fig. 14 shows the circuit diagram of a complete FM-if
detector system driving a stereo decoder. Using the
selectivity of two ceramic mters, the CAJ089E in
conjunction with the CA3090AQ stereo decoder provides the
basic signal processing between the tuner output and the
audio amplifiers. The gain of the silicon n·p-n
bipolar·transistor stage is adjusted to make up the losses of
the two filters. In addition to driving a tuning meter, the
voltage at pin 13 of the CA3089E may be used to drive a
··stereo defeat" circuit in the CAJ090AQ, thereby holding
the decoder in a monaural condition to improve the
signal-to-noise ratio under weak signal conditions. A
_.ted PC-board pattern and parts layout are shown in

FiB-IS.
Opontion at Frequl11Cies 0\I1e. Than 10.7 MHz

Because the CA3089E was designed for use in PM
broadcast receivers, its circuits are optimized for use at 10.7
MHz. Nevertheless, the device performs equally well over a
wide range of frequencies both above and below 10.1. MHz.
nie if amplifier response is essentiaDy flat from dc to more
than 20 MHz. The operation of the detector circuit is
dependent only on the external components. The operation
of the auxiliary sectlons-rf·AGC, meter output, and mute
logic - depend on internal peak. detectors, and, as a
consequence, their performance at lower frequendes is
limited. The internal capacito.. were optimized for 10.7 MHz
operation, and are too small to operate effectively at lower
frequencies. The detector efnciencies begin to deteriorate at
about 2 MHz. and the detectors are essentlaRy unusable at

Another condition affe.cting proper mute performance is
excessive gain in the tuner or preceding if stages. High gain
ahead of the CA3089E under a· condition of low
signal-te-noise ratio results in the noise being clipped by the
limiting amplifiers. The clipping has the effeCt" of reducing
the number of "holes" in the if envelope, and limits the mute
drive voltage at pin 12 to values insufficient to attenuate the
audio. If high gain is a system. requirement, an externally
derived mute logic voltage is necessary to drive pin S.

The external circuit on pin 12 in.Fig. 9(a) serves to fdter
the output, and provides a variable potential for
mute·threshold adjustment. The 47().ohm resistor in series
with pin 12 reduces the effective Q of the mter capacitor and
prevents the circuit from setting up on noi.e current
transients as the mute circuit belins to function. The voltage
divider, composed of the SOO kilohm potentiometer and 120
kilohm resistor, controls the threshold point. These values

Fig. '4-IFampllfmr/rlBrw:rorsysfBm and.flltH decothIr.

528 ________________________________________________________________

ICAN-6257
455 kHz without the use of external circuitry. The rf·AGe
and mute logic circuits do not develop sufficient de voltage

components are necessary. TIle CA3089E, operating in
conjunction
with
an
inexpensive
operational
transconductance amplifier,4,5 provides means of locking the
tuned circuit to the incoming frequency. Fig. 17 shows the
block diagram of such a system. TIle AFC output voltage
developed acro!:.') the resistor between pins 7 and 10 is
amplified by the op-amp and drives a varactor to maintain
the tuned frequency on the incoming-signal frequency.

distortion at pin 6. This feedback technique results in a very
low distortion modulation. The rf output of the CA3089E at
pin 8 is essentially a square wave, and is fed to a
tuned·amplifier stage to buffer the signal and restore the
sine-wave·shaped rf output signal.

Acknowlodgments
The author thanks Jack Cr':lft for his aid and suggestions in
many discussions and Frank Curley for his aid in circuit
construction and collection of data.

BibUopphy

Fig. 17- Detector f",quency·stabiliziJtion circuit.

Fig. 15-Su9IJI!sted PC-board pattern and parts layout for the circuit
of Fig. 14.

to perform their functions, and the mcter output signallosc5
its logarithmic characteristic and exhibits peaks and valleys as
input signal is increased. Operation of the ff-AGe and mutl'
logic circuits may be enhanced by the addition of a dc
amplifier and inverter to each circuit. A simple example using
a CA3096E IC transistor array is shown in Fig. 16. 3
The CA3D89E may be used effectively in narrow·band
communication receivers. In double-conversion receivers,
some of the functions of the CA3089E are negated at a
455-kHz intermediate frequency. However, if a ID.7-MHz:
intermediate freQuency is used. all of the auxiliarv features

The CA3D89E may also be used as the core of an
ultra·linear FM generator; Fig. 18 shows the circuit. The
carrier is generated by the CA3089E with the introduction of
feedback from the output terminal, pin 8. The carrier is
modulated by the varactor connected across the tuned circuit
at the input of the CA3089E. The varactor is driven by the
output of the differential amplifier, AI, using a CA3028
IC.6,7 TIlls differential·amplifier stage is driven at one ofits
input terminals by the audio modulating signal, Negative
feedback of the audio signal is provided by driving the other
differential·amplifier input from the recovered audio output
of the CA3089E at pin 6. The detector circuit uses a
double-tuned transformer to produce audio with very little

1. "Advances in FM Receiver Design," J. Avins, IEEE
Transactions on Broadcast and TV Receivers, Aug.,
1971.
2. "High·Performance FM Receivers Using High·Gain
Integrated·Circuit IF;Amplifiers," T.l. Robe, L. Kaplan
IEEE Transactions on Broadcast and TV Receivers.
Sept. 1966.
3. RCA Oat. Bulletin, File No. 595: CA3096 NPN/PNP
Transistor Array IC.
4. RCA Data Bulletin, File No. 475: CA3080 Operational
Transconductance Amplifier.
5. "Applications of the CA3080 and CA3000A
High·Performance
Operational-Transconductance
Amplifiers," H.A. Wittlinger, RCA Application Note
1CAN·6668.
6. RCA Data Bulletin, File No. 382: CA3028A,
Differential/Cascode Amplifiers.
7. "Application of the RCA CA3028A and CA3028B
Integrated Circuit RF Amplifiers in the HF and VHF
Ranges," RCA Application Note ICAN-5337.

'00
OUTPUT

OOI~
----l1f---+4"
33pF
~ODULATION

IN~

.,'-'
Fig. 16-External mute and rf-AGC drive circuits for the CA3089E
operating at 455 kHz_ External transistors are parts of the
CA3096E n-p-nlp-n-p transistor array.

may be used, but another set of problems is encountered.
The small deviation signals encountered in narrow-band
systems require the use of high·Q circuits in the quadrature
detector, as indicated in Table I. However, variations in
external-component parameters with temperature changes
may cause the tuned frequency of the detector to drift out
of the if pass band. Normally temperature·compensated

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Fig. 7. (a) Developed age bias as a function of signal level at
terminal7; (b) delayed age voltage at terminal 7.

Fig. 8 shows the RCA CA3068 coupled to a tuner that uses
an RCA type 40820 MOSFET in the ,f·amplifie, Slage. AGC
voltages are applied (shown in Fig. 8) to optimize over-all TVreceiver performance, so that, when maximum receiver sensitivity is required (such as during the reteption of weak signals
from the antenna) the tuner will operate at optimum· noise
factor and maximum gain. As the input signal level increases, it
is still desirable to operate the rf stage at optimum signal-tonoise ratio until the signal level is of sufficient magnitUde to
override any tuner noise degradation brought about by the
application of agc. Therefore, the gain-reduction voltage to
the tuner should be delayed until the signal level builds up.
Fig_ 7 (b) shows that this agc is delayed until the ifsignallevel
reaches an 8-millivolt level. Then the tuner·gain-reduction mode
is initiated. After the tuner gain reduction is expended, at
least another lO-dB gain reduction is still available in the
cascode portion of the if amplifier.
.
MOSFET
RF AMPLIFIER

, .. 08201

TRAP"']!

1___

!:!0"~_

Fig. 6. Schematic diagram of a typical tuner·to· PIX·IF link
circuit.

The second and third PIX·IF amplifier stages provide two
extra stages of gain (approximately 40 dB). The stages present a
very low driving-point impedance to the linear detector, as described earlier. The detected signal then undergoes an additional
12 dB of video amplification. The video output at terminal 19 is
nominally 7 volts (peak-to-peak.). AGe is developed when the
input signal reaches and exceeds the magnitude necessary to
produce this video output level. Fig. 7 (a) shows the developed
agc bias (lerminal-4 voltage) as a function of signal level al terminal6. Fig. 7 (b) shows the delayed age voltage at terminal 7
(for application to the tuner) with RI adjusted so that this
delay-bias is generated whenever the input signal at terminal 6
exceeds 8 millivolts.

".!!MH!

2

DELAYED-AGC

~~~?ER

OUTPUT

DELAY
AGe

Fig_ 8. Block diagram of a color if system_

As shown in Fig. 2, the agc system is, for the most part,
self-contained. An optimized agc response characteristic can be
achieved by useofa high·quality tantalum IO·microfarad capac-

ICAN-6303
itor connected between terminal 4 and ground. An RC decoupling network smooths the age ripple associated with the
charge and discharge of the I O·microfarad capacitor at the hori·
zontal-oscillator frequency rate. The agc system is normally
keyed from the horizontal-output circuit in the TV system. This
keying pulse should be applied to terminal 3. The magnitude of
the pulse should be sufficient to supply a nominal peak current
value of 0.8 milliampere into terminal 3. The value of the series
resistor Rs associated with terminal 3 may be computed as
follows: During the conduction period (with keyingapplied~ the
constant·voltage components within the integrated circuit
account for:
Vk

=H.2 V

(It is assumed that 1.1 = 0.8 mAl

If the keying·pulse magnitude. Vp' is 15 V.then:
IJ=O.HmA= 15· Vk

R,

(15 H.2IV

Rs

Rs = H.5 kilohms
The sound output is derived from terminal 2 at a level compaliblewith the input requirements of a TV·sound-if-subsystem
IC. such as the RCA CA3065. There is also a de component of
approximately 6.7 volts present at terminal 2. Coupling networks to subsequent circuits must contain a suitable d(·blo(king
capacitor.
Small (hokes located in the sound and video outputs
(terminals 2 and I g) should be self·resonating at the intermediate frequendes to prevent ifleakage into subsequent stages.
The r AJ06X if subsystem has an internal zener reference-diode that permits operation of the subsystem with an
external voltage·regulator pass transistor. A suggested drcuit
arrangement is shown as part of the over·all if schematic
diagram in Fig. 5 (b). The voltage·regulator pass-transistor has a
nominal output voltage of 11.2 volts. Bypassing of the V+
supply with reference to the if subsyslem is important. and the
suggested arrangement shown in the application circuit (Fig. 10)
should be used. Spedfically. terminal 15 should be bypassed to
terminal 17 on the CA3068. Even though terminal 17 is at dc
ground potential, it should not be tied to ground but rather
should be bypassed in the manner shown to avoid mutual impedance coupling within the CA3068.

which (auses more (Urrent to now through the collector (ircuit,
so that a positive (or forward) age potential is generated for the
bipolar transistor in the tUller.

TV RECEIVER PIX-IF CIRCUIT APPLICATIONS
In this section, the application of the CA3068 integrated
circuit in a color and a monochrome TV receiver is described.
The circuits shown were constructed on single-sided copper PC
boards.
As previously noted, because of the high gain encountered in
PIX-IF design. positive feedback must be avoided if the
amplifier is to remain free of spurious oscillation. To this end,
the optimization of printed board layout and component place·
ment is essential. The proper choice of bypassing components
and signal-path layout is necessary to avoid reedback through
ground loops.

IF CIRCUIT FOR COLOR TV RECEIVER
The schematic diagram of an if system for a color-lV receiver is shown in Fig. 10. A parts list and illustrations showing
the PC-board component layout (top View) and the actual
printed circuit (bottom view of board) are shown in AppendiX
A. Since most current color-TV receivers employ automatic·fine-tuning (AFT) systems,an AFT system using the CA3064
has also been included on the same board; Fig. 10 includes the
AFT circuit.
The if·response is determined by the triple·tuned circuit,
which consists of three traps: two preceding the IC and an interstage double-tuner circuit with one trap. In the tripled.tuned
circuit, the two bridge-T traps are used to provide attenuation of
the adjacent-channel picture carrier (frequency 39.75 MHz) and
adjacent-channel sound carrier frequency (47.25 MHz). A

between the tuner and the if "Iage. p•.uasitk re~onan(e and
couplings have been minimized tu maintain a high degree of
attenuation at frequendes remote from the if-re~()l1ance frc·
quen(y.
The interstage double-tuned bandpass ciJ(uit. with a bifilar
T·trap at 41.25 MHz. is similar lu that COlllllllllliy userJ in the
third stage of (ulor-TV receivers. Thcsuund and pi(turc (arriers
are present at the input (termin:.!1 12) to the 4.5 MHl sound·if
dete(tur dJ(uit. Trapping a(tion removes the 41.25 MHz sound
carrier at terminal 13 to prevent a differt!nce-frequency beat of
0.92 MHz with the chroma subcarrier at 42.17 MHz. The picture
carrier and chroma subcarrier entering terminal 13 are amplified, detected, and additionally amplified as detected video
signal. If the sound carrier is not attenuated by the 41.25 MHz
trap, the carrier will be detected as a large 4.5 MHz difference-signal in the video output. A 4.5 MHz trap (T5) is included
to prevent interference of a residual 4.5 MHz intercarrier signal
in the chroma and luminance circuits.
The chroma peaking circuit compensates for the slope of the
video response, as shown in Figs. II (a). II (b) and II (c). The
actual slope and shape of the video response between 3.08 MHz
and 4.08 MHz will vary because of normal component tolerance.
The chroma-peaking coil, L7, has two cores, one to adjust inductance to center the response at 3.58 MHz, and the other to
adjust chroma output level and bandwidth. The latter core
controls circuit Q with little effect on over·all inductance.
Photographs of the detected sweep-response (haracteristics
are shown in Fig. 12. The sweep·response of Fig. 12 ({) shows
the interstage alignment from TP3 (of Fig. 10) to terminal 9 of
the CA3068. The sweep·response curves in Figs.,12 (a) through
12 (e) show hO dB ofagc range from a level of 100 microvolts
(Fig. 12 (e)) to 100 millivolts (Fig. 12 (a)).
The alignment procedure for the color-TV PIX-IF system
using theCA3068. Fig. 10, is given in Appendix A.

MONOCHROME TV
The delayed-agc circuits used in the CA3068 were originally
intended to control a MOSFET in the rf-stage of the TV tuner.
This arrangement permits direct application of the delayed·agc
voltage from the CA3068 to the tuner. In monochrome
receivers, however, it is common practice to employ a bipolar
transistor in the rf-stage of the tuner, and a circuit with a "forward"-agc characteristic is required to control the rf-stage. This
characteristic is easily established by means of an inverter network utilizing a p-n-p transistor, as shown in the circuit of Fig. 9.

Fig. 10_ Schematic diagram of a typical application of the CA3068 to a PIX-IF circuit for a color-TV system.
A template of the printed circuit board used to construct this circuit, a diagram of the position of
all components on the board, a block diagram of the location of major components on the board,
and a circuit parts list are given in Appendix A.

Fig. 9. Block diagram of an if system for a monochrome receiver showing peripheral agc circuit.

As the input signal level increases, the forward-agc delay voltage
is developed at the tuner when the voltage at terminal 7 of the
CA3068 decreases. The agc voltage applied to the rf-stage ofthe
tuner (Fig. 9) is derived from the collector of the p-n-p transistor. As the delay-age voltage is generated at terminal 7 of the
CA3068, the base of the p-n-p inverter is driven into conduction,

common bridge impedance consisting of parallel-connected Ll
and R2 is used. Adjustment ofLI for best null ofthe47.25 MHz.
trap assures the desired 60-dB minimum attenuation.
The triple-tuned circuit provides, at center frequency, a
source resistance to the IC of 800 ohms and a voltage gain of
three from the input to pin 6 of the IC. The first section of the
triple-tuned circuit consists of L2 and C6. Capacitor C6 is in
parallel resonance with coil L2 at 44 MHz. The third section of
the triple·tuned circuit consists of coil LA and capacitor C14.
Coupling and voltage-gain from L2 to lA are provided by the
second section, coil L3 and capacitors CIO, CII, and C12. The
inductive reactance of 1.3 is made 75 times larger than that of L2
to provide a high degree of tuned-circuit isolation for ease of
alignment.
The circuit provides protection against interference resulting
from a strong rf signal which might inadvertently be introduced

IF CIRCUIT FOR MONOCHROME TV RECEIVER
The schematic diagram for a PIX-IF system for a monochrome TV system that employs the CAJ068 is shown in
Fig. 13. A PC-board component-layout diagram (top view), the
actual printed circuit (bottom view of board), and a circuit parts
list are shown in Appendix B. A sound-if system using the
CAJ065 has been included to show the simpliCity with which it
can be used in conjunction with the CAJ068.
The selectivity is provided in two sections, an input
single·tuned circuit with trap, and a double-tuned interstage
circuit. The resistive pad, RI, R2, and R3 of Fig. 13, is used to
terminate the link-cable and isolate cable effects from the high-Q
input circuit. The bridge-T trap-circuit is used to give maximum
attenuation to the adjacent-channel sound carrier. Precision
components (R2, CI, C2) achieve a good null at 47.25 MHz

________________________________________________________________ 533

ICAN-6303
without the need for additional components. The circuit Q is
controlled by Rl t and the resistive input network to yield a
3-dB bandwidth of 3 MHz centered at 44.5 MHz. The
"r'·equivalent circuit is used for interstage coupling to realize a
miniature, precision, double·tuned transformer. The mutual
coupling clement, LS, is an air-core, spring-winding coil which is
actually calibrated by physical dimensions. If necessary, this coil
may be "knifed" to provide a simple and effective coupling
adjustment. The circuit Q's are each set at 21 ,and are controlled
by Rl7 and Rl8,whkh also feed bias for the broadband amplifier and sound channels, respectively. The picture·carrier at
45.75 MHz is set at 50 percent to yield proper reception of the
vestigia! sideband. The color subcarrier at 42.17 MHz is placed
comparatively Iowan the response curve, since the resulting beat
with the 41.25 MHz is placed at greater than 5 percent but less
than 10 pcn:ent to produce etn adequate sound-if intercarrier
signal at 4.5 MHz, and yet maintain low inter modulation.
Typical over-all sensitivity of the if drl'uit is approximately 150
microvolts for full video output.
Interference from the 4S-MHz high-level signals and harmonks is prevented by care in passing and filtering. A J 2·microhenry choke (lA of Fig. 13), self-resonant at the fourth harmonic, is used in the video output lead; the sound output con-

.

'"

AUDI
"O
OUTPUT

~2R6b
1/4W

TUNERc>---l:===t~~===j-----MULTIPLEXED OUTPUT I VIOl" a
1001<510<:/01"
BOTTOM TRACE:TlME EXPANSION OF SWITCHING
BETWEEN INPUTS 2V/01" a
514S ec /OIV

Fig. 7-

Voltage waveforms for circuit of Fig. 6; top trace:
multiplexed output; lower trace: time expansion of
switching between inputs.

Fig. 8-

Voltage waveforms for circuit of Fig. 6; top trace:
output; lower trace: voltage expansion of output;
isolation in excess of 80 dB.

sample-and·hold

Fig. J 0 shows a "sampled" triangular signal. The lower
trace in the photograph is the sampling signal. When this
signal goes negative, the CA3080A is cutoff and the signal is
"held" on the storage capacitor, as shown by the plateaus on
the triangular wave·form, The center trace is a time
expansion of the top·most transition (in the upper trace)
with a time scale of 2 JLSec/div.

TOP TRAC[:SAMPL.EO SIGNAL. IV/PIV
TOf> TRACE: I "/01" I} m0ll-lec/DI" -OUTPUT
BOTTOM TRACE:VOlTAGE EXPANSION OF OUTf>UT
ImV/OIV I} IOO/-UT SUPERIMPOSEO
IV/OII,I e. 2J"sec/ON
TRACE SAMPLING SIGNAL 2011/011" a
2"sec/DN

BOTTO~

Fig. 13- Oscilloscope photo of ·'ramp·voltage"
sampled bV circuit of Fig, 9,

being

____________________________________________________________________ 539

ICAN-6668
In Fig. 14, the trace of Fig. 13 hC of tbe largest possible phase-compensation
capacitor. compatible with the required slew rate. In must
systems the capacitor is dwsen for the maximum allowable
.. tilt" in the storage mode and the resistor is chnsen so that

~1T ~C ~ 2MII/.

corresponding to the first pole in the

amplifier at an output current level of 500 /lAo It is
frequently desirable to optimize the system response by.the
placement of a small variable resistor in series with the
capacitor, as is shown in Figs. 9 and 15. The 120 pF
capacitor shunting the 2 kn resistor improves the amplifier
transient response.

TOP TRACE INPUT AND SAMPLED OUTPUT SUPER·
IMPOSED 100 mV/DIV a 100 n~ DIV
aOTTOM TRACE· SAMPLING SIGNAL 5V/DIV a
100 ns/DIV

Fig. 16- Oscilloscope photo for circuit of Fig. 15 operating
in sampling mode.

540

i~

-

'.0

.
g

_..
0'

,-t

,~~

1--1>" ~~

~

I:z"

.'

~tz

S

17 .;>& ,

I"-

oo~

0m

A

0.001

,

Fig_ 19- Amplitude modulator circuit using the OTA.

There are two terms in the modulation equation: the first
term represents the fixed carrier input, independent of Vm.
and the second term represents the modulation. which either
adds to or subtracts from the first term. When Vm is equal to
the Y- term. the output is reduced to zero..
In the preceding modulation equations the term

I-

-+

'0

Fig. 15- Schematic diagram of the OTA in a sample·andhold configuration (DTLITTL contra/logic).

Yx

10 - 19.2~)(V-) _ 19.2~~(Vm)(Modulation Equation).

and-hold circuit (Fig. 9).
Fig. 15 shows the basic circuit of Fig. Y implemented
with an RCA 2N4037 p-n-p transistor to minimize capacitive
feedthrough. Fig. 16 shows oscilloscope phutographs taken
with the circuit of Fig. 15 llperating in the sampling mude at
supply-voltage nf ±IS Y. The 9.1 kH resistnr in series with
the p-n-p transistor emitter establishes amplifier·bias·current
(lABel conditions similar to those used ill the circuit of Fig.
9.

W)l

o~
o~t

'0

AMPL IFIER BIAS CUFIRENT- rABC -,..A

Fig. 18- Slew rate as a function of amplifier·bias-current
(I ABC) with phase-compensation capacitance as a
parameter.

(I9.2)(Yx)

¥m

involving the amplifier-bias-current terminal voltage (V ABC)
(see Fig. 4 for Y ABC) was neglected. This term was assumed
to be small be..:ause V ABC is small compared with V- in the
equation. If the amplifier-bias·current terminal is driven by a
current-source (such .as from the collector of a p-n-p
transistor). the effect of V ABC variation is eliminated and
transferred to the involvement of the p-n-p transistor
base·emitter junction characteristics. Fig. 20 shows a method
of driving the amplifier·bias-current terminal to effectively
remove this latter variation. If an n-p-n transistor is added to

Gain Control - Amplitude Modulation
Effective gain control of a signal may be obtained by
controlled variation of the amplifier-bias-current (lABC) in
the OTA because its gm is directly proportional to the
amplifier-bias-current (IABc). For a speCified value of
amplifier-bias-current, the output current (10) is equal to the
product of gm and the input signal magnitude. The output
voltage swing is the product of output current ·(10) and the
load resistance (RV.
Fig. 19 shows the configuration for this form of basic
gain control (a modulation system). The output signal
current (10) is equal to -gm Y x ; the sign of the output signal
is negative because the input signal is applied to the inverting
input terminal of the OTA. The transconductance of the
OT A is controlled by adjustment of the amplifier bias
current, I ABC' In this circuit the level of the unmodulated
carrier output is established by a particular amplifier·bias-

Fig. 20- Amplitude modulator using OTA controlled by
p·n·p transistor.

leAN-666S
'.

the dn.:uit of Fig. 20 as an emitter-follower to drive the p-n-p
transistor, variations due to base-emitter I.:h:Hacteristks are
wnsiderably rCdlh.:ed due to the wlllplement;.uy nature of
the n-p-n base·emitter junctions. MureDver, the temperature
weftidents lIf the two ha~e-ellliller jU!Klions tend to I.:alll.:cl
one another. Fig. 21 shows a configuration llsing olle
Iwnsistor in the RCA type CAJOIHA II-p-n tr:.msistor-nr:.ty as

TOP TRACE.MOOULATION F~[OUENCY INPUT
o.20VQlTS pop 50!-'sec/OIV
CENTER TRACE AJ,jPLlTUOE J,jOOULATE OUTPUT
~OOmV/OIV
SO!-'5ec/DIV
BOTTOM TRACE_EXPANDED OUTPUT TO SHOW

a.

a.

Fig. 24- OTA analog multiplier driving an op·amp that
operates as a current-to-voltage converter.

DEPTH OF MODULATION 20mV/OIV
50",sec/DIV

a.

Fig. 2S shows a schematic diagram of the basic multiplier
with the adjustments set·up to give the multiplier an
accuracy of approximately ±7 percent "full-scale". There are
only three adjustments: I) one is on the output, to

Fig. 21- Amplitude modulator using OrA controlled by
p-n-p and n-p-n transistors.
TOPTRAC[:MODULATION FREQUENCY INPUT
20VOLTS
50"sec/DIV
BOTTOM TRACE-AMPLITUDE MOOULATED OUTPUT
500mV/DIV
~O",u.:/OIV

a.

a.

an input emitter-fullower. with the three remaining transistors or the transistur-array connel.:ted as a I.:urrent·sourl.:e
for the emitter - followers. The 100-k!1 potentiumeter
shown in these s.::hernatil.:s is used to null the effects of
amplifier input offset voltage. This potentiometer is :.Jdjusted
to sel the output voltage symmetril.:ally aboullero. Figs. 22a
and 22b show osdlloscope photographs of the uutput
voltages obtained when the drcuit of Fig. 19 is used as a
modul,Hor for both sinusoidal and triangular modulating
signals. This method of modulation permits a range
exceeding 1000; I in the gain. and thus provides modulation
or the I.:arrier input in excess of 99('{, The photo in Fig. nc
shows the excellent isolation achieved in this modubtor
during the "gated-orr' condition.
Four·Quadrant Multipliers
A single r A3080A is especially suited ror 1n:.JllY
low.frequency. low.power four-quadrant multiplier applications. The basic multiplier circuit of Fig. 23 is particularly
useful for waveform generation, doubly balanced modulation, and other signal processing applications, in portable
equipment, where low-power consumption is essential ,md
accuracy requirements arc moderate. The multiplier configuration is basically an extension of the previously discussed
gain-controlled configuration (Fig. 19).
To obtain a four-quadrant multiplier, the first term of
the modulation equation (which represents the fixed carrier)
must be reduced to zero. This term is reduced to zero by the
placement of a feedback resistor (R) between the output and
the inverting input terminal of the rA3080A, with the value
of the feedback resistor (R) equal to I/g m . Tile output
currellt is 10 = gm (-Yx) because the input is applied to the

Fig. 25- Schematic diagram of analog multiplier using OTA.

TOP TRACE.GATEO OUTPUT IV/DIV AND ~O",Slc/OIV
BOTTOM TRACE· VOLTAGE EXPANSION OF ABOVE
SIG~AL-SHOWING NO RESIDUAL
ImV/OIV AND ~0l-'uc/OIV-AT
LEAST 80 db OF ISOLATION

fq

'IOO~Hl

Fig. 22- a) Oscilloscope photo of amplitude modulator
circuit of Fig. 15 with Rm = 40 kfl., V + = 10 v and
V- = -10 V. Top trace: modulation frequency input
.=:::. 2~ V p-p; center trace: amplitude modulated
outPut 500-mV/div.; lower trace: expanded output
to show depth of modulation, 20 m V/div.; b)
triangular modulation; top trace: modulation frequency input ..::::: 20 V; lower trace: amplitude
modulated output 500 mV/div.; c) square wave
modulation, top trace: gated output 1 V/div.; lower
trace: expanded scale, showing no residual (1
m V/div) and at least 80 dB of isolation at fq = 100
kHz.

inverting terminal or the OTA. The output current due to the

1[:

resistor (R) is
Hence, the two signals cancel when R
l/gm' The current for this configuration is:

=::

10 =·19.2 ~ Vrn. and Vrn =Vy
TIle output signal for these configurations is a "current"
which is best terminated by a short-circuit. This condition
can be satisfied ~y making the load resistance for the
multiplier output very small. Alternatively, the output can be
applied to a current-to-voltage converter showll in Fig. 24.
In Fig. 23, the current "cancellation" in the resistor R is
a direct function of the OTA differential amplifier linearity.
In the following example, the signal excursion is limited to
±IO mV to preserve this linearity. Greater signal-excursions
on the input terminal will result in a significant departure
from linear operation (which may be entirely satisfactory in
many applications).

Fig. 23- Basic four quadrant analog mu/tiplier using an
OTA.

compensate for slight variations in the current·transfer ratio
of the current-mirrors (which would otherwise result in a
symmetrical output about some current level other than
lero): 2) the adjustment of the 2o-kn potentiometer
establishes the gm of the system equal to the value of the
fixed resistor shunting the system when the V-input is zero;
3) compensates for error due to input offset voltage.
Procedure for adjustment of the circuit:
1. a) Set the I Mil output-current balancing poten.
tinmeter to the center of its range
b) Ground the X- and Y- inputs
c) Adjust the 100 k!2 potentiometer until a zero-Y
reading is llbtained at the output.
..,

a) Ground the V-input and apply a signal to the Xinput through a low source-impedance generator.
(It is essential that a low impedance source be
used: this minimizes any change in the gm
balance or zero·point due to the SO-J.lA Y-input
bias current),
b) Adjust the 20-kfl. potentiometer in series with
V-input until a reading of zero-V is obtained at
the output. This adjustment establishes the gm of
the CAJ080A at the proper level to cancel the
output signal. The output current is diverted
through the S 1O-k!1 resistor.
3, a) Ground the X-input and apply a signal to the
Y-input through a low source-impedance generator.
b) Adjust the l-MQ resistor for an output voltage of
zero·V.
There will be some interaclion among the adjustments and
the procedure should be repeated to optimize the circuit
performance.
Fig. 26 shows the schematic of an analog multiplier
circuit with a 2N4037 p-n-p transistor replacing the V-input
"current" resistor, The advantage of this system is the higher
input resistance resulting from the current-gain of the p-n·p
transistor. The addition of another emitter-follower preceding the p-n-p transistor (shown in Fig. 21) will further
increase the current gain while markedly reducing-the effect
of the Ybe temperature·dependent characteristic and the
offset voltage of the two base-emitter junctions_

541

ICAN-66SS
DECODER

•• v

500kfl

Fig.

26~

Schematic diagram of analog multiplier using OTA
controlled bV a p-n-p transistor.

S2kn
lapF

51pF

>------11f---+--'VV'v-4
FRON
Q OR Q
10,l'-S ONE-SHOT

Fig. 28- Two-channel multiplexer and decoder using

orAs.

SOOmV/DIII ANO 200I',eclOlv
TRIANGU\fl INPUT 700 Hz

TO Vy

INPUT 511PP

CARRIER INPl.JT

TO

INPUT 135VPP

30kHz

\Ix

Figs. 27a and 27b show oscilloscope photographs of the
output signals delivered by the circuit of Fig. 26 which is
connected as a suppressed-carrier generator. Figs. 27c and
27d contain photos. of the outputs. obtained in signal
"squaring" circuits., i.e. "squaring" sine-wave and triangularwave inputs.
If ±15-V power supplies are used (shown in Fig. 26),
both inputs can accept ±IO-V input signals. Adjustment of
this multiplier Cifcuit is similar to that already described
above.

500mV/DIV

AND ?OO/"ec/OIV

MODULATING fREQUENCY 700 Hz TO \ly INPUT 511PP
CARRIER INPUT
21 kHl TO IIX INPUT 135VPP

TOP TRACE·INPUT .TO X A'-IO Y 2'11/0111 AND

ImsecIOIV-2DOHz
BOTTOM TRACE· OUTPUT 50DmV!O .....
Imsec!OIV -400t1.

A~JD

voltage gain equal to the (gm) eRo) product of the CA3080.
which is typically 142.000 (103dB). The output voltage and
current-swing of the operational amplifier formed by this
configuration (Fig. 9) are limited by the 3NI38 MOS/FET
perfmmance and its soun:c-tcrminal load. In the positive
direction. the MOS/FET may be driven into saturation; the
source-load resistancc and the MOS/FET cha~acteristics
becomc the factors limiting the output-voltage swing in the
negative directioll. The available negative-going load current
may be kept constant by the rcturn of the source-terminal to

The accuracy and stability of these multipliers are a
dircct fum:tion of the power supply-voltage stability because
the Y-input is referred to the negative supply-voltage.
Tracking of the positive and negative supply is also important
because the balance adjustments. for both the offset voltage
and output current arc also referenced to these supplies.
Other forms of four-quadrant multipliers using operational Inlllsconductance -{6:}+-9
CARRY OUT

"10"

.....
........

BATTERY

3-71/2
UNITS

Fig. 6- Photo of circuit·board layout.

Fig. 5- Counter-latch· rimer-control circuir schema ric.

______________________________________________________________ 555

Abstracts of Other Application Notes
AN-3193 . . . . . . . . . . . . . . . .. 9 pages
Application Considerations for the RCA-3N12B
VHF MOS Field-Effect Transistor
This Note describes applications and vhf
circuit considerations for a high-frequency nchannel MOS field-effect transistor, the RCA
3N 128. Biasing requirements and basic circuit
configurations are discussed, and selection of
the optimum operating point and methods of
automatic gain control are explained. The crossmodulation and intermodulation sistortion
characteristics of the 3N128 MOS transistor are
compared to those of bipolar transistors, and
procedures are given for the design of a practical
vhf amplifier that uses the 3N 128.
AN-3341 . . . . . . . . . . . . . . . .. 3 pages
VHF Mixer Design Using the RCA·3N12B MOS
Transistor
The 3Nl28 is a vhf MOS field-effect transistor suitable for use throughout the vhf band
(30 to 300 MHz) as an amplifier, mixer, or
oscillator. This Note discusses some of the design criteria pertinent to the construction of
MOS mixers, and presents an example of a
complete vhf MOS converter.
AN- 345 2 . . . . . . . . . . . . . . . .. 7 pages
Chopper Circuits Using RCA MOS Field-Effect
Transistors
Although electromechanical relays have long
been used to convert low-level dc signals into
ac signals or for multiplex purposes, relays are
seriously limited with respect to life, speed,
and size. Conventional (bipolar) transistors
overcome the inherent limitations of relays,
but introduce new problems of offset voltage
and leakage currents. This Note describes the
use of MOS field-effect transistors in solidstate chopper and multiplex designs that have
the long life, fast speed, and small size of
bipolar-transistor choppers, but that eliminate
their inherent offset-voltage and leakage-current
problems.
AN-3453 . . . . . . . . . . . . . . . . , 6 pages
An FM Tuner Using an RCA-404GB MOSTransistor RF Amplifier
This Note describes an FM tuner that incorporates an MOS field-effect transistor as the
rf amplifier, and shows how the MOS transistor
is instrumental in minimizing the spurious
responses normally found in FM receivers.
AN-3535 . . . . . . . . . . . . . . . .. 6 pages
An FM Tuner Using Single-Gate MOS FieldEffect Transistors as RF Amplifier and Mixer
Selection of the transistors for use in FMtuner stages involves consideration of such
device characteristics as spurious response, dynamic range, noise immunity, gain, and feedthrough capacitance. MOS fieldeffect transistors
are especially suitable for use in FM rf-amplifier
and' mixer stages because of their inherent
superiority for spurious-response rejection and
signal-handling capability. This Note describes
an FM tuner that uses an RCA-40468 MOS
transistor as the rf amplifier and an RCA-40559
MOS transistor as the mixer.
AN-4018 . . . . . . . . . . . . . . . "
5 pages
Design of Gate-Protected MOS Field-Effect
Transistors
MOS
(metal-oxide-semiconductor) fieldeffect transistors are in demand for rf-amplifier
applications because their transfer characteristics make possible significantly better performance than that experienced with other solidstate devices. Unless equipped with gate protection, however, MOS' transistors require careful handling to prevent static discharges from
rupturing the dielectric material that separates
the gate from the channel. This Note describes
the design of dual-gate MOS field-effect tran-

556

sistors that use a built-in signal-limiting diode
structure to provide an effective short circuit
to static discharge and limit high potential
buildup across the gate insulation.
AN-4125 . . . . . . . . . . . . . . . .. 7 pages
MOSIFET Biasing Techniques
Field-effect transistors are applied in rf
amplifiers and mixers, if and audio amplifiers,
electrometer and memory circuits, attenuators,
and switching circuits. The dual-gate MOS/FET
appears to be particularly useful in rf stages
because of low feedback capacitance, high
transconductance, and superior cross modulation with au tomatic-gain-con trol capability. The
rules for biasing FEY's vary slightly depending
on type. However, most possibilities are covered in this Note through examination of the
biasing of a single-gate, a junction-gate, and a
dual-gate transistor. Substrate biasing and biasing to compensate for temperature variations
are also discussed.
AN-4590 . . . . . . . . . . . . . . . . . 16 pages
Using MOS/FET Integrated Circuits in Linear
Circuit Applications
.
A brief review of MOS/FET IC device
theory is given, and some linear circuit applications are surveyed. Theory discussed includes
gate protection and electrical requirements.
Applications include choppers, attenuators,
constant-current sources, general-purpose amplifier circuits, and rf amplifiers, oscillators, and
mixers.
ICAN-40n
8 pages
Applications of the RCA·CA304B Integrated·
Circuit Amplifier Array
The RCA-CA3048 integrated circuit, an array
of four identical amplifiers, each with independent inputs and outputs, all on a single monollthic silicon chip, has an operating and storage
temperature range of - 25 0 C to +85 0 C. Each
amplifier in the low-noise array has a typical
open-loop gain of 58 dB and input impedance
of 90,000 ohms. The gain-frequency response.
stability, output swing versus supply voltage,
and noise of the device are discussed. Circuit
applications include Hartley and Colpitts Oscillators. astable muitivibrators. a 4-channellinear
mixer. a driver for a 600-ohm balanced line.
and a gain-con trolled amplifier.
ICAN-50 15
.
., .
. 15 pages
Application of the RCA-CA300B and CA3010
Integrated-Circuit Operational Amplifiers
This Note describes the circuit arrangement.
lists the performance characteristics. explains
the major design considcra tions. and disl'llSSCS
typical applications of the (' A3008 and CA 30 I 0
operational amplifiers. These amplifiers arc silicon monolithic integrated cin.:uits designed to
operate from two symmctricallow- or medium-

level dc power supplies (at supply voltages in
the range from ±3 volts to ±6 volts).

leAN-5030
11 pages
Application of the RCA·CA3000 Integrated·
Circuit DC Amplifier
This Note describes the RCA-(,A3000 dc
amplifier, a stabilized and compensated differential amplifier that has push-pull outputs, highimpedance (O.I-megohm) inpu ts, and gain of
approximately 30 dB at frequencies up to one
MHz. Its useful frequency response can be increased to several tens of megahertz by the use
of external resistors or coils. The CA3000 can
be used as a signal switch (with pedestal), a
squelchable audio amplifier (with suppressed
switching transient), a modulator, a mixer or a
product detector. When suitable external com·
ponents are added, it can also be used as an
oscillator. a one-shot multivibrator. or a trigger

with controllable hysteresis.
ICAN-5036 . . . . . . . . . . . . . . 9 pages
Application of the RCA·CA3002 IntegratedCircuit IF Amplifier
The RCA-CA3002 integrated-circuit if amplifier described in this Note is a balanced differential amplifier that can be used with either a
single-ended or a push-pull input and can provide either a direct-coupled or a capacitancecoupled single-ended output. Its applications
include RC-coupled if amplifiers that use the
internal silicon output-coupling capacitor, video
amplifiers that use an ex ternal coupling capacitor, envelope detectors, product detectors,
and various trigger circuits.

ICAN-5037
. . . . . . .
.. 4 pages
Application of the RCA-CA3007 IntegratedCircuit Audio Amplifier
This Application Note describes the R(, A(,A3007 audio driver, a balanced differential
configuration with either a single-cnded or a

differential input and two push-pull emitterfollower ou tpu ts. The circuit features ail-monolithic silicon epitaxial construction. and is
intended for usc as a direct-coupled driver in a

class B audio amplifier which exhibits both
gain and operating-point stability over the tcm-

perature range from --55 to 125 0 ('.
1(' AN-5038
8 pages
Application of the RCA·CA3001 Integrated·
Circuit Video Amplifier
The ('A 300 I silicon monolithic in tegra ted
circuit is designed fur lise in intermcdiakfrequency or video amplifiers :.It frequencies up

to 20 Mllz and in Schmitt-trigger applicaiions.
This integrated circuit can be gated. and gain

control can be applied. Thc CA3001 incorporates all-monolithic silicon epitaxial construction
designed for operation at ambient temperatures

from

55

to

I 25 0 C, balanced differential·

amplifier configuf4Ition with low-impedance
double-ended inpLl~,and a built-in temperaturecompens
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