1986_Sharp_MOS_Semiconductor_Data_Book 1986 Sharp MOS Semiconductor Data Book
User Manual: 1986_Sharp_MOS_Semiconductor_Data_Book
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SHARP
1986
SEMICONDUCTOR DATA BOOK
SEMICONDUCTOR DATA BOOK
(MOS Edition)
General Information
11 ~
4-Bit 1-Chip Microcomputers ~
8-Bit 1-Chip Microcomputers
[!
8-Bit Microprocessor and Peripheral LSls ~
16-Bit Microprocessor and Peripheral LSls ~
Peripheral LSls for Microcomputers ~
[ZJ
Memories [!
Support Tools for Microcomputers
LSls for Telephone
~
MOS ICs/LSls
~
Preface
In recent years, the seemingly unlimited
progress seen in integrated circuits technology
has brought about phenomenal growth in electronic products for consumer and industrial
use. As electronics continues to expand -in the
future, we will direct our efforts at carefully
researching trends and supplying our customers with products that meet their needs and
contribute to the betterment of their way of
life.
We have now completed the "Sharp Semiconductor Data Book - - MOS Edition", which
we present to you here how.
This data book lists the microcomputers,
memories and MOS LSIs produced and sold by
Sharp, which have a wide range of applicability. We hope you will find this data book useful
and will contact Sharp if you have any questions.
The information contained in the databook isintended to be a general product description. Sharp
reserves the right to make change in specifications
at any time and without notice.
Sharp does not assume any responsibility for use
of any circuitry described; no circuit patent
licenses are implied.
CONTENTS·
1. General Information ................................................. ;. 1
Products Lineup ...........................•... ; .................... 2
Package Outline ....................................................
12
Quality Assurance ................................................. 25
2. 4-Bit I-Chip Microcomputers ..................................... 35
3. 8-Bit I-Chip Microcomputers .................................... 165
4. 8-Bit Microprocessor and Peripheral LSIs ........ · .......... ·209
5. I6-Bit Microprocessor and Peripheral LSIs ................... 313
6. Peripheral LSIs for Microcomputers ........ · .................... 459
7. Support Tools for Microcomputers .... · ........ · .. · ............ ·561
8. Memories .............................................................. 581
9. LSIs· for Telephone .................................................. 731
10. MOS ICs/LSIs ......................................................... 795
General Information
Products Lineup
.--.-...r.-..-.--.-..-.-..-..-..-..--.-..-..-..-..-..-...r
. .
.
Products Lineup
•
4-Bit 1-Chip Microcomputer
Model
Process
Cycle
ime. (f' s
Supply
voltage
(V)
ClnTent
colEUlllPlion InstrucTYP.(mA) lions
[operating]
ROM
(bit)
RAM
(bit)
Sub·
routine Package
nesting
SM-3A
10
-15
12
57
2268X8
128X4
2
60QFP
SM-100
SM-105
SM-ll0
SM-115
SM-111
SM-116
10
10
10
10
10
10
-9
-9
-9
-9
-9
-9
10
10
13
13
13
13
58
58
90
90
90
90
1134X8
1134X8
2032X9
2032.X9
4064X9
4064X9
64X4
64X4
128X4
128X4
192X4
192X4
2
2
6
6
6
6
28DIP
28DIP
60QFP
60QFP
60QFP
60QFP
SM-114
10
-9'
20
90
4064X9
192X4
6
60QFP
SM-120
10
-9
20
54
1536X8
64X4
2
44QFP
10
-5
32
100
3072X9 128X4t16
3
60QFP
SM-4A
SM-5A
SM-5L
SM-500
SM-510
6)1
61'
61
61
61
-3
-3
-3
-2
-3
0.05
0.05
0.05
0.02
0.06
54
51
51
52
49
2268X8
1827X8
1827X8
1197X8
2772X8
96X4
65X4
65X4
40X4
128X4
1
1
1
1
2
60QFP
60QFP
60QFP
48QFP
60QFP
SM-511
61
-3
0.04
55
4032X8
128X4
2
60QFP
SM-520
11
-5
1.5
93
3072X10 160X4+ l6X2
4
64DIP
SM-525
11
-5
0.6
93
3072X10 160X4+ 16X2
4
64DIP
SM-530
91.6
-1.5
0.012
49
2016X8
88X4
1
80QFP
SM-531
91.6
-1.5
0.01
45
1260X8
52X4
1
60QEP
16
-4.5
0.23
57
2016X8
128X4
60QFP
SM-550
1.6
3-5
1
94
1024X8
80X4
SM-555
3.3
3-5
1
94
1024X8
80X4
SM-551
1.6
3-5
1
94
2048X8
128X4
SM-556
3.3
3-5
1
94
2048X8
128X4
2
using
RAM
area
using
RAM
area
using
RAM
area
using
RAM
area
SM-200
SM-540
2
PMOS
NMOS
CMOS
Remarks
External RAM
expandable
8-bit A/D conversion
8-bit AID conversion
8-bit AID conversion
8-bit AID conversion
8-bit AID conversion
Remote control
signal receiver
External ROM
External ROM/REM
Automatic
display circuit
External RAM
Melody generator
circuit
External RAM
Automatic
display circuit
External RAM
Automatic
display circuit
Clock counter circuit
Melody generator
circuit
Clock counter circuit
Melody generator
circuit
Dot matrix
Page
36
40
40
44
44
49
49
54
59
64
69
74
79
84
89
93
98
103
108
113
118
48QFP
8-bit serial
110 function
123
48QFP
8·bit serial
I/O function
123
60QFP
8-bit serial
110 function
128
60QFP
8· bit serial
110 function
128
Products Lineup
.'-'--------------------------(Continued)
SM-552
L6
3-5
1
94
SM-557
3_3
3-5
1
94
SM-5E3
L6
3-5
1
97
SM-563
6_6
3-5
0-4
93
SM-572
2
3-5
1-5
93
using
RAM
area
using
4096X8 256X4 RAM
area
using
4096X8 256X4 RAM
area
using
4096X8 l28X4t32X4 RAM
area
2032X9 128X4
6
SM-578
2
3-5
1-5
94
4064X9
192X4
6
SM-579
2
3-5
1-5
94
6096X9
256X4
6
SM-590
SM-591
2
2
3-5
3-5
0_5
0_5
41
41
508X8
1016X8
32X4
56X4
4
4
CMOS
•
256X4
60QFP
8-bit serial
I/O function
133
60QFP
8-bit serial
I/O function
133
80QFP
8-bit serial
I/O function
138
64QFP
8-bit serial
I/O function
139
64QFP
64DIP
64QFP
64DIP
64QFP
20DIP
20DIP
8-bit AID conversion
8-bit AID conversion
8-bit Serial 110 function
8-bit AID conversion
8-bit serial 110 function
16DIP, 18DIP
16DIP, 18DIP
144
150
151
152
156
8-Bit 1-Chip Microcomputer
Model
LH0801
LH0802
LH0803
LH0811
LH0812
LH0813
LH0881
•
4096X8
Cycle time
MIN- (JLs)
1-5
1-5
1-5
1-5
1-5
1-5
1-5
Supply
voltage
(V)
5±5%
5±5%
5±5%
5+5%
5±5%
5±5%
5±5%
Current
consumption
MAX_(mA)
180
180
180
180
180
180
180
I/O
pins
ROM
(bit)
RAM
(bit)
Package
Remarks
Page
32
32
32
32
32
32
24
2,048X8
4,096X8
-
144X8
144X8
144X8
144X8
144X8
144X8
144X8
40DIP
64DIP
40PBP
40DIP
64DIP
40PBP
40DIP
Z8601MCU
Z8602MPD
Z8603MPE
Z8611MCU
Z8612MPD
Z8613MPE
Z8681MCU
166
180
182
184
186
189
191
I/O
pins
ROM
(bit)
RAM
(bit)
Package
Remarks
Page
8-Bit CMOS 1-Chip Microcomputer
Cycle time
MIN- (JLs)
Supply
voltage
(V)
SM-803
2.2
5±10%
32
4,096X8
144X8
SM-812
1
3-5
48
2,048X8
128X8
SM-813
1
3-5
48
4,096X8
192X8
LU810V1
1
3-5
48
Model
Current
consumption
MAX.(mA)
-
128X8
40DIP
44QFP
64DIP
64QFP
64QFP
64DIP
64QFP
64DIP
-
195
-
198
-
201
-
204
--------------SHARP -..-.---------.-.
3
.....,----------...
.~
ProduotsLineup'
.......................,......~
-~--,.-
•
a-Bit Microprocessor and Peripheral LSls
Function
MOdel
Process
Supply
voltage
(V)
LH0080
LH0080A
LH0080B
Parallel
LH0081
input/output
LH0081A
controller
LH0081B
t80082
Counter / Timer
.L80082A
controller
L80082B
L80083
DMA controller
LH0083A
L80084
LH0084A
LH0084B
LH0085
Serial input/output
LH0085A
controller
LH0085B
L80086
LH0086A
LH0086B
Floppy disk
LH0110
controller
LH0110A
LH5080
CPU
LH5080L
LH5080LM.
Parallel
LH5081
input/output
LH5081L
.controller
LH5081LM
LH5082
Counter /Timer
LH5082L
controller
LH5082LM
CPU
Current
consumption
MAX.(mA)
150
200
200
' NMOS
5±5%
NMOS
5±5%
100
NMOS
5±5%
120
NMOS
5±5%
150
200
100
NMOS
5±5%
100
100
NMOS
CMOS
CMOS
CMOS
5±5%
5±10%
5±10%
5±10%
.170
180
10(TYP.}
2(TYP.)
2.5(TYP.)
Clock
fequency
(MHz)
2.5
4
6
2.5
4
6
2.5
4
6
2.5
4
2.5
4
6
2.5
4
6
2.5
4
6
2.5
4
2.5
2.5
2.5
2.5
- 2.5
2.5
2.5
2.5
2.5
Package
40DIP
40DIP
28DIP
40DIP
40DIP
40DIP
40DIP
.
Remarks
Page
Z80 CPU
Z80A CPU
Z80B CPU
Z80 PIO
Z80A PIO
Z80B PIO
Z80 CTC
Z80A CTC
Z80B CTC
Z80 DMA
Z80A DMA
Z80 SIO/O
Z80A SIO/O
Z80B SIO/O
Z80 SIO/1
Z80A SIO/1
Z80B 510/1
Z80SI012
Z80A SIO/2
Z80B 510/2
210
210
210
235
235
235
245
245
245
255
255
270
270
270
270
270
270
270
270
270
279
279
296
296
296
302
302
302
307
307
307
~
40DIP
~
~
40DIP
~
44QFP
40DIP
-
44QFP
-
28DIP
-
44QFP
-
-~~-'----SI-iARP'---'-'-'----------
4
------------------------Products Lineup
•
16-Slt Microprocessor and Peripheral LSls
Function
Model
Process
Supply
voltage
(V)
CPU
Memory
control unit
Serial communication
controller
CounterITimer parallel
input/ output unit
FIFO input/output
interface unit
FIFO buffer unit and
Z-FIFO expander
Serial parallel
combination controller
GPIB controller
Multitask support
processor
Universal
peripheral
controller
LH8001
LH8001A
LH8002
LH8002A
LH8010
LH8010A
LH8030
LH8030A
LH8036
LH8036A
LH8038
LH8038A
LH8060
LH8071
LH8072
LH8073
LH8075
LH8090
LH809QA
LH8091
LH8091A
LH8092
LH8092A
LH8093
LH8093A
LH8094
LH8094A
Current
consumption
MAX.(mA)
320
NMOS
5±5%
320
NMOS
5±5%
300
NMOS
5±5%
250
NMOS
5±5%
200
NMOS
5±5%
200
NMOS
5±5%
200
Clock
fequency
(MHz)
4
6
4
6
4
6
4
6
4
6
4
6
4
Package
48DIP
40DIP
48DIP
40DIP
40DIP
40DIP
28DIP
Remarks
Z8001 CPU
Z8001A CPU
Z8002 CPU
Z8002A CPU
Z8010 MMU
Z8010A MMU
Z8030 SCC
Z8030A SCC
Z8036 CIO
Z8036A CIO
Z8038 FlO
Z8038A FlO
314
,314
314
314
332
332
342
342
356
356
377
377
Z8060 FIFO
396
402
413
421
423
NMOS
5±5%
250
4
40DIP
NMOS
5±5%
250
4
40DIP
----
NMOS
5±5%
250
4
40DIP
--
NMOS
5±5%
250
NMOS
5±5%
250
250
250
NMOS
5±5%
250
4
6
4
6
4
6
4
6
4
6
40DIP
64DIP
64DIP
40PBP
40PBP
Page
Z8090 UPC
Z8090A UPC
Z8091 ~:~f~~pment
Z8091A ~:~~~~pment
Z8092 ~:~i~~pment
Z8092A ~:~fi~pment
Z8093 ~~~t~~k
Z8093A ~::'JI:."~~k
Z8094 ~~~ff~~k
Z8094A ~~Ou'l':.:~k
434
434
451
451
453
453
455
455
457
457
5
Products Lineup
__
~~~""
•
__''_'':'''''''''''
~-II!IIf:_""""""""''''''
Peripheral LSls for Microcomputers
Function
Model
Process
Supply
voltage
(V)
Serial communication
controller
CounterITimer parallel
input/output unit
Serial parallel
combination controller
GPIB controller
Multitask support
processor
Universal
peripheral
controller
Key-encoder and
data transmitter receiver
*1
*2
LH8530
LH8530A
LH8536
LH8536A
LH8571
LH8572
LH8573
LH8575
LH8590
LH8590A
LH8591
LH8591A
LH8592
LH8592A
LH8593
LH8593A
LH8594
LH8594A
LH8661
,Current
Clock
consumption ,fequency
MAX.(mA)
(MHz)
4
250
6
4
200
6
250
4
4
250
250
4
NMOS
5±5%
NMOS
5±5%
NMOS
NMOS
NMOS
5±5%
5±5%
5±5%
NMds
5±5%
250
NMOS
5±5%
250
NMOS
5±5%
250
NMOS
5±5%
250
NMOS
5±5%
250
NMOS
5±5%
250
NMOS
5±5%
180
I
4
4
6
4
6
4
6
4
6
4
6
8
Package
40DIP
40DIP
40DIP
40DIP
40DIP
40DIP
.40DIP
64DIP
64DIP
40PBP
40PBP
40DIP
Remarks
Page
460
28030 SCC
, 28030A SCC 460
28036 CIO
.474
28036A CIO 474
-49,1
-502
-511
--
513
28090 UPC
28090A UPC
28091*1
28091A *1
28092*1
28092A *1
28093*2
28093A *2
28094*2
28094A *2
525
525
542
542
544
544
546
546
548
548
--
550
Development device
Protopack emulator
. ; Microcomputer Development Support System
Model
LH8DH11 0
LH8DH130
LH8DH140
LH8DH312
LH8DH321
LH8DH330
LH8DH340
LH8DH403
LU4DH200
LUXXXH2
Function
Development Support System SM-D-8000 n; SM Series 28, 280, Z8000 development device
Development Support System SM-D-8100; 28, 280, 28000 development device
Development Support System SM-D-8200; 28, 280, 28000 development device
280B In-circuit Emulator, for SM-D-8000 n
Z8 In-circuit Emulator n, Stand-alone type
28000 Evaluation Board, Stand-alone type
28000 In-circuit Emulator SM-E-8100, Stand-alone type
PROM Writer SM-E-8000 n
SM Series Emulator Device SME-20, Stand-alone type
SM Series Evaluation Board
Page
562
564
566
569
571
572
573
575
576
578
~~~----'-'---SHARP ---.-..-.------~---
6
Products Lineup
~~.-..-.~~.-..-..-..-..-.~.-..-..-.~.-.~
•
Mask ROM
Capacih
(bit)
32K
64K
96K
12SK
256K
512K
1M
102M
•
Model
LH2331
LH2331A
LH2332
LH2332A
LH2362B
LH2367
LH5366A
LH5366S
LH5367
LH5396
LH5396A
LH5396S
LH23126
LH53127
LH53129
LH53129A
LH23257
LH53256
LH53257
LH53512
LH531000
LH53012
Series
Process
NMOS
Bit
composition
(bit)
4,096XS
NMOS
S,192XS
CMOS
CMOS
12,2SSXS
NMOS
CMOS
16,3S4XS
NMOS
CMOS
32,76SXS
CMOS
CMOS
65,536XS
131,072 X8
CMOS
103,680X12
Process
Bit
composition
(bit)
Supply
Access
Power
Cycle time
time
voltage consumption Package
MIN.(ns)
MAX.(ns)
(V)
MAX.(mW)
450
450
350
350
5±5%
5S0
24DIP
450
450
350
350
250
250
S40
24DIP
5±5%
250
250
420
2SDIP
2,500
4,000
5±10%
30
6,000
12,000
44QFP
3±0.5V
3.5
450
750
5±5%
60
7,500
6,000
35
4.5±0.5V
44QFP
3,000
4,500
60
1S,000
10
15,000
3±0.4V
250
250
5±1O%
440
2SDIP
44
250
350
5±10%
2SDIP
6,000
7,500
4.5±O.5V
35
44QFP
2,500
3,500
5±1O%
SO
250
250
440
28DIP
44QFP
800
900
5±10%
55
250
250
165
2SDIP
3,000
4,400
5±IV
24S0P
9
2SDIP
SO
5
250
250
5
-.
Remarks
Page
5S2
582
r-s86
r-s86
590
"594
599
'602
605
60S
608
ill
615
rsl8
~
~
630
~
'638
642
646
40DIP
647
EPROM
Capacit)
(bit)
64K
12SK
256K
Model
LH5764j-20
LH5764j-25
LH5764j-30
LH5764j-45
LH57128]-20
LH57128]-25
LH57128]-30
LH57128j-45
LH57256]-20
LH57256]-25
LH57256]-30
LH57256]-45
CMOS
CMOS
CMOS
Access
Cycle time
time
MIN.(ns)
MAX.(ns)
-200
250
S,192XS
300
450
200
-250
16,3S4XS
300
-450
-200
250
32,76SXS
300
-450
Supply
voltage
(V)
Power
consumption Package
MAX.(mW)
5±10%
150
2SDIP
(Ceramic)
150
2SDIP
(Ceramic)
Remarks
Page
6"50
~
~
~
651
5±10%
~
. '651
~
652
5±10%
150
2SDIP
(Ceramic)
'652
rrnrrn-
7
•
.,
1K
2K
4K
16K
Model
LH5101-30
LH5101-45
LH5101
LH5101L3
LH5101S
LH5101W
LH5102
LH5102-8
LH5102W
LH2114L-20
LH5114-4
LH5104-4
LH5116-15
LH5116-20
LH5117-15
LH5117-20
LH5118-15
LH5118-20
r
.
.
-
,Bit
composition
(bit)
Supply
Power
Access
Cycle time
time
voltage
consumption Package
MIN.(ns)
(V)
MAX.(mW)
MAX;(ns)
300
300
140
5±10%
450
450
800
800
250X4
CMOS
5±5%
145
22DIP
650
650
3,000
3,500
3±OAV
45
800
800
5±10%
150
1,200
1,200
5±5%
145
512X4
CMOS
800
900
22DIP
1,200
1,200
150
5±10%
NMOS
200
200
400
1,024X4
5±10%
18DIP
CMOS
450
450
110
CMOS ' 4,096X 1
450
450
18DIP
5±.10%
85
150
150
200
200
150
150
2,048X8
220
24DIP
CMOS
5±10%
200
200
150
150
200
200
frocess
Remarks
118 pin CS
20 pin OE
Page
653
653
658
658
602
666
670
670
675
680
684
688
693
693
118 pin GE, ~
20 pin CEI 698
118 pin CE, 703
20 pin CEI 703
Dynamic RAM
Capacity
'(bit)
Model
LH2164-15
LH2164-20
64K
LH2164A-15
LH2164A-20
, LH2464-10
LH2464-12
LH2464-15
LH2465c10
LH2465-12
LH2465-15
LH21256-10
256K
LH21256-12
LH21256-15
LH21257-10
LH21257-12
LH21257-15
LH21258-10
LH21258-12
LH21258-15
8
.........._ _ _. ._ _
StaticRAM
Capacih
(bit)
•
.
~
~
'
Products ,Lineup
................_ _. ._ _................
Process
NMOS
NMOS
NMOS
Bit
composition
(bit)
Access
Cycle time
time
MIN.(ns)
MAX.(ns)
150
270
200
330
65,536X1
150
260
200
330
100
120
150
65,536X4
100
120
150
100
200
120
230
150
260
100
200
262,144X 1
120
230
150
260
,
100
200
120
230
150
260
Supply
voltage
(\1)
Power
consumption Package
MAX.(mW)
248
16DIP
5±10%
275
5±10%
267.5
5±10%
467.5
440
385
467.5
440
385
467.5
440
385
18DIP
' Remarks
Page
708
708
717
717
726
r-------'-Page mode 726
r-------'-726
726
r-------'-Nibble mode
~
726
728
r-------'-Page mode
728
rns
rmrns
rmc-m-728
16DIP
Nibble mode
728
Byte mode
.............................. ......................... .........................
Products Lineup
~
•
Tone Dialer
LR4087
LR4089
Power Operating Oscillating
Tone
supply current frequency Oscillater
Mute output
output
lvoltage(V) TYP.(mA) (MHz)
CMOS 3.5-10
1
Crystal bipolar output
Complementary
3.58
CMOS 3.0-10
1
3.58
Crystal bipolar output N-channel open drain
LR4091
CMOS
3.0-10
1
3.58
Crystal
bipolar output N-channel open drain
LR4092
CMOS
3.5-10
1
3.58
Crystal
bipolar output
Model
•
•
~
Process
Remarks
Op amplifier
output
Complementary
Package Page
16DIP
16DIP
732
735
18DIP
738
16DIP
741
Pulse Dialer
Model
Process
LR40981A
LR40982
LR40991
LR40992
LR40993
LR40994
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Power Operating Oscillating
Make
supply current frequency Oscillator rate
r-roltage(V) MAX.(mA (kHz)
(%)
2.5-6
0.15
480
Ceramic
33/39
2.5-6
33/39
0.15
480
Ceramic
2.5-6
34/40
0.15
4
CR
34/40
2.5-6
4
CR
0.15
2.5-6
34/40
0.15
4
CR
2.5-6
34/40
0.15
4
CR
Pluse
ratio
(pps)
10
10
10/20
10/20
Pluse
Mute
output output
Positive
Negative
Negative
Negative
10/20 Negative
10120 Negative
Remarks
Negative
Negative
Positive
Negative
Negative Key signal
Negative Key. signal
Package Page
16DIP
16DIP
18DIP
18DIP
18DIP
18DIP
744
748
752
756
760
764
Pulse / Tone Dialer
Model
Process
Power Operating Oscillating
supply current frequency Oscillator
voltage(V) TYP.(mA) (MHz)
Make
rate
(%)
Pluse
Abbrevication
Redical
ratio
memory
function
(pps)
18 digits
18 digit last
.LR480lD
CMOS
2-6
2
3.58
Crystal
40
10/20
LR4802
CMOS
2-6
2
3.58
Crystal
32
10/20
LR4803
CMOS
2-6
2
3.58
Crystal
40
10/20
~
LR4804
CMOS
2-6
2
3.58
Crystal
.40
10120
LR4805
CMOS
2-6
1
3.58
Crystal
32
10120
LR4806B
CMOS
2...,.6
1
3.58
Crystal
33/37 10/20
X9 stations
18 digits
number
18 digit last
X9 stations
18 digits
number
18 digit last
X9 stations number
32 digit last'
---
numger
32 digit last
16 digits
number
32 digit last
X 20 stations
number·
Package Page
18DIP
768
18DIP
773
18DIP
778
20DIP
783
20DIP
788
28DIP
793
---~------SHARP~------~----
9
1
.---.....
.....,.-..........
·Products Lineup
•
..... ...............................
.-~~
.-
MOS Ie / LSI
F'unction
Driver
Clock/
TImer
LCD driver
Vacuum
fluorescent
display driver
10
Model
LH5010
LH5011
kH5010D
LH5011D
LH5012
LH5013
LH5012D
LH5013D
LR3428
LR3429
LR3464
LR3468
Process
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
LR3465
CMOS
LR3441
CMOS
LR3419
CMOS
LR3472
CMOS
LH5008
CMOS
LH5003
CMOS
LH5004
CMOS
LH5821
CMOS
LH5822
CMOS
LH5823
CMOS
LH5826
CMOS
LH5030
LH5031
CMOS
CMOS
LH5035A
CMOS
LH5036A
CMOS
LH5006A
LH5021A
LH5022
LR3691A
LR3692
LI2048
CMOS
CMOS
CMOS
CMOS
CMOS
PMOS
LH1001
PMOS
Features
6-circuit signal non-inversion type, INHIBIT input
6-circuit signal inversion type, INHIBIT input
7-circuit signal non-inve(sion type, INHIBIT input
7-circuit signal iIiversion.type, INHIBIT input
7-circuit signal non-inversion. type
7 -circuit signal inversion type
8-circuit signal ·non-inversion type,
8-circuit signal inversion type
Analog clock, alarm, oscillator: 4.19 MHz crystal
Analog clock, alarm, oscillator: 4.19 MHz crystal
Analog clock, alarm, oscillator : 32kHz crystal
Analog clock, alarm, oscillator: 32kHz crystal
Analog clock, melody generating function oscillator:
32kHz crystal
(Hour, min) LCD display, timecast, alarm, snooze function,
oscillator: 32kHz crystal
(Hour, min) Fluorescent display tube indication,
power failure display, oscillator 50/~0 Hz or 32kHz crystal
(Hour, min) Fluorescent display tube, 6-program-a-week
reservation, oscillator: 32kHz crystal
7-segment and 14-segment ·display, display RAM: 128 bits
5 X 7 -dot matrix display (master), display RAM:
240 bits, character generator: 125 types
5 X 7-dot matrix display (slave), display RAM:
320 bits, character generator: 128 types
Dot matrix display (master), display RAM:
1280 bits, common output: 20 lines, segment output: 44 lines
Dot matrix display (master), display RAM:
1280 bits, common output: 18 lines, segment output: 46 lines
Dot matrix display (master), display RA.M :
1280 bits, common output: 16 lines, segment output: 48 lines
Dot matrix display (slave), display RAM:
1280 bits, segment output: 64 lines
Dot matrix display (common), common output: 80' lines
Dot matrix display (common), common output;. 32 lines
Dot matrix display (segment), display RAM:
3200 bits, segment output: 80 lines
Dot matrix display (segment), display RAM:
3200 bits, segment output: 80 lines
Dot matrix display, common output or segment output: 40 lines
Dot matrix display, common output or segment output: 80 lines
Dot matrix display, common output or segment output: 80 lines
Dot matrix controller, max display capacity: 163,840 dots
Dot matrix controller, max display capacity: 640 X 256 dots
5 X 7-dot matrix display, character generator: 128 types
Grid drive, output voltage (MAX.): -50V,
output current (MAX.): 20mA
Package
16DIP.
16DIP
18DIP
18DIP
16DIP
16DIP
18DIP
18DIP
8DIP
8DIP
8DIP
8DIP
Page
908
·908
911
911
914
914
917
917
920
923
926
929
22DIP
932
48QFP
936
48QFP
94i
48QFP
945
60QFP
838
60QFP
899
60QFP
899
80QFP
879
80QFP
879
80QFP
879
80QFP
884
96QFP
44QFP
892
896
96QFP
889
96QFP
889
60QFP 866
100QFP 870
100QFP 870
60QFP 844
80QFP 853
60QFP 835
36QFP
905
.....---....---....------.......-.------------.....
Products Lineup
~--------•
MOS Ie / LSI (continued)
Function
High
voltage
Model
Process
LZI008AD
DMOS
LZI016AD
DMOS
LZI032AM
DMOS
LZll08AD
DMOS
LZ1116AD
DMOS
LZ1132AM
DMOS
LR3617
LR3727
LR3652
CMOS
CMOS
CMOS
LR3715M
CMOS
LU59001
CMOS
LR3461
CMOS
LR3462
CMOS
LR3681
CMOS
. LZ2020
CMOS
MOS
Audio &
Video
Remote
control
Voice
Synthesizer /
Melody
generator
CCD
Gate array
LZ92 Series
CMOS
Features
8-output, N-channel, output voltage (MAX.): 300V,
output current (TYP.): 35mA
16-output, N-channel, output voltage (MAX.): 250V,
output current (TYP.): 45mA
32-output, N-channel, output voltage (MAX.): 250V,
output current (TYP.): 45mA
8-output, P-channel, output voltage (MAX.): 300V,
output current (TYP.): 20mA
16-output, P-channel, output voltage (MAX.): 300V,
output current (TYP.): 30mA
32-output, P-channel, output voltage (MAX.): 300V,
output current (TYP.): 30mA
Up I down counter with LCD decoder driver
VTR data hack
PLL synthesizer for AM I FM radio
56-channel remote-controlled transmitter,
oscillator: 455 kHz ceramic
56-channel remote-controlled transmitter,
oscillator: 455 kHz ceramic
8-melody generation with accompaniment,
Electromagnetic speaker driver, CR oscillation
8-melody generation, piezo·electric drive, CR oscillation
Speech synthesizer, Waveform coding system,
Built-in 32K-bit data ROM, Base frequency: 4.19MHz
CCD image sensor, dynamic range (TYP.): 54dB,
Transfer efficiency more than 99.996%
Gate array, 300-5000 gates, 2.8ns/gate
Package
Page
18DIP
804
28DIP
807
44QFP
811
18DIP
815
28DIP
818
44QFP
821
48QFP
36QFP
22DIP
964
969
977
36QFP
952
20DIP
957
22DIP
824
18DIP
827
48DIP
831
24DIP
(Ceramic)
799
--
796
11
......
Package Outljoe
~.,
Package Outline (Unit: mm)
8
8DIP
5
14DIP
16DIP
12
16
9
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20
11
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7.62TYP.
..;
22DIP
10.16 TYP .
13
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PackageOuUine
.
......,.--.
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24DIP
CD
®
®
®
®
®
(J)
®
p~.54TYP.
0.5±O.1
Shrink
6.35±O.2
22.0±O.2S
7.62TYP.
3.45±O.2
4.2±O·2
P-i, 778 TYP.
0.46±O.1
Normal
Shrink
13.2±o.25
8.6±O.2
36.0±O·3
25.5±O..25
15.24 TYP: 10. 16 T¥P.
4.25±O.25
3.85±O.2
5.1 ±O.2
4.4±O.2
p-2.54T¥P. P-l, 778TYP.
O.5±O.1
(J)
O.46±O·1
28DIP
30DIP
Normal
13.2±o.2s
31.0±O·3
15.24TYP.
4.25±O·2
5.1±o.2
CD
®
®
®
®
®
Shrink
Normal
13.2±o.25
8.6±O.2
36.0±O.3
27.2±O.25
lS.24 TYP . 10. 16 TYP.
4.25±o.25
3.85±o.2
4.4±O.2
S.l ±O.2
p-2.54 TYP. P-l, 778 TYP.
O.46±O·1
(J) 0.5±O·1
3~ r"l t"J I'i fI t"J t"J ~ r"l r"l t"J t"J J'l r"1 ~6
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Package Outline
~.-..-..-.-..-..-.-..-.-~.-.-.--.-..-.-.
40DIP
21
42DIP
48DIP
15
P~kage. Outline
.
.
. - . - . - . - . - . . . . . , . - -..._ ..._~.-.:..._ _illr.. . . . ....,.IIiiIIIIiiiIif.....
640lP
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33
42.0MAX.
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I
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16
O.25±o.05
\: 15.24TYP ·
~
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~~~"",~~"",~....,....,.--r~....,
8.9 TYP .
40PBP
( Ceramic
Piggyback
40
21
)
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16.0±O"
O.8S±O.2
1.45±O.2
O.ITYP.
-------~---~-~SHARP,-~~-.--------
18
.....----
Package Outline
.-..-..-.~.-..-.~.-.~~~.-.~~~.-.
p-o.8 TYP•
36QFP
36 -0.38±o.1
0.15±o.o5
n7~-------' ~----
~
.,;
++1--E""'a::Il
N
o
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<=>
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............
10.0±O.2
0.85±0.2
1.45±O.2
16.0±O.4
o.rrvp
44QFP
_liE
0.15-{l.tl5
J-.-
-
0.85-°·2
1.45- 0 . 2
16.0,,0.4
. . . - - . - - - - - , . . . . - - $ H A R p . - - - - - - - - - - -..........
19
Paokage, Outline
........--.~...,...,.-. . ..-..-.. . .....r.-...........~......_
48QFP
p-o.75 TYP ,
24
N
o
~
0
+i
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__ +I
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13
16.01: 0 .4
O.I TYP ,
60QFP
0.15 ±0.05
f
N
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~
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1.0±0.2
1.9±0.2 .
20.3±0 .•
20
O.FYP' '
....
.-..-..-.
.......-....................-........-..-..-........ Package Outline
.-..-.
64QFP
64-0.4±O.!
64
1
I
20.0±O.2
\
24.3±o..
.
O.9±O.2
I
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1. 95±o.2
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(21.9)._ _ _ _ _~-~
76QFP
P-O.8 T¥P.
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I
22.0±0.4
O.I±O.!
21
p,i1~kage
Outline
80QFP
O.15±0.01
p-0.8 TYP.
~-----
+----I
1.25±0.2
18.0±0.2
2.4±0.2
O.1't:O.1
22.0±0.4
I"
80QFP
0.15±o.05
1'-0.8 TY I'·
I
20.0±0.2
, 24.3±0.4
0.9±O.,
1.95±0.2
0.1±0.1
_ _ ~~-----~-SHARP~------"--'----"""'-
22
......-..-.......-.................-.................-.......-.
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.-..-..-.
96QFP
p-O.FYP'
O.15±O.05
"II" .
,
I
~---+----,
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I
i
18.0±o.2
22.0±O.'
1.25±o.2
2.4±O.2
O.l±O.!
lOOQFP
23
44PLCC
;>1
6' ,
I,E
40
!" \
29
16.6.tO·2
(17.5)
DIP : Dual-In-Line Package
QFP : Quad Flat Package
SOP: Small-Outline Package
PBP : Piggyback Package
PLCC : Plastic-Leadless-Chip-Carrier
24
28
.....
.-.,.-.,.-.,
..... ..... ..... ..... ..... ..........
.-.,.-.,
.-.,
.-.,
.-.,
.-.,
Quality Assurance
.-.,
Quality Assurance
1.
Quality Assurance System
Sharp develops and manufactures a wide range
of consumer and industrial-use semiconductor products, including ICs and LSIs.
In recent years, the applications of ICs and LSIs
have expanded significantly, into fields where extremely high levels of quality are critical.
In response, Sharp has implemented a total quality assurance system that encompasses the entire
production process from planning to after-sales
service. This system ensures that reliability is a
priority in the planning and manufacturing stages,
and guarantees product quality through rigorous
reliability testing. We will introduce a part of
this system here.
Sharp's quality and reliability assurance activities are based on the following guidelines:
(1) All personnel should participate in quality
assurance by continually cultivating a higher
level of quality awareness.
(2) In the developmental stage of new products,
create designs that consider reliability in every respect.
(3) In addition to quality control in all manufacturing processes, all working environments,
materials, equipment, and measuring devices
should be carefully monitored to ensure quality and reliability from the very beginning of
the process.
(4) Confirm long-term reliability and obtain a
through understanding of practical limits
through reliability testing.
(5) Continually work to improve quality through
application of data from process inspections,
reliability testing, and market surveys.
2.
Quality and Reliability Control in New
Product Development
The development of new products begins with a
thorough understanding of the product specifications and quality that will satisfy the purpose for
which the product is intended and with developmental planning that carefully considers pricing,
quantity and the time of introduction to the market.
In the design stage, reliability is designed into
the product based on test data, process capability,
and field data, and experimental models are
made. These experimental models are referred to
as TS (technical samples), and are evaluated pri-
1 ;;=;:;
=
I--_ _ _ Evaluation of functions
and performance
I--_ _ _ Eva!uation of quality
and mass producibility
f----Evaluation of reliability
1 - - - - - Decision to mass
produce
Fig. 1
New Product Development Steps
marily for their ability to function and their performance.
Next, ES (engineering samples) are made and evaluated to determine whether the functions, performance and quality aimed for in the design stage
can be guaranteed under the existing manufacturing conditions. These ES are also evaluated in
quality and reliability tests to determine whether
their long-term reliability can be guaranteed.
After this, mass producibility is evaluated using
CS (commercial samples) obtained from a trial mass
production, and the decision to mass produce or
not is made. Fig. 1 shows the steps in the development of new products.
3.
Quality and Reliability Control in Mass
Production
(1 ) Quality Control of Materials
The quality and reliability of a product is
affected by its component materials as well as the
manufacturing processes and conditions.
The quality control of purchased component
. materials is ensured by material qualification and
inspection upon receipt.
.-....----~.------SHARP.---------~
25
........,.....,.... ..-.. .....
Q,uality Assurance
.....,.....,.....,
~-
Table 1
Material
Items
....,.....,
...........
.....,.....,.....,.....,
Examples of items considered in material approval
Wafers
Crystal growth method
,Crystal orientation
Doping
Oxygen content
Dislocation density
Diameter
Thickness
Parallelism
Specific resistance
Resins
Composition
Electrical characteristics
Thermal characteristics
Formability
Process characteristics
Reliability evaluation
Reliability characteris
tics
by elements used
Process
Lead frames
Composition
Electrical characteristics
Thermal characteristics
Physical characteristics
Appearance '
Dimensions
Processing a~cl,lracy
Plating characteristics
Process characteristics
.Bonding wire
Purity
Appearance
Dimensions
Strength
Elongation character-istics
Process characteristics
C
Control items
Purchase of material .
Silicon
wafers
Inspection upon receipt
,
Appearance, dimensions,
specific resistance
Eliminate items with incorrect dimensions;
scratches; and crystal defects and assure
resistance values.
Appearance, film thickness
Confirm the absence of pin
holes and assure film thickness.
Check the cleanliness of surfaces.
Oxidation
On line QC
Surface cleanliness
Photolithography
Visual inspection
On line QC
Development, etching
Check the suitability of development and
~tching.
Wire width
Control the wire width.
Electrical. characteristics
Eliminate items with unsuitable electrical
characteristics.
Appearance
Confirm the absence of breakage and
chips.
Appearance, bond strength
Check quality of die bond.
Appearance, tensile strength
Ch.eck position and shape of bond and
assure sufficient tensile strength.
Ion implantation
Chip electrical inspection
Dicing
Breakage screening
Die inspection
Die bonding
Die bonding inspection
Wire bonding
Wire bonding 'inspection
Fig .. 2
Example of process quality control
! '
.-----~-----SHARP,-~-.---.-.-..-.-
26
......-..-.......-.................-............-..-...........
Quality Assurance
.-..-..-.
Table 1 shows examples of material qualification
items. The inspections performed upon receipt of
materials use criteria compiled from the purchase
specifications and approval drawings, and employ
sampling inspection methods that conform with
MIL-STD-105D.
(2) Control of Manufacturing Environment
Environmental conditions in the manufacturing
process - such as temperature, humidity, and dust
- significantly affect the finished quality of semi·
conductor products.
Temperature is especially critical in maintaining
the accuracy of the measurement of electrical characteristics and the accuracy of various devices.
Humidity control is important for the prevention of
moisture penetration into a device and the prevention of static electricity. Temperature and humidity are thus strictly maintained at constant levels.
A dust-free environment is vital in the manufacture of refined semiconductor circuits, as dust can
be the critical determining factor in their quality
and reliability. Thus, the cleanliness of everything from air conditioning equipment to work benches to work clothes and office items is carefully
controlled.
Sharp is also concerned about creating an environment conducive to error-free high-precision
work, and so provides background music and interior colors appropriate for specific tasks.
agement.
We perform a final inspection of all finished products as well as further quality assurance inspections through sampling to fully ensure quality.
Detects found in these inspections are promptly
reported to the design and production sections, and
improvements made' in the processes to upgrade
our uniform quality capabilitieS.
Assembly process
Electrical
characteristics
All items
Appearance
All items
Eiectrical
characteristics,
Judge lot
appearance ' by sampling
-----------,
I
Reliability tests
Sampling
_ _ _ _ _ _ _ _ _ JI
(3) Control of Manufacturing Equipment and
Measuring Devices
Tremendous technological innovation and progress has been made in s~miconductors themselves
and in the processes and equipment by which they
are produced.
T,o achieve even higher levels of product uniformity and quality, Sharp is continually furthering the automation of its processes, strictly managing the maintenance of its manufacturing equipment,
and carefully monitoring the accuracy of all
measuring devices through daily and periodic inspections.
(4)
Process Quality Control and Product inspections
Shipment
Fig. 3
Product inspection system
Fig. 3 Shows the product inspection system.
Fig. 4 Shows an example of process quality
control.
(5)
Reliability Assurance
To guarantee the long·term reliability of our products, we periodically sample products and subject
them to reliability testing such as life tests and environmental tests.
In addition, reliability tests are performed
whenever process changes have been made.
Based on the fundamental concept of ensuring
quality and reliability throughout the manufacturing process, we check at each stage to determine
whether the prescribed characteristics are being
obtained and to prevent defective items from going
on to the next stage. We do this through strict
monitoring, inspection of all items, sampling inspections, and other standardized methods of man---...-..--.----SHARP-.--~-- ........ -
27
Q.uatity~sslM'anc'i.l·
.. ..r....__. .
,..-.r~~
~
.....~......-..r.~. .~..........__~..........
~~
SHARP
Manufacturing
Quality control
Quality assurance
Design '
Business, planning
Investigation
Development plan decision (New production planning
collferen~e)
sample/Engineering, sample
General evaluation (New product debut conference)
Pilot production
production go - ahead conference)
=
.~
""
o
"C
&::
Fig.4 (a) Quality assurance system (SHARP side)
28
_
_
-
.................... .............................. .....................
Customers
1
Design dept.
C
r
Confirmation of\.
Equipment
discussionS'
Parts
1
Quality Assurance
'
Manufacturing dept., Quality
dept. Assurance
Parts dept.
I
End user
Service dept.
)-~------------------~------~o~·----o
)
seleciion
specifications
0
(
Equipment
design
I
Design
sample
\..
r
\
r
\..
Purchase
specifications
}--(
Parts
approval
0
Speeificatjons
approval
)-
0
'\
./
r
\.
0
0
0
Mounting
approval
~
(
(
Sample
planning
)
Design review
• "\
r
../
\
Pilot
production
f
"\
\.
)
l
(
)
General evaluation
+
J'
Quality
\...
evaluation
"\
./
Process quality
1
Assembling
control
"\
J'
\.
r
\.
0
Sample
test
r
\..
Evaluation
/Analysis
Fig. 4
•
l.n s pections
/Aging
Reliability
evaluation
"\
./
)
"\
../
J'
\.
Operation
)
(b) Quality assurance system (User side)
.-.-.--.-----SHARP-----.-.---
29
Qua.lityAssurance
...............
..............r.....AIIiIIIIIir.............,___
~
.....,~...................... - .
Reliability Tests
4.
In addition to determining the extent to which
product reliability can be assured, the objectives of
reliability testing il1clude getting an understanding
of design limitations and the catastrophic failure
mode, and predicting reliability in the field.
The major categories of reliability testing are
durability tests, thermal environmental tests, and
mechanical test~. The standardized test .methods
used are those prescribed by official standards or
Table 2
Type
Durability
tests
Thermal
environmental
tests
Test item
High temperature
storage
High temperature
operation
High temperature,
high humidity
storage
High temperature,
high humidity
operation
Low temperature
storage
Temperature
cycling test
Heat shock test
Temperature and
humidity cycling
test
Solder heat
resistance
Shock test
Variable-frequency
vibration test
Pin strengeth
Mechanical
tests
Air-tightness
Salt spray test
'Solderability
Solvent resistance
30
associations such as the International Electronics
Commission (IEC), and the U. S. Military Specifications (MIL). Sharp standardizes
specifications to
conform with these standards.
Table 2 shows a representative reliability test.
Durability testing of semiconductor products
places the greatest emphasis on high temperature
operation tests. Priority in the testing of plastic
m'olded products is on high temperature, high
humidity storage (operation) tests.
all
Reliability test for semiconductor products
Test condition
T,tg(max.)
Top, (max.)
power supply voltage (max.)
.60t 90% RH
85t 85% RH
Pressure cooker at l20t and
2 atmospheres
60t 90% RH
85t 85% RH
T,tg(min.)
T,tg (max.)-T,tg (min.)
ot -lOOt (liquid)
-lOt to+65·C 90% RH
260t lOs
1,500G, 0.5 ms ±X, ±Y,±Z
20G, 20-2,000 Hz, X, Y, Z
Tensile strength : holds fixed load
for 10 seconds
Bending strength: bend once 90 iu
forward and reverse directions
(Load is determined based on piu
shape and the surface area of pin
section.)
' Test for minute leaks using helium
gas and large leaks using foaming.
Spray 5% salt solution
at Ta=35 t for 24 hours
230 tfor 5 seconds (with flux)
Dip in isopropanol and acetone fo
30 seconds at Ta=25t
Test objectives
Evaluate resistance to high temperatures in
longterm storage.
Evaluate resistance to long, term thermal and
electrical stress.
Evaluate resistance to high temperatures and
high humidity in long-term storage.
'Evaluate resistance to long-term thermal, humid,
ity and electrical stress.
Evaluate resistance to low temperatures in longterm storage.
Evaluate resistance to sudden extreme temperature changes.
Evaluate resistance to sudden extreme temperature changes.
Evaluate resistance to extreme temperature
changes at higgh humidity.
Evaluate resistance to thermal stress during
soldering.
Evaluate structural and mechanical resistance to
strong shocks.
Evaluate resistance to vibration during transport and use.
Evaluate resistance to mechanical stress applied
to pins.
Evaluate hermetic sealing.
Evaluate resistance to corrosion in salt spray
environment.
Evaluate solderability of pins.
Evaluate resistance to pitting.
Quality Assurance
.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.5.
offered and assure the products'long-life service,
please refer to this manual to help in designing systems that make best use of their capabilities.
(1) Maximum Ratings
It is generally known that the failure rate of
semiconductor products increases as the temperature increases. It is necessary, of course, that the
ambient temperature be within the maximum rated
temperature. Further it is desirable from the standpoint of reliability that the ambient temperature be
lowered as much as possible. The voltage, current,
and electric power used are also factors that significantly influence the life of semiconductor products. Voltage or current- that exceeds the rated
level may damaged, the semiconductor product;
even if applied only momentarily and the unit continues to operate properly, excessive voltage or
current will likely increase the failure rate.
Therefore, in actual circuit design, it is important that the semiconductor products used have a
certain degree of allowance with respect to the voltage, current and temperature. conditions under
which they will be used. The greater this allowance, the fewer the failures that will occur.
To keep failures to a minimum, the circuit should
be designed so that under all conditions to absolute
maximum, the ratings are not exceeded even
After-sales Service
If a product malfunctions after shipment, we
have the customer return the product for detailed
analysis. We also obtain complete information concerning conditions of use, frequency of occurrence,
and symptoms.
When the cause has been determined, we report
findings concerning the design, manufacturing process, or method of use to the departments concerned for preventive action against recurrence of
the malfunction. We then submit a report to the
customer.
This process of tracking the performance of our
products in actual use is an extremely effective
way to enhance product reliability. We direct a lot
of energy forwards its full imprementation.
Fig. 5 shows the routes through which accidents
and malfunctions outside of the company are handled, and Fig. 6 shows the procedures used in their
analysis.
6. Handling Precautions
All of the semiconductor products listed in this
data book were manufactured based on exacting
designs and under comprehensive quality control.
However, to take full advantage of the features
I
I
Complaint
: Reply
I
I
I
Report of
complaint
: Investigation
I report
I
I
,-
Quality assurance
I
Request for
corrective action
I
Report I
I
I
I Report
I
Request for
corrective action
I
I
I
I
I
I
Instructions
Manufacturing
Request for
corrective action
Fig. 5
--,
I
I
Design and
technology
Routes through which malfunctions
outside the company, are handled
----------------SHARP
.----.--~-----
31
quality Assurance
,....-r..... -................~-.,.-.-....... - .................................
momentarily and so that the maximum values for
any two' or more items are not achieved simultaneously. In addition, remember that the circuit
functions of semiconductor products are gua'ranteed' within the operating temperature'range (To.,)
of the absolute maximum ratings, but that storage
temperature (Tstg) is the range in a nonoperating
condition.
(2) Transportation and Storage
Semiconductor products are susceptible to high'
temperature and high humidity. Please store them
in a dry place as near to room temperature as
possible.
During shipping and storage, keep semiconductor products in the packaging they were delivered
in to prevent damage due to static electricity. If removed from tlIeir packaging, the terminals must be
shortcircuited with a conductive material or the entire units wrapped in aluminum foil. Also remember that nylon and plastic containers build up electrostatic charges easily and so should not be used
for storage or transportation.
Mechanical vibration and shock should also be
kept to a minimum.
(3) Assembly
When attached ,to printed, circuit boards, semiconductor products are removed from a conductive
container, so electrical equipment, work benches,
and operators must be grounded to protect the products fmm static electricity. It is good to use
grounded metal plating on the surf(ices of work
benches. Grounding metal rings and watch bands is
a convenient method for grounding operators. The
grounding of operators is required to prevent electric shock due to current leaks from electrical
equipment, so it must be performed through a resistance of 1 M
Working attire made of synthetic fabrics should
be avoided in favor of fabrics such as cotton that
do not easily generate static electricity.
Keeping the relative humidity in working areas
around 50% will 'also help to prevent the generation of static electricity.
Current leakage from electrical equipment is not
desirable from the standpoint of safety. All equipment'should therefore be, checked periodically for
, current leakage.
When forming the lead wires of semiconductor
products to be mounted, forceps or a similar tool
n.
32
that will prevent stress, frolll being applied to the
base of the wires should be used.
To prevent the input terminals of semicondudor
products on c()mpleted printed circuit boards from
becoming open during storage or transport, the terminals oilhe circuit board should be'shortcircuited
or the entire circuit board itself should be wrapped
in aluminum foil.
(4) Soldering and Cleaning
When using a soldering iron or solder bath, keep
the temperature below 260t the .time and within
10 seconds. If using a soldering'iron, use one with
no leakage from the soldering tip. An A class
soldering iron with an insulation resistance of less
than 10 Mil is recommended. When using a solder
bath, it should be grounded to prevent its having
an unstable electric potential.
Using a strongly acidic or alkaline flux for
soldering can cause corrosion of the lead wires. A
resin flux is ideal for this type of soldering.
To assure the reliability of a system, removal of
the flux used in soldering, is generally required.
Freon TE, a freon cleaning fluid, or difron solvent
S3-E is recommended for use as the cleaning fluid.
To prevent stress on semiconductor products
and circuit board w'hen using ultrasonic cleaning, a
cleaning method must be used that will shadow the
main unit from the vibrator and keep cleaning time
to less than 30 seconds.
(5) Adjustment and Tests
When the set is to be adjusted and tested upon
completion of the printed circuit board, the printed
circuit board must, be checked to ensure that there
are no solder bridges or cracks ,before the power is
turned on. Also, if the marked rated voltage and
~urrent are to be used, it is wise'to use a current
limiter.
Whenever a printed circuit board is to be removed or mounted on a socket, the power must be
turned off.
When testing with a probe, care must taken to
assure that the probe does to' come in contact with
other signals or the power supply. If the test location has been decided beforehand, it is wise to set
, up a specially designed test pin for testing.
When testing in high· and low temperatures, the
constant temperature bath must be groundeq and
measures taken to protect the set inside the bath
from static electricity.
Quality Assurance
Report
r--""]
'--- ....
Test is applied only to a hermetic sealed package.
Fig. Failure analysis procedure
33
4-Bit 1-Chip Microcomputers
[g
SM-3A
. PMOS 4-Bit 1-Chlp Microcomputer
SM-3A
•
PMOS 4-Bit I-Chip Microcomputer
Description
The SM-3A is a 4-bit single chip PMOS microcomputer with 2,268 bytes of ROM, and 128
words of RAM. It is well suited for low cost systems requiring many I/O control ports.
•
Pin Connections
KEa
KE2
KE,
AD ..
•
1
0
Features
1. PMOS process
2. ROM capacity 2,268 X 8 bits
3. RAM capacity 128 X 4 bits
4. Instructions 57
5. Subroutine nesting 2 levels
6. Input ports 8 bits
7. Output ports 37 bits
8. Input/Output ports 4 bits
9. On-chip clock generator circuit
10. High voltage outputs (-38V) 27 bits
11. Single power supply -15V (TYP.)
12. Instruction cycle lOps
1a. 60-pin quad-flat package
36
P
K~
Top View
PMOS 4-Bit 1-Chip Microcomputer
•
SM-3A
Block Diagram
Output Port
ROM
36x63x8
Frequency
Control
Clock
2
RAM
8x16x4
Output
Port
31
'----------------------yr---------------------Output Port
Symbol description
ALU
Acc
C
PB, PU,PM, PL
SC
:
:
:
:
:
Arithmetic logic unit
Accumulator
Carry F/F
Program counter
Stack register of program counter
RC
: Stack register of program counter
Bu, BM, BL : RAM address register
X
: Temporary register
S
: Flag F/F
DISP
: Display F/F
37
SM-3A
PMOS 4-Bit t-Chip Microcomputer
•
Pin Description
,.
Pin
KE j -KE 4
a, fJ, AK, 'TAB
DIO j -DI0 4
Rj -R 7
Rs -R 22
F j -F 4
ADI-AD IO
I/O
I
I
I/O
0
0
0
Type of circuit
Pull clown
Pull down
Complementary 3 states
Open drain
Open drain
Open drain
Open drain
IDF
0
Open drain
OD, R/W
T
ACL
0
I
I
0
Complementary
Pull down
ci
~2
Function_
Acc+--KEI-KE~
Possible to test 4 bits independently
Acc+--DIOj -DI0 4
Segment output or R register output
R register output
F j-F 4+--Acc
BL decode output or external RAM address output
Possible to set, reset and test by command
(Suitable for printer motor drive signal)
External RAM control output
For test (usually connected to VDD)
Auto clear
Synchronizing signal terminal
Frequency control terminal
Power source for external RAM connection
Power source for logic circuit
Complementary
VI, SYNC
Vs•
VDD, GND
•
Absolute Maximum Ratings
Parameter
Pin voltage
.
Operating temperature
Storage temperature
Note 1:
Note 2:
Note 3:
•
Symbol
VDD
Vs
VIN
VOUTI
VOUT2
Topr
T s ."
Rating
-20-+0.3
-20-+0.3
-20-+0.3
-20-+0.3
-40-+0.3
-10-+60
-55-+150
Parameter
Input voltage
Output voltage
Supply current
Cycle time
38
4:
5:
6:
7:
8:
Note
1
1
1
1,2
1,3
The maximum applicable voltage on any pin with respect to GND.
Applicable pins include: R/W, DIOI·DIO., OD, ADI-ADlO
Applicable pins include : RI-R2~, FI-F4, IDF
(V DD =-15.0V±10%, VN=-38V, Ta=,-10-+60"C)
Electrical Characteristics
Note
Note
Note
Note
Note
Unit
V
V
V
V
V
"C
"C
Applicable
Applicable
Applicable
Applicable
Applicable
pins
pins
pins
pins
pins
Symbol
VIHI
V1Ll
VIH2
VjL2
VOH!
VOLI
VOH2
VOL2
VOH3
VOL3
IDD
tc
Conditions
TYP.
VDD =-13.5V
MAX.
-10.0
-0.8
VDD =-13.5V
Io =-2mA
RL = 50k il connected to VN
Io =-8mA
RL=50kilconnected to VN
Io=-lmA
R,L =50kil connected to VDD
VDD =-15.0V
~, AK, TAB, KEI - KE.
ACL, Vc SYNC
RI- R7, FI"':F., IDF
Rs- R22
ADl- ADIO
MIN.
-2.5
-10.0
-2.0
VN+I
-3.5
VN+I
~L.O
VDD+l
-12
10
Unit
V
V
V
V
V
V
V
V
V
V
mA
f's
Note
4
5
6
7
8
SM-3A
PMOS 4-Bit 1-Chip Microcomputer
•
1.
2.
3.
4.
5.
6.
- 7.
8.
9.
•
Applications
Electronic cash register
Hard-Hold electronic calculator with printer
POS terminal
Electronic scale
Vending machine
Microwave oven controller
Electronic sewing machine
Controllers of game machines
Others electronic appliance controller~
System Configuration (for VTR program timer)
Control signals
For channel selection
Fluorescent tube display
Rl~------;---------------f
+15V
56kO
56kO
-20V
lOOkO
Key matrix
~'-'------SHARP-'-'---------
39
SM-1 00/SM-1 05
PMOS 4-Bit 1-Chip Microcomputer
SM-IOO/SM-I05
•
Description
•
PMOS 4-Bit I-Chip
Microcomputer
Pin Connections
The SM-100/SM-105 isa 4-bit single chip
PMOS microcomputer with 1,134 bytes of ROM;
and 64 words of RAM. It is well suited for low
cost systems requiring many I/O control ports.
•
Features
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
PMOS process
ROM capacity 1,134X8 bits
RAM capacity 64 X 4 bits
Instructions 58
Subroutine nesting 2 levels
Input ports 4 bits
Output ports 17 bits
Input/Output ports 1 bit
On-chip clock generator circuit
High voltage outputs (-38V) 18 bits
(only SM-100)
11. Single power supply - 9V(TYP.)
12. Instruction cycle 10 ps
13. 28-pin dual-in-line package
------------~-SHARP------ ............ - - - -
40
SM-1 00/SM-1 05
PMOS 4-Bit 1-Chip Microcomputer
•
Block Diagram
ACL
Output
Port
Oscillator
Instruction
1 - - - - - - - - - - 1 Decoder
~---------v~-------~
Output Port
Symbol description
ALU : Arithmetic logic unit
Acc : Accumulator
ACL : Auto clear
C
: Carry F/F
PC : Program counter
SC : Stack register of Program counter
•
RC
DIV
CG
X
ADC
S
:
:
:
:
:
:
Stack register of program counter
Frequency divider
Clock generator
Temporary register
RAM address register
Flag F/F
Pin Description
Pin name
KE 1-KE 4
IDF
R1-R7
R8 -R 13
R14 -R 17
T
ACL
OSCIN, OSC OUT
V DD , GND
I/O
I
I/O
0
0
0
I
I
Pull
Mid
Mid
Mid
Mid
Circuit type
down
voltage * open drain
voltage * open drain
voltage * open drain
voltage * open drain
Function
Acc -KE 1-KE 4
Can be set, reset, and tested by instructions
Segment output or R register output
R register output
R14-R17-Acc or R register output
For test (Connected to V DD normally)
Auto clear
For clock oscillation
Power supply for logic circuit
* For SM-IOO
--.-.--.--.-..--SHARP . . . - - . - - - - - - - - - 41
.SM'-100/SM-1 05
PMOS4-Bit 1-Chip Microcomputer
•
Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Note 1:
Note 2:
Note 3:
•
Symbol
Voo
VIN
VOUT
Topr
T S' 2
Ratings
-12-+0.3
-12-+0.3
-40-+0.3
-10-=--+50
-55-+150
Unit
V
V
V
Note
1
1,2
1,3
t
t
The .maximum .illm!icable voltage on any pin with respect to GND.
Apply to pins ACL, K,-K4, T, OSCIN, OSCOUT.
Apply to pins RI-RI7, !DF..
Recommended Operating Conditions
Parameter
Supply voltage
Oscillator frequency
•
Symbol
Voo
fosc
Ratings
-8.1--9.9
400 (TYP.)
Unit
V
kHz
(V oo =-9.0V±10%, V N=-38V, Ta=25·C)
Electrical Characteristics
Parameter
Input voltage
I SM-I00
I SM-I05
Output voltage
I SM-I00
I SM-I05
Current consumption
Oscillator frequency
Note
Note
Note
Note
Note
4:
5:
6:
7:
8:
Symbol
VIH1
VILl
VIH2
VIL2
VOH1
Conditions
MAX.
-0.8
Vo~+1
IouT =-lmA
Connect RL =50k'o' to VN
VOH2
IOtJT =-8mA
-1.0
V N+l
Voo +l
-1.0
10
400
[00
fose
Applied to pins KEI-KE~.
Applied to pins ACL, T, !DF.
Applied to pins Rl - R7, !DF.
Applied to pins R8-R17.
Reference oscillation: 10 ,us/cycle at 400 kHz
OSC 'N
Unit
V
V
V
V
V
V
Note
4
5
6
V
V N+.1
Voo +l
Connect RL =50k'o' to V N
OSC OUT
42
TYP.
Voo +l
VOLl
VOL2
MIN.
-1.8
V
rnA
kHz
7
8
PMOS 4-Bit 1-Chip Microcomputer
SM-110/SM-115
SM-II0/SM-115
•
Description
The SM-1I0/SM-1I5 isa 4-bit single chip
PMOS microcomputer with 2,032X9 bits of ROM,
128 words of RAM, and AID converter. It is well
suited for low cost systems requiring many I/O
control ports.
•
•
PMOS 4-Bit I-Chip
Microcomputer
Pin Connections
r-- . . .
~
I
p
Nm~U')tl:lZ.t--oom
........................
N N N N NIN 0 N N'N N N N N
41
31
Features
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
PMOS process
ROM capacity 2,032 X 9 bits
RAM capacity 128 X 4 bits
Instructions 90
Subroutine nesting 6 levels
Input ports 11 bits
Output ports 35 bits
InputlOutput ports 4 bits
On-chip clock generator circuit
Interrupt function
External interrupt 1
Timer interrupt 1
11. 8 bits AID conversion
12. Internal divider (1/50 or 1160)
13. High voltage outputs
(-35V) 21bits (only SM-lIO)
14. Single power supply -9V (TYP.)
15. Instruction cycle lOps
16. 60-pin quad-flat package
~--'--------SHARP-----~--'-----
44
SM-100/SM-105
PMOS 4-:Bit 1-Chip Microcomputer
•
Applications
1. Various types of mechanical controllers for
video players, vending machines, etc.
2. Game machines
•
System Configuration (Video timer)
Sun
AM
MOD
Tue Wed Thu Fri Sat
n 0
PM I_I I_I
0
0
R14
Memory indicator
Rr5
R8
Power-on indicator
SM-Ioo/SM-I05
Clock Timer 50/60
----.-----.---~-SHARP --.-.~---.-.-.
43
PMOS 4-Bit 1-Chip Microcomputer
•
SM-110/SM-115
Block Diagram·
Input
Port
Input/Output
Port
~~/~
__
~
________
Output Port
~
__________
-JA~
______________________
~
Analog
Input
Port
Stack
Register
(6Ievels)
ROM
(2,032X9
Control
and Judge
Interrupt
RAM
(l28X4)
TF
CG
IF
HF
15i}--------------------------{:~
'-v--'VDD ACL
GND
Symbol description
ALU : Arithmetic logic unit
Acc : Accumulator
ACL : Auto clear
C
: Carry F/F
U
'--y----/2.5kHz
Input Port
Pulse Output
PC : Program counter
CG : Clock generator
DIV
: Divider
BM, BL : RAM address register
"-v---"
Oscillator
DA
X
CF
D/ A convert er
Temporary register
Comparater
45
PMOS .4-Bit l-Chip Microcomputer
•
SM-110/SM-1.15
Pin Description
Pin name
KE 1 -KE 4
KH
KI
KT
KC 1 -KC 4
P 1 -P 4
R1 -R 16
I/O
I
I
I
I
I
I/O
0
0
Z I - Z I4
0
T
ACL
F
I
I
0
0
QI-Q4
"'2+
Pull
Pull
Pull
Pull
Circuit type
down
down
down
down
Function
Acc +-KE 1 -KE 4
HF flag set on t ; reset by instruction
IF flag set on t ; reset by instruction
External timer signal input (50 or 60Hz)
Analog input or Acc +-KC 1 - KC 4
P 1 -P 4 +-Acc
Q1-Q4- Acc
R register output
Z register output
For test (Connected to V00 normally)
Auto clear
2.5 kHz pulse output (System clock· 100kHz)
Sync' signal output
For clock oscillation
AID conversion standard power supply
Power supply for logic circuit
Open drain
Mid voltage * operi drain
Mid voltage * open drain
Mid voltage * open drain
CLio CL 2
VR, AGND
Voo, GND
* For SM-llO, ZI pin only is high voltage
•
Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Note
Note
Note
Note
•
Symbol
Voo
VIN
VOliTI
VOllT2
Topr
T$t~
Ratings
-12-+0.3
Voo -0.3-+0.3
Vj)j)-0.3-+0.3
-37-+0.3
-10-+70
-55-+150
Unit
V
V
V
V
Note
1
1,2
1,3
1,4
"C
"C
1: The maximum applicable voltage on any pin with respect to GND.
2: Applied to pins KHI-KEI, KCI-KCI, P,-P" Kl,-KIl, KT.
3: Applied to pins F, P,-P" Z,-Z,.
4: Applied to pins QI-Q" RI-RI6, z,.
Recommended Operating Conditions
Parameter
Supply yoltage
Reference voltage
Symbol
MIN.
-9.9
V[)o
VR
5/9 VDD -O.2
TYP.
MAX.
-8.1
-4.5
Unit
V
V
-~-""""---'-"SHARP-~------------
46
PMOS 4-Bit 1-Chip Microcomputer
•
SM-110/SM-115
(V oo =-9V±10%, VN (MAX.)=-35V, Ta=-10-70'C)
Electrical Characteristics
Parameter
Input voltage
I SM-110
Output voltage
I SM-110
Input current
Output current
Current consumption
Oscillator frequency
Symbol
VIIIl
VILl
VIII 2
VIL2
VOHl
VaLl
VOH2
VOL2
VOIU
VOH4
VOL4
lIIi
IR
IOL:)
100
AID conversion zero error
I
AID covers ion full scale error
AID conversion overall error
Reset time
MIN.
-2
tACL
TYP.
MAX.
Voo +2
-0.8
-4.5
Io =-10mA
Connect RL=50kO to VN •
Io=-lmA
Connect RL = 50k 0 to VN.
Io=-0.5mA
Io=-0.2mA
10= 10 /LA
VIN=OV
V R=-5V
Vo=Voo
-2.5
VN +l
-0.2
VN +l
-1
-1
180
900
Unit
V
V
V
V
V
V
V
V
V
V
V
/LA
/LA
/LA
13
400
VR=-5V
Vo[)=-9V
VR=-5V
V[)[)=-9V
VR =-5V
V[)[)=-9V
V R=-5V
V o[)=-9V
At power up
Voo +l
450
1200
-1
fosc
AID conversion linear error
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Conditions
30
rnA
kHz
±3
LSB
±3
LSB
±3
LSB
±3
LSB
20
ms
Note
1
1
2
2
3
3
4
4
5
6
6
7
8
5
10
11
12
Applied to pins KE,-KE" P,-P" KI, KH, KT
__
Applied to pins KC,-KC1. (When used as a digital input), ACL.
Applied to pins RJ(;-R"
Applied to pins RR-R" Q,-Q" Z,.
Applied to pins PI-P" Z,,-Z,
Applied to pins F.
Applied to pins KE,-KEI, KI, KH, KT.
Applied to pins YR. (current flowing into ladder resistance for AID conversion).
Applied to pins R,b-R" P,-P" Q,-Q" Z,,-Z1.
Measured in no· load condition.
Externally connected to oscillation circuit.
CF : Ceramic oscillator
KBR-400B(made by Kyocera Corp.)
R, : 1MO
C,: 220pF,C,: 220pF
l,uF /16
ALCo---~------~
56kO
Note 12:
The time for reset of "Low" signal that is applied to the ACL terminal after supply voltage returns to rated level.
----.--------SHARP---~.--.----
47
SM..:nO/SM~f15
_ r i...~··~.....
PMOS 4-Bit1-Chip Microcomputer
. . . . . . . . ._
. . ._
. . . . . . .
. . - .
. . . . . . . .
....."
.......
. - . . - .
..................
:11.
•. Applications
1. Microwave oven controllers
2. Blood pressure monitors
3. Controllers for home appliances and audio
equipment
•
' System Configuration (Microwave oven controllers)
.Fluorescent tube display
III"
n ,-,
III'd/U
Vnn
r--~J.....;:.;;:::';'::'::""-:f--:::L-....::...-~----,Crystal 220 F
400kHz
P
CL11--1_--11---,
Key matrix
Q---
}-........-\zs
CL2 .........~~,tF--1--;
I
I
I
ACL tE-_-"V'.rv-~
I
}-.......-\Z14
SM-llO/SM-1l5
L----:-~KE4
\
'--------'--tKEJ
50/60Hz
signal --r--->I
V,," 1----.----<>---<> -9 V
GNDt---t----.
AGND
48
PMOS 4-Bit 1-Chip Microcomputer
SM-111/SM-116
SM-lll/SM ... 116
•
Description
The SM-lll1SM-116 is a 4-bit single chip
PMOS microcomputer with 4,064 X 9 bits of ROM,
192 words of RAM, and AID converter. It is well
suited for low cost systems requiring many 110
control ports.
•
•
PMOS 4-Bit I-Chip
Microcomputer
Pin Connections
r--. ...
N
~
..,.
It:!
~
Q
Z
t--
GO
0)
..............
::<:NNNNNN(,!lNNNNNNN
41
3
3
31
F·
KC, 7
KC,
KC 2
KC,"
VR 51
Features
1. PMOS process
2. ROM capacity 4,064 X 9 bits
3. RAM capacity 192 X 4 bits
4. Instructions 90
5. Subroutine nesting 6 levels
6. Input ports 11 bits
7. Output ports 35 bits
8. Input/Output ports 4 bits
9. On-chip clock generator circuit
10. Interrupt function
External interrupt 1
Timer interrupt 1
11. 8 bits AID conversion
12. Internal divider (1150 or 1160)
13. High voltage outputs (-35V) 21bits (only
SM-ll1)
14. Single power supply -9V (TYP.)
15. Instruction cycle 10 ps
16. 60-pins quad-flat package
I (62+
, CL2
1
2
3
4
5
6
7
8
91
~ ~ ~ ~ r:J cE c:.~ ~
(,!l
<
(,!l
11 1
3
4
5
aa a a ~Id<
Top View
- - - - - - - - - - S H A R P .-..---------~-----49
PMOS 4-Bit1-Chip Microcomputer
•
SM-t111SM-116
Block Diagram
Output Port
r -____~----~--~----~----~A~----------------------------~
Analog
Input
Port
Stack
Register
(6 levels)
Control
and Judge
Interrupt
RAM
(192X4)
TF
IF
HF
'-v---" 2.5kHz
Input Port
Symbol description
ALU : Arithmetic logic unit
Ace : Accumulator
ACL : Auto clear
C
: Carry F/F
50
Pulse, Output
PC ,: Program counter
CG : Clock generator
DIV
: Divider
BM, BL : RAM address register
'--y--'
Oscillator
DA
X
CF
D/ A converter
Temporary register
Comparater
PMOS 4-Bit 1-Chip Microcomputer
•
SM-111/SM-116
Pin Description
Pin name
KE 1 -KE 4
KH
KI
KT
KC 1 -KC 4
P j -P 4
Qj-Q4
R1 -R 16
ZI-ZI4
T
ACL
F
1>2+
110
I
I
I
I
I
110
0
0
0
Pull
Pull
Pull
Pull
Circuit type
down
down
down
down
Function
Acc -KE 1 -KE 4
HF flag set on t ; reset by instruction
IF flag set on t ; reset by instruction
External timer signal input (50 or 60Hz)
Analog input or Acc-KCj-KC j
P I -P 4 -Acc
QI-Qj-Acc
R register output
Z register output
For test (Connected to VI>I> normally)
Auto clear
2.5 kHz pulse output (System clock·100kHz)
Sync signal output
For clock oscillation
AID conversion standard power supply
Power supply for logic circuit
Open drain
Mid voltage * open drain
Mid voltage * open drain
Mid voltage * open drain
I
I
0
0
CLio CL 2
YR. AGND
VDI>. GND
* For SM-1l1, ZI pin only is high voltage.
•
Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Note
Note
Note
Note
•
1:
2:
3:
4:
Symbol
VDI>
VIN
VOlITl
VOllT2
Topr
Tst~
Ratings
-12-+0.3
VDD -0.3-+0.3
VI>D-0.3-+0.3
-37-+0.3
-10-+70
-55-+150
Unit
V
V
V
V
Note
1
1,2
1,3
1,4
·c
t
The maximum applicable voltage on any pin with respect to GND.
Applied to pins KEI-KEI, KCI-KCI, PI-PI, Kl, KH, KT.
Applied to pins F, PI-PI, Z2-ZI.
Applied to pins QI-QI, RI-RI6, ZI.
Recommended Operating Conditions
Parameter
Supply voltage
Reference voltage
Symbol
MIN.
-9.9
VDI>
5/9 VDD -O.2
VR
TYP.
MAX.
-8.1
-4.5
Unit
V
V
---.-.-..-.--------SHARP - - - - - - - - - - - - 51
SM-111/SM-116
PMOS 4.:.Bit 1-Chip Microcomputer
•
(V DD =-9V±10%, VN (MAX.)=-35V, Ta=-.10-70·C)
Electrical Characteristics
Symbol
Parameter
Input voltage'
I SM·111
Output voltage
I SM·l11
Input current
VIlli
VII. I
VIm
V IL2
VOIII
VOL!
VOlI2
VOL"
VOIU
VOII.1
Vou
lIN
IR
Output current
Current consumption
Oscillator frequency
IoL:)
Ill[)
AID conversion zero error
AID coversion full scale error
AID conversion overall error
Reset time
MIN.
-2
t ACL
TYP.
MAX.
Vllll +2
-0.8
-4.5
Io =-10mA
Connect RL = 50kO to VN.
Io =-lmA
Connect RL = 50k 0 to V N.
Io=-0.5mA
Io=-0.2mA
Io =10,uA
VIN=OV
V R =-5V
VO=VDD
-2.5
V N+l
-2
V N+l
-1
1
180
900
13
400
V R =-5V
V Dn =-9V
V R =-5V
V"n= -9V
V R =-5V
VllI)=-9V
V R =-5V
V DD =-9V
. At power up
V1)[)+1
450
1200
-1
fosc
AID conversion linear error
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Conditions
30
Unit
V
V
V
V
V
V
V
V
V
V
V
,uA
,uA
,uA
rnA
kHz
±3
LSB
±3
LSB
±3
LSB
±3
LSB
20
Applied to pins KE,-KEI, P,-P" KI, KH, KT
Applied tu pins KC,-KCI. (When used as a digital input), ACL.
Applied to pins R'6- R9
Applied to pins RR-RI, QI-QI, Z,.
Applied to pins PI-PI, ZII-ZI
Applied to pin F.
Applied to pins KEI-KEI, KI, KH, KT.
Applied to pin YR. (current flowing into ladder resistance for AID conversion).
Applied to pins Rlo-RI, P,-PI, Q,-QI, Z1I-Z,.
Measured in no· load condition.
Externally connected to oscillation circuit.
CF : Ceramic oscillator
KBR-400B(made by Kyocera Corp.)
Rf: 1MO
CI: 220pF,C2: 220pF
l,uF/16
ACL
0---+-----,
56kO
Note 12:
52
The time for reset of "Low" signal that is applied to the ACL terminal after supply voltage returns to rated level.
ms
Note
1
1
2
2
3
3
4
4
5
6
6
7
8
5
10
11
12
SM-114
PMOS 4-Bit 1';"Chip Microcomputer
SM-114
•
PMOS 4-Bit I-Chip Microcomputer
Description
•
Pin Connections
The SM-1l4 is a 4-bit single chip PMOS microcomputer with 4,064X9 bits of ROM, 192X4 bits
of RAM, 8-bit A/D converter, timer/counter and
remote control signal receiver.
It is best suited to controllers which measure
temperature and humidity of analog value from a
sensor.
•
Z14
Features
1.
2.
3.
4.
5.
6.
7.
8.
9.
PMOS process
ROM capacity 4,064 X 9 bits
RAM capacity 192X4 bits
Instructions 92
Subroutine nesting 6 levels
Input ports 8 bits
Output ports 17bits
Input/Output ports 24 bits
Timer/counter
7-bit 1
8-bit 1
10. Interrupt functions
External interrupt 1
Timer interrupt 2
11. 8-bit A/D conversion
12. Remote control signal receiver
13. Single power supply -9V(TYP.)
14. Instruction cycle 10 ps (TYP.)
15. 60-pin Quad-flat package
54
R20 '
AGND
SM-11~/SM-116
PMO$4-Bit 1-Chip Microcomputer
•
Appli~a:tions
1. Microwave oven controllers
2. Blood pressure monitors'
3. Controllers for home applia,nces and audio
equipment
•
System Configuration (Microwave oven controllers)
Fluorescent tube display
I I I / ' ,-,,-,I
LII "LlU
Vuu
Key matrix
0---
}-..e---\Zs
CL2r-+-~~~-+-,
I
I
I
ACL IE--.--IIM---'
I
I
}-+----\Z14
SM-lll /SM-116
'-------:---.>-IKE 4
lkO
VI>I)I---1'--~-o-9V
\
'---------~KEI
SO/60Hz
GNDf---+'-----.
signal----1o---+I
AGND
lOOkO
iOOkO
lOO'kO
53
'
PMOS 4-Bit 1-Chip Microcomputer
•
SM-114
Block Diagram
.
Input' Output Port
Output
Port ,
Input Port
Symbol description
ALV
A ....
ACL
C
CY
B
:
:
:
:
:
:
Arithmetic logic unit
Accumula tor
Auto clear
Carry F F
Over flow F F
RAM address register
PC
SR
SP
INT
CG
Program counter
Stack register of program counter
Stack pointer
Interrupt control unit
Clock generator
RCV
D/A
COMP
DIV
VR
Remote control unit
D A converter
Comparator
Divider
Reference Voltage
------~.--SHARP.-----~--.-..---
55
·SM-H4
PMOS.4-Bit 1-Chip Microcomputer
•
Pin Description
Pin name
KC o -KC:1
KL
KI, KH
KT
PO-P:l
QO-Q3
RO(;-R3:1
ZO-ZI5
F
TA,TB
ACL
110
I
I
I
I
Pull
Pull
Pull
110
Open drain/Pull down *
0
0
I
I
0
Open dra{n/Pull down *
~
Circuit type
down*
.
*
down.
down* •
.'
Pull down
CLl> CL 2
VR, AGND
Voo , GND
Function
Analog input or Acc-KCo-KC:l
For optical remote control circuit
IF, HF flag set on t
External timer signal input
!
PO""'P:l
RO, R1, R3-RAM
QO-Q:l
RO,R1,R3
Can be set, reset individually
Sound output
For test (Connected to VDD normally)
Auto clear
System clocj{ output
For clock oscillation
A/D coversion standard power supply
Power supply for logic circuit
Acc-
* Mask option
•
Absolute Maximum Ratings
Parameter
Pin voltage
. Operating temperature
Storage temperature
Note 1:
•
Symbol
Ratings
-12-+0.3
Voo
(Voo-0.3)-+0.3
VIN
VOllT (V 00-0.3)- +0.3
-10-+70
Topr
-50-+150
TSt2
Unit
V
V
V
·C
Note
1
"C
The maximum applicable voltage on any pin with respect to GND.
Recommended Operating Conditions
Parameter
Supply voltage
Reference voltage
56
Symbol
Voo
VR
MIN.
-9.9
-4.5 .
TYP.
MAX.
-8.1
5/9VDD-O.2
Unit
V
V
-.
PMOS 4-Bit 1-Chip Microcomputer
•
SM-114
(V ee =-9V±10%, Ta=-10-70'C)
Electrical Characteristics
Parameter
VIHI
VILl
VIII2
VIL2
VIII :l
VIL:l
VOH!
VaLl
VOH2
VOL2
Inll
IR
Input voltage
OutJ'Ut voltage
Input current
Current consumption
Oscillator frequency
AID conversion linear error
AID conversion zero error
AID conversion full scale error
Note
Note
Note
Note
1:
2:
3:
4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Applied
Applied
Applied
Applied
Symbol
to
to
to
to
Conditions
MIN.
-1
Ratings
TYP.
MAX.
Voo +1
-2
Voo +1
-0.8
Voo +1
lo=-2mA
10=20 pA
Io =-2rnA
RL =50kO
VIN=OV
VR =-5V
-1
Voo +1 Voo +1.5
-1
100
fose
V R =-5V
VR =-5V
VR =-5V
Voo +1
180
500
20
400
900
±3
±3
±3
Unit
V'
V
V
V
V
V
V
V
V
V
pA
pA
rnA
kHz
LSB
LSB
LSB
Note
1
2
3
4
5
6
7
8
9
pins
pins
pins
pins
RO:l-ROo, RIa-RIo, R2:l-R20, R3:l-R30, POI-PO, Q:l-Qo
KI, KH, KL, KT
KC:.- Keo (when used as a digital input), ACL.
RO:l-ROo, Rl:!-RIo, R2:l-R20, R3:l-R30, POI-PO, Q:l-Qo, Z,,-Zo, F
(when an internal pull-down resistance is attached to R, P, Q, and Z)
Applied to pins RO:l-ROo, Rl:!-RIo, R2:l-R20, R3,,-R30, P,,-Po, Q:l-Qo, ZI'-ZO
(when an internal pull-down resistance is not attached).
Applied to pins RO,,-ROo, Rl:!-RIo, R2,,-R20, R3:I-R30, P,,-Po, Q,,-Qo, KI, KH, KL, KT
(when an internal pUll-down resistance is attached)
Applied to pin V. (current folwing into ladder resistance for AID conversion)
Measured in no-load condition_
Externally connected to oscillation circuit
Rr=lMO
CI = 220pF
C2=220pF
57
PMQS, 4-Bit 1-Chip Microcomputer
•
. SM-:-114
System Configuration (Controllers)
Control signals
, - -_ _~A
R33 -
R30 R23 -
Control signals
,
~
.R2o Zo
-
Z9
----:----1Rl,
ZlS.-------,
I
P3 k - - - - '
------I RIo
Control signals
P2i------'
....---.---IR0 3
I
--......c.--IRO o
Pli-------~
Po~-----~---'
KTt+--KI t - - - - } Sensor input 1
+-:--:---IQ3
I
KHk----
------IQo
KC 3
~ \
-------IF
Optical remote
control input o------IKL
, - - - - - - - 1 AGND
.------IGND
TB
TA V»»
To
KColE----
VDD
56k!l
C+-~- 1:~
,--1_M_!l-4_ _
220pF
58
}
I
Sensor input 2
(analog input)
SM-120
PMOS 4-Bit 1-Chip Microcomputer
SM-120
•
PMOS 4-Bit I-Chip Microcomputer
Description
•
Pin Connections
The SM-120 is a 4-bit single chip PMOS microcomputer with 1,536 bytes of ROM, 64 words of
RAM, and a 17-stage divider. It is well suited for
low cost systems requiring many 110 control ports.
•
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
Features
PMOS process
ROM capacity 1,536 X 8 bits
RAM capacity 64 X 4 bits
Instructions 54
Subroutine nesting 2 levels
Input ports 9 bits
Output ports 26 bits
External ROM expandable (512 X 8 bits)
On-chip clock generator circuit
Internal 17-stage divider with reset (timer circuit)
Alarm sound generator circut
High voltage outputs (-38V) 19 bits
Single power supply -9V (TYP.)
Instruction cycle 10 p.s
44-pin quad-flat package
59
SM-120
PMOS 4-Bit 1-Chip Microcomputer
•
Block Diagram
Output 'Port
Output Port
~
__
___
~A
~
Port
Input Port
'--v-"
Voo
GND
Symbol description
ALU
Ace
ACL
PC
60
Arithmetic logic unit
Accumulator
Auto clear
Program counter
SRI, SR,
DIVo, DIVI, DIV2
CG
H,L
Stack register of program counter
Divider
Clock generator
RAM address register
PMOS 4-Bit 1-Chip Microcomputer
•
Pin Description
Pin
P IO -P I3
P 2O -P 23
PI
BIO -B I3
R
lIO
I
I
I
Type of circuit
down
down
down
down
down
down
0
0
0
0
Pull
Pull
Pull
Pull
Pull
Pull
So-5 7
0
Open drain
0 0-0 10
F
T
ACL
OSCIN, OSCOUT
VDD, GND
0
0
I
I
Open drain
Pull down
Pull down
Pull down
•
Function
Aee-PlO-PI3
Aec -P 20 - P 23
PI flag set by t, reset by command
BlO-BI3+-Ace
Possible to set, reset, or CE signal output
Possible to set and reset
Display segment signal output or internal ROM
data output
Display digit signal output
Alarm sound output
For test
Auto clear
Clock oscillation
Power source for logic circuit
Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Note
Note
Note
Note
•
SM-120
1:
2:
3:
4:
Symbol
VDD
VIN
VOUTl
VOUTZ
Toor
TstQ
Rating
-20-+0.3
-20-+0.3
-20-+0.3
-40-+0.3
-10-+65
-55-+150
Unit
V
V
V
V
Note
1
1,2
1,3
1,4
"C
"C
The maximum applicable voltage on any pin with respect to GND.
Applicable to inputs
Applicable Pins BIO- Bt:l, a, aSCOlIT, R, F
Applica.ble Pins Do- DlO, SO-S7
Operating Conditions
P¥ameter
Supply voltage
Oscillator frequency
Note 5:
Symbol
Specified value
Unit
V DD
-8.1--9.9
300-800
V
fose
kHz
Note
5
Frequency supplied to aSCIN Pin.
61
......-.-....-:--,..-..-.-.-.-.-.-..-.-....... 'SM-120
PMOS4-Bit1-Chip Microcomputer
;~---
•
(V DD =-9.0±10%. V N=-36V, Ta=-10":"+65"C)
Electrical Characteristics
Symbol
Parameter
ViHl
V ILl
VIH2
V IL2
:IIHl
IILl
IIH2
IIL2
IIH3
IIL3
VOHl
VOLl
VOH2
VOL2
VOH3
VOL3
' V'OL3
VOH4
Input voltage
Input current
Output voltage
YOL4
Y'OL4
VOHS
VOLS
V'OLS,
IDD
Current consumption
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
6:
7:
8:
9:
10:
11:
12:
13:
14:
15:
Applicable
Applicable
Applicable
Applicable
Applicable
Applicable
Applicable
Applicable
Applicable
Applicable
Conditions
TYP.
MAX.
-7.0
-1.5
VIN=GND
VIN=V DD '
VIN='GND
VIN=VDD
VIN=GND
VIN=VDD
IoH =-6.0rnA
RL =50kO connected to V N
IoH =-2.0rnA
RL =50kO connected to V N
IOH=-0.5mA
IoL =50 pA
IoL =200pA
IoH =-1.0mA
IOL=50pA
IOL=200pA
IoH =-1.0rnA
IOL=100pA
IOL=300pA
pins PIO- PI3, P20- P':J
pins PI, ACL, aSCIN, T
pins PIO-PIS, P'O-P'3, PI, T
pin ACL
pin asclN ,
pins DIO-DI3
pins SO-S7
pins BIO- B13, F
pins R,
pin aSCOl1T
a
MIN.
-3.5
-7.0
200
-10.0
700
-10.0
5.0
-10.0
-2;5
V N+1.0
-2.0
V N+1.0
-3.0
V DD +1.5
V Do +3.0
-1.5
V Do +1.5
V Do +3.0
-1.5
V DD +1.5
V Do +3.0
20
Unit
V
V
V
V
pA
pA
pA
pA
pA
pA'
V
V
V
V
V
V
V
V
V
V
V
V
V
rnA
Note
6
7
8
9
10
11
12
14
15
PMOS 4-Bit 1-Chip Microcomputer
•
SM-120
Applications
1. VTR timer
2. Electronic home appliance controller
3. Game machine
•
System Configuration (for 5 X 7 dot matrix fluorescent display tube drive)
5 x 7 dot matrix fluorescent display tube
r-------------~--
--------------
lOkO
27kO
Power for display Crystal
-36V
524.288kHz -36V
2.2kO 470pF
27kO
IOkO
-36VO--"I/VIr-T
Sot---~+-+I Ao
~--+--IDo
SM-120
(
)
Ll2048
(Dot matrix driver)
\
I
I
I
I
--------6
Key matrix
---.-------SHARP.-.--...-.---63
-
-
.....----.
..... ....................,,----..........,.....
SM-200 NMOS 4-Bit I-Chip Microcomputer
~--
•
Description
The SM-200 is 4-bit single .chip NMOS microcomputer with 3,072X9 bits of ROM, 132 words of
RAM, automatic display circuit, and a 16-stage
divider. It is well suited for low cost systems reqlliring many 110 control ports.
SM:..200
•
Pin Connections
Q
22 r... d: rE d: ~ ~ rE ~ ~.:2~ ll~'
OSCIN"
SCOUT
7
CT
8
aD
•
Features
1. NMOS process
2. ROM capacity 3,072 X 9 bits
3. RAM capacity 128X4+ 16 bits
4. Instructions 100
5. Subroutine nesting 3 levels
6. Input ports 10 bits
7. Output ports 37 bits
8. Input/Output ports 4 bits
9. Enable 8 bits parallel input/output
10. Externally ROM/RAM expandable
11. External interrupt function
12. Internal 16-stage divider ·with reset
(timer circuit)
13. Serial interfaces 8 bits
14. On-chip clock generator circuit
15. Single power supply 5V (TYP.)
16. Instruction cycle 10 p.s
17. 60-pin quad-flat package
64
Top View
NMOS 4-Bit 1-Chip Microcomputer
•
SM-200
Pin Description
Pin
Ko-K 3
CT
I/O
I
I
I
I
P IO -P I3
I
P 2O -P 23
I/O
RW
0
OD
0
Eo-E 3
BIO -B I3
B20 -B 23
0 1 -0 3
0
0
0
0
Do-D l l
0
0 0 -0 7
F
INT
ACL
OSC IN, OSCOUT
VDD, GND
0
0
I
I
1.
h
•
Type of circuit
Pull down
Open
Pull down
Pull down for input
Function
ACCI-Ko-Ka
Set by t, reset of after test instruction execution
Internal clock period type, test possible
For pulse count per unit time
ACCI-PIO-PI3, Instruction code input for external
ROM
Acc2-P20-P2:j, Instruction code input for external
ROM data transter from/to RAM for external RAM
Set, reset by instruction; chip select for external ROM
Connected to RW pin for external RAM
Set, reset by instruction; Instruction code input for
external ROM; connected to OD pin for external RAM
Eo-E3-Accl
BlO-BI3-Accl
B2o-B23-AcC2
Set, reset by instruction
Display digit signal output; Address signal output for
external ROM, RAM
Display segment signal output
,
Alarm sound output
Set of INT F/F by t
Auto clear
Clock oscillation
Power supply for logic circuit
,
Pull down
Pull down
Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Note 1:
•
Symbol
VDD
VIN
Topr
T st•
Ratings
-0.5-+7
-0.5-V DD +0.3
-10-+65
-55-+150
Unit
V
V
Note
1
"C
"C
The maximum applicable voltage on any pin with respect to Vss (GND)
Operating Conditions
Parameter
Supply voltage
Oscillator frequency
Symbol
VDD
fosc
Specified value
4.5-5.5
262.144
Unit
V
kHz
--------------SHARP---.---------66
SM... 200
NMOS 4-Bit 1-:-Chip Microcomputer
,...."~I1fIfIfIIII'....,,,..,~.,.,,,;•.•~~'-~"""~..tIIIIIIIII!IP....-.r~"""""""A!IIIIIIIIW
•
Block Diagram
Divided
Display Segment Output
Display Digit Output
r - __________
~A~
Osci- {
Bator
Pulse
Input
____________
~
46
47
Asynchronous
Input
Symbol description
ALU
Acc,. Acc2'
ACL
C
PC
SR,. SR2. SR3
:
:
:
:
:
:
Arithmetic logic unit
Accumulator
Auto dear
Carry F/F
Program counter
Stack register of program counter
CG
DIV
H.L
SD
DD
X.Y
:
:
:
:
:
:
Clock generator
Divider
RAM address r,!'gister
Segment decoder
Digit decoder
Temporary register
65
NMOS 4-Bit 1-Chip Microcomputer
•
(VI)I)=5V, Vss=GND, fosc =262kHz, Ta=25"C)
Electrical Characteristics
Parameter
Input voltage
Input current
Output voltage
Symbol
VIlli
VILI
VIII2
VIL2
11111
IlL I
11112
IIL2
1m3
11114
hL4
VOIll
V'OIll
VOLI
VOH2
V'01l2
VOL2
VOll3
V'OIl3
VOL3
VOll4
V'01l4
VOL4
VOIIS
V'OH5
Current consumption
Note 2:
Note 3:
Note 4:
Note
Note
Note
Note
•
SM-200
5:
6:
7:
8:
VOLS
VOH6
VOL6
VOH7
VOL7
VOH8
VOL8
100
Conditions
MIN.
2.4
0
2.4
0
VIN =5V
VIN=GND
VIN =5V
VIN=GND
VIII =5V
IOH=10pA
101l=0.2mA
I 10L I =0.15mA
IOIl-25pA
IOIl=0.6mA
I 101. I =0.25mA
1011 =10 pA
1011 = O.4mA
I 10L I =0.3mA
IOII=10pA
IOIl=0.3mA
I IOL I = 0.3mA
1011 =10 pA
IOH=0.3mA
I IOL I =50 pA
IOH=0.2mA
I IOL I =0.25mA
IOII=0.15mA
I IOL I =0.15mA
IOH=50pA
I IOL I =50 pA
Open all input and output" pins
Applicable pins PIO-PI3, h-]2, INT, CT, ACL, P20P23 in input mode, OD in input mode.
Applicable pins Ko- K3
Applicable pins PIO-PI3, Ko-K3, 11,]2, INT, P20-P23
in input mode, OD in input mode
Applicable pin CT
Applicable pin OSC IN
Applicable pin ACL
Applicable pins BIO-BI3, B20-B23, Eo-E3, 01-03
Note
Note
Note
Note
Note
Note
Note
9:
10:
11:
12:
13:
14:
15:
Applicable
Applicable
Applicable
Applicable
Applicable
Applicable
Applicable
TYP.
Unit
V
V
V
V
15
-1
1
-1
5
15
MAX.
5
0.5
5
0.6
50
-10
10
-10
25
50
32
5
5
0.5
5
5
0.5
5
5
0.5
5
5
0.5
5
5
0.5
5
0.5
5
0.5
5
0.5
56
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
rnA
3.6
2.4
0
3.6
2.4
0
3.6
2.4
0
3.6
2.4
0
3.5
2.4
0
2.4
0
2.4
0
3.6
0
pA
pA
pA
pA
pA
pA
pA
Note
2
3
4
5
6
7
8
9
10
11
12
13
14
15
pins So- S7
pin RW
pin F
pins Do-[hlpin OD in output mode
pins P20-P23 in output mode
pin OSCOUT
Applications
1. General·purpose program timer
2. Controllers for electronic home appliances,
Audio equipment, Office machines
3. Door chime, Home security system
4. Hand-held calculator with printer
5. Cash register
6. Copy machine controller
7 . Vending Machine
8. Radio cassette tape recorder and PLL controller
9. TV remote control and channel controller
- - - - - - - - - S H A R P -----.-.---------.-..-.67
~I
;;;: ;;;:
•
"" _....,c::
}Key input
'<
MK output
3
~ ~;;;: >ri
I
I
~
~
.
I
I
I
I
I
I
I
I
cO'
d
~
o
::::J
...,
I o~
oo
:::0
FU output (2)
E2
(Output level reverses on each FU input)
EI I - - MT output
t----->-
I
I
I
en
CD
I
I
FU output
77r
DC
+ 5V
K3
Counter control
output
K2
KI
A
Eo
03
OD
INT
D9
DB
'"~.
g.
o
::::J
;;;:
c::::
~
....
s
B22
ON/OFF SQ
B21
r'l'1'
E.
'"'
-5'
~
....
B20
'0
oC/)
BI21MUTE
Bl1
BIO
(GND)
s,
il6 il6 D. il6 n, DI il6 Vss 80 81 82 83 8. 85 86
D,
Radio ON/OFF
'0-"
-...
~
"-
B23
SM·200
Dl1
Dlo
Melody output
01
VDD
RW
J2
JI
ACL
PC5 output
02
'I·~·'
en
-I
en
P L L shift register term inal
Cb
'og."'
....
2.
:;;
.:::!-.
I~
II
I
I
II
'I
I
I
U
SM-4A
CMOS 4:-Bit 1-Chip, Microcomputer
SM-4A
•
CMOS 4-Bit I-Chip Microcomputer
Description
The SM-4A is a 4-bit single chip CMOS microcomputer with 2,268 bytes of ROM, 96 words of
RAM, a 15-stage divider and 68-segment liquid
crystal driver circuits. It is well suited for applications of low power hand-held equipment with
many liquid crystal display segments.
•
•
Pin Connections
~~~~~~~~~~~:~::
0000000"0000000
Features
1. CMOS process
2. ROM capacity 2,268 X 8 bits
3. RAM cap~city 96 X 4 bits
4. Instructions 54
5. Subroutine nesting 1 level
6. Input ports 6 bits
7. Output ports 40 bits
8. Input/Output ports 4 bits
9. On-chip 50-stage divider with reset
(timer circuit)
. 10. External RAM driver (256 X 4 bits)
11. Direct LCD driver circuits (3V, 112 duty,
112 bias and 68 segments MAX.)
12. Standby mode (10 fJ-A current consumption)
13. Single power supply - 3V (TYP.)
14. Instruction cycle 61 fJ-S
15. 60-pin quad-flat package
1
2
3
4
....
M
N
......
5
0000:':
SSSS
6
~
7
I!
9
1
11 1
13
41
5'"''"'
N
~ ..,. z
r- ...
z:'::'::':U'
c:tl.Q
"
C/lU
o
~
N
Top View
- . - . - - - . - - - S H A R P ........ .-..---~---
69
CMds 4-Bit 1-Chip Microcomputer
..............................._
•
. SM-4A
.........,.............AIIIIiiIIIiF.....'...._ . ....""....
Block Diagram
Segment Output
r-___________________________________
________________________________
~A~
~
Segment
Output
Segment
Output
'---v--"
I/O Port
Symbol description
ALU
AI'c
ACL
C
Cx. CA. Pu. PL
Cs. SUo SL
70
:
:
:
:
:
:
'-v-'~
~~
Asynchronous Input Port
Input
Arithmetic logic unit
Accumulator
Auto clear
Carry F/F
Program counter
Stack register of program counter
Oscillator
BM. BL
DIV
PLA
Test
: RAM address register
: Frequency divider
: Programable logic array
CG
: Clock generator
WI-W,. Wl';...W. : Static shift·register
CMOS 4-Bit 1-Chip Microcomputer
•
Pin Description
Pin
K1 -K 4
a
110
I
I
I
110
0
f3
DIO I -DI0 4
Rl -R 4
01l-048
OSlo OS2
•
SM-4A
Function
Acc+-K l -K 4
Set by t, reset after test instruction execution
Input signal is held for 1 instruction, test possible
Acc-DIO I - DI0 4
Rl -R 4 +-Acc
Output of Wand W' registers' content; used for LCD
segment output
3-state level output possible, used for LCD common
output
For low voltage detection circuit
For test (usually connected to V00)
Auto clear
For clock oscillation
Power supply for LCD driver
Power supply for logic circuit
Type of circuit
Pull down
Pull down
Pull down
3-state output
Complementary
0
Hb H2
0
BA
Tlo T2
ACL
OSC lN , OSC OllT
VM
GND, Voo
I
I
I
Pull up
Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Symbol
Voo
VM
VlN
T oDr
Tst2
Ratings
-,3.5-+0.3
-3.5-+0.3
V00-0.3- +0.3
-5-+55
-55-+150
Unit
V
V
V
Note
1
"C
"C
Note 1: The maximum applicable voltage on any pin witb respect to GND.
•
Operating Conditions
Parameter
Supply voltage
Supply voltage
Oscillator frequency
Symbol
Voo
VM
fose
Specified value
-3.2--2.6
Voo/2 (TYP.)
32.768 (TYP.)
Unit
V
V
kHz
/
'-'-~-----"'--'--SHARP -----..--,-~----..--~
71
CMOS 4-Bit 1-Chip Microcomputer
•
'SM-4A
(V oo =-3.2--2.6V, Ta=25"C)
Electrical Characteristics
Parameter
Symbol
Conditions
MIN.
-0.6
V UIl •
V ILl
Input voltage
Output voltage
Ou.tput curreBt
Current consumption
3:
4:
5:
6:
7:
8:
Applicable
Applicable
Applicable
Applicable
Applicable
Applicable
-0.3
Vmz
V IL2
VOHI
VOLl
VOH2
VOL2
VOII:l
VOL:l
VOA
VOB
Voc
Iso
ISIN
InA
Ins
pin ACL
pins 0'8-0ll, Osl, OS2
pins DIOI-DIO,
pins R2, R3, R,
pins HI, H2
pin RI
V nn +0.3
louT-50 pA to Voo
IOllT =5,uA to GND .
IOllT=50 pA to Vno
loUT = 30 pA to GND
IOUT=50 pA to Vnn
IOlIT=50 pA to GND
No load
Voo =-3.0V
V M =-1.5V
VOllT =-0.2V
VOllT=Vno+0.2V
In full- range operation
When system clock is stationary
-0.5
V nn +0.5
-0.5
Voo+0.5.
-0.5
Vnn +0.5
-0.3
-1.5
-2.7
100
100
50
10
'
/
72
MAX.
Voo+0.6
Note 2: Applicable pins KI, K2, K3, K" a, f3
Note
Note
Note
Note
Note
Note
TYP.
100
20
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
'pA
pA
pA
pA
Note
2
3
4
5
6
7
8
SM-4A
CMOS 4-Bit 1-Chip Microcomputer
•
1.
2.
3.
4.
5.
6.
7.
8.
•
Applications
Hand-held calculator with clock function
High-quality clock
Cash register
General-purpose timer
Electronic scale
Game machine
Vending machine
Controllers for electronic home appliances
and audio equipment
System Configuration (for radio PLL controller)
LCD
DC voltage cutout O.02JlF
r---:~~.....J._--:::--.......Ji...--'32. 768kHz 22 pF
Band selection
OSCOUTI--+----I
r~-~BA
Tape stop
GND~-~~~~Nr~~~_,
Various controls {
V y. J--+_---,
SM-4A
220kO
PLL latch
PLL shift register' clock
PLL shift register data
MUTE
DIal
DI0 2
DI0 3
DIO.
V[)~-~~~+-----'
O_33,uF
ACL
a
P
047-----;~
046---~
045---~
04'---~
043-----;~
O.2-----;~
038--~
.-.----------SHARP-.-.-------
73
.---....--.... ........
CMOS 4-Bit 1-Chip Microcomputer
.-- -.".-~
-....,
SM-SA
•
The SM-5A is a 4-bit single chip CMOS microcomputer with 1,827 bytes of ROM, 65 words of
RAM, a 15-stage divider and 72-segment liquid
crystal driver. circuit. It is well suited for applications of low power hand-held equipment with
many liquid crystal display segments.
•
Features
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
74
..
CMOS 4-Bit I-Chip Microcomputer
Description
CMOS process
ROM capacity 1,827 X 8 bits
RAM capacity 65 X 4 bits
Instructions 51
Subroutine nesting 1 level
Input ports 6 bits
Output ports 42 bits
On-chip 15-stage divider with reset·
(timer circuit)
Direct LCD driver circuit
(3V, 112 duty, 112 bias and 72 segments
MAX.)
On-chip crystal-controlled oscillator
(32.768kHz)
Standby mode (10 pA current consumption)
Single power supply -3V (TYP.)
Instruction cycle 61 ps
60-pin quad-flat package
....- ....-
/' SM-SA
•
Pin Connections
CMOS 4-Bit 1-Chip Microcomputer
•
SM-5A
Block Diagram
Segment ______________________
Output
r -____________________
--JA~
Segment
Output
fl
~
5
. Segment
Output
,)-------{23
~
Output
Port
'--v---'
~
Asynchronous Input Port
Input
Symbol description
ALU : Arithmetic logic unit
Acc : Accumulator
CG : Clock generator
ACL: Auto clear
DIV : Frequency divider
C
: Carry flag
CF
CA, CB, Pu, PL
Cs, Su, SL
WI-W4, WI' -W4'
BM,BL
22:)-------------'
'--v--'
Oscillator
:
:
:
:
:
Carry F/F
Program counter
Stack register of program counter
Static shift register
RAM address register
75
............... .. ...... .......... .. .... .. ..... ..........
CMOS 4-:-Bit 1-Chip MicrOComputer
-~
•
~
~
~
SM-5A
~
~
~
~
~
Pin Oescription
Pin
K1 -K 4
a ,{J
0 11 -0 48
OSI-0S4
I/O
I
I
H},H2
0
-
0
-
R1 -R 4
0
Tp
T}, T2
ACL
OSCIN, OSCOUT
VM
Voo• GND
I
I
I
•
Type of circuit
Pull down
Pull up
,
Function
Acc-K 1 -K 4
Independent test possible
Output of cont!!nts of Wand W' registers; used for out-'
,put oLLCD segment
3,-state, level output possible; used for LCD common
output
R 1 -R 4-Acc, R 1 --·,Control output or alarm sound
output
For test (usually open)
For test (usually connected to GND)
Auto clear
For clock oscillation
Power supply for LCD driver
Power supply for logic circuit
Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Note 1:
•
Symbol
Voo
VM
VIN
Topr
To,,,
Rating
-3.5-+;0.3
-3.5-+0.3
VDo -0.3-+0.3
-5-+50
-55-+150
Unit
V
V
V
Note
1
'C
'C
The maximum applicable voltage on any pin with respect. to GND (GND=OV)
Operating Conditions
Parameter
Supply voltage
Supply voltage
Oscillator frequency
Symbol
Voo
VM
lose
Specified value
-3.3--2.7
Voo/2 (TYP.)
32.768 (TYP.)
Unit
V
V
kHz
....... -------~--SHARP'.-.----.-.--.--. ......... -
76
CMOS 4-Bit 1-Chip Microcomputer
•
SM-5A
(V oo =-3.0V±10%,GND=OV, Ta=25t)
Electrical Characteristics
Parameter
Input voltage
Input ,current
Output voltage
Current consumption
Oscillator start time
Note
Note
Note
Note
Note
Note
Note
Note
2:
3:
4:
5:
6:
7:
8:
9:
Symbol
VIH
VIL
IlHl
IlLl
IIH2
IlL2
VOHl
VOLl
VOH2
VOL2
VOA
VOB
Vc
lOA
Ios
Tosc
Applicable pins Kl, K2, K3, K4, a, fJ, ACL
Applicable pins Kl, K2, K3, K,
Applicable pins a, fJ
Applicable pins ~I,..QS'!......O~ OSI, all
Applicable pins RI, R2, R:l, RI
Applicable pins HI, H2
Mean current consumption at 32.768 kHz
Oscillating circuit constant
Conditions
MIN.
-0.6
TYP.
MAX.
Voo+0.6
15
1.5
1
1
VIN=OV
VIN =-3.0V
VIN=OV
V lN =-3.0V
IouT=30 pA to Voo
IouT= 10 pA to GND
IouT=100 pA to Voo
IouT= 100 pA to GND
-0.5
Voo+0.5
-0.5
-0.3
-1.8
-3.0
No load VM =-1.5V
In full-range operation
When system clock is stationary
-1.5
50
10
2
Voo+0.5
0
-1.2
-2.7
100
20
5
Unit
V
V
pA
pA
pA
pA
V
V
V
V
V
V
V
Note
2
3
4
5
6
7
pA
pA
8
s
9
~ -----VOH
----------VOA
------Voc
• Oscillator circuit
Oscillator circuit constant
Co=C G =15- 20.u F
---'--------SHARP------....-.-77
SM-SA
CMOS 4-Bit 1-Chip Microcomputer
•
Applications
1. Hand-held electronic calculator with clock
2.
3.
4.
5.
6.
7.
8.
9.
•
High-quality clock
Cash register
Hand-held electronic culculator with printer
pas terminal
Electronic scale
Game machine
Vending machine
Controller for electronic home appliances and
audio equipment
System Configuration (for LCD game machine)
AMI D·DD
U'UU
PM
LCD
DC voltage cutout O.02,uF
r---'-~-"------'--"""32.768kHz 20pF
0" OSConJ-....,..--i
Piezoelectric buzzer
=
Left
Right
-------~------SHARP----.-----
78
CMOS 4-Bit 1-Chip Microcomputer
SM-SL
•
CMOS 4-Bit I-Chip Microcomputer
Description
The SM-5L is a 4-bit single chip CMOS microcomputer with 1,827 bytes of ROM, 65 words of
RAM, a 15-stage divider and 72-segment liquid
crystal driver circuit. It is well suited for applications of low power hand-held equipment with
many liquid crystal display segments.
•
SM-5L
•
Pin Connections
~~;;"'MN_~
o
0 0 :.: :.: :.: :.: "
d Ie:. . uNz >>
'" <:!:I. ..:
Features
1. CMOS process
2. ROM capacity 1,827 X 8 bits
3. RAM capacity 65X4 bits
4. Instructions 51
5. Subroutine nesting 1 level
6. Input ports 6 bits
7. Output ports 42 bits
8. On-chip 15-stage divider with reset
(timer circuit)
9. Direct LCD driver circuit (3V, 112 duty, 112
bias and 72 segments MAX.)
10. On-chip crystal controlled oscillator
(32.768kHz)
11. Standby mode (2.5 pA current consumption)
12. Single power supply - 3V (TYP.)
13. Instruction cycle 61 ps
14. 60-pin quad-flat package
100 '"
ooooooozooooooo
....
..,
In
In
It)
IJ')
"
\CO
ID
t--
r--
l'-
I'-
Top View
79
CMOS 4-Bit ~1-Chip M i c r o c o m p u t e r ' SM:~5L
'
.....................................
.................,...........................
----~
•
Block Diagram
Segirient ______________________
Output
r -____________________
~A~
~
Segment
Output
~
Output
Port
'-----y--/ '--y---J
Symbol description
ALU : Arithmetic logic unit
Acc : Accumulator
CG : Clock generator
ACL : Auto clear
DIV : Frequency divider
C
: Carry F/F
80
'>--y-/
Oscillator
Asynchronous Input Port
Input
CA, CD, Pu, PL
Cs, Su, SL
WI-W4, WI' c--W.'
BM,BL
DDe
:
:
:
:
:
Program c.ounter
Stack register of program counter
Static shift resister
RAM address register
LCD supply voltage generator
CMOS 4-Bit 1-Chip Microcomputer
•
SM-5L
Pin Description
Pin
K1 -K 4
a,p
0 11 -0 48
OSI-0S4
0
HI> H2
0
-
-
RI -R 4
0
Tp
TI> T2
ACL
OSC IN , OSCOUT
VM
VDD , GND
I
I
I
•
Type of circuit
Pull down
Pull up
I/O
I
I
Function
Acc+-K 1 -K 4
Independent test possible '
Output of contents of Wand W' registers; used for output of LCD segment
3-state level output possible; usep for LCD common
output
R 1 - R4+- Ace, RI "'Control output or alarm sound
output
For test (usually open)
For test (usually connected to GND)
Auto clear
For clock oscillation
Power supply for LCD driver
Power supply for logic circuit
Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Note 1:
'.
Symbol
VDD
VIN
Topr
Tst2
Rating
-3.5-+0.3
VDD -0.3-+0.3
-5-+50
-55-+150
Unit
V
V
Note
1
"C
"C
The maximum applicable voltage on any pin with respect to GND (GND=OV)
Operating Conditions'
Parameter
Supply voltage
Oscillator frequency
Symbol
V DD
fose
Specified value
-3.3--2.7
32.768 (TYP.)
Unit
V
kHz
-"'-''--~''''''''---SHARP'-~---~---
81
SM-5L
CMOS 4-Bit 1-Chip Microcomputer
•
(Voo= -3.0V± 10%, GND=OV, Ta='25°C)
Electrical Characteristics
Parameter
Input voltage
Input current
Output voltage
, ,
Symbol
MIN.
Conditions
V oo +0.6
IIH!
15
IIL2
1
3
IIH3
V OHl
V OLI
louT=30
VOH2
louT=100 pAtoVoo
V OL2
IOlJT=100
IOllT= 10
pA
pA
-0.5
to Voo
Voo+0.5
-0.5
pA
pA
pA
V
Voo+0.5
-0.3
V
2
3
4
5
6
7
V
-1.8
-1.2
V
-2.7
V
8
Voc
VM
C 1 =C 2 =0.1
-1.5
-1.2
V
9
100
In Full-range operation
50
100
When system clock is stationary
2.5
5
pA
pA
10
2
5
s
11
10
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
V
V
to GND
No load V M= -1.5V
Note
V
to GND
pA
Unit
V
V 1L
V OB
Oscillation start time
MAX.
-0.6
V IH
V OA
Current consumption
, TYP.
pF
-1.8
Tosc
Applicable pins KI- K" a, fJ, ACL
Applicable pins KI - K,
Applicable pins a, fJ
Applicable pin ACL
Applicable pins ~I --::QSI, Oi, (i = 1- 4, j = 1 - 8)
Applicable pins RI- RI
Applicable pins HI, H,
Applicable pin VM
Mean current consumption at 32.768kHz
Oscillating circuit constant Ce, CD= 15-22pF
• Waveform of Hlo H2
-
__________ V""
~ ------ Vo "
------ Vile
• Oscillation circuit, Intermediate potential
generator circuit
wJ'
er
:1:.,
'T2 PF "t2PF
lr
OSC"
Cc
OSCOt:T
1rlDi~1 1
pC
o.l ttF o.l tt
-----------SHARP - . - - - - - - - - - - -
82
CMOS 4-Bit 1-Chip Microcomputer
•
SM-5L
Applications
1. Digital watch
2. Game machine
3. Controller for electronic home appliances and
audio equipment
4. Hand -held electronic calculator with clock
•
System Configuration
LCD
~tt==~---------
I r-
DC voltage
.-t-±",-"""-1cutout O.02}lF
.--...J.._--....:.....-.1.---,Crys~al
22 pF
HI aj; (36 lines) aSCol'TH-l11---.
22 pF
ascI~ '--'---R~
H2
Rt
ACL
SM-5L
VDD
Key matrix
- - - - . -.......... ------SHARP--~-------83
SM-SOO
CMOS 4-Bit 1-Chip Microcomputer
. . . . .. - . -_ _ _ _ _ _ _. . . .. -. . . .. - . -___
SM-500
•
_ _............._r......
~_~
CMOS 4-Bit I-Chip Microcomputer
Description
The SM-500 is a 4-bit single chip CMOS micro,computer with 1,197 bytes of ROM, 40 words of.
RAM, a 15-stage divider and 40-segment liquid
crystal driver circuits. It is well suited for applications of low cost, low-power hand-held equipment
with liquid crystal display.
•
Pin Connections
Cl
86686~668666
a
3
O~2
ose""
•
Features
1. CMOS process
2. ROM capacity 1,197X8 bits
3. RAM capacity 40 X 4 bits
4. Instructions 52
5. Subroutine nesting 1 level
6. Input ports 6 bits
7. Output ports 26 bits
' 8. Input/Output ports 8 bits
9. On-cp.ip 15-stage divider with reset
(timer circuit)
10. Direct LCD driver circuit (3V, 112 duty, 112
bias and 56 segments MAX.)
11. On-chip crystal controlled oscillator
(32.768kHz)
12. Standby mode (3 pA current consumption)
13. Single power supply -3V (TYP.)
14. Instruction cycle 61 ps
15. 48-pin quad-flat package
84
VillI
K.
K.
K2
<5 <5
ci! c>: c>: Ii ~ I...
"
0>.
~
d
<
~
Top View
CMOS 4-Bit 1-Chip Microcomputer
•
SM-500
Block Diagram
Segment Output
ROM
(1,197 X8)
'---y-/
I/O Port
'--y--/
ACL
Common Output
Oscillator
Symbol description
ALU
: Arithmetic logic unit
Acc
: Accumulator
ACL
: Auto clear
C
: Carry F/F
CA, CB, Pu, PL : Program counter
C~, Su, SL
: Stack register of program counter
CG
: Clock generator
DIV
: Frequency divider
WI - W4, WI' - W4' : Static shift register
BM, BL
Bp
KF
Ks
S
K
: RAM address register
: Backplate signal generator circuit
: Hit F/F
: 4-bit F/F
: 4-hit F/F (status register)
: Key input F/F
-..-.---------SHARP----------85
CMOS 4-Bit 1-Chip Microcomputer
•
8M-500
Pin Description
Pin
K1 -K 4
a,f3
I/O
I
I
0 11 -0 41
I/O
. OSI-OS4
110
0 12 -0 46
0
HI> H2
0
R1 -R 4
T
ACL
OSCIN , OSCOUT
VM
Voo, GND
0
I
I
•
Type of circuit
Pull down
Pull up
Function
Acc+-K 1-K 4
Independent test possible
Output of contents of Wand W' registers or input/out·
put to/ from KF register
Output of contents of Wand W' registers or i.nput/out·
put to/from Ks register
Output of contents of Wand W' registers; Used for
LCD segment output
3·state level output possible; used for LCD common
output
R1-R 4-Acc
For test (usually connected to GND)
Auto clear
For clock oscillation
Power supply for LCD driver
Power supply for logic circuit
Pull up
Pull down
Absolute .Maximum Ratings
?arameter
Pin voltage
Operating temperature
Storage temperature
Symbol
Voo
VM
VIN
VOUT
T_
T stg
Rating
-4.0-+0.3
Voo -+0.3
VDD -0.3-+0.3
VDo -0.3-+0.3
-10-+70
-55-+150
Unit
V
V
V
V
Note
1
t
t
Note 1: The maximum applicable voltage on aity pin with respect to GND.
•
Operating Conditions
Parameter
Supply voltage
Oscillator frequency
Symbol
Voo
VM
fose
Specified value
-3.3--2.7
V00/2 (TYP.)
32.768 (TYP.)
Unit
V
V
kHz
'-'-~'---------SHARP
86
...--...--,.--------
CMQS 4-Bit1-Chip Microcomputer
SM-SOO
(Voo=-3.0V±10%, GND=OV, Ta=25'C)
Electrical Characteristics
•
Parameter
Input voltage
Input current
Output voltage
Output Current
Current consumption
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Symbol
V IH
V1L
IHl
IH2
IL3
VOA
Vos
Voc
10HI
lOLl
IOH2
IOL2
103
104
lOA
los
Conditions
MIN.
-0.6
TYP.
Voo+0.6
15
3
1
V1N=OV
V1N=OV
VIN=Voo
-0.3
V M-0.3
No load VM=VOOI2
VoUT =-0.5V
VOUT=Voo+0.5V
VouT =-0.5V
VouT=Voo+0.5V
Vos=0.3V
Vos=0.5V
In full·range operation
When system clock is stationary
2: Applicable pins Kl-KI, a, p, ACL, 011-041, 051-0SI
3: Applicable pins Kl-K" 011-011, OSI-051
4: Applicable pin ACL
5: Applicable pins a, p
6: Applicable pins HI, H2
7: Applicable pins Oi, (i= 1-4, j=2-6)
8: Applicable pin Oll -041, OSI -051
9: Applicable pin Rl
10: Applicable pins Rz, R3, R,
11: Current consumption under no load conditions at fosc=32.768kHz
MAX.
V M+0.3
Voo+0.3
30
10
100
10
100
100
20
3
Unit
V
V
Note
pA
pA
pA
3
4
5
V
V
V
6
pA
pA
pA
pA
pA
pA
pA
pA
2
7
8
9
1-0
11
• H},H2 waveform
- IL
-u-J"C.--.====~=
U _______::::
Voc
• Oscillator circuit
c~fD~'"
Oscillator circuit constant
C"=C,,=22,,F
'-'-~-------""--'----SHARP ---~-----
87
.....
....,-.........,
.
...................--....,-......
OMOS 4-Bit l-Chip Microcomputer'
~-
•
. Applications
1. Digital watch
2. Game machine
3: pas terminal
4. Electronic scale
5. Controlle~ for electronic home appliances
and audio equipment
•
System Configuration (for digital watch)
R
12 H/24 H Cl-----i
KI~---------------'
K,!E-------------,
K31E-------,
1-----IOSC0 1:T
22pF
/3
R, R3 R. OSI OS2 a", 0 54
For
control
Mode switch
88
K.
CMOS 4-Bit 1-Chip Microcomputer
SM-510
•
CMOS 4-Bit I-Chip Microcomputer
Description
The SM-510 is a 4-bit single chip CMOS microcomputer with 2,772 bytes of ROM, 128 words of
RAM, a 15-stage divider and 132-segrnent liquid
crystal driver circuits. It is well suited for applications of low cost, low power hand-held equipment with liquid crystal display.
•
SM-510
•
Pin Connections
Q
~ :;~;.Q :..Q~:~:;..Q:~:
1
3
3
3
31
Features
L CMOS process
2. ROM capacity 2,772 X 8 bits
3_ RAM capacity 96X4+32X4 bits
4_ Instructions 49
5. Subroutine nesting 2 levels
6_ Input ports 6 bits
7_ Output ports 47 bits
8. On-chip 15-stage divider with reset
(timer circuit)
9. DirectLCD driver circuit (3V, 1/4 duty, 1/3
bias and 132 segments MAX.)
10. On-chip crystal controlled oscillator
(32.768kHz)
1 L Standby mode (10 pA current consumption)
12. Single power supply -3V (TYP_)
13. Instruction cycle 61 ps
14. 60-pin quad-flat package
~~-------SHARP"-------""'-~--""
89
CMOS 4-Bit 1-Chip Microcomputer
•
SM-510
Block Diagram
~
Seliment
________________________
~A~Output
________________________~
Display RAM
(32X4)
RAM
(96X4)
Segment
Output
Parallel
Output
Port
Test ' - - y - - / ACL Input
Parallel
Input
Port
Symbol description
ALU
: Arithmetic logic unit
Acc
: Accumulator
C
: Carry F/F
Pu, PM, PL : Program counter
Su, SM, SL : Stack register of program counter
Ru, RM, RL : Stack register of program counter
DIV
: Frequency divider
"---v-'
Voo
GND
W
BM, BL
Bp
H,L, Y
R
K
CG
'-v-'
Oscillator-
:
:
:
:
:
:
:
8-bit shift register
RAM address register
Backplate signal generator circuit
Hit F/F
2-bit F/F
Key input F/F
Clock Generator
- , - - - - - - - - - - - - - - S H A R P , - - . - . '......... ------------'"......-
90
CMOS 4-Bit 1-Chip Microcomputer
•
SM-510
Pin Description
Pin
K I -K 4
SA, PIN
aI-aIS, b I -b I6
bs
I/O
I
I
HI -H 4
0
SI- S8
Rr. R2
T
ACL
OSCIN, OSCOUT
Voo, GND
0
0
•
Type of circuit
Pull down
Pull up
Function
Acc-K I -K 4
Independent test possible
Output of contents of display RAM as LCD segment
signal
4-state level output possible; used for LCD common
output
Output of contents of W register
For piezo-electric buzzer direct drive
For Test (usually connected to V00)
Auto clear
For clock oscillation
Power supply for logic circuit
0
I
I
Pull down
Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Symbol
Voo
VIN
T oDr
T st•
Rating
-3.5-+0.3
V oo -+0.3
0-+50
-55-+150
Unit
V
V
t
t
Note
1
Note 1: The maximum applicable voltage on any pin with respect to GND.
•
Operating Conditions
Parameter
Supply voltage
Oscillator frequency
•
Symbol
Voo
fose
Unit
V
kHz
Specified value
-3.2--2.6
32.768 (TYP.)
(V oo =-3V±10%, Ta=25t)
Electrical Characteristics
Parameter
Input voltage
Input current
Output voltage
Output current
Current consumption
Note
Note
Note
Note
2:
3:
4:
5:
Applicable pins KI - K., PIN
Applicable pins ACL, BA
Applicable pins KI - K,
Applicable pin PIN
Symbol
VIllI
V ILI
VIII2
V OL2
IIII
IlL
VOH
VOL
VOA
VOB
Voc
Voo
Iso
ISIN
lOA
los
Conditions
MIN.
-0.6
TYP.
MAX.
Voo+0.6
-0.3
3
3
-0.5
VIN=OV
VIN=VOO
IOlJT=50 pA to Voo
IOUT=5 pA to GND
V oo =-3.0V
No load
VouT=-0.2V
VouT=Voo+0.2V
In full-range operation
When system clock is stationary
Note
Note
Note
Note
Voo+0.3
15
15
6:
7:
8:
9:
-0.3
-1.3
-2.3
-3.0
100
100
0
-1.0
-2.0
-3.0
60
10
Voo+0.5
0
-0.7
-1.7
-2.7
Unit
V
V
V
V
Note
pA
pA
4
5
V
V
V
V
V
V
pA
pA
pA
pA
2
3
6
7
8
9
Applicable pins SI -S8
Applicable pins al-al6, bl-blG, b8, HI-H,
Applicable pins RI, R2
Current consumption when fosc is 32.768kHz (TYP.) and
- 3.0V of V DISP is applied
--~------SHARP'--~---~--
91
GMQS:4-Bit 1-Chip Microcomputer
•
AppHcations
1. Hand-held electronic calcuator with multi-digit
display and clock
2. High-quality clock:
3. Handy game machine'
4. Equipment that. need mUltiple LCD display segments
•
System Configuration (Hand-held electronic caleuator with clock)
LCD
DC voltage cutout
O.02.uF
08C Ol"T I---D+ 0.6
-1
VI>D+ 0.6
-2.5
V",,+0.6
-2.5
V"D+0.6
-0.6
VI>D+ 0.6
-0.6
V I)Jl+0.6
600
50
90
11.2
32.768
150
Unit
Note
V
12
V
13,
V
14
pA
15
V
16
V
17
V
18
V
19
V
20
V
21
V
22
V
23
pA
pA
24
25
kHz
26
kHz
27
Applied to pins ACL, a, fJ, PE, QI, DIO,- DIO I, MP,- MP I
Applied to pins KEI-KE,
Applied to pin Cf
Applied to pins a, fJ, QI, KEI-KEI, Dial-Dia" MPI-MPI, F2 (during floating condition)
Applied to pins To-T'l
Applied to pins S,-S"
Applied to pins FI, F:l, F5
Applied to pins RI - R6, Q2, F I
Applied to pins R,-RJO
Applied to pins MPI-MPI, F2
Applied to pins DIOI-DIO,
Applied to pin Rf
No·load condition
No·load condition, VOll= -3.5V, internal CG with externally attached capacitance C= 15pF
Internal circuit with externally attached CG
Circuit with externally attached crystal oscillator
C,
pJ'
r
C
R=82kO
C=15pF
• When a ceramic oscillator is used, the operating
voltage VDD is limited to -5.5 to -4.5V.
• Oscillation starting voltage becomes larger than the
CR oscillation.
Cl=330pF
C2=150pF
Rl=lMO
R2 =5600
Ceram ic oscillator : KB R , (made by Kyocera Corp.)
Rl=200kO
CG=lOpF
Co=33pF
Crystal: KF-38G
(made by Kyocera Corp.)
~'-''---'---SHARP------'-'~-'--~
106
SM-525
CMOS 4-Bit 1-Chip Microcomputer
•
System Configuration (for VTR timer)
M
8.2V
U~
Fluorescent tube display
~~---r~:f::~::~::~:;::~C:::::::::::~---------o-30V
IkO
IkO
SM-525
KE,
-
KE, DIO, - DIO, F, - F; MP, - MP.
s.... --~
S
....
OSCOCT
GND
OSC"
Crystal
32.768kHz
c: ___ S
""
"'...."
00
~
Input signals ' - y - I Input signals
Control signals
1000
lkO
+5V
Key matrix
lkO
'----y---'
Input signals
.----.-...-.------'--SHARP ----------....-.----107
•. SM~530
CMQS 4-Bit 1-Chip .Microcomputer
SM-530
•
CMOS 4-Bit I-Chip Microcomputer
•
Description
Pin Connections
The SM-530 is a 4-bit single chip CMOS microcOlI).puter with 2,016 bytes of ROM, 88 words of
RAM, melody generator circuit and 96-segment
LCD driver circuit. It is well suited for low cost,
low power systems with many LCD segments.
•
Features
1. CMOS process
2. ROM capacity 2,016X8 bits
3. RAM capacity 64 X 4 + 24 X 4 bits
4. Instructions 49
5. Subroutine nesting 1 level
6. Input ports 8 bits
7, Output ports !i8 bits
8. Timer/Counter
(On-chip 15-stage divider with reset, 10second counter and 11100-second counter)
9. Direct LCD driver circuit (3V, 112 duty, 112
bias and 96 segments MAX.)
10. On-chip crystal controlled oscillator
(32.768kHz)
11. Melody generator circuit
12. Standby mode (1.5 p.A current consumption)
13. Single power supply -1.5V (TYP.)
14. Instruction cycle 91.6 p.s
15. 80-pin quad-flat package
108
Top Vi~w
/
CMOS 4-Bit 1-Chip Microcomputer
•
SM-530
Block Diagram
~
Segment Output
______________________________
________________________________
~A~
~
Segment
Output
ROM
(2,016 X 8)
RAM'
(4X16x4)
Pu(5)
PL(6)
Parallel
Output
Port
Battery
Alarm
Melody
Output
Parallel
Input
Port
12
'--v-'
Oscillator
Symbol description
ALU :
Acc
:
ACL :
C
:
Pu. PL :
Su, SL :
Arithmetic logic unit
Accumulator
Auto clear
Carry F/F
Program counter
Stack register of program counter
DDC
DIV
CG
BA
BM, BL
:
:
:
:
:
LCD supply voltage generator
Frequency divider
Clock generator_
Battery alarm circuit
RAM address register
109
..............-.---.... .............-:-----..... -........
,
SM~530
CMOS 4-Bit 1-Chip Microcomputer
-~
•
PIn Description
Pin name
Kl -K 4
KE l -KE 4
OlO- 0 4B
I/O
I
I
0
. Hl -H 2
0
F l -F 4
Sl-S4
So
BA
Test
ACL
OSC1N, OSC OUT
Voo, Vee, DDC
VM,GND
0
0
0
•
I
I
I
Circuit type
Pull down
Pull down
Pull down
Pull down
Function
Acc -Kl-K,j
Acc - KEl - KE4
Display RAM contents output as LCD segment signals
Tri-value output capability;
used for LCD common output
F l -F 4 -Acc
Sl-S4 - Acc
Melody output
For Iiatter,y alarm
For test (Connected to Voo normally)
Auto clear
For clock oscillation
LCD driv~ power supply
Power supply for logic circuit
Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Note 1:
Note 2:
Note 3:
•
Symbol
VM
Voo
VINl
V1N2
T oDr
T st•
Ratings
-2.0-+0.3
-4.0-+0.3
VM-0.3-+0.3
VoD -0.3-+0.3
-10-+60
-55'-+150
Unit
V
V
V
V
Note
1
1,2
1,3
1
t
t
The maximum applicable voltage on any pin with respect to GND.
Applied to pins Kl-Kl, KE1-KE1, Sl-S." Fl-FI, SO, Test, DDC, BA. ACL,
OSCIN, OSCollT
Applied to pins O;j(i= 1-4, j=O-B)HI, H2, Vc
Recommended Operating Conditions
Parameter
Supply voltage
Oscillation start voltage
Oscillator frequency
Symbol
VM
VOD
Vose
fose
Ratings
-1.2--1.8
-2.3--3.6
-1.4
32.768(TYP.)
Unit
V
V
V
kHz
-------~--SHARP.-.-.--·------
110
SM-S30
CMOS 4-Bit 1-Chip Microcomputer
•
(V M =-1.45-1.55V, V oo =-2.9--3.1V, Ta=25"C)
EI,ectrical Characteristics
Parameter
Input voltage
Input current
Boost output voltage
Output current
Current consumption
Oscillation start time
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
4:
5:
6:
7:
8:
9:
10:
11:
12:
13:
14:
15:
16:
17:
Symbol
V IH
V1L
IIHI
IIH2
V OO1
V OO2
10l
102
103
104
10HI
lOLl
IOH2
IOL2
IOH3
IOL3
105
100
los
Tosc
Conditions
V1N=OV
V1N=OV
VM =-1.55V, RL =5Mn
VM =-1.30V, RL =5Mn
Vos=0.5V
Vos=0.5V
Vos=0.5V
Vos=0.5V
VOLJT =-0.5V
VOllT =V M +0,5V
VOlJT =-0,5V
VOllT =V M +0.5V
VollT =-0,5V
VOllT =V M +0.5V
Vos=0.5V
During all operation
During system clock stop
MIN.
-0.5
TYP.
MAX.
VM +0.5
3
30
-2.80
-2.30
0.155
1.55
10
60
60
120
160
10
10
1.5
100
3
100
12
1.5
10
Unit
V
V
Note
pA
pA
5
6
V
V
7
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
pA
s
4
8
9
10
11
12
13
14
15
16
17
Applied to pins KI-K" KEI-KEI, Test, ACL, OSC'N
Applied to pins KI-K" KEI-KEI, ACL
Applied to pin Test
Applied to pin VDO
Applied to pins 0" (i= 1-4, j =O-B)
Applied to pins H" H,
Applied to pin DDC
Applied to pin Vc
Applied to pin SO
Applied to pins SI -S,
Applied to pin F I
Applied to pins F, - F I
Current consumption during 32.768kHz
Oscillation circuit constant, Cr;= 15pF, Cp=22pF
------------GND
~ ------- V"
--------V,,"
eH"H2 Waveform
Cc;=ISpF, C,,=22pF
e Oscillation circuit
e
Boost circuit
- - - - - - - - S H A R P - - - - - - -1". .-
j""
.....
.....
....................., ....,.....,
CMOS 4-8it 1-Chip Microcomputer
•
.............
..
......,~
Applications
1. Digital watch
2. Game machine
3. Digital clock
4. Controllers for home appliances and audio
equipment
5. Calculator with d9Ck
•
System Configuration Example (Caluculator watch)
.
Test
III
FJ
"
"8
F2
i:!0
F3
"...
F,
0
~
SO
R
Key matrix
112
................,.........
.
~.-.
..
'SM"':530
CMOS 4-Bit 1-Chip Microcomputer
SM-531
CMOS 4-Bit I-Chip Microcomputer
•
•
Description
The SM-531 is a 4-bit single chip CMOS microcomputer with 1,260 bytes of ROM, 52 words of
RAM, melody generator circuit and 80-segment
LCD driver circuit. It is well suited for low cost,
low power applications with many LCD segments_
•
Pin Connections
... z
~
uuQ~Qu
00
~""--MU)CJ)ZUCQU""_N
OOO:C:':oo,,<>Q>:':OO
1
3
3
3
31
Features
1.
2.
3.
4.
5.
6.
7.
8.
CMOS process
ROM capacity 1,260 X 8 bits
RAM capacity 32 X 4 + 20 X 4 bits
Instructions 45
Subroutine nesting 1 level
Input ports 6 bits
Output ports 42 bits
Timer/Counter
(On-chip 15-stage divider with reset, 1/100second counter)
9. Direct LCD driver circuit (3V, 1/2 duty, 112
bias and 80 segments MAX.)
10. On-chip crystal controlled cscillator
(32.768kHz)
11. Melody generator circuit
12. Standby mode (1.5 p.A current consumption)
13. Single power supply -1.5V (TYP.)
14. Instruction cycle 91.6 p.s
15. 60-pin quad-flat package
)
------------SHARP----..-,---113
CMOS 4-Bit 1-Chip
•
Microcomput~r
SM-531
Block Diagram
~
common{
Output
Segment Output
_____________________
____________________
A~
~
3
(2)----...r--"'L---~---...;;;..;...-------r----'
DDC
Segment
Output
ROM
(1.260xS)
RAM
(2X16X4)
PutS)
PL(6)
Parallel
Input
Port
\
Melody {
Output
9
'ID
'--v-'
VM
'-v--'
Test
Oscillator
GND
Symbol description
ALU
Acc
ACL
C
,Pu. PL
114
: Arithmetic logic unit
: Accumulator
: Auto clear
: Carry F/F
: Program counter
Suo SL
DDC
DIV
CG
BM. BL
:
:
:
:
:
Stack register of program counter
LCD supply voltage generator
Frequency divider
Clock generator
RAM address register
SM-531
CMOS 4-Bit 1-Chip Microcomputer
•
Pin Description
Pin name
K1 -K 4
•
KEh KE2
0 10 -0 49
110
I
I
0
Hh H2
0
SOh S02
Test
ACL
OSCIN, OSCO\JT
VDD , , Vee, DOC
V M, GND
0
I
I
Pul1 down
Function
Acc - K I -K 4
Acc - KEh KE2
Display RAM contents output as LCD segment signals
Tri·value output capability;
used for LCD common output
Melody output
For test (Connected to VM normal1y)
Auto clear
For clock oscillation
LCD driver power supply
Power supply for logic circuit
Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Note 1:
Note 2:
Note 3:
•
Circuit type
Pul1 down
Pul1 down
Symbol
VM
VDD
V INI
V IN2
Toor
T st"
Ratings
-2.0-+0.3
-4.0-+0.3
V M -0.3-+0.3
VDo -0.3-+0.3
-10-+60
-55-+150
Unit
V
V
V
V
Note
1
1
1,2
1,3
"C
"C
The maximum applicable voltage on any pin with respect to GND.
Applied to pins KI-KI, KEI, KE" Sal, SO" Test, DOC, ACL, OSCIN, OSCQlTT
Applied to pins O,j(i= 1-4, j=O-9), HI, H" Vc
Recommended Operating Conditions
Parameter
Supply voltage
Oscillation start voltage
Oscillator frequency
Symbol
VM
Voo
Vase
fose
Ratings
-1.8-1.2
-3.6-2.3
-1.4
32.768 (TYP.)
Unit
V
V
V
kHz
Note
4
Note 4: Oscillation ciruit constant CG= 15pF, CD= 22pF
Oscillation start. time : within 10 seconds .
.-----------SHARp.-..--------....-.
115
CMOS4-Bit 1-Chip Microcomputer
•
(V M =-1.45--:-1.55V,
Electrical Characteristics
Parameter
Input voltage
Input current
Boost output voltage
Output current
Current consumption
Oscillation starting time
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
5:
6:
7:
8:
9:
10:
11:
12:
13:
14:
15:
Symbol
VIH
VIL
IIHI
IIH2
VOOI
V002
101
102
103
104
105
100
los
Tosc
SM"531
Conditions
MIN.
-0.5
VIN=OV
VIN=OV
VM =-1.55V, RL-5MO
VM =-1.30V, RL =5MO
Vos=0.5V
Vns =0.5V
Vos=0.5V
Vos=0.5V
Vos=0.5V
During all operation
During system clock stop
Applied to pins KI-K" KEI, KE2" ACL, OSCIN
Applied to pins KI-K" KEI, KE2, ACL
Applied to pin Test
Applied to pin VOD
Applied to pins 0" (i= 1-4, j=0-9)
Applied to pins HI, H2
Applied to pin DOC
Applied to pin Vc
Applied to pins Sal, SO,
(::urrent consumption at 32.768kHz
Oscillation circuit constant CG=15pF, Co=22pF
TyP.
MAX.
VM +0.5
3
50
-2.80
-2.30
0.155
1.55
Ta=25"C)
Unit
V
V
Note
pA
pA
6
7
V
V
8
10
60
60
120
900
10
1.5
10
5
pA
pA
pApA
pA
pA
pA
9
10
II
12
13
s
15
14
• Hl,Hz Waveform
--------------GND
~---------
V~I
------------ VIlIl
• Oscillation circuit, Boost circuit
~---'--'---'-----SHARP
116
Voo=-2.~--3.1V;
.-------------,---
CMOS 4-Bit 1-Chip Microcomputer
•
SM-531
Applications
1. Digital watch
2. Game machine
3. Controllers for home appliances and audio
equipment
4. Calculator with clock
•
System Configuration (for melody alarm watch)
LCD
DC
voltage cutout
O.02,uF
~~--~--~~~--,
o
ij
(40Iines)
1/.1F
15pF
+
1.5 V
SM-531
V,,"
DDC
ACL
Vc
ACL
----------SHARP-------117
CMOS 4-Bit 1:"Chip Microcomputer
SM-S40
•
,
SM-S40
CMOS 4':'Bit I-Chip Microcomputer
Description
•
Pin Connections
The SM-540 is a 4-bit single chip CMOS microcomputer with 2,016 bytes of ROM, 128 words of
RAM, a 15-stage divider and a 256-segment liquid crystal driver circuit. It is well suited for
low power applications with 16 X 16 dot-matrix liquid crystal display_
•
Features
L CMOS process
2. ROM capacity 2,016 X 8 bits
3. RAM capacity 128 X 4 bits
4. Instructions 57
5. Subroutine nesting 2 levels
6. Input ports 6 bits
7. Output ports 55 bits
8. On-chip 15-stage divider with reset
(timer circuit)
9. Direct LCD driver circuit (4_5V; 1/8 duty,
113 bias and 256 segments MAX.)
10. On-chip clock generator circuit
1 L Standby mode (1 pA current consumption)
12. Single power supply -4_5V (TYP.)
13. Instruction cycle 16 ps
14. 60-pin quad-flat package
I
Vuu
5
ALM
-~-----~'---SHARP''''''-''''-'-'-~'-'-~
118
CMOS 4-Bit 1-Chip Microcomputer
•
SM-540
Block Diagram
Segment Output
ROM
(2,016X8)
Segment
Output
Backplate
Control
Common
Output
}-____~~I}-------~
Tone
Output
Oscillator
~
'--y-I
GND
Symbol description
ALU
Acc
C
P, PL
SCI, SC2
Segment
Driver
:
:
:
:
:
Arithmetic logic unit
Accumulator
Carry F/F
Program counter
Stack register of program counter
~--------'---SHARP
CG
DIV
BM, BL
S
X, SB
:
:
:
:
:
Clock generator
Frequency divider
RAM address register
Shift register
Temporary register
-----.-.-..-..-.-119
CMQS4-Bit 1-Chip Microcomputer
•
SM-S40
Pin Description
Circuit type
Pin name
K1-K 4
1/0
I
Ra
I/O
' Pull down
Rb
I/O
Pull down
al-al6
bl -bi6
H1-H s
SI-S4
RC
ALM
T
Sync
Rf
0
Vc
0
Function
Acc - K1 -K 4
R register output;
a F IF is\nput when R registerRa' is reset
R re~ister output;
f3 F IF is input when R register Rb is reset
0
Display RAM contents output as LCD segment signals
0
0
0
0
8·value output capability;used for LCD common output
S register output
R register output
For sound generator
For test (Connected to GND normally)
External clock input
System clock output
When system clock is running,
output at the same voltage as Vnn
LCD driver power supply
Power supply for logic circuit
I
I
Pull up
VDlSP
Vnn, GND
•
,
Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Ratings
Symbol
'-5,,5-+0,3
Vnn
-5.5-+0,3
VDlSP
VIN .' VM -0.3-+0.3
-5-+50
Toor
-'-55-+150
Tst~
Unit
V
V
'V
Note
1
1,2
1
"C
"C
Note 1: The maximum applicable voltage on any pin with respect to GND,
Note 2: VDlSP;;;;;VDD
•
Recommended Operating Conditions
Parameter
Supply voltage
Oscillator frequency
Symbol
Vnn
VDlSP
fose
Ratings
-5,5-+4.0
-5,5-+-3.0
120(TYP.)
Unit
V
V
kHz
--'-'-"'-~-,--SHARP------'-'---""""'-
120
CMOS 4-Bit 1-Chip Microcomputer
•
SM-540
(V DD =-4.5V, Ta=25'C)
Electrical Characteristics
Parameter
Input voltage
Input current
Output voltage
Output current
Current consumption
Note
Note
Note
Note
Note
Note
Note
Note
3:
4:
5:
6:
7:
8:
9:
10:
Symbol
VIH
VIL
IIH!
IlL!
IIH2
IIL2
VOA
VOB
Voc
VOD
VOE
VOF
10Hi
lOLl
10112
IOL2
IOH3
IOL3
IOH4
IOL4
IDA
IDs
MIN.
Conditions
TYP.
MAX.
0.6
Unit
V
V
20
1.5
3.0
1.5
pA
pApA
pA
-0.97
-3.12
-4.3
-1.95
-2.15
V
V
V
V
V
V
VDD +0.6
VIN=OV
VIN =-4.5V
VIN=OV
VIN =-4.5V
No load condition VDISP = -4.5V
No load condition VDlsp =-4.5V
No load condition VDlSP = -4.5V
No load condition VDISP- -4.5V
No load condition VD1SP= -4.5V
No load condition VDISP= -4.5V
VouT =-0.5V
VOUT=VDD+0.5V
VOUT= -0.5V
VOUT=VDD+0.5V
VouT=-0.5V
VOUT=VDD+0.5V
VOlIT =-0.5V
VOUT=VDD+0.5V
During operation
During system clock stop
Applied to pins Kl- K" R" Rb
Applied to pins Kl- K,
Applied to pins R" Rb
Applied to pins HI-H8, al-aI6, bl-bl6
Applied to pins SI--S,
Applied to pin RC
Applied to pin ALM
fose= 120kHz(TYP.) and VDlSP= -4.5V
-0.2
-1.38
-3.53
-2.35
-2.55
40
2
100
2
100
5
100
100
230
1
---------
3
4
5
6
pA
pA
pA
pA
pA
pA
pA
pA
pA
7
5
8
9
-rz-- - - -~A
10
eal-as,bl-bs Waveform
e Hl-Hs Waveform
~
Note
- VOA
-------VOB
------ -Voc
------------- - VOIl
Vo.'
----- - VOE
------- - V OF
- - - - - - - - - - - VIlIl
e Clock from external input pin SYNC
. 50kHz-144kHz
121
SM-540
.CMOS 4-Bit 1-Chip Microcomputer
....
~"""""""'''''''''''''_ _' I11!11!1••_''''_ _~''''~''''''''''''.-..r
•
Application
1. Game machine
.•
System Configuration (for LCD game)
16 x 16 dot matrix
LCD
K2 t - - - {
Hs
K3~--{
SM-540
K,iE---{
S,I-----I
S21-------'
Vc
lOOkO
R,
ViliSI'
BOkO
Piezoelectric
buzzer
2SC45B
122
CMOS 4-Bit 1-Chip Microcomputer
SM-550/SM-555
SM-550/SM-555
•
Description
The SM-550/SM-555 are 4-bit single chip
CMOS microcomputers with 1,024 bytes of ROM,
80 words of RAM, a15 stage divider and an event
counter.
They has the advantages of high-speed instruc·
tion cycle of 1.6 ,us(SM-550)/3.3 ,us(SM-555), 5
different interrupts, subroutine stack in the RAM
area, and byte-by-byte data transfer capability.
They are well suited for low power application
systems with many control ports.
•
•
CMOS 4-Bit I-Chip
Microcomputer
Pin Connections
E-
~~C-:~~~~~tO~~~
0.. 0.. 0.. 0.. E-C-'o..o.. 0.. 0..0.. 0..
~
r
Features
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CMOS process
ROM capacity 1,024 X 8 bits
RAM capacity 80 X 4 bits
Instructions 94
Subroutine nesting using RAM area
Input ports 4 bits
Output ports 8 bits
Input/Output ports 24 bits
Interrupt function
External interrupts 2
Internal interrupts 3
External ROM/RAM expandable
Timer/event counter
Serial interface 8 bits
Standby mode (10,uA current consumption)
Single power supply (2.7-5.5V)
Instruction cycle (MIN.)
1.6 ,us(SM-550)
3.3 ,us(SM-555)
48-pin quad-flat package
Top View
123
CMOS4-Bit 1""Chip Microcomputer
'.
Block Diagram
P
ROM
(1,024 X8l::
L
"'"
D
(:I
'1
Parallel
I/O
~)
Port
GND 7
Parallel
Output
Port
RESET 17
Parallel
I/O
Port
Symbol description
A,B
: Accumulators
ACL
: Auto clear circuit
ALU
: Arithmetic logic unit
CG
: Clo~k generator
DIV
: DivIder
H,L,D,E : General-purpose registers
IE
: Interrupt enable F /F
IFT,IFA,IFS
IFB,IFV : Interrupt requests
IME
: Interrupt mask enable F /F
124
Pl', PI.
PO - PB
PSW
RD, RE, RF
SB
SP
TC
TM
:
:
:
:
:
:
:
:
Program counters
Registers
Program status word regi'ster
Mode registers
Shift registers
Stack pointer
Count registers
Module registers
CMOS 4-Bit 1-Chip Microcomputer
•
Pin Description
Pin name
P7
PO, PI
P5,P8
P6
P4
P2,P3
INTA,INTB
TEST
RESET
~
CKj, CK z
OSC IN , OSCOUT
Voo , GND
•
Circuit type
Function
110
I
Pull up
4·bit parallel
110
Input-pull up
110 selectable by instruction
110
110
0
I
I
I
0
Input·pull up
Input-pull up
110 selectable using RF register
Serial interface input capability using RE register
4-bit parallel
Interrupt input
For test (Connected to GND normally)
Auto clear
System clock output
For system clock oscillation
For clock oscillation
Power supply for logic circuit
Pull up
Pull down
Pull up
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Output current
Operating temperature
Storage temperature
Note 1:
Note 2:
•
SM-550/SM-555
Symbol
Voo
VIN
VOUT
lOUT
Tope
T st "
Ratings
-0.3-+7.5
-0.3-V oo +0.3
-0.3-V oo +0.3
40
-20-+70
-55-+150
Unit
V
V
V
rnA
°C
°C
Note
1
1
1
2
The maximum applicable voltage on any pin with respect to GND.
Sum of current output from (or flowing into) output pin.
Recommended Operating Conditions
Parameter
Supply voltage
Crystal oscillator frequency
Basic clock
oscillator
frequency
Note 3:
Note 4:
Symbol
Voo
fose
SM-550
f
SM-555
f
Conditions
MIN.
2.7
-.
TYP.
MAX.
5.5
32.768
VDD =5V
VDD =3V
V[)[)=5V
V Do =3V
0.25
0.25
0.25
0.25
2.5
1
1.2
0.48
Unit
V
kHz
Note
3
MHz
4
MHz
Oscillation start time: within 10 seconds
Degree of fluctuation frequency: ± 30%
(tolerance of voltage fluctuation: ± 10%)
.....-.-.-..-.-------SHARP----------
125
SM-550/SM-555
CMQS 4-Bitt-Chip Microcomputer
(V DD =2.7-5.5V, Ta;=-20-+70"C)
Electrical Characteristics
•
Parameter
Symbol
VIHI
V ILI
V IH2
VIL2
Inptit voltage
Input current
lIN
10Hl
lOLl
IOH2
IOL2
Output current
IOH3
J
IOL3
lop
MIN.
0.7VDD
0
VDD -0.5
0
2
VIH=OV
IVoo =5.0V±10% 20
VOH =V DD -0.5V
50
VoL =0.5V
250
VOH =V DD -0.5V
100
500
VOL =0.5V
100
VOH =
V DD -0.5V IVoo =5.0V±10%
400
VoL =0.5V
0.5
IVoo =5.0V±10% 1.6
f=0.5 MHz, VDD =3.0V±10%
f=l MHz, V DD =5.0V±10%
Conditions
Current consumption
Standby
current
1ST
Note 1:
Note
Note
Note
Note
2:
3:
4:
5:
Note 6:
Note 7:
Note 8:
•
IVoo=3.0V±10%
IVoo=5.0V±10%
TYP.
MAX.
VDD
0.3VDD
VDD
0.5
200
200
Unit
V
V
V
V
,Note
pA
1
pA
pA
pA
pA
pA
1
2
3
4
5
mA
0.9
1
5
12
50
rnA
6
7
pA
I---
8
Applied to pins POO-P03, Plo-PI" P40-P43, P50-P53, P6o-P63, P8o-P83 (during input mode)
P7o-P73, INTA, INTB, RESET.
Applied to pins CK1, OSCIN, TEST.
Applied to pin CK2
Applied to pin '"
Applied to pins POO-P03, Plo-P13, P40-P43, P50-P53, P6o-P63,
P8o- P83 (during output mode)
P2o- P23, P30- P33
No·load, condition
No-load condition when crystal oscillation circuit is not operating. Connect OSCIN pin to GND.
No-load condition when crystal oscillation circuit is operating
Oscillation circuit
_ CKI
CK2
~
R
•
Clock oscillation circuit
External
The clock oscillation circuit is composed by connecting a resistance to the CKI and CK, pins. When
inputting an external' clock directly, input it
through CKI and leave CK2 open.
The system clock ( ~ ) used is the clock supplied
to CK, divided by 4.
126
R rCKI
fl,
1:J
CR oscillation
cIOCk-rl
Open
-tJ
External clock
SM-550/SM-555
CMOS 4-Bit 1-Chip Microcomputer
•
Applications
1. Controllers for various home appliances, audio equipment, office equipment, etc.
2. Vending machines
•
System Configuration (for mechanism controller)
+5V
~
u
Z
f-
::>
:>
U
Ul
0
Pulse input {
Control signals
INTA
INTB
P40
I
P43
POo
\
P0 3
Pl o
I
PI,
Z
-
-::<:
;;;u
0
~
U
Cl
Cl
>-
E-
o
I
14 13
£ ~ 0:Top View
------.-.----~--SHARP---~-~--
133
CMOS
•
4~Bit
t-Chip Microcomputer
SM-552/SM;.557
Block Diagram
P
L
D
Parallel
I/O
Port
ROM
(4, 096X81:: ," ~ )
RAM
(256X41:: '" r)
Parallel
Output
Port
OSC\\ 4
OSCo,"r 5
Parallel
I/O
Port
,
Parallel
Output Port
Symbol description
A,B
: Accumulators
ACL
: Auto clear circuit
ALU
: Arithmetic logic unit
CG
: Clock generator
DIV
: Divider
H,L,D,E : General-purpose registers
IE
: Interrupt enable F IF
IFT,IFA, IFS
IFB, IFV : Interrupt requests
IME
: Interrupt mask enable F IF
Pl', PL
PO-PB
PS W
RD,RE,RF
SB
SP
TC
TM
Parallel
I/O Port
:
:
:
:
:
:
:
:
Parallel
Input Port
Program counters
Registers
Program status word register
Mode registers
Shift registers
S tack point er
Count registers
Module registers
, . - . - - - - - - - - - S H A R P -~.-....-------.-.-134
'CMOS 4-Bit 1-Chip Microcomputer
•
SM-552/SM-557
Pin Description
Pin name
P7
PO,Pl
P5, P8
P6
P4
P9, PA, PB
P2,P3
INTA,INTB
TEST
RESET
~
Circuit type
Function
110
I
Pull up
4 -bit parallel
110
Input-pull up
110 selectable by instruction
110
I/O
110
0
I.
I
I
0
Input-pull up
Input-pull up
Input-pull up
I
110 selectable using RF register
Serial interface input capability using RE register
110 selectable by instruction
4-bit parallel
Interrupt input
For test (Connected to GND normally)
Auto clear
System clock output
For system clock oscillation
For clock oscillation
Power supply for logic circuit
Pull up
Pull down
Pull up
CK h CK 2
OSC IN , OSC OUT
Voo, GND
•
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Output current
Operating temperature
Storage temperature
Note 1:
· Note 2:
•
Symbol
Voo
VIN
VOUT
lOUT
Topr
TstK
Ratings
-0.3-+7.5
-0.3-V nn +0.3
-0.3-V no +0.3
40
-20-+70
-55-+150
Unit
V
V
V
rnA
Note
1
1
1
2
"C
·C
The maximum applicable voltage on any pin with respect to GND.
Sum of current output from (or flowing into) output pin.
Recommended Operating Conditic:ms
Parameter
Supply voltage
Crystal oscillator frequency
Basic clock
oscillator
frequency
Note 3:
Note 4:
Symbol
Voo
fose
SM-552
f
SM-557
f
MIN.
2.7
TYP.
MAX.
5.5
32.768
0.25
0.25
0.25
0.25
2.5
1
1.2
0.48
Unit
V
kHz
Note
MHz
r----
MHz
r--L
4
3
4.
VDD=5.0V
VDD=3.0V
135
CMOS 4;',Bit t-Chip M i c r o c , o m p u t e r S M - : 5 5 2 / S M - 5 5 7
'-1III!IIIIi~.II,I"...
, ......................~. . . . . . . . . . . . . . . . . . ..-...-.;~-"......_ , . " . . , . " , . "
•
E,lectrical Characteristics
Parameter
Input voltage
Input current
Symbol
lIN
lOLl
10112
IOL2
IOIl~1
Current consumption
Conditions
MIN.
0. 7Vuo
0
V DD .c:.0.5
VIlli
V ILt
'v III2
VIL2
10m
Output current
(V DD =2.7-5.5V, Ta=-2,0-+70t)
TYP.
0
VIN=OV
IVoo =5.0V±10%
VoIl =V Do -0.5V
VOL =0.5V
VoII =V oo -0.5V
VOL =Q.5V
VOII~
VDo -0.5V
I V",,=5.0V±10%
IOL3
VOL =0.5V
lop
f=0.5 MHzV Do =3.0V±10%
f=1 MHz V DD =5.0V±10%
1ST
Standby current
2
20
50
250
100'
500
100
400
0.5
I VoD =5.0V±10%
MAX.
V DD
0.3VDD
V DD
0.5
200
200
Unit
V
Vi
V
V
Note
pA
5
pA
pA
pA
/LA
pA
5
6
7
8
9
rnA
1.6
0.3
1
50
5
rnA
10
pA
~
11
Note 5: Applied to pins POo-PO" P1o-P13, P4o-P,43, P50-P53, P6o-P63, P8o-P83,
P90-P9, (during input mode) P7o-P73, INTA, INTB; RESET.
Note 6: Applied to pins CKI, OSC IN , TEST.
Note 7: 'Applied to pin CK 2
Note 8: Applied to pin '"
Note 9: Applied to pins POO-P03, P1o-P13, P4o-P43, P50-P53, P6o-P6"
P8o- P8, , P90- P9:1 , (during output mode)
PZo-PZ" P30-P3,; PAo-PA3, PBo-PB3
Note. 10: No·load condition
Note. 11: No-load condition when crystal oscillation circuit is operating
Note. 12: No-load condition when crystal oscillation circuit is not operating
•
Oscillation Circuit
CG=15pF, CD=22pF
•
Clock Oscillation Circuit
The clock osciUation circuit is composed by connecting a resistance to the CKI and CK, pins. When
inputting an external clock directly, input it
through CKI and leave CK2 open.
The system clock ( ¢ ) used is the clock supplied
to CK, divided by 4.
External
openi:j
C R oscillation
.---.----.-~------.-~SHARP
136
ciOCk-fi
External clock
- - - - - . - - - - . . - - ........
CMOS 4-Bit 1-Chip Microcomputer
•
SM-552/SM-557
Applications
1. Controllers for various home appliances, audio
equipment, office equipment, etc.
2. Vending machines
•
System Configuration (for mechanism controller)
+sv
PA3
\
INTA
Pulse input {
INTB
P4 0
\
P43
POo
\
Control signals
P03
..
-
SM -5521 SM -557
PA o
P93
\
P9 0
P83
Control signals
\
P80
P63
Plo
\
\
P6 0
} Input signals
Ph
.....-.~-.---- ........S H A . R P - - - - - - - - -
137
CMOS 4-Bit 1-Chip Microcomputer
S M- 5 E3
•
CMOS 4-Bit I-Chip ,Microcomputer
Description
The SM-5E3 is a 4-bit single chip CMOS microcomputer with 4,096 bytes of ROM, 256 words of
RAM, a 15 stage divider and an event counter. It
has the advantages of a high-speed instruction cycle of 1.6 ps, 5 different interrupts, subroutine
stack in the RAM area, and byte-by-byte data
transfer capability. It is well suited for low power application systems with many control ports.
•
Features
1.
2.
3.
4.
5.
6.
7.
8.
9.
SM-5E3
CMOS process
ROM capacity 4,096 X 8 bits
RAM capacity 256 X 4 bits
Instructions 99
Subroutine nesting using RAM area
Input ports 4 bits
Output ports. 16 bits
Input/Output ports. 48 bits
Interrupt function (External interrupts 2 and
internal interrupts 3)
10. External ROM/RAM expandable
11. Timer/event counter
12. Serial interface 8 bits
13. Standby mode (50 pA current consumption)
14. Single power supply (+2.7-+5.5V)
15. 1.6 ps instruction cycle (MIN.)
16. 80-pin quad-flat package
•
. Ph; Connections
P21 I
P22 2
P2, '
P3. •
P3, 5
P32 6
P33 7
P40 8
P41 9
P42 ,.
P4,lI
PSo 12
P5,13
PS2 14
P53 15
P60 "
P6,17
P62 18
P63 19
TEST
P70 21
P71 22
P72 23
P7" ,.
2.
Top View
- . - - - - - - - - - S H A R P . - . . . . - . - - . - - - - - - -.........
138
CMOS 4-Bit 1-Chip Microcomputer
SM-563
•
SM-563
CMOS 4-Bit I-Chip Microcomputer
Description
•
Pin Connections
The SM-563 is a 4-bit single chip CMOS microcompter with 4,096 bytes of ROM, 160 X 4 bits of
RAM, timer/event-counter and mUltiplex interrupt.
It is best suited to controllers of application systems to drive multi LCD segments.
•
Features
1. CMOS process
2. ROM capacity 4,096 X 8 bits
3. RAM capacity 160X4 bits
(including 32 X 4 bits for display)
4. Instructions 93
5. Subroutine nesting using RAM area
6. Input ports 4 bits
7. Input/Output ports 11 bits
8. Timer/event-counter
9. Interrupt functions 5
External interrupt
Serial 110 interrupt
Timer/event-counter interrupt
f. signal interrupt
Divider overflow interrupt
10. Serial interface 8 bits
11. Standby mode
12. Direct LCD driver circuits (1/4 duty, 113 bias
and 128 segments (MAX.))
13. Insturuction cycle 6.67 ps (MIN.)
14. Single power supply (2.7-5.5V)
15. 64-pin quad-flat package
Top View
--'---'---SHARP'--'---'--~--
139
CMOS 4-Bit 1-Chip Microcomputer
•
SM-563
Block Diagram
SP
ROM
(4,096XS)
RAM
(12SX4 )
Test
PU
RESET
Clock Output
Parallel
I/O
Port
H
D
PL
R4
R5
R6
R7
RD
RE
RF
2
Segment
Output
,
Common
Segment Output
Output
Symbol description
:
A,B
:
ACL
:
ALU
:
BR,DS
:
CG
:
DIV
:
D,E,H,L
:
HC
:
IE
IFA,IFB
IFS,IFT,IFV:
Accumulators
Auto clear
Arithmetic logic unit
Common signal control F/F
Clock generator
Divider
General-purpose registers
Common signal circuit
Interrupt enable F /F
: Interrupt mask enable F F
IME.
: Registers
PI-P3
Program counters
PL,PU
: Program status word register
PSW
R4- R7
: General- purpose registers
RD,RE,RF: Mode registers
SB
: Shift register
SP
: Stack pointer
TC
: Count register
: Module register
TM
Interrupt requests
-------~---SHARP-~-~-~---
140
SM-563
CMOS 4-Bit 1-Chip Microcomputer
•
Pin Description
Function
Acc +- PO O-P0 3
I/O selectable by instruction
I/O selectable individually
Sound output only when P2 3 pin is used for output
Serial interface input capability using RE register
Display RAM contents output as LCD segment signals
4·value output capability; used for LCD common output
For test (Connected to GND normally)
Auto clear
System clock output
For system clock oscillation
For clock oscillation
LCD driver power supply
Power supply for logic circuit
Circuit type
Pin name
PO O-P0 3
P1 0 -P1 3
I/O
I
I/O
Pull up
Pull up
P2 0 -P2 3
I/O
Pull up
P3 0 -P3 3
SO-S31
H1-H 4
TEST
RESET
I/O
0
0
I
I
0
Pull up
Pull down
Pull up
'"
CK[, CK 2
OSC'N. OSC OUT
Vos P• VOA• VOB
Voo• GND
•
'Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Output current
Operating temperature
Storage temperature
Symbol
Voo
VosP
VIN
VOUT
lOUT
Toor
T sto
Ratings
-0.3-+7
-0.3-+7
-0.3-V oo +0.3
-0.3-V oo +0.3
20
-20-+70
-55-+150
Unit
V
V
V
V
rnA
Note
1
1
1
2
"C
"C
Note 1: The maximum applicable voltage on any pin with respect to GND.
Note 2: Sum of current output from (or flowing into) output pin.
•
(V nn =2.7-5.5V)
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
Voo
VosP
Basic clock oscillator
frequency
f
Instruction cycle
t
Crystal oscillator frequency
Conditions
VnD=4.5~5.5V
VDD =4.5-5.5V
fosc
MIN.
2.7
2.7
250
250
6.6
2
TYP.
32.768
MAX.
5.5
Voo
600
2000
16
16
Unit
V
V
Note
kHz
3
/-,s
kHz
Note 3: Degree of fluctuation frequency: ±30%
• Oscillation circuit
CKI
CK2
~
R
CG=15pF. CD=22pF
....--.-~---------SHARP
------------------141
SM-:563
CMOS 4-Bit 1.-Chip Microcomputer
•
(Voo=2.7-5.5V, Ta=-20-+70t),
Electrical Characteristics
Parameter
Symbol
VIHI
V ILl
VIHZ
VILZ
Input voltage
Input cu'rrent
'IIH
IOHl
, lOLl
10HZ
IOLZ
Output current
IOH3
IOL3
Rc
Rs
VI
Vz
V3
V4
lop
Output impedance
Output voltage
Current consumption
Note
Note
Note
Note
Note
1ST
Conditions
f=600kHz, Voo=3.0V
Vosp=3.0V
Standby mode
Voo=3.0V
142
I
;
Applied to pins HI-HI
Applied to pins SO-S31
Applied to pins H2-Hl, So-S;"
No·load condition
No·load condition when bleader resistance is ON
No·load condition when bleader resistance is OFF
MAX.
Voo
0.3Vpo
Voo
0.5
200
200
250
Unit
V
V
V
V
Note
p.A
1
p.A
p.A
p.A
p.A
1
2
3
4
p.A
5
rnA
2.7
1.7
0.7
0
Vosp=3.0V
No·load
COA=lpF, COB=lpF
Note 9:
Note 10:
Note 11:
TYP.
5
10
1: Applied to pins POO-POI, RESET
Plo- Ph, P2o- P23, P30-P32 (during input mode)
2: Applied to pins CKl, Test, OSCIN
3: Applied to pin CK2
4: Applied to pins Plo- Ph (during output mode)
5: Applied to pins P2o- P23, P3o- P32 (during output mode)
Note 6:
Note 7:
Note 8:
MIN.
0.7Voo
0
Voo-0.5
0
20
V1N=OV
I VDD =4.5-5.5V
2
VOH =V DD -0.5V
50
250
VOL =0.5V
VoH =V oo -0.5V
5
VOL ;:0.5V
500
VOH =
400
Voo-0.5V I VDD =4.5-5.5V
100
1.6
VOL =0.5V
I VDD =4.5-5.5V
0.5
2
1
i
0.4
15
8
20
40
3
2.3
1.3
0.3
1.5
40
20
kn
kn
V
V
V
V
rnA
p.A
6
7
8
9
10
~
11
CMOS 4-Bit 1-Chip Microcomputer
•
Applications
•
The instruction cycle of the SM563. is fast and
the unit operates on little power, and therefore it is
ideal for use as a controller with a liquid crystal
display in a wide range of hand-held equipment
and home appliances.
•
SM-563
Applications Example
Portable devices, auto dialers, sphygmomano·
meters, thermometers, pulsemeters, radio controllers, cameras, home appliances, various timers,
VTR timers, home security system, pocket games
System Configuration
Key matrix
-.-------SHARP-------143
CMOS4-Bit 1-Chlp Microcomputer
5 M- 57 2
•
Description
.SM.;572
CMOS 4-Bit I..Chip MicrOC()mputer·
I
•
Pin Connections·
The SM-572 is a 4-bitsingle chip CMOS microcomputer with 2,032X9 bits of ROM, 128X4 bits
of RAM, 8 bits A/D converter and timer/counter.
It is best suited for applications requiring A/D
circuits.
•
Features
1. CMOS process
2. ROM capacity 2,032 X 9 bits
3. RAM capacity 128 X 4 bits·
4. Instructions 93
5. Subroutine nesting 6 levels
6. Input ports 8 bits
7. Output port . 1 bit
8. Input/Output ports 40 bits
9. Timer/counter
8-bit counters 2
10. Interrupt function
External interrupt 2
Timer interrupt 2
11. A/D converter 8 bits
Conversion time 32 ps(MIN.)
12. Single power supply (2.7-5.5V)
13. Instruction cycle 2 ps (MIN.)
14. 60-pin quad-flat package
....------,---SHARP"-~--------
144
CMOS 4-Bit 1-Chip Microcomputer
•
SM-572
Block Diagram
.
Input/Output Port
V,w
Val.
ROM
I 2,032 x9 )
Input
Port
MPX .
•
Input Output Port
Symbol description
ALU :
X
:
B
:
C
:
PC
:
SP
:
CG
:
MPX.:
A/D :
Arithmetic logic unit
X register
RAM address, register
Carry F/F
Program counter
Stack pointer
System clock generator
Multiplexer
A D convertor and Comparator unit
Ace
:
SR
RO,Rl,R2,R3:
DIV
Accumulator
Stack register
Latch
Divider
~'-'-'-----SHARP~'-''------'--'--
145
SM-572
CMos 4-Bit 1-Chip Microcomputer
•
Pin Description
Pin name
KC o -KC 3
110
I
KI, KH
KT,KL
I
ZO-ZI5
110
PO-P 3
1/0
QO-Q:l
110
RO,Rl,R2
F
T
ACL
.fOUT
Circuit type
3 states
110
0
I
I
0
Pull down
Pull down
CLl> CL 2
OSC IN , OSC OliT
VRH , VRL
Voo , GND
•
Function
Acc +- KC o - KC:l or AID conversion analog input
Acc +- KI, KH, KT, KL
KI ~ (IF flag set), KH +- (HF flag set),
KT +- (External timer signal input)
Z registor contents output;Can be tested individually
Reset ZF IF ",hen used as input pins
Acc - . PO-P:l
QO-Q:l +- Acc
Reset QF IF when used as input pins
RO, Rl, R2 +- Acc
Reset RF IF when used as input pins
Sound output or 1 bit output
For test (Connected to GND normally)
Auto clear
System clock output
For system clock oscillation
For clock oscillation
AID conversion standard power supply
Power supply for logic curcuit
Absolute Maximum Ratings
Parameter
Supply vo'tage
Input voltage
Output voltage
Output current *
Operating temperature
Storage temperature
Symbol
Vo~
VIN
VOUT
lOUT
T~pr
T".
Ratings
-0.3-+7.5
-0.3-V nn +0.3
-0.3-V nn +0.3
30
-10+70
-55+150
Unit
V
V
V
rnA
'C
'C
·Source current from output pin or sum of sync current.
•
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
Vno
Ratings
2.7-5.5
4-0.2 (Voo=5V)
2-0.2 (Voo=3V)
Unit
V
System oscillator frequency
fCL
System clock frequency
fs
500-50 (VDD=5V)
250-50 (V DD =3V)
kHz
Timer clock frequency
fosc
32.768 (TYP.)
kHz
146
KfHz
CMOS 4-Bit 1-Chip Microcomputer
•
SM-572
(V oo =2.7-5.5V,.Ta=-20-+70"C)
Electrical Characteristics
Parameter
Symbol
Input voltage
Input current
Output current
lUll
V1N=Von
11112
V1N=Vnn
10111
VOII =V IlD -O.5V
lOll
Vou=0.5V
IOL2
VolI =0.5V
1011
10112
ACL input pulse width
t ACL
V Illl rise time for
the internal ACL operation
tV1l1l
IA
Current consumption
1ST
Note
Note
Note
Note
Note
1:
2:
3:
4:
5:
Note
Note
Note
Note
Note
Note
Note
Note
6:
7:
8:
9:
10:
11:
12:
13:
Conditions
VUII
V 1LI
V IJI2
V1L2
VDD =5.0V±10%
VDIl =3.0V±lO%
VDIl =5.0V±1O%
VDIl =3.0V±lO%
VDIl =5.0V±lO%
VDIl =3.0V±lO%
VDI)=5.0V±lO%
VDIl =5.0V±lO%
VOII =V IlIl -0.5V
VolI =0.5V
Vllo =5.0V±lO%
VDIl =3.0V±10%
VDIl =5.0V±lO%
VDD =3.0V±10%
VDIl =5.0V±lO%
fs=500kHz
VDD =73.0V±10%
VDD =5.0V±lO%
fs=100kHz
VDD =3.0V±lO%
VDD =5.0V±10%
OFF mode
VDD =3.0V±lO%
VDD =5.0V±10%
VDIl =3.0V±10%
VDD =5.0V±10%
Hold mode
VDD =3.0V±10%
VDD =5.0V±'10%
VDD =3.0V±lO%
MIN.
0.7Voo
0
Von -0.5
0
80
20
8
2
1
0.4
25
10
1
0.4
200
200
1
TYP.
MAX.
300
90
25
8
Voo
0.3Voo
Voo
0.5
800
300
100
35
50
1.5
1
0.5
0.3
5
3
50
30
400
100
600
200
Unit
Note
V
1
V
2
p.A
3
p.A
4
rnA
5,6
p.A
5
rnA
6
p.A
7
ps
13
ms
14
rnA
8
flA
9
p.A
10
p.A
11
p.A
12
,
Applied to pins KH;KL, KI, Pa-Po, Q3-QO, R03-ROo, R13-Rlo, R23-R20, R33-R32, KC:,-KCo
Applied to pins Z[5-Z0, CL[, OSCIN/KT, ACL
.
Applied to pins Q3-QO, R03-ROo, R1:J-Rlo, *R23-R20, *R3a-R30, *ZI5-Z0
Applied to pin ACL
Applied to pins Q3-QO, R03-ROo, Rl:l-Rlo, R23-R20, R33-R3o, Z15-Z0
(*Jf CMOS buffer is specified for mask option, Note 6 applies to these pins.)
Applied to pins P3- Po, F, fOliT
Applied to pin CL 2
No·load condition
When the OSC1N/KT pin is connected to GND and in no· load condition.
When the timer clock crystal oscillation circuit and timer 1 are operating and in no·load condition.
When the OSClN/KT pin is connected to GND and in no·load condition, f,= 100kHz
When the OSClN/KT pin is connected to GND and in no·load condition, f,=500kHz
tACL is the ACL input pulse width required to cause ACL to operate when Von has completely risen.
VDD _______~~~,----------VDD
W
GND
tVDD
ACL __________~VDD - O.5V
tACL
Note 14: tVDD is the power supply rise time necessary for the built·in ACL to operate (ACL input pin is connected to GND).
147
....................,.-...;
•
..............................-................
'SM";'S72
CMOS 4.,.Bit 1-Chip Microcomputer
~
Oscillation Circuit (values for referen'ce)
(a) System clock frequency generating circuit (example 1)
(1)
(2)
400kHzoscillation
Oscillator. KBR-400B : Made' by Kyocera
Rr=IMO
Corp.
Rd=5600
CI=330pF
C'2=330pF
2 MHz oscillation
C~LI
CL2 Oscillator KBR-2.0MS : Made by Kyocera
Rr
C2
I
[]
Rr=lMO
I
Corp.
Rd
Rd=8200
Cl =33pF
C2
C2 =33pF
'- (b) System clock frequency generating circuit (example 2)
R-fcLCharacteristics
VDD-fcL Characteristics
N
::t:
N
i1
2
Rr=lOkO
»
"~
--
g.
~ 0.5
§ 0.4
]
Rr=82kO
0.3
~
.,
"
2
.."».
.&
J:: 0.5
c
.~
\\
~ootv
\Joo=3
V
~\
1;;
=
. CL 2
110
110
110
110
110
Pull
Pull
Pull
Pull
I
Circuit type
down *1
down* 1
down/open drain * 2
down*1
Pull down
V DD , GND
Function
Acc - RO o-R0 3 , RO o-R0 3 <-- RAM
Ace - Rl o-R1 3 , Rl o-R1 3 <-- RAM
Acc - R2 o-R2 3 , R2 o -R2 3 <-- RAM
Acc - R3 0 -R3 3 , R3 0 -R3 3 <-- RAM
Auto clear
For system clock oscillation
Power supply for logic circuit
*1 Mask option; Open drain 110 or CMOS output selectable
* 2 Mask option
-----~.--.---....----SHARP -----.----~-
(
153
CMOS 4-Bit 1-Chip Microcomp~ter
•
SM-590
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Source output current sum
Sync output current sum
Operating temperature
Storage temperature
•
Symbol
Ratings
-0.3-+7.5
Voo
-0.3-V oo +0.3
' VI
-0.3-V oo +0;3
Vo
120
:ZIoH
:ZIoL '
20
-10-+70
T@f
-55-+150
T stg
Unit
V
V
V
mA
mA
'C
'C
Recommended Operating Conditions
Parameter
Supply voltage
Command execution time
•
Symbol
Voo
tSYS
Conditions
3V±0.5V
5V±0.5V
MIN.
2.5
4
1
TYP.
MIN.
TYP.
MAX.
5.5
50
50
Unit
V
MAX.
50
50
6.3
6.3
Unit
/Ls
Clock Input Signal AC Characteristics
Parameter
Clock rise time
Clock fall time
Clock pulse width
Symbol
tr
tf
tL
tH
Conditions
Voo =2.5-5.5V
Voo =2.5-5.5V
Voo=5V±0.5V
Voo=3V±0.5V
0.08
0:45
ns
/LS'
Note: When external clock is input
•
(Voo=2.7V-5.5V. Ta=-10'C-+70'C)
Electrical Characteristics
Parameter
Input voltage
Input current
Symbol
Vun
V1LI
Vm2
V1L2
V1L3
e:.V 1
Imi
1m2
IAI
Current consumption
IA2
1ST
154
Conditions
MIN.
0.7Voo
0
Voo-0.5
0
Voo =5V±10%
0.7
1.1
Voo=5V±lQ%
15
Voo =3V±10%
VIN=VOO
V oo =5V±10%
70
Voo=3V±1O%
V1N=VOD
Voo=5V±1O%
tsys=2 f1S VDo =5V±10%
Voo =3V±10%
tSys= 10 f1s
Voo =5V±10%
Standby mode
TYP.
1.4
2
70
250
7
20
1
100
200
1
MAX.
Voo
,0.3V oo
Voo
0.5
2.1
3<.1
200
750
20
60
3
200
500
;, 2
Unit
V
V
V
V
V
V
Note
/LA
1
/LA
4:
1
2
3
mA
/LA
/LA
5
CMOS 4-Bit 1-Chip Microcomputer
SM-590
Output current
10 (MIN.)
~n
Pin
ROo
R0 1
R0 2
R0 3
RIo
Rl1
R12
R13
R20
R21
R22
R23
R3 0
R3 1
R3 2
CL 2/R3 3
Mask option
switch number
(Ta= -lO·C - +70·C)
IOH (rnA)
IOL (rnA)
Voo =5V±10% Voo=3V±10%
VoL=Oo4V
VoH =V oo -2V VOH =V OD -0.5V Voo =5V±10%
10
1
1.6
10
1
1.6
10
1
1.6
10
1
1.6
10
1
1.6
10
1
1.6
10
1
1.6
10
1
1.6
4
0.5
4
0.5
4
0.5
4
0.5
4
0.5
1.6
10
1
1.6
10
1
1.6
004
3
1
0.15
0.6
0.8
0.8
IOL (pA)
VOL =Oo4V
Voo =5V±10%
15
15
15
15
15
15
15
15
15
15
15
15
15
15
0.8
15
lIE
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
Note'
lIE
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
6
7
0.3
2
1
Note 1: Applied to pin ROo, ROI, RO" R03, RIo, Rh, Rh, Rh, R20, R2l, R2" R23, R30, R3l, R3,
. Note· 2: Applied to pins ACL, CL I
Note 3: Applied to pin R2, (when standby cancel signal is input)
t:. VI=VIH3-VIL3 (See the SM590 programming manual for details)
Note 4: Applied to pin ACL
Note 5: No-load condition
Note 6: When the contents of the R latch is output to the R3, pin_
Nate 7: When the clock input to the CLI pin is output from the R3, pin_
lIE: VDD=3V±1O%
155
SM-591
CMOS 4-Bit 1-Chip Microcomputer
SM-591
•
CMOS 4-Bit I-Chip Microcomputer
•
Description
Pin Connections
The SM-591 is a 4-bit single chip CMOS microcomputer with 1,016 bytes of ROM, 56X4 bits of
RAM.
It is best suited for use in a compact controller, a
system subcontroller and other various application
systems.
•
Features
1. CMOS process
2.
3.
4.
5.
6.
ROM capacity 1,016 X 8 bits
RAM capacity 56 X 4 bits
Instructions 41
Subroutine nesting 4 levels
Input/Output ports 15 bits (MAX.)
Available for use as lOrnA output port 10 bits
(MAX.) by mask option
(RO o-R0 3, R1 o-R1 3 , R3j, R3 2)
7. Standby mode
8. Single power supply (2.5 - 5.5V)
9. Instruction cycle 1 f.1S
ROo
1
10'~P~a-c-ka-g-e-'~I~/O~p-(o-rt-s-
16DIP
18DIP
20DIP
11 bits
13bits
15bits
RO" ,
R3,,/CL2 6
Top View
-'-'---'-'--SHARP~-------~-----
156
CMOS 4-Bit 1-Chip Microcomputer
•
SM-591
Block Diagram
Parallel I/O
Parallel Out/Oscillator Oscillator
, . -_ _ _ _ _ _ _ _ _ _.-J.4 _ _ _ _ _ _ _ _ _ _...,
Voo
RAM
(56X4)
ROM
(1016X8 )
ACL
Symbol description
A('(' : Accumulators
ALU : Arithmetic logic unit
: RAM address register
B
: .Carry F/F
C
: Clock generator
CG
•
GND
PC
RO-R3
SP
SR
X
: Program .counter
Register
: Stack pointer
: Stack register
: Temporary register
Pin Description
Pin name
RO o-R0 3
Rio-Ria
R2 o-R2 3
R3 o-R3 3
ACL
CLl> CL 2
I/O
I/O
I/O
I/O
I/O
I
Pull
Pull
Pull
Pull
Pull
Circuit type
down*l
down*l
down/open drain * 2
down* 1
down
V DD, GND
Function
Ace - ROo-RO:l , ROo-RO a +- RAM
Acc -Ri o-Ri 3 , Ri o-Ri 3 +- RAM
Acc - R2 o-R2 3 , R2 o-R2 3 +- RAM
Ace - R3 0 -R3 3 , R3 0 -R3 3 +- RAM
Auto clear
For system clock oscillation
Power supply for logic circuit
* 1 Mask option; Open drain 110 or CMOS output selectable
*2 Mask option
-.-----------SHARP.-..-.-------157
SM:.591
CMOS 4-Bit 1-Chip Microcomputer
•
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Source output current sum
_ Sync output current sum
Operating temperature
Storage temperature
•
Symbol
Voo
V,
Vo
-IIoHIIoL
Toor
T st•
Ratings
-0.3-+7.5
-0.3-V oo +0.3
-0.3-V oo +0.3
120
20
-10-+70
-55-+150
Unit
V
V
V
rnA
rnA
t
t
Recommended Operating Conditions
Parameter
Supply voltage
Command execution time
•
Symbol
Voo
Tsys
Conditions
3V±0.5V
5V±0.5V
MIN.
2.5
4
1
TYP.
MIN.
TYP.
MAX.
5.5
50
50
Unit
V
MAX.
50
50
6.3
6.3
Unit
ps
Clock Input Signal AC Characteristics
Parameter
Clock rise time
Clock fall time
Clock pulse width
Symbol
tr
t(
tL
tH
Conditions
Voo =2.5-5.5V
Voo =2.5-5.j'iV
Voo=5V±0.5V
Voo=3V±0.5V
0.08
0.45
ns
ps
Note: When external clock is input
•
(Voo=2.7V-5.5V, Ta=-10t-+70t)
Electrical Characteristics
Parameter
Input voltage
Input current
Symbol
Vnll
V'LI
VIII 2
V'L2
V'L3
6V,
Inll '
IIII2
IAI
Current consumption
IA2 '
1ST
158
Conditions
MIN.
0.7Voo
0
Voo-0.5
0
Voo =5V±10%
0.7
Voo =5V±10%
1.1
15
Voo =3V±10%
V'N=V OO
Voo =5V±10%
70
Voo =3V±10%
V'N=V OO
Voo =5V±10%
tsys=2 ps Voo =5V±10%
Voo =3V±10%
tSys= 10 pA
Voo =5V±10%
Standby mode
TYP.
1.4
2
70
250
7
20
1
100
200
1
MAX.
- Voo
0.3Voo
Voo
0.5
2.1
3.1
200
750
20
60
3
200
500
2
Unit
V
V
V
V
V
V
Note
pA
1
pA
4
1
2
3
rnA
pA
pA
5
CMOS 4-Bit 1-Chip Microcomputer
SM-591
Output current
10 (MIN.)
~
Pin
ROo
R0 1
R0 2
R0 3
RIo
Rl1
R12
R13
R20
R21
R22
R23
R3 0
R3 1
R3 2
CL 2 /R3 3
Mask option
switch number
IOH (rnA)
IOL (p. A)
VOL =O.4V
IOL (rnA)
VOL =O.4V
Voo =5V±10% Voo =3V±10%
VoH =V oo -2V VoH =V oo -O.5V Voo =5V±10%
10
1
1.6
1
10
1.6
1
1.6
10
10
1
1.6
10
1
1.6
10
1
1.6
10
1
1.6
10
1
1.6
4
0.5
4
0.5
4
0.5
4
0.5
4
0.5
1.6
10
1
1.6
10
1
1.6
3
0.4
1
0.15
0.6
liE
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.3
(Ta= -IO·C - +70·C)
Note
Voo =5V±10%
15
15
15
15
15
15
15
15
15
15
15
15
15
15
liE
8
8
8
8
8
8
8
8
8
8
8
8
8
8
15
8
2
6
7
1
Note 1: Applied to pins ROo, ROl, RO" R03, RIo, Rh, Rh, Rh, R2o, R21, R22, R23, R3o, R31, R32
Note 2: Applied to pins ACL, CL I
Note 3: Applied to pins R22 (when standby cancel signal is input)
!!. Vr=VIH3-VrL3 (see the SH59I programming manual for details)
Note 4: Applied to pin ACL
Note 5: No-load condition
Note 6: When the contents of the R latch is output to the R3 2 pin.
Note 7: When the clock input to the CLI pin is output from the R3, pin.
lIE: VDD =3V±10%
----....-......-.--------SHARP - - - - - - - - - - - - 159
DevetQpment Guide for 4-Bit 1-Chip Microcomputers (SM Series)
I
.
.
.
.
. ..
.
DeveJ6pmentguidefor.4-Bif 1-Chip
Microcomputers (SM Series)
(1)
Description
To facilita,te efficient product development using Sharp's SM series 4-bit, I-chip microcomputers, we have established a general development
procedure covering determination of specifications
to actual delivery of the microcomputer as shown
below.
(2)
Development Procedure
CD
Determination of specifications
Specifications for a product you intend to develop must be determined in such a way that the
functions required of the microcomputer are clear.
Specifications should be prepared by the user, but
consultation on SM series microcomputers will be
provided on request. In addition, a programming
manual is available for each microcomputer.
.
® Determining the microcomputer to be used
Select a microcomputer mos.t suitable for the product. After determining the model of microcomputer, we will work out a rough development schedule in consultation with the user.
® System design
Detailed specifications for the operation of the
SHARP.side.w~rk
End user side work
r1
Technical meeting/Determining
specifications
Creating checkout device
I
I
h
System' design
J
-~
Checker, checklist, circuit diagram of checker
t
Write programme/
assemble /debug
Program demonstration
I!t
Final check of
program
PLA designation
J
t
I
Program approval
ROM design drawing
I
I
TS evaluation/approval:
l
~
TS approval
ES evaluation/approval
I.
-l
TS manufacture/
forwarding
J
I
ES manufacture/
forwarding
I
ES approval
C S evaluation / approval :
+
CS man.ufacture/
I
L
CS approval
forwarding
~.
Mass production
Delivery of goods
160
l
I
J
X-----I
I
(Can be eliminated)
I
1------I
I
(Can be eliminated)
t.I ______
Development Guide for 4-Bit 1-Chip Microcompliters (SM Series)
--.-..---.-.-..-..-..-.-.-.-..-..-..-.microcOl~puter and its peripheral circuitry are determined of this stage. We recommend that the user
confer with Sharp's staff even if the user himself
under takes program development.
If Sharp is to carry out program development,
the user must prepare the specifications first. After consultation with Sharp, the user determines
the final specifications. The subsequent schedule
will then be settled after consultation with the
user.
@ Writing the program
A flow chart is worked out and based on it,
machine code is written. The mnemonic codes
used for coding are covered in the programming
manual or cross-assembler manual. After coding,
a source file is prepared using a computer editor.
Sharp's microcomputer development tools, the
SM-D-8000II or SM-D-80 system can be used for
this purpose. A microcomputer development system running under the CP/M (Digital Research Inc.)
operating system can also be used. For the preparation of source file, refer to the respective development systems' manuals (SM-D-8000II User's
Manual, for example).
® Assembler
The object file is created from the source file using the cross-assembler prepared for the development system.
There are a number of cross-assemblers available to meet the requirements of respective SM
series products. Please, contact us for details. .
® Debugging and program revision
After the object file has been created, the program must be debugged by operating the EVA board
or CPU unit while using the checker to monitor
program operatfon. If the program is not running
properly, it must be revised and re-qssembled until
a satisfactory object file is prepared. A number of
development tools are available to perform this
task efficiently.
(j) Final confirmation of program operation
The final confirmation of the program is included in the debugging work described in (2) ® if
program development was made by the user.
If Sharp undertook program development, three
copies of programming specifications are usually
presented to the user for final confirmation of
program operation one week before the ROM is
submitted. If no problem is found in the programming specifications, a copy of programming specifications shall be sent back to us bearing a signature of approval.
In the event that probelms are discovered in the
program at this time, the program will be revised
after consultating with the user.
PLA (Programmable Logic Array) assignments
If the program is developed by the user, the user
prepares the PLA assignments diagram which
should be submitted to Sharp about two weeks before the date on which the ROM is scheduled to be
submitted. The procedure for PLA assignment is
covered in the programming manual. Pre-printed
PLA assignment forms will be provided to the user
on request.
When the program is developed by Sharp, we
will make the PLA assignments.
®, ROM submission
If the program is developed by the user, the
ROM must be submitted in the form of either an
EPROM or diskettes. Along with the ROM , the
ROM map should also be submitted to make sure
that the correct data can be ,read from the ROM.
Whoever develops the program, it is impossible
to change the program after the ROM is submitted.
The final confirmation of program operation must
be extremely thorough.
®> TS (Technical Sample)
The TS is submitted to the user in a ceramic
package for performance evaluation as a trial model. If no problems are found, the user shall issue a
statement of performance approval. Note that' the
TS package is a ceramic type and differs from that
which will be mass produced.
@ ES (Engineering Sample)
After approval ofthe TS, the ES is prepared and
submitted to the user. The ES is normally contained in a plastic package the same shape as that
which will be mass produced.
After evaluating the performance of the ES, the
user shall issue performance approval, assuming
no problems are encountered. The ES may be skipped if desired.
@ CS (Commercial Sample)
After approval of the ES, the CS is prepared and
submitted to the User. The CS is the mass-production trial model so it is made in the same shape
and quality as that which will be mass prodl:lced.
After evaluating the performance of the CS, the
user shall issue performance approval, assuming
no problems are encountered. The CS may be skipped if desired.
@ Mass production
After approval of the CS, mass production is initiated. If the ES and/or CS is omitted, the user
shall advise us when to start mass production.
®
(3) Development Tools
To faciJ.itate program development for SM
161
@
2
==~
......
.......-....:--,.-..-
Development
Guide
for 4-BIt 1-Chip Microcomputers ,(SM Series)
.'
I
.~~~~~~~~~
~~
r-SM~W--~--~----------------~~
r---~-------------'
CPU
I
SM-D -8000 II
:
I
I
Floppy disk
ROM OK)
RAM (64K)
I
I
I
I
I
I
I
II
I
I
I
___________________________ JI
I
I
SIO
I
I
IL __________________ JI
PTP/PTR
Terminal printer
(Sharp writer, etc.)
series microcomputers, two kinds of development
tools are available: one which uses the SM-D8000II and one which uses the sharp MZ-80B
computer.
Development tools equipped with an RS232C interface running under the CP1M OS can also be
used.
CD SM-D-8000II system
This emulator consists of the keyboard, display
LED, PROM writer, and interfaces. Although it is
possible for the SME-20 to debug the prograin by
connecting the CPU unit or EVA board, more efficient debugging can be achieved by transferring
the object file through the SM-D-8000II and
RS232C interface.
For details, see the SM software package manual
and instruction manuals of the SM series,SMD-800011 and SME-20.
The SME-20 can be connected not only to the
SM-D-80001l, but to any development device
equipment with an RS232C interface.
@ SM-D-80 system
. The SM series development system can be configured by connecting the debugger unit and SM evalution board to the basic FDOS system (MZ-80B,
floppydisk, printer) of the commercial personal
computer MZ-80B. Various utility 'programs such
as a cross-assembler, debugger and editor which
operate under the control of the FDOS are provided as standard equipment to facilitate efficient
program debugging.
162
SM-series
evaluation board
Debugger unit
SM .evaluation
board
..........
Development Guide for 4-Bit 1-Chip Microcomputers (SM Series)
....,....,....,~....,....,~....,~~....,....,~~
~....,
Connector for PROM writer
----,
I
Power.
r------------------l
I
I
I
ROM (2K)
RAM (64K)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Expansion I/O
MZ-80B system
(FDOS)
L ___________ _
I
I
_____J
I
I
I
I
I
I
IL ____
I
I
Main body of debugger unit I
..---___.i..J---:-_ _-:--. _ _ _ _ ...lI
Floppy disk
SM -series
Printer
evaluation board
....--------SHARP-------163
a-Bit 1-Chip Microcomputers
LH0801
Z8-01 Microcomputer Unit
LHOSO 1 Z8-0! Microcomputer Unit
•
Description
•
Pin Connections
Compared to earlier single-chip microcomputers,
the Z8 offers faster execution; more efficient use of
memory, more sophisticated interrupt, input/output and bit-manipulation capabilities ; and easier
system expansion.
Under program control, the Z8 can be tailored to
the needs of its user. It can be configured as a
stand-alone microcomputer with 2K bytes of internal ROM, a traditional microprocessor that manages up to124K bytes of external memorY,or a parallel-processing element in a system with other
processors and peripheral controllers linked by the
Z-BUS. In all configurations, a large number of
pins remain available for 110.
•
Features
1. Complete single-chip microcomputer with internal ROM, RAM and 110
• RAM 124 bytes
• ROM 2K bytes
• 110 32 lines
2. On-chip two programmable 8-bit counter/timers, each with a 6-bit programmbre prescaler
3. Full-duplex UART
4. 144-byte register file
5; Register pointer so that short, fast instructions
can access any working register groups
6. Vectored, priority interrupts for 110, counter /
timers, and UART
7. Up to 62K bytes addressable external space
each for program and data memory
8. On':'chip oscillator
9. High speed instruction execution
• Working register operating time: 1.5 ps
• Average instruction execution time: 2.2 fJ.S
,; Maximum instruction execution time: 5.0 fJ.S
10. Low-power standby option which retains contents of general-purpose registers
11. Single + 5V power supply
12. All pins are TTL compatible
Top View
---.--.-----SHARP-----,~--...-.-,
166
Z8-01 Microcomputer Unit
•
LH0801
Block Diagram
System _
:ll
Clock
Serial and Parallel
I/O and Control
GND(OV)
Vte( +5V)
f"---., ~
}-------{ll}-------{
Machine Timing
&
Instruction Control
Port 3
ALU
UART
Flags
Program Memory
(2,048X8)
Counter/Timer
Register Pointer
Register File
(I24x8 )
Program Counter
Interrupt Control
Port 2
Port 0
Port 1
~-------vr--------
'---------vr ---------
I/O or
As-Als
I/O or AD o -AD 7
--~--~--SHARP'-~-''''''''-'--~
167
LH0801.
Z8-01 Microcomputer Unit
Pin Description
•
Pin
PO O-P0 7
Pl o -P1 7
P2 o-P2 7
P3 0 -P3 7
Meaning
Port
Port
Port
Port
-
•
Function
8-bit I/O port, programmable for I/O.
Programmable for I/O in btyes.
Programmable for I/O in bits.
P3 0 -P3 3 for input, P3 r P3 7 for output.
Active "Low", activated for external address memory
. transfer.
Active "Low", activated for external data memory
transfer.
Read at "High", Write at "Low".
Active "Low". Initializes.
Clock terminal pin.
Clock terminal pin.
I/O
I/O
I/O
I/O
I/O
0
1
2
3
0
AS
Address Strobe
DS
Data Strobe
0
R/W
RESET
XTALl
XTAL2
Read/Write
Reset
Clock 1
Clock 2
0
I
I
0
Absolute Maximum Ratings
Symbol
VIN
VOllT
Tops
T stg
Parameter
Input voltage
Output voltage
Operating temperature
Storage temperature
•
Ratings
-0.3-+7
-0.3-+7
0-+70
-65"':'+150
Unit
V
V
'C
'C
(Vee=5V±5%, Ta=0-+70'C)
DC Characteristics
Symbol
Parameter
Clock input high voltage
VeH
Clock input low voltage
VCL
Input high voltage
Input low voltage
Reset input high voltage
Reset input low volta,ge
Output high voltage
Output l~w voltage
Input leakage current
Output leakage current
Reset input current
Supply current
Supply current
VIR
VIL
VRH
VRL
VOH
VOL
IlL
IOL
IIR
Icc
IMM
Note 1:
[OH=
-100,u A and
[OL=
Conditions
Driven by external clock
oscillator
Driven by external clock
oscillator
IOII =-250pA
IOL=+2.0mA
OV:;;;:V IN :;;;:+5.25V
OV~VIN~+5.25V
MIN.
MAX.
Unit
3.8
Vee
V
-0.3
0.8
V
2.0
-0.3
3.8
-0.3
2.4
Vee
0.8
Vee
0.8
-10
-10
Vee=5.25V, VRL=OV
TYP.
Note
V
V
V
V
V
V
0.4
10
10
-50
180
10
1
1
pA
pA
pA
rnA
rnA
l.OmA as to Ao-All, MDS, SYNC, SCLK and [ACK in LH0802.
Vee
From output
under test
2.lkO
From output
ruDder test
o---~-~~~~
l8kO
1.5kO
;>CJ>-------...... ;'O>--+--CrystaI2
74LS04 ~CL-=15pF MAX.
' - - - -.....--'Crystall
lCL=15:PFMAX.
Test load 1
Test load 2
TTL external clock interface circuit
- - . . - . . - . . - - - - - - - - - S H A R P -~-.-.-.------
lEl8
Z8-01 Microcomputer Unit
•
LH0801
(Vcc=5V±5%, Ta=0-+70"C)
External I/O or Memory Read/Write
Symbol
TdA (AS)
TdAS (A)
TdAS (DI)
TwAS
TdA (DS)
TwDS
TdDS (DI)
ThDS (DI)
TdDS (A)
TdDS (AS)
TdR (AS)
TdDS (R)
TdDO (DS)
TdDS (DO)
TdW (AS)
TdDS (W)
Parameter
Address valid to AS t delay
AS t to address float delay
AS t to input data required
valid delay
AS t low width
Address float to DS ! delay
-
DS low width
I Read
I Write
DS! to input data required valid
Input data hold time
DS t to address active delay
DS t to AS! delay
Read valid to AS t delay
DS t to read not valid
Output data valid to DS! delay
DS t to output data not valid delay
Write valid to AS t delay
DS to write not valid delay
Conditions
Test load 1
Test load 1
MIN.
50
70
Test load 1
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
Test
load
load
load
load
load
load
load
load
load
load
load
load
load
1
1
1
1
1
1
1
1
1
1
1
1
1
MAX.
Unit
ns
ns
Note
2
2
360
ns
4
ns
ns
ns
2
80
0
250
160
200
0
80
70
50
60
50
80
50
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
3
4
2
2
2
2
2
2
2
2
Note 1:
Note 2:
All timing references use 2.0 V for a logic "I" and 0.8 V for a logic "0".
Delay times are for an input clock frequency of 8 MHz. If below this frequency, add the incremental clock period to the standard
delay time.
Note 3: DS lower width is for an input clock frequency of 8 MHz. If below this frequency, add 3 increments of clock period to the
standard. The width varies with execution command.
Note 4: These delay times show system memory access time with an 8·MHz QC unit. If below this frequency, add 4 increments of clock
period for TdAS (OIl or 3 increments of clock period for TdDS (OIl.
CLOCK
PORT 0,
DM
PORT 1
AS
DS
dTdRIAS'
_TdWIAS)
*"
TdDS(R)
TdDS(W)~
RiW
'-'-'--'-'-'--SHARP'--'-'-'-'--169
Z8-01 Microcomputer Unit
LH0801
Additional Timing Table
•
Symbol
TpC
Parameter
Input clock period
TrC, TfC
Clock input rise and fall times
TwC
Input clock width
TdSC (AS)
TdSY (DS)
TwSY
System clock input to AS delay
Command sync output to DS delay
Command sync output pulse width
(Vcc=5V±5%, Ta=O-+70'C)I:
Conditions
Driven by, external
clock oscillator
Driven by external
clock oscillator
MIN.
125
MAX.
1,000
Unit
ns
25
ns
Note
>
37
ns
200
160
ns
ns
ns
5
5,6
5,6
Note : All timing references use 2.0 V for a logic "1" and 0.8 V for a logic "0".
__
,
Note 5: Test load 1 is used when' SCLK and SYNC are outputt via port 3, aad test load 2 when SCLK and SYNC are direct-output with
64-pin version.
Note 6: With an 8 MHz QC unit. If below this frequency, add 2 increments of clock period.
CLOCK
SCLK
AS
Data input
sample
1--------1
Read cycle-=-1\-----\;-Write cycle
DS
r
t:TdSY (DS 1---+1
SYNC ~_,T_w_S_Y_____jt
•
(V cc =5V±5%, Ta=0-+70'C)
Handshake Timing
Symbol
TsOI (DA)
ThDA (OI)
,
Parameter
Data in setup time
Data in hold time
TwDA
Data available width
TdDAL (RY)
DAV! to RDY! delay
TdDAH (RY)
TdDO (DA)
TdRY (DA)
170
DAVt to RDY t delay
Data out to DA V ! delay
RDY to DAV t delay
Conditions
Input handshake
Test load 1
Input handshake
Test load 1
Output handshake
Test load 1
Input handshake
Test load 1
Output handshake
Test load 1
Test load 1
Test load 1
MIN.
0
230
MAX.
175
20
ns
175
ns
ns
0
150
ns
ns
0
50
0
Unit
ns
ns
205
ns
ns
Note
LH0801
Z8-01 Microcomputer Unit
DAV
(input)
TdDAL(RY)
RDY
(output)
Port read
Input handshake
DATA OUT
~
----~DO(DA)
Data out valid
DAV
(output)
RDY--------------~------~~~~--~
~---......---~
(input)
Output handshake
171
.z~-01 Microcomputer Unit
•
LH0801
Architecture
(1)
Address Spaces
(i) Program Memory
The 16-bit program
counter addresses 64K bytes of program memory
space. Program memory can be located in two areas
: one internal and the other external (Fig. 1). The
first 2048 bytes consist of on-chip mask-programmed ROM. At addresses 2048 and greater, the
Z8 executes external program memory fetches.
The first 12 bytes of program memory are reserved for the interrupt vectors. These locations'
contain six 16-bit vectors that correspond to the
six available interrupts.
(ii) Data Memory
The Z8 can address 62K
bytes of external data memory beginning at location 2048 (Fig. 2). External data memory may be
include with or separated from the external program memory space. OM, an optical I/O function
that can be programmed to appear on pin P3 4 , is
used to distinguish between data and program
memory space.
(iii) ,Register File
The 144-byte register
file includes four I/O port registers (RO-R3), 124
general-purpose registers (R4-R127) and 16 control and status registers (R240-R255). These registers are assigned the address locations shown in
Fig. 3.
Z8 instructions can access registers directly or
indirectly with an 8-bit address field. The Z8 also
'allows short' 4-bit register addressing using the
, Register Pointer (one of the control registers). In
the 4-bit mode, the register file is divided into nine
working-register groups, each occupying 16 contiguous locations. The Register Pointer addresses
the starting location of the active working-register
group'.
(iv) Stacks
Either the, internal register file
or the external data memory can be used for the
stack. A 16-bit Stack Pointer (R254 and R255) is
used for the external stack, which can reside anywhere in data memory between locations 2048 and
65535. An 8-bit Stack Pointer (R255) is used for
the internal stack that resides within the 124
general-purpose registers (R4-R127).
65,535
External data me,mory
65, 535
External ROM or RAM
2, 048
Location of firs t
On-chip ROM
byte ,of instructJon
'-....
executed after
f"'------ --- --- -------reset
12
11
IRQ5
IRQ5
10
IRQ4
9
IRQ4
8
IRQ3
7
Interrupt vector
IRQ3
6
(Lower byte)
IRQ2
5'"
IRQ2
,4 J!
IRQ1
r
3
Interrupt vecto
IRQ1
(Upper byte ) 2
IRQO
1
IRQO
0
Fig: 1
172
Program memory map
---------1
2,048 t-'
Not addressable
O~
Fig. 2
______________
~
Data memory map
Za-01 Microcomputer Unit
LOCATION
255 STACK POINTER(BITS 7-0)
254 STACK POINTER(BITS 15-8)
REGISTER POINTEIt
253
252 PROGRAM CONTROL FLAGS
INTERRUPT MASK REGISTER
251
250 INTERRUPT REQUEST REGISTER
249 INTERRUPT PRIORITY REGISTER
248
PORTS 0-1 MODE
PORT 3 MODE
247
PORT 2 MODE
246
TO PRES CALER
245
TIMER/COUNTER 0
244
T1 PRES CALER
243
TIMER /COUNTER I
242
241
TIMER MODE
SERIAL I/O
240
LH0801
IDENTIFIERS
Sl'L
SPH
RP
FLAGS
IMR
IRQ
IPR
POIM
P3M
P2M
PREO
TO
PREI
Tl
TMR
SIO
NOT
IMPLEMENTED
PORT
PORT
PORT
PORT
1
,0
3
2
I
0
000 0
~253
The upper nibble of the reg ister file address
>----+ provided by the register pointer specifies the
,active working-register group_
--1l
r--------,127
-.J
, l
r-Jl
1--
-f
The lower nibble
l 1-_ _ _ _ _ _ _ _-1 of the register
r
file address
SPECIFIED WORKING~ provided by the
REGISTER GROUP
instruction
points to the
specified
-I register'
__ll-________
f
P3
P2
PI
PO
Fig. 3 The register file
(2)
r7r6irsr4 I
l~
I_--::-:~:--.-_~I 240
t- - ,..
GENERAL- PURPOSE
REGISTERS
2
-..J:
r--.--ir
l
127
4
3
r--;--;:::==t--------., 255
I/O ports
The Z8 has 32 lines dedicated to input and output. These lines are grouped into four ports of
eight lines each and are configurable as input, output or address/data. Under software control, the
ports can be programmed to provide address outputs, timing, status signals, serial I/O, and parallel
I/O with or without handshake. All ports have active. pull-ups and pull-downs compatible with TTL
loads.
( i ) Port 1 can be programmed as a byt.e I/O
port or an address/data port for interfacing external memory.
Memory locations greater than 2048 are referenced through Port 1. To interface external memory, Port 1 must be programmed for the multiplexed Adress/Data mode. If more than 256 external locations are required, Port 0 must output the
additional lines.
(ii) Port 0 can be programmed as a nibble I/O
port, or as an address port for interfacing external
memory.
For external memory references, Port 0 can pro-
It--------t 15
r
--l r---iIOP;rts---- ~
Register file
Fig. 4 The register pointer
vide address bits AsAll (lower nibble) or As-A15
(lower and upper nibble) depending on the required
address space.
(iii) Port 2 bits can be programmed independently as input or output. The port is always available
for I/O operations. In addition, Port 2 can be configured to provide open-drain outputs.
(iv) Port 3 lines can be configured as I/O or
control lines. In either case, the direction of the
eight lines is fixed as four input (P3 0 -P3 3 ) and four
output (P3 4 -P3 7 ). For serial I/O, lines P3 0 and P3 7
are programmed as serial in and serial out respectively.
• handshake for Ports 0, 1 and 2 (DA V and
ROY)
•
four external interrupt request signals
(IRQo-IRQ3)
• timer input and output signals (TIN and TOUT)
• Data Memory Select (OM).
(3) Serial Input/Output
Port 3 lines P3 0 and P3 7 can be programmed as
serial I/O lines for full-duplex serial asynchronous
----.-~-"----SHARP-.-~--:-----
173
'Z8,...,01 Microcomputer Unit
Transmitted Oata (No Parity)
ISPjspl0710610sl04103102101100lSTI
T
I
LSTART BIT
EIGHT OATA BITS
TWO STOP BITS
Transmitted Oata (With Parity)
ISplSpl P 106105104103102101lDoiSTI
TI
I
LSTART BIT
SEVEN DATA BITS
OOD PARITY
TWO STOP BITS
I
Received Oata (No Parity)
IspI0710610sI0,10,,10210110oISTI
I
I
,
L.START BIT
EIGHT OATA BITS
ONE STOP BIT
Received Oata (With Parity)
ISpl pI0610sI0,10,,102101100ISTI
II
I
L.START BIT
SEVEN OAT A BITS
PARITY ERROR FLAG
ONE STOP BIT
Fig. 5 Serial data formats
LH0801
receiver/transmitter operation. The bit rate is con·
trolled by Counter/Timer' 0, with a maximum rate
of 62.5K b~ts/second.
The Z8 ~utomatically 'adds a start bit and two
stop bits to transmitted data (Fig. 5). Odd parity ,is
also available as an option.
'(4) Counter/Timer
The Z8 contains two 8-bit programmable counter/timers (To and T I ), each driven by its own 6-bit
programmable prescaler. The T I' prescaler can be
driven by internal or external clock sources;
however, the To prescaler is driven by the internal
clock bnly.
The counters can be start{!d, stopped, restarted
to continue, or restarted from the initial value. The
counters can also be programmed to stop upon
reaching zero (single-pass mode) or to automaticaily
reload the initial value and continue counting (modulo-n continuos mode). The counters, but not the
prescalers, can be read any time without disturbing
their value or count mode.
(5)
Interrupts
The Z8 allows six different interrupts from eight
sources: the four Port 3 lines P3 0 -P3 3, Serial In,
Serial Out, and the two counter/timers. These interrupts are both maskable and prioritized.
All Z8 interrupts are vectored. Polled interrupt
systems ,are also supported.
~-------'---SHARP~~-------.-Ir~
174
LH080t
Z8-01 Microcomputer Unit
•
Instruction Set Notation
(1)
Addressing modes
The following notation is used to describe the
addressing modes and instruction operations as
shown in the instr~ction summary.
IRR
Irr
X
DA
RA
1M
R
r
IR
Ir
RR
Indirect register pair or indirect
working-register pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register address
Indirect working-register address only
Register pair or working register pair
address
(2) Symbols
The following symbols are used in describing the
instruction set.
dst
Destination location or contents
src
Source location or contents
cc
Condition code (see list)
@
Indirect address prefix
SP
Stack pointer (control registers 254-255)
PC
Program counter
FLAGS Flag register (control register 252)
Register pointer (control register 253)
RP
Interrupt mask register (control register
IMR
251)
Assignment of a value is indicated by the symbol
"+-". For example.
dst +- dst + src
indicates that the source data is added to the destination data and the result is stored in the destination location. The notation "addr (n)" is used to refer to bit "n° of a given location. For example,
dst (7) refers to bit 7 of the destination operand.
(3) Flags.
Control Register R252 contains the following six
flalSs :
C
Carry flag
Z
Zero flag
·S
Sign flag
V
Overflow flag
D
Decimal-adjust flag
H
Half-carry flag
Affected flags are indicated by :
o
Cleared to zero
1
Set to one
Set or cleared according to operation
Unaffected
X
Undefined
(4) Condition codes
See Table 1.
*
Table 1 Condition codes
Value
1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000
Mnemonic
C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE
Meaning
Always true
Carry
No carry
Zero
Not Zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Never true
......
Flags set
C=l
C=O
Z=l
Z=O
S=O
S=l
V=l
V=O
Z=l
Z=O
(S XOR V) =0
(S XOR V) =1
(Z OR (S XOR V)) =0
(Z OR (S XOR V)) =1
C=O
C=l
(C=O AND Z=O) = 1
(C OR Z) =1
......
-------------------SHARP - - - - - - - - - - - - - - - - 175
Z8-01
~icrocomputer
LH0801
Unit
Opcodemap
(5)
Lower Nibble (Hex)
o
o
6.5
3
4
5
6
CI)
e.
CI)
:0
.0
Z
Oi
0.
8
10.5
10.5
rio rz
rio Ir2
Hz. RI
1H z• RI
6.5
6.5
6.5
6.5
10.5
10.5
6.5
9
A
R,
JR,
6.5
INC
r]. Ir:!
Hz, RI
6.5
10.5
~
IR z• RI
A
B
C
o
E
6.5
12/10.5 12110.0
12/10.0
6.5
LD
LD
DJNZ
JR
LD
JP
INC
rJ. Hz
rz. RI
rt. RA
ce, RA
rJ, 1M
ce, DA
r,
6.5
6.5
F
~
10.5
10.5
r------
10.5
INC SUB SUB SUB SUB SUB SUB
R],IM IR],IM
rio Irz
H2. HI
6.5
6.5
10.5
10.5
10.5
JP
9
RhlM rRJ.IM
10.5
rl. r2
IR 2 •
RI
r------
10.5
SRP SBC SBC SBC SBC SBC SBC
lRRI
JM
ri. rz
R:h HI
IR2.RJ
R],IM
IRlolM
B.5
B.5
6.5
6.5
10.5
10.5
10.5
10.5
DA
DA
OR
OR
OR
OR
OR
OR
R,
JR,
rl. rz
rJ, Irz
Hz, H,
1H z, HI
10.5
10.5
6.5
6.5
10.5
10.5
rl.
Ir 2
~
R 1 ,IM IRIoIM
10.5
~
10.5
POP POP AND AND AND AND AND AND
R,
JR,
rl. rz
rl.Irz
Hz. RI
IRz• RI
R!,IM
IRIoIM
6.5
6.5
6.5
6.5
10.5
10.5
10.5
10.5
r------
COM COM TCM TCM TCM TCM TCM TCM
JR,
HI.IM IR!.IM
r., rz
rl.Irz
Hz. RI
IRhR\
6.5
6.5
10.5
10.5
10.5
10.5
PUSH PUSH TM
TM
TM
TM
TM
TM
Hz. RI
IH20 Rl
H],IM
IR1.IM
H,'
JR,
rl. rz
r], Irz
10.5
10.5
12.0
18.0
~
r--;;:,-
DEC""' DEC""' LDE LDEI
JR,
rt.Irrz
6.5
6.5
RL
R,
JR,
fz,Irf,
Ir2.lrr]
10,5
10.5
6.5
6.5
12.0
6.5
6.5
CLR
CLR
JR,
6.5
r----;u-
18.0
LDE LDEI
INCW INCW CP
JR,
01
Irl.IrfL
RL
r l . f2
CP
flo
6.5
EI
10.5
Ir2
6.5
10.5
CP
CP
R z• R t
lRz• RI
10.5
10.5
10.5
lO~5
CP
CP
XOR XOR
XOR XOR XOR XOR
1'10 1'2
R2• R\
rlt Ir2
12.0
IR 2 • RI
R"IM
Ir I. Irr2
6.5
6.5
12.0
18.0
SRA SRA LDC LOCI
rio x.
20.0
20.0
CALL'
CALL
LD
Ir2.lrr,
IRRI
DA
rlo x, RJ
6.5
6.5
10.5
10.5
10.5
RR
10.5
LD
LD
LD
LD
LD
R,
JR,
1'1.11'2
R 2 • Rl
IR z, RJ
RItIM
lRloIM
8.5
6.5
r---s:sSCF
~
CCF
~
10.5
LD
LD
11'\,
RCF
10.5
6.5
JR,
r---s:s-
R~
RR
R,
IRET
LD
1'1, Irrz
SWAP SWAP
r----w:o
10.5
JR,
r~. 11'1'1
RET
IR"IM
18.0
R,
IRI
~
R"IM lRhIM
]0.5
10.5
RRC RRC LDC LOCI
8.5
F
rz
6.5
6.1
R,
E
rl.
JR,
6.5
D
10.5
10.5
R,
R,
C
10.5
HI.IM lR),IM
B.O
RR,
B
8
7
RLC ADC ADC ADC ADC ADC ADC
6.5
HH,
0.
::J
6
JR,
10/12.1 12/14.1
7
6.5
6.5
5
4
R,
R,
)(
3
DEC DEC ADD ADD ADD ADD ADD ADO
RLC
2
2
NOP
Rz.IR I
r2
-=--------------------''---------~-------,--~~------------~-------------------~
Bytes per Instruction
Lower Opcode
Nibble
t
Execution
Cycles
Upper Opcode
Nibble
-
First
176
A
Operand
3
Pipeline Cycles
~---
Mnemonic
Second Operand
2
3
Legend:
R =8~Bit Address
r = 4 ~ Bit Address
R 1 or rJ = Dst Address
R2 or n = Src Address
Sequence:
Opcode, First Operand, Second Operand
Note: The blank areas are not defined.
Z8-02 Microcomputer Unit
(6)
Instruction Summary
I
and Operation I
Instruction
LH0801
Addr Mode
dst src
(Note 1)
ADC dst,src
dst<-dst + src + C
ADD dst,src
(Note 1)
dst <-dst + src
ANDdst,src
(Note 1)
dst<-dst AND src
CALL dst
DA
SP<-SP-2
IRR
@SP<-PC;PC<-dst
CCF
C<-NOTC
CLR dst
R
IR
dst<- 0
COM dst
R
. dst<-NOT dst
IR
CP dst,src
(Note 1)
dst<-src
DA dst
R
IR
dst<-DA dst
DEC dst
R
dst<-dst-l
IR
DECW dst
RR
dst<-dst-l
IR
DI
IMR(7)<-0
DJNZ r,dst
RA
r<-r-l
if r o PC<-PC + dst
Range: +127,-128
EI
IMR(7) <-1
INC dst
r
dst<-dst+l
R
IR
INCW dst
RR
dst<-dst+ 1
IR
IRET
FLAGS<-@SP; SP<-SP + 1
PC<-@SP;SP<-SP+2;IMR(7)<-1
JP cc,dst
DA
if cc is true
PC<-dst
IRR
JR cC,dst
RA
if cc is true,
PC <-PC + dst
Range: +127,-128
LD dst,src
1M
r
dst<-src
r
R
r
R
LDC dst,src
dst<-src
LDCI dst,src
dst<-src
r<-r + l;rr<-rr + 1
LDE dst,src
dst<-src
Instruction
'Opcode Byte Flags Affected
(Hex)
CZSVDH
FF
------
40
-**0--
POP dst
dst<-@SP
SP<-SP+ 1
R
IR
50
51
------
70
- - - - - -
50
-**0--
D6
D4
------
EF
* - - - - -
****--
PUSH src
SP<-SP - 1; @SP<-src
RCF
C<-O
RET
PC @SP;SP<-SP+ 2
RLdst ~ R
C
7 0
IR
90
91
****--
***X- -
RLCdst~R
10
****
-
- - - - -
-**
o- -
-***- -***-- - - -
-
-
-
- - - - -
9F
------
rE
r=O-F
20
21
AO
Al
BF
-***--
C
RR dst
IR
11
- - -
- - - - -
7 0
EO
E1
****
I@:[ii}J
R
C
7 0
IR
CO
Cl
****
3D
****1*
DF
1-----
R
IR
DO
D1
***0--
1M
31
------
C
RRC dst
SBC dst,src
dst<-dst - src - C
SCF
C<-l
(Note 1)
4£lCil?f--l
SUB dst,src
dst <-dst - src
(Note 1)
20
****1*
******
SWAPdst ~
7 4 3 0
R
IR
(Note 1)
FO
Fl
X**X--
TCM dst,src
(NOT dst) AND src
TM dst,src
(Note 1)
dst AND src
60
-**0--
70
-**0--
XOR dst,src
dst<-dst XOR src
BO
-**0--
------
------
82
92
AF
o- -
-***--
------
Irr
r
71
CF
SRP src
RP<-src
cD
c=O-F
30
cB
c=O-F
r
Irr
7 0
R
IR
4il L[ii)J IRR
SRA dst
X
r
Ir
r
R
IR
1M
1M
R
Irr
r
Irr
Ir
------
(Note 1)
Nap
r
X
r
Ir
R
R
R
IR
IR
r
Irr
Ir
Irr
Opcode Byte Flags Affected
(Hex)
CZSVDH
OR dst,src
dst<-dst OR src
****0*
rC
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
E6
E7
F5
C2
D2
C3
D3
src
83
93
00
rA
r=O-F
dst
Irr
It
****0*
40
41
00
01
80
81
8F
Addr Mode
LDEI dst,src
Ir
dst<-src
Irr
r<-r + 1; rr<-rr + 1
10
BO
Bl
60
61
AD
I
and OperationJ
------
(Note 1)
Note 1 These instructions have an identical set of addressing
modes, which are encoded for brevity. The first opcode nibble is
found in the instruction set table above. The second nibble is ex·
pressed symbolically by a 0 in this table, and its value is found
in the following table to the left of the applicable addressing mode
pair.
For example, to determine the opcode of an ADe instruction use
the addressing modes r (destination) and Ir (source). The result is
13
-----------
Addr Mode
dst
src
r
R
R
R
IR
r
Ir
R
IR
1M
1M
Lower
Opcode Nibble
i
-----------SHARP--------..-,
177
Z8~01
•
Microcomputer Unit
LH0801
Register
R244 (TO)
Counter/Timer 0 Register
(F4H: Read/Write)
R240 (510)
Serial I/O R:egister
(FOH: Read/Write)
-,
ID71 Dsl Dsl D.I D31 D2 rDll Do I
I~I~I~I~I~I~I~I~I
LTD INITIAL VALUE
(WHEN WRITTEN)
(RANGE: 1-256 DECIMAL
01-00 HEX)
To CURRENT VALUE
(WHEN READ)
[SERIAL DATA (Do=LSB)
R245 (PREO)
Prescaler 0 Register
(F5H: Write Only)
R241 (TMR)
Timer Mode Register
(FlH : Read/Write)
II
ID71 D61 Dsl D,I D31D21 DII Do'
TOUT
M~g:~~oo
To OUT=OI
Tl OUT = 10
INTERNAL CLOCK OUT =11,
T IN MODES
EXTERNAL =00
CLOCK INPUT
GA TE INPUT = 01
TRIGGER INPUT = 10
(NON-RETRIGGERABLE)
TRIGGER INPUT = 11
(RETRIGGERABLE)
LO=NO FUNCTION
I=LOAD To
O=DIS. ABLE To COUNT
I=ENABLE To COUNT
O=NO FUNCTION
'
I=LOAD Tl
LLCOUNT MODE
O=To SINGLE-PASS
1 = To MODULO-N
RESERVED
PRES CALER MODULO
(RANGE: 1-64 DECIMAL
,
01-00 HEX)
O=DISABLE Tl COUNT
I=ENABLE Tl COUNT
R242 (T1)
Counter Timer 1 Register
(F2H: Read/Write)
I~I~I~!~!~I~I~I~I
LTI INiTIAL VALUE
(WHEN WRITTEN)
(RANGE 1-256 DECIMAL 01-00 HEX)
TI CURRENT VALUE
(WHEN READ)
R243 (PRE1)
Prescaler 1 Register
(F3H: Write Only)
ID1 ! D61 Dsl D.I D31 D21 Dd Do'
I
COUNT MODE
O=TI SINGLE-PASS
I=Tl MODULO-N
CLOCK SOURCE
1 = Tl INTERNAL
O=Tl EXTERNAL TIMING INPUT
(TIN) MODE
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
178
ID71 D61 Dsl D" D31 D21 DII Do'
R246 (P2M)
Port 2 Mode Register
(F6H: Write Only)
I D11 D6! Dsl D.I D31 D21 Dl ! Do
I
Lp 20- P 27 I/O DEFINITION
o DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT
R247 (P3M)
Port 3 Mode Register
(F7H: Write Only)
1LL
ID11D61 DsID.ID31 D21 D
dDo]
L 0 PORT 2 PULL-UPS OPEN DRAIN
1 PORT 2 PULL-UPS ACTIVE
RESERVED
o P32=INPUT
P3s=OUTPUT
1 P32=DAV1i/RDYO P3s=,RDYO/DAVO
00 P 33 = INPUT
P 3. = OUTPUT
~np33=INPUT
P3.=DM
11 P33=DAVl/RDYl
P3.=RDYI/DAVI
o P31 = INPUT (TIN)
P3s=OUTPUT (TouT)
I P31 =DAV2/RDY2
P3s=RDY2/D AV2
o P 30 = INPUT
P 31 = OUTPUT
.
1 P30=SERIAL IN
P37 = SERIAL OUT
o PARITY OFF
1 PARITY ON
LH0801
Z8-01 Microcomputer Unit
...........................................................................................................
'
,
R252 (FLAGS)
Flag Register
(Feu: Read/Write)
R248 (P01M)
Port 0 and 1 Mode Register
(F8u: Write Only)
J
I~I~I~I~I~!~I~!~I
I D7! Ds! Ds! D.! Da! D2! DI! Do!
~
PO.-P07 MODE
OUTPUT =00
INPUT = 01 .
A12- Als = IX
EXTERNAL MEMORY
TIMING
NORMAL=O
EXTENDED = 1
Llll
&SER FLAG Fl
USER FLAG F2
HALF CARRY FLAG
DECIMAL ADJUST FLAG
C'POO-P03
MODE
LOO=OUTPUT
01=INPUT
IX = Aa- All
STACK SELECTION
0 = EXTERNAL
1 =INTERNAL
Plo-Ph MODE
00 = BYTE OUTPUT
01 = BYTE INPUT
10=ADo-AD7
11 = HIGH· IMPEDANCE ADo- AD7,
AS,DS, R/W,Aa-All,AwAls
IF SELECTED
OVERFLOW FLAG
SIGN FLAG
ZERO FLAG
CARRY FLAG
R253 (RP)
Register Pointer
(FDu: Read/Write)
R249 (lPRl
Interrupt Priority Register
(F9u: Write Only)
I D71 Dsl Dsl D.I D31 D21 DI I Dol
RESERVE~ !
INTERRUPT GROUP
A)
PRIORITY
IRQ3,IRQ5 PRIORITY ( GROUP
RESERVED =000
0= IRQ 5> IRQ 3 '---+--+-1=IRQ3>IRQ5
C > A > B=OOI
A > B > C =010
IRQO, IRQ2 PRIORITY (GROUP B)
0=IRQ2>IRQO
A > C > B=Ol1
1 =IRQO>IRQ2
B > C > A = 100
IRQl,IRQ4 PRIORITY (GROUP C)
C > B > A=10l
O=IRQl>IRQ4
B > A > C=110
I=IRQ4>IRQl
RESERVED=lll
R250 (IRQ)
Interrupt Request Register
(F Au: Read/Write)
1
R251 (lMR)
Interrupt Mask Register
(FBu: Read/Write)
l[
.ID7IDsIDs!D.IDaID21 DIIDol
rs
DON'T CARE
DON'T CARE
r4
REGISTER POINTER
R254 (SPH)
Stack Pointer
(FEu: Read/Write)
.
IRQO=P32 INPUT
IRQ 1 = P 33 INPUT
IRQ 2 = P 31 INPUT
IRQ3=P3o INPUT, SERIAL INPUT
IRQ4=To, SERIAL OUTPUT
IRQ5=TI
RESERVED
r7~1~
I
~LLDON'T
CARE
rs~
DON'T CARE
I~!~I~I~I~I~I~I~I
[STACK POINTER UPPER
BYTE (SPa-SPIs)
R255 (SPL)
Stack Pointer
(FFH : Read/Write)
I D71 Dsl Dsl D.I D3\ D21 DII Do
I
[1 ENABLES IRQO-IRQ5
(Do=IRQO)
RESERVED
[STACK POINTER LOWER
BYTE (SPO-SP7)
1 ENABLES INTERRUPTS
- - - - - - - - ' - - - - - - - S H A R P ----~.-.-.-..-.-.-179
'LH0802
Z8-02 Development Device
LH0802 ,Z8-02 Development Devic;:e, ' _
•
Description'
Th~ 64:-pin Z&,..02 is the development version of
the Z8-01 with internal mask-programmed ROM.
This device allows the user to build the prototype
systems in hardware with an actual device and to
deveiop the code that is eventually mask-programmed into the on-chip ROM of the Z8-0l.
TheZ8-02 is identical to the Z8-01 with the
following exceptions :
• The internal ROM has been removed.
• The ROM address lines and data lines are buffered and brought out to external pins.
• Control lines for the new memory have been
added.
•
Pin Connections
P30
P2,
RESET 6
IVW
P2,
P2,
P21
P20
P3,
P3,
Pis
PI,
PI,
PO,
PI,
PQ.
Pit
PO,
lACK 21
In
SYNC
Do
In
·Ao
Al
Ao
A,
An
AlO
A.
A,
A,
Top View
- . . . . - . - - - - - . - . - - S H A R P ~...-...-.~-- .......... - - - - - - - - '180
Z8-02 Development Device
•
LH0802
Block Diagram
.,
., ."
!~
. iii
.
System .... ~ rJl .,
.
Clock
~ .. ~
""""
~~~A «
.,Q
.~
Serial and Parallel
1/0 and Control
A
Vee( +5V)
GND(OV)
17
2
3
6
7
....
In
In
8
9
Port 3
Instruction Control
....
..."""
0
.,.'"
ALU
In
Flags
UART
:g
«
....
.,"E
Register Pointer
::e
Counter/Timer
....."
E
Register Fil e
(I24X8)
Program 'Counter
Po.
...
Interrupt
Acknowledge
Output
!
Interrupt Control
21
-:;;"
A
..".."
E
Po.
Port 0
Port 1
'-----yr---~
I/O or As-A,s
' - - - - vr
-----
I/O or AD o -AD 7
* 1 Program Memory Data
* 2 System Clock Output
* 3 Instruction Sync
•
Strobe Output
Output
Pin Description
The Z8-20 has 64 pins, 40 of which are the
same as those on the Z8-01. The remaining 24
pins are as follows.
Pin
Ao-A l l
Do-D 7
MDS
lACK
--
Meaning
Address Bus
Data Bus
Data Strobe
Interrupt Acknowledge
110
0
I
0
0
SYNC
Command Synchronization
0
SCLK
System Clock
0
Function
Address signal for internal ROM.
Data signal for internal ROM.
Active "Low". Internal ROM addresses are valid.
Active "High". Detects an interrupt.
Active "Low". For synchronizing the command
fetch cycle.
Internlll system clock. 1/2 of the external clock.
181
[!
?8-03 Protopack Emulator
LH0803
•
LH0803
Z8-03 Protopack Emulator
Description
The 28-03 (LH0803) is a ROMless version of
the standard 28-01, housed in a pin compatible
40-pin package.
The 28-03 carries a 24-pin socket for a direct
interface to program memory. 2716 type EPROM
can be used for program memory.
The 28-03 allows the user to build the prototype and pilot production units. When the final
program is established, the user can then switch
over to the 28-01.
•
Pin Connections
P36
XTAL2 2
P31
XTALl 3
P27
P26
P25
RESET
R!W
6
P24
7
P23
P22
P21
P35
P20
P33
P34
Ph
Pl6
PIs
Pl4
Pb
Pl2
PIt
Plo
Top View
.-..-.------SHARP---.------182
LH0803
Z8-03 Protopack Emulator
•
Block Diagram
S erial and Parallel
I/O and ~ontrol
GND(OV)
System t
Clock
:l
~p:;
r------{ll}----{
Port 3
Instruction Control
ALU
...e-"
"
0
UART
....
Ul
Ul
Flags
""
«""
...>.
.'"
......
Registe~ Pointer
E
::?l
E
Counter ITimer
Register File
(124XS)
Program Counter
...'"
0..
;;
Interrupt
Acknowledge
Output
.=i""
!
.
Interrupt Control
Q
....
.....'"
E
0..
Port 2
Port 0
Port 1
I/O or ADo - AD?
*1 Program Memory Data Strobe Output
*2 System Clock Output
* 3 Instruction Sync Out put
o : This
•
is equipped with ROM
Pin Description
The pins of the 28-03 are compatible with those
of the 28-01. For the pin description, refer back'
to the 28-01 explanation.
183
~
LH0811·
Z8::J 1 MicrOComputer Unit
LH0811
•
Z8-11 Microcomputer Unit
Description
Compared to earlier single-chip microcomputers,
the Z8 offers faster execution; more efficient use of
memory; more sophisticated interrupt, input/output and bit-manipulation c~pabilities ; and easier
system expansion.
Under program control, the Z8can be tailored to
the needs of user. It can be configured as a standalone microcomp·uter with 4K bytes of internal
ROM, a traditional microprocessor that manages up
to 120K bytes of external memory, or a parallelprocessing element in a system with other processors and peripheral controllers linked by the
Z-BUS. In all configurations, a large number of
pins remain available for I/O.
•
Features
1. Complete single-chip microcomputer with internal ROM, RAM and 110
• RAM 124 bytes
• ROM 4K bytes
• 110 32 lines
2. On-chip two programmable 8-bit counter/timers, each with a 6-bit programmable prescaler
3. Full-duplex UART
4. 144-byte register file
5. Register pointer so that short, fast instructions
can access any working register groups
6. Vectored, priority interrupts for 110, counter/
timers, and UART
7. Up to 60K bytes addressable external space
each for program and data memory
8. On-chip oscillator
9. High speed instruction execution
• Working register operating time: 1.5 ps
• Average instruction execution time: 2.2 ps
• Maximum instruction execution time: 5.0 ps
10. Low-power standby option which retains contents of general-purpose registers
11. Single + 5V power supply
12. All pins are TTL compatible
•
Pin Connections
XTAL2 2
XTALl 3
o
P36
P3l
P27
P26
P2s
RESET
6
P2.
R/W
7
P23
P22
P2l
P20
P3s
GND
11
P33
P32
P3.
POo
Ph
POI
P16
P02
PIs
P03
PI,
PO.
Pis
POs
Ph
P0 6
Pll
P07
Plo
Top View
~-""""'-------SHARP---'----'-'
184
LH08011
Z8-11 Microcomputer Unit
•
Block Diagram
"0
"0 cil....
!::
i::
''""
System ~ -,
"'oS" ! "'"...."
~-~ " Q" ..:
~
!
0;::
(fJ
Serial and Parallel
I 0 and Control
,
~
GND(OV)
Vee( +5V)
~
."
11
Machine Timing
Port 3
&
Instruction Control
ALU
Flags
UART
Program Memory
(4,096X 8)
Counter Ti mer
Register Pointer
Register File
(124XS)
Program Counter
Port 0
Port 1
Interrupt Control
Port 2
•
T
T
I/O or As-A15
I/O or ADo- AD7
Pin Description
The pins of the 28-11 are compatible with those
of the 28-01. For the pin description, refer back
to the 28-01 explanation.
----~-.--~......---SHARP.-.----.-.---
185
Z8...,1,2 Development Device
LH08·12
•
LH0812
Z8-12 Development Device
Description
•
Pin Connections
The 64-pin 28-12 is the development version of
the 28-11 with internal mask-programl\led ROM.
This device allows the user to build the prototype
systems in hardware with an actual device and to
develop the code that is eventually mask-programmed into the on-chip ROM of the 28-11.
The 28-12 is identical to the 28-11 with the
following exceptions :
• The internal ROM has been removed.
• The ROM address lines and data lines are buffered and brought out to external pins_
• Control lines for the new memory have been
added.
Top View
~~'--~'---SHARP---'-~-'-~"""'"
186
LH0812
Z8-12 Development Device
•
Block Diagram
"0
...
"0 Ul
...
Ul ''""
"...
~
!:
Serial and Parallel
I/O an1 Control
System
Clock
GND(OV)
Vcc(+5V)
~
"';
~
"--
"'" -0os
" 0:::"
~ 0:::
~
!os
0
-0
-0
...::
Port 3
Instruction Control
~
"
2-
ALU
"
0
UART
'"
"...'"
Flags
-0
-0
«:
»
...
0
S
Register Pointer
"
;;;:
S
Counter Timer
Register File
'"...
1124X81
p..
bJl
...0
Program Counter
0;
Q.
Interrupt
Acknowledge
O~tput
11
..:;
!
0'"
Interrupt Control
S
...'"
...0
p..
OJ)
Port 2
Port
a
Port 1
I/O or ADo-AD,
* 1 Program Memory Data Strobe
* 2 System Clock Output
* 3 Instruction Sync Output
Output
--------SHARP-------187
~
..........-..
Z8~12 Development Device
•
...... -....
....
-----..,.~
,
. - . - . -........-~--:.--.:
LH08t2
Pin Description
The 28-12 has 64 pins, 40 of which are the
same as those on the 28-11. The remaining 24
pins are as follows.
Pin
Ao-A l l
Do -D 7
MDS
lACK
--
188
Meaning
Address Bus·
Data,Bus
Data Strobe
Interrupt Acknowledge
110
0
I
0
0
SYNC
Command Synchronization
0
SCLK
System Clock
0
Function
Address signal for internal ROM
Data signal for inter.nal ROM.
Active "Low". Internal ROM addresses are valid.
Active "High". Detects an interrupt.
Active "Low". For synchronizing the command
fetch cycle.
Internal system clock. 112 of the external clock.
Z8-13 Protopack Emulator
LH0813
•
LH0813
Za-I3 Protopack Emulator
Description
The 28-13 (LH0813) is a ROMless version of
the standard 28-11, housed in a pin compatible
40-pin package.
The 28-13 carries a 24-pin socket for a direct
. interface to program memory. 2732 type EPROM
can be used for program memory.
The 28 -13 allows the user to build the prototype and pilot production units. When the final
program is established, the user can then switch
over to the 28-11.
•
Pin Connections
o
P36
P31
P2,
P26
P25
RESET
6
P2.
a
P23
P22
P21
P3s
P32
P3.
POo
Ph
POI
P16
POz
P1s
POs
Pl.
P13
P12
Ph
P07
Top View
I
"
189
ZS",'13 Protopack Emulator
•
LH0813
Block Diagram
Serial and Parallel
I/O and Control
"
Vee( +5V)
GND(OV)
System t
Clock
:l
~c::
,}-----~ }-------~111}_----~
Port 3
Instruction Control
1
:;
o
UART
O - -.....-L;;>O-~---Crystal 2
74LS04 ;;;CI.=15 p FMAX.
'----~--
Crystal 1
ICI.=15 PF MAX.
Test load 1
•
AC Characteri~tics
The SM-803 is compatible with the 28-01 as to
the AC characteristics. Refer back to the 28-01
description.
•
New Functions
The SM-802 has two standby modes; HALT
and STOP.
TTL, external clock interface circuit
So there is no power consumption now. This mode
is cleared by a reset input, port 3 input, or timer
interrupt at a mask option (designated at the time
of ROM input).
(2) STOP mode·
The STOP mode is brought by decoding a STOP
instruction (FF6FH).
(1 ) HALT mode
The HALT mode is introduced by decoding a
HALT instruction (FF7F H). In this mode, the
oscillation circuit is kept in operation, but no system clock is internally supplied any more.
197
.........
........-:...,...,...,...,-.-
CMo.S 8-Bit 1-Chip Microcomputer
.~.-....,
SM-812
•
,
CMOS 8-Bit I-Chip Microcomputer
.
Description
The SM-812 is an 8-bit single chip CMOS micro·
€omputer with 2,048·byte of ROM, 128·byte of
RAM, timer/counter ,and multiplex interrupt capa·
bility.
It is best suited to high-function controllers due
to its single power supply and high-speed proces·
sing capability.
•
Features
1. CMOS process
2. ROM capacity 2,048 X 8 bits
3. RAM capacity 128 X 8 bits
4. 64-byte (MAX.) of address space
5. InstrudioJ?s 81
6. Subroutine nesting using RAM area
7. Output ports 32 bits
8. Input/Output ports 16 bits
9. Timer/counter
8 bit counter
2'
8 bit prescaler 1
10. Interrupt function
External interrupt
1
Serial 110 interrupt
1
Timer interrupts
2
Non-maskable interrupt 1
11. Serial interface 8 bits
12. Standby mode (HALT mode, STOP mode)
13. Single power supply (2.7-5.5V)
14. Instruction cycle 1 ps(MIN.)
15. 64-pin quad-flat package
198
SM-812
~...,.-....,~,
•
Pin Connections
WAIT
I
Ml
2
P3./SI
P31/SCK
P32!SO
P33/MRQ
P3./CN
P3s/T
P36/RD
P37/WR
NC
NC
PO./AD.
POJ/ADI
P02!AD2
P031 AD,
PO,I AD,
POsl ADs
PO,I AD,
3
'
s
'
7
8
•
IO
11
12
13
U
15
I'
17
18
19
Top View
SM-812
CMOS 8-Bit 1-Chip Microcomputer
•
Block Diagram
Output Ports and
External Address Bus
I/O Ports and
External Data Bus
-"
~
WAIT
Signal Input
Sync.
Clock Output
j
IIlO Ports
S ync... Reset
Clock Output
9
PC
SP
A
B
D
H
F
C
E
L
RAM
192XB
'
ROM
4096xB
11
IIO Ports
49
o
t--;;~~-+e--j
Prescaler
9
Interrupt Input
(non - maskable)
Interrupt Input
I
Output
Ports
P5
Oscillator
Symbol description
ADR
ALU
PC
SP
F·
A,B,C,D,E,H,L
INC/DEC
:
:
:
:
:
:
:
Address latch
Arithmetic logic unit
Program counter
Stack pointer
Flag register
General-purpose registers
Incrementer / decrementer
TM
:
TAC, TCB:
IE
:
IME
:
IFO-IF3 :
:
OSC
PO-P5
:
Ti'mer modular register
Timer counter
Interrupt enable F /F
Interrupt master enable F /F
Interrupt request register
System clock oscillator
Port register
199
OMOS8-Bit 1-0hip Microcomputer
•
SM-812
Pin Description
Pin
P4o~P47
P2 o/DB o
~P27/DB7
POol ADo
~P17/AD15
P3 0/S1
P3 1/SCK
P3 2 /S0
P3 3 /MRQ
P3 4 /CN
P3 5/T
P3 6 /RD
P3 7 /WR
P50~P57
--
110
110
Bidirectional
Circtit
Pull-up
Pull-up at input
0
Oil
O/Bidirectional
0
0
Oil
0
0
0
0
Pull-up at input
Pull-up at input
Pull -up at input
Pull-up
WAIT
I
Pull-up
INT
NMI
RESET
TEST
I
I
I
I
Pull·-l!P
Pull-up.
Pull-up
'" OUT. Ml
CK lo CK 2
VDD • GND
0
Function
Programmable for 110 in bits
External memory data bus
lIO in bytes
signal
BXternal memory address
Output in bytes
signal
Serial data input
Serial clock input/output
Serial data output
Memory request output
Output in bytes
Timer counter input
Counter signal output
Read signal output
Write signal output
Settablel resettable in bits
Used to prolong an access time for external memory
or to clear the standby mode.
Maskable interrupt request
Non·maskable interrupt request
Auto clear
For testing (usually connected to GND)
Synchronization clock output
For clock oscillator
Logic circ·uit power supply
----------SHARP...--.---------200
. CMOS 8-Bit 1-Chip Microcomputer
5 M- 813
•
CMOS a-Bit I-Chip Microcomputer
Description
The SM-813 is an 8-bit single chip CMOS microcomputer with 4,096-byte of ROM, 192-byte of
RAM, timer/counter and multiplex interrupt capability.
It is best suited to high-function controllers
due to its single power supply and high-speed processing capability.
•
Features
1.
2.
3.
4.
5.
6.
7.
9.
SM-813
CMOS process
ROM capacity 4,096 X 8 bits
RAM capacity 192 X 8 bits
64K-byte (MAX.) of address space
Instructions 81
Subroutine nesting using RAM area
Output ports 16 bits
Timer/counters
8-bit counters 2
8-bit prescaler 1
10. Interrupt function
External interrupt
1
Serial I/O interrupt
1
Timer interrupt
2
Non-maskable interrupt 1
11. Serial interface 8 bits
12. Standby mode (HALT mode, STOP mode)
13. Single power supply (2.7-5.5V)
14. Instruction cycle l!'-s (MIN.)
15. 64-pin quad-flat package
•
Pin Connections
WAIT 1
Ml '
P30/SI 3
P3'/SCK ,
P3';SO s
P3,/MRQ •
P3,/CN '
P3s/T 8
P3. 9
P3,1O
RD 11
WR 12
POD/ADD 13
PO,/AD, 14
PO,fAD, 15
P03/ AD, 16
PO,,/AD,17
POs/ADs 18
PO./AD. 19
43
Viln
" P40
" NC
40 P2,fDB,
39 P2./DB.
38 P2s/DBs
37 P2,/DB,
36 P2,/DB,
35 P2,fDB,
34 P2,/DB,
33 P20/DBo
Top View
201
.CMOS8-Bit1-Chip Microcomputer
___
.......... . . , . - :_ _
~_
•
~_~.
_______r.-_.._ _
SM ..813
BlOck Diagram
I/O Ports and
Output Ports and
External Data Bus
External Address
Bus
J. _ _ _ _ _ _""'
,------A------,
940
WAIT
Signal Input
Sync.
Clock Output
S ync. Reset 6
Clock Output
RAM
192XB
ROM
4096xB
l
~ Output
P5
I Ports
9
Interrupt Input
(non - maskable)
Interrupt Input
J
Oscillator
Symbol description
:
:
:
:
:
F
A,B,C,D,E,H,L :
:
INC/DEC
ADR
ALU
PC
SP
202
Address latch
Arithmetic logic unit
Program counter
Stack pointer
Flag register
General-purpose regi sters
Incrementer/decrementer
•
~'-'
TM
TAC, TCB
IE
IME
IF 0 - IF 3
OSC
PO - P 5
:. Timer modular register
: Timer cou~ten
: Interrupt enable F /F
: Interrupt master enable F /F
: Interrupt request register
: Sy!!tem clock oscillator
: Port register
CMOS 8-Bit 1-Chip Microcomputer
•
.~
SM-813
Pin Description
Pin
P4 o-P4 7
P2o/DBoP27/DB7
POo/ADo
-P1 7/AD 15
P3 0 /SI
P3 1 /SCK
P3 2 /SO
P3 3 /MRQ
P3 4 /CN
P3 5 /T
P3 s
P3 7
P5 0 -P5 7
RD
WR
--
I/O
I/O
Pull-up
Circtit
I/O
Pull-up at input
0
0/1
O/Bidirectional
0
0
0/1
0
0
0
0
0
0
Pull-up at input
Pull-up at input
Pull-up at input
Pull-up
WAIT
I
Pull-up
INT
NMI
RESET
TEST
"'OUT. Ml
CK h CK 2
VDD• GND
I
I
I
I
0
Pull-up
Pull-up
Pull-up
Function
Programmable for I/O in bits
External memory data bus
I/O in bytes
signal
External memory address
Output in bytes
signal
Serial data input
Serial clock input/output
Serial data output
Memory output
Output in bytes
Timer counter input
Counter signal output
Settablelresettable in bits
Read signal for external memory
Write signal for external memory
Used to prolong an access time for external memory
or to clear the standby mode.
Maskable interrupt request
Non-maskable interrupt request
Auto clear
For testing (usually connected to GND)
Synchronization clock output
For clock oscillation
Logic circuit power supply
-..-..-.----------SHARP.....-..--------203
.. LU8l0Vl
OMOS 8-Bit 1-Chip Microcomputer
LU81 0 V1 CMOS a-Bit I-Chip Microcomputer
•
Description
•
Pin Con.nections
LU810Vl, eliminating the internal ROM from
SM-812, is the ROM less version of SM-812 and it
uses Port 0 and Port 1 exclusively as the address
bus and Port 2 as the data bus. Other functions
are compatible with those of SM-812.
WAIT
Ml
•
I
2
Features
1. CMOS process
2. ROM capacity 128X 8 bits
3. 64K-byte (MAX.) of address space
4. Instructions 81
5. Subroutine nesting using ~AM area
6. Output ports 16 bits
7. Input/Output ports 8 bits
8. Timer 1counter
8-bit counters 2
8- bit prescaler 1
9. Interrupt function
" OBI
3:, DB.
Top View
External interrupt
1
Serial 1/0 interrupt
1
Timer interrupts
2
Non-maskable interrupt l '
10. Serial interface 8 bits
11. Standby mode (HALT mode, STOP mode)
12. Single power supply (2.7-5.5V)
13. Instruction cycle 1 ps(MIN.)
14. 64-pin quad-flat package
204.
LU810V1
CMOS 8-Bit 1-Chip Microcomputer
•
Block Diagram
Address Bus
Data Bus
A
,--------A----,
WAIT
Signal Input
Sync.
Clock Output
P3
Reset
, Sync.
Clock Output
!
fIIO p,,,,
U
~
RAM
"
192x8
Q
u'
l
2S
fIIO p""
49
Prescaler
GND
P5
Test
IO"'~'
Ports
9
Interrupt Input
(non -maskable)
Interrupt Input
Oscillator
Symbol description
:
:
:
PC
:
SP
F
:
A, B, C, D, E, H, L :
:
INC/DEC
ADR
ALU
Address latch
Arithmetic logic unit
Program counter
Stack pointer
Flag register
General-pupose registers
Incrementer / decrementer
--.-..-..-..-r'-'-~SHARP
TM
: Timer modular register
TAC, TCB: Timer counter
IE
: Interrupt enable F /F
IME
: Interrupt master enable F /F
IF 0 - IF 3 : Interrupt request' register
OSC
: System clock oscillator
: Port register
PO-' P5
---------------,205
~
.---..
---.-.-.-:---.....---
cMos 8-Bit 1-Chip Mjcrocomputer
.........
•
..............,............
Pin Description
Circtit
Pin
P4 o-P4 7
110
110
Pull up
DB o-DB 7
1/0
Pull up at input
AD o-AD 1s
0
, P3 0 /SI
P3 1 /SCK
P3 z /S0
P3 3 /MRQ
P3 4 /CN
P3 s /T
P3 6 /RD
P3 7 /WR
P5 0 -P5 7
--
Oil
Oil
0
0
Oil
0
0
0
0
"
Pull up at input
Pull up at input
/
Pull up at input
-,
Pull up
WAIT
I
Pull up
INT
NMI
RESET
TEST
1> OUT. Ml
CK h CK z
VDD• GND
I
I
I
I
0
Pull up
Pull up
Pull up
.
LU810V1
~---~---
Functioq
Programmable for 1/0 in bits
External memory data bus
I/O in bytes
signal
External,memoryaddress
Output in bytes
signal
Serial data input
Serial clock input! output
Serial data output
Memory request output
Output in bytes
Timer counter input
Counter signal output
Read signal output
Write signal output
Settablel resettable in bits
Used to prolong an access time for external memory
or to clear the standby mode.
Maskable interrupt request
Non-maskable interrupt request
Auto clear
For testing (usually connected to GND)
Synchronization clock output
For -clock oscillation
Logic circuit power supply
.....-.~~------SHARP~-~-------------
206
28 Series Ordering Information
.-..-..-...-,.-..-...-,.-...-,..-,..-,.-...-,---..-,.-.
Z8 Series Ordering Information
Below is discussed how to order the Z8 series
products.
Customers are requested to submit an EPROM or
paper tape as the ROM data media. The following
information should be attached in any form and
any means.
(1) ROM data media
(2) Specific data (chip select, marking, and
other information)
(3) Your company's name, your own name, and
stamp
(4) Ordering date
When submitting the ROM drawings, two sets of
ROM data media are also required together with a
list of ROM to see if the read-out data are correct.
With the ROM data media, we computer-aid·
ed-design a ROM masking magnetic tape and make
up EPROM or paper tapes, and their list, in order
to make sure the designed ROM data are correct.
These materials are then checked up by the customer for approval. If it is okay, we start masking
and make some technical evaluation samples (TS),
which are delivered to the customer. When the
samples are accepted, the customer will send us a
"TS Confirmation". By a mass-production order at
the moment or later, we will start producing the
product in large quantities.
SHARP
Client
t----+---~Business
dept .t--'--------,l>j
Project dept.
' - - - - - -......
t----+---~fiB3.u~s~in~e;ss;dde~PrttJ.-----------,
Business dept.
L-...;..:.-----+---~Business
dept..I------------jE---.J
Business dept.
Business dept.
....--------SHARP-------.-.
207
a-Bit Microprocessor
and Peripheral LSls
LH0080/LH0080A/LH0080B
Z80/Z80A/Z80B Central Processing Unit
-
LH0080/LH0080A/LH0080B
ZSOIZSOAlZSOB Central Processing Unit
•
Description
The Z80 product line is a complete set of microcomputer components, development system~ and
support software. The Z80 microcomputer component set includes all of the circuits necessary tp
bUild high-performance microcomputer systems
with virtually no other logic and a minimum num·
ber of low cost standard memory elements.
The LH0080 Z80 CPU (Z80 CPU for short below) i~ the third generation microprocessor implemented using an N-channel silicon-gate process.
The Z80 CPU is designed for using the standard
memory components, higher system throughput and
more efficient memory utilization. In addition, the
output signals of the Z80 CPU is decoded to control peripherals. The Z80 CPU requires only
single + 5V DC power supply and single phase
clock, theref~re it is easy for the Z80 CPU to Implement into a system.
The LH0080A Z80A and LH0080B Z80B CPU
are the high speed version which can operate at the
4MHz and 6MHz system clock, respectively.
•
Pin Connections
o
Top View
• , Features
1. 8-bit parallel processing single-chip microprocessor
2. N-'channel silicon-gate process
3. 158 instructions (The instruction of the 8080A
are included as a subset; 8080A software compatibility is maintained)
4. 22 registers
5. The capability of 3 modes maskable interrupt
and non-maskable interrupt
6. On-chip dynamic memory refresh counter
7. Instruction fetch cycle: 1.6ps(Z80), 1.0lPS
(Z80A), 0.67 ps(Z80B)
8. Single + 5V power supply and single phase
clock
9. All inputs and outputs fully TTL compatible
10. 40-pin dlial-in-line package
'--~~-----------SHARP -~---!.........-.--210
"
Z80/Z80AlZ80B Central Processing Unit
•
LH0080/LH0080A/LH0080B
Block Diagram
System Data
Bus
,
Halt State
Memory Request
Input/Output Request
Read
Write
Bus Acknowledge
Machine Cyclel
Refresh
Data Bus Interface
Instruction
Instructionrr-_ _ _---'
Decoder
Register 1-,...------,
ALU
Interrupt Request
Non- Maskable Interrupt
Wait
Bus Request
Reset
Address Bus Interface
V~~
GND System
C+5V) COy)
Clock
System Address Bus
211
LH0080/LHOO80A/LH0080B
Z80/Z80A/Z80B Central Processing Unit
•
Pin Description
Pin
Ao-A 15
. Do-D 7
-
Ml
MREQ
-10RQ
-
RD
-
WR
-RFSH
Data bus
Machin(t cycle one
3-state 0
liD request
3-state 0
Memory read
3-state 0
Memory write
3-state 0-
Halt state
0
Wait
I
--
Maskable interrupt
request
I
--
Non-maskable
interrupt request
I
Reset
I
Bus request
I
BUSAK
Bus acknowledge
O.
CLOCK
System clock
I
--
WAIT
INT
NMI
--RESET
--BUSRQ
---
System data bus
!
Memory request
0
HALT
System address bus
0
Refresh
--
Function
liD
3-state 0
{3idirectional
3-state
Meaning
Address bus
Active "Low". Indicates that the current machine cycle
is the OP .code fetch cycle of an instruction execution.
Active "Low''',- Indicates that the address bus holds a
valid address for a memory read or memory wri~e operation.
Active "Low". Indicates that the lower 8 bits of the
addres& bus holds a valid liD address' for an liD read
or write operation. Also generated concurrently with
Ml during an interrupt acknowledge cycle to indicate an
interrupt response.
Active "Low". Indicates that the CPU wants to read data
from memory or an liD device.
Active "L(')w". Indicates that the CPU data bus holds
valid data to be stored at the addressed memory or liD
location.
Active "Low". Indicates that the lower 7 bits of the_systern address bus can be used as a refresh address to the
system's dynamic memories. Tog~ther with MREQ at
"Low".
Active "Low". Indicates that a Halt instruction is being
executed. While halted, the CPU exe~utes NOPs to maintain memory refresh. The Halt state is cleared with RE- --SET, NMI, or INT (when allowed).
Active "Low". Indicates to the CPU that the addressed
memory or liD devices are not ready for a data transfer.
The CPU continues to enter a wait state as long as this
signal is acti ve.
Active "Low". Generated by liD devices. The CPU honors a request at the end of the current instruction if the
interrupt enable flip-flop is enabled.
Active "Low". Has a higher priority than INT. Always
recognized at the end of the current instruction, independent of the status of the interrupt enable flip-flop.
Automatically forces the Z80 CPU to restart at location
0066H.
Active "Low". Resets the int~rrupt enable flip-flop, the
program counter interrupt vector register and the memory refresh register, and sets the interrupt status to
Mode 0, in order to initialize the CPU.
Active "Low". Has a higher priority than NMI. Always
recognized at the end of the current machine cycle. Activated to allow a bus 11)aster other than the CPU to contro the system bus.
Active "Low". Indicates to the requesting device that the
external circuitry can control the system bus.
Inputs+5V single-phase clock.
--.----~--SHARP'---.--..--~.-..-.--
212 -
\.
I
'
"
•
Z80/Z80A/Z80B Central Processing Unit
•
LH0080/LH0080A/LH0080B
Absolute Maximum Ratings
Parameter
Input voltage
Output voltage
Operating temperature
Storage temperature
Symbol
VIN
VOllT
Topr '
T,tg
Ratings
-0.3-+7.0
-0.3-+7.0
0-+70
-65-+150
Unit
V
V
"C
"C
Standard Test Conditions
The characteristics below apply for the following standard test conditions, unless otherwise
noted. All voltages are referenced to GND (OV).
Positive current flows into the referenced pin.
All ac parameters assume a load capacitance of
100 pF. Add IOns delay for each 50. pF increase
in load up to a maximum of 200 pF for the data
bus and 100 pF for address and control lines.
•
(Vcc=5V±5%, Ta=0-+70"C)
DC Characteristics
Parameter
Clock input low voltage
Clock input high voltage
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Symbol
VILC
V IHC
V1L
VIH
VOL
VOH
Conditions
IOL =1.8mA
IoH =-250,uA
consumption
Input leakage current
3-state output leakage
current in float
•
Icc
I ILl I
I ILEAK I
MAX.
0.45
Vcc+ 0.3
0.8
150
200
200
10
Unit
V
V
V
V
V
V
rnA
rnA
rnA
,uA
10
,uA
Vcc
0.4
Z80 CPU
,Z80A CPU
Z80B CPU
O::£VIN::£VCC
VOllT =O.4V -Vcc
(f=lMHz, Ta=25"C)
Capacitance
Parameter
Clock capacitance
Input capacitance
Output capacitance
TYP.
2.4
.-
Curre~t
MIN.
-0.3
Vcc- 0 .6
-0.3
2.0
Symbol
CCLOCK
CIN
COllT
Conditions
Unmeasured pins returned
I
to ground
MIN.
TYP.
MAX.
35
5
10
Unit
pF
pF
pF
--~--'----SHARP'-''---'----
213
Z80/Z80A/Z80B Central Processing Unit
•
LH0080/LH0080A/LH0080B
(Vcc=5V±5%, Ta=0-+70°C)
AC Characteristics
No.
Parameter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Clock cycle time
Clock pulse width (High)
Clock pulse width (Low)
Clock fall time
Clock rise time
Clock t to address valiC\ delay
Address valid to MREQ ~ delay
Clock ~ to MREQ ~ delay
Clock t to MREQ t delay
MREQ pulse width (High)
MREQ pulse width (Low)
Clock ~ to MREQ t delay
Clock ~ to RD ~ delay
Clock t to RD t delay
Data setup time to clock t
Data hold time from RD t
WAIT setup time to clock ~
WAIT hold time after clock ~
Clock t to M1 ~ delay
Clock t to M1 t delay
Clock t to RFSH ~ delay
Clock t to RFSH t delay
Clock ~ to RD t delay
Clock t to RD ~ delay
Data Setup to clock t during
M2 , M3 , M4 or M5 cycles
Address stable prior to IORQ ~
Clock t to IORQ ~ delay
Clock ~ to IORQ t delay
Data stable prior to WR ~
Clock ~ to WR ~ delay
WR pulse width
Clock ~ to WR t delay
Data stable prior to WR ~
Clock t to WR ~ delay
Data stable from WR t
Clock ~ to HALT t or ~
NMI pulse width
BUSREQ setup time to clock t
BUSREQ hold time after clock t
Clock t to BUSACK ~ delay
Clock ~ to BUSACK t delay
Clock t to data float delay
Clock t to control output float delay
----(MREQ, IORQ, RD, and WR)
Clock t to address float delay
MREQ t ,IORQ t, RD and WR t
to address hold time
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
t
280 CPU
MIN.
MAX.
400*
TcC
180*
TwCh
TwCl
180
2000
TfC
30
30
TrC
145
TdCr (A)
TdA (MREQf) 125 *
TdCf (MREQf)
100
TdCr (MREQr)
1QO
170*
TwMREQh
TwMREQ1
360*
TdCf (MREQr)
100
TdCf (RDf)
130
TdCr (RDr)
100
TsD (Cr)
50
ThD (RDr)
0
TsWAIT (Cf)
70
ThWAIT (Cf)
0
TdCr (Mlf)
130
TdCr (Mlr)
130
TdCr (RFSHf)
180
TdCr (RFSHr)
150
TdCf (RDr)
110
TdCr (RDf)
100
Symbol
TsD (Cf)
TdA (IORQf)
TdCr (IORQf)
TdCf (I0RQr)
TdDm (WRf)
TdCf (WRf)
TwWR
TdCf (WRr)
TdDi (WRf)
TdCr (WRf)
TdWRr (D)
TdCf (HALT)
TwNMI
TsBUSRQ (Cr)
ThBUSRQ (Cr)
TdCr (BUSAKf)
Tdef (BUSAKr)
TdCr (Dz)
60
280A CPU
MIN.
MAX.
250*
1l0*
110
2000
30
30
110
65*
85
85
110*
220*
85
95
85
35
0
70
0
100
100
130
.120
85
85
50
320*
280B CPU*
MIN.
MAX.
165*
65 *
2000
65
20
20
90
35 *
70
70
65*
135*
70
80
70
30
0
60
0
80
80
110
100
70
70
40
ns
us
ns
ns
ns
ns
ns
ns
ns
us
ns
us
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
us
110*
180*
Unit
120
110
90
100
100
90
90
90
80
ns
ns
ns
ns
ns
us
ns
us
us
us
ns
us
ns
ns
us
us
ns
TdCr (CTz)
110
80
70
us
TdCr (Az)
110
90
80
ns
TdCTr (A)
90
110
75
85
80*
190*
90
100
80
80
65
300
80
80
0
70
-55*
60*
120*
70
135*
-10*
20*
160*
25 *
80
220*
360*
65
70
60
30*
260
300
80
50
0
80*
70
50
0
35 *
~
ns
Rising edge, ~ Falling edge
.....-.----------SHARP - - - - - - - - - - - - - - - 214
Z80/Z80A/Z80B Central Processing Unit
No.
46
47
48
49
50
51
52
53
Parameter
LH0080/LH0080A/LH0080B
Z80 CPU
MIN.
MAX.
TsRESET (Cr)
90
ThRESET (Cr)
0
TsINTf (Cr)
80
ThINTr (Cr)
0
TdMlf (I0RQf 920*
TdCf (IORQf)
110
TdCf (IORQr)
100
TdCf (0)
230
Symbol
RESET ! to clock t setup time
RESET from clock t hold time
INT to clock t setup time
INT from clock t hold time
M1 ! to IORQ ~ delay
Clock ~ to IORQ ~ delay
Clock t to IORQ t delay
Clock ~ to data valid delay
Z80A CPU
MIN.
MAX.
60
0
80
0
565*
85
85
150
All ac parameters assume a load capacitance of 100 pF. Add 10
p s delay for each 50 pF increase in load up to a maximum of 200
pF for the data bus and 100 pF for address and control lines.
• For clock periods other than the minimums shown in the table,
calculate parameters using the following expressions.
* All timings are preliminary and subject to change.
•
Z80B CPU*
MIN.
MAX.
60
0
70
0
365*
70
70
130
Unit
ns
ns
ns
ns
ns
ns
ns
ns
+5V
2.lkO
Footnotes to AC Characteristics
No.
1
2
7
10
11
26
29
31
33
35
45
50
Symbol
TeC
TwCh
TdA (MREQf)
TwMREQh
TwMREQl
TdA (IORQf)
TdO (WRf)
TwWR
TdO (WRf)
TdWRr (0)
TdCTr (A)
TdMIf (IORQf)
Z80
TwCh+TwCl+TrC+TfC
MAX.200ps
TwCh+TfC-75
TwCh+TfC-30
TcC-40
TcC-80
TeC-210
TeC-40
TwCI+TrC-180
TwCI + TrC - 80
TwCl+TrC-40
2TcC+TwCh+TfC-80
AC Test Conditions:
VIHC=Vcc-O.6V
VlH=2.0V
VIL=O.8V
VILC=0.45V
VOH=2.0V
VOL=O.8V
Z80A
TwCh + TwCI + TrC + TfC
MAX.200ps
TwCh+TfC-65
TwCh+TfC-20
TeC-30
TcC-70
TcC-170
TcC-30
TwCl +TrC-140
TwCl+TrC-70
TwCI+TrC-50
2TeC+TwCh+TfC-65
Z80B
TwCh + TwCl + TrC + TfC
MAX.200ps
TwCh+TfC-50
TwCh+TfC-20
TeC 30
TeC-55
TeC 140
TcC 30
TwCl+TrC:-140
TwCl+TrC 55
TwCl+TrC-50
2TeC+TwCh+TfC 50
FLOAT= ±O.5
- - - - - - - - - - - - - - - - - - - - - S H A R P ........ _ - - - . - . . - . _ -
215
.4.~O/Z80AlZ80B
CPU Timing
•
,L~OO80/LH0080A/LH.0080B
Central Processing Unit
(1.) Instruction Opcod~ Fetch
The Z80 CPU executes instructions by proceed-,
ing through a specific sequence of operations:
•
Memory read or write
.' 110 device read or write
.: Jnterrupt acknowledge
The basic clock per;iod is referred to as a T time
or cycle, ahti three or more T cycles make up a
machine cycle (MI, M2 or M3 for instance).
Machine cycles can be extended either by the CPU
automatically inserting one or more Wait states or
by the insertion of Dne or more Wait states by the
user.
The CPU places the contents of the Program
Counter (PC) on the addre~s bus at the start of the
. cycle (Fig. 1). Approximately one;-half clock cycle
lat~r, MREQ goes active.,WheQ active, RD indicate$
that the memory d~ta ca~ be enabled onto the CPU
data bus.
The CPU samples the WAIT input with the falling edge of clock state T,. During clock states T3
and Ti of an Ml cycle dynamic RAM refresh can
, occur while the CPU starts decoding and execu'ting
the instruction. When the Refresh Contro\signal
becomes active, refreshing of dynamic memory can
. take place.
'
CLOCK
Note:
Tw-~ait
cycle added when necessary for slow ancilliary devices.
Fig. 1 Instruction opcode fetch
(2)
Memory Read or Write Cycles
Fig. 2 shows the timing of memo!:L,fead or write
cycles other than~ opcode fetch (M 1) cycle.
The MREQ and RD signals functibn exactly as in
the fetch cycle. 1n a memory write cycle, MREQ
also becomes active when the address bus is stable.
The WR line is aj::tive when the data bus is stable,
so 'that it can be used directly as an R/W pulse to
most semiconductor memories.
•
,(3) Input or Output Cycles
Fig. 3 shows the timing for an 110 read or 110
write operation.
During 110 operations, the CPU automatically inserts a single wait state (T w). This extra wait state
allows sufficient time for an 110 port to decode the
address from the port address lines.
J
--~~----SI-tARP---------~2H5
"
Z80/Z80AlZ80B Central Processing Unit
l
LH0080/LH0080AlLH0080B
CLOCK
Ao-A15
MREQ
WAIT
RO
Read operation
{
~-r--cr--!--J
,/--'---~)"f--"" 1,-+--"\1
00-07
r----
1
WR
Write operation
00-07
Fig. 2
Memory read or write cycles
'-"---'--~'---SHARP-'-'----------
217
. LH0080/LH0080A/LH0080B ( .
ZSO/Z80AlZ80BCentral Processing Unit
"
T2
Tw·
Tw
.
'",
¥'
,
'"
T3
CLOCK
. {RD
I/O read operation
I/O write operation{
Do-D7
WR
Do-D7
--------~============:;~D[a~t~a~o~utL:======}
Note: Tw =One wait cycle automatically inserted by CPU.
Fig. 3 Input or output
(4)
Interrupt requesVacknowledge,cycle
The CPU samples the interrupt signal with the
rising edge of the last clock at the end of any instruction (Fig. 4). When an interrupt is accepted, a
special Ml cycle is generated. During this Ml cy-
cle, IORQ becomes active (instead of MREQ) to indicate that the interrupting device can place an 8-bit
vector on the data bus. The CPU automatically
adds two wait states to this cycle.
CLOCK
Notel: TL=Last state of previous instruction.
Note 2: Two wait cycles automatically inserted by CPU (*).
Fig. 4 Interrupt request/acknowledge cycle
218
LH0080/LH0080A/LH0080B
Z80/Z80AlZ80B Central Processing Unit
(5)
Non-maskable interrupt request cycle
NMI is sampled at the same time as the maskable
interrupt INT but has higher priority and cannot be
disabled under software control.
The subsequent timing is similar to that of a nor-
Last Mcycle
mal instruction fetch except that data put on the
bus by the memory is ignored. The CPU instead executes a restart (RST) operation and jumps to the
NMI service routine located at address 0066H
(Fig. 5).
------~~--------------------Ml------------------~
Last T time Tl
Ts
CLOCK
NMI
Ml
MREQ
RD
RFSH
'Although NMI is an asynchronous input, to guarantee its being
recognized on the following machine cycle, NMI's falling edge
must occur no later than rising edge of the clock cycle preceding
T LAST-
Fig. 15
(6)
Non-maskable interrupt request operation
Bus requesVacknowledge cycle
The CPU samples BUSREQ with the rising edge
of the last clock period of any machine cycle (Fig.
6). If BUSREQ is active, t~CPU sets its address,
data, and MREQ, IORQ; RD, and WR lines to a
high-impedance state with the rising edge of the
next clock pulse. At that time, any external device
can take control of these Iines,usually to transfer
data between memory and I/O devices.
(7)
Reset cycle
RESET must be active for at least three clock cycles for the CPU to properly accept it. As long as
RESET remains active, the address and data buses
float, and the co~trol outputs are inactive. Once
RESET goes inactive, three internal T cycles are
consumed before the CPU resumes normal processing operation. RESET clears the PC register, so
the first opcode fetch will be location 0000 (Fig. 8).
219
..........,..................,....
Z80/Z80A/Z80B C,entral Processing Unit
,~
,
'
......,......,......,-
............
LHQ080ltH0080AlLH0080B
.....,
CLOCK
BUSRQ
Ml
Unchanged
Note: TL=Last state of any M cycle.
Tx=An arbitrary clock c~c1e used by requesting device.
Fig. 6
Ml
Z-bus request/acknowledge cycle
",/E
"'1:'-
MI
MI
CLOCK
HALT
HAL T
r-t®
instruction received
~------------------------
NMI
Note: INT will also force a Halt exit.
Fig. 7
220
Halt acknowledge cycle
Z80/Z80AlZ80B Central Processing Unit
LH0080/LH0080A/LH0080B
CLOCK
RESET
Ml
============~~~~~~~7r-~f~--------------~
Il/IllI
\___
MREQ, ------______~~~~r-----~£rc--------------------~--------
RD, WR,
IORQ,RFSH,
BUSAK,
HALT
Fig. 8
Reset cycle
+5V
+5V
B
A
MI----I
74123
Q 1-------,1
)---- RESET
7408
151588
151588
Reset switch
RESET
Fig. 9
~~------------------
Reset circuit and timing diagram when M1 cycle has no wait state
221
LH0080/LH0080AlLH0080B
Z80/Z80A/Z80B Central Processing Unit
(Reference circuit>
RESET signal.
(2) A walt state in the Ml cycle
Input a RESET signal to start sampling this signal at the clock rising in the Ml cycle's T3 state.
~hen a 1 walt state occurs, this type of RESET signal can be generated by the circuit diagrammed in Fig. 10. In the circuit shown in Fig. 2,
no RESET signal is given during an interrupt acknowledge cycle.
•
The RAM contents may be adversely affected by
resetting the CPU while it is in operation.
To prevent this, a RESET signal should be input
in the following timings.
(1) No walt state in the M1 cycle
Input a RESET signal to start sampling this signal at the clock rising in the Ml cycle's T, state.
Fig. 9 shows a typical circuit generating such a
WAIT signal circle
WAIT
r--- -,---- -- - - ------------,
I
I
+5V
I
+5V·
I
+5V
I
7432
:+5V
I
MI
I
I
I
MREQ
B
I
A
I
CLOCK
74123
Q'-------'"-.....
RESET
7408
+5V.
IS1588
CLOCK
MI
MREQ
--J/
~'-_ _ _ _ _ _ _ _
\.....______-.J/
\1...-.,-_--1,
RESET
\~----Fig. 10 Reset circuit and timing diagram when
M1 cycle has a wait state
--.--.----...-.--SHARP
222
----~.-.-.-
Z80/Z80A/Z80B Central Processing Unit
•
CPU Registers
A Accumulator
B General Purpose
D General Purpose
H General Purpose
F Flag Register
C General Purpose
E General Purpose
L General Purpose
,
,
•
LH0080/LH0080A/LH0080B
F' Flag Register
C' General Purpose
E' General Purpose
L' General Purpose
A' Accumulator
B' General Purpose
D' General Purpose
H' General Purpose
.
8 bits
I Interrupt Vector
I
Index Register
IX
IY
Index Register
Stack pointer
SP
Program Counter
PC
16 bits
R Memory Refresh
.
Architecture
(1) CPU Registers
(i) Program Counter (PC)
The program
counter holds the 16 bits memory address of a cur~
rent instruction. The CPU fetches the contents
from memory address specified by the PC.
The PC feeds the data to the address line, automatically setting the PC value to + 1. When a program jump takes place, a new value is directly set to
the PC.
(ii) Stack Pointer (SP)
The stack pointer
holds the top 16-bit address of the stack with an
external RAM. An external file is based on LIFO
(Last- In, First-Out).
The data are transferred between a CPU-specified register and the stack by a PUSH or POP instruction. The last-pushed data are first popped
from the stack.
(iii) Index Register (IX & IV)
For index
mode addressing, there are independent index registers IX and IY, each of which holds 16-bit reference address.
In the index mode, the index registers are used to
designate the memory area for data input/output.
With an INDEX ADDRESSING instruction, an
effective address comes by adding a one-byte displacement to the register content. This displacement is an integral signed two's complement number
(iv) Interrupt Register (I)
The 280 CPU has
indirect subroutine call mode for any memory area
according to an interrupt. For this purpose, this
register stores the upper 8 bits of memory address
for vectored interrupt processing and the lower 8
bits for the interrupting device.
(.) Ref'esh Registe, IR)
Tb, built-in cefresh register provides user-transparent dynamic
memory refresh. Its lower 7 bits are automatically
incremented during each instruction fetch cycle.
While the CPU records a fetched instruction and
executes the instruction, the refresh register data
are placed on the address bus by a REFRESH control signal.
(vi) Accumulator and Flag Register (A & F)
The CPU has also two independent 8-bit accumulators in combination with two 8-bit flag registers.
The accumulators store an operand or the results of an 8-bit operation. The flag registers, on
the other hand, deal with the results of an 8-bit or
16-bit operation; for example, seeing if the result
is equal to 0 or not.
(Vii) General-Purpose Registers
There are
several pairs of general-purpose registers. In each
pair, they can be used separately or as a 16-bit
paired register. The paired registers are BC, DE,
HL, as well as Be' DE' HL'. Either of these sets can
work by an "Exchange" instruction at any time on
a program.
(2)
Arithmetic/Logical Unit (ALU)
An 8-bit arithmetic/logical operation instruction
is executed by the ALU inside the CPU. The ALU
connects to each register through the internal bus
for data transfer between them.
(3)
Instruction Register, CPU Control
Each instruction is read out of the memory, held
in the instruction register, and decoded. The con-
'-~'---'---SHARP'-''-------
223
14 ~
\
Z80/Z80A/Z80BCentral 'Processing Unit
LH0080/LH0080A/LH0080B
.......~.....,_ _................,............ . -...............-..r......._ _...............
/
trol unit controls this action and gives control signals necessary to read and write data from and to
the registers.
The,control unit also makes ALU control signal
and other external control signals.
(Interrupts: General Operation> The Z~W,CPU
accepts two interrupt input signals: NMI and INT_
The NMI is a non-maskable interrupt and has the
highest priority. INT is a lower priority interrupt
and it requires th,at interrupts be enabled in software in order to operate.
(1)
vice places an instruction on the data bus. This isa
Restart instruction or a Call instruction.
(ii) Mode 1 Interrupt Operation.
Mode 1
operation is very similar to that for the NML The
prir-cipal difference is that the Mode 1 interrupt
has a restart location of 0038H only.
,(iii) Mode 2 Interrupt Operation.
This interrupt 'mode has been designed to utilize most
effectively the capabilities of the Z80 microprocessor and its associated peripheral family. The
interrupting peripheral device selects the starting
address (16 bits) of the interrupt service routine. It
does this by placing an 8-bit vector on the data
bus during the interrupt acknowledge cycle. The
CPU forms a pointer using this byte as the lower
8-bits and the contents of the I register as the upper 8-bits. This points to an entry in a table of
addresses for interrupt service routines. The CPU
then jumps to the routine at that address.
All the Z80 peripheral devices have the interrupt priority circuit with a daisy-chain configuration. puring an interrupt acknowledge cycle, vectors are automatically fed. For more details, refer
to the Z80 PIO description. _
Non-Maskable Interrupt (NMi)
The non-maskable interrupt will be accepted at
all times by the CPU.
After recognition of the NMI signal, the CPU
jumps to restart location 0066H.
(2) Maskable Interrupt (INT)
The maskable interrupt, INT, has three prog-ram mabie response modes available.
(i) Mode 0, Interrupt Operation.
This
mode'is similar to the 8080Amicroprocessor interrupt service procedures. The interrupting de-
Table
~op::: :~::
t
_1;---ypOinte: b,'_S____,7_bi_ts
101
_ t'-___ From application device
I register contents
To the beg inning of service rotine
Fig. 1
Mode 2 interrupt diagram
- . . . . - . - - - - - - - S H A R p . - . . . . - . . - - - - - - .......... - 224
Z80/Z80A/Z80B Central Processing Unit
•
LH0080/LH0080A/LH0080B
Instruction Set
Table 1 8-bit load group
LD r, r
LD r, n
Symbolic
operation
,
r+-r
r+-n
LD r,(HL)
LD r, (IX+d)
r+- (HL)
r+- (IX+d)
LD r, (IY+d)
r+- (IY+d)
LD (HL), r
LD (IX+d), r
(HL)+-r
(IX + d)+-r
LD (IY+d), r
(IY+d)+-r
LD (HL), n
(HL)+-n
Mnemonic
,
HEX code
OP code
76 543 210 (Basic) C
,
01
r
r
40+
00 r 110
06+
+- n -+
01 r 110
46+
11 011 101
DD
01 r 110
46+
+- d -+
11 111 101
FD
01 r 110
46
+- d -+
01 110 r
70+
11 011 101
DD
01 110 r
70+
+- d -+
11 111 101
FD
01 110 r
70+
+- d -+
00 110 110
36
+- 0 -+
•
•
•
•
3
5
19
• ••• • •
• • • • • •
1
3
2
5
7
19
• ••• • •
3
5
19
2
3
10
4
5
19
• • • • • •
4
5
19
OA
1A
3A
• • • • • •
•••• ••
• • • • • •
1
1
3
2
2
4
7
7
13
02
12
32
• • •• • •
• • • • • •
• • • • • •
1
1
3
2
2
4
7
7
13
•
t
IFF
t
0
0
2
2
9
•
t
IFF
t
0
0
2
2
9
2
2
9
2
2
9
DD
36
LD (IY+d),
0
(IY + d)+-o
11
00
++00
00
00
++00
00
00
++11
01
11
01
11
01
11
01
FD
36
LD (BC), A
LD (DE), A
LD (00), A
(BC) +- A
(DE) +- A
(00) +- A
LD A,I
A +- I
LDA,R
A+-R
LDI,A
I +- A
LDR,A
R+-A
0
-+
0
-+
000 010
010 010
110 010
0
101
010
101
011
101
000
101
001
• •• • • •
• • • • • •
Comments
r,r
000
001
010
011
100
101
111
Reg.
B
C
D
E
H
L
A
-+
001 010
011 010
III 010
0
••
• •
••
• •
No. of No. of No. of
Bytes MCycles T States
1
1
4
2
2
7
• ••• • •
11 011 101
00 110 110
+d -+
+- 0
-+
0
•
•
•
•
H
7
19
(IX + d)+-n
A+- (BC)
A +- (DE)
A+- (00)
•
•
•
•
N
2
5
0
LD A, (BC)
LD A, (DE)
LD A, (00)
•
•
•
•
Flags
S
P/V
1
3
LD (IX+d),
111 101
110 110
d -+
Z
-+
-+
101
111
101
111
101
III
101
111
ED
57
ED
5F
ED
47
ED
4F
• • • •• • •
• • • • • •
Notes: r, r' means any of the registers A, B, C, D, E, H, L, IFF the content of the interrupt enable flip-flop, (IFF) is copied into the P/V flag_
Flags: C (carry), Z (zero), S (sign), P/V (parity/overflow), H (half carry), N (add/substract)_
: • =unchanged, O=reset, 1 =set, X=undefined.
: t set or reset according to the result of the operation.
-----~---SHARP-.----.-..---
225
\
.
LH0080/LH0080A/LH0080B
Z80/Z80A/Z80B Central Processing Unit
Table 2
OP code
HEX code
76 543 210 (Basic) C
00 ddO 001
01+
0 -+
0
11 011 101
DO
00 100 001
21
0
0
11 111 101
FD
00 100 001
21
0
n
00 101 016
2A
n
n
11 101 101
ED
01 dd1 011
4B+
+n
0
11 011 101
DD
00 101 010
2A
n
n
11 111 101
FD
00 101 010
2A
LD dd, nn
Symbolic
operation
dd ~nn
LD IX, nn
IX -
LD IY, 00
IY -00
10 HL, (00)
H +- (00+1)
L-(no)
10 dd, (00)
ddH +- (00+1)
ddL - (no)
10 IX, (no)
IXH +- (nn+ 1)
IXL - (nn)
LD IY, (nn)
IYH +- (on+1)
IYL - (rin)
10 (nn), HL
(nn+1) 4 - H 00 100
n
(nn) - L
n
(on+1) +- ddH 11 101
01 ddO
(nn) - ddL
n
n
(on+ l)+-IX~
11 011
(nn) +- IXL
00 100
n
n
(nn+ l)+-IYH
11 111
00 100
(nn) - IYL
n
n
SP -HL
11 111
11 011
SP - IX
11 111
11 111
SP - IY
11 111
(SP-2)+-qqL 11 qqO
(SP-1)+-qqH
(SP-2)+-IXL 11 011
(SP-1)+-IXH 11 100
(SP-2)+-IYL 11 111
(SP-l)+-IYH 11 100
qqH +- (SP+ 1) 11 qqO
qqL - (SP)
IXH+-(SP+ 1) 11 011
IXL +- (SP)
11 100
IYH'" (SP+1) 11 111
IYL - (SP) , 11 100
Mnemonic
10 (nn), dd
10 (nn), IX
10 (nn), IY
10 SP, HL
10 SP, IX
10 SP, IY
PUSH qq
PUSH IX
PUSH IY
POP qq
POP IX
POPIY
Notes:
Flags:
226
00
16-bit load group
---
No. of
N
H
• • • • • •
• • • • ••
• • • • ••
---.
.fl
.,.
Flags
pd S
• •
••
• • • • ••
-- -- --- --- --
----
Z
• • • • • •
No. of
No. of
Bytes M CyCles T States
3
10
3
4
4
14
4
4
14
3
5
16
4
6
20
4
6
20
4
6
20
3
5
16
4
6
20
010
22
101
011
ED
43+
• • • • • •
• • • • • •
• • • • ••
101
010
DD
22
• • • • ••
4
6
20
101
010
FD
22
• • • • • •
4
6
20
001
101
001
101
001
101
F9
DD
F9
FD
F9
C5+
1
2
1
2
6
10
2
2
10
1
3
11
101
101
101
101
001
DD
E5
FD
E5
Cl+
2
4
15
2
4
15
1
3·
10
101
001
101
001
DD
E1 .
2
4
14
2
4·
14
--
----
FD
E1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• •
• •
• •
••
.. •
••
• •
• •
• •
••
• •
••
••
• •
••
• •
• •
• •
Comments
dd
00
01
10
11
no : 2·byte oumber.
Lower byte just
after opcode.
Upper byte comes
next.
qq
00
01
10
11
dd is any of the register pairs BC, DE, HL, SP.
qq is any of the register pairs AF, BC, DE, HL.
(PAIR)H, (PAIR)L refer to high order and low order eight bits of the register pair respectively, e.g., BCL=C, AFH=A.
• =unchanged, O=reset, 1 =set, X=undefined, =set or reset according to the result of the operation
*
Reg.
BC
DE
HL
SP
Reg.
BC
DE
HL
AF
Z80/Z80A/Z80B Central Processing Unit
Table 3
Mnemonic
EX DE, HL
EX AF,AF'
EXX
EX (SP), HL
EX (SP), IX
EX (SP), IY
LDI
LDIR
LDD
LDDR
CPI
CPIR
CPD
CPDR
Symbolic
operation
DE-HL
AF-AF'
~~I'fj
IDE-DE'
\lIL
HL'
H ..... (SP+1)
L-(SP)
IXH ..... (SP+1)
IXL - (SP)
IYH ..... (SP+1)
IYL - (SP)
(DE) - (HL)
DE - DE+1
HL - HL+1
BC - BC-1
(DE) - (HL)
DE - DE+1
HL - HL+1
BC - BC-1
If BC=O end
(DE) - (HL)
DE - DE-1
HL - HL-1
BC - BC-1
(DE) - (HL)
DE -DE-1
HL - HL-l
BC - BC-1
If BC=O end
A- (HL)
HL ~ HL+1
BC - BC-1
A- (HL)
HL - HL+1
BC - BC-1
If A= (HL) or
BC=O end
A- (HL)
HL - HL-1
BC - BC-1
A- (HL)
HL - HL-1
BC - BC-1
If A= (HL) or
BC=O end
LH0080/LH0080A/LH0080B
Exchange, block transfer, block search groups
HEX code
OP code
76 543 210 (Basic) C
11 101 011
EB
00 001 000
08
11 011 001
D9
Z
Flags
S
P/V
N
H
••••••
••••••
• • • • • •
11 100 011
E3
11
11
11
11
11
10
011 101
100 011
111 101
100011
101 101
100 000
DD
E3
FD
E3
ED
AO
11 101 101
10 110 000
ED
BO
11 101 101
10 101 000
ED
A8
11 101 101
10 111 000
ED
B8
11 101 101
10 100 001
ED
Al
11 101 101
10 110 001
ED
B1
11 101 101
10 101 001
ED
A9
11 101 101
10 III 001
ED
B9
• • ••••
••••••
••••••
••
t
10
7
7
19
t
t
t
1
1
3
1
3
6
4
11
23
t
3
6
23
1
0
0
t
t
1*2
1
3
3
1*2
3
6
6
Note: V and P mean overflow and parity, respectively.
Flags: • = unchanged
O=reset
l=set
X=undefined
J = set or reset according to the 'result of the operation
.
7
19
Comments
r
000
001
010
011
100
101
111
Mnemonic
ADD
ADC
SUB
SBC
AND
OR
XOR
CP
Reg.
B
C
0
E
H
L
A
k
000
001
010
011
100
110
101
111
S=r, n, (HL),
(IX + d), (IY +d)
,
Mnemonic
INC
DEC
t
100
101
4*2
m=r, (HL),
11
(IX+d), (lY+d)
23
23
,.1: depends on s.
,.2: depends on m.
r
- - - . - -........... ----SHARP---~~--------~
228
LH0080/LH0080A/LH0080B
Z80/Z80A/Z80B Central Processing Unit
Table 5
General purpose arithmetic and CPU control groups
CPL
Symbolic
OP code
HEX code
76 543 210 (Basic) C
operation
Decimal
00 100 III
27
t
adjustment
(add/subtract)
A-A
00 101 111
2F
NEG
A-O-A
CCF
SCF
NOP
HALT
DI
EI
1M 0
C-C
C-1
No operation
CPU halted
IFF-O
IFF - 1
Set interrupt
mode 0
Set interrupt
mode 1
Set interrupt
mode 2
Mnemonic
DAA
1M 1
1M 2
11
01
00
00
00
01
11
11
11
01
11
01
11
01
101 101
000 100
111 111
110 111
000 000
110 110
110011
111 011
101 101
000 110
101 101
010 110
101 101
011 110
ED
44
3F
37
00
76
F3
FB
ED
46
ED
56
ED
5E
Z
t
Flags
S
P t
P/V
N
•
H
t
No. of No. of No. of
Comments
Bytes M Cycles T States
1
Decimal adjust
4
1
accumulator.
••••
1
1
1
1
4
t t
1
t
2
2
8
0
0
X
0
1
1
1
1
1
1
2
1
1
1
1
1
1
2
4
4
4
4
4
4
8
2
2
8
2
2
8
t
1
•
•
•
•
•
•
•
V
t
• •
••
••
• •
••
• •
• •
• •
• •
•
•
•
•
•
•
•
•
•
• •
••
••
••
• •
••
• •
Complement
accumulator
(one's complement).
Negate acc.
(two's complement).
Complement carry flag.
Set carry flag.
Interrupt not enable
Interrupt enable
Set interrupt mode.
Note : IFF indicates the interrupt enable flip· flop, CY indicates the carry f1ip·f1op.
Flags: • = unchanged, O=reset, 1 =set, X=undefined, , =set or reset according to the result of the operation
Table 6
ADD IX, pp
Symbolic
operation
HL-HL
+ss
HL-HL
+ss+C
HL-HL
-ss-C
IX-IX+pp
ADD IY, rr
IY -
Mnemonic
ADD HL, ss
ADC HL, ss
SBC HL, ss
INC ss
INC IX
ss IX -
INC IY
IY -
DEC ss
DEC IX
ss IX -
DECIY
IY -
16-bit arithmetic group
OP code
HEX code
76 543 210 (Basic) C
00 ssl 001
09+ t
11
01
11
01
11
00
IY+rr 11
00
ss+l 00
IX+l 11
00
IY+1 11
00
ss-l 00
IX-l 11
00
IY-l 11
00
101
ssl
101
ssO
011
pp1
111
rr1
ssO
011
100
111
100
ssl
011
101
III
101
101
010
101
010
101
001
101
001
011
101
011
101
011
011
101
011
101
011
ED
4A+
ED
42+
DD
09+
FD
09+
03+
DD
23
FD
23
OB+
DD
2B
FD
2B
Flags
S
Z
P/V
t t
V
t t
V
No. of No. of No. of
Bytes M Cycles T States
1
11
3
N
0
H
X
t
0
X
2
4
15
t
1
X
2
4
15
t
• • •
0
X
2
4
15
t
•
•
•
•
•
•
•
2
4,
15
•
•
•
•
•
•
• • •
Comments
ss
00
01
10
11
••
••••
• • • •
• • • •
0
X
• • • •
••••
• • • •
\
pp
00
01
10
1
2
1
2
6
10
2
2
10
1
2
1
2
6
10
rr
00
01
10
2
2
10
11
11
Reg.
BC
DE
HL
SP
Reg.
BC
DE
IX
SP
Reg.
BC
DE
IY
SP
Note: ss is any of the register pairs BC, DE, HL, SP.
pp is any of the register pairs BC, DE, IX, SP.
rr is any of the register pairs BC, DE, IY, SP.
Flags: • =unchanged, O=reset, 1 =set, X=undefinede, , =set or reset according to the result of the operation
229
zao/zaOA/zaOB Central Processing Unit
Table 7
Mnemonic
Symbolic
operation
LHooao/LHooaOA/LHooaoB
Rotate arid shift groups
HEX code
OP code
76 543 210 (Basic) C
Z
Flags
S
PlY
N
No. of No. of No. of
H ' Bytes MCycles T States
0
0
1
1
4
Rotate left circular
accumulator.
0
0
1
1
4
Rotate left
accumulator.
p
0
1
1
4
Rotate right circulart
accumulator.
0
0
1
1
4
Rotate right
accumulator.
Rotate left circular
register r.
RLCA
~
A
00 000 111
07
+
RLA
~
A
00 010 111
17
+
RRCA
~
A
00 001 111
OF
+
On
IF
+
CB
00+
CB
06+
DD
CB
+ t
p
t
0
0
2
2
,8
t t
p
t
0
0
2
4
15
t t
p
t
0
0
4
6
23
t t
p
t
0
0
4
6
23
+
0
0
RRA
Lii3=@lJ
A
R,LCr
RLC (HL)
RLC (IX+d)
~
r. (HL).
(IX+d).
(IY+d)
RLC (IY+d)
00
11
00
11
00
11
11
<-
00
11
11
<-
00
111
001 011
k
r
001 011
k 110
011 101
001 011
d .....
k 110
111 101
001 011
d
k 110
.....
06+
FD
CB
• • •
• ••
• ••
•••
,
Comments
r
000
001
010
011
100
101
111
Reg.
B
C
D
E
H
L
A
06+
RLm
~m
t +
p
RRC m
~
m
t +
p
+
0
0
RRm
LiBi=@J
+ +
P
+
0
0
m
'2*
2*
2
4
4
4
6
6
Mnemonic
RLC
RRC
RL
RR
8,* !
SLA
15
SRA
23
SRL
23
k
000
001
010
011
100
101
111
SLAm
~
m
t +
p
t
0
0
SRAm
~
t t
,P
t
0
0
m=r. (HL).
(IX+d). (IY+d).
SRL m
~
m
t t
p
t
0
0
* depends on m.
RLD
A~
RRD
A~
11 101 101
(HL) 01 101 111
(HL)
11 101 101
01 100 111
ED
6F
•
t
p
+
0
0
2
5
18
ED
67
•
t
p
t
0
0
2
5
18
Flags: • =unchanged
O=reset
l=set
X = undefined
t = set or reset according to the result of the operation
230
Rotate digit left and
right between the
accumulator and
location (HL).
The content of the
upper half of the
accumulator is un·
affected.
Z80/Z80AlZ80B Central Processing Unit
LH0080/LH0080AlLH0080B
Table 8 Bit set, reset and test group
BIT b, r
Symbolic
operation
Z +- rb
BIT b, (HL)
Z +- (HL)b
BIT b, (IUd)
Z +- (IX+d)b
BIT b, (IY+d)
Z +- (IY+d)b
Mnemonic
SET b, r
n+-1
SET b, (HL)
(HL)b +- 1
SET b, (IX+d)
(IX+d)b +- 1
SET b, (IY+d)
(IY+d)b +- 1
HEX code
OP code
76 543 210 (Basic) C
11 001 011
CB
01
r
40+
b
11 001 011
CB
01 b 110
46+
11 011 101
DD
11 001 011
CB
+- d .....
01 b 110
46+
11 111 101
FD
11 001 011
CB
+- d .....
01 b 110
46+
11 001 011
CB
r
a
b
11 001 011
CB
06+
a b 110
11 011 101
DD
11 001 011
CB
+- d .....
a b 110
06+
11 111 101
FD
11 001 011
CB
+- d
a b 110
06+
•
•
•
•
t
Flags
S
X X
N
0
H
1
t
X
X
0
1
2
3
12
t
X
X
0
1
4
5
20
t
X
X
0
1
4
5
20
Z
PlY
• • •• ••
• • • • ••
• • •• • •
• • •• • •
No. of No. of No. of
Bytes M Cycles T States
2
8
2
2
2
8
2
4
15
4
6
23
4
6
23
.....
RES b, m
fib +- 0
2*
2*
8*
2
4
4
4
6
6
15
23
23
Comments
r
000
001
010
011
100
101
111
Reg.
B
C
D
E
H
L
A
b
000
001
010
011
100
101
110
111
Bit Tested
0
1
2
3
4
Mnemonic
SET
RES
5
6
7
a
11
10
m=r, (HL),
(IX+d), (IY+d)
* depends on m
Note: The notation mb indicates bit b (0 to 7) or location ffi.
Flags: • = unchanged
o= reset
l=set
X=undefined
; = set or reset according to the result of the operation
-.....-.-------SHARP------------231
Z80/Z80Al~80B C~ntral processing Unit'
LH0080/LH0080AlLH0080B
Table 9 Jump group
OP code
HEX code
76 543 210 (Basic) C
11 000 011
C3
n -+
n -+
If condition cc
11 cc 010
C2+
is true PC ... nn,
n -+
otherwise conn -+
tinue
18
PC - PC+e 00 011 000
e-2 -+
If C=1
00 111 000
38
e-2
PC - PC+e
If C=O
continue
If C=O
00 110 000
30
e-2 -+
PC - PC+e
If C=1
continue
If Z=1
00 101 000
28
e-2 \ -+
PC - PC+e
IfZ=O
continue
If Z=O
00 100 000
20
e-2 -+
PC - PC+e
IfZ=1
continue
PC-HL
11 101 001
E9
PC -IX
11 011 101
DD
11 101 001
E9
11 III 101
PC -IY
FD
11 101 001
E9
10
If B - B-1 00 010 000
Bio
e-2 -+
PC - PC+l
If B=O
continue
Symbolic
operation
pc,- nn
Mnemonic
JP nn
• •
--
JR e
....
JR NC, e
...
••••••
....
JP (HL)
JP (IX)
JP (IY)
DJNZ, e
•
•
•
•
....
)
!
••••
• •• • • •
....
JR NZ, e
H
• • • • • •
....
JR Z, e
N
••• •• •
••••••
....
JR C, e
Flags
S
PIV
••••••
--
JP cc, nn
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
No. of No. of No. of
Bytes M Cycles T States
3
10
3
3
3
10
3
3
10
2
3
12
2
3
12
2
2
7
2
3
12
2
2
7
2
3
12
2
2
7
2
3
12
2
2
7
1
2
1
2
4
8
2
2
8
2
-3
2
2
Comments
cc
000
001
010
011
100
101
110
III
Condition
NZ
Z
NC
C
PO
PE
P
M
NZ : non-zero
Z : zero
C: carry
PO : parity odd
PE : parity even
P: sign positive
M : sign negative
13
8
-Note: e represents the extension in the relative addressing mode.
e is a signed two's,complement number in the range -126.129>
e -2 in the opcode provides an effective address of pc+e as PC i,s incremented by 2 prior to the addition of e.
e itself is obtained from opcode position_
Flags: • = unchanged
O=reset
1=set
X=undefined
t =set or reset according to the result of the operation
<
~-------~--SHARP-"---'------
232
Z80/Z80AlZ80B Central Processing Unit
LH0080/LH0080A/LH0080B
Table 10 Call and return group
Mnemonic
CALL nn
CALL cc, nn
RET
RET cc
RET!
RETN
RST p
Symbolic
operation
(SP-1) .... PCH
(SP-2) .... PCL
PC -nn
If condition cc is
false continue,
otherwise same
as CALL nn
PCL - (SP)
PCH .... (SP+ 1)
If condition cc is
false continue,
otherwise same
as RET
Return from
interrupt
Return from
non· mask able
interrupt
(SP-l) +- PCH
(SP - 2) +- PCL
PCH - 0
PCL - P
OP code
HEX code
76 543 210 (Basic) C
11 001 101 CD
n -+
n -+
11 cc 100 C4+
n -+
n -+
Z
Flags
S
PlY
N
H
•••• ••
---
••••••
11 001 001
C9
11 cc 000
CO+
11
01
11
01
101
001
101
000
101
101
101
101
ED
4D
ED
45
11
t
111
C7+
••••••
••••••
• • • • ••
• • • • ••
• • • • ••
No. of No. of No. of
Bytes M Cycles T States·
3
17
5
3
5
17
3
3
10
1
3
10
1
'3
11
1
1
5
2
4
14
2
4
14
1
3
11
Comments
,
cc
000
001
010
011
100
101
110
111
Condition
NZ
Z
NC
C
PO
PE
P
M
r
000
001
010
011
100
101
110
111
p
OOH
08H
10H
18H
20H
28H
30H
38.
Flags: • = unchanged
O=reset
l=set
X = undefined
• = set or reset according to the result of the operation
'--''-~-----SHARP'-''---~----
233
zao/zaOA/zaOB Central Processing Unit
lHooaO/lHOOaOAllHOOaOB
Table 11 Input and output group
IN A, (n)
Symbolic
operation
A+- (n)
IN r, (C)
r +- (C)
INI
OUT (n),A
(HL) +- (C)
B +- B-1
HL +- HL+1
(HL) +- (C)
B +- B-1
HL +- HL+l
Repeat until
B=O
(HL) +- (C)
B +- B-1
HL +- HL-1
(HL) +- (C)
B +- B-1
HL +- HL-1
Repeat until
B=O
(n) +- A
OUT (C), r
(C) +- r
OUTI
(C) +- (HL)
Mnemonic
INIR
INO
IN OR
OTIR
OUTD
OTDR
B +- B-1
HL +- HL+l
(C) +- (HL)
B +- B-1
HL +- HL+l
Repeat until
B=O
(C) +- (HL)
B +- B-1
HL +- HL-l
(C) +- (HL)
B +-B-1
HL +- HL-l
Repeat until
B=O
OP code
HEX code
76 543 210 (Basic) C
11011 011
DB
+- n .....
11 101 101
ED
01 r 000 .40+
11 101 101
ED
X
10 100 010
A2
11 101 101
10 110 010
N
H
P
t
0
t
t
CD
X
X
1
X
2
1
@
X
X
1
X
2
P/V
t
• • • • • •
•
ED
B2
X
No. of No. of No. of
Comments
Bytes MCycles T States
n ..... Ao-A7
2
3
11
Aex ..... As-A15
12
2
3
Flags
S
Z
4
16
5
21
(If Bi'O)
2
4
16
(If B=O)
11 101 101
10 101 010
ED
AA
X
t
CD
X
X
1
X
2
11 101 101
10 111 010
ED
BA
X
1
X
X
1
X
2
4
16
5
21
C"'" Ao-A7
B ..... As-A15
r.
000
001
010
011
100
101
111
Reg.
B
C
0
E
H
L
A
(If Bf 0)
.
@
2
4
16
(If B=O)
11
+11
01
11
10
010 011
n .....
101 101
r 001
101 101
100 011
D3
11 101 101
10 110 011
ED
B3
ED
41+
ED
A3
• • • • • •
• • • • ••
n ..... (A·BUS)O-7
Aex ..... (A·BUS)S-15
2
3
11
2
3
12
4
16
C ..... Ao-A7
5
21
B ..... As-A15
X
t
CD
X
X
1
X
2
X
1
X
X
1
X
2
(If BfO)
@
2
4
16
(If B=O)
11 101 101
10 101 011
ED
AB
X
t
CD
X
X
1
X
2
11 101 101
10 111 011
ED
BB
X
1
X
X
1
X
2
4
16
5
21
(If Bfa)
@
2
4
16
(If B=O)
CDlf the result of B-1 is zero the Z flag is set, otherwise it is reset.
®Z flag is set upon instruction completion only.
Flags: • =unchanged
O=reset
l=set
X=undefined
l = set or reset according to the result of the operation
Note:
------~-.-.--SHARP -.-....,-----~.-.--
234
Z80/Z80A/Z80B Parallel -Input/Output Controller
LH0081.1LH0081A1LH0081 B
LH0081/LH0081A/LH0081B
Z801Z80AlZ80B Parallel Input/Output Controller
•
Description
The 280 product line is a complete set of microcomputer components, development systems and
support software. The 280 microcomputer component set includes all of the circuits necessary to
build high-performance microcomputer systems
with virtually no other logic and a minimum number of low cost standard memory elements.
The LH0081 280 PIO (280 PIO for short below)
is a programmable two port device which provides
TTL compatible interfacing between peripheral devices and the 280 CPU. The 280 CPU configures
280 PIO to interface with standard peripheral devices such as tape punchers, print~rs, keyboards,
etc.
The LH0081A 280A and LH0081B 280B PIO
are the high speed version which can opeate at the
4MHz and 6MHz system clock, respectively.
•
•
Pin Connections
D6
BfA SEL
6
Features
1. Two independent 8-bit bidirectional peripheral
interface ports with "handshake" data transfer
control
2. N-channel silicon -gate process
3. Anyone of the following four modes of operation may be selected.
• Byte output mode
• Byte input mode
• Byte bidirectional bus (available on Port A
only)
• Bit mode
4. Programmable interrupt
5. Vectored daisy chain priority interrupt logic
included
6. The port B outputs can drive Darlington transistors
7. All inputs and outputs fully TTL compatible
8. Single +5V power supply and single phase
clock
9. 40-pin dual-in-line package
Top View
235
Z80/Z80A/Z80B ParallellnputlOutput Controller
•
LH0081 ILH0081 AlLH0081B
Block Diagram
Internal
Control Logic
;:;
fr
"
::.
c.
..:;"
0
...:
u
System Data Bus
Port A
Data Bus
.
's.
0
~
....:I
0
Il.
-=fr
"
c.
..:;"
0
::.
'"
Port AlB Select
"
o:l
:::>
Il.
u
-=fr
Machine Cycle 1
"
::.
c.
..:;"
0
I/O
Port B
Data Bus
o:l
..
~
Interrupt
0
Control Logic
> >
'"+ 2Q
z
u
u
>
"
-'"
u
0
U
e
'"
'»"
Ul
~
~
Il.
BReady
B Strobe
..:;
''""or" '" 0-=
'" :c :c'"
0::
~
" ~"
~
:::s
oj
oj
.. ..
.E'" ..:;!.. !..
~
c.
:::s
~
c.
:::s
..:;
'-'-~-----SHARP-------'-
236
Z80/Z80AlZ80B Parallel Input/Output Controller
•
Pin Description
Pin
Do-D 7
-
B/A SEL
Meaning
Data bus
I/O
Bidirectional
3-state
Port B or A select
I
Control or data select
I
CE
Chip enable
I
CLOCK
System clock
I
-
C/D SEL
-
-
M1
-IORQ
RD
lEI
lEO
INT
Ao-A 7
---
Machine cycle one
Input/ output
request
I
I
Read cycle status
Interrupt enable in
Interrupt enable out
Interrupt request
Port A bus
I
I
0
Open drain, 0
Bidirectional
3-state
A STB
Port A strobe
I
A RDY
Port A ready
0
Bo-B 7
Port B bus
--
•
LH0081/LH0081A/LH0081B
Bidirectional
3-state
B STB
Port B strobe
I
B RDY
Port Bready
0
Function
System data bus.
Defines which port is accessed. A high selects port B,
and a low port A.
Defines the type of data transfer on the data bus. A high
selects control, and a low data.
Active "Low". A low enables the CPU to transmit and
receive control words and data.
Standard Z80 system clock used for internal synchro·
nization signals.
Active "Low". Indicates that the CPU is acknowledging
-an interrupt, when both M1 and IORQ are active.
Active "Low". Read operation when RD is active, and
write operation when it is not active. Indicates that the
CPU is acknowledging an interrupt, when both IORQ
and M1 are active.
Active "Low". Read operation when active.
Active "High". Forms a priority-interrupt daisy-chain.
Active "High". Forms a priority-interrupt daisy-chain.
Active- "Low". Active when requesting an interrupt.
Transfers information between port A and a peripheral
device.
Active "Low". Used as a handshake line for data transfer synchronization on port A. Not used in the bit control mode.
Active "High". Used as a handshake line for data transfer synchronization on port A. Not used in the bit control mode.
Transfers information between port B and a peripheral
device.
Active "Low". Used as a handshake line for data transfer synchronization on port B. Not used in the bit control mode.
Active "High". Used as a handshake line for data transfer synchronization on port B. Not used in the bit control mode.
-
Absolute Maximum Ratings
Parameter
Input voltage
Output voltage
Operating temperature
Storage temperature
Symbol
V IN
V OUT T oDr
T sto
Ratings
-0.3-+7
-0.3-+7
0-+70
-65-+150
Unit
V
V
·C
·C
237
Z80/ZS0A/Z80B Parallel Input/Output Controller
LH008t1LH0081AILH0081 B
•
(Vcc =5V±5%,'Ta=0-+70t)
DC Characteristiqs
Parameter
input low voltage
Clock input high voltage
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Supply current
Input leakage current
3 state output! data
bus input leakage current
Darlington drive current
Clocl~
•
Symbol
Conditions
MLN.
-0.3
Vee- 0.6
-0.3
2.0
VILe
V IHe
VIL
VII'!
IOL =2mA
IoH = -250pA
VoH =1.5V
VOL
VOH
Icc
I ILl I
TYP.
2.4
O:;;;VIN~Vee
100
10
I Iz I
0:;;;V1N:;;;V ee
10
IOHD
REXT =390n
•
pA
rnA
(f=lMHz, Ta=25t)
Symbol
Conditions
CCLOCK
C1N
COUT
MIN.
. Parameter
TYP.
Unmeasured pins returne<1
to ground
MAX.
12
7
10
Unit
pF
pF
pF
(Vcc=5V±5%, Ta=0-+70t)
AC Characteristics
No.
Symbol
Z80
MIN.
400
170
170
PIO
MAX.
(Note 1)
2000
2000
30
30
Z80A
MIN.
250
105
105
PIO
Z80B PIO (Note 9)
MAX.
MIN.
MAX.
(Note 1) 165
(Note 1)
2000·
65
2000
2000
65
2000
20
30
20
30
Unit
TcC
TwCh
TwCl
TfC
TrC
17
IEI ~ to lEO ~ delay
TdlEI (IEOf)
190
130
120
ns
18
IEI t to lEO t delay
(After ED decode)
TdlEI (IEOr)
210
160
160
ns
6
7
8
9
10
11
12
13
14
15
16
238
TsCS (RI)
Th
TsRI (C)
TdRI (DO)
50
50
50
ns
0
0
0
ns
430
380
300
ns
ns
160
110
70
ns
115
TdRI (DOs)
115
70
Note
ns
ns
ns
ns
ns
Clock cycle time
Clock width (high)
Clock width (low)
Clock fall time
Clock rise time
CE, B/ A, C/O to RD, IORO ~
setup time
Any hold times for specified.
setup time
RD, IORQ to clock t setup time
RD, IORQ ~ to data out delay
RD, IORQ t to data out
float delay
Data in to clock t setup time
IORQ ~ to vector out delay
(INT ACK cycle)
M1 ~ to clock t setup time
M1 t to clock ~ setup time
(M1 cycle)
Ml ! to lEO ~ delay (interrupt
immediately preceding M1 ~ )
tEl to IORQ ~ setup time
(INT ACK cycle)
1
2
3
4
5
Unit
V
V
V
V
V
V
rnA
pA
-1.5
CapaCitance
Parameter
Clock capacitance
Input capacitance
Output capacitance
MAX.
0.45
Vee+ 0.3
0.8
5.5
0.4
6
2
50
50
40
ns
CL-50pF
TdIO (001)
340
160
120
ns
3
TsMl (Cr)
210
90
70
ns
TsMl (Cf)
0
0
0
ns
8
ns
5,7
ns
7
TsDI (C)
TdMI (lEO)
TsIEI (10)
.
300
140
100
190
140
100
5
C~=50pF
5
LH0081/LH0081A/LH0081B
Z80/Z80AlZ80B Parallel Input/Output Controller
Z80A PIO
MIN.
MAX.
MIN.
220
200
170
ns
TdC (RDYr) 200
190
170
ns
TdC (RDYf)
TwSTB
150
150
140
150
120
120
ns
ns
5
CL=50pF
5
4
TsSTB (C)
220
220
150
ns
5
ns
5
Parameter
Symbol
19
IORQ t to clock ! setup time
(to activate READY on next
clock cycle)
TelO(C)
20
Clock
21
22
Clock ! to READY ! delay
STROBE pulse width
STROBE t to clock ! setup
time (to activate READY on
next clock cycle)
IORQ t to PORT DATA stable
delay (Mode 0)
PORT OATA to STROBE t
setup time (mode 1)
STROBE ! to PORT OAT A
stable (mode 2)
STROBE t to PORT OAT A
float delay (mode 2)
PORT OAT A match to INT !
delay (mode 3)
STROBE t to INT ! delay
23
24
25
26
27
28
29
t Rising edge,
Note
Note
Note
Note
Note
Note
Note
Note
Note
1:
2:
3:
4:
5:
6:
7:
8:
9:
!
to READY
t
delay
Z80B PIO (Note 9)
Z80 PIO
MIN.
MAX.
No.
TdIO (PO)
200
TsPD (STB) 260
TdSTB (PO
230
160
180
230
MAX.
Unit
Note
ns
190
210
180
ns
5
CL=50pF
TdSTB (PDr)
200
180
160
ns
TdPD (INT)
540
490
430
ns
TdSTB (INT)
490
440
350
ns
~
Falling edge
TcC=TwCh+TwCI+TrC+TfC.
Increase TdRI (DO) by 10 ns for each 50 pF increase in load up to 200 pF max.
Increase TdIO (DOl) by IOns for each 50 pF, increase in load up to 200 pF max.
For Mode 2 : TwSTB>TsPD (STB).
Increase these values by 2 ns for each 10 pF increase in load up to 100 pF max.
TsCS (RI) may be reduced. However, the time subtracted from TsCS (RI) will be added to TdRI (DO).
2.5 TcC>(N-2) TdIEI (IEOf)+TdMI (IEO)+TsIEI (IO)+TTL buffer delay, if any.
Ml must be active for a minimum of two clock cycles to reset the PIa.
Z80B PIa numbers are preliminary and subject to change.
-------------SHARP-----.-........;...-239
-.,.-.-....
.............. -..
-
.•
.--
..........,...... ...
Z801Z80A/Z80B ParallellnputlOutput Controller'
.-
....
LH0081/LH0081A/LH0081 B
-.~....,~
AC Timing Chart
CLOCK
CE
B/A,C/O
RD,IORQ
OUT
Do-D,
{
.
IN
IORQ
Ml
lEI
lEO
READY
(ARDY or BRDY)
STROBE
(ASTB or B8TB)
Mode 0
Ao-A,
Mode 1
Mode 2
Mode 3
---"---~----SHARP---'-""""'~""""'------
240
Z80/Z80AlZ80B. Parallel Input/Output Controller
Programming
•
(1)
LH0081/LH0081A/LH0081B
(3) Interrupt control
The interrupt control words are as follows.
Interrupt vector read
An interrupting device needs giving an 8-bit interrupt vector to the CPU_ Using this vector, the
CPU forms an interrupt service routine address_
y
y
Indicates that the information
is interrupt control words
Effective in bit
control mode
Bit7 = 1:
(2)
Operation mode select
An operation mode is selected by writing data to
the 2-bit mode control register in the following
manner-
I~: I::(:ID~ IDrl :'1 ~I
'-y------'
'-----v------"
Mode Words
Indicates
Mode Words
Interrupt enable flag is set to enable an interrupt.
Bit7=O: Interrupt enable flag is reset to disable an interrupt.
Bit6-4: Defines interrupt conditions in the
bit mode. Ignored in other modes.
Bit3-0: Indicates interrupt control words.
If bit4 = I, the following control words are supposed to be written in the mask register.
X means they are not used
Mode
Byte output mode
Byte input mode
Bidirectional byte bus mode
Bit control mode
Ml
MO
0
0
1
1
0
1
0
1
In selecting the bit control mode, an input/output
direction should be set later.
Only the port data line with MB=O is monitored.
When the interrupt conditions are satisfied, an interrupt takes place.
Interrupt
enable
X
X
X
0
0
1
1
flag
'---...r----"
Not affected by
these -bits
Iio=l :Input ;
•
Interrupt control words
I10=O:Output
Timing
(1)
Output mode (Mode 0)
An output cycle is always started by the execution of an output instruction by the CPU_ The WR *
pulse from the CPU latches the data from the CPU
data bus into the selected port's output register.
The WR * pulse sets the Ready flag after a Lowgoing edge of CLK, indicating data is available.
Ready stays active until the positive edge of the
strobe line is received, indication that data was
taken by the peripheral. T~positive edge of the
strobe pulse generates an INT if the interrupt enable flipflop has been set and if this device has the
highest priority.
241
. Z80/Z80A/Z80B Parallel Input/Output Controller
. LHOb81/LH0081 AlLH0081 B
CLOCK
WR*
Port output
RDY
8TB
(2)
Input mode (Mode 1)
When STROBE goes Low, data is loaded into the
selected port iriput register. The next rising edge of
strobe activates INT, if Interrupt Enable is set and
this is the highest-priority requesting device. The
following falling edge of CLK resets Ready to an in·
active state, indicating that the input register is full
and cannot accept any mote data until the CPU
completes a rea~When a read is complete, the
positive edge of RD sets Ready at the next Lowgoing transition of CLK. At this time new data can
be loaded into the PIO.
CLOCK
Port input
RDY
RD"
(3)
Bidirectional mode (Mode 2)
This is a combination of Modes 0 and 1 using all
four handshake lines and the eight Port A I/O
lines. Port B must be set to the bit mode and its
inputs must be masked. The Port A handshake
lines are used for output control and the Port B
lines are used for input control. If interrupts occur,
242
Port A's vector will be used during port output and
Port B's will be used during port Input. Data is
allowed out onto the Port A bus only when- ASTB
·is Low: The rising edge of this strobe can be used
to latch the data into the peripheral.
Z80/Z80AlZ80B Parallel Input/Output Controller
LH0081/LH0081A/LH0081B
CLOCK
WR"
A RDY __________________-J
Port A data bus
------------C~~}t-~:1!~Q-+---
INT
B RDY
(4)
Bit mode (Mode 3)
The bit mode. does not utilize the handshake signals, and a normal port write or port read can be
executed at any time. When writing , the data is
latched into the output registers with the same timing as the output mode.
When reading the PIO, the data returned to the
CPU is composed of output register data from those
port data lines assigned as outputs and input regis-
ter data from those port data lines assigned as inputs. The input register contains data that was present immediately prior to the falling edge of RD. An
interrupt is generated if interrupts from the port
are enabled and the data on the port data lines
satisfy the logical equation defined by the 8-bit
mask and 2-bit mask control registers. However, if
Port A is programmed in bidirectional mode, Port B
does not issue an interrupt in bit mode and must
therefore be polled.
CLOCK
Port data bus
RD
L Data word 1 placed on bus
243
.-.-.--.........---..
Z80/Z80A/Z80B Parallel .Input/Output Controller
......,-....-
LH0081/LH0081 A/LH0081B
i
....,-----------~-
(5) Interrupt acknowledge timing.
During Ml time, peripheral Cflntroliers are inhibited from changing their interrupt enable status,
permitting the Interrupt Enable signal to ripp.le
through the daisy chain. The peripheral with lEI
High and lEO Low during INT ACK places a pre-
Last T state
programmed 8-bit interrupt vector on the data bus
at this time. lEO. is held Low until a Return From
Interrupt (RETI) instruction is executed by the·
CPU while lEI is High. The 2-byte RETI instruction is decoded internally by the PIO for this purpose.
Tw'
Tw'
T3
CLOCK
MI
lEO
lEI
(6)
Return from interrupt cycle
If a Z-:80 peripheral has no interrupt Pending
·and is not under service, then its IEO=1E1. If it has
an interrupt under service (i.e., it has already interrupted and received an interrupt acknowledge)
then its lEO is always Low, inhibiting lower priority devices from interrupting. If it has an interrupt
pending which has not yet been acknowledged, lEO
is Low unless an "ED" is decoded as the first byte
of a 2-byte opcode. In this case, lEO goes High until the next opcode byte is decoded, whereupon it
CLOCK
lEI
lEO
244
goes Low again. If the second byte of the opcode
was a "40", then the opcode was an RET! instruction.
After an "ED" opcode is decoded, only the
peripheral device which has interrupted and is currently under service has its lEI High and its lEO
Low. This device is the highest-priority device in the
daisy chain that has received an interrupt acknowledge. All other· peripherals have lEI = lEO. If the
next opcode byte decoded is "40". this peripheral device resets its "interrupt under service" condition.
LH0082/LH0082A1LH0082B
Z80/Z80A/Z,80B Counter Timer Circuit
LH0082/LH0082A/LH0082B
Z801Z80AlZ80B Counter Timer Circuit
•
Description
"
•
The Z80 product line is a complete set of microcomputer components, development systems and
support software. The 280 microcomputer component set includes all of the circuits necessary to
build high- performance microcomputer systems
with virtually no other logic and a minimum number of low cost standard memory elements.
The LH0082 280 eTe (Z80 eTe for short below) is a programmable, four channel device that
provides counting and timing functions for the Z80
epu. The Z80 epu configures the 280 eTC's four
independent channels to operate under various
modes and conditions as required.
The LH0082A 280A and LH0082B Z80B eTe
are the high speed version which can operate at the
4MHz and 6MHz system clock, respectively.
Pin Connections
o
ZC/TOo
7
Top View
•
Features
1. Four independent programmable 8-bit counterl16-bit timer channels
2. N-channel silicon gate process
3. Each channel may be selected to operate in
either a counter mode or timer mode
4. Programmable interrupts on counter or timer
states
5. When the down-counter reaches the zero count
the eTe reloads its time constant automatically
and continues it's channel operation
6. Readable down counter
7. Selectable 16 or 256 clock prescaler for each
timer channels
'8. Selectable positive or negative trigger may initiate timer or counter operation
9. Three channels have Ze/TO outputs capable of
driving Darlington transistors
10. Vectored daisy chain priority interrupt logic
included
11. Single +5V power supply and single phase
clock
12. All inputs and outputs fully TTL compatible
1,3. 28-pin dual-in-line package
·----.-..--~---SHARP
.......... - - - . - - - - 245
_-_.........
.._..._._----------_.....-....
LH0082/LH0082A1LH0082B
Z80/Z80AlZ80B Counter Timer Circuit
•
Bl.ock ,Diagra~
Zero Count/
Timeout Output
Clock/Trigger
Input
Internal
Control Logic
System
Data
Bus
Zero Count/
Ti meout Output
Clock/Trigger
Input
Zero Count/
Timeout Output
Clock/Trigger
Input
Clock/Trigger
Input
tIII
., > ><:>
t:>::
U)
-.,.,"
...
C,)
0
;:; G
uu z a
+
>
"
III
.=i
<1'
;jS
t:>::
!III
~
.,......"
'"
(n·2) TdlEI (lEaf) + TdMI (lEO) + TsIEI (10) + TTL buffer delay, if any.
[B] RESET must be active for a minimum of 3 clock cycles.
Notel: TcC=TwCh+TwCl+TrC+TfC.
Note 2 : Increase delay by 10 ns for each 50 pF increase in loading, 200 pF maximum for data lines, and 100 pF for control lines.
Note 3 : Increase delay by 2 ns for each 10 pF increase in loading, 100 pF maximum.
Note 4 : Timer mode.
Note 5 : Counter mode.
*: All timings are preliminary and subject to change.
--~--'-'--SHARP''''''---------
248
LH0082/LH0082A/LH0082B
Z80/Z80A/Z80B Counter Timer Circuit
•
AC Timing Chart
®
r
I'---CD---..
~ ®
CLOCK
r
... ;:q)
~ "~n~_r~
)l
CSo, CSI
-CE
J
IE-@~
IORQ
Read
](
1--(1)- ~ -®
'\.
~
L
\.
®~
-RO
r-®
®-~
¥
®- ~
'\.
®--iE---
00-07
i-@ f-J
fE--@~
X
CSo, CS,
write
X
k-ev-- ~
-CE
"\L.
¥
.....-4 ®
~'ll
IORQ
/
®--k--oo
)l
Do-Oj
-®
.....-..f- ®
}(
I-@--"'~
-{
Inter
acknowl edge
MI
~@ h
-IORQ
@f
,
I
I
00-07
-
INT
--®l~
I-©
,..".1.
CLK/TRGo-3
(Counter mode)
CLK/TRGo-3
(Timer mode)
ZCITOo-2
=
I
----'
~@
lb.$"
@~@---I
:i
\L
/
@
--1 re-@~
-@+/
f..:--@
lEO
lEI
~
®l =:-I
i-----@
---J
k-~
~@-r
@\.
~
.
~49
t:801Z80AIZ80B Counter Timer Circuit
'LH0082/LH0082A/LHOO82B
Programming
•
(1) Operation mocie select
To select a channel operating mode, write a channel control word having bit 0 changed to 1 in the
channel control register.
D7
Interrupt
enable
Ds
Ds
Prescaler
Mode value
D.
eLK/
D3
D2
Dl
Trigger Time
TRO
mode constant
Reset
edge
mode
selection
Do
1
D3 and Ds are used i~ timer mode only.
• Bit 7 = 0: Disables a channel interrupt.
• Bit 7 = 1: Enables a channel interrupt each
time the down-counter counts down to zero.
No interrupt is produced even with bit 7 as 1,
after the counter has counted down to zero
with bit 7 as O.
• Bit 6 = 0: Selects the timer mode, having the
prescaler output as the down-counter clock.
The timer's period comes in te. P. TC. Where
te represents system clock period, P has 16
or 256 (divisional scale by the prescaler), and
TC means an 8-bit programmable time constant (max. 256).
• Bit 6 = 1: Selects the counter mode, having the
external clock (CLK input) signal as the downcounter clock. The prescaler is not used.
• Bit 5 = 0: ,Used for the timer mode only. The
'prescaler divides the system clock into 16 sections.
.Bit 5 = 1: Used for the timer mode only. The
prescaler divides the system clock into 256
sections.
• Bit 4 = 0: Starts the timer operation at the trigger input falling edge in the timer mode. In the
counter mode, the down-counter comes on at
the clock input rising edge.
• Bit 4 = 1: Starts the timer operation at the trigger input rising edge in the timer mode. In the
counter mode, the down-counter comes on at
the clock input rising edge.
• Bit 3 = 0: Effective in the timer mode only.
With bit 1=1, the timer starts at the rising
edge of the machine cycle T2 which is next to
the write cycle of a time constant. With bit
1 =0, the timer starts at the rising edge of the
machine cycle Tl which is next to the write cycle of this control information .
• Bit 3 = 1: Effective in the timer mode only. The
timer starts by an external trigger input that
is given after the rising of the machine cycle
T2 next to the write cycle of a time constant.
250
•
•
•
•
The operation starts at the second clock rising
if the trigger input meets the set-up time, and
at the third clock rising if It does not. If an external trigger input is given before writing a
time c,onstant the' condition of bit 3 = 0 is
caused.
Bit 2 = 0: Indicates that there is no time constant written after the channel control word.
This bit cannot be 0 for the channel control
word to be immediately given when the channel is reset.
Bit 2 = 1: Indicates that there is a time constant
written after the channel control word. When
a time constant is written during a downcounter operation, the new constant is set into
the time constant register. But the counter
keeps on counting. Once the counter counts
zero, the new constant is available to use.
Bit 1 = 0: The channel acts as a down-counter.
Bit 1 = 1: Stops the operation as a down-counter. With bit 2 = 1, the operation restarts after
a time contant is written.
With bit 2 = 0, the channel does not act until a
hew control word is given.
(2)
Time constant programming
An 8-bit time constant is written into the time
constant register, following the channel control
word with bit 2 = 1. "00" (hexadecimal) indicates
the time constant 256.
Do
07
Os
Os
0,
TC7
(3)
I TCs I TCs
lTC,
TCa
TC2
TCI
TCo
Interrupt vector programming
If the Z-80 CTC has one or more interrupts enabled, it can supply interrupt vectors to the Z-80
CPU. To do so, the Z-80 CTC must be pre-programmed with the most-significant five bits of the
interrupt vector. Programming consists of writing
a vector word to the 110 port corresponding to the
Z-80 CTC Channel O. Note that Do of the v~ctor
word'is always zero, to distinguish the vector from
a channel control word. Dl arid D2 are not used in
programming the vector word. These bits are sup- ,
plied by the interrupt logic to identify the channel
requesting interrupt service with a unique interrupt vector. Channel 0 has the highest priority.
Z80/Z80AlZ80B Counter Timer Circuit
D6
V6
Dz
0
0
1
1
•
D,
0
1
0
1
D,
Ds
Vs
D3
Dz
V3
v,
D,
LH0082/LH0082A1LH0082B
and CSo selects the channel to be read. Ml must be
High to distinguish this cycle from an interrupt
acknowledge. No additional wait states are allowed.
(3) Interrupt acknowledge timing
Fig. 3 shows interrupt acknowledge timing. After an interrupt request~e Z-80 CPU sends an
interrupt acknowledge (Ml and IORQ). All channels are inhibited from changing their interrupt request status when Ml is ~tive-about two clock
cycles earlier than IORQ. RD is High to distinguish
this cycle from an instruction fetch.
The CTC interrupt logic determines the highest
priority channel requesting an interrupt. If the
CTC interrupt enable input. (lEI) is High, the high·
est proiority interrupting channel within the CTC
places its interrupt vector on the data bus when
IORQ goes Low. Two wait states (TWA) are automatically inserted at this time to allow the daisy
chain to stabilize. Additional wait states may be
added.
(4) Return from interrupt cycle
If a Z-80 peripheral has no interrupt pending
and is not under service, then its lEO = lEI. If it has
an interrupt under service (i.e.,it has already interrupted and received an interrupt acknowledge)
then its lEO is always Low, inhibiting lower priority devices from interrupting. If it has an interrupt
pending which has not yet been acknowledged, lEO
is Low unless an "ED" is decoded as the first byte
of a 2-byte opcode. In this case, lEO goes High until the next opcode byte is decoded, whereupon it
goes Low again. If the second byte of the opcode
Do
Vo
Channel
0
1
2
3
Timing
(1) Write cycle timing
Fig. 1 shows write cycle timing for loading control, time constant or vector words.
The CTC does not have a write signal input, so it
generates one internally when the read (RD) input
is High during T,. During T, IORQ and CE inputs
are Low. Ml must be High to distinguish a write
cycle from an interrupt acknowledge. A 2-bit binary code at inputs CSt and CSo selects the channel
to be addressed, and the word being written is
placed on the Z-80 data bus. The data word is
latched into the appropriate register with the rising edge of clock cycle T3.
(2) Read cycle timing
Fig. 2 shows read cycle timing. This cycle reads
the contents of a down-counter without disturbing
the count.
During clock cycle T2, the Z-80 CPU initiates a
read cycle by driving the following inputs Low: RD,
IORQ, and CEo A 2-bit binary code at inputs CSt
Tl
CLOCK
~
ru ~ ~rurL
T2
T3
X
Channel address
X
\
IORQ
I
RD
Ml
Input
I
I
I
Fig. 1 Write cycle timing
---~"'-'-----SHARP--'-----'-
251
LHOO82/LH0082A/LH0082B,
Z801Z80A/Z80B Counter Timer Cifc:uit
was a "4D," then the opcode was an RETI instruc~
tion.
After an' "ED" opcode is decoded, only the
peripheral device which 'has interrupted and is
currently under service has its IEI High and its
, lEO Low. This device is the highest-priority device
in the daisy chain that has received an interrupt
acknowledge. All other perjpherals have IEI' '" lEO. '
If the next opcode byte decoded is "4D", this
peripheral device resets its "interrupt under service" condition.
CLOCK
Channel address
Ml
0 0 -0 7
Output
Fig_ 2 Read cycle timing
Last T
state
CLOCK
---01
Tl
T2
Tw·
T.
n-l\....J ~ rL ~ ~ ~ ru
11
\
IORQ
- ---- ----
--- --- J
L ----
lEI
- ""\
,....-
II
It
Ml
lEO
Tg
Tw·
--
--~
-,
--- --- ~-U
r----
-h
Vector
I
00- 0 7
I
Fig. 3
Interrupt acknowledge timing
. - - . - - - - - - - - - - - $ H A R P . - - - - - . - . . - . .......... ~---
25,2
\
LH0082/LH0082A/LH0082B
Z80/Z80AlZ80B Counter Timer Circuit
Tl
T.
Tl
T2
T2
T3
Fig. 4
Return from interrupt cycle
T3
T.
Tl
CLOCK
Ml
RD
Do-D7
lEI
lEO
CD
Daisy chain prior to interrupt
During service
®
When Channel 2 requests interrupt and receives ackno~ledge.
During service
,®
When Channell requests interrupt and receives acknow ledge.
In this case, Channel 2 service is discontinued temporarily.
®
When Channell service is completed and RETI instruction is executed.
In this case, Channel 2 service is restarted.
®
When Channel 2 service is ~ompleted and RETI instruction is executed.
Fig. 5
Daisy-chain interrupt service
253
LH0082/LH0082A/LH0082B
Z80/Z80A/Z80B Counter Timer Circuit
(5)
(6) Counter operation/timer operation
Daisy-chain interrupt service
In the counter mode, the CLK/TRG pulse input
decrements the down-counter. The trigger is asynchronous, but the count is synchronized with CLK.
For the decrement to occur on the next rising edge
of CLK, the trigger edge must precede CLK bya
minimum lead time. In the timer mode, a CLK/TRG
pulse input starts the timer on the second succeeding rising edge of CLK. The trigger pulse is asynchronous, and it must have a minimun width. A
minimun lead time (210 ns) is required between the
active edge of the CLK/TRG and the next rising
edge of CLK to enable the prescaler on the following clock edge.
Fig. 5 shows a typical nested interrupt order
with the CTC. Channel 2 first requests an inter·
rupt to be serviced. If the higher-priority Channel
1 requests an interrupt while Channel 2 is in service, the Channel 2 service is interrupted and
Channell is serviced instead. Now the Channell
service routine has been completely executed, an
RETI instruction can be given to indicate that
Channel 1 has been serviced. At this moment,
Channel 2 will be in service again.
CLOCK
CLK
~
L
/
\
Counter mode
Down counter
I
ZC/TO
/
\
Zero count
\
CLOCK
TRG
/
Prescaler
Fig. 6
254
\
I
Start operatig
Counter operation/timer operation
Timer mode
Z80/Z80A Direct Memory Access
LH0083/LH0083A
LH0083/LH0083A
•
Description
•
ZSOIZSOA
Direct Memory Access
Pin Connections
The Z80 product line is a complete set of microcomputer components, development systems and
support software. The Z80 microcomputer component set includes all o'{ the circuits necessary to
build high-performance microcomputer systems
with virtually no other logic and a minimum number of low cost standard memory elements.
The LH0083 Z80 DMA (Z80 DMA for short below) is a powerful and versatile device for controlling and processing of data transfers. Its basic
function of managing CPU-independent transfers
between two ports is augmented by an array of features that optimize transfer speed and control with
little or no external logic in systems using an 8-or
16-bit data bus and a 16"'bit address bus.
Transfers can be done between any two ports
(source and destination), including memory-to-I10,
memory-to-memory, and I10-to-I10. Dual port
addresses are automatically generated for each
transaction and may be either fixed or incrementing/
decrementing. In addition, bitmaskable byte searches
can be performed either concurrently with transfers
or as an operation in itself.
The LH0083A Z80A DMA is a high speed version which can operate at the 4MHz system clock.
BAO 13
BAI 14
BUSRQ 15
CE/WAIT
Top View
•
Features
1. Transfers, searches and search/transfers in
byte-at-a-time, burst or continuous modes
2. Cycle length and edge timing can be programmed
3. Dual port addresses generated for memoryto-JlO, memory-to-memory, or I10-to-I10 operations Adderess may be fixed or automatically incremented/decremented
4. Next-operation loading without disturbing current operations via buffered starting-address
5.
6.
7.
8.
9.
10.
registers and an entire previous seQuence can
be repeated, automatically
Extensive programmability of functions CPU
can read complete channel status
Vectored daisy chain priority interrupt logic
Single + 5V power supply and single phase
clock
TTL-compatible inputs and outputs
40-pin dual-in-line package
N-channel silicon-gate process
.-.-----,---SHARP----------
255
l
..........,.....................................................................Z-80/Z80A Direct Memory Access
LH0083/LH0083A
,
•
Block Diagram
•...:0:.::;
;; ;; u"
0
l/')
+
u
u
:>
0
-'"
E
'"
>.
Ul
7
Bus Acknowlege In
Bus Acknowlege Out
Interrupt 'Request
Interrupt Enable In
Interrupt Enable Out
Interrupt
'and Bus
Priority
Logic
-Plllse
, Logic
Byte
COllnter
Port A
Address
System
Address
Bus
Syste'm Data Bus
Machine ,Cycle 1
I/O ReqQest
Memory Request
Read
256
Bus
Control
Logic
Control
and
Status
Registers
Byte
Match
Logic
Port B
Address
,
Z80/Z80A Direct Memory Access
•
LH0083/LH0083A
Pin Description
Ao-A'5
Pin
Meaning
Address bus
Do -D 7
Data bus
--
BAI
--
BAO
BUSRQ
110
3-state 0
Bidirectional
3-state
Bus acknowledge in
I
Bus acknowledge out
0
Bus request
Open drain, 0
CE/WAIT
Chip enable
I
CLOCK
System clock
I
Machine cycle one
I
---
-
Ml
-IORQ
Input/output request
Bidirectional
3-state
Function
System address bus.
System data bus.
Active "low". Used to form a bus priority- interrupt
daisy-chain.
Active "low". U sed to form a bus priority- interrupt
daisy-chain.
Active "low". Active when controlling the bus.
Active "low". Acts as CE when the CPU accesses the
DAM, and as WAIT when the DAM is the bus master.
Standard 280 system clock used for internal synchro·
nization signals.
Active "low". Indicates that CPU is acknowledging an in·
-terrupt, when both Ml and IORQ are active.
Active "low". Transmits and receives data from the CPU
as an input line. Acts as 10RQ for another device as an
output line. Indicates that the CPU is acknowledging an
-interrupt, when both IORQ and Ml are active.
Active "low". Requests a transfer from or to memory
with the DMA as a bus master.
Active "high". Used to form a priority-interrupt
,
daisy-chain.
Active "low". Used to form a priority-interrupt
daisy-chain.
Active "low". Active when requesting an interrupt. Can
also generate pulses.
Active "low". Reads data from the CPU as an input line.
Acts as RD for another device as an output line.
Active "low". Writes data from the CPU as an input line.
Acts as WR for another device as an output line.
With the DMA as a bus master, starts DMA operation
when active, and stops it when not active.
-
-MREQ
3-state 0
lEI
Interrupt enable in
I
lEO
Interrupt enable out
0
----
INT/PULSE
-
RD
-
-
Memory request
Interrupt request/pulse
Read
WR
Write
RDY
Ready
Open drain, 0
Bidirectional
3-state
Bidirectional
3-state
I
----------SHARP-.--..-.-----
257
Z80/Z80A ,Direct Memory Access
•
LH 0083/LH0083A
Absolute Maximum Ratings
Parameter
Input voltage
Output voltage
Operating temperature
Storage temperature
•
Symbol
VIN
VOUT
T oDe
Tstg
Ratings
-0.3-+7
-0.3-+7
0-+70
-65-+150
Unit
V
V
·C
·C
(Vce=5V±5%, Ta=0-+70·C)
DC Characteristics
Clock
Clock
Input
Input
Parameter
input low voltage
input high voltage
low voltage
high voltage
Symbol
Output low voltage
VOL
Output high voltage
Vall
Current
consumption
I Z80 DMA
I Z80A DMA
Input leakage current
3 -state output leakage current
3-state output leakage current
Data bus leakage current in
input mode
•
Conditions
VILe
VIlle
VIL
VIII
Icc
I ILl I
I lLOII I
I lLOL I
I ILD I
IOL =3.2mA for BUSREQ
IOL =2.0 mA-for all others
IoH =-250pA
t,=400ns
tc= 250ns
MIN.
-0.3
Vee- 0 .6
-0.3
2.0
O~VIN~Vee
VouT=2.4V
VOllT =O.4V
-
MAX.
0.45
5.5
0.8
5.5
Unit
V
V
V
V
0.4
V
150
200
10
10
10
V
mA
mA
pA
pA
pA
10
pA
2.4
-
OV~VIN~VCC
(f=IMHz, Ta=25·C)
Capacitance
Parameter
Clock capacitance
Input capacitance
Output capacitance
TYP.
Symbol
!
CCLOCK
CIN
COUT
Conditions
;Unmeasured pins returned
to ground
MIN.
TYP.
MAX.
35
5
10
Unit
pF
pF
pF
-~------SHARP-------'-
258
Z80/Z80A Direct Memory Access
•
LH0083/LH0083A
AC Characteristics
(1) Acting as CPU peripheral (inactive state)
No.
1
2
3
4
5
6
7
8
9
10
II
12
13
14
15
16
17
18
19
20
21
22
Parameter
Clock cycle time
Clock width (high)
Clock width (low)
Clock rise time
Clock fall time
Hold time for any specified setup time
IORQ, WR, CE ! to clock t setup time
RD ! to data output delay
Data in to clock t setup (WR or Ml)
IORQ ! to data out delay (INT A cycle)
RD t to data float delay (output buffer disable)
lEI! to IORQ ! setup (INT A cycle)
lEI t to lEO t delay
lEI! to lEO ! delay
Ml ! to lEO ! delay
(interrupt just prior to Ml ! )
Ml ! to clock t setup
MIt to clock ! setup
RD ! to clock t setup (Ml cycle)
Interrupt cause to INT ! delay
(INT generated only when DMA is inactive)
BAI t to BAO t delay
BAI ~ to BAO ~ delay
RDY active to clock t setup time
Symbol
TcC
TwCh
TwCl
TrC
TfC
Th
TsC(Cr)
TdDO(RDf)
TsWM(Cr)
TdCf(DO)
TdRD(D2)
TsIEI(IORQ)
TdIEOr(lElr)
T dIEOf(IElf)
280 DMA
MIN.
MAX.
400
4000
170
2000
170
2000
30
30
0
280
500
50
340
160
140
210
190
TdMl(IEO)
TsMlf(Cr)
TsMlr(Cf)
TsRD(Cr)
280A DMA
MIN.
MAX.
250
4000
110
2000
2000
110
30
30
0
145
380
50
160
110
140
160
130
190
300
210
20
240
90
-10
115
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Tdl(INT)
500
500
ns
TdBAlr(BAOr)
TdBAIf(BAOf)
TsRDY(Cr)
200
200
150
150
ns
ns
ns
150
100
Note : t Rising edge, ! Falling edge.
Note 1: Negative minimum setup values mean that the first-mentioned event can come after the second-mentioned event.
--~'--""-'--SHARP'--------
259
.......- ....... ............,..............-.. ........
Z80/Z80A~ Direct Memory Access
---.--.
~
CLK
CE. IORQ. WR.
RD
MI
lEI
lEO
INT
Interrupt state
I
_________F@).JI
-----+I----~
.
:: ~1~---(-@~)----;d~---RDY
~-@
~
_
Inactive
Acting as CPU peripheral (Inactive state)
260 .
......
,... LH0083/LH0083A"
..-.-..
~
Z80/Z80A Direct Memory Access.
LH0083/LH0083A
(2)
Acting as bus controller (active state)
No.
Parameter
Symbol
1
2
3
4
5
6
7
8
Clock cycle time
Clock width (high) .
Clock width (low)
Clock rise time
Clock fall time
Address output delay
Clock t to address float delay
Address to MREQ ~ setup (memory cycle)
Address stable to IORQ, RD, WR ~ setup
(110 cycle)
RD, WR t to addr. stable delay
RD, WR t to addr. float delay
Clock ~ to data out delay
Clock t to data float delay (write cycle)
Data in to clock t setup
.(read cycle when rising edge ·ends read)
Data in to clock ~ setup
(read cycle when falling edge ends read)
Data out to WR ! setup (memory clcle)
Data out to WR ~ setup (110 cycle)
WR t to data out hold time
Hold time for any specified setup time
Clock! to MREQ ! delay
Clock t to MREQ t delay
Clock ~ to MREQ t delay
MREQ low pulse width
MREQ high pulse width
Clock t to IORQ ! delay
Clock t to IORQ t delay
Clock! to IORQ t delay
Clock t to RD ~ delay
Clock! to RD ~ delay
Clock t to RD t delay
Clock ~ to RD t delay
Clock t to WR ~ delay
Clock ~ to WR ~ delay
Clock t to WR t delay
Clock ~ to WR t delay
WR Low pulse width
WAIT to clock ~ setup
Clock t to BUSREQ delay
Clock t to IORQ, MREQ, RD, WR float delay
TcC
TwCh
TwCl
TrC
TfC
TdA
TdC(AZ)
TsA(MREQ)
9
*10
*11
12
*13
14
15
*16
17
*18
19
20
21
22
23
*24
25
26
*27
28
29
30
31
32
33
34
35
36
37
38
39
Note
Note
, Note
Note
Note
:
1:
2:
3:
4:
(Vco=5V±5%, Ta=0-+70"C)
Z80 DMA
MIN.
MAX.
400
180
2000
180
2000
30
30
145
110
(21+(5)-75
Z80A DMA
MAX.
MIN.
250
110
2000
110
2000
30
30
110
90
(2)+(5)-75
Unit
ns
ns
ns
ns
ns
ns
ns
ns
TsA(IRW)
(1)-80
(1)-70
ns
TdRW(A)
TdRW(AZ)
TdCf(DO)
TdCr(Dz)
(3)+(4)-40
(3)+(4)-60
(3)+(41-50
(3)+(4)-45
ns
ns
ns
ns
230
90
150
90
TsDI(Cf)
50
35
ns
TsDO(WfM)
60
50
ns
4 ==
;;
TsDO(WPI)
TsDO(WPI)
TdWr(DO)
Th
TdCf(Mf)
TdCf(Mr)
TdCf(Mr)
TwMI
TwMh
TdCr(If)
TdCr(lr)
TdCr(Ir)
TdCr(Rf)
TdCr(Rf)
TdCr(Rr)
TdCr(Rr)
TdCr(Wf)
TdCf(Wf)
TdCr(Wr)
TdCf(Wr)
TwWl
TsWA(Cf)
TdCr(B)
TdCr(lz)
(1)-210
100
(31+(4)-80
0
(1)-170
100
(3)+(4)-70
0
100
100
100
(1)-40
(2)+(51-30
85
85
85
(1)-30
(21+(3)-20
90
100
110
100
130
100
110
80
90
100
100
(1)-40
70
75
85
85
85
95
'85
85
65
80
80
80
(1)-30
70
150
100
100
80
ns
us
us
fis
ns
us
ns
ns
ns
us
ns
us
ns
ns
ns
us
ns
ns
us
us
ns
us
us
ns
t Rising edge. ~ Falling edge
Numbers in parentheses are other parameter numbers in this table; their values should be substituted in equations.
All equations imply DMA default (standard) timing.
Data must be enabled onto data bus when RD is active.
Asterisk (*) before parameter number means the parameter is not illustrated in the AC Timing Diagrams.
26f
=
Lti0083/ LH0083A
Z8Q/Z80A Direct Memory Access
..-,,-,,-,,,,,,,,,,,
..~---;.,.~""",,,--,,,,,,,,,,,,,,-,-,-,,,,,,
'CLK;
DO-D7{ Input
Output
--~~--#-~---4+-----+---~
RD
WR
BUSR
Acting as bus controller (active state)
•
Prpgramming
The Z-80 DMA has two programmable fundamental states_
• an enabled state, in which it can gain control
of the system buses and direct the transfer
of data between ports, and
• a disabled state, in which it can initiate neither
bus requests nor data'transfers. When the
DMA is powered up or reset by any means,
it is automatically placed into the disabled
state.
(1)
Reading
The Read Registers (RRO-RR6) are read by the
CPU by addressing the DMA as an 110 port using
an Input instruction. The readable bytes contain
DMA status, byte-counter values, and port addresses since the last DMA reset. The registers are always read in a fixed sequence beginning with RRO
and. ending with RR6.
•
Read Register 0
T~O
O~I
t L: =D.MAS;;~:: ::~RED
D7 D6 D5 D. D3 D2 Dl Do
I Xlix
I
XI
I
L O = READY ACTIVE
.
O=INTERRUPT PENDING
O=MATCH FOUND
.
O=END OF BLOCK
~--------------INTERRUPT PENDING
•
Read Register 1
~I~I~I~~I~I~I~~I~~' BYTE COUNTER
(LOW BYTE)
•
Read Register 2
r--"TI__I'--"-I-TI'--I'--"-I--'--'1 'BYTE
CO UNT E R
(HIGH BYTE)
•
Read Register 3
,....-...--r--r-,---rr-r-...,.."
PORT A AD DRES S
L-..,I--'-.....l..~~~J..-~-' COUNTER (LOW BYTE)
•
Read Register 4
1 I 1
1
I-.l-...I....-'---'---I__"--...L.......I
PORT A ADDRESS
COUNTER (HIG H B YT E)
.-,------------.--..-SHARP-----.-.,.-.-.-.-.--
262
Z80/Z80A Direct Memory Access
•
Read Register 5
•
r-r--r---r-~"-""T'"""--' PO RT B AD D RE S S
COUNTER (LOW BYTE)
I
•
LH0083/LH0083A
Wr.ite Register 2
D, D6 Ds D. D3 D2 D, Do'
I 0 I I I I I 0 I 0 I 0 [ BASE REGISTER
BYTE
O=PORT B IS MEMORY
l=PORT B IS I/O
o =PORT B ADDRESS DECREMENTS
1 =PORT B ADDRESS INCREMENTS
o
=PORT B ADDRESS VARIABLE
1
=PORT B ADDRESS FIXED
1
I
Read Register 6
I PORT B ADDRESS
L..-...L.........L-~......L--J_J..-............. COUNTER (HIGH BY1IE)
(2) Writing
Control or command bytes are written into one
or more of the Write Register groups (WRO-WR6)
by first writing to the base register byte in that
group. All groups have base registers and most
groups have additional associated registers. The
associated registers in a group are sequentially
accessed by first writing a byte to the base register
containing register-group identification and pointer bits (I, s) to one or more of that base register's
associated registers.
•
Write Register 0
~-r-'-r--r--r--'-'---.-..,
bo
J=CYCLE LENGTH=4
l=CYCLE LENGTH =3
1 O=CYCLE LENGTH=2
1 1 =DO NOT USE
O=IORQ ENDS 112 CYCLE EARLY
0= MREQ ENDS 1/2 CYCLE EARLY
0= RD ENDS 112 CYCLE EARLY
0= WR ENDS 1/2 CYCLE EARLY
•
Write Register 3
D, D6 Dj D. D3 D2 D, Do BASE
I I I I I 0 I 0 [ REGISTER
D, D6 Ds D. D3 D2 D, Do
[ 0
I I I I [ BASE REGISTER BYTE
DO NOT USE
b0 61= TRANSFER
I 1 I
Jl
I
I
I
I
I
•
[ PORT A STARTING ADDRESS
I
I
I
I
I
1 J PORT A STARTING ADDRESS
I
I
I
I
I
J BLOCK LENGTH
(LOW BYTE)
[ BLOCK LENGTH
(HIGH BYTE)
Write Register 1
D, D6 Ds D. D3 D2 D, Do
I I I
1 I 0 I 0 I BASE REGISTER BYTE
I0 I
I
b=PORT
l=PORT
o =PORT A
1 =PORT A
= PORT A
=PORT A
o
1
I
I
I
I
A IS MEMORY
A IS I/O
ADDRESS DECREMENTS
ADDRESS INCREMENTS
ADDRESS VARIABLE
ADDRESS FIXED
[ J
b
o
1
1
BYTE
ON
MATCH
[
I
I
I
I
I
I
I
I MASK BYTE
(0= COMPARE)
[
I
I
I
I
I
I
I
[MATCH
BYTE
(LOW BYTE)
(HIGH BYTE)
I
1
l=STOP
DMA ENABLE =1
INTERRUPT ENABLE=l
1 0= SEARCH
1 1= SEARCH/TRANSFER
O=PORT B --->PORT A
l=PORT A--->PORT B
I
PORT B VARIABLE
L..-,-..J..,.....L---'---L..,..-J-.-.L..,-..J..,...J TIMING BYTE
~?~1t i'f-lJABLE
J=CYCLE LENGTH=4
l=CLCLE LENGTH =3
O=CYCLE LENGTH =2
l=DO NOT USE
O=IORQ ENDS 112 CYCLE EARLY
O=MREQ ENDS 112 CYCI;E EARLY
O=RD ENDS 112 CYCLE EARLY
O=WR ENDS 112 CYCLE EARLY
•
Write Register 4
D, D6 Ds D. D3 D2 D, Do
0 1 I BASE
1 1
REGISTER
BYTE
BY TE=
ll1 J
b b
1
0
1
CONTINU OUS= 0
BU RST= 1
DO NOT PROG RAM= 1
L
[
[
I
I
I
I
I
~
I
PORT B STARTING
ADDRESS (LOW BYTE)'
I PORT B STARTING
ADDRESS (fiG" BYTE)
0
j
j
INTERRUPT CONTROL BYTE
1=INTERRUPT ON
INTERRU PT
MATCH
ON R DY=l
l=INT ERRUPT AT
STATUS AF FECTS
EN D OF BLOCK
VE CTOR=l
l=PULSE GENERATED
[
I I I I I I r [ PULSE CONTROL
BYTE
INTERRUPT
[
[
I I
VECTOR'
I
I
VECTOR IS AUTOMATICALLY { 0 o = INTERRUPT ON RDY
ON MATCH
MODIFIED AS SHOWN
9 1o == INTERRUPT
INTERRUPT ON END
ONLY IF" STATUS
1
OF BLOCK
AFFECTS VECTOR" BIT IS SET i
1 = INTERRUPT ON MATCH
AND END OF BLOCK
!
263
.---....--AIIIIIIiII'-............
. Z80/Z80A Direc.t. Memory Ac.cess
. . ....-
LH0083/L:H0083A
-~-~-
•
~
Write -Register 5
....:...&..---I.-r-....,..~...,L...;.......~~
BASE REGIS TER
BYTE
O=REApy ACTIVE LOW /
'. 1 == READY ACTIVE HIGH
O'=CE ONLY
l=CE!WAIT MULTIPLEXED
STOP RESTART ON END
O=STOP ON END OF BLOCK
l=AUTO REPEAT ON END ,QF BLOCK
•
Write Register 6
D7 D6 Ds D. D3 D2 DJ Do
I1I I I I I I1I1
C3
I
I
I
I
I
1
0
0
0
0
0
0
0
1
I BASE
REGISTER BYTE
INTERRUPT LINE RESET, INTERRUPT REQUEST AND BUS REQUEST DISABLE,
INTERNAL READY STATE CLEAR, CE MULTIPLEX DISABLE, AUTOMATIC REPEAT
STOP
PORT A TIMING TOZ80 STANDARD TIMING
C7
1
CB
10010
PORT B TIMING TO ZIlO STANDARD TIMING
CF
1
0
BOTH PORTS START ADDRESS LOAD, BYTE CaNTER CLEAR
0
1
1
D3
1
0
1
0
0
ADDRESS CONTINU):': FROM CURRENT VALUE, BYTE COUNTER CLEAR
AB
o
1
0
1
0
INTERRUPT ENABLE
AF
o
1
011
INTERRUPT DISABLE
A3
o
o
o
o
o
o
1
0
0
0
0
0
0
1
INTERRUPT CIRCUIT RESET AND DISABLE (SAME AS RETI) , INTERNAL READY
STATE CLEAR
DMA ENABLE} EFFECTIVE FOR ALL SECTIONS BUT INTERRUPT.
87
83
A7
BF
B3
88
B7
BB
o
o
o
0
0
0
0
DMA DISABLE NOT ALL FUNCTIONS RESETTABLE, HOWEVER
1
0
0
1
READ SEQUENCE START FOR 1ST REGISTER DESIGNATED BY READ MASTER
REGISTER
.
STATUS REGISTER READ SETUP. FROM STATUS REGISTER FOR NEXT READ
1·1
1
1
1
1
0
0
0
0
1
0
1
101
ENABLE AFTER RETI. BUS REQUEST ONLY AFTER RETI EXECUTION
1
1
READ MASK FOLLOWS
I 0 I
1
I
INTERNAL READY STATE TO BE FORCEDLY CLEAR OF "RDY" PIN (USED. FOR
DMA BETWEEN MEMORIES NEEDING NO RDY SIGNAL. NOT OPERATIVE IN "BYTE
.MODE")
REINITIALIZE. END-OF-BLOCK BIT CLEAR
0
I
I
II
I
! I READ MASK (I=ENABLE)
STATUS BYTE
BYTE COUNTER
1 1'-------BYTE
COUNTER
fL'_ _ _
L _L_-_-_-_-_-=--=--=--=--=--=PORT
L_ _ _ _ _ _ _ _ PORT
PORT
'-----------PORT
264
A
A
B
B
(LOW 'BYTE)
(HIGH BYTE)
ADDRESS 1LOW BYTE)
ADDRESS HIGH BYTE)
ADDRESS LOW BYTE)
ADDRESS HIGH BYTE)
Z80/Z80A Direct Memory Access
•
Timing
(1) Inactive state timing (DMA as CPU
.
Peripheral)
In its disabled or inactive state, the DMA is
addressed by the CPU as an I/O peripheral for
write and read (control and status) operations.
Write timing is illustrated in Fig. 1.
Reading of the DMA's status byte, byte counter
or port address counters is illustrated in Fig. 2.
(2) Active state timing (DMA as BUS
. LH0083/LH0083A
wait cycle between T2 and T3. If the CE/WAIT line
is programmed to act as aWAIT line during the
DMA's active state, it is sampled on the falling edge
of Tz for memory tr~nsactions a~d the falling edge
of Tw for I/O transactions. If CE/W AIT is Low
during this time another T -cycle is added, during
which the CE/W AIT line will again be sampled.
The duration of transactions can thus be indefinitely extended.
CLOCK~
Controller)
(i)
Default read and write cycles
By default, and after reset, the DMA's timing of
read and write operations is exactly the same as
the Z-80 CPU's timing of read and write cycles for
men:lOry and 110 peripherals, with one exception:
during a read cycle, data is latched on the falling
edge of T3 and held on the data bus across the
boundary between read and write cycles, through
th'e end of the following write cycle.
Fig. 3 illustrates the timing for memory to-I/O
port transfers and Fig. 4 illustrates IIO-to-memory
transfers. Memory-to-memory and I/O-to-I/O
transfer timings are simply permutations of these
diagrams.
The default timing uses three T -cycles for memory. transactions and four T -cycles for 110 transactions, which include one automatically inserted
W:Q
Do-D7
-hLd::::::
-+-++---+-.. .cb
Fig. 1
CPU-DMA write cycle timing
Fig. 2
CPU-DMA Iread cycle timing
.---'---.---SHARP....--.--.--.-.~--
265
LH00J33!LH0083A
Z60!Z80A Dire.ct Memory Access
.................
....,.....__....,_ _ _....,.-r.__...
__
-.:~....,.-
I+-- Memory
TJ
.' CLOCK
-'--
Read
n-~
I/O Write
' Tw
. . . ~ ~r-Lr-~ L
T2
X
Tz
Tl
T3
,....
T3
L
X
MREQ
\
I
RD
\
J
Read {
IORQ
: Write
{
r
~
1\
_
WR
rr--
\
Do-D7
l)-
\
-- ---- ·7 r- ---- ---- --- 7 ..,- ---- r-... ---1---- -'
-- ---""1---- --\
\
oJ
Fig. 3 Transfer from memory to 1/0 device
Memory Write
I/O Read
Tl
CLOCK
Tw
T3
Tl
Tz
--;0
T3
- rLlLr- ~n- ~r--~~
- X
X
I'X
-
_ {IORQ
,Read .-
RD
T2
'
\
I
\
I
~
l}\
MREQ
Write { _
WR
CE/WAIT
-- ----
----
-- --- ---_. J \
----
\
I
I\..W
------- --T \:
---
Fig. 4 Transfer from 1/0 device to memory
~_.
Z80/Z80A Direct Memory Access
(ii) Variable cycle and edge timing
The
Z-80 DMA's default operation-cycle length for the
source (read) port and destination (write) port can
be independently programmed. This variable-cycle
feature allows read or write cycles consisting of
two, three or four T-cycles (more if Wait cycles
are inserted), thereby increasing or decreasing the
speed of all signals generated by the DMA. ~ddi
tion, the trailing edges of the IORQ, MREQ, RD and
WR signals can be independently terminated
one-half cycle early. Fig. 5 illustrates this.
In the variable-cycle mode. unlike default timing,
IORQ comes active one-half cycle before MREQ,
RD and WR. CE/W AIT can be used to extend only
the 3 or 4 T-cycle variable memory cycles and
only the 4-cycle variable 110 cycle. The CE/W AIT
line is sampled at the falling edge of T2 for 3-or.
4-cycle memory cycles, and at the falling edge of
T3 for 4-cycle 110 cycles.
During transfers, data is latched~ the clock
edge causing the rising edge of RD and held
through the end of the write cycle.
(iii) Bus requests
Fig. 6 illustrates the bus
request and acceptance timing. The RDY line,
which may be programmed active High or Low, is
sampled on every rising edge of CLK.
If it is found to be active, and if the bus is not in
use by any other device, the following rising edge
of CLK drives BUSREQ low. After receiving BUSREQ the CPU acknowledges on the BAI input
either directly or through a multiple-DMA daisy
chain. When a Low is detected on BAI for two consecutive rising edges of CLK, the DMA will begin
transferring data on the next rising edge of CLK.
(iv) Bus release byte-at-a-time
In Byte at
a Time mode. BUSREQ is brought High on the rising edge of CLK prior to the end of each read cycle
(search-only) or write cycle (transfer and transferl
search) as illustrated in Fig. 7. This is done regardless of the state of RDY.
The next bus request fo!:.l!!e next byte will come
after both BUSREQ and BAI have returned High.
(v) Bus release at end of block
In Burst
and Continuous modes, an end of block causes
BUSREQ to go High usually on the same rising
edge of CLK in which the DMA completes the
transfer of the data block (Fig. 8). The last byte in
the block is transferred even if RDY goes inactive
before completion of the last byte transfer.
(vi) Bus release on not ready
In Burst
mode, when RDY goes inactive it causes BUSREQ
to go High on the next rising edge of CLK after the
completion of its current byte operation (Fig. 9).
The action on BUSREQ is thus somewhat delayed
LH0083/LH0083A
from action on the RDY line. The DMA always
completes its current byte operation in an orderly
fashion before releasing the bus.
By contrast, BUSREQ is not released in Continuous mode when RDY goes inactive.
Instead, the DMA idles after completing the current
byte operation, awaiting an active RDY ~ain.
(vii) Bus release on match
If the DMA is
programmed to stop on match in Burst or Continuous modes, a match causes BUSREQ to go inactive on the next DMA operation, i.e., at the end of
the next read in a search or at the end of the following write in a transfer (Fig. 10). Due to the
pipelining scheme, matches are determined while
the next DMA read or write is being performed.
The RDY line can go inactive after the matching
operation begins without affecting this bus-release
timing.
(Viii) Interrupts
Timings for interrupt acknowledge and return from interrupt are the same
as timings for these in other Z-80 peripherals. (Refer to the Z80 PIO.)
Interrupt on RDY (interrupt before requesting
bus) does not directly affect the BUSREQ line. Instead, the interrupt service routine must handle
this by issuing the following commands.
a. Enable after return from interrupt (RETI)
(Command code 87H)
b. Enable DMA (Command code 87H)
c. An RETI instruction
-.-.-----.-.--SHARP..-......-------
267
Z80/Z80A Direct Memory Access
LH0083lLH0083A
-...r.-_......_ ..- I r - . - . - . - . - . -_ _..._-.:,..-.-.-
CLOCK
Ao-AIS
MREQ
- -
"""\r--.J1'- __ _
-...J,----I-'
~r
T-,--r-T
,, - - I
I
I
RD, WR
,
,
.L_..I_
L._.L_
I
'
~YCLE ~ CYCLE
• 2 CYClE 3
EARLY END EARLY END
'
EARLY END
Fig. 5 Variable cycle and edge timing
CLOCK
-INACTIVE
-B-U-SR-Q-
==~::_j-rt-----1'"'". --t I---+_+-_-+__+-__
I
BAl
__ J I
DMA
INACTIVE
Fig. 6
CLOCK
Bus request and acknowledgement
~~.
_ _ _ _ _ _ _ _ _ _ __
BUSRQ-HI
I
I
I
BAI
DMA
ACTIVE
Fig. 7
268
DMA
ACTIVE
I
i I"'D'M.A
--+-
INACTIVE
Bus clear (byte mode)
Z80lZ80A Direct Memory Access
CLOCK
LH0083lLH0083A
---ILnY
ACTIVE
RDY INACTIVE
L
LAST BYTE
OPERATION--i.......-DMA INACTIVE
BLOCK
r - IN
Fig. 8
End of block bus clear (burst, continuous mode)
ACTIVE
RDY INACTIVE
~.~_ _ _-I-_ _ _ _ _ __
BUSRQ
'- CURRENT BYTE
iOPERATION
Fig. 9
RDY
DMA INACTIVE
No READY bus clear (burst mode)
INACTIVE
BUSRQ --~I-.----i~'~-~I~B~Y~T~E~n~+~l~R~E~A~D~~
BYTE n - + I N MATCH FOUN
READ IN
ON BYTE n
Fig. 10
DMA INACTIVE
Mating bus clear (burst, continuous mode)
------~-----SHARP .. . . . - . - . - . - - - - - -
269
................ -........... -........-..... - . - . . -.........................
l80/l80A/l80B Serial Input/Output Controller
LH0084/84A!84B/85/85A/85B/86/86A/86B
LH0084/LH0084A/LH0084B .
LH0085/ LH0085A/LH0085B Z80/Z80A--:---
Read cycle timing
T2
Tw
T3
T\
CLOCK
CE
Channel address
IORQ
RD
Ml
DAtA
X
Input
Fig. 3 Write cycle timing
278
X
LH011 O/LH011 OA
Floppy Disk Controller
LH0 11 0/ LH0 110A Floppy Disk Controller
•
Description
•
Pin Connections
The LHOllO is a micro-program controlled
Floppy Disk Controller (FDC) designed as one of
the Z80 peripherals.
The LHOllO is fabricated with N-channel sili·
con-gate process technology, and packaged in a
40-pin dual-in-line package.
The LHOllO provides a TTL compatible inter·
face and requires a single + 5V power supply.
06
07
INT
MUXS
ROY
lOX
WP/TRo
VFO
•
Features
1. Can be connected directly to the Z80 CPU bus
• Daisy chain interrupt signal
• Interrupt vector output
• Recognition of the Z80 CPU RETI instruc·
tion
2. DMA or program controlled data transfers
3. Separate clocks for system control and FDD
control.
4. Can be connected to other microprocessors
5. IBM format compatible
• Single-sided, Dual-sided (FM)
Dual-sided double-density (MFM)
• FM: 128,256,512 bytes/sector
MFM: 256, 512,1024 bytes/sector
• 8, 15, 26 sectors/track
6. Can control minifloppies (change the 2MHz
FCLK to a 1MHz clock)
7. Can control 2 dual-sided double-density floppy
disk drives (4 single-sided drives)
8. A wealth of commands including VERIFY
command
*Can be specified as head load or head unload
9. A wealth of error status indicators available
during command processing
10. CRC generation and checking (X16+X12+X5+ 1)
11. Deleted data address mark (DDAM) processing
capabilities
12. Multi -sector processing capabilities
13. Signals generated for adjusting write data
under MFM recording
14. Inner track processing capabilities
15. Stepping speed, head load time and head unload
time after command processing' are program·
mabie
LCT/DIR 11
RS2
lEO
ORQ
FRISTP
RSo
PSL
CLOCK 15
WOA
WG
RRO
IORQ
FCLK
WOW
21 GNO
Top View
16. Interrupt enable and disable are programmable
17. Window inversion is programmable
18. Input/Output is TTL compatible (except for
clocks)
--'--'~--'--"-SHARP . - . - - - - - - - - - - -
279
,
• I'l
.1 ~
I9
N
00
.0
1
to
I
0"
()
7'
I
I
I
I
I
I
en
I
»
N
'C
/1
L
I
I
I
I
I
I'
C"lUl
o CIl
C"l"l
0"0
C
-""~
""'-'"
~C"l
S"
co
....
9
I\)
3
::;;: :0
:0 :0
Write
0
Unit Select .....
Head Load 00
H~ad Select
Signal ~elect ::
Wmdow'"
Read Raw Data l:l
0
Machine Cycle IRead
Chip Enable
I/O Request
.,. .,.:0
:0
System Data Bus
~ :0
:0 :0
CJ1
CJ1
::;;:
:0
:0 :0
0'>
en
::;;:
:os::
0-'
s::;;0
...,:0
Interrupt Enable In
Data Request
I~terrupt Enable Out
Interrupt Request
..
'I::l
"i
0
"i
9
....
<>
..,....
<:
"" "0z
+
C11
<:
<:>
<:
I;
I
I
I
I
h
I
~
I~
Floppy Disk Controller
•
LH011 O/LH011 OA
Pin Description
Meaning
Pin
Do-D 7
Data bus
110
Bidirectional
3-state
Register select
I
Ml
Machine cycle 1
I
RD
Read cycle
I
Chip enable
I
IORQ
110 request
I
CLOCK
System clock
I
FDC clock
I
lEI
Interrupt enable input
I
IEO
INT
Interrupt enable output.
Interrupt request
DRQ
Data request to DMA
0
Multiplex
0
WP/TRo
Write protect/track zero
I
FLT/TS
Fault/2-side disk
I
FR/STP
Fault reset/step
0
LCT/DIR
Low current/direction
0
RDY
Ready
I
IDX
Index
I
HDS
Head select
0
HDL
US
WG
WDA
RRD
Head load
Unit select
Writing gate
Write data
Read data
0
0
0
0
I
WDW
Window
I
RSo-RS2
-
-
CE
--
FCLK
MUXS
0
Open-drain 0
Function
System data bus
Used to select FDC internal register (RRO-RR6, WROWR7).
Active low. Produced by ANDing Ml and RESET' of
CPU. Active Ml with IORQ causes interrupt.
Active low. Read operations proceed when active.
Active low. Command or data transactions with CPU
,
possible when active.
Active low. Active RD designates read operation; inactive RD designates write operation.
-Interrupt occurs when IORQ and Ml are simultaneously
active.
Standard Z80 system clock is used as internal sync
signal.
2-MHz clock is used for synchronizing FDD control signal(l-MHz clock for mini-floppy control).
Active high. Used to form interrupt priority arbitration
loop circuit (daisy chain).
Active high. Used with IEI to form daisy chain.
Active low. Active when placing interrupt request.
Active high. Data request signal for transactions between FDC and DMA.
Multiplexer select signal.
Active high. WP signal at high MUXS, indicating that
mounted diskette is write-protected. TRo signal at low
MUXS, indicating that the head is positioned at track O.
Active high. FL T signal at high MUXS, indicating fault
status of FDD. TS signal at low MUXS, indicating that
2-side disk is mounted.
Active high. FR signal at high MUXS, resetting fault status of FDD. STP signal at low MUXS, indicating seek.
Active high. Connected to FDD low current input and
direction input. Denotes LCT signal except when seek
command is in effect, becoming high when head selects a
cylinder above track 44. DIR signal during seek command, becoming high when seek direction is toward disk
center (from perimeter).
Active high. FDD ready signal
Active high. Indicates the physical starting point on the
disk track.
With double-sided FDD, low HDS selects head 0 ; high
HDS selects head 1. With single-sided FDD, HDS can be
used as FDD select signal.
Active high. Puts the FDD head in load state.
Active high. Selects FDD unit.
Active high. Write command to FDD.
Active high. Serial data transferred to FDD.
Active high. Serial data from FDD.
Released by VFO circuit, used in separating RRD data
and clock.
------------------SHARP - - - - - - - - - - - -
281
LH011 O/LH011 OA
Floppy Disk Controller
110
0,
Meaning
VFO control,
Pin'
VFO
Function
Active high. Advises lock timing'to VFO'circuit.
Active high. Write correction signal in MFM mode, instructing external write-correction circuit to delay
WDA. Maintains active status in FM mode.
Active high. Write-cortectionsigTIal in MEM mode, in·
structing external write· correction circuit to accelerate
WDA. Maintains active status in FM mode.
,
PSL
Pre·shift
0
P~E
Pre·shift early
0
*Resetting FOC FOC has no reset terminal, but by maintaining Ml at low for more than 2-c1ock lengths when both IORQ and RD,are high,
the FOC's intern~1 reset flag is set and FDC reset is in effect. Reset status can be released by making access to an FOC register.
•
Absolute Maximum Ratings
Parameter
Input voltage
'Output voltage
Operating temperature
Storage temperature
•
Syoibol
VIN
VOUT
T oDr
T st•
Ratings
-0.3-+7
-0.3-+7
0-+70
-55-+150
Unit
V
V
t
t
(V cc =5V±5%, Ta=0-+70t)
DC Characteristics
Parameter
Clock input low voltage
Clock input high voltage
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input leakage current
Data bus 110 leakage current
Supply current
•
Symbol
VCL
VCH
VIL
VIH
VOL
VOH
I ILl I
I Iz I
Icc
Conditions
MIN.
-0.3'
Vee-0.6
-0.3
2.0
IOL=2.0mA
IOH =-250pA
OsVINsV CC
10
10
170
180
O~VIN~VCC
I LHOllO
I
MAX.
0.45
Vee + 0.3
0.8
Vee
0.4
2.4
LHOllOA
Unit
V
V
V
V
V
V
pA
pA
rnA
(f=IMHz, Ta=25t)
Capacitance
Parameter
Clock input capacitance
Input capacitance
Output capacitance
Input/Output capacitance
TYP.
Symbol
CCLOCK
CIN
COUT
Conditions
MIN.
All pins except the one to be
tested should be grounded.
CliO
MAX.
10
7
10
12
Unit
pF
pF
pF
pF
\
'-~~--------"""SHARP -.-..-.----.-.-~
282
I
Floppy Disk Controller
•
AC Characteristics
(1)
CPU interface
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
LH011 O/LH011 OA
(V cc =5V±5%, Ta"",0-+70t)
Parameter
Clock period
Clock pulse width, high
Clock pulse width, low
Clock rise time
Clock fall time
Hold time
Setup time to clock t under read/write cycle.
Delay time from RD J, to data output under
read cycle.
Data setup time to clock t under write/M1
cycle.
Delay time from 10RQ J, to data output
(interrupt cycle).
Delay time to bus floating.
lEI setup time to IORQ J, (interrupt cycle).
Delay time from lEI t to lEO t.
Delay time from lEI J, to lEO J,
Delay time from M1 J, to lEO J,
(at interrupt before M1 J,)
M1 J, setup time to clock t under INTA/M1
cycle.
RD J, setup time to clock t under read/M1
cycle.
Delay time from FCLK J, to INT output
10RQ J, setup time to clock t under 110
cycle.
Symbol
TcC
TwCh
TwCl
TfC
TrC
Th
TsCE(C)
LH0110
MIN.
MAX.
400
111
170
2000
170
2000
0
30
0
30
0
240
TdRI(DO)
TsDI(C)
500
50
TdIO(DIO)
TdRI(DOs)
TslEl(IO)
TdIEI(JEOr)
TdlEl(IEOf)
LH0110A
MIN.
MAX.
250
111
105
2000
105
2000
0
30
0
30
0
145
380
160
ns
160
ns
110
210
190
160
130
ns
ns
ns
ns
300
190
ns
200
TdMl(IEO)
ns
ns
ns
ns
ns
ns
ns
ns
50
340
Unit
140
TsMl(Cr)
210
90
ns
TsRI(C)
240
115
ns
TdC(INT)
Ts(IO)
300
240
300
115
ns
ns
(1) TcC=TwCh+TwCI +TfC+TrC.
t indicates rising edge, l l~dicates failing edge.
. . - . - . . - ., -.. - - . - . - - S H A R P
. ---------283
LH011 OlLH011 OA
Floppy Disk Coi:Jtroller
(2)
FDD interface
Parameter
No.
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
t
,
FDC clock period, standard floppy disk
FDC clock period, mini-floppy disk
FDC clock pulse width, high
FDC clock pulse width, low
FDC clock rise time
FDC clock fall time
Delay time from FDC clock t
Delay time from FDC clock t
(FDC clock !, in the case of MFM)
Write data pulse width, MFM
Write data pulse width, FM
Step pulse width
Step period
Fault reset pulse width
Delay time from clock t to fulfill IORQ
;
setup time
Data request period, MFM
Data request period, FM
Index pulse width
Read data pulse width
WDW setup time to read data
WDW hold time from read data
Window cycle time, MFM
Window cycle time, FM
Delay time from FDC clock ! to VFO
indicates rising edge,
!
Symbol
LHOllO/LHOllOA
MIN.
TYP.
MAX.
500
1000
TcFC
TwFCh
TwFCI
TfFC
TrFC
TdPS(FC}l
Unit
ns
ns
ns
ns
ns
ns
ns
220
220
30
30
280
.•.
170
TdWDA(FC)
250
500
12
.TwWDA
TwSTP
TcSTP
TwFR.
TcWDW
.•.
TdVFO(FC)
f1.S
ms
12
f1S
230
TdDRQ(FC)
TwIDX
TwRRD
TsWDW(RRD)
ThWDW(RRD)
ns
ns
1
16
32
TcDRQ
ns
ns
f1.S
f1.S
50
100
100
100
f1.S
ns
ns
ns
1
2
. f1.S
f1.S
150
ns
indicates falling edge.
~--.-......-----SHARP -----.--:--------~.-
284
LH011 O/LH011 OA
Floppy Disk Controller
•
AC Timing Diagram
"High" "Low"
Timing test level : CLOCK Vcc-O.6V
OUTPUT
2.0V
, INPUT
2.0V
FLOAT
..:IV
0.45V
O.8V
O.8V
O.5V
CLOCK
CE
RSo-RS2
IORQ
RD
--+--1t
I
----------------'h
®~
i
J
F
!
~---
~--@-
lEI
iEO----+@'---
lEO
-.---------SHARP---------285
-
.
:
Floppy Disk Controller
'_ _ _. . . .a._a._ _
~
t,
LH011 O/LH011 OA
....................-....,._ _....._
FCLK
PSL,PSE
WDA
VFO
DRQ
CLOCK
~--®'--.;..j
WDW
RRD
286
Floppy Disk Controller
•
LH011 O/LH011 OA
Internal Structure
•
The FDC consists of a CPU bus interface,· internal control circuit (microprogram controlled), interrupt control circuit and floppy disk drive (FDD)
control circuit. The interrupt control circuit arbitrates device priority and produces interrupt vectors.
The FDC has the registers:
• Two 8-bit data registers (RRO, WRO)
• Six 8-bit status registers (RRl, RR6)
• Seven 8-bit control registers (WRI-WR7)
FDC Registers
(1)
FDC readout registers
Among the seven FDC readout registers RRORR6, RR3 and RR4 are cleared at the beginning of
each command. The registers have the functions
listed in Table 1.
Table 1
FDC readout register functions
Register
RRO
PRI
RR2
PR3
RR4
PR5
PR6
Function
Data buffer
Control status
DMA control status; FDD control status
Error status, A
Error status, B
Physical track address
Sector address
• Read Register 0 (RRO)
I~I~I~I~I~I~I~I~I
~I- - - - - - B u f f e r register for latching data readout from FDD
• Read Register 1 (RR1)
I D7 I
Ds
I Ds I D. I Ds I Dz I Dl I Do I
~
Head selection }
Unit selection
Correspond to D7-Ds of WR3
Status selection
Deleted data address mark (DDAM) detection
(cleared at beginning of each command)
Seek (remains "l"during command execution)
Error B (ORed bits of RR4)
Error A (ORed bits of RR3)
Command end (set by reading RRl)
• Read Register 2 (RR2)
I D7 I Ds I Ds I D. I Ds I D2 I Dl I Do I
~
DRQ
HDL
MUXS
FLT/TS
WP/TRo
(indicate the status of FDD coutrol signals)
IDX
RDY
FDC ready (remains "0" during command execution)
-~-------SHARP--'-'-""-'------287
Floppy Disk. Controller
. LH011 O/LH011 OA
• Read Register 3 (RR3)
I
D7
I D6 I D5 I
D4
I D3 I
Dz
I
D1
I
Do
I
L Mis~ing data transfer (no data transfer between DRQs)
Mis~ing DAM receptio~
(no DAM reception after ID and sync field
dete~tion)
Missing sync field reception (no sync field reception
within stated bytes after ID detection)
Seek error/i1iconsistency error (TRo=O.after stated number of step pulses sent
by SEEK ZERO command; inconsistency of data dete~ted by VERIFY command)
Write error (FLT=l after writing i\lto FDD)
Fault error (FriD fault status when initiating WRITE.
WRITE WITH DDAM or WRITE ID command)
Write protect error (write-protected status when initiating WRITE.
WRITE WITH DDAM or WRITE ID command)
Not-Ready error (FDD not ready at c~mmand initiation.)
• Read Register 4 (RR4)
I
D7
I
D6
I
Ds
I
D4
I
D3
I
Dz
I
D1
I
Do
I
~
CRC error (data field)
CRC error (ID field)
DDAM error (DDAM detected by READ command)
Undefined record length'(ID field data size is not defined.)
Side error (inconsistent side data in ID field)
Address error (track data in ID field inconsistent with WR4)
Defective track (track data in 10 field is FFH)
Missing ID detection (target 10 remains undetected after 5 lOX receptions)
• Read Register 5 (RR5)
' - - - - - - - Current physical track address .
' - - - - - - - . , - - - - - - - U n u s e d (0)
• Read Register 6 (RR6)
I~I~I~I~I~I~I~I~I
IL-____ Sector address following access
' - - - - - - - - - - - - U n u s e d CO)
Table 2
(2)
FDC writing registers
Among the eight registers WRO-WR7 written in
by CPU, WRl, WR3, WR5 and WR6 do not accept
writing when FDC is busy. Tte registers have the
functions listed in Table 2.
288
Register
WRO
WRI
WR2
·WR3
WR4
WR5
WR6
WR7
FDC write register functions
Function
Data buffer
Command designation
Time setting
Number·of·sectors designation and pin control
Logical track address
Physical track address
Sector address
Interrupt vector
LH011 O/LH011 OA
Floppy Disk Controller
Write Register 0 (WRO)
Write Register S (WRS)
I D7 I D6 1 Ds 1 D.I
I~I~I~I~I~I~I~I~I
[
D3 1 D2 1 D, 1 Do 1
Buffer register for data sent to FFD
L
LSector address to be
accessed (same as RR6)
Urjused
Write Register 1 (WR1)
Write Register 7 (WR7)
L FDC
command
Window inversion (inversion prevented by "0")
Index count (index pulse'count after command
completion until head unloading : 0 for 2 pulses
; 1 for 5 pulses)
I~I~I~I~I~I~I~I~I
[ Interrupt vector (read out at INT A)
MFM/FM
-EIIDI interrupt enable flag
•
Commands
Write Register 2 (WR2)
(1)
L
CD
I D7 1 D6 1 Ds
1 D4 1 D31 D2 1 D, 1 Do 1
[Step rate time
(N ms for value N; 20 ms
for value N=O)
Head load time (4M ms for value M; 64 ms for
value M=O)
(time length is doubled for mini -floppy disk)
Write Register 3 (WR3)
[Number of sectors for
continuous access
HDS
L-------US
}
,
(FDD signal control)
~----------MUXS
Write Register 4 (WR4)
[Track address (seek track address
under SEEK command; track address
in ID field in other commands)
Unused
Write Register S (WRS)
(same as RR5)
Unused
Brief description
SEEK ZERO (0000/1)
Draw the head up to track 00. With command
having LSB=O, task is excuted while retaining the
head unload status; with LSB= 1, it is excuted
while retaining the head load status.
® SEEK (0010/1)
Move the head to specified track. With LSB=O,
task is execused while retaining the head unload
status; with LSB= 1, it is executed while retaining
head load status.
® READ (0100)
Read data from specified sector and transfer
each byte in data section to main system. When
data address mark is DDAM, operation is terminated as DDAM error.
e!) READ DDAM (0101)
Same as READ command, except that address
DAM causes DDAM error, while DDAM does not
cause error.
(§) READ BOTH (0110)
Same as READ command, except that address
mark DDAM does not cause error.
® READ CRC (0111)
Same as READ BOTH, except that data is not
transferred to main system.
(J) VERIFY (1000)
Compare each byte in data section read out from
a specified sector with the corresponding byte of
data received from main system.
® READ ID (1001)
Read out data in ID section of specified track and
transfer each byte to main system.
® WRITE (1010)
Write each byte of data received from main system into specified sector.
-----......-------SHARP--.-.....I.---------289
LH011 O/LH011 OA
Floppy Disk Controller'
WRITE 1D1 26 sectors/track (FM: 12.8 bytes/
sector; MFM: 256 bytes/se(!tor)
WRITE 1D2 15 sectors/track (FM: 256 bytes/
sector; MFM: 512 bytes/sector)
WRITE 1D3 8 sectors/track (FM: 512 bytes/sector; MFM: 1024 bytes/sector)
~ RESET STATUS (1111)
Initialize floppy disk drives.
@ WRITE WITH DDAM (1011).
Same as WRITE command, except that DDAM
and not DAM is written as address mark.
@ WRITE 1D1 (1100) \
@ WRITE 1D2 (1101)
@ WRITE 1D3 (1110)
Write initialization (ID section) and gaps of specified track. In this command, data section is filled
with gaps.
(2)
Commands and error status register A
::s::
Error status
Not-reaDB7
dy-error
Write proDB6
tect error
DB5 Fault error
DB4 Write error
Seek error
DB3
Inconsistencyerror
Missing
DB2 sync field
reception
Missing
DBI DAM
reception
Missing
DBD data
transfer
READ READ
DDAM BOTH
WRITE WRITE
RESET
READ
READ
VERIFY
WRITE WITH
ID
STATUS
eRe
ID
DDAM 1,2,3
SEEK
ZERO
SEEK
READ
X
0
0
0'
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
0
0
0
X
X
·X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
0
0
0
0
X
X
X
X
X
X
X
0
0 ..
0
0
0
X
X
X
X
X
X
X
0
0
0
X
0
0
0
0
0
X
X
(~) Commands and error status register B
~
Error status
Missing ID
DB7
detection .
DB6 Defect track
Address
DB5
error
DB4 Side error
Undefined
DB3 record
length
,DDAM
DB2
error
eRe error
DBI
(ID field)
eRe error
DBD
(data field)
WRITE WRITE
RESET
READ
READ
WRITE WITH
VERIFY
ID
eRe
ID
STATUS
DDAM 1,2,3
SEEK
ZERO
SEEK
READ
X
X
0
0
0
0
0
0
0
0
X
X
X
X
0
0
0
0
0
X
0
0
X
X
X
X
0
0
0
0
0
X
0
0
X
X
X
X
0
0
0
0
0
X
0
0
X
X
X
X
-0
0
0
0
0
X
0
0
X
X
X
X
0
0
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
Or
0
0
X
X
X
X
0
0
0
0
0
X
X
X
X
X
READ READ
DDAM BOTH
--------SHARP-------290
Floppy
•
Dis~
LH011 O/LH011 OA
Controller
CPU Interface Timing
(1)
(3)
FDC write cycle
RSo
RS2
Interrupt acknowledge cycle
MI
-,L_ _ _ _ _ _r----
lEI
====-===_1
I
I
CE
MI,RD--------------~-----------
r::
Do-D7 ______~I~_______________
Do-D7--------------~c::J~------
Vector
(2)
(4)
FDC read cycle
CLOCK
Interrupt return cycle
CLOCK
MI
____________c=
~
~~~
__
r--~
__
~----
RD
----~CJ~------~~~-----
MI
==:::':.::.-_-:.J"r-------------ED
lEI
,'-_____-Jr---
lEO
4D
----------------------~,---
Do -D 7 - - - - - - - - - - - - - - - -__<::::)---Data
---------~------SHARP ---~-.-------291
!
.-.-.-~-.-~-~
•
.--.....
..... .....
Flbppy Disk Controller
~
LH011 O/LH011 OA
~.-:
FDD Interface Timing
. (1)
READ, READ DDAM, READ BOTH, READ CYC, VERIFY, READ 10 command timing
-------1H)~J__-
,~
=::::~------~~
Command termination-:----r--
..lo......-------!H
-!~---
~---------~Jj
l~j---
.j)J--'-
('
11
--'---..A.---------it}
:) 1 - - - -
!
5~Falls if next command
No head load walt time needed if preceedmg command was
is not issued within a
certain time span.
a read/write command.
.
. f
.
.
--L1,:::;SL:yn:,:;;c.J.,.1~ID;U...I_--r.;ls;;,:YD;;;;;c.J.,.1---\rl~:_--l._-..JI.;;s~YD:::..cIL.o:1;:;:D. J,I_ _
Gap
(2)
Data section
. Gap
PSL and PSE timing
FCLK
WDA
-1l
D
n
C
D
n
C
D
C
D
C
~
D
PSL
PSE
MFM mode
FCLK
WDA
PSL
PSE
J CI
High
n
D
n
C
D
11.:..C
FM mode
- - - - - - . . . . . - - . - - . . . - . - - S H A R P -.-.--~-,-.--
292
Floppy Disk Controller
LH011 O/LH01.1 OA
(3) WRITE 101, WRITE 102, WRITE 103 command timing
~--------~n~------~i~~(--'------.....-.l!l
{~'r--~Com~~i~
Jl
T---------------~\~\------------~5~rj- - - - -
\~j
----J''----------ll!
Falls if next command
(
(I-----(~~ •
•
d ·th·
. 'C IS not I.SSU~ WI ID
- - - -__r......c::;NLo head load wait time needed if preceeding command was
a read/write command.
r a certam hme span.
f
5~~f-I
_ _ _ _ _--11
Jl
i~fj...___
X
X
~t::::to---=
Valid
~~
Valid
U
ID
II
gap
Gap Sync
1t::::tD==
lJ
ISync I I
)1
Gal!
ID
(4) WRITE, WRITE WITH OOAM command timing
US
HDS
=:::x
II
r{
::::::x'--------l(\}-.---------\11(----1.J
If-f--C-o-m-m-a-nd-te-r-m-in-a-ti-on-:::C~--------
MUXS _____
RDY
::J~~--------{ljf---------j~!-----
LCT
_ _ _J\...X
HDL
--------i}~
~(..
If---\~alls If next command
No head load wait time needed if preceeding command was ~is not issued within
(head/write command.
a certain time span.
!
~l-l- - - - -
VFO
------I.
WG
--------------~~~~------il(~-----
WDA
PSE
PSL
.
------------~~========~r\~~·====
-----~~~----~I~~----....L..--L...-~.I-~.I-..LI--tH
Sync ID ,
.
Gap
I
\ Data section
Sync
Gap
Sync ID
.--.-.-----SHARP-.--------
293
LH0110lLH0110A
Floppy Disk Controlle,r
(5)
RESET STATUS command timing
MUXS
:.:.J
L..:'
TYP.
FR.
-J 12ps l+rlL._'_---:._
FLT
DIR'
HDL
(6) SEEK ZERO command timing
MUXS:-1~
____________~~______~r::
STP
TY .
12ps
15}ls for 20ms seek rate time
HDL
__-LI____________________~~~------------
DIR
::t~
TRO
------------------------~l~
____________________
~ij~----------
(7) SEEK command timing
MUXS~~_ _ _ _ _ _ _ _~!~---Lr-:
STP
c:::::J
,
'
!----ITY~
12ps 15}ls for 20ms seek rate time
HDL
__-LI____________________~:----~------
J
DIR
RDY
294
.;,.j
~
)
LH011 O/LH011 OA
Floppy Disk Controller
•
System Configuration
Low current
LCT/DIR
Dire ction
MUXS
!
FR/STP
----WP/TR o
Multiplexer
FLT/TS
LHOIIO
FOC
-
Fault reset
-
Write protect
-
--
Step
Track zero
Fault
....- 2-side disk
US
Unit select
HDS
Head select
HDL
Head load
WG
Writing gate
IDX
Index
RDY
Ready
RRD
Read data
WDW
VFO circuit
VFO
6
PSL
PSE
WDA
~
MFM
~
Delay
circuit
Write data
CJ2MHz
FCLK
Oscillator
(lMHz fo r mini -floppy disk)
.-.----~~-SHARP~-.----------.-,
295
--............
.....
Z80 CMOS Central Processing Unit
~
-
-~-
LH5080/LH5080L/LH5080LM
zao
CMOS Central Processing Unit
•
Description
The LH50BO is 2BO CPU fabricated with CMOS
silicon-gate process technology and is fully compatible with the conventional NMOS 2BO CPU
(LHOOBO).
The LH50BO is designed with CMOS fully static
circuits and so provides low power consumption
and wide range power supply voltage operation. '
The LH5080LlLH5080LM provides power save
mode controlled by software. '
•
Features
1. 2BO CMOS CPU
2. Fully compatible with the NMOS 2BO CPU
(LHOOBO)
3. 15B instructions
4. 22 registers
5. 3 modes of maskable interrupt and a nonmaskable interrupt
6. Instruction fetch cycle 1.6 flS
7. Single + 5V power supply and single phase
clock
B. All inputs and outputs except clock input fully
TTL compatible
9. Fully static operation (DC-2.5MHz)
10. Low power consumption
11. Power save mode (LH50BOLlLH50BOLM)
12. 40-pin dual-in-line package
(LH50BO/LH5080L)
13. 44-pin quad-flat package (LH50BOLM)
Note: The l80 CMOS CPU (LH5080/LH5080LlLH5080LM) is
compatible with the l80 NMOS CPU (LH0080). So there is
no descrip.tion here about the pins, CPU registers,
architecture, interrupts, basic timings, and instruction, sets.
Refer back to the l80 NMOS CPU described earlier.'
,
29p
-
... .. ......- . -...-,..-..............
.-
LH5080/LH5080LlLH5080LM
•
Pin Connections
LH5080/LH5080L
o
Z80 CMOS Central Processing Unit
•
LH5080/LH5080L/LH5080LM
Block Diagram
System Data Bus
A
Halt State
Memory Request
Data Bus Interface
Input /Output Request
Read
Write
Bus Acknowledge
Machine Cycle 1
Refresh
Interrupt Request
CPU
Timing
Control
Instruction
Decoder
Inst.
Reg.
ALU
Register Array
Non Maskable Interrupt
Wait
Bus Request
Reset
Address Logic
a~d
Buffer
System Address Bus
297
Z80 CMOS Central Processing Unit
, ,.-..-.-.-.:__,._..
LH5080/LM50BOLlLH5080LM
....__,._.......-....................i.r.....r.--
~
•
Absolute Maximum Ratings
Parameter
Input voltage
Output voltage
Symbol
VIN
VOUT,
Ratings
-0.3-+7
-0.3-+7
Unit
V
V
Operating'temperature
Topr
0-+70
t
Storage temperature
T s ,"
-65-+150
t
•
(Vee=5V±10%, Ta=0-+70t)
DC Characteristics
Parameter
Clock input low voltage
Clock input high voltage
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Current conswnption
Input leakage current
3·state output leakage current
3·state output leakage current
Data bus leakage current
Current conswnption in PS
mode (LH50BOL/LH50BOLM)
Symbol
VILC
V IHC
VIL
VIH
VOL
VOH
Icc
I ILl I
IILOH I
I ILOL I
I ILD I
leeps
Conditions
IOL=1.BmA
IOH=-250 pA
(Note)
VIN=OV, Vee
VouT=Vee
VOUT=OV
MIN.
-0.3
Vee- 0.6
-0.3
2.4
TYP.
MAX.
0.45
Vcc+ 0.3
Note
1
2
2
10
pA
pA
pA
pA
150
pA
O.B
Vee
0.4
2.4
10
10
10
10
O~VIN~Vee
VIH=;,OV, Vee
Output pin open
Unit
V
V
V
V
V
V
mA
50
Note: TcC=400ns, Vn.=O.~ VIH=Vcc-OAV, output pin open.
Notel: The INT , WAIT, NMI and (BUSRQ) pins are arranged as shown below. Note 2: The Ao-A3 pins are arranged as shown below.
Note 1 and 2: The Do- D7 pins are arranged as shown ,below.~
•
(f=1MHz, Ta=25t)
Capacitance
Symbol
CeLocK
CIN
COUT
298
Parameter
Clock capacitance
Input capacitance
Output capacitance
MAX.
5
6
10
Unit
pF
pF
pF
Unmeasured pins returned
to ground
Z80 CMOS Central Processing Unit
•
AC Characteristics
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
t
Parameter
Clock cycle time
Clock pulse width (high)
Clock pulse width (low)
Clock fall time
Clock rise time
Clock t to address valid delay
Address valid to MREQ ~ delay
Clock ~ to MREQ ~ delay
Clock t to MREQ t delay
MREQ pulse width (high)
MREQ pulse width (low)
Clock ~ to MREQ t delay
Clock ~ to RD ~ delay
Clock t to RD t delay
Data setup time to clock t
Data hold time after RD t
WAIT setup time to clock ~
WAIT hold time after clock ~
Clock t to M1 ~ delay
Clock t to M1 t delay
Clock t to RFSH ~ delay
Clock t to RFSH t delay
Clock ~ to RD t delay
Clock t to RD ~ delay
Data setup to clock t during
M2, M3, M4 or Ms cycles
Address stable prior to IORQ ~
Clock t to IORQ ~ delay
Clock ~ to IORQ t delay
Data stable prior to WR ~ (memory cycle)
Clock ~ to WR ~ delay
WR pulse width
Clock ~ to WR t delay
Data stable prior to WR ~ (110 cycle)
Clock t to WR ~ delay
Data stable from WR t
Clock ~ to HALT t
NM1 pulse width
BUSREQ setup time to clock t
BUSREQ hold time after clock t
Clock t to BUSACK ! delay
Clock ! to BUSACK t delay
Clock t data float delay
Clock t to control output float
----delay (MREQ, IORQ, RD, and WR)
LH5080/LH5080LlLH5080LM
(Vcc=5V±10%, Ta=0-+70·C)
Symbol
TcC
TwCh
TwCl
TfC
TrC
TdCr (A)
TdA (MREQf)
TdCf (MREQf)
TdCr (MREQr)
TwMREQh
TwMREQ1
TdCf (MREQr)
TdCf (RDf)
TdCr (RDr)
TsD (Cr)
ThD (RDr)
TsWAIT (Cf)
ThWAIT (Cf)
TdCr (Mlf)
TdCr (M1r)
TdCr (RFSHf)
TdCr (RFSHr)
TdCf (RDr)
TdCr (RDf)
TsD (Cf)
TdA (IORQf)
TdCr (IORQf)
TdCf (IORQr)
TdDm (WRf)
TdCf (WRf)
TwWR
TdCf (WRr)
TdDi (WRf)
TdCr (WRf)
TdWRr (D)
TdCf (HALT)
TwNMI
TsBUSRQ (Cr)
ThBUSRQ (Cr)
TdCr (BUSAKf)
TdCf (BUSAKr)
TdCr (Dz)
TdCr (CTz)
MIN.
400*
180*
180
MAX.
30
30
145
125*
100
100
170*
360*
100
130
100
50
15
70
15
130
130
180
150
110
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
np
ns
ns
ns
ns
ns
60
320*
120
110_
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
110
ns
90
110
190*
90
360*
100
20*
80
120*
300
80
80
15
Rising edge, ~ Falling edge .
.....--.-.-.--.---SH~RP-------.-.
299
LH5080/LH5080L/LH5080LM
Z80'CMOS Central Processing Unit
No.
44
45
46
47
4S
49
50
51
52
53
Parameter
Clock t to address float delay
MREQ t ,IORQ t, RD t, and
WR t to address hold timE:
RESET to clock t setup time
Clock t to RESET hold time
INT to clock t setup time
Clock t to INT hold time
M1 ! to IORQ ! delay
Clock ! to IOR~ ! delay
Clock t to IORQ t delay
Clock ! to data valid delay
Symbol
TdCr (Az)
MIN.
Unit
ns
TdCTr (A)
160*
ns'
TsRESET (Cr)
ThRESET (Cr)
TsINTf (Cr)
ThINTr (Cr)
TdMIf (IORQf)
TdCf (IORQf)
TdCf (IORQr)
TdCf (D)
90
15
SO
15
920*
os
ns
' ns
ns
ns
ns
ns
ns
MAX.
110
110
100
230
t Rising edge, ! Falling edge
• For clock periods other than the minimums shown in the table, calculate parameters using the expressions in, the table on
the following page.
'
.. All timings are preliminary and subject to change.
Footnotes to AC Characteristics
No.
1
2
7
10
11
26
29
31
33
35
45
50
Symbol
TcC
TwCh
TdA (MREQf)
TwMREQh
TwMREQl
TdA (IORQf)
TdD (WRf)
TwWR
TdD (WRf)
TdWRr (D)
TdCTr (A)
TdMlf (IO~Qf)
Formula
TwCh+TwCl+TrC+TfC
MAX. 2001's
TwCh+TfC-75
TwCh+TfC-30
TcC-40
TcC-SO
TcC-210
TcC-40
TwCI+TrC-1S0
TwCl+TrC-SO
TwCI+TrC-40
2TcC+TwCh+TfC-SO
AC Test Conditions
e Input voltage amplitude: 004 V to 2.8V
e Input judge level: 0.8V and 2.0V
e Input signal rise and fall time : IOns
eOutput judge level: 0.8V and 2.0V
eClock input voltage amplitude: OAV to
eOutput load: ITTL+ 100 pF
Vcc-0.6V
Output Pins Measuring Circuit
Output pin o-.......~t-----1Ie-~
CR,
CR 3
CR.
CRI-CR<: IN914 or eguivalent
CI: 50pF for all pins
---.------,~--SH~RP.--,.-----~--
300
.........
Z80 CMOS Central Processing Unit
•
Power Save Function
The LH5080L/LH5080LM features the power
save (PS) function. After a HALT instruction has
been executed, the internal clock signal is automatically cut off to bring the CPU into the halt mode.
(1) PS mode setting
With a HALT instruction executed, the PS mode
will be automatically established. In this mode, the
internal clock signal is cut off to save the power
consumed for the clock signal operation. Cutting an
external clock signal does not give any problem inside, therefore, in this mode. To cut off the external
clock, it is possible to utilize the rise timing of a
HALT signal output. It should be noted, however,
that this timing cannot be used to restart the external clock.
In the PS mode, the bus request (BUSRQ) is not
accepted and the memory refresh is not done,
either.
LH5080/LH5080L/LH5080LM
is then cleared and the reset just as before is
carried out.
(ii) Clearing with NMI: Input the NMI signal
(edge trigger) to clear the PS mode and to carry out the instruction next to the HALT. Now
the non-maskable interrupt processing routine
will be introduced.
(iii) Clearing with INT: Input the INT signal
(level trigger) regardless of which state the interrupt enable flag is in. The PS mode is now
cleared and the HALT instruction executed. If
the interrupt enable flag is set up and the INT
signal is "Low' at the clock pulse rise timing
in the last clock cycle of the HALT instruction,
the mask able interrupt processing routine will
be introduced as the next machine cycle.
CLOCK
HALT~
PS·,
~~--Ml---------------------
RESET
CLOCK
.
...:===~~~~~~~~-r---
Ml
* PS is internal signal, and not output externally.
PS· _+--+~+--+...J
Halt clear by NMI INT
* PSis internal signal, and not output externally.
PS mode setting
CLOCK
HALT
(2)
PS mode clear
The PS mode is cleared by any of the following;
reset (RESET), non-maskable interrupt (NMI) and
maskable interrupt (INT).
When the external clock is shut down in the PS
mode, a stable clock signal must be input before
clearing the PS mode.
(i) Clearing with RESET: Input the RESET signal for more than 3 clock cycles. The PS mode
PS·
NMI
INT
* PS is internal signal, and not output externally.
PS mode clear by MI signal
------------SHARP .-.-..---------301
zao. CMOS Parallel 1/0 Controller
LH5081 fLH5081 L/LH5081 LM
,;.tI!IIIIIII'.-..-.....
......-..-..-..-,..-..- ..- -...... - . - . .....,~
LH5081/LH5081L/LH5081LM
zao CMOS Parallel 110 Controller
•
Description
The LH5081 is Z80 PIOfabricated with.CMOS
silicon gate prQ(;ess techrlOlogy and is fully compatible with the conventional NMOS Z80 PIO
(LH0081).
The LH5081 is designed with CMOS fully static
circuits and so provides low power consumption
and wide range power supply voltage operation.
The LH5081L1LH5081LM provides power save
mode controlled by softwave.
-
•
Pin Connections
LH5081/LH5081L
CE 4
C/D SEL 5
BIA SEL 6
Features
1. Z80 CMOS PIO
2. Fully compatible with NMOS Z80 PIO
(LH0081)
3. Tow independent 8-bit bidirectional peripheral
interface ports with handshake data transfer
control
4. 4 programmable operating modes
• Byte input mode
• Byte output mode
• Byte bidirectional bus mode (Port A only)
• Byte control mode
5. Programmable interrupt on peripheral status
conditions
6. Vectored daisy chain priority interrupt
7. Darlington transistor drive capability (port B
output)
8. All inputs and outputs except clock input fully
TTL compatible
9. Single +5V power supply and single phase
clock
10. Fully static operation (DC-Z.5MHz)
11. Low power consumption
12. Power save mode (LH5081L1LH5081LM)
13. Status read mode (LH5081L1LH5081LM)
14. 40-pin dual-in-line package
(LH5081/LH5081L)
15. 44-pin quad-flat package (LH5081LM)
Note: The Z80 CMOS CPU (LH5081/LH5081L) is compatible
•
with the Z80 NMOS PIO (LH0081). So there is no descrip·
tion here about the pins, programming, and basic timings
waveforms. Refer back to the Z8.0 NMOS PIO described
earlier.
302
•
Top View
LH5081LM
1
Top View
2
3
I~I~ ~
Z80 CMOS Parallel 1/0 Controller
•
LH5081/LH5081 L/LH5081 LM
Block Diagram
Internal
Control Logic
Port A
Input!
Output
System
Data
Bus
Port A
Data Bus
CPU
Bus
Input!
Output
Logic
Port A!B Select
Command/Data
Select
Chip Enable
Macbine Cycle 1
I!O Request
Read
Port B
Input!
Output
Port B
Data Bus
~
Interrupt
Control Logic
:; > ....u0
It)
= u
+
Q
.,;;
(.!)
u
z
.e
...
'Vi
CIl
..'". .s. ..'"
.'" ::c... ::c..
0
<:I'
..
..'" .
'"
!
.s !. ...'"
p::
Q.
r.z:I
Q.
....
r.z:I
Q.
!
.s
----~-.-----SHARP ----.----------~
303
LH5081 ILH5081 LlLH5081 LM
Z80 CMOS Pataltel 1/0 Unit'
•
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
•
Symbol
Vcc
VIN
VOUT
Topr
Ts".
Ratings
-0.3-7.0
-0.3-Vcc +0.3
-0.3-Vcc +0.3
0-+70
-65-+150
Unit
V
V
V
t
t
(Vcc=5V±10%, Ta=0-+70t)
DC Characteristics
Parameter
Clock input low voltage
Clock input high voltage
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Current consumption
Input leakage current
3-state output leakage current
3-state output leakage current
Data bus leakage current input
Darlington drive current
Current consumption in PS
mode (LH5081L/LH5081LM)
Symbol
VILC
VIHC
VIL
V IH
VOL
Conditions
MIN.
-0.3
Vcc- O.G
-0.6
2.2
10HD,
10L =2inA
IOH=-1.6mA
10H= -250 1'A
(Note)
VIN=OV, Vcc
VOUT=VCC
VOUT=OV
oS::VIN S::VCC
V OH = 1.5V, Port only
Iccps
Output pin open, VIN=OV, VCC
VOH
Icc
I ILl I
I lLOH I
I lLOL I
I ILD I
TYP.
MAX.
0.45
Vcc+ 0.3
0.8
Vcc+ 0. 3
0.4
2.4
Vee -D.4V
2
6
10
10
10'
10
-1.5
1
100
Note TcC=400ns, VIL=OAV, VIH=VCC-O.4V, output pin open.
Note 1: The A STB and B STG pins are arranged as shown below. • The INT pin is arraged as shown below.
Note 2: The Ao-A7 and Bo-B7 pins are arranged as shown below.
•
Parameter
Clock capacitance
Input capacitance
Output capacitance
304
""ID-'
L
Interruput request
(f=lMHz, Ta=25t)
Capacitance
Symbol
CCLOCK
CIN
COUT
Conditions
Unmeasured pins returned
to ground
-Note
pA
I'A
I'A
I'A
1
2
2
rnA
-
,.,,,,,,,,,, ,,1m••
Unit
V
V
V
V
V
V
V
rnA
MAX.
7
7
10
Unit
pF
pF
pF
pA
Z80 CMOS Parallel I/O Controller
•
LH5081 ILH5081 L/LH5081 LM
AC Characteristics
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
(V cc =5V±10%, Ta=0-+70t)
16
Parameter
Clock cycle time
Clock width (high)
Clock width (low)
Clock fall time
Clock rise time
CE, BfA, CfD to RD, 10RQ ~ setup time
Any hold times for specified setup time
RD, 10RQ to clock t setup time
RD, 10RQ ~ to data output delay
RD, 10RQ t to data output float delay
Data in to clock t setup time
10RQ ~ to data o_ut delay (INT ACK cycle)
M1 ~ to clock t setup time
Ml t to clock ~ setup time (Ml cycle)
Ml ~ to lEO ~ delay
(interrupt immediately preceding MI l)
lEI to 10RQ ~ setup time (INT ACK cycle)
17
lEI
18
lEI t to lEO t delay (after ED decode)
10RQ t to clock ~ setup time
(to activate READY on next clock cycle)
15
19
l
to lEO ~ delay
t
20
Clock ~ to READY
21
22
Clock ~ to READY l delay
STROBE pulse width
STROBE t to clock ~ setup time
(to activate READY on next clock cycle)
10RQ t to PORT DATA stable delay (mode 0)
PORT DATA to STROBE t setup time
(mode 1)
STROBE ~ to PORT DATA stable (mode 2)
STROBE t to PORT DATA float delay
(mode 2)
PORT DATA match to INT l delay (mode 3)
STROBE t to INT ~ delay
23
24
25
26
27
28
29
delay
Symbol
TcC
TwCh
TwCI
TfC
TrC
TsCS (RI)
Th
TsRI (C)
TdRI (DO)
TdRI (DOs)
TsDI (C)
TdlO (DOl)
TsMI (Cr)
TsMI (Cf)
MIN.
400
170
170
30
30
50
15
115
430
160
50
340
210
0
TdMI (lEO)
TsIEI (10)
MAX.
(Note l)
300
140
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
6
2
CL =50pF
3
8
ns
5,7
ns
7
5
TdlEI (IEOf)
190
ns
TdlEI (lEOr)
210
ns
CL =50pF
5
TcIO(C)
220
ns
TdC (RDYr)
200
ns
TdC (RDYf)
TwSTB
150
150
ns
ns
5
CL =50pF
5
4
TsSTB (C)
220
ns
5
ns
5
TdlO (PD)
TsPD (STB)
200
ns
260
TdSTB (PD)
230
ns
5
TdSTB (PDr)
200
ns
CL =50pF
TdPD (INT)
TdSTB (INT)
540
490
ns
ns
t Rising edge, ~ Falling edge
Note 1: TcC=TwCh+TwCl+TrC+TtC.
Note 2 : Increase TdRI (DO) by 10 ns for each 50 pF increase in load up to 200 pF max.
Note 3 : Increase TdIO (001) by 10 ns for each 50 pF, increase in loading up to 200 pF max.
Note 4 : For Mode 2 : TwSTB>TsPD (STB).
Note 5 : Increase these values by 2 ns for each 10 pF increase in loading up to 100 pF max.
Note 6 : TsCS (RI) may be reduced. However, the time substracted from TsCS (RI) will be added to TdRI (DO).
Note 7 : 2.5 TcC > (N·2) TdIEI (IEOf)+TdM1 (IEO)+TsIEI (10) + TTL Buffer Delay, if any.
Note 8 : M1 must be active for a minimum of two clock cycles to reset the PIO.
AC Test Conditions:
• Input voltage amplitude: OAV to 2.8V
• Clock input voltage amplitude: OAV to Vcc-O.6V
• Input signal rise and fall time : IOns
• Input judge level: O.8V and 2.0V
• Output judge level: O.8V and 2.0V
• Output load: ITTL+ lOOpF (unless otherwise specified)
------~.--.----SHARP
. - . - - . - . - . . - - ......... 305
LH5081 ILH5081 LlLH5081 LM
Z80 CMOS Parallel I/O Controller
•
Power Save and Status Information
Read Function
Un1ike the LH00811LH5081, the LH5081Ll
LH5081LM has the power save (l:'S) and status information read functions.
(1 ) Power save function
(i) PS mode setting
When the CPU
(LH5080LlLH5080LM) has executed an HALT instruction in the PS mode, the LH5081LlLH5081LM
reads this HALT instruction to automatically go
into the-PS mode. Now the internal clock signal is
cut off. Therefore, cutting an external clock input
gives no problem inside in this mode.
Data--------~r---~~---+---------
PS'
----------------~
PS mode set timing
Bits
Ml
ps'
(ii) PS mode clear
The. PS mode is cleared
by detecting the fall of the Ml signal. When the external clock is off in the PS mode, however, a stable
clock signal must be input before clearing the PS
mode.
When the CPU (LH50~OLlLH5080LM) is
cleared from the PS mode and comes into the next
fetch cycle, therefore, the LH5081LlLH5081LM is
also cleared from itsPS mode at ~he fall of the first
Ml signal in this cycle.
The PS mode clearing can be done by issuing an
interrupt request.
Set up the interrupt generate conditions in Mode
3 of the LH5081LlLH50S1LM. By this, an interrupt request (INT) is issued even in the PS mode,
the CPU (LH5080LlLH5080LM) is cleared from
the PS mode, and thus LH5081LlLH5081LM is
also cleared.
(2) Status information read
Under the following conditions, the mode setup
bits and handshake signals of Port A and Port B
are read from the data bus during the read cycle.
See the chart below.
Conditions: CE = "Low"~RD = "Low", IORQ
"Low", C/D = "High", BI A = X (undefined)
Return to original state
* PSis internal signal and not output externally.
PS mode clear timing
7
6
5
4
3
2
1
0
IAMIIAMOjARD\jASTIlI BMII BMO~RDYjilSTBI .
I
~most
~he
two bits of
Uppermost two bits of tbe
B port mode co~t~ol reglstor
Aport mode control registor
(Set mode bIts)
(Set mode bits)
LH5081/LH5081 LM status information words
306
Z80 CMOS Counter Timer Circuit
LH5082/LH5082L1LH5082LM
LH5082/LH5082L/LH5082LM
zao
CMOS Counter Timer Circuit
•
Description
The LH5082 is 280 CTC fabricated with CMOS
silicon-gate process technology and is fully compatible with the conventional NMOS 280 CTC
(LH0082).
The LH5082 is designed with CMOS fully static
circuits and so provides low power consumption
and wide range power supply voltage operation.
The LH5082L1LH5082LM provides power save
mode controlled by software.
•
•
Pin Connections
LH5082/LH5082L
o
Features
1. 280 CMOS CTC
2. Fully compatible with the NMOS 280 CTC
(LH0082)
3. 4 independent programmable 8-bit counter/
16-bit timer channels
4. Selectable counter/timer mode for each channel
5. Programmable interrupt triggered by counter/
timer
6. Downcounters !;eloaded automatically at zero
count
7. Readable downcounters
8. Selectablp. 16 or 256 prescaler (timer mode)
9. Selectable positive or negative triggers for timer
and selectable positive or negative clock edge
for counter
10. 2C/TO outputs of three channels capable of
driving Darlington transistors
11. Vectored and daisy chain piority interrupt
12. Single + 5V power supply and. single phase
clock
13. All inputs and outputs except clock input fully
TTL compatible
14. Fully static operation (DC-2.5MHz)
15. Low power consumption
16. Power save mode (LH5082L1LH5082LM)
17. 28-pin dual-in-line package
(LH50821LH5082L) .
18. 44-pin quad-flat package (LH5082LM)
Top View
o
"
U
Z
Top View
Note: The Z80 CMOS CTC (LH50821LH5082L/LH5082LM) is
compatible with the Z80 NMOS CTC (LH0082)_ So there is
no description here about the pins, programming, and basic
timing waveform. Refer back to the Z80 NMOS CTC described earlier.
-~--------SHARP--'-''--'-'------
307
LH5082~LH5082L/LH5082LM
Z80 CMOS Counter Timer Circuit·
•
Block Diagram
Zero Count/
Timeout 0
Clock/Trigger 0
Internal
Control
Logic
System'
Data
Bus
Zero Count/
Timeout 1
Clock/Trigger
CPU Bus
Input/
Output
Logic
Zero Count/
Timeout 2
Channel {
Select
Clock/Trigger 2
Machine Cycle 1
Interrupt
Logic
I/O Request
Clock/Trigger 3
_
~
'"
'"
III
~
S
> >
c:> "' ....
+ ~~.l
LI)
u zu)u
~ t!l
_ c=
~ t;
...
Q)
-
§": ~O
....
_::1
t & t~
t:i
!~]~!~
,.!;~
.-.-.----.....,.-.--SHARP-.-.------308
Z80 CMOS Counter Timer Circuit
•
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
•
LH5082/LH5082L/LH5082LM
Symbol
Vee
VIN
VOUT
ToDr
TstQ
Ratings
-0.3-+7.0
-0.3-Vee +0.3
-0.3-Vee +0:3
0-+70
-65-+150
Unit
V
V
V
t
t
(Vee =5V±10%, Ta=0-+70t)
DC Characteristics
Parameter
Clock input low voltage
Clock input high voltage
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Current consumption
Input leakage current
3-state output leakage current
3 -state output leakage current
Symbol
VILe
V IHe
V IL
. V LH
VOl.
VOH
I Icc I
I ILl I
I ILOH I
I IIOL I
Darlington drive current
IOHD
Current consumption in PS
mode (LH5082L1LH5082LM)
Iccps
Conditions
IOL =2mA
IoH =-1.6mA
IoH = -250pA
(Note)
VIN=OV, Vee
VouT=Vee
VOUT=OV
V()H=1.5V
AppIicated to ZC/TOo-ZCIT0 2
MIN.
-0.3
Vee- 0.6
-0.3
2.2
TYP.
MAX.
0.45
Vee+ 0.3
0.8
Vee
0.4
2.4
Vcc--:OAV
2.5
8
10
10
10
-1.5
Output pin open, VIN=OV, Vee
Unit
V
V
V
V
V
V
V
rnA
pA
pA
pA
Note
1
rnA
1
100
pA
Note: TcC=400ns, TcCTR=l p.s, VIL=O.4V, VIH=Vee-O.4V, output pin open.
Notel: The CLK/TRGo-CLK/TGa pins arranged as shown below.
•
(f=lMHz, Ta=25t)
Capacitance
Parameter
Clock capacitance
Input capacitance
Output capacitance
Symbol
CeLOeK
CIN
COUT
Conditions
Unmeasured pins returned
to ground
MAX.
5
5
10
Unit
pF
pF
pF
309
LH5082/LH5082L1LH5082LM
280 GMOS Counter Timer Circuit
•
(V cc =5V±10%, Ta;;=0-+70"C)
AC Characteristics
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Para!lleter
Clock cycle time
Clock width (high)
Clock width (low)
Clock Jail time
Clock rise time
All hold times
CS to clock t setup time
CE to clock _t setup time
IORQ ~ to clock t setup time_
RD ~ clock t setup time
Clock t to data out delay
Clock ~ to data out float delay
Data In to clock t setup time
Ml to clock t setup time
Ml ~ to lEO ~ delay
(interrupt immediately preceding Ml)
IORQ ~ to data out delay (INT A cycle)
lEI ~ to lEO ~ delay
lEI t to lEO t delay (after ED decode)
Clock t to INT ~ delay
- CLK/TRG t to INT ~ delay
(tsCTR (C) satisfied)
CLK/TRG t to INT ~- delay
(tsCTR (C) not satisfied)
CLK/TR9 cycle time
CLK/TRG rise time
CLK/TRG fall time
CLK/TRG width (low)
CLK/TRG width (high)
CLK/TRG t to clocl~ t setup time for
immediate count
CLK/TRG t to clock t setup time for
enabling of prescaler on following clock
Clock t to ZC/TO t delay
Clock t to ZC/TO ~ delay
lEI setup time to 10RQ ~ (INT A cycle)
Symbol
TcC
TwCh
TwCl
TfC
TrC
Th
TsCS (C)
TsCE (C)
TsIO (C)
TsRD (C)
TdC (DO)
TdC (DOz)
TsDI (C)
TsMI (C)
t
MIN.
400
170
170
MAX.
(Note 1)
30
30
15
250
200
250
240
240
230
60
210
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
2
TdMI (lEO)
300
ns
3
TdIO (001)
TdIEI (IEOf)
TdlEI (IEOr)
TdC(INT)
340
190
220
TcCt200
ns
ns
ns
ns
2
3
3
4
TdCLK (INT)
TcCt230
ns
5
TdCLK (INT)
2TcCt530
ns
5
5
TcCTR
TrCTR
TfCTR
TwCTRI
TwCTRh
2TcC
200
200
ns
ns
ns
ns
ns
TsCTR (Cs)
300
ns
5
TsCTR (Ct)
210
ns
4
TdC (ZC/TOr)
TdC(ZCITOf)
TsIEI (10)
50
50
260
190
140
ns
ns
ns
t Rising edge, ! Falling edge
IAI 2.5 TcC>(n-2) TdIEI (IEOf)+TdMI (lEO) +TsIEI (IO)+TTL buffer delay, if any:
IBI RESET must be active for minimum of 3 clock cycles
Note1: TcC=TwCh+TwCI+TrC+TfC.
Note 2 : Increase delay by 10 ns for each 50 pF increase in loading, 200 pI" maximum for data lines, and 100 pF for control lines.
Note 3 : Increase delay by 2 ns for each 10 pF increase in loading, 100 pF maximum.
Note 4 : Timer mode.
Note 5 : Counter mode.
All timing are preliminary and subject to change.
*
-~~-'--'---SHARP'-''-----'-~-
310
Z80 CMOS Counter Timer Circuit
AC Test Conditions
• Input voltage amplitude: 0.4 V to 2.S V
• Clock input voltage amplitude: 0.4 V to
Vcc-0.6V
• Input signal rise and fall time: IOns
• Input judge level: O.S V and 2.0 V
• Output judge level: O.S V and 2.0 V
.Output load: ITTL + 100 pF (unless otherwise specified)
•
Power Save Function
The LH50S2L1LH50S2LM has the power save
(PS) function.
(1) PS mode setting
When the CPU (LH50S0LlLH50S0LM) has executed a HALT instruction, the LH5082L/LH5082 LM
LH5082/LH5082L/LH5082LM
reads this HALT instruction to autmatically go into
the PS mode. In this mode, the internal clock
signal is cut off. The external clock may be off duro
ing the PS mode.
About the external clock stop, the same is true as
the power-saving CPU (LH50S0LlLH5080LM).
(2) PS mode clear
The PS mode is cleared by the fall of M1 signal
or the RESET signal.
When the external clock is off the PS mode,
however, a stable clock signal must be input before
clearing the PS mode.
Once cleared from the PS mode, the power-saving CPU (LH5080LlLH50S0LM) comes into the
next fetch cycle. At the time when the first M1 signal during this cycle falls, the LH5082L1LH5082LM
is also cleared from the PS mode.
CLOCK
CLOCK
RESET~
Ml
PS'
RD
. I
Reset state same as LH5082
* PS is an internal signal and not output externally.
Date
PS mode clear by RESET signal
_ _ _ _ _ _ _ _ _..:r Power save
state
* PS is an internal signal and not output externally.
PS mode set timing
CLOCK
Ml
PS'
~
~'----Return to original state
* PS is an internal signal and not output externally.
PS mode clear by MI signal
-----------SHARP-...-...-~-.---.-
311
16-Bit Microprocessor
and Peripheral LSls
ZS001 IZS001 AlZS002/ZS002A Central Processing Unit
LHS001 IS001 A/S002/S002A
LH8001/LH8001A/LH8002/LH8002A
zaoo IIZSOO IAlZSOO2lZS002A. Central Processing Unit
•
. Description
LH800i, Z8001 CPU and LH8002, Z8002 CPU
are advanced 16-bit microprocessor that spans a
wide variety of applications ranging from simple
stand..,alone computers to complexparallel-proces.sing unit. Essentially Z8000 CPU is a monolithic
minicomputer central processing unit.
The LH8001A Z8001A and LH8002A Z8002A
CPU are the high speed version which can operate
at 6MHz system clock.
•
•
Pin Connections
r------:----;::=====::----:L--:H=-SO--:Ol::-:;-=-LH=S=OO=-lA:i
Features
1. Regular, easy-to-use architecture
2. Instruction set more powerful than many minicomputers
3. Directly addresses 8M bytes
4. Eight user-selectable addressing modes
5. Seven data types that ra~ge from bits to 32-bit
l<;mg words and word strings
6. System and Normal operating modes
7. Separate code, data and stack spaces
8. Sophisticated interrupt structure
9. Resource-sharing capabilities 'for multiprocessing
systems
10. Multi-programming support
11. Compiler support
12. Memory management and protection provided
by Z8010 Memory Management Unit
13. 32-bit operations, including signed mUltiply
and divide
14. Z-BUS compatible
Top View
LH8002lS002A
Top View
.-......-.--------SHARP .-..-....----------
314
•
I
I
I
I
I
I
I
,
m
0"
0
'"0
ii"
CQ
;
3
Flags
Address
IData
Address St robe
I
Date Strobe
Memory Request
»
N
Bus Acknowledge
'0
I
I
I
I
I
I
I
....
I
Bus Request
I~
Multi- Micro In
Multi- Micro Out
Non- Maskable Interrupt
Segment
Number
Segment Trap
Non- Vector Interrupt
Vector Interrupt
System Clock
Control
Register
11 36
Vee GND
w
01,
II
Ii
III i
Ii
----.
U1
11111111
I~
I
h
II
II
ZSQ(H IZ8001 A/Z8002/Za002A Central, Processing Unit LH8001 lLH8001 A/LH8002/LH8002A
•
Pin Description
Meaning
Pin
ADo -AD I5
BUSAK
Bus acknowledge
0
RESET
Reset
I
Non-maskable interrupt
I
Vectored interrupt
Non-vectored
Interrupt
Stop
I
I
Active "Low". Requests a non-vectored interrupt.
I
WAIT
Wait
I
Ml
Mo
CLOCK
Multi-micro I
Multi-micro 0
System clock
I
0
I
Active "Low". For single-step instruction execution.
Active "Low". For synchronizing with a peripheral
device.
Active "Low". Forms a resource-request dai&y chain.
Active "Low". Forms a resource-request daisy chain.
Single-phase clock.
0
0
0
0
0
0
0
MREQ
ST o-ST 3
N/S
Address strobe
Data strobe
Read/write
Byte/word
Memory request
Status
Normal/system mode
3-state
3-state
3-state
3-state
3-state
3-state
3-state
SNo-SNs
Segment number
3-state 0
R/W
B/W
SEGT
BUSRQ
---
-NMI
VI
-NVI
STOP
--
Segment trap
I
' Bus request
I
Absolute Maximum Ratings
Parameter
Input voltage
Output voltage
Operating temperature
Storage temperature
"~
3-state
/
MUltiplexed system address and data bus.
Active ~Low". Addresses,are valid.
Active "Low". Data are valid.
Read at "High". Write at "Low".
Byte at "High". Word at "Low".
Active "Low". For memory access.
Specifies CPU status.
Normal mode at "High", System mode at "Low".
Designates segments to be accessed (for 28001 CPU
only).
Active "Low". Detects a segmentation trap from the
28010 MMU.
Active "Low". Requests the bus line.
Active "Low". Indicates the relinquished control of the
bus.
Active "Low", Resets the Z8000 CPU.
Active "Low". High-to-low transition not interrupted
non-maskable.
Active "Low". Requests a vectored interrupt.
AS
DS
•
Addressl data' bus
Function
lIO
Bidirectional
.
316
Symbol
V IN
V OUT
T01>t
- T st •
Ratings
-0.3-+7.0
-0.3-+7.0
0-+70
-65-+150
Unit
V
V
t
t
Z8001 IZ8001 A/Z8002/Z8002A Central Processing Unit LH8001 ILH8001 AlLH8002/LH8002A
.-.-.-~.-.-~.-~~~.-~~~.-~.-
•
(Vcc=5V±5%, Ta=0-+70t)
DC Characteristics
Parameter
Symbol
Clock input high voltage
VCH
Clock input low voltage
VCL
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Current consumption
•
VIH
V IL
VOH
VOL
I IlL I
I IOL I
Icc
MIN.
Conditions
Driven by external clock
oscillator
Driven by external clock
oscillator
MAX.
Vcc-004 Vcc+ 0.3
Unit
V
-0.3
0045
V
2.0,
-0.3
Vcc+ 0.3
0.8
V
V
V
V
204
IOH = -250 fLA
IOL=+2.0mA
Oo4:S::V IN :S::204V
004
10
10
300
Oo4~VouT~204V
fLA
fLA
rnA
AC Characteristics
Number
Symbol
1
2
3
4
5
TcC
TwCh
TwCI
TfC
TrC
6
TdC (SNv)
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
,30
31
32
33
34
35
TdC (SNn)
TdC (Bz)
TdC (A)
TdC (Az)
TdA (DR)
TsDI (C)
TdDS (A)
TdC(DW)
ThDR (DS)
TdDW (DS)
TdA (MR)
TdC (MR)
TwMRh
TdMR (A)
TdDW (DSW)
TdMR (DR)
TdC (MR)
TdC (ASf)
TdA (AS)
TdC (ASr)
TdAS (DR)
TdDS (AS)
TwAS
TdAS (A)
TdAz (DSR)
TdAS (DSR)
TdDSR (DR)
TdC (DSr)
TdDS (DW)
Parameter
Clock cycle time
Clock width (high)
Clock width (low)
Clock fall time
Clock rise time
Clock t to segment number valid
(50 pF load)
Clock t to segment number not valid
Clock t to bus float
Clock t to address valid
Clock t to address float
Address valid to read data required valid
Read data to clock ! setup time
DS t to address active
Clock t to write data valid
Read data to DS t hold time
Write data valid to DS t delay
Address valid to MREQ ! delay
Clock ! to MREQ ! delay
MREQ width (high)
MREQ ! to address not active
Write data valid to DS ! (write) delay
MREQ ! to read data required valid
Clock ! MREQ t delay
Clock t to AS ! delay
Address valid to AS t delay
Clock ! to AS t delay
AS t to read data required valid
DS t to AS ! delay
AS width (low)
AS t to address not active delay
Address float to DS (read) ! delay
AS t to DS (read) ! delay
DS (read) ! to read data required valid
Clock ! to DS t delay
DS t to write data not valid
'-'--~----SHARP
LH800JlLH8002(4MHz)
MIN.
MAX.
250
2000
105
2000
105
2000
20
20
LH800IA/LH8002A(6MHz)
MIN.
MAX.
165
2000
70
2000
2000
70
10
15
130
20
110
10
65
100
65
475*
30
80*
55
75
55
305
20
45*
100
75
0
195*
35*
0
295*
55*
80
210*
70*
55*
375*
70
135*
35*
35*
230*
80
80
60
60
35*
55*
90
80
220*
35*
55*
45'*
0
55*
130*
360*
70*
85*
70* ,
0
80*
205*
70
75*
65
45
Unit
ns
ns
ns'
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
----.----..----
317
-----------------Z8001 IZ8001 A/Z8002/Z80Q2A Central Processing, Unit LH8001lLH8001 A/LH8002/LH8002A
Number
Symb01
36
37
38
39
40
41
42
43
44
45
TdA (DSR)
TdC (DSR)
TwDSR
TdC (DSW)
TwDSW
TdDSI (OI)
TdC(DSf)
TwDS
TdAS (DSA)
TdC (DSA)
46
TdDSA (DR)
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
TdC (S)
TdS (AS)
TsR (C)
ThR (C)
TwNMI
TsNMI (C)
TsVI (C)
ThVI (C)
TsSGT (C)
ThSGT (C)
TsMI (C)
ThMI (C)
TdC (MO)
TsSTP (C)
ThSTP (C)
TsW (C)
ThW (C)
TsBRQ (C)
ThBRQ (C)
TdC (BAKr)
TdC (BAKi)
TwA
TdDS (S)
Note:
Parameter
Address valid to DS (read) l delay
Clock t to DS (read) l delay
DS (read) width (low)
Clock l to DS (write) l delay
DS (write) width (low)
DS (liD)
to read data required valid
Clock l to DS (II 0) l delay
DS (II 0) width (low)
AS t to DS (acknowledge) l delay
Clock t to DS (acknowledge) l delay
DS (acknowledge) l to read data
required delay
Clock t to status valid delay
Status valid to AS t delay
RESET to clock t setup time
RESET to clock t hold time
NMI width (low)
NMI to clock t setup time
VI, NVI to clock t setup time
VI, NVI to clock t hold time
SEGT to clock t setup time
SEGT to clock t hold time
MI to clock t setup time
MI to clock t hold time
Clock t to MO delay
STOP to clock l setup time
STOP to clock l. hold time
WAIT to clock l setup time
WAIT to clock l hold time
BUSREQ to clock t setup time
BUSREQ to clock t hold time
Clock t to BUSACK t delay
Clock t to BUSACK l delay
Address valid width
DS t to STATUS not valid
r
LH800IA/LH8002A(6MHz)
MIN.
MAX.
110*
180*
12,0
275* '
85
185*
95
80
110*
210*
185*
330*
120
410*
1065*
90
255*
690*
120
85
295*
455*
110
50*
180
0
100
140
110
20
70
0
180
0
85
120
85
100
0
30
10
80
10
100
100
150*
80*
75
75
95*
55*
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30*
70
0
70
70
50
20
55
0'
140
0
140
0
50
10
90
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
'ns
ns
ns
ns
t Rising, ! Falling, ( I) 2TcC + TwCh - 130ns
* Clock-cycle-time-dependent characteristics.
------~~----SHARP
318
LH800IlLH8002(4MHz)
MIN:
MAX.
-.--...-.---------
Z8001 IZ8001 AlZ8002/Z8002A Central Processing Unit LH8001 ILH8001 A/LH8002/LH8002A
.-..-.----.-..-.~.-.------.-.~--.-..-.--.-.
•
Composite AC Timing Diagram
RESET
--~X~~~~~')50~
______________,. ~4~ r-'~
~
NMI
:>i
VI,NVI
-
K53)a 1i54
SEGT
=
This composite timing diagram
does not show actual timing sequences.
Refer to this diagram only for the detailed
timing relationships of individual edges.
Use the preceding illustrations as an
explanation of the various timing sequences.
~. ~
BUSRQ
~.
BUSAK __________~JI--~
CLOCK
)
WkiJr---\"'------'.
,-
V7\
~~~~
SNo-SN6
I'
~
r----. I
.J~. ~
____~rGr,9~~--~~~~
ADDRESS
----+-.r;><1:=t====1=~~
J
{
A",-AD"
DATA IN
.
IE-I
DATA OUT
:i~--
~~
~
~f~
'='
"'f--®- 'l
:> I@ f ~~_)
:""~f--~ ~ .J--t------t---+--+,j--+"'""'K...lr"--
I_~
MREQ
L
II.rg\.
f'-----J I'V-
~
~
,-
~
lfijO)\
-=.
'C/
~@1'r-tk--+-+.(J
I",,......,H-+-tl'==t---+----t-........ lt"l
t@;r-;-.o--t+-t--t{I~.zm-_ _-i
--~--+-l~ ~v~ ~-o ~IE-t-L""-f{I~33}---I' ~ ~
AS
MEMORY
./
READ
--
1-
N.,
I='
I~~,~~~+=+=~;+==::l
'\I!!!
IQI
~
MEMORY
~
WRITE
-'
DS
INPUT /
OUTPUT
~
',v
;g ~f@-l
"""J<-+_--~+_+_--+-_, ~
~
-'
INTERRUP~
T --j
f-~I
f-@-'4 -.IM'!I...."
~
~Y'
.J--_
~/"I .... - - -...
.~m
~
-@-
.JI' .. ~
. J . r-_
r.---
ACKNOWLEDGE
-"!!:J.'-1(!:;lI-1
..
...---}
STo-STg
READ/WRIfE---....
)<
NORMAL/SYSTEM
~------------------------------~I
BYTE/WORD
-~'-'--'-'--SHARP---'-'--~-"--"'"
319
Z8001 IZ8001 AlZ80021Z8002A Central' Processing Unit LH8001 ILH8001 AlLH8002/LH8002A
•
Register Organization
The 28000 CPU is a register-oriented machine
that offers sixteen 16-bit general-purpose registers and a set of special system registers.
(1) General-purpose register
All general-purpose registers can be used as
but" one as index registers or
accumulators and all
../
memory pointers.
Register flexibility is created by grouping and
overlapping multiple registers (Fig. 1 and 2). For
byte operations, the first eight 16-bit registers
(RO ... R7) are treated a~ sixteen 8-bit registers
(RLO, RHO, ..., RL7, RH7). The sixteen 16-bit reg~
isters are grouped in pairs (RRO ... RR14) to form
32-bit long-word registers. Similarly, the register
set is grouped in quadruples (RQO ... RQ12) to
form 64-bit registers.
(2) Specific -purpose register
The 28000 CUP has the following specific-purpose registers.
• Refresh counter
•
Program status register
•
Program status area pointer
The refresh counter can be used to automatically
refresh dynamic memory. The refresh counter register consists of a 9-bit row counter, a 6-bit rate
RRO{
RR2{
RR4{
RR6{
RRS{
Ro~17====R=H=0===0*!=7==R=L=0==~0
I
RHI
i
RHO
Rol7
RROf
RR2,
RR4{
RR6{
{
RR8
RRIO
=~I
RHl
RH2
R31
RH3
R41
RH4
R51
RH5
R61
RH6
R71
RH7
01 }
I
RL2
RQO
"" RL3
i
I
}R~
RIA
RL5
I
RL6
!
RL7
{ RIOI
Rlli
}R~
RR12{ RI21
.
Rl3
{ R141
RR14 Rl5
R15
RQl2
SYSTEM STACK POINTER
NORMAL STACK POINTER
Fig. 2 Z8002 general-purpose register
I
ROW
9 S
I
I
I
I
I
I
o
I
Fig. 3 Refresh counter
counter and an enable bit (Fig. 3).
This group of status registers contains the program counter, flags and control words. When an interrupt or trap occurs, the entire" group is saved
"and a new program status group is loaded.
Fig. 4 illustrates how the program status groups
.of the 28001 and 28002 differ.
RRIO{RIO :=1= = = = = = = = = = = 9
Rll~l.=======~
RR12{ ::: ==============:
:=1
Fig. 1 Z8001 general-purpose register
II
RLl
0
RATE
=:~I==================~
R14'
SYSTEM STACK POINTER (SEG.NO.)
R14
NORMAL
STACK POINTER (SEG.NO.)
RRl4 {
"
R15'
SYSTEM STACK POINTER (OFFSET)
Rl5 NORMAL STACK POINTER (OFFSET)
RLO
RsI15
R91
RLl
R2~1==~R=H=2==~!===R=L=2==~
R3~L====R=H=3==~i==~R~L~3==~
R4~1====R=H=4===*i===§RL~4~==9
R5~1==~R=H=5==ii==RL=5==~
R6~1====R=H~6===\~I==~R§L~6==~
R7~1====R=H=7==~===R=L=7==~
01 7
RQI2
Z8001 IZ8001 AlZ8002/Z8002A Central Processing Unit LH8001 ILH8001 AlLH8002/LH8002A
Z8001 Program Status R-egisters
~
0
I0 ISfGIj'Ef 1 CRC" CRC,jFLAGI
Fig. 2 An SDLC loop
SDLC/HDLC/X.25 "INFORMATION
Fig. 1 Some Z-SCC protocols
•
SOLe Loop Mode
The Z-SCC supports SDLC Loop mode in addition to normal SDLC. In an SDLC Loop, there is a
primary controller station that manages the message traffic flow on the loop and any number of
secondary stations. In SDLC Loop mode, the Z-SCC
performs the functions of a secondary station while
a Z-SCC operating in regular SDLC mode can act
as a controller (Fig. 2).
A secondary station in an SDLC Loop is always
listening to the messages being sent around the
loop, and in fact must pass these messages to the
rest of the loop by retransmitting them with a
one-bit-time delay. The secondary station can
place its own message on the loop only at specific
times. The con,troller signals that .secondary stations may transmit messages by sending a special character, called an EOP (End Of Poll), around the loop.
The EOP character is the bit pattern 1111111 0.
Because of zero insertion during messages, this bit
pattern is unique and easily recognized.
When a secondary station has a message to
transmit and recognizes an EOP on the line, it
chages the last binary 1 of the EOP to a 0 before
transmission. This has the effect of turning the
EOP into a flag sequence. The secondary station
now places its message on the loop and terminates
the message with an EOP. Any secondary stations
further down the loop with messages to transmit
can then append thier messages to the message of
'the first secondary station by the same process.
350
•. Data Encoding
The Z-SCC may be programmed to encode and
decode the serial data in four different ways (Fig.
3). In NRZ encoding, a 1 is represented by a High
level and a 0 is represented by a Low level. In
NRZI encoding, a 1 is represented by no change in
level and a 0 is represented by a change in level. In
FM1 (more properly, bi-phase mark) a transition
occurs at the beginning of every bit cell. A 1 is represented by an additional translation at the center
of the bit cell and a 0 is represented by no additional transition at the center of the bit cell. FMO
(bi-phase space), a transition occurs at the beginning of every bit cell. A 0 is represented by an
additional transition at the center of the bit cell,
and a 1 is represented by no additional transition
at the center of the bit cell. In addition to these four
methods, the Z-SCC can be used to decode Manchester (bi-phase level). data by using the DPLL in
the FM mode and programming the receiver for
NRZ d~ta. Manchester encoding always produces a
transition at the center of the bit cell. If the transition is 0 to 1, the bit is a O. If the transition is 1 to '
0, the bit is a 1.
DATA --''--_-''-,
NRZ
NRZI
FMl
FM
MANCHESTER
Fig. 3
Data encoding methods
Z8030/Z8030A Serial Communications Controller
•
Auto Echo and Local Loopback
The Z-SCC is capable of automatically echoing
everything it receives. This feature is useful mainly in Asynchronous modes, but works in Synchronous and SDLC modes as well. In Auto Echo mode,
TxD is RxD. Auto Echo mode can be used with
NRZI or FM encoding with no additional delay, because the data stream is not decoded before retransmission. In Auto Echo mode, the CTS input is
ignored as a transmitter. enable (although transitions on this input can still cause interrupts if
programmed to do so). In this mode, the transmitter
is actually bypassed and the programmer is responsible for disabling transmitter interrupts and
WAIT /REQUEST on transmit.
The Z-SCC is also capable of Local Loopback . In
this mode TxD is RxD, just as in Auto Echo mode.
However, in Local Loopback mode, the internal
data is tied to the internal receive data and RxD is
ignored (except to be echoed out via TxD). The CTS
and DCD inputs are also ignored as transmit and
receive enables. However, transitions on these inputs can still cause interrupts. Local Loopback
works in Asynchronous, Synchronous and SDLC
modes with NRZ, NRZI or FM coding of the data
stream.
•
Baud Rate Generator
Each channel in the Z-SCC contains a programmable band rate generator. Each generator consists
of two 8-bit time constant registers that form a
16-bit time constant, a 16-bit down counter, and a
flip-flop on the output producing a square wave.
On startup, the flip-flop on the output is set in a
High state, the value in the time constant register is
loaded into the counter, and the counter starts
counting down. The output of the baud rate generator toggles upon reaching 0, the value in the time
constant register is loaded into the counter, and the
process is repeated. The time constant may be
changed at any time, but the new value does not
take effect until the next load of the counter.
The output of the baud rate generator may be
LH8030/LH8030A
used as either the transmit clock, the recieve clock,
or both. It can also drive the Digital Phase-Locked
Loop (see next section).
If the receive clock or transmit clock is not programmed to come from the TRxC pin, the output of
the baud rate generator may be echoed out via the
TRxC pin.
The following formula relates the time constant
to the baud rate (the baud rate is in bits/second
and the BR clock period is in seconds) :
1
baud rate
•
= 2 (time constant + 2) X (BR clock period)
Digital Phase-Locked Loop
The Z-SCC contains a Digital Phase-Locked
Loop (DPLL) to recover clock information from a
data stream with NRZI or FM encodling. The DPLL
is driven by a clock that is nominally 32 (NRZI) or
16 (FM) times the data rate. The DPLL uses this
clock, along with the data stream, to construct a
clock for the data. This clock may then be used as
the Z-SCC receive clock, the transmit clock, or
both.
For NRZI encoding, the DPLL counts the 32x
clock to create nominal bit times. As the 32x clock
is counted, the DPLL is searching the incoming
data stream for edges (either 1 to 0 or 0 to 1).
Whenever an edge is detected, the DPLL makes a
count adjustment (during the next counting cycle),
producing a terminal count closer to the center of
the bit cell.
For FM encoding, the DPLL still counts from 0
to 31, but with a cycle corresponding to two bit
times. When the DPLL is locked, the clock edges in
. the data stream should occur between counts 15
and 16 and between counts 31 and O. The DPLL
looks for edges only during a time centered on the
15 to 16 counting transition.
The 32x clock for the DPLL can be programmed
to come from either the RTxC input or the output of.
the baud rate generator. The DPLL output may be
programmed to be echoed out of the Z-SCC via the
TRxC pin (if this pin is not being used as an input).
------------SHARP---.-----351
Z803QJZ8030A Serial Communications Controller
•
LH8030/LH8030A
Read Registers
Read Register 10 .
Read Register 0 .
~~~-r~~-r~~'-~~RxCHARACTER
AVAILABLE
ZERO COUNT
Tx BUFFER EMPTY
DCD
SYNC/HUNT
CTS
Tx UNDERRUN /EOM·
BREAK/ABORT
Read Register 1
o
LOOP SENDING
o
TWO CLOCKS MISSING
ONE CLOCK MISSING
Read Register 12
I D7 I D6 I Ds I D. I D3 I D, I DJ I Do
ALL SENT
RESIDUE CODE 2
RESIDUE CODE 1
RESIDUE CODE 0
PARITY ERROR
Rx OVERRUN ERROR
CRC/FRAMING ERROR
END OF FRAME (SDLC)
Read Register 2
I~I~I~I~I~I~I~I~I
[INTERRUPT VECTOR'
• MODIFIED IN B CHANNEL
Read Register 3*
o
o
CHANNEL B
EXT/STAT IP'
CHANNEL B Tx IP'
CHANNEL B Rx II"
CHANNEL A EXT/STAT IP'
CHANNEL A Tx IP'
CHANNEL A Rx IP'
[
I
LOWER BYTE OF
TIME CONSTANT
Read Register 13
1~lllilllil~I~I~I~I~1
[UPPER BYTE OF
TIME CONSTANT
Read Register 15
o
o
DCDIE
SYNC/HUNT IE
CTS IE
Tx UNDER RUN / EOM IE
BREAK/ABORT IE
• ALWAYS 0 IN B CHANNEL
'-'---~---SHARP-'------'---
352
Z8030/Z8030A Serial Communications Controller
•
LH8030/LH8030A
Write Register 2
Write Registers
Write Register 0
1071 061 051 0./ 03/ 02/ 01/ Do /
1I
NULL CODE
NULL CODE
SELECT SHIrr LEFT MODE'
SELECT SHIFT RIGHT MODE'
0
0
0
1
1
0
1
1
~--------------Vs
~--------------------V7
NULL CODE
NULL CODE
RESET EX T/STATUS INTERRUPTS
SEND ABO RT
ENABLE IN T ON NEXT Rx CHARACTER
RESET Tx I NT PENDING
ERROR RES ET
Write Register 3
RESET HIG HEST IUS
0
1
0
1
0
1
0
1
NULL CODE
RESET Rx CRC CHECKE R
RESET Tx CRC GENERA TOR
RESET Tx UNDERRUN / EOM LATCH
I I
/ 071 061 051 04/ 031 02 / 01 Do
II~
'B CHANNEL ONLY
0
0
1
1
0
1
0
1
Rx
Rx
Rx
Rx
I 07 I061 051 0.1 031 021 01 I Do I
~
1
1
0
1
0
1
5
7
6
8
Rx ENABLE
SYNC CHARACTER LOAD INHIBIT
ADDRESS SEARCH MODE (SDLC) ~
Rx CRC HUNT
ENABLE
ENTER
MODE
AUTO ENABLE
BITS /CHARACTER
BITS /CHARACTER
BITS /CHARACTER
BITS /CHARACTER
Write Register 4
Write Register 1
0
0
INTERRUPT
VECTOR
~------------------V6
o
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
~~~
I
I 071 061 051 04/ 03/ 021 01 I Do I
1I
EXT INT ENABLE
Tx INT ENABLE
PARITY IS SPECIAL
CONDITION
0
0
1
1
Rx INT DISA BLE
Rx INT ON FI RST CHARACTER
OR SPECIAL CONDITION
INT ON ALL Rx CHARACTERS
OR SPECIAL CONDITION
Rx INT ON SPE CIAL CONDITION ONLY
WAIT /0 MA REQUEST ON
RECEI VE/TRANSMIT
WAIT /0 MA REQUEST
FUNCT ION
WAIT /0 MA REQUEST
ENABLE
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
ENABLE
~PARITY
PARITY EVEN/ODD
SYNC MODES ENABLE
1 STOP BIT/CHARACTER
1112 STO P BITS/CHARACTER
2 STOP BITS/CHARACTER
8 BIT SYNC CH ARACTER
16 BIT SYNC C HARACTER
SDLC MODE (01 111110 FLAG)
EXTERNAL SY NC MODE
xl CLOCK MODE
x16 CLOCK MODE
x32 CLOCK MODE
x64 CLOCK MODE
. . . . - . - - - - - - - - - - - - S H A R P ...--~--.-------
353
5
===_"
..........
.......................... ..........................
Z8030/Z8030A Serial Communications Controller
~~
.
- LH8030lLH8030A
~....,
~
.
~
Write Register 5
I D71 Dsl Ds I D.I D31 D2 I Dl I Do I
I~
0
0
0
1
1
0
1
1
Tx
Tx
Tx
Tx
Tx CRC ENABLE
RTS
SDLC/CRC 16
Ti ENABLE
SEND BREAK
5 BITS (OR LESS )/CHARACTER
7 BITS/CHARAC TER
6 BITS /CHARAC TER
8 BITS /CHARAC TER
DTR
Wrl!e Register 6
I D7! Dsl Dsl D.I D31 D21 Dl I Dol
SYNC7
SYNCl
SYNC7
SYNC3
ADR7
ADR7
FFJ~~~
SYNCs
SYNCs
SNNCs
SYNC2
ADRs
ADRs
SYNCs
SYNCs
SYNCs
SYNCl
ADRs
ADRs
SYNC.
SYNC.
SYNC.
SYNCo
ADR.
ADR.
SYNC3
SYNC3
SYNC3
1
ADR3
x
SYNC2
SYNC2
SYNC2
1
ADR2
x
SYNCl
SYNCl
SYNCl
1
ADRl
x
SYNCo
S'yNCo
SYNCo
1
ADRo
x
MONOSYNC, 8 BITS
MONOSYNC, 6 BITS
BISYNC, 16 BITS
BISYNC, 12 BITS
SDLC ADDRESS, 8 BITS
SDLC ADDRESS, 4 BITS
Write Register 7
ID71 Dsl Dsl D.I D31 D21 Dl I Do I
SYNC7
SYNCs
SYNCls
SYNCll
0
354
F,J~~~
I
SYNCs
SYNC.
SYNC14
SYNClO
SYNCs
SYNC3
SYNCls
SYNCg
SYNC.
SYNC2
SYNCl2
SYNCs
SYNC3
SYNCl
SYNCll
SYNC7
SYNC2
SYNCo
SYNClo
SYNCs
SYNCl
SYNCo
X
X
SYNCg
SYNCs
SYNCs
SYNC.
1
1
1
1
1
1
o
MONOSYNC, 8 BITS
MONOSYNC, 6 BITS
BISYNC, 16 BITS
BISYNC, 12 BITS
SDLC,FLAG
Z8030/Z8030A Serial Communications Controller
LH8030/LH8030A
Write Register 12
Write Register 9
I D71 D61 D51 D41 D31 D21 D, I Dol
I~
0
0
1
1
0
1
0
1
VIS
NV
DLC
MIE
STATUS HIGH/STATUS LOW
I
LOWER
BYTE OF
TC4 TIME
L---------------TC5 CONSTANT
L-_________________ TC6
o
NO RESET
CHANNEL RESET B
CHANNEL RESET A
FORCE HARDWARE RE SET
I I LL=~TgCC:3'
L---------------------TC7
Write Register 13
I D71 D61 D51 D41 D31 D21
D,
Write Register 10
II II
I D71 D61 D51 D41 D31 D21 DI I Dol
I~
0
0
1
1
0
1
0
1
6 BIT /8 BIT SYNC
LOOP MODE
ABORT/ FLAG ON UNDERRUN
MARK/FLAG-IDLE
GO ACTIVE ON POLL
NRZ
NRZI
FMI (TRANSITION =1)
FMO (TRANSITION =0)
Write Register 14
ID71 D61 D51 D41 D31 D21 D, I Do I
I~
Write Register 11
I]
TIUC OUT=XTAL OUTPUT
TIUC OUT=TRANSMIT CLOCK
TIUC OUT=GTGENERATOR OUTPUT
TIUC OUT= DPLL OUTPUT
TRxC 0/1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TRANSMIT
TRANSMIT
TRANSMIT
TRANSMIT
RECEIVE
RECEIVE
RECEIVE
RECEIVE
CL OCK=RTxC PIN
CL OCK=TRxC PIN
CL OCK= BR GENERATOR OUTPUT
CL OCK=DPLL OUTPUT
CLOCK = RTxC PIN
CLOCK = TRxC PIN
CLOCK = BR GENERATOR OUTPUT
CLOCK = DPLL OUTPUT
RTxC XTAL/NO XTAL
Lm ~~~~"oF
TC'2 TIME
L--------------TC 13 CONSTANT
'------------------- TC 14
'---------------------- TC 15
CRC PRESET I/O
ID71 D6 ID51 D41 D3 ID21 D, IDo I
I Dol
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
BR GENERATOR ENABLE
BR GENERATOR SOURCE
DTR/REQUEST FUNCTION
AUTO ECHOLOCAL LOOPBACK
NULL COMMAND
ENTER SEARCH MODE
RESET MISSING C LOCK
DISABLE DPLL
SET SOURCE=BR GENERATOR
SET SOURCE = --C
RTx
SET FM MODE
SET NRZI MODE
Write Register 15
ID71 D6[ D5[ D4[ D3[ D2[ D, [ Do [
I I ~:ERO COUNT IE
~DCDIE
SYNC!HUNT IE
'----------------CTS IE
' - - - - - - - - - - - - - - Tx UNDERRUN/EOM IE
L--------'-----BREAK/ABORT IE
.--..-------SHARP---------
355
Z8036/Z8036ACounter/Timer and Parallel 1/0 Unit
LH8036/LH8036A
LH8036/lH8036A
-Z8036/Z8036A Counter/Timer and Parallel I/O Unit
•
Description
The Z8036 Z-CIO Counter/Timer ~nd Parallel
. 110 elemeniis ,a general-purpose peripheral circuit, satisfying most counter/timer and parallel 110
needs encountered in system designs. This versatile device contains three 110 ports and three counter/timers. Many progra\llmable options tailor its
configuration to specific applications. The use of
the device is simplified by making all internal registers (command, status, and data) readable and'
(except for status bits) writable. In addition, each
'register is given its own unique address so that it
can be accessed directly-no special sequential operations are required. The Z-CIO is directly
Z-Bus compatible.
•
•
Pin Connections
o
' Features
1. Two independent 8-bit, double-buffered,
bidirectional 110 ports plus a 4-bit speci,dpurpose 110, port. 110 ports feature programmable polarity, programmable direction
(Bit mode), "pulse catchers," and programmable opendrain outputs
2. Four handshake modes, including 3-Wire (like
.
the IEEE-488)
3. REQUEST /W AIT signal for high-speed data
transfer
4. Flexible pattern-recognition logic, programmable as a 16-vector interrupt controller
5. Three independent 16-bit counter/timers with
up to four external access lines per counter/
timer (count input, output, gate, and trigger),
and three output duty cycles (pulsed, one-shot,
and s'quarewave), programmable as retriggerable or nonretriggerable.
6. Easy to use since all registers are read/write
and directly addressable.
356
Top View
Z8036/Z8036A Counter/Timer and Parallel I/O Uni.t
•
LH8036/LH8036A
Block Diagram
Interrupt Enable In
Int erupt Enabl e Out
Interrupt Request C24l--f
Interrupt Acknowledge
Address/Data
Bus
Data Strobe
Read/Write
Address Strobe 3
Chip Select {
•
Pin Description
Pin
AD o-AD 7
AS
-
DS
Meaning
Address/ data bus
Address strobe
I/O
Bidirectional
3-state
I
Data strobe
I
R/W
Read/write
I
CSo
CS 1
Chip select 0
Chip select 1
I
I
-
-INT
Interrupt request
Open-drain
Interrupt acknowledge
I
lEI
Interrupt enable in
I
lEO
Interrupt enable out
0
INTACK
PAo-PA 7
Port A I/O lines
PBo-PB 7
Port B I/O lines
PC O-PC 3
Port C I/O lines
PCLK
Clock
Bidirectional
3-state
Bidirectional
3-state
Bidirectional
3-state
I
Function
MUltiplexed system address/data bus.
Active low. AS determines address while low.
Active low. DS providies timing for data transfer
while low.
R/W indicates that the CPU is reading froln (high) or
writing to (low) the Z-CIO.
Active low. Chip select signal
Active high. Chip select signal
Active low. INT is pulled low when the Z·CIO
requests on interrupt.
Active low. INT ACK indicates that an Interrupt
acknowledge cycle is in progress.
Acvtive high. lEI is used to form an interrupt daisy
chain that determines the priority order of interrupts.
Active high. lEO is used to form an interrupt daisy
chain that determines the priority order of interrupts.
These eight I/O lines transfer information between the
Z·CIO's port A and external devices.
These eight I/O lines transfer information between the
Z-CIO's port B and external devices.
These four I/O lines transfer information between the ZCIO's port C and external devices.
Single-phase clock, need not be same as CPU clock.
Note: When AS and DS are detected "Low" at the same time, the Z-CIO is reset.
-.-------SHARP--------~-357
---___....._. . . ,. . . . . . . . .
. . ......,------.----
za036/Z8036A CQunter/Timer and Parallel. 1/0 Unit
LH8036/LH8036A
~~-,..-I':-
•
Absolute Maximum Ratings
Parameter
Input voltage
Output voltage
Operating temperature
Storage temperature
Note. 1:
Symbol
VIN
VOUT
Ratings
-0.3-+7.0
-0.3-+7.0
0-+70
-65-+150
T=
Tilic
Unit
V
V
"C
"C
Note
1
1
The maximum applicable voltage on any pin with respect to GND.
+5V
From output under test
+5V
1R
I
.
~'2kO
. ,
From output under test
I 25
50pF
~A
lSOPF
Standard test load
•
Open drain test load
(V cc =5V±5%, Ta=0-+70"C)
DC Characteristics
Parameter
Input high voltage
Input low voltage
Output high voltage
Symbol
VIH
VIL
VOH
Output low voltage
VOL
Input leakage current
Output leakage current
Supply current
.!
I IlL I
I IOL I
Conditions
,
IoH =-250,uA
IOL=+2.0mA
IOL=+3.2mA
0.4";;:V IN ";;:2.4V
0.4 ~VouT~2.4V
MAX.
Vcc+ 0.3
0.8
0.4
0.5
10.0
10.0
250
Unit
V
V
V
V
V
,uA
,uA
mA
(f=lMHz, Ta=0-+70"C)
Symbol
CIN
CO\!L
CliO
Conditions
Unmeasured pins
returned to ground
....-..-..-.-~-.-.--SHARP
358
MIN.
2.0
-0.3
2.4
Icc
Capacitance
Parameter
Input capacitance
Output capacitance'
Bidirectional capacitance
i
T.2kO
MIN.
MAX.
10.
15
20
Unit
pF
pF
pF
-..-.-..--------
Z8036/Z8036A Counter/Timer and Parallel I/O Unit
•
Ui8036/LH8036A
AC Characteristics
(1)
Interface timing
No.
Symbol
Parameter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
TwAS
TsA (AS)
ThA (AS)
TsA (OS)
TsCSO (AS)
ThCSO (AS)
TdAS (OS)
TsCSI (OS)
TsRWR (OS)
TsRWW (OS)
TwOS
TsOW (OSf)
TdOS (ORV)
TdOSf (OR)
ThOW (OS)
TdOSr (OR)
TdOS (ORz)
ThRW (OS)
ThCSI (OS)
TdOS (AS)
Trc
22
TdPM (INT)
AS low width
Address to AS f setup time
Address to AS f hold time
Address to OS ! setup time
CS o to AS f setup time
CS o to AS f hold time
AS f to OS ! delay
CS 1 to OS ! setup time
R/W (read) to OS ! setup time
R/W (write) to OS ! setup time
OS low width
Write data to OS ! setup time
OS (read) ! to address data bus driven
OS ! to read data valid delay
Write data to DS f hold time
OS f to read data not valid delay
OS f to read data float delay
R/W to OS f hold time
CS 1 to OS f hold time
OS f to AS ! delay
Valid access recovery time
Pattern match to INT delay (bit port)
23
TdACK (INT)
24
TdCI (INT)
25
TdPC (INT)
PCLK to INT delay (Timer mode)
26
27
28
29
TdAS (I NT)
TsIA (AS)
ThIA (AS)
TsAS (OSA)
30
TdOSA (OR)
31
32
33
34
35
36
TwOSA
TdAS (lEO)
TdlEI (lEO)
TslEI (OSA)
ThlEI (OSA)
TdOSA (INT)
AS to INT delay
INT ACK to AS f setup time
INT ACK to AS f hold time
AS f to OS (acknowledge) ! setup time
OS (acknowledge) ! to read data
valid delay
OS (acknowledge) low width
AS f to lEO ! delay (INT ACK cycle)
lEI to lEO delay
lEO to OS (acknowledge) ! setup time
lEI to OS (acknowledge) t hold time
OS (acknowledge) ! to INT t delay
LH8036
MIN.
MAX.
70
2000
30
50
130
0
60
60
100
100
0
390
30
0
250
30
0
70
55
55
50
1000
ACKIN to INT delay
(Port with handshake)
Counter input to INT delay
(Counter mode)
-
LH8036A
MIN.
MAX.
50
2000
10
30
100
0
40
40
80
80
0
250
20
0
180
20
0
45
40
40
25
650
1
1
4
4
1
1
1
1
0
250
350
0
250
250
250
390
180
250
250
100
350
150
100
100
70
70
600
600
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
1
1
1
1
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
lAs cycle
+ns
lAS cycle
+ns
lAs cycle
+ns
lAs cycle
+ns
ns
ns
ns
ns
2
3
4
5
ns
ns
ns
ns
ns
ns
ns
5
5
5
Note: • t " indicates a rising edge -and •. ! .. a falling edge.
Note 1: Parameter does not apply to Interrupt Acknowledge transactions.
Nate 2: Float delay is measured to the time when the output has changed 0.5 V from steady state with minimum ac load and maximum de
load.
Note 3: This is the delay from DS t of one CIa access to DS ! of another CIa access.
Note 4: The delay is from DAV ! for 3-Wire Input Handshake. The delay is from DAC t for 3-Wire Output Handshake. One additional
AS cycle is required for ports in the Single Buffered mode.
Note 5: The parameters for the devices in any particular daisy chain must meet the following constraint: the delay from AS t to DS !
must be greater than the sum of TdAS (lEO) for the highest priority peripheral, TsIEI (DSA) for the lowest priority peripheral, and
TdlEI (lEO) for each peripheral separating them in the chain.
359
Z8036/Z8036A Counter I Timer and Parallel 1/0 'Unit
LH8036lLH8036A
AS
R/W
Read
R/W
Write
-----++----4l'..,.-t------t-'-------
DS
Address
ADo - AD7
Z-CIO Write
\. Z-CIO Read
CPI,J interface timing
P~ttern
Blt~rt
match input
~
input
_ _ _ _match
___
_ _ _ _ _ _ _ _ _ _ _ _ _ _ __
~~
r:==-@--
----'----.
Counter input
PCLK
INT
Interrupt timing
360
Z8036/Z8036A Counter/Timer and Parallel 110 Unit
___
LH8036/LH8036A
---'XUndefined)>-----@-~
Vector)
lEI
lEO
Interrupt acknowledge timing
(2)
Handshake timing
No.
Symbol
Parameter
1
TsDI (ACK)
2
ThDi (ACK)
3
4
5
6
7
8
9
10
TdACKf(RFD)
TwACKI
TwACKh
TdRFDr(ACK)
TsDO (DAV)
TdDA Vf (ACK)
ThDO (ACK)
TdACK (DAV)
11
ThDi (RFD)
12
TdRFDf(ACK)
13
TdACKr(RFD)
14
TdDAVr (ACK)
15
TdACK (DAV)
16
TdDA Vif (DAC)
17
ThDi (DAC)
18
TdDACOr(DA V)
19
TdDA VIr (DAC)
Data input to ACKIN ~ setup time
Data input to ACKIN ~ hold
time-strobed handshake
ACKIN ~ to RFD ~ delay
ACKIN low width-strobed handshake
AGKIN high width-strobed handshake
RFD t to ACKIN ~ delay
Data out to DA V ~ setup time
DA V ~ to ACKIN ~ delay
Data out to ACKIN ~ hold time
ACKIN ~ to DA V t delay
Data input to RFD ~ hold
time-interlocked handshake
RFD ~ to ACKIN t
delay-interlocked handshake
ACKIN t (DAV t) to RFD t
delay-interlocked and 3-wire handshake
DA V t to ACKIN t (RFD t)
delay-interlocked and 3-wire handshake
ACKIN t (RFD t) to DAV ~
delay-interlocked and 3-wire handshake
DAV ~ to DACt
delay-input 3-wire handshake
Data input to DAC t hold
time-3-wire handshake
DAC t to DAV t
delay-input 3-wire handshake
DAV t to DAC ~
delay-input 3-wire handshake
LH8036
MIN.
MAX.
0
LH8036A
MIN.
MAX.
0
Unit
Note
ns
ns
0
0
0
25
0
1
1
0
20
0
1
1
ns
ns
ns
ns
ns
ns
AS cycle
[As cycle
0
0
ns
0
0
ns
0
0
ns
0
0
ns
0
0
ns
0
0
ns
0
0
ns
0
0
ns
0
0
ns
1
361
Z8036/Z8036A Counter/Timer and Parallel I/O Unit
No.
SymboL
LH8036/LH8036A
LH8036
MIN.
MAX.
Parameter
20
TdDA VOf (DAC)
21
ThDO (DAC)
"
22
TdDAClr (DA V)
23
TdDA VOr(DAC)
DAV! toDAC t
delay-output 3-wire handshake
Data output to DAC t hold
time-3-wire handshake
DAC t to DAV t
delay-output 3-wire handshake
DAV t to DAC !
delay-output 3-wire handshake
LH8036A
MIN.
MAX.
Unit
0
0
ns
1
1
AS cycl€
1
1
\As CyclE
0
0
ns
Note
Note 1: This time can be extended through the use of the deskew timers.
I--'--®
Data
ACKIN
Input (Input)
RFD--------------~
(Output)
Data
==x:~valid ®J:5=®==I
Output ACKIN
(Input)
data
;
® ~~
\
'-----
DAV - - - (Output)
Strobe handshake
Data
Input
ACKIN
(In"ut)
RFD
(Output)
Data
Output
ACKIN
(Input)
DAV
(Output)
Interlock handshake
'-'--~-~--SHARP-'-'-'--'-""'-""",
362
Z8036/Z8036A Counter/Timer and Parallel I/O Unit
LH8036/LH8036A
Data
DAV
(Input)
Input
RFD
(Output)
DAC
(Output)
Data
DAC
(Input)
Output
RFD
(Input)
DAV
(Output)
3-Wire handshake
(3)
No.
1
2
3
4
5
6
7
8
Counter/timer timing
Symbol
10
TcPC
TwPCh
TwPCl
TfPC
TrPC
TcCI
TClh
TwCIl
TfCI
TrCI
11
TsTI (PC)
12
TsTI (CI)
13
TwTI
14
TsGI (PC)
15
TsGI (CI)
16
ThGI (PC)
17
ThGI (CI)
18
TdPC (CO)
19
TdCI (CO)
9
Parameter
PCLK cycle time
PCLK high width
PCLK low width
PCLK fall time
PCLK rise time
Counter input cycle time
Counter input high width
Counter input low width
Counter input fall time
Counter input rise time
Trigger input to PCLKt
setup time (Timer mode)
Trigger input to counter input ~
setup time (Counter mode)
Trigger input pulse"width (High or Low)
Gate input to PCLK ~
setup time (Timer mode)
Gate input to counter input !
setup time (Counter mode)
Gate input to PCLK !
hold time (Timer mode)
Gate input to counter input !
hold time (Counter mode)
PCLK to counter output delay
(Timer mode)
Counter input to counter output delay
(Counter mode)
LH8036
MIN.
MAX.
250
4000
2000
105
105
2000
20
20
500
230
230
20
20
LH8036A
MIN.
MAX.
165
4000
2000
70
70
2000
10
15
330
150
150
15
15
Unit
Note
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
ns
2
ns
2
ns
ns
2
ns
2
ns
2
ns
2
ns
ns
Note 1: PCLK is only used with the counter/timers (in Timer mode), the "deskew timers, and the REQUEST/WAIT logic. If these functions
are not used, the PCLK input can be held low.
Note 2: These parameters must be met to guarantee that trigger or gate are valid for the next counter/timer cycle.
363
Z8036/Z8036A .counter/Timer and Parallel 110 Unit
LH8036/LH8036A
PCLK
PCLK/2 internal
Counter input
Trigger input
Gate input
Counter output
-------1'
_ _ _ _ _- . J
---------------~
Counter/timer timing
(4)
REQUEST/WAIT timing
No.
Symbol
DS ~
DS ~
PCLK
PCLK
4
5
TdACK (REQ)
ACKIN ~ to REQ f delay
6
TdACK (WAIT)
ACKIN ~ to WAIT
- 3
Note 1:
The Delay is from DAV
--
t
LH8036A
MIN.
MAX.
Unit
ns
ns
ns
ns
AScyc1es+
PCLK
cyc1es+ns
PCLK
cyc1es+ns
delay
! for the 3-wire input handshake_ Delay from DAC t for 3-wire handshake output mode.
REQUEST/WAIT
364
LH8036
MIN.
MAX.
to REQ ~ delay
to W AlT ~ delay
~ to REQ t delay
~ to WAIT f delay
TdDS
TdDS
TdPC
TdPC
I
2
(REQ)
(WAIT)
(REQ)
(WAIT)
Parameter
tim~ng
Note
1
Z8036/Z8036A Counter/Timer and Parallel I/O Unit
(5)
LH8036/LH8036A
Reset timing
No.
Symbol
Parameter
1
2
TdDSQ (AS)
TdASQ (DS)
3
TwRES
Delay from DS t to AS ! for no reset
Delay from AS t to DS ! for no reset
Minimum width of AS and DS both
low for reset
Reset internal
LH8036
MAX.
MIN.
40
50
LH8036A
MAX.
MIN.
15
30
250
170
____________________
Unit
Note
ns
ns
ns
~r
Reset timing
(6)
No.
Miscellaneous port timing
Symbol
1
2
3
4
Trl
Tfl
Twl's
TwPM
5
TsPMD
6
ThPMD
Parameter
Any input rise time
Any input fall time
1 's catcher high width
Pattern match input valid (Bit port)
Data latched on pattern match
setup time (Bit port)
Data latched on patter,n match
hold time (Bit port)
LH8036
MIN.
MAX.
100
100
250
750
0
1000
LH8036A
MIN.
MAX.
100
100
170
500
Unit
ns
ns
ns
ns
0
ns
650
ns
Note
1
Note 1: If the input is programmed inverting, a low-going pulse of the same width will be detected.
Any input
1's catcher input
--------'
Pattern match input _ _ _ _--::-:--..J
@'iE---+;.---
Data to be latched to - - - - - ' " \ J.-'--------~
pattern match
r-----
Miccellaneous port timing
handshake, they provide 16 input or output bits
•
Functional Description
with the data direction programmable on a bit-(1) 1/0 port operations
by- bit basis. Port B also provides access for
Of the Z-CIO's three 110 ports, two (Ports A and
Counter/Timers 1 and 2. In all configurations,
B) are general-purpose, and the third (Port C) is a
Ports A and B can be programmed to recognize
special-purpose 4:-bit port. Ports A and B can be
specific data patterns and to generate interrupts
configured as input, output or bidirectional ports
when the pattern is encountered.
with handshake (Four different handshakes are
The four bits of Port C provide the handshake
available.). They can also be linked to form a siglines for Ports A and B when required. A REnal 16-bit port. If they are not used as ports with
QUEST /W AIT line can also be provided so that
~....-.-...-----SHARP---'--------
365
- Z8036/Z8036ACounter/Timer and Parallel 1/0 Unit
Z-CIO transfers can be synchronized with DMAs
or CPUs. Any Port C bits not used for handshake
or REQUEST/WAIT can be used as input or output bits (individually data direction programmable)
or external access lines for Counter/Timer3. Port
C does not contain any pattern-recognition logic. It
is, however, capable orbit-addressable writes.
With this feature, any combination of bit can be set
and/or cleared while the other bits remain undisturbed without first reading the register.
(2) Bit port operations
In bit port operations, the port's Data Direction
register specifies the direction of data flow for
each bit. A 1 specifies an input bit, and a 0 specifies an output bit. If bits are used as I/O bits for a
counter/timer, they should be set as input or output, as required.
The Data Path Polarity register provides the
capability of inverting the data path. A 1 specifies
inverting, and a 0 specifies noninverting. All discussions of the port operations assume that the
path is noninverting.
The value returned when readin~ an input bit reflects the state of the input just prior to the read. A
1 's catcher can be inserted into the input data path
by programming a 1 to the corresponding bit position of the port's Special 110 Control register.
When a 1 is detected at the 1 's catcher input, its
output is set to a 1 until it is cleared. The 1 's
catcher is cleared by writing a 0 to the bit. In all
other cases, attempted writes to input bits are
ignored.
When Ports A and B include output bits, reading
the Data register returns the value being output.
Reads of Port C return the state of the pin. Outputs
can be specified as open-drain by writing a 1 to
the corresponding bit of the port's Special I/O Control register. Port C has' the additional feature of
bit-addressable writes. When writing to Port C, the
four most significant bits are used as a write protect mask for the least significant bits (0-4, 1-5,
2-6, and 3-7). If the write protect bit is written
with a 1, the state of the corresponding output bit
r
is not changed.
(3) Ports with handshake operation
Ports A and B can be specified as 8-bit input,
output, or bidirectional ports with handshake. The
Z-CIO provides four different handshakes for its
ports : Interlocked, Strobed, Pulsed, and 3-Wire.
When specified as a port with handshake, th~
transfer of data into and out of the port' and interrupt generation is under control of the handshake
366
LH8036/LH8036A
logic. Port C provides the handshake lines as
shown in Table 1. Any Port C lines not used for
handshake can be used as simple I/O lines or as
access lines for Counter/Timer 3.
When Ports A and B are configured as ports
with handshake, they are double-buffered. This
allows for more relaxed interrupt service routine
response time. A second byte can be input to or
output from the port before the interrupt for the
first -byte is serviced. Normally, the Interrupt
Pending (IP) bit is set and an interrupt is generated
when data is shifted into the Input register (input
port) or out of the Output register (output port).
For input and output ports, the IP is automatically
cleared when the data is read or written. In
bidirectional ports, IP is cleared only by command.
When the Interrupt on Two Bytes (ITB) control bit
is set to 1, interrupts are generated only when two
bytes of data are available to be read or written.
This allows a minimum of 16 bits of information to
be transferred on each interrupt. With ITB set, the
IP is not automatically cleared until the second
byte of data is read or written.
When the Single Buffer (SB) bit is set to 1, the
port acts as if it is only single-bufferd. This is useful if the handshake line must be stopped on a
byte-by-byte basis.
Ports A and B can be linked to form a 16-bit
port by programming a 1 in the Port Link Control
(PLC) bit. In this mode, only Port A's Handshake
Specification and Command and Status registers
are used. Port B must be specified as a bit port.
When linked, only Port A has pattern-match capability. Port B's pattern-match capability must be
disabled. Also, when the ports are linked, Port B's
Data register must be read or written before Port
A's.
When a port is specified as a port with handshake, the type of port it is (input, output, or bidrectional) determines the direction of data flow.
The data direction for the bidirectional port is determined by a bit in Port C (Table 1). In all cases,
the contents of the Data Direction register are
ignored. The contents of the Special I/O Control
register apply only to output bits (3-state Of
open -drain). Inputs may not have 1 's catchers ;
therefore. those bits in the Special I/O Control register are ignored. Port C lines used for handshake
should be programmed as inputs. The handshak~
specification overrides Port C's Data Direction register for bits that must be outputs. The contents of
Port C's Data Path Polarity register still apply.
Z8036/Z8036A Counter/Timer and Parallel I/O Unit
LH8036(LH8036A
Table 1. Port C bit utilization
Port AlB Configuration
Ports A and B : Bit ports
Port A : Input or output port
(Interlocked, strobed, or pulsed
handshake) *
Port B : Input or output port
(Interlocked, strobed, or pulsed
handshake) *
Port A or B : Input port (3·wire
handshake)
Port A or B : Output port (3·wire
handshake)
Port A or B : Bidirectional port
(Interlocked or strobed handshake)
PC3
Bit I/O
--
RFD or DA V (0)
PC2
Bit I/O
--
ACKIN (I)
PC.
Bit I/O
-REQUEST IW AIT
or Bit I/O
--
REQUEST IW AIT
or Bit I/O
RFD (0)
--
DAV(O)
RFD or DA V (0)
Bit 110
--
DAV(I)
DAC (I)
--
ACKIN(I)
--
FD or DAV (0)
REQUESTlW AIT
or Bit 110
REQUEST IW AIT
or Bit 110
REQUEST IW AIT
or Bit 110
PCo
Bit I/O
Bit I/O
-ACKIN (I)
DAC(O)
RFD (I)
--
INIOUT
*Both ports A and B can he specified input or output with interlocked, strobed, or pulsed handshake at the same time if neither uses RE·
QUESTlW AlT.
(4) Interlocked handshake
In the Interlocked Handshake mode, the action of
the Z-CIO must be acknowledged by the external
device before the next action can take place. Fig. 1
shows timing for Interlocked Handshake. An output
port does not indicate that new data is available
until the external device indicates it is ready for
the data. Similarly, an input port does not indicate
that it is ready for new data until the data source
indicates that the previous of the data is no loger
available, thereby acknowledging the input port's
acceptance of the last byte. This allows the Z-CIO
to interface directly to the port of a Z8 microcomputer, a UPC, an FlO, an FIFO, or to another
Z-CIO port with no external logic.
A 4-bit deskew timer can be inserted in the Data
Available (DA V) output for output ports. As data is
transferred to the Buffer register, the deskew timer
is triggered. After the number of PCLK cycles specified by the deskew timer time constant pi use one,
DA V is allowed to go Low. The deskew timer
therefore guarantees that the output data is valid
for a specified minimum amount of time before
DA Vgoes Low. Deskew timers are available for
output ports independent of the type of handshake
employed.
(5) Strobed handshake
In the Strobed Handshake mode, data is "strobed"
into or out of the port by the external logic. The falling
edge of the Acknowledge Input (ACKIN) strobes data
into or out of the port Fig. 1 shows timing for the
Strobed Handshake. In contrast to the Interlocked
Handshake, the signal indicating the port is ready for
another data transfer operates independently of the
ACKIN input It is up to the external logic to ensure
that data overflows or underflows do not occur.
INPUT HANDSHAKE
DATA
=x
VALID
XI..________
ACKIN
RFD
DATA LATCHED IN
BUFFER REGISTER
DATA MOVED
TO INPUT
REGISTER
INTERLOCKED
HANDSHAKE
OUTPUT HANDSHAKE
DATA
ACKIN
DAV
BUFFER REGISTER
"EMPTIED"
NEXT BYTE
DESKEW TIME
.,-----
\
STROBED HANDSHAKE
NEXT BYTE SHIFTED FROM OUTPUT
REGISTER TO BUFFER REGISTER
Fig. 1 Interlocked and strobed handshakes
(6) 3-wire handshake
The 3-Wire Handshake is designed for the situation in which one output port is communicating
with many input ports simultaneously. It is essen·
tially the same as the Interlocked Handshake, except that two signals are used to indicate if an in-
------------SHARP-----..-......---367.
.
,
-
.....- ............... ..........
Z8036/Z8936A Counter/Timer and ParalleVIIQUnit
-~
_.-:
put port is ready for new data or if it has accepted
the present data. In the 3-Wire Handshake (Fig. 2),
~he rising edge of one status line indicates that the
port is read'y for data, and the rising edge of
another status line indicates that the data has been
accepted. With the 3-Wire Handshake, the output
lines of many input ports can be bussed together
with open-drain drivers; the output port knows
when all the ports have accepted the data and are
ready. This is the same handshake as is used on
the IEEE-488 bus. Because this handshake requires'three lines, only one port (either A or B) can
be a 3-Wire Handshake port at a time. The 3-Wire
Handshake is not available in the bidirectional
mode. Because the port's direction can be changed
under software control, however, bidirectional
IEEE-488-type transfers can be performed.
INPUT HANDSHAKE
DATA ~_______________
DAV
INPUT
RFD -~~
OUTPUT
DAC
OUTPUT
'-------+---J DATA SHIFTED
TO INPUT REGISTER
DATA LATCHED I
IN BUFFER REGISTER
OUTPUT HANDSHAKE
piA T A _ _ _ _ _ _ _
_ _BYTE
___
NEXT
-JI,~
RFD
INPUT __________J
DAC
INPUT
LAST ONE
DAV
OUTPUT
BUFFER REGISTER
"EMPTIED"
NEXT BYTE SHIFTED FROM OUTPUT
REGISTER TO,BUFFER REGI~TER
Fig. 2 3-wire handshake
(7) Pulsed handshake
The Pulsed Handshake (Fig. 3) is designed to interface to mechanical-type devices that require
data to be held for long periods of time and need
relatively wide pulses to gate the data into or out of
the device. The logic is the same as the Interlocked
Handshake mode, except that an internal counter /
timer is linked to the handshake logic. If the port is
specified in the input mode, the timer is inserted in
the' ACKIN path,. The external ACKIN input trig-
..........
' LH8036/LR8036A
~-
INPUT PORT
ACKiN
cEXT~ERNAL)
,
ACKIN
TRIGGER COI!mR
INPUT
~(INTERNAL)
,QUTPlIT
CIT 3
• ,
r~l
.J
L
.
I
-
'
OUTPUT PORT
TRIGGER COUNTER
INPlIT
OlITPlIT
DAV
CIT 3
Fig. 3 Pulse handshake
gers the timer and its output used as the Interlocked Handshake's normal acknowledge input. If the
port is an outP\1t port, the timer is placed in the
Data Available (DAV) output path. The timer is
triggered when the ilOrmal Interlocked Handshake
DA V output goes Low and the timer output is used
as the actual DAV output. The counter/timer maintains all of its normal capabilities. This handshake
is not available to bidirectional ports.
(8) REQUEST/WAIT line operation
Port C can be programmed to provide a status
signal output in addition to the normal handshake
lines for either Port A or B when used as a port
with handshake. The additional signal is either a
REQUEST or WAIT signal. The REQUEST signal
indicates when a port is ready to perform a data
transfer via the Z-Bus. It is intended for use with a
DMA -type device. The WAIT signal provides synchronization for transfers with a CPU. Three bits
in the Port Handshake Specification register provide controls for the REQUEST /W AIT logic. Because the extra Port C line is used, only one port
can be specified asa port with a handshake and a
REQUEST /W AIT line. The other port must be a
bit port.
Operation of the REQUEST line is modified by
the state of the port's Interrupt on Two Bytes (ITB)
control bit. When ITB is 0, the REQUEST line goes
active as soon as the Z-CIO is ready for a data
transfer. If ITB is 1, REQUEST does not go active
until two bytes can be transferred. REQUEST
stays active as long as a byte is available to be
read or written.
The SPECIAL REQUEST function is reserved
for use with bidirectional ports only., In this case,
the REQUEST line indicates the status of the register not being used in the data path at that time. If
the IN/OUT line is High, the REQUEST line is '
High when the Output register is empty. If IN/OUT
is Low, the REQUEST line is High when the Input
. - - . - - - - - - - - - - S H A R P ---~----..-.-.-368
Z8036/Z8036A Counter/Timer and Parallel I/O Unit
register is full.
(9) Pattern-recognition logic operation
Both Ports A and B can be programmed to generate interrupts when a specific pattern is recognized
at the port. The pattern-recognition logic is independent of the port application, thereby allowing
the port to recognize patterns in all of its configurations. The pattern can be independently specified for each bit as 1, 0, rising edge, falling edge,
or any transition. Individual bits may be masked
off. A pattern-match is defined as the simultaneous
satisfaction of all non masked bit specifications in
the AND mode or the satisfaction of any nonmasked bit specifications in either of the OR or
OR-Priority Encoded Vector modes.
The pattern specified in the Pattern Definition
register assumes that the data path is programmed
to be non inverting. If an input bit in the data path
is programmed to be inverting, the pattern detected
is the opposite of the one specified. Output bits
used in the pattern-match logic are internally sampled before the invert/noninvert logic.
(10) Bit port pattern-recognition operations
During bit port operations, pattern-recognition
may be performed on all bits, including those used
as I/O for the counter/timers. The input to the pattern-recognition logic follows the value at the pins
(through the invert/noninvert logic) in all cases except for simple inputs with 1 '1) catchers. In this
case, the output of the 1 's catcher is used. When
operating in the AND or OR mode, it is the transition from a nomatch to a match state that causes
the interrupt. In the "OR" mode, if a second match
occurs before the first match goes away, it does not
cause an interrupt. Since a match condition only
lasts a short time when edges are specified, care
must be taken to avoid losing a match condition. Bit
ports specified in the OR-Priority Encoded Vector
mode generate interrupts as long as any match
state exists. A transition from a no-match to a
match state is not required.
The pattern-recognition logic of bit ports operates in two basic modes: Transparent and Latched.
When the Latch on Pattern Match (LPM) bit is set
to 0 (Transparent mode), the interrupt indicates
that a specified pattern has occurred, but a read of
the Data register does not necessarily indicate the
state of the port at the time the interrupt was
generated. In the Latched mode (LPM = 1), the
state of all the port inputs at the time the interrupt
was generated is latched in the input register and
held until IP is cleared. In all cases, the PMF indicates the state of the port at the time it is read.
If a match occurs while IP is already set, an
LH8036/LH8036A
error condition exists. If the Interrupt On Error bit
(IOE) is 0, the match is ignored. However, if IOE is
1, after the first IP is cleared, it is automatically
set to 1 along with the Interrupt Error (ERR). flag.
Matches occurring while ERR is set are ignored.
ERR is cleared when the corresponding IP is
.
cleared.
When a pattern-match is pressent in the ORPriority Encoded Vector mode, IP is set to 1. The
IP cannot be cleared until a match is no longer present. If the interrupt vector is allowed to include
status, the vector returned during Interrupt Acknowledge indicates the highest priority bit matching its specification at the time of the Acknowledge
cycle. Bit 7 is the highest priority and bit 0 is the
lowest. The bit initially causing the interrupt may
not be the one indicated by the vector if a higher
priority bit matches before the Acknowledge. Once
the Acknowledge cycle is initiated, the vector is
frozen until the corresponding IP is cleared. Where
inputs that cause interrupts might change before
the interrupt is serviced, the 1 's catcher can be
used to hold the value. Because a no-match to
match transition is not required, the source of the
interrupt must be cleared before IP is cleared or
else a second interrupt is generated. No error detection is performed in this mode and the Interrupt
On Error bit should be set to O.
(11) Ports with handshake patternrecognition operation
In this mode, the handshake logic normally controls the setting of IP and, therefore, the generation
of interrupt requests. The pattern-match logic controls the Pattern Match Flag (PMF). The data is
compared with the match pattern when it is shifted
from the Buffer register to the Input register (input
port) or when it is shifted from the Output register
to the Buffer register (output port). The patternmatch logic can override the handshake logic in
certain situations. If the port is programmed to interrupt when two bytes of data are available to be
read or written, but the first byte matches the specified pattern, the pattern-recognition logic sets IP
and generates an interrupt. While PMF is set, IP
cannot be cleared by reading or writing the data
registers. IP must be cleared by command. The input register is not emptied while IP is set, nor is
the output register filled until IP is cleared.
If the Interrupt on Match Only (IMO) bit is set,
IP is set only when the data matches the pattern.
This is useful in DMA-type applications when interrupts are required only after a block of data is
transferred.
----.--.---SHARP---~---~.-.-r--
369
Z8036/Z8036A Countertfimer and Parallel 110 Unit
(12) Counter/timer operation
the three independent 16-bit counter/timers
consist of a presettable 16-bit down counter, a
16-bit Time Constant register, a I6-bit Current
Counter register,art 8-bit Mode Specification register, an 8-bit Command and Status register, and
the associated control logic that links these registers.
The flexibility of the counter/timers is enhanced
by the provision of up,to four lines per counter /
timer (counter input, gate input, trigger input, and
counter/timer output) for direct external control
and status. Counter/Timer l's external I/O lines
are provided by the four most significant bits of
Port B. Counter/Timer 2's are provided by the
four least significant bits of Port B. Counter/Timer
3's external I/O lines are provided by the four bits
of Port C. The utilization of these lines (Table 2) is
programmable on a bit-by-bit basis via the Counter /Timer Mode Specification registers.
When external counter/timer I/O lines are to be
used, the associated port lines must be vacant and
programmed in the proper data direction. Lines
used for counter/timer I/O have the same characteristics as simple input lines. They can be specified as inverting or noninverting ; they can be read
and used with the pattern-recognition logic. They
can also include the 1 's catcher input.
Counter/Timers 1 and 2 can be be linked internally in three different ways. Counter/Timer 1 's output (inverted) can be uS'ed as Counter/Timer 2's
trigger, gate, or counter input. When linked, the
Table 2 Counter/timer external access
Function
Counter/timer output
Counter input
Trigger input
Gate input
'C/T!
PB4
PB5
PB6
PB7
C/T 2
PBO
PBl
PB2
PB3
C/T 3
peo
PCl
PC2
PC3
counter/timers have the same capabilities as when
used separately. The only restriction is that when
Counter/Timer 1 drives Counter/Timer 2's count
input, Counter/Timer 2 must be programmed with
its external count input disabled.
There are three duty cycles available for the tim'
er/counter output: pulse, one-short, and square
-wave. Fig. 4 shows the counter/timer waveforms.
When tte Pulse mode is specified, the output goes
High for one clock cycle, beginning when the down-counter leaves the count of 1. In the One-Shot
mode, the output goes High when the counter/timer
is triggered and and goes Low when the ddwn-
LH8036/LH8036A
'counter reaches O. When the square -wave output
duty cycle is spec-ified, the counter/timer goes
through two full sequences for each -cycle. The initial trigger causes the down-counter to be loaded
and the normal countdown sequence to begin. If a 1
count is detected on the down-counter's clocking
edge, the output goes High and the time constant
value is reloaded. On the clocking edge, when both
the down-counter and the output are 1 's, the output
is pulled back Low.
The Countinuous/Single Cycle (elSe) bit in the
Mode Specification register controls operation of
the down-counter when it reaches terminal count.
If C/SC is 0 when a terminal count is reached, the
'countdown sequence stops. If the C/SC bit is 1
each time the countdown counter reaches 1, the
next cycle causes the time constant value to be reloaded. The time constant value may be changed by
the CPU, and on reload, the new time constant
value is loaded.
Counter/timer operations require loading the
time constant value in the Time Constant register
and initiating the countdown sequence by loading
the down-counter with the time constant value.
The Time Constant register is accessed as two
8-bit registers. The registers are readable as well
as writable, and the access order is irrelevant. A 0
in the Time Constant register' specifies a time constant of 65,536. The down-counter is loaded in
one of three ways :
(1) By writing a 1 to the Trigger Command Bit
(TCB : write-only),
(2) On the rising edge of the external trigger input, or,
(3) For Counter/Timer 2 only" on the rising
edge of Counter/Timer l's internal output if
the counters are linked via the trigger input.
Once the down-counter is loaded, the countdown
sequence continues toward terminal count as long
as all the counter/timers' hardware and software
gate inputs are High. If any of the gate inputs goes
Low (0), the countdown halts. It resumes when all
gate inputs ate 1 again.
The reaction to triggers occurring during a
countdown sequence is determined by the state of
the Retrigger Enable Bit (REB) in the Mode Specification register. If REB is 0, retriggers are ignored
and the countdown continues normally. If REB is 1,
each'trigger causes the down-counter to be reloaded and the count-down sequence starts over
again. If the output is programmed in the Square
-Wave mode, retrigger causes the sequence to start
over from the initial load of the time constant.
------~-----SHARP-.-.--~.---.-.
370
LH8036/LH8036A
Z8036/Z8036A Counter/Timer and Parallel I/O Unit
The rate at which the down-countor counts is
determined by the mode of the counter/timer. In
the Timer mode (the External Count Enable IECE]
bit is 0), the down-counter is clocked internally by
a signal that is half the frequency of the PCLK input to the chip. In the Counter mode (ECE is 1), the
down-counter is decremented on the rising edge of
the counter/timer's counter input.
Each time the counter reaches terminal count, its
Interrupt Pending (IP) bit is set to 1, and if interrupts are enabled (IE= 1), an interrupt is generated. If a terminal count occurs while IP is already
set, an internal error flag is set. As soon as IP is
cleared, it is forced to a 1 along with the Interrupt
Error (ERR) flag. Errors that occur after the internal flag is set are ignored.
The state of the down-counter can determined in
two ways:
PCLK/20R
COUNTER INPUT
By reading the contents of the down-counter
via the Current Count register, or
(2) By testing the Count In Progress (CIP) status bit in the Command Status register.
The CIP status bit is set when the down-counter
is loaded; it is reset when the down-counter reaches
O. The Current Count register is a 16-bit register,
accessible as two 8-bit registers, which mirrors
the contents of the down-counter. This register can
be read anytime. However, reading the register is
asynchronous to the counter's counting, and the
value returned is valid only if the counter is stopped. The down-counter can be reliably read "on
the fly" by the first writing of a 1 to the Read
Counter Control (RCC) bit in the counter/timer's
Command and Status register. This freezes the
value in the Current Count register until a read of
the least significant byte is performed.
(1)
~~
TRIGGER~
U
GATE
fI
1 TC ITC-1ITC-1I TC- 21 .. ·1.1
PULSE OUTPUT
TC
I OaR
I
------------1r~
[J
ONE SHOT
OUTPUT - - - - '
SQUARE WAVE OUTPUT
FIRST HALF _ _ _ _ _ _ _ _ _ _
--j;c~1
_ _--l
SQUARE WAVE OUTPUT-----------------jfff------,
SECOND HALF
'----
Fig. 4
Counter/timer waveforms
..--.~------SHARP----------
371
Z8036/Z8036A Gounter/Timer and Parallel I/O. Unit
•
LH8036/LH8036A
Internal Registers
The followings' illustrate the contents of the Registers and, in addition, give to register address
summary
• Maste~ Interrupt C.ontrol Register (MICR)
Address : 000000
(Read/Write)
l:
II
107 1 06 1 Os 1041 03 1 Dd 011 Do I
MASTERINTERRUPT~
ENABLE (MIE)
1
DISABLE LOWER CHAIN (DLC)
NO VECTOR (NV)
COUNTER/TIMERS VECTOR
INCLUDES STATUS (CT VIS)
PORT A VECTOR INCLUDES------"
STATUS (PA VIS)
•
LRESET
L'RIGHT JUSTIFIED ADDRESSES
O=SHIFT LEFT (Ao from ADl)
I=RIGHT JUSTIFY (Ao from ADo)
'-------PORT B VECTOR INCLUDES
STATUS (PB VIS)
Master Configuration Control Register (MCCR)
Address: 000001
(Read/Write)
107106/051 D41 031021011 Dol
oj
PORT
ENABLE (PBE)
I
I
---CCOUNTERITIMER LINK
CONTROLS (LC)
LCI LCO
0
0 COUNTER/TIMERS INDEPENDENT
0
1 CIT 1's OUTPUT GATES CIT 2
0 CIT 1'8 OUTPUT TRIGGERS CIT 1
1
l I C I T l's OUTPUT IS CIT 2's
COUNT INPUT
COUNTER/TIMER 1
ENABLE (CTIE)
COUNTER/TIMER 2
ENABLE (CT2E)
PORT C AND COUNTER/------"
TIMER 3 ENABLE
(PCE AND CT3E)
•
'------PORTA ENABLE (PAE)
'-------PORT LINK CONTROL (PLC)
O=PORTS A AND B OPERATE INDEPENDENT
I=PORTS A AND B ARE LINKED
Port Mode Specification Registers (PMSR)
Addresses: 100000 Port A
101000 Port B
(Read/Write)
I
L
1071 D61 Os 1D41 D31 D21 01 Do 1
PORT
SEL~CTS
TYPE~
(PTS)
PTSI PTSO
o
o
1
1
0
1
0
1
BIT PORT
INPUT PORT
OUTPUT PORT
BIDIRECTIONAL
PORT
INTERRUPT ON TWO------'
BYTES (ITB)
SINGLE BUFFERED--------'--"
MODE (SB)
LLATCH ON PATTERN MATCH (LPM)
(BIT MODE)
DESKEW TIMER ENABLE (DTE)
(HANDSHAKE MODES)
.
PATTERN MODE SPECIFIC~TION
BITS (PMS)
PMSI PMSO
- 0 - --0- DISABLE PATTERN MATCH
o
1
"AND" MODE
1
0
"OR" MODE
1
1
"OR PRIORITY ENCODED
VECTOR" MODE
'------INTERRUPT ON MATCH ONLY elMO)
--.-.-----------SHARP ---....-.--------
372
Z8036/Z8036A Counter/Timer and Parallel I/O Unit
•
LH8036/LH8036A
Port Handshake Specification Registers (PHSR)
Addresses: 100001 Port A
101001 Port B
(Read/Write)
! D7! D61 D5! D.I Da! D2! D,
HANDSHAKE TYPE
SPECIFICATION~
LDESKW TIME SPECIFICATION
BITS
SPECIFIES THE MSB's OF
DESKEW TIMER TIME CONSTANT
LSB IS FORCED 1.
BiTS (HST)
HSTl HSTO
o
o
0
1
1
1
0
1
IDol
INTERLOCKED HANDSHAKE
STROBED HANDSHAKE
PULSED HANDSHAKE
THREE WIRE HANDSHAKE
REQUEST/WAIT SPECIFICATION-----'
BITS (RWS)
RWS2 RWSI RWSO FUNCTION
- 0 - --0- --0- REQUEST WAIT DISABLED
o
0
1
OUTPUT WAIT
o
1
1
INPUT WAIT
1
0
0
SPECIAL REQUEST
1
0
1
OUTPUT REQUEST
1
1
1
INPUT REQUEST
•
Port Command and Status Registers (PCSR)
Addresses: 001000 Port A
001001 Port B
(Read/Partial Write)
! D71 D6! D5! D4! Da! D21 Dl ! Dol
INTERRUPT UNDER
SERVICE (IUS)
INTERRUPT ENABLE {IE}
INTERRUPT PENDING {IP}
IUS, IE, AND IP ARE WRITTEN USING
THE F:0LLOWING CODE:
NULL CODE
CLEAR IP & IUS
SET IUS
CLEAR IUS
SET IP
CLEAR IP
SET IE
CLEAR IE
~
jJ
I
I
I
I
I
I
I
I
I
I
II
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
INTERRUPT ON ERROR (IOE)
PATTERN MATCH FLAG (PMF)
(READ ONLY)
INPUT REGISTER FULL (IRF)
(READ ONLY)
OUTPUT REGISTER EMPTY (ORE)
(READ ONLY)
0
1
0
1
0
1
0
1
INTERRUPT ERROR (ERR)
(READ ONLY)
-----------........,.-----.--SHARP~---------
373
.............................. .....
Z8036/Z8036A Counter/TImer and Parallel I/O Unit
,
•
~
Data Path Polarity Registers (DPPR)
LH8036/LH8036A
~~~
•
~
Special 1/0 Control Registers (SIOCR)
Addresses: 100010 Port A
101010 Port B
000101 Port C (4 LSBs only)
(Read/W rite)
Adclresses: 100100 Port A
101100 Port B
000111 Port C (4 LSBs only)
(Read/W~ite)
1~1~1~1~1~I~t~I~1
I~I~I~I~I~I~I~I~I
I
I
DATA PATH POLARITY (DPP)
0= NON -INVERTING
1 = INVERTING
•
..... .....
..........
~~
SPECIAL INPUT /OUTPUT (SIO)
0= NORMAL INPUT OR OUTPUT
1 = OUTPUT WITH OPEN DRAIN OR
INPUT WITH I's CATCHER
Data Direction Registers (DDR)
•
Port Data Registers (PDR)
Addresses: 001101 Port A
001110 Port B
(Read/Write)
Addresses: 100011 Port A
101011 Port B
ooono Port C (4 LSBs only)
(Read/Write)
I~I~I~I~I~I~I~I~I
•
DATA DIRECTION (DD)
0= OUTPUT BIT
1 = INPUT BIT
•
•
Address: 001111
(Read/Write)
4 MSBs
0= WRITING OF CORRESPONDING LSS ENABLED
1 = WRITING OF CORRESPONDING LSS INHIBITED
(READ RETURNS 1)
Pattern Polarity Registers (PPR)
Addresses: 100101 Port A
101101 Port B
(Read/Write)
ID71 D61 D51 D41 D31 Dzi D, IDo I
I
Pattern Transition Registers (PTR)
Addresses: 100110 Port A
101110 Port B
(Read/Write)
ID71 D61 Dsl D41 D31 Dzi D, IDo I
PM
O·
o
1
1
1
1
•
374
PT
0
1
0
0
1
1
PP PATTERN SPECIFICATION
X BIT MASKED OFF
X ANY TRANSITION
0 ZERO
lONE
0 ONE-TO-ZERO TRANSITION (\.)
1 ZERO-TO-ONE TRANSITION (,i')
Pattern Mask Registers (PMR)
Addresses: 100111 Port A
101111 Port B
(Read/Write)
-
Port C Data Register (PCDR)
I~I~I~I~I~I~I~I~I
I
........ ------~ .......... -SHARP . - . - . - - - - - - - - - - - -
LH8036/LH8036A
Z8036/Z8036A Counter/Timer and Parallel I/O Unit
•
Counter/Timer Command and Status Registers (CTCSR)
Addresses 0 0 1 0 1 0 Counter /Timer 1
o 0 1 0 1 1 Counter /Timer 2
o 0 1 1 0 0 Counter/Timer 3
(Read/Partial Write)
I~I~I~I~I~I~I~I~I
II
(IUS)-.J~
Interrupt under service
(Read/Write)
Interrupt enable (IE) - (Read/Write)
Interrupt pending (IP)
(Read/Write)
IUS, IE, IP are written using the following code
OOO=Null code
001 = Clear IP & IU S
010=Set IUS
011=ClearlUS
100 = Set IP
101 = Clear IP
110 = Set IE
111 = Clear IE
•
' • "'","" (CIP)
LCooo
(Read only)
Trigger command bit (TCB)
(Write only. Read returns 0)
Gate command bit (GCB)
(Read/Write)
Read counter control (RCC)
(Read/Set only cleared by reading CCR Ls)
' - - - - - - - - Interrupt error (ERR)
(Read only)
Counter/Timer Mode Specification Registers (CTMSR)
Addresses 0 1 1 1 0 0 Counter /Timer 1
o1
o1
1 1 0 1 Counter /Timer 2
1 1 1 0 Counter /Timer 3
(Read/Write)
C~H"OOM
,mg" ,,''(C/SC)~
External output enable (EOE)
I
I
II
I
External count enable (ECE)
External trigger enable (ETE)
External gate enable (EGE)
•
L
0.".,
,.".,.,. ,.,.,"
00 = Pulse output
.
01 = One -shot output
10 = Sq'uarew ave output
11 = Do not specify
Retrigger enable bit (REB)
Counter/Timer Current Count Registers (CTCCR)
Address 0 1 0 0 0 0 Counter/Timer 1's MSB
o 1 0 0 0 1 Counter/Timer l's LSB
o 1 0 0 1 0 Counter /Timer 2's MSB
o 1 0 0 1 1 Counter/Timer 2's LSB
o 1 0 1 0 0 Counter /Timer 3's MSB
o 1 0 1 0 1 Counter/Timer 3's LSB
(Read only)
I
I
D71 Dol Dsl D41 D31 D,I Dl Do I D71 Dol Dsl D41 D31 Dzi Dl I Do
Most significante byte---_--'f
I
----Least significant byte
,--I
375
L.,H8036/LH8036A
Z.8036/Z8036A Gounter/Timer and Parallel. I/O Unit
•
Counter/Timer Time Constant Registers (CTTCR)
Addresses: 010110 Counter/Timer
010111 ·Counter/Timer
011000 Counter/Timer
011001 Counter/Timer
011010 Counter/Timer
011011 Counter/Timer
(Read/Write)
MOST
1's MSB
1's LSB
2;s MSB
2's LSB
3's MSB
3's LSB
I~I~I~I~I~I~I~I~I~I~I~I~I~I~I~I~I
SIGNIFICANT------.JI
L-I--~--LEAST
BYTE
•
Interrupt Vector Register (lVR)
SIGNIFICANT
BYTE
•
Counter/Timer Status
D2
0
.0
1
1
Addresses: 000010 Port A
000011 Port B
000100 Counter /Timers
(Read/Write)
D1
0
1
0
C/T3
C/T2
C/Tl
Error
I~I~I~I~I~I~I~I~I
I
INTERRUPT VECTOR
•
Port Vector Status
(1)
P encoded vector mode
X(X
(2)
X
Number of highest priority
bit with a watch
All other modes
ORE IRF PMF
o 0 0
Normal
Error
•
Current Vector Register (CVR)
Address: 011111
(Read Only)
I~I~I~I~I~I~I~I~I
I
INTERRUPT V~CTOR BASED
ON HIGHEST PRIORITY
UNMASKED IP.
IF NO INTERRUPT PENDING
ALL 1'8 OUTPUT.
~----------SHARP-~-----3.76
Z8038/Z8038A FlO Input/Output Interface Unit
LH8038/LH8038A
LH8038/LH8038A Z80381Z8038A FlO
I~putl
Output Interface Umt
•
Description
The LH8038 Z8038 FlO provides an asynchronous 128 byte FIFO buffer between two CPUs or
between a CPU and a peripheral device_ This buffer interface expands to a 16-bit or wider data
path and expands in depth to add as many FIFOs
(and an additional LH8038) as are needed.
The LH8038 manages data transfers by assuming Z-BUS, non-Z-BUS microprocessor (a generalized microprocessor interface), Interlocked 2-Wire
,Handshake, and 3-Wire Handshake operating modes.
These modes interface dissimilar CPUs or CPUs
and peripherals running under differing speeds or
protocols, allowing asynchronous data transactions
and improving I/O overhead by as much as two
orders of magnitude.
The LH8038 supports the Z-BUS interrupt protocols, generating seven sources of interrupts upon
any of the following events: a write to a message
register, change in data direction, pattern match,
status match, over/underflow error, buffer full and
buffer empty status. Each interrupt source can be
enabled or disabled, and can also place an interrupt vector on the port address/data lines.
The LH8038A Z8038A 1"10 is the high speed
version which can operate at 6MHz system clock.
•
Features
1. 128-byte FIFO buffer provides asynchronous
bidirectional CPU/CPU or CPU/peripheral interface, expandable to any width in byte increments by use of multiple FIOs.
2. Interlocked 2-Wire or 3-Wire Handshake logic
port mode; Z-BUS or non-Z-BUS interface.
3. Pattern-recognition logic stops DMA transfers
and/or interrupts CPU; preset byte count can
initiate variable-length DMA transfers.
•
Pin Connections
o
+5V
[AJ
rnJ
~
mJ
ffi]
[f]
[Q]
llil
rn
rn
00
OJ
02
~
03
O.
05
0&
07
GNO
Mo
Top View
4. Seven sources of vectored/nonvectored interrupt which include pattern-match, byte count,
empty or full buffer status; a dedicated "mailbox" register with interrupt capability provides CPU/CPU communication.
5. REQUEST /W AIT lines control high-speed
data transfers.
6. All functions are software controlled via directly
addressable read/write registers.
377
Z8038/z8038A FlO Input/Output Interface Unit
•
LH8038/LH8038A
Block Diagram
Pattern
Match
Logic
Data Bus
Data
Buff~r
Register
Status Logic
and Registers
Pattern
Match
Logic
Data
Buffer
Register
128X8
FIFO Buffer
Data Bus
Port 1 Side I Port 2 Side
I
I
:-~------SHARP
378
....------...-.-----------
Z8038/Z8038A FlO Input/Output Interface Unit
•
LH8038/LH8038A
Pin Description
(1)
Pins common to both ports 1 and 2
Pin
Mo
Ml
(2)
Pin signal
Mo
Ml
Meaning
Multimicro output
Multimicro input
I/O
0
I
Function
Ml and Mo program Port 1 side
CPU interface
Z-bus low byte mode
Pin
Pin signal
Meaning
Do-D 7
AD o-AD 7
Address/ data bus
-----
I/O
Bidirectional
3-state
REQ/WAIT
Request/wait
0
DMASTB
DMA strobe
I
Data strobe
I
Read/write
I
Chip select
I
AS
Address strobe
I
G
INTACK
Interrupt acknowledge
I
H
lEO
Interrupt enable output
0
I
lEI
Interrupt enable input
I
Interrupt request
0
A
B
-
C
D
DS
-
R/W
-
CS
E
F
J
-
-
INT
Function
Multiplexed bidirectional bus, Z-BUS compatible
Active low. open-drain output with WAITselected ;
REQUEST line for DMA transfer; WAIT line for
data transfers to and from CPU.
Active low. Provides timing for data transfer to and
from the FIFO buffer.
Active low. Provides timing for data transfer to or
fn?m Z·FIO.
Active high signals CPU to head from Z-FIO ; active
Low signals CPU to write to Z-FIO.
Active low. Enables Z-FIO. Latched on the rising
edge of AS.
Active low. Addresses. CS and INT ACK are sampled
while AS is Low.
Active low. Latched on the rising edge of AS.
Active high. Sends interrupt enable to lower priority
device lEI pin.
Active high. Receives interrupt enable from higher
priority device lEI pin.
Active low, open-drain output.
Interrupt request signal to CPU.
(3) Z-bus high byte mode
Pin
Pin signal
Meaning
Do-D 7
ADo-;-AD7
Address/ data bus
A
B
C
D
E
F
G-J
-----
I/O
Bidirectional
3-state I
REQ/WAIT
Request/wait
0
DMASTB
DMA strobe
I
Data strobe
I
Read/write
I
Chip select
I
AS
Address strobl·
I
Ao-Aa
Address bits
I
-
DS
-
R/W
-
CS
-
Function
Multiplexed bidirectional bus, Z-BUS compatible.
Active low, open-drain output when WAIT selected;
REQUEST line for DMA transfer; WAIT line for
data transfers to and from CPU.
Active low. Strobes DMA data to and from the FIFO
buffer.
Active low. Provides timing for data transfer to or
from Z-FIO.
Active high signals CPU to read from Z-FIO ; active
low signal CPU to write to Z-FIO.
Active low. Enables Z-FIO. Latched on the rising
edge of AS
Active low. Addresses, CS and INT ACK are sampled
while AS is low.
Active high. Specify Z=FIO internal registers.
379
LH8038/LH8038A
l8038/Z8038A FlO Input/Output Inter:tace Unit
(4)
Non-Z-bus mode
Pin
Pin signal
Meaning
Do -D 7
Do-D 7
Data bus
-----
110
Bidirectional
3-state
REQ/WAIT
Req uestl wait
0
B
C
D
E
DACK
RD
WR
CE
DMA acknowledge
Read
Write
Chip select
I
I
I
I
F
C/D
Controll data
I
G
INTACK
Interrupt acknowledge
I
H
lEO
Interrupt enable output
0
I
lEI
Interrupt enable input
I
Interrupt
0
I/O
Bidirectional
3-state
A
-
-
J
(5)
INT
Pin signal
Meaning
Do -D 7
Do-D 7
Data bus
A
RFD/DAV
--
Ready for datal
data available
0
~:
---
ACKIN
--
Acknowledge input
I
Data availablel
data accepted
I
Full
0
B
DAV/DAC
C
FULL
C
DAC/RFD
Data acceptedl
ready for data
110
D
EMPTY
Empty
0
CLEAR
Clear
110
F
DATA DIR
Data direction
I/O
G
H
INo
OUT l
Input
Output
I
0
OE
Output enable
0
OUTa
Output
0
E
I
J
Bidirectional data bus.
Active low, open-drain output when WAIT is selected ; REQUEST line for DMA transfer; WAIT line
for data transfer to and from CPU.
Active low. DMA acknowledge signal.
Active low. Timing signal for reading.
Active low. Timing signal for writing.
Active low. Signal that is used to select Z-FIO.
Active high identifies control byte on Do-D7, active
low identifies data byte on Do- D7
Active low. acknowledges an interrupt.
Active high. Sends interrupt enable to lower priority
device IEI pin.
Active high. Receives interrupt enable from higher
priority device lEO signal.
Active low, open drain. Signals Z-FIO interrupt to
CPU.
Port 2-1/0 port mode
Pin
B
Function
---
-
Function
Bidirectional data bus.
For input handshake, RFD (active High) signals that
Z-FIO is ready to receive data. For output handshake,
DA V (active Low) signals that output data is valid
Active low. Signals that input data is valid in the case
of input handshake or that output data is received by
peripherals in the case of output handshake.
For input handshake, DA V (active low) signals that
input data is valid. For output handshake, DAC (active high) signals that listener has received data.
Active high, open drain. Signals that FIFO buffer is
full.
Both active high. For input handshake, DAC (an output) signals that data has been received from talker.
For output handshake, RFD (an input) signals that
the listeners are ready for data.
Active high, open drain. Signals that FIFO buffer is
empty.
Active low. Can clear data from FIFO buffer in the
case of input.
Data direction is controllable for input. Active high
signals data input to ports 2 ; Low signals data output from Port 2.
Input line to bit 0 (Do) of control register 3.
Output line from bit (D l ) of control register 3.
Actiye low. When low, enables bus drivers. When
high, floats bus drivers at high inpedance .
. Output line from bit 3 (D3) of control register 3_
---.-.------SHARP------------380
Z8038/Z8038A FlO Input/OLitput Interface Unit
•
LH8038/LH8038A
Absolute Maximum Ratings
Parameter
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Note
Symbol
V IN
VOUT
Top,
' T s'"
Ratings
-0.3-+7
-0.3-+7
0-+70
-6S-+1S0
Unit
V
V
"C
"C
The maximum applicable voltage on any pin with respect to GND.
+5V
+5V
2.2kn
From test output
0--..-+-1......
From test output
i
12.2k!l
r
50PF
Standard test load
•
Parameter
Input high voltage
Input low voltage
Output high voltage
Symbol
VlH
V IL
VOH
Output low voltage
VOL
I IIIL I
IloL I
ILM
Icc
Conditions
Ion =-2S0,uA
IOL =+2mA
IOL=+3.2mA
O
PORT 3
<8>
Z80 bus
I/O
Z80
} HANDSHAKE
SIGNALS
MEMORY
Z-bus
Z80 bus
Fig. 1 CPU to CPU configuration
•
Fig. 2 CPU to 110 configuration
CPU Interface
The LH8038 is designed to work with both
Z-bus and non-Z-bus-type CPUs on both Port 1
and Port 2. The Z-bus configuration interfaces
CPUs with time·multiplexed address and data in·
formation on the same pins. The Z8001, Z8002,
and Z8 are examples of this type of CPU. The AS
(Address Strobe) pin is used to latch the address
and chip select information sent out by the CPU.
The RIW (Read/Write) pin and the DS (Data
Strobe) pin are used for timing reads and writes
from the CPU to the LH8038 (Fig. 3 and 4).
Address valid
ADo-AD,
The non-Z-bus configuration is used for CPUs
where the address and data buses are separate. An
Example of this type of CPU is the Z80. The RD
(Read) and WR (Write) pins are used to time reads
and writes from the CPU to the FlO (Fig. 5 and 6).
The C/O (Cantrall Data) ~n is used to directly ac·
cess the FIFO buffer JC/D = Low) and to access
the other register (C/D = High).
To CPU
--<'-_....1)>-----«'-_....1)>----
AS
CS~
R/W
DS
,
:J
,'-_ _ _....J/
Fig. 3 Z-bus read cycle timing
389
LH8038/LH8038A
2-8038/Z8038A' FlO Input/Output Interface Unit·
Addre.ss valid
ADo-AD7
--cJ-<
Data from CPU
}--
AS~
CS
''-__--II
DS
Fig. 4
c/n
Z-bus write cycle timing
:==x
x:=
(ToCPU~
\I.-_ _ _ _ _ _ _-JI
CE
\1.-_ _ _ _-J1
RD
Fig. 5
Non-Z-bus read cycle timing
X
c/n
Do- D7
\
CE
WR
Fig. 6
•
<
From CPU
,
)
x==
I
I
Non-Z-bus write cycle timing
CPU-CPU Operation
(1) DMA operation
The LH8038 is particularly well suited to work
with a DMA in both Z-bus and non-Z-bus modes. A d~ta transfer between the LH8038 and system memory can take place durring every machin~
cycle on both sides of the LH8038 simultaneously.
(2) Message registers
Two CPUs can communicate through a dedicated
"mailbox" register without involving the 128 X 8
bit FIFO buffer. This mailbox approach is useful
for the transferring control parameters between
the interfacing devices on either side of the
LH8038 without using the FIFO buffer.
(3) Direction of data transfer operation
The Data Direction bit controls the direction of
data transfer in the FIFO buffer. This bit reads
correctly when read by either port's CPU. For example, if Port l's CPU reads Ii 0 (CPU output) in
its Data Direction bit, then Port 2's CPU reads a 1
(input to CPU) in its Data Direction bit.
390
c
\
R/W
•
CPU to I/O Operation
When Port 2 is programmed in the Interlocked
2-Wire Handshake mode or the 3-Wire Handshake
mode, and Port 1 is programmed in Z-bus or
non-Z-bus Microprocessor mode, the LH8038 interfaces a CPU and a peripheral device.
(1) Interlocked 2-wire handshake
In the Interlocked Handshake, the action of the
LH8038 must be acknowledged by the other half of
the handshake before the next action can take
place. In output mode, Port 2 does not indicate that
new data is available until the external device indicates it is ready for the data. Similarly, in input
mode, Port 2 does not indicate that it is ready for
new data until the data source (external device) indicates that the previous byte of the data is no longer available, thereby acknowledging Port 2's
acceptance of the last byte by Port 2's Ready for
Data Signal (RFD -+ High).
Z8038/Z8038A FlO Input/Output Interface Unit
(2) 3-wire handshake
The 3-Wire Handshake is designed for applications in which one output port is communicating
with many input ports simultaneously. It is essentially the same as the Interlocked Handshack, except that two signals are used to indicate that an
input port is ready for new data or that it has
accepted the present data. With 3- Wire Handshake, these lines (RFD, DAC) of many input ports
can be bussed together with open-drain drivers
and the output port knows when all of the ports are
ready and have accepted the data. This handshake
is the same handshake used in the in IEEE-488 Instruments. Since the port's direction can be changed
under software control, bidirectional IEEE-488-type
transfers can be performed.
(3) Data direction control
In CPU -to- I/O mode, the direction of data transfer can be controlled by the CPU side (Port 1)
under software control. The data direction can also
be determined by hardware control by defining the
LH8038/LH8038A
Data Direction pin of Port 2 as an input (Control
Register 3, bit 5 = 1).
For cascading purposes, the Data Direction pin
can also be defied as an output (Control Register 3,
bit 5 = 0) pin which reflects the current state of
the Data Direction bit. It can then be used to control the direction of data transfer for other
LH8038s or for external logic.
•
Programming
The programming of the LH 8038 is greatly simplified by the efficient grouping of the various operation modes in the control registers. Since all of
the control registers are read/write, the need for
maintaining thier image in system memory is eliminated. Also, the read/write feature of the registers aides in system debugging.
Each side of the LH 8038 has 16 registers. All
16 registers are used by the Port 1 side ;
Table 1 Z-FIO register address summary
Non-Z-bus
Z-bus high
Z-bus low
IRJA=O
RJA=l
Register
Control Register 0
Control Register 1
Interrupt Status Register 0
Interrupt Status Register 1
Interrupt Status Register 2
Interrupt Status Register 3
Interrupt Vector Register
Byte Count Register
Byte Count Comparsion
Register
Control Register 2 *
Control Register 3
Message Output Register
Message Input Register
Pattern Match Register
Pattern Mask Register
Data Buffer Register
x
D2
A2
AD3
AD2
D,
A,
AD2
AD,
Do
Ao
AD,
ADo
0
0
1
0
1
X
X
0
0
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
X
1
0
0
0
X
X
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
X
DT D4
ADT AD 5
ADTAD4
X
X
X
X
X
X
X
X
X
X
X
X
X
D3
A3
AD4
AD"
0
0
0
0
1
1
1
1
ADo
X
X
X
X
X
X
X
X
X
X
X
X
X
= Don't Care bit (0, 1)
* Register is only
0
Port 1 side
---.--.------~-SHARP---------
391
Z80S.8/Z8038A FlO Input/Output Interface Unit
•
LH8038/Lhl8038A
Control Register 0
Address:, 0000
(Read/Write)
I D7 I D6 I D51 D41 D3 I' D2 I DI I Do I
E~ABLED
J
(MIE)J
1
1 = INTERRUPTS
1 = DISABLE LOWER DAISY CHAIN (DLC)
1 = NO VECTOR ON INTERRUPT ( N V ) '
I'---r
Lin
I L I ~ RESET
.
' - 1 = RT.JUST.ADDRESS (RJA)
(BI) (Bo)·
}
o0 01 == NON-Z-BUS
Z-BUS CPU
,PROGRAMS
CPU
PORT 2 MODE
1 0 = 3-WIRE HS I/O
'
1 1 = INTERLOCKED HS
1 = VECTOR INCLUDES STATUS (VIS)
.
·READ-ONLY FROM
· PORT 2 SIDE
•
Control Register 1
Address: 0001
(Read/Write)
I D71 D61 D51 D41D31 D21 DI IDol
J
I
(MUST BE PROGRAMMED 0)
NOT USED
1 = FREEZE STATUS REGISTER COUNT
1 = MESSAGE MAILBOX REGISTER FULL·
JU
REQUEST/WAIT ENABLED
~L= 01 == WAIT
1 = REQUEST
1 = MESSAGE MAILBOX REGISTER UNDER
SERVICE·
1 = START DMA ON BYTE COUNT
1 = STOP DMA ON PATTERN MATCH
• READ-ONL Y BITS
•
Control Register 2*
Address: 1001
I D71 D61 Dsl D41 D31 D21 DI I Do I
(Read/Write)
I L L1 = PORT 2 SIDE ENABLED
BITS 2-7 NOT USED
MUST BE PROGRAMMED 0
1 = PORT 2 SIDE ENABLE HANDSHAKE
·THIS REGISTER READS ALL
O'S FROM PORT 2 SIDE
•
Control Register 3
Address: 1010
(Read/Write)
I D7 I D6 I D5 I D4 I D3 I D2 I DI I Do I
o~ PORT 1510E CONTROL S
CLEARJ·I
1 = PORT 2 SIDE CONTROLS
'
0= CLEAR FIFO BUFFER
0= PORT 1 SIDE CONTROLS
1 = PORT 2 SIDE CONTROLS
• READ-ONL Y BITS
··ONLY WHEN PORT 2 IS AN I/O PORT
392
I
I
1
I
Lpo RT 2SlOE-INPUT LINE· (PIN 33)"
PORT 2 SIDE-OUTPUT LINE (PIN 32)··
NOT USED (MUST BE PROGRAMMED 0)
PORT 2 SIDE-OUTPUT LINE (PIN 30)··
DATA DIRECTION BIT
1 = INPUT TO CPU
0= OUTPUT FROM CPU
ZS03S/ZS03SA FlO Input/Output Interface Unit
•
LHS03S/LHS03SA
Interrupt Status Register 0
Address: 0010
(Read/Write)
I D7 ID6 I D5 I D4 I D3 I D2 I DJ I Do I
MESSAGE INTERRUPT UNDER SERVICE (IUS}j
MESSAGE INTERRUPT ENABLE (IE)
:
MESSAGE INTERRUPT PENDING (IP):
IUS, IE, AND IP ARE WRITTEN USIN
THE FOLLOWING COMMAND:
NULL CODE 0
CLEAR IP & IUS 0
SET IUS 0
CLEAR IUS 0
SET IP 1
CLEARIP 1
SET IE 1
CLEAR IE 1
GI
•
II
[
•
NOT USED
(MUST BE PROGRAMMED 0)
:
I
0
0
1
1
0
0
1
1
I
0
1
0
1
0
1
0
1
Interrupt Status Register 1
Address: 0011
(Read/Write)
I D7 I D6 1 D5 1 D41 D31 D21 DJ 1 Do I
C~NGE
DATA
"''''''ON
UNDER
SERVI<::E (IUS)
'NTER'"",.J:
DATA DIRECTION CHANGE INTERRUPT
'
ENABLE (IE)
:
DATA DIRECTION CHANGE INTERRUPT:
PENDING (Ip)
NOT USED:
(MUST BE PROGRAMMED 0 )
IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:
NULL CODE
CLEAR IP & IUS
SET IUS
CLEAR IUS
SET IP
CLEARIP
SET IE
CLEAR IE
I
0
0
0
0
1
1
1
1
I I I I I I
:
:
:
,
:
I I
0
0
1
1
0
0
1
1
•
:
::
.'
0
1
0
1
0
1
0
1
II
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
PATTERN MATCH INTERRUPT
PENDING (I P)
PATTERN MATCH INTERRUPT
ENABLED IE)
PATTARN MATCH INTERRUPT
UNDER SERVICE (IUS)
US, IE, AND IP ARE WRITTEN USING
HE FOLLOWING ,COMMAND:
I~
0
1
0
1
0
1
0
1
L, ~ PATTERN NATC' FLAG·
NULL CODE
CLEAR IP & IUS
SET IUS
CLEAR IUS
SET IP
CLEAR IP
SET IE
CLEAR IE
*READ-ONL Y BITS
393
.. LH8038/LH8038A
Z8038/Z8038A FIO.lnput/Output Interface Unit
•
Interrupt Status Register 2
Address: 0100 (Read/Write)
lliER~
I t t~~~
~tdJ
BYTE COUNT COMPARE INTERRUPT UNDER
SERVICE (IUS ) ,
BYTE COUNT COMPARE INTERRUPT ENABLE (IE);
BYTE COUNT COMPARE INTERRUPT PENDING (IP):
,I
OVERFLOW ERROR
IUS,IE,AND IP ARE WRITTEN USIN
GI
THE FOLLOWING COMMAND:
.
:
.
NULL CODE
CLEAR IP & IUS
SET IUS
CLEAR IUS
SET IP
CLEARIP
SET IE
CLEAR IE
:
0
0
0
0
1
1
1
1
,
:
:
I
0
0
I
0
1
0
1
0
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
1
1
'
UNDERFLOW ERROR·
OR INTERRUPT PENDING (ID)
: ERR OR INTERRUPT ENABLED (IE)
R INTERRUPT UNDER SERVICE (IUS)
E,AND IP ARE WRITTEN USING
FOLLOWING COMMAND:
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
NU LL CODE
CL EAR IP & IUS
SE T IUS
CL EAR IUS
SE TIP
CL EARIP
SE TIE
CL EARlE
·READ-ONLY BITS
•
Interrupt Status Register 3
Address: 0101 (Read/Write)
~ER
I D7 I Ds I D5 I D. r D3 I D2 I Dl I Do I
IIUSl~
FUll mTERRDPr
SERVICE
FULL INTERRUPT ENABLE (IE);
FULL INTERRUPT PENDING (IP):
.
BUFFER FULL":
IUS, IE, AND IP ARE WRITTEN USI
THE FOLLOWING COMMAND
NULL CODE
CLEAR IP & IUS
SET IUS
CLEAR IUS
SET IP
CLARIP
SET IE
CLEAR IE
·READ-ONLY BITS
394
IIIIIL
:
:,
::
~GI I
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
I
0
1
0
1
0
1
0
1
:
,
:
::
.
I
0
0
0
0
1
1
1
1
I
0
0
1
1
0
0
1
1
I
0
1.
0
1
0
1
0
1
LBUFFER EMPTY·
EMPTY INTERRUPT PENDING (IP)
EMPTY INTERRUPT ENABLE (IE)
EMPTY INTERRUPT UNDER SERVICE (IUS)
IUS,IE,AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:
NULL CODE
CLEAR IP & IUS
SET IUS
CLEAR IUS
SET IP
CLEARIP
SETIE
CLEAR IE
Z8038/Z8038A FlO Input/Output Interface Unit
•
LH8038/LH8038A
Interrupt Vector Register
Address: 0110 (Read/Write)
I D7 I D6 I Ds I D. I D3 I D2 I Dl I Do I
~
I I I I
VECTOR STATUS
•
NOINTERRU PTS PENDING
BU FFER EMPTY
B UFFER FULL
OVER/UNDER FLOW ERROR
BYTE C OUNT MATCH
PAT TERN MATCH
DATA DIREC TION CHANGE
MAILB OX MESSAGE
Byte Count Register
Address: 0111 (Read Only)
I D7 I D61
Ds I D.I D3
•
I D2 I Dl I Do I
I D7 I D6 I Ds I D, I D3 I D2 I Dl I Do I
1
1
0
1
1
1
1
0
0
0
1
1
0
1
1
1
1
Pattern Match Register
I D7 I D6 I Ds I D. I D31 D2 I Dl I Do I
I I I I I I I I
STORES BYTE COMPARED WITH
BYTE IN DATA BUFFER REGISTER
•
I D7 I D6 I Ds I D. I D3 I D, I Dl I Do I
I I I I I I I I
CONTAINS VALUE COMPARED TO BYTE COUNT
REGISTER TO ISSUE INTERRUPTS ON MATCH
(BIT 7 ALWAYS 0.)
IF SET,BITS
I D7 I D6 I Ds I D.
I D3 I D2 I Dl I Do I
I I I I I I I I
STORES MESSAGE SENT TO MESSAGE
IN REGISTER ON OPPOSITE PORT OF FlO
Message Input Register
0~7
MASK BITS
0~7
IN PATTERN MATCH REGISTER.
MATCH OCCURS WHEN ALL
BITS AGREE.
NON~MASKED
Message Output Register
Address: 1011 (Read/Write)
Pattern Mask Register
Address: 1110 (Read/Write)
I I I I I I I I
•
0
Byte Count Comparison Register
Address: 1000 (Read/Write)
•
0
0
Address: 1101 (Read/Write)
REFLECTS NUMBER OF BYTES IN BUFFER
•
0
0
0
0
•
Data Buffer Register
Address: 1111 (Read/Write)
I D7 I D6 I Dsl D. I D3 I D2 I Dl I Do I
I I II I I I I
CONTAINS THE BYTE TRANSFERRED
TO OR FROM FIFO BUFFER RAM
Address: 1100 (Read Only)
I D7 I D6 I Ds I D. I D3 I D2 I Dl I Do I
I I I I I I I I
STORES MESSAGE RECEIVED FROM MESSAGE
OUT REGISTER ON OPPOSITE PORT OF CPU
-~------SHARP---------
395
LH8060
za060FIFO Buffer Unit and Expander
LH8060
Z8060 FIFO Buffer Unit and ·Expander
•
,.Description
The LH8060 First-In, First-Out (FIFO) buffer
unit consists of a 128-bit-by-8-bit memory,
bidirectional data transfer and handshake logic. The
structure of the FIFO unit is similar to that of other
available buffer units. LH8060 is a general-purpose unit; its handshake logic is compatible with that·
of other members of Z8, Z8000 family and Z8500
family.
•
Pin Connections
RFD/DAVA
I
ACKINA
2
FULL 3
EMPTY
0
A
B
4
OEA
DOH
DIH
D2B
•
Features
1. Bidirectional, asynchronous data transfer capability
2. Large 128-bit-by-8-bit buffer memory
3. Two-'wire, interlocked handshake protocol
4. 3-state data outputs
5. Wire-ORing of empty and full output for sensing of multiple-unit buffers
6. Connects any number of LH8060 in series to
form buffer of any desired length
7. Connects any number of LH8060 in parallel to
form buffer of any desired width
•
Top Vie.w
Block Diagram
Data Bus A
Ready-for· Datal
DataAvaiiable
Data
Buffer
A
Control
Logic
396
GND
128X8
RAM
Buffer
Memory I---.J\J Data
Buffer
B
Data Bus B
Z8060 FIFO Buffer Unit and Expander
•
Pin Description
Pin
Do -D 7
---
ACKIN
110
Bidirectional
3-state
Meaning
Data bus
Acknowledge input
I
Ready·for·data/data valid
0
Clear
I
DIR AlB
Data direction
I
EMPTY
Empty
0
Full
0
Output enable
I
--
RFD/DAV
--CLEAR
-
FULL
---OEA,OE B
•
LH8060
Function
Bidirectional data bus.
Active low.
Input handshake indicates that input data is valid; out·
put handshake indicates that output data has been reo
ceive by peripherals
Input handshake indicates RFD (active High) : Z-FIFO is
ready to receive data. Output handshake indicates DA V
(active low) : Output data is valid.
Active low.
When set to low, this line causes all to be cleared from
the FIFO buffer.
This line allows control of the input data direction.
When high, data is to be inputted through port B, when
low, data is to be intputted through port A.
Active high, open -drain. Indicates that the FIFO buffer
is empty
Active high, open -drain. Indicates that the FIFO buffer
is full.
Active low.
OE A, when high, causes the bus drive~or port A to
float to a high impedance level input. OE B controls the
bus drivers for port B in the same manner as OE A con·
troIs those for port A
Absolute Maximum Ratings
Parameter
Input voltage
Output voltage
Operating temperature
Storage temperature
Ratings
-0.3-+7
-0.3-+7
0-+70
-65-+150
Symbol
VIN
VOUT
Topr
T~
Unit
V
V
"C
"C
Note
1
1
Note 1: The maximum applicable voltage on any pin with respect to GND.
+SV
+SV
2S0pA
From output o----1>--,.,~...
under test
F_
"0'""
under test
Standerd test load
~
o--f
2.2kn
r
SOPF
Open-drain test load
'-~-------'--SHARP--'-----~~
397
Z8060 FIFO Buffer Unit and Expander
•
(Vcc=5V±5%, ra=0~+70"C)
DC Characteristics
Parameter
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input'leakage current
Output leakage current
Current consumption
•
Symbol
VIH
VIL
VOH
VOL
1IlL I
I IOL I
Icc
Conditions
IOH = -250 f1A
IOL = + 2mA, IOL = + 3.2mA
OA:S::VIN <2AV
•
MIN.
2
-0.3
204
TYP.
MAX.
Vcc +0.3
0.8
004,0.5
10
10
200
OA~VouT<2AV
(f=lMHz, Ta=0-+70"C)
Capacitance
Parameter
Input capacitance
Output capacitance
Bidirectional capacitance
Symbol
CIN
COUT
MIN.
Conditions
Unmeasurred pins retured
to ground
CliO
Unit
pF
pF
pF
MAX.
10
15
20
AC Characteristics
(1)
/
LH8060
Parameter
Input rise time
Input fall time
(2)
, (f=IMHz, Ta=0-+70"C)
Input pin
Symbol
tr
tf
Conditions
MAX.
100
100
Unit
ns
ns
2-wire interlocked handshake timing
No.
1
2
3
4
5
6
7
8
9
10
11
12
Symbol
TsDI (ACK)
TdACKf (RFD) .
TdRFDr (ACK)
TsDO (DAV)
TdDAVf (ACK)
ThDO (ACK)
TdACK (DAV)
ThDI (RFD)
TdRFDf (ACK)
TdACKr (RFD)
TdDAVr (ACK)
TdACKr (DA V)
13
TdACKINf (EMPTY)
14
TdACKINf (FULL)
15
16
17
18
19
ACKIN Clock Rate
TdACKINf (DAVQ
TwCLR
TdOE (DO)
TdOE (DRZ)
Parameter
Data input to ACKIN ~ to setup time
ACKIN ~ to RFD ~ delay
RFD t to ACKIN t delay
Data out to DA V t set'up time
DA V t ACKIN t delay
Data out from ACKIN t hold time
ACKIN t to DA V t delay
Data input from RFD t hold time
RFD ~ to ACKIN t delay
ACKIN t to RFD t delay
DA V t to ACKIN t delay
ACKIN t to DA V t delay
(Input) ACKIF t to EMPTY t delay,
(Output) ACKIN ~ to EMPTY ~ delay
(Input) ACKIN t to FULL t delay,
(Output) ACKIN ~ to FULL t delay
(Input or Output)
ACKIN t to DA V ~ delay
CLEAR "Low" hold.tiine to reset Z-FIFO
OE ~ to data bus driven delay
OE t to data bus float delay
Note: All timing references assume 2.0 V for a logic 1 and 0.8 V for a logic 0
398
MIN.
MIN.
0
0
25
0
0
0
0
0
0
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.0
700
0
MHz
ns
ns
ns
ns
Unit
V
V
V
V
p.A
p.A
rnA
LH8060
Z8060 FIFO Buffer Unit and Expander
•
AC Timing Diagram
DATA
RFD
EMPTY
FULL
Input timing
DATA
EMPTY
FULL
Output timing
DAV
Time from ACKIN! to DAV !
CLEAR
INPUT
\11"-------_®_....JI}/
OE
DATA OUT
Output enable and clear
.-.-.-.--.-.-..--SHARP -..-...----------
399
LH8060
Z8060:FIFO Buffer Unit and Expander
•
Interlocked 2-Wire Handshake
The LH8060 uses interlocked handshake operations for data trasfer. In interlocked handshake operation, the action must be acknowledged by the
other half of the handshake before the nextactton
can occur. The following describs the handshake
timing in input and output modes.
(1) Input mode
,.
In an Input Handshake mode, RFD (output) and
ACKIN (input) are used as the handshake control
lines. Unless the FIFO buffer is full, RFD is set
High and signals to the peripherals involved that
the FIFO buffer is ready to receive data. When the
acknowledge signal ACKIN from the external device is set Low, the LH8060 takes the input data
into the buffer and sets RFD Low to signal to the
peripherals that the input signal has been received.
This process is repeated until the FIFO is full,
RFD is kept low.
DATA IN
=x
Valid data X:::==::XValid dataL
This contorol feature allows the LH8060, with
no external logic, to directly interface with port of:
eZ8
'
eZ-CIO
ez-uPC
eZ-FIO
e Another FIFO
•. Resetting and Clearing the FI FO
The CLEAR input signal is used to reset and clear
the LH8060 FIFO. A Low level on this input clears
all data from the FIFO buffer and disallows any
data transfer.
•
Bidirectional Transfer Control
The LH8060 has bidirectional data transfer
capability ~nder control of the DIR AlB input.
When DIR AlB is set Low, data transfers are made
from Port A to Port B.
Setting DIR AlB High reverses the handshake
assignments and the direction of transfer.
ACKIN-
Table 1 Bidirectional control function table
RFD
-
DATA OUTJ Valid data C=X:Valid data><=::
ACKIN
DAV--"""""' - -_ _oJ
Fig. 2 2-wire interlocked handshake timing
(output)
0
1
•
Output mode
~,output handshake mode, DA V (output) and
ACKIN are used as the control lines. If the LH8060
has data in the FIFO buffer and if ACKIN is high
(indicating that the external device is ready to receive data), it sets DA V Low to signal to the external device that the output data is available.
.When the external device sets ACKIN low to indicate that it has received the data, LH8060 sets
DA V back to a high level. In response, the external
device sets ACKIN high to request the LH8060 for
the next data. This process repeats till the FIFO
buffer becomes empty. when it becomes empty,
DAVis kept high.
Port B
handshake
Output
Input
transfer
A to B
Bto A
Empty and Full Operation
The EMPTY and FULL. output lines can be
wire-ORed with the EMPTY and FULL lines of
other LH8060s and LH8038s. This capability enables the user to determine the emptylfull status of
a buffer consisting of multiple FIFOs, FIOs, or a
combination of both.
•
(2)
Port A
handshake
Input
Output
DIR AlB
Fig. 1 2-wire interlocked handshake timing
(input)
Interconnection EXl;I.mple
Fig. 3 illustrates a simplified block diagram
showing the manner iIi which LH8060s can be interconnected to extend an LH8038 buffer.
Table 2 Signals EMPTY and FULL operation
table
Number of
bytes in. FIFO
0
1-127
128
EMPTY
FULL
High
Low
Low
Low
Low
High
----....-~.-.---.---SHARP,-.-.-.- ......... - - - - - - - -
400.
LH8060
Z8060 FIFO Buffer Unit and Expander
•
Output Enable Operation
Table 3
The FIFO provides a separate Output Enable
(OE) signal for each port of the buffer. An OE output is valid only when its port is in the Output
Handshake mode. The control of this output function is sh~n in Table 3-Signal OE operates with
lines DIR AlB.
DIR AlB
DEA
Output control function table
DEA
0
X
0
0
X
1
1
0
X
1
1
X
Note:
Function
Disable port A output
Enable port B output .
Disable port A output
Enable port B output
Enable port A output
Disable port B output
Disable port A output
Disable port B output
X=Don't care
SYSTEM FULL
FULL
EMPTY
DATA
A BUS"
PORT 2
of
Z8038
V
I
EMPTY
FULL
"-
1'\
K
v/
~
-
'"
ACKINA
FULL
EMPTY
/
K=>
DATA BUS
LH8060
FIFO
LH8060
FIFO
---
R FD/DAV
DATA BUS
SYSTEM EMPTY
I
--
---
RFD/DAVB
ACKINA
RFD/DAVs
HANDSHAKE
} SIGNALS
ACKIN
OE
CLEAR
RFD/DAVA
Dr
OEB
OEA
CLEAR
RFD/DAVA
ACKINB
DIR AlB
1
nr
ACKINs
OEB
OEA
CLEAR
1
OUTPUT CONTROL
DIR AlB
SYSTEM CLEAR
SYSTEM DIRECTION
DA TA DIR
Fig. 3
Connection diagram
401
LH8071
Serial Parallel Combination Controller
LH8071
•
Serial Parallel Combination Controller
Description'
The LH8071 (SPCC71) is a peripheral device for
general purpose microcomputers, with control
functions for RS232C interface and Centronics interface, within a single LSI chip.
The LH8071 pr<;>vides a serial port for transferring data in asynchronous mode and also an 8-bit
parallel port with handshaking function as a Centronics interface.
The LH8071 has 24 commands for controlling
these ports. The commands not only control the operation of RS232C terminal units and printers, but
handle various utilities (e.g., code conversion) necessary for these units. Accordingly, the CPU needs
. merely to specify an operation through the command, thus significantly reducing the CPU's load in
handling 110 units through the program, and eventually reducing the amount of memory needed for
storing the program.
The LH8071 controls the peripheral unit control
lines (e.g., RTS and CTS of RS232C interface)
according to the status of the units, instead of by
software control from the CPU. Consequently, the
system designer can configure the interface merely
by connecting buffer devices and connectors.
In conclusion, the LH8071 not only easily implements the RS232C interface and Centronics interface, but achieves superior performance and space
reduction.
•
•
Pin Connections
o
RxD
TxD
DTR
CTS
DCD
RTS
SLCT
INPUT PRIME
FAULT
ACKNLG
WAIT
DATA STROBE
AD7
DATAs
AD6
DATA7
AD5
DATA6
AD.
DATA5
AD3
DATA.
AD2
DATA3
ADI
DATA2
ADo
DATAl
Top View
Features
1. Asynchronous data transfer serial port
• RS232C interface can easily' be realized
• Programmable data: format and Baud rate
,
2. Printer control parallel port
• Centronics interface can easily be realized
3. Data transfer and conversion functions by command
• 24 commands
4. Data conversion function
• Serial-parallel conversion
• Binary-ASCII conversion
• Intel hex, format acceptable for data input!
output
402
5. 128-byte data transfer buffer
• Useful for the serial port and parallel port
6. Z-bus interface
7. 40-pin dual-in-line package
8. Single + 5V power supply
Serial Parallel Combination Controller
•
LH8071
Block Diagram
Data Bus
Address! Data Bus
"'"
·2
o
Address Strobe
Internal
Control Logic
9
Interruput Request 5
Interruput Acknow ledge 6
Interruput Enable In 4
Interruput Enable Out 3
!;
'"
u"
Buffer
128
Bytes
-~----"'-'---SHARP'-'---'---'----
403
Seriat Parallel 'Combination Controller
•
LH8071
Pin Description
Pin
AD o -AD 7
AS
Meaning
lIO
Bidirectional
3 state
Address/ data bus
Address strobe
I
Data strobe
I
R/W
Read/write
I
CS
WAIT
Chip select
Wait
-
DS
Function
Multiplexedsystem address/data bus as address.
Active low. Fetch iiiformation on address/data bus as
address.
Active low. Transact information on address/data bus
as data.
High at reading. Output contents of internal register
onto address/data bus; Low at writing. Fetch data on
address/ data bus.
Active low. Chip selection signal
Active low, open-drain. Used to synchronize with CPU.
Active low, open-drain. Indicate interrupt request to
CPU.
Active low. Indicate interrupt acknowledge cycle.
Active high. Used to form interrupt priority arbitration
loop circuit (daisy chain).
Active high. Used to form daisy chain.
Output data
Active low. Indicate settlement of data.
Active high. Indicate printer in operation.
Active high. Acknowledge signal from printer.
Active low. Indicate printer inoperable.
Active low. Printer initializing signal.
Active low. Printer selection signal.
Receiving data line.
Transmitting data line.
Active low. Indicate readiness for data transmission.
Active low. Indicate data transmission is possible.
Active low. Data transmission request signal.
Active low. Indicate data reception is possible.
Single-phase clock, need not be same as CPU clock.
-
Interrupt request
INTACK
Interrupt acknowledge
I
lEI
Interrupt enable input
I
lEO
Interrupt enable output
Output data
Data strobe
Busy
Acknowledge
Fault
Prime input
Select
Recei ved data
Transmitted data
Transmission request
Transmission enable
Data terminal ready
Reception enable
Clock
a
a
a
--
INT
DATAI-DATA g
DATA STROBE
BUSY
ACKNLG
FAULT
INPUT PRIME
SLCT
RxD
TxD
RTS
CTS
DTR
DCD
PCLK
•
I
a
a
I
I
I
a
I
I
a
a
I
a
I
I
Absolute Maximum Ratings
Parameter
Input voltage *
Output voltage *
Operating temperature
Storage temperature
*
Symbol
V IN
VOliT
Toor
T st•
Unit
V
V
Ratings
-0.3-+7
-0.3-+7
0-+70
-65-+150
The maximum applicable voltage on any pin except for
VBB
"C
"C
with respect to GND.
+5V
2.2kO
"""I--"
Output terminal o---1~....
under test
Standard tellt load
- - - - - - - - - - - - - - - - - - - - - S H A R P - . . . . - , - ........ . - . - - - - -
404
·Serial Parallel Combination Controller
•
(Vcc=5V±5%. Ta=0-+70"C)
DC Characteristics
Symbol
VCH
VCL
VIH
V IL
VOH
VOL
I IlL I
I 10L I
Icc
Parameter
Clock input high voltage
Clock input low voltage
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Current consumption
•
LH8071
Conditions
MIN.
2.4
-0.3
2
-0.3
2.4
10H= -250 pA
10L =2mA
0:5::V IN :5::5.25V
TYP.
MAX.
Vcc
0.8
Vcc
0.8
0.4
10
10
250
0~VIN~5.25V
Unit
V
V
V
V
V
V
pA
pA
rnA
AC Characteristics
(Vcc=5V±5%. Ta=0-+70"C)
(1) CPU interface timing
No.
1
2
3
4
5
6
7
8
9
10
Symbol
TrC
TwCh
TfC
TwCl
TpC
TsCS(AS)
ThCS(AS)
TsA(AS)
ThA(AS)
TwAS
11
TdDS(DR)
12
TdDS(DRz)
13
14
15
TdAS(DS)
TdDS(AS)
ThDW(DS)
16
TdDS(DR)
17
18
19
20
21
22
23
24
TdAz(DS)
TwOS
TsRWR(DS)
TsRWW(OS)
TsDW(OSf)
TdAS(W)
ThWR(OS)
TsDR(W)
Parameter
Clock rise time
DSClock pulse high width
Clock fall time
Clock pulse low width
Clock period
CS setup time to AS t
CS hold time from AS t
Address setup time to AS t
Address hold time from AS t
AS low pulse width
Delay time from OS t to invalid
readout data
Delay time from DS t to readout
data floating
Delay time from AS t to OS ~
Delay time from OS t to AS ~
Written data hold time from OS t
Delay time from OS ~ to readout
data settlement
Delay time from address floating to DS
OS low pulse width
R/W high (read) setup time to OS ~
R/W low (write) setup time to OS !
Written data setup time to OS l
Delay time from AS t to WAIT !
R/W hold time from OS t
Time from valid readout data to WAIT
MIN.
MAX.
20
105
20
105
250
0
60
30
50
70
!
ns
2
2095
ns
ns
ns
1
ns
3
1.95
t
1
1
1
1
70
0
390
100
0
30
60
0
Note
51~
I~
-
ns
0
60
50
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t indicates rising edge. ~ indicates falling edge. The reference voltage levels for timing measurement are 2.0 volts for
'high'; O.S volts for 'low'.
Note 1: This does not apply to the interrupt acknowledge operation.
Note 2: The Max. value of TdAS (DS) does not apply to the interrupt acknowledge operation,
Note 3: The delay time depends on the status of LHS071 at the time of access by CPU.
405
I
I
L:.H8071
Serial Parallel Combination Controller
PCLK
ADo-AD7
CPU (read)
AS
R/W
(write)
R/W
(read)
ADo-AD7
CPU (write) ----.....f"l-t~..;...",,-~).---~=_+_----...:f,-
CPU interface timing
(2)
No.
Interrupt acknowledge timing
25
26
Symbol
TsIA(AS)
ThIA(AS)
27
TdAS(DSA)
28
TdDSA(DR)
29
30
31
32
33
34
TwDSA
TdAS(IEO)
TdIEIf(IEO)
TsIEI(DSA)
TdDS(INT)
ThIEI(DS)
Parameter
INT ACK setup time to AS t
INT ACK low hold time from AS t
Delay time from AS t to DS ~
(acknowledge)
Delay time from DS ~ (acknowledge)
to vector settlement
DS (acknowledge) low pulse width
Delay time from AS t to lEO
Delay time from IEI to lEO
lEI setup time to DS ~ (acknowledge)
Delay time from DS ~ to INT
lEI hold time from DS t
MIN.
0
250
MAX.
Unit
ns
ns
940
ns
360
475
290
120
150
500
100
Note
ns
ns
ns
ns
ns
ns
ns
Interrupt acknowledge timing
---'-~~------SHARP----'-----'---
406
LH8071
Serial Parallel Combination Controller
(3)
Reset timing
No.
Symbol
35
TdRDQ(AS)
36
TdWRQ(DS)
37
TwRES
Note 4:
Parameter
Delay time from DS t
(for suppressing reset) to AS ~
Delay time from AS t
(for suppressing reset) to DS ~
Minimum low width of AS and DS
(for setting)
MIN.
MAX.
Unit
Note
40
ns
50
ns
250
ns
4
MAX.
Unit
Note
19000
ns
5
MIN.
MAX.
18000
Unit
ns
Note
13000
The internal reset signal lags by 112 to 2 clocks behind external reset conditions.
Reset timing
(4) Serial port timing
No.
Symbol
38
TdTxC(TxD)
Parameter
Delay time from sending clock transition
to output data transition
MIN.
Note 5: Applies to all baud rates (110-9800 B) serial port timing
TxC
/
TxD
Serial port timing
(5)
No.
Parallel port timing
39
Symbol
TdACK(D)
40
TdD(DSTR)
41
TwDSTR
Parameter
Time from ACKNLG ~ to data output
Time from data output to
DATA STROBE ~
DATA STROBE pulse width
6000
ns
6000
ns
ACKNLG
DATAl
\
. DATAs
DATA STROBK
Parallel port timing
----------SHARP--.--------~
407
Sericil Parallel Combination Controller
•
LH8071
Registers
Table 1
The LH8071 has the following registers which
can be accessed externally (from CPU).
e Master interrupt control register (MIC)
e Data indirect address register (DIND)
eData status command registers (DSCO, DSCl,
DSC2, DSC3, DSC4, DSC5 and DSC8)
Table 1 shows the register addresses assigned to
these registers.
The master interrupt control register (MIC) is
used to control the interrupt operation (see Fig. 2).
Writing into the MIC register falls into two
groups.
Group 2 uses the write code shown in Table 2.
DSC31 D71 D6
I D51
D41 D31 D21 D1
[
-~-~-~-~
Register adpress
Register Register address
X XOOOOOX
DSCO
X X00001 X
DSC1
X XOO010X
DSC2
XXOOO11X
DSC3
X ):(00100 X
DSC4
Register Register address
XX00101X
DSC5
X X01000X
DSC8
X X10101X
DIND
X X11110X
MIC
Note: A15- A6 is decoded and applied to cs, so that the location in
the input/output address space is determined. Bits marked by 'x'
are underfined.
I Dol
Co 1 Buffer area over
1 0 Input characters are other than 0-F
(Intel format only) ,
1 1 Check - sum error
0 1 Printer not select
,
1 0 Printer paper empty
(requires external circuit)
1 1 Printer fault
L -_ _ _ _ _ _ _
Transter error
' - - - - - - - - - - Limit error
' - - - - - - - - - - - - Parity error
'---------~----Illegal command
Fig. 1 Error flag (DSC3)
MIC
I IE I IUS I IP I
IDLC I ICST I
TTT
T
~Command execution start
Lower chaining prohibited
_
' - - - - - - - - - - - Interrupt holding
' - - - - - - - - - - - - - Interrupt under service
Interrupt enabled
Fi'g. 2 Master interrupt control register
Table 2 MIC register write code
D7
0
0
0
,0
1
1
1
1
408
Group 2
D6
0
0
1
1
0
0
1
1
1
0
0
1
Do
X
0
0
0
0
0
0
0
0
1
0
0
D5
0
1
0
1
0
Group
D2
X
0
0
I
0
Function
Writing to Do and D2
Reset IP (D5) and IUS (D6)
Set IUS (D6)
Reset IUS (D6)
Set IP (D5)
Reset IP (D5)
Set IE (D7)
Reset IE (D7)
LH8071
Serial Parallel Combination Controller
•
°
Programming
mand. Command is used in specifying serial data
format using DSC2 (Fig. 3).
The result of command execution is indicated on
DSCO and DSC3. DSC3 indicates error status as
show in Fig. 1. DSC8 is used as a buffer register
after command 22 or 23 is executed.
Tables 3 and 4 show command functions versus
registers.
Use the registers, DSCO, DSCl, DSC2, DSC3,
DSC4, DSC5, and DSC8, to specify operation mode.
The 24 types of commands are made valid by first
writing a value corresponding to the desired com·
mand number into DSCO, then setting the CST bit
on MIC. The registers DSCl, DSC2, DSC4, and
DSC5 are used to specify parameters for each comOSC2
1
I 07 I 061 051 041 031 021 OJ I 00 I
-,---,
LPu'"m'"
o : even parity
1 : odd parity
Number of data bits
o : 7 bits
1 : 8 bits
' - - - - - - - B a u d rate (see Note)
o 0 0 : nOB
o 0 1 : 150 B
010:300B
011:600B
1 0 0 : 1200B
lOl:2400B
110:4800B
111:9600B
Number of stop bits of transmission
o : 1 stop bit
1 : 2 stop bit
L -_ _ _ _ _ _ _ _ _ _ _ Interrupt mode
L -_ _ _ _ _ _ _ _ _
o : Interrupt
L -_ _ _ _ _ _ _ _ _ _ _ _
Note:
enabled
1 : Interrupt disabled
Echo back
o : Echo back mode
Baud rate at PCLK = 4.0MHz
1 : Echo back disable
Fig. 3
Serial data format (DSC2)
.-----.---~--SHARP.-..-..-~.----
409
Serial Parallel Combination Controller
Table 3
~
Code
DSCO
0
OOH
1
01 H
2
02 H
Number of
putput byte
3
03 H
Number of
putput byte
4
04 H
5
05 H
Number of
bytes of
block transfer
6
06 H
Number of
putput byte!
7
07 H
Number of
putput byte!
Cornman
DSCI
LH8071
Command function and writing register contents
Parameter
DSC4
DSC2
Transfer
format and
operating mode
DSC5
Output serial-input data
to Centronics printer until
the stop character arrives
Output seriaI-input data
to Centronics printer.
Load address Load address
high order byte (low order byte)
Output buffer area
contents to serial port
in Intel format.
Read Intel format data on
serial port and store in
buffer area.
Initialize block transfer
between master CPU and
buffer
Output data in buffer area
via serial port.
Output data in buffer area
to printer.
-,
.".
8
08 H
Number of
output byte!
9
09 H
Number of
output byte!
10
OA H
Number of
output byte!
11
OB H
12
OCH
13
OD H
14
OE H
15
OFH
Number of
output byte
Output
starting
address
Output
starting
address
Output
starting
address
Output
starting
address
Display
Display
address
address
(High order) (Low order)
Display
Display
address
address
(High order) (Low order)
Number of
Output
input bytes character
Output
character
Number of
putput byte!
Load
address
Remarks
Sepcify transfer format .
and operating mode.
Stop
character
Output
starting
address
Output
starting
address
. Function
Load
address
Convert binary data in
buffer area into ASCII and
area.
Convert binary data in
buffer area into ASCII and
output via serial port.
Convert binary data in
buffer area into ASCII,
and output to printer.
Convert binary data in
buffer area into ASCII,
and output to printer.
Read ASCII data on serial
port, and store in buffer
area.
Read Intel format data on
serial port and store in
buffer area.
Read ASCII data on serial
port until arrival of CR
eode.
Convert data in buffer
area into Intel format and
output via serial port.
Stop character is
specified by DSC2.
Operation stops
upon detection of
Control C (hex 03).
Address information
of data is appended.
\
Operation stops
upon detection of
Control C (hex 03).
Operation stops
upon detection
of Control C (hex
03).
Address information
of data is appended.
Address information
of data is appended.
Used when reader is
connected to serial
port.
After CR reception,
CR and LF codes are
sent out via
serial port.
Used when a puncher is connected to
serial port.
- - - - . - . . . - - - - - - ! ? H A R P .-~------------410
Serial Parallel Combination Controller
Comman
~
Code
DSCO
16
10 H
17
llH
18
12H
19
13 H
20
14H
21
15 H
22
16 H
.,
23
17H
DSCI
Parameter
DSC2
DSC4
Number of
Output
input bytes character
Number of
putput bytes
Output
starting
address
LH8071
DSC5
Function
Read binary data on serial
port into buffer area for
storage.
Output data in buffer
area via serial ports.
Output null codes via
serial port.
Output EOF in Intel
format ( :OOOOOOOlFF)
via serial port.
Output null codes via
serial port.
Output EOF in Intel
format ( :OOOOOOOlFF)
via serial port.
Read I-byte data on serial
port.
Output data written in
DSC8 by CPU via serial
port.
Remarks
Used when a reader
is connected to serial
port.
Used when a puncher
is connected to serial
port. Operation stops
upon detection of
hex 03.
256 null codes
outputted.
Used when a puncher
is connected to serial
port.
Used when a puncher
is connected to serial
port.
Data is stored in
DSC8.
Data needs to be set
in DSC8 prior to execution (high order
byte)
--------------SHARP .---------------..
411
Serial Parallel Combination Controller
Table 4
LH8071
Register contents after command execution (readout register)
Parameter
OOH
01 H
02 H
03 H
Code
DSCO
2*
80 H
81H
82H
83 H
3*
C;OH
CI H
C2 H
C3 H
4
04 H
84 H
C4 H
5
6
7
8
9
10
11
12
05 H
06 H
07 H
08 H
09 H
OA H
OB H
OC H
. S5 H
86 H
87 H
88 H
89 H
8AH
8B H
8C H
C5 H
C6H
C7 H
C8 H
C9 H
CA H
CB H
CC H
13
OD H
8D H
CD H
14
OE H
8E H
CE H
Error status
15
16
17
18
19
20
21
22
23
OF H
10 H
llH
12H
13 H
14H
15 H
16 H
17H
8F H
90 H
91H
92Ii
93 H
94 H
95 H
96 H
97 11
CF H
DOH
DIH
D2H
D3 H
D4H
D5 H
D6 H
D7H
Error
Error
Error
Error
Error
Error
Error
Error
Error
'S
Command
0
1
2
3
Note 1
Note 2
Note 3
412
1*
*:
*:
*:
DSCI
DSC2
Error
Error
Error
Error
Number of inputted
bytes pluse hex 20
status
status
status
status
DSC5
flag
Hag
flag
flag
Error status flag
Error
Error
Error
Error
Error
Error
Error
Error
Number of inputted
bytes plus hex 20
DSC4
DSC3
Load address
Load address
(High order byte) (Low order byte)
status flag
status flag
status flag
status fl'ag
status flag
status flag
status flag
status flag
Load Adress
Load address
(High order byte) (Low order byte)
Number of inputteq
flag
byte pulse hex 20
flag
flag
flag
flag
flag
flag
flag
flag
flag
Error status flag
status
status
status
status
status
status
status
status
status
1
V,alue before command execution (command code value)
Value upon normal completion of command execution.
2
3
Value upon abnormal completion (error) of command execution.
These are common to all commands.
.
For error status flag value, see Fig. l.
If FAULT input becomes low (printer error) during command execution, LH8071 suspends operation until FAULT returns to high
(error recovery). At this time, DSCO has bit 6 set and bit 7 reset.
Serial Parallel Combination Controller
LH8072
•
LH8072
Serial Parallel Combination Controller
Description
•
Pin Connections
The LH80n (SPCCn) is a peripheral device for
general purpose microcomputer systems to perform
asynchronous serial data transfers and control of
Centronics compatible printers.
It supports full duplex asynchronous serial data
transfers. The transfer conditions such as the baud
rate and character length can be set by the
program. Further, it is equipped with a control I/O
terminal for simple organization of the various types
of modem interfaces. The Receive Buffer has a double buffer structure so that the master CPU can easily perform reading and writing of data.
A printer control I/O terminal is available for
easy connection to any printer which is Centronics
compatible. A handshake line and control for
other I/O lines is supported. A 128-byte printer
data buffer memory having an FIFO structure is
provided within the LH80n. Efficient use of the
printer unit by the master CPU is made possible
with this buffer.
In this way, the LH80n peripheral device for
Z8000 family, was developed to efficiently perform
serial data transfer and printer output control
within a compact pacil:age. It is suitable for use in
small systems such as personal computers which
use printer units, RS232C terminal units and modem units.
•
o
TxD
DTR
CTS
DCD
INTACK
DS
R/W
6
RTS
NC
INPUT PRIME
AS
BUSY
CS
FAULT
GND
WAIT
ACKNLG
DATA STROBE
AD,
DATA,
AD6
DATA,
AD;
DATA"
AD,
DATA"
AD3
DATA.
AD,
DATA:.
AD!
DATA,
ADo
DATA.
Top View
Features
1. Asynchronous Full Duplex Data Transfer
• Character length of 5""8 bits
· 1 or 2 stop bits
· No parity bit or odd/even parity
• F.alse start bit or rejection (rejects spike
noise in the mark line to prevent malfunction.)
• Full duplex
• Transmit buffer has double buffer structure.
• Receive buffer has FIFO structure.
• Error detection function, Parity error detection, Framing error detection, and Overrun
error detection
· Baud rates: 75, 110, 150,300,600,1200,
2400, 4800 baud selectable
2. Centronics Compatible Printer Control
RxD
3.
4.
5.
6.
· Furnishes printer interface signals compatible with Centronics specifications
· Built-in handshake function for data output
· Internal buffer: 128-byte FIFO structure
• Error detection: Printer fault error/Paper
empty error
Vector Interrupt
· Able to generate an interrupt on various
condition such as Transmit Buffer empty,
validity of received character, and printer
Output Buffer empty.
• Interrupt vectors for Transmit, Receive,
Printer and Error detection can be set individually.
Single + 5V power supply
Z-bus interface
40-pin dual-in-line package
..-.-----.--....-SHARP-------·-.-~--
413
LH8072
Serial Parallel Combination Controller
•
Block Diagram
Data Bus
Interface
Address! Data Bus
Address Strobe 9
Data Strobe 7
Chip Select 10
Read!Write 8
Wait 12
Interrupt Request
Interrupt Acknowledge
Interrupt Enable In
Interrupt Enable Out
Internal
Control Logic
Print
FIFO
128 Bytes
Data Bus
ERR
MSR
CTLTxS
RxS
PRS
TxB
RxB
PRB
6
---------SHARP
414
-.....---....-.~----.-
Serial Parallel Combination Controller
•
Pin Description
Pin
ADo-AD?
-
AS
Signal
Address/ data blls
110
Bidirectional
3-state
Address strobe
I
Data strobe
I
R/W
Read /write
I
CS
WAIT
INT
Chip select
wait
I
0
Interrupt request
0
INTACK
Interrupt acknowledge
I
lEI
Interrupt enable input
I
lEO
DATAI-DATA s
DATA STROBE
BUSY
ACKNLG
FAULT
INPUT PRIME
RxD
TxD
RTS
CTS
DTR
DCD
PCLK
Interrupt enable output
Output data
Data strobe
Busy
Acknowledge
Fault
Prime input
Receivived data
Transmitted data
Transmission request
Transmission enable
Data terminal ready
Reception enable
Clock
0
0
0
I
I
I
0
I
0
0
I
0
I
I
-
DS
-
•
LH8072
Function
Multiplexed system address/data bus
Active low. Fetch information on address/data bus as
address.
Active low. Transact information on address/data bus
as data.
High at reading. Output contents of internal register
onto address/data bus; Low at writing. Fetch data on
address/data bus.
Active low. Chip selection signal
Active low, open·drain. Used to synchronize with CPU.
Active low, open-drain. Indicate interrupt request to
. CPU.
Active low. Indicate interrupt acknowledge cycle.
Active high. Used to form interupt priority arbitration
loop circuit (daisy chain).
Active high. Used to form daisy chain.
Output data
Active low. Indicate settlement of data.
Active high. Indicate printer in operation.
Active high. Acknowledge signal from printer.
Active low. Indicate printer inoperable.
Active low. Printer initializing signal.
Receiving data line.
Transmitting data line.
Active low. Indicate readiness for data transmission.
Active low. Indicate data transmission is possible.
Active low. Data transmission request signal.
Active low. Indicate data reception is possible.
Signal·phase clock; need not be same as CPU clock.
Absolute Maximum Ratings
Parameter
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
VIN
VOUT
Topr
Tst~
Ratings
-0.3-+0.7
-0.3-+0.7
0-+70
-65-+150
*The maximum applicable voltage on any pin with respect to GND.
Unit
V
V
t
t
+5V
2.2kO
Output terminal o---+--~r-MI--'"
under test
Standard test load
415
/
Serial Parallel Combination Controller
tH8072
DC Characteristics
•
Parometer
Clock input high voltage
Clock input low voltage
Input high voltage,
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Current consumption
•
(Vee=5V±5%, Ta=0-+70"C)
Symbol
VeH
VeL
VlH
VIL
VOH
VOL
I IlL I
I IOL I
Icc
Condition,
MIN.
2.4
-0.3
2.0
-0.3
2.4
IoH =-250 pA
IOL=+2.0mA
MAX.
Vee
0.8
Vee
0.8
Unit
V
V
V
V
V
V
pA
pA
mA
0.4
10
10
250
0~VIN~5.25V
, 0~VIN~5.25V
Note
AC Characteristics
(1) 'CPU interface timing
No.
1
2
3
4
5
6
7
8
9
10
Symbol
TrC
TwCh
TfC
TwCI
TpC
TsCS (AS)
ThCS (AS)
TsA (AS)
ThA (AS)
TwAS
11
TdDS (DR)
12
TdDS (DRz)
i3
14
15
TdAS (DS)
TdDS (AS)
ThDW (DS)
16
17
18
19
20
21
22
23
24
I
/
TdDS (DR)
TdAz (DS)
TwDS
TsRWR (DS)
TsRWW (DS)
TsDW (DSf)
TdAS (W)
ThRW (DS)
TsDR (W)
Parameter
Clock rise time
Clock pulse width, high
Clock fall time
Clock pulse width, low
Clock period ,
CS setup time to AS t
CS hold time from AS t
Address setup time to AS t
Address hold time from AS t
AS low pulse width
Delay time from DS t to invalid
readout data
Delay time from DS t to readout
data fioating
Delay time from AS t to DS !
Delay time from DS t to AS !,
Written data hold time from DS t
Delay time from DS ! to readout
data settlement
Delay time from address floating to DS
DS low pulse width
R/W high (read) setup time to DS !
R/W low (write) setup time to DS !
Written data setup time to DS !
Delay time from AS t to WAIT !
R/W hold time from DS t
Time from vaild readout data to WAIT
MIN.
MAX.
20
105
20
105
250
0
60
30
50
70
Note
1
1
1
1
fiS
ns
0
70
60
50
30
Unit
ns
ns
ns
ns
ns
ns,
ns
ns
ns
2095
ns
2
ns
fiS
ns
1
3
0
390
100
,
0
30
195
60
0
ns
ns
ns
ns
ns
ns
ns
ns
f indicates rising edge, ! indicates falling edge. The reference voltage levels for timing measurement are 2.0 volts
'high' ; 0:8 volt for 'low'.
Note1: This does not apply to the interupt acknowledge operation.
Note 2: The Max. value of TdAS (DS) does not apply to the interrUpt acknowledge operation.
Note 3: The 'delay time depends on the status of LH8072 at the time of access by CPU.
. . . - - - - - - - - - - - - - - - - S H A R P - - - - - - - - - - - - - ..........- -
416
Serial Parallel Combination Controller
LH8072
PCLK
ADo-AD7
CPU (read)
DS
R/W
(write)
R/W
(read) _ _ _---::,---++-_--'
ADo-AD7
CPU (write)
CPU interface timing
(2)
No.
Interrupt acknowledge timing
25
26
Symbol
TsIA (AS)
ThIA (AS)
27
TdAS (DSA)
28
TdDSA (DR)
29
30
31
32
33
34
TwDSA
TdAS (lEO)
TdIElf (lEO)
TsIEI (DSA)
TdDS (INT)·
ThlEI (DS)
Parameter
INT ACK setup time to AS t
INT ACK low hold time from AS t
Delay time from AS t to DS ~
(acknowledge)
Delay time from D~ ~
(acknowledgge) to vector settlement
DS (acknowledgge) low pulse width
Delay time from AS t to lEO
Delay time from lEI to lEO
lEI setup time to DS ~ (acknowledge)
Delay time from DS ~ to INT
lEI hold time from DS t
0
250
Unit
ns
ns
940
ns
MIN.
MAX.
360
475
290
120
150
500
100
Note
ns
ns
ns
ns
ns
ns
ns
Interrupt acknowledge timing
-'-~~-~--SHARP'--'-"-'-------
417
LH8072
Serial Parallel Combination Controller
(3) Serial port timing
No.
Symbol
38
TdTxC (TxD)
Parameter
Delay time from sending clock transition
to output data transistion
MIN.
MAX.
Unit
Note
35000
ns
4
MAX.
Unit
ns
Note
Note 4:· Applies to all baud rates (75-4800 B)
TxC
/
TxD
Serial port timing
(4)
Parallel port timing
No.
39
Symbol
TaACK (D)
40
TdD (DSTR)
41
TwDSTR
MIN.
24000
Parameter
Time from ACKNLG l to data output
Time from data output to
DATA STROBE l
DAT A STROBE pulse width
6500
ns
6500
ns
,
\
AKCNLG
DATAl
I
DATAs
DATA STROBE
Parallel port timing
•
Registers
The LH80n uses 64 bytes in the system input!
output address space. Within this area, 14 bytes
are assigned to the I-byte registers (including data
buffer, status, register, control register, etc.) which
can directly be accessed by master CPU.
Table 1 lists the registers used for data transaction with the maser CPU and their addresses.
Table 1
Address
X XOOOOOX
XXOOO01X
X XOO010X
X XOOOllX
X X00100X
XX00101X
X XOOllOX
XXOOlllX
X XOIOOOX
XXOIOOIX
X X01010X
X XOIOll X
X XOllOOX
X X 11l10X
Register input/output address
Register
Error status register(ERR)
Mode setting register (MSR)
Control register (CTL)
Transmission status register (TxS)
Reception status register (RxS)
Printer status register (PRS)
Transmission buffer (TxB)
Reception buffer (RxB)
Printer buffer (PRB)
Transmission interrupt vector
register (Tx V)
Reception interrupt vector register
(RxV)
Printer interrupt vector register
(PRV)
Error interrupt vector register (ERV)
Master interrupt control register
(MIC)
Note: AIs-A6 is decoded and applied to CS, so that the location
in the input/output address space is determined. Bits
marked by 'x' are undefined .
....-.-----------SHARP---------.-.
418
LH8072
Serial Parallel Combination Controller
•
Programming
Note: Registers marked by. can be set or revised even
during the operation of LH8072.
The LH80n has 14 read/write registers which
can be accessed directly by the master CPU.
(1) Initialization
The device is initialized in accordance with the
following procedure.
(1) Following power-on reset, or master reset
by software, set the mode register is programmed for character format, baud rate,
stop bit and parity mode. Subsequently data
required by control register· and interrupt
vector registers· (transmission, reception
and printer error interrupt vector registers)
is programmed.
(2) Clear the error status register.
(3) Wait until the data transfer enable bit in the
master interrupt control register is set to
"I", making the LH80n operable.
In case interrupt is used, the above polling operation is unnecessary. When transmission, reception and printer output become enable, interupt request is forwarded to the master CPU, indicating
that the LH80n has become operable.
(2) Data inpuVoutput
Data transfer between LH80n and CPU is carried out in accordance with the following procedure.
(1) Poll the status registers (transmission, reception and printer status register) and wait
until they become "1". In case interrupt
(transmission, reception and printer interrupt) is used, interrupt occurs as soon as
the value of each status register becomes
"I", and polling is not necessary.
(2) After the status register has been set to "I"
(or after interrupt has occurred), begin data
transfer via the buffers (transmission, reception and printer buffers).
(3) Clear the status register. If the above operation is implemented using an interrupt
routine, the interrupt-under-service (IUS)
bit must be reset immediately before the end
of each interupt routine.
I D7 I D61 D5 I D. I D3 I D2 I D, I Do I
II
I L~:;:,~=
L -_ _ _ _ _ _ _ _
Frammg error
Overrun error
Printer fault
' - - - - - - - - - - - Paper out
' - - - - - - - - - - - - - Unused
' - - - - - - - - - - - - - - - Master reset
Fig. 1
Error status register (ERR)
I D7 I D6 I D5 I D.I D3 I D2 I D, I Do I
m
o
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
5
6
7
8
bits / character
bits / character
bits / character
bits / character
75B
nOB
150B
300B
600B
1200B
2400B
4800B
Stop-bit-2/Stop-bit -1
Odd -parity/Even -parity
With - parity/Without -parity
Fig. 2
Mode setting register (MSR)
'-~--'------SHARP--'----------~
419
LH8072
Serial Parallel Combination Controller
I Drl DG I Ds I D.I D31,D21 DI I Do I
I DrlDGI DsID.1 D31 Dzi DI I Do I
~
I"L=~~~,
~Transmission
IL-.---,----Reception
.
Fig. 8
enabled
Reception enabled
Printer o~tput ,enabled'
'----------Transmission interrupt enabled
'-----------Reception interrupt enabled
' - - - - - - - - - - - - P r i n t e r interrupt enabled
Fig. 3
I<------printer output data
Fig. 9
Control register (CTL)
I Dr
LTransmission buffer empty
Printer buffer (PRB)
I DGI Ds I D4 I D3 I Dzi DI I Do I
I
--------0
~.
Fig. 4
Reception buffer (RxB)
I Drl D61 Dsl D. I D3 I Dzi DI I Do I
I Dr I DG I Ds I D4 I D3 I Dz I D I I Do I
I
data
.
L-.---Transmission interrupt vector
Transmission status register (TxS)
Fig. 10 Transmission Interrupt vector register
I Dr I DGI Dsl D41 D31 Dzi Dd
Dol
(TxV)
I Drl D6 I Dsl ~41 D31 Dz I DI I Do'
I
LReception character valid
'-----0
Fig. 5
~1----RecePtion interrupt vector
Reception status register (RxS)
Fig. 11
I Dr I D6 I Ds I D41 D31 Dz I DI I Do ,
, I
Reception interrupt vector register (RxV)
I Drl D61 Dsl D41 D31 Dzi
Lprinter buffer empty
DI I
Dol
~'--------o
Fig. 6
I'-----Printer interrupt vector
Printer status re~ister (PRS)
Fig, 12
I Dr I D61 Dsl D41 D31 Dzi Dl I Dol
Printer interrupt register (PRV)
I Dr I D61 Dsl D41 D3 I Dz I DI I Do "
I
L-I------·Transmission data
'-----~-Error
Fig. 7 Transmission buffer (TxB)
Fig. 13
interrupt vector
Error interrupt vector register (ERV)
. I D7 I D61 Dsl D41 D31 D2 I DI I Do I
enable(MlE)~
Master interrupt Atreadmg±u
Interrupt under service(IUS)
I '
. Interrupt pending(IP)
:I
:'
,
:
:
:
At writing
!
:
0
0
1
1
1
0
1
0
1 ' 1
1
1
0
l
0
0
0
0
Fig. 14
420
1
0
1
0
1
0
1
I
' .
~L"
',""0 at wrItmg
..
~ U~defmedat readm,g:
.
DIsabled lower chaIning (DLC)
Data transfer enable ( reading only )
Undefined at reading/"O" at writing
Writing to Do, DI, Dz, D3 and D4
Reset IP a~d IUS
Set IUS
Reset IUS
Set IP
Reset IP
Set MIE
Reset MIE
Master interrupt control register (MIC)
LH8073
General Purpose Interface Bus Controller
LH8073
•
General Purpose Interface Bus Controller
Description
The LH8073 (GPIB73) is a microcomputer peripheral device used to control interface buses conforming to IEEE Std. 488-1978* (will be termed
simply "GPIB") The GPIB is used extensively as a
linkage bus between data gathering instrumentation
devices and a microcomputer system.
The LH8073 incorporates three functions of
talker, listener and controller, all integrated in one
chip. Using this device, the GPIB interface can be
provided for various instrumentation equipment,
personal computers and office computers.
The LH8073 is applicable to a CPU bus where
address and data are multiplexed. There is a complementary device LH8573 which is applicable for
a CPU bus where address and data are not multiplexed.
•
Pin Connections
+5V
1
40
SRQ/REN IN
PCLK
2
39
REN/SRQ OT
lEO
3
lNT
5
lNTACK
6
DS
7
R/W
8
WAIT
12
*Note : The standard disclosed in IEEE Std.
488-1978 "IEEE Standard Digital Interface for Programmable Instrumentation"
issued by IEEE, U.S.A.
Top View
•
Features
1. Built-in talker, listener and controller. Talker
function, listener function and controller function are integrated in one chip.
2. Built-in buffer memory. Talker or listener can
use 160-byte on-chip buffer.
3. EOI automatic transmission. Upon detection of
the last byte of or EOS in talker mode, EOI signal is transmitted automatically.
4. EOS automatic detection. Upon reception of
EOS in listener mode, the CPU is informed.
5. Built-in timer. The bus time-out period for
handshaking can be set by the on-chip timer in
the range of 200 p.s -12 ms at 50 p.s interval.
6. Interrupt function. Daisy-chain type interrupt
arbitration facility is provided, allowing vectored interrupt to CPU.
7. Z-bus interface.
421
LH8073
General Purpose Interface Bus Controller
Block Diagram
•
Address/
Data Bus
GPm
Bus
Da~
ir
I
l
IFC IN
IFC OT
SRQ/RENIN
9 REN/SRQOT
CONTI
Data Strobe
Read/Write'
Address Strobe
Chip Select
Wait
Interrupt Enable Out
Interrupt Enable In
Interrupt Request
Interrupt Acknowledge
TE
3
4
5
6
ATN
DAV
NDAC
NRFD
EOI
CONT2
+5V 1
PCLK 2
GND
,
,
--~------SHARP'-''''''-'-'''''''-'---
422
Multi Task Support Processor
LH8075
•
Multi Task Support Processor
Description
The LH8075 (MTSP 7 5 ) is the stand alone type
multitask support processor providing multitask
capabilities for any simple microcomputer system.
The concept of this multitask processing is similar
to a conventional real time OS (operating system).
The devices perform task management (creating,
deleting, etc.) independently of the master CPU, and
carry out multi task processing for systems bus
with arbitrary CPU architectures merely by connecting to the system bus.
User's programs are scheduled on a priority or
time-sliced basis. Tasks are switched by an interrupt caused by the LH8075, and commands are
given to the LH8075 by writing parameters and
command numbers in the specified register in the
LH8075.
•
LH8075
Features
1. Task management
· Up to eight tasks can be controlled concurrently. By using the task creating and deleting technique, a maximum of 255 tasks can
be handled.
· Tasks can be controlled on a priority basis by
the assignment of 255 priority levels.
2. Inter-task communication
· Inter-task communication is possible using the
"mail box" provided within the LH8075.
· Inter-task synchronization is possible using
the "mail box".
3. Built-in timer
· Timers with ranges from lOms to 255 hours
can be used for time-sliced processes and
checking I/O wait time.
• These times can be set independently for each
task.
4. Bulit-in clock. Time (hours, minutes and
seconds) can be set and read out.
5. 20-bit general-purpose I/O port
· Two 8-bit ports operable in bit input/output
• 2-bit input ports and 2-bit output ports.
· Tasks can be resumed using the 2-bit input
ports.
6. Memory assignment
• Working memory areas can be assigned to
each task.
•
Pin Connections
a
P30
P33
P27
P26
P2s
INTACK
6
P2.
P23
P2,
P2l
P20
P3l
WAIT
P3,
AD7
Pb
AD6
Ph
ADs'
Ph
AD.
Pl.
AD3
PI:.
AD,
PI.
AD!
PIl
ADo
Plo
Top View
--------..-.---SHARP ------.--..-.---423
Multi, Task Support Processor
•
, LH8075
Block Diagram
Port 1
Data Bus
Address! Data Bus
TeBl
Data Strobe
Read! W ri te
Address Strobe
Chip Select
Internal
Control Logic
MBXl
7
8
Port .2
Data Bus
9
10
I nterrupt Request
Interrupt Acknowledge
Interrupt Enable Out
Interrupt Enable In
0
6
3
4
SPB2
•
Pin Description
Pin
AD o-AD 7
-
AS
Meaning
Address/ data bus
I/O
Bidirectional
3-state
Address strobe
I
Data strobe
I
R/W
Read/write
I
CS
WAIT
Chip select
Wait
I
0
Interrupt request
0
IN TACK
Interrupt acknowledge
I
lEI
Interrupt enable input
I
lEO
Pl o-P1 7
P2 o-P2 7
P3 0 -P3 3
PCLK
Interrupt enable output
I/O port lines
I/O port lines
I/O port lines
Clock
0
110
I/O
110
I
-
DS
-
-INt
424
Function
Multiplexed system address/data bus.
Active low. Fetch information on address!data ,bus as
address.
Active low. Transact information on address/data bus
as data.
High at reading. Output contents of internal register on
address/ data bus ; Low at writing.
Fetch data on address/data bus.
Active low. Chip selection signal
Active low, open-drain. Used to synchronize CPU.
Active low, open·drain. Indicate interrupt request to
CPU.
Active low. Indicate interrupt acknowledge cycle
Active high. Used to form interrupt priority arbitration
loop circuit (daisy chain).
Active high. Used to form daisy chain.
Parallel input/output
Parallel input/output
Parallel input/output
Single· phase clock, need not be same as CPU clock.
Multi Task Support Processor
•
LH8075
+SV
Absolute Maximum Ratings
Parameter
Input voltage
Output voltage
Operating temperature
Storage temperature
•
Symbol
VIN
VOUT
:r
opr
T"2 .
Ratings
-0.3-+7
-0.3-+7
0-+70
-65-+150
2.2kO
V
Output pin
under test o--~-'--I~'"
V
"C
"C
SOpF
Standard test load 1
I
(Vee=5V±5%, GND=OV, Ta=0-+70"C)
DC Characteristics
Parameter
Clock input high voltage
Clock input low voltage
Input high voltage
Input low voltage
Output low voltage
Output low voltage
Inptt leakage current
Output leakage current
Current consumption
•
Unit
Symbol
VeH
VeL
VIH •
V IL
VOH
VOL
I IlL I
I IOL I
lee
Conditions
MIN.
2.4
-0.3
2
-0.3
2.4
IoH =-250,uA
IOL =2mA
MAX.
Vee
0.8
Vee
0.8
0.4
10
10
250
0~VIN~5.25V
0;;;;V IN ;;;;5.25V
Unit
V
V
V
V
V
V
,uA
,uA
rnA
AC Characteristics'
(1)
Master CPU interface timing
No.
1
2
3
4
5
6
7
8
9
10
Symbol
TrC
TwCh
TfC
TwCl
TpC
TsCS (AS)
ThCS (AS)
TsA (AS)
ThA (AS)
TwAS
11
TdDS (DR)
12
TdDS (DRz)
13
14
15
TdAS (DS)
TdDS (AS)
ThDW (DS)
16
TdDS (DR)
17
18
19
20
21
22
23
24
TdAz (DS)
TwDS
TsRWR (DS)
TsRWW (DS)
TsDW (DSf)
TdAS(W)
ThRW (DS)
TsDR (W)
Parameter
Clock rise time
Clock pulse width, high
Clock fall time
Clock pulse width, low
Clock period
CS setup time to AS t
CS hold time from AS t
Address setup time to AS t
Address hold time from AS t
AS low pulse width
Delay time from DS t to invalid
readout data
Delay time from DS t to readout
data floating
Delay time from AS t to DS l
Delay time from DS t to AS l
Written data hold time from DS f
Delay time from DS l to readout data
settlement
Delay time from address floating to DS
DS low pulse width
R/W high (read) setup time to DS l
R/W low (write) setup time to DS l
Written data setup time to DS l
Delay time from AS t to WAIT l
R/W hold time from DS t
Time from valid readout data to WAIT
MIN.
MAX.
20
105
20
105
250
0
60
30
50
70
l
ns
2
2095
ns
ns
ns
1
ns
3
195
t
1
1
1
1
70
0
390
100
0
30
60
0
Note
ns
0
60
50
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
The reference voltage levels for timing measurement are 2.0 volts for 'high' ; O.S volt for ·Iow'. All output paramaters are
measured under the stated load conditions.
Note 1: This does not apply to the interrupt acknowledge operation.
Note 2: The Max. value of TdAS (DS) does not to the interrupt acknowledge operation.
Note 3: The delay time depends on the status of LHS075 at the time of access by master CPU.
425
Multi Task Support Processor
LH8075
PCLK
ADo-AD7
Master CPU
(read)
AS
R/W
(writ!!)
R/W
(read)
ADo-AD7
Master CPU
(write)
WAIT
Master CPU interface timing
'-'~~----~-SHARP
426
.-..-.-.-.-.------
................... -............. -....... - . - . -....... - . - . -......
Multi Task Support Processor
LH8075
.-~
I
(2)
Interrupt acknowledge timing
No.
25
26
Symbol
TsIA (AS)
ThlA (AS)
27
TdAS (DSA)
28
TdDSA (DR)
29
30
31
32
33
34
TwDSA
TdAS (lEO)
TdIEif (lEO)
TsIEI (DSA)
TdDS (INT)
ThIEl (DS)
Parameter
INT ACK setup time to AS t
INT ACK low hold time from AS t
Delay time from AS t to DS !
(acknowledge)
Delay time from DS !
(acknowledge) to vector settlement
DS (acknowledge low pulse width
Delay time from AS t to lEO
Delay time from lEI to lEO
lEI setup time to DS ! (acknowledge)
Delay time from DS ! to INT t
IEI hold time from DS t
0
250
Unit
ns
ns
940
ns
MIN.
MAX.
360
475
290
120
150
500
100
ns
ns
ns
ns
ns
ns
ns
Interrupt acknowledge timing
(3)
Reset timing
No.
Symbol
1
TdRDQ (WR)
2
TdWRQ (RD)
3
TwRES
Parameter Delay time from DS t
(for suppressing reset) to AS !
Delay time from AS t
(for suppressing reset) to DS !
Minimum low width of AS and DS
(for resetting)
MIN.
MAX.
Unit
40
ns
50
ns
250
ns
Note
1
Note 1: The internal reset signal lags 112 to 2 clocks behind external reset conditions.
Reset timing
~--------------SHA.RP
------------.-....
427
Ml..\lti :Task Support Processor
(4)
No.
1
2
3
LH8075
Handshaking timing
Parameter
Symbol
TsDI (DA)
ThDA(DI)
TwDA
MIN.
0
230
175
20
0
Data setup time
Data hold time
DAV width
--
4
TdDAL(RY)
Delay, time from DA V low to RDY
5
TdDAH(RY)
Delay time from DAV high to RDY
6
7
TdDO(DA)
TdRY(DA)
Delay time from data output to ,DA V
Delay time from RDY to DA V
MAX.
175
--
150
0
50
0
205
Unit
ns
ns'
ns
ns
ns
ns
ns
ns
ns
. Note 1: Input handshaking
Note 2: Measured under the stated load conditions.
Note 3: Output handshaking
Data input
DAV input
RDYoutput
'---''--_ _ _ _ _..;;r
Port read
Input handshaking timing
Data output
,DAVoutput
__~>t
:--r
Valid output data
-®--I
Port
om.
1
1I--@~~
! \ >or?I®J. . .~. . .-
RDY input
.....
__ ...
Serial port timing
•
Basic Specifications
Table 1
LH8075 basic spec,ifications
Performance
Parameter
Task control function
Number of tasks registered
Number of tasks controlled
simultaneously
Priority level
Mail box
Unit clock
Scheduling
Memory allo,cation
Clock function
Parallel data input/output function
428
Max. 255; task number: hex 01-FF
Max. 8
Max. 255; priority level: hex 01-FF
Max. 5; mail box number: hex 01-05
10 ms
Priority order or time division; Task is switched by interrupt from LH8075.
User's RAM is segmented in units of hex 100 bytes; Arbitrary area ranging
hex OOOO-FFFF' can be controlled.
Time (hour, minute, second) setting and readout
Two '8-bit I/O ports and 'one 4-bit I/O port
Note
1,2
1,2
2,3
1,2
2,3
2
2
LH8075
Multi Task Support Processor
•
Teble 2
Registers
The LH8075 has the following registers which
can be accessed externally (from CPU).
(1) Task control
CPIO (Command parameter register)
This register writes the writing parameter previous to command writing. The readout parameter
is placed in CPIO upon completion of command execution.
CNST(Commandl status register)
This register is used to write a command. Execution information of executed command is placed
in CNST upon completion of command execution.
SPN1, SPN2 (New task stack pointer registers)
At occurrence of interrupt for task switching,
execution starting address information for the new
task is placed 'in this register.
SPB1, SPB2 (Old task stack pointer registers)
At occurrence of interrupt for task switching,
execution end address information for the executed
task is written in this register.
MIC (Master CPU interrupt control register)
Interrupt related parameters including interrupt
enable (IE), interrupt pending (IP) and interruptunder-service (IUS) bits are set or reset in this
register.
(2) 1/0 ports
P1D, P2P, P3D (port 1, 2, 3 data registers)
These registers are used to transact data via
port 1, port 2, and port 3.
Table 2 lists the register addresses.
Register address
Register
Address
PID
XXOOO01X
X XOO010X
P2D
P3D
X XOOOllX
CNST
SPN1
SPN2
X XOOllOX
X XOOlll X
X X01000X
SPB1
X X01001X
SPB2
X X01010X
CPIO
MIC
X X 10101 X
X X11110X
Note 1: Bits marked by 'x' may be either '0' or '1'.
Note 2: LH8075 uses 64 input/output address locations.
~
TIMR
PEND
.
~
~
T~
{.SM
~~~~ ~__~
~~g~T
~
TSPO
TCRT
TOEL ~
TOEL
GD
(1)
Task in execution releases CPU.
(2)
0
o
o
TSPO
(Wait)
./
~TOEL
Higher ranking ta,sk becomes ready.
Time-up by time division
TNXT
Fig. 1 Task status
MIC
I D, I 061 051 0.1 031 021 01 I 00 I
-~--~TTT L Undefined at reading/"O" at writing
~isabled
_
lower chaining (OLC)
o (unused)
Non -vector (NV)
\ - - - - - - - - - - I n t e r r u p t pending (IP)
! - - + - - - - - - - - - Interrupt under service (IUS)
,!----'--+----------Interrupt enable (IE)
,
At writing· :,
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Writing to 02 and O.
Reset IP and IUS
Set IUS
Reset IUS
Set IP
Reset IP
Set IE
IP, IUS and IE bits are set or reset' by writing in
Reset IE
these codes_
*:
Fig. 2
MIC bit configuration
....-...-----.-...---SHARP~---..-.-..--
429
Multi Task Support Processor
•
LH8075
Programming
The following describes the task control procedure using LH8075.
(1) Initialization
(1) The LH8075eauses interrupt for task switching
'However, in order to process, a separate interrupt processing routine must be prepared.
(2) Each task is provided with a stack area.
Table 3
Order
1
2
3
4
5
Item
Vector
RAM table
6
7
Task starting address and initial values for all registers are written at the top of each stack area.
(3) LH8075 is initialized. Table 3 lists the initialization information to be written in LH8075.
(4) When necessary, the clock is set and the
port mode is specified.
(5) Initialization completed. To transfer control
from the initialization routine to a task, the task execution command (TSTR) must be executed.
System information registered at initialization
Contents
LH8075 interrupt vector for task switching
User RAM start address (high order byte)
User RAM end address (high order byte)
Task number (hex 01-FF)
Priority level (hex 01 - FF)
Task
Task stack pointer (high order or low order byte)
1
Task stack pointer (low order or high order byte
Task table
4n
4n+1
4n+2
4n+3
Task
n
(2) Command execution
Table 4 lists the commands of LH8075, and
Table 5 lists the command execution information.
In writing commands into LH8075 the following
data entry procedure applies.
(1) Write parameters needed in writing command into CPIO in the order shown in Table 4.
Commands with blank parameter field in Table 4
do not require writing
(2) Write the command number in CNST.
(3) It is necessary to confirm the completion of
command execution by polling D7 in CNST (D 7 becomes "I" upon completion of command execution).
430
Task number (hex 01-FF)
Priority level (hex 01 - FF)
Task stack pointer (high order or low order byte)
Task stack pointer (low order or high order byte)
For commands without readout parameter, procedure is completed and the following procedures are
unnecessary. Commands with readout parameter
(CGET, MALC and PEND) further require the following procedures.
(4) When D6=1 in CNST (indicating the readout
parameter is prepared in CPIO), parameter is read
out from ePIO.
(5) Upon completion of parameter readout,
PRME command must be executed to notify
LH8075 of the parameter readout completion.
(6) Wait until CNST D7 becomes "I" to confirm
the completion of command execution.
Multi Task Support Processor
LH8075
Table 4 Command table
No.
OOH
OlH
Command name
INIT
TSTR
02 H
TCRT
Function
LH8075 initialization
Termination of LH8075
initialination and start of
task execution
Task creation
03 H
04 H
05 H
TDEL
TRSM
TSPD
Task deletion
Task resumption
Task suspension
06 H
TPRI
Task priority change
07 11
TSLI
Task time-slicing process
08 H
TNXK
09 H
TIMR
Swapping of task during
time-sliced execution
Timer setting
OAII
CSET
Clock setting
OBII
CGET
Clock readout
OCII
MALC
Memory allocation
0011
OEII
MREL
POST
Memory release
Message transmission
OFII
PEND
Message reception
10H
PMOO
Port mode setting
PRME
End of parameter readout
1111
Note 1:
Note 2:
Note 3:
Writing parameter
1. Total number of tasks
Readout parameter
1. Task number
2. Priority level
3. SP (high order or low
order byte)
4. SP (low order or high
order byte)
1. Task number
1. Task number
1. Task number
2. control switch
1.
2.
1.
2.
3.
Remarks
See
paragraph(1)
Task number
New priority
Priority
Time base
Count
See
paragraph(2)
1. control code
2. Count
See
paragraph(3)
1. Hour
2. Minute
3. Second
1. Number of memory
blocks required
1. Mail box number
2. Message data 1
3. Message data 2
4. Message data 3
5. Message data 4
I.-Mail box number
1.
2.
3.
1.
Hour
Minute
Second
Allocated memory
address
*
*
See
paragraph(4)
1.
2.
3.
4.
Message
Message
Message
Message
data
data
data
data
1
2
3
4
1. Port-l mode
2. Port-2 mode
3. Port-3 mode
*
See
paragraph(5)
*'
Commands marked by require PRME command execution at parameter readout completion.
Numerals given in 'writing parameter' and 'readout parameter' indicate the order of writing and reading.
Numerals in 'remarks' indicate the reference number of supplementary explanation .
.------..-.--SHARP.-..-.-.-..-.---
431
. LH8075
MultiTask Support Prcx:iessor·
Table 5
Command
name
IN IT
0
OOH
1
2
TSTR
02 H
TCRT
Normal termination
Task number or priority setting error
Double specification of same task
number
3 Total number of tasks equal to o or
larger than 8, Initialized information
error, RAM table error
0 Normal termination
3 Initial information not yet set
0
1
2
3
03 H
04 H
TDEL
TRSM
0
1
2
4
0
1
2
4
5
05H
TSPD
0
1
2
3
5
•
Command
name
TPRI
06 H
0
1
2
07 H
TSLI
0
1
5
08 H TNXT 0
09 H TIMR 0
1
Code
Execution
Code
01 H
Command el(ecution information
Normal termination
Ta~k number or priority setting error
Already created
Control tasks more than 8
Normal termination
Task number error
Specified task not yet created
Specify self
Normal termination
Task number error
Specified task not yet created
Specify self
Specification of task in ready s,tatus
Normal termination
Task number or control switch number error
Specified task not yet created
Control switch setting error
Specification· of task ill halt staus
OA H
CSET
OB H
OC H
CGET
MALC
OD H
MREL
OE H
POST
OF H
PEND
10 H
PMOD
PRME
11H
Execution
Normal termination
Task number or priority setting error
Specified task not yet created
Normal termination .
Ptiority error or data error
Cancellation without setting
Normal termination
Normal termination
Data error
5 Cancellation without setting
8 Resuming by TRSM
0 Normal termination
1 Data error
0 Normal termination
0 Normal termination
6 Allocation disabled
0 Normal termination
5 Memory not yet allocated
0 Normal termination
1 Mail box number error or message
data error
7 Mail box busy
0 Normal termination
1 Mail box number error
8 TRSM command issued by other task
or time out
0 Normal termination
0 Normal termination
Supplement for writing parameter
(1) 2. Controi switch
I 07 1061 05 1O. 103 102 10, 100 1
IL-------Control switch
o : Bring to complete stop
1 : Halt until external event 1 (fall of P 3,)
2 : Halt until external event 2 (fall of P 30)
(2)
2.
Time base
1071 06 1Ds 1o. 103 1D2 10, 1Do I
1
...- - - - - - T i m e base
o : Hour
1 : Minute
2 : Second
3 : 1/100 second
4 or above : Cancellation
432
_-_..
..... - . -..... -..... -...
Multi Task Support Processor
.-.-.(3)
LH8075
:.-...-...-...-...-...-
1. Control code
0: Hour
1 : Minute
2 : Second
3 : 1/100 second
4 or above : Cancellation
' - - - - - - - - Unused
' - - - - - - - - - - - - W a i t switch
0: Wait
1 : Time out period setting only
2.
Count
I 0, I 06 I Os I o. I 03 I 02 I01 I 00 I
LI------Count (Count multiplied by time base
becomes setup time)
(4)
2.
Only in message data I, '0' is not allowed.
(5)
1.
Port-1 mode
Ir-0-,""T,-0-6
0-s-',""'0-."T,-0-3...-,o-,""T,-O-IT",0-0"""',
T",
...
I - - - - - - P o r t - l bit I/O definition
(1 for input; 0 for output)
2.
Port-2 mode
Ir o-,""T,-0-6T"10-s-'l-o-."T,-03-,ro-,""T,-o-IT"lo-o-',
LI------Port-2 bit I/O definition
(1 for input; 0 for output)
3.
Port-3 mode
IrO-i""T,-O-6T"I-os-'I-0-."TI-O-alr 0-,""T1-0-1T"10-o"",
~~~~TTTLP~'" p.,h-,.n/"oo-'_
Port 1 : Push -pull/open -drain
P31 : External event 1 input
P 30 : External event 2 input
' - - - - - - - - Port -1 handshaking
( P31=OAVI/ROYl)
P32=ROYI/OAVI
' - - - - - - - - - - - Port -2 handshaking
( P30=OAV2/ROY2)
P33 = ROY2/0AV2
'------------Unused
--,-------SHARP-.....-,--------433
........... -.............................. -.......... ................. .
LH8090/LH8090A
Z8090/Z8090A Universal Peripheral Controller
.-.-
LH8090/LH8090A
~
,
,
za0901Z8090A Universal
Peripheral Controller
•
Description
The LH8090 Universal Peripheral Controller
(UPC) is an intelligent peripheral controller: for c\istributed processing applications. The LH8090
unburdens the host processor by assuming tasks
traditionally done by the host (or by added hardware), such as performing arithmetic; translating
or formatting data, and controlling I/O devices.
Based on the 28 microcomputer architecture and
instruction set, the LH8090 contains 2K bytes of
internal program ROM, a 256-byte register file,
three 8-bitI/0 ports, and two counter/timers.
The LH8090 offers fast execution time; an effective use of memory; and sophisticated interrupt, 1/
0, and bit manipulation. Using a powerful and extensive instruction set combined with an efficient
internal addressing scheme, the LH8090 speeds
program execution and efficiently packs program
code into the on-chip ROM.
•
Features
1. Complete slave microcomputer, for distributed
processing 2- bus use
2. Unmatched power of 28 architecture and instruction set
3. Three prpgrammable I/O ports, two with optional 2-Wire Handshake'
4. Six levels of priority interrupts from eight
sources: six from external sources and two
from internal sources
5. Two programmable 8-bit counter/timers each
with a 6-bit prescaler. Counter/Timer TO is
driven by an internal source, and Counter/
Timer Tl can be driven by internal or external
sources. Both counter/timers are independent of program execution
6. 256-byte register file, accessible. by both the
master CPU and LH8090, as allocated in the
LH8090 program
7. 2K bytes of on-chip ROM for efficiency and
versatility
434
•
Pin Connections
o
IEOI P37 3
IEIIP30 4
INT IP35
P31
P3.
P27
P2.
5
iN'l'ACK I P32 6
P2.
DS
7
P23
R/W
8
P22
P21
P20
WAIT
P3.
AD7
AD.
Pl.
AD5
PIs
AD.
Pl.
AD3
PIa
AD2
P12
AD1
ADo
Plo
Top View
LH8090/{'H8090A
Z8090/Z8090A Universal Peripheral Controller
•
Block Diagram
Program
Memory
2KX8
Address/
Data Bus
Read.' Write
Address Strobe
Chip Select
Wait
Port 1
8
9
IRP
l'ort2
Register
File
256X8
15=
•
Pin Description
Pin
ADo-AD 7
Meaning
. Address data bus
I/O
Bidirectional
Address strobe
I
Data strobe
I
R/W
Read/write
I
CS
Chip select
I
Wait
0
I/O port lines
I/O port lines
I/O port lines
I/O
I/O
I/O
-
AS
-
DS
-
-WAIT
Pl o-P1 7
P2 o-P2 7
P3 0 -P3 7
PCKL
Clock
I
Function
Multiplexed system address/data bus .
Active low. Causes information on the address/data bus
to be fatched as address
Active low. Causes information on the address/data bus
to be sent/received as data
A high level indicates a read cycle : Data is output from
the internal register to the address/data bus. A low
level indicates a write cycle : Data is fetched from the
address/ data bus.
Active low, Chip select signal.
Active low, open-drain. For synchronizaion with the
CPU.
Parallel I/O
Parallel I/O
Parallel I/O (4-bit input, 4-bit output)
Signal-phase clock, not need to be related to the CPU
clock.
-~'-'---""'--SHARP'-'-'--~----
435
Z8090/Z8090A Universal Peripheral Controller
__Nl_._'-'-''-'-:''_''__
'-'-:''-~
•
~''''''~
Absolute Maximum Ratings
Parameter
Input voltage·
Output voltage·
Operating temperature
Symbol
VIN
VOUT
Topr
Tstg
Storage temperature
*
LH8090/LH8090A
___
Ratings
-0.3-+7.0
-0.3-+7.6
0-+70
-65-+150
Unit
V
V
°C
°C
The maximum applicable voltage on any pin except for VBB, with respect to GNO.
•
Standared Test Conditions
The characteristics below apply for the following standard test conditions, unless otherwise
noted. All volta~es are referenced to GND. Positive
current flows into the reference pin. Standard con·
ditions are as followes .
4.75V~Vcc~5.25V
Vss=GND=OV
O°C::;;;Ta;£ +70°C
+5V
+5V
2.2kO
18kO
From output O----, and MR/W/IACK of the device for 64-pin development, IOH=100 Il A and
10L
Unit Note
V
V
V
V
V
1
V
1
pA
pA
rnA
1mA
---------SHARP-----.--------'.436
Z8090/Z8090A Universal Peripheral Controller
•
AC Characteristics
(1)
Master CPU interface timing
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Symbol
TrC
TwCh
TfC
TwC1
TpC
TsCS(AS)
ThCS(AS)
TsA(AS)
ThA(AS)
TwAS
TdOS(OR)
TdOs(ORz)
TdAS(OS)
TdOS(AS)
ThOW(OS)
TdOS(OR)
TdAz(OS)
TwOS
TsRWR(OS)
TsRWW(OS)
TsOW(OSf)
TdAS(W)
ThRW(OS)
TsOR(W)
Parameter
Clock rise time
Clock high width
Clock fall time
Clock low width
Clock period
to AS t setup time
CS to AS t hold time
Address to AS t setup time
Address to AS t hold time
AS low width
OS t to read data not valid
OS t to read data float delay
AS t OS ~ delay
OS t AS ~ delay
Write data to OS t hold time
OS ~ to read data valid delay
Address float to OS delay
OS low width
R/W(read) to OS ~ setup time
R/W(write) to OS ~ setup time
W rite data to OS ~ setup time
AS t to W AIT ~ valid delay
R/W to OS t hold time
Read data valid to WAIT t
cs
LH8090/LH8090A
LH8090
MIN.
MAX.
20
105
1855
20
105
1855
250
2000
0
60
30
50
70
0
70
2095
60
50
30
LH8090A
MIN.
MAX.
15
70
1855
10
70
1855
165
2000
0
40
10
30
50
0
45
40
2095
35
20
0
390
100
0
30
0
250
80
0
20
195
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
2
1
3
us
160
40
0
Unit Note
ns
ns
ns
ns
Note : The timing characteristics given reference 2.0V as High and O.8V as Low.
All output AC parameters use test load l.
Note 1:
Parameter does apply to interrupt acknowledge transactions.
Note 2:
The maximum value for TdAS (DS) does not apply to interrupt acknowledge transcations.
Note 3:
This parameter is dependent on the state of UPC at the time of master CPU access.
'-~--------SHARP----~------
437
Z8090/Z8090A Universal Peripheral Controller
PCLK
ADo-AD7
MASTER CUP
READ
AS
R/W
(WRITE)
R/W
(READ)
ADo-AD7
MASTER CPU
WRITE
WAIT
Master CPU interface timing
438
. LH8090/LH8090A
Z8090/Z8090A Universal Peripheral Controller
(2)
LH8090/LH8090A
Interrupt acknowledge timing
Parameter
No.
Symbol
25
26
27
28
29
30
31
32
33
34
TsIA(AS)
ThIA(AS)
TdAS(DSA)
TdDSA(DR)
TwDSA
TdAS(IEO)
TdIElf(IEO)
TsIEI(DSA)
TdDS(INT)
ThlEI(DS)
INTACK to AS t setup time
INTACK to AS t hold time
AS t to DS ! (acknowledge) delay
DS ! (acknowledge) to read data valid delay
DS ! (acknowledge) low width
AS t to lEO delay
lEI to lEO delay
lEI to DS ! (acknowledge) setup time
DS ! to INT delay
lEI to DS t hold time
ADo-AD7
=:x
Undefined
LH8090
MIK
MAX.
0
250
940
360
475
290
120
150
500
100
LH8090A
MIN.
MAX.
0
250
200
180
250
250
100
120
500
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
)>-------- "f-----J
INTACK
lEI
lEO
Interrupt acknowledge timing
439
Z8090/Z80gpA ~niver5al Peripheral Controller
(3)
No.
LH8090/LH8090A
Handshake timing
1
2
3
TsDi(DA)
ThDA(DI)
TwDA
Data in setup time
Data in hold time
Data available width
4
TdDAL(RY)
Data available low to ready delay time
5
TdDAH(RY)
Data available high to ready delay time
6
TdDO(DA)
TdRY(DA)
Data out to data available delay time
Ready to data available delay time
7
Note 1: Input handshake
LH8090
LH8090A
MIN.
MAX.. MIN.
MAX.
0
0
230
230
175
175
20
175
20
175
0
0
.150
150
0
0
50
50
0
205
205
0
Parameter
Symbol
Note 2: Test load 1
Unit
Note
ns
.ns
ns
ns
ns
ns
ns
ns
ns
1,2
1,2
2,3
1,2
2,3
2
2
Note 3: ·Output handshake
DATA IN
DAV INPUT
RDY OUTPUT
Port read
Input handshake timing
DATA OUT
r
-~t=®
Data out valid
DAV OUTPUT
RDY INPUT
\
\
~--@---->.:\,~
"
Output handshake timing
----~.-.----.---SHARP
440
.--.-.---.----
Z8090/Z8090AUniversai
•
Pe~ipheral
Controller
Functional Description
(1) Address space
On the 40-pin UPC, all address space is committed to on-chip memory. There are 2048 bytes
of mask programmed ROM and 256 bytes of
register file. I/O is memory-mapped to three
registers in the register file. Only the Protopack
version of the UPC can access external program
memory. See the section entitled "Special Configurations" for a complete description of the
Protopack version.
Program memory: Fig. 1 is a map of the 2K
on-chip program ROM. The first 12 bytes of
program memory are reserved for the LH8590
interrupt vectors. In the RAM version addresses OCH through 2FH are reserved for on-chip
ROM.
Register file: This 256-byte file includes
three I/O port registers (1-3H), 234 generalpurpose registers (6H-EFH), and 19 control,
Status and special I/O registers (OH,4H,5H and
FO-FFH). The functions and mnemonics assigned
to these register address locations are shown in
Fig. 1. Of the 256 UPC registers, 19 can be directly accessed by the master CPU; the others
are accessed indirectly via the ·block transfer
mechanism.
The I/O port and control registers are included in the register file without differentiation. This allows any UPC instruction to process I/O or control information, thereby eliminating the need for special I/O :and control in2047
LH8090/LH8090A
structions. All general-purpose registers can
function as accumulators, address pointers, or
index registers. In instruction execution, the
. registers are read when are defined as sources
and written when defined as destinations.
UPC instructions may access registers directly or indirectly using an 8-bit address mode or
a 4-bit address mode and a Register Pointet.
For the 4-bit addressing mode, the file is divided into 16 working register groups, each
occupying 16 contiguous locations (Fig. 3). The
Register Pointer (RP) addresses the starting
point of the active working. register group, and
the 4-bit register designator supplied by the instruction specifies the register within the group.
Any instruction altering the contents of the register file can also alter the Register Pointer. The
UPC inst~uction set has a special Set Register
LOCATION
:~AGS~
FDH
REGISTER POINTER
FCH
PROGRAM CONTROL FLAGS
FBH UPC INTERRUPT MASK REGISTER IMR
FAH
IRQ
UPC INTERRUPT REQUEST REGISTER
IPR
F9H
UPC INTERRUPT PRIORITY REGISTER
PIM
F8H
PORT 1 MODE
F7H
PORT 3 MODE
PORT 2 MODE
F6H
F5H
F4H
F3H
F2H
FI H
USER
ROM
IDENTIFIER
(UPC Side)
SP
STACK POINTER
MIC
MASTER CUP INTERRUPT CONTROL
FOH
EFH
ToPRESCALER
TIMER/COUNTER 0
T,PRESCALER
TIMER/COUNTER 1
TIMER MODE
MASTER CPU INTERRUPT VECTOR REG.
12 ~~~~HPlD °lFn\SftE~};ll OF INSTRUCTION
11
IRQ 5 LOWER BYTE
IRQ 5 UPPER BYTE
10
9
8
IRQ 4 LOWER BYTE
IRQ 4 UPPE R BYTE
7
6
IRQ 3 LOWER BYTE
5
4
3
2
IRQ 3 UPPER BYTE
IRQ 2 LOWER BYTE
J
IRQ 2
IRQ I
IRQ I
IRQ 0
UPPE R
LOWER
UPPER
LOWER
BYTE
BYTE
BYTE
BYTE
0
IRQO UPPER BYTE
Fig 1 Program memory map
P3M
P2M
PREO
TO
PREI
T1
TMR
MIV
GENERAL-PURPOSE
REGISTERS
DATA INDIRECTION REGISTER
DlND
LC
LIMIT COUNT REGISTER
PORT 3
PORT 2
P3
P2
PORT I
PI
DATA TRANSFER CONTROL REGISTER
Fig 2
DTC
Register file organization
-----------SHARP----.---------441
~
LH8090/LH8090A
Z8090/Z8090A Universal Peripheral Controller
r-
1-...,,0
011 1
I
o 000
7 5 H (01110101)
FDH
FOH
EFH
EOH
DFH
DOH
CFH
COH
BFH
BOH
AFH
AOH
9FH'
90H
8FH
80H
~
70H
6FH
60H
5FH
50 H
4FH
40H
3FH
30H
2FH
20 H
IFH
10 H
OFH
downs, compatible with TTL loads. In addition,
Port 1 and Port 2 may be configured as opendrain
outputs. Data in each port can be .known by reading
a corresponding Port Mode register in the same
way as acc~ssing the register.
Port 1: Individual bits of port 1 can be confi·
gured as input or output. This port can also be
programmed as 110 Handshake Line. This port is
accessed as general register 1H. It is written by
specifying address 1H as the destination of any instruction used to store data in the output registers.
The port is read by specifying address 1H as the
source of an instruction.
Port 2: lndividual bits of Port 2 can be confi- .
gured as inputs or outputs. This port is accessed as
general register 2H, and its functions and methods
of programming are the same as those or Port 1.
Port 3: This port can be configured as 1/0 or
control lines. Port 3 is accessed as general register
3H. The directions of the eight data lines are fixed.
Four lines, P30 through P33, are inputs, and the
. other four, P3. through P37, are outputs. The control fun~tions performed by Port 3 are listed in
Table 1.
Table 1
0
Function
'1: The 4-bit register pointer provides the upper nibble of the
register file address for the 4-bit address mode.
'2: The lower nibble of the register file address (010 1) is pro·
vided by the instruction.
Fig. 3
Pointer (SRP) instruction for iiIitializing or altering the pointer contents.
Stacks: An 8-bit stack Pointer (SP), register
R255. is used for addressing the stack, residing
within the 234 general-purpose regisgers. address
location 6H through EFH.
PUSH and POP instructions can save and restore
any register in the register file on the stack. During
CALL instructions, the Program Counter is automatically saved on the stack. During UPC interrupt
cycles, the Program Counter and the Flag register
are automatically saved on the stack. The RET and
IRET instructions pop the saved values of the
Program Counter and Flag register.
(2) Ports
The LH8090 has 24 lines dedicated to input and
output. These are grouped into three ports eight
lines each and can be configured under software
control as inputs, outputs or special control sig·
nals.
They can be programmed to provide Parallel 110
with or without handshake and timing signals.
All outputs can have active pullups and pull·
442
Handshake
Register pointer mechanism
UPC Interrupt
Request *
Counter ITimer
Master CPU
Port 3 control functions
Line
P31
P33
P3.
P36
P30
P3,
P33
P3,
P36
P35
P32
P30
P37
110
I
I
0
0
I
I
I
I
0
0
I
I
0
signal
DAV2/RDY,
-DAVdRDY,
-RDYdDAV,
-RDYzlDAV2
IRQ3
IRQ,
IRQ,
TIN
TOUT
INT
--INTACK
lEI
lEO
*
P3o. P3" and P33 can always be used as upe interrupt reo
quest inputs, regardless of the configuration programmed.
(3) Counter/timers
The LH8090 contains two 8-bit programmable
counter/timers, each driven by an internal 6-bit
programmable prescaler.
The T1 prescaler can' be driven by internal or
external clock sources. The TO prescaler is driven
by an internal clock source. Both counter Itimers
operate independently of the processor instruction
sequence to relieve the program from time-critical
oPerations like event counting or elapsed-time calculation.
Z8090/Z8090A Universal Peripheral Controller
The counters can be started, stopped, restarted
to continue, or restarted from the initial value.,
They can be programmed to stop upon reaching
end-of-count (Single-Pass mode) or to automatical·
ly reload the initial value and continue counting
(Modulo-n Continuous mode).
(4) Interrupts
The LH8090 allows six interrupts from eight
different sources as follows:
• Port 3 lines P3o, P31, and P33.
• The master CPU (3).
• The two counter/timers.
These interrupts can be masked and globally enabled or disabled. The order of their priority can
be specified. All interrupts are vectored.
Table 2 lists the LH8090's interrupt sources,
their types, and their vector locations in program
ROM.
The LH8090 also supports polled systems.
To acommodate a polled structure, any or all of
the interrupt inputs can be masked and the interrupt request register polled to determine which of
LH8090/LH8090A
the interrupt request needs service.
(5) Master CPU register file access
There are two ways in which the master CPU
can access the LH8590 register file: direct access
and block access.
Direst Access: Three LH8090 registers - the
Data transfer Control, the Master Interrupt Vector,
and the Master Interrupt Control - are mapped
directly into the master CPU address space.
The registers can directly be accessed in 16
bytes.
Block Access: The masteJ;" CPU may be transmit or receive blocks of data via address X X X
10101 (X X 10101 X for shift address). When the
master CPU accesses this address, the LH8090
register pointed to by the Data Indirection register
(DIND) is read or written.
The number of bytes is set in the Limit Count
register (LC). The LH8090 controls everything in
the block transfer and is therefore allowed to protect itself from master CPU errors.
Table 2 Interrupt types, sources, and vector locations
, Name
IRQO
IRQl
IRQ2
IRQ3
IRQ4
IRQ5
Source
EOM, XERR, LERR
DAVl, IRQl
-DA V2, IRQ2, TIN
IRQ3, lEI
TO
T1
Vector Location
0,
1
2, 3
4, 5
6,
8,
10,
7
9
11
Comments
Internal (RO Bits 0, I, 2)
External (P33) ! edge triggerd
External (P31) ! edge triggerd
External (P3o) ! edge triggerd
Internal
Internal
443
Z8090lZ8090A
•
IMR
Instruction
(1 ) Addressing modes
The following notation is used to describe the
addressing modes and instrucion operations.
IRR
Indirect register pair or indirect work·
ing-register pair address
Indirect working-register pair only
Irr
Indexed address
X
Direct address
DA
Relative address
RA
Immediate
1M
Register or working-register address
R
Working-register address only
r
Indirect-register or indirect workingIR
register address
Ir
Indirect working-register address only
RR
Register pair or working-register pair
address
(2) . Symbol
dst
Destination location or contents
Source location or contents
src
Condition code (see list)
cc
@
Indirect address prefix'
PC
Program Counter
SP
Stack Pointer (control register FFH)
FLAGS Flag register (control register FCH)
RP
Register Pointer (control register FDH)
Table 3
Value
1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000
LH8090lLH8090A
Universal Peripheral Controller
Mnemonic
C
NC
2
NZ
PL
MI
OV
NOV
EQ
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE
Interrupt mask register (control register FBH)
Assignment of a value is, indicated by the sym'
bol "+-n. For example.
dst +- dst + src
indicates that the source data is added to the destination data and the result is stored in the destination location. The notation "addr(n)" is used to
refer to bit "nn of a given location. For example.
dst (7)
refers to bit 7 of the destination operand.
(3) Flags
.
Control Register FCH contains the following six flags:
C
Carry flag
Z
Zero flag
S
Sign flag
V
Overflow flag
D
Decimal-adjust flag
H
Half-carry flag
Affected flags are indicated by:
o Cleared to zero
1
Set to one
Set or clear.ed according to operation
Unaffected
X
Undefined
(4) Condition codes
*
Table 3.
shows condition codes.
Condition codes
Meaning
Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Never true
Flags set
.........
C=l
C=O
Z=l
Z=O
S=O
S=l
V=l
V=O
Z=l
2=0
(S XOR V)=O
(S XOR V)=l
[2 OR(S XOR V)) =0
[2 OR(S XOR V)) = 1
C=O
C=l
(C=O AND 2=0)= 1
(C OR 2)=1
.........
-~--------.-.....-SHARP---.------
444
?:8090/Z8090A Universal Peripheral Controller
LH8090/LH8090A
(5) Opcode Map
Lower Nibble (Hex)
o
6.5
6.5
o
DEC
2
2
3
4
5
6
7
6.5
6.5
10.5
10.5
10.5
10.5
8
DEC ADD ADD ADD ADD ADD ADD
R.
IR.
TI, T2
fl,ITZ
Rz. R\
IRz, RI
RI.IM
IR,.IM
6.5
6.5
6.5
6.5
10.5
10.5
10.5
10.5
RLC
RLC
ADC ADC ADC ADC ADC
n,
R.
IR.
fl, T2
Rz. RI
IRz. RI
R •• IM
6.5
6.5
6.5
10.5
10.5
10.5
10.5
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
IR •• IM
R.
IR.
T],TZ
T\,IT2
Rz. RI
IR 2• R,
RI.IM
6.1
6.5
6.5
10.5
10.5
10.5
10.5
JP
SRP
SBC
SBC
SBC
SBC
SBC
SBC
IRRI
1M
Tt, IT!
Rz. RI
IRz, RI
RI.IM
IR •• IM
8.5
8.5
6.5
6.5
10.5
10.5
10.5
10.5
4
DA
DA
OR
OR
OR
OR
OR
OR
R.
IR.
TI,T2
TIoIT2
Rz, RI
IRz. R,
R •• IM
lRI.IM
.= 5
10.5
10.5
6.5
6.5
10.5
10.5
10.5
10.5
POP
POP
III
R.
IR.
r"r2
TI.IT2
.Q
6.5
6.5
6.5
6.5
xIII
:c
::::l
T2
C
o
6.5
6.5
12110.5
12110.0
6.5
12110.0
6.5
LD
LD
DJNZ
JR
LD
JP
INC
r"IM
ce, DA
"
flo
Rz
f2. RI
TI.
RA
ce, RA
F
E
I---
I
I---
I---
I---
I---
AND AND AND AND AND AND
Rz. RI . IR2• Rl
10.5
10.5
RI.IM
IR •• IM
10.5
10.5
I---
COM COM TCM TCM TCM TCM TCM TCM
Z 6
Gi
Q.
Q.
n,
B
IRI.IM
H.n
3
A
ADC
6.5
IT!
9
R.
JR.
TI,T2
fI, IT!
R2. RI
IR2. R\
R1. IM
10112.1
12114.1
6.5
6.5
10.5
10.5
10.5
10.5
TM
TM
TM
TM
TM
TM
TI,T2
TIoIT!
Rz• R,
RI.1M
IR\.IM
PUSH PUSH
7
8
9
R,
IR,
lO,:}
10.3
12.0
lOEI
IrT2
In. lIT!
RR.
IR.
6,5
6.5
12.0
18.0
RL
RL
lOE
LDEI
R.
IR •
T2,lrrl
Irz.lrrl
w.;)
10.;)
INCW INCW
A
B
0
E
6.1
01
I--6.1
EI
I--14,0
6.5
6.5
10.5
10.5
10.5
CP
CP
CP
CP
CP
CP
Rt.IM
IR1. 1M
10.5
IR.
n.T2
n.lr!
R2. R,
IR z• RI
6.5
6.5
6,5
6.5
10.5
10.5
CLR
CLR
XOR
XOR
XOR
XOR
XOR
XOR
IR2. RI
R],IM
IR!, 1M
IR.
TI,T2
6,5
6.5
RRC
RRC
R.
JR.
6.5
6.5
12.0
TI,lrn
12.0
SRA
SRA
n.lr!
R2. RI
IS.O
6.5
RCF
Tl,
20.0
x,
R2
20.0
10.5
CALL
LD
DA
f2, X, RI
R.
JR.
In.ITT\
IRR,
6.5
6.5
6.5
10.5
10.5
10.5
10.5
RR
RR
LD
LD
LD
LD
LD
lRz. RI
RJ,IM
IR!, 1M
R2• RI
R.
IR.
T\,In
8,5
8.5
6.5
10.5
LD
LD
lrl,TZ
Rz,IR,
R.
IR.
IRET
I---
10.5
LDC lOCI CALL"
f2.Irf!
~
LD
ITI,lrr!
18.0
RET
10.5
10.5
LDC LOCI
SWAP SWAP
F
I---
RR.
R.
C
RI
I---
18.0
DECW DECW LDE
T\,
IR 2•
IR1.IM
I--6.5
SCF
-
6.5
CCF
-
6.0
NOP
~--------~------~~------~--------~~----------~----------~~~
Bytes per
Instruction
3
2
Lower Opcode Nibble
Execution
Upper
Opcode
Cycles
Nibble~
First
A
Operand
Pipeline
Cycles
4 - - Mnemonic
2
3
Legend:
R = 8-Bit Address
r = 4 - Bit Address
Rl or n = Dst Address
R2 or r2 = Src Address
Sequence:
Opcode. First Operand. Second Operand
Note: The blank areas are not defined.
Second Operand
----.-------.---SHARP - - - - - - - - - - - . - . . .
445
Z8090/Z8090A 'Universal Peripheral Controller
LH8090/LH8090A
Instruction Summary
Instruction
and
Operation
I
I
ADC dst, src
dst....dst + src + C
ADD dst, src
dst ....dst + src
AND dst, src
dst ....dst AND src
CALL dst
SP....SP-2
@SP.... PC· PC ....dst
CCF
C.... NOT C
CLR dst
dst....O
COM dst
dst....NOT dst
CP dst, src
dst....src
DA dst
dst ....DA dst
DEC dst
dst.... dst-l
DECWdst
dst....dst-l
Addr. mode
dst src
(Note 1)
(Note 1)
00
****0*
(Note 1)
50
-**0--
D6
D4
------
EF
*---
R
IR
R
IR
(Note 1)
BO
Bl
60
61
AD
------
R
IR
R
IR
RR
IR
40
41
00
01
80
81
8F
***X--
RA
rA
r=O-F
DA
IRR
01
IMR(7) .... 0
DJNZ r,dst
r .... r-l
if r+O PC .... PC+dst
Range; + 127--128
EI
IMR(7) .... 1
INC dst
dst....dst+ 1
Opcode Flags Affected
(Hex) CZSVDH
10
****·0*
9F
-
-**0-****--
Instruction
and
Oparatlon
I
I
LDEI dst, src
dst....src
r .... r+ 1; rr ....rr+ 1
NOP
OR dst, src
dst.... dst OR src
POP dst
dst....@SP
SP....SP+l
PUSH src
Sp....SP-l· @SP ....src
RCF
C.... O
PET
PC ....@Sp· Sp....SP+2
4RL dst
------
R
IR
-**0--
------
70
71
CF
0
RR dst
4947
RRC dst
----
AF
~7 O~
----
FF
40
50
51
R
IR
R
IR
RLC dst
-
(Note 1)
O~
~7
-***--***--
Addr. mode
Opcode Flags Affected
(Hex) CZSVDH
dst src
Ir
Irr·
83
Irr
Ir
93
--
90
91
****--
R
IR
10
****--
O~
R
IR
EO
El
****
~7 O~
R
IR
CO
Cl
****
3D
****1*
DF
1
DO
Dl
* * * 0
31
------
2D
****1*
FO
Fl
X* *X--
sec dst, src
dst....dst - src - C
SCF
C.... l
(Note 1)
11
~
r
R
IR
RR
IR
INCW dst
dst....dst+ 1
IRET
FLAGS ....@SP;SP....SP+ 1
PC ....@Sp·SP ....SP+2;IMR(7).... 1
DA
JP cc, dst
if cc is true
PC ....dst
IRR
RA
JR cc, dst
if cc is true,
PC .... PC+dst
Range: +127--128
r
LD dst, src
1M
dst ....src
r
R
R
r
LDC dst, src
dst....src
LOCI dst, src
dst-src
r-r+ l' rr-rr+ 1
LDE dst, src
dst-src
446
r
X
r
Ir
R
R
R
IR
IR
r
Irr
Ir
Irr
r
Irr
X
r
Ir
r
R
IR
1M
1M
R
Irr
r
Irr
r
Irr
r
rE
-***-r=O-F
20
21
AO
-***-Al
BF
******
cD
c=O-F
30
cB
c=O-F
------
rC
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
E6
E7
F5
C2
D2
C3
D3
------
82
92
L,g ell t P
SRA dst
1M
SRP src
RP ....src
SUB dst, src
dst.... dst - src
SWAP dst
TCM dst,src
(Note 1)
~
I(NOT ds!) AND src
------
TM dst,src
dst AND src
XOR dst,src
dst.... dst XOR src
-----------
(Note 1)
60
* * 0
(Note 1)
70
* * 0
(Note 1)
BO
-**0--
Note 1: These instructions have an identical set of' addressing
modes, which are encoded for brevity. The first opcode nibble is
found in the instruction set table above. The second nibble is ex·
pressed symbolically by a 0 in this table, and its value is found
in the following table to the left of the applicable addressing
mode paie.
For example, to determine the opcode of an ADC instruction
using the addressing modes r (destination) and Ir (source) is 13.
Addr Mode
------
R
IR
dst
r
r
R
R
R
IR
src
r
Ir
R
IR
1M
1M
Lower
Opcode Nibble
!2J
11I
Ii]
lID
[ill
[Z]
Z8090/Z8090A Universal Periph~Hal Controller
•
LH8090/LH8090A
Register
RO (DTC)
upe Register Address (Hex): 00
I D7 I D61
D51 D,I D31 D21 DI I Dol
I
I/O REGISTER POINTER
ORP)I
_ _ _ _ _ _(_E_D_X---..J).
DISABLE DATA TRANSFER=O'
ENABLE DATA TRNSFER=1
NO TRANSFER ERROR =0
(XERR)
TRANSFER ERROR = 1
I(EOM) . 0=I=END OF MESSAGE
(LERR)
O=NO LIMIT ERROR
1 = LIMIT ERROR
R4 (LC)
R5 (DIND)
upe Register Address (Hex): 04
upe Register Address (Hex): 05
I D7 I D6 I Dsl D,I
I D71
D31 D21 DJ I Do I
<-I-
Ds! D51 D,I D31 D21 Dd Dol
_ _ _ _ LIMIT COUNT VALUE
(RANGE:0-255 DECIMAL
00- FF HEX)
LINDIRECTION ADDRESS
(Do= LSB)
R240 (MIV)
upe Register Address (Hex): f1
I D7 I D61 D5 I D4 I D31 D2 I DI I Do I
VECTOR DATA (Do = LSB)
I
R241 (TMR)
upe register address (Hex): Fl
I D71 D61
I
TOUT MODES=::::J
RESERVED = 00
To OUT = 01
TJ OUT = 10
INTERNAL CLOCK OUT = 11
TIN MODES - - - - - - '
EXTERNAL CLOCK INPUT = 00
GATE INPUT =01
TRIGG ER INPUT = 10
(NON -RETRIGGERABLE)
TRIGGER INPUT = 11
(RETRIGGERABLE)
R242 (T1)
Counter/Timer 1 Register
upe Register Address (Hex): F2
FU~CTION
O = NO
1 = LOAD To
C O = DISABLE To COUNT
1 = ENABLE To COUNT
0 = NO FUNCTION
1 = LOAD TI
' - - -_ _ _ 0 = DISABLE TI COUNT
1 = ENABLE TI COUNT
R243 (PRE1)
upe Register Address (Hex): F3
I D71 D61 D5 1 D41
I D71 D61 D51 D41 D31 D21 DIlDo I
C=:TI INITIAL VALUE
(RANGE: 1-2 5 6 DECIMAL
01-00 HEX)
L
D5 I D41 D31 D2 I DI I Do I
l
D31 D21 DIlDo 1
LCOUNT MODE
0 = TI SINGLE PASS
1 = TI MODULO· N
CLOCK SOURCE
0 = EXTERNAL TIMING IN
(TIN) MODE
1 = TI INTERNAL
'---------PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
.-----.----------SHARP - - - - - . - . - - - - - -
447
LH8090/LH8090A
Z8090/Z8090A Uhh,ersal Peripheral Controller
R245 (PREO)
Prescaler 0 Register
UPC Register .Address (Hex): F5
R244 (TO)
Counter/Timer 0 Register
UPC Register Address (Hex): F 4
1 071 061 Dsl 04 1 03 1 02
I 01 I Do I
1 07
'
L
I 061 Os I 041 031 02 I 0 1 I Do I
C=To INITIAL VALUE
(RANGE: 1-256 DECIMAL
I
01-00 HEX)
COUNT MODE
O=To SINGLE-PASS
1 = To MODULO· N
RESERVED
'-------PRESCALER MODULO
(RANGE: 1-64 DECIMAL
R246 (P2M)
Port 2 Mode Register
UPC Register Address (Hex): F6
01-00 HEX)
I 07 I 06 I Os I 04 I 031 02 I 01 I Do I
L
P20- P27 I/O DEFINITION
BIT AS OUTPUT
1 DEFINES BIT AS INPUT
o DEFINES
R247 (P3M)
Port 3 Mode Register
UPC Register Address (Hex): F7
I 07 I 061 Os I 041 03 I 02 I 01 I Do I
LS
Lo PORT 2 PULL-UPS OPEN DRAIN
1 PORT 2 PULL-UPS ACTIVE
o PORT
I PULL-UPS OPEN DRAIN
1 PORT I PULL-UPS ACTIVE
o P3S =
OUTPUT
I P3S = INT
RESERVED
o P33= INPUT
I P3F DAV1/RDYI
'-----0 P31= INPUT (TIN)
I Pl!= DAV2/RDY2
~-------'OP30=INPUT
I P30 = lEI
P34 = OUTPUT
P34 = ROY l/DA V I
P36 = OUTPUT (TOUT)
P36 = RDY2/DAV2
P37 = OUTPUT
P37 = IEO
L----------OP32=INPUT
I P3F INTACK
R248 (P1 M)
Port 1 Mode Register
UPC Register Address (Hex): F5
1 07
I 061 05 I 04 I 031 021 01 I Do I
I'----Plo-Ph I/O DEFINITION
o DEFINES BIT AS OUTPUT
I DEFINES BIT AS INPUT
.-.---.---------$HARP----------448
Z8090/Z8090A Universal Peripheral Controller
LH8090/LH8090A
R249 (lPR)
Interrupt Priority Register
upe Register Address (Hex): F9 (write only)
1 D71 D61 D51 D.I D31 D21 Dl I Do
I
RESERVED~
IRQl,IRQ4 PRIORITY (GROUP C)
o =IRQl>IRQ4
INTERRUPT GROUP PRIORITY--+---'----t------'
I =IRQ4>IRQI
RESERVED=OOO
C>A>B=OOI
~---IRQO,IRQ2 PRIORITY (GROUP B)
A>B>C=OIO
o =IRQ2>IRQO
A>C>B=OII
1 =IRQO>IRQ2
B>C>A=IOO
~-------IRQ3,IRQ5 PRIORITY (GROUP A)
C>B>A=lOI
o =IRQ5>IRQ3
B>A>C=IIO
1 =IRQ3>IRQ5
RESERVED =111
R250 (IRQ)
Interrupt Request Register
R251 (lMR)
.Interrupt Mask Register
upe Register Address (Hex): FB
upe Register Address (Hex): FA
I D7 I D6 I D5 I D.I D3 I D2 I Dl I Do I
Uk~
I D71 D61 D5 I D.I D3 I D2 I DJ I Do
I I
IRQO=MASTER CPU
COMMUNICATIONS
QI=P3, INPUT
Q2=P31 INPUT
Q3=P3, INPUT
IR Q4=To
IR Q5=Tt
RESERVED
I
I~
L I1 ENAIlLES
ENABLES
!ROO
IRQI
IRQ2
IRQ3
IRQ4
IRQ5
1 ENABLES
1 ENABLES
~-----1 ENABLES
' - - - - - - - - 1 ENABLES
' - - - - - - - - - RESERVED
' - - - - - - - - - - - - - 1 ENABLES INTERRUPTS
R252 (FLAGS)
Flag Register
R253 (RP)
Register Pointer
upe Register Address (Hex): Fe
upe Register Address (Hex): FD
I D71 D61 D5 I D.I
D31 D21 Dt! Do
LS
I
I
I D71 D61 D51 D.I
LUSER FLAG Fl
FLAG F2
HALF CARRY FLAG
DECIMAL ADJUST FLAG
'-------OVERFLOW FLAG
~-------SIGN FLAG
~--------ZEROFLAG .
'------------CARRYFRAG
~USER
I
D31 D21 DJ I Do
I
LDON'T CARE
~.-------REGISTER
(r.-n)
-----~--.---SHARP--.-.---~----
449
B
Z8090/Z8090A Universal Peripheral Controller
LH8090/LH8090A
R~54 (MIC)
Master CPU Interrupt Control Register
UPC Register Address (Hex): FE
I D71 D6 I Dsl D41 Dal D21 DI I Dol
o INTERRUPT REQUEST DISABLEDJ
o INTERRUPT REQUEST ENABLED
o NO INTERRUPT UNDER SERVICE
~I
II L:
;NO OF MESSAGE
ENABLE WHEN WRITE
1 WAIT DISABLE WHEN WRITE
o WAIT
1 INTERRUPT UNDER SERVICE
o ENABLE
o NO
MASTER CPU INTERRUPT. PENDING
1 MASTER CPU INTERRUPT PENDING
o VECTOR OUTPUT - - - - - - '
1 NO VECTOR OUTPUT
LOWER CHAIN
1 DISABLE LOWER CHAIN
' - - - - - - - 0 DISABLE DATA TRANSFER
1 ENABLE DATA TRANSFER
R255 (SP)
Stack Pointer
UPC Register Address (Hex): FF
I D7 I D61 Ds I D. I Da I D2 I DI I Do I
II-----STACK POINTER
Table 4.
OOH
04 H
05 H
FO H
FIH
F2H
F3 H
F4H
F5 H
F6 H
F7H
Control Register
Data transfer control register
Limit count register
Data indirection register
Interrupt vector register
Timer mode
Tl register
T 1 prescaler
TO register
TO prescaler
Port 2 mode
port 3 mode
port 1 mode
Interrupt priority
Interrupt request
Interrupt mask
Flag register
Register pointer
Master CPU interrupt control
register
FFH Stack pointer
F8 H
F9 H
FAH
EBH
FC H
FDH
FEH
Note:
Control register reset conditions
D7 D6 Ds D4 D3 D2 DI Do
X
X
X
X
0 0 0 0
Not defined
Not defined
Not defined
0 0 0 0 0 0 0 0
Not defined
X
X
X
X
X
X
0 0
Not defined
X
X
X
X
X
0 Q
X
1 1 1 1 1 1 1 1
1 0 0
0 0 0 0 X
1
1
X
X
0
X
0
0
1
1 1 1
Not defined
0 0 0 0
X X X X
Not defined
Not defined
0 0 0 0
Comments
Disable data transfer from master CPU
Stops TO and T1
Single-pass mode
1
1
Single-pass mode external clock source
Port 2 lines defined as inputs
Port 1. 2 open drain output
P3 s = INT
P3 o• P3 10 P3 2. P3 3 defined as' input
P3 4• P3 6• P3 7 defined as output
Port 1 lines defined as inputs
0
X
0
X
Reset interrupt request
Interrupts disabled
0
0
Master CPU interrupt disabled: wait
enable when write: lower chain enabled
Not defined
X means not defined.
---------.-.-..--SHARP -....--....-..-----
450
Z8091/Z8091 A Development Device
LH8091/LH8091 A
LH8091/LH8091A ~~:;:~;!DeViCe
•
Description
The 64-pin LH8091 is the development version
of LH8090 (Z8090) UPC with internal maskprogrammed ROM. This device allows the user to
the prototype systems in hardware without an
actual device and to develop the code that is eventually mask-programmed into the on-chip ROM of
the LH8090.
The LH8091 is identical to the LH8090 with the
following exceptions.
• The internal ROM has been removed .
• The ROM address lines and data lines are buffered and brought out to external pins.
• Control lines for the memory have been added.
The LH8091A is the high speed version which
can operate at 6MHz system clock.
•
Pin Connections
+5V
1
PCLK
2
Top View
451
Z8091fZ8091 A
•
Development Device
LH8091/LH8091A
Block Diagram
Program Memory Address Output
,
Address/Data
Bus
I/O
Address Strobe 9
Data Strobe 7
Read/W rite 8
Chip Select 10
I/O
Interrupt Request 5
Interrupt Acknowledge 6
Interrupt Enable In
Interrupt Enable
Out
Interrupt Acknowledge
Output/Memory Read
•
24)---------------'----------'
Pin Description
LH8091 has the same functions as those of a 40-pin device LH8090, and the functions of the additional 24
pins are as follows.
Meaning
Program memory address
Program data
Interrupt acknowledge
Imemory read.
I/O
0
I
MAS
Memory address strobe
0
MDS
Memory data strobe
0
Synchronization
0
Symbol
Ao'- All
Do -D 7
IACK/MR
0
-~
--
SYNC
Function
Used for the access to the external memory of 4K bytes.
Reads the data through these lines from the external memory.
Active high. This signal becomes high during interrupt or in·
struction fetch cycle of LH8591.
Active low. This signal is output every memory fetch cycle
for the interface with the external ROM.
Active low. This signal becomes low during instruction fetch
cycle or write cycle.
Active low. This signaJ becomes low at the clock cycle just
before Op-code fetching.
-------------SHARP,....-.-..-------452
Z8092/Z8092A Development Device
LH8092/LH8092A
LH8092/LH8092A
•
Description
•
The 64-pin LH8092 is the development version
of LH8090 (Z8090 UPC) with internal maskprogrammed ROM. This device allows the user to
the prototype systems in hardware with an actual
device and to develop the code that is eventually
mask-programmed into the on-chip ROM of the
LH8090.
The LH8092 is identical to the LH8090 with the
following exceptions.
• The internal ROM has been removed (But
there are 36 bytes of internal ROM for a bootstrap program) .
• The ROM address lines and data lines are buffered and brought out to external pins.
• Control lines for the memory have been added.
The LH8092A is the high speed version which
can operate at 6MHz system clock.
Z80921Z8092A
Development Device
Pin Connections
+5V 1
PCLK 2
P37/IEO 3
P3o/IEI •
P35/INT 5
P3,fINT ACK 6
5
P2.
P23
P22
Top View
.-----~--.-.--SHARP
--.------------453
Z8092/Z8092A Development Device
•
LH8092/LH8092A
Block Diagran
.
Program Memory Address Output
Address/Data
Bus
I/O
Address Strobe 9
Data Strobe 7
Read/Write 8
Chip Select 0
Wait 11
I/O
Interrupt Request 5
o
Interrupt Acknowledge 6
Interrupt Enable In
Interrupt Enable
Out
Interrl!!t Acknowledg 241}-------~--------------'
Memory/Read/ ' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
&~ti~~t
•
Pin Description
LH8092 has the same functions as those of a 40-pin device LH8090, and the functions of additional 24
pins are' as follows.
Symbol
Ao-Au
Meaning
Program memory address
I/O
00-07
Program data
I
LACK
Interrupt acknowledge
0
MAS
Memory address strobe
0
Memory data strobe
0
MR/W
Memory read/write
0
SYNC
Synchronization
0
-MOS
-
0
Function
Used for the access to the external memory of 4K bytes.
Reads for data through these lines from the external memory.
And it is possible to write into an external RAM through
these lines.
Active high. This signal is always active during interrupt cycle of LH8092.
Active low. This signal is output every memory feich cyclefor
interfacing with the external RAM.
Active low. This signal is outptt eyery memory fetch cycle for
cycle or write cycle.
This signal is high during instruction fetching by LH8092,
or low while writing into the external memory.
Active low. This signal becomes low during clock cycle just
before OP code fetching.
- - - - - - - - - - - - - - S H A R P - - - . - - - - - , - - - - - - - ........
454
LH8093/LH8093A
Z8093/Z8093A Protopack Emulator
LH8093/ LH809 3A ~:::1!093A
•
Description
The LH8093 (28093) is a ROMless version of
the standard LH8090, housed in a pin compatible
40-pin package.
The LH8093 carries a 40-pin soket for a direct
interface to program memory. 2716 type EPROM
can be used for program memory.
The LH8093 allows the user to build the prototype and pilot production units. When the final
program is established, the user can then switch
over the LH8090.
The LH8093A is the high speed version which
can operate at 6MHz system clock.
•
Protopack
Pin Connections
o
P31
P36
P37/IEO
3
P27
P30/IEI
4
P26
P3s/INT
5
P2s
P32/INTACK
6
P2.
P23
P22
P21
P33
P3.
Ph
PIs
PIs
Pl.
Pb
Ph
Ph
ADo
Top View
455
Z8093/ZS093A Protopack Emulator
LH8093/LH8093A
Block Diagram
•
*1*2*3'
Address/Data
Bus
Address Strobe
Data Strobe
Read/Write
Chip. Select
Program Data Input Program Memory Address Output
"
•
I/O
9
7
8
10
I/O
Interrupt Request
Interrupt Acknowledge
Interrupt Enable In
Interrupt Enable
Out
*1 Program Memory Data Strobe Output
*2 System Clock Output
*3 Instruction Sync Output
o : This
•
is equipped with ROM
Pin Description
LH8093 pins are compatible with those of LH8090. For pin descriptions of LH8093, refer to those of
LH8090.
456
Z8094/Z8094A Protopack Emulator
LH8094/LH8094A
LH8094/LH8094A ~~=094AProtopaCk
• . Description
The LH8094 (28094) is a RAM version (16K
bits RAM) of the standard LH8090, housed in a pin
compatible 40-pin package.
The LH8094 carries a 24-pin soket for a direct
interface to program memory, and has 36 bytes of
internal ROM for a bootstrap program.
The LH8094 allows the user to build the prototYPe and when the final program is established,
the user can then switch over the LH8090.
The LH8094A is the high speed version which
can operate at 6MHz system clock.
•
Pin Connections
o
P31
P36
P37/IEO
3
P2,
P30/IEI
4
P26
P35/INT 5
P32/INT ACK 6
P25
P2.
P23
P2,
P21
P33
P3.
PI6
PIs
Pl.
PIa
PI,
Ph
ADo
Top View
457
/
.Z8094/Z8094A· Protopack Emulator
•
LH8094/LH8094A
Block Diagram
Program Data Input
Program Memory Address Output
*1*2*3,~-----'~----~"r--------~'~--------~
Address/Data
Bus
Address Strobe 9
Data Strobe 7
Read/Write 8
Chip Select 10
Interrupt Request
Interrupt Acknowledge
Interrupt Enable In
Interrupt Enable
Out
*1 Program Memory Data Strobe Output
*2 System Clock Output
*3 Instruction Sync Output
C : This is equipped with RAM
•
Pin Description
LH8094 pins are compatible with those of LH8090. For pin descriptions of LH8094, refer to those of
LH8090.
458
Peripheral LSls for Microcomputers
!-H 85301 LH 8530A
Z8530/Z8530A Serial Communications Controller
LH8530/LH8530A
Z8S301Z8S30A Serial Communications Controller
•
Description
The LH8530 Z8530 SCC Serial Communications
Controller is a dual-channel, multi-protocol data
communications peripheral designed for use with
conventional non-multiplexed buses. The LH8530
functions as a serial-to-parallel, parallel-to-serial
converter controller. The LH8530 can be softwareconfigured to satisfy a wide variety of serial communications applications. The device contains a
variety of new, sophisticated internal functions including on-chip baud rate generators, Digital
Phase- Locked Loops, and crystal oscillators that
dramatically reduce the need for external logic.
The LH8530 handles asynchronous formats,
Synchronous byte-oriented protocols such as IBM
Bisync, and Synchronous bit-oriented protocols
such as HDLC and IBM SDLC. This versatile device supports virtually any serial date transfer application (cassette, disk tape drives, etc).
The device can generate and check CRC codes in
any Synchronous mode and can be programmed to
check data integrity in various modes. The
LH8530 also has facilities for modem controls in
both channels. In applications where these controls
are not needed, the modem controls can be used for
general-purpose I/O.
The daisy-chain interrupt hierarchy is also supported by the LH8530.
The LH8530 is packaged in a 40-pin ceramic
DIP and uses a single+ 5V power supply.
The LH8530A Z8530A SCC is the high speed
version which can operate at 6MHz system clock.
•
Features
1. Two independent, 0 to 1.5M bit/second, fullduplex channels, each with a separate crystal
oscillator, baud rate generator, and Digital
Phase-Locked Loop for clock recovery.
2. Multi-protocol operation under program control; programmable for NRZ, NRZI, or FM data
encoding.
3. Asychronous mode with five to eight bits and
one, one and one-half, or two stop bits per
•
Pin Connections
0
On
02
O.
06
RO
WR
AlB
INTACK
8
+5V 9
W/REQA
CE
o/e
GNO
SYNCA
W/REQB
RTxCA
SYNCB
RxOA
TRxCA
TxOA
OTR/REQA
RTxCB
RxllB
TRxCB
TxllB
RTSA
IlTR/R};qB
CTSA
RTSB
DCDA
CTSB
PCLK
Top View
character; programmable clock factor, break
detection and generation; parity, overrun, and
framing error detection.
4. Synchronous mode with internal or external
character synchronization on one or two synchronous characters and CRC generation and
checking with CRC-16 or CRC-CCITT preset
to either Is or Os.
5. SDLC/HDLC mode with comprehensive framelevel control, automatic zero insertion and deletion. I-field residue handling, abort generation and detection, CRC generation and checking, and SDLC Loop mode operation.
6. Local Loopback and Auto Echo modes.
----------$HARP-----~-.-.--
460
Z8530/Z8530A Serial Communications Controller
•
LH8530/LH8530A
Block Diagram
Serial Data
Baud Rate
Generator
A
11
Synchronization
Wait/Request
16 Data Terminal
Ready /Request
17 Request To Send
10
Data Bus
18
Clear to Send
23 Request To Send
Data Terminal
Ready / Request
30 Wait/Request
24
Synchronization
Baud Rate
Generator
B
Channel Clock
Serial Data
...
"o
U
461
.-..---..
.............................,..... ..........,.....
Z8530/Z8530A Serial Communications Controller
~
•
..........,
LH8530/LH853t>A
--~
Pin Description
Pin
Function
""
I
Channel select signal.
Chip enable
I
Active low. Enables the CPU to transmit ,and 'receive
command and data when low.
Clear to send
I
Active low. Enables the respective transmitters.
D/C
Datal control select
I
This signal defines the type of information on the data
bus. High means data; Low indicates a command.
--
DCDA
DCDB
Data carrier detect
I
Active low. Enables the respective receivers.
Do-D 7
Data bus
-
CE
CTSA
CTSB
-
Bidirectional
3-state
System data bus.
INTACK
Interrupt acknowledge
I
RD
RXDA
RXDB
RTXCA
RTXCB
RTSA
-RTSB
SYNCA
--SYNCB
TXDA
TXDB'
TRXCA
TRXCB
WR
Read
I
Active low. These outputs follow the state programmed
into the DTR bit.
Active high. lEI is used to form a daisy chain that deter·
mines the interrupt priority order.
Active high. lEO is used to form a daisy chain that de·
termines the interrupt priority order.
Active low, open·drain. Indicates an interrupt request to
the CPU.
Active low. This signal indicates an active interrupt
acknowledge cycle.
Active .low. This signal indicates a read operation.
Receive data
I
Active high. These are receive data lines.
Receive/transmit clocks
I
Active low. These are communication clock lines.
Req uest to send
0
Active low. Goes high after the transmitter is empty.
Synchronization
1/0
Data terminal
ready I request
0
lEI
Interrupt enable input
I
lEO
Interrupt enable output
0
DTI3/REQA
DTR/REQB
-INT
Interrupt request
---
Open-drain
Transmitl receive clocks
PCLK
Active high. These are transmit data lines.
These are communication clocks.
1/0
Write
W/REQB
Active low. Indicates that a synchronization pattern has
been recognized.
0
Transmit data
--W/REQA
---
•
'I/O
Meaning
Channel AI
Channel B select
AlB
I
Open-drain
Waitl request
Clock
I
+5V
Absolute Maximum Ratings
Parameter
Input voltage
Output voltage
Active low. This signal indicates a write operation.
Active low. Operate as request lines when the DMA is
the bus master or as wait lines when the CPU is the bus
master.
Single-phase clock. It does not have to be the CPU clock.,
Symbol
VIN
VOUT
-0.3~+7
-0.3-+7
Unit
V
V
Operating temperature
Topr
0-+70
·C
Storage temperature
T st•
-65-+150
t
Ratings
From output
under test 0--.-.-114-..
+5V
From output
under test
o--{
2.2kO
J;5OpF
Open-drain test load
462
Z8530/Z8530A
•
Serial Communications Controller
LH8530/LH8530A
(Vcc=5V±5%, Ta=0-+70"C )
DC Characteristics
Parameter
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Current consumption
•
Symbol
VlH
VIL
VOH
VOL
I hL I
I IOL I
Icc
Conditions
MIN.
2
-0.3
2.4
IOH=-250pA
IOL=+2mA
0.4 ;;;; VIN ;;;; 2.4V·
0.4 ;;;; VOUT ;;;; 2.4V
Unit
V
V
V
V
pA
pA
rnA
0.4
10
10
250
( f= IMHz. Ta=O- +70"C )
Capacitance
Parameter
Input capacitance
Output capacitance
Bidirectional
capacitance
MAX.
Vcc+0.3
0.8
Symbol
CIN
"COUT
Conditions
MIN.
Unmeasured Pins Returned to Ground
CliO
•
AC Characteristics
(1)
CPU interface timing, interrupt timing, and interrupt acknowledge timing
No.
Symbol
Parameter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
TwPCl
TwPCh
TfPC
TrPC
TcPC
TsA(WR)
ThA(WR)
TsA(RD)
ThA(RD)
TsIA(pC)
TsIAi(WR)
ThIA(WR)
TsIAi(RD)
ThIA(RD)
ThIA(PC)
TsCEl(WR)
ThCE(WR)
TsCEh(WR)
TsCEl(RD)
ThCE(RD)
TsCEh(RD)
TwRDl
TdRD(DRA)
TdRDr(DR)
TdRDf(DR)
TdRD(DRz)
TdA(DR)
TwWRI
TsDW(WR)
PCLK low width
PCLK high width
PCLK fall time
PCLK rise time
PCLK cycle time
Address to WR l setup time
Address to WR t hold time
Address to RD l setup time
Address to RD t hold time
INT ACK to PCLK t setup time
INT ACK to WR l setup time
INT ACK to WR t hold time
INT ACK to RD l setup time
INT ACK to RD t hold time
INT ACK to PCLK t hold time
CE low to WR l setup time
CE to WR t hold time
, CE high to WR l setup time
CE low to RD l setup time
CE to RD t hold time
CE high to RD l setup time
RD low width
RD l to read data active delay
RD t to read data not valid delay
RD ! to read data valid delay
RD t to read data float delay
Address required valid to read data valid delay
WR low width
Write data to WR ! setup time
LH8530
MIN.
MAX.
105 2000
105 2000
20
20
250 4000
80
0
80
0
0
200
0
200
0
100
0
0
100
0
0
100
390
0
0
250
70
590
390
0
MAX.
10
15
Unit
pF
pF
20
pF
LH8530A
MIN.
MAX.
70
1000
70 1000
10
15
165
2000
80
0
80
0
0
.200
0
200
0
100
0
0
70
0
0
70
250
0
0
180
45
420
250
0
Unit
Note
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
i
1
1
1
2
.-.--.-----SHARP--..-r---~.-.~-..
463
.Z85~O/Z8530A
Serial Communications Controller
No.
Symbol
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
ThDW(WR)
TdWR(W)
TdRD(W)
TdWRf(REQ)
TdRDf(REQ)
TdWRr(REQ)
TdRDr(REQ)
TdPC(INT)
TdIAi(RD)
TwRDA
TdRDA(DR)
TsIEI(RDA)
ThIEI(RDA)
TdIEI(IEO)
TdPC(IEO)
TdRDA(INT)
TdRD(WRQ)
TdWRQ(RD)'
TwRES
Trc
48
49
Note
Note
Note
Note
Note
1:
2:
3:
4:
5:
LH8530/LH8530A
LH8530
MIN.
MAX.
0
240
240
240
240
Parameter
W rite data to WR t hold time
WR ! to wait valid delay
RD! to wait valid delay
WR ! to W IREQ not valid delay
RD ~ to W IREQ not valid delay
WR t to DTR/REQ not valid delay
RD t to DTR/REQ not valid delay
PCLK ! to INT valid delay
INT ACK to RD ! (acknowledge) delay
RD (acknowledge) width
RD ! (acknowledge) to read data valid delay
IEI to RD ! (acknowledge) setup time
IEI to RD t (acknowledge) hold time
IEI to IEO delay time
PCLK t to lEO delay
RD ~ to INT inactive delay
RD t to WR ~delay for no reset
WR t to RD ! delay for no reset
WR and RD coincident low for reset
Valid access recovery time
5Tcl'Ct300
5TcPCt300
500
285
190
120
0
120
250
500
30
30
250
6TcPCt200
LH8530A
Unit· Note
MIN.
MAX.
0
ns
200 ns
4
200 ns
4
200 ns
200 ns
5TcPCt250 ns
5TcPCt250 ns
4
500 ns
ns
5
250
ns
180 ns
100
ns
0
ns
100 ns
250 ns
4
500 ns
15
ns
ns
30
250
ns·
6TcPCt 130
ns
3
Parameter does not apply to Interrupt Acknowledge transactions.
Float delay is defined as the time required for a ±O.5V change in the output with a maximum DC load and minimum AC load.
Parameter applies only between transactions involving the SCC.
Open·drain output, measured with open·drain test load.
Parameter is system dependent. For any SCC in the daisy chain, TdlAi (RD) must be greater than the sum of TdPC (lEO) for the
highest priority device in the daisy chain, TslEI (RDA) for the SCC, and TdlEIf (lEO) for each device separating them in the daisy
chain.
PCLK
A/B,D/C-J'~~+-____~__-4__________~~~~~~______
INTACK
W/REQ (WAIT)
W/REQ (REQUEST) ________
DTR/REQ (REQUEST) ________
~--~~-J
~
____
~~~
__
~
__
~--J
Read and write timing
. . . . . - . - - - - - - - - - - - - S H A R P -----~---~----
464
Z8530lZ8530A Serial Communications Controller
LH8530/LH8530A
PCLK
IN TACK ________~=t~:3~~~------~~~::==~:::
RD
IEI __~~~__~~~.~~________~.~______lEO
-------"'F-
INT __________________________- J
Interrupt acknowledge timing
Reset timing
Cycle timing
(2)
System timing
No.
Symbol
1
2
3
TdRxC(REQ)
TdRxC(W)
TdRxC(SY)
TdRxC(INT)
TdTxC(REQ)
TdTxC(W)
TdTxC(DRQ)
TdTxC(INT)
TdSx(INT)
TdExT(INT)
4
5
6
7
8
9
10
Note 1:
Note 2:
Note 3:
Parameter
RxC t to W IREQ valid delay
RxC t to wait inactive delay
RxC t to SYNC valid delay
RxC t to INT valid delay
TxC ~ to W IREQ valid delay
TxC ~ to wait inactive delay
TxC ~ to DTR/REQ valid delay
TxC ~ to INT valid delay
SYNC transition to INT valid delay
DCD or CTS transition to INT valid delay
LH8530
MIN. -MAX.
8
12
12
8
4
7
10
16
5
8
5
8
4
7
10
6
2
6
2
6
LH8530A
MIN.
MAX.
8
12
8
12
4
7
10
16
5
8
5
8
4
7
6
10
2
6
2
6
Unit
Note
TcPC
TcPC
TcPC
TcPC
TcPC
TcPC
TcPC
TcPC
TcPC
TcPC
2
1,2
2
1,2
3
1,3
3
1,3
1
1
Open·drain output, measured with open·drain test load.
RxC is RTxC or TRxC, whichever is supplying the receive clock.
TxC is TRxC or RTxC, whichever is supplying the transmit clock.
----.-----~---SHARP--.-.-------
465
Z8530/Z8530A Serial Communication Controller
LH8530/lH8530A
RTxC, TRxC {RECEIVE)
W/REQ (REQUEST)
W/REQ (WAIT)
SYNC (OUTPUT)
====::::I:=~
INT
RTxC, TRxC (TRANSMIT)
W/REQ (REQUEST)
W/REQ (WAIT)
DTR/REQ(REQUEST)
CTS'DCD@'
SYNC (INPUT)
:
--+-----I:.C£~________________
INT
~~~'
System timing
(3) General timing
No.
Symbol
1
2
3
4
5
6
7
8
9
10
TdPC(REQ)
TdPC(W)
TsRXC(PC)
TsRXD(RXCr)
ThRXD(RXCr)
TsRXD(RXCf)
rhRXD(RXCf)
TsSY(RXC)
ThSY(RXC)
TsTXC(PC)
TdTXCf(TXD)
TdTXCr(TXD)
TdTXD(TRX)
TwRTXh
TwRTXI
TcRTX
TcRTXX
TwTRXh
TwTRXI
TcTRX
TwEXT
TwSY
11
12
13
14
15
16
17
18
19
20
21
22
Parameter
PCLK l to W IREQ valid delay
PCLK l to wait inactive delay
RxC t to PCLK t setup time (PCLK 7 4 case only)
RxD to RxC t setup time (Xl mode)
RxD to RxC t hold time (Xl mode)
RxD to RxC l setup time (Xl mode)
RxD to RxC l hold time (Xl mode)
SYNC to RxC t setup time
SYNC to RxC t hold time
TxC L to PCLK t setup time
TxC l to TxD delay (Xl mode)
TxC t to TxD delay (Xl mode)
TxD to TRxC delay (send clock echo)
RTxC high width
RTxC low width
RTxC cycle time
Crystal oscillator period
TRxC high width
TRxC low width
TRxC cycle time
DCD or CTS pulse width
SYNC pulse width
LH8530
MIN.
MAX.
250
350
80
0
150
0
150
-200
3TcPC+200
LH8530A
MIN.
MAX.
250
350
70
0
150
0
150
-200
3TcPC+200
0
0
300
300
200
180
180
400
250
180
180
400
200
200
1000
300
300
200
180
180
400
250
180
180
400
200
200
1000
Unit
ns
ns
ns.
ns
ns
ns
n~
ns
ns
ns
ns
ns
ns
ns'
ns
ns
ns
ngns
ns
ns
ns
Note
1,4
1
1
1,5
1,5
1
1
2,4
2
2,5
6
6
6
3
,3
6
6
~'---~'-'---SHARP .-~-.....-.-----.-.--
466
Z8530/Z8530A Serial Communications Controller
LH8530/LH8530A
Note 1:
RxC is RTxC or TRxC. whichever is supplying the receive clock.
Note 2:
TxC is TRxC or RTxC. whichever is supplying the transmit clock.
Note 3:
Both RTxC and SYNC have 30 pF capacitors to ground connected to them.
Note 4:
Parameter applies only if the data rate is one· fourth the PCLK rate. In all other cases. no phase relationship between RxC and
Note 5:
Parameter applies only to FM encoding/decoding.
Note 6:
Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to chip PCLK
PCLK or TxC and PCLK is required.
requirements.
PCLK
W /REQ (REQUEST)
Vi /REQ(WAIT) _ _ _ _-=:-~-------'.
RTxC, TRxC(RECEIVE) _ _ _..."...,.....J['1
. RxD ____~~~~~~-~~~--~-------SYNC (EXTERNAL)
----J~--~r---~'~-----------------
TRxC, RTxC (TRANSMIT)
.
-----j
TxD ~@==-:ii 1<""---"';'-~-.I
TR.C
'-_ ____
.
(OU:E~ ESj,,----.~ ---J~
CTS,DCD
SYNC (INPUT)
~ ~
1-
~ ~
1~------
-------........., i-@--i k=@~
, i--@----I i:=@~
General timing
~~....-.--------SHARP-.---.-.-.---
467
................._-_............................................._,._.......................
ZS,5301Z8530A Serial Communications Contr.oIler
,
•
Data Communications Capabilities
The LH85'30 provides two independ~nt fullduplex
channels programmable for use in any common
Asyncl1ronous or Synchron~)Us data communication
protocol. Fig. 1 illustrates th~se protocols.
START
PARITY
1
l~TOP
LH8530/LH8530A
first secondary station by the same process. Any
secondary stations without messages to send merely
echo the incoming messages and are prohibited from
placing messages on the loop (except upon recognizing an EOP).
SDLC Loop mode is a programmable option in the
LH8530. NRZ, NRZI, and FM coding may all be used
in SDLC Loop mode.
lli&ilJ
::":M'"="A":::R':':KI::"N:-::G:-IW@[]jl@illjr-DA
....r-Ar"T"I"Ij
II
LINE
ASYNCHRONOUS
I SYNC IDATA I
::
IDATAI CRe, I CRC, I
MONOSYNC
~IS-:-Y-NC~I-SY-N-C-rID~A....T....:1\TI~:; IDATAI CRC, I CRC, I
-----
. CONTROLLER
SIGNAL~YNC
~:~~I-:::DA~T~A~I....c~R~C~d....C-:::RC~,~I
EXTERNAL SYNC
Ir.:F=-LA-:-G=-I""AD--DR--ESS-.!~INFqRM.1 CRC, I CRc,lFLAGI
SDLC/HDLC/X.25
Fig. 1 Some see protocols
Fig. 2 An SOLe loop
•
SDLC Loop Mode
The LH8530 supports SDLC Loop mode in addition to normal SDLC. In an SDLC Loop, there is a
primary controller station that manages the message
traffic flow on the loop and any number of secondary
stations. In SDLC Loop mode, the LH8530 performs the functions of a secondary station while an
LH8530 operating in regula~ SDLC mode can act as
a controller (Fig. 2).
A secondary station in an SDLC Loop is alway
listening to the messages being sent a~ound the loop,
and in· fact must pass these messages to the rest of
the loop by retransmitting them with a one-bit-time
delay. The secondary station can place its own message on the loop only at specific times. The controller signals that secondary stations' may transmit
messages by sending a special character, called an
EOP (En,d Of Poll), around the loop. The EOP character is the bit pattern 11111110. Because of zero
insertion during messages, this bit pattern is unique
.
and easily recognized.
When a secondary station has a message to transmit and recognizes an EOP on the line, it changes
the last binary 1 of the EOP to a 0 before transmission. This has the effect of turning the EOP
into a flag sequence. The secondary station now
places its message on. Hie 10QP and terminates the
message with an EOP. Any secondary stations
further down the lO\Jp with Ijlessages to transmit can
then append their messages to the message of the
468
•
Data Encoding
Tile LH8530 may be programmed to encode and
decode the serial data in four different ways
(Fig. 3). In NRZ encoding, a 1 is represented by a
High level and a 0 is represented by a Low level. In
NRZI encoding, a 1 is represented by no change in
level and a 0 is represented by a change in level. In
FMi (more properly, bi-phase mark), a transition
occurs at the beginning of every bit cell. A 1 is represented by an additional transition at the center of
the bit cell and a 0 is represented by no additional
transition at the center of the bit cell. In FMO (biphase space), a transition occurs at the beginning of
every bit cell. A 0 is represented by an additional
transition at the center of the bit cell, and a 1 is represented, by no additional transition at the center of
the bit cell. In addition to these four methods, the
LH8530 can be used to decode Manchester (bi-phase
level) data by using the DPLL in the FM mode and
programming the receiver for NRZ data. Manchester encoding always produces a transition at the
center of the bit cell. If the transition is 0 to 1, the
bit is a o. If the transition is 1 to 0, the bit is a 1.
............... ...............- .....
.....
Z8530/Z8530A Serial Communications Controller
~~~
~~.....,~
DA T A -...:.'-----'''----.
NRZ
~______~
o
NRZI
FMl
FMO
MAN-
CHESTER
Fig. 3
•
Data encoding methods
Auto Echo and Local Loopback
The LH8530 is capable of automatically echoing
everything it receives. This feature is useful
mainly in Asynchronous modes, but works in Synchronous and SDLC modes as well. In Auto Echo
mode, TxD is RxD. Auto Echo mode can be used
with NRZI or FM encoding with no additional delay, because the data stream is not decoded before
retransmission. In Auto Echo mode, the CTS input is ignored as a transmitter enable (although
transitions on this input can still cause interrupts
if programmed to do so). In this mode, the transmitter is actually bypassed and the programmer is
responsible for disabling transmitter interrupts
and WAIT IREQUEST on transmit.
The LH8530 is also capable of local loopback.
In this mode TxD is RxD, just as in Auto Echo
mode. However, in Local Loopback mode; the internal transmit data is tied to the internal receive
data and RxD is ignored (except to be echoed out
via TxD). The CTS and DCD inputs are also
ignored as transmit and receive enables. However,
transitions on these inputs can still cause inter·
rupts. Local Loopback works in Asynchronous,
Synchronous and SDLC modes with NRZ, NRZI or
FM coding of the data stream.
•
Baud Rate Generator
Each channel in the LH8530 contains a programmable baud rate generator. Each generator
consists of two 8·bit time constant registers that
form a 16·bit time constant, a 16·bit down counter, and a flip· flop on the output producing a
square wave. On startup, the flip-flop on the output is set in a High state, the value in the time constant register is loaded into the counter, and the
counter starts counting down. The output of the
baud rate generator toggles upon reaching 0, the
value in the time constant register is loaded into
the counter, and the process is repeated. The
~
LH8530/LH8530A
~
time constant may be changed at any time , but the
new value does not take effect until the next load
of the counter.
The output of the baud rate generator may be
used as either the transmit clock, the receive clock,
or both. It can also drive the Digital PhaseLocked Loop (see next section).
If the receive clock or transmit clock is not
programmed to come from the TRxC pin, the out·
put of the baud rate generator may be echoed out
via the TRxC pin.
The following formula relates the time constant
to the baud rate (the baud rate is in bitsl second
and the BR clock period is in seconds).
baud rate
•
1
2(time constant +2) X(BR clock period)
Digital phase-Locked Loop
The LH8530 contains a Digital Phase-Locked
Loop (DPLL) to recover clock information from a
data stream with NRZI or FM encoding. The
DPLL is driven by a clock that is nominally 32
(NRZI) or 16 (FM) times the data rate. The DPLL
uses this clock, along with the data stream, to construct a clock for the data. This clock may then
be used as the SCC receive clock, the transmit
clock, or both.
For NRZI encoding, the DPLL counts the 32X
clock 60 create nominal bit times. As the 32X
clock is counted, the DPLL is searching the incom·
ing data stream for edges (either 1 to 0 or 0 to 1).
Whenever an edge is detected, the DPLL makes a
count adjustment (during the next counting cycle),
producing a terminal count closer to the center of
the bit cell.
For FM encoding, the DPLL still counts from 0
to 31, but with a cycle corresponding to two bit
times. When the DPLL is locked, the clock edges
in the data stream should occur between counts 15
and 16 and between counts 31 and O. The DPLL
looks for edges only during a time centered on the
15 to 16 counting transition.
The 32X clock for the DPLL can be programmed
to come from either the RTxC input or the output
of the baud rate generator. The DPLL output may
be programmed to be enchoed out of the LH8530
via the TRxC pin (if this pin is not being used as
an input).
...--....-.------SHARP--------
469
Z8530/Z8530ASeriai Communicatipns· Controller
•
LH8530/LH8530A
Read Regi/sters
• Read Register 0
• Read Register
Rx CHARACTER
AVAILABLE
ZERO COUNT
Tx BUFFER EMPTY
DCD
SYNC/HUNT
CTS
Tx UNDERRUN /EOM
BREAK/ABORT
• Read Register 1
to
o
LOOP SENDING
o
TWO CLOCKS MISSING
ONE CLOCK MISSING
• Read Register 12
I~I~I~I~I~I~I~I~I
RESIDUE CODE 0
RESIDUE CODE 1
RESIDUE CODE 2
PARITY ERROR
Rx OVERRUN ERROR
CRC/FRAMING ERROR
END OF FRAME (SDLC)
• Read Register 2
ID7 ID6 1 Ds 1 D. 1 D3 1 D2 1 DIlDo 1
[
INTERRUPT VECTOR"
[
LOWER BYTE OF
TIME CONSTANT
• Read Register 13
I D71 D6 1 Ds I D. I D3 I D2 I DII Do I
[UPPER BYTE OF
TIME CONSTANT
"MODIFIED IN CHANNEL B
• Read Register 3·
CHANNEL B
EXT/STAT Ip·
CHANNEL B Tx IP"
CHANNEL B Rx Ip·
CHANNEL A EXT/STAT IP"
CHANNEL A Tx Ip·
CHANNEL A Rx Ip·
o
• Read Register 15
o
o
ZERO COUNT IE
DCD IE
SYNC/HUNT IE
CTS IE
TxUNDERRUN/EOMIE
BREAK/ABORT IE
·ALWAYS 0 IN CHANNEL B
--------SHARP-------470
.28530/Z8530A Serial Communications Controller
•
LH8530/LH8530A
Write Registers
• Write Register 0
D7
D6
D5
D.
D3
• Write Register 2
D2
Dl
Do
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
1
1
0
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
1
0
0
1
0
1
0
1
0
1
1
0
1
1
I~I~I~I~I~I~I~I~I
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 4
REGISTER 5
REGISTER 6
REGISTER 7
REGISTER 8
REGISTER 9
REGISTER 10
REGISTER 11
SEGISTER 12
REGISTER 13
REGISTER 14
REGISTER 15
[INTERRUPT
VECTOR
• Write Register 3
*
NULL CODE
POINT HIGH
RESET EXT /STAT INTERRUPTS
SEND ABOR T (SDLc)
ENABLE INT ON NEXT Rx CHARACTER
RESET TxIN T PENDING
ERROR RES ET
RESET HIG HEST IUS
NULL CODE
RESET Rx CRC CHECKE R
RESET Tx CRC GENERA TOR
RESET Tx UNDERRUN/E OM LATCH
Rx ENABLE
SYNC CHARACTER LOAD INHIBIT
ADDRESS SEARCH MODE (SDLC)
Rx CRC ENABLE
ENTER HUNT MODE
AUTO ENABLES
o
o
0
1
1
0
1
1
Rx
Rx
Rx
Rx
5 BITS/CHARACTER
7 BITS/CHARACTER
6 BITS/CHARACTER
8 BITS/CHARACTER
• Write Register 4
·WITH POINT HIGH COMMAND (D 5D.D3=00I)
D7
D6
D5
D.
0
0
1
1
0
0
1
1
0
1
0
1
D2
1
1
0
0
1
1
0
1
0
1
Dl
I Do I
L Lp
• Write Register 1
EXT INT ENABLE
Tx INT ENABLE
PARITY IS SPECIAL CONDITION
o 0 Rx INT DISABLE
o
~R I§lJ'A~'i'AtI~~~8fi.1~~CTER
I-"--t-"-O"WRT SO::E~h.LL RCOCNHD1~tocNTERS
1
1 Rx!NT ON SPECIAL CONDITION
L.....:O....L.....::.....JONLY
WAIT/DMA REQUEST ON RECEIVE/TRANSMIT
WAIT/DMA REQUEST FUNCTION
WAIT/DMA REQUEST ENABLE
D3
0
1
0
1
ARITY ENABLE
PARIT Y EVEN/ODD
SYNC MO DES ENABLE
1 STOP BIT /CHARACTER
11/2 STOP BITS/CHARACTER
2 STOP BITS/CHARACTER
8 BIT SYNC CHA RACTER
16 BIT SYNC CH ARACTER
SDLC MODE (011 11110 FLAG)
EXTERNAL SYN C MODE
Xl CLOCK MODE
x16 CLOCK MODE
X32 CLOCK MODE
X64 CLOCK MODE
-~-~----SHARP'-'---------'
471
,LH8530/LH8530A
Z85.30/Z8530A Serial Communications Controller
•
Write Register 5
Tx CRC ENASLE
RTS
SDLC/CRC·16
Tx ENABLE
SEND BREAK
Tx 5 BITS (OR LEssl/CHARACTER
~-+-7-I
1---:'--+-7-1 Tx 7 BITS/CHARACTER
1, 0 Tx 6 BITS/CHARACTER
1
1 Tx 8 BITS/CHARACTER
DTR
Write Register 6
ID,I"' I D'~' ID~", ID, ID.I
I
. SYNC 7
SYNC!
SYNC7
SYNC3
ADR7
ADR7
•
SYNC,
SYNCo
SYNCs
SYNC2
ADRs
ADRs
I
SYNCs
SYNCs
SYNCs
SYNC!
ADRs
ADRs
I I
SYNC.
SYNC.
SYNC.
S.YNCo
ADR.
ADR.
I I
I
I
SYNC3
SYNC3
SYNC3
1
ADR3
SYNC2
SYNC2
SYNC2
1
ADR2
x
x
SYNC!
SYNC!
SYNC!
1
ADRI
x
1
SYNCo MONOSYNC, 8 BITS
SYNCo MONOSYNC, 6 BITS
SYNCo BISYNC, 16 BITS
BISYNC, 12 BITS
1
ADRo SDLC,8 BITS
x SDLC,4 BITS
(ADDRESS RUN)
Write Register 7
ID, ID.I D'~:, for the data. Similarly, an input port does not
indicate that it is ready for new data until the data
source indicates that the previous byte of the data
is no longer available, thereby acknowledging the
. input port's acceptance of the last byte. This allows
the LH8536 to interface directly to the port of a Z8
microcomputer, a UPC, an FlO, an FIFO, or to
another CIO port with no external logic.
i A 4·bit deskew timer can be inserted in the Data
Available (DA V) output for output ports.
The deskew timer guan,mtees that the output
data is valid for a specified minimum amount of
time.
, Deskew timers are available for output ports in·
dependent of the type of handshake employed.
(5) Strobed handshake.
In the Strobed handshake, mode, data is "strobed~'
into or out of the port by the external logic. Fig. 1
shows timing for the Strobed handshake. IN contrast
to the Interlocked handshake, the signal indicating
the port is ready for another data transfer operates
independently of the ACKIN input. It is up to the external logic to ensure that data oyerflows or under·
flows do not occur.
PCo
Bit 110
Bit 110
DAC(O)
RFD(I)
-IN/OUT(I/O)
at'the same time if RFQUESTlW AlT.
INPUT HANDSHAKE
DATA ~~______________
ACKIN
(INPUT)
STROBED HAND j
RFD ---t-"o<:::\ SHAKE-Y--- -.,.--(OUTPUT)
DATA MOVEDINTERLOCKED
DATA LATCHED TO INPUT
HANDSHAKE
IN BUFFER
REGISTER
REGISTER
OUTPUT HANDSHAKE
DA fA
---1
ACKIN
(INPUT)
NEXT BYTE
DESKEW TIME
Jfr----
DAV
,
(OUTPUT)
BUFFER NEXT BYTE
HANDSHAKE
REGISTER SHIFTED FROM
"EMPTIED" OUTPUT REGISTER TO
BUFFER REGISTER
LSTROBED
Fig.1
Interlocked and strobed handshakes
~.-----....--.-SHARP-.---------
483
Z8536/Z8535ACounter/Timer and Parallel 1/0 Unit .
(6) 3-wlre handsha~e .
.
The 3-wire handshake is designed for the ~itua- '
tion in which one output port' is communicating'
with many input ports simultaneously. It is essen:
tially the' same as the lnterlocked handshake, except that two signals are used to indicate if an input.
port is ready for new data or if it has accepted the
'present data (Fig. 2). With the 3-wire handshake,
the output lines of many input ports can be bussed
together with open-drain drivers; the output port
knows when all the ports have accepted the data
and are ready. This is the same handshake as is
used on the IEEE-488 bus. Because this handshake
requires three lines, only one port (either A or B)
can be a 3:wire handshake port at a time. The 3wire handshake is not available for the bidirectional
mode. Because the port's direction can be changed
under software control, however, bidirectional IEEE488·type transfers can be performed.
INPUT HANDSHAKE
DATA ~~____________
DAV
(INPUT)
RFD ---'-+1""'(OUTPUT)
~ ____+-__.J
DAC
(OUTPUT)
DATA SHIFTED
TO INPUT
REGISTER
OUTPUT, HANDSHAKE
DATA ____________~,~N~E~X~T~B_Y~T_E_
RFD
(INPUT) --:--:-:::-=-:::~---J
DAC
(INPUT)
DAV
(OUTPUT)
NEXT BYTE
BUFFER REGISTER SHIFTED FROM
OUTPUT REGISTER TO
"EMPTIED"
BUFFER REGISTER
Fig.2
3-wire handshake
(7) Pulsed handshake
The Pulsed handshake (Fig. 3) is designed to interface to mechanical-type devices that require
data to be held for long periods of time and need
relatively wjde pulses to gate the data into or out
of the device. The logic is the same as the Inter·
locked handshake mode, except that an internal
. LH85361LH8q36A
. counter/timer is linked to /the handshake logic.
The counter/timer maintjlins all of its n:ormal
capabilities. This handshake is not available for
bidirectional ports.
INPUT PORT
ACKIN
ACKIN
OUTPUT PORT
__
DA V
~TRIGGER
'
INPUr
_
Fig. 3
COUNTER~ _ ' _
. D AV
OUTPUT
C/T3
.
.
Pulse handshake
(8) Pattern-recognition logic operation
Both Ports A and B can be programmed to
generate interrupts when a specific pattern is recognized at the port. The pattern:recognition logic
is indePendent of the port application, thereby
allowing the port to recognize patterns in all of its
configurations.. The pattern can be independently
specified for each bit as 1, 0, rising edge, falling
edge, or any transition. Individual bits may be
masked off.
(9) Bit port pattern-recognition operations
During bit port 'operations, pattern-recognition
may be performed on all bits, including those used
as 110 for the counter/timers.
The pattern-recognition logic of bit ports operates in two basic modes: transparent and latched.
In transparent mode, the interrupt indicates that a
specified pattern has occurred~ but a read of the
Data register does not necessarily indicate that
state of the port' at the time the interrupt was
, generated. In the Latched mode, the state of all the
port inputs at the time the interrupt was generated
is latched in the input register and held until IP is
cleared.
(10) Counter/timer operation
The three independent 16-bit counter/timers
consist of a presettable Hi-bit down counter, a 16'
bit Time Constant register, a 16-bitCurrent Counter register, an 8·bit Mode Specification register,
an ,8-bit Command and Status register, and the
associated control logic that links these registers.
The flexibility of the counter/timers is enhanced
by ,the provision of up to four lines per counter/
timer (counter input, gate input,. trigger input, and
counter/timer output) for direct external control
and status. Counter/Timer l's external I/O lines are
-------I------SHARP,--~.---~--
484
Z8536/Z8536A
Couner/Timer and Parallel 1/0 Unit
2's trigger, gate, or counter input.
When linked, the counter/timers have the same
capabilities as when used separately. The only restriction is that when Counter/Timer 1 drives
Counter 2's count input, Counter/Timer 2 must be
programmed with its external count input disabled.
There are three duty cycles available for the
timer / counter output: pulse, one-shot, and squarewave. Fig. 4 shows the counter/timer waveforms.
Counter/timer operations require loading the
time constant value in the Time Constant register
and initiating the countdown sequence by loading
the down-counter with the time constant value.
The Time Constant register is accessed as two 8bit registers. The registers are readable as well as
writable, and the access order is irrelevant.
Once the down-counter is loaded, the countdown
sequence continues toward terminal count as long
as all the counter/timers' hardware and software
gate inputs are High. If any of the gate inputs Low
(0), the countdown halts. It resumes when all gate
inputs are 1 again.
provided by the four most significant bits of port B.
Counter/Timer 2's are provided by the four least
significant bits of Port B. Counter/Timer 3's external
110 lines are provided by the four bits of Port C. The
utilization of these lines (Table 2) is programmable
on a bit-by·bit basis via the Counter/Timer Mode
Specification registers.
Table 2 Counter/timer external access
Function
Counter ITimer Output
Counter Input
Trigger Input
Gate Input
CIT!
PB4
PB5
PBG
PB7
C/T2
PBo
PBI
PB2
PB3
LH8536/LH8536A
C/T3
PCo
PCI
PC2
PC3
Lines used for counter/timer 110 have the same
characteristics as simple input lines, they can be
specified as inverting or noninverting; they can be
read and used with the pattern· recognition logic.
They can also include the 1 's catcher input.
Counter/Timers 1 and 2 can be linked inter·
nally in three different ways. Counter/Timer l's
output (inverted) can be used as Counter/Timer.
PCLK/2aR~~
caUNTERINPUT
.
TRIGGER ~
GATE
-------,
L-J
fI
TC
! TC / TC-l/TC-l!TC-2/ .... I I !
PULSE OUTPUT
all
r-l
--------Irr------J
'-,I
ONE SHOT OUTPUT
SQUARE WAVE OUTPUT
(FIRST HALF) - - - - - - - - - - - - - 1 ( 1 1 - 1_ _.....J
SQUARE WAVE OUTPUT - - - - - - - - - - - - - - - f f l f f - - - - - - ,
(SECOND HALF)
Fig.4
Counter/timer waveforms
485
,
,
,
,"
,
".
,
\
,
LH8536/LH8536A'
Z8636/4853SA C.ount~r/Timer and Parallel 1/0,Unit
•
Internal Registers
The followings, illustrate the contents of the
registers and, In addition, given to register,
address summary.
•
Master Interrupt Control Register (MICR)
AIIdress : 000000
(Read/Write)
I'~I~I~I~I~I~I~I~I
MASTERmTERRUPT~
ENABLE (MfE)
DISABLE LOWER CHAIN (DLC)
I I
NO VECTOR (NV)
I LL=
,
PORT A VECTOR INCLUDES
STATUS (PA VIS)
PORT B VECTOR INCLUDES _ _ _ _ _----'
STATUS (PB VIS)
•
ILRESET
LRIGHT JUSTiFIED ADDRESSES
0= Si-lIFT LEFT (Ao from AD!)
1 = RIGHT JUSTIFY(Ao from ADo)
COUNTER/TIMERS VECTOR
INCLUDESSTATUS(CT VIS)
Master Configuration Control Register (MCCR)
Address: 000001
( Read/Write)
dJj
I
I D( I D61 D51 D.I D31 D2ID! I Do COUNTER/TIMER
\
PORT B ENABLE (PBE).J
~ LINK CONTROLS (LC)
LCI LCO
- 0 -0- COUNTER/TIMERS INDEPENDENT
0
1 CIT l's OUTPUT GATES CIT 2
1
0 CIT 1> OUTPUT TRIGGE~S CIT 2
,1 CIT 1 s OUTPUT IS CIT 2 s
COUNT INPUT
PORT A ENABLE (PAE)
PORT LINK CONTROL (PLC)
0= PORT,S A AND B OPERATE INDEPENDENTLY
1 = PORTS A AND B ARE LINKED
COUNTER/TfMER 1 ENABLE (CT,IE),
COUNTER/TIMER 2 ENABLE (CT2E)
PORT C AND COUNTER/TIMER 3 ENABLE
(PCE AND CT3E)
•
Port Mode Specification Register (PMSR)
Addresses: 1100000 Port A
101000 Port B
(Read/Write)
1L
I~I~I~I~I~I~I~I~I
PORT TYPE
PTS 1 PTS 0 SELECTS {PT
o 0 BIT PORT
o 1 INPUT PORT
1
0 OUTPUT PORT
1
1 BIDIRECTIONA L PORT
INTERRUPT ON TWO BYTES '(ITB)
SINGLE BUFFERED MODE (S B)
INTERRUPT ON MATCH ,ONL Y IMO)
~J
.
LATCH ON PATTERN MATCH (LPM)
BIT MODE)
DESKEW TIMER ENABLE (DTE)
HANDSHAKE MODES)
PATT:ERN MODE SPECIFICATION BITS (PMS)
PMSI
P MS'O
--DISABLE
PATTERN MATCH
0
0
"AND"MODE
1
0
"OR" MODE
1
1
1
" OR PRIORITY ENCODED
1
VECTOR" MODE
,
~~~~~,~'-~SHARP~~~--'-""""'-----
486
Z8536/Z8536A Counter/Timer and Parallel I/O Unit
•
LH8536/LH8536A
Port Handshake Specflcation Registers (PHSR)
'Addressess : 100001 Port A
101001 Port B
----'-T
(ReadIWrite)
I~I~I~I~I~I~I~I~I
HANDSHAKE TYPE
SPECIFICATION BITS (HTS)----.J
HTSO
HTSI
-o
o INTERLOCKED HANDSHAKE
o
1 STROBED HANDSHAKE
1
o PULSED HANDSHAKE
1
1 THREE-WIRE HANDSHAKE
DESKEW TIME SPECIFICATION
L---BlTS
SPECIFIES THE MSB's OF
DESKEW TIMER TIME CONSTANT.
LSB IS FORCED 1.
REQUEST/WAIT SPECIFICATION BIT(RWS)
RWS 2 RWS 1 RWS 0
FUNCTION
..
--0- --0- -O-REQUESTIWAIT DISABLED
o
o
•
I
1
1
0
1
0
0
1
1
1
1
0
1
OUTPUT WAIT
INPUT WAIT
SPECIAL REQUEST
OUTPUT REQUEST
INPUT REQUEST
Port Command and Status Registers (PCSR)
Addresses: 001000 Por A
001001 Por B
(Read/Partial Write)
.
I
II
D71 D61 Dsl D.I D31 D21Dl Do
INTERRUPT UNDER
I
SERVICE (IUS)--"
INTERRUPT ENABLE (IE)
• INTERRUPT PENDING (Ip)
IUS. IE·, AND IP ARE WRITTEN
USING THE FOLLOWING CODE:
I I III
NULL CODE
0
0
0
CLEAR IP & IUS
0
0
1
SETIUS
0
1
0
CLEAR IUS
0
1
1
SET IP
1
0
o·
CLEARIP
1
0
.1
SET IE
1
~
0
CLEAR IE
1
1
1
L,NTERRUPT ON ERROR (IOE)
PATTERN MATCH FLAG (PMF)
(READ ONLY)
.
INPUT REGISTER FULL (IRF)
(READ ONLY)
OUTPUT REGISTER EMPTY (ORE)
(READ ONLY)
'-------INTERRUPT ERROR (ERR)
(READ ONLY)
.
\ .
~'-~--'-----SHARP'----'-'---""--
487
---.....
........... -
Z8~6iz8536A6dunt~r/Timer and
~
•
Data Path Polarity Registers (DPPR)
_
..... ...............
...,............-.
Parallel' I/O Unit
ilH8536/lH8536A
Special 1/0 Contr.ol Registers (SIOCR)
•
Addresses: 100010 Port A
Addresses: 100100 Port A
101100 Port B
101010 Port B
000101 Port C (4 LS B
s only)
00Q111 Port C (4 LSBs only)
(Read;Write)
(Read/Write)
I~I~I~I~I~I~I~I~I
I.
1~1~1~1~1~1~1~1~1
,
i
DATA PATH POLARITY (DPP)
0= NON-INVERTING
1 = INVERTING
SPECIAL INPUT/OUTPUT (SIO)
0= NORMAL INPUT OR OUT PUr
. 1 = OUTPUT WITH OPEN DRAIN -OR
INPUT WITH I's CATCHER
•
•
Port Data Registers (PDR)
Addresses: 001101 Port A"
001110 Port B"
(Read/Write)
Data Direction Registers (DDR)
Addresses: 100011 Port A
101011 Port B
000110 Port C (4 LSBs only)
( Read/Write)
•
Port C Data Registers (PC DR)
Address: 001111"
( Read/Write)
I
DATA DIRECTION (DD)
0= OUTPUT BIT
1 = INPUT BIT
"These registers can be addressed directly.
4 MSBs
WRITING OF CORRESPONDING LSB ENABLED
1 = WRITING OF CORRSPONDING LSB INHIBITED
(READ RETURNS 1)
o=
•
Pattern Polarity Registers (PPR)
Addresses :·100101 Port A
101101 Port B
(Read/Write)
•
I D71 Dol Dsl D41 D31 D,I 011 Do
I
1
Pattern Transition Registers (PTR)
Addresses: 100110 Port A
101110 PortB
(Read/Write)
•
PM PT PP PATTERN SPECIFICATJ4)N
0
X BIT MASKED OFF
o 1 X ANY TRANSITION
o
o
o
.1
1
Pattern Mask Registers (PMR)
Addresses: 100111 Port A.
101111 Port B
( R ead/W rite)
1
1
0
(iERO
lONE
0 ONE TO ZERO TRANSITION(~)
1 ZERO-TO-ONE TRANSITION (l')
I~I~I~I~I~I~I~I~I
·LI____
-------~SHARP-.-------.-. ........... -~
488
Z8536/Z8536A Counter/Timer and Parallel I/O Unit
•
LH8536/LH8536A
Counter/Timer Command Status Registers (CTCSR)
Addresses: 001010 Counter/Timer 1
001011 Counter/Timer 2,
001100 Counter/Timer 3
( ead/Partial Write)
I~I~I~I~I~I~I~I~I
INTERRUPT
UNDER
SERVICE
(IUS) ~I
~ COUNT IN
INTERRUPT ENABLE (IE)-.
INTERRUPT PENDING (IP)
IUS, IE, AND IP ARE WRITTEN
USING THE FOLLOWING CODE:
NULL CODE
CLEAR IP & IUS
SET IUS
CLEAR IUS
SET IP
CLEARIP
SET IE
CLEAR IE
•
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
.
0
1
0
1
0
1
0
1
~
PROGRESS (CIP)
(READ ONLY)
TRIGGER COMMAND BIT (TCB)
(WRITE ONLY READ RETURNS 0)
GATE COMMAND BIT (GCB)
' - - - - - - READ COUNTER CONTROL (RCC)
(READ/SET ONLY CLEARED BY READING CCR LSB)
' - - - - - - - - - INTERRUPT ERROR (ERR)
(READ ONLY)
CounterlTimer Mode Specifications Registers (CTMSR)
Addresses: 011100 Counter/Timer 1
011101 Counter/Timer 2
Counter/Timer 3
(Read/Write)
.
I~I~I~I~I~I~I~I~I
J
JI
CONTINUOUS SINGLE CYCLE (C/SC)
EXTERNAL OUTPUT ENABLE (EOE)
EXTERNAL COUNT ENABLE (ECE)
EXTERNAL TRIGGER ENABLE (ETE)
EXTERNAL GATE ENABLE (EGE)
•
1\
---,-OUTPUT DUTY CYCLE
L....SELECTS (DCS)
DCS 1 DCSO
0
0
PULSE OUTPUT
0
lONE-SHOT 0lJ TPUT
1
0
SQUARE-WAVE OUTPUT
l I D O NOT SPECIFY
RETRIGGER ENABLE BIT (REB)
CounterlTimer Current Count Registers (CTCCR)
Addresses: 010000 Counter/Timer
010001 Counter/Timer
010010 Counter/Timer
010011 Counter/Timer
010100 Counter/Timer
010101 Counter/Timer
(Read Only)
l's
l's
2' s
2' s
3' s
3' s
MSB
LSB
MSB
LSB
MSB
LSB
I~I~I~I~I~I~I~I~I~I~I~I~I~I~I~I~I
MOST SIGNIFICANT BYTE-------'I
IL-----LEAST SIGNIFICANT BYTE
489
Z85361Z8536A
Counter1Timer and Parallel 110 Unit
,
LH8536/LH85.36A
• C6unterITimer Time Constant Registers (CiTCR)
Addresses: 010110
010111
011000
011001
. 011010
011011
Counter/Timer l's MSB
Counter/Timer l's LSB
Co~nt~r/Timel' 2' s MSB
Counter/Timer 2' s LSB
Counter/Timer 3' s MSB
Counter/Timer 3' s LSB
(Read/Write)
I
D71 D61 D51 D.I D31 D21 DII Do I D71 D61 D51 D41 D31 D21 DI I Do I
MOST SIGNIFICANT BYTE
I
• Interrupt Vector Register (lVR)
Addresses: 000010 Port A
000011 Port B
000100 Counter/Timers
(Read/Write)
I~I~I~I~I~I~I~I~I
L-,--LEAST SH;NIFICAi-n
• Counter/Timer Status
• D2
0
0
1
1
01
0
0
C/T3
C/T2
CITI
1
Error
1
..
I
INTERRUPT VECTOR
• Port Vector Status
(1)
x
(2)
Priority Encoded Vector Mode
X X
All Other Mode
ORE IRF PMF
o 0 0
490
Number of highest priority bit with a match
Normal
Error
• Current yector Register (CVR)
.Address : 011111
(Read only)
10 71 0 61 D51 D41 031 021 DilDo
I
I
INTERRUPT VECTOR BASED
ON HIGTEST PRIORITY
UNMASKED IP.
IF .NO INTERRUPT PENDING.
ALL 1's OUTPUT.
BYT~
Serial Parallel Combination Controller
LH8571
•
Serial Parallel Combination Controller
Description
The LH8571 (SPCC71) is a peripheral interface
device for general purpose microcomputer systems
with two main control functions for an RS232C interface and Centronics interface, all within a single
LSI chip.
The LH8571 provides a serial port for transferring data in asynchronous mode-and an 8-bit parallel port with handshaking function as a Centronics
interface.
The LH8571 has 24 commands for controlling
these ports. The commands not oI?ly control the operation of RS23.2C teminal units and printers, but
handle various utilities (e.g.,code conversion) necessary for these units. Accordingly, the CPU needs
merely to specity an operation through the commands, thus significantly reducing the CPU's load
in handling 110 units through the program, and
eventually reducing the amount of memory needed
for storing the program.
The LH8571 controls the peripheral unit control
lines (e.g.,RTS and CTS of RS232C interface)
according to the status oj the units, instead of by
software control from the CPU. Consequently, the
system designer can configure the interface merely
by connecting buffer devices and connectors.
•
LH8571
•
Pin Connections
-+5V
PCLK
2
o
RxD
TxD
DTR
CTS
INTACK
6
RD
7
DCD
RTS
SLCT
INPUT PRIME
BUSY
CS
GND
WAIT
FAULT
ACKNLG
DATA STROBE
_ DB7
DATAs
DB6
DATA7
DB5
DATA6
DB.
DATAs
DBa
DATA.
DB2
DATAa
DBI
DATA2
DBo
DATAl
Top View
Features
1. Asynchronous data transfer serial port
• RS232C interface can easily be realized.
2. Printer control parallel port
• Centronics interface can easily be realized.
3. Data transfer and conversion functions by command.
• 24 commands.
4. Data conversion function .
• Serial parallel conversion.
• Binary-ASCII conversion.
• Intel hex, format acceptable for data input/
output.
,
5. 128-byte data transfer bufter.
• Useful for the serial port and parallel port.
6. Non-multiplexed bus interface.
7. 40-pin dual-in-line package.
8. Single + 5V power s~pply.
491
, LH8571
Serial Parallel Combination Controller
•
Block Diagram
Data Bus
Data Bus
Internal
Control Logic
Chip
Interrupt Request
Interrupt Acknowledge
Interrupt Enable In
Interrupt Enable Out
492
5
6
4
3
Buffer
128
Bytes
LH8571
Serial Parallel Combination Controller
•
Pin Description
Meaning
Pin
DBo-DB7
AID
RD
WR
CS
WAIT
-INT
•
Data bus
Address/ data select
Read
write
Chip select
Wait
, Interrupt request
lIO
Bidirectional
3-state
I
I
I
I
0
0
INTACK
Interrupt acknowledge
I
IEI
Interrupt enable input
I
lEO
DATA1-DATA g
DATA STROBE
BUSY
ACKNLG
FAULT
INPUT PRIME
SLCT
RxD
TxD
RTS
CTS
DTR
DCD
PCLK
Interrupt enable output
Output data
Data strobe
Busy
Acknowledge
Fault
Prime input
Select
Received data
Transmitted data
Transmission request
Transmission enable
Data'terminal ready
Reception enable
Clock
0
0
0
I
I
I
0
I
I
0
0
I
0
I
I
Function
System data bus
Address/ data select signal
Active low. Indicate the system in read operation.
Active low. Indicate the system in write operation
Active low. Chip selection signal
Active low, open-drain. Used to synchronize with CPU.
Active low, open-drain. Indicate interrupt request to
input.
Active low. Indicate interrupt acknowledge cycle.
Active high. Used to form interrupt priority arbitration
loop circuit (daisy chain).
Active high. Used to form daisy chain.
Output data
Active low. Indicate settlement of data.
Active high. Indicate printer in operation.
Active high. Acknowledge signal from printer.
Active low. Indicate printer inoperable.
Active low. Printer initializing signal.
Active low. Printer selection signal.
Receiving data line.
Transmitting data line.
Active low. Indicate readiness for dflta transmission.
Active low. Indicate data transmission is possible.
Active low. Data transmission request signal.
Active low. Indicate data reception is possible.
Single-phase clock. Need not be same as CPU clock.
Absolute Maximum Ratings
Parameter
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
VIN
VOUT
Topr
Tstg
Ratings
-0.3-+7
-0.3-+7
0-+70
-65-+150
Unit
V
V
"C
"C
* The maximum applicable voltage on any pin with respect to GND.
+5V
From output
under test
Standard test load
---------~--.---SHARP
---.------.-,
493
LH8571
Serial Parallel Combination Controller
•
DC Characteristics
Parameter
Clock input high voltage
Clock input low voltage
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage curreot
Output leakage current
Current consumption
•
(1)
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
(Vee=5V±5%, Ta=0-+70t)
Test Conditions
Symbol
VeH
VCL
VlH
VIL
VOH
VOL
I IIL
IloL
Ice
I
I
IOH=-250,..A
IOL=2mA
0;;;; VIN;;;;5.25V
0;;;; VIN;;;;5.25V
AC Characteristics
CPU interface timing
Symbol
TrC
TwCh
TfC
TwCI
TpC
TsAlD(WR)
TsAlD(RD)
ThAlD(WR)
ThAlD(RD)
TsCSf(WR)
TsCSf(RD)
TsCSr(WR)
TsCSr(RD)
ThCS(WR)
ThCS(RD)
TsDI(WR)
Tw(WR)
Tw(RD)
ThWR(DI)
TdRD(DI)
ThRD(DI)
TdRD(DIz)
TdRD(DBA)
TdWR(W)
TdRD(W)
TdDI(W)
Parameter
Clock rise time
Clock pulse width, high
Clock fall time
Clock pulse width, low
Clock period
AID setup time to WR ~
AID setup time to RD ~
AID hold time from WR t
AID hold time from RD t
CS low setup time to WR ~
CS low setup time to RD ~
CS high setup time to WR ~
CS high setup time to RD ~
CS low hold time from WR t
CS low hold time from RD t
Written data setup time to WR ~
WR pulse width
RD pulse width
W ritteo data hold time from WR t
Delay time from RD ~ to valid data
Written data hold time from RD t
Delay time from RD t to data bus floating
Delay time from RD ~ to readout data settlement
Delay time from WR ~ to W AIT ~
Delay time from RD ~ to W AIT ~
Delay time from valid data to WAIT t
Note : All AC output characteristics are based on the stated load conditions.
Note 1: The delay time depends on the device status at the time of access by CPU.
494
MIN.
2.4
-0.3
2
-0.3
2.4
MAX.
Vee
'0.8
Vee
0.8
0.4
10
10
250
Unit
V
V
V
V
V
V
,..A
,..A
mA
(Vee=5V±5%, Ta=0-+70t)
MIN.
MAX.
20
105
20
105
250
80
80
30
30
0
0
60
60
0
0
0
390
390
0
0
70
0
150
150
0
Uoit
ns
ns
ns
os
ns
ns
os
ns
os
os
os
ns
ns
ns
ns
ns
ns
ns
ns
os
ns
ns
os
ns
ns
ns
Note
1
Serial Parallel Combination Controller
LH8571
PCLK
AID
DB o -DB 7
Write
----------+-----~~-I~
DB o-DB 7
Read
~~--_+--""fI1
CPU interface timing
(2)
Interrupt acknowledge timing
No.
27
28
29
30
31
32
33
34
35
Note 2:
Parameter
Symbol
INT ACK low setup time to RD
TsACK(RD)
TdRD(DI)
MIN.
!
Delay time from RD ! to valid vector
lNT ACK low hold time from RD t
ThRD(ACK)
ThIEI(RD)
255
0
100
255
IEI hold time from RD t
RD (Acknowledge) low pulse width
TwRDI
TdIEI(IEO)
TdACK(IEO)
TdADKr(IEO)
150
! to
lEO
Delay time from lNT ACK hoIEO
!
t
Unit
Note
ns
2
ns
ns
ns
ns
120
Delay time from IEI to lEO
IEl setup time to RD !
Delay time from INT ACK
TslEl(RD)
MAX.
90
250
250
ns
ns
ns
ns
Interrupt arbitration loop circuit (daisy chain) is not used.
Vector
I--@
\
INTACK
@i- f-
-
)
I
~@~
-®j
@--..
f--- @-
-K
lEI
rE-@~
lEO
1(
I---@l----oo
\
~.
7
Interrupt acknowledge timing
---.-.----~--SHARP
--.---------------495
, LH8Sn
Serial Parallel Combination Controller
(3)
Reset timing
Symbol
TdRDQ(WR)
TdWRQ(RD)
No.
36
37
38 TwRES
,
.Parameter
MIN.
Delay time from,RD t (for suppressing reset) to WR
Delay time from WR t (for suppressing reset) to, RD
Minimum low width of WR and RD(for resetting)
l
l
MAX.
40
' 50
250
Unit
ns
ns
ns
Note
3
Note 3: The internal reset signal lags by 1/2 to 2 clocks behind external reset conditions.
Reset timing
(4)
Serial port timing
No.
Symbol
39 TdTxC(T"xD)
Note 4:
Note,
Parameter
Delay time from sending clock transition to output data transition
4
Applies to all baud raets (110·9800 B)
k
TxC /
TxD
I
===========@=~-----------Serial port timing
(5)
No.
Parallel port timing
Symbol
40 TdACK (D)
41 TdD(DSTR)
42 TwDSTR
Parameter
Delay from ACKNLG l to data output
Delay from data output to DATA STROBE
DATA STROBE pulse width
MIN.
l
ACKNLG
DATAl
K
\
DATA.
"'"
"-"
DATA STROBE
,
~
f-@- f--@...
Parallel port timing
496
'MAX.
13000 18000
6000
6000
Unit
ns
ns
ns
Note
Serial Parallel Combination Controller
•
LH8571
Table 1 Register address
Register
The
can be
•
•
•
LH8571 has the following registers which
accessed externally (from CPU).
Master interrupt control register (MIC)
Data indirect register (DIND)
Data status command registers (DSCO,
DSCl, DSC2, DSC3, DSC4, DSC5 and
DSC8)
Register
DSCO
DSCI
DSC2
DSC3
DSC4
DSC5.
DSC8
DIND
MIC
Register address
X X XOOOOO
X X XOOOOI
X X XOOOI0
X X X 00011
X X XOOI00
X X XOOI0l
X X XOI000
X X X 10101
XXXI1110
Note: A7-A, is decoded and applied to CS, so that the location in the input/output address space is determined.
Bits marked by 'x' are undefined.
DSC31 D71 D61 Ds I D.I D3 I D21 DJ I Do I
-,-,-,---,- L
01 Buffer overflow
1 0 Input characters are other than 0 - F .
(Intel format only)
11 Check -sum error (Intel format only)
1 Printer unselect
o
1 0 Printer paper out Cexternal" circuit required)
11 Printer fault
T ransf er error
Limit error
Parity error
I llegal command
Fig. 1
Error flag (DSC3)
Table 2 MIC register write code
The master interrupt control register (MIC) is
used to control the interrupt operation (see Fig.
2). Writing into the MIC register falls into two
groups. Group 2 uses the write code shown in
Table 2.
Group
D7 D6
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
2 . G~oup 1
Ds D2 Do
0 X X
1 0 0
0 0 0
1 0 0
0 0 0
1 0 0
0 0 0
1 0 0
Function
Writing to Do and D2
Reset IP CDs) and IUS CD 6 )
Set IUS CD 6)
Reset IUS CD 6 )
Set IP CDs)
Reset IP CDs)
Set IE (D7)
Reset IE CD 7)
497
LH8571
Serial Parallel Combination Controller·
1TT.
MIC L::::II=E:-,-II=U=sl~I=P:-LI_J.-...-"§==L=CJ...1~IC=S-:TI
T
~Command execution start
Lower chaining prohibited
L - - - - - - - - - - I n t e r r u p t holding
Interrupt under service
Interrupt enabled
Fig.2
Master interrupt control register
•
Programming
Use the registers, DSCO, DSCl, DSC2, DSC3,
DSC4, DSC5, and DSC8, to specify operation mode.
The 24 types of commands are made valid by first
writing a value corresponding to the desired command number into DSCO, then setting the CST bit
on MIC. The registers DSCl, DSC2, DSC4, and
DSC5 are used to specify parameters f()r each command. Command is used inspecifying serial data
format using DSC2 (Fig. 3).
The result of command execution is indicated on
DSCO and DSC3. DSC3 indicates error status as
shown in Fig. 1. DSC8 is used as a buffer register
after command 22 or 23 is executed.
Tables 3 and 4 show command functions versus
registers.
°
T
ooc21~1~1~1~1~1~1~1~1
- - -:,-r-
T.
Parity mode
o :Even parity
1 : Odd parity
Number of data bits
o : 7 bits
1 : 8 bits
'-----~---
Baud rate (see Note)
000 : 1l0B
001 : 150B
010 : 300B
011 : 600B
100 : 1200B
101 : 2400B
110 : 4800B
111:9600B
' - - - - - - - - - - - - N u m b e r of stop bits of transmission
o : 1 bit
1 : 2 bits
' - - - - - - - - - - - - - I n t e r r u p t mode
o : Interrupt enabled
1 : Interrupt disabled
' - - - - - - - - - - - - - - - E c h o back
o : Echo back mode
1 : Echo back disabled
Note: The baud rate described above is for PCLK=4.0MHz
Fig. 3
498
Serial data format (DSC2)
LH8571
Serial Parallel Combination Controller
Table 3
Command function and writing register contents
~
Code
DSCO
0
OOH
1
01H
2
02H
Number of
output bytes
3
03H
Number of
output bytes
4
04H
5
05H
Number of
bytes of block
transfer
6
06H
Number of
output bytes
Output starting
address
7
07H
Number of
output bytes
Output starting
address
8
08H
Number of
output bytes
Output starting
address
9
09H
Number of
output bytes
Output starting
address
10
OAH
Number of
output bytes
Output starting
address
11
OBH
Number of
output bytes
Output starting
address
12
OCH
Number of
iutput bytes
Nunber of
output bytes
13
ODH
Command
DSCI
Parameter
DSC4
DSC2
Transfer for·
mat and oper·
ating mode
Stop character
DSC5
Function
Remarks
Specify transfer format
and operating mode.
Output serial·input data to
Stop character is spe·
Centronics printer until
cified by DSC2.
the stop character arrives.
Operaion stops upon de·
Output serial·input data to
tection of Control C (hex
Centronics printer.
03).
Output buffer area con·
Load address Load address
Address information
tents to serial port in Intel
(high order byte) (low order byte)
of data is appended.
format
Read Intel format data on
serial port and store in
buffer area.
Initialize block transfer
between master CPU and
buffer area.
Operation stops upon de·
Output data in buffer area
tection of Control C (hex
via serial port.
03).
Operation stops upon de·
Output data in buffer
tectiOD of Control C (hex
area to printer
03).
Convert binary data
in buffer area into
ASCII and output via
serial port.
Convert binary data
Display address Display address in buffer area into Address information
(high order)
(low order)
ASCII and output via of data is appended.
serial port.
Convert binary data
in buffer area into
ASCII, and output to
printer.
Convert binary data
Display address Display address in buffer area into Address information
(high order)
(low order)
ASCII, and output to of data is appended.
printer.
Read ASCII data on se·
rial port and store in
buffer area.
Read Intel format data Used when a reader
on serial port and store is connected to serial
in buffer area.
port.
.-....-------SHARP-.-~~-----
499
Serial Parallel Combination Controller
~
Code
DSCO
14
OEH
15
OFH
Number of
output bytes
16
10H
Number of
input bytes
17
11H
Number of
output bytes
IS
12H
19
13H
20
14H
21
15H
22
I6H
23
17H
Command
DSCI
Parameter
DSC4
DSC2
LH8571
DSC5
Function
Read ASCII data on serial
port until arrival of CR
code.
Convert data in buffer
Load address Load address area into Intel format,
(low order byte) (high order byte) and output via serial
port.
Read binary data on
Output character
serial 'port into buffer
area for storage.
Output data in buifer area
,
via serial ports.
Output starting
address
Output character
Remarks
After CR reception, CR
and LF codes are sent
out via serial port.
Used when a puncher is
connected to serial port.
Used when a reader
is connected to serial
port.
Used when a puncher is
connected to serial port.
Opertion stops upon detec·
tion of hex 03.
Output null codes via 256 null codes out·
serial port.
putted.
Output EOF in Intel for·
mat ( : 00000001 FF) via
serial port.
Used when a puncher
Output null codes via
is connected to serial
serial port.
port.
Output EOF in Intel for· Used when a puncher
mat ( : 00000001 FF) via is connected to serial
serial port.
port.
Read I-byte data on Data is stored in
serial port.
DSCS.
Output data written Data needs to be set
in DSCS by CPU via in DSCS prior to exserial port.
ecution.
--.-.--------SHARP----.-.-.-.---
500
Serial Parallel Combination Controller
Table 4
~
Cornman
0
1
2
3
Register contents after command execution (readout register)
Parameter
Code
DSCO
1*
LH8571
DSCI
DSC3\
DSC2
00
01
02
03
2*
80
81
82
83
3*
COH
Cl~
C2~
C3H
4
04
84
C4H
5
6
7
8
9
10
11
12
05
06
07
08
09
OA
OB
OC
85
86
87
88
89
8A
8B
8C
C5H
C6H
C7~
C8.H
C9H
CA~
CB~
CCH
13
OD
8D
CDH
14
OE
8E
CEH
Error status
15
16
17
18
19
20
21
22
23
OF
10
11
12
13
14
15
16
17
8F
90
91
92
93
94
95
96
97
CFA
DOH
DIH
D2H
D3H
D4H
D5H
D6H
D7H
Error
Error
Error
Error
Error
Error
Error
Error
Error
Note 1:
Note 2:
1
*:
3
*:
Error
Error
Error
Error
Number of bytes
input+20H
status
status
status
status
Value before command execution (command
code value)
2 *: Value upon normal completion of command ex·
ecution.
DSC5
Load address
(high order byte)
Load address
(low order byte)
Load address
(high order byte)
Number of bytes
flag·
input+20H
flag
flag
flag
flag
flag
flag
flag
flag
flag
Load address
(low order byte)
flag
flag
flag
flag
Error status flag
Error
Error
Error
Error
Error
Error
Error
Error
Number of bytes
input+20H
DSC4
status
status
status
status
status
status
status
status
flag
flag
flag
flag
flag
flag
flag
flag
Error status flag
Note 3:
status
status
status
status
status
status
status
status
status
If FAULT input becomes low (printer error) during
command execution, LH8571 suspends operation un·
til FAULT returns to high (error recovery). At this
time, DSCO has bit 6 set and bit 7 reset.
Value upon abnormal completion (error) of
command execution.
These are common to all commands.
For error status flag value, see Fig.I.
501
LH8572
•
The LH8572 (SPCC72) is a peripheral device
for general purpose microcomputer systems to perform asynchronous serial data tansfers and control of Centronics compatible printers.
It supports full duplex asynchronous serial data
transfers. The transfer conditions such as the
baud rate and character length can be set by the
program. Further, it is equipped with a control 1/
o terminal for simple organization of the various
types of modem interfaces. The Receive Buffer
has a double buffer structure so that the master
CPU can easily perform reading and writing of
data.
A printer control 1/0 terminal is available for
easy connection to any printer which is Centronics
compatible. A handshake line and control for other
I/O lines is supported. A 128-byte printer data
buffer memory having an· FIFO structure is provided within the LH8572. Efficient use of the
printer unit by the master CPU is made possible
with this buffer.
hi this way, the LH8572 peripheral device for
general-purpose microcomputers, was developed to
efficiently perform serial data transfer and printer
output control within a compact package. It is
suitable for use in small systems such as personal
computers which use printer units, RS232C terminal units and modem units.
Features
1. Asynchronous Full Duplex Data Transfer
• Character length of 5 to 8 bits
• 1 or 2 stop bits
• No parity bit or oddleven parity
• False start bit or rejection (rejects spike
noise in the mark line to prevent malfunction.)
• Full duplex
• Transmit buffer has double structure.
.; Receive buffer has FIFO structure.
• Error detection function, Parity error detection, Framing error detection, and Overrun
error detection
• Baud rates: 75, 110, 150, 300, 600, 1200,
2400, 4800 baud selectable
502
LH8572·
.....,.-.
.-..
Serial Parallel Combination Controller
. Description
•
_.... __
...
Serial Parallel Combination Controller
.-..-..-..-..-..-..-.....,.-:...,.
•
Pin Connections
o
RxD
TxD
DTR
CTS
OCD
RTS
NC
INPUT PRIME
BUSY
CS
GND
WAIT
FAULT
ACKNLG
DATA STROBE
DB,
DATAs
DB6
DATA,
DB5
DATAs
DB4
DATA5
DB3
DATA4
DB2
DATA3
DB!
DATA2
DBo
DATA!
Top View
.2. Centronics Compatible Printer Control
.
• Furnishes printer interface signals compatible with Centronics specifications
• Built-in handshake fUnction for data output
• Internal buffer: 128-byte FIFO structure
• Error detection: Printr fault error/Paper
empty error
3. Vector Interrupt'
• Able to generate an interrupt on various
conditions such as Transmit Buffer empty,
validity of received character, and Printer
Output Buffer empty.
• Interrupt vectors for Transmit, Receive,
Printer and Error detection can be set individually.
4. Non-multiplexed bus interface
5. 40-pin dual-in-line package
Serial Parallel Combination Controller
•
LH8572
Block Diagram
Internal
Control Logic
Data Bus
Data Bus
ERR
MSR
CTL
Print
FIFO
128Bytes
Chip
TxS
RxS
PRS
ECW LDE LOEI
RL
INCW INCW
XOR
XOR
R"IM IR"IM
10,5
10,5
----w:o
rt. Ira
18,0
R"R,
IR"R,
R"IM IR"IM
10,5
~
CLR
XOR
R,
6,5
IR,
6,5
rl. r,
12,0
RRC
RRC
LOC LOCI
R,
6,5
IR,
6,5
Irra Jr. , IrTI
12,0
18,0
SRA LDC LDCI
R,
6,5
IR,
6,5
R;
. IR,
CP
CP
CP
XOR
XOR
ra.Irf. Ira ,ITT!
6,5
LO
SWAP SWAP
lrll
CP
IRET
XOR
RCF
R
10,5
f •• X,
d~'~L"
20,0
CALL
DA
10,5
IRR,
10,5
10,5
LD
R"R,
LD
LD
6,5
IR"R,
10,5
LO
LO
Irll Ta
R"IR,
f ••
10,5
LO
t
SRA
IR,
8,5
14.0
RET
IR" R,
10,5
CLR
R,
8,5
10,5
R"R,
10,5
rl. Ta
RR
EI
r •• Irz
6,5
IR,
6,5
RR
6T
ro,5
CP
Tl
01
10,5
CP
6,5
6T
~
SCF
LD
ra.x, R
10,5
-
6,5
CCF
LD
R"IM IR.. IM
----a.o
NOP
~------------------~~------------------~~----~----~------------'~'~--------
Bytes per
Instruction
2
3
Lower opcode nibble
Execution cycles
1
Pipeline cycles
2
3
Legend:
R = 8-Bit Address
r = 4-Bit Address,
R1 or r 1 = Dst address
R2 or r2 = Src Address
Sequence:
Opcode, First Operand, Second Operand .
Upper opcode _ _ A
. nibble
Note: The blank areas are, not defined.
First operand
Second operand
"2·byte instrliction; fatch cycle appears as a 3·byte instruction,
--~-~-----,'--SHAAP
536
- - - - .......... -.--..-..r-~
Z8590/Z8590A Universal Peripheral Controller
LH8590/LH8590A
(6) Instruction summary
Instruction
I Addr. mode
and
Operation I
dst src
(Note 1)
AOC dst, src
dst-dst+src+C
ADD dst, src
(Note 1)
dst-dst + src
AND dst, src
(Note 1)
dst-dst AND src
CALL dst
DA
SP-SP-2
IRR
@SP-PC; PC-dst
CCF
C-NOT C
R
CLR dst
dst-O
IR
COM dst
R
dst-NOT dst
IR
CP dst, src
(Note 1)
dst-src
OA dst
R
dst-DA dst
IR
DEC dst
R
dst-dst-l
IR
RR
OECW dst
dst-dst-l
IR
01
IMR171-0
OJNZ r,dst
r+-r-l
if r+O PC-PC+dst
Range' +127--128
EI
IMR(7)-1
INC dst
dst-dst+ 1
RA
R
IR
RR
IR
INCW dst
dst-dst+l
IRET
FLAGS-@SP;SP-SP+ 1
PC-@SP'SP-SP + 2'IM~(7)-1
JP cc, dst
DA
if cc is true
PC-dst
IRR
JR cc, dst
RA
if cc is true,
PC-PC+dst
Ranl!e: +127--128
LO dst, src
1M
r
dst-src
r
R
R
r
LOC dst, src
dst-src
LOCI dst, src
dst-src
r-r+ 1; rr-rr+ 1
LOE dst, src
dst-src
r
Irr
Byte
(Hex)
10
X
r
Ir
r
R
IR
1M
1M
R
Irr
r
Irr
r
Irr
r
Flags Affected
CZSVOH
****0*
00
****0*
50
-**0--
D6
D4
------
EF
*-----
BO
Bl
60
61
AO
40
41
00
01
80
81
8F
rA
r=O-F
r
r
X
r
Ir
R
R
R
IR
IR
r
Irr
Ir
Irr
Opcode
-**0-****--
Inst~~~ron
I Addr. mode
Operation I
dst src
LOEI dst, src
Ir
Irr
dst-src
Irr
Ir
r-r + l' rr-rr + 1
NOP
(Note 1)
OR dst, src
dst-dst OR src
POP dst
R
dst-@SP
IR
SP-SP+l
R
PUSH src
SP-SP-l; @SP-src
IR
RCF
C-O
RET
PC-@SP; SP-SP+2
R
RL dst
IR
RLC dst
-***--***--
Flags Affected
CZSVOH
83
93
-----
FF
40
------
50
51
------
-**0--
70
71
CF
0
-
AF
****--
'~7 o~ IR
R
10
11
****--
RR dst
l.ru ~
ql
R
IR
EO
El
****--
RRC dst
4::D-I7 0~
R
IR
CO
Cl
****--
7
-----------
------
rE
r=O-F
20
21
AO
Al
BF
-***--
SRA dst
-***--
SRP src
RP-src
SUB dst, src
dst-dst - src
******
cD
c=O-F
30
cB
c=O-F
------
rC
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
E6
E7
F5
C2
D2
C3
D3
------
------
(Note 1)
SBC dst, src
dst-dst-src-C
SCF
C-l
9F
82
92
Byte
(Hex)
90
91
~
* * * X--
Opcode
4:£Jr111
, SWAP dst
-----------
****1*
DF
1-----
of IRR
DO
Dl
***0--
1M
31
------
20
****1*
FO
Fl
X**X--
(Note 1)
60
-**0--
(Note 1)
70
-**0--
(Note 1)
BO
-**0--
(Note 1)
~
TCM dst,src
NOT dst) AND src
TM dst,src
dst AND src
XOR dst,src
dst-dst XOR src
R
IR
Note 1: These instructions have an identical set of addressing
modes, which are encoded for brevity. The first opcode nibble is
found in the instruction set table above. The second nibble is expressed symbolically by a 0 in this table, and its value is found
in the following table to the left of the applicable addressing
mode pair.
For example, to determine the opcode of an ADC instruction
using the addressing modes r (destination) and Ir (source) is 13.
Lower
Addr Mode
------
30
dst
r
src
r
Opcode Nibble
[2]
r
R
Ir
[ill
[i]
R
R
IR
R
IR
1M
1M
lID
lID
ill
~-------SHARP----------------
537
Z8590/Z8590A Universal Peripheral Controller.
•
'. LH8590/LH8590A
Register
RO (DTC)
Date Transfer Control Regist~r
UPC register address (Hex): 00
I D7 I Da I Ds I D4 I D3 I D2 I Dl I Do I
(EOM) 0
(IRP) 1
I/O register pointer = 1
1 =:End of message
Disable data transfer =O _ _ _ _~(E=D:::X~):...J
(LERR)
Enable data transfer= 1
o =No
limit error
1 =Limit error
No transfer error= O_ _ _ _ _----oc(X""E=R:,.:.R"")c..J
Transfer error= 1
R4 (LC)
limit Count Register'
R5 (DIND)
Date Indirect Register
UPC register address (Hex): 04
UPC register address (Hex): 05
I D7 IDa' I Ds ID4 ID3 ID2 IDl IDo I
I~I~I~I~I~I~I~I~I
,-I-----Indirection address
(Do=LSB)
,-I- - - - L i m i t count value
(range: 0-255 decimal OO-FF Hex)
R240 (MIV)
Master CPU Interrupt Vector Register
UPC register address (Hex): FO
I~I~I~I~I~I~I~I~I
LI------Vector data (Do=LSB)
R241 (TMR)
Timer Mode Register
UPC register address (Hex): F 1
T OUT modes
Reserved= 00
Toout=OI
Tl out = 10
Internal clock out = 11
:=J
TIN I!lodes - - - - - '
External clock input = 00
Gate input = 01
Trigger input(non-retriggerable) = 10
Trigger input (retriggerable) = 11
538
L.o
=No function
1 =Load To
- 0 =Disable To count
1 =Enable To count
' - - - - - 0 =No function
1 =Load Tl
' - - - - - - - 0 =Disable Tl count
1 =Enable Tl count
Z8590/Z8590A Universal Peripheral Controller
LH8590/LH8590A
R242 (T1)
CounterlTimer 1 Register
R245 (PREO)
Prescilier 0 Register
UPC register address (Hex): F2
UPC register address (Hex): F5
I~I~I~I~I~I~I~I~I
COUNT MODE
0= To SINNGLE-PASS
I=ToMODULO-N
RESERVED
'--------PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
LTI INITIAL VALUE
(RANGE: 1-.258 DECIMAL
01-00 HEX)
R243 (PRE1)
Prescaler 1 Register
R246 (P2M)
Port 2 Mode Register
UPC register address (Hex): F3
UPC register address (Hex): F6
I~I~I~I~I~I~I~I~I
COUNT MODE
0= TI SINGLE PASS
1 = Tl MODULO· N
CLOCK SOURCE
o = EXTERNAL TIMING INPUT
(TlN)MODE
1 = Tl INTERNAL
' - - - - - - - - PRES CALER MODULO
(RANGE: }-64 DECIMAL
01-00 HEX)
I
P2o-P27 I/O DEFINITION
o DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT
R244 (TO)
Counter/Timer 0 Register
UPC register address (Hex): F 4
I~I~I~I~I~I~I~I~I
L I - - - - - T o INITIAL VALUE
(RANGE: 1-258 DECIMAL
Oi-OO HEX)
R247 (P3M)
Port 3 Mode Register
UPC register address (Hex): F7
I D71 D61 Ds]
Dd DdD 2 ~ DI
I Do I
L
o PORT
2 PULL-UPS
1 PORT 2 PULL-UPS
o PORT 1 PULL-UPS
1 PORT 1 PULL-UPS
o P3s= OUTPUT
1 P35= INT
RESERVED
o P33=INPUT
1 P33= DAVl!RDYI
o P31= INPUT (TIN)
1 P 31 = DA V2!RDY2
o P30= INPUT
1 P3D = lEI
o P32=INPUT
1 P32=INTACK
OPEN DRAIN
ACTIVE
OPEN DRAIN
ACTIVE
P3. = OUTPUT
P 3. = RDYI!DA VI
P 36 = OUTPUT (T OUT)
P 36 = RDY2!DAV2
P37= OUTPUT
P37= lEO
-.----------SHARP.....-..------.-.--
539
...........-....-..--------.-w.....--------Z859O'/Z859O'A Universal Peripheral Controller
LH859O'/LH8590A
I
R248 (PIM)
Port 1 Mode Register
upe register address (Hex): F8
1~1~1~1~1~1~1~1~1
1'-------P1ocPb I/O DEFINITION
o DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT
, R249 (IPR)
Interrupt Priority Register
upe register address (Hex): F9 (Write Only)
I D7 I D6 I Ds I D.
RESERVED
D3
I D2 I Dl I Do I
I
:J
1 = IRQ4 >IRQl
INTERRUPT GROUP PRIORIT Y
RESERVED = 00 0
C>A>B=OO 1
A>B>C=Ol 0
A>C>B=Ol 1
B>C>A=100
C >B >A =101
B >A >C =110
RESERVED = 111
IRQO, IRQ2 PRIORITY (GROUP B)
o = IRQ2 >IRQO
1 = IRQO > IRQ2
IRQ3, IRQ5 PRIORITY (GROUP A)
IRQ5 > IRQ3
1 = IRQ3 > IRQ5
o=
R252 (FLAGS)
Flag Ftegister
R250 (IRQ)
Interrupt Request .Register
upe register address (Hex): FA
I D7
D6
IRQl, IRQ4 PRIORITY (GROUP C)
o = IRQl >IRQ4
)
upe register address (Hex): Fe
I Ds I D. I D3 I D2 I D, I Do I
I
IRQO
= MASTER CPU
COMMUNICTAIONS
'- IRQ1 = P33 INPUT
- I R Q 2 = P3, INPUT
IRQ3 = P30 INPUT
IRQ4 = To
IRQ5 =T,
RES ERVED
USER FLAG Fl
USER FLAG F2
HALF CARRY FLAG
DE;CIMAL ADJUST FLAG
' - - - - - OVERFLOW FLAG
' - - - - - - SIGN FLAG
' - - - - - - - ZERO FLAG
'---------CARRYFLAG
R251 (IMR)
Interrupt Mask Register
upe register address (Hex): FB
R253 (RP)
Register Pointer
upe register address (Hex): FD
I~I~I~I~I~I~I~I~I
I D7 I D6 I Ds I D4 I D3 I D2 I D, I Do I
~~
,
ENABLES
ENABLES
1 ENABLES
1 ENABLES
1 ENABLES
1 ENABLES
R ESERVED
1 ENABLES
I
IRQO
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
I'-'..- - - - - - - - R E--DONT
CARE
GISTER
,-I
POINTER
(rrn)
INTERRUPTS
.
-.--.--.-.-.-----SHARP ------.-.-------540'
LH8590/LH8590A
Z8590/Z8590A Universal Peripheral Cotroller
R254 (MIC)
Master CPU Interrupt Control Register
UPC register address (Hex): FE
o INTERRUPT
0-
REQUEST DISABLED
1 INTERRUPT REQUEST ENABLED
1 END OF MESSAGE
o WAIT ENABLE
o NO INTERRUPT
WHEN WRITE
1 WAIT DISABLE WHEN WRITE
UNDER SERVICE
1 INTERRUPT UNDER SERVICE
o NO
' - - - - 0 ENABLE LOWER CHAIN
1 DISABLE LOWER CHAIN
MASTER CPU INTERRUPT PENDING
1 MASTER CPU INTERRUPT PENDING
o VECTOR
OUTPUT
1 NO VECTOR OUTPUT
L . . - - - - - O DISABLE DATA TRANSFER
1 ENABLE DATA TRANSFER
R255 (SP)
Stack Pointer
UPC register address (Hex): FF
I~I~I~I~I~I~I~I~I
C=STACK POINTER (SPO-SP7)
.-.--.-----SHARP-~--~--.-
541
LH8591'1LH8591A
Z8591/Z8591 A Development Device
LH8591/LH8591A
•
Description
The 64 pinLH8591 (Z8591) is the development
version of LH8590 Z8590 UPC with internal
mask-programmed RqM. This device allows user
to prototype the system in hardware with an actual
device and to develop the code that is eventually
mask-programmed into the on-chip ROM of the
LH8590.
The LH8591 is identical to the LH8590 with the
following exceptions.
• The internal ROM has been removed.
• The ROM address lines and data lines are buffered and brought out to external pins.
• Control lines for the new memory have been
added.
The LH8591A is the high speed version which
can operate at 6MHz system clock.
•
Z8S911Z8S91A
Development Device
Pin Connections
+5V
PCLK
P3,/IEO
P3o/IEI
P35/INT
P32/INT ACK
1
2
3
4
6
RD,
WRs
A/D
9
Ph
4
MDS
23
IACK,RD
24
PI.
Top View
542
Z8591/Z8591 A Development Device
•
LH8591/LH8591 A
Block Diagram
Data Bus
I/O
I/O
Interrupt Request 5
Interrupt Acknowledge 6
Interrupt Enable In
Interrupt
•
Pin Description
LH8591 has the same functions as those of a 40-pin device LH8590, and the functions of the additional
24 pins are as follows:
Pin
AD-All
Do-D 7
IACK/MR
-MAS
--
MDS
--
SYNC
Meaning
Program memory address
Program data
Interrupt acknowledge
Imemory read
lIO
0
I
0
Memory address strobe
0
Memory data strobe
0
Synchronization
0
Function
Used for the access to the external memory of 4 K bytes.
Reads the data through these lines from the external memory.
Active high. This signal becomes high during interrupt or in·
struction fetch cycle of LH8591.
Active low. This signal is output every memory fetch cycle
for the interface with the external ROM.
Active low. This signal becomes low during instruction fetch
cycle or write cycle.
Active low. This signal becomes low at the clock cycle just
before Op-code fetching.
----~--.-------SHARP--~--------
543
LH8592iLH8592A
Z8592/Z8592A Development Device
LH8592/LH8592A
•
Description
The 64 pin LH8592 (Z8592) is the development
version of LH8590 Z8590 UPC with internal
mask-programmed ROM. This device allows user
to prototype the system in hardware with an actual
device and to develop the code that is eventually
mask-programmed into the on-chip ROM of the
LH8590.
The LH8592 is identical to the LH8590 with the
following exceptions.
• The internal ROM has been removed. (But
there are 36 bytes internal ROM for a bootstrap program).
• The ROM address lines and data lines are buffered and brought out to external pins .
• Contorl lines for the new memory have been
added.
The LH8592A is the high speed version which
can operate at 6MHz system clock.
•
Z85921Z8592A
Development Device
Pin Connections
+5V
1
PCLK
2
P37/IEO
P30!IEI
P35/INT
3
MDS
MR/W flACK
4
5
23
24
Top View
......... :-.-.--.-.~-SHARP--.-.-.-----544
Z8592/Z8592A Development Device
•
LH8592/LH8592A
Block Diagram
Data Bus
I/O
1/0
Chip
Interrupt Request 5
Interrupt Acknowledge 6
Interrupt Enable In 4
Interrupt Enable Out 3
+5V
PCLK
1}-------------~
2}---------------~
GND171}-----------------~~
Interrupt Acknowledge
Output
24)--------------------~
•
Pin Description
LH8592 has the same functions as those of a 40-pin device LH8590, and the functions of additional 24
pins are as follows:
Pin
Ao-A 11
Do-D 7
Meaning
Program memory address
Program data
I/O
0
lACK
Interrupt acknowledge
0
MAS
Memory address strobe
0
MDS
Memory data strobe
0
Memory re,ad/write
0
Synchronization
0
-
MR/W
---SYNC
I
Function
Used for the access to the external memory of 4K bytes.
Reads/writes the data through these lines from the external memory.
Active high. This signal is always active during interrupt cycle of
LH8092.
Active low. This signal is output every memory fetch cycle for interfacing with the external RAM.
Active low. This signal becomes low during instruction fetch cycle
or write cycle.
This signal is high during instruction fetching by LH8592, or low
while writing into the external memory.
Active low. This signal becomes low during clock cycle just before
Op- code fetching.
-----.-.---------SHARP . - . - - - - - - - - - 545
lH8593iLH8593A
Z8593/Z8593A Protopack Emulator
LH8'593/ LH859 3A, ~~~a:!593A
•
Description
TheLH8593 (Z8593) is a ROM less version of
the standard LH8590 (Z8590) housed in a pin
compatible 40 pin package.
The LH8593 carries a 24-pin soket for a direct
interface to program memory. 2716 type EPROM
can be used- for program memory.
The -LH8593 allows the user to build the prototype and pilot production units. When the final
program is established, the user can then switch
over the LH8590.
The LH8593A is the high speed version which
can operate at 6MHz system clock.
•
Protopack
Pin Connections
o
P37/IEO
3
P30/lEI
4
I;'3;/lNT
5
P32/INTACK
6
DBo
Top View
546
LH8593/LH8593A
Z8593/Z8593A Protopack Emulator
•
Block Diagram
Program Data Input Program Memory Address Output
*1*2*3r
' "
'
Data Bus
I/O
I/O
Chip
Interrupt Request 5
Interrupt Acknowledge 6
Interrupt Enable In
Int errupl Enable OUI
*1
*2
*3
Program Memory Data Strobe Output
System Clock Output
Instruction Sync Output
~ : This is equipped witch ROM.
•
Pin Description
LH8593 pins are compatible with those of LH8590 . For pin description, refer to those of LH8590.
.-..-.-.--.---SHARP------~-~--
547
~8594/Z8594A
Protopack Emul;:ltor
LH8594/LH8594A
LH8594/LH8594A ~:=5S:A Protopack
•
De.scription
The. LH8594(Z8594)is a RAM version (16K bits
RAM) of the standard LH8590, housed in a pin
compatible 40 pin package.
The LH8594 carries a 24-pin soket for a direct
interface to program memory, and has 36 bytes of
internal ROM for a bootstrap program.
This device allows the user to build the prototype, and when the final program is established,
the user can then switch over the LH8590.
The LH8594A is the high speed version which
can operate at 6MHz system clock.
•
. Pin Connections
0
P36
P37/IEO
3
P27
P30/lEI
4
P26
P35! INT
5
P25
P32/INTACK
6
P2.
P23
P22
P2,
P33
P3.
Ph
PIs
Top View
548
LH8594/LH8594A
Z8594/Z8594A Protopack Emulator
•
Block Diagram
Program Data Input Program Memory Address Output
*1*2*3'
•
If
•
Data Bus
Interrupt Request 5
Interrupt Acknowledge 6
Interrupt Enable In
Interrupt Enable Out
* 1 Program Memory Data Strobe Output
* 2 System Clock Output
* 3 Instruction Sync Output
e : This is equipped with RAM.
•
Pin Description
LH8594 pins are compatible with those of LH8590.
For pin description, refer to those of LH8590.
------------------SHARP - - - - - - - - - - - - - - - 549
LH8661
Key"'encoder and Data Transmitter/Receiver
LH8661
•
I
Key-encoder and Data TransmitterlReceiver
Description
The LH8.661 is a high performance and multipurpose interface LSI which has functions such as
signal encoding from key matrix circuit, serial data
transmission/receiving and parallel data input/
output.
The LH8661 can be operated on one of the following five modes:
• Encodes a key matrix signal, and outputs the
data to a serial port (Mode 1).
• Encodes a key matrix signal, and outputs the
data to a parallel port (Mode 2).
• Encodes a key matrix signal, and outputs the
data to both serial and parallel ports (Mode 3).
• Encodes a key matrix signal, and outputs the
data to serial port, concurrently, serial input
data is converted to parallel and output to a parallel port (Mode 4).
• Parallel input data is converted to serial and output to a serial port (key scanning function is
sleep)(Mode 5).
•
Pin Connections
RTS
XTAL2
2
XTALI
3
0
CTS
SLCT
INPUT' PRIME
FAULT
RESET
6
BUSY
NC
7
KSO,
NC
9
KSO"
KS02
KSO,
DS/RQ
DCD
ACK/RD
12
DTR
DATAl
KSIs -
DATA2
KSI7
KSI6
KSI5
DATA.
DATA5
I
KSI.
DATA6
KS13
DATA7
KSI2
DATAs
•
Features
1. Key encoding
• 102 keys compatible with JIS ASCII array can
be encoded.
• Selectable encoding (compatible with ]IS
6220-1976 information exchange-code) or
no·encoding (native code).
• Encoded data can be transferred in serial or
output in parallel (mono/bi-modes available)
2. Serial data communication
• Encoded· key data can be transferred in asynchronous serial mode.
• Serial port can be used as an RS232C interface by attaching buffers.
• Selectable data format (data 7/8, parity, stop
bit 112).
• Selectable baud rate (110, 150, 300, 600,
1200, 2400, 4800, 9600, 19200).
3. Parallel data input/output
• Encoded key data can be output to a parallel
port in parallel.
• Parallel port can be used as a printer interface
compatible with Centronics by attaching buff-
Top View-
ers.
4. Serial/parallel data conversion
• This device can be used as a serial/parallel
data converter with/without a matrix key
board.
5. Data buffers 80 bytes X 1 or 40 bytes X 2.
6. On-chip crystal oscillator circuit.
7. Single+5V power supply
8. 40-pln dual-in-line package
-----------..--..-.--SHARP .....--.-.-----....-.--
550
LH8661
Key-encoder and Data Trahsmitter/Receiver
•
Block Diagram
Key
In -
Scan
Data
Parallel
Data
I/O
Logic
and
Control
Mode
Registers
Buffer
80
Byte
Encoder
Vee
Buffer
Pointer
1
GND
In~ernal
Control
Logic
~-------'-'--SHARP
_ _ _ _ _ _ _ _ _ _ _--.r
551
Key-encoder and Date Transmitter/Receiver
•
LH8661
. Pin Description
Pin
KSI 1 -KSI 8
KS0 1 -KS0 4
DATA 1 -DATA 8
-DS/RQ
--ACKIRD
BUSY
--FAULT
INPUT PRIME
SLCT
RxD
TxD
RTS
CTS
DTR
DCD
RESET
XTAL 1
XTAL 2
•
Meaning
Key scan input
Key scan output
I/O
I
0
Bidirectional
3-State
Data bus
Data strobel request
0
Acknowledge/read
I
Busy
Bidirectional
Fault
Bidirectional
Prime input
Bidirectional
Select
Bidirectional
Received data
Transmitted data
Transmission request
Transmission enable
Data terminal ready
Reception enable
Reset input
Crystal
I
0
0
I
0
I
I
Bidirectional
Function
Active low. Key scan data signal input
Key matrix scanning signal output
System data bus
Active low. Data strobe signal when mode 1 to 4 is
selected; request signal when mode 5 is selected.
Falling edge active. Acknowledge signal when mode 1 to
4 is selected; read signal when mode 5 is selected.
Active high. Indicate printer busy (input) when mode 1
to 4 is selected; indicate data buffer full (output) when
mode 5 is selected.
Active low. Indicate printer disable (input) when mode
1 to 4 is selected; indicate data buffer full when mode 5
is selected.
Active low. Output printer initialization signal when in
mode 1 to 4; input data buffer pointer initialization signal when in mode 5.
Active high. Input printer select signal when in mode 1
to 4; indicate that parallel data output is available to device when in mode 5.
Receiving data line.
Transmitting data line.
Active Low. Indicate readiness of data transmission.
Active Low. Indicate data transmission enabled.
Active Low. Data transmission request signal.
Active Low. Indicate data reception enabled.
Active Low initialization input.
7.3728 MHz crystal oscillator connected.
Absolute Maximum Ratings
Parameter
Input voltage
Output voltage
Operating temperature
Storage temperature
•
Symbol
VIN
VOUT
Topr
Tstg
Ratings
-0.3-+7·0
-0.3-+7.0
0-+70
-65-+150
Unit
V
V
'C
'C
(Vcc=5V±5%, Ta=0-+70"C)
DC Characteristics
Parameter
Clock input high voltage
Clock input low voltage'
Input high voltage
Input low voltage
Reset input high voltage
Reset input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Reset input current
Supply current
Conditions
Symbol
Driven by external clock.
VCH
Driven by external clock.
VeL
VIH
VIL
VRH
VRL
VOH
IOH= :-250,uA
VOL .IoL=2mA
0;£ VIN;£ +5.25V
IIL
0;£ VIN;£ +5.25V'
IOL
Vee=5.25V, VRI,=OV
IIR
lee
/
MIN.
3.8
-0.3
2.0
-0.3
3.8
-0.3
2.4
-10
-10
MAX.
Vee
0.8
Vee
0.8
Vee
0.8
0.4
10
10
-50
180
Unit
V
V
V
V
V
V
V
V
,uA
,uA
,uA
mA
Note
----~------SHARP.-----.--.-;...-
552
LH8661
Key-encoder and Data Transmitter/Receiver
Vee
Vee
Vee
2.1kO
From output
under test
18kO
From output
under test
Vee
1.5kO
:>O~.......-J .Xl~>:--O
74LS04
Test load 2
Test load 1
•
Crystal 2
15pF MAX.
L----o--o Crystal 1
;;;
15pF MAX.
External C. G. circuit
AC Characteristics
(1) Serial port timing
( i ) Reception
No.
Time from DCD
(Vee = 5 V ±5%. OSC freq. = 7.3728 MHz. Ta = 0 to +70°C)
Parameter
to DTR signal output
DCD
Symbol
Tb DCD(DIR)
Note
\
DTR
~
RxD
f-e---CD-
(ii)
No.
®
®
Transmission
(Vee
Parameter
Time from RTS ! to CTS signal acknowledge
Time from RTS ! to data (TxD) output
=
5 V ±5%. OSC freq.
Symbol
Td RTS(CTS)
Td RTS(TxD)
=
7.3728 MHz. Ta
=
MIN.
2.7
25
Unit
p.s
p.s
0 to +70°C)
Note
~
\
,
--®...;
®
----'--.-----------SHARP - . - - - - - - . - - . - . - 553
Key-encoder and Data Transmitter/Receiver
(2) Parallel port timing
(i)' Input
No.
CD
@
®
@
(Vcc=5 V ±5%, OSC freq.=7.3728 MHz,Ta=O to+70°C)
Parameter
INPUT PRIME pulse width
Time from INPUT PRIME t to RQ signal output
RQ pulse width .
Data settlement time from RD ~
INPUT PRIME
RQ
DATA1-DATA s
No.
®
®
(j)
®
Symbol
Tw IP
Td IP (RQ)
TwRQ
Tr RD (D)
MIN.
7.0
MAX.
13.8
4.3
16
Unit
ps
ps
ps
ps
Note
:
-~
~
~
' @ ' - - - -
- ------Jx{S@-j
I
~---------------------
------------------
RD
(ii)
LH8661
Output
(Vcc=5 V±5%, OSC freq. =7.3728 MHz, Ta=O to+70°C)
Parameter
Time from INPUT PRIME t to ACK ~
Time from ACK ~ to data output
Time from data to DS ~
DS pulse width
Symbol
TdIP(ACK)
TdACK(D)
TdD(DS)
TwDS
,
MIN.
5.0
23
5.4
2.6
MAX.
Unit
ps
ps
ps
ps
Note
INPUT PRIME
DATAl -DATAs
•
________-+____- J
Operation Mode Setting
The LH8661 is available in five operation modes which are obtained by combining the key data'
encode, parallel data transfer, and serial data
transfer functions (Fig_I). An Operation mode is
selected with mode switches (MODEI-MODE4)
which control the scan signal, SCANl, and key
scan input signals, KSI 5 -KSI8 .
•
Key Matrix Configuration
The key matrix consists of key scan input signals (KSIl-KSI s) and scan signals (SCAN l -SCAN l6 ).
The matrix requires status control circuit (switches plus diodes) in addition to the maximum 102
554
types of keyboard switches.
The status control circuit should consist of operation mode selector, transmit data format selector, and baud rate selector. The LH8661's operation mode is selected by these settings.
The compatible keyboard types, their configuration and status control switches on the key matrix
and shown in Fig. 3. Conformity of key data to the
1IS code requires the key arrangement shown in
Fig. 2. The status control circuit should consist of
the SCAN 1 -SCAN 2 and key scan input signals
(KSIl-KSI s). (Note. Shaded sections in the fig. are
not usable.)
Key-encoder and Data Transmitter/Receiver
m===lfi]] RS232C
~:
LH8661
Parallel 'output
RS232C
IlOI~I~
..--,.Q.
LH8661
lIII11 1Il\
•
i .Q.
serialoutputd :
LH8661
']}
\~
{}
1-=
~
.Serial outpu/4t •
':1! ;" II "
Keyboard
(i) Operation mode 1
]o!;/~~
Printer with
~
Centronics interface
Keyboard
(iv) Operation mode 4
-~:===;;;;=~--I~~ Serial output
D rn 0:=<)\
~
LH8661
I~
Parallel output
Centronics interface
(v) Operation mode 5
(ii) Operation mode 2
m===lfi]] RS232C
~O=<)CiLH8~~1 iJD=O~~
I..(J.
is I P arall~1 L::-----:---'
j_II\~utPut
@. ~ ~
Centronics interface
Serial !tput
Keyboard
(iii) Oyeration mode 3
Fig. 1
Description of device operation modes
9
SK 2
SP
SK 3
SK 4
+
SK 6
5
EXT
Control
key
r--
SK 5
6
*
SK 7
7
/
SKs
A
+
Notel: A, B and C are local scan blocks
Note 2 : Shaded sections in the diagram are not usable
Fig. 2
c
-I
Alphanumeric sectioni2j-KANA
.
(S I)
sectIon
(SO)
Key types and key arrangement
-~------SHARP-~-----'-
555
J
LH8661
Key'-encoder Data Transmitter/Receiver
•
Keyboard Matrix
(2) Transmit character codes
The LH8661 can encode key data into]IS or native codes. Fig. 4 shows the transmit character
codes that conform to the ]IS C 6220-1976 Information Exchanging Codes. Fig. 5 shows the native transmit character codes. The following figure
shows typical combinations of keyface symbols in
the alphanumeric and Kana sections of a key.
(1) Key types and arrangement
The LH8661 is capable of encoding data from
up to 102 types of keys arranged on a key matrix
which consists of key scan input signals. KSI1-KSIs•
and scan signals. SCAN 3 -SCAN 16 . The 102 types of
keys are divided into the following two blocks:
CD Data key block: Consists of 96 keys
arranged on the matrix composed of scan signals
SCAN 5 -SCAN 16 and key scan input signals
KSI1-KSI s . When the ]IS code system is selected
(code select switch at OFF). key data is encoded
into the transmit character codes shown in Fig. 5.
In this case the key arrangement shown in Fig. 3
is required. When the native code system is
selected (code select switch at ON). key data is en·
coded into the transmit character codes as shown
in Fig. 6.
® Control key block: Consists of six keys on
the matrix which is composed of scan lines
RCAN 3 -SCAN 4 and key scan input signals
KSI1-KSI s . These keys are used to control data
key encoding and key scanning. The shaded portion of the control key block shown in Fig. 2 is not
usable.
/
Alphanumeric section
b5
0
0
0
0
b.
0
1
b 3 _b 2 b 1 b o Coil
Row 0
1
I
/
/
/
. ;/
/@
:;I
Fig. 3 Keyface symbols
(3) Key entry operations
The LH8661 supports the following key entry
features:
• Key contact bounce time of approx. 5 ms.
• Two-key rollover an(l N-key lockout.
• Typamatic capability
If any data key other than those listed below is
0- 0
0
0
0
1
0
0
1
1
1
1
0
0
0
1
0
2
1
3
4
5
5P 0
IB
P
6
0
1
1
1
7
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
1
1
0
1
0
1
1
0
1
D
E
F
0
0
0
1
1
1
A
Q a
.b.
CD @
® @
0
0
1
0
2
..!
8 9 A B C
P SK16 SK1 5P - 9
q
SK 2 ,
7' -T
2
B
R
b
r
SK3
r
-1
.:/
;t
@ @
0
0
1
1
1
1
0
3 ETX
:11=
3
C
5
c
5
?
T
-t
® ® i
d
t
SK4 J
SK 5 ,
;r:
~
1
5
e
u
SK 6
>t
T
~
0
f
g
=
1
6
7
V
0
8
.:t-
:I (j) @
'7 ® @
I) ® @
1
9
/
JL-
0
A
/,
l;
0
0
0
0
0
0 1
0 1
1 0
1 0
1
0
1
0
1
1
1
1
1 1
1 1
0
0
1
1
0
0
1
0
0
4
$ 4 D T
% 5 E U
& 6 F V
7 G W
(
8 H X
B5
) 9
HTAB
I Y
: J Z
LF
ESC +
; K [
1
1
B
0
0
1
0
C
1
F 51
0
1
1
D CR
.
*
-
E 50
/
~ KANA section
(50)
0
1
)/
r-----:-, /
(51)
b7 0
b6 0
E
,
h
i
X
y
SK 7 '7 7J
SK 8 7 :fSK 9 -{ 7
SKIO
Ir
j
Z
SK11
W
L
¥
=
M
1 m
>
N
1\
n
? 0
-
0
I
I
'"
::J
-\" @ @
®
®
®
E5C+C(43H)
E5C+D(44H)
E5C+H(48H)
5K 17
E5C+E(45H)
@
5K18
E5C+J (4AH)
@
5K19
E5C+K(4BH)
;I-
~
~
I'l
@ @
-\'
Y
7
'7
@ @
}
SKI3
:J.
A_
......
:-- @ @
>I<
SK15
"
-I!
DEL
')
'?
.~
E5C(1BH)+A(41H)
E5C+B(42 H)
HOME
SK12
SK 14
t
(~)'
I
k
<
.,
:;I
,.
. @®
'@ @
Fig. 4 Transmit character codes (1) •.• J IS codes
---~--------~-SHARP-'-"'-'-------""-'---
556
Key-encoder and Data Transmitter/Receiver
b3
b2
b1
bo
b, b6 b 5 b4
0
1
0
1 0
0
1
0
0
0
1 0
0
1
0
1
0
1
0
1
1
1
1
LH8661
'0
0
0
0
1
1
1
1
.1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
0
0
1
1
0
1
A
B
C
D
E
F
p @
WJJ)
J v@
E
H
0
0
1
1
0
1
0
1
0
0
4
5
6
7
8
9
0
EXT
->
7
/
SKa
SK 16
SKIs
7'-\",
SK I4
6
CoIl
Row
0
0
0
1
1
ENTER
<-
6
*
SK 7
1 0
2
RETURN
~
5
-
SK6
1
1
0 0
0
1
1
0
3
4
5
6
i
4
LF
HOME
3
BS
SKI9
HTAB
ESC
SKIs
+
SKs
SK4
2
SP
1
9
SK3
SKI3
SK I2
SK 11
8(
&
;t
10
.J:
1
1
7
DEL
SKI7
0
T
.,
@
[ j r
'"
3:j:1: 7
SKI
SKg
-
/
=l'
"
®
--® u -j-®
*
'7
•
1 '@ 9 )
:I
3
I
--
Y
~
-
z ':/
X
.~
@.
it
@
(j]) C
'/
J:l
® ] .b.IJ V I:::@
D @
S
0
iv
?
® / ;t..
G ®
11
>
11
¥ I@ T (j) F
2 @ 0
;;r
-1
A
I
8
-(
R @
0
4$? A ® y
"'?
7
1
-t
%
5
7
SK
-iz
-t'
"
SK2
~
.:::L
®
*
:@
'r
B (j])
;+@ N
v
::::I
~
@
@ A 7® L IJ@ M@
'£:
o '7® Q;$ICD
K @ ,
/
<
,*'
Note: b 7 =1 when KANA key is ON, b7 =O when off.
Fig. 5
Transmit character codes (2)... Native codes
pressed and held for more than 1 second when the
lIS code sytem is selected, the corresponding
transmit character code is repeatedly entered at a
frequency of approx. 20 Hz. When the native code
system is selected, all the 96 data keys are effective for the auto repeat function.
IJ2EkJ [ESk] I BS I ILF I IHTABI I RETURN I
I ENTER II ETXI
The above control keys are not effective for the
auto repeat function.
•
Serial Data Transfer
The LH8661 transmits serial data via RS232C
interface when in modes 1, 3, or 5. It can transmit
and receive serial data when in mode 4_
The serial data format can be selected from 7
bits with parity, 7 bits with no parity (b 7 fixed at
'0'), and 8 bits with no parity. Selection is executed with bit 7 or 8 and with parity switch (see
description of transfer data format setting).
Fig. 6 shows the serial data format.
(1) Transmit mode
The LH8661 automatically adds one start bit
and two stop bits to transmit data. It holds TxD at
high to maintain mark status between characters.
(2) Receive mode
Receive data must have one start bit, eight data
bits, and at least one stop bit. While the receiver
has a two-stage buffer, data will not be protected
in the event of an overrun.
~-'-'-'-----SHARP-'-'------
557
..........
......................... .........................
Key':'encoder and bata Transmitter/Receiver
~~
LH8661
~~
~
~
Transmitted data (No parity)
T
.
1-
Start bitT·
' - - - - 8 data bits
' - - - - - - - - - - - - 2 stop bits
Transmitted data (With parity)
ISP ISP I P I b6 I bs I b. I b3 I b2 I bl I bo IST I
TT
.
L
start bitT
' 7 data bIts
L - - - - - - - - - - O d d parity
' - - - - - - , - - - - , - - - - - 2 stop bits
Reception data (No parity)
I bs I b. I b3 I b2 I bl I bo IST I
-r
I
T
Start bit
L _ _ _ _ _ 8 data bits
1 stop bit
Reception data (With parity)
I SP I P I b6 I bs I b. I b3 I b2 I b, I bo IST I
TT
I
StaJ;:t
- - - - 7 data bits
' - - - - - - - - - - - - O d d parity
' - - - - - - - - - - - - 1 stop bit
_
L.
Fig. 6 Serial data format
•
Parallel Data Transfer
When in modes 2, 3, and 4, the LH8661 can
transfer parallel data to a printer having Centronics interface. When in mode 5, it can receive parallel data through Centronics interface.
(1) Centronics interface (parallel data transmission)
The LH8661 maintains INPUT PRIME at low
for a given time period after being reset. The
attached printer usually uses this ~ignal to initialize its internal circuitry. The LH8661 then tests
the SLCT and FA UL T inputs to see whether or
not the printer is ready for operation. When transmitting data, the device also tests for BUSY signals from the printer. When signal is at high, the
printer is busy printing and the device waits for
the printer to become ready. When the printer returns to the ready status, it resets the BUSY sig-
) nal to low and sets the ACKNLG signal at high.
Seeing that the ACK signal (inverse of ACKLNG)
is set to active low, the LH8661 transmits print
data. It then sets the DS signal to low a given time
period after completing data transmission. The
printer uses the DS signal to read the data on the
data bus (DATA1-DATAs),and prints it.
The data transmission timing is shown in Fig. 7.
(2) Parallel data reception
When the LH8661 is placed in mode 5, the {larallel data port becomes a Centronics input port.
Input data received through this port can be \,lUt·
put in serial form after being subject to parallel-.
to-serial conversion. The control signal SLCT is
set to high when the LH8661 settles in mode 5.
In receiving parallel data, the INPUT PRIME
signal must be set to low for a given time period.
~'-'------SHARP---'----'-"---'-
558
Key-encoder and Data Transmitter/Receiver
LH8661
INPUT PRIME (output)-V
\~----------------------------------------------
BUSY (input)
ACK (input)
-'X. .___
DA TAl -DAT As (output) _ _ _ _ _ _ _ _ _
D_a_ta_se_tt_led
_ _ __
DS (output)
Fig. 7
Parallel port output timing
INPUT PRIME (input) ~
BUSY (output)
\'-----------------------
RQ (output)
-'X'-___
DAT Al -DAT As (input) _ _ _ _ _ _ _ _ _ _
D_at_a_s_et_tl_ed_ _ _ __
RD (input)
Fig. 8
Parallel port input timing
Receiving this low transition signal, the LHB661
responds by initializing the data buffer pointer
and setting both the BUSY and RQ signals to low.
Seeing that the ACKLNG signal is set to high,
the data output device outputs data, then sets the
DAT A STROBE signal to low after a given time
period. The LHB661 uses this signal to read data
off the data bus (DAT AI-DAT A8). The LHB661
then sets the RQ signal to low to repeat data read
operation until the data buffer becomes full.
When the data buffer becomes full, the LHB661
activates the BUSY and F AUL T signals to inform
the output device. The parallel port input timing is
shown in Fig. B.
•
Data Buffer
The LHB661 has a built-in BO-byte RAM for
data buffer, which is used to hold key entry data,
serial input data or parallel input data.
When the device is in mode 1, 2, or 3, the full
BO-byte length of the buffer is used to hold key
entry data. When the device is in mode 4, the buffer is divided into a 40-byte segment to hold key
entu data and another 40-byte segment to hold
serial input data. When in mode 5, the full
BO-byte length of the buffer is used to hold parallel input data.
When the buffer becomes full, the LHB661 behaves as follows:
• No longer writes key entry data into the buffer.
• During serial data input, sets the DTR signal to
high to indicate buffer-full status to the data:
output device (having RS-232C interface). The
LHB661 accepts no serial data transferred
while the DTR is at high.
• During parallel data input, activates the BUSY
--and F AUL T signals to indicate buffer-full status to the parallel data output device. The
LHB661 outputs no RQ signal while the BUSY
and F AUL T signals are active.
- - - - - - - - - - - - - - - - S H A R P -.-..-.....-.--~-
559
Support Tools for Micrcomputers
Development Support System SM-D-8000 IT
LH8DH110
LH8 DH 11 0 Development Support System SM-D-8000 II
•
Description
This system operates under control of the floppy
disk operating system (FDOS), and incorporates
software for developing Z80 application programs.
The software includes a relocatable macro assembler, a text editor, and a debugger. The system
facilitates Z80 software development ap.d minimizes developing time. In addition, program developing software for Z8, Z8000 and SM series
can also be used in this system. The system can
also be an aid for developing Z80A and Z8 systems by connecting the In-circuit Emulator (Z80A
or Z8) to the system. In conjunction with a PROM
writer, the system writers EPROMs directly further reducing developing time.
•
Features
1. Z80A CPU (clock frequency>: 4MHz)
2. RAM: 64K bytes
3. Two double-sided double-density floppy disk
drives in standard (capacity: 2M bytes)
2ports
4. -RS232C
20mA curren loop 1port
(shared with RS232C port)
•
Baud rate 110-19200B
(9 levels selective)
5. Optional hardware
PROM writer
Z81Z80B In-circuit Emulator etc.
Block Diagram
Protect SW .
F'DO
PRO SW
RS232C
RS232C
l.
MAIN CPU borad
SUB CPU board
system bus
FDJ'
POWER SW
562
Development Support System SM-D-8000 IT
•
LH8DH110
Software Organization
Control
processor
SM-D-8000II
Operating
system
Language
processor
----i[ Resident
monitor
Command line interpreter
-r
Resident software
ZOO (standard)
Cross software
(option)
Utilities
(option)
-E
~
High-level
language (option)
-l
--i
Text editor
Relocatable macro assembler
Linker
Librarian
Symbolic debugger
System generator
SM series software package
for I-chip microcomputer
Z8 cross-assemhler development
Z-UPC cross-assembler
Z8000 software package
PROM programmer
Z80B in-circuit emulator debugger
Z8in-circuit emulator de1:iugger
~ASCAL
FORTH
FORTRAN
COBOL
BASIC
CP/M is a registered trade mark of Digital Research Inc.
7
--.---.---SHARP....-..---~---
563
...............,.....,..........
Development Support System SM-D-a100
,
.......
......,.~.....,.....,.....,....,.....,
LH8-DH130
•
Development $upport
LH8DH136
,
.....,.....,.....,~
Syste~
SM-D-8100
Description
This system in based on the Z8001 CPU and
operates under control of the floppy disk operating
system (SM-DOS8100). The system provides a
standard set of software for developing Z8000
programs. There include C compiler, relocatable
macro assembler, text editor and linker for cost
effective software development. The SM-D-8100
consists of main unit and a floppy disk'drive
unit. The main unit is provided with four RS232C
ports so that the system can be connected to other,
devices. The system has 256K-byte of RAM for
flexible upgrading in the future.
•
Features
1. Z8001 CPU (clock frequency: 4MHz)
2. RAM: 256K bytes (1 parity bit per 8-bit)
3. Two double-sided double-density floppy disk
drives in standard (separate unit), (Capacity:
2M bytes)
4. Four RS232C ports Baud rate: 110-19200B
, (9 levels selective for each port)
5. Centronics parallel output port
6. High-grade language, C compiler in standard
7. Optional hardware:
SM-E-8100 In-circuit Emulator
------------SHARP---------.-...... ----564
Development Support System SM-D-8100
•
LH8DH130
Block Diagram
Z8001
CPU
MH
1-_-:---' ~::--------I ZBI Bus
Buffer. 1-'----11',
L-_~=====L_ _~4~M~H~z~------_4BCLK
ZBi Bus
Buffer
,+12V
-12V
'+
5V
'-T-r-...,-,r--r-r-"T""T'......
___ ___ ___ ..J, GND--...----r-;--.....
L...-._--I
•
Disk Drive
(FD 0 )
Disk Drive
(FDI)
AC 100 V
Software Organization
.---Control processor (standard)
Resident monitor
Lcommand line interpreter (CLI)
t--- Language processor
Resident software (Z8000) (Standard)
C compiler
Text editor
Relocatable macro assembler
SM-D-8100
Linker
Operating system t-librarian
(SM - DOS 8100)
Debugger
Translator (Z80-+Z8000) (Standard)
PASCAL (under development)
,
Floating point arithmetic routines (under development)
Cross software (Option)
,
Z80 cross assembler (Development planned)
Z8 cross assembler (Development planned)
Z - UPC cross assembler (Development planned)
I-
E
"--Utility (Option)
LGeneral-purpose OS (Pianned)
.-.....----------SHARP---~-~.-.-----
565
De,v.elopment Support System SM-D-820.O
LH8DH140
•
Development Support System SM-D-8200
Description
LH8DH140 is a microcomputer system using the
28001CPU. It is used as the microcomputer development support device or as the general-purpose
microcomputer system, with the SM- UX8000 gener
ai-purpose operating system mounted; which is based
on the system of Bell Laboratories.
•
Features
1. Main memory function
• 768K byte RAM
• 1 parity bit for each 8 bits
• Memory management function
2. Supplementary memory function
• Hard disc drive: 1
Winchester type, 8 inch, 20M bytes
• Floppy disc drive: 1
for back up of hard disc equipment
double-side double-density, 8-inch, 1M
bytes
3. I/O interface
• Serial I/O interface: 4 ports
RS232C compatible
Baud rate: 110-9600 for each port
• Parallel I/O interface: I-port
Centro nice compatible
4. Optional hardware
·28000 in-circuit emulator (SM-E-8100)
• 28000 evaluation board
• 28 in-circuit emulator
566
LH8DH140
Development Support System SM-D-8200
LH8DH140
.....................................................................................
•
Block Diagram
AC100V
::[)=I ~
,,r - - - ,
Power Supply
,,
- - -- Main Board Slot 0- - - ----,
I
RAM
512K Bytes
:
with Parity
Internal Bus
I I
I J '
I
~ ~ ~
"" "" ""
'+ "I
~
Z
,
L ____________
r - - - - - - - - - - - - --Main Board Slot 1
1
~Oo~
:
, r--:,
Clock
~
ROMmn
~8;~1
,
1--1,--'
Buffer ~
Memory-Bus
Buffer_
1
+ '"
ZBI
Bus
32K Bytes
1
,
I
--------'
- --- -- ---l
I
' - - Z8010 Memory RAM MMU
-Bus 256K Bytes
nr
with Parity
!
ZBI Bus
r-t--
I
OSC_
'Hz
,
, ~
Internal Bus
:
1
1
f--r--I
'I
,
4MHz BCLK
16MHz MCLK
r---------------
Main Board Slot 2 - - - - - - - - - ,
&~
~
III
~
N
L_'--_-_-_-_-_-_-_-_-_-_-_-_-_-_-_...::..;.._'--_-_-_-_--_--_-_L--.....l J
1
Control
ROM
8K Bytes
.-_ _ _...,J ~1l-----1 Hard
,
Disk
:
Drive
.--,------J---l ~I----; Control
W
Buffer
RAM
2K Bytes
I
1
rr-
I
.-.!-
DMA
I
~ ~~~e~us
I
'-----I-nt-'ernal Bus
1
:
1
1
1
,
I
1
1
Z80A CPU
1
L_____________
1
_ _________ ,
J
r - - - - - - - - - - - - - Main Board Slot 3- - - - - - - - - - - ,
--t
r;----l
r-ttr--i
Floppy
Disk Drive Control
,
I
1
I
r----1
~
DMA
Internal Bus
'
:
ZBI Bus
Buffer
II
L- - - - - - -.i.j - - - - -.u -J:±. -.ll----,.t..±. - - - - - - I
,
,
Z 8036 CIO
Centronix
Interface
Z 8030 X 2
RS232C Interface
Centronix Parallel Output
Floppy
Disk Drive
RS232C Ports
7
1
t----t--
_I
1--;--1----'
, ZBI is the
1 Trademark
-1
of Zilog_ Inc_
HD-10F
Hard Disk Drive
I
Power Supply
u
q
AClOOV
567
Development Support System SM-D-8200
•
LH8DH140
Software Organization
Kernel
Shell
System utilities
User access control
File managment
Status display
System maintenance
Program run control
SM-UX8000
Operating system
Software development tools
Languages
,
Assembler (For Z800l)
C compiler (For Z800l)
C source beautifying program: cb
C program checker:lint
Spreadsheet interpreter
FORTRAN 77 compiler (option)
:
Text processing
1__ Text editor:ed
Fstream editor:sed
Programming support
~
:
,
Debugger:
adb
Loader
SCCS (Source code control system)
Program maintenance program
Cross software
L
Z8 cross software
r=..= Z80 cross software
!
.-.-.----~--SHARP-------------
568
Z80B In-Circuit Emulator
LH8DH312
•
LH8DH312
Z80B In-Circuit Emulator
Description
This is an SM-D-8000 II option, which provides
emulation functions for Z80B systems. The emulator operates under the control of FDOS. It
facilitates debugging and reduces development time
and costs.
•
Features
1. Support Z80B (6MHz) system
2. Real-time emulation
3. User system memory: 64K bytes
4. User 110 port: 256 ports
5. Memory address mapping function (unit:4K
bytes)
6. Hardware break point: 2
(with 16-bit counter)
7. User system RAM: 64K-byte static RAM
8. In-circuit emulator debugger
9. Execution modes of user program
(i) Real-time
(ii) 1 step (number of steps can be set)
(iii) Trace
(iv) Snapshot
10. Program can be change at mnemonic.
11. I/O device if the user system can read the
RETI instruction in the user RAM.
12. All the interrupts (NMI,mode 0,1,2) can be
used by the user.
---~------SHARP--~~---~
569
LH.8DH312.
Z80B>ln-Circuit Emulator
•
Block Diagram
~------------------------------I
Address Bus
Adress Bus
:==:::;~====~
I===~>t~
Z80B
CPU
Data Bus
- Control
Bus
I Head Board
:
~SI/l.~I--"140Pin
Plug
'"
c6
I
9 Clock Selectabl,e
Fla Cable~
I
I
I Clock Circuit I._S_W_J CPU Unit
Main Board
--------------------------------,
I
_
I
I
I
I
I
I
I
I
I
I
I
.,
"
'--'-'--1'-1-t
I
!
.=i
I
I
I
I·
I
I
I
ROM
I
I
~--------------------------------~---------~
570
Z8 In-Circuit Emulator
n
LH8DH321
LH8DH321
Z8 In-Circuit Emulator
II
•
Description
Z8 in-circuit emulator II (LH8DH321) is a device which has the function to support the development of the Z8 MCU 8-bit single-chip microcomputer (4Kbytes internal ROM: LH0811/LH0813, 2K
bytes internal ROM: LH0801/LH0803)_ Software
developed by the host computer can be downloaded
via RS232C into this emulator for program debug
purposes.
Prototype Z8 application systems under development and developed systems can be emulated on
the real time basis.
By debugging the user system while emulating,
the development term of the user system or maintenance period becomes shorter.
•
1.
2.
3.
4.
5.
•
Features
Usable for 4K and 2K bytes internal ROM
Stand-alone type: load the program from the
host computer, and save the program to the
host computer after debugging.
Mapping RAM can be designated for memory
area both of program and data.
User program in the external ROM can be
transferred to the mapping RAM.
Possess line assembler and reverse assembler,
making debugging effective.
6. Break point possessing 8-bit break counter can
be set: up to 4096 in the internal ROM (up to
2048 in the 2K internal ROM) 1 in the external ROM/RAM.
7. Step and trace of user program can be executed.
8. Contents of user program and register can be
displayed and changed.
9. 110 ports and register files can all be executed
by the user.
Block Diagram
Z8
Data r-....L.--,
Bus
Z80A
CPU
J1
J2
Terminal Host
571
~
7
~=
LH8DH330
Z8000 Evaluation Board
LH8DH330
•
Z8000 .Evaluation Board.
Description
This board is designed for evaluating application
systems .using the Z8000 I6-bit microprocessor.
It is also available for a development system due
to the emulation function.
•
Features
1. User RAM: 32K bytes
2. Monitor ROM : 8K bytes
3. Break point :- I point
4. Support for debugging Z800I CPU Z8002
, CPU programs
5. In-circuit emulation functions
6. Object program execution : Real time, single
step, and trace
7. Connection with SM-D-BOOO IT /SM-D-8100
via RS232C interface
•
Block· Diagram
Segment
Z8001
Z8002
CPU
7
Address/Data
16
Control
7
Status
12
User's Connecter
16
Console
SM-D-8000 II
572
LHSDH340
ZSOOOln-circuit Emulator SM-E-S100
LH8DH340
•
ZSOOO In-circuit Emulator SM-E-SIOO
Description
The SM-E-8100 supports the development of
28000 systems based on either the 28001 or
28002. A developed program loaded in the user's
system memory or, the emulator memory (user RAM
area) can be executed in real time. The SM-E8100 can emulate not only programs supplied from
a host equipped with RS232C ports such as the
SM-D-8000 II or SM-D-8100 but can also operate as a stand alone system.
•
Features
1.
2.
3.
4.
Emulation for both 28001 and 28002
All I/O ports opened for the user
User-opened RAM: 32K bytes (e~pandable)
Hardware,break points (status, N/S, R/W, B/W
available)
5. Break point counter (16-bit) available
6. Program execution : Real time, single step,
trace, and snap shot
7. Down load and up load from a host computer
8. Built-in debugger (with 32 commands)
573
LH8DH340
Z8000 In ...Circuit Emulator SM-E-8100
•
Block Diagram
Option
r:-----::;]
I
Changeable
:
I
I
I
I
I
1--:-:---:---11
Z8000
1
CPU
"""7-<3"7'~1
_J
Control
Circuit
...
2
'j3
~
574
...
Break
Register
2
,·e
0
::;;
Break
Counter
Mem,ory
by User's
32 K Bytes
LH8DH403
PROM Writer
LH8DH403
•
PROM Writer
Description
This equipment operates under control of
SM-D-8000 II, FDOS. The control program is supplied on the floppy disk. The equipment writes
programs that have been developed by using
SM-D-8000 II into EPROMs directly, thereby reducing developing time.
•
Features
1. Applicable EPROM 2732A, 2764, 27128, and
equivalents
2. Either mnemonic or spelled-out commands
acceptable
3. Data management in file from
4. LED indication during command execution
•
Block Diagram
SM-D-8000 II
PROM Writer Unit
1-------
I---------------~~----I
I
I
Address
Bus
Buffer
Address Bus
I
I
I
" I
I
I
Add~!s
Bus
h====~
Buffer
Data
Data Bus
II
1..::
__
'L-
I
Drive
Signal
Data
Bus
1,--------,
I
Control
I
Bus
I
Buffer
I
I~
_ _~
IL _____ _
Buffer Board
__ JI
--....,I
PROM
Bus
Buffer
Console
II
IC
Socket
I
I
I
I
Control Bus
PIO
,------L.L..--,
Drive Circuit
I
Cable
I
I
I
I
I
I
I
IL _____________________ I
~
+21 V
+sv
DC
Power
Supply
AC 100 V
575
LU4DH200
8M Series Emulator 8ME-20
LU4DH200
•
SM Series Emulator SME;:;20
Description
The LU4DH200 is an emulator designed to support the development of programs for the SM series
of 4-bit single-chip microcomputers. It consists
of a data input and control key board, LED for display data, PROM writer and interface enabling·
programs can also be dev~loped in ,RAM by using
the RS232Cto connect it to SM-D-8000 II which
supports a cross-assembler and other software to
facilitate program debugging.
•
Features
1. PROM writer (2716, 2732) in standard
2. RS232C 1 port
Baud rate 150-19200B
(8 levels selective)
·3. Paper tape reader interface;Paper tape puncher interface in standard
4. Support all functions of SM series by altering
PROM for PLA
5. Function of the emulator
• Execute/halt program
• Display/change data
• One step operation
• Execute start point of CPU
• Repair address
576
SM Series Emulator SME-20
•
LU4DH200
System Configuration
The SME-20 can be connected through the RS
232C to the SM-D-8000 II to allow efficient prog·
ram debugging.
It can also be connected to other support tools
which run under the CP1M operating system and
equipped with an RS-232C interface.
Host computer
¢==>
L......_ _ _- - I
RS232C
Emulator
(SME-20)
L!======::!J
URS232C
SM evaluation
board
,-----------------,
SM-D-8000II
r----------------------------,
SME-20
Working
RAM
Floppy Disk
(containing the editor,
cross assembler, etc.)
ROM (1 K)
RAM (64 K)
________________________ -1
RS232C
SIO
~
PTP/PTR
L ________________
Terminal Unit
(Sharp Writer, etc.)
SM Series
Evaluation
Board
.-~------SHARP----.-----
577
LUXXXH2
SM Series Evaluation Board
LUXXXH2
•
SM Series Evaluation Board
Description
There are designed for evaluating the SM series
of 4-bit 1-chip microcomputers. The boards are
functionally and electrically equivalent to the mask
ROM version.
Programs can be developed either at the EPROM
level, or when used with any of the SM series support tools (SM-D-80, SM-D-8000 IT ) programs
can be developed at the RAM level.
•
Features
l. System debug with EPROM
2. Debug at RAM base in conjunction with support tool(SM- 0-80, SM- 0-8000 IT)
3. Function of the evaluation board
• Hold function
• One- step function
• Auto-stop function
• Display of the program counter
• Display of accumlator and carry F IF
• Display of RAM address, the register and
memory
• Display of instruction code
• PLA set function
---.-.......------SHARP-.-.-------578
LUXXXH2
SM Series Evaluation Board
•
Block Diagram
-~
-11-.===;;;::;-
I
* Crystal
Memory
Display
Circuit
asc
Circuit
Vc (-5V)
GND (OV)
Break
Address
Setting
Circuit
l!:
I
Programming
(2716,2732 or
equivalent)
~
'---~~
Instruction
Display
Circuit
Control Board
Evaluation Card
•
SM Series Evaluation Board
Control board
The evaluation board consists of two printed circuit boards: the control board and the evaluation
card (on which the evaluation chip and EPROM
socket installed).
Evaluation chip
Evaluation card
(LUXXXH4)
-~-----'------SHARP-'---'-'---
579
Memories
NMOS 32768-Bit Mask Programmable Read Only. Memory
LH2331 ILH2331 A
lH2331/LH2331A
NMOS 32768-Bit Mask Programmable Read Only Memory
•
•
Description
Pin Connections
The LH2331/LH23-31A are fully static mask
programmable ROMs organized as 4,096-wordby-8-bit by using silicon~gate NMOS process technology.
•
o
Features
1.
2.
3.
4.
5.
6.
4,096-word-by-8-bit organization
Single + 5V power supply
Fully static operation (no cloS;k required)
All inputs and outputs TTL compatible
Three-state outputs
Access time (MAX.)
LH2331 : 450ns, LH233iA : 350ns
7. Power-down function
8. 24-pin dual-in-line package (pin compatible
with i 2732 type EPROM)
•
Top View
Block Diagram
Data Output
~
Output Enable
Al\dress Input
32.768
Cell Matrix
---~'-------"--SHARP-~-----""--'
582
NMOS 32768-Bit Mask Programmable Read Only Memory
•
LH2331 ILH2331 A
Absolute Maximum Ratings
Parameter
Pin voltage *
Operating temperature
Storage temperature
Symbol
VIN
Topr
T st "
Ratings
-.0.3-+7 ..0
0-+7.0
-55-+15.0
Unit
V
"C
"C
*Application voltage on any input pin with respect to ground.
•
Parameter
Output low voltage
Output high voltage
Input low voltage
Input high voltage
Input leakage current
Output leakage current
Chip enabled power
supply current
Chip disabled power
supply current
•
(Vcc=5V±l.o%, Ta=.o-+7.o"C)
DC Characteristics
Symbol
VOL
V OH
VII.
V IH
I ILl I
I lLO I
Conditions
IOI.=2 ..omA
IoH = 2.0.0 p.A
Access time
Chip enable setup time
Output enable time
Output hold time
Chip turn-off time
TYP.
2.4
.0.8
D";:VIN";:V CC
CE:;;;; 2V, D::£VouT::£V cc
IccI
Icc2
MAX.
.0.4
2..0
-
CE:;;;;2V
Unit
V
V
V
V
1.0
1.0
p.A
f'A
11.0
rnA
5.0
rnA
(Vcc=5V±l.o%, Ta=D-+7.o"C)
AC Characteristics
Parameter
MIN.
Symbol
MIN.
MAX.
MIN.
45.0
45.0
12.0
t ACC
teE
toE
tOH
tDF
LH2331
TYP.
.0
.0
1.0.0
LH2331A
TYP.
MAX.
35.0
35.0
12.0
.0
.0
1.0.0
Unit
ns
ns
ns
ns
ns
Test conditions o(AC characteristics
• Input voltage amplitude········································ .. · + 0.4 - + 2.8V
• Input rising/falling time ··········································10ns
• Input threshold level ·······························,··············1.5V
• Output threshold level .. ··········································· 0.8V and 2.0V
• Output load condition .. ············································ 1TTL + 100pF
•
(f=IMHz, Ta=25"C)
Capacitance
Parameter
Input capacitance
Output capacitance
Symbol
CIN
COUT
Conditions
VIN=.oV
VouT=DV
MIN.
TYP.
MAX.
15
15
Unit
pF
pF
'-'-~--"--'--SHARP ----------~--------
583
. NMOS 327.68-Bit Mask Programmable.Read Only Memory
•
Timing
Diagram
CE
(High impedance)
584
LH2331 ILH2331 A
NMOS 3276e-Bit Mask Programmable Read Only Memory
•
LH2331/LH2331A
Electrical Characteristics Curves (Vcc=5V, Ta=25"C unless otherwise specified)
Access time vs. supply voltage
].
Access time vs. ambient temperature
.,..:
1.4,..---,----,----,-----,
Ta=700e
.
..
.~ 1 . 2 1 - - - - + - - - - + - - - - f - - - - I
1;;
;;
~r--.
P:::
u
~
.,
"
<:"
to
III
.,..
.::
].,
1.2
u
u
1.0
1.0 I-----+-==~_+---I_-__I
.,
'5
0.8
to
to
0.6
4.5
5.0
6.0
5.5
Supply voltage Vcc
-- ---
<:
80
N
U
G 60
....u
..
<:
-5
I-- ICCI
N
U
~ 60
~
~ 40
e'"
Icc2
~
j
20
III
0
4.0
<:
4.5
5.0
Supply voltage Vcc
5.5
...,.
1.4
.,'"
.,8-"
.,~
6.0
Ta=700e
.,..:
1.4
.,
-
Icc2
Vcc=4.5 V
.~
os
1;;
;; 1.2
P:::
P:::
'"
.j
.j
V
"'u
u
1.0
~
~
V
./
0.8
S
0
0.6
4.0
1.0
j
""
i 0.8
s=
Itl
r---,-
IcC!
CE to output delay vs. ambient temperature
os
>
.::
r----
100
25
75
50
Ambient temperature Ta (T)
0
<:
;; 1.2
...
..:.,
20
>
(V)
CE to output delay vs. supply voltage
.,..:
--
..
40
~
..
r--- I----
....9
..::-
"8-
80
~
~
~
50
75
25
Ambient temperature Ta (Oe)
Average supply current vs. ambient
temperature
f.----
.::i
o
(V)
Average supply current vs. supply voltage
e:::
0.8
.,
"
<:"
0.6
4.0
-5
~
.j
~
V
~
P:::
.,
:3
1.4
.. Vcc=4.5 \r
I ~u 0.6
4.5
5:5
5.0
Supply voltage Vcc (V)
6.0
o
25
50
75
100
Ambient temperature Ta ee)
585
NMOS 32768-Bit Mask Programmable Read Only Memory
LH2332/LH2332A
LH2332/LH2332A
NMOS 32768-Bit Mask Programmable Read Only Memory
•
Description
•
Pin Connections
The LH23321LH2332A are fully static mask
programmable. ROMs organized as 4,096 -wordby-S-bit by using silicon-gate NMOS process technology.
•
o
Features
1. 4,096-word-by-S-bit organization
Single + 5V power supply
Fully static operation (no clock required)
All inputs and outputs TTL compatible
Three-state outputs
Access time (MAX.)
LH2332 : 450ns, LH2332A : 350ns
7. Programmable chip selects (CS1/CS lo CSz/CS z)
S. 24-pin dual-in-line package (JEDEC standard
pin configuration)
2.
3.
4.
5.
6.
•
Top View
Block Diagram
Data Output
~
Address Input
32.768
Cell Matrix
----------SHARP-------------586
NMOS 32768-Bit Mask Programmable Read Only MemOry
•
LH2332/LH2332A
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
Vee
VIN
VOUT
Top,
T stg
Ratings
-0.3-+7.0
-0.3-+7.0
-0.3-+7.0
0-+70
-55-+150
Unit
V
V
V
·C
·C
* The maximum applicable voltage on any pin with respect to GND.
•
Parameter
Supply voltage
Input voltage
•
Input leakage current
Output leakage current
Current consumption
-
Symbol
Vee
V IL
VIH
MIN.
4.75
TYP.
5
MAX.
5.25
0.8
2.0
Unit
V
V
V
(Vee=5V±5%, Ta=0-+70·C)
DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
•
(Ta=0-+70·C)
Recommended Operating Conditions
AC Characteristics
Parameter
Access time
Output hold time
Chip enable setup time
Chi p turn -off time
Symbol
VIL
VIH
VOL
VOH
I ILl I
I ILO I
Icc
Conditions
MIN.
TYP.
MAX.
0.8
2.0
IOL =2.0mA
IoH = 200 p.A
0.4
2.4
O~VIN~Vce
10
10
110
CS~2V, O~VouT~Vee
Unit
V
V
V
V
p.A
p.A
rnA
(Vee=5V±5%, Ta=0-+70·C)
Symbol
tAce
tClH
MIN.
MAX.
450
0
teE
tDF
TYP.
0
350
150
Unit
ns
ns
ns
ns
Test conditions of AC characteristics
•
Input voltage amplitude··········································· + 0.4 - + 2.8V
• Input rising/failing time···········································l0ns
•
Input threshold level·· ......................................... ····1.5V
• Output threshold level·································· ........... 0.8V and 2.0V
• Output load condition·············································· 1TTL + 100pF
•
-
(f=IMHz, Ta=25·C)
Capacitance
Parameter
Input capacitance
Output capacitance
Symbol
CIN
COUT
Conditions
VIN=OV
VOUT=OV
MIN.
TYP.
MAX.
15
15
Unit
pF
pF
587
~NlOS 32768-Bit Mask Programmable Read Only Memory
•
Timing
Diagram·
cs
Valid data
(High impedance)
588
.LH.2332/LH2332A
LH2332/LH2332A
NMOS 32768-Bit Mask Programmable Read Only Memory
•
Electrical Characteristics Curves (Vcc=5V, Ta=25t unless otherwise specified)
Access time vs. ambient temperature
Access time vs. supply voltage
1.4r---..,.....--...,----,---__,
1.4
Ta=70'C
.a.
Vee=4.75 V
>
//
.~ 1 . 2 1 - - - + - - - - + - - - + - - - \
10
Q;
Il:::
tl 1.01-.=......+---+--~==:::::J
:;
.§
:; 0 . 8 1 - - - + - - - - + - - - + - - - \
V
.~"
O.s
(Il
(Il
:l
V
~
~
..:""
0.6"::-_~~-~-!-::----=-=--~
4.0
4.5
5.0
Supply voltage
5.5
Vee
..:"
0.6
0
6.0
50.
25
75
Ambient temperature Ta (OC)
(V)
Average supply current vs.
supply voltage
Average supply current vs.
ambient temperature
so
SOr---~--~--_,_--__,
--
I--- I---
..:
~
60~--+_--~--_+--~
~
100
u
.....u
.,...
.
"
b"
§'
'"
60
r---
0;
40
(Il
201---+---~--_+--_;
...~.,
.
"
~
..:>
..:>
O~-~~-~~-~_!_::_-~
4.0
4.5
5.0
5.5
6.0
Supply voltage Vee
o
(V)
Input voltage vs. supply voltage
:>
:x:
:>
."..
100
2.0r---.,...---..,.....--...,-----,
2::
1.7
1.7
~
:x:
:>
1.4
VIH(MIN.)
.g:,
i
VIL(MAX.)
.::0
-..
1.4 ~VlH(MIN.J
VILCMAX.)
>
>.
=
.=;'"
75
25
50
Ambient temperature Ta ('C)
Input voltage vs. ambient temperature
2.0
2::
,.,
20
1.1
....."'"
O.S
4.0
4.5
5.0
Supply voltage
Vee
5.5
(V)
6.0
1.1
O.S !-_~:!=---=-=----=---~
o
25
50
75
Ambient temperature Ta
100
('C)
589
NMOS 65536-Bit Mask Programmable Read'Oniy Memory
LH2362B
NMOS 6SS36-Bit Mask ProQrammable Read
Only Memory
•
Description
The LH2362B is a fully static mask programmable ROM organized as 8,192-word-by-8-bit by
using silicon-gate NMOS process technology.
•
LH2362B
•
Pin Connections
o
Features
1. 8,192-word-by-8-bit organization
2. Single +5V power supply
3. Fully static operation (no clock required)
4. All inputs and outputs TTL compatible
5. Three-state outputs
6. Access time (MAX.) : 250ns
7. 24-pin dual-in-line package UEDEC standard
pin configuration)
Top View
•
Block Diagram
Data Output
,A
Control
Signal
Generator
1!32X8
Column Address Decoder
Address
Input
.,.,
....,
."
."
<:
~
o
!X:.
590
65,536(256 X 32 X 8)
Cell Matrix
NMOS 65536-Bit Mask Programmable Read Only Memory
•
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
Vcc
VIN
VOUT
Toor
T st•
Ratings
-0.3-+7.0
-0.3-+7.0
-0.3-+7.0
0-+70
-55-+150
* The maximum applicable voltage,on any pin with respect to GND.
•
Input voltage
Symbol
Vcc
V1L
VIH
MIN.
4.75
TYP.
5
MAX.
5.25
0.8
2.0
Unit
V
V
V
DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
0fltput high voltage
Input leakage current
Output leakage current
Current consumption
•
Unit
V
V
V
'C
'C
Recommended Operating Conditions
Parameter
Supply voltage
•
LH2362B
AC Characteristics
Parameter
Access time
Chip enable setup time
Chip turn-off time
Output hold time
(Vcc=5V±5%, Ta=0-+70'C)
Symbol
V1L
VIH
VOL
VOH
I ILl I
I ILO I
Icc
Conditions
MIN.
TYP.
MAX.
0.8
2.0
IOL=2.0mA
IOH=200pA
VIN=OV-Vcc
CS~2V, VOUT=OV-Vcc
0.4
2.4
10
10
160
Unit
V
V
V
,V
pA
p.A
rnA
(Vcc=5V±5%, Ta=0-+70"C)
Symbol
t ACC
tCE
tDF
tOH
MIN.
TYP.
MAX.
250
100
100
0
Unit
ns
ns
ns
ns
Test conditions of AC characteristics
• Input voltage amplitude ........................................... + 0.4 - + 2.BV
• Input rising/falling time ··········································10ns
• Input threshold level································· ............. 1.5V
• Output threshold level· .. ··························· .. ············· O.BV and 2.0V
• Output load condition ·············································1 TTL+ 100pF
•
(f=lMHz, Ta=25'C)
Capacitance
Parameter
Input capacitance
Output capacitance
Symbol
CIN
COUT
Conditions
V1N=OV
VOUT=OV
MIN.
TYP.
MAX.
16
13
Unit
pF
pF
591
NMOS 65536-Bit Mask Programmable Read Only Memory
•
Timing
Diagram
Ao-A12
~--tACC--~
(High impedance)
•
Chip Select
L
H
592
DouT (Data output)
High impedance
Valid data
LH2362B
NMOS 65536-Bit Mask Programmable Read Only Memory
LH2362B
Electrical Characteristics Curves (Ta = 25 "C unless otherwise specified)
•
Access time vs. ambient temperature
Access time vs. supply voltage
1.4
0;-
.
.,..
1.4
0;-
.
Ta=70·C
oS
.,..
.:::
.;.,
1.2
.:::
.;.,
---
Il::
1.0
u
u
.-- ~
;;
.,
]
1.2
V
~
Il::
f--
u
u
1.0
",-
;;
V
.,
]
.,..,'"'"
0.8
.,..,''""
Vcc=4.5V
oS
..,
0.8
..,
...::
...::
0.6
4.0
4.5
5.0
Supply voltage Vee
5.5
0.6
6.0
o
(V)
Supply current during operation vs.
supply voltage
< 100 .----,.-----.-----,------,
-5
50
75
100
25
Ambient temperature Ta ("C)
Supply current during operation vs.
ambient temperature
...:: 100
-5
Vee=5.0V
90~--+---1----~----~
.~
...
rv
80~--1------+----~------;
.S
.g
il
~
ii
1
~
70r-----4------+----~----~
60L---~--~--~~-~
4.0
4.5
5.0
Supply voltage Vee
5.5
6.0
.~
~
60 0
25
~
50
f'.
100
75
("C)
Chip enable time vs. ambient temperature
~
.,..
.~
os
0;
Il::
1.2
./
1.0
L
1.2
~ 1.0
/""
/
/
.~
oE
~ 0.8
il
., 0.8
:g
il
.9U 0.6
4.0
Vee=4.5V
.,
.,
""
1
70
1.4
0;
Il::
~
~
0;-
Ta=70·C
oS
il
Ambient temperature Ta
1.4
0;-
-ii
"-
(V)
Chip enable time vs. supply voltage
...,.
.
"'-f'....
-
~
~
.9-
""
U
4.5
5.0
Supplyvoltage Vee
5.5
(V)
6.0
0.6
o
25
50
Ambient temperature Ta
75
100
("C)
- - - - - - - - - . . - S H A R P - - - - - - ............ - -
593
'LH2367
NMOS 65536-Bit Mask Programmable Read Only Memory
LH2367
•
. NMOS 65536-Bit Mask Prograinmable Read Only
Memory
Description
•
Pin Connections
The LH2367 is a fully static mask programmable
ROM organized as 8,192-word-by-8-bit by using
silicon-gate NMOS process technology.
•
o
Features
1.
2.
3.
4.
5.
6.
7.
8.
8,192-word-by-8-bit organization
Single + 5V power supply
Fully static operation (no clock required)
All inputs and outputs TTL compatible
Three-state output
Access time (MAX.) : 250ns
Programmable chip select (CS h CS 2)
28-pin dua:I-in-line package
Top View
•
Block Diagram
.
Data Output
Address Input
65,536(256X32X8)
Cell Matrix
594
LH2367
NMOS 65536-Bit Mask Programmable Read Only Memory
•
Absolute Maximum Ratings
Parameter
Applied voltage *
Operating temperature
Storage temperature
Symbol
V
Toor
T stu
Ratings
-0.3-+7.0
0-+70
-55-+150
Unit
V
t
t
* The maximum applicable voltage on any pin with respect to GND.
•
Recommended Operating Conditions
Parameter
Supply voltage
Input voltage
•
Symbol
Vcc
V1L
VlH
MIN.
4.75
-0.5
2.0
TYP.
5
MAX.
5.25
0.8
Vcc
Unit
V
V
V
(Vcc=5V±5%, Ta=0-+70t)
DC Characteristics
Parameter
Input low voltage
In put high voltage
Output low voltage
Output high voltage
Input leakage current
Output leakage current
Chip enabled power supply
current
Chip disabled power supply
current
Symbol
V1L
VlH
VOL
VOH
I ILl I
I ILO I
Conditions
MIN.
-0.5
2.0
IoL =2mA
IOH = 200,uA
VIN=OV-Vcc
VOUT=OV-Vcc
(In non· selection mode)
MAX.
0.8
Vcc
0.4
0.01
10
Unit
V
V
V
V
,uA
0.01
10
,uA
50
80
rnA
20
40
rnA
2.4
ICCI
IcC2
TYP.
Note
Note: CE;;;:; 2.0V (Non·active) or CSt or CS. is non-active (CE type chip select)
•
(Vcc=5V±5%, Ta=0-+70t)
AC Characteristics
Parameter
Access time
Chip enable time (from CE)
Chip enable time (from CS)
Output enable time (from OE)
Output enable time (from CS)
Output turn-off time (from CE)
Output turn-off time (from CS)
Output turn-off time (from OE)
Output hold time
Symbol
tAcc
tCE!
tCE2
tOE!
tOE2
tOFl
tOF2
t OF3
toH
MIN.
0
TYP.
MAX.
250
250
250
100
100
100
100
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test conditions of AC characteristics
• Input voltage amplitude
................................. +OAV and +2.8V
• Input rising/falling time ·······················;··················10ns
• Input threshold level··········· .................................. ·1.5V
• Output threshold level··········· ................................. O.8V and 2.0V
• Output load condition ............................................. lTTL + 100pF
595
NMOS.65536-Bit Mask Programmable Read Only Memory
Timing
•
Diagram
(1) Type1 (CS1/CS2 is CE function type)
Ao-AI2
tCEI
CE
cs· 1
tCE2
OE
(High impedance)
*
1 CS is the logical product of CS 1 and CS 2
(2) Type2 (CS1/CS2 is OE function type)
t----tCE----'"'i
cs· 1
(High impedance)
*
596
1 CS is the logical product of CS 1 and CS 2
Valid data
LH2367
LH2367
NMOS .65536-Bit Mask Programmable Read Only Memory
•
Chip Select
OE
X
X
H
L
*1
*2
cr
CS*l
H
X
X
L
X
L
X
H
Mode
Non-select, power down
*2
Output non-select
Read
DouT
CS is high only when the CSl pin and the CSz pin are active at the same time and is low at
all other times. (Non·connection pins are continuously active.)
Chip select input CSl and CSz can be programmed into 2 types depending on the ROM pat·
tern (see timing chart).
Type
(1) CE function type
(2) OE function type
•
Do-D7
High impedance
High impedance
High impedance
Function of CSl pin and CSz pin
Functions at same time as CE pin; when CS = low, non-select power-down mode
Functions at same time as OE pin; when CS = low, output non· select mode
Electrical Characteristics Curves (Vcc=5V, Ta=25"C unless otherwise specified)
Access time vs. supply voltage
Access time vs. ambient temperature
1.4
1.4
".a.
>
.!=
....'"
..!!
Ta=70°C
'"
'-'
'-'
j
.~'"
1.0
I'---
'"
--
"*
'-'
'-'
1.0
j
.~'" 0.8
0.8
V
./"
V
/
~
III
III
III
III
"'"
"..,'"
<
Vcc=4.5V
co
>
1.2
.!=
....
1.2
~
".a
OJ
<
0.6
4.0
4.5
5.5
5.0
Supply voltage
Vee
0.6
6.0
(V)
o
25
50
75
Ambient temperature
Supply current during operation vs.
supply voltage
100
(OC)
Supply current during operation vs.
ambient temperature
<
120
Ta
120
~
'-'
.§
10...
~
100
OIl
.9
.g
i...
90
j
80
'-'
~
~
::i 110
/
/
110
.§
10...
~
~
~
100
~
""
~
8
00
4.0
4.5
5.0
Supply. voltage Vee
5.5
(V)
6.0
25
50
Ambient temperature
75
Ta
100
(OC)
597
NMOS 65536-Bit Mask Programmable
Read Only Memory
Chip enable time vs. supply voltage
.,..=
1.4
.
Ta=70·C
.,:-
.i::
'OJ
.s
1
-
-
0.6
4.0
4.5
5.0
Supply voltage Vee
598
.
5.5
(V)
6.0
1.4
Vee=4.5V
.,:-
/
1.2
e
.;
u
...
.,
:3
~.,c
.....S<
U
0.8
.S<
....
U
.,..=
E.,
p:;
~ 1.0
Chip enable time vs. ambient temperature
.i::
1.2
.Ql
LH2367
1.0
V
~
'/
0.8
0.6
o
25
50
75
Ambient temperature Ta
100
(·C)
CMOS 65536-Bit Mask Programmable Read Only Memory
LH5366A
•
CMOS 65536-Bit Mask Programmable Read
Only Memory
Description
The LH5336A is a mask programmable ROM
organized as 8,192-word-by-8-bit by using CMOS
process technology.
•
•
LH5366A
•
Pin Connections
u
z
Features
1. 8,192-word-by-8-bit organization
2. Single + 5V power supply
3. Low power consumption
4. Edge enabled operation (CEl, CE,)
5. Three-state outputs
6. Access time (MAX.) : 2.5 ps
7. Programmable chip select
8. Selectable byte or digit output
9. 44-piJ;l quad-flat package
Top View
Block Diagram
Address Input
65,536 (256X32X8)
Cell Matrix
~----------~v~-----------J
Data Output
599
CMOS 65536-Bit Mask Programmable Read Only Memory
•
LH5366A
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
Vcc
VIN
VOUT
T oDc
Ts'o
Ratings
-0.3-+7.0
-0.3-+7.0
-0.3-+7.0
0-+60
-55-+150
Unit
V
V
V
'c
·C
* The maximum applicable voltage on any pin with respect to GND.
•
Recommended Operating Conditions
Ratings
4.5-5.5
Parameter
Supply voltage
•
Unit
V
(V cc =5V±10%. Ta=0-+60·C)
DC Characteristics
Parameter
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Chip enabled power
supply current
Chip disabled power
supply current
Note 1:
•
Symbol
VIH
V1L
VOH
VOL
I ILl I
I lLO I
Conditions
MIN.
-0.3
Vcc -1.0
IOH = 100 pA
IOL =1.6mA
VIN=OV-Vcc
In non·selection mode
TYP.
Note
1.0
1.0
Unit
V
V
V
V
pA
pA
5
rnA
1
5
pA
0.4
IcC!
Icc2
MAX.
0.8
Vcc
2.4
C3 • VIN=0.2V or Vcc-0.2V
Average current at cycle time of 4,u s with output open and input set to OV or V cc.
AC Characteristics
Parameter
Address setup time
Chip enable setup time
Chip enable precharge time
Chip turn·off time (CE)
Chip turn·off time (CS)
Cycle time
Symbol
tAs
tCE
tD
tDFI
tDF2
[CYC
MIN.
1
TYP.
MAX.
2.5
1.5
1.5
1.5
4.0
Unit
ps
ps
f.1s
f.1s
f.1s
f.1s
Test conditions of AC Characteristics
• Input voltage amplitude·· ......................................... + 0.8V --- Vcc-1.0V
• Input rising/falling time· ......................................... 20ns
• Input threshold level··· ......................................... ··1.5V
• Output threshold level············································ 0.4 V and 2.4 V
• Output load condition ·········· .... ·······························10pF
--~--.----SHARP-.-.------
600
LH5366A
CMOS 65536-Bit Mask Programmable Read Only Memory
•
Timing Diagram
CE
CS
(High impedance)
•
Electrical Characteristics Curves (Vcc=5V, Ta=25"C unless otherwise specified)
Access time vs. supply voltage
1.4
".
Access time vs. ambient temperature
1.4
Ta=60'C
>
Q)
.~
>
1.2
Q)
~
-:0
Ql
p::
u
u
1.0
.~
~
Ql
p::
~
Q)
.~ 0.8
u
u
~
rn
rn
j
Q)
.~ 0.8
rn
"
..::" 0.6
0.6
4.0
4.5
5.0
5.5
Supply voltage Vee (V)
6.0
75
Ta
100
("C)
2.5
-.S
2.0
~
cQ)
1.5
bCo
~
Co
=
.....'on"
>
..::'"
50
..::
-.S
Ul
25
Average supply current vs. ambient
temperature
2.5
"
o
Ambient temperature
..::
..=
V
V
Q)
Average supply current vs. supply
voltage
.;:;
1.0
/'
Ul
Q)
u
1.2
-:0
j
..::""
Vee =4.5 V
".
..E!
..E!
V
/
I
tl 2.01-----+---+---+----1
V
......
~
~
1.5 ~==:j::==t:::::::i:~=-~
1
1.0
~
1.01-----+---+----+----;
~
>
0.5
4.0
5.0
4.5
Supplyvoltage Vee
5.5
(V)
6.0
~
..:: 0.5 '--_ _..L-_ _- ' -_ _~---'o
25
50
75
100
Ambient temperature Ta
('C)
~'-'-------SHARP'-'-"-----~
601
CMOS 65536-Bit Mask Programmable Read Only Memory
LH5366S
CMOS 65536-Bit Mask Programmable Read
Only Memory
•
Description
The LH5366S is a mask programmable .ROM
organized as 8,192-word-by-8-bit by using CMOS
process technology.
•
•
Pin Connections
Features
1. 8,192-word-by-8-bit organization
2. Single + 3V power supply
3. Low power consumption
4. Edge enabled operation (CEl> CE 2 )
5. Three -state outputs
6. Access time (MAX.) : 6 ps
7. Programmable chip select
8. Selectable byte or digit output
9. 44-pin quad-flat package
•
LH5366S
Top View
Block Diagram
65,536 (256X32X8)
Cell Matrix
Address Input
~----------~vr----------~I.
Data Output
'--'-~--'-'--SHARP -.--.-.~-------
602
LH5366S
CMOS 65536-Bit Mask Programmable Read Only Memory
•
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
Vcc
VIN
VOUT
T oDr
T stg
Ratings
-0.3-+5.0
-0.3-+5.0
-0.3-+5.0
0-+60
-55-+150
Unit
V
V
V
"C
"C
* The maximum appl\cable voltage on any pin with respect to GND.
•
Recommended Operating Conditions
Ratings
2.5-3.5
Parameter
Supply voltage
•
(V cc=3.0V, Ta=O- +60"C)
DC Characteristics
Parameter
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Chip enabled power
supply current
Chip disabled power
supply current
Note 1:
•
Unit
V
Symbol
VIH
VIL
VOH
VOL
I ILl I
I Iw I
Conditions
MIN.
Vcc- 0.6
TYP.
Note
0.5
1.0
1.0
Unit
V
V
V
V
p.A
p.A
1.0
rnA
1
5.0
p.A
0.6
IOH =50 p.A
IOL=50p.A
VIN=OV-Vcc
In non· selection mode
Vcc- 0.5
IcCl
Icc2
MAX.
Cs, VIN=0.2V or Vcc-0.2V
Average current at cycle time of 12,us with output open and input set to OV or Vce.
AC Characteristics
Parameter
Address setup time
Chip enable setup time
Chip enable precharge time
Chip turn-off time (CE)
Chip turn-off time (CS)
Cycle time
(Vcc =2.5-3.5V, Ta=0-+60"C)
Symbol
tAS
MIN.
1
teE
to
tDFl
tDF2
tCYC
TYP.
MAX.
6
6
1.5
1.5
12
Unit
p.s
p.s
p.s
p.s
p.s
p.s
Test conditions of AC characteristics
• Input voltage amplitude···········································+O.5V-Vcc-O.5V
• Input- rising/falling time········· ................................. 20ns
• Input threshold level .. ············· ....................•........... O.3V
• Output threshold level .. ···· ....................................... Vcc- O.3V
• Output load condition .. ············································ 10pF
603
CMOS 65536-Bit Mask Programmable Read Only Memory
•
LH5366S
Timing Diagram
Ao-A12
CE
CS
(High impedance)
•
Electrical Characteristics Curves (Vcc=5V, Ta=25t unless otherwise specified)
Access time vs. ambient temperature
Access time vs. supply voltage
1.4
Ta=60°C
".a.,..
~
co
.i: 1.2
p::
u
u
1.0
.;;
]
.,
"
<"
~
.~
\
0.8
Ul
Ul
0.6
2.0
1.2
.i:
,
.,
"...,
Vee=2.5 V
.aco
\
~.,
1.4
1.0
u
u
.;;
.,
'\
]
0.8
.,
"
<"
0.6
~
2.5
3.0
3.5
Supply voltage Vee (V)
4.0
o
50
100
75
(OC)
Average supply current vs.
ambient temperature
0.8.-----.-----;----,.--.---,
<
<
-5
-5
u
0.6
~
t:
0.4
0.61----+---+---+-----1
u
u
...,"...
.....u
......
B
...-
1
0.2
~.,
-----
~
...-
...
.,"
.l:>
..,.,...
2.5
3.0
0.4
0.2
co
.
<
Supply voltage Vee
.
~
Ul
0
2.0
604
25
Ambient temperature Ta
0.8
..
V
Ul
Ul
Average supply current vs.
supply voltage
<
~
3.5
(V)
4.0
o
25
50
75
Ambient temperature Ta
100
eC)
CMOS 65536-Bit Mask Programmable Read Only Memory
LH5367
CMOS SSS3S-Bit Mask Programmable Read
Only Memory
•
Description
The LH5367 is a mask programmable ROM
organized as 8,192-word-by-8-bit by using sili·
con-gate CMOS process technology.
•
1.
2.
3.
4.
5.
6.
7.
8.
LH5367
•
Pin Connections
00 cE
u u
Features
8,192-word-by-8-bit organization
Single +5V power supply
Low power consumption
Edge enabled operation (CEl. CE 2 )
Three-state outputs
Access time (MAX.) : 450ns
Programmable chip select
44-pin quad-flat package
Top View
•
Block Diagram
Address Input
65,536 (256X32X8)
Cell Matrix
y
Data Output
---~-------SHA.RP------"""""-
605
LH5367
CMOS 65536-8it Mask Programmable Read Only Memory
•
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
Vcc
VIN
VOUT
Topr
TSIJl
Ratings
-0.3-+7.0
-0.3-+7.0
-0.3-+7.0
0-+60
-55-+150
Unit
V
V
V
t
t
* The maximum applicable voltage on any pin with respect to GND.
•
Recommended Operating Conditions
Ratings
4.75-5.25
Parameter
Supply voltage
•
Unit
V
(Vcc=5V±5%, Ta=0-+60t)
DC Characteristics
Parameter
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Chip enabled power
supply current
Chip disabled power
supply current
Symbol
VIH
V1L
VOH
VOL
I ILl I
I lLO I
Conditions
IOH=100pA
IOL =1.6mA
VIN=OV-Vcc
In non-selection mode
. TYP.
MIN.
Vcc -1.0
-0.3
2.4
Icc!
Icc2
Cs , VIN=0.2V or Vcc-0.2V
Note 1: Average current at cycle time of 750ns with output open and input set to OV or Vcc_
•
AC Characteristics
Parameter
Address setup time
Chip enable setup time
Chip enable precharge time
Chip turn-off time (CE)
Chip turn-off time (CS)
Cycle time
Symbol
tAs
teE
tp
tDFl
tDF2
teyC
MIN.
50
TYP.
MAX.
450
300
·300
300
750
Unit
ns
ns
ns
ns
ns
ns
Test conditions of AC characteristics
• Input voltage amplitude .......................................... +0.8V-Vcc -1.0V
• Input rising/falling time · ............................ · ............ 10ns
• Input threshold level" ............................................ 1.5V
• Output threshold level· .......................... · .... ·: .......... ·OAV and 2AV
• Output load condition ........ · ...... · .............. · .............. ·10pF
•
Timing Diagram
Ao-A12
CE
CS
(High impedance)
606
MAX.
Vcc
0.8
Unit
V
Note
V
0.4
1.0
1.0
V
V
pA
pA
14
mA
5.0
pA
1
CMOS 65536-Bit Mask Programmable Read Only Memory
•
LH5367
Electrical Characteristics Curves (Vcc=5V, Ta=25"C unless otherwise specified)
Access time vs. supply voltage
.,
Access time vs. ambient temperature
].
Ta=60'e
.
.
~ 1.2
.,
.::
~~
1.0
Ol
i".......
...........
!
.,
oS
~
,
tl 1.0
!
.,
:a
til
til
.,"'"'
.,
..:""
0.8
..:""
6.0
5.0
&l
e
.g:
75
100
ee)
,V
/
/
./
/
V
./
..:
5
/
u
u
...
&l
t: 4.51----+---+---+----1
e
b
~
.
~
..:
..:
4.0
5.01----+---+---+----1
~
5.0
Supply voltage Vee
4.01---+---+---+-----1
3.S'-_ _..i-_ _..I.-_ _-:!::-_ _:-!
o
6.0
25
50
75
Ambient temperature Ta
(V)
100
('e)
Input voltage vs. ambient temperature
Input voltage vs. supply voltage
2.0
2:-
50
5.5.-----r----r---~-----,
5.0
3.0
25
Average supply current vs.
ambient temperature
6.0
.,..
~
Ambient temperature Ta
Average supply current vs.
supply voltage
~
o
(V)
Supply voltage Vee
~ 4.0
~
~
0.8
0.6
4.0
-.
Vee =4.75 V
.~
1;j 1.2
~
u
u
1.4
2.0,.---'T"""--....- - - , - - - - - ,
2:1.7
d 1.7
d
:>
23
:>
:>
23
:> 1.4
.,
.
.:::
VIH(MIN.)
1.
VIL
~
1.0
j
~
0.8
4.0
4.5
Supply voltage
1.0
u
u
j
---
oE'"
5.0
/
0.6
5.5
o
25
75
50
Ambient temperature
(V)
Vee
V
0.8
''""
"'"
<:"
Q)
0.6
3.5
/
~
Q)
of
''""
"
<:"
1.2
Q)
~
u
u
Vcc=4.0V
v.:
'\.
>
Q)
.~
1.4
Ta=60"e
v.:
Ta
100
("e)
Supply current during operation vs.
ambient temperature
Supply current during operation vs.
supply voltage
4
4
Vcc=5.0 V
tl'= 1.5,us
tl'= 1.5,us
3
3
LH5396A(tcYc ~4.0
o~
~J\.
- ~I
2
11-~
2
-
. . ",,7.5I1- S )
LH5396(tc\C _ _
LJ396(tcY cJ7 .5 ,uS ) -
I...i
...
=
"
o
3.5
4.0
5.0
4.5
Supply voltage
Vee
5.5
j
o
U)
0.4
C
:z: 4.5
.---V--
o
:>
'~"
.±::
~
"§,
...--...--
C
.-1
0.3
0
:>
.,
--
'"
"0 0.2
3.0
>
-"=
..s
:.a
"[ 1.5
'"
0.1
o
4.0
4.5
Supply voltage
5.0
Vee
(V)
5.5
3.5
----
:---
0-=
o-=
3.5
100
("e)
I oL =1.6mA
~
o
75
Ta
Output low voltage vs. supply voltage
6:0
= -lOO,uA
50
Ambient temperature
Output high voltage vs. supply voltage
IOH
25
(V)
4.0
4.5
Supply voltage
5.0
Vee
5.5
(V)
----------SHARP-------611
CMOS 98304-Bit Mas~ Programmable Read Only Memory
LH5396S
•
LH5396S
CMOS 98304-Bit Mask Programmable Read
Only Memory
Description
•
Pin Connections
The LH5396S is a ma~k programmable ROM
organized as 12,288-word-by-8-bit by using silicon-gate CMOS process technology.
•
Features
1.
2.
3.
4.
5.
6.
7.
8.
9.
•
12,288-word-by-8- bit organization
Single + 3V power supply
Low power consumption
Edge enabled operation (CEl. CEz)
Three-state ,outputs
Access time (MAX.) : 15 ps
Programmable chip select
Byte/digit output select
44-pin quad-flat package
Block Diagram
Control
Circuit
Address Input
.-----.-.--SHARP--------,,--612
CMOS 98304-Bit Mask Programmable Read Only Memory
•
lH5396S
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
Vee
VIN
VOUT
Top,
Tst2
Ratings
-0.3-+5.0
-0.3-+5.0
-0.3-+5.0
0-+60
-55-+150
Unit
V
V
V
"C
"C
* The maximum applicable voltage on any pin with respect to GND.
\
•
Recommended Operating Conditions
Parameter
Supply voltage
Input voltage
Operating temperature
•
Symbol
MIN.
2.6
Vee
-0.3
VIL
VIH Vee -0.5
Top,
0
TYP.
3
MAX.
3.4
0.5
Vee
60
Unit
V
V
"C
(V ee =+2.6-+3.4V, Ta=0-+60"C)
DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input leakage current
Output leakage current
Chip enabled power
supply current
Chip disabled power
supply current
Symbol
VIL
VIH
VOL
VOH
I ILl I
I ILO I
Conditions
MIN.
-0.3
Vee- 0.5
IOL=300pA
IOH=30pA
VIN=OV or Vee
In non· selection mode:
VOUT=OV or Vee
TYP.
MAX.
0.5
Vee
0.3
1.0
Unit
V
V
V
V
pA
1.0
pA
2.0
mA
1
2.0
pA
2
Vee- 0.3
0.8
IcC!
Iee2
Note
Note 1: Average current at cycle time of 18 p. s with output open and input set to OV or Vee.
Note 2: In chip selection mode: VIN=O.2V or VIN=Vcc-O.2V
•
AC Characteristics
(Vee=+2.6V-+3.4V,
Ta=0-+60"C)
,
Parameter
Address setup time
Chip enable setup time
Chip enable precharge time
Chip turn·off time (CE)
Chip turn·off time (CS)
Cycle time
Symbol
t AS
teE
tp
tDFl
tDF2
teYe
MIN.
2.0
TYP.
MAX.
Unit
p.s
15
3.0
p.s
p.s
3.0
3.0
10,000
p.s
p.s
p.s
Test conditions of AC characteristics
• Input voltage amplitude .......................................... +0.5V-V cc -0.5V
• Input rising/falling time ·········································20ns
• Input threshold level········································ .. · .. Vcc /2
• Output threshold level··········································· 0.3V and Vcc-0.3V
• Output load condition·· ............................................ Non loading
613
CMOS 98304-Bit Mask Programmable Read Only Memory
LH5396S
(f=IMHz, Ta=25t)
Capacitance
•
Symbol
CIN
COUT
Parameter
Input capacitance
Output capacitance
•
Conditions
V1N=OV
VOUT=OV
MIN.
TYP.
Timing Diagram
)K
tcvc
f-<-tAS
CE
J
I---tCE-
CS
I
tp
~
tDF2
~
,I
f-;;--t D F l -
///h
(High impedance)
•
Valid data
",~
Chip Select
CS O/CSO-CS 3 /CS 3
In selection mode
In non-selection mode
•
CE I
CE 2
L
L
H
H
H
L
L
H
X
X
Do-D7
DOUT
Mode
Read
High impedance
Non-selection
Byte/Digit Output Select
LlU
BID
L
L
H
H
L
H
L
H
614
D7
D7
D7
D7
D7
D6
D6
Ds
D6
D6
D5
D5
D5
D5
D5
Data output pins
D4
D3
D3
D4
D4
D3
D3
D4
D7
D4
D2
D2
D2
D2
D6
Dl
DI
DI
DI
D5
Do
Do
Do
Do
D4
MAX.
15
15
Unit
pF
pF
LH23126
NMOS 131072-Bit Mask Programmable Read Only Memory
LH23126
NMOS 131072-Bit Mask Programmable Read
Only Memory
•
Description
The LH23126 is a fully static mask programmable ROM organized as 16,384-word-by-8-bit by
using NMOS process technology.
•
Pin Connections
o
27 CSI/CSI/NC
Al3
As
A9
All
•
1.
2.
3.
4.
5.
6.
7.
8.
9.
•
Features
16,384-word- by-8-bit organization
Single + 5V power supply
Fully static operation (no clock required)
All inputs and outputs TTL compatible
Three-state outputs
Access time (MAX.) : 250ns
Programmab.1e chip select
Programmable output enable
28- pin dual-in-line package
OE/OE
CSo/CSo
Top View
Block Diagram
Data Output
J.
-.
-e
0
C; ~
Output Buffers
C
~ Q)~
o ._
Utllc.:l
~
.,.''""
"0
"0
Column Address Decoder
..:
c '"
E
..
..::t::
o
=
Uo:l
Address Input
'.,'""
.,''""
'"
"0
:;:
~
~~
o
=
O::o:l
<0
'" .,
:g"
..:
"0
u),.o
~
0
131,072(256X64X 8)
Cell Matrix
~
...... 0::0
615
LH~.3126
NMO.S 131072-Bit Mask Programmable Read Only Memory
Ab~olute Maximum t:latings
•
Parameter
Supply voltage *
Input voltage *
Operating temperature
Storage temperature
*
•
Symbol
Vcc
VIN
Topr
TsUr
Ratings
-0.3-+7.0
-0.3-+7.0
0-+70
-55-+150
Unit
V
V
t
t
The maximum applicable vol,tage on any pin with respect to GND.
Recommended Operating Conditions
Parameter
Supply voltage
Input voltage
•
Symbol
Vcc
V1L
V lH
MIN.
4.5
TYP.
5
MAX.
5.5
O.S
Unit
V
V
V
2.2
(Vcc=5V±1O%, Ta=0-+70t)
DC Characteristics
Parameter
Symbol
Input low voltage
V1L
Input high voltage
VlH
Output low voltage
VOL
Output high voltage
VOH
Input leakage current
I ILl I
Output leakage current
I ILO I
IDuring operation Icc I
Current
consumption
I During standby Icc2
•
AC Characteristics
Parameter
Read cycle time
Access time
Chip enable time
Output enable time
Chip select time
Output select time
Output turn·off time (from CS)
Output turn·off time (from OE)
Output hold time
Conditions
MIN.
-0.3
2.2
IOL=3.2mA
IoH =-400 f'A
VIN=OV-Vcc
VOUT=O-VCC during standby
CSsO.SV,
CS~2.2V
TYP.
MAX.
O.S
Vcc
0.4
2.4
10
10
SO
40
Unit
V
V
V
V
pA
pA
rnA
rnA
(Vcc=5V±10%, Ta=0-+70t)
Symbol
t RC
t ACC
tCE
tOE
tcs
tos
tDFl
tDF2
MIN.
250
toiI
10
TYP.
MAX.
250
250
100
10
10
70
70
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions for measurement of AC characteristics
• Input voltage amplitude ................................... +OA-+2AV
• Input rising/falling time ................................... 20ns
• Input decision level ·········································1.5V
• Output dicision level················,······················· O.BV and 2.0V
• Output load condition··········· <........................... 1TTL + 100pF
---~~~-~--SHARP---------------.-
616
NMOS 131 072-Bit Mask Programmable Read Only Memory
•
LH23126
Timing Diagram
Ao-A!3
tRC
{
~I
tACC
tCE
CS*!
tcs
OE*2
Do-D7
(High impedance)
*1 CS is the reverse polarity of CS
CS/CS is the logical product of CS/CSo and CS/CS/NC
*2 OE is the reverse polarity of OE
•
Chip Select
CS/CS"
H/L
LlH
OE/OE
00-07
H/L
DouT
LlH
High impedance
Mode
Operating
Operating
Standby
----.--~---SHARP--.-.-.--.--
617
CMOS 131072-Bit Mask Programmable
LH53127
•
'Rea~
CMOS l3l072-Bit Mask Programmable Read
Only Memory
Description
The LH53127 is a mask programmable ROM
organized as 16,384-word-by-8-bit by using
poly-crystal silicon-gate CMOS process technology.
•
•
Pin Connections
CS!/CSI
Features
1. 16,384-word-by-8-bit organization
2. Single +5V power supply
3. Low power consumption.
4. Edge enabled operation
5. All inputs and outputs TTL compatible
. 6. Three-state outputs
7. Access time (MAX.) : 250ns
8. Programmable .chip select
9. 28-pin dual-in-fine package
•
LH53127
Only Memory.
I
0
Vee
A;
CSo/CSo
AI3
As
As
As
A.
A.
All
A3
)E
A2
Al
CE
Ao
D7
D6
DI
D.
GND
Top View
Block Diagram
Data Output
"
Control
Signal
Generator
1!32XB
Col'1mn Address Decoder
Address
Input
.,
.,.,...
:g
65,536(256X32XB)
Cell Matrix
..:
,.
Q
e<::
-----------------SHARP
618
.------.-.~----
LH53127
CMOS 131 072-Bit Mask Programmable Read Only Memory
•
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
*
•
Ratings
-0.3-+7.0
-0.3-V ee +0.3
-0.3-Vee +0.3
0-+70
-55-+150
Unit
V
V
V
'C
'C
The maximum applicable voltage on any pin with respect to GND.
Recommended Operating Conditions
Parameter
Supply voltage
Input voltage
•
Symbol
Vee
VIN
VOUT
Topr
T st•
Symbol
Vee
V1L
VIH
MIN.
4.5
TYP.
5
MAX.
5.5
0.8
2.2
Unit
V
V
DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input leakage current
Output leakage current
Current consumption
Current consumption
during standby
(Vee=5V±10%, Ta=0-+70'C)
Symbol
V1L
VIH
VOL
VOH
I ILl I
I lLO I
IcC!
Iee2
Conditions
MIN.
-0.3
2.2
IOL=2.0mA
IoH =-1.0mA
VJN=OV-Vee
TYP.
1.0
1.0
8
1
Unit
V
V
V
V
pA
pA
mA
mA
30
pA
2.4
ISB
MAX.
0.8
Vee
0.4
CE=Vee, V1N=OV or Vee
Note
1
2
3
Notel: During high impedance output, CE=2.2V or OE=2.2V, VOUT=OV-Vee
Note 2: During operation, input amplitude is OV or Vee, teYe=350 ns and output pin is open.
Note 3: During chip non-select, input amplitude is OV or Vee, teye=350 ns, and output pin is open.
•
AC Characteristics
Symbol
Parameter
Cycle time
teye
Access time from CE
teE
Access time from CS/CS
tes
Access time from OE
tOE
Address setup time (from CE)
t ASE
Address setup time (from CS)
tASS
CE precharge time
t pE
CS/CS precharge time
t ps
Data off delay time from CE
toFl
Data off delay time from CS/CS toF2
Data off delay time from OE
toF3
(Vee =5V±10%, Ta=0-+70'C)
MIN.
350
TYP.
MAX.
250
250
100
0
0
100
100
0
0
0
100
100
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
619
.................................................,......................
CMOS 131072-Bit Mask Programmable Read Only'Memory
,
LH53121
~....,---..,
Conditions for measurement of AC characteristics
• Input voltage frequency··················,············:···· OAV -2AV
• Input rise/falI' time .......................................... IOns
• Input decision level ............ · ............................ 1.5V
• Output decisipn level ............................... ; ....... O.8V and 2.0V
• Output load condition ............ · .................. · .... · .. 1 TTL+ 100pF
Address input requires that it should be defined' during an active period.
•
Capacitance
Parameter
Symbol
Input capacitance
Output capacitance
•
CrN
COUT
Conditions
MIN.
Ratings
TYP.
MAX.
10
10
VrN=OV
VOUT=OV
Unit
pF
pF
Timing Diagram
(1)
When the CE input is used as the clock
(The chip is selected by the input of CSo/CSo• CS 1 ICS,.)
t---------tCYC-------~
Ao-At3
OE
Do-D,
(2)
----------------------~~K
When the CS input is used as the clock (9E~VIL(MAX.))
~------tCYC------__I
CSo/CSo
Chip select
CSt/CSt
Ao-At3
OE
--------SHARP.......,~-----....--,
620
CMOS 131072-Bit Mask Programmable. Read Only Memory
•
LH53127
Chip Select
IT
L
cSo/CSQ, CS,/CSISelect
Non-select
H
DE
L
H
X
X
Do-D7
Valid data output
High impedance
Mode
Read
Output non -select
Non-select
Standby
~---'---'---SHARP---'-'-"'-------
621
LH53129
CMOS 131072-Bit Mask Programmable Read Only Memory
LH53129
CMOS 131072-Bit Mask Programmable Read
Only Memory
•
Description
The LH53129 is a mask programmable ROM
organized as 16,384-word-by-8-bitby using silicon-gate CMOS process technology_
•
L
2.
3.
4.
5.
6.
7.
8.
9.
•
.
Pin Connections
uu
I~I~ I~I~
::Je.8ooci).ci)r.i)u
zz.;z;)CQ>uuuuz
Features
16,384-word-by-8-bit organization
Single +4.5V power supply
Low power consumption
Edge enabled operation (CE l. CE z)
Three-state outputs
Access time (MAX.) : 6 ps
Programmable chip select
Byte/digit output select
44-pin quad -flat package
•
Top View
Block Diagram
Chip Enable {
Cbi,
S.I~; {
l~
,
Circuit
Address Input
622
CMOS 131072-Bit Mask Programmable Read Only Memory
•
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
Vee
VIN
VOUT
T oDr
T s '"
Ratings
-0.3-+7.0
-0.3-+7.0
-0.3-+7.0
0-+60
-55-+150
Unit
V
V
V
"C
"C
* The maximum applicable voltage on any pin with respect to GND.
•
Recommended Operating Conditions
Parameter
Supply voltage
Input voltage
Operating temperature
•
Symbol
Vee
VIL
VIH
T oDr
MIN.
4.0
-0.3
Vee -1.0
0
TYP.
4.5
MAX.
5.0
0.8
Vee
60
Unit
V
V
"C
(Vee=4.5V±10%, Ta=0-+60"C)
DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input leakage current
Output leakage current
Chip enabled power
supply current
Chip disabled power
supply current
Note 1:
•
LH53129
Symbol
V IL
VIH
VOL
VOH
I ILl I
I ILO I
Conditions
MIN.
-0.3
Vee -1.0
IOL =1.6mA
IOH=100fLA
VIN=OV-Vee
In non -selection,
VOUT=OV-Vee
MAX.
0.8
Vee
0.4
2.4
3
leCl
lee2
TYP.
CS, VIN=0.2V or Vee-0.2V
Unit
V
V
V
V
1.0
fLA
1.0
fLA
7
rnA
5.0
fLA
Note
1
Average current at cycle time of 7.5,.,s with output open and input set to OV or Vee.
(Vee=4.5V±10%, Ta=0-+60"C)
AC Characteristics
Parameter
Address setup time
Chip enable setup time
Chip enable precharge time
Chip turn-off time (CE)
Chip turn-off time (CS)
Cycle time
Symbol
t AS
teE
to
tDFl
tDF2
tcYe
MIN.
1
TYP.
MAX.
6
1.5
7.5
1.5
1.5
10,000
Unit
fLS
fLS
fLs
fLS
fLs
fLs
Test conditions of AC characteristics
• Input voltage amplitude·· .. ······································· +0.8V-Vcc -1.0V
• Input rising/falling time···· ...................................... 20ns
• Input threshold level··· ........................................... 1.5V
• Output threshold level············································ 0.4 V and 2.4 V
• Output load condition ............................................. 10pF
•
(f=lMHz, Ta=25"C)
Capacitance
Parameter
Input capacitance
Output capacitance
Symbol
CIN
COUT
Conditions
VIN=OV
VOUT=OV
MIN.
TYP.
MAX.
15
15
Unit
pF
pF
-----------SHARP--------623
CMOS 131072-Bit Mask Programmable Read Only Memory'
•
lH53129
Timing Diagram
CE
CS
(High impedance)
•
Chip Select
CS O/CS O-CS 3/CS 3
L
L
In selection mode
In non-selection mode
•
CE 1 .
CE 2
H
L
L
H
H
II
X
X
Do D7
DOUT
Mode
Read
High impedance
Non-selection
Byte/Digit Output Select
LlU
BID
L
L
L
H
H
H
H
624
L
D7
D7
D7
D7
D7
D6
D6
D6
D6
D6
D5
D5
D5
D5
D5
Data output pins
D4
D3
D4
D3
D4
D3
D4
D3
D4
D7
D2
D2
D2
D2
D6
D1
D1
D1
D1
D5
Do
Do
Do
Do
D4
CMOS 131072-Bit Mask Programmable Read Only Memory
•
LH53129
Electrical Characteristics Curves (Ta=25"C unless otherwise specified)
Normalized chip-enable delay time
supply voltage
1.4
1.4
,
.,.,
II
~
u
u
1.0
'"
u
.:t::
0.8
u
<:
.II
t:.
u
.:t::'"
.;;'"
~ r---
1.0
4.0
5.0
4.5
Supply voltage Vee (V)
V
/'
,
0.8
0.6
5.5
o
25
50
Ambient temperature
4
<:
....
3
75
100
Ta
('C)
Supply current during operation vs.
ambient temperature
4
~
G
u
tcye =7.5 /JS
tl'=1.5/Js
g
....
/
0.0
Supply current during operation vs.
supply voltage
~
/
1n
0.6
3.5
Vee =4.0 V
1.2
"
~
'"
.;;
Normalized chip-enable delay time vs . .
ambient temperatur~
Ta=60'C
;; 1.2
?:
VS.
Vee=5.0V
tcye =7.5 /JS
tl'=1.5/Js
3
.~
......
--
"go
/
~
~
...'"
.g
2
.S:
.....
~
...
..,"
~
""
§'
4.0
4.5
5.0
Supply voltage Vee
Output high voltage
VS.
5.5
ient temperature
0.4
6.0
25
(V)
?:
IOL=1.6 rnA
0.3
~
:i
..c:
i
~
1
1.5
=
o
0
3.5
4.0
4.5
Supply voltage Vee
5.0
(V)
5.5
0
3.5
4.0
4.5
Supply voltage Vee
5.0
5.5
(V)
.-----.-------SHARP·~.-.----~-.-.
625
LH53129A
CMOS 131072-Bit Mask Programmable Read Only Memory
LH53129A
•
CMOS 131072-Bit Mask Progiammable
Read Only Memory
.
Description
•
Pin Connections
. The LH53129A is a mask programmable ROM
lorganized as 16,384-word-by-8-bit by using silicon-gate CMOS process technology.
•
Features
1.
2.
3.
4.
5.
6.
7.
8.
9.
16,384-word-by-8-bit organization
Single +5V power supply
Low power consumption
Edge enabled operation (CEl> CE z)
Three-state outputs
Access time (MAX.) : 2.5 ps
Programmable chip select
Byte/digit output select
44-pin quad-flat package
•
u
u
z
Z
Block Diagram
Data Output
~
Chip Enable { 18
8JVCC
5 GND
Chip Select { 24
LlU
9 B/D
30
L/U.B/D
Control
Circuit
Address Input
626
Top View
CMOS 131 072-Bit Mask Programmable Read Only Memory
•
LH53129A
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
Vcc
VIN
VOUT
Topr
T st "
Ratings
-0.3-+7.0
-0.3-+7.0
-0.3-+7.0
-5-+55
-55-+150
Unit
V
V
V
·C
·C
* The maximum applicable voltage on any pin with respect to GND.
•
Recommended Operating Conditions
Parameter
Supply voltage
In put voltage
Operating temperature
•
Symbol
Vcc
VIL
V IH
T oDr
MIN.
4.5
-0.3
Vcc -1.0
-5
TYP.
5
MAX.
5.5
0.8
Vcc
55
Symbol
V IL
VIH
Input leakage current
VOL
VOH
I ILl I
Output leakage current
I lLO I
Chip enabled power
supply current
Chip disabled power
supply current
V
·C
(V cc =4.5V+5V±10%, Ta=-5-+55·C)
DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Unit
V
Conditions
MIN.
-0.3
Vcc -1.0
IOL =1.6mA
IOH= 100 flA
VIN=OV-Vcc
In non-selection mode,
VOUT=OV-Vcc
MAX.
0.8
Vcc
0.4
2.4
7
IccI
Icc2
TYP.
CS, VIN=0.2V or Vcc-O.2V
Unit
V
V
V
V
1.0
f'A
1.0
flA
14
rnA
5.0
flA
Note
1
Note 1: Average current at cycle time of 4.0 p's with output open and input set to OV or Vee.
•
AC Characteristics(Vcc=5V±10%, Ta=-'-5-+55·C)
Parameter
Address setup time
Chip enable setup time
Chip enable precharge time
Chip turn-off time (CE)
Chip turn-off time (CS)
Cycle time
Symbol
tAS
tCE
tD
tDFI
tDF2
tcYC
MIN.
1
TYP.
MAX.
Unit
f'S
2.5
f'S
f'S
1.5
1.5
10,000
f's
f's
fls
1.5
Test conditions of AC characteristics
• Input voltage amplitude ........................................... +O.8V - Vcc-1.0V
• Input rising/falling time··· ...... ·· .... · .... ··· ............ ······· 20ns
• Input threshold level ............................................. ·1.5V
• Output threshold level ............................................ OAV and 2AV
• Output load condition'" .......................................... lOpF
---------------$HARP-------627
CMOS 131072-Bit Mask Programmable' Read Only Memory
•
LH53129A
- (f ko lMHz, Ta=25"C)
Capacitance
Parameter
Input capacitance
Output capacitance
•
Symbol
CIN
COUT
Conditions
V[N=OV
Va T=OV
MIN.
TYP.
Timing Diagram
tCYC
I--tAS
J
~r---t
CE
r
J---tCE-----I
CS
I---tOF1-
,,',/,
/.
(Highim pedance) .
•
Valid data
Chip Select
CS O/CS O -CS 3 /CS 3
In selection mode
L
L
In non-selection mode
H
H
X
•
CE 2
H
CE 1
L
L
H
X
Do 0 7
DOUT
Mode
Read
High impedance
Non-selection
Byte/Digit Output Select
LlU
BID
L
L
L
H
H
H
H
628
L
07
07
07
07
07
06
06
06
06
06
.
Os
Os
Os
Os
Os
Data output pins
03
04
03
04
04
03
04
03
07
04
O2
O2
O2
O2
01
01
01
01
06
Os
Do
Do
Do
Do
04
'%"
. MAX.
15
15
Unit
pF
pF
CMOS 131072-Bit Mask Programmable Read Only Memory
•
LH53129A
Electrical Characteristics Curves (Ta=25"C unless otherwise specified)
Normalized chip-enable delay time vs.
supply voltage
1.4
:>
1.4
Ta=60'C
1.2
"-
0
.n
II
u
u
:> 1.0
1.2
~
'"
0.8
0.6
4.0
4.5
1n
N
.
!:
II
------r-
5.0
.;:"'
.;:"'
G
./
go 3.0
.~
0.6
o
25
75
50
100
Ta
('C)
Supply current during operation vs.
ambient temperature
6.0 r-------,-----.----,
Vee=5.5V
G
teyc=4.0.us
..:i
tp=1.5.us
4.51===~===*==_t_----1
./
.,
0.8
-<
-5
..:i 4.5
-:0...
~
Ambient temperature
t eye =4.0.us
tl' =1.5.us
.§
~
(V)
Supply current during operation vs.
supply voltage
-5
1.0
~
"-
6.0
5.5
Supply voltage Vee
<" 6.0
Vee=4.5 V
U
u
<
.;:'"
Normalized chip-enable delay time vs.
ambient temperature
~
~
.§
-:0
~
""o
.~
30r---+----r---+--~
.
.g
.g
~ 1.5
~ 1.51----+----r---+--~
1i
1i
...
...
..e;.
..e;.
~
r/l
0
IS:
4.0
4.5
5.0
Supply voltage Vee
5.5
6.0
~
I
(V)
Ambient temperature Ta
Output high voltage vs. supply voltage
10H=0.4 mA
4.5
..,........ V"
........ ~
('C)
Output .low voltage vs. supply voltage
6.0
~'"
.,
0~--2~5~-~5~0---7=5~-~100
0.4
V
IOL=1.6 rnA
C
..J
0.3
0
:>
..,.
:'if
,;:: 3.0
.
,;:: 0.2
..
o
-
0
:;
..c
..s
~ 1.5
~ 0.1
:;
~
:;
o
,.,..
0
o
4.0
O~_~~_~~
4.5
5.0
Supply voltage Vee
5.5
(V)
6.0
4.0
4.5
_ _~____~
5.0
Supply voltage . Vec
5.5
6.0
(V)
.-.----------SHARP----.---629
NMOS 262144-Bit Mask Programmable Read Only Memory
LH23257
NMOS 262144-Bit Mask Programmable Read
·Only Memory
•
Description
The LH23257 is a fully static mask programmable ROM organized as 32,768-word-by-8-bit by
using silicon-gate CMOS process technology.
•
•
Pin Connections
0
A7
A6
A5
A.
Features
1. 32,768-word-by-8-bit organization
2. Single + 5V power supply
3. Fully static operation (No clock required)
4. All input and output TTL compatible
5. Three-state outputs.
6. Access time (MAX.) : 250ns
7. ~rogrammable chip select
8. Programmable output enable
9. 28-pin dual-in-line package
•
LH23257
A3
A2
AI
AI3
AM
A9
All
OE OE
cs
CS
Do
01
0;
02
Top View
Block Diagram
Data Output
"
Output Buffers
Address Input
262,144 Cell Matrix
630
Vee
A"
LH23257
NMOS 262144-BitMask Programmable Read Only Memory
•
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
*
•
Vcc
VIN
VOUT
Topr
Tst~
Unit
V
V
V
'C
'C
Recommended Operating Conditions
Input voltage
Symbol
Vcc
V IL
VlH
MIN.
4.5
-0.3
2.2
TYP.
5
MAX.
5.5
O.S
Vcc
Unit
V
V
V
(Vcc=5V±10%, Ta=0-+70·C)
DC Characteristics
Parameter
Symbol
Input low voltage
VIL
Input high voltage
VlH
Output low voltage
VOL
Output high voltage
VOH
Input leakage current
I ILl I
Output leakage current
I ILO I
Current
during operation
ICCl
consumption
I during standby Icc2
I
•
Ratings
-0.3-+7.0
-0.3-+7.0
-0.3-+7.0
0-+70
-55-+150
The maximum applicable voltage on any pin with respect to GND.
Parametet:
Supply voltage
•
Symbol
Conditions
MIN.
-0.3
2.2
IOL=3.2mA
IoH = -400,u A
VlN =0-5.5V
VouT =0-5.5V during standby
IouT=OmA
CS~O.SV, CS;;;;2.2V
TYP.
MAX.
O.S
Vcc
0.4
2.4
10
10
SO
45
Unit
V
V
V
V
,uA
p.A
rnA
rnA
AC Characteristics (Vcc=5V±1O%, Ta=0-+70'C)
Parameter
Read cycle time
Access time
Chip enable time
Output enable time
Chip select time
Output select time
Output turn-off time (from CS)
Output turn-off time (from OE)
Output hold time
Symbol
t RC
t ACC
tCE
tOE
tcs
tos
tDF!
tDF2
tOH
MIN.
250
TYP.
MAX.
250
250
100
10
10
70
70
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions for measurement of AC characteristics
• Input voltage frequency .................................... + 0.4 - + 2.4 V
• Input rise/fall time .......................................... 20ns
• Input decision level ....................................... "1.5V
• Output decision level ....................................... O.BV, 2.0V
• Output load .................................................. ·1 TTL+ 100pF
631
NMOS 262144-Bit Mask Programmable Rea~ Only Memory
•
(f=1MHz, Ta=25'C)
Pin Capacitance
Parameter
Input capacitance
Output capacitance
•
LH232.57
Symbol
CIN
COUT
MIN.
Conditions
V1N=OV
VOUT=OV
TYP.
8
12
Timing Diagram
tRC
~
~t\
I - - tOH
tACC
tCE
\
tDFl
tcs
"(-
tOE-
~ VII
(High impedance)
•
~\\
ro- tDF2
Valid data
Chip Select
CS/CS
LlH
H/L
632
OE/OE
LlH
H/L
Output
High impedance
DOUT
Current consumption
Standby
Operating
MAX.
-I) ) )
Unit
pF
pF
NMOS 262144-Bit Mask Programmable Read Only Memory
•
LH23257
Electrical Characteristics Curves (Vcc=5V, Ta=25"C unless otherwise specified)
Access time vs. supply voltage
.,
1.4
.::'"
1.2
Access time vs. ambient temperature
.,.a
...
~
..
.::'"
Ql
P:::
1.0
.~'" 0.8
''""
'"
"
..::"
V
0.6
4.0
v---
---
u
u
~
5.5
4.5
5.0
Supply voltage Vee CV)
0.6
6.0
tcYc=250ns
~ 60
.§
60
.--
40
1;j
V
....
"go
.ff
5.0
Supply voltage Vee
5.5
25
100
75
("C)
2.0
E::
:: 1.7
1.2
:>
VlH
;;'"
1.0
~1.4
.
.±::
'B
o
~
'"c
"
50
Input voltage vs. supply voltage
1.4
"
.0
r--
Ambient temperature Ta
~
"'
B
~ t:.........
6.0
.::'"
Ql
40
CV)
Output enable time vs. supply voltage
1;j
100
COC)
teYe=250ns
Vee=5.5V
1
.g
...
75
50
25
Ambient temperature Ta
Supply current during operation vs.
u
4.5
~
ambient temperature
.Ii;
.,.a
o
..:: 80
~
c
.~
go
~
~
0.8
'"
""'"
..::"
80
u
1.0
"
.~
supply voltage
~
1.2
'"
~
Supply current during operation vs.
~
Vee=4.5V
]
1;j
u
u
~
1.4
VIL
ILl
0.8
i-;;
0
0.6
4.0
4.5
5.0
5.5
Supply voltage Vee CV)
6.0
0.8
4.0
4.5
5.0
Supply voltage Vee
5.5
6.0
CV)
- . . - . - - - - - - S H A R P - - - - - . - . - - .......
633
CMOS
2~2144-Bit
Mask Programmable Read Only.Memory
LH5325·6
.•
LH53256
CMOS 262144-Bit Mask Programmable Read
Only Memory
•
Description
Pin Connections
The LH53256 is a mask programmable ROM
organized as 32,768-word-by-8-bit by using silicon-gate CMOS process technology.
•
Features
1.
2.
3.
4.
5.
6.
7.
8.
9.
32,768-word-by-8-bit organization
Single + 5V power supply
Low power consumption_
Edge enable operation (CEl> CE 2)
Three-state outputs
Access time (MAX.) : 800ns
Programmable chip select
Bytel digit output select
44-pin quad-flat package
•
Top View
Block Diagram
262,144 (512X64X8)_
Cell Matrix
Address Input
~----------~y~----------~
Data Output
----------SHARP---------634
LH53256
CMOS 262144-Bit Mask Programmable Read Only Memory
•
Absolute Maximum Ratings
Parameter
Pin voltage *
Operating temperature
Storage temperature
Symbol
VIN
,Topr
T stg
Ratings
-0.3-+7.0
0-+60
-55-+150
Unit
V
"C
"C
* The maximum application voltage on any pin with respect to GND.
•
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input leakage current
Output leakage current
Chip enabled power
supply current
Chip disabled power
supply current
Input capacitance
Output capacitance
Note
Note
Note
Note
•
(Vcc=5.0V±10%, Ta=0-+60"C)
DC Characteristics
Symbol
V;L
VIH
VOL
VOH
I ILl I
I Iw I
Conditions
MIN.
-0.3
Vcc -O.4
Note
1.0
1.0
Unit
V
V
V
V
pA
pA
Icc!
10
mA
2
Icc2
50
pA
3
CIN
COUT
5
10
pF
pF
4
4
IOL=2.0mA
IoH =-1.0mA
VIN=OV-Vcc
TYP.
MAX.
0.6
Vcc
0.4
2.4
1
1: CE I =Vcc-O.2V or CE2=O.2V or OE=Vcc-O.2V, VOUT=OV-Vcc
2: ~t amplitude: O.4V-Vcc-O.4V, tcYc=900ns, output open
3: CE1=VCC-O.2V, CE2=O.2V
4: Ta=25t:, f= IMHz
AC Characteristics (Vcc=5.0V± 10%, Ta=0-+60"C)
Parameter
Chip enable setup time
Output enable time
Address setup time
Address hold time
Chip turn·off time (CE)
Chip turn-off time (OE)
Chip enable precharge time
Cycle ,time
Symbol
tCE
tOE
t AS
tAH
tDFl
tDF2
to
tcYC
MIN.
TYP.
MAX.
800
100
30
100
100
100
100
900
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Test conditions of AC characteristics
•
Input voltage amplitude .........................•................ +O.4V-V cc -O.4V
•
Input rising/falling time ......................................... 20ns
•
Input threshold level ··············································1.5V
•
Output threshold level ..•......................................... 0.4 V and 2.4 V
•
Output load condition ............................................. 10pF
635
............,...............--...-:...-.........................
CMOS 262144-Bit Mask Programmable Read Only Memory
.............
~
• . Timing Diagram
A o -A 14
CSo/CSo-CS 3 /CS 3
L/U, BID
Input transition
(High impedance)
1-------tCYC----~~
•
Chip Select
Do-D 7
DOUT
CE 2
OE
CS2/CSO -CS 3/CS 3
Mode
L
H
0
1
In selection mode
Read
In non-seleCtion mode
Non-selection
L
H
H
L
L
H
CE 1
•
X
X
High impedance
X
Standby
X
Byte/Digit Output Select
L/U
BID
L
L
H
H
L
H
L
H
636
07
06
05
D7
D7
D7
07
D6
D6
06
D6
05
D5
D5
05
Data output pins
03
04
03
D4
D4
D4
04
D3
D3
07
D2
01
Do
D2
O2
D2
06
D1
D1
. D1
05
Do
Do
Do
04
LH53256
LH53256
CMOS 262144-Bit Mask Programmable Read Only Memory
•
Electrical Characteristics Curves (Ta=25t unless otherwise specified)
Normalized chip-enable delay time vs.
supply voltage
Normalized chip-enable delay time vs.
ambient temperature
1.4
1.4
Ta=60'C
~
>
<=
V cc=4.5V
....
1.2
"-
u;
II
tl
e 1.0
1.2
~
'"
<.)
U
'tn
C'O
~
~
~ 0.8
0.6
4.0
.
!:
II
--
'"
<.)
~
'"
~
5.5
6.0
6
---
4
~.
~
.,/
6
4
2
2
Vcc=5.5 V
tcyc=900 DS
tp =100 ns
o
4.0
4.5
5.5
5.0
Supply voltage
V cc
o
6.0
(V)
IOH=-1.0mA
IOL=4mA
Ta=75'C
4.5
0
>
.",..,.. I-""
.--' ~
25
50
Ambient temperature
75
Ta
100
("C)
Input voltage vs. supply voltage
Output voltage vs. supply voltage
~VOH
e
:=
2.4 r--------,------r---,
Ta=O'C(VlH)
Ta=60'C(VILl
1.8
>
.;
::l
>
0
..'"
25
50
75
100
Ambient temperature Ta' ('C)
8
tcyc =900 DS
tl'=100DS
>
/
Supply current during operation vs.
ambient temperature
8
0:
o
(V)
Supply current during operation vs.
supply voltage
e
~
/
0.8
0.6
5.0
4.5
Supply voltage Vee
6.0
1.0
3.0
'~"
1.2
;!:O
;!:O
0
0
'"
:;'" 1.5
i
0.6
.....c
.fr
=
0
o
4.0
VOL
5.5
5.0
4.5
Supply voltage Vee (V)
6.0
0
4.0
4.5
5.0
Supply voltage Vce
5.5
6.0
(V)
-----·-~.-----SHARP-.----------
637
- LH53257
CMOS 262144-Bit Mask Programmable Read Only Memory
LH53257
•
CMOS 262144-Bit Mask Programmable Read·
Only Memory
Description
The LH53257 is a fully static mask programmable ROM organized as 32,768-word-by-8-bit by
using polycrystal silicon-gate CMOS process technology.
•
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Features
32,768-word-by-8-bit organization
Single +5V power supply
Low power consumption
Fully static operation (No clock required)
All input and output TTL compatible
Three-state outputs
Access time (MAX.) : 250ns
Programmable chip select
Programmable output enable
28-pin dual-in-line package
•
•
Pin Connections
0
A7
A6
A,
A,
A3
A2
Al
An
DI
Top View
Data Output
638
CS CS
Dz
r - - -________~A~_ _~_ _~--~
Input
OE OE
Do
Block Diagram
Address
Vee
AI,
AI3
As
Ao
All
Cell Matrix
(32,76SXS)
LH53257
CMOS 262144-Bit Mask Programmable Read Only Memory
•
Absolute MaXimum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
Vee
VIN
VOUT
Toor
T st•
Ratings
-0.3-+7.0
-0.3-+7.0
-0.3":'+7.0
0-+70
-55-+150
Unit
V
V
V
"C
"C
*The maximum applicable voltage on any pin with respect to GND.
•
Recommended Operating Conditions
Parameter
Supply voltage
Input voltage
•
Symbol
Vee
VIL
VlH
MIN.
4.5
-0.3
2.2
TYP.
5
MAX.
5.5
0.8
Vee
Unit
V
V
V
(V ee =5V±10%, Ta=0-+70"C)
DC Characteristics
Parameter
Input low v~ltage
Input high voltage
Output low voltage
Output high voltage
Input leakage current
Output leakage current
Current
consumption
'.
IDuring operation
I During standby
Symbol
VIL
VlH
VOL
VOH
I ILl I
I lLO I
Icc
ISB
Conditions
MIN.
-0.3
2.2
10L =1.6mA
IOH=-200 pA
V IN =0-5.5V
CS=0.8V, CS=2.2V,
VoUT =0-5.5V
10uT=OmA
CS";:0.2V, CS~Vee-0.2V
TYP.
MAX.
0.8
Vee
0.4
10
Unit
V
V
V
V
pA
10
pA
30
30
rnA
pA
2.4
AC Characteristics (Vcc =5V±10%, Ta=0-+70"C)
Parameter
Read cycle time
Access time
Chip enable time
Output enable time
Chip select time
Output select time
Output turn·off time (from CS)
Output turn·off time (from OE)
Output hold time
Symbol
t RC
tAce
tCE
toE
tcs
tos
tDFl
tDF2
tOH
MIN.
250
TYP.
MAX.
250
250
100
10
10
100
100
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions for measurement of AC characteristics
• Input voltage frequency width····························· ······0.8 - 2.2V
• Input rise/fall time ................................................. 20ms
• Input decision level··· ............................................• ·1.5V
• Output decision level····················· .......................... 0.8V and 2.2V
• Output load .. ·························································1 TTL+ 100pF
---------SHARP-----.-.-.--639
CMOS 262144-:Bit Mask
•
Programmabl~
LH53257
Read Only Memory
(f=IMHz,Ta=25'C)
Pin Capacitance
Parameter
Input capacitance
Output capacitance
•
Symbol
CIN
CIN
Conditions
VIN-OV
VOUT=OV
MIN.
rip.
10
10
Timfng Diagram
Ao-Au
=x1-:_~-_-_-_-_~-_-_~t_RC~~~~~~~~~~
. .-_. . . I-.01----tACC----''"I
I-o,""-----tcE-----""I
,e
tcs
OE
(High impedance)
•
Chip Select
CS/CS
L/H
H/L
640
OE/OE
X'
LlH
H/L
Output
High impedance
Output
Power consumption
During standby
During operation
MAX.
~-.,;..-+.;;:.:...--_
Unit
pF
pF
LH53257
CMOS 262144-8it Mask Programmable Read Only Memorx
•
Electrical Characteristics Curves (Vcc=5V, Ta=25"C unless otherwise specified)·
Access time vs. supply voltage
Access time vs. ambient temperature
1.4
1.4
~
.
.,..
~
...,.
~
.~
1.2
"-
'"
].,
p::
u
u
1.0
.;;
.,
'Srn
.,rn
...:""
.~
...
~
0.8
1.2
;;
p::
-----
u
u
-
1.0
~
.;;
.,
.!
.,rnrn
~
~
O.I!
...:""
0.6
4.0
4.5
5.0
5.5
Supply voltage Vee CV)
0.6
6.0
o
25
50
75
Ambient temperature Ta
100
C·C)
Supply current during operation vs.
ambient temperature
Supply current during operation vs.
supply voltage
12
12.-----------.-----~----~
tnc=250ns
9
,/
V
tcye=250ns
Vee=5.5V
/
u
..::;
Vee=4.5V
~
9~~~,-----+-----~----~
/
.S...
.,.
go
./'
-T'----I--_..J
61----+-----+-----/----1
.rr.
.g
.
~
31----+-----+-----/----1
8
~
4.5
5.0
5.5
6.0
~
{fl
°0~--~25~-~5~0----~75~--~100
Supply voltage Vee CV)
Ambient temperature Ta
~
.,.
~
2.0
1.4
.~
...
;; 1.2
e
2'"
.,
...,
2:
;;'"
r-...
1.0
·s.,
~
C·C)
Input voltage vs. supply voltage
Output enable time vs.
supply voltage
0.8
""'"
::
:>
~
.,
~
'=
~
.;::
.
0
J
1.1
~
0
0.6
4.0
4.5
5.0
5.5
Supply voltage Vee (V)
6.0
0.8'--____-'-____--'-____--'____- - J
4.0
4.5
5.0
5.5
6.0
Supply voltage Vee
CV)
~.-~-----SHARP-.------------
641
. CMOS 524288-Bit Mask Prograf!1mable Read Only Memory
LH53512
CMOS 524288-Bit Mask Progrartunable Read
Only Memory
•
•
Description
The LH53512 is a mask programmable ROM
organized as 65,536-word-by-B-bit by using silicon-gate CMOS process technology.
•
1.
2.
3.
4.
5.
6.
7.
B.
Pin Connections
Features
65,536-word-by-B-bit organization
Single +5V power supply
Low power consumption
Edge enabled operation
Three-state outputs
Access time (MAX.) : 3.0 ps
Programmable chip select
24-pin small-outline package
Top View
•
Block Diagram
10
Address Input / Data Output
9
8
7
6
5
Low
Address I--r- X
Decoder
Latch
'4'
-
65,536 X8
Cell Matrix
3
8
8
~
~.
High
Address
Latch
Y
.1
l
Chip Select
{~.~
T
Chip
Select
PLA
~
16
Low Address
Read Signal
Decoder
Y Selecter
Output
Buffer
Output Latch /
Output Mode Select
1
~
4
High Address
Read Signal
~
Output
Control
I
U
Byte/Digit
S elect
I
1
GND
18 Vee
Output
Enable
,------...-. ....... . - - - - - S H A R P . - . - . - - - - - - 642
CMOS 524288-Bit Mask Programmable Read Only Memory
•
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
Vcc
VIN
VOUT
Topr
Tst2
Ratings
-0.3-+7.0
-0.3-+7.0
-0.3-+7.0
-5-+55
-55-+150
Unit
V
V
V
"C
"C
* The maximum applicable voltage on any pin with respect to GND.
•
(Ta=25"C)
Recommended Operating Conditions
Parameter
Supply voltage
Input voltage
•
LH53512
Symbol
MIN.
4.0
Vcc
-0.3
V1L
Vcc -1.0
VIH
TYP.
5.0
MAX.
6.0
0.8
Vcc
Unit
V
V
V
(V ee =5.0V±20%, Ta=-5-+55"C)
DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input leakage current
Output leakage current
Chip enable power supply
current
Chip disabled power supply
current
Symbol
V1L
VIH
VOL
VOH
I ILl I
I ILO I
ICCI
Icc2
Conditions
IOL=0.5mA
IOH =-0.5mA
MIN.
-0.3
Vec -1.0
TYP.
MAX.
0.8
Vcc
0.4
1.0
1.0
1,500
500
Unit
V
V
V
V
pA
pA
pA
pA
3.0
pA
Vcc -0.8
ICC3
Note
1
1
·2
a
.
Note 1: Input leakage current (except A/Do_7): VIN=OV-Vcc
110 leakage current (A/Do-7): VIN/OUT=OV-Vcc
CSI=0.2V, CSI=Vcc-0.2V or OE=0.2V, OE=Vcc-0.2V
Note 2: tcyc=4.4 ,.,s, Vcc=5.5V, output open, VIN= +0.4-+5.1 V
Note 3: tCyc= 15 ,.,S, Vcc=5.5V, output open, VIN=+0.4-+5.1 V
Note 4: CS1=0.2V, CS1=Vcc-0.2V
643
CMOS 524288-Bit Mask·Programmable Read Only Memory
•
LH53512
AC Characteristics (V cc =5:0V±20%, Ta=-5-+55'C)
Parameter
Low.er ·address setup timeLower address hold time
Higher address setup time
Higher address hold time
CS hold time (non· selection)
CS setup time
BID setup time
BID hold time
LAS pulse width
HAS pulse width
HAS access time
OE access time
AID open setup time
OE to data out delay
OE to pulse width
CSI data off delay
OE to data Qff delay
OE LAS delay
BID OE setup time
BID OE hold time
Cycle time (8-bit output mode)
Cycle time (4-bit output mode)
Symbol
tSLA
tHLA
tSHA
tHHA
tHC
tsc
tSB
tHB
tWL
tWH
tHAS
tOE
tFO
taD
two
tcF
tOF
taL
tSBO
tHBO
tcYCl
t CYC2
MIN.
0
200
0
200
0
200
0
200
500
500
TYP.
MAX.
3,000
1,000
0
0
0
0
0
200
200
200
4,400
580
200
200
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test conditions of AC characteristics
• Input voltage amplitude ........................................... +OAV -Vcc-OAV
• Input risingifalling time························ ................... 20ns
• Input threshold level .. ·· .. ············ .. ····· .. · .......... ··· ...... 1.5V
• Output threshold level .. ······ .. ···· .. ····· .. ·· .... ·· .... ···· .... ··OAV and Vee -O.8V
• Output load condition .......................... ·· ...... · ...... · .... l00pF
•
(f=IMHz, Ta=25'C)
Capacitance
Parameter
Input capacitance
Output capacitance
644
Symbol
CIN
COUT
Conditions
VIN=OV
VOUT=OV
MIN.
TYP.
MAX.
10
10
Unit
pF
pF
CMOS 524288-Bit Mask Programmable Read Only Memory
•
Timing
LH53512
Diagram
a-bit output mode
4-bit output mode
* DOUT=Do::-3 at B/D=O
repetition.
D4 - 7 at B/D= 1
Arbitrary order of output and number of output
645
,LH531 000
CMOS 1048576-Bit Mask Programmable Read Only Memory
LH531000
CMOS I048576-Bit Mask Programmable
Read Only Memory
•
Description
/ The LH531000 is a mask programmable ROM
organized as 131,072-wOl:d-by-B-bit by using
silicon-gate CMOS process technology.
Features
131,072-word-by-B-bit organization
Single+5V power supply
Low power consumption
Fully static operation
Automatic power down mode
All input and output TTL compatible
Three-state outputs
Access time (MAX.) : 250ns (normal mode)
BOns (nibble mode)
9. Programmable chip select
CS type 20pin = CS/~
OE type 20pin = OE/OE
10. 2B-pin dual-in-line package
•
Pin Connections
•
1.
2.
3.
4.
5.
6.
7.
B.
•
20
CS/CS/CE/CE
Top View
Block Diagram
Data Output
~~----~~~--------~
D7 Ds Ds D4 Da D2 DI Do'
CS/CS/OE/OE
20
Address
Input
1,048,576(131,072 X 8)
Cell Matrix
646
................ -........... -...... - . - . -...... - . -....................
CMOS 1244160-Bit Mask Programmable Read
Only Memory for "kanji" Characters Generation
LH53012 Series
I NEW I
CMOS 12441S0-Bit Mask
Programmable Read Only Memory for "kanji" Characters Generation
LH53012 Series
•
Description
LH530101 - 4 are mask ROMs for "kanji"
characters generation which memorize a total of
6834 characters of non-"kanji" and "kanji". It is
able to input the first and second bytes of JIS ~kan·
ji" code and a character is composed of 24 X 24
dots prescribed in lIS C 6226-1983
•
Pin Connections
.---------------------------------~
Vee
0
NC
NC
Y7
Y6
Y5
y,
•
Y3
Features
1. 4 chips in a set
Non-"kanji"(524 characters) + First standard
"kanji"(2965 characters) : LH530101 +
LH530102 Second standard "kanji"(3388 char·
acters) : LH530103 + LH530104
2. Row scanning method
3. 103,680-word-by-12-bit organization
4. Single + 5V power supply
5. Low power consumption
6. Fully static operation (no clock required)
7. Three-state outputs
8. Access time (MAX.) : 250ns
9. Involved the error correcting. circuit
10. 40-pin dual-in-line packge
y,
D5
GND
CSI
OE
NC
NC
D11
D",
D9
DB
D7
Top View
647
CMQS,124416-:-Bit Mask Programmable Read
OnJy Memory for "kanji" Characters Generation
.-........,....,...
•
...........
LH53012 Series
-.-.-.-..-.-.-.-
Block Diagram
30
Chip
Select {
Input
Chip
Select
Buffer
Output
Enable
Buffer
Enable
,...---'..........., Ao
Row
Decoder
Address
Buffers
Character
Address
Input
Sense
Amp.
Column
Decoder
Memory
Arrey
ECC
Output .
Buffers
Output
-----..--.-~.---SHARP,.- ........... -~.-.~--
648
Ordering Procedure of Mask ROM
.....
~~~.-~~.-~
.-.-~.-~~~~~
Mask ROM Ordering Procedure
The ordering procedure for mask ROMs is de·
scribed below along the mask ROM development
flow chart.
ROM data from the user should be submitted in
the form of an EPROM or on paper tape. At the
same time, the fo\1owing information should be provided.
(1) Type of media on which ROM data is provided
(2) Specified items (chip select, markings)
(3) Corporate name, person in charge, signature
(4) Date of order
When submitting the ROM, two sets of ROM data
media and ROM print-outs must be submitted to
make sure that correct data can be read from the
ROM.
After the ROM data is received, we use a CAD
system to create a magnetic tape to prepare the
ROM mask, and create a new EPROM or paper tape
and their print-outs for comparison to make sure
that the CAD-processed ROM data is correct.
After the user verifies that there are no problems with the results, we start preparing the mask
and the TS (technical sample) and submit these to
the user for evaluation.
If there are no problems with the TS, the user
submits the "Mask ROM TS Certification" to us.
We can begin mass production immediately or
shortly thereafter according to instructions given
by the user.
Mask ROM Development Flow Chart
Client
SHARP
EPROM or
paper tape
Mask ROM delivery
/+----+-------------1
Mass production start
---------.-.....-SHARP-.-.-,--------
649
CMOS 65536-Bit Electrically Programmable ROM
LH5764J
•
LH5764J
CMOS 65536-Bit Electrically Programmable
ROM
Description
•
Pin Connections
The LH5764] is a CMOS UV ERASABLE and
electrically programmable read only memory organized as 8,192-word-by-8-bit. It is especially well
suited for application where rapid turn-around
and/or bit pattern experimentation, and low-power
consumption and fast access time are important.
•
Features
1. 8,192-word-by-8- bit organization
2. Access Time (MAX.)
LH5764]-20 : 200ns
LH5764]-25 : 250ns
LH5764]-30 : 300ns
LH5764]-45 : 450ns
3. Single +5V power supply
4. Programming power supply: + 12.5V ± 40%
Programming pulse width : 1 ms/byte
5. Power consumption (MAX.) : 150m W (operation)
0.55mW (standby)
•
6.
7.
8.
9.
Fully static operation
Input and output TTL compatible
Pin compatible with i2764
28-pin dual-in-line package (Ceramic)
Block Diagram
65,536
Row Cell Array
Address Input
'" ...
ec .'". '"0
=
'Ii '"0
_'"0"
0'"0 '"
u
r---.
'" ~
l:3 1.0
:;
.!'"
OJ
OJ
'"
.~
co
Qi
1.2
~
~
0.8
l:3 1.0
:;
~
'"
/
.!'"
~ 0.8
0.6
4.0
4.5
5.0
5.5
Supply voltage
Vee
0.6
6.0
o
(V)
100
("e)
40
...:
5
G 30
N
<.)
<.)
~
30
>-<
c
..'::s"
C
20
is:
::s
OJ
co
75
Ta
...:
5
..'"
50
Average supply current vs.
ambient temperature
40
b"
25
Ambient temperature
Average supply current vs.
supply voltage
::s
/
...:""
...:""
..'"
1/
v
V
10
...:'"
~
>
----
~
~
4.5
r--
Q.
§OJ
g:,
.
co
,
10
...:'"
>
o
4.0
20
b"
5.0
5.5
SupplyvoItage Vee
o
6.0
(V)
----
25
50
Ambient temperature
...
100
75
Ta
("e)
Input voltage vs. ambient temperature
Input voltage vs. sup·ply voltage
2.0 ..-----..-----,----,---~
2.0
~
.... 1.5
;;
;;'"
V IH
-
i5
:>
VIL
'" 1.0
~
!
g
.:::
~
'[ 0.51---+----+----+----1
'[ 0.5
..s
o
4.0
.a
4.5
5.0
Supply voltage
5.5
Vee
(V)
6.0
o
25
50
Ambient temperature
75
Ta
100
("C)
657
CMOS 1024-Bit Sta~'ic Random Access Memory
LH51 01 iLH51 01 L3
LH510'1/LH5101L3
CMOS I024-Bit Static Random Access Memory
•
.•
Description
Pin Connections
The LH5101/LH5101L3 are fully static RAMs
organized as 256-word-by-4-bitby using silicon-gate CMOS process technology.
o
•
Features
1.
2.
3.
4.
5.
6.
256-word-by-4-bit organization
Single +5V power supply
Fully static operation
All inputs and outputs TTL compatible
Three-state outputs
Access time (MAX.)
LH5101 : 800ns, LH5101L3 : 650ns
7. Data can be held on +2V supply voltage
8. Low power supply current at standby mode
9. 22-pin dual-in-line package
•
Top View
Block Diagram
Chip Enable Input { 1
191)---L~
Data Output
Read/Write Input
Do<,
r.,.. { :
Output Disable 18
'--.r---I
Address Input
.-..-...-.....~----SHARP
658
----------------
. CMOS 1024-Bit Static Random Access Memory
•
LH51 01 ILH51 01 L3
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
Vcc
VIN
VOUT
Topr
T=
Ratings
-0.3-+7.0
-0.3-V cc +0.3
-0.3-V cc +0.3
0-+70
-55-+150
*The maximum applicable voltage on any pin with respect to GND.
•
Unit
V
V
V
"C
"C
(V cc =5V±5%, Ta=0-+70"C)
DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input current'
Output leakage current
Symbol
V1l
VIH
Val
VOH
I ILl I
I lLO I
Current consumption 1
IcC!
Current consumption 2
Iccz
Chip disabled current
consumption
Iccl
•
Conditions
MIN.
0.3
2.2
Iol =2.0mA
IOH =-1.0mA
0;&V1N;&V CC
0;&V1N;&V CC, CEI=2.2V
Output open, VIN=Vcc
CE 1 ;&0.65V
Output open, VIN=2.2V
CE I :S:0.65V
I LH5101
CE z ;&0.2V
I LH5101L3
TYP.
MAX.
0.65
Vcc
0.4
1.0
1.0
Unit
V
V
V
V
pA
pA
9
22
mA
13
27
mA
100
200
pA
2.4
AC Characteristics
(1)
(V cc=5V± 10%, Ta=O- +70"C)
Read cycle
Parameter
Cycle time
Access time
Chip enable time 1
Chip enable time 2
Output enable time
Chip turn-off time
Data hold time from address
Data hold time from CE I
Symbol
tRc
t ACC
teal
te02
too
tOF
tOHI
tOHZ
MIN.
800
LH5101
TYP.
MAX.
800
800
850
350
200
0
0
0
Cycle time
Access time
Chip enable time 1
Chip enable time 2
Data setup time
Data hold time
Pulse width
Recovery time
Input enable time
0
0
0
LH5101L3
TYP.
MAX.
650
600
700
350
150
Unit
ns
ns
ns
ns
ns
ns
ns
ns
(V cc=5V± 10%, Ta=O- +70"C)
(2) Write cycle
Parameter
MIN.
650
Symbol
twc
tAW
tcwI
tew2
tow
tOH
twp
tWR
tos
MIN.
800
200
600
600
400
100
400
50
200
LH5101
TYP.
MAX.
MIN.
650
150
550
550
400
100
400
50
150
LH5101L3
MAX.
TYP.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
659
. CMOS 1024.:Bif Static Random Access Memory·
LH51 01 ILH5101 L3 .
Test conditions of AC characteristics
• Input voltage amplitude .. ·· ....................................... + 0.65 - + 2.2V
• Input ri~ing/falling time········ .................................. 20ns
• Timing reference level··· .. ········································ L5V
• Output load condition .. ·················;··························1 TTL+ 100pF
•
(f=1MHz, Ta=25t)
Capacitance'
Parameter
Input capacitance
Output capacitance
•
Symbol
CIN
C~UT
Conditions
VIN=OV
VOUT=OV
MIN.
TYP.
6
15
**
Symbol
Conditions
VDR
VeE2~0.2V
lee DR
teDR
tR
VeE2~0.2V,
Unit
pF
pF
(Ta=0-+70t)
Low-Voltage Data Hold Characteristics
Parameter
Supply voltage for data
hold
Supply current for data hold
Chip turn:off time
Operation recovery time **
MAX.
10
20
MIN.
TYP.
MAX.
2.0
V
20
VDR=2.0V
Unit
pA
ns
ns
0
tRe
In data hold mode, all input/output pins are put below VD •.
tRC : Read cycle time
---------- ........ ~--~-SHARP -------...~---~
660
I
LH5101/LH5101 L3
CMOS 1024-Bit Static Random Access Memory
•
Timing
Diagram
(1 ) Read cycle
t-'--------tRC--------I
t---+--tC02:----I
OD
(in I/O common mode)
For'data input/output separation, OD is made low. In read cycle, R/~ is made high.
(2) Write cycle
~-----~tWC:--------~
_ _ _1-_--. J----·tCWl--.......j
eE,
I--+---t-tCW2:-------;~
Oh-DI.
f----tDW'-----!~
___-+~,~---:tw~--~~~~~----
R/W
In 110 common mode, OD is high during the write period. For data input/output separation, OD may be either high or low.
(3) Low-voltage data hold
Supply voltage
i.~--
~~~~~~:~----
'b
________________ __
V,,-------VIH::£:t:'~
O.2V---
--
OV----
~
-
------------
---
---
. - - - - - - . - . - - S H A R P .-......-,--_.-.....-._---
661
CMOS 1024-Bit Static Random Access Memory
LH5101S
•
LH5101S
CMOS l024-Bit Static Random Access Memory
•
Description
Pin Connections
The LH5101S is a fully static RAM organized as
256-word-by-4-bit by using silicon-gate CMOS
process technology.
•
Features
1. 256-word-by-4-bit organization
2.
3.
4.
5.
6.
7.
8.
Single + 3V power supply
Fully static operation
All inputs and outputs TTL compatible
Three-state outputs
Access time (MAX.) : 3.0 ps
Data can be held on +2V supply voltage
Low power supply current at standby mode
10 pA (MAX.)
9. 22- pin dual-in-line package
•
Top View
_Block Diagram
Chip' Enable Input {
Read/Write Input
19!>t==L~X~--'
Data Output
0
Do<, I"., { ':
Output Disable 18
'-v--'
Address Input
662
CMOS 1024-Bit Static Random Access Memory
•
LH5101S
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
Vee
VIN
VOUT
Topr
T.t ..
Ratings
-0.3-+7.0
-0.3-V ee +0.3
-0.3-Vee +0.3
-10-+60
-55-+150
Unit
V
V
V
'C
'C
*The maximum applicable voltage on any pin with respect to GND.
•
(V ee =2.6-3.4V, Ta=-10-+60'C)
DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input current
Output leakage current
Symbol
VIL
VIH
VOL
VOH
I III I
I lLO I
Current consumption 1
IcC!
Current consumption 2
lee2
Chip disabled current
consumption
leeL
•
Conditions,
MIN.
-0.3
Vee- 0.6
IOL =500 pA
IOH=-30pA
TYP.
MAX.
0.6
Vee
0.3
Unit
V
V
V
V
1.0
1.0
pA
5
11
rnA
8
13
rnA
10
pA
Vee- 0.6
OS::VIN~Vee
OS::VINS::V ee, CE I =Vee- 0.6
Output open, VIH = Vee,
CE I S::0.6V
Output open, VIN=2.2V
CEI~0.6V
O~VIN~Vee, CE2~0.2V
p.A
AC Characteristics
(1)
Read cycle
Parameter
Cycle time
Access time
Chip enable time
Address enable time
Output enable time
Chip turn-off time
Data hold time from address
Data hold time from CE I
Adress enable delay time
(2)
Write cycle
Parameter
Cycle time
Access time
Chip enable time 1
Chip enable time 2
Data setup time
Data hold time
Pulse width
Recove'ry time
Input enable time
Address enable delay time
(V ee =2.6-3.4V, Ta=-10-+60'C)
Symbol
t Re
t Aee
teo
t AEO
too
tOF
tOHl
toH2
toH3
tAEI
tAE2
MIN.
3.5
TYP.
MAX.
3.0
3.0
2.9
1.3
750
0
0
Unit
ps
ps
ps
ps
ps
ns
ns
0
ns
0.1
0.5
ps
p.s
(V ee =2.6-3.4V, Ta=-10-+60'C)
Symbol
twe
tAW
tewl
tAEW
tow
tDH
twp
tWR
tDs
tAE3
tAE4
MIN.
3.5
750
2.2
2.1
1.5
370
1.5
180
750
0.1
0.5
TYP.
MAX.
Unit
p.s
ns
p.s
p.s
p.s
ns
ps
ns
ns
p.s
-'-'-~--'--SHARP'-~~~----'--
663
CMOS 1024-Bit Static Random Access Memory
LH5101S
Test conditions of AC characteristics
• Input voltage amplitude· .. ··· .. ····················· .. ········ .... + 0.65 - + 2.2V
• Input risinglfaliing time .......................................... 10ns
• Timing reference level .......................................... "1.5V
• Output load condition ............................................ ·1 TTL+ 100pF
•
(fc=lMHz, Ta=25"C)
Capacitance
Symbol
Parameter
Input capacitance
Output capacitance
•
CIN
COUT
Conditions
MIN.
VOUT=OV
Symbol
V OR
IccoR
tCOR
tR
Conditions
VCE2 S:O.2V
VCE2 S:O.2V, VOR-2.0V
•
Timing
(1)
MIN.
2.0
t RC
tRe: Read cycle time
Diagram
Read cycle
~--------------tRC--~--------~
AE
OD
(in
I/O
common mode)
For data input/ output separation, OD is made low_
664
TYP.
MAX.
5
0
**In data hold mode, all input/output pins are put below VDR_
MAX.
10
20
Unit
pF
pF
(Ta= -10- +60·C)
Low-Voltage Data Hold Characteristics
Parameter
Supply voltage for data hold
Supply current for data hold
Chip turn-off time
Operation recovery time **
TYP.
6
15
VIN=OV
Unit
V
pA
ns
ns
LH5101S
CMOS 1024-Bit Static Random Access Memory
(2)
Write cycle
twe
Ao-A7
tew!
eE!
AE
tAt..W
tDH
DI!-DI.
tDW
tw
R/W
In 110 common mode, OD is made high during the write period. For data input/output separation, OD may be either high or low.
(3)
Low-voltage data hold
Supply voltage ,Vee
2.60V
VD.
AE
V 1H
O.2V
OV
-------}=:.=~'~~":~------
--------
'"b
~~~------------------~
--- ------ -
---
---
-----------------------------
Address enable (AE) may be high normally, but in this case, the address input level must strictly be below VIL and above VIH in.
clusive of noise spikes. Use of AE in such a timing relationship that the AE input is included inside the address input as shown
in the timing chart is fairly recommended.
665
LH5101W
CMOS 1024-Bit Static Random Access Memory
LH5101W
•
CMOS I024-Bit Static Random Access
Memory
•
Description
Pin Connections
The LH5101W is a fully static RAM organized
as 256-word-by-4-bit by using silicon-gate CMOS
process technology.
o
•
Features
1.
2.
3.
4.
5.
6.
7.
8.
256-word-by-4-bit organization
Single ,+ 5\1 power supply
Fully static operation
All inputs and outputs TTL compatible
Three-.state outputs
Access time (MAX.) : 800ns
Data can be held on +2V supply voltage
Low power supply current at standby mode
100 pA (MAX.)
9. 22-pin dual-in-line package
•
Top View
Block Diagram
Chip Enable Input{ 19iH-_ _L";Y->--"---'
Data Output
Output Disable
8
----~--.--,------SHARP ....-..-.~.-.------
666
CMOS 1024-Bit Static Random Access Memory
•
LH5101W
Absolute Maximum Ratings
Parameter
Supply voltage·
Input voltage
Output voltage·
Operating temperature
Storage temperature
•
Symbol
Vcc
VIN
VOUT
T=
T","-
Ratings
-0.3-+7.0
-0.3-Vcc +0.3
-0.3-Vcc +0.3
0-+70
-55-+150
Unit
V
V
V
'C
'C
*The maximum applicable voltage on any pin with respect to GND.
•
(V cc =5V±10%, Ta=0-+70'C)
DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input current
Output leakage current
Symbol
V1L
VIH
VOL
VOH
I ILl I
Current consumption 1
IcC!
Current consumption 2
Icc2
Chip disabled current
consumption
ICCL
•
IILO I
Conditions
MIN.
0.3
2.2
IOL=0.2mA
IoH =-1.0mA
0:5:V1N :5:Vcc
0:5:V1N :5:VCC , CE I -2.2V
Output open, VIN=Vcc,
CE 1;;;;0.65V
Output open, VIN=2.2V,
CE I :5:0.65V
TYP.
MAX.
0.65
Vcc
0.4
1.0
1.0
Unit
V
V
V
V
p.A
p.A
9
22
mA
13
27
mA
100
p.A
2.4
-
0;;;;V1N;;;;VCC, CE 2 ;;;;0.2V
AC Characteristics
(1)
(V cc =5V±10%, Ta=0-+70'C)
Read cycle
Parameter
Cycle time
Access time
Chip enable tillie 1
Chip enable time 2
Output enable time
Chip turn-off time
Data hold time from address
Data hold time from CE I
Symbol
t RC
tAcc
teOI
tC02
toD
tDF
toHl
tOH2
(2) Write cycle
Parameter
Cycle time
Access time
Chip enable time 1
Chip enable time 2
Data setup time
Data hold time
Pulse width
Recovery time
Input enable time
MIN.
800
TYP.
MAX.
800
800
850
350
200
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
B
(Vcc=5V±10%, Ta=0-+70'C)
Symbol
twc
tAW
tcwi
tCW2
tow
tOH
twp
tWR
tos
MIN.
800
200
600
600
400
100
400
50
200
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test conditions of AC characteristics
• Input voltage amplitude .......................... ·· .............. · +O.65-+2.2V
• Input risingifalling time ................................ · ........ ·10ns
• Timing reference level ............................................ 1.5V
• Output load condition .................. · .......................... 1TTL + 100pF
667
CMOS t024-Bit Static Random Access Memory
LH5101W
............... - ............ - ......_ _ _ _ _ _ _ _r.._..:_ _ _,.._.
•
(f=IMH~,
Capacitance
Parameter
Input capacitance
Output capacitance
•
Symbol
CIN
COUT
Conditions
VIN=OV
VOUT=OV
MIN.
TYP.
3.5
9
Symbol
VDR
IccDR
tCDR
til
Conditions
VCE2~0.2V
VCE2~O.2V,
**In data hold mode, all input/output pins are put below
me : Read cycle time
668
MIN.
2.0
12
TYP.
MAX.
5
VDR=2.0V
0
t RC
VOR.
6
Unit
pF
pF
(Ta=0-+70'C)
Low-Voltage Data Hold Characteristics
Parameter
Supply voltage for data hold
Supply current for data hold
Chip turn-off time
Operation recovery time **
MAX.
Ta=25'C)
Unit
V
pA
ns
ns
CMOS 1024-Bit Static Random Access Memory
•
Timing
(1)
LH5101W
Diagram
Read cycle
i-------tRC----------l
tCOI
t---+---tcoz-----I
too
00
(in I/O common mode)
tOF
i---tACC
DOl-DO.
For data input/output separation, OD is mode low, In read cycle, R/W is mode high.
(2) Write cycle
I-------twc----------.~
___+-__... ro<-----tcwl----t
CE z
I-+----tcwz---------;~
00
(in I/O common mode)
tOH
011-01.
I----tow----<*;;-.-
R/W
---~--,~-----twp
r-----~----
In 110 common mode, OD is made high during the write period. For data input/output separation, OD may be either high or low.
(3)
Low-voltage data hold
Supply voltage Vee
4.5V
VD.
CEz
VIH
O.2V
OV
=== __ ~~r~:·~~"-·:~~;;-u-
~~~-----------------~
--- -
-------------- ---
.-.-----------SHARP .-.-.-----------
669
CMOS 2048-Bit Static Random Access Memory
LH51 02/LH.51 02-8-
LH5102/LH5102-8
CMOS 2048-Bit Static Random Access Memory
•
•
Description
Pin Connections
The LH5102lLH5102-B are fully static RAMs
organized as 512-word-by-4-bit by using metalgate CMOS process technology.
Vee
AI
R/W
•
Features
1. 512-word- by-4-bit organization
Single + 5V power supply
Low power consumption
Data can be held on + 2V supply voltage
All inputs and outputs TTL compatible
Three-state outputs
Fully static operation
Pin compatible with SHARP LH5101 or Intel
5101 (except Pin 19)
9. Access time (MAX.)
LH5102-B: BOOns, LH5102 : 1,200ns
10. 22-pin dual-in-line package
2.
3.
4.
5.
6.
7.
B.
•
Top View
Block Diagram
Chip Select Input Qll:J+------,
Read/Write Input
u
Data Input { ;
Output Disable
'!'8=~;:::=~~:2~=j2f~~~
f(:
5i}-(:6)-o{7)----'
~
Address Input.
670
CMOS 2048-Bit Static Random Access Memory
•
LH51 02/LH51 02-8
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
Vcc
VIN
VOUT
T oDr
Tst2
Ratings
-0.3-+7.0
-0.3-V cc +0.3
-0.3-V cc +0.3
0-+70
-55-+150
Unit
V
V
V
t
t
*The maximum applicable voltage on any pin with respect to GND.
•
Parameter
Supply voltage
Input voltage
•
Symbol
Vcc
VIL
VIH
MIN.
4.75
-0.3
2.2
TYP.
5
MAX.
5.25
0.65
Vcc
Unit
V
V
V
(V cc =5V±10%, Ta=0-+70t)
DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input current
Output leakage current
Current consumption
Chip disable current
consumption
•
(Ta=0-+70t)
Recommended Operating Conditions
Symbol
VIL
VIH
VOL
VOH
I ILl I
I ILO I
IcC!
Icc2
IccL
MIN.
-0.3
2.2
Conditions
IOL=2.0mA
IoH --1.0mA
VIN=O or Vcc
CS~0.2V, VOUT=OV or Vcc
Output open, VIN - VCC
Output open, VIN = 2.2V
TYP.
MAX.
0.65
Vcc
0.4
7.0
1.0
22
27
Unit
V
V
V
V
pA
pA
rnA
rnA
200
pA
2.4
3
13
CS~0.2V
(Vcc=5V±5%, Ta=0-+70t)
AC Characteristics
Parameter
Unit
Read cycle
Cycle time
Access time
Chip enable time
Output enable time
Chip turn·off time
Data hold time
t RC
t ACC
1,200
900
teo
taD
tDF
toH
0
0
twc
tAW
tDW
tDH
twp
tWR
t DS
900
150
-200
70
650
100
150
800
800
400
200
0
0
1,200
1,200
500
250
ns
ns
ns
ns
ns
ns
Write cycle
Cycle time
Access time
Data setup time
Data hold time
Pulse width
Recovery time
Input enable time
1,200
300
0
100
400
200
250
ns
ns
ns
ns
ns
ns
ns
Test conditions of AC characteristics
• Input vqltage amplitude··········· ................................ + 0.65 - + 2.2V
• Input rising/falling time .......................................... 20ns
• Timing reference level······ ...................................... 1.5V
• Output load condition ········································ .. · .. 1TTL+ 100pF
671
CMOS 2048-Bit Static Random Access Memory
•
LH51021LH5102-8
(Ta=O-+70'C)
Low-Voltage Data Hold Characteristics
Parameter
Supply voltage for data hold
Supply current for data hold
Chip turn·off time
Operation recovery time **
Symbol
VDR
IccDR
tCDR
tR
Condition-s
Vcs~0.2V
MIN.
2.0
TYP.
Vcs";::0.2V. VDR=2.0V
MAX.
Unit
V
40
pA
ns
ns
0
t RC
**In data hold mode, all input/output pins are put below VD•. tRe: Read cycle time. -
•
(f=IMHz, Ta=25'C)
Capacitance
Parameter
Input capacitance
Output capacitance
672
Symbol
CIN
COUT
Conditions
VIN=OV
VOUT=OV
MIN.
TYP.
6
15
MAX.
10
20
Unit
pF
pF
CMOS 2048-Bit Static Random Access Memory
•
Timing
(1)
LH5102/LH51'02-8
Diagram
Read cycle
tRe
'V
'V
JI\
Ao- As
JI\
..... tOHr---
cs
~
teo
I
tOD-
OD ( Note 1)
(in I/O common mode)
I
J
----- -----tAee
----'V
_________ JI\
-----
I--tDFValid data
----
Notel: For data input/output separation, OD is made low.
(2) Write cycle
twe
Ao-As
cs
W
V--
JI\
.JIL-
,
l/
~
OD ( Note 2)
(in I/O common mode)
)
1"-V
tDH
i--=+
I---tos-
------ ----'V
------ ____ .11\tow
,V- ---~~- ----
Valid data
~
twp
'\
R/W
U
1\
I------tAW_
i--twR-
Note 2 : tn I/O common mode, OD is made high during the write period. For data input! output separation, OD may be either high
or low.
(3) Low-voltage data hold
Supply voltage
.
CS
---
'r
,~~n-----J ~~~~~ ~"~---1
.
Vo.--------teoR
~~~:::::::~~=====~======;
OV---
-
-
-
---
---'----.-..---SHARP . - . - . - - - - - - - -
673
LH51 02/LH51 02-8
CMOS 2048-81t Static Random Access Memory
•
Electrical Characteristics Curves (Vcc=5V, Ta=25"C unless otherwise specified)
Access time vs. supply voltage
1.4
"...,.
1.2
].,
Il::
u
u
1.0
.j
.,
.~
'.,'""
"
<:"
1.4
Ta=700e
..=
.::
Access time vs. ambient temperature
0.8
Vee=4.75 V
\
"'"
~
u
j
1.0
....--'
.,
~
V
V
V
/
.~
'" 0.8
~
<:"
0.6
4.0
0.6
5.5
4.5
5.0
Supply voltage Vee (V)
6.0
Current consumption vs. supply voltage
o
75
25
50
Ambient temperature Ta
100
coe)
Current consumption vs. ambient
temperature
5.0
5.0
<:
6
~
-
4.0
tl
13.0
~
§
i"
2.0
....-- ~
-
~
-
4.0
~
3.0
u
u
~§
"
~
"l3
l3"
1.0
4.0
2.0
1.0
4.5
5.0
5.5
Supply voltage Vee (V)
6.0
Input voltage vs. supply voltage
o
50
100
75
re)
Input voltage vs. ambient temperature
2.5
2:
2:
:: 2.0
2.0r---+---
>
., 1.5 i-----+----+---+----I
~
.:!::
1
~
0.5!";:-_ _:'-:-_ _:::-::-_ _-="="_ _-:'
4.0
4.5
5.0
5.5
6.0
Supply voltage Vee
(V)
-
V1L(MAX.)
:;
1.0 ......."----+----+---+----1
-
V1H(MIN.)
>.," 1.5
>
J
25
r--
Ambient temperature Ta
2 . 5 . - - - . , - - - . . . , - - -....- - ,
>;:;
r--
u
u
..I
--- ---
.§
11.0
0.5
o
25
50
100
75
Ambient temperature Ta
ee)
-~-~----SHARP--------~-~-~
674
CMOS 2048-Bit Static Random Access Memory
LH5102W
LH5102W
CMOS 2048-Bit Static Random· Access
Memory
•
Description
The LH5102W is a fully static RAM organized
as 512-word-by-4-bit by using metal-gate CMOS
process technology.
•
Pin Connections
o
Vee
A.
R!W
As
•
Features
512-word-by-4-bit organization
Single + 5V power supply
Low power consumption
Data can be held on + 2V supply voltage
All inputs and outputs TTL compatible
Three-state outputs
Fully static operation
Pin compatible with SHARP LH5101 or Intel
5101 (except Pin-19)
9. Access time (MAX.) : 1,200ns
10. 22-pin dual-in-line.package
1.
2.
3.
4.
5.
6.
7.
8.
•
Top View
Block Diagram
:J-----iRow
Row
!r-_-.....Buffers
Decoders
l--_-;of.Address.t==~Address
Chip Select Input 1 7 ' ) - + - - - - - - - ,
00----1 Input
l}----..... Data
.3}----..;o-j Control
Output Disable 181}----C>O-------L..J
~--------------------------~5~6
7~------~
'-----r---"
Address Input
--------------SHARP----------675
CMOS 2048-Bit Static Random Access Memory
•
lH51{)2W
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
-
Ratings
-0..3-+7.0.
-D.3- Vee+ D.3
-0.3 Vec +0.3
-20.-+70
-55 +150.
Symbol
Vee
VIN
,VOUT
Toor
T st•
*The maximum applicable voltage on any pin with respect to GND.
•
Unit
V
V
V
.'C
'C
Recommended Operating Conditions
Parameter
Supply voltage
Input voltage
•
Symbol
MIN.
4.0.
-0..3
2.2
Vee
V1L
V IH
TYP.
5
MAX.
5.5
0..65
Vee
Unit
V
V
V
(V ee =5V±10%, Ta=-2D-+70'C)
D'C Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input current
Output leakage current
Current consumption
Chip disabled current
consumption
•
Symbol
V1L
ViH
VOL
VOH
I ILl I
I Iw I
IcCl
Iec2
MIN.
0..3
2.2
IOL -2.DmA
IoH =-1.DmA
V1N-DV or Vee
CS~0.2V, VOUT-OV or Vee
Output open, V IN - Vee
Output open, VIN=2.2V
rCeL
CS;a;0.2V
I Symbol I
t Re
t Aee
teo
taD
tDF
tOH
twe
tAW
tDW
tDH
twp
tWR
t DS
MIN.
I
TYP.
I MAX. I
Unit
1.2
1.2
50.0.
250.
ps
j.lS
ps
ns
ns
ns
1.2
0.
0.
1.2
30.0.
6
10.0.
40.0.
20.0.
250
j.lS
ns
ns
ns
ns
ns
ns
Test conditions of AC characteristics
• Input voltage aIp.plitude···················· .. ····················· +0.65-+2.2V
• Input rising/falling time' ......................................... 20ns
• Timing reference lE\vel ............................................ 1.5V
• Output load condition ......................'....................... 1TTL + 100pF
676
TYP.
MAX.
0..65
7.0.
' 1.0
22
27
Unit
V
V
V
V
,pA
pA
rnA
rnA
20.0.
pA
Vee
0..4
2.4
(Vee=5V± 10%, Ta=-2D-+7D'C)
AC Characteristics
Parameter
Read cycle
Cycle time
Access time
Chip enable time
Output enable time
Chip turn·off time
Data hold time
Write cycle
Cycle time
Access time
Data setup time
Data hold time
Pulse width
Recovery time
Input enable time
Conditions
3
13
LH5102W
CMOS 2048-Bit Static Random Access Memory
•
. (Ta=-20-+70'C)
Low-Voltage Data Hold Characteristics
Parameter
Supply voltage for data hold
Supply current for data hold
Chip turn-off time
Operation recovery time **
Symbol
VOR
IccoR
tCOR
tR
Conditions
Vcs";;0.2V
Vcs~0.2V, VOR=2.0V
MIN.
2.0
TYP.
MAX.
Unit
V
40
pA
ns
ns
0
tRc
** In data hold mode, all input/output pins are put below VDR. tRC : Read cycle time
•
(f=IMHz, Ta=25'C)
Capacitance
Parameter
Input capacitance
Output capacitance
Symbol
CIN
COUT
Conditions
VIN=OV
VOUT=OV
MIN.
TYP.
6
15
MAX.
10
20
Unit
pF
pF
B
677
LH51.02W
CMOS 2048-Bit Static Random Access Memory
•
Timing
Diagram
(1). Read cycle
Ao-As
cs
J---1I----tco---..-i
OD (Note 1)
(in I/O common mode)
DO,-DO.
Valid d!lta
Notel: For data input/output separation, OD is made low.
(2) Write cycle
J---------twc------------~~
cs
OD (Note 2)
(in I/O common mode)
tDH
_ _~f_--!::::::j""----twp------lr_-.......,r_-R/W
Note 2 : In 110 common mode, OD is made high during the write period. For data input/output separation, OD may
be either high or low.
(3) Low-voltage data hold
_1m~:-_h:"_'~~=-l
8"",1, ........¥l'l'--·
VOR--------
cs
678
V[H~~~-----------------~~
O.2V---
--
ov--- -
-
-
-
-
-
--
--
---
-
-
---
---
LH5102W
CMOS 2048-Bit Static Random Access Memory
•
Electrical Characteristics Curves (Vcc=5V, Ta=25°C unless otherwise specified)
Access time vs. supply voltage
1.4
Ta=70'C
\
~
0.8
..,
0.6
4.0
...,
1.4
Vee=4.5V
/
>
:J..,'"
«:
.,
..El
.,
.~
Access time vs. ambient temperature
4.5
.~
1.2
.,
~
~
'""
5.0
5.5
Supply voltage Vee (V)
u
u
1.0
."!
,../
.,
,,/'
V
V
.~ 0.8
.,..,''""
..,
«:
6.0
0.6
-20
0
20
40
60
80
Ambient temperature Ta
Current consumption vs. supply voltage
100
('C)
Current consumption vs. ambient
temperature
5.0
5.0
«:
~
8 4.0
G
.....
.§
~ 3.0
"'"
~
i...
2.0
~
u
-
........ ~
-
~
.§
>==
:5
VIH(MIN.)
:5
:>
>
.,
:.::
-
1.5
VIL(MAX.)
0
>
:; 1.0
....."""
0.5 ~----:-"=--~7--~-=----:!
4.0
4.5
5.0
5.5
6.0
Supply voltage Vee
(V)
0.5
-20
0204060
Ambient temperature Ta
80
100
('C)
------------$HARP---------679
NMOS· 4096-Bit Static Random Access Memory
LH2114L-20
•
LH2114L-20
NMOS 4096-Bit Static Random
Access Memory
•
Description
Pin Connections
The LH2114L-20 is a fully static RAM organized as 1024-word-by-4-bit by using silicon-gate
NMOS process technology_
o
•
Features
1. 1,024-word-by-4-bit organization
2. Single + 5V power supply
3. Fully static oper~tion (no refresh or clockrequired)
4. All inputs and outputs TTL compatible
5. Three-state outputs.
6. Access time (MAX.) : ,200ns
7. 18-pin dual-in-line package
•
Top View
Block Diagram
Address Input
'"
"...'"
)-----------~~==~ ~ ...~
c "
)-----------c~=====1 ]o 8"
)--_ _ _--{:(~==~
M emory Array
64 Rows
64 Columns
U I=l
Row
I/O
Circuits '
Row Address
Decoders
T
Address Input
680
LH2114L-20
NMOS 4096-Bit Static Random Access Memory
•
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
Vcc
VIN
VOUT
Topr
T.tK
Ratings
-0.5-+7.0
-0.5-+7.0
-0.5-+7.0
0-+70
-55-+150
Unit
V
V
V
t
t
*The maximum applicable voltage on any pin with respect to GND.
•
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input leakage current
Output leakage current
Current consumption
•
(V cc =5V±10%, Ta=0-+70t)
DC Characteristics
Symbol
VIL
VIH
VOL
VOH
I ILl I
I ILO I
Icc
TYP.
MAX.
0.8
2.0
IoL =2mA
IoH =-lmA
VIN=OV or Vcc
CS=V IH, VI/0 =0.4V or Vcc
VIN =5.5V,IlIo=OmA
0.4
2.4
Unit
V
V
V
V
10
~A
10
pA
mA
70
AC Characteristics
(1) Read cycle
i
MIN.
Conditions
Parameter
Cycle time
Access time
Chip enable time
Chip select time
Output turn·off time
Output hold time
(Vcc=5V± 10%, Ta=0-+70t)
Symbol
tRc
t ACC
tCE
tcs
tOF
toH
(2) Write cycle
Parameter
Cycle time
Access time
Pulse width
Recovery time
Data setup time
Output turn·off time
Data hold time
MIN.
200
TYP.
MAX.
200
80
10
70
20
Unit
ns
ns
ns
ns
ns
ns
(Vcc=5V±1O%, Ta=0-+70t)
Symbol
twc
tAW
twp
tWR
tow
tOF
tOH
MIN.
200
15
170
15
100
TYP.
MAX.
70
0
Unit
ns
ns
ns
ns
ns
ns
ns
Conditions for measurment of AC characteristics
• Input signal level .. ·········································· +OA-+2AV
• Input signal rise/fall time ·································10ns
• Time measurement level .................................. ·1.5V
• Output load condition····································· .. 1TTL + 100pF
681
NMOS 4096-Bit Static Random Access Memory
•
LH211.4L-20
Pin Capacitance
Parameter
Input capacitance
Input/output capacitance
•
(f=lMHz, Ta=25'C)
Symbol
CIN
CliO
MIN.
Conditions
VIN=OV
VI/O=OV
TYP.
2
4.5
Timing Diagram
(1)
Read cycle
i--------tRC-------'"'i
i-----tACC--_
(Note) WE is "High"
(2)
Write cycle
Ao-Ag
CS
682
1
tire
tAIr
,. 3
MAX.
5
10
Unit
pF
pF
NMOS 4096-Bit Static Random Access Memory
•
LH2114L-20
Electrical Characteristics Curves (Vcc=5V, Ta=25t unless otherwise specified)
Access time vs. supply voltage
Access time vs. ambient temperature
1.2
1.2
V
~
~
..eco
..
~
..
\
.:::'"
~
1.1
<.>
<.>
1.0
~
j
]'"
.,.,
..,..,'"
0.9
.:::'"
"'"
1.1
~
/
/'
~
"""'-
--
<.>
<.>
1.0
j
]'"
.....
..,..,'"
/'
./
0.9
...:
...:
0.8
4.0
4.5
5.0
Supply voltage Vee
0.8
6.0
5.5
50
c
40
.E:>
~
V
~
V
<.l
~
-.
V
./
40
.,"
.'..'co""
...:
30
OIl
20 0
6.0
5.5
4.5
5.0
Supply voltage Vee (V)
25
50
"
75
100
(,C)
Input voltage vs. ambient temperature
2.5
2.5
2.0
2.0
:c
:5
.'"
~
Ambient.temperature Ta
>
;;.-
~
Co
Input voltage vs. supply voltage
..J
..........
'"
..,"
.E:>
Co
30
20
4.0
50
c
,/
~
?::
100
('G)
60
...:
..
:f
..'..'""
...:
75
...:
~
il
50
Average supply current vs.
ambient temperature
60
-..'"
25
Ambient temperature Ta
Average supply current vs.
supply voltage
<.>
o
(V)
VII!:--
1.5
~
OIl
.
.±:
i
:; 1.0
Co
.E
0.5
4.0
VlH
VIL
~
VIL
0
> 1.5
1.0
.E
4.5
5.0
Supply voltage Vee
5.5
(V)
6.0
50
75
25
100
Ambient temperature Ta ('C)
683
--------_....... .. ....- ..................- CMOS 4096""Bit Static Random Access Memory:'
.- .-
LH5114-4
•
LH5114-4
-
CMOS 4096. . Bit Static Random
Access
.
Memory
.'
\
•
Description
Pin Connections
The LH5114-4 is a fully static RAM organized
as 1024-word-by-4-bit by using silicon-gate
CMOS process technology.
o
•
Features
1. 1,024-word-by-4-bit organization
2. Single + 5V power supply
3. Fully static operation
4. All inputs and outputs TTL compatible
5. Three-state outputs
6. Access time (MAX.) : 450ns
7. Data can be held on + 2V supply voltage
8. Supply current at standby mode 10 ~A
(MAX.) on + 2V supply voltage
9. 18-pin dual-in-line package
•
Top View
Block Diagram
Memory Array
32 Rows
128 Columns
Chip Select Input ~
....--..
'fY=)
Write Input lO~-+~_~f---------rHH-t-----'
~----------------~~~~~~--------~
'----v--'
Address Input
684
LH5114-4
CMOS 4096-Bit Static Random Access Memory
•
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
Ratings
-0.3-+7.0
-0.3-V ee +0.3
-0.3-V ee +0.3
0-+70
-55-+150
Vee
VIN
VOUT
T oDr
Tst~
Unit
V
V
V
"C
"C
*The maximum applicable voltage on any pin with respect to GND.
•
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
Input voltage
Operating temperature
•
TYP.
5
MAX.
5.5
0.65
Vee
70
Unit
V
V
V
"C
(V ee =5V±10%, Ta=0-+70"C)
DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input leakage current
Output leakage current
Current consumption
Chip disabled current
consumption
•
MIN.
4.5
-0.3
2.2
0
Vee
V1L
VIH
Toor
Symbol
V1L
VIH
VOL
VOH
I ILl I
I lLO I
Icc
Conditions
IOL=2mA
IoH =-lmA
V1N=OV or Vee
CSS;:V IH • VIIO =O.4V or Vee
CS;;;;;0.65V. VIN=Vee=5.5V
CS;;;;;Vee,O;;;;;VIN;;;;;Vee
IeeL
TYP.
MAX.
0.65
1.0
1.0
15
Unit
V
V
V
V
pA
pA
rnA
100
pA
Vee
0.4
2.4
6
(V ee =5V±10%, Ta=0-+70"C)
AC Characteristics
Parameter
Read cycle
Cycle time
Access time
Chip enable time
Data hold time
Chip turn·off time
Write cycle
Cycle time
Chip select time
Chip select hold time
Access time
Address setup time
Pulse width
Recovery time
Data setup time
Data hold time
MIN.
-0.3
2.2
t
Symbol
t
MIN.
t Re
tAee
teo
tOH
tOF
450
twe
lew
teH
tAW
t AS
twp
tWR
tow
tOH
450
400
20
350
100
250
70
250
50
t
TYP.
t
MAX.
450
500
0
150
t
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test conditions of AC characteristics
• Input voltage amplitude ........................................... +0.65- +2.2V
• Input rising/falling time .......................................... IOns
• Timing reference level .......... · ................................. 1.5V
• Output load condition· ............................................ 1TTL + 100pF
.---.-~.---SHARP.-----.---
685
CMOS 4096-Bit Static Random Access Memory
•
LH5114-4
Low-Voltage Data Hold Characteristics
Parameter
Supply voltage for data hold
Symbol
Conditions
-
2.2V~VCC(PD ~Vcc
CS voltage for data hold
VCC(CS)
Supply current for data hold
Chip turn-off time
Operation recovery time
Icc PD
ts,PD)
tRPD
VIN=Vcc=2.0V
Symbol
CIN
Conditions
VIN=OV
VIIO=OV
•
MIN.
2.0
2.2
VCCPD
VCC(PD)
2.0V~VcgpQt~2.2V
TYP.
0.5
MAX.
10
Unit
V
V
V
pA
ns
ns
tRC
tRc
Capacitance
Parameter
Input capacitance
Output capacitance
•
CliO
MIN.
TYP.
MAX.
15
35
Timing Diagram
(1)
Read cycle
CS
1/01-1/0.
(Data output)
(2)
Write cycle
twc
tCH
tcw
cs \ \ \ '\
-J- / / / / / /
tAW
tAS ~ \
WE
1/01-1/0.
I
(D ata input)
(3)
'k.
tWR_
twp
«E
Low-voltage data hold
5V
VCC(PD)
OV
tDW
Fixed data
"I .. tDH~
»
Unit
pF
pF
LH5114-4
CMOS 4096-Bit Static Random Access Memory
•
Electrical Characteristics Curves (Vcc=5V. Ta=25"C unless otherwise specified)
Access time vs. supply voltage
1.4
Access time vs. ambient temperature
1.4
Ta=70'C
Vee =4.5 V
~
.
..3
>
.,/'
.~ 1.2
-............
tl 1.0
III
r---........
~
~
-............
III
.§
.,
~
..:"
:; 0.8
0.6
4.0
./
./
]
4.5
5.0
Supply voltage
~ 1.0
"-
5.5
Vee
V
III
.5
:; 0.8
.,.,
..:""
0.6
6.0
o
(V)
25
50
75
Ambient temperature Ta
100
('C)
Average supply' current vs.
Average supply current vs. ambient
supply voltage
temperature
20
20
..:
.5
tl 15
......
~...
e
10
1
;,
...
5
III
>
..:
u
15
".,......
10
~
o
-- ---
4.0
4.5
~
""
~
..,. r----- r--
~
8:
.,
.,"
>
..:
5.0
5.5
Supply voltage Vee
o
6.0
...
III
.,
~
1.0
.:::0
1>
I
-
:>
1.0
eC)
-
Vw
VIL
::
::
:>
r---
= 1.5 ....
:>
:>
100
75
2.0
G
1.5
50
r--
Input voltage vs. ambient temperature
2.0.----,-----r---...,----,
G
25
---
Ambi~nt temperature Ta
(V)
Input voltage vs. supply voltage
=
5
...
>
"S
0.5
.s"'"
o~--~-~~--~--~
4.0
4.5
5.0
5.5
6.0
Supply voltage
Vee
(V)
0.5
o
25
50
Ambient temperature
75
Ta
100
('C)
---.-----SHARP-...-.------~
687
................ -.....
........... ................-....,.....
CMOS'4096-Bit Static Random Access Memory
" "'LH5104-4
~.-~....,
LH5104-4
,•
.-'
CMOS 4096-Bit Static Random Access
Memory
"
Description
•
Pin Connections
The LH5104-4 is a fully static ~AM organized
as 4,096-word-by-l-bit by using silicon-gate
CMOS process technology.
o
•
Features
1. 4,096-word-by-l-bit organization
2. Single +5V power supply
3. Fully static operation (no refresh or clock reo
quired)
4. All inputs and outpu~s TTL compatible
5. Three-state outputs
6. Access time (MAX.) : 450ns
7. Data can be held on + 2V supply voltage
8. Supply current at standby mode 10 pA on
+ 2V supply voltage (MAX.)
9. l8-pin duai-in-line package
•
Top View
Block Diagram
Row
Address
Decoders
Data Input 1ll}--i-----1----:~-11>-------1
l---i>-----i.7 Data Output
Chip Select Input 10!}--;~---==:;J:J_ _ _.J
Write Input
688
8)....;~:±~J---------++-H-+++--...J
CMOS.4096-Bit Static Random Access Memory
•
LH51 04-4
Absolute Maximum Ratings
Parameter
Supply voltage *
Input voltage *
Output voltage *
Operating temperature
Storage temperature
Symbol
Vee
V IN
V OUT
TQI>r
T~
Ratings
-0.3-+7.0
0.3 Vee+ 0.3
-0.3 Vee+ 0.3
0-+70
-55 +150
Unit
V
V
V
"C
"C
*The maximum applicable voltage on any pin with respect to GND.
•
(Vee =5V±10%, Ta=0-+70"C)
DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input leakage current
Output leakage current
Symbol
VIL
VIH
VOL
VOH
I ILl I
I Iw I
Current consumption
Icc
Chip disabled current
consumption
IeeL
•
Conditions
MIN.
TYP.
MAX.
0.65
1.0
1.0
Unit
V
V
V
V
pA
pA
15
rnA
50
pA
2.2
IOL -3.2mA
IOH ImA
VIN OV or Vee open
CS- VIH, VOUT OAV or Vee open
CS- VIN , Output open
VIN =V ee =5.5V
CS~Vee,
004
204
VIN=OV or Vee
7
AC Characteristics
(1)
(V ee =5V±10%, Ta=0-+70·C)
Read cycle
Parameter
Cycle time
Acc·ess time
Chip enable time 1
Data hold time from address
Chip turn-off time
Output enable time
Symbol
t Re
t Aee
teo
taH
tOF
ta~
(2) Write cycle
Parameter
Cycle time
Chip select time
Access time
Address setup time
Pulse width
Recovery time
Data setup time
Data hold time
Output disable setup time
Output enable setup time
MIN.
450
TYP.
MAX.
450
450
30
120
20
Unit
ns
ns
ns
ns·
ns
ns
(V ee =5V±10%, Ta=0-+70"C)
Symbol
twe
tew
tAW
t AS
twp
tWR
tow
tOH
twz
tow
MIN.
450
320
340
120
200
90
200
300
TYP.
MAX.
110
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test conditions of AC characteristics
• Input voltage amplitude··················· ........................ + 0.65 - + 2.2V
• Input rising/falling time ··········································10ns
• Timing reference level· .......................................... ·1.5V
• Output load condition ................. ····························1 TTL+ 100pF
.-.-----~--.....-.--SHARP .-.~--.--.-.--
689
LH51 04-4
CMOS 4096.;.Bit Static Random Access Memory
•
(f=lMHz, Ta=25"C)
Capacitance
Parameter
Input capacitance
Output capacita~ce
•
Symbol.
CIN
COUT
Conditions
YIN=OY
YOUT=OY
MIN.
TYP.
-
CS v:oltage for data hold
Supply current for data hold
Chip turn·off time
Operation recovery time
YI
Icc PD
tS(pD
tR PD)
Conditions
2.2Y';;:YccPD ';;:Ycc
2.0Y~YCC(PD)~2.2Y
Unit
pF
pF
(Ta=0-+70·C)
Low-Voltage Data Hold Characteristics
Parameter
Symbol
Supply voltage for data holding YCCPD
MAX.
6
15
MIN.
2.0
2.2
YCC(PD)
YIN =Y cc =2.0Y
TYP.
Unit
Y
Y
0.2
t RC
tRc
MAX.
10
flA
ns
ns
'-~-------SHARP~-----'----
690
CMOS 4096-Bit Static Random Access Memory
•
Timing
(1)
LH51 04-4
Diagram
Read cycle
tRC
"V
\V
11\
1\
tOH
tACC
~
tc
cs
\\\\
,'/////1///
~
tou
DOUT
-
tDF
V L II
1\-"'.1'--
Valid data
\
"
\
/J
(2) Write cycle
fE-------twc:--------t
WE
DOUT
(3)
Low-voltage data hold
4.5V
VCC(PD)
OV _~C:.:::S:",-......J
691
CMOS 4096-Bit Static Random Access Memory
•
Electrical Characteristics Curves (Vcc=5V, Ta=25"C unless otherwise specified)
Access time vs. supply voltage
.,.a
1.4
10
;;
1.2
~
Il:::
($ 1.0
;;
.~'"
Ul
Ul
0.8
'"
<""
0.6
1.4
Ta=700e
...
.=:'"
Access time vs. ambient temperature
4.0
...
""
4.5
-............
~
.!!l
'"
Il:::
1.2
u
u
1.0
;;
~
.~'"
Ul
Ul
5.5
Supply voltage Vee (V)
6.0
15
u
......u
10
1
--------,
Ul
.-
5
..
<'"
o
4.0
4.5
~
5.5
5.0
Supply voltage Vee
2.0
G
..
...'"
1.0
..
~
i
..s
----
1.5
>
>
o
25
50
75
100
Ambient temperature Ta (Oe)
~
'ill.
~
4.0
C
.,
...
""
i
.'".."
~
r--
5
..'"
----
~~
<
o
25
50
75
---
100
(Oe)
Ambient temperature Ta
Input voltage .vs. ambient temperature
2.0
G
...
1.5
>
..
>
..'"
1.0
---
--- -
VIH
~L
!
..
'0
1
4.5
10
Ul
6.0
0.5
o
15
(V)
Input voltage vs. supply voltage
...
,
<
3
C
.'."
/
20
<
""
/
Average supply current vs. ambient
temperature
3
..'"
/'
0.8
0.6
5.0
20
u
V
/
"'"
<"
Average supply current vs. supply
voltage
......u
Vee=4.5 V
~
5.0
Supply voltage Vee
5.5
(V)
0.0
0.5
0
25
50
100
75
Ambient temperature Ta
ee)
-----~--~----SHARP.-.-.--.-----
692
CMOS 16384-Bit Static Random Access Memory
LH5116-15/LH5116-20
LH5116-15/LH5116-20
CMOS 16384-Bit Static Random Access Memory
•
Description
The LH5116-15/LH5116-20 are fully static
RAMs organized as 2,04S-word-by-S-bit by using
silicon-gate CMOS process technology_
•
•
Pin Connections
o
Features
2,04S-word-by-S-bit organization
Single +5V power supply
Fully static operation
All inputs and outputs TTL compatible
Three-state outputs
Access time (MAX.)
LH5116-15: 150ns, LH5116-20 : 200ns
7. Supply current at standby mode 10 pA
(MAX.) on + 2V supply voltage
S. 24-pin- dual-in-line package
L
2_
3_
4.
5.
6.
•
Top View
Block Diagram
~VCC
Memory- Array
128 Rows
128 Columns
~GND
Column
Address Buffers
Write In put,$l
}-
Chip Select 18~-t--tL:::8:=:::::
Output Enable 20
)}-----+-11-+--+--------'
1
L---~====~~--------~~r-----------------------~
Address Input
693
LH5116-15/LH5116-20
CMOS 16384-Bit Static Random Access Memory
Absolute Maximum Ratings
•
Parameter
Supply voltage *
Input voltage *
Operating temperature
Storage temperature
Symbol
Vcc
VIN
T OPT
T stg
Ratings
-0.3-+7.0
-0.3-Vcc +0.3
0-+70
-55-+150
Unit
V
V
'C
'C
*The maximum applicahle voltage on any pin with respect to GND.
•
(Vcc=5V±10%. Ta=0-+70'C)
DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input leakage current
Output leakage current
Current consumption
Current consumption
during standby
Symbol
V1L
VlH
VOL
VOH
I ILl I
I ILO I
ICCI
Icc2
ICCL
MIN.
-0.3
2.2
Conditions
IOL=2.1mA
IoH =-1.0mA
VIN=OV. Vcc
CS=V lH• Vl/o=OV-Vcc
Il/o=OmA (OE=Vccl
Il/o=OmA (OE=V lH )
CS=V cc. all other input pins=
OV-Vcc
TYP.
MAX.
0.8
Vcc+ 0.3
0.4
1.0
1.0
30
40
Unit
V
V
V
V
pA
pA
rnA
rnA
10
pA
2.4
15
25
Note
1
2
Notel: CS=OV; all other input pins=Vcc
Note 2: CS=VIL; all other input pins=VIH
•
AC Characteristics
(1)
Read cycle .
Parameter
Cycle time
Access time
Chip enable time
Chip select time
Output enable time
Output select time
Output turn-off time (from CE 2)
Output turn-off time (from CEll
Data hold time
(Vcc=5V±10%. Ta=0-+70'C)
Symbol
tRc
t ACC
teE
tcs
tOE
tos
tOFl
tOF2
tOH
MIN.
150
LH5116-15
TYP.
MAX.
LH5116-20
TYP.
MAX.
150
150
15
200
200
20
100
75
15
0
0
40
40
15
(2) Write cycle
20
0
0
20
60
60
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Vcc =5V±10%. Ta=0-70'C)
Parameter
Symbol
Cycle time
Chip select time
Access time
Address setup time
Pulse width
Recovery time
Output turn-off time (from OE)
Data setup time
Data hold time
Output turn-off hold time
(from WE)
Output turn-off time (from OE)
twc
tcw
' tAw
tAs
twp
tWR
tOFl
tow
tOH
tow
tOF2
MIN.
150
110
110
0
110
20
LH5117-15
TYP.
MAX.
MIN.
200
135
135
5
140
35
LH5117-20
TYP.
MAX.
Unit
70
10
80 .
10
ns
ns
ns
as
ns
ns
ns
ns
ns
15
20
ns
40
40
--~-'---~--SHARP
694
MIN.
200
60
60
ns
---.-.-----------
LHS116-1S/LHS116-20
CMOS 16384-Bit Static Random Access Memory
Conditions for measurement of AC characteristics
• Input voltage amplitude ........................................... +0.8- + 2.2V
• Input signal rise/fall time ................ ························10ns
• Time measurement level ····································· .... ·1.5V
• Output load condition ............................................. 1TTL + 100pF
•
Low Supply Voltage Data Hold Characteristics: (Vee =5V±10%, Ta=0-70'C)
Parameter
Data hold supply
voltage
Data hold supply
current
CS setup time
CS hold time
•
Symbol
Conditions
VeeDR
VCs"=Vee, VIN=OV or Vee
IecDR
Vee=Ves=2.0V,
VIN=OV or Vee
MIN.
MAX.
2.0
t Re
tRe
tSDR
tRDR
Unit
V
10
pA
ns
ns
(f=lMHz, Ta=25'C)
Capacitance
Parameter
Input capacitance
Input! output capacitance
•
TYP.
Symbol
CIN
CliO
Conditions
VIN=OV
VlIO=OV
~
MIN.
TYP.
MAX.
5
8
Unit
pF
pF
Timing Diagram
(1)
Read cycle
----tRc-----ti--...j
~:::::::-t-Ac-C~~--~--~---~.-,~~-tO-H----------cs
1------tCE----~"'"
I/O}-I/Os
~--.------SHARP.-----~.-.-~.---
695
.....
....
CMOS.16384-Bit Static Random Access Memory
~
(2)
~.-~~.-~
.-~
LH5116-15/LH5116-20
---.-~
Write cycle (Note 3)
~-----------twc----------~
Ao-AIO
1--------tAW -------+-~;o.j
cs
Note 3:· WE must be high when there is a change in Ao-Alo.
Note 4: When CS and WE are alLlow at the same time, write occurs during the. period twP.
Note 5: tWR is the time from the rise of CS or WE, whichever is first, to the end of the write cycle.
Note 6: During this period the input/output pin is in an output condition, so input with a phase reversed from
that of the output is not permitted.
Note 7: If CS should drop at the same time as WE or later, the output buffer is maintained at high impedance.
Note 8: OE is maintained at "L" level.
Note
9: DOUT outputs data with the same phase as the input data of this write cycle.
Note 10 : If CS is low during this period, the input/output pin is in the output condition. During this condition, a
data input signal with a phase opposite that of the output is not permitted.
(3)
Low supply voltage data hold
~-----;;+<-------
Data hold time
-----~ofE_=:.::...~
5.0V
4.5V
VIH
VCCDR
VIL
GND
696
--------------------------------
CMOS 16384-Bit Static Random Access Memory
•
LH5116-15/LH5116-20
Electrical Characteristics .Curves (Vcc=5V, Ta=25"C unless otherwise specified)
Access time vs. supply voltage
.,.e
Access time vs. ambient temperature
.,.e
1.2
...,.
1.1
.~
1;;
Ql
~
1.0
u
u
""~
.j
.,
.!
.,
1.2
..
.,..
.~
~
1.1
Il::
u
u 1.0
~ ...........
.,
.!
.,
0.9
C/l
C/l
C/l
C/l
/
V
0.9
..:""
..:""
0.8
4.0
4.5
5.0
Supply voltage Vee
5.5
0.8
6.0
o
CV)
25
50
75
Ambient temperature Ta
Average supply current 1 vs.
supply voltage
100
C·C)
Average supply current 1 vs.
ambient temperature
25
25
..:
-!
..:
-!
~
20
u
......u
-.,""
""
"
i
".,
...,.
.."
..:
C/l
15
/
,/
u
.;:;
/'
/
20
C
.,
"
""
b"
15
is:
.'..""
"
C/l
10
-- ---
r-- t---
10
..
..:'"
5
4.0
4.5'
5.0
Supply voltage Vee
5.5
25
6.0
CV)
75
100
C·C)
Input voltage vs. ambien! temperature
2.5
2.5
2:
2:
"
50
Ambient temperature Ta
Input voltage vs. supply voltage
2.0
".,
2.0
>
>
>=
.,OIl
~
.j
./
.
.::
1.5
$-=
1.0
..
0
0.5
4.0
---
~
4.5
~
5.0
Supply voltage Vee
~
>
-
.::0
'"~
VIL
5.5
CV)
1.5
VlH
..
$-=
6.0
VIL
1.0
0.5
o
25
50
75
Ambient temperature Ta
100
(·C)
--------SHARP-~-.-----
697
.........,.........,.....,.....,-
CMOS 16384-Bit Static Random Access Memory
.
LH5117 .:.15/LH5117-20
.-..-......,.....,.-.~
-.....,,.....,
LH5117-15/LH5117-20
CMOS 16384-Bit Static Random Access rtlemory
•
, •
Description
Pin Connections
The LH5117-15/LH5117-20 are f.ully static
RAMs organized as 2,048-word-by-8-bit by using silicon-gate CMOS process technology.
•
o
Features
1. 2,048-word-by-8-bit organization
2. Single +5V power supply
3. Fully static operation
4. All inputs and outputs TTL compatible
5. Three-state outputs
6. Access time (MAX.)
LH5117-15: 150ns, LH5117-20: 200ns
7. Supply current at standby mode 10 pA (MAX.)
on + 2V supply voltage
8. 24-pin dual-in-line package
•
Top View
Block Diagram
--lvcc
~GND
Memory Array
128 Rows
128 Columns
.~~______~~~r-~---------~,~
Data I/O
:ro
¥s
-ui
~
!
r---,
~
'is
Sense Amp.
L---->.
I
.
~
O r :
:::::---->-+-I+t+h
t
t
~
Column
Address Buffers
Write Input~
Chip Enable
::::---
'y-
{~r-jH~=8;:::::~)}-____-+--+--l_+-______--'
L--=====::::.-_.....:..__
--{4
5
6
.7~}----------------l
~
Address Input
698
hIII ~I>-+-+-f-h
Column Decoders
'-r-
f
~
.5il~~
L-k
~
CMOS 16384-Bit Static Random Access Memory
•
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Operating temperature
Storage temperature
•
Symbol
Vcc
VIN
ToDr
Tstg
Ratings
-0.3-+7.0
-0.3-V cc +0.3
0-+70
-55-+150
Unit
V
V
"C
"C
(V cc =5V±10%. Ta=0-+70"C)
DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input leakage current
Output leakage current
Current consumption
Current consumption
during standby
Notel:
Note 2:
•
LHS117-1S/LHS117-20
Symbol
V1L
VIH
VOL
VOH
I ILl I
I Iw I
Iccl
Icc2
ICCL
Conditions
MIN.
-0.3
2.2
ICL=2.1mA
IoH =-1.0mA
VIN=OV-Vcc
CS2=V IH • VIIO=OV-Vcc
IIIo=OmA (CEl=Vcd
IIIo=OmA (CE I =V IH )
CE 2=V cc. all other input
pins=OV-Vcc
MAX.
0.8
Vcc+ 0.3
0.4
1.0
1.0
30'
40
Unit
V
V
V
V
pA
pA
rnA
rnA
10
pA
2.4
15
25
Note
1
2
CE2=QV; all other input pins=Vcc
CE2=VIL; all other input pins=VIH
AC Characteristics
(1) Read cycle
Parameter
Cycle time
Access time
Chip enable time
Chip select time
Output enable time
Output select time
Output turn·off time (from CE 2)
Output turn·off time (from CEll
Data hold time
(2)
TYP.
(Vcc=5V±10%. Ta=0-+70"C)
Symbol
tRC
t ACC
tCE
tcs
tOE
tos
tDFl
tDF2
toH
MIN.
150
LH5117-15
TYP.
MAX.
MIN.
200
200
200
150
150
15
20
75
15
0
0
15
LH5117-20
TYP.
MAX.
40
40
Write cycle
100
20
0
0
20
60
60
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Vcc =5V±10%. Ta=0-70"C)
Parameter
Symbol
Cycle time
Chip select time
Access time
Address setup time
Pulse width
Recovery time
Output turn-off time (from WE)
Data setup time
Data hold time
Output turn-off hold time
(from WE)
twc
tcw
tAW
tAS
twp
tWR
tDF
tDW
tDH
tow
MIN.
150
110
110
0
110
20
LH5117-15
TYP.
MAX.
MIN.
200
135
135
5
140
35
LH5117-20
TYP.
MAX.
Unit
70
10
80
10
ns
' ns
ns
ns
ns
ns
ns
ns
ns
15
20
ns
40
---~"""-'--'-'--SHARP
60
------.-.----.-.
699
CMOS 16384-Bit Static Random Acce~s Memory
LH5H7-15/LH5117;.20
Conditions for measurement of AC characteristics
• Input voltage frequency width .: ............................... + 0.8 - + 2.2V
• . Input signal rise/fall time
.··············,··················10ns
• Time measurement level
·························:·······1.5V
• Output load conditions
······· .. ·····················:··1 TTL+ 100pF
•
. Low Supply Voltage Da~a Hold Characteristics
Parameter"
(Vcc =5V±10%. Ta=0-70"C)
Symbol
Conditions
MIN.
Data hold' supply voltage
VCCDR
V~E2=VCC. VIN=OV or Vcc
2.0
Data hold supply voltage
IccDR
VCC=VCE2=2.0V.
VIN=OV or Vcc
CS setup time
CS hold time
tSDR
tRDR
•
MAX.
Unit
V
10
pA
ns
ns
t RC
t RC
(f=1MHz. Ta=25"C)
Capacitance
Parameter
Input capacitan<;e
Input! output capacitance
•
TYP.
Symbol
CIN
CliO
Conditions
VIN=OV
VlIO=OV
MIN.
TYP.
MAX.
5
8
Unit
pF
pF
Timing Diagram
(l)
Readicycle
1-------tRC-----~~
~:= =-=-=-=- t-AC-C-=-=- =- =- =- =- . . .;-~;!-ci-tO-H-----
CE2
~----tCE----_3>oj
-.----------,-SHARP----.---~~.---
700
CMOS 16384-Bit Static Random Access Memory
LH5117-15/LH5117-20
(2) Write cycle (Note 3)/
~----------twc----------~~
~---------tAW--------~~~
14--+--- tcw (Note 7) --------;~
Note 3 : WE must be high when there is a change in Ao-AlO.
Note 4 : When CE2, CEI, and WE are all low at the same time, write occurs during the period twP.
Note 5 : tWR is the time from the rise of CE2 and CEI or WE, whichever is first, to the end of the write cycle.
Note 6 : During this period the input/output pin is in an output condition, so input with a phase reversed from that of
the output is not permitted.
Note 7 : If CE2 or CEI should drop at the same time as WE or later, the output buffer is maintained at high impedance.
Note 8 : Dour outputs data with the same phase as the input data of this write cycle.
Note 9 : If both CEI and CE2 are low during this period, the input/output pin is in the output condition.
(3) Low supply voltage data hold
5.0V
4.5V
VIH
VCCDR
VIL
GND
--------------------------------
-----------SHARP----.-.-.----701
OMOS 16384-Bit Static Random Access Memory
LH5117-15/LH5117-20
Electrical Characteristics Curves (Vcc=5V, Ta=25°C unless otherwise sp~ified)
•
Access time vs. supply voltage
.,
Access time vs ..ambient temperature
.,
1.2
.,.
,...
..e
III
.:=
..e
...
1.1
III
~
<.l
<.l
III
1.0
<
.,.,
~
<.l
<.l
1.0
.,.,
<""
0.9
III
<""
0.8
4.0
4.5
5.0
Supply voltage
5.5
Vee
0.8
6.0
CV)
<
C'C)
<
20
<.l
<.l
....
15
10
"...,
~
~
~
...'"
...
...'",.
III
III
20
III
b"
.,~
15
10
- --
r----
--
III
<
<
5
4.0
4.5
5.0
Supply voltage Vee
5.5
25
6.0
50
Input voltage vs. supply voltage
~
100
75
Ambient temperature Ta
CV)
C'C)
Input voltage vs. ambient temperature
2.5,-----r----.,---,----....,
2.5
~
:::l 2 . 0 1 - - - - t - - - + - - - + - - _ j
:>
:::l 2.0
:>
=
VIH
:>
1.51----t---+--==;;;;;;o-+~=-_j
~
.:::
~
11.01---+---+----+-----j
0.5 L-_ _I-_--:-I-_--:-I.:-_~
4.0
4.5
5.0
5.5
6.0
Supply voltage V cc
702
100
75
-.§.
/
III
50
25
-.§.
....
b"
...,g;
..,.g:,
25
Average supply current 1 vs.
ambient temperature
25
i..
o
Ambient temperature Ta
Average supply current 1 vs.
supply voltage
<.l
/
V
.,
.!j
III
....<.l
/'
:!
~
0.9
V
./
1.1
~
I'"
III
]
.:=
"~
]
..
1.2
(V)
-
-VIH
r-VIL
25
50
75
Ambient temperature Ta
100
C'C)
CMOS 16384-Bit Static Random Access Memory
LH5118-15/LH5118-20
LH5118-15/LH5118-20
CMOS 16384-Bit Static Random Access Memory
.
•
•
Description
Pin Connections
The LH5118-15/LH5118-20 are fully static
RAMs organized as 2,048-word-by-8-bit by using silicon-gate CMOS process technology.
•
o
Features
1.
2.
3.
4.
5.
6.
2,048-word -by- 8- bit organization
Single +5V power supply
Fully static operation
All inputs and outputs TTL compatible
Three-state outputs
Access time (MAX.)
LH5118-15: 150ns, LH5118-20: 200ns
7. Supply current at standby mode 10 pA (MAX.)
on + 2V supply voltage
8. 24-pin dual-in-line package
•
Top View
Block Diagram
Memory Array
128 Rows
128 Columns
"0
!::c
Data I/O
o
U
L~===~::!.:"'::"'::::'::'-_-<4
5
6
7 } - - - - - - - -_ _ _ _....I
\ Addresvs Input
J
~.-.-------SHARP--.------
703
lH5H8-15/LH5118-20
CMOS:16384..;Bit Static Random Access Memory
•
Abs.olute Maximum Ratings
Parameter
Supply voltage
Input voltage
Operating temperature
Storage temperature
•
Symbol
Vcc
VIN
Toor
T st•
Ratil).gs
-0.3-:-+7.0
-0.3-Vcc +0.3
0-+70
-55-+150
Unit
V
V
"C
"C
(Vcc=5V± 10%. Ta=O- +70"C)
DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input leakage current
Output leakage current
Symbol
V1L
VIH
VOL
VOH
I ILl 1
I Iw I
Current consumption
ICCI
Icc2
Current consumption
during standby
IccL
Conditions
MIN.
-0.3
2.2
ICL=2.1mA
IoH =-1.0mA
VJN=OV-Vcc
CE 2=V IH or CE I =V IH •
Vl/O=OV-Vcc
Il/o=OmA (WE=Vccl
Il/o=OmA (WE=V1Ll
CE 2 and CE I = Vcc. all other
input pins=OV-Vcc
TYP.
MAX.
O.B
Vcc+ 0.3
0.4
1.0
Unit
V
V
V
V
pA
1.0
pA
30
40
rnA
rnA
10
pA
2.4
15
25
Note 1: CE2=CEl=OV; all other pins=Vcc
Note 2: CE2=CEl=VIL; all other pins=VIH
•
AC Characteristics
(1)
Parameter
Cycle time
Access time
Chip enable time
Chip select time
Output enable time
Output select time
Output turn-off time (from CE 2)
Output turn-off time (from CEll
Data hold time(from address)
(2)
(Vcc =5V±10%. Ta=0-+70"C)
Read cycle
Symbol
tRc
tACC
tCE
tcs
tOE
tos
tOFl
tOF2
tOH
LH511B-15
TYP.
MAX.
MIN.
200
150
150
15
15
0
6
LH511B-20
TYP.
MAX.
200
200
20
150
40
40 .
15
200
20
0
0
20
60
60
Unit
ns
ns
ns
'ns
ns
ns
ns
ns
ns
(V cc= 5V± 10%. Ta=0-70"C)
Write cycle
Parameter
Symbol
Cycle time
Chip select time
Access time
Address setup time
Pulse width
Recovery time
Output turn-off time (from WE)
. Data setup time
Data hold time
Output turn-off hold
time (froni WE)
twc
tcw
tAW
tAS
twp
tWR
t
tow
tOH
704
MIN.
150
tow
MIN.
150
110
110
0
110
20
LH511B-15
TYP.
MAX.
MIN.
200
135
135
5
140
35
LH511B-20
,MAX.
TYP.
Unit
70
10
BO
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
20
ns
40
60
Note
1
2
LHS118-1S/LHS118-20
CMOS 16384-Bit Static Random Access Memory
Conditions for measurement of AC characteristics
• Input voltage amplitude········ .. ································· +O.8-+2.2V
• Input signal rise/fall time .. ········· ·····························10ns
• Time measurement level· .. ·······································1.5V
• Output load condition············································· 1TTL + 100pF
•
Parameter
•
Symbol
Conditions
MIN.
Data hold supply voltage
VeeDR
Vcrz=Vee• VIN=OV or Vee
Z.O
Data hold supply current
IeeDR
Vec=VeE2=Z.OV.
VIN=OV or Vee
CS setup time
CS hold time
tSDR
tRDR
TYP.
MAX.
Unit
V
10
p.A
ns
ns
tRe
t Re
(f=lMHz. Ta=Z5"C)
Capacitance
Parameter
Input capacitance
Input/output capacitance
•
(V ee =5V±10%. Ta=0-70"C)
Low Supply Voltage Data Hold Characteristics
Symbol
C IN
CliO
Conditions
VIN=OV
VIIO=OV
MIN.
. TYP.
MAX.
5
8
Unit
pF
pF
Timing Diagram
(1) Read cycle
t-----tRc----\k--l
A.-AI.
~=-=- =- =- =- :. .-t-A-C - - - - - - - -l>.-I.......;{f-tO-H----o!
iE------tCE----~
iE----tcs-----i
~_r±_----r_~~
1/01-1/0.
705
/
CMOS 16384-Btt Static Random Access Memory
LH5118-15/LH5118-20'
(2) Write cycle (Note 3)
~------------twe----------~~
Note 3 : WE must be high when there is a change in AD-AID.
Note 4 : When CE2, CEI, and WE are all low at the same time, write occurs during the period twP.
Note 5 : tWR is the time from the rise of CE2 and CEI or WE, whichever is first, to the end of the write cycle.
Note 6 : During this period, the input/output pin is in an output condition, so input with a phase reversed from that of
the output is not permitted.
Note 7 : If CE2 or CEI should drop at the same time as WE or later, the output buffer is maintained at high impedance.
Note 8 : DOUT outputs data with the same phase as the input data of this write cycle.
Note 9 : If both CEI and CE2 are low during this period, the input/output pin is in the output condition. During
this condition, a data input signal with a phase opposite that of the output is not permitted.
(3)
Low supply voltage data hold
5.0V
4.5V
VlH
Vee DR
VIL
GND
'--~-~'-----SHARP"-""--'-'--~---
706
CMOS 16384-Bit Static Random Access Memory
•
LH5118-15/LH5118-20
Electrical Characteristics Curves (Vcc=5V, Ta=,25°C unless otherwise specified)
Access time vs. supply voltage
.,..e
...,.
.
.~
1.1
P:::
u
u
j
.,
.,.,
.,
..:""
]
.,..e
1.2
Ql
1.0
0.9
0.8
4.0
Access time vs. ambient temperature
1.2
..
"-
""
4.5
.,..
.~
..!S
.,
1.1
u
1.0
L
~
5.0
Supply voltage Vee
u
,/
j
.,
""
]
.,.,
.,
..:""
0.9
0.8
6.0
5.5
o
(V)
G 20
C
.,
15
10
/'
V
v
G 20
V
.,.
15
"
.Q
§:
.,os
10
C
.
..:"
5
4.5
5.0
6.0
5.5
o
25
50
75
100
(·C)
Input voltage vs. ambient temperature
2.0
C
1.5
2.0
'"
~
1.0
-- ----
--- -
;;-==
4.5
5.0
Supply voltage Vee
VIL
1.0
"~
.::co
..
VIL
:; 0.5
""
......c
c
......
0.5
4.0
VlH
;;-
VlH
1.5
"~
i
r--- r--
Ambient temperature Ta
Input voltage vs. supply voltage
..
5
(V)
2.5
==
;;-
'""'"
os
.."..
Supply voltage Vee
...
:>
-- --
..:i
.
4.0
C
100
(·C)
..:
5
..:i
.,
.,..""
..:
75
25
25
"
.Q
.,""os""
5Q
Average supply current 1 vs.
ambient temperature
..:
5
os
25
Ambient temperature Ta
Average supply current 1 vs.
supply voltage
..
/'
V
P:::
V
5.5
(V)
6.0
0
75
50
25
Ambient temperature Ta (·e)
100
707
NMOS6.5536-Bit Dynamic Random Access Memory
LH21.64-15/LH2164-20
LH2164-15/LH2164-20
NMOS 65536-Bit Dynamic Random Access Memory
•
Description
•
Pin Connections
The LH2164 is a dynamic RAM organized as
65,536-word-by-1-bit by using high-performance
depletion load, n-channel double-poly silicon-gate
MOS technology.
o
•
Features
1. 65,536-word-by-1-bit organization
2. Access time (MAX.)
LH2164-15: 150ns, LH2164-20 : 200ns
3. Cycle time (MIN.)
LH2164-15: 270ns, LH2164-20 : 330ns
4. Power supply: +5V±10%
5. Power dissipation (MAX.) : 248mW(operation)
: 28mW(standby)
6. All inputs and outputs TTL compatible
7. Address and input date latch capability. __
8. Three-state outputs date controlled by CAS
and not latched at the end of cycle
9. Common 110 capability using the early-write
mode
10. Read/modify/write, page-mode, RAS-only refresh, and hidden ~efresh capabilities
11. Built-in gated CAS function
12. Built-in biasing-voltage generator circuit for
high-output board
13. 2 ms refresh period, 128 cycle refresh
14. 16-pin dual-in-line package
Top View
------.-~-~---SHA~P-.-- ....... - . . . . - . . - -
708
NMOS 65536-Bit Dynamic Random Access Memory
•
LH2164-15/LH2164-20
Block Diagram
;;.,
''""
{Row
addres~.I.mn addrs. ~
-tWCR
I !WC~
\l--
~
twp
~--
X
tCWL
/
tRWL
-t'DHValid data
K
tDHR
High impedance
DOUT
(3)
Read write and read modify write cycles
tRWC
tRAS
~
tAR
1
tCSH
tRSH
tCAS
f-o---- t RCD---;---'"
/
\. \.
tA~ ~
-~ow
tASC
.-1"4-
-t~X
addres!x'
J
teAH
t---
Column address
~
~tCWL-
-tRWL-
-I
tRWD
.
k---tCAC------<
~~
'~" .§
t
20~--+----r--~----;
~
~ ~
4.5
5.0
Supply voltage Vee
5.5
100L-----2~5----~50~--~7~5----~100
6.0
Ambient temperature Ta
(V)
Average supply current during standby
vs. supply voltage
('C)
Average supply current during standby
vs. ambient temperature
5r-----------~----~----~
5
..
temperature
50r-----------~----~----~
E
g
Ta=O'C
e
am~ient
Ta=O'C
Vcc=5.5V
.S
.a..."
~
""..,
"
4r---..,.----r--~--~
4
....
;;.-<
~
3
~~
~~
f 1
r--2
~ .!!
---
---I---
-
3r-----+-----+-----~----~
~-t-_-l
gj,$
~ "'g
~ .!!
-< '"
2r---+----r--~--~
-< '"
1
4.0
5.0
5.5
4.5
Supply voltage Vee (V)
6.0
1~----~----~----~----~
.0
25
50
75
Ambient temperature Ta
100
('C)
.--------SHARP-----------715
LH2164;"15/LH2164~20 .
NMOS 65536-Bit Dynamic Random Access Memory
Average supply current during RAS only
refresh vs. ambient temperature
Average supply current during RAS only refresh
vs. supply voltage
\
40~----------~----~----~
40
I :::~
Ta=O'e
-------~
Vee=5.5V
.!f
30 ~--,--.-----+---/-----t
.g
i
~
..."
'a
<"
201---+----+---/-----t
Ei
~
~1
...
.t
~ ~
101---+----+---/-----t
< b6
o
4.0
4.5
5.0
5.5
O~----~----~----~----~
o
6.0
Supply voltage Vee (V)
Average supply current during page mode
vs. supply voltage
40
.e
...g...
30
i...
...
B<"
b
E! 20
~-.,
co
...,... "".., 10
0
~ E!
:>
..:
~
.
~
----
4.0
716
40
Vee=5.5V
301---.---+---~----~
~
,,~
b" ..:E! 20 1 - - - + - - - - + - - - ; - - - ;
~
""~
~i
...~ E! 1 0 1 - - - + - - - - + - - - / - - - - - t
~ ~
""
o
Average supply current during page mode
vs. ambient temperature
.
Ta=O'e
OIl
.e...
..g
25
50
75
100
Ambient temp·erature Ta ('e)
5.5
5.0
4.5
Supplyvoltage Vee (V)
6.0
°O~----2~5----~50-,----~75~--~100
Ambient temperature Ta
('e)
NMOS 65536-Bit Dynamic Random Access Memory
LH2164A-15/LH2164A-20
LH2164A-15/LH2164A-20
NMOS 65536-Bit Dynamic Random Access Memory
•
Description
•
Pin Connections
The LH2164A is a dynamic RAM organized as
65,536-word-by-1-bit by using high-performance
depletion load, n-channel double-poly silicon-gate
MOS technology.
o
•
Features
1. 65,536-word-by-1-bit organization
2. Access time (MAX.)
LH2164A-15: 150ns, LH2164A-20 : 200ns
3. Cycle time (MIN.)
, LH2164A-15: 260ns, LH2164A-20 : 330ns
4. Power supply: +5V±10%
5. Power consumption (MAX.) : 248mW(operation)
: 28mW(standby)
6. All inputs and outputs TTL compatible
7. Address and input data latch capabili~
8. Three-state output data controlled by CAS and
not latched at the end of cycle
9. Common 110 capability using the early-write
- mode
10. Read/modify/write, page-mode, RAS-only refresh, and hidden refresh capabilities
11. Built-in gated CAS function
12. Built-in biasing-voltage generator circuit for
high-output board
13. 2 ms refresh period, 128 cycle refresh,
14. 16-pin dual-in-line package
Top View
--------$HARP-.--------717
- NMOS 65536-:-BitDynamic Random Access Memory
•
LH2164A-15/LH2164A-20
Block Diagram
. = fij
"'
m
E""
-00
o "
"
"
""'"
>.
...
c
c "
E""
Cflp.
I
" 0
-"
o "
E
~<
00
"......
<
"'"
"
Decoder
"'
m
c
Cflp.
I
E
I
~<
Row
1=====~Row
AdtRCDlm,,). When tRCD< tRCDlm,,), tRAC becomes large by (tRco-tRCDlm,,)).
Note 9: When tRCD=tRCDlm,,).
Note 10: Load condition for 2TTL + 100pF.
Note 11: tRCDlm,,) is the largest value of tRCD that protects tRAqm,,) and is not an operation limit. If tRCD(m,,);;>tRCD,
the access time is controlled by tCAC.
Note 12: tRCD(min)=tRAHlmm)+2tT+tASqmm).
Note 13: The fall of CAS becomes the reference of tDS and tDH in the early write cycle and WE becomes the
reference in the read/write cycle and in the read/modify/write cycle.
Note 14: twcs, tCWD, and tRWD are not operation limits at the point the operation mode is prescribed. When twcs
;:;;;tWCSlmm), the early write cycle begins and the Dour pin becomes high impedance.
If tRwD;:;;;tRWD(mm) when tCWD;:;;;tCWD(mm), the read/write cycle begins and the output data becomes in·
formation of the selector cell.
In the case of timing other than that above, output becomes indeterminate.
Note 15: Operation is guaranteed when either tRCH or tRRH is satisfied.
Note
•
5:
(Vee=5V± 10%,f= IMHz, Ta=O- +70"C)
Capacitance
Parameter
Input capacitance
Input capacitance
Output capacitance
Symbol
CIN !
CIN2
COUT
Conditions
Ao -A 7 , DIN, WE
RAS, CAS
DOUT
MIN.
TYP.
MAX.
5
6
8
Unit
pF
pF
pF
~---'--------~~SHARP - - - - - - - - - - - - - - - - -
720
NMOS 65538-Bit Dynamic Random Access Memory
•
LH2164A-15/LH2164A-20
Timing Diagram
(1 ) Read cycle
tRC
tRAS
RAS
tRSH
tCAS
CAS
Ao-A?
WE
tRAC
DouT
(2)
High impedance
Write cycle (Early write)
tRC
tRAS
fE----tRCD~
\
\
tAR-
~~H
--X
-
tA!f
Row address
-
I--tCRP-tCAS
r-
V
J I---tCPN---1-
~
Column addres
rLtRP~ ~
tRSH
tCSH
K
B
X
-tWCR
I"twc~
'\14-
twp
~f-
X
~/
tCWL
tRWL
-tDH~
Valid data
K
tDHR
High impedance
DOUT
'-~---'-"'--SHARP----"---------
721
NMOS 65538-Bit Dynamic Random Access Memory
(3)
LH2164A-15/LH2164A-20
Read/write and read/modify/write cycl~s
tRWC
RAS
tRAS
-
tAR
-
fE--tRCD
t-tRP ....... ' - -
tCSH
~
tRSH
tCAS
V-
r-.. '
tf.!!
-..
~
t~~
~w Addre~Column address
t~
WE
J I--tcPs-l'-
~
K
I--tqVLtCWD
~t'RWL---OO
I
.i
tRWD
-tCAC
High impedance
DOUT
--twp-.,.j
nn
Valid data
~-\.-
tRAC
~~
~
#U
~~
X!
J(
Vahd data
(4)
RAS only refresh cycle
~--------------tRC--------------~
i------tRp·-----"'"
High impedance
DoUT
722
NMOS 65538-Bit Dynamic Random Access Memory
(5)
Hidden refresh cycle
(6)
Page mode read cycle
LH2164A-15/LH2164A-20
723
NMOS 65536-B.it Dynamic Random Access Memory·
(7)
LH2164A-15/LH2164A-20
Page mode write cycle
Ao-A7
DIN
•
Electrical Characteristics Curves
Access time vs. supply voltage
Access time vs. ambient temperature
1.3
1.3
".a...,
>
.::
".a.,.
Ta=25'e
.::
1.2
Qj
Qj
Il::
.,
1.1
~
I'-...
.,
u
"
!
.,
'E.,
.,.,
<""
1.2
-:;;
-:;;
u
Vcc=5V
>
1.0
0.9
4.0
1.1
!
'"
4.5
.,
:3
~
5.0
Supply voltage Vee
1.0
III
III
"
«""
r--
5.5
~
~
25
6.0
/
50
75
Ambient temperature Ta
(V)
Average supply current during normal
operation vs. supply voltage
100
('e)
Average supply current during normal
operation vs. ambient temperature
50
50
..
Ta=O'e
Vcc=5.5V
.S
bO
.S
...
...
40
..a
i<
... 8
.....
"
b ..a"
~
30
~
~ ~
.,bO-ll.
..
.,...> ...8
III
0
~
~
~
III
lO
C.
..
0
< "
4.5
30
0
20
10
4.0
40
8~
"
~.~
c. ..
..c._
.,...
.,bO.,...> 8...
< "
0
5.0
Supply voltage Vee
724
..a
ffi<
... 8
5.5
(V)
6.0
20
,
25
50
75
100
Ambient temperature Ta ('e)
LH2164A-15/LH2164A-20
NMOS 65536-Bit Dynamic Random Access Memory
Average supply current during standby
vs. ambient temperature
Average supply current during standby
vs. supply voltage
5~--------~~----,-----~
5
Ta=O·C
r--
Vee=5.5V
.;...
.g
4
".,....
---
~
- -
.e>~
3
8:<
'" 8
rn~
r---
~E 2
f:--g
~ ~
--
< '"
1
4.0
1~----L-----~----~
5.5
5.0
4.5
Supply voltage Vee (V)
o
6.0
Average supply current during RAS only
refresh vs. supply voltage
.~
.
..Iii.
"'<
-------
30
.g
....
~
20
" 8
.e>~
""
''"" '""
~
""..=
~~
os
.
I~..,
Vec=5.5V
.
"''""
".'"
30
.5
~
B< 20
.e>3
""§"~
.'" .
... ....
<
10
~"i1
<~~0
§
4.0
4.5
5.0
5.5
Supply voltage Vee CV)
°o~--~L-----~----~----~
6.0
Average supply current during page mode
vs. supply voltage
25
50
75
Ambient temperature Ta
..,
100
C·C)
Average supply current during page mode
ambient temperature
IVS.
40~----------,-----~----~
40
..,
Ta=O·C
.
.g
".'"
.5
Vee=5.5V
.5
30
'" <
...
,,~
-8:~
8
20
'"'" "
,,"8
. ..,"
: 8 10
<"
10
>-
o
.
.g
".."
100
(·C)
40~----------~----~----~
Ta=O·C
P:::
____~
Average supply current during RAS only
refresh vs. ambient temperature
40
CI)
<
25
50
75
Ambient temperature Ta
-
> os
""
o
4.0
---
-
4.5
'" <
...
30
<>~
~
5.0
Supply voltage Vee
~
-8:~
8
20
'"''"" ""'0"
." ..,'"
: 8 10
> ..
< ""
5.5
(V)
6.0
0
0
25
50
75
Ambient temperature Ta
100
(·C)
---.---------SHARP-~----------
725
NMOS 262144-Bit Dynaniic Random Access Memor:y
LH2464/LH2465
LH2464/LH2465
•
Description
•
I NEW I
NMOS 262144-Bit Dynamic
Random Access Memory
Pin Connections
The LH2464/LH2465 .are dynamic RAMs organized as 65,536-word-by-4-bit by using highperformance depletion load n-channel double-polycide silicon-gate MOS technology.
•
Features
1. 65,536-word by-4-bit organization
2. LH2464 : page-mode
LH2465 : nibble-mode
3. Access time (MAX.)
LH2464/5-10 : lOOns
LH2464/5-12: 12Dns
LH2464/5-15: 150ns
4. Single +5V power supply
5. Power consumption (MAX.) :
467.5mW (operation)
27.5mW (stand-by)
6. CAS-before-RAS refresh capabilities
7. Built-in refresh counter
8. 4ms refresh period, 256 cycle refresh
9. 18-.pin dual-in-line package
726
Top View
NMOS 262144-Bit Dynamic Random Access Memory
•
LH2464/LH2465
Block Diagram
Clock
} - - - ; Generator
No.1
A,
Column
Address
Buffer
A.
A5
A6
A7
Row
Address
Buffer
Clock
Generator 1----_-------3>-1
No.2
2
3
:><
~
~
Refresh
Address
Counter
"
t:::
;<
~
.,...
""...:""
-----{JIQ)
VKB
Mute
Output
VDD
Oscilation ~81)-~--t""--,
Output
Oscilation
Input
Tone
Output
'-!.F~-~--
XMTR
Switch
GND
--J>--__--(~ Single
L-===~_ _ _ _ _ _
~--~--a~~~H~------~6r-----------------------------~
GND
732
Tone
Inhibit
Tone Dialer CMOS LSI-
•
LR4087
Absolute Maximum Ratings
Parameter
Supply voltage
Operating temperature
Storage temperature
Maximum power consumption
I
Maximum pin voltage
Ratings
10.5
30-+60
-55-+150
500
-0.3
+0.3
Symbol
VDD
Toor
T st•
PD
VIN1
VIN2
Unit
V
t
t
mW
V
V
Note
1
2
3
4
Note1: Referenced to GND.
Note 2: Ta=25t
Note 3: The maximum applicable voltage on any pin with respect to GND.
Note 4: The maximum applicable voltage on any pin with respect to VDD.
•
Recommended Operating Conditions
Parameter
Supply voltage
•
Raiting
3.5-10.0
Unit
V
(Ta=-30-+60t)
Electrical Characteristics
Parameter
STI input voltage
COL input voltage
--
ROW input voltage
I
Output voltage
I
ROW TONE
COL TONE
TONE output resistance
XMTR output
no key input
XMTR output
in key input
MUTE output
no key input
MUTE output
in key input
current,
current,
current,
current,
Standby current
Operating current
Input resistance
Tone output (no key input)
Output rise time
Pre-emphasis
Tone output distortion
Note
Note
Note
Note
Note
Note
5:
6:
7:
8:
9:
10 :
Symbol
VIH1
V1L1
VIH2
V1L2
V1H3
V1L3
VOK
Voc
RLl
RL2
IoHx1
IoHx2
Conditions
RL =lk.o
VDD=3.5V
V DD =10.0V
V DD =3.5V, VOHx=2.5V
V DD =10.0V, VOHX=S.OV
IXLEAK
VDD =10.0V, VOUT=OV
lOLl
IOL2
lOB!
IOH2
ISB1
ISB2
IOP1
IOP2
RIN
VDD =3.5V, VOL =0.5V
VDD=lO.OV, VOL =0.5V
V DD =3.5V, VOH=3.0V
VDD=lO.OV, VOH=9.5V
VDD=3.5V
VDD=lO.OV
VDD=3.5V
VDD =10.0V
MIN.
0.7VDD
0.0
0.7VDD
0.0
0.9VDD
0.0
317
396
-15
-50
TYP.
400
500
620
330
-25
-100
0.1
0.5
1.0
0.5
1.0
2.0
4.0
2.0
4.0
0.25
0.5
1.0
5.0
20
tr
1.0
VDD~4.0V
Applies to STI pin.
Note 11
Applies COL input pin
Note 12
Applies ROW input pin
Note 13
Ta=25t
All output pins open
-Note 14
Applies to XMTR output pins Note 15
3.0
2.0
MAX.
V DD
0.3VDD
V DD
0.1 VDD
V DD
0.3VDD
504
630
10.0
Unit
V
V
V
V
V
V
mV rms
mV rms
.0
.0
rnA
rnA
pA
rnA
rnA
rnA
rnA
100
200
2.0
10.0
100
-SO
5.0
3.0
-20
pA
pA
rnA
rnA
k.o
dBm
ms
dB
dB
Note
5
6
7
S
10
10
11
11
9
9,13
5,S
12,13
14
15
: Applies to MUTE output pin.
: Rise time for tone output to reach 90% of maximum amplitude after key input.'
: Characteristics of crystal resonator used. Rs=100n, Lm=96mH, CM=0.02pF,
Ch=5pF, F=3.579545MHz
: Level ratio of high group tone to low group tone.
__
: Unnecessary frequency components against total power of basic tone signal of ROW
and COL .
.-.-----.--'~---SHARP-.....------ ......... - - -
733
..............-..-...............-,.._..- . - ..................--.-..--.-......
. LR4087
Tone Dialer. CMOS LSI
•
System Configuration
IN40004o
(4X)
H----rrImwi'DD
1!!H_---,1~'RllW§
a+-_....,1;;.t3 ROW3 TONE
OUT 16
l!m~I!lIIii+---,liiiZ RliWi
...
\1
LR4087
9 COU
L----isi-lCOL3
1200
' - - - - - ' i - l , COLZ
L-----:S;..!COLI
3.579545
MHz
7 OSC
'"
MgM""IO,-+----+--.
osc
8 OUT GND
-"
6
0.0051'F
-----------------~
""....,......l-1~r 00
2N6660
network
•
Test Circuit
v
COLI
COLz
COLs
COL.
I
1
4
7
*
2
5
8
0
3
A
B
6
C
9
#
D
f
~ 3.579545MHz
I
7
1
3
8
T
4
5
9
Tone Output
16
ROWI
ROWz
ROWs
--
ROW.
LR4087
14
RL
13
--.__~'-------;::~J..---.cJ
Output
Oscillation
Input 8
Bipolar
Input
Any Key
Down Output
1 OPamp
Output
Chip
Disable
' - - - - - - - - - - - - - - - ' - - - - U 6 Single
Tone
Inhibit
738
Tone Dialer CMOS LSI
•
LR4091
Absolute Maximum Ratings
Parameter
Supply voltage
Operating temperature
Storage temperature
Maximum power consumption
Maximum pin voltage
Symbol
Voo
T oDr
T st•
Po
VINl
VIN2
Ratings
10.2
-30-+60
-55-+150
500
-0.3
+0.3
Unit
V
t
t
mW
V
V
Note
1
2
3
4
Notel: Referenced to GND.
Note 2: Ta=20t
Note 3: The maximum applicable voltage on any pin with respect to GND.
Note 4: The maximum applicable voltage on any pin with respect to VDO,
•
Recommended Operating Conditions
Parameter
Supply voltage
•
Rating
3.0-10.0
Unit
V
(Ta=-30-+60t)
Electrical Characteristics
Parameter
Supply voltage
Symbol
In operating
In stand-by
COL input voltage
ROW input voltage
Input voltage
Input resistance
Tone output level
Pre-emphasis
(high-group tone signal)
Tone output distortion
Output rise time
Voo
Voo
VlHl
VILl
VIH2 '
VIL2
VIH3
VIL3
Rl
VOUT
IAKD OFF
\
5:
6:
7:
8:
9:
10:
11:
12:
Note
Note
Note
Note
13:
14:
15:
16:
Note 17:
1.0
2.0
Voo =3.4-10.0V
AKD output off current
Note
Note
Note
Note
Note
Note
Note
Note
MIN.
TYP.
3.0
2.0
0.7VDO
0.0
Voo-0.3
0.0
0.7VOD
0.0
20
-10.Q -8.5
tr
IAKD ON
In operation
In operation
In stand-by
Tone output (no key input)
OP amplifier output resistance
OP amplifier output current
Ta=25t
Voo =3.4-3.6V
No filter
AKD output source current
Supply current
Conditions
When tone signal is output
CD=O
lop
lop
ISB
VDD=3.5V
VAKO=3.0V
VDo =10.0V
VAKD=OV
VOD=3.5V
VDD =10.0V
VoD =10.0V
Unit
V
V
V
V
V
V
V
V
kO
dBm
Note
3.0
dB
10,17
-20
5
dB
ms
11,17
12
/LA
13
500
1.0
5.0
1.0
10
VDD=3.0V
MAX.
10.0
10.0
Voo
0.3
Voo
O.3Voo
Voo
0.3VDD
100
-7.0
250
10
/LA
2.0
rnA
rnA
/LA
dBm
kO
/-LA
200
-80
5
6
7
8
'8
9,17
14
15
16
16
Voltage to whIch AKD output responds by key mput.
Applies to COL input pins (COLI-4).
Applies to ROW inQ!!!.pins (ROWI-4).
Applies to CD and STI input pins.
Applies to low-group single tone signal.
,
Level ratio of high-group tone signal to low-group tone signal.
__
Unnecessary frequency component against basic tone signal total power (RMS) of ROWand COL.
Rise time for tone output reach 90% of maximum amplitude after key input.
Crystal reasonators used are as follows :
R5=1000, Lm=96mH ,CM=0_02pF, Ch=5pF, F=3.579545MHz
AKD output is P-channel open drain output.
Crystal resonator is used as indicated in Note 12 when single key is pressed (pin 6).
In stand-by, CD="O', STI="I"
'
OP amplifier output resistance is determined by capacity of pin l. The 10 kO shown in the test circuit is used in a standard
filter circuit. When the capacity of pin 1 is too large, it is necessary to reduce the resistance_
RL (Pin 18)=6200 : Voo=3.4-5V
3000 : Voo=7.5V or more
- - - - - - - - - - . - . . - "'-SHARP ~~.-....-.---------..-,
739
Tone Dialer CMOS
•
Lsi
LR4091
Test Circuit
2
. 18
VDD -,.;Power
-
supply
LR4091·
~
17
1
~
---
7
VBIAS=O.5V: VDD;;>4.0V
VBIAS=OV: VDD>4.0V
740
lOkO
Tone Dialer CMOS LSI
LR4092
LR4092
•
Tone Dialer CMOS LSI
•
Description
Pin Connections
The LR4092 is a monolithic LSI and uses an inexpensive crystal reference to provide eight audio
sinusoidal frequencies. Dual-Tone Multi-Frequency is obtained by mixing these frequencies .
.
•
Features
1. Internal regulation of tone amplitudes
2. Internal loop compensation and pre-emphasis
3. Tone frequencies within 0.65% for 12 standard frequencies
4. Uses inexpensive 3.579545MHz television colorburst crystal
5. Tone-disable capability
6. Mute output for electronic switching
7. Uses either 2-of-8 keyboard or single contact
keyboard
8. Single-tone capability
9. 16-pin dual-in-line package
•
Top View
Block Diagram
Row Input
,
Mute
~--~.Q) Output
9
Oscillation 8hr--t--,
Output
Tone
Output
Oscillation 7
Input
'---4---(2
Chip
Disable
Single
~-~----------------~--------(l~ Tone
Inhibit
.-------.-.---".-~SHARP'--------.-~-
741
Tone Dialer CMOS LSI
•
LR4092
Absolute Maximum Ratings
Parameter
Supply voltage
Operating temperature
Storage temperature
Maximum power consumption
Maximum pin voltage
Symbol
Voo
Topr
TSJiL
Po
VINl
VIN2
Ratings
'+10.5
0-+60
-35-+85
500
-0.3
+0.3
Unit
V
"C
"C
mW
V
V
Note
1
2
3
4
Notel: Referenced to GND.
Note 2: Ta=25't
Note 3: The maximum applicable voltage on any pin with respect to GND.
Note 4: The maximum applicable voltage on any pin with respect to VDO.
•
Parameter
Supply voltage
Tel Loop in Operation
Power Supply in Operation
Stand-by
CD, STI mput voltage
logic"'l "
logic "0"
COL input voltage
logic "1"
logic "0"
ROW Input voltage
logic "1"
logic "0"
Input resistance
ROW
COL
CD, STI
742
"
Electrical Characteristics
I Symbol I
Voo.
VODb
Vs
(Ta=O- +60"C)
Conditions
CD=GND
MIN.
TYP.
3.5
3.8
3.0
MAX.
Unit
10.0
10.0
10.0
V
V
V
V
V
V
V
V
V
RRI
ReI
Ta=25"C
Ta=25"C
Ta=25"C
20
15
15
60
125
kO
kO
kO
Tone Dialer CMOS LSI
•
LR4092.
System Configuration
7
3
4
c:::::J !3.579545 MHz .
5
18
9
1
2
3
A
4
5
6
7
8
9
C
0 #
D
*
B
LR4092
14
6
13
12
11
16
10
1800
RCVR
Type 2500
Speech network
~~~--~----------~RR
GNI------'
Bl------'
1N4004
(X4)
743
Ptdse:Dia/er CMOS LSI
.....~~.......-
LR40981 A
. .IIIIIIf!.~. . . .~~....,.-.-......-
LR40981A
.•
.....~.-
Pulse Dialer CMOS LSI
•
Description
Pin Connections
The LR40981A is a monolithic CMOS LSI which
uses a ceramic resonator and provides the features
required for a pulse dialer with redial.
o
•
Features
1. Direct telephone· line operation
2. Uses 2-of-7 matrix keyboard
3. CMOS process for low-power operation
4. 2.5 -6.0V power supply
5. Make/Break ratio pin-selectable
6. Ceramic resonator ·used as frequency reference
7. Redial with:lf or
8. MUTE output for electronic switching
9. 16-pin dual-in-line.package
*
•
Top View
Block Diagram
!
COlumn.{
Input
5
Pulse
Output
Memory
I!';,~ {fi34>----i'"
o
r-----~9r----o~------------------~
Oscillation Oscillation Make/Break Hook Switch/Test
Input
,Output
Ratio Select
.
7~4
Mute
Output
Pulse Dialer CMOS LSI
•
LR40981A
Absolute Maximum Ratings
Parameter
Supply voltage
Operating temperature
Storage temperature
Maximum power consumption
Maximum pin voltage
Symbol
Voo
Topr
T s,"
Po
VIN1
VIN2
Ratings
-0.3-+6.2
-30 +60
-55-+150
500
-0.3
+0.3
Unit
V
t
t
mW
V
V
Note
1
2
3
4
Notel: Referenced to GNO.
Note 2: Ta=25t:
Note 3: The maximum applicable voltage on any pin with respect to GNO.
Note 4: The maximum applicable voltage on any pin with respect to VDD.
•
Recommended Operating Conditions
Parameter
Supply voltage
•
Specified value
2.5 6.0
Unit
V
(Ta=-30-+60t)
Electrical Characteristics
Parameter
Key contact resistance
Key board capacity
Input voltage
Key pull-up resistance
Key pull-down resistance
MUTE sink current
Pulse output sink current
(V 00- VRFF) value
Memory hold current
Operating current
MUTE, PULSE
Output off current
Note
Note
Note
Note
5
6
7
8
Applies
Applies
Applies
Applies
Symbol
RKI
CK1
KIH
KIL
KIRU
KIRO
1M
Ip
VREF
IMR
lop
ILKG
Conditions
2-of-7 input mode
MIN.
0.8Voo
GND
Voo=6.0V, VouT=6.0V
MAX.
1
30
Voo
0. 2Voo
Note
150
Unit
kO
pF
V
V
kO
kO
pA
mA
V
pA
pA
1
pA
6,7
100
4
Voo=6.0V, VIN=4.8V
Voo-2.5V, VouT-0.5V
Voo =2.5V, VouT -0.5V
ISUPPLy-150pA
All outputs in no-load state
All outputs in no-load state
TYP.
500
1.0
1.5
2.5
0.7
100
0.001
3.5
5
5
6
7
8
to key input pins (ROW 1-4, COLI-3)
to MUTE output pin.
to PULSE output pin.
to VREF pin.
745
Pulse Dialer CMOS LSI
•
LR40981A
Timil'lg. Diagram
:t* or
*
Key input
--------------------
COL scan
ROW scan
ON -HOOK input
I--++------------i
Digit 2
MUTE output
Digit 4
~---..,
L--";;""'-f-'
PULSE output -i----'
sci ator
1---- . ON -HOOK mode
ON-HOOK/I
TEST mode
"I"
"I
r-'~----
0
Redial mode
(Normal dial)
•
Test Circuit
Power supply
+
16
1
2
3
KeYboard{
}K~"ro
10
9
67% break
61% break
746
OFFHOOK
15
LR40981A
6
7
8
15kO
eratJon
3OkO
~
Pulse Dialer CMOS LSI
•
LR40981A
System Configuration
R3
TIP
RING
Telephone line
Re
VDD
M/B
I
I
C1 15 ON-HOOK
I
I
+-..:::..:__--1>-!6~GND
2
VRE~ULSE
I
I
I
.------'3'-1COL 1
.------'4'-1COL,
5 COL,
I
I
I
I
I
_______________ JI
LR40981A
I
4
7
...
2
5
8
0
3
6
9
#
14
13
12
11
ROW,
ROW,
ROW,
ROW, MUTE~I~O_ _-I--t
OSC" OSCOL'T
A type keyboard 7
Speech network
8
C3
QI.Q3
Q2.Q.
Q5
DI.D2
C1
:
:
:
:
2N5550
2N5401
2N6661
IN914
:
C 2 .C 3
:
20,uF (low leakage product)
lOOpF±20%
RI : 2.7kO
R2 : 75kO
R3: 22MO
R.: 390kO
R5: IMO
Re : 1500
R7 : 100kO
747
Pulse Dialer CMOS LSI
LA40982
_ __
'-'_'-''-~''_'''_'''_IPi:-''~''_''''_'''-'-'~
LR40982
•
Pulse Dialer CMOS LSI
..•
Description
Pin Connections
The LR40982 is a monolithic CMOS LSI which
uses a ceramic resonator and provides the 'features
required for a pulse dialer with redial.
o
•
Features
1. Direct telephone-line operation
2.
3.
4.
5.
6.
7.
8.
9.
Uses 2-of-7 matrix keyboard
CMOS process for low-power operation
2.5-6.0V power supply'
Make/Break ratio pin-selectable
Ceramic resonator used as frequency reference
Redial with :1:1: or
MUTE output for electronic switching
16-pin dual-in-line package
•
*
Top View
Block Diagram
!
COlumn{
Input
5
Memory
I~ {u.
3
Mute
Output
_---.
Oscillation Oscillation Make/Break Hook Switch/Test
Input
Output - Ratio Select
748.
Pulse
Output
LR40982
Pulse Dialer CMOS LSI
Absolute Maximum Ratings
•
Parameter
Supply voltage
Operating temperature
Storage temperature
Maximum power consumption
Maximum pin voltage
Notel:
Note 2:
Note 3:
Note 4:
•
Symbol
VDD
Toor
T st•
PD
VIN )
VlN2
Ratings
-0.3-+6.2
-30-+60
-SS-+lS0
SOO
-0.3
+0.3
Unit
V
Note
1
·C
"C
mW
V
V
2
3
4
Referenced to GND.
Ta=25t:.
The maximum applicable voltage on any pin with respect to GND.
The maximum applicable voltage on any pin with respect to VDO.
Recommended Operating Conditions
Parameter
Supply voltage
•
Specified value
2.5-6.0
Unit
V
(Ta=-30-+60"C)
Electrical Characteristics
Parameter
Key contact resistance
Key board capacity
Input voltage
Key pull-up registance
Key pull-down resistance
MUTE sink current
Pulse output sink cllrrent
(VDD-VRFF) value
Memory hold current
Operating current
MUTE, PULSE
Output off current
Note
Note
Note
Note
5
6
7
8
Applies
Applies
Applies
Applies
Symbol
RKI
CKI
KlH
KIL
KIRU
KIRD
1M
Ip
VREF
IMR
lop
ILKG
Conditions
2-of-7 input mode
MIN.
0.8VDD
GND
VDD=6.0V, VOUT=6.0V
MAX.
1
30
V DD
0.2VDD
100
4
VDD=6.0V, VIN=4.8V
VDD=2.SV, VOUT=O.SV
VDD=2.5V, VOUT=O.SV
IsuPPLY= 150 pA
All outputs in no-load state
TYP.
500
1.0
1.S
2.5
0.7
100
0.001
Unit
kO
pF
V
V
kO
kO
Note
pA
6
7
8
3.S
rnA
V
ISO
pA
pA
1
pA
S
S
6,7
to key input pins (RDW 1-4. COLl-3).
to MUTE output pin.
to PULSE output pin.
to VREF pin.
-.-----~---SHARP-.---.-----
749
Pulse Dialer CMOS LSI
.........r.-__...____
J
LR40982
........................,.........................
.....,
~
•
Timing Diagram
# or
*
Key input
--------'------------ JUUu-
COL scan
ROW scan,
ON -HOOK input
MUTE
output .-...1-....L.j
Digit 4
L......,;=---~
PULSE output--1I---,
SCI
I----OFF-HOOK mode
(Normal dial)
•
ON-HOOK/I
TEST mode
"""
.,
j-o.>------
ator ope,ratIon
Redial mode
Test Circuit
Power supply
+
16 15kll
15
.10
9 67% break
61% break
750
OFFHOOK
30kll
LR40982
Pulse Dialer CMOS LSI
•
System Configuration
TIP
RING
Telephone line
Rs
VDn
15 ON-HOOK
Q 6 GND
I 2
PULSE
,
~-----l~"":3'-1v REF
, - - - - ' - 1 COL,
4 COL,
r _ _-=-t
5 COL,
1 2
LR40982
14 ROW,
4 5 6
7 8 9
13 ROW,
12 ROW,
* 0 II 11 ROW4MUT"1-<~-+I
OSC'NOSCOUT
A type keyboard 7
8
1
1
1
-I
I
I
I
I
I
I
I
____________________ J I
Type 500 Speech network
QI.Q3. Q.=2N5550
Qs,Q6=2N5401
Q2=2N3822
D1 =lN914
C1 =20,uF(Iow leakage product)
C2.C3=100pF±20%
RI=8kO
R2=500kO
R3=22MO
R •• Rs=390kO
R6,R g =100kO
R7. RS=3kO
751
Pulse; Dialer CMOS LSI
LR40991
LR40991
Pulse Dialer CMOS LSI
•
Description
The LR40991 is a monolithic CMOS LSI which
uses a CR oscillator and provides the features required for a pulse dialer with redial.
•
PinConnec,ions
o
•
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Features
Direct telephone-line operation
Uses 2-of-7 matrix keyboard
CMOS process for low-power operation
2.5-6.0V power supply
Make/Break ratio pin-selectable
20/10 pps pin-selectable
Redial with :1:1: or
MUTE output for electronic switching
CR oscillator
IS-pin dual-in-line package
•
*
T~p View
Block Diagram
Pulse
Output
2 Mute
Output
L--r~~~J'<--------~o 20110
pps
Select
Make/Break
Ratio Select
Hook Switch/Test
~'-'~--~'---SHARP--'-"--'-'----
752
Pulse Dialer CMOS LSI
•
LR40991
Absolute Maximum Ratings
Parameter
Supply voltage
Operating temperature
Storage temperature
Maximum power consumption
Maximum pin voltage
Symbol
VDD
T oDr
T stg
PD
VIN!
V1N2
Ratings
-0.3-+6.2
-30-+60
-55-+150
500
-0.3
+0.3
Unit
V
t
t
mW
V
V
Note
1
2
3
4
Notel: Referenced to GND.
Note 2: Ta=25"'C.
Note 3: The maximum applicable voltage on any pin with respect to GND.
Note 4: The maximum applicable voltage on any pin with respect to VDO.
•
Recommended Operating Conditions
Parameter
Supply voltage
•
Rating
2.5-6.0
Unit
v
(Ta=-30-+60t)
Electrical Characteristics
Parameter
Key contact resistance
Key board capacity
Input voltage
MUTE sink current
MUTE source current
PULSE sink current
V REF output value
Memory hold current
Operating current
Key pull-up resistance
Key pull-down resistance
ON-HOOK pull-up resistance
MUTE, PULSE
output off current
Note
Note
Note
Note
5
6
7
8
Applies
Applies
Applies
Applies
Symbol
RKI
CK1
KIH
KIL
IML
IMH
Ip
VREF
IMR
lop
K1RU
KIRD
ROH
ILKG
Conditions
2-of-7 input mode
VDD =2.5V, VouT =0.5V
VDD =2.5V, VouT=2.0V
V DD =2.5V, VouT =0.5V
ISUPPLY= 150 /L A
All outputs in no-load state
All outputs in no-load state
VDD=6.0V
VIN=4.8V
VDD =6.0V, VouT=6.0V
MIN.
0.8VDD
GND
0.5
0.5
1.0
1.5
TYP.
MAX.
1
30
V DD
0.2VDD
3.5
Unit
kO
pF
V
V
rnA
rnA
rnA
V
150
/LA
2.0
2.0
2.5
0.7
100
100
4
100
0.001
Note
5
6
7
8
/LA
kO
kO
kO
1
/LA
to key input pins (ROWI-4, COLI-3).
to MUTE output pin.
to PULSE output pin.
to VREF pin.
----------SHARP----------------753
Pulse Dialer CMOS LSI
•
LR40991
Timing Diagram
Digit 1
Digit 2
# or *
-----.Ur----.L.Jr---------,Ur----------
Key input
COL scan
ROW
~----~~O!l~--- ~ -----------
m.r-
scan~: ____ ~~0!l~___ lJ1JLJl.Jl----------- ~
I
I
I
I
.
,
!
:"
~ I
MUTE output --'j
i
i
~
r),l'
ON -HOOK in;;-l
: :
PULSE output
I i
I
:l
:
I
I
t i l
I
III
I
!!
:
'
Oscillator stop
,
oscillatorl : : :1l1lrTT1I1n
------010: ..4kHz
-------"1'
.. .,.- ' Ii II
- - - - - - - - - - - - ____ rnr,JU
I
I
I I
tDB
I
I
::
tB
tlDP
I I I
~II
!!II.
I
I
:
I I
:
I
:
I ItMOI
I I
:
I
I
:
.I
'E:~I
Normal dial liP,
I
I"
·1·
I I I
I I
tpDP
/----'-'-"'"----1:11
ON -HOOK mode
:
I
CR2 output
r-
L.IU':
..
I!II~
I
.
•
OFF -HOOK mode
i
_.
i
Redial mode
OFF -HOOK mode
TEST
mode
~~---------------~~~--
\
•
Test Circuit
Power supply
+
1MO
1
KeYboard{
2
17
3
~: }
4
5
6
LR40991
~
OFF
-HOOK
IMO
Keyboard
1L12
60% break
66'% break .
20pps
IOppso--~
--.-------------SHARP - - - - - - - - - - - - -
754
Pulse Dialer CMOS LSI
•
LR40991
System Configuration
Telephone line
R6
Speech
network
R2
VDD
17 ONt--+---"-:-tHOOK
6 GND
2
12
MU TEI--~---+
~----~~~--~3~VREF
~_ _-,-/4 ~~~l LR4099I
.-____5, COL: PULSE~I~8~-----1-+----~
[t[t[tr--~I6~ROWI
15 ROW
7 R5
CRI 8 C2
1-4~~~-~I4d1 ____2
~OW
t*7hlj8rn9tl===:II3~
0 ;l:
ROW 4
C R2 t-9--1t;;RC-B4'
3
I
CR3I-'-..JIf'V\r~
I
M/B 20/10
I
11
I
I
10
I
I
I
IL
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ...1J
Rl=2.7kO
R2 =75kO
R3=22MO
R4=390kO
R5=2MO
R6=I500
R, =IOOkO
RB=220kO
Ql=2N5550
Q2=2N540I
Q3=2N5550
Q4=2N5550
Q5=2N2222
Q6=2N2303
C 1 =22,uF
C2=390pF
C 3 =IO,uF
D1 =IN9I4
D2=IN9I4
D3=IN4004
Relay: 1.5V bistable latching
9
------------------SHARP - - - - - - - - - - - - - -
755
, '\LR40992
Pulse Dialer CMOS LSI
,
LR40992
Pulse Dialer CMOS LSI
•
Description
The LR40992 is a monolithic CMOS LSI which
uses a CR oscillator and provides the features required for a pulse dialer with redial.
•
Pin Connections
o
•
Features
1. Direct telephone-line operation
2. Uses 2-of-7 matrix keyboard
3. CMOS process for low-power operation
4. 2.5-6.0V power supply
5. Make/Break ratio pin -selectable
6.,20/10 pps pin-selectable
7. Redial with :1* or
8. MUTE output for electronic switching
9. CR oscillator
10. 18-pin dual-in-line package
*
•
Top View
Block Diagram
!
Column {
Input
5
Row """
Pulse
Output
{11'46t--~
Mute
Output
L~=:::.!:....,.....r---------1Qg 20/10 pps
Select
Make/Break
Ratio Select
756
Hook Switch/Test
LR40992
Pulse Dialer CMOS LSI
Absolute Maximum Ratings
•
Parameter
Supply voltage
Operating temperature
Storage temperature
Maximum power consumption
Symbol
Voo
Topr
Tst2
Po
VIN1
V1N2
Maximum pin voltage
Note
Note
Note
Note
•
Ratings
-0.3-+6.2
-30-+60
-55-+150
500
-0.3
+0.3
Unit
V
'C
'C
mW
V
V
Note
1
2
3
4
1: Referenced to GND.
2: Ta=25t:.
3: The maximum applicable voltage on any pin with respect to GND.
4: The maximum applicable voltage on any pin with respect to VDD'
Recommended Operating Conditions
Parameter
Supply voltage
•
Specified value
2.5-6.0
Unit
V
(Ta=-30-+60'C)
Electrical Characteristics
Parameter
Key contact resistance
Key board capacity
Input voltage
Key pull-up resistance
Key pull-down resistance
MUTE sink current
Pulse output sink current
V REF output current
Memory hold current
Operating current
MUTE, PULSE
Output off current
Note
Note
Note
Note
5
6
7
8
Applies
Applies
Applies
Applies
to
~ut
Symbol
RKI
CK1
KJH
KIL
K1RU
K1RO
1M
Ip
Conditions
2-of-7 input mode
MIN.
0.8Voo
GND
IREF
IMR
lop
VOO,VREF=6.0V
All outputs in no-load state
All outputs in no-load state
ILKG
Voo=6.0V, VouT=6.0V
MAX.
1
30
Voo
0. 2Voo
Note
150
Unit
kO
pF
V
V
kO
kO
pA
rnA
rnA
pA
pA
1
pA
6,7
100
4
Voo=6.0V, VIN=4.8V
Voo=2.5V, VouT =0.5V
TYP.
500
1.0
1.0
7.0
0.7
' 100
0.001
5
5
6
,7
8
pins (RDW'-4, COL'-3)
to MUTE output pin.
to PULSE output pin.
to VOEF pin.
~--""'-'-'--~-SHARP-~------
757
Pulse Dialer CMOS LSI
•
LR40992
Timing Diagram
*
Digit 1
Digit 2
# or
Key input ~--""LJr-----'LJr--------""'LJ""---------COL scan
---uuuuuL___ ~~O~~
__
ROW scan
KnJlJ1Jlf
:
____
JUL...fIJlf ----------- ~
500Hz
----------~
ON-HOOKin~
: I:
--
i
MUTE output
:
---
PULSE output
I,
1
:
: :
I
I
I
i I
:
:I
CR2 output
,)l
:
I,
:
~~
r------f
U
: : 4kHz oscillato~:
:
tDB
I :
t8
II
tpop
,
•
.1.
r;
I
:
i
!
I
I
:
r-I
I
I
I
i :Oscillator stop
:
tmp
I I:
~
·1 ,
i Normal dial
liP,
I I
I
I
lI
I
I
.1':
I
I
tMol
~:,
OFF-HOOK mode
I
I
'
_.
Redial mode
OFF-HOOK mode
Test Circuit
Power supply
+
IMO
KeYboard{
2
17
3
16
4
15
5
6
LR40992
14
OFF
-HOOK
IMO
}KO,OOUd
13
12
60% break
66% break
20pps
10pps
758
~
-----+--------'"1~~n~II-;-ilnn
I I
I I I J44
: I U~L-----------------:.ru-I
I---------i,.
ON-HOOKmode
------------
TEST mode
LR40992
Pulse Dialer CMOS LSI
•
System Configuration
TIP
RING
2
6
3
V REF
GND MUTE
COL,
12
- - - 18
COL, PULSE
COL,
lR40992
ROW,
4
7
6
9
jj:
15
ROW,
14
ROW,
13
Rs
17 ON-
R6
ROW,
HOOK
20/10
10
RI =560kn
R2 = 1.4kn
R3 =470kn
R. =330kn
Rs = 2Mn
R6 =220kn
R7 =lOOkn
Rs = 3kn
R9 = 3kn
R IO =100kn
Rll = 10Mn
QI=2N5401
Q2=2N5550
Q3=2N5550
Q.=2N5401
Qs=2N5401
C I =68,uF
DI =IN4004
D2=lN4004
D3=IN4004
D.=IN4004
Ds=IN914
D6=lN914
D7=IN4004
C 2=390pF
ZI=120voit,
lwatt Zener
759
Pulse Dialer.CMOS LSI
LR40993
•
LR40993
Pulse Dialer CMOS LSI
•
Description
Pin Connections
The LR40993 is a monolithic CMOS LSI which
uses a CR oscillator and provides the features required for a pulse dialer with redial.
o
•
Features
1. Direct telephone-line operation
2. Uses 2-of-7 matrix keyboard
3. CMOS process for low-power operation
4. 2.5-6.0V power supply
5. Make/Break ratio pin-selectable
6.20110 pps pin-selectable
7. Redial with :j:j: or
8. MUTE output for electronic switching
9. CR oscillator
10. Beep-tone output for key input
11. 18-pin dual-in-line package
12
MUTE
*
•
Top View
Block Diagram
'"0
;
...
'"
~ I-----~
o~
~ ~ I-----~L______~______~~--;_~
'"
~
:.=:..:;
'"
"o
U
"
Pulse
8 Output
Tone
Output
Mute
Output
20/10 pps
Select
) - - - - - { l)----{J171}-........,----------.....J
Make/Break Hook SJitch/Test
Ratio Select
I
~-----------SHARP-----.---___:_
760
Pulse Dialer CMOS LSI
•
LR40993
Absolute Maximum Ratings
Parameter
Supply voltage
Operating temperature
Storage temperature
Maximum power consumption
Maximum pin voltage
Symbol
VDD
Topr
Tst~
PD
VINl
VIN2
,
Ratings
-0.3-+6.2
-30-+60
-55-+150
500
-0.3
+0.3
Unit
V
t
t
mW
V
V
Note
1
2
3
4
Notel: Referenced to GND.
Note 2: Ta=25'C.
Note 3: The maximum applicable voltage on any pin with respect to GND.
Note 4: The maximum applicable voltage on any pin with respect to VDO.
•
Recommended Operating Conditions
Parameter
Supply voltage
•
Specified value
2.5-6.0
Unit
V
(Ta=-30-+60t)
Electrical Characteristics
Parameter
Key contact resistance
Key board capacity
Input voltage
Key pull-up resistance
Key pull-down resistance
MUTE sink current
Pulse output sink current
TONE output sink current
TONE output source current
Memory hold current
Operating current
MUTE, PULSE
Output off current
Note
'Note
Note
Note
5
6
7
8
Applies
Applies
Applies
Applies
to
to
to
to
Symbol
RKI
CKI
KIH
KIL
KIRU
KIRD
1M
Ip
ITL
ITH
IMR
lop
ILKG
Conditions
2-of-7 input mode
MIN.
0.8VDD
GND
VDD =6.0V, VouT=6.0V
key input pins (ROW(-4, COL I MUTE output pin.
PULSE output pin.
TONE pin.
MAX.
1
30
VDD
0.2VDD
100
4
VDD =6.0V, VIN=4.8V
V DD =2.5V, VouT =0.5V
V DD =2.5V, VouT=0.5V
V DD =2.5V, V ouT =0.5V
V DD =2.5V, VOUT=VDD-0.5
All outputs in no-load state
All outputs in no-load state
TYP.
500
1.0
250
250
Unit
kO
pF
V
V
kO
kO
Note
pA
6
7
8
8
rnA
0.7
100
0.001
150
pA
pA
pA
pA
1
pA
5
5
6,7
3)
-'-~--'---SHARP~-'--'-'-----~
761
_
..........................._-,._.. ..........................................
Pulse Djaler CMOS LSI
•
LR40993
Timing Diagram
Digit 2
"* or *
r --------Ur----.Ur--------....U
Digit 1
Key inPlJt - - -....
-
COL scan
- - -. - ,UnUnUnUnUnl.""---------500Hz
~------------=unu______
: .
.
_____________~
R-O-W scan ~----52~f!z--- ~
ON -HOOK input
'
---1
~",,_-+i!~
+1---------------IJJ.l'--------------ir-
MuTE output
-
PULSE output
I
~l
1
:
I
:I
:!
: :
--';---;I-;I---lJf-----, ~
_ _';-_-1
1
ii
:
1
I..
I
I
:
1
tB
i
: : :
::
:
I I tMO.
I.~ I
~
-I
dial l/Pr
I
•
_____
MM~
____
I
':
-_*1.1\. .
~~
_________
Redial mode
MM~
+
\
Keyboard
18
-----L
17
{~
---.!..
.~
LR40993
OFF
-HOOK
/
:: }
~
_1_4__ Keyboard
6
13
7
J2
I390 p;'
8
11
/220kO
9
- 10
2MO
1MO
60% brea~
I
/
66% break
0---
20pps
-
lOpps
762 '
:
I
I
:
I
I
1
I
.od. :1
Power supply
~
.
i
.
_____________
OFF HOOK
Test Circuit
-
I
I
I
1
r
I
I
ON -HOOK _m_od_e.-IIf.._ _ _ _O_F_F_-_H_O_O_K_m_Od_e_ _ _ _
Tone output
.,
-------.,..--------+.nr--
..
tDS
'
tpDP 1 I
tIDP
1-------'-'-'-t~I.
I I Normal
1
:
. 1.
I I
I I I
: Oscillator stop
4kHz 1 1 Oscillator 1 1 I nn;----'-----'nn
-------:-~--------:-:4-.Jl!U
UJ.lL
I I
: :
CR2 output
I.
U
I
i I
TEST .odo
Pulse Dialer CMOS LSI
•
LR40993
System Co~figuratiori
RING Telephone line
TIP
Z2
1
2
4 5 6
7 8 9
0 #
*
VDD
11
M/B
2
TONE
12
6
GNDMUTE
3
COLI
13
4 COL2
5 ---'pULSE
COL3
LR40993
16
ROW 1
15 ROW2
R5
14
CR 1
ROW3
13 ROW. CR2
D7
N-,
I
I
I
I
I
I
1
CR 3
17 ONHOOK 10/20
I
I
R6
I
I
10
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ..J
Speech network
Rl =560kO
R2 = l.4kCl
R 3=470kO
R.=330kO
R5= 2MO
Rs=220kO
R 7·=100kO
Rs= 3kO
R9= 3kO
R IO =100kO
Rl1 =10MO
QI =2N5401
Q2=2N5550
Q3=2N5550
Q.=2N5401
Q5=2N5401
C 1 =68.u F
DI =IN4004
C 2=390pF
D2=IN4004
D3=IN4004
ZI. Z2=120V : 1watt
Zener Diode
D.=1N4004
D5=IN914
Ds=IN914
D7=IN4004
Ds = Zener Diode
'-'---'~------SHARP ~.-.-.-.------
763
'LR40994
Pulse Dialer CMOS LSI
LR40994
Pulse Dialer CMOS LSI
•
Description
The LR40994 is a monolithic CMOS LSI which
uses a CR oscillator and provides the features required for a pulse dialer with rediaL
•
Pin Connectio'ns
o
•
Features
L Uses'2-of-7 matrix keyboard
2. CMOS process for low-power operation
3. 2.5-6.0V power supply
4. Make/Break ratio pin-selectable
5. 20110 pps pin-selectable
6. Redial with # or
7. MUTE output for electronic switching
8. CR oscillator
9. Beep-tone output for key input
10. 18-:pin dual-in-line package
)
*
•
Top View
Block Diagram
!
Column {
Input "'5",----.
Row {
Input
Pulse
8 Output
I;
1
U3}--+j
Tone Output 2
L.,.-=:.:.:::::....,......Jt----------~
Mute
Output
20/10pps
Select
Make/Break Hook Switch/Test
Ratio Select
~------- ........ --SHARP--.--,-.-.-----~
764
Pulse Dialer CMOS LSI
LR40994
Absolute Maximum Ratings
•
Parameter
Supply voltage
Operating temperature
Storage temperature
Maximum power consumption
Maximum pin voltage
Note
Note
Note
Note
•
1:
2:
3:
4:
Symbol
VDD
Topr
T st•
Po
VIN1
VIN2
Ratings
-0.3-+6.2
-30-+60
-55-+150
500
-0.3
+0.3
Unit
V
Note
1
·C
"C
mW .-t----2
V
3
V
4
Referenced to GND.
Ta=25"C
The maximum applicable voltage on any pin with respect to GND.
The maximum applicable voltage on any pin with respect to V DO,
(Ta= -30- +60"C)
Electrical Characteristics
Parameter
Supply voltage
Key contact resistance
Key board capacity
Input voltage
Key pull-up resistance
Key pull-down resistance
MUTE sink current
PULSE output sink current
TONE output sink current
TONE output source current
Memory hold current
Operating current
MUTE, PULSE
Output off current
Note
Note
Note
Note
5:
6:
7:
8:
Applies
Applies
Applies
Applies
Symbol
VDD
RKI
CK1
KIH
KIL
KIRU
KIRD
1M
Ip
Conditions
2-of-7 input mode
IMR
lop
ILKG
VDD =6.0V, VOlrt=6.0V
ITL
to ~ut pins (ROW I to MUTE ou'tput pin.
to PULSE output pin.
to TONE pin .
4,
COL , -
TYP.
0.8VDD
GND
MAX.
6.0
1
30
V DD
0.2VDD
100
4
V oD =6.0V, VJN=4.8V
VDo =2.5V, VouT=0.5V
V Do =2.5V, VouT=0.5V
V DD =2.5V, VouT=0.5V
VDD =2.5V, VOUT=VDD-0.5V
All outputs in no-load state
All outputs in no-load state
IrH
MIN.
2.5
500
1.0
250
250
0.7
100
0.001
150
1
Unit
V
kD
pF
V
V
kD
kD
pA
mA
pA
pA
pA
pA
Note
pA
6,7
5
5
6
7
8
8
3)
.-..-------$HARP---------
765
LR40994
Pulse Dialer CMOS LSI
•
Timing Diagram
Digit 1
Key input
COL scan
ROW
--utI1Jl.AA___ ~~ Switch
18
Tone Output
17
Pulse Output
11
Mute Output
Mode Select
Col_ """ { ,
Test
Column Input
Oscillation Input
8
Oscillation Output
9
Von
•
GND
Pin Description
Key input
I
Ground
Test input
Oscillator
connection
I
I
MODE
Mode select
I
MUTE
Mute 'output
0
HKS
PULSE OUT
TONE OUT
774
Symbol
Power supply
110
Signal Name
V DD
COL 1 -COL 4
ROW 1 -ROW 4
GND
TEST
OSCIN
OSC OUT
0
Hook switch input
I
Pulse output
Tone output
0
0
Function
COL 4-string key input
ROW 4-string key input
Negative power supply pin.
Pin used for LSI testing
Connect crystal for color burst
Pin connection
V DD
Open
GND
Operating mode
20-pps pulse dialer
lO-pps dialer
DTMF tone dialer
Sending of MUTE signal
Pin connection
V DD
Open
GND
Operating mode
On-hook mode
On-hook mode
Off-hook mode
Sending lOOpps or 20pps pulse signal.
Sending of DTMF tone signal.
Pulse/Tone Dialer CMOS LSI
•
LR4802
(Ta=25"C).
AC Characteristics
Symbol
Parameter
Oscillation start time
Key debounce time
tDB
Pulse rate
PR
Break time
tB
MIN.
TYP.
4
10
20
68
Interdigital pause time
t IDP
1000
Mute overlap time
t MOL
Predigital pause time
t pDP
Tone output rate
tOR
2
40
220
Note 9:
Note
Note
Note
Note
Note
•
10:
11:
12:
13:
14:
MAX.
8
32
tos
Unit
Note
ms
9
10
ms
pps
ms
ms
4
r-1L
12
13
13
14
ms
ms
13
ms
When crystal oscillation element with characteristics Rs= 1000, Lm=96mH,
Cm=0.02pF, Ch=5pF, f=3.579545 MHz is used.
Key input is accepted after oscillation begins if valid after tOB.'
Opens the MODE pin.
Connect the MODE pin to VDO.
During 10·pps pulse mode (112 during 20·pps mode).
100 ms during DTMF mode.
Timing Diagram
(1)
Pulse mode
Key input
m
input
[IJ inpu;..:.t_ _ _ _ _ _ _ _ _ _~I~R-=E=D_=;I~A=L:.I-in...:p-u-t_ _ _ _ _ _ _ _ _ __
~
LJ
COL scan
ROW scan
------~ - - - - - - - - - - - - -
HKS input
MUTE input
PULSE input
Oscillator operation
OSCIN
(2)
DTMF mode
MUTE output
TONE output
~~:RSJ
Normal dialing mode
Automatic dialing mode
---......-.-------SHARP------------776
LR4802
Pulse/Tone Dialer CMOS LSI
•
System Configuration (tone mode connection example)
7
-
VOl)
~~~---+--~6~GND
TEST
RK B
----- 17
PULSE 1-1'-;'-1-<"'-
12
'----"VVIr----l HK S
R
Type 2500
GN
Speech network
C
R'3 3 _
4~
r - - - - " -5t C2
2 C3
LR4802
C
16
1 2
4 5
7 8 9 ST
*
0 #RE
Keyboard
15
14
13
GD
•
MUTE~I~I~-+--~-+----~t--r-~
S
R,
R2
10 P
R3
MODE
R.
OSC
OSCn, OUT
P T
8
9
Ql
3.579545 MHz
Connect to p' for pulse mode
Connect to T for tone mode
Z, =lODK820
Rl =2201W
R2 =560kO
R3 =1.5kO
R. =1500
R5 =270kO
R6 =510
R7 =5kO
Rs = 1000
R9 =2000
RlO= 100kO
Rll=IMO
R12=lOkO
R13=4700
Q,=2N6660
Q2=2N5401
Q3=2N5550
Q.=2N5550
Q5=2N5550
Q6=2N5550
Sl, S2, S3 = Hook switch
DI-D.=IN4004
D5=IN270
DF IN752 (5.6V)
D7=IN914
Ds=IN914
*1 R14=390
* 2C, =68!, F (Must be input to smooth the power supply and
prevent latch up.)
.-----~-----SHARP-.----~--...-
777
Pulse/Tone Dialer CMOS LSI
LR4803
•
LR4803
Pulse / Tone Diqler CMOS LSI
•
Description
Pin Connections
The LR4803 is a CMOS LSI for the repertory dialer switchable between tone and pulse dialing
(make/break ratio: 40%/60%) with ten 18-digit
number memory storage.
o
TONE OUT
PULSE OUT
ROW!
ROW2
•
Features
ROW3
1. Switchable between DTMF tone dialing and
pulse dialing modes
2. Stores ten 18-digit telephone number memory
including a redial memory
3. PABX pause storage
4. Uses the single contact, the standard 2 of 7 or
2 of 8 matrix keyboard
5. Make/Break ratio: 40%/60%
6. Switch able between 10 pps and 20 pps in
pulse dialing mode
7. A 3.579545MHz color burst crystal can be
used for the clock oscillator
8. 18-pin dual-in-line package
778
)
ROW.
HKS
MUTE
MODE
Top View
LR4803
Pulse/Tone Dialer CMOS LSI
•
Block Diagram
Hook Switch
18
Tone Output
17
Pulse Output
11
Mute Output
Mode Select
Col~o j,... { ,
-.," '..""
Test
til
Col umn Input
.~
Po.....:I
~. j,~. j
Oscillation Input
8
Oscillation Output
9
VDD
•
Pin Description
Signal Name
Voo
COL I -COL 4
ROW I -ROW 4
GND
TEST
OSCIN
OSCOUT
Symbol
Power supply
I/O
Key input
I
Ground
Test input
Oscillator
connection
I
I
0
Function
COL 4·string key input
ROW 4-string key input
Negative power supply pin.
Pin used for LSI testing
Connect crystal for color burst
Pin connection
MODE
Mode select
I
MUTE
Mute output
0
Voo
Open
GND
Sending of MUTE signal
Pin connection
HKS
PULSE OUT
TONE OUT
Hook switch inJlut
I
Pulse output
Tone output
0
0
Operating mode
20·pps pulse dialer
lO·pps pulse dialer
DTMF tone dialer
Voo
Open
GND
Operati\lg mode
On·hook mode
On·hook mode
Off· hook mode
Sending of lOOpps or 20pps pulse signal
Sending of DTMF tone signal.
- - - - - - - - - - S H A R P - - - - - . - ........ _ - - - -
779
Pulse/Tone Dialer CMOS LSI
•
LR4803
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Power consumption
Operating temperature
Storage temperature
Symbol
VDD
VIN
' PD
Toor
Toor'
Ratings
10.5
-0.3-VDD +0.3
500
-30-+60
-55-+150
Unit
V
V
mW
"C
"C
Note
1
2
3
Note1: Referenced to GND.
Note 2: The maximum -applicable voltage on any pin with respect to GND.
Note 3: Ta=25t
•
Recommended Operating Conditions
Unit
Parameter
Supply voltage
•
(Ta=25"C)
DC Characteristics
Parameter
Input voltage
l
Tone output
ROW
voltage
I COLUMN
Standby current
Operating current
Mute output current
Pulse sync output current
Pulse leakage output current
Key pull-up input resistance
Key pull-down input resistance
Mode pull-up input resistance
Mode pull-down input
resistance
HKS pull-up input resistance
Tone output distortion
Pre-emphasis
Note
Note
Note
Note
Note
4:
5:
6:
7:
8:
Symbol
V1L
VIH
VOR
Voc
ISB
lop
Io'L
IpL
I ILKG I
RKP
RKD
RMP
Conditions
RL=lkO
RL=lkO
VDD=3.5V
VDD=3.5V
VDD =2V, VoL =0.5V
V DD =2V, Vo=0.5V
V DD =6V, Vo=6V
V Do =3.5V
Voo=3.5V
VDo=3.5V
RMD
VDD=3.5V
R~K
Voo=3.5V
V Do ;;;;;4V, RL=lkO
V Do ;;;;;4V, RL=lkO
PE HB
MIN.
GND
0.8VDD
290
380
1
1
TYP.
350
450
3
2
2
MAX.
0.2VDD
V DD ,
450
550
6
3
100
5
100
rnA
rnA
rnA
pA
kO
kO
kO
100
kO
1
60
1
Unit
V
V
mV RMS
mV RMS
pA
2
-20
3
kO
dB
dB
Note
4
5
6
7
7
8
All output pins in no-load condition when clock is stopped and when on hook.
All output pins in no-load condition during key input and when on hook/off hook.
Applied to the MUTE pin.
Resistance. when ROW pin or COL pin is 125 Hz and is scanned at high or low level.
Unwanted frequency component corresponding to the total power of the fundamental tone signal of the ROW pin and COL pin.
/'
- - - - - - - - - - - - - S H A R P ---.-.-.-------~
Pulse/Tone Dialer CMOS LSI
•
LR4803
AC Characteristics
(Ta=Z5"C)
Symbol
Parameter
Oscillation start time
Key debounce time
tDB
Pulse rate
PR
Break time
tB
MIN.
TYP.
4
10
20
60
Interdigital pause time
tIDp
1000
Mute overlap time
Predigital pause time
Tone output rate
t MOL
2
40
220
Note 9:
Note
Note
Note
Note
Note
10:
11:
12:
13:
14:
MAX.
8
32
tos
t pDP
TOR
Unit
Note
ms
ms
9
10
pps
t--------
ms
ms
4
11
12
13
13
14
ms
ms
ms
13
When crystal oscillation element with characteristics Rs=1000, Lm=96mH,
Cm=O.02pF, Ch=5pF, f=3.579545 MHz is used.
Key input is accepted after oscillation begins if valid after tDB.
Opens the MODE pin.
Connect the MODE pin to VDD.
During 10·pps pulse mode (112 during 20·pps mode).
100 ms during DTMF mode .
• ' Timing Diagram
( 1)
Pulse mode
Key input
rn
input
IT] inpu~t_ _ _ _ _ _ _~_ _~I~R=E:.::D~I~A=L=-I_in..:.p...:ut_ _ _ _ _ _ _ _ _ __
L...J
~
COL scan
ROW scan
------~
HKS input
MUTE input
PULSE input
Oscillator operation
(2)
Osci lator operation
DTMF mode
MUTE output
TONE output
~~~:J
Normal dialing mode
Automatic dialing mode
---~-------SHARP-------.-
781
.............
..... ......
......
Poise/Tone Dialer CMOS LSI
~-
•
~...,~...,
~
.....
LR4803
.
...,~~~~
.
System Configuration (tone mode connection example)
S1
Rl
~~~~~~~--~~~~~~~o~~~~~~~~--
3-
4~
5 C2
2 C3
C.
1 2
4 5
7 8 9 ST
0 ;I:
*Keydoard
LR4803
MUTE
16
if;
15
R2
14
R3
13
MODE
R.
OSCIN
11
10 P 20pps
OSC
8
Q1
OUT
9
TWO
Ru
P T
3.579545 MHz
Connect to P for pulse mode
Connect to T for tone mode
ZI =10DK820 .
RI
R2
R3
R.
Rs
Rs
R7
=220,1W
=560kO
=1.5kO
=1500
=270kO
=510
=5kO
RB =1000
QI=2N6660
Q2=2N5401
Q3=2N5550
, Q4=2N5550
Q5=2N5550
Qs=2N5550
SI, S2, S3=Hook
DI-D4=lN4004
D5=1N270
Ds=1N752 (5.6V)
D7=1N914
DB=1N914
R9 =2000
RlO=100kO
Rl1=1MO
R12=10kO
R13=4700
* 1 R14=390
*2 CI=68,uF (Must be input to smooth the power supply and
prevent latch up.)
-----~~--~.-SHARP ~--,I-------------.-
782
Pulse/Tone Dialer CMOS LSI
LR4804
•
LR4804
Pulse / Tone Dialer CMOS LSI
Description
•
Pin Connections
The LR4804 is a CMOS LSI for the repertory dialer switchable between tone and pulse dialing
with a 32-digit last number redial and the mode
(pulse or tone) memory storages_
MOD OUT
2
o
TONE OUT
PULSE OUT
ROW\
ROW2
•
Features
L Switchable between DTMF tone dialing and
pulse dialing modes
2. The original mode in OFF HOOK state switchable by a pin and the mode in dialing by a
mode key
3. Stores a 32 -digit telephone number redial
memory and the mode memory
4. PABX pause Storage
5. Uses the single contact or 15 keys matrix
keyboard
6. Make/Break ratio: 40%/60%
7. Switch able between 10 pps and 20 pps in
pulse dialing mode
8. A 3.579545MHz color burst crystal can be
used for the clock oscillator
9. 20-pin dual-in-line package
ROW3
ROW.
HKS
MUTE
MOD SELECT
OSCOUT
lO/20PPS
SELECT
Top View
783
LR4804
Pulse/Tone Dialer CMOS LSI
•
Block Diagram
Mode Select
Hook Switch
Mode Select
19
Pulse Output
13
Mute Output
Column Input
_
CI,)~
~_~1~6
f15 _R3
~*~O~~lD~--~R4
Keyhoard
"'9~---;i-:-:"
1 2
4 5 6
OSCOUT
787
--....- ....---...
Pulse/Tone Dialer CMOS LSI
..........
LR4805
•
,
I
...................
LR4805
~
Pulse / Tone Dialer CMOS LSI,
Description
The LR4805 is a CMOS LSI for the dialer switchable between tone and pulse dialing (make/break
ratio: 32%/68%) with a 32-digit redial number
memory and the pulse or tone mode memory storages.
•
Pin Connections
TONE OUT
MOD OUT
2
0
PULSE OUT
ROWl
ROW2
COL3
•
Features
1. Switch able between DTMF tone dialing and
pulse dialing modes
2. The original mode in OFF HOOK state switchable by a pin and the mode in dialing by a'
mode key
3. Stores a 32-digit telephone number redial
memory and the mode memory
4. PABX pause Storage
5. Uses the single contact or 15 keys matrix keyboard
tl. Make/Break ratio: 32%/68%
7. Switchable between 10 pps and 20 pps in
pulse dialing mode
8.A 3.579545MHz color burst crystal can be
used for the clock oscillator
9. 20-pin dual-in-line package
788
GND
5
ROW3
ROW.
HKS
MUTE
MOD SELECT
OSCOUT
lO/20PPS
SELECT
Top View
Pulse/Tone Dialer CMOS LSI
•
LR4805
Block Diagram
Modle Select
r--------------;2~----------------------------------,
Hook Switch
Mode Select
19
Pulse Output
13
Mute Output
Column Input
RAM
Oscillation Output
L------------------{ll}------------------------(
Voo
IO/20PPS Select
Note)
Be sure not to apply higher voltage than Voo to the TONE
OUTPUT pin.
789
Pulse/Tone Dialer CMOS LSI
LR4805,
Pin Description
•
Pin
Voo
COLl-COLs
ROWl-ROW4
I/O
Key input
I
GND
Ground
OSCIN
OSCOUT
Oscillator connection
MOD OUT
Mode output
10120PPS
10/20PPS
SELECT
select input
MOD SELECT
.
Name
Power supply
MUTE
HKS
Function
Key input of COL 5th row
Key input of ROW 4th row
Negative power supply terminal
I
Collar burst crystal connected
0
0
0
Mute output
Hook switch
Operating mode
Voo
Pin connection
Operating mode
•
Pulse output
TONE OUT
Tone output
Parameter
Maximum pi!! voltage
Power dissipation
Operating temperature
Storage temperature
Note
Note
Note
Note
•
Symbol
Voo
VINl
VIN2
Po
Topr
Tstg
0.3
500
-30-+60
-55-+150
Operating mode
Voo
ON-Hook mode
ON-Hook mode
OFF-Hook mode
Transmission of 10pps or 20pps pulse signal
Transmission DTMF tone signal
Unit
V
V
V
mW
Note
1
2
3
4
"C
"C
1: Referenced to GND
2: The Maximum applicable voltage on any pin with respect to GND
3: The Maximum applicable voltage on any pin with respect to GND
4: Ta = 25't
Recommended Operatir:tg Conditions
Parameter
Supply voltage
790
DTMF tone dialer
Open
GND
0
0
Ratings
10.5
-0.3
Pulse dialer
GND
Pin connection
Absolute Maximum Ratings
Supply voltage
Voo
Transmission of Mute signal
"
PULSE OUT
LOW
IOpps pulse dialer
20pps pulse dialer
I
input
Tone
Level
GND
I
input
High impedance
Pin connection
I
,Mode select
Mode
Pulse
Unit
V
LR4805
Pulse/Tone Dialer CMOS LSI
•
DC Characteristics
Symbol
Paramater
Input voltage
Conditions
MIN.
VIL
TYP.
GND
VIH
0.8Voo
MAX.
Unit
0.2Voo
V
Note
Voo
V
VOR
RL= lkO, Voo=4V
300
400
500
mVRMS
COLUMN
Stand·by current
Voc
RL= lkO, Voo=4V
400
500
Voo=3.5V
1
600
2
mVRMs
ISB
Operating current
lop
Voo=3.5V
1
2
IOL
IpL
Voo=2V, VOL=0.5V
Pulse sink output current
Voo=2V, Vo=0.5V
Pulse leak output current
Key pullup input resistance
iLKG
RKP
Voo=6V, Vo=6V
pA
8
Voo=3.5V
60
KO
Key pulldown input resistance
RKO
Voo=3.5V
2
KO
9
9
HKS pullup input resistance
RHK
Voo=3.5V
30
Tone output
voltage
I
ROW
I
Mute output current
5
6
2
rnA
7
1
rnA
1
Voo 2': 4V
Tone output distortion
PEHB
Pre-emphasis
Memory retention current
KO
-23
Voo 2': 4V, RL=lkO
1
IMR
dB
2
3
dB
0.5
1
pA
10
Note 9: Resistance at which ROW pin or COL pin is scanned to
High/Low level by 125Hz.
Note 10: Unnecessary component~ainst basic tone signal
total power of ROWand COL pins.
Note 5: All output pins in no· load state, clock stationary, on·
hook.
Note 6: All output pins in no· load state, key input, off· hook.
Note 7: Applies to MUTE and MOD pins.
Note 8: Applies to MUTE, MOD, and PULSE pins.
•
pA
rnA
AC Characteristics
Paramater
Key bounce time
Symbol
tOB
Pulse rate
PR
Break time
tB
MIN.
TYP.
Unit
Note
ms
11
pps
r---
68
ms
14
54
10
20
MAX.
70
12
13
14
Interdigital pause time
tIDP
1,000
ms
Mute overlap time
Pre·digital pause time
tMOL
tpop
6
40
ms
16
ms
14
Tone output rate
tOR
220
ms
15
Note 11: Key input is accepted tOB after oscillation starts, if
effective.
Note 12: 1O/20pPs SELECT pin connected to GND.
Note 13: 10120pPs SELECT pin connected to Vo~.
Note 14: 10pPs pulse mode (1/2 in 20pPs pulse mode).
Note 15: 120 ms in DTMF mode.
Note 16: 3.5 ms in DTMF mode.
-.-----..-~-SHARP-.-.-.--.---
791
LR4805
Pulse/Tone Dialer CMOS LSI
•
Timing Diagram
rn
input IMODI inputlIl
input~ inputr--_ _ _~IR:.:;E=D=I~A=L=I~in...:p-u-t_ _ _ _....;........_ _ _ _ __
Key input
COL scan
,
,
ROW scan
HKS input
MUTE output
PULSE 'output
TONE output
lOOms
MOD output
OSCIN
Oscillator operation
OsciI ator operation
Normal dialing mode
Automatic dialing mode
(10pps at pins 11 and 12, on pulse mode select)
•
System Configuration
Rll
T
D?,:
Telephone line
81
~
D6
R
.
Ds
.. ,
..:J
~
~
Z2
D. ~
ZI
~~
;:r
Si
1 2 3 A RED·
IP
4 5 6 B P
7 8 g C IIIJ
0 :j:j:n
*
Keyboard
-~~,
Qs
1
18 CS
RI
17 R2
MUTE 13
16
LED
15 R3
MODOUT ~
0SC
R4/
IN.f'-. 2
1
91
110
1m
IRRB
R
GNI
: 2500 type speech
:
IL C __________
network
I
R7
S
I
R2
Q.
tf
D3
121
VDD
MOD
6
R8
GND
SEL
~ 10/20PPS
83
20 RIO
14
HKS TONE
3lk.o
4
5~ LR4805'
7 C3
19
8 C.
PULSE
+
Z~CI
~R3
Rs
Rg ckRI
D2
,
V Q3
~
DI
R.
I!
i
D
FI
G S
j:{6
a.
.... Q2
.
OSCOUT
3.579545MHz
QI = 2N5401
Q2 - Q s = 1N5550
CR I = CR033
DI - DB = 1N4004
R, = 1'00kO
R2 = 3kO
R3 = 470kO
R. = 1000
Rs = 220k.o (YoW)
R6 = 120kO
R7 = 2,5kO
RB
= 3.30
Rg = 10M.o
RIO = 1kO
Rl1 = 22.0 (W)
Z, = 5.6V: 1N752
Z2 = 110V : 1N5379
S, - S3 = Hook Switch
C I = 681'F
FI = 2N6660
Zener Diode
~'--'-"-----SHARP----'------·--
792
Pulse/Tone Dialer CMOS LSI
LR4806B
•
LR4806B
Pulse / Tone Dialer CMOS LSI
Description
The LR4806B is a CMOS LSI for the repertory
dialer switchable between tone and pulse dialing.
It offers one-touch dialing of up to 21 numbers,
last number redial and other features.
•
Pin Connections
TEST
1
10/20 pps
0
MOD OUT
M/B
MOD
3
OSCOUT
MUTE
4
OSCIN
COL,
COL2
•
Features
1. Switchable between DTMF tone dialing and
pulse dialing modes
2. The original mode in OFF HOOK state switchable by a pin and the mode in dialing by a
mode key
3. Stores twenty 16-digit telephone number memory and recalls by one-touch in the same mode
as the storing mode
4. Stores a 32 -digit telephone number redial
memory and the mode memory and can clear it
arbitrarily
5. Switchable for pulse ratio (10pps/20pps) and
for make ratio (33%/37%) in pulse dialing
mode
6. Hooking control input applied to on-hook dialing and speakerphone
7. Beep-tone output for key input
8. Auto-repeat dialing function/ (In other party's
absence, repeats recalls automatically at constant intervals)
9. Flash signal output
10. PABX pause storage
11. A 3.579545MHz color burst crystal can be
used for the clock oscillator
12. 28-pin dual-in-line package
ROWs
7
COL3
ROW.
S
COL.
ROW3
COLs
ROW2
COL6
ROW!
COL7
KEYTONE
COL.
PULSE OUT
GND
VDD
TONE OUT
Top View
--------SHARP-------793
MOS ICs/LSls
CMOS Gate Array
-LZ92 Series
,
--~~--.-.-~~~-.-.~~-~-
LZ92 Series
•
CMOS Gate. Array
•
Descripition
Feature.
1. Short developing time
2., Low development cost
3_ Suitable for ralatively sin all volume production
but large variety of special-purpose LSIs
4. Abundant series (for 300, 450, 600, 800,
1000, 1500,2200, 3000,4000, and 5000
gates)
The LZ92 series employs the lastest silicon-gate
CMOS technology, and features high speed and low'
power consumption.
The LZ92 series uses a single + 5V power
source, allowing a wide operating voltage range,
and having a TTL-level 110 interface.
The basic internal gate operates in a time delay
of 2.8ns. Ten series are availa-ble depending on the
number of gates: LZ92300, LZ92450, LZ92600,
LZ92800, LZ921000, LZ921500, LZ922200,
LZ923000,LZ924000 and LZ925000.
As development is supported by CAD system,
reliable development of special purpose LSI is
possible in a short time. In choosing a series, considers that 90 % of the internal gate can be used.
•
\
LZ92 Series Device List
Model
-Parameter
No, of gates (as counted in terms
of dual-input NAND gates)
No. of I/O buffers
Total No. of pins
LZ92300 LZ92450 LZ92600 LZ92800 LZ921000 LZ921500 LZ922200 LZ923000 LZ924000 LZ925000
300
450
600
816
1010
37
40
45
48
51
61
64
67
110 level
Internal gate
Input buffer
Delay time
Output buffer
Supply voltage
Internal gate
Power, consumption Input buffer
Output buffer
DIP
QFP
SOP
PGA
DIP: dual-in-Iine package
QFP : quad-flat package
2240
3145
4009
5000
83
112
97
70
86
100
120
TTL/CMOS level
2.8 ns per gate (F.0.=3, wire length 2mm)
128
140
150
54
136
TTL input 4,5ns/CMOS input 4.0ns (F.O.=3, wire length 2mm)
4.5ns (CL=20pF)
5V±5% (TTL interface)/5V±10% (CMOS interface)
25,uW/gate (F.0.=3, wire length 2mm, f=lMHz)
32,uW/gate (F,0.=3, wire length 2mm, f=lMHz)
600,uW/gate (f=lMHz, CL=20pF)
16,18,20 16,18,20 18,20,22 18,20.22 22,24,28 24,28,30
22 24 28 24 28 30 24 28 30
24,28,40
~,~,~ ~:~:~ ~:~:~ ~:~:~ ~,@,~ @,~.~
~,@
Package
1500
M
~
36.44,48 36,44.48
24 '
M
~.M
M
40,64
64
64
M
44,48,60 60,64.76
64,76,80 76,80,*96 76,80,*96
36.44.48 36,44,48 44,48,60
64,76,80 80,96
60
60,64
64,76
96.100
100
100
96
100
24
24
24
24
120
SOP: small-out-Iine package
PGA : pin-grid array
120.144 120,144,180
* Limited to 18 X 18 mm square type,
-----------SHARP.--.-.--------
796
CMOS Gate Array
•
LZ92 Series
Absolute Maximum Ratings
Symbol
Vee
VI
Vo
Topr
Tstg
Paramater
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
•
Ratings
-0.3-7
-0.3-Vee+0.3
-0.3-Vee+0.3
-10-+70
-55-+150
Unit
V
V
V
QC
QC
Recommended Operating Conditions
Symbol
Parameter
Supply voltage
Operating temperature
•
Vee
Topr
MIN.
4.75
-10
TTL level
TYP.
MAX.
5.25
5
+70
Symbol
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input leakage current
Output leakage current
•
VIL
VlH
VOL
VOH
iIL
Ioz
Test conditions
IOL=4mA
(
IOH=-2mA
Vl=OV-Vee
High impedance status
10r----------------------------,
Vcc=5V, Ta=25"C
.,
= 2mm
-.5
.~
5
c
.S
.
~
go
...
p..
o
2
3
4
5
6
7
Fan out number
V
QC
TTL level
MIN. TYP. MAX.
0.8
2.0
0.4
2.4
-10
10
-10
10
CMOS level
MIN. TYP. MAX.
1.5
3.5
0.4
4.0
-10
10
-10
10
Unit
V
V
V
V
pA
pA
Logic cells such as inverters, NAND gates, and
NOR gates, and composite gates such as latches
and flip-flops are available in 81 cell types.
(2) Input/output buffer cells
Buffer cells used in the periphery of a chip are
available in 6 types of write-only buffers, 4 types
of read-only buffers, and 4 types of read/write
buffers: 14 types in all.
•
.,
~
....
Unit
(1 ) Logic cells
Basic Cell Delay Time
The following figure shows typical propagation
delay times of a three-input NAND gate, two-input
NAND gate, and inverter each configured with
basic cells.
Wire length
CMOS level
TYP.
MAX.
5
5.5
+70
(Vee=5V±5%, Ta=-10-+70"C)
Electrical Characteristics
Paramater
MIN.
4.5
-10
8
9 10
Development of LSI Devices USing
Gate Arrays
For gate array development we provide the following:
CD Design manual
® Cell library
® Design form (2mm graph paper in A2 size)
® Test pattern coding sheet
® Logic template
After completing logic design in accordance with
the design manual. please submit the following to us:
CD Logic diagram
® Input/output timing diagrams (test data)
® Package specifications
® Pin configuration
797
LZ92 Series
CMOS Gate Array
•
Development Sequence Flowchart for Gate Array LSI
-----Presentation of
LST
specifications
-
Client
!
Logic circuit diagram
Timing chart (test data)
..;- Layout
I
Package specification
........ _ ,
.......
~
Approval
OK
approval
Critical path
assignment diagram
and specifications
~
Design manual
I:
-
Design manual
Design remarks
Function block
Method of drawing logic
circuit diagrams
Method of making timing chart
Log ic circuit
diagram
Tim ing chart input
-
Machine write
Logical circuit
output
1i
I
--
Cell library
I
!
Simulation and
SHARP
L
oglca Slmu ation
'
"
E
Jl
...'"
Approval
'"
Automated
positioning
Automated layout
OK
I
Q
«:
U
-
~
Timing simulation
t
I
~
Writing design
specification
documents
I
Appr./
OK
Mask making
I
-
Making master
wafer
(Before
dis tribution)
Trial sample test ~
1
I
Sample making and
NG
I
Evaluation
mass production
Mass production
I
Delivery
II
I
798
I
!
OK
I
Sample
Master wafer
LZ92300
LZ92450
LZ92600
LZ92800
LZ921000
LZ921500
LZ922200
LZ923000
LZ924000
LZ925000
CCD Image Sensor
LZ2020
LZ2020
•
CCD Image Sensor
•
Description
Pin Connections
The LZ2020 is a CCD linear image sensor with
2,048 PN photodiode elements, two 1,024-bit analog shift registers, an output amplifier and compensation output amplifier on a single chip.
•
Features
1. Dynamic range 54dB (TYP.)
2. Enhanced spectral response (particularly in the
blue range) and excellent output uniformity
3. Transfer efficiency 99.996%
4. 2,048 elements on a single chip; picture element size: 14 pmX 14 pm
5. On chip output amplifier and compensation
amplifier
6. All operating voltages under 15V
7.8 lines/mm resolution across a 256 mm page
8. 24-pin dual-in-line package (Ceramic)
•
Top View
Block Diagram
Shift Registor
Clock
~
r----U~--------~9
Reset
Transistor Reset
Transistor
Output Gate
, Drain
Gate
Clock
8}---------~5
Output
Transistor
Drain
Test
Output
1 Transistor
Transfer
Gate
Clock
Source
Dummy
3 Output
Transistor
Source
Test
Shift Resister
Clock
Dummy Reset
Transistor
Gate Clock
~
Dummy
Reset
Transistor
Drain
-~--------SHARP-'------'-'"
799
CeD Image Sensor
•
lZ2020
Absolute Maximum Ratings
Parameter
Pin voltage *
Operating temperature
Operating temperature
*
•
Ratings
"-0.3-+18
-25-+55
-40-+100
Symbol
VT
Vonr
T.t •
Unit
V
t;
t;
Voltage applied to any pin with respect to Vss.
Electrical Characteristics
(foil =f0l2=0.2MHz, fRs =O.4MHz, T 1nt =10ms, VoD =15V, V RD =14V, VoG =9V, VPG =l1V, Ta=25t;)
Parameter
Dynamic range
Saturation exposure
Saturation output voltage
Sensitivity
Photo response non-uniformity
Average dark signal
Dark signal non-uniformity
Spectrum range
Power consumption
Output impedance
Symbol
DR
SE
V••t
R
PRNU
ADS
DSNU
SR
P
Z
Conditions
(IX2)
(1)
(lX2)
(lX2)
(2X3)
(2)
(2)
MIN.
0.4
400
0.5
0
0
0.35
(2)
(2)
TYP.
54
0.7
550
0.8
±7.5
0.8
150
1.0
MAX.
1.3
650
1.2
±10
5.0
5.0
1.1
Unit
dB
1x's
mV
V/lx-s
%
mV
mV
pm
mW
k.o
Condition (1) : Standard tungsten lamp, 2854°K
Condition (2) : Load resistance, 1k
Condition (3) : Standard tungsten lamp, 2854 OK, with I -75 filter
(1) Photo Response Non- uniformity (PRNU)
Bit voltage non-uniformity
Within ± 3.0% relative to the previous bit
\
m I
,..-_,..- Reference
J.
it
U"J:~~-==t
level
.1V
.1V",= IVi-I-Vi I
.1V
V'_I XI00;;o3.0%
where, i=1-2,048
Effective bits: 0-2,047, Reference level is a voltage at reset.
(2) Signal Rise Time
tl = 120ns
t 2 =100ns
t3=I60ns
The output voltage shall settle within 100ns
after ~ IA has risen above 8 volts.
(Waveform is observed with an oscilloscope.)
800
LZ2020
CCO Image Sensor
(3) Output during halt period
f {> 1 =f {> 2=O.5MHz, fRS= lMHz
T 1nt =2.2ms, VoD =12V, VRD =14V, VOG=9V .
VPG =l1V, Ta=25t
The output during the halt period shall be 7mV or lower, while the output level is kept at 125mV.
Note:
•
The test conditions (1), (2) and (3) are applicable to items (1), (2), and (3).
Pin Capacitance
Parameter
Shift register clock
Transfer gate clock
Reset transistor gate clock
Output transistor source
•
(Ta=25"C)
Pin number
8,9,16,17
13
4,20
1,23
TYP.
550
230
10
10
Unit
pF
pF
pF
pF
Recommended Operating Conditions
Symbol
Parameter
Output transistor drain voltage
VOD
Reset transistor drain voltage
VRD
Output gate voltage
VaG
Photo gate voltage
VPG
Test pins 1 and 2
TP io TP 2
Test pins 3 and 4
TP 3 , TP 4
~ LAL> 12AL
Shift register clock, low level
~ JBL>
Shift register clock, high level
(Ta=25"C)
Conditions
VPG =V,sTH+l(V)
MIN.
14.5
13.5
8.0
10.0
14.5
TYP.
15.0
14.0
9.0
11.0
15.0
0
MAX.
15.5
14.5
10.0
12.0
15.5
Unit
V
V
V
V
V
V
0
0.5
0.8
V
11.0
12.0
13.0
V
0
9.0
0
9.0
0.5
10.0
0.5
10.0
0.8
11.0
0.8
11.0
V
V
V
V
; 2BL
; LAU, ; 2M
; LBU, ; 2BH
Transfer gate clock, low level
Transfer gate clock, high level
Reset gate clock, low level
Reset gate clock, high level
Shift register clock frequency
V PTL
V"TH
VRSL
VRSH
f;LA>f;2A
0.5
MHz
1.0
MHz
f;JB,f;2B
Reset gate clock frequency
fRs
801
LZ2020
CCD Image Sensor
•
Drive Signal Timing Chart
r-IE;------------T,",
-Il-------------ill-------l
¢T
RS
as
Optoelectric transducing period
1 2 3 4
~
~~
bits
t,>100ns
t5 > lOOns
2047
tl>O
tz>l,us
t3> 1,us
t/JT~
1 tl~tz~ t3r-
RS
t/JIA,t/JIB~
os
2
*2
>IE 1 1, z vs. T relationships
•
3
I, z vs. RS relationships
Photo-element Structure
AI
Channel stopper
Unit: mm
•
Standard Characteristics
Dark current characteristics
2)
100
55T I
<:>
:::
.. .
x
.,
.,
.±:
! '0"
'0
>
-" "
>
~
0
.~
I
>.
60
."'=
-'
40T
0
"
10
... 20
/
'"
/
./
1/""""':
.~
./
.;;
.,"
.,
./
/
.fr 40
Ul
~
I
:;
B
100
I
80
0; .S
Ul
Spectral sensitivity characteristics
til
./
./
0.5
1.0
1.5
2.0
2.5
Integration period T S (s)
50
V
.:::
~t
C
10
1\
\
,,-
"
0::
0
3.0
/
v 1\
..........
u
"
400
600
800
1,000
Wavelength (nm)
- - - - - - - - - - - - - - - - - S H A R P - - - - - - ' - - ...........
802
• I§
I
I
I
(J)
I»
I
I
I
ICIC
I
'0
IC3B
C,
.1~
0
::2.
<
CD
+I5V
0
;J;
I
I
~r
c:
CKQ
CKQ
J
K Q
J
K Q
IC2A
IC2B
IC5A
;:::;:
500
IC5B
500
CKQ
500
500
DS0026
X2
2kO
Voe
I
L
2kO
D Q
L_
J-+15V
Vee
I
I
I
I
I
I
IC3A
R,=IkO
C, =500pF
R,
lkO
I
~N
3
CD
~
+I2V
ICI
IC2,5,6
IC3
IC4
IC7,8,9
8I
~
SN 74132
SN 74107
SN 7404
SN7474
SN74I61
+15V
LZ2020
1
2
3
4
5
7
8
9
10
11
12
16
15
14
13
+15V
H
I
I
I
I
I
I
I
h
~
LZ1008AD
High VOltage MOS IC
LZI008AD
High Voltage MOS
•
Description
The LZI008AD is a high voltage (300V) 8-output-port monolithic Ie fabricated using Sharp's
advanced N-channel DMOS process. It can be used
as a matrix driver for electrolumiIlescent panels,
plasma display panels, electrostatic printers and
TTL-high voltage circuit interfaces.
•
1.
2.
3.
4.
5.
6.
•
Ie
Pin Connections
Features
High voltage 300V (MIN.)
Output current 35mA (TYP.)
Mutual conductance 10m U (TYP.)
TTL compatible
DMOS process
I8-pin dual-in-line package
•
Top View
Equivalent Circuit
Gate 1 Drain 1 Gate 2
Drain 2
Gate 8
Drain 8
L---+-----4.------4--------4-----<>-----Q Source
* leakage transistor
.-.--------SHARP-~--...-..----
804
High Voltage MOS IC
•
LZ1008AD
Absolute Maximum Ratings
Parameter
Input high voltage
On·output high voltage
Off·output high voltage
Power consumption
Derating ratio
Operating temperature
Storage temperature
Symbol
BVIN
Vo IN
Vo
OFF
PD
Conditions
Applied to input pins.
Applied to output pins at
V;N=5.5V.
Applied to output pins at
VIN=OV.
Ta;i25t
Ta>+25t
Ratings
-0.4-+15
Unit
V
Note
1,2
-0.4-+300
V
1,2
-0.4-+600
V
1,2
0.91
9.5
-20-+70
-55-+155
mW/t
t
t
Toor
TstR
W
Note 1: The maximum applicable voltage on any pin with respect to GND.
Note 2: Permanent damage will result if a voltage above the rated value is applied.
•
(Ta=-20-+70t)
Electrical Characteristics
Parameter
Output high voltage
Output voltage
Input high voltage
Threshold voltage
Symbol
BV OUT
VOUT
BV IN
Vp
Output current
lOUT
Output leakage current
lLO
Input leakage current
On·state resistance
Mutual conductance
Input capacitance
ILIN
RON
Gm
CIN
Conditions
VIN=OV, IOUT=20 pA
VIN =5.5V, D=O.1 %
IIN=20pA
VouT=10V,louT=lpA
VIN =4.5V, VouT =300V, D=O.l%
VIN =2.5V, VouT =300V, D=O.l%
VIN =O.4V, VOUT=300V
VIN =0.8V, VouT=300V
VIN =10V
VIN =4.5V, IouT=5mA
VIN =2.55V, VouT =100V
VIN=OV, f=IMHz
Note 3: D(duty cycle)=O.l%, see following waveform.
ON ----------~
MIN.
600
TYP.
MAX.
300
15
0.8
30
1.5
1.4
35
.10
/ 10
5.0
1.0
1.0
3
10
10
n
OFF---------~
L-__________~.
J
I
~.-----
Unit
V
V
V
V
Note
mA
3,4
pA
pA
pA
kO
mU
pF
5
4,5
4
4
4
3
4
tl =101's
t2=10ms
~1·~------;t2--------~.,
Note 4: At Ta=25't
Note 5: The value for one HVMOST output pin.
805
High Voltage MOS IC
•
lZ1008AD
Electrical\Characteristics Curves (Ta=25t unless otherwise specified)
)
On-state resistance vs. Ambient temperature
C 2.5
VOUT=5V
IouT=5mA
C
~
2
~
Threshold voltage vs. Ambient temperature
1.5;.--_,.-----r----,-----.------,
VOUT=lOV
IouT=I.uA
e
..
:>-
~
1.5
!
.2l
1
.,
(15
~
!
'f'
~
~
0
~
..,
L
--
-50
~
~
..!!
~
:si 115
-----
...8Ul
.,
.......
Eo-<
o
50
100
('C)
Ambient temperature Ta
60
VOUT=5V
. VIN=5V
- r---50
---r----- -
g 40
.. 30
il
~
20
1.. 10
o 0
o
-50
50
100
Ambient, temperature Ta
150
('C)
0
50
Ambient temperature
Output current vs. Ambient temperature
-<
~
0
-50
150
100
Ta
150
('C)
. Input current vs. Ambient temperature
4
!
z
3
..:;
---
V,,=10V
r----
~
1
o
50
Ambient temperature
100
Ta
150
('C)
Output current vs. Output voltage·
50
V,,=6V
-<
~ 40
....
:>
0
1i...
!i
30
20
...-
~
,~
5.5
5.04.5
I--
4.03.5
I Ifr
3.0
2.5-
10
2.0
1.5
0
100
200
Output voltage
300
VOUT
(V)
----~-----SHARP-...-.-.--.---
806
High Voltage MOS IC
LZ1016AD
LZI016AD
High Voltage MOS IC
•
Pin Connections
•
Description
The LZI016AD is a high voltage (250V) 16-output-port monolithic IC fabricated using Sharp's
advanced N-channel DMOS process. It can be
used as a matrix driver for electroluminescent
paneis, plasma display panels, electrostatic print·
ers and TTL-high voltage circuit interfaces.
•
•
Features
1. High voltage output 250V (MIN.)
2. Output current 45mA (TYP.)
3. Internal 8·bit X 2-shift-register circuit
4. Circuit expansion capability
5. TTL compatible
6. High speed data transfer (clock frequency
4MHz)
7. Single power supply: + 5V
8. DMOS process
9. 28-pin dual-in-line package
Top View
Block Diagram
...o
"
G
--.. 109,
'"
Qo
8bits
Shift Register
NC
Truth Table
T
DI~
CL
X
X
L
H
L
H
H
H
STB I-iVMOST
X
OFF
L
ON
H
ON
H
OFF
'
High Voltage
Output
~'-~-----SHARP-'-'--'----"-
807
High Voltage MOS IC
•
LZ1016AD
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Symbol
Vee
VIN
VOUT
ON·output high voltage
,VHVO(ON)
OFF ·output high voltage
VHVO(OFF
Power consumption
Derating ratio
Operating temperature
Storage temperature
Note
Note
Note
Note
PD
(Ta=25'C)
Conditions
Applied to the logic supply pin.
Applied to all input pin.
Applied to the data output pin.
Applied to the high voltage
output pin.
Applied to the high voltage
output pin.
Ratings
-0.3-+7
-0.3-+7
-0.3-+7
Unit
V
V
"V
Note
1
1
1
-0.3-+250
V
1,2,4
-0.3-+350
V
1,3,4
600
5
-20-+70
-55-+155
mW
mW/'C
'C
'C
Ta~25'C
Ta>+25'C
Toor
T st•
1: The maximum applicable voltage on any pin with respect 'to GND.
2: Applied when HVMOST is on.
3: Applied when HVMOST is off.
4: Permanent damage will result if a voltage above the started value is applied.
DC Characteruistics
•
(V ee =+5V±10%)
(1) HVMOST Characteristics
Parameter
Symbol
,ON·state resistance
RON
Output current
IHvo
Output leakage current
IlL I
Total output leakage current
I hL I
Conditions
HVMOST "ON"
IHvo=5mA, Ta=25'C
HVMOST ·ON"
VHvo =250V, Ta=25'C
HVMOST ·OFF"
VHvo =300V, Ta=-20-70'C
HVMOST ·OFF"
VHvo =300V, Ta=-20-70'C
TYP.
MIN.
MAX.
Unit
650
0
Note
mA
5
10
pA
6
30
pA
7
40
Note 5: D(duty circle)=O.1 %, see following waveform.
n
. .....- - -
ON ---------c:::Ltt
OFF ---- _ _r-L
IE
t2
..
I
tt=10ps, t2=10ms
Note 6: Value for each HVMOST output pin.
Note 7: Sum of total output leakage current.
(2)
Parameter
Supply voltage
Input high voltage
Input low voltage
Symbol
Icc
VIH
VIL
Output high voltage
VOH
Output low voltage
VOL
Input leakage current
I IlL I
808
(Vcc =+5V±10%, Ta=-20-+70'C)
Logic Section Characteristics
Conditions
MIN.
VIN=OV
2.0
-0.3
IoH = -0.5mA; applied to
Doun , DouTz.
IOL = 1.6mA; applied to
---Doun, Doun.
VIN=OV-Vcc
----
TYP.
MAX.
18
Vee
0.8
Unit
mA
V
V
V
2.4
0.4
V
10
pA
High Voltage MOS IC
•
LZ1016AD
(V cc =+5V±10%, Ta=-20-+70t)
AC Characteristics
Symbol
Parameter
Clock frequency
Clock pulse width
DIN setup time
DIN hold time
LS pulse width
Clock to LS delay
LS to clock delay
DouT delay
LS to STB delay
LS to CL delay
STB pulse width
CL pulse width
HVO fall time
HVO rise time
Conditions
MIN.
t,., t~
t DS
tDH
t LP
tCL
t LC
tpD
t LSB
tLCL
tsp
tcLP
tpL
tpH
MAX.
4
CL=30pF+ 1TTL
190
0
0
1
1
CL=2,200pF
RL=33kO
LZ 1016 A
Input signal conditions:
Input pulse level: + 0.8 to + 2.0V
Input rise/fall time: 20 ns
Time measurement level: 50%
Note
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
fLs
fLs
fLs
#s
fLS
#s
100
60
60
150
0
0
50
340
Note 7: Applied to data output pins.
Note 8: Applied to high voltage output pins; test circuit is as follows.
•
TYP.
f~
7
8
8
RL =33kO
-----4
..---+--_-.1\/"'----_ HV (300V)
(VCC=OV, f=lMHz, Ta=25t)
Pin Capacitance
Symbol
CiN
Parameter
Input capacitance
High voltage output
pin capacitance
CHVO
Conditions
MIN.
VIN=OV
VHVO=OV
TYP.
6
17
MAX.
10
Unit
pF
30
pF
•. AC Timing Chart
CLOCK
L5
5TH
7
_ _ _ _ _...J,r~:---tcLP'------o~-----HV08
~~------------
90 %
809
. High Voltage MOS IC
LZ1016AD
.......II!I!I• ......,..-....,....... . - . . . . , . . - . . . . , . . . . , . . . . , . . -_ _ _
•
,._~....,....,
Electrical Characteristics Curves (Vcc=5V, Ta=25t unless otherwise specified)
Output current vs. ambient temperature.
ON-state resistance vs. ambient
temperature
1200
eL="High"
,.
STB="Low
~<:
Sa
.,.,
z II
~!
"'..,
!
/
/
1000
o 0
800
..
...
600
til
'r;;
...'"
'"
E
'('
400
Z
0
200
I'
/
V
/
80
/
<:
~
0
:z:
.....>
d
i
o
-50
0
"~
60
50
......'"
..,os
os
0
-100
70
eL=Pulse
STB="Low
'\.
50
ISO
100
30
20
-100
200
("e)
Ambient temperature Ta
40
-50
0
'"
.
'" '"
50
100
Ambient temperature Ta
150
200
('e)
Output current vs. output voltage
70
60
<:
~ 50
0
..:;>
Ii...
...
..,os
-=
~
40
30
20
#;
JV
,
~
~
\'ee- 5.5\'
5.0\'
4.5V F - -
-
I--""
I
0
.
10
0
STB="Low
eL=Pulse(Note 1 )
100
300
200
Output voltage V HVO
(V)
Note 1: The pulse described below is applied to CL.
n
Vee -------I=t-tl .
GND----~ L---H---~ L
\E
t2
.\
tl=IOjls, h=IOms
(D=O.I%)
-------.....-.-----$HARP . . . . - . - - - - - - - - - - 810
High Voltage
Mas IC
LZ1032AM
LZI032AM
•
High Voltage MOS
Description
The LZ1032AM is a high voltage (250V) 32-output-port monolithic Ie fabricated using Sharp's
advanced N-channel DMOS process. It can be
used as a matrix driver for electroluminescent
panels, plasma display panels, electrostatic printers and TTL-high voltage circuit interfaces.
•
•
Ie
Pin Connections
Features
1. High voltage output 250V (MIN.)
2. Output current 45mA (TYP.)
3. Internal 32-bit shift register circuit
4. Expandable circuit structure
5. TTL compatible
6. High speed data transfer (clock frequency
4MHz)
7. Single power supply: + 5V
8. DMOS process
9. 44-pin quad-flat package
•
Top View
Block Diagram
Data
Output
High
Voltage
Output
Truth Table
Data
Input 6
DIN CL STB HVMOST
X
X
L
H
Clock
L
H
H
H
X
L
H
H
OFF
ON
ON
OFF
Latch Strobe Clear
Strobe
811
.........................................,..............:..,....:-..............-.
HighVortage MOS IC
LZ1032AM
(Ta=25t) .
•. Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Oiitput voltage
.Power consumption
Derating ratio
Operating temperature
Storage temperature
Symbol
Vee
VIN
You;.
VHVO(ON
~HVQLOFF
" Po
Conditions
Ratings
-0.3-+7
-0.3-+7
-0.3-+7
-0.3-+250
-0.3-+350
600
5
-20-+70
-55-+150
Appliep to input pins.
Applied to data output pins.
Ta~25t
Ta>+25"C
.
Topr
T't2
Unit
V
V
V
V
V
mW
Noie
1
1
1
1,2
1,3
mW/t
t
t
Note 1: The maximum applicable voltage on any pin with respect to GND.
Note 2: . The maximum applicable voltage when HVMOST is ON.
Note 3: The maximum applicable voltage when HVMOST is OFF.
•
DC Characteristics
(V ee =+5V±10%)
(1) . HVMOST Characteristics
Parameter
Symbol
ON·state resistance
RON
Drain current
IHvo
Output leakage current
Output total leakage current
Note 4:
Note 5:
Note 6:
(2)
IL
ITL
MIN.
Conditions
HVMOST "ON"
IHvo =5mA, Ta=25"C
HVMOST "ON"
VHvo =250V, Ta=25"C
HVMOST "OFF"
VHvo =300V, Ta=-20-+70t
HVMOST "OFF"
VHvo =300V, Ta=20-70t
TYP.
MAX.
Unit
650
n
40
Note
mA
4
10
pA
5
30
pA
6
Duty circle = 0.1 %. with 10,u s ON·period.
The value for one HVO output pin.
The total leakage current of HVO.
(V ce =+5V±10%,Ta=-20-+70"C)
Logic Characteristics
Parameter
Supply voltage
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Symbol
lee
VIR
VIL
VOH
VOL
IlL
Conditions
MIN.
VIN=OV
IoH = -0.5mA, Applied to DouT
IOL = 1.6mA, Applied to DouT
VIN=OV-Vee
2.0
-0.3
2.4
TYP.
MAX.
18
Vee
0.8
0.4
10
Unit
mA
V
V
V
V
pA
-----~~---SHARP~-.-..------.-....---
812
High Voltage MOS IC
•
LZ1032AM
(Vcc=+5V±10%, Ta=-20-+70t)
AC Characteristics
Parameter
Clock frequen~y
Clock pulse width
DIN setup time
DIN hold time
LS pulse width
Clock to LS delay
LS to clock delay
DouT delay
LS to STB delay
LS to CL delay
STB pulse width
CL pulse width
HVO fall time
HVO rise time
Symbol
Conditions
MIN.
TYP.
f~
t ~, t-;
tos
tOH
t LP
tCL
tLc
tpo
CL (D ouT )=30pF+1TTL
190
0
0
1
1
CL (HVO)=2,200pF, RL =33kO
CL (HVO)=2,200pF, RL =33kO
50
340
Note 7: The output delay depends on the load condition.
Test conditions:
Input pulse level: + 0.8 to + 2.0V
Input rise/faIl time: 20 ns
Time measurement level: 50%
HVO output load. condition: See figure.
•
Note
7
HV(300V)
RL =33kO
HVO
----i
LZI032AM
(VCC=OV, f=lMHz, Ta=25t)
Capacitance
Parameter
Input capacitance
Output capacitance
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
fls
fls
fls
flS
100
60
60
150
0
0
kSB
tLCL
tsp
t CLP
tpL
tpH
MAX.
4
Symbol
CIN
CHVO
Conditions
VIH=OV
VHVO=OV
All pms except for the pm under measurement are grounded.
MIN.
TYP.
6
17
MAX.
10
30
Unit
pF
pF
;
-----------SHARP----------813
High Voltage MOS IC
.LZ1032AM
........... - . . -__...._ ._ _...... - . . - . . - .......-.r.-.r.-.r.-..-......
•
' AC Timing Diagram
CLOCK
DIN
DouT
LS
STB
CL
90%
Hvon
•
Example of Application
The following is a thin film EL matrix panel
drive circuit fabricat~d by application of the high
voltage MOS Ie.
Note: The thin film EL matrix panel is a capacitive load.
814
High Voltage MOS
Ie
LZ1108AD
LZII08AD
High Voltage MOS
•
Description
The LZl108AD is a monolithic FET array fabricated using Sharp's abvanced P-channel DMOS
process_ It provides voltage as high as 600V in
input-off state, and permits stable operation at
300V drain voltage in input on state_ It can be
used as a matrix driver for electroluminescent
panels, plasma display panels, and electrostatic
printers.
•
•
•
Ie
/
.Pin Connections
o
Features
l. High voltage 300V (MIN_)
2_ High density 8 output/package
3_ Output current 20mA (TYP_ : VHVO = 300V)
4_ High mutual conductance 7.5m U (TYP.)
5_. DMOS process
6_ I8-pin dual-in-line package
Top View
Equivalent Circuit
Drain 8
Drain 1
Gate 8
Gate 1 o--.JVV'r-----1--I
Source
o-----+----'-~~--------------+-------~-'
'Leakage transistor
815
.....
......... .........--'
Absolute PI(Iaximum Ratings
(Ta=25"C)
High Voltage MOS IC
.-.~~
•
.LZ1108AD
-~~.-.~...--.~.....-~
Symbol
BV IN
Parameter
Input high voltage
, ON-output high voltage
BVo ON
/.
OFF-output high voltage
BVo OFF
Power consumption
Derating ratio
Operating temperature
Storage temperature
PD
Conditions
Appiy to input pins.
Applied to the output pin,
when ViN=5.5V.
Applied to the output pin,
when VIN=OV.
~
Ratings
-15-+0.4 ..
Unit
V
Note
1,2
-300-+0.4
V
1,2,3
-600-+0.4
V
1,2
600
5
-20-+70
-55-+150
mW
mW I"C
"C
"C
I.
Ta~25"C
Ta>+25"C
Topr
T s,",
Note 1: The maximum applicable voltage on any pin with respect to S (Source).
Note 2: Permanent damage will result if a voltage above the stated value is applied.
Note 3: D (duty cycle) = 0.1 %, ON time = 10 f.ls.
•
(Ta=-20-+70"C)
Electrical Characteristics
Parameter
Output high voltage
Output voltage
Input high voltage
Threshold voltage
Symbol
BVOUT
VOUT
BV IN
Vp
Output current
louT
Output leakage current
I lLO I
Total output leakage current
I hLO I
I ILIN I
Input leakage current
ON resistance
Mutual conductance
Input capacitance
Note 4:
RON
Gm
CIN
Conditions
VIN =OV,louT =-20pA
VIN =-5.5V,O=0.1%
IIN =-20pA
VOUT= -10V, lOUT = -1 pA
V1N =-4.5V, VouT =-300V, D=O.1%
V1N =-2.5V, VouT =-300V, D=O.1%
V1N =-0.4V, VouT =-600V
VIN =-0.8V, VouT =-'600V
V1N = -O.4V, VOUT= -600V
VIN =-0.8V, VouT =-600V
VIN =-10V
VIN = -4.5V, louT= -lmA
VIN =-3.0V, VouT =-150V
VIN=OV, f=lMHz
MIN.
-600
TYP.
MAX.
-300
-15
-1.1
-15
-1
-1.1
-20
10
10
30
30
5
2
1
3
7.5
10
Unit
V
V
V
V
Note
rnA
4,5
pA
pA
pA
pA
pA
6
5,6
7
5,7
5
5
5
kn
mU
pF
4
5
D (duty cycle) = 0.1 %; see following waveform.
r--------,
OFFn---ON _________
-::L:J-
Note 5: Ta=25"C
Note 6: Value for each HVMOST output pin.
Note 7: Sum of total HVMOST output current.
U
~1>------t2----_"'i~1
r---h=10J'S
t2=10ms
..
---------------SHARP
816
~.-.-.--.-.--
High Voltage MOS IC
•
LZ1108AD
Electrical Characteristics Curves
Output current vs. Output voltage
6'......2. -60
-:;
II
8
-50
<: -40
-5
1-<
::>
-30
~
~
""......
"
;;"
;;'"
0
-20
VIN=-7V
/
6V -
V
5V
V
4V
V
-10
o
3V
2V
---'200 -400 -600 -800 - 1000 -1200
Output voltage
V OpT
(V)
.--------SHARP--------
817
. High Voltage MOS IC
LZ1116AD
LZll16AD
••
High Voltage ·MOS
•
Description
Ie
Pin Connections
The L21116AD is a high voltage (- 300V)
16-output-port monolithic Ie fabricated using
Sharp's advanced P-channel DMOS process. It
can be used as a matrix driver for electroluminescent panels, plasma display panels, electrostatic
printers.
o
S'1'1l
CL
DOUT2
DIN2
GND
HVOIS
HV015
HV014
•
Features
1. High voltage output 300V (MIN.)
2. Output current 30mA (TYP. : VHVO = 300V)
3. Internal 8-bit X2-shift-register circuit
4. Expandable circuit structure
5. High speed data transfer (clock frequency
4MHz)
6. Single power supply: - 5V
·7. DMOS process
8. 28"':pin dual-in-line package
•
HV03
HV013
HVO.
HV012
HVOs
HVOll
HVOs
HVOIO
HV07
HV09
. HVOg
NC
Top View
Block Diagram
8bits
::ihift Register
,
Truth Table
DIN CL STB HVMOST
X L
X
OFF
H
ON
X L
H L
L
ON
OFF
L
L
L
High Voltage
Output
I,
~""""'------~--~SHARP~''-'----~--''''''''''''
818
High voltage MOS IC
LZ1116AD
(Ta=25"C)
Absolute Maximum Ratings
•
Parameter
Supply voltage
Input voltage
Output voltage
Symbol
Vee
VIN
VOUT
ON·output high voltage'
VHYO(ON)
OFF·output high voltage
~HVO(OFF
Power consumption
Derating ratio
Operating temperature
Storage temperature
Note
Note
Note
Note
•
1:
2:
3:
4:
Po
Conditions
Applied to the logic supply pin.
Applied to all input pins.
Applied to the data output pin.
Applied to the high voltage
output pin.
Applied to the high voltage
output pin.
Ta~25"C
Ta>+25"C
T oDr
T stg
Ratings
-7-+0.3
-7-+0.3
-7-+0.3
Unit
V
V
V
Note
1
1
1
-300-+0.3
V
1,2,4
-300-+0.3
V
1,3,4
600
5
-20-+70
-55-+150
mW
mW/"C
"C
"C
The maximum applicable voltage on any pin with respect to GND.
Ap'plied when HVMOST is ON. D (duty cycle) = 0.1 %, ON time = 10 "s
Applied when HVMOST is OFF.
Permanent damage will result if a voltage above the stated value is applied.
DC Characteristics
(1)
Parameter
Symbol
ON ·state resistance-
RON
Output current
IHyo
Output leakage cUl'rent
I IL I
Total output leakage current
I ITL I
Note 5:
Note 6:
Note 7:
(2)
(Vee=+5V±10%)
HVMOST Characteristics
Conditions
HVMOST "ON"
IHYo =-lmA, Ta=25"C
HVMOST "ON"
VHYo =-300V, Ta=25"C
HVMOST "OFF"
VHVO= -300V, Ta=-20-+70t;
HVMOST "OFF"
VHvo =-300V, Ta=-20-HOt;
MIN.
-20
TYP.
MAX.
Unit
1.3
kn
-30
Note
mA
5
10
p.A
6
10
p.A
6
D (duty cycle) = 0.1 %; see following waveform.
0:: ~~~~~~ ______t=:fr----------.. . . .U
Value for each HVMOST output pin.
Sum of total output leakage current.
'JooEE>-------t2-----"'''"i,
(V ec =+5V±10%, Ta=-20-+70"C)
Logic Section Characteristics
Parameter
Supply voltage
Input high voltage
Input low voltage
Symbol
Icc
VIR
V1L
Output high voltage
VOH
Output low voltage
VOL
Input leakage current
IlL
tl=10"s
t2=lOms '
Conditions
MIN.
V1N=OV
-0.8
Vee
IoH = -0.5mA; applied to
DouTl, DOUT2
IOL = 1.6mA; applied to
---DOUTh DOUT2
VJN=OV-Vee
----
TYP.
-6
MAX.
-12
0.3
-2.4
-0.5
Unit
mA
V
V
V
-2.5
10
V
p.A
--------.--------SHARP.-~~------
819
High Voltage MOS IC
LZ1116AD
(V cc =:=+5Y±10%, Ta=-20-+70"C)·
AC Characteristics
•
Parameter
Clock frequency
Clock pulse width
DIN setup time
DIN hold time
LS pulse width
Clock to LS delay
LS to clock delay
, DouT delay
LS to STB delay
LS to CL delay
STB pulse width
CL pulse width
HVO fall time
HVO rise time
Symbol
fl'
tl', tr
tos
ton
t LP
tCL
t LC
tpo
t LSB
t LCL
tsp
t CLP
tPL
tpn
Conditions
MIN.
CL=30pF
15
60
ps
ps
ps
ps
ps
ps
0
0
1
1
CL=900pF,
. RL =20kO
Note
7
8
8
RL=20kO
~r--+--"l-""'''''
.-
LZll16AD 1 ___
I
GND
)I
HV(-300VI
CL=900pF
(Vcc=OV, f=IMHz, Ta=25"C)
Capacitance
•
250
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
125
60
60
150
0
0
Input signal conditions:
Input pulse level: -2.0 to -0.8V
Input rise/fall time: 20 ns
Time measurement level: 50%
Parameter
Input capacitance
Output capacitance
MAX.
. 4
Note 7: Applied to data output pins.
Note 8: Appiled to high voltage output pins; test circuit is as follows.
•
TYP.
Symbol
CIN
Cnvo
Conditions
VIN=OV
Vnvo=OV
MIN.
T¥P.
6
17
MAX.
10
30
Unit
pF
pF
AC Timing Diagram
CLOCK
LS
-~l-<--
STB
CL -
t LSB
~-------------tsp------------~~
__________-JI1-'--------------tCLP------"'·~·-;.ll
I~----
PL
HV08
.
~
___________
..
~''7 %
1_0_%_o_.____________________--J~
.-....-------~--SHARP--".---------
820
High Voltage MOS IC
LZ1132AM
LZl132AM
•
High Voltage MOS
•
Description
Ie
Pin Connections
The LZ1132AM is a high voltage (300V) 32-output-port monolithic Ie fabricated using Sharp's advanced P-channel DMOS process. It can be used as a
matrix driver for electroluminescent panels, plasma
display panels, electrostatic printers.
•
•
Features
1. High voltage output 300V (MIN.)
2. Output current 30mA (TYP. : VHVO = 300V)
3. Internal 32-bit shift register circuit
4. Expandable circuit structure
5. High speed data transfer (clock frequency
4MHz)
6. Single power supplJ! : - 5V
7. DMOS process
8. 44-pin quad-flat package
14
1
HV03
HV02
Top View
Block Diagram
Data
Output
High
Voltage
Output
Data
Input
Truth Table
DIN CL STB HVMOST
X
L
X
OFFX
L
H
ON
L
ON
H L
L
L
L
OFF
8
Latch Strobe
Strobe
Clear
-------------SHARP - - - - - - - - - - - . . -
821
LZ1132AM
High Voltage MOS IC
•
Absolute Maximum Ratings
Symbol
Parameter
SUpply voltage
Input voltage
Output voltage
Power consumption
Derating ratio
Operating temperature
Storage temperature
Note 1:
Note 2.:
Ndte 3:
•
Ratings
-7"':"+0.3
-7-+0.3
-7-+0.3
-300-"""0.3
-350-+0.3
600
5
-;-20-+70
-55-+150
Conditions
Applied to all input pins.
Applied to the data output
Ta~25"C
Ta>+25"C
Top;
TSt2
The maximum applicable voltage on any pin with respect to GND.
The maximum applicable voltage when HVMOST is ON. D (duty cycle)
The'maximum applicable voltage when HVMOST is OFF.
Unit
V
V
V
V
V
mW
mW/"C
"C
"C
Note
1
1
1
1,2
1,3
= 0.1 %, ON time = 10 ps
.
DC Characteristics
(1)
Symbol
ON -state resistance
RON
Output current
IHvo
Output
leakag~
current
Total output leakage current
Note 4:
Note 5:
Note 6:
(2)
(V ee =-5V±10%)
HVMOST Characteristics
Parameter
I IL I
I ITL I
Conditions
,
HVMOST "ON"
IHvo =-lmA, Ta=25"C
HVMOST "ON"
VHvo =-300V, Ta=25"C
HVMOST "OFF"
VHvo =-300V, Ta=-20-t70'C
HVMOST "OFF"
VHvo =-300V, Ta==20-70'C
MIN.
-20
TYP.
MAX.
Unit
1.3
n
-30
Note
rnA
4
10
/LA
5
30
pA
6
Duty cycle = 0.1 %, ON time = 10 ps
Value for each HVMOST outPllt pin.
Sum of total output leakage current.
(Vee=+5V±10%, Ta=-20-+70"C)
Logic Section Characteristics
Parameter
Supply voltage
Input high. voltage
Input low voltage
Output high voltage
Output low voltage.
Input leakage current
-
i
Vee
VIN
VOUT
VHVO(ON
iVHVo(OFF
Po
Symbol
Icc
VIH
VIL
VOH
VOL
IlL
Conditions
MIN.
-0.8
IOH=-0.2mA; applied to DouT
IOL = 1.6mA; applied to DouT
VIN=OV-Vee
TYP.
-8
VIN=OV
Veee
-0.5
MAX.
-16
0.3
-2.4
Unit
rnA
V
V
V
V
/LA
-2.5
10
j
---------------SHARP . - . - . - - - - - - . - . - .
822
High Voltage MOS
•
Ie
LZ1132AM
(Vcc=5V±1O%, Ta=-20-+70"C)
AC Characteristics
Parameter
Clock frequency
Clock pulse width
DIN setup time
DIN hold time
LS pulse width
Clock to LS delay
LS to clock delay
DouT delay
LS to STB delay
LS to CL delay
STB pulse width
CL pulse width
HVO fall time
HVO rise time
Symbol
Conditions
MIN.
TYP.
f~
MAX.
4
125
60
60
150
0
0
t", t"
tos
tOH
t LP
tCL
tLc
tpo
250
CL (DouT)=30pF
0
0
1
1
kSB
t LCL
tsp
tcLP
tPL
t pH
CL (HVO)=900pF, RL=20kO
CL (HVO)=900pF, RL =20kO
Note 7: Output delay time varies depending on load condition.
Test conditions:
Input pulse level: -2.0 to +0.8V
Input rise/fall time: 20 ns
Time measurement level: 50%
HVO output load conditions (figure at right).
15
600
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps'
ps
Note
7
HV (-300Vi
RI =20kO
HVO
LZl132AM
-----I
Tel
=900pF
7Ir
•
(VCC=OV, f=lMHz, Ta=25"C)
Capacitance
Parameter
Input capacitance
Output capacitance
Conditions
V1N=OV
VHVO=OV
Symbol
CIN
CHVO
MIN.
TYP.
6
17
MAX.
10
30
Unit
pF
pF
All pins except pin being measurement are counnected to GND.
•
AC Timing Diagram
CLOCK
LS
-<>+--+>- t LS B
STB
CL
~-------------tsp------------~~
_ _ _ _ _ _ _ _ _ _ _ _- J~-------------tCLP------------~~
I~
1
_______________
PL
,
HV032
~_O_?~______________________
7tPH90%
--J'
--------------SHARP------.---~
823
LR3461
Electroni'c Melody Generator CMOS LSI
'LR3461
Electronic Melody Generator CMOS LSI
•
•
Description
The LR3461 is a CMOS LSI with melodies and
alarm functions. It can be used in music boxes
and alarm sound generators.
Pin Connections
o
T3 2
NC
MH
ML
OSCIN
OSCoUT 4
•
Features
Melody with accompaniment
Mask ROM programmable
8 melodies (3-melody select inputs)
Loudness volume control function
Melody envelope controlled by external CR cir-,
cuit
6. CR controlled oscillation system (with external
resistor)
7. Single power supply: -1.5V
8. CMOS process
9. 22-pin\dual-in line package
MA
1.
2.
3.
4.
5.
•
NC
VDl)
SI
S02
SOl
EV2
EVI
T2
Top View
Block Diagram
1 Vss(OV)
0
OJ
~
.
"
-~
0
Q)
0-
.£
Q)
>
,::
~~
824
c.,
~
~
OJ
~~
" 6.
.. =
::;;0
-~
~
8
"S
Q,)
[go
8_
o .,
" >
""
<~
c
8'"
.~
~;;
o ""
,,~
"=
<0
""
1"S
.,.... """
8
~o-<
..., ..., '--v---'.
"'~
"0
=
""
o
Q)~
~o
~ ~ ~1j"
0 cu
..........
..
.,~
"0
0
....
::;;cii
"i"'ii
~(/J
Electronic Melody Generator CMOS LSI
•,
LR3461
Absolute Maximum Ratings
Parameter
Pin voltage * 1
Pin voltage * 2
Operating temperature
Storage temperature
Symbol
VTl
VT2
Topr
Tstg
Ratings
+0.3--3.0
+0.3-Voo-0.3
-10-+50
-20-+100
• 1:
• 2:
Applied to Voo pin. Referenced to Vss.
Applied to pins other than Vss and Voo. Refers to the Vss pin.
•
Recommended Operating Conditions
Parameter
Supply voltage
Ext. resistor for OSC
•
Specifications
-2.0--1.2
390±5%
(Ta=25"C)
Unit
V
kO
(VOO= -1.5V, Ta=25"C)
Electrical Characteristics
Parameter
Input voltage
Input current
Output current
,
Supply current
Note 1:
Note.2:
Note 3:
•
Symbol
VOOa
Rs
Unit
V
V
"C
"C
Symbol
VIH
VIL
IIH!
IIH2
IOHl
IOH2
IOL2
IOH3
IOL3
IOH4
IOL4
loos
100.
Test conditions
MIN.
-0.3
TYP.
MAX.
-1.2
VIH=OV
VIH=OV
VOH=-0.5V
VOH=-0.5V
VOL=-lV
VOH=-0.5V
VOL=-lV
VOH=-0.5V
VOL=-lV
Standby state with no load
Melody ON with no load
Applied to ST, SI,S3, and MA pins.
Applied to SI pin when melody is OFF.
Applied to EVI and EV2 pins.
Melody Specifications
2 channels
Note 4:
Note 5:
Note 6:
2
10
250
3
3
5
200
200
5
10
200
3
1
Unit
V
Note
1
pA
pA
pA
2
3
pA
4
pA
5
pA
6
pA
rnA
Applied to SO, and S02 pins.
Applied to ML pin; Iou is for melody OFF.
Applied to MH pin; IOL is for melody OFF.
length of notes is controlled with "1" and "0".
J=
J:i(1)+ J:i(0) ................................. 2 steps
J. =J:i(1)+J:i(0)+J:i(0) ...................... · 3 steps
)! = J:i (1)+
J! (0)
................................ 2 steps
Numbers given in parenthese provide envelope
control.
Note: given in parentheses are output only for
attack sounds.
Variable at 15 steps each (minimum
length of note is selectable between 31
and 468 ms.)
2 types (other types are made
available by controlling step
count.)
If the shortest note in a tune is J!, the two types
of note, J! and J:i, can be specified in a step. The
1 to 15 endless
(A single play with auto stop can be specified by
connecting the T3 input to Voo, overriding the num·
ber of repeated plays specified in ROM.)
(Command types) Melody command
Control commands
Jump command
Set Repeat Count command
End command
----~-.-----.---SHARP
--c
C
---------------825
_-_....- ............__
......
Electronic Melddy.Generator CMOS LSI
,.-_
CD'
, Main melody tones
Main melody envelope control
Accompaniment tones
Accompaniment envelope control
Length-of-note control
One of eight pieces of music is selected by the
status of the music select input S1 to S3. Since
these inputs are provided with pull-down resistors, they may be connected to Vss or be left open.
If the status of the music select input is changed
during play! the newly selected piece of music will
be played from the beginning at that point.
LR3461(A version of the LR3461 into which
the following pieces of music have been written in
at Sharp:)
H:
Music
S2 S3
H H For Elise
H H Lorelei
L H The Smith in the Village
L H Romance of Love
H L Sakura Sakura
H L Annie Rolley
L L Green Sleeves
L L Cuckoo
Vss,~: VDD
LR3461
'
S1
H
L
H
L
H
L
H
L
.._....,....,
:.-.,.
Remarks
Beethoven
German song
Japanese children's song
Spanish song
Japanese old folk song
Scottish song
English fork song
German song
One shot type (repeat 1-15 times)
Start input ST
-1'l'--____-.-...n..____
Mode input MA
------------L.J
Melody output ON
OFF
Auto stop
®
Hold type (repeat -1-15 times)
S tart input S T
Mode input
MA _ _ _ _ _ _ _ _ _ _ _ _ __
ON
Melody output
OFF
Auto stop
®
Forced stop
Hold type (endless)
Start input S T
--1
Mode input MA _ _ _ _ _ _ _ _ _ _ _ _ __
Melody output ON
OFF
--1
/L-Forced stop
or open (specifies endless for all the
pieces.)
•
System Configuration
o
LR34611
33pF
+
Forced stop
Tn: 2SC1383
Trz: 2SA683
826
\
Electronic Melody Generator CMOS LSI
LR3462
•
LR3462
Electronic Melody Generator CMOS LSI
•
Description
Pin Connections
The LR3462 is a CMOS LSI with melodies and
alarm function.
S,
S2
•
0
S3
Features
MA
OSCOUT
T,
1. Mask ROM programmable
2.8 melodies (3-melody select input)
3. Capable of driving piezo-electric buzzer
4. CR controlled oscillation system (with external
resistor)
5. Single power supply: -1.5V
6. I8-pin dual-in-line package
ST
OSCIN
Vss
T3
T2
VDD
NC
NC
NC
so
so
NC
Top View
•
Block Diagram
Oscillator
Circuit
Programable
Counter
Tempo
Control
Circuit
Melody
Generator
Melody Output
Control Circuit
Melody Control
Jump, Repeat
Start, Stop
. - . - . - - - - - - S H A R P - - - - - - . - .......... ....,..----..
827
. LR3462
Electric Melody Generator CMOS LSI
•
Absolute Maximum Ratings
Parameter
Pin voltage
Pin voltage
Operating temperature
Storage temperature
Symbol
VTl
VT2
T~Dr
TSt2
Unit
V
V
"C
"C
Ratings
-0.3-+0.3
VTI -0.3-+0.3
-10-+50
-55-+150
Note
1,3
2,3
Note 1: Applied to VDD pin.
Note 2: Applied to pins except Vss, VDD.
Note 3: Referenced to Vss.
•
(Ta=25"C)
Recommended Operating Conditions
Parameter
Supply voltage
Oscillator frequency
SYJJ.lbol
Voo
fose
MIN.
-2
TYP.
MAX.
-1.2
33
Unit
V
kHz
Note
4
Note 4: The variable resistance Rsexternally attached between pins 15 and 16 varies between 0,1MO. When variance in the oscillation frequency between pins is permitted, use a fixed
resistance Rs =680kO ± 5%. (Note that when measuring the OSC OUT signal, variations in
the oscillation frequency may be caused by theinput impedance of the measuring device.)
•
(V oo =-1.5V, Ta=25"C)
Electrical Characteristics
Parameter
Input voltage
Input current
Output current
. Current consumption
Note 5:
Note 6:
Symbol
VIH
VIL
ITH
IOH
IOL
I~os
Ioo.
Conditions
VIH=OV
VoH =-0.5V
VOL=Voo+0.5V
Standby, no·load
Merody ON, no-load
TYP.
2
MAX.
-1.2
10
800
800
Unit
Note
V
5
pA
pA
3
1
6
pA
mA
Applied to pins ST, g, S2, S3, MA
Applied to pins SO, SO
------~----SHARP
828
MIN.
-0.3
---.-.--------.-
Electric Melody Generator CMOS LSI
•
LR3462
Melody Specifications
Max. 8
600 steps
1 sequence
2.5 octaves
15 steps each (select
mlllimum note length
between 31 and 468
ms)
2 types (lengths other
than these are realized
by the number of steps)
Example: When the longest note in the melody
is p, the two types of notes that can be specified for one step are ) and P. The length
of notes is controlled using "1" and "0".
J = P (1) + P (0) .................... 2 steps
J. = P (1) + P (0) + P (0) .......... 3 steps
Po = P (1) + }l (0) ..................... 7 steps
value in parentheses ( ) : envelope control
1 to 15 or endless (by con
necting the T 3 input to V DD, the melody can
be set to play once and then turn off automatically.)
Melody commands
Jump command
Con t ro I
.
d
TImes repeat command
comman s
End command
One of the eight melodies is
selected depending on the state of the melody
selection inputs Sl-S3. The melody selection
input pins have a built-in pull-down resistance, so they can be connected to Vss or used
open. When the state of the melody selection
inputs changes during play, the melody specified is played from the first.
-E
(1 ) One shot type (repeats 1 to 15 times)
Start input ST
.....In'-_____
~_ _ _ _ _ _ _ _ _
Mode input MA
Melody output ON
OFF
I
---.I
/'
Auto stop
(2)
/'
L
Forced stop
Hold type (repeats 1 to 15 times)
S tart input S T
Mode input MA
ON
Melody output
OFF
(3)
,------,
I
-.J
Auto stop
Hold type (repeats indefinitely)
S tart input S T
Mode input
Melody output
/I'
/'
L
Forced stop
~
L
MA
ON
OFF
L
r-------------~
'~
/
Forced stop
---.-----SHARP--------~
829
Electric Melody Generator CMOS L_SI
•
LR3462
System Configuration
!
LR3462
o
•
LR3462! (LSI with melodies written by Sharp)
Sl
H
L
H
L
H
L
H
L
H: High, L: Low
8~O
S2
H
H
L
L
H
H
L
L
Ss
H
H
H
H
L
L
L
L
Melody
When the Saints Go Marching in
Twinkle Twincle Little Star
Bridal March
Silent Night
Sole Mio
For Elise
Wedding March
Jingle Bells
o
LR3681
Voice Synthesizer CMOS LSI
LR3681
Voice Synthesizer CMOS, LSI
•
Description
The LR3681 is a voice synthesizer CMOS LSI.
The integration of all the functions required for
generating voice output enables voice synthesizer
'systems to be easily composed.
•
Pin Connections
~
08
gg~~S:g~22
...l
2 DAI
NC
•
Features
1. Voice output period of time: 4 - 5sec
(The voice quality is determined by the length
of voice generated)
2. Available sound sources include male, female
voices and effect sounds
3. Voice synthesis method is based on a waveform encoding system
4. 32K bits of data ROM on chip
5. Expandable up to 128K bits of external ROM
6. Internal 8-bit of DI A converter
7. Time base: 4.19MHz crystal
8. Single power supply: - 3V
9. CMOS process
10. 48-pin quad-flat package
•
5
6
7
ggg888~88
Top View
Block Diagram
y
Address Output for Interface
to External ROM
Data Input
Control
Output
.
Output
Input
831
LR3681
Voice Synthesiz9>r CMOS LSI
•
Absolute Maximum Ratings
Perameter
Pin voltage 1,
Symbol
Ratings
Unit
Voo
-6.0-+0.3
V
Pin voltage 2
VIN
Voo-0.3-+0.3
Operating temperature
Top'.
-20-+70
V
°C
Storage temperature
Tstg
-55-+150
°C
Note
1
The maximum applicable voltage on ~in with respect to Vss.
Note 1: Applied to pins NrN g• CEo POW. DAIo DA 2• OSC'N. OSCOUT• EO,-EO g• AOI-AOs•
, BO I-B06 • and CO I -C06 •
'
•
Recommended Operating Conditions
Parameter
Unit
Symbol
Specifications
Supply voltage
Voo
-,2.7--3.3
V
Oscillator frequency
fose
4.1943 (TYP.)
MHz
•
Electrical Characteristics
Parameter
Input voltage
IIlPut current
Output current
(Voo=-3.0V, Ta=25t)
Symbol
Conditions
MIN.
VIL
Voo+0.6
IlHl
VlN=OV
2
30
VlN=OV
2
30
hH3
VlN=OV
IOHI
VouT=-0.5V
lOLl
VOUT=Voo+0.5V
10HZ
VouT=-0.5V
100
IOL2
VouT=Voo+0.5V
100
3
100
,100
8
Rf open
6
1
Max. output voltage amplitude
Vpp
Rf= 20kO,C=100pF.Rf= 20kO
Oscillation start time
Tose
Voo=-2.7--3.3V
Note
, Note
Note
Note
Note
Note
Note
Note
2:
3:
4:
5:
6:
7:
8:
9:
Note 10:
Note 11:
Note 12:
832
MAX.
11H2
Of A converter bits
Of A converter monotonicity
Current consumption
TYP.
-0.6
VlH
Itot••
During region-wide operation
During standby
Applied to .pins ACL, Nl - N4, and EOI - E08.
Applied to pins NI - N8.
Applied to pins EOI - E08.
Applied to the ACL pin. ,
Applied to pins AOI - A08, BOI - B06, and COl - C06.
Applied to pinsCE and ROW.
Applied to the built-in DA converter.
Applied to pin DA2, with resistor Rf connected to pins
DAI and DA2 left open.
Applid to pin DAI. The difference in the output voltages at DAI,VOAI (00) and VOAI (FF), obtained when
the input data to DI A converter is 00 and FF, respectively is: VDAI (OO)-VDAI (FF)=Vp-p (where Rf=20
Kno1)_
Applied to pins OSCIN and OSCOUT (Co = CG = 5 pF).
Refers to the time required for the LSI to enter the region-wide operating status (POW rises) from the rising
edge 'of the N2 pin under standby status,
Measurement circuit
1.7
1.5
V
2
pA
pA
pA
4
pA
6
pA
7
bit
8
9
Vss
4.l9,4~MHz ceramic oscillator
CG=C D=5pF
'
3
5
V
10
ms
11
mA
1
Crystal :
Note
bit
50
kENO
Unit
pA
12
LR3681
Voice Synthesizer CMOS LSI
•
System Configuration
(1) Stand-alone LSI configuration
Pressing one, out of the eight switches (N.-NB)
connected to the input pins, produces the corresponding speech message. The number of connectable switches can be increased to 32 by building a
matrix with the output pins.
The voice output's maximum amplitude is almost
equal to the supply voltage. It is amplified by a
power amplifier to drive a speaker. A simple lowpass filter (CR network, etc.) should be used to eliminate RF noise.
I
Strobe
(2) System combined with a microcomputer
A microcomputer mllY be used to command the
voice synthesizer LSI to produce a specific speech
message. The device can be readily interfaced
with the CMOS version of the SM Series.
Data transfer
SM-500
LCD panel
Control !--=s"'ign=al:;:.s_ _--t N,
output
N2
Start/Stop
signals
Key input
BUSY signal
The following figure shows a sample system
configuration in which serial data is transferred
from the SM-500 to pin Nt of the device:
ACL
OINOOUT
LR3681
DA,
Control signals
Note N2: Starts in the standby mode.
~---'-'---"""'-~SHARP----~'-'-'---
833
Voice Synthesizer CMOS LSI
LR3681
..........~~........... . -__,._~............ - ....... - ...........-..r.....
•
Developing Procedure
The following table shows a typical procedure for developing the LR3681 with customized specifications:
Description
Responsible Party
Determines the 1/0 formats for the LSI, interface with microcomputer, etc.
Customer
Selects the tone from the samples provided by Sharp.
CustQmer
Determination of speech Specifies the words to be written into the device, extracts common words, Customer
3
message
and creates the recording manuscript.
Sharp
As a rule, a professional announcer records the contents of the recording
4 Recording
Customer
manuscript onto a tape, in a noise· free environment.
Checks the recorded tape for noise arid proper recording level. If any pro.b·
Sharp
5 Recorded tape check
lem is found, Sharp requests the customer to. reco.rd once again.
Inputs the recorded message into. a computer, where it is subjected to voice
Sharp
6 Voice analysis
analysis and data co.mpression for writing into ROM.
Writes the resulti"ng voice data into PROM, and programs the control sec·
Sharp
7 ROM writing
tion for lIO and other operations.
Emulation for voice tone Emulates the PROM co.ntaining data to evaluate the tone of the recorded
Customer
8
voice as well as the systems operations.
and LSI functions
If the result of emulation was positive, Sharp creates the mask for LSI
9 LSI mask generation
Sharp
device.
10 TS submission
Fabricates test sample devices, tests them, and submits them to the customer.
Sharp
11 TS evaluatio.n
Custo.mer evaluates the sample devices.
Customer
12 ES submission
Sharp submits engineering samples.
Sharp
Parameter
1 System specs
2 Synthesized voice ·tone
834
5 X 7 Dot Matrix Decoder PMOS LSI
LI2048
•
LI2048
5 X 7 Dot Matrix Decoder PMOS LSI
•
Description
Pin Connections
The LI2048 is a PMOS LSI capable of driving 5
X 7 dot-matrix vacuum-fluorescent displays, and
displaying 128 kinds of pattern.
•
1.
2.
3.
4.
5.
Features
128 patterns display
Direct drive of vacuum-fluorescent displays
Printer drive output
TTL level voltage drive
60-pin quad-flat package
3
~~~~JJ;~J6gJgg6
Top View
•
Block Diagram
Dot Select Input
GND
~
Dot
Display
Output
Display/ Print S2r----....J
Select Input
.
Dot Display Output
835
....
.......---,...-..
....
5X7.D0t Matrix Decoder
.-.~....,
•
.LI2048
-~....,~---~--~
Absolute Maximum Ratings
Parameter
Pin voltage *
Symbol
Voo
VN
.'VlIl,
Operating temperature'
Storage temperature
Topr
Ts...
, *Referenced to GND.
•
Ratings
-20-+0.3
-44-+0.3
.,-44-+0.3
-5-+55
-55-+150
Unit
V
V
V
t
t
Recommeded Operating Conditions
Parameter
Supply voltage
Display voltage
•
Symbol
Voo
VN
Ratings
-8.1--9.9
-40
Unit
V
V
Electrical Characteristics
Parameter
Input voltage
Output voltage
Current consumption
Output delay time
Symbol
VIH
V1L
VOHl
VOH2
VOL
100
IN
tUl
tdl
tU2
td2
Input resistance
•
RIN
Conditions
TYP.
MAX.
-4.2
IOH=3.0mA
IoH =1.0mA
VIN =-40V
Voo =-9.0V
VN=-40V
V1N =-40V
No loading
VN=-40V
Loading capacity; 100pF.
VIN =-40V
Function
(1 ) Dot matrix arrangement
~ ~ ~ ~ ~
@;) ~ ~ @;] ~
~ @;] ~ @;J @;]
@;] ~ @;J ~ ~
~ ~ ~ @;] ~
~ '~ ~ @;] @;]
,,'@;] ~ @;) [£;J @;J
836,
MIN.
-1.1
-1.0
-1.0
Unit
V
V
-36.5
8.5
3.0
4.0
5.5
5.0
15.0
1.0
rnA
ps
MO
5X7 Dot Matrix Decoder
(2)
Ll2048
Dot data output
For low CE l and CE 2 inputs.
Dot data output is determined by input Ao
-A6 •
(ii) For low CE l and high CE 2 inputs.
Dot data determined by input Ao - A6 is
stored by input A 7 - Ag and outputted as
dot data output Dil (i = 1-7) to the
printer.
(iii) For high input CEl.
No dot data output.
(i)
Input
CEI
0
•
CE 2
1
D-'L
output
A7
As
A9
Dll
D21
D31
D41
DSI
DSI
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
Dll
D21
D31
D41
DSI
DSI
Dn
Dn
DI2
D22
D32
D42
DS2
DS2
D72
Dl3
D 23
D33
D43
DS3
DS3
D73
D14
D24
D34
D44
DS4
D64
D74
D I5
D 25
D35
D45
DS5
DS5
D75
No dot data output
System Configuration
5 x 7 dot matrix fluorescent tube display
e
Di ;
Dil (i=1-7)
Printer
=1-7)
j=I-5
Dot output
Ao
Input
Al
A2
A3
A.
As
A6
A7
As
A9
Vi-<
VDD
Ll2048
-40V
-9V
GND
Input
837
LH5008
LCD Controlier/D-riVer CMOS LSI
LH5008
•
LCD -Controller / Driver CMOS LSI
_Description
•
Pin Connections
The LH5008 is a programmable LCD controller!
driver which interfaces in serial fashion to the
CPU of a microcomputer application system to
directly control and drive LCDs in static operation
-or dynamic operation (1/2,113 or 1/4-duty cycle).
The LH500? incorporates a segment decoder for
_generating specific segment patterns, and is also
capable of controlling the blinking of the display.
•
Features
1. CMOS process
2. Number of display digits
. 7 -s~gment device
1I4-duty cycle ·········16 digits
1/3-duty cycle ......... 10% digits
112-duty cycle ......... 8 digits
Static operation········· 4 digits
• 14-segment-device
1I4-duty cycle
8 digits
3. Operating mode
Static, 112, 113, and 1I4-duty drive
4. Biasing
Static, 112 and 113
5. Segment decoder output
• 7 -segment device ; numerics 0 - 9 and 5
symbols-. 14-segment device; 36 alphanumerics and
12 symbols
6. Blinking function
7. LCD direct drive
8. Serial input (8-bit unit)
9. Capable of multi-chip configuration
10. Single power supply: + 5V
11. 60-pin quad-flat package
.-------------.---SHARP.,-.-.....-.-.-..-.~-
838
LCD Controller/Driver CMOS LSI
•
LH5008
Block Diagram
LCD
Segment Output
Synchronous
Signal Input
/Output
Segment
Output
Chip Select
Busy Output
Command/
Data Select
Reset
Input
•
GND
Serial
Serial
Clock Input Data Input
'-v---'
VDD
Pin Description
Pin name
VDD, Vss
VLCI> V LC2, V LC3
SI
SCK
CID
CS
RESET
CL l
CL 2
SO-S3l
COM o-COM 3
BUSY
SYNC
No. of pins
3
3
1
1
1
1
1
1
1
32
4
1
1
110
Connect to
Power supply
I
MPU
Resistance
Resistance
0
Liquid crystal
110
MPU
LH5008
Functions
Power supply for logic circuit
Power supply for liquid crystal drive
Serial data input
Clock input for data shift
Datal command select pin
Chip select pin
Reset input
Internal clock oscillation pin
Internal clock oscillation pin
Liquid crystal segment drive signal
Liquid crystal common drive signal
Busy output
Sync. signal
.---------SHARP-.--.-----------839
LCD'Controlier/Driver CMOS LSI
•
LHS008.
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
Note 1:
•
Symbol
Voo .
VIN
VOUT
' Topr
J'stg
Ratings
-0.3-+7.0
~0.3-Voo+0.3
-0.3-V oo +0.3
-10-,+70
-55-'+150
Unit
V
V
V
"C
"C
Note
1
Referenced to Vss.
Recommend Operating Conditions
Parameter
Supply. voltage
Symbol
Voo
Oscillator frequency
fose
•
Conditions
MIN.
2.7
R=200kn, Voo =5V±10%
R=240kn, Voo =3V±10%
Input voltage ,
Input leakage current
Output leakage current
Output current
Output resistance
Current consumption
MAX.
5.5
Unit
V
130
100
kHz
(V oo =,5V±IO%, Ta=-10-70"C)
DC Characteristics
Parameter
TYP.
Symbol
VIH
V1L
I ILIH I
I ILIL I
I IWH I
I IWL I
IOHl
IOH2
lOLl
IOL2
RCOM
RSEG
100
Conditions
VIN=Voo
VIN=OV
VOUT = Voo
VOUT=OV
SYNC; BUSY
SYNC,
SYNC,
BUSY,
COM o-COM 3
VOUT=VDD-O.5V
VouT=lV
VouT=lV
VouT=0.5V
VOO: external clock
CLl> external clock
MIN.
50
85
2
2
900
400
400
0
250
200
TYP.
130
MAX.
200
175
16
16
Unit
kHz
kHz
fiS
fiS
ns
ns
ns
ns
ns
ns
Load capacitance = 50 pF
Load capacitance - 50 pF
3
1.5
fiS
fiS
fiS
fiS
fiS
fis
fis
50
pF
9
1
1
8tcyc *
8tcyc *
tcyC * =5 fiS
tcvc=lIfc
(Voo=2.7V-4.5V, Ta=-10-70'C)
Parameter
Operating frequency
Oscillator frequency
High-level clock pulse width
Low-level clock pulse width
SCK frequency
High-level SCK pluse width
Low-level SCK pluse width
BUSY t -+SCK hold time
SI setup time (to SCK t )
SI hold time (to SCK f )
Delay of 8th SCK f -+BUSY l
CS l-+BUSY l delay
C/D setup time (to 8th SCK t )
C/D hold time (to 8th SCK t )
CS hold time (to 8th SCK t )
High-levellCS pluse width
Low-levellCS pluse width
SYNC load capacitance
*
Symbol
fc
fosc
tWHC
tWLC
tcYK
tWHK
tWLK
tHBK
tsIK
tHKI
tOKB
tncSB
tsoK
tHKO
t HKCS
tWHCS
t WLCS
CLSY
Conditions
R=240kO±5% Voo =3V±10%
CLl> external clock
CLl> external clock
MIN.
50
50
3
3
4
1.8
1.8
0
1
1
Load capacitance=50 pF
Load capacitance=50 pF
TYP.
100
MAX.
140
140
16
16
fiS
ps
fis
ps
ps
ns
5
5
18
1
1
8tcyc *
8tcyc *
tCYC * =6.25 fiS
Unit
kHz
kHz
50
ps
fiS
fiS
ps
fiS
ps
ps
ps
ps
pF
tcyc= lIfc
841
LCD Controller/Driver CMOS LSI
u:iS008
AC Timing Diagram
•
Timing measurement voltage level
X
.
______- J
O.7VDD?/. O.3VDD _
./O. 7VDD
X···
I/ --......,..O.3VDD _
Measurement points
_
~------
Timing waveforms
t----tCyC (I/fc)--~
tWHCS
~-------------------tWLCS-------~------------~
tDCSB
- tHKCS
----.
I
\
O.5V
\
I
I
r----'
\
\
\
------.1.-
SI
eli)
________
~~~_______________t_S_DK---------~~~~------
*1: Voo-O.5V at Voo=5V±10%. Voo-O.75V at Voo=2.7-4.5V
* 2: O.8Voo at Voo=2.7-4.5V
* 3: O.2Voo at Voo=2.7-4.5V
842
LCD Controller/Driver CMOS LSI
•
LH5008
System Configuration
,
~ COMo -COM3
7-segment I6-column LCD
rV
50-531
{').
COMo-COM3
r-----------,
I
I
50-531
VDD
*CI
RESET
VLCI
LH5008
:: C2
51
::C3
VLC3
Ii"
SCK
CLI
CL2
I
I
: RESET
C/i)
C/i)
CS
VLC2
R3
BUSY
BUSY
Vss
ICS
I
151
I
SCK
IL
Microcomputer system
I
I
I
I
I
I
I
I
I
__________ J
1
-----~.-..-;...-----SHARP----.----.-----
843
LR3691A
LCD Dot Matrix Controller CMOS LSI
LR3691A
•
LCD Dot .Matrix Controller CMOS LSI
Description
The LR3691A is a controller CMOS LSI for dot
matrix graphic LCD units. It stores display data
corresponding to dot patterns from the 8-bit CPU
in the external RAM. From this RAM, it transfers
the display data to the LCD driver and generates
clocks necessary to drive the LCD.
•
Features
1. Controller for LCD dot matrix graphic display
2. Maximum display data = 163, 840 dots
(Horizontal X Vertical)
3. General 8-bit CPU interface
4. High -speed write cycle
5. Low frequency due to parallel output of data to
4 divisions of the LCD
6. Selectable display dots
a. The number of horizontal dots
• The LCD without right and left divisions
120,160,240,320,480,640 dots
• The LCD with right and left divisions
240,320,480,640,960,1280 dots
b. The number of vertical dots
· The LCD without upper and lower divisions
32,64, 100, 128 dots
• The LCD with upper and lower divisions
64, 12~ 200, 256,do~
7. Single power supply: 5V (TYP.)
8. CMOS process
9. 60-pin quad-flat package
844
•
Pin Connections
LCD Dot Matrix Controller CMOS LSI
•
LR3691A
Block Diagram
Meory
Address
Output
Oscillation
LCD Control
Timing Generator
Memory
Address
Output
LCD AC Drive
Output
Display Data Shift
CLOCK
Display Data Latch
CLOCK
Common Data Output
Column Counter
Row Counter
CPU Address Counter
Test
Memory Data Bus
•
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
Note 1:
•
Symbol
Vee
VI
Vo
Topr
Tstg
Ratings
-0.3-+7
-0.3-Vee+0.3
-0.3-Vee+O.3
-10-+70
-55-+150
Unit
V
V
V
°C
°C
Note
1
1
1
The maximum applicable voltage on any pin with respect to GND.
Recommended Operating Conditions
Parameter
Supply voltage
Input voltage
Output low current
Output high current
Clock frequency
Note:
Symbol
Vee
VI
MIN.
4.5
0
10L
lOR
fose
0.6
TYP.
5.0
MAX.
5.5
Vee
4
-500
6.6
Unit
V
V
rnA
f-lA
MHz
Any current sinks into the LSI is regarded posititve.
845
LCD Dot Matrix Controller CMOS LSI
LR3691A
DC Characteristics
•
(Vcc=5V±10%,GND=OV, Ta=-10-+70t)
Parameter
Symbol
VaLl
Output low voltage
VOL2
VOH!
VOH2
VILI
Output high voltage
Input low voltage
MIN.
Conditions
IOL=4mA
IOL=400pA
IOH=-0.5mA
IOH=-400pA
Input high current
IIH
Current consmnption
Icc
2.4
Vcc-0.6
VIH = Vcc
fosc=6.6MHz
Note
Note
Note
Note
2: Applied to
3: Applied to
4: Applied to
5: Applied to
Note
1,2
V
3
1,2
V
V
3
2,4
V
V
5
2,4
V
5
4,5
2
2,4,5
-30
-100
20
pA
pA
pA
12
36
rnA
-20
VIL=OV
VIL=OV
MOo -M0 7 and 0 0 -0 7 are 110 pins which are pulled up by
built·in resistors when in input mode.
Note 1: Applied to output pins other than CP" CP2. S, M, 01,
-01,. and OSCOUT.
•
V
V
0.4
0.5
VIH2
Input low current
Unit
0.4
0.2Vcc
0.8Vcc
VIHI
IlL!
, IIL2
MAX.
2.4
,
VIL2
Input high voltage
TYP.
pins MOo-M0 7 and 0 0 -0 7 ,
pins CP" CP2. S, M. 01,-01 4 , and OSCOUT
input pins other than OSC'N, T, andT 2.
pins OSC'N, T .. and T 2.
AC Characteristics
(1)
LCD control timing
(Vcc=5V±10%, Ta=-10-+70t)
CP 2 clock width
tWCP2
Data setup time
Data hold time
tDIS
MIN.
;-50
,; -100
tDIH
;-100
tLc
tCLD
twCP!
20
20
2';-50
;/2
-(~/2+100
- ;12,
l)
tM
tsc
t)
tcs
Parameter
Clock setup time (CP! l -CP 2 l)
Clock setup time (CP 2 t -CPt f)
CPt clock width
Fall time of CP 1 referring to M signal
Clock setup time (CP! l - S
Clock setup time (CP! l - S
Rise time of CP! and CP 2
Fall time of CPt and CP2
Symbol
tr
tf
Measurement Conditions
~ =lIfosc(fosc=O.6-6.6MHz), CL=50pF. VOLc=O.2Vcc. VOHc=O.8Vcc
Dh-DI.
M
s
~46
TYP
MAX.
;
;
;
Unit
ns
ns
ns
;12+25
;12
2;
;
200
ns
ns
ns
ns
ns
200
30
30
50
ns
ns
50
ns
LCD Dot Matrix Controller CMOS LSI
(2)
LR3691A
(Vee
RAM interface timing
= 5V ± 10%. Ta =
-10 - +70t)
Symbol
MIN.
TYP.
MAX.
Unit
Address output cycle time
tAC
tMRS
2s6
30
2s6 +50
100
ns
MRD setup time (to address)
Read data setup time
tDRS
2 s6 -50
0
180
Read data hold time
Memory write pulse width
tDRH
tMWW
Write recovery time
tDMW
Parameter
Write data output delay time (to MRD
t)
tDDW
Write data setup time
tDWS
Write data hold time
tDWH
MRD time from write data (Hz)
tDWZ
ns
ns
15
s6 -50
2 s6 -150
s6 -100
s6 -100
s6 -100
s6 -100
ns
s6
2s6
s6
s6
s6
s6
ns
ns
ns
ns
ns
ns
Measurement Conditions
; =lIfosc(fosc=0.6-6.6MHz). CL=20pF. VOL=0.8V. VOH=2.0V. VIL=0.8V. VIH=2.0V. and hand tr of input signal are less than 50 ns.
MAo-MAi.
MDo-MD7 (READ)
MDo-MD7 (WRITE)
(3)
(Vee
CPU interface (read cycle) timing
Parameter
Symbol
WAIT output time referring to RD
tRDWT
WAIT rise time referring to MRD
tWURD
Data output delay time referring to RD
tRDHZ
Data output settling time referring to WAIT
t
Data output hold time referring to RD
RD setup time referring to MA
Measurement Conditions
; = l/fosc(fosc=0.6-6.6MHz). CL=ZOpF. VOL=0.8V. VOH=2.0V.
tWTS
tRDH
tASRD
VIL=O.~V.
= 5V ±
MIN.
s6 -100
2 s6 -150
0
200
10%. Ta
=
-10 - +70t)
TYP.
MAX.
Unit
45
s6
25
2s6
20
150
ns
ns
150
ns
ns
ns
ns
VIH=2.0V. and hand tr of input signal are less than 50 ns.
MAo-MAl'
h~-----.lVOH
~~~______~~V~OL~-------------------
----'----SHARp.-.---.-.----.--..
847
LR3691A·
LCD Dot Matrix Controller CMOS LSI
(4)
(Vee = 5V ± 10%. Ta = -10 - +70"C)
CPU interface (read cycle) timing
,Paramerter
WAIT rise time referring to MRD
Data setup time referring to MWR
Data hold time referring to MWR
WR setup time referring to MRD
WAIT output time referring to WR
Symbol
tWUWR
tDSMW
tDHMW
tASWR
tWRWT'
MIN.
TYP.
1> -100
1>
1> -50
1>
1> -50
1>
Mj~.x.
200
45
150
Unit
ns
ns
ns
ns
ns
Measurement Conditions
1> = 1/fosc(fosc=0.6-6.6MHz). CL=20pF. VOL,=0.8V. VOH=2.0V. VIL=0.8V. VIH=2.0V. and hand teof input signal are less than 50 ns.
MAo-MA14
~_ _ _ _ _ _ _ _ _ _
MRD
•
VOH
>CJC
VOL
Functional Descriptions
(1) Power supply
The Vee pin requires + 5 VDC to the ground.
The GND pin should be externally grounded.
(2) Clock pulse and divider
The OSCIN pin of the device requires constant
application of a clock. A clock used for the CPU
may be used for this purpose. The OSCOUT pin,
which provides an inverse of the clock applied to
the OSCIN pin, should be left open.
(3) RES pin and reset pulse
The RES pin requires application of a reset
pulse when power is turned ON to initialize the
LR3691A's internal registers. The reset pulse
should be active high, and should have a pulse
width more than 4 time as long as that of the clock
"
pulse.
The input circuit for the RES pin uses a floating
gate.
(4) Data control pins
The LR3691A is controlled from the host CPU
through pins CS, .RD, WR,.and RS, The signals ap·
plied to pins RD, WR, and RS are made valid if the
CS pin is set to low.
The RD and.WR pins are used to determine the
direction of data transfer between the display RAM
and CPU.
The RS pin specifies the type of data exchanged
with the CPU through pins Do-D7, identifying dis·
play RAM address specification data and display
data.
The data control pin signal timing is' shown in
the paragraph for Electrical Characteristics.
The input circuit for these control pins have
floating gates.
(5) WAIT signal
The display RAM is accessed from both the CPU
and the LCD driver. To avoid contention, the
LR3691A delivers a WAIT signal to its WAIT pin
when the LCD driver is accessing the display
RAM, suspending display RAM access from the
CPU.
(6) Data input/output
The LR3691A exchanges data with its host CPU
through its pins Do-D7. The data transferred
through these pins are display RAM address data,
display RAM read data, and display RAM write
data. The data type is specified by controlling a
data control pin. The Do-Di pins are. normally connected to the host CPU's data bus. When in the input mode, the Do-D7 pins are pulled up through
pull·up resistors.
-------~------SHARP.-.-.--~---~-
848
LCD Dot Matrix Controller CMOS LSI
LR3691A
(7) Screen division and dot number selection
The LR3691A controls an LCD screen through
LCD drivers using serial data transfer scheme
with duty cycle of 1/32 to 1/128. The LCD
screen is often divided into sections to improve
contrast and reduce driving frequency and driving
voltage.
The LR3691A permits division of the LCD
screen into two sections both in the horizontal and
vertical directions. The ROWand CLM pins have
floating gate inputs with high impedance.
(8) Connection to display RAM
'The LR3691A should be connected to the dis·
play RAM as follows: The address data for display
RAM is output through pins MA o-MA 14 • If th~
display RAM consists of more than one chip, the
address data shoud be decoded through an address
decoder before being coupled to the display RAM.
Display dat.? is transferred through pins MDo'
MD 7 • The MRD and MWR pins are used to control the display RAM: the MAD pin provides a display RAM read command signal; the MWR pin provides a display RAM write command signal.'
(9) Display screen versus display RAM
The display RAM is accessed from the CPU or
LCD driver via the LR3691A. Access from the
LCD driver occurs every 32 cycles of the system
clock (applied to the OSCIN pin), of which one 16
cycle period is occupied by the LCD driver, and
the remaining 16 cycle period is available to the
o0 0 0 H
o0 0 I H
o0 0 2 H
o0 0 3 H
4 0 0 I
H
,4003
H
80 00
H
8.0 0 I
H
OOOOH
I
(OOOOH) (OOOh) I
0028HJ0029H I
(OOOFH) (OOIOHU
loooh
OOOh
(0002 H)
002AH
(OOI1H)
8000H
(8000H)
802 S.
(800FH)
800lH
(800h)
80219' H
(80IOH)
8002H
(8002H)
802 A H
(8011H)
. CPU. Display data is written and read byte-bybyte (8 bits). When viewed from the CPU, display
RAM address alllocations to the display screen
address are fixed. (To facilitate data readl
write access to the display RAM and to impove
availability of the RAM area, RAM addresses
are actually translated within the LR3691A before read Iwrite access is performed.) The first
addresses of the four sections on the screen are
fixed to OOOOH, 4000H, 8000H, and COOOH. An
example of the relationship between display RAM
addresses and screen addresses as viewed from
the CPU is shown in Fig. 1, where the number of
pixels per row on the screen is 640 (numbers
given in parentheses are that of 240).
00) LCD driver control
The LR3691A drives an LCD dot matrix display panel via LCD drivers using serial data transfer scheme. It uses its pins S, M, CPI CP2, and DII
-DI4 for controlling the LCD driver.
The S pin provides data signal to the shift register input of the LCD driver which drives the common electrodes. The M pin supplies a signal
needed for synchronized AC driving of the LCD
driver.
The CP2 pin drlivers a clock signal used to shift
display data. The CPI pin provides a display data
latch signal. The pins DII: -DI4 otuput display data
after converting the 8-bit parallel data from the
display RAM into serial data.
- - - - ----!-=:::=:!~Ti'i:T+-':-~;;"'-I__';';;7;'''+-
--
I!
I
8027 H
(800EH)
I
I
I
1
I co 1
I
COOOH
( COOOH)
C028 H
( COOFH)
CO 0 I H
(COOl H)
02H
(C002H)
I
-
~
~~_---
C027H
(COOEH)
C029 HI C02AH,
(COIOH) (COlh)
I
I
I
I
I
I
I
CO 0
CO 0
COO
COO
0
I
2
3
H
H
H
H
I
( a)
Memory map viewed from CPU
(Note)
Number of pixels per row is 640. (numbers given in ( ) are that of 240)
( b)
Display viewed from CPU
Fig. 1 Relationship between display RAM map and
display screen as accessed from the CPU
849
lR3691A
LCD Dot Matrix Controller CMOS LSI
0000.
000 1 •
0002 •
0003 •
0004.
0005.
0'006.
0007 •
0008 •
I
I
1
1
1
'I
1
I
(b)
( a)
Actual display screen
Actual memory map
Fig. 2
Actu~1
relationship beween display RAM map and display screen
Display screen
Display RAM
/
Fig. 3
Bit-by-bit relationship of display screen and display RAM
The Dh pin provides display data for the upper
left section of the display screen; the DIz pin pro,
vides that for the upper right section of the screen;
the Db pin provides that for the lower left section;
and the DI4 pin provides that for the lower right
section.
The LCD driver control singnal timing is shown
in the paragraph describing Electrical Characteristics.
(11) DIsplay enable
The DE pin is used to enable or disable display
to the screen. If set at low, the entire screen is
blanked. Data display is enabled only when the DE
pin is set at high. The DE pin is used to suppress
meaningless information from the screen pO,wer is
being turned on. It has a floating gate input.
(12) T1 and T2 pins
The T 1 and T2 pins should be connected to the
ground. These pins, having floating gate inputs,
are used for device test and are not available to
the user.
•
Display Control Method
Display control consists of display data processing, RAM addressing, and display screen selection.
(1) Display screen selection
The LR3961A drives the display screen via
shift·register type LCD drivers by, if necessary,
dividing the screen into four sections according to
the number of pixels (on the row and column) to be
displayed. The number of pixels per row is specified with the CLMo-CLM2 pins. The number of
pixels per column (duty) is specified with the
ROW 0 and ROW 1 pins. See the following table.
eLM
No. of pixels
ROW
No. of pixels
(2.1,0)
000
001
010
011
100
101
110
111
per row
(1,0)
00
01
10
11
per column
120
160
240
320
480
640
32
64
100
128
unused
unused
I
.----~--~.-.--SH.A.RP
850
, - . . - - ......... -----~-------
LCD Dot Matrix Controller CMOS LSI
If the screen is divided into two half sections
(left and right), the displayable number of pixels
becomes twice the numbers shown in the above left
table. If the screen is divided into upper and lower
, halves, the displayable number of pixels becomes
twice the numbers shown in the below-right table
on page 850.
To prevent flicker of the display image, the total
number of pixels per section should be limited to
40,960 of total pixels/divided screens.
(2) Display RAM address control
The addresses for the display RAM are
apparently specified with 15-bit address data,
whose output is implemented through pins
MAo-MA14. Meanwhile, the host CPU uses an
8-bit bus, Do-D7, to address the display RAM. To
specify a full 15-bit address, the CPU must transfer address data in two consecutive sequences:
first the lower byte, and next the upper byte. At
this time the RS pin (address specification) should
be set to '1'. Once a display RAM address is specified, it is automatically incremented each time the
CPU accesses it for read or write operation. So for
display RAM addresses which are consecutive can
be accessed by setting only the first address.
LR3691A
Address data is transferred in two consecutive
sequences for upper and lower bytes.
(3) Data write into display RAM
Data can be written into the specified display
RAM location. Specification is conducted by the
RAM address counter through the Do-D7 pins
when the RS is set at zero.
Once data is written, the RAM address counter
is automatically incremented, so that data may be
written consecutively.
(4) Data read from display RAM
Data can be read out of the display RAM location specified by the RAM address counter. Specification is implemented through the Do-D7 pins
when the RS is set at zero.
Once data is read, the RAM address counter is
automatically incremented.
851
•
!R
~I
I
I II,
J
CPU
-I
(Z80 system)
I
I
I
~J
\ Address Bus
, I I [:,
rl+
CL2 CLI M FCS~
IPS'
LH5021A
/LH5022 Dil ---
5V
1"1" 1"1"
"lJ
Y.O-YI
II-II
N
'D
I
I
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I
I
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CLz CLI M FCS ~
LH5021A IPS
/LH5022 OIl
FCS/PS DII
LH5021A
M /LH5022Y
CLI
I
Y.UI
RD
WR RS CS DE
CP I 1---0-1+--1-+-1---4
WAIT
~
CP2
M
Do- D7
,
LR3691A
MAo- MA14
~--~~
I,
III
Y.O-YI
u
w
,
if
o
YSO-YI
Y.O-YI
LH5021A
LH5021A
ILH5022 0 I 1 - DO ILH5022, OIl
FCS
FCS
CL2 CLI MIPS
CL2 CLI MIPS
I
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fr
YSO-Yl
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o
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I - - - - - - - - -, - - - - - / - LCD panel-- - - - - - - - - - - - - - -
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U
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LR3692
LCD Dot Matrix Controller CMOS LSI
LR3692
•
LCD Dot Matrix Controller CMOS LSI
Description
•
Pin Connections
The LR3692 is a controller LSI for dot matrix
graphic LCD unit. It stores display data transferred from 8-bit microcomputer in the external RAM
and generates LCD drive signal suitable as serial
type LCD driver.
Selectable from graphic mode and character
mode using character ROM for character display.
•
Features
1. Graphic or character mode selectable
2. Display duty: 1132 - 1/256
3. Maximum display capability
Graphic mode : 640 X 256 dots
Character mode: 80 X 32 characters
(if character font is 8 X 8)
4. Capable of interfacing to an 8-bit CPU
5. Serial! 4-bit parallel output
6. Capable of driving upper and lower divisions
LCD
7. Scroll function
8. Cursor display: ON, OFF, and BLINK
9. Character BLINK
10. Display ON, OFF
11. On -chip crystal oscillator
12. Single power supply: 5V (TYP.)
13. CMOS process
14. 80-pin quad-flat package
DTMG 24
0
25 26 2
11
...--------------SHARP - . - . - - - - - - - - - - -
853
LCD Dot Matrix Controller CMOS LSI
__
..
_.~~"";.-.-..-.-..-.....,..-.r.
•
LR3692
____
.~.-~.-
Block Diagram
Dot a Register
Upper Screen
Display Start
pper Screen
Display Start
Latch Pulse Period
Cursor Position
Display Duty·
Character Numher
Upper Screen
Address Counter
Lower Screen
Address Counter
Cursor Address
Register
Memory
Address
Output
~
®}
Register Select
:
Chip Select
71
Display OFF Input 25
73
Read Input
61
Write Input
Display RAM
Select Input
Display Timming
Output
Busy Output
.
GND
(
854
Memory
Data Bus
. Memory Read
Output
LCD Dot Matrix Controller CMOS LSI
•
Absolute Maximum Ratings
Symbol
Ratings
Unit
Note
Voo
-0.3-+7
V
-O.3-Yoo+O.3
V
°C
1
1
Operating temperature
VIN
Topr
Storage temperature
Tstg
Parameter
Supply voltage
Input voltage
Nate 1:
•
LR3692
0-+50
-55-+150
°C
The maximum applicable voltage on any pin with respect to GND.
Recommended Operating Conditions
Parameter
Unit
V
Supply voltage
•
(Voo=5V±5%. Ta=0-+50"C)
DC Characteristics
Parameter
Symbol
Conditions
Input low voltage
VILT
Input high voltage
Input low voltage
VIHT
VilC
Input high voltage
VlHC
. VOLT
iOL=2.0mA
VOHT
IOH=l.OmA
VOLC
VOHC
iOL=0.6mA
IOH=0.6mA
VIN=OV
Output low voltage
Output high voltage
Output low voltage
Output high voltage
Pull-up current
Supply current
III
IOD
Oscillator frequency
fose
Ext. clock frequency
Ext. clock duty
fCl
Duty
Rise time
tRCL
Fall time
tFCL
MIN.
TYP.
0
2.4
MAX.
0.4
Voo
0.2VDO
0
0.8Voo
VOD
0.4
2.4
0.4
YDo-O.4
10
fosc = 4MHz
With crystal oscillator
4
0.2
47.5
50
4
52.5
50
50
Unit
V
Note
1
V
1
V
V
2
2
V
V
3
3
4
V
V
pA
MHz
MHz
%
ns
ns
4
5
6
6
6
6
6
!
Note 1:
Note 2:
/ Note 3:
Note 4:
Note 5:
Note 6:
Applied
Applied
Applied
Applied
Applied
Applied
to
to
to
to
to
to
pins
pins
pins
pin's
pins
pins
MDo -MD7. RIo-RI? Do·D7. CS. RS. CEo WR, RD. and DOFF.
TEST and CGIN.
__ __
~_
MAo-MAI5. MDo-MD7. MWR. MRD,'Do-D7. BUSY, and DTMG.
CLIo CL 2• S. DUO-OU 3• DLo-DL3. and M.
_
_ ~ _
~_
TEST. MAo-MAI5. MDo·MD7, RIo-Ri? Do-D7. CS. RS. CEo WR. RD. and DOFF.
CGIN and CGOUT.
855
19D Dot Matrix Controller CMOS lSI
•
lR3692
AC Characteristics
(1)
LCD control signal
Parameter
Data setup time
Data hold time
Clock pulse low width
Clock pulse high width
Clock cycle time
Clock delay time
Clock pulse width
Clock delay time
Data delay tillie
Data hold time
Data setup time
Signal rise time
Signal fall time
(Vcc=5V±5%, fosc=4M!Jz, CL=15pF, Ta=;oO-+50"C)
I
Symbol
tsn
tHn
twLC
tWHC
tWCL2
tOCLl
tWCLl
tOCL2
tnM
tHS
tss
tr
tf
Conditions
MIN.
100
50
150
150
0
2
0
TYP.
375
125
250
250
500
125
4
135
MAX.
500
2
2
0.1 Vnn-0.9Vnn
0.1 Vnn-0.9Vnn
Unit
ns
ns
ns
ns
ns
ns
ps
ns
ns
ps
ps
50
50
ns
ns
DUo-DU3
DLo-DL3
~--tSD'--~-~
CL2
tDCLl
!E---;ofE--- t W C L I - - ¥ -....
CLI
M
j '-------------'X____
>-------tss--------......---tHS----!J-+J
S.
. . . . - - - . , - - - - - - - - S H A R P -~--.------..-.
856
LCD Dot Matrix Controller· CMOS LSI
(2)
'LR3692
Writing display control command
(Voo=5V±5%. Ta=0-+50t)
Symbol
Conditions
,
tSRS
tWWR WR and CS overlap time
Parameter
Signal setup time
Signal pulse width
Signal hold ti!lle
MIN.
500
220
30
250
30
tHRS
tso
tHO
Data setup time
Data hold ti!lle
TYP . . MAX.
Unit
ns
ns
ns
. ns
ns
2'O~V
RS
O.BV
"----tSRS
tH!lS
WR,CS
J - - - - . tSD~
X
.
------~
2.0V
:=
O.BV
~
"------------
(3) Control signal timing
Signal
Signal
Signal
Signal
Signal
delay
delay
setup
delay
delay
Parameter
time
time
time
time
time
tHD~
(VoD=5V±5%. fosc=4MHz. CL=15pF Ta=0-+50t)
Symbol
tOWR
tOOT
tSOT
tOBU
tOFF
Conditions
MiN.
0.2
0.2
0.2
0.2
TYP.
1
1
1
1
MAX.
Unit
p.s
p.s
p.s
p.s
200
ns
11~
~-.-----.r---SH~RP-'-------
857
....
....,._..........
.............,.......
LCD Dot Matrix Controller CMOS LSI
..
_.....,.....,
.....,.....,
J
2.0V
O.8V
LR3692
....,.....,
....,...-.:
~
~
~
2.0V
O.8V
'2.0V
tOWR
\
O.8V
J
~
tnDu
O.8V
O.8V
II
J
..... tOOT..,.
DTMG
O.8V,
2.0V
O.8V
MAo-MA15
/
\
(
)
2.0V
O.8V
·~;f
O_.8_V__________________
BUSY, DTMG, MWR, MRD
MlAo-MA15
2.0V
O.8V
'[
L - - - _
(4)
Parameter
--
MOR delay time
Data delay time
Bus switching time
--
MWR delay time
Data delay time
Data hold time
Data hold ti!lle
858
(Voo=5V±5%, fosc=4MHz, CL=15pF, Ta=0-+50t)
Bus timing (Direct mode)
Symbol
tOMRL
tOMRH
tOOR
tCOR
tOLMW
tnHMW
toow
tHOW
tHMO
Conditions
MIN.
\
TYP.
MAX.
150
150
150
0
150
150
150
50
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
LR3692
LCD Dot Matrix Controller' CMOS LSI
tDMRH
MDo-MD7
1/f-
CE
/
1\
1/
WR
/
I~HD:
-----i
~
\
tDDW
---..
MDo-MD7
)
~W
/
---
tHMD
'(
.-.--------------SHARP - - - - - - - . - - - - 859
LCDE)pt Matrix Controller CMOS LSI
(5)
Bus timing (I/O mode)
LR3692
!
(Voo=5V±5%,"fosc=4MHz, CL=15pF, Ta=0-+50"C)
Address delay time
Symbol
tcMO'
Address hold time
tUMO
Parameter
':
Conditions
MIN.
TYP.
.-
MAX.
Unit
150
ns
1
p.s
tCMO
MAo-MA15
(6) Display RAM access (display busy in 4-blt
Parameter
Symbol
mode)(Voo=5V±5%, fosc=4MHz, CL=15pF, Ta=0-+50"C)
Conditions
MIN.
Data setup time
tSMO
200
Data hold time
tHMO
b
Access cycle time
tCA
~
J\
tSMD
)
860
,
tHMD
,
K
MAX.
Unit
ns
ns
500
tCA
MAo-MA15
TYP.
ns
LCD Dot Matrix Controller CMOS LSI
LR3692
•
Display Control Commands
Display control is accomplished by writing commands and data into the command and data registers_
(1) Mode control
When writing data into the data regist~r, write
code OOH into the command register to specify the
Write Mode Control registerRegister name: Mode Control register
RS
07
06
05
1
0
0
0
0
0
0
0
I 03 I 02 I 01 I 00
o I 0 I 0 101 0
04
MOOEOATA
(5)
Setting cursor position
Register name: Cursor Position register
RS
07
06
05
04
03 1 02 1 01 1 00
1
0
0
0
0
0
0
0
0
0
o
CPo Specifies the row on which the cursor is located in Character mode. The horizontal length of the cursor is identical to
the HP.
(6) Setting lower byte of display start
. address (upper screen)
Register name: Display Start Address register
RS
07 1 06 1 05 1 04 1 03 1 02 1 01
Data contents
1: 4-bit parallel output 0: 1-bit serial output
0: Graphic mode
1: Character mode
0: ~isplay OFF
02
1: ~isplay ON
1: Cursor blink (character blink when cursor is off.)
00
1: Cursor ON
0: Cursor OFF
(7)
(2)
Setting character pitch
Register name: Character Pitch register
RS
07
1
0
RS
07
1
0
I 06 I 05 I D4
o I 0 I 0 I 0
(VP-1)
I 00
03
02
01
0
0
0
0
011
(HP)
VP: Vertical pitch in character mode. Invalid for Graphic mode.
HP: Horizontal pitch in character mode. Invalid for Graphic mode.
The HP can take on any of the following three
values. However, when in the 4-bit parallel output
mode, the horizontal character pitch is fixed at 8.
HP
5
6
8
DI
00
0
1
0
1
0
0
Horizontal character pitch 5
Horizontal character pitch 6
Horizontal character pitch 8
(3) Setting the number of characters per row
Register name: Characters Per Row register
I 05 I 04 I 03 I 02 I 01 I 00
RS
07
06
1
0
0
0
o I
0
I
0
I o· I
0
I
1
I
0
(HN-1)
HN: Specifies the number oj characters per row when in the char·
acter mode, and the number of bytes per row when in the
Graphic mode. When in the 4-bit parallel output mode, HN
should be set to a multiple of four (4).
Nunmber of pixels per row NX:
NX=HP x HN in Character mode
NX=8 x HN in Graphic mode
(4)
Setting display duty
Register name: Display register
~
1
~I~I~I~I~I~I~I~
0 I 0 101 0 I 0 I 0 I 1 I 1
(NY-1)
o
NY: Display duty -
1 1 1 0 1 0
(CP-1)
1
o
o
1
00
010101011101010
Lower byte of start address
Setting upper byte of display start
address (upper screen)
Register name: Display Start Address register
I 06 I 05 I 04 I 03 I 02 I 01 I 00
I 0 I 0 101 1 I 0 I 0 I 1
Upper byte of start address
This command sets the display start address for
the upper section of the screen. The display start
address refers to the RAM location in which the
data to be displayed in the upper left corner of the
screen is stored.
(a) Setting lower byte of display start
address (lower screen)
Register name: Display Start Address register
~
~1~1~1~1~1~1~1~
101 0
o
I 0 I 0 101 1 101
Lower byte of start address
1
(9) Setting upper byte of display start
address (lower screen)
Register name: Display Start Address register
~
~I~I~J~J~J~J~J~
1 0 1 0 101 0 1 0
1
110
o
.Upper byte of start address
1
1
This command sets the display start address for
the lower section of the screen. The display start
address refers to the RAM location in which the
data to be displayed in the upper left corner of the
lower section of the screen is stored.
1/(32-256)
---~~-----------SHARP .------~-.-.,-,
861
LCD Dot Matrix Controller CMOS LSI
LR3692
(10) Setting lower byte of cursor address
Register name: Cursor Address register
~
1
o
1/0 mode is selected by writing OCR into the
command register. When BUSY = 1, thl! display
RAM location specified by the Cursor Address
register can be accessed through DIo-DI7 for read
or write operations.
The LR3692 also permits direct display RAM
access using the address data fu~nished from the
CPU. In either case the value of the Cursor
Address register is incremented each time the display RAM is accessed.
~1~1~1~1~1~1~1~
0 I 0 I 0 101 1 I 0 I 1 I 0
Lower byte' of cursor address
(11) Setting upper byte of cursor address
Register name: Cursor Address register
RS
1
o.
I Ds I D5 I D4 I D3 I D2 I Dl I Do
0 I 0 I 0 101 1 101 1 I 1
D7
Upper byte of cursor address
This command sets cursor address data into the
cursor address counter.
(12) Setting latch pulse period
Regipter name: Latch Pulse Period register
RS
1
0
D7
0
0
Ds
I
D5
I
D4
I
D3
I
D2
0 I 0 I 0 101
1
I Dl I
I 1 I
•
Do
1
(NLP-l)
HN + 1 ;:;;; NLP ;:;;; 121rwhen in serial mode.
HN/4 + 1 ;:;;; NLP ;:;;; 128 when in 4-bit mode.
The display frequency fd is related with the latch pulse period
NLP by the following formula:
fd = 1/(8NLP. TXS. NY)
TXS: Shift clock period
·TXS = 500 ns when OSC frequency is 4 MHz.
NLP:
(13) Setting display RAM access mode
RS
1
o
System Configuration
(1) Interface with CPU
As shown in Figs. 1 and 2, the LR3692 (LCDC)
is connected to the· standard bus of the ZBO-type'
CPU, using it as a means of transferring data and
commands.
If the CS is at low and RS is at high, the command register within the LCDC is specified and
the data on the data bus is written in. The write
timing is determined by the WR signal. If the CS is
at low and RS is at high, the contents of the
LCDC's internal register requested by the command register cannot be read.
The CE, BUSY, DOFF, and DTMG signals are
used for CPU access to the display RAM.
I Ds I D5 I D4 I D3 I D2 I Dl I Do
0 I 0 I 0 I 01 1 I 1 I 0 1 0
D7
DATA
ICE
Ao-Als
RS
LR3692
LCDC
Z80A
CPU
CS
Decoder
IORQ
RD
RD
WR
WAIT
WR
-----------.--
BUSY
---------~
DOFF
DTMG
Do-Dr
Do-D7
MAo-MA1s
MDo-MD7
MRD
~
I
Display RAM
MWR
I
Fig. 1 Interface with CPU(I/O mode)
- . - . . - - - - . - . - - S H A R P ---.--~------..-.
862
LCD Dot Matrix Controller CMOS LSI
LR3692
Ao-Al5
RS
LR3692
LCDC
Z80A
CPU
MREQ
CE
j,
IQRQ
I
Decoder
I
I
I
I
RD
-WR
CS
RD
WR
I
WAIT
I-- 1------ -------t--
.
L
I LR74HC244X2
BUSY
DOFF
DTMG
Do-D7
Do-D7
MAo-MA15
MDo-MD7
MRD
I
Fig. 2
1!
Display RAM
MWR
I
Interface with CPU (Direct mode)
(2) CPU access to display RAM
CPU access to the display RAM includes the 110
mode which is made through the LCDC, and the
Direct mode which is directly performed from the
CPU.
CD 110 mode
A sample system configuration
for 110 mode access is shown in Fig. 1. A value for
OC. is first set into the command register. If the
BUSY is high. CS is low. ap.d RS is low. the RD.
WR. and Do-D7 lines are linked to the MRD. MWR.
and MDo-MD7 lines. respectively. At this time the
value of the Cursor Address register is output at
the MAo- MAls pins. The Cursor Addre~register
is incremented at the rising edge of the RD or WR
signal. The BUSY line is set to high during the flyback period in which the LCDC does not access the
. display RAM. Setting the DOFF to low causes the
BUSY to be set to high. making the display RAM
accessible at any timing. At this time. the LCD display is turned off.
® Direct mode
A sample system configuration for Direct mode access is shown in Fig. 2. The
Direct mode is selected if the value of the com·
mand register is anything but OCH. If BUSY is
high and CE is low, the RD, WR and Do-D7 pins
are linked to the MRD, MWR, and MDo-MD7 lines,
respectively. At this time the DTMG is set at low
and the MAo-MAl5 pins are set to high impedance,
to transfer the address specified of the CPU direct-
ly to the display RAM. The Cursor Address regis·
ter is incremented at the rising edge of the RD or
WR signal. The functions of the BUSY and DOFF
signals are identical to those in the 110 mode.
Note:
•
In either mode the BUSY signal is output only when the
CPU is accessing the display RAM. (When CE = 0 in
Direct mode; when CS=O, RS=O and the command regis·
ter value is OCH in I/O mode.) The BUSY is set to high in
all other cases.
LCD Control
(1) Graphic mode
The Graphic mode is selected by the Mode Control register value. In this mode each bit of the display RAM corresponds to each pixel on the LCD
screen.
CD Screen configuration
The numbers of
pixels per row and per column are determined by
the values of the Character-Per-Row register and
Duty register.
No. of pixels per row: HNx8, HN= 16 to 128
No. of pixels per column: NYX2, NY=32 to 256
(When both the upper and lower sections of the
screen are used.)
® Display start address
The display start
address refers to the first location of the di~play
RAM area to displayed, specified by 16-bit data.
Independent specification for the upper and lower
sections of the screen is possible. Further, the utilization of display start address makes page con-
----..--.-..--SHARP-.-.------~
863
LCD Dot Matrix Controller CMOS LSI
'LR3692
Display RAM
MSB
LSB
LCD panel
ll'"'·~-- .sXHN line
Upper sc~een start address
!a7 as as a4 aa a2 al ao
~I
ila7as as Maa a2 al ao
+
t-
NY line
Lower screen start address b1 ba bs b4 ba b2 bl bo
Upper screen
b, ... b, '" b, b, b, b
NY line
Lower screen
L~_---,
Fig. 3 Screen configuration (Graphic mode)
trol and screen scroll possible.
(2) . Character mode
The Character mode is specified by the value of
the Mode Control register. In this mode pixel pat·
terns are displayed by combining character codes
of the display RAM with the corresponding char·
acter patterns of the character generator ROM.
(CGROM).
CD Screen configuration The numbers of
characters per row and per column are determined
by the content of the Character-Per Row register,
Duty register, and Character Pitch register.
No. of characters per row: HN = 16 to 128
No. of characters per column: NYx2lVVP, NY= 32
x256
(When the upper and, lower sections of the screen
are used.)
The numbers of pixels per row and per column
are determined as follows:
No. of pixels per row: HHYx2
@ Character font
The character font is
specified by the value of the Character Pitch reg·
ister.
Horizontal pitch: HP=5, 6, 8
Vertical pitch: VP = 1-16
Fig. 4 shows an example of character font. If HP=
5 or 6, the LSB side of the Rlo-Rlt is invalid.
® Cursor display The cursor display mode
is determined by the value of the Mode Control reg·
ister. The cursor position.is specified by the vahte
of Cursor. Address register. Since the character
code address on the display RAM is specified for
cursor position specification, screen scrolling is
accompained by cursor scrolling.,
The cursor position in a character font is speci·
fied by the Cursor Position register.
@ Cursor blink
Cursor or character blink·
ing is controlled by the Mode Controll register.
.r- =-:1
r ~o:~~~:~~ol
HP
.000.0
0 • • • • • 00
,
~~: ~ ~ ~ ~ ~~
VLP
:
OD'D 0 0 0
••••••
.0 0 0 0 0 DO 0
Fig.4
864
CGROM address
MAls MA14 MAla MA12
J
CP
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
1
o
1
o
o
o
1
"0
1
1
1
o
o
o
o
0
Example of character font (HP=8, VP=10, CP=9)
LCD Dot Matrix Controller CMOS LSI
LR3692
LR3692
LCDC
Rlo-Rh
DUo-DU3 ===¢
----
MA12-MAI5 DLo-DL3 ===¢ Liquid crystal
panel
MAo-MAll
CLI
MDo-MD7
r-
I
Do-D7
Ao-AI5
CGROM
Fig. 5
JI
CL2
MRD
M
MWR
s--
Display RAM
I
Connections to CGROM and LCD panel
(TXS=500 ns when OSC frequency is 4 MHz.)
Flyback period
The LCDC does not access the display RAM during fiyback period.
Blinking is performed for approx. 1H (64 frams) at
1/2 duty.
(3) Parameter setting
CD Display frequency
The LR3692 uses
the two-frame AC display system. The display system. The display frequency is determined by Display Duty and the value of the Latch Pulse Period
register.
One frame period: Td=8NLP.TXS.NY
Display frequency: fd=l/Td
®
Flyback period TDIS:
When in Serial mode: TDIS= 18 (NLP-1)-8HN
. TXS
When in 4-bit mode: TDIS= 18 (NLP-1)-2HN
.TXS
Retrace time
CLI _ _ _ _ _ _ _ _ _ _
n
~
Fig. 6
r
I
Retrace time
~I
I"
I
~
____________
"I
I IL-
~I
Flyback period
865
. LH5006A
LCD Dot Matrix Driver CMOS LSI
LH5006A
LCD Dot Matrix Driver CMOS LSI
•
Description
The LH5006A has 2 sets of 20-stage bidirectional shift registers, 2 sets of 20-bit latches and 2
sets of 20 LCD drivers, so it converts serial character pattern data to parallel data and provides
selected or nonselected waveforms output in
accordance with mode select signal.
•
•
Pin Connections
Features
1. CMOS process
2. 40-LCD driver circuit
(a half of 40 drivers can be used either as segment signal drivers or as common signal
drivers)
3. Single power supply: -.5V (TYP.)
4. 60-pin quad-flat package
•
Top View
Block Diagram
Output
-------~------~
__
Output
------A~------
__
Output
Output
Data I/O
866
Shift
Direction
Select
Shift
Direction
Select
Data I/O
LH5006A
LCD Dot Matrix Driver CMOS LSI
•
Pin Description
Pin name
YI-Y20
Y 21 -Y. O
Name
Liquid crystal output
I/O
a
~
SHL I
SHL z
FCS
Ch. 1 data shift
direction selection
I
Ch. 2 data shift
direction selection
I
Ch. 2 mode selection
I
Functions
Ch. 1 liquid crystal output
Ch. 2 liquid crystal output
SHL I
Low
High
DLI
IN
OUT
DRI
OUT
IN
SHL 2
Low
High
DL2
IN
OUT
Shift direction
SR 21 -SR 40
OUT
IN
SR.o-SR zl
FCS
High
Low
Mode
Common signal drive mode
Segment signal drive mode
DR2
Common signal drive mode
M
DLI> DRI
DL 2 , DR2
CL I, CL z
VI> V2
V3, V.
V 5 , V6
VDD
VEE
Vss
Clock for liquid crystal
drive circuit
Data output
I
I/O
Clock
I
Liquid crystal drive circuit
output voltage supply
I
Power supply
Shift direction
SR I -SR 20
SR 20 -SR I
Segment signal drive mode
M
Display
Nondisplay
M
Display
High
Low
V2
VI
V6
Vs
High
Low
VI
V2
Non-display
Ch.l
Ch.l
Vs
V6
V3
V.
Ch. 1 input/output
Ch. 2 input/output
Clock for data latch
Durling select
Ch. 1 durling non-select
Ch. 2 durling non-select
For logic circuit (- 5V)
For liquid crystal drive circuit (-17V)
GND
----------SHARP-.------867
LHS'006A
LCD Dot Matrix Driver CMOS LSI
•
Absolute Maximum Ratings
Parameter
Applied voltage * (logic)
Applied voltage *
(LCD drive circuit)
Input voltage'"
Operating temperature
Storage temperature
Symbol
VDD
Ratings
+0.3--7.0
Unit
V
VEE
+0.3--13.5
V
VIN
Topr
,+0.3-V DD -0.3
-10-+70
-55-+150
V
"C
"C
TS'l<
*The maximum applicable voltage on any pin with respect to Vss.
•
(Vss=GND, VDD =-5±5%, VEE =-lOV±lO%, Ta=-10-+70"C)
DC Characteristics
Parameter
Symbol
Input low voltage
V1L
Input high voltage
VIH
Output lo~ voltage
VOL
Output high voltage
VOH
Voltage drop between
VOl
Y1-Y 1
VD2
Input leakage current
I ILl I
Output leakage current
I ILO I
Logic current consllmption
ILOG
LCD driver current consul!lption
IDRv
•
Symbol
tcWH
tCWL
tsu
tSL
tLS
tod
I:c,
Note 1: Applicabte pins CLIo CL 2
Note 2:. Applicabte pin CL 2
Note 3: Applicabte pins DL" DR" DL2, DR2
868
MIN.
TYP.
MAX.
-3.5
-1.5
IOL =O.4mA
VoH =O.4mA
When ImA current flows into one of the pins Y1 through S40
When O.2mA current flows into each of pins Y1 through S40
Logic clock 1.6MHz
LCD driver clock
VDD +O.4
-0.4
1.1
1.5
5.0
10.0
3.0
10.0
1kHz
Unit
V
V
V
V
V
V
pA
pA
mA
pA
(Vss=GND, VDD =-5±5%, VE~=-18--16V, Ta=-10-+70"C)
AC Characteristics
Parameter
Clock high width
Clock low width
Data setup time
Clock setup time (CL 2....CL 1)
Clock setup time (CL 1....CL 2 )
Output delay time
Clock rise/fall time
Conditions
Conditions
CL=15pF
MIN.
250
250
70
200
200
TYP.
180
50
MAX.
ns
ns
ns
ns
ns
ns
ns
Unit
1
2
3
1
1
3
1
LCD Dot Matrix Driver CMOS LSI
•
LH5006A
Timing Diagram
____________~x~_____
DATAIN
DATAoUT
FLM
•
System Configuration
I I
-VDD
>->--
-
I
M CPl CP2
FCS
SHLI
SHL2
VDD
LH5006A
DLI
Yl-Y4o
M
CP2 f - -
Vf
CPl !------'
...
.!!
'0
....c
...
0
C,)
-
-
-
FCS
SHLI
SHL2
DR2
U
~D
FCS SHLI SHL2
-M
L...- CP 2
Common driver Yl
CPl
\
LH5006A
DLI
Y.o
DRI
[ DL2
DR2
rr-
Segment driver
~
I
M CL2 CLI
Segment driver
LH5006A
Yl-Y40
~
LCD panel
-/
---....-----.-~--SHARP
.....-..-.------869
LH5021 AlLH5022
LCD Dot Matrix Driver CMOS LSI .
LH5021A/LH5022
•
Description
LH502lA/LH5022 is an LCD driver LSI which
can receive either serial input data or parallel input data. In case of the serial input mode, it can
be connected in series. It converts -character pattern data input to parallel data output with 80-bit
latch circuit and provides character pattern waveforms output in accordance with mode select signal.
•
•
LCD Dot Matrix Driver
CMOS LSI
Pin Connections
. . rn .. ~.3u..:;..:~..::~o_~21
o~~ ...
~~»UZQQQQ>Q~U>~~~»
899994990
65848281
o
Features
1. CMOS process
2. 80-LCD driver circuit
3. 4 functions selectable as follows
(a)Segment signal drivers on the serial input
mode
(b)Segment signal drivers with the chip-selectable function on the serial input mode
(c)Segment signal drivers with the chip-selectable function on the parallel input mode
(d)Common signal drivers on the serial input
mode
4. Auto count function ; in a chip selected state,.
counts 80 input data automatically and stops
the internal clock CL,
5. Power supply voltage: - 5V (TYP.)
6. Display voltage
LH5021A: -17V (TYP.),
LH5022: -24V (TYP.)·
7. 100-pin quad-flat package
870
o
312
51 Y5I
6
9144456784950
Top View
LCD Dot Matrix Driver CMOS LSI
•
LH5021 AlLH5022
Block Diagram
Chip Select
Output
r------{:MI}-----~
Alternate 85
Signal
Cloak
87}-------~
1-;::===1.....L.....I.....I.....I--::-;;:~~::~.....I.....L.....L"""1I-__+-_+_r:>-_..{89 Serial
Data
Output
-.-....-.------SHARP-------871
LCD Dot Matrix Driver CMOS LSI
•
LH5021 AlLH5022
Pin Description
Pin name
VDD
VEE
Vss
V 3, V 4
Yl-Y SO
CL I
CL 2
FCS,PS
Name
I/O
Power supply
Liquid crystal drive circuit
output voltage supply
0
Clock
I
Mode select
I
Functions
For logic circuit (- 5V)
For liquid crystal drive circuit (LH502IA: -17V, LH5022: -24V)
GND
Durling non-select, however Vss > (V3, V 4»VEE
For data latch *Must be applied when 4 times the shift clock
For data shift
FCS
PS
Low
Low
Low
High
High
Low
High
High
Note 1:
Note 2:
• 011 :
• 01 2 :
• 01 3 :
'01 4 :
Note 3:
Note 4:
Liquid crystal drive waveform
AC conversion signal input
I
01 1-01 4
Display data input
I
DO
EI
ED
Serial data output
For
chip select
0
M
872
I
0
Mode
I-bit serial input
segment driver
4-bit parallel input
segment driver
I-bit serial input
segment driver
Commnn driver
(serial input)
Chip select
DO out
X
0
0
High
0
High
X
0
In the serial input mode, data is supplied from
the 011 pin.
The relationship between data input during 4·bit
parallel input and the Y output is as follows.
Y b Y5 , Y9 , ••• Y 13 , Y77
Y2 , Y6 , Y lO , ... Y74 , Y78
Y3, Y7 , Y ll , .,. Y75 , Y79
Y4, Ys , Y12 , ... Y76 , Yso'
When used as a comon driver, the clock used for
transfer is input to the CL 2 pin. CL I is internally
fixed.
To minimize current consumption, it is necessary
to fix unused input pins to the same level as the
Vss pin or the V DO pin.
Common signal drive mode
Segment signal drive mode
Latch data
Low
(non·display)
High
(display)
Latch data
Low
(non-display)
High
(display)
M Yout.
Low
V3
High
V4
Low VEE
High GND
M Yout.
Low
V3
High
V4
Low GND
High VEE
When used with a common driver and in the serial input
mode, supply the data to the 011 pin. In this case, it is
necessary to fix 01 2 - 014 to the Vss level or the VDO level.
When used in the chip select mode, it becomes high level.
Used only in the chip select mode.
(1) The (CL 1 • CL 2) timing causes EO to become low level.
(2) After (1), the device is set to the select mode by inputting
a high signal to EI, and the input data is read in accord·
ing to the timing of the fall of CL 2 •
(3) When 80 items of input data (equivalent to 80 CL 2 clock
cycles in the serial mode or 20 CL z clock cycles in the
4·bit parallel mode) have been read in, EO automatically
becomes high level and data read in is terminated. EO is
reset 1.5 cycles later.
LCD Dot Matrix Driver CMOS LSI
Pin name
•
Name
I/O
Functions
(4) When two or more devices l:lre used in the chip select
mode, EO of the first stage and EI of the second stage are
connected and used.
1. EO of all devices connected is reset by (1) and goes
to the non·select condition and waits for EI input.
2. When a high signal is applied to EI of the initial de·
vice in the cascade connection, this device performs
the operations in (2) and (3).
3. Connecting EO of the initial devices to EI of the next
devices causes the devices perform the operations in
(2) and (3) after the initial device. This operation is
repeated in the same manner for all subsequent devices.
In the non-select condition, the shift clock CL 2 stops internally, so power consumption becomes extremely small.
Absolute Maximum Ratings
Parameter
Note 1: The
~aximum
Voo
LH5021A
Ratings
-7-+0.3
LH5022
Ratings
-7-+0.3
VEl
-20-+0.3
VIN
Topr
VDD -0.3-+0.3
-20-+70
-55-+150
Symbol
Applied voltage (logic)
Applied voltage
(Liquid crystal drive circuit)
Input voltage (logic)
·Operating temperature
Storage temperature
•
LH5021 A/LH5022
T st"
Unit
Note
V
1
-30-+0.3
V
1
Voo -0.3-+0.3
-20-+70
-55-+150
V
1
"C
t
applicable voltage on any pin with respect to Vss.
DC Characteristics
Parameter
. Symbol
Input low voltage
Input high voltage
Output high voltage
Output low voltage
VIL
VIH
VOL
VOH
Voltage fall between Vi - Yi
VOl
Voltage fall between Vi-Yi
VD2
Input leakage current
Output leakage current
Logic circuit selection
current consumption
Conditions
IOL =O.4mA
IoH =O.4mA
1 rnA to one of
YI-Y SO
0.2 rnA to each
of YI-Y SO
LH5021A *1
LH5022*2
MIN. TYP. MAX. MIN. TYP. MAX.
0.8Voo
0.8Voo
0. 2Voo
0. 2Voo
VDD+OA
~DD+OA
-0.4
-0.4
I Iu I
I ILO I
ILOG
1 bit serial
transfer (3.3MHz)
4 bit parallel
transfer (2.0MHz)
Unit
V
V
V
V
1.1
1
V
1.5
1.5
V
1
10
1
10
pA
pA
2.2
6.0
2.0
5.0
rnA
1.0
2.0
1.0
2.0
rnA
*1 VEE =-17V±1V
*2 VEE =-24V
873
LCD Dot Matr.ix Driver CMOS
•
LH5021 A/LH5022
AC Characteristics
(1)
1-blt Serial Input Segment Driver (PS=FCS="Low") (Voo =-5V±10%, vss=ov, Ta=-20-+70t)
Parameter
Clook frequency
High-level clock width
Low-level clock width
Data setup time
Data hold time
Output delay
High-level latch clock width
Clock margin time
(from CL I ~ to CL 2 l )
Clock margin time ... 2
(from CL 2 l to CL I l )
Clock margin time
(from CL 2 t to CL I t )
Clock t, l time
Overlap time of
CL 2 "L" and eLl "H"
Symbol
tc
tcwH
tcWL
tsu
tH
to
t LwH
Conditions'" 1
MIN.
300
130
130
70
50
CL =15pF
MAX.
230
130
*3
Unit
ns
ns
ns
ns
ns
ns
ns
Applicable pins
CL 2
CL 2
CLl> CL 2
011
011
DO
CL I
tc12
20
ns
CLl> CL 2
tc2l
200
ns
CLl> CL 2
tp2l
20
ns
CLl> CL 2
ns
CLl> CL 2
ns
CLl> CL2
50
tcT
130
tov
Test conditions
Input frequency: O.8VOlh O.2Voo: Input reference level: O.8V oo• O.2Voo: Output reference level: O_2V oo• O.8Voo
*1
*2
*
3
LH5021A
VEE =-17V±lV, LH5022 : V EE =-24V
Internal shift register determination time
1.5tc-tC12-tp21 - 3tCT
tCT
DIt
DO
Valid
tov
tP2I t CT
tCT
t C2I --t-t-l-.... t C12
YI-YSO
-~""-~-""""--SHARP---'-'''''''''''--~
874
LCD Dot Matrix Driver CMOS LSI
(2)
LH5021 AlLH5022
4-blt Input Segment Driver (PS="High", FCS="Low") (VDD=-5V±10%. vss=ov. Ta=-20-+70"C)
Parameter
Clock frequency
High-level clock width
Low-level clock width
Data setup time
Data hold time
Output delay
High-level latch clock width
Clock margin time
(from CLI ~ to CL 2 ~ )
Clock margin time * 2
(from CL 2 ~ to CLI l )
Clock margin time
(from CL 2 t to CLI t)
Clock t. ~ time
Overlap time of
CL 2 "L" and CLI "W
Symbol
tc
tcWH
tcWL
tsu
tH
tD
tLWH
Conditions * I
MIN.
500
230
230
70
50
CL=15pF
MAX.
230
130
*3
Unit
ns
ns
ns
ns
ns
ns
ns
Applicable pins
CL 2
CL 2
CL h CL 2
Dlh Dl 2• Dl3• Dl4 • EI
Dlh Dl 2• Dl 3• Dl4 • EI
EO
CLI
tcl2
20
ns
CL h CL 2
tc21
200
ns
CL h CL 2
tp21
20
ns
CL h CL 2
ns
CL h CL 2
ns
CLl> CL 2
50
tcT
tov
130
Test conditions
Input frequency: O_BV OD• O_2Voo; Input reference level: O.BVoo. O_2Voo: Output reference level: O.2V DO• O_BVoo
*1 LH5021A VEE =-17V±lV. LH5022: VEE =-24V
2 Internal shift register determination time
3 L51:c-1:c12-tp21-3I:cT
*
*
EI
... tC12
-~++
EO
to
tD
to
-------------SHARP-.-.--..----875
LCD Dot Matrix Driver CMOS LSI
(3)
LH5021 AlLH5022
(VDD =-5V±10%, Vss=OV, Ta=-20-+70·C)
Common Driver (PS="Low", FCS = "High")
Parameter
Clock frequency
High-level clock width
Low-level clock width
Data setup time
Data hold time
Output delay
Clock t , ~ time
Symbol
tc
tCWH
tcwL
tsu
tH
tD
tCT
Conditions * 1
. MIN.
MAX.
1000
130
830
70
50
CL=15pF
Test conditions
Input frequency: O.SV DD, O.2V DD; Input reference level: O.SV DD, O.2V DD;
*1 LH5021A VEE =-17V±lV, LH5022: VEE =-24V
500
50
Unit
ns
ns
ns
ns
ns
ns
ns
Applicable pins
CL 2
CL 2
CL 2
011
011
DO
CL 2
Output reference level: O.SV DO, O.2V DD
CL2
~J---tCWH
DO
Valid
Yt-YBo
.-.---.-.---SHARP------------
876
LCD Dot Matrix Driver CMOS LSI
(4)
LH5021 A/LH5022
1-bit Serial Input Segment Driver (PS="Low", FCS="High")
(VDD=-5V±10%, vss=ov, Ta=-20-+70"C)
Parameter
Clock frequency
High·level clock width
Low-level clock width
Data setup time
Data hold time
Output delay
High-level latch clock width
Clock margin time
(from CL I ~ to CL 2 ~ )
Clock margin time * 2
(from CL 2 ~ to CL I ~ )
Clock margin time
(from CL 2 t to CL I t )
Clock t, ~ time
Overlap time of
CL 2 "L" and CL I "H"
Symbol
te
teWH
teWL
tsu
tH
tD
t LWH
Conditions * I
MIN.
380
170
170
70
50
CL=15pF
MAX.
230
130
*3
Unit
ns
ns
ns
ns
ns
ns
ns
Applicable pins
CL 2
CL 2
CLIo CL 2
DIb EI
DIb EI
EO
CL I
tel2
20
ns
CLIo CL 2
tC21
200
ns
CLIo CL 2
t p21
20
ns
CLIo CL 2
ns
CLIo CL 2
ns
CLIo CL 2
50
teT
tOY
130
Test conditions
Input frequency: O.8V DD, O.2V OD ; Input reference level: O.8V oo• O.2Voo; Output reference level: O.2VDO• O.8VOD
*1 LH5021A VEE =-17V±1V. LH5022: VEE =-24V
2 Internal shift register determination time
3 1.5tc-tc'2-tp2,-3tcT
*
*
Ell
----oo+-loo-o·t C12
EO
to
to
to
877
• Ig
~I
en
I
'<
I
I
I
I
I
..l~
\ Address Bus
.!...>
U
II
II
.!...>
1r
FCS/PS DII
M LH5021A ~
/LH5022Y
CLI
r---v'
CL2
I
\ Control Bus
I,
.! .!.
\y. . ~ ~IDEClOD~~ER
RD
IORQ . WR
'-----.--...1
FCS/PSDII
'_
jjJ,
"I
RD
WR RS CS DE
WAIT
-'\
---,/ Do- D7
I
---;==
I
f---
CPI
CP2
M
LR3691A
DI
_
CS Do-D, WE OE
DISPLAY RAM
Ao-AI5
,..,J-,..L--L........J.,..,
CL. CLI M FCS
CL,'CLI M FCS
LH5021A IPS
LH5021A IPS
/LH5022 Dltf----- DO /LH5022 Dhf-
Yao-YI
Yao-YI
' Yao-YI
"'-.J.
{J,.
U
I
I
I
3
"0
CD
II
N
fr
T
___
-__
:::
-=~=
t:
a0"...
m
I
fr
10"
D)
:
Yao- YI
Yao-YI
LH5021A
LH5021A
ILH5022 Dh ----- DO ILH5022 Dh
FCS
FCS
CL, CLI MIPS
CL, CLI M IPS
0
:::l
----'----~-------LCD IPanel - - - - - - - - - - - IT!
Ii.
- I~
0
:::l
)(
:
LH5021A ~
M /LH5022Y~
CLI
I
=jl
11
rr-
1"-
I
:
CL2
IMAo- MAI4
DI2 Dh
DI.
MDo- MD, MWR MRD
r:
..!
DECODER
+5V
Yao-YI
II
~~~-.
-----, I
CL. CLI M FCS
CL, CLI M FCS
LH5021A IPS ___
LH5021A IPS
/LH5022 Dh r- -- DO /LH5022 Dh
1[" 1["
\ Data Bus
I
I
-1
(Z80 System)
I
I
I
I
I
I
II~~~~~~~-~~~---
CPU
!e.
CD
3
1t1'f"
.
Yao-YI
Yao-YI
LH5021A
LH5021A
ILH5022 Dh 1----- DO ILH5022 Dh rFCS
FCS
CL. CLI MIPS
CL. CLI MIPS
_
__ ---1 I
___ ----.J
I
--------1
:=~
1Ir
I!
I
I
II
II ~
~
I~
LH5821/LH5822/LH5823
LCD Dot Matrix Driver CMOS LSI
LH5821/LH5822/LH5823
LCD Dot Matrix Driver CMOS LSI
•
Description
The LH58211LH5822/LH5823 are CMOS driver LSls for LCD dot matrix display.
Anyone of display duty ratio, 117 - 1/20 can be
selected by programming.
Write and read to/from the built-in RAM of display data can be made only by 3 signals, serial
data, synchronous signal, and transfer clock.
The LH5826 is available for segment output expansion.
•
•
Pin Connections
::
'"
<-
'"
M
_
30 dj~u ~ -<:O:~O:O:O:cCd:
oo~~~~~>oo>u~~»~~~~~~~
• • Y5YHNDUDWoaUMOMUUOM
Features
1.
2.
3.
4.
Display data RAM: 1280bits
10-bit serial data transfer
Built-in oscillator for display
Duty (Selectable by programming)
LH5821: 1/7-1120
LH5822: 1/7-1118
LH5823: 1/7-1116
5. Segment output
LH5821 : 44bits
LH5822 : 46 bits
LH5823 : 48 bits
6. Common output
LH5821 : 20 bits
LH5822 : 18 bits
LH5823: 16 bits
7. Clock output for double voltage
8. Power supply voltage: 5V (TYP.)
9. Display voltage
LH5821, LH5822 : 12V (MAX.)
LH5823 : lOV (MAX.)
10. 80-pin quad-flat package
Top View
37 pin 38 pin 63 pin 64 pin
*
LH5821
BPIlI
BPlo
BP n
LH5822
S"
S"
BPlo
BP1 7
S"
S"
s"
s"
LH5823
BP14
--- f------'----
-'---~'-'--SHARP'-------'-
879
LCD Dot Mattix Driver CMOS LSI
•
LH5821/LH58221LH5823
Block Diagram
Frame Sync.
Clock
8
RAM
64 X 20 bits
.Display Clock
7
Load Control 49)------~---..I...-__,
~------~vr------~
Output
.-.------~--SHARP-.---.-.---
880
LCD Dot Matrix Driver CMOS LSI
•
LH5821/LH5822/LH5823
Absolute Maximum Ratings
Parameter
Symbol
Ratings
Vee
Vop
Topr
T stg
-0.3-+7
-0.3-+13(+11)
-5-+55
-5-+150
Pin voltage *
Operating temperature
Storage temperature
Unit
V
V
t:
t:
Note
1
1
Note 1: Referenced to GND. Value in parentheses ( ) applies to LH5823.
•
Recommended Operating Conditions
Parameter
Supply voltage
Display voltage
Symbol
Vee
Vop
MIN.
4.5
6
TYP.
MAX.
5.5
12(10)
Unit
V
V
Note
'2
Note 2: Value in parentheses ( ) applies to LH5823.
•
DC Characteristics
Parameter
Input voltage
Input current
Output voltage
Output resistance
Input leakage current
(V ee =4.5-5.5V, Ta=-5-55t:)
Symbol
V IH
V lL
IIH
IlL
V OH
VOL
RQ
RSEG
VIH=Vee
VlL=OV
IoH =410 pA
IOL =1.6mA
Vee=5V, Vos=1.0V
ReoM
Rv
I IL I
Vop=6V, Ta=25t:, Vos=IV
Ieel
Current consumption
Iee2
lop
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
•
Conditions
MIN.
Vee- O.S
0
TYP.
MAX.
Vee
O.S
50
1
25
2.4
O.S
Durling no-load blank display
f; = 100kHz, fcLo=OHz, Ta=25'C
Durling data write (write cycle 1145 MHz)
f; = 100kHz, ho=IMHz, Ta=25'C
Durling no-load blank display
VDP =12V, f; = 100kHz, 1116 duty
Unit
Note
V
3
pA
4
V
5
0
7
S
SO
1.0
1.5
40
30
4.5
1
kO
kO
200
500
pA
2
rnA
10
pA
5
9
0
pA
10
6
Applied to pins CLo, LC, SDo
Applied to pin LC
Applied to pins SDo, H, {Applied to all pins except LC
Applied to pins Q, Q
Applied to segment output pin.
Applied to common output pin.
Applied to pins VA, VB
AC Characteristics
. Symbol
Parameter
t Re
CLo cycle time
LC hold time
tLD
LC setup time
t LS
SDo setup time
tsso
SDo input/output switching time
to
Conditions
C L=50pF
MIN.
1
0
100
100
TYP.
MAX.
Unit
ps
SO
450
ns
ns
ns
ns
~'--~----SHA~P------'-'---
881
. LH5821 ILH5822lLH5823
LCD Dot Matrix'Driver CMOS LSI
•
AC Timing Diagram
CLo
LC
tSSD
SOo (Input)
0:X
S 00 (Output)
UMdm~±
~Input
--Input mode - - - - ! E - - - - - O u t p u t mode
•
mode
Functions
(1)
Pin description
Pin name
Vee, GND
Vop, VA, VM, VB
LC
CLo
RX
RY
'"
if
.
Q,Q
S20-S63 (LH5821)
S1S-S63 (LH5822)
S16-S63 (LH5823)
BPo-BP 19 (LH5821)
BPo-BP 17 (LH5822)
BPo-BP 15 (LH5823)
SDo
(2)
882
I/O
4
1
1
1
1
1
1
2
44
46
48
20
18
16
1
I
Functions
Power supply for logic circuit
Power supply for liquid crystal drive
Serial data transfer sync. signal
Serial data transfer clock input
Input clock oscillation pin
Input clock oscillation pin
Clock output for display
Liquid crystal frame sync. signal
Clock output for double voltage generation
0
Liquid crystal segment drive signal
Liquid crystal common drive signal
I/O
Serial data input/output
Relationship between 10-bit serial data and modes
lO·bit data/mode
Chip select/duty setup mode
RAM address setup mode
8-bit data write mode
8-bit data read mode
(C" C2
No: of pins
3
:
Control data, Do-D7 : Data)
CO
0
0
1
1
C1
0
1
o·
1
Do D1 D2 D3 D4 D5 D6
Chip select data
I Duty data
Ao A1 A2 A3 A4 A5 A6
Data
Data
D7
A7
LCD Dot Matrix Driver CMOS LSI
LH5821/LH5822/LH5823
• LC single
• (> signal
The (> signal is the clock output for display and
is supplied to LH5826.
• H signal
The H signal is the frame period signal for the
liquid crystal and is supplied to LH5826. When
the power is turned on, the timing signal in each
device is in an unsynchronized condition, and after
the H signal is generated, they are synchronized.
• Auto clear
When th'e power is turned on, the display signal
generates an OFF pattern. Auto clear is canceled
when all of the duty data of the chip select duty
data are made" 1" and input, and then the contents
of the RAM are displayed. The chip select duty
does not change at this time.
• Double voltage clock
A double voltage clock is output from pins Q and
Q. The Q and Q signals are clock signals made by
dividing the display clock (> by 2, and their respective polarities are opposite.
The LC signal is a sync. signal for serial trans·
fer, and when LC is low, LSI remains in the stand·
by condition regardless of the condition of SDo and
CL o, When' LC becomes high and clock CLo is supplied, the LSI is enabled.
• CL signal
The CL signal is the clock signal for serial transfer and is used to write and read serial transfer
data SDo.
• SDo signal
The SDo signal is lO-bit serial transfer data of
which the first 2 bits are control data and the remaining 8 bits are data. In the read mode the SDo
pin becomes an output pin and outputs the 8-bit
RAM data in serial. After the write or read mode
has been executed, the lower 6 bits, Ao-A5, of theRAM address are automatically incremented, but
As and A7 do not change.
• Chip select
In the LSI, the chip select code is set at "0000",
so by inputting the chip select code "0000" through
the SDo pin, this chip is selected:
The RAM address setting and writing and reading of the 8-bit data is executed only for the chip
selected, and once a chip is selected, it remains in
the selected condition until a select code for the
next chip is input.
•
System Configuration
~
Dot matrix LCD
~
~)
20
BPo-BP19
~
S20
64r
S63
.-
RY
LH5821
RX
{
H
¢
¢
eS3 I -
LH5826'
GND
GND
Vee
Vee
+!V
I f
7,
R
r
r
CS2
~
CSI f-
SDo LC CLo VDP VA Vo
j
1
VDP
RX
H
SDo LC CLo VDP VA VM VB
CPU
So S63
CS~
r- -
+5V
J
R
Cl: ~C2 : i:C3 : ~C4
,
----------SHARP-----.--883
lCO Dot Matrix Segment Driver CMOS LSI
LH5826
•
LCD Dot Matrix Segment Driver CMOS LSI
De$cription
The LH5826 is a segment driver CMOS LSI for
LCD dot matrix display. Write and read to/from
the built-in RAM of display data can be made only
by 3 signals, serial data, synchronous signal, and
transfer clock.
The LH5826 is available for segment output expansion of the LH5821, LH5822 and,LH5823.
•
'LH5826
•
Pin Connections
:: ......... .., .... ~QtL,j~ulC<." ...........
:::=
~~~oo~oo>oo>u~~»oooooooooooooo
5
5 54 3 5 51
4
4 4
4 4 42 41 40
Features
1.
2.
3.
4.
5.
6.
7.
Display data RAM: 1280 bits
lO-bit serial data transfer
Segment output: 64 bits
Up to 15 drivers expandable
Power supply voltage: 5V (TYP.)
Display voltage: 12V (MAX.)
80-pin quad-flat package
Top View
--------.----.----SHARP -----.-.---.-,-.--884
LCD Dot Matrix Segment Driver CMOS LSI
•
LH5826
Block Diagram
Segme'!,t Output
,--------------------------{15 ---- ----- 46
Frame Sync. 8
Clock
RAM
64x20bits
Dislay Clock 7
Load Control
Segment Output
•
Absolute Maximum Ratings
Parat:neter
Pin voltage
Operating temperature
Storage temperature
Note:1
•
Symbol
Ratings
Vee
VDP
Topr
Tstg
-0.3-+7
-0.3-+13
-5-+55
-55-+150
Unit
Note
V
1
"C
"C
Referenced to GND.
Recommended Operating Conditions
Parameter
Supply voltage
Display voltage
Symbol
MIN.
Vee
VDP
4.5
6
TYP.
MAX.
Unit
5.5
12
V
V
- - - - - - - - - - - - S H A R P . -.......... - - - - - - - - -
885
LCD Dot Matrix Segment Driver CMOS LSI
•
LH5826
(Vcc=5V±10%, Ta=-5-+55t)
DC Characteristics
Symbol
VlH
VIL
IlH
IrL
VOH
VOL
Parameter
Input voltage
Input current
Output voltage
RSEG
Icc!
Current consumption
Icc2
lop
•
2:
3:
4:
5:
6:
Applied
Applied
Applied
Applied
Applied
to
to
to
to
to
MIN.
TYP.
Vee-O.S
0
25
VlH=Vee
VIL=OV
IOH=400pA
IOL=1.6mA
MAX.
Vee
Note
V
2
pA
3
0.8
50
1
V
4
10
O.S
1
30
Vop=6V, Vos=lV, Ta=25t
During still image display under no load
ft} =100kHz, fcLO=OHz, Ta=25t
During data write (write cycle 1145 MHz)
ft} =100kHz, f~LO=lMHz, Ta=25t
During still image display under no load
Vop=12V, ft} = 100kHz, 1I20duty
pA
kO
5
6
200
500
pA
2
mA
10
pA
5
pins CLo, LC, SDo. H, and "'.
pin LC.
pin SDo.
all pins other than LC.
pins SO,S63.
(Ta=25t)
AC Characteristics
Symbol
Parameter
CLo cycle time
Conditions
MIN.
1
0
100
100
tRC
tLB
tLS
LC hold time
LC setup time
SDo setup time
SDo 1/0 switching time
•
Unit
2.4
I IL I
I/O leakage current
Output resistance
Note
Note
Note
Note
Note
Conditions
tsso
tLD
CL=50pF
TYP.
SO
MAX.
450
Unit
ps
ns
ns
ns
ns
AC Timing Diagram
\fV\JV
CLo
(
LC
tsso
SDo (Input)
U~dmOO
SDo (Output)
--Input mode----'i-'----:. Output mode
.---....-.~-----SHARP
886
±
Input mode
---...---------
LCD Dot Matrix Segment Driver CMOS LSI
•
LH5826
System Configuration
~
Dot matrix LCD
I""
BPo BPl9
{
{s:j
j::j
20
S20
S63
~
RY
LH5821
RX
H
H
¢
¢
{
GND
Vee
Vee
Jv
! t
1
VDP
R
TCl :
r
r
CS3 r-
GND
SDo LC CLo VDP VA VM VB
CPU
SO-S63
RX
""
LH5826
CSI r-
SDo LC CLo VDP VA VB
$
CS2 r-
i
CSot---:-t- +5V
""
R
C2 : j:C3 ~C4
1.
887
LH5826·
LCD Dot Matrix Segment Driver CMOS LSI
•
Functions
(1)
Pin Description
Signal
Vee, GND
VDP, VA, VB
<}
H
CSo-CSa
LC
CLo
RX
So-S6a
SDo
(2)
No. of pins
3
3
1
1
JlO
Function
Power supply for logic circuit
LCD driving power
Display clock input
LCD frame sync signal
Chip select input
Serial data transfer sync signal
Serial data transfer clock input
Connected Vee or GND
LCD segment driver signal
Serial data JlO
I
4
1
1
1
64
1
0
JlO
r10-blt serial· data versus mode
lO-bit data/mode
Chip Select Duty Setting Mode
RAM Address Setting Mode
8-bit Data Write Mode
8-bit Data Read Mode
CI
C2
0
0
1
1
0
1
0
1
Do DI D2 DaD4 D5 D6 D7
:
Chip Select Data
Duty Data
Ao Al A2 Aa A4 1\.5 A6 A7
Data
Data
I
(CI, C2: Control Data, Do-D7: Data)
• LC signal
The LC is a serial transfer sync signal input. If
the LC is at low, the LH5826 maintains standby
status ignoring the statuses of SDo and CLo. The
device enters the enable status when the LC is set
at high and the clock CLo is supplied.
0001 and 1111 for CS"a, CS2, CSI, and CSo, respectively. Chip select code DODO, used to select
the; LH5821-5823, cannot be used for the
LH6826.
• CLo signal
The 1> is a display clock input. The clock is
supplied from the LH5821-5823.
The CLo is a serial transfer clock input used for
writing or reading serial transfer data SDo.
• SDo signal
The SDo is a 10-bit serial transfer data line.
Data consists of two control bits and 8 data- bits.
When in the Read mode, the SDo pin functions as
an output to deliver 8-bit RAM data in serial
form. When read or write operation is completed,
the lower 6 bits, Ao-A5, of the RAM address are
incremented. Bits A6 and A7 do not change,
however.
• CSo-CSs pins
The CSO-CS3 are chip select inputs. On: the
LH5826,
the chip select code can take on a value between
•
_
'"
'"
...
~~oo~»>UUUUU~~>U~~::t:oooooooooo
7 71 1 69 6 67 66 6 64 6 62 61 60 59 5 5 56 5 54 53 52 51 50 49
o
Features
1. Display data RAM: 3200 bits
2. Segment output: 80 bits
3.1/32 or 1/40 duty
4. Automatic address modify
5. Scroll function
6. Power supply voltage: 5V (TYP.)
7. Display voltage: 15V (MAX.)
8. 96-pin quad-flat package
Top View
LH 5036A
""., '"' _ =
_
0
:::UCIlif:JfflffJZO
¢
_
N
_
0
0
._
-<:
;:)..JU 000 0 N ... or> '"
IfJlfJlfJoo»>ZUUUU~OO>U..J~XlfJlfJlfJrnrn
7 71 7 69 68 67 66 6 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
o
Top View
--.-------SHARP-.-.------
889
LCD Dot Matrix Segment Driver CMOS LSI
•
LH5035A/LH5036A
Block Diagram
LCD Power
, Supply
Frame
Sync.
Clock
5'~--01
Display Controller
RAM
40 X SObits
Display
Clock
GND
Load
Control
o
.•
CH (NCO)
Serial Data
Input I Output
(NC') is for LH5036A.
Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Symbpl
Vee
VOP
VTl
VT2
Topr
T s '"
Ratings
-0.3-+0.7
-0.3-+16
-O.3-V ee +0.3
-0.3-Vop +0.3
-5-+55
-55-+150
Unit
V
V
V
V
Note
1
1,2
1,3
"C
"C
Note 1: Referenced to GND.
Note 2: Applied to pins HSi, ~ 0, LC. CL o• SDo• CSO-CS 3, CH
Note 3: Applied to pins V~. VB. SO-S79
•
Recommended Operating Conditions
Parameter
Supply voltage
Display voltage
Symbol
Vee
Vop
MIN.
4
9.6
TYP.
MAX.
6
14.4
Unit
V
V
--~---""""'~-SHARP,'-'-----------
890
LSD Dot Matrix Segment Driver CMOS LSI
•
(Vee=4.0-6.0V, Vop =6.0-15V, Ta=-5-55t)
DC Characteristics
Parameter
Input voltage
1
Input voltage
2
Symbol
VIH
V1L
VIH
V1L
VOH
VOL
IOH
IOL
Output voltage
Output current
Display current consumption
IOH=400pA
IOL =1.6mA
VOP-VOHI =lV
VoL =lV
Vop =15V, Vee=6V
Durling no· load display
f~ =4kHz
CLo=OHz
1140 duty
V1N=OV or Vee
VOUT=OV (Va) or Vee (V A)
lop
I ILl I
I lLO I
Input current
Output leakage current
Note
Note
Note
Note
Note
Note
Conditions
lee
Logic current consumption
•
LH5035A1LH5036A
MIN.
2.4
0
3.2
0
2.4
TYP ..
. MAX.
Unit
Note
V
4
V
5
V
6
pA
7
Vee
0.8
Vee
0.8
0.8
100
100
50
300
.pA
1
20
pA
0.1
0.1
1.0
10
pA
pA
8
9
4: Applicable to pins LC, CL o, 50 0 , CS O-CS 3 , CH; Vce =4.5-5.5V
5: Applicable to pins ;'0, HS;; Vcc =4.5-5.5V
6: Applicable to pins 500 ; Vcc =4.5-5.5V
7: Applicable to pins 50 -5 79 ; VOH " VOHl is light signal output "High", "Low" voltage
8: Applicable to all input pins
9: Applicable to all output pins, ( ) applicable to segment output
System Configuration
+
Vee
[
CLoLSDo (10 HSi
CH LC
Vee
L
t-i.
,,--CS
LH5035A
VDP
t t
~
CLo LSDo (10 HSi
CH LC
t...L
'CS
LH5035A
VA VB
~o
r--n"-+-+--+-IVD~X RY DYoDYl
C~· R
......... I.......................,H VA
BPo ~
C~· r
LH5030 I ..!Q.../
WI
VM
BP3.'
IC~'
r
BP40 ~
~:"""-R-~VB
vr
~-+----4GND
7,"
0 0-- ---- 79 - - --- - - - -- ---- - - - - - --- -- ---- -- 560 - - ---·639
I
39
Dot matrix LCD
0
BP7•.AQ,,; 3~
0 ------79 - - -- - -- -- - --- - - - - -- - - - -- -- - - ---- - 560 ---- --639
~~~~~--------------------------~~~~~~~
¢Jo HSi
Vee
80
801
SO-S7'
SO-S7'
LH5035A
CS-f-..
Vee, GNO
5
LH5035A
4
4
LC1CHh
HSi (10 SDo CLo I '1Ir
iii
CS-f-."
LC1CHh
HS, (10 SDo CLo I '1Ir
TiT T
VDP'VA'VB~:=!;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cpu{ ============~:±==================~t==~
.---~-------SHARP
-.------,------891
LH5030
LCD Dot Matrix"Common Driv~r CMOS LSI
LH5030
•
LCD Dot Matrix Common Driver CMOS LSI
•
Description
Pin Connections
The LH5030 is a common driver CMOS LSI for
LCD dot matrix graphic display. A built-in CR
oscillator generates synchronous signal and clocks
necessary for display to send to a segment driver.
l~~~~E<~=U~~~»~oOO
~~~~~
~~~~Z»»Z>Q~Q~~~~~~~~~~
717
6766
6266
5
5
5
5549
8 BPs
0
47 BP6 .
46 BP1
45 BP,
44 BP,
•
Features
43 BP10
42 BPIl
BPlit
,
BPe8
BP61
1. Common outputs : 80 bits
2. Built-in CR oscillator
3. Selectable duty ratio
1/32,1140, 1164, 1180 duty
(2 pairs of common output, if 1132, 1140)
4. Power supply voltage: 5V (TYP.)
5. Display voltage: 15V (MAX.)
6. 96-pin quad-flat package
41 BP12
BP66
BPIJ
BPI4
BP658
BPIS
1111
4116171819
12
Top View
•
Block Diagram
Frame Sync. Clock
r-----~55ir------------,
LCD Driver
Test 54
Input
LCD
AC
Generator
Decoder
OSC
L---------------{i56r-------{
Display Clock
892
Counter
Frame
Sync.
Controller
LH5030
LCD Dot Matrix Common Driver CMOS LSI
•
Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Symbol
Vee
VDP
VTl
VT2
Toor
Totg
Ratings
-0.3-+7.0
-0.3-+16
-0.3-V ee +0.3
-0.3-VDP +0.3
-5-+55
-55-+150
Unit
V
V
V
V
"C
"C
Note
1
1
1,2
1,3
Note 1: Referenced to GND
Note 2: Applicable to pins HS" ; 0, RX, RY, DY 0, DY 1
Note 3: Applicable to pins BP o-BP79, V A, VB, VM
•
Recommended Operating Conditions
Parameter
Supply voltage
Display voltage
•
Symbol
Vee
VDP
MIN.
4
6
TYP.
MAX.
6
15
(Vee=5V±lV, VDP =6-15V, Ta=-5-+55"C)
DC Characteristics
Parameter
Input voltage
Output voltage
Output current
Input leakage current
Output leakage current
Current consumption
Unit
V
V
Symbol
VIR
V1L
VOH
VOL
IA
Is
IOH
10M
IOL
I ILl I
I lLO I
Icc
IDP
Conditions
IOH=400pA
IOL =1.6mA
VDP -V A=lV, VDP =6V
VB =lV, VDP =6V
VDP -VoH =lV, VDP =6V
VM-V OM =lV, VDP =6V
VoL =lV, VDP =6V
V1N=OV or Vee
HSi. Po: VOUT=OV or Vee
BPo-BP79: VOUT=OV or VDP
VDP =15V. Vee=6V no load
Durling no-load display (f ~ =8kHz. 1/80 duty)
MIN.
2.4
0
2.4
TYP.
MAX.
Vee
0.8
0.4
10
10
1.5
1.5
1.5
Unit
Note
V
4
V
5
mA
6,8
mA
7
4
30
30
5
5
5
0.1
1
pA
0.1
1
pA
50
2
150
6
pA
pA
9
Note
Note
Note
Note
4: Applicable to pins DY o• DY 1; Vcc =5V±10%
5: Applicable to pins HS i• ;0; V cc =5V±10%
6: Applicable to pins VA, VB
7: Applicable to pins BPo- BP 79
VOH and VOL are the high and low voltage resulting when the scan signal is output to the common pin. When the voltage
division resistance R for display equals r. (See System Configuration Example.)
Note 8: This specification prescribes the internal transistor drive force of the LSI. The normal maximum effective current of IA • IB is 10
mAo
Note 9: When pins VA. V M and VB are open.
893
LH5030
LCD Dot Matrix Common Driver CMOS LSI
•
(V ee =5V±IV, Vop =6-15V, Ta=-5-+55"C)
AC Characteristics
Parameter
Sync. signal delay
Display clock frequency ( ~ 0)
Symbol
to
f~
Conditions
~ 0, HSi pin load CL =15pF
Rf=R~±2%, Vee =5V±10%
MIN.
50
fo-30%
TYP.
100
fo
Note 1: When f+ =l/tRc, Ro=530kO, fo=3.0kHz
Note 2: When fo=2.24kHz-8.0kHz (Combination range of R, resistance)
i----tRCo-----.f
•
Pin Description
Pin name
Vee, GND
Vop, VA, VM• VB
DYo• DY 1
T
RX
RY
HS j
~o
BP o-BP 79
894
No. of pins
3
4
2
1
1
1
1
1
80
I/O
I
0
Functions
Power supply for logic circuit
Power supply for liquid crystal drive
Duty selectinput
Test input
Internal clock oscillation pin
Internal clock oscillation pin
Frame sync. signal
Display clock
Liquid crystal common drive signal
MAX.
fo+30%
Unit
ns
Note
1,2
LH5030
LCD Dot Matrix Common Driver CMOS LSI
•
System Configuration
L
Vr CLo SDo ;0 HSi
CH LC
..
LH5035A
~Vr~
VDP VA VB
~.
R
II
C~·
___ I
~r
~.
r
i.
C:
R'
V RX RYDX.DYI
DP
VA
BPo
\' ~
VM· LH5030 BP 39 Pl!...V
BP ••
\
VB
BP79
GND
Vee 1/10 HSi
4.
~S
LH5035A
SO-S79
~~
~~
\
\
Dot matrix LCD
0------79 -- --- ----- --- - - - --- - ---- --- - ---- - 560 ------639
8~
8~
J
SC-S79
LH5035A
4
CS~ GND
LClCH
HSi _. SDo CL.
5
---------------------
SO-S79
39
0
Vee
Vee, GND
VDP,VA,VB·
I-f-cs
l l 1
L
CLo SDo ;0 HSi
CH LC
0 0------79 - - --- - - - -- - - --- - - - - --- -- ---- -- 560 - - ----639
~ 39
"'"
L
v
4
TTT
SO-S79
~--------------------
LH5035A
4
CS-+--"
HS;
~o
LClCH
SD. CL.
f f t f
~
CPU{
" ..--..-~------SHARP-.-.-.-----
895
LH5031
LCD Dot Matrix Common Driver CMOS LSI
LH5031
•
LCD Dot Matrix Common Driver CMOS LSI
•
Description
Pin Connections
The LH5031 is a common driver CMOS LSI for
LCD dot matrix graphic display. A built-in CR
oscillator generates synchronous signal and clocks
necessary for display to send to a segment driver.
•
Features
l.
2.
3.
4.
5.
6.
Common output: 32 bits
Built-in CR oscillator
Duty ratio: 1/32 duty
Power supply voltage: 5V (TYP.)
Display voltage: 15V (MAX.)
44-pin quad-flat package
Top View
•
Block Diagram
~
______
Output
__________
~~A
~,
Frame Sync. Clock
}----'---(24}---------.,
LCD Driver
Test 23
Input
LCD
AC
Generator
Decoder
Counter
OSC
LCD
Power
Supply
Frame
Sync.
Controller
L-------------~25r-------------------------------------~
Display Clock
--------SHARP-----------896
(
LCD Dot Matrix Common Driver CMOS LSI
•
LH5031
Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Symbol
Vee
Vop
VTl
VT2
Topr
T s'"
Ratings
-0.3-+7
-0.3-+16
-0.3-Vee +0.3
-0.3-Vop +0.3
-5-+55
-55-+150
Unit
V
V
V
V
"C
"C
Note
1
1
1,2
1,3
Notel: Referenced to GND
Note 2 : Applied to pins HS;, 1> 0, RX, RY, DY o, DY 1
Note 3 : Applied to pins BP o-BP 79, VA, Va, VM
•
Recommended Operating Conditions
Parameter
Supply voltage
Display voltage
•
Symbol
Vee
Vop
Output voltage
Output current
Symbol
VOH
VOL
IA
IB
IOH
10M
IOL
Output leakage current
Iw
Current consumption
Icc
lop
Note 4
Note 5
Note 6
TYP.
MAX.
6
15
Unit
V
V
(Vee=5V±lV, Vop =6-15V, Ta=-5-+55"C)
DC Characteristics
Parameter
MIN.
4
6
Conditions
MIN.
IoH =400 pA
Vee- O.S
IOL =1.6mA
VOP-VA=lV
10
VB=lV
10
Vop -VoH =lV
1.5
VM-V OM =lV
1.5
VoL =lV
1.5
HS j , ~ 0 : VOUT=OV or Vee
BPo-BP 31 : VOUT=OV or Vop
Vop =15V, Vee=6V Durling
no· load display (f ~ = 3.2kHz)
TYP.
MAX.
O.S
30
30
5
5
5
Unit
Note
V
4
rnA
5
rnA
6
0.1
1
pA
25
1
SO
3
pA
Applicated to pins HSi, 1>0; Vcc =5V±10%
Applied to pins VA, Va
Applied to pins BPo, BP 31
V OH and VOL are the high and low voltages resulting when the scan signal is output to the common' pin.
---------SHARP---~-----897
LCD Dot Matrix Common Driver CMOS LSI
•
LH5031
AC Characteristics
(V ee =4-6V, Ta=-5-+55t:)
Parameter
Sync. signal delay time
Display clock frequency ( <} 0)
Symbol
tn
Conditions
f~
Rf =Ro ±5%
MIN.
50
fo -30%
TYP.
fo
MAX.
Unit
ns
Note
1,2
fo+30%
Note 1 :. When f~ =lItRc, Ro =850kO, f o=2kHz
Note 2 : When fo= 1012kHz-3.2kHz (Combination range of R, resistance)
i----tRc----ooj
1/>10
•
Pin Description
No. of pins
3
4
1
1
1
1
1
32
Pin name
Vee, GND
VDP, V A, VM, VB
T
RX
RY
HSi
<}o
BPo -BP 31
•
I/O
I
0
Functions
Power supply for logic circuit
Power supply for liquid crystal drive
Test input
Internal clock oscillation pin
Internal clock oscillation pin
Frame sync. signal .
Display clock
Liquid crystal common drive signal
,
System Configuration
~
VDP 'fA VB
~~ Rl
~~ ~r
Ca"
r
C/"
ER
::'1
RY
VDp RX
0,
VA.
BPo
V LH5031 I ~ :
M
BP31 ---y'
VB
31
GND
Vee
~Ir
"'0
,
Dot matrix LCD
0------ 79------------- ----------- ---------- 560----·-639
8
80-879
vL
LH5036A
HS, ¢o SDo LC CLo
5
SO-S79
----------------------
4
C8-+"
Vcc, GND
VP,VA,VB
ls~
11
H8;
Tf i
4
CS+-;>
LH5036A
HS; ;0 SDo LC CLo
iii
cpu{
.---~----SHARP.-..------.- ...... -
898
-
LH5003/LH5004
LCD Character Display CMOS LSI
LH5003/LH5004
•
Description
The LH5003/LH5004 are dot-matrix LCD controller driver capable of displaying 128 kinds of
alphanumeric and symbolic characters. They are the
most suitable LSls for constructing small dot-matrix LCD systems under under the control of 4-bit
or 8-bit microcomputer.
•
•
LCD Character Display
CMOS LSI
Pin Connections
LH5003
~ Q
z _ _ ;>
u~ "~ ~
U Q
Features
1. CMOS process
2. 5 X 7 dot-matrix LCD controller/driver
3. Display data RAM
240 bits (LH5003)
320 bits (LH5004)
4. Character Generator 128 patterns
5. Driving method duty··· 118 duty
6. Character configuration is 5 X 7 dots plus
cursor
LH5003 (Master) 6 digits
LH5004 (Slave)
8 digits
7. LCD drive circuit
LH5003 ; Common signal 8 bits
Segment signal 40 bits
LH5004 ; Segment signal 30 bits
8. Single power supply: - 5V (TYP.)
9. 60-pin quad-flat package
N_ln..,.""'="'_'"''''
0000000>0000000
Top View
LH5004
~ ~ ~ ~ z
u CG U
.0
S
Top View
......-.---------SHARP--~---------
899
LCD Character Display CMOS LSI
•
LH5003/LH5004
Block Diagram
LH5003
Common Output··
Clock
Segment
Output
Data Input
,
Segment Output
LH5004
Segment Output
Display
Control
Signal
Data
Control
Signal
Segment
Output
Data Input
.
Segment Output
-"~------SHARP-'-'------
900
LH5003/LH5004
LCD Character Display CMOS LSI
•
Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
•
Symbol
Voo
VIN
Toor
T st•
Ratings
-0.3-+8.0
-0.3-V oo +0.3
-10-+60
-55-+150
Unit
V
V
"C
"C
Recommended Operating Conditions
Parameter
Supply voltage
Oscillator frequency
•
Symbol
Voo
fCLK
Ratings
4.2-6.3
32-320
(V oo =5V,GND=OV, Ta=-10-+60"C)
Electrical Characteristics
Parameter
Input voltage
Input current
Output voltage
Current consumption
Note
Note
Note
Note
Note
Note
Note
Note
1:
2:
3:
4:
5:
6:
7:
8:
Symbol
VIL
VIH
VM
VA
VB
IlL
IIH
VaLl
VOHI
VaLl
VOHI
VOL3
VOM -VOH3
1m
102
103
Unit
V
kHz
Conditions
MIN.
TYP.
MAX.
1
Unit
1
4
3.5
0
2.5
4
1
VIN=OV
VIN =5V
No-load condition
I 10L I =50 pA
10H= 50 pA
No-load condition
fCLK =32kHz
fCLK =64kHz
fCLK =320kHz
V A-0.2
VB
VA
V
5
1.5
1
1
V B+O.2
V M -0.2
4.8
pA
1
5
0.2
VM+0.2
50
100
400
~
r-V
0
VM
5
28
60
220
r--
c--L
4
0.8
4.2
Note
6
r-7
pA
8
Applied to pins 10 -1 7, VFL, CLK, RST, CE, DISP, DIN
Applied to pin VM
Applied to pin VA
Applied to pin VB
Applied to pins OU-OS5
Applied to pin CS
Applied to pins HI-Hs
Output pin is opened and input pin set to GND level.
------------SHARP---------901
LCD Character Display CMOS LSI
•
LH5003/LH5004
Functions
Pin description
Pin name
Voo, GND
No. of pins'
VA, VB, VM
3
10 -1 7
8
DIN
1
DSP
1
CLK
1
RST
1
CE
1
CS
1
VFL
1
H1 -H 2
0 11 -0 15
8(0)*
30(40)*
110
Connect to
3
Power supply
I
MPU
Power
supply (CS) *
CE
0
MPU
Liq uid crystal
Functions
Power supply for logic circuit
Power supply VM=VOO/2
for liquid
VA=VM+~V
crystal drive VB=V M- ~ V (~V=1.0-VM)
Character code input (10 - 16 ) from MPU
Cursor display data input (I7)
High: character data read
one character shift in display memory
"High" : Display mode
"Low" : Blank mode
(reset of cascade control data
transfer control circuit)
Clock pulse input
"High" : Operation start signal
(reset of cascade controller, cascade control
data transfer control circuit, ring counter, etc.)
Chip enable pin
-
. Chip select pin
LCD frame frequency swithcing signal
"High: 111024 of clock frequency
"Low" : 11512 of clock frequency
LCD common signal drive signal
LCD segment signal drive signal
*Applied to LH5004
• elK signal
The clock signal is a clock pulse
used to operate LH5003 and LH5004 and is continually applied while the power is on. For the CLK
signal, apply the clock pulse made in the micro- .
computer system or a pulse made by dividing this
clock pulse and in sync with the microcomputer
system.
• DIN signal
The DIN signal is used to set the
data in the display memories of LH5003 and
LH5004. Each time the DIN signal rises, it reads
display data corresponding to the character code
applied to pins 10 through 17 into the display memory and shifts the existing contents of the display
memory one character. Set the pulse width of the
DIN signal to at least two cycles of the clock pulse
(a pulse width of 2TCK or greater when the clock
pulse period is T CK.)
• DSP signal
The DSP signal determines the
display condition. When it is high, the display
mode is set and when it is low, the blank mode is
set and the cascade controller and data transfer
control circuit are reset. Normally, the nsp signal
is made high after setting the data in the display
memories of the LH5003 and LH5004.
902
• RST Signal
The RST signal is used to initialize the internal control circuits of the LH5003
and LH5004 by applying the pulse of the RST signal to this pin immediately after the power is
turned on. Synchronize the fall of the RST pulse
with the rise of the clock pulse, and set the pulse
width of the RST pulse to at least four times that of
the normal clock pulse width (4 T CK .)
• 10-17 signal
The 10-17 signal is an 8-bit parallel signal that determines the characters and symbols to be displayed. Select the desired characters
using the data of pins 10-16 (see the table relating
input codes with displayed characters and symbols). When the h signal is high, the cursor is displayep, and when it is low, the cursor is displayed,
and when it is low, the cursor is blanked out.
LH5003 and LH5004 are controlled from the microcomputer system by the following procedure.
(1) The clock pulse is applied continually to the
CLK pin during the period from immediately
after the power is turned on until it is turned
off.
(2) Immediately after the power is turned on, the
RST pulse is applied to the RST pin.
LCD Character Display CMOS LSI
(3)
The DSP and DIN pins are made low. (Not
necessary if they are already low.)
(4) The character code of the character to be displayed is output to pins 10-17.
(5) The DIN pin becomes high level and -then low
level again. (Apply one pulse to the DIN pin.)
•
LH5003/LH5004
(6) Steps 4 and 5 are repeated for each display
position.
(7) The DSP pin is made high level. (This condition sets the display mode.)
(8) The contents of the display are changed by repeating steps 3 through 7.
Input Codes and Displayed Characters and Symbols
(LH5003/LH5004)
- - - - - - - - S H A R P --.-.....-.-..------------
903
LH5003/LH5004
LCD Character Display, CMOS LSI
•
System Configuration
-
-\ H -H8
~
5x7 dot matrix LCO (with cursor)
1
r--
~-t-lI
Micro computer
system
I
,..... .............
10 l?
-
(;11-( 65
GNO
H 1 -H 8
r---
LH5003
VM
CE
CS,
eLK DSP DINRSTVDD VA VB
r
CLK
OSP
DIN
RST
V DDJ
t
f
1
Rl"i
::Cl
R21
::C2
~
Rs
R.
U
1."
904
U
-l}
I
___ -II
0,
30
J
I
I
0 71 ,-0 145
0 11 -065
8
,.C s
C•
iJ
10 l?
40
0 11
0 85
GNO
LH5004
CE
OSP
CLK DIN RSTV D VA VB
t
Jf
n
LH1001
VFD Grid Driver PMOS LSI
LH100 1
•
VFD Grid Driver PMOS LSI
•
Description
Pin Connections
The LHIOOI is a VFD (Vacuum Fluorescent Dis·
play) grid driver with an internal 20-bit serial
shift register. Can be easily cascaded to extend
the display.
•
Features
L
2.
3.
4.
5.
6.
7.
•
Included 20-bit shift registers in a serial input
Data controlled by shift clock and chip select
Blanking input controlled by duty cycle
High output voltage: - 50V (MAX.)
High output current: 20mA (MAX.)
Built-in output load resistor
36-pin quad-flat package
Top View
Block Diagram
Serial Data Output
~----------------------------{6r-----------~------------,
Serial{ 8
Data
Input
9
Chip Select 1 r---------.,>i
20bit Serial Shift Register
Blanking 2}------------i;.j
Serial 3}----------i-L________________---.-r________________--.J
Clock
Input
Serial Data
Output
11
VN (-50V)
~--------------~vr--------------~
Output
-------------SHARP--------905
VFD Grid Driver PMOS LSI
•
LH1001
Absolute Maximum Ratings
Parameter
Pin voltage'"
V ss allowable current
Operating temperature
Storage temperature
Symbol
Voo
VN
VIN
Iss
Toor
T sto
Ratings
-20-+0.3
-55-+0.3
-55-+0.3
70
-5-+55
-55-+150
Unit
V
rnA
'C
'C
*Referenced to GND.
•
Recommended Operating Conditions
Parameter
Supply voltage
Display voltage
•
Symbol
Voo
VN
MIN.
-9.9
TYP.
MAX.
-8.1
-40
Unit
V
V
(V oo =-9V, Ta=25'C)
DC Characteruistics
Parameter
Input voltage
Output voltage
Output current
Current consumption
Note 1:
Note 2:
•
Symbol
VIH
VIL
VOH
VOL
IOH
IOL
100
IN
MIN.
-1.1
Conditions
TYP.
Unit
-1
IoH =20mA
VN =-50V
VoH =-1.1V
VoL =-4.2V
Voo =-9V
VN=-50V
-48
50
3
.3
1.5
4.0
Note
V
-4.2
V
1
pA
2
rnA
8
Applied to pins DG 1 -DG 20
Applied to pins SOlO. SOzo
(V oo =-9V, Ta=25'C)
AC Characteruistics
Parameter
CK frequency
CK cycle time
CK high·level width
CK low· level width
SI setup time
SI hold time
CK high active time
CK low active time
CK ! -+ SO delay time
Output delay time
Symbol
tcK
t KSY
tKH
tKL
tSIS
tSIH
tcSBKL
tCSBKH
tKso
tu
to
MIN.
Conditions
TYP.
MAX.
40
25
12
12
6
6
0
' 6
CL=10pF
VN =-50V, CL=100pF
-~------"'-'-'-----SHARP
.906
MAX.
...
3
15
20
5
20
Unit
kHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
--------.-
VFD Grid Driver PMOS LSI
•
LH1001
AC Timing Diagram
CK
CS
BK
SOlO
S020
Sh
SIz
10%
•
Pin Description
No. of pins
3
1
1
1
1
Pin name
Von, GND
VN
CS
BK
CK
Silo SI2
SOlo, S020
DG 1 -DG 20
I/O
I
2
2
20
0
Functions
Power supply for logic circuit
Power supply for display
Chip select ... select condition when CS="Low "
Blanking ...... blanking when BK="High"
Serial clock
Serial data input
Serial data output
Digit output for fluorescent display tube
l="High" level, O="Low" level
•
System Configuration
input
q.
SI2
Sh
S020
CS
BK lHIOOI
Dfl
CK
DG20
5 x 7 dot matrix fluorescent tube display
VN VDD GND
Dot output
Dij
-40V
VN
-9V O - - -......-+----------iVDD j=I-5CEl
(i=1-7)
~------------__IIIGND
l12048CE2
J<;:::J Input
Ao-A9
*CS input must be high level when power is turned on.
Input
-..--.-------SHARP--------
907
CMOS Driver
.......-,....,.-.--.....
~--
-
............... ..........
LH50l0/LH5011
--~
LH5010/LH5011 CMOS Driver
•
•
Description
Pin Connections
The LH5010/LH5011 are 6-circuit CMOS drivers with 2-common INHIBIT inputs (AIN, BIN).
The LH5010 is a non-inverting type and the
LH5011 is an inverting'type.
The outputs have an open drain construction
'fabricated using a P-channel MOS FET.
They are used as drivers for VFD and interfaces
between CMOS LSI and high-voltage MOS LSI.
15
OUT1(OUTd
14 OUT 2 (OUT 2 )
13 OUT3(OUT 3)
12
OUT.(OUT.)
II
OUTs (OUTs)
IOOUT6(OUT6)
•
Features
1.
2.
3.
4.
CMOS process
6 independent driver circuits
INHIBIT input port
Non-inverting type······ LH5010
Inverting type ........... LH5011
5. I6-pin dual-in-line package
•
'(
)= for LH5011
Top View
Block Diagram
High Voltage
Output
lnput
(LH5010)
High Voltage
Output
(Invert Signal)
Input
(LH5011)
----------SHARP.--.--..-~-------
908
CMOS Driver
•
LH5010/LH5011
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
•
Symbol
Ratings
VDD
VscO.5 - Vss+ 2O
Vss -0.5-V oo +0.5
VIN
VOUT Voo-50-Voo+0.5
-40-+85
To ~
-55-+125
T sto
Unit
V
V
V
"C
'c
Operating Conditions
Parameter
Supply voltage
Input voltage
•
Symbol
VDD
VIN
MIN.
3
0
TYP.
MAX.
18
VDD
Unit
V
V
Electrical Characteristics
Parameter
Symbol
Output high voltage
VOH
Output high current
IOH
VIH
Input voltage
VIL
Input current
IIH
IlL
Output leak·off
current
IOFF
Static current
consumption
IDD
Note
Note
Note
Note
VDD
(V)
5
I louT I ~1 pA
10
VIN=VSS or VDD
15
VoH =3V(V oo -2V)
5
VoH =2V(V oo -3V)
5
VoH =7V(V oo -3V)
10
VoH =12V(V oo -3V) 15
VouT=0.5V,4.5V
5
VOUT -1.0V, 9.0V 10
VouT =1.5V, 13.5V 15
VouT=0.5V,4.5V
5
VOUT= 1.0V, 9.0V 10
VouT =1.5V, 13.5V 15
VIH =18V
18
18
VIL=OV
15
VOUT=OV
VOUT =V DD -45V 15
5
VIN=VDD, Vss
10
output open
15
Conditions
-40"C
MIN. MAX.
4.95
9.95
14.95
-6
-9
-12
-17
3.5
7.0
11.0
1.5
3.0
4.0
0.3
~0.3
3
10
4.0
8.0
16.0
25"C
80"C
MIN. TYP. MAX. MIN. MAX.
4.95 5.00
4.95
9.95 10.00
9.95
14.95 15.00
14.95
5 -9
4
8 -11
6
-10 -28
--:8
-15 -39
-12
3.5 2.75
3.5
7.0 5.5
7.0
11.0 8.25
11.5
2.25
1.5
1.5
3.0
4.5
3.0
4.0
6.75
4.0
0.3
1.0
10 5
-10 5 -0.3
1.0
3
10
10
20
4.0
30
8.0
60
16.0
120
Unit
Note
V
1
rnA
1
V
2
V
2
pA
3
pA
1
pA
4
1: Applicable pins OUT j -OUT 6
2: RL =20kO, Applicable pins 1N.L:1N6' AIN BrN
3: Applicable pins IN j -IN 6 AlN, BrN
4: No load condition
-------------SHARP.-.---.-.--909
CMOS Driver
•
LH5010lLH5011
Truth Table
Input
AIN
L
L
*
H
B;
H
H
L
*
HZ : High impedance
Don't care
IN
L
H
*
*
Output
LH5010
LH5011
HZ '
High
HZ·
High
HZ
HZ
HZ
HZ
*:
•
Logic Diagram
• LH5010
• LH5011
IN,
IN2
OUT,
910
OUT2
INs
IN.
INs
INs
OUTs OUT. OUTs·· OUTs
LH501 OD/LH5011 D
CMOS Driver
LH5010D/LH5011D CMOS Driver
•
•
Description
Pin Connections
The LH5010D/LH5011D are 7 -circuit CMOS
drivers with 2 common INHIBIT inputs (A IN , BIN).
The LH5010D is a non-inverting type and the
LH5011D is an inverting type.
The outputs have an open drain construction
fabricated using a P-channel MOS FET.
They are used as drivers for VFD and interfaces
between CMOS LSI and high-voltage MOS LSI.
17 OUT 1 (OUT I )
150UT3(OUT3)
140UT.(OUT.)
130UT,(OUTs)
120UT6(OUT6)
11 OUT 7(OUT7)
•. Features
1.
2.
3.
4.
CMOS process
7 -independent driver circuits
INHIBIT input port
Non-inverting type ...... LH5010D
In verting type . . . . .. .. ... LH 5 011 D
5. 18 -pin dual-in -line package
•
)= for LH5011D
Top View
Block Diagram
Inhibit Signal
High Voltage
Output
Input
High Voltage
Output
(Invert ~ignaI)
Input
Inhibit Signal
Inhibit Signal
(LH5010D)
(LH5011D)
'-'-'-'---~--SHARP------------"-'
911
LH501 OD/LH5011 D
CMOS Driver
Absolute Maximum Ratings
•
Ratings
Symbol
VDD
Vss-0.5- Vss+20
Vss -0.5-V oo +0.5
VIN
VOUT VoO -50-V DD +0.5
-40-+85
Topr
-55-+125
Tst£
Par.ameter
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
•
Unit
V
V
V
°C
°C
Operating Conditions
Parameter
Supply voltage
Input voltage
•
Symbol
VDD
VIN
MIN.
3
0
TYP.
MAX.
18
VDD
Unit
V
V
Electrical Characteristics
Parameter
Output high
voltage
Output high
current
Symbol
VOH
IOH
VIN
Input voltage
VIL
Input current
IIH
IlL
Output leak·off
current
IOFF
Static current
consumption
IDD
Note
Note
Note
Note
1:
2:
3:
4:
Conditions
I louT I ~1
pA
VoH =3V(V DD -2V)
VoH =2V(V DD -3V)
VoH =7V(V DD -3V)
VoH =12V(V nn -3V)
VouT=0.5V,4.5V
VouT =1.0V,9.0V
VouT =1.5V, 13.5V
VouT=0.5V,4.5V
VOUT= 1.0V, 9.0V
VouT =1.5V, 13.5V
VIH =18V
VIL=OV
VOUT=OV
VOUT=VDD-45V
VIN=VDD, Vss
output open
Vnn
(V)
5
10
15
5
5
10
15
5
10
15
5
10
15
18
18
15
15
5
10
15
-40·C
MIN. MAX.
4.95
9.95
14.95
-6
-9
-12
-17
3.5
7.0
11.0
1.5
3.0
4.0
0.3
-0.3
3
10
4.0
8.0
16.0
25"C
80"C
'Unit Note
MIN. TYP. MAX. MIN. MAX.
4.95
4.95 5.00
V
1
9.95
9.95 10.00
14.95
14.95 15.00
-9
-4
-5
-8 -11
-6
rnA'
1
-10 -28
-8
-15 -39
-12
3.5 2.75
3.5
7.0
V
2
7.0
5.5
11.0 8.25
11.5
2.25
1.5
1.5
2
V
4.5
3.0
3.0
6.75
4.0
4.0
10 5
0.3
1.0
pA
3
-10 5 -0.3
-1.0
3
10
pA
1
10
20
4.0
30
pA
4
8.0
60
16.0
120
Applicable pins OUT1-OUT7,"VIN=Vss or VDD
RL=20kO, Applicable pins IN1-IN7, AIN, BIN
Applicable pins IN1-IN7, AIN, BIN
No load condition
--.----~-SHARP-.--'--~-----.-
912
CMOS Driver
•
LH501 OD/LH5011 D
Truth Table
Input
AIN
L
L
*
BIN
H
H
L
IN
L
H
*
*
*
HZ : High impedance
H
Output
LH5010D
LH5011D
High
HZ
High
HZ
HZ
HZ
HZ
HZ
* :Don't care
•
Logic Diagram
• LH5010D
IN7
OUT,
OUT.
OUT.
OUT.
OUTs
OUT6
OUT 7
• LH5011D
IN,
IN.
OUT,
OUT.
IN3
IN.
OUT.
OUT.
INs
OUTs
IN6
OUT6
IN7
OUT 7
- - - - - - - - - - S H A R P -........... . . . - . - - - - . . . . . . . . . ,
913
LH5012/LH5013
CMOS Driver
LH5012/LH5013 CMOS Driver
•
Description
The LH5012/LH5013 are 7 -circuit CMOS
drivers. The LH5012 is a non-inverting type and
the LH5013 is an inverting type.
The outputs have an open drain construction
fabricated using a P-channel MaS FET.
They are used as drivers for VFD and interfaces
between CMOS LSI and high-voltage MaS LSI.
•
Pin Connections
150UT 1 (OUT 1 )
14 OUT 2 (OUT,)
130UT 3 (OUT 3 )
120UT,(OUT,)
II
OUTs(OUT s )
IOOUT 6 (OUT 6 )
•
9
Features
1. CMOS process
2. 7 independent driver circuits
3. Non-inverting type ...... LH5012
Inverting type ........... LH5013
4. 16-pin dual-in-line package
•
OUT 7 ( OUT 7)
)= for LH5013
Top View
Block Diagram
High Voltage
Output
Input
(LH5012)
High Voltage
Output
(Invert Signal)
Input
(LH5013)
----------~--SHARP---'" ........... - . - . - . . . . - -
914
LH5012/LH5013
CMOS Driver
•
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
•
Symbol
Ratings
Vss -O.5-V ss +20
Voo
VIN
Vss-O.5- Voo+O.5
VOUT Voo -50-V oo +O.5
-40-+85
Toor
-55-+125
T st•
Unit
V
V
V
'c
'c
Operating Conditions
Parameter
Supply voltage
Input voltage
•
Symbol
VDD
VIN
MIN.
3
0
TYP.
MAX.
18
VDD
Unit
V
V
Electrical Characteristics
Parameter
Output high
voltage
Output high
current
Symbol
VOH
IOH
VIH
Input voltage
(LH5012)
VIL
VIH
Input voltage
(LH5013)
VIL
Input current
IIH
IlL
Output leak -off
current
IOFF
Static current
consumption
IDD
Note
Note
Note
Note
1:
2:
3:
4:
Conditions
IouT ;;;;l1'A
VoH =3V(V DD -2V)
VoH =2V(V OD -3V)
VoH =7V(V DD -3V)
VoH =12V(V oo -3V)
VouT=4.5V
VouT=9.0V
VouT=13.5V
VouT=0.5V
VOUT =1.0V
VouT =1.5V
VouT=0.5V
VOUT =1.0V
VouT =1.5V
VouT=4.5V
VouT=9.0V
VOUT=13.5V
VIH =18V
VIL=OV
VOUT=OV
VouT=Voo-30V
VIN=VDD, Vss
output open
-40"C
MIN. MAX.
5 4.95
10 9.95
15 14.95
-6
5
-9
5
10 -12
15 -17
3.0
5
10
8.0
15 12.5
1.0
5
10
2.0
15'
2.5
5
3.5
10
7.0
15 11.0
5
1.5
10
3.0
15
,4.0.
18
0.3
-0.3
18
15
3
15
10
5
4.0
10
8.0
16.0
15
r--
Y{?r
25"C
80"C
Unit
MIN. TYP. MAX. MIN. MAX.
4.95 5.00
4.95
9.95 10.00
9.95
V
14.95 15.00
14.95
-4
-5
-9
-8 -11
-6
rnA
-10 -28
-8
-15 -39
-12
3.0
3.0
V
8.0
8.0
12.5
12.5
1.0
2.0
V
2.5
3.5
3.5 2.75
7.0
5.5
7.0
V
11.0 8.25
11.0
2.25
1.5
1.5
4.5
3.0
3.0
V
4.0
4.0
6.75
10 5
0.3
LO
I'A
-10 5 -0.3
-1.0
3
10
I'A
20
10
4.0
30
8.0
60 I'A
16.0
120
Note
1
1
2
2
2
2
3
1
4
Applicable pins QUT,-QUT7, V'N=VSS or Voo
RL=20kO, IouT;;;;lI'A, Applicable pins INI-IN7
Applicable pins IN,-IN7
No load condition
'--~--'-'----SHARP----'-----
915
CMOS Driver
•
LH5012/LH5013
Logic Diagram (1 circuit)
• LH5012
Voo
I--C
Vss
• LH5013
Voo
·IN-C
Vss
-.-------~-SHAR/P
916
- - - - ......... --------------...
CMOS Driver
LH5012D/LH5013D
LH5012D/LH5013D CMOS Driver
•
•
Description
The LH50I2D/LH50I3D are 8-circuit CMOS
drivers. The LH5012D is a non-inverting type
and the LH50 I3D is an inverting type.
The outputs have an open drain construction
fabricated using a P-channel MaS FET.
They are used as drivers for VFD and interfaces
between CMOS LSI and high-voltage MaS LSI.
Pin Connections
o
170UT j (OUT j )
150UT 3 (OUT 3 )
140UT 4 (OUT 4 )
13 OUTs (OUTs)
120UT 6 (OUT 6 )
•
11 OUT,( OUT,)
Features
100UT s (OUT s )
1. CMOS process
2. 8 independent driver circuits
3. Non-inverting type ...... LH50I2D
Invertingtype ........... LH50I3D
4. I8-pin dual-in-line package
•
)= for LH5013D
Top View
Block Diagram
Input
High Voltage
Output
(LH5012D)
High Voltage
Output
(Invert Signal)
Input
(LH5013D)
'-'---~--~SHARP--------
917
CMOS Driver
•
LH5012D/LH5013D
Absolute Maximum Ratings
"
Parameter
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
•
Symbol
Ratings
Vss -O.5-Vss +20
VDD
Vss -O.5-V DD +O.5
VIN
VOUT VDD -50-VDD +O.5
-40-+85
, Toor
-55-:-+125
T.t2
Unit
V
V
V
°C
°C
Operating Conditions
Parameter
Supply voltage
Input voltage
•
Symbol
VDD :
VIN
MIN.
3
0
TYP.
MAX.
18
VDD
Unit
V
V
Electrical Characteristics
Parameter
Symbol
Conditions
,J
Output high voltage
Output low
current
VOH
IOH
VIH
Input voltage
(LH5012D)
VIL
VIH
Input voltage
(LH5013D)
VIL
Input current
IIH
IlL
Output leak·off
current
IOFF
Static current
consumption
IDD
Note
Note
Note
Note
I louT I ~lpA
VoH =3V(V DD -2V)
VoH =2V(V DD -3V)
VoH =7V(V DD -3V)
VoH =12V(V Do -3V)
VouT=4.5V
VouT=9.0V
VouT=13.5V
VouT=0.5V
VOUT =1.0V
VouT =1.5V
Vn,=0.5V
VOUT =1.0V
VlL =1.5V
VOuT=4.5V
VouT=9.0V
VouT =13.5V
VIH =18V
Vu;=OV
VOUT=OV
VOUT=VDD-30V
VIN=VDD• Vss
,output open
,--
y.qf
5
10
15
5
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
18
18
15
15
5
10
15
-40"(;
MIN. MAX.
4.95
9.95
14.95
-6
-9
-12
-17
3.0
8.0
12.5
1.0
2.0
2.5
3.5
7.0
11.0
1.5
3.0
4.0
0.3
-0.3
3
10
4.0
8.0
16.0
25"(;
80"(;
Unit
MIN. TYP. MAX. MIN. MAX.
4.95
4.95 5.00
V
9.95
9.95 10.00
14.95
14.95 15.00
-4
-5
-9
-8 -11
-6
mA
-8
-10 -28
-15 -39
-12
3.0
3.0
V
8.0
8.0
12.5
12.5
1.0
V
2.0
2.5
3.5
3.5 2.75
V
7.0
7.0
5.5
11.0
11.0 8.25
2.25
1.5
1.5
4.5
3.0
3.0
V
4.0
4.0
6.75
10 _5
-0.3
1.0
pA
-10 5 -0.3
-l.0
3
10
pA
10
20
4.0
30
8.0
60 pA
16.0
120
Note
1
1
2
2
2
2
3
1
4
1: Applicable pins OUTI-OUTs. VIN=VSS or VDD
2: RL=20kO. IouT;:;>;lpA. Applicable pins INI-INs
3: Applicable pins IN.-INs
4: No load condition
-.-----~~-SHARP'~.....--~~-~--
918
CMOS Driver
•
LH5012D/LH5013D
Logic Diagram (1 circuit)
• LH5012D
VDD
IN-t
• LH5013D
IN~
919
___.-__.-_.-_..........
.._......,...._
LR34~6
Analog .Olock CMOS IC
_:.iI._~
LR3428
•
Analog Clock CMOS IC
•
Description
Pin Connections
The LR3428 is a CMOS IC for electronic clocks
using a 4.19MHz crystal, 23-stage frequency divider, motor drive circuit and alarm output buffer.
•
Features
l.
2.
3.
4.
5.
6.
7.
Low power consumption
Low impedance output buffer
Modulated alarm output
Single power supply: + l.5V
1Hz stepper motor drive
4.194304MHz crystal oscillator
8-pin dual-in-line pac.kage
Top View
•
Block Diagram
ll-stage
Divider
12-stage
Divider
Output
Control
Circuit ,
Alarm
Control
Circuit
VDD(1.5V)
920
Reset Input
---'l/"
6
Alarm Output
Analog Clock CMOS IC
•
LR3428
Absolute Maximum Ratings
Parameter
Pin voltage *
Operating temperature
Storage temperature
Symbol
VDD
VIN
VOUT
Topr
Tst2
Ratings
-0.3-+2.5
-0.3-V oo +0.3
-0.3-V oo +0.3
-10-+60
-55-+150
Unit
V
V
V
'C
'C
* Referenced to Vss
•
Parameter
Supply voltage
Oscillator frequency
Oscillation start voltage
•
(Ta=25'C)
Operating Conditions
Symbol
VDD
fose
Vose
Electrical Characteristics
Parameter
Current consumption
Oscillation stability
Output on resistance
Alarm output on resistance
RESET pin pull up resistance
Symbol
IDD
Mlf
Rsatl
(P+N)
Rsat2
(P or N)
RR
Ratings
+ 1.15- + 1.80
4.194304 (TYP.)
1.15
Unit
V
MHz
V
(fosc=4.194MHz, CG =C o =15pF, C1 =400, Ta=25'C)
TYP.
25
MAX.
50
1
Unit
p.A
ppm
Voo=1.2V, RL =1800
50
100
0
Voo=1.2V, RL =9000
150
300
0
Conditions
VDD =1.5V
Voo= +1.2-+ 1.7V
Voo =1.5V, VIN=OV
MIN.
10
kO
--...-...-..--.----.-SHARP . - . - . - - - - - 921
_
........................... ....................-..-........................ .
Analog Clock CMOS IC
•
LR3428
J
Output Waveform
(1) OUT1,OUT2
-.;o+-+-:31.25ms
,
t-ls~
I
I
I
"----i--,....--Ir
. . -----Jn~-+!
--:":18...
i:
z
OUT _ _---I
I
I
RESET
(2)
I
LJi--~
U
I
I
I
1
Alarm output
,4t'-6.25ms -t-t-125ms ~8kHz
III~III"III~, J~IIIIIIII~II
.. ~OOm!1500m _
ALoUT
0(
1111111111111111111\
'
i
1,
I
-----------~'
~'-----------
LJ
RESET
•
1
I
~~
:
I
11111111,1111111
System Configuration
o
+-------12
Alarm Output
L -_ _--{
M }--_ _ _--l
Stepper Motor
I'
\
.--.------------$HARP .-----.-.....-.-..----
922
Analog Clock CMOS IC
LR3429
•
LR3429·
Analog Clock CMOS IC
•
Description
Pin Connections
The LR3429 is a CMOS IC for electronic clocks
using a 4.19MHz crystal, 23-stage frequency divider, motor drive circuit and alarm output buffer.
•
Features
1.
2.
3.
4.
5.
6.
7.
Low power consumption
Low impedance output buffer
Modulated alarm output
Single power supply: + 1.5V
1Hz stepper motor drive
4.194304MHz crystal oscillator
8-pin dual-in-line package
Top View
•
Block Diagram
0,,;11 ."•• {
ll-Stage
Divider
12-Stage
Divider
Output
Control
Circuit
Alarm
Control
Circuit
Vss(OV)
VDD (l.5V)
} Mo!
932
.~ .~
"" c
~~
-<
...El
:is
.~
1~
., ...
. . '"
e~
3,e- Il.._
<0
"
~ ...
..
t::
rn
0'"
"i.!
;;;00
Analog Clock CMOS LSI with Electronic Melody Generator
•
LR3465
Absolute Maximum Ratings
Parameter
Pin voltage *
Storage temperature
Operating temperature
* Referenced
•
to
Symbol
Vss
, VIN
VOUT
T st•
Tonr
Ratings
-0.3-+0.3
Vss -0.3-+0.3
Vss -0.3-+0.3
-55-+150
-10-+50
Unit
V
V
V
"C
"C
Ratings
-2.0--1.2
32.768 (TYP.)
-1.4
Unit
V
VDD
Operating Conditions
Parameter
Supply voltage
Oscillator frequency
Oscillation start voltage
•
Symbol
Voo
fose
Vose
kHz
V
(Voo=OV, Vss =-11.5V, Ta=25"C)
Electrical Characteristics
Parameter
Current consumption
Oscillation start time
Input voltage
Input current 1
Input current 2
Output current 1
Output current 2
Output current 3
Output current 4
Output voltage
Output pulse width
Output cycle
Output phase difference
Oscillation stability
Note
Note
Note
Note
Note
Note
Note
Note
Note
1:
2:
3:
4:
5:
6:
7:
8:
9:
Symbol
Isss
Issa
Tosc
V!H
V1L
I!HI
I!H2
IOHI
IOH2
IOL2
IOH3
IOL3
IOH4
IOL4
VOUT
t
TI
T2
Mlf
Conditions
Standby no load
Melody-ON no load
Voo=1.4V
MIN.
TYP.
MAX.
5
1
10
-0.3
VIN=OV
V1N=OV
VouT =-0.5V
VOUT= -0.5Y.
VOUT =-1.0V
VouT =-0.5V
VOUT =-1.0V
VouT =-0.5V
VOUT =-1.0V
Vss= -1.2V, RL =3000
2
10
250
3
3
5
200
200
5
0.9
-1.2
10
200
31.25
2
1
Vss =-1.7-1.2V
2.5
Unit
pA
mA
s
V
V
pA
pA
pA
pA
pA
pA
pA
pA
pA
V
ms
s
s
PPIlVO.IV
Note
1
1
2
2
3
4
5
6
7
8
9
9
9
1
Cn=Cc=22pF
,
Applies to STl, ST, -S3, MA pins
Applies to SI pin. Melody OFF time
Applies to EVl, EV, pins
Applies to SOl, SO, pins
Applies to ML pin. The value of 10H for melody OFF time.
Applies to MH pin. The value of IOL for melody OFF time.
Applies to PI, p, pins. RL= 300 (} (Refer to the right figure.
Refer to clock specifications.
933
AnaJog Clock CMOS LSI with Electronic Melody Generator
•
Clock Specifications
Predominant melody interval
Predominant envelope control
Accompaniment interval
Accompaniment envelope control
Note length control
'PII
~t~
J41..-~_"""",n
___
I.TI~
I
,I
P 21 :
n ...---.. .rL
According to the state of the music select input Sl-S3, one music will be selected from the
8 pieces of music available. The pull-down
,resistor built into the music select pins allows
the pins to be used either connected to Vss or
open.
If the music select input state is altered in the
middle of performance, the music then specified will be performed from the start. A
music selection for the LR34651 in which 8
pieces of music is written in is shown in the
table below.
'--T~
I
,I
By altering PLA, the output pulse width t
can be selected from the following: 15, 31, 46,
62, 78, 93, 109 (ms)
Second counting will be performed and the
output for the step motor will turn off while
the SS input is ON. On turning the SS input
OFF, the second counter is enabled to start.
(Maximum error: 31.25ms).
•
LR3465
Melody Specifications
Up to 8 pieces
600 steps X 13 bits
2 sources
2.5 octaves
For the sounds in parentheses (
), only
the attack sound output will be generated.
15 speeds for each music (The minimum note length shall be selected from between 31
-468ms).
2 kinds (Other notes of different
length can be represented by the different number
of steps.)
,
(Example) If the fastest note in a music is "
the kinds of note that can be specified by 1
step are '_and 1>. The note length control is
by "I" and "0".
J = 1> (1) + 1> (0) ............................... 2 steps
J. = 1> (1) + 1> (0) + 1>(0) ····,··············3 steps
iY = 1> (1) + )l (0) .............................. 2 steps
The number in parentheses (
) represents envelop control.
1-15 times, endless
Melody command
.
snooze command
Control command
Jump command
Repetition number setting
'
comniand
End command
1
934
Music select
input
Name pf music
SI S2 S3
H H H Westminster
L H H Westminster
H L H
Spring (Four
L L H
seasons) Vivaldi
Autumn (Four
H H L
seasons) Vivaldi
Winter (Four
L H L
seasons) Vivaldi
H L L Chime
L L L Alarm
*
*
TemNumber of
repetitions
po
J = T3=VDD T3=V55
68.6
96
96
1
1
8
1
1
1
96
10
1
96
8
1
40
5
1
192 Endless Endless
240 Endless Endless
Twinkle twinkle little star French music
Ii: VDD
L : Vss or open
(1) One shot type
Jl......___.....;._~n..____
Start input ST
Mode input MA
ON
Melody output OFF
Auto stop
Forced stop
LR3465
Analog Clock CMOS IC with Electronic Melody Generator
_ _ _. -_ _. - _. . . .. - . - . -. . .ra. . . . . . ._ . - _
(2) Hold type (Number of repetitions 1-15
times)
(3)
Hold type (Number of repetition Endless)
Start input
ST.J
Mode input
MA--------------
S tart input S T
Mode input MA
ON
L
r------------------,L-
Melody output OFF...J
ON'
Forced stop/
Melody output OFF'
Forced stop
Snooze function allows each music to be
programmed into the mask ROM independently_ However, the number of musics that can be
selected will be reduced because a program in
snooze function is one of the melody programs.
•
System Configuration (LR34651)
3.3JlF
+
LR34651
L5V
33JlF
Note TR,: 2SC1383
TR,: 2SA683
Envelope waveform is determined by
the value of R applied to pins No. 14
and No. 15.
Make sure that pins No. 10 and No.
12 are to be connected to No. 11.
Make sure that pin No.2 is to be connected to pins No. 11 or No. 21.
935
LR3441
LCD Digital Clock CMOS LSI
LR3441
•
LCD Digital Clock CMOS L8.I
•
Description
Pin Connections
The LR3441 is CMOS LSI for LCD display
clocks with a basic three function, daily alarm,
hourly alarm and timer.
•
Features
1. Three functions ("Hour", "Minute", "Second")
"Second" display by colon
2. Alarm function with Snooze function
3. Hourly alarm
4. Timer function
5. Instant second set function (1 - 59 sec ..... No
carry to the minute digit)
6. 3V dynamic LCD drive
7. 32.768kHz crystal oscillator
8. Single power supply : - 1.5V (with voltage
doubler)
•
Block Diagram
Control Circuit
Switch Input
936
Segment Output
"Common
Output
LCD Digital Clock CMOS LSI
•
LR3441
Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Note 1:
Note 2:
Note 3:
•
Symbol
Vss
VEE
VIN
VOUTl
VOUT2
Tope
T stg
Ratings
-2.0-+0.3
-4.0-+0.3
Vss -0.3-+0.3
Vss -0.3-+0.3
VEE-0.3- +0.3
-10-+60
-5.5-+150
Parameter
Supply voltage
Oscillator frequency
Oscillation start voltage
(Ta=25·C)
Symbol
Vss
VEE
fase
Vase
Ratings
-1.8--1.2
2Vss (TYP.)
32.768 (TYP.)
-1.4
Unit
V
V
kHz
V
(Voo=OV, Vss =-1.5V, VEE =-3.0V, Ta=25·C)
Electrical Characteristics
Parameter
Current consumption
Oscillation start time
Segment output current
Common output current
DDC output current
Vc output current
AL (ACloUT. TSoUT
Output current
AL (DCloUT' SLoUT• TMouT
Output current
Pull down resistance
Input voltage
Note
Note
Note
Note
Note
4:
5:
6:
7:
8:
Note
1
1
1,2
1,2
1,3
Referenced to VDD
Applies to Vss pins
Applies to VEE pins
Operating Conditions
•
Unit
V
V
V
V
V
·C
·C
Symbol
MIN.
lov
Conditions
No load
Vss= -1.4V
Vos=0.5V
Vos=0.5V
Vos=0.5V
Vos=0.5V
20
60
60
120
flA
flA
flA
flA
IOHl
VouT=-0.2V
200
flA
IOH2
Vos=0.2V
100
flA
RSI
RS2
RT
VIH
VIL
VIN=OV
VIN=OV
VIN=OV
Vss =-1.8--1.2V
Vss =-1.8--1.2V
I tota 1
Tosc
los
loc
100
TYP.
1.5
MAX.
3.0
10
Vss
flA
s
kO
kO
kO
700
500
100
-0.1
Unit
0
Vss+O.l
V
V
Note
4
4
5
6
7
8
8
Co=Cc=22pF, Cl=C2=O.1 pF
Applies to O.5HIl H, SF pins
Applies to ZA, S" S2, SN ISLoFF, SL, AL pins
Applies to TE, TI" Tl2, IR pins
Applies to O.5HIlH, SF, ZA, S" S2, SN/SLoFF, SL, AL, IND·SEL, ALoFF, 12H/24H pins
........-..-.-.-.----SHARP--------
937
LR3441
LCD. Digital Clock CMOS LSI
,•
Specifications
(1) Input control
Symbol
Sl
S2
SF
ZA
AL
SL
SN/SLoFF
ALoFF
12H124H
INDSEL
IR
O.5HIlH
(2)
(i)
LR3441
Pull down to V1m
Pull down to VDO
Pull down to VDO
Pull down to VDO
Pull down to VDO
Pull down to VDO
. Pull down to VDO
Open' drain
Open' drain
Open' drain
Pull down to VDO
Pull down to VDO
Content
"Hour" set
"Minute" set
Safety
o adjust
Alarm mode switch
Sleep timer mode switch
Snooze "ON" sleep "OFF"
Alarm output "OFF"
12 hours/24 hou~s switch
Indicator select
Initial . reset
Sleep time 32 minutes/64 minutes switch
Operation flow
Function read operation
(iii) 0 adjust
Operates only when the switch is
ON and returns automatically
after OFF
I...._ _ _ _ _ _...J
1-59 seconds are truncable
(iv) Alarm time display adjust operation
(ii) Time display adjust operation
1 push 1 word forward
ON more than 2 seconds
hour digit 1Hz forward
minute digit count up 5 minutes
at a time
(v) Sleep time display adjust operation
1 push 1 word forward
ON more than 2 seconds
hour digit 1Hz forward
minute digit count up 5 minutes
at a time
(Example) 2 --+ 3 --+ 5 --+ 10 ...
Correct from
whichever was
sel<\cted.0.5H/IH
1 push 1 word count down
ON more than 2 seconds count
down 5 minutes at a time
-----------SHARP-----P.....-...-..-"-----938
I
I
LCD Digital Clock CMOS LSI
LR3441
Mode display format
(vi)
Display
Mode
Time display
Time display
adjust operation
Alarm
time
Sleep
timer
SF & S, ON
SF & S2 ON
ALON
AL & S, ON
AL & S2 ON
SL ON
SL & S2 ON
HH :
*1 :
HH
HH :
*1 :
HH
MM
MM
*2
MM
MM
*2
MM
*3
1 Hz flashing
1 S, 1 count-up with each ON
2 S2 1 count-up with each ON_ Rapid feed by 5 minutes if S2
held ON for more than 2 seconds_
3 S2 1 count-down with each ON. Counts-down by 5 minutes
if S2 held ON for more tban 2 seconds_
*
*
*
•
Functions
(1) Alarm function
(i) If the set alarm time coincides with the real
time, the following outputs will be generated at
each of the following outputs.
• At AL(AC)ouT 4 minute tone output of 2kHz X
8Hz X 1Hz
• At AL(DC)ouT approximately 32 (64) minute controloutput
• At TMoUT approximately 32 (64) minute control
output
(ii) When the SN/SLoFF is turned ON while the
alarm output is being g~nerated, the output will be
interrupted for approximately 7 minutes until the
output generation is resumed. Called snooze function, it can be repeated fot either approximately 32
minutes or 64 minutes.
(iii) The alarm indicator selected by the INDSEL
pin with the alarm timer being set can "be displayed.
(iv) With ALoFF switch connected to Vss, the
alarm indicator will not be displayed and alarm
will not be output even if the alarm time and the
real time coincide.
(v) The alarm control output time can be
selected by the 0.5HIlH pin to either 32 or 64 minutes except when alarm output is being generated.
(2) Sleep timer functio!,)
(i) If the SL is depressed with no TMoUT output,
either 32 or 64 will be selected according to the
state of the 0.5HIlH pin and TMouT and SLOUT will
be output.
(ii) The remainder of the time can be displayed
if the SL is turned ON while the sleep timer is in
operation.
(iii) Whenever the SN/SLoFF pin is turned ON
while the sleep timer is in operation, the sleep out
will go OFF.
(iv) If the SL is turned ON during the alarm output, the TMoUT and AL(DC)oUT will be output for
another 32 or 64 minutes. The timer interval can
be selected by the 0.5HIlH pinto either 32 or 64
minutes except in the sleep operation.
(v) When S2 has been depressed to set the sleep
timer to "0" in rapid feed, it will stay at "0" on
further depression of S2.
(3) Timer out
The TM output (DC) will be generated when
either the sleep output or the alarm output (DC) is
generated. The timer out is an OR-circuit of the
sleep out and AL(DC)oUT. If the ALoFF is ON with
only AL(DC) as the output, the timer out will also
be turned OFF.
(4) Time Signal
The TSouT pin that outputs time signal is provided. The output starts at 59 minutes 57 seoncds.
(See the figure below.)
59min
57 sec
(5)
OOmin
58sec
'59 sec
OOsec
In the case of alarm and sleep overlap
(i) The figure below shows the state of each
output pin when the sleep timer goes into operation
during the alarm output.
When the SL is turned ON, the AL(DC)oUT and
TMouT intervals will be s~t to another 64 min/32
min. When the SN/SLoFF is turned ON, the TMouT,
ALoUT, and SLOFF will be turned OFF.
--------------SHARP
AL(AC)OUT ~'--_ _ _ _ _ _ _ __
AL(DC)OUT
~I---------"'L
I
I
:
SLOUT
L
I
I
™oUT
~
The S W that turns
the AL (DC)auT,
TMoUT, and
SLOUT OFF_
I
~
1
r---64min----,
I,ALoFFsW'I'
SL/SLoFF
SW+-
AL output synchroni zed
with real time
-~.---.-........,.--
939
LCD Digital Clock CMOS LSI
...
.-....,~.....,~-
(ii) When the alar~ time and the real time coincide while the sleep timer is in operation togenerate the alarm. output, the SLOUT and TMouT intervals
will be set for another '64 min/32 min.
~
.
I
AL(AC)OUT
~---r:-----;fl~--~----~'---
I~
I
I
AL(DC)wr
:
I
I
~
TMoUT
I
i
I
I
~
r----64min--r
TM OUT and
I
~:
'
!r-----+!:SN/SL",.,SW
SLOUT
into the OFF state
SLo~
--r---J
ALoUT syncronized
with real time
•
~--~
__........
In this case if the SN/SLoFF i~ turned ON, the
AL(DC)oUT and AQ(AC)OUT will go OFF never to be
output even 7 minutes later. When the ALoF~ is
turned ON, only the AL(AC)oUT will go OFF.
(6)
SLOUT
Switch to put
AL(DC)OUT
LR3441
.....
r..--II:.....,.....,.....,~
Initial reset·
If the IR pin is connected to Vss, initial reset will
be applied to immediately reset all the counters and
AM 12 : 00 or a : 00 will be displayed depending
on the 12H system in the case of the former, 24H
system in the case of the latter..
(7)
Indicator select
The INDSEL pin can select either the bell mark or
the note mark.
Note mark: with Voo connected or open
Bell mark: with Vss connected
System Configuration
24J----~
'LCD
:>---'---i46
48
O.l,uF
O.l,uF
0_1,uF
Note) 0.5H/1H : 0.5H :
1H :
12H/24H: 12H:
24H :
940
with
with
with
with
Von
V 55
Voo
V 58
connected or open
connected
connected
connected
Digital ON/OFF Clock Timer CMOS LSI
LR3419
•
LR3419
Digital ON/OFF Clock.Timer CMOS LSI
Description
•
Pin Connections
The LR3419 is a CMOS LSI designed to provide
clock and timer functions. The base frequency is
selectable: 50 Hz or 60 Hz line input or 32.768kHz
crystal. It is also capable of driving fluorescent
displays tube (VFD) directly.
•
Features
1. "flours-Minutes' display
2. Timer function that permits both ON/OFF
times to be set
3. Power failure indication
4. Directly static-drive a VFD
5. Time base: 50/60Hz line or 32.768kHz crystal
6. Power supply voltage: + 5V
7. CMOS process
8. 48-pin quad -flat package
•
Top View
Block Diagram
GND
Cont ral Input
Test
~=:=~=!=~:::!=~I_~Timer
ON/OFF
Detector
r
Timer
Output
Hour Advance
lO-min Advance
Min Advance 2
Timer ON/OFF 2
Real Time Mode
Timer ON Set Mode
Timer OFF
Set Mode
Segment Decoder/Driver
Segment Output
941
Digital ON/OFF Clock Timer CMOS. LSI
Absolute Maximum Ratings
•
Symbol
Voo
V IN
BV
Po
Parameter
Supply voltage
Inp·ut voltage
Output voltage
Power consumption
derating ratio
Conditions
Referenced to GND
Referenced to GND
IMerenced to GND
Ta~+25'C
J
Ta>+25'C
Pin current
II
Operating temperature
Storage temperature
Toor
T st•
Ratings
Unit
-0.3-+7.0
V
-0.3-(Voo+0.3)
V
V oo +0.3--23
V
mW
550
5.4
mW/'C
±2.0
rnA
±1.0
-10-+60
'C
-40-+100
'c
Note
1
1
2
Note 1: Applies to al-4, bI-a, CI--I, da--t, el-I, ft-1, gl-..a, QL, QH, QT pins
Note 2: . Applies to 110 pins except Note 1
•
Operating Conditions
Parameter
Supply voltage
Input voltage
Output voltage
•
.
Symbol
Voo
V IN
VQlIT
Conditions
Referenced to GND
Referenced to GND
Referenced to GND
MIN .
4.5
0
-21
TYP.
5.0
-19
MAX.
5.5
Voo
0
Unit
V
V
V
Electrical. Characteristics
Symbol
VIH
VIL
Parameter
Input voltage
Input current
.'
IIHI
IILl
IIH2
IIL2
IIH3
I'L3
IIH4
IIL4
11115
Input amplitude
Output voltage
Time' base
Current consumption
Note
Note
Note
Note
Note
Note
Note
942
I'Ls
VI
Vom
VOLI
VOH2
VOL2
f
100
3: Applies to CONI, CON" 12114 pins
4:
5:
6:
7:
8:
9:.
Applies to PI-3, SH, ST, SM, TI pins
Applies to ACL pin
Applies to TE, TI pins
Applies to XI pin
Applies to Tom pin
Clock display mode
Conditions
Applies to all input pins
Voo=5.0V
VIN=VOO
VIN=GND
VIN=VOO
VlN=GND
V'N=VOD ·
VIN=GND
VIN=VOJ)
VIN=GND
VIN=VOJ)
V'N=GND
f=50 or 60Hz
Io [[=0.5mA, Voo=5.0V
Connects to -19V at RL =100kO
lo[[=0.2mA, VOJ)=5.0V
IOL =-0.2mA, Voo=5.0V
CONI =GND, CON 2=GND
CONI =VoJ), CON 2 =GND
CON I =GND, CON2=V~J)
f=50Hz, VI=VOJ)V~~p
f=60Hz, Vi=VOJ)VD~D
With 32.768kHz crystal
MIN.
4.0
0
TYP.
5.0
-0.5
-10
4.0
4.5
-19.0
4.5
100
0.5
-0.5
MAX.
V OD
0.4
1.0
-1.0
30
-1.0
1.0
-3.0
1.0
3.0
-3.0
Voo
4.9
-18.0
4.9
0.1
50
60
32.768
0.5
Unit
Note
V
3-7
pA
3
pA
4
pA
5
pA
6
pA
7
Vp~p
V
1
V
8
kHz
50
50
50
pA
1
8
9
LR3419
Digital ON/OFF Clock Timer CMOS LSI.
•
(iii) Timer ON (OFF) time setting operation
Specifications
(1)
Basic time base
Time base
50Hz
60Hz
32.768kHz
Disable
*
Time base select input Time base input pin
CONl
CON,
Xl
0
1
0
1
0
0
1
1
50Hz
60Hz
Xc
OPEN
OPEN
P,(P3) and either SH, ST
or S M simultaneously
*
Oscillator feedback circuit that consists of crystal and
capacitance
(2)
( i)
Operation flow chart
o
Function readout operation
==>
o
Transits only when SW
is ON. Returns automatically
after it is turnd OFF
o
o
Setting will be complete when P2(P3) is OFF.
While being adjusted, the 10 minute digit does not increment
the hour digit, nor does the minute digit increment the 10 mi·
nute digit.
In the timer ON (OFF) time set mode, timing will not stop.
In the timer ON (OFF) time set mode, timer output will not be
affected even if the timer ON (OFF) time coincides with the time
display.
(iv)
Simultaneous depression of setting
switches
Normally only one of Pl, P2, and P3 goes ON. If
more than two of these are depressed simultaneously, they enter no input and go into the time display
mode.
(v)
Simultaneous depression of rapid feed
switches
Note:· Hour rapid feed (SH) will proceed as follows.
12-hour representation
12--'1 --.2·············· ·--.1 0--'11
L-.~---AM/PM c h a n g e - - - - - - - - 24-hour representation
2--.13--.14···· .... '--.23--.0--'1 --.2· .. ····· '--.11
r
C
(ii)
Normally only one of SIl, ST, and S" goes ON. If
more than two of these are depressed simultaneously, the following operation will proceed.
(a) If one input goes ON followed by another input that ON
J
Hour display adjust operation
i
SM -i-,_ _-<,~--!,...J
'-------'
i-----------i
Hour
forward
o
Counter digit below
second will be reset
(b)
Decade
minute
forward
1-,----
I
i--------.i
Minute
forwrd
More than 2 inputs go ON simultaneously
SH~
J
S
iI
r------1
T
SM
~
i
~r--------I
I
I
i
;
~i----+:-..J
:
r--~I-~---'I--
i
l lI~
~
~
I
o
o
After P is turned OFF, timing starts from 00 second.
While being adjusted, the 10 minute digit does not increment
the hour digit, nor does the minute digit increment the 10 minute digit.
,
Hour forward
I
I
Minute forward
~-:-'---'''---SHARP---'---'------
943
LR3419
Digital ON/OFF Clock Timer CMOS LSI
(vi) Power failare display function
In any mode, LSI will be initialized inside on application of ACL to display:
With 12 hour repres~ntation
PM 12 : 00
With 24 hour representation
12: 00
This whole display goes flashing, 0.5 second ON
and 0.5 second OFF. The display stays in the initial state. J To stop flashing, go into the time display mode (PION) and then timing starts with PI
turned ON.
On application of ACL with PI set to ON, the display will s,tay in the initial state without flashing.
On the next PION, the display still in the initial
state will go flashing. Then on the next PION,
•
flashing will stop. And on the next PION, timing
starts.
(vii)' Auto clear circuit
The internal state on power-up will be as follows.
(a) Time display
12 hour representation
PM 12 : 00
24 hour representation
12 : 00
And the second, counfer will be reset. From the
time when the auto clear input ceases to 'exist, it
will operate according to the mode input (PI, P2, P3).
(b) Time ON and Timer OFF time
'
PM 12 : 00
With 12 hour representation
With 24 hour representation
12 : 00
System Configuration
VI
FIP5B13S
V,
23 24 25 26 27
VB (-19V)
VDD(+5~)
+
22I00-I--+1
GND(OV)
21I00-I--+1
20 i-+--.-I;I!II
181-+-.....-/·
17 t--\-.....J.
16H--.-f.
15 I-o-f-.....J.
141-+-~141
13H---,-.....!ii5\
12H-.....-/'
llt--\-.....J,
10t-t-....-f~18I
91--i--4----'
3}6,7'H--+----l
2)
4,1--i~-4----~
Note 1: Set to side 2 under 24 hour system,
and set to side 1 under 12 hour system
Note 2: Time base selection
CONI
CONz
50Hz
side 1
side 1
60Hz
side 2
eide 1
32.758kHz
side 1
side 2
Note 3: Time base input circuit
(alAt 50Hz, 60Hz
O.lJlF.r-@
O-;f-:I:.@
SlJlIJlF
o
Note 4:
944
(plAt 32.768kHz
®
Fluorescent display tube FIP5B135
The number indicates the pin number.
The figure in (
) is for 12 hour system.
LR3472
VTR Program Timer CMOS LSI
LR3472
•
VTR Program Timer CMOS LSI
•
Description
Pin Connections
The LR3472 is a CMOS LSI for a 6 events 1 week
VTR program timer. It can directly drive a fluorescent display tube (VFD).
•
Features
1.
2.
3.
4.
5.
6.
7.
8.
9.
•
cS c3
"Hours-Minutes" display
Selectable 12/24 hr. format
Max. of 6 events 1 week
6-daily and I-weekly reservation
Directly drive a VFD
Time base: 32.768kHz crystal
Supply voltage: - 5V
CMOS process
48-pin quad-flat package
>2 ,;: :2
:2
Top View
Block Diagram
~ /'"~
Error Colon
UI' Down Rec. Power~
Grid
K Input
hr Set
.---.-.----~-SHARP'-.-.-~-----
945
L.H3472
VTR Program Timer CMOS LSI
•
Absolute Maximum Ratings
Parameter
Supply voltage * 1
Input voltage * 1
Output voltage * 1.2
Operating temperature
Storage temperature
*1
*2
•
Refer~
Symbol
Voo
V IN
VN
Toor
T st•
Ratings
+0.3--7.0
+0.3-V DD -0.3
+0.3--40
-10-+60
-55-+150
Unit.
V
V
V
·C
"C
to Vss
Applies to Rl-I-R'-I,DI-Ds, S,-Sh pins
Operating Conditions
Parameter
Supply voltage * 1
Input voltage * 1
Output voltage * 1.2
•
Symbol
Voo
V IN
VN
MIN.
-5.5
TY?
-5.0
MAX.
-4.5
0
Voo
-32
(V oo =-5.0V±10%, V N=-.32V, Ta=25"C)
Electrical Characteristics
Parameter
Input voltage
Input current
.'
Output voltage
Symbol
VIII
V IL
IIIn
IILl
IIH2
IIL2
11113
IIL3
11114
IlL4
V OHl
VOLI
V OH2
V OL2
V OlI3
V OL3
V OH4
V OL4
Oscillator frequency
fose
Current consumption
IODI
1002
Note 1:
Note 2:
Note·3:
Note 4:
Note 5:
Note 6:
Note 7:.
Note 8:
Note 9:
Note 10:
946
Unit
V
V
V
MIN.
-0.5
Conditions
TYP.
Voo
VIN=OV
VIN=Voo
VIN=OV
VIN=VOO
VIN=OV
VIN=VOO
VIN=OV
VIN=VOO
IoH =-6mA
RL =120kO to
IoH =-12mA
RL =120kO to
IoH =-2mA
RL=120kO to
IoH =-3mA
RL=120kO to
MAX.
0
Voo+0.5
10
-1
5
-1
1
-5
4
-1
~2.0
V N+1.2
VN
-2.0
V N+1.2
VN
-2.0
VN
V N+1.2
-2.0
VN
V N+1.2
32.768
No lo~d, uniterrupted power condition
No load, interrupted power condition
Vss
OSCIN
OSCOUT
Note
V
1
p.A
2
p.A
3
p.A
4
p.A
5
V
6
V
7
V
8
V
9
kHz
300
40
r,
Applies to Vee, ACL, TI", T2,
fi, a, K,-K. pins
Applies to Kl - K. pins
Applies to a, fiJins
Applies to Vee, r pins
Applies to ACL pins
Applies to S.-Sh pins
Applies to D,- D8, pins
Applies to RI-I-RI-4~ R2-1-R2-'
Applies to Ra-l-Ra-4, R'-I-R4-.'
Test circuit (right figure)
Unit
p.A
10
VTR Program Timer CMOS LSI
Specifications
•
(1)
Input keys and operations
LR3472
these keys to execute one by one the data being displayed on the fluorescent display tube. With each
depression of these keys, the data gets renewed by
1. But if they are held pressed for longer than 0.5
second, the data gets renewed by 1 every 0.25
second.
CSUn---i>Mon---i>Tue-+wect-:ThU-+Fri-+sa:-----YAlI daY~
( i ) Clock Call key
When to set the current time, depress the Day,
Hour, and Min keys one after another while holding
the key pressed. When both the Clock Call key and
anyone of the Day, Hour, and Min keys are released, the clock starts from 00 second. Depression
of the Clock Call key in other mode (time set mode)
causes the data that has been displayed on the
fluorescent display tube stored and at the same
time goes back into the clock mode.
(ii) Timer Call key
This key is for calling the 6 timers in sequence.
With each depression, this along with the symbol
will be displayed on the fluorescent display tube in
the order shown in the figure below. Only the data
called by the Timer Call key to the fluorescent display tube can be altered in timer setting and
clearing.
In current data setting, the Day key should be
depressed 7 times to return to the origin. But in
timer ON time setting, it should be depressed 8
times because of the additiona of "everyday".
(iv) Data renewal by the Hour key
In current time setting or recording time setting,
the data will be renewed in any of the following
manners depending on whether the clock is under
12 hour system or 24 hour system.
• Under 12 hour system
CPM12--+PMl--+PM2-+-~PMll-AM12~.AM]----+----+AM11~
• Under 24 hour system
CO
------+
1 ---> 2 ---> 3 --->
m
____ m m ___
--
23~
In recording time setting, the data is renewed in
the following manner.
CO -- 1
--->
2 ---> 3 ~ ------------------->11 ~
The recording time can be set to up to 11 hou'rs
'
and 59 minutes.
(v) Data renewal by the Min key
CO - - 1
(iii)
Day, Hour, Min key
To set the current time or set the timer, depress
--->
2 ---> 3
-+--------------->58->59~
(vi) Clear key
This key is used to clear the data of the timer
that is set. First depress the Timer Call key to call
the timer then depress the Clear key to clear the
stored data of the timer that was called to the
flourescent display tube.
The recording time data can be cleared independently but if their recording start time is cleared,
the recording time data of the same timer will also
be cleared. This key has a function of stopping the
execution of timer recording. In other words, while
timer recording is being excuted, only this key
along with the Timer Call key and the Clock key
that are used to confirm the preset time can be
accepted and clears in the clock mode only the data
of the timer which is executing recording to bring it
to a forced stop.
Simultaneous depression of any other key than
the Clock Call cannot be accepted. A new key input
cannot be recognized until all the keys are released.
-.-----.-~-SHARP--.-.-------
947
VTR Program Timer CMOS LSI
(vii) Other inputs'
(a) 12 hour/24,hour swiching input
(b) Tape end input
'
This input gone "Low" is r~cognized as the tape
end and causes the timer outputs Tp andT R to.go
"Low'" for the timer operation to come to an end.
(2)
LR3472
And unless this input is "High", tne timer output T p
and T R will not go ''.l{igh'' even if the current time
and the recording start time coincide in the clock
mode.
(c) Power failure detect output
Display and outputs
r--~
I SAT I
I
I
I
I
I
I
(ii) Outputs
The LR3472 has the following outputs.
Channel control output
2-bit Cu, CD
Timer power output
I-bit Tp
Timer rec output
I-bit T R
The channel control output is for controlling the
channel selector IC. The timer output T p goes
"High" in rec9rding start time and recording time
setting. And in the clock mode, it goes "High" 1 minute before the recording start time. The timer output T R in the clock mode goes "High" if the current
time coincides with rhe timer ON time in the clock
mode. Power failure causes all the displays to go
bla'nk and resets the output. When the power comes
back on, the power failure indication will be displayed during the. next 1 minute. If the power failure occurs while recording, T p goes "High" (on
channell now) and another 1 minute later, TR goes
"ijigh" (on the preset cha,nnel) to resume recording.
The power failure display is indicated, by flash·
ing 1 second ON and 1 second OFF. To stop the
948
I
I
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I
Start :RH
.I
I
I
L___ J
The clock has 12 hour system/ 2 4 hour system
switching capability. Under the 12 hour system,
AM/PM change-over occurs bet~een 11 o'clock
and 12 o'clock.
When the clock is under 24 hour system, so is
the ti~er ON time. The display "PRO" indicates the
time is set to the timer and lights up when setting.
The colon fashes 0.5 second ON and 0.5 second
OFF while the clock is in operation. The character
in the g7 position indicates the timer number in reo
cording start time setting and recording time setting. Error lights up when more than two timers
overlap.
r----'
I
B: :
I
I
I
I'
I
I
(i) Display
Sh
I
I
Length I R,-,
I
I
IR'_3
I Error I
!.. ____ J
flashing, depress the Clock Call key.
(3) Initial mode
.[CH1 ..... CH14 key--Shift the channel by Cu,
and CD.
Clock Call key --For clock setting mode
Goes into this mode after auto clear is reset on
power-up. This mode accepts only the CHI-CH14
keys and the Clock Call key for clock setting. Once
the Clock Call key is deressed, timing of the clofk,
and timer operation are disabled. Timing cannot be
performed until the clock is set.
Initial state display
SUN
0·0 D
Display after depression of the Clock Call key
(Note) The colon is lit.
(4)
Clock setting mode
Clock Call key
[
1
Day key - - d + 1 ---- d
Hour key h+1 - - h
...,,-,----,_'-::-.,., __
Min key m + 1 --m
Clock Call, Day, Hour, Min key
The LR3472 stays in this mode while the Clock
Call key is held pressed. This mode accepts the
Day, Hour, Min keys and allows for current time
setting. Note that the minute digit does not increment the hour digit and the hour digit does not increment the day digit.
LR3472
VTR Program Timer CMOS LSI
(5) Clock mode
Tape End - - - ' L - T n:(T m-l)nl>n--- T p
Tn-Tm
TH
3
Clock Call key ~ Day key
Hour key -~---+--- Current time set mode
. Min key
Timer Call key - - - - - - - - - - - Recording time set mode
CH1-CH14 key
C", Cn channel shift
TPITn=T'm
Tn ; Current time
T m; Timer ON time
T'm ; Timer OFF time
Lm=l, m=everyday-T p , TH
m1'1, m = everyday - T p, T R, m clear
m1'1, m = everyday - T p, T R, m clear
Clear key
Tape End _ _ _-1
This mode is an ordinary timer operation mode
in that the timer output T p goes "High" 1 minute
before the preset recording start time with the
Tape End input "High" and when the current time
coincides with the preset recording start time, the
timer output T R goes "High". Even when the current time reaches one minute before the preset recording start time or when it coincides with the recording start time, the timer outputs, T p and T R
will not go "High", nor will preset content be
cleared if the Tape End input is "Low".
When the timer output T p is "Low" (when timer
recording is not being executed), if the Clock Call
key and either of the Day, Hour, and Min key are
depressed simultaneously to go into the current
time setting mode, the current time can be adjusted.
And when the timer recording is not being executed with the T p "Low", the Timer Call key is depressed to go into the recording start time setting
mode to allow what is now being displayed to be
the recording start time and the preset channel for
the timer 1. On reaching the time where there is no
recording time left with the timer output T R "High"
(when timer recording is being executed), the timer
outputs T p and T R go "Low" to have the corresponding memory content to be cleared except in the
case that the memory content for the corresponding
time happens to be "every day" and the corresponding timer happens to be the No.1 timer. This indicates that the timer 1 is preset for every week.
If either the Clear Key is depressed or the Tape
End input goes "Low" with output T.p "High" (when
timer recording is being executed), the timer outputs Tp and TR go "Low" to have the memory content for the corresponding timer to be cleared except in the case that the preset content for the corresponding timer happens to be "every day" and
the corresponding timer happens to be the No.1
timer. The CHI-CH14 keys can be accepted for
the channel signal to be generated, while the timer
output T p is "Low".
(6) Recording start time set mode
Tape End - - - Daykey---Hour k e y - - - Min key
CH1-CH14 keyClock Call key - -
Tp
d + l-+d Day shift
h + l-+h Hour shift
m + l-+m Minute shift
ClI , Cn Channel shift
Display-+Memory, For the
clock mode
Timer Call key - - Display-+Memory, Timer
address shift, For recording
time setting mode
Clear key - - - - Recording start time clear,
Recording time clear
This mode is the recording start setting time mode.
The display in the state in which the called timer
has been cleared or in which the non-set timer has
been called is shown as below.
Day digits are all OFF.
The timer number is
that of the timer called.
(1-6)
......_ _ _ _ _ _ _ _ _ _-' The colon- is flashing.
-
.
-: -
I
- B
Ti;"er display when the
preset is cleared
The channel is set initially to channel 1. This
can be adjusted by the CHI-CH14 keys. The CHI
-CH14 keys and Day, Hour, and Min keys can be
depressed in any order and if unnecessary need not
be depressed at all.
To exit for the mode in which to set recording
time for the same timer, depress the Timer Call
key. In which case the timer output T p remains
"High". In this mode, the recording time memory for
the same timer will be cleared on depression of the
clear key. This mode disables timer recording.
-..-..----~--SHARP--------
949
.---,.-..
......
...........................
VTR Program Timer CMOS LSI
~~~.-.
(7)
Recording time set
Tape End -~-Hour key
Min key
Clear key
Clock Call key - -
Tp
h + I-h Hour shift
m + l-+m Minute shift
Recording time Clear
Display-+Memory, For the
.clock mode
Timer Call key - - Display-+Memory, Timer
.address shift. For recording
time set mode
This mode is the mode in which to set the record·
ing time. The display in the state in which the reo
cording timer for the called timer has been cleared
and in which the not·set time~ pas been called is
shown as below:
I-
I
The day digits are all OFF.
. The timer number (1-6)
d~splayed is that of the
tim er called.
.
io-_ _ _ _ _ _ _ _ _- ' The colon is flashing.
- : -
...:.. B
This mode does not respond to depression of any
of the Day key, and CHI-CHI4 keys. If not reo
quired, the recording time setting procedure by the
Hour and Min key can be skipped so that the Clock
Call key and the Timer Call key may be operated to
proceed to. the next step. If timer recording is
attempted with the recording time cleared, either
the Tape End signal goes "Low" or the recording
will continue until the timer recording gets inter·
rupted by the Clear key.
With the recording time set to 00 hour 00 mi·
nute, the Tp goes "High" 1 minute before the recording start time, but on reaching the recording
start time, the Tp and T R go "Low" to disable reo
cording. In this mode, the T p goes "Low" on transi·
950
LR3472 '
--.-..-.~--
tion by the Clock Call key to the clock mode. By th-e
. Timer Call key, this is the same operation as the
recording start time setting for the next timer.
This mode disable timer recording.
(8) Others
( i ) Error indication
The error indication lights up when more than 2
of the preset timer contents overlap and the numbers overlapped will be alterl!ately displayed as in
the example.
(Example) When the timer No.1, No.2, and No.3
overlap
1-+2-+3-+ 1-+2-+3-+·········
Note that more than 2 sets of overlaps cannot be
distinguished from each one of the sets.
If the recording time is not set, overlapped preset
times give no error display.
Error indication does not prevent transition to
the program that starts halfway through.
Timer~
.
I
(M>N
)
M, N are timers,
Tlmer~
No. 1-6
.
N
In the figure above, the timer M is the first to be
executed. In which case the memory for the timer M
gets cleared on completion of the timer M recording.
The timer N completes recording the following
week to be cleared.
(ii) Preset for the second week
If the current time is already past the recording
start time, it is considered as the preset time for
one week away.
.LR3472
VTR Program Timer CMOS LSI
•
System Configuration
~
!OOV
AC
IpI~
:(
I
..
.,,
~~
Fluorescent tube display
.. ! !tal =~rt.ttlLtltft.t
t
r47l r4~ r4~ 1441 ~~ 1421 F r4~ 13~ 138\ r3~
~.
~
~
"''..."
11
~
;: r"""'"
0
I
~
[[
I
.
Tape -end detector
circuit
Clock Clear
Day
H
13
ime ·14
9
10
;: f""Mr'
~~
[!
rs
.-=
J21 f""Mr'
-=
~
3Jl
~~
LR3472
~
~.9
6 2..m
~~
~~
'ii
I26If""I""'
5
~our
11
7
Min
12
8
.1
3
4
On
.;r.
-,g
@.IN''-
"-
I!fJ
if
15 16 Ll;!1 Ll~
I!2J
~ ~
~i5
Channel selector
L
~'-.--'--------SHARP
I
_ . - . i - - _ _ _ _ _ ____
951
Remote Control Transmitter CMOS LSI
LR3715M
•
LR3715M
Remote Control Transmitter CMOS LSI
Description
•
PinConnections
The LR3715M is a CMOS LSI developed for use
in infrared remote control transmitters.
•
Features·
1.
2.
3.
4.
5.
6.
56-channel of data can be transmitted
Transmission code: PPM
Time base: 455kHz ceramic oscillator
Supply voltage : 3V
CMOS process
36-pin quad-flat package
Top View
•
Block Diagram
VDD
...
....
.;
."
"...
'o·"
Key·
Input
"c
~
.S
System Address
GND
U
...
'"
·s...
"
U
DATA
Inverter
Circuit
."
0
Data
Expansion
Use
Signal
"c
~
Test
DA T A Counter
Control
Circuit
Key
Scan
Output'
Oscillation·
-'---'-'---~-----SHARP~""""""---"""-'--
952
...... - . -..... ............... .......................... LR371Srv1
Remote Control Transmitter CMOS LSI
.-.-.•
.-
I
.-
Absolute Maximum Ratings
Symbol
Voo
VIN
Parameter
Supply voltage
Input voltage
Supply current
Output current
Power consumption
Rating
-0.3-+6
-0.3-+6
±5
±2
483
-20-+70
-50-+125
100, lEE
lOUT
Po
Topr
Tstg
Operating temperature
Storage temperature
Note 1:
Note 2:
Conditions
Referenced to GND
Referenced to GND
Ta=25°C
Unit
V
V
mA
mA
mW
Note
1,2
2
"C
"C
refers to the current that flows into the VDD pin; lEE refers to the current draining from the GND pin.
The direction of current flowing into the device is defined as positive: that draining from the device is defined as negative. This
definition is also applied to the electrical characteristics.
IDD
• . Recommended Operating Conditions
Parameter
Symbol
Voo
VIN
, fose
Supply voltage
In put' voltage
Oscillator frequency
•
Conditions
MIN.
2.2
0
Referenced to GND
Referenced to GND
Current consumption
VIN
VIL
IIHl
Input voltage
Input current
Output voltage
Oscillator frequency
Feedback resistor
Note 3:
Note 4:
Note 5:
Note 6:
, Note 7:
Note 8:
Applied
Applied
Applied
Applied
Applied
Applied
to
to
to
to
to
to
IrLl
IIH2
IIL2
VOH!
VaLl
VOH2
VOL2
fosc
Rib
Unit
V
V
kHz
(Voo=3V, Ta=25"C)
Symbol
Voo
100
MAX.
3.3
Voo
455
Electrical Characteristics
Parameter
Supply voltage
TYP.
3
Conditions
All input pins open
I fosc oscillated
I fosc
MIN.
2.2
TYP.
3
stopped
Voo-O.6
0
VIN=VOO
VlN=GND
VIN=VOO
VlN=GND
IOH= -5 flA
IOL=400 flA
IOH=-0.5mA
IOL=1mA
MAX.
3.3
0.5
1
Unit
V
mA
Voo
0.6
1
-1
V
V
4
5
flA
4
flA
5
V
6
V
7
kHz
Mil
8
1
-150
VOD-OA
0,
Voo
0.4
Voo
0.4
Voo-OA
0
455
1
5
flA
Note
3
3
pin VDD,
pins CI·CS. C12. CI3
pins Ko·K6. TI. T2 '
pins SO,S7,
pin OUT
pin OSCIN. OSCOUT
.-~------SHARP---------.-.
,,953
Remote Control Transmitter CMOS LSI
o0 0 0
I
I
I
I
1,0 0 0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
:01010:0
I
I
I
I
1 00 0 0 0 O.
(3) . Precautions in preparing a receiver
Make sure that the non-inVerse and inverse
signals are transmitte'd alternately. Be sure to
verify that bit number 15 (K) is alternately set t?
"1" and "0". It is not enough only to ~ompare bits
C6 -C14 either after inverting them or before inverthing them.
® The PPM signal status "1" or "0" may be
identified by checking its pulse interval as follows
(fo=455 kHz):
Tp<0.42 ms ... Non-PPM signal
0.42 ms~Tp<1.69 ms ... "0"
1.69 ms;;;;';Tp<3.37 ms ... "1"
3.37 ms;;;;';Tp
... Non-PPM signal
If a non-PPM signal is received, the device
clears all bits and begins processing with the first
bit again .
® If 16 bits (17 pulses) or more of PPM signal are received, the device identifies it as a nonPPM signal, clears all bits, and begins processing
with the first bit again.
@ The correct data should be identified by
matching the system addresses and data expansion
bits of the transmitter and receiver.
CD
I
I
I
I
I
LR3715M
I
I
I
1
I
While it is possible to
@ Modulator circuit
transmit serial 15-bit PPM signals directly, it
causes the broadening of occupied bandwidth, To
prevent this, the device samples the 15-bit PPM
signa with a 37.9 kHz (When fo=455 kHz) signal
and transmits PPM signal at 100% amplitude mod. ulation.
IEnlarged diagram
+
JlfUU1J1JUUlJlJ
(f=455kHz)
U
r-----67.5ms
Forward signal
•
,'"
67.5ms---1
J0?W&'-------'~
26.4)iI
(2)
Parallel transfer
~
PD.
DIN
PDs
PD6
SYS2
VDD
SYS.
SYS3
SYSI
SYSs
Ei
2
,.,"'
.."
"'
LU59001
...
"
"
0
>iI
PDo
PDl
PD7
PD2
IPD3
963
LR3617
Up/pown Counter CMOS LSI with LCD Decoder-Driver'
LR3617'
Up / Down Counter CMOS LSI with LCD
Decoder-Driver
•
Description
The LR3617 isan up/down counter with a decoder driver for 3 1 / 2 digit LeOs. It is best suited
to tape counters for use in micro cassette tape recorders and VTRs.
•
•
Pin Connections
_
N
~~,§g-tj~
c:Z~r:Z::<
QQ»»E-.P
VIN=OV
5.0V at 1M!l
IOL =lmA
5.0V at 1M!l
IOL =lmA
IOlI=-lmA
IOL =lmA
External resistance= 3.3k!l
0.0
0.0
4.0
0.0
4.0
0.0
4.5.
0.0
2.5
3.0
MAX.
5.0
0.1
5.0
1.0
1.0
-100
1.0
-1.0
5.0
0.5
5.0
1.0
5.0
0.5
3.5
Unit
Note
mA
V
1
I'A
2
I'A
3
V
4
V
5
V
6
MHz
1: Applies to all input pins
2: Applies to Do-D3 pins
3: .Applies to input pins except Do- D3 pins
4: Applies to HCR, TCR pins
5: Applies to Sl -S, pins
6: Applies to DOliT pin
--~-----SHARP~-'-'------
'970
VTR Data Back CMOS LSI
•
Operation
(1)
Data store operation
The input
data switch input pin is a pin that switches the way
the input data is taken in. As will be shown later, it
is suited for data setting by digital switch when
this input pin is "Low" and for reading in the data
from the external LSI when it is "lIigh".
( i)
(ii)
Input data switch (CNT pin)
Input data select outputs (SI ...... S6 pins)
As will be shown later, these outputs produce
the output of strobe signal for each digit when the
CNT pin is "Low" and produce the output of interface signal for the external LSI when the CNT pin
is "High".
(iii) Data input (Do ...... D3 pins)
Enter the data
selected by the data select outputs. The data inputs
is by entering 6 times serially negative logic parallel BCD codes with each dight consisting of 4 bits.
The data input is in the following order: 10 years'
digit, 1 year's digit, 10 months' digit, 1 month's
digit, 10 days' digit, and 1 day's digit.
Note that with each data, the Do pin is LSB, and
the D3 pin is MSB.
(iv) Data clock input (DCLK pin)
Enters
the fundamental clock input for data transfer when
the CNT pin is "High". This clock sets up the data
transfer timing. With the CNT pin "Low", zero
blanking input for the 10 months' and 10 days'
digit occurs. When the DCLK pin is "High", zero
blank is enabled. And when it is "Low", no zero
blank is enabled. Note that zero blank is disabled
'
when the CNT pin is "High".
(2) Display operation
(i)
Horizontal sync signal and vertical sync
signal input (HSYNC, VSYNC pin)
To synchronize the picture, the positive-going
horizontal sync pulse and vertical sync pulse are to
be applied to these input signal pins. The pulse
width required is more than Ips for the horizontal
pulse, and more than twice the horizontal pulse
width for the vertical pulse.
(ii) Horizontal positioning (HCR pin)
Input pin for the time constant of the one-shot
multi vibrator positions the horizonal display in
the picture. By varying the time constant of the external CR, horizontal display position can be
changed.
(iii) Vertical positioning (Vl ...... V126 pins)
Input pins for positioning. The level of this pin
determines the vertical display position.
V12B
V64
V32
VI6
VB
V,
V2
VI
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
I
H
H
I
H
H
I
L
L
I
L
L
I
L
H
I
H
L
I
H
L
H
H
I
L
H
set value
1
2
I
99
100
"
"
H
H
I
H
H
I
H
H
I
H
H
I
H
H
I
H
H
I
254
255
Set value=128' V12B+64' V6.+32· V32+16' VI6+8' VB
+4' V.+2 • V2+VI
Through the combinations in the table above
any set value can be selected from 1 to 255. Th~
display starts in the position (set value + 4) scan
lines from the fall of VSYNC.
(iv) Oscillator input and output (OSGN, OSCoUT
pins)
The frequency of the built-in oscillator is
determined by the external resistor connected between these pins. The oscillator frequency of this
oscillator determines the horizontal size of the
character.
(v) Display time input (TCR pin)
Input pin
for time constant of one-shot multivibrator' that determines how long the characters shall be displayed on the screen. By varying the time constant of
the external CR, display time can be changed.
(Vi) Display data output (DouT pin)
Display
data output pin that produces "Low" output when
no character is being displayed and produces
"High" or "Low" output according to the display
when character(s) is(are) being displayed.
(Vii) Display blanking input (BL pin)
Input
that disables the display data output (DOl'T pin).
When this pin goes "High", the DOtTT pin always will
go "Low" level. This pin only disables the DouT output and does not affect the internal working of the
LSI.
~ii~ Display start input (START pin)
Input.
for not only starting to read external data into the
LSI but also for displaying this data on the screen
after the data is read.
When this input changes from "Low" to "High",
the one-shot multivibrator that determines the display time will be triggered.
The data display time is determined by the time
constant of the CR externally connected to the display time input pin.
--~--'-'---SHARP'-'-------
971
[ill
10;=_
·LR3727
VTR Data Back CMOS LSI
•
Display
The display is a total 6-digit, I-line display of
year, month, and day each consisting of 2 digits;
The character organization and character array
are as follows_
D3
Dz
D,
Do
P3
D2
D,
Do
Low
High
High
Lbw
Indication
Indication
~
r-----'
I
I
High
High
High
High
High
High
High
Low
[OJ
~
High
High
Low
High
2
High
High
Low
Low
3]
High
Low
High
High
High
Low
High
Low
High
Low
Low
High
High
Low
Low
Low
Low
High
High
High
Low
,
[8J
Low
Low
I
I
: (blank):
I
I
I
I
L_____ J
(1) Character organization
The display character is of 5 X 7 numerics and
dots that separate year, month, and day. The dots
are fixed and not erasable.
(2) Character array
The character organized as described above will
be displayed in array as follows. And the character
size, and spacing are as shown in the figures A and
B.
A : Approx. 550ns (when the frequency of the
built-in oscillator is 1.8MHz)
B : Scan line_ ... _.3 lines/field
%
§J
[§
Low
Character array
o
Display of October 25,' 81
•
Description of Operation
(1) On application of the source voltage V oo ,
the capacitor externally connected to the timer T
starts charging. And when the pulse is applied to
each of.the VSYNC and HSYNC pins, display function is enabled. The display this time is not consistent, but most of the time, only the dots that separate the digits are displayed and the characters
that would otherwise follow get blanked.
No input signal should be applied prior to power-up because the LR3727 is of CMOS structure. It
should be remembered that source voltage should always be kept turned on because of the LSI's small
current consumption except when displaying.
When the capacitor externally connected to the
timer T finishes charging, the LR3727 will go into
the standby mode.
(2) Apply.the horizontal sync pulse and vertical
-.-.-..-.-------SHARP - - - - - - - - - -
972
LR3727
VTR Data Back CMOS LSI
mined by the time constant of the CR externally
connected to the TCR pin. Therefore, if the TCR is
left connected to GND, the operation time of the LSI
will be infinitely long and go into continuous display. (However, if the CNT pin is "High", the display data will be read into the LSI only once immediately after the START signal input. Even in
continuous display, the START signal should be
entered again to alter the display.)
(4) On the top signal going "High", the external
data will be read into the LSI with the timing as
shown in Fig. 1 and Fig. 2. In the data read timing
chart, the CR time constant of the TRC pin (or TP
signal output time) is shown to be long enough compared to the vertical sync signal cycle (longer than
2 cycles). With the CR time constant of the TCR pin
short (shorter than the vertical sync signal cycle),
the complete external data cannot be read into the
LSI.
The HP signal in the timing chart just discussed
sync pulse to the HSYNC and VSYNC pin respectively. Until the START signal is applied, the
whole LSI is in static state and retains the initial
state with the DouT pin "Low", oscillator in static
state, Sl-SS in high impedance state ("High"), and
each of the time constant input pins (TCR pin, HCR
pin) in high impedance state ("High").
VSYNC pin~...J"L.......fl
START pin
~i-------------~i------:---
TCR pin - - - - ,
. ~~
:
:
I
TP signal
-.l
r--I
(I:
LSI function TP - :
(3) Vary the START input pin from "Low" to
"High" to enter the START signal. As shown in the
following figure, the TP signal is generated in the
LSI while the TP signal is in sync with the VSYNC
signal. More than 1 JL s of the width START input
signal is required. The TP signal width is deter-
HSYNCpm ~~__~L__~~__~~__~~~'L-~'~~I~-4I__~__~~__~~!L-~I~-4I~~__~L__
I
I
I
I
I
I
I
I
I
I
I
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
START pin ~r--r--rl --r--r--:--1--r-l--t--~-T--1--i--~1
1
I
1
I
I
I
I
I
I
I
I
VSYNC pin
I
TP' signal
J I
I
1
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1
!
' I! :
I
I : : : I
I
I :
--
! I I
HP signal _____.I.
I
I
S1 pin
------~I I
I---!
I
I
1
i
I
I
I
I
S2 pin
---------+-......,~
Sa pm
-----------~~I~..,l~ ~:I--~~~__--------------------
:
!
i r '_ _
I
I
HI
I
I
I
I
I
I
I
I
1
II
II
~I1---------------------
1
1
I
I
I
I
I
I
--------~~+-~~II~U~~·-------------------
S5 pin
I
S6 pin
I
I
Do-D3 pms
aOOZ77710zwm
t •
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-
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tJpmIMWl77ZmmmOV77m
110· II
flO II I 10 I
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1
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"Iday'si
D 't C
years year s months month s days d' 'I
on
are digit digil digit digit digil IgJ
\
.
D 't Care
. on
Fig. 1 Data read timing (eNT pin "Low")
.-~----.-~---SHARP~-----.---
973
VTR Data Back CMOS LSI
. . . ._
LR3727
. . . . .. -......NII-..~_. . . . .. - .. . . . ._
Start pin
---fI-'
---------------------------I
,
DCLK pin
VSYNC pin
........................._
,
,I'
,
_--;._ _....11
I
,,
_.......- _...1• I1
TP signal ,
I
SI pin
-"'T'".....,~
S2 pin, --+----+--,
S3 pin,
---iL.----+---+-~r_-+_-"'T""-_+-__1
------+,---1
,
,
S5 pin
,
S. pin
------+,--.,~___1
I
I
!I
I
I
I
I
I
, .
I
I
I
,
I
S5 pin
I
I
I
.
,
Do - D 3 pins""'''''''''''''''''77'77'77:'77:'77:'77:'77:~
I 10
II ear's pO
II
I 10 I Ida 's I
Don't Care I years' I ~.
,months' I month's I days' I d'! I Don't Care
digit
gtt
digit
digit
digit
19tt
Fig. 2 Data read timing (eNT pin "High")
is a signal in sync with the rise of the horizontal
sync signal applied to the HSYNC pin and has a,
pulse width that is determined by the time constant
of the CR externally connected to the HCR pin.
Duty varies with the horizontal display position on
the screen.
The external data applied to Do - D3 pins goes
into sync with the rise of the horizontal sync signal
applied to the HSYNC pin when. the CNT pin is
"Low", or goes into sync with the rise of the clock
applied to the DCLK pin when the CNT pin is
"High", to be read into the LSI. Note that while the
LSI is reading external data, the display gets blanked and therefore the DouT pin maintains "Low".
The external data read into the LSI is a 6 character data and is stored in a 6 X 4 shift register.
The data for the dots that separate each digit will
be set up in the LSI as fixed data. These character
data o~ fixed data are to be through the multiplexer
to the character generator.
(5) The data read time is followed by the di,splay time if the TP signal is "High". The display
time lasts while the TP signal maintains "High" and
comes to an end when the TP signal goes "Low".
During the display time, it is so designed, the V
address counter counts the HP signals (the pulse
width of which is determinerl by the time constant
of the CR externally connected to the HCR pin) that
. is in sync with rise of the horizontal sync signal
applied to the HSYNC pin, collects out of the character generator the character data output produced
du'ring each horizontal scan time, and produces
- - - - - - - - - - - - - - S H A R P - - - . - . . . . . - r ........... . - - 974
LR3727
VTR Data eack CMOS LSI
serially through the 5-bit shift register the character outputs one by one at the DouT pin_
In the meantime, the H address counter counts
the timing pulses HC that occur during 1 horizontal
time to construct a character address and transmit
6 character data and 2 dot data to the character
generator.
The oscillator operates only part of the horizontal time (when HP is "Low") where display is to be
performed, to generate not only 5-bit shift register
data but also the clock for the timing circuit and
load sequentially 6-character 2.:dot data into the
5-bit shift register.
H.SYNC
pm
Fig. 3 shows the timing chart of the 1 field immediately after data read. One character is divided
into 7 parts with each part displayed during the 3
horizontal scan lines per field so that vertical size
of one character is 21 horizontal scan lines high
per field. During the display time, this operation
repeats with each input of vertical sync signal applied to VSYNC pin.
Fig. 4 shows the timing chart of 1 horizontal
time during the display. One character is di~ided
horizontally into 5 parts so that their signal outputs will be produced from the DouT pin.
n.
....,'-f~,IL..~L-fIL.-~L-1I"--~L..-IL--IIL...-iL~iL-~L.-!'L.-~L..-!'-' ....-1L~
HP signal
-1"\ '
,
VSYNC
pin
~~f--~~-~~~~4-~-~!-+--+-~~~~4-~-+--+-r--t~~~-1--i----
:
,
.
I
VPsignal
----,L-~-r-~~~4--4-+__+i-~-r-~~~--~-+-+-~-r-ii~-i--t-~--I
I
,
I
I
I
Oscillation
interval
DOUTpin __________~
1
2
3
4
5
6
7
Fig. 3
HSYNCpin
-1l~
HPs~al~
Display timing in 1 field (TP signal = "High")
__________________________________________________________
______________________________________________________________
oSCouTpin
HC signal
DOUT pin
IIIIII
arm
0
arm ann
0
mm arm
0
II~II~II~
Fig. 4
Display timing in 1 horizonal time (TP signal
=
"High")
.--.--------SHARP-----------
975
LR3727
VTR Data Back CMOS LSI
System Configuration
•
VDD (+5V)
GND
;;-0
VDD or GND
OSCIN,OSC OUT
Horizontal
sync signal
CNT
Vertical
sync signal
Start signal
r
VSYNC
Output
LR3727
START
Set 10th digit of the year
VDD
Set last digit of the year
Set 10th digit of the month
Set last digit of the month
Set lOth digit of the day
Set last digit of the day
'-'-"'-'~~-'---SHARP---------
976
Phase Locked Loop Frequency Synthesizer CMOS LSI
LR3652
•
LR3652.
Phase Locked Loop Frequency Synthesizer
CMOS LSI
Description
•
Pin Connections
The LR3652 is a CMOS LSI designed for PLL
frequency synthesizer AM/FM radios. It can be
controlled directly by the Sharp 4-bit I-chip
SM-4A or SM-5A microcomputers.
GND
Co
Cl
NC
C2
•
Features
1. Reference frequencies
FM mode
2.25kHz, 2.5kHz, 12.5kHz, 25kHz, 50kHz
AM mode
1kHz, 4.5kHz, 5kHz, 9kHz, 10kHz
2. Frequency division ratio: 113 - 11999
3. FM mode: pulse-swallow type
4. Charge-pump output port and an N-channel
open drain transistor are contained for use in
LPF amp.
5. 5-bit input ports
6. Time base: 3.6MHz crystal
7. Single power supply: + 3V
8. CMOS process
9. 22-pin dual-in-line package
•
NC
C3
NC
OSCoUT' 9
OSCIN
FM
AM
PSC
Top View
Block Diagram
4 Lock Detector
Programmable Divider
Strobe
FM Local
OSC.
Frequency
Programmable Counter
for Prescaler Control
Prescaler
Control
AM Local
OSC.
Frequency
977
Phase Locked Loop Frequency Synthesizer CMOS LSI
LR3652
__. - . - . - . - . - . - . - . - . - . - . - . - . - r........ -....... •
Absolute Maximum Ratings
Parameter
Supply voltage
External voltage
Input voltage
Current consumption
Output current
Operating temperature
Storage temperature
/
Symbol
V DD
Vee
V IN
IDD
lOUT
Topr
T st "
Ratings
-0.3-+6.0
-0.3-+18
-0.3-+6.0
±10.0
±2.0
-20-+60
-55-+125
Unit
V
V
V
rnA
rnA
V
V
Note
1
2
2,3
Note 1: Applies to DI. Dz pins.
Note 2: The direction of flowing into the LSI is defined as positive, and flowing out of the
LSI as negative.
Note 3: Applies to output pins.
•
Operating Conditions
Parameter
Supply voltage
External voltage
Input voltage
Oscillator frequency
•
Symbol
V DD
Vee
V IN
fose
MIN.
2.7
0.0
0.0
3.6
TYP.
3.0
MAX.
3.3
15.0
V OD
Unit
V
V
V
MHz
Note
1
(VDD=3.0V, Ta=25"C)
Electrical Characteristics
Parameter
Symbol
Supply voltage
V DD
Current consumption
IDD
Input voltage
Vm
V IL
1111
Input current
IlL
fIN
VOH1
VaLl
V OH2
V OL2
VOll3
VOL3
Input frequency
Output voltage
VOll4
VOL4 '
Oscillator freq uency
PSC delay time
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Applies
Applies
Applies
Applies
Applies
Applies
Applies
to
to
to
to
to
to
to
fose
TLH
TilL
Conditions
fose= 3.6MHz
FM or AM=3.0MHz, 0.3V p - p
fose=3.6MHz, output pin open
FM or AM=3.0MHz, 0.3V p - p
MIN.
TYP.
MAX.
Unit
Note
2.7
3.0
3.3
V
4
2.5
5.0
rnA
4
V
5
pA
5
MHz
6
V
7
V
8
V
9
V
1
MHz
10
ns
8
3.0
0.4
1.0
-1.0
2.6
0.0
VIN=3.0V
Sine wave VIN =0.3V p - p
Connects to V DD at 100kO
IOL = 100 pA
IoH = -200 pA
IOL = 200 pA
IOlI =-200pA
IOL =200 pA
Vee =15Vat 100kO
with G1 and G 2 grounded
IOL = LOrnA,
with (;1 and Gz grounded
3.0
2.6
0.0
2.6
0.0
2.6
0.0
14.80
0.0
3.0
0.4
3.0
0.4
3.0
0.4
14.95
15.00
0.4
3.6
V IN =3.0MHz, sine wave
0.5V p - p
300
300
Voo pin
ST, Co, CI, C2, C3, pins
AM, FM pins
LK pin
PSC pin
CP, CPz pins
OSCIN, OSCOUT pins
,-----------'SHARP---------------978
Phase Locked Loop Frequency Synthesizer CMOS LSI
•
How to Use Pins
Programmable counter for
counter range
prescaler control
.................. = 4
(1) OSCIN, OSCOUT (Crystal oscillation)
If a prescaler with its frequency dividing ratio
switchable between 1/40 and 1/44 is used:
Mode ................................................... ·····.· ... ·················FM
Channel space ····················································10OkHz
Frequency dividing ratio.................................. 1/123
Count range of the counter for
.................................. 4
prescaler
OSC 1N OSCOUT GND
Crystal
3.6MHz
Co
ST
Co
Cl
C2
C3
1
MF
Ml
M2
Ma
2
P3l
P3Z
P33
P3'
3
P21
PZ2
P23
P2.
4
Pll
PIZ
PI3
P14
5
PI
P2
P3
p,
6
"Low"
"High"
"Low"
"High"
Function
With MF "Low" and "High", AM mode and FM mode respectively.
For Ml - M3, refer to the other table.
P31-P3' set the frequency dividing ratio for the 100's digit of the
programmable counter.
P21 - P2. set the frequency dividing ratio for the 10's digit of the
programmable counter.
PIl - PI. set the frequency dividing ratio for the l's digit of the programmable counter.
PI- p, set the count range of programmable counter for pulse swallowing.
Indicate the end of data input and data latch.
Reference frequency (kHz)
FM mode (MF"Higb") AM mode (MF"Low")
MI
Mz
M3
"Low"
"High"
"Low"
"High"
"Low"
"Low"
"Low"
"High"
"High"
"Low"
"Low"
"Low"
"Low"
"Low"
"High"
2.25
2.50
12.50
25.00
50.00
1.0
4.5
5.0
9.0
10.0
FM mode
25kHz
1
2
3
4
Latch
I" _:E !lIe: alE _Iii!! -I.
Iii iii
;IIi
i
ColII~il
I
1
1
I
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1
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1
1
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1
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1
:
1
;
1
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111
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Cz~
e3 1
I
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1
1
:~r-Jrl~ri~
LJ LJ ~ !-.J LJ I
ST~
1
1
.1 14
t;<;2t
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