1986_Silicon_Systems_Data_Book 1986 Silicon Systems Data Book

User Manual: 1986_Silicon_Systems_Data_Book

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Analog/Digital
Bipolar/CMOS
Integrated Circuits

Table of Contents

Advanced and Preliminary Information
In this data book the following conventions are
used in designating a data sheet "Advanced"
or "Preliminary:'

Advanced- indicates a product still in the
design cycle, and any specifications are based on design goals
only. Sample availability is
indicated in the text.
Preliminary- indicates a product not completely released to production.
The specifications are based
on preliminary evaluations
and are not guaranteed.
Small quantities are available,
and SSI should be consulted
for current information.

Product Index
Page
Customer Reply Card
Table of Contents ............................................................................. .
Product Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Numerical Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

II
IV

Section 1. TELECOMMUNICATIONS PRODUCTS
Tone Signalling Products
SS1201, DTMF Receiver (5V) .................................................................
SS1202/203, DTMF Receiver (5V) .............................................................
SS1204, DTMF Receiver (5V subscriber) ........................................................
SSI 207, Integrated MF Receiver ...............................................................
DTMF Receivers Application Guide ............................................................
SSI 20C89, DTMF Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SSI 20C90, DTMF Transceiver (Call Progress) ....................................................
SSI 957, DTMF Receiver With Dial Tone. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SSI 980, Call Progress Tone Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SSI 981, Call Progress Tone Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SSI 982, Call Progress Tone Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

1-4
1-8
1-12
1-16
1-20
1-26
1-32
1-38
1-44
1-48
1-48

Modem Products
SSI K212, Single Chip Bell 212 Modem .........................................................
SSI K214, Analog Processor For V.22 bis Modems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SSI K222, Single Chip V.22 Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SSI 223, 1200 Baud FSK Modem ..............................................................
SSI K224, Single Chip V.22 bis Modem .........................................................
SS1291/213, 1200 BPS Full Duplex Modem Device ................................................
SSI 3522, Bell 212AIV.22 Modem Filter .........................................................

1-52
1-60
1-62
1-68
1-72
1-76
1-82

Speech Synthesis Products
SSI 263A, Phoneme Speech Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-86
SSI 263A, Speech Synthesizer User Guide ...................................................... 1-94

Switching Products
SSI 80C50, CMOS DigitallC T-1 Transmitter .....................................................
SS180C60, CMOS DigitallC T-1 Receiver .......................................................
SSI 22100, CMOS 4x4 Crosspoint Switch With Control Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SSI 22101/102, CMOS 4x4x2 Crosspoint Switches With Control Memory .. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SSI 22106, 8x8x1 Crosspoint Switch With Control Memory ..........................................
SSI 22301, PCM Line Repeater ................................................................

1-100
1-106
1-112
1-118
1-124
1-132

Section 2. MICROPERIPHERAL PRODUCTS
HDD Read/Write Amplifiers
SSI 104, 104L, 108, 122, 4 Channel R/W Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SSI 114, 4 Channel Thin Film R/W Circuit .......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SS1115, Winchester R/W Circuit ...............................................................
SSI117/117R, 2, 4, 6 Channel R/W Circuit .......................................................
SSI 117A/117AR, 2, 4, 6 Channel R/W Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SSI 188, 4 Channel R/W Circuit . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SSI 501/501R, 6, 8 Channel R/W Circuit ........................................................
SSI 510/510R, 4 Channel R/W Circuit ..........................................................
SSI 520, 4 Channel Thin Film R/W Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SSI 521R, 6 Channel Thin Film R/W Circuit ......................................................

2-2
2-6
2-10
2-16
2-22
2-28
2-34
2-40
2-46
2-50

HDD Head Positioning
SSI101A Differential Amplifier ................................................................ 2-54
SSI 116 Differential Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-56
II

Product Index (Contd.)
Page

HDD Read Data Path
SS1531, Data Separator and Write Precompensation Circuit. ........................................ 2-58
SSI 540, Read Data Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-66
SS1541, Read Data Processor ................................................................ 2-74

HDD Motor Control/Support Logic
S81 545, Winchester Disk Drive 8upport Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-80
S81 590, 5%" Motor Speed Control ............................................................ 2-84
S81591, 5%" Winchester Motor Speed Control ................................................... 2-88

Floppy Disk Drive Circuits
SSI 570, 2 Channel Floppy Disk R/W Circuit ..................................................... 2-92
S81 575, 2, 4 Channel Floppy Disk R/W Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-98
SSI 580, Port Expander Floppy Disk Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-102

Tape Drive Circuits
SS1550, 4-Channel Mag Tape Read Circuit ...................................................... 2-108

Memory Products
SSI67C401 FIFO 64x4 Memory ............................................................... 2-114
SSI67C402 FIFO 64x5 Memory ............................................................... 2-114

Section 3. CUSTOM/SEMICUSTOM INTEGRATED CIRCUITS
CMOS and Bipolar Process Charts ............................................................
Integrated Design Methodology ...............................................................
Custom/Semicustom Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Custom Design Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS/Bipolar Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-2
3-3
3-3
3-4
3-5

Section 4. ANALOG/DIGITAL STANDARD CELLS
Standard Cell Library ....................................................................... 4-1
Advanced Standard Cell Information-Basic Standard Cell List ...................................... 4-2

Section 5. GENERAL INFORMATION
SSI Product Selector Guide (Telecom) ..........................................................
SSI Product Selector Guide (Microperipheral) ....................................................
Packaging ................................................................................
Package Matrix Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ordering Information ........................................................................

5-1
5-2
5-4
5-5
5-6

Plastic Dip 8 Pins and 14 Pins ......................................................................
Plastic Dip 16 Pins and 18 Pins .....................................................................
Plastic Dip 20 Pins and 22 Pins .....................................................................
Plastic Dip 24 Pins and 28 F'irls .....................................................................
Plastic Dip 32 Pins and 40 Pins .....................................................................
Cerdip 8 Pins and 16 Pins ............................................ ~ .............................
Cerdip 18 Pins and 22 Pins .........................................................................
Cerdip 24 Pins and 28 Pins .........................................................................
Surface Mounted Device (PLCC) 28 and 44 Leads ....................................................
SON 8,14 and 16 Leads ...........................................................................
SOL 16 and 20 Leads .............................................................................
SOL 24 and 28 Leads ............................................................................
Flat Package Dimensional Diagrams and Dimensional Chart
10,24,28, and 32 Pins ...........................................................................
Quality Assurance and Reliability ...................................................................
Quality Assurance Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

5-7
5-8
5-9
5-10
5-11
5-12
5-13
5,-14
5-15
5-16
5-17
5-18

III

5-19
5-20
5-26

Numerical Index

881 20C89 ..............................
881 20C90 ..............................
881 67C401 .............................
881 67C402 .............................
88180C50 ..............................
88180C60 ..............................
881101A ...............................
881104 ................................
881 104L ...............................
8~1M .........•......................
881114 ................................
881115 ................................
881116 ................................
881 117/117R ...........................
881 117A/117AR .........................
881122 ................................
881 188 ................................
881201 ................................
881202 ................................
881203 ................................
881204 ................................
881207 ................................
881 K212 ...............................
881 K214 ...............................
881 K222 ...............................
881223 ................................
881 K224 ...............................

Page
1-26
1-32
2-114
2-114
1-100
1-106
2-54
2-2
2-2
N
2-6
2-10
2-56
2-16
2-22
2-2
2-28
1-4
1-8
1-8
1-12
1-16
1-52
1-60
1-62
1-68
1-72

881 263A ...............................
8812911213 .............................
881 5011501 R ...........................
881 510/510R ...........................
881 520 ................................
881 521 R ...............................
881 531 ................................
881 540 ................................
881541 ................................
881 545 ................................
881550 ................................
881 570 ................................
881 575 ................................
881580 ................................
881 590 ................................
881 591 ................................
881 957 ................................
881980 ................................
881981 ................................
881982 ................................
881 3522 ...............................
88122100 ..............................
88122101 ..............................
88122102 ..............................
88122106 ..............................
88122301 ..............................

IV

Page
1-86
1-76
2-34
2-40
2-46
2-50
2-58
2-66
2-74
2-80
2-108
2-92
2-98
2-102
2-84
2-88
1-38
1-44
1-48
1-48
1-82
1-112
1-118
1-118
1-124
1-132

Section 1

TELECOMMUNICATION
PRODUCTS

SSI TPD Product
Selector Guide

INNOVATORS IN INTEGRATION

TELECOMMUNICATIONS CIRCUITS

Circuit Function

Device

Features

Power
Supplies

Package

Page
No.

Tone Signaling Products
SSI201

Integrated DTMF Receiver

Binary or 2-of-8 output

12V

22 DIP

1-4

SSI202

Integrated DTMF Receiver

Low-power, binary output

SV

18 DIP

1-8

SSI203

Integrated DTMF Receiver

Binary output, Early Detect

SV

18DIP

1-8

SSI204

Integrated DTMF Receiver

Low-power, binary output

SV

14 DIP

1-12

SSI207

Integrated MF Receiver

Detects central office tone signals

10V

20 DIP

1-16

SSI20C89

Integrated DTMF Transceiver

Generator and Receiver, I'P interlace

SV

22 DIP

1-26

SSI20C90

Integrated DTMF Transceiver

Generator and Receiver, I'P interlace, Call Progress Detect

SV

22 DIP

1-32

SSI9S7

Integrated DTMF Receiver

Early Detect, Dial Tone reject

SV

22 DIP

1-38

SSI980

Call Progress Detector

Detects supervision tones, Teltone second-source

SV

8 DIP

1-44

SSI981

Precise Call Progress Detector

Detects supervision tones, Teltone second-source

SV

22 DIP

1-48

SSI982

Precise Call Progress Detector

Detects supervision tones, Teltone second-source

SV

22 DIP

1-48

Modem Products
SSIK212

1200/300 bps Modem

DPSK/FSK, single chip, autodial, Bell 212A

10V

28,22 DIP I-S2

10V

28 DIP

1-60

SSI K214

2400 bps Analog Front End

Analog Processor for DSP V.22 bis Modems

SSI K222

1200 bps Modem

V.22 version of K212, Pin Compatible

SSI223

1200 bps Modem

FSK, HDX/FDX

10V

16DIP

SSI K224

2400 bps Modem

V.22 is version of K212, Pin Compatible

10V

28,22 DIP 1-72

SSI2911213

1200 bps Modem

DPSK, two chips, low-power

10V

40/16 DIP

1-76

SSI3S22

1200 bps Modem Filter

Bell 212 compatible, AMI second-source

10V

16 DIP

1-82

Speech Synthesizer

Phoneme-based, low data rate, VOTRAX second-source

SV

28,22 DIP 1-62
1-68

Switching Products
SSI80CSO

T1 Transmitter

Bell D2, D3, D4, serial format and mux, low power

SV

28DIP,O

1-100

SSI80C60

T1 Receiver

Bell D2, D3, serial synchron. and demux, low power

SV

28DIP,O

1-106

SSI22100

Cross-point Switch

4x4xl, control memory, RCA second-source

12V

16 DIP

1-112

SSI22101/2

Cross-point Switch

4x4x2, control memory, RCA second-source

12V

24 DIP

1-118

SSI22106

Cross-point Switch

8x8xl, control memory, RCA second-source

SV

28 DIP

1-124

SSI22301

PCM Line Repeater

Tl carrier signal recondition

SV

18DIP

1-132

1-1

551 Telecommunications capabilities
Silicon Systems offers a broad line of standard telecommunications circuits aimed at providing cost-effective
solutions for common customer application problems.
At the heart of SSi's efforts in the communications
market is its pioneering work with CMOS switched
capacitor filters. Our early success with the DTMF
receiver has enabled us to develop a familyof chips
utilizing the switched capacitor filter technology.

As a trendsetter in the field, Silicon Systems is
leading the way towards a whole new era of VLSI circuits for telecommunications. Our broad selection of
DTMF receivers demonstrates not only technological
leadership in our own semiconductor field but also our
capability to anticipate the growing needs of the fastpaced telecommunications marketplace.

Here are a few completed circuits that demonstrate our broad telecommunications IC capability:

BIPOLAR

Integrated Circuit Function

MOS

Application

Integrated Circuit Function

Application

Telephone Answering
Machine

DTMF Receiver

• Decodes Touch-Tone®
Telephone Signals

VHF/UHF Gain Mixer

Radio Receiver

300 Baud Modem

Data Transmission

Pulse Width Modulator

Switching Power Supply

1200/2400 Baud Receiver

FSKIPSK Modem

Controller

Home Appliance

Error Corrector

Military Radio

Digital Receiver

Remote Control

Remote Transmitter

PCM Encoder/Decoder

Telecom System

Telephone Answering
Machine

Digital Correlator/
Integrator

Radio Telescope

Phoneme Based Speech
Synthesizer

Text-to-Speech

Audio System Receiver

PROCESSES
Silicon Systems offers circuits in junction-isolated,
bipolar, Single and double-layer metal. Plus, SSi has a
CMOS capability that includes not only a metal-gate
process but also a Silicon-gate process that produces
circuits packed with more functions in a smaller size for
high-speed, low-power performance. These are the most
popular and reliable processes in the two basic
technologies, and SSI's advanced ultra-clean wafer fab
produces higher yields than ordinary facilities.

Display Timing Generator

TV Sets

Video Processor

Infrared Video System

16 Channel Switching
Matrix

Bank Communications
System

Digital Loop Detector

Traffic Signal Control

Programmable Digital
Receiver

Home Appliance Remote
Control

Vocal Tract System

Speech Synthesis

CUSTOMER SERVICE
Silicon Systems provides individualized service for every
customer. Our Customer Service Department is
dedicated to responsive service and is staffed with
personnel trained to consider our customers' needs as
their most urgent requirement. Product quality and
service are both viewed as cornerstones for SSi's
continued growth.

PRODUCT QUALITY
Silicon Systems has made a major investment in
product test and in-line quality control equipment. For
example, a state-of-the-art LTX CP80 is used for functional and parametric testing of sophisticated analog,
digital, and combination AID circuits. In this way, SSi is
dedicated to the delivery of complex VLSI circuits to
meet the incoming quality level you require.

"No responsibility is assumed by S5i for use of these products nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No
license is granted under any patents, patent rights or trademarks of SSi. S5i reserves the right to make changes in specifications at any time and without notice.

1-2

1-3

INTEGRATION

Integrated
DTMF Receiver
551201

Data Sheet

'Mn

SSI 201 Pin Out
SSI 201 Block Diagram

(Top View)

FEATURES
•
•
•
•
•

• Excellent speech immunity
• 22-pin DIP package for high system density
• Output in either 4-bit hexadecimal code or binary
coded 2 of 8
• Synchronous or handshake interface
• Three-state outputs

Central office quality
NO front-end band-splitting filters required
Single, low-tolerance, 12-volt supply
Detects either 12 or 16 .standard DTMF digits
Uses inexpensive 3.579545 -MHz crystal for
reference

DESCRIPTION
The SSI201 employs state-of-the-art circuit technology
to combine digital and analog functions on the same
CMOS chip using a standard digital semiconductor
process. The analog input is pre-processed by 60-Hz
reject and band splitting filters and then hard-limited to
provide AGC. Eight bandpass filters detect the individual
tones. The digital post-processor times the tone
durations and provides the correctly coded digital
outputs. Outputs interface directly to standard CMOS
circuitry, and are three-state enabled to facilitate
bus-oriented architectures.

The SSI 201 is a complete Dual Tone Multiple Frequency
(DTMF) receiver detecting a selectable group of 12 or 16
standard digits. No front-end pre-filtering is needed. The
only externally required components are an inexpensive
3.58-MHz television "colorburst" crystal (for frequency
reference) and two low-tolerance bypass capacitors.
Extremely high system density is made possible by using
the clock output of a crystal connected SSI 201 receiver
to drive the time bases of additional receivers. The SSI
201 is a rnonolithic integrated circuit fabricated with lowpower, complementary symmetry MOS (CMOS) processing. It requires only a single low tolerance voltage
supply and is packaged in a standard 22 pin DIP.
14

Integrated DTMF Receiver
551201
ANALOG IN (pin 12)

H/B28 (pin 2)

This pin accepts the analog input. It is internally biased
so that the input signal may be AC coupled. The input
may be DC coupled as long as it does not exceed the
positive supply. Proper input coupling is illustrated below.

This pin selects the format of the digital output code.
When H/B28 is tied high, the output is hexadecimal
When tied low, the output is binary coded 2 of 8.
The table below describes the two output codes.

Hexadecimal

VIN Vp :

!!:
::t:

~

>-@-~
ANALOGI
IN
I

.011'F

£

ANALOG
IN

> lOOK

I

!!:

>-1~®-5

10pF

I

I

I

I ~
I I
I

Oigit

08

04

02

1

0

0

2

0
0

0
0
1
1

3
4

I-

10pF

5
6

>lOOK

7

I

0
0
0
0

Binary Coded 2 of 8
01

08

04

02

01

0

1

0

0

0

0

1

0

0

0

1

1
0
1

0
1

0

0

0
0

0
1

0

0

0
1

0
1

1
1
0

0

0
0
0

1
1

0
1
1

0

1

8

1

0

0

0

1

0

0
1

1

9

1

0

0
1

1
0
1

1

CRYSTAL OSCILLATOR

0

1

0

0
1

0

1

1

0

1

The SSI 201 contains an onboard inverter with sufficient
gain to provide oscillation when connected to a low-cost
television "color-burst" crystal. The crystal oscillator is
enabled by tying XEN (pin 16) high. The crystal is
connected between XIN (pin 15) and XOUT (pin 14). A
l' MEGn 10% resistor is also connected between these
pins. In this mode, ATB (pin 17) is a clock frequency
output. Other SSI 201's may use the same frequency
reference by tying their ATB pins to the ATB of a crystal
connected device. XIN and XEN of the auxiliary devices
must then be tied high and low respectively. Twenty-five
devices may run off a single crystal-connected SSI 201
as shown below.

*

1

0

1

1

1

1

0
0
1

#

1

1

0

0

1

1

0
1

A

1

1

0

1

0

0

1

B

1

1

1

0

0

1

1

1

C

1

1

1

1

1

1

0

0

0

0

0

1

0
1

1
1

1

IN1633 (pin 5)
When tied high, this pin inhibits detection of tone pairs
containing the 1633-Hz component. For detection of all
16 standard digits, IN1633 must be tied low.

XIN
15
ATB

14
SSI201

16

XEN

OUTPUTS 01, 02, 04, 08 (pins 1,22,21, 20) and EN
(pin 3)

17

Outputs 01 , 02, 04, 08 are CMOS push-pull when
enabled (EN high) and open circuited (high impedence)
when disabled by pulling EN low. These digital
outputs provide the code corresponding to the detected
digit in the format programmed by the HI B28 pin. The
digital outputs become valid after a tone pair has been
detected and they are then cleared when a valid pause
is timed.

XIN CONNECTED TO Vp
15
SSI201
17

16

XEN

UP TO 25 DEVICES

1·5

DV (pin 18) and ClRDV (pin 19)

N/C PINS (pins 7. 8.11)
These pins have no internal connection and may be left
floating.

OV signals a detection by going high after a valid
tone pair is sensed and decoded at the output pins 01 ,
02, 04, 08. OV remains high until a valid pause occurs
or the CLROV is raised high, whichever is earlier.

DTMF DIALING MATRIX
INTERNAL BYPASS PINS
S1, S2 (pins 9, 10)
In order for the 881201 OTMF Receiver to function
properly, these pins must be bypassed to VNA with
O.D1I'F ± 20% capacitors.

ColO

Col 1

Col 2

Col 3

Row 0

CD

0

[I]

0

Row 1

0

0
0

0

[!J

[!]

[£]

~

~

@]

POWER SUPPLY PINS
Vo (pin 6) VNA (pin 13) VND (pin 4)
Row 2

The analog (V NA) and digital (V ND) supplies are brought
out separately to enhance analog noise immunity on
the chip. VNA and VND should be connected externally
as shown below.

Row 3

12V SYSTEM

0
c:J

Note: Column 3 is for special applications and is not normally used in
telephone dialing.

6

DETECTION FREQUENCY

.:!:..-

12V

SS) 201

±10%

1-6

low Group '.

High Group '.

Row 0 = 697 Hz

Column 0 = 1209 Hz

Row 1 = 770 Hz

Column 1 = 1336 Hz

Row 2 = 852 Hz

Column 2 = 1477 Hz

Row 3 = 941 Hz

Column 3 = 1633 Hz

JiliamJl
rsfunJ'"
c',"'ml:~14)

14351 .yWd Roo, TO,1I0,

731-7110, 1WX mo.'95-280,

Input Voltage ................. (Vp + .5V) to (VND - .5V)
(All inputs except ANALOG IN)
ANALOG IN Voltage ......•....(Vp + .5V) to (Vp - 22V)
DC Current into any Input.. .................. ± 1.0mA
Lead Temperature ............................ 300°C
(soldering, 10 sec.)

ABSOLUTE MAXIMUM RATINGS*
DC Supply Voltage Vp .......................... +16 V
(Referenced to VNA, VNO )
Operating Temperature ••... - 40°C to+85°C Ambient
Storage Temperature ........•....•... -65°C to 150°C
Power Dissipation (25°C)......................... 1 W
(Derate above TA = 25° C @ 1OmW /0 C)

(-40°C ~ TA ~ +85°C, Vp - VNO = Vp - VNA = 12V

ELECTRICAL CHARACTERISTICS
Parameter

Conditions

Frequency Detect Bandwidth
Amplitude for Detection
Minimum Acceptable Twist

each tone

twist =

·Operation above absolute maximum ratings may damage the device
Note: All SSI 201 unused inputs must be connected to Vp or VNo,
as appropriate.

Min

Typ

±(1.5 + 2 Hz)

±2.3

± 10%)

Max

Units

± 3.0

% of fa

-24

+6

dBm
referenced to 600 n

-8

+4

dB
ms

high tone
low tone

Detection Time

20

25

40

Pause Time

25

32

40

ms

2

Vrms

OdB

dB referenced to
lower amplitude tone

60-Hz Tolerance
Dial Tone Tolerance
Talk Off

"precise" dial tone
MITEL tape
#CM 7290

hits

2

"0" level, 750/-lA load
"1" level, 750/-lA load

VND
Vo - 0.5

VND + 0.5
V,

V
V

Digital Inputs
(except H/B28, XEN)

"0" level
"1" level

VND
V, - .3(V, - VND )

VND + .3(V, - VND )
V,

V
V

Digital Inputs
H/B28,XEN

"0" level
"1" level

VND
V, -1

power Supply Noise

wide band

Digital Outputs
(except XOUT)

Supply Current
Noise Tolerance
Input Impedence

TA = 25°C
V,-VNA=V,-VND=12V±10%

29

MITEL tape
#CM 7290
Vp ?- ViP

?- Vp-22

VND +1
V,

V
V

25

mV pop

50

mA

-12

dB referenced to
lowest amplitude tone

100KM15pF

No responsibility is assumed by SSi for use of this product
nor for any infringements of patents q,nd trademarks or other
rights of third parties resulting from its use. No license is
1-7

granted under any patents, patent rights or trademarks of
SSi. SSi reserves the right to make changes in
specifications at any time and without notice,

INTEGRATION

551202/203
5V Low-Power
DTMF Receiver

Data 5heet
DESCRIPTION
The SSI 202 and 203 are complete Dual Tone
Multiple Frequency (DTMF) receivers detecting a
selectable group of 12 or 15 standard digits. No
front-end pre-filtering is needed. The only externally required components are an inexpensive
3.S8-MHz television "colorburst" crystal (for frequency reference) and a bias resistor. Extremely
high system density is made possible by using
the clock output of a crystal connected SSI 202
or 203 receiver to drive the time bases of additional receivers. Both are monolithic integrated
circuits fabricated with low-power, complementary
symmetry MOS (CMOS) processing. They require
only a single low tolerance voltage supply and are
packaged in a standard 18 pin plastic DIP.

tones. The digital post-processor times the tone
durations and provides the correctly coded digital
outputs. Outputs interface directly to standard
CMOS circuitry, and are three-state enabled to
facilitate bus-oriented architectures.
FEATURES
• Central office quality
• NO front-end band-splitting filters required
• Single, low-tolerance, 5-volt supply
• Detects either 12 or 16 standard DTMF digits
• Uses inexpensive 3.579545 -MHz crystal for
reference
• Excellent speech immunity
• Output in either 4-bit hexadecimal code or
binary coded 2 of a
• la-pin DIP package for high system density
• Synchronous or handshake interface
• Three-state outputs
• Early detect output (SSI 203 only)

The SSI 202 and 203 employ state-of-the-art
circuit technology to combine digital and analog
functions on the same CMOS chip using a standard digital semiconductor process. The analog
input is pre-processed by 50-Hz reject and band
splitting filters and then hard-limited to provide
AGC. Eight bandpass filters detect the individual

SSI 202/203 Block Diagram

r
:

S.6.NOPASS FILTERS
697

04

EN

16

08

15

ClRDY

!N1633

! ~:;:L::;U~EI
I DETECTORS I

II

02

17

01

~----,

I

18

HEX/B28

I

1 •

4

Vp

5 881 202 14

N/C

13

ATB

GNO

12

XIN

I

XEN

11

XOUT

ANALOG IN

10

GNO

,.

18

02

17

04

EN

16

08

IN1633

15

ClROV

01
HEX/B28

Vp

5

881 203 14

for a static sensitive component

1-8

OV

ED

13

ATB

GNO

12

XIN

XEN

11

XOUT

ANALOG IN

10

GNO

Pin Out
(Top View)

CAUTION: Use handling procedures necessary

OV

551202/203
5V low-Power
DTMF Receiver
HEX/B28
This pin selects the format of the digital output code.
When HEX/B28 is tied high, the output is hexadecimal.
When tied low, the output is binary coded 2 of 8.
The table below describes the two output codes

ANALOG IN
This pin accepts the analog input. It is internally biased
so that the input signal may be AC coupled. The input
may be DC coupled as long as it does not exceed the
positive supply. Proper input coupling is illustrated below.
Vp

Vp

Hexadecimal
VIN<

I

vp I
I

!!:

:t

>---@~
ANALOG I
IN

I
I

:

.011'F

I

[

>-1~~
ANALOG I 0

t--

e.

VIN> VP

10pF

IN

I
I

I I

r-

CRYSTAL OSCILLATOR
The SSI 202 and 203 contain an onboard inverter
with sufficient gain to provide oscillation when
connected to a low-cost television "color-burst"
crystal. The crystal oscillator is enabled by tying
XEN high. The crystal is connected between XIN
and XOUT. A 1 MQ 10% resistor is also connected between these pins. In this mode, ATB is a
clock frequency output. Other SSI 202's (or 203's)
may use the same frequency reference by tying
their ATB pins to the ATB of a crystal connected
device. XIN and XEN of the auxiliary devices must
then be tied high and low respectively. Ten
devices may run off a single crystal-connected
SSI 202 or 203 as shown below.

XEN

B

t

XIN CONNECTED TO Vp

12
SSI 202

13

0
1
1

*

1

#
A

1
1

B

1

1

C
0

1
0

1
0

0
0
0
0
1
1

08

04

02

01

0
0
0
1
1
1
0
0
0
1
1
1

0

0
1
0
0
1
0
0
1
0
1

1

0

0
1
0
1
0
1

0
0
0
0
0
1

0
0
1
1

0
1

1
1
1

0
0
1
1
0

0
1

0
0
1
1

0
1

0
1
0

1
1
0
0
1
1

0
1

0
1

0
1
0
0
1
0
0
1
0
0
1
1
1
1
1

0
0
1
1
1
1

OUTPUTS 01, 02, 04, 08 and EN
Outputs 01 , 02, 04, 08 are CMOS push-pull when
enabled (EN high) and open circuited (high impedence)
when disabled by pulling EN low. These digital
outputs provide the code corresponding to the detected
digit in the format programmed by the HEX/ 828 pin. The
digital outputs become valid after a tone pair has been
detected and they are then cleared when a valid pause
is timed.

Vp

SSI202

0
0
0
1
1
1
1

0

0
0
0
0
0
0
0
1
1
1

01

IN1633
When tied high, this pin inhibits detection of tone pairs
containing the 1633-Hz component. For detection of all
16 standard digits, IN1633 must be tied low.

11

13

1

9

The SSI 202 is designed to accept sinusoidal input
wave forms but will operate satisfactorily with any input
that has the correct fundamental frequency with
harmonics greater than 20 dB below the fundamental.

ATB

02

8

GND

12

04

3
4
5
6
7

10pF

I

XIN

08

2

I
GND

Oigit

Binary Coded 2 of 8

XEN

B

UP TO 10 DEVICES

1-9

DVandCLRDV
OV signals a detection by going high after a valid
tone pair is sensed and decoded at the output pins 01,
02, 04, 08. OV remains high until a valid pause occurs
or the CLROV is raised high, whichever is earlier.
ED (551 203 only)
The EO output goes high as soon as the SSI 203
begins to detect a OTMF tone pair and falls when
the 203 begins to detect a pause. The 01, 02, 04,
and 08 outputs are guaranteed to be valid when
OV is high, but are not necessarily valid when EO
is high.
N/CPIN5
These pins have no internal connection and may be left
floating.

551 202/203 TIMING

01,02,04,08'--+---'

OV---\----'

CLROV·--t----t----------'

DTMF DIALING MATRIX

Row 0

ColO

Col 1

[!J

0
0
0
0

0

Row 1

[2J

Row 2

c:J

Row 3

Col 2

Col 3
PARAMETER

0

0
0
0
0

TONE TIME: for detection

IOFF
10

25

RELEASE TIME

IR

35

DATA SETUP TIME

ISU

7

DATA HOLD TIME

IH

for rejection

~

Note: Column 3 is for special applications and is not normally used in
telephone dialing.

40

DETECT TIME

PAUSE TIME: for detection

@]

ION

40
-

for rejection

[!J

SYMBOL MIN. TYP. MAX. UNITS
ION
IOFF

-

-

20
-

ms
ms
ms

20

ms

46

ms

50

ms

4.2

-

5.0

ms

160

250

ns

-

-

-

,s

OV CLEAR TIME

ICL

-

elROV pulse width

IPW

200

ED Detect Time

lED

7

ED Release Time

IER

2

-

-

200

-

-

150

200

ns

-

-

200

300

ns

180

250

ns

OUTPUT ENABLE TIME
CL = 50pF RL = 1KSl
OUTPUT DISABLE TIME

ns

2·2

ms

18

ms

300

ns

C.L = 35pF RL = 500 Sl

DETECTION FREQUENCY

OUTPUT RISE TIME
CL = 50pF

Low Group '.
Row
Row
Row
Row

0
1
2
3

697
770
= 852
= 941
=
=

Hz
Hz
Hz
Hz

OUTPUT FALL TIME

High Group '.
Column
Column
Column
Column

0
1
2
3

1209
1336
= 1477
= 1633
=
=

CL = 50pF

Hz
Hz
Hz
Hz

1-10

-

(714) 731·7110, TWX 910·595·2809

Input Voltage ................. (Vp + .5V) to - .5V
(All inputs except ANALOG IN)
ANALOG IN Voltage ...........(Vp + .5V) to (Vp -1 OV)
DC Current into any Input .................... ± 1 .0mA
Lead Temperature ............................ 300°C
(soldering, 10 sec.)

ABSOLUTE MAXIMUM RATINGS·
DC Supply Voltage Vp . . . . . . . . . . . . . . . . . . . . . . . . . . . + 7 V
Operating Temperature ...... -4,o°C to +85°C Ambient
Storage Temperature .•............••. -65°C to 150°C
Power Dissipation (25 P C) ..................... 65 mW
(Derate above TA = 25°C @6.25mW/oC)

'Operation above absolute maximum ratings may damage the device
Note: All SSI 202/203 unused inputs must be connected to Vp or Gnd,
as appropriate.

ELECTRICAL CHARACTERISTICS
Parameter

(- 40°C";;; TA ,,;;; + 85,0 C, Vp = 5V

MInimum Acceptable I wist

Typ

Max

Units

+(1.5 + 2 Hz)

+2.3

± 3.5

% of fa

Conditions

Frequency Detect Bandwidth
Amplitude for Detection

each tone

twist =

± 10%)

Min

high tone
low tone

-32

-2

dBm
referenced to 600 n

-10

+10

dB

60·Hz Tolerance
Dial Tone Tolerance

"precise" dial tone

0.8

Vrms

OdB

dB referenced to
lower amplitude tone
hits

2

Talk Off

MITEL tape #CM 7290

Digital Outputs
(except XOUT)

"0" level, 400 )JA load
''1' level, 200)JA load

0
V, - 0.5

0.5
Vp

V
V

Digital Inputs

"0" level
"1" level

0
0.7V,

0.3V,
V,

V
V

Power Supply Noise

wide band

10

mV p.p

SllPp!y. Current

TA = 25°C

Noise Tolerance
Input Impedence

MITEL tape
#CM 7290
Vp~V'n~Vp'10

rnA

16

10

dB referenced to
lowest amplitude tone

-12
100k..o.O'15pF

"*'.~~
iJi i
,
~

125M'N.

050'

:t.015

No responsibility Is aii$UM$d by SSI for ui£l$ of th~8 products nor for any Infringements of patents and trademarks or other rights Of thitd parties resulting from Its

.050"

.Ol~~OO3-1r- ±T~'; "1

r

.100 ±.Olo
TYP

use. No license is granted under any patents, patent rights or trademarks of SSt 55i
reserves the right to make changes In speclficath:ims at any time and without notice.

1-11

551204
5V low Power
DTMF Receiver

INNOVATORS IN INTEGRATION

Data Sheet
DESCRIPTION

FEATURES

The SSI 204 is a complete Dual Tone Multiple Frequency
(DTMF) receiver that detects all 16 standard digits. No front-end
pre-filtering is needed. The only externally required components are an inexpensive 3.58-MHz television "color-burst"
crystal for frequency reference and a bias resistor. An Alternate
Time Base (ATB) is provided to permit operation of up to 10 SSI
204's from a single crystal. The SSI 204 employs state-of-theart "switched-capacitor" filter technology, resulting in approximately 40 poles of filtering, and digital circuitry on the same
CMOS chip. The analog input signal is pre-processed by 60-Hz
reject and band split filters and then zero-cross detected to provide AGC. Eight bandpass filters detect the individual tones.
Digital processing is used to measure the tone and Pause durations and to provide output timing and decoding. The outputs
interface directly to standard CMOS circuitry and are three-state
enabled to facilitate bus-oriented architectures.

•

Intended for applications with less
requirements than the SSI 202

•

14-Pin plastic DIP for high system density

•

NO front-end band splitting filters required

•

Single low-tolerance 5-volt supply

•

Detects all 16 standard DTMF digits

•

Uses inexpensive 3_579545-MHz crystal

•

Excellent speech immunity

•

Output in 4-bit hexadecimal code

•

Three-state outputs for microprocessor interface

r-------,
r BANDPASS FILTERS

I

I
I
I
TIMING
CIRCUITAV

02

14

01

13

08

EN

12

DV

VP
N/c

SSI 204

11

ATB

10

XIN

XEN

XOUT

ANALOG IN

ONO

SSI 204 Pin Out
(Top View)

Block Diagram
CAUTION: Use handling procedures necessary
for a static sensitive component

1-12

04

551204
5V Low Power

Subscriber
DTMF Receiver
ANALOG IN

OUTPUTS 01, 02, 04, 08, and EN

This pin accepts the analog input. It is internally biased so that
the input signal may be AC coupled. The input may be DC
coupled as long as it does not exceed the positive supply. Proper input coupling is illustrated below.

Outputs 01, 02, 04, 08 are CM08 push-pull when enabled (EN
high) and open circuited (high impedance) when disabled by
pulling EN low. These digital outputs provide the hexadecimal
code corresponding to the detected'dlgit. The digital outputs
become valid after a tone pair has been detected and they are
then cleared when a valid pause is timed. The table below
describes the hexadecimal codes.

VIN---0~

ANALOGI
IN
I

e.

VIN> Vp

:

.011'F

I

>-1K)-G

10pF

ANALOG
IN

I
I
I

Digit

08

04

02

1
2

1

1
1

0

3
4

0
0
0

>100K!l

0
0
0
0
0
0
0

0

10pF

1
1
1
1

0
0

0

1
1

0

1
1
1
1
1
1
1
1

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

0

0

0

0

01

!!:

I ~
I I
I

~

5

I

6
7
8
9
0

GND

GND

The 881204 is designed to accept sinusoidal input wave forms
but will operate satisfactorily with any input that has the correct fundamental frequency with harmonics greater than 20 dB
below the fundamental.

.

#
A

CRYSTAL OSCILLATOR

B

The 881 204 contains an onboard inverter with sufficient gain
to provide oscillation when connected to a low-cost television
"color-burst" crystal. The crystal oscillator is enabled by tying
XEN high. The crystal is connected between XIN and XOUT.
A 1 Mn 10% resistor is also connected between these pins.
In this mode, ATB is a clock frequency output. Other 881204's
(or 202's) may use the same frequency reference by tying their
ATB pins to the ATB of a cryStal connected device. XIN and XEN
of the auxiliary devices must then be tied high and low respectively. Ten devices may run off a single crystal-connected 881
204 (or 202) as shown below.
'

C
0

1
1
1
1
1
1
1

OV
OV Signals a detection by going high after a valid tone pair is
sensed and decoded at the output pins 01, 02, 04, 08. OV
remains high until a valid pause occurs.
N/CPIN
This pin has no internal connection and may be left floating.

Vp

XIN
10
ATB

OTMF DIALING MATRIX

9
551204

11

ColO

Coil

Col 2

Col 3

Row 0

[2J

0

0

0

Row 1

~

0

Row 3

8

[!]
[!]
[!]

~

Row 2

~
~
~

XEN

6

XIN CONNECTED TO V.

10
551204

11

XEN

@]
~

Note: Column 3 Is for special applications and is not normally used in
telephone dialing.

UP TO 110 DEVICE5

1-13

DETECTION FREQUENCY
Low Group to

High Group to

Row 0 = 697 Hz

Column 0 = 1209 Hz

Row 1 = 770 Hz

Column 1 = 1336 Hz

Row 2 = 852 Hz

Column 2 = 14n Hz

Row 3 = 941 Hz

Column 3 = 1633 Hz

Noise will also be reduced by placing a grounded trace around
XIN and XOUT pins on the circuit board layout when using a
crystal. It is important to note that XOUT is not intended to drive
an additional device. XIN may be driven externally; in this case
leave XOUT floating.

01,02,04,08,--+---'

APPLICATION NOTES
DV--+---'

The SSI204 will tolerate total input rms noise up to 12dB below
the lowest amplitude tone. For most telephone applications, the
combination of the high frequency attenuation of the telephone
line and internal band-limiting make special circuitry at the input
to the SSI 204 unnecessary. However, noise near the 56kHz
internal sampling frequency will be aliased (folded back) into
the audio spectrum, so if excessive noise is present above
28kHz, the simple RC filter as shown below may be employed
to band limit the incoming signal.

2.4K±5%.
NOISY \.
SIGNAL

.l-------I

>----'\Mr--~

PARAMETER
TONE TIME: for detection

40

-

tOFF

40

tOFF

-

DETECT TIME

to

25

RELEASE TIME

tR

35

DATA SETUP TIME

tsu

7

DATA HOLD TIME

tH

4.2

PAUSE TIME: for detection
for rejection

OUTPUT ENABLE TIME
8812104

ION
tON

for rejection

ANALOG IN

SYMBOL MIN. TYP. MAX. UNITS

-

-

-

mS

20

mS

-

mS

20

mS

46

mS

50

mS

-

!,-S

5.0

mS

-

-

200

300

nS

-

-

150

200

nS

-

-

200

300

nS

-

-

160

250

nS

-

CL = 50pF RL = lKn

I·o\"'20%

OUTPUT DISABLE TIME
CL = 35pF RL = 500n
OUTPUT RISE TIME
CL = 50pF
OUTPUT FALl. TIME

Filter for use in extreme high frequency input noise environment.

CL = 50pF

ABSOWTE MAXIMUM RATINGS·
DC Supply Voltage Vp .................. , .... +7 Volts

ANALOG IN Voltage ........... (Vp + 0.5V) to (Vp -10V)

Operating Temperature ....... - 40°C to + 850C Ambient

DC Current into any Input .................... ±1.0mA

Storage Temperature ................. -65°C to 1500C

Lead Temperature ............................ 300°C
(soldering, 10 sec.)

Power Dissipation (25OC) ...................... 65 mW
(Derate above TA = 25°C @ 6.25 mW/OC)

·Operation above absolute maximum ratings may damage the
device.

Input Voltage .................. (Vp + 0.5V) to - 0.5V
(all inputs except ANALOG IN)

Note: All SSI 204 unused inputs must be connected to Vp or Gnd.

as appropriate.

1-14

JifkonJz
rJkmJ'
"
1_4_35_1_M_Yf_o_rd_R_o_ad_,_Tu_5t_in_,c_~ _71_4_)_73_1-_7_1 _~_T_W_X_9_10_-5_9_5-_2_80_9

_____________________

____________________

ELECTRICAL CHARACTERISTICS (-40°C';;;; TA ';;;;+85°C, V p = 5V ± 10%)
Parameter

Conditions

Frequency Detect Bandwidth
Amplitude for Detection

Min

Typ

±(1.5 + 2Hz)

±2.3

each tone

Minimum Acceptable Twist

twist =

Max

Units

± 3.5

% of fa

-32

-2

dBm
referenced to 500 n

-8

+4

dB

high tone
low tone

50-Hz Tolerance
"precise" dial tone

Dial Tone Tolerance
Talk-Off
Digital Outputs
(except XOUT)

MITEL tape
#CM 7290

0
0.7Vp

Power Supply Noise

wide band
TA=25°C

Noise Tolerance

hits

O.3Vp
Vp

V
V

10
16
-12

Vp >V,,>V p -10V

mV pop
mA
dB referenced to
lowest amplitude tone

100KSl//15pF

l'I_-JllT
-u
325

V
V

10

MITEL tape
#CM 7290

Input Impedance

0.5
Vp

0
Vp - 0.5

"0" level
"1" level

Supply Current

Vrms
dB referenced to
lower amplitude tone

2

"0" level, 400 JiA load
''j'" level, 200 JiA load

Digital Inputs

08
OdB

310

1
LEAD NO 1 IDENTIFICATION
(OPTIONAL)

.009
.015

I

r-~

.720MAX,---j

'.~~~.
I
I I
--L-

'

040±020

1~'
.050
±.015

No responsibility is assumed by 55i for use of this product nor for any
infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent

~

,

JU
'
-1

I
018 ±.003
TVP

.050

~ ±.OO5
TYP

--i

I

.

I
i.--.100±.010
I
TYP

rights or trademarks of 55i. 55i reserves the right to make changes in
specifications at any time,and without notice.

551207

Irlt~rClt~

MF Receiver

INTEGRATION

PrelimirlClry DCltCl Sheet
GENERAL DESCRIPTION
The 881 207 is a complete Multi-Frequency (MF) receiver that
can detect all 15 tone-pairs, including ST and KP. This
receiver is intended for use in equal access applications and
thus meets Bell and CCITT R1 central office register
signalling specifications.

FEATURES
• Meets Bell and CCITI R1 specifications.
• 20·pin plastic DIP.
• Single low·tolerance 5V supply.
• Detects all 15 tone'pairs including ST and KP

No anti-alias filtering is needed if the input signal is bandlimited to 26 KHz. The only external component required is an
inexpensive television "color burst" 3.58 MHz crystal.

• Long KP capability
• Built·in amplitude discrimination.
• Excellent noise tolerance.

The 881 207 employs state-of-the-art switched capaCitor filters
in CMOS technology. The receiver consists of a bank of
channel-separation bandpass filters followed by zero-crossing
detectors and frequency-measurement bandpass filters, an
amplitude check circuit, a timer and decoder circuit, and a
clock generator. The device does not attempt to identify
strings of digits by the KP (key pulse) and ST (stop) tone pairs.

• Outputs in either "n of 6" or hexadecimal code.
• Three·state outputs, CMOS·compatible and TILcompatible.

The outputs interface directly with standard DMOS or TTL
circuitry ahd are three-state enabled to facilitate bus-oriented
architecture.

SSI 207 Block Diagram

I

I

I
I
I
I

I
I

I

I

I

I
I

I
I

I

I
I
I

I

IL.. _____
PRE FILTER I•

I
I
I

AGND

20

XOUT

VIN

19

Xl

MEl<

18

X2

QUAL

17

CSTR*

LKP

16

DGND

EN

15

OV

Voo

14

DE

DO

13

05

12 - 0 4

01

I

02

I

10

11

03

I

CHIP CLOCKS

I

I
I

XOUT

IL

Pin Out
(Top View)

I

_ _TONE
_ _DETECTOR
_ _ _ _ ...I

CAUTION: Use handling procedures necessary
for a static sensitive component

1-16

551207
Integrated
HEX MODE (HEX pulled high)
In the "hex" mode, DO to D3 provide a 4-bit code identifying one of the 15 valid tone combinations according to
the following table:

VIN
This pin accepts the analog input. It is internally biased
to half the supply and is capacitively coupled to the
channel separation filters. The input may be DC coupled
as long as it does not exceed the positive supply. Proper
input coupling is illustrated below.

R = '" 100kr2

Channels

Voo

VIN

Crystal Oscillator
The SSI207 contains an on-board inverter with sufficient'
gain to provide oscillation when connected to a low cost
television "color-burst" crystal. The on-chip clock
signals are generated based on the oscillator. The
crystal is connected between X1 and X2. X-OUT is a 3.58
MHz square wave capable of driving other circuits as
long as the capacitive load does not exceed 50 pF.

_.

D3 D2 D1 DO

1

0

0

0

1

0-2

700,1100

2

0

0

1

0

1-2

500,1100

3

0

0

1

1

0-3

700, 1300

4

0

1

0

0

1-3

900, 1300

5

0

1

0

1

2-3

1100,1300

6

0

1

1

0

0-4

700, 1500

7

0

1

1

1

1-4

900, 1500

8

1

0

0

0

2-4

1100,1500

9

1

0

0

1

3-4

1300, 1500

0

1

0

1

0

2-5

1100,1700

KP

1

0

1

1

4-5

1500, 1700

ST

1

1

0

0

1-5

900,1700

ST1

1

1

0

1

3-5

1300,1700

ST2

1

1

1

0

700, 1700

ST3

0-5

--

1

1

1

1

0

0

0

0
.-

NOTE: In the hex mode, D4 = DE and D5 = DV.

The outputs will be cleared to zero when no valid tone
pair is present.

Data Strobe
Data Error Strobe
Tristate Digital Outputs

LKP
The KP timer control. When high, the KP pulse must be
longer than the other tone pairs before it will be
detected. When low, the KP pulse is treated as any other
pulse.

n of 6 MODE (HEX pulled low)
Whenever a valid 2 of 6 code has been recognized, the
DV strobe rises. It remains high until the code goes
away, or the CSTR* line is activated. It will not reactivate until a new code is detected. Whenever an invalid
2 of 6 code is recognized, (1 of 6, 3 of 6, etc.) the DE
strobe rises to indicate a transmission error. The DE
strobe remains high until all errors stop, a valid tone pair
is detected, or the CSTR* line is activated. Once cleared
by CSTR, it will not reactivate until a new invalid condition is detected. The DE and DV strobes will never be
high simultaneously.

QUAL
Enables tone pair qualification. When low, the threshold
detector outputs are passed to the data outputs (DO-D5),
without validation, in the format selected by the HEX
pin. These outputs, plus strobes DV and DE, are updated
once per 2.3 ms frame. (DV and DE represent "2-of-6" indicators in this mode). Note that the strobes will cycle
once per frame (even when the inputs are stable). As
always, data changes only when both strobes are low.

The off-chip output register can be clocked by either the
rising or falling edge of the strobe. The outputs will be
cleared to zero when no valid tone is present.

CSTR*
This input clears both the DV and DE strobes. After
CSTR* is released, the strobes will remain low until a
new detect (or error) occurs. The output data is latched
by CSTR* and will not change while CSTR* is low, even
in the event that a new detect is qualified internally.
(Note that improper. use of CSTR* may result in missed
detects.

In the "n of 6" mode (HEX pulled low), each output
represents one of the six frequencies according to the
following table:
Frequency
700
900
1100
1300
1500
1700

Name

700,900

any other signal

The digital output format is neither "n of 6" or 4-bit
hexadecimal.
DV
DE
DO to D5

Tone Pair Freq.

0-1

Output Pin
DO
D1
D2
D3
D4
D5

EN"
The tristate enable control - When low, the DO-D5 outputs are in the low impedence state. In an interrupt
oriented microprocessor interface, EN* and CSTR* will
often be tied together to provide automatic reset of the
strobes when the output data is enabled.
1-17

DC Specifications (O°C~ TA~ 70°C, VDD=5V+
- 10%)
Symbol

Min.

Max.

Unit

Supply Current

Idd

20

mA

Output Logic 0

Vol

-

-

101 =8mA

-

-

0.5

101 = 1mA

-

-

0.4

V

Output Logic 1

Voh

-

-

Rating

V

loh= -4mA

-

VDD·1.0

-

loh= -1mA

-

VDD·0.5

-

V

Vih

2.0

-

V
V

Input Logic 1

V

Input logic 0

Vii

-

0.8

Analog Input Impedance (Input between VDD and AGND)

Zin

100kl30pF

-

Digital Input Current (Input between VDD and OGND)

lin

-50

50

fAA

Unit

n

I-- Tpse----l

I Tbr--i ITone 1

SSI 207 Timing

Tone2

--Y
Tskew

)

-l I--Td...,----j
I --i
r-I

DV(QUAL=1)
DV (QUAL=O)

c:==

Tstr

f l L _____

:

I

:

If1l1JLJlIUlJlll'--_____

-r

!-Tstr

DE(QU~

Timing Specifications

~I--Tsep
Symbol

Min.

Max.

TONE DETECTION

Td

-

-

-

KP (LKP = VDD)

-

55

-

ms

KP (LKP = DGND)

-

30

-

ms

Parameter

-

30

-

ms

Tr

-

-

-

KP (LKP = VAN)

-

-

30

ms

KP (LKP = DGND)

-

-

10

ms

All others

-

-

10

ms

Tskew

4

-

ms

Tpse

20

-

ms

Bridged Pause Duration

Tbr

-

10

ms

Minimum Strobe PW

Tstr

-

-

-

-

20

-

ms

All others
TONE REJECTION

Tone Skew Tolerance
Pause Duration

QUAL High

-

2

-

ms

Tsep

-

-

20

ms

2

-

Rise Time

Tr

-

100

ns

Fall Time

Tf

-

100

ns

CSTR* Width

Tw

50

-

ns

Data Enable Time

Ten

-

100

ns

Data Disable Time

Tdis

-

100

ns

Trst

-

100

ns

QUAL Low
Minimum Strobe Separation
QUAL High
QUAL Low

Strobe Reset Time
1·18

ms

Absolute Maximum Ratings
DC Supply Voltage Vp ......................... + 7V
Operating Temperature .......... ODC to 70 DC Ambient
Storage Temperature ................. 65 DC to 150 DC
Power Dissipation (25 DC) .................... 650mW
(Derate above TA=25°C @ 6.25 mW/DC)

Input Voltage .................... (Vp to 3V) to - 0.3V
DC Current into any input .................... ± 10mA
Lead Temperature ........................... 300 DC
(Soldering, rosel)
·Operating above absolute maximuum ratings may damage the device.

AC Characteristics (ODC';:;; TA 70 DC, VDD =5V -+ 10%)
Conditions

Parameter

Symbol

Min

F

± (0.015'

-

Frequency for Detect

Max

-

Units
Hz

Fo+5)
Amplitude for Detect

each tone

A

Amplitude for No Detect

-

An

Twist Tolerance

TW=

high tone

-25

0

0.123

dBm

2.191

Vpp

-

-35

dBm

-

0.039

Vpp

-

dB

TW

6

low tone

Third MF Tone Reject Amp

relative to highest tone

T3

-15

-

dB

Noise Tolerance

N

Nn

20

-

dB

60 HZ Tolerance

same as above

81

-

dBrn

0.777
68

-

dBrn

0.174

-

Vpp

_ one false operation
n - 2500 (10 digits)

same as above

180 HZ Tolerance

___ -1.020±

N60
N180

.002_~_SEE NOT~~
SEE NOTE #4

1h-

"'11"'11

3' [TYP. 2 PLACES,

~

1;----------------.1

!
.12S0IAx.001
EJECTOR PIN MARK
BOTTOM SURFACE

I

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~ ;""'11
±

,~, }1(1 -:-vo~

PARTING 4 PLACES)

001-, ~E

,t;if\ :;:~1"

.073
(TYP2 PLACES)

060 ± .002

060 ±

fF= 060 ± 004

Notes:
1. Package to frame mismatch not greater than
.004" in any direction. To be measured in
molded strip form.
2. Side to side and end to end package mismatch
(top harf vs. bottom half alignment) not
greater than .003".
3. Leads to be within .010"01 true position.
4. Shoulder intrusion/protrusion not greater

than .002".
5.

I(TYP 4 PLACES)

0051010 INSIDE RAD

~J

018:--l=:J

002

."

,.

100

Vpp

6.
7.

8.

Raised letters spelling "Singapore" on one
bottom ejector pin area. Letters must not
extend out past bottom package surface and
are to be less than .003" in depth. Letters to
be arranged in a radial pattern with at
least a .040"character size.
Maximuum flash between leads to be .003".
End flash not to exceed .010". Total package
length including this flash must be maintained
as shown on drawing.
Package surface to be matte finish (23-27
channilles) except for ejector pin, index
notch and pin 1 identification markings .

_ . - - 1.030 MAX PKG OUTLINE

The "PRELIMINARY" designation on an SSi data she~t indicates that the
product is not yet released for production. The specifications are subject to
change, are based on design goals or preliminary part evaluation, and are
not guaranteed. 5Si should be consulted for current information before us·
ing this product. No responsibility is assumed by SSi for its use; nor for any

infringements of patents and trademarks or other rights of third parties
resulting from its use. No license Is granted under any patents, patent
rights or trademarks of 55i. SSi reserves the right to make changes in
specifications at any time and without notice.

1-19

Jifwn

14_3_5_1_M_Y_fO_rd_R_o_O_d_,T_u_st_in_'_CO_I_ifo_r_Jlni_O~_(7rJfcfflJ"
_1_4)_7_3_1_-7_1 _0_'_TW

_______________________________

__
X_9_10_-5_9_5_-2_8_0_9__________________________________

Application Guide
for
SSi Monolithic Dual-Tone Multi-Frequency (DTMF) Receivers
band-split filter is amplified and limited by a zero-crossing
detector. The limited signals, in the form of square waves, are
passed through tone frequency band pass filters. Digital
logic is then used to provide detector sampling and determine
detection validity, to present the digital output data in the
correct format, and to provide device timing and control.

Detailed Description of Operation
Noise and Speech Immunity
The two largest problems confronting a DTMF Receiver are:
1) Distinguishing between valid tone pairs (or pauses) and

other stray signals (or speech) that contain valid tone
pair frequencies.
2) Detecting valid tone pairs in the presence of noise,
which is typically found in the telephone (or other transmission medium) environment

The 55i integrated DTMF Receivers are complete Touch-Tone
detection systems. Each can operate in a stand-alone mode
for the majority of telecommunications applications, thereby
providing the most economical implementation of DTMF
signaling systems possible_ Each combines precision active
filters and analog circuits with digital control logic on a monolithic CM05 integrated circuit 55i DTMF Receiver use is
straightforward and the external component requirements are
minimal. This application guide describes device operation,
performance, system requirements, and typical application
circuits 'for the 55i DTMF Receiver circuits.

How the SSi DTMF Circuits Work
General Description of Operation

Figure 1. SSi 202 Block Diagram

The task of a DTM F Receiver is to detect the presence of a
valid tone pair on a telephone line or other transmission
medium. The presence of a valid tone pair indicates a single
dialed digit; to generate a valid digit sequence, each tone pair
must be separated by a valid pause.

The 55i DTMF Receivers use several techniques to distinquish
between valid tone pairs and other stray signals. These techniques are explained in later sections. Briefly, the techniques are:
1) Pre-filtering of audio signal. Removes supply noise and

The following table gives the established Bell system standards for a valid tone pair and a valid pause:
One Low-Group Tone
-and-

697 or 770 or 852 or 941 Hz

One High-Group Tone

1209 or 1336 or 1477 or
1633 Hz

Frequency Tolerance

fo ± (1.5% + 2 Hz)
- 24 dBm '" A '" + 6 dBm @ 600n
(Dynamic Range 30 dB)
-8 dB '" High-Group Tone", +4 dB

Amplitude Range
Relative Amplitude
(Twist)
Duration
Inter-tone Pauses

dial tone from input audio signal and emphasizes the
voice frequency domain_
2) Zero-cross detection. Limits the acceptable level of

noise during detection of a tone pair. Important for
speech rejection.
3) Valid tone pair/pause sampling. 5amples the detection
filters and checks for consistency before determining
that a received tone pair or pause is valid.

Low-Group Tone
40ms or longer
40ms or longer

Audio Preprocessor

The 55i DTMF Receivers meet or exceed these standards.

The Audio Preprocessor is an analog filter that band limits the
input analog signal between 500 Hz and 6 KHz. In addition, it
emphasizes the 2 KHz to 6 KHz voice region.

5imilar device architecture is used in all the S5i DTMF
Receivers. Figure 1 shows the 551 202 Block Diagram. In
general terms, the detection scheme is as follows: The input
signal is pre-filtered and then split into two bands, each of
which contains only one DTMF tone group. The output of each

Band limiting suppresses power supply and dial tone frequencies, and high frequency noise. The emphasized voice region
helps to equalize the audio response since many phone lines
tend to roll off at about 1 KHz. The upper voice frequencies
are important in providing speech immunity.

1-20

Tone Band Splitting

and VND, an unfiltered supply may be used at VND. It is
necessary that VND and VNA differ no more than 0.5 Volts.

After the analog signal is preprocessed, it is then split into
two bands, each of which contains only one DTMF tone
group. The band-split filters are actually band'stop filters to
maintain all frequencies except the other tone group; this is
done to maintain all analog information to enhance speech
immunity but not allow the other tone group to act as interfering noise for the band being detected. These band-stop filters
have "floors" that limit the amount of tone pair twist which
further enhances speech immunity. See device data sheets for
acceptable twist limits.

The analog circuitry of the devices require low power supply
noise levels as specified on the device Data Sheet. Power
supply noise effects will be slightly less if the analog input is
referenced to VP. This is normally accomplished by connect·
ing VP to ground and utilizing a negative power supply. The
effects of excessive power supply noise will cause decreased
tone amplitude sensitivity and less tone detection frequency
bandwidth.

Zero·Crossing Detectors

Digital Inputs

The output of each band·split filter is amplified and limited by
a zero-crossing detector (limiter). The function of the zerocrossing detector is to produce a square wave at the prime
frequency emanating from the band-split filter. If a pure tone
is not present, as in the case of voice or other interfering
noise, a rectangular wave with a variable period will result.
Proportional to the interference, the limiter output power is
spread over a broad frequency range as the zero crossings
"dither". When a high level of noise (or speech) occurs, no
single bandpass filter pair will contain significant power long
enough to result in a tone detection. The zero-crossing detec·
tor also acts as AGC (Automatic Gain Control) in that the output amplitude is independent of input amplitude; this additionally establishes an acceptable signal-to-noise ratio not
dependent on tone amplitude.

The digital inputs are directly compatible with standard CMOS
logic devices powered by VP and VN (or VND). The input logic
levels should swing within 30% of VP or VN to insure detection. Any unused input must be tied to VN or VP. Figure 2
shows methods for interfacing TTL outputs to 12 Volt SSi
DTMF Receivers.
Analog Input
The Analog Input is the signal input pin for the devices, and
is specially biased to facilitate its connection to external cir·
cuitry, as shown in Figure 3. The signal level at the Analog
Input pin must not exceed or fall more than a few volts below
the positive supply as stated on the device Data Sheets. If
this condition cannot be guaranteed by the external circuitry,
the signal must be AC coupled into the chip with a .D1/LF ± 20%
capacitor.

Bandpass Filters and Amplitude Detectors
The bandpass filters perform tone frequency discrimination.
Their responses are tailored so that if the frequency of the
limited square wave from the zero-crossing detector is within
the tone frequency tolerance, the filter output will exceed the
amplitude detector threshold. The amplitude detectors are
interrogated periodically by the digital control circuity to ascer·
tain the presence of one and only one tone in each band for
the required duration. In a similar fashion, valid pauses are
measured by the absence of valid tone pairs for the specified
time.

Vp

>OK

12 VOLT

SSI

Timing and Logic
The only precision external element needed for the SSi DTMF
Receivers is a 3.58 MHz crystal (color-burst frequency) for the
on-board oscillator. This generates the precise clock for the
filters and for the logic timing and control of the rec~ive.

Figure 2. Interlace circuits for conversion from TIL output levels
to 12 volt SSi DTMF input levels

Circuit Implementation
Standard CMOS technology is used for the entire circuit. Logic
functions use standard low·power circuitry while the analog
circuits use preCision switched·capacitor-filter technology.

Vp

VIN

<

I
I
I

How to Use the SSi DTMF Receivers

,Vp

ANALOG
IN

Although static protection devices are provided on the high·
impedance inputs, normal handling precautions observed for
CMOS devices should be used.

I

I

Vp

I
I
I

>-0-~"

Precautions

I
I

vpl

Q.

01/iF

~
10pF

I

>-It=7 5£.
ANALOG
IN

~

I

I
I

I

A destructive high current latch-up mode will occur if pin
voltages are not constrained to the range between VN - .5 Volt
and VP + .5 Volt (except AIN as described below). In applica·
tions where voltage spikes may occur, protection must be provided to ensure that the maximum voltage ratings are not
exceeded. This may require the use of clamping diodes on the
Analog Input to protect against ringer voltage, for example, or
on the power supply to protect against "Supply spikes.

VNA

VNA

Figure 3. Direct and AC coupled configurations

Analog Input Noise
The SSi DTMF Receivers will tolerate wide·band input noise of
up to 12dB below the lowest amplitude tone fundamental duro
ing detection of a valid tone pair. Any single interference
frequency (including tone harmonics) between 1 KHz and
6 KHz should be at least 20 dB below the lowest amplitude
tone fundamental. Adherence to these conditions will ensure
reliable detection and full tone detection frequency bandwidth.
Because of the internal band limiting, noise with frequencies
above 8 KHz can remain unfiltered. However, noise near the
56 KHz internal switched·capacitor·filter sampling frequency
will be aliased (folded back) into the audio spectrum; noise
above 28 KHz therefore should be low-pass filtered with a
circuit as shown in Figure 4 using a cut-off frequency (Fc) of
6.6 KHz.

Power Supply
Excessive power supply noise should be avoided and to aid
the user in this regard, power supply hook-up options are provided on some devices.
Since the digital circuitry of the devices possess the high
noise immunity characteristics of CMOS logic, limited power
supply noise is required only for the analbg section. On those
SSi DTMF receivers that have separate Analog Negative and
Digital Negative supply connections (grounds), namely VNA

1·21

Figure 6 shows a more featured version of Figure 5. These
added options include:

A 1 KHz cut·off frequency filter can be used on "normal"
phone lines for special applications. When a phone line is particularly noisy, tone pair detection may be unreliable. A 1 KHz
low pass filter will remove much of the noise energy but maintain the tone groups; however, a decreased speech immunity
will result. This usage should only be considered for applica·
tions where speech immunity is not important, such as control
paths that carry no speech.

1) A 150 Volt surge protector to eliminate high voltage spikes.
2) A Texas Instruments TCM1520A ring detector, optically
isolated from the supervisory circuitry.
4) Back-to-back Zener diodes to protect the DTMF (and optional
mu Itiplexer Op-Amp) from ringer voltage.

Some DTMF tone pair generators output distorted tones which
the SSi DTMF Receivers may not detect reliably (inexpensive
extension telephones are an example). Most of the interfering
harmonics of these tones may be removed by the use of a
3 KHz row-pass filter as in Figure 4. Some speech immunity
degradation will result, but not as bad as using the 1 KHz
filter mentioned above.

R

FC
(KHz)

5) Audio multiplexer which allows voice or other audio to be
placed on the line (a recorded message, for example) and not
interfere with incoming DTMF tone detection.

C

(KO)

"F)

(± 5%)

(± 20%)

1.0

1.6

0.1

3.1

5.1

.01

ON/OFF HOOK
RELAY

SSt 201

.01
6.6
2.4
- _... _-----

Figure 4. Filter for use in noisy environments

SUGGESTED
COMPONENT
VALUES

B

150V

ANALOG
INPUT

Telephone Line Interface

551 DTMF
RECEIVER

In applications that use an SSi DTMF Receiver to decode
DTMF signals from a phone line, a DAA (Direct Access
Arrangement) must be implemented. Equipment intended for
connection to the public telephone network must comply with
and be reg istered in accordance to FCC Part 68. For PBX
applications refer to EIA Standard RS-464.

Figure 6. Full Featured Phone Line Interface

An integrated voice circuit may also be implemented for line
coupling, such as the Texas Instruments TCM1705A, however,
this approach is typically more expensive than using a transformer as shown above.

Some of the basic guidelines are:
1) Maximum voltage and current ratings of the SSi DTMF
Receivers must not be exceeded; this calls for protection from
ringing voltage, if applicable, which ranges from 80 to 120
Volts RMS over a 20 to 80 Hz frequency range.

Outputs
The digital outputs of the SSi DTMF Receivers (except XOUT)
swing between VP and VN (or VND) and are fully compatible
with standard CMOS logic devices powered from VP and VN.
The 5 Volt DTMF devices will also interface directly to LSTIL.
The 12 Volt DTMF devices can interface to TIL or low voltage
MOS with the circuit in Figure 7.

2) The interface equipment must not breakdown with highvoltage transient tests (including a 2500 Volt peak surge) as
defined in the applicable document.
3) Phone line termination must be less than 200 Ohms DC and
approximately 600 Ohms AC (200-3200 Hz).
4) Termination must be capable of sustaining phone line loop
current (off·hook condition) which is typically 18 to 120 mA DC.

v,
12 VOLT

5) TI1e phone line termination must be electrically balanced in
respect to ground.

-::>o~--- TO TTL OR 5V MOS.

VND

6) Public phone line termination equipment must be registered
in accordance to FCC Part 68 or connected through registered
protection circuitry. Registration typically takes about six
months.

1
Figure 7. SSi 12 Volt DTMF to TTL Level Interface

Ready made DAA devices are also available. One source is
Cermetek Microelectronics, Sunnyvale, California.

Data Outputs D8, D4, D2, and D1 are three-state enabled to
facilitate interface to a three-state bus. Figure 8 shows the
equivalent circuit for the data outputs in the high impedance
state. Care must be taken to prevent either substrate diode in
Figure 8 from becoming forward biased or damage may result.

Figure 5 shows a simplified phone line interface using a 600
Ohm 1:1 line transformer. Transformers specially designed for
phone line coupling are available from many transformer
manufacturers.

SSI201

TIPj

OUTPUT PIN

SSi DTMF
RECEIVER
RINGa---3
1:1

600n
Figure 8. Equivalent Circuit of SSi OTMF Receiver Data Output
in High Impedance State

Figure 5. Simplified Phone Line Interface

1-22

Timing

and the other between XOUT and VN (or VND). Extra caution
should be used to avoid stray capacitance on the resonant circuit when using a ceramic resonator instead of a quartz crystal.

Within 40 ms of a valid tone pair appearing at the DTMF
Receiver Analog Input, the Data Outputs D8, D4, D2 and D1
will become valid. SSI 201 timing is shown in Figure 9 (refer
to the device Data Sheet for other timing diagrams). Seven
microseconds after the data outputs have become valid DV
will be raised. DV will remain high and the outputs valid while
the valid tone pair remains present. Within 40 ms after the
tone pair stops, the DTMF will recognize a valid pause. DV is
lowered approximately 45 ms following the end of the tone
pair, and the data outputs all set to zero 4.56 ms following DV
going low. DV will strobe at least for the same duration as the
received tone pair.

When the oscillator connected as above and XEN tied high,
the ATB (alternate time base) pin delivers a square wave output at one-eighth the oscillator frequency (447.443 KHz
nominal). The ATB pin can be converted to a time base input
by tying XEN low; ATB can then be externally driven from
another device such as the ATB output of another DTMF. No
crystal is required for the ATB input device; XIN must be tied
high if unused. Several 5Si DTMF Receivers can be driven with
a Single crystal (refer to device data sheet for fan-out limit).
XOUT is designed to drive a resonant circuit only and is not
intended to drive additional devices. If a 3.58 MHz clock is
needed for more than one device and it is desirable to use
only one resonant deVice, an outside inverter should be used
for the time base, buffered by a second inverter or buffer. The
buffer output would then drive XIN of the 5Si DTMF Receiver
as well as the other device(s); XOUT must be left floating and
XEN tied high.

System Interface
Provision has been made on the S5i DTMF Receivers for
handshake interface with an outside monitoring system. In
this mode, the DV strobe is polled by the monitoring system
at least once every 40 ms to determine whether a new valid
tone pair has been detected. If DV is high, the coded data is
stored in the monitoring system and then CLRDV is pulsed
high. With some systems operating in the handshake mode, it
may be desirable to know when a valid pause has occurred.
Ordinarily this would be indicated by the falling edge of DV.
However, in the handshake mode, DV is cleared by the mono
itoring system each time a new valid tone pair is detected
and, therefore, cannot be used to determine when a valid
pause is detected. The detection of a valid pause in this case
may be observed by detecting the clearing of the Data Outputs.
Since, in hexidecimal format (the mode normally used with a
handshake interface), the all zero state represents a commonly
unused tone pair (D), the detection of a valid pause may be
detected by connecting a four-input NOR gate to the device
outputs and sensing the all zero state.

Dial Tone Rejection
The 55i DTMF Receivers incorporate enough dial tone rejection
circuitry to provide dial tone tolerance of up to 0 dB. Dial tone
tolerance is defined as the total power of precise dial tone
(350 Hz and 440 Hz as equal amplitudes) relative to the lowest
amplitude tone in a valid tone pair. The filter of Figure 10 may
be used for further dial tone rejection. This filter exhibits an
elliptic highpass response that provides a minimum of 18 dB
rejection at 350 Hz and 24 dB rejection at 440 Hz so long as
the component tolerances indicated are observed. The DTMF
on-chip filter rejects 350 Hz at least 6 dB more than 440 Hz.
Therefore, employing the filter of Figure 10 yields a dial tone
tolerance of + 24 dB.

Time Base
The SSi DTMF Receivers contain an on-chip oscillator for a
3.5795 MHz parallel resonant quartz crystal or ceramic
resonator. The crystal (or resonator) is placed between XIN
and XOUT in parallel with a 1 Mohm resistor, while XEN is
tied high. Since the switched-capacitor-filter time base is
derived from the oscillator, the tone detect band frequency
tolerance is proportional to the time base tolerance. The 5Si
DTMF Receiver frequency response and timing is guaranteed
with a time base accuracy of at least ± .01 %. To obtain this
accuracy the CTS Part No. MP036 or Workman Part No. CY1-C
or equivalent quartz crystal is recommended. In less critical
applications a suitable ceramic resonator may be implemented.
ANAlOG
INPUT

I--lI '. 3~

NE BURST

"' 0'1

I

I

tslh

-..t J..--

V,

0271'F
10'/,

TO S8, DTMF

50'

r.o:-

_I
~ ~~''"'

ALL RESISTORS
ALL CAPS 5%
UNLESS NOTED
OP AMPS: 1/2 LM1458
OR EQUIV

Vp OR VN

~

~

tdv

I

I

c::J

Figure 10. Dial Tone Reject Filter

'ph< ----If--CLROV-Vp

.01J.LF

D..

>---0~
I Q.
DIN

I-

10pF

I
D..

~KV-~
I
DIN

I

>100k-U

7

Q.

Receiver Outputs and the DE Pin
Outputs 00,01,02,03 are CMOS push-pull when enabled
(DE low) and open-circuited (high impedance) when
disabled (DE high). These digital outputs provide the
',hexadecimal code corresponding to the detected digit.
The table below shows that code.

r-

10pF

I

>100kn

I

I

I
GND

XEN

UP TO 10 DEVICES

I

I
I

SSI20C89
11

II
I

XEN

10

I

I
I
I

7

SSI20C89
11

XIN CONNECTED TO Vp

Vp

I

9

GND

Digit

Input:
Output:

07
03

1
2
3
4
5
6
7
8
9
0

The SSI20C89is designed to accept sinusoidal input
wave forms but will operate satisfactorily with any input
that has the correct fundamental frequency with harmonics greater than 20 dB below the fundamental.
Crystal Oscillator
The SSI 20C89 contains an onboard inverter with sufficient gain to provide oscillation when connected to a
low-cost television "color-burst" crystal. The crystal is
placed between XIN and XOUT in parallel with a 1 Mohm
resistor, while XEN is tied high. Since the switchedcapacitor-filter time base is derived from the crystal
oscillator, the frequency accuracy of all portions of the
20C89 depends on the time base tolerance. The SSI
OTMF Receiver frequency response and timing is

0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0

*#
A
B
C
0
Table 1

1-27

Hexadecimal code
06
05
04
02
01
DO
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0

0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

The digital outputs become valid and OV signals a
detection after a valid tone pair has been sensed. The
outputs and OV are cleared when a valid pause has
been timed.

DETECTION FREQUENCY

Low Group

Generator
The OTMF generator on the SSI 20C89 responds to a
hexadecimal code input with a valid tone pair. Pins
04-07 are the data inputs for the generator. A high to
low transition on LATCH causes ·the hexadecimal code
to be latched internally and generation of the appropriate OTMF tone pair to begin. The OTMF output is
disabled by a high on RESET and will not resume until
new data is latched in.

to

High Group

to

Row 0 = 697 Hz

Column 0 = 1209 Hz

Row 1 = 770 Hz

Column 1 = 1336 Hz

Row 2 = 852 Hz

Column 2

Row 3 = 941 Hz

Column 3

= 1477 Hz
= 1633 Hz

DTMF OUT
The output amplitude characteristics listed in the
specifications are given for a supply voltage of 5.0 V.
However, the output level is directly proportional to the
supply, so variations in it will affect the OTMF output.
A recommended line interface for this output is shown
below.

Digital Inputs
The 04,05,06,07, LATCH, RESET inputs to the OTMF
generator may be interfaced to open-collector TIL with
a pull-up resistor or standard CMOS. These inputs
follow the same hexadecimal code format as the
OTMF receiver output. Table 1 shows the code for each
digit. The dialing matrix and detection frequency table
below list the frequencies of the digits.

1:1

DTMFOUT

1----...,. ~OTIP

L~-.--OR'NG

DTMF DIALING MATRIX
ColO

Col 1

Col 2

Row 0

CD

IT]

[2]

0

Row 1

8]

0

[!]

Row 2

[2]

0
0

[!J

[£]

Row 3

c:J

~

0

@]

Col 3
100n

Absolute Maximum Ratings'
DC Supply Voltage (Vp-Vn) ...................... + 7V
Voltage at any Pin (Vn =0) ........... - 0.3 to Vp + 0.3 V
01 N Voltage ...................... Vp + 0.5 to Vp-1 0 V
Current through any Protection Device ........ ± 20mA
Operating Temperature Range ....... -40°C to +85°C
Storage Temperature ................ -65OC to 150°C

Note: Column 3 is for special applications and is not normally used in telephone
dialing.

*Operation above absolute maximum ratings may damage the device.

1-28

Recommended Operating Conditions
Unit

Min.

Max.

Supply Voltage

4.5

5.5

V

Power Supply Noise (wide band)

-

10

mVpp
cC

Parameter

0

70

-.005

+.005

%

Crystal Shunt Resistor

0.8

1.2

Mn

DTMF OUT Load Resistance

100

-

Ambient Temperature
Crystal Frequency (F Nominal =3.579545 MHz)

n

Digital and DC Requirements

tions do ncit apply to the following pins: DIN, XIN, XOUT,
and DTMF OUT. Positive current is defined as entering
the circuit. Vn = 0 unless otherwise stated.

The following electrical specifications apply to the
digital input and output signals over the recommended
operating range unless otherwise noted. The specifica·

Parameter

Test Conditions

Min.

Max.

Unit

Supply Current*

-

-

30

mA

Power Dissipation

-

-

225

mW

Input Voltage High

-

0.7Vp

Input Voltage Low

-

Input Current Low

-

Output Voltage High
Output Voltage Low

Input Current High

-

V

0.3Vp

V

10

J.l.A

-10

-

J.l.A

loh= -0.2mA

Vp·0.5

-

V

101 = +O.4mA

-

Vn +0.5

V

'with DTMF output disabled

DTMF Receiver
Electrical Characteristics
Test Conditions

Parameter

Frequency Detect Bandwidth

-

Min.

Typ

Max.

Unit

±(1.5+2Hz)

±2.3

±3.5

%Fo
dBmltone

Amplitude for Detection

Each Tone

-32

-

-2

Twist Tolerance

-10

-

+10

dB

60Hz Tolerance

-

Vrms

Dial Tone Tolerance

Precise Dial Tone

-

-

0.8
0

dB*

Speech Immunity

MITEL Tape #CM7290

-

2

-

Noise Tolerance

MITEL Tape #CM7290

-

-

Input Impedance

-

100

-

• Referenced to fowest amplitude tone

1·29

-12

-

hits
dB*

kn

Timing Characteristics
Parameter

Symbol

Min.

Tone Time for Detect

ton

40

Max.

-

Unit
ms

Tone Time for No Detect

ton

-

20

ms

Pause Time for Redetection

toff

40

-

ms

Pause Time for Bridging

toff

-

20

ms

Detect Time

td1

25

46

ms

Release Time

tr1

35

50

ms

Data Set Up Time

tsu1

7

-

Data Hold Time

thd1

4.2

5.0

/ls
ms

Output Enable Time

-

200

ns

Output Disable Time

-

200

I

ns

DTMF Generator
Electrical Characteristics
Test Conditions

Parameter
Frequency Accuracy
Output Amplitude
Low Band
High Band
Output Distortion

-

Min.

Max.

Unit

-1.0

+1.0

%Fo

-

R1=100ntoVn, Vp-Vn=5.0V

-

-7.2

dBm

-6.6

-4.6

dBm

-20

dB

-

DC to 50kHz

-

-

-·9.2

Timing Characteristics
Max.

Unit

Start-Up Time

tstart

-

2.5

fts

Data Set-Up Time

tsu2

100

ns

Data Hold Time

thd2

50

-

RESET Pulse Width

trp

100

LATCH Pulse Width

tpw

100

Parameter

Symbol

Min.

1-30

-

ns
ns
ns

JifuonJl rJfunr

,CA.::~.71.4.).7.31.-7.1 .0.,T.W.X.9.1.0-.5.95.-.28.0.9

______________________
14.3.51.M.Y.fo.r.d.RO.O.d.,T.u.st.in__

_____________________

Timing Diagrams
DTM F Decoder

DTMF Generator

04,05,06,07

-=::x: ~
=:.J

--1

ISU 2

Ihd2

b=---------

X'-________________

~Ipw--l

1
;.1-------------~tpw-...,I. . .
1)----;:===:.~1
_________________
~I
RESET
-

LATCH

I---(Note

L I_ _ _ _ _ _ _ _ _ __ _

---I I--- 's'ar'

!---Ir --!
p

OTMFOUT----------~CC____________>;~--------------------Note 1: The indicated time may be as small as 0 sec meaning that the LATCH and
RESET lines may be tied together.

PLASTIC DIP
22 Pins

~~,-E::::::]
1_-_·,--t.200tJO.48IMAX

,,-----::.J

;~~t-I
360 It 144)

I

nl
01510.341)
-~)

~ -:~: :!!::~:-j

No responsibility is assumed by SSi for use of this product
nor for any infringements of patents and trademarks or other
rights of third parties resulting from its use. No license is
1-31

granted under any patents, patent rights or trademarks of
SSi. SSi reserves the right to make changes in
specifications at any time and without notice.

J~~ffunJ'"

~~g~scewerWiH1

________N_N_O_VA_J_O~IN IN_T_E_G_RA_J_IO_N_________C
__O-II-pr-O-g-re-S-s-D-e-t-e-c-tio_n__

Data Sheet
GENERAL DESCRIPTION
Silicon Systems' new SSI 20C90 is a complete Dual
Tone Multiple Frequency (DTMF) Transceiver that can
both generate and detect all 16 standard Touch-Tone
digits. The SSI 20C90 circuit integrates the performance
proven SSI 202 DTMF Receiver with a new DTMF
generator circuit.
The DTMF Receiver electrical characteristics are identical to the standard SSI 202 device characteristics. The
DTMF generator provides performance similar to the
Mostek MK5380, but with an improved (tighter) output
amplitude range specification and with the addition of
independent latch and reset controls.
An additional feature of the 20C90 is "imprecise" call
progress detector. The detector detects the presence of
Signals in the 305-640 Hz band.
The only external components necessary for the SSI
20C90 are a 3.58 MHz "colorburst" crystal with a
parallel 1 Mn resistor. This provides the time base
for digital functions and switched capacitor filters in the
device. No external filtering is required.

FEATURES
• DTMF Generator and Receiver on one chip
• 22·Pin plastic DIP
• Low· power 5 Volt CMOS
• DTMF Receiver exhibits excellent speech immunity
• Three·state outputs (4·bit hexadecimal) from DTMF
Receiver
• AC-coupled, internally' biased analog input
• Latched DTMF Generator inputs
• Analog input range from - 32 to - 2 d Bm (ref 600 n )
• DTMF output typo - 8 dBm (Low Band) and - 5.5 dBm
(High Band)
• Uses inexpensive 3.579545 MHz crystal for reference
• Easily interfaced for microprocessor dialing
• Call progress detection

03

22

02

21

07

D1

20

D6

19

D5

18

D4

DO
DE

SSI20C90

OV

VP

17

LATCH

XEN

16

RST

DIN

15

DET

XOUT

14

LIN

XIN

10

13

DTMFOUT

ATB

11

12

VN

Pin Out
(Top View)

CAUTION: Use handling procedures necessary
for a static sensitive component

551 20C90 Block Diagram
1-32

SSI20C90

DTMF Transceiver with
Call Progress Detection

CIRCUIT OPERATION
Receiver
The OTMF Receiver in the SSI 20C90 detects the
presence of a valid tone pair (indicating a single dialed
digit) on a telephone line or other transmission medium.
The analog input is pre·processed by 60 Hz reject and
band splitting filters, then hard·limited to provide
Automatic Gain Control. Eight bandpass filters detect
the individual tones. The digital post·processor times
the tone durations and provides the correctly coded
digital outputs. The outputs will drive standard CMOS
circuitry, and are three·state enabled to facilitate
bus·oriented architectures.

20C90 depends on the time base tolerance. The SSI
OTMF Receiver frequency response and timing is
specified for a time base accuracy of at least
± 0.005%. ATB is a clock frequency output. Other
devices may use the same frequency reference by tying
their ATB pins to the ATB of a crystal connected
device. XIN and XEN of the auxiliary devices must then
be tied high and low respectively, XOUT is left floating.
XOUT is designed to drive a resonant circuit only and
is not intended to drive additional devices. Ten devices
may run off a single crystal·connected SSI 20C90 as
shown below.

Vp

XIN

DIN
This pin accepts the analog input. It is internally biased
so that the input signal may be AC coupled. The input
may be DC coupled as long as it does not exceed the
positive supply. Proper input coupling is illustrated
below.

10
ATB

SSI20C90

7

XEN

11

XIN CONNECTED TO Vp
Vp

Vp

I

I

I

VIN>Vp

VIN---0~
DIN

.01J.tF

~

10pF

SSI20C90

II
I
I

11

I

>--fKV-~
DIN
I Q.

r-

10pF

>100k!l

I

I

7

XEN

UP TO 10 DEVICES

!!:

I
I

I
I

10

Receiver Outputs and the DE Pin
Outputs 00,01,02,03 are CMOS push·pull when enabled
(DE low) and open·circuited (high impedance) when
disabled (DE high). These digital outputs provide the
hexadecimal code corresponding to the detected digit.
The table below shows that code.

I
GND

GND

The SSI 20C90 is designed to accept sinusoidal input
wave forms but will operate satisfactorily with any input
that has the correct fundamental frequency with har·
monics greater than 20 dB below the fundamental.
Crystal Oscillator
The SSI 20C90 contains an onboard inverter with suffi·
cient gain to provide oscillation when connected to a
low·cost television "color·burst" crystal. The crystal is
placed between XIN and XOUT in parallel with a 1 Mohm
resistor, while XEN is tied high. Since the switched·
capacitor·filter time base is derived from the crystal
oscillator, the frequency accuracy of all portions of the

Digit

Input:
Output:

07
03

1
2
3
4
5
6
7

0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0

8
9
0

*#
A
B
C
0
Table 1

1-33

Hexadecimal code
06
05
04
02
01
DO
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0

0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

DTMF OUT

The digital outputs become valid and DV signals a
detection after a valid tone pair has been sensed. The
outputs and DV are cleared when a valid pause has
been timed.

The output amplitude characteristics listed in the
specifications are given for a supply voltage of 5.0 V.
However, the output level is directly proportional to the
supply, so variations in it will affect the DTMF output.
A recommended line interface for this output is shown
below.

Generator
The DTMF generator on the SSI 20C90 responds to a
hexadecimal code input with a valid tone pair. Pins
D4-D7 are the data inputs for the generator. A high to
low transition on LATCH causes the hexadecimal code
to be latched internally and generation of the appropri·
ate DTMF tone pair to begin. The DTMF output is
disabled by a high on RESET and will not resume until
new data is latched in.

DTMFOUT

1:1
~OTIP

1 - - - -......

~ORING

Digital Inputs

woil

The D4,D5,D6,D7, LATCH, RESET inputs to the DTMF
generator may be interfaced to open·collector TTL with
a pull-up resistor or standard CMOS. These inputs
follow the same hexadecimal code format as the
DTMF receiver output. Table 1 shows the code for each
digit. The dialing matrix and detection frequency table
below list the frequencies of the digits.

Call Progress Detection
The Call Progress Detector; consists of a bandpass
filter and an energy detector for turning the on/off
cadences into a microprocessor compatible signal.

DTMF DIALING MATRIX
LIN Input
ColO

Col 1

Col 2

Col 3

Row 0

CD

IT]

~

Row 1

0

Row 2

0

0
0

0
0
0

[!]
@]

Row 3

8

~

0

@]

This analog input accepts the call progress signal and
should be used in the same manner as the receiver
input DIN.
DET Output
This output is TTL compatible and will be of a frequency
corresponding to the various cadences of Call Progress
signals such as, on 0.5 sec/off 0.5 sec for a busy tone,
on 0.25 sec/off 0.25 sec for a reorder tone and on 0.8-1.2
sec/off 2.7-3.3 sec for an audible ring tone.

Note: Column 3 is for special applications and is not normally used in telephone

Absolute Maximum Ratings·

dialing.

DC Supply Voltage (Vp-Vn) ...................... + 7V
Voltage at any Pin (Vn = 0) ........... - 0.3 to Vp + 0.3 V
DIN Voltage ...................... Vp + 0.5to Vp-10V
Current through any Protection Device ........ ±20 mA
Operating Temperature Range ....... - 40°C to + 85°C
Storage Temperature ................ -65°C to 150°C

DETECTION FREQUENCY
Low Group fo

= 697
= 770
Row 2 = 852
Row 3 = 941
Row 0

Hz

Row 1

Hz
Hz
Hz

High Group fo

= 1209
= 1336
Column 2 = 1477
Column 3 = 1633
Column 0

Hz

Column 1

Hz

*Operation above absolute maximum ratings may damage the device.

Hz
Hz

1-34

Recommended Operating Conditions
Unit

Min.

Max.

Supply Voltage

4.5

5.5

V

Power Supply Noise (wide band)

-

10

mVpp
°C

Parameter.

0

70

-.005

+.005

%

Crystal Shunt Resistor

0.8

1.2

Mn

DTMF OUT Load Resistance

100

-

n

Ambient Temperature
Crystal Frequency (F Nominal = 3.579545 MHz)-

Digital and DC Requirements
The following electrical specifications apply to the
digital input and output signals over the recommended
operating range unless otherwise noted. The specifica·

tions do not apply to the following pins: LIN, DIN, XIN,
XOUT, and DTMF OUT. Positive current is defined as
entering the circuil. Vn =0 unless otherwise stated.

Min.

Max.

Supply Current'

-

-

30

mA

Power Dissipation

-

-

225

mW

Input Voltage High

-

0.7Vp

-

V

-

0.3Vp

V

-

10

IJ.A

Parameter

Test Conditions

Input Voltage Low

Unit

Input Current Low

loh= -0.2mA

Vp·0.5

-

IJ.A

Output Voltage High
Output Voltage Low

101= +0.4mA

-

Vn+0.5

V

Input Current High

-10

V

·with DTMF output disabled

DTMF Receiver
Electrical Characteristics
Parameter

Test Conditions

Min.

Typ

Max.

±(1.5+2Hz)

±2.3

±3.5

%Fo

-2

dBm/tone

Frequency Detect Bandwidth

-

Amplitude for Detection

Each Tone

-32

Twist Tolerance

-

-10

60Hz Tolerance

-

Dial Tone Tolerance

Precise Dial Tone

Speech Immunity

MITEL Tape #CM7290

-

Noise Tolerance

MITEL Tape #CM7290

-

Input Impedance

-

100

2

-

Unit

+10

dB

0.8

Vrms

0

dB'

-

hits

-12

dB'

-

kn

*Referenced to lowest amplitude tone

Timing Characteristics
Symbol

Min.

Max.

Unit

Tone Time for Detect

ton

40

-

ms

Tone Time for No Detect

ton

-

20

ms

Parameter

1·35

Timing Characteristics (cont.)
Parameter

Symbol

Min.

Pause Time for Redetection

toff

40

-

ms

Pause Time for Bridging

toff

-

20

ms

Detect Time

td1

25

46

ms

Release Time

tr1

35

50

ms

Data Set Up Time

tsu1

7

-

J.!s

Data Hold Time

thd1

4.2

5.0

ms

-

200

ns

200

ns

Output Enable Time

-

Output Disable Time

-

Max.

Unit

DTMF Generator
Electrical Characteristics
Test Conditions

Parameter
Frequency Accuracy
Output Amplitude

R1

=100.0.

to Vn, Vp - Vn =5.0 V

Min.

Max.

Unit

-1.0

+ 1.0
-

%Fo

-

-

Low Band

-

-9.2

-7.2

dBm

High Band

-

-6.6

-4.6

dBm

-20

dB

Output Distortion

-

DC to 50kHz

Timing Characteristics
Max.

Unit

Start·Up Time

tstart

-

2.5

J.!s

Data Set·Up Time

tsu2

100

-

ns

Data Hold Time

thd2

50

ns

RESET Pulse Width

trp

100

-

LATCH Pulse Width

tpw

100

-

ns

Parameter

Symbol

Min.

ns

Call Progress Detector
Electrical Characteristics
Conditions

Parameter
Amplitude for Detection
Amplitude for No Detection
Detect Output

305 Hz - 640 Hz

Min.

Max.

Unit

-40

0

dBm

305 Hz - 640 Hz

-

-50

dBm

I >2200Hz, <160Hz

-25

dBm

Logic 0

-

.5

V

Logic 1

4.5

-

V

VDD -10

VDD

100

-

V
kn

"LIN" Input

Max Voltage

Input Impedance

500 Hz

Timing Characteristics
Max.

Symbol

Min.

Signal Time lor Detect

ton

40

-

ms

Signal Time for No Detect

ton

-

10

ms

Interval Time for Detect

tolf

40

-

ms

Interval Time lor No Detect

toff

-

20

ms

Parameter

Unit

Detect Time

td2

-

40

ms

Release Time

tr2

-

40

ms

1·36

1.4 35.1 M.Y fO.'~.R O.~ :.T ~C.At~i.n7,.,~.).7.31._7.1.10.,T.W.':.'

.........................

..

Timing Diagrams

DTM F Decoder

OIN
01,02,04,08

OV

1__ ---I',r, I-I
I
tSU1~ I----J t--thdl
I
I

~tdl

DTMF Generator

04,05,06,07

-==x --I
::::j

LATCH

'.1.0.-5.9.5-.2.80.9.........................

Ihd2

f:::---------------

X

ISU2 I---Ipw---l

--.J
1
~tpw I..

1.-------------(Note 1)----;::==:::::..~1

..

1

1..._ _ _ _ _ _ __

RESET _ _ _ _ _ _ _ _ _ _ _.....

--l I--

~ Irp

Islarl

---I

OTMFOUT-----~C(============»-------------Note 1: The indicated time may be as small as 0 sec meaning that the LATCH and RESET lines may be tied together.

Call Progress Detector

OET------'

PLASTIC DIP

22 Pins

~~~,~::

::::::]

1_ _

410 (10.414)
.310 (9.652) -

1200(3048)MAX~

.175 (4.445)

MAX

~~=±

r

.060 (i.524)

.oisl0-3U)

,-1

~W W,-11;=f

J10 (2.79o!J .a90 (2.286) ~3 (.5842) .160 (4.064)
.090 (2.286) .Q75 (1.905) .015 (.3810) .100 (2.540)

No responsibility is assumed by SSi for use of this product
nor for any infringements of patents and trademarks or other
rights of third parties resulting from its use. No license is

.015 (0.381)
.... (0.2032)

r-:~~ ::J.:~H

granted under any patents, patent rights or trademarks of
SSi. SSi reserves the right to make changes in
specifications at any time and without notice.

1-37

551957
DTMF Receiver
with Dial Tone
Reject Filter

JhJl rJkmJ'"
INNOVATORS IN INTEGRATION

Data 5heet
GENERAL DESCRIPTION
The SSI 957 combines switched-capacitor and digital
frequency measuring techniques to decode Dual-Tone
Multifrequency (DTMF) signals to four bit binary data.
Dial tone rejection and 60 Hz noise rejection filters are
built in. Fabricated as a monolithic integrated circuit
using low power CMOS processing, the SSI 957 is
packaged in a 22-pin DIP and operates from a single 5
through 12 volt DC supply. An inexpensive 3.58 MHz
television crystal and a resistor are the only external
components required. High system density may be
achieved by using the clock output of one crystal
connected receiver to drive the time bases of additional
receivers.
The SIGNAL IN input to the SSI 957 interfaces readily
to telephone lines, radio receivers, tape players, and
other DTMF signal sources. Inputs A and B control
sensitivity to a maximum of -38 dBm, while the 12/16
input determines the signals to be detected. The preprocessing stages of the SSI 957 filter out dial tone and
noise, split the signal into its high frequency group and
low frequency group components, and hard limit each
component to provide automatic gain control. Four
discriminators in each group then detect the individual

so

12/16

tones. Post-processing stages of the SSI 957 time the
tone durations and store binary data for outputting as
determined by the HEX input. The STROBE output is
activated by the presence of valid data in the output
register and cleared by the detection of a valid end-ofsignal pause or by the CLEAR input. An early signal
presence indicator, BD, facilitates applications requiring
tone blocking. The data outputs operate with simple
logic circuits or microprocessors, and are tristate
enabled to facilitate bus-oriented architectures.
FEATURES
• Complete DTMF receiver in 22-pin DIP
• Decodes all 16 DTMF digits
• Excellent dial tone and speech immunity
• Meets telephone impulse noise immunity standards
• Digitally selectable sensitivity to - 38 dBm
• Selectable 4-bit hexadecimal or binary-coded 2-01-8
output
• Fabricated using low-power CMOS technology
• Operates on single DC supply
• Uses inexpensive 3.58 MHz crystal
• Second source 01 Teltone M-957

HEX

DE

DO

22

01

HEX

21

02

DE

20

03

VNO

19

CLEAR

12116

18

STROBE

VP

17

AUXCLK

SO

16

osc/elK

15

XIN

14

XOUT

N/C

10

13

Vt---\ f

NOTE: COUPLING
CAPACITOR MUST BE USED
WHEN VIN IS GREATER
THAN VP.

Figure 3.lnput Signal Configuration

8

852

1336

1000

1001

9

852

1477

1001

1010

0

941

1336

1010

1101

*

941

1209

1011

1100

#

941

1477

1100

1110

A

697

1633

1101

0011

B

770

1633

1110

0111

C

852

1633

1111

1011

D

941

1633

0000

1111

Absolute Maximum Ratings (Note 1)
DCSupplyVoltage(Note2) ................. , .. 16.0V
VoltageonSIGNALIN ....... (VP + 0.5V) to (VP -22V)
Voltage on Any Pin Except
SIGNAL IN ............... . (VP + O.5V)to(VND-0.5V)
Storage Temperature Range. . . . . . . .. - 65° to 150ce
Operating Temperature Range .......... -40° to 85°C
Lead Soldering Temperature ....... 260 °C for 5 seconds
Power Dissipation .............................. 1W
Notes:
1.

Exceeding these ratings may permanently damage the 55l 957.

2. VP referenced to VND, VND should be a equal potential to VNA.
VND and VNA are normally grounded.

Note: The SSI 957 detects signals A through D when the 12116 input is at
logic "0".

1-40

Table 4: Electrical Specifications (- 40"C :;; TA :;;
Parameter

SIGNAL IN Input
Requirements

+ 85 0c)

Conditions

Min

Typ

VP= 12V

-

+6

dBm

A=1,B=0

-27

-

+3

dBm

1

A=O, B= 1

-30

-

0

dBm

1

-

dBm

-

-

1

1

-

-32

-

-2

dBm

1

-35

-

-5

dBm

1

A=O, B=1

-38

-

-8

dBm

1

-

dBm

1

-

-

-40

±2.5% ±(1.5%+2)

Signal Frequency
Deviation Without
Detection

-

Twist

-

-

-

Gaussian Noise

-

-

-

Dial tone Level (per
tone, F,;; 480 Hz)

±3.5% ±3.0%

-

Hz

-

Hz

-

± 10

dB

2

12

A-7

dB

3

-

-

A+22

dB

4

0

-

3.6

V

5

Logic 0 Voltage

VP= 12V
VP=5V

0

-

1.5

V

5

Logic 1 Voltage

VP= 12V

8.4

-

12.0

V

5

VP=5V

3.5

-

5.0

V

5

Logic 0 Voltage

VP = 12V,lo = 1.0mA

0

-

1.2

V

5

VP = 5V,l o = O.4mA

0

-

0.5

V

5

VP=12V,l o = -0.5mA

10.8

-

12.0

V

5

VP = 5V,l o = - 0.2mA

4.5

-

5.0

V

-

-

10.0

p..A

Logic 1 Voltage
Tri-State Leakage
Miscellaneous
Characteristics

CMOS Latch·up Voltage

Power
Requirements

Supply Current

SIGNAL IN Input
Impedance

-

I

I

-

F = 1kHz, paralleled
with 15 pF

Power Dissipation
(Outputs Open)
Power Supply Wide
Band Noise
(A=O, B=O)

20

I

-

-

5

-

V

7

-

-

0

-

VP = 12V

-

20

40

mA

-

VP=5V

-

9.

18

mA

-

VP = 12V

-

204

480

mW

6

VP=5V

30

90

mW

VP= 12V

-

-

25

mVpp

-

VP=5V

-

-

10

mVpp

-

Notes:
1. With an ambient temperature of 25 °e, the signal duration and signal
interval at minimum, and the signal frequency deviation and twist at
maximum. The unit "dBm" refers to decibels above or below a
reference power of one milliwatt into a 600-ohm load. (For example,

4.

-24 dBm equals 49 mVrms.)

3.

-

-

A=1, B=O

Signal Frequency
Deviation With Detection

2.

-32

-

A=O, B=O

A=1, B=1

Digital Ouput
Characteristics

Notes

-24

VP=5V

-

Units

A=O, B=O

A=1, B=1

Digital Input
Requi rements

Max

-

Signal Level (per tone)

Twist is defined as the ratio of the level of the high-frequency DTMF
component to the level of the low-frequency DTMF component.
With an ambient temperature of 25°C, the signal level at A + 5, the
signal frequency deviation ahd twist at 0, and the signal applied 50

5.
6.
7.

1-41

100k

6

ms off and 50 ms on. The A level is the minimum detect level
selected.
With the signal duration and signal interval at minimum; and the
signal frequency deviation and twist at maximum. The A level is the
minimum detect level selected.
Logic levels shown are referenced to VND.
For an ambient temperature of 25°C.
Power supply excursions above this value can cause device damage.

3.58 MHz

~
RECEIVER
1 AUDIO

r---

SIGIN

P10
P11
P12
P13

00
D1

D2
00

SSI957

Of

AUX

osel
elK

j----l VP
2-T0-4
DECODER

I
RECEIVER
2 AUDIO

f - - l--

SIG IN ClK
SSI957

--

BA

elK

AUX

l
V1
V2

STROBE

I--

DO
D1
D2
D3
Of

Boo

D1
D2

STROBE

OSCi

elK I---HND

4-TO·1
MUX

V

MICROCOMPUTER
(la, 8051, R65OOI11. ETC.)

P20
P21

P14

I
AUX
RECEIVER
3 AUDIO

l---

SIG IN ClK
SSI957

DO
D1
D2
D3

NOTE: All IC'S POWERED FROM 5 VOC_

Df

STROBE

~~~ I----< VND
Figure 4.Multlple Rec;eiver/Microprocessor Interlace

PLASTIC DIP
22 Pins

=.~:::::::]
---=-:i
1_----1.200130_481 MAX

CERDIP
22 Pins

Figure 5. Package Dimensions

1-42

1-43

551980
Con Progress
Tone Detector

INTEGRATION

Data Sheet
DESCRIPTION
The SSI 980 Call Progress Tone Detector circuit
allows automatic equipment to monitor tones in dial
telephone systems that relate to the routing of calls.
Such tones commonly include dial tone, circuits-busy
tone, station-busy tone, audible ringing tones, and
others. By sensing signals in the range of 305 to 640 Hz,
the SSI 980 does not require the use of precision tones
to function. This means that tones which vary with
location or call destination can be detected regardless
of their exact frequency. The SSI 980 is sensitive to
signals from 0 dBm to - 40 dBm.
The low power CMOS switched capacitor filters used in
the SSI 980 derive their accuracy from a 3.58 MHz clock,
which in turn may be derived from other devices in the
system being designed. The SSI 980 is available in
plastic and ceramic DIP 8-pin packages.

FEATURES
• Detects tones throughout the telephone progress
supervision band (305 to 640 Hz)
• Sensitivity to - 40 dBm
• Dynamic range over 40 dB
• 40 ms minimum detect (SO ms to output)
• Single supply CMOS (lOW power)
• Supply range 4.5 to 5.5 V DC
• Uses 3.58 MHz crystal or external clock.
• 8·pin DIP
• Second source of Teltone M·980.

551 980 Block Diagram

XIN

VDD

XOUT

ENABLE

Vss

DETECT

SIGIN

Pin Out
(Top View)
Applications:
• Automatic Dialers
• Dialing Modems
• Billing Systems
• Service Supervision
• Test Equipment
• Traffic Measurement Equipment

CAUTION: Use handling proceduras necessary
for a statiC sensitive component

1-44

551980
Coli Progress Tone Detector
Table 2:
Absolute Maximum Ratings·

Table 1: Pin Functions
Pins

Function

SIGIN

Accepts analog input signal. Voltage
levels given in Table 3, timing in
Table 4.

OETECT

Call progress detect output. Goes to
logic "1" when signal in 305-460 Hz
band is sensed. See Table 4 for
timing.

ENABLE

Application of logic "1" on this pin
enables the output; logic "0" disables
output.

VREF

Supplies voltage at half VDD for
voltage reference of on-chip op amps.

XIN, XOUT

DCSupplyVoltage(VDO-VSS) .................. 16.0V
VoltageonSIGNALIN ......... VDD + 0.5VtoVSS - 22V
Voltage on Any Pin Except
SIGNALIN ................ VDD + 0.5Vto VSS - 0.5V
Storage Temperature Range .............- 65 to 15O·C
Operating Temperature Range ............... Oto 70·C
Lead Soldering Temperature (for 5 sec) ........... 260·C
*Exceeding these ratings may permanently damage the device.

Crystal connections to on-chip
oscillator circuit

VDO

Positive power supply connection

VSS

Negative power supply connection

Table 3:
ELECTRICAL CHARACTERISTICS Ta = 25 "C, VDD - VSS = 4.5 to 5.5 V
Parameter

Conditions

Min.

Typ_

Max_

Unit

Supply Current

Vdd- Vss=5V

-

4

10

mA

Signal level for Detection

305-640 Hz

-40

-

0

dBm

Signal level lor Rejection

305-640 Hz
1'>1025 Hz, <190 Hz

-

-

-50
0

dBm
dBm

"Detect" output

lout = +1mA
Logic 0
Logic 1

"Enable", "XIN" input

-

-

-

-

0.5

V
V

VSS
VDD-0.2

-

VSS+0.2
VDD

V
V

-

4_5

-

lin='10J1.A
Logic 0
Logic 1

-

-

"XIN" Duty Cycle

-

40

-

60

%

"XIN", "XOUT" Loading

-

-

-

10

pF

"VREF" Output
nominal = (VDD + VSS)/2

Deviation
Resistance

-

+2
6.75

kn

"SIGIN" input

Max Voltage
Impedance (500 Hz)

-

VDD
-

kn

-2
3.25
VDD -10
80

Note: dBm is referenced to 600 Q

1-45

-

%

V

Figure 1: Detect and Re,ject Regions
OdBm

MUST DETECT
REGION'

SIGNAL
LEVEL

-4OdBm

NDT DETECT
REGION

-5OdBm

FREQUENCY

Table 4
TIMING CHARACTERISTICS

Ta = 25"C, VDD - VSS = 4.5 to 5.5 V

Parameter

Min.

Conditions

Max.

Unit

Signal Duration for
Detection (tMD)

305-640 Hz

40

-

ms

Signal Duration for
Rejection (tND)

305-640 Hz

-

20

ms

Signal Dropping from:
- 40 to - 50 dBm (t2)
oto - 50 dBm (t1)

40
90

-

ms
ms

-

50

ms

-

20

ms

Interval Duration for Detection

-

Detect Time (tD)
Tone Dropout Bridging (tS)

Figure 2: Basic Timing

SIGIN
DETECT
~
ENABLE===~

Figure 3: Effect of Amplitude on Timing

SIGIN

I

DETECT~

1-46

Figure 4: Applications Circuits

PHONE LINE
AUDIO

3.58 MHz

3.58 MHz

551 20213/4

DV
STROBE

ANALOG
IN
DATA

Dialer

DTMF Receiver

0 -,-.r
....

PINNQ.'

IDENT.

Plastic Dip
8-Pins

~::~

No responsibility is assumed by SSi for use of this product nor for any infringe·
mente. of patents and trademarks or other rights of third parties r$Sulting from
its use. No license Is gral1ted under any patents. patent rights or trademarks of

1-47

5Si. 5S1 reserves the right to make changes In speclfloations at any time and
wlthOl,lt noties.

551981/982
INNOVATORS IN INTEGRATION

Precise Call Progress
Tone Detector

Data 5heet
DESCRIPTION

FEATURES

The SSI 981 and 982 Precise Call Progress Tone Detector circuits enable automatic monitoring of tones in dial
telephone systems for the purpose of routing calls. Built
using CMOS switched capacitor technology, each has
four independent channels for detecting precise tones in
the 305 to 640 Hz range. The outputs of the channels have
a response related to the respective tone durations.

• Detects & decodes precise tones throughout
305-640Hz telephone progress band
• 35dB dynamic range
• Single supply CMOS (low power)
• Adjustable gain sensitivity
• Supply range 4.5 to 5.5 VDC
• Uses 3.58 MHz crystal
• Three-state outputs
• Standard 22-pin DIP
• Second source to Teltone M981 and M982

The SSI 981 and 982 are identical except for the tones
detected. The SSI 981 will decode 350Hz, 400Hz, 440Hz
and 480Hz. The SSI 982 will decode 350Hz, 440Hz,
480Hz and 620Hz tones.

SSI 981/982 Block Diagram

SIGIN

"'"

XRANG

OE
DET4

"'"

9811982

,",UT

",,'

Pin Out
(Top View)

Figure 1

CAUTION: Use handling procedures necessary
for a static sensitive component

1-48

DEm

551 981/982
Precise Call Progress Tone Detector
CIRCUIT OPERATION
The functional block diagram is shown in figure 1. Channels 1 and 2, ·and 3 and 4 are multiplexed, respectively
as shown. Each channel starts with a 4-pole band-pass
filter that reduces the amplitude of out-of-band signals.
The output of the front-end filter is fed into two circuits,
one being a zero-crossing detector which functions as a
limiter-AGC, and the other being a circuit that controls the
level of the interference floor based on the level of the incoming signal. The output of the ZCD, an energy-limited
signal, is fed into a peak-to-peak detector that determines
if the precise frequency is present by checking the
amplitude of the signal from the back-end filter. Pulses
from the peak-to-peak detector, which indicate the
presence of the precise tone, are counted to time the
duration of the input pulsed-tone. If the criteria of the
specifications are met, the appropiate detect output goes
to the high state. As shown in figure 1, all circuitry after
the front-end filters is multiplexed. A digital demultiplexer
follows the P-P detector to provide the four distinct outputs.

(OE ="1") and high impedance when disabled
(OE ="0"). A "1" on a Det pin indicates that the appropiate valid tone pulse was detected (see table 2).
Detect timing is shown is figure 2.
STROBE & EN
The STROBE pin is the logical OR of the DETn outputs
and will indicate when anyone of the four call progress
tones has been detected. STROBE is unaffected by OE
but goes to a high impedance state when EN="O".
XIN, XOUT & X358
Internal timing and clocks are derived from the 3.58MHz
clock. The SSI 981 and 982 contain an on-board inverter
with sufficient gain to provide oscillation when connected
to a low cost "colorburst" crystal. The crystal is connected between XIN an XOUT. A lMohm 10% resistor is
also connected between these pins. In this mode, X358 is
a clock frequency output available to drive other parts requiring the same frequency.
The part will also operate with an external digital clock
(duty cycle 40% to 60%).

SIGIN
The input signal is applied to the SIGIN pin and is ACcoupled into the front-end filters. The SSI 981 and 982
can amplify a low level signal by 10dB when the XRANG
pin is held low.

VREF
Internal analog Signal reference voltage. Noise or interference coupled onto this pin may degrade chip
functionality.

DET OUTPUTS & OE
Outputs DETl-4 are CMOS push-pull when enabled

TST1 & TST2
Manufacturer's special test pins.

Table 1:
TIMING CHARACTERISTICS

TA = 25°C, VDD - VSS= 4.5V to 5.5V

Parameter
Signal Duration for Detection too

Conditions
In band, see Table 1

Time to Detect, too
Bridge Time, tB
Signal Duration for Rejection tiD

Noise at SIGIN: -50dBm, 0.2-3.4 kHz

Min

Max

Units

200

-

ms

-

200

ms

30

ms

160

-

Time to Release tRD

-

ms

200

ms
s

Interval Duration for Detection
of both Signals

High to Low; High, 0 dBm Low, -25 dBm

1

-

DETn pin Enable Time, tEN
Z to Low or High

CL = 50pF, RL = 100kfi

-

100

I1S

-

100

I1S

DETn pin Disable Time, tDS
Low or High to Z

Table 2: FREQUENCY DETECTION
Signal
Present (fo)

Figure 2: TIMING CHARACTERISTICS

981
SIGIN

DET1 DET2 DET3 DET4 OE STROBE EN

982

350Hz 350Hz

1

X

X

X

1

1

1

400Hz 620Hz

X

1

X

X

1

1

1

440Hz 440Hz

X

X

1

X

1

1

1

480Hz 480Hz

X

X

X

1

1

1

1

Other In-Band

0

0

0

0

1

0

1

High Impedance

0

0

0

DETn

Any
1-49

NOTE: Out of band tones may cause short detect pulses if at sufficient
amplitude and pulsed duration.

ELECTRICAL CHARACTERISTICS (O°CS;TAS;70°C)
Parameter

Test Conditions

VDD
Oscillator Frequency Deviation
(at XOUT) Irom 3.57959 MHz

Min

Max

4.5

5.5

Units

V

-0.01

+0.01

%

Power Supply Noise (0.1 - 5) KHz

-

20

mVp·p

Current Drain
(VDD = 5.5V, TA = O°C)

-

30

mA

+1.0
0

% 0110
dBm

-

-50

dBm

-

6

dB

-

0

dBm

VDD

V
Kil
pF
dB

Must Detect Signal:
Frequency Range
Level (2)

In Band, see Table 1

Must Reject Signal:
Level

Noise at SIGIN
- 50 dBm, 0.2 to 3.4 kHz

-1.0
-25

Level Skew between (4) Adjacent
In-Band Signals lor Detection 01 Both
Steady State Responser:
Must Reject Level (3)
SIGN Pin:
Voltage Range
Input Impedance
Gain
XRANG Pin:
VIL
VIH
Pullup Current

10 - 5% >1 >10 + 5%
See Table 1

VDO -10
80

1=500 Hz
XRANG =0

15
10.1

-

0.5

VDO-2.0

---

XRANG = VSS

Detect Pins, DETn:
VOL
VOH
IOZ

ISINK = -1mA
ISOURCE = 1mA
VO = VDD,VSS

STROBE Pin:
VOL
VOH

ISINK = -1mA
ISOURCE = 1mA

OE, ENABLE Pin:
VIL
VIH
Pullup Current

9.9

---

-

-10

-

0.5

VDO-0.5

-

VDO-0.5

VDD-2.0
OE, Enable = VSS

External Clock:
VIL
VIH
Duty Cycle

XOUT Open

XIN, XOUT Loading
Capacitance
Resistance

Crystal Oscillator Active

X358 Pin:
VOL
VOH
Duty Cycle

CL = 20 pF
ISINK = -10 /-lA
ISOURCE = 10 /-lA

-

1
0.5

0.5

-

-

-10

-

0.2

VDO-0.2
40

60

V
V
/-lA
V
V
/-lA
V
V
V
V
/-lA
V
V
%

-

10

20

-

-

0.2

V

-

V
%

VDO -0.2
40

60

pF
Mil

Notes:
(1) All parameters are specified at VDD =5 volts and XRANG at a
logical "hi" state, which implies unity front·end gain. Power levels

(3)

Large input voltage transients may cause excessive ringing in the
highly selective filter, causing spurious detection, The detects are

(4)

Any tone 40Hz· 1% from fo must adhere to this specification,
where fo is defined in Table 1.

in dBm are referenced to SOOn.

(2) A post-filter AGe is employed to enhance end·of·tone detection for
high-level signals. A drop in amplitude of the input tone may
cause an end-of-tone (interval) indication.

not considered as incorrect circuit operation.

1-50

JhJlCA.: ~_71_4_)_73_1_-7_1 _0_,T_W_X_9_1_0-_5_95_-_28_0_9

_____________________1_4_3_51_M_Y_fo_rd_R_o_a_d,_T_us_t_in,__

_____________________

Absolute Maxumum Ratings •
DC Supply Voltage (VDD - VSS) ................. +7V
Voltage on any pin except SIGIN VSS -0.3V to VDD +0.3V
Voltage on SIGIN ............. VDD -18V to VDD +0.3V

Storage Temperature Range ......... -65 0 C to 150 0 C
Operating Temperature Range ........... 0 0 C to 70 0 C
Lead Soldering Temperature .................. 260 0 C
• Exceeding these ratings may permanently damage this device.

Normal Call Progress Tones And Sequence

Tone
Precision Dial Tone
Old Dial Tones

Frequency (Hz)

Cadence
continuous

350
+440

continuous
600 +120
or 133. and other
combinations

Old Busy

600
+120

0.55 on
0.55 off

Precision Reorder

480
+620

0.3 5 on local
0.2 S off reorder

Old Reorder

600
+120

0.2 5 on toll
0.3 S off reorder
0.255 on toll
0.25 5 off local

Old Audible Ringback

440
+480

2 son
4 5 off

420 +40
and other
combinations

2 son
4 5 off

2.31 SECONDS

DIALTONE~

0.55 on
0.55 off

Precision Audible Ringback

TIMING

TONES

o ISECONDS

480
+620

Precision Busy

CALL PROGRESS

AUDIBLE

RING~

~
I

BUSY~

I

REORDER'~
°ISECONDS

2.3

I

SECONDS

"20 INTERRUPTIONS/MIN.

PLASTIC DIP
22 Pins

r6~~~'~:::::::::

]

1_-1.200(J048)MAX~

~mMRlWW:~")

r

060(1524)
~

c-I
110(211)4)

I--W W C-Il;=f
090(2.286)

023(.5842).160(4064)

090(2.21l61.015(1.905}~~

No responsibility is assumed by 58! for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from
its use. No license is granted under any patents, patent rights or trademarks of

SSi. 58! reserves the right to make changes in specifications at any time and
without notice.

1-51

INTEGRATION

SSI K212
Single Chip Bell
212 Modem

Preliminary Data Sheet
INTRODUCTION

FEATURES

The SSI K212 is a true single-chip modem device that
provides the functions needed to construct a typical
Bell 212A standard full-duplex modem. Using an
advanced CMOS process that integrates analog, digital,
and switched-capacitor array functions on a single
substrate, the SSI K212 offers excellent performance
and a high level of functional integration in a single 28
pin DIP configuration. The K212 provides the basic PSK
and FSK modulator/demodulator functions, call progress and handshake tone monitors, test modes, and a
DTMF dialer. This device supports all Bell 212A modes of
operation, allowing both synchronous and asynchronous
communication. The K212 is designed to appear to the
systems designer as a microprocessor peripheral, and
will easily interface with popular one-chip microprocessors (80C51 typical) for control of modem functions
through its 8-bit multiplexed address/data bus or via an
optional serial command bus. An ALE control line Simplifies address demultiplexing. Data communication
occurs through a separate serial port only.

• One-chip fully Bell103/212A compatible modem

The K212 is ideal for use in either freestanding or integral· system modem products where full-duplex 1200
BPS data communications over the 2-wire switched
telephone network is desired. Its high functionality, low
power consumption, and efficient packaging simplify
design requirements and increase system reliability.
A complete modem requires only the addition of the
phone line interface, a control microprocessor, and
RS-232 level converters for a typical system. The use of
coherent demodulation techniques also assures the
user of optimum performance when communicating
over degraded lines.

• Full duplex operation at 0-300 and 1200 BPS
• FSK (300 BPS) or PSK (1200 BPS) encoding
• Compatible with standard microprocessors
(8048, 80C51 typical)
• Serial (22 Pin DIP) or parallel microprocessor bus
interface (28 Pin DIP)
• Maskable interrupts
• Serial port for data transfer
• Selectable asynch/synch and
scrambler/descrambler functions
• Coherent demodulation technique provides optimal
performance
• Call progress, carrier, and long·loop detect monitor
• DTMF tone generator
• Test modes available - ALB, DL, RDL, Mark, Space,
Alternating bit patterns
• Space efficient 22·pin DIP, 28'pin DIP and Quad packages
• CMOS technology for low power
consumption (120 mW)
• Low power IDLE mode uses< 10mW
• Single +12 V supply
• TTL and CMOS compatible inputs and outputs

BLOCK DIAGRAM

ADO-AD7

RO

We
ALE

cs

RESET

INT

STATUS

AND
CONTROL
LOGIC

T,O
R,O

l

RXD

MICROPROCESSOR
BUS

RXC

I-----l-t

TXC

CAP

IM,{l

UART/USART

3.1872 MHz
CRYSTAL

• AC Coupling is not needed when using RXF input,
see spec for Input limitations.

Note: A simple low speed back channel can be configured using a DTMF Encoder and Decoder (SSI202)

Received Output Waveforms
SYNC

RXD

1 . ______--'

L

(a) High SIN Ratio Analog Input

SYNC

RXD

"'-.1

[\1 N

"'-.1 N

N

N

N

(b) Low SIN Ratio Analog Input

The "PRELIMINARY" designation on an SSi data sheet Indicates that the
product Is not yet released fol production. The specificatfons are subject to
change, are based on design goals or preliminary part evaluation, and are
not guaranteed, SSI should be consulted for current information before usIng this product. No responsibility Is assumed by SSI for Its use; nor for any

Infringements of patents and trademarks or other rights of, third parties
resulting from its use: No license Is granted under any patents, patent
rights or trademarks ofSSi. SSI resarves the right to make changes In
speCifications at any time and without notice.

1-71

JifuonJl ~fUnJ

551 K224
Single Chip
V.22 bis Modem

INTEGRATION

(Availability: Fall 1986)

Preliminary Data Sheet

INTRODUCTION
The SSI K224 is a highly integrated single-chip modem
I.C. which provides the functions needed to construct a
V.22 bis compatible modem, capable of 2400 BPS fullcondition~l'\:Y'
duplex operation over dial-up lines. Using an advanced
FEAT.~R
CMOS process that integrates analog, digital signal pro.,;Of\~-fhi~ multi-mo
cessing, and switched-capacitor array functions on a
":~~a~
.i!
single substrate, the SSI K224 offers excellent perfor-.ii·•... ~. F~JI ""'x,ppeJ~iQ a ·'0-300, 1200, and 2400 BPS
mance and a high level of functional integration in a
I,.. .. ~···'F~:K
PSr.···~,Soft (1200 BPS), or QAM (2400
'" 'ir;;:"".ElPS').CI'l'i'I'g."'·
single 28 pin DIP configuration. The K224 provi
QAM, PSK and FSK mOdulator/demodulator,lli\., ~\.P·i·ri'aQ~ .•Softwa
patible with SSI K212 and
call progress and handshake tone monitors,~~e"""\ ·'~,~22 ·1:~hip . ~
and a tone generator capable of prQ06".i,~9· ••;~,.,•.I,riterfas.e8'·dir.· .
tandard microprocessors
answer, and simultaneous 550!lJ)Q . 1'SPO·'
.' (80~S);'80~1 typi .....• ..•• \
required for European apeljlilati:9n~:;t':•••,s.~riji'J.(1~ PI') DI~) Ofpal'al!e,.I>microprocessor bus
all V.22 bis, V.22, V.21 ,~ell,~12A,'a"
'; (~8"'Qin DI~) tq,r C\:lnttol
'
of operation. all
boti\s' chronol,ls
~ . ""Rort'tor t'~ tjansfer
chronous com .
,224 i~ .' gne to a~;••.•.••\.. J,
I~.jnl'
tfi"
pear to the systEl.m
'·~i:r9processo..J,,/i"'......,.....•,
·i., I.(.S
",
h
d
bl Id
bl
4
···'i.·
b!e
hlsync an scram er escram er
peripheral, and ~jll
popularli1,"e~9hip
ns'"
microprocessors e~O
control of modli/m\.
:if ~11:,ynchronous and asynchronous operating
functions through ilts .t,
Pldexbed a~dre:~~data'~~t"
.f / ril'odes
or via an optional $e~.,!,,1 comman
us. n
con '''! \,,' ,.,J"~ Adaptive equalization for optimum performance
line simplifies addr~s's demultiplexing. Data communic~ .'
over all lines
tions occurs through a separate serial port only. The
.,/'
• Programmable transmit gain (15dB, 1dB steps),
K224 is pin and software compatible with the SSI K212
selectable receive boost (+ 12dB)
• Call progress, carrier, answer tone, and signal
and K222 one-chip modem I.C.·s, allowing system
upgrades with a single component change.
quality monitors
The K224 is ideal for use in either free standing or in• DTMF and guard tone generators
tegral system modem products where full-duplex 2400
• Test modes available - ALB, DL, RDL, Mark,
BPS data communications over the 2-wire switched
Space, Alternating bit patterns
telephone network is desired. It's high functionality, low
• Space efficient 22 and 28 pin DIP packages
power consumption, and efficient packaging simplify
• CMOS technology for low power consumption (120
design requirements and increase system reliability. A
MW) with power down mode (30 mW)
complete modem requires only the addition of the phone
• Single + 12 volt supply
line interface, a control microprocessor, and RS-232 level
• TTL and CMOS compatible inputs and outputs

\

(

,·....\·'f.
:j

SSI K224 Block Diagram

,,<

F,e

QUAMI

PULSE
SHAPER

MODULATOR

CAUTION: Use handling procedures necessary
for a static sensitive component

1-72

551 K224
Single Chip V.22 bis Modem
OPERATION
General
The SSI K224 was designed to be a complete V.22 bis
compatible modem on a chip. It requires only the addition of a control microprocessor, RS-232, and a phone
line interface to design a complete modem. As many
functions as possible were included in order to simplify
implementation into typical modem designs. In addition to
the basic 2400 BPS QAM, 1200 BPS PSK and 300 BPS
FSK modulator/demodulator sections, the device also includes synch/asynch converters, scramber/descrambler,
call progress tone detect, and DTMF tone generator
capabilities. All V.22 bis and Bell 212A modes are supported (synchronous and asynchronous) and test modes
are provided for diagnostics. Most functions are selectable as options and logical defaults are provided when
override modes are chosen. The device can be directly
interfaced to a microprocessor via its 8-bit multiplexed
address/data bus for control and status monitoring. Data,communication takes place through a separate serial port.

QAM Modulator/Demodulator
The SSI K224 encodes incoming data into quad bits
represented by 16 possible signal points with specific
phase and amplitude levels. The baseband signal is then
filtered to reduce intersymbol interference on the
bandlimited telephone network. The modulator transmits
this encoded data using either a 1200 Hz (originate
mode) or 2400 Hz (answer mode) carrier. The demodulator
reverses this procedure but also recovers a data clock
from the incoming signal. Adaptive equalization corrects
for varying line conditions by automatically changing filter
parameters to compensate for those line characteristics.
PSK Modulator/Demodulator
The K224 modulates a serial bit stream into dibit pairs
that are represented by four possible phase shifts as
prescribed by the Bell 212AIV.22 standard. The baseband signal is then filtered to reduce intersymbol interference on the bandlimited 2-wire PSTN line.
Transmission occurs on either a 1200 Hz (originate
mode) or 2400 Hz carrier (answer mode). Demodulation
is the reverse of the modulation process, with the incoming analog signal eventually decoded into dibits and converted back to a serial bit stream. The demodulator also
recovers the clock which was encoded into the analog
signal during modulation. Demodulation occurs using
either a 1200 Hz carrier (answer mode or ALB originate
mode) or a 2400 Hz carrier (originate mode or ALB
answer mode). The K224 uses a phase locked loop
coherent demodulation technique that offers inherently
better performance than typical DPSK demodulators used
by other manufacturers. Adaptive equalization is also used in PSK modes for optimum operation with slowly varying line conditions.
FSK Modulator/Demodulator
The FSK modulator frequency modulates the analog output signal using two discrete frequencies to represent the
binary data. The Bell 103 standard frequencies of 1270 Hz
and 1070 Hz (originate mark and space) and 2225 Hz
and 2025 Hz (answer mark and space) are used when this
mode is selected. V.21 frequencies are used when this
mode is selected. Demodulation involves detecting the

received frequencies and decoding them into the appropriate binary value. The rate converter and
scrambler/descrambler are bypassed in the FSK modes.
Passband Filters and Equalizers
A high and low band filter is included to shape the
amplitude and phase response of the transmit signal and
provide compromise delay equalization and rejection of
out of band signals in the receive channel. Amplitude
and phase equalization is necessary to compensate for
distortion of the transmission line and to reduce intersymbol interference in the bandlimited receive signal. The
transmit signal filtering corresponds to a 75% square
root of raised Cosine frequency response characteristic.
Asynchronous Mode
The asynchronous mode is used for communication with
asychronous terminals which may communicate at 1200
BPS + 1%, - 2.5% even though the modem's output is
limited to 1200 BPS ± .01%. When transmitting in this
mode the serial data on the TxD input is passed through
a rate convertor which inserts or deletes stop bits in the
serial bit stream in order to output a signal that is exactly
1200 BPS ± .01%. This signal is then routed to a data
scrambler (following the CCITT V.22 algorithm) and into
the analog PSK modulator where dibit encoding results
in a V.22 bis or Bell 212A standard output Signal. Both
the rate convertor and scrambler can be bypassed for
handshaking, FSK, and synchronous operation. The
device recognizes a break signal and handles it in accordance with Bell 212A specifications. Received data is
processed in a similar fashion except that the rate convertor now acts to reinsert any deleted stop bits and output data to the terminal at no greater than 1219 BPS. An
incoming break signal will be passed through without incorrectly inserting a stop bit.
Synchronous Mode
Synchronous operation is possible only with the QAM or
PSK modes. Operation is similar to that of the asynchronous mode except that data must be synchronized to
a provided clock and no variation in data transfer rate is
allowable. Serial input data appearing at TxD must be
valid on the falling edge ot TxCLK. Receive data at the
RxD pin is clocked out on the rising edge of RxCLK. The
asynch/synch convertor is bypassed when synchronous
mode is selected and data is transmitted out at essentially the same rate as it is input.
Parallel Bus Interface
Six 8-bit registers are provided for control, option select,
and status monitoring. These registers are addressed
with the AO, A 1, and A2 multiplexed address lines (latched by ALE) and appear to a control microprocessor as
six consecutive memory locations. Five control registers
are read or write memory. The status detect register is
read only and cannot be modified except by modem
response to monitored parameters.

SSI K224
Single Chip V.22 bis Modem
operation is initiated when the RD line is taken low. The
next eight cycles of ExCLK will then transfer out eight
bits of the selected address location LSB first. A write
takes place by shifting in eight bits of data LSB first for

eight consecutive cycles of ExCLK. WR is then pulsed
low and data transfer into the selected register occurs on
the rising edge of WR.

Preliminary Pin Configuration
CLK

28

GND

GND

22

RXA

XTAL 1

"Z1

RXA

CLK

21

VREF

XTAL 2

26

VREF

XTAL 1

20

RES

ADO

25

RES

XTAL 2

19

!SET

24

!SET

AD

18

RXCLK

24

RXCLK

A1

22

RXD

AD4

21

AD5

20

AD1
55! K224

AD2
AD3

55!
K224
SER

17

RXD

A2

16

TXD

TXD

DATA

15

EXCLK

CSB

WRB

14

TXCLK

AD6

10

19

EXCLK

ROB

10

13

!NTB

AD7

11

18

TXCLK

VDD

11

12

TXA

ALE

12

17

!NTB

WRB

13

16

TXA

ROB

14

15

VDD

Pin out
Top View

The "PRELIMINARY" designation on an 55i data sheet indicates that the
product is not yet released for production. The specifications are subject to
change, are based on design goals or preliminary part evaluation, and are
not guaranteed. 55i should be consulted for current information before us·
ing this product. No responsibility is assumed by 55i for its use; nor for any

1-74

infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent
rights or trademarks of SSi. SSi reserves the right to make changes in
specifications at any time and without notice.

1-75

551291/213 Modem
1200 BPS
Full Duplex
Modem Device Set

INTEGRATION

Preliminary Data Sheet
GENERAL DESCRIPTION
The SSI 291/213 is a CMOS I.C. device set that forms
the basis for a 1200 bps Be1l212A compatible modem.
The SSI 213 is amodem filter that provides the channel
separation, equalization, and answer/originate steering
logic needed for Bell 212A operation. The 291 contains the
Bell 212 modulator and demodulator, AGC, scrambler/de·
scrambler, and carrier detect monitor. Clock generator and
undedicated low pass filter functions are also included to
minimize the requirement for external components. Using
TIL and CMOS compatible I/O, the device set is designed
to provide a low-cost modem when integrated with a onechip control microprocessor.
The 291/213 device set is ideal for use in either free standing,
or integral system modem products, where full-duplex 1200
bps data communications over the 2-wire switched
telephone network is desired. Its high functionality, reduced
power consumption, and low-cost simplify design
requirements and increase system reliability. A complete
modem can be implemented by adding a phone line
interface, a control microprocessor, and RS-232 level
converters for a typical system. The use of coherent
demodulation techniques assures the user of optimum
performance when communicating over degraded lines.

FEATURES
• Two-chip set compatible with 2-wire PSTN
phone lines
• Available In 40- or 28-pin DIP (SSI291) and III-pin
DIP (SSI 213)
• Full duplex operation at 1200 bps
• PSK encoding in Bell 212A format
• Will interface with standard microprocessors
through serial control lines
• Serial port for data transfer
• Selectable answer/originate, clock frequencies
• Support functions on-Chip: clock generator,
low-pass filter, receive clock flag
• Coherent demodulation technique provides optimal
performance
• CMOS technology for low power consumption
(100 mW typical)
• ± 5V supplies
• TTL and CMOS compatible inputs and outputs

SSI 291/213 Block Diagram

291

213

CLOCK

PSK MODULATOR

PSK DEMODULATOR

SCRAMBLER/DESCRAMBLER

RXD

CAUTION: Use handling procedures necessary

for a static sensitive component

1-76

551 291/21 13 Modem 1200 BPS
Full Duplex Modem Device Set
General
The SSI 291/213 is designed to serve as a low-cost 1200
bps full-duplex modem that offers Bell 212A 1200 bps
compatibility when used with a control microprocessor.
The modulator/demodulator, as well as various support
functions needed to integrate the function with a
microprocessor in a minimum cost system, were
included in the device set. In addition to the basic 1200
bps PSK modulator/demodulator, the product also
includes a carrier detect monitor,
scrambler/descrambler, clock generator, and a DTMF
low-pass filter for eliminating distortion from
microprocessor-generated dual-tones. A zero-crossing
detector simplifies the design of the 300 bps FSK
demodulator function, and signal control logic is
included to ease the addition of this operating mode to
the device set. An included "receive signal flag" can be
used as an interrupt, reducing the load on the system
processor when operating in Bell 212A mode. The 1200
bps Bell 212A mode is supported (synchronous
operation) and test modes are provided for chip
diagnostics. The device set can be directly interfaced to
a microprocessor using serial lines for data transfer,
control, and status monitoring.

back to a serial bit stream. Demodulation occurs using
either a 1200 Hz (Answer mode) or a 2400 Hz
carrier (Originate mode). The 291/213 uses a phase
locked loop coherent demodulation technique that
offers inherently better performance than typical DPSK
demodulators used by other manufacturers.
Passband Filters and Equalizers
A high and low band filter is included in the SSI 213 to
shape the amplitu-de and phase response of the transmit
signal and provide compromise delay equalization and
rejection of out of band signals in the receive channel.
Amplitude and phase equalization is necessary to
compensate for distortion of the transmission line and
to reduce intersymbol interference in the bandlimited
receive signal.
Signal Control Logic
Signal control logic is provided that allows addition.of
the 300 bps mod/demod function to a system using the
SSI 2911213 device set. This logic (see diagram) allows
Single pin routing. of externally provided 300 bps digital
signals to the LSTX and RX outputs for either full or
half-duplex operation.
Synchronous Operation
The SSI 291/213 is designed to provide synchronous
operation at the 1200 bps rate. In this mode, data is
synchronized to a provided clock, and no variation in
data transfer rate is allowable. Proper transmit action
requires that serial input data appearing at TxD be valid
on the falling edge of SGT. A receive data flag acts as a
synchronization device for microprocessor interfacing.
Received data at the RxD pin may be read after the
RXFLG goes low, and this flag is reset after a read
operation by externally setting GLRFLG.

PSK Modulator/Demodulator
The 291/213 modulates a serial bit stream into dibit
pairs that are represented by four possible phase shifts
as prescribed by the Bell 212A standard. The baseband
signal is then filtered to reduce intersymbol interference
on the bandlimited 2-wire PSTN line. Transmission
occurs on either a 1200 Hz (Orginiate mode) or 2400 Hz
carrier (Answer mode). Demodulation is the reverse of
the modulation process, with the incoming analog
signal eventually decoded into dibits and converted

LGO

28

RCVA

AXC

27

LGI

Voo

28

VA

CD

25

GND

SCR

2.

FSKOUT

23

8T212

22

SSt TEST

6tAFiG
RXFLG

=

7

SSt 291Y

AXC

40

LGO

Q

3.

ACVA

VDD

38

LGI

37

VA

CD

36

GND

SCR

35

FSKOUT

CLRFLG

3.

ST212

33

SSI TEST

32

PSKTXE

RXFLG
SSI291
ANS

LSON

TXCPU

HDX
AX
LSAX

40

RXCPU

,.

20

,.

TXD

TXCPiJ
ISON
Rsf

SCT

11

18

XT1

SEL

FRAME

12

17

XT2

SCT

,.

27

HDX

HBFOUT

16XBPS

13

16

PSKOUT

FRAME

15

26

XT1

DIGGND

15

FOSC

fXCi'Ij
SEL

I'iXrl

,.

21

PSKTXE

TEST

10

31

TEST

11

30

TX1i

12

29

AXCPU

13

28

LSAX

AXIN

16

TXIN

VDD

15

,.

ANALOGGND

13

ANS

VCO

16

25

XT2

BXBPS

17

2'

PSKOUT

15XBPS

18

,.

23

AX

TX OUT

16TXC

22

FOSC

RXOUT

AXD

20

21

lSTX

1-77

SSt 213

NC

OSCIN

12

LBFOUT

CLKOUT

11

VSS

,.

eLK SEL
NC

Pin Descriptions Pin Number

I

I

SSI 291

I

Description

Type

Label

I

-

GND

Power ground termination

I

-

VDD

+5V ± 10% power input

I

-

VR

Analog voltage reference

291

1/0

25

36

3

4

26

37

291Y

Power

Control Interface
10

13

I

LSTTL

SEL

-

12

I

LSTTL

RST

-Selects output frequency for clocks as shown:
SEL
RST
16TXC
16XBPS
8XBPS
1
1
0
0

1
0
1
0

8

9

I

LSTTL

21

32

I

LSTTL

PSKTXE

15

LSTTL

FOSC

153_6KHz clock output

ANS

4800Hz
4800Hz
19200Hz
19200Hz

4819Hz
4819Hz
19505Hz
19505Hz

2409Hz
LOGIC 1
9752Hz
LOGIC 1

ANS/ORG mode- A logic "1" selects originate mode
PSK transmit enable -

a "0" enables output
"1" sets PSKOUTto "1"

22

0

-

17

0

LSTTL

8XBPS

8 X 1219Hz clock output

13

18

0

LSTTL

16XBPS

16 X 1219Hz clock output

-

19

0

LSTTL

16TXC

16 X 1200Hz clock output

23

34

I

LSTTL

ST212

Self test: causes mod and demod to operate on the same frequency

7

8

0

LSTTL

RXFLG

Receive data flag - reset to a low level in conjunction with
latching of data at RXD on the rising edge of the SCR clock

6

7

I

LSTTL

CLRFLG

Clear data flag -

A low sets the RXFLG output to a high level

Analog Interface
16

24

0

Analog

PSKOUT

PSK modulator output

1

40

0

Analog

LGO

Output for DTM F filter

28

39

I

Analog

RCVA

Receive analog (from bandsplit filter)

27

38

0

Analog

LGI

Input for two pole low pass DTMF filter

18

26

I

Analog

XT1

Connection for 2.4576MHz crystal

17

25

I

Analog

XT2

Connection for 2.4576MHz crystal

2

1

0

Analog

RXC

AGC analog output

RS·232 Signal Interface
19

30

I

LSTTL

TXD

Input for 1200 bps synchronous data

11

14

0

LSTTL

SCT

Derived synchronous transmit data clock on the rising edge of SCT

14

20

0

LSTTL

RXD

Output for received 1200 bps synchronous data which is latched
into the RXD output on the rising edge of SCR. RXFLG - the
receive data flag is reset to a low level at the same time

5

6

0

LSTTL

SCR

4

5

0

LSTTL

CD

TXD data is latched

Synchronous receive data clock
Carrier detect -

1-78

a low level indicates carrier present

551 291

Pin Descriptions Pin Number

I 291VI

291

~1_1_IO_IL-~Ty~p_e~L-L_ab_e_I__

D_es_c_ri~Pt_io_n__________________________________~

L -_ _

5ignal Control Logic

-

11

I

LSTTL

LSON

9

10

I

LSTTL

TXCPU

Low speed transmit data input to logic

1--

29

0

LSTTL

RXCPU

Low speed receive data input to logic

Low speed online enable

27

I

LSTTL

HDX

Selects half duplex echo logic

-

28

I

LSTTL

LSRX

Low speed receive data from an external FSK Demodulator

-

21

I

LSTTL

LSTX

Low speed transmit data (to an external FSK modulator)

-

23

0

LSTTL

RX

Low speed switched data output (to CPU)
PSK demodulator quadrature signal

t-----'-----

Miscellaneous

-

2

0

Analog

Q

3

0

Analog

I

PSK demodulator in-phase signal

12

15

0

LSTTL

FRAME

Derived synchronous baud clock - 600 Hz signal is low for the first
half of the baud interval and high for the last half

24

35

0

LSTTL

FSKOUT

Receive analog zero crossing detector output

-

16

0

LSTTL

VCO

VCO output from demodulator circuit

20

31

I

LSTTL

TEST

A logic "1" forces the SCT output high

22

33

I

LSTTL

SSITEST

High level selects internal test mode

f---

Operating limits -

551 291

Pin Number

291Y
3

291
4

Label

Parameter

Conditions

Min

Nom

Max

VDD

Supply voltage

-

4.5

5

5.5

V

Supply current

-

-

-

mA

70

°c

-

V

Units

Temperature range

-

VIH

IIH<10pA

2.2

-

VIL

IIL< 1O I.lA

-

-

0.7

V

VOL

IOL = 1.6 mA

-

-

0.4

V

CMOS

IOL = 10pA

-

-

0.2

V

OUTPUTS

IOH = 4Ol.lA

2.6

-

-

V

IOH = 10l.lA

-

VDO-0.2

V

Rise time

CL<100 pF

-

300

ns

Fall time

300

ns

All LSTTL

-

inputs
All LSTTU

-

0

CL <100 pF

-

-

1

40

RCVA

lin

O ANALOG PATH

AIR

V,

vp

V,

AO - - - Audio Out

DIV2

AGND
OIV/2

1", XCKf2

TP1

0== XCK

Ai.

XCK

External Clock

RNV

ReadlWrite

TP2

RS>

22

"
"

CS1

18

PBiRST

RSO
CS>

Acknowledge/
Request New Data

D2
DGND

CAUTION: Use h~ndllng procedures necessary
for a static sensitive component

SSI 263A Pin Out
(Top View)

Signal Diagram

1-86

CSO

D7

"

Chip Select

A '

DO-D7~

I I f777777777777m

,~

VALID

I--T

RSO/RS1IRS2

~

VALID

I

:~r""''"'''''"'?:2><

VALID

TACC---l

VA~ID

>@

RSO/RS1IRS2

w:;;x

:

II

/~----~~~-----r-J~

---oJ TWS :

I
1

--::C:::SO'777------~ 1

-------~/

I

I
~~____~I~~~_______J~

·Valid data latched on first rise or fall of RrVV,

(VDD

1

~~------------'/

CS1

I

Timing Characteristics

I
1

I

I

CS1

1_,--THR

~:""77~777777777777777777777777

~TE
-C-S-O----------- I
I -----------------

~

I

:

_,-TWS--i

R~

TRW-----.,

~TE

:~

VALID

~ i--TH

---R~------~'

'

D7~

~

S-----1 I

csa or CS1

= 4.5 to 5.5 Volts, TA =·40 to

Item

into inactive.

+ 85 deg. C)
Limits

Symbol
Min.

Units.
Max.

Data Setup Time

TS

120"

nsec

Data Hold Time

TH

10""

nsec

TWS

200

nsec

TRW

2.25"

Strobe Width
ReadlWrite Cycle Time
RiselFal1 Time
D7 Output Access Time

J.Lsec

TE

100

nsec

TACC

180

nsec

THR

180

nsec

D7 Output Hold Time
Notes: * Based on color burst frequency .
•• Timing relative to deselect by either CSO, CS1, or RIW changing.

MODE SELECTION CHART
Function

DR1

DRO

'CTL' BIT

HI

HI

HI-LO

AIR active; phoneme timing response; transitioned inflection (most
commonly used mode)

HI

LO

HI-LO

AIR active; phoneme timing response; immediate inflection

LO

HI

HI-LO

AIR active; frame timing response; immediate inflection

LO

LO

HI-LO

Disables AIR output only; does not change previous AIR response

ABSOLUTE MAXIMUM RATINGS
Symbol

Limit

VDD-VSS

7.0

V

Input Voltage

VIN

-0.5 to VDD + 0.5

V

Item
Supply Voltage

Units

D.C. Current at Inputs

IINM

Storage Temperature

TS

-55 to + 125

Operating Temperature

TA

-40 to +85

°C

Power Dissipation

Pd

500

mW

1·90

± 1.0

mA
°C

SSl263A
Electrical Characteristics

Description

Unless otherwise specified, 4.5 :0;; VOD:O;; 5.5; -40 deg. C"5: TA "5: 85 deg. C;
1.50MHz :o;;XCK frequency "5:2.0MHz, when XCK/2 = logic 1 or
0.75MHz S; XCK frequency "5: 1.0MHz, w~en XCK/2 = logic 0
Conditions

POWER SUPPLY
Supply Current

PD/RST= 1, CTL=O

Supply Current

PD/RST = 0, CTL = 1

AUDIO OUTPUT
Output Level

AW phoneme
RL = 50Kohm to GND through 1fJ.F cap.

DC Output Offset
Resistive Loading

AC coupled to AO to GND

Capacitive Loading

To GND to ensure Stable A

Description

0.28VDD

0.37VDD

0.50VDD

0.5VDD

0.6VDD

0.7VDD

10

Conditions

Vpp
V
Kohm

100

pF

Symbol

BIUS CONTR.OL INPUTS, DATA INPUTS (RSO, RS1, RS2, CSO, CS1, 00·07 PD/RST)
Input High Voltage

VIH

VSS+2.4

VDD+0.3

VDC

Input Low Voltage

VIL

-0.3

+0.8

VDC

Input Leakage Current

VIN =0 to VDD

liN

5

Input Capacitance

VIN =0 TA=25°C
measured at f = 1.0MHz

CIN

10

fJ.A
pF

CIN(D7)

20

pF

5.0

fJ.A

IOUA/R)

0.4

VDC

IUA/R)

10

fJ.A

Input Capacitance, D7 Input
Input Current, D7 in
TRI·State "OFF" State

VIN = 0.4 to 2.4 V

IIN(TS)

2.0

07 OUTPUT
D7 Output Low Voltage

ILoad = 0.4 mA into D7

D7 Output High Voltage

I Load = 205 fJ.A out of D7

AIR OUTPUT
Output Low Voltage

IL=3.2 mA into AIR

Output High Leakage Current VOut = 0.0 io VDD
Output Capacitance

VOut=O VDC TAMB=25°C'
f=1.0MHz

COut(A/R)

15

pF

DIV21NPUT
Input Low Voltage

VIUDIV2)

·0.3

.2 VDD

V

Input High Voltage

VIH(DIV2)

.8VDD

VDD+0.3

V

5

fJ.A

Input Leakage

VIN =0 to VDD

1·91

Symbol

Min.

Input Low Voltage

VIH(IC)

-0.3

Input High Voltage

VIH(IC)

2.4

Description

Conditions

Typ.

Max.

Units.

+0.8
VDD+0.3

V

XCLK

VIN

Input Current

= 0.0 to VDD

IIN(C)

5

CIN(C)

Input Capacitance
Duty Cycle

D(XCLK)

0.4

10

pF

0.6

-

TYPICAL MICROPROCESSOR IMPLEMENTATION

ROM

AUDIO AMP
(LM386)

CPU (6808)

"10

"1,

AO

IRQ

A1

07

"1,s

'Y/J-V
GS1

EX
X

05

RS1

PO/RST

04

RSO

07

DO

os

03

<;P,

10

R/iN

02

01

05

02

01

02

04

RST

00

OGNO

03

-

OATA8US
CONTROL8US
02

20

GSO 19

06

A15
4MHZ

= 1.0MHz

1-92

0<,

18
17
16
15
14

~
0..,
06'
Os

V

p..A

1-93

l4.3.5.l.M.Y.fo.rd.R.o.a.d.'T.~.st.In.~.:a.I.,~.r.nr.a_"~.(7.~.4.).7.31.,7.1.10.,.~:

______________________________

__X.9.10.,.59.5.,.28.0.9__________________________________

User's Guide
for
Phonetic Programming Using the SSI 263A
Phonetics

A1, AE1, AH1, AY, E1, E2, EH1, HN, HV, IE, IU, IU1, L1, LB, LF,
OU, R1, R2, U1, UH1, UH2, UH3, YI,:A, :OH, :U, :UH,

Every speech sound (phoneme) in any language may be
represented by a special symbol (phonetic symbol), These
symbols are used in WRITING precisely the sound sequence
(phonetic transcription) of a word according to the way it is
pronounced, There are many different phonetic symbol sets
(phonetic alphabets), Each would contain a minimum number of
symbols to represent the basic sounds (phonemes) required to
pronounce any word in the language, Additional symbols are
usually included which represent sounds with slight to great
variations in the basic sounds (allophones), These symbols are
used to assist in the transcription of words that reflect a regional,
dialectic, or foreign pronunciation,

The NO-SOUND symbols represent silent states, One of these
symbols represents a "pause" state, It is used to separate
phoneme sequences into phrase-like segments which assist in
more closely imitating the natural pausing in human speech for
breathing or for delayed emphasis, The "pause" is treated as a
phoneme when it is selected for a transcription and will be subject
to phoneme parameter programming, It has the ability to maintain
the parametric levels of duration, inflection, amplitude, etc" during
its silence, thus audibly affecting the movement of the preceding
and following phonemes, Other NO-SOUND symbols represent
"hold" states, They are used in combination with BASIC
phonemes or ALLOPHONEs to generate articulation variations on
their pronunciations, The NO-SOUND symbols are:

The process of transcribing a spoken word into its phonetic
components begins with identifying the number of sounds in the
word, then tagging each with a label to specify its type,
Consonants and vowels are the most familiar labels but these may
be broken down into subtypes (e,g" stop consonants, back
vowels, etc,) as the need for more specificity arises, Once the
sounds have been identified, their symbols are selected, then
written in sequence, The resulting transcription should allow
another person to identify the pronunciation without having heard
the word spoken,

HFC, HVC, PA,
Now that there is a tool to use for writing the sounds that are
heard, the next stage is to identify the sounds that are produced
by the SSI 263A speech synthesizer.

551 263A Phoneme Review
Thus far in this program, it has been established that: (1) spoken
words are made up of a series of sounds; (2) each speech sound
in a language may be represented by an identifying symbol; and
(3) the spoken word may be written according to its sound
sequence using these special symbols, Before a word may be
written phonetically, however, users may wish to study further the
SSI 263A speech sounds, What makes one sound different from
another and how these differences may be helpful to phonetic
programming will be essential information for phonetic
programmers,

Note that when using a phonetic alphabet to transcribe words into
their sound sequences, there is not a one-to-one correspondence
between the alphabet characters (orthographics) used to spell
words and the phonetic symbols (phonetics) used to represent
their pronunciations, For example, in the word "phones" there are
6 letters but only 4 sounds, Conversely, the word "I" has 1 letter
but 2 sounds, It may be of some assistance to keep a dictionary
handy for reference, Dictionaries use their own phonetic system to
describe the pronunciations of every word entry, It will be
necessary to learn at least one phonetic alphabet in order to
engage in phonetic transcription, The SSI 263A Phonetic Alphabet
is the referent used in this manual. However, if another system is
already known, it is easily translated into the referent.

The sound that is represented by each phonetic symbol in the SSI
263A Phonetic Alphabet must be audibly learned, The easiest
way to approach this task is to start with the sounds already
known and associate a symbol with them, For example, from
spelling we have already learned that vowels may be "long" or
"short" and are often differentiated by their particular spelling
formats, Every time a word with a "short a" sound is heard (sat,
fat, cat, bat, happy, plaster, ankle, Saturday, amplify, contaminate,
etc,) the symbol IAEI should come to mind, A "long a" sound (fate,
state, bait, lace, maybe, stable, arrangement, etc,) is actually a
diphthong (two sounds combined into a single unit) and may be
represented by the symbols IA AY/.

When transcribing vocabulary from orthography (standard
alphabet spelling) to phonetics, it is common to place the phonetic
sequence between right slash marks when the transcription
appears in running text. The word "phones;' for example, would be
transcribed as IF 0 N ZI when using SSI 263A phonetic symbols,
This allows the reader easier identification of phonetic segments,

551 263A Phonetic Alphabet
The phonetic alphabet used to represent the SSI 263A phonemes
is the SSI 263A PHONETIC ALPHABET. Refer to the Phoneme
Chart for a complete listing of the phoneme symbols,

In standard orthography, there are only 5 vowel letters to
represent 17 vowel sounds, In phonetics, each vowel sound will be
represented by its own symbol or symbol combination,

Of the 64 alphanumeric symbols in the SSI 263A Phonetic
Alphabet, 34 represent sound BASIC to the pronunciation of
American English, The remaining 30 symbols fall into 2 groups:
the ALLOPHONE group and the NO-SOUND group, The BASIC
sound symbols are:

Again, from spelling, we have learned that the letter "c" may have
a hard sound as in "cat" or a soft sound as in "city:' The hard
sound is actually a IKI as in "kite" and the soft sound is an lSI as
in "sing:' Users must identify which sound (/KI or lSI) is used in
the transcription of a "c:' You will not find a symbol C in a phonetic
alphabet. Like "C;' the letters "Q" and "X" will not be found in
phonetic alphabets, They are transcribed into the sound
sequences IK WI and IK PA Sf, Refer to the Phoneme Chart
during this learning period, It provides example words to describe
the pronunciations corresponding to each symbol.

A, AE, AH, AW, B, D, E, EH, ER, F, HF, I, J, K, KV, L, M, N, NG, 0,

00, P, R, S, SCH, T, TH, THV, U, UH, V, W, Y, Z,
Symbols in the ALLOPHONE group represent speech sounds that
vary in pronunciation from one of the basic sounds, They may be
used in transcribing words or word segments (syllables or
morphemes) whose pronunciations are not satisfied by the basic
phonemes alone (words rooted in a foreign language, words
adapted by a regional dialect, etc,), The ALLOPHONE symbols
are:

Users may add more words to the examples above to continue
identifying the symbol-sound relationship for IAEI and IA AY/.
Follow this technique for each symbol in the alphabet. For
auditory verification, enter the sound that is being reviewed into
the device, Speak aloud your example word for the SSI 263A
1-94

sound in an attempt to match that which the synthesizer is
emitting.
Voiced
Voiceless

Example: lEI = "long e" vowel sound
= meat, read, need, repair, before, phoneme,
erase, brief, people, timeliness, seniority,
receive, catastrophe.
Example: IFI

Africa, alphabet, cough.

Users who already have a familiarity with phonetics and SSI 263A
synthetic sounds, may wish to follow the sound review procedures
in order to auditorily determine the difference between two sounds
or identify new ones. For example, enter the IUHI phoneme into
the device. Then enter IUH1/, IUH2/, and IUH3/. Listen to each
sound noting the pronunciation variations. Be aware that there are
no duplicate sounds resident on the SSI 263A chip.
Whenever a SSI 263A sound is audited that cannot be readily
identified as to its appropriate usage, do not be concerned. The
review is designed only to provide a method for establishing an
auditory memory for each sound and a visual memory for its
symbol. Phonetic programming may begin anytime after the initial
review. Return to the review later as your familiarity with the
BASIC sounds increases and as your need for sound alternatives
to those BASIC sounds becomes more apparent.
If there is a question as to which symbols should be chosen to
transcribe a word into its sound sequence, make a written note of
the word by circling the letter(s) that present the problem. Later,
when phonetic programming has begun, a phoneme sequence
may be created for the word and users may verify auditorily which
phonetic selection produces the most appropriate translation.

Consonant Sounds
There are 22 Consonant Phonemes, subdivided according to their
manner of production in the human speech mechanism. Some are
characterized by the noise emitted when the articulators obstruct
the air flow (Fricatives like lSI). Vowel-like consonants have the
least amount of obstruction and may occasionally be used as a
vowel substitute. Stop consonants are obstructed completely,
release of air flow occuring at the onset of the next sound. Notice
that Affricates are a sequence of 2 sounds (a Stop followed by a
Fricative) spoken as a single unit. Unlike vowels, which always
have a vocal source during production, consonants may be voiced
(V) or unvoiced (U) (no vocal source during air flow). When
listening to the manner in which a consonant is produced during
speech, note its special characteristics that distinguish it from all
other consonants. The figure below displays all of the consonant
sounds within their production groups.

Voiced
Voiceless

Stops
B, D, KV
P, T, K

Fricatives
Z, V,J, THV
S, F, SCH,
TH,HF

Nasals
M,N,NG

Consonant sounds are selected for a sequence in much the same
manner as an alphabet character would be selected for the
spelling of a word. Users must be alert, however, to identify the
exceptions. Occasionally, a consonant appears in the spelling of a
word but not in its sound sequence: the "b" in "comb" is not
pronounced and the sound sequence reflects the absence of the
"b": IK OU MI. Some exceptions have grammatical rules that may
be used in determining the appropriate sound. For example, a
consonant may have 2 pronunciations according to its sound
environment. The "s" used to pluralize the two words that follow
are pronounced differently based on whether the sound that
precedes it is voiced or unvoiced. An "s" pronunciation will match
the voicing characteristics of the sound it follows.
Examples: tips = IT I P SI
tabs = IT AE B ZI
There are other types of consonantal exceptions. For example,
the "t" in a word like "nation" is pronounced ISHI and the program
might look like this: nation = IN A AY SH UH3 N/. Users must
listen to each word's pronunciation to determine the appropriate
phoneme selection.
There are 7 Consonant Allophones, each noted in the table below.
The ILl consonant is used in the initial position of a sequence for
words beginning with "I::, while the ILFI allophone will occupy a
medial or final position in a sequence: e.g., lull = IL UH LF/. The
ILBI and the ILiI allophones would be used when a most
constricted pronunciation of an "I:: was required, as would occur
for some words of foreign languages.
Consonant
Phoneme
L

SSI 263A Phoneme Discussion
The SSI 263A Phonetic Alphabet is divided into 3 groups for the
purpose of differentiating between phonemes and allophones.
Another way of dividing the Alphabet is according to usage. The
most familiar division is a two sections split: CONSONANT
sounds and VOWEL sounds. Within each of these sections,
sounds may be further subdivided according to the distinctive
features that best describe the sounds phonetically or
acoustically. The more that is known about a sound, the easier it
is to determine how it may be used in transcribing and phonetically
programming a word.

Glides
W,Y

Consonant Chart
Voiced and voiceless consonants are subdivided into 6
categories according to the manner in which they are
produced in the human vocal tract: i.e., how the air flow
is obstructed by the articulators to make each sound
different.

= "voiceless fricative" consonant
= farm, false, aft, feet, finger, phrase, phone,

Once you have reviewed auditorily the sounds you already have
a familiarity with from spelling, proceed to the BASIC sound list in
the above text and continue the review. Be aware that several
consonant sounds will not provide output unless they have
another sound following. This is the case with IB/, 10/, IP/, ITI, and
IKI. When one of these sounds is entered into the SSI 263A,
follow it by a vowel and listen to both in sequence.

Semi-vowels
R,L

R

Consonant
Allophones
Ll,LB,LF
Rl, R2

Consonant
Phoneme

R
Y

Vowel
Allophone
ER
YI

Allophone Listing for ILl, IR/, & IYI
The IRI is an initial pOSition phoneme. Both IRll and IR21 have
more constricted pronunciations than IRI and may be used in
sequence with soundless interrupts to create a trilled IR/. Often
when the IRI is required in a medial or final position, it is vowelized
and the IERI is used. Listening to the production of all four of
these sounds will auditorily show that they may, occasionally, be
used interchangeably.
Examples: red = IR EH 01
bird = IB ER 01
motor = 1M OU T ERI
The /YI consonant, used as the final sound in words ending with
''y;' has a vowel allophone that may be used as the initial sound of
words starting with Y' Note that both /YI and /YII are auditorily
very close to the lEI and the IIEI vowels and may be considered
interchangeable.
Vowel Sounds
There are 12 BASIC Vowel Phonemes. Vowels are subdivided
according to the manner in which they are produced. All vowels
are voiced sounds but each has a different output based on the
degree of obstruction created by the opening of the mouth and the
tongue pOSition. Lip positions, another obstructing articulator, may
range from spread flat to round. While the lips are in any of these
positions, the jaw may be simultaneously dropped from a closed
to an open position.

Affricates
(0, J)
(T, SCH)

1-95

Closed

~

Open

Front Vowels
Spread
E
I
A
EH
AE

...

Medial Vowels

this: IAH EH EI or IAHI UH3 lEI or IAHI EH3 AY/. In their fullest
durations, a three-sound sequence would over articulate the
diphthong. Shortening the first and last sounds by 1 duration and
the medial sound by 2 durations will produce a more acceptable
pronunciation (see SSI 263A Phoneme Parameters).

Back Vowels
Rounded
U

00

a

UH
(ER)

SS1 263A Phoneme Parameters (Attributes)

AW
AH

To achieve an accurate pronunciation of a word produced by the
SSI 263A synthesizer requires more than a selection of the
appropriate phonemes. Like human speech sounds, synthesized
sounds are further defined by the rate at which they are emitted
(duration), the level of pitch at which they are emitted (inflection or
frequency), and the intensity with which they are produced
(amplitude). These are considered the three major speech
parameters which give the overall production of a word its
linguistic character, transforming simple speech into more
complex language. Inflection, amplitude, and duration are only
three of the parameters that users have control of during the
programming process. The rate at which one sound moves into
another (articulation) is also a controllable parameter. Other
parameters are: the slope of the inflection (slope), the rate of each
selected duration (rate), and the extended inflection frequencies
(extenSion). Users may also select the base frequency at which
speech may be produced (filter frequency). Refer to SSI 263A
Phoneme Parameters, for the range of each and typical default
values selected.

Vowel Quadrilateral
Vowels begin their production with the same voiced
energy. Changes in the position of the tongue (front or
back), the shape of the lips (from spread flat to
rounded), and the position of the lower jaw (from closed
to open) determine the final characteristics that allow
listeners to distinguish between vowel sounds.
Refer to the SSI 263A Phoneme Chart for the pronunciation
reference on each BASIC vowel sound. Utilize the sound review
techniques on the previous pages to practice identifying the vowel
sounds in words and associating them with their phonetic
symbols.
.
The allophonic variations of vowels, 20 in number, are used in a
phonetic program to enhance the pronunciation of a word. There
are some cases where the allophone is required for articulate
pronunciations. This is true for IAY/, /VII and IIUI, which are
integral components in the phonetic sequences for the "long a"
and the varied "long u:'

Every phoneme selected for a sequence must be accompanied by
assignments for each of the eight parameters. As users become
more aware of their need to create different language effects with
their synthesized speech output, they will require the flexibility and
choice that comes with programmable parameters. For example,
with 4 selectable durations per phoneme, each actual
pronunciation of each sound may be changed. Thus, every sound
has four possible outputs increasing the users' choice from 64
phonemes and allophones to 256. Each of the 256 may be
effected differently by each of the 32 possible inflection
assignments. Add to these possibilities 16 variations in amplitude
and 16 variations in rate. The possible combinations are not
limitless, of course, but they are very great and users are
encouraged to experiment with as many as possible.

Examples: same = IS A AY MI
you = /VIIU UI
The table below places each allophone into the vowel
quadrilateral to demonstrate approximately how they might relate
to the BASIC vowels. Users are in no way restricted to traditional
phonetic transcriptions that use only the BASIC vowel phonemes.
Be encouraged to experiment with allophones. Place them in
different positions in a sequence to auditorily check how they
effect the overall pronunciation of a word.

Closed

~

Open

Front Vowels
Spread
YI EllE
AY
AI
EHI
AEI

..

Medial Vowels

E2
UHl
UH2
UH3

Several of the parameters effect synthetic speech output as a
whole. These are articulation, pitch extension, and filter frequency.
Users may select a single level at which to set the filter frequency,
for example, and maintain that level throughout the programming
process.

Back Vowels
Rounded
Ul
IU lUI

au

Phonetic Programming Methodology
Due to the great variety of phonemes and parameter choices, as
well as the different effects the parameter selections have on the
speech sounds, a systematic approach to selecting the variables
is advised. The approach described below is only one of several
that might be used. It may be adjusted to accommodate the user's
special programming style or to accommodate later
implementation of automatic control techniques.

AHI

Allophone Placement in Vowel Quadrilateral
Vowel allophones are placed in the vowel quadrilateral
according to their production features. The sounds they
emit vary slightly from the BASIC vowels that occupy the
same positions.

The first step is to transcribe the target word, phrase, etc., into its
basic phonetic components. Next, enter these sounds into the SSI
263A and auditorily check the output. Use the default values
suggested in the Nominal Phoneme Parameter Table. The results
should be a bit stilted if not misarticulated for the first trial
program. Phoneme adjustment is next. Continue to make changes
in the phoneme sequence, auditorily monitoring the changes, until
an adequate pronunciation of the target is established.

Four vowel allophones-I:A/, I:OH/, I:U/, and I:UHI - are adapted
pronunciations of four of the BASIC vowels. These sounds are
most commonly used for phonetically programming a foreign
word. They may also be used as transitory sounds to link
phonemes with opposite production features such as a round,
open vowel with a very constricted, narrow consonant.
There are five vowels that require two or more vowel sounds in
sequence in order to achieve their pronunciations. These are
generally referred to as diphthongs. Refer to the Diphthong
Conversion Chart.

Begin parameter adjustments. First, maintain articulation, pitch
extension and filter frequency at nominal values. The device
should be kept in the transitioned inflection mode. Make
adjustments in the levels of only one of the remaining 4
parameters at a time, beginning with the duration and moving on
to the inflection, rate, and amplitude (in that order) once the
specific effect that the parameter can make has been made.
Return to a previously adjusted parameter at any time based on
need.

The vowel quadrilateral is a handy tool to use for selecting vowel
phonemes for diphthongs and other multi-phoneme. units. For
example, the diphthong in the word "I" starts with an IAHI and
ends with an lEI. In order to move smoothly from the first sound to
the second (transition), another vowel may be inserted between
these two sounds in sequence. The most likely choice would be a
vowel that falls somewhere between IAHI and lEI in the
quadrilateral: e.g., IUH/, IE HI, III, etc. The sequence may look like

1-96

PHONEME CHART
Hex Code'
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
lA
lB
lC

10
IE
IF
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
*Note -

Phoneme Symbol
PA
E
El
Y
YI
AY
IE
I
A
AI
EH
EHI
AE
AEI
AH
AHI
AW

0
OU

00
IU
lUI
U
Ul
UH
UHl
UH2
UH3
ER
R
Rl
R2
L
Ll
LF
W
B
D
KV
P
T
K
HV
HVC
HF
HFC
HN

Example Word (or Usage)
(pause)
MEET
BENT
BEFORE
YEAR
PLEASE
ANY
SIX
MADE
CARE
NEST
BELT
DAD
AFTER
GOT
FATHER
OFFICE
STORE
BOAT
LOOK
YOU
COULD
TUNE
CARTOON
WONDER
LOVE
WHAT
NUT
BIRD
BOOF
RUG
MUTIER (German)
!,IFT
PLAY
FALL (final)
'liATER
BAG
PAID
TAG (glottal stop)
PEN
TART
KIT
(hold vocal)
(hold vocal closure)
t!EART
(hold fricative closure)
(hold nasal)

z

~ERO

S

SAME
MEASURE
SHIP
VERY
FOUR
THERE
WITH
MORE

J

SCH
V
F
THV
TH
M
N
!:'!lNE
NG
RANG
;A
MARCH EN (German)
:OH
LQWE (French)
FUNF (German)
:U
MENU (French)
:UH
E2
BITIE(German)
LUBE
LB
Hex codes shown with ORO, DR1 = a (longest Duration)

SSI 263A Diphthong Conversion Chart
Phoneme Sequence
Example Words
A AYY

rain, became, stay

A IE EHI UH3 LF

mail, hale, avail

AHI AEI EHI Y

time, rhyme, sky

AHI EHI IE AW UH3 LF
AHI EHI IE UH3 ER

smile, style, while
fire, liar, inspire

UH3 AHI Y

mice, right, sniper

o

road, stone, lower

U

OU 00
AHI AW 0 U
UH3 AHI 0 U
o UHl AHI I IE

tore, four, floor

o

UH3 EHI I 00 LF
IU U U

boil, spoil, doily
tune, spoon, do

YI IU U U

you, few, music

loud, flower, hour
house, about, ouch
boy, noise, annoy

SSI 263A Multi-Unit Conversion Chart
Phoneme Sequence
Example Words
T HFC SCH

church, latch

KV HVC HF

good, lag, angry

D J

just, ledge, wage

KV HF HFC
P HF

lake, corn, check

K HF W
T HF
HFC K HF HVC S

quest, quick, aqua
top, trip, strain

pipe, pay, poor

six, exit, taxi

Nominal Phoneme Parameter Table
(Suggested Default Values for Speech Development)
Amplitude (A3 ---) AO)
Range-O to F (softest to loudest, 0 = silent)
Default-C
Exceptions-KV = 0, B = D = 6
Duration (DR1, ORO)
Range- 3 to 0 (shortest to longest)
Default-O
Filter Frequency Range (F7 ---) FO)
Range-OO to FF (lowest to highest)
Default-E9
Inflection (Pitch) (110 ---) 16, Transitioned Inflection
Mode Only)
Range-O to 1F (lowest to highest, 0 = silent)
Default-04
Extension and Range of Pitch (111,12 ---) 10)
Range-O to 7 (low); 8 to F (high)
Default Value-8
Rate of Speech (R3 ---) RO)
Range-O to F (slowest to fastest)
Default-A
Slope of Inflection (16 ---) 13, Transitioned Inflection
Mode Only)
Range-Ot07
Default-O
Articulation (Rate of) (A3 ---) AO)
Range-O to 7 (slow to fast)
Default- 5

1-97

Example of Using Phonetic Programming Methodology:

au

Developing "Hello"

U
PA
PA

Phoneme Parameters
Pho.D Tln-S ARE FF
KEY:

Pho

~

T
In
S
A
R
E
FF

~

DP
IS
RE
TA
FF

~

o~
~
~
~
~
~
~

~
~
~
~

SSI 263 Register Data
DP IS RE TA FF

Phoneme
Duration
Articulation
Inflection
Slope of Inflection
Amplitude
Rate
Extension and Range of Pitch
Filter Frequency
Duration/Phoneme Register
Inflection/Slope Register
Rate/Extension Register
Articulation/Amplitude Register
Filter Frequency Register

1. Original Phoneme Entry:
Pho.D T In-S ARE
PA .0 5 OA·O C A 8
PA .0 5 OA·O C A 8
HF .0 5 OA·O C A 8
EH .0 5 OA·O C A 8
L
.0 5 OA·O C A 8
.0 5 OA·O C A 8
PA .0 5 OA·O C A 8
PA .0 5 OA·O C A 8

a

FF
E9
E9
E9
E9
E9
E9
E9
E9

DP
00
00
2C
OA
20
11
00
00

a
au

FF
E9
E9
E9
E9
E9
E9
E9
E9

2. Phoneme
Pho.D T
PA .0 5
PA .0 5
HF .0 5
EH .0 5
UH3.0 5
LF .0 5
UH3.0 5
.0 5
.05
U
.0 5
PA .0 5
PA .0 5

Selection Refinement
In-S ARE FF
OA·O C A 8 E9
OA·O C A 8 E9
OA·O C A 8 E9
OA·O C A 8 E9
OA·O C A 8 E9
OA·O C A 8 E9
OA·O C A 8 E9
OA·O C A 8 E9
OA·O C A 8 E9
OA·O C A 8 E9
OA·O C A 8 E9
OA·O C A 8 E9

DP IS
00 50
00 50
2C 50
OA 50
18 50
22 50
18 50
11 50
12 50
16 50
00 50
00 50

3. Duration
Pho.D T
PA .0 5
PA .0 5
HF .1 5
EH .0 5
UH3.2 5
LF .0 5
UH3.2 5
.2 5
.0 5
U
.3 5
PA .0 5
PA .0 5

Adjustment
In-S A R
OA·O C A
OA·O C A
OA·O C A
OA·O C A
OA·O C A
OA·O C A
OA·O C A
OA·O C A
OA·O C A
OA·O C A
OA·O C A
OA·O C A

DP
00
00
6C
OA
98
22
98
91
12
06
00
00

IS RE TA FF
50 AS 5C E9
50 A8 5C E9
50 A8 5C E9
50 A8 5C E9
50 A8 5C E9
50 A8 5C E9
50 A8 5C E9
50 A8 5C E9
50 A8 5C E9
50 A8 5C E9
50 A8 5C E9
50 A8 5C E9

DP
00
00
6C
48
98
22
98
91

IS RE TA
50 A8 5C
50 A8 5C
50 A8 5C
50 A8 5C
50 A8 5C
50 A8 5C
50 A8 5C
50 A8 5C

a
au

a
au

4. Phoneme
Pho.D T
PA .0 5
PA .0 5
HF .1 5
EH1.1 5
UH3.2 5
LF .0 5
UH3.2 5
.2 5

a

E
8
8
8
8
8
8
8
8
8
8
8
8

FF
E9
E9
E9
E9
E9
E9
E9
E9
E9
E9
E9
E9

and Duration Adjustment
In-S ARE FF
OA·O C A 8 E9
OA·O C A 8 E9
OA·O C A 8 E9
OA·O C A 8 E9
OA·O C A 8 E9
OA·O C A 8 E9
OA·O C A 8 E9
OA·O C A 8 E9

RE
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8

TA
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C
5C

5
5
5
5

5. Inflection
Pho.D T
PA .0 5
PA .0 5
HF .1 5
EHI .1 5
UH3.2 5
LF .0 5
UH3.2 5
.2 5
.0 5
.2 5
U
PA .0 5
PA .0 5

Address 000
001
010
011
lXX

IS RE TA
50 A8 5C
50 A8 5C
50 A8 5C
50 A8 5C
50 A8 5C
50 A8 5C
50 A8 5C
50 A8 5C

.0
.2
.0
.0

FF
E9
E9
E9
E9
E9
E9
E9
E9
E9
E9
E9
E9

FF
E9
E9
E9
E9
E9
E9
E9
E9

8
8
8
8

E9
E9
E9
E9

12
96
00
00

50
50
50
50

5C
5C
5C

E9
E9
E9

Adjustment
In-S A R
08·0 C A
08·0 C A
OA·O C A
08·0 C A
09·0 C A
08·0 C A
05·0 C A
05·0 C A
06·0 C A
07·0 C A
OA·O C A
08·0 C A

E
8
8
8
8
8
8
8
8
8
8
8
8

FF
E9
E9
E9
E9
E9
E9
E9
E9
E9
E9
E9
E9

DP
00
00
6C
48
98
22
98
91
12
96
00
00

IS RE TA
58 A8 5C
58 A8 5C
50 A8 5C
40 A8 5C
48 A8 5C
40 A8 5C
28 A8 5C
28 A8 5C
30 A8 5C
38 A8 5C
50 A8 5C
58 A8 5C

FF
E9
E9
E9
E9
E9
E9
E9
E9
E9
E9
E9
E9

..

C
C
C
C

A8
A8

A8

6. Phoneme, Duration, Inflection, and Rate Adjustment
DP IS RE TA FF
Pho.D T In-S ARE FF
PA .0 5 08·0 C A 8 E9
00 58 A8 5C E9
PA .0 5 08·0 C A 8 E9
00 58 A8 5C E9
HF .1 5 OA·O C 7 8 E9
6C 50 78 5C E9
48 40 08 5C E9
EHI .1 5 08·0 C 0 8 E9
UH3.2 5 09·0 C C 8 E9
98 48 C8 5C E9
LF .0 5 08·0 C C 8 E9
22 40 C8 5C E9
UH3.2 5 05·0 C 9 8 E9
98 28 98 5C E9
.2 5 05·0 C 9 8 E9
91 28 98 5C E9
.0 5 06·0 C A 8 E9
12 30 A8 5C E9
.2 5 07·0 C C 8 E9
96 38 C8 5C E9
U
06 50 78 5C E9
U
.3 5 OA·O C 7 8 E9
PA .0 5 08·0 C A 8 E9
00 58 A8 5C E9
PA .0 5 OA·O C A 8 E9
00 50 A8 5C E9

a
au

7. Phoneme, Duration, Inflection, Rate, and
Adjustment
DP
Pho.D T In-S A R E FF
PA .0 5 08·0 C A 8 E9
00
PA .0 5 08·0 C A 8 E9
00
EH .0 5 07·0 0 0 8 E9
OA
HF .1 5 OA·O 4 7 8 E9
6C
48
EH1.l 5 08·0 C 0 8 E9
98
UH3.2 5 09·0 A C 8 E9
22
LF .0 5 08·0 A C 8 E9
UH3.2 5 05·0 C 9 8 E9
98
91
.2 5 05·0 C 9 8 E9
12
.0 5 06·0 C A 8 E9
96
U
.2 5 07·0 A C 8 E9
06
U
.3 5 OA·O 0 7 8 E9
00
PA .0 5 08·0 C A 8 E9
00
PA .0 5 OA·O C A 8 E9

a
au

Amplitude
IS RE TA
58 A8 5C
58 A8 5C
38 08 50
50 78 54
40 08 5C
48 C8 5A
40 C8 5A
28 98 5C
28 98 5C
30 A8 5C
38 C8 5A
50 78 50
58 A8 5C
50 A8 5C

FF
E9
E9
E9
E9
E9
E9
E9
E9
E9
E9
E9
E9
E9
E9

8. Further Adjustment (depending on personal preference)
Pho.D T In-S ARE FF
DP IS RE TA FF
PA .0 5 00·0 C A 8 E9
00 68 A8 5C E9
PA .0 5 00·0 C A 8 E9
00 68 A8 5C E9
EH .0 5 00·0 0 0 8 E9
OA 68 08 50 E9
HF .1 5 07·0 2 8 8 E9
6C 38 88 52 E9
EH1.l 5 09·2 C 0 8 E9
48 4A 08 5C E9
UH3.2 5 09·4 A C 8 E9
98 4C C8 5A E9
LF .0 5 09·0 A C 8 E9
22 48 C8 5A E9
UH3.2 5 07·7 C 9 8 E9
98 3F 98 5C E9
.2 5 06·4 C 9 8 E9
91 34 98 5C E9
.1 5 05·2 C A 8 E9
52 2A A8 5C E9
U
.2 5 06·3 3 5 8 E9
96 33 58 53 E9
U
.3 5 07·4 0 C 8 E9
06 3C C8 50 E9
PA .0 5 05·4 C C 8 E9
00 2C C8 5C E9
PA .0 5 01·4 C C 8 E9
00 DC C8 5C E9

a
au

1-98
-~~-

A8 5C E9

A
A
A
A

OA·O
OA·O
OA·O
OA·O

----"-._----------"-

1-99

SSI80C50
CMOS DigitallC
T-1 TransmUter

INTEGRATION

Data Sheet
DESCRIPTION

FEATURES

The SSI 80C50 is a CMOS digital IC that provides all
the formatting to T-1, 02 or T-1, 03 specifications. The
IC is functionally identical and pin compatible with the
Rockwell R8050, but offers reduced power consumption
and provides greater output current drive (fully TTL).
The data rate is 1.544 MHz.

• Second source, Rockwell R8050

The IC performs 8-bit parallel to serial conversion channel data is received and then serially transmitted
in two formats: binary and as a pair of unipolar outputs. Inputs control the formatting features available
- alarm reporting, highway signalling, zero data suppression, and framing. Several timing signal outputs
are provided to indicate channel, frame, and multiframe boundaries.

• TTL compatible
• CMOS low power dissipation
• Single 5V supply
• Provides formatting, timing and control for T-1, D2 or
T1, D3
• Provides timing signals to synchronize channel and
framing data

SSI,80C50 Block Diagram
SYNCIN

TEST

SYNOUT
CLOCK

, - - - - - - t - - - t U FRSYNC

CHCLKF()~--,--~~

r---~~--l--+--~SSTB

BIT 1

INH

B70PTN

81T3

TEST

CHCLKF

FRSYNC

PARALLEL TO SERIAL
CONVERTER

8-81T

81T4

eGIS

81T2

55TB

BIT5

UNPLRA

Bin

UNPLRB

BIT6

GNO

BIT7

BINOUT

VOO

SYNOUT

CLOCK

LOOP

ALARM

ACH
HWY SIGNALING

BCH

or--l.!~IL"U--rL----_.J

ALARM

df----------l--:;Z:ER:O~C;::;H:;:A:;:N:N:EL;-I

eGIS

Ojr--______- j_ _:.BI~T.:::ST::.U::.F.:..F:::IN::G_....J

5-81T

BIT8

BCH

ACH

ALARM REPORTING

INH

B7DPTN

SYNCIN

Pin Out
(Top View)

1----10 BINOUT

df----------I---F::R:-:A::M:E:B:IT~-l
Ojr--______--;___I::.:N.:::SE:R~T:.::IO::.:N~_.J

UNPLRA
UNPLRB

Voo GND

LOOP

1-100

CAUTION: Use handling procedures necessary
for a static sensitive component

551 Boeso

T-1 Transmitter
Pin Description
'Pin No.

Description

Name

1

B70PTN

Provides bit 7 as an alternate bit position for "1" stuffing

2

TEST

Used only for device testing, otherwise this pin should be grounded or open (on chip
pulldown resistor to ground). In test mode (TEST = 1) the bit/channel counters count 13, not
193 bits per frame - shortening test throughout time.

3

FRSYNC

Frame sync allows external synchronization of the transmitter's frame counter. When
FRSYNC becomes "1", the frame counter is set to frame 1. If FRSYNC is held high and does
not return to "0" before the rising edge of CLOCK, BINOUT will "1" and UNPLRA & UNPLRB
will toggle each GLOCK cycle.

4

S·BIT

In conjunction with CCIS, provides an alternate way to control the multiframe signalling bit (FS)
transmission. The S·BIT input is transmitted at the multiframe signalling bit (FS) if GCIS is "1 ".

5

CCIS

Common Channel Interoffice Signalling strap. Provides optional control for replacing the
automatic FS bit pattern with a 4·kilobit common channe.1 signalling path. When CCIS is high,
the S·BIT input replaces the FS pattern and the insertion of ACH and BCH is suspended. The
CCIS input may also be used to provide the alternate method of alarm reporting.

6

SSTB

4kHz multiframe strobe. SSTB is the least significant bit of the frame counter. Unless it is
directly set by FRSYNC, SSTB will be "1" as each FT bit is serially transmitted, and will be
"0" as each multiframe alignment signal FS is transmited.

7
8

UNPLRA
UNPLRB

Serial data unipolar outputs. Two paired unipolar outputs are
provided for the purpose of creating a single serial data transmission in bipolar format.

9

GROUND

Ground

10

BINOUT

Serial data output, binary formatted.

11

SYNOUT

Channel sync output. Provides a means to synchronize to the internal bit/channel (mod 193)
counters. SYNOUT is high one bit time, beginning just prior to the first data bit of a frame be·
ing serially transmitted. SYNOUT is the only output determined by the falling edge of CLOCK.

12

LOOP

Loop strap. Intended Used for user testing, otherwise this pin should be grounded or open
(on chip pulldown resistor to ground). When enabled to "1 ", LOOP forces the unipolar outputs
to transmit, alternating ones and zeros, regardless of input conditions, while BINOUT still
provides normal data outputs.

13

SYNCIN

SYNCIN allows external sychronization of the bit/channel counters (modulo 193). When SYN·
CIN becomes "1", the counters are set to the state corresponding to the output of the fram·
ing (FT or FS) bit. The first bit of channel one will be output on BINOUT (and UNPLRA or
UNPLRB) as a result of the first rising edge of CLOCK following the returr. of SYNCIN to "0".

14

BCH

"B" channel highway signalling allows the user to transmit one bit of signalling per channel
data sample in frame 12 only.

15

ACH

"A" channel highway signalling allows the user to transmit one bit of signalling per channel
data sample in frame 6 only.

16
20·25
27

BITS
1·8

Bit 1, the sign bit, will be serially transimitted first, followed by bits 2 through 8. The falling
edge of GHCLKF indicates input channel data has been clocked into the input register
and always occurs during the final bit (bit 8) of each sample.

17

ALARM

Used for reporting alarm conditions. If the ALARM signal is "1 ", bit 2 of every channel is
transmitted as "0".

18

CLOCK

1.544MHz clock.

,

19

VDD

Power.

26

CHCLKF

Channel clock false. The falling edge of CHCLKF, occurring as bit 8 of any channel is being
serially transmitted, indicates input data has been clocked into the input register. With the
exception of an extra bit period extending the low level duration at frame bit time, CHCLKF is
a divide·by·eight of CLOCK.

28

INH

Inhibit zero channel monitor.
1-101

Counters Channel data (BIT1-BIT8) is parallel loaded into
an input register and is then serially transmitted out
at BINOUT at the clock rate of 1.544 MHz. Bit1 is the
sign bit, bit 2 the MSB and bit 8 the LSB. When the last
bit (bit 8) is being transmitted, the next channel is
loaded into the register, latched by CHCLKF. Three
counters control the transmission of data. The bit
counter (modulo 8) decodes which bit is being
transmitted, generates CHCLKF, and increments the
channel counter at the end of each channel. The
channel counter (modulo 24) outputs a pulse for frame
synchronization which is one clock period wide
(SYNOUT), and increments the frame counter. The frame
counter (modulo 12) signals odd or even frames (SST B).
External synchronization is available with pins SYNCIN,
which initializes the bit and channel counters, and
FRSYNC which initializes the frame counter.

will toggle UNPLRA to "0" and UNPLRB to "1".
Whenever BINOUT is "0", both unipolar outputs are
forced to "0".
Alarm reporting and Signalling The device provides control for alarm reporting and
highway signalling with inputs ALARM, ACH and BCH
- all three are latched in by CHCLKF. In remote alarm
signalling bit2 of every channel is transmitted as "0".
Alternate remote alarm signalling may be used with
signals CCIS and S-BIT. In highway signalling ACH
replaces bit 8 of every channel in frame 6 only; likewise
BCH replaces bit 8 in frame 12.
Bit Stuffing The device provides for automatic bit stuffing for all zero
channel samples. Input INH inhibits the zero channel
monitor (zcm) while input B70PTN controls whether
bit 7 or bit 8 is stuffed. If INH is high, bits 7 and
8 are transmitted as normal, i.e., bits 7 and 8 are
transmitted as received unless the frame is a signalling
frame (6 or 12) - in which case the highway signalls
replace bit 8 as previously described. If INH is low, the
zcm is enabled and the following applies. For signalling
frames, if the first seven channel bits and the signalling
highway are all "0", bit 7 will be forced to "1". For the
other frames, if all the channel bits are "0", then bit 7
will be "1" if B70PTN is "1", otherwise bit 8 will be
forced to "1" if B70PTN is "0".

Transmit Ouputs The device provides two types of transmit formats a
binary ouput (BINOUT) and a pair of unipolar outputs
(UNPLRA and UNPLRB). BINOUT is the binary formatted
serial conversion of the parallel input channel data. The
unipolar outputs toggle for each "1" to be serially
transmitted, and are complements of each other. For
example, if the current BINOUT is "1", UNPLRA is "1"
and UNPLRB is "0", the next output of "1" on BINOUT

CONTROLS
:r

MODE

;;

1) Normal parallel to serial transmission

z

~

en

IL a: u
0
~ :l

.

FRAME
#

HIGHWAY
SIGNALING
A B

t 6, 12

B
B
B

8 1 8 2 8 3 8 4 8 5 8 6 8 7 Sa
B I B z 8 3 8 4 8 5 B6 B7 8 8
81 8 2 8 3 84 85 8e 8 7 88

8 1 B2 8 3 8 4 8 5 8 6 8 7 8 8

A
A
A

B
B
B

8, 8 2 8 3 8 4 8 5 B6 8 7 8 6

6
12

8, 8 2 8 3 8 4 8 5 Be 8 7 8 8
8 1 8 2 8 3 8 4 8 5 Be 8 7 8 8

8 1 0 8 3 8 4 8 5 6 6 8 7 B8
B,O 8 3 8 4 8 5 8 6 B7 A
8 1 0 8 3 8 4 8 5 B6 8 7 B

a) Alternate signalling
4) Zero Data
- ignore A & B
Suppression
b) bit 7 option

ON

1·12

A

B

8 1 8 2 8 3 8 4 8 5 B6 8] 8 8

8 1 8 2 8 3 8 4 8 5 8 6 8 7 B8

ON

",2

A

B

0 000

o

c) stuff bit 8
stuff bit 7
stuff bit 7

0

t 6,12

ON
ON
ON

ignore A & B

3) Alternate signalling -

ON

SERIAL BINOUT
CHANNEL BIT POSITION
1 2 3 4 5 6 7 8

A
A
A

6
12
2) Alarm report (bit 2 of All channels)

INPUT 8 BITS
CHANNEL OATA
1 2 3 4 5 6 7 8

0

0

o

0

0

0

o

0

0

0 0

o

0

0

0

0

0

1 0

0 0
0 0
0 0

0
0
0

0
0
0

0
0
0

0
0
0

0 1
1 0
1 0

t6,12

A

B

o

ON
ON
ON

t 6,12

A
0
A

B
B
0

0 0 0
0
0 0
0 0 0 0
0 0 B,
0
0 0 0 0 0 B.

6
12

FramingThe device automatically inserts frame information at
the beginning of each frame. An FT bit is inserted before
the sign bit (bit1) of channel 1 in odd frames, stretching

o

0

ON ON

0

0

o

o

o

o

ACH Replaces BtT 8 IwFrame No 6

FRAME NUMBER

FT

0

1

the channel to 9 bits, an FS bit likewise is inserted in
even frames. Alternatively, the FS bit insertion can be
externally controlled by pins CCIS and S-BIT.

r1

FS

B, 8 2 8 3 8 4 8 5 So B7 A
8 1 B2 8 3 8 4 8 5 B6 8 7 B

,

0/

BCH Replaces BIT 8 In Frame No 127

l--'--'-+--'--"--'+-'--'-'--I,....-'....J...."":"'+-'-'-"+-'--'-"-j--'--'-..=......J
1

SST8

SYNOUT

-'-_.l..----'_-'-_.J.........---'_-'-_.J.........---'._-'-_.J.........---'._-'-_"--....J...

FRSYNC

7-~--:----:--:----:---:----,:---.,...-~---,:---.,...-.l..---:--:­

SYNCIN

...J....---'L---L_...L.---''---'''_...L..._L-....I.._..I....-....:L-....I.._.I....--l.c..--.1

1-102

FT
FRAME
NUMBER

1

0

S-8IT

l

1-8
1-8

0

4

5

SIGNALLING
CHANNEL

1-8

1

2

3

BIT NUMBERS IN CHANNELS

FS

MUL TIFRAME ALIGNMENT
FRAME
SiGNAL
CHARACTER BITS SIGNALLING BIT
ALIGNMENT
SIGNAL
CCIS = 0
CCIS = 1

0

S-8IT

1

S-8IT

1-8

1

1-8

6

1-7

8

A

8

8

~-

7

1-8

0

8
9

1

1-8
1-8

10
11

S-8IT

1
1

S-8IT

0

S-8IT

1-8

0

1-8

12

SUPER FRAME

1-7

1.5ms

--

-I

•••••••

SIGN
BIT

T-1 formatting: 8 bits -to a channel

24 channels to a frame
12 frames to a super-frame
193 bits to a frame

FT insertion at beginning of odd frames
FS insertion at beginning of even frames

Absolute Maximum Ratings
Positive5.0VSupplyVoltage, VDD .............. _.. 7V
Storage Temperature " _............... - 65 to 150·C
Lead Temperature (Soldering 10sec.) ............ 260·C

Input Pins ... __ ........... _..... - 0.3Vto VDD + 0.3V
Output Pins __ .... ____ .. -0.3VloVDD +0.3Vor15mA
Inputs and outputs are prot~cted against static discharge with industry
standard protection devices.

1-103

Recommended Operating Conditions
Symbol

VDD Supply Current

-

CLOCK Frequency

VDD

-

Unit

Test Conditions

Min

Max

Clock active, Ouputs open, Inputs to rail

-

10

mA
kHz

Parameter

IDD

10

1600

VDD

-

4.76

5.25

V

Temperature

-

0

70

·C

-

2.0

-

V

-

0.8

V

DC Requirements
VIH

Input Hi Voltage

VIL

Input Lo Voltage

VOH

Output Hi Voltage

I source = -1.0mA

2.4

-

V

VOL

Output Lo Voltage

I sync = 2.0mA

-

0.4

V

Timing Characteristics
t1s

Latched Setup Time

(.1)

20

-

ns

t1 h

Latched Hold Time

(1)

250

-

ns

t2s

Setup Time

(2)

350

-

ns

t2h

Hold Time

(2)

20

-

ns

t3s

Setup Time

(3)

200

-

ns

t3h

Hold Time

(3)

20

-

ns

t3pw

Pulse Width

(3)

100

-

ns

t4s

FRSYNC Setup Time

NRTZ

525

FRSYNC Hold Time

NRTZ

20

-

ns

t4h
C

Capacitive Load

Outputs

-

25

pF

tr, If

Output Rise, Fall Time

50% in, to 90% or 10% out

-

100

ns

td1

Output Prop Delay

(4) From Rising Edge of CLOCK

-

350

ns

td2

SYNOUT Prop Delay

From Falling Edge of CLOCK

-

350

ns

(1) Bin, BIT2, BIT3, BIT4, BITS, BIT6, BIT?, BITS, ACH, BCH, ALARM
(2) S·BIT, CCIS, LOOP, INH, B70PTN

(3) SYNCIN, FRSYNC
(4)BINOUT, UNPLRA, UNPLRB, CHCLKF, SSTB

CLOCK

1
(SertaIDala)

1

6

1

1

7

8

1

0

I

FT

I

0

1

1

2

1

3

1

4

1

5

1

6

I

I

7

8

I

1

2

1

1

4

1

'---___---'r-

101

CHCLKF

SYNOUT

I

I
I

--------'rTlwl- - - - - - - - - - - - - - - - - - - - I

I

SYNC'N

----------+'11I

SYNC,N

-------t'ir®l4:--------------------I

II
I

t_'"_~-+'IF-l'~='"'t3ec=.S-------------------

FRSYNC _ _ _ _ _ _

BINQUT

UNPLRA

UNPLRB - - - - - - - '

....;I@

lOOP _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Notes:

CD

Extended count for frame bit insertion.

@

Timing for external synchronization of SYNCIN and FRSYNC

@ Loop mode

1-104

ns

l_4_3_5l_M_Y_foR_O'~_: T_~ t_in,_c A~_7 '~_) 7_31_-7_1 0_,T_W ':_9 1_0-_5 95_- 28_0 9

____________________

CLOCK
BINOUT
BIT#

__

_____________________

,

/

,

Timing For: BIT1·BITB. ACH. BCH. ALARM. INH. B70PTN

/

I

I

I

---t

t1S--I

\

I

For 1

/

k-I~
I-tH

----X I

I

t 2$

/

~

I

I
I

BIT1·BIT8
ACH. BCH
ALARM

\

I

I

CHCLKF

INH
B70PTN

/

I

X----

I

--I

-----J I-- t2H

-*---

' _-

Timing For: Loop. Test. SBIT. CCIS

\

CLOCK /

/

.....

I

LOOP TEST
CCIS S BIT

Timing For. Altemate Remote Alarm Reporting
CLOCK
BINOUT
BIT #
S BIT

CCIS

/

\
CH 24

/
I

\
CH 24

I

\

/

I

FS

I

,

----X

\
CH1,

I

X----

/
Output Timing

SSi. SSi reserves the right to make changes in specifications at any time and
without notice.

No responsibility "is assumed by SSI for use of this product nor for any infringements of patents and trademarks or other rtghts of third parties resulting from
its USB. No license is granted under any patents, patent rights or trademarks of

1-105

JhJlrJkmr
INTEGRATION

SSI80C60
CMOS Digital IC

T-1 Receiver

Data Sheet
Remote alarm reporting is monitored and an alarm is
indicated at the B2ALRM pin if 255 consecutive bit 2
zeros are received. The incoming data is monitored for
loss of carrier and an alarm is indicated at the CALRM
pin if 31 consecutive zero bits are received.

GENERAL DESCRIPTION
The SSI 80C60 is a CMOS digital IC that receives and
deserializes serial unipolar data in a T-1, 02 or T-1, 03
format The IC is functionally identical and pin
compatible with the R8060 but offers reduced power
consumption and provides greater output current drive
(fully TTL).

FEATURES
• Second source, Rockwell RB060
• TTL compatible
• CMOS low power dissipation
• Single 5V supply
• Locks onto and deserializes incoming T-1, D2 and
T-1, D3 datain 5ms
• Generates timing signals to synchronize channel and
frame information
• Monitors and detects
- FS bit
- Frame sync
- Carrier
- Remote alarm reporting

The IC receives 1.544 MBit/s unipolar data and an
extracted clock. The data pattern is in 193 bit frames,
each frame consisting of a frame bit (FT) or a signaling bit (FS) followed by 192 bits of data representing
24 channels of 8 bit words. F frames and S frames
alternate. The receiver synchronizes by locking
to (FT) which occurs every 386 bits and which
continually alters between 1 and 0, and deserializes the
data stream into 24 eight bit wide channels which are
clocked out of the 8 data bit pins at a 192,000 channells rate with each channel repeated at a 8000 frame/s
rate. Signaling bits (FS), which are positioned 193 bits
behind the frame bit, are outputed at the SBIT pin.

Block Diagram

Vao

--..t.
COB7

GND~

C086
PARALLEL
OUTPUT DATA

CDINH--------i

REGISTER
-CDB3

CDB2
COBl

SYNCEN

-------+-..r----:-'-----,

TCLK

SIGFRB

Voo

SBCLK

TDATA
TESTO

COBB

B2ALRM

TESTI

CDBl

FRALRM

COB6

FRALRM

TDATA

TCLK

CHCLK
386 BIT FRAME
POSITION COUNTER

CHCLK

CDB5

MAXCNTB

CDB4

CHSVNCB

CDB3

SYNCEN

CDB2

CHSYNCB

MAXCNT8

COBl

SBCLK

GNO

CDINH

SBALRM

TESTO

S81T

S81T
TESTI~

SIGFRB

Pin Out
(Top View)

CALRM

CAUTION: Use handling procedures necessary
for a static sensitive component

1-106

SSI80C60
T-1 Receiver

Pin

Name

1

TCLK

Description

Data clock. Nominal clock frequency is 1.544 MHz. Data bits are clocked into the
chip on the falling edge of the clock.

2

VDD

Power

3

WIHBT

Write inhibit clock. Strobes high once every channel for two TCLK periods and is
used to load the 8-bit parallel channel output data into external circuitry.

4

B2ALRM

Bit 2 alarm signal, active high. Goes high indicating a remote alarm when 255 consecutive O's are received in the bit 2 position. Resets low after bit 2 becomes 1.

5

TESTI

Test input, when low puts the circuit in its test mode. Must be high or left open
during normal operation.

6

FRALRM

Frame alarm, active high. Goes high when frame sync is lost.

7

CHCLK

Output data channel clock, going high signals new parallel data output.

8

MAXCNTB

Strobes low once every two frames for one TCLK period during the expected input
of FT.

9

CHSYNCB

Channel sync clock, strobes low once every frame for six TCLK periods during
channel 1.

10

SYNCEN

Frame synchronization enable. When low, disables the automatic resync search initiated by a frame alarm condition.

11

MRB

Master Reset, active low resets the circuit.

12

GND

Ground

13

CALRM

Carrier alarm signal, active high. Goes high if 31 consecutive zeros are received in
the TDATA input. Resets low when TDATA becomes 1.

14

SBALRM

FS alarm signal, active high. Signals an FS alarm when the previous FS bits have
been a 0 followed by 1111. SBALRM is reset low when the FS bit pattern 10001 occurs. The SBALRM transition occurs during channel 1 of FS frame.

15

TESTa

Test mode output.

16

SBIT

Signaling bit, outputs the FS received 2 frames before the current FS.

17

CDINH

Channel data inhibit, when high forces CDB1 through CDB7 pins high. CDB8 is not
affected.

18-25

CDB1-8

Bit 1, the sign bit, will be serially received first, followed by bits 2 (MSB) through bit
8 (LSB). The rising edge of CHCLK indicates output channel data has been clocked
out and occurs as the final bit (bit 8) is received.

26

TDATA

Serial data input.

27

SBCLK

4 kHz signal that is low during even frames and high during odd frames.

28

SIGFRB

Signal frame clock, strobes low during frame 6 and 12.

Timing - Timing signals for channel and frame
synchronization.
WIHBT
CHCLK
MAXCNTB
SIGFRB
CHSYNCB
SBCLK
SBIT

1-107

Alarms - Alarm conditions reported.
SBALRM
B2ALRM
CALRM
FRALRM

SUPER FRAME

·1

1.5ms

•••••••

T·1 formatting:
8 bits to a channel
24 channels to a frame
12 frames to a super-frame
193 bits to a frame
FT insertion at beginning of odd frames
FS insertion at beginning of even frames

SIGN

BIT

FRAME ALARM
FRALRM goes high indicating an out-of-frame condition when:
(1) The frame sinchronization algorithm is in progress.
(2) MRB is low.
(3) The current FT is in error and a previous FT error
occurred in the past four frames.
(4) CALRM is low.

FRALRM returns low when:
(1) Frame synchronization is complete.
(2) CALRM is high.
During frame sync output signals CHCLK, CHSYNC,
and WIHBT will continue normally for 2 frame periods
- afterwards they will be high. For most data patterns
frame sync requires less than 5 milliseconds to acquire
frame lock.
CLOCK

OUT

SHIFT REG

(3868IT5)

TDATA

MEMORY SHIFT REG
1386 BITS)

OUT

CLOCK

MRBU
FRALRM

..-J

CHSYNCB~~_.~·

l---------

2 FRAME

LJ

PERIOD~

FRAME SYNCHRONIZATION

SIGNALING SYNCHRONIZATION

BIT (F-SIT) PATTERN

BIT (S-SIT) PATTERN

(101010)

(001110)

FIRST FRAME

BIT (F/S BIT)

i

-''-,.....:~,.....:=--r'~r':.....,r~.....!~-:~-:,~,-;-;,-;;,--:--,
10

12

CHSYNCB

SBCLK

SIGFRB

rl---------'L..Jr--------..,~

MAXCNTB

1-108

-.._ - - S BIT FRAME
CH 24

I

FBIT FRAME - - - _
..CH 1

r,_ _ _

A

---'A~ _

_ _"""'

TDATA INPUT 17 IS 11 12131 41516 I 7 la I F 11 12 I 31 41 51 61 7 I al1 1 21 3 1
CLOCKED DATA I 71a 11 12 I 31 4151 6171 al F 11 I 2 13 I 4 I 516 I 7 I SI1 12 131
TCLK

WIHBT
CHSYNCB
SBCLK
SBIT

NO CHANGE

SIGFRB

u

MAXCNTB

CHANNEL DATA
PARALLEL OUTPUT

~__C_H_2_3_0_UT_P_U_T_-J)(~___C_H_2_4_0_U_TP_U_T___~

..

F BIT FRAME

I

S BIT FRAME

CH 24
,

A

.,

CH 1
\

A'-_ _ _- - - .

TDATA INPUT I 71 al1 I 213 14 1516 I 7 IS IS 11 I 21 3 14 151 6 I 7 I a 11 I 21 3 I
CLOCKED DATA 17 I al1 I 2 I 3141 51 61 71 a l S 11 I 21 31 41 51 61 7 I al1 I 21 3 I
TCLK
CHCLK

--.J

WIHBT
CHSYNCB
SBCLK
SBIT

________________

---'x~

__________________

SIGFRB

MAXCNTB
CHANNEL DATA
PARALLEL OUTPUT

-----P.
----v _ CH
_
23 _
OUTPUT_---'XI -_ _
CH 24_
OUTPUT
_ _v--;;;;~

1-109

Absolute Maximum Ratings
Positive 5.0V Supply Voltage, VCC ................. 7V
Storage Temperature .................. - 65 to 150°C
Lead Temperature (Soldering 10 sec.) ........... 260 °C
Input Pins ..................... - 0.3V to VDD + 0.3V
Output Pins ............ - 0.3V to VDD + 0.3V or 15 mA
Inputs and outputs are protected against static discharge with industry
standard protection devices.

Recommended Operating Conditions
Symbol
100

Parameter

Test Conditions

VDD Supply Current

Clock active, Outputs open, Inputs
to rail

Min

-

Max

Unit

5

mA
kHz

-

CLOCK Frequency

-

10

1600

VDD

VDD

-

4.5

5.5

V

-

Ambient Temperature

-

0

70

°C

Max

Unit

DC Requirements
Symbol

----

Parameter

Test Conditions

Min

VIH

Input Hi Voltage

-

2.0

-

VIL

Input Lo Voltage

-

-

0.8

V

VOH

Output Hi Voltage

I source

2.4

-

V

VOL

Output Lo Voltage

I sink = 2.0mA

-

0.4

V

Max

Unit

= -1.0mA

V

Timing Requirements
Symbol

Parameter

Test Conditions

Min

t1 s

TDATA setup time

from CLOCK edge falling

100

-

ns

t1 h

TDATA hold time

from CLOCK edge falling

100

-

ns

t2h

Setup time

(1) from WIHBT edge rising

0

-

ns

t3h

CDB1·8 hold time

from CHCLK edge rising

0

200

ns

td1

Output delay

(2) from CLOCK edge rising

-

300

ns

-

Output delay

(3) from CLOCK edge rising

-

400

ns

-

CALRM delay

from CLOCK edge

-

300

ns

-

FRALRM delay

from CLOCK edge

-

600

ns

tr, tf

Output rise, fall time

90% to 10%

-

100

ns

-

SYNCEN low (inhibit sync)

before FRALRM edge rising

200

-

ns

-

SYNCEN high (initiate sync)

before MRB edge rising

200

-

ns

-

CDB1-7 valid/high

after CDINH edge falling/rising

-

150

ns

-

FRALRM high

after MRB falling edge

-

250

ns

(1) SIGFRM, FRALRM
(2) CHCLK. CHSYNC, WIHBT, MAXCNTB. SBCLK
(3) SIGFRM, SBALRM. B2ALRM. SBIT. CDB1·8

1-110

____________________

Jifkon
Jl rJkmJ"
.14.3.5.1.M.Yf.o.rd.R.o.ad.,.Tu.s.tin.,_CA~.71.4.).7.31.-7.1 .0.,T.W.X.9.1.0-.5.95.-.28.0.9

_____________________

OUTPUT TIMING
INPUT TIMING

T~A_ -x~---,x-

--

C:"'OCK~
I

V I

CHClK

\'----

TCLK

I

1- 'D'-~+I______
~~

1

-----l '3H

L-

_ _

COB

'·8

------xr:--:- I I

--Ir

trll

MRB

SBALRM CALRM
FRALRM CHCLK
WIHBT CHSYNCB

B2AlRM

255th CONSECUTIVE BIT 2 0

CLOCKED
TDATA

0'
1,12131415161,181,1,131415161,181'1

CLOCK

OHClK

'------'1

L

B2ALRM _ _ _ _ _ _ _ _ _ _ _- J

SBALRM

g;~~KED[

B [ 5 [, 12 [ 3 14 [5 [6 [ , [ 8 [, [ 2 [

CLOCK

SBALRM

CALRM
29

30

31

CLOCKED

I

DATA

n

CLOCK

CALRM

No responsibility is assumed by SSi for use of these products nor for any infringe-

use. No license is granted under any patents, patent rights or trademarks of SSi. SSi

ments of patents and trademarks or other rights' of third parties resulting from its

reserves the right to make changes in specifications at any time and without notice.

1-111

55122100
CMOS 4x4 Crosspoint
Switch with Control
Memory

INTEGRATION

Data Sheet
GENERAL DESCRIPTION

FEATURES

The SSI 22100 combines a 4 x 4 array of crosspoints
(transmission gates) with a 4-line-to-16 decoder and 16
latch circuits. Anyone of the sixteen transmission gates
(crosspoints) can be selected by applying the appropriate
four line address. The selected transmission gate can be
turned ON or OFF by applying a logical ONE or ZERO
respectively to DATA IN and strobing the STROBE input
to a logical ONE. Any number of the transmission gates
can be ON simultaneously. When the device is "powered
up", the states of the 16 switches are indeterminate.
Therefore, all switches must be turned OFF by setting the
STROBE high and DATA IN low, then addressing all switches
in succession.

Low ON resistance-7Sf! typo at VDD = 12V
•

"Built-In" control latches
Large analog signal capability-±VDD/2

•

10-MHz switch bandwidth
Matched switch characteristics-A RON
at VDD = 12V

•

= 1Sf! typo

High Iinearity-O.SolO distortion (typ.) at f
VIN = SVp _p , VDD = 10V, and RL = 1kf!

= 1kHz,

Standard CMOS noise immunity
100% tested for maximum quiescent current at 20V

The SSI 22100 is supplied in 16-lead hermetic dual-in-line
ceramic packages and 16-lead dual-in-line plastic
packages.

Second source for RCA CD22100

SSI22100 Block Diagram

STROBE

DATA
IN
15
Vl

PIN CONFIGURATION
X2

'4
V2

,.

16

VDD

DATA IN

15

Vl

C

14

V2

D

13

X4

B

12

X3

A

11

V4

STROBE

10

V3

..J

0

10

II:
I-

V3

z

0

u
~

Xl

Vss
11
V4

Pin Out
(Top View)

CAUTION: Use handling procedures necessary
for a static sensitive component

1-112

55122100
CMOS 4x4 Crosspoint Switch with Control Memory
PIN DESCRIPTION
Pin No.
9,1,2,3

I X1 to X4
I

2

Maximum Ratings, Absolute-Maximum Values: (cont.)

Symbol

DATA IN

Description

Data input. The selected
crosspoints can be turned on
oroff by applying a logical
ON E or ZERO, respectively, to
the data input and a logical
ON E to the STROBE.

6,5,3,4

A,B,C,D

Address inputs

7

STROBE

STROBE input

8

Vss

Ground

Y1 to Y4

Transmission lines in
Y direction

VDD

Positive Power Supply

15,14,10,11
16

Operating·temperature range (TA):
Package type D .................... -55to + 125°C
Package type P ..................... -40to + 85°C
Storage temperature range (T stg) ....... -65 to + 150°C
Lead temperature (during soldering):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case
for 10 s max ............................... + 265°C

Transmission lines in X
direction

* Maximum current through transmission gates (switches) ; ; : : 25 rnA.

Recommended Operating Conditions
For maximum reliability, nominal operating conditions
should be selected so that operation is always within the
following ranges:
Characteristic

I

MIN.

MAX.

UNITS

3

18

V

Supply·Voltage Range (For
TA = Full Package·
Temperature Range)

Maximum Ratings, Absolute·Maximum Values:
DC supply-voltage range, (VDD)
(Voltages referenced to VSS Terminal ... -0.5 to + 20 V
Input voltage range, all inputs ....... -0.5 to VDD + 0.5 V
DC input current, anyone input- .. ' ............ ± 10 mA
Power dissipation per package (PD):
For TA =-40 to + 60°C (package type P) ...... 500 mW
For TA = + 60 to + 85°C (package type P)
Derate Linearly at 12 mW/oC t0200mW
For TA = -55 to + 100°C (package types D) ... 500mW
For TA = + 100 to + 125°C (package types D)
Derate Linearly at 12 mWO/Cto 200 mW
Device dissipation per tranSmission gate
For TA = full package-temperature range
(all package types) .......................... 100mW

TRUTH TABLE
Address

B
0
0

A

0

1

1
1

0

1
0

0
0

1

1
1

0

1

Select
C

D

0
0
0
0

0
0
0
0
0
0
0
0

1
1
1
1

Address
A

X1Y1
X2Y1
X3Y1
X4Y1
X1Y2
X2Y2
X3Y2
X4Y2

0

1
0

1
0

1
0

1

Select

B
0
0

1
1

C

D

0
0
0
0

1
1
1
1
1
1
1
1

1
1
1
1

0
0

1
1

X1Y3
X2Y3
X3Y3
X4Y3
X1Y4
X2Y4
X3Y4
X4Y4

Dynamic Electrical Characteristics at TA = 25°C
Characteristic
'is
kHz

I

Conditions
RL
kf!

I

Limits

ViS"i" VDD
(V)

(V)

Min.

5
10
15

5
10
15

-

I

Typ.

I

Units
Max.

Crosspoints
Propagation Delay Time, (Switch ON)
Signal Input to Output, tPH L" tpLH

-

10

60
30
20

ns

-

30
15
10

-

40

-

MHz

CL=50 pF; tr, tf=20 ns
Frequency Response, (Any Switch ON)

1

1

5

10

Sine wave input,
VOS
20 log-- = -3 dB
Vis
Sine Wave Response, (Distortion)

1

Feedthrough (All Switches OFF)

1.6

1

5

10

-

0.5

-

%

5

10

-

-80

-

dB

1,
Sine wave input

• Peak-ta-peak voltage symmetrical about VDO
-2~

1-113

Dynamic Electrical Characteristics at TA = 25°C (cont.)
Conditions
RL , Vis· , VDD

Characteristic
tis

kHz

,

kfl

(V)

1

10

Limits
Units
Min.'

Typ. , Max.

-

1.5
0.1

5-15
5-15
-

-

18
30
0.4

-

5
10
15

-

300
125
80

600
250
160

5
10
15

-

-

110
40
25

220
80
50

5
10
15

-

350
135
90

700
270
180

Propagation Delay Time:
Strobe to Output, tPHZ
(Switch Turn-OFF)

5
10
15

-

-

165
85
70

330
170
140

Data-In to Output, tPZL
(Turn-ON to Low Level)

5
10
15

-

210
110
100

420
220
200

Address to Output, tPHZ
(Turn-OFF)

5
10
15

435
210
160

870
420
320

95
25
15

190
50
30

ns

ns

(V)

Crosspoints (cont'd)
Frequency for Signal Crosstalk
Attenuation of 40 dB
Attenuation of 110 dB

-

10

Sine wave input

Capacitance,
Xn to Ground
Xn to Ground
Feedthrough

-

-

-

-

MHz
kHz

pF

Controls
Propagation Delay Time:
Strobe to Output, tpZH
(Switch Turn-ON to High Level)
Data-In to Output, tpZH
(Turn-On to High Level)

RL=1kfl
CL=50pF,
tr,tf = 20 ns

Address to Output, tpZH
(Turn-ON to High Level)

-

-

-

Minimum Setup Time,
Data-In to Strobe, Address, tsu

5
10
15

Minimum Hold Time,
Data-In to Strobe, Address, tH

5
10
15

-

180
110
35

360
220
70

5
10
15

0.6
1.6
2.5

1.2
3.2
5

-

5
10
15

-

300
120
90

600
240
180

Maximum Switching Frequency, fO
RL = 11dl CL =50pF
t r, tf=20 ns
Minimum Strobe Pulse Width, tw
Control Crosstalk,
Data-In, Address, or Strobe to Output
Input Capacitance, CIN

-

I

10

I

10

-

-

10

-

Any Control Input

-

-

1-114

ns

MH,z

ns

75

-

mV
(peak)

5

7.5

pF

Square wave input
tr, tf = 20 ns

*Peak-to-peak voltage symmetrical about VOO/2

ns

Static Electrical Characteristics
Characteristic

Limits at Indicated Temperature (OC)f

Conditions

I Max.
- 40 II Min. I+25
I + 85 I + 125
Typ. I Max. I Max.
Max.

Units

VIN
(V)

VOO
(V)

- 55
Max.

-

5
10
15
20

5
10
20
100

5
10
20
100

-

0.04
0.04
0.04
0.08

5
10
20
100

150
300
600
3000

150
300
600
3000

475
135
100
70

500
145
110
75

-

-

225
85
75
65

600
180
135
95

725
205
155
110

800
230
175
125

n

-

5
10
12
15

-

5
10
12
15

-

25
10

-

-

n

All switches
OFF

0,18

18

±100'

± 1000

nA

Input Low
Voltage
VIL Max.

OFF Switch
IL <0.2p.A

-

1.5
3
4

1.5
3
4

Input High
Voltage,
VIH Min.

ON switch
see RON
charac·
teristic

-

V

-

3.5
7
11

±0.1

±1

p.A

Crosspoints
Quiescent
Device Current,
IDD Max.

-

ON Resistance
RON Max.

AON Resistance
ARON
OFF Switch
Leakage
Current
IL Max.

-

-

Any Switch
VIS=
o to VDD
Between
any two
switches

-

-

-

-

-

-

-

-

8

-

5

± 100

-

±1

-

5
10
15

1.5
3
4

-

-

-

5
10
15

3.5
7
11

3.5
7
11

-

18

±0.1

Controls

-

Input
Current,
liN Max.

Any control

0,18

-

-

-

-

-

-

±10·5

I
I

-

p.A

I

*Oetermined by minimum feasible leakage measurements for automatic testing.
tValues at -55, + 25, + 125, apply to 0 package. Values at -40, + 25, +85, apply to P package.

VDD
VDD

VDD

VDD

~

16

o

vss
13

13

12

10

Quiescent corrent test circuit

10

Note:
Measure inputs
sequentially to
both VOO and VSS'
Connect all unused
inputs to either
VOOorVSS'

Input current test circuit.
Note: Close switch S
after applying VOO
Dynamic power dissipation test circuit.

1-115

Voo

ON

Vis

SW

= ANY CROSSPOINT

OFF switch input or output leakage
current test circuit.

STROBE

= OATA·IN = VDD

Propagation delay time test circuit and
waveforms (signal input to Signal output,
switch ON).

CONTROLS

rI
rL-J
L-J

-r-,

Voo
CONTROL

o

---.J

SW

Test circuit and waveforms for crosstalk
SW = ANY CROSSPOINT

(control input to signal output).

= ANY CROSSPOINT
Test circuit for crosstalk between switch

circuits in the same package.

DATA-IN

Von 50%

STROBE

Voo
DATA·IN

SW

= ANY CROSS POI NT
Propagation delay time test circuit and waveforms ( STROBE to signal output,
switch Turn-ON or Turn.QFF).

DATA-IN

VODJE:

OATAI~250%·tPZL
VOD Vos

o

=

SW
ANY CROSSPOINT
VDD
STROBE

=

Propagation delay time test circuit and waveforms (data-in to signal output,
switch Turn-ON to high or low level).

1-116

90%

JhJz
,CA~ _71_4_)_7_3-'"
1_-7_1 _0_,T_W_X_9_1_0-_5_95_-_28_0_9

_____________________
14_3_5_1M_Y_fo_r_d_Ro_a_d_,T_u_st_in__

_____________________

ADDRESS = 0

SW = ANY CROSSPOINT
STROBE = VDD

Propagation delay time test circuit and waveforms (address to signal
output, switch Turn·ON or Turn-OFF).

No responsibility is assumed by S5i for use of these products nor for any infringements of patents and trademarks or other rights-of third parties resulting from its

use. No license is granted under any patents, patent rights or trademarks of SSi. SSi
reserves the right to make changes in speCifications at any time and without notice.

1-117

551 22101/22102
CMOS4x4x2
Oosspoint Switches
with Control Memory

INTEGRATION

Data Sheet
GENERAL DESCRIPTION
The SSI 22101 and 22102 crosspoint switches consist of
4 x 4 x 2 arrays of crosspoints (transmission gates), 4-line
to 16-line decoders, and 16 latch circuits. Anyone of the
sixteen crosspoint pairs can be selected by applying the
appropriate four-line address, and any number of crosspOints can be ON siniultaneously. Corresponding crosspOints in each array are turned on and off simultaneously, also.
In the SS122101, the selected crosspoint pair can be
turned on or off by applying a logical ONE or ZERO,
respectively, to the DATA input, and applying a ONE to
the STROBE input. When the device is "powered up", the
states of the 16 switches are indeterminate. Therefore,
all switches must be turned off by putting the STROBE
high, DATA low, and then addressing all switches in
succession.
The selected pair of crosspoints in the SSI 22102 is turned on by applying a logical ONE to the Ka (set) input
while a logical ZERO is on the Kb input, and turned off
by applying a logical ONE to the Kb (reset) input while a
logical ZERO is on the Ka input. In this respect, the controllatches of the SSI22102 are similar to SET/RESET

flip-flops. They differ, however, in that the simultaneous
application of ONEs to the Ka and Kb inputs turns off
(resets) all crosspoints. All crosspoints in both devices
must be turned off as VDD is applied.
The SSI22101 and SSI22102 are supplied in 24-lead
hermetic dual-in-line ceramic packages and 24-lead dualin-line plastic packages.

FEATURES

•

Low ON resistance-7sn typo at VDD = 12V

•

Large analog signal capability-±VDD/2

•

10-MHz switch bandwidth

•

Matched switch characteristlcs- ~RON = an typo
at VDD
12V

•

High Iinearity-0.25% distortion (typ.) at f = 1kHz,
VIN
5V p _p , VDD- VSS
10V, and RI
lkn

"Built-In" latched inputs

=

=

=

=

Standard CMOS noise immunity
•

Second source for RCA CD22101 & CD22102

Block Diagram SSI 22101/22102

r+,-+--t+-t-+----+:;;;-' :] SIGNALS
Y3

OUT(IN)

VDO

r+,-h-++-+-+.,OO".
)(2'

r+,-h-++-+-+"7=-V4
ADDRESS

22

V,·

,.

Y2'

X4'

r+'-h-++-+-+.:,.:.)

SIGNALS
OUT(IN)

•

55) 22101

X,

X2'

X,

V,

V,'

21

Yl

20

Y2

Y2'

20

Y2

19

X4

X4'

19

X4

X3

X3'

"

X3

6

551

22102

'7

V4

V4'

"

V>

V>'

16

Y3

'5

X,

Xl'

15

X1

'4

OAl>

'3

STROBE

10

Vss

12

Y3'

Pin Out
(Top View)

CAUTION: Use handling procedures necessary
for 8 static sensitive component

1-118

A

22

V4'

Vss

r+,-+--t+'-+----+,C- V4'

Voo

23

Y3'

X,'

9

24

23

23

V4

55122101/22102
CMOS 4x4x2 Crosspoint Switches with Control Memory
PIN DESCRIPTION

23,1,
2,11

A-D

10,3,
7,6,

X1'-X4'

4,5,9,
8,

Y1'-Y4'

12
13

Vss

Recommended Operating Conditions
For maximum reliability, nominal operating conditions
should be selected so that operation is always within the
following ranges:

Description

Pin No. Symbol

Address line inputs
Input transmission lines to be paired
with Y1'-Y4'.
Output transmission lines to be
paired with X1'·X4'.

14

DATA
(22101
only)

Data input

14,13

Ka,Kb
(22102
only)

Switch control inputs. When Ka
1
and Kb
0, the selected switches
0 and Kb
are turned on. When Ka
1, the selected switches are turn1 and Kb
1, all
ed off. While Ka
the switches are turned off.

X1-X4

21,20,
16,17
24

Min.

Max.

Units

3

18

V

Ground

~TROBE Strope input. A logical "one" of
(220101 STROBE will turn on or off the
specified switches when DATA is
only)
ONE or ZERO respectively.

15,22,
18,19

Characteristic
Supply-Voltage Range (For
TA = Full PackageTemperature Range)

=

=

=

Control Truth Table for SSI22101

=

=

=

Function

Address

Switch On

ABC D
1 1 1 1

1

1

15 (X4Y4) &
15' (X4'Y4')

Switch Off

1 1 1 1

1

0

15 (X4Y4)&
15' (X4'Y4')

Select

No Change

XXX X

0

X

XXX X

1 = High Level; 0 = Low Level; X = Don't Care

Control Truth Table for SSI 22102

Input transmission lines to be paired
with Y1-Y4.

Function

Y1-Y4

Output transmission lines to be
paired with X1·X4.

VDD

Positive power supply.

Maximum Ratings, Absolute·Maximum Values:
DC supply-voltage range, (VDD)
(Voltages referrenced to VSS Terminal ... -0.5 to + 20"
Input voltage range, all inputs ........ -0.5to VDD + 0.5V
DC input current, anyone input' .............. ± 10 rnA
Power dissipation per package (PD):
ForTA = ·40 to + 60·C(packagetypeP) ...... 500 mW
.. Derate
For TA = + 60 to + 85·C (package type P)
Linearly at 12 mW/·Ct0200mW
For TA = -55 to + 100·C (package type D) ... 500 mW
For TA = 100 to 125°C (package type D) ...... Derate
Linearly at 12mW·/Cto 200 mW
Device dissipation for transmission gate
For TA = full package-temperature range
(all package types) .......................... 100mW
Operating-temperature range (TA):
Package type D
................. -55 to + 125 ·C
Package type P .... _ ................. -40 to + 85 ·C
Storage temperature r?nge (Tstg) ........ -65 to + 150·C
Lead temperature (during soldering):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case
for10smax ............................... ±265·C

Strobe Data

Address

Ka

Kb Select

Switch On

ABC D
1 1 1 1

1

0

15 (X4Y4) &
15' (X4'Y4')

Switch Off

1 1 1 1

0

1

15 (X4Y4) &
15' (X4'Y4')

All Switches
Off#

XXXX

1

1 ALL

No Change

XXXX

0

0

XXXX

1 = High Level; 0 = Low Level; X = Don't Care
# In the event that Ka and Kb are changed from levels 1,1 to 0,0 Kb
should not be allowed to go to 0 before Ka,otherwise a switch which was
off will inadvertently be turned on.

Decoder Truth Table
Address
A BCD
0 000
1 o 0 0
0 1 o 0
1 1 o 0
0 0 1 0
1 0 1 0
0 1 1 0
1 1 1 0

*Maximumcurrent through transmission gates (switches) = 25 mAo

1-119

Select

Address

A BCD
X1Y1 & X1'Y1' 0 o 0 1
X2Y1 & X2'Y1' 1 o 0 1
X3Y1 & X3'Y1' 0 1 0 1
X4Y1 & X4'Y1' 1 1 0 1
X1Y2 & X1'Y2' 0 0 1 1
X2Y2 & X2'Y2' 1 0 1 1
X3Y2 & X3'Y2' 0 1 1 1
X4Y2 & X4'Y2' 1 1 1 1

Select
X1Y3&X1'Y3'
X2Y3 & X2'Y3'
X3Y3 & X3'Y3'
X4Y3 & X4'Y3'
X1Y4&X1'Y4'
X2Y4 & X2'Y4'
X3Y4 & X3'Y4'
X4Y4 & X4'Y4'

Static Electrical Characteristics
Characteristic

Conditions

Fig.

VIS

VOO

(V)

(V)

Limits at Indicated Temperature (OC)t

-551 -40

I

I Min. I

+25

J

+851 +125

Units

I Max. I Max.

Max.

5
10
20
100

150
300
600
3000

150
300
600
3000

225
85
75
65

600
180
135
95

725
205
155
110

800
230
175
125

n

25
10
8
5

-

-

-

n

±1000

nA

Max.

Max.

Typ.

5
10
20
100

5
10
20
10r

-

0.04
0.04
0.04
0.08

-

Crosspoints
Quiescent
Device Current,
100 Max.
ON Resistance
RON Max.

~ON

Resistance,
~RON

OFF
Leakage
Current
IL Max.

1

Any Switch
VIS=
o to VOO

5
10
15
20
5
10
12
15

475
135
100
70

500
145
110
75

-

5
10
12
15

-

-

0,18

18

± 1000

-

±1

±100·

~

5
10
15

1.5
3
4

-

-

-

-

1.5
3
4

1.5
3
4

5
10
15

3.5
7
11

3.5
7
11

-

-

3.5
7
11

-

Between
any two
switches
All switches
OFF

-

4

!

-

-

-

-

jJ.A

Controls
Input Low
Voltage
VIL Max.

OFF Switch
IL<0.2fLA

Input High
Voltage,
VIH Min.

ON switch
see RON
charac·
teristic

Input
Current,
liN Max.

Any control

-

-

2

0,18

18

±0.1

-

±0.1

*Determined by minimum feasible leakage measurements for automatic testing.
tValues at - 55, + 25, + 125, apply to 0 package. Values at - 40, + 25, + 85, apply to P package.

1-120

-

I -

±10·5 ±0.1

±1

V

±1

pA

Dynamic Electrical Characteristics at TA = 25·C
Conditions

Characteristic
tis 1 RL
kfi
kHz

Limits

1Vis -I VDD
(V)

(V)

IFi9.

5
10
15

5
10
15

5

Units

Min. 1 Typ.1 Max.

Crosspoints
Propagation Delay Time, (Switch ON) Signal
Input to Output, tPHL, tPLH

-

Frequency Response, (Any switch ON)

1

10
CL

-

30
15
10

60
30
20

ns

-

40

-

MHz

-

1
0.25
0.15

-

-96

-

dB

=50pF; t r, tf = 20ns
1

10

5

Sine wave input,
Vos
3 dB
20 log-y;;-

=-

Sine Wave Response, (Distortion)

1
1
1

1
1
1

Feedthrough
All Switches OFF (See Fig. 13)

1.6

0.6

Frequency for Signal Crosstalk
Attenuation of 40 dB
Attenuation of 95 dB (See Fig. 112.)

-

Capacitance,
Xn to Ground
Y n to Ground
Feedthrough

2.5
5
7.5

5
10
15
10

2*

13

-

%

-

Sine wave input

-

-

0.6

1

10

-

-

2.5
0.1

-

Sine wave input

MHz
kHz

-

-

-

pF

-

25
60
0.6

-

500
230
170

1000
460
340

-

515
220
170

1000
440
340

500
215
160

1000
430
320

-

480
225
155

960
450
300

-

450
200
135

900

-

450
200
130

900
400
260

450
165
110

900
330
220

280
130
90

560
260
180

-

-

-

-

-

-

-

Controls
Propagation Delay Time, High Impedance to
High Level or Low Level, tpZH, tPZL
Strobe to Output, SSI 22101

=
=
=

RL
1kfi
CL
50 pF,
t r, tf
20 ns

Data·ln to Output, SSI.22101

Ka to Output, SSI22102

I
I

Address to Output, SSI22101,SSI 22102

I
I

i

Propagation Delay Time, High Level or Low
Level to High Impedance, tpHZ, tPLZ
Strobe to Output, SSI 22101

I

I

Kb to Output, SSI 22102

5
10
15

6

5
10
15

7

5
10
15
5
10
15
5
10
15
5
10
15

Data-In to Output, SSI22101

5
10
15

Ka - Kb to Output, SSI 22102

5
10
15

L----

• Peak-to-peak voltage symmetrical about VOO unless otherwise specified.
-2-

* RMS
1-121

8

6

-

-

-

-

-

-

-

400
270

ns

Dynamic Electrical Characteristics at T A = 25°C (cont'd)
Limits

Conditions

Characteristic
tis
kHz

I

RL
kf!

I

VDD
(V)

I

Fig

Min.

I

Typ·i Max.

Units

Controls (cont'd)
RL = 1k.
CL = 50 pF,
t r, tf = 20ns

Address to Output,
SS122101,SS122102

5
10
15

8

-

425
190
130

850
380
260

-

260
120
80

500
240
160

-

0
0
0

Minimum Strobe Pulse Width tw
SSI22101

5
10
15

Address to Strobe Setup or Hold Times,
tsu, tH, SSI 22101

5
10
15

Strobe to Data·ln Hold Time, Time,
thHL; thLH, SSI 22101

5
10
15

Address to Ka and Kb Setup or Hold Times,
tsu, tH, SSI 22102

5
10
15

Minimum Ka • Kb Pulse Width, tw
SSI22102

5
10
15

-

Minimum Ka Pulse Width, tw
SSI22102
Minimum Kb Pulse Width, tw
SSI22102
Control Crosstalk, Data·ln, Address, or Strobe
to Output

100

10

-

-

-160
-70
-50

10

-

200
80
60

400
160
120

-

-160
-70
-50

0
0
0

-

375
160
110

750
320
220

5
10
15

-

425
175
120

850
350
240

5
10
15

-

-

200
90
70

400
180
140

-

75

-

5

5

-

11

ns

-

mV
(peak)

Square wave
input = 5V, tr,tf
= 20ns, Rs =
1kf!
Any Control
Input

Input Capacitance, CIN

9

-

7.5

pF

Note: Close switch S after applying VOO

Note:
Measure inputs
sequentially to
both VOD and VSSConnect all unused
inputs to either
VODorVSS-

Fig.1 - Quiescent current test circuit

Fig. 2 -

Input current test circuit.

1-122

Fig. 3 -

Dynamic power dissipation test

circl~H

for SSt 22101

silicon
Jl rJkmJ'
14_3_5.1.M_Yf.o.rd.R.O.Od_,_TU.S.tln.,_CA.:~.7.14.).7.31.-7.1.10.,.TW.X

______________________

__
91.0.-5.9.5-.2.80.9_____________________

ON

50pF

SW ~ ANY CROSSPOINT
STROBE ~ DATA-IN ~ VDD
Fig. 5 -

Propagation delay time test circuit and waveforms
(signal input to signal output, switch ON).

VDD~~

DATA-IN

STROBE

Fig. 4

~

OFF switch input or output leakage current
test circuit (16 or 32 switches).

0

VDD - DATA-IN

50pF

DATA·IN

V"

90%

o

10%
-

Fig.6 -

tpHZ

Propagation delay time test circuit and waveforms (strobe to signal
output, switch Turn·ON or Turn-OFF).

VDD-_

ADDRESS

ADDRESS ",1

50%

VDD

"~"

l50

Fig. 7 -

0=rj;c ~-tPZH

VD D - - -

J~~PF
6~ '.
SW ~ ANY CROSSPOINT
STROBE ~ VDD

50o/~

50%

VDDJE:

DATA.I~~50%
IpZL
VOD -

90%

Vo,

PF

o

Propagation delay time test circuit and waveforms (data-in to
signal output, switch Turn-ON to high or low level).

~ \
:Ath

SW ~ ANY CROSSPOINT
STROBE = VDO

n

Fig. B -

Propagation delay time test circuit waveforms (address to
signal output, switch Turn-ON or Turn-OFF).

~rthLH

I
J\

STROBE

::-j

----X ________ ..1'<::----ADDRESS

t

~

OUTPUT OF SWITCH
ADDRESSED

Note:
Set all switches to OFF initially. Apply Voo to all X inputs and return all
Y outputs to VSS through 1K. Address X1Y2 (ABeD) with tin 10kHz.

Note
If setup and hold times provided are too short, an unaddressed switch
may be turned on or off simultaneously with the addressed switch.

Fig. 9 - Address to strobe setup and hold times.

Fig. 10 - Strobe to Data-In hold time th for SS122101.

ON

Vi'o--r-Gi
!~O

OFF

~V"

!~O l~o

10001l

Fig. 12 - Test circuit for crosstalk between
switch circuits in the same package.

Fig. 11 - Test circuit and waveforms for crosstl3.lk
(control input to signal output).

No responsibility is assumed by S5i for use of this product nor for .any infringements of patents and trademarks or other rights of third parties resulting from
its use. No license is granted under any patents, patent rights or trademarks of

Yo,
ISOLATION (dB) '" 20 LOG

5Si. 5Si reserves the right to make changes in specifications at any time and
without notice.

1-123

V'i;

Fig. 13 - Test circuit for feedthrough
(any OFF switch).

Jh Jl rskmJ'"

55122106

8x8x1 Crosspoint Switch
with Control Memory

INTEGRATION

Data Sheet
GENERAL DESCRIPTION

FEATURES

The SSI 22106 is an 8x8x1 analog switch array of CMOS
transmission gates designed using high-speed CMOS
technology. It offers high noise immunity and has very low
static power consumption.

• 64 crosspoint switches in an 8x8 array

At power up all switches are automatically reset. A "low"
on the Master Reset turns OFF all switches and clears the
control latches. A 6-bit address through a 6-line-to-64-line
decoder selects the transmission gate which can be turned
ON by applying a logical ONE to the DATA INPUT and
a logical ZERO to the STROBE. Similarly, any transmission
gate can be turned OFF by applying a logical ZERO to
the DATA INPUT while strobing the STROBE with a
logical ZERO.
A CE allows the crosspoint array to be cascaded for
matrix expansion in both the X and Y direction. The
SSI 22106 is supplied in a 28-lead hermetic dual-In-line
ceramic package and 28-lead dual-In-line plastic packages.

• lAP compatible control inputs
• On chip line decoder and control latches
• Ron resistance 9Sfl max @ 4.SV
• ~Ron 2sfl typical @ 4.SV
• Operation voltage 2 -10V
• Analog signal capability Vdd/2
• Automatic' power up reset
• Parallel data input
• Second source for RCA CD 22106
• Address latches on-chip
• CMOS or TTL ("T" suffix) compatible inputs

SSI 22106 Block Diagram

DATA

STROBE

A5

ADDRESS

DECODER
AND
LATCHES

8x8
SWITCH

Yo - Y7

I

CE

A4

STROBE

27

A3

Cl'

26

A2

DATA

25

A,

VSS

24

AO

Xo

23

X,

22

X3

58122106

X2
X4

21

X5

X6

20

X7

MR

10

19

VDD

Y7

11

18

Yo

Y6

12

17

Y,

Y5

13

16

Y2

Y4

14

15

Y3

I

\
Xo - X7

CAUTION: Use handling procedures necessary
for a static sensitive component

1-124

55122106

8x8x1 Crosspoint Switch with Control Memory
PIN DESCRIPTION
Pin No. Symbol
24,25,
26,27,
28,1,

Maximum Ratings, Absolute - Maximum Values:
DC Supply - Voltage (Vcc)
(Voltages referenced to ground) ............ - 0.5 to 11 V
DC Input Diode Current, 11K
(ForVI< - 0.5V orVI>Vcc + 0.5V) ............. ± 20mA
DC Output Current, 10K
(ForVo<-0.5VorVO>Vcc + 0.5V) ............ ±20mA
DC transmission gate current ................ ± 25mA

Description
6 bit address control inputs

AO·A5

STROBE Strobe input. A "low" of STROBE in·
put permits DATA input to turn on or
off the switch specified to connect
X's and V's

2

3

CE

4

Chip Enable input. A "low" of CE
allows the crosspoint array to be
cascaded for matrix expansions in
both the X and Y directions.

DATA

6,23,
7,22,
8,21,
19,20

Operating - Temperature Range (TA):
PackageTypeD ................... -55to + 125°C
Package Type P .................... - 40 to + \85 °C

Ground

XO,X7

Storage Temperature (T stg) ........... - 65 to

8 lines in X direction

MR

10

For TA = - 55 to + 100°C (Package Type D) ... 500mW
For TA = + 100 to 125°C (Package Type D) .
. . . . . . . . . . . . . Derate Linearly at 12mW/ °C to 200mW

Data Input. With a "zero" of
STROBE, a "one" of DATA turns on
the switch and a "zero" of DATA in·
put turns off the switch.

Vss

5

Power DisSipation per Package (PO):
ForTA = - 40 to + 60°C (Package Type P) .... 500mW
For TA = + 60 to + 85°C (Package Type P)
............. Derate Linearly at 12mW/oC t0200mW

Recommended Operating Conditions:
For maximum reliability, nominal operating conditions
should be selected so that operation is always within the
following ranges:

Master Reset input. A "low" of MR
turns off all switches and clears the
control latches.

ra·11

YO'Y7

8 lines in Y direction.

19

VDD

Positive Power Supply.

+ 150°C

Characteristic
Supply·Voltage Range
(For TA = Full Package
Temperature Range) Vcc
SSI 221061P, 22106MD
SSI 221061TP, 22106MTD
DC Input or Output Voltage
Yin, Vout

Min

Max

Units

2
4.5

10
5.5

V
V

0

Vcc

V

Static Electrical Characteristics
SSI 22106
Test
Conditions
Characteristic
VI
V
High·Level
Input Voltage

10
rnA

lP/MD
Types

2

-

4.5

-

9

-

-

Low·Level

Input Leakage
Current
(Any Control)
Quiescent Device
Current
(with MR= 1)

1.5

4.5 3.15

9
Input Voltage

VIL

MD
Types

-401
-551
+25°C
+85°C + 125°C
Vee
V Min Typ Max Min Max Min Max
2

VIH

lP
Types

6.3

-

1.5

-

1.5

3.15

-

3.15 -

6.3

V

-

to

2.7

5.5
Any Voltage
Between
5.5
Vee & Gnd

2.7

2.7

Vee
or
Gnd

10

-

-

±0.1

-

±1

-

±1

Icc

Vee
or
Gnd

10

-

-

5

-

50

-

100

1·125

Units

2

-

-

2

-

2

-

V

-

-

0.8

-

0.8

-

0.8

V

-

-

±0.1

-

±1

-

±1

pA

-

-

2

-

20

-

40

pA

5.5

0.5

II

MTD
Types

4.5
-

1.35

-

tTP
Types

-401
-551
+25°C
+85°C + 125°C
Vee
V Min Typ Max Min Max Min Max

-

1.35

0.5

VI

tTP/MTD
Types

6.3

-

0.5
1.35

Test
Conditions

4.5

-

Vee
or
Gnd

to

5.5

Static Electrical Characteristics (Cont.)
SSI22106
1P/MD
Types

Test
Conditions
Characteristic

Off Leakage
Current
(with MR = 1)

1P
Types

10

Vce

V

mA

V

IL ~witches
OFF

1TP
Types

MTD
Types
Units

-401

-551
+ 125°C

VI

Vec

-401

-551

+85°C

+ 125°C

Min Typ Max Min Max Min Max

V

V

-

5.5

-

-

0.1

-

1

-

1

pA

-

4.5

-

64

95

-

120

-

140

.0.

-

4.5

-

58

85

-

110

-

130

.0.

4.5

-

25

-

-

-

-

-

.Q

+25°C

10

-

-

0.1

-

1

-

1

Vcc

2

-

470 700

-

875

-

1050

to

4.5

-

64

95

-

120

-

140

Gnd

9

-

45

70

-

90

-

100

-

-

-

-

-

-

-

-

Vcc/2

4.5

-

58

85

-

110

-

130

9

40

60

-

80

-

90

-

-

-

-

-

-

-

to

-

-

-

-

Gnd

Ron

"On" Resistance

Vcc

-

-

-

-

Between Any Two

to

4.5

-

25

Gnd

9

-

23

-

t::.Ron

0

I III "ON"

-10

Min Typ Max Min Max Min Max

I II

IIII

\

2

m
:s

m

·3

I

V'S" 2 V pop

0
-4 i=

:r-50

RS = RL = 600Q
TA = 25 D C
I

-30

,

::S-40

"

0~~
OV
<.~'I'

:r:
-70
<>
UJ

~-80

~~~

-90

V

-110

100

1K

-4

30

,

~

:::>

0"
a:

:::>

-8

UJ

.

'"z

lOOK

1M

~

:r:
u

0~

~

:S

<.~'Y'

'"z

~

?

~'- 70
<>
UJ

ii

.,..I

Tri"1 ATTI~r'°N

40

:r: ·50

z

>-6 >~
:r:
-7 u
>-

-10

0
-2

m

z

UJ

9

.r-

-100

5

0
·10
·20

~

V

:::>
~-60
I-

Vcc

0
-1

ATTENUATION

Voo == 4.5 V
Vss = -4.5 V

-20

10

1TP/MTD
Types

All

"On" Resistance

Channels

Test
Conditions

+85°C

+25°C
VI

MD
Types

10M

1M

lOOK

(Hz)

Typical "ON" switch attenuation and "OFF" switch feed through as a function
of frequency.

Switching Characteristics
SSI22106
25°C
Characteristic

Test Conditions

Vss

IP
& MD

Vee

-40°C to +85°C

ITP
& MTD

IP

-55°C to +125°C

ITP

Units

MTD

MD

Min Max Min Max Min Max Min Max Min Max Min Max
CONTROLS
Propagation Delay Time
tpZH for Strobe to Output
(Switch Turn-on to High Level)
tpZH for Data-in to Output
(Turn-on to High Level)

I

RL
CL
tr,tt

= 10K{l
= 50pF
= 6ns

0
0
0

2
4.5
9

-

0
0
0

2
4.5
9

-

-

1-126

370
110
65
240
75
50

-

-

-

-

120
-

-

-

-

-

-

-

-

85

-

-

-

-

385
125
70
255
85
55

-

-

-

-

135
-

-

-

-

-

-

95
-

-

-

-

400
135
75

-

-

270
90
60

-

-

-

100
-

-

150

-

ns

55122106
8x8xl Crosspoint Switch with Control Memory
Switching Characteristics (cant.)
55122106
-40°C to +85OC

25°C
Characteristic

Test Conditions

lP
& MD

lTP
&MTD

Vss

Vcc

0
0
0

2
4.5
9

-

380 110 65 -

0
0
0

2
4.5
9
2
4.5
9

-

400
135
90

lP

-55OC to + 125°C

lTP

MD

Units

MTD

Min Max Min Max Min Max Min Max Min Max Min Max
Address to Output
(Turn-on to High Level)
Propagation Delay Time
Strobe to Output
(Switch Turn-off
Data-in to Output
(Turn-on to Low Level)
Address to Output
(Turn-off)

tpZH

tPHZ
tpZL
RL = 10 kn
CL= 50 pF
tpHZ

Minimum Set-up Time
Data-in to Strobe, Address
Minimum Hold Time
Data-in to Strobe, Address
Minimum Strobe Pulse Width

Maximum Switching
Frequency
Input (Control)
Capacitance

tr tr = 6 ns

tsu

tH

tw

Fa

Cl

0
0

-

240
75
50

-

-

-

420
140
95

0
0
0

2
4.5
9

-

0
0
0

2
4.5
9

35
20
15

0
0
0

2
4.5
9

85
25
20

0
0
0

2
4.5
9

200
45
25

0
0
0

2
4.5
9

0.7
3.0
7

-

-

-

-

-

120

-

-

-

-

-

-

150 -

-

-

-

85

-

-

-

150
-

-

-

-

-

-

-

20

-

-

-

-

25

-

-

-

-

-

-

400
125
75

-

-

-

135
-

-

-

-

170

-

-

-

-

-

-

95

-

-

-

-

440
155
100

-

170

-

-

-

-

45
20
15

-

20

-

-

90
25
20

-

-

-

-

-

-

-

55

-

-

-

-

-

-

-

2.8

-

-

-

-

0.6
2.8
6.5

10

-

10

-

210
55
30

-

-

40
20
15

-

420
135
80

420
155
100
255
85
55

-

-

-

-

-

25
-

-

-

-

-

150

-

-

400
160
110

-

180

-

-

270
90
60

-

-

-

100

460
165
105

-

-

180

-

20

-

-

-

-

-

25

-

-

-

220
60
35

-

-

-

-

2.5

-

-

-

-

10

-

10

-

-

-

-

65

-

-

-

-

-

-

2.6

-

-

-

0.5
2.7
6.0

10

-

10

-

ns

-

-

95
25
20

ns

ns

ns

70

-

ns

MHz

pF

Analog Channel Characteristics
55122106
25°C
Characteristic

Test Conditions VIS

Vss

Vcc

-

0
0

-

-

2
4.5
9

IP
& MD

-40OC to +85°C

ITP
& MTD

IP

- 55°C to + 1250C
MD

ITP

Units

MTD

Min Max Min Max Min Max Min Max Min Max Min Max
Propagation Delay Time tPHL
Signal Input to Output
tpLH
Switch Frequency
Response@ -3dB
Crosstalk Between
Any Two Channels

-

RL = 10kn
CL = 50 pF
tr,tf = 6 ns

-

RS=RL=600n 2Vp-p -2.25 2.25
2Vp-p -4.5 4.5
RS=RL=600n,
1=1 KHz
f=1 MHz

P-P -2.25
/:V
2Vp-p -2.25
2Vp-p -4.5

30
20
15

-

2.25
2.25
4.5

-

20

-

-

Typ.
5
6

Typ.
5
6

Typ.
-110
-53
-55

Typ.
-110
-53
-55

1-127

-

33
22
17

-

-

-

-

22

-

35
25
19

-

25

ns

MHz

dB

Analog Channel Characteristics (con!.)
SSI22106
-40OC to +85°C

25°C
Test Conditions VIS

Characteristic

Vss

Vce

1P
& MD

HP
& MTD

1P

1TP

-55°C to +125°C
MD

Units

MTD

MiniMax MiniMax Min Max Min Max Min Max Min Max
Switch "OFF"
-40dB Feed Through
-Frequency
Total Harmonic
Distortion

THD

Control to Switch
Feed-thru Noise
(DATA IN, Strobe, Address)
Capacitance
Xn to Gnd
YntoGnd

MH

8

Typ.
7
8

Typ.
.05
.05
0.25
0.12

Typ.
.05
.05
0.25
0.12

%

5
10

Typ.
35
65

Typ.
35
65

10
10

Typ.
48
44

Typ.
48
44

Rs=RL=6000 2Vp-p -2.25 2.25
2Vp-p -4.45 4.45
RL =10kO
1=1 kHz sinewave
RL =6000
1=lkHz sinewave

4Vp-p
8Vp-p
4Vp-p
7Vp-p

RL =10k!l
t r ,tl=6 ns

5
10

-2.25 2.25
-4.5 4.5
-2.25 2.25
-4.5 4.5

0
0

Co
1=1 MHz
1=1 MHz

0
0

Typ.
7

mV
pF

Yo

Y1

Y2

AO
Y3

A1
A2
Y4

A3
A4
Y5

A5

Ye

Y7

1-128

Truth Table
c-

!

AS A4 A3 A2 A1

Ao

Select

AS~A3A2A1

Ao

Select

0
a
a
a
0
0
0
a

0
a
a
a
0
0
0
a

a
a
a
a
1
1
1
1

a
0
1
1
a
a
1
1

0
1
a
1
0
1
0
1

Xo
X1
X2
X3
X4
X5
X6

0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

0
a
0
0
0
0
0
a

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0

a
a
0
0
a
a
0
a

0
0
0
0
0
0
a
a

1
1
1
1
1
1
1
1

a
a
a
a
1
1
1
1

0
0
1
1
a
0
1
1

a
1
0
1
0
1
a
1

Xo
X1
X2
X3
X4
X5
X6

0
:
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

0
a
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0: Xo Y3
1 I X1 Y3
o i X2 Y3
1 ! X3 Y3
01 X4 Y3
1 X5 Y3
o I X6 Y3

Y1
Y1
Y1
Y1
Y1
Y1
Y1
Xl Y1

1

1

Xo
X1
X2
X3
X4
X5
X6

i

Xl

I Xl

AS A4 A3 A2 A1

-Y2
Y2
Y2
Y2
Y2
Y2
Y2
Y2

0
a
a
a
0
a
0
a

Yo
Yo
Yo
Yo
Yo
Yo
Yo
Xl Yo

Switch

Switch

Switch

Ao

1 0 0 0 0 0
100001
100010
100011
100100
1 0 0 1 0 1
1 0 0 1 1 0
1 0 0 1 1 1
1
1
1
1
1

0
0
0
0
0

1
1
1
1
1

0
0
0
0
1

0
0
1
1
0

0 I
1I
0i
1·
0

Ao

Y4
Y4
Y4
Y4
Y4
Y4
% Y4
Xl Y4

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

o
0
1
1
0
0
1
1

0 Xo
1 X1
0 X2
1 X3
0 X4
1 I X5
01 X6
1 I Xl

Xo
X1
X2
X3
X4

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

a

0 Xo Yl
1 X1 Yl
0 X2 Yl
1 X3 Yl
0 X4 Yl
a 1 X5 Yl
1 0 X6 Yl
1 1 Xl Yl

Xo
X1
X2
X3
X4
X5

Y5
Y5
Y5
Y5
Y5

1 0 1 1 0 1 IX5 Y5
1 0 1 1 1 a X6 Y5
1 0 1 1 1 1 Xl Y5

Y~_

Switch
As A4 A3 A2 A1

Select

J

0
0
0
1
1
1
'1

0
0
1
1
0

DATA·IN

SW

~

ANY CROSSPOINT

Propagation delay time test circuit and waveforms (strobe to signal
output, switch Turn-ON or Turn-OFF).

DATA·IN

V00JE:

VOO£.

OATA_I~~50%'PZH

OATA_I~~50%.'PZL

VOO

Vos
0-

SW ~ ANY CROSSPOINT
STROBE ~ VDD

VOD -

Vos

o

10%

Propagation delay time test circuit and waveforms (data-in to signal output,
switch Turn-ON to high or low level).

1,129

90%

Select

Y6
Y6
Y6
Y6
Y6
Y6
Y6
Y6

ADDRESS

SW-ANY CROSSPOINT
STROBE = VOO

=0

VDD-ADDRESS
50%

50%

Propagation delay time test circuit waveforms (address to signal output,
switch Turn-ON or Turn-OFF).

+5V

+5V

CMOS
OUTPUT
CONTROL
INPUT

Vce

SSI 22106

ANALOG OUTPUT
0-5V

ANALOG
INPUT
(}-5V

GND
TYPICAL SINGLE-SUPPLY CONNECTION FOR SSI 22106

+5V
+5V
CMOS BIPOLAR
OUTPUT

+5V

CONTROL
INPUT

rJ_

OVIL
-5V
-5V

SSI 22106

ANALOG OUTPUT

-5 to +5V

ANALOG
INPUT
-5 to +5V

-5V
TYPICAL DUAL-SUPPLY CONNECTION FOR SSI 22106

+5V

+5V

TTL TYPE
OUTPUT

Vcc
CONTROL
INPUT
SS122106f

ANALOG OUTPUT

O-SV
ANALOG
INPUT
(}-5V
VSS

GND
TYPICAL SINGLE-SUPPLY CONNECTION FOR SSI 22106T WITH TTL INPUT

1-130

50%

JiIkonJz
rsfonJ
c: :~_71_4_)_73_1_-7_1 _0_,T_W_X_9_1_0-_59_5_-2_8_0_9

____________________1_4_3_51_M_Y_fo_rd_R_o_a_d,_T_us_ti_n,__

_____________________

Telecommunications Circuits
Circuit Function

Features

Tone Signaling Products

551201

Integrated DTMF Receiver

Binary or 2-of-8 output

551202

Integrated DTMF Receiver

Low-power, binary output

551203
551204

Integrated DTMF Receiver

Binary output, Early Detect

Integrated DTMF Receiver

S51207

integrated MF Receiver
Integrated DTMF Receiver
Integrated DTMF Transceiver

Low-power. binary output
Detects central office tone signals
Generator and Receiver, IJP interface

Integrated DTMF Transceiver

Generator and Receiver, f.lP interface, Call Progress Detect

Call Progress Detector

Detects supervision tones, Teltone second-source

551981

Precise Call Progress Detector

Detects supervision tones, Teltone second·SQurce

551982

Precise Call Progress Detector

Detects supervision tones, Teltone second·source

551957
55120C89
55120C90
551980

Early Detect, Dial Tone reject

12V
5V
5V
5V

22 DIP
18 DIP
18DIP
14DIP

10V

20 DIP

5V
5V

22 DIP
22 DIP

5V
5V

22 DIP
8DIP

5V
5V

22 DIP

10V
10V

28 DIP
28 DIP

5V

28 DIP

22 DIP

Modem Products

551 K212

1200/300 bps Modem

OPSK/FSK, single chip, autodial, Bell 212A

551 K214

2400 bps Analog Front End

Analog Processor for DSP V.22 bis Modems

551 K222

1200, 600, 300 bps Modem

DPSK, FSK, single chip, autodial, V.22

551223

1200 bps Modem

F5K, HDX/FDX

10V

16DIP

551 K224

2400 bps Modem

QAM, DP5K, F8K single chip Y.22 bis

10V

28 DIP

551291/213

1200 bps Modem

DPSK, two chips, low·power

10V

40/16 DIP

5513522

1200 bps Modem Filter

8ell212 compatible, AMI second·source

10V

16DIP

5V

124 DIP

Speech Synthesis Products

I 551 263A I 5peech 5ynlhesizer

! Phoneme·based, low data rate, VOTRA>< second·source

Switching Products

55180C50

T1 Transmitter

Bell 02, 03, 04, serial format and mux, low power

5518OC60
55122100

T1 Receiver

Bell 02, 03, serial synchron. and demux, low power

Cross-point Switch

4x4x1, control memory, RCA second·source

12V

16DIP

5512210112
58122106

Cross·point Switch

4x4x2, control memory, RCA second·source

Cross·point Switch

8x8x1, control memory, RCA seeond·source

12V
5V

55122301

PCM Line Repeater

T1 carrier signal recondition

24 DIP
28 DIP
18DIP

No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or ot,her rights of third parties resulting from
its use. No license is granted under any patents, patent rights or trademarks of

5V
5V

5V

28DIP,Q
28DIP,Q

SSi. SSi reserves the right to make changes in specifications at any time and
without 'notice.

1·131

Jifuon Ji rskmJ'"

55122301
PCM Line Repeater

INNOVATORS IN INTEGRATION

Data Sheet
GENERAL DESCRIPTION
The 881 22301 monolithic PCM repeater circuit is designed for T1 carrier systems operating with a bipolar pulse
train of 1.544 Mb/s. It can also be used in the T148
carrier system operating with a ternary pulse train of 2.37
Mb/s. The circuit operates from a 5.1V ± 5% externally
regulated supply.

The 88122301 is supplied in an 18-lead dual-in-line
plastic package.
FEATURES

The 881 22301 provides active circuitry to perform all
functions of signal equalization and amplification,
automatic line buildout (ALBO), threshold detection, clock
extraction, pulse timing, and buffered output formation.

Fig. 1 -

•

Automatic line buildout

•

5.IV supply voltage

•

Buffered output

•

Second source for RCA CD22301

SSI 22301 Block Diagram

Vee
14

ALBO

OUTPUTS

j

2

Hf----4

"
"

ALBOGROUNO

ALBO 1 OUTPUT

17

ALBO 2 OUTPUT

t------H13
PHASE
SHIFT

PREAMP
INPUT

PREAMP
OUTPUT

j
j

ALBO BIAS

asc BIAS

ALBO 3 OUTPUT

15

PREAMP INPUT +

14

Vee

PREAMP INPUT -

13

CLOCK LIMITER OUTPUT

PREAMP OUTPUT +

12

TIMING PULSE INPUT

10

OUTPUT PULSE 2

PREAMP OUTPUT -

LC TANK INPUT

OUTPUT PULSE 1

f-------+-{12

I C~E

SUBSTRATE

Pin Out
(Top View)

[PUT

CAUTION: Us. handling procedures necessary
for a static sensitive component

1-132

55122301

PCM line Repeater
PIN DESCRIPTIONS

I

PIN DESCRIPTIONS
Description

No. Symbol

Description

Pin No. Symbol

1.

ALBO
Ground ALBO Ground

17.

ALBO
Bias

ALBO Bias control input

2.

ALBO 1 Automatic line build out
Output Output 1

18.

Sub·
strate

Substrate ground

3.

ALB02 Automatic line build out
Output Output 2

4.

ALB03 Automatic line build out
Output Output 3

5.

Preamp
Input+ Positive terminal for pulse input

6.

Preamp Negative terminal for pulse input
Input-

7.

Preamp Positive terminal for preamplified
Output+ output pulse

8.

Preamp Negative terminal for preamplified
Output- output pu Ise

I

9.

VEE

Emitter power supply or digital
ground

10.

Output' Output pulse 2
Pulse 2

11.

Output Output pulse 1
Pulse 1

12.

Timing
Pulse
Input

13.

14.
15.
16.

Maximum Ratings - Absolute Maximum Values
at ambient temperature (TAl = 25·C
DC Supply Voltage ............................. 10V
DC Current (Into Pin90r10) .................... 25 mA
PeakCurrent(lntoPin90r10) ................. 100mA
Input Surge Voltage
(Between Pins5and6, t = 10ms) ............... 50V
Output Surge Voltage
(Between Pins 10 and 11, t = 1 ms) .............. 50 V
Power dissipation per package (PD)
ForTA = -40to +60·C .................. 500 mW
ForTA = +60·C
to + 85·C .... Derate Ii nearly at 12 mW/°C) to 200 mW
Device dissipation per output transistor
ForTA = full package·temperature range ..... 100 mW
Operating temperature range ........... - 40 to + 85·C
Storage temperature range ............ - 65 to + 150·C
Lead temperature (during soldering)
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case
for10smax ............................... +256·C

Phase shifted clock input
*C1 AND L1 RESONATE

AT 1.272 MHz

Clock Clock limiter output
Limiter
Output
Vcc

O.1fLF

0-IH----~>----1

Collector power supply
8.2k.ll

LC Tank External LC clock input
Input
OSC
Bias

Oscillation bias for LC resonance
130n

Fig.2 DC and output pulse test circuit.

PULSE OUTPUT

Static Electrical Characteristics TA = 25"C, Vce = 5.1V±5%
Min.

Typ.

Max.

Units

ALBO Ports Off Voltage

2,3,4,17

-

0

0.1

V

Amplifier Pin Voltage

5,6,7,8

2.4

2.9

3.4

V

Output Voltage

10,11

-

5.1

-

V

12,13,15,16

3.1

3.6

4.1

V

Characteristic

Clock Pin Voltage
DC Currents
Supply Current

Pins

Fig.

2

14

Output Leakage Current

10,11

Dynamic Electrical Characteristics TA = 25·C, VCC = 5.1 V ± 5%
Characteristic

Symbol

Fig.

Min.

Typ.

Zin

3

-

20

-

-

k£l

Preamplifier Output Impedance

Zout

3

-

-

2

k£l

Preamplifier Gain @ 2.37 MHz

Ao

3

-

47

50

-

dB

Preamplifier Input Impedance

1·133

Note

Max.

Units

Dynamic Electrical Characteristics (cont'd)
Symbol

Fig.

Note

Min.

Typ.

Max.

fl.Vout

3

1

-50

0

50

mV

lin (CL)

4

2

10

-

-

kn
kn

Characteristic
Preamplifier Output Offset Voltage
Clock Limiter Input Impedance

Units

ALBO Off Impedance

lALBO (off)

4

3

20

-

-

ALBO On Impedance

lALBo(on)

4

4

-

-

10

n

DATA Threshold Voltage

VTH (D)

5

5,8

0.75

0.8

0.85

V

CLOCK Threshold Voltage

VTH(CL)

5

6,8

-

1.12

-

ALBO Threshold

VTH(AL)

5

7,8

1.5

1.6

1.7

V

42

45

49

%

V

VTH (D) as % of VTH (AL)

-

-

-

VTH (CL) as % of VTH (AL)

-

-

-

65

70

75

%

VOL

2

9

0.65

0.8

0.95

V

9

-0.15

0

0.15

V

40

ns

Buffer Gate Voltage (low)

fl.VOL

2

Output Pulse Rise Time

tr

2,6

9,10

-

-

Output Pulse Fall Time

tf

2,6

9,10

-

-

Differential Buffer Gate Voltage

Output Pulse Width
Pulse Width Differential
Clock Drive Current

40

ns
ns

tw

2,6

9,10

290

324

340

fl.tw

2,6

9,10

-10

0

10

ns

ICL

-

2

-

mA

-

-

Notes:
1. No signal input. Measure voltage between pins 7 and 8.
2. Measure clock limiter input impedance at pin 15.
3. Adjust potentiometer for 0 volts. Measure ALBO off impedances from pins 2. 3 and 4 to pin 1.
4. Increase potentiometer until voltage at pin 17 ;;;: 2 Vdc. Measure ALBO on impedances from pins 2, 3 and 4 to pin 1.
5. Adjust potentiometer for l1v = 0 volts. Then slowly increase 6.v in the positive direction until pulses are observed at the DATA terminal.
6. Continue increasing tJV until the DC level at the clock terminal drops to 4 volts.
7. Continute increasing 6.v until the ALBO terminal rises to 1 volt.
8. Turn potentiometer in the opposite direction and measure negative threshold voltages by repeating tests outlined in notes 5, 6, and 7.
9. Set ein =. 2.75 mV (rms) at f ~ 1.185 MHz. Adjust frequency until maximum amplitude is obtained at pin 15. Observe output pulses at pins 10 and 11.
10. Adiust input signal amplitude until pulses just appear in outputs. Increase input amplitude by three dB.

l,:

18
17

1.

""\

"·1'

1.0/lF

50Q

-=

15

}

12

f----.---<:

1.
VCc =5.1V

14
13

200kQ

18
17

~O'"

15
14
13

f-------+--(J
O.Ol/lF

VCC =5.1V

..J.

12

N.C.

11

11

10
10

Fig.4 - Test circuit for impedance measurement.

Fig.3 • Preamplifier gain and impedance measurement circuit.

17

16
15

3V

8.2kQ

~~ ~

pi If"+JVV'v---+-t-':--"""'---I

'"F~

I
I
I
I

'"F(~
CLOCK
~1/lF

14

.f11l F

2kQ
VCC =5.1V

13

2.75 Vrms
@1.185MHz

8.2kQ

O%-~- ' - - - - - - - -../.-+-

_II,L

I I

8.2kQ

Fig.6 . Output pulse waveform.
DATA

Fig.S - Test circuit for threshold voltage measurement.

1-134

JiIkonJzc: :~_71_4_)_7_31_-7_1 _0_,T_W_X_9_1_0-_5_95_-_28_0_9

_____________________1_4_3_51_M_Y_fo_rd__
RO_O_d,_T_us_t_in,__

_____________________

SOO·800pl

Vee

Typical Application of 551 22301

14

A01 2}-1------j
A023Hf------{
A03

2200pF

PHASE SHIFT
NETWORK

5100

82K

1.8K

No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from
its use. No license is granted under any patents, patent rights or trademarks of

SSi. SSt reserves the right to make changes in specifications at any time and
without notice.

1-135

Section 2

MICROPERIPHERAL
PRODUCTS

2

551 MPD Product
Selector Guide

INTEGRATION

MICROPERIPHERAL PRODUCTS

Head

#of
Channels

~pe

Device

Power
Supplies

Internal
Write
Current
Source

Internal
Center Tap
Voltage
Source

Internal
Rd
Option

Write
Current
Ra!)e
(m )

Read
Gain
(typ)

Read/Write
Data Port(s)

Page
No.

HDD ReadfWrite Amplifiers
SSI104
Ferrite
4

+fN.-4V

x

35

15 to 45

Differential, Bi-directional

2-2

SSI104L

Ferrite

4

+fN,-4V

x

35

15t045

Differential, Bi-directional

2-2

SSI108

Ferrite
Thin Film

4
4

+fN,-4V

x

35

15 to 45

Differential, Bi-directional

±5V

x

N/A

x

123

55 to 110

Differential/Differential

2-2
2-6

Ferrite
Ferrite

2,4,5
2,4,6

±5V
+5V,+I2V

x
x

40
x

100

30 to 50
10 to 50

Differential, Bi-directional
Differential/TTL

2-10

x

Ferrite

2,4,6

x

x

x

100

10 to 50

Differential/TTL

4

35

15t045

Differential, Bi-directional

2-22
2-2

SSI188

Ferrite
Ferrite

+5V,+I2V
+fN,-4V

4

+fN,-5V

SSI501

Ferrite

6,8

+5V,+I2V

x

SSI510
SSI520

Ferrite
Thin Film

4
4

+5V,+I2V
±5V

SSI521

Thin Film

6

+5V,+I2V

SSI114
SSI115
SSI117
SSI117A
SSI122

Device

x

43

35 to 70

Directional, Bi-directional

2-28

x

100

10 to 50

Differential/TTL

2-34

x
x

x
x
N/A

x
x

100
123

10 to 35
30 to 75

Differential/TTL
Differential/Differential

2-40
2-46

x

N/A

x

100

20 to 70

Differential/TTL

2-50

Function

HDD Head Positioning
SSI101A
Preamplifier-Ferrite Head
SS1101A-2
SSI116

Preamplifier-Ferrite Head
Preamplifier-Thin Film Head

SS116-2

Preamplifier-Thin Film Head

2-16

Features
Av = 93, BW=10MHz,en=7.0nVyrHz

2-54
2-54

8.3V/1CN

Av = 93, BW = 10MHz,en = 7.0nVyrHz
Av = 250, BW=20MHz,en=0.94nVyrHz

+12V

Av=250, BW=20MHz,en= 0.94nVyrHz

8.3V/1OV
+12V

2-56
2-56

HDD Read Data Path
SSI531

Data Separator

SSI540
SSI541

Read Data Processor

+5V
+5V,+I2V

Read Data Processor

+5V, +12V

High Performance PLL, XTAL

asc, Write Precompensation

2-58

Time Domain Filter

2-66

AGC, Amplitude & Time Pulse
Qualification, RLL Compatible

2-74

2-80
2-84

HDD Motor Control/Support Logic
SSI545
SSI590

Support Logic

+5V

Includes 57506 Bus Drivers/Receivers

2-Phase Motor Speed Control

+12V

SSI591

3-Phase Motor Speed Control

+12V

± 0.035% Speed Accuracy
± 0.05% Speed Accuracy

2-88

FlOppy Disk Drive Circuits
Read Data Path
Read/Write
Support Logic

+5V,+I2V

2 Channel Read/Write With Read Data Path

2-92

+5V, +12V
+5V,+I2V

2,4 Channel Read/Write Circuit
Port Expander, Includes SA400
Interface Drivers/Receivers

2-98

1 Read Data Path

+ 5V, + 12V

SSI570
SSI575
SSI580

2-102

Tape Drive Circuits
1 SSI 550

1 4 Channel Read/Write w/ Read Data Path

Memory Products
SSI67C401

64 x 4 FIFO

Low Power, High Speed Buffer (10MHz, 15MHz)

SSI67C402

64x5FIFO

Low Power, Hi9h Speed Buffer (10MHz, 15MHz)

2-1

12-1081

4-Channel
Read/Write Circuit
551104, 104l, 108, 122
INTEGRATION

Data Sheet

US

CE

ws Lr~----.,

H01
H02
OXLr~--~~L-----~
OYLr~--~--------~

2.
23

WS

VCC

22

H21

US

21

H22

WC

20

H01

NC

19

H02

NC

18

H31

NC

17

H32

OX

16

H11

15

H12

OY

L--=,;J=r---'

GNO

VEE
HS1

10

HS2

11

,.

CE

VEE

12

13

GNO

SSI 104/108 Pin Out

H11
H12
H21
H22

HS1 Lr-+---r---~

H31
H32

HS2

WC

Block Diagram

VEE

22

GNO

HS1

21

WS

VCC

20

H21

us

19

H22

WC

18

H01

OX

17

H02

NC

16

H31

OY

15

H32

HS2

H11

VEE

10

"13

H12

GNO

11

12

CE

SSI 122 Pin Out

FEATURES
• IBM 3350 compatible performance.
• IBM compatible power supply voltages and logic
levels.

DESCRIPTION
The 551 104 is a monolithic bipolar integrated circuit.
for use in high performance disk drive systems where it
is desirable to locate the control circuitry directly on the
data arm. Each circuit controls four heads and has
three modes of operation: Read, Write and Idle.
The 104L is a low·noise version of the 104 with ali

• Four read/write channels .
• Safety circuits

other parameters identical. Both are packaged in a 24
pin flat pack.
The 551 108 and 122 are identical in performance
to the 104. The 108 is packaged in a 24 pin dip package
while the 122 is packaged in a 22 pin dip.

2-2

4-Channel
Read/Write Circuit
551 104, 104L, 108, 122
CIRCUIT OPERATION

WRITE MODE
In the write mode, the circuit functions as a current
gate. Externally suppl ied write current is gated by the
state of the head select and data inputs to one side of
one head. Head voltage swings are monitored by the
head transition detect circuit. Absence of proper head
voltage swings, indicating an open or short on either
side of the head or absence of write current, will cause
a fault current to flow into the unsafe pin.

write current is applied to the chip when the chip is in
read mode, the write current will be drawn from the
unsafe pin and the fault will be detected.
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage VCC .................... 7.0V
Negative Supply Voltage, VEE ................. - 5.5V
Operating Junction Temperature ......... 0 °C to 110°C
Storage Temperature ................ - 65°C to 150°C
Input Voltages
Head Select (HS) ............. VEE - 0.3V to + 0.3V
Unsafe (US) ................. - 0.3V to VCC + 0.5V
Write Current (WC) ................. VEE - 2 to 0.3V

READ MODE
In the read mode, the circuit functions as a low noise
differential amplifier. The state of the head select
inputs determines which amplifer is active. Data is
differentially read from one of four heads and an open
collector differential signal is put across the Data X
and Data Y pins. If a fault condition exists such that
ELECTRICAL CHARACTERISTICS

Data (Dx, Dy) ..................... VEE - 0.3V to 0.3V
Chip Enable (CE) ........... VEE - 0.3V to VCC + 0.5V
Write Select (WS) ............... - 0.3V to VCC + 0.3V

Unless otherwise specified, 5.7 SVCC S6.7, - 4.2S VEE S - 3.8, OOS T, :::O;:110°C.

POWER SUPPLY

ALL UNITS
Test Conditions

Parameter

Min.

Max.

Units

11.5

23

mA

75+ ICE

rnA

Positive Supply Current (ICC)

Read/Write

Positive Supply Current (ICC)

Idle

Negative Supply Current (lEE)

ReadlWrite

70

mA

Negative Supply Current (lEE)

Idle

52

mA

Min.

Max.

Units

0.0

0.7

LOGIC SIGNALS
Parameter

Test Conditions

Chip Enable Low Voltage (VLCE)

ReadlWrite

Chip Enable High Voltage (VHCE)

Idle

Chip Enable Low Current (ILCE)

VCE = O.OV

Chip Enable High Current (IHCE1)

VCE

Chip Enable High Current (IHCE2)

VCE

Write Select High Voltage (VHWS)

Write/ldle

3.2

Write Select Low Voltage (VLWS)

Read/ldle

Write Select High Current (IHWS)

Write/ldle, VWS = 3.8V
Transition unsafe current off
Transition unsafe on

VCC-1.0 VCC+0.3

V
V

-1.45

-0.47

mA

-350

-100

Il A

+ 100
3.8

Il A
V

-0.1

0.1

V

0.6
0.6

3.2
4.2

mA
mA

0.1

mA

Head Select High Voltage (VHHS)

-1.12

-0.72

V

Head Select Low Voltage (VLHS)

-2.38

-1.51

V

240

Il A

60

IlA

3.7
0.16
1.25

rnA
mA
mA

Write Select Low Current (I LWS)

= VCC
= VCC

- 1.0
+ .3V

Read/ldle, VWS

= 3.8V

Head Select High Current (IHHS)
Head Select Low Current (ILHS)
Total Head Input Current

Sum of all head input currents with IWC
Write, VCT = 3.5V
Read, VCT = O.OV
Idle
2-3

=0

READ MODE
Test Conditions

Parameter

Differential Gain

Yin = ImV p.p, OVDC, f = 300kHz
Tj = 22°C
Tj = O°C
Tj = 110°C

Min.

Max.

Units

28
28
22.2

43
46
43

V/V
V/V
V/V

Common Mode Rejection Ratio

Yin = 100mVpp, OVDC, f-:;: 5MHz

45

dB

Power Supply Rejection Ratio

Yin =OV, f-:;: 5MHz
.:0, VCC or .:0, VEE = 100mVpp

45

dB

Bandwidth

lin = On , Yin = 1mVPP, f midband = 300kHz

30

Input Noise

Yin = OV, lin = On, Power Bandwidth = 15MHz

9.3

t-tVRMS

Input Noise (104L)

Yin = OV, lin = On, Power Bandwidth = 15MHz

6.6

t-tVRMS

Input Current

Yin = OV

26

t-tA

Differential Input Capacitance

Yin = OV

23.5

pF

Differential Input Resistance

Yin = OV
Tj = 22°C
Tj = O°C
Tj = 110°C

585
565
585

915
915
1070

n
n
n

120

mV

-0.78

-0.32

V

40

0.1
45

mA
mA

MHz

Output Offset Voltage

lin = 0

Common Mode Output Voltage

Yin = 0

Unsafe Current

Write Current = OmA
Write Current = -45mA

Dynamic Range

DC input voltage where AC gain falls to
90% of OVDC input value. (Measured with
0.5mVpp AC input, Tj = 30°C

2.0

mVp

Channel Separation

Yin = 1mVpp,OVDC, f = 5MHz
3 channels driven

40

dB

WRITE MODE
Test Conditions

Parameter

Min.

Differential Input Voltage

0.175

Single Ended Input Voltage

-0.68

Current Gain

IWC = -45mA

Write Current Voltage

IWC = -45mA

0.95

IUS = +45mA

Head Center Tap Voltage
Differential Head Voltage

IWC = - 45mA, Lh = 1Ot-tH

Single Ended Head Voltage

IWC = - 45mA, Unselected heads at 3.5V
Selected Side of Selected
Head Current = OmA
= 90mA

Unsafe Current

Unselected Head Current

IWC = -30mA, f = 2M Hz;
Lh = 9t-tH
VUS = 5.0V - 6.3V, Lh = 0
IWC = 45mA, Rh = ooone side of head only

1.0
V
V

3.8

V

5.7

7.2

Vp

0.9
0.0
1.4+VCC 3.7+VCC
15
15
-2.0

2-4

VCC+.3

3.2

IWC = - 45mA, f = 2MHz, Lh = 9.5.uH

DX DY Input Current

V
mA

VEE+025 VEE+ tOV
4

Units

V
-0.45

-45

Write Current

Unsafe Voltage

Max.

V
V

1.0
45
45

mA
mA
mA

2.0

mAp

2.0

mA

.M.Yf.O~.d.R.~.s.tin.,_~~wx
.{icon.~.,
91~5952809

_ _ _ _ _ _ _ _ _ _ _.14.3.5.1

SWITCHING CHARACTERISTICS
Parameter

Test Conditions

Min.

Max.

Units

Idle to Read/Write Transition Time

-

0.5

pS

Read/Write to Idle Transition Time

-

0.5

pS

Read to Write Transition Time

-

0.5

pS

Write to Read Transition Time

-

0.5

pS

Head Select Switching Delay

-

50.0

nS

-

15

nS

-

15

nS

-

2

nS

-

1
5.1

pS
pS

=
=
=

-45mA, Lh

=

-30mA, f

= 0, f = 5MHz
= 0, f = 5MHz
= 0, f = 5MHz

Head Current Transition Time

IWC

Head Current Switching Delay Time

IWC

Head Current Switching Hysterisis

- 45mA, Lh
IWC
Data rise and fall time::;; 1 nSec

Unsafe Switching
Delay Time

IWC

- 45mA, Lh

= 2MHz;

Lh
Lh

= 9pH
= OpH

0.8

HEAD SELECT TABLE

I

Head Selected

HSI

HS2

0
1
2
3

1
0
1
0

1
1
0
0

l

WS _ _ _ _~r--------------------4(~(------------------------~~

DX·DY----....J

r-------4j(r-------.
WC------------------.....I

HS1&2

CE

=-=x'----------1:~:

____><=

L---------------~~rl------------------~r---~~
..J/
\1------1 r--_=-=~=-- _ _...-..J7
~
HEAD OPEN

us _______

NORMAL WRITE

WRITE MODE SYSTEM TIMING

No responsibility is assumed by SSi for use of this product
nor for any infringements of patents and trademarks or other
rights of third parties resulting from its use. No license is

2-5

granted under any patents, patent rights or trademarks of
SSi. SSi reserves the right to make changes in
specifications at any time and without notice.

Thin Film - 4-Channel
Read/Write Circuit
551 114
INTEGRATION

Preliminary Data 5heet
IMF

us

WS

wsvcr~~~~-'~~
RD C,---'--------'
f---,----+-OH01
f--"""'-"--+-OH02

Rllr'-...--'--------'
WD (L---'------J

f---+-{)H11
1--"'''"'-'-+-QH12

WD
HS1
HS2 ~F"---'--'-_---.J

GND

VEE

vwe

CE

WSV

RIW

HS1

HDO

HS2

HDO

WD

HD2

WD

HD2

f-::-:-::--+--U H21
f--"'=':'-+-{) H22

WUS

HD1

IMF

HD1

H31
f--"'=-+-OH32

vee

HD3

RD

HD3

lID

GND

vwe Lr---'-----'
SSI 114 Pin Out
SSI 114 Block Diagram

FEATURES
• Thin film head compatible performance
• Four Read/Write Channels
• TTL - compatible logic levels

• Operates on standard
power supplies

DESCRIPTION
The 881 114 is an integrated read/write circuit designed
for use with non-center tapped thin film heads in disk
drive systems. Each chip controls four heads and has
three modes of operation: read, write, and idle. The circuit contains four channels of read amplifiers and write
drivers and also has an internal write current source.
A current monitor (IMF) output is provided that

2-6

+ 5 volt

and - 5 volt

allows a multichip enable fault to be detected. An
enabled chip's output will produce one unit of current.
An open collector output, write select verify ryv8V), will
go low if the write current source transistor is forward
biased. The circuit operates on + 5 volt, and - 5 volt
power and is available in a 24 pin flatpack.

Thin Film - 4-Channel
Read/Write Circuit
551114
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage, VCC ..................... 6V
Negative Supply Voltage, VEE .................. - 6V
WRITE MODE
Operating Junction Temperature ........ 25 °c to 125°C
In the write mode (RiW and CE low) the circuit func·
Storage Temperature ................ - 65°C to 150°C
tions as a differential current switch. The Head Select
Lead Temperature (Soldering, 10 sec) ........... 260 °c
inputs (HS1 and HS2) determine the selected head. The
Input Voltages
Write Data Inputs (WD, WD) determine the polarity of
Head Select(HS) .............. - O.4V to VCC + 0.3V
the head current. The write current magnitude is
Chip Enable (CE) .............. - 0.4V to VCC + 0.3V
adjustable by an external 1% resistor, Rx from VWC to
Read Select (RIW) ..... - O.4V or - 2mA to VCC + 0.3V
VCC, where
Write Data (WD, WD) ................... VEE to 0.3V
Iw = _______K~w~--~__ -0.7mA
Head Inputs (Read Mode) ........... - 0.6V to + O.4V
Outputs
Rx(1 + Rh + Rh)
Read Data (RD, RD) .............. 0.5V to VCC + 0.3V
Rd
1k
Write Unsafe (WUS), ........... - O.4V to VCC + 0.3V
Where Kw = Current Gain Factor = 130 Amp·Ohms
and 20mA
Rh
Head plus External Wire Resistance
Write Select Verify (WSV) ...... - 0.4V to VCC + 0.3V
Rd = Damping Resistance
and20mA
Current Monitor (IMF) .......... - O.4V to VCC + 0.3V
READ MODE
Current Reference (VWC) ......... VEE to VCC + 0.3V
In the Read Mode, (RiW high and CD low), the circuit
and SmA
functions as a differential amplifier. The amplifier input
Head Outputs (Write Mode) ........ Iw max = 150mA
terminals are determined by the Head Select inputs.
Thermal Characteristics
Flatpack Package .......... eJA = 144 °CIW(stili air)
eJA
30°CIW
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, 4.75 :::;;VCC :::;;5.25,
- 5.5 :::;;VEE :::;; - 4.95V, 25 ° :::;; T aunction) :::;;125°C.
POWER SUPPLY

CIRCUIT DESCRIPTION

=

=

Parameter

Test Conditions

Power Dissipation

All modes, 25 ~Tj :::;;100
100° < Tj <125°C

Min.

Max.

Units

-

612+6.7Iw
563+6.7Iw

mW
mW

Positive Supply Current (ICC)

Idle Mode

-

10+ Iw/19

rnA

Positive Supply Current (ICC)

Read Mode

-

40+ Iw/19

rnA

Positive Supply Current (ICC)

Write Mode

-

3S+ Iw/19

rnA

Negative Supply Current (lEE)

Idle Mode

-12-lw/19

rnA

Negative Supply Current (lEE)

Read Mode

-66-lw/19

Negative Supply Current (lEE)

Write Mode

-75-1.16Iw

Max.

Units

rnA
rnA

LOGIC SIGNALS
Parameter

Test Conditions

Min.

Chip Enable Low Voltage (VLCE)

Read or Write Mode

-

O.S

V

Chip Enable High Voltage (VHCE)

Idle Mode

2.0

Chip Enable Low Current (lLCE)

VLCE

-

rnA

Chip Enable High Current (IHCE)

VHCE = 2.0V

-

Read Select High Voltage (VHRIW)

Read or Idle Mode

2.0

-

Read SelectLow Voltage (VLRIW)

Write or Idle Mode

O.S

V

Read Select High Current (IHRIW)

VHRIW

-

0.015

rnA

Read Select Low Current (ILRIW)

VLRIW

= OV

-1.60

= 2.0V
= OV

-0.3

V
rnA
V

2.0

-

rnA

Head Select High Voltage (VHHS)
Head Select Low Voltage (VLHS)

-

O.S

V

-0.15

2·7

V

HEAD SELECT TABLE
Head Selected

HS1

HS2

0

0

1

1

2
3

0

0
0
1
1

1

LOGIC SIGNALS
Parameter

Test Conditions

Min.

Max.

Units

-

0.25

mA

0.25

mA

Head Select High Current (IHHS)

VHHS = VCC

Head Select Low Current (ILHS)

VLHS = OV

WUS, WSV Low Level Voltage

ILUS = 8mA (denotes safe condition)

-

0.5

V

WUS, WSV High Level Current

VHUS = 5.0V (denotes unsafe condition)

-

100

-0.1

IMF on Current

2.20

3.70

J.!A
mA

1M F off Current

-

0.02

mA

IMF Voltage Range

0

VCC+0.3

V

READ MODE

Tests performed with 100fl load resistors from RD and RD through series isolation diodes to VCC.
Min.

Max.

Units

Differential Voltage Gain

Vin = 1mVpp, f=300kHz

75

170

V/V

Voltage Bandwidth (- 3dB)

Zs < 5Q ,Vin = 1mVpp
f midband = 300kHz

45

-

MHz

-

1.1

nV/1RZ
pF

Parameter

Test Conditions

Input Noise Voltage

Zs = OQ , Vin = OV,
Power Bandwidth = 15MHz

Differential Input Capacitance

Vin = OV, f = 5MHz

-

65

Differential Input Resistance

Vin = OV, f = 5MHz

45

96

Q

Input Bias Current (per side)

Vin = OV

-

0.17

mA

Dynamic Range

DC input voltage where AC gain falls to
90% of the gain with .5mVpp input signal

-3.0

3.0

mV

CMRR

Vin = 100mVpp, OV DC
1MHz '

551117 A Pin Assignments

cs

18

HSO

6S

22

HSO

GND

17

WDI

GND

21

HS1

HOX

20

WDI

11741117R-4

19

VDD1

4 Channels

18

16

VDD1

15

VDD2

HOY

14

VCT

H1Y

Rm

13

H1X

H2X

WC

12

H1Y

11

WUS

10

VCC

NC
HOX

4

117 ·21117 R·2

HOY

4

H1X

2 Channels

H2Y -

8

Riii
RDX

8

RDY

WC

10

RDX

11

18-LEAD PDIP

6S

HSO

GND

HS1

HOX

WDI

HOY

VDD1

VDD2

H1X

VDD2

17

VCT

H1Y

VCT

16

H3X

H2X

H3X

15

H3Y

H2Y

H3Y

14

WUS

Rm

NC

WC

NC

13

VCC

12

RDY

RDX

WUS

RDY

VCC
24-LEAD FLAT PACK

22-LEAD PDIP

HSO

28

HS1

cs

27

HS2

GN

26

WDI

HOX

25

VDD1

24

VDD2

23

VCT

22

H5X

H2X

21

H5Y

H2Y

20

H4X

HOY

117·61117 R·6

H1X

6 Channels

H1Y

:;; <
Cl

:r :r
c.>

H4Y
H4X

l

~

-<

(Jl

c:

Cl

18

17

16

15

JJ

JJ

Z

0

0

Cl

,.

x

13

12

-<

19

11P WC

20

10

PRiii
PH2Y
8 PH2X

H5Y

21

H5X

22

VCT

23

7pH1Y

9

117-6/117 R-6

6 Channels

Rm

10

19

H4Y

VDD2

24

6

PH1X

WC

11

18

H3X

VDD1

25

5

HOY

NC

12

17

H3Y

RDX

13

16

WUS

RDY

14

15

VCC

26

\

27

1

28

2

3

P

0
:r
:;; :r :r :r
(Jl
1,11 Gl
z 0x
!2 fil "! 0
0

28-LEAD PDIP,
FLAT PACK

28-LEAD PLCC (flU AD)

THERMAL CHARACTERISTICS:

eJA

18·LEAD
PDIP

100"C1W

22·LEAD
POIP

gooCIW

24-LEAD
FLAl PACK

6IJ"C1W

28-LEAD
POIP
FLAT PACK
PLCC

TBO
50"C1W

80"C/W

No responsibility is assumed by SSi for use of this product
nor for any infringements of patents and trademarks or other
rights of third parties resulting from its use. No license is

2-21

granted under any patents, patent rights or trademarks of
SSi. SSi reserves the right to make changes in
specifications at any time and without notice.

SSI117A/1l7AR- Series
2, 4, or 6-Channel
Read/Write Circuits

INTEGRATION

Data Sheet
FEATURES
GENERAL DESCRIPTION
T~e SSI 117A devices are bipolar monolithic integrated
circuits designed for use with center-tapped ferrite
recording heads. They provide a low noise read path,
write current control, and data protection circuitry for
as many as six channels. The SSI 117A requires +5V
and + 12V power supplies and is available in 2, 4, or 6
channel versions with a variety of packages.

• + 5V, + 12V power supplies
• Single- or multi·platter Winchester drives
• Designed for center.tapped ferrite heads
• Programmable write current source
• Available in 2, 4, or 6 channels
• Easily multiplexed for larger systems
• Includes write unsafe detection

The SSI 117AR differs from the SSI 117A by having
Internal damping resistors.

• TTL compatible control signals

SSI 117 A Block Diagram

WUS

VDD2

VCT

f-------.(")

HOX

1-------.(") HOY

A/Vi
MODEI ___
SELECTi-

~-JL-~~=====r----------~

f-------..f""'

H1X

f-------.(")

H1Y

1-------.(")

H2X

1--------...('

H2Y

CS
MULTIPLEXER
RDX
RDY

1-------.(") H3X
WDI

1-------..(") H3Y
f-------~ H4X
H4Y

HSO
HS1
HS2

(}------------------------------~----------~

cr---------------------------------+----------~

WC

CAUTION: Use handling procedures necessary
for a static sensitive component

2·22

HSX

HSY

SS1117A/l17AR- Series

2, 4, or 6-Channel ReadjWrite Circuits
Circuit Operation

Any of the following conditions will be indicated asa
high level on the Write Unsafe, WUS, open collector
output.

The SSI 117A functions as a Write driver or as a read
amplifier for the selected head. Head selection and
mode control are described in Tables 2 & 3. Both RiW
and CS have internal pull up resistors to prevent an
accidental write condition.

•
•
•
•
•
•

WRITE MODE
The Write mode configures the SSI 117A as a current
switch and activates the Write Unsafe Detector. Head
current is toggled between the X· and V-side of the
recording head on the falling edges of WDI, Write Data
Input. Note that a preceding read operation initializes
the Write Data Flip Flop, WDFF, to pass current through
the X-side of the head. The magnitude of the write
current, given by

Head open
Head center tap open
WDI frequency too low
Device in Read mode
Device not selected
Nowrite current

After the fault condition is removed, two negative
transitions on WDI are required to clear WUS.
READ MODE

In the Read mode the SSI 117A is configured as a low
noise differential amplifier, the write current source and
the write unsafe detector are deactivated, and the write
data flip flop is set. The RDX and RDV outputs are driven
by emitter followers and are in phase with the "X" and
"V" head ports.

Iw = KlRwc, where K = Write Current Constant
is set by the external resistor, Rwc, connected from pin
WC to GND.

Note that the internal write current source is
deactivated for both the Read and the chip deselect
mode. This eliminates the need for external gating of the
write current source.

TABLE 1: PIN DESCRIPTIONS
Name -

Symbol

Description

HSO - HS2

Head Select: selects up to six heads

CS

Chip Select: a low level enables device

RIW

ReadIWrite: a high level selects Read
mode

WUS

TABLE 2: MODE SELECT
CS

RIW

MODE

a
a

a

Write

1

Read

1

X

Idle

Write Unsafe: a high level indicates an
unsafe writing condition

WDI

Write Data In: a negative transition
toggles the direction of the head
current

HOX- H5X
HOV - H5V

X, V head connections

RDX, RDV

X, V Read Data: differential read signal
out

WC

Write Current: used to set the
magnitude of the write current

VCT

Voltage Center Tap: voltage source for
head center tap

VCC

+5V

VDD1

+12V

VDD2

Positive power supply for the Center
Tap voltage source

GND

Ground

TABLE 3: HEAD SELECT

a=

HS2

HS1

HSO

HEAD

a
a
a
a

a
a

a

a

1

1

1

a

2

1

1

3

1

a

4

1

a
a

1

5

1

1

X

none

Low level
1 = High level
X = Don't care

2-23

ABSOLUTE MAXIMUM RATINGS

(All voltages referenced to GND)

Parameter
DC Supply Voltage

Symbol

Value

Units

VDD1
VDD2
VCC

-0.3to +14
-0.3to +14
-0.3 to +6

VDC
VDC
VDC

Digital Input Voltage Range

Yin

- 0.3 to VCC + 0.3

VDC

Head Port Voltage Range

VH

- 0.3 to VDD + 0.3

VDC

WUS Port Voltage Range

Vwus

-0.3to +14

VDC

Write Current

IW

60

mA

Output Current: RDX, RDY
VCT
WUS

10

-10
-60
+12

mA
mA
mA

Tstg
Tj

-65 to + 150
+ 25 to + 125
260

·C
·C
·C

Value

Units

Storage Temperature Range
Junction Temperature Range
Lead Temperature (10 sec Soldering)
RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol

DC Supply Voltage

VDD1
VDD2
VCC

12 ± 10%
6.5 to VDD1
5 ± 10%

VDC
VDC
VDC

Head Inductance

Lh

5 to 15

Damping Resistor (117A only)

RD

500 to 2000

ftH
ohms

RCT Resistor

RCT

130 ± 5% (1/2 watt)

ohms

Write Cu rrent

IW

25 to 50

mA

RDX, RDY Output Current

10

oto 100

ftA

DC CHARACTERISTICS

Unless otherwise specified VDD1 = 12V ± 10%, VCC = 5V ± 10%,
+ 25·C 
J:
g; fJr z0

J:

~

28-LEAD QUAD

THERMAL CHARACTERISTICS:

eJA

III-LEAD
PDIP

l00"C1W

22-LEAD
PDIP

9O°CfW

2"'L~\D

FLAT PACK

6O"C1W

28-LEAD
PDIP
FLAT PACK
QUAD

80°C/W
TBD
50 0 CIW

No responsibility is assumed by SSi for use of this product
nor for any infringements of patents and trademarks or other
rights of third parties resulting from its use_ No license is

2-27

granted under any patents, patenl,rights or trademarks of
SSL SSi reserves th.e right to make changes in
specifications at any time and without notice_

551188
4-Channel
Read/Write Circuit

INTEGRATION

Preliminary Data Sheet
FEATURES
• Fast switching characteristics
• TTL compatible control Signals
• Four head capacity
• Designed for center-tapped ferrite heads
• Includes write unsafe detection
• Easily multiplexed

GENERAL DESCRIPTION
The SSI 188 is a high-performance, bipolar integrated
read/write circuit for use with center tapped, ferrite
heads. It provides a low noise read path, write control
circuitry and data protection circuitry for 4 channels.
The SSI 188 requires + 6_5 V and - 5_2 V power supplies.
It is available in a 24 pin flat pack.

WITS

VCT

0

<;>

I

I
HS 1

I

I

UNSAFE
CONDITION
DETECTOR

I

I

HSO

I

WC

I

I

DX
DY

A

WRITE
CURRENT
DIVERTER

J
I

I

READ CURRENT
SOURCE

<'

GND

VCT

VEE

22---

H2X

21

H2Y

24

WuS

I

CENTER TAP
DRIVER

MODE
CONTROL

GND'0-

VCC

WC
HEAD
SELECT

~

DIFFERENTIAL
READ
AMPLIFIERS
AND
WRITE
DRIVERS
(4 CHANNELS)

HS1

HOX

HSO

HOY

SS1188

CS==j7

Riw
(Pin 9 must be

left open.)

·8

18

H3X

17

H3Y

N.C.

16

H1X

DX

15

H1Y
VCC

~

HOX

/POST

HOY

24 Lead Ceramic Flat Pack

H1X

Pin Out
(Top View)

H1Y

~

GND

VEE

H2X
H2Y

~>

H3X
H3Y

~ER

Block Diagram

CAUTION: Use handling procedures necessary
for a static sensitive component

2-28

551 188
4-Channel
Read/Write Circuit

Table 1: Pin Descriptions

Circuit Operation
The SSI 188 has 3 selectable modes of operation as
illustrated in Table 2. The RiW and CS inputs which
determine these modes have internal resistor pullups to
prevent an accidental write condition. Depending on the
mode selected, the chip performs as a write gate or read
amplifier for the selected head. Table 3 shows proper
head addressing. In the Idle mode all inputs and outputs
are in a high-impedance state, except the WC pin which
is diverted to GND.

Symbol

Write Mode
In this mode, externally supplied write current is gated
to the "X" side of the chosen head when the DX input is
low and to the "Y" side when DY is low. The write
unsafe detector is activated when the SSI 188 is in the
write mode. A low on the WUS pin indicates one of the
following unsafe conditions:

Name -

Description

HOX-H3X
HOY-H3Y

X, Y head connections

DX,DY

X, Y ReadlWrite Data: differential read
data in/write data out signal

WC

Write Current: External write current
generator connected to this pin

VCT

Voltage Center Tap: voltage source for
head center tap

VCC

+6.5V.

VEE

-5.2V.

GND

Ground

Table 2: Mode Select

• Head open or shorted
• No write current
• No write data transitions
During a normal write cycle the pin is initially low and
then goes high after the differential input makes two
transitions. Two transitions are also needed to clear
WUS after a fault condition.

CS

R/W

MODE

0

0

Write

0

1

Read

1

X

Idle

Table 3: Head Select
Read Mode
The SSI188 amplifies the differential signal on the
addressed head when in the read mode. The amplified
signal is output on the open-collector DX and DY pins,
with a gain dependent on external resistors tied from
each pin to ground. The nominal values listed in this
data sheet were obtained with 50 ohm resistors and can
be doubled by using 100 ohm resistors. Polarity is such
that the DX output is more positive when the "X" side of
the head is more positive. External gating of the write
current source is not necessary because an on-chip
diverter circuit prevents the write current from flowing in
the head circuits during the read and idle modes.

HS1

HSO

HEAD

0

0

0

0

1

1

1

0

2

1

1

3

Temperature Monitoring
Two sets of series diodes are included on the chip for
junction temperature monitoring. Between both the HSO
and HS1 pads to GND, two diodes are connected in
series as shown in the figure below.

Table 1: Pin Descriptions
Symbol

Name -

Description

HSO - HS1

Head Select: selects up to four heads

CS

Chip Select: a low level enables device

R/W

ReadlWrite: a high level selects Read
mode

WUS

Write Unsafe: open collector output,
low indicates unsafe condition

Hsoo--------1-----f----l
HEAD
SELECT

HS1o---------r-----~

2-29

____J

To calibrate the diodes remove power from the SSI 188,
pull down on the HSO or HS1 pin with a constant current
and measure the diode forward bias voltage as the
temperature is varied. To monitor temperature measure
the diode forward bias voltage in either read or write

mode and compare to the previously determined
calibration curve.
Applications
These circuits are suggested for interfacing the
differential DX and DY lines and either ECl or TTL data.

VEE

VEE

50U

RE
RE

1---

r---l

"'=$

OX

50U

I

(3/5) CA3127E

Ox

ECl
Write
Date

Write

I

oa~

R/W-

l

I

5011

Oy

L ___ .JI
(112) MC10113

Oy

50n

RE

VEE

-

VEE

VCT

VEE

-

(%) SN7511Q

1-------1
I

TTL

50n

I

Ox

I

Write Data

Oy

I
I

RNJ

50U

L ______ .-J

-

Absolute Maximum Ratings'

(All voltages referenced to GND)

DC Supply Voltages (VCC) ................... 7.5 V DC
(VEE) ................. -6.0VDC
Digital Input Voltage Range ..... - 0.3to VCC + 0.3 V DC
Head Input (Read Mode) .............. - 0.6 to 0.4 V DC
Head Select (HSO, HS1) ............. - 0.4 V (or - 2mA)
toVCC + 0.3 V DC
WUS Port Voltage Range ........ - 0.4 to VCC + 0.3 V DC
Write Current(lw) .......................... - 80 mA

Output Currents (VCT) ...................... - 80 mA
(WUS) ....................... 10mA
DX, DY Voltage ................... - 0.1 to + 0.3 V DC
Differential VoltagelVR/W - VCSI ............ 6.5 V DC
Storage Temperature Range (T5tg) ...... - 65 to + 150 'C
Junction Temperature Range (Tj) . : ..... + 25 to + 125 'C
lead Temperature (10 sec soldering) ............ 260 'C
*Operation above these ratings may cause permanent damage to the

device.

2-30

Recommended Operating Conditions

DC Supply Voltage

VCC
VEE

6.5 ± 5%
-5.2 ± 5%

Head Inductance

lh

1.5t015

H

Write Current

Iw

35 to 70

mA

DC Characteristics

VDC

Unless otherwise specified: VCC = 6.5 ± 5%, VEE = - 5.2 ± 5 %, + 25°C:J---------i----------~HSO

HSl

r======t~==~~-~X)·-------~----------IHS2

~A~;E

WDI
RDX

READ
DATA

ROY

H3Y
H4X
H4Y
H5X
H5Y
H6X
H6Y

RWC
WC
Note 1: An external 1/2 watt resistor, RCT, given by:
RCT

=

GND

120 (50ftw) ohms, where Iw IS in rnA can be used to limit

H7X
H7Y

internal power dissipation. Otherwise connect VDD2 to VDD1.

Note 2: A ferrite bead (Ferroxcube 5659065/4A6) can be used to suppress write current overshoot and ringing induced by flex cable parasitics.
Note 3: Umit DC current from RDX and ROY to 100uA and load capacitance to 20pF.
Note 4; Damping resistors reqUired on SSt 501 only.

2-38

JifkonCA.: ~.Jl71.4.).7rsfcmJ'
.31.-7.1 .0.,T.W.X.9.1.0-.5.95.-.28.0.9

____________________1.4.35.1.M.y.fo.rd.R.o.a.d,.T.us.ti.n,. .

______________________

551 501/501R Pin Assignments

KEY , - - - - - - - ,
HOX

32

GNO

HOY

31

MUST REMAIN OPEN

H1X

30

Cs

HW

29

RN>!

H2X

28

WC

27

ROY

26

ROX

25

HSO

H2Y
H3X

501-8/501 A-a

H3Y

8 Channels

24

HS1

H4Y

10

23

HS2

H5X

11

22

VCC

H4X

HOX

40

GNO

HOX

28

GNO

HOY

39 _

MUST REMAIN OPEN

HOY

27

MUST REMAIN OPEN

NC

38

NC

H1X

26

NC

37

NC

25

RIW

36

cs

HW

H1X

24

WC

HW

35

RIW

H2Y

H2X

34

WC

H3X

501-61501R-6
6 Channels 23
22

H2Y

33

ROY

H3Y

21

HSO

32

ROX

H4X

20

HS1

31

HSO

H4Y

10

19

HS2

30

HS1

H5X

11

18

VCC

H.'3X
H3Y

H5Y

12

21

WOI

H6X

13

20

WUS

H6Y

14

19

VDD1

H7X

15

18

VDD2

H7Y

16

17

VCT

32-PIN FLAT PACK

H2X

cs

10

501-BI501A-8

ROY
ROX

H4X

11

H4Y

12

29

HS2

H5Y

12

17

WDI

H5X

13

28

VCC

VCT

13

16

WUS

H5Y

14

27

WOI

V002

14

15

V001

H6X

15

26

WUS

H6Y

16

25

NC

NC

17

24

NC

8 Channels

NC

18

23

VDD1

H7X

19

22

VD02

H7Y

20

21

VCT

28-LEAD COIP, PDIP

THERMAL CHARACTERISTICS:

eJA

4O·LEAD CDIP, PDIP
28-LEAD
COIP

PLCC

52°CfW
80'CfIN
50°CfW

32·LEAD

FLAT PACK

5QOCIW

40·LEAO

COIP

45°CfW

Note: NIC pins have no external connection

POIP

~ 6 6 6 6
28
WUS

27

<

<

S§

26 25 24 23 22

~ ~ ~ 6
21

20 19 18

29

17

NC

WOI

30

16

H6Y

VCC

31

15

H6X

HS2

32

14

H5Y

HS1

33

13

H5X

HSO

34

12

H4Y

11

H4X

10

H3Y

44·LEAD

18
ROX

35

ROY

36

WC

501-81501R-8
8 Channels

37

H3X

ROX

38

H2Y

ROY

H2X

wc

43

44

1

2

3

4

5

6

<
<
00<
~ 2 ~

::r
~

15

12

14

13

11

H5X
H4Y

HSO

39
42

45"CfIN

HS1

NC

41

16

70'CfIN

PLCC

HS2

RIW

40

17

PDIP

501-6/501 R-fi
6 Channels

H4X
H3Y
H3X
H2Y
H2X

RIW
262728123

6 6

QI [ ~ ~ ~

o

6 6 ~ ~

fhl~~~~~~

ffi'

:0

3

~

w
3·

i

44-LEAD PLCC (OUAD)

28-LEAD PLCC (OUAD)

3

o

~

Notes: All views are from top.
NC pins have no internal connection.

No responsibility is assumed by SSi for use of this product
nor for any infringements of patents and trademarks or other
rights of third parties resulting from its use. No license is

2-39

granted under any patents, patent rights or trademarks of
SSi. SSi reserves the right to make changes in
specifications at anytime and without notice.

SS1510/510R
4-Channel
Read/Write Circuits

INTEGRATION

Preliminary Data Sheet
FEATURES
• + 5V, + 12V power supplies

GENERAL DESCRIPTION
The 551 510 devices are bipolar monolithic integrated
circuits designed for use with center-tapped ferrite
re~ording heads. They provide a low noise read path,
write current control, and data protection circuitry for
as many as four channels. The 551 510 requires + 5V
and + 12V power supplies and is available in a variety
of packages.

•
•
•
•

Single- or multi-platter Winchester drives
Designed for center.tapped ferrite heads
Programmable write current source
Easily multiplexed for larger systems

• Includes write unsafe detection
• TTL compatible control signals

The 551 510R differs from the SSI 510 by having internal
damping resistors.

551510 Block Diagram

WUS

VDD2

VCT

HOX

R/W
MODEl__
SELECT

-:==r===~~~3F======~--~

HOY

/--------n H1X
MULTIPLEXER / - - - - - - - . . (

RDXLr------------~~+---~

H1Y

j--------n H2X

RDYcr------------~~+-~,

/--------n

H2Y

1--------" H3X

WDlcr----------------+---~

H3Y

H~cr----------------------------~--------~
(}------------------------------~----------~

HS1

WC

CAUTION: Use handling procedures necessary
for a static senslHve component

2-40

SSI510j510R
4-Channel Read/Write Circuits
Circuit Operation

Any of the following conditions will be indicated asa
high level on the Write Unsafe, WUS, open collector
output.

The SSI 510 functions as a write driver or as a read
amplifier for the selected head. Head selection and
mode control are described in Tables 2 & 3. Both RiW
and CS have internal pull up resistors to prevent an
accidental write condition.
WRITE MODE
The Write mode configures the SSI 510 as a current
switch and activates the Write Unsafe Detector. Head
current is toggled between the X· and V-side of the
recording head on the falling edges of WDI, Write Data
Input. Note that a preceding read operation initializes
the Write Data Flip Flop, WDFF, to pass current through
the X-side of the head. The magnitude of the write
current, given by
Iw = K/Rwc, where K = Write Current Constant
is set by the external resistor, Rwc, connected from pin
WCto GND.

•
•
•
•
•
•

Head open
Head center tap open
WOI frequency too low
Oevice in Read mode
Oevice not selected
No write current

After the fault condition is removed, two negative
transitions on WOI are required to clear WUS.
READ MODE
In the Read mode the SSI 510 is configured as a low
noise differential amplifier, the write current source and
the write unsafe detector are deactivated, and the write
data flip flop is set. The RDX and RDV outputs are driven
by emitter followers and are in phase with the "X" and
"V" head ports. They should be AC coupled to load.
Note that the internal write current source is
deactivated for both the Read and the chi p deselect
mode. This eliminates the need for external gating of the
write current source.

A Voltage Fault detection circuit assures Data Security
by preventing application of Write Current during power
sequencing or power loss.
TABLE 1: PIN DESCRIPTIONS
Symbol

Name -

Description

HSO - HS1

Head Select

CS

Chip Select: a low level enables device

RIW

ReadIWrite: a high level selects Read
mode

CS

RIW

MODE

0

0

Write

Write Unsafe: a high level indicates an
unsafe writing condition

0

1

Read

1

X

Idle

WUS
WOI

Write Data In: a negative transition
toggles the direction of the head
current

HOX- H3X
HOV - H3V

X, V head connections

ROX, ROV

TABLE 2: MODE SELECT

TABLE 3: HEAD SELECT

X, V Read Data: differential read signal
out

WC

Write Current: used to set the
magnitude of the write current

VCT

Voltage Center Tap: voltage source for
head center tap

VCC

+5V

VDD1

+12V

VDD2

Positive power supply for the Center
Tap voltage source

GND

Ground

HS1

HSO

HEAD

0

0

0

0

1

1

1

0

2

1

1

3

0= Low level
1 = High level
X = Oon't care

2-41

ABSOLUTE MAXIMUM RATINGS

(All voltages referenced to GND)
Symbol

Value

Units

VDD1
VDD2
VCC

-0.3to +14
-0.3 to + 14
-0.3 to +6

VDC
VDC
VDC

Yin

- 0.3 to VCC + 0.3

VDC

Head Port Voltage Range

VH

- 0.3 to VDD + 0.3

VDC

WUS Port Voltage Range

Vwus

-0.3 to + 14

VDC

Write Current

IW

60

mA

Output Current: RDX, RDY
VCT
WUS

10

-10
-60
+12

mA
mA
mA

Tstg
Tj

-65to+150
+25to +125
260

°c
°c
°c

Symbol

Value

Units

VDD1
VCC

12 ± 10%
5 ± 10%

VDC
VDC

Parameter
DC Supply Voltage

Digital Input Voltage Range

Storage Temperature Range
Junction Temperature Range
Lead Temperature (10 sec Soldering)

RECOMMENDED OPERATING CONDITIONS
Parameter
DC Supply Voltage
Head Inductance

Lh

5 t015

fLH

Damping Resistor (510 Only)

RD

500 to 2000

ohms

RCT Resistor

RCT

160 ± 5% (1/2 watt)

ohms

Write Current

IW

10 to 35

mA

DC CHARACTERISTICS

Unless otherwise specified VDD1 = 12V ± 10%, VCC = 5V ± 10%,
+25°C  (Vee-VEE) = ±10%, RL = 130n
TA = 25°C to 70°C, RL = 130n

eMRR, Input Referred

f.s.5MHz

Output Offset (Differential)

Min.

Typ.

Max.

77

93

110

10

20

-

800

Units

MHz

1000

1250

n

-

3

-

pF

3

-

-

mVpp

26
30
35

35
40
45

mA

-

-

600

mV

-

8

14

/-IV

50

65

-

dB

-

±1.3

-

%

-

-0.2

-

%/e

55

70

-

dB

Recommended Operating Conditions

Min.

Type

Max.

Units

Supply Voltage (Vee-VEE)

7.45
9.0
10.8

8.3
10.0
12.0

9.15
11.0
13.2

V
V
V

Equivalent Input Noise
PSRR, Input Referred
Gain Sensitivity (Supply)

101A-2 only
Input Signal Vi

-

2

-

mVpp

Ambient Temp. T A

0

-

70

e

2-55

Jifuon Jl rJkmJ"

551 116
Differential
Amplifier

INTEGRATION

Data Sheet
GENERAL DESCRIPTION
The SSI 116 is a high performance differential amplifier
applicable for use as a preamplifier for the magnetic
servo thin film head in Winchester disk drives.

NC

10

H

INPUT1(+)

SEE NOTE 1

INPUT 21-)

Vcc

SEE NOTE 1

OUTPUT 2 1-)

NC

SEE NOTE 1

INPUT 1 1+)

INPUT 2

FEATURES
• Narrow gain range
• 50MHz bandwidth
• IBM 3370/3380·compatible performance
• Operates on either IBM·compatible voltages (8.3V) or
OEM·compatible (10V)
• Packages include 8·pin CERDIP or Plastic DIP and
custom 10'pin flatpack.
• 551 116-2 available to operate with a 12V power
supply

vcc

SEE NOTE 1

OUTPUT 2

H

OUTPUT 1 1+)

VEE

VEE

Flat Pack

551116 Pin Configuration
(Top View)

5

4

OUTPUT '1+)

Cerdip
Plastic Dip

NOTE 1: Pin must be left open and
not connected to any circuit etch.

Connection Diagram
Vcc

17

r-------~

5

~~E~_
VVY
JL

~~------*-----~--~I

HEAD

~--------------~--~~
Icc
•..

~

2-56

Recommended Load Conditions
1. Input must be AC coupled
2. Cc's are AC coupling capacitors
3. RL's are DC bias and termination resistors, 100 D.
recommended
4. REO. represents equivalent load resistance
5. Ceramic capacitors (0.1 /IF) are recommended for
good power supply noise filtering

Jifuon
Jl rJfcmJ_Tu_s_tln_'_CA~~714)

Yf_o_rd_R_o_Od_,
_ _ _ _ _ _ _ _ _ _ _ _14_3_5_1_M_

731-7110, TWX 910-595-2809

Absolute Maximum Ratings
Power Supply Voltage (VCC-VEE) ................................. 12V
SSI 116-2 ................................... 14V
Operating Power Supply Range ..................... 7.9V to 10.5V
SSI 116-2 ..................... 7.9V to 13.2V
Differential Input Voltage .......................................... ± 1V

Storage Temperature Range ................... -65°C to 150 °C
Operating Ambient Temperature (TA) .......... 15 °C to 60°C
Operating Junction Temperature (TJ) .......... 15 °C to 125°C
Output Voltage ............................ VCC-2.0V to VCC +OAV

ELECTRICAL CHARACTERISTICS Tj = 15°C to 125°C (VCC-VEE) = 7.9V to 105V (to 132V for 116-2)
Test Conditions

Min.

Typ.

Max.

Unit

Gain (Differential)

Parameter

Yin = 1mVpp, TA= 25°C, F = 1MHz

200

250

310

mV/mV

Bandwidth (3dB)

Yin = 1mVpp, CL = 15pF

20

50

-

Gain Sensitivity (Supply)

-

1.0

%/V

15 OC < T A < 55°C

-

-

Gain Sensitivity (Temp.)

-0.16

-

%/C

MHz

Input Referred, RS = 0

-

0.7

0.94

nVJjHZ

I nput Capacitance
(Differential)

Yin = 0, f = 5MHz

-

40

60

pF

I nput Resistance
(Differential)

-

-

200

-

Common Mode Rejection
Ratio Input Referred

Yin = 100mVpp, f = 1MHz

60

70

Input Signal Level

Common Mode

-

-

Power Supply Rejection
Ratio Input Referred

Vee + 100mVpp, f = 1MHz

46

52

Input Dynamic Range
(Differential

DC input voltage where AC gain is
90% of gain with 0.2mVpp input signal

-

-

Output Offset Voltage
(Differential)

Yin = 0

Output Voltage
(Common Mode)

Inputs shorted together and
Outputs shorted together

Single Ended Output
Resistance
Single Ended Output
Capacitance

Input Noise Voltage

-600

300

-

-

n
dB
mVpp
dB

±0.75

mV

600

mV
V

Vcc-0.45

Vec-0.6

VCC-1.0

-

10

-

-

-

-

-

10

pF

28
29
39

40
42
50

mA

VEE+2.6

-

Power Supply Current

VCC-VEE = 9.15V
VCC-VEE = 11V
VCC-VEE = 13.2V

Input DC Voltage

Common Mode

Input Resistance

Common Mode

116-2 only

80

n

V

n

Recommended Operating Conditions

Min.

Type

Max.

Units

Supply Voltage (VCC-VEE)

7.45
9.0
10.8

8.3
10.0
12.0

9.15
11.0
13.2

V
V
V

116-2 only
Input Signal Yin

-

1

-

Ambient Temp. TA

15

-

65

2-57

mVpp
°C

SSI531
Data Separator and
Write Precompensation
Circuit

INNOVATORS IN INTEGRATION

Preliminary Data Sheet
GENERAL DESCRIPTION

FEATURES

The SSI 531 Data Separator performs data synchronization and write precompensation of encoded data. The
interface of the SSI 531 is optimum for use with Western
Digital's WD1010IWD2010 controller family.

• MFM & RLL Data Synchronization.
• Optimized for use with the WD1010/WD2010
controller family.
• Fast acquisition Phase Locked Loop.
• 1F detection.
• Write precompensation.
• Write data resynchronized for reduced jitter.
• No external delay line or varactor diode required.
• Single +5V power supply.

The SSI 531 contains a high performance Phase Locked
Loop for read data synchronization, a crystal controlled
reference oscillator for write data synchronization, and
write precompensation circuitry.
The SSI 531 employs an advanced bipolar technology
which affords precise bit cell control without the need for
external active components.
The SSI 531 requires a single +5V power supply and is
available in 24-pin DIP and 28-pin PLCC packages.

SSI 531 Block Diagram

ROC

ENCODED
READ DATA

READ
CLOCK

vcca+--

I
GNDOJ--l

I

CONTROL
LOGIC

-=-

C~~~Tt.L f---<~-......- - - - - t

)I----l

MFM WRITE
DATA

PRECOMP
ENABLE

1-----------------~J~L~6~

N/2
DIV

LATOR

}7-------_e.jRE.SYNCH

EARLY
LATE

SYNCH
READ DATA

SYNCHRONIZER

0,----1

+_---'

~~~T 1-_ _ _ _ _ _ _ _ _

01-----1

I1.- _ _ _ _ _ _ _

_

I
I

COMP
WRITE DATA

_ _ _ _ _ _ _ _ _ _ _ JI
PRECOMP SET

CAUTION: Usa handling procedures necessary
for a static sensitive component

2-58

551 5 3 1 .
.
Data Separator and Write Precompensation Circuit
CIRCUIT DESCRIPTION

is dependent on the initial phase error on switching (max
is 0.5 rad.) as well as the damping factor and natural
frequency of the lOop. The lower two waveforms are an
expansion of the ENCODED READ DATA and VCO IN
signals showing the effect of disabling the VCO during
reference switching and the subsequent stairstep
characteristic of the VCO waveform as the PLL locks to
the new input.

Data Synchronization

Re~d Data synchronization is accomplished with a high
performance, fast acquisition Phase Locked Loop (PLL).
The input from the disk drive, ENCODED READ DATA, is
phase locked with the VCO clock. The synchronized
Read Data and the VCO clock divided by two are made
available for external data extraction at the SYNCH READ
DATA and READ CLOCK pins respectively.

The synchronizer circuit separates the data and clock
pulses using windOWS derived from the VCO output. The
window edges are aligned with the oppOSite edge from
that used to phase lock the VCO. Using a VCO running
at twice the expected input frequency allows accurate
centering of these windows about the expected bit
positions.

The synchronized Read Data is synchronized in a jitterfree manner such that leading edge transitions occur at
the center of READ CLOCK half cycles. This is accomplished by internally decoding and re-encoding using
the READ CLOCK as a reference.
When READ GATE changes state, the VCO is stopped
and restarted in phase with the PLL input which can be
either the internal Crystal Oscillator or ENCODED READ
DATA. In this manner the lock time is reduced due
to small angles of phase error. Limiting the phase error
by restarting the VCO in phase with the input prevents
the PLL from locking to harmonics and short lock times
are assured. The correct phase of READ CLOCK is also
ensured by resetting the N/2 Divider at the same time as
the VCO restart.

1F Data Detection
The 531 provides a flag, 1F DETECT, that indicates a
continuous stream of "1's" or "D's".
The period of the 1F Detect Retriggerable One-Shot is set
so that the sum of the 1/4 Cell Delay and the. One-Shot is
nominally 1-114 times the 2F frequency data period. This
results in the 1F DETECT output remaining high during a
continuous high frequency input representing a field of
"1's" and "D's". External components R1F and C1F at
the 1F DETECT SET pin are used to set the One-Shot
delay.

When READ GATE is high, the 1/4 CELL DELAY allows
the Phase Detector to be enabled prior to when an
edge of the encoded input is to occur. This updates the
PLL on a sampled basis and corrects for any phase error
with each subsequent input pulse. When READ GATE is
low the Phase Detector is continuously enabled and the
PLL is both phase and frequency locked to the reference
oscillator. By locking the VCO to the reference oscillator it
is virtually at the correct frequency when the PLL is
switched to track ENCODED READ DATA.

A Latch operates in conjunction with the One-Shot to
guarantee a minimum 1F DETECT output pulse width of
one data period.
Write Precompensation
Write precompensation reduces the effect of intersymbol
interference caused by magnetic transition proximity in
the disk media. Compensation consists of shifting written
data pulses in time to counteract the read back bit
shifting caused by such interaction. The severity of the
intersymbol interference is a function of radial velocity of
the media, the magnitude of the write pulse and the data
pattern. Typically, write precompensation is enabled at the
same time as the write current level is reduced.

The following waveforms area graphic representation of
the PLL alternately locking to ENCODED READ DATA
and the Crystal Oscillator.
Encoded
Read Data

Read Gate

veo In
Encoded
Read Data

veo In

XX

L~L.~_-_-_-_-__ _ _ _ _ _ __

The COMP WRITE DATA output is are-synchronized
version of the MFM WRITE DATA input that has been
time shifted, if needed, to reduce intersymbol interference.
Re-synchronization, to the internal crystal oscillator, is
performed to minimize bit jitter in the output waveform.
The magnitude of the time shift, TC, is determined by the
RC network at the PRECOMP SET pin and is applied as
noted in Table 1 according to the states of EARLY, LATE
and PRECOMP ENABLE. Figure 2 is a further illustration
of these timing relationships.

..J
I
I

~I }

Expanded Scate

~
i

With an ENCODED READ DATA input of 5 MHz, the final
DC level of the VCO waveform is constant as shown with
transients occurring at each edge of the READ GATE.
The amplitude and duration of the VCO locking transient
2-59

Table 1: Write Precompensation Truth Table

Pin Name

[

Description

Output Pins (cont)

PRECOMP
Enable

--EARI,.Y

LATE·

0

X

X

1

0

0

1

0

1

TN-TC

1

1

0

TN+TC

1

1

1

TN

Delay
Constant
Illegal State

CaMP WRITE
DATA

Re-synchronized and precompensated write data.

READ CLOCK

Voltage-controlled oscillator output
divided by two. SYNC READ DATA
is synchronized to this signal.

SYNC READ
DATA

Synchronized read data output.
Leading-edge transitions occur at
center of READ CLOCK half
cycles.

1F DETECT

Flag used to locate strings of
MFM-encoded 1's or O's in the
ENCODED READ DATA input.

TN=Nomlnal Pulse Delay
TC=Magnitude of Time Shift
Reference Oscillator
The crystal controlled oscillator serves as the system
master clock for the write functions. Its frequency divided
by two provides a WRITE CLOCK for an external MFM
encoder. It is also used to re-synchronize the MFM
WRITE DATA for precise timing control when writing data
to the disk. A series resonant crystal should be used.

XTAL1, XTAL2

Additionally, the oscillator output is used as a standby
reference for the PLL when READ GATE is low. This
enables the PLL to lock rapidly to incoming data when
required.

Connections for oscillator crystal.
If oscillator is not required, XTAL1
may be driven by TTL logic signal
at twice the data rate and XTAL2
left open.

PRECOMP SET

Pin for R-C network to control
write precompensation early and
late times.

When an external system clock, is available it may be
connected to XTAL1 and XTAL2 should be left open.

1F DETECT SET

Pin for R-C network to control the
1F detect period. Component
values are dependent on the
minimum data period that will
keep 1F DETECT high.

1/4 CELL DELAY
SET

Pin for R-C network to control the
1/4 CELL DELAY. This allows the
Phase Detector to be enabled 1/4
of the data period prior to receiving an MFM data input.

Pin Name

External Component Connection Pins

Description

Input Pins
MFM WRITE
DATA

Write data to be resynchronized
and precompensated. Synchronous with WRITE CLOCK.

PRECOMP
ENABLE

Enables precompensation to be
controlled by -EARLY or -LATE.

EARLY

When low causes the MFM
WRITE DATA pulses to be written
early.

CF1, CF2

Pins for the capaCitor used in conjunction with RF and RS to set the
VCO center frequency.

LATE

When low causes the MFM
WRITE DATA pulses to be written
late.

RF, RS

Pin for resistors used in conjunction with capaCitor to set the VCO
center frequency.

ENCODED
READ DATA

MFM encoded read data pulses
from the read amplifier circuits.

PD OUT

Output of phase detector, input to
loop filter

READ GATE

Selects the reference input to the
PLL. Selects ENCODED READ
DATA when high, crystal oscillator
when low.

VCO IN

Control input of the VCO, for connection of the loop filter output.

VCC

+5V

GND

Power and signal ground
connection.

Absolute Maximum Ratings'
Characteristics
Rating
Storage Temperature ............... -65°C to + 1300C
Ambient Operating Temperature, TA ....... O°C to +70OC
Junction Operating Temperature ......... OOC to + 130°C
Supply Voltage, VCC ............. -0.5 Vdc to +7.0 Vdc
Voltage Applied to Logic Inputs -0.5 Vdc to VCC +0.5 Vdc
Maximum Power Dissipation ................. 800 mW

Output Pins
WRITE CLOCK

Crystal-controlled reference
oscillator frequency divided by
two. Used by the controller to
generate MFM WRITE DATA.

'Operation above the absolute max, min ratings may damage the device.

2-60

551531
Data Separator and Write Precompensation Circuit
Electrical Characteristics
DC Characteristics

Unless otherwise specified 4.75V 

z

0
0
m

0

'1

<:

(f)

:n

--<

l>

ill

m

0

m
0
0

m

z

0

0

0

5
()

'"

~

28-Lead PLCC (Quad) Pin Out

The "PRELIMINARY" designation on an SSi data sheet indicates that the

infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent
rights or trademarks of SSi. SSi reserves the right to make changes in

product is not yet released for production. The specifications are subject to
change, are based on design goals or preliminary part evaluation, and are
not guaranteed. SSi should be consulted for current information before using this product. No responsibility is assumed by SSi for its use; nor fer any

specifications at any time and without notice.

2-65

JhJl rsfonf'

551 540 Series
Read Data Processor

INTEGRATION

Preliminary Data 5heet
GENERAL DESCRIPTION

of a differential line-driver output. The SSI 540-4 has the
same features as the SSI 540-3 but also deletes the head
select buffers. The SSI 540-4 is available in a 22-Pin dip.

The SSI 540 is a bipolar integrated circuit that provides
all data processing necessary for detection and
qualification of MFM read signals from rigid media.
ST506 compatible interfacing is provided for write data
signals, head select lines and recovered read data as
applicable.

When used with a read/write preamplifier (Le. SSI117 or
SSI 501), the SSI 540 or SSI 540-2 and required external
passive components perform all read/write signal processing necessary between the heads and the interface
connector of an ST506 compatible Winchester disk
drive. With the SSI 540-3 and SSI 540-4 a line driver
is required.

In read mode the SSI 540 provides amplification,
differentiation and time domain qualification of head
preamplifier outputs. The recovered data is available at
the output of a differential line driver that conforms to
the ST506 interface specification. In write mode the SSI
540 provides a differential line receiver conforming with
ST506 requirements. Schmitt Trigger inputs on head
select lines and an open collector output for voltage
fault indication are provided for interface compatibility.
All other logic inputs and outputs are TTL compatible.

FEATURES
• Differential Read and Write Ports
• Schmitt Trigger Head Select Inputs for Higher Noise
Immunity
• Programmable Gain
• Time Domain Pulse Qualification Supports MFM
Encoded Data Retrieval
• Supply Voltage Fault Detection
• + 12 Volt and + 5 Volt Power Supplies
• I/O Meets ST506 Requirements
• Dual-In-Line and Surface Mount Packages Available
• Adjustible Time Domain Filter and Output Pulse Width
Settings

The SSI 540-2 is a dual ground version for use in noisier
environments. In order to provide this feature the
number of head select lines is reduced to 2.
Two other versions of the SSI 540 are available that offer
subsets of the above configurations. The SSI 540-3 has
dual grounds and an open-collector RD output instead

SS1 540-1, -2, -3 Block Diagram

I. - - - - ~

.-S)_

'L GN"Q:.:.:'_ - - I
551 540-4 Block Diagram

V~~~~~E

SSIS4O, -2, -3

1

,-----~~CL.'Q-'Q....----l

>t-----------~~HOO'

VFLTEI~

+-------------~~H'"
..A II .......

I

SSl540-4

jHS2B,snolavaliableon54Q.2)

H"O>t----...:..=...:c.c'-'=~-~~"'"

CAUTION: Usa handling procedu.... nece..ary
for a static sensitive component

2-66

1

551 540 Series
Read Data Processor
Circuit Operation

The Differentiator output is AC coupled into a zerocrossing detector that provides an output level
change at each positive or negative zero transition on
its input. The zero-crossing detector output is coupled to
a Time Domain Filter that eliminates false triggering of
the output one-shot by spurious zero-crossings. The
validity decision is based on a minimum duration between zero crOSSings that can be set externally by an RC
network on the TO pin.

In both read and write modes, Schmitt Trigger inputs are
used to buffer the three head select lines providing the
increased noise immunity required of a ST506 interface.
A power supply monitoring function, VFLTB, is provided
to flag a low voltage fault condition if either supply is
low. A low voltage fault condition results in a low level
output on the VFL1'B pin.
READ MODE

The output of the Time Domain Filter triggers a one-shot
that defines the output pulsewidth based on an external
RC network on the PW pin. These output pulses are fed
into a line driver that provides a high-current differential
output at RD + and RD -, or are made available as an
open-collector output at RD +.

In the read mode (MODE input high) the read signal is
detected, time domain qualified and made available at
RD + and RD - as differential MFM encoded data, or at
the RD + open collector output. This is accomplished by
the on·board Amplifier, Dlfferentiator, Zero CrOSSing
Detector, Time Domain Filter, Output One Shot and Line
Driver circuits.

Write Mode

The amplified and filtered read back signal, which con·
tains pulses corresponding to magnetic transitions in
the media is AC coupled into the input amplifier. A
resistor, Rg, connected between pins G + and G - is
used to adjust the 1st stage amplifier gain according
to the following expression.
680
17

+

Where Rx =
Rx

In the write mode (MODE input low) the differential line
receiver is enabled. This receiver accepts the differential
data from the ST506 interface and outputs a TTL signal
for the write data input of an external RIW amplifier. A
low on the MODE input also puts the read outputs in a
high impedance state, allowing several 540's tC1be
multiplexed on a bus.

94 x (Rg + 42)
230 + Rg

Layout Considerations
The SSI 540 is a high gain wide bandwidth device thatrequires care in layout. The designer should keep analog
signal lines as short as possible and balanced. Analog
test pOints should be provided with a probe ground in
the immediate vicinity. Do not run digital signals under
the chip or next to analog inputs. Use of a ground plane
is recommended along with supply bypassing and
separation of the SSI 540 ground from other circuits on
the disk drive PCB.

First stage gain can be monitored at the DIF + and
DIF - pins.
The amplifier is followed by an active differentiator
whose external network serves to transform peaks in the
input signal into zero-crossings while maintaining the
time relationship of the original input peaks. Differentiator response is set by an external capacitor or more
complex series LRC network between the DIF + and
DIF - pins. The transfer function with such a network is:

AV2 =
where:

Cex
Rex
Lex
s

Absolute Maximum Ratings·
5VSupplyVoltage, Vcc ... ...................... . 6V
12VSupplyVoltage, Vdd . ....................... 14 V
Storage Temperature ................ - 65 to + 150 DC
Operating Temperature, Tj ............ + 25 to + 135 DC
Lead Temperature (soldering 10 sec) ............ 260 DC
Pin Voltages
IN + ,IN -,G+,G- ,DIF +,DIF -,
OUT + ,OUT - ,DIN + DIN - ...... 0.3V to Vdd + 0.3V
RD + ,RD - ,WRTOUT,HSO,
HS1,HS2,VFLTB ..... -0.3VtoVcc + 0.3Vor 100 mA
TD,PW,MODE,WRT + ,WRT -,
HSOB,HS1B,HS2B ........... -0.3VtoVcc+0.3V

- 1420 Cex s
LexCex s' + (Rex + 46) Cex s + 1
=
=
=
=

external capacitor (50 pf to 250 pf)
external resistor
external inductor
jw = j27rf

Total gain from IN + and IN - to OUT + and OUT - is:
Av= Av, x Av,
To reduce pulse pairing (bit shift), it is essential that the
input to the zero-crossing detector be maximized to
reduce the effect of any comparator offset. This means
thaUhe above gains should be chosen such that the
differential voltage at OUT + and OUT - approaches
5 Vpp at max input and frequency.

'Operation above absolute maximum ratings may
damage the device.

2-67

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, 4.5V< Vee < 5.5V, 10.8V 5k.n AC coupled (i.e. no DC current).
Test Conditions

Parameter

IMin. I Max.

Units

Amplifier & Active Differentiator
Differential
Voltage Gain (IN ± to OUT ±)
Bandwidth

Rg = "" ,Rex = 800n

7.2

12.6

VIV

Rg = On , Rex = 200n

72

155

VIV

-3dB point

30

-

MHz

Common Mode
Input Impedance ('IN ±)

3.5 typ

kn

6.0 typ

k.o.

Differential Input
Resistance (IN ±)

V(IN + - IN -) = 100mVpp,
2.5 MHz, AC coupled

Differential Input
Capacitance (IN ±)

V(IN + - IN -) = 100mVpp,
2.5 Mhz, AC coupled

-

8

pf

Input Noise (IN ±)

Inputs shorted together
Rg =On , Rex = 200n

-

10

nV/v'Hz

V(DIF + DIF -)
Output Swing

Set by Rg

-

3.2

Vpp

V(OUT + - OUT-)
Output Swing

Set by Rex, Lex, Cex
Impedance

-

5

Vpp

Dynamic Range

Common mode DC input where gain falls to 90%
of O.OV DC common mode input. 10mVpp AC
input, Rg ="", Rex = 12000.

-240

-240

mV

I

DIF + to DIF - pin Current

±1.9

-

rnA

OUT + to OUT - pin Current

±3.8

-

rnA

CMRR (input referred)

V(IN +) = V(IN -) = 100mVpp,
5MHz, Rg=O.o. ,Rex=200n

40

-

dB

PSRR (input referred)

Vdd or Vcc = 100mVpp,
5Mhz, Rg = 0.0. , Rex = 200.0.

40

-

dB

2-69

Parameter

Test Conditions

Min.

Max.

Zero Crossing Detector

1

-

Input Offset Voltage
Input Signal Range

I

5.0

mV

5.0

Vpp

4.4 typ

Differential Input
Impedance (DIN ±)

kn.

Line Driver (551 540 & 540·2 only)
Output Sink Current

VOL = 0.5V, V(MODE) = 2.0V

20

VOH = 2.5V, V(MODE) = 2.0V

-2

-

mA

Output Source Current
Output Current

Vo = OV to Vcc,V(MODE) =OV

-50

50

j.lA

30

ns

mA

Output Rise Time

Vo= 0.7Vto 1.9V
100n between RD + and RD -, 30pf to GND

2

Output Fall Time

Vo = 1.9V to 0.7V
100n between RD + and RD -, 30pf to GND

2

30

ns

13.8

114

ns

Time Domain Filter
Delay Range

TTD1 = 0.184xRTD x CTD,
RTD = 1.5kn. to 3.1kn. , CTD = 50pf to 200pf,
V(DIN + - DIN -) = 100mVpp, 5MHz, AC coupled
square wave See Fig 2

Delay Range Accuracy

Vcc = 5.0V, Tj = 60·C

-

±15

ns

Variation with supply and temperature

-

12

ns

Delay = TD2 - TD1 See Fig 2

-

80

ns

30

80

ns

-

5

ns

Propagation Delay
Data Pulse
Pulse Width

TPW = 0.184 x RpW x CPW
RpW = 2k.a, CPW = 150pf

V(DIN + - DIN -) = 100mVpp, 5MHz, AC coupled
square wave w/2nsec rise & fall times.

Skew

V

(WRT+ ~WR:~~l-~I-/___\-\--___

-~

See Fig 2

~'eo~t

~;eo~

::F--J1l-JK
=l
1=
TRISE

T FALL

Fig. 1: Write Mode Timing.

2-70

551 540 Series
Read Data Processor
Applications Information

+5V

GND

+12V

10

551540

HOX C-~----1
BOOn
HOY C--+.-----1

HSOB
2B

BOOn

551117

20
HS1B
14

HS2B

27

H2X ~-+-----1 B
BOOn
H2Y C--+.-----1

PLCC
PIN OUT
WRT+

WRTMODE

H3X ,---+-----1
BOOn
H3Y "--4-_ _--1

RD-

RD+

10;Al

Design Example
As a design example a system using a 4-channel SSI117
Read/Write preamplifier will be used.
Assumptions-coding scheme is MFM
-data rate is 5 Mbits/second
-Ferrite head output is 1 mVpp min.
and 2 mVpp max.
The output from the SSI117 is 80 mVpp to 240 mVpp.
Assuming a 6 dB loss through the external low pass
filter the input to the SSI 540 at IN +, IN - is:
40mVpp to 120 mVpp differential voltage.
For this analysis the ± 37% tolerance on gain from
IN +, IN - to OUT +, OUT - will be equally divided
between the gain stage and the differentiator, so each
will contribute a ± 17% variance from nominal values.
The objective is to get a 5 Vpp Signal at OUT + ,OUT - at
max input and max frequency. For MFM the 2f frequency
in a 5 Mbitlsec data rate is 2.5 MHz, 1f is 1.25 MHz.

the 5 Vpp max spec at OUT + ,OUT - the maximum
differential voltage gain is:
__5__ = 1.79 max gain
2.79
which is nominally a gain of 1.53
For Cex only:

Av, =

680
17 +17.17

1.53

Cex = 21ffv'(1420)' _ (1.53x46)'

=68pf

check for current saturation:
Ic = Cex x Vp x 21ff must be less, than 1.9 mA
For Cex, Rex network:
The following two formulas are used:
j 1420 Cex 21ff
1.53 =
j (Rex + 46) Cex 21ff + 1

1

Rex + 46 =

Cex A 2m max
where A is chosen for position of comer
frequency to reduce high frequency noise gain
from the single capacitor network.
Graphically the method is as follows:

Gain Setting
Maximum gain from the amplifier occurs when Rg =0.
So calculating for nominal gain:
Rx = _..::9..:.4..::x,-4:=2,-230

O.1.uf

= 17.17
= 19.9 nominal or 16.52 min to
23.28 max

The voltage swing at the DIF + , DIF - pins is:
120 mVpp x 22.25 = 2.79 Vpp max
40 mVpp x 17.55 = 0.661 Vpp min
This is within the 3.2 Vpp max guaranteed by this
specification, so max gain will be used.
Differentiator Design
The differentiator can be as Simple as a capacitor or as
complex as a series RLC network. In order not to violate

11

2-71

2f

Af·

2otfVin(t)

Check for current saturation using the following formula.
Ip =

Effect of Gain Tolerance

At minimum gain the lmVpp input at 1.25 MHz frequency
has the following effects:

iVp21rfCex
1 + j 27ff Cex (R+ 46)

Using the capacitor only results with Cex

For Rex, Cex, Lex networks, the following formulae are
used:
- j 1420 Cex 2... f

Gain G

Diff gain =

1 - LexCex (2 ...f)' + j (Rex + 46) Cex 2...f

v'[1 - LexCex (2 ...f)'J' + [(Rex + 46) Cex 2... fJ'

L

1r2 - tan-1

[(Hex_~~Cex 2...f

]

Thus, with all tolerances considered, a lmVpp to 2mVpp
input to the SSI i17 will result in a 5 Vpp to 416 mVpp
input to the zero-crossing detector.
ONE·SHOT CONSIDERATIONS

2... v'L ex Cex

The timing for both one shots conform to the same
equation:
t = 0.184 x C x R

(Rex + 46) Cex
---2-;;Le~Cex -

Damping Factor I;;

0.758 nominal

so with a 661 mVpp input the min voltage @ OUT + lOUT is 416 mVpp.

1 - LexCex (2 ...f)'

Center Freq f n

1420 Cex 2... f
+ (46 Cex 2 ...f)'

Using ± 17% tolerance, min gain = 0.629

1420 Cex 2...f

I-

.)1

= 68pf

Setting of the time domain one·shot reflects the
expected base line shouldering effect at the 11 frequecy
and is set accordingly. In this example the output
pulse width has been set at approximately 30 nsec and
the time domain filter at approximately 80 nsec.

dO
Group Delay df

EXTERNAL FILTER

This technique adds another pole to the differentiator
response to attenuate high frequency noise. The center
frequency damping ratio and group delay are chosen to
meet system requirements. Values for the center frequency are usually from 2 to 10fmax and the damping
factor may be from 0.3 to 1.

The filter on the output of the read/write amplifier, limits
the bandwidth of the input to the SSI 540. This reduces
the noise input to the differentiator which can produce
spurious zero-crossings. The design of this filter is not
discussed here, but general aspects of its transfer
function will be discussed.

Graphically the method is as follows:

On the outer tracks of an ST506 compatible drive using
a MFM coding technique, the output pulses return to
baseline or exhibit shouldering.

1,(1)

v

Outer Track Waveform

11

21

In

This waveform has a high third harmonic content. In
order to preserve this waveform the filter must not add
any distortion to this harmonic. For this reason, the
most common filter type used is a Bessel Filter which
has a constant group delay (~) or linear phase shift.
Thus for a 5 Mbitlsec MFM waveform a Bessel Filter with
constant group delay and a - 3 dB point of 3.75 MHz
is required. This is the type of filter used in the design
example.

a.IVin(l)

As with the previous Rex, Cex example, care must be
taken to insure a 90 phase shift at the frequencies of
interest (1f and 2f or 1.25 MHz and 2.5 MHz). This
requirement is modified by any need to compensate for
phase distortion caused by preceeding signal processing.
0

2-72

silicon Jl rsfonf" 91O~95-2809

_ _ _ _ _ _ _ _ _ _ _14_3_5_1_M_Yf_O_rd_R_o_O_d,_T_us_ti_n,_CA:!f;14) 731-7110, TWX

~ ~ ---.evallset

Shift contributed by the SSI 540 is:
0.26 nsec at maximum input and frequency
6.2 nsec at minimum input and frequency
In some literature this effect is called Pulse Pairing. If
the RD + ,RD - waveform is displayed on an
oscilloscope with the trigger holdoff adjusted to fire on
succeeding pulses the following waveform is observed:

T

(OUT+ -

OUT-)'-~~"",
I-- ~

COMPARATOR
OUTPUT

I

I

-1J

II

Ii

--, i---c Crt

rhl

:

I~

(RD+ - R D - = U J l 1

·l-- t1

I

t2--1

Effect of Comparator Offset on output waveform

Bit Shift or Pulse Pairing
Theoretical consideration of this aspect of pulse
replication relative solely to the SSI 540 indicates that
comparator offset is the major contributing parameter.
For sinusoidal inputs the offset produces a nonsymetric waveform as shown.

Pulse Pairing

where t2 - t1, = 4 lit or 2 x (Bit Shift)
Using this technique and a sinusoidal input to DIN ±
of varying amplitude at 1.25 MHz and 2.5 MHz, the
following results were obtained.

The RD + ,RD - output pulses have been offset from
true position (zero·crossing) by an amount lit, that is
dependent on Voffset and OUT + ,OUT - amplitude.
This relationship is
lit = ~ sin -1

w

DIN ± Input
Vp _ p

(VOff)
(radians)
Vp

5

3
1

So, referring to previous results:
when OUT + ,OUT 5 Vpp @ 2.5 MHz
lit = 0.13 nsec
416 mVpp @ 1.25 MHz
when OUT + ,OUT lit = 3.1nsec
As can be seen above the center pulse has been shifted
from its true position by2 lit. So for this example the Bit

.7
.3
.1

.07
.06
.05
.04

.03

RD ± Pulse Jitter (4-,t) nsee
1.25 MHz

2.5 MHz

0.6
0.6
0.6

0.8
0.0

1.4

0.0

1.6
3.8
5.6
6.2
7.0

0.5
1.2

1.0

2.4

3.2
3.5
4.5
6.0

9.6

11.8

551 540. Pin Assignments
28 PIN DIP

22 PIN OJp

28 PIN DIP

28 PIN DIP
OIF+
22

-- OIF-

HSOB

SSI540
GND1
GND2
VFLTB

RD+

H'"

15 -WRT-

2e PIN PLCC

28 PIN PLCC

28 PIN PLCC

~~~~~~~
~

The "PRELIMINARY" designation on an SSi data sheet indicates that the
product is not yet released for production. The specifications are subject to
change, are based on design goals or preliminary part evaluation, and are

not guaranteed. SSi should be consulted for current information before using this product. No responsibility is assumed by SSi for its use; nor for any

infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent
rights or trademarks of SSi. SSi reserves the right to make changes in
specifications at any time and without notice.

2-73

551541
Read Data
Processor

INNOVATORS IN INTEGRATION

Preliminary Data 5heet
FEATURES
• Level qualification supports high resolution MFM
and RLL encoded data retrieva,l

DESCRIPTION
The SSI 541 is a bipolar integrated Circuit that provides
all data processing necessary for detection and
qualification of MFM or RLL encoded read signals. The
circuit will handle data rates up to 15 Megabits/sec.

• Wide bandwidth AGC input amplifier
• Supports data rates up to 15 megabits/sec

In read mode the SSI 541 provides amplification and
qualification of head preamplifier outputs. Pulse
qualification is accomplished using level qualification of
differentiated input zero crossings. An AGC amplifier is
used to compensate for variations in head preamp output
levels, presenting a constant input level to the pulse
qualification circuitry.

• Standard 12V ±10% and 5V ±10% supplies
• Supports embedded servo pattern decoding
• Write to read transient suppression
• Fast and slow AGC attack regions for fast transient
recovery

The AGC loop can be disabled so that a constant gain
can be used for embedded servo decoding or other
processing needs.
In write mode the circuitry is disabled and the AGC gain
stage input impedance switched to a lower level to allow
fast setting of the input coupling capacitors during a write
to read transition.
The SSI 541 requires +5V and + 12V power supplies and
is available in a 24 pin DIP and 28 pin PLCC.

SSI 541 Block Diagram
OUT+

OUT-

DIN-

OIN+

CIN-

CIN+

OIF-

1------

C OUT

RD

ONE-SHOT

I

I
I

BYP

I

I
I

I
I

AGNOO

I

I
I
I
______ J

I

'- ---0------o GND

AGe

LEVEL

R!WB

HYS

o OUT

os

CAUTION: Use handling procedures necessary
for a static sensitive component

2-74

551 541
Read Data Processor
CIRCUIT OPERATION
Read Mode

The filtered clock path signal is differentiated to transform
signal peaks to zero-crossings which clock an edgetrigger circuit to provide output pulses at each zerocrossing. The pulses are used to clock the D type flipflop. The COUT pin is a buffered test point for monitoring
this function.

In the read mode (R/wB input high or open) the input
read signal is amplified and qualified using an AGC
amplifier and pulse level qualification of the detected
signal peaks.

The differentiator function is set by an external network
between the DIF+, DIF- pins. The transfer function is:

The amplified head signals are AC coupled to the
IN+ and IN- pins of the AGC amplifier that is gain
controlled by full wave rectifying and amplifying the
(DIN+ - DIN- ) voltage level and comparing it to a
reference level at the AGC pin. A fast attack mode, which
supplies a 1.5mA charging current for the capaCitor at the
BYP pin, is entered whenever the instantaneous DIN±
level is more than 125% of set level. Between 100% and
125% the slow attack mode is invoked, providing 0.17mA
of charging current. The two attack modes allow rapid
AGC recovery from a write to read transition while
reducing zero crossing distortion once the amplifier is in
range.

AV =

-2000Cs
LCs2 + (R+92) Cs + 1

Where: C= external capaCitor (20pf to 150pf)
L = external inductor
R = external resistor
s = jw = j27TI
During normal operation the dilferentiator circuit clocks
the D flip-flop on every positive and negative peak of the
signal input to CIN+, CIN-. The D input to the flip-flop
only changes state when the signal applied to the DIN+,
DIN - inputs exceeds the hysteresis comparator threshold
opposite in polarity to the previous peak that exceeded
the threshold.

The level at the AGC pin should be set such that the
differential voltage level at the DIN+, DIN- pins is
1.00Vpp at nominal conditions. The circuit can swing
3.0Vpp at the OUT+, OUT- pins which allows for up to
6dB loss in any external filter connected between the
OUT+,OUT- outputs and the DIN+, DIN- inputs.

The clocking path, then, determines signal timing and
the data path determines validity by blocking signal peaks
that do not exceed the hysteresis comparator threshold.

Gain of the AGC section is nominally
Av2 = exp V2 - V1
Av1
5.8 x Vt

The delays from CIN+, CIN- inputs to the flip-flop clock
input and from the DIN +, DIN - inputs to the flip-flop D
input are well matched.

Where: Av1 and Av2 are initial and final amplifier
gains. V1, V2 are initial and final voltages on
the BYP pin.

WRITE (DISABLED) MODE

Vt = (K x T)/q = 26mV at room temperature.
One filter for both data (DIN+, DIN- input) and clock
(CIN+, CIN- input) paths, or a separate filter for each path
may be used. II two filters are used, care must be
exercised to control time delays so that each path is timed
properly. A multi-pole Bessell filter is typically used for its
linear phase or constant group delay characteristics.
The filtered data path signal is fed into a hysteresis
comparator that is set at a fraction of the input signal
level by using an external filter/network between the
LEVEL and Hys pins. Using this approach allows setting
the AGC slow attack and decay times slow enough to
minimize distortion of the clock path signal. This "feedforward" technique, utilizing a fraction of the rectified
data path input available at the LEVEL pin as the
hysteresis threshold, is especially useful in the slow
decay mode of the AGC loop. By using a short time
constant for the hysteresis level, the qualification method
can continue as the AGC amplifier gain is slowly ramped
up. This level will also shorten the write to read transient
recovery time without affecting data timing as the circuit
will be properly decoding before the AGC gain has
settled to its final value. The comparator output is the
"D" input of a D type flip-flop. The DOUT pin provides a
buffered test pOint for monitoring this function.

In the write or disabled mode (R/WB input low) the digital
circuitry is disabled and the AGC amplifier input
impedance is reduced. In addition the AGC amplifier gain
is set to maximum so that the loop is in its fast attack
mode when changing back to Read Mode. The lowered
input impedance facilitates more rapid settling of the
write to read transient by reduCing the time constant of
the network between the 881 541 and a read/write
preamplifier, such as the 881 510.
Internal 881 541 timing is such that this settling is
accomplished before the AGC loop is activated when
going to read mode. Coupling capaCitors should be
chosen with as low a value as possible, consistant with
bandwidth requirements, to allow more rapid settling.
LAYOUT CONSIDERATIONS

The 881 541 is a high gain wide bandwidth device that
requires care in layout. The designer should keep analog
signal lines as short as possible and well balanced. Use
of a ground plane is recommended along with supply
bypassing and separation of the 881 541 and associated
circuitry grounds from other circuits on the disk drive
PCB.

2-75

PIN DESCRIPTION
Pin Name

Description

Pin Name

Description

VCC

5 volt power supply

VDD

12 volt power supply

AGND, DGND

Analog and Digital ground pins

RIWB

TTL compatible read/write control pin

IN+,IN-

Analog signal input pins

OUT+,OUT-

AGC Amplifier output pins

BYP

The AGC timing capacitor is tied between
this pin and AGND

HOLDB

TTL compatible pin that holds the AGC
gain when pulled low

AGC

Reference input voltage level for the AGC
circuit

DIN+, DIN-

Analog input to the hysteresis comparator

Absolute Maximum Ratings'
5V Supply Voltage, VCC ......................... 6V
12V Supply Voltage, VDD ........................ 14V
Storage Temperature .................. -65° to 150°C
Lead Temperature ............................ 260°C
RiW, IN+, IN-, HOLD ........... -0.3V to VCC + 0.3V
........... -0.3 to VCC + 0.3V or + 12mA
RD
All others ...................... -0.3V to VDD + 0.3V

HYS

Hysteresis level setting input to the
hysteresis comparator

LEVEL

Provides rectified signal level for input to
the hysteresis comparator

DOUT

Buffered test point for monitoring the flipflop D input

CIN+, CIN-

Analog input to the differentiator

DIF+, DIF-

Pins for extrenal differentiating network

COUT

Buffered test point for monitoring the
clock input to the flip-flop

OS

Connection for read output pulse width
setting capacitor

RD

TTL compatible read output

1

1

READ - Read amp on, AGC active,
Digital section active

1

0

HOLD - Read amp on, AGC gain
held constant Digital section active

0

X

WRITE - AGC gain switched to maximum, Digital section inactive, common
mode input resistance reduced

·Operation above these rating may cause permanent damage to device.

Electrical Characteristics

Mode

R/WB HOLOB

Unless otherwise specified 4.5V~ VCC~ 5.5V, 10.8V~ VDD~ 13.2V, 25C~ Tj~ 135C

I Parameter

I Test Conditions

I

Min.

I

Typ.

I

Max.

I Units

POWER SUPPLY
ICC -

VCC Supply Current

Outputs unloaded

-

IDD -

VDD Supply Current

Outputs unloaded

-

Pd -

Power Dissipation

Outputs unloaded, Tj

=

135C

-

14

mA

70

mA

-

730

mW

0.8

V

LOGIC SIGNALS
VIL -

Input Low Voltage

VIH -

Input High Voltage

ilL -

Input Low Current

IIH -

Input High Current

VOL -

Output Low Voltage

VOH -

Output High Voltage

-

-0.3

= 0.4V
VIH = 2.4V
10L = 4.0mA
10H = 400!1A

0.0

-

-

2.4

2.0

VIL

-

-

V

-0.4

mA

100

!1 A

0.4

V

-

-

V

-

1.0

!1S

MODE CONTROL
Read to Write Transition Time

-

-

Write to Read Transition Time

AGC settling not included, transition to high
input resistance

1.2

-

3.0

!1S

Read to Hold Transition Time

-

-

-

1.0

!1S

WRITE MODE
Common Mode Input Impedance
(both sides)

RIWB pin

low

2-76

I Parameter

I Test Conditions

Min.

I

Typ.

I Max. I Units I

READ MODE
AGC Amplifier

Unless otherwise specified IN+ and IN- are AC coupled, OUT+ and OUT- are loaded differentially
with> 600[2 and each side is loaded with <10pf to GND, a 2000pf capacitor is connected between BYP
and GND, OUT+ is AC coupled to DIN+, OUT- is AC coupled to DIN-, AGC pin voltage is 3.0VDC.
[2
Differential Input Resistance
5K
V(IN+ - IN-) = 100mVpp@ 2.5MHz
Differential Input Capacitance

V(IN+ -

IN-) = 100mVpp@ 2.5MHz

Common Mode Input Impedance R/wB pin high

-

-

10

pF

-

1.8

-

K[2

0.25

-

K[2

83

V/V

15

nVlYHz

(both sides)

R/wB pin low

Gain Range

1.0Vpp ~ V(OUT+ -

Input Noise Voltage

Gain set to maximum

-

-

Bandwidth

Gain set to maximum -3dB point

25

-

Maximum Output Voltage Swing

Set by AGC pin voltage

3.0

OUT+ to OUT- Pin Current

See Note 1, No DC path to GND

-

-

Output Resistance

-

20

30

Output Capacitance
(DIN+ - DIN-) Input Voltage I
Swing VS AGC Input Level

-

-

15

pF

30

-

0.48

-

Vpp/V

%

OUT-) = 2.5Vpp

mVpp~

1.5~

V(IN+ - IN-) = 550mVpp
V(AGC)~ 3.75V

±3.2

(DIN+ - DIN-) Input Voltage
Swing Variation

30mVpp~

Gain Decay Time (Td)

Vin=300mVpp- 150mVpp at 2.5MHz, Vout to
90% of final value. See Fig. 1a

Gain Attack Time (Ta)

From Write to Read transition to Vout at 110% of
final value Vin=400mVpp @ 2.5MHz. See Fig. 1b

-

Fast AGC Capacitor Charge
Current

V(DIN+ = DIN-)= 1.6V
V(AGC) = 3.0V

-

Slow AGC Capacitor Charge
Current

V(DIN+ - DIN-)= 1.6V
Vary V(AGC) until slow discharge begins

-

Fast to Slow Attack Switchover
Point

V(DIN+ -

DIN-)

V(DIN+ -

DIN-) Final

AGC Capacitor Discharge
Current

(IN+ - IN-)~ 550mVpp, AGC
Fixed, Over supply and temperature

4.0

MHz
Vpp
mA
[2

-

-

±4

-

50

-

f-tS

4

-

f-tS

1.5

-

mA

0.17

-

mA

-

1.25

-

-

-

4.5

-

f-tA
f-tA
dB

>

V(DIN+ - DIN-)= O.OV
Read Mode
Hold Mode

-0.2

-

-

1.5

Vpp

11

K[2

6.0

pF

CMRR (Input Referred)

V(IN+)=V(IN-)= 100mVpp @5MHz, gain at max.

40

PSRR (Input Referred)

VCC or VDD = 100mVpp @5MHz, gain at max.

30

+0.2

dB

Note 1: AGe amplIfIer output current may be Increased as In Fig. 4.

HYSTERESIS COMPARATOR

-

Input Signal Range

-

Differential Input Resistance

V(DIN+ -

DIN-)= 100mVpp@2.5MHz

5

Differential Input Capacitance

V(DIN+ -

DIN-)= 100mVpp@2.5MHz

-

-

-

2.0

-

K[2

-

-

10

mV

0.21

Common Mode Input Impedance (both sides)
Comparator Offset Voltage

HYS pin at GND ~1.5K[2 across DIN+, DIN-

Peak Hysteresis Voltage vs HYS
pin voltage (input referred)

1V< V (HYS)< 3V

-

HYS Pin Input Current

1V< V (HYS)< 3V

0.0

LEVEL Pin Max Output Current

-

3.0

-

LEVEL Pin Output Resistance

I (LEVEL)= 0.5mA

-

180

2-77

-

V/V

-20

f-tA
mA
[2

-

I Parameter

I Test Conditions

Min.

Typ.

I

Max.

Units

HYSTERESIS COMPARATOR (cont.)
DOUT Pin Output Low Voltage

0.0';;; 10L';;; 0.5mA

V

DOUT Pin Output High Voltage

0.0';;; 10H';;; 0.5mA

V

ACTIVE DIFFERENTIATOR

-

Input Signal Range

-

Differential Input Resistance

V(CIN+ -

Differential Input Capacitance

V(CIN+ -

CIN-)= 100mVpp @ 2.5 MHz

5.8

CIN -)= 100mVpp@ 2.5 MHz

-

Common Mode Input Impedance (both sides)
DIF+ to DIF- Pin Current

Differentiator Impedance must be set so as not
to clip signal at this current level.

Comparator Offset Voltage

DIF+, DIF- AC Coupled

COUT Pin Output Low Voltage

0.0';;; 10H';;; 0.5mA

COUT Pin Output Pulse Voltage
V(high)-V(low)
COUT Pin Output Pulse Width

±1.3

-

1.5

Vpp

11.0

KD

6.0

pF

2.0

-

KD

-

mA

-

-

-

VDD-3.0

-

V

0.0';;; 10H';;; 0.5mA

-

+0.4

0.0';;; 10H';;; 0.5mA

-

30

-

nS

10.0

mV

V

OUTPUT DATA CHARACTERISTICS (REF. FIG. 2) Unless otherwise specified V(CIN+ - CIN-) = V(DIN+ - DIN-) =
1.0Vpp AC coupled since wave at 2.5MHz differentiating network between DIF+ and DIF- is 100D
in series with 65pF, V (Hys) = 1.8DC, a 60pF capacitor is connected between OS and VCC,
RD- is loaded with a 4D resistor to VCC and a 10pF capacitor to GND.
Parameter

Test Conditions

Min.

Typ.

Max.

Units

D-Flip-Flop Set Up Time (Td1)

Min delay from V(DIN+ DIN-) exceeding
threshold to V(DIF+ - DIF -) reaching a peak

0

nS

-

-

-

-

Propagation Delay (Td3)

110

nS

Output Data Pulse Width
Variation

Td5 = 670 Cos, 50 pF ';;;Cos';;; 200 pF

-

%

-

-

±15

Logic Skew Td3 -

Td4

Output Rise Time

VOH = 2.4V

Output Fall Time

VOL = O.4V

VIIN+ -IN-'

]JjV\

r- Td-1

'\/

V (IN+ - IN-)

RMI

,.,

V{OUT+ -

OUT-)

nS
nS

18

nS

IL

7\/\
~

-1

VIOUT+-OUT-'~

3
14

tL

T.

7\/ \1J;-=rr=rJ¥-c==-r,-[(b)

110%

Fig. 1: AGC Timing Diagram

Fig. 2. Timing Diagram

2-78

JifkonJl rJfunJ···

.c: :~_71_4_)_7_31_-7_1 _0_,T_W_X_9_1_0-_5_95_-_28_0_9

______________________
14_3_5_1M_Y_fo_r_d_Ro_a_d_,T_u_5t_in__

_____________________

TO SERVO
CIRCUIT

1----,

Kt:~:~
~

i
I

I
I

I
I

I

I

,~-+~

6

I

I
READMIRITE
AMPLIFIER

DIGITAL
GROUND

' - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

READIWRITE
CONTROL & WRITE DATA

NOTE: Circuit traces lor the 12Y bypass capacitor and the AGe hold capacitor should be as short as possible with both capacitors returned to the Analog Ground pin

Fig. 3: TYPICAL READ/WRITE ELECTRONICS SET UP
(component values, where given, are for a 5MB/sec system)

551 541 Pin Assignments
Fig. 4: Modification of AGC Amplifier Output Current
to drive low impedance fillers.

""o------------------@ we/CARO

><>------------@ CARt
ORSEl

,}---.=,---+-__________________________---!.

1)o------------{2

A~ll~1JY

~--------_+----------------------~=LJ?------------~~TR~
r----------t-----------------------t-rlP------------~32 ~UIT

~----------~~ R~

1------1----1----1

~----------~23 SC

[DotT-,-t---t-rlJc-------------(34 SEEK COMPLETE
~----------~28

DR SLTD

1---+-+-+------------------\113 DIR IN

.--+-+--+--______________-{t2

T1

~GNO

PHOTO 0

IN 1

Vee

(22Y2____________________-.::O:::.2V~+;.>----t_--------------------\19

TRK 0

-==:::'D;p---------------{3

OUT 1

4 ) - - - - - - - - -___________________

e-----.
2-80

CAUTION: Use handling procedures necessary
tor a static sensitive component

551545
Winchester Disk Drive
Support Logic
ABSOLUTE MAXIMUM RATINGS
Characteristic .............................. Rating
VCC supply voltage ......................... 7 volts
Storage temperature ............... -65°C to + 150°C

ELECTRICAL CHARACTERISTICS

Unless otherwise specified: 4.5 < Vcc

Parameter
LOGIC OUTPUTS

Ambient operating temperature ........ oce to + 70°C
Logic input voltage ............. -0.5 VDC to 7.0 VDC
Lead temperature (soldering 10 sec) ............ 260°C

I

< 5.5V; 0 deg C < Ta < 70 deg C

Test Condition

I

Min.

I

Max.

I

Units

Refer to table 1 for output type, pin number cross reference

TYPE 01 (OPEN COLLECTOR) OUTPUTS

Output High Current

VOH = 5.5V

Output Low Voltage

IOL= 16mA

TYPE 02 (TOTEM POLE) OUTPUTS

Output High Voltage

IOH = -400 l1A

2.5

-

Output Low Voltage

IOL= BmA

-

0.5

V

-

-100

mA

Short Circuit Current

V

TYPE 03 (OPEN COLLECTOR) OUTPUTS

Output High Current

VOH= VCC

Output Low Voltage

IOL= 30mA

TYPE 04 (OPEN COLLECTOR) OUTPUTS

Output High Current

VOH = 5.5V

Output Low Voltage

IOL=4BmA

LOGIC INPUTS
TYPE 11 INPUTS

Input High Voltage

2.0

-

V

Input Low Voltage

-

O.B

V

Input Low Current

VIL= 0.5V

-

-O.B

mA

Input High Current

VIH = 2.4V

-

400

l1A

Positive going, VCC = 5V

1.3

2.0

V

Negative going, VCC = 5V

0.6

1.1

V

-

TYPE 12 (SCHMIDT TRIGGER) INPUTS

Threshold Voltage

V

Hysteresis

VCC= 5V

0.4

Input High Current

VIH = 2.4V

-

40

Input Low Current

VIL= 0.5V

-

-O.B

l1 A
mA

TYPE 13 (INTERNAL PULLUP) INPUTS

Input High Voltage

2.0

-

V

Input Low Voltage

-

O.B

V

Input Low Current

-

-1.2

V

VIL= 0.5V

2-81

Parameter

Test Condition

COMPARATOR INPUTS

Threshold Voltage

Index Ref
Photo 0

Positive going

-

580

mV

Negative going

370

-

mV

-

280

mV

Positive going

120

-

mV

30typ

-

mV

10

-

kQ

40

nS

40

nS

DB5 to ACTIVITY LAMP

-

40

nS

DB4 to TRCKO -

-

40

nS

Negative going
Hysteresis
Input Resistance

VCC = 5.0V, OVcc1 - 0.5V at MIN LIMIT

30

70

mV pk

T1

VTO = 2.0V VT1 = O.BV Vo pulse value
<0.5V at MAX LIMIT,
>Vcc1 - 0.5V at MIN LIMIT

97

153

mV pk

T2

VTO = O.BV VT1 = 2.0V Vo pulse value
<0.5V at MAX LIMIT,
>Vcc1 - 0.5V at MIN LIMIT

13B

202

mV pk

T3

VTO = 2.0V VT1 = 2.0V Vo pulse value
<0.5V at MAX LIMIT,
>Vcc1 - 0.5V at MIN LIMIT

210

290

mV pk

Level Comparator Ditt. Input
Resistance

Yin

= 5V p-p @

Level Comparator OFF Output
Leakage

Vo

= Vcc1

Level Comparator ON Output
Voltage

VTO = O.BV VT1 = O.BV Yin
diff. dc 10 = 2.0mA

Delay Comparator Upper
Threshold Voltage

Level Comparator Input
Thresholds, Single-Ended,
Each Input

5

-

KQ

-

25

/l-A

-

0.25

V

Vo > 2.4V

.65Vcc1

.75Vcc1

V

Delay Comparator Lower
Threshold Voltage

Vo< 0.5V

.25Vcc1

.35Vcc1

V

Delay Comparator Input Current

OV< Vin< Vcc1

-

25

/l-A:

100kHz

2-111

=

± 140mV

551550

POSTAMPLIFIER
CHARACTERISTICS

Output Load = 2.5KO + 0.1J..tF line-line, Yin = 100mV p-p, 100kHz sine wave,
dc-coupled (to provide proper biasing). CG = 0.1J..tF RG = O.

Differential Input Impedance
Bandwidth,1dB
Bandwidth,3dB
Maximum Difl. Output Voltage
Small Signal Single-Ended
Output Res.

Min.

Test Conditions

Characteristics
Differential Voltage Gain

AO
A1
A2
A3
A4
A5
AS
A7
ARG
when

=

VGO
O.BV
VGO = 2.0V
VGO
O.BV
VGO
2.0V
VGO
O.BV
VGO
2.0V
VGO
O.BV
VGO
2.0V
VGO = 2.0V
RG
2.5KO

=
=
=
=
=
=

VG1
VG1
VG1
VG1
VG1
VG1
VG1
VG1
VG1

=
=
=
=
=
=
=
=
=

O.BV
O.BV
2.0V
2.0V
O.BV
O.BV
2.0V
2.0V
2.0V

=

VG2
O.BV
VG2 = O.BV
VG2 = O.BV
VG2
O.BV
VG2
2.0V
VG2
2.0V
VG2 = 2.0V
VG2
2.0V
VG2
2.0V

=
=
=

=
=

=
= 2.0V VG1 = 2.0V VG2 = 2.0V
VGO = 2.0V VG1 = 2.0V VG2 = 2.0V
VGO = 2.0V VG1 = 2.0V VG2 = 2.0V
VGO = O.BV VG1 = O.BV VG2 = oav
Yin = 100kHz sine wave THO <5%
VGO = 2.0V VG1 = 2.0V VG2 = 2.0V
VGO

Yin = OV

Max.

A7-14.75 A7-13.25
A7-12.75 A7-11.25
A7-10.75 A7-9.25
A7-B.75 A7-7.25
A7-S.75 A7-5.25
A7-4.75 A7-3.25
A7-2.75 A7-1.25
32
A7-4.5
A7·7.5

-

Units
dB
dB
dB
dB
dB
dB
dB
dB
dB

10

-

KO

1.5

-

MHz

3.0

-

MHz

5

-

Vp-p

-

35

0

-

± 1.0

V

3.5

V

10 = 1mA p-p, 100kHz

Input Bias Offset Voltage
Range

VGO = O.BV VG1 = O.BV
THO <2.0%

Input Bias Common-Mode
Voltage Range

VGO
O.BV VG1 = O.BV
THO <2.0%

=

2-112

VG2 = O.BV
VG2

= O.BV

2.SB

JifuonJl rJkms

CA:"~714)

_ _ _ _ _ _ _ _ _ _ _.14.3.5.1M.Y.fO.r.d.R.OO.d.'T.U.st.in_,

731-7110, TWX 910-595-2800

r
m
INO-

40

S1

INO+

39

SO

Z

il

IN1-

38

IN1+

37

PREOUT+

IN2-

36

G2

IN2+

35

PSTIN -

PREOUT-

IN3-

34

PSTIN+

IN3+

33

GAIN2

32

GAIN 1

31

G1

CTVOLT
VCC2

10

SSI550

28

""<
c
'"Z" "[;;
J>

<
0
c

."

."

~

(")

--i

+

I

;rJ

]

::! ci

'1

"

m

27

26

25

24

23

22

20

19

18

~

~

J>

<
(")

21

N/C

LEV-

LEV+

TDF

GO

DWP

PSTOUT-

SIGNAL DETECT

PSTOUT+

DEL IN

AGND

11

30

PSTOUT+

DELIN

12

29

PSTOUT -

SSI550

SIGNAL DETECT

13

,.

28

GO

GAIN1

VCC2

DWP

27

LEV +

GAIN2

CTVOLT

LEV-

G1

AGND

TOF

15

26

DATA PULSE

16

25

LEV OUT

PSTIN+

IN3+

DGND

17

24

DIF+

PSTIN-

IN3-

VCC1

18

23

DIF-

NC

TO

19

22

CAP2

T1

20

21

CAP1

IN2+

40

42

43

4.

"m "m
0
0

fg

'Ii

41

0
~

40-PIN DIP
Pin Out (Top View

:0

:0

c

C
--i
I

--i

+

~
I

~ ~ ~

+

+

z

~ il
I

44-PIN QUAD

Pin Out (Top View)

THERMAL CHARACTERISTICS: 0 JA
40-PIN
40-PIN
44 -PIN

PDIP
CDIP
QUAD

The "PRELIMINARY" designation on an 88i data sheet indicates that the
product is not yet released for production. The specifications are subject to
change, are based on design goals or preliminary part evaluation, and are
not guaranteed. S8i should be consulted for current information before using this product. No responsibility is assumed by S8i for its use; nor for any

2-113

infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents," patent
rights or trademarks of SSi. SSi reserves the right to make changes in
specifications at any time and without notice.

SS167C401/402
First-In First-Out (FIFO)
64x4 or 64x5 Memory

INTEGRATION

Preliminary Data Sheet
GENERAL DESCRIPTION

FEATURES

The SSI 67C401/402 devices are high speed, expandable
memories operating as a First-In, First-Out, (FIFO)
asynchronous register of either 64 words by 4-bit (SSI67C
401) or 64 words by 5-bit (SSI67C402). The SSI67C401/402
are CMOS devices. A 10 MHz shift rate provides the fast
transfer of data necessary for applications in high speed
tape or disc controllers and communication buffers. A
single +5V power supply is required.

•
•
•
•
•
•
•
•
•

10 MHz shift in, shift out rates
Choice of 4-bit or 5-bit width
TTL compatible inputs and outputs
Readily expandable in word and bit dimensions
Output pins directly opposite corresponding input
pins
Asynchronous operation
Pin compatible with MMI 67401 Series
Low power consumption
HCT input and output characteristics

Block Diagrams

Pin Assignments
00

Ne

16

Vee

°1
°2
03

INPUT READY

15

SHIFT OUT

14

OUTPUT READY

r

SHIFT IN

INPUT
READY

SHIFT
OUT

67C401

DATA IN

13
12

D1

OUTPUT
READY

SHIFT
IN

SSI

:

01

°2

10

O:!

GND

MASTER RESET

~}

11

OUTPUTS

MASTER RESET

SSI 67C401 64x4

°1
°2
03
0.

INPUT
READY

18
17

SHIFT OUT

SHIFT IN

16

OUTPUT READY

DATA IN
OUTPUT
READY

MASTER RESET

SSI 67C402 64x5

Vee

Ne
INPUT READY

00

Do
D1
D2
D3
D4

r

SSI
67C402

15

~}

D1

14

01

:

13

02

12

03

D4

11

GND

10

OUTPUTS

°4
MASTER RESET

Pin Out
(Top View)

CAUTION: Use handling procadures necessary
for a statk: sensitive component

2-114
-----~-----

----------------~~----~--------.---~--~~=-.~-~

SS167C401/402

First-In First-Out (FIFO)
64x4 or 64x5 Memory
may be shifted out by bringing SO high. The rise of SO
causes OR to go low. Valid data is maintained while SO
is high. When SO is brought low, the upstream data (providing the next stage contains valid data) is shifted to the
output stage and OR goes high. If the FIFO is emptied,
OR stays low and the ax data remains as before.

CIRCUIT DESCRIPTION
Data Input
When the FIFO is reset, the Master Reset is pulsed low
to prepare the device for data input. Data is entered at
the Ox inputs as controlled by the Input Ready (IR) and
Shift In (SI) logic. With IR high, data can be accepted.
Data present at the data inputs is entered into the first
position on the rising edge of SI. As SI is taken high, IR
goes low indicating the FIFO is busy. When SI Is set
low, IR goes high if the memory is not full. In the FIFO,
data is shifted towards the output progressively until a
full memory position is encountered. Thus, the memory
is fi lied with the first data word at the output position
and subsequent data words in order behind it. If the
memory is full, that is all 64 word positions contain valid
data, IR remains low after SI is set low.
Data Transfer
After data input, transfer of a data word from a memory
position to an adjacent empty memory position is
automatic, activated by on·chip control. Thus, data
stacks up at the output end of the FIFO while memory
positions that are emptied as data is unloaded are
moved to the input end. The time for data (or emptied
positions) to move the entire length of the memory is
defined as the throughput, or fall through, time (tPT).

Application Notes
The Input Ready (IR) and Output Ready (OR) may be
used as status signals indicating that the FIFO is
completely full (IR stays low for at least fall through
time tptl or that the FIFO is completely empty (OR stays
low for at least tpt).
Since the high speed FIFO is particularly sensitive to
small glitches as might be caused by long reflective
lines, high capacitances, or poor supply decoupling and
grounding, circuit design should account for these
potential problems ensuring that adequate ground
planes and decoupling measures are taken. For
example, it is recommended that a 0.11J.f ceramic
capacitor be connected directly between VCC and
ground with a very short lead length.
5V

Standard Test Load

Data Output
Data outputs at the Ox pins are controlled by the Output
Ready (OR) and Shift Out (SO). When valid data is
shifted to the outputs, OR goes high. With OR high, data

OUTPUT O--~~-~r---f" TEST POINT

Absolute Maximum Ratings* (All voltages referenced to GND)
Parameter

Symbol

Value

Units

Vcc

7

VDC

Yin

7

VDC

Vout

5.5

VDC

Tstg

-65to +125

°C

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
* Operation above

absolute maximum ratings may permanently damage the device.

Electrical Characteristics
Symbol

(4.75 <:;;V cc <:;;5.25 V, O°C <:;;TA <:;;75°C unless otherwise specified)

Parameter

Min

Max

Unit

-

0.8

V

High-level Input Voltage

-

2

-

IlL

Low-Level Input Current

VCC=MAX Vin=0.4V

-0.4

mA

IIH

High-Level Input Current

VCC = MAX Yin = 2.4V

50

IIMH

Maximum Input Current, High

VCC=MAX Vin=5.5V

-

1

IJ.A
mA

IIML

Maximum Input Current, Low

VCC=MAX Vin=0.5V

-

15

mA

VOL

Low-level Output Voltage

VCC=MIN IOL=8mA

-

0.4

V

VOH

High-Level Output Voltage

VCC=MIN 10H= -4.0mA

-

V

lOS

Output Short-Circuit Currentt

VCC=5V

VIL

Low-Level Input Voltage

VIH

ICC

Supply Current

Test Conditions

-

-80

Vout=4.5V

-

-80

-

100

I

VCC=MAX
Vin=VccorGND
Outputs Open Ckt

t Not more than one output shoutd be shorted at a time and dUtaUon of the short-circuU should not exceed one second.
2-t15

4.0

I Vout=0.5V

V

mA
IJ.A

Switching Characteristics Over Operating Conditions
Symbol

Z

Parameter

Min

Max

Unit

100
35
35

-

ns

-

ns

-

ns

-

45
45

ns

0
45
100
35
35

-

ns

-

ns

Shift Out to Output Ready HIGH

-

ns

too

Output Data Delay

10

55
55
55

tpT

Data Throughout (fall through) time

-

3

tMRW

Master Reset Pulse'

35

-

tMRORL

Master Reset to OR LOW

tMRIRH

60
60

ns

Master Reset to IR HIGH

-

tMRS

Master Reset to SI

-

ns

tlPH

Input Ready Pulse HIGH

-

ns

tOPH

Output Ready Pulse HIGH

35
30
30

-

ns

tiN

Shift In Rate (Period between data loading)

tSIH

Shift In HIGH Time

tSIL

Shift In LOW Time

tlRL

Shift In to Input Ready LOW

tlRH

Shift In to Input Ready HIGH

tlDS

Input Data Set Up

tlDH

Input Data Hold Time

tOUT

Shift Out Rate (Period between data unloading)

tSOH

Shift Out HIGH Time

tSOL

Shift Out LOW Time

tORL

Shift Out to Output Ready LOW

tORH

Master reset puts the register logic to "all cells empty", and sets IR high,

1-----

tiN

------1-----

tiN

-------I

SHIFT IN

Input Timing

SHIFT OUT

-+__-+_"\

QUTPUTREADY _ _

OUTPUT DATA

==J=::~J~~&xE~Gt~~J@&xE~~~t==C-~D:AT:A===
o

outputnmlng

Figure 3. Timing Waveforms

(2)

The diagram

assum~s, that at this time, words 63, 62, 61

are loaded with A, B, C Data, respectively

2-116
-_=-_ - - - - - - - -______________________

. __. c c . - .

ns
ns
ns
ns
ns
ns
f.ls
ns
ns

Jbc:rt.714)
cfl rJkmJ'
JE? ,"__
731-1110, TWX 910,595,2809

_ _ _ _ _ _ _ _ _ _ _1_4_3_51_M_Y_fO_r_d_RO_O_d_,T_U_51_in_,

SHIFTOUT~
SHIFTIN - :

I

INPUT READY ...::::.-

+------.1

"n_

fl~~~l~==~IpT==~'~
~-~

OUTPUT READY

'1'-"

____________~lr--tOPH--L--

~fl,,-'

G) FIFO Initially empty
G) Shifl Out held HIGH

I.PH Specification
(DFIFOisiniliallyfull

IpT and iOPH Specification

CD Shift In held HIGH
MASTER RESET

--------

!--'MRW-

-

'MRIRH

INPUT READY

fl

\

lMRORL----

_ _ _ tMRS

SHIFT IN

---=1
CD

FIFO Initially lull

Master Reset Timing
Figure 4. Timing Waveforms

SHIFT IN

OR

INPUT READY

SO

OUTPUT READY

I

SHIFT OUT

00
01

""00'

02
03
MASTER RESET

o-----.....--------...l
Figure 5. Cascading FIFOs to Form 128x4 FIFO.

FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the FIFDs themselves.

"

Co
0,
0,
0,

Me

0,
0,
0,
0,

"

Co
0,
0,
0,

00
0,
0,

C,

c, Me

c,

c,

0,
C,

00
0,
0,

0,
0,
0,

0,
0,

""

Me

C,

0,

Me

00
0,
0,
0,

0,
C,
0,

0,
0,
0,

Co
C,

0,

0,

00
0,

Co
C,
0,

°c
0,
0,
0,

0,

Oc
0,

0,

C,

Me

0,

0,
MASTER RESET

Figure 6. 192x12 FIFO.
FIFOs are expandable in depth and width. However, in forming wider words two external gates are required to generate
composite Input and Output Ready flags. This need is due to the different fall through times of the FIFOs.

The "PRELIMINARY" designation on an 55i data sheet indicates that the

product is not yet released for production. The specifications are subject to
change, are based on design goals or preliminary part evaluation, and are
not guaranteed. SSi should be consulted for current information before using this product. No responsibility is assumed by SSi for its use; nor for any

infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent
rights or trademarks of SSi. SSi reserves the right to make changes in
specifications at any time and without notice.

2·117

Section 3

CUSTOM/
SEMICUSTOM

3

SILICON SYSTEMS - LEADING THE WAY IN CUSTOM/SEMICUSTOM IC'S

At SSi, we've been in a leadership role in
custom circuits, first with superior IC design
capabilities, and then with one of industry's finest wafer fabrication facilities. Today we're still
pacing the field in the burgeoning market for
"application specific" custom/semicustom lC's.
We've maintained our position by carefully
monitoring evolving market requirements and
providing cost-effective, quality solutions for
even the most specialized applications.

Custom/Semicustom Approach to Integrated
Circuits
Custom IC's are not just a side line at SSi;
they've always been our primary business. We
provide the full range of custom IC design with
such practical semicustom options as pre-built
standard cells and switched capacitor filter
arrays. With a top engineering staff supported
by our unique Integrated Design Methodology
(10M), and with a fully automated wafer

In both engineering and technology, we offer
versatility: with design capabilities for digital,
analog, and combined digital/analog ICs along
with a wafer fabrication capability that includes
both Bipolar and CMOS technologies.
SpeGification

Approval

fabrication facility designed especially for
custom and "Application-Specific" lC's, we can
cut custom design time down to readily
acceptable limits.

Design &
Layout
Mask
Fabrication

Integrated Solution for You
So whether your requirements fall in our specialty areas of telecommunications and rotating
memories, or other application areas appropriate for custom/semicustom lC's, we offer the
advantages of a complete IC development and
production operation; single-point accountability, smooth progress through all phases of a
project, and a high level of quality assurance.
The result: reduced time and cost to produce
the best custom/semicustom IC's available.

Wafer
Fabrication

Wafer
Testing
Production
Assembly

Final
Test

3-1

VERSATILITY - THE OPTIMUM APPROACH FOR EACH CUSTOMER

Silicon Systems has focused on the ASIC
(Application Specific Integrated Circuit) market
for over 10 years and has developed a versatile
offering of customized components that covers
the design spectrum.
The digital market can be satisfied by our Mask
Programmed Logic Arrays (MPLA) for implementation of complex logic functions and by
our full custom or standard cell library for large
scale system designs.

at Silicon Systems which allows quick turnaround from design concept to working silicon.
The ultra-clean wafer fab supports both Bipolar
and CMOS technologies with high and low
voltage options as well as single or double
layer metal interconnections. These variations
permit us to select the optimum process when
fabricating a new circuit.
DIGITAL APPLICATION SPECTRUM
No. of Gates
1000

1500

2000

2500

3000

3500

Fig.1

Our standard cell library is implemented on the
CC process (311m silicon gate CMOS) allowing
high density, low power digital and analog
functions to be integrated, while operating with
standard 5-volt levels. The proprietary "CD"
process extends operation from 3.5V to 14V for
higher performance analog or analog/digital
functions while our proprietary Bipolar "BJ"
process offers extremely high density and performance combined with very low noise.

Table 1

The analog market is served by our Bipolar
analog array for moderate complexity needs,
by switch capacitor arrays for filter needs and
by full custom or standard cell library for
higher levels of sophistication. All four design
technologies also accommodate full analog
and digital integration on the same chip for
total system solutions.
Design engineering, semiconductor processing
and testing are all housed in the same facility

Silicon Systems also offers full capability for
supporting Customer Owned Tooling (COT)
with any of our industry standard processes.

Table 28

3-2

4000

4500

5000

5500

7000

7500

aooo

INTEGRATED DESIGN METHODOLOGY - THE IDM'" ADVANTAGE

When deciding to convert a system or subsystem design to silicon the user can choose
either a fully customized approach or a
semi-customized approach, each with its
own benefits. For these designs SSi offers the
alternatives of fully "handcrafted" custom
design in CMOS and Bipolar or standard cell
design in CMOS. As seen in Table 3, the fully
individualized custom gives the advantages of
chip size (lower production cost) and highest

With Computer Aided Design (CAD) playing a
major role in our product development cycle,
SSi has developed an Integrated Design system
that accommodates an interlocking set of
design methods all supported by a single CAD
system. This Integrated Design Methodology
(10M''') allows the user to design at the transistor level (either composite or symbolic), at a
procedural macro level (silicon compiler), with

INTEGRATED DESIGN METHODOLOGY

TRANSISTOR
LEVEL DESIGN

PERFORMANCE

COST

HIGHEST

LOWEST

SI
AREA

DESIGN TIME

DEGREE OF
AUTOMATION

LONG

LOW

GENERATED
MACROS

PREDESIGNED
BUILDING
BLOCKS

STANDARD
CELLS

(GATE ARRAYS)
Figure 2

performance (speed, input offset, etc.) while
semicustom, using a pre-characterized
standard cell library, offers the advantages of
lower NRE, faster turnaround and somewhat
higher first article success rate. SSi adds to
the flexibility of the standard cell concept by
its willingness to develop special cells as
needed to satisfy design requirements that lie
between the two custom design technologies.
MACRO IC USING 10M

Table 3

Parameterized Building Blocks (PBB), or with
conventional standard cells. Each of these
design levels has a unique set of attributes, as
shown in Figure 2, accessible in a "mix or match"
manner under 10M. This enables an efficient
performance/design-time tradeoff.

3-3

"CUSTOMIZED SERVICE" - TOTAL SUPPORT FROM CONCEPT THROUGH FINAL TEST

Silicon Systems offers experienced staffing
throughout its organization along with stateof-the-art CAD and processing facilities to
efficiently develop customized products.

CUSTOMER

CUSTOMER INTERFACE

We start with a large, expert staff of design
engineers to help define the product from both
the system and silicon aspects. The design is
then developed using our advanced CAD tools
and programs including ALICE (Automated
Layout for Integrated Circuit Engineering),
which accurately handles chip design from
schematic input to pattern generator output, all
within one system. SSi engineers utilize an
advanced version of "SPICE" to simulate DC,
transient, noise, distortion, and AC response for
CMOS and Bipolar. It accurately models such
second order effects as weak-inversion,
high-level injection, temperature dependent
mobility, etc.
SSi has adapted a special program called
"SWITCAP" for switched-capacitor filter
frequency domain analysis which accurately
predicts the frequency response of switchedcapacitor filters. Our Automatic Network
Intertrace Algorithm (ANITA'") compares the
network description generated from the captured
circuit to the layout as it proceeds. This guarantees that no interconnection errors exist
and that all component sizes and tolerances
match those used in the design analysis. The
completed design goes through a masking
procedure and the wafers are run in our
ultramodern class 10 (lOppm particulate count)
wafer fabrication facility. It is a "paperless"

Figure 3

and continuous facility monitoring.

Table 4

environment accomplished by downloading
process information to in-place terminals and
processing equipment. The PROM IS (process
Management Information Systems) program
that accomplishes this control provides workin-process tracking, engineering data collection,

After the wafer prototype is fabricated, SSi
packages a few representative chips using
in-house assembly for design verification. The
units are tested in-house by one of our
advanced analog or digital tester. We can test
your circuit with your existing test program or
help you create a test program from your
specification.
After approval of prototypes or characterization
lots (if needed) the final step is off-shore
assembly for volume production.
We can also perform hi-rei screening and
burn-in, if desired.
3-4

SSi

CUSTOM - THE "TAILORED" APPROACH

Table 10

The above tables show some of our
demonstrated high performance design capabilities in Bipolar and CMOS. These analogi
digital chips cover a wide range of challenging
circuit functions that were designed for a
diversity of system applications.

Table 11

As part of a total capability SSi offers commercial, industrial, and hi-rei product flows, as
well as packaging options that include Dual-inLine, Flatpacks, and plastic Quads. For further
detailed information on product flow and
packaging call SSi or refer to our Quality and
Reliability Brochure.
3-5

Section 4

STANDARD
CELLS

4

STANDARD CELL LIBRARY - ANALOG AND DIGITAL

Table 5

The standard cells shown in Table 5 represent
the basic building blocks or "primitives" of our
present library. In addition to these cells,
macros are already scheduled for functions
such as RAM, ROM, PLA etc. Others can be
generated and added to the library on an "as
needed" basis. As part of the SSi flexibility in
custom we will design new cells to accommodate any feasible "special" requirements.

Table 7

The characteristics shown in Table 6 are
indicative of our cell library in 5 Volt 311m Si
gate CMOS (CC process). An additional library
of higher performance analog cells will be made
available on our CD process.

Table 6

4-1

JbJl rJfonf

BASIC
STANDARD
CELL LIST

INTEGRATION

CELL NUMBER

CELL NUMBER

DESCRIPTION

BASIC LOGIC FUNCTIONS
21N NOR GATE
Cl120
Cl130
31N NOR GATE
41N NOR GATE
Cl140
2 IN NAND GATE
C1220
3 IN NAND GATE
C1230
C1240
4 IN NAND GATE
INVERT/NON-INVERT PAIR
C1300
INVERTER (lX)
C1310
TRANS. GATE (ENABLE<)
C1320
DUAL TRANS. GATE (COMP ENABLES)
C1330
INVERTER TRI STATE (ENABLE<)
C1360
BUFFER TRI STATE (ENABLE<)
C1380
LATCH W/S<
C1410
C1420
LATCH R/S
C1430
LATCH R R/S (CROSS COUPLED NORS)
LATCH W R
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Create Date                     : 2013:10:20 11:08:34-08:00
Modify Date                     : 2013:10:20 20:56:40-07:00
Metadata Date                   : 2013:10:20 20:56:40-07:00
Producer                        : Adobe Acrobat 9.55 Paper Capture Plug-in
Format                          : application/pdf
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Page Layout                     : SinglePage
Page Mode                       : UseNone
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