1986_Siliconix_FET_Databook 1986 Siliconix FET Databook

User Manual: 1986_Siliconix_FET_Databook

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January 1986
Small-Signal

FET

Data Book

Siliconix

Siliconix Incorporated reserves the right to make changes In the circUitry or

specifications at any time without notice and assumes no responsibility for
the use of any circuits described herein and makes no representations that
they are free from patent infringement

Warning Regarding Lile Support Applications

Siliconix products are not sold for applications In any medical equipment
Intended for use as a component of any life support system unless a specIfic
written agreement pertaining to such Intended use IS excecuted between the
manufacturer and Siliconix Such agreement will require the equipment
manufacturer either to contract for additional reliability testing of the Slllconix
parts and/or to commit to undertake such testing as a part of ItS
manufactUring process In addition, such manufacturer must agree to
indemnify and hold Siliconix harmless from any claims arising out of the use
of the Slllconix parts In life support equipment
.

Stresses listed under "Absolute Maximum Ratings" may be applied (one at a
time) to devices without resulting In permanent damage This is a stress
rating only and not subject to production testing. Exposure to absolute
maXimum rating conditions for extended periods may effect device reliability

© 1986 Siliconix Incorporated
Printed in U.S.A.

Siliconix

Introduction
Design Alternatives
Data Sheets
Geometry
Selector Guides
Package Data
Application Notes
Worldwide Sales Offices
Siliconix

_
_
_
_,
_
_,
_
_

7

Table of Contents
Section 1. Introduction
Small Signal FET ....................................................................... 1-1
Glossary of Terms and Abbreviations .................................................... 1-2
How to Use the Cross Reference ......................................................... 1-5
Cross Reference ........................................................................ 1-6
Product Information ....................................................................1-17
Hi-Rei Capabilities ......................................................................1-18
Process Option Flow Chart ..............................................................1-19
Additional Product Options for European Customers ...................................... 1-20
Die Process Information ................................................................1-21

Section 2. Design Alternatives
The Source for FETs ..................... 2-1
Using JFETs as Front-End Devices
for Op Amps ............................ 2-2
Compare Using JFETs as Front-End
Devices ................................. 2-2
JFETs as Front-End Devices with a
BiFET Op Amp ........................... 2-2
Using FETs as Analog Switches .......... 2-3
Using JFETs as Diodes ................... 2-3
FETs as Current Regulator ................ 2-4

Section 3. Data Sheets
2N3819 ................................. 3-1
2N3821 ................................. 3-2
2N3822 ................................. 3-2
2N3823 ................................. 3-2
2N3824 ................................. 3-3
2N3921 ................................. 3-4
2N3922 ................................. 3-4
2N3954 ................................. 3-5
2N3954A ................................ 3-5
2N3955 ................................. 3-5
2N3955A ................................ 3-5
2N3956 ................................. 3-6
2N3957 ................................. 3-6
2N3958 ................................. 3-6
2N3970 ................................. 3-7
2N3971 ................................. 3-7
2N3972 ................................. 3-7
2N4084 ................................. 3-4
2N4085 ................................. 3-4
2N4091 ................................. 3-8
2N4092 ................................. 3-8
2N4093 JAN TX ......................... 3-8
2N4117 ................................. 3-9
2N4117 A ................................ 3-9
2N4118 ................................. 3-9
2N4118A ................................ 3-9

2N4119 ................................. 3-9
2N4119A ................................ 3-9
2N4220 ................................3-10
2N4220A ...............................3-10
2N4221 ................................3-10
2N4221A ...............................3-10
2N4222 ................................3-10
2N4222A ...............................3-10
2 N4223 ................................3-11
2 N4224 ................................3-11
2N4338 ................................3-12
2N4339 ................................3-12
2N4340 ................................3-12
2N4341 ................................3-12
2N4391 ................................3-13
2N4392 ................................3-13
2N4393 ................................3-13
2N4416 ................................3-14
2N4416A ...............................3-14
2N4856 ................................3-15
2N4856A ...............................3-16
2N4857 ................................3-15
2N4857A ...............................3-16
2N4858 ................................3-15
2N4858A ...............................3-16
2N4859 ................................3-15
2N4859A ...............................3-16
2N4860 ................................3-15
2N4860A ...............................3-16
2N4861 JAN TX ........................3-15
2N4861A ...............................3-16
2N4867 ................................3-17
2N4867A ...............................3-17
2N4868 ................................3-17
2N4868A ...............................3-17
2N4869 ................................3-17
2N4869A ...............................3-17
2N5018 ................................3-18
2N5019 ................................3-18
2N5045 ................................3-19

Silicanix

Table of Contents (Continued)
Section 3. Data Sheets (Cont'dj
2N5046
2N5047
2N5114
2N5115
2N5116
2N5196
2N5197
2N5198
2N5199
2N5432
2N5433
2N5434
2N5452
2N5453
2N5454
2N5457
2N5458
2N5459
2N5460
2N5461
2N5462
2N5463
2N5464
2N5465
2N5484
2N5485
2N5486
2N5515
2N5516
2N5517
2N5518
2N5519
2N5520
2N5521
2N5522
2N5523
2N5524
2N5545
2N5546
2N5547
2N5564
2N5565
2N5566
2N5638
2N5639
2N5640
2N5902
2N5903
2N5904
2N5905

................................3-19
................................3-19
................................3-20
................................3-20
JAN TX ........................3-20
................................3-21
................................3-21
................................3-21
................................3-21
................................3-22
................................3-22
................................3-22
................................3-23
................................3-23
................................3-23
................................3-24
................................3-24
................................3-24
................................3-25
................................3-25
................................3-25
................................3-25
................................3-25
................................3-25
................................3-26
.............. " ................. 3-26
................................3-26
................................3-27
................................3-27
............................... :3-27
................................3-27
................................3-27
................................3-27
................................3-27
................................3-27
................................3-27
'................................3-27
................................3-28
................................3-28
................................3-28
................................3-29
................................3-29
................................3-29
................................3-30
................................3-30
................................3-30
................................3-31
................................3-31
................................3-31
................................3-31

2N5906 ................................3-31
2N5907 ................................3-31
2N5908 ................................3-31
2N5909 ................................3-31
2N5911 ................................3-32
2N5912 ................................3-32
2N6905 ................................3-33
2N6906 ................................3-33
2N6907 ................................3-33
2N6908 ................................3-34
2N6909 ................................3-34
2N6910 ................................3-34
2N6911 ................................3-35
3N163 .................................3-36
3N164 .................................3-36
BF244A ................................3-37
BF244B ................................3-37
BF244C ................................3-37
BF245A ................................3-38
BF245B ................................3-38
BF245C ................................3-38
BF256LA ...............................3-39
BF256LB ...............................3-39
BF256LC ...............................3-39
CR022 through CR530 .................. 3-40
CRR0240 through CRR4300-2 ............ 3-41
DN5564 ................................3-43
DN5565 ................................3-43
DN5566 ................................3-43
DN5567 ................................3-44
DPAD1 .................................3-45
DPAD2 .................................3-45
DPAD5 .................................3-45
DPAD10 ................................ 3-45
DPAD20 ................................3-45
DPAD50 ................................3-45
DPAD100 ...............................3-45
FN4117 ................................3-46
FN4117A ...............................3-46
FN4118 ................................ 3-46
FN4118A ...............................3-46
FN4119 ................................3-46
FN4119A ...............................3-46
FN4392 ................................3-47
FN4393 ................................3-47
J105 ...................................3-48
J106 ...................................3-48
J107 ...................................3-48
J108 ...................................3-49
J109 ...................................3-49

Siliconix

Table of Contents (Continued)
Section 3. Data Sheets (Cont'd)
J110 ...................................3-49
J111 ...................................3-50
J111A ..................................3-51
J112 " .................................3-50
J112A ..................................3-51
J113 ...................................3-50
J113A ..................................3-51
J174 ...................................3-52
J175 ...................................3-52
J176 ...................................3-52
J177 ...................................3-52
J201 ...................................3-53
J202 ...................................3-53
J203 ...................................3-53
J204 ...................................3-53
J210 ...................................3-54
J211 ...................................3-54
J212 ...................................3-54
J230 ...................................3-55
J231 ...................................3-55
J232 ...................................3-55
J270 ...................................3-56
J271 ...................................3-56
J300 ...................................3-57
J304 ...................................3-58
J305 ...................................3-58
J308 ...................................3-59
J309 ...................................3-59
J310 ...................................3-59
J500 ...................................3-60
J501 ...................................3-60
J502 ...................................3-60
J503 ...................................3-60
J504 ...................................3-60
J505 ...................................3-60
J506 ...................................3-61
J507 ...................................3-61
J508 ...................................3-61
J509 ...................................3-61
J510 ...................................3-61
J511 ...................................3-61
J552 ...................................3-62
J553 ...................................3-63
J554 ...................................3-63
J555 ...................................3-63
J556 ...................................3-63
J557 ...................................3-63
JPAD5 .................................3-64
JPAD10 ................................3-64
JPAD20 .............................. , .3-64

J PAD50 ................................3-64
JPAD100 ...............................3-64
JPAD200 ...............................3-64
JPAD500 ...............................3-64
JR135V ................................3-65
JR170V ................................3-65
JR200V ................................3-65
JR220V ................................3-65
JR240V ................................3-65
M440 ..................................3-66
M441 ..................................3-66
M5911 .................................3-67
M5912 .................................3-67
MFE823 ................................3-68
MPF102 ................................3-69
MPF108 ................................3-70
MPF109 ................................3-71
MPF111 ................................3-72
MPF112 ................................3-73
P1086 ..................................3-74
P1087 ..................................3-74
PAD1 ..................................3-75
PAD2 ..................................3-75
PAD5 ..................................3-75
PAD10 .................................3-75
PAD20 .................................3-75
PAD50 .................................3-75
PAD100 ................................3-75
PN4091 ................................3-76
PN4092 ................................3-76
PN4093 ................................3-76
PN4117 ................................3-77
PN4117A ...............................3-77
PN4118 ................................3-77
PN4118A ...............................3-77
PN4119 ................................3-77
PN4119A ...............................3-77
PN4120 ................................3-77
PN4120A ...............................3-77
PN4302 ................................3-78
PN4303 ................................3-78
PN4304 ................................3-78
PN4391 ................................3-79
PN4392 ................................3-79
PN4393 ................................3-79
PN4416 ................................3-80
PN5163 ................................3-81
SD210DE ...............................3-82
SD211DE ...............................3-84
SD212DE ...............................3-82

Siliconix

Table of Contents (Continued)
Section 3. Data Sheets (Cont'd)
S02130E ...............................3-84
S02140E ...............................3-82
S02150E ...............................3-84
S02100 ................................3-86
S02110 ................................3-88
S02120 ................................3-88
S05000 ................................3-90
S05001 ................................3-90
S05002 ..........•.....................3-90
S05200 ................................3-95
S05400 ................................3-98
S05401 ................................3-98
S05402 ................................3-98
Si1800 ............................... 3-103
Si2400 ............................... 3-104
Si8901 ............................... 3-106
SSTlll .............................. 3-108
SST112 .............................. 3-108
SSTl13 .............................. 3-108
SST174 .............................. 3-109
SST175 .............................. 3-109
SST176 .............................. 3-109
SSTl77 .............................. 3-109
SST201 .............................. 3-110
SST202 .............................. 3-110
SST203 .............................. 3-110
SST204 .............................. 3-110
SST211 .............................. 3-111
SST213 .............................. 3-111

SST215 .............................. 3-111
SST308 ..............................
SST309 ..............................
SST310 ..............................
SST404 ..............................
SST405 ..............................
SST406 ..............................
SST4416 .............................
U200 ................................
U201 ................................
U202 ................................
U231 ................................
U232 ................................
U233 ................................
U234 ................................
U235 ................................
U257 ................................
U290 ................................
U291 ................................
U304 ................................
U305 ................................

3-113
3-113
3-113
3-114
3-114
3-114
3-115
3-116
3-116
3-116
3-117
3-117
3-117
3-117
3-117
3-118
3-119
3-119
3-120
3-120

U306 ................................ 3-120
U308 ................................ 3-121
U309 ................................ 3-121
U310 ................................ 3-121
U311 ................................ 3-122
U320 ................................ 3-123
U321 ................................ 3-123
U322 ................................ 3-123
U350 ..........................•..... 3-124
U401 ................................ 3-125
U402 ................................ 3-125
U403 ................................ 3-125
U404 ................................ 3-125
U405 ................................ 3-125
U406 ................................ 3-125
U410 ................................ 3-126
U411 ................................ 3-126
U412 ................................ 3-126
U421 ................................ 3-127
U422 ................................ 3-127
U423 .........................•...... 3-127
U424 ................................ 3-127
U425 ................................ 3-127
U426 ................................ 3-127
U427 ................................ 3-128
U428 ................................ 3-128
U430 ................................ 3-129
U431 ................................ 3-129
U440 ................................ 3-130
U441 ................................ 3-130
U443 ................................ 3-130
U444 ................................ 3-130
U1897 ............................... 3-131
U1898 ............................... 3-131
U1899 ............................... 3-131
VCR2N ............................... 3-132
VCR3P ............................... 3-132
VCR4N ............................... 3-132
VCR7N ............................... 3-132
VCRllN ............................. 3-134

Section 4. Geometry
Useful JFET Parameter Relationships .. " .4-1
OMCA ................................. 4-2
OMCB .................................. 4-2
MBN .................................. 4-4
MRA ................................... 4-6
NCB ................................... 4-8
NCL ................................. .4-11

Siliconix

Table of Contents (Continued)
Section 4. Geometry (Cont'd)
NH ................................... .4-12
NIP ...................................4-15
NKL .................................. .4-17
NKM ................................. .4-18
NKO ..................................4-19
NNR ................................. .4-20
NNT ..................................4-22
NNZ ................................. .4-24
NPA ................................. .4-25
NQP ................................. .4-28
NRL ...................................4-30
NT ................................... .4-32
NVA ................................. .4-34
NZA ................................. .4-35
NZB ...................................4-35
NZF ...................................4-37
PSA .................................. .4-40
PSB ...................................4-40
PSC-B ................................ .4-42
VRMA ................................ .4-43

Section 5. Selector Guides
Tips on Selecting the Right FET for Your
Application ............................. 5-1
Application Selection Preferences ........ 5-2
Product Selector Guide .................. 5-3
Application Parameter Importance Guide .5-4
JFET Geometry Selector Guide .......... 5-7
Product Specifications .................. 5-10

Section 6. Package Data
TO-18
TO-18
TO-52
TO-71
TO-72
TO-78
TO-92
TO-92

(2-pin) ........................... 6-1
(3-pin) ........................... 6-1
.................................. 6-1
.................................. 6-1
.................................. 6-2
.................................. 6-2
.................................. 6-2
Lead Form ........................ 6-2

TO-99 .................................. 6-2
TO-92 Taping Specifications ............. 6-3
SOT-23 ................................. 6-4
SOT143 ................................ 6-4
SOIC-8 pin ............................. 6-4
16-Lead DIP Plastic ...................... 6-5
16-Lead DIP Ceramic .................... 6-5
14-Lead SO Plastic ...................... 6-6

Section 7. Application Notes
An Introduction to FETs ................. 7-1
FET Biasing ............................7-12
Composite Op Amp for
High Performance ...................... 7-22
Applications for the Si1000 Series JFET
Amplifier ..............................7-25
FETs for Video Amplifiers ............... 7-31
Audio-Frequency Noise Characteristics of
Junction Fets ..........................7-39
Differential JFET Amplifier ..............7-47
Wideband UHF Amplifier with HighPerformance FETs ......................7-49
High-Performance FETs In Low-Noise
VHF Oscillators .........................7-52
FETs in Balanced Mixers ................7-55
A New Current Limiter Extends
Protection to 240V ......................7-65
The FET Constant Current Source .......7-71
Build a Precision Constant
Current Source ......................... 7-73
FETs as Voltage-Controlled Resistors ....7-75
FETs as Analog Switches ...............7-84
DMOS FET Analog Switches and Switch
Arrays .................................7-92
A High Performance Video Switch Using
the SD5002 ........................... 7-100
A High Quality Audio
Crosspoint Switch .................... 7-105

Section 8. Worldwide Sales Offices .... 8-1

Siliccnix

Introduction __

Siliconix

-;>

Small Signal FEY
Present Position:
Siliconix specializes in offering a broad product line of Nand P Channel JFETs, N-Channel OMOS and N &
P-Channel MOS products. Our packaging capabilities range from hermetically sealed metal cans, plastic TO-92 and
surface mount packages to side braze type packages for switch arrays. These proucts are geared to offer design
alternatives to our customers. We specialize in ultra low leakage, low noise, high gain/slew rate, low ROS(on), and
high speed switching.
Future Product Plans:
Expanding the already broad FET product line will focus on the following new product areas:
o High current, high voltage current regulator
IF 10-100 rnA
BV'" 100V
o Series of depletion mode lateral OMOS devices for use in high gain amplification.
o Surface mount additions will include SOT143 (4 leaded SO package) and S08 (8 leads).

Silicanix

1-1

ut

Glossary of Terms and Abbreviations
--...o 1. Upper case letters indicate DC voltages and currents .
--a 2. Lower case letters indicate AC voltages and currents.
C

f

.a
.a

c:c

"'a

c

a
ut

.E
..a>-

~
'too
o
ut
ut

o

ij

3. Subscripts can refer to the terminals used in the measurements, I.e., VG
bol, i.e., tf = Fall Time, tr = Rise Time .

=

H

Siliconix

Gate Voltage; or simply help define the sym-

4. Triple subscripts are used for terminal references only. The first subSCript IS the object terminal. The second subSCript IS
the common terminal. The third gives the condition of the remaining termlnal(s). S = Short, 0 = open and X = neither
open nor short (refer to the test conditions). Example: BVGSS = Breakdown Voltage from gate to source with the drain
shorted to the source.
btg

= Common-Gate Forward Susceptance

Cgs

= Gate- Source Capacitance

bts

= Common-Source Forward Susceptance

Ciss

= Common-Source Input Capacitance

bigs

= Common-Gate Input Susceptance

Coss

= Common-Source Output Capacitance

biss

= Common-Source Input Susceptance

Crss

= Common-Source Reverse Transfer CapacI-

bOgS

= Common-Gate Output Susceptance

boss

= Common-Source Output Susceptance

brg

= Common-Gate Reverse Susceptance

b rs

= Common-Source Reverse Susceptance

BVOGO

= Drain-Gate Breakdown Voltage with

tance

Source Open

Csb

= Source-Body Capacitance

Csd

= Source-Drain Capacitance

Csgo

= Source-Gate Capacitance

0

= Drain

eN

= Equivalent Short-Circuit Input Noise
Voltage

BVOSS

= Drain-Source Breakdown Voltage with
Gate Shorted

BVSDX

= Drain-Source Breakdown I(0ltage

fm

= Figure of Merit

G

= Gate

91g

= Common-Gate Forward TransconductancE

91s

= Common-Source Forward Transconduc-

Tied to Reference Voltage
BVG1SS

= Gate 1-to-Sou rce Breakdown Voltage

with Gate Shorted

tance
BVG2SS

= Gate 2-to-Sou rce Breakdown Voltage

with Gate Shorted

gfso

= Common·Source

tance @VGS
BVGSS

Forward Transconduc·

=0

= Gate-Source Breakdown Voltage with

9fs1/9fs2

Gate Shorted

= Common-Source Forward Transconduc-

tance Ratio
BVSDS

= Source-Drain Breakdown Voltage with

Gate Shorted
BVSGO

= Source-Gate Breakdown Voltage with

Cli9

= Common-Gate Input Conductance

9is

= Common-Source Input Conductance

909

= Common- Gate

90S

= Common-Source Output Conductance

90ss

= Common-Source Output Conductance @

Source Open
Cdb

= Drain-Body Capacitance

Cd90

= Drain-Gate Capacitance

Cgb

= Gate-Body Capacitance

Cgd

= Gate-Drain Capacitance

1-2

VGS
gos1-gos2

Siliconix

=

Output Conductance

0

= Differential Output Conductance

Glossary of Terms and Abbreviations (Cont'd)
= Common-Gate Power Gain
=

Common-Source Power Gain

10(off)

=

Oraln Cutoff Current

10(on)

= Drain ON Current

lOGO

= Drain-Gate Leakage

lOSS

=

Saturation Orain Current with Gate
Shorted

IOSS1/IOSS2 = Saturation Orain Current Ratio
=

Forward Current

Re (Vig)

=

Common-Gate Input Conductance

Re (Vis)

= Common-Gate Output Conductance

Common-Source Output Conductance

Re (Vos)

=

Re (V rg )

= Common-Gate Reverse Transconductance

Re (V rs )

=

S

= Source

td

=

Delay Time

Id(off)

=

Turn-Off Delay Time

Id(on)

=

Turn-On Delay Time

Common-Source Reverse Transconductance
= Common-Source Input Resistance

= Fall Time

= Gate Operating Current

=

Junction Temperature

=

Gate-to-Gate Leakage Current

=

Differential Gate Operating Currents

loff

= Turn-Off Time

=

Gate-to-Body Leakage Current with Gate
Shorted

ton

= Turn-On Time

= Lead Temperature
= Gate Forward Current
= Gate Reverse Current with Gate Shorted
= Storage Temperature

Tstg
IG1SS

= Gate 1-to-Source Leakage Current with
= Body Voltage

Gate Shorted
=

IG2SSR

Gate 2-to-Source Leakage Current with
Gate Shorted

VBB

= Body Supply Voltage

Vo

= Drain Voltage

=

Gate 1-to-Source Reverse Leakage Current

VOO

= Drain Supply Voltage

=

Gate 2-to-Source Reverse Leakage Current

VDS(on)

= Orain-Source ON Voltage

=

Equivalent Open-Circuit NOise Current

Ip

= Pinch-Off Current

NF

=

NOise Figure

=

Continuous Power Dissipation

=

Peak Operatl ng Voltage

= Gate Voltage

= Gate Supply Voltage
=

IVGS1-VGS21

= Differential Gate-Source Voltage
=

POV

Ll.IVgs1-Vgs21

= Drain-Source ON Resistance

Ll. T

Gate-Source Voltage

Oifferentlal Gate-Source Voltage

= Differential Gate-Source Voltage Change
with Temperature

VGS(f)

= Gate-Source Forward Voltage

= Common-Gate Forward Transconductance

VGS(th)

=

Common-Source Forward Transconductance

VGS(off)

= Gate Source Cutoff Voltage

rOS(on)

=

Re (Yfg)
Re (Yfs)

=

Static Drain-Source ON Resistance

Siliconix

Gate Threshold Voltage

1-3

'" Glossary of Terms and Abbreviations (Cont'd)
g

..

..-a

!

.a
.a
C
"'U
C

a
'"E

VG1S(off)

= Gate

1 to Source Cutoff Voltage

VG2S(off)

= Gate 2 to Source Cutoff Voltage

Vs

= Source Voltage

VSS

= Sou rce Supply Voltage

Zd

= Dynamic

Zk

= Knee AC

0.

= Current Temperature Coefficient

°J-A

= Junction to Ambient Thermal

0J-C

=Junction to Case Thermal

Impedance

.

..

~
o

t-

a
'"'"o

i5

1-4

Siliconix

Impedance

Resistance

Resistance

"7

How to Use the Small-Signal
FET Cross Reference
The following examples illustrate how the FET Cross Reference and Index should be used:

Case (1)

Recommended replacement offered by Siliconix is identical to Industry Part Number.

Industry Part Number

Type and Classification

Recommended Replacement

2N4391

N JFET

2N4391

Case (2)

Recommended replacement offered by Siliconix is not identical to Industry Part Number.

Industry Part Number

Type and Classification

Recommended Replacement

2N3457

N JFET

2N4338

The recommended replacement may be exact, tighter or looser on electrical characteristics, and may
be a different package or pin-out. Data sheets for both parts should, if possible, be reviewed for a complete comparison.
Type and classification abbreviations are described as follows:
BF
CR
CRR

(JFET Plastic)
(Current Limited)
(Current Limiter)
o
(Dual)
OM
N-Channel DMOS
ON
(Dual N-Channel Metal Can)
DPAD (Dual Pico Ampere Diode)
FN
(N-Channel Metal Can)

ENH
JPAD
JR
N

P
PAD

SO
SI

SST

Siliconix

(Enhancement-Mode Normally-Off)
(Plastic Pico Ampere Diode)
(Plastic High Voltage Diode)
(N-Channel)
(P-Channel)
(Pico Ampere Diode)
(N-Channel DMOS)
(N-Channel FETs)
(JFET in SOT-23 Plastic Package
SOT-143
SOIC-8 Pin)

II1II

1-5

Small-Signal FEY Cross Reference
Industry
Part Number

Data
Sheet
Page

Geometry
Page

Industry
Part Number

Type and
Classification

Recommended
Replacement

Data
Sheet
Page

Geometry
Page

Type and
Classification

Recommended

lN5283
lN5284
lN5285
lN5286
lN5287

CL
CL
CL
CL
CL

N JFET
N JFET
N JFET
N JFET
N JFET

CR022
CR024
CR027
CR030
CR033

2N3457
2N3458
2N3459
2N3460
2N3608

N JFET
N JFET
N JFET
N JFET
PMOS ENH

2N4338
2N434l
2N434l
2N4340
3N163

lN5288
lN5289
lN5290
lN529l
lN5292

CL
CL
CL
CL
CL

N JFET
N JFET
N JFET
N JFET
N JFET

CR039
CR043
CR047
CR056
CR062

2N3684
2N3685
2N3686
2N3687
2N38l9

N JFET
N JFET
N JFET
N JFET
N JFET

2N4339
2N4339
2N4340
2N434l
2N38l9

lN5293
lN5294
lN5295
lN5296
lN5297

CL N JFET
CL N JFET
CL N JFET
CL N JFET
CL N JFET

CR068
CR075
CR082
CR09l
CR100

2N3820
2N382l
2N3822
2N3823
2N3824

P JFET
N JFET
N JFET
N JFET
N JFET

J270
2N382l
2N3822
2N3823
2N3824

lN5298
lN5299
lN5300
lN530l
lN5302

CL
CL
CL
CL
CL

N JFET
N JFET
N JFET
N JFET
N JFET

CRll0
CR120
CR130
CR140
CR150

2N392l
2N3922
2N3954
2N3954A
2N3955

o N JFET
o N JFET
o N JFET
o N JFET
ON JFET

2N392l
2N3922
2N3954
2N3954A
2N3955

lN5303
lN5304
lN5305
lN5306
lN5307

CL N JFET
CL N JFET
CL N JFET
CL N JFET
CL N JFET

CR160
CR180
CR200
CR220
CR240

2N3955A
2N3956
2N3957
2N3958
2N3967

ON JFET
ON JFET
o N JFET
ON JFET
N JFET

2N3955A
2N3956
2N3957
2N3958
2N422l

lN5308
lN5309
lN53l0
lN53ll
lN53l2

CL N JFET
CL N JFET
CL N JFET
CL N JFET
CL N JFET

CR270
CR300
CR330
CR360
CR390

2N3967A
2N3968
2N3968A
2N3969
2N3970

N JFET
N JFET
N JFET
N JFET
N JFET

2N422l
2N4339
2N4339
2N4339
2N3970

0

2N397l
2N3972
2N4084
2N4085
2i'1q091

N JFET
N JFET
ON JFET
ON JFET
i'I JFET

2N397l
2N3972
2N4084
2N4085
2i11q091

en

2N4091A
2N4092
2N4092A
2N4093
2N4093A

N JFET
N JFET
N JFET
N JFET
N JFET

2N409l
2N4092
2N4092
2N4093
2N4093

N JFET
N JFET
N JFET
N JFET
N JFET
N JFET
PMOS ENH
N JFET
N JFET
N JFET

2N4l17
2N4l17A
2N4ll8
2N4ll8A
2N4ll9
2N4ll9A
3N163
2N3822
2N4220
2N4220A

Replacement

~

0
0

10

as
'lil

0

t:ii

U.

"iii
c::

Ol

en

lN53l3
lN53l4
2N3066
2N3067
2N30a8

CL N JFET
CL N JFET
N JFET
N JFET
N JFET

CR430
CR470
2N4340
2N4338
2N433ii

2N3069
2N3070
2N307l
2N3084
2N3085

N JFET
N JFET
N JFET
N JFET
N JFET

2N434l
2N4339
2N4338
2N434l
2N434l

2N3086
2N3087
2N3088
2N3088A
2N3089

N JFET
N JFET
N JFET
N JFET
N JFET

2N434l
2N434l
2N4339
2N4339
2N4339

2N3089A
2N3365
2N3366
2N3367
2N3368

N JFET
N JFET
N JFET
N JFET
N JFET

2N4339
2N4340
2N4338
2N4338
2N434l

2N4l17
2N4l17A
2N4ll8
2N4ll8A
2N4ll9
2N4ll9A
2N4l20
2N4l39
2N4220
2N4220A

2N3369
2N3370
2N3436
2N3437
2N3438

N JFET
N JFET
N JFET
N JFET
N JFET

2N4340
2N4339
2N434l
2N434l
2N434l

2N422l
2N4221A
2N4222
2N4222A
2N4223

N JFET
N JFET
N JFET
N JFET
N JFET

2N422l
2N4221A
2N4222
2N4222A
2N4223

2N3452
2N3453
2N3454
2N3455
2N3456

N JFET
N JFET
N JFET
N JFET
N JFET

2N4340
2N4338
2N4338
2N4340
2N4338

2N4224
2N4267
2N4302
2N4303
2N4304

N JFET
PMOS ENH
N JFET
NJFET
NJFET

2N4224
3N163
PN4302-l8
PN4303-l8
PN4304-l8

1-6

~

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CD

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:7

Small-Signal FET Cross Reference (Cont'd)
Data
Sheet
Page

Geometry
Page

Industry
Part Number

Type and
Classillcalion

Recommended

Data
Sheet
Page

Geometry
Page

Type and
Classllicatlon

Recommended
Replacement

2N4338
2N4339
2N4340
2N4341
2N4352

N JFET
N JFET
N JFET
N JFET
PMOS ENH

2N4338
2N4339
2N4340
2N4341
3N163

2N5103
2N5104
2N5105
2N5114
2N5115

N JFET
N JFET
N JFET
P JFET
P JFET

2N4416
2N4416
2N4416
2N5114
2N5115

2N4382
2N4391
2N4392
2N4393
2N4416

P JFET
N JFET
N JFET
N JFET
N JFET

2N5115
2N4391
2N4392
2N4393
2N4416

2N5116
2N5158
2N5159
2N5196
2N5197

P JFET
N JFET
N JFET
ON JFET
ON JFET

2N5116
2N5434
2N5433
2N5196
2N5197

2N4416A
2N4445
2N4446
2N4447
2N4448

N JFET
N JFET
N JFET
N JFET
N JFET

2N4416A
2N5432
2N5433
2N5432
2N5433

2N5198
2N5199
2N5245
2N5246
2N5247

ON JFET
ON JFET
N JFET
N JFET
N JFE

2N519B
2N5199
PN4416
J305-18
J304-1B

2N4B56
2N4B56A
2N4856JAN
2N4856JANTX
2N4B56JANTXV

N JFET
NJFET
N JFET
N JFET
N JFET

2N4856
2N4B56A
2N4B56JAN
2N4856JANTX
2N4856JANTXV

2N524B
2N5257
2N525B
2N5259
2N535B

N JFET
N JFET
N JFET
N JFET
N JFET

2N54B6
2N5457
2N545B
2N5459
2N4340

2N4B57
2N4857A
2N4857JAN
2N4B57JANTX
2N4B57JANTXV

N JFET
N JFET
N JFET
N JFET
N JFET

2N4B57
2N4B57A
2N4B57JAN
2N4B57JANTX
2N4857TANTXV

2N5359
2N5360
2N5361
2N5362
2N5363

N JFET
N JFET
N JFET
N JFET
N JFET

2N4340
2N4339
2N4339
2N4339
2N4222A

2N4858
2N4858A
2N4858JAN
2N4858JANTX
2N4858JANTXV

N JFET
NJFT
N JFET
N JFET
N JFET

2N4858
2N4B5BA
2N4858JAN
2N4858JANTX
2N4858JANTXV

2N5364
2N5391
2N5392
2N5393
2N5394

N JFET
N JFET
N JFET
N JFET
N JFET

2N4224
2N4867A
2N486BA
2N4869A
2N4869A

Cl

2N4859
2N4859A
2N4859JAN
2N4859JANTX
2N4859JANTXV

N JFET
N JFET
N JFET
N JFET
N JFET

2N4859
2N4859A
2N4859JAN
2N4859JANTX
2N4859JANTXV

N JFET
N JFET
N JFET
N JFET
N JFET

2N4B60
2N4860A
2N4860JAN
2N4860JANTX
2N4860JANTXV

N JFET
N JFET
N JFET
N JFET
N JFET
N JFET
N JFET
ON JFET
ON JFET
ON JFET

2N4869A
2N4869A
J210
U312
2N5432
2N5433
2N5434
2N5452
2N5453
2N5454

i:i5

2N4860
2N4860A
2N4860JAN
2N4860JANTX
2N4860JANTXV

2N5395
2N5396
2N5397
2N5398
2N5432
2N5433
2N5434
2N5452
2N5453
2N5454

2N4B61
2N4861A
2N4861JAN
2N4861JANTX
2N4861JANTXV

N JFET
N JFET
N JFET
N JFET
N JFET

2N4861
2N4B61A
2N4861 JAN
2N4861JANTX
2N4861JANTXV

2N5457
2N545B
2N5459
2N5460
2N5461

N JFET
N JFET
N JFET
P JFET
P JFET

2N5457
2N5458
2N5459
2N5460
2N5461

2N4867
2N4867A
2N4868
2N4868A
2N4869

N JFET
N JFET
N JFET
N JFET
N JFET

2N4867
2N4867A
2N4868
2N4868A
2N4869

2N5462
2N5463
2N5464
2N5465
2N5484

P JFET
P JFET
P JFET
P JFET
N JFET

2N5462
2N5463
2N5464
2N5465
2N54B4

2N4B69A
2N4977
2N4978
2N4979
2N501B

N JFET
N JFET
N JFET
N JFET
P JFET

2N4869A
2N5432
2N5433
2N5434
2N5018

2N5485
2N5486
2N5515
2N5516
2N5517

N JFET
N JFET
ON JFET
ON JFET
o N JFET

2N54B5
2N54B6
2N5515
2N5516
2N5517

2N5019
2N5020
2N5045
2N5046
2N5047

P JFET
P JFET
ON JFET
ON JFET
ON JFET

2N5019
2N3329
2N5045
2N5046
2N5047

2N5518
2N5519
2N5520
2N5521
2N5522

ON JFET
ON JFET
o N JFET
ON JFET
o N JFET

2N5518
2N5519
2N5520
2N5521
2N5522

Induslry
Pari Number

~

0
0

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ttl

1ii

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Replacement

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1-7

Small-Signal FET Cross Reference (Cont'd)
Industry
Part Number

Type and
Classilicallon

Recommended

2N5523
2N5524
2N5545
2N5546
2N5547

ON
ON
ON
ON
ON

JFET
JFET
JFET
JFET
JFET

2N5549
2N5561
2N5562
2N5563
2N5564

Type and
Classification

2N5523
2N5524
2N5545
2N5546
2N5547

3N145
3N146
3N155
3N155A
3N156

PMOS
PMOS
PMOS
PMOS
PMOS

ENH
ENH
ENH
ENH
ENH

3N163
3N163
3N163
3N163
3N163

N JFET
ON JFET
ON JFET
o N JFET
ON JFET

2N4392
U401
U402
U404
2N5564

3N156A
3N157
3N157A
3N158
3N158A

PMOS ENH
PMOS ENH
PMOS ENH
PMOS ENH
PMOS ENH

3Nl63
3N163
3N163
3N163
3N163

ON JFET

3N163
3N164
3N174
14T
142T

PMOS ENH
PMOS ENH
PMOS ENH
N JFET
N JFET

3N163
3Nl64
3N163
2N3819
PN4392

158T
159T
100S
102M
102S

N JFET
N JFET
N JFET
N JFET
N JFET

PN4302
PN4416
PN4304
2N5486
PN4302

103M
103S
104M
105M
105U

N JFET
N JFET
N JFET
N JFET
N JFET

2N5457
2N5459
2N5458
2N5459
2N4222

2N5565
2N5566
2N5592
2N5593
2N5594

NJFET
N JFET
N JFET

2N5565
2N5566
2N3822
2N3822
2N3822

2N5638
2N5639
2N5640
2N5647
2N5648

N JFET
N JFET
N JFET
N JFET
N JFET

2N5638
2N5639
2N5640
2N4117A
2N4117A

2N5649
2N5801
2N5802
2N5803
2N5902

N JFET
N JFET
N JFET
N JFET
o N JFET

2N4117A
2N4393
2N4393
2N4392
U421

2N5903
2N5904
2N5905
2N5906
2N5907

Data
Sheet
Page

Industry
Part Number

Replacement

o N JFET

ON
ON
ON
ON
ON

JFET
JFET
JFET
JFET
JFET

Geometry
Page

~

0
0

I:D

as
1ii

C

U422
U423
U421
U422
U423

u..

'iii

Iii
iii
t:

Cl

en

Recommended
Replacement

106M
107M
110U
115U
120U

N JFET
N JFET
N JFET
N JFET
N JFET

2N5485
2N5486
2N4339

125U
130U
135U
155U
182:;

N JFET
N JFET
N JFET
N JFET
N JFET

2N4339
2N4341
2N4339
2N4416
2N4391

183S
1975
1985
1995
200S

N JFET
N JFET
N JFET
N JFET
N JFET

2N3823
2N4338
2N4340
2N4341
2N4392

2N4340

ON JFET
ON JFET
ON JFET
ON JFET
N JFET

U423
U423
2N5911
2N5912

2N5950
2N5951
2N5952
2N5953
2N6451

N JFET
N JFET
N JFET
N JFET
N JFET

PN4416
PN4416
J305
J305
2N4393

2N6452
2N6453
2N6454
2N6483
2N6484

N JFET
N JFET
N JFET
ON JFET
ON JFET

2N4393
2N4393
2N4393
U401
U402

200U
201S
202S
203S
204S

N JFET
N JFET
N JFET
N JFET
N JFET

2N3824
2N4391
2N4392
2N3821
2N3821

2N6585
2N6568
2N6656
2N6657
2N6658

ON JFET
N JFET
V MOS N ENH
V MOS N ENH
V MOS N ENH

U404
U290
2N6656
2N6657
2N6658

210U
231S
232S
233S
234S

N JFET
ON JFET
ON JFET
ON JFET
ON JFET

2N4416
2N3954
2N3955
2N3956
2N3957

2N6659
2N6660
2N6661
2N6905
2N6906

V MOS N ENH
V MOS N ENH
V MOS N ENH
ON JFET
ON JFET

2N6659
2N6660
2N6661
2N6905
2N6906

235S
241U
250U
251U
703U

ON JFET
N JFET
N JFET
N JFET
N JFET

2N3958
2N4869
2N4091
2N4392
2N4220

2N6907
2N6908
2N6909
2N6910
2N6911

ON JFET
NJFET
NJFET
NJFET
N JFET

2N6907
2N6908
2N6909
2N6910
2N6911

704U
705U
707U
714U
734U

N JFET
N JFET
N JFET
N JFET
NJfET_

2N4220
2N4224
2N4860
2N3822
2N4416

1-8

PN44i6

en

ill

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iii

'Iii

II:

Siliconix

Geometry
Page

~

0
0

I:D

as
1ii

C

Iii

u..

iii

2N5908
2N5909
2N5911
2N5912
2N5S4S

E

Data
Sheet
Page

t:

Cl

en

iii
E

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CD

:E

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~II:

"7

Small-Signal FET Cross Reference (Cont'd)
Industry
Part Number

Type and
Classification

Recommended

Replacement

Data
Sheet
Page

Geometry
Page

Industry
Part Number

Type and
Classillcalion

Recommended
Replacement

734EU
751U
752U
753U
754U

N JFET
N JFET
N JFET
N JFET
N JFET

PN4416
2N4340
2N4340
2N4341
2N4340

BC264
BC264A
BC264B
BC264C
BC2640

N JFET
N JFET
N JFET
N JFET
N JFET

PN4304
PN4302
PN4304
PN4304
PN4416

755U
756U
1227A
1278A
1279A

N JFET
N JFET
N JFET
N JFET
N JFET

2N4341
2N4340
2N3822
2N3821
2N3821

BF244NB/C
BF245NB/C
BF410A
BF410B
BF410C

N JFET
o N JFET
N JFET
N JFET
N JFET

BF244NB/C
BF245NB/C
J201
J202
J203

1280A
1281A
1282A
1283A
1284A

N JFET
N JFET
N JFET
N JFET
N JFET

2N4224
2N3822
2N4341
2N4340
2N4222

BF4100
BF010
BF011
BF012
BF013

N JFET
N JFET
N JFET
N JFET
N JFET

J204
U401
U401
U402
U402

1285A
1286A
1325A
1714A
2000M

N JFET
N JFET
N JFET
N JFET
N JFET

2N3821
2N4220
2N4222
2N4340
2N3823

BF014
BF015
BF016
BFR30
BFR31

N JFET
N JFET
N JFET
N JFET
N JFET

U403
U405
U405
88T202
88T202

2001M
2078A
2079A
2080A
2081A

N JFET
o N JFET
o N JFET
o N JFET
o N JFET

2N3823
2N3955
2N3955
2N5546
2N5546

BFR45
BF821
BF521A
BF567
BF568

N JFET
N JFET
ON JFET
N JFET
N JFET

2N4416
2N5199
2N5199
2N3821
2N3823

2098A
2099A
2130U
2132U
2134U

ON
ON
ON
ON
ON

JFET
JFET
JFET
JFET
JFET

2N5545
2N5546
2N5452
2N3955
2N3956

2136U
2138U
2139U
2147U
2148U

o N JFET

ON JFET
ON JFET
ON JFET
ON JFET

2N3957
2N3958
2N3958
2N3958
2N3958

2149U
A5T3821
A5T3822
A5T3823
A5T3824

ON JFET
N JFET
N JFET
N JFET
N JFET

2N3958
J305
J305
PN4416
J302-18

A192
A0830
A0831
A0832
A0833

N JFET
ON JFET
ON JFET
o N JFET
ON JFET
ON JFET

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1-11

Small-Signal FEY Cross Reference (Cont'd)
Data
Sheet
Page

Type and
Classification

Recommended
Replacement

J1406
K2l0-l8
K2ll-l8
K2l2-l8
K300-l8

ON JFET
N JFET
N JFET
N JFET
N JFET

U406
J2l0
J2ll
J2l2
J2l0

Jl07-l8
Jl08
Jl08-l8
Jl09
Jl09-l8

K304-l8
K305-l8
K308-l8
K309-l8
K3l0-l8

N JFET
N JFET
N JFET
NJFET
N JFET

J304
J305
J308
J309
J3l0

N JFET
N JFET
N JFET
N JFET
N JFET

Jll0
Jll0-l8
Jlll
Jlll-18
J112

KE3684
KE3685
KE3686
KE3687
KE3823

N JFET
N JFET
N JFET
N JFET
N JFET

2N434l
2N4340
2N4339
2N4338
J304-l8

Jll2-l8
Jl13
Jl13-l8
J174
J174-l8

N JFET
N JFET
N JFET
P JFET
P JFET

Jll2-l8
Jl13
Jl13-l8
J174
J174-l8

KE3970
KE3971
KE3972
KE4091
KE4092

N JFET
NJFET
N JFET
N JFET
N JFET

PN4391-l8
PN4392-l8
PN4393-18
PN439l-l8
PN4392-l8

J175
J175-l8
J176
J176-l8
Jl77

P JFET
P JFET
P JFET
P JFET
P JFET

J175
J175-l8
J176
J176-l8
J177

KE4093
KE4220
KE4221
KE4222
KE4223

N JFET
N JFET
N JFET
N JFET
N JFET

PN4393-1B
2N5457
2N5457
2N5459
J304-l8

Jl77-l8
J20l
J20l-l8
J202
J202-l8

P JFET
N JFET
N JFET
N JFET
N JFET

J177-l8

KE4224
KE4391
KE4392
KE4393
KE4416

N JFET
N JFET
N JFET
N JFET
N JFET

J304-l8
PN439l-l8
PN4392-l8
PN4393-18
PN4416

J203
J203-l8
J204
J204-l8

J204
J204-18

(f)

KE4856
KE4857
KE4858
KE4859

"'IU

-E

I\C"touu

N JFET
N JFET
N JFET
N JFET
i~ JFET

PN4391-18
PN4392-l8
PN4393-18
PN4391-18

J210

N JFET
N JFET
N JFET
N JFET
N JFET

J211
J2l2
J230
J230-l8
J23l

N JFET
N JFET
N JFET
N JFET
N JFET

J2ll
J212
J230
J230-18
J231

KE4861
KE51 03
KE51 04
KE5105
KK4416-18

N JFET
N JFET
NJFET
NJFET
NJFET

PN4393-18
J305
J304
J306
PN4416

J23l-l8
J232
J232-l8
J270
J270-l8

N JFET
N JFET
N JFET
P JFET
P JFET

J23l-18
J232
J232-l8
J270
J270-l8

LOF603
LOF604
LOF605
M163
M164

NJFET
N JFET
N JFET
PMOS ENH
PMOS ENH

2N4221A
2N4221A
2N4221A
3N163
3N164

J27l
J271-l8
J300
J300NB/C/O
J304
J305
J308
J309
J310
J401

P JFET
P JFET
N JFET
N JFET
N JFET
N JFET
N JFET
N JFET
N JFET
ON JFET

J271
J27l-18
J300
J300NB/C/O
J304
J305
J308
J309
J310
U401

MEM520
MEM520G
MEM561
MEM561G
MEM806

PMOS
PMOS
PMOS
PMOS
PMOS

3N164
3Nl64
3N163
3N163
3N163

MEM806A
MFE823
MFE2000
MFE2001
MFE2004

PMOS ENH
PMOS ENH
NJFET
N JFET
N JFET

3N163
MFE823
2N4416
2N4416
2N4093

J402
J403
J9l00
J1404
J1405

ON JFET
ON JFET
GLNFET
ON JFET
ON JFET

U402
U403
J552
U404
U405

MFE2005
MFE2006
MFE2007
MFE2008
MFE2009

N JFET
N JFET
N JFET
N JFET
N JFET

2N4092
2N409l
2N4860
2N4859
2N4859

Induslry
Part Number

Type and
Classification

Jl05
Jl05-l8
Jl06
Jl06-l9
Jl07

N JFET
N JFET
N JFET
N JFET
N JFET

Jl05
Jl05-l8
Jl06
Jl06-l8
Jl07

Jl07-l8
Jl08
Jl08-l8
Jl09
Jl09-l8

N JFET
N JFET
N JFET
N JFET
N JFET

Jll0
JllO-l8
Jlll
Jlll-18
Jll2

1-12

Recommended
Replacement

Geometry
Page

..l<:

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Part Number

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Silicanix

PN4392-1ii

ENH
ENH
ENH
ENH
ENH

Data
Sheet
Page

Geometry
Page

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Small-Signal FEY Cross Reference (Cont'd)
Industry
Part Number

Type and
Classification

Recommended
Replacement

Data
Sheet
Page

Geometry

Industry

Page

Part Number

Type and
Classification

Recommended
Replacement

MFE2010
MFE2011
MFE2012
MFE2093
MFE2094

N JFET
N JFET
N JFET
N JFET
N JFET

2N5434
2N5433
2N5432
2N4338
2N4339

NF583
NF584
NF585
NF4302
NF4303

N JFET
N JFET
N JFET
N JFET
N JFET

2N5434
2N5433
2N4859
2N4302
2N4303

MFE2095
MK10
MMBF310
MMBF4391
MMBF4392

N JFET
N JFET
N JFET
N JFET
N JFET

2N4540
2N4416
55T310
SST113
SST112

NF4304
NF4445
NF4446
NF4447
NF4448

N JFET
N JFET
N JFET
N JFET
N JFET

2N4304
2N5432
2N5433
2N5432
2N5433

MMBF4393
MMBF4416
MMBF4860
MMBF5310
MMBF5457

N JFET
N JFET
N JFET
N JFET
N JFET

SST111
5ST4416
5ST111/112
5ST310
S5T202

NF5163
NF5457
FN5458
NF5459
NF5484

N JFET
N JFET
N JFET
N JFET
N JFET

2N5163
2N5457
2N5458
2N5459
2N5484

MMBF5460
MMBF5484
MMBF5484
MMBF5486
MMBFU310

N JFET
N JFET
N JFET
N JFET
N JFET

55T5460
5ST202
SST5484
SST5486
55T310

NF5485
NF5486
NF5555
NF5638
NF5639

N JFET
N JFET
N JFET
N JFET
N JFET

2N5485
2N5486
2N5555
2N5638
2N5639

MMF1
MMF2
MMF3
MMF4
MMF5

D N JFET
D N JFET
D N JFET
D N JFET
D N JFET

2N3921
2N3921
2N3921
2N3921
2N3921

NF5640
NF5653
NF5654
PAD1
PAD2

N JFET
N JFET
N JFET
PAD N JFET
PAD N JFET

2N5640
2N5653
2N5654
PAD1
PAD2

MMF6
MMT3823
MPF102
MPF103
MPF104

D N JFET
N JFET
N JFET
N JFET
N JFET

2N3921
2N3823
MPF102
2N5457
2N5458

PAD5
PAD10
PAD20
PAD50
PAD100

PAD
PAD
PAD
PAD
PAD

PAD5
PAD10
PAD20
PAD50
PAD100

MPF105
MPF106
MPF107
MPF108
MPF109

N JFET
N JFET
N JFET
N JFET
N JFET

2N5459
2N5485
2N5486
MPF108
MPF109

P1086
P1086-18
P1087
P1087-18
PN4091

P JFET
P JFET
P JFET
P JFET
N JFET

P1086
P1086-18
P1087
P1087-18
PN4091

MPF111
MPF112
MPF256
MPF820
MPF970

N JFET
N JFET
N JFET
N JFET
P JFET

MPF111
MPF112
J309
U310
J174

PN4092
PN4093
PN4117
PN4117A
PN4118

N JFET
N JFET
N JFET
N JFET
N JFET

PN4092
PN4093
PN4117
PN4117A
PN4118

MPF971
MPF4391
MPF4392
MPF4393
NF500

P JFET
N JFET
N JFET
N JFET
N JFET

J176
PN4391-18
PN4392-18
PN4393-18
2N4416

PN4118A
PN4119
PN4119A
PN4120
PN4120A

N JFET
N JFET
N JFET
N JFET
N JFET

PN4118A
PN4119
PN4119A
PN4120
PN4120A

NF501
NF506
NF510
NF511
NF520

N JFET
N JFET
N JFET
N JFET
N JFET

2N4416
2N4416
2N4393
2N4393
2N4339

PN4302
PN4302-18
PN4303
PN4303-18
PN4304

N JFET
N JFET
N JFET
N JFET
N JFET

PN4302
PN4302-18
PN4303
PN4303-18
PN4304

NF521
NF522
NF523
NF530
NF531

N JFET
N JFET
N JFET
N JFET
N JFET

2N4339
2N4339
2N4340
2N4341
2N4339

PN4304-18
PN4391
PN4391-18
PN4392
PN4392-18

N JFET
N JFET
N JFET
N JFET
N JFET

PN4304-18
PN4391
PN4391-18
PN4392
PN4392-18

NF532
NF533
NF580
NF581
NF582

N JFET
N JFET
N JFET
N JFET
N JFET

2N4341
2N4339
2N5432
2N5432
2N5433

PN4393
PN4393-18
PN4416
PN5163
PF510

N JFET
N JFET
N JFET
N JFET
P JFET

PN4393
PN4393-18
PN4416
PN5163
2N5018

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N JFET
N JFET
N JFET
N JFET
N JFET

Data

Sheet
Paga

Geometry
Page

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1-13

Small-Signal FET Cross Reference (Cont'd)
Industry
Part Number

Type and
Classification

Recommended

Replacement

Data
Sheet
Page

Geometry
Page

Industry
Part Number

Type and
Classification

Recommended
Replacement

PF511
8D210DE
8D2110E
8D2120E
802130E

P JFET
ON JFET
ON JFET
ON JFET
ON JFET

2N5014
8D210DE
8D211DE
8D2120E
8D2130E

88T6909
88T6910
8U2078
8U2079
8U2098

N JFET
N JFET
ON JFET
ON JFET
ON JFET

88T6909
88T6910
U425
U425
2N5197

802140E
802150E
8il000
8il0l0
8il020

ON JFET
ON JFET
N JFET
N JFET
N JFET

8D2140E
8D2150E
2N6908
2N6909
2N6910

8U2098A
8U2098B
8U2099
8U:W99A
8U2365

ON
ON
ON
ON
ON

2N5197
2N5196
2N5197
2N5197
U401

8ill00
8i1800
8i2000
804091
804391

N JFET
JFET Array
N JFET
N JFET
N JFET

2N6911
811800
812000
88T4091
88T4391

8U2365A
8U2366
8U2366A
8U2367
8U2367A

ON JFET
ON JFET
ON JFET
ON JFET
ON JFET

U401
U402
U402
U403
U403

804416
88T111
88T112
88Tl13
88T174

N JFET
N JFET
NJFET
N JFET
P JFET

88T4416
88T111
88T112
88T113
88T174

8U2366
8U2368A
8U2369
8U2369A
8U2410

ON JFET
ON JFET
ON JFET
o N JFET
o N JFET

U404
U404
U405
U405
U424

88T175
88T176
88T177
88T201
88T202

P JFET
P JFET
P JFET
N JFET
N JFET

8ST175
88T176
88T177
88T201
88T202

8U2411
8U2412
T05911
TD5911A
T05912

ON JFET
o N JFET
ON JFET
ON JFET
D N JFET

U425
U426
2N5911
2N5911
2N5912

88T203
88T204
88T211
88T213
88T215

N JFET
N JFET
N DM08
N OM08
N DM08

88T203
85T204
85T211
88T213
85T215

TD5912A
TI514
TI825
TI826
TI827

D N JFET
N JFET
D N JFET
D N JFET
D N JFET

2N5912
2N4340
U401
U402
U404

58T308
85T309
88T31 0
88T405
85T406

N JFET
N JFET
N JFET
D N JFET
D N JFET

88T308
85T309
88T310
881405
88T406

TI841
TI858
TI859
TI573
TI874

N JFET
N JFET
N JFET
N JFET
N JFET

2N4859
J305-18
U1837
PN4391-18

88T41 0
88T411
88T412
88T4302
88T4303

D N JFET
D N JFET
ON JFET
N JFET
N JFET

85T410
58T411
88T412
85T4302
88T4303

TI875
TI888
TIX541
TIXS42
TN4117

N JFET
N JFET
N JFET
N JFET
N JFET

PN4393-18
2N5486
2N4859
PN4393-18
2N4117

88T4304
88T4391
88T4392
88T4393
88T4416

N JFET
N JFET
N JFET
N JFET
N JFET

88T4304
88T4391
85T4392
88T4393
55T4416

TN4117A
TN4118
TN4118A
TN4119
TN4119A

N JFET
NJFET
N JFET
N JFET
N JFET

2N4117A
2N4118
2N4118A
2N4119
2N4119A

58T4856
55T4857
55T4858
88T4859
85T4860

N JFET
N JFET
N JFET
N JFET
N JFET

58T4856
58T4857
58T4858
58T4859
58T4860

TN4338
TN4339
TN4340
TN4341
TP5114

N JFET
N JFET
N JFET
N JFET
P JFET

2N4338
2N4339
2N4340
2N4341
2N5114

58T5114
58T5115
58T5116
88T5484
55T5485

P JFET
P JFET
P JFET
N JFET
NJFET

55T5114
85T5115
5ST5116
58T5484
58T5485

TP5115
TP5116
U182
U183
U197

P JFET
P JFET
N JFET
N JFET
N JFET

2N5115
2N5116
2N4857
2N3824
2N4339

85T5486
58T5638
55T5639
55T5640
55T6908

N JFET
N JFET
N JFET
N JFET
N JFET

58T5486
58T5638
55T5639
5ST5640
55T6908

U198
U199
U200
U201
U202

N JFET
N JFET
N JFET
N JFET
N JFET

2N4340
2N4341
U200
U201
U202

1-14

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JFET
JFET
JFET
JFET
JFET

PN4~92-1B

Data

Sheet
Page

Geometry
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Small-Signal FET Cross Reference (Cont'd)
Industry

Type and

Recommended

Part Number

Classification

Replacement

Data
Sheet
Page

Geometry
Page

Industry

Type and

Part Number

Classification

Recommended
Replacement

Data

Sheet
Page

Geometry
Page

U221
U222
U231
U232
U233

N JFET
N JFET
D N JFET
D N JFET
o N JFET

2N4391
2N4391
U231
U232
U233

U428
U430
U431
U440
U441

D N JFET
D N JFET
D N JFET
D N JFET
ON JFET

U428
U430
U431
U440
U441

U234
U235
U240
U241
U242

D N JFET
D N JFET
N JFET
N JFET
N JFET

U234
U235
2N5432
2N5433
2N5432

U443
U444
U508
U1177
U1178

D N JFET
D N JFET
N JFET
N JFET
N JFET

U443
U444
CR030
2N4220A
2N3821

U243
U254
U255
U256
U257

N JFET
N JFET
N JFET
N JFET
D N JFET

2N5433
2N4859
2N4860
2N4861
U257

U1179
U1180
U1181
U1182
U1277

N JFET
N JFET
N JFET
N JFET
N JFET

2N3821
2N4221A
2N4220A
2N3821
2N4339

U273
U273A
U274
U274A
U275

N JFET
N JFET
N JFET
N JFET
N JFET

2N4118A
2N4118A
2N4119A
2N4119A
2N4119A

U1278
U1279
U1280
U1281
U1282

N JFET
N JFET
N JFET
N JFET
N JFET

2N4339
2N4340
2N4339
2N3822
2N4341

U275A
U280
U281
U282
U283

N JFET
D N JFET
D N JFET
D N JFET
D N JFET

2N4119A
U231
U231
U232
U232

U1283
U1284
U1285
U1288
U1287

N JFET
N JFET
N JFET
N JFET
N JFET

2N4340
2N4341
2N4220
2N4341
2N4092

U284
U285
U290
U291
U295

D N JFET
D N JFET
N JFET
N JFET
N JFET

U233
U234
U290
U291
U295

U1322
U1323
U1324
U1325
U1420

N JFET
N JFET
N JFET
N JFET
N JFET

2N4221A
2N4221A
2N4220A
2N4222
2N3821

Cl
IW
LL

U1421
U1422
U1714
U1637E
U1897

N JFET
N JFET
N JFET
N JFET
N JFET

2N3822
2N3822
2N4340
U1837
U1897

Ci5

U1897·18
U1897E
U1898
U1898·18
. U1898E

N JFET
N JFET
N JFET
N JFET
N JFET

U1897·18
U1897·18
U1898
U1898·18
U1898·18

-"
0
0

II)

 > megohm input impedance; subpicoamp leakage;
simple, two-leaded current
sources and limiters; differential amplifiers with > > 100
volt/microsecond slewing
while achieving picoamp input
current; and protection
diodes-Siliconix is the
source.
Siliconix offers awide variety of packages: the hermetically sealed metal can;
plastic TO-92; surface-mount SOT-23,
SOT-143, and SOIC; and also die/chip
products. Our products include n- and

Siliconix

p-channel JFETs, enhancement-mode
MOSFETs, and n-channel enhancementmode DMOS FETs - the broadest FET
line in the world.
Siliconix has specialized in offering highperformance products for high-performance designs. Our specialty has been
to fill the gap which exists between the
best ICs available in the industry and
discrete devices.
Siliconix began manufacturing smallsignal Field Effects Transistors 20 years
ago. Our emphasis has been, and will
continue to be, ultrahigh-performance
devices. Our product line is the broadest
FET line in the world, and our commitment to this technology has never
waivered. Our manufacturing capacity
ensures timely delivery on even the large
volume run-rates.

FET:f
8JV $;';COII;I

2-1

Using JFETs

as'rontend
dertlces tor

a"AmllS

By using alow-leakage, low-noise and high-gain dual
JFET with a relatively inexpensive, general-purpose
biFET op amp, overall circuit performance is far superior
than by using the best biFET op amp available. With
present technology, the biFET-op amp approach has

Check out the
Overall Circuit Performance
circuit performance:
NOise (10 Hz)
Leakage
Slew Rale

certain compromises - either on low-leakage, low noise
or high gain (slew rates). One or two of these performance characteristics will be compromised with the
biFET. By using aFET as a"front-end" device, all three
can be achieved.

UsingOPA-lll Circuit

Using U403 with OP-15 Circuit

33nVI-v'HZ
1 pA
2.9VI"S

20nV/-v'HZ
1pA
12V1"S

< 10 nVI..(RZ

U401-6, 2N6905-B, 2N5564-6
U421-6
2N5911-12
2N5564-6

Specific Device Performance Characteristics
Low Noise (en)
Low Leakage (IG)
High Gain I (gfs)
High Slew Rates

< 1 pA
> 7500 "mhos thru 450 MHz
> 50 VI".5

Com"are

+15V

Using JfElS

as front-End

OPA·III

GUARD

De,,'ces

,'...

I

BiFETOpAmp

3~

'\

~ lO~F
7 :J; TANT

v+

I

\, ~ CASE OUT 6
V-

~ [::/4

5M

1'2
l 10~F

2K

TANT

~

-15v
lOOK
IDS

...







__

_

JfElSas

• ___A

nuRI-eRD

De"i. with
a BifET

+15V

10K

...

+15V'"

10K
-5V

a" Am"

Y21
GUARD

10~F

I Y2
U403

lTANT

500~

416
lOOK

5M

2-2

lOS

Siliconix

2K

Using FETs
as Analog
Switches

JFETs and DMOS FETs offer flat oN-resistance, plus
low ON-resistance in addition to ultrahigh-speed
switching. Siliconix DMOS devices operate as high as

500 MHz.

C.pmpare the discrete
approach to the IC Device Technology
approach where Slllcomx - DMOS
SD210-15
performance makes the
SD5000-2
difference:

Switching time

CMOS
CD4016

FETS

as Analog

Switches
Selector
Guide

Using JFETs
as Diodes
Compare traditional diodes
to the Siliconix line of
PAD - Pico Amp Diodes:

Device
SD210·15
SD5000
Jill
J112
J113
2N4391
2N4392
2N4393
Jl05
Jl06
Jl07
J10B
Jl09
Jll0

ros(on)

Ins

45 ohms

SOns

50 ohms

Technology

SWitchingt(on)

ros(on)

DMOS
DMOS
JFET
JFET
JFET
JFET
JFET
JFET
JFET
JFET
JFET
JFET
JFET
JFET

1ns
1ns
7ns
7ns
7ns
15ns
15ns
15ns
15ns
15n5
15ns
4ns
4ns
4ns

45 ohms
45 ohms
30 ohms
500hms
1000hms
30 ohms
60 ohms
l000hms
30hms
6 ohms
Bohms
Bohms
120hms
lBohms

JFETs make ultralow-Ieakage diodes by using the gate
and the drain of the device.

Devicel
Technology

Capacitance

Breakdown
Voltage

Leakage

2ns

1.5pF

75 V

7-10nA

lN457
lN484

300ns

1.5pF

70V

100pA

JFETS
PAD-l

250ns

20pF

45V

1pA

Blpolar5 as
diodes
(lowest leakage)

200ns

30pF

30·60 V

1N914 (gold doped)
lN4148

Switching Time
(recovery time)

-

4-5pA

If speed IS critical. then the gold-doped diodes are the first choice If leakage IS important- choose the SllIcomx PAD-l series

Siliconix

2-3

JFETs as low
leakage Diolle
Selector 6uille

Leakage
IR

Breakdown BVR
Reverse Breakdown VoHage

Capacitance
cR

Device
Number

Type
Package

1 pA
2 pA
5 pA
10 pA
20 pA
50 pA
100 pA

-45
-45
-45
-35
-35
-35
-3S

V
V
V
V
V
V
V

0.8pF
0.8pF
0.8pF
2.0pF
2.0pF
2.0pF
2.0pF

DPAD1*
DPAD2*
DPADS*
DPAD10'
DPAD20'
DPADSO'
DPAD100'

Modified TO-78
Modified TO-71
Modified TO-71
Modified TO-71
Modified TO-71
Modified TO-71
Modified TO-71

5 pA
10 pA
20 pA
50 pA
100 pA
200 pA
500 pA

-35
-35
-35
-35
-35
-35
-35

V
V
V
V
V
V
V

2.0pF
2.0pF
2.0pF
2.0pF
2.0pF
2.0pF
20pF

JPAD5
JPAD10
JPAD20
JPAD50
JPAD100
JPAD200
JPAD500

2-Leaded
2-Leaded
2-Leaded
2-Leaded
2-Leaded
2-Leaded
2-Leaded

TO-92
TO-92
TO-92
TO-92
TO-92
TO-92
TO-92

1 pA
2 pA
5 pA
10 pA
20 pA
50 pA
100 pA

-45
-45
-45
-35
-35
-35
-35

V
V
V
V
V
V
V

o8pF
o8pF

PADl
PAD2
PAD5
PAOlO
PAD20
PAD50
PAD100

3-Leaded
3-Leaded
3-Leaded
3-Leaded
3-Leaded
3-Leaded
3-Leaded

TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18

08pF
2.0pF
2.0pF
20pF
20pF

• D = Dual Diode

FETS
as Current

Regulators

Current
Regulator
Selector 6uille

2-4

Siliconix offers simple, two-leaded temperaturecompensated current regulators. The inherent design of
the JFET produces devices where the current is insensitive to temperature changes and with atemperature
coefficient better than 30.00ppm per degree c. The

breakdown voltage of the devices are rated at 100 V,
and they provide excellent constant current down to
1-2 V. The devices are selected in the 10% ranges from
100 ~A to 5.6 rnA for use in precise instrumentation.

Part Number

IF(mln)

TOLERANCE %

CR022
CR024
CR027
CR030
CR033
CR039
CR043
CR047
CR056
CR062
CR068
CR075
CR082
CR091
CR100
CRll0
CRl20
CRl30
CRl40
CRl50
CRl60
CR180
CR200
CR220
CR240
CR270
CR300
CR330
CR360
CR390
CR430
CR470
CR530

198 flA
216 ~A
243 ~A
270 flA
297 flA
351 flA
387 ~A
423 ~A
504 ~A
558 ~A
612 ~A
675 ~A
738 ~A
819 ~A
900 ~A
990 ~A
1.09mA
1.17mA
1.26mA
1.35mA
1.44mA
1.62mA
180mA
1.98mA
2.16mA
2.43mA
2.70mA
2.97mA
3.24mA
3.51 mA
3.87mA
4.23mA
4.nmA

10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%

Siliconix

BV
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

Package
jail 2-leaded devices)
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO·18
TO-18
TO·18
TO-18
to-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18
TO-18

Data Sheets _

Siliconix

n-channel JFET
designed for • • •

H
Siliconix

------

Performance Curves NH NRL
See SecHon 4

General Purpose Amplifiers
• Analog
Switching
•

BENEFITS
• Low Cost
III Specified at 100 MHz
o Automatic Insertion Package

iNOT RECOMMENDED
FOR NEW DESIGNS.

"ABSOLUTE MAXIMUM RATINGS (25°C)

Drain-Gate Voltage ............................ 25 V
Drain-Source Voltage .......................... 25 V
Reverse Gate-Source Voltage ................. -25 V
Gate Current ................................ 10 rnA
Continuous Device Dissipation
at (or Below) 25°C Free Air Temperature
(Note 1) ................................. 200 mW
Storage Temperature Range ........ -55°C to +150°C
Lead Temperature
(1/16" from Case for 10 seconds) .......... . 260°C

Plastic

TO-92
See Section 6

"D

'4:

G,

C

•

C

Bottom View

•

G

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic
1

12

BVGSS

Gate-Source Breakdown Voltage

IGSS

Gate Reverse Current

loSS

Saturation Drain Current

I~

I

I~

C

VGS

Gate-5ource Voltage

6

VGS(off)

Gate-Source Cutoff Voltage

7

IYfs l

8

9

10

-

D
V
N
A
M
I
C

11

IYo.1
Ciss
Crss
IYfsi

Common-Source Forward

Transfer Admittance

V

Test Conditions
IG =-lI'A, VOS =0

nA

-2

I'A

2

20

mA

-0_5

-7_5

V

VOS = 15 V,ID = 200 I'A

-8

V

VDS=15V,ID=2nA

2000

Admittance
Common Source Input

Capacitance
Common Source Reverse

Transfer Capacitance
Common Source Forward

Unit

-2

Common Source Output

Transfer Admittance

Max

-25

S

I- T
3 A
I- T

1-

Min

6500

I'mho

50

I'mho

8

pF

4

pF

1600

I'mho

* JEDEC registered data

VGS = -15 V, VDS = 0

TA = 100'C

VOS = 15 V, VGS = 0 (Note 2)

VDS = 15 V, VGS =0 (Note 2)

f = 1 kHz

VDS=15V,VGS=0

f = 1 MHz

VDS=15V,VGS=0

f=100MHz

NH
NRL

NOTES:

1- Derate linearly to 125°C (free air temperature at a rate of 2 mW/"C)_
2. Pulse tested pulse width = 100 ms, duty cvcle" 10%_

Siliconix

3-1

n-channel JFETs
designed for • • •

H

Siliconix

Performance Curves NRL
See Section 4

Amplifiers
• Small-Signal
• Oscillators

BENEFITS
Operates from High Supply
• Voltages
BVGSS>50V

*ABSOLUTE MAXIMUM RATINGS (25°C)
Gate-Drain or Gate-Source Voltage (Note 1)
Gate Current
Total Device Dissipation at (or below) 25°C
Free-Air Temperature (Note 2)
Storage Temperature Range
Lead Temperature
(1/16" from case for 10 seconds)

TO-72
See Section 6

-50 V
10 mA
300mW
-65 to +200°C

'4:

300°C

G

~

c

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
CharacterIStiC

,
-2"3

..
-

5

S

IGSS

Gate Reverse Current

T
A
T
I

BVGSS

Gate Source Breakdown Voltage

VGS(off)

Gate·Source Cutoff Voltage

C

VGS

Gate Source VoltaQe

2N3822

2N382'
M,n

M.x

M,"

-0 ,

-05

nA

-0 ,

-0 ,

-05

pA

-50
-4

-30

7

-

8

Saturation Dram Current (Note 3)

9"

Common Source FOIward
Tran';tconductance (Note 3)

IVIsI

-

Common Source Forward

Transadmlttance

Vas = 15 V.IO = 200pA

-70

05

25

2

10

4

20

4500

30gp

6500

3,5OD

6,500

3000

3.200

9

0

90s

10

20

35

N
A
M

C ISS

Common Source Input
Capacitance

6

6

6

11

1
C

Crss

Common Source Reverse Transfer
Capacitance

2

2

2

NF

NOIse Figure

5

5

6

200

200

200

-

12

VOS'" 15V,IO= 4OO IJ A
rnA

Vas = 15V, VGS=D
f = 1 kHz

,umho

10

Y

t"l00MHz
VOS=15V,VGS=O

pF

dB

VOS=15V,VGS"'0,
Rgen::: 1 meg, BW = 5 Hz

f = 10 Hz
Equivalent Short Circuit Input

en

NOise Voltage

nV

v1'i1

VOS'" 15V,VGS=O,BW=5Hz

NRL

* JEDEC Registered Data.

,

NOTES:

Due to symmetrical geometry, these umts may be operated With source and drain leads Interchanged
2. Derate linearly to 175°C free-air temperature at rate of 2 mWfC.
3 These parameters are measured dUring a 2 msec Interval 100 msec after d-c power IS applied,

3-2

f:: 1 kHz

f::: 1 MHz

~

13

I
I '50°C

VOS=15V.l0"'50IlA

Common Source Output
Conductance (Note 3)

-

-30 V, Vas = 0

VOS=15V,lo=05nA

-4

1500
1500

=:

V

-2
-1

lOSS

VGS

IG=-lp.A,VOS=D

-8

-6

-10
6

Test Conditions

Max

-0 ,

-50

-05

2N3823
Unit

M,n

Max

Siliconix

n-channel JFET
designed for • • •

H

Siliconix

Performance Curves NRL
See Sedion 4

High Speed Commutators
Choppers

III
III

BENEFITS
I nsertion Loss
• Lowrds{on)
< 250 n
Ii)

High Off-Isolation
I D{off) < 0_1 nA

*ABSOLUTE MAXIMUM RATINGS (25°C)
Gate-Drain or Gate-Source Voltage (Note 1)
Gate Current
Total Device Dissipation at (or below) 25°C
Free-Air Temperature (Note 2)
Storage Temperature Range
Lead Temperature
(1/16" from case for 10 seconds)

TO·72
See Section 6

-50V
10mA
300mW
-65 to +200° C

'4:

300°C

G

0

~

s

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Mm

Characteristic

1...2. S
2

T
A
3 T
I- I
C
4

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

ID(off)

Drain Cutoff Current

'ds(on)

Drain-Source ON Resistance

C ISS
Crss

Max

Umt

-0.1

nA

-0.1

IJA

Test Conditions
VGS = -30 V. VDS = 0

150°C

1-

5

D

I- V
6

17

N
A
M
I
C

-50

V

IG = -lIJA. VDS = 0

0.1

nA

0.1

IJA

250

n

VGS = 0 V. ID = 0

Common-Source Input Capacitance

6

pF

VDS = 15 V. VGS = 0

Common-Source Reverse Transfer Capacitance

3

pF

VGS = -8 V. VDS = 0

VDS = 15 V. VGS = -8 V

150°C
f = 1 kHz

f= 1 MHz

NRL

• JEDEC registered data.
NOTES:
1. Due to symmetrical geometry. these units may be operated with source and drain leads Interchanged.
2. Derate linearly to 17SoC free-air temperature at rate of 2 rnWfC

Silicanix

3-3

monolithic dual
n-channel JFETs
designed for • • •

H

Siliconix

Performance Curves NNR
See Section 4

• DiHerential Amplifiers

BENEFITS
Minimum System Error and Calibra• tion
5 mV Offset Maximum (2N3921)
Amplifier Design
• Simplifies
Low Output Conductance
TO-71
See Section 6

*ABSOLUTE MAXIMUM RATINGS (25°C)

G1

Gate-Drain or Gate-Source Voltage ..............• -50 V
Gate Current ............................... 50 rnA
Total Device Dissipation
(Derate 1.7 mW;oC to 200°C) ..•............ 300mW
Storage Temperature Range •............. -65 to +200°C

~~
81

S2

'2

o
G, 0 3

5

02

0
6 0 G2

.,
2

0,

G2

7

0'
0

.0 '•

G,

Bottom View

l~

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Min

Characteristic

.2.

IGSS

Gate Reverse Current

BVOGO

Drain-Gate Breakdown Voltage

4"T
-::-A

VGS(offl
VGS

Gate-Source Cutoff Voltage
Gate-5ource Voltage

-"-c

IG

Gate Operatmg Current

2

~s

~:
b
•

...l...
8
9

lOSS
9fs
100 gos
l1 V CISS
C rss
13M 9fs
1 gos

12":
14
_c
15

NF

16

1-

M
A
T
1- C
18 H

17

IlA

1

Common-Source Output Conductance
Common-Source Input Capacitance
Common-Source Reverse Transfer Capacitance
Common-Source Output Conductance

2N3921

0.95

Max

2N3922
Min

Max

Ilmho

5

5

10

25

1.0

0.95

1.0

d8

2N4OB4
Min

0.95

VOG = 10V,I0 = 700ilA

100·C

VOS = 10V, VGS = 0

VOS=10V,VGS=1J

2

Min

I 100·C

10 = lilA. IS = 0
VOS-l0V.10-lnA
VOS - 10V,I0 = lOOIlA

pF

20

Spot NOise Figure

VGS=-30V. VOS=O

"mho

1500

Common-Source Forward Transconductance

Test Conditions

pA
nA
mA

10
7500
35
18
6

1500

Common-Source Forward Transconductance (Note 1)

Transconductance Ratio
(Note 3)

V

-2.7
-250

• JEOEC registered data.
NOTES:
1. Pulse test duration = 2 ms.
2. Measured at end points, TA and TB.
3. Assumes smaller value 10 numerator.

3-4

-1

-25

IVGS1-VGS2 1'
aIVGS1-VGS2 1 Gate-Source Differential Voltage
Change with Temperature
aT
(Note 21
91,1

nA

-3
-0.2

Differential Gate-Source Voltage

-gfs2

-1
50

Saturation Drain Current (Note 1)

Characteristic

Unit

Max

Max

VOG = 10V.10 = 700llA
VOS=10V,VGS

2N4085
Min

Max

Unit

15

15

mV

10

25

"vfc

1.0

-

1.0

0.95

0

1= I kHz

1 = 1 kHz
f= 1 kHz,
RG= 1 meg

Test Conditions

O·C
VOG=10V, TA=
10 = 700llA TB = 100·C
f = I kHz

NNR

Siliconix

monolithic dual
n-channel JFETs
designed for • • •

H

Siliconix
Performance Curves NQP
See Section 4
BENEFITS
Accuracy & Stability
• HighOffset
Less Than 5 mV (2N3954, 54A)

and Medium Frequency
• Low
Differential Amplifiers
Input
• High
Impedance Amplifiers

Drift Less Than 5 fJ.VrC (2N3954A)
Range
• WideIG Dynamic
Specified @ V DS =20 V
• LowCissCapacitance
<4 pF
TO·71
See Section 6

ABSOLUTE MAXIMUM RATINGS (25°C)
Any Case-To-Lead Voltage ...•.....•• " .•...•.. ±100 V
Gate-Drain or Gate-Source Voltage •••••..•...••.• -50 V
Gate Current. . . • . • . • . . • • . • • • • • • • • • . • . . . . . .• 50 mA
Total Device Dissipation at (Each Side) ..••......... 250 mW
85°C Case Temperature (Both Sides) ............ 500 mW
Power Derating (Each Side) •••••.•...••••• 2.86 mWrC
(Both Sides) ••••.•••..••••• 4.3 mWrC
Storage Temperature Range •••••..••.••• -65 to+200oC
Lead Temperature (1/16" from case for 10 seconds) ••• 300°C

G,

~~
8,

G2

82

'2

G~

G' 30 0 506 °2
0,2 0 ,0 07 02

5,

[

0,

'1

Bottom View

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
CharacterIStic

1

2'

13
14
I5
IS
17"
IS

IGSS

Gate Reverse Current

BVGSS

Gate·Source Breakdown
Voltage
Gate-Source Cutoff
Voltage
Gate-Source Forward
Voltage

s VGS(olll
T
A
T VGS(II
I
C VGS

l"i

110

IG

Gate Operating Current

lOSS

Saturation Dram
Current

gls
1-+1IE. 0
13 y gas
1- N
14 A CISS
I-M
15 I Crss

-c

Gate-Source Voltage

Common-Source Forward
Transconductance
Common-Source Output
Conductance

2N3954
Min Max
-100
-600
-50

2N3954A
M,n Max
-100
-500
-50

-10

-1.0

-4.5

2.0
-42
-05 -4.0
-50
-250
05 50
1000 3000
1000
35

-05
05
1000
1000

2N3955
Max
-100
-500
-50

Min

2N3955A
Max
-100
-500
-50

Min

Unit

VGS - -30 V,
VOS=O
VOS 0,
IG =-I)1A
VOS 20V,
10
= 1 nA
V
VOS= 0,
!G..= 1 rnA
VOS=20V
pA VOS 20 V,
nA 10 = 200)1A
VOS-20V,
rnA VGS=O

-4.5

-1.0 -45

-1.0

20
-4.2
-40
-50
-250
50
3000
35

20
-42
-0.5 -40
-50
-250
05 50
1000 3000
1000
35

20
-4.2
0.5 -40
-50
-250
05 5.0
1000 3000
1000
.u mho
VOS=20V,
35
VGS=O
40

-45

Common-Source Input
Capacitance
Common-Source Reverse
Transfer Capacitance

40

40

4.0

12

12

12

1.2

pF

16

Cdgo

Drain-Gate Capacitance

1.5

1.5

1.5

1.5

17

NF

Common Source Spot
NOise Figure

05

0.5

05

05

dB

10

10

10

10

nA

-

Differential Gate
18
IIG1- IG21
Current
1- M
Saturation Dram Current
19 A IOSS1/10SS2 Rat'o (Note 11
-T
Differential Gate-Source
20 C IVGS1-VGS21 Voltage
_H
Gate-Source
Differential
21 I
Voltage Change with
22"N t.IVGS1-VGS21 Temperature
_G
Transconductance RatiO
23
!lisl/9Is2
(Note II

0.95

1.0

095

50
08
1.0
097

10

1.0

0.95

5.0
0.4
0.5
097

Test Conditions

pA
nA

10

1.0

095

10.0
2.0
2.5
097

1.0

0.95

1.0

-

5.0
1.2
1.5

mV

10

-

ITA-125C

10 50llA
10 200)1A
TA-125C
1 1 kHz
1 200 MHz
1= 1 kHz

IEII

1= 1 MHz
VOG 10V,
IS= 0
VOS 20V,
VGS =0,
RG = 10 Mn
VOS 20V,
10 = 200)1A,
VOS - 20 V
VGS=O

1= 100 Hz
T = 125°C

VOS~20V,

T = 25°C to -55°C

10=2001lA

T-25 Cto 125 C
1= 1 kHz

* JEDEC registered data

NOTE:

NQP

1. Assumes smaller value in numerator.

Siliconix

3-5

.monolithic dual

H

Siliconix
Performance Curves NQP
See Section 4

n-channel JFETs
designed for • • •

•
•

BENEFITS
Range
• WideI G Dynamic
Specified @ V DS = 20 V

Low and Medium Frequency
DiHerential Amplifiers
High Input Impedance Amplifiers

• LowCissCapacitance
<4 pF
TO·71
Sea Section 6

*ABSOLUTE MAXIMUM RATINGS (25°C)
Any Lead-To-Case Voltage .................... ±100 V
Gate:Orail1 OJ Gate·~ource Voltage ............•.. -50 V
Gate Current ............................. " 50 rnA
Total Device Dissipation at (Each Side) ............. 250 mW
85°C Case Temperature (Both Sides) ............ 500 mW
Power Derating (Each Side) ................ 2.86 mWrC
(Both Sides) .........•...... 4.3 mWrC
Storage Temperature Range .............. -65 to +250°C
Lead Temperature (1/16" from case for 10seconds) ... 300°C

G,

~~
8,

G2

S2

Sz
Dz
G, 30 0'06

0,

20

,0

l

07 G2

S,

Bottom View

0,

Gz

"

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

1

2"
--=3

4_ T5
5 A
aT
_I
7 C

8

-9
10
i~
I...E...
13 D
I-V
14 N

I-~

15 I
I-C
16

117

18
I- M
19 A
I-T
20 C
H

'211
1_ N
22 G

'23"

Gate Reverse Current

BVGSS

Gate-Source tsreakdown
Voltage

-50

VGS(off)

Gate-Source Cutoff Voltage

-10

VGS(f)

Gate-Source Forward Voltage

VGS

Gate-Source Voltage

IG

Gate Operating Current

lOSS

Saturation Drain Current

IVI,I

Min

-0.5

0.5

Max

-500
-50

-4.5

2N3958
MIn

-100

-500

-1.0

Max

pA

-500

nA

-50
-4.5

-1.0

-4.5

2.0

2.0

-4.2

-4.2

-4.2

-0.5

-4.0

-0.5

pA

-250

-250

-250

nA
rnA

5.0

0.5

5.0

1000 3000

1000

3000

Transconductance

1000

1000

1000

35

35

= 150'C

VOS =OV,IG = 1 rnA

VOS= 20V,I0 = 200!,A

-50

1000 3000

Conductance

IT

VOS=20V,10=50!,A

-4.0

-50

0.5

VGS=-30V, VDS=O

VOS=20V,IO= 1 nA
V

-50

5.0

Test Conditions

VDS=OV,IG=-l!,A

2.0

-4.0

Unit

-100

Common-Source Forward

Common-Source Output

9o,

2N3957

Max
-100

IGSS

VOS=20V,10=200!,A

I T •. =125C
,

VO'S = 20 V, VGS = 0
f= 1 kHz
1= 200 MHz

!,rnho

1= 1 kHz

35
VDS = 20 V, VGS = 0

CISS

Common-Source Input
Capacitance

4.0

40

40

Crss

Common-Source Reverse
Transfer Capacitance

1.2

1.2

1.2

Cdgo

Drain-Gate Capacitance

1.5

1.5

1.5

NF

Common-Source Spot
NOise Figure

0.5

0.5

0.5

dB

VOS = 20 V, VGS = OV,
RG = 10M!),

1=100Hz

IiGJ-iG21

Differential Gate Reverse
Current

10

10

10

nA

VOS = 20 V, 10 = 200!,A

T = 125'C

IOSS1/ IOSS2

Saturation Drain Current
Ratio (Note 1)

1.0

-

VDS=20V, VGS=O

IvGS1-VGS2

Differential Gate-Source
Voltage

1

1= 1 MHz

0.95

Gate-Source Voltage
aIVGS1-VGS2 1 Differential Change With
Temperature
Transconductance Ratio
(Note 1)

9f,l/91,2

*JEDEC registered data
NOTE:
1. Assumes smaller value

3-6

2N3956
Moo

In

0.95

1.0

0.90

1.0

0.85

15

20

25

4.0

6.0

8.0

5.0

7.5

10.0

10

0.90

1.0

0.85

1.0

pF
VDG=10V,.IS=0

rnV

VDS = 20V,ID = 200!,A

T = 25'C to -55'C
T = 25'C to 125'C
1= 1 kHz

NQP

numerator.

Silicanix

n-channel JFETs·
designed for • • •

H

Siliconix

Performance Curves NCB
See Section 4

Switches
• Analog
Choppers
• Amplifiers
•

BENEFITS
I nsertion Loss
• Low
rOS(on) < 30 n (2N3970)
Off-Isolation
• Good
IO(off) < 250 pA

TO·18
See Section 6

*ABSOLUTE MAXIMUM RATINGS (25°C)
Reverse Gate·Drain or Gate·Source Voltage ......... -40 V
Gate Current ................................ 50 mA
Total Device Dissipation at 25°C ~ase Temperature
Derate Linearly at the Rate of 10 mWrC ........... 1.8 W
Storage Temperature Range .............. -65 to +200°C
Lead Temperature
(1/16" from case for 60 seconds) ............... 300°C

.~:

G.C

s

D

*ELECTRICAL CHARACTERISTICS (2S0C unless otherwise noted)
Characteristic
1

2'
'3

-

BVGSS

Gate Reverse Breakdown Voltage

lOGO

Dram Reverse Current

2N3970
M,n
-40

4

~

s

T
6 A
I- T
7 I
1- C

2N3972

2N3971

Max

Min

Max

Min

Max

250

250

250

pA

500

500

500

nA

250

250

250

pA

500

500

500

nA

VOG = 20V, IS = 0

12

D
V
N

150°C

10(0ff)

Drain Cutoff Current

VGS(off)

Gate-Source Cutoff Voltage

-4

-10

-2

-5

-0.5

-3

V

VOS=20V,10=lnA

lOSS

Saturation Drain Current
(Pulsewidth 300 p.s, duty cycle'; 3%)

50

150

25

75

5

30

mA

VOS = 20V, VGS = 0

VOS(on)

Drain-Source ON Voltage

V

VGS=O

rOS(on)

Static Drain-Source ON ReSistance

30

60

100

12

VGS=O.lo=lmA

rds(on)

Drain-Source ON Resistance

30

60

100

12

CISS

Common-Source Input Capacitance

25

25

25

Crss

Common-Source Reverse Transfer
Capacitance

6

6

6

td(on)

Turn-On Oelay T,me

10

15

40

tr

RlseT.me

10

15

40

toft

Turn-Off Time

30

60

100

VOS=20V,VGS=-12V

I 10=

15
1

111

14

IG = -1 p.A, VOS = 0

2

ITo

I-

Test Conditions

V

8

1'9

113

Unit

-40

-40

I

150°C

IEII

5mA

10 = 10mA

110=2OmA

f = 1 kHz

VGS-O,IO=O
VOS = 20 V, VGS = 0

pF

f= 1 MHz
VOS=O,VGS=-12V
VOO = 10 V, VGS(on) = 0

15

1m
1-

17

S

w

ns

2N3970
2N3971
2N3972

RL VGS(oft)
10(on)
20mA 45012 -10V
lOmA 85012 - 5 V
5mA 16K12 - 3 V

VDD

~DD'VDSlDN'

• JEOEC regIStered data.

IO(ONj

VIN

S
RC;
.. son..

Siliconix

VOUT

NCB
INPUT PULSE
RISE TIME 025n.
fALL TlME075ns
PULSE WIOTH lOOn.
PULSE RATE 550 pps

SAMPLING SCOPE
RlSETlME04nl
INPUT RESISTANCE 10 M
INPUT CAPACITANCE 1 5pF

3-7

H

n-channel JFETs
designed for . . .

Siliconix

Performance Curves NCB

See Section 4
BENEFITS

•
•
•
•

Analog Switches
Commutators
Choppers
Integrator Reset Switch

• Low I nsertion Loss
High Accuracy in Test Systems
rDS(on) < 30 n (2N4091)
• High 'Off-Isolation
ID(off) < 200 pA
• High Speed
trise < 10 ns (2N4091)
• Short Sample and Hold Aperture Time
Crss <5 pF

*ABSOLUTE MAXIMUM RATINGS (25°C)

Q

TO-18
See Section 6

Reverse Gate-Drain or Gate-Source Voltage ......... -40 V
Gate Current ............................... 10 rnA
Total Device Dissipation at 25°C Case Temperature
(Derate 10 mWrC) ....•.................... 1.8 W
Storage Temperature Range .............. -55 to +200°C
Lead Temperature
(1/16" from case for 60 seconds) .............. 300°C

.~:

D

S

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

l~r-

BVGSS

Gate-Source Breakdown Voltage

'DGO

Dram Reverse Current

2N4091

Min

2N4092

Max

-40

Mon

2N4093

Max

Min

-40

Max

-40

200

200

400

400

Unit

200

pA

400

nA

4

200

pA

5

400

nA

rr-

IS

r-

...!....
~
~
10

-

S
T
A
T
I
C

11

-

IDloff)

400

VGSloff)
IDSS

Saturation Dram Current
INote 1)

30

-10

-7

-1
8

15

V

VDS=20V,ID= 1 nA

mA

VDS = 20V, VGS = 0

02

13
:i4

0.2
80

n

VGS=O,ID=lmA

50

80

n

VGS - O,ID = 0

16

16

5

5

5

Turn-ON Delay Time

15

15

20

Rise Time

10

20

40

Turn-OFF Time

40

60

BO

'DSlon)

Static Drain-Source ON Resistance

30

50

16

D

'dslon)

Olraln-Source ON Resistance

30

CISS

Common-Source Input Capacitance

16

y

N

Crss

Common-Source Reverse Transfer
Capacitance

19
tdlon)
I- S
20 W tr
toff

* JEDEC registered data

i= 1 MHz
VDS= 0, VGS = -20 V
VDD = 3 V, VGSlon) = 0

ns

2N4091
2N4092
2N4093

~
D
S

Siliconix

'Dlon)
6.6mA
4
2.5

INPUT PULSE

RL

VIN

i= 1 kHz

VDS = 20V, VGS = 0

pF

VGSloff)
-12V
-8
-6

RL
425n
700
1120

NCB

VDD

NOTE:
1. Pulsewidth = 300 Ils, duty cycle';; 3%.

3-8

150°C

riD = S.6mA

121

150°C

ID =2 5 mA
mA

VGS=O

Dram-Source ON Voltage

150°C

I ID =4

V

VDSlon)

0.2

-15

18

-5

VGS = - 8 V

VGS=-12V

nA
-2

12

I~

VDS = 20 V

pt\

400
-5

150°C

VGS=- SV

nA

200
Gate-Source Cutoff Voltage

IG = -lilA, VDS = 0
VGS = -20 V, IS = 0

pA

200

Dram Cutoff Current

Test Conditions

V

RISE TIME
VOUT

SAMPLING SCOPE

< 1 ns

;~t~ET~~~T~ ~

=~

PULSE DUTY CYCLE
10%
PULSE GENERATOR IMPEDANCE son

RISETIME04ns
INPUT RESISTANCE 10 M
INPUT CAPACITANCE 1 7 pf

n-channel JFETs
designed for •

H

Siliconix

Performance Curves NT
See Section 4

• •

Input
• Ultra-High
Impedance Amplifiers

BENEFITS
• Low Power
loSS < 90 p.A (2N4117)
• Minimum Circuit Loading
IGSS < 1 pA (2N4117A Series)

Electrometers
pH Meters
Smoke Detectors
Intrusion Alarms

TO-72
See Section 6

*ABSOLUTE MAXIMUM RATINGS (25°C)
Gate-Drain or Gate-Source Voltage (Note 1) .....•.. -40 V
Gate-Current ............................... 50mA
Total Device Dissipation
(Derate 2 mWrC to 175°C) ................ 300mW
Storage Temperature Range ............ _. -65 to +175°C
Lead Temperature
(1/16" from case for 10 seconds). " ........... 255°C

"4:

G

~

0

~
s

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
2N4117/A
FN4117/A

Characteristic

Min

Gate Reverse Current

1

::2
3

-4
5
-6
-

IGSS

S
T
A
T
I

C

7

-

IGSS

2N4117 Senes Only
FN4117
Gate Reverse Current
2N4117A Series Only
FN4117A

-10

-10

-10

pA

-25

-25

-25

nA

-1

-1

-1

pA

-2.5

-2.5

-25

nA

-0.6

-1.8

-1

-3

-2

-6

Saturation Dram Current

0.03 0.09
0.015

008

0.24

0.20

060

210

80

250

100

330

(Note 2)

FN4117A

Common-Source Forward
Transconductance (Note 2)

9 N

gas

Conductance

Ciss

Common-Source Input
Capabltance

-c
11

Unit

C rss

Common-Source Output

Common-Source Reverse Transfer
Capacitance

-40

-40

-40
V

70

Test Conditions

Max

Gate·Source Cutoff Voltage

gls

I

Min

VGS(off)
IDSS

A
M

Max

Gate-5ource Breakdown Voltage

y

10

Min

2N4119
2N4119A

BVGSS

D

8

Max

2N4118
2N4118A

VGS = -20 V. VDS = 0

VGS = -20 V. VDS = 0

5

10

3

3

3

1.5

1.5

1.5

150°C

IG=-lI'A.VDS=O
VDS = 10 V. ID = 1 nA

mA

VDS= 10V.VGS=0

f

I'mho
3

150°C

~

1 kHz

VDS=1OV.VGS=0
pF

1= 1 MHz

NT

*JEDEC registered data.
NOTES:

1. Due to symmetrical geometry. these Units may be operated with source and drain leads Interchanged.
2. This parameter IS measured dUring a 2 ms Interval 100 ms after power is applied. (Not a JEDEC condition.)

Siliconix

3-9

n-channel JFETs
designed for • • •

H

Siliconix

Performance Curves NRUNPA
See Section 4

Small-Signal Amplifiers
• VHF
Amplifiers
• Oscillators
• Mixers
•

BENEFITS
• High Gain
Low Receiver NOise Figure

•

*ABSOLUTE MAXIMUM RATINGS (25°C)

TO-72
See Section 6

Gate-Drain or Gate-5ource Voltage (Note 1) ______ .. -30 V
Gate Current ............................... 10 mA
Drain Current
15 mA
Total Device Dissipation at (or below) 25°C
Free-Air Temperature ...................... , , " 300 mW
Derate Linearly to 175°e Free-Air Temperature at Rate
of2 mWre
Storage Temperature Range, , . , , , . , , , , , . , -65 to +200o e
Lead Temperature
(1/16" from case for 10 seconds), , , , , , , .. , . , , . 3000 e

..............................

'4:

G

~

g

D

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

2N4220,
2N4220A

Min
1

2'

-J

-4'
5

-

S
T
A
T
I
C

6
7

8
9
-

IGSS

Gate Reverse Current

~vGSS

Gate-Source Breakaown Voilage

VGS(otf)

Gate-Source Cutoff Voltage

VGS

Gate-Source Voltage

lOSS

Saturation Drain Current
(Note 21

9fs

0

V
N
A
M
10 I

IVlsl

Common-Source Forward

Transconductance (Note 2)
Common-Source Forward

Transadmlttance
Common-Source Output

2N4221,
2N4221A

Min

Max

2N4222,
2N4222A

Max

Min

-0.1

-0.1

-0.1

nA

-0.1

-0.1

-0.1

IlA

-30

-3D

-8
-2

-6

(2001 (2001

(5001

(5001

6

5

15

5000

2500

6000

-2.5

(501

(501

05

3

2

1000 4000

2000

-1

750

750

10

20

40

CISS

6

6

6

11

Crss

Common-Source Reverse Transfer
Capacitance

2

2

2

12

NF

NOISe F,gure, Only 2N4220A,
2N4221A,2N4222A

2.5

2.5

2.5

-c

-

Conductance (Note 2)

V
(IlAI
mA

*JEDEC registered data.

150·C

VOS= 15V,IO=0.1 nA
VOS=15V,IO=( I
VOS=15V,VGS=0
1= 1 kHz
1= 100 MHz
VOS = 15 V, VGS = 0

pF

dB

1=1 kHz

1= 1 MHz

VOS-15V,VGS=0
Rgen = 1 meg

1= 100 Hz

NRL/NPA

NOTES:
1. Due to symmetrical geometry. these umts may be operated with source and drain leads interchanged.
2. These parameters are measured dUring a 2 msec Interval 100 msec after d-c power IS applied.

3-10

V

I

=-lOp.A, \/OS= IJ

ILmho

Common-Source Input
Capacitance

90 s

VGS=-15V,VOS=0

!G

-5

-0.5

750

-30
-6

-4

Test Conditions

Uniu

Max

Siliconix

n-channel JFETs
designed for • • •

H
Siliconix

------

Performance Curves NRL/NH
See Section 4

• VHF Amplifiers
• Mixers

BENEFITS

• LowNFNoise
= 3 dB Typical @200 MHz
• EasyC Tuning
< 2 pF
rss

*ABSOLUTE MAXIMUM RATINGS (25°C)

:::t
MIlf

TO-72

Sae Section 6

Gate-Drain or Gate-Source Voltage (Note 1) __ ...... -30 V
Gate Current ............................... 10 mA
Drain Current .............................. 20mA
Total Device Dissipation at (or below) 25°C
Free-Air Temperature (Note 2) .............. 300 mW
Storage Temperature Range .............. '-65 to +200°C
Lead Temperature
( 1/16" from case for 10 seconds) .............. 300°C

I.!

'4:

G

~

~

0

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

2N4223
Mm

1

~

-

3
4

5

S
T
A
T
I
C

IGSS

Gate Reverse Current

6VGSS

Gate-Source Breakdown Voltage

VGS(ott)

Gate-Source Cutoff Voltage

VGS

Gate-Source Voltage

-

7

lOSS

Saturation Drain Current (Note 3)

gt,

Common-Source Forward
Transconductance (Note 3)

CISS

Common-Source Input
CapacItance (Output Shorted I

0
8

!-

y

N

9
10

C rss
H

IVIsI

!- I
11

-

12

G
H

1"'13

F
R
E

1-

Q

14

Mm

-0.25
-0.25

6

2N4224

Max

nA

-0.5

IlA

-0.1

-6

-0.1

-6

(025)

(0.5)

(0.5)

-10

-7

a

-1.0

-7.5

V

(0.3)

(0.21

(02)

(rnA)

3

18

2

20

3000

7000

2000

7500

rnA

VOS = 15 v, 10 = ( )

VOS=15V,VGS=0

t = 1 kHz

Ilmho

6

VOS=15V,VGS=0

t= 1 MHz

pF

2

2
2700

150°C

IG=-lO IlA,VOS=O

V
(nA)

(03)

6

Test Conditions

VGS=-20V,VOS=0
V

(0.251

Transfer Capacitance
Transadmmance

-0.5

-~O

-30

Common-Source Reverse

Common-Source Forward

Unit

Max

1700

9 155

Common-Source Input
Conductance (Output Shorted)

800

800

goss

Common-Source Output
Conductance (Input Shorted)

200

200

Gp ,

Small Signal Power Gain

NF

NOise Figure

J,lmho
VOS=ISV,VGS=O

f = 200 MHz

10
dB
5

* JEDEC registered data.

VOS=15V,VGS=O,
Rgen = 1 K

NRl./NH

NOTES:

1. Due to symmetncal geometry, these units may be operated With source and drain leads Interchanged.
2. Derate linearly to 175Q C free-air temperature at rate of 2 mWfC
3. These parameters are measured dUring a 2 msec Interval 100 msec after d-c power IS applied.

Siliconix

3-11

--

n-channel JFETs
designed for • • •

H

Siliconix

Performance CUIVeS NPA

See SectIon 4

• Small-Signal Amplifiers
• Choppers
• Voltage-Controlled Resistors

• LowNFNoise
< 1 dB at 1 kHz
Operation from Low Power Supply
• Voltages

*ABSOLUTE MAXIMUM RATINGS (25°C)

Off-Isolation as a Switch
• HighID(off)
< 50 pA

BENEFITS

< 1 V (2N4338)

VGS(off)

Biasing Design with Tightly
• Simple
Specified Parameter Tolerances
3:1 lOSS. Vp. gfs Ranges

Gate-Drain or Gate-Source Voltage (Note 1) ........ -SO V
Gate Current ............................... SOmA
Total Device Dissipation (Note 2) .............. 300 mW
Storage Temperature Range .............. -65 to +200°C
Maximum Operating Temperature ............... 17So C
Lead Temperature
(1/16" from case for 10 seconds) ............... 300°C

TO·1S
See Section 6

"4:

G,C

Ii

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise specified)
Characteristic

[....!.

IGSS

2

[-

2N4338

Min

Gate Reverse Current
Gate-Source Breakdown
Voltage

3 S BVGSS
_T
A
Gate-Source Cutoff
4 T VGS(off) Voltaqe

2N4339

Max

Min

2N4340

Ma.

Min

2N4341

Ma.

Min

Ma.

-0.1

-0.1

-0.1

-0.1

nA

-0 I

-0.1

-0.1

-0.1

IlA

-so

-50

-50

Test Conditions

Unit

VGS=-30V,VOS=0

-50

,150'C

IG=-1IlA,VOS=0
V

-03

-I

-0,6

-18

-I

-3

-2

-6

VOS = IS V, 10 = 0.1 IlA

~I

5

C

10(off)

Dram Cutoff Current

lOSS

Saturation Dram Current
(Note 3)

6
7

-

8

Qfs
90S

-0
9 V rds(on)
_A
N
10 A Ciss
_M
I
II C Crss

-

12

NF

Common-Source Forward

Transconductance (Note 3)
Common-SouTce Output
Conductance
Dram-Source ON

Resistance
Common-Source Input

0.05

0.05

0.05

0.07

nA

VOS= 15V

(-5)

(-5)

(-5)

(-10)

(V)

VGS= (

mA

VOS = 15 V, VGS = 0

02

0.6

O.S

1.5

1.2

3.6

3

9

600

1800

800

2400

1300

3000

2000

4000
Ilmho VOS= 15V, VGS=O

5

IS

30

60

2500

1700

1500

800

7

7

7

7

Common-Source Reverse
Transfer Capacitance

3

3

3

3

NOise Figure

I

I

I

I

Capacitance

f= I kHz
ohm

pF

dB

VOS=O, VGS=O

VOS = 15 V, VGS = 0

f= I MHz

VOS = IS V, VGS = 0
Rgen = I meg, BW = 200 Hz f = I kHz

NPA

* JEOEC registered data
NOTES:
1. Due to symmetrical geometry. these units may be operated with source and drain leads interchanged.
2. Derate linearly to 175°C free·alr temperature at rate of 2 mwtC
3 These parameters are measured during a 2 msec Interval 125 msec (I DSSl and 625 msec (9fs) after d-c power IS applied.
(Not a JEDEC conditIOn.)

3-12

)

SilicDnix

n-channel JFETs
designed for • • •

H

Siliconix

Performance Curves NCB
See Section 4
BENEFITS
Low Insertion Loss, High Accuracy in
• Test
Systems rOS(on) < 30 n

Switches
• Analog
• Commutators
• Choppers
• Integrator Reset Switch

(2N4391)
• No Offset or Error Voltages Generated
by Closed Switch
Purely Resistive
High Isolation Resistance from
Driver
High Off-Isolation IO(off) < 100 pA
High Speed tON < 20 ns

•
•

*ABSOLUTE MAXIMUM RATINGS (25°C)
Reverse Gate-Drain or Gate-Source Voltage ......... -40 V
Gate Curre~t ................................ 50 mA
Total Device Dissipation at 25°C Case Temperature
(Derate 10 mWrC) .......................... 1.8 W
Storage Temperature Range .............. -65 to +200°C
Lead Temperature
(1/16" from case for 60 seconds) ............... 300°C

1

2"
-3

-4

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

2N4391
Mon

2N4392

Max

Mon

2N4393

Max

M,n

-100

-100

-100

pA

-200

-200

-200

nA

100

pA

200

nA

-40

-40

-40

"5

~
-:;
"8
~

-10

11

S
T
A
T
I

c

-

12

10(011)

Dram Cutoff Current

pA

200

nA

VGS= -5 V
VOS = 20 V

Gate-Source Forward Voltage

VGS(off)

Gate-Source Cutoff Voltage

-4

-10

-2

-5

-05

-3

lOSS

Saturation Dram Current
(Note 1)

50

150

25

75

5

30

1

1

1

0.4

VGS=-12V

V

Dram Source ON Voltage

'OS(on)

StatIc Dram-Source ON ReSistance

30

60

100

0
V
N

rds(on)

Dram-Source ON ReSistance

30

60

100

CISS

Common-Source Input Capacitance

14

14

14

Crss

Common-Source Reverse Transfer
Capacitance

td(on)

Turn-ON Delay Time

15

t,

3.5
3.5

110 -6mA

1'0 -12 mA
VGS = 0, 10 = 1 mA

n
n

Rise Time
Turn-OFF Delay Time

5

5

5

20

35

50

25

tl

Fall Time

15

20

30

pF

I VGS - I VGS--

15

5 V 1= 1 MHz

7V
-12 V

VOO = 10 V, VGS(on) - 0
ns

2N4391
2N4392
2N4393

'O(on)
12mA
6
3

VDD
51 n

* JEDEC registered data

NOTE.
1 Pulse test required, pulse width'" 300 /lS, duty cycle ~ 3%.

1000pF
PULSE o--i

': i:Kl!
VIN
SCOPE
51 n
~

Siliconix

1 kHz

VOS=20V,VGS=0

VGS

ldloff)

I

VGS-O, 10-0

3.5
15

150°C

110 = 3 mA
VGS=O

VOS=O

~
23 S
"24w

150°C

VOS=20V,VGS=0

04

17

150°C

VOS=20V,10=1 nA

mA

V

VOS(on)

VGS = -7 V

IG = 1 mA, VOS = 0

0.4

14
15
16
~
20
21

IG = -1 !lAo VOS = 0

nA

VGS(I)

S

I
I150°C

VGS=-20V.VOS=0

pA

100
200

D

Test Conditions

V

100

13

18

Umt

Max

.fl\

.~:

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

Q

TO·1S
See Section 6

NCB

lOOOpF
f--VOUT

D

1'"1
5m

~

RL

VGS(off)
-12V
-7
-5

~

RL=(~J-5tn
Dlon)

SAMPLI NG SCOPE
RISE 'NPUT
TIME  25°C)
Storage Temperature Range
Lead Temperature
(1/16" from case for 10 seconds)

Q

TO-18
See Section 6

30V
.50mA
500mW
-65 to +200°C

[\

.~:

300°C

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)

I~
I~
31

I~t
I~T

Moo

BVGSS

Gate-Source Breakdown Voltage

IGSS

Gate Reverse Current

Dram Cutoff Current

I-J~

VGS(off)

Gate-Source Cutoff Voltage

lOSS

Saturation Drain Current (Note 2)

I~

VGS(f)

Forward Gate-Source Voltage

I-jC
10

I~
Im~
12,

~

13 'I

15
17

30

Moo

Dram-Source ON Voltage

2N5116

Max

30

Min

V

500

500

pA

10

1.0

1.0

IlA

-50P
-10

-500

pA

-1.0

IlA

5

10

3

6

1

4

-30

-90

-15

-50

-5

-25

ReSistance

-1

-1

150

n

100'

150

n

25

25

27

Common·Source Reverse Transfer
Capacitance

7

7

7

'd(on)

Turn-ON Delay'Tlme

6

10

25

10

20

35

6

8

20

15

30

60

If

Fall Time

If= 1 kHz
If= 1 MHz

VOS - 0, VGS = 12 V (2N5114)
VGS = 7 V 12N5115), VGS = 5 V (2N5116)
2N5114
10V

VOO

VGG

ns

RL
RG

.~ 15K

01pF

V,N

41-

5'1 12K ,
'
iSAMPLING
.,n
5,n
SCOPE

Siliconix

2N5115
6V

2N5116
6V

20V

12 V

8V

130n

910n

2000 n

lOOn

220n

390 n

-15 mA

-7mA

-3mA

PSB

RG

,

3-20

pF

VGS=O,IO=O

VOS--15, VGS-O

10(on)

:.JEDEC registered data
NOTES:
1. Due to symmetrical geometry these Units may be operated With
source and dram leads Interchanged.
2 Pulse Test PW 300 Ils, duty cycle""" 2

VGS=O,IO=-l rnA

100

Crss

H

VOS = -15 V (2N5115, 2N5116)
IG = -1 rnA, VOS = 0

75

Common-Source Input Capacitance

Rise Time

VOS = -15 V, 10 = -1 nA

VGS = 0, VOS = -18 V (2N5114)

VGS = 0,10 = -15 rnA (2N5114)
10 = -7 rnA 12N5115), 10 = -3 rnA 12N5116)

75

CISS

150·C

V

-0.6

Dram-Source ON

Turn·OFF Delay Time

V

-0.8

StatiC Drain-Source ON

Id(o")

VGS = 20V, VOS= 0

VOS = -15 V, VGS = 12 V (2N5114)
VGS = 7 V (2N51151,
150·C
VGS = 5 V (2N5115)

rnA

-13

'OS(on)

1r

IG = lilA, VOS = 0

-1

'dslon)

ReSistance

Test Conditions

Umt

Max

30

500

-10

VOSlon)

I
, T

~r

Max

-500

10(off)

,A

2N5115

2N5114

Characteristic

,

INPUT PULSE

SAMPLING SCOPE

RISE TIME < 1 ns
RISE TIME 0 4 ns
FALL TIME < 1 ns
INPUT RESISTANCE 10 Mn
PULSE WIDTH 100 ns
INPUT CAPACITANCE 1 5 pF
REPETITION RATE 1 MHz

monolithic dual
n-channel JFETs
designed for • • •

•
•

BENEFITS
Minimum System Error and Calibration
S mV Maximum Offset (2NS196, 97)
Low Drift
sp'v;oc Maximum (2NS196)
Simplifies Amplifier· Design
Low Output Conductance

•
•
•

G,

., .,
~~
G, 0 32

G2

~

UI

G2

D, s~

·2

VGS =-30V. Vos =0

1-

22

Ll.IVGS1-VGS2 1
Ll.T
(Note 21

Gate-Source Differential Voltage
Change With Temperature

isos1-Sos2 1

IS0·C

VOS = 20 V. 10 = 1 nA
VOG =20V.10 =200~A
12S·C
VOS=20V,VGS=0
VOS=20V.VGS-0
VOG - 20 V. 10 =200~A
VOS-20V,VGS=0
VOG - 20 V, 10 =200~A

1= 1 kHz

VOS=20V. VGS=O

1- 100 Hz,
RG = 10 Mn
1=1 kHz

2NS19B
Min Max

2NS199
Min Max

S

5

5

S

nA

VOG - 20 V. 12S·C
10=2001'A

Umt

Test Conditions

095

1

0.9S

1 0.9S

1

o 9S

1

-

VOS= 20V, VGS =OV

0.97

1

0.97

1 0.9S

1

o 9S

1

-

1= 1 kHz

S

S

10

IS

S

10

20

40

rnV
~vfc

1

-

1= 1 MHz

2NS197
Min Max

S

Differential Output Conductance

:8

IG=-I~A.VOS=O

2NS196
Min Max

Differential Gate Current

),

Test Conditions

VRZ

Saturation Drain Current Ratio
10SS1
(Note 11
IOSS2
Transconductance Ratio
91s1
-9"2
(Note 11
IVGS1-VGS2 1 Differential Gate-Source Voltage

'2
G,

Bottom View

IIGI-IG2 1

10

20

40

1

1

1

p.mho

VOG =20 V. TA = 2S·C
ID=200~A TB = 12S·C
TA - _SSDC
TB = 2S·C
1=1 kHz
NQP

.. JEDEC registered data.

NOTES:
1 Assumes smaller value in numerator

2 Measured at end pOints, T A and TB

Siliconix

~

Z

Z

a ,

*ELECTRICAL CHARACTERISTICS (2S0C unless otherwise noted)
Characteristic
Min
Max
Umt
1
pA
-2S
Gate Reverse Current
IGSS
1'2
-SO
nA
13' S BVGSS Gate-5ource Breakdown Voltage
-~O
I"'i' T VGS(olll Gate-Source Cutoff Voltage
-0.7
-4
V
A
15 T
Gate-5ource Voltage
-02
-3.B
I-=- I VGS
-15
pA
6 C IG
Gate Operating Current
-IS
nA
1'1
Saturation Dram Current
07
7
rnA
lOSS
Common-5ource Forward Transconductance
1000
4000
91s
I~9
Common-Source Forward Transconductance
700
1600
91s
pmho
1m 0 90S
Common-Source Output Conductance
50
lli" y 90S
Common-Source Output Conductance
4
I-=- N C ISS
Common-Source Input Capacitance
6
I..g. A
pF
13 M
Common-Source Reverse Transfer Capacitance
2
I - I C'SS
14 C NF
Spot NOise Figure
o.s
dB
1nV
IS
20
Equivalent Short·CircUlt Input NOise Voltage
en

-0
'I

-0

°2

°
670

UI

CO

·2

a
5

~

Z

UI

TO·71
See .Section 6

Gate-Drain or Gate-Source Voltage .••.•••••.•..•• -SO V
Gate Current ...•...••.......•...•..•...•.•. SOmA
Device Dissipation (Each Side), T A = 85°C
(Derate 2.56 mW;oC) ......•.•....•.•..••.. 250mW
Total Device Dissipation, T A = 8SoC
(Derate 4.3 mW;oC) ..•......•.•••.•....••• SOOmW
Storage Temperature Range •..••..•.••..• -65 to +200°C

-

UI

~

Performance Curves NQP
See Section 4

*ABSOLUTE MAXIMUM RATINGS (2S0C)

16
117
I-M
A
lB T
1- C
19 H
I-I
20 N
I_G
21

Z

Siliconix

DiHerential Amplifiers
FEY Input Op Amps

Characteristic

~

H

3-21

n-channel JFETs

H
Siliconix

designed for • • •

Performance .Curves NIP
See Section 4

ON Resistance
• Low
Analog Switches
• Commutators
• Choppers
Integrator Reset Capacitors
• Low
• Noise Audio Amplifiers

BENEFITS
Insertion Loss
• LowrOS(on)
< 5 n (2N5432)
• Small Error in Measurement Systems
VOS(on) < 50 mV (2N5432)
High Off-Isolation
10(off) < 200 pA
High Speed
~(on) <4ns
Low Noise Audio-Frequency Amplification
en < 2 nVIy'Hz at 1 kHz Typical

•
•
•

*ABSOLUTE MAXIMUM RATINGS (25°C)
Reverse Gate-Orain or Gate-Source Voltage ......... -25 V
Gate Current. .............................. 100 mA
Drain Current .............................. 400 mA
Total Device Dissipation at 25°C
Free-Air Temperature (Note 1) ............... 300 mW
Storage Temperature Range .............. -65 to +150°C
Lead Temperature
(1/16" from case for 10 seconds) ............... 300°C

TO-52
See Saction 6

.~:

G,C

~

s

D

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic
1

!-

2

1"3

:~5 AT

IGSS

Gate Reverse Current

BVGSS

Gate Source Breakdown Voltage

iOloll)

Dram Cutoff Current

VGSloff)

Gate-Source Cutoff Voltage

lOSS

Saturation Dram Current
INote 2)

rOSlon)

Static Dram-Source ON Resistance

VOSlon)

Dram-Source ON Voltage

2N5432
Min

7

T
I
C

1"8
Ig
10
1- 0
11

rds(on)

Dram-Source ON Resistance

CISS
I- Y
N
12
Crss

Common-Source Input Capacitance

13
114

S

115 w
-16

Common-Source Reverse Transfer

Capacitance

Min

I

-200
-25

-4

Max
-200

pA

-200

-200

nA

-25
200

200

pA

200

200

200

nA

-9

-3

-4

-1

100

VGS=-15V.VOS=0

V

200

-10

Test Conditions

Unit

-200

-25

150
2

2N5434

Min

Max

-200

S

16"
1-

2N5433

Max

30

vOS=5V.vGS=-iOit

V

VOS=5V.10=3nA

mA

VOS=15V.VGS=0

7

10

ohm

50

70

100

mV

5

7

10

30

30

15

15

15

Id{on)

Turn-ON Delay Time

4

4

4

Ir

Rise Time

1

1

1

Id{olf)

Turn-OF F Delay Time

II

Fan Time

6

6

6

30

30

30

150"C

IG = -1 I'A. VOS = 0

5

30

I

150"C

VGS=0.10=10mA

ohm VGS-O.IO -0

1-1 kHz

pF

VOS=0.VGS=-10V

1= 1 MHz

ns

VOO=15V.
145 n (2N5432)
VGS{on) = o.
RL = 143 n (2N5433)
VGS(olf) = -12 V.
140 n (2N5434)
10(on) = 10 mA

NIP

• JEOEC regIStered data.
NOTES:
1. Derate linearly at the rate 01 2.3 mWi"C.
2. Pulse test reqUired pulsewldth 300 I's. duty cycle';; 3%.

voo

~~.~~'
o
~
RL -

VIN

VOUT
RG S

son

-=-

3-22

Siliconix

-:'

INPUT PULSE
RISE TIME 0 25 ns
FALL TIME 075 ns
PULSE WIDTH 200 ns
PULSE RATE 550 pps

SAMPLING SCOPE
RISE TIME 0 4 ns
INPUT RESISTANCE 10 M
INPUT CAPACITANCE 1 5 pF

monolithic dual
n-channel JFETs

H

Siliconix

designed for • • •

Performance Curves NQP
See Section 4

and Medium Frequency
• Low
DiHerential Amplifiers

BENEFITS
Minimum System Error and Calibra• tion

*ABSOLUTE MAXIMUM RATINGS (25°C)
Any Lead-To-Case Voltage _ ••.•.••••••••••.... ±100 V
Gate-Drain or Gate-Source Voltage .•••.••....••• -50 V
Gate Current .••.••.••••••••••••••••••••.... 50 rnA
Total Device Dissipation at (Each Side) ............• 250 mW
85°C Case Temperature
(Both Sides) ....•..•.... 500 mW
Power Derating (Each Side) ••••••••••••.• 2.86 mWrC
(Both Sides) ••••.•••.•••••• 4.3 mWrC
Storage Temperature Range .•••••.•••••. -65 to +250°C
Lead Temperature (1/16" from case for 10 seconds) ••. 300°C

•

5 mV Offset Maximum (2N5452)
Simplifies Amplifier Design
Output Conductance Less that
1 J./mho
TO·71
See Section 6

G,

~~
8,

Characteristic

12..
1.3..
3 S
1- TA
4 T
15" CI

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown

Voltage

VGS(of!l
VGS

Gate-Source Cutoff

Voltage

It
I~

VGS(I)

lOSS

Gate-Source Voltage
Gate-Source Forward Voltage
Drain Saturation Current

I~9

gl.

Transconductance

90S

Common-Source Output
Conductance

11't
11't
I;';"
12

0
y

li4'

I

Ciss

N
I- A
13 M Crs,

Cdgo
1- C
15
en
116
NF

Common-Source Forward

Common.source Input

Capacitance
Common-Source Reverse
Transfer Capacitance

D2
G, 30 0506

21 N
1_ G
22

"

Bottom View

(25a C

unless otherwise noted)
2N5452
2N5453
2N5454
Umt
Min Max Min Max
Min
Max
-100
-100
-100 pA
-200
-200
-200 nA
-50
-50
-50

02

G2

"

Test Conditions
VGS=-30V, VOS=OV
VOS=

I

•

ITA=150C

0 V,IG =-IIlA

-1 -4.5
-1 -4.5
-1 -4.5 V VOS =20 V, 10 =1 nA
-0.2 -4.2 -0.2 -4.2 -0.2 -4.2
VOS =20V,Io =50llA
2
2
2
VOS=OV,IG=lmA
0.5 5.0 0.5 5.0
0.5 S.O mA VOS =20V, VGS =OV
1000 3000 1000 3000 1000 3000
1000
1000
1000
Ilmho VOS= 20V, VGS =0 V
3.0
3.0
3.0
VOS - 20 V,IO =200llA
1.0
1.0
1.0
4.0
4.0
4.0
VOS =20V, VGS =OV
1.2
1.2
1.2 pF

1= 1 kHz
1= 100 MHz

1= 1 MHz

1.5

1.5

VOG

20

20

!!Y.
20 VHz
0.5 dB

VOS =20V, VGS =0 V

1= 1 kHz

VDS=20V,VGS=OV,

1=100Hz

Input Noi.e Voltage

Common-Source Spot
NOise Figure

0.5

0.5

0.95

1.0

0.95

1.0

0.97

5.0
0.4
0.5
1.0

10.0
0.8
1.0
0.97 1.0

0.25

0.25

0.95

1.0

0.95

15.0
2.0
2.5
1.0

NOTE:
1. Assumes smaller value

0.25

-

=10V,IS=OV

RG =10M!2
VOS =20V, VGS= OV

mV
VOS

-

-

1= 1 kHz

1.5

Gate-Source Voltage
 100dB

designed for • • •

•

• Differential Amplifiers

•

ABSOLUTE MAXIMUM RATINGS (25°C)

TO·71

• Sea Section 6

Gate-Drain or Gate-Souce Voltage ............ -40 V
Gate Current ...•.••....•....•...••.•.•••••.. 50 mA
Device Dissipation (Each Side), TA = 85°C
(Derate 2.0 mW/oC .....•......••..•.••••• 250 mW
Total Device Dissipation T A = 85° C
(Derate 3.0 mW/o C) ........•..•.....••••. 375 mW
Storage Temperature Range ..•.••.. -65°C to +200°C
Lead Temperature
(1/16" from case for 30 seconds) ....••....• 300°C

G,

..
~~

G2

.,

'2

G,
D,

D:!
0'
06

,0
20

01 G2

,0

.,

G!.2

Bottom View

D,

"

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Min

Characteristic

1..2.
I~

IGSS

I""; •

I~
12
6

BVGSS
T
A VGSlotfl
T V,,<
I

e

17"

1-;';
I~

0
V
N
A
M
I

'13
I- e
14

'6

1,7

1'8

M
A
T

e

H
I
N
19 G

20

12'

IG - -, ~A, VOS =0
VOS -2DV,IO -1 nA

pA

VOG = 20 V, 10 = 200~A

-D2

-38
-'00

lOSS

SaturatIon Dram Current INote 1)
INote 1)

""

'f,

Common-Source Forward Transconductance

90.

Common-Source Output Conductance

90'
CISS

Common-Source Output Conductance

Crss

Common-Source Reverse Transfer Capacitance

'n

Equivalent Short CirCUIt Input
NOise Voltage

INote 1)

05

-'00
75

1000

4000

500

1000

IOSS2
IVGS,-VGS2 1

Differential GateSource Voltage

VGS = ·30 V, VOS = 0

125°C

mA

VOS = 20V, VGS - 0
VOS=20V,VGS=0
VOG=20V,10=200~A

pmho

,
pF

5
30
'5
10

12N55'5-24

Ma. Mon

'0
095

l>IVGS,-VGS2 1 Gate-Source Voltage
Differential Dnft
l>T
(Note 3)

,

095

Ma.

Mon Ma.

'0

10

,

095

,

Mon

095

nV

f - 1 kHz

Unit

Test Conditions

Ma.

Mon Ma.

10

10

nA

VDG-20V.
10 = 200~A

,

-

VOS= 20V, VGS= 0

mV

,

090

'0

'5

'5

5

10

20

40

80

40

VDG=20V,

80

10 '"
1905 1-9052 1
9151
9h2

CMRR

Differential Output
Conductance
Transconductance
Ratio (Notes 1 and 2)
Common Mode
Rejection Ratio
(Note 41

0'

0'

097

1 097

'00

'00

,

0'
095

,

0'

0'
095

,

0.90

,

12SoC

TA::: 2SoC
TB '" 125°C
pvlc

20

--

f::: 10 Hz

VOG =20V, 10 = 200~A

.iif,'

5

10

f::: 1 MHz

VDS '" 20 V, VGS '" 0

5

5

f= 1 kHz

VOS - 20V, VGS - 0
VOG =20V, 10 -200~A

25
12N55'5-19
2N5520-24

150°C

nA

2N5515,20 2N5516,2' 2N5511.22 2N5518,23 2N5519.24

Differential Gate
Current
Saturatlo'n Dram
Current Ratio
(Notes 1 and 2)

Test Conditions

'0

Common-Source Input Capacitance

I-

1-

V

-4

Gate Operating Current

lOSS,

nA

-07

Mo"

,-

-250

Gate-Source Cutoff Voltage
Gate Source Voltage

IG

IIG,-IG2 1

pA

-40

Characteristic

,5

Umt

Gate-Source Breakdown Voltage

Common-Source Forward Transconductance

8
1'9

I"'iii

Gate Reverse Current

Max

·25D

200~A

TA - -5SoC
TB = 25°C

pmho
f= 1 kHz

VDO - 10 to 20 V,

• JEDEC registered data
NOTES.
1 Pulse test required, pulsewldth ::: 300 ~s, duty cycle
2 Assumes smaller value In numerator

dB

90

ID=200~A

NQP

3 Measured at end pomts, T A and TB

<:. 3%.

l>VOO
) ,.1.VDD
4 CMRR::: 2010910 ( l>IVGS,-VGS21

Siliconix

CI

10 V

3-27

monolithic dual
n-channel JFETs

H

Siliconix

Performance CurvesNCB/NZB
See Section 4

designed for • • •

•

BENEFITS

•
•

General Purpose
DiHerential Amplifiers

High Input Impedance
IG< 5OpA.
Minimum System Error and Calibration
5 mV Offset Maximum (2N5545)
TO-71

*ABSOLUTE MAXIMUM RATINGS (25°C)

Se. Section 6

Gate-Drain or Gate-Source Voltage •••.•. , ...• , .••• -50 V
Gate Current .• , . . • . . . , . , . . • . . • . • . . . . . . • . . . . , 30 mA
Device Dissipation (Each Side), TA

= 25°C

G,

(Derate 1,67 mWrC) .. , ...••. , • . • . • . . • . . . . 250 mW

~~
8,

Total Device Dissipation, T A = 25°C

02

82

'z Dz

(Derate 2.67 mWrC) ., . . . • • . . • . . . • . . . . . . . • 400 mW

fo

Storage Temperature Range •.. , .. , • . . . • . . -65 to +200°C

0'
02,

0,

Lead T emperatLJ re

o

(1/16" from case for 30 seconds) . , •.• , .••••.•.• 300°C

670 62

a

' "

'2 _aDz
G,

Bottom View

0,

J\

8,

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

1
12'
1'3
14'
15'
1'6

S
T
A BVGSS
T VGS(off)
I
c IG
lOSS
7
9fs
1'6
0 gos

'9

'iii

V

-50
-0.5

Gate-Source Breakdown Voltage

Gate-Source Cutoff Voltage
Gate Operating Current
Saturation Drain Current

0.5
1500

Common-Source Forward Transconductance

Common-Source Output Conductance

C1S5

Common-Source Input Capacitance

N Crss
A
M
NF
11

Common-Source Reverse Transier Capacitance

.;..:..

-12

Min

Gate Reverse Current

IGSS

I'

2N5545
Min

Differential Gate Current

14

10SSl
IOSS2

Saturation Drain Current

15 M IVGS1-VGS2 1
A
T
C
H Il.IVGS1-VGS2 1
16 I
Il.T
N
i- G
9fsl
17
9fs2
118
190s 1-9os21

-

Ratio (Note

1)

0.95

2N5546

Max
5

Min

1

0.90

V
pA
mA

Min

1

0.90

IG =-1 p.A, VOS=O
VOS = 15 V.IO = 0.5 nA
VOG = 15 V, 10 = 200 p.A
VOS -15 V, VGS =0
f= 1 kHz

pF
dB
nV

v'HZ

1

Differential Gate-Source

5

10

15

5

10

15

10

20

40

Unit

f= 1 MHz
2N5545

VOG=15V, 2N5546
10 = 200p.A 2N5545
2N5546

10

20

VOG=15V,10=200p.A

-

VOS=15V,VGS=0

mV

VOG = 15V

40
VOG = 15V,I0 =200p.A

Transconductance Ratio

(Note 1)
Differential Output
Conductance

0.97

1
1

0.95

1
2

0.90

1

-

i= 10 HZ,
RG = 1 Mfl
f= 10 Hz

Test Conditions

nA

p.vfc

Differential Drift (Note 2)

L
I TA= 150°

VOS=15V,VGS=0

Voltage
Gate-Source Voltage

Test Conditions

VGS=-30V.VOS=0

p.mho

2N5547
Max
5

Max
5

• JEOEC registered data.
NOTES:

TA=125°C

10 = 50p.A
10=200p.A
TA = 25°C
TB = 125°C
TA = _55°C
TB = 25°C
f = 1 kHz

3 p.mho
NCB/NZB

1 Assumes smaller value in numerator.

2. Measured at end pOints, TA and TB.

3-28

pA

-4.5
-50
8
6000
25
6
2

180
200

IIG1-IG21

-

nA

Equivalent Short CirCUit Input Noise Voltage

13

-

-150

Spot NOise Figure

Characteristic

-

Unit

3.5
5

C
en

Max
-100

Siliconix

matched dual
n-channel JFETs
designed for • • •

H
Siliccnix

Performance Curves NCB
See Section 4

Differential
• Wideband
Amplifiers
• Commutators

BENEFITS
Gain
• High7500
Minimum 9fs
• Specified Matching Characteristics
~mho

*ABSOLUTE MAXIMUM RATINGS (25°C)

TO·71
See Section 6

..........................

Gate-Gate Voltage
±80V
Gate·Drain or Gate·Source Voltage .............. -40 V
Gate Current ............................... 50mA
Device Dissipation (Each Side), T A = 25°C
(Derate 2.2 mW;oC) ....................... 325mW
Total Device Dissipation, T A = 25°C
(Derate 3.3 mW;oC) ..............•........ 650mW
Storage Temperature Range .............. -65 to +200°C
Lead Temperature
(1/16" from case for 10 seconds) ............... 300°C

G,

~~
8,

G2

52

82

o· 02
o.

G, 30

0,

0 7 G2

20

Gt

,0

8,

G2

Ii

"

Bottom View

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic
1

2"
3"
4"
5"
"6
"7"

S
T BVGSS
A VGS(off)
T
I VGS(f)
C lOSS

8

9"

i'ON

iT~

A

117

mA

VOS=15V,VGS=0

100

n

10 = 1 mA, VGS - 0

7500

12,500

Common-Source Output Conductance

Crss
CISS

Common-Source Reverse Transfer CapaCitance
Common-Source Input Capacitance
Spot NOise Figure

1.0

Equivalent Short CircUit Input NOIse Voltage

50

9f.2

pF

12

2N5565

Min

Max

M,n

Max

095

1

0.95

1

0.95

1

5

10

20

10

25

50

Unit

-

095

1

25
0.90

1

50
0.90

1

f= 1 MHz
f - 10Hz, Rg = 1M
f= 10 Hz

v'Hz

Max

10

VOG=15V,10=2mA

dB
nV

2N5566

*JEDEC registered data_
NOTES:
1. Pulse test required, pulse width 300 /JS, duty cycle
2. Assumes smaller value In numerator
3. Measured at ends POints, TA and TB.

f= 1 kHz

3

Test Conditions

VOS = 15 V, VGS = 0

mV

I'VI

Transconductance Ratio
(Note. 1 and 2)

f= 100 MHz

Jlmho

Min

~IVGS1-VGS21 Gate-Source Voltage
DifferentIal Oroft (Note 3)
~T
9f.l

f= 1 kHz

7000
45

2N5564

I
I 150'C

VOS=OV,IG = 2 mA

30

90.

Differential Gate-Source
Voltage

VOS = 15 V,IO = 1 nA

1.0

9f.

IVGS1-V GS2 1

V

5

Common-Source Forward Transconductance
(Note 1)

Saturation Drain Current
Ratio (Note. 1 and 2)

VGS=-20V, VOS=O
IG=-lI'A,VOS=O

-3

rOS(on)

IOSS2

nA

-40
-05

Gate-Source Voltage

10SSl

Test Conditions

pA

-200

Characteristics

15 T
-C
H
16 I
N
G

Unit

Saturation Drain Current (Note 1)
Static Dram Source ON Resistance

121 NF
=C
13
en

14
-M

Max
-100

Gate-5ource Breakdown Voltage
Gate-Source Cutoff Voltage

0

y

Min

Gate-Reverse Current

IGSS

'c
-

TA = 25'C
TB = 125'C
VOS=15V,10=2mA

TA = -55'C
TB = 25'C
f= 1 kHz

NCB
~

3%.

Silicanix

3-29

--

n-channel JFETs
designed for • • •

H

Siliconix

Performance Curves NCB/NZB
See Sedion 4

Switches
• Analog
Commutators
• Choppers
•

BENEFITS
Low Cost
• Industry
Package
• AutomaticStandard
I
nsertion
• Fast Switching Package
• trise < 5 ns (2N5638)
I nsertion Loss
• LowrDS(on}
< 30 n (2N5638)
Short
Sample
• Crss <4 pFand Hold Aperture Time

*~ABSOLUTE

MAXIMUM RATINGS (25°C)
Drain-Source Breakdown Voltage ................ 30V
Drain-Gate Breakdown Voltage
30V
Source-Gate Breakdown Voltage ................. 30V
Forward Gate Current ........................ 10mA
Total Device Dissipation at TLEAD = 25°e ...... 625mW
Derate above 25°e
5.68 mWre
Operating Junction Temperature Range ..... -65 to +135°e
Storage Temperature Range .............. -65 to +150°C
Lead Temperature
(1/16" from case for 10 seconds) ............... 3000 e

Plastic

.................

TO-92
See Section 6

...................

o~:

GD
s c
o c

0

Bottom View

s

G

i*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

2N5638

Min

-

1

BVGSS

2. s

Gate-Source Breakdown
Voltage

2N5639

Max Min

-30

2N5640

Max Min

-30

Unit

-30

V

-1.0

-1.0

-1.0

nA

3 T

-1.0

-1.0

-1.0

IJA

4A

1.0

1.0

1.0

nA

10

1.0

1.0 Ill\,

IGSS

Gate Reverse Current

Test Conditions

Max
IG=-101JA.VOS=0
VGS=-15V.VOS=0

TA = +10o"C

VOS = 15 V. VGS = -12 V 12N5638)
"GS = -8 V (2F\J5539}, '-'GS - -6'1 (21'J564C)

ST
1
-C

10(011)

Dram Cutoff Current

"6

lOSS

Saturation Dram Current

- 7

VOSlon)

Drain-Source ON Voltage

0.5

0.5

0.5

8

rOSlon)

Static Oram-5ource ON
Resistance

30

60

100

9

rdslon)

Resistance

30

60

100

CIIS

Common-Source Input
Capacitance

10

10

10

C rss

Common-Source Reverse
Transfer Capacitance

4.0

4.0

4.0

Idlon)

Turn-On Oelay Time

4.0

6.0

8.0

VOO=10V

1010nl=12 mA 12N563BIRL = BOO

tr

Rise Time

5.0

8.0

10

VGSlon)= 0

'Olon)= 6,mA 12NS6391 RL = 1.6k

tdlo!!)

Turn-OFF Delay Time

5.0

10

15

tl

Fall Time

10

20

30

.1-

0
10 y
I- N
11
12

1-

,ll S
14 W

115

.

50

25

5.0

mA

VOS = 20 V, VGS = 0 INote 1)

V

VGS = 0,10 = 12 mA 12NS63B),

-

TA=I~COC

10 = 6 rnA 12N5639), 10 = 3 rnA 12N5640)

Orain-5ource ON

JEOEC regIStered data

NOTE:

n

pF

nsec

10 = 1 mA, VGS = 0
VGS=O,IO=O

1=1 kHz

VGS = -12 V, VOS = 0

1= 1 MHz

VGSloff)= -10 V '010nl=3 mA 12N5640)

RL - VOD -lrDS(on! +501
'0

~~~~:!k..t= VGS(on!
~9"

1 Pulse test PW .;; 300 f.JSec, duty cycle';; 3.0%

--i

-----vGsc••,

1-'.-1.1.::: "",,'

~~tr

~~:~TBJ

10%

voo

IcPU~C
GENERATOR

10Kn{

;_

~

~

n 12N563BI
n 12N56391
RL =3.2k n 12N56401
NCB/NZB

o 1J'F
TO 50 OHM SCOPE B

__

,~OO1"FI
TO 50 OHM SCOPE A
SCOPE
TEKTRONIX 561A
OR EQUIVALENT

3-30

Siliconix

,

matched dual
n-channel JFETs
designed for • • •

H
Siliconix

Performance Curves
See Section 4

NT

BENEFITS
Matching Characteristics Specified
• High
Input Impedance

Differential Amplifiers
• High
Input
• Impedance
Amplifiers

•

= 1 pA Max (2N5906-9)

IG

TO·78
See Section 6

ABSOLUTE MAXIMUM RATINGS (25°C)
Gate-to-Gate Voltage ........................ ±80V
Gate-Drain or Gate-Source Voltage ............... -40 V
Gate Current ................................ 10 mA
Device Dissipation (Each Side), T A = 25°C
(Derate 3 mWrC) ........................ 367mW
Total Device Dissipation, T A = 25°C
(Derate 4 mWrC) ........................ 500mW
Storage Temperature Range .........•.... -65 to + 200°C

0,

~~
s,

c
0,

62

82

S2

J

0 50 D2

'0

06 G2
7

20

0,

10

°2

S,

[

Bottom View

~\

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
CharactenstlC

1-2.
I~
I~
4

S
T
A

:5' ~

'6'
I...!
9

1;;1'2
1_
13

114
1_

IGSS

Gate Reverse Current
Gate-Source Breakdown Voltage

-40

VGS'off)
VGS

Gate-Source Cutoff Voltage

·0.6

Gate Source Voltage

IG

Gate Operating Current

lOSS

Saturation Drain Current

9"

Transconductance

'0.

Common-Source Output Conductdnce

C ISS

Common-Source Input Capacitance

ens

Common Source Reverse Transfer
Capacitance

0
V

N

~
I
C

15

116

Transconductance

'0'

Common-Source Output Conductance

'n

EqUivalent Short CIrCUIt Input

NF

Spot NOise Figure

17
"Gl-IG2'

1-

IOSSl
19
I _ M IOSS2
A
9f51
20 T
C 91s2

1- H

I~I

1VGS1-VGS2'

(Note 1)

Transconductance RatiO
(Note 1)

Differential Gate-Source Voltage

N

22 G

123

1'24

A1VGS,-VGS2' Gate-Source Voltage DIfferential
Drift INote 21
AT
19os1-90s2 1

Differential Output Conductance

pA

-5

nA

-45

V

VDS .... 10 V. 10 - , nA
VOG '" 10 V,IO;\O 30p.A

-3

·1

pA

-3

-1

nA
pA

500

70

260

70

250

3

3
, 5
50

pF

'50

1

1

02

0'

3

1

f = 1 kHz
VOS'" 10V, VGS = 0
f= 1 MHz

j.Jmho

f'" 1 kHz

~

VOS= 10V.VGS=O

dB

2N5903.7

2N5904.8

2N5905.9

Mon

Mon

Mon

M,n

095

097

Max

Max

Max

20

20

20

20

02

02

02

02

1

095

1

097

1

095

1

095

--

VOG::: lOV.IO::: 30llA

2N5902,6
Max

125"C

12SOC

pmho

5

15
150

I
I

-4

30

50

VGS=-20V.VOS=0
IG--lpA.VOS=O

500

Differential Gate Current
Saturation Dram Current RatiO

-2

30

NOise Voltage

Characteristic

'18

-46
-4

-40
-06

Test Conditions

Unit

Max

5

Common-Source Forward

"Is

2N5906-9
M,n

-10

Common-Source Forward

'10

Max

-5

BVGSS

C

I,

2N6902-5
Mon

,

0.95

1

095

1

,

5

5

10

15

5

10

20

40

URit

nA

-

-

10

20

40

02

02

02

02

Test Conditions
VOG=10V, 2N5902·5
10 =30I1A.
2N5906·9
TA"'25"C
VOS=10V,VGS=O

f = 1 kHz

mV
VOG::; lOV, TA- 2Soe
T6 = 12SDC
'0;:: 30pA

/NtC
5

f - lOa Hz,
RG = 10 M

pmho

TA = _55°C
TB = 25"C
f= 1 kHz

• JEDEC regIstered data
NOTES:
1. Assumes smaller value 1n numerator
2. Measured at end pOints, TA and TB

Siliconix

3·31

matched dual
n-channel JFETs
designed for • • •

-- •
0-

H

Siliconix

Performance Curves NZf..D
See Section 4
BENEFITS
through 100 MHz
• HighgfsGain
> 5000 ~mho

Wideband Differential
Amplifiers

1ft

Z

~

• Matching Characteristics Specified
TO·78
See SectIon 6

ABSOLUTE MAXIMUM RATINGS (25°C)

........................

±80V
Gate·to·Gate Voltage
Gate·Drain or Gate·Source Voltage ..........•... -25 V
Gate Current ............................... 50 rnA
Device Dissipation (Each Side), (Derate 3 mW;oC) .. 367mW
Total Device Dissipation,(Derate 4 mW;oC) ....... 500mW
Storage Temperature Range ...•........•. -65 to +200 0 c
Lead Temperature
(1/16" from case for 10 seconds) ............... 3000 C

G,

~~
s,

8,

c

405

30

G,

G2

S2

°2
06

0
'0

0 G2
7
10

0,

J ~,
0,

8,

Bottom View

[

*ELECTRICAL CHARACTERISTICS (250 unless otherwise noted)
Min

Characteristic
1

12"

IGSS

Gate Reverse Current

S
T
A
15
T
II

BVGSS

Gate·Source Breakdown Voltage

VGS(off)

Gate·Source Cutoff Voltage

VGS

Gate·Source Voltage

IG

Gate Operating Current

I~

l"t
6

C

1-

7

lOSS

8
19
Iiii' 0
y
I
112 N
A
113 M
I
14 C

'iT

-

-

15

(Note 1)

-5
-4
-100

pA

VOG = 10 V,IO = 5 mA

-100

nA

7

40
10,000
10,000

90S

Common-Source Output Conductance

100

90S

Common~Source

150

Output Conductance

Common-Suurct! input Capacitance
Common-Source Reverse Transfer Capacitance

1.2

Equivalent Short Circuit Input NOise Voltage

20

Spot Noise Figure

Differential Gate Current

17

IVGS1-V GS2 1

(Notes 1 and 2)

Min

20
0.95

Differential Gate-Source Voltage

1

Max
20

095

1

10

15

20

40

20
0.95

1

* JEDEC registered data

1

f= 100 MHz
f= 1 kHz
f = 100 MHz

pF

VOG=10V.10=5mA

nV

f= 10kHz
RG = lOOK

dB
Unit
nA

-

f= 1 MHz
f = 10 kHz

VFiZ

Tast Conditions
VOG = 10 V. 10 = 5 mA

TA = 125°C

VOS= 10V, VGS=O

mV

40
0.95

TA = 125°C

f= 1 kHz

/lvtc

G
Transconductance Ratio (Note 2)

2N5912

Max

TA = 150°C

VOS = 10 V, VGS = 0 V

/lmho

1

aIVGS1-V GS2 1 Gate-Source Voltage Differential
Orift (Note 3)
aT

-9fsl
9152

mA

5

Ciss
Crss

Saturation Drain Current Ratio

-

TA = 25°C
TB = 125°C
VOG = 10 V, 10 = 5 mA

TA = _55°C
TB = 25°C
f= 1 kHz

NZF-D

NOTES:
1. Pulsewidth" 300 1lS. duty cycle" 3%

2_ Assumes smaller value In numerator.
3. Measured at end POints, T A and Ta.

3-32

VOS = 10 V. 10 = 1 nA

5000

Min

VGS = -15 V. VOS = 0

V

5000

IIGHG21

21

-1
-0.3

Forward Transconductance

en

Test Conditions

IG =-1 /lA, VOS=O

Common-Source Forward Transconductance

10SS1
IOSS2

-

nA

9fs

~

19 Il
-I
20 N

-250

Common~Source

2N5911

A
T
C

pA

9fs

NF

M

-100

-25

Saturation Drain Current

Characteristic

-18
-

Unit

Max

Silicanix

monolithic dual
n-channel JFETs

Performance Curves NNR
See Sedion 4

1

BVGSS

-

2

IGSS

3
4
5

5 VGS(off)
T
A
T VGSton)

,

C
lOSS

~
7

-

-

8
9

10
11

0

Y
N
A
M
I
C

12

-

13
14
15

,M
A

Gate-Source Cutoff
Voltage

Min

-35
50

-35
-50

Saturation Dram Current
(Note 2)
Gate Current (Note 11

9f.

Common Source Forward
Transconductance (Note 2)

9 0S

Common-Source Output
Conductance

05

100

Input

0,

20

-35

-3.0

-15
-02

100

05

-30

Test Conditions
Vos = O"G

pA

VOS ~ O'VGS
VOS

V

100

VOS
VG5

10V.
=0

= 15V.

rnA
pA

VOG

-5

nA

'0 = 200l'A

20

20

20

30

30

eN

EqUivalent Short-Circuit
Input NOise Voltage

15

15

15

CMRR

Common-Mode Rejection
RatiO INote 3)

5

Vos == 10V,

VOG

10

nV

25

25

300,,5 duty cycle ~ 3% 3 CMRR '" 2010910

~

Silicanix

= 15V.
~

= 1 kHz

f'" 1 MHz

15V.

f

=0

=::

dB

VoG '" 10 to 20 V. 10

rnV

VoG

6V

AlV GS1

4 Measured at end pomts. TA' Te and TC

VOS
VG5

=

10 V. 10

=

VoG = 10V.
10 = 200"A

p'vrc

50

f

10 '" 200~A

,;Hi

95
10

-

TA - 125"C

VG5. 0

pF

95

= 200l'A

7000

30

=::

= 15 V, '0 = 1 nA

VOG == 15 V, '0

-5
2000

= -15V

-23

-5

7000

= -l~A

V

-5

2000

I G2\,

~ '2

Unit

M..

Crss

1 Appro)umatelv doubles for every lOGe mcrease m TA 2 Pulse test duration

S

,0

Bottom View

80

NOTES

Z

0-

07 G2

'1

80

Gate-Source Voltage Dlfferentlal Drift (Note 4)

N

06

-5

95

0-

02

o·

G, 30

80

Differential Gate-Source
Voltage

=

82

Common Source Reverse
Transfer Capacitance

T
C IVGSl - VG52'
H
I 6f\/G51 - VGS~
N
6r
G

0-

'2

2N690717A

Min

-23
05

8,

#lmho

Capacltdnce

N

Z

G2

-5

7000

.2000

M..

~~

-15
-02

-23

Voltage (on)

Common-~aurce

2N6906/6A

-15
-3.0

Gate-Source

IG

CISS

2N6905/5A
Min
Ma.

-02

=

TO·71

ABSOLUTE MAXIMUM RATINGS (25°C)
G,
Gate-Drain or Gate-Source Voltage ................... 35 V
Forward Gate Current ............................. 10 mA
Device Dissipation (each side)
@ TA = 85°C derate 2.6 mW%OC ............... 300 mW
Total Device Dissipation
@ TA = 85°C) ................................. 500 mW
Storage Temperature Range. '" ............ -65 to 200°C
ELECTRICAL CHARACTERISTICS (@ 25°C unless otherwise noted)

-

0CII

BENEFITS
• Minimum System Error and Calibration
5 mV Offset Maximum (2N6905)
95 dB Minimum CMRR (2N6905-07)
• Low Drift with Temperature
10 p,vrc Maximum (2N6905)
• Operates from Low Power Supply
Voltages
VGS(off) < 2.5 V
• Simplified Amplifier Design
Output Conductance < 2 p,mho
• Low Noise
en = 10 nVI v'Hz at 10Hz Typical

Noise FEY Input
• Low
Amplifiers
and Medium Frequency
• Low
Amplifiers
Impedance Converters
• Precision
• AmplifiersInstrumentation
• Comparators

Gate-Source Breakdown
Voltage
erslon
Gate Reverse Current
(Note 11

Z

Siliconix

designed for • • •

Charaderistic

N

H

DO

~

10 Hz

=

200"A

200"A

TA Ta
TC

=::

=

55"C.
+25GC
+125GC

lVOD = 10V

V GS2 1

3-33

-So n-channel JFET

IE

---en... designed for. • •

Siliconix

Performance Curves NBB
See Section 4

... • Infra-red Detector
Micropower Pre-amplifier
Z •
o

BENEFITS
• Reduced Component Count,
Lower Circuitry Cost
Input O,!,er Voltage Clamp by
Two Built·in Diodes
• Low Noise
• Low Leakage

0-0

~

•

-- •
o
o

...

-

•

Transducer Impedance
Conve'rter
Hearing Aid Pre-amplifier

D

G

U;

ABSOLUTE MAXIMUM RATINGS (25°C)
Gate-Drain or Gate-Source Voltage . ......... -30V
Gate-Current ................................. 10 mA
Total Device Dissipation (25°C) ............. 300 mW
Storage Temperature Range ........... -55 to 200°C
Operating Temperature Range ......... -55 to 150°C
Power Derating .......................... 2.4 mWrC
Lead Temperature (10 seconds @ 1/16") •••.•••. 300°C
.,

4th

~

-8
---...
I
o

en
-0

Z

~

.~.

* r--~~~ll
S

I

II
I

[)llb
:

s

:

L__ J I

I,I"

I.

r---1

I

'l ___
. ,l

L_________ J

0

TO·72

11I

1---""'(.8-----1

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
2N690B

Characteristics

Min

BVGSS

Gate·Source Breakdown Voltage (Note 1)

IGSS

Gate Reverse Current (Note 1)

VGS(off)

Gate Source Cutoff Voltage (Note 1)

lOSS

Saturation Drain Current (Note 1)

9ls

Common~Source Forward
Transconductance (Note 1)

gos

Common~Source

Max

2N6909
Min

Max

-30

-30
Typ

~

-25

-0.3

-1.B

0.05
100

Typ

2N6910

Min

Unit

Max

-30
Typ

~

-1 pA VG4

~

0 V. VOS

~

V

IG

pA

VGS ~ -15V. VOS ~ OV. VG4 ~ OV

0V

~

-25

~

-25

-0.6

-2.3

-0.9

-3.5

V

VOS ~ 10 V. 10 ~ 1 nA. VG4 - 0 V

2.0

0.20

3.5

0.6

5.0

rnA

VOS - 10 V. VGS - 0 V. VG4 - 0 V

3000

400

3500

1200

4000

-

Output Conductance

50

(Note 1)

Test Conditions

75

100

I"'mlio

VUS - 15 V, VGS = 0 V. YG4

=0 V

Ciss

Common-Source Input Capacitance

5.0

5.0

5.0

pF

VOS ~ 10V. VGS ~ 0 V. I ~ 1 MHz

Crss

Common-Source Reverse Transfer
Capacitance (Note 1)

2.0

2,0

2.0

pF

VOS ~ 10 V. VGS ~ 0 V. VG4 - 0 V.
FREQ ~ 1 MHz

en

Equivalent Short CirCUit Input
NOIse Voltage

25

.JHZ

VGS(I)

Gate-Source Forward Voltage (Note 1)

± 1.2

V

IG - ±0.5 rnA. VOS - 0 V. V04 - 0 V

:t10

pA

VG4

dB

VOS ~ 15 V. VGS ~ 0 V.
RGEN ~ 1 MEG. F ~ 1 kHz

IG4
NF

Forward Gate Diodes Current (Note 2)

Typ

fo-

25

Typ

~

± 1.2

~
±1

Noise Figure

:t10
1.0

25
:t

Typ

~

Typ

~

1.2

::t:10

Typ

r---;:,

1.0

1.0

NOTES:
1. Measured when the gate lead is shorted to the 4th lead. i.e •• characteristIc olthe FET only (VG4
2. FOlWard diodes' current when a voltage Is applied between the gate and the 4th lead.
Device Available in Surface Mount (SOT·l43)-Order Number

3·34

~

SST690B. SST6909. SST6910

Siliconix

nV

VOS ~ 10V. VGS ~ OV. I ~ 10Hz

~

±100 mV

NBB
~

0 V).

n-channel JFET
Amplifier

H

Siliconix

Performance Curves NBB
See Sedion 4

designed for • • •

••
•
•

-_.

--eft

BENEFITS
• Reduces Component Count,
Lower Circuitry Cost
• Input Over Voltage Clamp by
Two Built-in Diodes
• Monolithic Source Resistor
• Low Noise
• Low Leakage

Infra-red Detector
Micropower Pre-amplifier
Transducer Impedance
Converter
Hearing Aid Pre-amplifier

~.

G'

:. 1 !

ABSOLUTE MAXIMUM RATINGS (25°C)
Maximum Supply Voltage (VDD) .............. -30 V
Gate Current ................................ 100 mA
Total Device Dissipation (25°C) ............. 300 mW
Storage Temperature Range ........... -55 to 200°C
Operating Temperature Range.......... -55 to 150°C
Power Derating .......................... 2.4 mWfC
Lead Temperature (10 seconds @ 1116") ........ 300°C

~,

o
o

r-----------,1
r ~i':'

I

I

,---, I

:

s

:

I ~-,
n

b
'.
,---, I!

6 HiL __ J

I

0

I
! G! I
I"==-<
,--_.
II
IL __________
JI

TO-12

!-11r.as-----!

I l D!

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristi~

Min

Max

Unit

VGs(ope,)

Gate-Source Voltage

0.15

2.8

V

IO(oper)

Drain Current

5.0

85

p.A

"n

Equivalent Short Circuit
Input NOise Voltage

10

25

IG4

Forward Signal Current

±1

±10

Av

Source Follower Gain (AV)

Z(m)

Input Impedance

Z(out)

Output Impedance

Vf

Forward Voltage

IG

Gate Leakage

NF

0.75

30

Current

Typ

= 20 V. VG4 = 0 V (Note 1)

VOS = 10 V. VGS = 0 V
FREQ = 100 Hz

pA

VGS = ±100 mV

VN

VOO = 10 V. FREQ

100

Gil

VGS'" ±100 mV

Kil

VOO - 10 V. FREQ - 1 kHz.
VG4 = 0 V (Note 1)

45

1

70

= 1 kHz

IG = ±0.5 mAo VOS = 0 V, V04 = 0 V

±1.0

V

25

pA

VOO - 15 V, VG4 = 0 V (Note 1)

dB

VOO = 15 V, VG4 = 0 V.
RGEN = 1 Mil. F = 1 kHz

1

NOTE:
1. VG4 = 0 V, Test CondItion implies the gate and 4th lead are shorted.
In

'V'HZ

VOG

0.85

Noise Figure

Device Available

nV

Test Conditions

NBB

Surface Mount (SOT 1431-0rder Number-SST6911

Siliconix

3-35

IEII

z
(II)

H
enhancement-type
p-channel MOSFETs
Perfonnance Curves MRA
designed for •••
See Sedion 4

Siliconix

Input Impedance
• Ultra-High
Amplifiers

•
•

BENEFITS
Rugged MOS Gate Minimizes Handling
• Problems

Eledrometers
Smoke Detedors
pH Meters
Digital Switching Interfaces
Analog Switching

± 125 V Transient Capability
Gate-Leakage
• LowTypically
0_02 pA
Off-Isolation as a Switch
• HighlOSS
< 200 pA

*ABSOLUTE MAXIMUM RATINGS (25°C)
TO-72
See Section 6

Drain-Source or Gate-Source Voltage 3N 163 _..... -40 V
Drain-Source or Gate-Source Voltage 3N 164 ...... -30 V
Transient Gate-Source Voltage (Note 1) ......... ±125 V
Drain Current ............................. -50 rnA
Storage Temperature
-65 to +200°C
Operating Junction Temperature ......... -55 to +150°C
Total Device Dissipation
(Derate 3.0 mWrC to 150°C) .............. 375mW
Lead Temperature 1/16" From Case For 10 Seconds .. 265°C

.................

~

JD

Go---J~B

1.

B.C

D

G

*ELECTRICAL CHARACTERISTICS (25°C and VBS = 0 unless otherwise noted)
Characteristic

3N163
Min

IGSS

Min

Gate-Body Leakage Current

----s
----=-----f

T
A
T

~I

g C

-----;0

----;;-----;2
13 0

BVOSS Drain-Source Breakdown Voltage
BVSOS Source-Dram Breakdown Voltage
Gate Source Voltage
VGS
VGS 'h Gate-Source Threshold Voltage
Drain Cutoff Current
lOSS
Source Cutoff Current
ISOS
'O'onl ON Drain Current

14 N gos
--;SA C
ISS

!_M

Common-5ource Forward
Transconductance

l---;s

'd(onl

Turn-ON Delay Time

I~W

'r
'off

RiseTime

20

-30
-30
-2.5
-2

-6.5
-5
-200
-400
-30
250
4,000

-SOO

-30
300

1,000

4,000

2.5

2.5

0.7

0.7

3

3
12
24
50

VGS' -30 V, VOS' 0

V
oA
mA
n

jlmho

TA -12UOC

10 =-101lA, VGS' 0
'S·-10IlA, "GO· VRO - 0
VOS' -15 V,IO' -0.5 mA
VOS' Vr.S, '0' -101lA
VOS' -15 V, VGS' 0
VSO· -20 V, VGO = 0, VOB
VOS' -15 V, VGS - -10 V
VGS' -20 V,IO =-1001lA
VOS' -15 V,
10·-10mA

NOTE:
1, Transient gate-source voltage JEDEC registered a. ±125 V.
vlN
5011

d
RG

Siliconix

c

0

f'l kHz

pF

VOS' -15 V,IO' -10 mA f= 1 MHz

ns

VOO=-15V
'O(onl '-10mA
RG' RL = 1.5 kn

MRA

VDO

*JEDEC registered data

3-36

TA'125"C

pA

25~

12
24
50

Turn-OFF Time

-£.5
-5
-400

-3

250

Common-Source Input Capacitance

Coss

Crss

2,000

Common-Source Output
Conductance
Common-Source Reverse Transfer
Capacitance
Common-Source Output Capacitance

I~S

-5

rOS(an) Dram-Source ON Resistance

9fs

-y

16 I
i----;J C

-40
-40
-3
-2

Test Conditions

Unit

VGS = -40 V, VOS' 0
-10
-26

4

-Ss

Max

-10
-25

---!..

----4
----.2.

3N164

Max

vOUT
INPUT PULSE
RISE TIME..:;; 2 ns
PULSE WIDTH ~ 200 nl

SAMPLING SCOPE

t,<; 02ns
CIN"'2rF
RIN;>10Mn

n-channel JFETs
designed for • • •

H

Silicanix
Performance Curves NH
See Section 4

VHF/UHF Amplifiers
• Oscillators
• Mixers
•

BENEFITS
• Wide Band
High Yfs/Ciss Ratio
Low Feedback Capacitance
Crss = 0.85 pF Typical

•

• Selected I DSS and V GS Ranges

ABSOLUTE MAXIMUM RATINGS (25°C)
Drain-Gate Voltage ............................. 30 V
Drain-Source Voltage ........................... 30 V
Reverse Gate-Source Voltage ...................... 30 V
Forward Gate Current ......................... 10 mA
Continuous Device Dissipation
at (or Below) 25°C Free Air Temperature
(Note 1) ................................ 200 mW
Storage Temperature Range ............ -55°C to +150°C
Lead Temperature
(1/16" from case for 10 seconds) ........ , ...... 260°C

TO·92
See Section 6
• INSULATED CASE
• INSENSITIVE TO LIGHT

,~:

s

G

a

l!)
G

0

s

0

Bottom View

ELECTRICAL CHARACTERISTICS (25°C)
Characteristic
1

-

BVGSS

2

IGSS

Gate Reverse Current

3'
-S

lOSS

Saturation Dram Current

-

~I
7

-

-9
- 10
11

-

VGS

0
12 Y C rss
_N
13 A 1
"14M -g,s

Unit

Test Conditions

V

IG = -1 j.lA, VOS = 0

nA

VGS=-20V,VOS=0

25

rnA

VOS = 15 V, VGS = 0

BF244A

2.0

6.5

rnA

Selected Into Following
BF244B
Groups (Note 2)
BF244C

6.0

15

rnA

12

25

rnA

Corresponding to
lOSS groups

BF244A

-{).4

-2.2

V

BF244B

-1.6

-3.8

V

BF244C

-3.2

-7.5

V

-{l.5

-8

V

6.5

mrnho

VGS(off) Gate·Source Cutoff Voltage
gls

Max

-5

C

B

Typ

-30

2

4

T
5 A lOSS
-T

Min

Gate·Saurce Breakdown Voltage

Small·Signal Comman·Source Forward
Transconductance
Common-Source Reverse
Transfer Capacitance
Input Resistance

'
15 C

C ISS

Common-Source Input Capacitance

""16

Coss

Common-Source Output Capacitance

3

5.5
0.85 .

pF

VOS = 15 V,IO = 200j.lA

VOS = 15 V,IO = 1Oj.lA
VOS=15V,VGS=O,I=1 kHz
VOS=20V, VGS=-1 V

I 1= 100 MHz

25

kn

10

kn

VOS = 20 V, V'GS =-1 V

4

pF

VOS=20V,VGS=-1 V

1.6

pF

VOS = 20V, VGS =-1 V

NOTE:
1. Oerate linearly to 125°C Iree·aor temperature at the rate 01 2.5 mwtC.
2. Pulse test PW .. 300 j.lS, duty cycle .. 3%.

Silicanix

-

VOS = 15 V, VGS = 0

I 1=200MHz

NH

3-37

n-channel JFETs
designed for • • •

H

Billcanix
Performance Curves NH
See Sedion 4

VHF/UHF Amplifiers
• Oscillators
• Mixers
•

BENEFITS
• Wide Band
High Yfs/Ciss Ratio
Low Feedback Capacitance
Crss = 0.85 pF Typical

•

• Selected I DSS and V GS Ranges
ABSOLUTE MAXIMUM RATINGS (25°C)
Drain·Gate Voltage ............................. 30 V
Drain-Source Voltage ........................... 30 V
Reverse Gate-Source Voltage ...................... 30 V
Forward Gate Current ......................... 10 mA
Continuous Device Dissipation
at (or Below) 25°C Free Air Temperature
(Note 1) ................................ 200 mW
Storage Temperature Range ............ -55°C to +150°C
Lead Temperature
(1/16" from case for 10 seconds) ............... 260°C

TO·92

See Section 6
• INSULATED CASE

• INSENSITIVE TO LIGHT

.~:

Characteristic

-

Min

BVGSS

Gate-Source Breakdown Voltage

2

IGSS

Gate Reverse Current

iOSS

Saturation Drain Current

--;:I-=- S

BF245A

!~

T
5 A
1- T

I~

1---2..
8
Ig

lOSS

I
C

VGS

Selected Into Following
BF245B
Groups INote 21
BF245C

Corresponding to
lOSS groups

110
11

gfs

1-0
12 V Crss
I- N
13 A 1
M g,s

114

Typ

15 C

VGS = -20V. VOS =0
VOS = 15 V. VGS = 0

20

65

rnA

6.0

15

rnA

12

25

rnA

-2.2

V
V

BF245C

-3.2

-75

V

-{)5
3

55
085

Common·Source Input Capacitance
Common-Source Output Capacitance

-8

V

65

mmho

pF

VOS= 15V. VGS =0

VOS=15V.IO=200 /lA

VOS=15V.IO=IO/lA
VOS = 15 V. VGS = O. f = 1 kHz
VOS= 20V. VGS =

1V

I f=100MHz

25

k!l

10

kH

4

pF

VOS = 20 V. VGS = --1 V

16

pF

VOS = 20 V. VGS = -1 V

Input Resistance

CISS

Test Conditions
IG = -1 /lA. VOS = 0

nA

-3.8

Coss

C

rnA

16

Common-Source Reverse
Transfer Capacitance

C

S

25

-{).4

Transconductance

G

-5

BF245A

Smail-Signal Common-Source Forward

DO

2

NOTE:
1. Derate linearly to 125°C free-air temperature at the rate of 2 5 mWrC
2. Pulse test PW " 300 /lS. duty cycle'" 3%

3-38

Unit
V

I-I

""16

Max

-30

BF245B

VGSloff) Gate·Source Cutoff Voltage

D

G

Bottom View

ELECTRICAL CHARACTERISTICS (25°C)

1

s

Siliconix

VOS=20V.VGS=-IV

I f = 200 MHz
I'JH

n-channel JFETs
designed for • • •

m

H

"T1

Slllcanlx

en

en

rl>

Performance Curves NH
See Sedion 4

• UHF Amplifiers
• Mixers
• Oscillators

N

m
"'T1

N

en

BENEFITS

•
•

en

r-

High Gain
Gpg = 14 dB Typical at 800 MHz
Selected lOSS Ranges

m
m
"'T1

N

en

en

ABSOLUTE MAXIMUM RATINGS

r-

Drain-Gate Voltage _............................ 30 V
Drain-Source Voltage ........................... 30 V
Reverse Gate-Source Voltage ...................... 30 V
Forward Gate Current ......................... 50 mA
Total Device Dissipation @ 25°C ................ 350 mW
Derate above 25°C ...................... 3.5 mW/oC
Storage Temperature Range .............. -65 to +150°C
Lead Temperature
(1/16" from case for 10 seconds) ............. , .260°C

o

TO-92
See Section 6

• INSULATED CASE
• INSENSITIVE TO LIGHT

o~:

s

DD

Min

Characteristic

-2

3'

-4
-5

6"

-:;
8

-

BVOGO Drain-Gate Breakdown Veltage
S IGSS
T
VGSloffl
A
T lOSS
I
C
lOSS

9fs

9

gos
0
y
Ciss
N
11 A Crss
M
12 I flYfs)
C
Gpg
13

10

-

-

14

NF

Typ

-5
-7.5

-0.5

Drain Current at Zero Gate Voltage INote 1)

3

12

V

18

mA

3

7

mA

BF256LB

6

13

mA

BF256LC

11

18

mA

INote 1)
Common-Source Output

Conductance

4.5

5.5

VGS=-20V,VOS=0
VOS =15V,IO = 10nA

-

/lmho
4.5

pF

1.2

pF

f=l MHz

Capacitance

Cutoff Frequencv INote 2)

Test Conditions
IG = -1 /lA, VOS = 0

mmho

50

Common-Source Reverse Transfer

Common-Gate Neutralized Insertion

e

VOS=15V,VGS=0 f = 1 kHz

Common-Source Input Capacitance

Noise Figure

nA

BF256LA

Common-Source Forward Transconductance

Power Gain

Unit
V

Gate-Reverse Current

Gate-Source Cutoff Voltage

Selected into
Following Groups
INote 1)

Max

-30

e

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)

1

S

G

1000

MHz

14

d8

VOS = 10 V, RS = 47

n, f = 800 MHz

7.5

dB

VOS = 15 V, RS = 47

n, f

= 800 MHz

NH
NOTES:
1. Pulse test PW .. 300 /lS, duty cvcle .. 2%.
2. Frequency at which the real part of the forward transconductance falls 3 dB relative to the value at 1 kHz.

Siliconix

3-39

H
current regulator diodes
Performance Curves
designed for • • •
NKL NKM NKO See Section 4
Siliconix

Regulation
• Current
Limiting
• Current
• Biasing
• Low Voltage References

BENEFITS
Simple Two Lead Current Source
Current Insensitive to Temperature
Changes
Temperature Coefficient Better
Than 3000 ppm/oC On All Devices
• TO-18 Package for Improved Current
Control
Simplifies Floating Current Sources
No Power Supplies Required
1V Operation

•
•

•
•
ABSOLUTE MAXIMUM RATINGS (25°C)

TO-18 (MODIFIED)
See Section 6

.....................

Peak Operating Voltage
100 V
Forward Current
20 mA
Reverse Current .•••••••.•..•.••.•..••.•.•... 50 mA
Thermal Resistance 8JC
100°C/W
Power Dissipation at TC = 25°C
1.25 W
Operating Junction Temperature
-55 to +150°C
Storage Temperature· .••••.•••••.•.. -55° to +200° C

............................
..................
............
.....

a

z.

Symbol

'F'
RegUlatorCUMnt

Test Cortditlanl

Un..

z.

Dynamic
ImpHlince

Y,=Z5Y

V,_25Y

(Note')

(Note 2)

(mAl

Mll

.om

Min

M..

CR022

022

0198

0242

CnO.014
CR027
CR030
CR033

02.

UJlb

Ulb4

021
030
033

0243
0270
0297

CR039
CR043
CR047
CROS6
CR062

039
0.3
047
056
062

CR068
CR075
CR082
CR091
CRloo

CR,,.

M..

T,.

"

038

33
29
26
21

, 0
10
10
10
10

100
087
075
056
047

20
18
16
13
115

0400
0335
0290
0240
0205

Min

0297
0330
0363

115
'0'
9'
85
78

275
235
195
'60
135

0351
0387
0423
0504
0559

0429
0473
0517
0616
0682

410
330
270
'90
155

69
6'
56
50

068
075
082
091
100

0612
0675
0738
0819
0900

0748
0825
0902
'001
1100

135
115
100
088
080

85
72
60
52

0990
'08
117
126
135

1210
132
143
'54
165

070
064
'059
054
051

38
33

CRl30
CRl40
CRtSO

110
120
130
140
150

CR160
CRt80
CR200
CR220
CR240

'60
180
200
220
240

'44
'62

176
198
220
242
264

0475
0420
0395
0370
0345

CR270
CR300
CR330
CR3SO
CR390

270
300
330
360
390

297
330
363
396
429

CR4]O
CR470
CR530

430
470
530

367
423

473

'77

563

,80
198
216
243
270
297

32'
351

517

Peak OpentIng Voltage

YF" 25Y

Vf = 2SV

INote4)

-SS·C.;; TA..;" 25"C

O"C~TA"';5O"C

Y,=25V
2S·C ... TA ..::; 125"C

MlnVottI

Typ ppml"C

TypppmrC

Typ ppmt"C

+2600
+2400
+2100
+1800
+1500

+'900
+1650
+1400
+1150
+950

+1220

051
055

'00
'00
'00
'00
'00

, 05
105
110
120
130

065
071
077
09'
100

'00
'00
'00
100
100

+1050
+800
+550
+50
-200

+800
+350
+'50
-250
-450

+150
0
-200

170
150
130
110
095

115
120
125
129
135

070
075
080
085
095

100
100
100
100
100

250
200
-25
-200
-425

-SO

-375
-475
-550
-675
-825

25
22

0180
0155
0135
0115
0105

080
071
060
052
0'6

140
,.5
150
155
160

115
125
130
135

100
'00
100
100
'00

-'50
-675
-1050
-1125
-1150

'00
095
088
080
075

0092
0074
006'
0052
0044

035
030
025
022
020

165
175
185
195
200

050
055
060
065
070

'00
100
100
100
100

1300
'000
425
125

875
650
250
0
-225

0320
0300
0280
0265
0255

068
060
056
052
048

0035
0029
0024
0020
0017

0'8
014
013
011
010

215
225
235
2SO
260

075
085
090
085
100

100
100
100
'00
100

-'50
-375
-650
-825
-925

-425
-550
-750
-8SO
-900

0245
0235
0220

045
040
035

0014
0012
0010

009
008
005

275
290
310

110
"0
170

100
'00
'00

-1025
-1100
-1200

-1000
-1100
-1200

••
44

32

D.'
0.6

..

,

Pulse test-steady state currents may very
Pulse test-steady state Impedances may vary
Main Vf required to Insu,e IF > 08 IF1!mln)
Max VF where IF < 1 1 IF1(maxlls guaranteed

3-40

G

It: .. 11 IF1IMex)

NOTES:
1
2
3
4

Temperature CoefficIent rrypals)

•
0
M

VoII.

T,.

T,.

CR110

= 08 "11Mlnl
(Note 3)

MO

90
.0
70
60
50

Min

I,

VF=6V

A

.,

POV

VL

KlMMllmpedancti lImltlngVoltqe

C, CASE

CATHODE

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Parameter

~

Siliconix

725

-150
-.00

-550
-925

-toOO
-1200
-1300
-1250
-1225

+1050
+800
+600
+'50

•

K
L

-500
-700

-9SO
-1050
-1150
-1225
-1275

•
K

M

400
225
0
-225
-400

-600
-700
-875

-'-1100
000

-1200

-'-1400
300

••

0

current regulator diodes
designed for . . .

H

Silicanix

• Current Regulation
• Current Limiting
BENEFITS
• Simple Two Lead Current Source
• Current Insensitive to Temperature
Changes
Temperature Coefficient Better
Than O.15%/"C On All Devices
• TO-18 Package for Improved Current
Control
• Simplifies Floating Current Sources
No Power Supplies Required

• Biasing
• Low Voltage References
ABSOLUTE MAXIMUM RATINGS (25°C)
Peak Operating Voltage ...................... 100 V
Forward Current. . . . . . . . . . . . . . . . . . . . . . . . . .. 20 mA
Reverse Current ........................... 50 mA
Thermal Resistance 8JC ..................... 100°C/W
Power Dissipation atTc = 25°C ................ 1.25 W
Operating Junction Temperature ........ -55 to +150°C
Storage Temperature .................. -55 to +200°C

TO-1B (MODIFIED)
See Seclion 6

ANODE

C, CASE
CATHODE

A

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Svmbol
Parameter
Test Conditions

POV

IFI

Zd

VL

Peak Operating Voltage

Regulator Current

Dynamic Impedance

Limiting Voltage

IF = 1.1Fl(Max)

VF= 25V

VF= 25V

IF = 0.8 I Fl(Min)

(Note 1)

(Note 2)

(Note 3)

(Note 4)

Units

Maximum Volts

(mn)

(rnA)

Nom

Min

Max

Min

(V)
TVp

Max

TVp

1.0

0.5

9.5

1.05

0.7

CRR0240

100

0.240

O.IBO

0.300

5

CRR0360

100

0.360

0.270

0.450

2.5

CRR0560

100

0560

0.420

0.700

12

6

1.30

1.1

CRROBOO

100

O.BOO

0.600

1.000

O.B

5.2

1.35

0.85

13

CRR1250

100

1.250

0.937

1.560

0.5

2.5

1.60

1.3

CRR1950

100

1.950

1.460

2.440

0.37

O.B

1.95

0.65

CRR2900

100

2.900

2.160

3.600

0.28

0.56

2.35

0.9

CRR4300

100

4.300

3.240

5.400

0.22

0.35

3.00

1.46

CRR0240-560 -NKL
CRR080D-1250 - NKM
CRR1950-4300 - NKO

NOTES:
1. Max VF where IF< 1.11Fl (max) is guaranteed.
2. Pulse test - steady state current may vary.
3. Pulse test - steady state impedances may vary.
4. Min VF required to insure IF

> 0.8

IF1 (min).

Silicanix

3-41

-

APPLICATIONS

Parallel Operation

The current-limiter diode is the electrical dual of the Zener diode.

CR,

~+v,z;;-

ITOTAL=ICR,+ICR2
,
1
=
+ Zd2

-v

Current-Limiter Diode V-I Characteristic

CR2

(When I,

Zd1

Series Operation
12 -11

< 12, that is

< 0.2 I,)

EQUIVALENT CIRCUIT

I,

I,
1

c,

Z.

VOLTS

POISICR1) < POALLOWED

BV (FOR SERIES DEVICES)

=BV,+ BV2

RS
1

SYMBOLS AND DEFINITIONS

Rs

A
C

Forward Current (Anode Positive)
Current at a specified Test Voltage, VF

Collector or Drain
Hi-Z Load Resistors

Constant-Current
Timing Circuits

Anode (Drain)
Cathode (Source and Gate Shorted)

POV
81
8 JC
oJA

Peak Operating Voltage
Current Temperature Coefficient
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient

ZK

Knee AC Impedance at specified VF. ZK should
be as high as possible and is specified as a minimum.
Dynamic Impedance at specified VF. Zd is specified as a minimum.

Zd

Emitter or Source Biasing
+

+

?

?

Constant-Current Supply
or Current-Limiting Element

~

e

9

Logic Circuit Pull-Up
Current Source

0

T-'-------0

3-42

+

9

Siliconix

matched dual
n-channel JFETs
designed for • • •

H

Siliconix

Performance Curves NCB-D
See Sedion 4

Differential
• Wideband
Amplifiers
• Commutators

BENEFITS
High Gain
7500 tLmho Minimum gfs
Specified Matching Characteristics

•
•

ABSOLUTE MAXIMUM RATINGS (25°C)

TO-71

..........................

See Section 6

±80V
Gate-Gate Voltage
Gate-Drain or Gate-Source Voltage .....•..•••... -40 V
Gate Current .....•.•••.•.••.•.•..•.•.....•.. 50 rnA
Device Dissipation (Each Side), T A = 25°C
(Derate 2.2 mW/oC) ..•...••..•....•.•.••.• 325mW
Total Device Dissipation, T A = 25°C
(Derate 3.3 mW/oC) •.••..•••••••.•.•.•..•. 650mW
Storage Temperature Range •••.•..••....• -65 to +200°C
Lead Temperature
(1/16" from case for 10 seconds) ........•...... 300°C

G,

~~
S,

Gz

82

S2

.4.

02
0'
06
0 7 G2
20
0,
,0

G, 30

s,
Bottom View

"

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

1

1'2
I~

14
5'
6"
1"
8

g10
'iT
i2
13

-

S
T
A
T
1
C

IGSS

Gate-Reverse Current

BVGSS
VGS(off)
VGS(I)
lOSS
rOS(on)

Gate-Source Breakdown Voltage

91.
O
V 90.
N
A Crss
M C1SS
1 NF
C
ifn

-40
-D.5

Gate-Source Cutoff Voltage

pA
nA
V

2

5

Static Drain Source ON Resistance

7500
7000

Common-Source Forward Transconductance

(Nol.')

3

Equivalent Short Circuit Input NOise Voltage

DN6664
Min
Max

pF

12
1.0
50
DN5666
Min Max

1 0.95

1 0.9S

1

Unit

-

10

20 mV

10

25

SO

10

25

50

1 0.90

Test Conditions

VOS = 15 V, VGS =0

/IV!
·C VOS =15 V, 10 =2 mA

1 -

1= 1 kHz
1= 100 MHz
1= 1kHz
1= 1 MHz
1= 10 Hz, Rg =1M
1= 10Hz

v11z

5

1 0.90

VOG=15V,lo=2mA

dB
nV

ON6666
Mm Max

I
I 150·C

IG=-l/1A,VOS=O
VOS=15V,10-lnA
VOS =0 V, IG =2 mA
VOS=15V,VGS=0
10=1mA,VGS=0

65

Spot NOise Figure

09S

n

Test Conditions

VGS' -20 V, VOS= 0

/lmho

Common-Source Output Conductance

0.95

mA

50
100
12,500

Common-Source Reverse Transfer Capacitance
Common·Source Input Capacitance

Saturation Drain Current
IOSS1
14
RaIla, (Nol.' 1and 2)
-M IOSS2
A IVGS1-VGS2 1 Differential Gate·Source
15 T
Voltage
-C
H AIVGS1-VGS2 1
Gate-5ource Voltage
16 1
Oill.r.nlial 0,,11 (Nol. 3)
N
AT
G
91.1
Transconductance RatiO
17
(No I•• 1and 2)
91.2

Unit

-3

Gate-Source Voltage
Saturation Drain Current (Note 1)

Characteristics

-

Max
-100
-200

Min

TA = 2S·C
TB =12S·C
TA =-S5·C
TB = 2S·C
1= 1kHz
NCB-O

, NOTES:

1. Pulse test required, pulse width 300 J.lS. duty cycle <: 3%.
2 Assumes smaller value tn numerator.
3. Measured at ends POints, TA and Ta

Silicanix

3-43

l1li

H

matched dual
n-channel JFETs

Siliconix

designed for...

Performance Curves
NCB-D
See Section 4

• Dual FEY

BENEFITS
• High Density
• Matched Switch Resistance
Constant rOS(on) with Signal

•
ABSOLUTE MAXIMUM RATINGS (2S0C)

TO-71
See Section 6

Gate-Gate Voltage ............................. ±80 V
Gate-Drain or Gate-Source Voltage ............... -40 V
Gate Current ................................ 50 mA
Device Dissipation (Each Side), T A = 25°C
(Derate 2.2 mW;oC) ....................... 325 mW
Total Device Dissipation, T A = 25°C
(Derate 3.3 mW;oC) : ...................... 650 mW
Storage Temperature Range ............ -65°C to +200°C
Lead Temperature
(1/16" from case for 10 seconds) ............... 300°C

G,

~~
8,

G2

S2

'2

.,

20

D,

J

o'06 D2

G, 30

01 G2

,0

02
D,

"

Bottom View

ELECTRICAL CHARACTERISTICS (2S0C unless otherwise noted)

I

Characteristic
1
~

-

IGSS
BVGSS

Gate-Sou rce Breakdown Voltage

-40

VGS(off)

Gate·Source Cutoff Voltage

-0.5

VGS(f)

Gate-Source Voltage

-Sc

lOSS

Saturation Drain Current (Note 1)

~
8

----g

D
Y
N

10
_M
A
11
T
-C
12
H

I

I\I1!!X

-100
-200

S
3
T
A
----:- T
5
I

------;-

Min

Current

Gate~Reverse

'J!'!it

pA
nA

I

Te:t Condition;
VGS=-20V.VOS=0

I
15o"C

IG = 1 I'A, VOS = 0
-3

V

2.0
5

mA

100

11

rOS(on)

Static Drain Souroe ON Resistance

Cgd

Oraon-Gate Capacitance

7

Cgs

Gare-5ource Capacitance

7

IOSSI
IOSS2

Saturation Drain Current
Ratio (Notes 1 and 2)

IVGS1-VGS21

Differential Gate-Source
Voltage

9fsl
9fs2

Transconductance Ratio
(Notes 1 and 2)

0.9

0.9

pF

VOS=15V,VGS=0
10= 1 mA,VGS=O
VGS= -10V

f= 1 MHz

VOS= 10V

1

-

20

mV

1

VOS= 15V,10= 1 nA
VOS=OV,IG=2mA

60

-

VOS=15V,VGS=0

f = 1 kHz

NCB-O

NOTES:
1. Pulse test required, pulse width 300 I'S, duty cycle .. 3%.
2. Assumes smaller value in numerator.
3. Measured at end points, T A and TB.

3-44

I

Silicanix

dual

•

PICO

ampere diodes

designed for • • •

H
Siliconix
---

BENEFITS
• Very High Off-Isolation
1 pA Max (DPAD1)
• High Isolation Between Diodes
20 Femto Amp Typical (DPAD1)
• Matched Capacitances
• Compact Packaging

Circuits
• Clipping
Diode Switching
• High
• CircuitsImpedance Protection

TO-71 (MODIFIED)
(Pins 2 and 6 Removed)
See Section 6

TO-7B (MODIFIED)
(DPADI Only)
See Section 6

ABSOLUTE MAXIMUM RATINGS (25°C)
Forward Gate Current, Each Side ................ 50mA
Total Device Dissipation @ T A = 25°C
Derate 4.0 mW;oC to 125°C................. 400 mW
Storage Temperature Range ............. -55 to +125°C
Lead Temperature
(1/16" from case for 10 seconds) '" ............300°C

it

~

c,

~,

fi

A2

C2

~'~
A1~,'

A'~A2

o

C,

A2

C,
BotlomVlew

Bottom View
(Alternate)

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
CHARACTER ISTIC

MIN

TYP

MAX

UNIT

TEST CONDITION

- 21

-1

DPADI

-2

DPAD2

3"

-5

-

~S

IR

Reverse Current

-10

5 T
-A
6 T
-I
7 C

-

2..
9

- 10

BVR

Reverse Breakdown Voltage

VF

Forward Voltage Drop

11 D
- Y CR
12 N
13

~

-45

VR

-50

DPAD50

-100

DPAD100

V
1.5
0.8
2.0
0.1

0.2

IR

DPAD1, 2, 5

~-II'A

IF~

pF

VR

pF

VR1

DPAD10. 20, 50, 100

1 mA

~

-

DPAD10
DPAD20

-35
0.8

~-20V

-20

-120

Capacitance

ICR1-CR2 1 Differential Capacitance

DPAD5
pA

DPAD1, 2, 5,10,20,50,100

-5 V, I

~

DPAD1, 2, 5

1 MHz

DPAD10, 20, 50, 100
=VR2=-5V,I~

1 MHz

DPAD1, 2,5, 10,20,50,100

T

APPLICATION
Operational Amplifier Protection. I nput Differential Voltage limited to 0.8 V
(typ) by DPADS 0 1 and O2 Common mode input voltage limited by DPADS 03
and 04 to ±15 V.

0,
03

'*' oit I:" '

t !_ . .

v

Typical sample and hold circuit with clipping. DPAD diodes reduce oflset voltages
fed capacitively from the F ET switch gate.

Silicanix

IR<'~tl

DPAD10

+15 V

04

-15V

DPAD1

I
en
f

t,

DPADl

2N4393.
CONTROL SIGNAL

C

j

2N4117A

~UT
3-45

n-channel JFETs
designed for . . .

H

Siliconix

Performance Curves NT
See Section 4

• Ultra-High Input
Impedance Amplifiers
Electrometers
pH Meters
Smoke Detectors

BENEFITS
• Low Current
IDSS < 0.15 mA (FN4117A)
• Minimum Circuit Loading
IGSS < 1 pA

TO-72

*ABSOLUTE MAXIMUM RATINGS (25°C)

See Section 6

Gate-Drain or Gate-Source Voltage (Note 1) .. _..... -40 V
Gate-Current ... _. _.. _..... _. _. _. _. , ... _. . .. 50 mA
Total Device Dissipation
(Derate 2 mWrC to 175°C) ......... _. _... , 300 mW
Storage Temperature Range. _. _. _...... _. -65 to +175°C
Lead Temperature
(1/16" from case for 10 seconds) ... _. __ .. _, . _. 255°C

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

FN4117A
Min Max

Gate Reverse Current

FN4118A
Min

Max

FN4119A
Min
Max

Unit

-;

-1

-1

pA

-2.5

-2.5

-2.5

nA

I....!...

S

IGSS

3

A

BVGSS

Gate-Source Breakdown Voltage

VGS(off)

Gate·Source Cutoff Voltage

-0.6

-1.8

-1

-3

-2

-6

lOSS

Saturation Drain Current
(Note 2)

003

0.15

0.08

0.4

0.20

1.2

70

250

80

250

100

330

Test Conditions

VGS=-20V,VOS=0

150·C

1~:Tr--------------------------r--;---;----r---r---r---r---r------------~---------1
-40
-40
-40
I~ T~~~-=~~~-=-=~~~-4---+--~--~--;_~;-__1

I'~ ~

5

6

1-,7

I~
8

D

gfs

i~a~~~~dSu~~:~~:(~:~d2)

__

Common-Source Output

C'SS

Capacitance

V

IG=-Ip.A,VOS=O

VOS=10V,lo=lnA
rnA

VOS= lOV,VGS=O

yr-------------------~--~--_+--_r--_r--;_--;___1 Jlmho

N

Ar~s _____c_o_nd_u_ct_an_c_e____________-+__-+__-1____r-__r-__+-__;-__~
M
I

Common-Source Input

3

5

10

3

3

3

I~ C~------~~--------~~-+--~---r---r--;---~~
Common-Source Reverse Transfer
1.5
1.5
1.5
9
Crss
Capacitance

pF

VOS=10V,VGS=0
f= 1 MHz

NT

...JEDEC registered data.

NOTES:
1. Due to symmetrical geometry. these units may be operated with source and drain leads interchanged.
2. This parameter is measured during a 2 ms Interval 100 ms after power IS applied. (Not a JEDEC condition.)

3-46

f ' l kHz

Silicanix

n-channel JFETs
designed for • • •

H

Siliconix

Performance Curves NCB
See Section 4
BENEFITS
Low Insertion Loss, High Accuracy in
• Test
Systems rON

Switches
• Analog
Commutators
• Choppers
• Integrator Reset Switch
•

No Offset or Error Voltages Generated
• by
Closed Switch

•
•

*ABSOLUTE MAXIMUM RATINGS (25°C)

Purely Resistive
High Isolation Resistance from
Driver
High Off-Isolation ID(off) < 100 pA
High Speed tON < 20 ns

Q

TO-18

Reverse Gate-Drain or Gate-Source Voltage ___ ..... _-40 V
Gate Current ............... _........... _.... 50 rnA
Total Device Dissipation at 25°C Case Temperature
(Derate 10 mW;oC) ..... , ____ .. _............. 1.8 W
Storage Temperature Range. _... _........ --65 to +200°C
Lead Temperature
(1/16" from case for 60 seconds) ............... 300°C

See Section 6

o~:

o

'"m
-m
'"
~

5

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

'.....!..

2

-3
-4
5

IGSS

Gate Reverse Current

8VGSS

Gate-Source Breakdown Voltage

~S
]T IDloff) Drain Cutoff Current
I---, .A
81 T VGSlfi Gate-Source Forward Voltage
Ig- 'Ic, VGSloff) Gate-Source Cutoff Voltage
Saturation Dram Current
10
IDSS
INot.1I
~

1ii
-:-

FN4392
Ma.
Mon
-100
-200
-40

-2
25

100
200
1
-5
100

Dram Source ON Voltage

04

rOSlon)

Static Dram-Source ON Resistance

rds(on)

Dram-Source ON Resistance

~ D
Y
N
~
20
"'21 s
22 ' W
23

CISS

Common-Source Input Capacitance

60
60
16

C rss

Common-Source Reverse Transfer
Capdcltance

~

-

Umt

-40

1
-3

-05
5

tdlon)
t,
tdloff)
tf

Turn-ON Delay Time

Rise Time
Turn-OFF Delay Time

Fall Time

VGS =-20 V. VDS =0

VDS =20 V VGS =-5 V
150·C

IG =1mA, VDS =0
VOS =20 V. 10 =1 nA
mA VOS =20 V, VGS =0
110 - 3 mA
V VGS=O liD =6 mA
IID-12mA
n
VGS O,llo=lmA
n VGS O,IID 0
f =1kHz
VDS =20 V. VGS =0
I VGS =- 5 V f = 1 MHz
pF
VGS - - 7V
VOS =0
VGS--12V
VOD - 10 V, VGS(on) - 0
VGS(off)
1010ni
ns FN4392
6
-7
FN4393
3
-5

100
100
16
5

5
15
5
50
30

yoo
5111

NOTE'
1 Pulse test reqUired, pulse width = 300 jJS, duty cycle ~ 3%

1000pF
PULSE 0-1

o~--r"
VIN
SCOPE

5112

-=-

Silicanix

150·C

IG=-lpA,VDS=O

V

60

15
5
35
20

Test Conditions

pA
nA
V
pA
nA
pA
nA

04
VDSlon)

.g
18

FN4393
Ma.
-100
-200
100
200

~
13
14
15

-

Mon

l'

5H!

-=-

IEII
RL

16KU
32KH
NCB

1000pF
t---VOUT

RL=(~)-51n

D

s1
-=-

O(onl

ONPUTPULSE

RISE TIME< 05ns
FALL TIME < 0 5 ns
PULSE DUTY CYCLE 1%

SAMPLING SCOPE

RISE TIME 04 os
INPUT RESISTANCE 50 n

3-47

..
.. •
.,.. •
.-..

., n-channel JFETs
-0 designed for • • •
0
., Analog Switches

H

0

1ft

0

Siliconix

Performance Curves NVA
See Section 4
BENEFITS
• Very Low Insertion Loss
rOS{on) < 3 n (J105)
• No Offset or Error Voltages Generated
by Closed Switch
Purely Resistive
High Isolation Resistance from
Driver

Choppers

• Commutators

TO-92
See Section 6

ABSOLUTE MAXIMUM RATINGS (25°C)

Plastic

.~:

Gate-Drain or Gate-Source Voltage ............... - 25 V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50 mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mWfC) ...................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

o

G

GD
o

o

0

o

0

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

Jl05

Jl06

"1111 Till IVidA

1

"25
T
'3
_A

-7

.J!

Gate Reverse Current (Note 1)
Gate-Source Cutoff Voltage

-4.5

BVGSS

Gate-5ource Breakdown Voltage

-25

Drain Saturation Current (Note 2)

500

~

-10

-3 nA

-3
-2

-6 -0.5

25

-25

200

-4.5

100

V
mA

IO(off)

Drain CU10ff Current (No1e 11

3

3

3 nA

rOSlon)

Dram Source ON ReSistance

3

6

8

CdQ(off)

Dram Gate OFF Capacitance

35

35

35

Cooloffl

Source Gate OFF Capacitance

35

35

35

160

160

160

9 0 Cdglonl
V
+
N
A Cso(onl

-1211

Mill iy.., MdA Mill iyl' ividX

-3

IGSS
VGS(offl

4 T lOSS

51
5 C

Jl07

1--'-":";"r--+-~'::"'-+-'~-T---1Uni1

ON Capacitance

Fall Time

NOTES:
1. Approximately doubles for every 10·C increase
2. Pulse 1est duration = 300 I'S; duty cycle ~ 3%.

3-48

VOS=5V.IO=I/lA
VOS= 15V. VGS=OV
VOS=5V.VGS=-lOV

n
VOS=OV,VGS=-10V

Turn On Delay Time
15
15
15
1dlon
I
Rise Time
20
20
20
1r
C ~--------~----------------+--+~+-~--;-~---r~r--r~ns
Turn Off Delay Time
15
15
15
1dloff)

1f

VOS = 0 V, VGS = -15 V

f= 1 MHz

pF

Dram Gate plus Source Gate

M

13

Test Conditions

20

20

20

VOS=VGS=OV
SWitching Time Test Conditions

Jl05
1.5V
VOO
VGS(offl -12V
50n
RL

Jl06
15V
-7V
50n

Jl07
15V
-5V
50n

NVA
In

TA.

Siliconix

n-channel JFETs
designed for • • •

Siliconix

Performance Curves NIP
See Sedion 4

•
• Choppers
• Commutators
• Low Noise Audio Amplifiers
Analog Switches

-....
....

H

BENEFITS
Low Cost
•. Automated Insertion Package
Low Insertion, Loss
rDS{on) < 8 n (Jl08)
No Offset or Error Voltages Generated
by Closed Switch
Purely Resistive
High Isolation Resistance from
Driver
Fast Switching
td{on) + tr = 5 ns Typical
Low Noise
en = 6 nV/yHz at 10 Hz, Typ (J110)

•
•

•
•
•

i

o

-0

....

....
o

-g

Plastic

ABSOLUTE MAXIMUM RATINGS (25°C)
Gate-Drain or Gate-Source Voltage .............. , -25V
Gate Current ..................... ' ........ 50mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mWrC) ................... , .. 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ............. , .-55 to 150°C
Lead Temperature Range
(1 /16" from case for 10 seconds) . , ............ 30QoC

TO·92
See Section 6

,~:

G
GD
s

D

S

0

D

0

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Jl0B

Characteristic
1

12'5
1'3:

'GSS

I~~

7
IS

1-

Gate-Source Breakdown Voltage

lOSS

Dram Saturation Current INote 2)

' 0 (011)

0

Min

Typ

-6

Max
-3

-25

-25

BO

40

10

Dram-Gate Plus Source-

UOit

nA

-4

-05

V

3

3
25

15

15

15

15

15

15

VOS=5V,10=1~A
~A

rnA

V OS -15V,V GS -OV

nA

V OS =5V,V GS =-10V

!l

VOS <; 0 1 V, VGS - OV
vOS = OV, VGS = -10V

pF
85

Gate ON Capacitance

85

85

Turn ON Delav Time

4

4

4

AlseTime

1

I

1

Turn OFF Delay Time
Fall Time

-

Test Conditions
V OS =OV,V GS =-15V

V OS -OV,I G --l

B

Cdg(on!

If

Max
-3

-2

3

Source-Gate OFF Capacitance

+

Typ

11

Csg(off!

N C,g(on!
I-A
10 M Id(on!
Iii I I,
I-c
12
'd(offi

M,n

-25

Dram Cutoff Current (Note 1)

Drain-Source ON Reslstane

Jll0

Jl09
Max

-10

-3

Cdg(off! Dram-Gate OFF Capacitance

9 y

113

Gate Reverse Current (Note 1)

BV GSS

'OS(on!

Typ

-3'

V OS(of1) Gate-Source Cutoff Voltage

I-T

17

Min

n,

6

6

6

30

30

30

f= 1 MHz
VOS = VGS = 0

SWltchmg Time Test Conditions
Jl08
Jl09
Jl10
l,5V
1.5 V
15V
VOO
VGS(offi -12V
150n
RL

-7V

-5V

150n

150n

NIP

NOTES:
I, ApprOXimately doubles for every 10°C Increase In TA-

2 Pulse Test duration 300 jlS, duty cycle <; 3%

Silicanix

3-49

n-channel FETs
designed for • • •

H

Siliconix

Performance Curves NCB
See Section 4

• Analog Switches
• Choppers
• Commutators

BENEFITS
Low Cost
• Automated
Package
• Low InsertionI nsertion
Loss

•

rDS(on)

< 30 n

(J 111)

No Offset or Error Voltages Generated
• by
Closed Switch

...Z••

•
•

....
~

III

-

Purely Resistive
High Isolation Resistance from
Driver
Fast Switching
~(on) + tr = 13 ns Typical
Short Sample and Hold Aperture Time
Cgd{off) < 5 pF
Cgs(off) < 5 pF

:::)

(J

...Z
III

:::)

o

:e
III

~

Plastic

ABSOLUTE MAXIMUM RATINGS (25°C)
TO·92
See Section 6

Gate-Drain or Gate-Source Voltage ............... -35V
Gate Current .•.... _.......•...........•.... 50 mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mWtC) . ..................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

G
GO

.~:

0

~

=»
en

S

s

C

o

c

Bottom View

ELECTRiCAL CHARACTERISTICS (25"C unless otherwise noted)
J112

J111

J113

Characteristic

1

--;-

-

3

s
T
A

T

....!.I

...:..C

Test Conditions

UNIT
M,n

Tvo Ma.

M,n

Tvo

-1

Ma.

M,n

-1

IGSS

VGSloff)

Gate Source Cutoff Voltage

-3

BVGSS

Gate Source Breakdown Voltage

35

35

-35

lOSS

Dram Saturation Current INote 2)

20

5

2

-10

Tvo Ma.

-1

Gate Reverse Current (Note l'

-1

nA

-3

-5

VOS '" 0 V. VGS" -15 V
VOS=5V,IO=1iJ.A

V
VOS = 0 V, IG = -1 iJ.A
rnA

VOS=15V.VGS=OV

IDloU)

Dram Cutoff Current (Note 1)

-1

-1

-1

nA

VOS = 5 V. VGS = -10 V

6

'OSlon)

Dram Source ON Resistance

30

50

100

Cdg(offl

Dram Gate OFF Capacitance

5

5

5

"

Vos = 0 1 V. VGS = OV

1

B
-0

Csgloffl

Source Gate OFF Capacitance

5

5

5

V

Cdglon)

28

28

28

Csgtonl

Dram Gate Plus Source Gate
ON Capacitance

tdlan)

Turn On Delay Time

1

1

7

t,

Rise TIme

6

6

6

td(aff)

Turn Off Delay Time

20

20

20

tf

Fall Time

15

15

15

-

9

-;;;:
_M

11

I

-c

..E.
13

VOS"'OV,VGS=-10V

3-50

VDS=VGS=O

ns

NOTES:
1. Approximately doubles for every 10° C increase in T A.
2. Pulse Test duration 300 JlS; duty cycle .. 3%.

f= 1 MHz

OF

Swltchmg Time Test Conditions
J111
J112
lOV
10V
VOD
-1 V
-12 V
VGS(offl
800
Sl
1,600n
RL

NCB

Siliconix

J113
10V

-5V
3,2oon

n-channel JFETs
designed for • • •

Siliconix
Performance Curves NCB
See Section 4

Switches
• Analog
Choppers
• Commutators
•

BENEFITS
• Low Insertion Loss
rOS(on) < 30 n (J111A)
• High Off-Isolation
10(off) < 200 pA
• No Error or Offset Voltages Generated
by Closed Switch
Purely Resistive

ABSOLUTE MAXIMUM RATINGS (25°C)

......
...
...c.....
~
c..
......

c..

H

~

~

TO·92
See Section 6

Gate-Drain or Gate-Source Voltage ............... -40 V
Gate Current ................................ 50 mA
Drain Current .............................. 400 mA
Total Device Dissipation
(25°C Free Air Temperature) ................ 350 mW
Power Derating ............................... 3.27 mW/"C
Storage Temperature Range ................ -55 to +150°C
Operating Temperatufe .................... -55 to +135°C

"~:

INSULATED CASE
•

INSENSITIVE TO LIGHT

GO

Lead Temperature
(1/16" from case for 10 seconds) ............... 300°C

s

D

o

D

Bottom View

0

s

G

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

1

-; ~
- A
..2

IGSS

Gate Reverse Current (Note 1)

VGS(off)

Gate-Source Cutoff Voltage

BVGSS

Gate·Source Breakdown Voltage

4 T lOSS
I
C I o (of!)
6
rOS(on)

Saturation Drain Current (Note 2)

7

Cdg(off)

~

"'5

-

9

JlllA
Min
Max

J112A
Min Max

-200

-5

-10

J113A
Min Max

-200
-2

-7

-200
-1

-40

-40

-40

30

15

8

Drain Cutoff Current (Note 1)

Unit
pA

-5

Test Conditions

VOS = 0, VGS =-15 V
VOS = 5 V. 10 = 1 /lA

V

VOS = O. IG = -1 /lA

mA

VOS=15V.VGS=0

200

200

200

pA

VOS=5V.VGS=-10V

30

50

80

n

VOS"'O.l V. VGS=O

Drain Gate OFF Capacitance

5

5

5

0
y Csg(off)

Source·Gate OFF CapacItance

5

5

5

N Cdg(on)

Dram Gate Plus Source Gate
ON Capacitance

28

28

28

+
Csg(on)

Drain Source ON Resistance

VOS = O. VGS = -10 V
pF

f= 1 MHz
VOS = VGS = 0

NCB

NOTES:
1. Approximately doubles for every 10°C increase m TA.
2. Pulse test duration = 300 /lS; duty cycle .. 3%.

Siliconix

3-51

-

- p-channel JFETs

.....
.........
..
., !:::...

.. •
...,:!:- •
...........'"- •
.,'"
-0

.,~~an...

H

Siliconix

Performance Curves
PSA/PSB/PSC
See Section 4

designed for • • •
Analog Switches

BENEFITS

• Low Cost

Iftl--.

..... ...

• Simplifies Series-Shunt Switching
when Combined with J113, its N-Channel Complement
Low Insertion Loss
rOS(on) < 85 n (J174)
No Offset or Error Voltages Generated
by Closed Switch
Purely Resistive
High Isolation Resistance from Driver
Short Sample and Hold Aperture Time
Csg(off) < 5.5 pF
Cdg(off) < 5.5 pF
Fast Switching
td(on) + tr =7 ns Typical

Choppers
Commutators

•
•

II

>
-

•

::;)

o

...Z
III

::;)

o

:e
III

u

:Ea=

::;)

-'"

•

ABSOLUTE MAXIMUM RATINGS (25°C)
Gate-Drain or Gate-Source Voltage (Note 1) ....•.... 30V
Gate Current ..•.......................•...• 50 rnA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mW/C) ...................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

Plastic

TO·92
Sea Section 6

o~:

sD

G

D

a
a

Bottom View
0

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristics
1
2

VGs(off)

12

i

6

3

1

4

I

08

3-52

VOs = 0, VGs = 20 V
VOs=-15V,lo=-10nA

30
-135 -7

-70

-20

mA

VOs= -15V.VGs=0

-1

-1

-1

-1

nA

VOs=-15V,VGs=10V

85

125

250

300

rl

VGs = O. VOs = -0,1 V

Drain-Gate OFF

30

30

-2

-35 -15

VOS=O,IG=I~A

30

Capacitance

5.5

55

5.5

55

Csg(off)

Source-Gate OFF
Capacitance

55

55

55

5.5

Drain-Gate Plus SourceGate ON Capacitance

32

32

32

32

VOs = O. VGs = 10 V
f= 1 MHz

pF

TUrn On Delay Time

2

5

15

20

t,

Rise Time

5

10

20

25

td(oltl

Turn Off Delay Time

5

10

15

20

tf

Fall Time

10

20

20

VOS = VGs= 0

ns

NOTES:
1. Geometry

Test Conditions

V

113

nA

225

Cdg(offl

0
Cdg(onl
9 V
+
N Csg(on)
I-A
10 M td(on)
I:: C

10

Resistance

1-

1-,

5

Orain-Source ON

18

J177

1

1

Dram Cutoff Current
(Note 2)

'Os(on)

J176

Saturation Drain Current -20
(Note 3)

Voltage

l7

Voltage

Gate-Source Breakdown

3 T BVGSS
I_A
4 T 1055
I
I- c
5
10(0111
6

Gate-Source Cutoff

J175

Unit

Gate Reverse Current
iNuu:ii2j

IGss

11_ s

J174

Min Typ Ma. Min Typ Ma. Min Typ Ma. Min Typ Ma.

IS

symmetrical. Units may be operated With source and drain leads Interchanged.

Siliconix

25

SWitching Time Test Conditions
J175
J174
J176 JI77
-10V
-6V
-6 V
-6V
VOO
3V
BV
6V
VGs(off) 12V
560n 1.2Krl 5.6Krl 10Krl
RL
OV
OV
OV
OV
VGs(onl

2. Approximately doubles for every 100 e Increase," T A.
3. Pulse test duration := 300 tJ.s; duty cycle OS;;; 3%.

PSA/PSBI

PSC

n-channel JFETs
designed for • • •

H

Siliconix

Performance Curves NPA
See Section 4

• General Purpose Amplifiers

BENEFITS

• High Input Impedance
IG = 10 pA Typical

• Good for Low Power Supply
Operation
VGS(off)

< 1.5V (J201)

rn ...

g~

CO
-~

:<

Plastic

ABSOLUTE MAXIMUM RATINGS (25°C)

II

Gate-Drain or Gate-Source Voltage (Note 1) ....... -40 V
Gate Current ............................... 50mA
Total Device Dissipation at 25a C Ambient
(Derate 3.27 mWrC) ...................... 360 mW
Operating Temperature Range ............. -55 to 135a C
Storage Temperature Range ............... -55 to 150a C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300a C

'4:

en
en

...

~

o

.

G
GD
D

s

s

c

D

C

~

o
w

..

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
J202

J201
CharacterIStic

1

IGSS

-S
2 T

Moo

Gdle Reverse Current
Gate Source Cutoff
Voltage

-03

3 T

BVOSS

Gate Source Breakdown
Voltage

-40

4 C

IDSS

Saturation Dram Current
INote 3)

02

5

'G

Gate Current (Note 2)

-,
-

6
_ 0 'Is
y

7 N 'as

-A

-,

9 C

10

Transconductance (Note 3)
Common Source Output

Conductance

Mon

hp

-15

J203

Max

Mon

Typ

-100
-40

-OB

Max

M,n

J204
Typ

-100

-20

-100

Test Conditions

Unit

Ma.

-100

pA

-20

-03

VOS - D. VGS - -20 V
VOS - 20 V. 10 '" 10 nA

V
-40
10

09

45

1,000

500

40

-10

-10

-25

-40
20

02

-10

-10
1,500

VOS" D. IG '" -1 pA

12

500

3

10

VOsc20V,VOS'0

pA

VOG'" 20 V. 10 '" IOSSlmm)

1500
f:: 1 kHz

25

VDS
4

Crss

Common·Source Reverse
Transfer Capacitance

I

1

I

1

en

Equivalent Short Circuit
Input NOIse Voltage

5

5

5

10

4

4

~

20V, VGS:

a

Siliconix

-

4

pF

NOTES:
1 Geometry IS symmetncal. Units may be operated With source and dram leads Interchanged
2 ApproXimately doubles for every 10°C Increase In T A
3 Pulse test duration = 2 ms

II1II

mA

,umho

1

35

Common Source Input
Capacitance

8 M C1SS

-

Common Source Forward

Max
-100

(Note 2)

VGS/offJ

-A

TVp

nV

ff,

f : 1 MHz

VOS

~

10 V, VGS = 0

f: 1 kHz

NPA

3-53

n-channel JFETs
designed for • • •

...,
•
...,
~

H

Siliconix

Performance Curves NZF
See Section 4

General Purpose Amplifiers

o

BENEFITS

• High!Its Gain
= 7000 Jlmho Minimum

~

(J211,J212)
Impedance
• HighIGSSInput
=100 pA Maximum
Ciss = 5 pF Typical

TO-92
See Section 6

ABSOLUTE MAXIMUM RATINGS (25°C)

Plastic

..............
...............................

.~:

Gate-Drain or Gate-Source Voltage
-25 V
Gate Current
10mA
Total Device Dissipation at 25° C Ambient
(Derate 3.27 mWtC) .........•............ 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

GD
s
o

0
0

0

s

G

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
J210

Characteristic

IGSS

Min

VGSloff) Gate-Source Cutoff Voltage
Gate-Source Breakdown Voltage
BVGSS
lOSS

Saturation Dram Current (Note 2

5C

lG

Gate Current (Note 1)

6

91s

Common-Source Forward
Transconductance (Note 2)

7

Y gas

-

0

-N
8 A C,ss
-M
9 I erss

_C
10

"n

J211
Max

Typ

MIn

-100

Gate Reverse Current (Note 1)

1 S
2T
A
-T
4 I

'3

Typ

-1

-3

-25

J212
Max

15

-2.5

-45
20

-6

-4

40

15
-10

Unit
pA
V

Test Conditions
VOS=O,VGS=-15V
VOS= 15V,IO= 1 nA
VOS = 0, IG = -1 IlA

rnA

VOS = 15 V, VGS = 0

pA

VOG=lOV,lo=lrnA

12,000

12,000 7,000

1= 1 kHz

~mho

150

Conductance
Common-Source Input

200

200

Capacitance

4

4

4

Common-Source Reverse
Transfer Capacitance

1

1

1

10

10

10

VOS: 15 V, VGS = 0
pF

EqUivalent Short-Circuit Input

NOise Voltage

Ill!

!'HZ

1= 1 MHz

I--1= 1 kHz

NZF

NOTES:
In

TA.

2. Pulse test duratIon:;:: 2 ms.

3-54

-100

-10
12,000 6.000

Common-Source Output

1. ApprOXimately doubles for every lOGe mcrease

Max

-25

7

-10
4,000

Typ

-100
-25

2

Min

Siliconix

n-channel JFETs
designed for • • •

...

~

H
Siliconix

Performance Curves NPA
See Section 4

W

o

...

~

...
W

and Sub-Audio
• Audio
Amplifiers

BENEFITS
Low Noise
• Ultra
en = 8 nV/v'Hz Typical at 10 Hz
en = 2 nV1v'Hz Typical at 1 kHz

TO·92
See Section 6
Plastic

ABSOLUTE MAXIMUM RATINGS (25°C)

"~:

Gate-Drain or Gate-Source Voltage (Note 1) ........ -40V
Gate Current ............................... 50 rnA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mW/"C) ...................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ........ , ...... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) , ... , ......... 300°C

G
GO
0

s

S

0

o

0

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic
1
I-

IGSS

s

15

IG

6
91s
1-0
7 y 90S
I_N
8 A CISS
I_M
9 I C rss
I_ C
10
en
111

Typ

Gate Reverse Current

Gate-Source Breakdown
Voltage
Saturation Drain
Current (Note 3)

Common-Source Output
Conductance
Common-Source Input

Capacitance
Common-Source Reverse

J232

Typ

Min

-3

-05
-40

Max

3

-250
-5

-15

Max
-250

Umt
pA

-6

-3'

6

3,500 1,500

VOS = 0, VGS = -30 V
VOS=20V,IO= lilA
VOS = O,IG = -lilA

5

-2

Test Conditions

V

-40

2

-2
1,000

Typ

Min

-40

0.7

Gate Current (Note 2)
Common-Source Forward
Transconductance (Note 3)

J231
Max
-250

(Note 2)

Gate-Source Cutoff
VGS(off) Voltage

2 T
I-A
3 T BVGSS
I-I
4 C lOSS

J23D

Min

10

-2
4,000 2,500

VOS=20V,VGS-O

pA

VOG = 10 V, 10 = 0.5 rnA

5,000
1= 1 kHz

Ilrnho
1.5

3

6

4

4

4

VOS=20V,VGS=0
pF

Transfer Capacitance

1

EqUivalent Short Circuit

8

Input Noise Voltage

2

1
30

8

IEII

rnA

1= 1 MHz

1

30

2

NOTES:
1. Geometry is symmetrical. Unit may be operated with source and drain leads interchanged.
2. Approximately doubles for every 10°C Increase in TA.
3. Pulse test duration = 2 ms.

Siliconix

8
2

30

.!!Y

tIHz

VOS = 10V, VGS =0

Hz
-ff == 110kHz

NPA

3-55

-----

p-channel JFETs
designed for • • •

H

Siliconix

Performance Curves
PSA/PSB/PSC
See Sedion 4

• General Purpose Amplifiers

BENEFITS
• Low Cost
• Automatic Insertion Package
• High Gain Amplifiers
9fs = 14,000 Mmho Typical (J271)
• Low Noise
en = 6 nVlJHi at 1 kHz Typical

...Z••
...

1M

-o~

:)

...Z
i

1M

::)

1M

~

TO·92
See Secllon 6

ABSOLUTE MAXIMUM RATINGS (25°C)

Plastic

Gate·Dratn or Gate Source Voltage (Note 1) ....•.... 30 V
Gate Current ..•........................... -50 rnA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mW/"C) ...................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

.~:

~

::)

'"

G

s

sD
0

G

C

o

C

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unleSs otherwise noted)
J270
Characteristic
1

'2
-3'
4

5"

S
T
A
T
I
C

6

7
8
9
-

IGSS

Gate Reve ..e Current (Note 2)

VGS(off)

Gate-Source Cutoff Voltage

0.5

BVGSS

Gate-Source Breakdown Voltage

30

lOSS

Saturation Drain Current (Note 3)

·2

IG

Gate Current (Note 2)

gfs

Common·Source Forward
Transconductance (Note 3)

90s

Common·Source Output
Conductance

0

y

Min

N
A Ciss
M
I Crss
C
10
en

Common..source Input
Capacitance

Typ

J271
Max

Min

Typ

200
20

200
1.5

6,000

60
15,000

Test Conditions
VOS=0,VGS=20V
VOS = ·15 V, 10 = ·1 nA
VOS=O,IG=lpA

-50

·6

15

pA
V

30
-15

Unit

4.5

8,000

mA

VOS=-15V, VGS=O

pA

VOG = -15 V, 10 = 10SS(min)

18,000
pmho

200

f = 1 kit.!

500
VOS = -15 V, VGS = 0

32

.

32

Common-Source Reverse
Transfer Capacitance

4

4

EqUivalent Short·Circuit
Input Noise Voltage

6

6

NOTES:
1. Geometry is symmetrical. Units may be operated with source and drain leads interchanged.
2. ApproxImately doubles for every 10°C increase In TA.
3. Pulse test duration = 2 ms.

3-56

Max

Silicanix

pF

...JJY....

11HZ

f= 1 MHz

VOS=-10V, 10= 10SS(min) f= 1 kHz

PSA/PSB/PSC

n-channel JFETs
designed for • • •

H

Siliconix
-----

Performance Curves NZF
See Section 4

VHF/UHF Amplifiers
• Oscillators
• Mixers
•

BENEFITS
•

•
•

High Power Gain
20-23 dB Typical at 100 MHz,
Common-Source
17_5-20_5 dB Typical at 100 MHz,
Common-Gate
Low Noise Figure
1_3 dB Typical at 100 MHz
High Dynamic Range
Greater than 100 dB
TO-92

Sea Section 6
ABSOLUTE MAXIMUM RATINGS (25°C)

Plastic

.~:

Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . -25 V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mW/"C). _ . . . . . . . . . . _ .. _ .. _ ... 360 mW
Operating Temperature Range ....... _ .. _ .. -55 to 135°C
Storage Temperatu re Range_ ... __ ... _ . _ . _ . -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .. _ . . . . . . . . . . . 300°C

GO
s

0

D

0

Bottom View

D

s

G

ELECTRICAL CHARACTERISTICS (25°C unless otherwise specified)
Characteristic

--.!.

-2

S

T

Max

Gate Reverse Current

IGSS

nA

-0.1

IlA

Gate·Source Breakdown Voltage

-25

4

VGS(off)

Gate·Source Cutoff Voltage (Note 1)

-1.5

-7.0

IDSS

Saturation Dram Current (Note 1, 2)

4

45

I

:-c
5

6

0
y

9fs

Common·Source Forward Transconductance
(Note 1)

7

N

gas

Common·Source Output Conductance

200

Common-Source Reverse Transfer
Capacitance

1.7

Common-Source Input Capacitance

5.5

A

B M Crss
_I

9 c Ciss

Characteristic
IDSS
(Note 2)

Saturation Drain
Current

VGS{off)

Gate Source
Cutoff Voltage

J300A
Min Max
4
-1.5

9
-3.0

J300B
Min Max
7
-2.0

Test Conditions

Unit

-0.5

3 A BVGSS
T

!-

-

Min

VGS=-15V, VDS=O

TA= 125°C

IG = -1IlA, VDS = 0

V

VDS=10V,ID=1nA

rnA

VDS= 10V, VGS=O

4500 9000

J300C
Min Max

15

12

25

-4.0

-2.5

-5.0

NOTES:
1. lOSS and VGSS(offl are selected into 5 range. and labeled according to above table.
2. Pulse test PW .; 300 JlS, duty cycle'; 3%.

Siliconix

Ilmho

VDS= 10V, ID = 5 rnA, f= 1 kHz

pF

VDG= 10V, ID = 5 rnA, f= 1 MHz

J300D
Max

~Min

21

45

-3.5

-7.0

Unit

Test Conditions

rnA

VDS=10V
VGS=OV

V

VDS=10V
ID=1nA

NZF

3-57

-

n-channel JFETs
designed for • • •

H

Siliconix

Performance Curves NH
See Section 4

Amplifiers
• VHF/UHF
Oscillators
• Mixers
•

BENEFITS
for Operation at 100
• Characterized
and 400 MHz
• LowNFNoise
= 1.7 dB Typical at 100 MHz
TO-92
See Section 6 •
Plastic

.~:

ABSOLUTE MAXIMUM RATINGS (25°C)
Gate-Drain or Gate-Source Voltage ............... -30 V
Gate Current ............................... lOrnA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mwtC). ..................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

GO
s

D

D

D

D

BottomViaw

s

G

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic
1 S

12" T
13~
I-I
4 C
5

1-

6 0
V
I- N

-

7 A
M
8 I
C

9

IGSS

Gate Reverse CUrrent (Note 1)

VGS(off)

Gate Source Cutoff Voltage

BVGSS

Gate Source Breakdown Voltage

lOSS

Saturation Drain Current INote 2)

9ts

Transconductance (Note 21

90S

Common-Source Output
Transconductance

C ISS
Crss

-14
-15

H
I

liS

119
120
I-

I~

15

4,500

Capacitance
Common-Source Reverse
Transfer Capacitance

-100
-05

-3

-30

5

Cc.,.,mo!"-Scurce Input

Max

Untt
pA
V

Test Conditions
VOS = 0, VGS = -20 V
VOS=15V,IO=1 nA
VOS = 0, IG = -1 pA

1

8

mA

VOS= 15V,VGS=0

7,500 3,000
t = 1 kHz

pmho

50

50
VOS= 15V,VGS=0

3,5

3.5

0.85

0.85

pF

f= 1 MHz

90ss

boss

Common-Source Output
Susceptance

91ss

Common-Source Input
Conductance

b,ss

Common-Source Input
Susceptance

7,500

Common-Source Power

20

Gam

11

NOise Figure

1.7

VOS=i5V,lo=5mA,

f = 100 MHz

(Single SIdeband)

3.8

RG = 1 Kn

f = 400 MHz

Gps

22

123'

-6

-30

Q

U
E
N
C
V

Typ

-100
-2

i- F

16
!- R
17 E

Min

Common-Source Output
Conductance

G
H

J305
Max

9f,

Coss

12

13

Typ

Common-Source Output
Capacitance
Common-Source Forward
Transconductance

10

:iI

Common-Source Forward

J304
Mon

NF

10

1.0
t= 100 MHz

3,000
4,200

f = 400 MHz

60

60

f= 100 MHz

800

f= 100 MHz

f= 400 MHz

80
800

pmho

3,600
80

VOS = 15 V, VGS = a

f= 400 MHz

800
2,000

f= 400 MHz
f= 100 MHz

80

f= 100 MHz

2,000

f = 400 MHz
f= 100 MHz
VOS=15V,lo=5mA

f= 400 MHz

dB

NOTES:
NH

1. ApprOXimately doubles for every 10°C Increase 10 TA.
2. Pulse test duration = 2 ms.

3-58

Silicanix

-------

n-channel JFETs
designed for • • •

•
•
•

H

Siliconix

Performance Curves NZB
See Section 4
BENEFITS
Industry Standard Part
In Low Cost Plastic Package
High Power Gain
11 dB Typical at 450 MHz
Common-Gate
Low Noise
2.7 dB Typical at 450 MHz
Wide Dynamic Range
Greater than 100 dB
Easily Matches to 75 n Input

VHF/UHF Amplifiers
Oscillators
Mixers

AB~OLUTE

•

•
•
•
•

MAXIMUM RATINGS (25°C)

Drain-Gate Voltage ............................ 25 V
Source-Gate Voltage. _......................... 25 V
Forward Gate Current ........................ 10mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mW/"C) ...................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

Plastic

TO-92

See Section 6

,~:

lD
S

D

o

D

Bottom View
S

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

1

BVGSS

112 SlOSS
T
1-= A
4 T VGS(off)

1-'
5

e

lOSS

16

VGS(f)

Gate-Source Breakdown
Voltage

Of.

18

go.

1-

D

9

~

Gate-Source Cutoff
Voltage

Saturation Dram
Current (Note 11

1-

A
10 M gog

1- ,
11 C Cgd

1eg•

12

113

'n

ward Transconductance

Common-Gate Output

VGS =-15 V.
VOS=O

-10

.A

-10

-40

-20

-65

V

12

60

12

30

24

60

rnA

10

V

10
B,OOO

17.000

10
10,000

8.000

17.000

250

250

250

13,000

12,000

150

100

150
25

18

25

50

43

50

Equivalent Short-CIrcuit
Input NOise Voltage

Transconductance

Common-Source Output
Conductance

Common·Gate Power
Gam at NOise Match

19

NF

NOise Figure

20

Gpg

21

NF

Common-Gate Power

Gam at NOise Match
NOise Figure

pF

10

10

10

12

12

12

14

14

14

04

04

04

VOS = 0, 10 = 1 rnA

015

015

015

nV

v'H.

10 = 10mA

VOS

=

D,

VGS=-10V

VOS"10V.
lo=10mA

f"1 kHz

f= 1 MHz

f"100Hz

mmho

16

16

16

15

15

15

11

11

11

27

27

27

VOS"'10V.
IO"'10mA

f-105MHz

dB

f "450 MHz

NOTE.

NZB

1 Pulse test PW 300 1'5, duty cycle" 3%

Siliconix

--

Vos = 10 V. VGS = a

VOS" 10 V.
/-Imhos

13,000

18

Common-Source Forward

T '" +125°C

Ves:; 10V,ID '" 1 nA

w
o

17,000

43

G pg

-

-10

nA

-65

~

IG =-1/JA. VOS=O

-10

25

Common-Source Input
Conductance

~

-10

-10

w

o

Test Condltlonl

Unit

V

50

RelY.sl

18

M..

18

Common-Gate Input
Conductance

17 F Re(yO$)

TVp

-25

43

Re(Ylg)

-R

Mon

Gate-Source
Capacitance

15

~

M..

Gate-Dram
Capacitance

Re(yfs)

18

J310

-10

Output Conductance

Conductance

Mon

-10

Common-Source

Transconductance

M..

JOOS
TVp

-25

Voltage

14

-

TVp

-25

Gate-Source Forward

Common-Gate Forward

9ig

Mon

Gate Reverse Current

Common-Source For-

7

J308

G

0

3-59

-

H
n-channel JFETs
current regulator diodes
Performance Curves NCL
designed for. • •
See Section 4

Siliconix

•
•
•
•

o

BENEFITS

Current Regulation
Current Limiting
Biasing
Linear Ramp and Staircase
Generator

• Low Cost
• Simple Two Lead Current Source
• Simplifies Floating Current Sources
No Power Supplies Required
• Good Operating Current Tolerance
±20%
TO-92 (MODIFIED)
See Section 8

1ft

-t

.

ANODE

ABSOLUTE MAXIMUM RATINGS (25°C)

o

~

Peak Operating Voltage .......................... 50 V
Forward Current ............................. 20 mA
Reverse Current.............................. 50 mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mW;oC) ...................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ............... -55 to 150°C
Lead Temperature Range
(1 /16" from case for 10 seconds) .............. 300°C

o

1ft

-t

Plastic

-

CATHODE

CO

A

c

C

A

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
J500

J501

J502

J503

J504

J505

Min

0.192

0.264

0.344

0.448

0.600

0.800

Nominal

0.240

0.330

0.430

0.560

0.750

1.000

Max

0.288

0.396

0.516

0.672

0.900

1.200

Characteristic

..2...
2

S
T
A
T
4
I
,- C
5

-

IFI

Forward Current (Note 1)

3

-

16
7

1-

I~
9

D

V
N

POV

Peak Operating Voltage
(Notes 1 and 2)

Min

50

50

50

50

50

50

Max

1.2

13

15

1.7

1.9

2.1

Typ

08

0.9

1.1

1.2

1.4

1.5

VL

LImIting Voltage (Note 3)
Small·Signal DynamIc
Impedance (Note 1l

Min

4.0

22

15

12

0.8

05

ZFI

Typ

8.0

6.0

4.4

3.4

2.5

1.9

CF

Anode·Cathode CapacItance

Typ

2

2

2

2

2

2

Unit

mA

VF = 25 V

IF = 1.1 IFI (Max)
V
IF = 0.9 IFI (Min)

Mn

V F = 25 V. f = 1 kHz

pF

VF=25V.f=1 MHt
NCL

NOTES:
1. Pulse test duration = 2 ms.
2. MaxImum VF where IF < 1.1 IFI (Maxl is guaranteed
3. M,nomum VF required to Insure IF > 0.9 IFI(Min)·

Current· Limiter Diode
V·I Characteristic
I.

IF,
VR

I
VL

I.,
3-60

Test Conditions

Siliconix

pov

V.

~~---

n-channel JFETs
current regulator diodes
Performance Curves NCL
designed for • • •
See Section 4

Siliconix

---~~-

•
•
•
•

...
o
...
UI

ANODE

Plastic

~

o

CO

...
~
...
o
...
UI

UI

TO-92 (MODIFIED)
See Secllon 6

Peak Operating Voltage .......................... 50 V
Forward Current ............................. 20 mA
Reverse Current .............................. 50 mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mWtC) ...................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

0-

'I

• Low Cost
• Simple Two Lead Current Source
• Simplifies Floating Current Sources
No Power Supplies Required
• Good Operating Current Tolerance
±20%

ABSOLUTE MAXIMUM RATINGS (25°C)

o

UI

BENEFITS

Current Regulation
Current Limiting
Biasing
Linear Ramp and Staircase
Generator

...
UI

H

UI

CATHODE

c

cO
A

A

C

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

I....!.
2

I3

-

4

-

2

S
T

-

J!.
9

Forward Current (Note 1)

A

T
I
C

POV

VL

6
7

IFI

D

y
N

ZFI
CF

Peak Operating Voltage
INotes 1 and 21

JS06

JS07

JS08

JS09

JS10

JSll

24

29

3.8

3.0

3.6

4.7

43

S.6

Moo

1120

1.440

1.9

Nominal

1.400

1.800

24

Max

1.680

2.160

29

3.6

Min

SO

50

SO

50

50

50

Max

2.5

2.8

31

3.5

39

4.2

Typ

1.8

20

2.2

2.5

28

3.0

Smail-Signal Dynamic

Moo

033

02

,02

0.15

015

012

Impedance INote 1I

Typ

1.4

1.0

0.70

060

0.50

0.30

Anode-Cathode Capacitance

Typ

2

2

2

2

2

2

Limiting Voltage (Note 3)

NOTES
1 Pu Ise test du ration

Test Conditions

Unit

mA

VF = 25 V

IF = 11 IFI IMaxl

v

IEII

IF =091FI IM,"I

M12

VF=25V,f= 1 kHz

pF

VF

= 25 V, f = 1 MHz

NCL
=

2 ms

Current· limiter Diode
V-I CharacterIStic

2 MaXimum VF where IF < 1 1 IFHMax) IS guaranteed
3. Minimum VF required to Insure IF > 09 'FI(MIn)
IF

IF,

VR

I

/

VL

pov

VF

R

Silicanix

3-61

H
n-channel JFETs
current regulator diodes
Performance Curves NKL, VRMA
designed for • • •
See Section 4
Siliconix

------

BENEFITS

Regulation
• Current
Limiting
• Current
Biasing
• Linear
Ramp and Staircase
• Generator

• Low Cost
• Simple Two Lead Current Source
• Simplifies Floating Current Sources
No Power Supplies Required

TO-92 (MODIFIED)

See Secllon 6

ABSoLuTE MAXIMUM RATINGS (25°C)

ANODE

Plastic

~

Peak Operating Voltage ......................... 100V
Forward Current ............................. 20 mA
Reverse Current.............................. 50 mA
Total Device Dissipation
(25°C Free Air Temperature) ....................... 350 mW
Power Derating (to +125°C) ..................... 3.27 mW/oC
Storage Temperatu re Range ............... -55 to 135°C
Operating Temperature Range ............. -55 to 135°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

CATHODE

cO

A

A

C

c

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unless otherwise notprl)
Characteristic

4

-

5

-6

-7

S
T
A
T
I

IFl
POV

C

Max

Peak Operating Voltage
(Notes 1 and 21

VL

Limiting Voltage (Note 3)

ZFl

Smail-Signal DynamiC
Impedance (Note 11

CF

Anode-Cathode Capacitance

0
N

Forward Current (Note 1)

250

700

200

-

NOTES:
1 Pulse test duration

VF = 100 V
IJ.A

VF = 25 V
VF = 1.0 V

IF = led IFI

100
1.1

1.0

(Max)

~

----

IF = 09 IFI (Mini

15

44
2

M!!

VF = 25 V. f = 1 kHz

pF

VF

= 25 V. f

= 1 MHz

NKL, VRMA
='

2 ms

2. MaXimum VF where IF < 1 1 IF1(Max) IS guaranteed
3. MInimum VF required to Insure IF > 091FlIMm)

3-62

Test Conditions

Untt

V

~ V
9

Typical

770

1.2.

-23
-

Min

.

-- -

Siliconix

H

current regulator diodes
designed for • • •

Siliconix

Performance Curves NCL
See Section 4

Regulation
• Current
Limiting
• Current
Biasing
• Low
• Voltage References

BENEFITS
• Simple Two Lead Current Source
• In Low Cost Plastic Package
• Simplifies Floating Current Sources
No Power ~upplies Required

TO-92 (MODIFIED)
See Section 6

ABSOLUTE MAXIMUM RATINGS (25°C)

Plastic

Peak Operating Voltage .......................... 50 V
Forward Current ............................. 20 mA
Reverse Current.............................. 50 mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mWtC). ..................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

ANODE

~

DC
o

A

CATHODE

c

Bottom View

A

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Dynamic

Regulator Current

Limiting Voltage

VF=25V

IF=0.8 IFllmin) IFF 1.1

Peak op Volt

Impedance

Knee
Impedance

IF NOM

IF MIN

IF MAX

VL

VL

VOP

'ZD

'ZK

Nominal
rnA

Min
rnA

Max
mA

Max
Volts

Typical

IFIIMax)
Min Volts

Typical
Megohms

Typical
Megohms

J553

05

018

0.75

13

075

50

10

2

J554

10

0.6

16

1.75

055

50

1

1

J555

2.0

14

2.6

2.15

075

50

88

025

J556

30

2.4

38

2.6

075

50

6

014

J557

45

36

53

30

15

50

48

009

PART NUMBER

NOTES:
1 Pulse test-steady state currents may vary.
2. Pulse test-steady state Impedance may vary.
3 Min VF reqUIred to IRsure IF>O 8 IFI Imin).
4 Max VF where 'F < 1 1 IF1(max) IS guaranteed.

NCL

Siliconix

3-63

High Impedance Diode
Switching
High Dynamic Range Log Amps
High Isolation Protedion
Circuits

BENEFITS
• Low Cost

TO·92 (MODIFIED)

See Section 6

Plastic

ABSOLUTE MAXIMUM RATINGS (25°C)

A

Forward Current ............................ 10 mA
Total Device Dissipation ........•.....•...... 360 mW
Storage Temperature Range ............ -65°C to +135°C
Lead Temperature
(1/16" from case for 10 seconds) ............. 300°C

*
AO
C

C

Bottom View

ELECTRICAL CHARACTERISTICS (25°C)
Min Typ

Characteristic

-5

JPAD10

-10

--

JPAD20

-20

JPAD50

-50

S
T
A
T
I
C

1

IR

Reverse Current (Note 1)

JPAD100

-100

JPAD200

-200

3

0
V

4

N

Unit

pA

-35

-BO

BVR

Breakdown Voltage (Reverse)

VF

Forward Voltage Drop

0.8

1.5

CR

Capacitance

1.5

2.0

pF

NOTE:

1. The JPAD type number denotes Its maximum reverse current value in pica amps.
Devices with IR values intermediate to those shown are also available on request.

3-64

Test Conditions

-500

JPAD500

-2
-

Max

JPAD5

Silicanix

VR

=-5 V. f = 1 MHz

Preliminarv

high voltage
protection diode

H

Siliconix

designed for. . .

Performance Curves VRMA
See Section 4

• High Impedance Diode
Switching

BENEFITS
• Offers High Voltage Protection
• Broad Current Range

• High Dynamic Range Log Amps
• High Isolation Protection
Circuits

TO-92 (MODIFIED)

ABSOLUTE MAXIMUM RATINGS (25°C)

See Secllon 6

Anode to Cathode Voltage
JR135V ...................................... 135V
JR170V ...................................... 170V
JR200V ...................................... 200 V
JR220V ...................................... 220V
JR240V ...................................... 240V
Forward Diode Current IF ........................ 20mA
Reverse Diode Cu rrent IF ......................... 50 mA
Power Dissipation PO .......................... 360mW
(Derate 3.27mW/oC)
Storage Temperature TSTG .............. -55°C to 150°C
Operating Temperature TOp .............. -55°C to 135°C

Plastic
A

*
cD
c

A

D

c
A

Bottom View

ELECTRICAL CHARACTERISTICS (25°C)
Characteristic

Min Typ Max
JR135V

1

2

POV

IF'
IF2

Peak Operating Voltage'

Forward Current

Unit

Test Conditions

-

135

JR170V

170

JR200V

200

JR220V

220

JR240V

240

V

200

IF=1mA

VF=2V

770

200

/J A

3

VL

Limiting Current

4

ZD

Dynamic Impedance

2

MQ

5

AIF/AT

IF Temp Coefficient

+0.6

%/oC

0.9

V

VF= 100V
1= 0.8 IF' (min)
VF=25V
VF=2-100V
TA = -20 to + 85°C
VRMA

NOTE:

1. Pulse test duration 2 ms.

Silicanix

3-65

-I monolithic dual
o

I

g
Silicanix

n-channel JFET
designed for • • •
• Hybrid Circuits
Wideband Differential
• Amplifiers
• VHF/UHF Amplifiers

Performance Curves NNZ
See Sedion 4
TO·71
See Section 6

S2

02

fo
0,

0' 2

1
0 0

610 02

0,
S,
Bottom View

0,

~~
S,

BENEFITS

G2

52

• High Gain through 100 MHz
gfs > 4500 Mmho
• Low Insertion Loss
• Tight Tracking

ABSOLUTE MAXIMUM RATINGS (25 0 C)
S2 ...~D2

Gate-Drain or Gate Source Voltage ................. -25 V
Gate Current ........................................ 50 rnA

0,

lA

TO-71 = M440, M441

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic
1 S
2T
-A
3 T
-I
4 C

"5
6

-

0

Gate-Source Cutoff Voltage

BVGSS

Gate-Source Breakdown VOltage

lOSS

Saturation Dram Current (Note 2J

IG

Gate Current (Note 11

9fs
90s

M CISS

-~
9

Typ

Gate Reverse Current (Note 1)

VGS(offl

V

7 N
-A

8

IGSS

M440
Min

Common·Source Forward

Transconductance

-6

-1
-25

Crss

Common-Source Reverse
Transfer Capacitance

IVGS1-VGS21

Differential Gate-Source Voltage

Typ

Max
-500

-6

-1
-25

6

30

6

-500
9.000 4.500

4.500

Unit
pA
V

Test Conditions
VOS=0.VGS=-15V
VOS = 10 V, 10 = 1 nA
VOS=O.IG=-I~A

30

rnA

VOS= 10V,VGS=0

-500

pA

VOG = 10 V. 10 = 5 rnA

9.000
f = 1 kH2

IJmho

200

Conductance
Capacitance

Min

-500

Common-Source Output
Common·Source Input

M441
Max

200
VOG = 10 V. 10 = 5 rnA

50

50

12

12

f= 1 MHz

pF

M
10

A
T

10

rnV

VOG = 10 V. 10 = 5 rnA

NNZ

NOTES:
1. ApprOXimately doubtes for every 10°C Increase In TA
2. Pulse test duration = 300 IoIsec; duty cycle <;; 3%.

3-66

20

Siliconix

monolithic dual
n-channel JFETs

H

Silicanix

designed for • • •

Performance Curves NNZ
See Section 4

• Hybrid Circuits
DiHerential
• Wideband
Amplifiers
• VHF/UHF Amplifiers

• High Gain through 100 MHz
gfs > 5000 J.!mho
TO·78
• Low Insertion Loss
See Section 6
• Tight Tracking

BENEFITS

G1

~~
S1

ABSOLUTE MAXIMUM RATINGS (25 0 C)

5,
40'

30

06

0
'0

0

G,
01

Mm

Ma.

1

~

S
12 T
4
A
IS
T
I- I
6 C
17

8

9
';0 0

11

y

112 N
A
:13 M
I- I
14 C

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

Unit

-100

pA

-250

nA

VGS(off)

Gate-Source Cutoff Voltage

VGS

Gate-Source Voltage

IG

Gate Operating Current

lOSS

Saturation Drain Current
(Note 1)

91s

Common-Source Forward Transconductance

5000

10,000

91s

Common-Source Forward Transconductance

5000

10.000

90S

Common-Source Output Conductance

100

90S

Common-Source Output Conductance

150

-1

-5

-0 3

-4
nA

40

mA

Common-Source Input Capacitance
Common-Source Reverse Transfer Capacitance

12

en

EqUivalent Short Circuit Input NOise Voltage

20

Spot NOise Figure

16

-

17
M
1- A
I~ T
C
19 H
I- I
N
20 G

IIGl-IG2 1

Differential Gate Current

10SSl
IOSS2

Saturation Dram Current RatiO
(Notes 1 and 2)

IVGS1-VGS2 1

Differential Gate-Source Voltage

Min

20
095

~IVGS1-VGS21 Gate-Source Voltage Differential
Onft I Note 3)
~T

1

Ma.
20

095

1

10

15

20

40

pF

91s1

Transconductance RatiO (Note 2)

095

1

095

1

1= 100MHz
1=1 kHz

VOG=10V.10=5mA

nV

Unit
nA

-

1= 1 MHz
1= 10kHz
1=10kHz
RG = lOOK

dB

Test Conditions
VOG = 10 V, 10 = 5 mA

TA = 125°C

VOS = 10 V. VGS = a

mV

121

TA = 12SoC
VOS=10V.VGS=OV

v'FfZ

40

20

,

I = 100 MHz

/lV/oC

(Guarantee-no test)

TA = 150°C

1=1 kHz

1
MS912

Ma.

VGS=-15V,VOS=0

/lmho

5

Min

M5912

Test Conditions

VOG=10V,10=5mA

pA

CISS

Characteristic

G,
D,
= M5911,

VOS= 10V,10= 1 nA

-100

7

MS911

TO-78

V

-100

Crss

NF

I~o ~,

IG = -1 /lA, VOS = a

-25

1-

15

G,

7

10
5,

Bottom View

*ELECTRICAL CHARACTERISTICS (25 0 unless otherwise noted)
Characteristic

D,

C

Gate-Drain or Gate Source Voltage ................. -25 V
Gate Current ........................................ 50 rnA

G2

S2

-

TA= 2S·C
TB = 125°C
VOG = 10 V, 10 = 5 mA

TA = -S5°C
TB = 2SoC
f = 1 kHz

91s2

NNZ

* JEDEC registered data
NOTES:
1 Pulsewldth :s:;;; 300 /.lS, duty cycle :s:;;; 3%
2 Assumes smaller value 10 numerator
3 Measured at end pomts, T A and Ta

Silicanix

3-67

-

enhancement-type
p-channel MOSFET
designed for • • •

• High-Input
Impedance Amplifiers

H

Siliconix

Performance Curves MRA
See Section 4
BENEFITS
• High Input Impedance
IGSS = 30 Femto Amp Typical
• High Gain
gfs = 1000 j.tmho Minimum

Smoke Detectors
Electrometers
pH Meters
ABSOLUTE MAXIMUM RATINGS (25°C)
Drain-Source Voltage ........................... 25 V
Gate-Source Voltage ........................... ±10 V
Drain Current ............................... 30 mA
Total Device Dissipation at (Or Below) T A = 25°C
(Derate 3 mW;oC to +150°C) ........ , ... , ... 375 mW
Operating Junction Temperature ........... -55 to +150°C
Storage Temperature .................... -65 to +200°C
Lead Temperature
(1/16" from case for 10 seconds) ............... 265°C

TO-1S
See Section 6

JD
Go----J,s

S,B.C ~

G

D

ELECTRICAL CHARACTERISTICS (25°C)
Characteristic

-

1

2
3

-4

-5

S
T
A
T
I
C

6 0
y
IN
7 A
1- M
I
8
C

Min

IGSS

Gate-Source Leakage Current

BVOSS

Drain-Source Breakdown Voltage

-25

VGS

Gate-Source Voltage

-2.0

Max

Unit

-1.0

pA

--6.0
-20

Test Conditions
VGS=-10V,VOS=0

V

10 = -10 /lA, VGS = 0

V

VOS =-10 V, 10 =-10/lA

lOSS

Orain Cutoff Current

nA

VOS=-10V,VGS=0

10(on)

ON Drain Current

-3.0

mA

VOS =-10V, VGS=-10V

9fs

Common-Source Forward
Transconductance

1000

/lmhos

Ciss

Common-Source Input
Capacitance

6.0

Crss

Common-Source Reverse
Transfer Capacitance

1.5

pF

VOS =-10V, 10 = -2 mA, f = 1 kHz

VOS =-10V, VGS= -10V, f= 1 MHz

MRA

3-68

Siliconix

n-channel JFET
designed for • • •

3C

H
Siliconix

Performance Curves NH/NRL
See Section 4

VHF/UHF Amplifiers
• Mixers
• Oscillators
•

S
"'G

"ft

B'ENEFITS
Low Cost
• Automatic Insertion Package

•

TO-92
See Section 6

ABSOLUTE MAXIMUM RATINGS (25°C)

Plastic

Drain-Gate Voltage __ ............. _ ............ 25 V
Source-Gate Voltage .............. _ ............ 25 V
Drain-Source Voltage ........................... 25 V
Forward Gate Cu rrent ...... _...... _ .......... 10 mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mWrC) .... __ ................ 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ......... _ ..... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

,~:

G
GO
0

o

0

•

0

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

Min

1

-2
-

IGSS
S
3 T BVGSS
A
T
4 I VGS(of!)
C
5
lOSS

-6

VGS

7

9f.

8 0

Re(yt.)

-

-

N

Re(yo,)

-

A
10 M
I
-C
11

-

12

Gate-Source Breakdown

Voltage

Unit

-2.0

nA

-2.0

p.A

-25

Test Conditions

VGS =-15 V, VOS = 0

TA = +100°C

IG =-10p.A, VOS = 0
V

Gate-Source Cutoff
Voltage
Saturation Drain Current
Gate-Source Voltage

Common-Source Forward

Transconductance
Common-Source Forward

Transconductance

-8.0
2.0

20

-{l.5

-7.5

2000

7500

VOS=15V,lo=2nA
mA
V

-

VOS = 15 V, V GS = 0 (Note 1)
VOS=15V,IO=200p.A
f = 1 kHz

1600
IJmhos

y

9

Gate Reverse Current

Max

Common-Source Output
Conductance

Common-Source Input

Re(Yi')

Conductance
Common-Source Input

Ci"
Crss

Capacitance
Common-Source Reverse

Transfer Capacitance

200

f=100MHz
VOS = 15V, VGS=O

800
7.0
pF

f = 1 MHz

3.0

NOTE:
1. Pulse test PW = 300 p.s; duty cycle"; 3%.

NH/NRL

Siliconix

3-69

OQ

o

n-channel JFET
a.
:e designed for • • •

H

Siliconix

I I.

Performance Curves NH/NRL
See Section 4

• VHF/UHF Amplifiers
• Mixers
• Oscillators

BENEFITS

•

Low Cost
• Automatic Insertion Package

TO·92
See Section 6

ABSOLUTE MAXIMUM RATINGS (25°C)

Plastic

Drain·Gate Voltage ............................ 25 V
Source·Gate Voltage ........................... 25 V
Drain-Source Voltage ........................... 25 V
Forward Gate Current ........................ 10 rnA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mW/"C) ...................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) . , " .... , ..... 300°C

.~:

G
GO
,-s

o

0

C

S c

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

1

12

5 IGSS
,- T
3 A 6VGSS
1_ T
4 I VGS(off)

'"5 c
6
7

12

-13

-14

--8.0

1.5

24

2000

7500

gos

10 M Re(Yis)
I
11

-25

Common-Source Output
Conductance

1- C

nA
I'A

-{l.5

9fs

9 y Re(yos)
N

Unit

-1.0
-1.0

Gate·Source Cutoff Voltage
Saturation Drain Current

I-A

Max

Gate-Source Breakdown
Voltage

Common-Source Forward
Transconductance

18
Re(Yfs)
1_ 0

-

Gate Reverse Current

lOSS

I-

Min

Common-Source Forward
Transconductance

V

VGS=-15V,VoS=0

TA - +100°C

iG=-10I'A,VOS=O
VOS=15V,IO=10I'A

mA

VOS = 15 V, VGS = 0 (Note 1)

f = 1 kHz
75
1600

Common-Source Output
Conductance

Common-Source Input
Conductance

I'mhos
200

f = 100 MHz

VOS=15V,VGS=0

800

Ciss

Common-Source Input
Capacitance

6.5

Crss

Common-Source Reverse
Transfer Capacitance

2.5

NF

Noise Figure

pF

2.5
3.0

dB

NOTE:
1. Pulse test, pulse width = 300 I'S, duty cycle';; 3%.

3-70

Test Conditions

f = 1 MHz

VOS = 15V, VGS=O, RG = 1M
VOS = 15 V, VGS = 0, RG = lK

n
n

f = 1 kHz
f=100MHz
NH/NRL

Siliconix

n-channel JFET
designed for • • •

~

H
Siliconix

"1'1

~

Performance Curves NRLJ
NPAINH See Section 4

• General Purpose Amplifiers
• Analog Switches

"

BENEFITS
Low Cost
• Automatic Insertion Package

•

TO-92
See Section 6

ABSOLUTE MAXIMUM RATINGS (25°C)
Drain-Gate Voltage _______ . _.. _................ 25 V
Source-Gate Voltage ........................... 25 V
Drain-Source Voltage ........................... 25 V
Forward Gate Current ................... _.... 10 mA
Total Device Dissipation at 25° C Ambient
(Derate 3.27 mWtC). .. _.................. 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

Plastic

'4:

G
GD
D

s

s

c

D

C

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic
1

S IGSS

I- T
2

A BVGSS

I3

14

Gate Reverse Current
Gate-Source Breakdown

Voltage

T
I VGS(oll)

Gate-Source Cutoll Voltage

C IDSS

Saturation Dram Current

5

9ls

1- D

Min

Common-Source Forward

Transconductance

-25

Typ

Max

Unit

-0.01

-1.0

nA

-60
V

-0_2

-8_0

0_5

24

800

6000

Test Conditions

VGS=-15V.VDS=0

VDS = 15 V.ID = 10l'A
mA

VDS = 15 V. VGS = 0 (Note 1)

1=1 kHz

I'mho

6

Common-Source Output

Y gos
I- N
7 A
CISS
M
II
8
C Crss

Transfer Capacitance

19

NOise Figure

NF

Conductance
Common-Source Input
Capacitance

10

75

4_5

7.0

1.0

3.0

0.04

2.5

VDS = 15 V. VGS = 0
pF

Common-Source Reverse

-

IG =-10I'A. VDS=O

dB

1=1 MHz

VDS = 15 V. VGS = O.
RG = 1M n

1=1 kHz

NRlINPA/NH

NOTE:
1. Pulse test PW .; 630 ms. duty cycle'; 10%.

Silicanix

3-71

-- designed
n-channel JFET
for
....
~

H

I ""

Siliconix

Performance Curves 'NRU
NPAINH See Sedion 4

•••

General Purpose Amplifiers
• Analog
Switches
•

BENEFITS
Low Cost
•• Automatic
I nsertion Package

TO-92
See Section 6

ABSOLUTE MAXIMUM RATINGS (25°C)

Plastic

Drain-Gate Voltage ............................ 20V
Source-Gate Voltage ........................... 20V
Drain-Source Voltage........................... 20V
Forward Gate Current ....................... _. 10 mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mWrC) ...................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

'4:

G
GO
D

s

s

0

D

0

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

5 IGSS
I- T
2 A BVGSS
T
I VGS(off)
C
lOSS
1

1"3
4"
5

- Y0
6
- AN
7
M
I
8 C

-

Gate·Source Breakdown Voltage
Gate·Source Cutoff Voltage
Saturation Drain Current

9fs

Common-Soutce Forward Transconductance

gas

Common-Source Output Conductance

Ciss

Common-Source I nput Capacitance

Crss

Min

Gate-Reverse Current

Common-Source Reverse Transfer

Capacitance

Typ

Max

Unit

-.01

-100

nA

-20
-0.5

-10.0

0.5

20

V

Test Conditions
VGS=-10V.VOS=0
IG=-lO"A.VOS=O
VOS=10V,IO=1"A

mA

VOS = 10 V, VGS = 0 (Note 1)

500
10

f = 1 kHz

"mho
VOS=10V,VGS=0

4.5

pF

f = 1 MHz

1.0

NRL/NPA/NH
NOTE:
1. Pulse test PW .;; 630 msec, duty cycle';; 10%.

3-72

Siliconix

n-channel JFET
designed for • • •

~

H

Siliconix

Performance Curves NRL
See Section 4

VHF/UHF Amplifiers
• Mixers
• Oscillators
•

--

."
'"II

~

BENEFITS
Low Cost
•• Automatic
I nsertion Package

TO·92
See Section 6

Plastic

ABSOLUTE MAXIMUM RATINGS (25°C)
Drain-Gate Voltage ............................ 25 V
Source-Gate Voltage ........................... 25 V
Drain-Source Voltage ........................... 25 V
Forward Gate Current ........................ 10 mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mWrC) ...................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

o~:

G

0

TD
o

D

S

D

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic
IGSS

1-2.
2

S

BVGSS

I- T
3

A
T

VGS(off)

I- I
4 C

15

lOSS
9fs

6
Re(Yf.)
1- 0
7 Y C's.
I- N
8

Crss

Min

Gate Reverse Current

Gate-Source Breakdown

Voltage
Gate·Source Cutoff
Voltage
Saturation Drain Current

Common·Source Forward

Transconductance
Common·Source Forward

Transconductance
Common-Source Input

Capacitance
Common-Source Reverse
Transfer Capacitance

Typ

Max

Unit

-om

-100

nA

-25

Test Conditions
VGS=-10V,VOS=0
IG =-10"A, VOS=O

V
-0.5

-10.0

1

25

1000

7500

VOS=10V,IO=1"A
mA

VOS = 10 V, VGS = 0, (Note 1)

-

f = 1 kHz
"mho

800

f = 100 MHz
VOS=10V,VGS=0
3.5

pF

f = 1 MHz

0.85
NRL

NOTE:
1. Pulse test PW = 300 I'S, duty cycle'; 3%.

Siliconix

3-73

p-channel JFETs
designed for • • •

H

Siliconix

Performance Curves
PSAJPSB/PSC
See Sedion 4

Switches
• Analog
• Choppers
• Commutators

BENEFITS
I nsertion Loss
• LowrDS(on)
= 75 n Maximum (P10S6)

Offset or Error Voltages Generated
• No
by Closed Switch
Purely Resistive

ABSOLUTE MAXIMUM RATINGS (25°C)
TO-92
See Se.tion 6

Gate-Dram or Gate-Source Voltage (Note 1) __ • __ .. _. 30V
Gate Current .................... __ . _..... __ 50 mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mW/"C). ........... __ . __ . ____ 360 mW
Operating Temperature Range ____ . _... _... -55 to 135°C
Storage Temperature Range..... _.. __ . _... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) ........... _. _300°C

G
.~: GD
5

0

o

0

5

0

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Pl0B6
Max

Characteristic
1

-

BVGSS

--.2.

-

4

- 65
-7
-

S
T

30

30

Gate Reverse Current

*

10(0f!)

Dram Cutoff Current

lOGO

Drain Reverse Current

I

c

VGS(off) Gate-Source Cutoff Voltage
lOSS

8
9

rOS(on)

10

rd,(on)

0
V Ciss

12

Crss

N

- 13

W

- 15

I
T
C

14

Saturation Drain Current

VOS(on) Oraln-Source ON Voltage

11
-

Voltage

Min

3

-

IGSS

Gate-Source Breakdown

S

16 H

Static Drain-Source ON

Resistance
Drain-Source ON Resistance
Common-Source Input

Capacitance

Pl0S7
Max

Min

V

2

2

-10

-10

-0.5

-0.5

IJA

2

2

0.1

0.1

nA
p.A

10

5

-5

-10

nA

V
mA
V

IG = 1 p.A, VOS = 0
VGS= 15V, VOS=O
VOS =-15 V, VGS = 12 V (Pl086)
VGS = 7 V (Pl087)
VOG=-15V,IS=0

TA =85'C

VOS=-20V,VGS=0

-0.5

VGS = 0,10 =-5 mA (Pl086),IO =-3 mA (Pl087)

75

150

n

lo=-lmA,VGS=O

75

150

n

10=O,VGS=0

45

45

f = 1 kHz

VOS =-15 V, VGS = 0
pF

Common-Source Reverse

Transfer Capacitance

10

TA=85'C

VOS=-15V,10=-1 p.A

-0.5

f = 1 MHz

10

VOS = 0, VGS = 12 V (P1OS6)
VGS = 7 V (Pl087)
VOO = -6 V, VGS(on) = 0

td(on)

Turn-ON Oelay Time

15

15

tr

Rise Time

20

75

VGS(of!)

10(on)

RL

td(of!)

Turn-OFF Oelay Time

15

25

Pl0S6

12V

-5mA

910n

tf

Fall Time

50

100

Pl087

7V

-3mA

1.8Kn

n,

PSAIPSB/PSC

NOTE:

1. Due to symmetrical geometry these units may be operated with
source and drain leads interchanged.
I

3-74

Test Conditions

Unit

SilicDnix

low-leakage

pi(o-amp

H

Siliconix

iodes

designed for • • •

BENEFITS
• Very High Off-Isolation
1 pA Max (PAD1)

•
• Diode Switching
Impedance
• High
Protection Circuits
Clipping Circuits

Q

TO-18 (MODIFIED)
See Secllon 6

I1

ABSOLUTE MAXIMUM RATINGS (25°C)
Forward Current ........................... 50mA
Total Device Dissipation ..................... 300 mW
Storage Temperature Range ............ -55°C to +125°C
Lead Temperature
(1/16" from case for 10 seconds) .............. 300°C

ANODE

CATHODE

*.

CATHODE

(C... le.d for
PAD1, 2, & 5 only)

ANODE

0

-

CATHODE

o

CASE

Bottom View

ELECTRICAL CHARACTERISTICS (2S·C unless otherwise noted)
Characteristic
1
12
13
I-S
I~ T
5 A
1ST
I-I
l-i C
19
110
11 D
I-V
12 N

Min

Typ

Max

Unit

Test Conditions

-1

PADl

-2

2

-5
IR

-10

Reverse Current

5
pA

PAOlO

VR = -20 V

-20

20

-50

50

-100
BYR Breakdown Voltage (Reverse)
VF

Forward Voltage Drop

CR

Capacitance

-45

PAD100

-120

-35

PAD1, 2, 5
IR = -1/1A

V
0.8

1.5
0.8

~AD10

Oavt

+15 V

04

pF

VR=-5V,f=1 MHz

'R<'PAt

.....

PADt

I
8 1n

1"

I

-15V

PAOlO, 20, 50,100
PAD1, 2, 5,10,20,50,100

IF = 5 rnA

2

D,"*" Dit I: '

l1li

l

t,

PAD1

2N4393.
CONTROL SIGNAL

C

j

PAD1. 2. 5
PAOlO, 20, 50, 100

2N4111A

t

VOUT

APPLICATION
Operational Amplifier Protection. Input Differential Voltage limited
to 0.8 V (typ) by PADS 01 and 02 Common mode input voltage
limited by PADS 03 and 04 to ±15 V.

Typical sample and hold circuit with clipping. PAD diodes reduce
offset voltages fed capacitively from the FET switch gate.

Siliconix

3-75

H

n-channel JFETs
designed for • • •

Siliconix

BENEFITS

Switches
• Analog
• Commutators
• Choppers
• Integrator Reset Switch

• Low Insertion Loss
High Accuracy in Test Systems
rDS(on) < 30 n (PN4091)
• High Off-Isolation
ID(off) < 200 pA
High Speed
trise < 10 ns (PN4091)
• Short Sample and Hold Aperture Time
Crss <5 pF

•

Plastic

ABSOLUTE MAXIMUM RATINGS (25°C)

TO·92
See Section 6

Reverse Gate-Drain or Gate-Source Voltage ......... -40 V
Gate Current ............................... 10mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mWrC) ...................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

o~:
GO

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

1

BVGSS

2"

-

lOGO

..2.

Gate-Source Breakdown Voltage

PN4091

Min

PN4092

Max

-40

Dram Reverse Current

Min

Max

-40

-=.

S
T

1010fl)

9

T

C

pA

400

400

400

nA

200

pA

400

nA

i11

1055

1-

Saturation Dram Current

INote 1)

-10

30

nA

-1 p.A. VOS

-1

-5

8

15

V
mA

VOslon)

'it

0.2

Dram-Source ON Voltage

VOs

VOs

~

VOS = 20V, VGs

V

J

Static Dram-Source ON ReSistance

30

50

80

11

VGs

a'raln-Source ON Resistance

30

50

80

11

VGs = 0, 10

C1SS

Common-Source Input Capacitance

16

16

16

Crss

Common-Source Reverse Transfer
Capacitance

5

5

5

tdlon)

Turn-DN Oelay Time

15

15

20

Rise Time

10

20

40

Turn-OFF Time

40

60

80

N

19

pF

~

-21

toff

3-76

V,N

~
D

Silicanix

0

mA

10=6.6mA

~

0

f~

1 kHz

f~

1 MHz

VOs~20V, VGs~O

VOs

~

0, VGs = -20 V

VOO ~ 3 V, VGslon) ~ 0
ns

PN4091
PN4092
PN4093

1010ni
6.6mA
4
2.5

VGsloff)
-12V
-8
-6

RL
42511
700
1120

NCB

Voo
NOTE:
1. Pulsewldth = 300 p.s, duty cycle';;; 3%.

150°C

0, 10 = 1 mA

-S
20 W t,

~

10 =4

VGs=O

'dslon)

18

150°C

10 = 2.5 mA

'Oslon)

I- V

150°C

20 V, 10 ~ 1 nA

16

0

150°C

VGs~-12V

0.2

17

0

VGs ~ - 8 V

~'20V

115

1-

~

VGs = - 6 V

0.2

113

G

VGS=-20V.IS=0

nA
-7

12

I

~

~A

-2

s

Test Conditions
IG

pA

400

-5

D

Unit

200

400

Gate-Source Cutoff Voltage

D

200

200

VGsloff)

D

V

200

I- I

D

200

Dram Cutoff Current

A

10

Max

-40

-5
- R7

5

Bottom View

PN4093

Min

4

~

i

Performance Curves NCB
See Section 4

INPUT PULSE
VOUT

RISE TIME < 1 ns
FALL TIME < 1 m
PULSE WIDTH 1 ,.1
PULSE DUTY CYCLE 0;;; 10%
PULSE GENERATOR IMPEDANCE

SAMPLING SCOPE
RISETIME04nl
INPUT RESISTANCE 10 M
INPUT CAPACITANCE 1 7 pF

son

n-channel JFETs

.H

Siliconix

designed for • • •

Performance Curves NT
See Sedion 4

• Ultra-High Input
Impedance Amplifiers

BENEFITS

ZZ
~~

10"""1

J>J>
ZZ

""

-~~

o~­
(X)

ABSOLUTE MAXIMUM RATINGS (25°C)

""
ZZ

Reverse Gate-Drain or Gate-Source Voltage ......... -40 V
Gate Current ............................... 10 rnA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mW;oC) ...................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

TO·92

-~~

Plastic

See Section 6

o~­
(X)
J>J>

,~:

GO
S

C

o

c

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
CharacteristIC

PN4117

PN4118

PN4ll9

PN4120

PN4117A

PN4118A

PN4119A

PN412DA

Umt

Test ConditIOns

Min Typ Max Min Typ Max Min Typ Max Min Typ Max

1

:-

.~ S
3

4"

-

5
6

T
A
T
I

C

IGSS

B

Gate Reverse Current
PN4117 Series Only

-10

-20

pA

-25

-25

-50

nA

-1

-1

-1

-5

Gate-Source Breakdown Voltage

VGSloffl

Gate-Source Cutoff Voltage

-06

-1 B -1

Saturation Dram Current

003

009 0.08

0.24 020

060 003

03

210

250 100

330

300

(Note 2)

Common-Source Forward

Transconductance (Note 2)

9 N
_A
M
10 I

gos

Common-Source Output
Conductance

C ISS

Common-Source Input
Capal::1tance

-c

Crss

Common·Source Reverse Transfer
Capacitance

-25
-40

70

-25
-40

80

-25

-10

-40

-40
-3

-2

-6

nA
I

V

-06

70

VGS = ·20 V. VOS = 0

VGS = -20 V. VOS = 0

10QoC

IG=-lpA.VOS=O
VOS-l0V.IO-l nA

rnA

VOS=10V.VGS=O

,umho
10

100°C

pA

BVGSS

9fs

11

-10

-25

IGS5

0
Y

-

-10

Gate Reverse Current
PN4117A Senes Only

lOSS

--""
-~~

10"""1

• Low Power
lOSS < 90 J1.A (PN4117)
• Minimum Circuit Loading
I GSS < 1 pA (PN4117 A Series)

Electrometers
pH Meters
Smoke Detectors

ZZ
""

f"" 1 kHz

20
VOS= IOV,VGS=O

pF
15

15

15

f= 1 MHz

15

NT
NOTES:
1. Due to symmetrical geometry. these units may be operated With source and drain leads interchanged.
2. This parameter is measured dUring a 2 ms Interval 100 ms after power IS applied.

Siliconix

3-77

n-channel JFETs
designed for • • •

H

Siliconix

Performance Curves NPA, NH

See SecHon 4

• General Purpose Amplifiers

BENEFITS
Low Cost
• High
Impedance
• IG Input
= 35 pA Typically
• Lowen Noise
= 5 nV1y'Hz Typically

@

1 kHz

TO-92

See Section 6

ABSOLUTE MAXIMUM RATINGS (25°C)

Plastic

.~:

.......

Gate-Drain or Gate-Source Voltage (Note 1)
-30V
Gate Current ............................... 50 rnA
Total Device Dissipation at 25°C Ambient.
(Derate 3.27 mWtC) . ..................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

G
GO
D

•

•

D

D

D

Bottom View

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic
1
I- S
2
T
1- A
T
!
4
I

--2-

I- e
5
6

IGSS

Gate Reverse Current (Note 2)

8VGSS

Gate-Source Breakdown Voltage

VGS(otf)

Gate-Source Cutoff Voltage

lOSS

Saturation Drain Current (Note 31

91s

Transconductance (Note 31

90s

Common-Source Output
Conductance

Crss

Common-5ource Reverse Transfer
Capacitance

17

18

I9

I10

D
y
N
A
M
I
C

C1SS
COG

Common-Source Forward

PN4302

Max

Mon

PN4303
Min
Max

Upit

1

-1

-1

nA

01

--0.1

--0.1

~A

-30

-30

5.0

1000

-30
-10

~O

-40
0.5

PN4304
Max
Min

4.0

10

2000

0.5

15

V

11

12

Drain-Gate Capacitance

IVlsl

Common-Source Short Circuit
Forward Transadmlttance

~A,

TA = 85°C

VOS = 0

VOS = 20 V,IO = 10 nA

1000

50

50

50

1=1 kHz

3

3

3

6

6

6

2

2

2

VOS=20V,
VGS =0
1= 1 MHz

Common-Source Input Capacl-

NOise FIgure

IG = -1

.umho

tance

NF

VGS = -10V.
VOS =0

rnA

pF
VOG= 10V,
IS = a

1=140kHz

dB

VOS=10V,
VGS =0

1=1 kHz,
Rgen =10M!l

,umho

VOS=20V,
VGS =0

1= 10MHz

l-

-

Tast Conditons

20

2.0

700

1400

(Note 3)

3.0

700

NPA, NH
NOTES:

1. Geometry IS symmetrical. Units may be operated with source and drain leads Interchanged
2. ApprOXimately doubles for every 10°C Increase In TA'
3. Pulse test dUration = 2 ms

3-78

Silicanix

n-channel JFETs
designed for • • •

H
Siliconix

Performance Curves NCB
See Section 4

Switches
• Analog
• Commutators
• Choppers

BENEFITS

• Low I nsertion Loss
Offset or Error Voltages Generated
• No
by Closed Switch
Purely Resistive
High Isolation Resistance from
Driver
Plastic
Low Cost

•
ABSOLUTE MAXIMUM RATINGS (25°C)

1'0·92

Reverse Gate·Drain or Gate·Source Voltage ....... , ,-40 V
Forward Gate Current, , , , , , , ' , , ' , , , ' , , , , , , , , , , 50 mA
Total Device Dissipation at 25° C Ambient
(Derate 3.27 mW;oC), , , . , , , . , , , , . , , , , . , , , . 360 mW
Operating Temperature Range. , . , , , . , , , , . ,-55 to 135°C
Storage Temperature Range, , , , , , , , , , , , , . ,-55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) , , , , , , . , , , , . , ,300°C

See Section 6

o~:

G
GO
s

D

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
PN4391

Characteristic

Mm

1----2....

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

:~

Mox

Mm

-1 0

-200

-200

-200

--40

Test Conditions

Ur1lt

-10

--40

V

--40

VGS = -20 V, VOS = 0

I

VGS=-5V

200

:~ ~
7

IO{off)

100°C

IG""-l}J.A,VOS"'O

10

~

D

Max

-10

nA

1---2.
3

Mm

D

Bottom View

PN4393

PN4392

Mox

S

D

100'C

10

Drain Cutoff Current

nA

VOS = 20 V

VGS=-7V

200

{ao°c

-A

'~T
9
!-

1....22..

10

VGS=-12V
200

I

e

I~

VGS(offJ

GaTe-Source Cutoff Voltage

--4

-10

-2

-5

--05

lOSS

Saturation Drain Current (Note 1)

50

150

25

100

5

12

-3

V

60

mA

I~

VOS(on)

Dram-Source ON Voltage

rOS{on)

Static Drain-Source ON ReSistance

04

14

I~

30

100

rds(on)

Drain-Source ON ReSistance

30

60

100

17

C ISS

Common-Source Input Capacitance

16

16

16

1-

18
-D
19
V Crss

td~on)

Turn-ON Delay Time

22

tc

Rise Time

1---;;-

V

VGS = 0

"
"

VGS=O, 10

pF

VOS = 0

10

=:

3 mA

10

=:

6 mA

=:

IEII

1 mA
f'" 1 kHz

VGS = 0, VOS = 0
VOS=20V,VGS=0
VGs=:-5V

5

21

23

5

N

100'C

1 nA

VOS=20V,VGS=0

5
Common-Source Reverse Transfer
Capacitance

=:

lo"'12mA
60

16

I-

20 V, 10

04

1-

I......:..':...

=:

04

1-

I-

VOS

VGS

=:

-7V

f

=:

1 MHz

VGS=-12V

15

15

15

5

5

5

Voo

ns

S td(off}

Turn-OFF Delay Time

20

35

50

W tf

Fall Time

15

20

30

10 V, VGS(on) '" 0
lo(on)
VGSloffl
-12 V
PN4391
12 mA
-7
PN4392
6
PN4393
-5
3
=:

RL
BOOn
16K
32K

NCB
NDTE
1 Pulse test required, pulse Width

=:

300

}.IS,

duty cycle

< 3%

Siliconix

3-79

... n-channel JFETs
•
-0

H

•Z designed for • • •
- • VHF Amplifiers

Siliconix

A.

Performance Curves NH
See Section 4

10()

BENEFITS

-3 •

• LowN FNoise
= 3 dB Typical at 400 MHz
• WideHighBand
9fs/Ciss Ratio

Mixers

t-

en
en
II

>=

:::)

G
IU
t-

Z

:::)

o

ABSOLUTE MAXIMUM RATINGS (25°C)

Plastic

TO·92
See Section 6

Gate-Drain or Gate-Source Voltage ............... -30V
Gate Current ............................... 10 mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mWrC). ..................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) .............. 300°C

,~:
GD

:e

D,

0

S

0

~DG

Bottom View

IU

U

:!
~

:::)

en

Min

Characteristic
1
12
-S
T
3 A
I-T

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

1
4 C VGS(off)
15
6 D
I-y

-c
10

Saturation Drain Current (Note 1)

13

F

-R
14 E
_0
U
15 E
I_N
16 C
I-Y
17

VGS =-15 V, VDS = 0 V

IG = -1 p.A. VDS = 0 V

5

15

4500

7500

VDS= 15V,ID= 1 nA
mA
p.mho

f = 1 kHz

50

Common-Source Output Conductance

VDS= 15V,VGS=OV
Common-Source Reverse Transfer Capacitance

0.8

Common-Source Input Capacitance

4

Common-Source Output Capacitance

2

Characteristic

-~

nA

-6

Gate-Source Cutoff Voltage

Common-Source Forward Transconductance

11 H 9 155
'"121 b l55

10

Test Conditions

V

IDSS

Coss

Unit

-30

9fs

1-2.. N 90S
B A erss
-M
9 1 CISS

Max

100 MHz
M,n
Max

Common-Source Input Conductance
Common-Source Input Susceptance

pF

400 MHz
Min
Max

f= 1 MHz

Unit

100

1000

2500

10,000

9 0 55

Common-Source Output
Conductance

75

100

boss

Common·Source Output
Susceptance

1000

4000

9fs

Common·Source Forward
Transconductance

Gps

Common·Source Power Gain

NF

NOise Figure

Test Conditions

p.mho
VDS=15V,VGS=OV

4000
18

10
2

dB
4

VDS=15V,ID=5mA
VDS = 15 V, ID = 5 mA, RG = lK
NH

NOTES:
1. Pulse test duration

3-80

= 300115

Siliconix

n

n-channel JFET
designed for • • •

H

Siliconix

"...Z
VI

0W

and Medium Frequency
• Low
Amplifiers

BENEFITS

• Low Cost

TO·92
See Section 6

ABSOLUTE MAXIMUM RATINGS (25°C)

Plastic

Gate·Drain or Gate·Source Voltage ............... -25V
Gate Current (FWD) ......................... 10 mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mW/"C) ...................... 360 mW
Operating Temperature Range ............. -55 to 135°C
Storage Temperature Range ............... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) ........... " .300°C

o~:
GD
s

c

D

C

S
D

G

Bottom View

*ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

-J,

Gate Reverse Current

"3

Gate-Source Breakdown Voltage

2 S IGSS
T
A BVGSS

4" i

-

6
7

-

VGS(off)

5 C VGS

Saturation Drain Current

rds(on)

Drain-Source ON Resistance

9fs

-9

D gos

y

10 N 9fs
-A
11 M Ciss
I
12 C Crss

-

-13

-

14

Common.source Forward

Transconductance

-{l.S

Common-Source Forward
Common-Source Input Capacitance

Unit
nA
p.A

-25

-{l.4

1.0

2000

Test Conditions
VGS=-15V,VOS=0

TA-85°C

IG =-10 p.A, VOS = 0
-8.0

V

-7.5

Common-Source Output Conductance

Transconductance

Max
-10

Gate·Source Voltage

loss

8

-

Gate-Source Cutoff Voltage

Min

VOS=15V,IO=1p.A
VOS = 15 V, 10 = 100 p.A

40

mA

500

n

VOS = 15 V, VGS = 0
VGS=O,IO=O

9000

IEII

f = 1 kHz

200 p.mho
1800

VOS=15V,VGS=0
20

f = 1 MHz

pF

Common-Source Reverse Transfer
Capacitance

5.0

NF

Common-Source Spot Noise Figure

3.0

eN

Equivalent Short Circuit Input Noise
Voltage

50

dB
nV

y'Hz

RG=150kn
VOS=15V,10=1 mA

f = 1 kHz
NBW = 150 Hz

• JEOEC registered data

Siliconix

3-81

III

~

~

Q

n-channel DMOS FE's

Designed for Military and Industrial Applications • •

'"

•
~
•
~
Q •
•
III
Q
o •
•
~
Q
•
•
III

'"
Q

'"

High-Speed Switching
Analog Switch
Multiplexer
Digital Switch
A to D Converters
D to A Converters
Choppers
Sample and Hold

•

Performance Cu'rves DMCB
See Sedion 4
BENEFITS
• Ultra low feedback capacitance

(O.30pF)
• High switching speeds «1 ns)
• Gate can accept

± 40V

TO-72
So. Soctlon &

ABSOLUTE MAXIMUM RATINGS (DC)
Drain Current .........•........................ 50mA
Total Device Dissipation at 25DC
Case Temperature ............................. 1.2W
Storage Temperature Range ............. -650 to +2000 C
Lead Temperature (1 116 H from case for 10 sec.). ..... 3000 C
Operating Temperature Range ........ -55 0 to+150 o C

G

Orain-to-source

+30

+10

+20

Vdc

VSD

Source-to-drain*

+10

+10

+20

Vdc

VOB

Orain-to-substrate

+30

+15

+25

Vdc

VSB

Source-to-substrate

+15

+15

+25

Vdc

VGS

Gate-to-souice

±4O

±40

~ ."
~~

Vdc

VGB

Gate-to-substrate

±40

±40

±40

Vdc

VGO

Gate-to-drain

±40

±40

±40

Vdc

Typical Switching Waveform

TEST CONDITIONS

+5V- - -

Switching

510

Rl

-r----"'"
foo%

.JI

VIN

+voo

S

S0210 S0212 S0214 UNIT

PARAMETER
Vos

TO SCOPE

~

~

o

50%

OV --.1" 110 %

Input pulse td.lr<1ns
Pulse width = 1oon8

Rep rate = 1MHz

SWITCHING CHARACTERISTICS

SAMPLING SCOPE

tr(ns)

td(ON)(ns)

tr<360ps
RIN=1MQ
CIN =20pF

VDD
1

10
5
15

1

RL

Typ

Max

680
680
1k

06
07
09

10

Typ

Max

07 110

08

10

tOFF(ns)

Typ
90
90 1
140

Max
.•

•

-tOFF IS dependent on Rl and CL and does not depend on the device characteristics

3-82

Siliconix

DC ELECTRICAL CHARACTERISTICS (TA = 25°C
PARAMETER
Breakdown voltage
Orain-to-source
SVOS

1

-

unless otherwise specified,)

TEST CONDITIONS

SD210
SD212
SD214
UNIT
Min Typ Max Min Typ Max Min Typ Max

VGS=VSS=OV.IO=10!'A
VGs=Vss=-5V.ls=10nA

30

35
25

10

10

25

20

2

SVSO

Source-Io-drain

VGo=Vso=-5V
lo=10nA

10

10

20

"3

SVOS

Orain-to-substrate

15

15

25

-4

VGS =OV. source OPEN
lo=10nA

SVSS

Source-to-substrate

VGS=OV. drain OPEN
IS=10!'A

15

15

25

5

-

6

8
T
A
T
I
C

7""

ISO (OFF) Source-to-drain

Gate

IGSS

-8
-

Laakage current
lOS (OFF) Orain-to-source

9

VGS=VSS=-5V
VOS=+10V
VOS=+2OV

1

VGO=VSO=-5V
VSO=+10V
VSO=+2OV

1

Threshold voltage

VOS=VGS=VT.IS=l1'A
VSS=OV

ros(ON)

Orain-to-source
resistance

lo=1.0mA. VSS=O
VGS=+5V
VGS=+10V
VGS=+15V
VGS=+20V
VGS=+25V

V

10
1

10
nA

10

10

1

1

VOS=VSS=OV
VGS= ±40V

VT

1

10

25

0.1
0.5

1.0

2.0

50

70
45

30
23

0.1
0.1

1.0

2.0

50

70
45

30
23

19
17

10
0.1

0.1

1.0

2.0

50

70
45

30
23

19
17

V

Q

19
17

AC ELECTRICAL CHARACTERISTICS
PARAMETER
10

11

U
'13

14

gfs
D
y
N
A
M
I
C

Forward transconductance

Small Signal Capacitancas
(See capacitance model)

TE8T CONDITIONS
VOS=10V. VSs=OV
lo=2OmA.f=lkHz

8D212
8D214
SD210
Min Typ Max Min Typ Max Min Typ Max
10

15

10

15

10

15

UNIT
mmhos

VOS=10V.f=lMHz
VGS=VSS=-15V

C(GS+GO+GIl)

Gata node

2.4

3.5

2.4

3.5

2.4

3.5

C(GO+OB)

Orain node

1.3

1.5

1.3

1.5

1.3

1.5

C(GS+SB)

Source node

3.5

5.5

3.5

5.5

3.5

5.5

COG

Reverse transfer

0.3

0.5

0.3

0.5

0.3

0.5

IEII

pF

DMCB

Siliconix

3-83

n-channel DMOS FETs

Designed for Military and Industrial Applications

•
•
•
•
•
•
•
•

High-Speed Switching
Analog Switch
MUltiplexer
Digital Switch
A to D Converters
D to A Converters
Choppers
Sample and Hold

• • •

Performance Curves DMCB
See Sedion 4
BENEFITS
• Ultra low feedback capacitance
(O.30pF)
• High switching speeds «1 ns)
• Diode protected gate

TO-72
SaeS.ctlon8

ABSOLUTE MAXIMUM RATINGS (OC)
Drain Current ••••..••••••••.•.••••••••.•••..•.. 50mA
Total Device Dissipation at 25°C
Case Temperature ............................. 1.2W
Storage Temperature Range ••...•••••••• -65° to +200°C
Lead Temperature (1/16"fromcasefor 10sec.) •••••• 30QoC
Operating Temperature Range •.••.... _55° to +150°C
PARAMETER

Vos
VSO
VOB
VSB

Orain-to-source
Source-to-drain*
Orain-to-substrate
Source-to-substrate

VGS

Gate-to-source

VGB

Gate-to-substrate

VGO

Gate-to-drain

S0211 SD213 SD21&
+10 +20
+30
+10
+10 +20
+15 +25
+30
+15 +15 +25
-25
-15
-15
+25

+25

+30

-0.3

-0.3

-0.3

+25
-30
+25

+25
-15
+25

+30
-25
+30

UNIT

Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Typical Switching Waveform

TEST CONDITIONS

+5V- - - - , - - - - - - , .

,-A50%

I~%

VIN

Switching

10%

OV

TO SCOPE +Voo

510

VO:~DD----X~;.

RL

OV- - -

Input pulse. td, tr <1 ns
Pulse width = 100n5

Rep rate =1 MHz

d.~
'1<10.:,:%_....:.10:':'%:1\
t,l~~FF

SWITCHING CHARACTERISTICS

SAMPLING SCOPE

tr<360ps
RIN =1 M2
CIN=20pF

90%

tdION)(na)
Voo

I

5

10
15

trlns)

10FFlna)

RL

Typ

Max

Typ

Max

Typ

16BO
6BO
lk

06
0.7
0.9

10

07
06
10

11.0

9.0
90
140

I

Max

-tOFF IS dependent on RL and CL and does not depend on the device characteristics.

3-84

Siliconix

DC ELECTRICAL CHARACTERISTICS ITA = 25°C unless otherwise specified.)
PARAMETER
Breakdown voltage
Orain-to-source
BVDS

1

TEST CONDITIONS

SD213
SD216
SD211
UNIT
Min Typ Max Min Typ Max Min Typ Max

VGS=VBS=OV,ID=10jIA
VGS=VBS=-5V,ls=10nA

30
10

35
26

10

26

20

2

BVso

Source-to-drain

VGO=VBO=-6V
ID=10nA

10

10

20

3

BVDB

Orain-to-substrate

1!j

16

25

-4

VGB=OV, source OPEN
ID=10nA

BVSB

Source-to-substrate

VGB=OV, drain OPEN
IS=10jIA

15

15

26

-

Leakage current
IDS (OFF) Drain-to-source

5

-

6

S
T
A
T
I
C

1""
-

ISD (OFF) Source-to-drain

Gate

IGBS

8

VT

9

rDs(ONI

VGS=VBS=-5V
VOS=+10V
VDS=+2OV

1

VGO=VBO=-5V
VSO=+10V
VSO=+2OV

1

10

10

VDB=VSB=OV
VGB=+25V
VGB=+30V

Threshold voltage

VOS=VGS=VT,IS=ljIA
VSB=OV

Orain-to-source

lo=I.0mA, VSB=O
VGS=-+5V
VGS=+10V
VGS=+15V
VGS=+2OV
VGS=+26V

resistance

1

26

V

10
1

10

1

10

nA

10

1

10

10

jIA
10

0.5

1.0

2.0

50
30

70
46

0.1

1.0

2.0

50
30

70
46

0.1

1.0

2.0

50
30

70
46

23

23

23

19

19

19
17

V

Q

AC ELECTRICAL CHARACTERISTICS
PARAMETER
10

11

12
13
14

gfs
D
y
N
A
M
I
C

Forward transconductance

Small Signal Capacitances
(See capacitance model)

TEST CONDITIONS
VOS=10V, VSB=OV
lo=20mA,f=lkHz

SD211
SD213
SD215
Min Typ Max Min Typ Max Min Typ Max
10

15

10

15

10

UNIT
mmhos

16

VOS=10V, f= lMHz
VGS=VBS=-15V

C(GS+GO+GB)

Gate node

2.4

3.5

2.4

3.5

2.4

C(GO+OB)

Orain node

1.3

1.5

1.3

1.5

1.3

1.5

C(GS+SBI

Source node

3.5

5.5

3.5

5.5

3.5

5.5

COG

Reverse transfer

0.3

0.5

0.3

0.5

0.3

0.5

--

3.5
pF

DMCB

Silicanix

3-85

- n-channel
D-MOS FETs
o
o

H

Siliconix

C"4

Q

en

designed lor Military and Industrial Applications.
Amplifiers
•• VHF/UHF
Mixers
•• Oscillators
High-Speed Switching
Normally lIOn" Switch
•• Analog!
Digital Switch
Multiplexer
•• Low-Voltage Switch
FEATURES
• High Figure-of-Merit gfs/C
• High Speed Switch « 1 Ins)
• High Gain
• Wide Dynamic Range-Input
• Low Voltage Requirements
Battery Operation

BENEFITS
• High Frequency Gain
• High Speed Switching
• Low Distortion

=

~

TO·72
See Section 6

ABSOLUTE MAXIMUM RATINGS (OC)
Drain Current .............................. 50 mA
Total Device Dissipation at 25°C
Case Temperature .......................... 1.2W
Storage Temperature Range ........ -65° to +200°C
Lead Temperature
(1"16 from case for 10 sec.) ................ 300°C
Operating Temperature Range ...... -55° to +150°C
DC ELECTRICAL CHARACTERISTICS (TA

2

3

SVDS
'GSS
VGS(offl

4

~
6

----a

'D ~ l;

V,N

Vo
600

RL

510

/90%
50%

10%

VOD

I+-

C--

90%

50%

'\10%

10%/

'rl+-

ov - - -_

TYP

MAX

1.0

TYP

MAX

TYP

0.7

1.0

9.0

MAX

TdlONI

90%

Your

RL

-::;j I+- '0"

5

680

0.6

10

680

0.7

0.8

9.0

15

lk

0.9

1.0

14.0

'tOFF is dependent on RL and does not depend
on the device characteristics.

TYPICAL CHARACTERISTICS

MAXIMUM POWER DISSIPATION
.1 TEMPERATURE

Z

e.

1.000

g

900

i
oS

800

z

700

0
j:

::

600

0;

500

I/)

Q

400

w

300

0

200

a:

~

II.

150

13SW
0..
w
(J 120

I' F'-SOUR1CE-Td-sueJTRATE
IVse) VOLTS

10

Z

~ 105 5

I/)

iiia:

~
~

w

(J

a:

r--

:::I

90

~
~

60

0

I

30

10-'15

\

7S

45

"'" ~

I/)

0
t-

100

zI

0
0

20

40

60

80

;C

100

a:

c

TEMPERATURE('C)

3-92

DRAIN-TO-SOURCE RESISTANCE.s
SOURCE-TO-SUBSTRATE AND
GATE-TO-SOURCE VOLTAGE

::::

Siliconix

15

r-DRAIN-TO-S URCE CURRENT •

5~

AMBIENT TEMPERATURE (T A) '25'C

0
0

4

8

12

16

20

GATE-TO- SOURCE VOLTAGE (VGS) VOLTS

TYPICAL CHARACTERISTICS (Cont.)

DRAIN-TO-SOURCE RESISTANCE
va TEMPERATURE

~

e.

<
a.

iL

Ul 100

g

0

W

0

80
70

iii

60

z

Iii

W
II:
W

0

40

0

30

I

20

~

10

0

10M

W

1M

<
I.:
<
W

lOOk

CJ

,.......r-

...
<

~V

II:

<

I

I-

100

I

10

W

0

II:

0

50

25

75

1

;;;)

100

lOOk
<
1.:<
"be§>" _ - -

30

~~~
u'?J-

c

15

10 = 10 nA

225

= 10 uA

225

'0

= 1 uA, VSB = 0 V
= Vss =0 V. VGS =30 V
10 = 10 rnA. Vss = 0 V. VGS = 5 V
10 = 10 rnA. Vss = 0 V. VGS = 10 V
10 = 10 rnA. Vss = 0 V. VGS = 15 V
10 = 10 rnA. Vss = 0 V. VGS = 20 V
10 = 10 rnA. Vss = 0 V. VGS = 5 V
Vos = 0 V. Vss = -55 V. VGS = 4 V
See Figure 1, PLO

::.

UNIT

25

V

01

1

20

50

75

Vos

ros (on)
Cgg

LO,-L02 Capacitance

av.

15

Vas::' VGS = VTH • Is

ros (on)

ReSistance Matching

av,

::.

Dram Open, VGe =

III

0

= Vss = -5 V. Is = 10 nA
= Vos = -5 V. 10 = 10 nA

Source Open. VGS

'Gas

Drain-Source "ON" ReSistance

LIMITS
MIN' TYP3 MAX

uA

2
30

n

23
19
7

3,

44

pF

8

+17 dBm

dB

+35

MHz

200

NOTES:
1 Refer to PROCESS OPTION FLOWCHART for additional ,"formation
2 The algebraic convention whereby the most negative value IS a minimUm, and the most posItive value IS a maximum, IS used In thiS data sheet
3 TYPical values are for DESIGN AID ONLY, not guaranteed nor subject to production testmg

APPLICATION HINTS
Schematic of the baSIC commutation-type HF doublebalanced mixer using resonant-gate excitation Recom-

mended reading is AN85-2 "A Commutation DoubleBalanced MOSFET Mixer of High Dynamic Range."

-VGG

so."

THT

0"

"Pll.~[1
°Il °

.J,.

a
"

'-----v----/
LOW,PASS
IMAGE TERMINATING
FILTER
(OPTIONAL)

1

L-

ID(mAJ

~llq

'I

~

IJ /

1000

"

T4·1

R

l6vI !,2V L
II

5000

T4·1

JL

IDIV

1680

PF

~~

0

~.

VJ

//

I

/

-5000
-5000

Figure 1

/

8V

IEII

/

-

~
ov

/ /I
/1."
v IL!J
/ '/
VOS

0
l000/DIV

(V)

5000

First and Third Quadrant I-E Characteristics Showing Effect
01 Gate Voltage Leading to large-Signal Overtoad Distortion.
Figure 2

Siliconix

3-107

Small Signal
-- JFETs
for
- designed
••
-- •
C")

en

!!!
('\4
en

BENEFITS

Analog Switches
Choppers
Commutators

!!!

Silicanix

• Low Cost
• Automated Insertion Package
• Low Insertion Loss
rDS(on) <300 (SST111)
• No Offset or Error Voltages
Generated by Closed Switch
Purely Resistive
High Isolation Resistance
from Driver
• Fast Switching
td(on) + tr
13 ns Typical
• Short Sample and Hold
Aperture Time
Cgd(off) <5 pF
Cgs(off) <5 pF

•••

t-

H

Performance Curve NCB
See Section 4

t-

t-

en
en

=

ABSOLUTE MAXIMUM RATINGS (25°C)
Gate-Drain or Gate Source Voltage ........... -35 V
Gate Current ................................. 50 mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mWrC) .... . . . . . . . . . . . . . . . .. 360 mW
Operating Temperature Range ......... -55 to 135°C
Storage TempElrature Range ........... -55 to 150°C
Lead Temperature Range
(1116" from case for 10 seconds ............ 3000C

.'=)-

o~:

+
L

04

~

:E --

___

29MAX

09S

~

G

~

~
0

e~

5

TOP VIEW

~

+12 MAX

005MIN

DIMENSIONS IN MILLIMETRES

SOT-23

ELECTRICAL CHARACTERISTICS (2SOC unless otherwise noted)

I

Che!'e~er!~t!c
I

IGSS

Gate-Reverse Current

VGSloftl

Gate-Source In+ offl Voltage

I

SST111
Min

Max
1

BVGSS

Gate-Source Breakdown Voltage

lOSS

Saturation Drain Current (Note 1)

rOS lonl

Drain-Source on Resistance

gd~
1,0ft)1
sg off)

Drain-Gate off! Capacitance
Source-Gate off

Cdg 10n)/+ Orain-Gate on! Capacitance
C loni"
Source-Gate on

sa

-3

-10

I

SST112
Min
-1

Max

I

SST113
Min

Max

Unit

I

Test Conditions

1

nA

-5

-3

V

VOS - 5 V, 10 - 1 /LA

V

VOS - 0, IG - l/LA

-35

-35

-35

20

5

2

VOS

o V, VGS

mA

VOS - 15 V, VGS - 0
VOS - 0.1 V, VGS - 0

30

50

100

ohm

5

5

5

pf

VOS

= 0, VGS = -10 V, f = 1 MHz

28

28

pf

VOS

= VGS = 0, f = 1 MHz

28

NOTE:
1. Pulse test duration 3001-1-5; duty cycle .so3%

ORDERING INFORMATION

3-108

Device

Marking

SST111

Cll

SSTl12

C12

SSTl13

C13

15 V

1

Silicanix

NCB

Performance Curve PSAI
PSB/PSC See Section 4

Small Signal
JFETs

BENEFITS
• LowCost
• Simplifies Series-Shunt Switching when
Combined with SST113, Its N-Channel
Complement
• Low Insertion Loss
rOS(on) <850 (SST174)
• No Offset or Error Voltages Generated by
Closed Switch
Purely Resistive
High Isolation Resistance from Driver
• Short Sample and Hold Aperture Time
Csg(off) 6.0 pF Typical
Cdg(off) 6.0 pF Typical
• Fast Switching
td(on) + tr 7 ns Typical

designed for • • •
•
•
•

H

Silicanix

Analog Switches
Choppers
Commutators

ABSOLUTE MAXIMUM RATINGS (25°C)

=

Gate-Drain or Gate-Source Voltage (Note 1) ..... 30 V
Gate Current ................................. 50 mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mWrC) .. . . . . . . . . . . . . . . . . . .. 360 mW
Operating Temperature Range ......... -55 to 135°C
Storage Temperature Range ........... -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) . . . . . .. . . ... 300°C

~
G

D

a--aJ
275MAX_,

..

=1,5 2.MAX

04L._
+

s

6

~O'5

Id--

D

,:~1'2MAX

TOP VIEW

\

005MlN
DIMENSIONS IN MILLlMETRES

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
SST174

Characteristic

Min

IGSS

Gate-Reverse Current
(Note 2)

VGS (offl

Cutoff Voltage

BVGSS

rOS(on)

Gate-Source

5

Gate-Source

10

30

Breakdown Voltage

-20

Static Drain-Source

Max

6

3
30

-135

-7

-70

Capacitance

r-1YE6

I

Cdg(onl
Csg(on)

Drain-Gate on!
Capacitance
Source-Gate on

~

I TYP

Device

Marking

SST174

574

SST175

575

SST17B

576

SSTl77

577

TYP

1

4

O.B

Max

-2

Test Conditions

nA

2.25

V

VOS = -15 V, 10 = -10 nA

V

VOS = 0, IG = 1 /LA

VOS = 0, VGS = 20 V

-20

rnA

VOS = -15 V, VGS= 0

250

300

ohm

VGS = 0, VOS = -0.1 V

TYP

..!!!..

pi

VOS - 0, VGS - 10 V,
1= 1 MHz

..!!!..

pi

VOS = VGS = 0, f = 1 MHz

-35

I

Unit

1

30

6
32

SST1n
Min

1

125

Source-Gate off

ORDERING INFORMATION

Max

30

Cdg(offl
Csg(off)

32

SST176
Min

1

B5

ON Resistance
Orain·Gate offl

SST175
Min

1

Saturation Drain
Current (Note 31

lOSS

Max

6
I TYP
32

-1.5

6

32

-

NOTES:
PSAIPSB/PSC
1. Geometry is symmetrical. Units may be operated with source and drain leads interchanged.
2. Approximately doubles for every 10"C increase in TA.
3. Pulse test duration = 300/LSi duty cycle :G3%

Silicanix

3-109

Small Signal
JFETs

Performance Curve NP
See Sedion4

H

Silicanix

BENEFITS
• High Input Impedance
IG 5 pA Typical
• Good for Low Power Supply
Operation
VGS (off) <1.5 V (SST201)

designed for ...

=

• General Purpose Amplifiers

~:

ABSOLUTE MAXIMUM RATINGS (25°C)
Gate-Drain or Gate-Source Voltage (Note 1) ... -40 V
Gate Current ................................. 50 mA
Total Device Dissipation at 25°C
(Derate 3.27 mW/oC) . . . . . . . . . . . . . . . . . . . .. 360 mW
Operating Temperature Range ......... -55 to 135°C
Storage Temperature Range ........... - 55 to 1500C
Lead Temperature Range
(1/16" from case for 10 seconds) ........... 3000C

·=~I.L

04

t

.-

_a

~095

29MAX

095

~

o

C~--=}2MAX

TOP VIEW

\

005MIN

DIMENSIONS IN MILLIMETRES

SOT·23

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
SS1"201

Characteristic

Min

Gate Reverse Current

(Note 2)

VGS(off)

Gate·Source
Cutoff Voltage

-0.3

BVGSS

Gate·Source
Breakdown Voltage

-40

Saturation Drain

0.2

Current (Note 3)

-1.5

1.0

IG

Rt.

Common·Source Forward
TransconauC18nce \Note 3)

90S

Common-Source Output
Conductance

I lYP
1.0

Ciss

Common-Source Input
Capacitance

I lYP

SST203
Min

-0.8

-4

0.9

4.0

500

1000

4

1!iOO

VOS = O. VGS = -20 V

-2.0

V

VOS = 20 V. 10 = 10nA

V

VOS = O. IG = l"A

3

I lYP
5
500

3.6

~

I lYP

~

I lYP

I lYP

4

-W5

2.0
4

I lYP
10

mA

VOS = 20 V. VGS = 0

pA

VOG = 20 V. 10 = 200 "A

3-110

Device

Marking

SST201

POl

SST202

P02

SST203

P03

SST204

~04

v. VGS =

~m!l0s

VOS = 2U

"mhos

VOS = 20 V. VGS = O. f = 1 kHz

O. f

pf

VOS = 20V. VGS = 0

nVl--./Fil.
f= 1 kHz

VOS - 10 V. VGS - O.
f= 1 kHz

= 1 kHz

NPA

NOTES:

ORDERING INFORMATION

Test Conditions

nA

I lYP

5

5

0.2

Unit

0.1

lYP

I lYP

4

I lYP

20

~
5

5

Max

-40

-40
4.6

SS1"204
Min

-2.0 -10.0 -0.3

I lYP

5

Max
0.1

0.1

I lYP

Noise Voltage

Max

-40

Gate Current

en

Min

0.1

IGSS

lOSS

SS1"202

Max

1. Geometry is symmetrical. Units may be operated with source and drain leads interchanged.

2. Approximately doubles for every 10"C increase In TA'
3. Puis. test duration = 2 ms.

Silicanix

n-channel DMOS FETs

Designed for Military and Industrial Applications

•
•
•
•
•
•
•
•

High-Speed Switching
Analog Switch
Multiplexer
Digital Switch
A to D Converters
D to A Converters
Choppers
Sample and Hold

...

Performance Curve DMCB
See Section 4
BENEFITS
• Ultra low feedback capacitance
(0.30pF)
• High switching speeds «1 ns)
• Diode protected gate
SOT-143
TOP VIEW

ltr i GJ

r~::::;-,

I

ABSOLUTE MAXIMUM RATINGS (OC)
Drain Current .................................. 50mA
Total Device Dissipation at 25°C
Case Temperature ........................ 360mW
Storage Temperature Range ......... -55° to +150°C
Lead Temperature (1/16" from case for 10 sec.). ..... 300° C
Operating Temperature Range . . . . . . . . __ 55° to +150 0 C

I

B

II L~~ II
f-

rl

I

h

I

I

~
•
1... _ _ _ _ ...1

5

I

0

S

J

+10

+20

Vdc

+10

+10

+20

Vdc

+30

+15

+25

Vdc

Source-to-substrate

+15

+15

+25

Vdc

Gate-to-source

-15
+25

-15
+25

-25
+30

Vdc

Gate-ta-substrate

-0.3
+25

-0.3
+25

-0.3
+30

Vdc

Gate-to-drain

-30
+25

-15
+25

-25
+30

Vdc

Drain~to·source

+30

VSD

Source-to-drain'

VDB

Drain-to-substrate

VSB
VGS
VGB
VGO

GtJJ DC

S0211 S0213 S0215 UNIT

PARAMETER

VDS

-

Typical Switching Waveform

TEST CONDITIONS

+5V - - - -r----~
90 %

TO SCOPE

+voo

510

RL

,-A1

VIN

Switching

50%
10%

OV

Input pulse td, tr< 1ns
Pulse width lOOns
Rep rate = 1MHz

=

SWITCHING CHARACTERISTICS

SAMPLING SCOPE

td(ON)(ns)

tr<360ps
RIN

=1 MQ

Voo

680
1 680

Typ
06
07

1k

09

RL

CIN =20pF
I

*tOFF

IS

10
5
15

Max
10

tr(ns)
Typ
Max
07
10

Typ

OB

90
90

10

140

tOFF(ns)
Max

I

dependent on AL and CL and does not aepend on the device characteristics

Siliconix

3-111

DC ELECTRICAL CHARACTERISTICS (TA =25°C unless otherwise specified.)
PARAMETER
Breakdown voltage
Orain-to-source
BVOS

1

2
-

......

...

~
en
en

-

-

SST215
SST213
SST211
UNIT
Min Typ Max Min Typ Max Min Typ Max

VGS=VBS=OV,IO=10,.A
VGS=VBS=-5V, IS= 10nA

30
10

35
25

10

25

20

BVso

Source-to-drain

VGO=VBO=-5V
lo=10nA

10

10

20

3

BVOB

Orain-to-substrate

VGB = OV, source OPEN
lo=10nA

15

15

25

4

BVSB

Source-to-substrate

VGB =OV, drain OPEN
IS = 10,.A

15

15

25

5

Leakage current
lOS (OFF) Orain-to-source

25

V

-

-

TEST CONDITIONS

S
T
A
T
I
C

6

7

ISO (OFF) Source-to-drain

Gate

IGBS

8

-9

VGS=VBS=-5V
VOS=+10V
VOS=+2OV

1

VGO=VBO=-5V
VSO=+10V
VSO=+20V

1

10

VOB=VSB=OV
VGB=+25V
VGB = +30 V

VT

Threshold voltage

VOS=VGS=VT,IS=lI'A
VSB=OV

ros(ON)

Drain-to-source
resistance

lo=1.0mA, VSB=O
VGS=+5V
VGS=+10V
VGS=+15V
VGS=+2OV
VGS=+25V

1

10

10

1

1

10

1

10

nA

10

10

10

,.A
10

0.5

1.0

2.0

50
30

75
50

0.1

1.0

2.0

50
30

75
50

0.1

1.0

2.0

50
30

75

23

23

23

19

19

19
17

V

50

Q

AC ELECTRICAL CHARACTERISTICS
PARAMETER
10

-

gfs

0
y
11

12
- 13

-14

N

Forward transconductance

Small Signal Capacitances
(See capacitance model)

TEST CONDITIONS
VOS = 10V, VSB = OV
lo=2OmA, f= 1kHz

SST215
SST211
SST213
Min Typ Max Min Typ Max Min Typ Max
9.0

15

9.0

9.0

15

15

mmhos

VOS = 10V, f= 1 MHz
VGS=VBS=-15V

A C(GS+GO+GB) Gate node

2.4

3.5

2.4

3.5

2.4

3.5

Orain node

1.3

1.5

1.3

1.5

1.3

1.5

C(GS+SB)

Source node

3.5

6.0

3.5

6.0

3.5

6.0

COG

Reverse transfer

0.3

0.5

0.3

0.5

0.3

0.5

M
I
C

C(GO+OB)

UNIT

pF

DMCB

ORDERING INFORMATION
Device

3·112

Marking

55T211

011

55T213

013

55T215

015

Siliconix

Small Signal

Performance Curve NZB
See Sedion 4

JFETs

designed for.

H

Silicanix

BENEFITS
Industry Standard Part
In Low Cost Plastic
Package
High Power Gain
11 dB Typical at 450 MHz
Common-Gate
• Low Noise
2.7 dB Typical at 450 MHz
• Wide Dynamic Range
Greater than 100 dB
Easily Matches to 75 n Input

•

••

Amplifiers
•• VHF/UHF
Oscillators
Mixers
•

•

•

<275MAX_

~.~.
"~: ~1

ABSOLUTE MAXIMUM RATINGS (25°C)

,.L __

Drain-Gate Voltage ............................. 25 V
Source:Gate Voltage ........................... 25 V
Forward Gate Current ........................ 10 mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mWrC) ..................... 360 mW
Operating Temperature Range ......... -55 to 135°C
Storage Temperature Range ........... -55 to 1500C
Lead Temperature Range
(1/ 16" from case for 10 seconds) ............ 300°C

r

G

095

W

I

t4MAX

s

D

cA;X

TOPVIEW

~

t12MAX

005MIN

DIMENSIONS IN MILLIMETRES

50T-23

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
55T308

Characteristic

Min

IGSS

Gate-Reverse Current

BVGSS

Breakdown Voltage

-25

VGS(off)

Gate-Source
Cutoff Voltage

-1

55T309

Min

-1

Gate-Source

Saturation Drain Current

lOSS

Max

12

(Note 1)

gfs

Common-Source
Forward Transconductance

NF

Noise Figure

Max
-1

SO

8000

-1
12

-4
30

10000

~
2.7

Max
-1

-25

-25
-S.5

55T310

Min

-2

-S.5

24

SO

8000

~
2.7

~
2.7

Test Conditions

Unit
nA

VGS

~

-15V, VOS

~

0

= 1 p.A

V

VOS ~ 0, IG

V

VOS

= 10 V, 10 = 1 nA

rnA

VOS

= 10 V, VGS = 0

J.l.mhos

VOS

= 10 V, 10 = 10 rnA, f = 1 kHz

dB

VOS

= 10 V, 10 = 10 rnA, f = 450 MHz
NZB

NOTE:
1. Pulse test PW 300 p.s; duty cycle .. 3%

ORDERING INFORMATION
Device

Marking

SST30a

zoa

SST309

Z09

SST310

Z10

Silicanix

3-113

l1li

-

monolithic dual
n-channel JFETs

H

Silicanix

Performance Curves NNR
See Section 4
BENEFITS
Minimum System Error and
Calibration
• 15 mV Offset Maximum
(SST404)
95 dB Minimum CMRR (SST404)
• Low Drift with Temperature
25 p'vr C Maximum (SST404)
• Operates from Low Power Supply
Voltages
VGS(off) < 2.5V
• Simplifies Amplifier Design
Output Conductance < 2 p.mho
Low
Noise
•
en = 6 nVVHz at 10 Hz Typical

designed for • • •

•

Noise FEY Input
• Low
Amplifiers
and Me.dium Frequency
• Low
Amplifiers
Impedance Converters
• Precision
• AmplifiersInstrumentation
• Comparators
ABSOLUTE MAXIMUM RATINGS (25°C)
Gate-Drain or Gate-Source Voltage
Forward Gate Current.
Device Dissipation (each side)
@TA = 85°C derate 2.6 mWtC
Total Device Dissipation
@TA = 85°C (derate 5 mwtC)
Storage Temperature Range

ORDERING INFORMATION
50V
lOrnA

Device

300mW

Marking

55T404

404

55T405

405

55T406

406

500mW
-65 to 200°C

ELECTRICAL CHARACTERISTICS (@ 25°C unless otherwise noted)
404
M,n Mo,

CharacterIstic

1

2
3
4

BVGSS

T

VOSlon)

-5

05

B

8

'G

Gate Current/Note 1)

aVG! - G2

Gate-Gate Breakdown
Voltage
Common Source Forward
Transconductance (Note 2)

9

- '"
10
- '0'
11

~

,- N

-5

-25

-25
-5

2000

O.

100

05

VDG" 15 V,

-15

-15

-15

pA

-10

-10

-10

nA

'0 = 200p.A

V

VOS=O.VGS=O IG=±lI1A

±50

'50
7000

2000 7000

20

2000

20

9fs

1000 2000

52

501C-8 PIN

~O'
Dl

52

51

D2

C

02

1= 1 kHz

2000

1000

2000
f= 1 kHz

Common-Source Output
Conductance

20

Common-Source Input

C ISS

1000

20

20

30

30

15

'N

Equivalent Short CtrCUlt
Input NOIse Voltage

20

20

20

CMRR

Common Mode Rejection
RatiO (Note 3)

IVGSI - VGS21

Differential Gate-Source
Voltage

15

20

Gate SourceVoltagp Differ
en'~' ,)"ft \Note 4)

25

40

Capacitance

VOG"'5V,
10'" 200IJA

pF

I- T
I.

Ves= IOV,
VGS=O

20

30

~

TA = 12SoC

7000

80

~

5,

02

VOS=15V,IO=lnA

VOS=10V,VGS=Q

80

,-

4~

"'UU -~:::; V, iO - 20Dj.lA

mA

80

17

VOS=O,VGS=-30V

100

Common Source Reverse
Transfer Capacitance

I-

pA

-25

Crss

16

01
VOS= 0, 10 =-lIJA

-23

-71

14

,-

Test Conditions

V

pmho

Common Source Forward
Transconductance

1
C

100

1-50

Common Source Output
Conductance

12 A gas

13

-25

UnIt

M"

-50

-25

-23

Vc!t;:g;:: (on)

(Note 21

-50

40B
M,n

V

Gate Source
Saturation Drain Current

5 C 'OSS

.,--

Gate-Source Cutoff
Voltage

405
Mo,
M,n

-25

(Note 1)

S VGSloff)

-,

-50

Gate Reverse Current

lOSS

~

Gate Source Breakdown
Voltage

95

nV
H,

f= 1 MHz

VOS'" 15V.
VGS=O

f'" 10Hz

dB

VOG = 10 to 20 V, '0 '" 200IJA

40

mV

VOG = IOV, '0 = 200j.lA

80

/lvte

90

I

~

61VGSI - VGS21

6T

NOTES
1 Appro.lmately doubles for every 10 e Increase In TA 2 Pulse tes1 duration = 300J.ls,duty cycle" 3%
Q

4 Measured at end POints. TA.

3-114

VOG"'lOV.
10 = 200JjA

3 eMRR=20IoQl0

Te and Te

Silicanix

T A" ~55"e. T6 = +25°e
Te = +125"'e

[~]
.~VOD=10V
GS1· GS2

NNR

Small Signal

H

Siliconix

JFETs

Performance Curve NH
See Sedion 4

designed for • • •

••

BENEFITS
Low Noise
NF=3dB Typical at 400/MHz
Wide Band
High gfs/Ciss Ratio

•

VHF Amplifiers
Mixers

•

ABSOLUTE MAXIMUM RATINGS (25° C)
Gate-Drain or Gate-Source Voltage ..... , ..... -30 V
Gate Current ................................. 10 mA
Total Device Dissipation at 25°C Ambient
(Derate 3.27 mWOC) ...................... 360 mW
Operating Temperature Range ......... -55 to 135°C
Storage Temperature Range •••• 0' • • • • • -55 to 150°C
Lead Temperature Range
(1/16" from case for 10 seconds) ............ 300°C

(75MAX~I __

,~:

ooLttil""
W
r

095

G

1--1
'4 MAX

s

0

TOP VIEW

~A;X t12MAX
~

005MIN

DIMENSIONS IN MllUMETRES

SOT-23

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic
IGSS

Gate Reverse Current

Min

BVGSS

Gate-Source Breakdown Voltage

VGS(off)

Gate-Source Cutoff Voltage

lOSS

Saturation Drain CUrrent (Note 1J

9fs

Common-Source Forward Transconductance

90S

Common-Source Output Conductance

Max

Unit

1.0

nA

-30
-6
5

15

4500

7500
50

erss

Common-Source Reverse Transfer Capacitance

Ciss

Common-Source Input Capacitance

4

Coss

Common-Source Output Capacitance

2

9iss

Common-Source Input Conductance

biss

Common-Source Input Susceptance

2000

BOOO

90ss

Common-Source Output
Conductance

45

60

boss

Common-Source Output
Susceptance

700

3000

9fs

Common-Source Forward
Transconductance

G ps

Common-Source Power Gain

NF

Noise FIgure

400 MHz
TYP
700

VOS = 15 V. 10 = 1 nA

Device
SST4416

f = 1 kHz

JLmho
VOS = 15V. VGS = OV

f= 1 MHz

pF

Unit

IEII

Test Conditions

",mho
VOS = 15V. VGS = OV

5500
20

13

1

2.5

dB

NOTE:

ORDERING INFORMATION

IG = 1 ",A. VOS = 0 V

rnA

O.B

100 MHz
TYP
50

Characteristic

V

Test Conditions
VGS = 15 V. VOS = 0 V

VOS = 15 V. 10 = 5 rnA
VOS= 15V.IO= 5mA,RG= 1 KG
NH

t. Pulse test duration = 300 "'S.

Marking

I

H16

Silicanix

3-115

n-channel JFETs
designed for • • •

H

Siliconix

Performance Curves NCB
See Section 4

Switches
• Analog
• Commutators
• Choppers

BENEFITS
I nsertion Loss
• LowrOS(on)
< 50 on (U202)

Off-Isolation
• Good
10(off) < 1 nA

TO-tS

ABSOLUTE MAXIMUM RATINGS (25°C)

See Section 6

Gate-Drain or Gate-Source Voltage ............... -30 V
Gate Current .....•......................... SOmA
Total Device Dissipation at 25°C Case Temperature
(Derate 10 mWrC) ......................... 1.8W
Storage Temperature Range .............. -65 to +200°C
Lead Temperature
( 1/16" from case for 10 seconds) ............•. 300°C

.~:

j

G.C

\

0

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
U200

Characteristic
1

1"2

-3
-4
-

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

VGS(off)

Gate-Source Cutoff Voltage

S

T
A

T

Min

i

10(011)

Dram Cutoff Current

6

lOSS

Saturation Drain Current (Note 1)

7

rds(on)

Draln-~ource

5

-

C

8
-

0
Y C1SS

9

Crss

N

U201

Max

3

ON Resistance

Common-Source Input
Capacitance (Note 1)
Common-Source Reverse Transfer

Capacitance

U202

Max

3-116

Max

Unit

-1

-I

-I

nA

-1

-1

JlA

-3

-1.5

-5

-3.5

-10

V

1

i

1

nA

1

1

1

JlA

25

15

75

30

Test Conditions

VGS = -20 V, VOS = 0

-30

-30

I
150°C

IG=-IJlA,VOS=O
VOS = 20 V, 10 = 10 nA
VOS = 10 V, VGS = -12 V

150

mA

VOS = 20 V, VGS = 0

150

75

50

ohm

VGS = 0,10 = 0

30

30

30

8

8

8

150°C

f = 1 kHz

VOS=20V,VGS=0
f= 1 MHz

pF
VOS=O VGS=-12V

NCB

NOTE:
1. Pu1se test required, pulsew,dth

Min

-1
-30
-0.5

Min

= 300 Jlsec, duty cycle .;; 3%.

Silicanix

monolithic dual
n-channel JFETs
designed for • • •

H

Siliconix

Performance Curves NQP
See Section 4

• Differential Amplifiers

BENEFITS

•

Good Matching Characteristics
TO-71
See Section 6

ABSOLUTE MAXIMUM RATINGS (25°C)
Gate-Drain or Gate-Source Voltage ______ ••••••••• -50 V

G,

Gate Current ••••••••••••••••••••••••••••••• 50mA
Total Device Dissipation at 25°C
(Derate 1.7 mW/oC to 200°C) ••••••••••••••• 300mW

s,

G,

Lead Temperature

10

o·
o.

,0
'0

°1

from case for

S2

S2

Storage Temperature Range •••••••••••••• -65 to +200°C

(1/16"

~~
10

0,

0 7 G2

s,

seconds) •....•••••.•••• 300°C

G2

Gt., 0,

Bottom View

~,

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

I-.!.
2
13' S
1'4 T
A
15' T
I -"- I
6 C

Min

IGSS

Gate Reverse Current

BVGSS
VGS(o!fl
VGS

Gate-Source Breakdown Voltage
Gate-Source Cutoff Voltage
Gate-Source Voltage

IG

Gate Operating Current

7

lOSS

Saturation Dram Current (Note 1)

8

91,

Common-Source Forward Transconductance (Note 11

1-

19 0 915
1'iO V 9o,

1000
600

Common-Source Output Conductance
Common-Source Output Conductance

Common-Source Input Capacitance
Common-Source Reverse Transfer Capacitance

1-

EqUivalent Short CircUit Input Noise Voltage

en

Characteristic

Unit
pA

-500

nA

-4.5
-4.0
-50

0.5
1000

Common-Source Forward Transconductance (Note 1)

N
I "iT A 9o,
M
112
I C1SS
I~ c Crss
14

-50
-05
-0.3

Max
-100

U232
Max

U233
Max

VGS=-30V. VOS=O

V

IG=-lI'A.VOS=O
VOS=20V.10=1 nA

pA

VaG = 20 V. 10 = 200 I'A

-250
5.0
5000

nA
mA

VOS = 20 V. VGS = 0

1600
35
10
6
2

I'mho

80

U231
Max

Test Conditions

U234 U235
Max Max

125·C

VOS = 20V. VGS = 0
VOG = 20 V.IO = 200l'A
VOS = 20 V. VGS = 0
VaG = 20 V.IO = 200l'A

pF
nV

Test Conditions

Differential Gate Current

10

10

10

10

10

nA

VOG= 20V.10=200I'A

16

(loss 1-1OSS2)
IOSSl

Saturation Drain Current

5

5

5

10

15

%

VOS=20V. VGS=O

5

10

15

20

25

mV

10

25

50

75

100

17 M iVGS1-VGS2 i
1- A
T
18 C t>iv GS1-V GS2i
I-H
t>T
19 I
N
1- G
(91,1-91,2)
20
91,1

Voltage
Gate-Source Voltage

Oillerentlal Orilt (Note 2)

---

Transconductance Match

igo,l-9o,2 i

Differential Output
Conductance

121

Match (Note 1)
Differential Gate-Source

I'vtc
10

25

50

75

100

3

5

5

10

15

5

5

5

5

5

(Note 1)

1= 1 kHz

1= 100 Hz

IIGl-IG2 i

1-

1= 100MHz

1= 1 MHz

15

1-

1= 1 kHz

VOS= 20 V. VGS = 0

v'Hz
Unit

150·C

VaG = 20 V. 10 = 200 I'A

125·C

TA = 25·C
TB = 125·C
TA=-55 C
TB = 25·C

%

1=1 kHz

NOTES:
1. Pulse te,t required. pul,ewidth = 3001's. duty cycle';; 3%.
2. Measured at end point'. TA and TB.

I'mho

NQP

SilicDnix

3-117

IBI

matched dual
n-channel JFET
designed for • • •

•

H

Siliconix

Performance Curves NZP-D, NNZ
See Section 4
.
BENEFITS

Wideband DiHerential
Amplifiers

• High Gain through 100 MHz
9fs = 4500 ",mho Minimum
• Matching Characteristics Specified

TO-7B
So. Section 6

ABSOLUTE MAXIMUM RATINGS (25°C)
Gate-Drain or Gate-Source Voltage ........•...... -25 V
Gate Current ...•....•.................•.... 50mA
Device Dissipation (Each Side). T A = 85°C
(Derate 3.85 mWrC) .......•.•....•.....•. 250 mW
Total Device Dissipation, T A = 85°C
(Derate 7.7 mWrC) ........ '..........•.... 500 mW
Storage Temperature Range .....••..•... -65 to + 200°C
Lead Temperature
(1/16" from case for 10 seconds) ...........•...300°C

G,

~~
s,

S:!

c
G1

G2

82

405
D2
sO
0&
0
0 G2
20
7

0,

,0

A ~,
_I D,

s,

BottomViow

ELECTRICAL CHARACTERISTICS (250 unless otherwise noted)
Characteristic
1

"2
-3
"4
"5

S
T
A
T
I
C

6

-;
8

-9

0

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

VGS(off)

Gate.source Cutoff Voltage

lOSS

Saturation Drain Current (Note 1)

10

Max

Unit

-100

pA

-250

nA

-25
-1

-5

5

40

4500

10,000

VOS=10V,lo=5mA

1= 1 kHz

4500

10,000

VoG = 10 V,lo = 5 mA

1= 100 MHz

Common-Source Output Conductance

200

90S

Common-Source Output Conductance

200

Common-Source Reverse Transfer Capacitance

1.2

12

en

Equivalent Short Circuit Input Noise Voltage

30

13 M
A
T
14

!.oSSl
loSS2

Saturation Drain Current Ratio (Notes 1 and 2)

C

IvGS1-VGS2 1

Differential Gate-Source Voltage

H
I

91s1

N 91$2
16 G 90s1-9os2 1

Transconductance Ratio (Note 2)

5

0.85

VoS = 10 V, 10 = 5 mA

1= 1 kHz
1= 100 MHz

pF

VoG= 10V,10= 5mA

!JY
VFiZ

1
100

0.85

JLmho

1= 1 MHz
1= 10kHz

VoS = 10V, VGS = 0
mV
VoG=10V.10=5mA

1

I-

1= 1 kHz
Oifferential Output Conductance

20

JLmho

NZF-D, NNZ

NOTES:
1. Pulse test required. pulse width = 300 JLS, duty cycle .. 30%.
2. Assumes smaller value in numerator.

3-118

= 10 V, 10 = 1 nA

VoS = 10V, VGS= 0

Common-Source r orward Transconductance

Common-Source Input Capacitance

15

VoS
mA

I 15ttC

IG=-lI'A,VoS=O

Common-Source Forward Transconductance

C1SS

'-

VGS=-15V.VoS=0

91s

Cr•s

-

V

Test Conditions

9fs

V 90S

N
A
M
I'll
._ C

Min

SUiccnix

n-channel JFETs
designed for • • •

c

H

Siliconix

Performance Curves NVA
See Section 4

Switches
• Analog
• Commutators
• Choppers

~
~

BENEFITS

•

Ultra-Low Insertion Loss
rOS(on) <3.0n (U290)

•

High Off-Isolation
10(off) <1 nA

8c

ABSOLUTE MAXIMUM RATINGS (25°C)
TO·52

Sa. Section 6

Reverse Gate-Drain or Gate-Source Voltage ......... -30 V
Gate Current .............................. 100mA
Drain Current
1.5 A
Total Device Dissipation at 25°C
Free-Air Temperature (Note 1) ............... 500 mW
Storage Temperature Range .............. -65 to +200°C
Lead Temperature
( 1/16" from case for 10 seconds) .............. 300°C

11\

...............................

M

.~:

"I
0

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic
1

-

,23

1-; S

-5

'6

-;

-

T
A
T
I
C

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

VGS(off)

Gate-Source Cutoff Voltage

10(off)

8

9
10

IGSS

0

U290

Min

U291
Max

Min

Max

-1

-1

nA

-1

-1

J.lA

-30

Dram Cutoff Current

-10

-1.5

-4.5
nA

1

1

J.lA

30

70

mV

VGS=O,10=10mA

mA

VOS=10V,VGS=0

lOSS

(Note 2)

rOS(on)

Static Dram-Source ON
Resistance

10

3.0

2

7

n

VGS = 0 V,IO = 10 mA

rds(on)

Drain-Source ON ReSistance

1.0

3.0

2

7

n

VGS=O,IO=O

500

200

CSGO

Source-Gate OFF Capacitance

30

30

12

COGO

Dram-Gate OFF Capacitance

30

30

CSG+COG

Source Gate Plus Dram Gate
On Capacitance

160

160

14

!d(on)

Turh-ON Delay Time

15

15

15

i-

17

VOS = 5 V, VGS = -10 V

Drain-Source ON Voltage

11

16

VOS = 15 V, 10 = 3 nA

1

VOS(on)

Saturation Drain Current

150·C

IG = -1 J.lA, VOS = 0

1

V
N
A
M
I
13 C

-

VGS = -15 V, VOS = 0

-30
V

-4

Test Conditions

Unit

I

150·C

f = 1 kHz

VSG = 15 V, 10 = 0
pF

VOG=15V,IS=0
VOS~O,

f= 1 MHz

VGS = 0

VOO = 1.5 V, 10(on) =:30 mA, RL = 50n,
VGS(on) = 0 V,

S

tr

Rise Time

20

20

W

td(off)

Turn·OFF Delay Time

15

15

V GS(off) = -12 V (U290)

tf

Fall Time

20

20

VGS(off) = - 7 V (U291)

ns

NVA

NOTES:
1. Derate linearly at the rate of 4.0 mW/'C.
2. Pulse test required pulsewidth 300 J.ls, duty cycle <:; 3%.

Siliconix

3-119

-

p-channel JFETs
designed for • • •

H

Siliconix

Performance Curves
PSA/PSB/PSC
See Section 4

Switches
• Analog
• Commutators
• Choppers

BENEFITS
I nsertion Loss
• LowrDSlon)
< 85 n (U304)

Off-Isolation
• HighID(off)
< 500 pA

ABSOLUTE MAXIMUM RATINGS (25°C)

U

TO-18
See Section 6

;rr

~

Reverse Gate-Drain or Gate-Source Voltage (Note 1) .. 30V
Gate Current ............................... 50mA
Total Device Dissipation, Free-Air
(Derate 2.8 mW/oC) ....................... 350mW
Storage Temperature Range .............. -65 to +200°C
Lead Temperature
(1/16" from case for 60 seconds)
. 300°C

.~:

............

D

G~C

•

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic
1

12"
3'

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

~ ::

VGSlnffl

Gate-Source Cutoff Voltage

T
5 A
T
I

VOS(on)

Drain-Source ON Voltage

lOSS

SaturatIon Drain Current (Note 2)

-

6'

-7
-8

C

U304
Min

U305

Max

U306

Max

Min

Max

Unit

500

500

500

pA

10

1.0

1.0

p.A

30
5

Min

30

30

10

3

6

1

1

-30

-90

-15

-60

-5

125°C

VDS - -15 V.ID = -1,.A

-0.6

-0.8

I

VGS = 20 V, VOS = 0
IG= 1 /lA, VOS=O

V
-1.3

Test Conditions

VGS = 0, 10 = -15 mA (U304),
10 = -7 rnA (U305),
10 = -3 mA (U306)

-25

mA

VOS=-15V,VGS=0

-500

-500

-500

pA

VOS = -15 V, VGS = 12 V (U304),
VGS = 7 V (U305),
125"C
VGS = 5 V (U306)

I o(off)

Drain Cutoff Current
-1.0

-1.0

-1.0

p.A

"9

'OS (on)

Static Dram-Source ON Resistance

B5

110

175

n

VGS=OV,IO=-l mA

10

'ds(on)

Drain-Source ON ReSistance

85

110

175

n

VGS=OV,IO=O

CISS

Common-Source Input Capacitance

27

27

27

7

7

7

22:
12

0

Y
N

13

S

14
15

W
I
T

1e Hc

Crss

Common-Source Reverse Transfer

td(on)

Turn-ON Delay Time

20

25

25

t,

Rise Time

15

25

35

teI(off)

Turn-OFF Delay Time

10

15

20

tf

Fall Time

25

40

60

Capacitance

pF

VOS - 0, VGS = 12 V (U304)
VGS = 7 V (U305),
VGS = 5 V (U306)

VOO
ns

VGSloff)

RL
VGS(on)
1010n)

U304
-10V

U305
-6V

f= 1 MHz

U306
-6V

12V

7V

5V

580n

743U

1800n

0
-15mA

0
-7 rnA

0
-3mA

PSA/PSB/PSC

NOTES:
1. Due to symmetrical geometry these Units may be operated with
source and drain leads Interchanged.
2. Pulse test pulsewldth = 300 p.s, duty cycle .. 3%.

3-120

f = 1 kHz

VOS=-15V,VGS=0

Siliconix

n-channel JFETs
designed for • • •

H

Siliconix

Performance Curves NZB
See Section 4

Amplifiers
• VHF
End High Sensitivity
• Front
Amplifiers
Osci Ilators
• Mixers
•

BENEFITS
• I ndustry Standard
• High Power Gain
16 dB at 105 MHz, Common-Gate
11 dB at 450 MHz, Common-Gate
Low Noise
2.7 dB Noise Figure at 450 MHz
• Wide Dynamic Range
Greater than 100 dB
• 75 n Input Match Common Gate

•

ABSOLUTE MAXIMUM RATINGS (25°C)
TO·52

Gate-Drain or Gate-Source Voltage ............... -25 V
Gate Current ............................... 20mA
Total Power Dissipation at T A = 25°C
500mW
Power Derating to 1500 C .................. 4.0 mWrC
Storage Temperature Range .............. -65 to +[209"6
Lead Temperature
(1/16" from case for 10 seconds) .............. 300°C

See SectiDn 6

11

..........

.~:

"' !H

s

0

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic

1...2.

IGSS

2

I- S
3
4

T

15

T
I
C

Voltage

Gate-Source Cutoff Voltage

16

VGS(I)

7

1-

gIg
0
y

8
gog
1_ N
9

IW

111

1..2.!.
13
1I~

A Cgd
M
Cgs
I
C
-en

I

11'7
118
1-

Min

U310
Typ Max
-150

pA

-150

-150

-150

nA

-25

V

VGS
VOS

= -15 V,
=0

TA=125°C

IG=-II'A,VOS=O

-1.0

-4.0

-2.5

~.O

12

60

12

30

24

60

mA

VOS= 10V,VGS=0

1.0

V

IG=10mA,VOS=0

Common-Gate Forward
Transconductance (Note 1)

1.0
10

1.0
10

17

Common-Gate Output

10

17

VOS=10V,
10=10mA

Drain-Gate Capacitance

2.5

2.5

2.5

Gate-Source Capacitance

5.0

5.0

5.0

Equivalent Short Circuit
Input NOise Voltage

10

10

10

15

15

15

14

14

14

0.18

0.18

0.18

0.32

0.32

14

16

14

16

14

16

Gam (Note 2)

10

11

10

11

10

11

NOise Figure

pF
nV

~

VGS=-10V,
1= 1 MHz
VOS=10V
VOS = 10V,
10=10mA

1=100Hz
1= 105 MHz
1= 450 MHz
1=105MHz

mmho

0.32

Common-Gate Power

19

1=1 kHz

250 .umho

250

Conductance

VOS = 10 V, 10 = 1 nA

mmho

17

250

90g

Test Conditions

Unit

-150

-25

Gate-Source Forward
Voltage

Common-Gate Output
Conductance

NF

Max

~.O

(Note 1)

Common-Gate Forward
Transconductance

E Gpg
Q

U309
Typ

-1.0

SaturatIOn Drain Current

gIg

R

Min

-150

-25

H

I~F
16

Gate-Source Breakdown

VGS(oll)
lOSS

U308
Typ Max

Gate Reverse Current

BVGSS

1- A

Min

VOS=10V,
10=10mA

1= 450 MHz
1= 105MHz
1= 450 MHz

1.5

20

15

2.0

1.5

2.0

2.7

3.5

2.7

3.5

2.7

3.5

dB

1=105MHz
1= 450 MHz

NZB

NOTES:

1. Pulse test duration = 2 ms
2. Gain (Gpgl measured at optimum input noise match.

Siliconix

3-121

n-channel JFET
designed for • • •

H

Siliconix

-----

Performance Curves NZB
See Section 4

• VHF Amplifiers
• Oscillators
• Mixers

BENEFITS
• High Power Gain
16 dB Typ @ 105 MHz, CommonGate
11 dB Typ @ 450 MHz, CommonGate
• Low Noise Figure
1.5 dB Typ@ 105 MHz
2.7 dB Typ @ 450 MHz
• Wide Dynamic Range-Greater than
100 dB

ABSOLUTE MAXIMUM RATINGS (25°C)

TO-72
See Section 6

Gate-Drain or Gate-Source Voltage ............... -25 V
Gate Current ............................... 10mA
Total Device Dissipation (Derate 1.7 mWrC) ..... 300 mW
Storage Temperature Range .............. -65 to +200°C
Lead Temperature
(1/16" from case for 10 seconds)
300°C

o~:

.............

~

~

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Characteristic
1

12
1- S
3 T
1- A
4 T

I-I

5 C

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

Min

Typ

Max

pA

-150

nA

-25
-6

20

no

Saturation Drain Current (Note 1)

VGS(f)

Gate·Source Forward Voltage

7

9fg

Common-Gate Forward Transconductance (Note 1)

B 0

gog

Common-Gate Output Conductance

Cgd

Gate·Dral" Capacitance

2.5

Cgs

Gate·Source Capacitance

5.0

-Y
9 N
'10

150·C

VOS= 10V,IO= 1 nA

1
10.000

"If!.

VDS=1QV,'lGS=O

V

IG = 1 rnA, VOS = 0

17,000
pmho

VOS = 10 V, 10 = 10 mA

if = 1 kHz

pF

VOG= 10V,IO= 5mA

if= 1 MHz

250

NZB

NOTE:
1. Pulse test duration = 2 ms.

3-122

VGS=-15V.VOS=0
IG = -lpA, VOS = 0

-1

lOSS

-

Test Condition.

V
VGS(off) Gate-Source Cutoff Voltage

6

i-

Unit

-150

Siliconix

-

n-channel JFETs
designed for • • •

•
•

H

Siliconix
-----

- ---

Performance Curves NIP
See Section 4

VHF BuRer Amplifiers
IF Amplifiers

W
N

•

• HighgfsGain
= 120,000 ,umho Typical
Wide
Dynamic
Range
•
• Low Intermodulation Distortion
TO-39

c

W
N
N

~

See Section 6

Gate·Drain or Gate·Source Voltage ................ -25 V
Gate Current ............................... 100 rnA
Total Device Dissipation (25°C Case Temperature) ...... 3 W
Power Derating (to 150°C) .................. 24 mWrC
Storage Temperature Range .............. -55 to +150°C
Operating Temperature Range ............. -55 to +150°C
Lead Temperature
(1/16" from case for 10 seconds) ............... 300°C

N

o
c

BENEFITS

ABSOLUTE MAXIMUM RATINGS (2S0C)

cW

l

.~:

s

0

ELECTRICAL CHARACTERISTICS (2S0C unless otherwise noted)
Characteristic
I

1-

I~ sT

I";4
15
I6

A
T
I

e

I]
8

1-

U320
Min

IGSS

Gate Reverse Current (Note 1)

VGSloffl
BVGSS

Gate-Source Cutoff Voltage
Gate-Source Breakdown Voltage

-25

lOSS

Saturation Drain Current (Note 21

100

VGS(I)

Gate-Source Forward Voltage

'OS(on)

Drain-Source ON ReSistance

9fs

Common-Source Forward

Transconductance (Note 21

Typ

-2

75

U322

U321
Max

Min

Typ

Max

Max
-3

nA

-0 5
-10

-0 5
-4

-0.5

pA

-1

-3

-10

-25

80

250

200

700

rest Conditions

Umt

-3

500

Common-Source Input

Typ

-3

-25

120

M,n

V
mA

I

VGS=-15V VoS=OV
'
IT = 100·C
VoS-5V, 10= 1 mA
IG=-lpA,VoS=OV
VOS=15V,VGS-OV

1

1

1

V

IG = 1 mA, VoS = a V

10

11

8

n

VGS -

200

75

120

200

75

130

200

mmhos

a V, 10 -10 mA

VOS = 15 V, VGS =

0
V
N
10
A
111 M
I

C1SS

Cas

Gate-Source Capacitance

12

12

12

VGS=-10V,10-0

I':'::

Cgd

Gate-Drain Capacitance

12

12

12

VGO=-10V,IS=0

13

-en

EqUivalent Short CirCUit
Input NOise Voltage

2

2

2

14

gig

Common Gate Forward
Transconductance

55

55

55

9

I-

112 e

115

1-

Crss

H
I
G g,g
H

Capacitance

30

30

30

Common-Source Reverse
Transfer Capacitance

15

15

15

Commen-Gate Input
Conductance

1-'-'- R

GPS

Common-Gate Output
Conductance
Power Gain (Note 3)

*

Ft
NF

Gam-Bandwidth (Note 4)
NOise Figure (Note 3)

16

117

F
E

Q

909

56

56

56

05

0.5

05

9
400

2.5

pF

nV

~

mmho

9

400

MHz

25

dB

Silicanix

VGS = -10 V, VOS = a V

VOS = 5 V, 10 = 10 mA

1=1 kHz

1= 1 MHz

1=1 kHz

VoG = 20 V, 10 = 25 mA 1= 50MHz

dB

9

400
25

NOTES:
1. ApprOXimately doubles for every 10°C Increase," TA
2. Pulse test duration = 2 ms.
3. NOise figure ~SSB) and power gain measured In cIrcuIt shown," FIgure 1
4. Computed as 9fs/Crss.

aV

VOS= 15V,VGS=OV
ValL= 20 V,!JL - 25 mA.11

= 30 MHz
NIP

3-123

-

H
quad-ring demodulator
designed for ...
Performance Curves NZB
See Section 4

Siliconix

Double-Balanced Mixers
• VHF
• Analog Multipliers

BENEFITS
•
•
•
•

ABSOLUTE MAXIMUM RATINGS (25°C)

High IMD Intercept Point
Conversion Gain
High 1 dB Compression
Suitable for PC Board
Construction

Gate-Drain or Gate-Source Voltage .............. -25V
Gate Current. . . . . . . .. . . . . . . . . . . ... . . . . . .. . . ... 25 mA
Total Continuous Power Dissipation
at (or Below) 25°C Free Air Temperature
(Derate 8.0 mWrC to 150°C ................... . 1W
Storage Temperature Range .......... . -65 to +150°C
Lead Temperature
(1/16" from case for 10 seconds) .............. 300°C

PIN 2 0,. 04

.,
Bottom View

FEATURES

• 4 Matched U310 JFETS
• Low Turn-on Resistance
• High Transductance
Reference Application Note AN72-1

+VGS

Ll,12_13"Hy
Cl-001,.F
C2 C1-o10",F
C3 C4-30pF

+VDD

C5,C8-&8pF

Contact factory for Application Note AN 73-4.

ELECTRICAL CHARACTERISTICS (25'C unless otherwise noted)
U350

Characteristic

,

IGSS

2

-S
3 T BVGSS
-A
T VGS{off)
I
C
5
VGS(f)

•
-

•

.
7

-

•

0
y

N
A
_M

~~

"

,.

Voltage
Gate-Source Cutoff
Voltage

-2

Test Conditions

Unit
nA

VGS = -15V. VOS = 0

!,A

(Note 1)

-6

TA - ..L125G C

IG

= -1 p.A, VOS = 0

10

= 1 nA. Vas'"

10 V (Note 1)

IG = 1 mA VOS "" 0 (Note 1)

Voltage
Dram Saturation Current

2.

Common-Source Forward
Transconductance

'0

go,

Common-Source Output
Conductance

Cg ,

Gate-Source Capacitance

Cgd

Dram Gate Capacitance

Rds(on)

Dram-Source ON
ReSistance

60

,.

'50

rnA

."
pF

50

90

"
dB

NOIse Figure

lOSS/lOSS

VOS"" 10 V,
10 = 10mA

f = 1 kHz (Note 1)

VGS"" -10V,IO - 0
VOO = -10V,IS

(Conversion Gam)

Saturation Drain Current
RatiO

VOS"" 15 V, VGS = 0 (Notes 1 and 2)

mil

25

NF

=0

C grsfgls

17

VGS = 0, 10 = 0

f= 1 kHz

VOS - 20 V,
VGS
YzVOS(off).
RO"" 1.700 n

f = 100 MHz (Note 3)

=

09

'0

VOS"" 15 V. VGS "" 0 (Note 2)

VOS"" 15 V, 10 "" 1 nA

gas/gas

09

'0

Common-Source Forward
Transconductance

09

, 0

Differential Output
Conductance

09

'0

VOS'" 15V, 10 '" 10 rnA

Other gate terminal clamped to -8 V

2 Pulse test PW 300 ~sec DC "" 3%

Siliconix

f '" 1 kHz

NZB

NOTES

3-124

f"" 1 MHz (Note 1)

Gate-Source Cutoff

_H

,

-,

Gate-Source Forward

M
'5 A VGS{off}IVGS(off) Voltage RatiO
_T

'6

Max

-25

gls

-

TVp

Gate Reverse Current
Gate-Source Breakdown

lOSS

12 H G,

13 F

Min

3 See Figure 1

H

monolithic dual
n-channel JFETs
designed for • • •

Siliconix

Performance Curves NNR
See Section 4
Minimum System Error and Calibra• tion

•
•

•
•

5 mV Offset Maximum (U401)
95 dB Minimum CMRR (U401-04)
Low Drift with Temperature
10 Ilvrc Maximum (U401. 02)
Operates from Low Power Supply
Voltages
VGS(off) < 2.5 V
Simplifies Amplifier Design
Output Conductance < 2 Ilmho
Low Noise
en = 6 nV/y'Hz at 10 Hz Typical
TO-71

~p.:_oo.
0,

50V
10mA

G2

51

U4Ql

M,n

BVGSS

Gate-Source Breakdown
Voltage

'GSS

Gate AeverseCurrent
INote 1)

3

VGSlcff)

Gate Source Cutoff
Voltage

4

~ VGSlon)

1

12

1-

I-~
I-

I

5 C lOSS

1-

I~

'G

1-

(Note 21

G~te·G~te

Breakdown

eVG, - G2

9

",

Common Source Forward
Transconductance (Note 2)

'.,

Common Source Output
Conductance

110

1-

11 ~
I- N
12 ~

1-

52

°1

~

17

~

,

U404

M..

Moo

-50

-25

-50
-25

-5

"'X

M,n
-50

-5

-25

M,n

"'X

-50

-25

-2,5

U406

U405

M..

-25
-5

-25

-25
-5

UHlt

Test Conditions

V

VOS=O,IG=-lIJ,A

pA

VOS=O. VGS=-30V

-25

VOS=15V,'O .. lnA
V

-23
05

-23

-23

-23

-23

-23

VeG = 15 V, '0 = 200lJ,A

100

rnA

VOS=10V,VGS=O

-15

-15

-15

-15

-15

-15

pA

VOG=15V.

-10

-10

-10

-10

-10

-10

nA

'0 = 200IJ,A

V

Ves = 0, VGS = O,IG" ±II1A

100

±50

05

100

±50

05

100

05

±50

±50

2000 7000

2000 7000

20

20

2000

100

7000

2000

20

05

100

±50
7000

2000

05

±50

7000

2000 7000

20

20

20

VOS'" 10V,
VGS"'O

I

TA

IEII

"125~C

f= 1 kHz

I1mho

gas

20

Common..source Input
Capacitance

80

80

80

80

80

80

c",

Common Source Reverse
Transfer Capacitance

30

30

30

30

30

30

'N

EqulvalentShort,Clrcult
Input NOise Voltage

20

20

20

20

20

20

CMRR

Common Mode RejectIOn
RatiO (Note 3)

IVGSI - VGS21

OlfferentlalGate-Source
Voltage

1000

2000

1000

2000

1000

2000

1000 2000

1000

2000

1000

2000
f= 1 kHz

I,-T
1-

M,n

-25
-5

G~~2

Bottom View

Common Source Forward
Transconductance

1-

,.

Voltage

-25

07 G2

,0

Common Source Output
Conductance

1
13 C CISS

15

-5

'0

5,

U403

"'X

,,~.

G, 30 0 506 °2

500mW
-65 to 200°C

gfs

114

-25

Gate CurrentlNote 11

8

Moo
-50

-50

Gate-Source
Voltage lonl
Saturation Dram Current

U402

M..

52

300mW

ELECTRICAL CHARACTERISTICS (@ 25°C unless otherwise noted)
Characteristic

18 N A.lVGSl - VGS21

--I1-T--

Gate·Source Voltage Differ·
entlal Onft(Note 4)

-

BENEFITS

Noise FEY Input
• Low
Amplifiers
and Medium Frequency
• Low
Amplifiers
Impedance Converters
• Precision
• AmplifiersInstrumentation
• Comparators
ABSOLUTE MAXIMUM RATINGS (25°C)
Gate-Drain or Gate-Source Voltage
Forward Gate Current.
Device Dissipation (each side)
@ T A = 85° C derate 2.6 mW/" C
Total Device Dissipation
@ T A = 85°C (derate 5 mW/"C)
Storage Temperature Range

c
~
o

20

20

20

20

20
VeG = 15V,
10 = 200l1A

pF

95

95

95

9S

90

nV
h_

VeG = 10V, 10 = 200l1A

10

15

20

40

mV

10

10

25

25

40

80

"vfc

[jilv::,~eGS2J

f= 10Hz

VOG = 10 to 20 V, 10" 2oo,..A

10

3 CMRR = 2010910

Ves= 15V,
VGS=O

dB

5

NOTES
1 ApprOXimately doubles for every 100 e Increase In TA 2 Pulse test duration" 3OOl1s, duty cycle" 3%

f"'IMHz

,avoe '" 10 V

VOG-IOV,
10 = 200J,lA

T A = -55°C, TS· +25°C
TC" +125°C

NNR

4 Measured at and pOints, TA, Ta and TC

3-125

monolithic dual
n-channel JFETs

H

.. designed for •••
...

Siliconix

lit

Performance Curves NQP
See Section 4

::)

o

::)

BENEFITS

• FET Input Amplifiers
• Low and Medium Frequency
Amplifiers
• Impedance Converters
• Precision Instrumentation
Amplifiers
• Comparators

• Low Cost
• Minimum System ~rror and Calibration
10 mV Offset Maximum (U410)
70 dB Minimum CMRR (U410)
• Low Drift with Temperature
10 IlV/"C Maximum (U410)
• Simplifies Amplifier Design
Low Output Conductance
TO-71

See Section 6

ABSOLUTE MAXIMUM RATINGS (25°C)
Gate-To-Gate Voltage _........................ ±40 V
Gate-Drain or Gate-Source Voltage ............... -40 V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50 mA
Total Package Dissipation (25°C Free-Air) _...... _375 mW
Power Derating ........................... 3.0 mW;oC
Storage Temperature Range .............. -65 to +150°C
Lead Temperature (1/16" from case for 10 seconds) .. 300°C

G, 0'
02

J

W
~

7

0, .,

ci,:D2

Bottom View

.

0, "

ELECTRICAL CHARACTERISTICS (2.5°C unless othilrwise noted)
Characteristic
1

IGSS

Gate Reverse Current
(Note 1)

VGS(off)

Gate-Source Cutoff
Voltage

12

1_ 5

T
3 A BVGSS
I-T
4 I lOSS
C

-5

-

U410

Min

Gate-Source Voltage

Min

Typ

U412
Max

Min

Typ

"200
-35

-0.5

Max
"200

Unit
pA

-35

-0.5

Test Conditions
VOS = 0, VGS = -30 V
VOS=20V,IO= 1 nA

V
-40

-40

-40

VnltAgp

Gate Current (Note 1)

-35

-0.5

Saturation Drain Current
(Note 2)

IG

U411
Max
"200

Gate-Source Breakdown

VGS

Typ

05

50

0.5

5.0

VOS = 0 V,IG = -lpA

0.5

"200

50

mA

"200

pA

-02

-3.0

V

4,000 1,000

4,000 1.000

4,000

1,200

1,200

1,200

"200

VOS = 20V. VGS= OV

VOG = 20V,I0 = 200llA
6
7
9f.

Ii

!i'o
loy

90.

Common-Source Forward

Transconductance

-02

-3.0

1,000
600

Common-Source Output

Conductance

-N
11 ~ CISS
-I
12 C C,..

-13

en

~

Common-Source Input

Capacitance
Common-Source Reverse
Transfer Capacitance

600

600

20

20

20

5

5

5

45

45

4.5

12

1.2

1.2

VOS=20V.VGS=0 V
~mho

VOS=20V,VGS=OV

f= 1 MHz

!lll.

VOS = 20 V,IO = 200llA

f'l00H-

VOG = 20 V,IO = 200llA

50

50

50

10

20

40

mV

10

25

80

pVrC

NOTES:
1. Approximately doubles for every lOoe Increase In TA
2. Pulse test duration = 300 /lSec, duty cycle'" 3%.
3. Measured at end potnts, T A and TB.

80

70

f = 1 kHz

pF

Differential Gate-Source
Voltage

80

VOG = 20 V,IO = 200llA
VOS= 20V. VGS - OV
VOG = 20 V,IO = 200llA

Equivalent Short-Circuit
Input NOise Voltage

lvGS1-VGS2)
14
-T
alvGS1-VGS2 1 Gate-Source
15 ~
Differential Dnft (Note 3)
AT
f--I
Common-Mode ReJection
16 ~ CMRA
Ratio (Note 4)

3-126

-30

-0.2

vHZ

dB

VOG = 20V,I0 = 200llA
TA = 25°C to TB = 85°C
VOO = 10 V to VOO = 20 V
10 = 200IlA

NQP
4 CMAR = 20log10 [

avOO

d,aVOO = 10 V.

.el.IvGS1-VGS2)

Siliconix

monolithic dual
n-channel JFETs
designed for

H

Performance Curves
See Section 4
BENEFITS

• • •

Electrometers
Impedance Converters

Soo Section 6

Gate-to-Gate Voltage ......................... ±40 V
Gate-Drain or Gate-Source Voltage ........... -40 V
Gate Current .................•.•............ 10 mA
Device Dissipation (Each Side). T A = 25°C
(Derate 3,2 mW/oC to 150°C) ............. 400 mW
Total Device Dissipation. T A = 25°C
(Derate 6.0 mW/oC to 150°C) ....•........ 750 mW
Storage Temperature Range ........ -65°C to +150°C

G,

~~
5,

c
G,

T

I-A
4 T
I
I---;-c

U421-3

U424·6

Min Typ Max

Min Typ Max

I6
17

Gate-Source BreakdoWn Voltage

-40 -60

-40 -60

BVG1G2

Gate-Gate Breakdown Voltage

±40

±40

IGSS

Gate Reverse Current (Note 1)

VGS{off)

Gate-Source Cutoff Voltage

VGS

Gate-Source Voltage

lOSS

Saturation Drain Current

60

0.5
500

-2.0 -0.4

-3.0

-1.8

-2.9

Test Conditions

IG=-lIlA,VOS=O

pA
nA

T = +25°C
T = +125°C

VGS = -20 V, VOS = 0

pA

T=+2s"C
T=+12SoC

VOG = 10 V,IO = 30llA

VOS = 10 V, 10 = 1 nA

V

60

800

1500 300

50C

gf,

Common-Source Forward Transconductance

go,

Common-Source Output Conductance

lla°

10

10

Ciss

Common-Source Input Capacitance

3.0

3.0

300

0(', ~,

G2

'

Bottom View

30
30

10
25
250

1000

°2

IG = -lilA, 10 = 0, IS = 0

10

-0.4

o~

Unit

8
19

I-V
11 N Crss
I_A
12 M !If,
I-I
13 C gos
1-

~o

V

Gate Operating Current (Note 1)

5,
4 05

5,

BVGSS

IG

G2

82

0, '0 10

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)

1
I2
I3 S

VOG = 10 V, 10 = 30llA
VOS= 10V, VGS=O

IlA

VOS=10V,VGS=0
pF

Common-Source Reverse Transfer Capacitance

1.5
120

f= 1 MHz

1.5

350 120

350

3.0

3.0

f= 1 kHz

Illl
Common-Source Output Conductance

14

en

I15

Equivalent Short Circuit Input
NOise Voltage

NF

Noise Figure

20
10

70

20
10

1.0
U421,4

Characteristic

IEII

f= 1 kHz

Illl

Common-Source Forward Transconductance

70

VOG = 10 V,lo = 30jlA
nVA/Hz

1.0

U422,5

If

d8

U423,6

=

10 Hz

f= 10 Hz
f= 1 kHz
RG = 10M n

Test Conditions

Min Typ Max Min Typ Max Min Typ Max Unit
16 M IVGSl - VGS21 Differential Gate-Source Voltage
I-A
Differential Gate-Source Voltage
17 T IVGS1 - VGS21
liT
Change With Temperature(Note 2)
C
I l a H CMRR
Common Mode Rejection Ratio
90
{Note 3)
NOTES.
1. Approximately doubles for every 1 ±0.1 volts, the VCR
FET characteristic has noticeable curvature.
This series of junction FETs is intended for applications
where the drain-source voltage is a low-level a-c signal with
no doc component. Thus the FET operating point will
swing symmetrically around VOS = O. In the first quadrant,
signal distortion depends on what extent the FET output
characteristic deviates from a straight line or linear relation.
Besides the linearity problem in the third quadrant, when
VGS is near zero and vds > 0.5 volt rms, the gate-channel
junction will become f.orward biased and cause additional
curvature in the characteristic. Also, whenever the gate becomes forward biased due to any combination of VGS and
vds, it ceases to be a high-impedance control terminal for
the VCR.
Fig. 3 presents a normalized plot of ros versus normalized
VGS where VGS(off) is defined as that value of VGS at
IO/IOSS = 0.001. The dynamic range of ros is shown as
greater than 100:1. For best control of ros the normalized
_VGS should lie between 0 and 0.8 VGS(off) because as

0
VGS"O

5

vc~!J"--~

.....

t--

,
,
0

5

vGs·o

~"

VCA'N t--I'i

VCR4N

--'\

vJAiN'

,
,
"

.lJJ

,,'

'dl!ONI

",

III

DRAIN-SOURCE ON RESISTANCE (ohm"

-

",

Fig. 4

Fig. 5

For further information on using FETs as voltage·variable
resistors, consult Siliconix Application Note AN73·1.

* L. Evans; "Biasing FETs for Zero OC Orift"; Electro Technology, August 1964.

3-133

..z voltage-controlled

H

Silicanix

~

~

resistor FETs
designed for • • •
Small Signal Attenuators
• Filters
• Amplifier Gain Control
• Oscillator Amplitude Control
•
TO-71

See Section 6

G,

~~
S1

G2

S2

S2

° D2
° G2
G, 0 3 2' 6,0
D, ° 2,

ABSOLUTE MAXIMUM RATING (25°C)

s,

Gate-Drain or Gate-Source Voltage ....... _......... 25 V
Gate Current ................................ 10 mA
Total Device Dissipation at T A = 25°C
(Derate at 2.0 mW/oC to 175°C) .............. 300 mW
Storage Temperature Range .............. -55 to +175°C

0'

Bottom View

,A

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)

Characteristic

VCR11N
Min
Max

Unit

-0 2

nA

Test Conditions

1

IGSS

Gate Reverse Current

2

BVGSS

Gate-Source Breakdown Voltage

3

VGS(off)

Gate-Source Cutoff Voltage

-B

-12

4

rds(on)

Drain Source ON Resistance

100

200

5

Cd go

Drain-Gate Capacitance

B

6

Csgo

Source-Gate Capacitance

B

VGS= -10V,ID= 0

7

rosml%
rOsmax

95

1

VOS= 100mV

rOSl - 200l!

95

1

VGSl =VGS2

r[>SI = 2kl!

-25

Note
1 VGS1

3-134

V

n
pF

VGS=-15V,VDS=0
IG = -lilA, VDS = 0
ID= lilA, VDS= 10V
VGS= O,ID = 0

f = 1 kHz

VGD=-10V,IS=0

f = 1 MHz

NSH*
+ Control Voltage necessary to force rOS. to 200n or 21<0

'Contact factory for geometry information.

Siliconix

Geometry mill

Siliconix

c

Useful JFET Parameter
Relationships (Approximate)

lc

""'II

....

III

Bulk & Junction Leakage Current
vs Ambient Temperature

On Resistance
vs Ambient Temperature

W

19

~105~~~~~~+=~~~==~
>10"-4-~-+~f--+-4--f--+-?~

~

r

~103f--4-~-+~f--+-4-~1/~__~

~10'r-~~-+~r-~L'~--r-~-r-i

a:

1 f--4-~-+-/-k--t--t--r-4-~-i

a:

B ~tj2~=l==l=tt=+=l:=j

/

17

>

~ 15

~

13

~
w
>

/

g

09

a:

07

p

05

~

~

10"JL-.L...L-L---1__L-.L...L-L---1--l
-75

...J

-25

25

75

125

AMBIENT TEMPERATURE

03
-75

175

1.2

,"

08

a:

3
~

1/

04

o2
-25

25

75

125

-75

175

AMBIENT TEMPERATURE (OCI

(OC)

..
.,
f
..-.

ii"

" '"

w 06

;l

a3
~

14

~ 10

11

~

_#

~

'3
~

~ 16

~

~

10'1

~ 10- 2

18

w

"

~,o2f--4-~-+~f--+-47~-+--~

~

Dram Current and Transconductance
vs Ambient Temperature

o~

75
125
25
AMBIENT TEMPERATURE ("Cl*

fit

-.

175

-25

~

-":J>
""a
><
fit

Typical rDS(on)
vs Normalized Gate Source
Cutoff Voltage

Saturation Current
vs Cutoff Voltage
MAX

MAX
14

"

w

o

w>

Z

e

12

>0
j:::u

o

wCl

ow

8

"';::

.... w

6

.....

"-

o

~4!

4

o

on

z:O:

Z

"'-

i!:'"

'\.

on~

0:>

"

Z

0:>

wZ

"-

~

:'lon 10

o

0:

ZO

"

0 ....

rOSlon)

I--

-+-

~
~

MIN
-, 0

-08

-06

-04

-02

~

!"-

/

~

0:

"

~

\
........

/ /
/ /
/ /'

it

1\

on
on
on

9

MIN

MIN

MAX

-.3

LL

..-

1/ /

o
z
o

APPROXIMATE "ON" RESISTANCE

VOS(offl (NORMALIZED)

V

a:

I........

0:

/

~
0:

a

V

~

.,? V
MIN

MAX

VGS(off) CUTOFF VOLTAGE

l1li

Saturation Current
vs ON Resistance
MAX

\\

\

ffia:
a:

\\.

~

<.J
Z

\

o
~
0:

~

"-

on
on
on

"- ."-..
f'... ........ l'-

..... ........

9

MIN

I""""
MAX

MIN
rOSlon) ON RESISTANCE

'When 10> 5

X

102

Siliconix

4-1

H

n-channel DMOS FEY
designed for " " "
•
•

190MILS
BACKSIDE - SUBSTRATE

DIESIZE~190X

Siliconix

Ultra high speed switching
High gain amphfication

BENEFITS:

•
•

TYPE

Pf.CKAGE

PRINCIPAL DEVICES

Single

TO-72

S02100E. S0211 OE
S02120E. S02130E
S02140E. S02150E

Quad

Dual 10 LlOe
16 Pm
Side Braze

S05000l, S050011
S050021

Dual 10 Line
16 Pin
Plastic

S05000N, S05001 N
S05002N

Surface Mount
SO-14

S05400CY, S05401 CY
S05402CY

Ch,p/Wafer

AvaJiable as above specifications

ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)

0004

0004

0004

0004

(0102)

;01021

(0"i021

;0;0])

Switching speed < 1 ns
Gain gfs > 10,000 "mhos

DIESIZE=350XJ50MILS
BACKSIDE ~ SUBSTRATE

PERFORMANCE CURVES (25°C unless otherwise noted)
Drain Current
vs Drain to Source Voltage

Dram to Source Resistance
vs Gate to Source Voltage

80 r-:V-:-D-S~'-:-:,.-:-V,--,--,.--,----,

70~-1--_+--~-1-~~

E

100

Leakage vs Voltage

r-"TT11Wn""T"""T---.-r--.----r-""T"---'

10-; , - , . - - , - - , - - , . - - ,

:£
108~_~_-+

«
~

~
<
~

u

~

~

30~-1--_+-i~~~1--~

5l

20~-1--~~~~-1--~

"'

':116"111
o

2

VGS

~

4

6

8

40~+-+-+-'

"g

~

5

J

vds ~ l v

30

~

z

~

~

u

25

20

II

VGS - 4V

I

vJs·lv

'0

......

80

,,6"I~

60

"'~
I

I I
12

16

40

Z

VGS - 2 V

VOS - ORAIN TO SOURCE VOLTAGE (VI

4-2

100

~

Q

20

20

25

Forward Transconductance
vs Drain Current

u

II

20

Dram to Source Resistance
vs Temperature

~

~

I,. I I

VOLTAGE (VOLTS)

u

:i

10

VGS - GATE TO SOURCE VOLTAGE (VOLTS)

VV

~

,. 1/
~
iJ
" I"' .....

z

10 10

Q

Dram Current
vs Gate to Source Voltage
V~S ~ 0 V

10 9~-+-~--~~-e~~

d

10

40

+-_~_-+

Q

z

GATE TO SOURCE VOLTAGE (VOLTS)

35

__

.

~ r-"

'::. ~

-60

-20

V

::::
~~
""k ;...

~ ~ ~ :::=:~r

)0= SmA
VBS - OV

20

60

'00

TEMPERATURE ( C)

Siliconix

140
10 - DRAIN CURRENT (mAl

PERFORMANCE CURVES (Cont'd) (25°C unless otherwise noted)
Threshold Voltage
vs Source to Substrate Voltage

Threshold Voltage vs Temperature

25

3
VBS~-10V

VBs~

2

VaS"'_TV

r-

1

VBS"'_O~

10 = lilA

I-

-L f-+f-+r-r-

~ ~r-

~
0

20

~

15

"~
0

>
0

10

~

05

i=

I"

....

V

1/

V

/'

V
V
10 -lj.1A
VGS = Vos = Vth

VGS = Vos '" Vth

-60

20

20

60

TA =25 C

100

140

lao

-10

TEMPERATURE [ C)

SOURCE TO SUBSTRATE VOLTAGE (VOL IS)

Capacitance
vs Gate to Sou rce Voltage

Common-Source Output Conductance
vs Drain Current

.............
5

........
2
1

-

""

-

-

Leakage vs Temperature

VDSO lO::±-Vas = VGS
F = 1 MHz

CI(GSt S8)

Ibo

8
5

1

t

~

JBI

12

GATE TO SOURCE VOLTAGE (VOL IS)

I~ ~

800

J"~

.J.Q~+·.:;)2
600

'//'t
':.I/'

40 0

~

g

~ IDGII
10

,

Z

C(GS+GO+GB!

C

1000

~

j

"z
~

I I
I I

- 14

TEMPERATURE ('C)

200

I-

/~ /'

~~

--"!!~
,.. ~

0

12

16

20

10 - DRAIN CURRENT (mAl

Siliconix

4-3

enhancement-type
n-channel MOSFET
designed for •••

1
L---....f----+-l

H

Siliconix

•

Audio Amplifiers

BENEFITS:

•

Analog Circuits

•

•

Digital Switching Circuits

Integrated Zener Clamp Protects the
Gate

•

Commutating Circuits

•

Normally OFF

TYPE

PACKAGE

PRINCIPAL DEVICES

Single
Single

TO-72

Ml16
Ml16CHP

Chip

ALL WMEPoSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMFTEFIS'

PERFORMANCE CURVES (25°C unless otherwise noted)
Output Characteristics

Transfer Characteristic
20

20
V BS '" 0

VGS'" lOV

.§. 16
~

~_
=>

'2

".
'-'

"

f-VGS'" Vos
Vss" 0

.....

"

II

9V=

/
J

.v

/'

6V

'"

,J

7V

C

I

o

Ii

3V

4V

/

SV

V

V

'0

10

VGS - GATE-SOURCE VOL lAGE (VOllS)

Vos - DRAIN-SOURCE VOLTAGE (VOL TS)

Forward Transconductance
vs Drain Current

Low Voltage Output
Characteristics
5000

a

2

+25~

Vss" 0
f= 1 kHz

r---

~

I

vJsJ"t

r-

/'

f-+--+-+--t-h

--r---

,/'
./

+125 C

--

- 1-- ! -

/'

'/

"

'""

'/

C

I

- 1--

0'

2

"

6

8

10 - DRAIN

Vos - DRAIN-SOURCE VOL lAGE (VOL is)

10 12

14

CURR~NT

16

18

20

(rnA)

Output Conductance vs
Drain Current

Drain-Source ON State Resistance vs
Gate-Source Bias

-1--

- -- -

,--

+12S'C

1---1-----

!'-V-+_+_+-_+___ _. __ _
'0 0~~2----C4----C~6-=.-:'':-0-':':2----:"4:--:'':-6-:':'.~20

'0 0~~2----C4C-6::-~.-:'0':---:':':-2-:':'4----:"6:-:'~.-"20·
10 - DRAIN CURRENT lmA)

VGS - GATE-SOURCE VOLTAGE lVOL lSI

4-4

Siliconix

PERFORMANCE CURVES (Cont'd) (25°C unless otherwise noted)
Substrate Capacitance vs
Voltage

k-+- I! 1~H' +-++-+-+---j

w

"~
0

16

I----'t'--+---i--I-+-+-+++--j

~ 121--\~__l-r~~~I-+-+-r.-+~
C,b
~

I.

0

12

~~

Z

~o

~~

'-~

w

81-~~+-+--1---+-'--~~~~~

~

~

.~t==C"=!~::~$:~~Cd~bir-~

"
I

@

>
16

12

20

-I-YGs·Jos
10= lOIlA

16

>

g

u

5

-

20

2'r-'--r-r-'--r-~'--r-r-'

~w

I.

Gate Threshold Voltage vs
Substrate Bias

./

V
V

10

V

/

•
L

6

•
2
0

-5

-10

-15

-20

Vas - SUBSTRATE-SOURCE BIAS (VOL IS)

VSS/VOB - SDURCEIDAAIN·SUBSTRATE

VOL lAGE (VOL lSI

Gate Leakage Current vs
Gate-Source Bias

Gate Capacitance vs
Voltage

C,d

/f--2

I-

12

16

1

20

o

10

15

20

25

30

VGS - GATE-SOURCE VOL TAGE (VOL lSI

VGSIVGO - GATE-SOURCE/DRAIN
VOL lAGE (VOL lSI

Source-Drain Leakage Currents vs
Voltage

II1II

Siliconix

4-5

enhancement-type
!Khannel MOSFET

H

Siliconix

designed for •••
•
•

Analog and Digital Switching
General Purpose Amplifiers

•

Smoke Detectors

BENEFITS:

all dimensions In inches
lall dlmensions in millimeters)

TYPE
Single
Single
Single

•

High Gata Trensientlfeltage BreakdDWn Eliminates Need for Gate
Protective Diode
Ultra-High Input Impedance

•
•

Low Leakage
Normally OFF

•

PACKAGE

PRINCIPAL DEVICES

TO-t8
TO-72
Chip

MFE823
3N163-64
3N163~4CHP,MFE823CHP

PERFORMANCE CURVES (25°C unless otherwise noted)
Output Characteristics
-so

Vas

1-40

-16V

0:

::J -30

....... r-

I.

"i5

~ -10

l-

V

J

::'2J.= ....

- t:::"!;J-: 1=

A/ r-

I

V

8'!.= I;;;:;
I;;;:;

l .....

V

6"-=

V

~io'

-

-12

VGS - GATE-SOURCE VOLTAGE (VOLTS)

Low-Level Output
Characteristics
-'000 r'--r-"T:-:-r-r-'..-r-,.-,--,

¢

J

-14V

...- -

Ib

-20

c

P

_~DS"VGS
Ves=D

..... r- ~,.J.=
l=I-- r-

ffi0:

~

Transfer Characteristic

VGS--20V

0

10 (on) - DRAIN ON CURRENT (rnA)

Silicanix

PERFORMANCE CURVES (Cont'd) (25°C unless otherwise noted)
Drain-Source ON Resistance vs
Gate-Source Voltage

Low-Level ON Drain-Source
Voltage vs Gate-Source Voltage

lOOK

~ 25
o

'o-'~O~~
vSS-o_f--

~

--

10= lOrnA

ID",OmA

~

515

"-

>

w

"5'" 1.0
"I
z
<1

TA"'+125 C

!3

Q

r-+-+-i' 'i2SjC

'0 0 o

-2 -4

-6

05

"

I

:g

I

>

-2

-8 -10 -12 -14 -16 -18 -20

VGS - GATE-SOURCE VOLTAGE (VOL TSI

/

CISS

24

y

ii:' 21

'z"

18

~

12

~

~ 15

~

-8 -10 -12 -14 -16 -18 -20

Drain-Source Leakage Current vs
Temperature

Voltage
27

-4 -6

VGS - GATE-SOURCE VOLTAGE iVOL TS)

Capacitance vs Gate-Source
30

10

I

o ID(Off)-VGS-VBS-O.VDS=-20V~~
ISloft) - VGO = VsO" 0, VSD os -20 V

;....-t-r

)7

v'os J-'S'V
vas" O

Coss

'i'

I- ....-

I
I

,oHm,1

20

ISloff)

MHz

IOfof,t-

I
I

09

c",

O.

,

f--'"

I

03

-'2

I
16

00

20

VGS - GATE-SOURCE VOLTAGE (VOLTS)

,

10

30

50

70

90

T-TEMPERATURE

Siliconix

110

130

150

rei

4-7

III

n-channel JFETs

U

H

designed lor •

Z

•

1
""

•
•
•

(Om;

j

Silicanix

Analog Switches

BENEFITS:

Commutators

•

No Offset or Error Voltages Generated
by Closed Switch. Purely Resistive.
High Isolation Resistance From

•

High Off· Isolation IDloffl

•

High Speed tON

Choppers
Integrator Reset Switch

Driver

< 100 pA

< 20 ns

TYPE
Single

PACKAGE
TO·18

Single

TO·92

Dual
Single

TO·71
Chip

Dual

Chip

2N5566 Chip Set, DN5566 Chip Set

On Resistance & Output
Conductance vs GateSource Cutoff Voltage

Gate Operating Current
vs Drain Gate Voltage

ALL DIMENSIONS IN INCHES
/ALL DIMENSIONS IN MILLIMETERSI

PRINCIPAL DEVICES
2N3970·72, 2N4091·93, 2N4391·93
2N4856·61, 2N4856A·61 A. FN4392,93
U200·01, VCR2N
2N5638·40, 2N5653·54, Jlll·13
PN4091 ,93 PN4391·93 Ul 897·99
2N5564·66, ON5564·66, ON5667
All of above single devices
available In ch ip form

PERFORMANCE CURVES (25°C unless otherwise noted)
Drain Current & Transconductance
vs Gate Source Voltage
~

76~Lt.ll00

200

.ffi

.s

~ ~

lOSS. Vos '" 20V. VGS = OV
DIs VOS=l5V,VGS=OV
VGSloffl. Vos = 10V. 10 = 11lA

0:
0:

1l

I

z

~

o
Z
o

100

~

V

V17

IY

V

V

"1

I

I-

17
o ./

~

!il ~

~

m

"

II:

45

;I ~
> Pii

30

C

17,,0....

15

~
~

3"

o

~

I- ~

10=

t-

-5

-10V

f')c

2

t-- ~ r-

"'",k

I -

9r

S'

1/

rOSlon)' VGS

I

....

100~A

=0

'0

10j' jA

J

I

~~~ : ~5~

o

VGSloff) - GATE·SOURCE CUTOFF VOLTAGE (VOLTS)

1000

100

/II
\

i
i

Til IZ

10m~~

I-I

S (fNI

20
-10

-5

'0

0

I

g~:::~g~:~OV_

'=1MHz

s

n1f~1!!!V

J
E

.sw

.""
""
.""

JI

111111111

VGSloff)- -8 0 V

•
to....

ens

1"·8

I!:

l- t-- I-

a

-12

V

0.,

-16

·20
VOS - GATE-SOURCE VOL TAGE (VOLTS)

01

111111

111111111

111111

111111111

10

10

Transfer Characteristics

16o

\

I

~~
-~Q

o.

l' ~
-2

-4

~ 120

~ 30

:::t

DO

o

I

.9

40

"

-10

""z
:::t

~~~r
~~~

'iIIIo,
-8

40

z

0:

-6

VOS = 20V

1
.

Z

VGS - GATE·SOURCE VOLTAGE (VOLTS)

4-8

Transfer Characteristics

1
1l

~~

40

,0

1

10 - ORAIN CURRENT (mAl

VOS"20V

!;

\
~ 120
0:
;..~~""~
il
E

~
0.1

50

160

!;

80

-6V

Transfer Characteristics

VOS = 20V

Zi

!

200

1

VES(OFFI = -2V

...:

0,

11100

.1

Jlilll

10 - DRAIN CURRENT (mA)

200

a:
c

100

30

ig f~~~kHr5~ 111111 I 11111111
:is
10
I!'$
'"

VGS(off) = -2 0 V

"0I

26

,00

~i

0

20

Transconductance vs Drain Current

~

01

Z

~CISS

·4

z

111111111

VGS--50V

~

I'\.

'"

,.

Z

21,\

4

Common·Source Output Conductance
vs Drain Current

'5

VOG - ORAIN GATE VOLTAGE (VOL lS)

VGS(OFFI-GATE·SOURCE CUTOFF VOLTAGE (VOLTSI

Common-Source Capacitances
vs Gate-Source Voltage

r- 2 m~

IGlon)@IO • _

JLLgos

\

~Z ~~
50
II:~

I ..... I--"'V
l- J-,,~

§

60

VGS(OFFI VOS = 'OV-

I I I I 1.1

l-

o.

I I

-~o'\r-6'o

I

..... :::::;;;

"'"

Silicanix

Q

Q

tS~~~

9, 0

-2
-3
-1
-5
-4
VGS - GATE-50URCE VOLTAGE (VOLTS)

~~~.

20 ~~

0:

o

~~

\

0

'--r--'~ ........

05

~
~~

10

I'.

15

20

VGS - GATE SOURCE VOLTAGE (VOLTS)

25

Z
m

PERFORMANCE CURVES (Cont'd) (25°C unless otherwise noted)
Output Characteristic
(V GS(off) = -1.5V)
VGS=IO/~

'I

VGS·~3V

/

I.'!
iff, I

,

V~

......

I---"
02

f-

- I-

VG1S=05V

-

--IJ

~-

VGS' -0 2~

12

- ..:c:.1
11

J~ i--'"
I.
00

f.v;t.,lov
5 2v

r-

VGS=1

4~j

VGS",,6V

as

04

V s=
16

12

i.--" 1-1"""

30

V 1/l- f-

1... b
a:
a:

f/l/

""z
~

V

10

e,

i--"

9

r-

BV
20

;J-

I vI
'/ 1/

a:
a:

1/, 1 /
/
r/,

""z

",

1//,
~ '/

a:

e

9

4

,

/

VGS=-15V

....1

VGr-25V

~

J~ /

80

S

1/

a:

/

IiI
1/ il /
/1 V /
III if / ......

~ /,; V
A~
~ I---"

00

01

v~s=-~v

VGS I-O,8V

r--

VGS=-10V

::

VGs=-12V

e

,s

r-

Is

'/
/'

"
Z

1

r-I--

K

±

= ~IF/~VF
=I~VFI"F -J504

4

6
VFIV)

-

~

'--

--

I-I--

5

2
VFi 25V

J501

o

50

10 (STEADY STATE)-

J507/8

~GOS

40

=10 (PULSED. DATA SHEETVALUEI==

J511

/

o

30

Typical Variation of 10 with Temperature
Steady State and Pulsed Value

Family Curves

I-~Fl

20

VF - FORWARD VOl.T AGE (VOLTS)

IF -LIMITER CURRENT (mAl

100
-50
10

-25

25

50

75

100

125

T - TEMPERATURE ("Cl

Siliconix

4-11

...

n-channel JFET

%

H

designed for • • •

Z

ALL DIMENSIONS IN

IN6~:1}

Silicanix

•

VHF/UHF Amplifi.rs

•

Oscillators

•

Mixers

•

Low Input Capacitance High Speed
Switch

BENEFITS:
• Low Noise
NF = 3 dB Tvpical @400 MHz

TYPE
Single
Single

PACKAGE
TO-72
TO-92

Single

Chip

(ALL DIMENSIONS IN MILl/METERSI

•

Wid.band
High 9fs/Ciss Ratio

PRINCIPAL DEVICES
2N3966, ?N4416-16A, 2N3819, 2N4223-4, 2N5484-6,
2N5555, 2N5668-70, MPF102, MPF10B, MPFI12, PN4416,
J304-5, MPF109, MPF111

All of the above devices

PERFORMANCE CURVES (25°C unless otherwise noted)
On Resistance & Output
Conductance vs GateSource Cutoff Voltage

~
§.

400

Drain Current & Transconductance
vs Gate Source Cutoff Voltage

r--r~~~~~~----;---'40

_

U

~,

Z

0

w

~ 300 1---+-\~r-""':r-"':-r--W'--l30 c

~~

~

8

~200

20e;

i

~

,

~ 100
~
o

10 m
3

!

I

26 ,---.,.---.,.---.,.---.,.---.,.-..,.. 7

!
~

20

~
~

U

Z

:o

15

5

o

10

4

~

3

~

2

~

100

.,.

Vas-GATE·SOURCE VOLTAGE IVOLTS)

Output CharacterIStic
(VGS(off) = -4.0V)

~

~

0'

!

32

~
>

........... "-

.,
w

U:;'-!'5~
IO=5mA

2.
24

,.
12

"

is
Z

I

,';f

a

o
10

15

15

Equivalent Input Noise Voltage
vs Frequency

0

10

10
VOG-ORAIN GATE VOLTAGE IV}

"~

VGS(off)0I-2V

20

25

30

,0

Transconductance vs Drain Current

,K

'00

'OK

100K

f - FREQUENCY 1Hz)

Vos - DRAIN-SOURCE VOLTAGE IVOLTSI

'6

Transconductance Characteristics
7

VGS a

V'

VOG - 15V
f - 1 kHz

1J

VI-

vGS,' .~ 5V

l/

VGS

, OV

I 1
VGf

'1 5v

vGf

2 10v

VGS

25V

VGS

3 OV

6

.......
-2V

~

5

VGSIOFFI = -35V

'/
12
vDS

16

20

DRAIN-SOURCE VOLTAGE jVOLTSI

l\

r.....

VOS= lSV
'''1 kHz

I'

N, "- ~

I"

r--..~r\..
3
4

"

_55°C

~+25°C I-f-

~125OC

J~~ J".. ,,~
~
,

2

4-12

o

:s -~
\

~,\VGS(offl· -4 v

~

B

·'2

01 mA

o:-§

VGS=
f-1kHz=

w

"

·B

~

Vas loffl-GATE-SOURCE CUTOFF VOLTAGE (VOLTSI

§,
·4

9""

'mA

100

~

= 5 mA

3"

~

o

~

0

,

""

o

~

10

~

I-"

'-'" -..:: ::::-

w

oS

~

§

'000

I

0

~

c

Common-Source Output Conductance
vs Drain-Source Voltage

I

~
~

Z

Common Source Input Capacitance
vs Gate-Source Voltage

~ ~~g:~~~v

IGIONI@IO
C[ 1000

::D

~

~

~~os!ov

~

I

~ VGS(offl- GATE SOURCE CUTOFF VOLTAGE (VOLTS)

I

Gate Operating Current vs
Drain- Gate Voltage

',0
ID-ORAIN CURRENT ImAI

Silicanix

'0

+25.C7.
+12S·C ..........

., I'

·2

-3

I'~
·4

·5

VGS - GATE-SOURCE VOLTAGE (VOLTS)

z

PERFORMANCE CURVES (Cont'd) (25°C unless otherwise noted)
Output Characteristic
(VGS(off) = ~1.0V)

Output Characteristic
(VGS(off) = -2V)

,u

14

I/VGS=OV

I I
l/vGS--04v 1

_16

".s
>a:i

I
III

12

1/ I

a:
a:

::>

r/,

CJ

z

DB

;;

VI.

a:

c

~

VV

,•

04

o

~GSi-T

I-

v

....

o

IGSI O

I-'

VGS=-12V

~

- -

04

02

VGS=-14V

04

08

1 2

1 6

o

2,0

VOS-DRAIN-SOURCE VOLTAGE (VOLTS)

VGS-OI

-12

/

'I
hI
'III / V

01

~

0

....

-16

+125°C~

-20

9

JI),

/

1

J.

iiia:

1

1

::>

If r-

z

VGS=,

a:
I

92
00

10

VGS·O/.

I

'/

.s
~

~ 06

12

~ 04
~

o

I

,/

rl

f/

II

1

/

ffia:
CJ

2

a:
C

I

I

9

VGs'-16v

VGS'O I

II

1-

02

04

06

08

10

Vos - DRAIN SOURCE VOLTAGE (VOLTS)

,/

/'

'1/ / .....

VGS= -1 2V

4
12
16
20
VDS - DRAIN SOURCE VOLTAGE (VOLTS)

Siliconix

fl.V
IE.

..-

00
VDS

TT

/

/I
I. I
'II /

14v
' - VG~.tJ

I

/VGso-l OV I
/VGso-15V

I- -

VG!=

VGS'~OB~i~GS'-1 OV

-16

Output Characteristic
(VGS(off) = -4.0V)

a:

z
;;

-12

-B

-4

VGS -GATE-SOURCE VOLTAGE (VOLTS)

I

vGS=-'2V

o

00

VGi·-J2V

::>

VGs=-Dav

1//

20

-

5

~GS!OV
- I-

VbS'-06V_ f-

...-

16

r-.

VOS -lOV

Output Characteristic
(VGS(off) = -1.5V)

/l

CJ

o
I
.9 02

I

/VGS'-r v

IJI

a:

::>

1

~os"

ov

VDS-DRAIN SOURCE VOLTAGE (VOLTS)

vds. 02J
I

'\

5-~0 ...

VGS=12V
VGS=14V
=16V
VGS=' BV
GS=2.0V

C

Output Characteristic
(V GS(off) = -1.5V)

4' 08

-5

1\

VGS 06V
VGS OBV

....

CJ

;;

VOS-DRAIN·saURCE VOLTAGE (VOLTS)

10

-4

I

VGS" 04V

r

a:

~

I

VGS: 0 2V

I VG'S--J 2V
05

-3

Common Source Reverse Feedback
Capacitance vs Gate Source Voltage

vGs=ol

.s>-

1

-~GSh, rv

~J /'

,

"""

-2

VGS - GATE-SOURCE VOLTAGE (VOL TSI

25

I

-,

.........IVGS=-OBV

0

VOS - DRAIN SOURCE VOLTAGE IVOLTS)

;; B

'VG~.j6V-

I, /

>-

::>

-8

VGS._02:{+=
, , ,

III V

55 C

-1

-4

Output Characteristic
(VGS(off) = -3.0V)

VGS=-04V

;;

Is; I/J
t-- :~~~~c

-5~0L"\ l\.
.~ [.25°C
~

10

02

"z

0t
Q4V

VGS= -05V

o

Output Characteristic
(VGS(off) = -1.5V)

-'~
a:

~GS;
VGS=

1

"'-,,,'\\ I'\.

i

VIGS -0 IV

a:

9

21\

II

"z 06
;;

~DS~ 15 v_

I
I

6 \

VGS = -0 tV

~ 08
::>

lVGS=-10V
Jl

V

!,o

/

::l

I

Transfer Characteristics
20

II

12

~GS'· -d6V l - I-

1/

::c

VGs=-20V

I

_--,1;-1
'fGS;-2t
: VG f·- 3,oV

4
12
16
20
DRAIN SOURCE VOLTAGE (VOLTS)

l1li

4-13

::t
Z

PERFORMANCE CURVES (Cont'd) (25°C unless otherwise noted)
Common-Source Input Admittance
vs Frequency
'00

~VDS-16V
!===vGS-o

I

b'!,..

Yls· ... +Jb,1

"' '0

~

...

,

£

i

,

g

200
300 400
600 8001000
f - FREQUENCV (MHz)

-t-ttt

b..

yos=aos+Jbos

--'".

00
'DO

200
300 400
GOD BOO 1000
f - FREnUENCY (MHz)

!"~

,

E001100

200
300 400
600 BOO 1000
f - FREQUENCY (MHz)

5 Parameters 511 Common-Source
vs Frequency
~

~ 09

r---.....

~""

..........

8

~

~

~07

-50~

~

4~

~ 061---+V
-,4--'-I-+-H+H-30

g

~

.-"

100

200

300

500

700

m

-10
1000

5 Parameters 522 Common-Source
vs Frequency

'

~

~.

~09

-401

~

~~

!iDS

-30~

~07

20-

~

~~

!::ld4 1111111~:1
200

300

500

f - FREQUENCY (MHz)

4-14

Siliconix

09
VOS"'5V
08 VGS=O

60
50

"- •

3D

\.

10

700

1000

:im"

7

,

80

70

OS

100

200

300

~

20'"

, ~
,

ZG=ZL=50n+Jo

•

..

40,

600

f - FREQUENCY (MHzl

f - FREQUENCY (MHz)

100

,
,
,
,
,

0

-90

-GO

----300 400
600 8001000
200
f - FREQUENCY {MHz}

5 Parameters 521 Common-Source
vs Frequency

-100

~
~~~: ~5 v +--+--+'-'!.'-+--hl1-H-80 ~

~ 05

-b n

-Uri

r-

I 0 100

...
~

_~DSI:15V

-VGS-O

~O"~~!!BI
,

i-""'-bh

~ 08 ZG = ZL .. 50 U+ 10 f-+-+\-'l.4-iH-i-70 m

,

10 Y12

_

~

... ,0F====::C:::-TllrnTn- 110

y22

=~DS·'SV
-VGS-O

,

....-

10

~

ICommon-source Output Admittance
vs Frequency

0

-gfs

~c

!
~

'0

~

Common-Source Reverse
Transfer Admittance vs Frequency

w 10 Yrs--grs-lbrs~V

yfs" gil pJbfs

~
f(

./

0

~~~~:~5V

"'

~

~

i,

Common-Source ForWI!!"Q
-;Transfer Admittance vs Frequency
10o Y21

700

60
1000

n-channel JFET

H

designed lor • • •

ALL DIMENSIONS IN INCHES
/ALL DIMENSIONS INMILLlJ.lETERSJ

Silicanix

•

Low ON Resistance Analog Switches

BENEFITS:
•
•

Low Insertion Loss
Small Error in Meesurement Systems
VOS(onl < 50 mV (2N54321

•

High Off-Isolation IO(om

•
•

High Speed td (on I < 4 ns
Low Noise Audio-Freq Amplification
eN < 2 nV l../Hz at 1 kHz

•

Commutators

•
•

Choppers
Integrator Reset Capacitors

•

Low Noise Audio Amplifiers

TYPE

PACKAGE

Single
Single
Single

TO-52
TO-92
Chip

-"z

< 200 pA

PRINCIPAL DEVICES
2N5432-34
Jl0B-l0
All of the above devices

PERFORMANCE CURVES (2S·C unless otherwise noted)
.

Drain ·Current &-i=o-i'wardTransconductance vs Gate Source
Cutoff Voltage

~ 800

"DSJ.

vds·. kv

J.

ffi TI.VGS~OV
~ 800 _ VGSloffl.'VD~~'OV
'D~'"A /
i3

V

~

"y

is
~

200

~

•

60

fl~. VOS= 10V
lI VGri

I

0

o

~

•

00

60

'0

'A-

..

~ ill
'"
-I

~-

III

..:<:

C

10sy

.l. f.--' ~

I

200

Vl

/

~

i'l

J

1/

~

,..... 260 ~

/

z

c 400

L

On Resistance & Output
Conductance vs GateSource Cutoff Voltage

~

.6

10-10SS

!!1 ge
~
'0

•

0Z

-I

n
C

10

IO=1/o1A

2

"'-

0

o

!

IO=200pA

~

,

c:

~

~

] .0

f

1

100

0

~
u

60

./~

'0

10

16

~
20

26

30

VOG-DRAIN-GATE VOLTAGE (VOLTS)

Equivalent Input Noise Voltage and
Noise Current vs Frequency

Common Source Input Capacitance
vs Gate-Source Voltage

eo

D~'mA,ji

IO=10mA

VGS(off)-GATE-SOURCE CUTOFF VOLTAGE
IVOLTS)

w

J

;!

~

~S=10V

6

4

'00

~I

10

I

.00

~"c

•2bs !

\

g z
!l
!; c~

Common Source Reverse Feedback
Capacitance vs Gate Source Voltage

~

reSlon): VGS" OV
le""OmA

,/

w~

I~

.00

w

VGS(off)-GATE-SOURCE CUTOFF VOLTAGE
(VOLTS)

~

•

....... ..V"". 48

Dot: VOS· 10V

u"

f;l

Gate Operating Current
vs Drain-Gate Voltage

ii'

~

I

z

!'oo~

40

1\
\\

\

"

/VOS~6V

0

D' f--.\.. 1.

VD~P10V
00
-4
-8
-12
-16
VGS -GATE-SOURCE VOLTAGE (VOLTS)

Transfer Characteristics
VOS=20V

<400 ~

!Z

.i3

~300

z

a 200

1

u

:J

c
Z
c
Olz

\ \
"-

c

r-.. ~-

-

..

~
t:::::~::"':===>J...mlllll....L.LlllIW • .-'·
1K
10K
.OOK
.00

-8

-12

-16

f- FREQUENCY 1Hz)

Forward Transconductance
vs Gate Source Voltage
.80

.........

120

VDS .. 20V
f a 1 kHz

b,.

i'- t'.....

1\

\ \

,

~

~

\

r\

60

~

" '" "'"

-.

.
.."
..
I-

'\I"

~

o-'5~

!!1
I
:=r

1

-4

10

g
ill

VGS-GATE-SOURCE VOLTAGE (VOLTS)

I-

I

~

~~sl'oV

o

~

\

:5

9,00

o

IoS

600

oS

.......... VOS=OV

,~ ...... VyDS~,6V

YOs=OY

20

~~
g

0'
0-14~ ,

o .

-1

-2

-3

-4

-5

-6

VGS - GATE-SOURCE VOLTAGE (VOLTS)

VGS - GATE-50URCE VOLTAGE (VOLTS)

Siliconix

4-15

-

I

A.
Z

PERFORMANCE CURVES (Cont'd) (2S0C unless otherwise noted)
Output Characteristic

Output Characteristic
(VGS(off) = -1.5V)
20

0

I VGS-O

II

'f

"~
E

,I"t-

vtT

~ 10

,"

:>

".;;

'/

is,

'/

r

~

00

/'

.... ,...
,...

--

~

1<,
0
:>
I<

-VGS~-O

4V

1VGS·-O
1 5V

t-"

I<

,

~

I~

7V

VG~='D~V -

vJS"rV,-

l - I-

H~S"-:OBV

O.

04

/h

Ie
00

, 0

DB

50

.Ii 40

V

E-

ffi
..

.

30

."

20

-I-

V
V

Q

I

9'0

-

-- -

:>

~

i.-

....

"
E-

VGS='O 2V

.......... y.::;

"
Z

30

Q

20

.

;;

VGS·-O 5V
I

I

VGs=·Q 6V
V 's=-O 7V

,.

40

!5

1 1

~rOt
I

~

"..-

'2

10

~:::::

0

VGS' _0'2V

f-"

IVGSI•

Lv

Vas=

04V

E-

'"

VGS"}ov
VGS=·1.6V

1,/

0:
0:

0:

~

VGS=-20V
V~6V

,...

;;

07V

,.

VdS"-J5V

rV
"Uz 200 y/

,YGS· ~
VGS -09V
12

"..-

'/

~ 300

VGS= _06V
a

!I

"

VGS -05V

-

10

IVGs"o

400

f-"

0

VOS-DRAIN·SOURCE VOLTAGE (VOLTS)

08

Vas=O

VGS" -'11\'

I ..... ..-

!?

20

I

y

VGS-'O 8V

00

..-

V

50

~

IVG~_-O ~v

06

500

70

r-++O!V

04

v

Output Characteristic
(VGS(off) = -6.5V)

(VGS(off) = -2V)
60

t:::t

02

Output Characteristic

~VGS OV

,...

--

VGS'"

VDS-DRAIN·SOURCE VOLTAGE IVOLTS)

VOS-DRAiN.SOURCE VOLTAGE (VOLTS)

Output Characteristic
(V GS(off) = -1.5V)

/'

V

.1':/

V~S=-12V

02

....f~V -

/

//

VGS"'-10V

I-

00

VGt"2J-

1/

I.

I

VGS"'1V

II 1/

V

Vos-ORAIN·SOURCE VOlTAGE IVOLTSI

I

l-

I

""

C

VGS -0 BV
VGS~'O

'I
'I

"z
;;

VVGS"OV

/YGs"-02V

I I /
I V
II

~

-

JGS--r 3V

'00

vGS~1

-

/,VGS--02V

I,
'IV ./

Output Characteristic
(VGS(off) = -6.5V)

(VGS(off) = -2.0V)

100

VGS=·36V

~

~

o

VGS=·3.0V
VGS=·40V
G8=·46V

o
4
B
12
16
20
VOS-DRAIN·SOURCE VOLTAGE (VOLTS)

20

VOS - DRAIN SOURCE VOLTAGE (VOLTS)

Output Characteristic
(VGS(off) = -9.0V)
'DO

+_
I

VGS"OY
vGS;'r

VGF"2y

'll V VGSi3V

BO

/,1 ,/

~ /' V

o
o

..

iQ

0.4

08

0••

~

~0:

...

;;
Q

w

V

'0

~

~

bIg

Q

~

~

w

>

1
'0

~
I

50

;

70 100

f _ FREQUENCY (MHz)

BOO

1

600

~

..
~

:;) 400

"
Z

~
~

200

~

....

---

V~

It ~
r/ ....
V
....
V

.....

v:: ..-

I-'

-

'0

VGS-O

~DDI= ,I5V I 1_
VGSIOFF) -'2V
TA +2i c

vGs--Io

80

VQSO-;Z

ov =1=

VGS--25V

~
;::

I

.0

2

~
I<

VGS--30V

VGS--35V
G8--40V
VGS"-45V

v,s~-i 0

=1

e

VGS-·'5V

I'....

40

20

12

'6

20

4-16

r-....

1~=J'mr

~
~

-

-20

!

40

~

-60

-80

'0

VGSIOFFI-GATE-SOURCE CUTOFF VOLTAGE IVI

Siliconix

T~ ='25°t

' '_

VtSTFF\ =

ti-

VGS{OrFI = -8SV

I, .'

VGSIOFF) = -55V

1'0.: ~

20

1
-10

.'\

30

o
-40

200

100

VOO= 1$V

::J

1

o

50

t::
t?
zI<

.....

70

f - FREQUENCV (MHz)

Switching Turn-On Time vs Drain
Current

;::

lo=36mA

1 I

o
VOS-DRAIN·SOURCE VOLTAGE WaLTS)

-

I

I

F:!

r- -

=
1

50

10

~

Switching Turn-On vs Gate-Source
Voltage

VGS-5V

I

0'

w

0;:

200

VOS-DRAIN SOURCE VOLTAGE (VOLTS)

Output Characteristic
(VGS(off) = -9.0V)

10

w

~

1.0

'0

..
....
.

-gig

if

I

VOG=20V
lo-20mA

~

0:

JGS"~V

I02

~ '00

I- Et:J~

JJ.~

I.

~

w

VOG-2DV
I =20mA

~

... VGS"6V
I

-; 1K

E-

1l

l-

I

,...

II/, '/

Reverse Transfer Admittance Common
Gate vs Frequency

i

VGS"'4V

/1 /
fl.

Forward Transfer Admittance Common
Gate vs FrequenCY
i 1K

'"

VGrOJFIJ

o

~

t'--

-T I': b.:: t:--

IJ J

1

50

'0

'5

20

to-DRAIN CURRENT (mAl

25

n-channel JFET
current regulator diode

H

Siliconix

designed for • • •
BENEFITS:

•
•

Current Regulation
Current Limiting

•
•

Biasing
Low Voltage References

•
•

Simple Two Lead Current Source
Current Insensitive to Temperature
Changes. Temperature Coefficient
Better Than O.15%rC On All Devices

ALLDIMlNSIDNSININCHlS
rALL DIMENSIONS IN MILLIMETERSI

TYPE
Smgle

PACKAGE
TO-IS (2-lead)

Smgle

Chip

z
p

PRINCIPAL DEVICES
CR022 Thru CR062
CRR0240 Thru CRROS60
All of above

•

TO·1S Package for Improved Current
Control

•

Simplifies Floating Current Sources
No Power Supplies Required

PERFORMANCE CURVES (25°C unless otherwise noted)
Knee Impedance vs
Regulator Current

Dynamic Impedance vs
Regulator Current

Limiting Voltage @ 0.8 IF vs
Regulator Current
10

100

VF = 25V

VF= 25V

~w

...iii
u
2

~0

~

.......

10

w

'~"

c 10
>

;!l

i

'E"
~;;
2

~ 10
c>I
~

DOl
0.1

~-L-L~~~

01

10

IF-REGULATOR CURRENT (mAl

Temperature Coefficient
-SSoC';;Tj';;2SoC vs
Regulator Current

u

~

010 1--I-I-+++HtI--+-++++1ttI

I

0.05

1~

01

10

1---t-t-+-t+lMl---t-t+++1ttl

i

Thermal Resistance vs
Power Dissipation

015 \--I-I-+++t+lt--+-++++tttI
010 1--t-:-f+++I+tI--+-t+H11tH

~
'-

1000

-OJ.:.:,_

~ 0 05 I----t--J.-+-++tttf---+-++~H+I

~ -005 1---++-1I-ttl1t----jH+l+tttl

1-0 10

*
i!!

-0.15

1---t-tH--t+H+I---t-t+++1ttl
1---t-t-+-t+tttf----t--t+++1ttl
01

1.0
IF-REGULATOR CURRENT (mAl

~ -0.05 1--++HH+1t-H-++1l+tftl

*

-0 15

10

0.1

1.0
IF-REGULATOR CURRENT (mAl

"

'=1MHz

5

170

~ 150

10

20

40

1

"

I'

i

L
SOD

--

I

CR043-

I

300
400
IF !!>AI

500

600

o

CR030

Y
If-'GOS
ZFl

200

-

400

06

.!!- 04

50
100

300

08

02

3D

200

Family Curves

110

VF - FORWARD VOL TAGE !VOL TSI

100

PD - POWER OISSIPATION (mW)

"- ~

130

I-

10

ABOVE

TC - 25"c INFINITE HEATSINK

o

10

~

r-...

10

RDS vs IF Geometry: NKL
190

0,

~IER~~~~~~~~~ IN

1---+--t+++tttl---+-t+~H+I

Capacitance vs Forward Voltage

5

1--:--- RANGE
TA- 2S·C STILL AIR, CURRENT
'

~ -0.10 I---+-++++I-*I---+-++~H+I

0

~-

- -~~ --=

w

25

:::±,.t;

0J-c

8w

W

II:

10

IF-REGULATOR CURRENT (mAl

Temperature Coefficient
2SoC .;; Tj .;; 12SoC vs
Regulator Current

~ 0.15 \---';I-H-t+tHt--If-VF = 25V

~

__~~WWULU

10

IF-REGULATOR CURRENT (mAl

o

(MHI = ~IF/~VF
(!ll = ~VFI"F
4

ftCR022

6

10

VF(VI

NOTE: IF. Regulator Current is specified under pulse conditions. In operation, final current will be a function of junction
temperature. IF (steady state) = IF x [' + 01 (Tj - 25°C)] where 01 is the temperature coefficient of IF and TJ is the junction
temperature.
Tj may be found by Tj
for all devices.

= Tamb + 0j-aPO = Tcase + OJ-cPO. T' must

not exceed l50°C.--'--or-'--is the derating factor
0j_ a
0j_ c

Silicanix

4-17

~
z

n-channel JFET
current regulator diode

CATHODE IS BACKSIDE CONTACT

~

r
1_~'O030

i

'00'"

designed for • •

·•
··

~~ IIIII1 1-:]'1
A

~ I-r'"

I

~

(OJl40)

(ALL DIMEr.lSIONS

IN MILLIMETERSI

.

BENEFITS:
Simple Two Lead Current Source
Current Insensitive to Temperature
Changes. Temperature Coefficient
Better Than 0.15%1" C On All Devices
TO·1B Package for Improved Current
Control
Simplifies Floating Current Sources
No Power Supplies Required

Current Regulation

•

Current limiting

•

Biasing
low Voltage References

SlOg Ie

PACKAGE
TO·18 (2-lead)

PRINCIPAL DEVICES
CR068 Thru CR150
CRR0800 Thru CRR1250

SlOg Ie

Chip

All of above

TYPE

i"43J

ALL DIMENSIONS IN INCHES

H

Siliconix
- -

•
•

PERFORMANCE CURVES (25°C unless otherwise noted)
Dynamic Impedance vs
Regulator Current

Knee Impedance vs
Regulator Current

100

Limiting Voltage @ 0.8 IF vs
Regulator Current
10

10
VF" 25V

;;

VF"'6V

~

~

w

~
w

w

u
Z

«

U

z 10

10

S

"~

«

S
~

iu

0

«

i2

z 10
~

I
Ii:

I
iii

V-

10

>
z
;:

w
w

;;

VF= 25 V

~0

;;

"

01

;;
:l

I

~

>
D1

u
~
...
ill

1

001
01

10

10

10

Temperature Coefficient
-55°C ~ T J ~ 25°C vs
Regulator Current

Temperature Coefficient
25°C ~ Tj ~ 125°C vs
Regulator Current

Thermal Resistance vs

~...

VF" 25 V

u

i.l

010

~

005

Power DIssipation
1000

VF= 25V

015

~

...u
w

DOS
0

8w

0

Ir

I

0

~

«

_-+

~ -010

~

-

~-0151

II

01

~I

II

1111111
10

.!.. -0 15

1111111
10

.....

,

f= 1 MHz

15

§
...

5

a

r--..
10

II:
II:

::J

900

30

40

50

300

400

500

CR150

1.6

",

I
III

12

"

3
Iii
1

DO

CR120

CR~91

,

08

::J

"'i'--,
20

200

20

II:

"\

II:

I

u

100

1.1

~

'"
~'OOO

10:\

g

\

1100

w

~

0

Family Output Characteristics

1200

20

•

REGULATOR 2fi IN AROVF
CIRCUIT BOARD
TC - 2SOC INFINITE HEATSINK

Po - POWER DISSIPATION (mW)

RDS vs IF

Capacitance vs Forward Voltage

«
...

.-

IF - REGULATOR CURRENT {mAl

25

~

10

10

10

01

IF - REGULATOR CURRENT {mAl

I! I i i

~= 25°C STILL AIR. CURRENT

I

.-

~

',-,

---~-

----l
+-;-r :-

~f~ ~- ·];~rt'1t-r~
~ -~~- t~j --- ~ - RA~GE

i:

~ -010
I

--.~

100

~

"~ -005

~

r!~.

r- 1-

z

Ir

~ -005

--}jl- JI=

I- c--

u

u

w

10

IF - REGULATOR CURRENT (rnA)

010

u

10

IF - REGULATOR CURRENT {mAl

015

*"

01

IF - REGULATOR CURRENT (mAl

CROSB

II

0

800

5

6

7

8

9

10 "

12 13 14

0

2

0

6

8

10

VF-FORWARD VOLTAGE IVOLTS)

IF (mA)

VF - FORWARD VOL TAGE (VOLTS)

NOTE: IF. Regulator Current is specified under pulse conditions. In operation. final current will be a function of junction
temperature. IF (steady state) = IF x [1 + 81 (Tj - 25°C)] where 81 is the temperature coefficient of IF and Tj is the Junction
temperature.
Tj may be found by TJ = Tamb
for all devices.

4-18

+ 8j-aPO

= Tcase

+ 8j-cPD. Tj must not exceed 150'C.-.-1-or ~iS the derating factor
8J- a

Siliconix

J-C

n-channel JFET
current regulator diode

Siliconix

designed for • • •
•

Current Regulation

BENEFITS:

•

Current Limiting

•

Simple Two Lead Current Source

•
•

Biasing
Low Voltage References

•

Current Insensitive to Temperature
Changes. Temperature Coefficient
Better Than 0.15%f C On All Devices

•

TO-18 Package for Improved Current
Control

•

Simplifies Floating Current Sources
No Power Supplies Required

Single

PACKAGE
TO·1812-leadl

PRINCIPAL DEVICES
CRl60 Thru CR530
CRR1950 Thru CRR4300

Single

ChID

All of above

TYPE

ALLDIMENSION$ IN INCHES
fAll DIMENSIONS IN MllllMETERSI

z

H

S

PERFORMANCE CURVES (25°C unless otherwise noted)
Dynamic Impedance vs
Regulator Current

Knee Impedance vs
Regulator Current

Limiting Voltage @ 0.8 IF vs
Regulator Current

i 1

IF - REGULATOR CURRENT (mA)

IF - REGULATOR CURRENT (mAl

IF - REGULATOR CURRENT (mA)

Temperature Coefficient
-55°C';; Tj .;; 25°C vs
Regulator Current

Temperature Coefficient
25°C';; Tj .;; 125°C vs
Regulator Current

Thermal ReSistance vs
Power DISSipation

u
~ 0"
....
ili 0'0
u

~
0

o 010L,,_-'-.Li...LJ~,.Lo---'-_....J.lJ,0

'0

0'

VF= 25V

~....
15

0'0

IE

005



I
-'6

-8
-'2
VGS-GATE-SOURCE VOLTAGE (VOLTS)

~55'~f

--=

!2
,;,
!2

VO"OV

v

VOIG"~V

005 mA

10

Z

"~

I

o~

-4

02mA= (;:/j

100

g

I
I

y'VO~5V

4

;;;

1-- r-v

§
~

Common-Source Input Capacitance
vs Gate-Source Voltage

...

)!kVDS~5V

~

~

05mA

~1000

-2 5

f'llllllill
1\

."

VGS-GATE-50URCE CUTOFF VOLTAGE IVOLTS)

Common Source Reverse Feedback
Capacitance vs Gate Source Voltage

Vos=O

~

,.~ "1
Z

VGSloffl VOS=10V1O=1JlA

-05

•8

//
//,.,

\

~
I
0

15V

VGS:: ov

V

VOS=15V

....... V

9

Vas" ov

500

>(

/

I

4-20

2N3921-2. 2N4084-5. 2N5045-7.
2N6905-7. U401-6. 2N5046CHP-47CHP.
U403CHP-06CHP. 2N4085CHP. 2N6905-7CHP

Chip

rOS(on) 10 -= 100jJA

~
iiiII:

4

V V

0

~
II:

~

Low Noise
en = 6 nV/y'Hz at 10 Hz 1\'plcal

10000

"z

lOSS
-VOS=1ISV
VGS=ov

•

PRINCIPAL DEVICES

w

80

Simplifies Amplifier Design
Output Conductance < 2 p.mho

On Resistance & Output
Cond ucta nce vs GateSource Cutoff Voltage

Drain Current & Transconductance
vs Gate Source Voltage

iiiII:

PACKAGE
TO-71

•

1K

10K

100K

I-FREQUENCV (Hzl

Forward Transconductance
vs Drain Current
'0

JOG~ '5~

f-

55"{I
fL ~
'j

1
~

VGSIOff)=~I~r;2/

U1;I:Hf

+25°C

II:
II:

""z

~

I

V~~;off) "'-2 'OV

/

~

o
I

9

l,,1li

o
-20

-16

Vi..?' j125jC- } ~~
I
-12

-08

-04

Vas - GATE SOURCE VOLTAGE (VOLTS)

Siliconix

05
VOG= 15V

0,

"1' 1"1'1111
001

01
10 - DRAIN CURRENT (mA)

10

zz

PERFORMANCE CURVES (Cont'd) (25°C unless otherwise noted)
Output Characteristic
(V GS(off) = -D.6V)
020


"~ f'
""c: ~
fil
n "
z

*

~
~

VGS::

rOSlon)

'.'

O.

~

D.

..Ii".

03

02
VGS (offl
Vas = l0V

I

E

0

0
10

20

..

......-

I

S

[

e

30

~

i

"
"~
"


'"0
z,
0

0.1

~
001
0

6

10

,.

2.

30
20
3'
VOG -DRAIN-GATEVOLTAGE (VOLTS)

e",

0

-4

-8

-12

-18

-20

VaG - DRAIN GATE VOLTAGE (VOLTS)

CMRR vs Drain Current
'20

..1\

~

I:D~30jJA

'GSS

10

"-

0
lK

Equivalent I nput Noise
Voltage vs Frequency

i

~

II

1

u

30

0:

15

10 - DRAIN CURRENT (PAl

Gate Operating Current
vs Drain·Gate Voltage

'""'"
"~

III
100

10

100

e,u

0-

VGSloff,'"' V

VGS -GATE SOURCE VOLTAGE !VOLTS}

iii0:

""
~
"u,

0-

1"14
-16

'"

u

VGSI~I.'1·2~

"u0

!'.;t\

1
1

ii

2

IO=30 /AA
f= 1 MHz

1
.......

~

0-

r--..C\
r-... ~

.....

.a-

::0
0

I' I\.

;--.

l.
""u

I'...

25

10V
'''1kHz

VOS'"

1l

r .. _55°C

Capacitance vs Drain Gate Voltage

1\

20

,.

w 110

Q
Q

i\

:;;

z

0

:;;

1\

r--

~30"A

•

10

'iiri
100

lK

10K

f - FREQUENCY IHzl

~

90

is

80

a:
a:

.... !'--

10

100

:;;

,ODK

1---

-

-

JJJ111,J1

tf

CMRR

= 20 log -6VDG
-6VGS' - 2

10
00, 002

IIII I D.III

DO.

01

02

10

ID DRAIN CURRENT (mA)

BIll
1

I

Silicanix

4-23

n-channel JFET

1

··

i~ Etl
0023
(0584)

•

High Power Gain

Oscillators

•

low Input Capacitance

TYPE

PACKAGE

PRINCIPAL DEVICES

Dual

TO-78
TO-71
Chip

2N5911-12, U257 U443-u444
U440-41

Dual
Dual

~

.

BENEFITS:

Mixers

,-o-rm;

~~

'~2J

Siliconix

High Frequency Amplifiers

·

(0;;;;

(0

H

designed for • . •

.

MS911CHP, MS912CHP,
M440CHP, M441CHP

ALlDIMEf-

~
~~

VySlr"'1 V'IS

o

~':Iml] 111
~
~

/

='G@'O

w

VOS 0

~~

VGS

>-

1

50

j'«~VOS'O

~

V

~


'If "

10

Noise Voltage vs Frequency

VGS-GATE-SOURCE VOLTAGE (VOLTS]

VDS

JJ
11/

100

VOG - DRAIN-GATE VOLTAGE (VOLTS)

."-

-16

VDS=15V

0.4

~

<>
C

n

06

-06

~

Z

0

..g.

rDS

~~~

Transfer Characteristics

-08

n

o ~

,,-

'l

3

VGS-GATE-SOURCE VOLTAGE (VOLTS)

-10

w

.!:i... ..
".

6

",-

~
~

4

I

-12

C

IO{on)@IO

26

!:: 6

YOS=6

-

'0

~ 1000

Common Source Input Capacitance
vs Gate-Source Voltage

w
u

o

./ '5

k:.

/'

20

10000

'"
T
0

VGSIOFF) GATE SOURCE CUTOFF
VOLTAGE IVOLTS)

"ii:

o

" ><
V

-

,

o
o

VGS (off]-GATE-SOURCE CUTOFF VOLTAGE (VOLTS)

\ /

i\.

.;'

loSS

IV'

\

IDSS,9ts
VOS=20V
VOs=OV

:J

= ,OV ID = , p.A

VGSloff) VDS

/

/

4

II:

25

1500

~

Gate Operating Current
vs Drain-Gate Voltage

~

~
-12 ~8

,

g
~

5 m

:'i

,0"3
~

05

~4

VGS - GATE-SOURCE VOLTAGE (VOLTS)

4-25

£f

PERFORMANCE CURVES (Can't) (25°C unless otherwise noted)

Z

Output Characteristic

Output Characteristic

(VGS(off) = -o.5V)

(VGS(off) = -o.5V)

02

I

VGS~O

II
Y/
J
II
fl

;( 0.16

g

iii

~ 012
a:
::>

"~ 008

I I

~s·:-OT

I--- II-

...

v

II

Vr.s.= -0 30V

02

04

06

08

VGS=O

•
~

~Ol

a:

-

II,L
fl

,

11'1 /

01V

- II I
VGS--1 4V - I-

VG =-O3~_

V

v IS"1051_

V

11

B

a:

c

J

I

EaD4

'0

!J./,GS ~ -0 iv.!

::0

"~oo

Vas e

r-

I.~

-

VGS=-06V

-I

< 08

02

03

~

v~s-I-o.~

~ 06

02

04

05

12

tVGS~O.~

VGf=-"2V

...z

! i~ S~-! 4

a:

'I

~012
::0

Ii

"

~008

v

'I

I
,9004

~ 3.0

1/

a:
a:

1/

04

03

01

02

03

I

I I

r 17

+25"c

+~5°~_

O.BV

VGS=

VGS- 1.0V

VG$~-

---

VOS-DRAIN·SOURCE VOLTAGE (VOLTS)

••

20

/

8

~

-

-5

/>' 'Y

v·4

tiC~w ,

&

•. 2V

""-, V
G =-1 BV

12

,

-20"C_

VGs=-14V

os

05

Transfer Characteristics

Vas" -06

i.-

,910

04

Ves-DRAIN·SOURCE VOLTAGE (VOLTS)

VGS" -04

"""

c

BV

IVG~~_2 OV
02

o

VGS" -02

v-

~

I

V

0'

....

"z 20

vos=-'

20

VOS=15V

g

5=-16V

..........

,.

......

vJob

4.0

y

~
C

.

~(;S~~06.
VGS=-10V

g

:;,...

Output Characteristic
(VGS(off) = -2.3V)

(VGS(off) = -2.3V)

.......

~/

VGS- -0 BV

-OBV

Ves-DRAIN·SOURCE VOLTAGE (VOLTS)

Output Characteristic

r<,016 r-

VGS

VGS=-36V

V ~}Jov

~~

VGS·-05V

"""

Vas=-3 ov

II-)'.

VGS .. -04V

C

... VGS--2 6V

'J

VGS =-0 3V

a:

.9

V~S=-:2.0 ~_

rT
/!/

::>

"~ 04

20

I/VGS~.I.~E
VGk::·15V

I I I

a:

16

(VGS(off) = -4.2V)
'0

g

VOS-DRAIN-SOURCE VOLTAGE (VOLTS)

018

12

Output Characteristic

VGS=-01V

I

01

GS::-3 BV

o

VOS-DRAIN-SOURCE VOLTAGE (VOLTSI

VGS=D

~

I

VGS=-07V

~-

o

20

Output Characteristic
(VGS(off) = -1.0V)

(VGS(off) = -1.0V)

:ito 16

VGs=-3V

o

Vas-DRAIN·SOURCE VOLTAGE (VOLTS)

Output Characteristic

°

VGS::-Z BV

,.

12

10

VDS-DRAIN·SOURCE VOLTAGE (VOLTS)

02

\'GSL-2J

VG$' -03OV

-03

o

VGS=-l BY

;'

VGS= -02SV

VGS" -025V

VGS~O

1J}5V
VGS~-' bv

/

r/

vGl- -b 1Vl
vG~- j, ,J.
vG~-j,2vl

fo-""

I

'1 'I

~

......

VG~' j,05t

II

VGS" -0 zov

I

~004

I IT

1

GS=O

~ls·~'~- I-- I-i..--

(VGS(off) = -4.2V)

'0

1I I

I

VGS=-O Q5V

C

o

04

Output Characteristic

+~5"C

T7r

"

-4

-3

-2

-1

VGS - GATE-SOURCE VOL TAGE (VOLTS)

Vos - DRAIN SOURCE VOLTAGE (VOL iSI

Output Characteristic

Output Characteristic

(VGS(off) = -3.0V)

(VGS(off) = -3.0V)

, 0

V~s~~

rGS~OV
I, 1~'~;f- IVqs"'-:o

1/
III
II rL

<08

£
~

~06

VGS"' -02V

v~s ~I-o

U,

a:

::0

"
"a:

~

'(f

!:04

IltV
WI

C

I

,902

V

J.'/
02

GS~·Tv
I
I I

~
C

06

08

10

Ves-DRAIN-SOURCE VOLTAGE (VOLTS)

4-26

4

1/

""z
2

9

~

o

VOS-15V
fo: 1 kHz

1400

;,O"C=;

bt I-

+25"C

V fo-""

tJ,L

V

JGSl2 O~
12

'6

17~

Ves-DRAIN-SOURCE VOLTAGE (VOLTS)

Siliconix

'7

-10

-08

-06

!!;
!'l

400

§

~25°~_ 200

)!

+85°C'-04

800 ~;I

600

-,O"C/C;C

20

~

li!

Fe

r7

VIGS~~2 6~

~

1200 0

1000 ;;

+85"C

vU.ol_

....

o

'600

1

v~stJ.

1/'"

I

I
04

~

a:
a:

VGS--05V

I-o It: l-

o

1V-f-

1

Transconductance Characteristics

-02

VGS - GATE-50URCE VOLTAGE (VOLTS)

!!!

~

z

PERFORMANCE CURVES (Con't) (25°C unless otherwise noted)
Transconductance Characteristics

I

VOS'" 15V
, .. , KHz

/'

/I
-20'S- '2·Y
V V
V K;.
J Vl(.:' 'M~

~?c
If r

~ VI
~
A~

L Qi'
-1.6

-1.2

//I

!

...

I

-

VGS - GATE..$OURCE VOLTAGE (VOL TSI

o

o

-2~C7

<...~ ~7

-I

500

3500;VOS-15V
1:1 1 kHz

-2"CX

"
1500 i!
z
8
1000

Transconductance Characteristics

2800

Vos= 15V
f"1kHz

I

Il

A'

il!.

f-

+8S"C

L--'

-24 -20

-1.6 -1.2

1500

+isa:g

+25"C

-2.8

?ii

"i!
-I

-20"C

1000

+8S"C

I

+8S"C-

.N
A".11

II
2500
2000

c:

I

I
3000 ~

+25°C

1

!§

~

iL,

1

+BSoC

;;-

~ ~+25"C
-08

2500 ~

2000

~

Transtonductance Characteristics

500

z

~

z

"5

~

;;-08 -04

VGS - GATE-SOURCE VOLTAGE (VOL TSI

-6

-5

-4

-3

-2

-1

i

VGS - GATE-SOURCE VOLTAGE (VOLTS)

l1li

Silicanix

4-27

A.

8ACKSIDE .!UNCTION ISOLATED
FAOM ACTIVE CClHTACTS

G

monolithic
dual n-channel JFET

Z

H

Siliconix

designed for •••
•

General Purpose Differential Amplifiers

TYPE
Dual

PACKAGE
TO-71

Dual

Chip

BENEFITS:

•

Low Cost

•

High Input Impedance

PRI,NCIPAL DEVICES
2N3954-55. 2N3954A-55A.
2N3956-58. 2N5046-47.
2N5196-99. 2N5515-24. 2N5452-54
U231-35. U410-12

(06101

2N3955. 2N3966-58
2N5047. 2N5199
2N5454. U233-35
U411.12

ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS/

PERFORMANCE CURVES (25°C unless otherwise noted)
Drain Current & Transconductar1Ce
vs Gate-Source Cutoff Voltage

-

10SS.9fs VOS '" lOV

IVGS-OV-

-

?

3

/.~

n"
0;:-

V/

"
I
e~

850

\

w
2

U

~
iiia:

750

"

850

p

go,

~~
n:O

u

1
~

;;
"

VGS(oJ) VOS = 10 V
10=1fJ.A

,
3

VGS(off)- GATE-50URCE CUTOFF
VOLTAGE (VOLTS)

Gate Operating Current
vs Drain Current

~

A
1\

~S'o.'

/

--,--

Vos == tOO mV
\
GS = ov
I
I
A r\:GS(r'f)7:~
t= ;:v

"

"'v
/1

a: 450
0

I

c

1

'OSlo.J'\J

I'-+-

V

350 0

10

r
I

o

1/

\

a: 550

~

VOS=20V
VG5~,OV

\

me iil

//

/.

i:g

"0
n:o w

/10 , 5 - I--

~",

:0

.,
2

g"/V

1/

.,.

On Resistance & Output
Conductance vs GateSource Cutoff Voltage

.

..8~
2

g
~

~

2 ;;-

o

1

-1
-2
-3
VGS(off)-GATE-SOURCE CUTOFF VOLTAGE (VOLTS)

Common Source Reverse
Feedback Capacitance
vs Gate Source Voltage

10

25

~

3.6

.!!
~

32

~

28

;

VOS -10V

~

c3 20

'"u

'8

1'2
I

08

ur:!

04

k

vcs-s

V

~\\

VOS=10

"- /
8

10

12

14

,

16

~~

VGS-GATE-SOURCE VOLTAGE (VOLTS)

Common Source Output Admittance
vs Drain-Source Voltage
'00

11

.3
"

~

VGSloff)--33V

10

i

:--F

~JJt"0~

I

I11I I

"

I.

IIII

1

o
10

t2

16

14

'0

100

'K

'OK

lOOK

f - FREQUENCY (Hz)

Common Source
Forward Transconductance
vs Drain Current

VOG" 15V
f-1 kHz

VGS(off) "'-33V

'0

~~~~~~~;;~~~~

8",

5

~ VGSloff) '" - 81 V

5o

I

g

VGS(off)- -0 a1 v
0 ' _ __

I

0' o

.i
10

15

20

25

'g~o'~~~O~,~-LUli~'~O-LLU~~

30

VOS - DRAIN-50URCE VOL TAGE (VOLTS)

00'

0'

10

10 - DRAIN CURRENT (rnA)

4-28

i' 'O'200pA
I"~l

'O~_

~

'0

'0

i5

VGS-GATE-SOURCE VOLTAGE (VOLTS)

if

w

"

Common-Source Output Conductance
vs Drain Current

f - ' kHz

~
.3

'5

0

Vos=10

o

"~
$

I
1

'\ l\.

o

~...

VDS=5

'\\ V

o

~

,r-..

w

24

VOs=O

50

20

~

\

40

Equivalent Input Noise Voltage
vs Frequency

Common Source Input Capacitance
vs Gate-Source Voltage

40

u:-

30

20

VOG - ORAIN·GATE VOLTAGE (VOLTS)

Siliconix

'0

10 - DRAIN CURRENT (rnA)

z

PERFORMANCE CURVES (Cont'd) (25°C unless otherwise noted)
Output Characteristic
(VGS(off) = -1.0V)
0200

VGS=O

li

a-a 160
z

I I
VGS--03V

l

lI. 1/

0:

"
U

II '/ /
f!J '/ i--"'r-

~ 0080

C

Eo 040

, --

o

01

02

II / / I-' -f I

1/ /'
!f// vr-

fJJ VV

!l~

VG' __ Lv

I#. ;....03

04

05

01

VOS-DRAIN·SDURCE VOLTAGE (VOLTS)

~

i=""
06

~
~

"
u
z

vLs.ll

20

I I I

C( 16

0:

C

VGS= -O.4V

9

VGS= -O.5V

I 02

VGS

~

'//11-

"

C

~

02

a
04

05

E

Ci

a

02

C

I

.9

04

I I
VGS·-02V--

VGS= 04V--

3

"

VGs=-06'li-f--

;;

VGS--OBv'-f--

Z

vGs .. -oav

0:

C

VGS"-10V~b

9,

vGs=-' 2V

I

VGS=-14V

VGS=-10V

,.

20

4

o

VOS-DRAIN-SOURCE VOLTAGE (VOLTS}

B

12

VGS=-16V

,.

12

20

16

20

Vas-DRAIN. SOURCE VOLTAGE (VOLTSI

VDS-DRAIN-SOURCE VOLIAGE (VOLTSI

Transfer Characteristics
Low VGS(off)

,0

08

VG~-ok====

:< ,

U

VG~= ~6VI-

/

0:

06

04

Vas-DRAIN-SOURCE VOLTAGE IVOLTS)

~

VGS"-04V
08

VG~=}.v

VGk=-Jov

E

I I

U
Z

VG~=).v
f-'"i I

~

~

VGS"'-02

~12

-

Output Characteristic
(VGS(off) = -2.3V)

I I

~
"

r-

l-

VGS::-1.4V

{fl.'/, V
~:/" V

0:

."

VGS=-1.2V

V

I'll>

0'

vcis--l2V
03

,tt

III- rJ V~~:jlB:V

I r/. '/

06

U

;;

I I
vris--lov

-06

'2

1
.
Z

VGl--+-- r-

V~S=~02~
v~s-I 03~_ I-:::

;;

02

VGs· ...

r/vGs·.-o~v

08

0:

VGS--OBV

-

VGS-O!

Output Characteristic
(VGS(off) = -1.5V)

VGS" -0 tV

a'

'a

VOS-DRAIN-SOURCE VOLTAGE (VOLTS)

Output Characteristic
(V GS(off) = -1.0V)
08

VG~-~06V

V

vCli= ... 6V

V-.

a

II I

VGS=-05V

~ /'

I

~GS~j2~±=
I 1/ I I
~VGS·-04it-

e-

£)

Output Characteristic
(VGS(off) = -2.3V)

VGS=O

r-- I-

VGS'"-04V

~ 0 120

05

V~S·~02~- :-- e-

LLj

..s

Output Characteristic
(V GS(off) = -1.5V)

Transfer Characteristics
Medium V GS(off)

Transfer Characteristics
High VGS(off)

08
VDG=15V

T=-55"c -..J

VOG=15V

T = +2S·C
1

1

T=+l25°C

/J

/

~

06

T=-SSoC V

1

T+soii

,.'"
C

04

02

W

VOG"'lSV

6"
T=+25°C

'"'"::1
...

T<>+12S 0 Ci /

~

~V

g

IT =+25"C

'j

Z

T= +12S"C

W7

.-

::::::: :?'
-16 -14 -12 -1.0 -08 -06 -04 -02

-40

-35

30

'-20~15 -10

25

05

VGS - GATE-SOURCE VOLTAGE (VOL TSI

Transconductance Characteristics

Transconductance Characteristics

Low V GS(off)

Medium V GS(off)

"8 2000

1'500

~ 4500

~

C

~

::o

~~

1

i

g

3000

"\ ~\J.T·+f5°C

...~

r----. .~
500
I--

~ 1500

T=~ ~ ~

02

04 -06 -08

10

12

ii2
14

16

VGS - GATE-SOURCE VOLTAGE (VOL lSI

1

i

~

//

)- , /

~ ~V
~F"'"

-'5

00

VGS - GATE-SOURCE VOLTAGE {VOL TSI

l1li

CMRR vs Drain Current

I

'20

w 110

c

0

1\
1\

5z

.......... !=-55°C
1000

f= 1 kHz

w

r\

-30

V

1 r--/

V~G' ,IS V

6000

f= 1 kHz

w

"8

1

V~G' ,~V

1

-

0 0

VGS - GATE-SOURCE VOLTAGE (VOLlSI

/

V

:!

"\ ).
~

z

'00

:!
:!
0
u

90

0

/ ' T=-SS"C
T= +25°C

"'\ ~

i'-

~
"'I"'""
~

I

II:
II:

:!
u

80

T"I'2Sor"
0

-05 -10 -15 -20 -25 -30 -35-40
VGS - GATE-SOURCE VOLTAGE (VOL lSI

Siliconix

70
005
02
05
00' 002
IO-DRAIN CURRENT (rnA)

a'

, 0

4-29

...I

GATE ALSO BACKSIDE CONTACT

~

n-channel JFET

SAND D AliI' SYMMETRICAL

z

H

designed for • • •

Siliconix

•

Small Signal Amplifiers

BENEFITS:

•

VHF Amplifiers

•

•

Oscillators

Wide Input Dynamic Range
High IG Breakpoint Voltage

•
•

High Gain
Low Insertion Loss Switches

•

Mixers

•

Switches
TYPE
Single

ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERSI

PACKAGE
TO-72

Single

TO-92

Single

Chip

PRINCIPAL DEVICES
2N3821-4. 2N3921-22. 2N4220-2
2N4220A-2A.2N4223-24
2N3819.2N5457-9

MPF109. MPFlll, MPF102. MPF108,
MPFl12
All of the above

PERFORMANCE CURVES (25°C unless otherwise noted)
On Resistance 8t Output
Conductance vs Gate-Source Cutoff
Voltage

Drain Current & Transconductance vs
Gate-Source Cutoff Voltage

--

•
V

4DD.

•
./

-2

,

Vos= 15V
VGS= 0
gfs@lf""kHz
VGS(off) @ 10 = 1 nA

./
-1

2

I

1/
-3

-4

-5

-6

-7

Output Characteristic
(VGS(off) = -2.0V)

-Lo.L.J- f-

•

-02V

II

3

rf

2

,

-J•• J- f-

~

V
V--

-D6V

~

-10V

-Dav

-,

200

~ili

Co:

0

,
,

"

~

S .s>-

0
Z

g ~
"
~Z "~

.,

~

00

;;;

0

0

.-3
!

6

,
,

.
2

-01 V

-02V

-.'~-I-

~

-05V

04

ry ,.
Vos - DRAIN SOURCE VOLTAGE (VOL lS)

Transfer Characteristics

Transfer Characteristic

I

I

2~ f--

·x

VOS=15V

TA~-'8.lc

~

·"·0

." ""K'
,.J.;;-::

l'\. ~-4.·C

.

-4"~

-,

~'\
"I

~

-z.

~

-3.

-4.

Vas - GATE-SOURCE VOL lAGE (VOL TS)

Leakage Currents vs
Ambient Temperature

Transconductance Characteristics

-6

Transconductance Characteristics
~

1'-..

~

7 1/

+85°C

c

•

75

100

T - TEMPERATURE ('C)

125

-1

150
VGS - GATE-SOURCE VOL lAGE (VOLTS)

Siliconix

~

'\

/
50

-

TA=+85°C

"5·CI'-,.\
~ ~;S-...

IG

25

Vos= 15V

f-lkH,

V'2.·C
\i'-..
k': 1'< '\- .... c

I=-'GSS

/

I
I

6000

~

:gS:~DvGG~ 15-~~~ ~~50=1J~~ ~

-7

VGS - GATE-SOURCE VOLTAGE (VOLTS)

]

t=

-h3J

V

c

VGS(OFFI-GATE SOURCE CUTOFF VOLTAGE IVOLTS)

,.

V

V- I-

6

0

~2•• C

,.

~

<1

10 ~

~z 100

.

-000

4-30

l~
z",

20

Vas- DRAIN SOURCE VOLTAGE (VOL lS)

0

~.

30

'l300

o:W
CO

3 TA'

-12V
-14V

-,•

~

I I I

JGsL.L f-

0

e

VGS- GATE SOURCE CUTOFF VOLTAGE (VOL TSI

•

w

z"
:;:s.
3000

I

, I
I

I

0
0:

I--

I/,OSS

•

000 ~

"7

/

74

I-2

•

Output Characteristic
(VGS(off) = -O.BV)

~

-2

-3

-4

'"

~

-5

-6

-7

VGS - GATE SOURCE VOLTAGE (VOL IS)

PERFORMANCE CURVES (Can't) (25°C unless otherwise noted)
Equivalent Input Noise Voltage and Noise
Current vs Frequency
10-14

100

1000

,;:1
1

~

2

~

0

10

0

~

.

'",@iR "ID~

w
~

w

~

i5
z

In@IO'"OlI0SS

1

~'D·~·'1tl
en@IO~

z
I.

10

lK

100

100

.1

10

VGS(off!
10

,.,.-

,-,

-

-3ZV

I-I-H-

\

VGS(offl

:g

16

1'·-1·:

-1ZV,=

I I I

1

10-16
lOOK

10K

~~D~~.'5V

VGS 0
f 1 kHz

~

...2 ~
;; "
i; "
~
~ "';'

>

Common-Source Output Admittance
vs Drain Current

S

iii !l
"c: ~
10-15~

w

:;"
"

Common-Source Output Admittance
vs Drain-Source Voltage

I

24

III1

0'
001

40

32

Vas - DRAIN-SOURCE VOLTAGE (VOL TSI

10 - CRAIN CURRENT (mAl

f - FREQUENCV (Hz)

Common-Source Capacitances
vs Gate-Source Voltage

I.s

5
Vos" 15V
f=l MHz

1\
1\

10

VOS=15V

V21

VGS-O

1:--9f5

z

~

U

Z

~

I----b~

" ,

"~ 0'1.,..--'"

Z

~

1

~"

;;

:r
-

-4

~

/'

~
~

Q

en,

bl~

~

~
..........c~

'"

Vas'" 15V
VGS=O

.sw

/

~

"-

10

~
E

w
u

_\

Common-Source Input
Admittance vs Frequency

Common-Source Forward
Transadmittance vs Frequency

001

50

10

100

V

00 1
10

200

50

100

200

f - FREQUENCY (MHz)

f - FREQUENCY (MHz)

VGS- GATE-SOURCE VOLTAGE (VOLTS)

Gate Operating Current
vs Drain-Gate Voltage

Common-Source Reverse Transfer
Admittance vs Frequency

-10

10 Y12

j

VD.

~
~

.sw
~

~

"~

"

~-o.o1

~ID"'mA

o

10

15

20

~

25

30

'ON' Resistance vs
Ambient Temperature
5
14

~

J

~
~
w
>

2

u

g
1

~

e

1

"~
;;
"

1

"

001
10

~

-'n
50

100

00 1
10

200

Drain Current and Transconductance
vs Ambient Temperature
15

I I

w 14

:-

;i

13

u 12

~

1/

11

Vos"15V
VGS"O

"\

9fs@f=1kHz

"\
"\

~

~ 10

/

"I......1"-

3

09

9fsANO losS

~ 08
w

:3

07

07

"> 06

06
-55

-15

25
65
105
T - TEMPERATURE lOCI

200

Common-Source Forward
Transconductance vs Drain Current

8

o5

100

f - FREaUENCY (MHz)

V

9

50

f - FREQUENCY (MHz)

>

10

gos~

0

VGS=O

1

~~,~
.,/

~

::"

/

10= lDOjiA

VoS=15V
VGS=O

Q

~

"

VOG - DRAIN-GATE VOLTAGE (VOLTS)

w

01

~

ID"'OO~A-

.oDD 1

:3

I - - I--b"

~

!i1

w
u

z

~

1/

V22

I.s

!l

-0 1

10

15V

VGS=O

E

1-10

Common-Source Output
Admittance vs Frequency

05
-55

145
10 - ORAIN CURRENT (mA)

Siliconix

-15

25

65

T- TEMPERATURE

I
l'\. I
1'\.1
105

145

rc)

4-31

-

I

GATE ALSO BACKSIDE CONTACT
SAND D ARE SYMMETRICAL

n-channel JFET

H

designed for • • •
•

Siliconix

Ultra-High Input Impedance Amplifiers
Electrometers

BENEFITS:

•

Low Power
lOSS < 90 IlA 12N41171

pH Meters
Smoke Detectors
TYPE

ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERSI

High Input Impedance
IG < 1 pA 12N5906-091
PRINCIPAL DEVICES
2N4117-9.2N4117A-9A.
FN4117-18. FN4117A-18A. VCR7N
PN4117 Thru PN4120
PN4117A Thru 4120A

•

Smgle

PACKAGE
10-72

Songle

TO-92

Dual
Smgle

TO-78
Chip

All songles above.

PERFORMANCE CURVES (25°C unless otherwise noted)
On ReSistance & Output
Conductance vs GateSource Cutoff Voltage'

Drain Current and Transconductance
vs Gate-Source Cutoff Voltage
g

;c

05

9fs, lOSS VOS = 10V
VGS" OV

E

~

~ 04

:J
a:
u

_

~

V-

03

a:

l/'

c

oZ

02

!ia:

/".

V f-"'"" V

~

I/

025!¥ ~ 16000

~ ~ 12000

/

~

1, ~r
. V

~

0 0

-1

VGSloff)' V010V
IO=lp.A

1

-2

-3

-4

8000

~ ~

6000

m Q

4000

~ ~

005

01

on
I

w

8~

g~

010

:J

!;t

~

... Z
a 15 ~ ~ 10000

~
i

a

VGS(off) - GATE-80URCE CUTOFF VOLTAGE (VOLTS)

lIIIiS

~
~

100

'0-

1

1000

;;;'
,
z

!;l
t;

"

~

~z
::"

~

10

10-15 j;

100

,.

10K

I~GS(Offl =-1 v.

100

VGS(off)

~

~,
ili

10-16
lOOK

.....
10

01

~

o

20

10

30

50

40

60

VOG -DRAIN GATE VOLTAGE (VOLTS)

Leakage Currents vs Ambient
Temperatu re

_100~.L.~
1 ~

V

l]wft~'111

-3V

10

100

o

1000

25

50

76

100

125

150

Reverse Feedback Capacitance
vs Gate Source Voltage

Input Capacitance
vs Gate-Source Voltage
036

0:

!
f"'"

20

~

032

19

~~
5

028

l'lz

""

;:
0

10

~

"
~

U
t-

~

~

,
J

0

J
100

1000

prVos=ov
I

17

01
10 - ORAIN CURRENT (~AI

VOS=10V

,.......
18

l!,

10

'G55= 1==

E

&"

22
VGS(off) = -4 & V
Vos.,20V
f-lkHz

u/

1. 0

~

I
I OS =6V
,

- --

p<...
"- '"S
--.. r-- r-....

~

t--

:-r-12

-16

VGS-GATE SOURCE VOLTAGE (VOLTS)

4-32

?E ~

g'2!

§

T - TEMPERATURE (GCI

!i

is

2

10 - DRAIN CURRENT (,uA)

10

I

100

gila
~ Z

111111111

10

Common-Source Output Conductance
vs Drain Current

~

4

I illllill

L

f - FREQUENCY (Hzl

C

IDt'f

~

~

~

,i'
10

6

1111

:J
C

~

z,

w

~~

Vas 10V
f"l kHz

w

g

g
6

n

1~~~A3~

lK

Common-Sou rce
Forward Transconductance
vs Drain Current

'3

"~

ill

10

J

~.~OI::~r-

~/f"'"

!.

Q

I
I
'82000
..... ~
0
-1
-3
-2
-4
VGS(oll) _ GATE-SOURCE CUTOFF VOLTAGE (V)

ur 14

w

12 I

r"-.. ./

Equivalent Input Noise Voltage and
Noise Current vs Frequency
lK

90:"

~s(on)

1:
w
~~
C"
--t ~

200fJA

IG@IO===:

g -

V

\

iii

10K

14 '"

rDS(on,: ID = 100 mA VGS = OV
gOS:
VGS=OV

'z

g ~ 14000
020::e

Gate Operating Current
vs Drain-Gate Voltage

Siliconix

\D~~OV
\
I'

"

1"24
I 020

J

.::-.

I"'--

.......

VOS=5V
VOS=10V

1
-4

-8

-12

-16

VGS-GATE SOURCE VOLTAGE (VOLTS)

....z

PERFORMANCE CURVES (Cont'd) (25°C unless otherwise noted)
Output Characteristic
(V GS(off) = -l.DV)
50
4"

VGS=D

.3

~a:

30

'{II.

"
20

~V.v

C

10

o

1--

~

I

E

,/

Wy

u

~

200

,VGS'-O'V I
VGS- -0 'Vi

I.
Z v~GS"'-03V
/) :tV
Vas'" -04V

40

--

1

...

-02

I

06V

160

IEa:

12 0

a:

a:

f/ , /

-06

-08

Ib /

I

E

0

o

-010

V

o

03V 1=

I

VG~5V

~

80

C

I

E

I

, 2

08

VV

~

VGS=

~

a:
a:
u

02

V

"z

;;
a:
c 0'
I
E

05V
07V

I I

/'
,/

...-

20

'6

'2

Z

I

04

;;
g

VGS=-06V

00

"
U

I

..

40

16

#

0

~ vf-'"
~/
~ V-

~+v
vds";~ ov

02
4
6
B
10
VOS-DRAIN.SQURCE VOLTAGE (VOLTS)

20

Output Characteristic
(VGS(off) = -3.5V)
05

VGS=~

02V

VGS'"

120

Vo =·20V

03

VGS=

VGS=

I V
'I. v 1/ VGJ=-Jov
';';:11
1/1' '/ V
~Gs=-' SV

~

VDS-DRAIN-SOURCE VOLTAGE (VOLTS)

I

VGS=-04V

'I

\;

1 1 1
:-"I'GS1''I"

/,

Output Characteristic
(VGS(off) = -2.5V)

VGS=-OlV

/

~.,:ov

£. l-

Output Characteristic
(V GS(off) = -l.DV)
tGslo

g

l-

/ v;Gs~~~O sJ-

Oi 160

~r-15V

~

VOS-DRAIN-SOURCE VOLTAGE (VOLTSI

60

I I

V-

'/

0

200

V~S"J _

//

"

u

z
;;

Vas'" cav
-04

V

V

/

c
VGS"'-07V

j~ I..-

o

VGS""-05V
Vosg

~

g

1

,..'1

Output Characteristic
(VGS(off) = -3.5V)

Output Characteristic
(VGS(off) = -2.5V)

V~I

I-

I--"

I-

-

VG1=Josv

L

VGS=-10V

/
/'

h

,
,

VG~oJ 5V

V'

lGS l_015v
;""1

,v

VGls··,lov

I
VGS=-15V

Lr-

VGS=-20V

VG~"215V

VG1s=J ov

I

VGS'"·30V

II
20

'6

12

Vos - DRAIN-SOURCE VOLTAGE (VOLTS)

o

o

·4

·8

·12

-16

-20

VDS-DRAIN-SOURCE VOLTAGE (VOLTS)

VDS-DRAIN-SOURCE VOLTAGE (VOLTS)

Transfer Characteristics

Transfer Characteristics
'00

JDs .,6v-

«
80
.;
... .\
,,-\
~
a: 60
a:

c

""

I
920

~

"z
u

~ 40

~

'..."
"~
a

-20"9

V

,~

/I

25°C
BSoC

'P~/

/

~/::,..

7'

~

'\
\

E 50 ~
~

-06

-DB

-10

-12

~~

~

I~
~

"<:: !!;;:;.J..

-04

400

-08

~1-2O°C

2S"C
8S o C

z

I'~

'"

a~

i""'I
-12

-

f-t'

C
1200

~

E

~y.

-,

-'6

-3

-2

"""

-4

-5

VGS - GATE-SOURCE VOLTAGE (VOLTS)

Transconductance Characteristics

Transconductance Characteristics

Transconductance Charactenstics

20 0

tDs·,Lf= 1 kHz

0

'"

~ 40

~
~

0

-02

-04

"

~

-06

IS::150

~

~ 100

...C
~

~

-10

-12

VGS - GATE-SOURCE VOL TAGE (VOLTS)

I _~Ds!"olvI f= 1 kHz

I'-...

1"~

Z

~

-08

~

'"

~5;

~

\~

7250

w 200

I

~

o

I

8S·C

II

600

VGS - GATE-SOURCE VOLTAGE (VOLTS)

r--v-:
5Z '2 O~ V 7 ' -2~~.C I
-:/
85'C
~ O~ 7: ~
~ 8 ..........
~ ............. ~
...
i

X~

100

~

...r:;

2OOC ,
25°C

lOV-

VDS

VGS - GATE-SOURCE VOLTAGE (VOLTS)

1
.. '6

~

1'\ ~ r-

I

I / '-l

-04

.\

150

Transfer Characteristics
800

~DS~ 'O~_

1\
200

C

...... ~
-02

13

250

~

I>< ~
k ".:\

I.........

~

I

a

-04

:it;
5Z
~

-'2

I

200

160

Z

~

08

240

~ 120

~

~

50

I-- I--

.......

1('"\

~

i

-20·C
2S"C
8S·C

~ 1/.... c?

1~ ."
.,
80

"

.'\'"

'"

~

-'6

Vas - GATE-SOURCE VOL TAGE (VOLTS)

Siliconix

I

i

a

f'lkH,

6

25;~"J_ 1---

r--... '\.
~"'"
Vi r--. ........ I"-

,

"\

40

~

JDs 2,oL

. -,

~Y.'

~

~

'? K

-2..

l1li

-,

-2

...... !,

~

-4

'"

~
-5

VGS - GATE-SOURCE VOL TAGE (VOLTS)

4-33

n-channel JFET

.H

designed for •
•
•

Analog Switches
Commutators

•

Choppers

Siliconix
BENEFITS:
• Vary Low Insertion Loss
'OSlon) < 2.5 Ohms IU290)

•

ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILUMETEI1S)

High Off·lsolation

TYPE

PACKAGE

PRINCIPAL DEVICES

Single
Single
Single

TO·52
TO·92
Chip

U290·1
Jl05-7
U290CHP-l CHP, Jl05CHp·7CHP

PERFORMANCE CURVES (25°C unless otherwise noted)
Saturation Drain Current and
Drain-Source 'ON' Resistance vs
Gate-Source Cutoff Voltage
~ 20

!

600

7

IOSS@VOS-10V

~

z"

PULSE. TEST

"

1 2f- ~~SI~ff} ~VDS = 10V

10= 10nA

~

o

rOS(on)

/

Z 0B

o

~

i
I

45

o

<"400

Z

~300
0:
i3 250
~2OD

~

in

g:g
3

1l

"-m
30

-t- r"-,

fOS{on) @lIe" 1 rnA
VGS=O

I--"

~

~_Irs

I

r"--I.£'

V

4

0

I

/6

I

\!

0 1000

"

450

f- ~~GS=O

ffi 1 6

Drain-Source Resistance vs Normalized
Gate-Source Voltage

Output Characteristic

~

;350

h'C.

50

I~ ;..-::!--

0 _10_20_30-40_50_60_70_80_90_100

l- I-"

-02V

!--I"""

-D.4V

,.....--~

I

~

~

-1.0V

I

I

10

~

09

0:

OB

!...

07

£E'

'"

V

V

_I--"
0010203040506070.80910

Leakage Currents vs
Ambient Temperature

Equivalent Input Noise Voltage vs
vs Frequency
12
VOS=5V
lo·,OmA

~

10

~

w

iL

\

'

;;

V

I

Z

~

VGS"2V

[I

I-

~

TRANSFER CAPACITANCE
12

VGS· 1V
VGS" 3V

II.

80

S

" II
~100

~

VGS-O

r!1~~~V-

180

~

lOOK

Output Characteristic
(VGS(offl = -7.5VI

Common-Source.Capacitance
vs Gate-Source Voltage
200

~-1 0

10K

lK

f - FREQUENCY (Hz)

-10

~

100

10

Leakage Current vs
Drain·Gate Voltage

4-34

1

VGSIVGS (off) NORMALIZEO

l:fnl ItJH11
>

,.

0:

-ur;

Ves - ORAIN-SOURCE VOL TAGE (VOLTS)

Drain-Source 'ON' Resistance vs
Ambient Temperature

10 = 1 mA

i2w

~

-

@

100

>

12345678910

VGS(off) - GATE-SOURCE CUTOFF VOLTAGE (VOLTS)

i"w

fos(on)

w

"
;I

VGS;!...

0150

~'OO

E,VGS@lVOS"'10V
I=VGS(Off)@VOS"'10V
I-lo-100nA

~

!;(

-lVGS=5V

I

v

JGs 16v

o
a

02

04

0.6

08

Vos - DRAIN-SOURCE VOLTAGE (VOLTS)

1.0

n-channel JFET
designed for • • •
•

•

VHF/UHF Amplifiers
Front End High Sensitivity Amplifiers

•

Oscillators

•

Mixers

•

Wide Dynamic Range

•

75 Ohm Input Match Common Gate

Greater Than 100 dB

Gate Operating Current
vs Drain-Gate Voltage

BENEFITS
•

Industry Standard

•

High Power Gain
_

PACKAGE

PRINCIPAL DEVICES

Single

TO-52
TO-72

U308-10

w

'""

Chip

'0

"''"E

U4301,4350
J308CHP-l0CHP,

TO-78

•... if--

'00

~w

U311
J308-10,2N5638-40

TO-92

;.--

lJj ~

IGon@IO

1000

~

/AU DIMENSIONSINMILLIMETERSI

TYPE

Z
l>
........
Z
N
m
N

10000

16 dB at 100 MHz, Common Gate
11 dB at 450 MHz, Common Gate

Songle
Single
Dual
Single

Siliconix

Low Noise

3 dB Noise Figure at 450 MHz

•

All DIMENSIONS IN INCHES

H

BENEFITS

I

~~

IGSS

'0

U308CHP-l0CHP, U311CHP

Dual

Chip

U430CHP-1CHP

.'7

0'

o

PERFORMANCE CURVES (25°C unless otherwise noted)
On Resistance & Output Conductance
vs Gate-Source Cutoff Voltage
90

I--

60

200

~

gos Vcs = 10V VGS" OV

\

/

i'-..V

V

c:

60 ::-J

~

~

g

140

o

i

I"--.

I--

o

~

rOSlon)

"I

80

f-J-'

g.

1

!

00

4

VGSlollj-GATE-SOURCE CUTOFF VOLTAGE (VOLTSj

'0 o

1

10

g

8

g

"-

~

I

I~

~

J

I

So

~
I
S!

'/ /
6

///

il

"

4

/I.

0:

C

~
~~

I

S!

2

~

~

~

C

I

S!

DB

12

16

20

VOS-ORAIN-SOURCE VOLTAGE (VOLTS)

o

II

. . . "1 1 1
~-~BV

......

VV' f20

~G~._,lov

'2

12

16

20

1

,.

1

VGS=O

J !12v

-I-

Gs

1/

V
V

--

tsLL

-I-

Lliav
J

Gs : _DIBV

VGS=-10V
VGS=-12V

o
20

Vas-DRAIN-SOURCE VOLTAGE (VOLTS)

Siliconix

IBI

Vas"'-12V
DB

2.

-~Gi-+

V' f-

04

-

VGS"'-06V

Output Characteristic
(VGS(off) = -1.7V)

lJ,lv
LGJ._,I.v

VGS=-2SV
04

V

/

Vas-aRAIN-SOURCE VOLTAGE (VOLTS)

I
LsU,v

Iv f-

""z

1 1

J;

100KHz

~Gslo

40

0:
0:

V~-20V

f/

10KHz

1I.r

So

1 1
1 1

1KHz

60

I-

II
f!I/

100Hz

Output Characteristic
(VGS(off) = -3.0V)
;;

VGS=-1 5V

,

/

IZ

i

v~s= I-O~V_
VGS=-04V

FREQUENCY (Hzl

+_ re-

/IVG :.-10V

-,.

,J, -

VGS-D.I_

~,....

'1/

'2

4

1\

10Hz

VVGO·p
VGS.-~ 5V
16

-'2

-B

I

1

Vos= lOV
10= lOmA

o

I

:----+-

-4

'0

IIIIIIIII

2

Output Characteristic
(VGS(off) = -3.0V)

~

o

VGS-GATE-SQURCE VOLTAGE (VOLTS)

l!

-4
-8
-12
-16
VGS-GATE-SOURCE VOLTAGE (VOLTS)

0:
0:

.

f.,.(

~

Output Characteristic
(VGS(off) = -1.7V)

6

o

""

~

10

'o"

i-

~

~

/'

100

fREQUENCY (MHz)

Output Admittance Common Gate

-30

"

1

-Org

~

-50

~ 090

~ 086

1000

FREQUENCY (MHz)

/

E
Z

600

fREQUENCY (MHz)

~

Reverse Reflection Coefficient
Common Gate

r-.

I

f

VOG=10V

~ "em '"

~

-::2""

~

3••

w

ril

FREQUENCY (MHz)

IS221

i

V

I

/
100

:=e

.§

!2

"'-1

I-"

l

~

.;
IS'21

'b

10

Reverse Transfer Admittance
Common Gate

;;

80

i

-b

4: 521

065

~

....,

--

-40

/

070

'O=10mA

w
u

-50

075

vos·tOV

1

VOG'" tOV
Ie-lOrnA

15211

.........

Forward Transfer Admittance
Common Source

Forward Transfer Admittance
Common Gate

'...

.....

.,

...

01
100

300

6DO

FREQUENCY lMHz)

Siliconix

1000

100

200

50.

FREQUENCY (MHz)

1000

n-channel JFET

H

designed for • • •

Siliconix

•

High Frequency Amplifiers

BENEFITS:

•
•

Mixers
Oscillators

•

High Power Gain

•

Low Input Capacitance

All DIMENSIONS IN III.CHES
1.41 L DIMENSIONS INMILLIWiTERSI

TYPE

PACKAGE

PRINCIPAL DEVICES

Single
Dual
Dual
Single
Dual

TO-92
TO-78
TO-71
Chip
Chip

J300, J210-12
2N5911-12, U257 U443-U444
U440-41
J300, J210-2CHP
2N5912CHP,U257CHP
U441CHP, U444CHP

PERFORMANCE CURVES (25°C unless otherwise noted)
On Resistance & Output
Conductance vs GateSource Cutoff Voltage

Drain Current and Transconductance vs
Gate-Source Cutoff Voltage
350

'2

9fs& lOS VOS'" lav
vGS",av

Vv
9h/

//
//

~

l\ros{onJ@lo=lmAvos=av
90s@VOS= laV, VGS= OV

,."z
'0
"-i

~
1
~~

"I

c:~

5l;-;;

;j"

««

~~

Ira
]0:
fl

no

lOSS

~~

7 3

g.

VGSloffl

v~sorv- • !

'nA I I I

p.~V

~

V
150

1\

p

~

~~

V

300

k

Gate Operating Current
vs Drain-Gate Voltage

250

/

200

~ ~ 160

'00
90S

V

~

50

•

VaS(off)-GATE-SOURCE CUTOFF VOLTAGE (VOLTS)

g I!!
z «

~

'00

10 @ JD-----t---ID~2mA

-2

-3

"?i "I
Z
0
"~ 5

'0

-4

-5

lOSS

g. 52~

3'

!

1°

-1

1000

;:

1> .....

1VySI!,,11 v~so'tV 1'"1'

-0

w

-i

'00

/

~~

5

" "~
~
c:

0

50

.-..

~

0,
a

-6

4

8

12

16

20

24

VDG-DRAIN-GATE VOLTAGE (VOlTSI

VGS(offJ-GATE-SOURCE CUTOFF VOLTAGE (VOLTS I

Common Source Input Capacitance
vs Gate-Source Voltage

Common Source Feedback Capacitance
vs Gate-Source Voltage

Equivalent Input Noise Voltage
vs Frequency
100

\

I~

VOS"O

.x.
......

f\:: vor

VOS=5

p--

"'05"10

.... l.X ......

,\

:;.
OS

ov

~

>

~ ~ .......

vo~o,ov

~
I

~
....... ::--- h' t--

-4

-'6

-12

-8

-4

"5

12

w

~

.s>-

I"

~
c

-'0

"~

~

'-::

"'
>-

4

~

2

:il
a:

li!
-2

--3

-4

-5

VGS - GATE SOURCE VOLTAGE (VOLTSJ

I
~

1\ r--,

6

«
-5

'00

'0

-16

+12~

_+125• C

=t:r 'i

I""- .......

-,

)'0

~

~

il

!IIII
gts@f=lkHz
VOS"'15V

11111

8

I

~
:il

~

-3

-4

-5

I

.£

I

L

Wi= 'O~A+--I
24mA~

//
~

4

~

~

\~

VGS - GATE-SOURCE VOL TA(3E (VOLTS)

Siliconix

100](

16:nA

6

~

~
-2

~

"

5

L
0

~

" V-

'OK

'K

f - FREQUENCY 1Hz!

Forward Transconductance vs
Drain Current

~~~;01tHZ
-<;5,1:- I--- f- .:>U~+25'~_
+12S"C

1 '0 ......

-,5

;;

-,

-12

Transconductance
Characteristics

Transfer Characteristics

I

-8

Vas-GATE-SOURCE VOLTAGE (VOLTSJ

VGS-GATE-SOURCE VOLTAGE (VOLTSJ

~

1~
0'

o

"'
z"
~
"
.9

'0

w

"

VOS=5V

Id'
a

01

02

as

'0

10 - DRAIN CURRENT (mAl

4-37

-

PERFORMANCE CURVES (Cont'd) (25°C unless otherwise noted)
Output Characteristic

Output Characteristic

Output Characteristic

(VGS(off) = -a.8V)

(VGS(off) = -a.8V)

(VGS(off) = -S.OV)

1-1-~

05

Vas·

VG!'J.w'
I

/11

V

I

0'2

I
I

i

v~.'-oL I-t-

~
II:

I

8

I

'11/
i.-

008

;;

:!i

~GsL+

I 004

g

'I

tlL

....

I

Vas--03V

"-

o

05

•o

Output Characteristic

(VGS(off) =-1.0V)

(VGS(off) =-1.0V)

GS-

Vo." - ..IV

0160

I I
I

I

--

fl

L
0'

/

-

-

10120

...~
B

I

VOS,,-o4V

z
;;

I

I

vGs·-~fJV

II. /'

~

o

05
1.0
Vas-DRAIN.SOURCE VOLTAGE (VOLTSI

Output Characteristic

(VGS(off) = -2.8V)

(VGS(off) = -2.8V)

I 081-~~~~~~~
I

:c

..illoS
.
"
u

!! 2

~I

g,

i.-'"

0.•

.."

~'6

I

Vi"""

u

I

,..

V"

I

g ,

Ylgs=g,gs+.bl9S
30D

VOS=-2.0V

••

~

~~

--

VOS=-2.6V

o.,

1000

m

T--g,~,-

~
a:

2•

~

100

-bn

-~ 7"

I 0.0 1

VOS-DRAIN-SOURCE VOLTAGE (VOLTS)

Silicanix

lo"'10mA

!I

. ,.

BOD

Reverse Transfer Admittance
vs Frequency

VG.'-"'sv

VG~=-1.~V

YtSS-UISS+Jb,ss

COMMON GATE

FREOUENCY (MHz)

=-3.5V)

VGJ=-1L

Z

~10

VOS-DRAIN-SOURCE VOLTAGE (VOLTS)

4-38

V

!Z

Yo ".z!.v
I

~f-""""

0'100

./

Voo-,OV

2•

."". VGS=-Z.ov

COMMON SOURCE

,

20

voJ=o

1

GS=-'.&V

./

31---','7 r--

"-lav

,.

.

,,............,

2'

vos-'t -

.!.'I /

f///
1/1/ / '
Ij:Y

(VGS(off)

,

vO;'·-,.4V
12

I---

b= ...
6f==",

6

Output Characteristic

I / /'
'I V

4
B
,2
16
20
VOS-DRAIN-SOURCE VOLTAGE (VOLTS)

VOS"-1.0V
=-12V

Output Characteristic

3

VGS=-3 BV

o

Vo

VOS-DRAIN-SOURCE VOLTAGE (VOLTS)

1,1 1/

vGs=-d 5V
VGS=-30V

VOG=10V
lo-10mA

VOS-DRAIN-SOURCE VOLTAGE (VOLTSI

4

VGS=-'sv
VGS=-20V

Input Admittance vs
Frequency

Vos,,-OGY

05

V~"~0'5~t
I I I

VGb"_,'.v

o

2.

Vos"-OGY

Vo

VOS"!'I

JGS ~ _015V

V

I

E

,/.,.,-

(VGS(off) = -3.5V)

'0

:o ,. ~

V....

Va =·2OV
0.26

"z

u ,.

VOS· -04Y

I ......

04

vds..lov

Vas· -02Y

I

'.2 I-I-Hh"""If-::*"";:;"T:'':;:::-I

f-

I
V

20

v,,~.ol

oS

"9

. ,..

Output Characteristic

.

--

VG~•.J.

26

VOS-ORAIN-SOURCE VOLTAGE (VOLTS)

:c , .• I--I--+--hfl-A,~

~
~

ffi

VGS",-04V

•

Vas=-3 BY

05
VOS-ORAIN-SOURCE VOLTAGE IVOLTS)

a:
a:

Vas"-o sv

•a

I I

i.-'"

j~

••

1.

I I I

0040

Iw.

I

g,

VQS=-30V!

i---"

(VGS(off) = -5.0V)

Vas" -03V

Vas"-0 7V

1//, V. V

2

3.

~o.U2V

.....

:!i

VOS"-05V

IVI V V

U

I I
v~s·-r·'v;-

Output Characteristic

Vos" -0 1V

0080

/'

.:. ......

I V,Sj

"...-

JG)-oJvi

"
~

VGS·-20~-1-

J
I

~ 3

Ie

I I I

VGS--0711

'/.

!Z

08=-05

Output Characteristic

lJ IL VGr-'j'V

4

oS

8
12
16
20
Vos-DRAIN-SOURCE VOLTAGE (VOLTS)

10

VDS-DRAIN.SOURCE VOLtAGE (VOLTSI

06

:c

VGS,,-o4V

Vas" -05V

o

Vos"

lGsU,v

......

Z

Vas--D3Y

'/'

-

I

Vv~s.~, °t+1I-

VGS~OI

I

-'n

...

.
I
.,~-

600
300
FREQUENCY (MHz)

1000

PERFORMANCE CURVES (Cont'd) (2S0C unless otherwise noted)
Output Admittance vs
Frequency

Forward Transfer Admittance
vs Frequency

:g

10§~
VOG" lOV

10= lOrnA

bogs and boss

!

:::;\'l10~--!!II

:l
c

Of,

~

~

90gSandgoss

r'~'fll
~l=

OO~O~O----~~~30~O~~~.O~O~~'UOOO

FREQUENCY (MHz)

FREaUENCY (MHz)

Siliconix

4-39

I

p-channel JFET

GATE IS BACKSIOE CONTACT
S ANO DARE SVMETFlICAL

H

designed for •••
•

Analog Switches

•

Commutators

•

•
•

Choppers
Integrator Reset Switch

Low Insertion Loss in Switching Systems
RON < 75 n 12N5114)

•

Short Sample and Hold Aperture Time
Crss<7pF

•

High Off-Isolation 1010ff) < 500 pA
PRINCIPAL DEVICES

PACKAGE
TO-18
TO-92
Chip

TYPE
Single
Single
Single

ALL DIMENSIONS IN INCHES

Siliconix
BENEFITS:

2N5018-19. 2N5114-16. U304-6, VCR3P
J174-7. J270-1. Pl086-87
2N5018CHP-19CHP.2N5114CHP-16CHP
U304CHP-6CHP. Pl086CHP-87CHP
J270CHP-271 CHP

(ALL DIMENS/ONS IN MltL/METERSI

PERFORMANCE CURVES (25°C unless otherwise noted)
Output Characteristic
(VGS(off) = +1_5VI

VG~-+Lv~ - r-

VGS=O

i

I I

1....

I

1
5

VGs=+04V

~

II:
II:

:>
(J

z

II:
II:

I
II, /

1

~

c

I(/J

!!

rJ

I

:>

V

4

Z

V-

c

I--"

~

......

I

/'

!!

vGi +J 8V

Iii.

o

1/

(J

~ VGS=+06V

,/

1£ ......

o

10V

05V

I

I
II II
'III

!I V

I

srrvtt
I

VVGS

V

~

"

V

i

15

~(J

",""

(J

!

~

10

II:

o
I

k

i'

20

I

I,V

IO"'1,..A

3
8

On Resistance and Output
Conductance vs Gate-Source
Voltage
300

H

go,
rOS(on)

r-

If
I

o

1\
\

\

It

~./

VGS"''''' sV

goo/,

VGs:::+25V

20

10

@VOS=15VVGS=OV
@IO= 7OO IlAVG=O

!:i

1

.....

lOSS

./ VGS(off)=VOS=-10V

VGS(offj-GATE-SOURCE CUTOFF VOLTAGE (VOLTS)

VGS=+20V

o

05V

./

/

20

vel=+1 0 v

t'~-

VOS-DRAIN-SOURCE VOLTAGE (VOLTS)

V

g:

E

~

/

I
If

~~40

+09V

18

.....

I/,
fl ".- -I- r-

:>

025V

~j:

II:W

,.

-

/

60

11:

~

S
....z

=t 15V

!

Z

VGS"~

12

/Of,

II:

0_

G = +08V

8

80

Z

;;

VGS"+ 0 6'+l

r---t1:

;( 20

V~+20V

/

vGS-ov ,...
l

~

25

I

I

uts&IOSS@VOS"OSV

Output Characteristic
(VGS(off) = +3_0V}

Output Characteristic
(VGS(off) = +3_0VI
VGS-+05V

---

4

100
VGS=+OV

Ves-DRAIN-SOURCE VOLTAGE (VOLTS)

VOS-DRAIN-SOURCE VOLTAGE (VOLTS)

VGS=:O

'"

--

I

I- :""1GS·~
1Gs·~
l- I1-1-- V~
VGs.,+04V
I-r-~GS=+1.0

~

VGS=+10V

ov

Drain Current & Transconductance
vs Gate-Source Cutoff Voltage

Output Characteristic
(VGS(offl =+1.5V)

o

VDS-DRAIN-SOURCE VOLTAGE (VOLTS)

./

4

~
~

I

rOS(on)

J
6

B

VGS-GATE-SOURCE CUTOFF VOLTAGE (VOLTSj

Output Characteristic
(VGS(offl = +5_0VI
05

50

-it

J
I I
~e/~
4tt, ~.r-

-

r- 7'r-,:.,(j

'I

s

--

o ~
o

.... l-

VGS=+40V

(J

25

r

Z

~

~

c

I

!!

II

/'

7'

--

;'GS~" ~v

i--

r----tG~., ~v i;::;;
VGS"'+20V

i;::;;

VGs=+26V

t=

05=+40V VGS"'+30V
VGs=+35V

10

o

10

VOS-DRAIN-SOURCE VOLTAGE (VOLTSj

Siliconix

20
~

<..

4

o

o

~

8z
o

./

2

4

2 ~

" ...... -

/'

-1

o

V

V

12

16

VGS-GATE-SOURCE VOLTAGE (VOLTSj

PERFORMANCE CURVES (Cont'd) (25°C unless otherwise noted)
Output Characteristic
(VGS(off) = +8.0V)
'0

Output Characteristic
(VGS(off) = +8.0V)
'00

1
III VGS-+2V I

Vas a

Vos

VGS-=+lV

~!-

1/

VGS=+3V

-'
II

1/1 :/
W! r/ 1/

v, V

~GS1'4vL

V

V

I 1/

II, l::i: V

[AV

I I

II::"'==:

"f

.§

Vas = -15V

w

;t -8 0

u

.§

2

>-

~

~

~

"c

°t"

-40

"c,
~ -20

•

2

§

""

2

"">il

r-...

~

" ""

"11

~

VGS - GATE SOURCE VOLTAGE {VOLTS)

§

~ 16

,.

I<
I

;Ii

,
,
,

u;'

2

o

20

VOS;.10

o

-4

-8

'2

'6

10-13
VOS"'-10V

lOSS = -9 a rnA

@

MAX

10- 14

~z

C;
c
>

AVG

:!!
0
z

1'1.
MIN

10- 15

"

,::
..i

,.

VGS - GATE-SOURce VOLTAGE (VOL lSI

~

~

I

2

~
n

""

6

,,,
I
2

~
w

B

4

~.:>'

Equivalent Input Noise Voltage and
Noise Current vs Frequency

9fs@f-lkHz

0

VOS"'S

VGS-GATE.SOURCE VOLTAGE (VOLTS)

Vos -15V

I'

VOS"O

B

'K

4

~ rx

~
I

Transconductance
Characteristics

-'00

1l

~

Vas-DRAIN-SOURCE VOLTAGE (VOLTS)

Transfer Characteristics

-6

2

!: 24

VOS"'+60V

'0

VOS-DRAIN.SOURCE VOLTAGE (VOLTSI

iii~

w
u

-~ I::;;

"'==: t::: I

'0

o

it
Eo 32

I-

VOS"'+5 OV

VGS::;'V

o ~ l-

I
Vos""+1 ov

Vos=+3 OV

II
I I

V-

fol

'LL f-""
'L ~ r- r- VDS~+4 ov i::;:
V
l - f-f-

VGS-'5V

I--'

!-

Common Source Input Capacitance
vs Gate-Source Voltage

10- 16

f - FREQUENCY (Hz)

l1li

Siliconix

4-41

m

u
en

H

p-channel JFET
designed for •••

a.

•
•
•
•

lip

10" l/JA

2

1055,91$

TYPE

PACKAGE

PRINCIPAL DEVICES

TO-92
Chip
TO-72
TO-1S

2N5460 -65
All of the above
AVailable thru the factory
Contact local sales office

9

6

,

V

~

"1 V

0/

-12

./

/

/

'/

1

-2

o

0

IIOS

VGS~

~
~

~

u

z -

~

VGS"'2511

VGs=30V

-12

-20

-16

Vp

V05=-15V

IIOS

~

i.;'

'j VGS"r v
VGS!ofl "4SV

.... ....

VG "'3SV

.....

I'

1

1

vo§:,L

- 2

-

4

-6

-8

-TO

VOS - ORAIN TO SOURCE VOLTAGE (VI

Output Characteristics

Output Characteristics
-2

r;~---,--~--~~--~~I00

ras

VG "'25V

1

-8

IIOS - DRAIN TOSOURCE VOL lAGE (VI

ON Resistance & Output Conductance
vs Gate to Source Cutoff Voltage

'"

'I.
2jj

Y I I I

VGS.20Vt.1:f

, '1'1 ~

0

VG =3511

~~~~,-«V

I II
If
,/'/

z - 6

20V

1.00"""

-,

0

-f

~

511

1 OV

..'/

lip - GATE TO SOURCE CUTOFF VOLTAGE (V)

g

VG~= 1511

I"'""

-,

I- 8
~

",

-6

6

vos-

-

-8

V

Output Characteristics
-10

v~s=ov

VGSlolt) =4511

-10

L

1105=-'511
IIOS= 0

Lowi n <15nV/$zat10kHz
Low leakage < 10 pA at 30 V

Output Characteristics

lJS/

VDS~-15V

•
•

Single

Drain Current & Transconductance
vs Gate to Source Cutoff Voltage
-1

BENEFITS;

Amplifiers
Sample and hold
Choppers
Analog Switches

ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERSI

,

Silicanix

,
VGS(olll'"

SV

VGS" OV

0

ID~-100/JA

80

-2 0

.

<" -400 r--r---H'-'I--..'
~

z

~-300r--+*.~~~-+-4__~+-r-~

/

6

F

2

/

8

vds., 2V

'"

vds .

'"

4V

Vas = 6V

/'

VGS

M

Bv

V~"'10V

4

-0

- 10

lias -

lip - GATE TO SOURCE CUTOFF VOLTAGE IV)

DRAIN TO SOURCE VOL.TAGE IVI

10000

16

Noise Voltage vs Frequency

20
IG(Or'lt@ 10

sI

1000

,Q

0

\~~

1

~
u

z

~

U

'5", f'..

~ ION...

,

~

u

~,

-10

-20

-30

-40

so

IIOG - DRAIN GATE VOLTAGE IV}

4-42

-60

-

liDS = SV

c,u
C 5S _ _ _
r
0

0

~

\,5 V

10
VGS - GAlE TO SOURCE VOLTAGE (V)

Silicanix

~

"':;<

~

VOS"-5V

Vos

~

~

~'5V

Vos"

r>

•,
~

........ ::: ::.- -:..-:.r-=:;,;

j
1

~

-20

Vos - DRAIN TO SOURCE VOLTAGE (V)

Capacitance
vs Gate to Source Voltage

Gate Operating Current
vs Drain-Gate Voltage

- 12

12

2

0

~

~

~
0

>

~,
,~

100

lK

10K

F - FREQUENCY IHt)

TOOK

high voltage
protection Cliode
designed for •••

D

0020·
(00508)

A

j
,~.
-------t-----'-","-,.

BENEFITS

• Limiting Current
• Voltage Protection
• Voltage Oecoupling

1

• Series element
• Two terminals

• Simple to use
• High breakdown voltage
(JR24OV -240 volts)
ALL DIMENSIONS IN II(CHES

• Low Cost

(ALL DIMENSIONS IN MILLIMETERS/

PRINCIPAL DEVICES

PACKAGE
TO·92

TYPE

Single

JR135V. JR170V, JR200V
J R220V, J R240V

PERFORMANCE CURVES (25°C unless otherwise specified)
Dynamic Impedance Vs.
Anode-Cathode Voltage at
Temperature

Output Characteristic

.200

1

900

m

,..-

a:
a:

U

600

;i

~

-

-.'"

300

.....

:Ii

/

i''c"

C

80

120

160

200

240

o

280

o

50

i:

--

400

z

.

~

iii

'"Ca:

200

UI

..

~

.
I

c

;;

-- ......

.......... ..........
150

75

100

'\

155

iii
::;

-15

~

-35

\.

{!:-55
-75
230

,..=

200

250

I"\..

240

250

250

270

2BO

.25

'"

300

BV vs Temperature

280

'"'-

480

+

320

iii

260

~

l-

f- ~OS (MHI = .lIFI.lVF
ZFl (II,

= .lVFI.lIF

I

0

0

ISO

290

BVAC-ANODE·CATHDDE VOLTAGE (VOLTS)

r--. r-.....

240

IF=.m?' ............

r-

220

I"SO

25

'\

300

.SO

25

I!!

~

.El
.!!-

100

o

+45

640

JR~V

--

300

-H;5

::;

Family Curves

JJ

I-

"

\..

105

+85

ffi..

800

=
- ~r

0

"-

100

Free Air Temperature
Dissipation Derating Curve

!

25·C

:: \..

VAC-ANODE-CATHODE VOLTAGE (VOLTS)

VAC-ANODE-CATHODE VOLTAGE (VOLTS)

500

\

~ .25"':C

N

40

\. -55·C

--

~
u

0

o

~

51

C

o

~

U
Z

Q

I

UI

UI

L

/'

UI

9

~

a

/

k-fo"""

/'-

I-

"

165

/
./

Breakdown Voltage Vs.
Temperature

I- --

I
4

TA-AMBIENTTEMPERATURE IOe)

10

6
VF(VI

-

200

.80
-55 -35

0

25

45

65

85

105 125

TEMP rCI

IF vs Temperature
./

600

..,./
VF

_ 400

'"

.El
.!!-

/'

=20V ..,./ ........-::: ~
,......

:::...-'/:: ~

~ -:;::::;200 ,.....
o

o

25

50

75

100

125

TEMP ("CI

Siliconix

4-43

"',,

'

,
,

'.

,

I

'.'

'"

"""

Selector Guides _
.,'

,',

.'

Siliconix

,

,',

'

"

>

'

"

:"

'

:!

Tips on Selecting the Right FET
for Your Application

1

o
::I
en

-..~
CD

The "Product Specification," a short form version of technical data, will provide you direct
reference to Siliconix part numbers and a condensed version of technical specifications

-.

..
_.
..
::I

ca

:r

IF YOU ARE NOT FAMILIAR WITH THE FET PARAMETERS YOU NEED:
1.

Turn to page 5-4, "How to Choose the Correct FET for Your Application." Using this guide, determine the
important FET parameters.

2.

Next, turn to page 5·6, "JFET Geometry Selector Guide." Using this guide, choose the appropriate
geometry.

3.

Once you have chosen a geometry, turn to "Geometry Characteristics," section 4 of the catalog. Here you
make the choice of a suitable part number.

4.

Now that you have the part number, you will find complete electrical specifications of these products in the
"Data Sheets," section 2 of the catalog.

CD

;a

ca:r

,.
"II

~

""I

IF YOU ARE FAMILIAR WITH THE PARAMETERS YOU NEED:
1.

Turn to the "Product Specifications," pages 5·9 through 5·18 to determine the proper part number(s).

2.

Double-check your choices against the data sheets, and select the part most suited for your application.

~

C

""I

:..
-.
"D_.

'V
'V

-

..
o
::I

l1li

Siliconix

5-1

Small-Signal FET Application
Selection Preference
Additional Information

"

't,-'"
 100 MHz

P

S

p

P

HF> 400 MHz Prrme
General Purpose Amplifier

P

P

Low Noise Amp (10 Hz anI

p

S

S

P

S

low Noise Amp> 50 MHz

S

P

P

p

S

P

P

P

p

p

P

P

P

P

P

P

P

P

S

S

MIcrovolt AmplIfier

P

S

P

P

P

Low Leakage Diode

P

S
P

S

P

P

P

P

S

P

P

P

P

P

Drfll Srngle Ended Inp Stag

S

Hrgh Slew Rate Diff Amp

S

S

p

Oscillator

S

P

P

Voltage Controlled Resistor

S

P

P

P

P

P

Analogi Digital SWitch

S

Multiplexing

P

P

P

P

P

P

P

P

P

P

P

P

P

p

p

P
P

P

S

P

P

P

S

S

P

Choppers

P

P

p

Reed Relay Replacement

P

P

S

P

p

P

p

p

S

p
S

S

P

P

S

p

p

p

p

p

p

p

p

p

p

P

p

P

P

P

P

p

P
P

P

Sub pA Dual Drff Pair

P

Sample Hold

P

p

S

S

S

S

Buffer Interface to CMOS
Matched SWitch

S

Current limiter
Current Source

P

P

P

P

P

P

P
P

S

P

Low Leakage Dual Diode

Hybrid Chips

P

P

P

S

Active Filter

S

P

P

P

P

P

P

p

P

S

P

Electrometer Preamp

< 1 5V

(j

PS8 PSCD NCl NKl NKM NKO OMCB iRMA HNZ MDN NBA DMCA/~

P

P

S

P

.,

P

P

S

AGC Amplifier

P

~~~

~

P

Dual Dlff Parr

Smoke Detector Input

...~
~q)~

aDS'

t ~~f t:;~tJ~~

P

P

P

P

High Frequency Mixer

.J # ~~

'$!l.,"ljr l ? ll;f, '/;llli/l~'?",
S

~J

<0 <0
~.t

,>e;~ ...

~ ~"

~ t'\I~"'''z
1'\1
!':i
"
rJl
J'
~"'~t::l'?$§~"1-

Popular Product
Type

'
~~.§9
~Cb.....

,~

nrc

f ~ct' ~. ~ ~r

Battery Operated Amp

~f; ~t

J-.
'"

~

f$.~dl'll

p

S

LV

P

p

P

S

p

S

p

P
S

S

P

LV

High Voltage Protection Diode

p

P

P

P

P

p

P

P

S

p

Military Application
As an option, Sillconlx offers all hermetically packaged
product processed to MIL·STD·750. For Information,
contact your local Sfltconlx Sales Office or Silicon IX,
Incorporated direct.

LV = Lrmlted

5-2

Silicanix

P e:;. PfJme Choice
S

= Secondary (alternative) Choice
Value

P

Small-Signal FET Product Selector Guide
Application

Detail
Application
Audio
Buffer
Oifferential
High Input
Impedance
High Frequency

AMPLIFIER

FET Input Op Amp
Low Oistortion

Low noise (en).
9ls/gos
Low IG. high 9ls
Good matching VGS.
91s. lOSS. IG
Very low IG
(e.g .• MOSFET)

Preamplilier

Operate near 10ZO. high
91s/10 ratio
High 9ls/Ciss ratio. NF

Commutators
Oigital
Integrator Reset
Sample and Hold

Fast switching time
ros/IO(off) switching
efficiency
LowC rss
Fast switching time

Current limiting
Relerence Current
Source
Biasing

Low goss.
low VGS(off).
high BVGSS

VOLTAGE
CONTROLLEO
RESISTORS

Gain Control
Amplitude Stability
Attenuators

High VGS(off) for wide
dynamic range and low
distortion

VHF

RF parameters. NF. high
9fs/Ciss ratio.
10wCrss

UHF
Oouble Balanced

Class A
OSCILLATORS
Class C

;9Is/gos
; l> VOS/l> VGS
@Io;const

ROS(on)
VOS(on)
10(off)
Switching Times

ROS(on)
vs.
Capacitance

9ls
90S
lOSS max

Very low ROS(on). High
lOSS
Low Crss

CONSTANT
CURRENT
SOURCE

MIXERS

Voltage
amplilication
lactor I'

Unimportant
FET Parameters

Good matching VGS.
91s. lOSS. IG
High VGS(off) compared
to signal ampliWoe
Low VGS(off)
Lowen. in. low I" noise.
10wNF

Analog Gates
Choppers

Major
Tradeolls

High 9ls/Ciss ratio. NF.
RF parameters

Low Supply Voltage
Low Noise

Video

SWITCHES

Important FET
Parameters Required

lOSS
vs.
BVGSS

Matching
characteristics
Good 9fs at operating
frequency
Low Ciss lor VHF
operation

9fs
vs.
Capacitance

Siliconix

Prelerred
Parts
2N4339·40
2N4867·69
J230·32
J202·4
J30S-10
U308·10
2N5911·12
2N4117A·19A
U401·6
U421·6
2N6905·7
2N6908·11
511000·20
511100
55T201·4
55T4416
55T30B·l0

S0210·15DE
5D5000
2N4091·3
2N4391·3
PN4391·3
Jl0S-l0
Jl05·7
U290·1
2N5432·4
2N4856·61
2N5114·16

91s. ROS(on). 10(011).
VOS(on) switching
times. RF para me·
ters. capacitance

CRR Series
J50Hl
J552
Any J·FET

9fs. BVGSS. lOSS

VCR Series
Any J·FET

rOS(on)
VOS(on)
10(off)

U350
U430·1
U440·1·3·4
2N5911·12
U308·10
J30B·10
50210·15DE
5i8901
2N4416
PN4416
U308·10
J30B·10

5-3

-

Small Signal FET Application/
Parameter Importance Guide

!/iiJ;iiijlj/tiJ
S'
~p

KEY PARAMETERS

\;:,.

~

Q;js,

Low Current Amplifier
Low Freq Amplilier < 100 Hz
High Freq Amplilier > 100 MHz
HF ;:: 400 MHz Prime
General Purpose Amplilier
Low Noise Amp (10 Hz en)
Low Noise Amp> 50 MHz
High Frequency Mixer
Dual 0111 Pair
AGC Amplilier
Electrometer Preamp
Microvolt Amplilier
Low Leakege Diode
Low Leakage Dual Diode
Smoke Detector Input
Battery Operated Amp < 1.5V
Dill/Single Eneed Inp. Stag.
High Slew Rate Diff Amp
----Active Iilter
Oscillator
Voltage Controled Resistor
Hybrid Chips
Analog/Digital Switch
Multiplexing
Choppers
Reed Relay Replacement
Sub pA Dual 0111 Pair
Sample Hold
Buffer I nterfaee to CMOS
Matched Switch
Current Limiter
Current Source
High Voltage Protection Diode

,

....(!j

Min.

Max.

0

,

,

0

0

,
0

Max.

~(!j.::!!

Max.

0

'"

~(!j

Min.
Max.

D
(0)

,

,

~

'"

....Q

Max.

.

/'
I'
I'
I'
71*
I'

Min.

,

0

D

'/D

,

0

,

~

!'.>

0,0 ~~Q~

Max.

?

,
(')

,

,
,

?

,

Max.

?

0

0

,

0

0

,

*

(')

,
0

·
?
*
0

,
,
,

,

,

,

,
0

,

·,
·

..

'/'
/'
I'
/*
/'
I'
'/*

'I

,

,

,

0

,

'/

(')
(')

,

,

,

,

,

Max.

-..If

Max.

?

,
?

G
G
G

,

?

?
D

,

·

?

,

·

D
D
D
D

?
D
D

D

?
?

D

.

?

·
,

D

,

,

,

.
0

,
0

0

r

'/

0

0/

0

'/
0/

,

I'

,
(0)

0

./

or
'r

"
0

'/'

.,
0

"/ - Indicates "Min"

I' - Indicates "Max"

D - Desired "nominal" limit - rarely critical

(0) _

Indicates Parameter in Parenthesis

G - Guaranteed by Ciss- C rss - 9,s- and device design

Siliconix

?
?

,
,

.
0

D
0

'/
?

,

- Important FET Parameter - Required

,

./

0

·,

c.i~

Same as application area

(')

,

0

~

?
?

(*)

D

0<;

b

,

G

D

?

q,~

.

D
D
G

0

,

Min.
Max.

~

If

§:'

~

:!::,f. \;:,.

0

? - Important lor some applications

5-4

o:~

0

,

e' q,~

~

0

0

··
·
,
·

I'
I'

(')

·
0

'/*

·, ·
,

~

Min.
Max.

I'

IfR(!j

g; ~

@I

...Q

I'
I'

0
0

,

....Q

,

,

,

w
~
,~~

';;/:

D

,
0

~

.....Q

~(!j

~

,..(!j

~

10

(5i

LIMIT

~

~

,

0

Application

Detail Application

Audio

AMPLIFIER

Important FET Parameters Required

Low IG. hIgh 91s

Differential

Good matching VGS. gls' lOSS. IG

High Input
Impedance

Very low IG leg .• MOSFET)

High Frequency

High 9fs/C,ss ratio, NF, RF parameters

FET Input Op Amp

Good matching VGS. gls. lOSS. IG
High VGSloff) compared to SIgnal

~

on
Voltage amplification

factor JJ.
= gl,lgos

::r
o
o

ROSlon)
VOSlon)
10(011)

Low VGSloff)

IS

Low Noise

Lowen.Tn. low l/f nOlse,low NF

::r

Preamplifier

Operate near 10ZO. hIgh glsll 0 ratIo

= l>VOS/l>VGS@ 10 = canst

Video

HIgh gls/C"s ratIo. NF

Analog Gates

Fast sWitching time

Choppers

'OS/IOlofl) switching effiCIency

Commutators

LowC rss

Digital

Fast switching time

CD

n

..

o

ROSlon)
vs
Capacitance

Integrator Reset

Very low ROSlon). High lOSS

Sample and Hold

LowC rss

...

Switching Times

i...
...

91s
90S
lOSS max

~

Current Limiting

CONSTANT
CURRENT
SOURCE

:z::

Low Supply
Voltage

amplitude

SWITCHES

Unimportant FET Paramete ..

Low nOISe len I. gis/gas

Buller

Low Distortion

Major Tradeoff.

Reference Current

Source

Lowgoss.law VGSlaff)' hIgh BVGSS

IDSS
vs
BVGSS

91s. ROSlon)' 1010ff). VOSlon)
sWltchmg times, RF parameters
capacitance

BiaSing

.
~
.

i'
C

VOLTAGE
CONTROLLED
RESISTORS

J>

Gain Control

Amplitude StabIlity

High VGSloll) lor WIde dynamic
range and low distortion

"a

gls· BVGSS. lOSS

-"a_.

"U

Attenuatars

...o_.

VHF
MIXERS

UHF
Double Balanced

::a

RF parameters, NF. high 9fs/Ciss ratio,
lowC rss
Matching characteristics

'DSlon)

IDI

VDSlon)
IDlolf)

OSCILLATORS

Class A

Good'9fs at operating frequency

Class C

Low C1SS for VHF operation

Silicanix

91s
vs
Capaci tance

5-5

.=
~
...2

Preferred Parts

Basic Circuit"
vp•

voo

-

Rz RO

f---o

.,0-- ..to,

Iii
II.

30

I
"..•

Voo" 15
Vss = -15

MU

MU

2K
330
330
2K
330
330
4.7K

Cs

RZ

Rt

n

20

82

R, E f es
'::-

Rs

IV)

NF

47 11
100
1
100
1
0
47 11
100
1
100
0
1
1 Source
~

~

~

~

'00
mA

Ro
n

(VI

5
8
8

lK
820
820
27K
15K
15K
0

15
15
3

6
8
8
5

·0

5
25
5.5
11

AV

8·11
9
19
18·24
15
33
097

Follower

2N4339-40
2N4867·69
J230·32
J202·4
J308·10
U308-10
U401·6
U421·6

.".

JFET Voltage Amplifier Stage Application Nota: TA70·2

.r.«
!J
on

2N4091·3
2N4391·3
PN4091·3
PN4391·3
J108·10
J105·7
U290·1
2N5432·4
SD210DE·215DE

s ' y o : a,

.!!..

8

.c

C
E Q2

-16V

Shunt·Resistor Analog Switch Application Note: AN73·5

Ioc

e

Ilf---=O

a

CRR Series
J501·11
J552·7

40V

.co

1Mt~.

RS

u:

RS

2W

Any J·FET

h

JR135V·240V

SjlA101mA

'---1~_--<)

29

Equivalent Circuit of a JFET Current Limiter Application Note: 0171·1

~=

V,

01:

o,~

zcc

v,

V2

V2

0,

••,

.

.A.

VCR Series
Any J-FET

VH

Distortion Free Voltage Controlled Attenuato. (VCRI Application Note: AN73·1

U430-1
U44O-1-3-4
2N5911-12
U308-10
J308-10
2N4416
U350
S08901

Singl.Salanced VHF Balanced Mixer Application Note: AN72-1

v

(*~T

2N4416
PN4416
U308·10
J308-10

'vo

UHF Transmission Line Oscillator Application Note: 0173·2
*for further details see Application Notes, Index 5

5·6

Siliconix

""'1'1

JFET Geometry Selector Guide

~

fo
:I

!

~
en

-"
CD
CD

o

USEFUL JFET INFORMATION

'"'

Q
=

cqs + Cgd

c_.

Input Capacitance

Q.

CD
COSS

=

Cds + Cgs + Cbd

Output Capacitance

CRSS

=

Cqd

Reverse Feedback Capacitance

10Z

=

lOSS

9fso

=

K

2
(...Q&L)
VGS(off)

Variation of I(zero tc) with Gate Source Cutoff Voltage

lOSS

----

Forward transconductance a. a function of lOSS and VGS(off) at zero gate-source voltage

VGS(off)

gf.

=

9f.o(l-

(K

VGS

---I

= 1.5 to 2.5; typically = 2 for N-channel junction

F ET)

Vanatlon of 9fs with gate bias

VGS(off)

gl.

=

VGS(off)

=

Variation of 9fs with dram current

91.0 VI 011 OSS
2 lOSS
---

Gate-Source cutoff voltage in term. 01 lOSS and 91.0

9lso

VOS

~

VGS(off)

(~)

11,

Drain voltage at which drain current saturates

lOSS

1

rOS

""

-

Reciprocal relationship between drain-source resistance and forward transconductance. AcVGS(off) i.e, in the triode region

curate when VOS

91s
(V GS(0ff)12

rOS

""

10

=

K

= 1.5 to 2.5

<

Variation of drain resistance in the triode region

KlOSS [VGS(off) - VGS I

lossh-~)

2
Variation of drain current with gate-source voltage. The square law transfer characteristic.

VGS(off)

5-7

-

CD

'1J

JFET Geometry Selector Guide (Cont'd)

"!.

N-Channel JFETs

.-::t
u
.CD
CD

-en

..

~

CD

E
0

CD

"..,...
l-

II.

~

-'

~

-10

OJ

"~

0/'",

-5

~

0

>

It

e

-2

.
u
u
a:

-1

:>

:>
0

-0.5

~

-0.2

"

v

~

~... ~
.. ~

~

~.~

I

i~r

1111

~
:

1.0

0.1
IpSS -

v

W)

m

-0.1
0.01

IlH

~

10

1000

100

SATU~ATION P~AIN CU~RENT

~

'OS(ool- STATIC DRAIN·SOURCE ON RESISTANCE (OHMSI

140

~

-10

~

-5.0

It

-2.0

'"

g

10K

(mA)

~

I'j-

:Zw
~~

100

gg

so

~~
Le

6.

8~

-1.0

u

a:~

120

-0.5

~~
lK

10

gil. - COMMON· SOURCE FORWARD
TRANSCONDUCTANCE (.mhos)

4.

i~
g!

3.

1 kHz

a:w

00

10 kHz

~~

0--'

ilig

19Hz
100 Hz

20

=

68nV/JHi

t:::::J

i

10

I~!

~~;~zi~ii~i~
N

z
z

5-8

~
§
~

-'w

~5
::>z
:ilS

I'j

i

c:::::J

enQVos·10V
VGS-o

I

.1·.

IIIIIII

lK

goo. - COMMON-SOURCE OUTPUT
CONPUCTANCE ",mhoa)

i
LEGEND

100

40

2.

aVGSS @ IG = -, .A
VDS - 0

I

20

Of. @VOS = 10V
VGS=O

'5
10

40pF
1SOpF

.i
w

C,...@VOS=1OV

Vos=O

m
a:1'j

n
U

~I

HqUpn~
Z

Ii
z

Z

~

JFET Geometry Selector Guide (Cont'd)

"II

=
o
:I
..-<..
Ci)
CD

P-Channel JFETs

CD

ii)

~

0
~
w

"~
0

.,J
1

::>

0.5

a:

PSCB

1=

"

>

0.1
-0.1
lOSS -

-10

-1.0

-100

0
w
0

a:

::>
rOSton) @ '0 '" -10 p.Y

~

YGS = 0
VaS!oll) @ VOS ~ - 10 V
10:: -1 p.A

SATURATION DRAIN CURRENT (rnA)

0.1

100

10

~

0;-

W

""I

PSCB
I glao @

10

0.1

~

0.1
9'80 -

"

>

PSAlPSB

Vos = -10 V
VGS '" 0
I" 1 kHz
VaS!oll) @ VOS ~ -1 OV

lf-

0;-

rOS(on) - STATIC DRAIN-SOURCE
ON RESISTANCE (OHMS)

"

>

0.5

I-

10K

lK

1

g

0

"I

.

"
G

0
I-

::>

PSAIPS B PSCB

1=

:z

~

~

a:

0.5

~

::>

:z
0;-

1

II

l::

~

::>
0
w
0

CD
CD

0

0
I-

PSAlPSB

-

5

>

>
~

::>

0
w
0

CIt

10

"~

5

0

lL

0
I-

0
~
w

10

"~

5

>

"I

~

~

0
~
w

l::

0

ii)

ii)
10

= -1

1

Ci)
C

-.
a.

p.A

100

10

CD

COMMON·SOURCE OUTPUT
CONDUCTANCE (/-Lmhos)

ii)

~

0
~
w

""~

80

10

,,~

00
to?!!
Ww

~

~
~

::>

0
w
0

0.5

i=f--

:z
~

"

PSCB

g088 @ YOS = -10 V
Vas'" 0
t = 1 kHz
VaS!oll) @ VOS ~ -1 OV
10 = 1 p.A

0

>

:;~

PSAlPSB

a:

i0;-

~~

0.1
1
gOIl -

100

10

I

60

~"

if'

I

::>

"I

Vos=O

o~

>

0

lK

,,0
0>
O:z
>-;0
1-0

40

~~

10Hz

100Hz

60

1 kHz

"'w
0"
:x: "
...zO

~I~

I

10kHz

=
=
=

en@Vos=-10V
VGS= 0

40

w>

~w
,,~

~o

10

iil"
,,:;;

-

LEGEND

1--

",I-

0

l-

80

BVGSS@IG= lilA

w _

5

"z
0 ...
w::>

20

20

~

f~C=~

iii~

0

0

PSAlPSB

PSCB

PSAlPSB

COMMON-SOURCE OUTPUT
CONDUCTANCE (p.mhos)

~

40

0
z

VGS"O

;'!

...~
"~

w
0

~

>-"
Ww
"'0
wz
0"

30

4

00
~a:
:ow
O~
o~

,0

1:1

2

,J~

0
0

I
~

-

6

"' ...
~~
z"

20

:0
:0

0

Cr1S@VOS=-10V
VGS=O

w

ffiu::

"'"0

"0z

-

8
C.u@VOs=-10V

0

n
PSCB

0

PSAlPSB

~

PSCB

Siliconix

PSAlPSB

5-9

'!'

N &FI-Channel Single FETs

o

~n

-ncn

"'II

l>
-i
Z
C

-r
' m
!'l>

"
;:
",

m

"

m
il'

o

:J

)C'

.... l>

z
0

~

"'II

On

2N4117
2N4117A
2N4118
2N4118A
2N4119
2N4119A
PN4117
PN4117A
PN4118
PN4118A
PN4119
PN4119A
PN4120
FN4117
FN4117A
FN4118
FN4118A
FN4119
FN4119A
FN4392
FN4393

N
N

72

N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N

72
72
72

2N4220A
2N4221 A
2N4222
2N4338
2N4339
2N4340
2N4341
2N4B67
2N4B67A
2N4868

N
N
N
N
N
N
N
N
N
N
N
N
N
N

72
72
72

2N4B6BA
2N4869
2N4B69A
511000·
(2N6908i
511010(2N6909)
51102012N6910)'
511100·
12N6911)
J230
J230·18
J231
J231·18
J232

72

72
92
92
92

92
92
92
92
72

72
72

72
72

72
18
18

;:r"
l> .... m

xc;)

x~~

-.m

'",

-l>
c;)
m

-< ....

'<0:1:

;:'"
l>l>

-"'II

Gate
001
0.001
001
0.001
001
0001
0.01
0001
0.01
0.001
001
0001

:....~o
Chnl

-

-

.

0005
0.001
0005
0.001
0.005
0.001
01
01

0.1
0.1

72
72
72
72
72

01
0.1
01
0.1
0.1
0.1
01
0.25
0.25
025
0.25
025
0.25
0,025

N

72

0,025

N

72

0.025

-

18
18
18
lB

72

72

N

72

0025

N
N
N
N
N

92
92
92
92
92

025
025
025
025
025

r
0

-

-

-

-

-

-

-

-
"3 ccn
OZ
~

Z

~~m
<

•

;:l>C
l>Q-I
X-I
'-l>

00:
00:
0.0"
0.0"
02
02
003
0,03
008
008
02
0.2
0.2
003
003
0.08
008
0.2
0.2
25
5.0
05
2.0
50
0.2
05
12

JO
04
04
10
10
25
25

Max.

Mm,

009
009
024

70
70

024
06
06
0.09
009
024
024
0.6
06
0.6
0.09
02
0.24
04
0.6

90
100
100
70
70
80
80
100
100
100
70
10
80
80
100
100

12

80

Max.
210
210
250
250
330
330
210
210
250
250
330
330
330
210

210
250
250
330
330

100
60

30
GO

1000
2000

15
06
15
36
90
12
12
30
30
75
75
2.0

2500
600
800
1300
2000
700
700
1000
1000
1300
1300
100

4000
5000
6000
1800
2400
3000
4000
2000
2000
3000
3000
4000
4000
3000

N

;:.

n

m

Gate
fl

-

3
3
3
3
3
3

-

-

-

-

-

-

-

3

-

-

-

-

-

60
100

6

2.5
25
25
1'0
10
10
10
20
10
20
10
20

1M
1M
1M
1M
1M
1M
1M

3

3

-

6
6
7
1

7
7
25
25
25
25
25
25
5

10

-c;)

l>
Z
n
m

o·!lo;:
, m

-

-"<

Chnl
Max

n.

-

NT

..

NT
NT
NT
NT
NT
NT
NT
NT
NT
NT
NT
NT
NT
NT
NT
NT
NT
NT
NCB
NCB

.

-

3K
3K

3K
3K
3K
3K
3K
3K

3K

3K
14
14

-

NPA
NPA
NPA
NPA
NBA·A

30

3.5

400

3500

5

25

-

30

50

1200

4000

5

25

-

-

NBA-A

2.8

30

-

25

NBA·B

40
40
40
40
40

-

30
30
30
30
30

-

-

30
30
50
5.0
60

-

1000
1000
1500
1500
2500

2500
2500
3000
3000
4000

I

rr

mo

~::-::

»
G)
m

-

NBA-A

-

-

1

NPA
NPA
NPA
NPA
NPA

a

_.
n

en

CO
J

-m-n
0

.....

...

."

0
0.

...
C

0

en

"0
(1)

NPA
NPA

2.3

30
30
60
60
10

m

NPA
NPA
NPA

3.5

0.7
07
2.0
20
5.0

i'i

NRL
NRL
NRL
NPA

-

25

0

m

<

... -1

-

-

3

&'m

-

..

iii

....

0

l>;:r
xl>-i
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Z

Min.

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....

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Z
n
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0

•~~2
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0

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m

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-'I
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m

o

J
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Chnl

J232-18
J270-18

N
P

92
92

0.25
0.2

-

2N3819
2N3823
2N4223
2N4224
2N4416
2N4416A
2N5484
2N5485
2N5486
2N5668
2N5669
2N5670
J210
J211
J212
J270
J271
J300
J304
J305
J308
J309
J310
MPF102
MPF108
MPF112
PN4416
U30B
U309
U310
U311
U312

N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
P
P
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N

92

2.0
0.5
0.25
0.5
0.1
0.1
1.0
1.0
10
2.0
2.0
2.0
0.1
01
0.1
0.2
02
0.5
0.1
0.1
1.0
1.0
1.0
2.0
1.0
100
1.0
015
0.15
0.15
015
0.1

Z
~

72
72
72
72
72
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
52
52
52

72
52

Min.

Min.

Max.

6.0
2.0

40
30

5.0
2.0

10
15

2500
6000

4000
15000

8.0
B.O
B.O
8.0
6.0
6.0
3.0
4.0
60
40
60
8.0
30
4.5
6.0
2.0
45
6.0
6.0
3.0
65
4.0
65
7.5
8.0
10
6.0
60
40
6.0
6.0
60

25
30
30
30

2.0
4.0
3.0
2.0
5.0
50
10
40
B.O
1.0
4.0
80
2.0
7.0
15
20
60
6.0
5.0
1.0
12
12
24
2.0
1.5
1.0
5.0
12
12
24
20
10

2000
3500
3000
2000
4500
4500
3000
3500
4000
1500
2000
3000
4000
7000
7000
6000
BOOO
4500
4500
3000
BODO
10000
BOOO
2000
2000
1000
4500
10000
10000
10000
10000
6000

6500
6500
7000
7500

30
35
25
25
25
25
25
25
25
25
25
30
30
25
30
30
25
25
25
25
25
25
30
25
25
25
25
25

20
20
lB
20
15
15
5.0
10
20
5.0
10
20
15
20
40
15
50
30
15
8.0
60
30
60
20
24
25
15
60
30
60
60
30

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-

-

-

-

-

-

-

-

-

-

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0
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7500
7500
6000
7000
BOOO
6500
6500
7500
12000
12000
12000
15000
1BOOO
9000
7500

20000
20000
18000
7500
7500
7500
7500
20000
20000
lBOOO
20000
10000

3:»C
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n
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-

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-

-

5.5

7.5
7.5
7.5
7.0
65

Ul

iii

Gate

-

-

-

lK
lK

-

-

2.0
2.0
3.0
2.0
20
25
2.5
25

lK
lK
lK
lK
lK
lK
lK
lK

-

-

-

-

-

-

2.5

1M

-

-

-

-

40
7.5
75
75
75
50

20

lK

-

-

-

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30

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6
6
6
4
4
5
5
5
7
7
70

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3:- 0
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-

-

-

-

-

-

-

-

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n

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NRL
NRL
NRL
NRL

-

NH
NH
NH
NH
NH
NH
NH
NH
NZF
NZF
NZF
PS·A/B
PS·A/B
NZF
NH
NH
NZB
NZB
NZB
NH
NH
NH
NH
NZB
NZB
NZB
NZB
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2N3824

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2N3970
2N3971
2N3972
2N4091
2N4092
2N4093
2N4391
2N4392,
2N4393*
2N4856
2N4856A
2N4857
2N4857A
2N4858
2N4858A
2N4859
2N4859A
2N4860
2N4860A
2N4861
2N4861A
2N5018
2N5019
2N5114
2N5115
2N5116
2N5432
2N5433
2N5434
2N5638
2N5639

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N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
P
P
P
P
P
N
N
N
N
N

72
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
lB
18
18
18
52
52
52
92
92

2
0

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0.1
025
0.25
025
0.2
0.2
02
01
0.1
0.1
0.25
0.25
025
0.25
0.25
0.25
0.25
0.25
0.25
0.25
0.25
0.25
2.0
2.0
0.5
0.5
0.5
0.2
0.2
0.2
1.0
1.0

Chnl
0.1
025
0.25
0.25
0.2
0.2
0.2
0.1
0.1
0.1
0.25
025
0.25
025
0.25
0.25
0.25
0.25
0.25
0.25
0.25
0.25
10.0
10.0
0.5
05
0.5
0.2
0.2
0.2
1.0
1.0

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0

8.0
10
5.0
30
10
7.0
5.0
10
5.0
3.0
10
10
6.0
6.0
40
4.0
10
10
6.0
6.0
4.0
4.0
10
5.0
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6.0
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2N5640
JI05
Jl05·18
JI06
JI06-18
JI07
JI07-18
Jl08
Jl08-18
JI09
Jl09-18
Jl10
JIIO·18
Jll1
J111-18
J112
J112-18
J113
J113-18
J174
J174-18
J175
J175-18
J176
J176-18
JI77
JI77-18
Pl086
P1OS6-18
Pl087
Pl087-18
PN4391
PN4391-18
PN4392
PN4392-18
PN4393
PN4393-18

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N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
P
P
P
P
P
P
P
P
P
P
P
P
N
N
N
N
N
N

92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92

1.0
3.0
3.0
30
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0'
3.0
1.0
1.0
1.0
10
10
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
2.0
2.0
20
20
1.0
1.0
1.0
10
1.0
10

1.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
10.0
10.0
100
100
1.0
10
1.0
10
1.0
1.0

6.0
10.0
10
6.0
6.0
4.5
45
10
10
6.0
6.0
4.0
4.0
10
10
5.0
5.0
3.0
3.0
10
10
6.0
6.0
4.0
4.0
2.25
2.25
10
10
50
50
10
10
50
50
30
3.0

Z
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30
25
25
25
25
25
25
25
25
25
25
25
25
35
35
35
35
35
35
30
30
30
30
30
30
30
30
30
30
30
30
40
40
40
40
40
40

ut02l

-l>
Z
0
m

Z

Max.

Min.

Max.
-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

100
100
60
60
25
25
20
20

-

150
150
,00
100
60
60

-

-

-

-

'

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-

-

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3:l>C:
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-

-

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5.0
500
500
200
200
100
100
80
80
40
40
10
10
20
20
5.0
5.0
20
2.0
20
20
7.0
7.0
2.0
2.0
1.5
1.5
10
10
50
50
50
50
25
25
50
50

zs~

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1:

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en

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-

-

-

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0
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n

n.Max.

-

-

-

100
30
3.0
60
6.0
8.0
80
80
8.0
12
12
18
18
30
30
50
50
100
100
85
85
125
125

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

45
45
45
45
14
14
14
14
14
14

...

Chnl

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-CI
!em
lto
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" m
~
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250
250
300
300
75
75
150
150
30
30
60
60
100
100

<

NCB
NVA
NVA
NVA
NVA
NVA
NVA
NIP
NIP
NIP
NIP
NIP
NIP
NCB
NCB
NCB
NCB
NCB
NCB
PS-A/B
PS-A/B
PS-A/B
PS-A/B
PS-A/B
PS-A/B
PS-A/B
PS-A/B
PS-A/B
PS-A/B
PS-A/B
PS-A/B
NCB
NCB
NCB
NCB
NCB
NCB

3

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50210
50211
50212
50213
50214
50215
U200
U201
U202
U290
U291
U304
U305
U306
U1897
U1897-18
U1898
U1898·18
U1899
U1899·18

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N
N
N
N
N
N
N
N

N
N
N

p
P
p
N
N
N
N
N
N

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00

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72
72

72
72
72
72

18
18
18
52
52
18
18
18
92
92
92
92
92
92

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Gate

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100
100
100
100
100
100
1.0
10
1.0
1.0
10
05
05
05
04

100
100
100
100
100
100
1.0
1.0
1.0
1.0
1.0
0.5
05
05
02
02
02
02
02
02

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04
04
04
04

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30

30
10
10
20
20

30
30
30
30
30
30
30
30
40
40
40
40
40
40

z

10
10
10
10

10
10
3.0
15
30
500
200
30
15
50
30
30
15
15
8.0
80

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0
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0

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2.0
2.0
2.0
20
20
2.0
30
50
10
10
4.5
10
6.0
40
10
10
70
70
50
50

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cm

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Max.

Min.

Max~

-

-

-

-

-

..

-

-

25
75
150
-

-

-

..

..

..
-

-

-

-

90
60
25

-

-

-

-

-

.-

-

..

-

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..
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-

-

-

0

m

5.5
5.5
5.5
5.5
5.5
5.5
30
30
30
60
60
27
27
27
16
16
16
16
16
16

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n, Max.

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-

70
70
70
70
70
70
150
75
50
25
7.0
85
110
175
30
30
50
50
80
80

OMCB·B
OMCB·A
OMCB·B
OMCB·A
OMCB·B
OMCB·A
NCB
NCB
NCB
NVA
NVA
PS·A/S
PS-AiB
PS·A/B
NCB
NCB
NCB
NCB
NCB
NCB

n
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2N3821
2N3822
2N4220
2N4221
2N4222
2N5457
2N5458
2N5459
J201
J201·18
J202
J202·18
J203
J203·18
J204
J204·18
J270
J271·18
MPF109
MPFlll
PN4302
PN4302·18
PN4303
PN4303-18
PN4304
PN4304·18
PN5163

z
0

...
~

N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
P
P
N
N
N
N
N
N
N
N
N

~~
;;:;0:

-00
...
-il>

l>l>
XCI
.m

-

';0:

-l>
CI
m
72
72
72
72
72
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92

Gate

Chnl

0.1
0.1
0.1
0.1
0.1
1.0
10
1.0
01
0.1
01
01
01
0.1
0.1
0.1
02
02

-

1.0
100
10
1.0
10
1.0
1.0
1.0
10

-

-

-

-

-

-

-

-

-

-

-O::-i
,:c:0J:
;;:r-:Il
l>-im
xl>~
:...~o
r-

:;;

8.0
10
4.0
4.0
6.0
60
10.0
10
8.0

Z

I

50
50
30
30
30
25
25
25
40
40
40
40
40
40
25
25
30
30
25
20
30
30
30
30
30
30
25

0.5
20
0.5
2.0
5.0
1.0
20
40
02
02
09
0.9
40
4.0
1.2
1.2
6.0
60
05
0.5
0.5
05
4.0
40
05
05
10

~~~

~~

aZ

Min.

zS'iS

-0-

6(')1

m:ll
zl>
-i-i

.0000:ll
;;:r-m
l>-il>
xl>;O:
. ClC
-mo

C

40
6.0
40
6.0
8.0
6.0
70
8.0
15
15
40
4.0
10
10
20
2.0
45
45

~~~

-o::m

en

'";;rO:ll
O-i
-Zl>
"oz
3c: m

-om
3C:l>

- r-

!

z
0
m
Max.

Mm.

Max .

25
10
3.0
60
15
50
90
16
1.0
100
4.5
45
20
20
3.0
3.0
50
50
24
20
5.0
50
10
10
15
15
40.0

1500
3000
1000
2000
2500
1000
1500
2000
500
500
1000
1000
1500
1500

4500
6500
4000
5000
6000
5000 •
5500
6000

-

-

-

-

-

-

-

8000
8000

18000
18000

800
500
1000
1000
2000
2000
1000
1000
2000

6000

-

9000

;;:l>C:
l>£1-i
X-i
:...l>
Z
0
m
6
6
6
6
6
7
7
7
50
50
50
5.0
50
50
50
50

-

NO::
•~~m
;;:. 0
l>;;:rxl>-i

:...~I!i

om

Gate
n

~

200
200

3.0
3.0
3.0

I

1M
1M
100M

-

-

-

-

-

-

3

:Il
m
m
iii
-i
l>
z
0
m

...,,~Cii

W~
g. ~

Chnl
n.Max.

-

-

-

-

-

-

-

-

-

-

-

25

1M

-

-

-

6
60
6
60
6
6.0
20

2.0
2.0
20
2.0
30
20
50.0

1M
1M
1M
1M
1M
1M

-

-

-

70

::I m
... -i
-:Il

-

-<

I

NRL
NRL
NRL
NRL
NRL
NRL
NRL
NRL
NPA
NPA
NPA
NPA
NPA
NPA
NPA
NPA
PS·A/B
PS·A/B
NRL
NRL
NPA
NPA
NPA
NPA
NPA
NPA

-

0
m

0::

n
m

-a

-en_.•

c.o

:l

-a-n
m

.....

G)

en
"0

m
Z
m

CD
0

»
r

~

:0
"tI

C
:0
"tI

0
en
m

_._.

...
-0
.....
0

a_.

0

::::J

fn

0

:l

Co

~

(]I

----

I

C[I

......

N-Channel Dual FEls

Ol
"0

~

"

l>
:II
-I
2

C

;:
III
m
:II

2N5196
2N5197
2N5198
2N5199
2N5545
2N5546
2N5547

m
0'
o

J
)C'

2N6905
2N6906
2N6907
U401
U402
U403
U404
U405
U406
U421
U422
U423
U424
U425
U426

U427

;>;
l>
CI

'"

Z

::j

51

-

"
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N

U42B

N

2N5515
2N5516
2N5517
2N5518
2N5519
2N5520
2N5521
2N5522
2N5523
2N5524
2N6905
2N6906
2N6907
U401
U402

N
N
N
N
N
N
N
N
N
N

N
N
N
N
N

9
71
71
71
71
71
71
71

71
71
71
71
71
71
71
71
71
78
78
78
78
78
78
78
78
71
71
71
71
71
71
71
71
71
71

71
71
71
71
71

- ....
!>l>
"",

;:;>;
l>l>
XCI
.m

-=-Gate

0025
0025
0.025
0.025
01
01
01
0.Q15
0.Q15
0.015
0025
0025
0025
0025
0025
0.025
0001
0001
0001
0003
0003
0003
0.005
0.005
025
0.25
0.25
0.25
025
025
0.25
0.25
0.25
025
0.Q15
O.ot5
0.Q15
0.025
0.025

~g~

-om
3Cl>

'"

l>:II-I
-:II C
",:II
2l>

:...~S

xl>;>;
. CI 0
-"'0

2

0

2

-<-I
:'0:1:
;:.-:11
l>"''''
Xl> In

....

40
40
4.0
4.0
4.5
4.5
45
2.5
2.5
2.5
25
2.5
2.5
2.5
2.5
2.5
2_0
2.0
2_0
30
30
30
20
30
40
40
40
40
4.0
40
40
40
40
4.0
2.5
2.5
2.5
25
25

- ... l>

:E

Mm,

50
50
50
50
50
50
50
35
35
35
50
50
50
50
50
50
40
40
40
40
40
40
40
40

07
07
0.7
0.7
05
05
05
0.5
0.5
0.5
05
05
05
05
05
05
006
006
006
006
006
006
006
006

40
40
40
40
40
40
40
40
40
40
35
35
35
50
50

05
05
05
05
05
05
05
05
0.5
0.5
0.5
0.5
0.5
05
05

-0"... ."
l> 2...

g-o'

......0

:,;~~
l>_

~i!
2
0
m

Max.
70
70
70
7.0
8_0
8_0
80
10
10.
10
10
10
10
10
10
10
10
10
10
18
1S
18
18

L8
75
75
75
75
75
75
75
75
7.5
75
10
10
10
10
10

Mm.

1000
1000
1000
1000
1500
1500
1500
2000
2000
2000
2000
7000
2000
2000
2000
2000

300
300
300
300
300
300
250
250
1000
1000
1000
1000
1000
1000
1000

...

--2
2" 0

-2l>
"3 ccn
02

MdX.

-

-

-

-

-

1500
1500
1500
1500
1500
1500

-

-

-

-

1000

-

1000
1000
2000
2000
2000
2000
200&

-

-

-

-

X'"
:...l>
2
0
m

60
60
60
60
6.0
60
60
8.0
8.0
8.0

SO
80
:")0
of)

ao
::-;0
30
30
30
30
30
30
3.0
30

25
25
25
75
75
25
25
25
25
25
8.0
8.0
8.0
8_0
8.0

:n~Cii

Cl."

m
In

!! '"
20
20
20
20
200
200
200
15
15
15
20
20
70
20
20
20
10

10
10
10

10
10

-

30
30
30
30
30
15
15
15
15
15
15
15
15
20
20

Static Match
[mV, Max.l
50
50
10
15
50
10
15
5
15
25
50
10
10
15
70
40
10
15
7b

III
15
25
25
40
50
50
10
15
15
50
50
10
15
15
5
10
25

5.0
10

I'm
g.~
",. ...m
-:II

lit ...

0
....
0

:...~~

-CI

:To'"

:r

;:' 0
l>;: ....
xl>'"

3

20c

-2-1
"3cc
0 ...

:II

!"~l~

en

.. 00

:I:

Temp Tracking
~Vf C
50
10
20
40
10
20
40
10
25
50
10
10
25
25
40
80
10
25
40
10
25
40
40
80
50
10
20
40
80
50
10
20
40
80
10
25
50

10
10

' l>
;:2
l>0
X'"
:...
50
50
50
50
25
25
25

-

20
2.0
20
20
20
20
05
05
05
10
10
10
30
50
10
10
10
10
10
10
10
10
10
10

m

Nap
Nap
Nap
Nap
Nap
Nap
Nap
NNR

20
20

NNA
NNR

-en
I

-.

(Q

::J

-m
C

r

NN'"
NNR
NNR
NNR
NNA
NNR
NNR
NNR
NNT
NNT
NNT
NNT
NNT
NNT
NNT
NNT

-

-

(;

-<

Nap
NOP
NOP
NOP
Nap
NOP
Nap
NOP
Nap
Nap
NNR
NNR
NNA

-

0

'"<

C

0

:E

r

m
l>

"l>

C)

m

-n

-I

en

"tJ
(I)

0-.
....
-.
0
C

....
-.
0
::J

(I)

r

0

~
Z

0

en

m

",.......

0
0

......

:J

a.

~

-----

--------

N-Channel Dual FETs
."
~

."
~

n

...'"

z
c:
li:
III
m

:II

m
0'

oj

X'

~

2

!!

-r

'"
~

}a~

m

li:'"

~~

Cl

...
-",c:

-< ... -
:ii:
"0
r
"T1

m
:II

:::J

--n

m
.....

en
-0
CD

_.
....
-.
0

G)

m
m

Z

:II

l>
r

"0

c

:II
"0

0

en
m

0
Q

....
-.

0

:::J

en
---.

0

0

:::J
....
..
a.

SWITCH

-

Product Specifications (Cont'd)
Low Leakage Diodes
Part
Number

Package
(TO· I

DPADI
DPAD2
DPAD5
DPAD10
DPAD20
DPAD50
DPAD100

78
71
71
71
71
71
71

Dual
Dual
Dual
Dual
Dual
Dual
Dual

JPAD5
JPAD10
JPAD20

92
92
!32

JPAD50
JPAD100
JPAD200
JPAD500
PADI
PAD2
PAD5
PAOlO
PAD20
PAD50
PAD100

Breakdown

Reverse
Current
(pA, Max.)

Diode

Forward
Voltage Drop
Volts (Max.)

Voltage
(Volts)

Mm.

Max.

1
2
5
10
20
50
100

45
45
45
35
35
35
35

120
120
120

Smgle
Smgle
Smgle

5
10
20

35
35
35

-

92
92
92
92

Single
Smgle
Single
Single

20
50
100
500

35
35
35
35

-

18
18
18
18
18
18
18

Smgle
SlOg Ie

1
2
5
10
20
50
100

45
45
45
35
35
35
35

120
120
120

SIOgle

Smgle
Single
Smgle
Song Ie

-

-

-

-

-

Capacitance
(pF, Max.)

1.5
1.5
1.5
15
1.5
1.5
1.5

08
0.8
0.8
2.0
2.0
2.0
2.0

1.5
1.5
1.5

2.0
2.0
20

15
15
15
1.5

20
2.0
20
2.0

1.5
15
1.5
15
15
1.5
1.5

0.8
08
0.8
2.0
20
2.0
2.0

Voltage Controlled Resistors
Part
Number

N orP

VCR2N
VCR3P

N
P
N
P
N

\ J ...... nAfli

VCR5P
VCR7N

Resistance
(Channel n)

Threshold Voltage
(Volts)

Breakdown

Package
(TO,
)

Voltage
(Volts, Min.)

Min.

Max.

18
72
HI
72
72

15
15

3.5
3.5

15

~o
~.~

15
15

3.5
2.5

Geometry

Min.

Max.

70
7.0

20
70

60
200

,n

~nn

600

70
50

300
4000

900
8000

NCB
PS'A/B

NP/\
PS·A/B
NT

P-Channel MOSFETs
Part

Number
3N163
3N164
MFE823

9- 18

Package
(TO· )

72
72
18

Operating
Modo

ENH
ENH
ENH

Threshold
Voltage
(Volts, Max.)

Resistance

5.0
5.0
6.0

250
300

Channel
(n.Max.1

-

Leakage
Channel On
(mA)

Min.

Max.

5.0
3.0
30

30
30

Leakage
Breakdown
ChannolOff
Voltage
(nA,Max.1 (Volts, Max.1

-

Siliconix

-

-

20

40
30
25

Input

Capacitance
(pF, Max.)

2.5
2.5
6.0

Reverse
Capacitance

Geometry

(pF, Max.)
0.7
0.7
1.5

MRA
MRA
MRA

Product Specifications (Cont'd)
Current Regulator Diodes
Part
Number
CR022
CR024
CR027
CR030
CR033
CR039
CR043
CR047
CR056
CR062
CR068
CR075
CR082
CR091
CR100
CR110
CR120
CR130
CR140
CR150
CR160
CR180
CR200
CR220
CR240
CR2'70
CR300
CR330
CR360
CR390
CR430
CR470
CR530
CRR0240
CRR0360
CRR0560
CRR0800
CRR1250
CRR1950
CRR2900
CRR4300
J500
J501
J502
J503
J504
J505
J506
J507
J508
J509
J510
J511
J552
J553
J554
J555
J556
J557
J9100
JRl35V
JR170V
JR200V
JR220V
JR240V

Package
ITO· )
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92
92

92

Forward
Current

ImA)
022
024
027
030
033
039
043
047
056
062
068
075
082
091
100
1 10
120
130
140
150
160
180
200
220
240
270
300
330
360
3.90
430
470
5.30
.24
.36
.56
80
195
195
290
430
024
0.33
043
0.56
075
1.00
140
1.80
240
3.00
360
4.70
0.05
( 18,075)
106 ,1.6)
(1.4 ·2.6)
124·38)
(36·5.3)
0.05
0.200
0.200
0.200
0.200
0.200

Forward
Current
Tolerance

1%)
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
25
25
25
25
25
25
25
25
20
20
20
20
20
20
20
20
20
20
20
20
50

..

..
..
..
..

50

..
..
..

-

Limiting

Voltage
IVolts, Max.)

Peak Operating
Voltage
IVolts, Max.)

Dynamic

Forward

Impedance

Capacitance

IMn,Max.)

IpF, typ)

100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100

13
10
90
80
6.6
41
3.3
27
19
1 55
1 35
1 15
100
088
080
070
064
058
054
051
0475
042
0395
037
0.345
032
030
0.28
0265
0255
0245
0235
0.20
.9
41
1.15
08
.54
.37
28
05

..
..
..
..

50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
135
170
200
220
240

5.0
30
20
14
1.0
06
04
025
025
020
020
0.15
20
10
10
88
.6
,48
20
2.0
2.0
2.0
2.0
2.0

100
100
100
100
100
105
105
1 10
120
1.30
1 15
120
125
129
1 35
140
145
1.50
1 55
160
165
1 75
185
195
200
2 1~
225
235
250
260
275
290
3.10
1.0
105
130
135
160
195
235
300
120
130
150
1 70
190
210
250
2.80
310
350
390
420
15
75
75
.75
.75
15
1.5
09
0.9
0.9
0.9
0.9

Siliconix

Geometry

..

NKL
NKL
NKL
NKL
NKL
NKL
NKL
NKL
NKL
NKL
NKM
NKM
NKM
NKM
NKM
NKM
NKM
NKM
NKM
NKM
NKO
NKO
NKO
NKO
NKO
NKO
NKO
I'4KO
NKO
NKO
NKO
NKO
NKO
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NKL
NKL
NKL
NKM
NKM
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NKO

2
2
2
2
2
2
2
2
2
2
2
2
2

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NCL
NCL
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NCL
NCL
NCL
NCL
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5-19

Package Data __

Siliconix

Package Data

H

At Siliconix' option, lead finish will be either Gold

Siliconix

Plate or Tin Plate. Electrical Characteristics are not affected.

."
Q
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45'
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TO-18
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0150

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(292)

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(445)
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ALL DIMENSIONS IN INCHES.
IALL DIMENSIONS IN MILLIMETERS)

45'

TO-18
(3 PIN)

0i15
0195
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----

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0

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TO-71

Siliconix

6-1

-

Package Data (Cont'd)

!!.lliJO
0170
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0178
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112101
0500
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1

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1

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At Siliconix' option, lead finish will be either Gold

Plate or Tin Plate. Electrical Charac;teristics are not affected.

-0040
11021
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!ill!!.

0209
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(531)

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TO-92 Device to TO-5 Pin Circle

to standard part type

Order number (-05) suffix to standard part type

Siliconix

45'

Package Data (Cont'd)

."
Q

At Siliconix' option, lead finish will be either Gold

n

Plate or Tin Plate. Electrical CharacterIStics are not affected.

~

a

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TO-92 TAPING SPECIFICATIONS AND WINDING STYLES

..
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19.5±0.5

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0±0.5

All dimensions in millimeters.

OPTlONJ

OPTION 1

STYLEAISPREFERRED

STYLE E IS A PAEFERRED STYLE

ROUNOOUT
DAAIN OFF FIRST

ROUNDED SIDE OF mANSISTOR AND ADHESIVE TAPE VISIBLE

STANDARD TAPE & REEL FLAT OUT GATE OFF FIRST

OPTION 2

RQUNDEDSIDE

ROUND OUT
GATE OFF FIRST
FLAT SIDE OF TRANSISTOR AND ADHESIVE TAPE VISIBLE

ROUNDED SIDE OF TRANSISTOA AND ADHESIVE TAPE VISIBLE

Note: Order information-TRX = option (Standard Si option = Option 1) If not
deSignated option 1 will be chosen. Tape and ammopack available-contact
factory.

Siliconix

6-3

Package Data (Cont'd)

At Siliconix' option, lead finish will be either Gold

Plate or Tin Plate. Electrical Characteristics are not affected.

1--- +008
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6-4

Siliconix

Package Data (Cont'd)

"

Q
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Plate or Tin Plate. Electrical Characteristics are not affected.

~

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6-5

Package Data (Cont'd)

At Siliconix' option, lead finish will be either Gold

Plate or Tin Plate. Electrical CharacterIStics are not affected.

~
14

13

033.

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(874)

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L

Application Notes _

Siliconix

An Introduction to FETs

INTRODUCTION
The basic pnnciple of the field-effect transistor (FET) has
been known since J .E. Lilenfeld's patent of 1925. The theoretical description of a FET made by Schockley in 1952
paved the way for development of a classic electronic device
which provides the designer with the means by winch he can
accomplish nearly every circuit functIOn. The field-effect
transIstor earlier was known as a "unipolar" transistor, and
the term refers to the fact that current IS transported by
carriers of one polarity (majority). whereas in the conventional bipolar transistor earners of both polarities (majority
and minority) are involved.
This Application Note provides an insight into the nature of
the FET, and touches briefly on its basic characteristics,
terminology and parameters, and typical applications.
The followmg list of FET applications indicates the versatility of the FET family:
Amplifiers
Small Signal
Low Distortion
High Gain
Low Noise
Selective
D.C.
High-Frequency

Switches
Chopper-type
Analog Gate
Commutator

Current Limiters
Voltage-Controlled
Resistors
Mixers
Oscillators

In fact, FET teclmology today allows a greater packaging
density in large-scale integrated CIrcuits (LSI) than would
ever be possible with bipolar deVIces.
(Although there is no industry-accepted definitIOn of LSI,
apparently when the equivalent circUIt of an IC contains
more than 1,000 active elements (500 gates) or is "very complex", the end product may be called LSI. With a typical
LSI chip measurmg less than 200 x 200 mIls; tius is highdensity packaging indeed.)
The f3!mly tree of FET devices (FIgure I) may be divided
into two main branches, junction FETs (JFETs) and Insulated Gate FETs (or MOSFETs, metal-oxide-silicon field-effect
transistors). Junction FETs are inherently depletion-mode
devices, and are available in both P- and N-Channel configurations. MOSFETs are available in both enhancement or
depletion modes, and exist as both N- and P-Channel devices.
The two main FET groups depend on dIfferent phenomena
for their operation, and will be discussed separately.

I

I

I

I

This very wide range of FET applications by no means implies
that the device will replace the more widely-known bipolar
transistor in every case. The simple fact is that FET characteristics - which are very different from those of bipolar
devices - can often make possible the design of technically
supenor (and sometimes cheaper) circuits. This comment
applies not only to networks employing discrete devices and
conventIOnal components such as resistors and capacitors,
but also extends to both linear and digItal integrated circuits.

I

JUNCTION

I
DEPLETION

I
I P.CHA,NNEL I

Siliconix

I

FIELD EFFECT
TRANSISTORS

I

I

I

INSULATED
GATE

I

I

ENHANCE·
MENT

I
I
I N.CH~NNEL I

I

IP

I

-

I

CH~NNEL I

I

I
I

I N.CHANNELI

FET Family Tree
Figure 1

7-1

Junction FETs
In its most elementary version, this transistor consists of a
piece of high-resistivity semiconductor material (usually silicon) which constitutes a channel for the majority carrier
flow. The magnitude of this current is controlled by a voltage applied to a gate, which is a reverse-biased PN junction
formed along the channel. Implicit in this description is the
fundamental difference between FET and bipolar devices:
when the FET junction is reverse-biased the gate current is
practically zero, whereas the base current of the bipolar transistor is always some value greater than zero. The FET is a
high input resistance device, while the input resistance of the
bipolar transistor is comparatively low. If the channel is
doped with a donor impurity, N-type material is formed and
the channel curr&nt will consist of electrons. If the channel
is doped with an acceptor impurity, P-type material will be
formed and the channel current will consist of holes. N-Channel devices have greater conductivity than P-Channel types,
since electrons have higher mobility than do holes; thus NChannel FETs tend to be more efficient conductors than
their P-Channel counterparts.

Junction FETs are particularly suited to manufacture by
modern planar epitaxial processes. Figure 2 shows this process in an idealized manner. First, N-type silicon is deposited

~

(A) P-type silicon substrate

~(B)

N-type silicon laver deposited epitaxiallv

~(C)

start isolation region

Impurity diffused in to

(0) More impurity diffused
in to complete isolation

and form N-tvpe channel

(E) Final form taken bV FET:
with N-type channel embedded in P-type substrate

Idealized Manufacture of an N-Channel Junction FET
Figure 2

7-2

epitaxially (single-crystal condensation surface) onto monocrystalline P-type silicon, so that crystal integrity is maintained. Then a layer of silicon dioxide is grown on the surface of the N-type layer, and the surface is etched so that an
acceptor-type impurity can be diffused through into the
silicon. The resulting cross-section is shown in Figure 2C, ~d
demonstrates how a P-type annulus has been formed in the
layer on N-type silicon. Figure 20 shows how a further
sequence of oxide growth, etching, and diffusion can produce
a channel of N-type material within the substrate.

In addition to the channel material, a FET contains two
ohmic (non-rectifying) contacts, the source and the drain.
These are shown in Figure 2E. Since a symmetrical geometry is shown in the idealized FET chip, it is immaterial
which contact is called the source and which is called the
drain; the FET will conduct current equally well in either
direction and the source and drain leads are usually interchangeable.

(For certain FliT applications, such as amplifiers, an asymmetrical geometry is preferred for lower capacitance and
improved frequency response. In these cases, the source and
drain leads should not be interchanged.)

Figure 2E also shows how the N-Channel is embedded in the
P-type silicon substrate, so that the gate above the channel
becomes part of this substrate. Figure 3 shows how the FET
functions. If the gate is connected to the source, then the
applied voltage (V OS) will appear between the gate and the
drain. Since the PN junction is reverse-biased, little current
will flow in the gate connection. The potential gradient
established will form a depletion layer, where almost all the
electrons present in the N-type channel will be swept away.
The most depleted portion is in the high field between the
gate and the drain, and the least-depleted area is between
the gate and the source. Because the flow of current along
the channelfrom the (positive) drain to the (negative) source
is really a flow of free electrons from source to drai~ in the
N-type silicon, the magnitude of this current will fall as more
silicon becomes depleted of free electrons. There is a limit
to the drain current (IO) which increased VOS can drive
through the channel. This limiting current is known as lOSS
(Drain-to-Source current with the gate Shorted to the
source). Figure 3B shows the almost complete depletion of .
the channel under these conditions.

Figure 3C shows the output characteristics of an N-Channel
JFET with the gate short-circuited to the source. The initial
rise in In is related to the buildup of the depleti0!llayer as
VOS increases. The curve approaches the level of the limiting
current lOSS when In begins to be pinched off, The physical
meaning of this term leads to one definition of pinch-off
voltage, Vp, which is the value of VOS at which the maximum loSS flows.

Siliconix

The mechanisms of Figure 3 and 4 react together to provide
a family of output characteristics as shown in Figure SA.
The area below the pinchoff voltage locus is known as the
triode or "below pinchoff' region; the area above pinchoff
is often referred to as the pentode or saturation region. FET
behavior in these regions is comparable to that of a power
grid vacuum tube, and for this reason FETs operating in the
saturation region may be used as excellent amplifiers. Note
that in the "below pinchoff' region both VGS and VOS
control the channel current, while in the saturation region
VOS has little effect and VGS essentially controls 10 ,

DEPLETION
LAYER

(A) N-channel FET working below saturation (VGS = 0).
(Depletion shown only In channel region).

Figure SB relates the curves of Figure SA to the actual circuit arrangement, and shows the number of meters which
may be connected to display the conditions relevant to any
combination of VOS and V GS' Note that the direction of
the arrow at the gate gives the direction of current flow for
the forward·bias condition of the j unction. In practice, however, it is always reverse-biased.

DEPLETION
LAYER

(B) N·channel FET working in saturation region (VGS = 0)
/-IVDSI
lOSS

I
I

/ C>

SATURATION REGION/

=

IVpl - IVGsl

ABOVE PINCH-OFF

~I---- VGS

=

0

I

!

VDS--

'"

(e) Idealized output characteristic for VGS = O.

Figure 3
VDS-_

In Figure 4, consider the case where VOS = 0, and where a
negative voltage VGS is applied to the gate. Again, a deple·
tion layer has built up. If a small value of VOS were now
applied, this depletion layer would limit the resultant chan·
nel current to a value lower than would be the case for
V GS = O. In fact, at a value of IVGSI ;;, IV pi the channel
current would be almost entirely cut off. This cutoff voltage
is referred to as the gate cutoff voltage, and may be expressed
by the symbol Vp or by V GS(off)' Vp has been widely used
in the past, but V GS(off) is now more commonly accepted
since it eliminates the ambiguity between gate cut·off and
drain pinch-off. V GS(off) and Vp, strictly speaking, are
equal in magnitude but opposite in polarity.

(A) Family of output characteristics for N-channel FET
ID

(Bl Circuit arrangement for N-channel FET

Figure 5

N-channel FET Showing Depletion Due To
Gate-Source Voltage (VDS = 0)
Figure 4

The P·Channel FET works in precisely the same way as does
the N-Channel FET. In manufacture, the planar process is
essentially reversed, with the acceptor impurity diffused
first onto N-type silicon, and the donor impurity diffused
later to form a second N-type region and leave a P-type chan-

Siliconix

7-3

-

ne!. In the P-Channel FET, the channel current is due to hole
movement, rather than to electron mobility. Consequently,
all the applied polarities are reversed, along with their directions and the direction of current flow. Figure 6A shows the
circuit arrangement for a P-Channel FET, and Figure 6B
shows the output characteristics of the device. Note that the
curves are shown in another quadrant than those of the NChannel FET, in order to stress the current directions and
polarities involved.

o

Fir!-~~~~~~~~~

INSULATING
LAYER

SUBSTRATE

(A) Idealized cross-section through an N-channel depletiontype MOSFET

In summary, a junction FET consists essentially of a channel of semiconductor material along which a current may
flow whose magnitude is a function of two voltages, VDS
and VGS. When V DS is greater than Vp, the channel current
is controlled largely by V GS alone, because V GS is applied
to a reverse-biased junction. The resulting gate current is
extremely small.

(B) CirCUit arrangement for N-channel depletion MOSFET
mA

'4V

'2V

VGS= 0

-2V

(A) Corcuit arrangement for P-channel FET

-4V
12

VGS-

16

VOL T5

Vos--

Vos-_

Vp

vGS(Off}=====:f::="'?~:I

tel

I

Family of output characteristics for the
2N3631 N-channel depletion MOSFET

Figure 7

i5

in a manner similar to the N-Channel junction FET when a
voltage of the correct polarity is applied to the cha...~nel, as
in Figure 7B.

~iL_.J,oss
r---I

VGS=O-

ABOVE PINCH-OFF

¢ IQ

BELOW PINCH-OFF

1-IVosl • IVpl - IVGsl
(B) Familv of output characterIStics for P-channel FET
Figure 6

MOSFETs
The metal-oxide-silicon FET (MOSFET) depends for its
operation on the fact that it is not actually necessary to form
a semiconductor junction on the channel of a FET in order
to achieve gate control of the channel current. Instead, a
metallic gate may be simply isolated from the channel by a
thin layer of silicon dioxide, as shown in Figure 7 A. Although
the bottom of the insulating layer is in contact with the Ptype silicon substrate, the physical processes which occur at
this interface dictate that free electrons will accumulate at
the interface, spontaneously forming an N-type channel.
Thus a conducting path exists between the diffused N-type
source and drain regions. Further, the MOSFET will behave

7-4

Output characteristics of an N-Channel MOSFET are shown
in Figure 7C. Because there is no junction involved, V GS
can be reversed without engendering a gate current; the gate
may be made either positive or negative with respect to the
source. Under these circumstances, still more free electrons
will be attracted to the channel region, and I D will become
greater than I DSS. This mode of operation is represented by
the higher members of the family of ourput characteristics.
Because the application of a negative gate voltage causes the
channel to be depleted of free electrons - thus reducing ID the device just described is called adep/etion-mode MOSFET.
The foregoing has established that the depletion-mode
MOSFET is a "normally-ON" device: when VGS = 0, a conducting path exists between source and drain. In many circuits a "normally-OFF" device would be useful, a condition
which leads to the concept of an enhancement-mode MOSFET. In the latter device, an increasing voltage applied to the
gate will enhance channel wnduction, and depletion will
never occur, ID being zero when VGS =o.

Siliconix

A P-Channel enhancement-mode MOSFET is shown in Figure 8_ Here, an acceptor impurity has been diffused into an
N-type substrate to form P-type source and drain regions_
No conducting channel exists between the source and the
drain, because no matter how the drain-source voltage is
applied one of the PN junctions will always be reverse-biased.
On the other hand, if a negative voltage is applied to the
gate, a field will be set up in such a direction as to attract
holes into the upper layer of the substrate and produce a
P-type channeL A family of output characteristics for a
typical MOSFET is shown in Figure 8C. The idealized
cross-section illustrated in Figure 8A may be used to show
how the characteristics of Figure 8C come about. Refer
to Figure 9 for an extension of this phenomenon.

If a constant (negative) gate voltage, (V GS(K») is applied,
then an essen tially-uniform P-Channel depletion layer will
be induced, as in Figure 9A. If a negative drain voltage is

applied, then current, In, will flow through the drain. As
IVnsl increases, In also increases. However, the voltage
between the drain and the gate decreases, so that the thickness of the channel at the drain end is reduced as in Figure
9B. Therefore, the relationship of In versus VnS will eventually reach a limiting value when Vns = VGS, and the
channel becomes pinched off. This condition is shown in
Figure 9C.
Different values.of VGS give rise to limiting values of In; so
that the characteristic family of output curves which was
shown in Figure 8 is realized. Characteristics of depletionmode MOSFETs also come about for the same reason,
except that members of the output characteristics family
also exist for VGS values of zero or reversed polarity. The
P-Channel enhancement-mode MOSFET is currently the
most popular member of the FET family in current use, and
is in fact the basic element in many LSI integrated circuits.

LAYER 11 NG
F=rLr::!!!!!!!!~~!i!!!!;,,1~ INSULA

(A)

SUBSTRATE (OR BODYI

B

CA) Idealized cross-section through a P-channel enhancement

MOSFET
'0

(8)

(8) Circuit arrangement for P-channel enhancement MOSFET

Vos--

VGS=-l

v=========:,.

-2V _ _ _ _ _ _ _

-4V--------6V------

-

(C)

~

i5

-9V----(e) Family of output characteristics for a P-channel enhancement MOSFET
Figure 8

Idealized approach of pinch-off,
(A) VOS = 0, (8) lVoSI < IVGsl, (e) lVosl> IVGSI
Figure 9

Silicanix

7-5

FET Characteristics

Major parameters include:

The FET enjoys certain inherent advantages over bipolar
transistors because of the unique construction and method
of operation of the field-effect device. These characteristics
include:

• No thermal runaway
and

negligible

intermodulation

• BV GSS - Gate-to-source breakdown voltage with the
drain shorted to the source
• gfs - Common-source forward transconductance

• High input impedance at low frequencies

• Cgs - Gate-source capacitance

• Very high dynamic range (> 100 dB)

• Cgd - Gate-drain capacitance

• Zero temperature coefficient Q point
• Junction capacitance independent of device current
The transfer function of a FET approximates to a squarelaw response, and the second and higher-order derivatives of
gm are near zero; thus strong second and negligible higherorder harmonics are produced. Intermodulation products
are extremely low.
The input impedance of a FET is simply the impedance of a
reverse-biased PN junction, which is on the order of 10 10 to
10 12 .Q. In practice, the input impedance is limited by the
value of the shunt gate resistor used in a self-bias commonsource circuit configuration. At RF frequencies, the input
impedance drop is proportional to the square of the frequency; for example, in a 2N4416 FET, the input impedance
would be 22K.Q at 100 MHz. Also, the input susceptance
increases linearly with frequency, since it is a simple parasitic capacitance.
The FET has very high dynamic range, in excess of 100 dB.
Thus it can amplify very small signals because it produces
very little noise, or it can amplify very large signals because
it has negligible intermodulation distortion products. It also
has a zero temperature coefficient bias point (zero TC point)
at which changes in temperature do not change the quiescent
operating point.
Junction FET capacitances are more constant over wide current variation than are the same parameters in a bipolar
device. This inherent stability allows high-frequency (VHF
through L-band) oscillators to be built which are far more
stable than oscillators using low-frequency crystals and
multiplier stages.
FET Terminology and Parameters
Any introduction to the nature, behavior, and applications
of field-effect transistors requires that certain questions be
answered on FET electrical quantities and parameters - in
particular, the most important parameters, and the means
by which they can be measured. The following discussion
will defme specific FET parameters and their associated
subscript notations, and present basic test circuits and
results.

7-6

• VGS(off) - Gate-source cutoff voltage
• IGSS - Gate-to-source current with the drain shorted
to the source

• Lownoise

• Low distortion
products

• I DSS - Drain current with the gate shorted to the
source

Special attention should be given to the subscript "s" because it has two different meanings and three possible uses.
In FET notations, an "s" for the first or second subscript
identifies the source terminal as a node point for voltage
reference or current flow. However, when using triple subscript notation, an "s" for the third subscript does not refer
to the FET source terminal. It is an abbreviation for "shorted", and signifies that all terminals not designated by the
first two subscripts must be tied together and shorted to the
common terminal, which is always the second subscript.
Therefore, the term IGSS refers to the gate-source current
with the drain tied to the source.
Because of the typical low input and output admittance of
the FET, four-pole admittance equations are commonly used
to describe electrical characteristics of the FET:

(1)

\Vhel1 Y II , Y 21 , Y 12 and Y22 al~ u~fillta.l a~ Lh~ inpuL,
reverse transfer, forward transconductance, and output
admittances respectively, Equation 1 reduces to

(2)

For a three-lead FET, 11 usually corresponds to the gatesource terminal and 22 corresponds to the drain-source
terminal(i.e., the device is connected in the common-source
mode). Thus

ii = Yis Vgs + Yrs vds

io =Yfs

(3)

Vgs + Yos vds

Here, the second subscript for the y parameters designates
the source lead as the common or ground terminal.

Siliconix

14.--.--r-,--r--,--

IOSS- Drain Current at Zero Gate Voltage (ID at VGS = 0)
By itself, I DSS merely refers to the drain current that will
flow for any applied VDS with the gate shorted to the source.
However, when a particular value for VDS is given, equal to
or greater than Vp (see Figure 10), IDSS indicates the drain
saturation current at zero gate voltage. Some FET data
sheets label IDSS for VDS greater than Vp as ID(on).

lOSS

Ves - DRAIN SOURCE VOL rAGE (VOL lS)

I

I

FET 10 vs Vo Output Characteristics
Figure 11

I

The knee of the curve is important to the circuit designer
because he must know what minimum VDS is needed to
reach the pinch·off region with VGS = O. When appropriate
bias voltage is applied to the gate, it will pinch off the chan·
nel so that no drain current can flow; VDS has no effect
until breakdown occurs. The specific amount of V GS that
produces pinch.off is known as the gate·source cu toff voltage,

I
I

I---SATURATION REGION---I

I
I
I
I
Vp

Ves - DRAIN SOURCE VOLTAGE

VGS(off)·

BVOGS

VGS(off) Test Procedure
FET Characteristic at V GS = 0
Figure 10

VGS( off) - Gate-Source Cutoff Voltage
The resistance of a semiconductor channel is related to its
physical dimensions by R = pL/ A, where

p = resistivity
L = length of the channel
A = W x T = cross·sectional area of channel
In the usual FET structure, Land Ware fixed by device
geometry, while channel thickness T is the distance between
the depletion layers. The position of the depletion layer can
be varied either by the gate·source bias voltage or by the
drain·source voltage. When T is reduced to zero by any com·
bination of VGS and VDS, the depletion layers from the
opposite sides come in contact, and the a-c or incremental
channel resistance, rDS' approaches infinity. As earlier noted,
this condition is referred to as "pinch-off' or "cutoff' because the channel current has been reduced to a very thin
sheet, and current will no longer be conducted. Further
increases in VDS (up to the junction reverse·bias breakdown)
will cause little change in I D. Accordingly, the pinch.off
region is also referred to as the pentode or "constant·cur·
ren t" region.

Although the magnitude of VGS(off) is equal to the pinch.
off voltage, Vp, defined by the pinch·off knee in Figure 10,
rapid curvature in the area makes it difficult to defme any
precise point as Vp. Taking a second derivative ofVDS/I D
would yield a peak corresponding to the inflection point at
the knee, which approximates Vp. However, this IS not a
Simple measurement for production quantities of deVIces. A
better measure is to approach the cutoff point of the ID
versus VGS characteristic. This is easier than trying to specify
the location of the knee of the ID versus V DS output
characteristic.
A typical transfer characteristic I D versus VGS is shown in
Figure 12. The curve can be closely approximated by
VGS )
~1 -VGS(off)
---

ID=IDSS
14

\

12
10

Siliconix

(4)

IDS~

SLOPE"'~=9fS
..WGS

VOS=·5V

\

-Vos ~VGS(off)

1\\

TA=-55C

, \ ~TA=25C
06

4

In Figure 10, pinch.off occurs with VGS = O. In Figure 11,
VGS controls the magnitude of the saturated ID' with in·
creases in VGS resulting in lower values of constant ID' and
smaller values of VDS necessary to reach the "knee" of the
curve. The current scale in Figure II has been normalized to
a specific value of I DSS.

2

-

"'~

,,~

2~Tr151f1
04

DB

~
12

~

16

20

VGS(off)

24

28

VGS - GATE-SOURCE VOLTAGE (VOLlS)

Typical 10 vs VGS Transfer Characteristic
Figure 12

7-7

Equation 4 and Figure 12 indicate that at VGS = VGS(off)'
ID = O. In a practical device, this cannot be true because of
leakage currents. If I D is reduced to less than 1 percent of
I DSS, V GS will be within 10 percent of the VGS(off) value
indicated by Equation 4. If I D is reduced to 0.1 percent of
I DSS ' the indicated VGS(off) error will be reduced to about
3 percent. For a true indication of VGS(off)' and a realistic
picture of the parameters of Figure 12, care must be taken
that leakage currents do not result in an error in the VGS(off)
reading. Typically, at room temperature, I percent ofI DSS
is still well above leakage currents but is low enough to give
a fairly accurate value of VGS( off)'

IGSS - Gate-Source Cutoff Current
The input gate of a P-Channel FET appears as a simple PN
junction; thus the input doC input characteristic is analogous
to a diode V-I curve, as is shown in Figure 14.

BVGSS

A typical circuit for measuring VGS(off) is shown in Figure
13. At V GS = 0, the value of I DSS can be measured. Then,
byincreasingVGS until IDis 0.01 percent ofIDSS' the value
of VGS(off) is obtained. From a production standpoint, it
is more convenient to specify ID at some fixed value (such
as I nA), rather than as a certain percentage of I DSS' Thus
a pinchoff voltage specification may be given as indicated in
Table I.

10

-10

30

20

40

VGS - GATE VOL TAGE (VOL TS)

-1

P-Channel FET Input Gate Characteristic
Figure 14

In the normal operating mode, with VGS positive for a PChannel device, the gate is reverse-biased to a voltage between zero and VGS(off)' This results in a doc gate·source
resistance which is typically more than 100M n. The gate
current is both voltage- and temperature-sensitive. Figure
15 shows this relationship for IGSS versus temperature and
VGS'

104 r-~-"---'-="'--~""-T""--'
IGSS IS NORMALIZED TO VALUE AT

103I-T_A_.+25_·c_A+N_D_V-+GS_o_30-jV_+_t----1>""/71

Circuit for Measuring VGS(OFFI
Figure 13

I Vj~

102 f---+-+--t---\--'-:>4c"£-¥---1

Table I
Typical Pinch-Off Voltage SpeCification

I

I

Characteristic

VGSloffl

Min

I

Max

I

Units

1

4

10

~

,

~

I

Gate-source pinch-off voltage of

VOS =-5 V.IO =-lI'A

:

Volts

~~V_+----j
Vos=o-

.-0V;~ I

I

l¥rrllill
a

~

0

~

~

H

~

~1~

TA - AMBIENT TEMPERATURE (OC)

Another method which provides an indirect indication of
the maximum value of VGS(off) is shown in Table II. The
characteristic specified is ID(off)' whereas the parameter of
interest is VGS =8 volts. The specification does say that the
maximum VGS(off) is approximately 8 volts, but no provision is made for stating a minimum VGS(off)' as was done
in Table I. Therefore, another test must be made if
VGS(off) (min) is to be specified.

Table II
Indication of Maximum Vp

Characteristic

IOloffl

Pmch·off
drain current

7-8

Test Conditions

VOS

-12 V,
V GS = 8 V
=

Moo

Max

Unit

-10

I'A

IGSS V5 Temperature
Figure 15

If the gate-source junction becomes forward-biased, (negative voltage in a P-Channel device) or if VGS exceeds the
reverse-bias breakdown for the junction, the input resistance
will then become very low.
The FET is normally operated with a slight reverse bias
applied to the gate-source; hence a good measure of the doc
input characteristic is to check the gate current at a value
of gate-channel voltage that is below the junction breakdown rating. In device evaluation, there are three common
measurements of gate current: IGDO' I GSO , and the combined measurement I GSS ' These measurement circuits are
shown in Figure 16.

SilicDnix

The question is, should I GDO and IGSO be measured
separately, or will one measurement of IGSS suffice? One
thing is certain: IGSO + I GDO > IGSS, because the drain
and the source are not completely isolated. They are, in
fact, electrically connected via channel resistance. For most
FETs, if VG is greater than VGS(off)' the difference between
(IGSO + I GDO ) and IGSS is small; therefore, the measure·
ment of IGSS is a realistic means of controlling both I GDO
andI GSO ·
In a circuit, VGD may be biased between zero and BV GDS,
while VGS will be between zero and VGS(off): therefore,
IG is not necessarily the same as IGSS.
BV GSS - Gate-Source Breakdown Voltage
FET input terminals have been previously described as having
NP or PN junctions, depending on the channel material. As
such, the junction breakdown voltage is a necessary
parameter.
A useful equivalent circUlt for a FET is the distributed con·
stant network shown in Figure 17, for a P·Channel FET. If
an N-Channel device is being evaluated, the diodes would be
reversed. In most applications, the gate·drain voltage is
greater than the gate·source voltage; thus the gate·drain
breakdown ratmg is most important. However, it is also pos·

sible to consider the gate·source junction breakdown and
the apparent drain-source breakdown (i.e., in Figure 17,
when a high negative voltage is applied from drain to source,
CRt will break down while CRn becomes forward·biased).
Some device manufacturers use a BV GDO rating, which
means they are only checking diode CRI. A better method
is to use a BV GSS rating (gate·source breakdown with the
drain shorted to the source), because it checks both CRI
and CRn' in addition to exposing the weakest breakdown
path along the entire gate·channel junction. The BV GSS test
also allows the user to in terchange source and drain lead con·
nections without worry about device breakdown ratings.
Admittedly, a BV GSS test will reject some units which
might pass a BV GDO test; the number rejected, however,
will be insignificant compared to the advantage of providing
symmetrical operatIOn.

Test Procedures for BVGSS
Junctions may break down softly or sharply;junctions with
soft knee breakdown are undesirable. Without examining
each individual unit on a curve tracer, devices with a soft
knee may be eliminated by selecting a low current level for
breakdown measurement (see Figure 18).

GATE

0--...,..--'1+-.....- - 0 DRAIN

CR"

-----""'--0

SOURCE

A Useful FET Equivalent Circuit
Figure 17

Three Common Measurement of Gate Current
Figure 16

SOFT KNEE (FAILING)

-

SHARP BREAKDOWN

Examples of Soft Knee and Sharp Knee Breakdown
Figure 18

Siliconix

7-9

gfs - Transconductance
Transconductance, gfs' is a measure of the effect of gate
voltage upon drain current:

tJo
gfs =LWGS ' VOS =constant

Specifications for gfs are shown in Tables III and IV. Note
that there is a difference in the test conditions specified for
the N-Channe12N3823 and the P-ChanneI2N3329. The gate
voltage for the 2N3823 is established as zero. This means
that gfs is measured at ID = IDS S, as in Table III.

(5)
Table III 12N38231
Test

Characteristic

The interrelation of gfs to the parameters lOSS and
VGS(OFF) should be noted. Equations 4, 6 and 7 describe
the value of 10 and gfs in a FET for any value of VGS
between zero and VGS(OFF).

9f. Small-signal commonsource forward

transconductance

Characteristic

(7)

where gfso is the value of gfs at VGS = 0 and IDSS is the
value of ID at VGS =O. With these equations, the value of
gfs can be calculated with a fair degree of accuracy (20 per·
cent) ifI DSS and VGS(off) are known.
Figure 19 shows normalized curves for I D and gfs as functions of VGS in a P-Channel FET. These curves were obtained from actual measurements on typical diffused channel FETs, such as the 2N2606. The curves agree very weJl
with Equations 4 and 6 un til V GS( off) is approached. For
these curves, VGS(off) was assumed to be the value of VGS
where ID/IDSS =0.001.

YI. Common-source
forward transfer
admittance

Max

Unit

3,500

6,500

.umho

Test
Conditions

Mm

Max

Unit

20

"mho

V OS =-10V,
I D =-1mA
1=1 kHz

The test conditions shown in Table IV specify a certain
value for I D (-1 rnA for the 2N3329). This means that for
each unit tested, VGS is adjusted until I D equals the specified value. The conditions specified in Table III simplify
testing of the gfs parameter by eliminating the necessity of
adjusting V GS' Figures 20 and 21 show typical test setups
for the two methods.

L

'V lkc

9fsfl]fs

VOS= 15V,
V GS = 0,
1=1 kHz

Min

Table IV (2N3329)

(6)

210SS
gfso =- VGS(off)

Conditions

-f---

T

~

i !~~~!~'D~/lD~"SS~~I~I~~
=
10-1 -VOS=-5V f=lkc

FOR gl5 MEASUREMENTS

Test Circuit for 9fs with VGS = 0
Figure 20

11_- VDS

Normalized Curves for 10 and g15
as Functions of V GS
Figure 19

The drain current of a JFET operating in the triode (below
pinch-off) region can be accurately predicted by using Equation 8, where

~

)~

.
VOS
lo/tnode = lOSS V - - GS(off)

7-10

(8)

Siliconix

v

Test Circuit for 915 with 10 Specified
Figure 21

Junction FET Capacitances
Associated with the junction between the gate and the channel of a FET is a capacitance whose value and geometric
distribution are functions of the applied voltages VGS and
V DS - Because of the complexity of dealing with such a
distributed capacitance, a simplification is made so that two
lumped capacitances, CgS and Cgd , exist between the gate
and the source and drain, respectively. (A much smaller
capacitance, Cds' also exists between tne drain and the
source, stemming mainly from the device package; this
header capacitance is small enough so that it can be ignored
for most purposes.)
Data sheets quote Cgs and Cgd (or other capacitances from
which they may be derived) for specified operating conditions. Occasionally, graphs are included which show the
variations of Cgs and Cgd as the result of changing conditions of V DS, VGS and temperature. If these data are not
presented, an estimate of inter·electrode capacitance values
may be made by assuming that these values vary inversely
with the square root of the bias voltage. The temperature
variations will be very small, because they depend on the
-2.2 mV;oC change injunction potential difference.
Assuming that the FET is properly biased - that is, that the
doc conditions are met by the external circuitry - It is possible to construct an incremental equivalent circuit from
which the small-signal or a-c performance may be predicted.
Such an equivalent circuit is shown in Figure 22.

',d

I

Go-----~--~~--~

I

D

C,d

>--

1

Vas

I

'~II

'"

CO'

>--

': o~

(g;;;-)

So-----_+------------------~----_+----~
NOTE

The incremental channel current is given by the transconductance, gfs' multiplied by the incremental gate voltage.
For the small signal, vgs ' this is manifested in the equivalent
circuit by the current generator gfsvgs. Notice that the conventional direction of flow of this current is such that id
flows into the FET, in a "positive" direction.
Many circuits can be designed around the equivalent circuit
for the junction FET. The actual values of gfs adn rds can
be measured as previously mentioned; there remains only
the requirement to establish the methods of determining
Cgs and Cgd.
First, assume that the FET is in operation and that the drain
is connected to the source via a large capacitor, i.e., the
drain and source are short-circuited to a-c. Under these circumstances, a capacitance measurement between the gate
and the source will give
Cgss (or Ciss) = Cgs + Cgd

Second, assume that the gate and source are short-cirCUIted
to a-c in a similar manner. A capacitance measurement between the drain and the source will now give
Cdss (or Cos s)

~

Cgd

(10)

The alternative symbols C ISS and Coss simply refer to measurements made at the Illput (gate) and the output (drain)
respectively. An alternative symbol for Cgel IS Crss , whIch
refers to the "reverse" capacitance.
In data sheets, It IS customalY to state (= Ciss) Cgss and
Cdss (= Coss)· Crss IS often given III place of Coss because
if Cds <{ Coss, which is usually the case, then C rss == Coss
Equations (9) and (10) can be used III those instances where
it is necessary to extract Cgs and Cgd, as in
Cgs = Ciss - Cgd = Ciss - Crss

s

(9)

(11)

and

Cgss" c1ss = Cgs + Cgd

Coss" Cgd + Cds

~

Cgd

=

Cgd = Crss

Crss

Incremental Equivalent Circuit for the Junction FET
Figure 22

The equivalent capacitance from the gate to the source, CgS '
is shunted by a very large input resistance, rgs ' with both of
these parameters being characteristic of a reverse-biased
junction. Similarly, the equivalent capacitance from the gate
to the drain is shunted by the very large resistance rgd. (For
most purposes, rgs and rgd may be neglected, and the gate
impedance of the FET treated as pure capacitance). At the
drain side of the equivalent circuit the small capacitance
Cds - which stems from the header material- is shunted by
the incremental channel resistance, rds. This resistance is
capable of wide variations, depending on bias conditions.
Since the equivalent circuit is fundamentally relevant to the
pinch-off or saturated condition, rds will be on the order of
megohms.

(12)

Remember that all capacitance measurements should be
made at the same bias levels, since the capacitances are functions of applied voltages. To indicate the order of the capacitances to be found in a junction FET, consider the values
given in the data sheet for the Silicolllx 1202 N-channel
FET. They are given as
Ciss (at VDS = 20 V and f = I MHz) = 5 pF max.
and
Crss (at VDS = 20 V and F = I MHz) = 2 pF max.
Hence, at a drain-soUlce voltage of 20 V and a frequency of
I MHz, Cgs = 5 - 2 = 3 pF maximum. Even though the FET
is physically symmetrical, bias conditions have forced the
capacitances to be unequal.

Silicanix

7-11

-

H

Siliconix

FET Biasing

INTRODUCTION
Engineers often design FET amplifiers that are unnecessarily
sensitive to device characteristics because they may not be
familiar with proper biasing methods.
One way to obtain consistent circuit performance in spite of
wide device variations is to use a combination of constantvoltage and self biasing. The combined circuit configuration
turns out to be the same as that generally used with bipolar
transistors, but its operation and design are quite different.
Three Basic Circuits

Vos iVOLTS)

Let's examine three basic common-source circuits that can
be used to establish a FET's operating point (Q-point) and
then see how two of them can be combined to provide
greatly improved performance. The three basic biasing
schemes are:
• Constant-voltage bias, which is most useful for rf and
video amplifiers employing small dc drain resistors.

Figure 1. A large dynamic range is provided by the operating point
at VDsa = 15 V, loa = 0.39 mA and VGSa = -0.4 V. The output
characteristics are for a typical 2N4339.

The constant-voltage bias circuit (Figure 2) is analyzed by
superimposing a line for VGG = constant on the transfer
characteristic of the FET.

• Constant-current bias, which is best suited to lowdrift dc amplifier applications such as source followers
and source-coupled differential pairs.

rt

VOO

RG

-VGG

12

":"

CONSTANT

~~~ LOAD

.B

I

-16

-1.2

Figure 2. Constant-voltage bias is maintained by'the V GG supply as
shown on this typical 2N4339 transfer curve. Input signal eg moves
the load line horizontally.

Reprinted From ELECTRONIC DESIGN, May 24, 1970, June 7,1970.

7-12

OUTPUT

"

The Q-point established by the intersection of the load line
and the VGS = -0.4 V output characteristic of Figure I
provides a convenient starting point for the circuit comparison. The load line shows that a drain supply voltage, VOO '
of 30 V and a drain resistance, RO' of 39K n are being used.
The quiescent drain-to-source voltage, VOSQ' is 15 V,
allowing large signal excursions at the drain. Maximum input
signal variations of ±0.2 V will produce output voltage
swings of ±7.0 V - a voltage gain of 35.

vos= 15V

RO

• Self bias (also called source bias or automatic bias),
which is a somewhat universal scheme, particularly
valuable for ac amplifiers.

Siliconix

The transfer characteristic is a plot of I D vs VGS for constant
VDS. Since the curve doesn't change much with changes in
VDS , it is quite useful in establishing operating bias points.
In fact, it is probably more useful than the output characteristics because its curvature clearly warns of the distortion to
be expected with large input signals. Furthermore, when a
bias load line is superimposed, allowable signal excursions
become evident and input voltage, gate-source signal voltage,
and output signal current calculations may be made
graphically.

VOS .. 15V

12

DB

/_-_~r---~~--~04
DC LOAD LINE

-16

The heavy vertical line at VGS =-0.4 V establishes the Qpoint of Figure 1. No voltage is dropped across resistor RG
because the gate current is essentially zero. RG serves mainly to isolate the input signal from the VGG supply.
Excursions of the input signal, eg, combine in series with
VGS so that they add algebraically to the fixed value of
-0.4 V. The effect of signal variation is to instantaneously
shift the bias line horizontally without changing its slope.
The shifting bias line then develops the output signal current
as shown in Figure 2.
The constant-current bias approach (Figure 3) for establishing the Q·point of Figure 1 requires a 0.39-mA current
source. For an ideal constant·current generator, input signal
excursions merely shift the bias line horizontally and produce no resultant gate-source voltage excursion. This bias
technique is therefore limited to source followers, sourcecoupled differential amplifiers, and to ac amplifiers where
the source terminal is bypassed to ground at the signal frequency.

Ff

v OO

VOS=15V

RO

eg

Ro

-=-

OUTPUT

,:}

-=-

-: AC LOAD LINE

-12

Figure 4. Partial bypassing of the current source (Figure 3) lowers
the circuit gain by tilting the ac load line from the vertical. The
capacitor drop subtracts from ego

This will lower the gain of the amplifier because of signal
degeneration at the source. The input signal, eg, is reduced
by the drop across the capacitor:

(I)
It is clear from Figure 4 that the input signal only shifts the
operating point by an amount equal to VgS ' the effective
input signal. As the signal frequency is decreased, the slope
of the ac bias line decreases, causing the effective input signal to approach zero.

Self Bias Needs No Extra Supply
The self-bias circuit (Figure 5) establishes the Q-point by
applying the voltage dropped across the source resistor, RS,
to the gate. Since no voltage is dropped across RS when
I D = 0, the self-bias load line passes through the origin. Its
slope is given by -I/RS. Therefore, the desired Q-point is
established by setting -l/RS = IDQ/VGSQ.

12

~
o

DB

i5
3'
1:

+VO:UTPUT

vos -15 v

12

'g

RG

-=-

-1.

RS

-=-

08

'd --Lb---~'

Figure 3. Constant-current bias fixes the output voltage for any RD.
Hence, input signals cannot affect the output unless the current
source is bypassed.

If an ac ground is prOvided by a bypass capacitor across the
current source, a vertical ac bias line will be established.
Input signal variations will then translate the ac bias line
horizontally, and signal development will proceed as with
constant-voltage biasing (Figure 3).
Should the bypass capacitor not provide a sufficiently low
reactance at the signal frequency, the ac bias line will not be
vertical. It will still intersect the transfer curve at the Qpoint but with a slope equal to -{l/Xc) = -wc (Figure 4).

-16

-12

-08

_

o

!

S~~~~I~N~C
04

-04

VGS IVOLTS)

Figure 5. The self·bias load line passes through the origin with a
slope -1/RS. Bypassing RS will steepen the slope and increase the
gain of the circuit.

Signal development is the same as in the case of the partially
bypassed constant-current scheme except that the load line
is a dc bias line. Signal degeneration is described by Equation 1 with Xc replaced by RS. The ac gain of the circuit
can be increased by shunting RS with a bypass capacitor, as
in the constant-current case. The ac load line then passes
through the Q·point with a slope - (1/Zs) = -(we + I/RS).

Siliconix

7-13

-

The circuit is biased automatically at the desired Q-point,
requires no extra power supply and provides a degree of current stabilization not possible with constant-voltage biasing.
A fourth biasing method, combining the advantages of constant-current biasing and self biasing, is obtained by combining the constant-voltage circuit with the self-bias circuit
(Figure 6). A principal advantage of this configuration is
that an approximation may be made to constant-current
bias without any additional power supply. The bias load line
may be drawn through the selected Q-point and given any
desired slope by properly choosing VG G' (The bias line intercepts the VGS axis at VGG .) The larger VGG is made, the
larger RS will be and the better will be the approximation
to constant-current biasing.

Biasing for Device Variations
The value of the combination-bias technique becomes apparent when one considers the normal production spread of
device characteristics. The problem is illustrated in Figure 7
VGS=O

12

-02V

08

-04V

04

_Dav

1
E

-D6V

-10V
-12V

10

40

50

VOS(VOlTSl

+Voo

+VOD

3IJ

20

+VOD

1.2

08

eo
VGS=D

04

-02V
QA

c

b

-04V
-D6V

10

20

30

40

50

Vos (VOLTS)

VOS=15V

Figure 7. The wide variations in device performance shown by this
pair of output characteristics make clear the disadvantages of con·
stant~voltage biasing.

12

-16

-12

-08

-04

VGS (VOLTS)

+04

+08

+12

+16
VGG

Figure 6. All three combination-bias circuits are equivalent. They
add constant·voltage biasing to the self·bias circuit to establish a
reasonably flat load line without sacrificing dynamic range.

All three circuits in Figure 6 are equivalent. Circuit 6(a)
requires an extra power supply. The need for an additional
supply is avoided in 6(b) by deriving VGG from the drain
supply. R 1 and R2 are simply a voltage divider. To maintain
the high input impedance of the FET, Rl and R2 must
both be very large.
Very large resistors cannot always be found in the exact ratio
needed to derive the desired VGG in every circuit application. Circuit 6(c) overcomes this problem by placing a large
RG between the center point of the divider and the gate.
This allows Rl and R2 to be small, without lowering the
input impedance.
One point of caution worth remembering is that as VGG is
increased, Vs increases, and VDS decreases. Therefore with
low VDD , there may be a Significant decrease in the allow·
able output voltage swing.

7-14

where two limiting sets of output characteristics, representing the actual min-max spread of the Siliconix 2N4339, are
presented. Limiting characteristics like these are not normally available. Even if they were, however, they'd be of
little help in establishing operating points suitable for all
devices with output characteristics lying between the two
extremes. The problem is much more easily approached by
llsiIlg the sct of lirrJting transfer chaiactelistil,..s of FigUltl 8.
(See next page.)
Attempting to establish suitable constant-voltage bias conditions for a production spread of devices is practical only for
circuits with very small values of dc drain resistance - for
example, circuits with inductive loads. As the constantvoltage bias plot of Figure 8 reveals, constant gate bias causes
a significant difference in operating IDQ for the extreme
limit devices. At VGS =-0.4 V, the range ofIDQ is 0.13 to
0.69 rnA, and VDS Q for a given RD will vary greatly for
most resistance-loaded circuits. For the example of Figure 1,
with RD = 39K n and VDD =30 V, VDSO varies from near
saturation (5 V) to 25 V.

An apparently excellent method of biasing is the constantcurrent method of Figure 3. Biasing in this manner fixes the
operating drain current for all devices and sets VDS Q to
VDD - IDQRL for any device in the production spread.
VGS automatically finds a value to set the appropriate
IDQ = constant for all devices. For the constant-current
bias plot of Figure 8, with IDQ = 0.39 rnA, VGS would
range from -0.11 to -0.67 V.

Siliconix

15

15
VOS

Vos= 15V

08

".,e

-12

-16

-DB

-12

VOS= 15V

-08

-04

VGS (VOLTS)

VGG=04V

VGS (VOLTS)

".,e

04

04

-16

15V

12

12

08

=

15

r-------------~~--_,_15

VOS=15V

12

08

".,e

04

-16

-12

-08

-16

-04

+12

+16

VGS (VOLTS)

VGS (VOLTS)

Figure B. The advantages of combination biasing, when one is working with a spread of device characteristics, are made obvious by plotting
the load lines for the various types of biasing on a pair of limiting transfer curves.

Output characteristics are not needed as long as I DQ is
chosen to be below the minimum I DSS . With RD = 39K n
and VDD = 30 V, VDS Q is 14.8 V for all devices.
The disadvantages of the constant-current method are that
it allows no signal to be developed unless the current source
is bypassed and, as we shall see, it lacks the flexibility to
provide constant gain despite variations in the forward
transconductance, gfs' of the devices.
The self-bias scheme is a reasonable choice for single-ended
de amplifiers and for ac amplifiers. In unbypassed or dc circuits, some compromise must be made between the gain
loss due to current feedback degeneration and the advantage
of current stabilization achieved with high RS.
An appropriate choice of I DQ limits can be made by using
the pair of limiting transfer curves. For example, for RS =
lK n, the load line shown on the self-bias curve of Figure
8 is established. The maximum I Dis 0.52 rnA, and the minimum I D is 0.24 rnA. The operating range of VDS Q may be
calculated for any value of VDD and RD. Clearly, for
RD = 39K n, the maximum-limit device (device B) would
operate with VDS Q = 9.8 V and the minimum-limit device
(device A) would operate with VDSQ = 20.6 V. This results
in fairly satisfactory operation for all devices. However, such
a variation in IDQ imposes severe limitations on the circui t de sign.

A better approach is illustrated by the combination-bias
curve of Figure 8 with VGG = 1.2 V. The range ofIDQ for

this bias condition is 0.25 rnA to 032 rnA. A similar minimum difference in I DQ could be achieved with RS = 6K n
and VGG = 0, (a self-bias condition) but the operating points
would be pushed toward the toe of the transfer characteristics and allowable signal input would be reduced.
The upper load line allows Vgs = ± 1.8 V (limited by I DSSA)'
while the lower line allows a Vgs of only ±0.7 V (limited by
VCS( off)A)· (The subscript letters A and B refer to the minimum and maximum devices, respectively.) The combination
circuit allows almost ideal operation over the full production
spread of devices. Even with RD = 62K n, the VDSQ would
range only between 10 and IS V.

For this circuit, RD should be chosen to allow the largest
output signal swing for I DQ midway between the two
extremes of 0.25 and 0.32 rnA; namely 0.285 rnA. Setting
the voltage drop across RD at one-half of (VDD 2VGS (off)typ) or 14 V, yields RD = (14 V/0.285 rnA) =
49Kn.

It is helpful, in any design, to know the effect of tempera-

ture variations on the transfer curves and transconductance
characteristics. Ideally, minimum and maximum transfer
characteristics would be plotted at three temperatures:
above, below, and at room temperature. Then the design
would take all types of variation into account.

Siliconix

7-15

-

Minimize the Gain Variations

Leaving RS unbypassed helps reduce gain variations from
device to device by providing degenerative current feedback.
However, this method for minimizing gain variations is only
effective when a substantial amount of gain is sacrificed.
A better approach is to use the combination-bias technique
with the bias ppint selected from the transfer and transconductance curves (Figure 9).

,---------:v::-o-s.::-:,::".:7
v".5

Step 5.

Travel vertically up to the maximum limit
transfer curve to find IDQB at VGSQB' This
is IDQB "" 0.36 rnA.

Step 6.

Construct an RS bias line through points
QA and QB on the transfer curves. The slope
of the line is l/RS' and the intercept with the
VGS axis is the required VGG .

As Figure 9 demonstrates, it may be somewhat inconvenient
to perform Step 6 graphically. An algebraic solution can then
be employed instead. The source resistance is given by

(2)
and the bias voltage is
VGG =RS IDQB + VGSQB

(3)

Care should be taken to maintain the proper algebraic signs
in Equations 2 and 3. (For n-channel FETs, VGS is negative
and I D is positive. For p-channel units, the signs are reversed.)

If the transconductance cUrves of Figure 9 are not available,
gfs can be determined by simply measuring the slope of the
transfer curve at the desired operating point. Just place a
straight-edge tangent to the curve at the Q-point and note
the points at which it intercepts the ID and VGS axes. The
slope and gfs are given by:
slope = gfs = ID(intercept)/- VGS(intercept)

Figure 9. Gain variations are minimized when the load line is de-

signed to intersect the pair of limiting transfer curves (top) at points
of equal gf. (bottom).

As Figure 9 shows, it is possible to find an RS and a VGG
that will set IDQA and IDQB to values so that gfsQ will be
the same for both devices. The gfsQ of ~!! int('rmediat('
devices will be approximately equal to the limiting values.
Thus, a constant, or nearly constant, stage gain is obtained
even with a bypass capacitor.
The design procedure is as follows:

Step 1.

Select a desired I DQA below I DSSA- A good
value, allowing for temperature variations, is
60% ofl DSSA- This will allow for decreasing
IDSS due to temperature variation and for
reasonable signal excursions in load current.

Step 2.

Enter the transfer curves at I DQA ""
0.6 IDSSA (0.3 rnA) to find VGSQA' This
VGSQA "" 0.2 V for the 2N4339.

Step 3.

Drop vertically at VGSQA to the minimum
limit transconductance curve to find gfsQAThe value as read from the plot is approximately 1000 ILmho.

Step 4.

Travel across the gfs plot to the maximum
curve to fmd VGSQB at the same value of
gfs' This is VGSQB "" -0.7 V.

7-16

(4)

In designing a constant-gain circuit, simply set the straightedge tangent to the transfer curve of device A at point QA
and slide it, without changing its slope, until it is tangent to
the curve of device B. The tangency point is QB'
Designing Without Output Curves
Although the transfer characteristic has been seen to be
extremely valuable in designing a bias ciicuH, 1t cannot be
used to graphically establish VDSQ ' However, if a set of output curves is not available, VDS Q can be determined or
selected from the transfer curve by using the following procedure:

Step 1.

Establish RS and limiting values of I DQ ,
VGSQ and gfsQ from the transfer curve.

Step 2.

Establish VDD as available, but in no case
greater than BVGSS nor less than several
times VGS(off)' There are special cases where
VDD will be below this limit, but in no case
should instantaneous Vdg be allowed to fall
below 2 x VGS(off) if minimum distortion is
to be achieved.

Step 3.

Set VDS Q approximately midway between
VDD and 2 x VGS(off); lower iflarge output
signals will not be handled.

Step 4.

Select RD to give the appropriate VDSQ ' The
formula is:

RD = [(VDD - VDSQ)/0.5 IDQA + IDQBl -RS

Silicanix

(5)

In the example of Figure 8, this procedure would have
yielded VOSQ;(30-3)/2; 13.5 V and RO; (30 - 13.5)/0.5
(0.52 + 0.24) rnA - IK n ; 42.SK n.

Step 5.

By considering 10 circuits, which represent virutally every
source-follower configuration, the designer can obtain consistent circuit performance despite wide device variations.
There are two basic connections for source followers: with
and without gate feedback. Each connection comes in
several variations (Figure 10). Circuits 10(a) through 10Ce)
have no gate feedback; their input impedances, therefore, are
equal to RG. Circuits 10{f) through 10(k) employ feedback
to their gates to increase the input impedance above RG.

Check to ensure that with this R O' device B
is not in a saturated condition - VOQB ;
VOO - IOBQ Ro > 2VGS(0ff) + RS IOBQ·
Decrease RO if this condition is not met.

An alternate method, that selects Ro to provide a specified
voltage gain, follows Steps I and 2 above and then proceeds
as follows:
Step 3.
Step 4.

Determine required stage gain, Av' and set
RO ; Av/gfsQ·
Calculate VOSQ to ensure that the criteria
of Step 2 are not violated:

VDSQ ; VDD - (RD + RS) IDQ

Step 5.

Before getting into the details of bias·circuit design, note
several general observations that can be made about the
circuits of Figure 10:
• Circuits a, d and f can accept only positive and small
negative signals, because these circuits have their
source resistors connected to ground. The other circuits can handle large positive and negative signals
limited only by the available supply voltages and
device breakdown voltage.

(6)

• Circuits c, d, e, h, j, and k employ current sources to
improve drain-current (In) stability and increase gain.

If necessary, change I OQ ' VOD' Av and/or
Rn to obtain an optimum compromise . ••

• Circuits d, e and k employ FETs as current sources.
In circuit d, Q2 must have a lower cut-off voltage,
VGS(off)' and a lower zero gate·voltage drain current,
InSS' than Ql.
• Circuits e, g, h and k employ a source resistor, RS'
which may be selected to set the quiescent output
voltage equal to zero.

FET SOURCE-FOLLOWER CIRCUITS
Too little knowledge of biasing methods for FET amplifiers
sometimes keeps engineers from making maximum use of
FETs in circuit designs. The common-drain amplifier, or
source follower, is a particularly valuable configuration; its
high input impedance and low output impedance make it
very useful for impedance transformations between FETs
and bipolar transistors.
+VOD

+VOD

AS

+VOD

-Vss

-:.-

b

+VOD

+VOD

+VOD

AG

AS

-Vss

a

• Circuits e and k use matched FETs. RS is selected to
set In near the specified low-drift operating current.
The input·output offset is zero.

d

c

+VOD

+VOD

+VOD

+VOD

e

-

AS1
AS

AG

AG

AS

°2
AS2

-Vss

-Vss

h

k

Figure 10. Virtually every practical source-follower configuration is represented in this collection of ten circuits. The configurations in the
top row do not employ gate feedback; the corresponding ones in the bottom raw do.

Silicanix

7-17

Biasing Without Feedback is Simple
The no-feedback circuits of Figure 10 (circuits IO(a) through
IO(e) use simple biasing techniques (see the earlier article).
Circuit IO(a) is a self-bias configuration; the voltage drop
across RS biases the gate (which draws essentially zero current) through resistor RG' Since no gate-to-source voltage,
VGS ' can be developed when In = 0, the self-bias load line
passes through tpe origin (Figure II). For the 2N4339 FET,
whose limiting transfer characteristics are used throughout
this article, the quiescent drain current is seen to lie between
about 0.25 and 0.55 rnA when a IK n source resistor is
used. The quiescent output voltage lies between +0.25 and
+0.55 V.

Circuit IO(d) is similar to IO(c) except that the VGS =0 output characteristic of FET Q2 is used as a current source. As
seen in Figure 13,02 does not supply constant current when
its VnS gets very small. This technique should therefore be
used only to bias FETs whose VGS(off) is Significantly higher than the equivalent VGS(off) of the current-source
FET diode.
r----------~15
VOS=15V

12

08

04

.--------::V-08-="""'5"'V,,'5
12

-16

-12

-08

-04

VGS !VOLTS)

08

Figure 13. FET 02 doesn't behave like an ideal current source when
its VOS gets very small (Figure IOd). Therefore, 01 should have a
significantly larger VGS(off) than 02 does.

04

-1.6

-12

-04

-D8

VGS (VOLTS)

Figure 11. Self biasing (Figure IDa) uses the voltage dropped across
the source resistor, RS to bias the gate. The load line passes through
the origin and has a slope of -1/RS.

A pair of matched FETs is-used in the circuit of Figure IO(e),
one as a source follower and the other as a current source.
The operating drain current (InQ) is set by RS2, as indicated
by the load line of Figure 14. The drain current may be anywhere from 0.20 to 0.42 rnA, as shown by the limiting
transfer characteristic intercepts; however, VGS I = VGS2
because the FETs are matched.
r-------~-~rI5

VDS=15V

12

Circuit 100b) is another example of source-resistor biasing
with a -VSS supply added. The advantage over circuit lO(a)
is that the signal voltage can swing negative to approximately-VSS ' Two bias lines are shown in Figure 12, one for
VSS = -15 V and the other VSS = -1.6 V. For the first case,
the quiescent output voltage lies between +0.18 and +0.74 V.
For the second, it lies between +0.3 and +0.82 V.

08

04

VGS (VOLTS)

,----------r '5

Figure 14. This load line is set by RS2 and 02 which acts as a current source (Figure IDe). If its components are properly matched,
the circuit will have zero or near-zero offset.

Ves" 15V

12

08

Since 1m = In2 and VGSI = VGS2, choosing RSI = RS2
will ensure that the voltage from point A to B equals the
voltage point from point C to D (Figure IO(e». This source
follower, therefore, exhibits zero or near-zero offset. If the
FETs are temperature-matched at the operating In, the
source follower will exhibit zero or near-zero temperature drift.

C

~
04

Rs=60K

Rs"

-1.

-12

-08

-04

10K

+04

VSS=-15V

VSS=-16V

+08

+12

+16

Biasing With Feedback Increases Zm

VGSIVOLTSI

Figure 12. Adding a VSS supply to the self-bias circuit (F igure 1Db)
allows it to handle large negative signals. The load line's intercept
with the VGs·axis is at VGS = -VSS. Bias lines are shown for
VSS = -15 V and VSS = -1.6 V.

The bias load line for circuit IO(c) is just a horizontal line
(I n = constant). The quiescent output voltage is between
+0.15 and 0.7 V for In =0.3 rnA.

7-18

Each of the feedback-type source followers (Figure 10(f)
through 100k) ) is biased by a method similar to that used
with the nonfeedback circuit above it. However, in each
case, RG is returned to a point in the source circuit that
provides almost unity feedback to the lower end of R G. If
RS is chosen so that RG is returned to zero dc volts (except
in circuit 10(f), then the input/output offset is zero. RI is
usually much larger than RS'

Siliconix

Circuit 10(1) is useful principally for ac·coupled circuits. RS
is usually much less than Rita provide near· unity feedback.
The bias load line is set by RS (Figure IS). The output load
line, however is determined by the sum of RS + R l' The
feedback voltage VFB , measured at the junction of RS and
R 1, is determined by the intercept of the RS + R 1 load line
with the VGS axis. The quiescent output voltage is
VFB - VGS'
r--------------------,-15
12

oa

<5

3"
1!
RS + Rl "10K

04

AS + R, '" 10K

·16

-12

-04

·OB

<04

.oa

"2

"6

circuit l(h) differs from that of Figure 10(g) (Figure 16) in
that the load line is perfectly flat. In Figure 16 the load line
is almost, but not quite, flat; it has a slope of -I/SOk.
Circuit 1O(j) is similar to 10(h) except that the output is
taken from the top of RS to reduce the output impedaI)ce.
RS must be trimmed if the circuit is to work at all properly.
In Figure 17, the constant·current load line represents a
0.3·mA current source, and the effect of a IK n source
resistor is shown. The offset voltage is seen to lie between
0.2 and 0.75 V. The intercept of the RS load line and the
VGS axis sets the voltage at the junction of RS and the cur·
rent source (VFB ). For RS = IK n, VFB will be between
-0.1 V and +0.45 V. Since VFB appears at the gate, it must
be zero if the dc input impedance of the circuit is to
be preserved.
r-------------~~~_,_15

VOS"'15V

VGS (VOL TS)

Figure 15. The bias load line is set by RS but the output load line is
determined by RS + Rl when gate feedback is employed (Figure
lot). The feedback Vfb is determined by the intercept of the
RS + Rl load line and the VGS axis.

12

In the circuit of Figure 10(g), RS can be trimmed to provide
zero offset. As the curves show (Figure 16), RS will be
between 670 ohms and 2.SK n. RS is much less than R 1.
The source load line intercepts the VGS axis at VSS =
-VGG=-IS V.

04

oa

<5

3"
1!

r-------------~V70-S-o~15~V~15

-1.6

-12

-08

-04

15-'03 rnA

+04

+08

'12

"6

VGS (VOLTS)

Figure 17. If Rs is not trimmed so that the load line passes through
the origin, a voltage will appear at the gate causing a reduction in dc
input impedance. The incremental input impedance will not

be affected.

This can be done by trimming RS, as shown dashed in Fig·
ure 17. The biasing then becomes the same as for cir·
cuit 100h).

·16

·12

-DB

-04

'04

VGS (VOLTS~

.oa

'"

"6

Figure 16. RS can be trimmed to provide zero offset at some point
between 670 ohms and 2.5K
(Figure 10g). The source load line

n

intercepts the VGS axis at VSS = VGG = -15 V. Note that this load
line is not perfectly flat. It has a slope of -1/50K. because the current source is not perfect; it has a finite impedance.

Circuit 10(h) is almost the same as 100g); the difference is
that resistor RI is replaced by a current source. Since an ideal
current source has infinite impedance, the bias curve of

Biasing for circuit 10(k) is identical to that for circuit 1O(e)
(Figure 14) except that feedback is added to raise the input
impedance .••

REFERENCES
(I)

(2)

Siliconix

Sherwin, J.S., "How, Why and Where to Use FETs,"
Electronic Design,. May 17, 1966, p. 94.
Sherwin, J.S., "Knowing the Cause Helps to Cure
Distortion in FET Amplifiers," Electronics, Dec.
12,1966, pp. 99·105.

7-19

ta

APPLICATIONS

H

Siliconix

Amplifier Charts

.c

......-.u

For convenience this chart offers the designer circuit values for a variety of commonly used J-FET amplifiers .

G)

a.

E

Voo

C

fR~-

Ro
~eo

I

1.1'-

"

---"1
R,

RS
~

-::'

*cs

__ ..JI

-::'

Amplifier Design Chart
(CS for 3 dB Point at 50 Hz)

voo
IVI

AS

1m

AI
IMS11

A2
IMS11

Cs

100

AO

eo Max

I"FI

(mAl

1m

IVI

AV

VOO
IVI

AS
Ikni

A,
R2
IMHI IMni

VOO'15
VSS'-15
VOO = 15

VSS' -15

560
27K

100
33

10

3K
75K

11

100

lK
lK

85

096

Follower

85

096

15

Follower

20

47

11

330

100
100

2K

47

11

VOD'" 15

4 7K

15

820

15

30

10

1M

45

510

1M

17

620

22

35

097

10

82

1M

120

36

06

22

50

02

35

18-24

20

82

1M

120

120

15

30

82

1M

120

180

15K

55

33

510

1M

11

097

VDD - -<.15
VSS' -15

Source
Follower

15

2N4118

So .. rcc

Follower

75
10

35

097

2N4119

12K

15

220

22K

35

lK

12

100

39K

lK

12

100

56K

20

56

30

56

38
35

40-55

25

13

098

15

13

098

70
5"F"

35

at5V

70

150
240

10
3

330

17
17-23

20

68

300

27

18

30

68

300

68

45

VDO "" +15

510

VSS" -15
"ACAmpltfier

7-20

Source
Follower

12

420

25

Source
Follower

AV

57
15

360

15K

20

75K

eo Max
IpKVI

120
270

27K

J113

47K

45

100

220

Vee· 15
VSS'-15

45

1M

8-11

19

10

30

RO
Ikni

100

330
VSS' -15

lK
820

330

1M

10

VOO '" +15
VSS' -15

330
30

10

097

J112

2K

10
20

25

Source

Source

75K

100
I"AI

2N4117

J111

30

Cs

Siliconix

Source
Follower

40

10

097

APPLICATIONS (Cont'd)

:I=-

H

Siliconix

3

--....---

"U

.,CD

n

:::r
a
:L
1ft

---I

R,

RS

~ Cs

,

~--...I

Amplifier Design Chart
Voo

RS

Rl

R2

Cs

(V)

1m

1m

1m

lpF) ImA) IKn)

100

RO

.0

Max

Ipk V)

AV

Voo

RS

Rl

R2

Cs

IV)

1m

1m

1m

IpFI ImAI IKm

2N433B
1500

t--2--

1M

30

15
5100

1M

36K

1M

1500

1M

5100

1M

2M

t--2-30

t--2--

30

36K

1M

1500

1M

5100

1M

36K

1M

Voo = +15 lOOK
VSS=-15

1M

45

o
25
30

25
5M

30

o

I-E-8 2M

36
25
9·12
0.25 f-":;43:;;67+-..;1;.;5:-+-..;1;;;6:.;.2~4
20
20-30
0.12 f--;88;;;22+--:3;:;.0;-+-,1c:;0..:.1.:;0.~5
1.5
24·37
0.15
27
1.0
13·18.5
82
40
21.5·27
0.25 f-::i:8",2+--;2;:-:.5;.-+-..:3",2-;-4::;-t9
100
3.0
43·64
150
4.5
14.5-16
0.12 t---:1;;5",0+--:2;:;.5;-+--:3",8-;-,5::;-!4
200
1.5
40-50
0.15
82
5.0
37·52

270

0.12

10

680
15

30

28·31

015

120

7.0

54·76

0

9.0

098

~ 042 1--;2:;;0+---;3;:;.0;-+--+,7.;:,7.~5

1M

9100

1M

6.8M

35

27K

1M

3M

25

~~

40
15

~:~

30

27K

1M

47
6.5
15·17
042
47
4.0
38·47
I--::SC:-l+-:4"'.S:--+--'4'"'0'"'.5C:-1
40
0
o
43
8.0
4.5
13M I - - 0 32 1--:4"'3+-:5"'.0:--+-""'4;-:0"'.4c:-1
3
35
68
4.5
53.60
68
40
49·52
75M 25
0.2 I-l-0:"'0+-:7'"'.0:--+--:6'"'6-:.7c:-1
0

1800

1M

t--- 042 1--=7""5+--=5-;.0:--+--:5"'8.-:7"""'0

1M

9100

1M

o

40
45

o

9100

1M

22M

r--25
~

27K
Voo = +15
VSS=-15

75K

1M
1M

12M

25

o

75

75

70
73.77
70
7.0
0.32 1-~6~8+--::6-:.5:--+--::5:::9.'::67-1
4
120
70
80.85
100
12
33
0.2 r.l-;;0~0+--;;5,.;0:--t;-;~6:=:5-~6~8
180
80
100·115

o

10

VOO-+15
VSS=-15

.0 Max
Ipk VI

AV

1200

1M

3900

1M

680

1M

1200

1M

3900

1M

20K

1M

680

1M

1200

1M

3900

1M

20K

2M

22K

1M

15

I-i~~.~rt-i~'i.~~+--;~1:i.~i;·~irl

65

6.8

2.0

9.10.5

r---265

12

60

9.5·10

39

7.0

7.5·8

r--!L-

I-~~~H---;~;'j:~~-t--;~~t:~!~~

40

04

r--L
60

~.~

~~:~~

11

39

20

39.42

075

o

12

0.96

o

~~

1

2N4341

15

23·25

100
68

022

45

~~:~~

9
0.32 1--;1",8+-:2",.0:--+--:1;-:7-:.1c:-1
30
25
26·28
22
1.0
16·18
0 2 1--::4~3+-;2;:;.0;-+--;2;;;8-:.3~0

~

1800

r--2-

1M

1--:2"'7"'0+--;5"'0:-+-7"'6"'.1"'0:::-1
5

2N4339
1800

RO

2N4340

~300 0.15 f-l;;2",0+-+.14:-+--;:-:.:;2::<-J8

o

100

30

45

0.98
VOO=+15
VSS=-15

Siliconix

1000

1M

70

1200

1.2M 7.5M

-SO

2000

1M

3.5

r.~~:~H~~rig~+-:3;::.!i-~~

r--!L70

2.7

~:~

~.~

80

3.5

9.1
3.9

15
40

41
11·13
7.5·8

50

0.7

18

30

16·21

~.~

6i~

22M

80

27
35

6.8

70

13

5.6M

50

0.7

30

9.0

28·35

o

1.9

o

135

094

1000

1M

1200

l.lM

2000

1M

15K

1M

33M

1000

1M

~

+0

1200

1M

2000

1M

15K

1M

10K

1M

15M

:g

g

7-21

-

H

Silicanix

Composite Op Amp
for High Performance

For op amp applications requmng the best possible
performance, consider a composite op amp that takes
advantage of differing process technologies. A JFET dual
can be combined with a Signetics NE5534 bipolar op amp
for outstanding performance. Input bias current can be
reduced, yet slew rate can be very high (20V / J.l.sec to
40V /Jlsec) and the circuit is unity·gain stable. Output
swing is a minimum of ±12V into a 600 ohm load when
operating from ±15V power supplies. This high output

capability combined with a JFET input stage makes this
an excellent amplifier for high·speed integrators, SAMPLE/
HOLD circuits, peak detectors, and log amplifiers.
The input portion of the circuit is shown in Figure I. The
NPN input stage of the NE5534 Ie op amp is biased into
cut-off by connecting both inverting and non-inverting
inputs to the negative rail. A JFET preamplifier input stage

High Performance Op Amp Using The Siliconix 2N5912

v+(O--------~I~---------------e-~i~~~~~~~~~_:17========N=E5=5=3=4='=====,

t

R

2.SV

Ce

RD
D

0.1BmA

+-

r---~

=:=
I

Re

___________-,~------------~~----~----~--~~--~-----J~-,
,

+-,~

-INo-.....+-...,

+IN o------------J~----------'

RD-1.37K

v-cr----------~----~------~

7-22

Re

B

Silicanix

is then connected into the PNP second stage of the NE5534
and the currents that formerly flowed through the NE5534
NPN input pair are now diverted into the JFET input pair.
Drain resistors RD effectively parallel the collector resistors
RC from within the IC op amps and the JFET drain
currents will then be the sum of the currents through RD
and Rc. The voltage across the parallel combination of RD
and RC is nominally 2.5V due to the internal biasing of the
NE5534. Going directly into the second stage of the IC op
amp ratherthan into the NE5534 NPN input stage has two
distinct advantages:
1. Frequency response is better in that the phase shift of

the bipolar input stage is avoided. A high-current JFET
input stage, such as the 2N5912 when operated in the
ImA to SmA drain current range, has excellent
frequency response in comparison to an NPN stage
operating in the 150MA to 200MA range.
2. The operating level at the JFET drains is only 2.5V
below the positive supply rail, therefore the commonmode input range for the JFET input stage can be
relatively high. The combination of low input bias
current with high frequency response is useful for
SAMPLE( HOLD circuits, high-speed integrators,
photo-multiplier tube amplifiers, and high-speed data
conversion circuits.
Although more expensive than a single monolithic op amp,
the combination of a JFET preamp with a bipolar IC
second stage can provide substantially better performance
than any monolithic alternatives.
A Siliconix 2N5912 JFET dual was chosen for the input
stage in this example because of its high operating current
range, high gain, and excellent frequency response. The
saturation drain current IDSS has a specified range of7mA
to 40mA, but is typically lOrnA to 24mA. Gate source
cutoff voltage VGS(off) is in the range of -I V to -5V with a
typical value of approximately -2V to -4V. The 2N5912
characterization curves indicate that any drain current
from ImA to 8mA will provide good performance, and
2mA was chosen for this application.
The current diverted from the bipolar input stage to the
JFET input stage is nominally 180MA on each side;
therefore a drain current on each side of 1.82mA is needed
from the drain resistors RD to make up a total drain
current of 2.0mA. The drain resistor R D therefore needs to
be approximately 2.5V(1.82mA, or 1370 ohms on each
side.
Gain of the JFET input stage can now be calculated. From
the 2N5912 characterization curves, forward transconductance gfs will be in the range of 2.6mmhos to 5mmhos for
units having IDSS of lOrnA to 24mA and when operated at
a drain current of 2mA. The differential gain can be
approximated by the product gfs RD. Using a center value
of 4.3mmhos and 1230 ohms, (RD and RC in parallel),
then the gain will be approximately 6.5, or I6dB. Total

amplifier gain was found to closely approximate the gain
curve for a 5534 being operated alone.
The cascode configuration using two input pairs as shown
has several advantages. Most importantly, the input gate
current is dramatically reduced due to the lower drain-togate voltage on the input pair. In the cascode configuration,
the gate-to-source voltage on the upper pair will be the
drain-to-source voltage of the input pair even with the
common-mode input variations. All of the common-mode
swing is taken up by variations in VDS of the upper pair.
Gate leakage of the input pair is primarily dependent on
drain-to-gate voltage VDG, which will be a constant
-2V GS in this cascode configuration. Drain-to-gate voltage
on the input pair will be low, typically in the 3V to 6V range,
which is well below the "IG breakpoint". From the
characterization curves on the 2N5912, gate current leakage
will be under 2pA for drain-to-gate voltages under 6V. The
cascode configuration is very effective in reducing input
bias current for JFET input stages. Another advantage of
the cascode configuration is a reduction of input capacitance.
The input pair drains are "bootstrapped"to the common source
point and both must follow the gate Voltage. The effective
capacitance from gate-to-drain and from gate-to-source is
reduced. In addition, output conductance is reduced by the
cascode configuration which also helps CM R. Adding the
second JFET pair significantly improves both input bias
current and common-mode rejection without degrading
other parameters.
The constant current source consisting of Q3 and Q4
primarily improves common-mode rejection and rejection
of power supply variation. It also establishes the nominal
operating voltage at the input (pins I and 8) of the 5534 op
amp. The current will be a constant VBE( RE independent
of fluctuations in power supply voltage or input voltage
level. This current source has very high impedance, therefore
common-mode inputs are heavily attenuated.
Common-mode-rejection-ratio (CMRR) is very high due
to the use of a constant current source, but can be further
improved by matching of drain resistance. The parallel
combination of RD and RC is the effective drain resistance
for this design. The transconductance ratio between the two
sides of the input pair also directly affects CMRR. The
drain resistors should be well-matched to minimize the
CMRR adjustment range since it also affects offset and
drift.
Each I % mismatch in drain resistance will cause approximately IIMV (OC of input offset voltage drift. CMRR can
be readily trimmed to over 100dB. CMRR vs. frequency is
excellent due to the use of the 2N5912, a wide-bandwidth
FET, in a casco de configuration.
A high performance op amp should also have good output
characteristics, low noise, and high slew rate. The NE5534
op amp is rated for ±14V mimimum output swing into a
600 ohm load when operating from ±15V power supplies.
Output resistance is typically 0.3 ohms. The Siliconix

Siliconix

7-23

--

2N5912 characterization curves show a typical equivalent
input noise voltage of only IOnV/y'fIzat 10Hz. There is
also a component of noise from the second stage, but its
effect is divided by the input stage gain and its contribution
is small. Input current noise of this composite op amp is
very low due to the typical operating level of I pA input bias
current. For slew rate, this circuit is capable of 50V / f.lsec
when going negative. Positive slew rate is 50V / f.lsec
without use of a compensation capacitor, but drops to
25V/ f.lsec with a 20pF compensation capacitor. Compensation capacitance will generally be needed only when driving
capacitive loads. Even the lower value of slew rate,

7-24

25V / f.lsec, corresponds to a full-power (±IOV) frequency
of 400KHz.

While the vast majority of op amp applications can be
satisfied through use of conventional I C op amps, there are
applications in high-performance instrumentation systems
that require superior performance. This composite op amp,
which makes use of precision dual JFET input pairs and a
high performance IC op amp, provides a unique combination of low input bias current, high CMR, low noise,
excellent frequency response, and high output swing.

Siliconix

H
Siliconix

Applications for
the Si1000 Series JFET Amplifier
Doyle L. Slack

INTRODUCTION
The Sillconlx SI 1000 sene; " much more than a JFET, It IS a
complete monolithic amplifier CirCUit featuring a low nOIse, low
leakage J FET and two parallel diode; from the gate of the device
to the substrate. An optional Internal source resistor may be
connected between source and substrate to proVide a complete
source follower amplifier In one ;mall package. This applicatIOn
note will discuss the operation of the SI 1000 senes and Its uses and
advantages. Also, several example applications CirCUits are meluded to show the SIIOOO senes' versatility as an Impedance
matchmg circuit and/ or small signal amplifier.

DEVICE OPERATION AND SPECIFICATIONS
The SIIOOO series NBA geometry comes m two versIOns' the
SIIOOO family and the SIIIOO The Si 1000 family (Si 1000, SIIOIO,
S(1020) mcorporates the features of two of our more popular
J FET products, producing a unique combination of low nOIse
and low leakage Two parallel dIOdes are connected between the
JFET gate and the substrate (which is tied to the fourth lead of the
package) These dIOdes clip transient spikes and overvoltages,

TO~~2
___ 0,

"<>-r

I

I

I

I

r------------,I
r---, I

I

5

L____ j

o

COMMON

TO~U!2---:,
I
I
I

I

S

I
I
L ____ ...J

~,
o

COMMO~

Si1100 Series

I

C

I

I

:L __ ~:

I
I

II
I

:

Si1000 Series

"<>-r-

protecting the output of the CirCUit from sudden voltage
fluctuation,.
The SI 1100 has the same features as the SI 1000 but also Ineludes
an internal resistor from source to substrate This resistor
completes the source follower circuit and sets the output
Impedance of the amplifier.
Figure I shows the two CirCUits and their connectIOns to the
leads of a TO-72 can. It also gives the pad layout and dimensions
of the SI 1000 and SI 1100 die for use m hybnd circuit applications.
The mternal source resistor m the SIlIOO supplies a complete
source follower amplifier circuit with a typical Rs range 000 to 60
Kohms. However, If a source resistor outside of this range IS
deSIred or a different type of amplifier that still provides input
overvoltage protectIOn is needed, the Si 1000 senes without the
source resistor should be used, since it allows more design
fleXibility. Table I shows some of the more Important typical
values for the Si 1000 series and SI 1100 deVICe, and Table 2 gives
the differences between the parts m each of the two families. A
transfer charactenstlc graph IS Ineluded in Figure 2to give an Idea
of the operating range of the SIIOOO senes.

COMMON

I

I

I

'.MILS

-

i---~
0

I
I

:

G

I
I

L ___ J

:

L __________

J_

I•

•

,. "'ILS

I

Figure 1. Schematic diagrams, lead connections, and die layout for the Si1000 series and Si1100 circuits.

Siliconix

7-25

Table 1. Typical values for discussed parameters of the Si1000 family and the Si1100.

snooo
PARAMETER

Family

SillOO

Oiode Leakage
JFET Leakage

<2pA
-...--I{--o

-

TO

8 ohm
LOAD

2.7n

Il00nF

Figure 4. Schematic diagram of an audio amplifier utilizing the Si1100 as a microphone preamplifier.

Siliconix

7-27

But what If an even lower load impedance such as 50 ohmns
from a transmISSIOn line is to be used? FIgure 5 shows how the
output impedance of the source follower CIrCUIt can be lowered

even more wIth the help of a bIpolar transistor. The reflected
resistance through the base of the bipolar is paralleled with the
effective output resistance of the Si 1000 cIrcuit to produce an
output resistance of less than 60 ohms and a voltage gam of better
than .95 V IV. This allows both the source and load to be optImally
matched with virtually no sIgnal loss.

+5VTO+10V

12K

I
I
I

2.7K

____ .1

Figure 5. Schematic diagram of the bipolar assisted low
output impedance source follower amplifier.

The bipolar assisted source follower gives great flexibIlIty by
allowing interface between any ultra hIgh Impedance source and a
50 ohm load with virtually no signal loss or noise insertion. Some
examples of ultra high impedance transducers are electret microphones, input preamplifIers for hearing aids, accelerometers for
military and industrial sensing, infrared sensors, and ion chambers
such as those used for industnal radiatIOn exposure monitors.
Another example of how the SIlIOO family could be used is
given in Figure 6. Here, the Si 1100 series circuit input IS
connected to a capacitive field sensor (as simple as a pIece of
double sided circuit board). Any induced voltage change on the
plates is fed to the input ofthe peak detector section of the op-amp
cIrcuit. The Schmitt trigger monitors the voltage across the
capacItor and changes its output state when the capacItor voltage
crossed the 2.5 Volt tngger pomt. The output from the Schmitt
trigger sWItches between 0 and 5 Volts and is microprocessor
compatible for sensor applications such as computer-controlled
mtruder alarms.

30K

+5V

I
I
I
I
IL _____ _

>"""--.;0 TTL

OUT

30K

10K

I

Figure 6. Schematic diagram of the Si1100 proximity sensor.

7-28

62K

Siliconix

Another transducer mterface problem occur; when hIgh Imped-

common source amplIfIer mode where low power or battery

ance mea~urement network\) are connected to operational

operatlOn.s Important F.gure 8 gIves a CIrcUlt that wIll operate In

amplIfIer; for dIfferentIal mea,urement ThIS ean be ,olved by the

the 10 to 20 mIcroamp range at a 12 Volt supply voltage. The

c.rcuit m F.gure 7 Here a paJr ofSIIOOO ,ene, parl> ha, been u,ed

dIode protection .s still available m thIS confIguratIOn. but the

to mOnItor a high Impedance bndge for an mstrumentallon

CIrcUlt voltage gam wIll be between 10 and 20, with extremely low

amplif.er. Thi, cIrcuit allow, precIsIOn mea,urement at low mput

power consumptIOn (approx.mately 250uW). Thb.s very deSIrable
for remote or battery operation where mmlmum maintenance I.!o.

s.gnal level; and easy 7eromg of the amplifIer output

.mportant

However. don't thmk that the SIIOOO fam.ly has to be used Just
a, a ,ource follower. Another me of the SIIOOO ver;lOn IS

In

the

+12V

390K

100nF

o-II---*--i--+---+I

lOOK IloollF

Figure 7. Schematic diagram of the low signal SilDDD high impedance instrumentation amplifier.

+6V
+6V

r------

I

S.1100

lOOK

1M

+12V

+6V

-12V

-

100K

I
I
I
I
I

1M

L _____ _

Figure 8. Schematic diagram of the SilDDD series low power common source amplifier.

Siliconix

7-29

CONCLUSION
With Its low noise and low leakage combmatlOn, the SilOOO

be converted to any sUItable amplifIer desIgn and still provIde

senes amplifIer IS an ideal circUIt for Impedance matchmg. The
SIIIOO senes CIrcUIts are dedIcated for use as source follower

dIOde protectIon. There are many good reasons to include these

amplIfIers. Although the SIIOOO senes has also been desIgned for
source follower applIcatIOns, it is flexIble enough that It may easIly

7-30

devIces In your desIgns, such as small SIZe, outstandmg performance, and reasonable cost. These advantages make the SIIOOO
senes preferable for numerous small sIgnal applicatIOns.

.H

Siliconix

FETs for Video Amplifiers

INTRODUCTION
The field·effect transistor lends itself well to video amplifier
applications. Gain bandwidth products in excess of 250 MHz
may be easily achieved using simple one or two transistor
circuits. DC input resistances in the tens of megohms range
may also be easily achieved while input capacitances may be
significantly reduced to less than I pF by well known circuit
techniques. Video amplifiers have applications in communi·
cations and pulse amplifying circuits and normally operate
up to lOa MHz.

For this analysis the gate source leakage resistance has been
ignored due to its high value. Redrawing the input equivalent
circuit as a simple parallel RC combination results in

Behavior of FET Input Resistance

Figure 2

A prime FET parameter, input impedance, has a large effect
in determining the frequency response of a FET video am·
plifier. It is not a simple RC network but one in which the
real and imaginary parts are a function of frequency.
The voltage generator source resistance Rg and the FET
input impedance Zin form a frequency sensitive attenua·
tion network. The larger the Rg, the worse will be the fre·
quency response, and vice versa. Examining this in greater
detail, consider the input equivalent circuit of a FET con·
nected in the common source configuration,
where

where
GI = Re IYin I
= w 2 [TICI (l + w 2T22) + T2C2 (l + w 2 TI2)]
1- (w 2TIT2)2 + w 2 (T1 2 + T22)

(1)

and
BI =Im 1Yinl

Rgs and Rgd = bulk series gate resistance
Cgs and Cgd = bulk series gate capacitance
Goss
= output conductance

..~

(2)

where

C,d

A,d

G

= w[CI (I + w 2T22) + C2 (I + w 2TI2)]

D

A"

C"

~
Figure 1

$

T) =CgdRgd
90s$

T2 = CgsRgs

(3)

The input resistance varies inversely with the square of the
frequency (see Figures 3 and 4) while the input reactance is
inversely proportional to the frequency (see Figure 3).

Siliconix

7-31

-

In common-source circuits, ltG, will typically fall to < 2K
ohms at 100 MHz while C, remains substantially constant at
'east up to 1000 MHz. Figures 3 and 4 below exhibit these
relationships_

+15V

-rRo
5600

100~WI

Figure 5

/'

/'

The 3-dB frequency w3 is given by:

-j'Sljg'li+;blssl

o ~O~O'-£_----'--:J=OO,---J---'--:6:::00:-'-'-'::'OOO

(7)

FREQUENCY {MHz}

Figure 3

-+15V

(8)

7 x 10- 12 X 560
W3 = 255

X

106

(9)

l000n

j-~oo
o-,-.-~.
--h
••
100KO

y

¥1%2N5911/121

910

(10)

The low frequency voltage gain for this configuration is
given by:
A _ gfsRD
Y - 1 + gfsRS

O'---L-LLW~~-'-~L-U~
,
10
100
FREQUENCV (MHz)

(BI

(AI

f3 =39MHz

Ay

Figure 4

(11)

= 4.9

(12)

To maintain low input capacitance, and thus a high input
impedance over a wide frequency range, feedback may be
applied to most circuits. Such techniques are explored in
"FET and Bipolar Cascade" section (page 5). The effect of
Rg on the frequency response is shown in Figures 6, 9, 11,
13 where various amplifier configurations are investigated_

where

Circuits tc Con~dcr

Measured Performance

Five video amplifier circuits are considered_ They are:

Figure 6 shows the frequency response of the circuit. The
low-frequency gain was measured at 4.5 and the 3-dB bandwidth at 44 MHz giving a gain bandwidth product of
197 MHz_ This compares with a calculated gain bandwidth
of 191 MHz.

Common-Source Configuration
Shunt-Peaked Common-Source Configuration
Source Follower
Cascode Amplifier
FET and Bipolar Cascade

gfs = 15 mrnho when ID = 12 mA, the quiescent current
RD=560n

(13)

RS=47 n

(14)

14

....,."T1111II1IIII11"'CTTrmr-rTmI""--jTU"'Urmrn

Common-Source Circuit 1

1I1 ......
12 H-t+tttt
11I111Itt-'Iod-tttiiP'oHttHtll-ttffi1ltl

The circuit of Figure 5 features high input impedance and
high voltage gain_ The drain resistor is set at 560 ohms to
maintain good bandwidth which, with 50-ohm generator
impedance, is determined primarily by the drain load components. These are:

10

R n =560n
(4)
CT =Cgd +Cn+Cs
(5)
Cgd = 2.0 pF, CD the YTVM probe, 2.0 pF, and Cs is
circuit stray capacitance of 3 pF.
CT = 2 + 2+ 3 = 7 pF
(6)

7-32

Siliconix

1I ~!IU1

r-

11~~l5!!.1

10

100

FREQUENCV (MHz)

Figure 6

1000

Effect of Increasing Generator Impedance
If the generator resistance Rg is increased to 1K ohm, the
input time constant of the FET is increased. The bandwidth
of the amplifier is now determined primarily by the input
time constant which consists of generator impedance
(Rg = lK ohm) shunted by Cin (see Figure 7).

The response of an input signal of frequency fo will then be
boosted to an extent depending on the loaded Q of the
tuned circuit; the loaded Q in turn is dependent on the
unloaded Q of inductor L, Rg and the FET input resistance.
Next consider shunt peaking in the drain circuit. In Figure
8 the inductor L is set to such a value that a low Q tuned
circuit is formed; the resonating capacitance C is the parallel
combination of Cgd plus stray and load capacitances. For a
flat response, the LC circuit is tuned to the 3-dB frequency
of the resistance loaded circuit of Figure 5. (See Appendix.)
+1SV

Figure 7

where

= (5.9 x 3.5) + (0.6 x 10) + 3.

Cin = 30 pF

(15)
(16)

Figure 8

The required value of Lis:

where

T'
R 2C

Cgd = 3.5 pF

(I 7)

Cgs = 10 pF

(18)

The corresponding 3-d8 frequency is given by:
(19)
109
30 x 10- 12 x 10 3
f3

(20)

30

=5.3 MHz

=

and for the circuit in Figure 8.

(24)
(25)

= 0.78J.LH

where

1

w3=--CinRg

L

(21)

which agrees closely with the measured bandwidth as shown
in Figure 6.

RD= 560.11

(26)

C

= Cgd + CStray + CVTVM PROBE

(27)

C

= 1.2 + 1.3 + 2.5 = 5 pF

(28)

Due to the low circuit Q (about 5), the value of L is
not critical.
The 3-dB bandwidth shown in Figure 9 now extends to
67 MHz giving a gain bandwidth product of:

Shunt-Peaked Common-Source Circuit
The frequency response of the resistance-loaded commonsource circuit may be significantly extended by shunt peaking at the gate and/or drain. Consider first the gate circuit.
Here an inductor may be connected in shunt with the gate
and set to such a value that it forms a tuned circuit with the
FET input capacitance. The frequency of resonance is
determined by:
fo=-----

(29)

67 x 4.2 = 281 MHz

-

(22)

21r-JLC;;;
where
FREOUENCY (MHz)

(23)

Siliconix

Figure 9

7-33

When RS is bypassed by a 0.1 capacitor, the low frequency
voltage gain is given simply by:

which is near the measured value of 0.94. Measured perfor.
mance is shown in Figure 11. The output resistance of this
source follower is given by:

(30)

AV=gfsRD
= 15 x 10- 3 x 560

(31)

=8.4 (18.5 dB)

(32)

The gain bandwidth product tends to remain constant
whether RS is bypassed or not and this effect is shown in
Figure 9.

I
1
Ro = gfs = 5 x 10-3

{34)

= 200 n

and in this circuit, Ro was measured at 165 ohms. The
source follower is a useful versatile circuit which may be
used as an impedance converter, level shifter, buffer stage,
or as an input circuit to an op amp or feedback amplifier.
1

Source-Follower Circuit 2

1111 I

A 1300 is used in the FET source·follower circuit, Figure
10, because of its low input capacitance and high gfs which
remains high at the frequency range of interest. A source
follower exhibits a high input impedance and low output
impedance. The real part of the output impedance is the
reciprocal of gfs which is independent of frequency up to
about 600MHz. The input capacitance isC gd + C gs (1 - Ay)
which, in this case, is approximately 1.5 pF maximum. The
input capacitance is also independent of frequency and
independent of load when the load is larger than the output
resistance Ro.

-1

IR~= lK

:!!

g
Z.

-2

w

~

-3

,g

-4

3 dB FREQUENCY

Ag= lKU
3 dB FREQUENCY

-6
01

Rg =50U

10

100

1000

FREQUENCY (MHd

Figure 11

Cascode Circuit

+12V

The cascode circuit has applications as a buffer amplifier for
use with high stability oscillators or in low level power amplifiers2 mainly due to its low reverse transfer characteristics. The advantages and considerations of this configuration, Figure 12, are similar to those listed for the common·
source circuit. An extra advantage exists in the cascode
circuit, namely the low input capacitance:

I

=:OOT
-12V

CD

11111

--= IV,HJ

25PF

-:!::-

Figure 10

The frequency response is dependent mainly on the gener·
ator internal impedance. For example, when Rg is increased
to lK ohm the bandv:idth fall:; to 80 ~,lHz. In this partkulai
circuit, the low·frequency voltage gain is 0.94.

Cin = Cgs + (1 - AV) Cdg

(35)

Cin = Ciss + Cgd

(36)

+15V
1KG

The input resistance is proportional to 1/[2 as explained in
the section, "Behavior of Input Resistance," and at some
high frequency will go negative, particularly if the source
resistor is large. For example, with the circuit in Figure 10,
the input resistance is high at 10 MHz but in the negative
resistance region at 100 MHz. However, when RS is 1000
ohms, the input resistance is real at this frequency.
The voltage gain of a source follower is given by:
Figure 12

(33)

Thus Ay is almost independent of RS when RS is large.
Using typical values for the 1300 (or 'h 2N5912) in Figure
10, the drain current is 3 rnA, gfs is 5 mmho and RS 4700
ohms,
AV=0.96

7-34

where AV is the voltage gain from Q, gate to Q, drain
which is essentially unity. Ciss for the U257 dual FET is
5 pF and Cdg is I pF, therefore
Cin = 5 + 1 = 6 pF, excluding strays of 4 pF
Thus Miller effect is minimized and a good gain bandwidth
product is achieved.

Siliconix

Figure 13 shows cascode frequency response. The voltage
gain at low frequency is 15 dB (x 5.6) and the bandwidth is
24.5 MHz with a generator impedance of 50 ohms. Gain
bandwidth product is 137 MHz.

The frequency response of this circuit is controlled by the
output time constant if ft of the transistor is much greater
than the amplifier bandwidth. In the circuit shown the a-c
load is 2.5 pF.

28 r-TTTTnmr-rTTlrrmr-rrrmm
24

This produces an a-c voltage at the emitter whose amplitude
is almost equal to that at the base. Thus at the FET,
Vg ~ Vs ~ vd and all three signals are in phase. In this way
Miller effect capacitance is largely eliminated.

b-HtttfIH--t-ttlH+ttt-t-ttttlttl

CONCLUSION
The input resistance of a FET is inversely proportional to
the frequency squared, while the input capacitance remains
constant to at least 1000 MHz.
100
FREQUENCY (MHz)

Figure 13

FET and Bipolar Cascade
The FET and bipolar transistor combination of Figure 14
makes a good video amplifier because the FET input provides
the voltage gain thus obtaining a superior gain bandwidth
product. The feedback capacitor a-c couples the emitter to
the drain. The a-c voltage at the gate is nearly equal to that
at the source. This source voltage is doc coupled to the base.

Several video amplifier configurations are considered. The
common-source circuit is considered first: in the example,
the low frequency gain is 4.5 and the 30-dB bandwidth
44 MHz (gain bandwidth 197 MHz). By shunt peaking in the
drain circuit, gain bandwidth is increased to 260 MHz. The
simple source-follower circuit gives a gain near unity with
GBW almost 300 MHz and an output resistance of I/gfs' The
cascode circuit features a low input capacitance and GBW
of 137 MHz. The circuit featuring the best gain bandwidth
is the FET and bipolar combination. A gain of II dB and
bandwidth of 90 MHz is achieved.

12
0

L.Ut
.......

l.'d'

BOONTON

91CVTVM

6

62Kn

2200

27Kn

001

0

10

100

FREQUENCY!MHz)

-12V

Figure 14

Figure 15

Ell

Silicanix

7-35

APPENDIX
Selection of Video Amplifier Designs with
Perfonnance Summary
Note. All output voltages measured with Boonton 91C VTVM.
Common Source Stage
+15V

RO

Device

Rg

n

RS
RS RD
Gain dB
Bypassed n n

cin

BW

GBW

pF

MHz

MHz

44
40
5.0
3.5

197
300

2N4393 50
50

x

47560
47560

lK
lK

x

47560
47560

4.5
7.5
4.5
7.5

911K
-91 lK
911K
91 lK

3.8 11.6
6.3 16.0
3.8 11.6
6.3 16.0

11.0
14.5
11.0
14.5

27.5
30.0
9.5
6.5

103
189
36
41

1201.5K
1201.5K
1201.5K
1201.5K

3.9 11.8
6.2 15.8
3.9 11.8
6.2 15.8

11.5
13
11.5
13

25
19
8
7

98
118
31
44

J300

50

Y,

50
2N5912 lK

x

lK

x

2N4416 50
50
lK
lK

x
x

13.0
17.5
13.0
17.5

22
26

Common-Source Circuit

Cascode

+lSV
+15V

10Kn

lKn

":"

-15V

Rg

n

50
50
lK
lK

7-36

RS
Gain dB
Bypassed

x
x

2.7
5.6
2.7
5.6

8.5
15
8.5
15

Cin

BW

GBW

pF

MHz

MHz

n

9
11.5
9
11.5

27
27
9.5
9.0

73
151
73
51

50
lK
50
lK

Rg

Siliconix

L
~

0
0

8
15

Gain

dB

3.5
3.5
3.5
3.5

11
11
11
11

Cin

BW

GBW

pF

MHz

MHz

2
2
2
2

20
11
37
17

70
38.5
130
60

Shunt-Peaked Common-Source Stage
2N4393

J300
(V,2N5911/12)

+15V

+15V

":"

Rg

n

RS
Bypassed

Gain

dB

4.2
7.5
4.2
7.5

12.5
17.5
12.5
17.5

BW

GBW

MHz

MHz

66
54
6.0
3.5

277
405
25
26

Rg

50
50

x

lK
lK

x

RS

n

Bypassed

50
50

x

Gain

dB

3.9
6.3

11.8
16.0

BW

GBW

MHz

MHz

67
67

262
421

2N4416
+15V

":"

L

n

RS

J.tH

Bypassed

50
50
50

4
4

Rg

x
x

5

Gain

dB

3.9
6.2
6.2

11.8
15.8
15.8

BW

GBW

MHz

MHz

45
40
45

175
248
279

Common-Drain Common-Emitter Stage

I

lROn
":"

Rg

n

RE
Bypassed Gain
(O.IIlFl

dB

Cin

BW

GBW

pF

MHz

MHz

2.0
2.0
2.0
2.0

39
21
13
11

117
525
39
275

Rg

50
50

x

lK
lK

x

3
25
3
25

9.5
28
9.5
28

Siliconix

n

50

lK

25 F
•

Gain dB

Cin
pF

BW

GBW

MHz

MHz

15
15

1.0
1.0

32
15

5.6
5.6

179
84

7-37

Source-Follower Circuit
+15V

+15V

Dual
FET
Rg

n

Gain

50
1K

0.92
0.92

C in
Stray pF Total pF

Ro

BW

GBW

n

MHz

MHz

350
55

326
50

2.2

2.7

165

2.2

2.7

165

where
R t = Rgs
R2=Rgd
=jw

CI = Cgs

(1)

C2 = Cgd

(2)

,n
T

CI

C2

T

(Input to Output! mV

Gain

BW

GBW

MHz

MHz

U257 50
2N5912 1K

100

0.98

70

69

100

0.98

15

14.7

U232 50

10

0.98

85

83

1K

10

0.98

13

12.7

Note. Ro - output resistance of the source follower.

Derivation of Input Admittance Terms

Offset (Max)

Rg

n

The response below shows the "normal" 3·dB frequency
without peaking - fl' It is now required to raise the response
at f 1 by 3 dB to achieve a maximally flat response. Therefore, under these conditions the total impedance seen by
the drain at f 1 must equal the impedance seen by the drain
at fo ' Also at f 1, Xc = RV Substituting for Xc in Equation 5:

o>--_-----'f
(3)
- W 2CI C2

(Rt + Rz) + s(CI + C2)

fO
FREQUENCY

(4)

(1- w2RIR2CIC2) + s(CIRI + C2R2)

RL2+w 2L2
RL2 =(

,1-~L

Derlvnticn of Shunt Peaki.ig forniula
The equivalent circuit of the drain load is shown in the Figure below. The total impedance seen by the drain is given by:

+1
(7)

RL 2= 2wLRL

(8)

RL =2wL

(9)

RL
41T fl

(10)

L

~RL

(6)
)

RL2- 2wLRL + w 2L2 + RL 2 = RL 2 + w 2 L2

(5)

n

L 2

and
ro
-"

fl

21TRLC

RL2C
,:.L=-2--

(11)

REFERENCES
1. Sherwin, I.S., "Liberate Your FET Amplifier," Electronic Design, May 1970.
2. Siliconix Application Tip, "FET Cascode Circuits Reduce
Feedback Capacitance," August 1970.

7-38

Silicanix

H

Siliconix

Audio-Frequency Noise Characteristics
of Junction FETs
Bruce Watson

INTRODUCTION
The purpose of this application note is to identify and
characterize audio frequency noise in junction field-effect
transistors_ Emphasis is placed on basic device characteristics rather than on end applications, since it is important for the circuit designer to know the salient noise
behavior of the FET, and how those characteristics may be
specified by production-oriented test parameters_

~ctor,

a source resistor RG, with a thermal noise voltage
eT, is added to the circuit.

A noise factor (F) may be defined as
F=

Total available output noise power
Noise power at output due to thermal noise of RG
or

Defming FET Noise Figure
For analysis, it is convenient to represent noise in a FET
by assuming that an ideal noise-free device has two external
noise sources, eN and I N- These noise sources are chosen
to have the same output as would an actual noisy FET. An
equivalent circuit is shown in Figure I.

F=

Noise power output due to RG + noise power output due to FET
Noise power output due to RG
or

F =1 + Noise power output due to FET
Noise power output due to RG
or
Gain X noise power of FET referred to input
F=l+
Gain X noise power due to RG

NOISE-FREE FET

r- l

'N

RG

~ 'T

11

L~ J

I

or
RL

'N

Noise power of FET referred to input
F=I+
Noise power due to RG

The thermal noise voltage across RG is(l)

(1)
Representing Noise in an Ideal FET
Figure 1

where k = 1.380 x 10-23 JoulestK (Boltzmann's Constant),
T = temperature in oK, and B = bandwidth in Hz_ Therefore
noise power due to RG is

A noise factor (F) is a Figure of Merit of a device with
respect to the resistance of a generator. To calculate a noise

Siliconix

(2)

7-39

1&1

The noise power of the FET referred to the inpu t is

(3)

where RN ~ 0.67/gfs' the equivalent
resistance for noise. The eN, except in the llf n region,
closely approximates the equivalent thermal noise voltage
of the channel resistance.
In the so·called

Ilfn region, eN is expressed as

When expressions for the noise power of both the FET and
RG are substituted, the noise factor becomes
eN 2 +TN 2RG2
_
F-I + 4kTRGB

(8)

(4)

where n varies between I and 2
and is device· and lot·oriented.

A noise figure (NF) expressed in dB indicates the presence
of added noise power from the FET or another active
device. The noise figure is always given with reference to a
standard, specifically the generator resistance RG:

The characteristic bulge in eN in the Ilf n region has been
observed to some extent in all junction FETs submitted to
test. The breakpoint or corner frequency shown as f I in
Figure 2 is lot- and device design-oriented, and varies from
about 100 Hz to I kHz.

(5)

NF = 10 log 10 [F]
The noise figure of the FET is

(6)
When junction FET noise is expressed in terms of the noise
figure (NF), an inherent disadvantage arises in that the
noise figure value is dependent upon the value of the generator resistance, RG' Therefore, the eN, TN method remains as the best way to quantitatively express the noise
characteristics of the FET itself.
Describing Junction FET Noise Characteristics

As indicated in Equations (7) and (8), eN is inversely pro·
portional to the square root of the transconductance of the
FET (eN 0: l/ViiJ. eN can be lowered by a factor of
llYN if N devices with matched electrical characteristics
are connected parallel. For example, when

N = 2

(9)

let
(10)
and let

Junction FET eN and TN characteristics are frequencydependent within the audio noise spectrum, and take a form
as shown in Figure 2.

(1 I)

Thus,

1--.

OR FLICKER
EXCESS NOISE
REGION

II

0

~

JOHNSON OR
NYQUIST THERMAL
NOISERECION

GENERATOR
RECOMBINA
OR SHOT NOISE

"ON

REGION

From Equation (7)

,

UllJJ
BREAK

eNI

POINTS

'N

SLOPES

Ii

0

,

'0

(12)

,

E",n
t-

f'llill JJ
lDO

'K

'N

= v'4kT(0.67/gfsl)B

(13)

,
and

'2

(14)

II

10K

f - FREQUENCY {Hz)

Thus,
Characteristics of Junction FET Noise
Figure 2

(IS)

eN, the equivalent short circuit input noise voltage (with
the exception of the llf n region), is defined as(2)

(7)

7-40

A second way to achieve low eN is to use a device with a
large gate area. Empirically, eN is inversely proportional to
the square of the gate area (eN 0: I/AG 2), independent of
gfs' This large gate area philosophy has been followed in the

Siliconix

design of the Siliconix 2N4867 A FET, and noise performance of the device is discussed later in this Application
Note_ A major advantage of this type of design is that eN is
significantly lowered andlN also remains at a low value_

1--:;,-;;--------1
I
15Ku

I
I

15K II

The equivalent open-circuit input noise current, TN' with the
exception of the shot noise region shown in Figure 2, is due
to thermally-generated reverse current in the gate channel
junction_ It is defined as

I
I

I

10K 11

(16)
where q = 1.602 x 10-19
coulomb (the magnitude of the electron charge), IG is the
measured DC operating gate current in amperes, and B is
bandwidth in Hz. The expression is accurate only when the
measured gate current is the result of bulk device conductance. It is possible for the measured gate current to be due
to conductance stemming from contamination across the
leads of the semiconductor package.
At higher frequencies, as in the shot noise region shown in
Figure 2, TN can be approximated as being equal to the
Nyquist then' 11 noise current generated by a resistor: (3)

-=-I-=-

I
I

L __ -~ _

SH~~~;:~~~~~~~~SRE

I

~S~O:::E~~SJ

Test Circuit to Measure Popcorn Noise
Figure 3

The graph in Figure 4 shows "moderate" burst noise observed in a group of junction FET differential amplifiers
which were measured in the test circuit.

(17)
x

_13D~I~

where Rp is the real part of the
gate-to-source input impedance. The breakpoint or corner
frequency f2 in Figure 2 is lot- and device design-oriented
and can vary from 5 kHz to 50 kHz.
Another form of noise found in junction FETs is known as
"popcorn" or burst noise; the term popcorn noise was originated in the hearing aid industry because of noise or level
shifts which are present in input stages, and which resemble
the sound of corn popping.
Popcorn noise is a form of random burst input noise current which remains at the same amplitude, and which is confmed to frequencies of 10Hz or lower. The suitability of a
FET device is dependent on the amplitude of the burst, its
duration, and its repetition rate. The origins of popcorn
noise are not completely identified, but are believed to be
caused by intermittent contact in aluminum-silicon interfaces and by contamination in the oxidation processes.
A test circuit to measure popcorn noise in differential
junction FET amplifiers is shown in Figure 3. In practice,
popcorn noise is evaluated on an engineering basis, and not
on a production-line basis. No correlation between llf n
noise at 10Hz and popcorn noise has yet been found in
junction FETs_ However, if the amplitude of the burst is
large and occurs frequently, then I/f n noise voltage (eN)
is masked and difficult to evaluate at 10Hz.

I

1.

YLOTTlR TJE

D4,V '
NOlsIEBURST

I--

REFE~REO +0 INPJT

!

f-#1

NOIS~
BURT-

-

STABLE
DC Ul.VGs'llTi
DRIFTONLY-

#2

#3

TA - 25°C

:]""'N

--

,..

NOISE BURSTS

"

~NOISEI

BURSTS

and l/fl

eN

-

-

Popcorn Noise in Differential Amplifiers
Figure 4

Operating Point Considerations
Unlike bipolar transistors, where eN and TN characteristics
vary directly with change in collector current (IC), similar
characteristics in junction FETs will vary only slightly as
drain current (I D) is varied. This is true so long as the FET
is biased so that the drain-source voltage is greater than the
pinch-off voltage (VDS > Vp or VGS(off»The eN in junction FETs will be lowest when the devices
are operated at VGS = 0 (I D = I DSS), where transconductance (gfs) is at its highest value. This will be true only if
device dissipation is maintained very low in relation to the
total dissipation capability of the FET.

Silicanix

7-41

__

The curves in Figure 5 illustrate changes in eN as the operating drain current (I D) is varied. Note that the lowest eN
did not occur at VGS = 0, because of high power dissipation and a resultant rise in junction temperature at the
operating point.
~

-'0

2N3B22
(NRL GEOMETRY)

~ =TA'" 25"C

~HIGHI.ITYPE

1 -10
>-

iii
~
~

i3
~

lK

-01
10 "BREAKPOIN~

~

I

g-OOl

E=
-001

=-

~

L
O"'lmA

'0

.....-r

too

10

15

100p.A_

20

25

3D

VOG - DRAIN-GATE VOLTAGE (VOL lSI

Gate Operating Current vs

Drain~Gate

Voltage

Figure 7
,~~~~~~~~~WW

10

100

lK

-100

10K

1- FREQUENCY (Hz)

Ci'
.s

eN Changes vs 10 Variations

-10

~ -'0

Figure 5

(NZ~~~g~~~RYI ~

~TA-25·C

HIGH gm/C lis TYPE
'rnA

IG@IO

E1G@lo=smA

~
~

ilw

The optimum (lowest) iN in depletion-mode junction FETs
should occur at VGS = 0 QD = I DSS). In practice, very
little change will be seen in iN when the operating point is
changed, provided that the drain-gate voltage is maintained
below the gate current (IG) breakpoint and power dissipation is kept at a low level. The curves in Figure 6 illustrate
TN characteristics as a function of drain-gate voltage at
points below, on, and above the IG breakpoint voltage.

~

-01 IG "BREAKPOINr'

• -.0
!;

,

-00

,

'ass

'0

'5

20

25

VOG - DRAIN·GATE VOLTAGE {VOL TSI

Gate Currents vs Drain-Gate Voltage

Figure 8

Characteristics of eN andTN at Low Temperature
Three equations presented earlier ( (7), (16) and (17) )
show that eN andiN are temperature dependent. eN andiN
are proportional to .,ff, and both will be reduced if the
temperature is lowered. In Equation (16), TN is proportional to .jI(}; IG will halve for each temperature drop of
10 to UOC. eN is also proportional to v'RN, where RN ~
0.67 igfs. Thus when gfs IS mcreased, which is typical of
junction FETs operating at low temperature, eN will
also lower.

w!..u.......-..JI.WJL-.L.J.I.llWJL.....I...L..U.UW 10- 16
lOOK
'OK
'00
'0

'K

f - FREQUENCY (Hz)

In Figure 9, gfs has been plotted vs temperature for a silicon junction FET, and the low temperature limitation
caused by a dropoff in gfs is clearly shown.

iN Characteristics as Function of Drain-Gate Voltage
Figure 6

In circuit design, particular attention must be paid to draingate voltage (VDG) to minimize gate current (IG) under
operating conditions. The critical drain-gate voltage (IG
breakpoint voltage) can be anywhere from 8 to 40 V,
depending on device design. (4) Gate operating current (IG)
should not be considered equal to gate reverse current
(IGSS) in linear amplifier applications. IGSS is only an indication of reverse-biased junction leakage under non-operating conditions. The Curves in Figures 7 and 8 show how
IG breakpoint is related to basic device design. Device
designs with a high gfs/Ciss ratio have low breakpoint voltages, typically at VDG = 10 V, whereas high /.I. devices
(1.1. =fds . gfg). have much higher IG breakpoints, typically
VDG =20- 30V.

7-42

SilicDnix

1E

8000

-'
w
u

z

;!

g
e
z
e

.~

500.
4000

2N4416

lo-3mA

r

/

1'-

SLOPE05VC~ r-

"

~

l-

e

~

~

2000

~

~

•

i

100

200

T - TEMPERATURE (OK)

gfs vs Temperature
Figure 9

300

In connection with the plot of gfs vs temperature, note
that the relationship can vary from approximately 0.2% to
I % per degree C. The gfs slope depends upon the basic de·
sign of the FET, and upon the proximity of the drain current operating point to I DZ , the zero temperature coefficient point.
The major application for junction FETs at low temperature is in charge-sensitive amplifiers. (5) For best performance
in this type of application, a high gfs/Ciss ratio is required.
Recommended Siliconix FET types for such applications are the 2N4416 (NH geometry) and the U311
(NZA geometry).
Test Measurements
By definition, eN and iN are referred to the input of the
device under test. To measure eN, the test circuit shown in
Figure 10 will prove useful.

An alternate method of performing the above test is to use
a Quan-Tech Transistor Noise Analyzer consisting of a
Model 2173 Control Unit and a Model 2181 Filter. The
analyzer has provision for measuring eN and determining
NF with various values of RG in FET and bipolar devices
with selectable test conditions. The measuring system has a
constant gain of 10,000. The analyzer records output noise
at selected frequencies between 10Hz and 100 kHz in the
device under test, with the scale shown as the actual output
divided by 10,000. This is then the output noise referred to
the input. The equivalent bandwidth for testing is I Hz.
There are certain instances where the test circuit or the
Transistor Noise Analyzer are not adequate to measure eN
at certain frequencies oyer certain bandwidths in the I/f n
region. The rms noise over a bandwidth from flow to f high ,
where there is a I/f n characteristic over the entire range,
can be computed as

+VOD

eN = [eN knownj.[f
. In
known

0

1MH

J

csc lOOn

1

V,N

I

(~)jl/2n
flow

(18)

Figure 11 represents this equation graphically. For example,
eN known = 70 x 10'9 v/.,jHi at 10 Hz. How much noise is
in the band from 4.5 to 5.5 Hz? The noise has a Ilfl characteristic over the entire range. Thus

OUT

0)

MOUNT 0 U T AND INPUT CIRCUITRY
IN SHIELDED ENCLOSURE

or

Test Circuit to Measure eN
Figure 10

(20)

.!he following procedure should be used to make the
eN test:

4.975 Hz is the mean center frequency where f mean =
(flow' fhigh)1/2.

1. Set tunable fIlter to required flow and fhigh . Adjust oscillator to mean center frequency (fmean =
[flow' fhighll/2).
2. Set Vosc to 100 mV with Switch I in positioneD
I 102
ComputeVinl = 10' x - = 10'5V= IOIlV.
10 6
.
Vout!
3. Measure Voutl ' Compute overall gam as Ay = - V ; =
ml

-

'NKNOWN

4. Set Switch I to position@and measure Vout2 '
Compute Vin2 , the equivalent short-circuit input

I 'known

noise voltage (eN), using Ay from Step 3. Vin 2
Vout2 -

~ = eN
y

.
.
m volts over bandWIdth flow to fhigh .

Siliconix

Computing rms Noise Over a Bandwidth
Figure 11

7-43

TN measurements are difficult to implement at best. At frequencies below f2 in Figure 2,TN is assumed to have a constant level or "white" noise characteristic which may be
correlated to gate current, I G. From Equation (16) IG is
established as the measured bulk gate current. Because
measured gate current (IG) is the result of all conductan~s
at the gate, the resultant gate current and the computed iN
due to bulk material can be assumed to be this value or less.
The total equivalent input noise of the FET can be approximated by(6)
(21)
where eT 2 is the thermal noise of
the generator resistance RG and eni 2 is the total noise
referred to the input. This approximation assumes that the
equivalent noise voltage and the current generators vary
independently. Equation (21) implies that TN 2 can be calculated ifeN 2, eT 2 and total noise e ni2 are known. The
difficulty here is that in MOS or junction FETs, the RG
must be very large to detect the anticipated small value of
TN' However, when RG is very large eT 2 is much greater
than TN 2 . RG 2_ For example, over a 1 Hz bandwidth at
25"C, ifRG is equal to 100 Mn, then
eT 2 = 4kTRG = 4 x 1.38 x 10-23 x 2.95 x 102 x 108 =
1.63 x 10-12

V/YHz.

(22)

or
(27)
When a 10 pF mica capacitor was used in the evaluation
circuit (up to a frequency of 100 Hz) a correlation offrom
80 to 90% was obtained when compared to TN 2 computed
from measured gate current readings.
At frequencies above 100 Hz direct computation ofTN via
the capacitor method becomes unwieldy because of the
rapid decrease in capacitor reactance at these frequencies.
In calculating TN at higher frequencies, an alternate method
is to measure (Rp) the real part of the gate-source impedance of the FET. (7) When ~ is measured at various frequencies, the equivalent short-circuit input noise current
ON) can be computed as a function of frequency (See
Equation (17) ). A convenient instrument to measure Rp is
the Hewlett-Packard Type 250A Rx meter or equivalent.
The Type 250A Rx meter can measure Rp accurately up to
200K ohms. As is shown in Figure 12, this establishes the
low frequency limit of 20 MHz for TN computed via direct
measurement of Rp for the Siliconix FET Typ:..2N4117 A.
For frequencies between 100 Hz and 20 MHz, iN must be
extrapolated, as is shown in Figures 12 and 13. For FET
types with lower Rp (such as the Siliconix 2N4393)TN c~
be computed down to 2 MHz, and hence extrapolated iN
between 100 Hz and 100 kHz is more accurate.
10-12

Cij 1000K

AnticipatedTN is

~
~

ew

TN "" 10-15 Amperes/v'HZ

(23)

e

z

"in

10-13 ~

lOOK

I."

~
w

~

and

~

TN 2 = 10-30 Amperes/YHz.

(24)

Z

10- 14 ~

'.K

..

1

Thus

~

~

"

"'~

.,

lK

,.

,

10-15

lK

f - FREQUENCY (MHz)

(25)

Low Frequency Limit for Calculated iN

Figure 12

Therefore, TN 2 . RG 2 is much less than eT2 , which renders
this method of finding TN impractical for most common
MOS FETs or junction FETs.
An improved method of measuring TN 2 is to substitute a
low-loss mica capacitor for resistor RG. The mica capacitor
by defmition does not have equivalent thermal noise voltage,
and thus Equation (21) becomes
..LllUUL.Ll..IlillU

1.-1.

1000K

(26)
(where

7-44

Xc =capacitive reactance)
Siliconix

,,,
1
Z

(J

f - FREQUENCY 1Hz)

Extrapolated iN

YS

Frequency

Figure 13

The following are representative eN, iN curves for Siliconix J-FET products. Of particular importance is the geometry
which by its design governs the basic noise characteristics of product types derived from it.

NCB

NIP

lK

lK

10- 13

2N5434

INI GEOMETRY)

Ii
-"
OS

15

2'

,

z

0

10- 14

100

~

c

15

.

0

10

,

,if
1
10

10K

0

~

~

~

10- 15

,

z

0

J1)-14 ~

100

~

~

>

g

OS

0

~

0
0

m

2'

Ii-"

z
l>

>

l"

is

EI

,if

w

0

~

10- 15

10

"

,

~

z

10- 16
lOOK

l>

1
10

f - FREQUENCY (Hz)

100

lK

10K

10- 16
lOOK

f - FREQUENCY (Hz)

NPA

NRL
10- 13

lK

~

lK

2'

,

z

0

OS

10- 14

w

"~

~

0

0

>
0

10- 15

is

,

Z

,if

I.
S

10- 13

2N3821
(NRl GEOMETRY)

VOS=10V
'OSS=106mA

~
OS

,,',

TA=2S·C

z

0

10- 14 ~

100

0

15
~

~

0

>
10- 15

10

0

;;
;-

is

£1

,if

I.
l>

l"

z

,

£1

10- 16
tOOK

10K

f- FREQUENCY (Hz)

10-16
lOOK

f - FREQUENCY (Hz)

PSA

NT
10- 13

~

,,',
Z
0

~w

iii0

"~

~

..

0

>

Z

w

0

is

10- 15 ~

,if

~

z

,

lK

,,',

~:;;

Z

10- 14

-"
w

"~

~

0

Z

>
w

10- 15

0

is

,

z

~

;;

~

,if
1

10K

~

0

10

100

lK

10K

lOOK

f - FREQUENCY (Hz)

f - FREQUENCY 1Hz)

FET Noise Characteristics by Geometry
Figure 14

Siliconix

7-45

CONCLUSION
Contemporary junction FETs have noise voltages (eN) equal
to those found in low-noise bipolar transistors_ Each type
of device has a different operating mechanism: the FET is
voltage-actuated, while the bipolar transistor is currentactuated. Hence, FETs have an inherently lower noise current (iN) and are preferred over bipolar devices in most
audio-frequency applications where low-noise performance
is a design requirement.
When bias points are properly selected, as described in this
Application Note, the excellent low-noise characteristics of
high gfs junction FETs can be realized.
The curves shown in Figure 14 are representative ofeN and
TN performance of Siliconix junction FETs. Of particular
importance in these curves is the process geometry by which
the basic design of the FET governs the noise characteristics of product types derived from it. Readers are invited
to refer to the Siliconix FET catalog for full geometry performance data, and for specific part numbers stemming
from the generic process geometries.
In the measurement section of this Application Note, it
was shown that direct eN measurements can readily be
made. TN can be guaranteed at frequencies below 100 Hz by
measuring the DC operating gate current (IG). When IG is

7-46

known, iN can be extrapolated from frequencies below
100 Hz to predict noise performance at frequencies to
100kHz.

REFERENCES
(1)

Nyquist, H., "Thermal Agitation of Electric Charge in
Conductors," Phys. Review 32 (1928), plIO.

(2)

Van der Ziel, A., "Thermal Noise in Field-Effect
Transistors," Proceedings of the IRE, Vol. 50, August
1962, pp 1808-1812.

(3)

Fitchen, F.C. and Motchenbacher, C.D., LOW NOISE
ELECTRONIC DESIGN, 1st Edition, John Wiley &
Sons, New York, 1973, pp 103-107.

(4)

MacDonald, Charles L., "Behavior of FET Gate
Current," Siliconix incorporated Application Note,
April,1969.

(5)

Radeka, V., "Field-Effect Transistors in ChargeSensitive Amplifiers," National Academy of Sciences,
National Research Council Publication 1184.

(6)

Op. cit., LOW NOISE ELECTRONIC
pp 3Q.31.

DESIGN,

(7)

Op. cit., LOW NOISE ELECTRONIC
pp 103-107.

DESIGN,

Siliconix

H

Siliconix

Differential JFET Amplifier
Ted List

The discrete JFET differential amplifier has many perfonnance
advantages over its integrated circuit equivalent. In particular, the
noise levels and input leakage currents can be significantly lower.
Given adequate device characterization data, designing a discrete
amplifier IS a simple two-step procedure.
For example, the U40l,s a monolithic dual JFET used in low-noise
JFET-input amplifiers, low-to-medium frequency amplifiers, precision instrumentation amplifiers and comparators. The device has
an excellent offset voltage rating (5mV) and nonnally does not
need thennal and offset adjustments in the circuit because the two
JFETs are closely matched. The characteristics are guaranteed at
15V and 200,...A, Table I, and the equivalent input noise is specified
at 20nV/!Hz maximum at 10Hz.
Two steps are required to design a circuit with good gain and noise
characteristics.
Step I: Using the circuit shown in Figure I, assume ± 15V supplies
are available (±V,). The source voltage Vs is set equal to zero so
that 15V appears across the current-limiting diode, CRt. Since the
JFETs are characterized and production tested at 200,...A, choose
a current-limiting diode with a forward-current rating close to

400,...A (200,...A quiescent current in each JFET).
The CR043 , for instance, is rated at 430,...A and operates well
with a 15V drop across it. The remaining 15V is divided between
the JFETs and the drain resistors. The 7.5V across the JFETs is
more than sufficient for operation tn the saturation region.
Step 2: Calculate the value of the drain resistors from their voltage
drop (7.5V) and current (215,...A):
RL ,

= RL2 =

7'%.215

= 34.884kfi

The nearest standard 5% value to 34.88kfi is 36kfi; 33kfi could
also be used.
In summary.
+V, = +15V
-V, = -15V
Q, and Q 2 = 'h U401
R L , = RL2 = 36kfi (3kfi optional)
CR,
CR043

=

The amplifier characteristics are shown in Table 2.

Table I - U401 Partial List of Parameters
Parameters
VGS(off)
IG

g,.

g08

CRSS

en
VGS,-VGS2
a(vGS,-VGS2~aT

Vos
Vos
Vos
Vos
Vos
Vos
Vos
Vos

ConditIon

Limits

= l5Vl o = lnA
= l5Vl o = 200,...A
= l5Vl o = 200,...A

- 0.5 to - 2.5V
-15pA
2t07mmhos
20,...mhos
3pF

= l5Vl o = 200,...A

= l5Vl o = 200,...A
= l5VVGS = OV

= 10Vl os =200,...A
=10Vln = 200,...A

Siliconix

--

20nV/IHZ
5mV

1O,...V/oC

7-47

Table 2 - Amplifier CharactenslIcs
~33
~31kn

<15pA
~5mV
~13mW

Vt +

~

.~ RLt

eot

-

.....

e02

...

.....

~ ~CR1
• V1 -

Figure 1

7-48

RL2

H
Siliconix

Wideband UHF Amplifier with
High-Performance FETs
Ed Oxner

INTRODUCTION
A new freedom in UHF amplifier design is possible with
high-performance "Super FETs" such as the Siliconix U3l0
Junction FET. Typical advantages include a closely-matched
75 ohm input for extremely low return loss in cable systems,
and high spurious response rejection with the 3rd order 1M
intercept measured at +29 dBf 1)

The amplifier circuit in Figure 1 is designed for 225 MHz
center frequency, 1 dB bandwidth of 50 MHz, low input
VSWR in a 75-ohm system, and 24 dB gain. Three stages of
U310 FETs are used, in a straight forward design.
Typical parameters are taken from the U310 data sheet:

Additionally, the high common-gate forward transconductance of the U3l 0 (20,000 /1mho maximum) makes it possible to design an amplifier with wide bandwidth and good
gain, since the figure of merit (gm/C) of the FET is 2.35 x
109 typical - higher than any other known UHF Junction
.FET.

Cl,C4,C7.Cg=68pF
C2.CS
= 500 pf
C3,CG• Cs
01, Q,

act

= 1000 pF
= S.hconlx U310

Forward Transconductance
Input Admittance at 225 MHz
Output Admittance at 225 MHz

L1,L3,LS
L2. L4 • L6
RFC1. RFC2

= 120 nHy

R1. R2

=5HI

l4mmhos
13 mmhos
4mmhos
0.27 mmhos
2.6 mmhos

--

Vo = +20 V

=222nHy
'" 2 2 nHy

Figure 1

Siliconix

7-49

Input match is simplified because the FET input (real) impedance is nearly 77 ohms. A coupling capacitor is used in the
amplifier, rather than a tuned circuit, and thus the values
may be determined:

I
Cs = wXs

where:

'" 68 pF

RsRp

Xp

Three cascaded synchronous single-tuned stages are used to
achieve the desired gain, and thus stage bandwidth and Q
are determined:(2)

Bandwidth of 3 Stages(3) = )2 1/3 -I
Bandwidth of I Stage

75 x 77

= Xs =1T.85 = 488 n

and
Cp= 1.47 pF

( E; )
Ls

I
=-2=120 nHy

=1.122 (I dB)

giving

w CT

Figure 2 shows that the measured input VSWR in the 75ohm system indicated an available bandwidth considerably
greater than that required for the amplifier design criteria.

B/W (I dB)

=98 MHz

Q = 1.15

200 MHz
400 MHz

Blanchard Chart (Inverted Circle Impedance Chart)

Figure 2

7-50

Silicanix

The computed voltage gain per stage is approximately
gfs Rt / n or 2.22 (7 dB). Measured gain for all three stages is
24 dB. The U310 FET in the final stage operates at lOSS,
and thus accounts for the higher measured gain. The gain/
bandwidth response of the amplifier is shown in Figure 3.

With a FET output impedance of 3700 ohms shunted by
approximately 2.5 pF (with 0.5 pF allowed for stray capacitance), the total parallel resistance necessary to obtain the
desired bandwidth is:
Q= wCRt

The 3rd order spurious intercept point is plotted graphically
in Figure 4.(4) The importance of a high intercept point
becomes apparent in a crowded high-level area of the spectrum where signal purity is of utmost priority.

R =
1.15
=330n
t 1.415 x 109 x 2.5 x 10- 12
The tank circuit impedance appearing in shunt with the FET,
is therefore calculated to be about 365 ohms. From this, the
inductance is:

REFERENCES

R
365
L = - = - - =222nHy
wQ w1.15
with a turns ratio of 2.3: 1 to match to 75 ohms. Since each
stage is designed for 75 ohm input and output, three cascaded stages complete the amplifier design.

225 MHz

200 MHz

(1)

"Don't Guess the Spurious Level," ELECTRONIC
DESIGN, February 1, 1967, pp. 70-73.

(2)

REFERENCE DATA FOR RADIO ENGINEERS,
4th ed., p. 242, ITT Corp., New York, N.Y.

(3)

Valley and Wallman, VACUUM TUBE AMPLIFIERS,MIT Rad. Lab. Series, Vol. 18, pp. 172-173.

(4)

Op. cit., "Don't Guess the Spurious Level."

250 MHz
+40
B/W (1 dB) - 50 MHz

INTERCEVOINT

fo= 225 MHz

+20

~

...

1dVV I
/
II
V
Ii
G-24dB

COMPRESSION

24 dB

~

23 dB

-20

-40

III

-60

/

Jrd ORDER

INTERMODULATION
'[RODUCT [

-60

-40

-20

+20

POWER IN IdBm)

Figure 4

Figure 3

-Silicanix

7-51

H

Silicanix

High-Performance FETs
In Low-Noise VHF Oscillators
Ed Oxner
Most communications receivers are limited in their dynamic range because of saturation in the early stages of RF amplifiers or mixers. However, some receiver designs are available which overcome this limitation by using parametric amplifiers and
converters to achieve spectacular increases in dynamic range. There still remain certain limitations in dynamic range which
cannot be remedied by parametric devices. In these cases, the problem lies in the heterodyning of noise sidebands which appear on the receiver local oscillator, entering the passband through strong interfering signals.
Common Types of Noise
Although noise is often difficult to characterize because of its random or nondeterministic nature, it is possible to differentiate various forms of noise through an understanding of the Gaussian distribution of noise about an RF carrier. Briefly stated,
the three major forms of noise are (I) low-frequency noise (I/f); (2) thermal noise (4kTRB); and "shot" noise (in). Further,
these types of noise can be identified from their relationship to the main RF carrier. For example, low-frequency noise predominates very close to the carrier, and falls to insignificant levels when it is displaced more than 250 Hz from the carrier.
Low-frequency noise is associated with surface contamination and other irregularities, such as gate current leakage.
Thermal noise plays the predominant role in the region from the I/f decay point to approximately 20 kHz from the carrier,
and is commonly associated with equivalent resistance where the rms value of noise voltage of the Thevenin generator becomes
the classic (4kTBR)~. Noise appearing beyond the 20 kHz is known as Shot noise, and is directly attributable to noise current.
Because of the typically uniform distribution of shot noise it is also referred to as "white noise."
Origins of Osclllator AM Noise

_Althoug..h an oscillator tends to produce a wave that is nearly sinusoioal, there are other fluctuations pn"spnt_ When the energy
in the frequency domain close to the carrier is observed on a spectrum analyzer, noise appears as a modulation phenomenon.
This observation would be greatly enhanced if the noise contribution was coherent and consisted of discrete sideband frequencies. Without a doubt, the major component of AM noise is the contribution oflow-frequency noise (Iff). Both thermal
and shot noise are relatively insignificant segments of AM noise when compared to I/f. A graph of AM noise vs frequency
removed is shown in Figure I.

-'OOr----r--~----~---r--------~--_r----~--~--~----~--_r------__,
Ie· 760 MHz
;
,
I

;v/
-110

-'20

-r ~~?~iN;:iQ~~~~:RMON'CS
: I I I
!
i
I I
I

81W-10Hz

Of

.

: NORMALIZED NOISE

-130

-140

-15~'':'-DH-::-'--:50::'D~H-:-'--:-':-'kHl..,---'---..J.-'':Z~k'::H,.J....J-'"''''-''''''"'""'"3:-'k"':H'---'---:-'4:-:k":H'-'-.....-'-'.....--:_5~k":'H'=--......--'"u
FREQUENCY (kHZ)

AM Noise vs Frequency Removed from the Carrier

Figure 1

7-52

Silicanix

Design of a VHF Oscillator
The important design considerations for best oscillator performance include using a FET with high forward transconductance,
maintaining the gate at ground potential, and keeping a high unloaded tank Q. The high transconductance is necessary to
reduce the effective noise resistance. The grounded gate reduces the noise voltage contributions to those of the gate leakage
current and the series gate resistance. The high tank circuit Q serves as an effective filter for the sideband noise energy.
The oscillator design is somewhat extraordinary for a circuit employing a FET. The FET chosen was the Siliconix U31O, which
has a forward transconductance value higher than 18 mmho at zero bias (VGS = 0). The oscillator basically consists of two coaxial resonators, one for the FET source and the other for the drain. Oscillation is established by capacity coupling between
the two resonators; output coupling is derived from the magnetic coupling which exists at the open ends of the resonators.
Optimum resonator Q is achieved by designing the coaxial resonators for a characteristic impedance of 75 ohms. The oscillator circuit is shown in Figure 2, and construction details are shown in Figure 3 .
CJ
-

1 pF (SEE TEXT)

.---f---f<») ~~~PUT

C,
100pF

~ J:R::",

*1'000

0

+Vo

'

Oscillator Circuit

Oscillator Construction Details

Figure 2

Figure 3

The technique to establish the proper resonator length for the desired frequency is somewhat tricky, and requires a first-order
approximation of the anticipated capacitive fringing which derives from both the FET and the feedback network. A short circuited coaxial transmission line is theoretically resonant at a quarter-wave length of the resonating frequency, except for the
effects of fringe field capacitance. At resonance

(I)
If the fringe capacitance is known,

Xc

can be calculated as

Xc

=

1
wC

(2)

From this, the resonator length can be determined as

Xc

= tan III

(3)

In making these calculations, a Smith chart is invaluable, as is shown in the following illustration:
Frequency of oscillation
= 760 MHz
FET bigs (from data sheet) = 16 mmbo
Cgs = 3.4 pF
Capacitance from bigs
Allow for stray capacitance and
Cs = 1.5 pF
the feedback network
4.9'pF
Thus

Xc

= j 0.57 (normalized to 75 n)

Locate 0.57 on the Smith chart. The wavelength toward the load = 0.081 X. Since a wavelength at 760 MHz is 39.5 cm., then
the resonator cavity length is simply

39.5 x 0.081 = 3.20 cm (1.26 inches)

Silicanix

(4)

7-53

-

In the completed FET coaxial oscillator circuit, the output coupling loop consists of a single turn made fast to the cavity by
the BNC flange and the FET itself. Although the feedback network appears somewhat crude, it can be replaced by a small
trimmer capacitor for similar operation.
Conclusions
Measured performance of the oscillator is shown in Table IA; AM noise measurements in a 10 Hz bandwidth are shown in TableIB.

TABLEIB
AM Noise Measurement
Frequency Displaced From Carrier

TABLEIA
Oscillator Measured Performance @ 25'C
VD])(V)
ID~mA)

Pout (dBm)
Frequency (MHz)

+10
IS
+6.6
725

+15
16.2
+15.2
742.7

+20
18.2
+18.3
754.7

+25
21
+20
762.9

50Hz
500Hz
I kHz
5kHz

dBc
-130
-139
-143.5
-146

The Reike diagram shown in Figure 4 makes possible the accurate prediction of expected power output and operating frequency with the oscillator feeding directly into a mismatched load. Expansion of the Rllike diagram to show frequency vs
transmission line length (in degrees) will allow prediction of the long-line effect on oscillator stability.

Reike Diagram

Figure 4

7-54

Siliconix

H

Siliconix

FETs in
Balanced Mixers
Ed Oxner

INTRODUCTION
Initial evaluatiOn of the active FET mixer Will imply a disadvantage because of local oscillator dnve requirements;
bipolar devices m low-level mixers require very little dnve
power. However, m high-level mixing this disadvantage IS
overcome in that drive requirements at such mixing levels
are generally the same, no matter whether bipolar or FET
devices are used.

When high-performance, high-frequency junction field-effect
transistors (JFETs) are used in the design of active balanced
mixers, the resulting FET mixer circuit demonstrates clearly
superior characteristics when compared to l!s popular passive
counterpart employing hot-carrier diodes. Companson of
several types of mixers is made in Table I. The advantages
and disadvantages of senuconductor devices currently used
in various mixer cirCUits are shown in Table II.

Why FETs for Balanced Mixers?
The performance pnoritles of modern communication systems have stnngent requuements for wide dynamiC range,
suppression of mtermodulation products, and the effects of
cross-modulation. All of the foregoing parameters must be
conSidered before noise figure and gam are taken mto
account.

Why an Active Mixer?
Active mixmg suggests lugh-Ievel ITIlxmg capability. High
level nuxing m turn infers that active mIXers outperform
passive mixer circuits in terms of wide dynamic range and
large-Signal handling capability. Additionally, the active mixer offers unproved converSiOn efficiency over the passive
mixer, permitting relaxation of the IF amplifier gain requirements and even possible eliminatiOn of the customary RF
amplifier front end.

Since FETs have inherent transfer charactenstics approximatmg a square-law response, their third-order intermodulatlon distortIOn products are generally much smaller than
Table II

Table I
MIXER TYPE

Charactenstic
BandWidth

Single-Ended
Several

DEVICE

Single

Double

Balanced

Balanced

Decade

Decade

decades
possible
0.5

025

Interport
Isolation

Little

10-20 dB

>30dB

Relative

OdB

Bipolar

Low NOIse Figure

High Gam

High 1M
Easy Overload

Low D.C. Power

Subject to Burnout

Low NOise Figure
High Power Handling
High Burn-out Level

High L.O Dnve

Interface to I.F.
Conversion Loss

Low NOise Figure

Optimum Conversion Gam not

Conversion Gain
Excellent 1M products
Square Law CharacterIStic
Excellent Overload
High Burn-out Level

possible at Optimum Square
Law Response Level

JFET

+3 dB

DISADVANTAGES

TranSistor

Diode

1.0

Relative 1M
DenSity

ADVANTAGES

+6dB

L.O. Power
Dual-Gate
MOS FET

Siliconix

Low 1M Distortion
AGC
Square Law Characteristic

High L.O. Power

High NOise Figure

Poor Burnout Level
Unstable

7-55

II1II

those of bipolar transistors. Harmonic distortion and cross·
modulation effects are third.order-dependent, and thus are
greatly reduced when FETs are used in active balanced
mixers.

ahead an additional one-half of the IF cycle, FET "A" is
again ON, but the noise component has advanced 1800
(wift) through the coupling structure, and is now "out of
phase". The process continually repeats itself.

A secondary advantage derives from available conversion
gain, so that the FET mixer becomes simultaneously equivalent to both a demodulator and a preamplifier.

The end result of this averaging (detection) is the cancellation of the noise which originated in the local oscillator,
providing that the mixer balance is precise. (1)

First Order Balanced Mixer Theory

The analysis of the conversion of the signal to the IF passband is similar, but the signal is injected into the coupling
structure at the equipotential tap. Thus at time t2' the signal
vector (e s) is "out of phase" with the local oscillator vector,
elo. The resulting envelope develops a cyclic progression at
the IF rate, since the signal is "demodulated" by the mixing
action of the FETs.

Essential details of balanced mixer operation, including signal conversion and local oscillator noise rejection, are best
illustrated by signal flow vector diagrams (Figure 1).

I,

A schematic of a prototype balanced mixer is shown in
Figure 2. DeSign criteria, in order of priority, include the
following:

II,:;::J H'--..:..,..u....u---------f-- IF

(1)

Intermodulation and Cross-Modulation

(2)
(3)

Conversion Gain
Noise Figure

FETe

SIGNAL
CONVERSION

NOISE
J\EJECTION

A

I

Selecting the Proper FET
Local Oscillator Injection

(6)

Designing the Input Transformer

(7)

Designing the IF Network

Intermodulation and Cross-Modulation
A basic aim in mixer design is to avoid the effects of intermodulation product distortion and crossmodulation. Part
of the problem may be resolved by using a balanced mixer
circuit.
The active transfer function of the FET is represented by a
voltage-controlled current source. For both crossmodulation and interrnodulation, the amount of distortion is proportional to the amplitude of the gate-source voltage. Since
input power is proportional to input voltage, and inversely
proportional to input impedance, the best FET 1M and
cross-modulation performance is obtained in the commongate configuration where the impedance is lowest.(2)

elo

~
lien
I,

_11_WfJ

II

Signal and Noise Vectors

Figure'

Energy conversion into the intermediate frequency (IF) passband is the major concern in mixer operation. In the following analysis, both the signal and noise vectors are shown
progressing (rotating) at the IF rate (wift); the resulting
wave occurs through vector addition.
The analysis of local oscillator noise rejection (Figure 1)
assumes, for simplicity of explanation, that noise is coherent.
Thus at some point in time (t l ) the noise component (en)
is "in phase" with the local oscillator vector (elo) and FET
"A" (the rectifying element) is ON; the JFET mixer acts as
a switch, with the local oscillator acting as the switch drive
signal. One-half cycle later, at time t 2 , the signal flow is
reversed for both the local oscillator vector and the noise
component, FET "A" is OFF and FET "B" is ON. Moving

7-56

(4)
(5)

When JFETs are used as active mixer elements, it is important that the devices be operated in their square-law region.
Operation in the FET square-law region will occur with the
device in the depletion mode. Considerable distortion will
result if the FET is operated in the enhancement mode
(positive, for an N-channel FET); by analogy, the problems
encountered are similar to those which arise when positive
drive is placed on the grid of a vacuum tube.
Square-law region operation emphasizes the importance of
establishing proper drive levels for both quiescent bias and
the local oscillator. The maximum conversion transconductance, gc' is achieved at about 80% of the FET gate cutoff
voltage, VGS(off)' and amounts to about 25% of the forward
transconductance, gfs' of the FET when used as an amplifier.

Siliconix

T,

III III
III III
III III

SIG

C,
50nn

~

4
50n

OUTPUT
IF

C1. C5 - 01 "fd
c2. C4- 1 - 10 pF
C3
- 1000pF
C6. ca - 30 pF
C7. Cg - 68 pF

C31

eTO
-OlI1F
LT. L2- 1 311Hy

===.

°1.°2- U310 121
T1

0. U430

- RELCOM BT-9

Prototype Active Balanced Mixer

Figure 2

Since conversion gam (or loss) must be considered, it
common to equate voltage gain Av, as:

IS

load impedance is high, then distortion will develop. However, if proper steps are taken to prevent drain load distortion, the varactor effect will also be inhibited.

(1)

where gc is the conversion transconductance and RL is the
FEr dram load.

15

criminately increasing the drain load resistance will adversely
affect any design priority concerning distortion - particularly intermodulation product distortion.

SOURCE INJECTED MIXER (L
& SIGNAL)
FREQ LO .. 120 MHz, POWER LO +17 dBm

\
14

An attempt to achieve maximum conversion gam by mdls-

a

\

13
12

"
'0

Distortion takes different forms in mIXers. Most obvIOUS is
that distortion which will occur if the FEr is driven into
the enhancement mode, as noted earlier. A more pernicious
form is drain load distortion. And finally, there is the socalled "varactor effect."

\

~~~iNS:~;E~!:CHEl

1700 ohms

50DOohms - -

\
\

INTERCEPT
POINT

\

.44
.40

.3.
>32

\
\

"',0
.'2

.,
.4

The most frequent cause of poor mixer performance stems
from signal overloading in the drain circuit. Excessive drain
load impedance degrades the intermodulation characteristics
and produces unwanted crossmodulation signals.(3) A characteristic of the FEr balanced mixer is that the correct
drain load impedance is inversely proportional to the value
of the conversion transconductance. Figure 3 shows the
improvemen t in IM characteristics obtained in the prototype
mixer with the drain load impedance reduced to 1700 n
from 5000 n. Specifically, the dynamic load line must be
plotted so that the signal peaks of the instantaneous peak-topeak output voltage are not permitted to enter into the nonsaturated ("triode") region of the FEr. Suitable and unsuitable drain load lines are shown in Figure 4. Load impedance
selection is quantified in Equations 18 through 20.
Distortion from the "varactor effect" is of secondary importance, and arises from an excessive peak voltage signal
swing, where the changing drain-to-sorce voltage can cause
a change in parasitic capacitance, erss' and give rise to harmonics.(4) A FEr tends to be voltage-dependent when the
drain voltage falls appreciably below 6 volts. If the source
voltage (from the power supply) is also low and the drain

Silicanix

VGS

Comparison of Mixer 1M Characteristics

Figure 3

Plotting Drain Load Lines

Figure 4

7-57

Conversion Gain

Figure 5 shows plots of normalized conversion transconductance, gc/gfs versus normalized quiescent bias, VGS/
VGS( off), for different oscillator injections.

In a FET, forward transconductance is defined as( 5)

(2)

-1- t- ~~~~':>:0

28

and conversion transconductance is defined as(6)
dID(wi)

c

dVgs(wr)

! \ \

2.

(3)

g =---

1..-- I~

24

~

/,-16

~

where wi = the intermediate frequency and wr = the signal
frequency.

12

The effects of time-varying local oscillator voltage, V 2, and
the much smaller signal voltage, V I, must be considered:
Vgs = VI cos Wit + V2 cos w2t

I
o

(4)

/

VLO = VG~(Off' -

\ov

VGSloffJ

- LO=-,-_

V

/

X

rv

r-VLO" 0 8 VaS(off)

v

~ ,\ \
~ \ i\

VaSfoffl
LO=-.-

02 04

06 DB 10

~ I\.

1214

16 18 20

VGONGSloff)

For square law operation(7)

Normalized 9cl9f vs. VGl;N GS(off)
(from "FET RF Mixer DeSign Technique", S.P. Kwok,
WESCON Convention Record (1970) 8/1, p.2.)
Figure 5

(5)

V2 + VGS ';;;VGS(off)
Drain current is approximately defined by (8)
VGS] 2
ID =IDSS [ I - - - VGS(off)
or (9)
I

""gfso VGS(off)
D
2

[1- ~l

(6)
Noise Figure
2

VGS(off)

(7)

or
I

gfso
D"" 2VGS(off)

(8)

then (10)
ID""

g[so
2VGS(off)

(complex Taylor expansion)

(9)

which can be reduced to
gfso
ID(IF)""2V
VIV2cos(wl-w2)t
GS(off)

(10)

Like the common-gate FET amplifier, the common-gate FET
balanced mixer is sensitive to generator resistance, R g.(1I)
A change of a decade in Rg can produce a noise figure variation of as much as 3 dB.
In the design of the prototype FET active balanced mixer,
the generator resistance of the FETs is established by th~
hybrid coupling transformer. Two important cliteria for the
FETs in the circuit are high forward transconductance, and
a value of power-match source admittance, gigs' which closely matches the output admittance of the coupling transformer. In the common-gate configuration, match point~ fer
optimum power gain and noise do not occur at the same
value of generator resistance (Figure 6). Optimum noise
match can only be achieved at the sacrifice of bandwidth.

and the conversion transductance is
(11)
Equation II suggests that gc increases without limit as V 2
increases without limit. However, to avoid operation of the
FET in the "triode" region, the peak-to-peak swing of V 2
should not exceed VGS( off)'
Thus
2 V2 peak ';;;VGS(off)

(12)
GENERATOR RESISTANCE In}

or
V

7-58

k ~ VGS(off)
2 pea '"
2

(13)

Silicanix

Power Gain and Noise Matching
Figure 6

How to Select the Proper FET
Conversion efficiency is determined by conversion transconductance, gc' which in turn is directly related to such
FET parameters are zero-bias saturation current, lOSS, and
the gate cutoff voltage, VGS(off):
lOSS
gC=VGS(off)2 IV21

however, that conversion transconductance, gc' can never
be more than 25% of forward transconductance. Thus as
tradeoff considerations begin, the first sacrifice to be made
will be the degree of achievable conversion gain. Intermodulation performance will follow with the third tradeoff being
available noise figure. Table III lists a numbet of possible
alternatives to the U310.

(14)

gfso

Table III
DEVICE TYPE

TYPical

""-==-=-=--

(15)

2VGS(0ff)

Equation 15 appears to indicate that FETs with high lOSS
are to be preferred. However, lOSS and VGS(off) are related,
and Figures 7 A and 7B show that devices from a family
selected for high lOSS do not provide high conversion transconductance, but actually produce a lower value of gc'

v

Characteristic

lOSS

U310*

2N5912

2N441S*

14K

SK

5K

2N3823
3.5K

40mA

15mA

lOrnA

lOrnA

·Similar devices are also available in plastic packages:
U310 (J310)
2N4416 (2N5486. J304-18)

Local Oscillator Injection

/

Low 1M distortion products and noise figure, plus best
conversion gain, will be achieved if the voltage swing of the
local oscillator across the gate-to-source junction is held to
the values presented in Figure 5. VLO is expressed in terms
of peak-to-peak voltage, while VGS(off) is a d.c. voltage.

2r-~-r-r~~t------+---+--4

Local oscillator injection can be made either through a bruteforce drive into the JFET source through the hybrid input
transformer, or through a direct-coupled circuit to the JFET
gates where less drive will be required for the desired voltage
swing, Two circuits to obtain direct gate coupling are suggested in Figure 8.

'oss(mA.)

a.

4r--r-r-r+-~+------+--~-

'3L-~-5~LJ-LL'~.------2~.--~3.~4.
IDSS (mAl

b.

--

Relationship of lOSS and VGS(offl
Figure 7

GATES TIED IN PARALLEL
L2 RESONATES WITH Cg
a.

Best mixer performance is achieved with "matched pairs"
of JFETs. Basic considerations in selecting FETs for this
application are gate cutoff voltage, VGS(off)' for good conversion transconductance, and zero-bias saturation current,
lOSS' for dynamic range. A match to 10% is generally adequate. Among currently available devices, the Siliconix
U310 and the dual U431 offer excellent performance in
both categories; common-gate forward transconductance is
20,000 pmhos max at VOS = 10 V, ID = 10 rnA, and
f= 1 kHz.
There is, of course, the possibility that FET cost is a major
consideration in evaluating the active balanced mixer approach - the familiar price/performance tradeoff. If this is
the case, there are a number of other Siliconix FETs which
will provide suitable alternatives to the U310. Remember,

Siliconix

GATES DRIVEN PUSH-PULL
SOURCES TIED TOGETHER
b.
Alternate Forms of L.O. Injection
Figure 8

7-59

-

The source-injection method is used in the design of the
present mixer to maintain the inherent stability of a common-gate circuit. A minor disadvantage with the dlrectdrive method is that the required gate-to-source voltage
swing requires considerable local oscillator input power_
For source injection through the transformer. best mixer
performance is obtained with a local oscillator drive level of
+12 to +17 dBm across a 50-ohm load.

",

"

Conversely, direct coupling to the FET gates occurs at a
higher impedance level and less local oscillator drive power
is required. The functional tradeoff resulting when the gates
are tied together is that shunt susceptance requires some
form of conjugate matching, and thus brings about an undesirable reduction of instantaneous mixer bandwidth.

"

",
4-Port Hybrid with Phase and Isolation
Figure 9

Designing the Input Transfonner
Five criteria are important to the design of the hybrid input
coupling transformer for best mixer performance. The impedance transformer must

(1)

Consist of four single-ended terminals, for the local
oscillator, the input signal and FETs A and B

(2)

Offer a match between either input to a symmetrical balanced load '

(3)

Provide as much isolation as possible between the
signal and local oscillator ports (Figure 9)

(4)

Maintain a differential phase of 1800 across the
symmetrical balanced loads

(5)

Introduce the least possible amount of loss

A transformer using ferrite cores and meeting these five
requirements is derived from elementary transmis~ion-Iine
theory (Figure 10). Transmission line transformers have a
low-frequency cutoff determined by the falloff of primary
reactance as frequency is decreased. This reactance is determined by the series inductance of the transmission line conductors. On the other hand, high-frequency performance is
enhanced by minimizing the phYSical length of the transmissIOn line. Minimizing overall line length while mamtaining suitable reactance can be accomplished by using a
high-permeability core material such as a ferrite. (12) The
transformer constructed for the balanced FET mixer closely
resembles the balanced 4-port unsymmetrical 1800 hybrid
device described by Ruthroff.(l3)

2"

:: ==

Hybrid Input Coupling Transfonner
Figure 10

7-60

Siliconix

=.

'"
Zo"2R

Although Ruthroff does not discuss the method of determining the winding length ofbifilar Wife, a solution is offered
by Pitzalis.(l4) The Pitzalis definitions for wire length are
as follows (Figure 11):
7200n .
max length = -f- - (mches)
upper

A

2R

(16)
ZR

.
nun length

20RL
/) f

=(1 + P Po

lower

(mches)

-=-

(17)
a.

where RL = the load impedance, p/Po = the relative
permeability of the ferrite at the lower frequency, and n =
a fractional wavelength determined by the amount of allowable phase error.

Zo" 2 Zo OPTIMUM

Zo = Zo OPTIMUM

Zo= }Zo OPTIMUM

Selection of the ferrite core material is determined mainly
by performance requirements. A prime consideration for
wide band performance is the temperature coeffiCient of the
ferrite, which must have a low loss tangent over the required
temperature range, i.e., high Q.

02

06

14

,.

LENGTH OF WIRE A (n)

b.

In addition, an important design factor involves the relative
permeabihty of the core, since inductance of a conductor is
proportional to the permeability of the surrounding medium.(1S) A high permeability material placed close to the
transmission line conductors acts upon the external fringe
field present, appreciably magnifying the inductance and
providing a lower cutoff frequency. Power transferred
from input to output is coupled directly through the dielectric medium separating the transmission hne condcutors;
thus a relatively small cross-sectIOn of ferrite material can
operate in an unsaturated state at impressively high power
levels. For the FET balanced mixer, ferrite core material
with a permeability of 40 provides satisfactory operation
from 50 to 250 MHz. Figure 11 also demonstrates that a
lower transmission line impedance, Zo, is to be preferred
over a higher ZOo Both S().ohm and 10().ohm transmission
lines are required for the mixer transformer; twisted pairs
will provide satisfactory results. A characteristic impedance
of 45 on is obtained from 3 turns-per-inch of Belden
No. 24 AWG enamel wire, while 3~ turns-per-inch of No.
24 (7X32) Belden plastic covered wire provide Zo = 100
ohms. Each core is wound with 2 inches of the proper
twisted pair, with min/max lengths calculated from Pitzalis'
data (Formulae 16, 17).
As with all broadband transformers, the coil has an inherent
parasitic inductance which must be capacitor-compensated
(C 2, C4, Figure 2).(16) A trim capacitor is required at the
two input terminals, and is adjusted only once to optimize
the differential phase shift across the symmetrical balanced
FETs. Phase match of the hybrid structure may be tracked
to within ±2 degrees (about 180°) to 250 MHz. Effective
resistance transformation is useful from 50 to 550 MHz
(Figure 12) - but phase track beyond 250 MHz may show
too much deterioration.

Toroid Coil Winding Data
Figure 11

Designing the IF Network
The IF network performs two important functions III the
FET balanced mixer circuit. It provides for optimum match
between the FETs and the IF amplifier, and it effectively
bypasses the circuit RF components (signal and local
oscillator).
In network deSign, it is essential that the RF and local oscillator signals be sufficiently isolated from the intermediate
frequency signal to maintain rejection levels of at least
20 dB. If thiS isolation IS not maintallled, conversion gain
and noise figure are degraded.
The simplest technique for design of the IF network is to
use the well-known pi (11) match structure from each FET
drain to a common balanced output transformer network. (17) This pi match technique is especially suitable for
a narrow-band intermediate frequency output, serving three
useful functions. First, it serves to achieve the proper drain
load match between the FETs and the IF structure. Second,
it provides the very necessary isolation of the intermediate
frequency signal. And third, it serves as a simple filter to
provide a monotonic decrease in Impedance as frequency
departs from the IF center frequency, f o.(l8, 19) This third
function, shown in Figure 13, prevents the drain load impedance from skyrocketing out of control and giving rise to
distortion products.
Selection of the dynamic drain impedance value in the IF
network is a critical point in design of the structure. Intermodulation product distortion and crossmodulation will be

Siliconix

7-61

~

__

50n - 200n Balun
Figure 12

both affected by the instantaneous peak-to-peak output
voltage of the FETs, if the value of the dynamic drain impedance allows these signal peaks to enter either the pinch-off
voltage or breakdown voltage regions of the transistors'<20)
If the impedance is too high, the dynamic range of the mixer
will be severely limited; if the impedance is too low, useful
conversion gain will be sacrificed.

A first-order approximation to establish the proper load
impedance may be obtained when

For the U3lO FET, the optimum drain load impedance is
established at slightly less than 2000 ohms, with sufficient
local oscillator drive and gate bias determined from the conversion tran scond uctance curve in Figure 5.
The output IF coupling structure is an 800-ohm CT to 50ohm trifilar-wound transformer (Relearn BT-9 or equivalent).
The pi (n) match into this transformer provided a dynamic
drain load impedance of 1700 ohms on each FET; excellent

(18)

t
DISTORTION REGION

where

. = IDSS [1 v
gs- ] 2
Id
- -

(19)

VGS(oft)

=======,,-,-,---,====='-'
'.

and
(20)

7-62

Siliconix

Pi hr' Match Filter Function
Figure 13

1M performance was obtained. Value of operating Q was
established at 10 as the best compromise to insure that the
tolerance of the pi match components would permit the IF
output to peak within the allowable bandwidth at the associated IF amplifier. A Q of more than 10 would result in a
greatly restricted bandwidth, while a Q of less than 10 would
result in excessively high capacitance, excessively low induc·
tance, and unsatisfactory filter performance.

Table IV
5()'250 MHz Mixer Performance Comparison

JFET

Characteristic
IntermoduJatlon Intercept Point

+32 dBm +28 dBm

Dynamic Range

80dBt

+8.5dBm

+3dBm

+1 dBmt

+2.5 dB'

-6dB

+18 dB

7.2dB

6.5 dB

6.0dB

Signal when the deSired Signal

first expenences compression)
ConverSion Gam
Single~sldeband

NOise Flgure@

50MHz

tEstlmated

Insertion loss measurements on the IF network amounted to
3 dB in the center of the passband, while insertion loss on
the hybrid assembly measured 1.2 dB. The network exhibited
a Q of 10. Gain .and noise fIgures were measured over the
full S(}'2S0 MHz bandwidth, with a single-sideband noise
figure ranging from 7.2 dB at SO MHz to 8.6 dB at 2S0
MHz. Conversion gain was a flat +2.S dB.

Two-tone third-order inter modulation is expressed in terms
of the intercept point.(21) With two signals 300 kHz apart,
the balanced mixer suppressed third-order products -89 dB
with both signals at -10 dBm, representing an intercept
point of+32 dBm.

r.
";::<

:

Ih

+12 dBmt

100dB

(the level for an unwanted

Tests of the operational prototype FET balanced mixer
demonstrated that the active mixer has several characteris·
tics superior to those of passive mixer counterparts. These
comparisons are made in Table IV (measurements of all
three mixers were made under laboratory conditIOns).

m

Bipolar

100dB

Desensitization Level

Mixer Performance

Schottky

'If.

·Conservatlve minimum

Figure 14 shows a comparison of third-order 1M products
emanatmg from both the JFET balanced mixer and a typical low-level double-balanced diode mixer, under similar
operating conditions. Noise figure and intercept point are
shown at various bias and local oscillator drive levels in
Figure IS.

The performance of the active mixer is clearly supenor to
that of the diode mixers, contributing overall system gain
in areas critical to telecommunications practice, and reducing
associated amplifier requirements.

r

.

lIH

"up ..

J,9

-"

t

:-,-

~.".-"

~

JfET BALANCED
MIXER

-

l&1li

Comparison of 3rd Order 1M Products
Figure 14

Silicanix

7-63

MEASURED PERFORMANCE SOURCE - INJECTEO MIXER
L 0 POWER +17 dBm AND +22 dBm
DRAIN LOAD IMPEDANCE 170on, 5000n

15

I

14

\

13

12
11

,.

?.
\

17K

6.

\

2.

\

24

"

2.

,.
12

VGS

Noise Figure and, Intercept Point Performance

Figure 15

CONCLUSION
The reason for using the three-core bifilar transformer
(Figure II A) in this tutorial article stemmed from the relative analytical simplicity of such a design. An alternative
transformer is the single-core trifiJar-wound design. The
definitions for wire lengths (Equations 16 and 17) are
equally applicable to trifdar as they are for bifilar.

(8) J. Watson, INTRODUCTION TO FIELD-EFFECT
TRANSISTORS, Siliconix, Inc., Santa Clara, Ca.,
95054 (I 970). p. 18.
(9) Op. cit., ECOM.Q503-P005-G82I.
(10) Op. cit., "Non-Linear Distortion and Mixing Processes
in FETs," p. 2112.
(II) Op. cit., "High-Frequency JFET Characterization."
(12) O. Pitzalis and T. Couse, "Broadband Transformer
Design for RF Transistor Power Amplifiers," ECOM2989, July 1968. Also in Proc. Electronic Component
Conference (1968).

REFERENCES
(I) Pound, R.V., MICROWAVE MIXERS, MIT Rad. Lab.
Series, Vol. 16, Figure 6.14, p. 274 (1948).
(2) "High-Frequency JFET Characterization and Applications," J.B. Compton, DESIGN ELECTRONICS,
March, 1970.
(3) "The Solid State Receiver," W. Sabin, QST, July
1970, pp. 35-43.
(4) Penfield, P., and Rafuse, R., VARACTOR APPLICATIONS, MIT Press, Cambridge, Mass., (1962), pp. 73ff.
(5) "Non-Linear Distortion and Mixing Processes in
FETS," J.S. Vogel, Proc. of IEEE, Vol. 55, No. 12
1967, pp. 2109-2116.
(6) "UHF FET Mixer of High Dynamic Range," ECOM0503-P005-G821 (1969).(Available from U.S. Army)
(7) Op cit., ECOM-0503-P005-G821.

7-64

(13) "Some Broadband Transformers," C.L. Ruthroff,
Proc. IRE, Vol. 47, Aug. 1969, pp. 1337-1342 (Figure 7(b).
(14) Op. cit., ECOM-2989, July 1968.
(IS) Op. cit., ECOM 2989, p. 6.
(16) Op. cit., ECOM 2989, p. 7.
(17) ARRL HANDBOOK, American Radio Relay League,
NeWington, Conn. (1970) p. 49.
(18) "Reactive Loads - The Big Mixer Menace," P. Will,
MICROWAVES, April 1971, pp. 38-42.
(19) Op. cit., "The Solid State Receiver."
(20) "Distortion in FET Amplifiers," J. Sherwin, ELECTRONICS, Dec. 12, 1966.
(21) "Don't Guess The Spurious Level," F.C. McVay,
ELECTRONIC DESIGN, Feb. 1,1967, pp. 70-73.

Siliconix

H

Siliconix

A New Current Limiter
Extends Protection to 240V
Ted List

INTRODUCTION
SIlicomx has developed a family of protective devices with
ratings ranging from 135 volts to 240 volts. These are two
terminal devices which provide active current control over
a voltage range of (l.9V to 240V. Five parts are offered
which provide protectIOn for the following maximum
voltages:
Part No.
JR
JR
JR
JR
JR

Peak Operating \bltage
135
170
200
220
240

135V
170V
200V
220V
240V

volts
volts
volts
volts
volts

signal levels below 0.6 volts, no additIOnal distortIOn is
introduced. Power consumption is micro-watts, except In
the protective mode where the dISsipatIOn IS the applied
voltage multiplied by the limiting current.
Because these are two-terminal devices, Installation into a
PC board is simple, cost effective, and no additional
CirCUitry or power supplies are needed.

FUNCTIONAL DETAIL

The current IS limited to a minimum of 160l'A at 0.9 volts
and a maximum of ImA at the Peak Operating \bltage
(POV). The series Impedance is a resistive 5Kll and at

The eqUivalent cirCUit (shown in Fig. lc) IS a current
generator With a resistor and capacitor in parallel. This
differs from the classic constant-current diode in that it
contains no external source resIStor. Voltage is developed
across the channel-source resistance (VP/ Idss).

c

a) Symbol

b) Schematic

c) Equivalent

FIGURE 1
High Voltage Protection Diode (current limiter)

Siliconix

7-65

l
!zw
a:
a:

:::)

U

w

C

o
~
c

;
a:

fZ

~

I

~0~1I~~H-11-1-1-1-1-1-1-1-+-+++1-+-+-+-+-+-+-r-r1-~

II
o

I

I
50

100

150

200

250

VAC ANODE - CATHODE VOLTAGE (VOLTS)

FIGURE 2
JR135 Output Characteristics

FIGURE 2 OUTPUT CHARACTERISTICS
There is a difference between a current limiter and a
current regulator. The difference involves both the
intended usage and the current tolerance. The current
regulator is mtended to be an accurate device providing a
specific amount of current at a specific circuit location.
Naturally, a nominal value and a tolerance are involved;
typical maximum tolerances are 5%, 10%, 20% or 30%, and
interchangibiiity and control of circuit parameters are the
reasons for the tolerance.
In contrast, the currenL iiInitel J~ a plutective uevice.
Minimum and maximum limits of current are imposed, but
the tolerance is much less Important. The JR 135, for
example, has no nominal value but does have a 770!,A
maximum value and a 200!,A minimum value. This equates
to a nominal 485!,A ±58~,.

The output characteristic is shown in Fig. 2 with the
measured and typical parameters to show how device
functions and how it is controlled.
The first point of note is VL, the limiting voltage. This is 0.9
volts and is measured at 80% of IFI minimum. The other
information provided by this measurement is the maXlffium
insertion resistance. Applying Ohm's law, 0.9 volts divided
by l60!,A (0.8 x 200t.) gives series impedance (resistive) of
5625 ohms.
The device is measured for minimum current at 2.0 volts.
The value is 200jLA minimum. This value defines one point
on the line representing dynamic impedance. The dynamic

7-66

impedance IS a measure of control of current as voltage
changes. A typical value of dynamic impedance is specified
at 25 volts. The value is 2 meg ohms minimum. The current
will change 0.5jLA per volt of voltage change.
The next point of interest is at 100 volts. At 100 volts, both
minimum and maximum currents are measured. Interestmgly enough, if we apply what we know about the parts,
some trends then form:
1. Minimum value 200!,A at 25V plus 75 volts-timesO.5!'A shows a mmmum lOO-volt limit of 2371-'A.
2. Working backward from 77U!'A at IUOV gives
maximum value at 2 volts of 733!'A and a band
533!,A wide instead of 570!,A.
The remaining point of mterest is the POY. This is measured at lmA because the maximum allowable open line
current in a telephone system is lmA, and this part was
developed with the telephone market m mind. The breakdown characteristic of this device is softer than that of the
J-Fet current regulator.

APPLICATIONS
The primary advantage of using this device is high POY. The
JR series of devices offers applicatIOns for two types of
needs:
1.

Protection

2. Current Regulation

Siliconix

IR
TO REST
OF CIRCUIT

VOLTAGE ACROSS Rin (VOLTS)
FIGURE 3a
Simple Series Protection

iR
TO REST
OF CIRCUIT
DIODE

t

go

VOLTAGE ACROSS Rin (VOLTS)
FIGURE 3b
Series Protection With Shunt Diode

IR
eln

•

-IR

~ ~

•

TO REST
OF CIRCUIT

},:

+

i
r

-=-

VOLTAGE ACROSS Rin (VOLTS)
FIGURE 3c
Bipolar Series Protection

iR
eln

•

iR

~ ~

TO REST
OF CIRCUIT

•

I·:

1
go

-

VOLTAGE ACROSS Rln (VOLTS)

FIGURE 3d
Series Regulators Increase Voltage Protection

Siliconix

7-67

Protection

Current Regulation

FIg. 3 illustrates four variations on the Prot('ctive TIlt'me. A
plot of the resultant voltage (VRL) and lin accompani('s
each vanation. Comhined variations are possible.

Another use of the high-voltage current hmiter is that of
current regulator. TillS is a mutter of current tolerance.
The JR Series current limit IS 200,.,A to 770,.,A measured at
100 volts. These parts are also measured at 2.0 volts with a
single limit value of 200,.,A minimum. The maximum value
is :3t;O')" of the minimum value. This does not make a good
current regulator, but selection is possible.

Fig. :3a depIcts the sImple ",'rips Iinlltpr. TIlt' voltag<'
developt'd across Rin IS a fum·t IOn of tilt' resIstance of [{in.
If Rin is large, the voltagp applied to Rin will be large. [fthe
power dissipated in Hm and th" remainder of the input
drcuit is too large, Pltllt'r the Rill must lw reducl'd or the
voltage must b(' limited. Zenpr di()(lp, or forward-hIased
diodl's will limit this voltage.
A diode can be used to IhUlt til<' \"oltagp across Hill (Fig.
3b). The diode starts to limit at 0.(; or 0.7 volts, til!' samp as
thp current limiter.
Bipolar voltage protect ion (·an II(' pl·o\~ded by using backto-hack eurrent Iimitprs. (Fig. at"). T[lt' ,ame eonsideratrons
apply as III Fig. :3a and :3b.
Increased protection can be accomphshed by connecting
the de~ees in seri('s. (Fig. :3d). The ultlluate circuit using:3
de~ces in series appl'ars in FIg. 4

Cl1

o

Cl2

Cl3

Cl4

Cl5

Cl6

~~~ ~ VGS(off} preferably VDG> 2 VGS(off) (17)

7-72

Siliconix

"Biasing FETs for Zero DC Drift," Evans, L.,
Electrotechnology, August 1964.

H

Siliconix

BUILD A PRECISION CONSTANT
CURRENT SOURCE
By John Grabeklis

Thejunction field-effect transistor (J-FET) has been popular as a constant-current source (eeS) but was restricted
in application because of its relatively low current and
voltage ratings. Furthermore, the J-FET ees generally
involved a tradeoff between lllgh current and low precision, or low current with somewhat improved preCISIOn;
and temperature always played a critical role.

to 100 rnA. This current is provided by the dual 15 V power
supply which must also accommodate the ees reference
current. The Circuit shown m Figure I can work into loads
rangmg in voltage from -10 VDe to +50 V DC. Power dissipation IS a lumtmg factor at high currents and care must
be taken in mountmg the MOSPOWER FET to a suitable
heatsink.

The MOSPOWER® FET, controlled by a low-cost op-amp
resolves many of the former problems ofthe J-FET regulator. MOSPOWER FETs may be selected offering lllgh standoff voltages capable of handhng many amperes. Since precision control of current no longer depends solely upon the
selection of the FET precision high-current regulation IS
possible.

Since It is impossible to deSign a ees with an output current lower than the lOSS of the MOSFET, care should be
taken to use the lowest leakage MOSFET consistent with
the deSired goals. Furthermore, the overall preciSIOn of the
regulator depends upon using the lowest gate leakage current, lGSS, available.

An adjustable ees using a MOSPOWEH FET and an opamp can have either a pOSitive or negative compliance voltage. A ees with negative compliance IS shown m Figure 1.
Th establish a positive compliance voltage, the n-channel
VN1206B is replaced by a p-channel VN1206B; ground is
connected to point B instead of point A; and the currentsensmg resistor is connected to point e instead of point O.
The output current range, using either the p-channel
VN1008B or the n-channel VN1206B, extends from 10 p.A

Combming the VN1206B and the VN1008B a dual bidirectional ees regulator can be assembled, as shown in Figure
2. By gangmg the switches, KI - K4, thiS design can be used
to supply either a pOSitive or negative current. Current
tracking between the two outputs, eel and ee2, depends
upon the precision matching of Rl and R2. Accuracy
depends upon the combmed gate leakage current, lGSS;
the offset voltage and current of the op-amps; the tolerance and match of the resistors, RI and R2; and the accuracy of the reference voltage, VREF.

Silicanix

7-73

-

TABLE
VALUE OF R (Fig. 1 & Fig. 2)
ILoad (IL)

Resistance (R)

10 J.lA
100 J.lA
1 rnA
10 rnA
100 rnA

1.5 M!l
150 K!l
15 K!l
1.5 Kn
150 Kll

Power
Rating

V.W
V.W
V.W
'hW
3W

D

Precision Current Source
Figure 1 (Note 1)

-15 VOLTS

Dual Precision Current Source
Figure 2 (Note 1)

NOTE:
1. All sWitches are shown for negative compliance.

7-74

Siliconix

H

Silicanix

FETs As
Voltage-Control/ed Resistors

,INTRODUCTION
The Nature of VCRs
A voltage-controlled resistor (VCR) may be defined as a
three-terminal variable resistor where the resistance value
between two of the terminals is controlled by a voltage
potential applied to the third.
A junction field-effect transistor (JFET) may be defined as
a field-controlled majority carrier device where the conductance in the channel between the source and the drain is
modulated by a transverse electric field. The field is controlled by a combination of gate-source bias voltage, VGS,
and the net drain-source voltage, VOS.

Figure 1 details typical operating characteristics of an NChannel JFET. Most amplification or sWitching operations
of FETs occur in the constant-current (saturated) region,
shown as Region II. A close inspection of Region I (the unsaturated or pre-pinchoff area) reveals that the effective
slope indicative of conductance across the channel from
drain to source is different for each value of gate-source bias
voltage.(2) The slope is relatively constant over a range of
applied drain voltages, so long as the gate voltage is also
constant and the drain voltage is low.
VOS" VGS - VGSIOffl--fLOCUSCURVE

REGION

Under certain operating conditions, the resistance of the
drain-source channel is a function of the gate-source voltage
alone and the JFET will behave as an almost pure ohmic
resistor.(l) Maximum drain-source current, lOSS, and minimum resistance, rOS(on)' will exist when the gate-source
voltage is equal to zero volts (V GS = 0). If the gate voltage is
increased (negatively for N-Channel JFETs and positively
for P-ChanlJ~_tl:le resistance will also increase. When the
drain ciirr;nt is r;ctiiam to a point where the FET is no
longer conductive, the maximum resistance is reached. The
vo~tage at this point is referred to as the pinchoff or cutoff
voltage and is symbolized by VGS = VGS(off). Thus the
device functions as a voltage-controlled resistor.

Siliconix

11_--r.~1--REGION II~

VGs"O
------~-~---------

SATURATION
REGION

-

VoslVI

Typical N-Channel JFET Operating Characteristics
Figure 1

7-75

Resistance Properties of FETs
The unique resistance-controlling properties of FETs can be
deduced from Figure 2, which is an expanded-scale plot of
the encircled area in the lower left-hand corner of Figure 1.
The output characteristics all pass through the origin, near
which they become almost straight lines so that the incremental value of channel resistance, rds' is essentially the same
as that of d.c. resistance, rDS, and is a function of V GS.(3)

Typical rDS curves for several Siliconix N-channel JFETs
are plotted in Figure 4.( 4) the graphs are usefulin estimating
IDS values at any given value of VGS. All quantities given in
Figure 4 are for typical units, so some variation should be
expected for the full range of production devices. It is therefor deisrable to convert Figure 4 to a ndrmalized plot. This
1MEG

Figure 2 shows extension of the operating characteristics
into the third quadrant for a typical N-Channel JFET. While
such devices are normally operated with a positive drainsource voltage, small negative values of V DS are possible.
This is because the gate-channel PN junction must be slightly
forward-biased before any significant amount of gate current
flows. The slope of the VGS bias line is equal to /:;IDj/:;V DS =
IjrDS. This value is controlled by the amount of voltage
applied to the gate. Minimum rDS, usually expressed as
rDS(on)' occurs at VGS = 0 and is dictated by the geometry
of the FET. A device with a channel of small cross-sectional
area will exhibit a high rDS(on) and a low IDSS. Thus a FET
with nigh IDSS should be chosen where design requirements
indicate the need for a low rDS(on).

~

:2

100K

/

/

I

/

.....-r

/

V / V /,
~

/

/,./ V /

/

-

vc;s"a

voslO1v-

-- c-- I-100

-1

-2

-3

-4

-5

-6

VGS - GATE·SOUACE VOLTAGE (V)

Incremental Drain-Source Resistance for Typical N-Channel FETs
Figure 4

has been done m Figure 5. The resistance IS normalized to
its specific value at VGS = 0 V. The dynamic range of rDS
is shown as greater than 100:1, although for best control of
rDS a range of 10: 1 is normally used.
N-Channel JFET Output Characteristic Enlarged Around VOS = 0
Figure 2

Figure 3 extends the rds characteristics of a FET to a comparison with the performance of 4 fixed resistors. Note the
pronounced similarity between the two types of devices.

Siliconix offers a family of FETs specifically intended for
use as voltage-controlled resistors. The devices are available
in both N-Channel and P-Channel configurations (Figures 6A
and 6B) and have rDS( on) values ranging from 20 n to
4,000 n (Figure 7).

Comparison of FET and Resistor Characteristics

Figure 3

7-76

Siliconix

=VOS

VCR3P'\.~

2

~
~

5
l'--r-OVouT

P·Channel VCR Photomultiplier Load. Required Low Photomulti·
plier Anode Current (Usually < 1 "AI Implies that VC R will Always
Perform in Linear Region Near Origin

Figure 15

Cascaded VCR Attenuator
Figure 11

,----,--------__oVCC
VIDEO

OUTPUT
~-------__oVOUT

V,N

o-jH---+-I::.

Wide Dynamic Range AGC Circuit. No Gain through FET with

Voltage Controlled Variable Gain Amplifier. The Te. Attenuator

Distortion Proportional to Input Signal Level

Provides for Optimum Dynamic Linear Range Attenuation

Figure 12

Figure 16

7-78

Siliconix

Signal Distortion: Causes

Reducing Signal Distortion

Figure 17A repeats the FET output characteristic curves of
Figure 2, to show that the bias lines bend down as VOS
increases in a positive direction toward the pinch-off voltage
of the FET. The bending of the bias lines results in a change
in rDS, and hence the distortion encountered in VCR circuits;
note that the distortion occurs in both the first and third
quadrants. Distortion results because the channel depletion
layer increases as VOS reduces the drain current, so that a
pinch-off condition is reached when VOS =VGS - V GS(off).
Figure l7B shows how the current has an opposite effect

The majority of VCR applications require that signal distortion be kept to a minimum. Also, numerous applications
require large signal handling capability. A simple feedback
technique may be used to reduce distortion while permitting
large signal handling capability; a small amount of drain
signal is coupled to the gate through a resistor divider n-etwork, as shown in Figure 18.
VCR LINEARIZATION

VGS -0

VOUT
-'1.5 V
-25V

-

. .-'""T-_;:::---~tf~;::=:f=
10

-30V

Figure 18

N-Channel JFET Output Characteristic Enlarged Around
Figure 17A

Vas = 0

The application of a part of the positive drain signal to the
gate causes the channel depletion layer to decrease, with a
corresponding increase in drain current. Increasing the drain
current for a given drain voltage tends to linearize the V GS
bias curves. On the negative half-cycle, a small negative voltage is coupled to the gate to reduce the amount of draingate forward bias. This in turn reduces the drain current and
linearizes the bias lines. Now the channel resistance is dependent on the DC gate control voltage and not on the drain
signal, unless the VDS = VGS - VGS( off) locus is approached.
Resistors R2 and R3 in Figure 18 couple the drain signal to
the gate; the resistor values are equal, so that symmetrical
voltage-current characteristics are produced in both quadrants. The resistors must be sufficiently large to provide
minimum loading to the circuit:

>V---------~

(4)

-V~--~---7J-V

Typically, 470K n resistors will work well for most applications. RJ is selected so that the ratio of rDS(on) IIRL to
[(rDS(on) II R0 + Rrl gives the desired output voltage, or:

o

1

rOS(on) IIRL .
(rOS(on) IIRL) + Rl

DIODE
CATHODE
WHEN SIGNAL
SWINGS NEGATIVE

V,N

VOUT

(5)

The feedback technique used in Figure 18 requires that the
gate control voltage, VGG' be twice as large as V GS in Figure 17B for the same rDS value. Use of a floating supply
between the resistor junction and the FET gate will overcome this problem. The circuit is shown in Figure 19, and
allows the gate control voltage to be the same value as that
voltage used without a feedback circuit, while preserving the
advantages to be gained through the feedback technique.

Figure17B

in the third quadrant, rising negatively with an increasingly
negative V DS. This is due to the forward conduction of the
gate-to-channel junction when the drain signal exceeds the
negative gate bias voltage.

Appendix A to this Application Note is an analytical approximation of VCR FET distortion characteristics, both calculated and measured.

SilicDnix

7-79

l1li

,

The forward-biased gate-drain PN junction may be seen at
approximately -0.6 V, and bending of the bias curve is
apparent in the third quadrant. The photo also demonstrates
the comparison between a fixed resistor (the linear line
superimposed on the bias curve) and the distortion apparent
in the VCR without feedback compensation; the VCR signal
is unusable with the indicated amount of distortion.

",
V ,N

Experimental Results

In Figure 21, the same VCR7N FET is shown operating with
the addition of the feedback resistors. Distortion has been
reduced to less than 0.5%, and the characteristics of the VCR
are now closely comparable to those of a fixed resistor.

Figures 20 through 23 show low voltage output characteristic curves for a typical Siliconix N-Channel voltage-controlled resistor, VCR7N. Bias conditions are shown both
with and without feedback. Figure 20 shows a two-volt
peak-to-peak signal on the V GS = 0 V bias curve, with the
VCR operating in the first and third quadrants. The VCR is
operated without feedback.

In Figures 22 and 23, the same VCR FET characteristics are
shown, with VGS adjusted for higher rDS' No feedback network is employed in Figure 22, and measured distortion is
greater than 8%. In Figure 23, the feedback resistors have
been added and distortion has been reduced to less than
0.5%.

Figure 19

<"

.:1
_0

200

200

100

100

<"

.:1

0

.E'

~

.

0

-100

-100

-200

-200

I

-I

I

eol lTfl mil Ii!
,!!
~

II

!. I ! I J

IriIi
II!;i

~

-1.0

-0.4

0

0.4

-1.0

1.0

I
-0.4

VCR7N with No Feedback
Figure 20

-0.4

0

I
1.0

0.4

VCR7N with Feedback
Figure 21

-1.0

1.0

-0.4

0

0.4

Vos(V)

Vos(V)

VC R7N with Feedback
Figure 23

VC R7N with No Feedback
Figure 22

7-80

0.4

Vos(V)

Vos (VI

-1.0

0

Siliconix

1.0

Some degree of non-linearity will be experienced in both
the first and third quadrants as VGS approaches the FET
cut-off voltage. For this reason, it is important that the
feedback resistors be of equal value so that the non-linearities likewise will be equal in both quadrants. Figure 24
shows a curve of distortion vs R2/R3, in both quadrants.

It has also been shown that FETs with high pinch-off voltage
require larger drain-to-source voltages to produce drain current saturation. Therefore, FETs with high V GS(off) will
have a larger dynamic range in terms of applied signal amplitude, while maintaining a linear resistance. It is advautageous to select FETs with high V GS(off) (compatible with
the desired rOS value) if large signal levels are to be
encoun teredo

",

'~'
"2

R3

,.

,,

,.

,

~

APPENDIX A -

From proceedings of the IEEE, October, 1968, pp. 1718-1719.

VCR

"",\o,'Os~."".

Abstract - An analytical approximation of FET characteristics for positive and negative voltages is presented. The distortion in an application as a controlled
attenuator is calculated, and a method of reducing
distortion by a factor of more than 50 is described.

fO'l'COS.,""

p.Ol\)o:;t~".,

'2

........ ....

"G'3,. .."
VGS=O

'.0

~

0.2

04

06

08

10

25

20

15
R2/R 3

Controlled resistors are used in oscillators, controlled amplifiers, and attenuators.c 6,7) The possible control range is
much larger for field-effect transistors (FET) than for other
elements with comparable time constants (e.g., diodes). The
signal-to-noise ratio is considerably improved.

Distortion vs R2/R3
Figure 24
'0

Distortion resulting from changes in temperature are also
minimized by the feedback resistor technique. rOS will
change with temperature in an inverse manner to the behavior of FET drain current. Table I presents the result of VCR
laboratory performance tests of distortion vs temperature.
The VCR7N again was employed. Signal level was 2 V peakto-peak.
Table I
Temperature

Without Feedback
ros - 10 'oseO")

I

With Feedback

fOCI

ros .. rOSlonl

+125

>13%

<05%

<05%

+ 25

>10%

>5%

<05%

<05%

- 55

39%

32%

<05%

<05%

>6%

'OS

rOSlon)

rOS" 10 rOSlonl

I

Comparison Between Mathematical Approximation of FET Characacteristics (Solid Lines) and Measured Curves (Broken Lines) for
a Typical N·Channel JFET
Figure 25

SUMMARY
This Application Note has presented a brief description of
the use of junction field-effect transistors as voltage-controlled resistors, including details of operation, characteristics, limitations, and applications. The VCR is capable of
operation as a symmetrical resistor with no DC bias voltage
in the signal loop, an ideal characteristic for many applications.
Where large signal-handling capability and minimum distortion are system requirements, the feedback neutralization
technique for VCRs is an important tool in achieving either
or both ends.

Figure 25 shows idealized and real FET characteristics. In
region A (above pinch-off) 10 is independent of V OS:(8)

ID =IDSS

(

VGS)
1- Vp

2

(1)

Region B, where VOS < (V GS - Vp), is the so-called triode
region. (In the following discussion all the signs (+, -) will
be valid for N-Channel FETs.) The characteristics can be

Silicanix

7-81

-

approximated by a quadratic function, of which the maxi·
mum and a second point (the origin) are known. The approxi·
mation is

where gDS is the differential conductance at the origin;
when VGS = 0, then gDS = gDSS' The attenuation for the
circuit of Figure 26(a) is

ID=IDSS

1+

21DSS
= (Vp)2

]_1

RgDS

=[

(7)

RgDSS VI

+

--~----~~~~--~~-

2RgDS VI )
2Vp ( I + RgDS + 2Vp (I + RgDS)

This is the same function that can be found by a simple
analysis based on semiconductor theory. The less negative
of the two voltages across the junction (VGS, VG D) controls
the channel conductance. Under the condition that the FET
is symmetrical (drain and source interchangeable), the fol·
lowing consideration is true. If VGD were the controlling
voltage and VDS < 0, I D < 0, then the characteristics
would be the same as in the first quadrant:

v,

b
I

V2

Vos

(.,

",

Since the controlling voltage for both regions (B and E) is
VGS,

V,o-~~----~---------oV2

(4)
Substituting (4) into (3), we get (2); the same approxima·
tion can be used in Band E. The limits of region E where
(2) is valid are VGD = 0 and VGD = Vp. The characteristics
in region D can be found from (1) with the same consider·
ation:

ID=-IDSS

( 1- VGS-VDS
)
Vp

2
(5)

The mathematical approximation is compared with the
measured characteristic in Figure 25. In the regions C and F
the junction is forward biased. The characteristics are depen·
dent on the internal resistance of the gate voltage source
since gate current flows.
The FET as a controlled resistor works in region Band E.
The higher the resistance, the more non·linear are the char·
acteristics. For most applications this is undesirable. Based
on the simple approximation (2), the relation between distor·
tion, control range, and maximum to minimum attenuation
will be described for a simple voltage divider [Figure 26(a)].
Most applications can be based on this simple example. The
conductance in any point of region BorE is

G
DS

=~ =- 2lDSS
VDS

Vp

(1-

VGS)
Vp

lDSS
gDSSVDS
- (Vp)2 VDS = gDS + 2Vp

7-82

(bl

(al Controlled JFET Attenuator. (bl Controlled Attenuator with
"Feedback" Making Characteristics Linear and Svmmetrical
Figure 26

To reduce (7) to a more tractable form, the following in·
equality is introduced:
VI RgDSS
2Vp (1

+ RgDS] 2

«I

so that (7) can now be approximated by the expansion
VI- - ( 1RgDSVI
)
V=+
2 I + gDSR
2Vp (1 + RgDS] 2
...

(8)

Only the second harmonic will be considered for the distor·
tion since the third is much smaller. For small distortion
(d« I and RgDSS» 1),
VI RgDSS
d =---=---==---;:
41Vpl [I + RgDS] 2

(9)

If V2 is held constant,

(6)

Silicanix

(10)

"'"

There are several means of reducing distortion. By connecting two identical FETs in antiparallel or antiseries, nonlinearities can be cancelled out to a certain extent. A better
linearization is possible by usmg one FET with "feedback".
It has been shown above that the characteristics would be
symmetrical if VGO were the control voltage in the third
quadrant. By adding 0.5 VOS to the control voltage, the two
voltage VGS and VGO interchange when VOS changes sign:

,":;

JSf.)

I-~---

~

~VGS(OIfI

...1

fA

(b";

~\
a

•

\

§

1%

I

V

~.:.--==

~2"OOlVGS(QfU i
I

•

VGS = VH + 0.5 VDS

i

j .,

01%

I
•

V2=OTVGS(off!

,........

•. . . . .

~
e

jl

n

~

then (13) used in (2) gives

I

~

I

",. ...t
001';;

o

'"

(14)

V2 = 0 01 ~GS(Offl

y

(13)

VGD = VH - 0.5 VDS

o'

VGSIVGS(offl

Distortion as a Function of VGSIVGS(off) for Two Different
V2/VGS(off)' la) Theoretical for Figure 26(a). Ib) Measured with
Circuit of Figure 26Ia). Ie) Measured with Circuit of Figure 261b)
Figure 27

Figure 27 shows a comparison of measured and calculated
distortion. If VGS approaches Vp, the above restrictions are
violated; the expression for the distortion can no longer be
applied. If V DS < 0, VGS = 0, then the FEr works in regIOn
F; the distortion will be higher than predicted. From (10)
we get for a prescribed maximum distortion a maximum
amplitude as a function of VGS:
(11)

V2max = 4d max IVp - VGSI

For a given d max and V 2max the ratio of minimum to
maximum attenuation is
Amin
1 + RgDSS
Amax = m = +
V2max
1 RgDSS 4d max IVpl

The resulting characteristic is linear and symmetrical in B
and E. The improvement in distortion performance can be
seen in Figure 27. A distortion of 12 percent for V 2 =0.1
Vp at VGS = 0.8 Vp is reduced through linearization to 0.1
percent. Figure 26(b) shows a possible circuit. The frequency
range of the controlled signal must be much higher than that
of the con trolling signal V H to keep the direct interference of
V H on V 2 small. R3 is set for minimum distortion. If V 2
and VH are in the same frequency range, a high impedance
amplifier must be used. V 2 is at the input; the output is
connected to the FET gate. The amplification is approximately 0.5 (adjustable). The control voltage is introduced
through a second input so that no direct interference with
V 2 occurs.

REFERENCES
(1)

J. Watson, INTRODUCTION TO FIELD-EFFECT
TRANSISTORS, Siliconix, Inc. Santa Clara, Calif.
95054 (1970), p. 58.

(2)

"FETs As Voltage-Variable Resistors," Carl D.
Todd, ELECTRONIC DESIGN, Sept. 13, 1965,
pp.66-69.

(3)

Op. cit., AN INTRODUCTION TO FIELD-EFFECT TRANSISTORS, p. 22.

(4)

"FETs As Voltage-Controlled Resistors," Siliconix,
inc., Santa Clara, Calif., 1966.

(5)

Op. cit., AN INTRODUCTION TO FIELD-EFFECT TRANSISTORS, p. 61.

(6)

W. Gosling, "Voltage Controlled Attenuators Using
Field-Effect Transistors," IEEE Trans Audio, Vol.
AU-13, pp. 112-120, Sept.-Oct., 1965.

(7)

J.S. Sherwin, "Voltage Controlled Resistors
(FET)," Solid State Design, pp. 12-14, Aug. 1965.

(8)

L.J. Sevin, "Field-Effect Transistors," New York,
McGraw-Hill, 1965.

4d max IVpl

"'"

(12)

V2max

valid only for m > 1. Note that the maximum distortion is
reached only for minimum attenuation. Examples:
dmax = 10 percent V2max = 0.001 Vp

m = 400

d max = 1 percent V2max = 0.01 Vp

m=

4

Although these relations are only first-order approximations,
they give a good estimate of FEr attenuator characteristics_
The maximum amplitude is proportional to Vp. FETs with
high Vp are desirable for attenuator applications. Unfortunately, the majority of commercially available FETs are made
with low Vp for use in amplifiers.

Siliconix

7-83

l1li

H

Siliconix

FETs as Analog Switches

INTRODUCTION
The past has seen a pronounced growth of analog/digital
systems which employ integrated circuits. One of the interface elements in such a system is the digitally-controlled
analog switch. As more and more applications arise for
the analog switch, especially in the areas of industrial
processing and control, the question is often asked: "Which
is the best switch for my application?"
The sheer variety of applications precludes any pat answer
to this question; however, the user of analog switches can
gain valuable insight on the subject through an understanding
of the nature of solid·state switches. Areas which require
exploration include:

(I)
(2)

Cross-sections for three types of N-channel FETs are shown
in Figure I.
GATE Igl
SOURCE (~l

DRAIN Igi

N-CHANNEL DEPLETED WITH APPLICATION
OF NEGATIVE GATE VOLTAGE

(AI

Basic factors affecting switch performance.
Details of switch-driver circlIi! design.

uATEIg,1

(3)

Total switching characteristics of driver circuits
and switches.

(4)

Characterization of the analog switch at high
frequencies.

SOURCE I§I

DRAIN IQI

BODY (!I

GATE

MOS-fET

The intent of this Application Note is to consider (I) above,
in detail, with minor attention to the other areas.
(8)

N-CHANNEl DEPLETED WITH APPLICATION OF
NEGATIVE GATE VOLTAGE NEGATIVE BODY
VOL lAGE ALSO DEPLETES THE CHANNEL

Field-Effect Transistor Operation
The field-effect transistor (FET) is in effect a conductor
whose cross-sectional area may be varied by the application
of appropriate voltages. When the conducting area (the chan·
nel) is maximum, conductance is also maximum (minimum
resistance). When the conducting area is minimum, conductance is minimum (maximum resistance). This phenomenon
makes possible the use of FETs as analog switches. When
conductance is maximum, the switch is in the ON state;
when conductance is minimum, the switch is in the OFF
state. In the ON state, an N-type channel contains N-type
carriers; similarly, P-channel FETs contain P-type carriers.

7-84

GATE 191

METAL

BODY

f!.1

GATE
MOS-fET

(el

Siliconix

N-CHANNEL CREATED HERE WITH APPLICATION
Of POSITIVE GATE VOLT AGE

N·ehannol FET eross-Sections
Figura 1

P-channel FET cross-sections are quite similar, except that
the channel contains P-type carriers and the voltage polarities are reversed. Depletion-mode devices are shown in Figures IA and IB; these FET types have high channel conductance (are ON) with zero gate-channel voltage, and are characterized as "normally-ON" switches. An enhancementmode FET is shown in Figure 1C. This device requires that
voltage be applied to the control gate to create a conducting
channel - the ON state. Enhancement-mode FETs are said
to be normally-OFF.
For enhancement-mode devices, channel conductance (gOS)
is a function of length (L), width (W), thickness (T), carrier
mobility (P), and mobile carrier concentration (Nc):

Note that the slopes (lIg0S/lIVGS) for all three types of
N-channel FETs are constant and positive, while the slopes
for the P-channel devices are constant and negative. N- and
P-channel depletion-mode FETs are ON when VGS =0, while
enhancement-mode devices of both types are OFF when
VGS = O. Typically, the cut-off voltage, VGS(off)' is designed
to fall in the 1-to-1O volt range, while the gate-to-source
threshold voltage, VGS(th) - that amount of voltage applied
to the point where the device begins to conduct - falls in
the l-to-5 volt range. Figure 2 also demonstrates that gos is
approximately a linear function of VGS , with zero gos
occuring at VGS(off) or VGS(th), as follows:

gDS

Effective channel thickness and carrier concentration are
functions of the electric field in the channel. Voltage on the
control gate changes the field, and hence the channel conductance, gDS.
The gate voltage is applied with respect to the channel (source
or drain). In most devices, the function of the source and
drain can be interchanged, because of symmetrical FET
geometry. By convention, however, voltage is specified between gate and source, VGS. Figure 2 shows the variation of
gos with VGS for both N- and P-channel devices. In all cases,
gos = l/roS·

(depletion)

gDS = K2!VGS - VGS(off)!

=K2!VCS - VCS(th)!

(enhancement)

For a given active area, a junction FET (JFET) will have a
higher conductance slope than a MaS FET. Additionally,
N-channel carriers have higher mobility than P-type carriers.
Thus, all things being equal, N-type FETs have higher gos
(= l/rDS) than P-type devices. If the active area of the device
is increased to raise the gos level, three other FET parameters will also be increased: leakage, capacitance, and cost_
The design tradeoffs of these latter parameters are discussed
in this Application Note.
When a FET is used as an analog switch, the drain-to-source
voltage, VOS' may be either positive or negative. In the OFF
state, a typical switch may have VOS = ±20 V. In the ON
state, current flows equally well from drain to source or
from source to drain (the channel is a resistor). For most
applications, the voltage across the switch will be small.

N-CHANNEL

P-CHANNEL

,

'os . -

os
J-FET

o£'OS
~G
S

o

Vp

(AI

Vp Vas

(D)

MOS-FEY
(DEPLETION

TVPEI

:l
s:

~±~.

0

o

'os

Vp

0

J

Gcr1fi

)...

t

B D--4-I

MOS-FET
(ENHANCEMENT TYPE)

roo

VOSlth) 0

(c)

vGS

-

(E)

(B)

Channel Conductance vs Gate-Source Voltage
Figure 2

Siliconix

'os

v GS

(F)

7-85

RS1O -

VS1G

-2-

"

I

V,

I

2 PORT
NETWORK

RL

V2

(AI

OFF

(BI

V S1G

ON

(CI

I).C Equivalent Circuits
Figure 3

OFF Condition Calculation

DC Equivalent Circuits
The perfect switch would have infinite resistance (zero conductance) when open and zero resistance (infinite conductance) when closed. While the FET is not a perfect switch,
there are many applications where this deviation from perfection is unimportant. This statement can be justified by
an analysis of the implications of the circuits shown in
Figure 3.

(I)

I I = IS = I nA
VSIG - V I = I I . RSIG = (I nA)(IO n) = 10 nV
% Error in V I =

(10-8 V) (102)
10 V
= I x 10-7%

12=ID=lnA
\ The general two-port network in Figure 3A couples the sig- (2)
nal source, VSIG, to a resistive load, RV The network can be
V2(ofO = 12RL = (I nA) (200K n) = -200 !LV
characterized by its terminal voltages and currents, VI, V2,
II, and 12. Figure 3B shows the equivalent circuit ofa FET
(2 x 10-4)(102)
% Error in V2(oft)* =
10
= 0.002%
switch in the OFF state. In this condition, the "source" and
"drain" are not connected to one another; however, two
leakage current sources, IS and In, are present. The same
device is shown in the ON state in Figure 3C. The following
typical values are assumed for the circuit:
ON Condition Calculation
VSIG = 10 V (full scale)

II =IS+ID- 12

IS

V2
12 = RL

=ID= I nA

rDS = lOOn
RL

~

VSIG
RL + RSIG + rDS

VSIG - V2 ~ (50 !LA) (I 10 n) = 5.5 mV

=200Kn

RSIG= Ion
In the following calculations, leakage curren t (deviation
from the state of a perfect switch) is expressed in terms of
error percentage.

7-86

% Error in V2* = (5.5 x

1~~3)(102)

*Referred to VSIG (full scale)

Silicanix

= 5.5 x 10-2 = 0.055%

The foregoing calculations indicate that for all but the most
critical applications the performance of the FET equivalent
circuits in Figure 3 is a good approximation of the perfect
switch. In particular, the OFF condition leakage currents
contribute only a negligible portion of total error.
The actual error currents of three different types of FET
switches are shown in Figure 4. The measured error is much
lower than the I nA (1000 pA) obtained from the sample
calculations. These data are taken from aMOS FET, an N·
channeIJFET, and a complementary MOS (CMOS) combination including a P-channel device and an N-channel device
diffused onto the same substrate. The behavior of these
FETs as elements of analog switching integrated cirCUIts will
be dealt with in detail elsewhere in this Application Note.

110

_. f-"'

90

~.

WITH RESISTANCE MODULATION

NO RESISTANCE MODULATION
-100
% ERROR" , t Rl

~ ~ ..! V~ IV~ ='0)
~VDIVs=O)

100

turn Q2 ON and Q3 OFF, so that S] and G] are connected
(VGS = 0 V) and QI is ON. If VGS is allowed to vary, gns
(= l/rnS) will also vary. This variation in resistance appears
as a source of error when the switch is ON, and the error is
defined as resistance modulation. In Figure 6, the error
percentage in the case of resistance modulation is greater
than that which occurs when funs =O.

... ~;tl·

~.

~-

-100
HL

% eRROR" 1+

'as

'os -+ &'OS

Error Due to Switch ON Resistance (rOS)
Figure 6

80

<

-.!:

70

~ 60

a:
0
-

if

rr

50
40

J

30

-

20
10

iGT
~'

~.

~.

~DGI72

-16

-12

-8

fI- ~I~~!!;;;

-1.-

DG200

-4

o

12

4

16

VOLTAGE IV)

FET Switch Error Currents
Figure 4

The JFET as a Switch
A suitable driving circuit must be considered when assessing
the performance of the JFET as a switch. Such a circuit is
shown in Figure 5.

~

.::.r--o °1

s,

+10V

V,N

G,

VS1G " tl0V

ON

-20V

I!=;=
0,

~

G,

The suggested driving circuit of Figure 5 eliminates t>rnS at
low frequencies. The typical positive supply voltage is + I 0 V
and the typical negative supply voltage is -20 V. In order
for VGS to change, current must flow through Q2, which is
ON. There are only two possible current paths through Q2;
(I), through Q3, which is OFF and subject only to variations
in leakage current, or (2), into the gate of QI, which is also
subject to leakage current. Since both paths through Q2
provide only negligible changes in VGS, their effect in the
circuit may be ignored. As the switching frequency is increased, capacitive reactance will provide lower impedance
paths, so that some degree of funs is possible. Thus two
conditions contribute to t>rnS = 0 in the circuit. First,
VSIG ~ VG I, due to the low impedance between these
points. Second, the output impedance of Q3 (driver output)
is very large when compared to the RON of Q2.
When VIN is +10 volts, Q2 is OFF and Q3 is ON; G 1
is at -20 volts and Q] is OFF. In Figure 7, note that QI will
remain OFF only so long as VS1G > (VGI - VGS(off)'
VGS(off) is a negative voltage for an N-channel FET; thus
the negative analog signal is limited by the VGS(off) of Q]
and the negative supply (VG I ~ -20 V).
The ON condition is also shown in Figure 7. gns is constant
because with VG ] ~ VSIG imposed by the switch control
circuit, VGS ~ O.

,os ros,

19"1

'-

~------------

03

ON

VG1 a!VS1G

OFF

VGl

------

\

\

-20V

Vp

JFET Switch Control Circuit
Figure 5

-'0

Note that QI is an N-channel JFET, Q2 is an enhancementmode P-channel MOS FET, and Q3 is an enhancement-mode
N-channel MOS FET. From Figure 2, VIN of -20 V will

Siliconix

VS1G
\

-'5

> (VG1 -

Vp)

FOR DeVICE TO
REMAIN Off

-'0

-"

E!!

-20V

'0

VSIGIVI

Switch ON Condition
Figure 7

7-87

--

The MOS FET as a Switch

The CMOS Switch

The P-channel enhancement-mode MaS FET is currently
used in more applications than its N-channel counterpart.
The consideration of MaS FET switch performance will
thus center on P-channel devices.

As noted previously, the typical PMOS switch circuit will
exhibit a variation in ON conductance as the analog voltage
is varied. This undesirable characteristic can be overcome by
paralleling P- and N-channel FETs, as shown in Figure lOA.
For the ON state, the N-channel gate is forced positive and
the P-channel gate is forced negative. Figure lOB shows the
combined conductance of the two FET switches. The integrated combination of N-channel and P-channel devices on a
common substrate is referred to as complementary MaS
(CMOS).

The ON and OFF conditions of the MaS FET are analyzed
in Figure 8. When the device is in the ON stage, note that the
FET begins to tum ON when VSIG (VS or VO) becomes
VGS(th) volts more positive than VG (= -20 V).
+lDV
B

I_ANALOG VOLTAGE RANGE_

I

s<>-:lir

r

I

D

1
I
I

1

1
1

G

1
1

1

,#

I"~

,-4<::

lOS (-10V)

-'0

-20

I
I
I

CHANNEl-TO-BODY
DIODE BECOMES
FORWARD-BIASED

(A)

1/
1
+'0

,

VS1GfVl
9

OS

PMOS Channel Conductance ('OS) vs Signal VoltagB
Figu,e 8

=-

DOS OF CMOS

fOS

Figure 8 also indicates that at any given point along the
gos vs VSIG curve, a unique value of gos will be obtained.
Assume that a battery is inserted between the source and the
gate, with the source clamped to the body as shown in
Figure 9.

~B

/B'

~~~~S~trD------~

°1

J;,ov~rf

1

-'5

-'0

..

-5

+'0

+'5

...·SIG

T_____________'________---'j"L

....V_SIG__

P-MOS

I

"Floating" Battery and Clamped Sou,ca
Figure 9

N-MOS

VG

-15V

+15V

ON

I VG

+15V

-15V

OFF

I
I

(B)

A constant voltage between source and gate will produce a
PARALLEL P-MOS AND'N-MOS (CMOS)
constant value of gos vs VSIG , provided that the body-toOFF CONDITION
source voltage is also constant. In a MaS FET, variation of
DS 'os
VG IN-TYPE)" -15V,
the body-to-source voltage will also cause a modulation of
VG (P-TYPE) • +1SV,
gOS' To further complicate the picture, several MaS FETs
/e,
will have a common body when they are integrated on a
single chip. Finally, the construction of a "floating battery"
CHANNEL-TO-BODY
circuit is difficult. Thus MOS FEr switch designers currently ~~;~N~~rL~-:"~DV
DIODE OF f:- TYPE
DEVICE FORWARD
DEVICE FORWARD
C?pe with the problem of L\.rOS by specifying rOS for a BIASED
BIASED
given switch at several points over the entire analog volt- -~~---r---.---+---;---r---,...t..=
10
15
--5
age range.
-'0

,

•

o-

-,.

Referring to the switch in the OFF condition (VG = +10 V),
it is apparent that no problem will exist until the source-tobody or drain-body diode becomes forward-biased.

7-88

Siliconix

(C)

Characteristics of CMOS Devices
Figu,e10

The OFF condition for the CMOS deVIce wIll be main tamed
so long as the channel-Io-body diodes do not become forward-biased, as shown in Figure IOC.
The major advantages the CMOS construction technique
makes to analog switching are:
• Lower rOS vanation with analog signal characteristics,
similar to the performance of a junction FET .
• Analog signal range extends to + and - supply voltages.
For instance, using the same ± 15 V supplies tYPIcal of
operational amplifiers, the signal-handling capability of
the syste111IS limited by the op amp, /lot by the slVllch.
Summary of FET Switch Performance and Tradeoffs

v-",

"~
~

100

--

-

u
Z

~

in

iii

lon

-15V

1!!

TA=25C

/

/

/

/

CMOS (DG2CO)

cz:
V~
~..:

<.,()~

/

.."

,0+/

/
001%

01%

'"

Tolerable level of t.rOS and rOS
Figure 12

r-

JFET (OG181, 184, 187, 190)

JFET !DGlao. 183, 186, la9}

~

/

ALLOWABLE ERROR IN VL

I

10

/

//

.#+ ..

/

0001%

CMOS (OG300 SEAIES)

,

~

-----

.........JFET (DalB2, 185, 18a, 191)

0

.."

~lpMOS (oOll2)

CMOS (OGlOl)

..,--

'"z

I

/
,-y
.
,~

/

V+ '" t15V

'-

g

laOCH

IOOH

Figure II compares the performance of three ;wltch types
wIth respect to IDS(on) vs VSIG' If one examInes the rDS
charactenstlcs of the mtegrated sWltchlllg CIrcuits DG 172
and DG 181, thele may be a tendency to dIsmISS the DG 172
on the baSIS of Its apparent IIlfenor performance

,.

The curves in Figure 12 define the maximum rOS (or &OS)
which can exist for a given allowable error percentage with
a fixed value of R L. Recall that in the circuit in Figure 3, a
resistive load of 200K n was assumed. If it is also assumed
that an error level of 0.1 % is tolerable, then rOS =200 n is
the maximum allowable switch resistance. On the other
hand, if settling time is not critical, then an RL of I megohm,
yielding rOS = IK n is permissible.

In situations where setthng time is indeed a design consideration, the circuits in Figure 13 will provide an overview of
the exact nature of settling time for V2 (=V0 at turn-OFF
and turn-ON. For a turn-ON SIgnal, CL charges through rOS'
During turn-OFF, C'L dIscharges through RL' For a system
error level of 0.1%, RL = 1000 rOS; therefore, the maximum
settling time for V2 occurs during turn-OFF.

1

-lS

-10

-5

10

15
V,

Vo - ANALOG SIGNAL VOL rAGE (VOL lSI

t

Performance of Three F ET Switches
Figure 11

In reality, the companson between the monolithIc DG 172
and the hybrid DG 181 is not clear-cut. Imtial Clfcuit design
considerations must determine what degree of error can be
tolerated by the application in terms of t.rOS and rOS' Once
this error factor has been determined, the designer should
contact a switch manufacturer for applications assistance in
selecting the best switch for his purpose, in terms of both
rDS and cost From thiS vlewpolllt, the slllgie-chlp DG 172
will perform creditably in applications where &OS and rOS
error are not critical, and the device costs considerably less
than the DGI81.

V,

sw

'os

R,

CD

Cs

OPEN SWITCH CAPACITANCE

V,

t

To amplify the preceding point, consider the definition of
the tolerable level of &OS and rOS'

Siliconix

-

V,
sw

FCs

'os

C~ ~

CLOSED SWITCH CAPACITANCE

Switch Settling Time Equivalent Circuits
Figure 13

(Cont'd)

7-89

I

Switch Capacitance

.....

v,

V2

SW

'os
;:

+

*es

eo

"sTRAV

The simplified representation of switch capacitance shown
in Figure 13 can be used to provide a very good estimate of
what problems (if any) will be caused by switch capacitance
in a given application.

OPEN SWITCH CONTAINING STRAY CAPACITANCE
CL .. Co + eSTRAY

V,

V2

sil
VSIG

+

'os
;:~

eo ~

*es

In general, the lower the switch capacitance the better the
switching time and high-frequency isolation performance_
The subjects of switching time and high-frequency isolation
are covered in other Application Notes in this series_

eSTRAY

In general, capacitance is proportional to the active area in a
FET chip, prior to bonding onto a header. Additional stray
capacitances are introduced when the leads are brought out
through the device package. Thus, as lower rOS (higher gOS)
is required, the active area is generally increased to obtain
that parameter. The increase in area leads to an increase
in capacitance.
The foregoing statements are true so long as one is dealing
with a given device type. However, in transition from a JFET
to a PMOS device, a significant difference will be observed
in the active areas required for a given rOS. Figure 14 compares the area of a JFET (from the hybrid DG181 circuit)
and the monolIthic PMOS circuit of all 4 switches of a
OG 172. Note that the rDS for the JFET is approximately
one-third that of the total PMOS device, while the active
PMOS area is almost three times greater than that of the
JFET. Yet the ratio ofPMOS·to-JFET capacitance is almost
2: I. For the single OG 172 switch the comparison to the
JFET is a larger rDS( on) for the smaller area.

CLOSED SWITCH CONTAINING STRAY CAPACITANCE

Switch Settling Time Equivalent Circuits
Figure 13

=

Consider a switch with Cs Co = 3 pF, for an application
requiring 0_1 % accuracy with 5 !Jsec settling time. A typical
stray capacitance (C IN for an op amp) may be 6 to 7 pF.
Therefore, CL =3 pF + 7 pF =10 pF. Resistance loads, RL'
of lOOK n, 50K n, and 25K n are considered for the switch.
The time required for an RC system to settle to within 0.1 %
of its final value is 6.9 time constants (6.9 RC). Table 1 OGI72 (ALL 4 SWITCHESI
MOS-FET (PMOSI
shows the RL and rOS values necessary to satisfy a number
of settling time specifications. From Table I, it is apparent
that so long as R L .;;; 12K n, the desired settling time of
5 !Jsec will be achieved.

TABLE I

25K 25
50K 50
·72K 72
lOOK 100

10
10
10
10

tON (V21"
(0.1% settling timel
(nsecl

tOFF (V 21"
(0.1% settling timel

1.72
3.45
5.00
6.90

1.72
3.45
5.00
6.90

34.0
MILS

(Jlsecl

OG181
JFET

l

12.9
MILS

'MaK imum R L for tset = 5 Jlsee

., Does not include delav times
1--14.4MILS-I

If cost is a design constraint, it is wise to make a close analysis of actual system switch requirements. Too often, designers buy unnecessary performance capability. In Table I, the
switch with rOS = 25 n costs nearly twice as much as does
the switch with rOS = 50 n, yet either switch will meet the
5 !Jsec settling time specification.

7-90

!-13.7 MILs-l

'OS = 42.1l

'os=15.1l

AREA = 489.6 MIL 2

AREA = 176.7 MIL2

Co

= 10pF

Co = 6pF

Active Area Comparison of PMOS and JF ET Switches
Figur.14

Siliconix

J

Switch Comparison
A comparison between the characteristics of the three types
of JFET switches is made in Table II.

This Application Note has surveyed the characteristics of
FET switches and their associated drivers. In considering the
FET as an analog switch, discussion has largely centered on
the devices themselves, including specific load problems and

applicable driver circuits. Total switch performance is a
function of the switch and the switch driver. Typically, high·
performance switch drivers require numerous switching
transistors. When discrete devices are considered, the total
parts count will be high and the cost will be prohibitive.
From the standpoint of cost, improved performance, and
smaller size, the integrated circuit FET switch and driver is
often the superior choice.

TABLE II
Switch
Tvpe

Analog Signal
Range

.

'OS

LlrOS

Leakage,
10 0 '15

PMOS

(V.- VGS(th))  1 MHz.)
Low crosstalk
High "Off" Isolation
Excellent phase linearity
High speed switching « 1 ns.)
freedom from switch "popping"
Small size
Direct control by digital gates
Use of DC coupling only

The size of a complex audio switching array can be greatly
reduced by using IC analog switches. The prototype array
is an 8x2 stereo crosspoint switch mounted on a 4x7 inch
board. Other switch configurations may be fabricated with
little effect on the switch characteristics. This single board
can replace a score of rotary switches and the bundles of
audio cable often found in audio mixers. Furthermore,
ground loop problems are reduced by eliminating the cable
bundles.
Siliconix SD5002s were chosen because of low "on" resistance, low switch capacitance, and very fast switching
times. The National Semiconductor LF347 quad op-amp
was chosen for its excellent audio characteristics in a quad
package. 'I\vo LF347s are used in this switch providing a
summing and output amplifier for each of four channels.
The SD5002s are held "normally open" by biasing the
switch gates to ground potential through 10K ohm resistors. For any switch configuration, the appropriate
switch( es) are closed by biasing the appropriate gate(s) to
the positive voltage supply. In this circuit pairs of switches
are controlled together to affect the left and right channels
of a stereo input simultaneously. This is accomplished
simply by tying the applicable switch gates together and
using a common bias resistor. The ability to directly interface the SD5002 gates to digital integrated circuits opens
up immense opportunities to the design engineer for
switch control.

Silicanix

7-105

-

SUMMING
NODE FROM
7 OTHER SWITCHES

LF347
CHANNEL 1
LEFT INPUT BUS

SUMMING AMP
Rio 7SK

OUTPUT AMP

RL

CHANNEL 1
RIGHT INPUT BUS

0--1

...1_NP-1U...
T_N_O_D_E_-'\R"SIlr--;;r._ _O
51 S

~;~

TSK

INPUT NODE

D

t
I
I

"··.--::1::-21r.S;--o

D 9

."'.

7RSK
S

O)--Ir----~

RA75K

I

I+V)-o-::::'
CHANNEL 2

I
I

'~::i:
~=
I!.

CHANNEL 2
LEFT INPUT 8US

RIGHT INPUT BUS

D

I

RL

RL

11 G

I
L~~

-

S~~~Ec:. ~~~;C~~~M

RO Goon

I SUBSTRATE I_V)
__ J2
FIGURE 1

INPUTS

RSS
SWITCH ""'::-t---l~ --;-"IM.--1-INPUTS

INPUT
BUSSES

S05002S

SUMMING ~-I,--_---i~1
NODES

LEFT

RIGHT

LEFT

CHANNEL
A OUTPUTS

FIGURE 2

7-106

RIGHT

CHANNEL
B OUTPUTS

Silicanix

Figure 1 shows how a single SD5002 is configured as a 2xl
stereo switch. Figure 2 shows how the circuit can be
expanded into a switch matrix. Eight SD5002s are required
to construct the 8x2 stereo matrix array. One RL is
required for each channel input for termination while
separate RSs are employed to feed the signal from the
inputs to the various switches. An input bus is consequently formed at the junction of these resistors.
The summing nodes are located at the inverting inputs of
the summing amplifiers. The SD 5002 drains are connected
to these summing nodes. A larger array will cause reduced
system performance due to longer lead lengths and
increased circuit capacitance. Nevertheless, large matricies can be configured with little performance compromise
because of the low initial switch capacitance. RL's value
should reflect the value of the source impedance. Deletion
of RL will seriously degrade crosstalk and off isolation performance while lower values of RL will improve these specifications. RC may be adjusted for a wide range of system
gain while a value of about 150K ohms will set the circuit
to unity gain. RD sets the value of the output impedance
and if the switch is to feed a high impedance load, RO
should be included to maintain system performance.
Electrolytic and mica capacitors are used on the circuit
board for bypassing the two power supply voltages. Supply
voltage bypassing will reduce both high and low frequency
noise and help stabilize the system. The entire circuit
should be well shielded particularly if it will be exposed to
strong RF or power line fields. Conductors carrying high
currents should be kept away from the circuit. Double

sided PC board should be used creating a ground plain on
the component side as an additional precautionary
measure.
Table 1 shows the switch performance of the 8x2 crosspoint configuration. RL was set to 10K ohms, reflecting the
high impedance of the test oscillator's output. Regulated
power supply voltages of plus and minus 9 to 15 volts may
be used. The signal voltages should be kept under about 3.5
volts PTP to maintain switch performance.

TABLE 1
Frequency

Crosstalk

"Off" Isolation

%THD

(Hz.)

50
100
200
500
IK
2K
5K
10K
20K
50K
lOOK

-74db.
-74
-74
-74
-74
-73
-70
-67
-62
-55
-50

-75db.
-75
-75
-75
-75
-74

-71
-68
-62
-55
-49

.006
.005
.004
.003
.003
.003
.003
.004
.006
.020
.045

Signal voltages: 3 volts P.T.P.
supply voltages: + and - 12 volts

-Siliconix

7-107

NOTES

Siliconix

Worldwide Sales Offices _

I

Siliconix

Worldwide Sales Offices
United States
CENTRAL
Siliconix Incorporated

1327 Butterfield Rd.,
Suite 616
Downers Grove, IL 60515
(312) 960-0106
TWX: 910-695-3232

Siliconix Incorporated

Two King James South,
Suite 143
24650 Center Ridge Road
Westlake, OH 44145
(216) 835-4470
TWX: 810-427-9258

Siliconix Incorporated

3310 Keller Springs Road
Suite 120A
Carrollton, TX 75006
(214) 385-4046/4047
TWX": 910-860-9262

EASTERN
Sillconix Incorporated
31 Bailey Avenue
Ridgefield, CT 06877
(203) 431-3535
TWX: 710-467-0660

Siliconlx Incorporated
395 Totten Pond Road
Waltham, MA 02154
(617) 890-7180
tWX: 710-324-1783

Sillconlx Incorporated

Cranes Roost Office Park
311 Whooping Loop
Altamonte Springs, FL 3270'
(305) 831-3644
tWX: 810-853-0320

NORTHWESTERN
Siliconix Incorporated
2201 Laurelwood Road
Santa Clara, CA 95054
(408) 988-8000
tWX": 910-338-0227

Sillconix Incorporated

309 Inverness Way, South
SUite J
Englewood, CO 80112
(303) 799-1575
tWX": 45-0228

SOUTHWESTERN
Sillconlx Incorporated
17821 E. 17th Street
Suite 240
Tustin, CA 92680
(714) 544-8378/7275
TWX: 910-595-2643

International
European
FRANCE
Sillconix S.A_R.L.

Centre Commercial de L'Echat
Place de l'Europe
94019 Creteil Cedex
Tel: (1) 43.77.07.87
TLX: Siliconix 230389F
FAX: (1) 43.39.11.71

WEST GERMANY
Sillconlx GmbH

Johannesstrasse 27
0-7024 Filderstadt-l
Postiach 1340
Tel: (0711) 702066
FAX: (0711) 7061 50
TLX: 7-2555533

FAR EAST
HONG KONG
Sillconix (H.K,) Ltd.
5th Floor
Liven House
61-63 King Yip Street
Kwun Tong, Kowloon
TEL: 3-427151
TLX: 44449S1 LXHX

JAPAN
Nippon Sillconix
Incorporated

1-1 Uchlsalwai-Cho 2-Chome
Chiyoda-Ku, TokYO 100
TE[: (03) 506-3470
TLX: 23~2739 NSIXJ

Siliconlx GmbH

Klrchfeldstr. 4
0-8025 Unterhaching
Munich
Tel: 089-611-4091
TLX: 528305

SCANDINAVIA
Siliconix. Sweden Ltd.
Box 569
S17526 Jlirfalla
Sweden
TEL: (0) 758 12610
TLX: 16404

UNITED KINGDOM
Sillconix Ltd.

3 London Road
Newbury, Berks
RG131JL
TEL: ~0635130905
FAX: 0635 34805
TLX: 49357

ITALY
Sillconix (Italy) Ltd.
Via Vincenzo Monti 8
20123 Milano
TEL: (02) 345 22 11
TLX: 331837

Silicanix

8-1

u.s. and Canadian Sales Representatives
U.S. Sales
Representatives
ALABAMA
Huntsville (35815)
Rep Inc.
P.O. Box 4889
11535 Gilleland Rd.
(205) 881-9270
TWX: 810-776-2102

ARIZONA
Tempe (85282)

Quatra Associates, Inc.
4645 S. Lakeshore Drive
Suite 1
(602) 820-7050
TWX: 910-950-1153

CONNECTICUT
Cheshire (06410-0160)
Scientific Components
1185 South Main Street
(203) 272-2963
TWX: 710-455-2078

FLORIDA
Altamonte Springs
(32701)
llemtronic Associates
657 Maitland Ave.
(305) 831-8233
tWX: 810-854-0321

Ft. Lauderdale (33309)
Semtronlc Associates
3471 Northwest 55th SI.
(305) 731-2484

Clearwater (33516-2248)
Semtronic Associates
1467 S. Missouri Ave.
(813) 461-4675

GEORGIA
lIIcker (30084)

Rep Inc.
1944 Cooledge Road
Suite 1
(404) 938-4358
TWX: 810-766-0822

ILLINOIS
Des Plaines (60018)

Electron Markeling Corp.
3158 Des Plaines Ave.
Suite 109
(312) 298-2330
TWX: 910-233-0183

INDIANA
Indianapolis (46240)
Wilson Technical Sales, Inc.
P.O. Box 40699
4021 W. 71st Street
(317) 298-3345
tWX: 910-997-8120

IOWA
Cedar Rapids (52403)
Electromec Sales, Inc.
1500 2nd Ave. S.E.
Suite 205
(319) 362-6413
tWX' 910-525-1342

KANSAS
Overland Park (66207)
PMR, Inc.
5760 W. 95th St.
Suite 140
913) 381-0004
316) 684-4141

NEW YORK
Endwell (13760)

Tri-Tech ElectroniCS, Inc.
3215 E. Main Street
(607) 754-1094
TWX: 510-252-0891

FayeHevllle (13066)

Tri-Tech Electronics, Inc.
6836 E. Genesee Street
(315) 446-2881
tWX: 710-541-0604

Fishkill (12524)

Tn-Tech ~Iectromcs, Inc.
14 Westview Drive
(914) 897-5611

1

MARYLAND
Columbia (21046)

E. Rochester (14445)

Tri-Tech Electronics, Inc.
300 Main Street
(716) 385-6500
tWX: 510-253-6356

Pro Rep
8310 GuiHord Rd.
(301) 992-7460
TWX: 710-862-0862

Melville (11747)

MASSACHUSETTS
Melrose (02176)
Pro Comp Sales
One West Foster Street
Suite 10
(617) 665-2340
TLX: 910-380-9030

MICHIGAN
Brighton (48116)

A. P. ASSOCIates
9903 Webber
(313) 229-6550
TLX: 287310 (APAIUR)

MINNESOTA
Bumsville (55337)

Electromec Sales Inc.
101 W. Burnsville Pkwy.
(612) 894-8200
TWX: 910-576-0232

MISSOURI
Si. i.ouis jii3i4iij

PMR, Inc.
11710 Administration Dr.
Suite 2
P.O. Box 28708
(314) 569-1220
TWX: 910-764-0881

NEW JERSEY
Marlton (08053)
B.G.R. Associates
Evesham Commons
525 RI. 73
Suite 100
(609) 983-0200
TWX: 710-990-5086

Teaneck (07666)
R. T. Reid Associates
705 Cedar Lane
(201) 692-0200
twX: 71 0-990-5086

R. T. Reid Associates
20 Broadhollow Rd.
Suite 3001
(516) 351-8833
TWX: 990-997-3030

NORTH CAROLINA
Raleigh (27607)

Rep Inc.
7406 F Chapel Hill Road
(919) 851-3007
tWX: 810-726-2102

CharloHe (28212)
Rep Inc.
Independence Office Park
6407 Idlewild Rd., Ste. 226
(704) 563-5554
TWX: 810-726-2102
TLX: 821765

OHIO
Cleveland (44143)

Arthur H. Baler Company
16 Alpha Par k
(216) 461-6161
tWX: 810-427-9278

Dayton (454141

Art~ur H. Baier Company

4940 Profit Way
(513) 276-4128
twX: 810-459-1624

OKLAHOMA
Tulsa (74145)
MREP tompany
7966 East 41 st Street
Suite 7E
(918) 665-3562

OREGON
Beaverton (97005)
Blair Hirsh Co., Inc.
4855 SW Ridgecrest #211
(503) 641-1875

TENNESSEE
JeHerson City (37760)

Rep Inc.
P.O. Box 728
113 So. Branner Ave.
(615) 475-4105/9012/9013
TWX: 810-570-4203

TEXAS
Dallas (75243)

MREP Company
13405 Floyd Circle
Suite 110
(214) 669-9706

Grapevine (76051)

MREP Company
P.O. Box 487
403 E. Wall
(817) 481-7502/7503 &
(817) 488-6583/6584
TWX: 910-350-5298

Missouri City (77459)
MREP Company
1306 FM 1092
Suite 208
(713) 216-0798

Houston (77055)
MREP Company
9440 Old Katy Road
Suite 106
(713) 461-4197

Round Rock (78681)

MREP Company
850 S. Great Oaks Blvd.
Suite 120M
(512) 244-6755

UTAH
Sail Lake City (84115)
Sage Sales
3349 South Main Street
(801) 467-5451
TWX: 910-925-5153

w''!S!!!N!:TOP!
Lynnwood (98036)

Blair Hirsh Co., Inc.
P.O. Box 2250
19410 36th Avenue West
SUite 106
(206) 774-8151
tWX' 910-977-0131

WISCONSIN
Wauwatosa (53226)
Larsen Associates
10855 West Potter Road
(414) 258-0529
TWX: 910-262-3160

canadian Sales
Representatives
Islington, Ontario
IM9B6E3)

!>ipe Thompson, Ltd.
5468 Dundas SI. W.
Ste.206
(416) 236-2355
tWX: 610-492-4367

North Gower, Ontario
Pipe Thomspon, Ltd.
(613) 258-4067

8-2

Siliconix

U.S. Distributors
ALABAMA
Huntsville (358051
Hamilton/Avnet #23
4940 Research Drive
(205) 837-72tO
TWX: 810-726-2162

Huntsville (35801)
Marshall Industries
3313 Memorial Pkwy.
(205) 881-9200

Huntsville (35805)

Pioneer/Huntsville
4825 University Square
(205) 837-9300
tWX: 810-726-2197

ARIZONA
Phoenix (85023)

Wyle laboratories-EMG
17855 N. Black Canyon Hwy.
(602) 249-2232
tWX: 910-951-4282

Temp,e (85281)

Hamllton/Avnet, #04
505 South Madison Dr.
(602) 231-5100
twX: 910-950-0077

CALIFORNIA
Anaheim (92807)

Zeus West, Inc.
1130 Hawk Circle
(714) 632-6880
TWX: 910-591-1696

Canoga Park (91304)
Marshall Industries
8015 Deering Ave.
(818) 999-5001
TWX: 910-494-4821

Chatsworth (91311)
Hamllton/Avnet #48
9650 DeSoto Ave.
(818) 700-6500
TWX: 910-321-3639

EI Segundo (90245)

Wyle DIStributIOn ~roup
451 E. 124th Avenue
(303) 457-9953
TWX. 910-936-0770

Irvine (92714)

Wheatridge (80033)

Marshall Industries
17321 Murphy Ave.
(714) 660-0951
TWX' 910-595-1969

Irvine (92714)

Wyle laboratorles-EMG
17872 Cowan Ave.
(714) 863-9953
TWX. 910-595-1572

Milpitas (95035)
Marshall Industries
336 los Caches
(408) 943-4658
TWX: 910-339-9298

Ontario }91764)

Hamilton Avnet #49
3002 E. 'G' Street
(714) 989-8309
twX 910-321-2806

Reseda (91335)

Jan Devices
6925 Canby, Bldg. 109
(213) 708-1100
TWX: 910-997-1130

Sacramento (95348)
Hamilton/Avnet #35
4103 Northgate Blvd.
(916) 920-3150

San Diego (921231
Hamilton/Avnet, #02
4545 Viewridge Ave.
(619) 571-7510
TWX: 910-335-1216

San Diego (92123)

Chatsworth (91311)

Wyle Laboratories-EMG
9525 Chesapeake Drive
(619) 565-9171
TWX: 910-335-1590

Costa Mesa (92626)

Wyle Distribution Group
3000 Bowers Avenue
(408) 727-2500
tWX: 910-379-6480

Avnet Electronics # 71
20501 Plummer
(818) 700-2600
Avnet ElectrOniCs
350 McCormick Ave.
(714) 754-6111
TWX: 910-595-1928

Costa Mesa (92626)

Hamilton Electro Sales, #29
3170 Pullman Street
(714) 641-4100
TWX: 910-595-2638

Culver City (90230)

Hamilton Electro Sales, #01
10912 W. Washington Blvd.
(213) 558-2121 or
(714) 522-8200
TWX: 910-340-6364

Thornton (802411

Wyle laboratorles-EMG
124 Maryland Street
(213) 322-8100
TWX: 910-348-7140

Santa Clara (95052)

Sunnyvale (94086)
Bell Industries
1161 No. Fairoaks Ave.
(408) 734-8570
TWX. 910-339-9378

Sunnyvale (94086)
Hamilton/Avnet #03
1175 Bordeaux Avenue
(408) 743-3300
tWX: 910-339-9332

COLORADO
Englewood (80111)

Bell Industries
8155 W. 48th Avenue
(303) 424-1985
tWX' 910-938-0393

CONNECTICUT
Danbury (06810)
Hamilton/Avnet, #21
Commerce Drive
Commerce Park
(203) 797-2800
TWX: 710-456-9974

Milford (06460)
Falcon Electronics
5 Higgins Drive
(203) 878-5272
TWX: 710-462-8407

Wallingford (06492)
Marshall Industries
20 Sterling Drive
Barnes Industrial Park
(203) 265-3822
TWX: 910-997-5197

FLORIDA
Altamonte Springs
(32701)
Pioneer Electronics
221 North Lake Blvd.
(305) 834-9090
tWX: 810-850-0177

Deerfield Beach (33444)

GEORGIA
Norcross (30092)

Hamilton/ Avnet, # 15
5825 Peachtree Corners E-D
(404) 447-7500
TWX: 810-766-0432

Norcross (30093)
Marshall Industries
4364B Shakelford Road
(404) 923-5750
TWX: 810-766-3969

Norcross (30093)

Pioneer Electronics
5835 "B" Peachtree Corner
(404) 448-1711

ILLINOIS
Bensenville (60106)
Hamilton/Avnet, #10
1130 Thorndale Ave.
(312) 860-7780
tWX: 910-227-0060

Elk Grove Village (60007)
GBl/Goold Electronics
610 Bonnie lane
(312) 593-3222

Elk Grove Village (60007)
Pioneer/Chicago
1551 Carmen Orive
(312) 437-9680
TWX: 910-222-1834

INDIANA
Carmel (46032)
HamiitonfAvnet, #28
485 Gradle Drive
(317) 844-9333
TWX: 810-260-3966

Pioneer Electronics
674 S. Military Trail
(305) 771-8377
twx: 510-955-9653

Indianapolis (46278)

Ft. Lauderdale (33309)

Indianapolis (46250)

Hamilton/ Avnet, # 17
6801 N.W. 15th Way
(305) 971-2900
TWX: 510-956-3097

St. Petersburg (33702)
Hamilton/Avnet, #25
3197 Tech Drive No.
(813) 576-3930
TWX: 810-863-0374

Winter Park (32792)
Hamilton/ Avnet
6947 UniverSity Blvd.
(305) 628-3888
TWX: 810-853-0322

Winter Park (32789)
Milgray Electronics
1850 lee Avenue
(305) 647-5747

Hamilton/Avnet, #06
8765 E. Orchard Road
Suite 708
(303) 740-1000
TWX: 910-931-0510

Siliconix

Marshall Industries
6990 Corporate Drive
(317) 297-0483
Pioneer/Indiana
6408 Castleplace Drive
(317) 849-7300
TWX: 810-260-1794

IOWA
Cedar Rapids (52404)
Hamilton/ Avnet
915 33rd Ave. SW
(319) 362-4757

KANSAS
Lenexa 166214)

Marshall ndustries
8321 Melrose Drive
(913) 492-3121

Overland Park (66215)
Hamilton/Avnet, #58
9219 Quivlra Road
(913) 888-8900
TWX: 910-743-0005

8-3

u.s.
MARYLAND
Columbia (210451

Hamilton/Avnet, #i2
6822 Oak Hall Lane
(30~ 995-3500 (MD)
(301 621-5410 (DC)
TW : 710-862-1861

GailhersburQ (20760)
Pioneer/Washington
9100 Gaither Road
(301) 921-0660
TWX: 710-828-0545

Gaithersburg (20760)
Marshall Industries
16760 Oakmont Avenue
(301) 840-9450
TWX: 710-828-9748

MASSACHUSETIS
Burlington (01803)
Milgray Electronics
79 Terrace Hall Avenue
(617) 272-6800
tWX: 510-225-3673

Burlington (01803)
Marshall Industries
1 Wilshire Road
(617) 272-8200
TWX: 710-332-6359

Woburn (019601
Hamilton/ Avnet Efectronics
100 Centennial Drive
(617j531-7430 (Sales)
(617 532-3701 (Admin.)

MICHIGAN
Grand Rapids (49508)
Hamilton/Avnet, #67
2215 29th St. S.E. A5
(616) 243-8805

Livonia (48150)

Hamilton/ Avnet, #66
32487 Schoolcraft
(313) 522-4700
TWX: 910-997-5193

Livonia (48150)

Pioneer/Michigan
13485 Stamford
(313) 525-1800
tWX: 810-242-3271

MINNESOTA
Minneapolis (55435)
Industrial Components
5000 W. 78th St.
(612) 831-2666
TWX: 910-576-3153

Minnetonka (55343)
Hamilton/Avnet, #63
10300 Bren Road, East
(612) 932-0600
TWX: 910-576-2720

Minnetonka (55343)
PIOneer/Twin Cities
10203 Bren Road, East
(612) 935-5444
TWX: 910-576-2738

Distributors (Cont'd)

MISSOURI
Earth City (63045)
Hamilton/Avnet, #05
13743 Shoreline ct.
(314) 344-1200
tWX: 910-762-0606

SI. Louis (63146)

Franklin Electronics
11638 Page Service Drive
(314) 993-5333

NEW HAMPSHIRE
Manchester (03103)

Hamilton/ Avnet
444 E. Industrial Park Dr.
(603) 624-9400

NEW JERSEY
Cherry Hill (08003)
Hamllton/Avnet, #14
One Keystone Avenue
(609) 424-0100
TWX: 710-940-0262

Fairfield (07006)
Hamilton/ Avnet, # 19
10 Industrial Road
(201) 575-3390
TWX: 710-734-4388

Fairfield (07006)

Marshall Industries
101 Fairfield Road
(201) 882-0320
TWX: 710-989-7052
Marshall Industries
102 Gaither Dr., Unit 2
(609) 234-91 00 (NJ~
(215) 627-1920 (PA
TWX: 710-897-136

NEW MEXICO
Albuquerque (87123)
Bell Industries
11728 Linn N.E.
(505) 292-2700
TWX. 910-989-0625

A!!!!!!;!!erq!!e (871 ~~)
Hamilton/Avnet #22
2524 Baylor Drive S.E.
(505) 765-1500
TWX: 910-989-0614

NEW YORK
Buffalo (14202)

Commack (11720)

Falcon Electronics
2171 Jericho Turnpike
(516) 462-6350

East Syracuse (13057)
Hamilton/Avnet, #08
1600 Corporate Circle
(315) 437-2642
TWX: 710-541-1560

Endwell (13760)

Pioneer/Oayton
4433 Interpoint Blvd.
(513) 236-9900
TWX: 810-459-1622

Haup,pauge (11788)

Solon (44139)

Hamllton/Avnet, #20
933 Motor Pkwy.
(516) 231-9800
tWX: 510-224-6166

Hauppauge (11787)
Marshall Industries
275 Oser Avenue
(516) 273-2424
TWX: 510-220-1139

Port Chester
Zeus Components, Inc.
100 Midland Ave.
(914) 937-7400
tWX: 710-567-1248

Rochesler (14623)

Hamilton/ Avnet, # 61
333 Metro Park
(716) 475-9130
TWX: 510-253-5470

Rochester (14623)
Marshall Industries
1260 Scottsville Road
(716) 235-7620
tWX: 510-253-5526
Hamilton/Avnet, #j9
1065 Old Country Road
(516) 997-6868
TWX: 510-221-0676

Woodbury (11797)
Pioneer/Long Island
60 Crossways Park W.
(516) 921-8700
TWX: 510-221-2184

NORTH CAROLINA
Charlotte (28210)
Ploneer/NC
9801-A Southern Pine Blvd.
(704) 527-8188
TWX: 810-620-0366

Raleigh (27604)

Hamilton/Avnet, #24
3510 Spring Forrest Road
(919) 878-0819
TWX: 510-928-1836

OHIO
Cleveland (44105)

Summit Inc.
916 Main Street
(716) 884-3450
TWX: 710-522-1692

Dayton (45424)

Milgray Electronics, Inc.
77 Schmitt Blvd.
(516) 420-9800
TWX: 510-225-3671

Westbury (115901

MI. Laurel (08057)

Marshall Industries
10 Hooper Road
(607) 754-1570
TWX: 510-252-0194

8-4

Farmingdale (11735)

Pioneer/Cleveland
4800 E. 131s1 Street
(216) 587-3600
TWX: 810-422-2210

Dayton (45459)

Hamillon/Avnet, #64
954 Senate Drive
(513) 433-0610
tWX: 810-439-6700

Dayton (45424)
Marshall Industries
6212 Executive Blvd.
(513) 236-8088
TWX: 810-459-1935

Marshall Industries
5905B Harper Rd.
(216) 248-1788
TWX: 810-427-2701

Warrensville Heights
(44128)
liamilton/Avnet, #62
4588 Emery Industrial Pkwy
(216) 831-3500
.
tWX: 810-427-9452

Westerville (43081)
Hamilton/ Avnet, # 79
777 Brooks Edge Blvd.
(614) 882-7004

OKLAHOMA
Tulsa (74129)
Quality Components
9934 E. 21st Street S.
(918) 664-8812

Tulsa (74129)
Hamilton/ Avnet

OREGON
Hillsboro (971231
Wyle Laboratories-EMG
5289 N.E. Elam Young Parkway
Bldg. E-l00
(503) 640-6000
tWX: 910-460-2203

Lake Oswego (97034)
Hamillon/Avnet, #27
6024 S.W. Jean Road
Bldg. C., Suite 10
(503) 635-8836
TWX: 910-455-8179

PENNSYLVANIA
Horsham (19044)
Pioneer Electronics

2f:ii1

r,ihr~lt~r Rn~ti

(215) 674:400ij-TWX: 510-665-6778

Pittsburg (15222)
Hamilton/ Avnet
2800 Liberty Avenue
(412) 281-4150

Pittsburg (15238)
Pioneer/Pittsburgh
259 Kappa Drive
(412) 782-2300
TWX: 710-795-3122

TEXAS
Addison (75001)

Quality Components
4257 Kellway Circle
(214) 733-4300
TWX: 910-860-5459

Austin (78758)
Hamilton/Avnet, #26
1807A W. Braker Lane
(512) 837-8911
TWX: 910-874-1319

Austin (78758)

Wyle Distribution
2120-F W. Braker Lane
(512) 834-9957
TLX: 834-0779

Siliconix

U.S. Distributors (Cont'd)
Austin (78758)

Pioneer Electronics
9901 Burnet Road
(512) 835-4000
TWX: 910-874-1323

Austin (78758)
Quality Components
2427 Rutland Drive
(512) 835-0220
TLl<: 324930

Dallas (75234)
Pioneer Electronics
13710 Omega Road
(214) 263-3168
TWX: 910-860-5563

Dallas (75240)

Zeus Components
14001 Goldmark
(214) 783-7010

Houston (77063)
Hamilton/Avnet, #11
8750 Westpark
(713) 975-3500
TWX: 910-881-5523

Houston (77036)

UTAH
Salt Lake City (84119)

Pioneer
5853 Point West Dnve

Irving (75062)

Hamilton/ Avnet, # 16
2111 W. Walnut Hill Lane
(214) 659-4151
TWX: 910-860-5929

Richardson (75083)
Wyle DistributIOn
1810 N. Greenville Ave.
(214) 235-9953
TWX: 310-378-7663

Richardson (75081)
Zeus Components
1800 N. Glenville
(214) 783-7010
TWX: 910-867-9422

Sugarland (77478)
Quality Components
1005 Industrial Blvd.
At Bournewood
(713) 240-2255
TWX: 910-880-4893

WISCONSIN
Milwaukee (53214)

Hamilton/Avnet, #09
1585 West 2100 South
(801) 972-2800
TWX. 910-925-4018

Marsh Electronics, Inc.
1563 South 101 st Street
(414) 475-6000
TWX: 910-262-3321

Sail Lake City (84104)

New Berlin (53151)

Wyle Laboratones-EMG
1959 South 4130 West
(801) 974-9953

WASHINGTON
Bellevue (98005)
Hamilton/Avnet, #07
14212 N.E. 21st Street
(206) 453-5844
TWX: 910-443-2469

Bellevue (98005)
Wyle Distribution Group
1750 132nd Avenue N.E.
(206) 453-8300
TWX: 910-443-252G

Hamilton/ Avnet, # 57
2975 Moorland Road
(414) 784-4510
TWX: 910-262-1182

CHIP DISTRIBUTOR
FLORIDA
Orlando (32807)
Chip Supply, Inc.
1607 Forsyth Road
(305) 275-3810
TWX: 810-850-0103

Orlando (32817)
Chip Supply, Inc.
7725 N. Orange Blossom Trail
(305) 298-7100

Siliconix

8-5

canadian Distributors
BRITISH COLUMBIA
Burnaby (V5G 4J7t

RAE Inaustrial Elec. td.
3455 Gardner Court
(604) 291-8866
tWX: 610-929-3065
Tll(: 04-356533

ONTARIO
Downsview (M3J 123)
Future Electronics
82 51. Regis Crescent N.
(416) 638-4771
tWX: 610-491-1470

8-6

Mississauga (L4V 1M5)
Hamilton/Avnet, #59
6845 Redwood Drive
(416) 677-7432
twx: 610-492-8867

Nepean CK2E 7L5)

ALBERTA
Calgary CT2E 6Z2)

Hamilton/Avnet
2816 21st Street N.E.
(403) 230-3586

Hamilton/Avnet, #60
2110 Colonade Road
(613) 226-1700
tWX: 0534971

QUEBEC
Pointe Claire (H9R 4C7)
Future Elec.
237 Hymus Blvd.
(514) 694-7710
TWX: 610-421-3251

SI. Laurent (H4S 1M2)
Hamilton/Avnet, #65
2795 Rue Halpern
(514) 335-1000
tWX: 610-421-3731

Ottawa (K2C 3P2)
Future Elec.
Baxter Centre
1050 Baxter Road
(613) 820-8313

Siliconix

European Representatives/Distributors
AUSTRIA
Ing. Ernst Sieiner
Hummelgasse 14
A-1130 Vienna
TEL: 0222/827474/0
TLX 135026

BELGIUM
J P. Lemaire S A.
Av. Limburg Stlrum 243
B-1810 Wemmel
TEL: (02) 460-05-60
TLX: 24610

DENMARK
Dltz Schweitzer A.S
Vallensbaekvej 41, Postboks 5
DK-2600 Glostrup
TEL: (02) 45-30-44
TLX 33527

FINLAND
Instrumentarium Electronics
PO. Box 64
SF 02631 Espoo 63
TEL (358)-0-5281
TLX 124426 HAVUL SF
FAX (358) 524-986

FRANCE
Almex
48 Rue de l.'Aubeplne
B.P. 102
92164 Antony Cedex
TEL' (1) 4 666-21-12
TLX: 250067
Alrodls
40 Rue Villion
69008 Lyon
TEL: (7) 800-87-12
TLX: 380636
Baltzinger Sari
B.P. 183
67042 Strasbourg Cedex
TEL (88) 331852
TLX: 870952F

I.T.T. Multicomposant
38 Avenue Henn Barbusse
B P 124
9223 Bagneux Cedex
TEL: (1) 4 664-16-10
TLX. 270763

GREECE

SCAIB
80 Rue d'Arcuell
94523 Rungls Cedex
TEL: (1) 4 687-12-13
TLX: 204-674F

ITALY

GERMANY
Ditronic GmbH
Julius-Hoelder Str. 42
7000 Stuttgart 70
TEL: (0711) 720010
TLX 7255638
EBV Elektronik GmbH
Dberweg 6
0-8025 Unterhaching
TEL' 089-61105-1
TLX: 524535
EBV Elektronlk GmbH
Alexanderstrasse 42
7000 Stuttgart 1
TEL (0711) 247481
TLX 722271
EBV Elektronik GmbH
Dstrasse 129
4000 Dusseldorf
TEL' (0211) 84846/7
TLX' 8587267
EBV Elektronrk GmbH
Kiebltzrain 18
3006 Burgwedel l/Hannover
TEL: (05139) 5038
TLX: 923694
EBV Elektromk GmbH
Schenckstr 99
6000 Frankfurt M 90
TEL: (069) 785037
TLX: 413590

Composants S A.
Avenue Gustave Elffel
B P. 81
33605 Pes sac Cedex
TEL: (56) 36-4040
TLX: 550696F

Ing. BUro Rainer Konig
Konigsbergerstrasse 16A
1000 Berlin 45
TEL: 030-772-8009
TLX: 184-707

Composants S A.
55 Avenue LoUIS Broguet
31400 Toulouse
TEL: (61) 20-82-38
TLX. 530957

Ing. BUro K.H Dreyer
Albert Schweitzer-Ring 36
2000 Hamburg 70
TEL: (040J 669027
TLX: 216 484

Composants S.A
183 Route de Paris
86000 POltlers
TEL' (49) 88-60-50
TLX: 591525

Ing. Buro K.H. Dreyer
Flensburger Strasse 3
2380 SchleSWig
TEL. (04621) 24055
TLX' 02-21334

Composants S.A.
57 Rue Manoir de Servlgne
21, Route de Lorient
B.P. 3209
35013 Rennes Cedex
TEL. (99) 54-01-53
TLX: 740311

Ultratronik GmbH
Munchner Strasse 6
8031 Seefeld
TEL: (08152) 7090
TLX. 05-26459

General Electronics Ltd
209 Thlvon Street
Nikala, Plreaus GR-184-54
TEL: (1) 4904934
TLX: 212949 GELT GR
Dott Ing. Giuseppe De Mico
S.PA.
20060 Cassin a de Pecchl
Via Vlttono Veneto 8
Milano
TEL: (02) 9520551
TLX: 330869
FAX. (02) 9522227

NETHERLANDS
Koning en Hartman
Elektrotechniek BV
1 Energreweg
2627 AP Delft
PO. Box 125
2600 AC Delft
TEL: 15609906
TLX: 38250
FAX: 15619194

NORWAY
A.S. Klell Bakke

~vre Raellngsvei 20

.0. Box 27
N-2001 Lrllesstr0m
TEL: (02) 83-02-20
TLX: 19407
FAX: (02) 831455

PORTUGAL
Telectra S A.R.L.
Praceta Av Dr. Mario
Moutinho, Lote 1258
1400 Lisboa
TEL: (1) 616221
TLX: 12598

SPAIN
Comerclal Espanola de
Componentes S.A.
Arzobispo Morcilio
24 Oflclna 5
Madnd 28029
TEL: (1) 733-7054/55
TLX. 47010
Redls Logar SA
Lopez de Hoyos
78 DPDD, Madnd 28002
TEL. (1) 4113561
TLX 23967
FAX: (1) 4117423
Redis Logar SA
Aragon 208-210
Barcelona 11
TEL: (3) 2549048

SWITZERLAND
Abalec A.G
Landstrasse 78
CH-8116 Wurenlos
TEL: 01-730-0455
TLX: 59834

UNITED KINGDDM
Abercorn Electromcs Ltd
SUite 1A
17 Waterloo Place
Edinburgh, Scotland EH1 3BG
TEL. 031-557-4700
TLX: 727229
Barlec-Richfleld Ltd.
Foundry Road, Horsham
West Sussex RH13 5PX
TEL: 0403-51881
TLX. 877222
Farnell Electromc
Components Ltd
Canal Road
Leeds LS12 2TU
TEL: 0532-636311
TLX' 55147
Hartech Ltd.
7 West Pallant
Chichester
West Sussex PO 191 TO
TEL' 0243-773511
TLX: 86230
HB Electromcs Ltd.
Lever Street
Bolton BL3 6BS
TEL: (0204) 386361
TLX: 63478
FAX: (0204)
Macro-Marketing Ltd.
Burnham Lane
Slough, Berks
TEL (06286) 4422
TLX: 847945
Semiconductor Specialists
(UK) Ltd.
Carroll House
159 High Street
West Drayton
Middlesex UB7 7XB
TEL: (08954)445522/446415
TLX. 21958

YUGOSLAVIA
Contact: Belram S.A.
83 Avenue des Mimosas
1150 Brussels, Belgium
TEL: 734-33-32/734-26-19
TLX: 21790

SWEDEN
Komponentbolaget NAXAB
Box 4115
S-171-04 So Ina
TEL. 08-985140
TLX: 17912 KDMP
FAX: 08-7645451

Siliconix

8-7

Worldwide Sales Offices
International Representatives/Distributors
AUSTRALIA
NSD Australia
(A Division of HardieTrading Ltd.)
205 Middleborough Road
Box Hill
Victoria 3128
TEL: (03) 890-0970
TLX: M37857

BRAZIL
Cosele Commerclo e Serviclos
Electronicos Ltda.
Rua da Consolacaco, 867
01310 Sao Paulo
TEL: 255-1733
TLX: 1130869-CSEL-BR

HONG KONG
Array Electronics Ltd.
Rm 2001 B Nam Fung Centre
264-298 Castle Peak Road
Tseun Wan
NT
TEL: 0-424131
TLX: 37200 Array HK
CABLE: ARRAYEL
Atek Electronics Co. Ltd.
RM.1302ArgyleCentre,Phasel
688 Nathan Road
Mongkok
Kowloon
TEL: 3-916333/4
TWX: 37119 ATEK HX
Century Electronic Products Co.
Unitllll,ll/F,CenturyCentre
44-46 Hung To Rd.
Kwun Tong
Kowloon, Hong Kong
TEL: 3-420101/2
TLX: 51226 CEPCO HX
CABLE: CENTURYEPC
CSD Central Systems Design Ltd.
(for Gate Array Products)
Onit 507-508 5/F Citicorp Glr.
18 Whitefield Rd.
Causeway Bay
Hong Kong
TEL: 5-701181
TLX: 73990 CSDHX
CABLE: 9994 HK
FAX: 5-701354
Gibb, Livingston & Co. Ltd.
Sungib Industrial Centre
53 Wong Chuk Hang Rd.
Aberdeen, Hong Kong
TEL: 5-558331
TLX: HX73470
CABLE: GIBB HONG KONG

INDIA

LATIN AMERICA

Zenith Electronics
106, Millal Chambers
Nariman Point
Bombay 400021
TEL: 2029464
TLX: 2NTH
Authorized U.S. Agent
Fegu Electronics Inc.
2584 Wyandotte SI.
Mtn. View, CA 94043
TEL: (415) 961-2380
TLX: 345599

ISRAEL
Telsys Ltd.
12 Kehilat Venetsia SI.
Tel Aviv
TEL: (3) 494891
TLX: 032392
FAX: (3) 497407

INDONESIA
Sinar Electnk
Glodok Baru Blok C/120BB
JL. Hayam Wuruk
Jakarta-Barat
Indonesia
TEL: 623243
CABLE: LlONGKINYAMKO

Intectra Inc.
2629 Terminal Blvd.
Mt. View, CA 94043
TEL: (415) 967-8818
TLX: 345545 Intectra MNTV
CABLE: INTECTRA

MALAYSIA
Carter Semiconductor (M)
SON Berhad
Jalan Lapangan Terbang,
Ipon, Malaysia
TEL: 514-033
TLX: MA44050

NEW ZEALAND
S.T.C. (NZ) Ltd.
P.O. Box 26064
10 Margot Street
Epsom, Auckland 3
TEL: 500-019
TLX: NZ21888

PHILIPPINES
Alexan Commercial
812 Elcano Street
Binando
Manila, Philippines
TEL: 405-952
TLX: 27484 CEI PH

SINGAPORE

JAPAN
Tomen Electronics Corporation
1-1 Uchisaiwai-Cho, 2-Chome
Chiyoda-Ku, Tokyo 100
TEL: 81-3-506-3490
TLX: J-23548

KOREA
A-Mee Trading Co., Ltd.
Rm. 302 New Hanil Bldg.
156-1 Yumri-Dong
Mapo-Ku
Seoul
TEL: 716-6883
TLX: 7176728

Carter Semiconductor (s)
PTE Ltd.
07-03 Cuppage Centre
55 Cuppage Road
Singapore 0922 R.O.S.
TEL: 235-6653
TLX: 36443 CARSIN
FAX: 7342449

SOUTH AFRICA
Electrolink (PTY) Ltd.
P.O. Box 1020
Capetown 8000
TEL: 215-350
Tlx, 527-7320

lAlWAN
Don Business Corp.
'6F, No. 33, Alley 24
Lane 251
Nanking East Road
Sec. 5
Taipei, Taiwan
TEL: 766-4515, 760-7801-3
TLX: 25641 DONBC
CABLE: "DONBC" TAIPEI

THAILAND
Choakchai Electronic Supplies
128/22 Rhanon Atsadang
BanQkok 2
Thailand
TEL: 221-0432
TLX: 84809 CESLP T-H
CABLE: SAHAPI PHAT
Dynamic Supply
Engineering R.O.P.
12 Soi Psana I Ekami
Sukhumvit 63
Bangkok 10110
Thailand
TEL: 392-8532
TLX: 8245 DYNASUP
CABLE: DYNASUPPLY

TURKEY
TUrkelek Electronic Co. Ltd.
Hatay Sokak No.8
Ankara
TEL: (41) 18983
TLX: 42120

VENEZUELA
P. Benavides S.R.L.
Avilanas a Rio Edificio
Rio Caribe, Local 9
Caracas
TEL: 52-92-97
TLX: 21801 PBTH

Buseok Electronics
Rm. 423 Ga Yul Gm Dong
Sewoon Sang GA Bldg.
No. 116-4 Jangsa-Dong
Chong Ro Ku
Seoul
R.O. Korea
TEL: 265-5891
TLX: K28742 KPTRDCO

Manufacturing Facilities
lAlWAN
Siliconix (Taiwan) Ltd
Manlle Export Processing Zone
Kaohsiung
TEL: 3615101-4
TLX: 78571235

8-8

HONG KONG

UNITED KINGDOM

Siliconix \H.K.) Ltd.
5/6/7th Foors
Liven House
61-63 King Yip Street
Kwun Tong, Kowloon
TEL: 3-427151
TLX: 4444951 LXHX

Siliconix Ltd.
Morriston, Swansea
SA66NE
TEL: (0792) 74681
TLX: 48191
FAX: (0792) 798401

Silicanix

UNITED SlATES
2201 Laurelwood Road
Santa Clara, CA 95054
TEL: (408) 988-8000
TLX: ~1 0-338-0227



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