1986_Standard Microsystems 1986 Standard

User Manual: 1986_StandardMicrosystems

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INDEX

PAGE

PART NUMBER

3

FUNCTIONAL

5-9

CROSS REFERENCE

10-12

GENERAL INFORMATION
INTRODUCTION

13-16

CUSTOM CAPABILITIES

17-24

QUALITY ASSURANCE & QUALITY CONTROL

25-32

DATA COMMUNICATION PRODUCTS

....

33-262

BAUD RATE GENERATOR

.... 263-290

CRT DISPLAY

. . .. 291-456

FLOPPY DISK/HARD DISK

.... 457-662

KEYBOARD ENCODER

.... 663-678

SHIFT REGISTER

.... 679-688

MICROPROCESSOR PRODUCTS

.... 689-734

ORDERING INFORMATION

.... 735-742

TABLE
OF

CONTENTS

PART NUMBER INDEX
PART NUMBER
COM 1553A
COM 1553B
COM 1671
COM 1863
COM 2017
COM 2502
COM 2601
COM 2651
COM 2661
COM 5016/T
COM 5025
COM 5026/T
COM 5036/T
COM 5046/T
COM 52C50
COM 7210
COM 78808
COM 8004
COM 8017
COM 8018
COM 8046/T
COM 8116/T
COM 81C17
COM 8126/T
COM 8136/T
COM 8146/T
COM 8156/T
COM 81C66/T
COM 8251 A
COM 8502
COM 9004
COM 9026
COM 9032
COM 9046
COM 90C56
COM 90C57
COM 9064
CRT 5027
CRT 5037
CRT 5047

PAGE
35
51
67
83
91
91
99
107
119
265
131
267
265
267
143
145
157
173
179
83
273
275
187
277
275
277
285
289
189
179
205
213
229
235
239
241
243
293
293
301

PART NUMBER
CRT 5057
CRT 7004
CRT 7220
CRT 8002
CRT8002H
CRT 8021
CRT 9006
CRT 9007
CRT 9021
CRT 9028
CRT 9041
CRT 9053
CRT 9128
CRT 9153
CRT 9212
CRT 97C11
FOC 765A
FOC 1791
FOC 1793
FOC 1795
FOC 1797
FOC 7265
FOC 72C65
FOC 72C66
FOC 9216/B
FOC 9229T/BT
FOC 92C36/B
FOC 9238/B/BT
FOC 9239/B/BT
FOC 92C49
FOC 9266
FOC 9267
FOC 9268
FOC 9791
FOC 9793
FOC 9795
FOC 9797
HOC 1100-01
HOC 1100-12
HOC 1100-03
3

-_ ....._ - - -

--_.._----_ ..

-

PAGE
293
303
309
333
347
355
363
369
389
401
417
433
401
433
449
455
459
477
477
477
477
459
475
475
493
497
505
509
513
521
523
539
555
557
557
557
557
573
577
581

PART NUMBER
HOC 1100-04
HOC 1100-05
HOC 7261
HOC 9223
HOC 9224
HDC 9225
HOC 9226
HOC 9227
HYC 9058
HYC 9068
HYC 9078

PART NUMBER
KR 9600
KR 9601
KR 9602
MPU 800
MPU 810A
MPU 830
MPU 831
SR 5015
SR 5017
SR 5018

PAGE
585
589
593
595
599
635
647
655
251
257
261

4
-._--_.. - - - - - - - - -

---

-._----_._-_._-- - - - - - - - - -

_._._._._-

PAGE
665
665
665
691
715
727
727
681
685
685

FUNCTIONAL INDEX
Data Communication Products

5

Data Communication Products CONT.

(2)For future release

OR! Display

VIDEO TERMINAL LOGIC CONTROLLERS

l"M"3' be custom mask programmed

'''For future release

6

CI.! Display CONT.

VDAC'" DISPLAY CONTROLLERS

~DEO~TRIBUTESCONTROLLERS

'May be custom mask programmed
("Also available as ORTBOO2A, B, 0-001 Katakana
ORTBOO2A, B, 0-003, -OlB 5 x 7 dot matrix
VT100 and VT220 are registered trademarks of Digital Equipment Oorp.

(1

("Also available as ORT7004A, B, 0 -003
5 x 7 dot matrix

Microprocessor Products

7

Baud Rate Generator

(')Maybe custom mask programmed (')For future release

Keyboard Encoder

(l)Maybe custom mask programmed (2)For future release

8

~ Floppy Disk/Rard Disk
~~=

.MIW Shift Register

9
.... _... -

....

_-_..._ - - _ . _ - - - - - - - - - -

SMC CROSS
Description
UART (1'12 S8)"

AMI

AMD

Fairchild

S1883'

Harris

Intel

AY 5-1013A

UART (1,2 S8)"
UART (n-Channel)"

General
Instrument

AY 5-1013
S6850'

F6850'

UART (n-Channel)"
UART (n-Channel)'

S1602'

USRT

S2350'

AY 3-1015

HM6402'

AY3-1015

HM6403'

ASTRO
PCI
EPCI

AY2661
8251

USART
Multi-Protocc
USYNRT

S6852'

8251A
F3846'
F3856'
F68488'
96LS488'

IEEE-488

8291/92'

COAX I/F Circuit
LAN Controller
AY5-8116/36

Dual 8aud Rate Gen.

AY 5-3600'

90 Key KB Encoder
CRT Controller
Character Generator

HD4702'
HD6405'

F4702'

Single 8aud Rate Gen.

8275
S8564'

Character Generatorl
Display Controller
82720

Graphics Controller
Video Processor and
Controller
Video Attributes
Controller
Video Terminal Logic
Controller
Shift Register

S2182/3/5

CMOS Microprocessor
CMOS RAM-I/O-Timer
CMOS ROM-I/O
CMOS InpuVOutput
Octal UART
'Functional equivalent.
"Most UART'S are interchangeable; consult the factory for detailed information on interchangeability.

10

REFERENCE GUIDE
Motorola

Signetics

Western
Digital

-

-

-

TMS6011

TR1602

-

-

-

TR1402

NSC858'

-

-

-

-

-

-

-

-

-

-

-

-

TR1983'

-

-

-

-

-

-

-

TR1863

-

-

-

-

-

-

-

-

-

INS1671

-

-

-

-

-

UC1671

MM5303'

SCR1854'

-

INS2651

-

2651

-

-

-

-

MC2661'

-

-

2661

-

-

-

-

-

INS8251

-

-

-

-

TR1983'

2652'

6852'

-

-

SD1933'

MC6BB488'

DP8340/41 ,

fJ.PD8251A

-

2652

SND5025

-

-

-

TMS9914'

WD9914'

-

-

-

-

-

-

fJ.PD7210

-

-

-

-

-

-

-

WD2840'

-

-

-

-

-

-

-

BR1941
BR194314

-

-

-

-

-

-

TMS5001

-

-

TMS9927

-

-

-

-

-

-

-

-

MC14411'

MM30r

-

-

-

MM5740'

-

-

i
MC6845'

DP8350'

-

-

MCM66700'
MC6570

DM8678'

-

2609

I

I
I

Texas
Instruments

2536'

-

I

DEC

-

MC6850'

I

Solid
State
Scientific

-

-

I

NEC

-

-

I

National

-

-

-

-

-

-

-

-

-

-

-

SND5027
SND5037

SND8002

I

I

-

-

-

-

-

-

SCN2674'

-

-

-

-

-

SCN2675'

-

-

-

-

-

-

fJ.PD7220
fJ.PD7220A

-

-

I

-

NS455'

-

-

-

-

-

5024'

-

2532'

-

-

I
I

-

NSC800

-

-

-

-

-

-

I
I
I
I

-

NSC810A

-

-

-

-

-

-

-

NSC830

-

-

-

-

-

-

-

NSC831

-

-

-

-

-

-

-

-

-

78808

-

-

\

I
I

-

-

11

TMS3113'
TMS3114'

-

FLOPPY DISK/HARD DISK
Description
Floppy Disk Controller

SMC
Part #

Fujitsu

FDC1791-02

MB8876

NEC

-

Western
Digital

Intel

-

FD1791-02

-

-

FD1792-02

-

-

FD1793-02

-

Floppy Disk Controller

FDC1792-02

Floppy Disk Controller

FDC1793-02

Floppy Disk Controller

FDC1794-02

-

-

FD1794-02

-

Floppy Disk Controller

FDC1795-02

-

-

FD1795-02

-

-

-

FD1797-02

-

FD1791-02'

M8877

Siemens

Rockwell

SAB-1791

-

-

-

SAB-1793

-

-

SAB-1795

-

-

SAB-1797

-

-

SAB-1791'

-

Floppy Disk Controller

FDC1797-02

Floppy Disk Controller

FDC9791

MB8876'

Floppy Disk Controller

FDC9793

M8877'

-

FD1793-02'

-

SAB-1793'

Floppy Disk Controller

FDC9795

-

-

FD1795-02'

-

SAB-1795'

-

Floppy Disk Controller

FDC9797

-

-

FD1797-02'

-

SAB-179T

-

Floppy Disk Controller

FDC765A

-

fLPD765A

-

Microfloppy Disk Controller

FDC7265

-

fL PD7265

-

8272A

-

-

765A

-

-

Floppy Disk Controller

FDC765A-2

-

fLPD765A-2

-

-

-

-

Floppy Disk Controller

FDC72C65

-

fLPD72065C

-

-

-

-

Microfloppy Disk Controller

FDC72C66

-

fLPD72066C

-

-

-

-

Floppy Disk Data Separator

FDC9216

-

-

FD9216

-

-

-

Floppy Disk Data Separator

FDC92C36

-

-

FD92C32

-

-

-

Hard Disk Controller

FDC7261A

-

-

-

-

Hard Disk Controller

HDC1100-XX

-

-

-

-

HDC9224

-

-

-

-

Universal Disk Controller

fLPD7261A

fL PD7260"

'SMC part will replace cited device with no changes required.
"Functional Equivalent.

12

WD1100-X

-

Innovation in Microelectronic
Technology is the Key to Growth at
Standard Microsystems.
Since its inception, Standard Microsystems has been a leader in creating new
technology for metal oxide semiconductor large scale integrated (MOS/LSI) and
very large scale integrated (MOSNLSI) circuits.
Standard Microsystems' COPLAMOS® silicon gate n-channel process, licensed to
over 15 prominent semiconductor companies, is the defacto standard for high
speed, high density integrated circuits.
COPLAMOS® utilizes a self-aligned, field-doped, locally oxidized structure to eliminate parasitic currents and shunt capacitance, allowing the tight packing of circuitry essential for VLSI, yet with performance rivaling that of bipolar technologies.
In addition, on-chip generation of substrate bias, also pioneered by Standard
Microsystems, when added to the COPLAMOS® technology, results in the ability
to design dense, high-speed, low-power n-channel MOS integrated circuits
through the use of one external power supply voltage.
Another Standard Microsystems' innovation is the CLASp® process. CLASp® provides a fast turnaround, easily programmable semi-custom LSI technology
through the use of ion implantation to define either an active or passive device
ih the matrix of a memory or logic array. This step is accomplished after all wafer
manufacturing steps are performed including metalization and final passivation
layer formation. Thus, the wafer can be tested and stored until customer needs
dictate the application, a huge saving in turnaround time and inventory costs.
These innovations in both process and circuit technology have received widespread industry recognition. In fact, many of the world's most prominent semiconductor companies have been granted patent and patent/technology licenses
covering various aspects of these technologies. The companies include Texas
Instruments, IBM General Motors, ITT, Western Electric, Mostek, Hitachi, Fujitsu,
National Semiconductor, Mitsubishi, NEC, AT&T, Data General, and Oki Electric,
among others.
Over the past few years, scientists and engineers at Standard Microsystems have
been developing a technology to significantly reduce the sheet resistivity of the
gate material used in MOS, dramatically decreasing internal time constants in
MOS devices.

13

This technology replaces the polycrystalline silicon normally used in n-channel
MOS devices with an alternate material, titanium disilicide, This has enabled
Standard Microsystems to become the first semiconductor manufacturer to
market and sell MOSNLSI circuits which employ a metal silicide to replace the
conventional doped polycrystalline silicon layer,
Standard Microsystems is continuing its technological leadership with the introduction of new products utilizing advanced low power n-well and p-well CMOS
processes,

We~ve

Established a Position as the
Industry Leader in Microprocessor
Peripheral Products with a Steady String
of Industry "Firsts".

Innovation at Standard Microsystems extends far beyond new processes,
Standard Microsystems has established a position as the industry leader in microprocessor peripheral products with a steady string of industry "firsts",
Standard Microsystems has continually recognized the need for communication
controllers to handle the latest data communication protocols, As a result,
Standard Microsystems has introduced many new products in the area of data
communications, Among these are the COM2601. the first synchronous receiver/
transmitter for bi-sync protocols, and the COM5025, the first multi protocol
receiver/transmitter for all standard bit and byte oriented synchronous protocols,
including SDLC, HDLC, ADCCP, bi-sync, and DDCMP,
Recognizing the office automation requirement for distributed processing via
local area networks, SMC was the first to sell a monolithic VLSI circuit for Local
Area Network Control, the industry standard COM9026, a complete controller for
token-passing LAN systems, Other areas pioneered by SMC, with the introduction
of unique monolithic controllers, include two important IBM families of computers
with large installed bases and very high growth rate, The COM9064 is the first single controller for the IBM 3270 Coax Type uN' protocol, while the COM52C50 is the

14

first and only single chip controller for the IBM System/3x that is commercially
available in the market.
SMC also has a first in the area of military standards with the COM1553B controller. This device integrates all the functions necessary to implement the MIL-STD1553B communication protocol adopted as a standard by the three branches of
the military in the U.S.
These data communications firsts offer designers cost effective solutions to the
problems of connecting small computers to each other and to Mainframes.
In another area, CRT display systems have traditionally required a great deal of
support circuitry for the complex timing, refresh and control functions.
This need led the engineers at Standard Microsystems to develop the CRT5027
Video Timer and Controller (VTAC®), the first CRT controller to provide all of these
functions on a single chip. The display, graphics and attributes control functions
were then all combined for the first time in the CRT8002 Video Display Attributes
Controller (VDAC®).
Another major achievement has been the development of the "next generation"
Video Processor And Controller (VPAC®), the CRT9007. Besides replacing up to 80
SSI and MSI TTL devices, the VPAC® is the first CRT controller to provide a hardware
solution to many of the software problems of CRT Video Controller design. The
CRT9007 is the basis of a complete high performance, low cost, CRT control family, which includes single and double row buffers, and a variety of Video Attribute
Controllers utilizing the COPLAMOS® technology to run from 20 MHz to 33 MHz.
The various elements of the VPAC® family can be selected to provide the optimal
video control solution from low to high end systems.
Most recently, the CRT9028 VTLC and CRT9053 EVTLC have integrated the entire
video and attribute control functions, as well as the character generator, all on
one VLSI circuit. A complete terminal can be built using these devices with just the
inclusion of a RAM and microprocessor.
Standard Microsystems has spearheaded many developments in the rotating
memory area as well. Extracting the actual stored data and clock signals from
the distorted and jittery signal provided by a floppy disk drive has historically
required not only a large number of analog components, but finicky production
line adjustments. Both of these problems are solved by SMC products. The
FDC9216 Floppy Disk Data Separator provides a revolutionary single chip solution
to the data separation problem in a single 8 pin mini-dip package. Utilizing both
long-term and short-term timing correctors, the FDC9216 requires absolutely no
external components or adjustments. The FDC9229 Floppy Disk Interface Circuit
provides, in addition to the digital data separator, a clock generator, precom-

15

pensation generator, and head load timer. The new FDC9236 and FDC9239 provide even higher resolution data acquisition with the additional benefit of low
power CMOS technology. The FDC9236 and FDC9239 are pin for pin replacements for the FDC9216 and FDC9229. SMC's FDC9238 offers high resolution,
CMOS technology, and FDC765 compatibility, all in a 14 pin package.
Along with these datd separators, Standard Microsystems offers a broad line of
floppy disk controllers, including the FDC9266, FDC9267, and FDC9268, which
combine the industry standard FDC765A Floppy Disk Controller with a choice of
SMC Data Separator/Precompensation Generators, all on one chip. The
FDC9266, FDC9267, and FDC9268 provide the highest level of integration in
floppy disk control circuits.
The HDC9224 Universal Disk Controller is the first IC to control not only hard disks,
but also floppy disks and the tape drives used to back up the disks, as well. In
addition, it offers user transparent error detection and correction for up to four 16
head drives.
Hard disk drives suffer from the same signal distortion and jitter as floppy disk
drives. SMC provides a choice of Hard Disk Data Separators to solve this problem.
The HDC9226 enhances the HDC9224 by providing hard disk data separation
with a soft error rate as low or lower than that of the drive itself. The HDC9227 Dual
Data Separator includes both a Hard Disk Data Separator and a high resolution
Floppy Disk Data Separator on a single chip. Designed for use with either the
HDC9226 or HDC9227, the HDC9223 Analog Data Separator Support chip
includes all the active analog circuit components needed to form a phase
locked loop for performing hard disk data separation.
The HDC9225, when used with the HDC9224, greatly reduces the total number of
lC's required by a hard disk control system, while permitting low cost RAMs to be
used in a dual-ported configuration to improve system performance.
Achievements like these help keep Standard Microsystems' custom and standard
products in the forefront of technology, with increased speeds and densities and
a lower cost per function.

Improvements· in Processing and
Manufacturing Keep Pace with
Advances in Semiconductors.
With the phenomenal growth of the electronics industry, innovation is, of course,
highly desirable. But if the products are to perform as designed. they also have to
be reliable.
That's why at Standard Microsystems we take every means to insure the utmost
quality and dependability. Consequently, "state-of-the-art' applies not only to
our products, but to the way we manufacture them.
In wafer fabrication, the latest equipment and techniques are employed. In
addition to conventional processing equipment we use ion implantation technology extensively. We also use plasma reactors for much of our etching and
stripping operations to maintain tight tolerances on process parameters. Perkin
Elmer scanning projection printers and TRE mask steppers assure that the critical
photolithographic requirements of the latest small geometry processes are met.
Standard Microsystems' commitment to excellence is further demonstrated in
the use of the latest Fairchild, Megatest and Genrad testers. Our full service
capability lets us make full use of the technologies we develop. We can produce
any quantity of semiconductors customers may require. Whafs more, we can
provide our customers with the fast delivery times that they require in today's
increasingly competitive environment.
16

Standard Microsystetns' Custom Capability.
Custom MOS. A Small Revolution
with a Large Impact.

design and cell library based designs. Where
reduction of chip size for lowest production
pricing in high volume is the dominant factor,
the fully crafted design method will provide
the best solution. However, development
costs and development time will be greatest.
Where quick turnaround and reduction of
engineering costs are .dominant factors then
use of our cell library design approach will be
the better alternative.
Regardless of the design approach, a custom circuit will provide-

Remarkable advances in semiconductor
technology, combined with the availability of
quality, low-cost electronics, continue to
open new markets for products incorporating
micro-electronic components.
Today, metal-oxide semiconductor/large
scale integrated (MOS/LSI) circuits are integral
components in computers and computer
peripherals, automobiles, televisions, electrical appliances, data communications, bank
terminals, telephones and a host of other significant applications.
With further applications for large scale
integrated and very large scale integrated
(VLSI) circuits being discovered every day,
one thing is certain. They will have a profound
effect on our lifestyle.

Lowest Overall Cost.
The overall cost savings realized with custom
MOSNLSI circuitry can be substantial, especiaily when high-volume production is
encountered.
Savings are effected in several ways.
Because custom designed circuits contain
only necessary componer,1ts, the cost of
unused circuitry on standard microprocessors
or integrated circuits is eliminated. Costs for
troubleshooting, repair and warranty claims
are reduced. In addition, custom MOS can be
more economical over SSI and MSI when purchase, inventory and assembly costs are considered. Also, when a system contains a large
amount of SSI and MSL its custom counterpart
can significantly reduce power consumption.

Custom Commitment.
Custom Products has its own management
marketing, and engineering te()m that is fully
dedicated to developing and producing
standard cell semicustom and full custom
products.
Custom MOS/LSI is a major portion of oUr
business. A sizable portion of all our revenue is
a direct result of our custom MOS/LSI projects.
Over the years, Standard Microsystems has
developed custom circuits for a wide variety
of applications: Computers and computer
peripherals, telecommunications and data
communications, garage door openers and
burglar alarms, electronic toys and games,
musical instruments and more. Both over-theair and cable T.v. systems have made use of
our custom circuits. One company's line of
word processing equipment makes almost
exclusive use of our custom LSI.
As a company committed to serve the custom marketplace, Standard Microsystems has
developed the resources and established
procedures for MOS/LSI and MOSNLSI circuit
development that enables the company to
respond rapidly to growing customer needs.

Lowest Parts Count.
There are many applications where a singlepackage custom LSI or VLSI circuit can outperform a microprocessor and its ROM and
RAM circuits while reducing costs. A custom LSI
unit can rapidly execute repetitive functions
using high speed logic. A microprocessor
needs time-consuming algorithms to do the
same thing.
Highest Reliability.
Higher reliability is achieved. especially when
replacing circuits that contain significant
amounts of SSI and MSI. Fewer parts and solder points reduce the failure rate and raise
the reliability. This means low MTTR (mean
time to repair), which translates into lower
maintenance costs and higher customer
satisfaction.

The Custom Option.
Standard Microsystems offers two custom
design alternatives: fully crafted custom
17

---- - - - - - - - - - - - - - - - - - - - - - -

Minimum Size, Weight, Power Dissipation.

Although the designer is constantly monitoring this process, he is not actually "in line",
Therefore, problems due to human error are
virtually eliminated and you're assured that
first silicon is working silicon.
The result? You get the semicustom ICs you
need quickly and your development and
production costs are reduced.

The size and complexity of printed circuit
boards are greatly reduced when using a
custom circuit. The custom circuit results in a
most compact package, specifically
designed to perform only the necessary tasks
utilizing minimum power and space.
Unique Proprietary Features.

Bringing Process, Software and
Hardware Together.

Proprietary design is another major benefit. It
protects your design from would-be copiers
because it makes testing and support difficult.
This, coupled with the complexity of custom
semiconductor fabrication, makes duplicating your custom circuit far less probable.

Process technology you can count on.

For over a decade, Standard Microsystems
has been atthe leading edge of n-channel,
silicon-gate process technology, Our patented COPLAMOS® process is used throughout the world and is one of the most widely
licensed processes in the semiconductor
industry,
Now we've channeled our expertise into a
production-proven 3-micron, silicon-gate
CMOS process that's compatible with the
design rules of several other major semiconductor manufacturers, including NCR Corporation, our contractual alternate source, it's
the cornerstone of our Customation ™design
system.

A Complete Cell Library Design
System for Semicustom LSIMSI.
An idea whose time has come.
To prosper, if not survive, in today's fast-paced

electronics industry, you must differentiate
your products from the competition.
This means designing in more features,
~igher r~liability ~nd .Iower power consumption, while reducing size to a minimum. Of
course, your next-generation products should
also cost less than their predecessors.
I:ull custom CMOS LSINLSI is one way to
achieve these goals, but that approach has
definite limitations. For example, long development times can upset scheduled product
introductions and high development costs
can significantly erode profit margins,
Fortunately, the availability of powerful
workstations and a new generation of CAD
software tools has created a viable alternative: Semicustom LSINLSI.
Now, Standard Microsystems Corporation is
offering you a complete semicustom design
system that combines the advantages of full
custom CMOS with rapid turnaround, low cost
and virtually guaranteed first-time success,
We call our new system Customation™.lt is
a "standard cell" design approach that uses
a database of proven building blocks and a
family of state-of-the-art software tools which
enable the engineer to both perform the
design and verify it with the utmost speed and
precision,
, A typical Customation ™ design sequence
Involves the use of a progression of software
design tools, with the output of one serving as
the input for the next,

A large, proven cell library.

The Customation ™cell library includes more
than 180 cells, Most emulate 74LS logic functions, so your design engineers are already
familiar with them. The design system stores
the cell layouts, logical models and performance characteristics of each cell in its database, You can feel confident about the
performance of these cells, too, They are
thoroughly characterized and have been
used successfully in numerous applications,
Standard Microsystems is dedicated to
incorporating more complex macrocells and
supercells into the library, These currently
encompass such functions as ROMs, RAMs,
and core microprocessors and, in the future,
will include data communications functions
as well as computer peripheral controllers
developed at SMC.
Industry-standard software.

Customation ™gives you a complete and
integrated set of software tools for design,
simulation, modeling, checking, and verification test pattern generation,

CUSTOMATION m is a trademark of Standard Microsystems Corporation
COPLAMOS® is a registered trademark of Standard Microsystems Corporation,

18

Whenever possible, we've utilized "industrystandard" software that provides a wellproven package of design aids which many
of your engineers may already be comfortable using. It can also be licensed through
Standard Microsystems.

You also have the option of doing your
design work on a workstation located at one
of our convenient design centers or having
SMC engineers perform the entire design.

Technical support.
We offer continuing technical support for our
Customation ™ users. Our application engineers are experts in the use of the Customation ™ design system and can provide prompt
assistance from our home office and our
regional sales offices. An applications engineer assigned to your program will be available to assist you with any problems that may
arise during the course of the development.
Standard Microsystems has developed a
particularly strong applications expertise in
data communications, video displays, disk
controllers, and small computer peripherals
and can provide very extensive support in
these areas.

A turnkey workstation.
Standard Microsystems offers a complete
turnkey workstation design system that you
can use at your own facility. This system, along
with SMC's utility software, is optimally configured for semicustom design, combining
high performance and ease of operation.
We are also constantly enhancing our software to support other workstations and mainframes. Workstations can be acquired directly
from the manufacturer or through special
arrangement with SMC.
Much of our software already runs on VAX
computers. We are currently porting our cell
library and software onto several other popular workstations. Please check with us on the
status support for your preferred workstation.

A typical design sequence.
If needed, you obtain a powerful CAD workstation either from us or directly from the
workstation manufacturer.
We teach your design engineers all they
need to know about "front-end" design using
the Customation ™ design system.
You design and verify logic on workstations
at your own facility or at our design centers,
performing the logic simulations and generating the input and output test vectors.
You submit the resulting netlist to us for layout and post-layout timing parameter
extraction.
We perform the chip layout with our cell
place-and-route program and return actual
layout timing parameters for designer review.
You sign off the design only after you are
totally satisfied with the final simulations using
actual parameters.
We fabricate prototype circuits.
SMC's design engineers can also perform
the full design or assume responsibility at any
step in the design process.

A Design Partnership.
Comprehensive training.
Even if you've never had IC design experience, Standard Microsystems can quickly
teach you to create cell-based ICs using
Customation
At our plant on Long Island, we conduct
classes for all skill levels, tailoring our instruction to your particular needs and experience
level. We cover all phases of design, and
you'll work on an actual Customation ™ workstation to get hands-on experience and
sharpen your design technique. You'll complete the training session ready to produce
usable designs utilizing Customation
TM.

TM.

Do your design work at your place or ours.
A major benefit of Customation ™ is the control it gives you over your design. You work at
your own pace-at your own facility, if you
wish-verifying the logic through simulation
at each step of the way.
We provide everything you need to perform the design from schematic capture
through logic simulation and timing analysis.
Once you're satisfied with your design, we'll
perform automatic placement and routing
from your netlist. We then carry the process
through masks, wafers and prototypes.

Fast Turnaround, Low Cost,
Guaranteed Results.
Working silicon within 8 weeks.
Fast turnaround is another important benefit
of Customation ™ . We can supply working
prototypes within eight weeks of receipt of
your signed-off netlist.
Design time and logic simUlation is
dependent on you, the customer. With an
19

The Full Design Custom Program.

experienced designer using our Customation ™ design system, frontend design should
take approximately 4 weeks,*

Typically in a custom program where
Standard Microsystems performs all of the
operations-from design through to finished
product-the following sequence applies:

Cost-effective chips.

Unit cost depends on a variety of factors: gate
count, complexity of interconnect, package
cost and performance requirements, A Customation ™ design, however, almost always
results in a smaller die size than a comparable gate array design, This means lower
prices when you get into volume production,
Your system will have fewer ICs compared to
MSI, gate array, or microprocessor-based
designs, resulting in lower assembly and test
costs, lower power consumption and
enhanced reliability,
SMC will calculate and commit to a production price for your Customation ™ chip
based on your design specifications, This
means that you will know your exact production costs before you undertake the design,

Evaluation.

The customer's system characteristics are
carefully evaluated from the information provided to determine the feasibility of the custom approach, considering such factors as
system partitioning, functional performance,
operational environment, operating speed,
power requirements, process selection, packaging and testing,
After concluding this evaluation, Standard
Microsystems will quickly provide a Quotation
to the potential customer, which will
include- a firm development schedule
-the non-recurring engineering charge (NRE)
- a production price schedule

Second source security.

Standard Microsystems has signed a worldwide, comprehensive agreement with NCR
Corporation, providing for the mutual second
sourcing and joint development of our CMOS
standard cell libraries,
Not only does this agreement assure compatibility at both the process and netlist level,
it merges together two of the most innovative
and well-respected cell libraries in the semiconductor industry, The common library will
be supported on the four leading workstations: Daisy, Mentor, Valid Logic and
Metheus/CV.
The agreement also calls for ongoing technical cooperation, Both companies are committed to the enrichment of the cell library
through the addition of MSI cells and supercells, Our joint effort will continue with the
development of next-generation, fine-line
geometry process technologies,

System Definition.

Once the design is authorized, a thorough
specification review takes place between
Standard Microsystems' engineers and the
customer's engineers, In this critical phase,
Standard Microsystems' years of successful
design experience are applied as an extension of the customer's design resource in a
close working relationship,
Circuit Design.

Required functions are converted to detailed
MOS logic, The logic is verified via advanced
logic simulation routines, utilizing our in-house
computers, VAX 11/785 and/or breadboard
emulators, Circuit simulation is done using
SPICE, MOSAID, and Standard Microsystems
proprietary software,

Guaranteed results.
Artwork Generation.

With Customation you're virtually guaranteed first time success, We've designed our
system for outstanding accuracy with a number of strategic checkpoints to find and eliminate problems before the circuit is fabricated.
In fact, we guarantee you'll get the results
you want by making the following commitment: "Standard Microsystems will bear the
cost of any design iteration that is required as
a result of an error in cells, utilities and design
tools making up the Customation ™ system,"
TM,

At Standard Microsystems, device layout is a
blend of custom "hand-crafting" and sophisticated CAD, using our Calma GDS I and GDS II
color graphics systems, to achieve the optimum composite drawing in terms of size and
schedule, Check plots are obtained on our
Xynetics and Versatec plotters, and
advanced design rule checks (DRC) and
electrical rule checks (ERC) provide com prehensive artwork verification,

'These design and prototype development cycles are based on a 1600 gate equivalent chip design,

20

Mask Fabrication.
Production tooling is obtained from qualified
mask vendors to Standard Microsystems'
exacting, above-industry standards. Colored
overlays of each mask layer are typically
used as a final check point.

All wafer processing is done in our facilities,
utilizing state-of-the art equipment. Standard
Microsystems has made sUbstantial investments in projection alignment equipment
direct-step-on-wafer equipment and
advanced ion-implantation, sputtering, deposition and plasma etch equipment.
Assembly.

Wafer Fabrication.

Standard Microsystems can provide a wide
variety of industry-standard packages, including ceramic, plastic and CERDIP dual-in-line
types, flat-packs and chip carriers. The latest
in automated equipment such as our automatic wire bonders, insure high quality and
high volume throughout.

Standard Microsystems offers a variety of
processes, including a CMOS silicon-gate
process, and a range of n-channel silicongate processes. We will determine the appropriate process to satisfy each customer's
cost/performance requirements.

PROCESS
9000

TYPE
n-MOS

10000

n-MOS

SMC PROCESS CHARACTERISTICS
TYPICAL
CHANNEL SUPPLY
MAX.
FREQ.
LENGTH
VOLTAGES
30
MHz
+5, +12
4f.L
optional
- 5, (optional)
451V1Hz
+5
3f.L

20000

CMOS

2f.L

+5

60MHZ

30000

CMOS

3f.L

+3to +6

45MHz

FEATURES/
COMMENTS
n-channel, si-gate process,
moderate to high
performance.
very high performance
n-channel process.
advanced si-gate CMOS
process.
si-gate CMOS process.

Customer Owned Tooling.
An area of continuing interest to Standard
Microsystems is that of Customer Owned Tooling (COT) or Customer Supplied Tooling (CST).
In contrast to a full custom design program
where Standard Microsystems is responsible
for the MOS design, a COT/CST program is
one in which the design function will be completed by the customer or an outside design
house.
Many customers find it desirable to
develop an in-house LSI design capability, for
their internal circuit requirements. Standard
Microsystems can provide valuable assistance in achieving this goal.
The customer then provides Standard
Microsystems with either a completed composite drawing, a data base tape (in suitable
format), or an actual processing mask set.

Whatever the entry level, Standard Microsystems is prepared to carry the program
through to completion.
If the design is in the formative stages, the
requirements will be studied and the most
suitable set of design rules will be provided.
If the design is already completed,
Standard Microsystems will examine the
design rules used and recommend which of
our processes is most compatible. If small variations to our "standard" processing are
required, they can usually be accommodated at little or no expense.
Standard Microsystems has developed
comprehensive test sites that are incorporated into our masks for the purpose of parametric and quality assurance measurements.
Automated equipment collects and stores
21

measurements from these test sites. If a customer purchases wafers from us, these measurements are provided with the wafers. If a
customer chooses to have masks fabricated
himself, our test site can be provided for
incorporation into the masks.
Standard Microsystems is also prepared to
work with customers in establishing a suitable
test interface which will enable us to provide
the wafer probe and final test operations. Of
course, packaging and burn-in are also
available.
Whichever approach is taken, Standard
Microsystems wants to participate in a partnership that makes best use of our respective
areas of expertise. We'll work together to
bring the project to completion; on time and
on budget.

Device
Specification

C

U
Composite
Drawing

¢

S
T

0

M
E
R
E
N
T

C
I
R
C

Customer Interface.

U
I

Standard Microsystems is a "full capability"
company. We have the resources-an experienced staff and state-of-the-art equipment-to design, process, package and test
our Custom MaS circuits.
Our customers are becoming increasingly
aware of the benefits of custom circuits in
their product lines. They know their products
and markets best. Some have developed the
technical expertise to perform or participate
in the early design phases of a custom program. For this reason, Standard Microsystems
offers a variety of customer interface possibilities to serve the broadest possible market.

T

R
Y
Data
Base
Tape

p

¢

0
I
N
T
S

D
E
V

E
L

o

P
M
E
N

T
C
y

C
L
E

Communications: The Key to
Custom Development.
On every Custom program, we establish
communications with our customers that last
throughout the development and production
phases.
Our engineers work in an environment that
stimulates creativity while encouraging
adherence to pragmatic objectives. The status of each program is closely monitored.
Strict scheduling, thorough program management and frequent customer contact
have become the hallmark of a Standard
Microsystems Custom program. Numerous
testimonials from satisfied customers give evidence of our ability to perform-to specification and on time.

D
E
L
I

V
E
R
Y

P

o
Final
Product

22

I
N

T
S

STANDARD MICROSYSTEMS CORPORATION
STANDARD CELL LIBRARY
Cell Name

Description

Logic Gate Cells
LSOO
LS02
LS04
LS08
LS10
LS11
LS20
LS21
LS25
LS27
LS28
LS30
LS32
LS37
LS40
LS51a
LS51b
LS54
LS55
LS64
LS86
LS133
LS134
LS260
LS266
Buffer Cells
LS125
LS126
LS240
LS242
LS243
LS244
LS245
LS265a
ILS265b
IILS365
',LS366
LS367
LS368
',Shift Register Cells
LS95
lS164
1

_S166
I_S178
15179
'_S194
1
I.S195
IS198
IS295
'S395
I

Cell Name

Description

Flip-Flop Cells
2-lnput NAND Gate
2-lnput NOR Gate
Inverter
2-lnput AND Gate
3-lnput NAND Gate
3-lnput AND Gate
4-lnput NAND Gate
4-lnput AND Gate
4-lnput NOR Gate with Strobe
3-lnput NOR Gate
2-lnput NOR Gate with Buffer
8-lnput NAND Gate
2-lnput OR Gate
2-lnput NAND Gate with Buffer
4-lnput NAND Gate with Buffer
2-Wide, 2-lnput AND-OR-Invert Gate
2-Wide, 3-lnput AND-OR-Invert Gate
4Wide, 2-lnput & 3-lnput
AND-OR-Invert Gate
2-Wide, 4-lnput AND-OR-Invert
Gate
4-2-3-2 Input AND-OR-Invert Gate
2-lnput Exclusive OR (XOR) Gate
13-lnput NAND Gate
12-lnput NAND Gate with
Tri-State Output
5-lnput NOR Gate
2-lnput Exclusive NOR (XNOR) Gate
Non-Inverting Tri-State Buffer
Non-Inverting Tri-State Buffer
Inverting Tri-State Buffer
Inverting Transceiver.
Non-Inverting Transceiver
Non-Inverting Tri-State Buffer
Octal Non-Inverting Transceiver
1-lnput, Dual Complimentary
Output Gate
2-lnput AND Gate
w/Complimentary Dual Output
Hex Non-Inverting Tri-State Buffer
Hex Inverting Tri-State Buffer
Quad Non-Inverting Tri-State Buffer
Quad Inverting Tri-State Buffer
4-Bit Parallel I/O, Serial Input
Left/Right SR
8-Bit Parallel Output, Serial Input SR
w/Clear
8-Bit Parallel/Serial Input, Serial
Output SR w/Clear
4-Bit Universal Shift Register
4-Bit Universal SR with Async. Clear
4-Bit Bidirectional Universal SR
w/Clear
4-Bit Parallel Input/Output SR
w/Clear
8-Bit Bidirectional Universal SR
w/Clear
4-Bit Universal Shift Register
4-Bit Universal SR w/Async. Clear,
Tri-State Outputs

LS73
LS74
LS174
LS175
LS374
LS377
Latch Cells
LS75
LS77
LS100
LS116
LS375
Multiplexer/
Selector Cells
LS151
LS152
LS153
LS157
LS158
LS253
LS352
LS353
Counter Cells
LS163a
LS169a

Decoder/
Encoder Cells
LS138
LS139
LS148
Comparator Cell
LS85
Arithmetic
Operator Cell
LS83
LS283
LS183
Parity Generator Cell
LS180
Input/Output Pads(Individual Gates)
LS041P
LS071P
LS741P
LS141P
LS040P
LS050P
LS070P
LS740P
LSBI

J-K Flip-Flop with Clear
D Flip-Flop with Preset & Clear
Hex D Flip-Flop with Direct Clear
Quad D Flip-Flop with Direct Clear
Octal D Flip-Flop with Tri-State Output
Octal D Flip-Flop
Dual Transparent Latch
Dual Transparent Latch
Quad Transparent Latch
Quad Transparent Latch with Clear
Dual Transparent Latch

8: 1 Multiplexer with Strobe
8: 1 Multiplexer, Inverting
4: 1 Multiplexer
Quad 2:1 Multiplexer
Quad 2:1 Multiplexer, Inverting
4: 1 Multiplexer, Tri-State Output
4: 1 Multiplexer, Inverting
4: 1 Multiplexer, Tri-State, Inverting
4-Bit Syncronous Binary Counter
4-Bit Syncronous Binary Up/Down
Counter

3:8 Decoder with Enable
2:4 Decoder with Enable
8:3 Priority Encoder
4-Bit Magnitude Comparator

4-Bit Full Adder
4-Bit Full Adder
Full Adder
9-Bit Odd/Even Parity Checker

Inverting Input Pad Buffer
Non-Inverting Input Pad Buffer
D Flip-Flop Input Pad Buffer (D input only)
Schmitt Trigger Input Pad Buffer
Inverting Output Pad Buffer
Open Drain,lnverting Output Pad Buffer
Non-Inverting Output Pad Buffer
D Flip-Flop Output Pad Buffer
(Q output only)
Bi-Directional Pad Buffer

STANDARD MICROSYSTEMS
CORPORATION

23

STANDARD MICROSYSTEMS CORPORATION
STANDARD CELL LIBRARY

Cell Name

Description

Cell Name
Counter Cells

Gate Cells
ANDB
AOl211
AOl22
AOl31
EXNOR
EXOR
HBUF
MBUF
INBUF
INV
INV3/0UTINV
IOBUF
DLYCEL
LS125
LS240
LS242
NAN2
NAN3
NAN4
NAN5
NOR2
NOR3
NOR4
ORB
OAI31
INVT
TBUF

Description

B Input AND Gate

LS163A
LS169A

2-1-1 AND-OR-Invert
2-2 AND-OR-Invert
3-1 AND-OR-Invert
ExclUsive NOR Gate
Exclusive OR Gate
High Drive Buffer
Medium Drive Buffer
Input Buffer
Inverter
High Drive INV/Output Buffer
Input/Output Buffer
Delay Cell
Non-Inverting Tri-State Buffer
Inverting Tri-State Buffer
Inverting Trqnsceiver
2 Input NAND Gate
3 Input NAND Gate
4 Input NAND Gate
5 Input NAND Gate
2 Input NOR Gate
3 Input NOR Gate
4 Input NOR Gate
B Input OR Gate
3-1 OR-AND-Invert
Inverting Tri-State Driver
Non-Inverting Tri-State Driver

4-Bit Syncronous Binary Counter
4-Bit Syncronous Binary Up/Down
Counter

Arithmetic Operator
LSB3
LS85

4-Bit Full Adder
4-Bit Magnitude Comparator

Analog Cells
ANSW

DS121B
DS1238
DS1323
DS1527

DS172B
DS202B
DS2232
OSCP
POR
VCM1
VCM2
VCM3
OPAMP
COMPOS
COMPG

Analog Switch
Schmitt Trigger (1.2-1.BV)
Schmitt Trigger (1.2-3.BV)
Schmitt Trigger (1.3-2.3V)
Schmitt Trigger (1.5-2. 7V)
Schmitt Trigger (1.7-2.BV)
Schmitt Trigger (2.0-2.BV)
Schmitt Trigger (2.2-3.2V)
General Purpose Oscillator
Power On Reset
Voltage Reference (50uA)
Voltage Reference (100uA)
Vottage Reference (200uA)
General Purpose Operational
Amplifier
High Speed Low Power
Comparator
General Purpose
Comparator

Pad Cells
Latch &
Flip·Flop Cells
CCND
CCNR
DFF
DFFR
DFFRS
JKFF
LAT
LATBUF
LATR
LS74A
LS76A
LS100
LS116
LS175
LS164
LS194
SRBN
UDC
PCL2

INPD
IOPD2S
IOPD4
IOPD4S
IOPDB
IPPD4
IPPDB
ODPD4
ODPDB
ONPD4
ONPDB
OPD4
OPD8
OPPD4
OPPDB
PU30
PD30

Cross Coupled NAND Latch
Cross Coupled NOR Latch
D Flip Flop
D Flip Flop with Reset
D Flip Flop w/Set & Reset
J-K Flip Flop
Transparent Latch
Tri-Statable Transparent Latch
Transparent Latch with Reset
D Flip Flop with Set & Reset
J-K Flip Flop
Quad Transparent Latch
Quad Transparent Latch w/Ciear
Quad D Flip-Flop w/Direct Clear
B-Bit Parallel Output. Serial Input
SRw/Clear
4-Bit Bidirectional Universal SR
w/Clear
Shift Register
Up/Down Counter
Two Phase Clock

Supercells
ROM Supercell
RAM Supercell
TIMER I Supercell
65CX02 Supercell
ATOD Supercell
SCC Supercell
BRG Supercell
VCO Supercell

Multiplexer Cells
MUX2
LS151
LS153

Multiplexer Cell
B: 1 Multiplexer with Strobe
4:1 Multiplexer

Modular ROM (512 bits)
Modular RAM (512 bits)
16-Bit CounterlTimer
B-Bit Core Microprocessor
B-Bit Analog to Digital Converter
Serial Communication
Baud Rate Generator
Voltage Controlled Oscillator

STANDARD MJCROSYSTEMS
CORPORATION

Decoderl
Encoder Cells
LS13B
LS139

Input PAD
2mA Split P-Channell/O PAD
4mA Input/Output PAD
4mA Split P-Channell/O PAD
BmA Input/Output PAD
Input PAD with 400uA Pullup
Input PAD with BOOuA Pullup
4mA 5V Open-Drain Output PAD
BmA 5V Open-Drain Output PAD
4mA 7V Open-Drain Output PAD
BmA 7V Open-Drain Output PAD
4mA Output PAD
BmA Output PAD
4mA Tri-State Output PAD
BmA Tri-State Output PAD
P-ChannelPuliup
N-Channel Pulldown

3:B Decoder with Enable
2:4 Decoder with Enable

24
--

-------

Quality Assurance
and Quality Control
Volume manufacturing of quality products requires a rigorous commitment on behalf of STANDARD MICROSYSTEMS and all of its employees. Each phase of the
operation from design to shipping must adhere stringently to documented procedures which have produced
a product of proven reliability.

Manufacturing flow is monitored by Quality Control to
insure that parameters meet specifications on incoming
material, within the line and at outgoing inspection. Clean
room standards, calibration and work methods are also
monitored.
The Quality Assurance Department is the customer representative with the primary responsibility of evaluating
product to current industry standards and related
responsibilities of evaluating developmental processes,
product and the standards themselves.

The design of a reliable product is assured by adherence
to tested and proven design rules. Any change in design
rules must be evaluated using a design-rule test vehicle.
Each new product is evaluated first by prototype wafer
runs and thorough preliminary production and device
characterization.

1.0

The following is a more detailed description of the types
of screening performed and how SMC is organized to
produce quality products.

Scope

3.5

2.0

3.6

Approach

MIL-I-45208
MIL-M-38510

Applicable Documentation

MIL-M-55565
MIL-STD-105

SMC internal specifications define every phase of production and must be approved by the designated representatives of Engineering, Manufacturing, Processing,
Quality Control and Quality Assurance departments.

3.1

MIL-STD-883
MIL-STD-1331

Design Rules (DR-XX)

3.1.1 Geometric design rules define layout considerations, alignment structures, critic;:ll-dimension targets,
and input-protection networks.
3.1 .2 Electrical design rules define performance criteria, measurement methods, device parameters, and
process parameters.

3.2

4.0

Package Options, Features

4.1

Ceramic (no suffix)

Purchase Specifications (PS-XX)

4.2

Cerdip (Suffix "CD")

Meets MIL-STD-883 internal moisture content requirements of Method 5005. Substrate connections are made
through jumper chips, gold eutectic die attach.

Process Specifications (WX-XX, AX-XX)

3.3.1 The procedures used for wafer processing and
assembly of microcircuits are fully documented.

3.4

Calibration System
Requirements
Inspection System
Requirements
General Specification for Microcircuits
Packaging of Microcircuits
Sampling Procedures and Tables
for Inspection by Attributes
Test Methods and Procedures for
Microelectronics
Microelectronics Terms and
Definitions

Gold plating on external leads and die cavity, gold eutectic die attach.

All critical material is purchased to SMC specifications
from qualified vendors.

3.3

Military Standards and Specifications

MIL-C-45662

Factors relating to quality and reliability are discussed in
the following order: package options, screening, process control, test and characterization, quality conformance/reliability testing, and failure analysis.

3.0

Quality Assurance Procedures (QA-XX)

QA procedures define methods for product/process
qualification, reliability testing and failure analysis.

The measures taken by SMC to produce reliable integrated circuits and the assembly/screening' options
available to the customer are given in this sectior,.

4.3

Quality Control Procedures (QC-XX)

Plastic (Suffix "P")

The plastic used is a 8-type epoxy or an approved
advanced type having a better resistance to a humid
environment.

QC procedures define the sampling techniques, accept!
reject criteria and test methods used in quality audits.

25

5.2.5 Final Electrical Test
Verifies functional and parametric performance to the
device specifications.

5.0 Screening Options
5.1 High-Reliability Screening
The routing is as defined in MIL-STD-883 Method 5004
for Class B product. Periodic Quality Conformance data
(para. 9.2) is taken on generically similar parts. A sample
flow chart for ceramic product is given on page 30.

5.3

Custom Screening

Certain applications require special screening which can
be arranged upon request.

5.1.1 Internal Visual
Both Die and Preseal Visual inspections are to the criteria of Method 2010, Condition B of MIL-STD-883. An
AQL audit is performed on each lotby Quality Control.

6.0 Electrical Test
6.1 Probe and Final Test
SMC test programs are developed by Test Engineering
and verified by device characterization. An approval procedure is required for the transfer of a new test program
or a revised test program from engineering to production.

5.1.2 Stabilization Bake
All parts are given the stabilization bake according to
Method 1008, Condition C of MIL-STD-883.

6.2

5.1.3 Temperature Cycling
All parts are subjected to 10 cycles of - 65°C to + 150°C
per Method 1010, Condition C of MIL-STD-883.

Characterization/correlation

Characterization of parts and correlation of test results
with customer incoming testing performed on SMC test
equipment, including Megatest and Sentry'" , and Gen
Rad test systems.

5.1.4 Constant Acceleration
All parts are subjected to a 30,000 g force in the Y1 orientation per Method 2001, Condition E.

6.3

Product Engineering

5.1.5 Seal
Hermeticity testing is performed to conditions A and C
of MIL-STD-883 Method 1014.

SMC product engineers characterize parts to improve
processing target parameters and test correlation with
customers.

5.1.6 Pre burn-in Electrical Test.
Ordinarily this is the same as final electrical test.

7.0 Purchased Material
Manufacturing materials are purchased from qualified
vendors to SMC procurement specification.

5.1.7 Burn-in
Condition A and Condition D of MIL-STD-883 Method
1015 are available. The stress is applied for 160 hours at
125°C or at other temperatures according to the timetemperature regression.

8.0 Quality Control
The Quality Control Department reports to the Vice
President of Quality Assurance. QC is responsible for
incoming inspection, in-process audits, out-going
inspection, document control, processing returned
material and certification of compliance to specification.

5.1.8 Final Electrical Test
Verifies functional and parametric performance to the
device specifications.

8.1

5.1.9 Final Visual Inspection
All parts are inspected to Method 2009 of MIL-STD-883.

5.2

Incoming Inspection

Inspectors verify critical parameters on all material used
in manufacturing. The department maintains an
approved vendor list and interfaces directly with vendor
QC departments.

Standard Screening

Standard Screening is designed for the industrialcommercial customer and is available in all package
types. For hermetic packages, temperature cycling,
centrifuge and hermeticity are specified as well as die,
preseal, and final visual inspection.

8.2

5.2.1 Standard Die and Preseal Visual Inspections
(AC-04, AC-08, AD-04, AD-09, AP-98, AP-92, QC-32,
QC-33)
These inspections were developed from Method 2010 of
MIL-STD-883. The inspection criteria are specific to
SMC's PMOS, NMOS COPLAMOS® and CMOS
technologies.

QC inspectors verify proper documentation and perform
an external mechanical/visual inspection prior to
shipment.

In-process Audits

QC performs an on-going monitoring of wafer processing, test and assembly functions.

8.3

8.4

OutgOing Audit

Document Control

All procedures for design, wafer processing, assembly,
quality control and quality assurance are maintained by
document control.

5.2.2 Temperature Cycling (AC-15, AD-13)
Temperature cycling is performed to the MIL-STD-883,
equivalent of Method 1010 Condition C,- 65°C/ + 150°C,
ten cycles.

8.5

Returned Material Processing

Returned material, whether for device performance or
clerical reasons, is processed through visual and electrical testing.

5.2.3 Constant Acceleration (centrifuge)(AC-16, AD-14)
Constant Acceleration is performed to the MIL-STD-883,
equivalent of Method 2001, Condition E, 30,000 g in the
Y1 orientation.

8.6

Certificates of Compliance

Certificates of Compliance are available for specified
screening and/or for products ordered under a customer
part number/specification.

5.2.4 Hermeticity (AC-11, AD-15)
Includes fine and gross leak testing to SMC equivalent
of MIL-STD-883 Method 1014 Conditions A and C.

9.0 Quality Assurance
The Quality Assurance Department is the customer's

26

representative and is independent of the product line and
manufacturing organizations. Quality Assurance is
responsible for reliability assessment of new and existing processes, material analysis, failure analysis, calibration and development of evaluation methods.

9.1

9.3.3 Failure Analysis is performed upon request by
sales, marketing or manufacturing organizations and is
also performed on reliability test failures. The failure
analysis procedures support the development of new
product, process improvements, and the evaluation of
screening methods.

Process Qualification

9.3.4 Material analysis is performed on layers of the
integrated circuit and on packaging to support the engineering development. This characterization is performed on in-house facilities. Independent outside
analytical laboratories are used to supplement SMC
facilities if and when required.

All new processes and process revisions must equal or
exceed the reliability of existing processes on applicable
sections of the SMC Quality Conformance Test.

9.2

Quality Conformance Test

Samples of finished product are tested periodically to the
criteria of QA-01 (see table 1). This test sequence provides historical data which is also used for qualification
of new products and processes. The various subgroups
contain tests referenced in Method 5005 of MIL-STD-883
as well as tests designed around industry reqUirements
not yet incorporated in military standards.

9.3

9.4 Calibration
The Quality Assurance Calibration Laboratory specifies
calibration intervals, performs calibration and maintains
calibration records. The laboratory is traceable to the
National Bureau of Standards.

Analysis

9.3.1 The analytical facilities include a scanning electron microscope equipped with energy dispersive X-ray
(EDX), an infrared microscope, optical microscopes, a
laser cutter, metallurgical equipment, an X-ray unit and
electronic test instruments.

10.0

Lot Traceability

SMC maintains traceability on all product types in all
packaging options (including plastic). The information
available includes:

9.3.2 Scanning electronic microscopy is used in the
periodic evaluation of workmanship in wafer processing
and assembly, to support engineering efforts at process
development and improvement, and in failure analysis.

10.1

Wafer Processing Records

Sign-off and date on all operations, critical measurements and inspection records.

DATE CODE INTERPRETATION
86

Ih"'" two digi""h,"omb" 01

,..,5

the calendar week of the year

TJ
41

M

lot identification suffix

B1 = BURN-IN (WHEN APPROPRIATE)

(DEVICE TYPE)
SMC (DATE CODE)

ASSEMBLY LOCATION
(IF OTHER THAN U.S.A.)

PIN 1
INDICATION-.::r-,.,.-"..-.,.-_ _ _ _ _....--n.....,...,..-,I

BOTTOM MARKING

TOP MARKING

27

10.2

Wafer Lot Acceptance (Mapping)

10.3

Wafer Probe and Final Test Data

These are correlated with mapping results to develop
optimized process targets and yield improvement.
Device parameters are recorded using a high-speed
Accutest'" 3600 system. Further evaluation is performed using an HP 4145A semiconductor parametric
analyzer.

10.4

Assembly Records

Inspection results and screening throughput are recorded with date and sign-off for each lot.

TABLE 1-QA-01 QUALITY CONFORMANCE
GROUP B TESTS
MilStd
Test
Subgroup 1
Physical dimensions

SMCTest
Method

883
Method

Condition

2016

Subgroup 2
Resistance to solvents

QC-21

2015

Marking Permanence

Subgroup 3
Solderability

QC-15

2003

Soldering temperature of
245 ± 5°C

QC-33

2014

Failure criteria from design
and construction
requirements of applicable
procurement document

Subgroup 4
Internal visual and
mechanical

Subgroup 5
Bond strength
~1) Thermosonic
2) Ultrasonic or wedge
Die shear strength
Subgroup 6
Internal water-vapor
content

Subgroup 7
Seal
~al Fine
b Gross
Subgroup 8
Electrical parameters
Electrostatic discharge
sensitivity
Electrical parameters

2011
QC-31
QC-35

Quantity/
accept no. or
LTPD

Frequency
Package Type

2 devices
(no failures)

every package
lot

4 devices
(no failures)

every
shipment

15

periodic
conformance

1 device
(no failures)

periodically

15

periodic
conformance
all hermetic

3 devices
(no failures) or
5 devices
(1 failure)

periodic
conformance
all hermetic

(1) Test conditiun C or D
(2) Test condition C or D
2019
1018

5,000 ppm maximum water
content at 100°C

AC-11

1014

As applicable

5

periodic
conformance
all hermetic

3015

Group A, subgroup 1
Test condition A or B

15

QA-11

new device
types

Group A, subgroup 1

GROUP C TESTS-DIE RELATED
MilStd
Test
Subgroup 1
Steady state life test
End-point electrical
parameters
Subgroup 2
Temperature cycling
Constant acceleration
Seal
(a) Fine
(b) Gross
Visual examination
End-point electrical
parameters

Method

QA-02

1005

1010
2001

Final test

AC-15
AC-16

Quantity/
accept no. or
LTPD

Package
Type

Test condition to be
specified (typical!y
1,000 hours at 125°C)
As specified in the
applicable device
specification

5

all

Test condjtion C, 10 cycles
Test condition E min.
Y, orientation only
As applicable

15

all
hermetic

883

SMCTest
Method

1014

Condition

AC-11
QC-22
Final test

As specified in the
applicable device
specification

28

GROUP D-PACKAGE RELATED
MilStd
Test
Subgroup 1
Physical dimensions
Subgroup2
Lead integrity
Seal
(a) Fine
(b) Gross
Lid torque
Subgroup 3
Thermal shock
Temperature cycling
Moisture resistance
Seal
(a) Fine
(b) Gross
Visual examination

SMCTest
Method

883
Method
2016

QC-19

2004

AC·11

1014

Test condition B2 (lead
fatigue
As applicable

2024

As applicable

AC-15

1011
1010

Test condition B, 15 cycles
Test condition C, 100
cycles

AC-11

1004
1014

Seal
(a) Fine
(b) Gross
Visual examination
End-point electrical
parameters
Subgroup 5
Salt atmosphere
Seal
(a) Fine
(b) Gross
Visual examination

End-point electrical
parameters
Subgroup 9
Autoclave (Pressure
Cooker)
End-point electrical
parameters

Package
Type

15

all

15

all
all
hermetic
cerdip only

15

all
hermetic'

15

all
hermetic

15

all
hermetic'

3 devices
(no failures)
or 5 devices
(1 failure)

all
hermetic

15

all

1000 hours 85°C!85%
Relative Humidity

15

plastic

48 hours at 2 atm 121°C

15

plastic

As applicable

2002
2007

Test condition B minimum
Test condition A minimum

AC-16

2001

AC-11

1014

Test condition E minimum,
Y, orientation
As applicable

---

As specified in the
applicable device
specification

AC-11

1009
1014

Test condition A minimum
As applicable
Per visual criteria of
Method 1009

Subgroup 6
Internal water-vapor
content

Subgroup 7
Adhesion of lead finish
Subgroup 8
Humid Environment

Quantity!
accept no. or
LTPD

Per visual criteria of
Method 1004 and 1010
As specified in the
applicable device
specification

End-point electrical
parameters
Subgroup 4
Mechanical shock
Vibration, variable
frequency
Constant acceleration

Condition

1018

5,000 ppm maximum water
content at 100°C

2025
QA-04
Final test

QA·05
Final test

* packages having gold plating thicknesses of 200 microinches or less are not required to pass subgroups 3 and 5.

29

CERAMIC

HI REL AVAILABLE
ON ALL HERMETIC PACKAGES·

WAFER LOT ACCEPTANCE

WAFER LOT ACCEPTANCE
WAFER PROBE
WAFER PROBE

AC-14 SAW
AC-14 SAW
AC-02 BREAK
AC-02 BREAK
AC-03 DIE PLATE
AC-03 DIE PLATE
AC-04 STD DIE VISUAL
AC-18 HI REL VISUAL
METHOD 2010 CONDo B

QC-32 DIE INSPECTION AUDIT

QC DIE VISUAL AUDIT
METHOD 2010 CONDo B

AC-05 DIE ATTACH

AC·05 DIE ATTACH
AC-06-AL WIRE BOND

METHOD 2019
DIE SHEAR STRENGTH

AC-07-AU WIRE BOND

AC-06·AL WIRE BOND

AC·07-AU WIRE BOND

AC-08 PRE-SEAL VISUAL INSP
METHOD 2011 BOND STRENGTH
QC-33 PRE-SEAL AUDIT
AC-09 SEAL

AC·18 HI REL VISUAL
METHOD2010COND. B

AC-10 MARK

PRE-SEAL VISUAL AUDIT
METHOD 2010 CONDo B
AC·09 SEAL

AC-15 TEMP CYCLE -65/+ 150'C 10CY
AC·10 MARK
AC-16 CONST ACCEL Y1-30,000 G
AC-11 HERMETICITY
METHOD 1008 STABILIZATION BAKE
AC-12 TRIM
METHOD 1010 CONDo C
TEMP CYCLE

FINAL TEST

METHOD 2001 CONDo E
CONSTANT ACCELERATON

PACK

METHOD 1014 SEAL
(HERMETICITY)
AC·12 TRIM
SHIP

PRE-BURN·IN TEST
METHOD 1015 BURN-IN
FINAL TEST
PACK
METHOD 2009
EXTERNAL VISUAL

The Quality Control Department reports at the same level
as the manufacturing, test and process engineering
departments. QC is responsible for incoming inspection, in-process audits, out-going inspection, document
control, processing returned material and certification of
compliance to specification.

OUTGOING INSPECTION

30

PLASTIC (NOTE 1)

CERDIP

WAFER LOT ACCEPTANCE

WAFER LOT ACCEPTANCE

WAFER PROBE

WAFER PROBE

b'-_-"'A"'D"'-O'-'1-'W.:..
LI)
+

IREcElV"E--------(j)

::J
al

I
I
I

_

I r-

OAT 1
CT

~

~I----­ l O T fJ

C§ -<

;l5 -<
"' -<
:'?

:
I
I

f-I-' I
a:
w
>--

(j)

w

I
U
Z

I
I

~~: ~

>-

COMMAND SYNC
HARRIS
HD 15531
DATA SYNC
ENCODER/ I-'R"'C"-V:....:..:.N:..::RZ"-_ _ _ I
DECODER

_____

V~

OAT 0

.~

-

_______

1<:.--_----=0"-0--"-0_7__-,~

{

"0" WORD FLG
INVALID WORD FLG

H :~ACGS ~1_'~ ~"'~ '*S~'f';~"'~g,:;~ ~;~i'7;T~ O~" M[, _ P~-L~-ETlj-E;: - = - =:::1: ~~~~~~:gER

XMIT NRZ

COM1553A{

DATA REQUEST
DATA AVAIL
RCV INTERRUPT

TX CLK
TX ENABLE
SEND DATA

HAND
SHAKES

!!~A'::!'~0: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ '--'

I-T'"-X"'I~N'icTj;iER~R~U~P~T~"'-----1
I-~R~E~A~D~D~A:#TA~E~N¥;BL---__I

1-~:=iTtAijKE;;.D~AT;Af;EN~B;L~=====~
STATUS WD ENBL

I

«
::;
CONTROL {

.15
JaR
I

BLOCK DIAGRAM 2

AD1-AD5
TERMINAL
ADDRESS

36
--------------- - - - - - - -

Z

··0·· MESSAGE FLG

RCV CLK

~

'-

DATA

o
<..?

INTERRUPT ACK
TX MODE
BUS CONTROLLER

DESCRIPTION OF PIN FUNCTIONS

PIN NO.

NAME

SYMBOL

FUNCTION

1

"0" MESSAGE FLAG

0MF

The ZERO MESSAGE FLAG output is set when the 7th
through 11th bits of the NRZ serial input data in a command
envelope (see figure 1) are zero. 0MF is an open drain output.

2

"0" WORD FLAG

0WF

The ZERO WORD FLAG output is set when the 12th through
16th bits of the NRZ serial input data in a command envelope (see
figure 1) are zero. 0WF is an open drain output.

3

INVALID WORD
FLAG

IVWF

The INVALID WORD FLAG output is set when the word just
received has an invalid parity bit or invalid format. IVWF is an open
drain output.

4

DATA AVAILABLE

DTA AVL

DATA AVAILABLE is set when a word received is ready to be read.
When the COM 1553A is the bus controller, DTA AVL occurs on
command, status or data words. When the COM 1553A is a remote
terminal, DTA AVL is set only on data words. DTA AVL is an open
drain output.

5

RECEIVE INTERRUPT

RCVINT

RECEIVE INTERRUPT is set to zero when the 6th bit follo~
command sync is a zero and thefirst5 bits match AD1-AD5. RCV INT
is reset to one by fA or POR, or if the line is not active for 32
receive clocks.

6

TRANSMIT INTERRUPT

TXINT

TRANSMIT INTERRUPT is set to zero when the 6th bit following a
command sync ~a one,and thefirst5bits matchAD1-AD5. TXINT is
reset to one by IA or POR.

7

COMMAND SYNC

CMD SYN

COMMAND SYNC is an input from the Manchester decoder and
must be high for 16 receive clocks enveloping the receive NRZ data
of a command word.

8

DATA SYNC

DTA SYN

DATA SYNC is an input from the Manchester decoder and must be
high for 16 receive clocks enveloping the receive NRZ data of a
data word.

9

RECEIVER NRZ

RCV NRZ

Receiver serial input from Manchester decoder. Data must be stable
during the rising edge of the receive clock.

10

STATUS WORD
ENABLE

SWE

SWE is the output enable for the following open drain outputs:
0MF
0WF
IVWF
DTA AVL
DTA RQ
MSG CPLT

11

POWER ON RESET

POR

POWER ON RESET. Active low for reset.

12

INTERRUPT ACKNOWLEDGE

1A

fA resets TX INT, REC INT, 0MF, 0WF and BRD CST. fA may occur
between the trailing edges of receive clocks 6 and 10, or between the
leading edge of receive clock 12 and the falling edge of receiveclock
15, or after the falling edge of clock 17.

13

RECEIVE CLOCK

14

VALID WORD

RCV CLK

The RECEIVE CLOCK is synchronous with the Receiver NRZ input
during the command sync or data sync envelopes.

VW

This input is driven by the VALID WORD output of the Manchester
Decoder. VW should occur immediately after the rise of the first
RCV CLK following the fall DATA SYNC or COMMAND SYNC.

37

I

DESCRIPTION OF PIN FUNCTIONS

PIN NO.

NAME

15

SEND DATA

16

DATA REQUEST

17

MESSAGE COMPLETE

18

SYMBOL

FUNCTION

SD

SEND DATA is a "handshake" signal received from the Manchester
encoder indicating that the encoder is ready for the COM 1553A to
transmit data. SD will bracket 16 transmit data clocks. The contents
of the transmitter buffer will be transferred into the transmit register
when SD is low.

DTA RQST

DATA REQUEST is an open drain output which is set high when
the transmitter holding register is ready to accept more data.

MSG CMPLT

In the receive mode the MESSAGE COMPLETE output is set low
when the appropriate number of data words have been received. In
the transmit mode, MSG CM PLT indicates that the appropriate
number of command, status or data words have been transmitted.
When the COM 1553A is a bus controller, MSG CMPLT will be
asserted low when 33 command status or data words have been
transmitted. MSG CMPLT is an open drain output.

TRANSMIT ENABLE

TXENA

A TRANSMIT ENABLE signal will be sent to the Manchester
Encoder to initiate transmission of a word. TXENA is generated
under the following conditions:
1) COM 1553A is a bus controller: A TXMODE pulse will setTXENA.
A second TXMODE pulse will reset TXENA.
2) COM 1553A is a remote terminal. A Transmit Command from the
Controller will cause a TRANSMIT INTERRUPT (see pin 6). When
this is acknowledged by a TXMODE pulse from the system, TXENA
will beset.
TXENA will then be reset by either
A) Send Data Command associated with the last data word.
B) a second TXMODE pulse.
3) COM 1553A is a remote terminal. The falling edge of a DATA
SYNC associated with the last data word of a message while in the
receive mode. TXENA will be reset during the next SEND DATA
envelope.

19

TRANSMIT CLOCK

TXCLK

Transmitter shift clock.

20

TRANSMIT NRZ

21

BUS CONTROLLER

XMIT NRZ
BC

Serial data output to the Manchester Encoder.

Be determines whether the COM 1553A is acting as bus controller
(BC

TXMODE

TXMODE is a system input controlling transmission. See TXENA
(pin 18).

TAKE DATA ENABLE

TDE

TDE is an input from the system initiating transmission. Two TDE
pulses are required for each 16 bit data word, one for each 8 data
bits placed on D0-D7.

DATA BUS

D0-D7

Bidirectional 8 bit Data Bus to the system. D0 is the LSB. D0-D7
present open drain outputs.

READ DATA ENABLE

RDE

RDE is an input from the system instructing the COM 1553A to place
the received data onto D0-D7. Two RDE pulses are required per 16
bit data word, one for each 8 bits.

AD5-AD1

AD1-AD5 provide addressing to the COM 1553A. Each input has a
pull-up resister allowing Simple switching to ground to select the
user address.

22

TRANSMIT MODE

23

24-31
32

33-37

= 0) or as a remote terminal (BC = 1).

ADDRESS

38

POWER SUPPLY

39

BROADCAST

40

GROUND

VCC
BDCST
GND

+5 Volt supply.
BDCST is set low when a "broadcast" command word (th~address
bits all set to "one") is being received. BDCST is reset by IA.
Ground

38

OPERATION ... RECEIVE
The COM 1553A is considered in the receive mode when
TXENA = o. The most significant bit of both command
and data words is received first.
Message reception is initiated when CMD SYN goes
high. The next 16 receive clocks are used to shift serial
data into RCV NRZ.

MOD~

If 32 clocks are received after the rising edge of CMD
SYN or DTA SYN an "Idle Line Reset" condition exists.
This implies that a new CMD SYN or DTA SYN has not
yet been received within 16 clocks of the fall of the
previous sync signal. The "Idle Line Reset"will reset the
following signals:
REC INT
"0" MSG FLG
fXTN'F
"0" WRD FLG
BRD CST

The first 5 bits of a command word designate a remote
terminal address. These 5 bits are compared with AD1-5.
Should the address bits compare, the sixth bit is
examined. If it is a zero, a RECEIVE INTERRUPT is generated. If it is a one, a TRANSMIT INTERRUPT is
generated.
Bit fields 7-11 and 12-16 are examined for all zeros. All
zeros in bitfield 7-11 denotes a "ZERO MESSAGE" and all
zeros in bit field 12-16 denotes a "ZERO WORD."
Receipt of a data word is indicated when DTA SYN
goes high.
When DTA SYN or CMD SYN goes low, the contents of
the 16 bit receive register are loaded into the receive
buffer. The buffer is organized into two groups of 8 bits
each. The most significant 8 bits (byte 1) will be enabled
onto the 8 bit data bus on receipt of the first RDE pulse
(RDE1). The second byte will be enabled on receipt
of the second RDE pulse (RDE2).
A DATA AVAILABLE is generated for data words only.
However, data will be available on D0-D7 for both command and data words.

When the commanded number of data words have been
received, a MESSAGE COMPLETE signal is generated.
As the transmitter and receiver registers operate
independently, the COM 1553A will receive its own
transmission. The following signals are inhibited during
transmission:
BC =0

BC

=1

DAT AVL
IVWF
RECINT
XMTINT
0MG
f/N'oIF
BRD CST
JAM MESSAGE ERROR*
*JAM MESSAGE ERROR is an internal signal. See
OPERATION ... TRANSMIT MODE.

RECINT
XMTINT
BRD CST
0WF
0MF
JAM MESSAGE ERROR*

OPERATION ... TRANSMIT MODE
The COM 1553A is considered in the transmit mode
when TXENA = 1. This is caused by a TXMODE pulse
(see description of pin functions, pin 18)~ The TXMODE
pulse in turn is a system response to a transmit
command from the receiver.

the least significant 2 bits of the first 8 bit byte, and a
TDE2 will load all 8 bits of the second byte. Note that
these TDE pulses must be sent (and data presented)
before the first SD = 1 response from the Manchester
Encoder.
A JAM ADDRESS occurs when 1) a transmit command
is addressed to the COM 1553A 2) A TXMODE pulse is
received and 3) a valid word signal is received. Upon a
JAM ADDRESS the COM 1553A will load its address into
the first 5 bits of the transmit register.
Alternatively, a JAM ADDRESS will also occur at the
fall of the last data sync after valid receive command
has been detected.
The JAM ADDRESS function will be inhibited if a "0"
word and "0" message condition exists in the command
word. The JAM ADDRESS will be reset by the leading
edge of SEND DATA.
The JAM MESSAGE ERROR function occurs when, in
the receive mode, a data word is not followed by a
VALID WORD.signal. JAM MESSAGE ERROR consists
of loading a one in the sixth bit location of the transmit
shift register (the message error location).
JAM MESSAGE ERROR is inhibited when the transmit
command word contains "0" Message and "0" Word
fields.
When the commanded number of data words has been
transmitted a MESSAGE COMPLETE signal will b!il
generated.

When the Manchester Encoder receives TXENA = 1, it
will respond with SEND DATA = 1. The COM 1553A will
then send the system a DATA REQUEST.
Data-is loaded into the transmitter data buffer from the
8 bit data bus by pulsing TDE. The 8 most significant
bits are loaded in by the first TDE pulse (TDE1), the 8
least significant bits by the second TDE pulse (TDE2).
When SEND DATA (pin 15) is low, the transmitter shift
register inputs will follow either the transmit buffer
output, JAM ADDRESS or JAM MESSAGE ERROR signals. When SEND DATA is high, the shift register parallel
inputs are disabled and the shift register contents are
shifted out in NRZ form using the 16 negative edges in
the send data envelope.
To facilitate transmission of the status word from a
remote terminal. the COM 1553A will "jam" the first
(most significant) 6 bits of the status word into the
transmit register when BC is high. These bits will
automatically be sent at the first SEND DATA pulse. In
general for MIL-STD-1553A the remaining 10 bits will
normally be all zeros and will automatically be sent out
as such. If it is desired to send additional status
iriformation (for MIL-STD-1553B). a TDE1 pulse will load

39

GENERAL OPERATION NOTES
1. BUS CONTROLLER. When BC = 0, signifying that the COM 1553A is the bus controller the following is true:
A. DTA AVL is generated on the rising edge of the 17th receive clock following a Command Sync or Data Sync. This
allows the bus controller to receive command, status or data words regardless of their address.
B. TXENA is contingent only on TXMODE. A bus controller can therefore transmit whenever it desires.
C. The jam functions are inhibited.
2. INVALID WORD FLAG. When BC = 0, IVWF will be set if the Valid Word input (from the Manchester decorder) does
not go high following receipt of all words. This includes words received from the same device's transmitter. (This
provides a validity test of the controller transmission).
When BC = 1, IVWF will be set if Valid Word does not go high following receipt of all command and address words
addressed to the terminal.
IVWF will be set for the following conditions:
Message type
Transit Group

Word
Transmit command
Status word
Data word

Terminal is
receiving
transmitting
transmitting

Receive Group

Receive command
Data word
Status word
Receive command
Transmit command
Status word
Data word
Status word
Receive command
Transmit command
Status word
Data word
Status word

receiving
receiving
transmitting
receiving
receiving
receiving
receiving
transmitti ng

Receive/Transmit
Group (this
terminal addressed
to receive)
Receive/Transmit
group (this terminal
addressed to
transmit)

IVWF generated
yes
no
no
yes
yes
no
yes
no
no
yes
no
no
yes
no
no
no

receiving
receiving
transmitting
transmitti ng
receiving

3. POWER ON RESET. During power-up, paR is a low to high exponential with a minimum low time, after the
supply is within specified limits, of 10 microseconds. paR may also occur asynchronously anytime after power
has stabilized.
paR initializes the following outputs:
QJMG
QJWF
BRD CST
XMTINT

TDE
DTA AVL
TXENA
DTA RQ

RECINT
MSG CMPLT
IVW
RDE

The following circuit may be used to implement paR.
TO OTHER SYSTEMS
10K

2mfd

I
IN914 orequiv.

4. WORD COUNT: Word count is decoded as follows:

01 02 03 04
0 0 0 0
0 0 0 1
1 1 1 1
0 0 0 0

05 Word Count
1
1
0
2
31
1
32
0
40

TRANSMIT TIMING FIGURE 1

~18-i-19-i-20--1
TXCLK

TXENA

~

SEND DATA _ _ _ _ _ _ _ _ _ _ _ _

~--------~!~I------~

1'00----16 transmit e'oeks-----.,.~I'-_ _ _ _ __

XMITNRZ _

MSB

MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range ....................................................... -55°C to +125°C
Storage Temperature Range ......................................................... -55°C to +150°C
Lead Temperature (soldering, 10 sec.) ......................................................... +325° C
Positive Voltage on any Pin, with respect to ground .............................................. +8.0V
Negative Voltage on any Pin, with respect to ground .............................................. -0.3V

'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute
Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes
or "glitches" on their outputs when the AC power is switched on and off. In addition, voltage transients on the
AC power line may appear on the DC output. If this possibility exists it is suggested thata clamp circuit be used.

ELECTRICAL CHARACTERISTICS (TA
PARAMETER
DC CHARACTERISTICS
Input Voltage Levels
Low Level, VIL
High Level, VIH
Output Voltage Levels
Low Level VOL
High Level VOH
Low Level VOL
Output Leakage, ILo
Input Current, AD1-AD5
Output Capacitance
Input Capacitance
Power Dissipation

== -55°C to 125°C, Vee == +5 ±5%, unless otherwise noted)
MIN

TYP

MAX

UNIT

0.8

V
V

0.4

V
V
V
J.lA
J.lA
pf
pf
mW

3.0
3.0

4.0
0.4
10
60
5
10

41

10
25
500

COMMENTS

IOL == -1.6 mA, except open drain
IOH == 100 J.lA, except open drain
IOL == -1.6 mA, open drain output
VIN

== OV

PARAMETER
AC CHARACTERISTICS
Clock Frequency
Clock Duty Cycle
Rise and fall tim s, l~bTEDE
TXMODE, S E,
rise and fall times, all
other iriputs
receiver cloGk-NRZ
receiver clock-sync delay
receiver clock-VW delay
VW reset delay
transmit clock-TX ENA delay
TX ENA pulse width
transmit clock-send data set-up
transmit clock-send data hold time
transmit clock fall to NRZ
transmit clock rise to NRZ
TX MODE pulse width
TX MODE to TX ENA delay
VALID word to TX ENA delay
Data sync to TX ENA delay
TX ENA reset delay
DATA SET-uptime
TDE pulse width
Data Hold time
Cycle time
DTA RQST Delay
Output Enable time
RDE Pulse width
receive cycle time
Flag delay time
Output disable time
SEND DATA delay
TDE off delay
TDE1 delay
SYN to RDE
RDEtoSYN
Status word Enable
Status word Disable
Flag delay time
VW delay time
IVWF delay time
DTA AVL delay time
DTA RQST delay time
8RD CST delay time
8RD CST pulse width
flag reset delay
Interrupt delay
IA pulse width
Interrupt pulse width
Flag reset time
DTA AVL reset delay
IVWF reset delay
MSG CMPLT turn-on delay
MSG CMPLT turn-on delay

0

SYMBOL

MIN

TYP

MAX

UNIT

fT, fR

980
45

1000
50

1020
55

KHz
%

tr, tf

20

ns

tr, tf

50
65
85
100
500

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

tRN
tSR
tRY
tvs
tTx
txw
tTs
tST
tTN
tNT
tMW
tMX
tvx
tox
tsx
tOl
t02
t03
tD4
tDS
t06
tD7
tD8
tD9
tOl0
tOIl
t012
tD13
tD14
t01S
tSE
tso
tCF
tcv
tCI
tCD
tSR
tRB
tBW
tlB
tRI
tlA
tlW
tFR
tRD
tRY
tMR
tMF

25
60
40
140
0
95
150
750
750
750
750
100
150
100
450
450
100
150
450
450
100
2.5
1.5
500
500

16000

17000

3.5

J1s
J1s
ns
ns

2.5
100
100
1
90
450
500
450
2
1
750
1.5
150
1

J1s
ns
ns

J1s
ns
ns
ns
ns

J1s
J1s
ns

J1S
ns

J1s
450
750
750
1.5
1.5

42

ns
ns
ns

J1s
J1s

COMMENTS

figure38
figure38
figure38
figure3C
figure4A
figure4A
figure 48
figure4C
figure48
figure48
figure5A
figure58
figure58
figure5C
figure5C
figure6A
figure6A
figure6A
figure6A
figure6A
figure 68
figure68
figure 68
figure 68
figure68
figure6C
figure6C
figure6C
figure flD
figure6D
figure8A
figure8A
figure88
figure88
figure88
figure88
figure8C
figure8C
figure8D
figure 8D, 8E
figure8D
figure8D
figure8D
figure8F
figure 8F
figure8F
figure 9A, 98
figure 9A, 9C

RECEIVE TIMING FIGURE 2
RCV ClK

II

CMD SYNC

II

DATA SYNC

RNRZ

I::

MSB

I

lSB

r--=

VW

II

RECEIVER INPUT TIMING FIGURE 3

TRANSMITTER TIMING FIGURE 4

3A

4A

RevelK
COMMAND!
DATA SYNC

------,~

-

TXCLK

TXENA

~'"'

1h CLOCK CYCLE

!..

38
ANRZ

Rev elK

48

-,.~

,--TXClK

-

CMO/DATA SYNC

r

~

~

\

-i

,,,~

'"'~

SEND DATA

_h,_ 1-'''_

1---, .. _
XNRZ
VW

3C

4C

CMD/DATA SYNC

vw

TXClK

=J1"

SEND DATA

43

~

~.~

/

TRANSMIT ENABLE (TX ENA) TIMING FIGURE S

SA
I

h~w-.:u:;=

-----,U

1-\

I

TXENA

-----------tM-,~-rI--~~
SB*

L

R~~~r ~:LI5~IL6~1~7~1~8LI9~ll~01~1~11~12~1~13~ll~4Lll~5~ll~61~1-L1-L1~~I~ ~

-JI

*CMD SYNC

_____

TX MODE, NEGATIVE TRANSITION WILL
OCCUR IN CROSS-HATCHED AREA.

I

I

--.J

~XXXXXXXX)l

~IJiSmin

r-

::::.Jis~m:.::i~n---II r---

1-=---:-1

I
I
I
I

ru-

I
I

I
I

I
I
I
I

I

I

I

~------\

-! F 0.6 Jis typ

VALID WORD

--------------------------~,

TX ENA

-4

I

\1

Ftvx

LAST DATA
SEND

sc**

~ \
) ~

BC= 1
DATA SYNC

-----.l

RCV BIT TIMES

I

~

1 I 2 I ~ }\-L--'-,,----,-=16
I 15
-+I----IH=
I

II
I

TX ENA

SEND DATA

----------------I-,,-~~!~~~
--------~(

I

rJ

**THIS IS THE LAST DATA WORD BRING RECEIVED. THIS TERMINAL PREVIOUSLY
HAD RECEIVED A REC CMD WORD WITH OUR ADDRESS AND A REC/XMIT BIT = 0
DURING THIS MESSAGE SEQUENCE. TX ENABLE IS SET BY MSG CMPLT
FUNCTION AND RESET BY RECEIPT OF SEND DATA.

44
-------------------

~

....

-_.

_.-_._---

DATA BUS TIMING FIGURE 6

6A
013-07-

BITS 0-7

BITS 8-15

TOE

DlA ROST

IL--

~I"

I,,~ ~Io._

_

leI

I,,~

_te, _
_Io.~

I"

6B
00-07-

BITS 0-7

BITS 8-15

ROE

DlA AVL
L...-

IVW

-10.-

_1._

_1"._

~Ioo

I..

_

L...-

10"_

I..

I ..

DATA BUS TIMING FIGURE 6

IA RESETS FIGURE 7

6C
I 1 I 2 I 3 I 4 I 5 16 I 7 I

TXENA

SEND DATA

TOE

-i=""
'fITE2 STATE

~

I

CMDSYN~
BRD CST

I

r-

I...

I••

l
--j

TOEI STATE
"O"MSG FLG

"O"WRDFLG

NOTE: SEND DATA RISING EDGE INITIALIZES TOE TO TOEl STATE
INVW FLG

DTA AVL

(DATA SYNC == 1)
TX INT OR REG INT

60

iA
CMO SYN
0'

OTA SYN

ROE

a 191101111121131141151161171181191201

REC elK

1"r--1J==!45

II
II
II
II
II

I
I
I
I
I

I
I
I
I
I
I
I
I
I
I
I
I
I

I
I
I
I
I
I
I
I
I
I
I
I
I

~
I
I

~

II
II
II
II
II
II
II

I
I
I
I
I
I
I

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

I
I
I
I
I
I
I
I
I

:r

~

7

10
RISES FALLS

TA OCCURRING

II

II
II
II
II
II
II
II
II

"II
II

III
III
III
III
III
III
1'1
III
III
III
!II

IWi
Ij
II

1
1r
II

iWJ
,

I
I
I

I
I
I
I

t2

15

~

RISES FALLS

I
I
I
I

~

17

FALLS

DURING ZONE A RESETS: BRD CST. TX INT. REG INT.

TA OCCURRING DURING ZONE B RESETS: BRD CST. TX INT. REG INT. '0" MSG FLG.

TA OCCURRING DURING ZONE C RESETS: BRD CST. TX INT. REC INT. '0" MSG FLG.
"O"WRD FLG,

I

STATUS FLAGS FIGURE 8

8A

g

~'l

--ll-=,
. J----'~~,Jl---

STATUS BITS

REC elK

o MSG FLG
0WRD FLG

88

vw
IVWF

DTA AVL

Notes:1. SWE = 0
2. IVWF and OTA AVl reset by RDE2 or REC eLK 14 of the

next word

SEND DATA

8e

OTA RQ

I+- 4 ---+i-- 5 ---+i-- 6 ---+i-- 7 ---+i-- • -+- 9
REC elK

80
TXINT. REC INT

I

"0"WRD FLG,

8E

","MSGFLG

______

~

~~-t.----1--~~~~~~~--------~

U-

DTAAVL

IVWF

RDE

'RDE2
If ROE is not used to reset IVWF and ROE. then they are
reset by ReV elK 14 as shown below.

8F

f+--13-------o-1---14 -------1---15 -------0-1---16-------1
Rev elK
OTA AVL

IVWF

~
I ..

46

MESSAGE COMPLETE FIGURE 9
BUS CONTROLLER MODE
BC

MSG CMPLT

TX MODE

9A
SEND DATA

~I

II

-l~

~l
--11

I~

I

I'i

I

I~!--I.,I

HI.,

'WORD COUNTER IS PRESET TO 33
"MSG CMPLT SET
DATA PULSE

I., MAX

AFTER RISE OF 33RD SEND

REMOTE TERMINAL, RECEIVE COMMAND RECEIVED

r

-------------1111-------

f-~

BC ~

CMD SYNC

I -----------lljl------I
I
I

L1l

RCV CLK 16

9B

I

1

---+--------ll~

DTA SYNC

I
I
I

,I1 - - - - - - - - - - 1 \ \

I

MSG CMPLT

I--l I.,

I

'WORD COUNTER PRESET TO COUNT IN COMMAND WORD
"MSG CMPLT GENERATED BY LAST DATA SYNC OF
THE MESSAGE GROUP

REMOTE TERMINAL, TRANSMIT COMMAND RECEIVED
,--------~\f_I-------------

BC~

CMD SYNC

RCV CLK

9C

~I~--------

LJi

SEND DATA

-----l\

r--1

\~

UL....--

MSG CMPLT

I

.,

-

'WORD COUNTER PRESET TO TRANSMIT COMMAND WORD FIELD
PLUS 1. THIS ALLOWS FOR THE STATUS WORD.
"MSG CMPLI GENERATED BY THE LAST SEND DATA OF
THE TRANSMIT MESSAGE GROUP.

47

TYPICAL SYSTEM OPERATION

1_------=~10EXAMINE>.=~O

I

6th BIT

~-.~

____

~1
L--,~

-r;J
8
TO MPU

r--'-.

FROM MPU

{;;7

Y8

'SEE FIGURE 7 FOR ALLOWABLE TIMES TO SEND iA

48

o

49

OPEN DRAIN OUTPUT
FIGURE 10

INTERNAL LOGIC

00-07 INPUTI OUTPUT
FIGURE 11
Vee

INTERNAL LOGIC

J2
OTHER OUTPUTS
FIGURE 12
Vee

INTERNAL LOGIC

STANDARD MICROSYSTEMS
CORPORATION
3S",,""cus8lv(l~NYlI18l

,S!6'Z/33100

N,'X·510nlill!9I!

Circuli diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore. such information does nol convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

50

----- - - - - - - - - - - - - - - - - - - -

COM15538
~PCFAMILY

PRELIMINARY

MIL-STD-15538 "SMART®"
o Support of MIL-STD-1553B
o Operates as both Remote
Terminal and Bus Controller
o Manchester II Serial Biphase
Input/Output
o 16 bit Microprocessor
compatible
o Command/Data Sync
Detection/Identification
o Automatic Command
Response Generation
o On-Chip Address Recognition
o Error Detection For:

o
o
o
o

Sync Errors
Parity Errors
Word Count Errors
Bit Count Errors
Invalid Manchester Code
Incorrect Address
Incorrect Bus Response Time
TTL Compatible
Recognizes Mode Codes and
Broadcast Commands
Provides DMA handshaking
signals
COPLAMOS® n-Channel
MOS Technology

I

PIN CONFIGURATION

FEATURES

I"

U

D"
D"
D"
D"

40
41
42
43
44

3

5
6
7 8 91011121314151617

Df1

N

0

3

28
27
26
25
24
23
22
21
20
19
18

-

PACKAGE: 44-pin LCC

Rm
VC
WE
Vee
D,
N/C
D,
D,
D,
D3
D,

38 MANOUT

37 MANour

D12

"Wlet ulZ Zu..
ClCl8~~zZZ~ClCl
~ ~ :H
....
~

39 GNO

Dl0

3938373635343332313029

CSTRA
MANOUT
MANOUT
GND
DB
N/C
D,

40 08

D9

I~OOa:Ill>Z>UO:E_
Ie I~ IG(!i 8 ~ ~ letti ~ IU I:::;

D13

36 CSTRA

D14

35 jjffi

D15

34 CD

i3C

TXMODE

8

33 RT

POR

9

32 BGACK

12MHz eLK 10

31 VOO

MANIN 11

30 veB

MANIN 12
MCF 13

00 14
01 15
02
03
04
05
06

16
17
18
19
20

29 CSTR
28 DTACK

Me

27

261M
25 RW

24
23

vc
WE

22 Vee

21 07

PACKAGE: 40-pin D.i.P.

GENERAL DESCRIPTION
The COM1553B SMART® (Synchronous Mode Avionic
Receiver-Transmitter) is a 40-pin COPLAMOS® n-Channel
MOSIVLSI circuit designed to simplify the interface of
a microprocessor or buffer to the serial MIL-STD-1553B
data bus.
The COM1553B is a double buffered serial to parallel,
parallel to serial converter. It receives serial Manchester \I
biphase encoded data from a 1553B bus receiver and converts it to 16 bit parallel data. When receiving Manchester
II data, the COM1553B detects and identifies sync polarity,
reconstructs the clock, detects zero crossing, checks for the
proper number of bits and performs a parity check on the
incoming data. In addition to parity check, the COM1553B
also checks for sync errors, invalid Manchester code,
improper word count, incorrect address and incorrect bus
response time. The transmitter in turn, accepts 16 bits parallel gata and serially transmits it as Manchester \I data,

appending the appropriate sync and parity.
The COM1553B recognizes protocol commands, and
automatically generates the proper response, thereby offloading what otherwise would be microprocessor tasks. This
feature eliminates critical software timing requirements.
The COM1553B is designed to work both as a Bus Controller and Remote Terminal, making it universal within the
MIL-STD-1553B environment. The COM1553B automatically loads and recognizes its own address. It determines
the type of transfer required in both the Bus Controller and
Remote-Terminal modes and generates the proper control
signals to complete the transfer. It automatically transmits
the status word and detects message errors and mode
commands. Furthermore, it generates the control signals
for DMA operation, therefore eliminating processor
intervention.

51

'5VDC~Vcc

16 BIT
BIDIR
BUFFER

I

16 BIT
DATA BUS

t12VocivrJd

5VDC~

Vhb

I

I

f-...J.-,--.....~ R W

I

-

DATA

I
I

I
I
c:.n

..

~-t--~WE

t---r----I..~ CSTRA

MANCHESTER
ENCODER
DECODER

~~gJENCE 1

&

LOGIC

HIGH SPEED
ERROR
CHECKING
LOGIC

MANIN
I\)

READY

6 BIT
COUNTER
RESPONSE
TIMER

.. INVALID MSG

~-t--~.

CD

~--'--""-VC

MANIN

f---+-....~ DTR

MANOUT

..

I--~-- MC

MANOUT

5 BIT
WORD COUNTER
& MODE
DECODE
LOGIC
12MHz~

I

RTBC

I.

CSfR

I ..

BGACK

I•

-'=

I
-~
O'"--oj

I"

I

I
I
_J

'C","",W

L _______ _
FUNCTIONAL BLOCK DIAGRAM

DTACK

MCF

DESCRIPTION OF PIN FUNCTIONS
PIN NO.
1-7,14-21,
40
8
9
10
11
12
13

NAME
16-bit Data Bus

SYMBOL
DO-D15

Transmit Mode

TXMODE

Power On
Reset
12 MHz Clock

POR
12MHz
ClK
MANIN

Complementary
Manchester In
Manchester In

MANIN
MCF

22
23

Mode Code
Flag
Power Supply
Write Enable

24
25

Valid Command
Read/Write

VC
R/W

26

Invalid
Message

1M

27

Message
Complete
Data Transfer
Acknowledge
Command
Strobe

MC

28
29

30
31
32

VCC
WE

DTACK
CSTR

Power Supply
Power Supply
Bus Grant
Acknowledge
Remote
Terminal/Bus
Controller
Command/Data

VBB
VDD
BGACK

DTR

38

Data Transfer
Request
Command
Strobe
Acknowledge
Complementary
Manchester
Output
Manchester

39

Ground

33

34

35
36

37

RT/BC

CID

CSTRA

MANOUT

MAN OUT
L

I

GND

FUNCTION
Three-state bidirectional data lines used to transfer Command, Data, Error and
Status Words between the COM1553B and external memory.
This output signal when high indicates that the COM1553B is transmitting information on the 1553B bus.
Input signal used to initialize or reset the Error registers. The RT address must be
reloaded after POR is issued.
12 MHz clock input.
This input is low when there is no data on the bus. A high level indicates that the
data is in its negative state (Refer to receive waveform, figure 3).
This input is low when there is no data on the bus. A high level indicates that
the data is in its positive state (Refer to receive waveform, figure 3).
Output signal that is active high when a mode command (all I's or all O's in subaddress) has been detected.
+ 5 volts DC supply.
Output signal. When low, WE indicates that the data on the 16 bit data bus is stable and can be written into the external memory.
Output signal that is pulsed high to signify the reception of a valid command.
Output signal that indicates whether a DMA transaction is a COM1553B read
(when high) or a write (when low) operation.
Output signal which is pulsed low at the same time as MC to indicate that a message error has occurred.
1M is also pulsed low while MC remains high if there are errors in the Command
word with matching address.
Output signal used as either an interrupt or flag to the processor whenever a
COM1553B transaction has been completed.
This input signal when low indicates that the Data Transfer Request
(DTR) and BGACK has been acknowledged and data is on the data bus.
This input signal when low is used to inform the COM1553B that a Command
Control Code is available in external memory. When the COM1553B is ready, it
issues a Command Strobe Acknowledge and initiates a memory read cycle to
load the Command Control Code bits CB2-CBO.
- 5 volts DC supply voltage.
+ 12 volts DC supply.
This input signal, when low, indicates that the processor has acknowledged DTR
and relinquished the data bus.
When this.l!Jj;)ut is high the COM1553B operates as a Remote Terminal.
When RT/BC is low, the COM1553B operates as a Bus Controller.
This output signal during memory write operations indicates either a Command
or Data Word transfer. A low level indicates that the COM1553B is writing a Data
Word, Status Word, the contents of the Error Register, or the contents of the last
Command Register into external memory.
A high level indicates that the transferred word is a Command Word. During
memory read operations this output is low. It goes high to indicate that data has
been latched internally and the read operation is completed.
Output signal that initiates a DMA transfer with the processor.
This output pulse acknowledges the receipt of the command strobe and initiates
the Command Control Code (CB2-CBO) transfer.
This output signal is high when the COM1553B is not transmitting.
A low level indicates that output data is in a positive state (refer to driver
waveform, figure 4).
This output signal is high when the COM1553B is not transmitting.
A low level indicates that output data is in a negative state (refer to driver
waveform, figure 4).
Ground

53

FUNCTIONAL DESCRIPTION
The COM1553B is organized into the following five
sections:

DO), DTACK and BGACK are generated by the processor
and these bits are loaded into the COM1553B 3-bit latch
decode register. The command is then decoded in accordance with Table A. Timing associated with loading these
control bits into the COM1553B is shown in Figure 1.

Manchester Encoder/Decoder
This section performs the manchester encoder and
decoder functions and code error check. The receiver continuously monitors the MANIN and the MANIN input lines
for a valid sync. After the reception of the 3 bit sync, the
receiver is in full synchronization. It then checks for transition errors and correct (odd) parity. If an error is detected in
the Command Word the receiver resets itself, pulses 1M and
waits for another valid sync. If any errors are detected in
Data and Status Words, the appropriate error bits in the
Status and Error register are set.
The transmitter section encodes the NRZ data from the
data bus into Manchester II and appends, depending on
word type, the proper sync and parity.

Transmit Last Command
Allows the State Sequencer to bypass a memory read
cycle to external memory and transmit the Last Command
from the TRLC register following the Status Word transmission.
Broadcast
When the address field of the Command Word is all ones
(11111), the State Sequencer is informed that a Bus Controller or a Remote Terminal is transmitting a Broadcast
Command.

State Sequencer Logic

Word Count Zero
Input from the 5-bit counter and count decode logic
informing the State Sequencer that all Data Word memory
cycles are complete.

The State Sequencer section generates the appropriate
signals to various intemal sections to control the overall
device operation.
Inputs 'to the State Sequencer which establish its operational modes are as follows:
Remote Terminal/Bus Controller (RT/BC)
Determines whether the data terminal is operating as
a Remote Terminal or as a Bus Controller. As a result of
Dynamic Bus Allocation, any terminal shall be capable of
performing either function at different times.

Sync Input
Indicates the type of sync word just strobed into the
receive register.
Address Compare
When programmed as a Remote Terminal, the
COM 1553B compares the contents of the address register
with the address field of the received Con.,nand Word. If
the addresses compare, the State Sequencer will respond
to the received command.

Command Control Code bits D2-DO (CB2-CBO)
These Command Control Code bits determine the type
of memory operation the COM1553B will execute. Transfer
of these commands to the COM1553B are initiated by
asserting Strobe Command (CSTR) low. This informs the
COM1553B that a command is available in external memory. When the COM1553B acknowledges the CSTR signal,
it sets the CSTRA output low. The CSTR must be reset within
1.5 f,Ls after CSTRA. The COM1553B then initiates a memory read cycle by setting R/W high, C/O low, and DATA
TRANSFER REQUEST (DTR) low. When the Command
Control Code bits are valid on the bidirectional data bus (D2READ/WRITE (R/W)...Jr

Any Error
This input to the State Sequencer indicates that one of
the seven possible errors have been set in the error register
at the end of a message (Refer to Error register).
Contiguous Word
Set if there is a transition 2 f,Ls. after the parity transition
of the last word, this signifies that a contiguous word follows the word presently in the receive register (Refer to
figure 5).

----------------------------

WRITE ENABLE (WE)..J
DATA TRANSFER REQUEST (DTR) _ _ _ _--,

LOW UNTIL
DTACK _ _ _ _ _ _ _- - ,

BGACR RECOGNIZED
SOME DELAY OF MS INDICATES DATA VALID

COMMAND STROBE (CSTR) - - - ,
MEMORY STROBE (MS)
COMMAND STROBE
ACKNOWLEDGE (CSTRA)
BUS GRANT ACKNOWLEDGE (BGACK)
DATA
COMMAND/DATA (C/O)

.....
' _--'-'H""O"'LD""C"'S"'T.!.!R""U.:.:.NT.!.!IL"-"'CS"'T.!.!R"'A_---'
L -_ _~H~O=LD~DA~T~A~~U~NT~IL~L~A.!.!T=CH~E~D~_~

HOLD BUS UNTIL DMA COMPLETE

------~:«==~CO~N~T~F':()L BITS CB2, CB1, CBO
LOW UNTIL BITS LATCHED INTERNALLY

FIGURE 1:
BUS CONTROLLER TIMING SEQUENCE
Loading the Command Control Code Bits into the COM1553B prior to
transmitting a Command or initiating a Diagnostic Sequence.

54

I

>

---------

Remote Terminal should be less than 14 fls.lfthe response
is greater than 14 fls. the response error bit is set in the
error register.

Error Detection Logic
The error detection logic of the COM1553B detects the
following errors:

Address Mismatch
An address mismatch occurs when a Bus Controller
detects a mismatch between the address of the Status Word
reply from a Remote Terminal and the Remote Terminal
address of the Command.

Improper Sync
One or more words have been received with incorrect
sync polarity (For example a Status Word with Data Sync).
Invalid Manchester II Code
One or more words have been received with a missing
transition during the 17 fls. data and parity bit time.

InternCjI Register Description

Information Field Greater Than 16 Bits
The decoder has detected a transition within one bit time
(1 flS.) following the parity bit in one or more words.

Remote Terminal Address And Status Code Register
This register is loaded when the processor issues a load
Remote Terminal Address (RTA) command. The word that
is loaded in this register consists of 9 bits of status information (00-08) and the 5-bit address (011-015). The
Remote Terminal Address may be checked any time by
reading out the Error register. The RTA and Status Code
register must be loaded before the COM1553B may respond
as a Remote Terminal.
Table 1 defines the data bus bits which correspond to the
Remote Terminal Address and Status Code register and
Status Word that transmitted. Bits DO, 02, 03 and 08 are
double buffered to allow the RT to retain this information
after the Status Code register is updated. For all legal commands, other than Transmit Last Status and Transmit Last
Command Mode command, the Status Word register is
updated with these four bits, Any Error and the Broadcast
flag. The Dynamic Bus Control and Terminal Flag bits are
modified by the appropriate Mode Code commands
whereas, the Broadcast Flag and Any Error bits are set by
the COM1553B internal logic. The Reserved Bits and the
RT address bits are transferred directly into the Status Word
register during the RTA and Status Code command.
Bits DO, 02, 03, and 05-09 are cleared after transmission for all commands except Transmit Last Status and
Transmit Last Command Mode Code.

Odd Parity Error
One or more words have been received with a parity error.
Improper Word Count
An improper word count error occurs when the number
of Data Words received is not equal to the number of words
indicated in the word count field of the Command Word. In
the case of a Mode Code without data, no Data Words
should follow the Mode command. Mode Codes with data
should consist of only one Data Word. If the contents of the
word counter are not zero, and there is no contiguous Data
Word, then the receive message is considered incomplete
(e.g., fewer words were received than indicated by the word
count in the Command word). If the contents of the word
counter are zero and there is a transition detected 2 fls. after
the parity transition of the last Data Word, then this also will
cause an improper word count. In either case, the Message
Error bit of the Status Word is set and not transmitted and
the invalid message (1M) ou!20 pin pulsed at the same time
as the message complete (MC) signal output.
Response Time
The amount of time between the end of transmission of
a Command or Data Word and the Status Word reply by a

TABLE A:
COMMAND CONTROL CODE BIT DEFINITION

DATA BITS
RT/BC 0'5 0'4 0'3 0'2 0" 010 0 9 0 8

CONTROL
BITS
CB2-CBO
0 7 Do 0 5

0 4 0 3 O2

0,

X

X

X

X

X

X

X

X

X

X

X

X

X

X

1

1

X

X

X

X

X

X

X

X

X

X

X

X

X

X

1

0

X

X

X

X

X

X

X

X

X

X

X

X

X

X

0

0

X

X

X

X

X

X

X

X

X

X

X

X

X

X

0

0

0

X

X

X

X

X

X

X

X

X

X

X

X

X

0

1

0

X

X

X

X

X

X

X

X

X

X

X

X

X

0

1

X-DON'T CARE

55

Do FUNCTION
READ DATA
X
REGISTER
LOAD RT ADDRESS
REGISTER AND
X
STATUS CODE
REGISTER
0 READ LAST CMD
READ ERROR AND
REMOTE TERMINAL
1
ADDRESS
REGISTERS
BUS CONTROLLER
0 TRANSMISSION
BUS CONTROLLER
1
RT TO RT TRANSFER

TABLE 1
Data Bus Bit
015(MSB)
014
013
012
011
010
09
08
07
06
05
04
03
02
01
00 (LSB)

RTA and Status
Code Reg. Bits
RTA Bit 4 (MSB)
RTA Bit 3
RTABit2
RTABit1
RTA Bit 0 (LSB)
Not used
Instrumentation Bit
Service Request Bit
Reserved
Reserved
Reserved
Not Used
Busy
Subsystem Flag Bit
Oynamic Bus Control
Acceptance Enable Bit
(See Note)
Terminal Flag Enable
Bit (See Note)

Internal Logic
Signals
-

Any Error
Broadcast Flag
Oynamic Bus Mode Code
command
Inhibit Terminal Flag (set)
or
Override Terminal
Flag (reset)
Mode Code command

Status Word
Transmitted
RTA Bit 4 (MSB)
RTA Bit3
RTA Bit2
RTABit1
RTA Bit 0 (LSB)
Message Error
Instrumentation
Service Request
Reserved
Reserved
Reserved
Broadcast Flag
Busy
Subsystem Flag
Oynamic Bus Control Bit

Terminal Flag

Note: When the Oynamic Bus Control Acceptance Enable bit is set, the RT will accept a Oynamic Bus Mode code
request. If this bit is reset the RT will reject a Oynamic Bus Mode Code command request. The Terminal Flag
Bit (if enabled) is only set high if no Inhibit Terminal Mode Code command has been received, or if an Override
Inhibit Terminal bit command is received.
-

Last Command Word Register
The last valid Command Word received by a Remote
Terminal is stored in an internal 16 bit Last Command Register. This makes it readily available for transmission onto
the data bus whenever the Remote Terminal receives a
Mode Command to transmit the last Command Word. The
Last Command Register contents are automatically written into external memory following a receive or a transmit
message.
As a bus controller (BC), the Last Command Register is
used to hold the command transmitted before the present
command. In RT-RT transfers this register of the BC holds
the receive command while the transmit command is being
transmitted.
The processor has the option of reading the Last Command Register of either a bus controller or remote terminal,
by issuing a Read Last Command Register command code.

Last Command register automatically into exterral memory
at the end of each command message because these registers may change before the processor has determined
the necessity of reading them. The Error register may be
read anytime during a message except during message
transfers.

TABLE 2
The 16-bit error word is defined as follows:

DATA BUS
LINE
015
014

013
012
011
010

Error Register And RTA Register
(Error Register)
A 7-bit error register is provided in the COM1553B to hold
any errors associated with the previous message. If one
or more of the 7 error types exists, the COM1553B asserts
the Invalid Message output pin (1M) at the same time that
Message Complete (MC) is asserted, cueing either a Remote Terminal or a Bus Controller that an error occUrred in
the previous message. If desired, the processor may read
out the 16-bit error word by issuing a read error register
command code. When operating as a Remote Terminal, the
COM1553B will write the Receive register, Error register and

p9

08
07
06
05
04

03
02
01
00
'Unused bits are set high.
56

ERROR BIT
DEFINITION
RT Address Bit 4
RT Address Bit 3
RT Address Bit 2
RT Address Bit 1
RT Address Bit 0
Unused
Improper Sync
Address Mismatch Error
Improper Word Count
Response Time Error
Information Field> 16 Bits
Unused
Invalid Manchester II
Parity Error
Unused
Unused

- _. . . _.

----------

Mode

Det~ction

Logic

The Override/Inhibit Terminal Flag and Dynamic Bus
Control Mode Code commands, when received by the
COM1553B, may change the state of the Terminal Flag and
Dynamic Bus Control bits of the Status Word register. The
Inhibit Terminal Flag Bit Mode Code command resets the
Terminal Flag bit.
The Override Inhibit Terminal Flag Mode Code command enables the Terminal Flag bit if it was previously disabled. Finally, Dynamic Bus Control Mode Code command
sets the Dynamic Bus Control bit in the Status Word if the
Dynamic Bus Control Enable bit is high. If the enable bit is
low, the Dynamic Bus Control bit in the Status Word remains
low when a Dynamic Bus Control Mode Cooe command is
receiveq.

Both receive and transmit Command Words for a Remote
Terminal and Bus Controller are decoded by the Mode
Detection Logic. The Mode Detection Logic examines the
following Command Word field to establish the correct
operating mode for the COM1553B (Refer to TABLE B).
Subaddress/Mode Code Field (05-09)
and Data Word Count/Mode Code (00-04)
This field Determines if the command is a normal command or a Mode command. A subaddress field of 00000 or
11111 implies a Mode command. All other codes are interpreted as a subaddress. Once a Mode Command is
detected the most significant bit of the Data Word Count!
Mode Code field is decoded. A most significant bit of "zero"
implies no associated data with the Code Command. A
"one" in this position implies that a Data Word will follow.
The COM1553B recognizes five Mode Code commands
(Refer to TABLE B). Transmit Last Command or Transmit
Last Status word Mode Code commands, when received
by the COM1553B, will automatically transfer the contents
of the Transmit ~ast Command or Transmit Last Statl!s register onto the 1553B serial bus.

Broadc!lst Mode Code
Bro§.dcast Mode Code Qommands are acknowledged if
the T/R bit is low. If the T/R bit is high all Broadcast Mode
Gode commands without associated Data words are
acknowledged except Dynamic Bus Control and Transmit
Last Status Word.
Illegal Broadcast Commands are not acknowledged; the
1M output pin is, however, pulsed low.

TABLE B
MODE CODE DEFINITION
FUNCTION
Broadcast

Mode Codes

DETECT
CONDITION
All ones in RT
address field of
CMDWD .

DETECTED
BY
Broadcast
Decode Logic

All zeros or
ones in subaddress field
ofCMD WD

Mode Code
Decode Logic

SPECIAL
CONDITIONS
Status wprd is
written into Memory
but not transmitted
MSB of Word Count
o = No data Word
1 = With Data Word

(1) Dynqmic
Bus
Control

Word Count
Field = 00000

(2) Transmit
Last
Status
Word
(3) Inhibit
Terminal
Flag Bit
(4) Override
Inhibit
Terminal
Flag Bii
(5) Transmit
Last
Command

Word Count
Field = 00010

Word Count
Field = 00110
Word Count
Field = 00111

Word Count
Field = 10010

57

COMMENTS
Address compare
must recognize all
ones as Broadcast
Word Count
is Decoded
as mode code
Dynamic Bus Accept
Bit of Status word
enabled for
transmission
Status Word remains
unchanged

Terminal Flag Bit of
Status word inhibited
until overriden
Removes Inhibit from
Terminal Flag Bit of
Status Word
Status Word
Transmitted followed
by Last Command
Register. Status Word
remains unchanged.

I

OPERATION
When operating as either a Bus Controller or Remote
Terminal, the COM1553B decodes the Command Word and
determines the type of message transfer. Having determined the type of message transfer, the COM1553B
generates the proper control and timing signals to complete the transfer (refer to Figure 2). The types of messages
are listed below:
1) Bus Controller to Remote Terminal
2) Remote Terminal to Bus Controller

~us

3)
4)
5)
6)
7)
8)
9)
10)

Remote Terminal to Remote Terminal
Mode Code without Data Word
Mode Code with Data Word (transmit)
Mode Code with Data Word (receive)
Broadcast Bus Controller to Remote Terminal
Broadcast Remote Terminal to Remote Terminal
Broadcast Mode Code without data
Broadcast Mode Code with data

Controller Transaction (RT/BC of the COM1553B set low)

The following section describes each 1553B information
transfer format from the Bus Controller viewpoint. A table
showing external memory operation is also provided for
each message format.
Note that all MIL-STD-1553B serial bus activity is initiated by the Bus Controller.

Bus Controller-to-Remote Terminal Transfer (BC to RT)
This message format covers transactions where the Bus
Controller transmits a receive Command and Data Words
to a Remote Terminal. Initializing the COM1553B is accomplished by the processor loading an external memory
address counter with the starting address of the COM1553B
memory control block (address where the Command Control Code CB2-CBO resides). The Bus Controller processor
next issues a Command Strobe (CSTR) and holds it
low until the COM1553B issues a Command Strobe Acknowledge (CSTRA). The COM1553B then responds with a
Data Transfer Request (DTR) which initiates a normal
memory cycle.
Refer to figure 1 for timing associated with loading the
Command Control Codes (CB2-CBO) into the COM1553B

prior to transmitting the Command Word.
The first memory cycle loads tile Command Control Code
bits CB2-CBO from external memory into the COM1553B
functioning as Bus Controller (BC). The BC decodes this
command to determine the type of memory transaction to
perform (refer to TABLE A). The next read cycle loads the
Command Word into the BC command register and then
transmits it onto the 1553B bus. This Command Word, while
in the command register, determines the BC mode of operation. The BC then completes this BC to RT transaction by
issuing a predetermined number of read cycles (determined by the value in the word count field of the Command
Word) and transmitting the data onto the 1553B bus. After
transmission of the last Data word, the BC initializes its
response timer, expecting a Status Word from the remote
terminal within 14 f,Ls.
After the reception of the Status Word, the BC initiates a
memory write cycle which writes the Status Word into the
external memory. If the BC doesn't receive the Status Word
within the allowed response time the message error bit
is set.

1/0

o

o

OlR

-+________--.

c/o _ _ _ _

lOW UNTIL DTACK

o

R{W

o

WE

DATA BUS

LOW UNTIL
SOON AFTER
DTACK

- - - - -...

_____

F<'i§il¥W)...._______---i,--:OD~AT~A:__">_------_{
WORD

COMMAND WRITE TO MEMORY

DATA WRITE TO MEMORY

FIGURE 2

58

DATA READ FROM MEMORY

TABLE 5
RTto RT

TABLE 3
BC to RT (The BC transmits a receive
command to the RT)
MEMORY
ADDRESS

1
2

..
3

34
35

MEMORY
CONTENTS
XXX2 H
RECEIVE
COMMAND
DATA
DATA
DATA
DATA
**
STATUS

MEMORY
ADDRESS

COM1553B
MEMORY
OPERATION

1
2

READ'
READ

3
READ
READ
READ
READ

4

WRITE

5

'reads command control code bits CB2-CBO
** response time
X = don't care

Remote Terminal Transfer to Bus Controller
This message format covers transactions where the Bus
Controller sends a transmit command to a Remote Terminal
and requests data from it. Initialization of the BC for normal
memory cycles is the same as the previous transfer. The
difference between this transfer and the previous transfer
is that after the Command Word is transmitted, the BC waits
14 f-Ls for the Status Word and the requested number of Data
Words. The Status and Data Words are written into external
memory via write cycles as they are received by the BC.

36

37

MEMORY
CONTENTS

COM1553B
MEMORY
OPERATION

XXX3 H
RECEIVE
COMMAND
TRANSMIT
COMMAND

READ'
READ

STATUS
(transmitting
RT)
DATA
DATA
DATA
DATA

WRITE

**
STATUS
(receiving RT)

READ

WRITE
WRITE
WRITE
WRITE

WRITE

'reads command control code bits CB2-CBO
** response time
X = don't care
Mode Code Command without Data
The Bus Controller transmits a specific Mode Command
and expects a Status Word back from the addressed
Remote Terminal.

TABLE 6
TABLE 4
BC to RT (The BC transmits a Transmit
Command to an RT)
MEMORY
ADDRESS
1
2

3
4

35

MEMORY
CONTENTS
XXX2 H
TRANSMIT
COMMAND
**
STATUS
DATA
DATA
DATA
DATA

MEMORY
ADDRESS
1
2

COM1553B
MEMORY
OPERATION

3

READ'
READ

MEMORY
CONTENTS
XXX2 H
COMMAND
**
STATUS

COM1553B
MEMORY
OPERATION
READ'
READ
WRITE

'reads command control code bits CB2-CBO
**response time
X = don't care
Mode Command with Data
(BC receives a single word)
In this mode the Bus Controller issues a transmit Mode
Command to an RT. The addressed Terminal responds to
the Bus Controller with a Status Word and a single Data
Word.

WRITE
WRITE
WRITE
WRITE
WRITE

'reads command control code bits CB2-CBO
** response time
X = don't care

TABLE 7
MEMORY
ADDRESS

RT-to-RT Transfer
In this message format, the Bus Controller first issues a
receive Command Word to the receiving Remote Terminal,
followed by a transmit Command Word to the transmitting
terminal. Next, the transmitting RT responds with a Status
Word and the requested number of Data Words to both the
receiving RT and BC. The receiving RT at the end of the
message sends a Status Word to the BC. As Status and
Data Words are received by the BC they are written into
external memory.

1
2

MEMORY
CONTENTS
XXX2 H
COMMAND
**
STATUS
DATA

COM1553B
MEMORY
OPERATION
READ'
READ

WRITE
3
WRITE
4
'reads command control code bits CB2-CBO
**response time
X = don't care

59

I

Mode Command with Data
(BC transmits a single word)
The Bus Controller issues a receive Mode Command and
one Data Word to a Remote Terminal. A Status Word is
returned by the Remote Terminal to the Bus Controller.

RT to RT Transfer (Broadcast)
This transfer is similar to the normal RT to RT transfer
with the exception that the Status Word is not returned by
the receiving RT.

TABLE 8

TABLE 10

MEMORY
ADDRESS
1
2
3

MEMORY
CONTENTS
XXX2 H
COMMAND
DATA
**
STATUS

4

COM1553B
MEMORY
OPERATION

MEMORY
ADDRESS

READ*
READ
READ

1
2
3

WRITE

*reads command control code bits CB2-CBO
**response time
X = don't care

4

..5

MEMORY
CONTENTS
XXX3 H
RECEIVE
COMMAND
TRANSMIT
COMMAND
**
STATUS
DATA
DATA
DATA
DATA

COM1553B
MEMORY
OPERATION
READ*
READ
READ

WRITE
WRITE
WRITE
WRITE
WRITE

Bus Controller (Broadcast) to Remote Terminal Transfer
36
In this mode the Bus Controller issues a Broadcast Com*reads command control code bits CB2-CBO
mand followed by a number of Data Words. In all Broadcast
Command transfers a BC will not expect to receive a Status . **response time
X = don't care
Word back.

TABLE 9
MEMORY
ADDRESS
1
2

.
3

34

MEMORY
CONTENTS
XXX2 H
RECEIVE
COMMAND
DATA
DATA
DATA
DATA

THE FOLLOWING NOTE APPLIES TO THE CURRENT
VERSION OF THE COM 1553B:
When operating as a Bus Controller in a RT (Remote
Terminal) to RT transfer, the COM1553B may incorrectly set
the Invalid Sync Bit in the Error Register if the status word
response from the receiving RT occurs between 4 and 7
microseconds.
The Bus Controller (BC) may confirm that an error free
message transmission occurred by requesting that the
receiving RT transmit the last status word. If this status word
matches the previous status word, then an error-free transmission occurred.

COM1553B
MEMORY
OPERATION
READ*
READ
READ
READ
READ
READ

*reads command control code bits CB2-CBO
** response time
X = don't care

Remote Terminal Transaction (RT/BC input of the COM1553B set high)
The following section addresses each COM1553B
information transfer format from the Remote Terminal
viewpoint.

The Subaddress field is thereafter decoded by external
logic and the Command word is written into external
memory. The RT then receives a predetermined number of
Data Words (specified by the word count field). As each Data
Word is received it is written into external memory. After the
reception of the last Data Word the RT transmits the Status
Word, the Message Error, Broadcast Flag, Terminal Flag,
Subsystem Flag, Busy, and Service Request bits are
updated for all commands except for the Transmit Status
Word and Transmit Last Command Code commands. While
transmitting the Status, the RT writes it into memory. The
RT also writes the Last Command Register, Error Register
and Receive Register into memory and then asserts Message complete.
Note that the receive register of the RT will contain the
transmitted Status Word.

Bus Controller to Remote Terminal Transfer
(BC to RT, where RT receives data)
In this transfer the COM1553B designated as the RT
receives a command to receive data. As the Command
Word is completely shifted into the receive shift register, the
RT compares the Command Word address field with the
preloaded Remote Terminal address. This determines if the
message is addressed to the receiving RT. If the Command
Word is valid, the RT issues a Data Transfer Request (DTR)
to initiate a memory cycle. Once the processor relinquishes
control of the data bus, during the Bus Acknowledge
(BGACK) time, the Command Word is placed on the data
bus.

60

TABLE 11
BC TO RT (RT receives data from BC)
MEMORY
ADDRESS
1

2
3

··
34
35
36
37
38

MEMORY
CONTENTS
COMMAND
DATA
DATA

..

DATA
**
STATUS
LAST
COMMAND
ERROR
REGISTER
RECEIVE
REGISTER

transfers. The only exception is that the receiving terminal
waits for the first Data Word from the transmitting terminal.
This satisfies the protocol requirement that the transmitting
terminal first send its status to the controller before it transmits the data to the receiving terminal.

COM1553B
MEMORY
OPERATION
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE

Mode Command with Data
(RT receives a Mode Code Command to transmit)
In this transfer, after the Transmit Mode Command is
received, the RT transmits the Status and one Data Word.

WRITE
WRITE

TABLE 13

WRITE

MEMORY
ADDRESS

WRITE

1

2
Remote Terminal-to-Bus Controller Transfer
(RT transmits data to BC)
The Remote Terminal receives a Transmit Command
Word from the Bus Controller. The RT will then proceed to
decode the Command Word, as in the previous case and
within the response time transmits the Status Word.
While the Status Word is being transmitted the RT issues
a write memory cycle to write the Status Word into external
memory. Thereafter, the Data words are read from memory
and transmitted. After the last word is transmitted the RT
writes the contents of the Last Command Register, Error
Register and the Receive Register into memory.

3
4
5
6

1

2
3

··

34
35
36
37

MEMORY
CONTENTS
COMMAND
**
STATUS
DATA
DATA
DATA
DATA
LAST
COMMAND
ERROR
REGISTER
RECEIVE
REGISTER

WRITE
WRITE
READ*
WRITE
WRITE
WRITE

Mode Code Command with Data
(RT receives a Mode Command to receive)
This transfer is similar to a Receive Command having only
one Data Word.

COM1553B
MEMORY
OPERATION

TABLE 14

WRITE

MEMORY
ADDRESS

WRITE
READ
READ
READ
READ
WRITE

1
2

3
4

5

WRITE

6

WRITE

**'response time

COMMAND
**
STATUS
DATA
LAST
COMMAND
ERROR
REGISTER
RECEIVE
REGISTER

COM1553B
MEMORY
OPERATION

*For a Transmit Last command Mode Code, Data is not
read from memory but transmitted from the internal Last
Command register.
** response time

TABLE 12
Remote Terminal to Bus Controller
(RT Transmits Data to BC)
MEMORY
ADDRESS

MEMORY
CONTENTS

MEMORY
CONTENTS
COMMAND
DATA
**
STATUS
LAST
COMMAND
ERROR
REGISTER
RECEIVE
REGISTER

COM1553B
MEMORY
OPERATION
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE

0** response time
Bus Controller Broadcast Transfer to RT
The RT receives a Broadcast Command to receive data.
If data received during a broadcast message is invalid, the
COM1553B will set the message error bit.

Remote Terminal-to-Remote Terminal Transfers
From the Remote Terminal viewpoint, RT-to-RT transfers are similar to the RT to BC receive or transmit data
61

I

TABLE 15
RT RECEIVE
MEMORY
ADDRESS
1
2

32
33
34
35

MEMORY
CONTENTS
COMMAND
DATA
DATA
DATA
DATA
STATUS
LAST
COMMAND
ERROR
REGISTER

Broadcast Mode Code Command Without Data
This Mode Code command is detected if the MSB of
the word count field is zero. This transaction is the same as
the previous transfer except that there is no Data Word
transfer.

COM15538
MEMORY
OPERATION
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE'
WRITE

TABLE 17
MEMORY
ADDRESS
1
2
3

WRITE

'In all broadcast transfers, a memory cycle is shown for the
Status Word but the RT does not transmit it on the 1553B
bus.

4

1
2
3
4
5

COMMAND
DATA
STATUS
LAST
COMMAND
ERROR
REGISTER

WRITE
WRITE'
WRITE
WRITE

Broadcast RT to RT Transfer
For this message transfer a Broadcast Command
to receive is issued by the Bus Controller. This is followed
by a normal Transmit Command to the transmitting Remote Terminal. The Remote Terminal responds with a normal transmit message format of Status Word and Data
Word(s). The receiving terminals do not transmit a Status
Word after receiving the data. However, they do go through
a memory cycle to load the Status Word into their respective memories.
For the Remote Terminal receive transfer refer to Table
15. The only difference in this transfer is that there is a gap
time between the Command and Data word.
For the Remote Terminal transmit transfer refer to Table
12. The only difference in this transfer is that the Receive
Register is not written into memory.

TABLE 16
RT RECEIVE
MEMORY
CONTENTS

COMMAND
STATUS
LAST
COMMAND
ERROR
REGISTER

COM15538
MEMORY
OPERATION

'In all broadcast transfers, a memory cycle is shown for
the Status Word but the RT does not transmit it on the
1553B bus.

Broadcast Mode Code Command with Data
This Broadcast Mode Code command is detected if the
MSB of the word count field is a logical high.
Transmission of the Status Word is suppressed as in the
previous case but is loaded into external memory.

MEMORY
ADDRESS

MEMORY
CONTENTS

COM15538
MEMORY
OPERATION
WRITE
WRITE
WRITE'
WRITE
WRITE

'In all broadcast transfers, a memory cycle is shown for
the Status Word but the RT does not transmit it on the
1553B bus.

62

MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range ................................................................................ - 55 to + 125'C
Storage Temperature Range .................................................................................. - 55 to + 150'C
Lead Temperature (soldering, 10 seconds) .......................................................................... ,. + 325'C
Positive Voltage on any pin ............................................................................................. + 15V
Negative Voltage on any pin except VBB, with respect to ground .......................................................... - .3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not
be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power
is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is
suggested that a clamp circuit be used.

DC ELECTRICAL CHARACTERISTICS TA = -5510 125'C, Vee = 5.0V ±5%, VDD = 12V ±5%, VBB = -5V ±5%

V"
V'H
VOL
VOH

Ie
C'N
C,
CL

Pw

PARAMETER

MIN

Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Leakage Current
Input Capacitance
Output Capacitance
Load Capacitance
Power Dissipation

-0.3
3
2.4

TYP

MAX

40
100
5

UNITS
V
V
V
V
fLA
pf
pf
pf
W
mA
mA
mA

MAX

UNITS

0.8
Vec
0.4
5
10
25
15
150

4
10
10
100
0.8

100
Icc
IBB

COMMENTS

IOL
10H

= -3.2 mA
= .8mA

TA

= 25'C

AC ELECTRICAL CHARACTERISTICS
PARAMETER
clk
t,
tf
t,
t2
t3
t4
t5
t6
t,
t,
t9
t10
t11
t12
t"
t"
t"
t"
t"
t"
tf9
t 20
t21
t22
t23
t24
t"
t26

clock frequency
Clk, rise time
Clk, fall time
DTRandWE
BGACKtoDTR
WEto DATA
DTACKtoWE
DTACKtoR/W
DTACKtoCio
CSTR to CSTRA
CSTRA to CSTR
CSTRAwidth
C/Oto DATA
CMDto fM
1M width
VCwidth
VCto 1M
C/OtoMC
C/OtolM
C/OtoMC
C/OtoMC
CMD to MCF reset
CMD to MCF set
CMDtoVC
C/O to MCF reset
C/O to MCF set
PORwidth
Receive CMD to DTR
Transmit CMD to DTR

MIN

0.5
0.8
50

TYP
12
6
6
0.6
1.3
100
1.5
1
1.5

1
2
2
1.5
2.5
673
1.5

500

MHz
ns
ns
fLS
fLS
ns
fLs
fLs
fLs
fLs
fLs
ns

0
3.25
500
1
1.75
700
2.25
750
1.25
3.75
4.75
2.75
1.5
1
2.5
4.25
5.75

63

fLS
ns
fLS
fLs
ns
fLs
ns
fLs
fLs
fLs
fLs
fLs
fLS
fLs
fLs
fLs

COMMENTS
50% duty cycle

FIGURE 3:
RECEIVER LOGIC WAVEFORMS
I

FIGURE 5:
CONTIGUOUS WORD
I

1

1

-I

~I"""_- SYNC - -....

MANIN

I-PARITY ...

I

I

2 I-l s - l
L_
r---MAX
- I
LINE TO LINE

DTR VS COMMAND WORD
RECEIVE
CMD

LINE TO LINE

,.-,--+---r-r-,.......,
PI
LI1~1__+-_----'-11--'81'-19..L.1:-I

\--t"--I

WD

I

MANOUT

I

L

DTR

I

lrf\Ji
I

I

I

I

I

I

OVERLAP t.,

TRANSMIT r-T---r---'-"-r--1
CMD
+-_~118JI_19~lp--,1

1,_1JI__

WD

I-t~-I

= 10 ns TYP.

FIGURE 4:
DRIVER LOGIC WAVEFORMS
MODE CODE FLAG (MCF)
ASA RT

VC

t-t,,-l _______
____________
~n'_

ASABC
~3

r---C/O

l~

I--

BIT COMMAND CONTROL C O D E - - - l
READ FROM MEMORY
. I

I

________________~1

~

COMMAND WORD - 1
READ FROM MEMORY
I

__________~r--

~~~
I~

MCF

~~~

__________________~r_

POR

AFTER POWER IS
STABLE

64

AC CHARACTERISTICS

BGACl< - - - _ - - - - - ,

}.'-----BGACK

It-4-,,-tI

-------,1~-------

orR _ _ _ _ _ _
1

\ I-'--r
I

DTA - - - - - "

_--.Jr--

1,----DTAcK -

_ _ _ _ _ _---,

wE---+I---____~~_·_,~
II
~
I

}.'---I

I

I

}--.; ...-l,;rI

I

I

I-o.~ I

1

I

A W -----\

I

DATA

--------x=

---+I----------<<:~-+i

r:~---------+I-~I

~~t,o-

:
I

(

DATA

•

I

I

r-

~.~

I
DTACK

CID

1

I

~

iI

I

I

I

I

~

1

CSTA

:

r-

CD~i

1

_ _ _ _ _~
~

I

I

1

I

1-'• .,...--

CSTA"A

t-'. --.
I
------''------LJ~---

OTR

-------'1t-'"~
...______

I

WRITE CYCLE

I

READ CYCLE

A

CONTROL

•
r

DMA
CONTROLLER

TRANSCEIVER!
TRANSFORMER 1\.r----v'I

M68000

MICROPROCESSOR
SYSTEM

COM1553B

vA~~~--~D7AT~A~1I1iL-----~~-~~1
J.J,
r

DMA
MEMORY

TYPICAL SYSTEM IMPLEMENTATION

65

I

INVALID MESSAGE (1M)
ASART

MESSAGE COMPLETE (MC)
ASART

CASE 1
CMDWD

CASE 1 AT THE COMPLETION OF AN ERROR FREE BROADCAST COMMAND TRANSACTION AFTER THE
ERROR REGISTER IS WRITTEN INTO MEMORY.

IL'~I__~______~I'~"LI'~9~lp~1
!--1,,--1
1
~

1M

CIO

--H-CASE 2

THE TIR BIT IN THE BROADCAST
CMD IS SET HIGH.

BROADCAST WD .....
,...J'-VC
1M

MC

I"

CIO

--t l I"

__1-____-L,_"LI,-'-'91~P21

I"

I--------------~~
I
t-I,,---j

CIO

11----------------~~1~"1

MC

I
__________~n~
______
ASABC

CASE 3 WHEN THE BC ISSUES A RECEIVE COMMAND,THE
MC SIGNAL OCCURS AFTER THE STATUS WORD IS
WRITTEN INTO MEMORY.
OR
WHEN THE BC ISSUES A TRANSMIT COMMAND,
THE MC SIGNAL OCCURS AFTER THE LAST DATA
WORD IS WRITTEN INTO MEMORY.

-----------------lll-iI"I-

1M

I~
--------1111

MC

------------~I~

CIO

--ll-

I

I"

CASE 4

,,1-

CASE 2 AT THE COMPLETION OF A TRANSMIT OR RECEIVE
COMMAND TRANSACTION AFTER THE DATA REGIST.ER IS WRITTEN INTO MEMORY.

AN ERROR OCCURRED DURING
A BROADCAST CMD

CASE 3

-1

' ____
___________~n~

MC

NON BROADCAST CMD

: --!,1~
-------------;1-,
I ..

CIO
1M
MC

CASE 5

AS A BC OR RT

------------~

CASE 4 AT THE COMPLETION OF LOADING THE RT
ADDRESS REGISTER OR
READING THE DATA REGISTER.

------------~
ASABC

CID

A TRANSMIT OR RECEIVE BC TRANSFER

MC

_ _ _ _ _---J~

CIO
1M

MC

CASE 5 AFTER READING THE ERROR REGISTER.

~

-----------------.r-~I,,~-l

CIO

--------------~~

MC

-1 I" 1------------~~

NOTE: Message complete and invalid message outputs!l.!.
the COM 15536 are negative pulses i.e. MC and 1M.

Circuit diagrams utilizing SMC products arejncluded as a means of illustrating typical semiconductor applications: consequently complete mformation sufficient for construction purposes is not necessarily given. The
information has been ,carefully checked and. is belie.ved to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such Information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

66

- - - - - ------------------------------------------

COM1671
J.L PC FAMILY

Asynchronous/Synchronous Transmitter-Receiver

ASTRO
FEATURES
D SYNCHRONOUS AND
ASYNCHRONOUS
Full Duplex Operations
D SYNCHRONOUS MODE
Selectable 5-8 Bit Characters
Two Successive SYN Characters Sets
Synchronization
Programmable SYN and DLE Character
Stripping
Programmable SYN and DLE-SYN Fill
D ASYNCHRONOUS MODE
Selectable 5-8 Bit Characters
Line Break Detection and Generation
1-, 1V2-, or 2-Stop Bit Selection
Start Bit Verification
Automatic Serial Echo Mode
D BAUD RATE-DC TO 1M BAUD
D 8 SELECTABLE CLOCK RATES
Accepts 1X Clock and Up To 4 Different
32X Baud Rate Clock Inputs
Up to 47% Distortion Allowance With 32X
Clock
D SYSTEM COMPATIBILITY
Double Buffering of Data
8-Bit Bi-Directional Bus For Data, Status,
and Control Words
All Inputs and Outputs TTL Compatible
Up To 32 ASTROS Can Be Addressed
On Bus
On-Line Diagnostic Capability
D ERROR DETECTION
Parity, Overrun and Framing

PIN CONFIGURATION
Vee
IACKI

CS
WE
IACKO

RPLY

INTA

iill0
CAll
OAL2
~

OAL4
OAL5
IDi[6
OAL7
("O'i'R) CD

iID
(RiNG) CE
MISC
(V,,)GNO

1
2
3
4
5
6
7
8

'-"

40
39
38
37
36
35
34
33

32
10
9
0 31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21

P Vee

pRE

P CA (IlTS)
P ~ (T50)
CB(t:TS\

58 (1XTC)
00 (1XAC)
A4
A3
A2
A1

CF (CARi"i)

CC (om1)
BB (H51)
103
104
IDS
MA

me

Vee

D COPLAMOS® n-Channel Silicon
Gate Technology
D Pin for Pin replacement for
Western Digital UC1671 and
National INS 1671
D Baud Rate Clocks Generated by
COM5036 @ 1X and
COM5016-6 @ 32X
APPLICATIONS
Synchronous Communications
Asynchronous Com[l1unications
Serial/Parallel Communications

General Description
The COM1671 (ASTRO) is a MOS/LSI device which performs the functions of interfacing a serial data communication
channel to a parallel digital system. The device is capable of full duplex communications (receiving and transmitting) with
synchronous or asynchronous systems. The ASTRO is designed to operate on a multiplexed bus with other bus-oriented
devices. Its operation is programmed by a processor or controller via the bus and all parallel data transfers with these
machines are accomplished over the bus lines.
The ASTRO contains several "handshaking" signals to insure easy interfacing with modems or other peripheral devices
such as display terminals. In addition, a programmable diagnostic mode allows the selection of an internal looping feature
which allows the device to be internally connected for processor testing.
The COM1671 provides the system communication designer with a software responsive device capable of handling
complex communication formats in a variety of system applications.

67

DAL BUS
CONTROL

COMMUNICATION
CHANNEL CONTROL

CLOCK
CONTROL

Organization
Data Access Lines - The OAL bus is an 8-bit bi-directional port over which all address, data, control, and status

transfers occur. In addition to transferring data and control words the OAL bus also transfers information
related to addressing of the device, reading and writing requests, and interrupting information.
Receiver Buffer - This 8-bit parallel register presents assembled received characters to the OAL bus when

requested through a Read operation.
Receiver Register - This 8-bit shift register inputs the received data at a clock rate determined by Control
Register 2. The incoming data is assembled to the selected character length and then transferred to the
Receiver Buffer with logic zeroes filling out any unused high-order bit positions.
Syn Register - This 8-bit register is loaded from the OAL bus by a Write operation and holds the synchronization

code used for receiver character synchronization. It serves as a fill character when no new data is available
in the Transmitter Buffer during transmission. This register cannot be read onto the OAL bus. It must be loaded
with logic zeroes in all unused high-order bits.
Comparator - The 8-bit comparator is used in the Synchronous mode to compare the assembled contents of

the Receiver Register and the SYN register or the OLE register. A match between the registers sets up
stripping of the received character, when programmed, by preventing the data from being loaded into the
Receiver Buffer. A bit in the Status Register is set when stripping is effected. The comparator output also enables
character synchronization of the Receiver on two successive matches with the SYN register.
DLE Register - This 8-bit register is loaded from the OAL bus by a Write operation and holds the OLE character

used in the Transparent mode of operation in which an idle transmit period is filled with the combination
OLE-SYN pair of characters rather than a single SYN character. In addition the ASTRO may be programmed to
force a single OLE character prior to any data character transmission while in the transmitter transparent mode.
Status Register - This 8-bit register holds information on communication errors, interface data register status,

match character conditions, and communication equipment status. This register may be read onto the OAL bus
by a Read operation.
Control Registers - There are two 8-bit Control Registers which hold device programming signals such as mode

selection, clock selection, interface signal control, and data format Each of the Control Registers can be
loaded from the OAL bus by a Write operation or read onto the OAL bus by a Read operation. The registers are
cleared by a Master Reset.
Transmitter Buffer - This 8-bit parallel register holds data transferred from the OAL bus by a Write operation.
This data is transferred to the Transmitter Register when the transmitter section is enabled and the Transmitter
Register is ready to send new data.
Transmitter Register - This 8-bit shift register is loaded from the Transmitter Buffer, SYN register, or OLE

register. The purpose of this register is to serialize data and present it to the serial data output.

68
-

----------------------

----

Astro Operation

Asynchronous Mode
Framing of asynchronous characters is provided by a Start bit (logic 0) at the beginning of a character
and a Stop bit(s) (logic 1) at the end of a character. Reception of a character is initiated on recognition
of the first Start bit by a positive transition of the receiver clock, after a preceding Stop bit(s). The Start
and Stop bits are stripped off while assembling the serial input into a parallel character.
The character assembly is completed by the reception of the Stop bit(s) after reception of the last
character bit (including the parity bit, if selected). If the Stop bit(s) is a logic 1, the character is
determined to have correct framing and the ASTRO is prepared to receive the next character. If the Stop
bit(s) is a logic 0, the Framing Error Status flag is set and the Receiver assumes this bit to be the Start
bit of the next character. Character assembly continues from this point if the input is still a logic 0 when
sampled at the theoretical center of the assumed Start bit. As long as the Receiver input is spacing, all
zero characters are assembled and error flags and data received interrupts are generated so that line
breaks can be determined. After a character of all zeroes is assembled along with a zero in the Stop
bit(s) location, the first sampled logic one is determined as a Stop bit and this resets the Receiver
circuit to a Ready state for assembly of the next character.
In the Asynchronous mode the character transmission occurs when informa&ncontained in the
Transmitter Buffer is transferred to the Transmitter Register. Transmission is initiated by the insertion
of a Start bit, followed by the serial output of the character (including the parity bit, if selected), then the
insertion of a 1,1.5, or 2 bit length Stop condition. If the Transmitter Buffer is full, the next character
transmission starts after the transmission of the Stop bit(s) of the present character in the Transmitter
Register. Otherwise, the Mark (logic 1) condition is continually transmitted until the Transmitter
Buffer is loaded.

Synchronous Mode
Framing of characters is carried out by a special Synchronization Character Code (SYN) transmitted
at the beginning of a block of characters. The Receiver, when enabled, searches for two contiguous
characters matching the bit pattern contained in the SYN register. During the time the Receiver is
searching, data is not transferred to the Receiver Buffer, status bits are not updated, and the Receiver
interrupt is not activated. After the detection of the firstSYN character, the Receiver assembles
subsequent bits into characters whose length is determined by the contents of Control Register 2. If,
after the first SYN character detection, a second SYN character is present, the Receiver enters the
Synchronization mode until the Receiver Enable Bit is turned off. If a second successive SYN character
is not found, the Receiver reverts back to the Search mode.
In the Synchronous mode a continuous stream of characters are transmitted once the Transmitter
is enabled. If the Transmitter Buffer is not loaded at the time the Transmitter Register has completed
transmission of a character, this idle time will be filled by a transmission of the character contained in
the SYN register in the Non-transparent mode, or the characters contained in the DLE and SYN registers
respectively while in the Transparent mode of operation.

69
~~-.---------------------------------

Astro Operation
Receiver
The Receiver Data input is clocked into the Receiver Register by a 1X Receiver Clock from a modem
Data Set, or by a local32X bit rate clock selected from one of four externally supplied clock·inputs.
When using the1X clock, the Receiver Data is sampled on the positive transition of the clock in both
the Asynchronous and Synchronous modes. When using a 32X clock in the Asynchronous mode, the
Receiver Sampling Clock is phased to the Mark-To-Space transition of the Received Data Start bit and
defines, through clock counts, the center of each received Data bit with + 0%, -3% at the positive
transition 16 clock periods later.
In the Synchronous mode the Sampli ng Clock is phased to all Mark-To-Space transitions of the
Received Data inputs when using a 32X clock. Each transition of the data causes an incremental
correction of the Sampling Check by 1/32nd of a bit period. The Sampling clock can be immediately
phased to every Mark-To-Space Data transition by setting Bit 4 of Control Register 1 to a logic one,
whi Ie the Receiver is disabled.
When the complete character has been shifted into the Receiver Register it is transferred to the
Receiver Buffer; the unused, higher order bits are filled with logic zero's. At this time the Receiver
Status bits (Framing Error/Sync Detect, Parity Error/OLE Detect, Overrun Error, and Data Received)
are updated in the Status Register and the Data Received interrupt is activated. Parity Error is set, if
encountered while the Receiver parity check is enabled in the Control Registers. Overrun Error is
set if the Data Received status bit is not cleared through a Read operation by an external device when
a new character is transferred to the Receiver Buffer. This error flag indicates that a character has
been lost; new data is lost while the old data and its status flags are saved.
The characters assembled in the Receiver Register that match the content of the SYN or the
OLE register are not loaded into the Receiver Buffer, and the DR interrupt is not generated, if Bit 3 of
Control Register 2 (CR23) or Bit 4 of Control Register 1 (CR14) are set respectively, and SYN Detect and
OLE Detect are set with the next non SYN or non OLE character. When both CR23 and CR14 are set
(Transparent mode), the DLE-SYN combination is stripped. The SYN comparison occurs only with the
character received after the OLE character. If two successive OLE characters are received only the
first OLE character is stripped. No parity check is made while in this mode.

TransmiHer
Information is transferred to the Transmitter Buffer by a Write operation. Information can be loaded
into this register at any time, even when the Transmitter is not enabled. Transmission of data occurs
only when the Request to Send bit is set to a logic 1 in Control Register 1 and the Clear To Send input is
logic O. Information is normally transferred from the Transmitter Buffer to the Transmitter Register
when the latter has completed transmission of a character. However, information in the OLE register
may be transferred prior to the information contained in the Transmitter Buffer if the Force OLE signal
condition is enabled (Bits 5 and 6 of Control Register 1 set to a logic 1). The control bit CR15 must be
set prior to loading of a new character in the Transmitter Buffer to insure forcing the OLE character
prior to transmission of the data character. The Transmitter Register output passes through a flip-flop
which delays the output by one clock period. When using the 1X clock generated by the Modem Data
Set, the output data changes state on the negative clock transition and the delay is one bit period.
When using a local32X clock the the transmitter section selects one of the four selected rate inputs and
divides the clock down to the baud rate. This clock is phased to the Transmitter Buffer Empty Flag
such that transmission of characters occurs within two clock times of the loading of the Transmitter
Buffer, when the Transmitter Register is empty.
When the Transmitter is enabled, a Transmitter interrupt is generated each time the Transmitter
Buffer is empty. If the Transmitter Buffer is empty, when the Transmitter Register is ready for a new
character, the Transmitter enters an idle state. During this idle time a logic 1 will be presented to the
Transmitted Data output in the Asynchronous mode or the contents of the SYN register will be
presented in the Synchronous Non-transparent mode (CR16 = 0). In the Synchronous Transmit
Transparent mode (CR16 = 1), the idle state will be filled by DLE-SYN character transmission in that
order. When entering the Transparent mode OLE must precede the contents of the Transmitter Buffer.
This is accomplished by setting of Bit 5 of Control Register 1.
If the transmitter section is disabled by a reset of the Request to Send, any partially transmitted
character is completed before the transmitter section of the ASTRO is disabled. As soon as the Clear
To Send goes high the transmitted data output will go high.
When the Transmitter parity is enabled, the selected Odd or Even parity bit is inserted into the last
data bit of the character in place of the last bit of the Transmitter Register. This limits transfer of
character information to a maximum of seven bits plus parity or eight bits without parity. Parity cannot
be enabled in the Synchronous Transparency mode.

70

Input/Output Operations
All Oata, Control, and Status words are transferred over the Oata Access Lines (OAL 0-7). Additional input
lines provide controls for addressing a particular ASTRO, and regulating all input and output operations. Other
lines provide interrupt capability to indicate to a Controller that an input operation is requested by the ASTRO.
All input/ output terminology below is referenced to the Controller so that a Read or input takes data from the
ASTRO and places it on the OAL bus, while a Write or Output places data from the OAL bus into the ASTRO.
A Read or Write operation is initiated by the placement of an eight-bit address on the DAL bus by the
Controller. When the Chip Select signal goes to a logic 0 state, the ASTRO compares Bits 7-3 of the DAL bus
with its hard-wired ID code (Pins 17, 22, 24, 25, and 26) and becomes selected on a Match condition. The ASTRO
then sets its RPL Y line low to acknowledge its readiness to transfer data. Bit 0 must be a logic 0 in Read or
Write operation. A setup time must exist between CS and the RE or WE signals to allow chip selection prior to
read/write operations.
Read
Bits 2-0 of the address are used to select ASTRO registers to read from as follows:
Bits 2-0
Selected Register
000
Control Register 1
010
Control Register 2
100
Status Register
110
Receiver Buffer
When the Read Enable (RE) line is set to a logic 0 condition by the Controller the ASTRO gates the contents
of the addressed register onto the OAL bus. The Read operation terminates, and the device becomes unselected,
when both the Chip Select and Read Enable return to a logic 1 condition. Reading of the Receiver Buffer clears
the Oata Received Status bit. The data is removed from the DAL bus when the RJ:: signal returns to the logic
high state.
Write
Bits 2-0 of the address are used to select ASTRO registers to be written into as follows:
Bits 2-0
Selected Register
000
Control Register 1
010
Control Register 2
100
SYN and OLE Register
110
Transmitter Buffer
When the Write Enable (WE) line is set to a logic 0 condition by the Controller the ASTRO gates the data
from the DAL bus into the addressed register. If data is written into the Transmitter Buffer, the TBMT Status bit
is cleared to a logic zero.
The 100 address loads both the SYN and OLE re·gisters. After writing into the SYN register the device is
conditioned to write into the OLE if followed by another Write pulse with the 100 address. Any intervening
Read or Write operation with other addresses or other ASTROs resets this condition such that the next 100 will
address the SYN register.
Interrupts
The following conditions generate interrupts:
Data Received (DR)
Indicates transfer of a new character to the Receiver Bufferwhile the Receiver is enabled.
Transmitter Buffer Empty (TBMT)
Indicates that the Transmitter Buffer is empty while the Transmitter is enabled. The first interrupt occurs when
the Transmitter becomes enabled if there is an empty Transmitter Buffer, or after the character is transferred
to the Transmitter Register making the Transmitter Buffer empty.
Carrier On
Indicates "'C"'a':::rr"'ie:"cr"O"'"e"'t"'e""c"to:C:r input goes low and the Data Terminal Ready (OTR) bit (CR1 0) is high.
Carrier Off
Indicates C"'' 'a:::rr'' ie::-:r''O' 'e:1t:::e'' c' to'' r input goes high and the Oata Terminal Ready (OTR) bit (CR10) is high.
Data Set Ready On
Indicates the Data Set Ready input goes low and the Data Terminal Ready (OTR) bit (CR1 0) is high.
Data Set Ready Off
Indicates the Oata Set Ready input goes high and the Oata Terminal Ready (OTR) bit (CR10) is high.
Ring On
Indicates the Ring Indicator input goes low and the Oata Terminal Ready (OTR) bit (CR10) is low.
Each time an interrupt condition exists the INTR output from the ASTRO is made a logic low. The following
interrupt procedure is then carried out even if the interrupt condition is removed.
The Controller acknowledges the Interrupt request by setting the Chip Select (CS) and the Interrupt
Acknowledge Input (IACKI) to the ASTRO to a low state. On this transition all non-interrupting devices receiving
the IACKI signal set their Interrupt Acknowledge Output (IACKO) low, enabling lower priority daisy-chained
devices to respond to the interrupt request. The highest priority device that is interrupting will then set its RPL Y
line low. This device will place its 10 code on Bit Positions 7-3 of the OAL bus when a 10wRE signal is received.
The data is removed from the OAL bus when the Read Enable (RE) signal returns to the logic one state. To reset
the Interrupt condition (lNTR) Chip Select (CS) and IACKI must be received by the ASTRO.

71

I

Description of Pin Functions
Pin No. Symbol

Pin Name

Function

1/0

1
21
40
20

V..
Vee
Voo
Vss

POWER SUPPLY
POWER SUPPLY
POWER SUPPLY
GROUND

23

MR

MASTER RESET

The Control and Status Registers and other controls
are cleared when this input is low.

815

DALODAL7

DATA ACCESS LINES 1/0

Eight-bit bi-directional bus used for transfer of data,
control status, and address information.

17
22
24
25
26

107
106
105
104
103

SELECT CODE

Five input pins which when hard-wired assign the
device a unique identification code used to select
the device when addressing and used as an
identification when responding to interrupts.

3

CS

CHIP SELECT

The low logic transition of CS identifies a valid
address on the DAL bus during Read and Write
operations.

39

RE

READ ENABLE

This input, when low, gates the contents of the
addressed register from a selected ASTRO onto
the DAL bus.

4

WE

WRITE ENABLE

This input, when low, gates the contents of the DAL
bus into the addressed register of a selected
ASTRO.

7

INTR

INTERRUPT

2

lACK I

INTERRUPT
ACKNOWLEDGE IN

5

IACKO INTERRUPT
0
ACKNOWLEDGE OUT

This output goes low in response to a low IACKI if
the ASTRO is not the interrupting device.

6

RPLY

This open drain output, to facilitate WIRE-ORing,
goes low when the ASTRO is responding to being
selected by an address on the DAL bus or in
affirming that it is the interrupting source.

REPLY

- 5 Volts
PS
PS
+ 5 Volts
+ 12 Volts
PS
GND Ground

0

This open drain output, to facilitate WIRE-ORing,
goes low when any interrupt conditions
occur.
When the Controller (determining the interrupting
ASTRO) makes this input low, the ASTRO places
its 10 code on the DAL bus and sets reply low if it is
interrupting, otherwise it makes IACKO a low.

0

72

Description of Pin Functions
Pin No. Symbol

1/0

Pin Name

Function

30
31
32
33

R1
R2
R3
R4

CLOCK RATES

These four inputs accept four different local 32X
data rate Transmit and Receive clocks. The input on
R4 may be divided down into a 32X clock from a
32X, 64X, 128X, or 256X clock input. The clock used
in the ASTRO is selected by bits 0-2 of Control
Register 2.

37

BA

TRANSMITTED DATA

27

BB

RECEIVED DATA

38

CA

REQUEST TO SEND

36

CB

CLEAR TO SEND

This input, when low, enables the transmitter
section of the ASTRO.

28

CC

DATA SET READY

This input generates an interrupt when going ON or
OFF while the Data Terminal Ready signal is ON.
It appears as bit 6 in the Status Register.

16

CD

DATA TERMINAL
READY

18

CE

RING INDICATOR

29

CF

CARRIER DETECTOR

35

DB

TRANSMITTER
T-IMING

This input is the Transmitter 1X Data Rate Clock.
Its use is selected by bits 0-2 of Control Register 2.
The transmitted data changes on the negative
transition of this signal.

34

DD

RECEIVER TIMING

This input is the Receiver 1X Data Rate Clock. Its
use is selected by bits 0-2 of Control Register 2. The
Received Data is sampled by the ASTRO on the
positive transition of this signal.

19

MISC

MISCELLANEOUS

0

This output is the transmitted serial data from the
ASTRO. This output is held in a Marking condition
when the transmitter section is not enabled.
This input receives serial data into the ASTRO.

0

0

This output is enabled by bit 1 of Control Register 1
and remains in a low state during transmitted data
from the ASTRO.

This output is generated by bit 0 in Control Register
1 and indicates Controller readiness.
This input from the Data Set generates an interrupt
when made low with Data Terminal Ready in the
OFF condition.

I

0

This input from the Data Set generates an interrupt
when going ON or OFF if Data Terminal Ready is
ON. It appears as bit S.in the Status Register.

This output is controlled by bits 4 and 5 of Control
Register 1 and is used as an extra programmable
signal.

73

Device Programming
The two a-bit Control Registers of the ASTRO determine the operative conditions of the ASTRO chip.

Control Register 1
2

1

0

SYNciASYNC

ASYNC

ASYNC (TRANS. ENABLED)

~

ASYNC

SYNC/ASYNC

SYNC/ASYNC

SYNC/ASYNC

0- LOOP
MOOE
1 - NORMAL
MODE

0- NON BREAK
MOOE
1 - BREAK MODE
TX

o -1Y2 or 2 STOP BIT
SELECTION
1 - SINGLE STOp· BIT
SELECTION

0- NON ECHO MODE
1 - AUTO ECHO MODE

0- RECEIVER
DISABLEO
1 - RECEIVER
ENABLEO

0- SETS RTS
OUT=1
1 - SETS IITS
OUT=O

0- SETS DTR
OUT=l
1-SETSIiffi
OUT=O

!Y!!f...

ASYNC (TRANS. DISABLED)

o - TRANSM ITTER
NON TRANS·
PARENT MODE
1 - TRANSMITTER
TRANSPARENT
MODE

0OUT=1
1 - MISC OUT=O

0- DLE STRIPPING
NOT ENABLEO
1 - OLE STRIPPING
ENABLED

0- NO PARITY ENABLED
1 - PARITY CHECK
ENABLED ON
RECEIVER AND
PARITY GENERATION
ENABLEO ON
TRANSM lITER

SYNC (CR16=0)

SYNC (CR12 = 0)

0- NO PARITY
GENERATED
1 - TRANSMIT PARITY
ENABLED

0- msc OUT=l
1 - msc OUT=O

BIT

6

7

4

5

mm:

3

SYNC (CR12 = 1)

SYNC
0- RECEIVER PARITY
CHECK IS DISABLEO
1 - RECEIVER PARITY
CHECK IS ENABLED

SYNC (CR16=1)
0- NO FORCE OLE
1 - FORCE DLE

Bit 0
Controls the Data Terminal Ready output on Pin 16 to control the CD circuit of the Data Set.
A logic 1 enables the Carrier and Data Set Ready interrupts. A logic 0 enables only the telephone line
Ring interrupt. The DTR output is inverted from the state of CR1 o.
Bit 1
Controls the Request to Send output on Pin 38 to control the CA circuit of the Data Set. The RTS output
is inverted from the state of CR11. A logic 1 combined with a low logic Clear to Send input enables
the Transmitter and allows TBMT interrupts to be generated. A logic 0 disables the Transmitter and
turns off the external Request to Send sig·nal. Any character in the Transmitter Register will be
completely transmitted before the Transmitter is turned off. The Request to Send output may be used
for other functions such as Make Busy on 103 Data Sets.

Bit2
A logic 1 enables the ASTRO to receive data into the Receiver Buffer, update Receiver Status
Bits 1,2,3, and 4, and to generate Data Received interrupts. A logic 0 disables the Receiver and clears
the Receiver Status bits.
Bit3
Asynchronous Mode
A logic 1 enables check of parity on received characters and generation of parity for transmitted
characters.
Synchronous Mode
A logic 1 bit enables check of parity on received characters only. Note: Transmitter parity enable is
controlled by CR15.

74

Bit4

Asynchronous Mode
A logic 1 enables the Automatic Echo mode when the receiver section is enabled. In this
mode the clocked regenerated data is presented to the Transmitter Data output in place of normal
transmission through the Transmitter Register. This serial method of echoing does not present any
abnormal restrictions on the transmit speed of the terminal. Only the first character of a Break
condition of all zeroes (null character) is echoed when a Line Break condition is detected. For all
subsequent null characters, with logic zero Stop bits, a steady Marking condition is transmitted until
normal character reception resumes. Echoing does not start until a character has been received and the
Transmitter is idle. The Transmitter does not have to be enabled during the Echo mode.
Synchronous Mode
A logic 1, with the Receiver enabled does not allow assembled Receiver data matching the OLE
register contents to be transferred to the Receiver Buffer; also, parity checking is disabled.
When the Receiver is not enabled this bit controls the Miscellaneous output on Pin 19, which may be
used for New Sync on a 201 Data Set. When operating with a 32X clock and a disabled Receiver, a logic
1 on this bit also causes the Receiver timing to synchronize on Mark-To-Space transitions.
BitS

Asynchronous Mode
A logic 1, with the Transmitter enabled, causes a single Stop bit to be transmitted. A logic 0 causes
transmission of 2 stop bits for character lengths of 6,7, or 8 bits and one-and-a-half Stop bits for a
character length of 5 bits.
With the Transmitter disabled this bit controls the Miscellaneous output on Pin 19, which may be used
for Make Busy on 103 Data Sets, Secondary Transmit on 202 Data Sets, or dialing on CBS Data Couplers.

Synchronous Mode
A logic 1 combined with a logic 0 on Bit 6 of Control Register 1 enables Transmit parity; if CR15=0 or
CR16=1 no parity is generated. When set to a logic 1 with Bit 6 also a logic 1, the contents of the OLE
register are transmitted prior to the next character loaded in the Transmitter Buffer as part of the
Transmitter Transparent mode.
Bit 6
Asynchronous Mode
A logic 1 holds the Transmitted Data output in a Spacing (Logic 0) condition, starting at the end of any
current transmitted character, when the Transmitter is enabled. Normal Transmitter timing continues
so that this Break condition can be timed out after the loading of new characters into the Transmitter Buffer.
Synchronous Mode
A logic 1 conditions the Transmitter to a transparent transmission which implies that idle transmitter
time will be filled by DLE-SYN character transmission and a OLE character can be forced ahead of any
character in the Transmitter Buffer (Bit 5 above). When forcing OLE transmission, Bit 5 should be set to
a logic 1 prior to loading the Transmitter Buffer, otherwise the character in the latter register may be
transferred to the Transmitter Register prior to sending the OLE character.
Bit7
A logic 0 configures the ASTRO into an Internal Data and Control Loop mode and disables the
Ring interrupt. In this diagnostic mode the following loops are connected internally:

a. The Transmit Data is connected to the Receive Data with the BA pin held in a Mark condition and
the input to the BB pin disregarded.
b. With a 1X clock selected, the Transmitter Clock also becomes the Receive Clock.
c. The Data Terminal Ready (DTR) Control bit is connected to the Data Set Ready (DSR) input, with
the Data Terminal Ready (DSRj output pin held in an OFF condition (logic high), and the DSR input
pin is disregarded.
d. The Request to Send Control bit is connected to the Clear To Send (CTS) and Carrier Detector (CF)
inputs, with the Request To Send (RTS) output pin held in an OFF condition (logic high), and the CTS
and Carrier Detector input pins are disregarded.
e. The Miscellaneous pin is held in an OFF (logic high) condition.
A logic 1 on Bit 7 enables the Ring interrupt and returns the ASTRO to the normal full duplex
configuration.

75

Control Register 2
Control Register 2, unlike Control Register 1, cannot be changed at any time. This register should be
changed only while both the receiver and transmitter sections of the ASTRO are in the idle state.
BIT

7

5

6

SYNC/ASYNC
CHARACTER LENGTH SELECT
00=8 BITS
01 =7 BITS
10=6 BITS
11=5BITS

4

3

MODE SELECT

SYNC/ASYNC

ASYNC

o-

0- EVEN PARITY
SELECT
1 - 000 PARITY
SELECT

0- RECEIVER CLK=
RATE 1
1 - RECEIVER CLOCK
DETERMINED BY
BITS 2-0

ASYNCHRONOUS

MODE
1 - SYNCHRONOUS
MODE

SYNC (CRI6 = 0)
0- NO SYN STRIP
1 - SYN STRIP

2

1

a

SYNC/ASYNC
CLOCK SELECT
000
001
010
011
100
101
110
111

-

lX CLOCK
RATE 1 CLOCK
RATE 2 CLOCK
RATE 3 CLOCK
RATE 4 CLOCK
RATE 4 CLOCK
RATE 4 CLOCK
RATE 4 CLOCK

~
~
~

2
4
8

SYNC (CR16=1)
0- NO OLE-SYN STRIP
1 - DLE-SYN STRIP

Bits 0-2

These bits select the Transmit and Receive clocks.
Bits

Clock Source

210
000
o0 1
010
011
100
1 0 1
110
1 1 1

Rx
Tx
I
1X Clock (Pin 35)
I 1X Clock (Pin 34)
Rate 1 32X clock (Pin 30)
Rate 2 32X clock (Pin 31) ,
Rate 3 32X clock (Pin 32) ,
, .
Rate 4 32X clock (Pin 33)
Rate 4 32X clock (Pin 33) (-:- 2) ' j
Rate 4 32X clock (Pin 33) (-:- 4) ' j
Rate 4 32X clock (Pin 33) (-:- 8) *j

NOTES:
• Rx clock is modified by bit 3 in the asynchronous mode.
tRate 4 is internally dividable so that the required 32X clock may be derived from an applied 64X, 128X, or 256X clock
which may be available.

Bits 3
Asynchronous Mode

A logic 0 selects the Rate 1 32X clock input (Pin 30) as the Receiver clock rate and a logic 1 selects the
same clock rate for the Receiver as selected by Bits 2-0 for the Transmitter. This bit must be a logic 1
for the 1X clock selection by Bits 2-0.
Synchronous Mode

A logic 1 causes all DLE-SYN combination characters in the Transparent mode when DLE strip (CR14)
is a logic 1, or all SYN characters in the Non-transparent mode to be stripped out and no Data Received
interrupt to be generated. The SYN Detect status bit is set with reception of the next assembled
character as is transferred to the Receiver Buffer.
Bit4

A logic 1 selects odd parity and a logic 0 selects even parity, when parity is enabled by CR13
andlorCR15.
BitS

A logic 1 selects the Synchronous Character mode. A logic 0 selects the Asynchronous Character mode.
Bits 6-7

These bits select the full character length (including parity, if selected) as shown above. When parity is
enabled it must be considered as a bit when making character length selection (5 bits plus parity = 6 bits).

76

Status Register
The data contained in the Status Register define Receiver and Transmitter data conditions and
status of the Data Set.
7
- Data
Set
Change

S
• Data
Set
Ready
(DSR)

5
- Carrier
Detector

4
- Framing
Error
• Syn
Detect

3
-DLE
Detect
• Parity
Error

2
- Overrun
Error

1
0
• Transmitter
- Data
Buffer
Received
(DR)
Empty
(TBMT)

BitO
A logic 1 indicates that the Transmitter Buffer may be loaded with new data. It is set to a logic 1
when the contents of the Transmitter Buffer is transferred to the Transmitter Register. It is cleared when
the Transmitter Buffer is loaded from the DAL bus, or when the Transmitter is disabled.
Bit 1
A logic 1 indicates that an entire character has been received and transferred into the Receiver
Buffer. It is cleared when the Receiver Buffer is read onto the DAL bus, or the Receiver is disabled.
Bit2
A logic 1 indicates an Overrun error which occurs if the previous character in the Receiver
Buffer has not been read and Data Received is not reset, at the time a new character is to be transferred
to the Receiver Buffer. This bit is cleared when no Overrun condition is detected (the next character
transfer time) or when the Receiver is disabled.
Bit3
When the DLE Strip is enabled (CR14) the Receiver parity check is disabled and this bit is set to a logic 1
if the previous character to the presently assembled character matched the contents of the DLE
register; otherwise it is cleared. The DLE DET remains for one character time and is reset on the next
character transfer or on a Status Register Read. If DLE Strip is not enabled this bit is set to a logic 1
when the Receiver is enabled, Receiver parity (CR13) is also enabled, and the last received character
has a Parity error. A logic 0 on this bit indicates correct parity. This bit is cleared in both modes when
the Receiver is disabled.
Bit4
Asynchronous Mode
A logic 1 indicates that the received data did not have a valid stop bit, while the Receiver was enabled,
which indicates a Framing error. This bit is set to a logic 0 if the stop bit (logic 1) was detected.
Synchronous Mode
A logic 1 indicates that the contents of the Receiver Register matches the contents of the SYN Register.
The condition of this bit remains for a full character assembly time. If SYN strip (CR23) is enabled this
status bit is updated with the character received after the SYN character.
In both modes the bit is cleared when the Receiver is disabled.

Bit 5
This bit is the logic complement of the Carrier Detector input on Pin 29.
BitS
This bit is the logic complement of the Data Set Ready input on Pin 28. With 202-type Data Sets
it can be used for Secondary Receive.
Bit7
This bit is set to a logic 1 whenever there is a change in state of the Data Set Ready or Carrier Detector
inputs while Data Terminal Ready (CR1 0) is a logic 1 or the Ring Indicator is turned ON, with DTR a
logic o. This bit is cleared when the Status Register is read onto the DAL bus.

77

I

Flow Chart Transmitter Operations

ASYNC

(Xl

TRANSMITTER SECTION (SYNCHRONOUS]

Flow Chart Receiver Operations

I

79

READ

I_---TARL--.:::I''-------.r
WRITE

r--TCSRLF---:k~-----------~TARL.----~-------'

INTERRUPT

INVALID ADDRESS CODE

1 - - - - - Tcsll-------<~

RPLY

TCSREH
~

Tpi
IACKI

L.,'1

IACKO

80

r

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range " ............................................... OOC to + 70°C
Storage Temperature Range ............................................. ,. -55°C to +150°C
Lead Temperature (soldering, 10 sec.) ................................................ +325°C
Positive Voltage on any Pin, with respect to ground..... .................. ..... ... ....... +18.0V
Negative Voltage on any Pin, with respect to ground ....................................... -0.3V
'S~resses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
ELECTRICAL CHARACTERISTicS
(TA=O°C to 70°C, Vcc= +5V ±5%, VDD = +12V ±5%, VBB=-5V ±5%, Vss= av, unless otherwise noted)
Min

Parameter
D.C. Characteristics
INPUT VOLTAGE LEVELS
Low Level, VIL
High Level, VIH
OUTPUT VOLTAGE LEVELS
Low Level, VOL
High Level, V OH
INPUT LEAKAGE
Data Bus
All others
POWER SUPPLY CURRENT
Icc
IDo
IBB
A.C. Characteristics
CLOCK-RCP, TCP
frequency
DAL Bus
Address Set-Up Time
T As
Address Hold Time
TAH
Address to RPLY Delay
TARL
CSWidth
Tcs
CS to Reply OFF Relay
TcsRLF
Read
TARE
TREcsH
TREcs
TREo
Write
T AwE
TWEcsH
TWE
T DS
TDH
TwEcs
Interrupt
Tcsi
TcsRE
T CSREH
T RECS
To,
T IAO
TRED
TIARL
T CSRLF
Til
TREI
Note 1: If

Unit

0.8

V
V

0.4

5.0
5.0

IOL=1.6ma
IOH=100p.a

10.0
10.0

p'a
p'a

0",VIN ",5 V
VIN = +12v

80.0
10.0
1.0

rna
rna
rna

MHz

1.0
0
150

250

ns
ns
ns
ns
ns

RL =2.7 Kn

180

ns
ns
ns
ns

CL =20 pf

400
250
0

Address~ WESpacing

250
20
200
150
100
250

1000

0
250
20
250
200
250
180
250
250
200
250

0

Comments

V

2.4

250
20
250

CS to IACKI Delay
CS to RE Delay
CS and RE Overlap
RE to CS Spacing
IACKI Pulse Width
IACKI to Valid 10 Code Delay
RE OFF to DAL Open Delay
IACKI to RPLY Delay
CS to RPLY OFF Delay
IACKI to IACKO Delay
RE OFF to IACKO OFF Delay

Max.

2.4

Address and RE Spacing
RE and CS Overlap
RE to CS Spacing.
RE to Data Out Delay

WE and CS Overlap
WE Width
Data Set-Up Time
Data Hold Time
WE to CS Spacing

Typ.

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
n5
ns
ns
ns
ns
ns
ns

See Note 1.
See Note 1.
RL=2.7Kn

RE goes low after lACK I goes low. the delay will be from the falling edge of RE.

81

----------------

--------------------

t
~

UJ
Oz

IN 3008

0"
~

~
,

olll~

" I" t

(J)

~Z

I~

~~
~o

~a:

Sn81"'0

c

o

-0
<'>,
~I

i':'

z'i!

~I II
00

I~

Ofu(J)
«

:;::

Ill!
~

-v

a:

I~

...

III
:::J

C)

;:
c
o

...J
...JUJ
«z
-zo

• t
• I~
•e

a: « u

o

~~

c

'iii
.c

o
I

>.

III

'iii

c

,5

~

(J)

UJ
00

:0

ro

0300801

0"

f'"

~

«
0

N

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ien

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a:

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely re/iable. However, no responsibility is

assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights.of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

82

COM 1863
COM 8018
/lPC FAMILY

Universal Asynchronous Receiver/Transmitter
UART
PIN CONFIGURATION
FEATURES

VDD
·HIACC
Gnd
ROE
R08
R07
R06
ROS
R04
R03
R02
RO'
RPE
RFE
ROR

o Compatible with TR1863 timing
o High accuracy 32X clock mode: 48.4375% Receiver Distortion
Immunity and improved RDA/ROR operation (COM 8018 only)
o High Speed Operation-62.5K baud, 200ns strobes
o Single +5V Power Supply
o Direct TTL Compatibility-no interfacing circuits required
o Input pull-up options: COM 8018 has low current pull-up
resistors; COM 1863 has no pull up resistors

o Full or Half Duplex Operation-can receive and transmit
simultaneously at different baud rates
o Fully Double Buffered-eliminates need for precise external

timing
I mproved Start Bit Verification-decreases error rate
046.875% Receiver Distortion Immunity
Fully Programmable-data word length; parity mode; number
of stop bits: one, one and one-half, or two
Master Reset- Resets all status outputs and Receiver Buffer
Register
Three State Outputs-bus structure oriented
Low Power-minimum power requirements
Input Protected-eliminates handling problems
Ceramic or Plastic DIP Package-easy board insertion
Baud Rates available from SMC's COM 8046, COM 8116,
COM 8126, COM 8136, COM 8146 baud rate generators

SWE
RCP

o

o
o
o
o
o
o
o

R5AR
ROA
RSI

TCP
POE
NOB'
NOB2
NSB
NPB
CS
T08
T07
T06
TOS
T04
T03
T02
TO'
TSO
TEOC

fl5S
TBMT
MR

PACKAGE: 40-Pin D.1.P.

FUNCTIONAL BLOCK DIAGRAM
T01 T02 T03 T04 TOS T06 T07 T08

TOS

23

TSO

GENERAL DESCRIPTION

TEOC

TCP

The Universal Asynchronous Receiver/Transmitter is an
MOS/LSI monolithic circuit that performs all the receiving and
transmitting functions associated with asynchronous data
communications. This circuit is fabricated using SMC's
patented COPLAMOS® technology and employs depletion
mode loads, allowing operation from a single +5V supply. The
duplex mode, baud rate, data word length, parity mode, and
number of stop bits are independently programmable through
the use of external controls. There may be 5,6,7, or 8 data
bits, odd/even or no parity, and 1 or 2 stop bits or 1.5 stop bits
when utilizing a 5-bit code. These programmable features
provide the user with the ability to interface with all
asynchronous peripherals.

SWE

CS
NPB
NSB
NOB2
NOB'
POE

TBMT
RPE
RFE
ROR
RDA

STATUS
WORD
BUFFER
REGISTER

ROAR

2'

MR
VDD

f-------i;rl HIACC·
Gnd

*If pin 2 is taken to a logic 1 the COM 8018 will operate in a high
accuracy mode. If pin 2 is connected to -12V, GND, a valid logic
zero, or left unconnected, the high accuracy feature is disabled,
and the UART will operate in a 16X clock mode. Pin 2 is not connected on the COM 1863.

83

ROE

DESCRIPTION OF OPERATION- TRANSMITTER

commences. TEOC goes low, TSO goes low (the
start bit), and TBMT goes high indicating that the
data in the data bits buffer register has been loaded
into the transmitter shift register and that the data
bits buffer register is available to be loaded with
new data.
If new data is loaded into the data bits buffer register
atthistime, TBMT goes low and remains in this state
until the present transmission is completed. One
full character time is available for loading the next
character with no loss in speed oftransmission. This
is an advantage of double buffering.
Data transmission proceeds in an orderly manner:
start bit, data bits, parity bit (if selected), and the
stop bit(s). When the last stop bit has been on the
line for one bit time TEOC goes high. If TBMT is
low, transmission begins immediately. If TBMT is
high the transmitter is completely at rest and, if
desired, new control bits may be loaded priorto the
next data transmission.

At start-up the power is turned on, a clock whose
frequency is 16 or 32 times the desired baud rate is
applied, and master reset is pulsed. Under these
conditions TBMT, TEOC, and TSO are all at a high
level (the line is marking).
When TBMT and TEOC are high, the control bits
may be set. After this has been done the data bits
may be set. Normally, the control bits are strobed
into the transmitter prior to the data bits. However,
as long as minimum pulse width specifications
are not violated, TDS and CS may occur simultaneously. Once the data strobe (TDS) has· been
pulsed,the TBMT signal goes low, indicating that
the data bits buffer register is full and unavailable to
receive new data.
If the transmitter shift register is transmitting previously loaded data the TBMT signal remains low.
If the transmitter shift register is empty, or when it is
through transmitting the previous character, the
data in the buffer register is loaded immediatelyinto
the transmitter shift register and data transmission

TRANSMITTER BLOCK DIAGRAM

ODD/EVEN
PARITY SELECT

CONTROL
STROBE

11--0----

DATA STROBE

TRANSM ITIER
BUFFER

EMPTY
16X or 32X

SERIAL
OUTPUT

CLOCK

END OF
CHARACTER
HIACC

DESCRIPTION OF OPERATION - RECEIVER

33/64 bit times (in the 32X mode, HIACC = 1), a
genuine start bit is verified. Should the line return
to a marking condition prior to a 1/2 bit time, the
start bit verification process begins again. A mark
to space transition must occur in order to initiate
start bit verification. Once a start bit has been
verified, data reception proceeds in an orderly
manner: start bit verified and received, data bits
received, parity bit received (if selected) and the
stop bit(s) received.

At start-up the power is turned on, a clock whose
frequency is 16 or 32 times the desired baud rate is
applied and master reset is pulsed. The data
available (RDA) signal is now low. There is one set
of control bits for both the receiver and transmitter.
Data reception begins when the serial input line
transitions for mark (high) to space (low). If the
RSI line remains spacing for 15/32 to 17/32 bit
times (in the 16X mode, HIACC = 0) or 31/64 to

84

receiver assu mes that the previously received
character has not been read out and the over-run
flip-flop is set high. The only way the receiver is
aware that data has been read out is by having the
data available reset low.

If the received parity bit is incorrect, the parity
error flip-flop of the status word buffer register is
set high, indicating a parity error. However, if the
no parity mode is selected, the parity error flipflop is unconditionally held low, inhibiting a parity
error indication. If a stop bit is not received, the
framing error flip-flop is set high, indicating a framing error.

Subsequently the RDA output goes high indicating
that all outputs are available to be examined. The
receiver shift register is now available to begin receiving the next character. Due to the double buffered receiver, a full character time is available to
remove the received character.

On the negative RCP edge preceding the stop-bit
center sample, internal logic looks at the data
available (RDA) signal. If, at this instant, the RDA
signal is high, or the RDAR signal is low, the

RECEIVER BLOCK DIAGRAM

BITS FROM
HOLDING _____________
CONTROL
REGISTER

l:======~====~~~~~==========~~====l

SERIAL
INPUT

16X or 32X
CLOCK

HIACC-------~---------------'

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

SYMBOL

FUNCTION

NAME

1

VDD

Power Supply

+5 volt Supply

2

HIACC

High Accuracy
Mode

Enables 32X clock and improved RDA/ROR operation.
See NOTE on high accuracy mode.

GND

Ground

Ground

RDE

Received Data
Enable

A low-level input enables the outputs (RD8-RD1) of the
receiver buffer register.

5-12

RD8-RD1

Receiver Data
Outputs

These are the eight 3-state data outputs enabled by RDE.
Unused data output lines,as selected by NDB1 and NDB2,
have a low-level output, and received characters are right
justified, i.e. the LSB always appears on the RD1 output.

13

RPE

Receiver Parity
Error

This 3-state output (enabled by 8WE) is at a high-level if
the received character parity bit does not agree with the
selected parity.

14

RFE

Receiver Framing
Error

This 3-state output (enabled by SWE) is at a high-level if
the received character has no valid stop bit.

3
4

--

85

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

SYMBOL

NAME

FUNCTION

15

ROR

Receiver Over
Run

This 3-state output (enabled by SWE) is at a high-level if
the previously received character is not read (RDA output
reset not completed) before the present character is
transferred into the receiver buffer register.

16

SWE

Status Word
Enable

A low-level input enables the outputs (RPE, RFE, ROR,
RDA, and TBMT) of the status word buffer register.

17

RCP

Receiver Clock

This input is a clock whose frequency is 16 times (16X) or
32 times (32X) the desired receiver baud rate.

18

RDAR

Receiver Data
Available Reset

A low-level input resets the RDA output to a low-level.
RDAR must have gone low and come high again before
ROR is sampled to avoid overrun indication.

19

RDA

Receiver Data
Available

This 3-state output (enabled by SWE) is at a high-level
when an entire character has been received and transferred
into the receiver buffer register.

20

RSI

Receiver Serial
Input

This input accepts the serial bit input stream. A high-level
(mark) to low-level (space) transition is required to initiate
data reception.

21

MR

Master Reset

This input should be pulsed to a high-level after power
turn-on. This sets TSO, TEOC, and TBMT to a high-level
and resets RDA, RPE, RFE,ROR and RD1-RD8 toa low-level.

22

TBMT

Transmitter
Buffer Empty

This 3-state output (enabled by SWE) is at a high-level
when the transmitter buffer register may be loaded with
new data.

23

TDS

Transmitter
Data Strobe

A low-level input strobe enters the data bits into the
transmitter buffer register.

24

TEOC

Transmitter End
of Character

This output appears as a high-level during the last half
clock cycle of the last stop bit. It remains at this level
until the start of transmission of the next character or
for one-half of a TCP period in the case of continuous
transmission.

25

TSO

Transmitter
Serial Output

This output serially provides the entire transmitted
character. TSO remains at a high-level when no data is
being transmitted.

26-33

TD1-TD8

Transmitter
Data Inputs

There are 8 data input lines (strobed by TDS) available.
Unused data input lines, as selected by NDB1 and NDB2,
may be in either logic state. The LSB should always be
placed on TD1.

34

CS

Control Strobe

A high-level input enters the control bits (NDB1, NDB2,
NSB, POE and NPB) into the control bits holding register.
This line may be strobed or hard wired to a high-level.

35

NPB

No Parity Bit

A high-level input eliminates the parity bit from being
transmitted: the stop bit(s) immediately follow the last data
bit. In addition, the receiver requires the stop bit(s) to follow
immediately after the last data bit. Also, the RPE output is
forced to a low-level. See pin 39, POE.

86
-------- - - - - -

DESCRIPTION OF PIN FUNCTION
PIN NO.

SYMBOL

NAME

FUNCTION

36

NSB

Number of
Stop Bits

This input selects the number of stop bits. A low-level input
selects 1 stop bit; a high-level input selects 2 stop bits.
Selection of two stop bits when programming a 5 data bit
word generates 1.5 stop bits.

37-38

NDB2,
NDB1

Number of Data
Bits/Character

39

POE

Odd/Even Parity
Select

40

TCP

Transmitter
Clock

These 2 inputs are internally decoded to select either 5,6,7,
or 8 data bits/character as per the following truth table:
NDB2 NDB1
data bits/character
L
L
5
L
H
6
H
L
7
H
H
8
The logic level on this input, in conjunction with the NPB
input, determines the parity mode for·both the receiver and
transmitter, as per the following truth table:
NPB POE
MODE
L
L
odd parity
L
H
even parity
H
X
no parity
X don't care
This input is a clock whose frequency is 16 times (16X) or
32 times (32X) the desired transmitter baud rate.

=

TRANSMITTER TIMINGS BIT, PARITY, 2 STOP BITS

TRANSMITTER START-UP

TOS

1111 I II

TBMT

TSO

RECEIVER TIMINGS BIT, PARITY, 2 STOP BITS

START BIT DETECT AND VERIFY

o

2

1

16

17

+16X
_32X

RC~-"~

~~A~ ·.... ID~T~e}~R~~1 STOP,'STOP2IsTART

III I I II
l'-___. . , ___ce_n~ter,sample

RSI

CENTER BIT
SAMPLE

minimum continuous low
required for start·bit verification

RECEIVER TIMING DETAIL
5
13

6
14

8
16

7
15

9
17

10
18

-16X
-32X

RCP

RDA

(HIACC =0)===========:::;-_-:.____________

(HIA~CA 1)=======-=-=-=-=-=-=-~1:;:::=-----------=

R~~:D8,

APE, AFE

X
-'----'X'--___________

___________

87

-----~.---.----~------------------

MAXIMUM GUARANTEED RATINGS·
Ope~ating Temperature Range ..................................................... 0 0 Cto + 70 0 C
Storage Temperature Range .• , ...... , ........ ; ................................. -55 0 C to +150 0 C
Lead Temperature (soldering, 10 sec.) ...................................................... +325 0 C
pbsitive Voltage on iuiy Pin, with respect to ground ........... ; ............................... +8.0V
Negative Voltage on any Pin (except Pin 2), with respect to ground .......................... -0.3V
Negative Voltage on Pin 2, with respect to groiJnd ............... ; ......................... -13.2V
Stresses above those listed may cause permanent damage to the device. This is a stress
rating dhly and functional operation of the device at these or at any other condition above
those indicated In the operational sections of this specification is not implied.
NOTE: When pow~ring this device from laboratory or system powersupplies, itis important
that the Absolute Maximum Ratings not be exceeded or device failure can result. Some
power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power is
switched on and off. In addition, voltage transients on the AC power line may appear on the
DC output. If this possibility exists it is suggested that at clamp circuit be used.
ELECTRICAL CHARACTERISTICS (TA = 0 0 C to 70 0 C, Voo = +5V ±5%, unless otherwise noted)

,

: Paral!leter

D.C; CHARACTERISTICS
INPUT \lOLTAGE LEVELS
Low-level: Vil
High"level, VIH
OUTPUT VOLTAGE LEVELS
Low-level, VOL
High"ievel, VOH
INPUT CURRENT
i..ow~level, IlL
INPUT LEAKAGE
OUTPUT CURRENT
Leakag~, ILO .
SHbrtcircuit; los"
INPWT cApAcITANCE
. All ihpLlts, GIN
OUTPUT CAPACITANCE
All outpUt~,COUT
POWER SUPPLY CURRENT
Icc,
A.C. CHARA0
>0

ns
ns

DB1-DB8
NPB, NDB2, NDB1, POE

>0
>0

ns
ns

DB1-DB8
NPB, NDB2, NDB1, POE
Load = 20pf +1 TTL input
RDE: TpD1, TpDo
RDE

180
100

250
250

ns
ns

··Not more than one output should be shorted at a time.
NOTES:
1. Under steady state condition no current flows for TTL or MOS interfacing. A switching current of 1.6 mA
maximum flows during a transition of the input.
2. The three-state output has 3 states:
1) low impedance to Vcc
2) low impedance to GND
3) high impedance OFF ="! 10M ohms
The OFF state is controlled by the RDE input.
103

DESCRIPTION OF OPERATION - RECEIVER/TRANSMITTER

The input clock frequency for the receiver is set at
the desired receiver baud rate and the desired
receiver sync character (synchronous idle character) is loaded into the receiver sync register. When
the Receiver Reset input transitions from a highlevel to a low-level the receiver is set into the search
mode (bit phase). In the search mode the serially
received data bit stream is examined on a bit by bit
basis until a sync character is found. A sync character is found, by definition, when the contents of the
receiver sync register and the receiver shift register
are identical. When this occurs the Sync Character
Received output is set high. This character is then
loaded into the receiver buffer register and the
receiver is set into the character mode. In this mode
each character received is loaded into the receiver
buffer register. The receiver provides flags for Receiver Data Available, Receiver Over Run, Receiver
Parity Error, and Sync Character Received. Full
double buffering eliminates the need for precise
external timing by allowing one full character time
for received data to be read out.
The input clock frequency for the transmitter isset

at the desired baud rate and the desired transmitter
sync character is loaded into the transmitter sync
register. Internal logic decides if the character to be
transmitted out of the transmitter shift register is
extracted from the transmitter data register or the
transmitter sync register. The next character transmitted is extracted from the transmitter data register
provided that a Transmitter Data Strobe pulse
occurs during the presently transmitted character.
If the Transmitter Data Strobe is not pulsed, the next
transmitted character is extracted from the transmitter sync register and the Sync Character Transmitted output is set to a high level. Full double buffering eliminates the need for precise external timing by
allowing one full character time to load the next
character to be transmitted.
There may be 5, 6, 7, or 8 data bits and odd/even
or no parity bit. All inputs and outputs are directly
TTL compatible. Tri-state data output levels are
provided for the bus structure oriented signals.
Input strobe widths of 200ns, output propagation
delays of 250ns, and receiver/transmitter rates of
250K baud are achieved.

FLOW CHART-TRANSMITTER

TURN POWER ON
SET CONTROL BITS - PULSE cs
SET SYNC CHARACTER ONTO THE DATA BUS - PULSE TSS
SELECT BAUD RATE-TCP

SET DATA BITS ONTO

DATA BUS-PULSE ToS
TBMT = 0

SET SYNC CHARACTER
ONTO DATA BUSPULSE TSS

LOAD TRANSMITTER SHIFT
REGISTER FROM TRANSMITTER
DATA REGISTER

SCT=O
TBMT = 1

LOAD TRANSMITTER SHIFT
REGISTER FROM TRANSMITTER
SYNC REGISTER
seT = 1

104

FLOW CHART-RECEIVER

TURN POWER ON
SELECT CONTROL BITS-PULSE CS
SET RECEIVER SYNC CHARACTER ONTO DATA BUS-PULSE RSS
PULSE RR-SETS RECEIVER INTO SEARCH MODE. RDA ~ ROR ~ RPE

~

SCR

~

0

SHIFT 1 BIT INTO THE RECEIVER SHIFT REGISTER

I

DOTHE
CONTENTS OF THE

NO

RECEIVER SHIFT REGISTER

COMPARE TO THE CONTENTS
OF THE RECEIVER
SYNC REGISTER
?

YES
SET THE RECEIVER INTO THE CHARACTER MODE
SCR~1

LOAD THE RECEIVED CHARACTER INTO THE RECEIVER BUFFER REGISTER-RDA = 1
EXAMINE OUTPUTS. PULSE ROAR, ADA 0
IF DESIRED, SET NEW RECEIVER SYNC CHARACTER ONTO DATA BUS-PULSE RSS

=

SHIFT 1 BIT INTO THE RECEIVER SHIFT REGISTER

NO

HAS
A COMPLETE CHARACTER
BEEN RECEIVED

?

SET seR

=1

DOTHE
CONTENTS OF THE

YES

NO

RECEIVER SHIFT REGISTER

SETSCR~O

COMPARE TO THE CONTENTS
OF THE RECEIVER

SYNC REGISTER
?

HAS

THE PROPER

YES

PARITY BIT
BEEN R~CEIVED

YES

IS

RDA~O

?

105

NO
>--------.!
'-_----,_ _--'

NO

>--------~

'------,----'

USRT TIMING DIAGRAM
TCP

:

n

niiNote1
TDS ________~ ~-----------t_----------------~
1, -___________________________
TBMT ________- .
~____________~:lrN-o-te-1----------------,~

...

I

SCT ------------------------I:r-----,
I
I

1

L -_ _ _ _ _ _ _ _ _ _ _ _

~I------------------~r1

I
TSO :='I-=- -:.L-_-L-_T_-r_-I_- J _ l _ l _ - J - _ - C _ l _ - r I

-l-X_-C_l_-~-_-L_

k - - - Sync Character - 1 4 - - Data Character

Data Character

------.j

RCP

_-.l_+-_I___

--I--

L -,,----

J -+ L 1-1_1-- L _1_
14-------- Sync Character ~-r-: Data Character
I .1- I
I Data Character
RR~------------------~II~~II--rl----------~I--~I--~Ir-----------~--I

-Lllr-'-IJ -

RSI

I

ROAR
RDA

I

1 -1-

!

nIl

1

------------------;-:---+1--+1----------'

I Note l2

"I

I

III

-+1_.....11,1__ JNote3

J

I

~~

1

I

!

Note3

:1

=1 [ ±=
NOTE 1
The transmitter shift register is
loaded with the next character
at the positive clock transition
corresponding to the leading
edge of the last bit of the
current character on the TSO
output. TBMT is set high
approximately two microseconds after this clock transition.
If it is desired that the next
character be extracted from
the transmitter data register
the leading edge of the TOS
should occur at least one
microsecond prior to this
clock transition.

:1
III
.

rNote3

I

R01-8 _

1

I

:
---------~I~I

~

I

,

1

SCR --,
I.L

I

,I- - i - - - - - - - - ' - - I
\ _
1

L - ._ _ _ _ _ _ _ _ _ _ _ _

RPE

I

1

~ __________ ~
-~

I
I

I

I

I

I

II

-=- J./":=' D

NOTE 2
In order to avoid an ROR
indication the leading edge of
the ROAR pulse should occur
at least one microsecond prior
to the negative clock transition
corresponding to the center
of the fi rst bit after the last data
bit on the RSI input.

--r'1
I

==- =- =- =- =- =] ~ J:

NOTE 3
The ROR, RPE, SCR and R01ROB outputs are set to their
correct levels approximately
two microseconds after the
negative clock transition
corresponding to the center of
the first bit after the last data
bit on the RSI input. The ROA
output is set high at the next
negative clock transition.
The solid waveforms correspond to a control register
setti ng of 5 data bits and a
parity bit. The dashed waveforms are for a setting of 6 data
bits and no parity bit.

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes

at any time in order to improve design and supply the best product possible.

106

COM 2651
JLPc FAMILY

Programmable Communication Interface
PCI
PIN CONFIGURATION

FEATURES
D Synchronous and Asynchronous Full Duplex or
Half Duplex Operations

D2 1

D Re-programmable ROM on-chip baud

D

D

D

D

rate generator
Synchronous Mode Capabilities
- Selectable 5 to 8-Bit Characters
- Selectable 1 or 2 SYNC Characters
-Internal Character Synchronization
- Transparent or Non-Transparent Mode
-Automatic SYNC or OLE-SYNC Insertion
-SYNC or OLE Stripping
- Odd, Even, or No Parity
- Local or remote maintenance loop back mode
Asynchronous Mode Capabilities
- Selectable 5 to 8-Bit Characters
-3 Selectable Clock Rates (1X, 16X, 64X the
Baud Rate)
- Line Break Detection and Generation
-1, 1 V2, or 2-Stop Bit Detection and Generation
- False Start Bit Detection
- Odd, Even, or No Parity
- Parity, Overrun, and framing error detect
- Local or remote maintenance loop back mode
-Automatic serial echo mode
Baud Rates
- DC to 1.0M Baud (Synchronous)
- DC to 1.0M Baud (1X, Asynchronous)
- DC to 62.5K Baud (16X, Asynchronous)
- DC to 15.625K Baud (64X, Asynchronous)
Double Buffering of Data

28 D1

27 DO

D3 2
RxD 3

26Vcc

GND 4

25 RxC

D4 5

24 DTR

D5 6

23RTS

D6 7

22 DSR

D7 8

21 RESET

TxC 9

A110
CE11
A012
R/W 13
RxRDY 14

'---_.

20 BRCLK
19TxD
18 TxEMT/DSCHG
HCTS
16DCD
15 TxRDY

Package: 28-pin D.I.P.

D Internal or External Baud Rate Clock

D
D
D
D

-16 Internal Rates:50 to 19,200 Baud
Single +5 volt Power Supply
TTL Compatible
No System Clock Required
Compatible with 2651, INS2651

GENERAL DESCRIPTION
Asynchronous Receiver/Transmitter (USART)
The COM 2651 is an MOS/LSI device fabricated
using SMC's patented COPLAMOS® technology
designed for microcomputer system data comthat meets the majority of asynchronous and
munications. The USART is used as a peripheral
synchronous data communication requirements,
and is programmed by the processor to comby interfacing parallel digital systems to asynmunicate in commonly used asynchronous and
chronous and synchronous data communication
synchronous serial data transmission techniques
channels while requiring a minimum of processor
including IBM Bi-Sync. The USART receives serial
data streams and converts them into parallel data
overhead. The COM 2651 contains a baud rate
characters
for the processor. While receiving serial
generator which can be programmed to either
data, the USART will also accept data characters
accept an external clock or to generate internal
from the processor in parallel format, convert them
transmit or receive clocks. Sixteen different baud
to serial format and transmit. The USART will sigrates can be selected under program control when
nal the processor when it has completely received
operating in the internal clock mode. The on-Chip
or transmitted a character and requires service.
baud rate generator can be ROM reprogrammed to
Complete USART status including data format
accommodate different baud rates and different
starting frequencies.
errors and control signals is available to the
processor at any time.
The COM 2651 is a Universal Synchronous/
107

I

)

DATA BUS

00-07

DATA SUS
BUFFER

t

~

)

$YN/DLE CONTROL

SVN 1 REGISTER
SYN 2 REGISTER
OLE REGISTER

OPERATION CONTROL

•

RESET

..

AD

..

Al
R/W

..

•

MODE REGISTER 1

¢

MODE REGISTER 2
COMMAND REGISTEA

-

r--

STATUS REGISTER

~

TRANSMITTER

)

HOLDING REGISTER

TRANSMIT DATA

TRANSMIT

TxD

SHIFT REGISTER

r--

•

BRCLK

•

•

---.

ROM

AE·PROGRAMMABlE
BAUD RATE
GENERATOR
AND
CLOCK CONTROL

:-- r--

J 1

r--

I--

r---

RECEIVER

RECEIVE DATA

HOLDING REGISTER

DSR
DCD
CTS
RTS

.
..
..

RECEIVE
SHIFT REGISTER

~
MODEM
CONTROL

~

•

RxD

---

DTR

..

~~~~~

Vee

• GND

COM 2651 ORGANIZATION
The COM 2651 is organized into 6 major sections.
Communication between each section is achieved via
an internal data and control bus. The data bus buffer
allows a processor access to all internal registers on the
COM 2651.
Operation Control
This functional block stores configuration and operation commands from the processor and generates appropriate signals to various internal sections to control the
overall device operation. It contains read and write circuits to permit communications with a processor via the
data bus and contains Mode Registers 1 and 2, the
Command Register, and the Status Register. Details of
register addressing and protocol are presented in the
COM 2651 programming section of this specification.
Timing
The COM 2651 contains a Baud Rate Generator (BRG)
which is programmable to accept external transmit or
receive clocks or to divide an external clock to perform
data communications. The unit can generate 16 commonly used baud rates, anyone of which can be selected
for full duplex operation. Table 6 illustrates all available
baud rates.
Receiver
The Receiver accepts serial data on the RxD pin, converts this serial input to parallel format, checks for bits
or characters that are unique to the communication

technique and stores the "assembled" character in the
receive data holding register until read by the processor.

Transmitter
The Transmitter accepts parallel data from the processor,
converts it to a serial bit stream, inserts the appropriate
characters or bits (based on the communication technique) and outputs a composite serial stream of data on
the TxD output pin.
Modem Control
The modem control provides three output signals and
accepts three input signals used for "handshaking" and
status indication between the COM 2651 and a modem.
SYN/OLE Control
This section contains control circuitry and three a-bit
registers storing the SYN1, SYN2, and OLE characters
provided by the processor. These registers are used in
the synchronous mode of operation to provide the
characters required for synchronization, idle fill and
data transparency.
Interface Signals
The COM 2651 interface signals can be grouped into two
types: the processor-related signals (shown in Table 2) which
interface the COM 2651 to the processor, and the devicerelated signals (shown in Table 3), which are used to interface to the communications equipment.
108

TABLE 2-PROCESSOR RELATED SIGNALS
PIN NO.

NAME

1,2,5,6, Data
7,8,27,28
10,12

SYMBOL
D7-D0

Address

A1,A0

FUNCTION
Bidirectional; 8 bit, three state data bus used to transfer commands, data and status
between the COM 2651 and a processor. D0 is the least significant bit; D7 is the most
significant bit.
I nput; Address lines used to select COM 2651 registers.

11

Chip Enable

CE

13

Read/Write

RIW

Input; Processor read/write direction control. This signal defines the direction of the
data bus D7-0 when the COM 2651 is selected. D7-0 drives out (read) when this signal is
low and accepts data input when this signal is high. The input only has meaning when
the chip enable input is active.

14

Receiver Ready

RxRDY

Output; This signal is the complement of Status Register bit 1 (SR1). When low, it
indicates that the Receive Data Holding Register (RHR) has a character ready for input
to the processor. It goes high when the RHR is read by the processor, and also when
the receiver is disabled. It is an open drain output which can be used as an interrupt
to the processor.

15

Transmitter
Ready

TxRDY

Output; This signal is the complement of Status Register bitO (SRO). When low, it
indicates that the Transmit Data Holding Register (THR) is ready to accept a data
character from the processor. It goes high when the data character is loaded. This output
is valid only when the transmitter is enabled. It is an open drain output which can be
used as an interrupt to the processor.

18

Transmitter
empty/data
set change

TxEMT/
DSCHG

Output; This signal is the complement of Status Register bit 2 (SR2). When low, it
indicates that the transmitter has completed serialization...QU.he last character loaded
by the processor, or that a change of state of the DSR or DCD inputs has occurred.
This output goes high when the Status Register is read by the processor, if the
TxEMT condition does not exist. Otherwise, the THR must be loaded by the processor
for this line to go high. It is an open drain output which can be used as an interrupt
to the processor.

21

Reset

26

Su pply Voltage

4

Ground

Reset

Vee
GND

Input; when this signal is low, the operation specified by the RIW, A1 and A0 will be
performed. When this input is high, D7-0 are in the high impedance state.

Input; A high on this input performs a master reset on the COM 2651. This signal
asynchronously terminates any device activity and clears the Mode, Command and
Status registers. The device assumes the idle state and remains there until initialized
with the appropriate control words.
+5 volts supply.
Ground.

TABLE 3-DEVICE RELATED SIGNALS
PIN NO.

NAME

FUNCTION

SYMBOL

3

Receive Data

RxD

Input; Serial data to the receiver. "Mark" is high "space" is low.

9

Transmitter
Clock

TxC

Input or Output; If the external transmitter clock is programmed, this input controls
the rate at which the character is transmitted. Its frequency is 1X, 16X or 64X, the Baud
rate as programmed by Mode Register 1. The transmitted data changes on the falling
edge of the clock. If the internal transmitter clock is programmed, this pin becomes
an output at 1X the programmed Baud rate.

16

Data Carrier
Detect

DCD

Input; This signal must be low in order for the receiver to function. The complement
appears in the Status Register bit 6 (SR6). When this input changes state a low output
on TxEMT/DSCHG occurs.

17

Clear to Send

CTS

Input; This signal must be low in order for the transmitter to function. If it goes high
during transmission, the character in the Transmit Shift Register will be transmitted
before termination.

19

Transmit Data

TxD

Output; Serial data from the transmitter. "Mark" is high, "Space" is low. This signal is
held in the "Mark" condition when the transmitter is disabled.

20

Baud Rate Clock

22

Data Set Ready

DSR

Input; This general purpose signal can be used for Data Set Ready or Ring Indicator
condition. Its complement appears as Status Register bit 7 (SR7). When this input
changes state, a low output on TxEMT/DSCHG occurs.

23

Request to Send

RTS

Output; This general purpose signal is the complement of the Command Register bit 5
(CR5). It is normally used to indicate Request to Send.

BRCLK

Input; The standard device requires a 5.0688MHz clock to the internal Baud rate
generator allowing for Baud rate shown in Table6. The reprogrammable ROM on chip
allows for user specificed Baud rates and input frequency. Consult the factory for
details. This input is not required if external receive and transmit clocks are used.

109
.-

~~-----.

----~~-~~-----~~~~--------

TABLE 3-DEVICE RELATED SIGNALS

PIN NO.

NAME

SYMBOL

FUNCTION

24

Data Terminal

i5'FR

Output; This general purpose signal is the complement of the Command Register
bit 1 (CR1). It is normally used to indicate Data Terminal Ready.

25

Receive Clock

RxC

Input or Output; If the external receiver clock is programmed, this input controls the
rate at which the character is to be received. Its frequency is 1X, 16X, or 64X the Baud
rate, as programmed by Mode Register 1. Data are sampled on the rising edge of the
clock. If internal receiver clock is programmed, th is pin becomes an output at 1X the
programmed Baud rate.

COM 2651 OPERATION
The functional operation of the COM 2651 is programmed
by a set of control words supplied by the processor.
These control words specify items such as synchronous
or asynchronous mode, baud rate, number of bits per
character, etc. The programming procedure is described
in the COM 2651 Programming section ofthis data sheet.
After programming, the COM 2651 is ready to perform
the desired communications functions. The receiver
performs serial to parallel conversion of data received
from a modem or equivalent device. The transmitter
converts parallel data received from the processor to a
serial bit stream. These actions are accomplished within
the framework specificed by the control words.

to the hunt mode. (Note that the sequence SYN1-SYN1SYN2 will not achieve synchronization). When synchronization has been achieved, the COM 2651 continues to assemble characters and transfers them to the
Holding Register. The RxRDY status bit is set and the
RxRDY output is asserted each time a character is assembled and transferred to the Holding Register. The Overrun
error (OE) and Parity error (PE) status bits are set as
appropriate. Further receipt of the proper SYN
sequence sets the SYN DETECT status bit. If the SYN
stripping mode is commanded, SYN characters are not
transferred to the Holding Register. Note that the SYN
characters used to establish initial synchronization are
not transferred to the Holding Register in any case.

Receiver
The COM 2651 is conditioned to receive data when the
input is low and the RxEN bit in the command
register is true. In the asynchronous mode, the receiver
looks for a high to low transition on the RxD input line
indicating the start bit. If a transition is detected, the
state of the RxD line is sampled again after a delay of
one-half of a bit time. If RxD is now high, the search for
a valid start bit is begun again. If RxD is still low, a valid
start bit is assumed and the receiver continues to sample
the input line at one bit time intervals until the proper
number of data bits, the parity bit, and the stop bit(s)
have been assembled. The data is then transferred to the
Receive Data Holding Register, the.RxRDY bit in the
status register is set, and the RxRDY output is asserted.
If the character length is less than 8 bits, the high order
unused bits in the Holding Register are set to zero. The
Parity Error, Framing Error, and Overrun Error status
bits are strobed into the status register on the positive
going edge of RxC corresponding to the received character boundary. If a break condition is detected (RxD is
low for the entire character as well as the stop bit[s]).
only one character consisting of all zeros (with the
Framing error status bit set) will be transferred to the
Holding Register. The RxD input must return to a high
condition before a search for the next start bit begins.
When the COM 2651 is initialized into the synchronous
mode, the receiver first enters the hunt mode on a 0 to 1
transition of RxEN (CR2). In this mode, as data is shifted
into the Reciver Shift Register a bit at a time, the contents of the register are compared to the contents of the
SYN1 register. If the two are not equal, the next bit is
shifted in and the comparison is repeated. When the two
registers match, the hunt mode is terminated and character assembly begins. If the single SYN operation is
programmed, the SYN DETECT status bit is set. If double
SYN operation is programmed, the first character assembled after SYN1 must be SYN2 in order for the SYN
DETECT bit to be set. Otherwise, the COM 2651 returns

Transmitter
The COM 2651 is conditioned to transmit data when the
CTS input is low and the TxEN command register bit is
set. The COM 2651 indicates to the processor that it can
accept a character for transmission by setting the
TxRDY status bit and asserting the TxRDY output. When
the processor writes a character into the Transmit Data
Holding Register, the TxRDY status bit is reset and the
TxRDY output is returned to a high (false) state. Data
is transferred from the Holding Register to the Transmit
Shift Register when it is idle or has completed transmission of the previous character. The TxRDY conditions are then asserted again. Thus, one full character
time of buffering is provided.

ocr;

In the asynchronous mode, the transmitter automatically
sends a start bit followed by the programmed number
of data bits, the least significant bit being sent first. It then
appends an optional odd or even parity bit and the programmed number of stop bits. If, following transmission
of the data bits, a new character is not available in the
Transmit Holding Register, the TxD output rel)J..<:!ins il.
the marking (high) condition and the TxEMT/DSCHG
output and its corresponding status bit are asserted.
Transmission resumes when the processor loads a new
character into the Holding Register. The transmitter can
be forced to output a continuous low (BREAK) condition by setting the Send Break command bit high.
I n the synchronous mode, when the COM 2651 is initially
conditioned to transmit, the TxD output remains high and
the TxRDY condition is asserted until the first character to
be transmitted (usually a SYN character) is loaded by the
processor. Subsequent to this, a continuous stream of
characters is transmitted. No extra bits (other than parity,
if commanded) are generated by the COM 2651 unless the
processor fails to send a new character to the COM 2651
by the time the transmitter has completed sending the
previous character. Since synchronous communication
does not allow gaps between characters, the COM 2651
110

asserts TxEMT and automatically "fills" the gap by
transmitting SYN1s, SYN1-SYN2 doublets, or DLE-SYN1
doublets, depending on the state of MR16 and MR17.
Normal transmission ofthe message resumes when a new
character is available in the Transmit Data Holding
Register. If the SEND DLE bit in the command register is
true, the DLE character is automatically transmitted prior
to transmission of the message character in the transmit
holding register.

COM 2651 INITIALIZATION FLOW CHART
INITIAL RESET

_----,,L-----.

COM 2651 PROGRAMMING

need not be programmed if external

clocks are used.

Prior to initiating data communications, the COM 2651
operational mode must be programmed by performing
write operations to the mode and command registers.
In addition, if synchronous operation is programmed,
the appropriate SYN/DLE registers must be loaded. The
COM 2651 can be reconfigured at any time during program execution. However, if the change has an effect on
the reception of a character the receiver should be disabled. Alternatively if the change is made 11/z RxC periods
after RxRDY goes active it will affect the next character
assembly. A flowchart of the initialization process
appears in Figure 1.
The internal registers of the COM 265Lare accessed by
applying specific signals to the CE, RIW, A 1 and AO
inputs. The conditions necessary to address each register
are shown in Table 4.
The SYN1, SYN2, and DLE registers are accessed by
performing ~rite operations with the conditions A 1=0,
AO=1, and R/W=1. The first operation loads the SYN1
register. The next loads the SYN2 register, and the third
loads the DLE register. Reading or loading the mode
registers is done in a similar manner. The first write (or
read) operation addresses Mode Register 1, and a subsequent operation addresses Mode Register 2. If more
than the required number of accesses are made, the
internal sequencer recycles to point at the first register.
The pointers are reset to SYN1 Register and Mode
Register 1 by a RESET input or by performing a "Read
Command Register" operation, but are unaffected by any
other read or write operation.
The COM 2651 register formats are summarized in
Tables 5, 6, 7 and 8. Mode Registers 1 and 2 define the
general operational characteristics of the COM 2651,
while the Command Register controls the operation
within this basic framework. The COM 2651 indicates
its status in the Status Register. These registers are
cleared when a RESET input is applied.

CE

A1

AD

R/W

1

X
0
0
0
0

X
0
0

X
0

1
1

0

1
1
1
1

0
0

0

0
0
0
0
0
0
0
0

NOTE
Mode Register 1 must be written

L._;';;"-.,..._ _....I before 2 can be written. Mode Register 2

1
1

N

NOTE
SYNl Register must be written
before SYN2 can be written. and
SYN2 before OLE can be written.

N

FUNCTION

Tri-state data bus
Read receive holding register
Write transmit holding register
Read status register
Write SYN1/SYN2IDLE registers
Read mode registers 1 and 2
Write mode registers 1 and 2
Read command register
Write command register

1
1
1
0

1

NOTE

See AC Characteristics section for timing requirements.

Table4-COM 2651 REGISTER ADDRESSING

111

MODE REGISTER 1 (MR1)
Table 5 illustrates Mode Register 1. Bits MR11 and MR10
select the communication format and Baud rate multiplier. 00 specifies synchronous mode and 1X multiplier.
1X, 16X, and 64X multipliers are programmable for
asynchronous format. However, the multiplier in asynchronous format applies only if the external clock input
option is selected by MR24 or MR25.
MR13 and MR12 select a character length of 5,6, 7, or 8
bits. The character length does not include the parity bit,
if programmed, and does not include the start and stop
bits in asynchronous mode.
MR14 controls parity generation. If enabled, a parity bit
is added to the transmitted character and the receiver
MR17

MR16

Sync/Async
ASYNCH: STOP BIT LENGTH
OO=INVALID
01 =1 STOP BIT
10=1'" STOP BITS
11 =2 STOP BITS

SYNCH: TRANSPARENCY CONTROL

O=DOUBLE SYN
1=SINGLE SYN

O=NORMAL
1=TRANSPARENT

NOTE

MR15

MR14

Parity Type

Parity Control

0=000
1=EVEN

SYNCH:NUMBER
OFSYN CHAR

performs a parity check on incoming data. MR15 selects
odd or even parity when parity is enabled by MR14.
In asychronous mode, MR17 and MR16 select character
framing of 1, 1.5, or 2 stop bits. (if 1X baud rate is programmed, 1.5, stop bits defaults to 1 stop bits on transmit). In synchronous mode, MR17 controls the number
of SYN ch.aracters used to establish synchronization
and for character fill when the transmitter is idle. SYN1
alone is used if MR17=1, and SYN1-SYN2 is used when
MR17=0. If the transparent mode is specified by MR16,
DLE-SYN1 is used for character fill and SYN Detect, but
the normal synchronization sequence is used. Also OLE
stripping and OLE Detect (with MR14=0) are enabled.

I

MR13

MR12

MRll

Character Length

O=DISABLED
1=ENABLED

00=5
01=6
10=7
11=8

I

MR1D

Mode and Baud Rate Factor

BITS
BITS
BITS
BITS

OO=SYNCHRONOUS 1X RATE
01=ASYNCHRONOUS 1X RATE
10=ASYNCHRONOUS 16X RATE
11=ASYNCHRONOUS 64X RATE

Baud rate factor In asynchronous applIes only If external clock IS selected. Factor IS 16X If
internal clock is selected. Mode must be selected (MRll, MR10) in any case.

TABLE 5-MODE REGISTER 1 (MR1)

MODE REGISTER 2 (MR2)
inputs TxC and RxC as the clock source for the transmitter and receiver, respectively. If the BRG clock is
selected, the Baud rate factor in asynchronous mode is
16X regardless of the factor selected by MR11 and MR10.
In addition, the corresponding clock pin provides an
output at 1X the Baud rate. Custom Baud rates other
than the ones provided by the standard part are available. Contact the factory for details.

Table 6 illustrates Mode Register 2. MR23, MR22, MR21,
and MR20 control the frequency of the internal Baud
rate generator (BRG). Sixteen rates are selectable. When
driven by a 5.0688 MHz input atthe BRCLK input (pin 20),
the BRG output has zero error except at 134.5, 2000, and
19,200 Baud, which have errors of +0.016% +0.253%,
and +3.125% respectively.
MR25 and MR24 select either the BRG or the external
MR27

I

MR26

MR25

MR23-MR20

MR24

Theoretical
Transmitter
Clock

NOT USED

O=EXTERNAL
1=INTERNAL

Receiver
Clock
O=EXTERNAL
1=INTERNAL

Baud
Rate

frequency

Code

l6X Clock

Actual
Frequency
l6XCIock

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200·

0.8 KHz
1.2
1.76
2.152
2.4
4.8
9.6
19.2
28.8
32.0
38.4
57.6
76.8
115.2
153.6
307.2

0.8 KHz
1.2
1.76
2.1523
2,4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8

NOTE -Error at 19200 can be reduced to zero by using crystal frequency 4.9152MHz
16X clock is used in asynchronous mode. In synchronous mode, clock multiplier is 1X.
Baud rates are valid for crystal frequency = 5.0688MHz

TABLE 6-MODE REGISTER 2 (MR2)

112

Percent
Error

0.016

-

-

-

-

0.253

-

3.125

Divisor
6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16

COMMAND REGISTER (CR)
Table 7 illustrates the Command Register. BitsCRO (TxEN)
and CR2 (RxEN) eriable or diSable the transmitter and
receiver respectively. A O. to 1 transition of CR2 forces
start bit search (async mode) or hunt mode (sync mode)
on the second l1xC rising edge. Disabling the receiver
causes RxRDY to go high (inactive). If the transmitter is
disabled, it will complete the transmission ofthecharacter
in the Transmit Shift Register (if any) prior to terminating operation. The TxD output will then remain in the
marking state (high) while the TxRDY and TxEMT will
go high (inactive). If the receiver is disabled, it will terminate operation immediately. Any character being assembled will be neglected.
In asynchronous mode, setting CR3 will force and hold
the TxD output low (spacing condition) at the end of the
current transmitted character. Normal operation resumes
when CR3 is cleared. The TxD line will go high for at least
one bit time before beginning transmission of the next
character in the Transmit Data Holding Register. In synchronous mode, setting CR3 causes the transmission
of the DLE register contents prior to sending the character in the Transmit Data Holding Register. CR3 should
be reset in response to the next TxRDY.
Setting CR4 causes the error flags in the Status Register
(SR3, SR4, and SR5 ) to be cleared. This is a one time
command. There is no internal latch for this bit.
The COM 2651 can operate in one of four sub-modes
within each major mode (synchronous or asynchronous).
The operational sub-mode is determined by CR7 and
CR6. CR7-CR6=OO is the normal mode, with the transmitter and receiver operating independently in accordance with the Mode and Status Register instructions.
In asynchronous mode, CR7-CR6=01 places the COM
2651 in the Automatic Echo mode. Clocked, regenerated
received data is automatically directed to the TxD line
while normal receiver operation continues. The receiver
must be enabled (CR2=1), but the transmitter need not
be enabled. Processor to receiver communications continues normally, but the processor to transmitter link
is disabled. Only the first character of a break condition is echoed. The TxD output will go high until the
next valid start is detected. The following conditions
are true while in Automatic Echo mode:
1. Data assembled by the receiver are automatically
placed in the Transmit Holding Register and retransmitted by the transmitter on the TxD output.
2. The transmitter is clocked by the receive clock.
3. TXRDYO~tut=1.
4. The TxE i'DSCHG pin will reflect only the data set
change condition.
CR7

I

CR6

Operating Mode

OO=NORMAL OPERATION
01 =ASYNCH: AUTOMATIC
ECHO MODE
SYNCH: SYN AND/OR
OLE STRIPPING MODE
10=LOCAL LOOP BACK
11 = REMOTE LOOP BACK

CR5

5. The TxEN command (CRO) is ignored.
In synchronous .mode, CR7-CR6=01 places the COM
2651 in the Automatic SYN/DLE Stripping mode. The
exact action taken depends on the setting of bits MR17
andMR16:
1. In the non-transparent, single SYN mode (MR17MR16=10), characters in the data stream matching
SYN1 are not transferred to the Receive Data Holding
Register (RHR).
2. In the non-transparent, double SYN mode (MR17MR16=OO), characters in the data stream matching,
SYN1, or SYN2 if immediately preceded by SYN1, are
not transferred to the RHA. However, only the first
SYN1 of an SYN1-SYN1 pair is stripped.
3. In transparent mode (MR16=1), characters in the
data stream matching DLE, or SYN1 if immediately
preceded by DLE, are not transferred to the RHA.
However, only the first DLE of a DLE-DLE pair is
stripped.
Note that Automatic Stripping mode does not affect the
setting of the DLE Detect and SYN Detect status bits
(SR3 and SR5).
Two diagnostic sub-modes can also be configured. In
Local Loop Back mode (CR7-CR6=10), the following
loops are connected internally:
1. The transmitter output is connected to the receiver
input.
2. DTR is connected to DCD and RTS is connected to
CTS.
3. The receiver is clocked by the transmit clock.
4. The DTR, RTS and TxD outputs are held high.
5. The CTS, DOD, DSR and RxD inputs are ignored.
Additional requirements to operate in the Local Loop
Back mode are that CRO (TxEN), CR1 (DTR), and CR5
(RTS) .must be set to 1. CR2 (RxEN) is ignored by the
COM 2651.
The second diagnostic mode is the Remote Loop Back
mode (CR7-CR6=11). In this mode:
1. Data assembled by the ,receiver is automatically
placed in the Transmit Holding Register and retransmitted by the transmitter on the TxD output.
2. The transmitter is clocked by the receive clock.
3. No data are sent to the local processor, but the error
status conditions (PE, OE, FE) are set.
4. The RxRDY, TxRDY, and TxEMT/DSCHG outputs are
held high.
5. CRO (TxEN) is ignored.
6. All other signals operate normally.

CR4

Reque8tto
Send

Re8etError

O=FORCE Ri'S
OUTPUT HIGH
1=FORCE RTS
OUTPUT LOW

O=NORMAL
1=RESET
ERROR FLAG
IN STATUS
(FE.OE,
PE/DLE DETECT)

CR3

CR2

CR1

CRO

SynclAsync

Receive
Control (RxEN)

Data Tennlnal
Ready

Transmit
Control (TxEN)

O=DISABLE
1=ENABLE

O=FORCE DTR
OUTPUT HIGH
1 =FORCE 5'i'Fl
OUTPUT LOW

O=DISABLE
1=ENABLE

ASYNCH:
FORCE BREAK
O=NORMAL
1=FORCE
BREAK
SYNCH:
SEND OLE
O=NORMAL
1=SEND OLE

TABLE 7 - COMMAND REGISTER (CR)

113

STATUS REGISTER (SR)
The data contained in the Status Register (as shown in
Table 8) indicate receiver and transmitter conditions and
modem/data set status.
SRO is the Transmitter Ready (TxRDY) status bit. It, and
its corresponding output, are valid only when the transmitter is enabled. If equal to 0, it indicates that the
Transmit Data Holding Register has been loaded by the
processor and the data has not been transferred to the
Transmit Shift Register. If set equal to 1, it indicates that
the Holding Register is ready to accept data from the
processor. This bit is initially set when the Transmitter
is enabled by CRO, unless a character has previously
been loaded into the Holding R~ister. It is not set when
the Automatic Echo or Remote LOOR Back modes are
programmed. When this bit is set, the TxRDY output pin
is low. In the Automatic Echo and Remote Loop Back
modes, the output is held high.
SR1, the Receiver Ready (RxRDY) status bit, indicates
the condition ofthe Receive Data Holding Register.lfset, it
indicates that a character has been loaded into the
Holding Register from the Receive Shift Register and is
ready to be read by the processor. If equal to zero. there
is no new character in the Holding Register. This bit is
cleared when the processor reads the Receive Data
Holding Register or when the receiver is disabled by CR2.
When set, the RxRDY output is low.
The TxEMT/DSCHG bit, SR2, when set, indicates either
a change of state of the DSR or DCD inputs or that the
Transmit Shift Register has completed transmission of a
character and no new character has been loaded into
the Transmit Data Holding Register. Note that in synchronous mode this bit will be set even though the
appropriate "fill" character is transmitted. TxEMT will not
go active until at least one character has been transmitted. It is cleared by loading the Transmit Data Hold-

ing Register. The DSCHG condition is enabled when
TxEN = 1 or RxEN = 1. It is cleared when the Status Register is read by the processor. When SR2 is set, the TxEMT/
DSCHG output is low.
SR3, when set, indicates a received parity error when
parity is enabled by MR14. In synchronous transparent
mode (MR16=1), with parity disabled, it indicates that
a character matching the DLE Register has been received.
However, only the first DLE of two successive DLEs will
set SR3. This bit is cleared when the receiver is disabled and by the Reset Error command, CR4.
The Overrun Error status bit, SR4, indicates that the
previous character loaded into the Receive Holding
Register was not read by the processor at the time a new
received character was transferred into it. This bit is
cleared when the receiver is disabled and by the Reset
Error command, CR4.
In asynchronous mode, bit SR5 signifies that the received character was not framed by the programmed
number of stop bits. (if 1.5 stop bits are programmed,
only the first stop bit is checked.) If the RHR contains all
D's when SR5=1, a break condition is present. In synchronous non-transparent mode (MR16=0), it indicates
receipt of the SYN1 character in single SYN mode or the
SYN1-SYN2 pair in double SYN mode. In synchronous
transparent mode (MR16=1), this bit is set upon detection of the initial synchronizing characters (SYN1 or
SYN1-SYN2) and, after synchronization has been
achieved, when a DLE-SYN1 pair is receiv..ed. The bit is
reset when the receiver is disabled, when the Reset Error
command is given in asynchronous mode, or when the
Status Register is read by the processor in the synchronous mode.
SR6 and SR7 reflect the conditions of the DCD and-DSR
inputs respectively. A low input sets the corresponding
status bit and a high input clears it.

SR7-

SR6

SR5

SR4

SR3

SR2

SRI

DataSet
Ready

Data Carrier
Detect

FEISYN Detect

Overrun

PEfDLE Detect

TxEMTfDSCHG

RxRDY

O=DSRINPUT
IS HIGH
1 =BSl'i INPUT
ISLOW

O=DCDINPUT
IS HIGH
I=DCDINPUT
ISLOW

O=NORMAL
I=OVERRUN
ERROR

ASYNCH:
O=NORMAL
1 = FRAMING
ERROR
SYNCH:

ASYNCH:
O=NORMAL
1 = PARITY
ERROR
SYNCH:

0= NORMAL
I=SYNCHAR
DETECTED

O=NORMAL
l=PARITY
ERROR
OR
DLECHAR
RECEIVED

O=NORMAL
l=CHANGE
INDSROR
DCD.OR
TRANSMIT
SHIFT REGISTERIS
EMPTY

TABLE 8-STATUS REGISTER (SR)

114

O=RECEIVE
HOLDING REG
EMPTY
I=RECEIVEHOLDING REG
HAS DATA

SRO
TxRDY
O=TRANSMIT
HOLDING
REG BUSY
l=TRANSMIT
HOLDING
REG EMPTY

TIMING DIAGRAMS
TxRDY, TxEMT

(Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode))

OATA1

DATA 4

~D----"A,"2131415IB

I

TKO

T.EN~

DATA 1

OFTHR

1;2

I 3 I 4 15
OATA2

1 I I'
B

C A

I 2I 3I •
DATA 3

i'I·

I

I

I

I
I

I

I
I

I

5?

I

I

I

DATA 1

C.....-D-..~

I

I

\)

/

I I'
A

I
I
I

j
CEFORlJI
WRITE

C

OATA4

I

I

I

wt=

~

DATA 3

NOTES
A ""Start bit
B =Stop bit 1

C =Stop bil2
D := rxD marking condition

TxEMT goes low at the beginnmg of the last data bit.ar, If parity IS enabled, at the beginning 01 the panlybit.

RxRDY

(Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode])

READ
STATUS

o
RJD

I~

A "

1;2 1 3 ,4 I
DATAl

OVERRUN

REAO

READ
RHR
(DATAl)

STATUS

51 B I C

I
,,

It

1"

2 ! 3 14
OArA2

READ
RHR

READ

RHR

READ
RHR

(OATA2)

(DATA3)

(DATA3)

151 B Ie ) - , 0 , I
,

It

I'!

2( 3 I 4 (5
DATA 3

I

B I

:

T'-_--+_____________--'". . .

STATU:;.S:::.'.:..T_ _ _ _ _ _ _ _ _ _

CEFOR-----------, ,f-----------------"'-.:::::-:. ,,---READ

RHR

READ
RHR

(DATA I)

(DATA3)

READ

NOTES
A

Slanb,!

B
C
o

Slopbll!
Stopblt2
TxD markmg condition

115

TIMING DIAGRAMS (Cont'd)

RESET

CLOCK

RESET-1='RES~--

BRCLK, TiC,

TRANSMIT

Rill

RECEIVE

1 BIT TIME
(1, 16, OR 64 CLOCK PERIODS)

-i

TxC
(INPUT)

TxD

TxC

(OUTPUT)

READ AND WRITE

ce---\I

Ao,A,

0 0 -0 7

(WRITE)

00·01
(READ)

~~~~-J''-~~Jr~-------4--J~-----------

116

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range .................................................................. O°C to + 70°C
Storage Temperature Range .................................................................. -55°C to +150°C
Lead Temperature (soldering, 10 sec.) .................................................................. +325°C
Positive Voltage on any Pin, with respect to ground ....................................................... +18.0V
Negative Voltage on any Pin, with respect to ground .................................................•..... -o.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this
specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it it important that the Absolute Maximum
Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their
outputs when the AC power is switched on and off. In addition, voltage transients on the AC power line may appear on the
DC output. For example, the bench power supply programmed to deliver +12 volts may have large voltage transients when
the AC power is switched on and off. If this possibility exists it is suggested that a clamp circuit be used.

DC ELECTRICAL CHARACTERISTICS
PARAMETER

V,L
V,H
VOL
VOH
I,L
ILH
ILL
Icc
C,N

Input voltage
Low
High
Output voltage
Low
High
Input leakage current
Output leakage current
Data bus high
Data bus low
Power supply current
Capacitance
Input

TA=O°C to +70°C, Vcc =5.0V ±5%
MIN

TYP

MAX

UNIT

0.8

V

0.4

V

10

pA

10
10
150

pA
/lA
mA

20

pF

2.0

2.4

COUT

Output

20

pF

C,iO

Input/Output

20

pF

AC ELECTRICAL CHARACTERISTICS
PARAMETER

tAES
teE
tAS
tAH
tes
teH
tos
tOH
tAxS
tAXH
too
tOF
teED
fBA'j
fAfT
tBAH
tBRL

tAfTH
tAfTL1
ITxo
ITes

Pulse width
Reset
Chip enable
Setup and hold time
Address setup
Address hold
8/W control setup
R/W control hold
Data setup for write
Data hold for write
Rx data setup
Rx data hold
Data delay time for read
Data bus floating time
Jorread
CE to CE delay
Input clock frequency
Baud r~enerator
TxCorRx
Clock width
Baud rate high
Baud rate low
TxC or R'i<'C high
TxC or AXe low
TxD delay from falling
edgeofTxC
Skew between TxD
changinlfBd falling
edge of Tx output

TEST CONDITIONS

IOL=1.6mA
IOH=-100pA
V ,N =Ot05.25V
Vo=4.0V
Vo=0.45V

fc=1MHz
Unmeasured pins tied
to ground

TA=O°C to +70°C, Vee=5.0V ±5%
MIN

TYP

MAX

UNIT

1000
300

ns
ns

20

ns
ns
ns
ns
ns
ns
ns
ns
ns

20
20
20
225
0
300
350
250
150

ns
ns

5.0738
1.0

MHz
MHz

700
1.0
dc

5.0688

70
70
500
500
650
0

NOTE:
1. fAfT and tR(TL shown for all modes except Local Loopback. For Local Loopback mode
fR[T=O.7 MHz and tA/TL =7oons min.

117

TEST CONDITIONS

CL=100pF
CL=100pF

ns
ns
ns
ns

fBAG=5.0688MHz
fBAG =5.0688MHz

ns

CL=100pF

ns

CL=100pF

TYPICAL APPLICATIONS

SYNCHRONOUS INTERFACE
TO TERMINAL OR
PERIPHERAL DEVICE

ASYNCHRONOUS INTERFACE
TO CRT TERMINAL

ADDRESS BUS

ADDRESS BUS

CONTROL BUS

CONTROL BUS

I
\

DATA BUS

----!

J

\

I

\

DATA BUS

JB~

R.D

R.D . . .

T.D
T.DJ---'"

COM 2651

COM 2651

RiC
T.C

BRCU(

\-4------l

SYNCHRONOUS
TERMINAL
OR PERIPHERAL
DEVICE

CRT
TERMINAL

ASYNCHRONOUS INTERFACE
TO TELEPHONE LINES

SYNCHRONOUS INTERFACE
TO TELEPHONE LINES

PHONE
LINE

PHONE
LINE

INTER·

INTER-

FACE

FACE
SYNC
MODEM

t

TELEPHONE
LINE

TELEPHONE
LINE

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications, consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does notconveytothe purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

118

-------------------------------------------

COM 2661-1
COM 2661-2
COM 2661-3
pPC FAMILY

Enhanced Programmable
Communication Interface
EPCI
FEATURES
D Synchronous and Asynchronous Full Duplex or

PIN CONFIGURATION

Half Duplex Operations

D Re-programmable ROM on-chip baud
rate generator
D Synchronous Mode Capabilities
-Selectable 5 to a-Bit Characters
-Selectable 1 or 2 SYNC Characters
-Internal or External Character Synchronization
- Transparent or Non-Transparent Mode
- Transparent mode DLE stuffing (Tx)
and detection (Rx)
,
-Automatic SYNC or DLE-SYNC Insertion
-SYNC, DLE and DLE-SYNC stripping
-Odd, Even, or No Parity
-Local or remote maintenance loop back mode
D Asynchronous Mode Capabilities
-Selectable 5 to a-Bit Characters plus parity
-3 Selectable Clock Rates (1X, 16X, 64X the
Baud Rate)
-Line Break Detection and Generation
-1, 1'12, or 2-Stop Bit Detection and Generation
- False Start Bit Detection
-Odd, Even, or No Parity
-Parity, Overrun, and framing error detect
- Local or remote maintenance loop back mode
-Automatic serial echo mode (echoplex)
D Baud Rates
-DC to 1.0M Baud (Synchronous)
-DC to 1.0M Baud (1X, Asynchronous)
-DC to 62.5K Baud (16X, Asynchronous)
-DC to 15.625K Baud (64X, Asynchronous)

02 1

2801

03 2

2700

RxO 3

26 Vee
25 RxC/BKOET

GNO 4
04 5

240TR

05 6

23RTS

06

220SR

07

21 RESET
20BRCLK
19TxO
18 TxEMT/OSCHG

A012

17CTS

R/W13

160CO

RxROY 14

15TxROY

Package: 28-pin D.I.P.

D Double Buffering of Data
D RxC and TxC pins are short circuit protected
D Internal or External Baud Rate Clock
D 3 baud rate sets (2661-1, -2, -3)
D 16 internal rates for each version
D Single +5 volt Power Supply
D TTL Compatible
D No System Clock Required
D Compatible with EPCI 2661

GENERAL DESCRIPTION

The COM 2661 is an MaS/LSI device fabricated
The COM 2661 is a Universal Synchronous/
using SMC's patented COPLAMOS® technology.
Asynchronous Receiver/Transmitter (USART)
It is an enhanced pin and register compatible
designed for microcomputer system data comversion of the COM 2651 that meets the majority of
muriications. The USART is used as a peripheral
and is programmed by the processor to comasynchronous and synchronous data communicamunicate in commonly used asynchronous and
tion requirements, by interfacing parallel digital
synchronous serial data transmission techniques
systems to asynchronous and synchronous data
including IBM Bi-Sync. The USART receives serial
communication channels while requiring a minidata streams and converts them into parallel data
mum of processor overhead. The COM2661
characters for the processor. While receiving serial
contains a baud rate generator which can be
data, the USART will also accept data characters
programmed to either accept an external clock or
from the processor in parallel format, convert them
to generate internal transmit or receive clocks.
to serial format and transmit. The USART will sigSixteen different baud rates can be selected under
nal the processor when it has completely received
program control when operating in the internal
clock mode. Each version of the COM 2661 (-1,
or transmitted a character and requires service.
Complete USART status including data format
-2, -3) has a different set of baud rates. Custom
errors and control signals is available to the
baud rates can be ROM reprogrammed to accommodate different baud rates and different starting
processor at any time.
frequencies.
119
_.

__

._------_... _ - - - - -

----------------.

)

DATA BUS
00-07

DATA BUS

BUFFER

t

~

)

$YN/DLE CONTROL

SYN 1 REGISTER
SYN 2 REGISTER
OLE REGISTER

OPERATION CONTROL

RESET

~

AO

~

MODE REGISTER 1

Al

~

MODE REGISTER 2

~

COMMAND REGISTER

R/W

<=
I---

I---

STATUS REGISTER

~

r--

)

TRANSMITTER

TRANSMIT DATA
HOLDING REGISTER

TRA1'.!SMIT

TxD

SHIFT REGISTER

BRCLK

~

•

•

i5CB

m
FITS

•

•

ROM
RE-PROGRAMMABLE
BAUD RATE
GENERATOR
AND
CLOCK CONTROL

!

-

-

I--

•
MODEM
CONTROL

t

RECEIVER

RECEIVE DATA
HOLDING REGISTER
RECEIVE
SHIFT REGISTER

~

•
•

1-- -

•

RxD

"r-

..

om

..

6~~~l~

Vee

GND

COM 2661 ORGANIZATION

The COM 2661 is organized into 6 major sections.
Communicatioh between each section is achieved via
an internal data and .control bus. The data bus buffer
allows a processor access to all internal registers on the
COM 2661. The differences .between the COM 2661 and
COM 2651 are outlined in table 1.

or characters that are unique to the communication
technique and stores the "assembled" character in the
receive data holding register until read by the processor.

Transmitter
The Transmitter accepts parallel data from the processor,
converts it to a serial bit stream, inserts the appropriate
characters or bits (based on the communication technique) and outputs a composite serial stream of data on
the TxD outpUt pin.

Operation Control
This functional block stores configuration and operation commands from the processor and generates appropriate signals to various internal sections to control the
overall device operation. It contains read and write circuits to permit communications with a processor via the
data bus and contains Mode Registers 1 and 2, the
Command Register, and the Status Register. Details of
register addressing and protocol are presented in the
COM 2661 programming section of this specification.

Modem Control
The modem control provides three output signals and
accepts three input signals used for "handshaking" and
status indication between the COM 2661 and a modem.

SYN/OLE Control
This section contains control circuitry and three 8-bit
registers storing the SYN1, SYN2, and OLE characters
provided by the processor. These registers are used in
the synchronous mode of operation to provide. the
characters required for synchronization, idle fill and
data transparency.

Timing
The COM 2661 contains a Baud Rate Generator (BRG)
which is programtnable to accept external transmit or
receive clocks or to divide an external clock to perform
data communications. The unit can geherate 16 commonly used baud rates, anyone of which Can be selected
for full duplex operation. Tables 2a, b, and c illustrate all
available baud tates.

Interface Signals
The COM 2661 interface signals can be grouped into
two types: the processor-related signals (shown in Table
3) which interface the COM 2661 to the processor, and
the device-related signals (shown in Table 4), which are
used to interface to the communications equipment.

Receiver
The Receiver accepts serial qata on the RxD pin, converts this serial input to parallel format, checks for bits

120

TABLE 3-PROCESSOR RELATED SIGNALS
NAME

PIN NO.
1,2,5,6,
7,8,27,28
10,12

SYMBOL

FUNCTION

Data

07-00

Bidirectional; 8 bit, three state data bus used to transfer commands, data and status
between the COM 2661 and a processor. 00 is the least significant bit; 07 is the most
significant bit.

Address

Al,A0

Input; Address lines used to select COM 2661 registers.

11

Chip Enable

CE

13

Read/Write

P,/W

Input; Processor read/write direction control. This signal defines the direction of the
data bus 07-0 when the COM 2661 is selected. 07-0 drives out (read) when this signal is
low and accepts data input when this signal is high. The input only has meaning when
the CE input is active.

14

Receiver Ready

RxRDY

Output; This Signal is the complement of Status Register bit 1 (SRI). When low, it
indicates that the Receive Data Holding Register (RHR) has a character ready for input
to the processor. It goes high when the RHR is read by the processor, and also when
the receiver is disabled. It is an open drain output which can be used as an interrupt
to the processor.

15

Transmitter
Ready

TxRDY

Output; This signal is the complement of Status Register bit 0 (SRO). When low, it
indicates that the Transmit Data Holding Register (THR) is ready to accept a data
character from the processor. Itgoeshighwhenthedata characteris loaded. Thisoutput
is valid only when the transmitter is enabled. It is an open drain output which can be
used as an interrupt to the processor.

18

Transmitter
empty/data
set change

TxEMT/

Output; This signal is the complement of Status Register bit 2 (SR2). When low, it
indicates that the transmitter has completed serialization of the last character loaded
by the processor, or that a change of state of the DSR or DCD inputs has occurred.
This output goes high when the Status Register is read by the processor, if the
TxEMT condition does not exist. Otherwise, the THR l)1ust be loaded by the processor
for this line to go high. It is an open drain output which can be used as an interrupt
to the processor.

21

Reset

26

Supply Voltage

4

Ground

DSCRG

Reset

Vee
GND

Input; when this signal is low, the operation specified by the R/W, AI and A0 will be
performed. When this input is high, 07-0 are in the high impedance state.

Input; A high on this input performs a master reset on the COM 2661. This signal
asynchronously terminates any device activity and clears the Mode, Command and
Status registers. The device assumes the idle state and remains there until initialized
with the appropriate control words.
+5 volts supply.
Ground.

TABLE 4-DEVICE RELATED SIGNALS
PIN NO.

NAME

3

Receive Date

9

Transmitter
Clock/External
Sync

16

SYMBOL
RxD

FUNCTION
Input; Serial data to the receiver. "Mark" is high "space" is low.

TxC/
XSYNC

Input or Output; If the external transmitter clock is programmed, this input controls
the rate at which the character is transmitted. Its frequency is IX, 16X or 64X, the Baud
rate as programmed by Mode Register 1. The transmitted data changes on the falling
edge of the clock. If the internal transmitter clock is programmed, this pin can be a
lX/16X clock output or an external jam synchronization input.

Data Carrier
Detect

DCD

Input; This signal must be low in order fo~receiver to function. The complement
appears in the Status Register bit 6 (SR6). DCD causes a low Qutputon TxEMT /DSCHG
when its state changes if CR2 or CRO= 1. II DCD goes high while receiving, the RxC
is internally inhibited.

17

Clear to Send

CTS

Input; This signal must be low in order for the transmitter to function. II it goes high
during transmission, the character in the Transmit Shift Register will be transmitted
before termination.
.
.

19

Transmit Data

TxD

Output; Serial data from the transmitter. "Mark" is high, "Space" is low. This signal is
held in the "Mark" condition when the'trilnsmitter is disabled.

20

Baud Rate Clock

22

Data Set Ready

DSR

Input; This general purpose signal can be used for Data Set Ready~inQ Indicator
condition. Its complement appears ils Status Register bit 7 (SR7). DSR causes' a low
output on TxEMT /DSCHG when its state changes if CR2 or CRO=I.

23

Request to Send

RTS

Output; This general purpose signal is the complement of the Command Register bit 5
(CR5). It is normally used to indicate Re~lto Send. lithe TransmitShilt Registeris not
empty when CRS is reset (1 to 0), then RTS will go high on TxC time after the last serial
bit is transmitted.
.

24

Data Terminal
Ready

DTR

Output; This general purpose signal is the complement of the Command Register
bit 1 (CR1). It is normally used to indicate Data Terminal Ready.

25

Receive Clock/
Break Detect

BRCLK

RxC/
BKDET

Input; Clock input to the internal baud rate generator (See Tables 2a, b and c); not
required if the external receiver and transmitter clocks are used.

Input or Output; If the external receiver clock is programmed, this input controls the
rate at which the character is to be received. Its frequency is IX, 16X, or 64X the Baud
rate, as prpgrammed by Mode Register 1. Data are sampled on the rising edge of the
clock. If internal receiver clock is programmed, this p'in can bea lX/16X clock or a
break detect output.

121

I

Table 2b BAUD RATE GENERATOR CHARACTERISTICS
2661-2 (BRCLK=4.9152MHz)

Table 1 COM 2661 ¥s. COM 2651
1.MR2Bi16,7

Controlpin9,25

Not used

2.DLEdelect-SR3

SR3=:O for OLE-OLE,
OlE-SYNC1

SR3= tlor OLE-OLE.
OLE-SYNC!

Second character after
OLE; or receiver
dlsable,orCR4=1

Receiverdisable. or
CR4 = 1

4. Send OLE-CR3

One lime command

Reset via CR3 on next
TxADY

3. Reset of SA3, OLE

detect

5. OLE stuflmg in
Iransparentmode

Automatic OLE stuffing
when OLE is loaded
except I! CR3 == 1

None

6. SYNCt stnpping
in double sync
non-transparent
mode

All SYNC1

First SYNC! of pair

7. Baudraleversions

Three

One

B. TerminateASYNC

Reset CRS in response 10 Reset CRO when TJ(EMT
TxRDY changing from
goes from t to O. Then
0 to 1
reset CAS when TxEMT
goesfromOtol

transmission
(drop RTS)

9. Break delect
10. Stop bit searched
11. External jam sync

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
~-----.-

45.5
50

----

Two
No

12. Data bus timing

Improved over 2651

13. Data bus drivers

Sink 2.2mA
Source400IlA

MR23-20

-----OOOo-=--- 0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110

Sink 1.6mA
Source 100llA

1 InternalBRGusedlorRxC
:1 InternalBRGusedlorTxC

Table 2a BAUD RATE GENERATOR CHARACTERISTICS
2661-1 (BRCLK=4.9152MHz)
MR23-20

BAUD
RATE

ACTUAL
FREQUENCY
16X CLOCK

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
ttl1

50
75
110
134.5
150
200
300
600
1050
1200
1800
2000
2400
4800
9600
19200

0.8kHz
1.2
1.7598
2.152
2.4
3.2
4.8
9.6
16.8329
19.2
28.7438
31.9168
38.4
76.8
1536
307.2

PERCENT
ERROR

-001

0196
-0.19
-0.26

75
110
134.5
150
300
600
1200
1800
2000
2400
4800
g60a
19200
38400

ACTUAL
FREQUENCY
16XCLOCK

a 7279kHz
08
1.2
1.7598
2.152
2.4
4.8
9.6
192
28.7438
31.9168
38.4
768
153.6
3072
614.4

PERCENT
ERROR

0.005

-001

-0.19
-0.26

DIVISOR

6752
6144
4096
2793
2284
2048
1024
512
256
171
154
128
64

32

"
8

Table 2c BAUD RATE CHARACTERISTICS
2661:..3 (BRCLK=5.06BBMHz)

FEand null character

Pm 25'
One
Pin 9'

BAUD
RATE

MR23·20

DIVISOR

6144
4096
2793
2284
2048
1536
1024
512
292
256
171
154
128

ACTUAL
BAUD
FREQUENCY
PERCENT
.-"R..
AT,-"E.~r-"16",X",CL",O",CK'-r---",ER,",R",OR,"--.....
D~'V,..'SO",R"--I

5008kHz
75
1.2
110
1.76
134.5
2.1523
150
2.4
300
4.8
600
96
1200
192
1800
28.8
2000
32.081
2400
38.4
3600
576
4800
768
7200
115.2
9600
1536

NOTE~ _~C!..0_

0.016

0253

6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33

L.._",-,31",6.8'_--L.--",3...
12"-.5--,-_,,"'---...J

15Xclocklsusedmasynchronousmode In synchronous mode. clock mult,pherl$ lXand
BRGcanbeusedonlylorTxC

64
32
16

COM 2661 OPERATION
The functional operation of the COM 2661 is programmed
by a set of control words supplied by the processor.
These control words specify items such as synchronous
or asynchronous mode, baud rate, number of bits per
character, etc. The programming procedure is described
in the COM 2661 Programming section of this data sheet.
After programming, the COM 2661 is ready to perform
the desired communications functions. The receiver
performs serial to parallel conversion of data received
from a modem or equivalent device. The transmitter
converts parallel data received from the processor to a
serial bit stream. These actions are accomplished within
the framework specified by the control words.

bits are strobed into the status register on the positive
going edge of RxC corresponding to the received character boundary. If the stop bit is present, the receiver will
immediately begin its search for the next start bit. If the
stop bit is absent (framing error), the receiver will interpret a space as a start bit if it persists into the next bit
time interval. If a break condition is detected (RxD is
low for the entire character as well as the stop bit), only
one character consisting of all zeros (with the Framing
error status bit set) will be transferred to the Holding
Register. The RxD input must return to a high condition
before a search for the next start bit begins.
Pin 25 can be programmed to be a break detect output
by appropriate setting of MR27-MR24. If so, a detected
break will cause that pin to go high. When RxD returns to
mark for one RxC time, pin 25 will go low. Refer to the
break detection timing diagram.
When the COM 2661 is initialized into the synchronous
mode, the receiver first enters the hunt mode on a 0 to 1
transition of RxEN (CR2). In this mode, as data is shifted
into the Receiver Shift Register a bit at a time, the contents of the register are compared to the contents of the
SYN1 register. If the two are not equal, the next bit is
shifted in and the comparison is repeated. When the two
registers match, the hunt mode is terminated and character assembly begins. If the single SYN operation is
programmed, the SYN DETECT status bit is set. If double
SYN operation is programmed, the first character assembled after SYN1 must be SYN2 in order for the SYN
DETECT bit to be set. Otherwise, the COM 2661 returns
to the hunt mode. (Note that the sequence SYN1-SYN1-

Receiver
The COM 2661 is conditioned to receive data when the
DCD input is low and the RxEN bit in the command
register is true. In the asynchronous mode, the receiver
looks for a high to low (mark to space) transition of the
start bit on the RxD input line. If a transition is detected,
the state of the RxD line is sampled again after a delay of
one-half of a bit time. If RxD is now high, the search for
a valid start bit is begun again. If RxD is still low, a valid
start bit is assumed and the receiver continues to sample
the input line at one bit time intervals until the proper
number of data bits, the parity bit, and one stop bit have
been assembled. The data is then transferred to the
Receive Data Holding Register, the RxRDY bit in the
status register is set, and the RxRDY output is asserted.
If the character length is less than 8 bits, the high order
unused bits in the Holding Register are set to zero. The
Parity Error, Framing Error, and Overrun Error status
122

------------------------------------------------SYN2 will not achieve synchronization). When synchronization has been achieved, the COM 2661 continues to assemble characters and transfers them to the
Holding Register. The RxRDY status bit is set and the
RxRDY output is asserted each time a character is assembled and transferred to the Holding Register. The Overrun
error (OE) and Parity error (PE) status bits are set as
appropriate. Further receipt of the proper SYN sequence
sets the SYN DETECT status bit. If the SYN stripping
mode is commanded, SYN characters are not transferred to the Holding Register. Note that the SYN characters used to establish initial synchronization are not
transferred to the Holding Register in any case.
External jam synchronization can be achieved via pin 9
by appropriate setting of MR27-MR24. When pin 9 is an
XSYNC input, the internal SYN1, SYN1-SYN2, and DLESYN1 detection is disabled. Each positive going signal
on XSYNC will cause the receiver to establish synchronization on the rising edge of the next RxC pulse.
Character assembly will start with the RxD input at this
edge. XSYNC may be lowered on the next rising edge of
RxC. This external synchronization will cause the SYN
DETECT status bit to be set until the status register is
read. Refer to XSYNC timing diagram.

COM 2661 PROGRAMMING
Prior to initiating data communications, the COM 2661
operational mode must be programmed by performing
write operations to the mode and command registers.
In addition, if synchronous operation is programmed,
the appropriate SYN/DLE registers must be loaded. The
COM 2661 can be reconfigured at any time during program execution. A flow chart of the initialization process
appears in Figure 1.
The internal registers of the COM 2661J!.re accessed by
applying specific signals to the CE, R/W, A1 and AO
inputs. The conditions necessary to address each register
are shown in Table 5.
The SYN1, SYN2, and DLE registers are accessed by
performing ~rite operations with the conditions A1 =0,
AO=1, and R/W=1. The first operation loads the SYN1
register. The next loads the SYN2 register. and the third
loads the DLE register. Reading or loading the mode
registers is done in a similar manner. The first write (or
read) operation addresses Mode Register 1, and a subsequent operation addresses Mode Register 2. If more
COM 2661 INITIALIZATION FLOW CHART

Transmitter
The COM 2661 is conditioned to transmit data when the
CTS input is low and the TxEN command register bit is
set. The COM 2661 indicates to the processor that it can
accept a character for transmission by setting the
TxRDY status bit and asserting the TxRDY output. When
the processor writes a character into the Transmit Data
Holding Register, the TxRDY status bit is reset and the
TxRDY output is returned to a high (false) state. Data
is transferred from the Holding Register to the Transmit
Shift Register when it is idle or has completed transmission of the previous character. The TxRDY conditions are then asserted again. Thus, one full character
time of buffering is provided.
In the asynchronous mode, the transmitter automatically
sends a start bit followed by the programmed number
of data bits, the least significant bit being sent first. It then
appends an optional odd or even parity bit and the programmed number of stop bits. If, following transmission
of the data bits, a new character is not available in the
Transmit Holding Register, the TxD output remains in
the marking (high) condition and the TxEMT IDSCHG
output and its corresponding status bit are asserted.
Transmission resumes when the processor loads a new
character into the Holding Register. The transmitter can
be forced to output a continuous low (BREAK) condition by setting the Send Break command bit high.
In the synchronous mode, when the COM 2661 is initially
conditioned to transmit, the TxD output remains high and
the TxRDY condition is asserted until the first character to
be transmitted (usually a SYN character) is loaded by the
processor. Subsequent to this, a continuous stream of
characters is transmitted. No extra bits (other than parity,
if commanded) are generated by the COM 2661 unless the
processor fails to send a new character to the COM 2661
by the time the transmitter has completed sending the
previous character. Since synchronous communication
does not allow gaps between characters, the COM 2661
asserts TxEMT and automatically "fills" the gap by
transmitting SYN1s, SYN1-SYN2 doublets, or DLE-SYN1
doublets, depending on the state of MR16 and MR17.
Normal transmission of the message resumes when a new
character is available in the Transmit Data Holding
Register. If the SEND DLE bit in the command register is
true, the DLE character is automatically transmitted
prior to transmission of the message character in the
transmit holding register.

INITIAL RESET

NOTE
Mode Register 1 must be written
L...=;.;;.;.;;;;.;;;.;;=~ before 2 can be written. Mode Register 2
need not be programmed if external
clocks are used.

r--....,.,,,,",,"---.
N

NOTE
SVN1 Register must be written
before SVN2 can be written. and
SVN2 before DLE can be written.

N
N

Figure 1

123

than the required number of accesses are made, the
internal sequencer recycles to point at the first register.
The pointers are reset to SYN1 Register and Mode
Register 1 by a RESET input or by performing a "Read
Command Register" operation, but are unaffected by any
other read or write operation.
The COM 2661 register formats are summarized in
Tables 6, 7, Band 9. Mode Registers 1 and 2 define the
general operational characteristics of the COM 2661,
while the Command Register controls the operation
within this basic framework. The COM 2661 indicates
its status in the Status Register. These registers are
cleared when a RESET input is applied.

CE

A1

AO

RIW

1
0
0
0
0
0
0
0
0

X

X

X

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

FUNCTION
Tri-state data bus
Read receive holding register
Write transmit holding register
Read status register
Write SYNI/SYN2/DLE registers
Read mode registers 1 and 2
Write mode registers 1 and 2
Read com mand register

Write command register

NOTE
See AC Characteristics section for timing requirements.

Table 5-COM 2661 REGISTER ADDRESSING

MODE REGISTER 1 (MR1)
In asynchronous mode, MR17 and MR16 select character
framing of 1, 1.5, or 2 stop bits (if 1X baud rate is programmed, 1.5, stop bits defaults to 1 stop bits on transmit). In synchronous mode, MR17 controls the number
of SYN characters used to establish synchronization
and for character fill when the transmitter is idle. SYN1
alone is used if MR17= 1, and SYN1-SYN2 is used when
MR17=0. If the transparent mode is specified by MR16,
DLE-SYN1 is used for character fill and SYN Detect, but
the normal synchronization sequence is used. When
transmitting, a DLE character in the transmit holding
register will cause a second DLE character to be transmitted. This DLE stuffing eliminates the software DLE
compare and stuff on each transparent mode data character. If the send DLE command (CR3) is active when a
DLE is loaded into THR, only one additional DLE will be
transmitted. Also DLE stripping and DLE Detect (with
MR14=0) are enabled.

Table 6 illustrates Mode Register 1. Bits MR11 and MR10
select the communication format and Baud rate multiplier. 00 specifies synchronous mode and 1X multiplier.
1X, 16X, and 64X multipliers are programmable for
asynchronous format. However, the multiplier in asynchronous format applies only if the external clock input
option is selected by MR24 or MR25.
MR13 and MR12 select a character length of 5, 6, 7, orB
bits. The character length does not include the parity bit,
if programmed, and does not include the start and stop
bits in asynchronous mode.
MR14 controls parity generation. If enabled, a parity bit
is added to the transmitted character and the receiver
performs a parity check on incoming data. MR15 selects
odd or even parity when parity is enabled by MR14.

SynclAsync
ASYNCH: STOP BIT LENGTH
OO=INVALIO
01 =1 STOP BIT
10=1% STOP BITS
11=2 STOP BITS

MR14
Parity Control

0=000
l=EVEN

SYNCH: NUMBER
OFSYN CHAR

SYNCH: TRANSPARENCYCONTROL

O=OOUBLE SYN
1=SINGLE SYN

O=NORMAL
1=TRANSPARENT

NOTE

MR15
Parity Type

MR16

MR17

MR13

I

MRII

MR12

Character Length

O=OISABLEO
l=ENABLEO

00=5 BITS
01=6 BITS
10=7 BITS
11=8 BITS

Baud rate factor In asynchronous applies only If external clock is selected. Factor is 16X if
internal clock is selected. Mode must be selected (MAti, MAIO) in any case.

I

MR10

Mode and Baud Rate Factor

OO=SYNCHRONOUS IX RATE
01=ASYNCHRONOUS IX RATE
10=ASYNCHRONOUS 16X RATE
11=ASYNCHRONOUS 64X RATE

TABLE 6-MODE REGISTER 1 (MR1)

MODE REGISTER 2 (MR2)
COM 2651. MR23-20 are don't cares if external clocks
are selected (MR25-24=0). The individual rates are
given in table 2a, band c.
MR24-MR27 select the receive and transmit clock source
(either the BRG or an external input) and the function
at pins 9 and 25. Refer to table 7.

Table 7 illustrates mode register 2 (MR23, MR22, MR21
and MR20 control the frequency of the internal baud rate
generator (BRG). Sixteen rates are selectable for each
COM 2661 version (-1, -2, -3). Version 1 and 2 specify a 4.9152 MHz TTL input at BRCLK (pin 20); version
3 specifies a 5.0688 MHz input which is identical to the

MR23-MR20

MR-27-MR24

0000
0001
0010
0011
0100
0101
0110
0111

TxC

RxC

Pin 9

Pin 25

E
E

E

I

E
I
E
I
E
I

TxC
TxC
IX
IX
TxC
TxC

RxC
IX
RxC
IX
RxC

16X
16X

RxC

I
E
E
I
I

I

16X
16X

1000
1001
1010
1011
1100
1101
1110
1111

TxC

RxC

Pin 9

Pin 25

Mode

E
E
I
I
E
E
I
I

E
I
E
I
E
I
E
I

XSYNC'
TxC
XSYNC'
IX
XSYNC'
TxC
XSYNC'
16X

RxC/TxC
BKDET
RxC
BKDET
RxC/TxC
BKDET
RxC
BKDET

sync
async
sync
async
sync
async
sync
async

NOTES
1. When pin 9 is programmed as XSYNC input. SYNI. SYNI-SYN2. and DLE-SYNI detection is disabled.

TABLE 7-MODE REGISTER 2 (MR2)

124

Baud Rate Selection

See baud rates in table 2

E=External clock 1=lnternal clock (BRG)
IX and 16X are clock outputs

STATUS REGISTER (SR)
The data contained in the Status Register (as shown in
Table 9) indicate receiver and transmitter conditions and
modem/data set status.
SRO is the Transmitter Ready (TxRDY) status bit. It, and
its corresponding output, are valid only when the transmitter is enabled. If equal to 0, it indicates that the
Transmit Data Holding Register has been loaded by the
processor and the data has not been transferred to the
Transmit Shift Register. If set equal to 1, it indicates that
the Holding Register is ready to accept data from the
processor. This bit is initially set when the Transmitter
is enabled by CRO, unless a character has previously
been loaded into the Holding Register. It is not set when
the Automatic Echo or Remote LOOR Back modes are
programmed. When this bit is set, the TxRDY output pin
is low. In the Automatic Echo and Remote Loop Back
modes, the output is held high.

register is read by the processor. If the status register is
read twice and SR2=1 while SR6 and SR? remain
unchanged, then a TxEMT condition exists. When SR2 is
set, the TxEMT/DSCHG output is low.
SR3, when set, indicates a received parity error when
parity is enabled by MR14. In synchronous transparent
mode (MR16= 1), with parity disabled, it indicates that
a character matching the DLE Register has been received,
and the present character is neither SYN1 nor DLE. This
bit is cleared when the next character following the
above sequence is loaded into the Receive Data Holding
Register, when the receiver is disabled, or by a reset
error command, CR4.
The Overrun Error status bit, SR4, indicates that the
previous character loaded into the Receive Holding
Register was not read by the processor at the time a new
received character was transferred into it. This bit is
cleared when the receiver is disabled and by the Reset
Error command, CR4.
In asynchronous mode, bit SR5 signifies that the received character was not framed by a stop bit, i.e., only
the first stop bit is checked. If the RHR contains all
D's when SR5=1, a break condition is present. In synchronous non-transparent mode (MR16=0), it indicates
receipt of the SYN1 character in single SYN mode or the
SYN1-SYN2 pair in double SYN mode. In synchronous
transparent mode (MR16= 1), this bit is set upon detection of the initial synchronizing characters (SYN1 or
SYN1-SYN2) and, after synchronization has been
achieved, when a DLE-SYN1 pair is received. The bit is
reset when the receiver is disabled, when the Reset Error
command is given in asynchronous mode, or when the
Status Register is read by the processor in the synchronous mode.
SR6 and SR? reflect the conditions of the DCD and DSR
inputs respectively. A low input sets the corresponding
status bit and a high input clears it.

SR1, the Receiver Ready (RxRDY) status bit, indicates
the condition of the Receive Data Holding Register. If set,it
indicates that a character has been loaded into the
Holding Register from the Receive Shift Register and is
ready to be read by the processor. If equal to zero, there
is no new character in the Holding Register. This bit is
cleared when the processor reads the Receive Data
Holding Register or when the receiver is disabled by CR2.
When set, the RxRDY output is low.
The TxEMT/DSCHG bit, SR2, when set, indicates either
a change of state of the DSR or DCD inputs (when CR2
or CRO= 1) or that the Transmit Shift Register has completed transmission of a character and no new character
has been loaded into the Transmit Data Holding Register.
Note that in synchronous mode this bit will be set even
though the appropriate "fill" character is transmitted.
TxEMT will not go active until at least one character has
been transmitted. It is cleared by loading the Transmit
Data Holding Register. The DSCHG condition is enabled
when TxEN = 1 or RxEN = 1. It is cleared when the status
SR7

SR6

Data Set

Ready

Data Carrier
Detect

O=DSRINPUT
IS HIGH
1 =DSR INPUT
ISLOW

O=DCD INPUT
IS HIGH
1 =DCD INPUT
ISLOW

SRS
FE/SYN Detect

ASYNCH:
O=NORMAL
l=FRAMING
ERROR
SYNCH:
O=NORMAL
l=SYN CHAR
DETECTED

SR4

SR3

Overrun

PE/DLE Detect

O=NORMAL
l=OVERRUN
ERROR

ASYNCH:
D=NORMAL
l=PARITY
ERROR
SYNCH:
O=NORMAL
1 =PARITY
ERROR
OR
DLECHAR
RECEIVED

SR2
TxEMT/DSCHG
O=NORMAL
l=CHANGE
IN DSROR
DCD. OR
TRANSMIT
SHIFT REGIS·
TEAlS

EMPTY

TABLE 9-STATUS REGISTER (SR)

126

SRl

RxRDY
O=RECEIVE
HOLDING REG
EMPTY
1 =RECEIVE
HOLDING REG
HAS DATA

SRO

TxRDY
O=TRANSMIT
HOLDING
REG BUSY
l=TRANSMIT
HOLDING
REG EMPTY

TIMING DIAGRAMS
TxRDY, TxEMT

(Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode])

DATA 1

DATA 4

....--D-----...AI'(2131415IB

I

TxD

TxEN

-.-J

C

DATA 1

I

A

I' ,

2, 3, ,
DATA 3

i1
5

B

C ..... D ......~

I

I

I

I

I

I

I

DATA 4

:

-----,-5==:'==-~----,:
'-------'~~

CEFo--l--R1f}e
r'
I---WRITE

OF THR
DATA 1

DATA 2

DATA 3

DATA 4

NOTES
A =Start bit
B =Stop bit 1
C =Stop bit 2
P =TxD marking condition
TxEMT goes low 'lt the beginning of the last data bit, or, if parity is enabled, at the beginning of the parity bit.

RxRDY

(Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode])

RxEN

SYNDET
STATUS:.;B:;.'T:...-_ _ _ _ _ _- - '

J

CEFOR
READ
READ
STATUS

READ
STATUS

READ

READ

READ

READ

(DATA1)

(DATA 2)

(DATA3)

(DATA3)

RHR

RHR

D

~
R.D - - - - ,

I 3 14 1 51 B I C

A 1'12

DATA 1

I

,

I

A

f '1

2

1 3 1 4 I 51 B l e i - I 0 1 - A
DATA 2

I

:

I

l'

RHR

I 21 3 1 4 I

51

B

RHR

I

DATA 3

RxEN

OVERRUN
STATU;:.S:::B'"'-T_ _ _ _ _ _ _ _ _ _+_-;~-------------"""'<:_..J

C E F O R - - - - - - - - - - - - - ' ' ' ' ,,~---------------..::.....,....-.., ,,~--READ
READ

READ

(DATA 1)

(DATA3)

RHR

RHR

NOTES
A
B
C
D

=Slartbit
=Stopbit 1
=Stopbit2
= TxD marking condition

127

I

TIMING DIAGRAMS (Cont'd)

RESET

CLOCK

BRCLK, TiC,

RiC

RECEIVE

TRANSMIT

-

1 BIT TIME
(1, 16, OR 64 CLOCK PERIODS)

~

TxC
(INPUT)

TxD

TiC

(OUTPUT)

EXTERNAL SYNCHRONIZATION WITH XSYNC
1X

READ AND WRITE

Rx~

tes

XSYNC SETUP TIME--300ns

tH~ XSVNC HOLD TIME
XSYNC---1

cr---"",I

ONE RxC

I

-j
RxD

Ao.A,
CHARACTER ASSEMBLY

BREAK DETECTION TIMING
Rx CHARACTER- 5 BITS, NO PARITY

DO-07
(WRITE)

AxC-: 16
or 64

n
l

RxD

DQ-D7

I LOOK FOR START BIT·- L.OWClF RxD IS HIGH.:
I LOOK fOR HIGH TO LOW TRANSITION)
I
FALSE START BIT CHECK MADE (RxD LOW) I

f

.

.

(READ) ";';;==~f-'
SET FE BIT"

NOTE
*If the stop bit is present, the start bit
search will commence immediately.

128

MISSING STOP BIT DETECTED,
SET FE BIT.
o ·RHR, ACTIVATE RxADY.
SET BKDET PIN.
RxD INPUT· RxSR UNTIL A MARK
TO SPACE TRANSITION OCCURS.

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range .................................................................. 0° C to + 70° C
Storage Temperature Range .................................................................. -55°C to +150°C
Lead Temperature (soldering, 10 sec.) .................................................................. +325°C
Positive Voltage on any Pin, with respect to ground ....................................................... +18.0V
Negative Voltage on any Pin, with respect to ground ....................................................... -0.3V

'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this
specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it it important that the Absolute Maximum
Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their
outputs when the AC power is switched on and off. In addition, voltage transients on the AC power line may appear on the
DC output. For example, the bench power supply programmed to deliver +12 volts may have large voltage transients when
the AC power is switched on and off. If this possibility exists it is suggested that a clamp circuit be used.
DC ELECTRICAL CHARACTERISTICS TA =0°Cto+70°C, Vcc=5.0V±5%

VIL
V,H
VOL
VOH
IlL
IeH
IeL
Icc
C,N

CO UT
Cia

PARAMETER
In put voltage
Low
High
Output voltage
Low
High
Input leakage current
Output leakage current
Data bus high
Data bus low
Power supply current
Capacitance
Input
Output
Input/Output

MIN

TYP

TEST CONDITIONS

MAX

UNIT

0.8

V

0.4

V

10

pA

10
10
150

pA
pA
mA

Vo=4.0V
Vo=0.45V

20
20
20

pF
pF
pF

fc=1MHz
Unmeasured pins tied
to ground

MAX

UNIT

TEST CONDITIONS

2.0

2.4

IOL=2.2mA
IOH=-400pA
V,N=O to 5.5V

AC ELECTRICAL CHARACTERISTICS TA =0°Cto+70°C, Vcc=5.0V±5%

tRES

tCE
tAs
tAH

les
tCH
tos
tOH
tRxS
tRXH

too
tOF
teEo
fSRG
fSRG

PARAMETER
Pulse width
Reset
Chip enable
Setup and hold time
Address setup
Address hold
B/W control setup
R/W control hold
Data setup for write
Data hold for write
Rx data setup
Rxdata hold
Data delay time for read
Data bus floating time
for read
CE to CE delay
Input clock frequency
,Baud rate generator
(2661-1, -2)
Baud rate generator

MIN

TYP

1000
250

ns
ns

10
10
10
10
150
0
300
350

ns
ns
ns
ns
ns
ns
ns
ns
ns

CL=150pF

ns

CL=150pF

200
100

ns

600
1.0

4.9152

4.9202

MHz

1.0

5.0688

5.0738

MHz

1.0

MHz

~66~
fR Tl

tBRH
tSRH

teAL
teAL
tR 11-11

tR TL

hxo
~TCS

TxCorRxC
Clock width
Baud rate high
(2661-1, -2)
Baud rate high
(2661-3)
Baud rate low
(2661-1,-2)
Baud rate low
_(2661-3)
TxC or RxC high
TxC or RxC low
TxD delay from falling
edge of TxC
Skew between TxD
changinQMd falling
edge of TxC output

dc
75

ns

70

ns

75

ns

70

ns

480
480

ns
ns
650
0

NOTE:
1.

and tR TL shown all modes except Local Loopback. For Local Loopback mode
r=O.7MHz and tA TL =700ns min.

fR T

fA

.129

fSRG=4.915MHz; measured
atV,H
fsRG=5.0688MHz; measured
atV,H
fsRG =4.915MHz; measured
atVIL
fSRG=5.0688MHz; measured
atVIL

ns

CL=150pF

ns

CL=150pF

TYPICAL APPLICATIONS

SYNCHRONOUS INTERFACE
TO TERMINAL OR
PERIPHERAL DEVICE

ASYNCHRONOUS INTERFACE
TO CRT TERMINAL

\

ADDRESS BUS

\

ADDRESS BUS

L
\

DATA BUS

r------,

R.D
T.D

COM 2661

~

.,ATom
CONVERT

r-,"-if2J)-=Oo----.-.

I

I

J~~~
T.D

COM 2661

R.C
T.C

BRCLK ....._ _ _

~

5.0688 MHz

\

DATA BUS

R.D

1---"L ______ J
(OPT)

\

CONTROL BUS

CONTROL BUS

SYNCHRONOUS
TERMINAL
OR PERIPHERAL

DEVICE

CRT

OSCILLATOR

TERMINAL

ASYNCHRONOUS INTERFACE
TO TELEPHONE LINES

SYNCHRONOUS INTERFACE
TO TELEPHONE LINES

PHONE
LINE

PHONE
LINE

INTER·

INTER·

FACE

FACE
SYNC
MODEM

t

TELEPHONE
LINE

TELEPHONE
LINE

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications, c~nsequently complete information sufficient for construction purposes is not necessarily given. The
informatIOn has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey tothe purchaserofthesemiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve rlgsign and supply the best product possible.

130

---- ------------------------

COM 5025
JLPC FAMILY

Multi-Protocol
Universal Synchronous Receiver/Transmitter
USYNR/T
PIN CONFIGURATION

FEATURES

o Selectable Protocol-Bit or Byte oriented

M5EL
Tep

o Direct TTL Compatibility

T50

o Three-state Input/Output BUS
o Processor Compatible-8 or 16 bit

TXENA

T5A
ADA

o High Speed Operation-1.5 M Baud-typical

TXACT

o Fully Double Buffered-Data, Status, and Control Registers
o Full or Half Duplex Operation-independent Transmitter and

o
o

TBMT
MA
Vee

OBee

OB~'
OB02

Receiver Clocks
-individually selectable data
length for Receiver and
Transmitter
Master Reset-resets all Data, Status, and Control Registers
Maintenance Select-built-in self checking

DB~3

OB04
OB05
OB06
OB~7

DPENA
BYTE OP
A~

PACKAGE: 40-Pin D.i.P.

BIT ORIENTED PROTOCOLS-SDLC, HDLC, ADCCP
o Automatic bit stuffing and stripping
o Automatic frame character detection and generation
o Valid message protection-a valid received message is
protected from overrun
o Residue Handling-for messages which terminate with a
partial data byte, the number of valid
data bits is available

BYTE ORIENTED PROTOCOLS-BISync, DDCMP
o Automatic detection and generation of SYNC characters
SELECTABLE OPTIONS:

o Variable Length Data-1 to 8 bit bytes
o Variable SYNC character-5, 6, 7, or 8 bits
o Error Checking-CRC (CRC16, CCITT-O, or CCITT-1)
o

SELECTABLE OPTIONS:
o Variable Length Data-1 to 8 bit bytes
o Error Checking-CRC (CRC16, CCITT-O, or CCITT-1)
-None
o Primary or Secondary Station Address Mode
o All Parties Address-APA
o Extendable Address Field-to any number of bytes
o Extendable Control Field-to 2 bytes
Oldie Mode-idle FLAG characters or MARK the line
o Point to POint, Multi-drop, or Loop Configuration

o

-VRC (odd/even parity)
-None
Strip Sync-deletion of leading SYNC characters after
synchronization
Idle Mode-idle SYNC characters or MARK the line

APPLICATIONS

o Intelligent Terminals
o Line Controllers
o Network Processors
o Front End Communications

o Remote Data Concentractors
o Communication Test Equipment
o Computer to Computer Links
o Hard Disk Data Handler
131

General Description
The COM 5025 is a COPLAMOS® n channel silicon gate MOS/LSI device that meets the majority of
synchronous communications requirements, by interfacing parallel digital systems to synchronous serial
data communication channels while requiring a minimum of controller overhead.
The COM 5025 is well suited for applications such as computer to modem interfaces, computer to computer
serial links and in terminal applications. Since higher level decisions and responses are made or initiated by the
controller, some degree of intelligence in each controller of the device is necessary.
Newly emerging protocols such as SOLC, HOLC, and AOCCP will be able to utilize the COM 5025 with a
high degree of efficiency as zero insertion for transmission and zero deletion for reception are done
automatically. These protocols will be referred to as Bit Oriented Protocols (BOP). Any differences between
them will be discussed in their respective sections. Conventional synchronous protocols that are control
character oriented such as BISYNC can also utilize this device. Control Character oriented protocols will be
referred to as CCP protocols. Other types of protocols that operate on a byte or character count basis can
also utilize the COM 5025 with a high degree of efficiency in most cases. These protocols, such as OOCMP
will also be referred to as CCP protocols.
The COM 5025 is designed to operate in a synchronous communications system where some external
source is expected to provide the necessary received serial data, and all clock signals properly
synchronized according to EIA standard RS334. The external controller of the chip will provide the
necessary control signals, intelligence in interpreting control signals from the device and data to be
transmitted in accord with RS334.
The receiver and transmitter are as symmetrical as possible without loss of efficiency. The controller of the
device will be responsible for all higher level decisions and interpretation of some fields within message
frames. The degree to which this occurs is dependent on the protocol being implemented. The receiver and
transmitter logic operate as two totally independent sections with a minimum of common logic.

References:
1. ANSI-American National Standards Institute
X353, XS34/589
202-466-2299

3. EIA-Electronic Industries Association
TR30, RS334
202-659-2200

2. CCITT-Consultative Committee for International
Telephone and Telegraph
X.25
202-632-1007

4. IBM
General Information Brochure, GA27-3093
Loop Interface-OEM Information, GA27-3098
System Journal-Vol. 15, No.1, 1976; G321-0044

Terminology
Term

Definition

Term

Definition

BOP

Bit Oriented Protocols: SDLC, HDLC, ADCCP

GA

01111111 (0 (LSB) followedby7-1's)

CCP

Control Character Protocols: BiSync, DDCMP

LSB

First transmitted bit, First received bit

TDB

Transmitter Data Buffer

MSB

Last transmitted bit, Last received bit

RDB

Receiver Data Buffer

RDP

Receiver Data Path

TOSR

Transmitter Data Shift Register

TOP

Transmitter Data Path

FLAG

01111110

LM

Loop Mode

ABORT

11111111 (7 or more contiguous 1's)

132

BLOCK DIAGRAM
MASTER

RESET

Rep
RXENA
RXACT

RDA
RSA

SFA

1

h

:1 "-,,-,

:i;

I:

T8MT

-+---------,

0 .........

RSI

MAINT
SEL

.....

Ul
Ul

TSO

0815

0814

0813

0812

0811

DB1,if'

DBIS

DB18

Ao

At

A2

WR

DPENA BYTEOP

0817

DBJ6

OBJS

OB14

DBf3

DBJ'2

DB9'1

DB"

Description of Pin Functions
Pin No. Symbol
2
3
4

Vee
RCP
RSI
SFR

5

RXACT

6

RDA

7

RSA

8

Name

110

Function

Power Supply
PS
I
Receiver Clock
Receiver Serial Input I
Sync/Flag
0
Received
Receiver Active
0

Receiver Data
Available
Receiver Status
Available

RXENA

Receiver Enable

9
10
11
12
13
14
15
16
17
18
19
20
21
22

GND
DB/68
DB,,9
DB1/6
DBll
DB12
DB13
DB14
DB15
W/R
A2
Al
A/6
BYTEOP

Ground
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Write/Read
Address 2
Address 1
Address 0
Byte Operation

23

DPENA

Data Port Enable

+ 12 volt Power Supply.
The posHive-going edge of this clock shilts data into the receiver shift register.
This input accepts the serial bit input stream.
This OUtpu1 is set high, for 1 clock time of the
RCP, each time a sync or flag character is received.
This output is asserted when the RDP presents the first data character of the
message to the controller. In the BOP mode the first data character is the first
non·flag character (address byte). In the CCP mode: 1. if strip-sync is set; the
first non-sync character is the first data character 2. if strip-sync is not set; the
first data character Is the character following the second sync. In the BOP
mode the trailing (next) FLAG resets RXACT. In the CCP mode RXACT
is never reset, it can be cleared via RXENA.
0
This output is set high when the RDP has assembled an entire character and
transferred it into theiRDB. This output is reset by reading the ROB.
0
This output is set high: 1. CCP-in the event of receiver over run (ROR)
or parity error (if selected), 2. BOP-in the event of ROR, CRC error (if selected)
receiving REOM or RAB/GA. This output is reset by reading the
receiver status register or dropping of RXENA.
A high level input allows the processing of RSI data. A low
level disables the RDP and resets RDA, RSA and RXACT.
GND Ground
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus.
Wire "OR" with DBIJIIl-DB07
For 8 bit data bus
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus.
Controls direction of data port. W/R= 1, Write. W/R=O, Read.
Address input-MSB.
Address input.
Address input-LSB.
"asserted, byte operation (data port is 8 bits wide) is
selected. If BYTE OP=O, data port is 16 bits wide.
~*b~_~~

24
25
26
27
28
29
30
31
32
33

DB07
DB"6
DB,,5
DB!14
DB/63
DB,,2
DB/61
DB/6/6
Vee
MR

Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Power Supply
Master Reset

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PS

34

TXACT

Transmitter Active

0

35

TBMT

Transmitter Buffer
Empty

0

36

TSA

0

37

TXENA

Transmitter Status
Available
Transmitter Enable

38

TSO

0

39

TCP

Transmitter Serial
Output
Transmitter Clock

40

MSEL

Maintenance
Select

__

~~~~~~~~~

may be strobed. If reading the port, DPENA may reset (depending on register
selected by address) RDA or RSA. If writing into the port, DPENA may reset
(depending on register selected by address) TBMT.
Bidirectional Data Bus-MSB.
Bidirectional Data Bus.
Bidirectional Data Bus.
Bidirectional Data Bus.
Bidirectional Data Bus.
Bidirectional Data Bus.
Bidirectional Data Bus.
Bidirectional Data Bus-LSB.
+5 volt Power Supply.
This input should be pulsed high after power turn on. This will: clear all flags, and
status conditions, set TBMT = 1, TSO= 1 and place the device in the primary
BOP mode with 8 bit TX/RX data length, CRC CCITT initialized to aliI's.
This output indicates the status of the TOP. TXACTwili go high after asserting
TXENA and TSOM coinsidently with the first TSO bit. This output will reset one
half clock after the byte during which TXENA is dropped.
This output is at a high level when the TDB
orthe TX Status and Control Register may be loaded with
the new data. TBMT =0 on any write access to TDB or TX Status and
Control Register. TBMT returns high when the TDSR is loaded.
TERR bit, indicating transmitter underflow.
Reset by MR or assertion of TSOM.
A high level input allows the processing of transmitter
data.
This output is the transmitted character.
The positive going edge of this clock shilts data out of the
transmitter shift register.
Internally RSI becomes TSO and RCP becomes TCP.
Externally RSI is disabled and TSO= 1.

134
------~-~-.--.-

--

....

-

----------_."-

Definition of Terms
Register Bit Assignment Chart 1 and 2
DataBu
DB08
DB09
DB10
DB11
DB12-14

DB15

DB8

DB9

DB10
DB11
DB15

DB8-10

DB11

DB12
DB13
DB14
DB15
DB13-15

DB8-10

DB11
DB12

Term

Definition

RSOM

Receiver Start of Message-read only bit. In BOP mode only, goes high when first non-flag (address byte)
character loaded into RDB. It is cleared when the second byte is loaded into the RDB.
REOM
Receiver End of Message-read only bit. In BOP mode only, set high when last byte of data loaded into RDB, or
when an ABORT character is received. It is cleared on reading of Receiver Status Register or dropping of RXENA.
RAB/GA
Received ABORT or GO AHEAD character, read only bit. In BOP mode only, if LM=O this bit is set on receiving an
ABORT character; if LM = 1 this bit is set on receiving a GO AHEAD character. This is cleared on reading of
Receiver Status Register or dropping of RXENA.
ROR
Receiver Over Run-read only bit. Set high when received data transferred into RDB and previous data has not
been read, indicating failure to service RDA within one character time. Cleared on reading of Receiver Status
Register or dropping of RXENA.
A,B,C
Assembled Bit Count-read only bits. In BOP mode only, examine when REOM= 1. ABC=O, message terminated
on stated boundary. ABC=XXX, message terminated (by FLAG or GA) on unstated boundary, binary value of ABC
= number of valid bits available in RDB (right hand justified).
ERRCHK
Error Check-read only bit. In BOP set high if CRC selected and received in error, examine when REOM= 1. In
CCP mode: 1. set high if parity selected and received in error, 2. if CRC selected (tested at end of each byte) ERR
CHK = 1 if CRC GOOD, ERR CHK = 0 if CRC NOT GOOD. Controller must determine the last byte of the
message.
TSOM
Transmitter Start of Message-W/R bit. Provided TXENA-1, TSOM initiates start of message. In BOP, TSOM-1
generates FLAG and continues to send FLAG's until TSOM=O, then begin data. In CCP: 1. IDLE=O, transmit out of
SYNC register, continue until TSOM=O, then begin data. 2. IDLE=1 transmit out of TDB. In BOP mode there is also
a Special Space Sequence of 16-0's initiated by TSOM=1 and TEOM=1. SSS is followed by FLAG.
TEOM
Transmit End of Message-W/R bit. Used to terminate a message. In BOP mode, TEOM= 1 sends CRC, then
FLAG; if TXENA= 1 and TEOM= 1 continue to send FLAG's, if TXENA=O and TEOM= 1 MARK line. In CCP: 1.
IDLE=O, TEOM= 1 send SYNC, ifTXENA= 1 and TEOM=1 continue to send SYNC's, ifTXENA=O and TEOM= 1
MARK line. 2.IDLE=I, TEOM=I, MARK line.
TXAB
Transmitter Abort-W/R bit. In BOP mode only, TXAB=1 finish present character then: 1. IDLE=O, transmit ABORT
2.IDLE=1, transmit FLAG.
TXGA
Transmit Go Ahead-W/R bit. In BOP mode only, modifies character called for by TEOM. GA sent in place of FLAG.
Allows loop termination-GA character.
TERR
Transmitter Error-read only bit. Underflow, set high when TDB not loaded in time to maintain continuous
transmission. In BOP automatically transmit: 1. IDLE=O, ABORT 2. IDLE= 1, FLAG. In CCP automatically transmit:
1. IDLE=O, SYNC 2. IDLE= 1, MARK. Cleared by TSOM.
X,Y,Z
Y
X
-W/R bits. These are the error control bits.
o
0
0
X'6+X12+X5+1CCITT-lnitializeto"1"
o
0
1
X'6+ X12+ X5+ 1 CCITT-Initialize to "0"
o
1
0
Not used
X'6+ X15+ X'+ l-CRC16
o
1
1
1
0
0
Odd Parity-CCP Only
1
0
1
Even Parity-CCP Only
1
1
0
Not Used
1
1
1
Inhibit all error detection and transmission
Note: Do not modify XYZ until both data paths are idle
IDLE
IDLE mode select-W/R bit. !'Iffects transmitter only. In BOP-control the type of character sent when TXAB
asserted or in the event of data underflow. In CCP-controls the method of initial SYNC character transmission and
underflow, "1" = transmit SYNC from TDB, "O"=transmit SYNC from SYNC/ADDRESS register.
SEC ADD
Secondary Address Mode-W/R bit. In BOP mode only-atter FLAG looks for address match prior to activating
RDP, if no match found, begin FLAG search again. SEC ADD bit should not be set if EXADD=1 or EXCON=1.
STRIP SYNC/LOOP Strip Sync or Loop Mode-W/R bit. Effects receiver only. In BOP mode-allows recognition of a GA character. In
CCP-atter second SYNC, strip SYNC; when first data character detected, set RXACT =1, stop stripping.
PROTOCOL
PROTOCOL-W/R bit. BOP=O, CCP= 1
'APA
All Parties Address-W/R bit. If selected, modifies secondary mode so that the secondary address or 8-1's will
activate the RDP.
TXDL
Transmitter Data Length-W/R bits.
TXDL3 TXDL2 TXDL 1
LENGTH
o
0
0
Eight bits per character
1
1
1
Seven bits per character
1
1
0
Six bits per character
1
0
1
Five bits per character
0
0
Four bits per character'
1
o
1
1
Three bits per character'
o
1
0
Two bits per character'
o
0
lOne bit per character'
'For data length only, not to be used for SYNC character (CCP mode).
RXDL
Receiver Data Length-W/R bits.
RXDL3 RXDL2 RXDL 1
LENGTH
o
0
0
Eight bits per character
1
1
1
Seven bits per character
0
Six bits per character
1
1
0
1
Five bits per character
1
0
0
Four bits per character
1
o
1
1
Three bits per character
0
Two bits per character
o
1
o
0
1
One bit per character
EXCON
Extended Control Field-W/R bit. In receiver only; if set, will receive control field as two 8-bit bytes. Excon bit should
not be set if SEC ADD =1.
EXADD
Extended Address Field-W/R bit. In receiver only; LSB of address byte tested for a "I". If NO-continue receiving
address bytes, if YES go into control field. EX ADD bit should not be set if SEC ADD = 1.

z

'Note: Product manufactured before 1Q79 may not have this feature.

135

- - ---_.._-_. - - - - - - - - - - - - - - - - -

*

'6>
Q)

a:

eE
o

()
Q)

'0

o
:2

Register Bit Assignment Chart 1
REGISTER
Receiver Data
Buffer
(Read OnlyRight JustifiedUnused Bits= 0)
Transmitter Data
Register
(Read/WriteUnused Inputs=X)

OP07

OPlI6

Opd5

OP04

OPIJ3

OPlI2

OPlIl

OPSS

RD7

RD6

RDS

RD4

RD3

RD2

RD1

RD0

Sync/Secondary
Address
(Read/WriteRight JustifiedUnused Inputs=X)

SSA7

MSB

LSB

TD7

TD6

TDS

TD4

TD3

TD2

TD1

MSB

TD~

LSB
SSA6

SSAS

SSA4

SSA3

SSA2

SSA1

MSB

SSAi3
LSB

Register Bit Assignment Chart 2
REGISTER

OP15

OP14

OP13

OP12

OPll

OPld

OP89

opds

Receiver Status
(Read Only)

ERRCHK

C

B

A

ROR

RAB/GA

REOM

RSOM

TXStatus
and Control
(Read/Write)

TERR
(Read Only)

0

0

0

TXGA

TXAB

TEOM

TSOM

Mode Control
(Read/Write)

*APA

PROTOCOL

STRIP
SYNC/
LOOP

SEC ADD

IDLE

Z

Y

X

Data Length
Select
(Read/Write)

TXDL3

TXDL2

TXDL1

EXADD

EXCON

RXDL3

RXDL2

RXDL1

• Note: Product manufactured before 1Q79 may not have this feature.

Register Address Selection
1) BYTE OP = 0, data port 16 bits wide
A1
P$
A2

o
o

o

X

1

X
X
X

o

Register
Receiver Status Register and Receiver Data Buffer
Transmitter Status and Control Register and Transmitter Data Buffer
Mode Control Register and SYNC/Address Register
Data Length Select Register

X = don't care

2) BYTE OP = 1, data port 8 bits wide
A2
A1
AlJ

0 0 0

o
o
o

0

o
1

o
o

o
1

Register
Receiver Data Buffer
Receiver Status Register
Transmitter Data Buffer
Transmitter Status and Control Register
SYNC/Address Register
Mode Control Register

o
Data Length Select Register

136

BOP TRANSMITTER OPERATION

CCP TRANSMITTER OPERATION

(PROCESSOR LOAD OR MASTER RESET)

(PROTOCOL

==

1; XYZ

A

YES

NO

137
------------------

= CRG 16)

CCP RECEIVER TIMING
Rep

MR

JlJLJl;s.IlI1.J4s
JL

u-u-

1.,

J'L,I

~

WIR:l

W/R:O

.J

---.J C

SFR

s-LSL
[l'--_ _ l
CSTC .=L'

RDA

RSA

RXACT

-----,

I

1~

Jl JnL

W/R=O W/R=O

READ

READ
ETX

I
I
I
I

SYNC~

!-SYNe
RS'

nL.£ATA
B.EAD
1

...J

I

----'I

~

~f

W/R:O

n l!TX
~EAD

n

NOTE 1
OPENA
(not clock edge related)

RXENA

J~f

DATA 1 _ _' - _

~

I I
~
ETX

I=:

eRe

~

~

~

_I NOTE 2

ROR
ERR CHK

L
I
I
I

=r=

rLlrL
I
I
I
I
I
I

~.m2

L-

I
I
I
I
I
I

I
I

L

___r-L::

NOTE 1- Mode set for CCP with CRG selected
NOTE 2-11 overrun had occured-no READ STX
NOTE 3-ERR CHK must be sampled before next byte or before RXENA brought low

w

())

CCP TRANSMITTER OPERATION
Tep

MR

TXENA

~ ~
I
JL___
II
I

-----',--NOTE 1
MODE SYNC

DPENA

T50M:!

I I

I I
I .I
I
II T50M::1

~

I

I FIRST SYNC
I, SENT

(not clock edge related)

T8MT

n

n

~

I
I
I
I
II

TSQM=O

rfl--P r-u-,.v

LOAD
STX

LOAD
DATA 1

nI

~NOTE2--l

I

I SECOND SYNC
I, SENT

LOAD
ETX

n

u/ rvL

'lJ

TEOM=!

L

I

r--y ,..cr/

n

,JL/~

I

L

=~

r-

@};j
TSO

~SYNe

NOTE I-Mode is CCP with CRG selected
NOTE 2- Trailing edge of DPENA must occur at least one-half
crock pulse prior to TBMT=1 10 avoid underrun

~

Fx

I

'I"

SYNC

__

I

DATA

ETX

eRe

~

MARK

BOP RECEIVER TIMING

JLSLn~

RCP

JL

MR

LrLJ4 LJ~ u#Lj-'l'

W/R=O
Address Byte

W/R_l

n

~
,

1

NOTE
----.J ~

OPEN"
not clock edge relaled

,
I

~

-.SL

~

l

I

•• ,FLAG

~

~

I

Byte

Control
B~.

Data
Byte #1

Data
Byte 112

RSA

RXACT

WiR=O
COntrol Byte

_lL -.JL

W/R:O
W/R=O
Data Byte #1 Data Byte,2

W/A=O
Dala Byte #3

~ ~ ~

.L~"---

~

s-

_ _ _ __

S-

RSCM

(..)
(0

W/R=O
Read Status

---.-JLJL
,
I
,

Ig~~..

i...-FLAG •.•

-Ll~

EEL l
LSllLfi
_J

NOTE2

~

~
~

~

L-

~

REOM

...I.

W/R=O
Data Byte #4

,--,

sLJ

~
?;1

RDA

WIR=O
Read Status

,L._

"TTT77T17TTTT7",",f., ~ FLAG •••
RSI

ULJ-'l'L-?"L~U-Y'LJLJLS

I

RXENA

SFR

LJ~

ERR,CHK, ABC,
ROA, RABIG"

r--

,

,NOTE2

.------,
I
,

I
I

NOTE 1-:1 reqUlred·bu! not done In this example

NOTE 2-11 no OPEN" to read Oala By1e 112

BOP TRANSMITTER OPERATION

Ji
n ~n ~n L...Jn l,.f,..n..s-u~ JL.j#--LflSL//ru //LrLn.. // ~
. L...J

TCP

I

MA

~ ..

TXENA

~ •..

T50M-1

I

I

I

I.

I

..~

:

I
I TSOM~O

OPENA
not clock edge felated

I
I

TBMT~

,.

TXACT~

----

I

load;
I

load
Control

Load
DalaLer:gth

Dala Byte

TEOM=l

ole 1-1

~

~

~

--.JL

Address

rL

TSO~
Note 1-Trailing edge 01 DPENA must occur alleasl one-half clock

pulse prior 10 TBMT = 1. To avoid underrun.

~;--

load

L

J-------"L

J
I

l

~

Address Byte

\-.LAG ...
Icon',oIs",

(LaStD8laByte

-r:::::;:- CRCl

r-

~I~

~

... ----i

MARK

~

AC TIMING DIAGRAMS

TCP~
TBMT

Hi----.I

RCP

\...._ __

I~o~r
RXACT

--

x==

~j--

RDA,RSA ~

DPENA
W/R=1
to Transmitter

I

DPENA

'-_ __

to Receiver
Registers

"g."" ~'
TBMT

\'----

W/R=O

IJOO':1

~

RDA'RSA~

TCP
RXENAJ
TSO

~300ns,min

Resets: RDP-RDA, RSA,
RXACT, receiver
into search
mode (for FLAG)

TXACT

Note: Unless otherwise specified all times are maximum.

Data Port Timing

READ FROM USYNR/T

WRITE TO USYNR/T

140

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range ...............................................................O°C to + 70°C
Storage Temperature Range ............................................................... -55°C to + 150°C
Lead Temperature (soldering, 10 sec.) ............................................................... +325°C
Positive Voltage on any Pin, with respect to ground ..................................................... +18.0V
Negative Voltage on any Pin, with respect to ground ..................................................... -0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation 01 the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies
exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on and off.
In addition, voltage transients on the AC power line may appear on the DC output. For example, the
bench power supply programmed to deliver + 12 volts may have large voltage transients when the
AC power is switched on and off. If this possibility exists it is suggested that a clamp circuit be used.
ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C, Vce= +5V±5%, Voo= + 12V ±5%, unless otherwise noted)
Parameter

Min.

D.C. Characteristics
INPUT VOLTAGE LEVELS
Low Level, V,L
High Level, V,H
OUTPUT VOLTAGE LEVELS
Low Level, VOL
High Level, VOH
INPUT LEAKAGE
Data Bus
All others
INPUT CAPACITANCE
Data Bus, C,N
Address Bus, C,N
Clock, C,N
All other, C,N
POWER SUPPLY CURRENT
Icc

Typ.

2.0

Unit

0.8
Vee

V
V

0.4

V

IOL=1.6ma
IOH=40/La

50.0

/La
/La

0",;V,N",;5v, DPENA=O orW/R=1
V'N=+5v

2.4
5.0

Comments

pf
pf
pf
pf
70
90

100

A.C. Characteristics
CLOCK-RCP, TCP
frequency
PWH
PWL
tr, tf
DPENA, TWOPENA
Set-up Time, TAS
ByteOp, W/R
A2, A"Ao
Hold Time, TAH
Byte Op, WIR,
A2, A" Ao
DATA BUS ACCESS, TOPA
DATA BUS DISABLE DELAY, Topo
DATA BUS SET-UP TIME, TOBS
DATA BUS HOLD TIME, TOBH
MASTER RESET, MR

Max.

ma
ma
TA=25°C

DC
325
325

1.5
10

250
0

50/Ls

0

MHz
ns
ns
ns
ns
ns
ns

150
100
0
100
350

141
----------------------

ns
ns
ns
ns
ns

I

Receiver Data

and
Receiver Status
Access Sequence
Preferred reading sequence of receiver ADA and RSA.

YES

EXIT

CCP RECEIVER OPERATION

BOP RECEIVER OPERATION
PROCESSOR LOAD
ORMA

PROTOCOL-'
XYZ·CRC 16

TEST MADE AFTER 8 RXCLK'S

TEST MADE

AFTER 6 elKS
24 RXCLK'S
(pIPELINE DELAY)

16 RXCLKS

DELAY

RXENA
~O?

NO

PROCESSOR MUST READ
EAA CHK BIT BEFORE
RXENA~O

YES
y,S

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

142

-----~-----------------------------------------

COM52C50
PRELIMINARY

Twinax Interface Circuit (TIC)
FEATURES

PIN CONFIGURATION

D Conforms to IBM 5250 System Standard
Do

D Operates at 1Mbps Data Rate

0,
0,
0,
0,

D Transmits and Receives Manchester II Encoded Data
D On Chip Parity Generation and Checking

05
06

D Programmable Interframe Zero Bit Insertion
D Handles Multi Byte and Single Byte Transfers
D Multiple Address Select Register Allows for Up to 7

0,
RO
WR
INT,
INT,
RST
GNO

Mode Address Emulation

D Master Mode Permits Message Initiation

28 J
27 J
26
4
25
24 J
23
22 ]
21 ]
20 ]
19 ]
10
18 ]
g11
12
17 ]
13
16 ]
15
14
L -_ _ _ _
- l]

Vee
TX
OTX
TXEN
RX
NIC

CS
A,
A,
Ao
ROY
CLKOUT
XTAL,
XTAL,

PACKAGE: 28-pin DIP

D Internal/External Loopback Capability for Self Test
Diagnostics

z

~ ~ ~I~ ~:t ~

D Low Power Cmos
D 28 Pin Plastic Dual In Line and Chip Carrier Packages

25242322212019
18
17
16
15
14
13
12

OTX
TX
VCC
Do

D Open Drain Output on Interrupt Pins
D On Board Predistortion Circuitry

0,
0,
0,

D On Board Crystal Oscillator (8M Hz) Simplifies Clock
Generation

2
4

READY
CLKOU
XTAL2
XTAL1
GNO
RESET
INT2

567891011

D TTL Compatible Inputs and Output

C\ ~ ~ bl@I~I~

D Single + 5v Supply

PACKAGE: 28-pin PLCC
Pin configuration subject to change, contact factory for details.

GENERAL DESCRIPTION
The COM52C50 is a CMOS device that performs the communications interface to the IBM 5250 TWINAXIAL bus. It
interfaces to a general purpose microprocessor on one side
and to the IBM 5250 TWINAXIAL bus on the other side. The
COM52C50 handles the parallel to serial and serial to parallel conversion of data to and from the TWINAXIAL bus
and the encoding and decoding of data in Manchester II for-

mat. The COM52C50 consists of a RECEIVE BLOCK, a
TRANSMIT BLOCK, and CONTROL circuitry. The receive
and transmit sections of the COM52C50 are separate and
may be used independent of one another. The COM52C50
generates and detects the bit sync, parity, and the fill zero
bit patterns according to the IBM 5250 standard.

143
--~------------

..

~---------------------

INTERRUPT
CONTROL

COM52C50 INTERNAL BLOCK DIAGRAM

DATA
BUS

A

DO-D7
r

1

ADDRESS
BUS

I

.II DECODE

AO-A1
WR
RD

TWINAX
INTERFACE
CHIP

TX

RX
INT2
XTAL1

RESET

XTAL2

TWINAXIAL
CABLE

~
2

COM52C50

INT1
I

rS

TXD
CS

.
INTERRUPT
REQUEST

TX
ENABLE

~

(

-

kJ

~D~
8MHZ

SYSTEM
RESET

TYPICAL COM52C50 INTERFACE
1I1'r"~I,...t:'1>J1r:'T~~' IIC~

Circuit diagrams utilizing SMC products are included as a means of illustrating typic<;tl semiconductor applications; can·
sequently complete information sufficient for construction purposes is not necessarily given. The information has been
=;jii~iiiiiii.i. carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Fur~
thermore, such information does not convey to the purchaser of the semiconductor devices described any license under
the patent rights of SMC or others. SMC reserves the right to make changes at any time in order to improve design and
supply the best product possible.

144

COM 7210

Intelligent GPIB Interface Controller
FEATURES

PIN CONFIGURATION

o All Functional Interface Capability Meeting IEEE

o
o
o
o
o
o
o
o
o

Standard 488-1978
-SH1 (Source Handshake)
-AH1 (Acceptor Handshake)
- T5 or TE5 (Talker or Extended Talker)
-L3 or LE3 (Listener or Extended Listener)
-SR1 (Service Request)
-RL 1 (Remote Local)
-PP1 or PP2 (Parallei Poll) (Remote or Local
Configuration)
-DC1 (Device Clear)
-DT1 (Device Trigger)
-C1-5 ((Controller) (All Functions))
Programmable Data Transfer Rate
16 MPU Accessible Registers-8 Read/8 Write
2 Address Registers
-Detection of MTA, MLA, MSA (My Talk/Listen/
Secondary Address)
-2 Device Addresses
EOS Message Automatic Detection
Command (IEEE Standard 488-78) Automatic
Processing and Undefined Command Read Capability
DMA Capability
Programmable Bus Transceiver I/O Specification
(Works with TI.IMotorola/lntel)
1 to 8 MHz Clock Range
TTL Compatible

~

T/R 1
T/R2
CLOCK
RESET

T/R3
DMAREO
DMAACK

3
4
5
6

CS
RD
WR
INT
DO
D1
D2
D3
D4
D5
D6
D7
GND

9
10
11
12
13 (
14 [
15 (
16 [
17 [
18 (
19 (
20 [

D

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

Vee

!:Of
NDAC
NRFD
DAV

Df08
DI07

Df08
5lO5

iJI04
DlO3

Di02
BlO1
SRQ

i\TIi!
REN
IFC
RS2
RS1
RSO

PACKAGE: 4D-pin D.I.P.

o COPLAMOS®n-Channel Silicon Gate Technology
o + 5V Single Power Supply
o 40-Pin DIP
o 8080/85/86 Compatible

GENERAL DESCRIPTION
The COM7210 TLC is an intelligent GPIB Interface Controller designed to meet all of the functional requirements
for Talkers, Listeners, and Controllers as specified by the
IEEE Standard 488-1978. Connected between a processor
bus and the GPIB, the TLC provides high level manage-

ment of the GPIB to unburden the processor and to simplify
both hardware and software design. Fully compatible with
most processor architectures, Bus Driver/Receivers are the
only additional components required to implement any type
of GPIB interface.

145

----~.-.-.-.-------.

REGISTERS

DiOa-DiOf
DATA IN

07 ..... 00

CS

MESSAGE
DECODER

COMMAND PASS
THROUGH

RS2 ..... RSO

AD

BYTE OUT
INTERFACE
FUNCTIONS

WA
ADDRESS STATUS
DMAREQ

SH I

DMAACK

AH I
ADDRESS MODE
TslTES

ADDRESS all

L3/LE3

GPIB CONTROL

SA I
END OF STRING

ALI

PP1/PP2

INT

DC I

DT I
SERIAL POLL

CI

C2
PARALLEL POLL

C3
AUX.IAIlIBI/IEI
C4

CLOCK

C6

INTERNAL
COUNTER

AUX. COMMAND
DECODER
RESET

BLOCK DIAGRAM

146

T/R 3-T/R 1

----""----------------------

DESCRIPTION OF PIN FUNCTIONS
1/0

PIN
1

T/R1

0

2

T/R2

0

3

CLK

I

SYMBOL

4

RST

5

T/R3

I
0

6

DMAREQ

0

7

DMAACK

I

8

CS

I

9

RD

I

10

WR

I

11

~

0

INT

12-19
20
21-23

DO-7
GND
RSO-2

110

24
25

IFC
REN

110
110

26

ATN

110

27
28-35

SRQ
D101-8

110
110

36
37
38

DAV
NRFD
NDAC

110
110
110

39

EOI

110

40

Vee

I

DESCRIPTION
Transmit/Receive Control-Input/Output Control Signal for the GPIB
Bus Transceivers.
Transmit/Receive Control-The functions of T/R2, T/R3 are determined
by the values of TRM1, TRMO of the address mode register.
Clock-(1-8 MHz) Reference Clock for generating the state change
prohibit times T1, T6, T7, T9 specified in IEEE Standard 488-1978.
Reset-Resets 7210 to an idle state when high (active high).
Transmit/Receive Control-Function determined by TRM1 and TRMO of
address mode register (See T/R2).
DMA Request-721 0 requests data transfer to the computer system,
becomes low on input of DMA acknowledge signal DACK.
DMA Acknowledge-(Active Low) Signal connects the computer system
data bus to the data register of the 7210.
Chip Select-(Active Low) Enables access to the register selected by
RSO-2 (read or write operation).
Read-(Active Low) Places contents of read register specified by
RSO-2-on DO-7 (Computer Bus).
Write-(Active Low) writes data on DO-7 into the write register specified
by RSO-2.
Interrupt Request-(Active High/Low) Becomes active due to any 1 of 13
internal interrupt factors (unmasked) active state software configurable,
active high on chip reset.
Data Bus-8-bit bidirectional data bus, for interface to computer s~stem.
Ground.
Register Select-These lines select one of eight read (write) registers
during a read (write) operation.
Interface Clear-Control line used for clearing the interface functions.
Remote Enable-Control line used to select remote or local control of
the devices.
Attention-Control line which indicates whether data on DID lines is an
interface message or device dependent message.
Service Request-Control line used to request the controller for service.
Data Input/Output-8-bit bidirectional bus for transfer of message on
the GPIB.
Data Valid-Handshake line indicating that data on DID lines is valid.
Ready-'or Data-Handshake line indicating that device is ready for data.
Data Accepted-Handshake line indicating completion of message
reception.
End or Identify-Control line used to indicate the end of multiple byte
transfer sequence or to execute a parallel polling in conjunction with ATN.
+5VDC

FUNCTIONAL DESCRIPTION

Introduction
The IEEE Standard 488 describes a "Standard Digital
Interface for Programmable Instrumentation" which, since
its introduction in 1975, has become the most popular means
of interconnecting instruments and controllers in laboratory, automatic test and even industrial applications. Refined
over several years, the 488-1978 Standard, also known as
the General Purpose Interface Bus (GPIB), is a highly
sophisticated standard providing a high degree of flexibility
to meet virtually most all instrumentation requirements. The
COM7210 TLC implements all of the functions that are
required to interface to the GPIB. While it is beyond the
scope of this document to provide a complete explanation
of the IEEE 488 Standard, a basic description follows:
The GPIB interconnects up to 15 devices over a common
set of data control lines. Three types of devices are defined
by the standard: Talkers, Listeners, and Controllers,
although some devices may combine functions such as
TalkerlListener or Talker/Controlier.

Data on the GPIB is transferred in a bit parallel, byte serial
fashion over 8 Data 1/0 lines (0101-0108). A 3 wire handshake is used to ensure synchronization of transmission and
reception. In order to permit more than one device to receive
data at the same time, these control lines are "Open Collector" so that the slowest device controls the data rate. A
number of other control lines perform a variety of functions
such as device addressing, interrupt generation, etc.
The COM7210 TLC implements all functional aspects of
Talker, Listener and Controller functions as defined by the
488-1978 Standard, and on a single chip.
The COM 721 0 TLC is an intelligent controller designed to
provide high level protocol management of the GPIB, freeing
the host processor for other tasks. Control of the TLC is
accomplished via 16 internal registers. Data may be transferred either under program control or via DMA using the
TLC's DMA control facilities to further reduce processor

147
---

"-----"-""---------------------

overhead. The processor interface of the TLC is general in
nature and may be readily interfaced to most processor
lines.
In addition to providing aU control and data lines necessary
for a complete GPIB implementation, the TLC also provides a unique set of bus transceiver controls permitting the
REGISTER NAME

use of a variety of different transceiver configurations for
maximum flexibility.

Internal Registers
The TLC has 16 registers, 8 of which are read and 8 write.
SPECIFICATION

ADDRESSING
RRRWRC
S S S R 0 S
2 1 0

Data In (OR)

o

Interrupt Status 1 (1 R)

0 0 1 1 0 0

0 0 1 0 0

I 017
I CPT
I INT
I S8
I CIC
I CPT?

Interrupt Status 2 (2R)

0 1 0 1 0 0

Serial Poll Status (3R)

0 1 1 1 0 0

Address Status (4R)

1

Command Pass Through (5R)

1 0 1 1 0 0

Address 0 (SR)
Address 1 (7R)

1 1 0 1 0 0 1 X
1 1 1 1 o 0
EOI

8yte Out (OW)

0 0 0 0 1 0

Interrupt Mask 1 (IW)

0 0 1 0 1 0

Interrupt Mask 2 (2W)

o

Serial Poll Mode (3W)
Address Mode (4W)

o

0 1 0 0

I

015

APT

OET 1 END
LOK 1 REM

SROI

I
I

I

I

DIS

I

014

CO

ATN

SPMS

I LPAS

TPAS

CPTS

CPT5

CPT4

CPT3

S4

S5

I 012 I 011
I ERR I DO
I LOKC 1 REMC
I S3 I S2
I LA TA

SI 1
MJMN 1

I CPT2

CPTI

CPTO 1

I

OLO

A05-0

A04-0

A03-0

A02-0

A01-0 1

0L1

A05-1

A04-1

A03-1

A02-1

A01-l

I

805

804
END

0

SROI

OMAO

0 1 1 0 1 0

S8

rsv

SS

1 0 0 0 1 0

ton

Ion

TRMI

TRMO

Auxiliary Mode (5W)

1 0 1 0 1 0

CNT2

CNTI

CNTO

Address 0/1 (SW)

1 1 0 0 1 0

ARS

OT

OL

A05

End of String (7W)

1 1 1

EC7

ECS

EC5

EC4

013

012

011

I

803

802

DEC

ERR

OMAI 1 CO
S4
S5

DIS

I

015

014

COM21 COMI

COMO

I
I

A03 1 A02
EC2
ECI

AOI

1

ECO

I

A04

I

EC3

010

Interrupt Registers
The interrupt registers are composed of interrupt status bits,
interrupt mask bits, and some other noninterrupt related bits.
READ
APT

OET

END

DEC

INTERRUPT
STATUS 2 (2R)

INT

SROI

LOK

REM

CO

ERR

DO

01

I LOKC I REMC I AOSC

1

WRITE
INTERRUPT
MASK 1 (IW)

CPT

APT

INTERRUPT
MASK 2 (2W)

0

SROI

END

DEC

I OMAO I OMAI

CO

OET

148

ERR

01

COM41 COM3

0

Holds information written into it for transfer to the GPIB

CPT

800

AOMO

S3

0

1"'--::8-=0'::'7-'-1-=8-=0C':'s--r1-=8:-::0=-=5--r-:8:"':0:":4--"--:8::-:0::-:3-'--'8=-=0::-:2:--1'--:::-80=-1:--'--=-80=-O::-"l

INTERRUPT
STATUS 1 (IR).

I

DO

I S2
I AOMI

I
I

Holds data sent from the GPIB to the computer
BYTE OUT (OW)

801

AOSC

Data Registers

I

I

I

LOKC 1 REMC

The data registers are used for data and command transfers between the GPIB and the microcomputer system.
017

1
AOSC 1

I

OET

I

1

01

OTO

APT

DATA IN (OR)

010

OTI
80S

1 0

DEC

SS

807

o

013

PEND

CPT

1 0 0 1 0

I

DO

01

I LOKC I REMC I AOSC

1

SI

I

I

--~--

~~~~~~~~~~~~~~~--~~~~~~~~~-

Interrupt Status Bits
INT
CPT
APT
DET
END
DEC
ERR
DO
01
SRQI
LOKC
REMC
ADSC
CO

There are thirteen factors which can generate an interrupt from the COM 721 0, each with their own status bit and
mask bit.

OR of All Unmasked Interrupt Status Bits
Command Pass Through
Address Pass Through
Device Trigger
End (END or EOS Message Received)
Device Clear
Error
Data Out
Data In
Service Request Input
Lockout Change
Remote Change
Address Status Change
Command Output

The interrupt status bits are always set to one if the interrupt
condition is met. The interrupt mask bits decide whether the
INT bit and the interrupt pin will be active for that condition.

Noninterrupt Related Bits
LOK
REM
DMAO
DMAI

Lockout
Remote/Local
EnablelDisable DMA Out
EnablelDisable DMA In

Serial Poll Registers
READ
SERIAL POLL
STATUS (3R).

S8

I PEND I

S6

S4

S3

S1

SO

S4

S3

S2

S1

TPAS

LA

TA

I MJMN I

0

0

S5

WRITE
SERIAL POLL
MODE (3W)

S8

rsv

S6

S5

The Serial Poll Mode register holds the STB (status byte:
S8, S6-S1) sent over the GPIB and the local message rsv
(request service). The Serial Poll Mode register may be read
through the Serial Poll Status register. The PEND is set by
rsv = 1, and cleared by NPRS' rsv = 1 (NPRS = Negative
Poll Response State).

Address Mode/Status Registers
ADDRESS STATUS (4R)

CIC

ATN

I SPMS I LPAS

ADDRESS MODE (4W)

ton

Ion

I TRM1 I TRMO I

The Address Mode register selects the address mode of
the device and also sets the mode for T/R3 and T/R2 the
transceiver control lines.
The functions of T/R2, T/R3 terminals (2 and 5) are determined as below by the TRM 1, TRMO values of the address
mode register.
T/R2
EOIOE
CIC
CIC
CIC
EOIOE = TACS

T/R3
TRIG
TRIG
EOIOE
PE

TRM1
0
0
1
1

I ADM1 I ADMO I

CIC = CIDS + CADS
This denotes if the controller interface function is active or
not.
When "1": ATN = output, SRO = input
When "0": ATN = input, SRO = output

TRMO
0
1
0
1

PE = CIC + PPAS
This indicates the type of bus driver connected to 0108 to
0101 and DAV lines.
When "1": 3 state type
When "0": Open collector type
TRIG: When DTAS state is initiated or when a trigger auxiliary command is issued, a high pulse is generated.

+ SPAS + CIC· CSBS

Upon RESET, TRMO and TRM1 become "0" (TRMO =
TRM1 = 0) and local message port is provided, so that T/
R2 and T/R3 both become "LOW:'

This denotes the input/output of EOI terminal.
When "1": Output
When "0": Input

149

I

Address Modes
ton
1

Ion
0

ADM1
0

ADMD
0

0

1

0

0

0

0

0

1

0

0

1

0

0

0

1

1

ADDRESS
MODE
Talk only
mode
Listen only
mode
Address mode 1
@
Address mode 2

@

Address mode 3
@
Combinations other than above indicated Prohibited.

Notes:

@

CONTENTS OF
ADDRESS (D)
REGISTER

CONTENTS OF
ADDRESS (1)
REGISTER

Address Identification Not Necessary
(No controller on the GPIB)
Not Used
Major talk address or
Major listen address
Primary address
(talk or listen)
Primary address (major
talk or major listen)

@
@

-Either MTA or MLA reception is indicated by coincidence of either address with the received address.
Interface function T or L.

Minor talk address or
Minor listen address
Secondary address
(talk or listen)
Primary address (minor
talk or minor listen)

-Address register 0 = primary, Address register 1 =
secondary, interface function TE or LE.
-CPU must read secondary address via Command
Pass Through Register interface function (TE or LE).

Address Status Bits
ATN
LPAS
TPAS
CIC
LA

Data Transfer Cycle (device in CSBS)
Listener Primary Addressed State
Talker Primary Addressed State
Controller Active
Listener Addressed

TA
MJMN
SPMS

Talker Addressed
Sets minor TIL address Reset = Major TIL
address
Serial Poll Mode State

Address Registers
ADDRESS 0 (6R)

X

DTO

DLO

ADDRESS 1 (7R)

EOI

DT1

DL1

ADDRESS 0/1 (6W)

ARS

DT

DL

I AD5-0 I AD4-0 I AD3-0 I AD2-0 I AD1-0 I
I AD5-1 I AD4-1 I AD3-1 I AD2-1 I AD1-1 I
I AD5 I AD4 I AD3 I AD2 I AD1 I

The TLC is able to automatically detect two types of
addresses which are held in address registers 0 and 1. The
addressing modes are outlined below.

Address settings are made by writing into the address 0/1
register. The function of each bit is described below.

Address 0/1 Register Bit Selections
ARS
DT
DL

-Selects which address register, 0 or 1
-Permits or Prohibits address to be detected
as Talk
-Permits or Prohibits address to be detected
as Listen

AD5-AD1 -Device address value
EOI
-Holds the value of EOI line when data is
received

Command Pass Through Register
COMMAND PASS
THROUGH (5R)

I CPT7 I CPT6 I CPT5 I CPT4 I CPT3 I CPT2 I

The CPT register is used such that the CPU may read the
DIO lines in the cases of undefined command, secondary

CP1

I CPTO I

address, or parallel poll response.

End of String Register
ENDOF
STRING (7W)

I

EC7

I

EC6

I

EC5

I

EC4

This register holds either a 7- or a-bit EOS message byte
used in the GPIB system to detect the end of a data block.

EC3

I

EC2

I

EC1

I

ECO

I

Aux Mode Register A controls the specific use ofthis register.

Auxiliary Mode Register
AUXILIARY
MODE (5W)

I CNT2 I CNT1 I CNTO I COM4 I COM3 I COM2 I COM1 I COMO I
150

This is a mUltipurpose register. A write to this register generates one of the following operations according to the values of the CNT bits.
CNT

BIT
NAME

COM

A,

0
1

Prohibit
Permit

A3

0
1

Prohibit
Permit

A4

0
1

7bitEOS
8bit EOS

2 1 0 4 3 2 1 0
0 0 0
0 0 1
0 1 1
1 0 0
1 0 1
1 1 0

OPERATION
Issues an auxiliary command
C4 C3 C, C, Co specified by C4to Co.
The reference clock frequency is
o F3 F, F, Fo specified and T" T" T" T, are
determined as a result.
Makes write operation to the parallel
U S P3 P, P,
poll register.
Makes write operation to the aux.
A, A3 A, A, Ao (A) register.
Makes write operation to the aux.
B4 B3 B, B, Bo (B) register.
OOOE,Eo Makes write operation to the aux.
(E) register.

o0

Auxiliary Commands
COM
43210
00000

iepon

-

00010

crst

-

00011
00100
00101

rrfd
trig
rtl

-

00110
00111

seoi
nvid

-

01111

vid

-

OXOOl
10000
10001

sppf
gts
tca

-

10010
11010

tcs
tcse

-

10011
11011

Itn
Itnc

-

11100
11101
lXll0
1 Xlll
10100

lun
epp
sifc
sren
dsc

-

Internal Counter

Auxiliary B Register

Listen
Listen with Continuous
Mode
Local Unlisten
Execute Parallel Poll
Set/Reset IFC
Set/Reset REN
Disable System Control

0 0 1 0 F3 F2 F, Fo

The internal counter generates the state change prohibit
times (T" T 6 , T 7 , Tg) specified in the IEEE std 488-1978 with
reference to the clock frequency.

BIT
NAME

0
1
0
1

1
0

Permit
Prohibit

B,

1
0

Permit
Prohibit

1

T,
(high-speed)
T,
(low-speed)
INT
INT

B3

0
1
0

ist = SROS
1
B4
0

1 0 1 B4 B3 B2 B, Bo

ist = Parallel
Poll Flag

Auxiliary E Register

FUNCTION
Permits (prohibits) the detection
of undefined command. In other
words, it permits (prohibits)
the setting of the CPT bit on
reception of an undefined
command.
Permits (prohibits) the
transmission of the END
message when in serial poll
active state (SPAS).
T, (high speed) as T, of
handshake after transmission of
2nd byte following data
transmission.

Specifies the active level of
INTpin.
SROS indicates the value of ist
level local message (the value of
the parallel poll flag is ignored).
SROS = 1 ... ist = 1.
SROS = O... ist = O.
The value of the parallel poll flag
is taken as the ist local message.

1 1 0 0 0 0 E, Eo

This register controls the Data Acceptance Modes of the
TLC.
BIT

Eo
E,

FUNCTION

1
0
1
0

Enable
Disable
Enable
Disable

DAC Holdoff by initiation of DCAS
DAC Holdoff by initiation of DTAS

Parallel Poll Register
The Parallel Poll Register defines the parallel poll response
of the COM 721 O.

o

I U I S I P3 I P, I P, I

I ~ECIFYING

STATUS BIT
OUTPUT LINE (DIOl TO D108)

2 bits control the GPIB data receiving modes of the 7210
and 3 bits control how the EOS message is used.

Ao

Bo

B,

Auxiliary A Register 1 0 0 A4 A3 A2 A, Ao
Of the 5 bits that may be specified as part of its access word,

A,
0
0
1
1

Makes the 8 bits/7 bits of EOS
register the valid EOS message.

The Auxiliary B Register is much like the A Register in that
it controls the special operating features of the device.

0 C 4 C 3 C2 C, Co

Immediate Execute ponGenerate local pan
Message
Chip Reset-Same as
External Reset
Release RFD
Trigger
Return to Local Message
Generation
Send EOI Message
Non Valid (OSA reception)Release DAC Holdoff
Valid (MSA reception, CPT,
DEC, DET)-Release DAC
Holdoff
Set/Reset Parallel Poll Flag
Go To Standby
Take Control
Asynchronously
Take Control Synchronously
Take Control Synchronously
on End

FUNCTION
Permits (prohibits) the setting of
the END bit by reception of the
EOS message.
Permits (prohibits) automatic
transmission of END message
simultaneously with the
transmission of EOS message
TACS.

SPECIFYING STATUS BIT
POLARITY
S = 1: IN PHASE
S = 0: REVERSE PHASE

DATA RECEIVING MODE
Normal Handshake Mode
RFD Holdoff on all Data Modes
RFD Holdoff on End Mode
Continuous Mode

{ U = 1: NO RESPONSE TO PARALLEL POLL
U = 0: RESPONSE TO PARALLEL POLL

151

I

~

I

A18-8

1
~

~

8085

(J1
t\)

:JJ
rS'

6
0

nnil

:JJI:EI:JJ
O:O~5

~ ~

INT 6

RST 6.5

en

~

COM7210
RST 5.5 tJDMAREQ

I

::! ~Ii
.J» o:JJI:EI»:JJ
~I0:IJ~~ s:
m
00
~ :JJ

TIMER OUT
DMAACK

T/R3_1
RESr IN

1

v

"H"

~v

»

....

»0

'?

....

OJ

00

-:JJI

m

DEVICE CONTROL

OJ

MINIMUM 8085 SYSTEM
WITH COM7210

C'l!'
ml:

:Em"';>;

S:I

~

CE\-ot-"H"

8355

2

8155

1

-I » :JJ n

~CJ0r-mr-

IOR\--"H"
PA7-O, PB7-O
~

SWITCHES

I

J-

DISPLAY

--------------------------------

COM7210

GPIB

MC344SAX4

NOs
Q!Q:z.

~
01 5

r

010 4
01°2
010 1

T/R3 (EOIOE)

roT

BUS A
BUS B
BUSC
BUS 0

S/RA.O

PEA·O

DATA A
DATA B
OATAC
DATA 0
~ S/RA·O

5iO'3

T/R1

DATA A
DATA B
OATAC
DATA 0

OIOS
010 7
OIOS
010 5

BUS A
BUS B
BUSC
BUS 0

01°4
010 3
010 2
010 1

PEA·O

W-ri>SIR A
DATA A
S/RB
DATA B
I - - S/Rc
OATAC
' - - - - s/Ro
DATA 0

BUS A

EOI

~

DAii
NJmi
NOAC

BUS B

OAV

BUSC

NRFO

BUS 0

NOAC

PEA·O

T/R2 (CIC)

mm
A'rlii
REN
IFC

r-t>-

S/RA

DATA A
L - - S/RB
OATAB
r S/Rc
OATAC
~ SiR 0
DATA 0

BUS A

ATN

BUSC

REN

BUS 0
PEA·O

IFC

TT

.. H.... L ..

Note:

"L"

In this example, high-speed data transfer cannot be made since the bus
transceiver is of the open collector type (Set B, = 0).

OIOS

08

5m7
Di06
Di05
5i04

07
Os
05
04

010 3
010 2
Dl01

02
01

T/R3 (PE)

PE

COM7210

03

SRO
ATN

m
DAii

BSt---~

B7t--BSt--B5t--SN751S0 B 4 t - - B3t--B2t--91t--TE

,
j

T/R1

T/R2 (CIC)

~

>GPIB

TE
DC
SRO
ATN
EOI SN751S1
OAV
NRFO
NOAC

t--t--t---

iFC

IFC

t--t--t--t---

REN

REN

t---_

NRFO
NOAC

Note:

SRO

BUS B

In the case of low-speed data transfer (B, = 0), the TIR, pin can be used as a
TRIG output. The PE input of SN75160 should be cleared to "0."

MINIMUM 8085 SYSTEM
WITH COM7210 (CO NT.)

153

I

ELECTRICAL CHARACTERISTICS
MAXIMUM GUARANTEED RATINGS (T, = 25'C)
PARAMETER

SYMBOL

Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature

Vee
V,
Va
Topi
T"

DC CHARACTERISTICS (T.
PARAMETER
Input Low Voltage
Input High Voltage
Low Level
Output Voltage

MIN

UNIT
V
V
V
'C
'C

± 10%)

LIMITS
TYP

-0.5
+2.0

VOH1

MAX

UNIT

+0.8
Vee + 0.5

V
V

+0.45

V

10l = 2mA
(4 mA: T/R1 Pin)

V

10H = - 400 flA
(Except INT)
10H = - 400 flA

+2.4
+2.4

VOH2

TEST CONDITIONS

V
+3.5

10H

=-

= OV -

III

-10

+10

flA

V,N

10l
Icc

-10

+10
+180

flA
mA

VOUT

MAX

UNIT

10
15
20

pF
pF
pF

50 flA
Vee

= 0.45V -

Vee

= 25'C, Vee = GND = OV)

PARAMETER

CS, RS2 -

SYMBOL

= 5V

Val

High Level
Output Voltage
(INTPin)
Input Leakage
Current
Output Leakage
Current
Supply Current

Input Capacitance
Output Capacitance
1/0 Capacitance

+ 70'C, Vee

VIL
V,H

High Level
Output Voltage

CAPACITANCE (T,

= 0 to

RATINGS
-0.5 - + 7.0
-0.5 - +7.0
-0.5- +7.0
0- +70
-65- +125

SYMBOL

MIN

LIMITS
TYP

C 'N
COUT

Guo

TEST CONDITIONS
f = 1 MHz
All Pins Except Pin Under Test Tied to
ACGround

0

_ _ _i -_ _ _ _.... I - - - - tRR

-----11,.----------.
~----tRv

-----I

D7-0

\.ltAKD

DMAREQ

t:::~K'Q==:t~__________________
TIMING DIAGRAM

154

AC CHARACTERISTICS, (T. = 0 to 70°C, Vee = 5V'± 10%)
LIMITS
PARAMETER
EOI j --+ DIO
EOI j --+ T/R11
EOll--+ T/RI!
ATN j --+NDAC j
ATNj --+ T/Rl j
ATN j --+ T/R2 j
DAV j --+ DMAREQ
DAV j --+ NFRD j
DAV j --+ NDAC 1
DAV 1--+ NDAC j
DAV 1--+ DRFD 1

SYMBOL

MIN

MAX
250
155
200
155
155
200
600
350
650
350
350

t EODI

tEOT11
tEOT12
tATNO
tATT1

tATT2
tOVAQ
tOVNR1

tovNDl
tOVND2
tOVNR2

UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

RD j --+ NRFD 1

tANA

500

ns

NDAC 1 --+ DMAREQ 1

tNDRQ

400

ns

NDAC 1--+ DAV 1

tNDDV

350

ns

WR 1--+010

twO!

250

ns

NRFD 1--+ DAV j

tNRDV

350

ns

WR 1--+ DAV j

tWDv

830

ns

TRIG
Pulse Width

tTR1G

Address Setup to RD

tAR

Address Hold from RD
RD Pulse Width
Data Delay from Address
Data Delay from RD j
Output Float Delay from RD 1
RD Recovery Time
Address Setup to WR
Address Hold from WR
WR Pulse Width
Data Setup to WR
Data Hold from WR
WR Recovery Time
DMAREQ j Delay from DMAACK
Data Delay from DMAACK

tRA
tRR
tAD
tRO
to,
tRV
tAW
tWA
tww
tow
two
tRV

CS, RS2 - 0

+ tSYNC
50

ns

85
0
0
170

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

250
150
80

0
250
0
0
170
150
0
250

130
200

tAKRQ

tAKD

=t=,AW=lt_tww
t=tow

----------------~X

TIMING DIAGRAM

155

RSO- RS2
CS

3E_tWA

'-------

07 - 0

CONDITIONS
PPSS --+ PPAS, ATN = True
PPSS --+ PPAS, ATN = True
PPAS --+ PPSS, ATN = False
AIDS --+ ANRS, LIDS
TACS + SPAS --+ TADS, CIDS
TACS + SPAS --+ TAOS, CIDS
ACRS --+ ACDS, LACS
ACRS--+ACDS
ACRS --+ ACDS --+ AWNS
AWNS-·ANRS
AWNS --+ ANRS --+ ACRS
ANRS--+ACRS
LACS, 01 reg, selected
STRS --+ SWNS --+ SGNS,
TACS
STRS --+ SWNS --+ SGNS
SGNS --+ SDYS, BO
reg. selected
SDYS --+ STRS, T, = True
SGNS --+ SDYS --+ STRS
BO reg. selected, RFD = True
N, = fc = 8 MHz,
T, (High Speed)

=:Jl(______

two:

tRV

.}-

)(~.~~~~~~~~~===

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully Checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

156

COM78808
PRELIMINARY

Eight-channel Universal
Asynchronous Receiver/Transmitter
Octal UART
PIN CONFIGURATION

FEATURES

D Eight independent full duplex serial data lines
D Programmable baud rates individually selectable for
each line's transmitter/receiver (50 to 19,200 baud)

D Summary registers that allow a single read to detect a

VSS2

63

data set change or to determine the cause of an interrupt on any line

42

Dffi

63
64

65

D Triple buffers for each receiver
D Device scanner mechanism that reports interrupt
request due transmitter/receiver interrupts

i5SR'6

67

Tx06

68

TxDS

DSRS

D Independently programmable lines for interrupt-driven

oe05
Rx05

operation

TxD3

r---------l
I
I
I
I
I
I
78808
I CAVITY DOWN
I
CONNECTIONS
I
I
I
I
I
I
I
I
I
I
IL _ _ _ _ _ _ _ _ _ .JI

D Modem status change detection for Data Set Ready
(DSR) and Data Carrier Detect (DCD) signals

40

DCD3

39

RxD3

37

DCo2
6SR2

R~D7

36
35

hD2

34

hOI

33

ITSRi

32

6CDi

31

RxDl

30

RxOO

29

6C5O

28

DSRO

hOO

D Programmable interrupts for modem status changes
D Synchronizes critical read-only registers
PACKAGE: 68-pin Cerdip quadpack

GENERAL DESCRIPTION
The COM78808 Eight-channel Asynchronous Receiver/ basic operations necessary for simultaneous reception and
Transmitter (Octal UART) is a VLSI device for new gener- transmission of asynchronous messages on eight indeations of asynchronous serial communication designs and pendent lines. Figure 1 is a functional block diagram of the
for microcomputer systems. This 68-pin device performs the COM78808 Octal UART.

157

TxOQ

RxDO
DSRO
DCDO
INTERRUPT
SUMMARY
REGISTER

TxDl

RxDl
DSR 1
DCDl

TxD2
RxD2
DSR2
DCD2
TxD3
RxD3
DSR3
DCD3

DATA SET
CHANGE
SUMMARY
REG ISTE R

TxD4
RxD4
DSR4
DCD4

TxD5
RxD5
DSRS

DCD5
Tx06
RxD6
DSR6

DATA BUS

1-----11---

DCD6
TxD7

ClK

RxD7

CONTROL BUS

DSR7
' -_ _ _- - ' , - - - - - - DC07

MRESET

FIGURE 1: COM78808 OCTAL UART FUNCTIONAL BLOCK DIAGRAM
TABLE 1-COM78808 PIN AND SIGNAL SUMMARY
Pin

Signal

Input/Output

Definition/Function

10-13,22-25

Dl<7:0>

input/output

Data lines <7:0>-Receives and transmits the parallel
data.

50-52,54-56

ADD<5:0>

input

Address<5:0>-Selects the internal registers in the Octal
UART.

17

CS

input

Chip select-Activates the Octal UART to receive and transmit data over the Dl<7:0> lines.

21,53

DS1,DS2

input

Data strobe 1 and 2-Receives timing information for data
transfers. The DS1 and DS2 inputs must be connected
together.

18

WR

input

Write-Specifies direction of data transfer on the Dl <7:0>
lines.

14

RDY

output

Ready-Indicates when the Octal UART is ready to participate in data transfer cycles.

15

RESET

input

Reset-Initializes the internal logic.

57

MRESET

input

Manufacturing reset-For manufacturing use.

58

ClK

input

Clock-Clock input for timing.

62,67,2,7,
41 ,36,33,28

DSR<7:0>

inputs

Data set ready-Monitor data set ready (DSR) signals from
modems.

63,66,3,6,
40,37,32,29

DCD<7:0>

inputs

Data set carrier detect-Monitor data set carrier detect
(DCD) signals from modems.

49

IRQ

output

Interrupt request-Requests a processor interrupt.

45-47

IRQlN<2:0>

output

Interrupt request line number-Indicates the line number of
originating interrupt request.

48

IRQTxRx

output

Interrupt request transmit/receive-Indicates whether an
interrupt request is for transmitting or receiving data.

61,68,1,8,
42,35,34,27

TxD<7:0>

outputs

Transmit data-Provides asynchronous bit-serial data output streams.

64,65,4,5,
39,38,31,30

RxD<7:0>

outputs

Receive data-Accepts asynchronous bit-serial data input
streams.

44,26,9

Voo

input

Voltage-Power supply voltage

16,59,43

Vss

input

Ground-Ground reference

158

+ 5 Vdc.

DATA AND ADDRESS
Data lines (DL<7:0»-These lines are used for the parallel transmission and reception of data between the CPU
and the Octal UART. The receivers are active when the data
strobe (051, 052) signal is asserted. The output drivers are
active only when the chip select (C5) signal is asserted, the
data strobe (051, 052) signal is asserted, and the write
(WR) signal is deasserted. The drivers will become inactive
(high-impedance) within 50 nanoseconds when one or more
of the following occurs: the ch~lect (C5) signal is deasserted, the data strobe (051,052) signal is deasserted, or
the write (WR) signal is asserted.

Address (ADD<5:0»-These lines select which Octal
UART internal register is accessible through the data I/O
lines (OL<7:0» when the data strobe (051,052) and chip
select (C5) signals are asserted. Table 2 lists the addresses
corresponding to each register. The receiver buffer and
transmitter holding @9!ster for each line have the same
address. When the (WR) signal is deasserted, the address
accesses the receiver buffer register and when asserted, it
accesses the transmitter holding register.

TABLE 2-COM78808 REGISTERS ADDRESS SELECTION
ADD Line*
<5>

<4>

<3>

<2>

<1>

<0>

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
1
1

0
0
0
0
0

0
0
0
0
0

1
1
1
1
1

0
0
0
0
0

0
0
0
0
0

1
1
1
1
1

0
0
0
0
0

0
0
0
0
0

1
1
1
1
1

1
1
1
1
1

Read/Write

Register

0
0
1
0
1

Read
Write
Read
Read/Write
Read/Write

Line 0 Receiver Buffer
Line 0 Transmitter Holding
Line 0 Status
Line 0 Mode Registers 1,2
Line 0 Command

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
Read/Write
Read/Write

Line 1 Receiver Buffer
Line 1 Transmitter Holding
Line 1 Status
Line 1 Mode Register 1,2
Line 1 Command

0
0
0
0
0

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
Read/Write
Read/Write

Line 2 Receiver Buffer
Line 2 Transmitter Holding
Line 2 Status
Line 2 Mode Register 1,2
Line 2 Command

1
1
1
1
1

0
0
0
0
0

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
Read/Write
ReadIWrite

Line 3 Receiver Buffer
Line 3 Transmitter Holding
Line 3 Status
Line 3 Mode Register 1,2
Line 3 Command

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
Read/Write
Read/Write

Line 4 Receiver Buffer
Line 4 Transmitter Holding
Line 4 Status
Line 4 Mode Register 1 ,2
Line 4 Command

1
1
1
1
1

0
0
0
0

1
1
1
1
1

0
0
0
0
0

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
Read/Write
Read/Write

Line 5 Receiver Buffer
Line 5 Transmitter Holding'
Line 5 Status
Line 5 Mode Register 1,2
Line 5 Command

1
1
1
1
1

1
1
1
1
1

0
0
0
0
0

0
0
0
0
0

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
Read
Read/Write

Line 6 Receiver Buffer
Line 6 Transmitter Holding
Line 6 Status
Line 6 Mode Register 1 ,2
Line 6 Command

1
1
1
1
1

1
1
1
1
1

1
1
1
1
1

0
0
0
0
0

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
Read/Write
Read/Write

Line 7 Receiver Buffer
Line 7 Transmitter Holding
Line 7 Status
Line 7 Mode Register 1 ,2
Line 7 Command

X
X

X
X

X
X

1
1

0
0

0
1

Read
Read

Interrupt Summary
Data Set Change Summary

b

*X = Either.O or 1.

BUS TRANSACTION CONTROL
Chip select (C5)-This signal is asserted to permit data
transfers through the OL <7:0> lines to or from the internal
~ters. Data transfer is controlled by the data strobe (051 ,
052) signal and write (WR) signal.
Data strobe (D51, D52)- The data strobe inputs (051 and
052) must be connected together. This input receives tim-

ing information for data transfers. During a write cycle, the
CPU asserts the data strobe signal when valid output data
is available and deasserts the data strobe signal before the
data is removed. During a read cycle, the CPU asserts the
data strobe signal and the Octal UART trj3.nsfers the valid
data. When the data strobe signal is deasserted, the
OL <7:0> lines become a high impedance.

159

Write (WR)-The write (WR) signal specifies the direction
of data transfer on the DL<7:0> Rins by controlling the
direction of their trallscelvers. If the WR signal is asserted
during a data transfer (the CS, DS1, and DS2 signals
asse~, the Octal UART is receiving data from DL<7:0>.
If the WR signal is deasserted during a write data transfer,
the Octal UART is driving data onto the DL <7:0> lines.
INTERRUPT REQUEST
Interrupt request IRQ-The IRO pin is an open drain output. The int~gral int~rrupt scanner asserts the IRO signal
when it has detected an interrupt condition on one of the
eight serial data lines.

to be asserted. A TTL high at a DSR pin causes the DSR
bit in the corresponding line's status register to be deasserted. A change of this input from high-to-Iow, or low-tohigh, causes the assertion of the data set change
(DSCHNG) bit that corresponds to this line in the data set
change summary register. Changes from one state to the
other and back again that occur within one microsecond may
not be detected.
Carrier detect (DCD<7:0»-These eight input pins, one
for each serial data line of the Octal UART, are typically connected through intervening level converters to the received
line signal detect (also called carrier detect) outputs of
modems. A TTL low at a:OCD pin causes the DCD bit of the
corresponding line's status register to be deasserted. A
change of this input from high-to-Iow, or low-to-high, causes
the assertion of the data set change (DSCHNG) bit corresponding to this line in the data set change summary register. Changes from one state to the other and back again
that occur within one microsecond may not be detected.

Interrupt Request transmit/receive (lRQTxRx)- This
signal indicates when the interrupt scanner in the Octal
UART stops and asserts IRO because of a transmitter
interrupt condition (the IROTxRx signal is asserted) or
because of a receiver interrupt condition (the IROTxRxsignal is deasserted). The signal is valid only while IRO is
asserted. The state of IROTxRx signal also appears as bit GENERAL CONTROL SIGNALS
oof the interruptsu~mary register.
Ready (RDY)-The ROY pin is an open drain output. Upon
detecting a negative transition of chip select (GS), the Octal
Interrupt requ!'!st line number (lRQLN<2:0»-These UART asserts the ROY signal to indicate readiness to take
lines indicate the line number at which the Octal UART part in data transfergcles. The ROY signal deasserts after
interrupt scanner stopped and asserted the interrupt request the trailing edge of CS.
(IR~nal. The 'lumber on these lines is valid only while
the IRO signal is asserted. Line IROLN<2> is the high- Reset (RESET)-When the RESET input is asserted, the
order bit and the IROLN line is the low-order bit. The TxD<7:0> lines are asserted and all internal status bits
state of these signals also appears as bits in the interrupt listed in th~ "Architecture Summary" discussion are cleared.
summary register: IROLN<2> as bit 3, IROLN<1 > as bit Manufacturing reset (MRESET)-This signal is for man2, and IROLN as bit 1. Table 3 shows the line numbers ufacturing use only and the input should be connected to
corresponding to settings of IROLN<2:0>.
ground for normal operation.
MISCELLANEOl!S SIGNALS
Clock in (CLK)-AII baLJd rates and internal clocks are
derived from this input. Normal operating frequency is
4.9152 MHz ± 0.1 percent and duty cycle is 50 percent ± 5
percent.

TABLE 3-COM78808 INTERRUPT REQUEST
LI~E ASSIGNMENTS
IRQ Line
<2>

0
0
0
0
1
1
1
1

Line
<1>

<0>

0
0
1
1
0
0
1
1

0
0
0
1

0
1
0
1

0
1
2
3
4
5
6
7

POWER AND GROUND
Voltage (Voo)"",Power supply 5 Vdc
Ground (Vss)-Ground reference

SERIAL DATA
Transmit data (TxD<7:0»-These outputs transmit the
asynchronous qit-serial data streams. They remain at a high
level when no data is being transmitted and a low level when
the TxBRK bit in the associated line's command register is
set.
Receive data (RxD<7:0»-These lines accept asynchronous bit-serial data streams. The input Signals must
remain in the high state for at least one-half bit time before
a high-to-Iow transition is recognized. (A high-to-Iow transition is required to signal the beginning of a "start" bit and
initiate data reception).
MODEM SIGNALS
Data set ready(D~R<7:0»- These eight input pins, one
for each serial data: line on the GOM78808, are typically
connected via intervening level converters to the data set
ready outputs of modems. A TTL low at a DSR pin causes
the DSR bit (bit 7) in the corresponding line's status register

ARCHITECTURE SUMMARY
The Octal UART functions as a serial-to-parallel, parallelto-serial converter/control/er. It can be programmed by a
microprocessor to provide different characteristics for each
of its eight serial data lines (stop bits, parity, character length,
split baud rates, etc.)
Each serial line functions the same as a one-line UARTtype d€vice thereby reducing the number of chips and conserving space on communication devices that require multiple communications lines.
An integral interrupt scanner checks for device interrupt
conditions on the eight lines. Its scanning algorithm gives
priority to receivers over transmitters. The scanner can also
check for interrupts resulting from changes in modem control signals DSR and OGD.
L'
.. R .
. me-specific eglsters
Each of the eight serial data lines in the Octal UART has a
set of registers for buffering data into and out of the line and
for external control of the line's characteristics. These registers are selected for access by setting the appropriate
address on lines ADD<5:0>. Lines ADD<5:3> select one
of the eight data lines. Lines ADD<2:0> select the specific
register for that line, Refer to Table 2 for the register address
assignments.

160

Receiver buffer register-Each line's receiver consists of
a character assembly register and a two-entry FIFO that is
the receiver buffer register. When the RxEN bit in a line's
command register is set, received characters are moved
automatically into the line's receiver buffer as soon as they
have been deserialized from the associated communications line. When there are characters in this FIFO, the
RxRDY bit is set in the status register for the line.
The assertion of the RxRDY signal for a line that already
has the RxlE bit of its command register set causes the
interrupt scan~ogic to stop and generate an interrupt
condition (the IRQ signal is asserted). When the receiver
buffer is read, the interrupt condition is cleared (the IRQ
signal is deasserted) and the interrupt scanner resumes
operation.
If there is another entry in a line's FIFO, the RxRDY bit
remains asserted. When the interrupt scanner reaches this
line again, the assertion of RxRDY causes the scanner to
halt and assert the IRQ again.
Asserting the RESET signal or clearing the RxEN bit initializes the receiver logic of Octal UART. The RxRDY flag is
cleared and the receiver buffer register outputs become
undefined. Any data in the FIFO at that time is lost.

Assertion of the RESET signal initializes the transmitter logic
of the Octal UART. The TxRDY flag is cleared and the transmitter holding register's contents are lost. The transmitter
enable (Tx~N) bit in the line's command register is also
cleared by RESET. If at the end of the reset process, the
TxEN is reasserted and TxRDY bit is reasserted. Software
clearing of TxEN alone produces results different from the
full RESET in that the transmitter holding register's contents are not lost; they are transmitted when TxEN is set
again.
Status register-Each line has a read-only status register
that provides information about the current state of the given
line. This register indicates a line's readiness for transmission or reception of data and flags error conditions in its bit
fields. Figure 3 shows the format of the status register. Table
3 lists the flag bits in each status register.

Transmitter holding register-Each line has a writable
transmitter holding register. When the TxEN bit in the line's
command register is set, characters are moved automatically from the output of this register into the transmitter serialization logic whenever the serialization logic becomes idle.
When this register is empty, the TxRDY bit in the line's status register is set. If the transmitter interrupt enable (TxIE)
bit in the line's command register is also set, the interrupt
scanner logic halts and generates an interrupt condition. If
a character is then loaded into the register, the interrupt is
cleared and the scanner resumes operation.

I
DSR

oeD
FER
ORR
PER
TxEM T

I

I

I

I

I

I

I

I

J I

DY
hRD Y

FIGURE 3: COM78808 STATUS REGISTERS
(LINE 0-6) FORMAT

TABLE 4-COM78808 STATUS REGISTERS (LINES 0-7) DESCRIPTION
Bit

Description

7

DSR (Data set ready)-This bit is the inverted state of the DSR line.

6

DCD (Data set carrier detect)-This bit is the inverted state of the DCD line.

S

FER (Frame error)-Set when the received character currently displayed in the receiver buffer register was not
framed by a stop bit. Only the first stop bit is checked to determine that a framing error exists. Subsequent
reading of the receiver buffer register that indicates all zeros (including the parity bit, if any) can be interpreted
as a Break condition. This bit is cleared by clearing RxEN (bit 2) of the command register, by asserting the
RESET input, or by setling the reset error RERR (bit 4) of the command register.

4

ORR (Overrun error)-Set when the character in the receiver buffer register was not read before another character was received. Cleared by clearing RxEN (bit 2) of the command register, by asserting the RESET input,
or by setting reset error RERR (bit 4) of the command register.

3

PER (Parity error)-If parity is enabled and this bit is set, the received character in the receiver buffer register
has an incorrect parity bit. This bit is cleared by clearing RxEN (bit 2) of the command register, by a,sserting the
RESET input, by selling reset error RERR (bit 2) of the command register, or by reading the current character
in the receiver buffer register.

2

TxEMT (Transmitter empty)-Set when the transmitter serialization logic for the associated line has completed
transmission of a character, and no new character has been loaded into the transmitter holding register.
Cleared by loading the transmitter holding register, by clearing TxEN (0) of the command register, or by asserting the RESET input.

1

RxRDY (Receiver buffer ready)-When set, a character has been loaded into the FIFO buffer from the deserialization logic. Cleared by reading the receiver buffer register, by clearing RxEN (bit 2) in the command register,
or by asserting the RESET input.

0

TxRDY (Transmitter holding register ready)-When set, this bit indicates that the transmitter holding register is
empty. Cleared when the program has loaded a character into the transmitter holding register, when the transmitter for this line is disabled by clearing TxEN (bit 0) in the command register, or by asserting the RESET
input. This bit is initially set when the transmitter logic is enabled by the setting of TxEN (bit 0) and the transmitter holding register is empty. This bit is not set when the automatic echo or remote loopback modes are programmed. Data can be overwritten if a consecutive write is performed while TxRDY is cleared.

161

Mode registers 1 and 2- These read/write registers control the attributes (including parity, character length, and line
speed) of the communications line.
Each of the eight communications lines has two of these
registers, both accessed by the same address on
ADD<5:0>. Successive access operations (either read or
write, in any combination) alternate between the two registers at that address by use of an internal pointer. The first
operation addresses mode' register 1, the next address
mode register 2, and another after that would recycle the
pointer to mode register 1. The pointer is reset to point to
mode register 1 by RESET or by a read of the command
register for this line. These registers should not be accessed
by bit-oriented instructions that do read/modify/write cycles
such as the PDP-11 BIS, BIC, and BIT instructions.

Figure 4 shows the format of mode registers 1 and Table 5
describes the function of the register information.

STOP----'
PAR C T R L - - - - - - - '
CHAR LENGTH - - - - - - - - - '
RSRV-------------~

MCIE - - - - - - - - - - - - - - - - - - '

FIGURE 4-COM78808 MODE
REGISTERS 1 (LINE 0-6) FORMAT

TABLE 5-COM78808 MODE REGISTERS 1 (LINES 0-6) DESCRIPTION
Bit
7,6

5,4

3,2

1
0

Description
STOP-These bits determine the number of stoR bits that are appended to the transmitted characters as
follows. These bits are cleared by asserting the RESET input.
Stop Bits
Bits
7
6
0
0
Invalid
1.0
0
1
1
0
1.5
1
1
2.0
PAR CTRL (Parity control)-These bits determine parity as follows and are cleared by asserting the RESET
input. X = either 1 or O.
Parity Type
Bits
5
4
1
Even
1
0
1
Odd
X
Disabled
0
CHAR LENGTH (Character length)-These bits determine the length (excluding start bit, parity, and stop
bits) of the characters received and sent. Received characters of less than 8 bits are "right aligned" in the
receiver buffer with unused high-order bits equal to zero. Parity bits are not shown in the receiver buffer. The
character length bits are cleared by asserting the RESET input. The character length bits are defined as
follows:
Bit Length
Bit
3
2
0
0
5
0
1
6
7
1
0
1
1
8
RSRV (Reserved and cleared by asserting the RESET input.)
MCIE (Modem control interrupt enable)-When set and RxlE (bit 5) of the command register is set, the
modem control interrupts are enabled. Refer to the Interrupt Scanner and Interrupt Handling information.
Cleared by asserting the RESET input.

Figure 5 shows the format of mode registers 2 and Table
6 indicates the baud rate selections of the register. Bits 7
through 4 of the mode register 2 control the transmitter
baud rate and bits 3 through 0 control the receiver baud
rate. These registers are cleared by asserting RESET input.

Command register-These read/write registers control
various functions on the selected line. Figure 6 shows the
format of the command registers and Table 6 describes
the function of the register information.

I

i

DPER
Rxl E

'\

I' - vI- - 'I I I I I I I
MODE~
I

RERR
Tx BR I<

XMIT RATE - - - - ' .
RECV RATE _--,-_ _ _ _ _ _ _ _--J

Rx EN
Tx I E
TxEN

FIGURE 5-COM78808 MODE
REGISTERS 2 (LINE 0-6) FORMAT

FIGURE 6-COM78808 COMMAND
REGISTERS (LINE 0-6) FORMAT

162

TABLE 6-COM78808 MODE REGISTERS 2 (LINES 0-6) DESCRIPTION
Bit

Description

7:0

XMIT RATE/RECV RATE (Transmitter/Receiver Rate)-Selects the baud rate of the transmitter (bits 7:4) and
receiver (bits 3:0) as follows:
Error·
Transmitter Bits
Receiver Bits
Actual
Nominal
(percent)
7
6
5
4
3
2
1
0
Rate
Rate
0
0
0
0
0
0
0
0
same
50
0
0
0
1
0
0
0
1
same
75
0.826
0
0
1
0
0
0
1
0
110
109.09
1
1
0
0
1
1
134.5
133.33
0.867
0
0
0
150
1
0
0
0
1
same
0
0
0
1
0
1
0
1
0
1
300
same
0
1
1
0
0
1
1
0
600
same
0
1
1
1
0
1
1
1200
same
1
1
0
0
0
1
0
0
1800
1745.45
3.03
0
1
0
0
1
1
0
0
1
2000
2021.05
1.05
2400
1
0
1
1
0
1
same
0
0
1
0
1
1
1
0
1
1
3600
3490.91
3.03
1
0
0
1
1
0
0
4800
same
1
1
1
0
1
1
6981.81
3.03
0
1
7200
1
1
0
1
1
1
0
9600
same
1
1
1
1
1
1
1
19200
same
1
1
1

-

'The frequency of the clock input (ClK) is 4.9152 MHz. The clock input may vary by 0.1 percent. This variance results in an error
that must be added to the error listed.

TABLE 7-COM78808 COMMAND REGISTERS (LINES 0-7) DESCRIPTION
Bit

Description

7,6

OPER MODE (Operating mode)-These bits control the operating mode of the channel as follows. These
bits are cleared by asserting the RESET input.
Bit
Operating Mode

7

6

0
0
1
1

0
1
0
1

Normal operation
Automatic echo
local loopback
Remote loopback

5

RxlE (Receiver interrupt enable)-When set, the RxRDY flag (bit 1) of the status register for this line will
generate an interrupt.

4

RERR (Reset error)-When set, this bit clears the framing error, overrun error, and parity error of the status
register associated with this line. This bit is cleared by asserting the RESET input (not self-clearing).

3

TxBRK (Transmit break)-When set, this bit forces the appropriate TxD<7:0> line to the spacing state at
the conclusion of the character presently being transmitted. When the program clears this bit, normal operation is restored, and any character pending in the transmitter holding register is moved into the serialization
logic and transmitted. The minimum break length obtainable is twice the character length plus 1 bit time.
The maximum break length depends on the amount of time between the program setting and clearing this
bit, but is an integral number of bit times. This bit is cleared by asserting the RESET input.

2

RxEN (Receiver enable)-When set, this bit enables the receiver logic. When cleared, it stops the assembling of the received character, clears all receiver error bits and the RxRDY (bit 1) of the status register,
clears any receiver interrupt conditions associated with this line, and initializes all receiver logic. This bit is
cleared by asserting the RESET input.

1

TxlE (Transmit interrupt enable)-When set, the state of the associated TxRDY flag (bit 0) of the status register is made available to the interrupt scanner logic. When the interrupt scanner logic scans this line, it
determines if the TxRDY flag is asserted and generates an interrupt by asserting the IRQ signal.

0

TxEN (Transmitter enable)-When set, this bit enables the transmitter logic. When cleared, it inhibits the
serialization of the characters that follow but the serialization of the current character is completed. It also
clears the TxRDY flag (bit 0) of the status register, clears any transmitter interrupt conditions associated with
this line, and initializes all transmitter logic except that associated with the transmitter holding register. The
character in the transmitter holding register is retained so that XON/XOFF situations can be properly processed. This bit is cleared by asserting the RESET input.

Bits 5 through 0 enable the line's receiver and transmitter,
enable handling of interrupts, initiate the transmission of
break characters, and reset error bits for the line. Refer to
"Interrupt Scanner" and "Interrupt Handling" paragraphs
for detailed interrupt information. Bits 7 and 6 control the
operating mode of the line. The four modes that can be
set are:

D Normal

163

operation-The serial data received is assembled in the receiver logic and transferred in parallel to the
receiver buffer register. (The RxEN bit must be set.) Data
to be transmitted is loaded in parallel into the transmitter
holding register, then automatically transferred into the
transmitter logic and serialized for transmission. (The
TxEN bit must be set.)

o Automatic echo-The serial data received is assembled
into parallel in the receiver logic (the RxEN bit must be
set) and transferred to the receiver buffer register. Arriving serial data is also routed to the line's TxD pin for
serial output. TxEN is ignored and the transmitter logic
is disabled. TxRDY flags and TxEMT indications are
cleared. No transmitter interrupts are generated.

o Localloopback-The serial data from the RxD input

is ignored and the receiver serial input receives data from
the transmitter serial output. The data is assembled into
parallel form in the receiver logic (the RxEN bit must be
set) and transferred to the receiver buffer register where
it can be read by the program. Data to be transmitted to
the receiver is loaded in parallel form into the transmitter
holding register from which it is automatically moved into
the transmitter logic and serialized for transmission. (The
TxEN bit must be set.) The transmission goes only to the
receiver serial input; the TxD output is held high. As
in normal operation, transmission and reception baud
rates are controlled by the transmitter speed and receiver
speed entries in mode register 2.

SUMMARY REGISTERS
The Octal UART contains two registers that summarize the
current status of all eight serial data lines, making it possible to determine that a line's status has changed with a single read operation. These registers are selected for access
by setting the appropriate address on pins ADD <2:0>.
Because the registers are shared by eight serial lines, the
line-selection bits (ADD <5:3» are ignored when these
registers are accessed. Refer to "Interrupt Scanner and
Interrupt Handling" for detailed interrupt information.
Interrupt summary register-This read-only register indicates that a transmitter or receiver interrupt condition has
occured, and indicates the line number that generated the
interrupt. Figure 7 shows the format of the interrupt summary register and Table 8 describes register information.

o Remote loopback-The serial data received on the
RxD line is returned to the TxD line without
further action. No data is received or transmitted. The
RxRDY, TxRDY, and TxEMT flags are disabled. The
TxEN and RxEN bits of the command register are held
cleared, causing the transmitter and receiver logic to be
disabled.

FIGURE 7-COM78808
INTERRUPT SUMMARY REGISTER FORMAT

TABLE 8-COM78808 INTERRUPT SUMMARY REGISTER DESCRIPTION
Bit
7

6:4

3:1'

0'

Description

IRQ (Interrupt request)-When set, this bit indicates that the interrupt scanner has found an interrupting condition among the eight serial lines of the Octal UART. These conditions also result in the Octal UART asserting the IRQ signal.
RAZ (Read as zero)-Not used
INT LINE NO (Interrupting line number)-These bits indicate the line number upon which an interrupting condition was found. These bits correspond to the IRQLN <2:0> signals-(bit 3 = IRQLN<2>, bit 2= IRQLN<1 >,
and bit 1 = IRQLN. Refer to Table 3.
Tx/Rx (TransmiVreceive)-This bit indicates whether the interrupting condition was caused by a transmitter (Txl
Rx equals 1) or a receiver (Tx/Rx equals 0). This bit corresponds to the IRQTxRx signal of the Octal UART
and is set when IRQTxRx is asserted.

'Bits 3-0 above represent the outputs of a free-running counter and are valid only when bit 7 is set.

Data set change summary register-When the DSR or
DCD inputs that are associated with a line change state,
the bit corresponding to that line in this read-only register
is set. The current state of the DSR and DCD inputs can

DSCHNG 7 -0 - - - - - - - - - '

FIGURE 8-COM78808 DATA SET CHANGE
SUMMARY REGISTER FORMAT

then be obtained from that line's status register. If the state
of a line changes twice within one microsecond, the change
in state may not be detected. Figure 8 shows the format
of the data set change summary register.
When the MCIE bit in a line's mode register 1 is set and
RxlE is also set, the modem control interrupts are enabled
Iorthat line. If DSCHNG for that line is then set, the interrupt
scanner will halt and assert the IRQ signal. The data set
change summary register bits are cleared by writing a 1 into
the bit position. A program that uses this register should read
and save a copy of its contents. The copy can then be written back to the register to clear the bits that were set. The
system interrupts should be disabled and writeback should
directly follow the read operation.
Assertion of the RESET signal disables and initializes the
data set change logic. When the RESET signal is deasserted, future changes in DSR and DCD are reported as
they occur.

164

INTERRUPT SCANNER AND INTERRUPT HANDLING
The interrupt scanner is a four-bit counter that sequentially
checks lines 0 through 7 for a receiver interrupt (counter
positions (0-7) and then checks the lines in the same order
for a transmitter interrupt (counter positions 8-15). If~
scanner detects an interrupt condition, it stops and the IRQ
signal is asserted. An interrupt must be serviced by software or no other interrupt request can be posted,
The scanner determines that a line has a receiver interrupt
if the line's receiver buffer is ready and receiver interrupts
are enabled for that line (RxRDY and RxlE = 1) or either of
the line's modem status signals has changed state and both
receiver and modem control interrupts are enabled for that
line (DSCHNG and RxlE and MCIE = 1),
The scanner determines that a line has a transmitter interrupt if the line's transmitter holding the register is empty and
transmitter interrupts are enabled for that line (TxRDY and
TxIE=1).
When the scanner detects an interrupt, it reports the line
number on the IRQ<2:0> lines. The IRQTxRx signal is
asserted for a transmitter interrupt and deasserted for a
receiver interrupt. The appropriate bits are also updated in
the interrupt summary register. The IRQ line is deasserted
and the scanner is restarted for each of the following three
types of interrupt conditions.

where it stopped, thus providing receivers with equal priority. If the scanner was stopped by a transmitter condition,
the scanner restarts from position 0 (line D's receiver), thus
giving receivers priority over transmitters,

EDGE-TRIGGERED AND LEVEL-TRIGGERED INTERRUPT SYTSTEMS
If the interrupt system of the Octal. UART is used only for
generating interrupts for the RxRDY and/or TxRDY flags,
the IRQ line can be connected to a processor having either
edge-triggered or level-triggered interrupt capability. If the
modem control interrupts are being used (MCIE in mode
register 1 = 1), the IRQ line can be connected only to a processor that uses level-triggered interrupts.

MODEM HANDLING
The TxEMT (transmitter empty) bit of the status register is
typically used to indicate when a program can disable the
transmission medium, as when deasserting the request-tosend line of a modem, A typical program will load the last
character for transmission and then monitor the TxEMT bit
of the status register,
The assertion ofthe TxEMT bit to indicate thattransmission
is complete may occur a substantial time after the loading
of the last character. After the last character is loaded, one
character is in the transmitter holding register and one
character is in the serialization logic. Therefore, it will be
two character times before the transmission process is
completed. Waiting for the TxRDY signal to assert before
monitoring the TxEMT status shortens this by one character time because the TxRDY status bit indicates that there
are no characters in the transmitter holding register. The
times involved are calculated by taking the reciprocal of the
baud rate being used, multiplying by the number of bits per
character (a starter bit-5,6,7, or 8 data bits; plus parity bit
if enabled; and 1,1.5, or 2 stop bits), and multiplying by either
two characters or one, depending on when TxEMT monitoring begins,

o Reading the receiver buffer or resetting the RxlE bit of

the interrupting line for the first type of receiver interrupt
previously described.

o Resetting the MCIE, RxIE, or DSCHNG bit of the interrupting line for the second type of receiver interrupt previously described,

o Loading the transmitter holding register or resetting the
TxlE bit of the interrupting line for transmitter interrupts.
If the scanner was originally stopped by a receiver interrupt
condition, the scanner resumes sequential operation from

V DD
TEST
POINT
TEST
POINT

FROM
OUTPUT )

1

!' '

..

V DD

V DD

j

f

Ik

I

,\~

~

FROM
OUTPUT

r:

r

':"

Ik

S1 CLOSED: PULL UP
S2 CLOSED: PULL DOWN
S1 AND S2 CLOSED: DIVIDER

FIGURE 9-COM78808 OUTPUT LOAD CIRCUITS
165

S1

n

LOAD B - TH R E E-ST ATE OUTPUTS

LOAD A - STANDARD OUTPUTS

I k S2

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range .................................................................................. O°C to + 70°C
Storage Temperature Range ................................................................................. - 55° to + 125°C
Lead Temperature (soldering, 10 sec.) ................................................................................ + 300°C
Positive Voltage on any I/O Pin, with respectto ground .................................................................. + 7V
Negative Voltage on any 110 Pin, with respect to ground ................................................................. - 0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not
be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power
is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. For example, the bench
power supply programmed to deliver + 5 volts may have large voltage transients when the AC power is switched on and off. If this
possibility exists it is suggested that a clamp circuit be used.

TABLE 9-COM78808
DC ELECTRICAL CHARACTERISTICS

TA = O°C to 70°C, V DD =

+ 5V

Symbol

Parameter

V,H

High-level input voltage

V IL

Low-level input voltage

VOH

High-level output voltage

VDD=Min.
10H = 3.5 mA for DL <7:0>
IDH = 2.0 mA for all
remaining output except IRQ
and RDY

VOL

Low-level output voltage

VDD=Min.
10L = 5.5 mA for DL<7:0>
10L = 3.5 mA for all remaining
outputs

I'H

Input current at maximum
input voltage

VDD=Max.
V,=VDD(Max.)

III

Input current at miminum
input voltage

VDD=Max.
V,=O.OV

108 1

Short·circuit output
current for DL <7:0> all
remainin!lQ!!!puts except
IRQandRDY

VDD=Max.

IOZL2

Three-state output
current

VDD=Max.
Vo=O.4V

Three-state output
current

IDD

Supply current

C".

C103

IOZH2

Test Condition

± 5%

Requirements
Min.
Max.
2.0

Units
V

0.8

V
V

2.4

0.4

V

10

fl.A

-10

fl.A

-50

-180

mA

-30

-110

mA

10

fl.A

VDD=Max.
Va = 2.4V

10

A

VDD=Max.
TA=O°

240

mA

Input capacitance

4

pF

Input/output capacitance

5

pF

'No more than one ouput should be short circuited at a time, and the duration of the short should not exceed 1 second.
'All three-state output drivers are wired in an liD configuration. The parameters include the driver and input receiver leakage currents.
'The parameters include the capacitive loads of the output driver and the input receiver.

TIMING PARAMETERS
11 shows the signal timing for a write cycle to transfer inforFigure 10 shows the signal timing for a read cycle to transfer mation from the processor to the Octal UART. Table 11 lists
information from the Octal UART to the processor. Figure the timing parameters for the read and write cycles.

166

!\

DSl DS2

1_1OPWLR_

ADD' 5:0

-----XI

.
IX

VALID ADDRESS

~

---'
WR

~l

-!:

-~

lDPWH --

X
IAHO

IASU

+-+

twsu

~tWHO

ICSU

i~ _teHo

V

-\J

1--1-

+-tRDH~

IRDL

,..----,.

~VALIDDATAOUTf-i

DL' 7:0

tDOZL, tDOZH ~ tOF_1

...

_tDD-j

•

•

tOOLZ, 100HZ

IRQ
I.-tID_1

FIGURE 10-COM78808 BUS READ CYCLE TIMING

OSl/DS2

.!

..~tOPWLW·

XI

..... __ ...__

WR

f-'ASU

.

~.

J

IOPWH -

A

iI\

VALID ADDRESS

1--.

.-

tAHO

/

_I

~ f+-twsu

-

IWHO

i!
I

I'

4-r t- tcsu

-.~

~tRDH~1

\
~
DL ". 7:0

~

ICHO

'RDLli

i

VALID DATA IN

I
I

!.-'Dsu-----+lI_'DHD--·1

IRQ

FIGURE 11-COM78808 BUS WRITE CYCLE TIMING

167

TABLE 10-COM78808 BUS READ AND WRITE TIMING PARAMETERS
Symbol

Definition

tAHo

Hold time...9.f..E valid ADD <5;0> to a valid high level of
DS1 and DS2.

10

tASU

Setup tim~a valid ADD <5;0> to the falling edge of
DS1 and DS2.

30

tCHO

Hold time...9.f..E valid low level of CS to a valid high level of
DS1 and DS2.

10

Setup tim~a v<\lid low level of CS to the falling edge of
DS1 and DS2.

30

too

Propagation dElli!Y. of a valid low level on DS 1 and DS2 (if
CS is low and WR is high) to valid high or low data on DL
<7;0>.

165

tODLl

PrQQ§gation delaY..Q! a valid high level on DS1 and DS2
(if CS is low and WR is high) to DL <7;0> output drivers
disabled.

tcsu

tOOHZ

Requirements (ns)
Min.
Max.

tooLZ
tOOHZ
tODLZ

tOOHZ
tODLZ
tOOHZ

tOOZl

C L=150 pF

50
50
60
60
65
65

CL=50pF
CL=50pF
C L= 100pF
C L= 100pF
C L= 150pF
C L=150pF

165
165

C L= 150pF
C L= 150pF

Propagation dElli!Y. of a valid low level on DS1 and DS2 (if
CS is low and WR is high) to DL <7;0> output driver
enabled.
0
0

tODzl
tOOZH

tDF

Hold time provided during a read cycle by Octal UART of
val&.hjgh or low data on DL <7;0> after the rising edge
of DS1 and DS2.

tOHO

Hold time of a valid DL <7;0> to a valid high level of
DS1 or DS2.

tOPWH

Pulse width high of DS1 and DS2.

450

Pulse width low of DS1 and DS2 when WR is high (read
operation). Refer to timing parameter tDPWLW also.

180

10,000

Pulse width low of DS1 and DS2 when WR is low (write
operation). Refer to timing parameter tDPWLR also.

130

10,000

tOPWLR

tOPWLW

tosu

t\03

tRDH4

tRDL

Load
Circuit'

Setup tim~a valid DL <7;0> to the falling edge of
DS1 and DS2.

0
30

0

Propagation delay of a valid low level on DS1 and DS2 (if
CS is low) to a high level on IRQ.

635

C L=50pF

Propagation ~ of a valid high level of CS to a valid
high level on RDY.

210

CL=50pF

Propagation delay of a valid low level on CS to a valid
low level on RDY.

90

C L=50pF

tWHO

Hold time of a valid high or low level of WR to a valid high
level of DS1 and DS2.

10

twsu

Setup time of a valid high or low level of WR to the falling
edge of DS1 or DS2.

30

'Refer to Figure 9 for the load circuits used with these measurements.
2The tooLZ and tOOHZ parameters are measured with CL= 150 pF. The values of tOOLZ and tOOHZ for CL= 50pF and CL= 100 pF have been derived for
user convenience.
'Total rise time depends on internal delay plus the pullup delay introduced by the external resistor being used. The too parameter can be calculated
by the following: t,o = 500 + RC L where R = value of the resistor that connects to capacitor CL in load A, Figure 9.
'Total rise time depends on internal delay plus the pull up delay introduced by the external resistor being used. The tROH parameter can be calculated
by the following; tROH = 75 + RC L where R = value of the resistor that connects to capacitor CL in load A, Figure 9.

Figure 12 shows the signal timing for the clock input. interrupt timing, effect of the RESET input on data strobe. data
set carrier detect (OeD) and data set ready (OSR) input

timing. and the transmit data output timing. Table 11 lists the
timing parameters for Figure 12.

168

ClK

CLOCK

,eo," '0 ,e""e,

IRO

~

~

------+[-_-'IS-U--,~\------....//r-L_-"-HO----~+------

I

INTERRUPT

(I
1~----'""-----fL

~

RESET

'" ""

-I_

'ORSU

>1

~--'ORHO

-----1>1\'------

EFFECTOF RESET ON DATASTAOBE

OCD DSR

-'XJ'I-__-'V_A_Ll_D_OC_D_D_S_R_DA_T_A_ _-fIX'-___________

7,0 '_ _ _ _

1--_ _ _ _ tospw _ _ _ _ _•
DCD DSR INPUT

TxD

7:0

TRANSMIT OAT A OUTPUT

FIGURE 12-COM78808 MISCELLANEOUS SIGNAL TIMING
TABLE 11-MISCELLANEOUS WRITE TIMING PARAMETERS
Symbol

Definition

Requirements (ns)
Min.

tcp

Period of ClK.

203.45 (4.9152 MHz)

tCPwH

Pulse width high of ClK.

tCPwL
tORHO

Pulse width low of ClK.

tDRSU

load Circuit'

95
95

Hold time of a valid high level of DS1 and DS2 to a valid
high level of RESET.
Setup time of a valid high level of DS1 and DS2 to the
rising edge of RESET.

1,000
900

tospw

Pulse width high or low of DCD <7:0> and DSR <7:0>

tlHO

Hold time provided by Octal UART from a valid IRQlN
<2:0> and IRQTxRx to a valid high level of IRQ.

100

C L =50pF

t lSU

Setup time provided by Octal UART from a valid IRQlN
<2:0> and IRQTxRx to a valid low level of IRQ.

100

C L =50pF

tRES

Pulse width low of RESET.

tTXSK

Pulse width high or low provided by Octal UART on the
TxD <7:0> lines. At each baud rate, the actual pulse
widths provided vary by t TXSK ' This timing parameter
should be used to determine cumulative reception/transmission errors.

1,000

1,000

'Refer to Figure 9 for the load circuits used with these measurements.

169

250

C L =50pF

ments. Figure 14 shows the waveforms for the three-state
outputs measurement.

Figure 13 shows the input and output voltage waveforms
for the propagation delay and setup and hold measure-

SET-UP AND HOLD

PROPAGATION DELAY

FIGURE 13-COM78808 PROPAGATION DELAY
AND SETUP AND HOLD VOLTAGE WAVEFORMS

VINI~.~~) _~
________ _
OUTPUT CONTROL

V,L

08V

I~~: ~~OT~ ~:

VOH 145V)
OUTPUTISEENOTE1)1.5V
VOL +0.5
VOUT (AS MEASUREO)

I

----

lt

-

---j- -------- - - - - - -

tZH INOTE 36)

~

tlZ -

-----

_

-

INOTE 3C)

--- VOL +O.5V

I

___h..--tH_Z_-1.-,;",1-- (NOTE 3C)

VOUTIAS~~~S.:'oR;~ =-=-=--___ 1 _______
1.5V
OUTPUT VOL (NOTE 2)
10.0 V)

------

1 ___ VOH-05V

1.5V

THREE-STATE OUTPUTS
NOTES:

1.

INTERNAL CQNDITIONSARE SUCH THAT THE OUTPUT IS LOW EXCEPT WHEN DISABLED BY
THE OUTPUT CONTROL.

2.

INTERNAL CONDITIONS ARE SUCH THAT THE OUTPUT IS HIGH EXCEPT WHEN DISABLED BY
THE OUTPUT CONTROl.

3.

REFER TO FIGURE 9. A"" 51 ClOSED, B "" S2 CLOSED, C = 51 AND 52 CLOSED.

FIGURE 14-COM78808 THREE-STATE OUTPUT VOLTAGE WAVEFORMS

170
- - - - - - - - - - - - - - - -.. _-

APPENDIX E

68 LEADED CEROUAD GULLWING VERSION (GA)

-~

.050

I
PIN 1 INDENT

/

.900
SO:

1.125
"'.005

r

.018L
.022

"DEFINES MINIMUM CLEAR LEADFRAME ZONE -zone consists of package body,
including ceramic and glass.

68 LEADED CEROUAD FLAT LEAD VERSION (FA)

L

.050

I
PIN 1 INDENT

/

.900
SO:

1.250
",.005

.018L
.022-t--

"DEFINES MINIMUM CLEAR LEADFRAME ZONE -zone consists of package body,
including ceramic and glass .

.155

tax ~
~

C

C

C

C

C

Cl C

C

I

171

Cl Cl

STANDARD MICROSYSTEMS
CORPORATION
35MarcusBtV'

'------

,--

csf------

AD
Wl"i
RS

I

:

f------

TRANSMIT

if---.J

BUFFER
TRANSMIT

i

SHIFT REGISTER

f:~

TRANSMIT CONTROL
MODE

-----v

READ

WRITE

0

REG.

-

~

DECODE
LOGIC

BAUD
SELECT
REG

,-----INT.
INTERRUPT

MASK

r-----

BAUD RATE
GENERATOR

I------

'r--

I

STATUS

REG

RECEIVE CONTROL

-

r---

RECEIVE
CONTROL

REG.

SHIFT REGISTER

!--

y---

RECEIVE

BUFFER

IT
nn
~

;S

CLOCK

'--------

'------

GND ' - -

r-----

-

Vt--------

I------- ®.
LOGIC :-r--

v" '--

I

r--

~

L--

TXOUT

,------

COM8117 BLOCK DIAGRAM

187

AX IN

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications:

consequently complete information sufficient for construction purposes is not necessarily given. The information
has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described
any license under the patent rights of SMC or others. SMC reserves the right to make changes at any time in order
to improve design and supply the best product possible.

188

COM 8251A
J1- PC FAMILY

Universal Synchronous/Asynchronous
Receiver/Transmitter
USART PIN CONFIGURATION
FEATURES
o Asynchronous or Synchronous Operation
- Asynchronous:
5-8 Bit Characters
Clock Rate-1, 16 or 64 X Baud Rate
Break Character Generation
1,1'12 or 2 Stop Bits
False Start Bit Detection
Automatic Break Detect and Handling
- Synchronous:
5-8 Bit Characters
Internal or External Character Synchronization
Automatic Sync Insertion
Single or Double Sync Characters
Programmable Sync Character(s)
Baud Rate-Synchronous-DCt064K Baud
-Asynchronous-DC to 19.2K Baud
Baud Rates available from SMC's COM 8116,
COM 8126, COM 8136, COM 8146, and COM 8046
o Full Duplex, Double Buffered Transmitter and
Receiver
Odd parity, even parity or no parity bit
Parity, Overrun and Framing Error Flags
Modem Interface Controlled by Processor
All Inputs and Outputs are TTL Compatible

02

28 01

03

27 DO

RxO 3

26 Vee

GNO 4

25 RxC

04 5

24 OTR

05 6

23 RTS

06 7

22 OSR

07 8

21 RESET
20 ClK

TxC 9
WR 10
C/O 12
RO 13

o
o

19 TxO
18 TxEMPTY

CS 11

RxROY 14

17 CTS
16 SYNOET/BO
15 TxROY

PACKAGE: 28-pin O.I.P.

o Compatable with Intel 8251A, NEC f1PD8251A

o Single +5 Volt Supply
o Separate Receive and Transmit TTL Clocks

o
o
o
o

o Enhanced version of 8251
028 Pin Plastic or Ceramic DIP Package
COPLAMOS® N-Channel MaS Technology

o

BLOCK DIAGRAM

GENERAL DESCRIPTION
The COM 8251A is an MaS/LSI device fabricated
using SMC's patented COPLAMOS® technology that
meets the majority of asynchronous and synchronous
data communication requirements by interfacing
parallel digital systems to asynchronous and
synchronous data communication channels while
requiring a minimum of processor overhead. The
COM 8251A is an enhanced version of the 8251.
The COM 8251A is a Universal Synchronous/
Asynchronous Receiver/Transmitter (USART)
designed for microcomputer system data
communications. The USART is used as a peripheral
and is programmed by the processor to communicate
in commonly used asychronous and synchronous
serial data transmission techniques including IBM
Bi-Sync. The USART receives serial data streams and
converts them into parallel data characters for the
processor. While receiving serial data, the USART
will also accept data characters from the processor in
parallel format, convert them to serial format and
transmit. The USART will signal the processor when it
has completely received or transmitted a character
and requires service. Complete USART status,
including data format errors and control signals such
as TxE and SYNDET, is available to the processor at
any time.

hD

TxRDY
TxEMPTY

T,e

RxRDY

RxC

L-_-l

-~~~g~~1

189
- - - - - - _ .__....

__. _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

DESCRIPTION OF PIN FUNCTIONS
PIN NO. SYMBOL

NAME

INPUT/
OUTPUT

FUNCTION
An 8-bit, 3-state bi-directional DATA BUS used to interface the
COM 8251A to the processor data bus. Data is transmitted or
received by the bus in response to input/output or ReadlWrite
instructions from the processor. The DATA BUS also transfers
Control words, Command words, and Status.

1,2,27,
28,5-8

02,03, DO,
01,04-07

DATA BUS

1/0

3

RxD

RECEIVER DATA

I

4

GND

GROUND

GND

9

TxC

TRANSMITTER
CLOCK

I

The TRANSMITTER CLOCK controls the serial charactertransmission rate. In the Asynchronous mode, the TxCfrequency is
a multiple of the actual Baud Rate. Two bits of the Mode/nstruction select the multiple to be 1X, 16X, or64Xthe Baud Rate. In the
Synchronous mode, the TxC frequency is automatically selected to equal the actual Baud Rate.
Note that for both Synchronous and Asynchronous modes,
serial data is shifted out oftheUSART bythefallingedgeofTxC.

10

WR

WRITE DATA

I

A "zero" on this input instructs the COM 8251 A to accept the
data or control word which the processor is writi ng out to the
USART via the DATA BUS.

11

CS

CHIP SELECT

I

A "zero" on this input enables the USART for reading and writing
to the processor. When CS is high, the DATA BUS is in the float
state and RD and WR will have no effect on the chip.

12

C/O

CONTROL/DATA

I

The ControllData input, in conjunction with the WR and RD
inputs, informs the USART to accept or provide either a data
character, control word or status information via the DATA BUS.
0= Data; 1 = ControllStatus

13

RD

READ DATA

I

A "zero" on this input instructs the COM 8251A to placethedata
or status information onto the DATA BUS for the processor
to read.

14

RxRDY

RECEIVER READY

0

The RECEIVER READY output indicates that the Receiver
Buffer is ready with an "assembled" character for input to the
processor. For polled operation, the processor can check
RxRDY using a Status Read or RxRDY can be connected to the
processor interrupt structure. Note that reading the character
to the processor automatically resets RxRDY.

15

TxRDY

TRANSMITTER READY

0

TRANSMITTER READY signals the processor that the transmitter is ready to accept a data character. TxRDY can be used
as an interrupt or may be tested through the Status information
polled qQ§'aton. TxRDY is automatically reset by the leading
edge ofWR when a data character is loaded from the processor.

16

SYNDETI
BRKDET

SYNC DETECTI
BREAK DETECT

1/0

The SYNDET feature is only used in the Synchronous mode.
The USART may be programmed throughtheMode Instruction
to operate in either the internal or external Sync mode and
SYNDET then functions as an output or input respectively. In
the internal SYNC mode, the SYNDET output will go to a "one"
when the COM 8251A has located the SYNC character in the
Receive mode. If double SYNC character (bi-sync) operation
has been programmed, SYNDET will go to "one" in the middle
of the last bit of the second contiguously detected SYNC character. SYNDET is automatically reset to "zero" upon a Status
Read or RESET. In the external SYNC mode, a "zero" to "one"
transition on the SYNDET input is sampled during the negative
half cycle of RxC and will cause the COM 8251A to start assembling data character on the next rising edge of RxC. The
length of the SYNDET input should beat least one RxC period,
but may be removed once the COM 8251A is in SYNC. When
external SYNC DETECT is programmed, the internal SYNC
DETECT is disabled.

This input receives serial data into the USART.
Ground

190

---~~.------

PINNa. SYMBOL

NAME

INPUT/
OUTPUT

16
(cont.)

FUNCTION
The SYNDET/BRKDET pin is used in both Synchronous and
Asynchronous modes. When in SYNC mode the features for
the SYNDET pin described above apply. When in Asynchronous
mode, the BREAK DETECT output will go high when an all zero
word of the programmed length is received. This word consists
of: start bit, data bit, parity bit and onestop bit.Resetonly occurs
when Rx Data returns to a logic one state or upon chip RESET.
The state of BREAK DETECT can also be read as a status bit.

17

CTS

CLEAR TO SEND

I

A "zero" on the CLEAR TO SEND input enables the USART to
transmit serial data if the TxEN bit in the Command Instruction
register is enabled (one).
If either a TxEN off or CTS off condition occurs while the Tx is
in operation, the Tx will transmitalithedataintheUSARTwritten
prior to the Tx Disable command before shutting down.
.

18

TxE

TRANSMITTER EMPTY

0

The TRANSMITTER EMPTY output signals the processor that
the USART has no further characters to transmit. TxE is automatically reset upon receiving adatacharacterfrom theprocessor. In half-duplex, TxE can be used to signal end of a transmission and request the processor to "turn the line around".
The TxEN bit in the command instruction does not effect TxE.
In the Synchronous mode, a "one" on this output indicates that
a SYNC character or characters are about to be automatically
transmitted as "fillers" because the next data character has not
been loaded; an underflow condition. If the USART is operating in the two SYNC character mode, both SYNC characters will
be transmitted before the message can resume. TxE does not
go low when the SYNC characters are being shifted out. TxE
goes low upon the processor writing a character to the USART.

19

TxD

TRANSMITTER DATA

0

This output is the transmitted serial data from the USART. When
a transmission is concluded the TxD line will alwllYs return to
the marking state unless SBRK is programmed.

20

ClK

CLOCK PULSE

I

The ClK input provides for internal device timing. External
inputs and outputs are not referenced to ClK, but the ClK
frequency must be greater than 30 times the RECEIVER or
TRANSMITTER CLOCKS in the 1X mode and greater than 4.5
times for the 16X and 64X modes.

21

RESET

RESET

I

A "one" on this input forces the USART into the "idle" mode
where it will remain until reinitialized with a new set of control
words. RESET causes: RxRDY =TxRDY =TxEmpty =SYNDETI
BRKDET = 0; TxD = DTR = RST = 1. Minimum RESET pulse
width is 6 lev, ClK must be running during RESET.

22

DSR

DATA SET READY

I

The DATA SET READY inRut can be tested by the processor
via Status information. The DSR input is normally used to test
Modem Data Set Ready condition"

23

RTS

REQUEST TO SEND

0

The REQUEST TO SEND output iscontrolledviatheCommand
word. The RTS output is normally ~sed to drive the Modem
Request to Send line.
.

24

DTR

DATA TERMINAL

0

The DATA TERMINAL READY output is controlled via the
Command word.Th~ lJ'I'R output is normally used to drive
Modem Data Terminal Ready or Rate Select lines.

25

RxC

RECEIVER CLOCK

I

The RECEIVER ClQCK is the rilte at which the incoming character is received. In .the Asynchronous mode, the AXe frequency
may be 1, 16 or 114 times the actual Baud Rate but in the Synchronous mode the RxC frequency must equal the Baud Rate.
Two bits in the mode instruction select Asynchronous at 1X,
16X or 64X or Synchronous operation at 1X the Baud Rate.
Data is sampled into the USART on the rising edge of RxC.

26

Vee

Vee SUPPLY VOLTAGE

PS

~

+5 volt supply

191

I

DESCRIPTION OF OPERATION-ASYNCHRONOUS
Transmission -

Receive-

When a data character is written into the USART, it automatically adds a START bit (low level or "space") and the
number of STOP bits (high level or "mark") specified,by
the Mode Instruction, If Parity has been enabled, an odd
or even Parity bit is 'inserted just before the STOP bit(s).
as specified by the Mode Instruction, Then, depending
on CTS and TxEN, the character may be transmitted as a
serial data stream at the TxD output Data is shifted out by
the falling edge of TxC at a transmission rate of TxC,
TxC/16 or TxC/64, as defined by the Mode Instruction,

The RxD input line is normally held "high" (marking) by
the transmitting device, A falling edge (high to low transition) at RxD signals the possible beginning of a START bit
and a new character, The receiver is thus prevented from
starting in a "BREAK" state, The START bit is verified by
testing for a "low" at its nominal center as specified by the
BAUD RATE, If a "low" is detected, it is considered valid,
and the bit assembling counter starts counting, The bit
counter locates the approximate center of the data, parity
(if specified), and STOP bits, The parity error flag (PE) is
set, if a parity error occurs, Input bits are sampled at the
RxD pin with the rising edge of RxC, If a high is not detected for the STOP bit, which normally signals the end
of an input character, a framing error (FE) will beset After
the STOP bit time, the input character is loaded into the
paralled Data Bus Buffer of the USART and the RxRDY
signal is raised to indicate to the processor that a character
is ready to be fetched, If the processor has failed to fetch
the previous character, the new character replaces the old
and overrun flag (OE) isseI. All the error flags can be reset
by setting a bit in the Command Instruction, Error flag
conditions will not stop subsequent USART operation,

If no data characters have been loaded into the USART, or
if all available characters have been transmitted, the TxD
output remains "high" (marking) in preparation for sending the START bit of the next character provided by the
processor, TxDmay be forced to send a BREAK (continuously low) by setting the correct bit in the Command
Instruction,

DESCRIPTION OF OPERATION-SYNCHRONOUS

Transmission As in Asynchronous transmission, the TxD output remains "high" (marking) until the USART receives the first
character (usually a SYNC character) from the processor,
After a Command Instruction has set TxEN and after
Clear to Send (CTS) goes low, the first character is ser~
transmitted, Data is shifted out on the falling edge of TxC
at the same rate as TxC,
Once transmission has started, Synchronous Data Protocols require tha,t the serial data stream at TxD continue
at the TxC rate or-SYNC will be lost If a data character is
not provided by the processor beforetheUSARTTransmit
Buffer becomes empty, the SYNC character(s) loaded
directly following the Mode Instruction will be automatically inserted in the TxD data stream, The SYNC character(s) are inserted to fill the line and maintain synchronization until the new data characters are available for
transmission, If the USART becomes empty, and must
send the SYNC; character(s). the TxEMPTY output is
raised to signal the processor that the Transmitter Buffer
is empty and SYNC characters are being transmitted,
TxEMPTY is aUtomatically reset by the next character
from the processor,

ReceiveIn Synchronous receive, character synchronization can
be either external or internal. If the internal SYNC mode

has been selected, the ENTER HUNT (EH) bit has been
set by a Command Iflstruction, the receiver goes into the
HUNT mode,
Incoming data on the RxD input is sampled on the rising
edge of RxC, and the contents of the Receive Buffer are
compared with the first SYNC character after each bit has
been loaded until a match is found, If two SYNC characters
have been programmed, the next received character is
also compared, When the (two contiguous) SYNC character(s) programmed have been detected, the USART
leaves the HUNT mode and is in character synchronization, At this time, the SYNDET (output) issethigh,SYNDET
is automatically reset by a STATUS READ,
If external SYNC has been specified in the Mode Instruction, a "one" applied to the SYNDET (input) for at least
one RxC cycle will synchronize the USART.
Parity and Overrun Errors are treated the same in the
Synchronous as in the Asynchronous Mode, If not in
HUNT, parity will continlle to be checked even if the receiver is not enabled, Framing errors do not apply in the
Synchronous format
The processor may command the receiver to enter the
HUNT mode with a Command Instruction which sets
Enter HUNT (EH) if synchronization is lost Under this
condition the Rx register will be cleared ,to all "ones",

192
- - - - -- - - - - - -

OPERATION AND PROGRAMMING
The microprocessor program controlling the COM 8251A
performs these tasks:

Control codes determine the mode in which the COM
8251A will operate and are used to set or reset control
signals output by the COM 8251A.

- Outputs control codes
-Inputs status
- Outputs data to be transmitted
-Inputs data which has been received

The Status register contents will be read by the program
monitoring this device's operation in order to determine
error conditions, when and how to read data, write data or
output control codes. Program logic may be based on
reading status bit levels, or control signals may be used
to request interrupts.

INITIALIZING THE COM 8251A
Figure 1. Control Word Sequences for Initialization
MODE CONTROL
}

MODE CONTROL

INITIALING
SEOUENCE

COMMAND

SYNC #1
C/15= 1

C/D=1

DATA

SYNC #2
(OPTIONAL)

.

COMMAND

COMMAND

)

INITIALING
SEOUENCE

DATA
C/D=O

:
:

C/D=1

COMMAND

DATA

.

C/D=O

{

DATA

.

ASYNCHRONOUS OPERATION

SYNCHRONOUS OPERATION

The COM 8251A may be initialized following a system
RESET or prior to starting a new serall/O sequence. The
USART must be RESET (external or internal) following
power up and subsequently may be reset at any time
following completion of one activity and preceding a
new set of operations. Following a reset, the COM 8251A
enters an idle state in which it can neither transmit nor
receive data.

mode byte) output as control codes will be interpreted as
SYNC characters. For either asynchronous or synchronous operation, the next byte output as a control code is
interpreted as a command. All subsequent bytes output
as control codes are interpreted as commands. There are
two ways in which control logic may return toanticipating
a mode control input; following aRESETinputorfoliowing
an internal reset command. A reset operation (internal via
IR or external via RESET) will cause the USART to interpret the next "control write", which should immediately
follow the reset, as a Mode Instruction.

The COM 8251A is initialized with two, three or four control words from the processor. Figure 1 shows the sequence
of control words needed to initialize the COM 8251A, for
synchronous or for asynchronous operation. Note that
in asynchronous operation a mode control is output to
the device followed by a command. For synchronous
operation, the mode control is followed by one or two
SYNC characters, and then a command.
Only a single address is set aside for mode control bytes,
command bytes and SYNC character bytes. Forthis to be
possible, logic internal to the chip directs control information to its proper destination based on the sequence in
which it is received. Following a RESET (external or internal), the first control code output is interpreted as a mode
control. If the mode control specifies synchronous operation, then the next one or two bytes (as determined by the
193

After receiving the control words the USART is ready to
communicate. TxRDY is raised to signal the processor
that the USART is ready to receive a character for transmission. Concurrently, the USART is ready to receive
serial data.
C/O
0
0
1
1
X
X

RD
0
1
0
1
X
1

WR
1
0
1
0
X
1

CS
0
0
0
0
1
0

USART - Data Bus
Data Bus - USART
Status - Data Bus
Data Bus - Control
Data Bus - 3-State

MODE CONTROL CODES
The COM 8251A interprets mode control codes as illustrated in Figures 2 and 3.
Control code bits Oand 1 determine whether synchronous
or asynchronous operation is specified. A non-zero val ue
in bits 0 and 1 specifies asynchronous operation and defines the relationship between data transfer baud rate and
receiver or transmitter clock rate. Asynchronous serial
data may be received or transmitted on every clock pulse,
on every 16th clock pulse, or on every 64th clock pulse,
as programmed. A zero in both bits 0 and 1 defines the
mode of operation as synchronous.
For synchronous and asynchronous modes, control bits
2 and 3 determine the number of data bits which will be
present in each data character. In the case of a programmed
character length of less than 8 bits, the least significant
DATA BUS unused bits are "don't care" when writing data
to the USART and will be "zeros" when reading data. Rx
data will be right justified onto DO and the LSB for Tx data
is DO.
For synchronous and asynchronous modes, bits 4 and 5

determine whether there will be a parity bit in each character, and if so, whether odd or even parity will beadopted.
Thus in synchronous mode a character will consistoffive,
six, seven or eight data bits, plus an optional parity bit. In
asynchronous mode, the data unit will consist of five, six,
seven or eight data bits, an optional parity bit, a preceeding
start bit, plus 1,1 'h or 2 trailing stop bits. Interpretation of
subsequent bits differs for synchronous or asynchronous
modes.
Control code bits 6 and 7 in asynchronous mode determine
how many stop bits will trail each data unit. 1'h stop bits
can only be specified with a 16X or 64X baud rate factor.
In these two cases, the half stop bit will be equivanlent to
8 or 32 clock pulses, respectively.
In synchronous mode, control bits 6 and 7 determine
how character synchronization will be achieved. When
SYN DET is an output, internal synchronization is specified ;
one or two SYNC characters, as specified by control bit 7,
must be detected at the head of a data stream in order to
establish synchronization.

COMMAND WORDS
Command words are used to initiate specific functions
within the COM 8251A such as, "reset all error flags" or
"start searching for sync". Consequently, Command
Words may be issued by the processor to the COM 8251A
at any time during the execution of a program in which

specific functions are to be initialized within the communication circuit.
Figure 4 shows the format for the Command Word.

Figure 4. COM 8251A Control Command
7

6

5

4

3

2

O_BitNo.

I I I I I I I I

~

TxEN
1 = Enable transmission
a = Disable transmission
DTR
1 = DTR output is forced to a
RxE
1 = Enable RxRDY

a = Disable RxRDY
SBRK
1 = TxD is forced low

a = Normal operation
ER
1 = Resets all error flags in
Status register (PE. OE. FE)
RTS
1 = RTS output is forced to a

IR
1 = Reset format
EH
1 = Enter HUNT mode

194

Figure 2. Synchronous Mode Control Code.

O~BitNo.
7 6 5 4 3 2
r-,--r-.--r-,--r-.-.
I
10 10 1

I

I I

L=

'-,-I

'-,-I

syncmOde
00
01
10
11

5 bits per character
6 bits per character
7 bits per character
8 bits per character

' - - - - - - - - - 0= Parity disable, 1 = Parity enable
' - - - - - - - - - - - 0= Odd parity, 1 = Even parity
L..-_ _ _ _ _ _ _ _ _ _ _

1--_ _ _ _ _ _ _ _ _ _ _ _ _

0= SYNDET output
1 = SYNDET input
0=2 SYNC characters
1 = 1 SYNC character

Figure 3. Asynchronous Mode Control Code.

7

6

5

4

3

2

O_BitNo.

.----r--r---'11l"---Ir---1Ir---tI--'Ir---t1
'-,-I

'-,-I

'-,-I

t

OO
01
' - - - - - 10
11

Invalid (SYNC mode)
Async mode, 1X Baud rate factor
Async mode, 16X Baud rate factor
Async mode, 64X Baud rate factor

00 5 bits per character
' -_ _ _ _ _ _ 01 6 bits per character
10 7 bits per character
11 8 bits per character
' - - - - - - - - - - 0 = Parity disable, 1 = Parity enable
'-----------0

= Odd parity, 1 = Even parity

00
1--_ _ _ _ _ _ _ _ _ _ _ _ _

01

10
11

195

Invalid
1 stop bit
1'/' stop bits
2 stop bits

I

Bit 0 of the Command Word is the Transmit Enable bit
(TxEN). Data transmission for the COM 8251A cannot
take place unless TxEN is set (assuming CTS = 0) in the
command register. The TX Disable command is prevented
from halting transmission by the Tx Enable logic until all
data previously written has been transmitted. Figure 5
defines the way in which TxEN, TxE and TxRDY combines
to control transmitter operations.
Bit 1 is the Data Terminal Ready (DTR) bit. When the DTR
command bit is set, the DTR output connection is active
(low). DTR is used to advise a modem thatthe data terminal
is prepared to accept or transmit data.

Bit 2 is the Receiver Enable Command bit (RxE). RxE is
used to enable the RxRDY output signal. RxE, when zero,
prevents the RxRDY signal from being generated to notify
the processor that a complete character is framed in the
Receive Character Buffer. It does not inhibitthe assembly
of data characters at the input, however. Consequently,
if communication circuits are active, characters will be
assembled by the receiver and transferred to the Receiver
Buffer. If RxE is disabled, the overrun error (OE) will probably be set; to insure proper operation, the overrun error
is usually reset with the same command that enables RxE.

FigureS.
Operation of the Transmitter Section as a Function of TxE, TxRDY and TxEN
TxEN
1

TxE
1

TxRDY
1
Transmit Output Register and Transmit Character Buffer empty.
TxD continues to mark if COM 8251A is in the asynchronous mode.
TxD will send SYNC pattern if COM 8251A is in the Synchronous
Mode. Data can be entered into Buffer.

o

o

Transmit Output Register is shifting a character. Transmit Character
Buffer is available to receive a new byte from the processor.

o

Transmit Register has finished sending. A new character is waiting
for transmission. This is a transient condition.

o

o

Transmit Register is currently sending and an additional character
is stored in the Transmit Character Buffer for transmission.

0/1

0/1

Transmitter is dis,abled.

Bit 3 is the Send Break Com mand bit (SBR K). When S BR K
is set, the transmitter output (TxD) is interrupted and a
continuous binary "0" level, (spacing) isappliedtotheTxD
output signal. The break will continue until a subsequent
Command Word is sent totheCOM8251A to removeSBRK.
. Bit 4 is the Error Reset bit (ER). When a Command Word
is transferred with the ER bit set, all three error flags (PE,
OE, FE) in the Status Register are reset. Error Reset occurs
when the Command Word is loaded into the COM 8251A.
No latch is provided in the Command Register to save the
ER command bit.
Bit 5, the ;:;R:-eq'::"u-e--s""'t""~""o""S'-:e'::"n-:;d Command bit (RTS), sets a
latch to reflect the RTS signal level. The output of this
latch is created independently of other signals in the
COM 8251A. As a result, data transfers may be made by
the processor to the Transmit Register, and data may be
actively transmitted to the communication line through
TxD regardless of the status of RTS.

return to the Idle mode. All functions within the COM
8251A cease and no new operation can be resumed until
the circuit is reinitialized. If the operating mode is to be
altered during the execution of a processor program, the
COM 8251A must first be reset. Either the RESET input
can be activated, or the Internal Reset Command can be
sent to the COM 8251A. Internal Reset is a momentary
function performed only when the command is issued.

Bit 6, the Internal Reset (IR), causes the COM 8251A to

Bit 7 is the Enter Hunt command bit (EH). The Enter Hunt
mode command is on Iy effective for the COM 8251 A when
it is operating in the Synchronous mode. EH causes the
receiver to stop assembling characters at the RxD input,
clear the Rx register to all "ones", and start searching for
the prescribed sync pattern. Once the "Enter Hunt" mode
has been initiated, the search for the sync pattern will
continue indefinitely until EH is reset when a subsequent
Command Word is sent, when the IR command is sent to
the COM 8251A, or when SYNC characters are recognized.
Parity is not checked in the EH mode.

STATUS REGISTER
The Status Register maintains information about the
totally equivalent to the TxRDY output pin, the relationship
current operational status of the COM 8251A. Status cari
is as follows:
be read at any time, however, the status update will be
TxRDY (status bit) = Tx Character Buffer Empty
inhibited during status read. Figure 6 shows the format of
TxRDY (pin 15) = Tx Character Buffer Empty • CTS • TxEN
the Status Register.
TxRDY signals the processor thatthe Transmit Character
Buffer is empty and that the COM 8251A can accept a new
character for transmission. The TxRDY status bit is not

196

RxRDY Signals the processor that a completed character
is holding in the Receive Character Buffer Register for
transfer to the processor.

Figure 6. The COM 8251A Status Register

7
I

6
I

5
I

4
I

3
I

2
I

O~BitNo.

I

I

I

t

TxRDY
RxRDY
TxE
PE
Parity error
OE
Overrun error
FE
Framing error
SYNDET/BRKDET
DSR

TxE signals the processor that the Transmit Register
is empty.
PE is the Parity Error signal indicating to the CPU that the
character stored in the Receive Character Buffer was
received with an incorrect number of binary "1" bits. PE
does not inhibit USART operation. PE is reset by the ER bit.
OE is the receiver Overrun Error. OE is set whenever a byte
stored in the Receiver Character Register is overwritten
with a new byte before being transferred to the processor.
OE does not inhibit USART operation. OE is reset by the
ER bit.
FE (Async only) is the character framing error which indicates that the asynchronous mode byte stored in the
Receiver Character Buffer was received with incorrect bit
format ("0" stop bit), as specified by the cu rrent mode. FE
does not inhibit USART operaton. FE is reset by the ER bit.

SYNDET is the synchronous mode status bit associated
with internal or external sync detection.
DSR is the status bit set by the external ""D:-a-;-ta-S"e-ct"R"e-a-d'y
signal to indicate that the communication Data Set is
operational.
All status bits are set by the functions described for
them. SYNDET is reset whenever the processor reads the
Status Register. OE, FE, PE are reset by the error reset
command or the internal reset command or the RESET
input. OE, FE, or PE being set does not inhibit USART
operation.
Many of the bits in the status register are copies ofexternal
pins. This dual status arrargement allows the USART to
be used in both Polled and Interrupt driven environments.
Status update can have a maximum delay of 16 tCY periods.

Note:
1. While operating the receiver it is important to realize
that the RxE bit of the Command Instruction only inhibits the assertion of RxRDY; it does not inhibit the
actual reception of characters. As the receiver is constantly running, it is possible for it to contain extraneous
data when it is enabled. To avoid problems this data
should be read from the USART and discarded. This
read should be done immediately following the setting
of the RxE bit in the asynchronous mode, and following
the setting of EH in the synchronous mode. It is not
necessary to wait for RxRDY before executing the
dummy read.

3. The USART may provide faulty RxRDY for the first read
after power-on or for the first read after the receiver is
re-enabled by a command instruction (RxE). A dummy
read is recommended to clearfaulty RxRDY. This is not
the case for the first read after hardware or software
reset after the device opration has been established.
4. Internal Sync Detect is disabled when External Sync
Detect is programmed. An External Sync Detect Status
is provided through an internal flip-flop which clears
itself, assuming the External Sync Detect assertion has
removed, upon a status read. As long as External Sync
Detect is asserted, External Sync Detect Status will
remain high.

2. ER should be performed whenever RxE of EH are programmed. ER resets all error flags, even if RxE = O.

197

MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range ............................................................ 0° C to +70° C
Storage Temperature Range .......................................................... -55°C to +150°C
Lead Temperature (soldering, 10 sec) ........................................................... +325°C
Positive Voltage on any Pin, with respect to ground ................................................. +8.0V
Negative Voltage on any Pin, with respect to ground ................................................ -0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these at any other condition above those indicated in the operational
sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute
Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit
voltage spikes or "glitches" on their outputs when the AC power is switched on and off.
In addition, voltage transients on the AC power line may appear on the DC output. If this
possibility exists it is suggested that as clamp circuit be used.

ELECTRICAL CHARACTERISTICS (TA = 0° e to 70 0 e, Vcc = +5V ±5%, unless otherwise noted)

I MIN. I

PARAMETER

SYMBOLI

MAX.

UNIT

I

TEST CONDITIONS

D.C. Characteristics
VIL

Input Low Voltage

-0.3

0.8

V

VIH

Input High Voltage

2.0

Vcc

V

VOL

Output Low Voltage

0.45

VOH

Output High Voltage

V
V

2.4

IOL=2.2 mA
IOH

= -400 pA

IOFL

Output Float Leakage

±10

pA

VOUT = Vcc TO 0.45V

IlL

Input Leakage

±10

pA

VIN = Vcc TO 0.45V

Icc

Power Supply Current

100

mA

All Outputs = High

Capacitance
CIN

I,nput Capacitance

CliO

I/O Capacitance

TA= 25°C, Vcc= GND

I !

10
20

pF
pF

!fC=1MHZ
Unmeasured pins returned to GND

A.C. Characteristics
Bus Parameters (Note 1)
Read Cycle:

CiiS)

o

ns

Note2

Address Hold Time for READ (CS, C/O)

o

ns

Note 2

Address Stable Before READ (CS,
READ Pulse Width

250

Data Delay from READ
READ to Data Floating

10

ns
200

ns

100

ns

Note 3, CL = 150 pF

Write Cycle:

o
o

ns

WRITE Pulse Width

250

ns

tow

Data Set Up Time for WRITE

150

ns

two

Data Hold Time for WRITE

o

ns

tRV

Recovery Time Between WRITES

6

tCY

Note 4

Notes 5, 6

tAW

Address Stable Before WRITE

tWA

Address Hold Time for WRITE

tww

ns

Other Timings:

tCY

Clock Period

.320

1.35

ps

t¢

Clock High Pulse Width

120

tcy-90

ns

t

Clock Low Pulse Width

90

198

ns

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

20

ns

tA, tF

Clock Rise and Fall Time

tOT,

TxD Delay from Falling Edge of TxC

tSA,

Rx Data Set-Up Time to Sampling Pulse

2

f.1s

tHAx

Rx Data Hold Time to Sampling Pulse

2

f.1s

fTx

Transmitter Input Clock Frequency
1X Baud Rate
16X Baud Rate
64X Baud Rate

hpw

hpo

fA,

5

tAPO

DC
DC
DC

64
310
615

f.1s

kHz
kHz
kHz

Transmitter Input Clock Width
1X Baud Rate
16X and 64X Baud Rate

12
1

tCY

Transmitter Input Clock Pulse Delay
1X Baud Rate
16X and 64X Baud Rate

15
3

tcy
tcy

Receiver Input Clock Frequency
1X Baud Rate
16X Baud Rate
64X Baud Rate

tAPW

1

DC
DC
DC

tcy

64
310
615

kHz
kHz
kHz

Receiver Input Clock Pulse Width
1X Baud Rate
16X and 64X Baud Rate

12
1

tCY
tCY

Receiver Input Clock Pulse Delay
1X Baud Rate
16X and 64X Baud Rate

15
3

tCY

hxAOY

TxRDY Pin Delay from Center of last Bit

tTxRDY CLEAR

TxRDY I from Leading Edge of WR

tAxAOY

RxRDY Pin Delay from Center of last Bit

tA,AOY CLEAA RxRDY j from Leading Edge of RD

TEST CONDITIONS

tcy
8

tcy

Note?

150

ns

Note?

24

tCY

Note?

150

ns

Note?

tiS

Internal SYNDET Delay from Rising
Edge of RxC

24

tCY

Note?

tES

External SYNDET Set-Up Time Before
Falling Edge of RxC

16

tCY

Note?

20

tCY

Note?

8

tCY

Note?

20

tcy

Note?

hxEMPTY

TxEMPTY Delay from Center of Data Bit

twc

Control Delay from RisJ!:!fLEdge of
WRITE (TxEn, DTR, RTS)

tCA

Control to READ Set-Up Time (DSR, CTS)

NOTES: 1.
2.
3.
4.

AC timings mili!sured VOH = 2.0, VOL= 0.8,j!nd with load circuit of Figure 1.
Chip Select (CS) and Command/Data (C/O) are considered as Addresses.
Assumes that Address is valid before RDI.
This recovery time is for RESET and Mode Initialization. Write Data is allowed only when TxRDY
Writes for Asynchronous Mode is 8 tCY and for Synchronous Mode is 16 tCY.
5. The TxC and RxC frequencies have the following limitations with respect to ClK.
For 1X Baud Rate, fTX or fRx:O; 1/(30 tCY)
For 16X and 64X Baud Rate, fTX or fAX:O; 1/(4.5 tCY)
6. Reset Pulse Width = 6 tCY minimum; System Clock must be running during RESET.
7. Status update can have a maximum delay of 28 clock periods from the event affecting the status.

= 1. Recovery Time between

+20

2V

Typical Ll Output
Delay Versus
Ll Capacitance (pF)

/

-10

Figure 1.

-20
-100

TEST LOAD CIRCUIT

199

L

+10

/
·50
~

/....
SPEC

-r-SO

CAPACITANCE (pF)

+100

WAVEFORMS

System Clock Input

CLOCK 0

Transmitter Clock & Data

he (b. MODE)

TX'r: (16xMOOE)

Tx DATA

Receiver Clock & Data

(Ax BAUD COUNTER STARTS HERE)
START BIT

Ax DATA

DATA BIT

1-.-t"'D~.·

------hI

----I.r---tRPw-------l
Rxe (1x MODEl

'----______----'1

1}---;:-;;~==c::------11

RxC (16xMODE)

INT SAMPLING
PULSE

200
- - - ..........

__

.... _ - -

.....

_ ...... _ - - -

DATA BIT

~

Write Data Cycle (CPU

~r-------------tTxRDY CLEAR

---~/

TxRDY

USART)

IH'ww 11--------

---------~ I~

~
I~ 'DW ~I-j

we
DATA IN m.B.)

'WD
__ _ _~D~O~N.~T~CA~R~E_~~~~~1=~-~D~O~N~'T~C~AR~E~
DATA STABLE

--------~~;

C/D

~,------

------------~~~~'A_W_·_____~_'W~Ay---------

os

Read Data Cycle (CPU
R,RDY _ _ _ _~/

~
DATA OUT (D.B.)

- -_________

~

USART)

\1
I I~~'-R'-R-D-Y-CL-E-A-R----'RR--~I-----

4

~
~I l-t RD

DATA FLOAT

I

CID

--------~!~
'\

cs

--------~ 'AR .

-I

I-'DF
DATA FLOAT

DATA OUT ACTIVE

~Y----

~--------

Write Control or Output Port Cycle (CPU

~

(~~~E~ ----------------,X~

USART)

_____

I: ,wc--I

~ ----------~ - - - - - - I-'DW----i

two

DATA IN (D.B.)

!--- 'AW
_________ I~CS

1---1 'WA
t

c/o _ _ _ _ _ _ _ _~J'T

,~

'AW

_ _ _ __

---Ir'W,",A~_ _ __

~,--_ _ _ _~Y

NOTE =1· TWC INCLUDES THE RESPONSE TIMING OF A CONTROL BYTE.

201

I

Read Control or Input Port (CPU
oSR.CTS
INoTE=" __________

AD

USART)

+-

r--------------------------~--------

~X~----------~------------------------

1- ==11_

tCR
--------,~

-i4

DATA OUT

10.B.1

-I tAR

tRR-1
X~----

1- tRo

1r--

-

-

toF

-

tRA

CID _ _ _ _ _ _ _~!I

~

-I
I-Os ------------~~L_____________~y_____
tAR -

-

tRA

NOTE =1: TCR INCLUDES THE EFFECT OF mON THE TxENBL CIRCUITRY,

Transmitter Control & Flag Timing (ASYNC Mode)

tTxEMPTY1}r___
Tx EMPTY

~
1'----+--....,

Tx READY
(STATUS BIT)

Tx READY
(PIN)

CIO
Wr SBRK

Tx DATA
DATA CHAR 1

DATA CHAR 2

'O-_NM~LC-"
"'>-

""

l;;c

EXAMPLE FORMAT = 7 BIT CHARACTER WITH PARITY & 2 STOP BITS.

Receiver Control & Flag Timing (ASYNC Mode)
,----<

BREAI( DETECT

~

-

OVERRUN ERROR
(STATUS BITI
RIIRDY

~

1

r:-IRIIRDY

CHAR2
LOST

1RdOATA
c/o

~'RKEn'

WrERR

1,--.

.u

V

>1
RIIDATA

DATA CHAR 2

~

~En

V

•

WrR~F7

~

,J

VJ.JJ.jJJJJ
EXAMPLE fORMAT

W.

>---DATA CHAR 3

,-

7 BIT CHAAACTER WITH PARITY & 2 STOP BITS.

202
- - - - - - - - ---------------

Transmitter Control & Flag Timing (SYNC Mode)

.~

CIO

1

t

~It

h READY
ISTATUS !lIT)

I

-=J-::'~
W,DATA

MARKING STATE

~

SYN~

DATA
CHAR 2

CHAR 1

,.

1"1, DATA

".

0'"

CHAR 1

•

".

0', "

W'COMMA'::ri
SBRK·

CHAR 4

AT~

SYNC CHAR 2

".

0'"

•

CDH:TRA~

CHAR 3

".

0"

J'

0"

'"

"

j

I
I

W, SBRK.
COMMA"

W. DATA
CHAR 3

~

tL

r-

f

W,()ATA

0"

r-~

\'I,DATA
CHAR S

MA~;\
STAn

STATE

DATA
CHAR ')

STATE

.,.

SYNC
CHAR

, , " ,

".

ETC

,," , ,"
'"

EXAMPLE FORMAT' S BIT CHARACTER WITH PARITY. 2 SYNC CHARACTERS

Receiver Control & Flag Timing (SYNC Mode)

~TE#~

SYNDET
{PIN) NOTE __ ,

'15_

tES_

~

SYNDET 15.BI

~

If-

t'--~

ERROR IS,B)

~;t

R. ROY IPINI

~~V'EH

Rd DATA
CHAR 1

R.E"

L

SYNC
CHAR 1

~VNC

DATA
CHAR 1

CHAR 2

l[)
CHAR :<'

>---DATA
CHAR3

\{;;I~!::'

.... i iTTTTTtT; ; ; i . W-Ui:iI,i±sT "1'1111' ' ,
NOTE
NOTE

['SOA;US L

EXIT HUNT MODE
SET SYNC DEl

Rd DATA

, , ':1,1' , , >).,

T

~
~

~

x •• x

~

203

DIAlA

DATA
CHAR 1

DON'T CARE
~

." ':').'
I
/

EXIT HUNT MODE!
sn SYN DET ISTATUS BIT)

INTERNAL SYNC, 2 SYNC CHARACTERS, S BITS, WITH PARITY
EXTERNAL SYNC, 5 BITS. WITH PARITY

r--

I'll. EHI;>

J~

JlI1IlM
L

t±

--

CHAR 1

CHAR 3

-V
DONT
CARE

"'~

I

r-

Ir

r---

fu

L Ir--

CHAR 2
~

0

,

CHAR ASSY
BEGINS

1JUl

2

"

.

M

SET SYNDET ISTATUS BITI

He

APPLICATION OF THE COM8251A

Asynchronous Serial Interface to CRT Terminal,
DC to 9600 Baud

Synchronous Interface to Terminal or Peripheral Device

SYNCHRONOUS

CDM8251A

RiC

OR PERIPHERAL

fie

DEVICE

SYNDET

Asynchronous Interface to Telephone Lines

Synchronous Interface to Telephone Lines

ADDRESS BUS

6SR
5'fR
CDM6251A

PHONE
LINE

PHONE
LINE
INTER
FACE

SYNC
MODEM

ffi
FiTS

FACE

R;c

T.C

TELEPHONE

TELEPHONE

LINE

COM8251A Interface tOJlP Standard System Bus
~----

ADDRESS BUS

"

\

~

CONTROL BUS

tiD R

IIOW

RESET

I

OATA BUS

c/o

os

D
07 Do

RD

WR

RESET

CLK

COM8251A

Circuit diagrams utilizing SMC products are included as a means of illustrating tYPical semiconductor applicacomplete information su~flcie~t for construction purposes is not necessarily glv.en. The
Information has been carefully checked and IS believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore. such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time In order to Improve deSign and supply the best product possible.

~Ions; c~nsequently

204

COM 9004

IBM 3274/3276
Compatible COAX Receiver/Transmitter
PIN CONFIGURATION

FEATURES
D Conforms to the IBM 3270 Interface Display
System Standard

D Transmits and Receives Manchester II Code
D Detects and Generates Line Quiesce, Code
Violation, Sync, Parity, and Ending Sequence
(Mini Code Violation)

Vee
GNO
TP

GNO
T10
T9

T9S
AOE

TBMT

DO
D1
D2
D3
D4
D5
D6
D7
A9
A10
SWE
AP
SCLK

D Multi Byte or Single Byte Transfers
D Double Buffer Receiver and Transmitter
D Separate Data and St'jtus Select
D Operates at 2.3587 11Hz
D TTL Compatible Inputs and Outputs
D COPLAMOS® n-Channel Silicon Gate
Technology

V",
GND

TOS
N/C'
DLOOP
TD

ffi
TC
AD
ALOOP

14
15
16
17

ASSE
BCLK
ADA
CVD
ATA

18
19

Vdd

20

MR

DA

'Internally connected. Not for external use.

GENERAL DESCRIPTION
The COM 9004 is an MOSILSI circuit which may be used
to facilitate high speed data transmission. The COM 9004
is fabricated using SMC's patented COPLAMOS® technology and may be used to implement an interface between
IBM 3274/3276 compatible control units and 3278/32871
3289 compatible terminal units. The receiver and transmitter sections of the COM 9004 are separate and may be used
independently of each other.

The COM 9004 generates and detects the line quiesce, code
violation, parity, and mini code violation bit patterns.
The on-chip parity logic is capable of generating and
checking either even or odd parity for the entire 10 bit data
word. In addition, parity may be generated for the least significant 8 bits of the data word (this parity bit would replace
the ninth data bit).

f5S

"""T9
TlO
TP

DO
01
03
0'
05
06
07

ROE
·R,
RlO
RTA
T8MT

OA

evo
'WE
BClK

SClK

205

ORGANIZATION
The COM 9004 is organized into 9 major sections. Communication between each section is achieved via internal
data and control busses.

transmit circuitry. It also generates the Line Quiesce, Code
Violation, sync bits and Mini Code Violation patterns.

Transmitter Shift Register

Transmitter Holding Register

The transmitter shift register is an 11 bit parallel to serial
shift register. It accepts data from the transmitter holding
register and the parity generation logic and converts it into
serial form for transmission.

The transmit holding register is a 12 bit latch. This latch is
loaded with the transmit data and parity generation information from the system bus.

Tri-State Buffers

Receive Control/Parity Check

These buffers allow gating of the COM 9004's status word
onto the system data bus.

This logic checks the received character for the specified
parity and ensures that no Transmit Check conditions
occurred. It also handles the self test mode and generates
a strobe when the complete data word is received.

Bus Transceiver
The bus transceiver allows bi-directional data transfer
between the system data bus and the transmit and receive
holding registers.

Receiver Shift Register
This logic is a serial to parallel shift register that converts
the received information into a 10 bit data word and RTA
status bit.

Parity Generator
Tilis logic determines and generates the correct parity for
the data in the transmitter holding register.

Receiver Holding Register
This register holds the assembled data word until it is read
by the processor.

Transmitter Control
This logic generates signals required to enable external

DESCRIPTION OF PIN FUNCTIONS
Processor Related Signals
PIN NO.
6-13

38

NAME
Transmit!
Receive Data
Bits
Transmit Bit 9
Select
Transmit Bit 9

39
3

Transmit Bit 10
Transmit Parity

T10

18

System Clock

SCLK

36

Transmitter
Data Strobe
Reset Data
Available
Status Word
Enable

TDS

4

26
16

SYMBOL
DO-D7

T9S
T9

TP'

RDA
SWE

23

Receive Data
Available

DA

25

Code Violation
Detected

CVD

37

Transmit Buffer
Empty
Receive Bit 9
Receive Bit 10
Receiver Turnaround

TBMT

14
15
24

5
17

'The SYNC bit

Receive Data
Enable
Receiver
Parity

IS

R9
R10
RTA

RDE
RP'

FUNCTION
Bidirectional: 8 bit, three state data port used to transfer data between the COM
9004 and the processor.
DO is the first bit transmitted.
Input: A low level on this pin enables T9 to be transmitted as bit 9. A high level on
this pin causes T9 to determine the type of parity bit generated for bits DO-D7.
Input: If T9S is low, this supplies transmit bit 9. If T9S is high, then T910w forces
odd parity and T9 high forces even parity to be generated for DO-D7. In this case
the parity bit generated is transmit bit 9.
Input: This pin supplies transmit bit 10.
Input: This input controls the parity bit for transmit bits 1-10. A low level on this pin
causes odd parity and a high level on this pin causes even parity to be generated
for bits 1-10. The parity bit generated is transmit bit 11.
Input: This signal is used to synchronize the COM 9004. The transmitter is loaded
and started on the low to high transition of SCLK if TDS is low. DA is reset on the
low to high transition of SCLK if RDA is low.
Input: This input and SCLK are used to load the transmitter holding register and
start the transmit sequence. Code Violation Detect (CVD) is reset at this time.
Input: This input and SCLK are used to reset DA.
Input: A low level at this pin enables the status word buffer outputs (DA, CVD,
TBMT, R9, R10, and RTA). A high level on SWE places the status word buffer
outputs in a high impedance state.
This three-state output signal is at a high level when an entire word has been
received and transferred into the receiver buffer register. It is only set if a Transmit
Check Condition did not occur.
This three-state output signal is at a high level if a valid Code Violation was
detected at the receiver since the last time the transmitter was loaded. It is reset
when the transmitter is loaded.
This three-state output signal is at a high level when the transmit holding register
may be loaded with new data.
This three-state output signal is receiver data bit 9.
This three-state output signal is receiver data bit 10.
This three-state output signal is set to a high level when a valid Mini Code
Violation is detected. It is only set if a Transmit Check did not occur. It is reset
when the transmitter is loaded.
Input: A low level enables the outputs of the receive data register DO-D7.
Input: This input determines whether the entire received word will be checked for
even or odd parity. A low at this pin will cause a check for odd parity and a high at
this pin will cause a check for even parity. This input has an internal pull-up
resistor.

Included In panty checking.

206

---------------------------------------------------------------

DESCRIPTION OF PIN FUNCTIONS (cont.)
29

NAME
Analog
Loopback

SYMBOL
ALOOP

34

Digital
Loopback

DLOOP

21

Master Reset

PIN NO.

1
22
19
2,20,40

Supply Voltage
Supply Voltage
Supply Voltage
Ground

MR

V"
Vdd
Vbb
GND

FUNCTION
Input: A low level on this pin disables the receiver except when the transmitter
is active. A high level on this pin and DLOOP will cause the receiver to be
disabled while the transmitter is active.
ALOOP is used to allow loop-back through the line drivers and receivers. This
input has an internal pull-up resistor.
Input: A low level on this pin disables the receiver except when the transmitter
is active. TG is forced to a high level to disable the external coax driver. Data
input to the receiver is internally wrapped from the transmitter data output.
This input has an internal pull-up resistor.
Input: This input should be pulsed low after power-on. This signal resets DA to
a low level and sets TG and TBMT to a high level. This input has an internal
pull-up.
+ 5 volt supply
+ 12 volt supply
-12 volt supply
GROUND

Device Related Signals
PIN NO.

27

NAME
Baud Rate
Clock

SYMBOL
BCLK

33

Transmit Data

TD

31

Transmit Clock

TC

30
32

Receive Data
Transmit Gate

RD
TG

28

Receive
Single Shot
Enable

RSSE

FUNCTION
This input is a clock whose frequency is 8 times the desired transmitter and
receiver baud rate (typically 18.8696 MHz for 3274/3276 operation). This input
is not TTL compatible.
Output: Serial data from the transmitter. This signal is a biphase Manchester II
encoded bit stream. This output is high when no data is being transmitted.
The Transmit Clock output is '/2 the frequency of BCLK. It is synchronized with
TD and used to provide external pre-distortion timing.
Input: Accepts the serial biphase Manchester II encoded bit stream.
Output: This signal is low during the time that the transmit data is valid. TG is
used to turn on the external transmit circuitry.
Input: A high level on this pin enables an internal digital single shot on RD. This
limits a high level on RD to 3 clock times. Also when high it will cause the
receiver not to detect a valid Code Violation. A low level disables the single shot
causing no reshaping of the RD input signal.

COM 9004 OPERATION
The COM 9004 consists of a receiver section that converts
Manchester II phase encoded serial data to parallel data
and a transmitter section that converts parallel data to
Manchester II phase encoded serial data.

after a line Quiesce, Code Violation and sync bit have been
detected by the receiver. It is reset when the transmitter of
the COM 9004 is asserted. By examining this signal, the
processor can determine whether a timeout or Transmit
Check condition caused a receiver error.

Receiver

The received message is checked for the Code Violation
sequence (start sequence) bit pattern, preceding the first
data word, and Mini Code Violation (end sequence)
following the last data word.

The receive input is sampled at 8 times the data rate. The
receiver logic is brought into bit synchronization during the
Line Quiesce pattern. Once the Code Violation following
the Line Quiesce is detected, the receiver is brought into bit
and word synchronization. The internal receiver clock is
adjusted after each transition to compensate for jitter and
distortion in the received data signal.

The data word consists of 10 data bits, a sync bit and a parity bit. Receiving data in multiple byte format is functional
only when even parity is selected.

Transmitter

Message transfers must conform to the IBM 3270 protocol
in order for the COM 9004 to acknowledge them.

The transmitter section basically consists of a 12-bit holding
register, parallel to serial shift register and a parity generator.
The firmware initiates a transmit sequence by strobing TDS
low. The data is loaded into the holding register on the rising
edge of SCLK while TDS is low. Nine bits of data (DO-D7
and T10) are transferred without change to the transmit shift
register. The logic level of T9S determines whether T9 will be
transmitted as parity on the preceding eight bits, or as data.

The data word along with the first bit of the next word or ending zero (bit 13) is shifted into a shift register. Once it is
assembled it is transferred and held in the holding register
until another data word is assembled.The 13th bit is inverted
and presented to the bus or RTA (receiver turn-around).
Therefore RTA is set high on the last word of a message
and is reset when the transmitter is loaded with the
response.

After the processor loads the transmit holding register with
data, status signal TBMT is driven inactive low until the COM
9004 transfers the data from the transmit holding register
to the transmit shift register. After the transfer, TBMT is driven

Once the data word is in the holding register and parity is
correct the data available (DA) status signal is set high.
The Code Violation Detect signal (CVD) goes active high

207

Diagnostic Modes

high. The processor should not try to load data into the COM
9004 while TBMT is low. When initiating a data transmission,
the COM 9004 automatically transmits a Line Quiesce
pattern and a Code Violation. The data is then shifted out
of the shift register with a sync bit (1) inserted before the
data word, and a parity bit appended after the data word.

NORMAL OPERAT]ON (ALOOP AND DLOOP HIGH)
Internal read data signal follows the RD input as long as the
COM 9004's transmitter is off. The receiver will be disabled
while the transmitter is active.
ANALOG LOOPBACK (ALOOP LOW AND DLOOP HIGH)
The internal read data signal follows the RD input as long
as the COM 9004's transmitter is active.

If a new word is loaded into the COM 9004 before the parity
bit of the previous word has been transmitted, a sync bit (1)
followed by the new data bits is transmitted. If not, after the
COM 9004 transmits the last data word (no more transmit
sequences are started), a sync bit (0) and a Mini Code
Violation is appended to the end of the message.

DIGITAL LOOPBACK ALOOP HIGH AND DLOOP LOW)
The internal read data signal follows an internally generated
and latched valid transmit signal (only when the transmitter
is active.) The output TG is disabled in digitalloopback mode.

Output TG goes active low one-half bit cell time before the
first Line Quiesce character is output. It is made inactive
(high) during the transmission of the Mini Code Violation.

DISABLE RECEIVER (ALOOP AND DLOOP LOW) _
The internal read data signal is held low and output TG
is disabled.

MESSAGE FORMATS

CODE
VIOLATION

ENDING
SEQUENCE

CODE
VIOLATION
SYNC
BIT

SYNC
BIT
DATAN
(10 BITS)

Bits on the coax appear as positive and negative going
pulses. A positive pulse to negative pulse transition in the
middle of the bit cell is interpreted as a logical '0'. A negative
pulse to positive pulse transition in the middle of a bit cell is

PARITY
BIT

ENDING
SEQUENCE

interpreted as a logical '1'. A predistortion pulse is generated
for every pulse transition from an up to down level or a down
to up level.

Line Quiesce Pattern

I
1
1
1
1

I

I

1__ 1

1

I

1
1
1

1
1
1
1
1

one bit
time

I
1
1

I
I_-I
I

1

1

I

I

1

1 __ 1

The Line Quiesce pattern consists of five contiguous logical
ones. It establishes an equilibrium condition on the coax
following line turnaround.

208

Code Violation Pattern

1

1
1

1
1

__ I

__ I

1

1

1

I

1

1

1

1

1

1

1

1

1
1_ _ 1
I

1
1
1

I

1

I

1_ _ _ _ 1

1
last "1"
of linequiesce

I

I

1

I-code

violation

1

sync bit

The Code Violation pattern is a bit sequence containing
no mid-bit time level transition in two of its three bit
cells. It is a unique pattern that violates the encoding
rules and indicates the start of valid data.

Mini Code Violation Pattern

bit times:

11

1

12

0

p

2
mcv

"1 "
or
"0"

last data
byte

Ending Sequence

The Mini Code Violation (MCV) pattern is a bit
sequence containing no mid-bit time level transition
in either of its bit cells. It is a unique code that violates
the encoding rules and indicates the end of valid
transmit data.

Transmit Check
A Transmit Check is defined as follows:
1) A logical zero sync bit in the ending sequence not
followed by a Mini Code Violation.
2) Loss of a level transition at the mid-bit time during
other than a normal ending sequence.
3) A transrnission parity error.

209

3
mcv

I

MAXIMUM GUARANTEED RATINGS'
. . . . . . .. O°C to + 70'C
. ..................... - 55' to + 150'C
.............. .
. ..... +300'C
................
.. ..... + 18.0V
. ....... -0.3V

Operating Temperature Range .... .
Storage Temperature Range .... .
Lead Temperature (soldering, 10 sec.) ................... .
Positive Voltage on any I/O Pin, with respect to ground ...... .
Negative Voltage on any I/O Pin, with respect to ground .... .

'Stresses abo,v~ those listed may cause permanent damage to the device. This is a stress rating only and lunctional operation of the
device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not
be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power
is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. For example, the bench
power supply programmed to deliver + 12 volts may have large voltage transients when the AC power is switched on and off. If this
possibility exists it is suggested that a clamp circuit be used.
DC ELECTRICAL CHARACTERISTICS (TA= O'Cto 70'C, Vee = +5V ±5%, VDD = + 12V ±5%, VBB = -12V ±5%)
PARAMETER
DC CHARACTERISTICS
INPUT VOLTAGE LEVELS
VILLow
V,H High
V,H High
V'HHigh
OUTPUT VOLTAGE LEVELS
VDLLow
VOH High

MIN

TYP

-0.3
2.0
4.3
3.0

MAX

UNIT

.8
Vee
Vee + .3
Vee + .3

V
V
V
V

(Except BCLK, MR)
(BCLKonly)
MRonly

.4

IOL=2.0 mA
10H= - .25 mA

2.4

POWER SUPPLY CURRENT
Icc
IDD
IBB
INPUT LEAKAGE CURRENT
All inpui pins

70
16
5

CAPACITANCE
C'N
C'N

COMMENTS

mA
mA
mA

All outputs = V aH

.01

mA

V,N = Oto Vee

10
35

pf
pf

(Except BCLK)
(BCLKonly)

AC ELECTRICAL CHARACTERISTICS (TA = O°C to 70'C, Vee = +5V ±5%, VDD = + 12V ±5%, V BB = -12V ±5%)
PARAMETER
Clock Frequency
BCLK
SCLK

Clock Width
SCLK High
tSKH
SCLK Low
tSKL
BCLK High
tBKH
BCLKLow
tBKH
t,
BCLK rise time
BCLK fall time
tF
~ to Data Valid Delay
tROD
SWE to Data Valid Delay
t500
tDF Data Read to Bus Float
t DS Data Setup Time
tDH Data Hold Time
DA to receive data
tDAV
valid delay
tTe TC clock period
tTCLD TC to TG low delay
tTCHD TC to TG high delay
tTDS Transmit data to TG
setup time
tTOH Transmit data to TC
hold time
TBMT active to de-active
tD
t aDe TBMTcycie
tDD TBMT de-activated
toss TDS set up
TDS hold
tOSH
tMR MR pulse width

MIN

TYP

MAX

UNIT

7
DC

18.8696
4.7474

18.9
5

MHz
MHz

6
6
50
50
50

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

80
80
20
20

100
10
-100

100
106

-53

30
30

10
20

ns
ns
ns
ns
ns

200
3.2
2
200
100

1
100
10
300

210

ns
j.lS
j.ls
ns
ns
ns

CONDITIONS

TIMING DIAGRAMS

MISC. TIMING

BUS INPUT TIMING

SCLK

BCLK

I

toss

TDS/RDA*

tOH

MR

I---tos
DATA

RECEIVE DATA TIMING

VALID DATA

T~

A

OA _ _ _ _ _ _ _

I
tOAV'"

00-07,
R9, R10

1

~

---~~

'should include only one rising edge
of SCLK within this pulse.

VALID DATA

BUS OUTPUT TIMING

*OA may occur from 100 ns before to 100 ns after data is valid.

RDE

TRANSMITTER TIMING

SWE

TG

TO

1""'1.0-----1

..11

BIT CELL - - - - - ;•

DATA,
STATUS
VALID

tsoo

------~<~------~>---

TBMT CYCLE
TBMT

..J

I:---too~

\""....-----tooc

211
----

..

-~--

... \

r:

•

~

a
en
O~

,

L>25

J

~

aUJ

~

a:

a

rz:ii
(')'7

2:

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a
U

W

I-

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X


ZI

a

en

~

a:

a::

a:

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(j)

L{)

Z

a:

::;;
~

0

0:

w

U

N
N

rio
f-Z

UJe;:

~o

:::>f-

o...~
~(/)

.. UJ

'-a:

1-1
~-I

f-

>-0>

0:<1:>

uro
ro

0
a
....
..".

STANDARD MICROSYSTEMS
CORPORATION 5~!iiii~
35 Marcus B,vd Hauppa210:
:lTIO a !::I~I~
z ~ Iii: ~ ~ « ~ ~ « ~
(fJ

I...J

NIC
AD,
AD,
ADs
AD,
AD,
GND
CLK
ILE
WE
DE

ET2
CA
ET'
TEST2
TEST'
DWR

'-../

RNi
lOR EO
MREO
AS
REO
WAIT
AlE
ADIE

[

5E

WE
lIT
ClK
GND

10
9
0
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

POR
Vee
RX

TX
DSYNC
A8
IDDAT
IDlD
A9
A'O
ECHO
INTR
ADO
AD'
AD2
AD3
AD4
AD5
AD6
AD7

Q::E

PACKAGE: 44·pin PLCC

PACKAGE: 40·pin DIP

GENERAL DESCRIPTION
The COM 9026 is a special purpose communications adapter
for interconnecting processors and intelligent peripherals
using the ARCNET local area network. The ARCNET local
area network is a self-polling "modified token passing" network operating at a 2.5 M bit data rate. A "modified token
passing" scheme is one in which all token passes are
acknowledged by the node accepting the token. The token
passing network scheme avoids the fluctuating channel
access times caused by data collisions in so-called CSMAI
CD schemes such as Ethernet.

The COM 9026 establishes the network configuration, and
automatically re-configures the network as new nodes are
added or deleted from the network. The COM 9026 performs address decode, CRC checking and generation, and
packet acknowledgement, as well as other network management functions. The COM 9026 interfaces directly to the
host processor through a standard multiplexed address!
data bus.
An external RAM buffer of up to 2K locations is used to hold
up to four data packets with a maximum length of 508 bytes
per message. The RAM buffer is accessed both by the processor and the COM 9026. The processor can write commands to the COM 9026 and also read COM 9026 status.
The COM 9026 will provide all signals necessary to allow
smooth arbitration of all RAM buffer operations.

The COM 9026 circuit contains a microprogrammed sequencer and all the logic necessary to control the token
passing mechanism on the network and send and receive
data packets at the appropriate time. A maximum of 255
nodes may be connected to the network with each node
being assigned a unique ID.

• ARCNET is a registered trademark of the Datapoint Corporation.

213

CA

CLOCKS

ClK

AND

DSYNC
POR

SYNCHRONIZATION

~·5V

~GND

TX

RX

'--_ _ _ _ _-J'\j 8

INTERNAL
BUS

WORKING
REGISTERS

ET1
ET2

r--L.L-~~~_Iolo

ECHO
TESTl
TEST2

IDDAT

INTR
IOREO
MREO

AS
DWR

AlYIE AlE

ILE L WE OE

COM 9026 BLOCK DIAGRAM
INT--~-----r=========!-----------r~'N~T;R--------~
10REa

PA15-8

MREO

DWR

RJW

AlO-8
AS -

......- -....~

A07·0

PAD7-0

WAIT

--~--1

WAIT

DE WE

REO

RD

A10-8

0107-0

RAM BUFFER DE
WE

FIGURE 2-TYPICAL COM 9026 INTERFACE
214

DESCRIPTION OF PIN FUNCTIONS (refer to figure 2)
NAME
DIP PIN NO.
31,32,35 ADDRESS 10,
9,8

SYMBOL
A10,A9, A8

21,22,23,
24,25,26,
27,28
8

ADDRESS/
DATA 7-0
I/O REQUEST

10REQ

9

MEMORY
REQUEST

MREQ

7

READ/WRITE

10

ADDRESS
STROBE

AS

11

REQUEST

REQ

12

WAIT

WAIT

6

DELAYED
WRITE

DWR

29

INTERRUPT
REQUEST

INTR

18

INTERFACE
LATCH
ENABLE

ILE

14

ADDRESS/
DATA INPUT
ENABLE
ADDRESS
INPUT
ENABLE
LATCH

ADIE

13

15

17

AD7-ADO

R/W

AlE

This output signal enables the processor's upper 3 address bits (PA 10-PA8) onto
the interface address bus (IA1O-IA8).

L

This output signal latches the interface address/data bus (IAD7 -IADO) into a latch
which feeds the lower 8 address bits of the RAM buffer during address valid time
of all RAM buffer access cycles.
This output signal is used as a write pulse to the external RAM buffer. Data is referenced to the trailing edge of WE.
This output signal enables the RAM buffer output data onto the interface
address/data bus (IAD7-IADO) during the data valid portion of all RAM buffer
read operations.
This output signal synchrOnously loads the value selected by the 10 switches into
an external shift register in preparation for shifting the 10 into the COM 9026. The
shift register is clocked with the same signal that feeds the COM 9026 on pin 19
(CLK). The timing associated with thi~ signal and IDDAT (pin 34) is illustrated in
figure 19.
This input signal is' the serialized output from the external 10 shift register. The 10
is shifted in most significant bit first. A high level is defined as a logic"1".
The levels on these two input pins specify the timeout durations used by the COM
9026 in its network protocol. Refer to the section entitled "Extended Timeout
Function" for details.

WRITE
ENABLE
OUTPUT
ENABLE

WE

33

10 LOAD

IDLD

34

10 DATA IN

1,3

EXTENDED
TIMEOUT
FUNCTION 2,
1
TRANSMIT
DATA
RECEIVE
DATA

16

37
38

FUNCTION
These three output signals are the three most significant bits of the RAM buffer
address. These signals are in their high impedance state except during COM
9026 access cycles tothe RAM buffer. A10 and A9 will take on the value nn as
specified in the ENABLE RECEIVE or ENABLE TRANSMIT commands to or
from page nn and should be viewed as page select bits. For packets less than
256 bytes a 1K buffer can be used with A8 unconnected. For packets greater
than 256 bytes, a 2K buffer is needed with A8 connected.
These 8 bidirectional signals are the lower 8 bits of the RAM buffer address and
the 8 bit data path in and out of the COM 9026. ADO is also used for I/O command
decoding of the processor control or status commands to the COM 9026.
This input signal indicates that the processor is requesting the use of the data bus
to receive status information or to issue a command to the COM 9026. This signal
is sampled internally on the falling edge of AS.
This input signal indicates that the processor is requesting the use of the data bus
to transfer data to or from the RAM buffer. This signal is sampled internally on the
falling edge of AS.
A high level on this'input signal indicates that the processor's access cycle to the
COM 9026 or the RAM buffer will be a read cycle. A low level indicates that a
write cycle will be performed to either the RAM buffer or the COM 9026. The write
cycle will, not be compjeted, however, until the DWR input is asserted. This signal
is an internal transparent latch gated with AS.
This input signi!! is used by the COM 9026 to sample the state of the 10REQ,
MREQ and R/W inputs. The COM 9026 bus arbitration is initiated on the falling
edge of this signal.
This output signal 'acknowledges the fact that the proc.essor's I/O or memory
cycle has been sampled. The signal is equal to MREQ or 10REQ passed through
an internal transparent latch gated with AS.
This output signal is asserted by the COM 9026 at the start of a processor access
cycle to indicate that it is not ready to transfer data. WAIT returns to its inactive
state when the COM 9026 is ready for the processor to complete its cycle.
This input signal informs the COM 9026 that valid data is present on the processor's data bus for write cycles. The COM 9026 will remain in the WAIT state until
this signal is asserted. DWR has no effect on read cycles. If the processor is able
to satisfy the write data setup time, it is recommended that this signal be
grounded.
This output signal is asserted when an enabled interrupt condition has occured.
INTR returns to its inactive state by resetting the interrupting status condition or
the corresponding interrupt mask bit.
This output signal, in conjunction with ADIE, gates the processor's address/data
bus (PAD7-PADO) onto the interface address/data bus (IAD7-IADO) during the
data valid portion of a Processor Write RAM or Processor Write COM 9026
operation.
This output signal enables the processor's address/data bus (PAD7-PADO) captured by AS or ILE onto the interface address/data bus (IAD7 -IADO).

OE

IDDAT
ET2, ET1

TX
RX

This output signal contains the serial transmit data to the CABLE
TRANSCEIVER.
This input signal contains the serial receive data from the CABLE
TRANSCEIVER.

215

DESCRIPTION OF PIN FUNCTIONS (Continued)
PINNa.
4,5

30

, NAME
TEST PIN 2
TEST PIN 1

19

ECHO
DIAGNOSTIC
ENABLE
CLOCK

2

CA

36

DELAYED
SYNC
POVVER ON
RESET

40

39
20

+.5 VOLT
SUPPLY
GROUND

SYMBOL
TEST2
TEST1
ECHO

ClK
CA

DSYNC
paR

Vee
GND

FUNCTION
These input pins are grounded for normal chip operation. These pins are used in
conjunction with ET2 and ET1 to enable various internal diagnostic functions
when performing chip level testing.
\A(hen this input signal is low, the COM 9026 will re-transmit all messages of
lengtH less than 254 bytes. This input should be tied high for normal chip operation and is only utilized when performing chip level testing.
A. continuous 5 MHz clock input used for timing of the COM 9026 bus cycles, bus
arbitration, seriallD input, and the internal timers.
This input signal is a 5 MHz clock used to control the operation of the COM 9026
microcoded sequencer. This input is periodically halted in the high state by the
DSYNC output.
This output signal is asserted by the COM 9026 to cause the external clock generator logic to halt the CA clock. Refer to figure 9.
This input signal clears the COM 9026 microcoded sequencer program counter
to zero and initializes various internal control flags and status bits. The paR status bit is also set which causes the INTR output to be asserted. Repeated assertion of this signal will degrade the performance of the network.
Power Supply
Ground

PROTOCOL DESCRIPTION
character which is the 2's complement of the number
of data bytes to follow if a "long packet". is being sent.
-N data bytes where COUNT = 256-N (512-N for a
"long packet")
-two CRC (Cyclic Redundancy Check) characters. The
CRC polynomial used is X'6 + X15 + X2 + 1.

LINE PROTOCOL bESCRIPTION
The lihe protocol dm be described as isochronous because
each byte is preceded by a start interval and ended with a
stop interval. Unlike asyncHronous protocols, there is a constant amount 9ftime separating each data byte. Each byte
will take up exactly i 1 clock intervals with a single clock interval being 400 n\'lnoseconds in dlJratidn. As aresult, 1 byte is
transmitted every 4.4 microseconds and the time to transmit
a message can be exactly determined. fhl;! line idles in a
spacing (logic 0) condition. A logic '0' is defined as noJirie
activity and a logic 1 is defined as a pulse of 200 na,noseconds
duration. A transnilssion starts with an ALERT BURST consisting of 6 unit intervals of mark (logic 1). Eight bil data characters are then sent with each character preceded by 2 unit
intervals of mark ~lid one unit interval of space. Five types of
transmission Can be sent as described below:

Acknowledgements
An ALERT BURST followed by one character; an ACK
(ACKnowledgement-ASCII code 86 H EX) character. This
message is used to acknowledge reception of a packet
or as an affirmative response to FREE BU FFER
ENQUIRIES.

Negative Acknowledgements
An ALERT BURST followed by one character; a NAK (Negative AcKnowledgement-ASCII code 15 HEX). This message is used as a negative response to FREE BUFFER
ENQUIRIES.

Invitations To Transmit
An ALERT BURST foliowed by three characters; an EaT
(end of transmission-ASCII code 04 HEX) and two
(repeated) DID (Destination IDentification) characters. This
message is used to pass the token from one node to another.

NETWORK PROTOCOL DESCRIPTION
Communication on the network is based on a "modified token
passing" protocol. A "modified token passing" scheme is
one in which all token passes are acknowledged by the node
receiving the token. Establishment of the network configuration and management of the network protocol are handled eniirely by the COM 9026's internal microcoded
sequencer. A processor or intelligent peripheral transmits
data by simply loading a data packet and its destination ID
into the RAM buffer, and issuing a command to enable the
transmitter. When the COM 9026 next receives the token,
it verifies that the. receiving node is ready by first transmitting a FREE BUFFER ENQUIRY message. If the receiving
node transmits an ACKnowledge message, the data packet
is transmitted followed by a 16 bit CRC. If the receiving node
cannot accept the packet (typically its receiver is inhibited),
it transmits a Negative AcKnowledge message and the
transmitter passes the token. Once it has been established
that the receiving node can accept the packet and transmission is complete, the receiving node will verify the packet.

Free Buffer Enquiries
An ALERT BURST followed by three characters; an
ENQ (ENQuiry-ASCII code 85 HEX) and two (repeated)
DID (Destination IDentification) characters. This message
is used to ask ahoiher node if it is able to accept a packet
of data.

Data Packet,s
An ALERT BURST followed by the following characters:
- an SOH (start of header-ASCII code 01 HEX)
-a SID (Source IDentification) character
-two (repeated) DID (destination IDentification)
characters.
-a single COUNT character which is the 2's complement of !tie number of data bytes to follow if a "short
packet" is being sent or 00 HEX followed by a COUNT
216

If the packet is received successfully, the receiving node
transmits an acknowledge message (or nothing if it is
received unsuccessfully) allowing the transmitter to set the
appropriate status bits to indicating successful or unsucessful delivery of the packet. An interrupt mask permits
the COM 9026 to generate an interrupt to the processor when
selected status bits become true. Figure 3 is a flow chart
illustrating the internal operation of the COM 9026.

microseconds, the COM 9026 increments the NID value and
transmits another INVITATION TO TRANSM IT using the new
NID equal to the DID. If activity appears before the 74.7
microsecond timeout expires, the COM 9026 releases control of the line. During NETWORK RECONFIGURATION,
INVITATIONS TO TRANSMIT will be sent to all 256 possible ID's. Each COM 9026 on the network will finally have
saved a NID value equal to the 10 of the COM 9026 that
assumed control from it. From then until the next NETWORK RECONFIGURATION, control is passed directly
from one node to the next with no wasted INVITATIONS TO
TRANSMIT sent to ID's not on the network. When a node
is powered off, the previous noqe will attempt to pass it the
token by issuing an INVITATION TO TRANSMIT. Since this
node will not respond, the previous node will time out and
transmit another INVITATION TO TRANSMIT to an incremented 10 and eventuallY 9 re~ponse' will be received.

NETWORK RECONFIGURATION
A significant advantage of the COM 9026 is its ability to adapt
to changes on the network. Whenever a new node is activated or deactivated a NETWORK RECONFIGURATION
is performed. When a new COM 9026 is turned on (creating
a new active node on the network), or if the COM 9026 has
not received an INVITATION TO TRANSMIT for 840 milliseconds, it causes a NETWORK RECONFIGURATION by
sending a RECONFIGURE BURST consisting of eight marks
and one space repeated 765 times. The purpose of this burst
is to terminate all activity on the network. Since this burst is
longer than any other type of transmission, the burst will
interfere with the next INVITATION TO TRANSMIT, destroy
the token and keep any other node from assuming control
of the line. It also provides line activity which allows the COM
9026 sending the INVITATION TO TRANSMIT to release
control of the line.

The time required to do a N~TWORK RECONFIGURATION depends on the number of nodes in the network, the
propogation deiay between nodes and the highest 10
nt.lmber on network but will pe in the range of 24 to 61
milliseconds.

BROADCAST MESSA~ES
Broadcasting gives a particular node the ability to transmit
a data packet to all nodes on the network simultaneously.
10 zero is reserved for this feature and no node on the network can be assigned 10 zero. To broadcast a message,
the tran!lmitting node's processor simplY. loads the RAM
buffer with the data packet and sets the destination 10 (DID)
equal to zero. Figure 8 illustrates the position of each byte
in the packet with the DID residing at address 01 HEX of .
the current page selected in the TRANSMIT command. Each
individual nodI'! has the ability to ignore broadcC!st messages by s~tting the most signficant ~it of the ENABLE
RECEIVE TO PAGE nn command (see "WRITE COM 9026
COMMANDS") to a logic zero.

When any COM 9026 sees an idle line for greater than 78.2
microseconds, which will only occur when the token is lost,
each COM 9026 starts an internal time out equal to 146
microseconds times the quantity 255 minus its own 10. It
also sets the internally stored NID (next 10 representing the
next possible 10 node) equal to its own 10. If the timeout
expires with no line activity, the COM 9026 starts sending
INVITATIONS TO TRANSMIT with the DID equal to the
currently stored NID. Within a given network, only one COM
9026 will timeout (the one with the highest 10 number). After
sending the INVITATION TO TRANSMIT, the COM 9026
waits for activity on the line. If there is no activity for 74.7

COM 9026 OPERATION
BUFFER CONFIGURATION

of buffer location 02 is zero or non zero. During a receive
sequence, the COM 9026 stores data in the receive buffer,
also a 256 (or 512) byte segment of the RAM buffer. The
processor I/O commanq which enables either the COM 9026
receiver or the COM 9026 transmitter also initializes the
respective buffer page register. The formats of the buffers
(both 256 and 512 byte) are shown below.

During a transmit sequence, the COM 9026 fetches data
from the Transmit Buffer, a 256 (or 512) byte segment of the
RAM buffer. The appropriate buffer size is specified in the
DEFINE CONFIGURATION command. When long packets are enabled, the COM 9026 will interpret the packet as
a long or short packet depending on whether the contents

FIGURE 8RAM BUFFER
PACKET
CONFIGURATION

ADDRESS

COUNT

FORMAT
SID
DID
COUNT - 256 N
NOT
USED
DATA BYTE 1
DATA BYTE 2

ADDRESS

i
1

FORMAT
SID
DID

1

-I

COUNT" 512

I
I

N

NOT
USED

1

I
I

•

I

255

DATA BYTE N

I

511

NOT
USED

COUNT

DATA BYTE 1
DATA BYTE 2

~YTEN=1---1

511

SHORT PACKET
(256 OR 512 BYTE PAGE)

DATA BYTE N·1
DATA BYTE N
LONG PACKET
(512 BYTE PAGE)

217

N" DATA PACKET LENGTH
SID = SOURCE ID
DID - DESTINATION ID
(0 FOR BROADCASTS)

POWER ON

~~______~CACK ~~----------------~

• The ID set by the external switches is continually sampled during COM 9026 operation
- ID refers to the identification number assigned to this node
- NID refers to the next identification number receiving the token from this ID
- SID = source identification
- DID = destination identification
- SOH = start of header character; preceeds all data packets

FIGURE 3-9026 OPERATION

218

PROCESSOR INTERFACE

will also use the interface bus (IA 1O-IAB, IAD7-IADO) when
performing 1/0 access cycles (status reads from the COM
9026 or command writes to the COM 9026).

Figure 2 illustrates a typical COM 9026 to processor interface. The signals on the left side of this figure represent typical processor signals with a 16 bit address bus and an B bit
data bus with the data bus multiplexed onto the lower B
address lines (PAD7-PADO). The processor sees a network node (a node consists of a COM 9026, RAM buffer,
cable transceiver, etc. as shown in figure 2) as 2K memory
locations and 4 1/0 locations within the COM 9026.

To accomplish this double buffering scheme, the RAM buffer
must behave as a dual port memory. To allow this RAM to
be a standard component, arbitration and control on the
interface bus (IA1O-IAB, IAD7-IADO) is required to permit
both the COM 9026 and the processor access to the RAM
buffer and, at the same time, permit all processor 1/0 operations to or from the COM 9026.

The RAM buffer is used to hold data packets temporarily
prior to transmission on the network and as temporary storage of all received data packets directed to the particular
node. The size of the buffer can be as large as 2K byte locations providing four pages at a maximum of 512 bytes per
page. For packet lengths smaller than 256 bytes, a 1K RAM
buffer can be used to provide four pages of storage. In this
case address line lAB (sourced from either the COM 9026
or the processor) should be left unconnected. Since four
pages of RAM buffer are provided, both transmit and receive
operations can be double buffered with respect to the processor. For instance, after one data packet has been loaded
into a particular page within the RAM buffer and a transmit
command for that page has been issued, the processor can
start loading another page with the next message in a multimessage transmission sequence. Similarly, after one message is received and completely loaded into one page of
the RAM buffer by the COM 9026, another receive command can be issued to allow reception of the next packet
while the first packet is read by the processor. In general,
the four pages in the RAM buffer can be used for transmit
or receive in any combination. In addition, the processor

Processor access cycle requests begin on the trailing edge
of AS if either 10REQ or MREQ is asserted. These access
cycles run completely asynchronous with respect to the COM
9026. Because of this, upon processor access cycle
requests, the COM 9026 immediately puts the processor
into a wait state by asserting the WAlT output. This gives
the COM 9026 the ability to synchronize and control the
processor access cycle. When the processor access cycle
is synchronized by the COM 9026, the WAIT signal is eventually removed allowing the processor to complete its cycle.
For processor RAM buffer access cycles, AlE and ADIE
enable the pro1\essor address captured during AS time onto
the )!lterface address bus (IA 1O-IAB, IAD7-IADO). The signal L will capture the B least significant bits of this address
(appearing on IAD7-IADO) before the data is multiplexed
onto it. At the falling edge of L, a stable address is presented to the RAM buffer. For read cycles, OE allows the
addressed RAM buffer data to source the interface addressl
data bus (IAD7-IADO). In figure 2, this information is passed
into a transparent latch gated with WAIT. At the falling edge
of WAIT, the data accessed by the processor is captured

~ooo

CLK~

As~lr------------------------------~l~
l~
:~'---_

PA15.S===x'HIADDR
PAD7·0

MFfEQ

==XLo ADDR qlr-____-'X
=m\

RD _ _ _ _ _ _
IA10·S

anI

:t=no

~~rl---------------\--------------------_4I~l---------

---------'lll----<

HI ADDR

,-tl

>----<

H

l~

- - - - - - - - 4\~

~~l- - - - - -

}--<'----!t~u,-,-,-_ __

IAD7.0--------4\~ RAM

ADIE

RAM Do",

\'---______----.J~I
\'---______~~l--------

I

\

I

Ir-----------------------~l~t----------

FIGURE 4-PROCESSOR READ RAM FOLLOWED BY COM 9026 READ RAM
219

and driven out via the logic function RD anded with REO.
For Q!Q.cessor 110 read cycles from the COM 9026, ADIE
and AlE are used to enable the processor address into the
COM 9026. Data out of the COM 9026 is gated through the
transparent latch and appears on the processor's data bus
with the same control signals used for RAM read cycles.

As stated previously, processor requests occur at the failing edge of AS if either 10REO or MREO are active. COM
9026 requests occur when the transmitter or receiver need
to read or write the RAM buffer in the course of executing
the command. If the COM 9026 requests a bus cycle at the
same time as the processor, or shortly after the processor,
the COM 9026 cycle will follow immediately after the processor cycle. Figure 4 illustrates the timing relationship of
a Processor RAM Read cycle followed by a COM 9026 RAM
read cycle. Once the AS signal captures the processor
address to the RAM buffer and requests a bus cycle, it takes
4 ClK periods for the processor cycle to end. Figure 4 breaks
up these 4 ClK periods into 8 half clock interval labeled 1P
through 8P. A COM 9026 access cycle will take 5 ClK periods
to end. Figure 4 breaks up these 5 ClK periods into 10 half
intervals labeled 1C through 1DC.

For processor write cycles, after the falling edge of L, the
COM 9026 produces a WE (write enable) output to the RAM
buffer, and the IlE output from the COM 9026 allows the
processor data to source the interface address/data bus
(IAD7-IADO). At this time the COM 9026 waits for DWR
before concluding the cycle by removing the WAIT output.
DWR should only be used if the processor cannot deliver
the data to be written in enough time to satisfy the write setup
time requirements of the RAM buffer. By delaying the activation of DWR, the period of the write cycle will be extended
until the write data is valid. Since the architecture and operation of the COM 9026 requires periodic reading and writing of the RAM buffer in a timely manner, holding the DWR
input off for a long period of time, or likewise by running the
processor at a slow speed, can result in a data overflow
condition. It is therefore recommended that if the processor
write data setup time to the RAM buffer is met, then the DWR
input should be grounded.

If a processor cycle request occurs after a COM 9026 request
has already been granted, the COM 9026 cycle will occur
first, as shown in figure 5. Figure 5 illustrates the timing
relationship of a COM 9026 RAM Write cycle followed by a
Processor RAM Write cycle. Due to the asynchronous nature
of the bus requests (AS and ClK), the transition from the
end of the COM 9026 cycle to the beginning of the processor cycle might have some dead time. Refering to figure 5,
if AS falling edge occurs after the start of half ClK interval
9C, no real contention exists and it will take between 200
and 500 nanoseconds before the processor cycle can start.
The start of the processor cycle is defined as the time when
the COM 9026 produces a leading edge on both ADIE and
AlE. If the processor request occurs before the end of half

For processor I/O write cycles to the COM 9026, ADIE and
AlE are used to enable the processor's address onto the
interface data bus. IlE is used to enable the processor's
write data into the COM 9026. Delaying the activation of
DWR will hold up the COM 9026 cycle requiring the same
precautions as stated for Processor RAM Write cycles.

~ooo

ClK

AS ____~r----\L_______________________________4I~

--JX....-'H"'I.:..;A;::;DD"-'R-'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-I:t=x~___
PADY·O _ _ _ _--JX lO ADDR XPROCESSOR WRITE DATA
X'-__
RW.MREO _ _ _~'U\~\\L-____~/~7LI_________________________~~~
PA15·8 _ _ _ _

---<::==x'--___
I~

1...,//

REO ______1
....

\'-____________________-J,

IVA
IA 10·8

----<
_

IAD7-0

COM 9026 HI ADDR

>------<

AlE

II

_ _~~C~OM~'~!02[°=xJC~O~G9~2~2~T~==>--~~l~O~AD~DRS(~P~RO~CEBo~R==~----i~-----LO AnnR
WRITE DATA

WAIT _ _ _ _ _ _ _---',
ADIE.

)

HIADDR

II

\....---------;1/1-----------

--------------~\

,,-------1111--------

\L__________~r----\L______~/

\'-----,

\'------',

1/

II

'----1~-----,lIr------

IlE

FIGURE 5-COM 9026 WRITE RAM FOLLOWED BY PROCESSOR WRITE RAM

220

----~ .

.~-~-.

---------------------~

ClK interval 5C (figure 5 illustrates this situation), then the
processor cycle will always start at half ClK interval 1P. The
uncertainty is introduced when the processor request occurs
during half ClK intervals 6C, 7C or 8C. In this case, the
processor cycle will start between 200 and 500 nanoseconds later depending on the particular timing relation
between AS and ClK. The maximum time between processor request and processor cycle start, which occurs when
the processor request comes just after a COM 9026 request,
is 1300 nanoseconds. It should be noted that all times
specified above assume a nominal ClK period of 200
nanoseconds.

BIT 2 (RECON) set to a logic "0".
BIT 1 (TMA) set to a logic "0".
BIT 0 (TA) set to a logic "1".
In addition the OSYNC output is reset inactive high and the
interrupt mask register is reset (no maskable interrupts
enabled). Page 00 is selected for both the receive and the
transmit RAM buffer. After the paR signal is removed, the
COM 9026 will generate an interrupt from the nonmaskable
Power On Reset interrupt. The COM 9026 will start operation four CA clock cycles afterthe paR signal is removed.
At this time, the COM 9026, after reading its 10 from the
external shift register, will execute two write cycles to the
RAM buffer. Address 00 HEX will be written with the data
01 HEX and address 01 HEX will be written with the 10
number as previously read from the external shift register.
The processor may then read RAM buffer address 01 to
determine the COM 9026 10. It should be noted that the data
pattern 01 written into the RAM has been chosen arbitrarily. Only if the 01 pattern appears in the RAM buffer can
proper operation be assured.

Figures 6 and 7 illustrate timing for Processor Read COM
9026 and Processor Write COM 9026 respectively. These
cycles are also shown divided into 8 half clock intervals (1 P
through 8P) and can be inserted within figures 4 and 5 if
these processor cycles occur.

POWER UP AND INITIALIZATION
The COM 9026 has the following power up requirements:
1-The paR input must be active for at least 100
milliseconds.
2-The ClK input must run for at least 10 clock cycles before
the paR input is removed.
3-While paR is asserted, the CA input may be running or
held high. If the CA input is running, paR may be
released asynchronously with respect to CA. If the CA
input is held high, paR may be released before CA
begins running.

CLOCK GENERATOR
The COM 9026 uses two separate clock inputs namely CA
and ClK. The ClK input is a 5 MHz free running clock and
the CA input is a start/stop clock periodically stopped and
started to allow the COM 9026 to synchronize to the incoming data that appears on the RX input.
Figure 9 illustrates the timing of the CA clock generator and
its relationship to the OSYNC output and the RX input. The
OSYNC output is used to control the stopping of the CA clock.
On the next rising edge of the CA input after OSYNC is
asserted, CA will remain in the high state. The CA clock
remains halted in the high state as long as the RX signal
remains high. When the RX signal goes low, the CA clock
is restarted and remains running until the next falling
edge of OSYNC. (See figure 20 for an implementation of
this circuit.)

Ouring paR the status register will assume the following
state:
BIT 7 (RI) set to a logic "1".
BIT 6 (ETS2) not affected
BIT 5 (ETS1) not affected
BIT 4 (PaR) set to a logic "1".
BIT 3 (TEST) set to a logic "0".

CLK~

ClK~~

AS~~I----------

AS~l-l- - - - - - - - - - - PA156~

HIADDR

PAD7.0~~
IORED

-----ss\\

PA15.8~

:t-{----------

PAD7.0:==X LOW ADOR X:::::,";P:O;ROVC'i"ES:..U_--'~'-L..L.
_ _ _ _ _ _ _ _ _ __

~~l-----------------

RD-------'l'-l

WR

'---

REQ----1..J..L./n"TT"----ll1l----------IAlO·8
IAD7-0

,--

REQ-1.l.1../n-rr------ll1-1- - - - - - - - - IAlO·8 - - - - - - - l l l - {

-------ll~COM 9026 DATAOUT'r-

IAD7-0------l1~

_ ____---'~l-1------~\

AlE

-----\,1

-------lll--____

~
------/l~----

FIGURE 7-PROCESSOR WRITE COM 9026
221

I

000

CA

Rx------------------------~l~------~

FIGURE 9-CA CLOCK GENERATOR TIMING

EXTENDED TIMEOUT FUNCTION
ET2 ET1
1
1
1
0
1
0
0
0

There are three timeouts associated with the COM 9026
operation.

Response Time
This timeout is equal to the round trip propagation delay
between the 2 furthest nodes on the network plus the maximum turn around time (the time it takes a particular COM
9026 to start sending a message in response to a received
message) which is known to be 12 microseconds. The round
trip propagation delay is a function of the transmission media
and network topology. For a typical system using RG62 coax
in a baseband system, a one way cable propagation delay
of 31 microseconds translates to a distance of about 4 miles.
The flow chart in figure 3 uses a value of 74.7 microseconds (31 +31 +12+margin) to determine if any node
will respond.

RESPONSE
IDLE
RECONFIGURATION
TIME (ms)
TIME (/Ls) TIME (/LS)
840
78
86
1680
316
285
624
1680
563
1237
1680
1130

TABLE 1
COM 9026 INTERNAL PROGRAMMABLE
TIMER VALUES

I/O COMMANDS
I/O commands are executed by activating the 10REQ input.
The COM 9026 will interrogate the ADO and the R/Vii inputs
at the AS time to execute commands according to the following table:
10REQ ADO
low
low
low
low
low
high
low
high

Idle Time
This time is associated with a NETWORK RECONFIGURATION. Refering to figure 3, during a NETWORK RECONFIGURATION one node will continually transmit INVITATIONS TO TRANSMIT until it encounters an active node.
Every other node on the network must distinguish between
this operation and an entirely idle line. During NETWORK
RECONFIGURATION, activity will appear on the line every
78 microseconds. This 78 microsecond is equal to the
response time of 74.7 microseconds plus the time it takes
the COM 9026 to retransmit another message (usually
another INVITATION TO TRANSMIT). The actual timeout
is set to 78.2 microseconds to allow for margin.

R/W
low
high
low
high

FUNCTION
write interrupt mask
read status register
write COM 9026 command
reserved for future use

READ STATUS REGISTER
Execution of this command places the contents of the status register on the data bus (AD7 -ADO) during the read portion of the processor's read cycle. The COM 9026 status
register contents are defined as follows:
BIT 7-Receiver inhibited (RI)-This bit, if set high, indicates that a packet has been deposited into the RAM
buffer page nn as specified by the last ENABLE
RECEIVE TO PAGE nn command. The setting of
this bit can cause an interrupt via INTR if enabled
during a WRITE INTERRUPT MASK command. No
messages will be received until an ENABLE
RECEIVE TO PAGE nn command is issued. After
any message is received, the receiver is automatically inhibited by setting this bit to a logic one.
BIT 6-Extended Timeout Status 2 (ETS2)-This bit reflects the current logic value tied to the ET2 input pin
(pin 1).
BIT 5-Extended Timeout Status 1 (ETS1)-This bit reflects the current logic value tied to the ET1 input pin
(pin 3).

Reconfiguration Time
If any node does not receive the token within this time, the
node will initiate a NETWORK RECONFIGURATION.
The ET2 and ET1 inputs allow the network to operate over
longer distances than the 4 miles stated earlier. DC levels
on these inputs control the maximum distances over which
the COM 9026 can operate by controlling the 3 timeout values described above. Table 1 illustrates the response time
and reconfiguration time as a function of the ET2 and ET1
inputs. It should be noted that for proper network operation,
all COM 9026's connected to the same network must have
the same response time, idle time and reconfiguration time.

222

BIT 4-Power On Reset (POR)-This bit, if set high, indicates that the COM 9026 has received an active
signal on the POR input (pin 40). The setting of this
bit will cause a nonmaskable interrupt via INTR.
BIT 3-Test (TEST)-This bit is intended for test and diagnostic purposes. It will be a logic zero under any
normal operating conditions.
BIT 2-Reconfiguration (RECON)-This bit, if set high,
indicates that the reconfiguration timer has timed
out because the RX input was idle for 78.2 microseconds. The setting of this bit can cause an interrupt via INTR if enabled by the WRITE INTERRUPT
MASK command. The bit is reset low during a
CLEAR FLAGS command.
'
BIT 1-Transmit Message Acknowledged (TMA)-This bit,
if set high, indicates that the packet transmitted as
a result of an ENABLE TRANSMIT FROM PAGE
nn command has been positively acknowledged.
This bit should only be considered valid after the
TA bit (bit 0) is set. Broadcast mesages are never
acknowledged.
BIT 0-Transmitter Available (TA)-This bit, if set high,
indicates that the transmitter is available for transmitting. This bit is set at the conclusion of a ENABLE TRANSMIT FROM PAGE nn command or upon
the execution of a DISABLE TRANSMITTER command. The setting of this bit can cause an interrupt
via INTR if enabled by the WRITE INTERRUPT
MASK command.

WRITE INTERRUPT MASK
The COM 9026 is capable of generating an interrupt signal
when certain status bits become true. A write to the MASK
register specifies which status bits can generate the interrupt. The bit positions in the MASK register are in the same
position as their corresponding status bits in the STATUS
register with a logic one in a bit position enabling the corresponding interrupt. The setting of the TMA, EST1, and
EST2 status bits will never cause an interrupt. The POR
status bit will cause a non-maskable interrupt regardless of
the value of the corresponding MASK register bit. The MASK
register takes on the following bit definition:
.

The three maskable status bits are anded with their respective mask bits, and the results, along with the POR status
bit, are or'ed to produce the processor interrupt signal INTR.
This signal returns to its inactive low state when the interrupting status bit is reset to a logic "0" or when the corresponding bit in the MASK register is reset to a logic "0". To
clear an interrupt generC!ted as a result of a Power On Reset
or Reconfiguration occurance, the CLEAR FLAGS command should be used. To clear an interrupt generated as a
result of a completed transmission (TA) or a completed
reception (RI), the corresponding masks bits should be reset
to a logic zero.

WRITE COM 9026 COMMANDS
Execution of the following commands are initiated by performing a processor 1/0 write with the written data defining the
following commands:
WRITTEN DATA
00000000
00000001
00000010

000nn011

bOOnn100

0000c101
000rp110

COMMAND
reserved for future use
DISABLE TRANSMITTER-This command will cancel any pending transmit command
(transmission has not yet started) when the COM 9026 next receives the token. This command will set the TA (Transmitter Available) status bit when the token is received.
DISABLE RECEIVER-This command will cancel any pending receive command. If
the COM 9026 is not yet receiving a packet, the RI (Receiver Inhibited) bit will be set
the next time the token is received. If packet reception is already underway, reception
will run to its normal conclusion.
ENABLE TRANSMIT FROM PAGE nn-This command prepares the COM 9026 to
begin a transmit sequence from RAM buffer page nn the next time it receives the
token. When this command is loaded, the TA and TMA bits are set to a' logic "0". The
TA bit is set to a 10~C one upon completion of the transmit sequence. The TMA bit will
have been set by t is time if the COM 9026 has received an acknowledgement from
the destination COM 9026. This acknowledgement is strictly hardware level which is
sent by the receiving COM 9026 before its controlling processor is even aware of
message reception. It is also possible for this acknowledgement to get lost due to line
errors, etc. This implies that the TMA bit is not a guarantee of proper destination
reception. Refer to figure 3 for details of the tra,nsmit sequence and its relation to the
TA and TfV1A status bits.
'
ENABLE RECEIVE TO PAGE nn-This command allows the COM 9026 to receive
data packets into RAM buffer page nnand sets the RI status bit to a logic zero. If "b"
is a logic "1 ", the COM 9026 will also receive broadcast transmissions. A broadcast
transmission is a transmission to ID zero. The RI status bit is set to a logic one upon
successful reception of a message.
DEFINE CONFIGURATION-If c is a logic "1 '; the COM 9026 will handle short as
well as long packets. If c is a logic "0", the COM 9026 will only handle short packets
(less than 254 bytes).
CLEAR FLAGS-If P is a logic "1" the POR status flag is cleared. If r is a logic "I", the
RECON status flag is cleared.

All other combinations of written data are not permitted and can result in incorrect chip and/or network operation.
223

M~XIMUM

GUARANTEED RATINGS'

Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. ....... 0 to 70°C
............
. . . . . . . . . . .. - 55 to 150°C
Storage Temperature Range. .. . . . . . . . . . . . . . . . . . . . . . . .
Lead Temperature (soldering, 10 seconds) . .
. ................... + 325°C
Positive Voltage on any pin .........................
...........
+ BV
Negative Voltage on any pin, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device Irom laboratory or system power supplies, it is important that the Absolute Maximum Ratings not
be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power
is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. II this possibility exists, it is
suggested that a clamp circuit be used.

DC ELECTRICAL CHARACTERISTICS (TA = DOG to 7Doe, Vee = 5.DV ± 5%)
PARAMETER

-0.3
2.2
Vee- 0.5

VOH

input low voltage
input high voltage 1
input high voltage 2
output low vOltage 1
output low voltage 2
output high voltage

2.4

UNITS
V
V
V
V
V
V

VOH

output high voltage

2.7

V

IL
C'N
C oa
CL
Icc

input leakage current
input capacitance
data PHs; capacitance
all other capacitance
power supply current

VIL

V1H1

V1H2
VOL'

VOL2

MIN

TYP

MAX

O.B
Vee
6.5
0.4
0.5

lBO

:tl0
20
50
30
350

COMMENTS
except CA and CLK
lor CA or CLK
10L = 1.6ma
10L =2.0ma
except Tx and DSYNC
10H = -IOOfLA
Tx and DSYNC only
10H = -IOOfLA

fLA
pf
pf
pf
ma

r-----------------------i
I 5 6K ,~w

r--------------------I
I
I
I
I

I

I
I
I
I
I
I
I
I
IL__

I
I
I

_ ______________________________________ _

COM

9026

PULSE 1

RXIN

PULSE 2

DSVNC
COM
CA

AX

f-oIIo-------I
f-oII-------I

fXf---------~~

ClK

f-oII----.----1

CA

9032

RXQUT

fX

OSC

LANCLK

lDDAT

L ••• --YI'
,

FIGURE 20: TYPICAL SYSTEM IMPLEMENTATION
224

I
I
I

_ __ -.l

e

AC ELECTRICAL CHARACTERISTICS (TA = 0° to 70 0 , Vee = 5 OV +- 5%)
PARAMETER

MIN

tPW1 ClK pulse width
tpER1 ClKperiod
ClKofftime
tOFFl
tPW2 CA pulse width
tpER2 CAperiod
CAolitime
tOFF2
ClK, CA rise time
tR
ClK, CA fall lime
tF
I,
widlh of addr. slrobe
REQ oulpul delay
12
WAIT asserlion delay
13
delay 10 rising edge
14
of processor cycle
dala hold inlo COM 9026
I.
selup COM 9026 dala oul
I.
WE delay from ClK
17
TX on delay from CA
I.
falling edge
TX off delay from CA
I.
rising edge
AS period
I"
DSYNC delay from CA
I"
rising edge
delay 10 wail off
1'2
DWR selup lime
1'3
IlE delay from ClK
1'4
processor addr. setup from ADIE,
I,.
processor command selupJime
I,.
addr. enable selup li'!1e 10 l
117
addr. hold lime from l
I,.
slrobe and dala hold for read
I,.
120
AD bus HI impedance 10 OEs
12,
delay of IDLD from ClK rising edge
delay of IDDAT from ClK rising edge
122
123
oil delay from ClK rising edge
addr. 10 RAM dala valid
124
OE selup 10 WAIT falling edge
12•
slrobe & dala hold for wrile
12•
addr. enable setup to WAIT
t27
ADIE 10 OE delay
t2•
COM 9026 write dala hold lime
t2•
OE 10 RAM dala valid
t30
13,
slalus selup 10 AS falling edge
stalus hold from AS falling edge
132
RX selup 10 CA rising edge
133
RX hOld lime from CA rising edge
t34
POR aclive time
13•

65
190
65
60
190
60

TYP

MAX

200

600

100

300
20
20
400
100
200

50
0
0

UNITS

Ip
80
60
0
10

21p+l00

100
150

ns
ns
ns
ns
ns

10

150

ns

10

150

ns
ns

20
50
10

100

7/21 p

100
50

125
50
50
20
0
0
0
0

120
50
100
300

140
50
300
40
80
0
50
50
80
30
100

140

COMMENTS

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms

Ip = IpER,

tp = tpER2

after Vee has been stable for
lime 13., Ihe minimum PDR
active lime is 10 cycles of elK.

The above timing information is valid for a worsl case 40% 10 60% duly cycle on ClK. All times are measured from the 50% point of
the signals.

FIGURE 10CLK,CA
AC CHARACTERISTICS

ClK

CA

225

AS

REO

FIGURE 11PROCESSOR ACCESS
SYNCHRONIZATION

~13

WAIT

lOR EO,
MREO,

STABLE

R/W

I...

:V
1r-------'1
I,

~l

ClK

START OF PROCESSOR
ACCESS CYCLE

CA

RX

TX

DSYNC

FIGURE 12-TRANSMIT AND RECEIVE TIMING

~_~_'~

elK
ADIE, AlE

n"

,,,~~

_

I-t,\

oWE

OW,

_"

I

I

1,,t

'11"1

I

r---+-I- -

r',,}~I-I J\¥~

I
"' I ~r-,.J
I-I"~

I
1

WAIT

1- " ' ' - - - _ - - - ' -_ _ _ _ __

FIGURE 13-PROCESSOR WRITE RAM AC TIMING
226

ClK

1P

ADIE~IU

2P

4P

3P

"1

.~.

l

t

1-1,,,

WAIT

-t

~

6P

7P

8P

il"'j

OE

AlE

5P

I

I"'-t-I"j

1''"1

I"

FIGURE 14-PROCESSOR READ RAM AC TIMING
2C

;--;c\

/

4C

II

5C

\

6C

VALID
COM 9026 ADDR

A10-8

rr "J

-'' 1=''-

AD7-0

l

J~t

OE

c

1

I

VALID
\
COM 9026 ADDRESS

'c

1--1; II

IN

/

9C

RAM DATA
INTO COM 9026

.If

~"r-~Int-

I,c~

FIGURE 1S-COM 9026 READ RAM AC TIMING

~

/

2C

J

A10-8

AD7-0

-WE

[

1\
V

3C

T

-----I

/

5C

\

6C

VALID COM 9026 ADDRESS

1

VALID
COM 9026 ADDR

4C

I,

fI

7C

\

8C

t--

1

I

COM 9026 DATA
TO RAM

1-1

I,

f-~

L"=t,,,.

f-Ic

.1.
I

1,,-

FIGURE 16-COM 9026 WRITE RAM AC TIMING
227

f

9C

~c

I
I

~'J-

\

lC

ClK/

AD7-0

2C

/

\

3C

4C

;=f

\

5C

6C

7C

COM 9026 DATA OUT

11
~')

r

jROCESSOR ADDR)

/

""

/

L,t

AlE

WAIT

\

BC

/

9C

~

t'"-1

FIGURE 17-PROCESSOR READ COM 9026 AC TIMING
ClK/

\

lC

2C

'

AD7-0

ADIE, AlE

1

3C

r
,

PROCE,SSOR ADD~

-tt'"-

I

4C

/5C~

t---t",

\

PROCESSOR DATA IN

/

I

I

IlE

I

\

BC

/

9C

~oc

I

-j'''r
I

I\,,1
L,'1

DWR

7C

~

LA

~t"t-

WAIT

FIGURE 18-PROCESSOR WRITE COM 9026 AC TIMING
1

0
CLK---./

--

2

~I"

1-----

IDLD

t"

--

-

7

3

~~

---j,~~

-

-j,C

IDDAT
(FROM SHIFT REGISTER)

0

~,r-

-~

?

(

-"-

I

FIGURE 19-10 INPUT AC TIMING
STANDARD MICROSYSTEMS
CORPORATION ~!ii\iiiiiii.ji
35Mar.lppauyeNY"168

15161:'733100

rwX5102278898

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
Information has been carefully checked and is believed to be entirely reliable. However, no responsibility IS
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any liconse under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

228

------- - - - - - - - - - - - - - - - - - -

STANDARD MICROSYSTEMS
CORPORATION

COM 9032

COM 9032

Local Area Network Transceiver
LANT
FEATURES

PIN CONFIGURATION

D Reduces chip count for COM 9026 ARCNET'
implementations by 6-8 TTL chips

D Performs all clock generation
functions for the COM 9026

D Compatible with the COM 9026

D Provides line drive signals
for transmission

D Converts incoming serial receive
data to NRZ data format

D Generates two 4 MHz general purpose
clocks

PULS2

1 "-..J16

PULS1

2

15

INHTX

BLNK

3

14

TX

CPUCLK

4

13

CA

CKSEL

5

12

DSYNC

TTLCLK

6

11

RXOUT

OSC

7

10

RXIN

GND

8

9

Vee

LANCLK

GENERAL DESCRIPTION
The COM 9032 local area network transceiver is a companion chip to the COM 9026 local Area Network Controller (lANC) and will perform the additional functions
necessary to allow simple interface to a transmission media
for all ARCNET' (or equivalent) local area networks. Using a
20 MHz input clock, the COM 9032 will produce two, 5 MHz
clocks for the COM 9026. The first 5 MHz clock is free running and will directly feed the ClK input of the COM 9026
(pin 19). The second 5 MHz clock has start/stop capability
which is controlled by the DSYNC output of the COM 9026
(pin 36) and the received data inputas required by the COM
9026 (pin 2). Two additional 4 MHz free running clocks are
also generated on the COM 9032 to allow operation of other
logic, a microprocessor, or an lSI controller.
During data reception, the COM 9032 will convert incoming serial receive data from the transmission media to NRZ
form which will directly feed the RX input oi the COM 9026
(pin 38). During transmission, the COM 9032 converts
the transmit data from the COM 9026 (TX, pin 37) into the
waveforms necessary to drive opposite ends of the rf
transformer used in the ARCNET' cable electronics shown
in figure 2.

'4

I---f-!-... PULS2

TX-~_--;

1S

INHTX-"-~-t---;

TRANSMIT
LOGIC

OSYNC_'.::.2~ .......+--;

,.

RXIN-~++++-I

I---f-"-'"

BLNK

I---t-=-...

PULS,

1-_ _+-",'3. . . CA

I -....-j-'''''... RXOUT

16

+5V
GND

OSC""":'-.J-+t-i

I---t-"... LANCLK

1---4>--t.-=-TTCLK
CKSEL--"-~-+--;

t---+-... CPUCLK

FIGURE 1:
COM 9032 BLOCK DIAGRAM

* ARCNET is a registered trademark of the Datapoint

Corporation.
229

r-----------------------,
1_1
1
1

~---------------------

1
1

1
1
1
1

1

1
1
1

1
1
1

52.3!l

,%

1

1

O.471-'h

1
1

1
1
1
1

---~
I\)

W

COM

o

9026

PULSE 1

RXIN

PULSE 2
DSYNC

1

.1

OSYNC
CA

COM

9032

RX
C
A § RXOUT
IDLD

TX
CLK

TX

OSC

I

I

I.....

1 ~8~HRZE
WAVE

LANCLK

10 OAT

Pin compallble fiber-optic driver
Raycom Systems
6395 Gunpark Drive
Boulder. Colorado 80301
PIN R-3101

L ••• ~II

FIGURE2:
TYPICAL COM 9032 INTERCONNECT

Circuitry inside dolled lines is contained in a hybrid
module available from the following sources:
Cenlralab, Inc
2601 Soulh Moorland Road
P.O. Box 2145
Milwaukee, WI 53201
Part # Siraight Lead Frame-71-0961-001
Righi Angle Frame-71-0961-002
Micro-Technology, Inc.
W141 N5984 Kaul Avenue
Menomonee Falls, WI 53051
Pari # A60101 (specily slraight or righl
angle frame)
Zenilh CRT & Components Operations
100 Milwaukee Avenue
Glenview, IL 60025
Part # Straighl Lead Frame-EG-A059101A
Righi Angle Frame-EG-A059102A

DESCRIPTION OF PIN FUNCTIONS
(Refer to figure 2)

COM 9026 INTERFACE
PIN NO.
1,2

NAME
PULSE 2
PULSE 1

SYMBOL
PULS2
PULS1

3

BLANK

BLNK

10

RECEIVE IN

RXIN

11

RECEIVE
OUT
DELAYED
SYNC
CA

RXOUT

TRANSMIT
DATA
TRANSMIT
INHIBIT

TX

12
13

14
15

DSYNC
CA

INHTX

FUNCTION
PULS2 and PULS1 are two nonoverlapping negative pulses which occur every
time the TX input is pulsed. PULS2 and PULS1 are used to feed an external
driver as shown in figure 2.
When used with the circuitry shown in figure 2, this output should be left unconnected. The timing of this signal is shown in figure 4.
This input is the recovered receive data from the network. For each dipulse .
appearing on the network, the comparator shown in figure 2 will produce a positive pulse which directly feeds this input.
This output is the NRZ data generated as a function of the RXIN pulse waveform
which directly feeds the RX input of the COM 9026 (pin 38).
This active low input, which is asserted by the COM 9026, will halt the CA clock
output.
This output is a 5 MHz starVstop clock that is halted when DSYNC goes active
low and restarted by a low signal on the RXOUT output. This clock is capable of
driving 70 pf plus one LS load with 20 nanoseconds rise and fall times.
This input, which is asserted by the COM 9026, is the serial data transmitted by
the node.
This active low input inhibits the TX signal from initiating transmit signals by forcing PULS1 and PULS2 to a high and BLNK to a low. This signal should be
asserted during a power on reset condition.

SYSTEM CLOCK INTERFACE
PIN NO.
4

NAME
CPU CLOCK

SYMBOL
CPUCLK

5

CLOCK
SELECT

CKSEL

6

TTL CLOCK

TTLCLK

7
9

OSCILLATOR
LOCAL AREA
NETWORK
CLOCK
GROUND
+5 VOLT
SUPPLY

OSC
LANCLK

8
16

GND
Vee

FUNCTION
This output is a 4 MHz free running clock capable of driving 130 pf with 30 nanosecond rise and fall times. It is identical to the TTLCLK input when CKSEL is
high. When CKSEL is low, this output becomes the inversion of the signal that is
fed into the TTLCLK input.
This input selects the clock interface option for the TTLCLK and CPUCLK. When
this signal is high, both the TTLCLK and CPUCLK are identical 4 MHz free running clock outputs which are generated from the 20 MHz input clock (OSC) via a
divide by 5 frequency divider. When this input is low, the TTLCLK pin becomes an
input and the CPUCLK output will produce the inversion of the signal appearing
on TTLCLK input.
This pin can be either an input or an output depending on the state of the
CKSEL input. When CKSEL is high, a free running 4 MHz clock is ouput. When
CKSEL is low, the pin becomes an input which drives an inverter that feeds the
CPUCLK output.
This input requires a 20 MHz clock.
This output will supply the free running 5 MHz clock to the COM 9026, pin 19. It is
capable of driving 70 pf plus one LS load with 20 nanoseconds rise and fall times.
Ground
Power Supply

FUNCTIONAL DESCRIPTION
duces a positive pulse for each dipulse received from the
cable. These pulses are captured by the COM 9032 and are
converted to NRZ data with the NRZ data bit boundaries
being delayed by 5 OSC clock periods as shown in figure
5. As each byte is received by the COM 9026, the CA clock
is stopped by the COM 9026 (via DSYNC) until the first
bit of the next byte is received which will automatically restart the CA clock. The COM 9026 uses the CA clock to
sample the N RZ data and these sample points are shown in
figure 5.
Typically, RXIN pulses occur at multiples of the transmission rate of 2.5 MHz (400 nanoseconds). The COM 9032
can tolerate distortion of plus or minus 100 nanoseconds
and still correctly capture and convert the RXIN pulses to
NRZformat.

Transmit logic (refer to figures 2 and 4)
The COM 9026, when transmitting data on TX, will produce a negative pulse of 200 nanoseconds in duration to
indicate a logic "1" and no pulse to indicate aJQ9ic "0".
Refering to figure 4, a 200 nanosecond pulse on TX is converted to two, 100 nanosecond nonoverlap~lses
shown as PULS1 and PULS2. The signals PULS1 and
PULS2 are used to create a 200 nanosecond wide dipulse
by driving opposite ends of the RF transformer shown in
figure 2.

Receive logic (refer to figures 2 and 5)
As each dipulse appears on the cable, it is coupled
through the RF transformer, passes through the matcheq
filter, and feeds the 75108B comp~rator. The 75108B pro231

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range .................................................................................... O°C to 70°C
Storage Temperature Range ................................................................................... - 55° to 150°C
Lead Temperature (soldering, 10 sec.) .................................................................................. 325°C
Positive Voltage on any Pin .......................... , .................................................................... + 8V
Negative Voltage on any Pin ............................................................................................ -0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
DC ELECTRICAL CHARACTERISTICS (T. = O°C to + 70°C, Vee = 5V ± 5%)
PARAMETER
INPUT VOLTAGES
V,H
VIL
OUTPUT VOLTAGES
VOHI

MIN

TYP

UNIT

0.8

V
V

2.7
2.4

V

VOLl
VOH2
VOl2
VOH3

MAX

0.4

V

0.4

V
V
V

0.4

V

50
10

/LA
/LA

20

pf

20

rnA

MAX

UNIT

Vcc-0.5
Vee-0.5

VOL3
LEAKAGE CURRENT
I"
1'2
INPUT CAPACITANCE
C'N
SUPPLY CURRENT
Icc

COMMENTS

10H= -0.4 rnA, PULS1, PULS2,
BLNK, RXOUT and TILCLK
______
outputs.
10L = 4.0 rnA, PULS1, PULS2,
BLNK, RXOUT and TILCLK
outputs.
10H = - 0.1 rnA, CPUCLK output.
10L = 0.1 rnA, CPUCLK output.
10H = - 0.1 rnA, CA and LANCLK
outputs.
10L = 0.4 rnA, CA and LANCLK
outputs.
TILCLK input with CKSEL low.
all other inputs.

at 20 MHz OSC frequency.

AC CHARACTERISTICS
PARAMETER
OSC Input
tey ,
tCHl

tell

CA, LANCLK
IeY2
tCH2

Ie"
tF2
tR2
TILCLK
tev3

t CH3
teLa
CPl)CLK (CKSEL is high)
t CY4
tCH4
tCl4

MIN

TYP
50

ns
ns
ns

200

ns
ns
ns
ns
ns

20
20
75
75
20
20
250

ns
ns
ns

250

ns
ns
ns
ns
ns
ns

110
110
110
110
30
30
45

tF4
tR•
tOCK

TRANSMIT TIMING
t STC
tHTC
top
t p1W
tWB
tp2W

50
10

30
60
2teYI
t CY1
2teYI

tAST

RECEIVE TIMING
tRS
tRW

30
10

too

tRO
tS50

tsse

tROW

40

10

5teYI + too
20
400

232

70

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

COMMENTS

for CKSEL low.

OSC

1"];.:-'--1"'--.. .

I"'---r

"+----:"

k.

cJ;:==-I'"- "

(cJ~~Et~w) ~'t
1o,"

CPUCLK
(CKSEL HIGH)

J'-10'"f---

---

FIGURE 3: CLOCK TIMING

OSC

CA

TX

FIGURE 4: TRANSMIT TIMING PARAMETERS

"~,
DSVNC

~_

----'--

~

~
SAMPLE

FIGURE 5: RECEIVE TIMING PARAMETERS

233

I

t

SAMPLE

I

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully c~ecked and is believed to be entirely reliable. However. no responsibility is
assumed for inaccuracies, Furthermore. such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

234

COM9046
PRELIMINARY

Single Side Band Speech Scrambler

FEATURES

PIN CONFIGURATION

o Speech ScramblinglDescrambling
o High Dynamic Range
o Low Voltage Operation
o Low Power Consumption
o On Board Crystal Oscillator
o Uses Common Color Burst Crystal

N/C

Scramble 2
Vss 3
Ref 4
In-B 5
Out-B 6

o Full Duplex Operation
o Selectable Scramble Enable/Disable
o Switched Capacitor Filter

Vdd A 7

o COPLAMOS® n-Channel Silicon Gate Technology

14
13
12
11
10

XTAL,
N/C

XTAL,
In-A
Out-A

9 Vdd
8 Vss A

GENERAL DESCRIPTION
The COM9046 is a monolithic integrated circuit containing a voice scrambler, a descrambler and a crystal oscillator. It is designed to provide speech communication
equipment with a privacy feature. The COM9046 is also
designed to operate with power supply voltages as low as
± 2Volts. The low voltage operation and low power consumption of the COM9046 make it ideal for use in portable
equipment.
Two identical speech channels are contained in the
COM9046 for full duplex operation. Either channel is cap a-

235

ble of performing the scrambling or descrambling function.
These functions can be enabled or disabled via an external
pin. The on-board oscillator employs an inexpensive 3.58
MHz TV color-burst crystal. Switched capacitor techniques
are used to perform analog signal proceSSing in the
COM9046.
Typical applications for the COM9046 are Voice
Communications, Cellular Phones, Wireless Phones,
PBX's, Dictation Machines, Two-way Radios and Audio
Recording Equipment.

10
SPEECH
INPUT

DOUBLE
SIDEBAND
MODULATOR

LOW PASS
FILTER

DOUBLE
SIDEBAND
MODULATOR

LOW PASS
FILTER

OUT-A

OUT-B
SPEECH
INPUT

SCRAMBLE

Vdd
2.6V

f

VddA

Vss

VssA
--2.6V

10

.'~fp~f

15pf -10%

10M

125Pf woOf
0

..

Vss

Figure 1 BLOCK DIAGRAM

DESCRIPTION OF PIN FUNCTIONS
PIN#

NAME

1

N/C

SYMBOL

DESCRIPTION
No Connection

2

Scramble

-

3

Digital Supply

Vss

Negative digital supply. Vss is typically - 2.6 volts with respect to pin 4.

4

Ref Input

Ref

Analog ground or mid-supply voltage. This is the chip 0 volt reference.

-5

Vss applied to this pin asserts the scramble; Vdd asserts non-scramble.

In-B

Channel B audio input. D.C. voltage must be OV with respect to pin 4.

6

Audio Output B

Out-B

Channel B audio output. DC voltage is OV typical with respect to pin 4.

7

Analog Supply

Vdd A

Positive analog supply. Vdd is typically

8

Analog Supply

Vss A

Negative analog supply. Vss A is typically - 2.6 volts with respect to pin 4.

Audio Input B

+ 2.6 volts with respect to pin 4.

+ 2.6 volts with respect to pin 4.

9

Digital Supply

Vdd

10

Audio Output A

Out-A

Channel A audio output. DC voltage is OV typical with respect to pin 4.

11

Audio Input A

In-A

Channel B audio input. D.C. voltage must be OV with respect to pin 4.

12

Crystal input/
Ext Clock

XTAL,

13

N/C

14

Crystal input

XTAL2

Positive digital supply. Vss is typically

Crystal Oscillator input or external clock. External clock frequency should
be 3.58MHz with an amplitude of 4Vp-p and OVDC.
No connection
Crystal Oscillator output. This pin is left floating when external clock is
applied to pin 12.
236

OPERATION
Figure 1 shows a block diagram of the chip. Also shown
in Figure 1 are the required external components.
Since switched-capacitor filters are used on the chip, the
input speech signal must first be filtered by an anti-aliasing
one-pole low pass filter before it is applied to the Audio input
pin. The filter 3dB break pOint, which is determined by the
product of C1 and R1 plus the output impedance of the audio
source, should be less than 20KHz. This filter is required
only if high frequency noise is present at the input. To maintain an output signal to noise ratio of 40dB, any unwanted
signal higher than 3.5KHz contained in the speech input
must be filtered to 40dB below the nominal speech input
level, due to the fact that the on-chip modulator is switched
at3.5KHz.
The on-chip double sideband modulator can be turned
on or off by asserting the SCRAMBLE input pin. The 3.5KHz
switching frequency of the modulator is generated by divid-

ing the output of the oscillator by 1024. The modulator output contains two sidebands centered at the suppressed
switching frequency of 3.5KHz. The upper sideband is
attenuated by a 4th order Butterworth lowpass filter. The
filter, consisting of two biquad switched capacitor filters in
cascade, is clocked at 111.9KHz. The inverted input speech
spectrum appears at the filter output, and is available at the
Audio Output pin. The filter output circuit is designed to drive
a maximum capacitive load of 5pf in parallel with a minimum resistance of 15K ohms.
A parallel resonant crystal oscillator is employed in the
device. The parallel resonant crystal should have a maximum series resistance of 150 ohms with a shunt capacitance of 5pf. To insure reliable oscillator performance, the
components shown connected to XTAL pins 14 and 12 in
Figure 1 should be used.

ELECTRICAL CHARACTERISTICS

COM9046

MAXIMUM GUARANTEED RATINGS':
Operating Temperature Range ......................................................................... -15°Cto +55°C
Storage Temperature Range ........................................................................... -55°C to + 125°C
Lead Temperature (soldering, 10 sec.) .................................................................
+325°C
Positive Voltage on any pin with respect to Vss ........................................................
+ 6.5 V
Negative Voltage on any pin with respect to Vss . ...... . . .. .. . . .. .... .. .. .... .... .. .... .. .. .. .... . .. . ..
- 0.3 V

·Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other condition above those indicated in the operational sections of this specifications is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum
Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their
outputs when the AC power is switched on and off. In addition, voltage transients on the AC power line may appear on
the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
ELECTRICAL CHARACTERISTICS (Ta
±5%.)
Parameter

Supply Current
Insertion Loss
Audio Voltage Swing
SIN Ratio
Modulation Frequency
Bandedge of Sideband Filter
Scramble Input High
Scramble Logic Low
Input Resistance
Dynamic Output Resistance
3.5KHz Feedthrough

=

-10°C to + 50°C, Vdd
Min

=

Vdd A

=

+2.6V ±5%, Vss

Typ

Max

Units

5
0
0.8

8
1
1

ma
db
Vp-p
db
KHz
KHz
V
V
MOhm
Ohm
db

40
3.5
3.2
Vdd-1.0
Vss

Vdd
Vss+.3
5
900
-60

237

-50

=

Comments

Vss A

=

-2.6V

I

~,

'tnt

~,

RADIO OR WIRE
TRANSMISSION
MEDIUM

COM 9046

Cctl.
COM 9046

E,"

En

~))~3
E"

E"

'"UL

Lt,

~, ~,
Figure 2 TYPICAL APPLICATION
'Inverted Frequency Spectrum of the Inspect Signals
are Transmitted on the Transmission Medium.

15pF±10%

~
0.1 JlF
Audio ~ _ I
inA

1

T

4K

15pF±10%

,.0 t

12

y----,

~

I
T

10M

14

11

10--7 0utA

5

6 ---70uiB

2000PFt
Audio _'in B

0.1 JlF
II

+5V

4K

y----, I

2000PFt
COM9046

lOOK

l'

Scramble
2

lOOK

. ,+5V

Vdda

-p~'#

1

7-

4
3
Vss

±01JlF

Vdd

9

Ref

10K

8

2.2K
Vssa

~ I

10pF

"
" .1JlF

2.2K

RECOMMENDED CONNECTION FOR SINGLE +5V SUPPLY OPERATION
STAN~D

MICROSVSTEMS

CORPORATION

35M1roJs8Yd~JtYll78!
(516~2n-3HXl

TWX 510-2278898

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
.
at any time in order to improve design and supply the best product possible.

238

COM90C56
PRELIMINARY

Enhanced Local Area Network Controller
ELANe
FEATURES

PIN CONFIGURATION*

o 5.0/2.5 M bit data rates
o 100% compatible with COM9026 (in slow mode)
ARCNET local area netWork controller

o 64 K byte shared buffer memory
o Handles variable length data packets (up to 2 K long)

XTAL1
XTAL2
REO
ACK
NC
Rm

o Supports up to 255 nodes per network segment
o Allows 8/16 bit word per sync to enhance line efficiency
o Allows for nodal priority
o Supports event scheduling via buffer descriptors
o On board GP event counters (4) to monitor the network
o On chip network diagnostics
o Duplicate ID detection/prevention
o Node list/Group list requests
o Provides mail distribution capabilities
o Supports group broadcast messages
o Provides the hooks for broadband systems (modem)
o lnternallexternalloopback capability for self test
o Ram buffer test capability
o On board oscillator
o Low power CMOS technology

cs
AO
A1
A2
A3

A4
AS
A6
A7
AS
A9
A10
A11
A12
A13
A14
A15
GROUNO

vcc
GNO
RECON
ECHO
NC
RESET

os
RELAYCON
PULSE2
PULSE1
TXC
RXC
RX
10LO
INTR2
INTR1
07
06
05
04
03
02
01
00

PACKAGE: 48-pin D.I.P.

048 pin D.I.P. plastic package or PLCC
Single + 5v Supply

o
o Compatible with HYC9058, HYC9068, HYC9078

• Available in PLCC

Pin configuration subject to change, contact factory for details.

GENERAL DESCRIPTION
The ELANC is a general purpose communications adapter
designed to provide high speed intercommunication
between a number of intelligent electrical machines. Data
is carried over a variable media (twisted pair, coax, or fiber
optics) in variable size packets up to 2048 bytes long at

speeds of up to 5.0 Mbps. The interconnection of Several
nodes through their associated ELANCs forms an enhanced
local area network. Each node has a unique ID number from
1 to 255 to distinguish it from other nodes on the same
network.

239

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I
STANDARD MICROS'ISTEMS
CORPORATION
.

38'v'::/1:l31NI

sns V1131SAS lSOH

I

Circuit diagrams utilizing SMC products are included as a means of illustrating typical applications: consequently
complete information sufficient for construction purposes is not necessarily given. The information has been carefully
checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore,
such information does not convey to the purchaser of the products described any license under the patent rights of
SMC or others. SMC reserves the right to make changes at any time in order to improve design and supply the best
product possible.

242

COM 9064
PRELIMINARY

IBM® 3274/3276
Compatible COAX Receiver/Transmitter
FEATURES

PIN CONFIGURATION"

o Conforms to the IBM® 3270 Interface Display
System Standard

GND
T10
T9
TBMT
TOS
NIC'

Vee
GND

o Transmits and Receives Manchester II Code
o Detects and Generates Line Quiesce, Code

TP
T9S
ADE
DO
01
02
03
04
05

Violation, Sync, Parity, and Ending Sequence
(Mini Code Violation)

o Multi Byte or Single Byte Transfers
o Double Buffer Receiver and Transmitter
o Separate Data and Status Select

DLOOP
TO

TG
TC
AD

Al50P

06
07
A9
A10
SWE
AP
SCLK
N/C

o Operates at 2.3587 MHz
o TTL Compatible Inputs and Outputs

o COPLAMOS® n-Channel Silicon Gate
Technology

o Single + 5 Volt power supply

ASSE
BCLK
ADA
CVD
ATA
DA
N/C

MR

GND

"Internally connected. Not for external use.
""PLCC (J LEAD QUAD PACK) also available.

GENERAL DESCRIPTION
The COM 9064 is an MOSILSI circuit which may be used
to facilitate high speed data transmission. The COM 9064
is fabricated using SMC's patented COPLAMOS® technology and may be used to implement an interface between
IBM® 3274/3276 compatible control units and 3278/32871
3289 compatible terminal units. The receiver and transmitter sections of the COM 9064 are separate and may be used
independently of each other.

The COM 9064 generates and detects the line quiesce,
code violation, parity, and mini code violation bit patterns.
The on-chip parity logic is capable of generating and
checking either even or odd parity for the entire 10 bit data
word. In addition, parity may be generated for the least significant 8 bits of the data word (this parity bit would replace
the ninth data bit).

T9S

",0

m

Ie
0'

02
03
04
blOOP
ALOOP

ADA
RD
RP
RSSE

RW

R"

RTA
TBMT

DA
eVD

SWE
BCLK
SClK

IBM' is a registered trademark of the International Business Machines Corporation

243

ORGANIZATION
The COM 9064 is organized into 9 major sections. Communication between each section is achieved via internal
data and control busses.

Transmitter Holding Register
The transmit holding register is a 12 bit latch. This latch is
loaded with the transmit data and parity generation information from the system bus.

transmit circuitry. It also generates the Line Quiesce, Code
Violation, sync bits and Mini Code Violation patterns.

Transmitter Shift Register
The transmitter shift register is an 11 bit parallel to serial
shift register. It accepts data from the transmitter holding
register and the parity generation logic and converts it into
serial form for transmission.

Tri-State Buffers

Receive Control/Parity Check

These buffers allow gating of the COM 9064's status word
onto the system data bus.

This logic checks the received character for the specified
parity and ensures that no Transmit Check conditions
occurred. It also handles the self test mode and generates
a strobe when the complete data word is received.

Bus Transceiver
The bus transceiver allows bi-directional data transfer
between the system data bus and the transmit and receive
holding registers.

Parity Generator
This logic determines and generates the correct parity for
the data in the transmitter holding register.

Transmitter Control
This logic generates signals required to enable external

Receiver Shift Register
This logic is a serial to parallel shift register that converts
the received information into a 10 bit data word and RTA
status bit.

Receiver Holding Register
This register holds the assembled data word until it is read
by the processor.

DESCRIPTION OF PIN FUNCTIONS
Processor Related Signals
PINNa.
6-13

38

NAME
Transmit!
Receive Data
Bits
Transmit Bit 9
Select
Transmit Bit 9

39
3

Transmit Bit 10
Transmit Parity

T10
TP'

18

System Clock

SCLK

36

Transmitter
Data Strobe
Reset Data
Available
Status Word
Enable

TDS

4

26
16

SYMBOL
00-07

T9S
T9

ROA
SWE

23

Receive Data
Available

25

Code Violation
Detected

CVO

37

Transmit
Buffer Empty
Receive Bit 9
Receive Bit 10
Recever Turnaround

TBMT

Receive Data
Enable
Receiver
Parity

RDE

14
15
24

5
17

OA

R9
R10
RTA

RP*

*The SYNC bit is included in parity checking.

FUNCTION
Bidirectional: 8 bit, three state data port used to transfer data between the COM
9064 and the processor.
DO is the first bit transmitted.
Input: A low level on this pin enables T9 to be transmitted as bit 9. A high level on
this pin causes T9 to determine the type of parity bit generated for bits 00-07.
Input: If T9S is low, this supplies transmit bit 9. If T9S is high, then T9 low forces
odd parity and T9 high forces even parity to be generated for 00-07. In this case
the parity bit generated is transmit bit 9.
Input: This pin supplies transmit bit 10.
Input: This input controls the parity billor transmit bits 1-10. A low level on this pin
causes odd parity and a high level on this pin causes even parity to be generated
for bits 1-10. The parity bit generated is transmit bit 11.
Input: This signal is used to synchronize the COM 9064. The transmitter is
loaded and started on the low to high transition of SCLK if TOS is low. OA is reset
on the low to high transition of SCLK if ROA is low.
Input: This input and SCLK are used to load the transmitter holding register and
start the transmit sequence. Code Violation Detect (CVO) is reset at this time.
Input: This input and SCLK are used to reset DA.
Input: A low level at this pin enables the status word buffer outputs (DA, CVD,
TBMT, R9, R10, and RTA). A high level on SWE places the status word buffer
outputs in a high impedance state.
This three-state output signal is at a high level when an entire word has been
received and transferred into the receiver buffer register. It is only set if a Transmit
Check Condition did not occur.
This three-state output signal is at a high level if a valid Code Violation was
detected at the receiver since the last time the transmitter was loaded. It is reset
when the transmitter is loaded.
This three-state output signal is at a high level when the transmit holding register
may be loaded with new data.
This three-state output signal is receiver data bit 9.
This three-state output signal is receiver data bit 10.
This three-state output signal is set to a high level when a valid Mini Code
Violation is detected. It is only set if a Transmit Check did not occur. It is reset
when the transmitter is loaded.
Input: A low level enables the outputs of the receive data register 00-07.
Input: This input determines whether the entire received word will be checked for
even or odd parity. A low at this pin will cause a check for odd parity and a high at
this pin will cause a check for even parity. This input has an internal pull-up
resistor.

244

DESCRIPTION OF PIN FUNCTIONS (cont.)
PIN NO.

29

NAME
Analog
Loopback

SYMBOL
ALOOP

34

Digital
Loopback

DLOOP

21

Master Reset

MR

Supply Voltage

Veo
NIC
GND

1
19,22,35
2, 20, 40

Ground

FUNCTION
Input: A low level on this pin disables the receiver except when the transmitter
is active. A high level on this pin and DLOOP will cause the receiver to be
disabled while the transmitter is active.
ALOOP is used to allow loop-back through the line drivers and receivers. This
input has an internal pull-up resistor.
Input: A low level on this pin disables the receiver except when the transmitter
is active. TG is forced to a high level to disable the external coax driver. Data
input to the receiver is internally wrapped from the transmitter data output.
This input has an internal pUil-up resistor.
Input: This input should be pulsed low after power-on. This Signal resets DA to
a low level and sets TG and TBMT to a high level. This input has an internal
pull-up.
+ 5 volt supply
No Connection
GROUND

Device Related Signals
PIN NO.

27

NAME
Baud Rate
Clock

SYMBOL
BCLK

33

Transmit Data

TD

31

Transmit Clock

TC

30
32

Receive Data
Transmit Gate

RD
TG

28

Receive
Single Shot
Enable

RSSE

FUNCTION
This input is a clock whose frequency is 8 times the desired transmitter and
receiver baud rate (typically 18.8696 MHz for 3274/3276 operation). This input
is not TTL compatible.
Output: Serial data from the transmitter. This Signal is a biphase Manchester II
encoded bit stream. This output is low when no data is being transmitted.
The Transmit Clock output is '12 the frequency of BCLK. It is synchronized with
TD and used to provide external pre-distortion timing.
Input: Accepts the serial biphase Manchester II encoded bit stream.
Output: This signal is low during the time that the transmit data is valid. TG is
used to turn on the external transmit circuitry.
Input: A high level on this pin enables an internal digital single shot on RD. This
limits a high level on RD to 3 clock times. Also when high it will cause the
receiver not to detect a valid ~ocJe Violation. A low level disables the single shot
causing no reshaping of the RD input signal.

COM 9064 OPERATION
The COM 9064 consists of a receiver section that converts
Manchester II phase encoded serial data to parallel data
and a transmitter section that converts parallel data to
Manchester II phase encoded serial data.

Receiver
Message transfers must conform to the IBM 3270 protocol
in order for the COM 9064 to acknowledge them.
The received message is checked for the Code Violation
sequence (start sequence) bit pattern, preceding the first
data word, and Mini Code Violation (end sequence)
following the last data word.
The data word consists of 10 data bits, a sync bit and a parity
bit. Receiving data in multiple byte format is functional only
when even parity is selected.
The data word along with the first bit of the next word or
ending zero (bit 13) is shifted into a shift register. Once it is
assembled it is transferred and held in the holding register
until another data word is assembled. The 13th bit is inverted
and presented to the bus or RTA (receiver turn-around).
Therefore RTA is set high on the last word of a message
and is reset when the transmitter is loaded with the
response.
Once the data word is in the holding register and parity is
correct the data available (DA) status signal is set high.
245

The Code Violation Detect signal (CVD) goes active high
after a line Quiesce, Code Violation and sync bit have been
detected by the receiver. It is reset when the transmitter of
the COM 9064 is asserted. By examining this signal, the
processor can determine whether a timeout or Transmit
Check condition caused a receiver error.
The receive input is sampled at 8 times the data rate. The
receiver logic is brought into bit synchronization during the
Line Quiesce pattern. Once the Code Violation following the
Line Quiesce is detected, the receiver is brought into bit and
word synchronization. The internal receiver clock is adjusted
after each transition to cornpensate for jitter and distortion
in the received data signal.

Transmitter
The transrnitter section basically consists of a 12-bit holding
register, parallel to serial shift register and a parity generator.
The firrnware initiates a transmit sequence by strobing TDS
low. The data is loaded into the holding register on the rising
edge of SCLK while TDS is low. Nine bits of data (DO-D7
and T10) are transferred without change to the transmit shift
register. The logic level ofT9S determines whether T9 will be
transmitted as parity on the preceding eight bits, or as data.
After the processor loads the transmit holding register with
data, status signal TBMT is driven inactive low until the COM
9064 transfers the data from the transmit holding register

I

to the transmit shift register. After the transfer, TBMT is
driven high. The processor should not try to load data into
the COM 9064 while TBMT is low. When initiating a data
transmission, the COM 9064 automatically transmits a Line
Quiesce pattern and a Code Violation. The data is then
shifted out of the shift register with a sync bit (1) inserted
before the data word, and a parity bit appended after the
data word.

Diagnostic Modes
NORMAL OPERATION (ALOOP AND DLOOP HIGH)
Internal read data signal follows the RD input as long as the
COM 9064's transmitter is off. The receiver will be disabled
while the transmitter is active.
ANALOG LOOPBACK (ALOOP LOW AND DLOOP
HIGH)
.
The internal read data signal follows the RD input as long
as the COM 9064's transmitter is active.

If a new word is loaded into the COM 9064 before the parity
bit of the previous word has been transmitted, a sync bit (1)
followed by the new data bits is transmitted. If not, after the
COM 9064 transmits the last data word (no more transmit
sequences are started), a sync bit (0) anda Mini Code
Violation is appended to the end of the message.

DIGITAL LOOPBACK ALOOP HIGH AND DLOOP LOW)
The internal read data signal follows an internally generated
and latched valid transmit signal (only when the transmitter
is active.) The output TG is disabled in digital loopback
mode.

Output TG goes active low one-half bit cell time before the
first Line Quiesce character is output. It is made inactive
(high) during the transmission of the Mini Code Violation.

DISABLE RECEIVER (ALOOP AND DLOOP LOW)
The internal read data signal is held low and output TG
is disabled.

MESSAGE FORMATS

CODE
VIOLATION

ENDING
SEQUENCE

SYNC
BIT

CODE
VIOLATION
DATAN
(10 BITS)

SYNC
BIT

Bits on the coax appear as positive and negative going
pulses. A positive pulse to negative pulse transition in the
middle of the bit cell is interpreted as a logical '0'. A negative
pulse to positive pulse transition in the middle of a bit cell is

COAX
IDLE

ENDING
SEQUENCE

PARITY
BIT

interpreted as a logical '1 '. A predistortion pulse is generated
for every pulse transition from an up to down level or a down
to up level.

Line Quiesce Pattern

1

1

,

1

,

__I
1
1
1

1

1

,

,

__ I
1

,

' __ I
1

' __ I
,

lone bit
time

,

~---~------~

,

__ I

,

1

1

1

1

1

1

1

1

1

1

' __ I

1

I

I

,

246

,
1

1
,

The Line Quiesce pattern consists of five contiguous logical
ones. It establishes an equilibrium condition on the coax
following line turnaround.

---------

,

1

,
--l
,
I
,,
I

1

Code Violation Pattern

1

I

1

1

I

__ I
I
1
I
I

I

1

I
I

I

1_ _ 1

1_ _ __

1

I

I

last "1"
of linequiesce

1

I

__ I
I
1

I

I

I

1_-_1
1

code

1

violation

I
I

sync bit

The Code Violation pattern is a bit sequence containing
no mid-bit time level transition in two of its three bit
cells. It is a unique pattern that violates the encoding
rules and indicates the start of valid data.

Mini Code Violation Pattern

11

bit times:

12
p
"1"
or
"0"

I
I

0

I_-

I
I
I
I

2

3

mcv

mcv

I
I
I
I

I
I
last data
byte

Ending Sequence

The Mini Code Violation (MCV) pattern is a bit
sequence containing no mid-bit time level transition
in either of its bit cells. It is a unique code that violates
the encoding rules and indicates the end of valid
transmit data.

Transmit Check
A Transmit Check is defined as follows:
1) A logical zero sync bit in the ending sequence not
followed by a Mini Code Violation.
2) Loss of a level transition at the mid-bit time during
other than a normal ending sequence.
3) A transmission parity error.

247
----

_._----------------------------------

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range .................................................................................. O°C to + 70°C
Storage Temperature Range ................................................................................. - 55° to + 150°C
Lead Temperature (soldering, 10 sec.) ................................................................................ +300°C
Positive Voltage on any I/O Pin, with respectto ground .................................................................. + 8.0V
Negative Voltage on any I/O Pin, with respectto ground ................................................................. - 0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not
be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power
is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. For example, the bench
power supply programmed to deliver + 5 volts may have large voltage transients when the AC power is switched on and off. If this
possibility exists it is suggested that a clamp circuit be used.

DC ELECTRICAL CHARACTERISTICS (TA = O°Cto 70°C, Vee = +5V ±5%)
PARAMETER
DC CHARACTERISTICS
INPUT VOLTAGE
VILLow
V,H High
V,H High
V,H High
OUTPUT VOLTAGE
VOL Low
V OH High

MIN

TYP

-0.3
2.0
4.3
3.5

MAX

UNIT

.8
Vee
Vee+·3
V ee + .3

V
V
V
V

.4

125

(Except BCLK and MR)
(BCLKonly)
(MR only)
10L
10H

2.4

POWER SUPPLY CURRENT
lee
INPUT LEAKAGE CURRENT
All input pins

COMMENTS

= 2.0mA
= -.25 mA

mA

All outputs

.01

mA

V ,N

10
35

pf
pf

= VOH

= Oto Vee

CAPACITANCE
C'N
C'N

(Except BCLK)
(BCLKonly)

AC ELECTRICAL CHARACTERISTICS (TA = O°C to 70°C, Vee = + 5V ± 5%)
PARAMETER
Clock Frequency
BClK
SClK

ClockWidih
SCLKHigh
tSKH
SCLK Low
tSKL
BCLK High
tSKH
BCLKLow
tSKH
t,
BCLK rise time
BCLK fall time
tF
RDE to Data Valid Delay
SWE to Data Valid Delay
Data Read to Bus Float
tDF
t DS
Data Setup Time
Data Hold Time
tDH
DA to receive data
tDAV
valid delay
tTe
TC clock period
tWLD TC to TG low delay
tWHD TC to TG high delay
tTDS Transmit data to TG
setup time
Transmit data to TC
tTDH
hold time
TBMT active to de-active
to
tTDDe TBMT cycle
too TBMT de-activated
TDS set up
tDSS
TDS hold
tOSH
tMR MR pulse width

MIN

TYP

MAX

UNIT

7
DC

18.8696
4.7474

18.9
5

MHz
MHz

6
6
50
50
50

ns
ns
ns
ns
ns
ns
ns
ns
ns

100

ns
ns
ns

80
80
20
20

tRDD

tSDD

100
10
-100
106
-53

30
30

10
20

ns
ns
ns
ns
ns
ns

200
3.2
2
200
100

1
100
10
300

248

j.1S
j.1S

ns
ns
ns

CONDITIONS

TIMING DIAGRAMS

MISC. TIMING

BUS INPUT TIMING

SCLK

BCLK

TDS/RDA*

MR
DATA

RECEIVE DATA TIMING
OA _ _ _ _

VALID DATA

T~

J
I

t OAV"

00-07,
R9. R10

:

~

'Only one rising edge of SCLK within this pulse width.

~--~L~~VA~L]loDo~AIT;JAL=

BUS OUTPUT TIMING

-DA may accor from 100 ns before to 100 ns after data is valid.

RDE

TRANSMITTER TIMING

SWE

TD

1-'11.1-----1

BIT CELL

------.l_1

DATA,
STATUS
VALID

tSDD

------~~~-------)---

TBMT CYCLE
TBMT

..J

I:---tDD

....

r

~""41
...----tDDC-----I"'~1

249

,

'<:
0

~

0

rZ,<:
, 

5

0

w

J-G;~

a:
0

N

~

Z

"-

co
Z

~

Z

i5i
a'i :3

l'i

w

~

:0

0

"l
"-

""



::;:
'<:

...J

0

(f)

'<:

...J

0

Z

~

Z

a:
0

0

z
Ia:

I~

'"

0

0

In

I~

0

a:

Z
J:
u

w

m
N

~

W

Z

Vi

><

ci

J:

u
~~Q;

0

~B~

I-Zo

~~~
:01-'"

>
co

W

I-

>=
w
z
co

ffi ;J

"

~

a:

u

U)

ie
to- -;.

a:

W

0

~

ct
0
0

..:..
ct
0

i:i:

>

I-

"- U) ' "

...-:00::

..:-:wo
_a:u

+

I~-

;:

-0>

a:(/)

tii
0

~_

I/QSTROBE

-l-

r-r-I-I

«

DS
CS

Ig

ERO

OI:U

01:

---1-

8

-

DATA BUS

II I
III I

I

R/W

a

Ul

W

e-( )
I(/)
Z

«
II:
e-

'--

at
(J)«x
~()~-.J

ADDRESS

(J)

'--

64K DYNAMIC RAM

Circuit diagrams utilizing SMC products are included as a means of illustrating typical applications; consequently
complete information sufficient for construction purposes is not necessarily given. The information has been carefully
checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore,
such information does not convey to the purchaser of the products described any license under the patent rights of
SMC or others. SMC reserves the right to make changes at any time in order to improve design and supply the best
product possible.

262

_

Baud Bate Generator

263

264
---- - - - - - - - - - - - - -

-----------------------------------------------

COM 5016
cOM5016T
COM 5036
COM5036T
Dual Baud Rate Generator
Programmable Divider
PIN CONFIGURATION

FEATURES

o On chip crystal oscillator or external
frequency input
o Choice of 2 x 16 output frequencies
o 16 asynchronous/synchronous baud rates
o DIRECT UART/USRT/ASTRO/USYNRT
compatibility
o Full duplex communication capability
o High frequency reference output'
o TTL, MOS compatibility

XTALlEXT1 1

18 XTALlEXT2

\...J

17 IT

+5v 2

16 TA

IR 3
RA 4

15 TB

RB 5

14 Tc

Rc 6

13 To

Ro 7

12 STT

STR·8

11 GND

+12v 9

10 Ixl4'

BLOCK DIAGRAM
STT

T.
T,

REPROGRAMMABLE
FREQUENCY SELECT

Tc

To

XTAUEXTl

DIVIDER

+2

fr

DIVIDER

+2

fR

XTAL

L

CLOCK

BUFFER

XTALlEXT2

A A

+5v

·COM 5036/T only

265

J..

GND +12v

General Description
The Standard Microsystems COM 5016/COM 5036 Dual Baud Rate Generator/Programmable Divider is an N-channel
COPLAMOS® MaS/LSI device which. from a single crystal (on-chip oscillator) or input frequency is capable of generating
32 externally selectable frequencies.
The COM 5016/COM 5036 is specifically dedicated to generating the full spectrum of 16 asynchronous/synchronous data
communication frequencies as shown in Table 1. One of the sixteen output frequencies is externally selected by four address
inputs. on each of the independent dividers. as shown in Table 1.
Internal re-programmable ROM allows the generation of other frequencies from other crystal frequencies or input frequencies. The four address inputs on each divider section may be strobe (150ns) or DC loaded. As the COM 5016/COM 5036
is a dual baud rate generator. full duplex (independent receive and transmit frequencies) operation is possible.
The COM 5016/COM 5036 is basically a programmable 15-stage feedback shift register capable of dividing any modulo
up to (2 15 -1).
By using one of the frequency outputs it is possible to generate additional divisions of the master clock frequency by
cascading COM 5016/COM 5036·s. The frequency output is fed into the XTALlEXT input on a subsequent device. In this way
one crystal or input frequency may be used to generate numerous output frequencies.
The COM 5016/COM 5036 can be driven by either an external crystal orTTL logic level inputs; COM 5016T/COM 5036T
is driven by TTL logic level inputs only.
The COM 5036 provides a high frequency reference output at one-quarter (1/4) the XTALlEXT input frequency.

Description of Pin Functions
Pin No.

Symbol

Name

Function

XTAL/EXT1

2
3
4-7
8

Crystal or
External Input 1
Power Supply
Vee
Receiver Output
f.
Frequency
RA• RB• Re. Ro Receiver-Divisor
Select Data Bits
Strobe-Receiver
STR

10
11
12

Voo
fx/4'
GND
STT

Power Supply
fx/4
Ground
StrobeTransmitter

13-16

To. Te. T B• TA

17

fT

18

XTALlEXT2

TransmitterDivider
Select Data Bits
Transmitter
Output
Frequency
Crystal or
External Input 2

9

'COM 5036/T only

This input is either one pin of the crystal package or one polarity
of the external input.
+ 5 volt supply
This output runs at a frequency selected by the Receiver divisor
select data bits.
The logic level on these inputs. as shown in Table 1. selects the
receiver output frequency. fRo
A high level input strobe loads the receiver data (R A• R B• Re. Ro) into
the receiver divisor select register. This input may be strobed or
hard-wired to a high level.
+ 12 volt supply
1f4 crystal/ clock frequency reference output.
Ground
A high level input strobe loads the transmitter data (T A • T B• Te. To)
into the transmitter divisor select register. This input may be
strobed or hard-wired to a high level.
The logic level on these inputs. as shown in Table 1. selects the
transmitter output frequency. fT'
This output runs at a frequency selected by the Transmitter divisor
select data bits.
This input is either the other pin of the crystal package or the
other polarity of the external input.

For electrical characteristics. see page 221.

266

COM 5026
cOM5026T
COM 5046
cOM5046T
Baud Rate Generator
Programmable Divider
FEATURES

PIN CONFIGURATION

o On chip crystal oscillator or external
frequency input
o Choice of 16 output frequencies
o 16 asynchronous/synchronous baud rates
o Direct UART/USRT/ASTRO/USYNRT
compatibility
o High frequency reference output*
o TTL, MaS compatibility

XTAUEXT1 1

14

\...J

XTAL/EXT2 2

tOUT

13 A

+5v 3

12

B

NC 4

11 C

GND 5

10 D

NC 6

9

ST

+12v 7

8

f)(/4*

BLOCK DIAGRAM

ST

A

REPROGRAMMABLE
FREQUENCY SELECT

B
C
D

ROM

XTAUExn
DIVIDER

XTAL

~
~----~~----~
CLOCK
BUFFER

XTAUEXT2

r

+2

fOUT

---------------,

I ~

+4

~_______ J

_______

A A J..
+5v

*COM 5046/T only

267

GND

+12v

~J

GENERAL DESCRIPTION
The Standard Microsystems COM 5026/COM 5046 Baud Rate Generator/Programmable Divider is an N-channel
COPLAMOS® MaS/LSI device which, from a single crystal (on-chip oscillator) or input frequency is capable of generating
16 externally selectable frequencies.
The COM 5026/COM 5046 is specifically dedicated to generating the full spectrum of 16 asynchronous/synchronous data
communication frequencies as shown in Table 1. One of the sixteen output frequencies is externally selected by four address
inputs; as shown in Table 1.
Internal re-programmable ROM allows the generation of other frequencies from other crystal frequencies or input frequencies. The four address inputs may be strobe (150ns) or DC loaded.
The COM 5026/COM 5046 is basically a programmable 15-stage feedback shift register capable of dividing any modulo
upto (2"-1).
By using the frequency output, it is possible to generate additional divisions of the master ciock frequency by cascading
COM 5026/COM 5046's. The frequency output is fed into the XTALlEXT input on a subsequent device. In this way one crystal
or input frequency may be used to generate numerous output frequencies.
The COM 5026/COM 5046 can be driven by either an external crystal or TTL logic level inputs COM 5026T/COM 5046T
is driven by TTL logic level inputs only.
THE COM 5046 provides a high frequency reference output at one-quarter (1 /4) the XTALlEXT input frequency.

Description of Pin Functions
Pin No.

Symbol

Name

Function

XTAL/EXT1

Crystal or
External Input 1

This input is either one pin of the crystal package or one polarity
of the external input.

2

XTAL/EXT2

Crystal or
External Input 2

This input is either the other pin of the crystal package or the
other polarity of the external input.

3

Vee

Power Supply

+ 5 volt Supply.

4,6

NC

No Connection

GND

Ground

Ground

7

Voo

Power Supply

+ 12 volt Supply.

8

fx/4*

Reference
Frequency

High frequency reference output@ (1/4) fiN

9

ST

Strobe

A high-level strobe loads the Input Address (AA, AB, Ac, Ao)
into the Input Address register. This input may be strobed or
hard wired to a high-level,

Ao. Ae. AB. AA

Input Address

The logic level on these inputs. as shown in Table 1, selects
the output frequency.

fouT

Output
Frequency

This output runs at a frequency as selected by the Input Address.

5

10-13
14

*COM 5046/T only

268

ELECTRICAL CHARACTERISTICS COM5016, COM5016T, COM5026, COM5026T,
COM5036, COM5036T, COM5046, COM5046T
MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range .................................................. . ........... O'C to + 70'C
Storage Temperature Range .............................................................. -55'C to + 150'C
Lead Temperature (soldering, 10 sec.) .............................................................. +325'C
Positive Voltage on any Pin, with respect to ground .................................................... +18.0V
Negative Voltage on any Pin, with respect to ground .................................................... -0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.

ELECTRICAL CHARACTERISTICS (TA= O'C to 70'C, Vee = + 5V:±: 5%, Voo= + 12V:±: 5%, unless otherwise noted)
Parameter

Min.

D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, V'L
High-level, V'H
OUTPUT VOLTAGE LEVELS
Low-level, VOL

Typ.

2.0

High-level, VOH
INPUT CURRENT
Low-level, III
INPUT CAPACITANCE
All inputs, C'N
EXT INPUT LOAD
POWER SUPPLY CURRENT
Ice
100
A.C. CHARACTERISTICS
CLOCK FREQUENCY
PULSE WIDTH
Clock
Strobe
INPUT SET-UP TIME
Address
INPUT HOLD TIME
Address
STROBE TO NEW FREQUENCY DELAY

Vee-1.5

Max

Unit

Comments

0.8
Vee

V
V

excluding XT AL inputs

0.4
0.5

V
V
V

4.0

IOL
10L

= 1.6ma
= 3.2ma

10H = WOILA

0.3

mA

V'N = GND, excluding XTALinputs

5
8

10
10

pi

V'N = GND, excluding XTAL inputs
Series 7400 unit loads

28
12

45
22

mA
mA
MHz

5.0688

TA = +25'C
XTAL, EXT

ns

50% Duty Cycle :±:5%
See Note 1.

50

ns

See Note 1.

50

ns
ILS

= 1 If'N (18)

150

DC

3.5

Note1: Input set-up time can be decreased to;;" Ons by increasing the minimum strobe width by 50ns to a total 01 200ns.

TIMING DIAGRAM

I

NOTE 1

~
I
I
1/

- - - +001----

r----i-J-------------"

V'H

/
/

STROBE CST)

/

I

V,L---L----J

"Address need only be valid during the last Tpw, Min time of the input strobe.

269

Crystal Operation
COM5016
COM5036

External Input Operation
COM5016/COM5016T
COM5036/COM5036T

74XX
TTL

74XX
TTL

74XX-totem pole or open collector output (external
pull-up resistor required)

Crystal Operation
COM5026
COM5046

External Input Operation
COM5026/COM5026T
COM5046/COM5046T

74XX
TTL

74XX
TTL

74XX-totem pole or open collector output (external
pull-up resistor required)

For ROM re-programming SMC has a computer program available whereby the customer
need only supply the input frequency and the desired output frequencies.
The ROM programming is automatically generated.

Crystal Specifications
User must specify termination (pin, wire, other)
Prefer: HC-18/U or HC-25/ U
Frequency - 5.0688 MHz, AT cut
Temperature range O'C to 70'C
Series resistance < 50 f1
Series Resonant
Overall tolerance :t .01 %
or as required

270

Crystal manufacturers (Partial List)
Northern Engineering Laboratories
357 Beloit Street
Burlington, Wisconsin 53105
(414) 763-3591
Bulova Frequency Control Products
61-20 Woodside Avenue
Woodside, New York 11377
(212) 335-6000
CTS Knights Inc.
101 East Church Street
Sandwich, Illinois 60548
(815) 786-8411
Crystek Crystals Corporation
1000 Crystal Drive
Fort Myers, Florida 33901
(813) 936-2109

APPLICATIONS INFORMATION
+5.0v

Charge pump techniques
using the + 5 volt power
supply can be used to
generate the + 12 volt
power supply required.
The + 12 volt power
supply of figure 1 will
supply the 22 milli- amps
that is typically required.

+12v
OUT
12v

280n

Figure 1

100pf

VOLTAGE CHARGE PUMP
SUPPLY FOR +12v SUPPLY

To Chip Power
Supply Pin

From Power
Supply

When powering this device from laboratory - - - - . - - - - -........----~~-­
or system power supplies, it is important
that the Absolute Maximum Ratings not be
exceeded or device failure can result. Some
power supplies exhibit voltage spikes
or "glitches" on their outputs when the AC
power is switched on and off. In addition,
voltage transients on the AC power line
may appear on the DC output. For example,
the bench power supply programmed to
1N914
Typ.
deliver + 12 volts may have large voltage
transients when the AC power is switched
on and off. If this possibility exists it is
suggested that the clamp circuit of figure 2
or a Semtech'bi-polarity silicon transient
Figure 2
suppressor such as the 1N611 0 be used.
'SEMTECH CORPORATION
652 Mitchel Road
Newbury Park, California 91320
213-628-5392

271

OVER-VOLTAGE
PROTECTION
CIRCUIT

COM5016, COM5016T, COM5026, COM5026T,
COM5036, COM5036T, COM5046, COM5046T

Baud Rate Generator Output Frequency Options
'table 1.
CRYSTAL FREQUENCY
Tr'mit/Receive
Address
C B A

0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Baud
Rate

Theoretical
Frequency
16XCIock

50
0.8 KHz
75
1.2
110
1.76
134.5
2.152
150
2.4
3do
4.8
600
9.6
1200
19.2
1800
28.8
2000
32.0
2400
38.4
3600
57.6
4800
76.8
7200
115.2
153.6
9600
19.200 307.2

(16X clock)

Table 2.

= 5.0688 MHz

Actual

Frequency
16XCIock

Percent
Error

0.8 KHz
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8

0.016

0.253

3.125

CRYSTAL FREQUENCY
Duty
Cycle
Divisor
%

0

C

B

A

50/506336
50/504224
50/502880
50/50 2355
50/502112
50/50 1056
50/50 528
50/50 264
50/50 176
50/50 158
50/50 132
50/50
88
50/50
66
44
50/50
48/52
33
50/50
16

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Tr'mlt/Receive
Address

Theoretical
Frequency
16X Clock

Baud
Rate

0.8 KHz
50
75
1.2
110
1.76
134.5
2.152
150
2.4
300
4.8
600
9.6
1200
19.2
1800
28.8
2000
32.0
2400
38.4
3600
57.6
4800
76.8
115.2
7200
9600
153.6
19,200 307.2

(32X clock)

Table 3.
CRYSTAL FREQUENCY = 5.0688 MHz
Tr'mlt/Recetve
Address
0
C B A

0
0
0
0
0
0
0
0
1
1

1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Theoretical

Actual

Baud

Frequency

Frequency

Percent

Rate

32X Clock

32X Clock

Error

50
75
110
134.5
150
200
300
600
1200
1800
2400
3600
4800
7200
9600
19,200

1.6KHz
2.4
3.52
4.304
4.8
6.4
9.6
19.2
38.4
57.6
76.8
115.2
153.6
230.4
307.2
614.4

1.6KHz
2.4
3.52
4.306
4.8
6.4
9.6
19.2
38.4
57.6
76.8
115.2
153.6
230.4
316.8
633.6

.06

3.125
3.125

OUTPUT FREQUENCY OPTIONS
Part No.

Dash Number

Table 1

5016/5016T
5026/5026T
5036/5036T
5046/5046T

STD

Table 2

-5

Table 3

-6

STO

-5

-6

STD
STD

N/A
N/A

N/A
N/A

·When Duty Cycle is not exactly 50%, it is50%± 10%.

272

Duty
Cycle
%

Divisor

50/50 3168
50/50 2112
50/50 1440
1177
50/50 1056
50/50 792
50/50 528
50/50 264
50/50 132
50/50
88
50/50
66
50/50
44
33
22
50/50
50/50
16
50/50
8

(16X clock)

= 4.9152 MHz

Actual

Frequency

Percent

16X Clock

Error

0.8 KHz
1.2
1.7589
2.152
2.4
4.8
9.6
19.2
28.7438
31.9168
38.4
57.8258
76.8
114.306
153.6
307.2

-0.01

-0.19
-0.26
0.39
-0.77

Duty
Cycle
%

Divisor

50/506144
50i50 4096
2793
50/50 2284
50/50 2048
50/50 1024
50/50 512
50/50 256
171
50/50 154
50/50 128
85
64
5Oi5O
43
50/50
32
50/50
16

COM 8046
COM8046T

Baud Rate Generator
Programmable Divider
FEATURES

o On chip crystal oscillator or external
frequency input
o Single + 5v power supply
o Choice of 32 output frequencies
032 asynchronous/synchronous baud rates
o Direct UART /USRT / ASTRO/USYNRT

PIN CONFIGURATION
XTAL/EXT1
XTAL/EXT2 2

compatibility
ORe-programmable ROM via CLASp®
technology allows generation of other
frequencies
TTL, MaS compatible
1XClockviafo/16output
Crystal frequency output via fx and fx/4
outputs
Output disable via FENA

+5v 3
tx 4
GND 5
to/16 6

FENA 7
E 8

o
o
o
o

'---./

16 to
15 A
14 B
13 C
12 0
11 ST
10 tx/4
9 NC

BLOCK DIAGRAM
ST>---'

A
B
C
D
E

REPROGRAM MABLE
FREQUENCY SELECT
DIVIDER
ROM

10
XTALlEXT1

XTAL

L

DIVIDER

CLOCK

XTALlEXT2

BUFFER

10/16
FENA

Ix

A

~

fx/4

+5v GND

273

General Description
The Standard Micrcisystems' COM 8046 is an enhanced version of the COM .50,46 .Baud Rate
Generator. It is fabricated using. SMC's patented
COPLAMOS® and, CLASp® technologies and employs depletion mode loads, allowing operation from
a single +5v supply.
The standard COM 8046 is specifically'dediCilted to
generating the 'full spectrum of 16 asynchronous/
synchronous data c,ommunicatioo 'fr,equencies for 1X,
16X and 32X, UART/USRT/ ASTRO/USYNRT devices.
The COM 8046 features an inte~nal crystal 9scillator
which may be used toprovid!'l the master reference
frequency. Alternatively, an external reference may be
supplied by applying complementary TTL level signals to pins 1 aric;l2. Parts suitable for use only with an
external TTL reference are milrked COM 8046T. TTL
outputs used to drive the COM 8046 or COM 8046T
should not be usea to drive other TTL inputs, as noise
immunity may be compromised dile to excessive
loading.
The reference frequency (fx) is used to provide two
high frequency outputs: one at fx and the other at
fx/4. The fx/4 output will drive one standard 7400
load, while the fx output will drive two 74LS loads.
The output of,the oscillator/buffer is applied to the
divider for generation of the output frequency fo. The
divider is capable of dividing by any integer from 6

to 2" + 1, inclusive. If the divisor is' even, the output
wilt. be square; otherwise the ,output will be high
longer than it is low by one fx clock period. The output
of the divid!'lr is also divided internally by 16 arid made
available.at the fo/1,6 output pin. The fo/16 output will
drive one and the fooutput will drive tWo standard
7400 TTL loads. Both1he fo aod fo/16 outputs can be
disabled by sUpplying a low logic level to the FENA
input "in. 'Note that ,the, FENA input has an internal
pUll-up wj'lich will 'cause the pin to rise to approximately Vee if left unconnected.
The divisor ROM contains 32 divisors, each 19 bits
wide, and is fabricated using SMC's unique CLASP®
technology. This process permits reduction of turnaround-time for ROM patterns.
'
The five 'divisor select bits are held in an externally
strobed data latch .. The strobe input is level sensitive:
while, the !?trobe is high, datil is passeq directly
through to the ROM. Initiation of a new frequency is
effected within 3.51's of a change hi any of the five
divisorsel!'lct bits; strobe ac;tivity is ootrequired.
This feature may be disabled through a CLASP~ programming option causing new frequsl)cy initiation to
be delayed until the end of the current fo half-cycle
All five data Inpilts have pull-ups identical to that
of the FENA input, while the strobe input has no
pull-up.

Description of Pin Functions
Pin No.

Symbol

Name

Function

XTAL/EXT1

C.rystalor
External Input 1
Crystal or
External Input 2
Power Supply
fx
Ground

This input is either one pin of the crystal package or one polarity
ofthe external input.
This input is either the other pin of the crystal package or the other
polarity of the external input.
+ 5 volt supply
Crystal/clock frequency reference output
Ground.
1X clock output
A low level at this inpLit causes the fa and fo/16 outputs to be
held high. An open or a high level at the FENA input enables the
fo and fo/16 outputs.
Most significant divisor select data bit. An open at this input is
equivalent to a logic high.
No connection
1A crystal! clock frequency reference output.
Divisor select data strobe. Data is sampled when this Input is high,
preserved when this input is low.
Divisor select data bits. A= LSB. An open circuit at these inputs
is equivalent to a logic high.
16X clock output

2

XTALlEXT2

3
4
5
6
7

Vee
fx
GND
fo/16
FENA

8

E

9
10
11

NC

NC

fx/4

fx/4

ST

Strobe

12-15

D,C,B,A

D,C,B,A

16

fo

fo

fo/16

Enable
E

For electrical characteristics, see page 231.

274

-_

....

_------------------

COM 8116
COM 8116T
COM 8136
COM 8136T
Dual Baud Rate Generator
Programmable Divider
FEATURES

PIN CONFIGURATION

o On chip crystal oscillator or external

XTALlEXT1 1

frequency input

o Single +5v power supply

18 XTALlEXT2

\...J

17 IT

+5v 2

o Choice of 2 x 16 output frequencies
016 asynchronous/synchronous baud rates
o Direct UART/USRT/ ASTRO/USYNRT
compatibility
o Full duplex communication capability

o High frequency reference output*

ORe-programmable ROM via CLASp®
technology allows generation of other
frequencies
TTL, MaS compatibility
Compatible with COM 5016/COM 5036

fR 3

16 TA

RA 4

15 T,

R, 5

14 Tc

Rc 6

13 TD

RD 7

12 STT

STR 8

11 GND

NC 9

10 fxl4'

o

o

BLOCK DIAGRAM
sn
T.

REPROGRAMMABLE
FREQUENCY SELECT

T,
Tc
To

XTAUEXTI

DIVIDER

+2

fT

DIVIDER

+2

fR

XTAl

L

CLOCK

BUFFER

XTAUEXT2

A A

+5v

'COM 81361T only

215

GND

General Description
The Standard Microsystem's COM 8116/COM 8136 is an
enhanced version of the COM 5016/COM 5036 Dual Baud
Rate Generator. It is fabricated using SMC's patented
COPLAMOS® and CLASP® technologies and employs
depletion mode loads, allowing operation from a single + 5v
supply.
The standard COM 8116/COM 8136 is specifically dedicated to generating the full spectrum of 16 asynchronousl
synchronous data communication frequencies for 16X
UART/USRT devices. A large number of the frequencies
available are also useful for 1X and 32X ASTRO/USYNRT
devices.
The COM 8116/COM 8136 features an internal crystal oscillator which may be used to provide the master reference
frequency. Alternatively, an external reference may be supplied by applying complementary TTL level signals to pins
1 and 18. Parts suitable for use only with an external TTL
reference are marked COM 8116T/COM 8136T. TTL outputs used to drive the COM 8116/COM 8136 or COM 8116TI
COM 8136T XTALlEXT inputs.should not be used to drive

other TTL inputs, as noise immunity may be compromised
due to excessive loading.
The output of the oscillator/buffer is applied to the dividers
for generation of the output frequencies fT' fRo The dividers
are capable of dividing by any integer from 6 to 2 19 + 1,
inclusive. If the divisor is even, the output will be square;
otherwise the output will be high longer than it is low by one
fx clock period.
The reference frequency (fx) is used to provide a high frequency output at fxl4 on the COM 81361T.
Each of the two divisor ROMs contains 16 divisors, each 19
bits wide, and is fabricated using SMC's unique CLASP®
technology allowing up to 32 different divisors on custom
parts. This process permits reduction of turn-around time
for ROM patterns. Each group of four divisor select bits is
held in an externally strobed data latch. The strobe input is
level sensitive: while the strobe is high, data is passed directly
through to the ROM. Initiation of a new frequency is effected
within 3.5JLs of a change in any of the four divisor select bits
(strobe activity is not required). The divisor select inputs have
pull-up resistors; the strobe inputs do not.

Description of Pin Functions
Pin No.

Symbol

Name

Function

XTALlEXT1

2
3
4-7
8

Crystal or
External Input 1
Power Supply
Vee
Receiver Output
fR
Frequency
RA, R B, Re, Ro Receiver-Divisor
Select Data Bits
STR
Strobe-Receiver

9
10
11
12

NC
fx/4 •
GND
STT

No Connection
fxl4
Ground
StrobeTransmitter

13-16

To, T e, T B, TA

17

fT

18

XTAL/EXT2

TransmitterDivider
Select Data Bits
Transmitter
Output
Frequency
Crystal or
External Input 2

'COM 81361T only

This input is either one pin of the crystal package or one polarity
of the external input.
+ 5 volt supply
This output runs at a frequency selected by the Receiver divisor
select data bits.
The logic level on these inputs, as shown in Table 1, selects the
receiver output frequency, fRO
A high level input strobe loads the receiver data (R A, R B, Re, Ro) into
the receiver divisor select register. This input may be strobed or
hard-wired to a high level.

V4 crystal/ clock frequency reference output.
Ground
A high level input strobe loads the transmitter data (T A, T B, T e, To)
into the transmitter divisor select register. This input may be
strobed or hard-wired to a high level.
The logic level on these inputs, as shown in Table 1, selects the
transmitter output frequency, fT'
This output runs at a frequency selected by the Transmitter divisor
select data bits.
This input is either the other pin of the crystal package or the
other polarity of the external input.

For.electrical characteristics, see page 231.

276

COM 8126
COM 8126T
COM 8146
COM 8146T

Baud Rate Generator
Programmable Divider
FEATURES

PIN CONFIGURATION

o On chip crystal oscillator or external
frequency input
o Single + 5v power supply
o Choice of 16 output frequencies
016 asynchronous/synchronous baud rates
o Direct UART/USRT/ASTRO/USYNRT
compatibility
o High frequency reference output"

XTAUEXT1 1

\J

14 fouT

XTAUEXT2 2

13 A

+5v 3

12 B

ORe-programmable ROM via CLASp®
technology allows generation of other
frequencies
TTL, MaS compatibility
Compatible with COM 5026/COM 5046

NC 4

11 C

GND 5

10 0

o
o

NC 6

9

ST

NC 7

8

fx/4 '

BLOCK DIAGRAM

ST"--A

REPROGRAM MABLE
FREQUENCY SELECT

B

C
ROM

D

XTALlEXT1
DIVIDER

XTAL

L

CLOCK

BUFFER

XTAUEXT2

+2

fouT

t-----..----I
' " - -_ _ _ _ _ _ _ _ _- - '

,------------------------,
I

I

I

+4

I

fx/4' I

~---------~
A

L _____________ J

~

+5v

'COM 81461T only

277

GND

General Description
The Standard Microsystem's COM 8126/COM 8146 is
an enhanced version of the COM 5026/COM 5046 Baud
Rate Generator. It is fabricated using SMC's patended
COPLAMOS® and CLASp® technologies and employs
depletion mode loads, allowing operation from a single
+5vsupply.
The standard COM 8126/COM 8146 is specifically dedicated to generating the full spectrum of 16 asynchronous/
synchronous data communication frequencies for 16X
UART/USRT devices. A large number of the frequencies
available are also Llseful for 1X and 32X ASTRO/USYNRT
devices.
The COM 8126/COM 8146 features an internal crystal oscillator which may be used to provide the master reference
frequency. Alternatively, an external reference may be supplied by applying complementary TTL level signals to pins
1 and 2. Parts suitable for use only with an external TTL reference are marked COM 8126T/COM 8146T. TTL outputs
used to drive the COM 8126/COM 8146 or COM 8126T/COM
8146T XTALlEXT inputs should not be used to drive other
TTL inputs, as noise immunity may be compromised due to
excessive loading.

The output of the oscillator/buffer is applied to the divider
for generation of the output frequency. The divider is capable of dividing by any integer from 6 to 2'9 + 1, inclusive. If
the divisor is even, the output will be square; otherwise the
output will be high longer than it is low byonefx clock period.
The reference frequency (fx) is used to provide a high frequency output at fxl4 on the COM 81461T.
The divisor ROM contains 16 divisors, each 19 bits wide,
and is fabricated using SMC's unique CLASp® technology.
This process permits reduction ofturnaround time for ROM
patterns. The four divisor select bits are held in an externally strobed data latch. The strobe input is level sensitive:
while the strobe is high, data is passed directly through to
the ROM. Initiation of a new frequency is affected within
3.5f1s of a change in any of the four divisor select bits (strobe
activity is not required). This feature may be disabled through
a CLASp® programming option causing new frequency initiation to be delayed until the end of the current fOlfT half-cycle.
The divisor select inputs have pull-up resistors; the strobe
input does not.

Description of Pin Functions
Pin No.

Symbol

Name

Function

XTALlEXT1

Crystal or
External Input 1
Crystal or
External Input 2
Power Supply
No Connection
Ground
fx/4
Strobe

This input is either one pin of the crystal package or one polarity
of the external input,
This input is either the other pin of the crystal package or the other
polarity of the external input.
+5 volt supply

2

XTAL/EXT2

3
4,6,7
5
8

Vee

9

NC
GND
fx/4 •
ST

10-13

D,C,B,A

14

fOUT

Divisor Select
Data Bits
Output
Frequency

Ground

V4 crystall clock frequency reference output.
A high level strobe loads the input data (A, B, C, D) into the input
divisor select register. This input may be strobed or hard-wired to
a high level.
The logic level on these inputs as shown in Table 1, selects the
output frequency.
This output runs at a frequency selected by the divisor select
data bits.

'COM 81461T only

278

ELECTRICAL CHARACTERISTICS COM8046, COM8046T, COM8116, COM8116T, COM8126,
COM8126T, COM8136, COM8136T, COM8146, COM8146T

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range ...............................................................O°C to + 70°C
Storage Temperature Range .............................................................. - Ssoc to + lS0°C
Lead Temperature (soldering, 10 sec.) ............................................................... + 32SoC
Positive Voltage on any Pin, with respect to ground .................................................... + 8.0V
Negative Voltage on any Pin. with respect to ground .............. ' ...... , ................................ -0.3V
<'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies
exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on and off.
In addition, voltage transients on the AC power line may appear on the DC output. If this possibility
exists it is suggested that a clamp circuit be used.
ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C, Vee= +SV:tS%, unless otherwise noted)
Parameter

Min.

D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, VOL
High-level, V'H
OUTPUT VOLTAGE LEVELS
LoW-level, VOL

High-level, VOH
INPUT CURRENT
Low-level, IOL
INPUT CAPACITANCE
All inputs, C,"
EXT INPUT LOAD
POWER SUPPLY CURRENT

Typ.

Max.

Unit

0.8

V
V

excluding XTAL inputs

0.4
0.4
0.4

V
V
V
V

forf x/4, fo/16
3.2mA, for fo, fR' fT
10L = 0.8mA, for fx
IOH=-100I'A; for f" IOH=-SOI'A

-0.1

mA

V," = GND, excluding XTAL inputs

10
10

pF

V," = GND, .excluding XTAL inputs
Series 7400 equivalent loads

SO

mA

0.01

7.0

MHz

0.01

S.l

MHz

lS0

DC

ns

2.0

3.S

S
8

Icc
A.C. CHARACTERISTICS
CLOCK FREQUENCY, f,"

STROBE PULSE WIDTH, tpw
INPUT SET-UP TIME
tos
INPUT HOLD TIME
tOH
STROBE TO NEW FREQUENCY DELAY

Comments

10L =1.6mA;
10L =

TA'= +2SoC
XTALlEXT, SO% Duty Cycle :tS%
COM 8046, COM 8126, COM 8146
XTALlEXT, SO% Duty Cycle ±S%
COM 8116, COM 8136

ns

200
SO
3.S

ns
I'S

@f,=5.0MHz

TIMING DiAGRAM
~-----Irw-----_~

STROBE

I---------tos ------"----J

DIVISOR
SELECT
DATA

V'H

279
- - _.._ - - -

Crystal Operation
COM 8116
COM 8136

External Input Operation
COM 8116/COM 8116T
COM 8136/COM 8136T

74XX

TIL

74XX-totem pole or open collector output (external
pull-up resistor required)

Crystal Operation
COM 8126
COM 8146
COM 8046

Exlernal.lnput Operation
COM 8126/COM 8126T
COM 8146/COM 8146T
COM 8046/COM 8046T

74XX

74XX

TTL

TTL

74XX-totem pole or open collector output (external
pull-up resistor required)

For ROM re-programming SMC has a computer program available whereby the customer
need only supply the input frequency and the desired output frequencies.
The ROM programming is automatically generated.

Crystal Specifications
User must specify termination (pin, wire, other)
Prefer: HC-18/U or HC-25/ U
Frequency - 5.0688 MHz, AT cut
Temperature range O'C to 70'C
Series resistance <50 n
Series Resonant
Overall tolerance ± .01 %
or as required

280

Crystal manufacturers

(Partial List)

Northern Engineering Laboratories
357 Beloit Street
Burlington, Wisconsin 53105
(414) 763-3591
Bulova Frequency Control Products
61-20 Woodside Avenue
Woodside, New York 11377
(212) 335-6000
CTS Knights Inc.
10.1 East Chu rch Street
Sandwich. Illinois 60548
(815) 786-8411
Crystek Crystals Corporation
1000 Crystal Drive
Fort Myers, Florida 33901
(813) 936-2109

COM 8046
COM8046T

I

Table 2
REFERENCE FREQUENCY=5.068800MHz
Divisor
Select

EDCBA
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

Desired
Baud
Rate
50.00
75.00
110.00
134.50
150.00
200.00
300.00
600.00
1200.00
1800.00
2400.00
3600.00
4800.00
7200.00
9600.00
19200.00
50.00
75.00
110.00
134.50
150.00
300.00
600.00
1200.00
1800.00
2000.00
2400.00
3600.00
4800.00
7200.00
9600.00
19200.00

Clock
Factor
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X

Desired
Frequency
(KHz)
1.60000
2.40000
3.52000
4.30400
4.80000
6.40000
9.60000
19.20000
38.40000
57.60000
76.80000
115.20000
153.60000
230.40000
307.20000
614.40000
0.80000
1.20000
1.76000
2.15200
2.40000
4.80000
9.60000
19.20000
28.80000
32.00000
38.40000
57.60000
76.80000
115.20000
153.60000
307.20000

Divisor
3168
2112
1440
1177
1056
792
528
264
132
88
66
44
33
22

Hi

8
6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16

281

Actual
Baud
Rate
50.00
75.00
110.00
134.58
150.00
200.00
300.00
600.00
1200.00
1800.00
240p.OO
3600.00
4800.00
7200.00
9900.00
19800.0p
50.00
75.00
110.pO
134.52
150.00
30p.00
600.00
1200.00
1800.00
2005.06
2400.00
3600.00
4800.00
7200.00
9600.00
19800.00

Actual
Frequency
(KHz)
1.600000
2.400000
3.520000
4.306542
4.800000
6.400000
9.600000
19.200000
38.400000
57.600000
76.800000
115.200000
153.600000
230.400000
316.800000
633.600000
0.800000
1.200000
1.760000
2.152357
2.400000
4.800000
9.600000
19.200000
28.800000
32.081013
38.400000
57.600000
76.800000
115.200000
153.600000
316.800000

Deviation
0.0000%
0.0000%
0.0000%
0.0591%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
3.1250%
3.1250%
0.0000%
0.0000%
0.0000%
0.0166%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.2532%
O.OOOP%
0.0000%
0.0000%
0.0000%
0.0000%
3.1250%

COM8116, COM8116T, COM8126, COM8126T
COM8136, COM8136T, COM8146, COM8146T

Baud Rate Generator Output Frequency Options
(16X clock)

Table 1.
Tr'mlt/Receive
Address

0

C B

A

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Theoretical
Baud
Rate

Frequency
16X Clock

50
0.8 KHz
75
1.2
110
1.76
134.5
2.152
150
2.4
4.8
300
600
9.6
1200
19.2
28.8
1800
2000
32·0
2400
38.4
3600
57.6
76.8
4800
72QO
115.2
9600
153.6
19.200 307.2,

Actual
Frequency

16X Clock

0.8 KHz
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8

Percent
Error

CRYSTAL FREQUENCY = 4.9152 MHz
Duty
Cycle
%
Divisor

Tr'mlt/Receive

Address
C B A

0

SO/50 6336
50/504224
SO/50 2880
0.016 SO/50 2355
50/502112
SO/50 1056
50/50 528
SO/50 264
SO/50 176
0.253 SO/50 158
SO/50 132
SO/50
88
SO/50
66
SO/50
44
48/62
33
3.125 SO/50
16

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Theoretical

Baud

Frequency

Rate

16X Clock

50
0.8 KHz
75
1.2
110
1.76
134.5
2.152
2.4
150
300
4.8
600
9.6
1200
19.2
1800
28.8
2000
32.0
2400
38.4
3600
57.6
4800
76.8
7200
115.2
9600
153.6
19,200 307.2

(32X clock)

Table 3.
CRYSTAL FREQUENCY
Tr'mit/Rece!V8

0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Address
C B A

0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

(16X clock)

Table 2.

CRYSTAL FREQUENCY = 5.0688 MHz

=5.0688 MHz
Duty

Baud

Frequency'

Actual
Frequency

Percent

Rate

32X Clock

32XCIock

Error

Theoretical

50
75
110
134.5
150
200
300
600
1200
1800
2400
3600
4800
7200
9600
19,200

1.6KHz
2.4
3.52
4.304
4.8
6.4
9.6
19.2
38.4
57.6
76.8
115.2
153.6
230.4
307.2
614.4

1.6KHz
2.4
3.52
4.306
4.8
6.4
9.6
19.2
38.4
57.6
76.8
115.2
153.6
230.4
316.8
633.6

.06

3.125
3.125

OUTPUT FREQUENCY OPTIOIIIS
Table 1

Dash Number
Table 2

Tabla 3

sro
sro

-5
-5

-6
-6

·When Duty Cycle is not exactly 50%, it is 50% ± 10%.

282

Cycle
% Divisor

SO/50 3168
SO/50 2112
SO/50 1440
1177
SO/50 1056
SO/50 792
SO/50 528
SO/50 264
SO/50 132
SO/50
88
SO/50
66
44
50!50
33
SO/50
22
SO/50
16
SO/50
8

Actual
Frequency
16X Clock

0.8 KHz
1.2
1.7589
2.152
2.4
4.8
9.6
19.2
28.7438
31.9168
38.4
51.8258
76.8
114.306
153.6
307.2

Percent

Error

-0.01

-0.19
-0.26
0.39
-0.77

Duty
Cycle
%

Divisor

50/506144
50!50 4096
2793
SO/50 2284
SO/50 2048
SO/50 1024
SO/50 512
50!50 256
171
SO/50 154
SO/50 128
85
SO/50
64
43
SO/50
32
SO/50
16

STANDARDM

COM 8116T

COR

Baud Rate Generator Output
Frequency Options
COM 8116T·013
CRYSTAL FREQUENCY
Transmit!
Receive

0

0
0
0
0
0
0
0

0
1
1
1
1
1
1
1
1

Address
C B A

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Baud

Theoretical
Frequency

Rate

l6X Clock

50
0
1
75
0
110
1
134.5
0
150
1
200
0
300
1
600
0
1200
1
1800
2000
0
1
2400
3600
0
4800
1
0
9600
1 19,200

~

COM 8116T·OO3

2.76480 MHz

Actual
Frequency
l6X Clock

Percent
Error

0.8 KHz
0.8 KHz
1.2
1.2
1.76
1.76
2.152
2.152
2.4
2.4
3.2
3.2
4.8
4.8
9.6
9.6
19.2
19.2
28.8
28.8
32.149
32.0
38.4
38.4
57.6
57.6
76.8
76.8
153.6
153.6
307.2
307.2

0
0
-.006
-.019
0
0
0
0
0
0
+ .465
0
0
0
0
0

CRYSTAL FREQUENCIES

g:~re
%

Transmit!
Receive
Address

Divisor

50/50 3456
50150 2304
50/50 1571
50150 1285
50150 1152
50150
864
50150
576
50/50
288
144
50150
50150
96
50150
86
50150
72
50150
48
50150
36
50150
18
44156
9

Baud
Rate

0

C

B

A

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
50
1
75
110
0
134.5
1
0
150
1
200
0
300
1
600
0
1200
1
1800
0
2000
1
2400
0
3600
1
4800
0
9600
1 19,200

Frequency

Frequency
l6X Clock

l6X Clock

799.9Hz
0.8 KHz
1200.0
1.2
1.76
1759.7
2.152
2151.7
2399.6
2.4
3.2
3199.5
4.8
4799.3
9598.6
9.6
19227.9
19.2
28.8
28795.9
32.0
32012.5
38333.4
38.4
57868.7
57.6
76.8
77158.3
153.6
154316.6
307.2
300917.5

COM 8116T ·013A
Transmit!
Receive
Address

C

B

A

Baud
Rate

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

100
150
220
269
300
400
600
1200
2400
3600
4000
4800
7200
9600
19,200
38,400

Duly

Theoretical

Frequency

Actual
Frequency

Percent

16X Clock

l6X Clock

Error

%

Divisor

1.6 KHz
2.4
3.52
4.304
4.8
6.4
9.6
19.2
38.4
57.6
64.0
76.8
115.2
153.6
307.2
614.8

1.6KHz
2.4
3.5197
4.3032
4.8
6.4
9.6
19.2
38.4
57.6
64.298
76.8
115.2
153.6
307.2
614.8

0
0
-.006
-.019
0
0
0
0
0
0
+.466
0
0
0
0
0

50150
50150
50150
50/50
50150
50150
50150
50150
50150
50150
50150
50/50
50150
50150
50/50
44156

3456
2304
1571
1285
1152
864
576
288
144
96
86
72
48
36
18
9

283

6.01835 MHz

Actual

CRYSTAL FREQUENCY-5.52960 MHz

0

~

Theoretical

Cycle

Percent
Error

0
0
0
0
0
0
0

a

+0.14
0
0
-0.17
+0.46
+0.46
+0.46
2.04

g:~re
%

Divisor

50150 7523
50150 5015
50150 3420
50150 2797
50/50 2508
50/50 1881
50/50 1254
50/50
627
50150
313
50/50
209
188
50/50
157
50150
50/50
104
50/50
78
50150
39
50/50
20

I.

~

~

RCP

RSI
COM 8017
COM 2017

DUAL
BAUD RATE GENERATOR

UART

IT

TCP

TSO

t

I

Typical UART-Dual Baud Rate Generator Configuration
Full Duplex-Split Speed

R.
R,
R,

SA

TSO

BB

RSI

COM 1671
ASTRO

DB

XTAL

...-------1

D

1------,
R

R

XI------!~XTAL/EXT1

"~-~-XTAL/EXT2

Typical External Oscillator Hook-Up

L-_ _ _ _ _~

To System

+v
XTAL/EXT1

~

c:::::J XTAL
COM 8XXX

To System

50-100PF+
XTAL/EXT2

I

Generation of Communication Reference Frequency and
System Clock from a single crystal

Circuil diagrams utilizing SMC products are included as a means of illustratmg typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and IS believed to be entirely reliable. However. no responsibility is
assumed for inaccuracies. Furthermore. such information does not convey to the purchaser of the semiconductor
devices descrrbed any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

284

COM 8156
COM 8156T
PRELIMINARY

Dual Baud Rate Generator
Programmable Divider
FEATURES

PIN CONFIGURATION

D On chip crystal oscillator or external frequency input
D High crystal/clock frequency operation
D Choice of 2 x 16 output frequencies

D 16 asynchronous/synchronous baud rates
D High frequency reference outputs

D Direct UART/USRT/ASTRO/USYNRT compatibility
D
D
D
D
D

Full duplex communication capability
N-channel silicon gate technology
Single

18

Ra

Re

2

17
16

fA
Vee

Rb

+ 5 v power supply

TTL, MOS compatibility

Rd

3

STR

4

15

XTAL,

XTAL2

5

14

fo

fo/4

6

13

GND

7

12

fT
Ta

STT

8
9

11

Tb

10

Te

Td

Re-programmable ROM technology allows generation
of other frequencies

BLOCK DIAGRAM

T,
Tb
T,
Td

BUFFER

XTALI

h

0

EXT 1

S
C

to

I
L
L

A

to

T

0

XTALI

R

EXT2

BUFFER

+5V~

GlND
STR

285

tR

0-

4

GENERAL DESCRIPTION
The Standard Microsystem's COM8156 is a dual baud rate
generator that operates at twice the crystal/clock frequency
of the COM8116/36. It is fabricated using SMC's patented
COP LAM OS 'M technology and employs depletion mode
loads allowing operation from a single + 5V supply.
The standard COM8156 is specifically dedicated to generating the full spectrum of 16 asynchronous/synchronous
data communication frequencies for 16X UART/USRT
devices. A large number of the frequencies available are
also useful for 1X and 32X ASTRO/USYNRT devices.
The COM8156 features an internal crystal oscillator which
may be used to provide the master reference frequency.
Alternatively, an external reference may be supplied by
applying complementary TTL level signals to pins 1 and 9:
Parts suitable for use only with an external TTL reference
are marked COM 8156T. TTL outputs used to drive the
COM8156 or COM8156T XTALlEXT inputs should not be
used to drive other TTL inputs, as noise immunity may be
compromised due to excessive loading.

The output of the oscillator/buffer is applied to the dividers
for generation of the output frequencies fT' fRo The dividers
are capable of dividing by an integer from 6 to 2 '9 + 1, inclusive. If the divisor is even, the output will be square; otherwise the output will be high longer that it is low by one fa
clock period.
The crystal frequency is divided by two to give (fa) and again
by four to give (f014)' The transmit (fT) and receive (fR) frequencies are obtained by dividing (fa) by N. Up to 32 different divisors can be mask-programmed on custom parts to
accommodate different crystal frequencies and divider
schemes. Each group of four divisor select bits is held in an
externally strobed data latch. The strobe input is level sensitive: while the strobe is high, data is passed directly through
to the ROM. Initiation of a new frequency is effected within
3.5us of a change in any of the four divisor select bits (strobe
activity is not required). The divisor select bits (strobe activity is not required). The divisor select inputs and the strobe
inputs have pull-up resistors.

DESCRIPTION OF PIN FUNCTIONS
PIN NO.
15
16
17

SYMBOL
XTALlEXT 1
Vee
fR

NAME
Crystal
Power Supply
Receiver Output

FUNCTION
This input receives one pin of the crystal package.
+ 5 Volt Supply.
This output runs at a frequency selected by the Receiver
Address Inputs.

18
1-3

Ra Rb Re, Rd

4

STR

5

XTALlEXT2

6

fO!4

7
8

GND
STT

Ground
Strobe-Transmitter
Address

Ground
A high-level input strobe loads the transmitter address (Ta,
Tb, T e , Td) into the transmitter address register. This input
may be strobed or hard wired to + 5V.

9-12

Td T e , Tb Ta

The logic level on these inputs, as shown in Table 1, selects
the transmitter output frequency, fT'

13

fT

Transmitter
Divisor Select
Address
Transmitter
Output Frequency

14

fo

Oscillator
Output Frequency

This output runs at a frequency selected by the crystal-7 2.

Receiver
Divisor Select
Address
Strobe-Receiver
Address
Crystal
Oscillator
Output

The logic level on these inputs as shown in Table 1, selects
the receiver output frequency, fRo
A high-level input strobe loads the receiver address (Ra, Rb,
Re , Rd) into the receiver address register. This input may be
strobed or hard wired to + 5V.
This input receives one pin of the crystal package.
This output runs at a frequency selected by the crystal -7 8.

This output runs at a frequency selected by the Transmitter
Address inputs.

286

ELECTRICAL CHARACTERISTICS

COM8156, COM8156T

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range ...................................................................... O°C to + 70°C
Storage Temperature Range ..................................................................... - 55° to + 150°C
Lead Temperature (soldering, 10 sec.) .................................................................... + 325°C
Positive Voltage on any Pin, with respectto ground .......................................................... + 8.0V
Negative Voltage on any Pin, with respect to ground ......................................................... - 0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these'or at any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum
Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their
outputs when the AC power is switched on and off. In addition, voltage transients on the AC power line may appear on the
DC output. If this possibility exists it is suggested that a clamp circuit be used.

ELECTRICAL CHARACTERISTICS (TA = O°C to 70°C, Vee = +5V ±5%, unless otherwise noted)
PARAMETER
DC CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low Level V"
High Level V'H
OUTPUT VOLTAGE LEVELS
Low Level VOL

MIN

TYP

MAX

UNIT

0.8

V
V

excluding XTAL inputs

0.4
0.4
0.5

V
V
V
V

10L
10L
10L
10H

-0.1

mA

V," = GND, excluding XTAL inputs

pF

V,N = GND, excluding XTAL inputs

2.0

High Level V OH
2.4
INPUT CURRENT
Low-level, I"
INPUT CAPACITANCE
All inputs, C 'N

5

10

EXT INPUT LOAD

8

10

POWER SUPPLY CURRENT
lec
AC CHARACTERISTICS
CLOCK FREQUENCY, fiN
STROBE PULSE WIDTH, tpw
INPUT SET-UP TIME
tos
INPUT HOLD TIME
TOH
STROBE TO NEW FREQ. DELAY
OUTPUT CLOCKS DUTY CYCLE
fa
fa.,
fR' IT
CRYSTAL CHARACTERISTICS
Series Crystal Resistance
Crystal Shunt Capacitance

=
=
=
=

1.6 mA, for f o '
3.2 mA, for fR' fT
3.2 mA, for fa
-100 f.LA

Series 7400 equivalent loads

60

mA

5.0

11.0

MHz

150

DC

ns

XTAUEXT, 50% Duty Cycle ± 5%

ns

50
50

ns

40
45
48

2

COMMENTS

30
5

287

3.5

f.LS

6Q
55
52

%
%

70
10

pi

%

(U 1.5V LEVEL
(a 1.5V LEVEL
(U 1.5V LEVEL
(U Resonance

•

TIMING DIAGRAM

•

lew

V V,H

/

STROBE

tDC~

2.4V

1\It-

Vil

---

.7V

~

...-tOH

DIVISOR
SELECT
DATA

Baud Rate Generator Output Frequency Options
COM8156/COM8156T
(16X clock)
CRYSTAL FREQUENCY = 10.1376 MHz

0

0 0

0

50
75
110
134·5
150
300
600
1200
1800
2000
2400
3600
4800
1 1 0 1 7200
1 1 1 o 9600
1 1 1 1 19.200

0 a a 1
a a 1 a
0 0 1 1
a 1 a a
0 1 0 1
0 1 1 a
a 1 1 1
1 a a a
1 0 a 1
1 a 1 o
1 a 1 1
1 1 a o

COM8156·005/COM8156T·005
(16X clock)
CRYSTAL FREQUENCY = 9.8304 MHz

Theoretical
Actual
Duty
Frequency Frequency Percent Cycle
16X Clock 16X Clock Error
% Divisor

Tr'mitJReceive
Address
Baud
D C B A Rate

Tr'mit/Receive
Address
Baud
D C B A Rate

a
a
0
a
a
a
a

0.8 KHz 50150 6336
0.8 KHz
1.2
1.2
50150 4224
1.76
1.76
50150 2880
2.152
2.1523 0.016 50150 2355
2.4
2.4
50150 2112
4.8
4.8
50/50 1056
9.6
9.6
50/50 528
19.2
19.2
50/50 264
50/50 176
28.8
28.8
32.0
32.081
0.253 50/50 158
38.4
50/50 132
38.4
57.6
57.6
50/50
88
76.8
50/50
76.8
66
115.2
115.2
50/50
44
153.6
153.6
48/52
33
307.2
316.8
3.125 50/50
16

0
1
1
1
1
1
1
1
1

Crystal Operation

a a a
a a 1
a 1 a
a 1 1
1 a a
1 0 1
1 0
1 1 1
0 0 a
0 0 1
0 1 a
0 1 1
1 0 a
1 0 1
1 1 o
1 1 1

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19.200

Actual
Duty
Theoretical
Frequency Frequency Percent Cycle
16XCIock 16X Clock Error
% Divisor

0.8 KHz
0.8 KHz
1.2
1.2
1.76
1.7589
2.152
2.152
2.4
2.4
4.8
4.8
9.6
9.6
19.2
19.2
28.8
28.7438
31.9168
32.0
38.4
38.4
57.6
57.8258
76.8
76.8
115.2
114.306
153.6
153.6
307.2
307.2

-

50150 6144
50150 4096
2793
50150 2284
50150 2048
50/50 1024
50/50 512
50/50 256
-0.19
171
-0.2650/50 154
50/50 128
0.39
85
50/50
64
-0.77
43
50/50
32
50/50
16

-0.01

External Input Operation
74XX
TTL

74XX-totem pole oropen collector output (external
pull·up resistor required)

For ROM re·programming SMC has a computer program available whereby the customer
need only supply the input frequency and the desired output frequencies.
The ROM programming is automatically generated.

Crystal

Sp~cifications

User must specify termination (pin, wire, other)
Prefer: HC·18/U or HC·25/U
Frequency: 10.1376 MHz, AT cut
Temperature range DoC to 70°C
Series resistance <50 n
Series Resonant
Overall tolerance:+: .01 %
or as required

STANDARD MICROSYSTEMS
CORPORATION
35MarcusSivd,ltaco;lpauge,NYI11BS

15161273-3100 rwX-510-2l?-S898

Crystal manufacturers (Partial List)
Northern Engineering Laboratories
357 Beloit Street
Burlington, Wisconsin 53105
(414) 763·3591
Bulova Frequency Control Products
61·20 Woodside Avenue
Woodside, New York 11377
(212) 335·6000

CTS Knights Inc.
101 East Church Street
Sandwich, Illinois 60548
(815) 786·8411
Crystek Crystals Corporation
1000 Crystal Drive
Fort Myers, Florida 33901
(813) 936·2109

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; con$equently complete information sutficient for construction purposes is not 'necessarily given., The
information has been carefully checked and IS believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

288

---- .------------------------------------

COM81C66

PRELIMINARY

Universal Rate Generator & Timer
FEATURES

PIN CONFIGURATION

o Three independent 32 bit programmable counters
o Clock input from DC to 16 MHz
o Low power CMOS
o 8/16-pin Dual-In-Line package
o Uses a crystal or a TTL sign'al as frequency source
o Single + 5 Volt power supply

Do
D,
D2

D,
D.
D5

D,
GND

V"

XTAL,
XTAL2
RATE,
RATE2
RATE,

cs
D7

PACKAGE: 16-pin D,I.P,

GENERAL DESCRIPTION
The TIMER chip is a device designed to provide a convenient and inexpensive solution to applications requiring
programmable multiple clock divider sources. The source
frequency can be either an integrated crystal controlled
oscillator, or an external TTL signal. The TIMER consists of
a data input portion, a register addressing block and three
counter blocks.

DATA
BUS

'"

V

The counter blocks are accessed and programmed independently and they can be configured to operate in various
modes simultaneously.
The TIMER chip serves a broad range of applications some
of which are: Programmable rate generations, pulse generation, motor control, real time clock, interrupt applications and others.

i-.,.------'

RATE OUT

csr------L--~
RATE OUT

RATE OUT

COM8166 BLOCK DIAGRAM

289

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications:
consequently complete information sufficient for construction purposes is not necessarily given. The informalion
has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described
any license under the patent rights of SMC or others. SMC reserves the right to make changes at any time in order
to improve design and supply the best product possible.
.

290

CRT Display
.••••.••.•. •.1"~•.•.• .•.
N~be:t'

J-;;:;~':::':::'~~

Power

Descl'iptioJl.

Supplies Package

Provides Mofthe
tJ.mingan::I---H--l-f-+-l-H---t:>I:1

1-

HAI_
32x8PROM

HARRIS HM·7602
OR EQUIVALENT

5
SLOAD

(from system)

cs

HA'r---i-t
HA2

Figure 4.
SELF LOADING SCHEME
FOR VTAC® SET-UP

r---f--H

HA, f---t-t-H
HA, f--+5

'--------'
ROW SELECTS
TO CHARACTER GENERATOR

296

Register Selects/Command Codes
A3 A2 A1

0
0
0
0
0
0
0
0

ArJ

Select/Command

Description

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Load Control Register (0
Load Control Register 1
Load Control Register 2
Load Control Register 3
Load Control Register 4
Load Control Register 5
Load Control Register 6
Processor Initiated Self Load

0
0
0

0
0
1

0
1
0

Read Cursor Line Address
Read Cursor Character Address
Reset

0

See Table 1

Command from processor instructing
VTAC® to enter Self Load Mode (via external PROM)

Up Scroll

o
o

0

1

0

Load Cursor Character Address*
Load Cursor Line Address*
Start Timing Chain

1

Non-Processor Self Load

Resets timing chain to l.Qflleft of page. Reset
is latched on chip by OS and counters are
held until released by start command.
Increments address of first displayed data
row on page. ie; prior to receipt of scroll
command-top line = 0, bottom line = 23.
After receipt of Scroll Command-top line =
1, bottom line = O.

Receipt of this command after a Reset or
Processor Self Load command will release
the timing chain approximately one scan line
later. In applications requiring synchronous
operation of more than one CRT 5027 the
dot counter carry should be held low during
the OS for this command.
Devic~ill begin self load via PROM
when OS goes low. The 1111 command
should be maintained on A3-0 long
enough to guarantee self load. (Scan
counter should cycle through at least
once). Self load is automatically terminated and timing chain initiated when the
all "1 's" condition is removed, independent of OS. For synchronous operation
of more than one VTAC®, the Dot Counter
Carry should be held low when the command is removed.

*NOTE: During Self-Load, the Cursor Character Address Register (REG 7) and the Cursor Row Address
Register (REG 8) are enabled during states 0111 and 1000 of the R3-R0 Scan Counter outputs respectively.
Therefore, Cursor data in the PROM should be stored at these addresses.
TABLE 1
BIT ASSIGNMENT CHART
HORIZONTAL LINE COUNT

I
MODE: INTERLACED!

NON INTERLACE,D I

DATA ROWS/FRAME

LAST DISPLAYED DATA ROW

0 I REG 6 <-.1.1..-.J..-.1~-,-I--'----Li---LI--'I---'~I
I I ~ I REG 31,-,-W,-,-6-,-I5--,-1-,-1---,--,--,1'--J

i

H SYNC WIDTH

'

SKEW BITS

I

H SYNC DELAY

c::;::::':::;::

SCAN LINES/FRAME

r-Ic;::=;:=;=:;i~;=:;=::;::t-,

CURSOR CHARACTER ADDRESS

,....c:;=:::;==r='~:;=::;==?-,

REG 1 71 61 1 I 31 ?j@IREG417111 I ~ I REG 7 7--,1---1---,---,----,1--1-1---,-,1",-,I
I

L..:I

SCANS/DATA ROW

REG21 I ~ I

REG5,...c1~;=I:;==r=r:':::::;:::::;:1=r1::J....,01 REG 8 1.._1-'- - 'I_~C_I . _R_s0.L. R_R. Lr_w. .l.i_D . .oI_~_'1

CHARACTERS/DATA ROW

i I ~ 12Th-I

VERTICAL DATA STAAT

297

AC TIMING DIAGRAMS
FIGURE 1 VIDEO TIMING

DOT COUNTER
CARRY

I

IL....---------------------'I

I

rI4-------------------PWL--------------------~~------PWH----~-'"11

H~-7
H SYNC, V SYNC. BLANK,
CURSOR VIDEO,
COMPOSITE SYNC

I--------T DEL

1 --------t.~

FIGURE 2 LOAD/READ TIMING

Ds------------~---~-_;

FIGURE 3 SCAN AND DATA ROW COUNTER TIMING

HSYNC--------------'

--R0-3

DR~-5

-"\I/~-----­

-+________...J/

__________________________

L

________ __

I---To" , . ·R0-3 and DR0-5 may change prior to the falling edge of H sync
CRT 5057 LINE LOCK

I

o--~
LOCK~
I
LINE

IN
VERTICAL

TH~~~~gLD

.~-----'H-------,

r-!

I

~~f ------------~

PROGRAM: SCANS/FRAME TO BE GREATER THAN

ILiNELOC~MIN_X H

298

Note: To ensure
a stable display when
using the line lock
mode, the CRT 5057
should be used with DC
coupled monitors only.

-----------------------------------------

MAXIMUM GUARANTEED RATINGS'"
Operating Temperature Range .. , " , , " , , " ' , " ' , " " " " " " " " . , . , " ' , ' , " ' , " " " " " ' " ,O°C to + 70°C
Storage Temperature Range " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " - 55°C to + 150°C
Lead Temperature (soldering, 10 sec.) , , , . , . , , , . , , . , , , , , , , . , , , ' , , . ' , ' , , , . , , . , , , , , , , , , , ' , ' , , ' , , , , . , , . ,+325°C
Positive Voltage on any Pin, with respect to ground "" .. " " " , . " . " " " " " " " " " . " , . " . " " " , . , + 1B,OV
Negative Voltage on any Pin, with respect to ground ...... ".,.,.,', .. "., ........... ' ... , .. "' .. , ... ". -0.3V
"Stresses above those listed may cause permanent damage to the device, This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied,
NOTE: When powering this device from laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies
exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on and off.
In addition, voltage transient~ on the AC power line may appear on the DC output. For example, the
bench power supply programmed to deliver + 12 volts may have large voltage transients when the
AC power is switched on and off. If this possibility exists it is suggestec;l that a clamp circuit be used.
ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C, Vce= +5V:t:5%, VDD= + 12V:t:5%, unless otherwise noted)
Parameter

Min.

Typ.

D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low Level, V,L
High Level, V,H
Vee-1.5
OUTPUT VOLTAGE LEVELS
Low Level-VoL for RID-3
Low Level-VoL all others
2.4
High Level-VoH for RIil-3, DB.0-7
High Level-VoH all others
2.4
INPUT CURRENT
Low Level, IiL (Address, CS only)
Leakage, hL (All Inputs except Address, CS)
INPUT CAPACITANCE
Data Bus, C'N
DS, Clock, C'N
All other, C'N
DATA BUS LEAKAGE in INPUT MODE
IDB
POWER SUPPLY CURRENT
Icc
IDD
A.C. CHARACTERISTICS
DOT COUNTER CARRY
frequency
0.5
PWH
35
PWL
215
tr,tf
DATA STROBE
PWfSS
150ns
ADDRESS, CHIP SELECT
Set-uptime
125
Hold time
50
DATA BUS-LOADING
Set-uptime
125
Hold time
75
DATA BUS-READING
TDEL2
TOEL4
5
OUTPUTS: HIil-7, HS, VS, BL, CRV,
CS-TOEL.
OUTPUTS: R\1-3, DRrd-5
TDEL3

10
25
10

BO
40

Max.

Unit

O.B
Vee

V
V

0.4
0.4

V
V

10L =3,2ma
IOL = 1,6ma
10H = BO/La
IOH=40/La

250
10

p.A
p.A

V,N =O.4V
O:5V,N:5VCC

15
40
15

pF
pF
pF

10

p.A

100
70

Comments

OAV"" V,N "" 5.25V

mA
mA
TA = 25"C

4,0

10

*

50

MHz
ns
ns
ns

Figure
Figure
Figure
Figure

1
1
1
1

Figure 2

10~s

ns
ns

Figure 2
Figure 2

ns
ns

Figure 2
Figure 2

125
60

ns
ns

Figure 2, CL=50pF
Figure 2, CL=50pF

125

ns

Figure 1, CL=20pF

750

ns

Figure 3, CL=20pF

*R0-3 and DR0-5 may change prior to the falling edge of H sync

Restrictions
1. Only one pin is available for strobing data into the device via the data bus, The cursor X and Y coordinates are therefore
loaded into the chip by presenting one set of addresses and outputed by presenting a different set of addresses. Therefore
the standard WRITE and READ control signals from most microprocessors must be "NORed" externally to present a single
strobe (DS) signal to the device.
2. In interlaced mode the total number of character slots assigned to the horizontal scan must be even to insure that vertical
sync occurs precisely between horizontal sync pulses,

299

General Timing
HORIZONTAL TIMING

START OF LINE N

START OF LINE N+ 1

V:~/ZZZIZZZZ~(~Z~~L!ZZZZZZZZ;u:J
n
lzzzm
CHARACTERS PER DATA LINE
HORIZONTAL SYNC DELAY
(FRONT PORCHI
HORIZONTAL SYNC WIDTH

HORIZONTAL LINE COUNT=H
VERTICAL TIMING
START OF FRAME M OR ODD FIELD
START OF FRAME M+ lOR EVEN FIELD
SCAN LINES PER F R A M E - - - - - - - - - .•."

I"

-I"l,------,,-V-,-,OCLI-,--ZL.;ZlCLI. .LZ"--,ZZCLZ.. LZ.L,777Tlc. LL-L.-. LLO-,--Z-,-ZL-1ZI-<-I.. LZL.JZ!CLZ-,--ZUI1.......n .
I-

VERTICAL DATA

=:j .

ACTIVE V(DEO=
DATA ROWS PER FRAME

•

I

== 3H

START

Composite Sync Timing

VOH

H

V

VZZZ

I--J
L VERTICAL SYNC

'

SyNv9l------lr'--------... _ _----' 4 ' - - - " = - _ - - ' 5 ' - -_ _ _---' 6
L S f l 4 J r - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____

~----~~~-------

PRESET _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'

CLEAR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'

SO VIDEO
7 DOT FI ELD ----''''--'''---''''---'''-''''-_''''_"'''-''''-'''-'''--'''~__'''__'''__'''_''''___''''_'

SO VIDEO
8 DOT FIELD

----'''--''''--''''-'''~__'''__-''''--'--'''--"''-''''_'''~__''''__''''__'__''''_J

BF ~ Back Fill

TYPICAL VIDEO OUTPUT

r - - - - - - - - - - ClK (to chip)

Vee

500n

CP EXTERNAL - - - 1

ClK

) - - . - - - - - - j__-

QI------<- PE (to chip)

74S74
lOAD/SHIFT EXTERNAL-----' D

NOTE
The differences between the CRT 7004 and CG5004l-1 are detailed below:

CG5004L-1
1. If both the Preset and Clear inputs are
brought high simultaneously the Serial
Output is disabled and may be wire-ORed.
2. AlllnputsV'H = Vee -1.5v

CRT 7004
1. Clear overrides Preset, no output disable is
possible.

2. All inputs (except ClK) V'H = 2.0v, min.
ClK V'H = 4.3v, min.
3. SO VOL = O.4v @ IOL = O.4mA 74lSXX load
4. Shift Register is dynamic
5. Clear directly forces the output low and will
be latched (for a character time) by PE.

3. SO VOL = O.4v @ IOL = O.2mA
4. Shift Register is static
5. Clear-directly forces the output low; when
released, the output is determined by the
state of the shift register output.
6. General Timing Differences-See Timing
Diagram

6. General Timing Differences-See Timing
Diagram
307

._--_ _ - - - - - - - - - - - _ . _ - - ..

CRT 7004-003
(5 X 7 ASCII)
CODING INFORMATION

Dot Matrix Character Generator

The Cursor for the CRT 7004-003 is presented as a double underscore on Rows 8 and 9.

308

CRT 7220A
CRT 7220A-1
CRT 7220A-2

High-Performance
Graphics Display Controller
FEATURES

PIN CONFIGURATION

o Microprocesser Interface
DMA transfers with 8257- or 8237-type controllers
FIFO Command Buffering
Display Memory Interface
Up to 256K words of 16 bits
Read-Modify-Write (RMW) Display Memory cycles
as fast as 500ns
Dynamic RAM refresh cycles for non accessed memory
Light Pen Input
External video synchronization mode
Graphics Mode
Four megabit, bit-mapped display memory
Character Mode
8K character code and attributes display memory
Mixed Graphics and Character Mode
64K if all characters
. 1 megapixel if all graphics
Graphics Capabilities
Figure drawing of lines, arc/circles, rectangles, and
graphics characters in 500ns per pixel
Display 1024-by-1 024 pixels with 4 planes of color
or grayscale
Two independently scrollable areas
Character Capabilities
Auto cursor advance
Four independently scrollable areas
Programmable cursor height
Characters per row: up to 256
Character rows per screen: up to 100

2xWCLK

DBiN

o

HSYNC
V/EXTSYNC
BLANK
ALE
DRQ

lW:R
RD

o
o
o
o
o

WR
AO
DBO
DB1
DB2
DB3
DB4
DBS
DB6
DB7
GND

o

1
2
3
4
5

6
7
8
9
10
11
12
13
14
15·
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

Vee
A17
A16
AD1S
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
ADS
AD4
AD3
AD2
AD1

21 LPEN/DH

PACKAGE: 4o-pin D.I.P.

o Video Display Format

o

o
D
o
o

Zoom magnification factors of 1 to 16
Panning
Command-settable video raster parameters
Technology
Single + 5 volt Power Supply
COPLAMOS® n-Channel Silicon Gate Technology
DMA Capability
Bytes or word transfers
4 clock periods per byte transferred

GENERAL DESCRIPTION
The CRT 7220A High-performance Graphics Display Controller (HGDC) is an intelligent microprocessor peripheral
designed to be the heart of a high-performance raster-scan
computer grap~ics and character display system. Positioned between the video display memory and the microprocessor bus, the HGDC performs the tasks needed to
generate the raster display and manage the display memory. Processor software overhead is minimized by the
HGDC's sophisticated instruction set, graphics figure
drawing, and DMA transfer capabilities. The display memory supported by the HGDC can be configured in any number of formats and sizes up to 256K 16-bit words. The display
can be zoomed and panned, while partitioned screen areas
can be independently scrolled. With its light pen input and
multiple controller capability, the HGDC is ideal for advanced
computer graphics applications.

puter graphics system. Through the division of labor established by the HGDC's design, each of the system
components is used to the maximum extent through a sixlevel hierarchy of simultaneous tasks. At the lowest level,
the HGDC generates the basic video raster timing, including sync and blanking signals. Partitioned areas on the
screen and zooming are also accomplished at this level. At
the next level, video display memory is modified during the
figure drawing operations and data moves. Third, display
memory addresses are calculated pixel by pixel as drawing
progresses. Outside the HGDC at the next level, preliminary calculations are done to prepare drawing parameters.
At the fifth level, the picture must be represented as a list of
graphics figures drawable by the HGDC. Finally, this representation must be manipulated, stored, and communicated. By handling the first three levels, the HGDC takes
care of the high-speed and repetitive tasks required to
implement a graphics system.

The HGDC is designed to work with a general purpose
microprocessor to implement a high-performance com-

309

r-~D;M;A--~------------r-;'::;::~~HSVNC
Control

V/EXT SYNC

L-______..r~ BLANK

LPENIDH

+SVo---

GNOo---2xWCLKO---

DESCRIPTION OF PIN FUNCTIONS
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12-19
20
21
22-34
35-37

SYMBOL

IN/OUT

2XWCLK
DBIN
HSYNC
V/EXTSYNC
BLANK
ALE (RAS)
ORO
DACK
RD
WR
AO
DBO-DB7
GND
LPEN/DH
ADO-AD12
AD13-AD15

IN
OUT
OUT
IN/OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN/OUT

38

A16

OUT

39

A17

OUT

40

VCC

FUNCTION

Clock Input
Display Memory Read Input Flag
Horizontal Video Sync Output
Vertical Video Sync Output or External VSYNC Input
CRT Blanking Output
Address Latch Enable Output
DMA Request Output
DMA Acknowledge Input
Read Strobe Input for Microprocessor Interface
Write Strobe Input for Microprocessor Interface
Address Select Input for Microprocessor Interface
Bidirectional data bus to Host Microprocessor
Ground
Light Pen Detect Input/Drawing Hold Input
Address and Data Lines to Display Memory
Character Mode: Line Counter Outputs, Bits 0-2
Mixed Mode: Address and Data Bits 13-15
Graphics Mode: Address and Data Bits 13-15
Character Mode: Line Counter Output, Bit 3
Mixed Mode: Attribute Blink and Clear Line Counter Output
Graphics Mode: Address Bit 16 Output
Character Mode: Cursor Output and Line Counter Bit 4
Mixed Mode: Cursor and Bit Map Area Flag Output
Graphics Mode: Address Bit 17 Output
+ 5 Volt Power Supply

IN
IN/OUT
IN/OUT

-

310

FUNCTIONAL DESCRIPTION

Drawing Controller

Microprocessor Bus Interface
Control of the HGDC by the system microprocessor is
achieved through an 8-bit bidirectional interface. The status register is readable at any time. Access to the FIFO buffer
is coordinated through flags in the status register and operates independently of the various internal HGDC operations, due to the separate data bus connecting the interface
and the FIFO buffer.

Command Processor
The contents of the FIFO are interpreted by the command
processor. The command bytes are decoded, and the
succeeding parameters are distributed to their proper
destinations within the HGDC. The command processor
yields to the bus interface when both access the FIFO
simultaneously.

DMAControl
The DMA control circuitry in the HGDC coordinates transfers over the microprocessor interface when using an
external DMA controller. The DMA Request and Acknowledge handshake lines directly interface with a DMA controller, so that display data can be moved between the
microprocessor memory and the display memory.

Parameter RAM
The 16-byte RAM stores parameters that are used repetitively during the display and drawing processes. In character mode, this RAM holds four sets of partitioned display
area parameters; in graphics mode, the drawing pattern
and graphics character take the place of two of the sets
of parameters.

The drawing processor contains the logic necessary to calculate the addresses and positions of the pixels of the various graphics figures. Given a starting point and the
appropriate drawing parameters, the drawing controller
needs no further assistance to complete the figure drawing.

Display Memory Controller
The display memory controller's tasks are numerous. Its
primary purpose is to multiplex the address and data information in and out of the display memory. It also contains the
16-bit logic unit used to modify.the display memory contents during RMW cycles, the character mode line counter,
and the refresh counter for dynamic RAMs. The memory
controller apportions the video field time between the various types of cycles.

Light Pen Deglitcher
Only if two rising edges on the light pen input occur at the
same point during successive video fields are the pulses
accepted as a valid light pen detection. A status bit indicates to the system microprocessor that the light pen register contains a valid address. If this input is held high for a
period greater than four 2xWCLK cycles, drawing execution is halted.

PROGRAMMER'S VIEW OF HGDC
The HGDC occupies two addresses on the system microprocessor bus through which the HGDC's status register
and FIFO are accessed. Commands and parameters are
written into the HGDC's FIFO and are differentiated based
on address bit AO. The status register or the FIFO can be
read as selected by the address line.
AO

0

Video Sync Generator
Based on the clock input, the sync logic generates the raster timing signals for almost any interlaced, non-interlaced,
or "repeat field" interlaced video format. The generator
is programmed during the idle period following a reset. In
video sync slave mode, it coordinates timing between
multiple HGDC's.

Memory Timing Generator
The memory timing circuitry provides two memory cycle
types: a two-clock period refresh cycle and the read-modify-write (RMW) cycle which takes four clock periods. The
memory control signals needed to drive the display memory devices are easily generated from the HGDC's ALE and
DBIN outputs.

Zoom & Pan Controller
Based on the programmable zoom display factor and the
display area entries in the parameter RAM, the zoom and
pan controller determines when to advance to the next
memory address for display refresh and when to go on to
the next display area. A horizontal zoom is produced by
slowing down the display refresh rate while maintaining the
video sync rates. Vertical zoom is accomplished by repeatedly accessing each line a number of times equal to the
horizontal repeat. Once the line count for a display area is
exhausted, the controller accesses the starting address and
line count of the next display area from the parameter RAM.
The system microprocessor, by modifying a display area
starting address, can pan in any direction, independently of
the other display areas.

I

I

READ

WRITE

Status Register

Parameter Into FIFO

I

I

I

I

I

I

I I

FIFO Read
1

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

Command Into FIFO
I

I

I I

I

I

I

I

I

I

HGDC Microprocessor Bus Interface Registers

Commands to the HGDC take the form of a command byte
followed by a series of parameter bytes as needed for specifying the details of the command. The command processor
decodes the commands, unpacks the parameters, loads
them into the appropriate reigsters within the HGDC, and
initiates the required operations.
The commands available in the HGDC can be organized
into five categories as described in the following section.

HGDC COMMAND SUMMARY
Video Control Commands

311

1. RESET 1 Resets the HGDC to its idle state.
2. RESET 2 Resets the HGDC to its idle state. Does
not resynchronize video timing. Blanks
the display.
3. RESET 3 Resets the HGDC to its idle state. Does
not resynchronize video timing. Does not
blank the display.
4. SYNC
Specifies the video display format.
5. VSYNC
Selects master or slave video synchronization mode.
6. CCHAR Specifies the cursor and character row
heights.

SR-3: Drawing in Progress

Display Control Commands
1. START
Ends Idle mode and un blanks the display.
2. BLANK 1 Controls the blankingaHd unblanking
of the display, along with video
resynchronization.
3. BLANK 2 Controls the blanking antl unblanking of
the display. Does not blank the display.
4. ZOOM
Specifies zoom factors for the display and
graphics characters writing.
5. CURS
Sets the position of the cursor in display
memory.
6. PRAM
Defines starting addresses and lengths
of the display areas and specifies the
eight bytes for the graphics character.
7. PITCH
Speci,fies the width of the X dimension of
display memory.

Drawing Control Commands
1. WDAT

2. MASK
3. FIGS
4. FIGD
5. GCHRD

Writes data words or bytes into display
memory.
Sets the mask register conte,!')ts.
: '"
Specifies the parameters forthe drawing
controller.
Draws the figure as specified above.
Draws the graphics character into display memory.

Data Read Commands
1. RDAT:

2. CURD:
3. LPRD:

Reads data words or bytes from display
memory.
Reads the cursor position.
Reads the light pen address.

DMA Control Commands
1. DMAR

2. DMAW

Requests a DMA read transfer.
Requests a DMA write transfer.

STATUS REGISTER FLAGS

II I I t

ttl

oat,a Ready
FIFO Full

FIFO Empty
' - -_ _ _ _ _ Drawing in Progress

, :

DMA Execute
Vertical Sync Active

~i::~~~~::::c~:~:el

Status Register (SR)

SR-7: Light Pen Detect
When this bit is set to 1; the light pen address (LAD) register
contains a deglitched value that the system microprocessor
may read. This flag is reset after the 3-byte LAD is moved
into the FIFO in response to the light pen read command.

SR-6: Horizontal Blanking Active/Vertical Blank
Active
A 1 value for this flag signifies that horiiontal retrace blanking or vertical retrace blanking is currently underway
dependent on the status of the VH bit in SYNC or the
RESETx parameter 6.

While the HGDC is drawing a graphics figure, this status bit
is a 1.

SR-2: FIFO Empty.,
This bit and the FIFO Full flag coordinate system microprocessor accesses with the HGDC FIFO. When it is 1, the
Empty flag ensu,res that all the commands and parameters
previously sent to the HGDC have been interpreted.

SF-1: FIFO Full

A1at this flag indicates a full FIFO in the HGDC. A 0 ensures
that there is room for at least one byte. This flag needs to
be checked out before each write into the HGDC.

SR-O: Data Ready
When this flag is a 1, it indicates that a byte is available to
be read by the system microprocessor. This bit must be
tested before each read operation. It drops to a 0 while the
data is transferred from the FIFO into the microprocessor
interface data register.

FIFO OPERATION & COMMAND PROTOCOL
The first-in, first-out buffer (FIFO) in the HGDC handles the
command dialogue with the system microprocessor. This
flow of information uses a half-duplex technique, in which
the single 16-location FIFO is used for both directions of
data movement, one direction at a time. The FIFO's direction is controlled by the system microprocessor through the
HGDC's command set. The host microprocessor coordinates these transfers by checking the appropriate status
register bits.
The command protocol used by the HGDC requires differentiation of the first byte of a command sequence from the
succeeding bytes. The first byte contains the operation code
and the remaining bytes carry parameters. Writing into the
HGDC causes the FIFO to store a flag value alongside the
data byte to signify whether the byte was written into the
command or tHe parameter address. The command processor in the HGDC tests this bit as it interprets the entries
in the FIFO.
The receipt of a command byte by the command processor
marks the end of any previous operation. The number of
parameter bytes supplied with a command is cut short by
the receipt of the next command byte. A read operation from
the HGDC to the microprocessor can be terminated at any
time by the next command.
Tne FIFO changes direction under the control of the system
microprocessor. Commands written into the HGDC always
put the FIFO into write mode if it wasn't in it already.
If itwas in read mode, any read data in the FIFO at the time
of the turnaround is lost. Commands which require a HGDC
response, such as RDAT, CURD and LPRD, put the FIFO
into read mode after the command is interpreted by the
HGDC's command processor. Any commands and parameters behind the read-evoking command are discarded
when the FIFO direction is reversed.

SR-5: Vertical Sync
Vertical retrace sync occurs while this flag is a 1. The vertical sync flag coordinates display format modifying commands to the blanked interval surrounding vertical sync. This
eliminates display disturbances.

SR-4: DMA Execute
This bit is a 1 during DMA data transfers.

READ-MODIFY-WRITE CYCLE
Data transfers between the HGDC and the display memory
are accomplished using a read-modify-wrile (RMW) memory cycle. The four clock period timing of the RMW cycle is
used to: 1) output the address, 2) read data from the memory, 3) modify the data, and 4) write the modified data back
into the initially selected memory address. This type of

312

- - - -.. _ . _ - - - - - - - - - - - - - - - - - - - - - -

memory cycle is used for all interactions with display memory including DMA transfers, except for the two clock period
display and RAM refresh cycles.
The operations performed during the modify portion of the
RMW cycle merit additional explanation. The circuitry in the
HGDC uses three main elements: the Pattern register, the
Mask register, and the 16-bit Logic Unit. The Pattern register holds the data pattern to be moved irit'o memory. It is
loaded by the WDAT parameters or, during drawing, from
the parameter RAM_ The Mask register contents determine
which bits of the read data will be modified. Based on the
contents of these registers, the Logic Unit performs the
selected operations of REPLACE, COMPLEMENT, SET, or
CLEAR on the data read from display memory.' .
The Pattern register contents are ANDed with the Mask
register contents to enable the actual modification of the
memory read data, on a bit-by-bit basis. For graphics drawing, one bit at a time from the Pattern register is combined
with the Mask. When ANDed with the bit set to a 1 in the
Maskregister, the proper single pixel is modified by the Logic
Unit. For the next pixel in the figure, the next bit in the Pattern register is selected and the Mask register bit is moved
to identify the pixel's location within the word. The Execution word address pointer register, EAD, is also adjusted as
required to address the word containinQ Ire next pixel.
In character mode, all of the bits if] tne'pattern register are
used in parallel to form the respective bits of the modify data
word. Since the bits of the character code word are used in
parallel, unlike the one-bit-at-a-time graphics drawing process, this facility allows any or all of the bits in a memory
word to be modified in one RMW memory cycle. The Mask
register musi be loaded with 1s in the positions yvhere modification is to be permitted.
The Mask register can be loaded in either of two ways. In
graphics mode, the CURS command contains a four-bit dAD
field to specify the dot address. The command processor
converts this parameter into the one-of-16 forlT)at used in
the Mask register for figure drawing. A full 16 bits can be
loaded into the Mask register using the MASK command.
In addition to the character mode use ment\q[1ed above, the
16-bit MASK load is convenient in graphics mode when all
of the pixels of a word are to be set to the same value.
The Logic Unit combines the data read from display memory, the Pattern Register, and the Mask register to generate
the data to be written back into display memory. Anyone of
four operations can be selected: REPLACE, COMPLEMENT, CLEAR or SET. In each case, if the respective Mask
bit is 0, that particular qit of the re;'ld d!3-ta is returned to
memory unmodified. If the Mask bit is 1; the modification is
enabled. With the REPLACE operation, the Pattern Register data simply takes the place of tre read data for modification enabled bits. For the other three operations, a 0 in
the modify data allows the read data bit to be returned to
memory. A 1 value causes the specified operation to be
performed in the bit positipns with set Mask bits.

addressed space of these words. Addressing of individual
pixels is handled by the HGDC's Internal RMW logic.
During the drawing process, the HGDC finds the next pixel
of the figure which is one of the eight nearest neighbors of
the last pixel drawn. The HGDC assigns eac;h of these eight
directions a number from 0 to 7, starting with straight down
and proceeding counterclockwise.

Drawi'19 Directions

Figure drawing requires the proper manipulation of the
address and the 'pixel bit position according to the drawing
direction to determine the next pixel of the figure. To move
to the word above or below the current one, it is necessary
to subtract or add the number of words per line in display
memory. This parameter is called the pitch. To move to the
word to either side, the Execute word address cursor, EAD,
must be increme'rlted or decremented as the dot address
pOinter bit reaches the LSB or the MSB of the Mask register.
Tei move to a pixel within the same word, it is necessary to
rotate the dot addreSS pointer register to the right or left.
The table below summarizes these operations for each
direction.
Dir

Operations to Address the Next Pixel

000

EAD-P-. EAD

001

EAD-P_EAD
dAD (MSB) = 1 :EAD -1

010

dAD (MSB)1 :EAO

011

EAD-P-tEAD
dAD("1SB)=l:EAD-l ~EADdAD~LR

~

EAD dAD ~ LR

1 _ E!,O dAD _LR

100

EAO-P_EA~

101

EAD-P-tEAD
q/lD (LSB) = 1 :EAD -1

110

dAD (LSB) == 1 :EAD -1 ..... EAD dAD .... RR

111

~

EAD dAD ~ RR

EAD-P-+EAD
dAD (LSB) = 1 :EAD -1 -+ EAD dAD -+ RR

Where P PitCh, LR Left Rotate, RR Right Aotat~,
EAD = Execute Word Address, and
dAD == Dot Address stored in the ¥ask Register.

FIGURE DRAWINGS
The HGDC draws graphics figures at the rate of one pixel
per read-modify-write (RMW) display memory cycle. These
cycles take four clock periods to complete. At a clOCk frequency of 8MHz, this is equal to 500ns. During the RMW
cycle the HGDC simultaneously calculates the address and
position of the next pixel to be drawn.
The graphics figure drawing process depends on the display memory addressing structure. Groups of 16 horizontally adjacent pixels form the 16-bit words which are handled
by the HGDC. Display memory is organized as a linearly

Whole word drawing is useful for filling areas in memory with
a single value. By setting the Mask register to all1s with the
MASK command, both the LSB and MSB of the dAD will
always be 1, so that the EAD value will be incremented or
decremented for each cycle regardless of direction. One
RMW cyde will be able to effect all 16 bits of the word for
any drawing tYPe. One bit in the Pattern register is used per
RMVV cycle toyvrite all the bits oftheword to the same value.
Thene~t Pattern bit is used for the word, etc.

313

I

,

For the various figures, the effect of the initial direction upon
the resulting drawing is shown below:
Dlr

Line

000

~

001

Arc

~,>-,7

Character Slant Char Rectangle

1JlflJlJ

D

" ~
,',
~ L> ~ ff 0

~

r)

~

i/

0

"

010
011

100
101
110
111

,-

~~

A

V

A

C:~~,

~ ~

~/J fU1JU1
,1

/,

~
?
i,
"
'" i
~

'~:,-,)

~
~

"

~

<>

0

0

ff CJ

~ ~

<>

DMA

f'N
~
~::

HGDC Drawing Controller coordinates the RMW circuitry
and address registers to draw the specified figure pixel by
pixel.
The algorithms used by the processor for figure drawing are
designed to optimize its drawing speed. To this end, the
specified details about the figure to be drawn are reduced
by the microprocessor to a form conducive to high-speed
address calculations within the HGDC, In this way the
repetitive, pixel-by-pixel calculations can be done quickly,
thereby minimizing the overall figure drawing time. The table
below summarizes the parameters.
Drawing Type

~
l'N

Initial value·
Line

Arc"

D

D2

DI

DM

0

8

8

-I

-I

,"II
'*'

21,,01-1"11
,-I

2(1,,01-1"11) 21"01
2(,-1)
-I
rsln a i

Rectangle

rsln
3

A-I

8-1

Area Fill

8-1

A

A
A

~

Read

~

Graphic Character"·

#

DC

8-1

A

OMAW

W-'
0-1

C-I

OMAR

0-1

C-2

+ Write Data

-1

A-I

(C-2Y2t

Notes: All numbers are shown in base 10 for convenience. The HGDC accepts base 2 numbers
(2$ complement notation) where appropriate.
·Initial values for the various parameters remain as each drawing process ends.
"Circles are drawn with 8 arcs, each of which span 45°, so that sin r.b

Note that during line drawing, the angle of the line may be
anywhere within the shaded octant defined by the DIR value.
Arc drawing starts in the direction initially specified by the
DIR value and veers into an arc as drawing proceeds. An
arc may be up to 45 degrees in length. DMA transfers are
done on word boundaries only, and follow the arrows indicated in the table to find successive word addresses. The
slanted paths for DMA transfers indicate the HGDC changing both theX and V components of the word address when
moving to the next word, It does notfollow a 45 degree diagonal path by pixels,

DRAWING PARAMETERS
In preparation for graphics figure drawing, the HGDC's
Drawing Processor needs the figure type, direction and
drawing parameters, the starting pixel address, and the
pattern from the microprocessor. Once these are in place
within the HGDC, the Figure Draw command, FIGD, initiates the drawing operation. From that point on, the system
microprocessor is not involved in the drawing process, The

= 1/'1/2 and sin fI =

O.

""Graphic characters are a special case of bit-map area filling in which B and A ~ 8. If A == 8
there is no need to load D and D2.
Where:
-1 = all ONES value.
- == No parameter bytes sent to GDC for this parameter.
dol= The larger at dox or doy.
doD= The smaller at dox or doy.
r== Radius of curvature, In pixels.
cb== Angle from major axis to end of the arc. cb ~ 45?
9= Angle frorn major axis to start of the arc. H~ 45?
T := Round up to the next higher integer.
L == Round down to the next lower integer.
A=- Number ot pixels in the initially specified direction.
B== Number of pixels in the direction at right angles to the
initially specified direction.
W== Number of words to be accessed.
C= Number of bytes to be transferred in the initially specified
direction. (Two bytes per word if word transfer mode
is selected.)
D= Number of words to be accessed in the direction at right
angles to the initially specified direction.
DC== Drawing count parameter which Is one less than the number of AMW cycles to be executed.
OM== Dots masked from drawing during arc drawing.
t= Needed only for wo~ reads.

GRAPHICS CHARACTER DRAWING
Graphics characters can be drawn into display memory PRAM are repeated horizontally and vertically the number
pixel-by-pixel. The up to 8-by-8 character display is loaded of times specified by the zoom factor.
into the HGDC's parameter RAM by the system micropro- The movement of these PRAM bytes to the display memory
cessor, Consequently, there are no limitations on the char- is controlled by the parameters of the FIGS command,
acter set used. By varying the drawing parameters and Based on the specified height and width of the area to be
drawing direction, numerous drawing options are available. drawn, the parameter RAM is scanned to fill the required
In area fill applications, a character can be written into dis- area.
play memory as many times as desired without reloading
For an 8-by-8 graphics character, the first pixel drawn uses
the parameter R A M . ,
Once the parameter RAM has been loaded with up to eight the LSB of RA-15, the second pixel uses bit 1 of RA-15, and
graphics character bytes by the appropriate PRAM com- so on, until the MSB of RA-15 is reached.
mand, the GCHRD command can be used to draw the bytes
The HGDC jumps to the corresponding bit in RA-14 to continue the drawing. The progression then advances toward
into display memory starting at the cursor. The zoom magnification factor for writing, set by the zoom command, conthe LSB of RA-14. This snaking sequence is continued for
trols the size of the character written into the display memory . the other 6 PRAM bytes. This progression matches the
in int~ger multiples of 1 through 16. The bit values in the
sequence of display memory addresses calculated by the
314
-- - - - - - - - - - - - -

drawing processor as shown above. If the area is narrower
than 8 pixels wide, the snaking will advance to the next
PRAM byte before the MSB is reached. If the area is narrower than 8 lines high, fewer bytes in the parameter RAM
will be scanned. If the area is larger than 8 by 8, the HGDC
will repeat the contents of the parameter RAM in two
dimensions, as required to fill the area with the 8-by-8 mozaic. (Fractions of the 8-by-8 pattern will be used to fill areas
which are not multiples of 8 by 8).

In this way any stored parameter byte or bytes may be
changed without influencing the other bytes.
The PRAM stores two types of information. For specifying
the details of the display area partitions, blocks of four bytes
are used. The four parameters stored in each block include
the starting address in display memory of each display area,
and its length. In addition, there are two mode bits for each
area which specify whether the area is a bit-mapped graphics area or a coded character area, and whether a 16-bit or
a 32-bit wide display cycle is to be used for that area.
The other use for the PRAM contents is to supply the pattern for figure drawing when in a bit-mapped graphics area
or mode. In these situations, PRAM bytes 8 through 16 are
reserved for this patterning information. For line, arc, and
rectangle drawing (linear figures) locations 8 and 9 are
loaded into the Pattern Register to allow the HGDC to draw
dotted, dashed, etc. lines. For area filling and graphics bitmapped character drawing locations 8 through 15 are referenced for the pattern or character to be drawn.
Details of the bit assignments are shown for the various
modes of operation.

PARAMETER RAM CONTENTS: RAM ADDRESS
RAOTO 15
The parameters stored in the parameter RAM, PRAM, are
available for the HGDC to refer to repeatedly during figure
drawing and raster-scanning. In each mode of operation the
values in the PRAM are interpreted by the HGDC in a predetermined fashion. The host microprocessor must load the
appropriate parameters into the proper PRAM locations.
PRAM loading command allows the host to write into any
location of the PRAM and transfer as many bytes as desired.

Graphics and Mixed Graphics and Character Modes

Character Mode

RA-O

I

0

0

I

~=~~==~==~==~)

I

L

1

~I__~--'-__~_SA~D_1_"~__'_ ~__'

2

~1__~L_E~N1_,~ ~1_0__'__o__'_I__SA~D_1"__'

~~~~(::r~ ~~d~:!i)iflcance

__

__

Length of Display Partition
Area 1 with low and high
significance fields (line count)

Length of Display Partition 1
(line count) with high and
low significance fields

In mixed mode, a 1 Indicates an

A Wide Display cycle width
of two words per memory cycle

'---------- :~:I~:t~~g:~h~~~~:::;:;~na 0

'-------------~~::W~~~ ~~tl~h!:td:~~I~~
The display address counter
is then Incremented by
2 for each display scan
cycle. Other memory cycle
types are not influenced.

Display Partition Area 1

I~startlngaddresswlthlow,

SADl l

~.-~~-~--'--~--'--~--'

graphics mode this bit must be O.
When 1, the DAD Is Incremented
every other display cycle.
Display Partition Area 2

RA·4

address and
i- starting
length with Image

SAD2 L

bit as in area 1

Display Partition 2

0

0

o

I

LEN2L
WD21

0

I

SAD2 M

starting address
I--- and
length

SAD2 L

AA·4

LEN2l

SAD2 H

I

WD211M
0

0

0

0

lEN2H

AA;8

o

I

LEN3l

10

11

0

WD31

0

I

0

0

0

0

o

14

LEN4L

15

0

WD41

I

I

or

or

GCHR8

GCHA7

GCHA5

12

GCHA4

13

GCHA3

---

14

GCHA2

15

GCHA1

Display Partition 4
starting address
and length

0

0

0

0

LEN4H

315
- - _... _-----

SAD2H

11

SAD4H

I

I

GCHA6

0

SAD4L

0

o

AMO

LEN3 H

RA-12
13

SA03H

I

0
LEN2~

starting address
I--- and
length

SAD3L

0

PTN L

PTN H

Display Partition 3
AA·8

cl

I

I

~"

Pattern of 16 bits used for
figure drawing to pattern
dotted, dashed. etc. lines

Graphics character bytes
be moved into display
r-- tomemory
with graphics
character drawing

1/

VIDEO CONTROL COMMANDS
Command Bytes Summary
RESET'

I

Reset
Blank the display, enter
idle mode, and initialize
within the HGDC:

0

-FIFO

RESET2

-

1

Command Processor

-Internal Counters
RESET3

BLANK1

BLANK2

SYNC

VSYNC

CCHAR

1 0

This command can be executed at any time and does not
modify any of the parameters already loaded into the HGDC.
If followed by parameter bytes, this command also sets the
sync generator parameters as described below. Idle mode
is exited with the START command.
RESET 1 : Resync video timing in slave mode.
RESET 2: Blank the display and do not resync.
RESET 3: Unblank the display and do not resync.

1 0

1 0

I
I
I

0

0

0

Pl

Mode of Operation select bits
See below

P2

Active Display Words per
line - 2
Must be even
number with bit 0 '" 0

P3
START

ZOOM

CURS

1 0

I
I

Horizontal Sync Width - 1
' - - - - - - - - - - - - - Vertical Sync Width, low bits

0

P4

PRAM

\,---'- - - - Horizontal Front Porch Width -

SA

~-

PITCH

WDAT

,--,-_~H_F.LP....-'--~_...L.._VS~"----,f-- VerHeal Syne Wid,h, high bi's

,I

TYPE

o

I

MOD

PS

DH

PH

P6

VH

VL

I- Horizontal Back Porch Width I- Vertical Front Porch Width

HBP
VFP

P7

FIGS

VBP

1

Display Lines per
I- Active
Video Field, low bits

AL,

MASK

PB

1

ALH

f--

L---'-_~--'I'\;:-"""_-'----''---'---J.

Active Display Lines per
Video Field, high bits

FIGD
' - - - - - - - - Vertical Back Porch Width

GCHRD

ROAT

,

I

TYPE

CURD

o

LPRD

o

DMAR

,

1

I
I

II
0

0

o

0

o

1

I

TYPE

1

I

MOD

TYPE
1

OMAW

MOD

'

I,

1

1

MOD

In graphics mode, a word is a group of 16 pixels. In character mode, a word is one character code and its attributes,
if any. The number of active words per line must be an even
number from 2 to 256. An all-zero parameter value selects
a count equal to 2n where n = number of bits in the parameter field for vertical parameters. All horizontal widths are
counted in display words. All vertical intervals are counted
in lines.
If the Drawing Hold (DH) is set to one, pin 21 (LPEN/DH) is
used as the drawing hold control pin. When the input to
LPEN/DH is held high for over four 2 x WCLK clocks, the
drawing address output is temporarily held and the display
address is output.
The HGDC allows an even or odd number of lines per frame.
Selection is via the VL flag, the seventh bit of the sixth
parameter byte following a RESET or SYNC command.
When VL is 0, an odd number of display lines is generated.
316

VL

2 Field Sequence with '12 line offset. Each field displays alternate
lines.
Noninterlaced Framing: 1 field brings all of the information to the screen.
Interlaced Framing:

Number of lines In Interlaced mode
Odd, as in 7220
Even

When VH = 0, status operation is as in CRT 7220.

Dynamic RAM Refresh Cycles Enable

D

VH

Blank Status Bit Definition

No Refresh -

Status register bit 6 indicates Horizontal Blank
Status register bit 6 indicates Vertical Blank

Refresh -

STATIC RAM

Dynamic RAM

Dynamic RAM refresh is important when high display
zoom factors or DMA are used in such a way that not all of
the rows in the RAMs are regularly accessed during display raster generation and for otherwise inactive display
memory.

PH is the most significant bit (9) of the display pitch
parameter. Use the PITCH command to set the lower
eight bits.

Drawing Time Window
Drawing during active display lime and retrace blanking

SYNC GENERATOR PERIOD CONSTRAINTS

Drawing only during retrace blanking

Access to display memory can be limited to retrace blanking intervals only, so that no disruptions of the image are
seen on the screen.

Horizontal Back Porch Constraints
1, In general:
HBP~3 Display Word Cycles (6 clock cycles).
2. If the Image bit or WD modes change within one video
field:
HBP~5 Display Word Cycles (10 clock cycles).
3, If interlace, mixed mode, or split screen is used:
HBP~5 Display Word Cycles (10 clock cycles),

RESET2 1 0

R!,SETJ

o

1 0

o

1 0

l'

Both commands allow a reset while presenting reinitialization of the internal sync generator by an external sync source
(slave mode),

Horizontal Front Porch Constraints
1. In general:
HFP~2 Display Word Cycles (4 clock cycles),
2. If the HGDC is used in the video sync Slave mode:
HFP~4 Display Word Cycles (8 clock cycles).
3, If the Light Pen is used:
HFP~6 Display Word Cycles (12 clock cycles).
4. If interlace mode, DMA, or ZOOM is used:
HFP~3 Display Word Cycles (6 clock cycles).

Cursor & Character Characteristics

CCHAR:' 0 , 1 , 0 , 0
~-r'--~~:::;:======::::;- External SYNC Enable

~ 'Dt'-E_I_O_'___

L_R_ _ _ _

Horizontal SYNC Constraints

-

1. If interlaced display mode is used:
HS~5 Display Word Cycles (10 clock cycles).
2. If DRAM Refresh is enabled:
HS~2 Display Word Cycles (4 clock cycles).

P2

,

~_

Lines per character row - 1
Display Cursor if 1

B~~~'----C-TO-P---f---~Ut~~~J~P

line number

-

0 _ Blinking Cursor
1 - Steady Cursor
~-------- Blink Rate, lower bits

P3

Modes of Operation Bits

L....L---'-C,BO:-T'--'----L_.>-BR_"...L-.....JI-- Blink Rate, upper bits

\ ' - ' - - - - - - Cursor Bottom line number in

C G

Display Mode

o

0

Mixed Graphics & Character

o

1

Graphics Mode

1 0

Character Mode

1 1

Invalid

I

S

Video Framing

o
o

0

Noninterlaced

1

Invalid

1

0

Interlaced Repeat Field for Character Displays

1

1

Interlaced

Repeat Field Framing:

the row CBOT < LR

In graphics mode, LR should be set to O. The blink rate
parameter controls both the cursor and attribute blink rates.
The cursor blink-on time = blink-off time = 2 x BR (video
frames). The attribute blink rate is always '12 the cursor
rate but with a % on -% off duty cycle. All three parameter
bytes must be output for interlace displays, regardless of
mode. For interlace displays in graphics mode, the parameter BRL = 3.

2 Field Sequence with '12 line offset between otherwise identical
fields.

When SE = 0, the HGDC, in slave mode, detects the falling
edge of EX. SYNC on the first frame. When SE = 1 , the
HGDC, in slave mode, detects the falling edge of EX, SYNC
on every frame.

317

DISPLAY CONTROL COMMANDS

SYNC Format Specify
SYNC:

<--I-'---'----'---'~~,_.L.I I
0

Start Display & End Idle Mode

D-,-JE

L

The displav is enabled by
a 1, and blanked by a O.

START:

P'

See below

P2

, 0

, '

, 0

!

'

,

'

I

Display Blanking Control
Horizontal Sync Width
' - -_ _ _ _ _ _ _ _ _ Vertical Sync Width, low bits

----,r

'----'--'-_HF.....P...-"'---'-----'_V_'S_"

\~'----

P5

DH

PH

HBP

P6

VH

VL

VFP

VBP

1...-- The
display is enabled
bya 1, and blanked by

BLANK1: L_,---,---,_-,--,-_",--_ILD-.-JE
.
.
.

aD.
Vertical Sync Width, high bits

BLANK2:

BLANK 2 does not cause the resyncing of an HGDC in
slave mode. BLANK 1 does cause the resyncing of an
HGDC in slave mode.

I-I-- Vertical Front Porch Width

Zoom Factors Specify

Active Display Lines per
I-- Video
Field, low bits

AL..

1-

Active Display .Lines per

'----'---'-_""\_~.'._. -_-_L.:_-':_-:_-_--'_!_ Video Field,
"-

high bits

Vertical Back Porch Width

P'

This command also loads parameters into the sync generator, The various parameter fields and bits are identical
to those at the RESET command, The HGDC is not reset
nor does it enter idle mode.

Vertical Sync Mode
VSYNC:

OISP

~zoom factor for graphics

GCHR

'---~-'-'-.:\--'-_'----'---'_-'-__'

character writing and area

filling

\
~--------

Display zoom faclor

Zoom magnification factors of 1 through 16 are available
using codes 0 through 15, respectively.

Cursor Position Specify

1,--0~,_,~_~~~_~,--'-I_~.-'

L

LI_,---,---,_-,--,-_-,--_ILD_E...JI

Horizontal Front Porch Width

Horizontal Back Porch Width

AL,

P7

PB

0 , 1 , '

The START command generates the video signals as
specified by the RESETX or SYNC command.

Active Display Words per
line Must be even
number with bit 0 0

P3

P4

I

Mode of Operation select bits

0 -Accept External Vertical

CURS:

Sync - Slave Mode

0

1

1 -Generate & Output Vertical
Sync - Master Mode

When using two or more HGDCs to contribute to one image,
one HGDC is defined as the master sync generator, and the
others operate as its slaves, The VSYNC pins of all HGDCs
are connected together.
A few considerations should be observed when synchronizing two or more HGDCs to generate overlayed video via
the V/EXT SYNC pin. As mentioned above, the Horizontal
Front Porch (HFP) must be 4 or more display cycles wide.
This is equivalent to eight or more clock cycles, This gives
the slave HGDCs time to initialize their internal video sync
generators to the proper point in the video field to match the
incoming vertical sync pulse (VSYNC). This resetting of the
generator occurs just after the end of the incoming VSYNC
pulse, during the HFP interval. Enough time during HFP is
required to allow the slave HGDC to complete the operation
before the start of the HSYNC interval.
Once the HGDCs are initialized and set up as Master and
Slaves, they must be given time to synchronize. It is a good
idea to watch the VSYNC status bit of the Master HGDC
and wait until after one or more VSYNC pulses have been
generated before the display process is started. The START
command will begin the active display of data and will end
the video synchronization process, so be sure there has
been at least one VSYNC pulse generated for the Slaves to
synchronize to.

P'

EAD

I--

Execu'e Word Address,
low byte

I--

Execu'e Word Address.
middle byte

'--~-'-_~-'-__'_-'---'--'_

EAD

P2

'---'--'-_~-'---'_-'-__'--'_

P3

1WG I

dAD

0

1

E~D

I---

(Graphics Mode only)

~::~::~:~~:~~~

'---'--\-\..'-'
-

_ _ word Address, top bits
Dot Address within the word

In character mode, the third parameter byte is not needed.
The cursor is displayed for the word time in which the display scan address (DAD) equals the cursor address. In
graphics mode, the cursor word address specifies the word
containing the starting pixel of the drawing; the dot address
value specifies the pixel within that word.
When the WG bit issettoone, any data following the WDAT
command is written as is. When the WG bit is set to zero,
the 7220A performs as the 7220 does: The pattern written
is determined by the least significant bit of each parameter
byte following the WDAT command. This bit is expanded
into 16 identical bits which form the pattern.

318

Parameter RAM Load
PRAM:

LI_O~__~~l~I__~_SrA__~~
'----_ _ _ _ _ Starting Address in
parameter RAM

I ,

to 16 bytes to be loaded
'-----'----'__~~__-'---'--___''___'r into the parameter RAM

P,
I
I
I

starting at the RAM address

specified by SA

Po

From the starting address, SA, any number of bytes may
be loaded into the parameter RAM at incrementing
addresses, up to location 15. The sequence of parameter
bytes is terminated by the next command byte entered into
the FIFO. The parameter RAM stores 16 bytes of information in predefined locations which differ for graphics and
character modes. See the parameter RAM discussion for
bit assignments.

Pitch Specification
PITCH:

P1:

LI_o-'--___'~~~__~~__'___'~1

l. __~--'----'___"_-'--__

!

"----'----ll

Mask Register Load
Number of word addresses
in display memory in the
horizontal direction

This value is used during drawing by the drawing processor.
to find the word directly above or below the current word,
and during display to find the start of the next line.
The Pitch parameter (width of display memory) is set by two
different commands. In addition to the PITCH command,
the RESET (or SYNC) command also sets the pitch value.
The "active words per line" parameter, which specifies the
width of the raster-scan display, also sets the Pitch of the
display memory. Note that the AW value is two less than the
display window width. The PITCH command must be used
to set the proper memory width larger than the window width.

DRAWING CONTROL COMMANDS
Write Data into Display Memory

"'----RMW Memory cycle
Logical Operation:

o _____ REPLACE with Pattern
1 _____ COMPLEMENT

o .........-- RESET to zero
1~SETto1

' - - - - - - - - - - - Data Transfer Type:

::======LOW

o _c<--_ _ _ _ _ _ Word, Low then High byte

o1
1

•

High Byte
Byteafthe
of the Word
Word
Invalid

•

during the RMW memory cycle.
In graphics bit-map situations, only the LSB of the WDAT
parameter bytes is used as the pattern in the RMW operations. Therefore it is possible to have only an all ones or
all zeros pattern. If the WG bit of the third parameter of the
CURS command is se110 one, any byte following the WDAT
command is written as is. In coded character applications
all the bits of the WDAT parameter:? are used to establish
the drawing pattern.
The WDAT command operates differently from the other
commands which initiate RMW cycle activity. It requires
parameters to set up the Pattern register while the other
commands use the stored values in the parameter RAM.
Like all of these commands, the WDAT command must be
preceded by a FIGS command and its parameters. Only the
first three parameters need to be given following the FIGS
opcode, to set up the type of drawing, the DIR direction, and
the DC value. The DC parameter + 1 will be the number of
RMW cycles done by the HGDC with the first set of WDAT
parameters. Additional sets of WDAT parameters will see a
DC value of 0 which will cause only one RMW cycle to be
executed per set of parameters.

MASK:

LI_o-,--~__--,----,__~--,-__~O...JI

Pl

,--I~~M~,-'----"-~I

Low significance byte

L-I-'-----'--~M"--'----'-~I

High significance byte

P2

This command sets the value of the 16-bit Mask register of
the figure drawing processor. The Mask register controls
which bits can be modified in the display memory during a
read-modify-write cycle.
The Mask register is loaded by the MASK command and
the third parameter byte of the CURS command. The MASK
command accepts two parameter bytes to load a 16-bit value
into the Mask register. All 16 bits can be individually one or
zero, under program control. The CURS command on the
other hand, puts a "1 to 16" pattern into the Mask register
based on the value of the Dot Address value, dAD. If normal
single-pixel-at-a-time graphics figure drawing is desired,
there is no need to do a MASK command at all since the
CURS command will set up the proper pattern to address
the proper pixels as drawing progresses. For coded character DMA, and screen setting and clearing operations using
the WDAT command, the MASK command should be used
after the CURS command if its thirq parameter byte has
been output. The Mask register should be set to all "ONES"
for any "word-at-a-time" operation.

Valid Figure Type Select Combinations
P1

P2
etc,

WORD l OR BYTe

~ Word low Oata Byte or

'-----'----'__~~__-'---'--___'__I- -

I

Single Byte Data value

SL

R

A

GC

Operation

L

Character Display Mode Drawing, Individual Dot Drawing,

WORD H

L- Word transfer only:

L___,__~~__-,--~__~-,--_l

OMA, WDAT, and RDAT

High Data Byte

Straight Line DraWing

Upon receiving a set of parameters (two bytes for a word
transfer, one for a byte transfer), one RMW cycle into Video
Memory is done at the address pointed to by the cursor EAD.
The EAD pointer is advanced to the next word, according
to the previously specified direction. More parameters can
then be accepted.
For byte writes, the unspecified byte is treated as all zeros

Graphics Character Drawing and Area filling with graphics
character pattern
Arc and Circle Drawing
~____~~~__~R~ec~la~ng~le~D~ra~~in~g____________________

Slanted Grapnics Character Drawing and Slanted
Area Filling

Only these bit combinations assure correct drawing
operation.

319

Figure Draw Start

Graphics Character Draw and Area Filling Start

~~ .LI_O~__~~__~~__~~_O~I
On execution of this instruction, the HGDC loads the
parameters from the parameter RAM into the drawing
processor and starts the drawing process at the pixel pointed
to by the cursor, EAD, and the dot address, dAD.

Based on parameters loaded with the FIGS command, this
command initiates the drawing of the graphics character or
area filling pattern stored in Parameter RAM. Drawing
begins at the address in display memory pointed to by the
EAD and dAD values.

DATA READ COMMANDS
Figure Drawing Parameters Specify

LI_0-L__L-~

FIGS:

__L--L__

Read Data from Display Memory

L-~_o~1
Data Transfer Type:

o
PI

o-.------Low byte of the Word only

Drawing Direction Base

I _.- - - - - - H i g h byte of the Word only

Figure Type Select Bits:

I - ..
------Invalid

' - - - - - - - Line (Vector)
' - - - - - - - - - Graphics Character
' - - - - - - - - - - - Arc/Circle
' - - - - - - - - - - - - Rectangle
' - - - - - - - - - - - - - - Slanted Graphics Character

P2

rl~~~D~C'~~r-I DC Drawing Parameter

-,---,----,It

I'--.-L

P3 1"--1 GD I---'---L---L-DC"

\~_ _ _ _ _ _ _ _ _ GraPhiCS Drawing flag for use in
Mixed Graphics and Character Mod

P4

P5

P6

P7

Using the DIR and DC parameters of the FIGS command
to establish direction and transfer count, multiple RMW
cycles can be' executed without specification of the cursor
address after the initial load (DC = number of words or
bytes).
As this instruction begins to execute, the FIFO buffer direction is reversed so trat the data read from display memory
can pass to the microprocessor. Any commands or parameters in the FIFO at this time will be lost. A command byte
sent to the HGDC will immediately reverse the buffer direction back to write mode, and all RDAT information not yet
read from the FIFO will be lost. MOD should be set to 00 if
no modification to video buffer is d?sired.

Cursor Address Read

ci~~~D~'~::::;'I 0 Drawing Parameter
ILI__

~-L ~~ D~" ~~~U
__

__ __

ci;==~~D2~'~~'I
ILI__~-L

__

~~ D~~_"-L ~_D
__

The following bytes are returned by the HGDC through the
FIFO:
02 Drawing Parameter
PI

P9

A7

Execute Address (EAD),
low byte

__

P2

P8

O-.~-----Word,lowthenhighbyte

A15

EADM

~

";========~==~

d;=~~DI~'~~CI 01 Drawing Parameter

P3

_
'----'-__'----'-__- ' -.......__'----'-~

I. .__

Execute Address (EAD),

m!ddlebyte
Execute Address (EAD),
high bits

..

~~ ~"~"-

L--L__L--L__D'-I"__'---L----'f)

..

Dot Address (dAD), high byte

PIO~~~DM~'~~tDMDraWingparameter
Pl1
_

'i

..

'L' ,
.:..

:he parameters take on
different mterpretatlo!1s for
different figure types.

The Execute Address, EAD, points to the display memory
word containing the pixel to be addressed.
The Dot Address, dAD, within the word is represented as a
1-of-16 code for graphics drawing operations.

320

DMA CONTROL COMMANDS

Light Pen Address Read

DMA Read Request
OMAR:

The following bytes are returned by the HGDC through the
FIFO:

11

1 1 TYPE 11 1 MOO

'--,-_,--....L._I=I:.===~=~

D.ta Transfer Type:

°_.o-------Word,
°-.o__-----Low Byte altha Word

Low then High Byte

_~........_LA...o_,-,-~_-,-A_0..JI--- Light Pen Addr.ss, low byte

0<_----- High Byte of the Word

1 - ..

,-1_A7........
,

1 _.o<_-----!nvalid

I,-

_~

A_1S
........
,

........_LA
........
O"_,--......._
1

A_8",J~ Light Pen Address,

...

•

1-

I'-_o-,-_,--........_,---,-_O-,I_LA
........
O_".....

middle byte

DMA Write Request

Light Pen Address, high byte

ru.!A\ll:
~RMW

The light pen address, LAD, corresponds to the display word
address, DAD, at which the light pen input signal is detected
and deglitched,
The light pen may be used in graphics, character, or mixed
modes but only indicates the word address of light pen
position,

Memory logical Operation:

0........-- REPLACE with Pattern

1 --COMPLEMENT
0.......- RESET to Zero
1~SETtoOne

1 - - - - - - - O a I 8 Transfer Type:

°•
°_.----1 -.0-------

Word, Low then High Byte
Low

~yte

1 _.- - - - - I n v a l l d

321

of the Word

High Byte aftha Word

ELECTRICAL CHARACTERISTICS

Voltage on Any Pin with Respect to Ground
Power Dissipation
'COMMENT: Exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC CHARACTERISTICS T.

= O°C to 70°C; Vee = SV ± 10%; GND = OV

Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Leak Current
(except VSYNC. r:>ACJ<)
Input Low Leak Current
(VSYNC. DACR)
Input High Leak Current
(except LPEN/DH)
Input High Leak Current
(LPEN/DH)
Output Low Leak Current
Output High Leak Current
Glock Input Low Voltage
Clock Input High Voltage
Vee Supply Current

CAPACITANCE Ta

Limits
Typ

Max
0.8
Vee + 0.5
0.45

Unit
V
V
V
V

-10

fLA

I'L

-500

fLA

I'H

+10

fLA

I'H

+500

fLA

-10
-10
0.6
Vee- 1.O
270

fLA
fLA
V
V
mA

Symbol
VIL

Min
-0.5
2.2

V'H
VOL
VOH
III

2.4

10L
10H
VeL
VeH
Icc

-0.5
3.5

Test
Conditions
(j)

®®
10L = 2.2 mA
10H = - 400 fLA
V, = OV

V, = Vee
Vo = OV
Vo = Vee

= 2SoC; Vee = GND = OV

Parameter
Input Capacitance
1/0 Capacitance
Output Capacitance
Clock Input Capacitance

Symbol

Cf

AC Characteristics, Ta

Parameter
Address Setup to RD !
Address Hold from RD !
RD Pulse Width
Data Delay from RD !
Data Floating from RD !
RD Pulse Cycle

Write Cycle
Parameter
Address Setup to WR !
Address Hold from WR !
WR Pulse Width
Data Setup to WR!
Data Hold from WR
WI'! Pulse Cycle

Limits
Typ

COUT

Notes:
(j) For2XWCLK. V'L = -0.5Vto +O.6V.

Read Cycle

Min

Unit
pF
pF
pF
pF

Max
10
20
20
20

Test
Conditions
fc = 1 MHz

V,
(unmeasured) = OV

® ForWR. V'H=2.5VtoVee+0.5v'

® For 2XWCLK. V'H = + 3.9V to Vee + 1.0V.

= O°C to 70°C; Vee = S.OV ± 10%; GND = OV

(HGDC-CPU)
Symbol
tAR
tRA
tRRl

tR01
to,
tRCY

7220AD Limits
Min
Max
0
0
t RCY-% tClK
tRD • +20
75
0
75

7220AD-1 Limits
Max
Min
0
0
tRCy-%tCLK
tADl + 20
65
65
0

7220AD-2 Limits
Min
Max
0
0
tRCy-%tCLK
tRDl + 20
55
0
55

4 tClK

4 tClK

7220AD Limits
Min
Max
0
10
80 .
twCY - tCLK
65
10

7220AD-1 Limits
Min
Max
0
10
70
twCY - tClK
55
10

7220AD-2 Limits
Min
Max
0
10
60
twCY - tClK
45
10

4 teLK

4 tClK

4tCLK

4 teLK

Unit
ns
ns
ns
ns
ns
ns

Test
Conditions

CL = 50pF

(HGDC .....CPU)
Symbol
tAW
tWA
tww
tow
two
twCY

322

Unit
ns
ns
ns
ns
ns
ns

Test
Conditions

DMA Read Cycle

(HGDC<-+CPU)

7220AO Limits'
Symbol
Min
Parameter
Max
DACK Selup 10 RD 1
0
IKR
DACK Hold from RD 1
0
IRK
RD Pulse Widlh
tAD2 + 20
tRR2
Dala Delay from RD 1
1.51cLK + 80
tRD2
DREQ Delay from
t AEO
100
2XWCLKl
DREQ Selup 10 DACK 1
0
10K
DACK High Level Widlh
10K
tCLK
DACK Pulse Cycle
4 t CLK "
IE
DREQ 1 Delay from
IClK + 100
tKQ(R}
DACKI
DACK Low-level Widlh
ILK
2tClK
'for high byle and low byle Iransfers: IE = 51 clK

DMA Write Cycle
Parameter
DACK Selup 10 WR 1
DACK Hold from WR 1

R/M/WCycie
Parameter
Address/Dala Delay
from 2XWCLK 1
Address/Dala Floaling
from 2XWCLK 1
Inpul Dala Selup 10
2XWCLKl
Inpul Dala Hold from
2XWCLK 1
DBIN Delay from
2XWCLKl
ALE 1 Delay from
2XWCLKI
ALE 1 Delay from
2XWCLKl
ALEWidlh
ALE Low Widlh
Address Selup 10 ALE 1

Display Cycle
Parameter
Video Signal Delay
from 2XWCLK 1

Input Cycle
Parameter
Input Si~nal Selup 10
2XWCL 1
Input Signal Widlh

Clock
Parameter
Clock Rise Time
Clock Fall Time
Clock High Pulse Widlh
Clock Low Pulse Widlh
Clock Cycle

7220AO-1 Limits
Min
Max
0
0
tRD2 + 20
1.51CLK + 70

7220AO-2 Limits
Min
Max
0
0
t R02

+ 20
1.51cLK

85
0

+ 60

75
0

tCLK

tCLK

4t CLK '

4tCLK "

IClK

ns

Test
Conditions

Cl - 50pF
Cl

= 50 pF

ns
ns
ns

+ 90

2tcLK

Unit
ns
ns
ns
ns

IccK

+ 80

ns

Cl = 50 pF

ns

2tCLK

(GDC<-+CPU)
7220AO-l Limits
Min
Max
0
J
0

I

7220AO-2 Limits
Min
Max
0
0

Unit
ns
ns

7220AO Limits
Min
Max

7220AO-l Limits
Min
Max

7220AO-2 Limits
Min
Max

Unit

lAD

20

105

20

90

15

80

ns

Cl

= 50pF

tOFF

20

105

20

90

15

80

ns

Cl

= 50 pF

t Ol8

0

Symbol
IKW
IWK

7220AO Limits
Min
Max
J
0
0

I
I

J

J
J
I

Test
Conditions

(GDC<-+Display Memory)
Symbol

0

ns

0

IDE

Test
Conditions

ns

tOlH

IDE

IDE

20

80

20

70

15

60

ns

Cl

= 50pF

IRR

20

80

20

70

15

60

ns

Cl

= 50pF

IRF

20

65

20

55

15

50

ns

Cl

= 50 pF

IRW
IRL
lAA

%tcLK
1.51cLK - 30

ns
ns
ns

Cl - 50pF

30

tOE

1/3 tCLK

%t CLK

1.51clK - 30
30

1.51clK - 30
30

(GDC<->Display Memory)
Symbol

72200 Limits
Min
Max

72200-1 Limits
Min
Max

72200-2 Limits
Min
Max

I

J

I

I

Ivo

I

90

I

80

70

Unit

Test
Conditions

ns

CL = 50pF

Unit

Test
Conditions

(GDC<->Display Memory)
Symbol

7220AO Limits
Min
Max

7220AD-l Limits
Min
Max

7220AD-2 Limits
Min
Max

tps

10

10

10

ns

tpw

tcu<

tCLK

tClK

ns

7220AD Limits
Min
Max
15
15
70
70
165
10,000

7220AD-l Limits
Min
Max
15
15
61
61
145
10,000

7220AO-2 Limits
Min
Max
15
15
52
52
125
10,000

(2XWCLK)
Symbol
ICR
ICF
ICH
ICl
tCLK

323

Unit
ns
ns
ns
ns
ns

Test
Conditions

Display Memory Display Cycle Timing

Microprocessor Interface Write Timing
AO.1iiViiiidJt

~

Valid

- -....ft'WRatt
WR:

ww

1-

w
,

j~

DBO-7:--;'ln-va"'II"'d-7I-~--:-ln-va-::II""d-'1-

I---tw"

1

Microprocessor Interface Read Timing

DBO~ 7:_~H~i9;;h~~-K::~~r}H;;;;;;;;;;;;.;:;;;;;;;-r--Impedance
High Impedance
i o - - - - - tRCy

Display Memory RMW Timing
Microprocessor Interface DMA Write Timing
2xWCLK:

ADO-1S:

2xWCLK:

DREQ:

A1S, A17:_+-'I9I-_ _ _ _ _ _-f___.-J'-_

DACK:

ALE:

WR:

' 1 - - - - - t RC
tWH

(WR

i to HSYNC t ) ;? tCL~

t~H (DACK

l

to HSYNC

i) "" tw

Microprocessor Interface DMA Read Timing

2xWCLK:

OREa:

DACK:

-----hrr::::=--~=:i}+:::::::~

RD':-

DBO

7:--;;;;;;;;;;;;;;;;;;;;;;;:;--{!~~)(3~u~~;;;;;;::
Impedance

TIMING WAVEFORMS

324

-------1

Display and RMW Cycles (1x Zoom)

2xWCLK:

ALE:

DliiN:
W
I\J

01

ADD-IS:

AI6,17:

HSYNC:
BLANK:
V/EXTSYNC:

TIMING WAVEFORMS

Display and RMW Cycles (2x Zoom)

2xWCLK.

DBIN:

\

/

~

Ol

Output Address

AOG-15:

Output Address

Output Address

Input Data

I
IX

Output Data

Output Address}

I
A16.17,:D

BLANK,

X

X

----r\

/

TIMING WAVEFORMS

I

X'-_ __

\

Zoomed Display Operation with RMW Cycle (3x Zoom)

2xWClK:

ALE:y

OBIN,

w

ro

.....

\

I

\

I
I

\

.~. ,+o. ."'_,_)
A16.17

Blank'

I

:J=x:

---r==\

I

/

(~. . ~. . )----{ '"~~ _O~)
H

I

~

,

(~"

.. _.}-

X

X'-_____

I

\

I

TIMING WAVEFORMS

Clock Timing (2XWCLK)

Light Pen and External Sync Input Timing

2XWCLK'~a==e;
LPEN,---EX. SYNC,
lew

Video Sync Signals Timing

I'

1H

2XWCLK'../'J\.../\./\J ____ ~ _ _..f\J\..r

1

___ J'J\... __ J\..

HBLANK:J

!

HSYNC,

\1...._____________

ADO.,5:X:=::::X==::X= ~ ~ ~:: ::x==x==x::~ ::::-:::x::::x.::~:: x:=:::: ~ ~t
LCQ-4,==:X

' \

r--1H--1--------------------------------------------~

ADO"5':txx=:: :x:~OOC::xx:xx::::::::::~ =::~ =:: =~= ~ ===:: =:: == ::==:x:x::xx::::: xx::
=== ::t=::==x::::=== ====:::: ~::::::::::==::=:: == =:: =x::=::~~:x:
LCD-4'=t=

>c

ROW:=*
I

____________________ 1

t

__________________________ _

ROW:=*====*==x:: ----::::x=::=::x--------I

VBLANK:

----

1

!

'-- _ _ _ _

.J!

VSYNC'-..'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

t - - - - - - - - - - - - - - - 1V ( F r a m e ) - - - - - - - - - - - - - - - - - \

Interlaced Video Timing
HBLANK'JL __

...JLJL __ ..JLJL __ ~ __ .JL __ -IL __ JLJL __ .JL.JL_

I

I

1

1

VBLANK:L __ ~---I------I----L

:

' I

VSVNC: ,
(Interlace) I

I

1

1

1

I

I

1

1

1

__ S - - - - , - I - - - - - I - I - -

'

I

I

~

I

~I'-----__

Odd Field
1

----'-----1------

,

Even Field - - - - ' 1 - - I

I

(NOI~~e~~~~)---------'1

~
TIMING WAVEFORMS

328

r---------

-----------,
Clock

CRT 7220A
HGDC

DBC)'?
Data

MJ

~
W

I\)

(0

~

HSYNC

i

LPEN

Host
Computer

---------------------------~

BLOCK DIAGRAM OF A GRAPHICS TERMINAL

Video Horizontal Sync Generator Parameters

1~'------------------------1H----------------------~
~

HBLANK:--.J

__________________________

I

I
~r-

I

I
HSYNC: _ _ _ _' - _ - - - - ' I l L_ _ _ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____'__

I
I

I

---1

I

H=-t

I

I

I

~HBP---f------C/R---------I.I

Video Vertical Sync Generator Parameters

I1-'- - - - - - - 1 V - - - - - - - - - - - I ° 1
VBLANK:

I

I
I

I

~
I
I

VSYNC:--.IlL_ _ _ _.:....._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.--_ _~nl.-----I--

I

I

I

I

I

I

I

I

I

I

iVFPrl

I

I--

VBP

- - 1 - - - - - - - L/F------------\-.!

i

----l
Cursor-Image Bit Flag

2 x CCLK

HBLANK
HSYNC

CRS-Image

--l I-- IcCK
...Il.IUUl

--J:r

rf----l f I----

Y1s

1
~

~ I~

10 IcCK

Invalid

----l/L
x::~
Image

TIMING WAVEFORMS

330

tBP----j

VS

VIDEO FIELD TIMING
~

rL.-

HSYNCOutput
BLANK Output

~.,'

'

~

H----i---------;;:::::;::::;-;;"''"'''"'"'CC:-:,----------1:,,.. ; ... _-Vertical SYNC Lines
Vertical Back Porch Blanked Lines
Horizontal
SYNC~

Pulse
Horizontal
Front Poreh - - I
Blanking

,

0-

;3
U
Z

Active
Display
Lines
Horizontal
Back Porch
Blanking

~

r-Vertical Front Porch Blanked Lines

DRAWING INTERVALS

~

Drawing Inlerval

~ Additional Drawing Interval When
~ in Flash Mode

~ Dynamic RAM Refresh if Enabled, Otherwise
~ Additional Drawing Interval

DMA REQUEST INTERVALS

DMA Request Interval
Additional DMA Request Intervals
When in Flash Mode

331

STANDARD MICROSVSTEMS
CORPORATION
JSMartU56l11dt1~NVI1188

[511;'n33100 TWXS10??1889!!

Circuit diagrams utilizing SMC products are included as a means of illustrating typical applications; consequently
complete information sufficient for construction purposes is not necessarily given. The information has been carefully

checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore,
such information does not convey to the purchaser of the products described any license under the patent rights of
SMC or others. SMC reserves the right to make changes at any time in order to improve design and supply the best

product possible.

332

CRT 8002
J.L PC FAMILY

CRT Video Display Attributes Controller
Video Generator
VDACTM
PIN CONFIGURATION

FEATURES

o On chip character generator (mask programmable)
o

o
o
o

o

o
o
o

VIDEO

1

28 RETBL

27 CURSOR
128 Characters (alphanumeric and graphic)
LD/SH 2
7 x 11 Dot matrix block
VDC 3
26 Ms\l
On chip video shift register
A0 4
25 MS1
Maximum shift register frequency
A1 5
24 BLINK
CRT 8002A
20MHz
A2 6
23 V SYNC
CRT 8002B
15MHz
A3 7
22 CHABL
CRT 8002C
10MHz
A4 8
21 REVID
Access time
400ns
On chip horizontal and vertical retrace video blanking
20 UNDLN
A5 9
No descender circuitry required
A6 10
19 STKRU
Four modes of operation (intermixable)
18 ATTBE
A7 11
Internal character generator (ROM)
17 GND
Vee 12
Wide graphics
16 Rjl
R2 13
Thin graphics
15 R1
R3 14
External inputs (fonts/dot graphics)
Subscriptable
On chip attribute logic-character, field
Reverse video
Expandable character set
Character blank
Exte rn al fo nts
Character blink
Alphanumeric and graphic
Underline
RAM, ROM, and PROM
Strike-thru
On chip address buffer
Four on chip cursor modes
On chip attribute buffer
Underline
+ 5 volt operation
Blinking underline
TTL compatible
Reverse video
MaS N-channel silicon-gate COPLAMOS® process
Blinking reverse video
CLASp® technology-ROM and options
Programmable character blink rate
Com~atible with CRT 5027VTAC®
Programmable cursor blink rate

o
o

o
o
o
o
o
o
o

General Description
The CRT 8002 attributes include: reverse video, character blank, blink, underline, and strike-thru. The
character blink rate is mask programmable from 7.5 Hz
to 0.5 Hz and has a duty cycle of 75/25. The underline
and strike-thru are similar but independently controlled functions and can be mask programmed to any
number of raster lines at any position in the character
block. These attributes are available in all modes.
In the wide graphic mode the CRT 8002 produces a
graphic entity the size of the character block. The
graphic entity contains 8 parts, each of which is associated with one bit of a graphic byte, thereby providing for 256 unique graphic symbols. Thus, the CRT
8002 can produce either an alphanumeric symbol or
a graphic entity depending on the mode selected.
The mode can be changed on a per character basis.

The SMC CRT 8002 Video Display Attributes Controller
(VDAC) is an N-channel COPLAMOS® MaS/LSI device
which utilizes CLASP® technology. It contains a
7X11X128 character generator ROM, a wide graphics
mode, a thin graphics mode, an external input mode,
character address/data latch, field and/or character
attribute logic, attribute latch, four cursor modes, two
programmable blink rates, and a high speed video
shift register. The CRT 8002 VDAC'· is a companion
chip to SMC's CRT 5027 VTAC. Together these two
chips comprise the circuitry required for the display
portion of a CRT video terminal.
The CRT 8002 video output may be connected directly
to a CRT monitor video input. The CRT 5027 blanking
output can be connected directly to the CRT 8002
retrace blank input to provide both horizontal and
vertical retrace blanking of the video output.
Four cursor modes are available on the CRT 8002.
They are: underline, blinking underline, reverse video
block, and blinking reverse video block. Anyone of
these can be mask programmed as the cursor function. There is a separate cursor blink rate which can
be mask programmed to provide a 15Hz to 1 Hz blink
rate.

The thin graphic mode enables the user to create single line drawings and forms.
The external mode enables the user to extend the onchip ROM character set and/or the on-chip graphics
capabilities by inserting external symbols. These external symbols can come from either RAM, ROM or
PROM.

333

MAXIMUM GUARANTEED RATINGS"
Operating Temperature Range ...............................................................O°C to + 70°C
Storage Temperature Range ........................
. ........................ - 55°C to + 150°C
Lead Temperature (soldering, 10 sec.) ............................................................... +325°C
Positive Voltage on any Pin, with respect to ground .................................................... +S.OV
Negative Voltage on any Pin, with respect to ground ...................
. ........................ -0.3V
'"Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies
exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on and off.
In addition, voltage transients on the AC power line may appear on the DC output. If this possibility
exists it is suggested that a clamp circuit be used.

ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C, Vcc= +5V:<::5%. unless otherwise noted)
Parameter
D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, V,L
High-level, V,H
INPUT VOLTAGE LEVELS-CLOCK
Low-level, V,L
High-level, V,H
OUTPUT VOLTAGE LEVELS
Low-level, VOL
High-level, VOH
INPUT CURRENT
Leakage, IL (Except CLOCK)
Leakage, IL (CLOCK Only)
INPUT CAPACITANCE
Data
LD/SH
CLOCK
POWER SUPPLY CURRENT
Icc

Typ.

Min.

Comments

Max.

Unit

O.S

V
V

excluding VDC
excluding VDC

O.S

V
V

See Figure6

V
V

IOL =0.4 mA, 74LSXX load
IOH= -20).tA

2.0

4.3
0.4
2.4

/lA
/lA

o:SV IN :'::V cc

10
20
25

pF
pF
pF

@1MHz
@1MHz
@1MHz

100

mA

10
50

O:SV,N:SV CC

A.C. CHARACTERISTICS
See Figure 6, 7

SYMBOL

PARAMETER

CRT 8002A

CRT 8002B

CRT 8002C

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

1.0

20

1.0

15

1.0

10

UNITS

VDC

Video Dot Clock Frequency

PWH

VDC-High Time

15.0

23

40

ns

PWL

VDC-Low Time

15.0

23

40

ns

400

tCY

LD/SH cycle time

t" t f

Rise, faU time

t SET•UP

Input set-up time

t HOLD

533
10

SOO
10

MHz

ns
10

ns

""'0

"",0

"",0

ns

Input hold time

15

15

15

ns

t pOI , tpDO

Output propagation delay

15

t,

LD/SH set-up time

10

15

20

ns

t,

LD/SH hold time

15

15

15

ns

50

334

15

65

15

100

ns

ROW ADDRESS
R0-R3

BLOCK

DIAGRAM

~

~

I

ADDRESS/DATA
INPUTS
~ ADDRESSI
DATA
LATCH
CURS OR

MODE SELECT~ - MODE SELECT1 _

~

1

LOGIC

I
I

~

t

-j

REVER SE VIDEO - CHAR ACTER BLANKUNDER LINE

-

BLINK

.

I
I

I

I

DECODER

tJ
I

J:::)

~r

I

C~

AtJ 7"

"""/

LOGIC
LOGIC

~ LOGIC

ATTRIBUTE
LOGIC

j::]

I

Jz~
A0

""""-1D

VIDEO DOT CLOCK
LOADI SHIFT

CP
SRI!

V""'~I

GRAPHIC
LOGIC

7x11x128
ROM

C6
V A7

~

I

I

v

I
I

ATTRIBUTE
LATCH

STRIK ETHRU_

I

I

LINE
DECODER

UNDERLINE
SELECT

I
I

I

I

I

SELECT

I

RETRA CE BLANK
ATTRI BUTE ENABLE

" ' '"'" 2J

I

A7

SHIFT
REGISTER
8 BIT

Q

SR7

VIDE o

CURSOR RATE
LOGIC

I CHARACTER RATE

4.3V
VDC
O.BV

2.0V
LD/SH

~'r-------~,"<

~"-------- O.8V

I

:
I

!

ALL INPUTS
(exceplVDC,LD/SHj

VIDEO
OUTPUT

~//~~;~
'l//////////
/ / // / / /~'i-::______________-ti': __-1~2'OV
~

x

--------".

FIGURE 7
AC TIMING DIAGRAM

~,"O,,_

O.8V

tser.up
I
I

Ii

I·

X~-2.0V

X

,------"""'"

~-----!i----'

I",

335

·1

~------

O.4V

DESCRIPTION OF PIN FUNCTIONS
SYMBOL

PIN NO.

INPUT/
OUTPUT

NAME

1

VIDEO

Video Output

0

2

LD/SH

Load/Slilli

I

3
4-11

VDC
A11-A7

Video Dot Clock
Address/Data

I
I

PowerSupply
Row Address
Ground
Attribute Enable

PS
I
GND
I

12
Vee
13,14,15,16 R2,R3,Rl,R0
17
GND
16
ATTBE

19

STKRU

Strike-Thru

I

20

UNDLN

Underline

I

21

REVID

Reverse Video

I

22

CHABL

Character Blank

I

23

V SYNC

V SYNC

I

24

BLINK

Blink

I

25
26

MSI
MStfj

Mode Select 1
Mode Select Iil

I
I

I

MSI

MS0

MODE

1
1
0
0

1
0
1
0

Alphanumeric
Thin Graphics
External Mode
Wide Graphics

FUNCTION
The video output contains the dot stream for the selected row of the alphanumeric, wide graphic, thin graphic, or external character after processing by
the attribute logic, and the retrace blank and cursor inputs.
In the alphanumeric mode, the characters are ROM programmed into ihe
77 dot~ (7X11) allocated for each of the 126 characters. See figure 5. The top
row (R ) and rows R12 to R15 are normally all zeros as is column C7. Thus, the
character is defined in the box bounded by Rl to R11 and C~ to C6. When a row
of the ROM, via the attribute logic, is parallel loaded into the 6-bit shift-register,
th'e first bit serially shifted out is C7 (A zero; or a one in RIOVID). It is followed
by C6, C5, through C~.
The tiining of the Load/ Shift pulse will determine the number of additional
(- -, zero to ,N) bac~eros (or ones if in REVID) shifted out. See figure 4.
When the next Load/Shift pulse appears the next character's row of the ROM,
via the attribute logic, is parallel loaded into the shift register and the cycle
repeats.
The 6 bit Shift~ster parallel-in load or serial-out shift modes are established
by the Load/ I t input. When low, this input enables the shift register for
serial shifting with each Video Dot Clock pulse. When high, the shift register
parallel (broadside) data inputs are enabled and synchronous loading occurs
on the next Video Dot Clock pulse. During parallel loading, serial data flow
is inhibited .. The Address/Data inputs (A0-A7) are latched on the negative
transition of the Load/Shift input. See timing diagram, figure 7.
Frequency at which video is shifted.
In the Alphanumeric Mode the 7 bits on inputs (AIil-A6) are internally decoded
to address one of the 126 available characters (A7=X). In the External Mode,
AtfJ-A7 i.9'used to insert an 6 bit word from a user defined external ROM, PROM
or RAM into the on-chip Attribute logic. In the wide Graphic Modes AIil-A7 is
used to define one of 256 graphic entities. In the thin Graphic Mode A0-A2 is
used to define the 3 line segments.
+ 5 volt power supply
These 4 binary inputs define the row address in the current character block.
Ground
A positive level on this input enables data from the Reverse Video, Character
Blank, Underline, Strike-Thru, Blink, Mode Select ~, and Mode Select 1 inputs
to be strobed into the on-chip attribute latch at the negative transition of
the Lbad/Shift pulse. The latch loading is disabled when this input is low.
The latched attributes will remain fixed until this input becomes high again.
To facilitate attribute latching on a character by character basis, tie ATTBE
high. See timing diagram, figure 7.
When this input is high and RETBL - 0, the parallel inputs to the shift register
are forced high (SRIll-SR7). providing a solid line segment throughout the
character block. The operation of strike-thru is modified by Reverse Video
(see table 1). In addition, an on-chip ROM programmable decoder is available
to decode the line count on which strike-thru is to be placed as well as to
program the strike-thru to be 1 to N raster lines high. Actually, the strike-thru
decoder (mask programmable) logic allows the strike-thru to be any number
or arrangement of horizontal lines in the character block. The standard strikethru will be a double line on rows R5 and R6.
When this input is high and RETBL - 0, the parallel inputs to the shift register
are forced high (SR0-SR7), providing a solid line segment ihroughout the
character block. The operation of underline is modified by Reverse Video
(see table 1). In addition, an on-chip ROM programmable decoder is available
to decode the line count on which underline is to be placed as well as to
program the underline to be 1 to N raster lines high. Actually, the underline
decoder (mask programmable) logic allows the underline to be any number
or arrangement of horizontal lines in the character block. The standard underline will be a single line on .R".
When this input is low and RETBL - 0, data into the Attribute Logic is presented
directly to the shift register parallel inputs. When reverse video is high data
into the Attribute Logic is inverted and then presented to the shift register
parallel inputs. This operation reverses the data and field video. See table 1.
When this input is high, the parallel inputs to the shift register are all set low,
providing a blank character line segment. Character blank will override blink.
The operation of Character Blank is modified by the Reverse Video input.
See table 1.
This input is used as the clock input for the two on-chip mask programmable
blink rate dividers. The cursor blink rate (50/50 duty cycle) will be twice the
character blink rate (75/25 duty cycle). The divisors can be programmed from
+ 4 to + 30 for the cursor (+ 6 to + 60 for the character):
When this input is high and RETBL - 0 and CHABL - 0, the character will blink
at the programmed character blink rate. Blinking is accomplished by blanking
the character block with the internal Character Blink clock. The standard
character blink rate is 1.675Hz.
These 2 inputs define the four modes of operation of the CRT 6002 as follows:
Alphanumeric Mode - In this mode addr.esses .AIil-A6 (A7=X) are internally decoded to address 1 of the 128 available ROM characters. The
addressed character along with the decoded row will define a 7 bit output
from the ROM to be loaded into the shift register via the. attribute logic.
Thin Graphics Mode~ In this mode A0-A2 (A3-A7=X) will be loaded
into the thin graphic logic along with the row addresses. This logic will
define the segments of a graphic entity as defined in figure 2. The top of
the entity will begin on row 0000 and will end on a mask programmable row.

336

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

SYMBOL

NAME

INPUT/
OUTPUT

25
26
(cant.)

27

CURSOR

Cursor

I

28

RETBL

Retrace Blank

I

FUNCTION
External Mode - In this mode the inputs M-A7 go directly from the
character latch into the shift register via the attribute logic. Thus the user
may define external character fonts or graphic entities in an external
PROM, ROM or RAM. See figure 3.
Wide GraRhics Mode-In this mode the inputs A0-A7 will define a graphic
entity as described in figure 1. Each line of the graphic entity is determined
by the wide graphic logic in conjunction with the row inputs R~ to R3. In
this mode each segment of the entity is defined by one of the bits of the
8 bit word. Therefore, the 8 bits can define any 1 of the 256 possible graphic
entities. These entities can butt up against each other to form a contiguous
pattern or can be interspaced with alphanumeric characters. Each of the
entities occupies the space of 1 character block and thus requires 1 byte
of memory.
These 4 modes can be intermixed on a per character basis.
When this input is enabled 1 of the 4 pre-programmed cursor modes will be
activated. The cursor mode is on-chip mask programmable. The standard cursor will be a blinking (at 3.75 Hz) reverse video block. The 4 cursor modes are:
Underline-In this mode an underline (1 to N raster lines) at the programmed
underline position occurs.
Blinking Underline-In this mode the underline blinks at the cursor rate.
Reverse Video Block-In this mode the Character Block is set to reverse
video.
Blinking Reverse Video Block-In this mode the Character Block is set to
reverse video at the cursor blink rate. The Character Block will alternate
between normal video and reverse video.
The cursor functions are listed in table 1.
When this input is latched high, the shift register parallel inputs are uncondition'!ffimcleared to all zeros and loaded ihto the shift register on the next
Load/ I t pulse. This blanks the video, independent of all attributes, during
horizontal and vertical retrace time.

TABLE 1
CURSOR

RETBL

REVID

CHABL

UNDLN*

X

X

X

X

0
0

1
0
0

0
0

0
0

0
1

0
0
0

0
0
0

0
1
1

1
0
0

X

0
Underline'

0
0

1
0

1
0

X
X

Underline'

0

0

1

X

Underline'

0

1

0

X

110"

Underline'

0

1

1

X

HO"

Blinking" Underline'

0

0

0

X

"1"
'11 "
D

Blinking" Underline'

0

0

1

X

Blinking" Underline'

0

1

0

X

"0"

Blinking" Underline'

0

1

1

X

"0"
"1"

REVID Block
REVID Block

0
0

0
0

0
0

0
1

D
"0"

REVID Block
REVID Block

P

1
0

X

"1"

0

0
0

1

"0"

REVID Block
REVID Block

0
0

1
1

0
0

0
1

D
"1"
D
HOll

0
1

"0"
D

"1 "
D

HO"
is

"0"

D

"1"
"1"
D
Hi"

"0"

D

'i1 "

"0"

is

is
is

FUNCTION
S.R. All
(q.R.)All
(S.R)'
(S.R.) All others
(S.R.)All
(S.R.)All
(S.R.) ,
(S.R.) All others
(S.R.)All
(S.R.)'
(S.R) All others
(S.R.)'
(S.R) Ali others
(S.R.)'
(S.R.) All others
(S.R)'
(S.R.) All others
(S.R.) , Blinking
(S.R.) All others
(S.R)' Blinking
(S.R.) All others
(S.R.)' Blinking
(S.R.) All others
(S.R.) , Blinking
(S.R.) All others
(S.R) All
(S.R.)'
(S.R.) All others
(S.R) All
(S.R)'
(S.R.) All others
(S.R.)All
(S.R)'
(S.R) All others
(S,R)All

0
1
1
X
REVID Block
0
0
Blink" REVID Block
0
0
1
0
0
0
Blink" REVID Block
1
X
0
0
Blink" REVID Block
{ "tom,to N"m,1 Vid,,/REVID
At Cursor Blink Rate
0
1
0
0
Blink" REVID Block
1
0
1
0
Blink" REVID Block
1
X
0
1
Blink" REVID Block
'At Selected Row Decode "At Cursor Blink Rate
Note: If Character is Blinking at Character Rate, Cursor will change it to Cursor Blink Rate.

337

FIGURE 5
ROM CHARACTER BLOCK FORMAT
R2

R1

Ra'

R0

0

0

0

0

0

0

0

0

0

0

R1

0

0

0

0

0

0

0

0

0

0

0

R2

0

0

1

0

0

0

0

0

0

0

0

0

R3

0

0

0

0

0

0

0

0

0

0

R4

0

0

0

0

R5

0

0

1

0

(ALL ZEROS)

R3

0

(ALL ZEROS) - - 0

77 BITS
(7x11 ROM)

ROWS

-------------0
0
0
0
0
0
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

R6

0

0

0

0

0

0

0

0

0

R7

0

1

1

1

0

0

0

0

0

0

0

0

R8

1

0

0

0

0

0

0

0

0

0

0

0

R9

0

0

0

0

0

0

0

0

0

0

0

R10

0

0

0

0

0

0

0

0

0

R11

0

0

0

0

0

0

0

0

R12

0

0

0

0

0

0

0

0

R13

0

1

{~
'C7

-------------0
0

0

0

0

0

0

0

R14

0

0

0

0

0

0

0

R15

C6

C5

C4

C3

C2

C1 C0

'COLUMN 7 IS ALL ZEROS (REVID = 0)
COLUMN 7 IS SHIFTED OUT FIRST

~ EXTENDED ZEROS (BACK FILL)
FOR INTERCHARACTER SPACING (NUMBER CONTROLLED
BY LO/SH, VDC TIMING)

CONSULT FACTORY FOR CUSTOM FONT AND OPTION PROGRAMMING FORMS.

338

0

0

FIGURE 1
WIDE GRAPHICS MODE
5 BITS"
ROW ADDRESS

0000

I

MSO=B MS1=O

N BITS"

I

3 LINES'

A7

C7 C6 C5 C4 C3 C2 Cl

1
R0'

A3

Rl

3 LINES

R2
3 LINES

R3

3 LINES

R4
R5
R6
R7

RS
'ON CHIP ROM PROGRAMMABLE TO 2, 3, OR 4 LINE MULTIPLES
• 'CAN BE PROGRAMMED FROM 1 TO 7 BITS

••• LENGTH DETERMINED BY lD/SH, VDC TIMING
EXAMPLE: 10010110

~,@

o/m1.1
~

NOTE: Unselected raster line rows.
are always filled with ones.

R14

~

R15 L -________________

~

BF=back fill

FIGURE 2
THIN GRAPHICS MODE
MSO=0' MS1 =1

N BITS

I

C7 C6 C5 C4 C3 C2 C1 CiJ BF BF ...

R)l'

-R ow 0000

R1
R2
R3
R4
R5
R6
R7
R8

l-

R9
R1.0'
PROGRAMMABLE

r-T7-:~"""""/·h"7:'7'7'7

R11

ROW

R12 L.L.£JC..£....<"<'.( / 'r<-~'-'-'i /
R13
R14

Ix IxIx Ix

x

I I I
A2

A1

R15
A0

NOTE: When A1 :=; "1 ", the underline
rowl rows are deleted.
When A1 = "0", the underline,
if selected, will appear.

X=DON'T CARE
THE INSIDE SEGMENT IS MASK PROGRAMMABLE
TO ROW 0000
"
LENGTH DETERMINED BY LD/S'R, VDC TIMING

BF=back fill

FIGURE 3
EXTERNAL MODE
MS0'=1 MS1=D
C7

R0'. - R15

C6

C5

C4

C3

C2

C1

A51 A41 A31 A2

A1

CI'l

I

SF

SF

A01 A71 A71· . ·1

SF=backfili

339

I

FIGURE 4

TYPICAL VIDEO OUTPUT

VDC

r-----l
18DorisDori
Isc:ioT"1
IgoaT"
LD/SH - - 1
I______________--'\.f~b.~ .£IEb.q.J'-_ _ _ _ _ _ _ _ _ _ _---':.fu:hQ.L-L£~b.~
VIDEO DATA

8 DOT FIELD
VIDEO DATA
9 DOT FIELD
NOTE: C. y
x = character number
y = column number

SIr-;-

BF=back fill

XTAL

~~

7404

74160
DOT
COUNTER
(+N)
CP

CARRY

I

CHARACTER CLOCK

VIDEO DOTCLOCK

ADDRESS BUS

~

DCC

H SYNC

DB0-7

V SYNC

A0-3

C SYNC

B

BI-DIRECTIONAL DATA BUS

4

CHIP SELECT

VTAC
CRT 5027

CS

LOGIC

DATA STROBE

BL

HORIZ.SYNC

....

o

VERT. SYNC

()

~

COMPOSITE
SYNC

o

BLANKING

=i

s:
z

o

o

:D

~

DS

B CHARACTER COLUMN
H0-7

6

CHARACTER ROW
DR0-5

III

DATA BUS
MICROPROCESSOR

ADDRESS BUS
CONTROL BUS

CHARACTER
ADDRESS
BUS

SELECTOR
WITH
OPTIONAL
MEMORY
MAPPING
CIRCUIT
(IF REQUIRED)

~

~

I

RAM & ROM
(FOR "PI

FIGURE 6

i~

'2-PORT RAM
lKx8 TO 4KxB
CHARACTER
FRAME
BUFFER

IN

~

7

DATA
BUS
ATTRIBUTES
VIDEO DOT
CLOCK

~
OUT

'OR 1 PORT RAM
WITH BI-DIRECT
PORT

CRV

RASTER
SCAN
COUNTER

ASCII

.LL ADDRESS
c.-

r

R0-3

TIMING
FROM
DOT COUNTER
OR
CHARACTER
CLOCK

VDAC
CRT 8002

-

()

c

:D
U>

0

-

:D
"n

,.
r-

G>

RETRACE
BLANKING
SERIAL
OUTPUT

CRT 5027 VTAC
CRT 8002 VDAC
J.lP CONFIGURATION

r - - - - - - - - - - V D C (to chip)

Vee

SOOn
cp EXTERNAL ---~

r-~-----~--~CLK

74S74
LOAD/SHIFT EXTERNAL----1D

340

Qt----~-LD/SH

(to chip)

CRT 8002-001
(KATAKANA)

CODING INFORMATION

CRT Video Display-Controller
Video Generator VDACTM

THIN GRAPHICS MODE

WIDE GRAPHICS MODE

C7 C6 C5 C4 C3 C2 Cl cp BF SF ..

RfI
RJJ

R1

R1

R2

:: H~-++-H~H.-1+~

R3

R'
RS

R'

R6

:: 1+--7-~>---7,~~+4-*l

R7

R7

R9

RS

R8

Hc-f-++H~r.H-+~

R1)1

Rll

NOTE

/fL'c:..:...<'-f/

::: LL..'-.L<:L.I.'(
R14

R15
R14
R15

NOTE: When At = '" ", the underline
row/rows are deleted.
When At;; "0", the underline.
if selected, will appear

NOTE: Unselected raster line rows
are always filled with ones.

~--------------~
BF""back fill

BF= back fill

ATTRIBUTES
Underline
Underline will be a single horizontal line at row R11
Cursor
Cursor will be a blinking reverse video block, blinking at 3.75 Hz

341

Blink Rate
The character blink rate will be 1.875 Hz
Strike-Thru
The strike-thru will be a double line at rows R5 and R6

CRT 8002-003
(5X7 ASCII)

CODING INFORMATION

CRT Video Display-Controller
Video Generator VDACTM

WIDE GRAPHICS MODE

THIN GRAPHICS MODE

C7 C6 C5 C4 C3 C2 Cl C{!
R0

R0

R1
R2
R3

R1
R2

.~H-""""r-r~+71

R3

R4

R4

:: I-+H~~*~

R5

R7

R7

R6

R8~~~

R8

R9

R9

R10
R11

Note: R11-R15 are

R12

always filled with ones.

R12

R13

R13

R14

R14

R15

R15

ATTRIBUTES
Underline
Underline will be a single horizontal line at H8
Cursor
Cursor will be a blinking reverse video block, blinking at 3.75 Hz

342

Blink Rate
The character blink rate is 1.875 Hz
Strike-Thru
The strike-thru will be a single horizontal line at R4

CRT 8002-005
(ASCII)

CODING INFORMATION

CRT Video Display-Controller
Video Generator VDAC ™

WIDE GRAPHICS MODE ..

THIN GRAPHICS MODE

C7 C6 C5 C4 C3 C2 C1 C0 SF BF,

C7 C6 C5 C4 C3 C2 C1 C0 BF

A~

A~

R1

A1

A2

A2

A3~~~~T-~~H

A3

A4

A4

A5

A5

A6

A7
AS

A6

~-*-*-%~-+~-8

A7
AS

A9

A9

Al1

Al1 Ir--:~""""'/ '--_,'"
A12 f-L--L....L.......L-L-""'V

A10

A13
A14
A15

ATTRIBUTES
Blink Rate

Underline

Underline will be a single horizontal line at R12

The character blink rate is 1.875 Hz

Cursor

Strike-Thru

Cursor will be a reverse video block

The strike-thru will be a double line at rows R5 and R6

343
-----------------------------------

CRT 8002-011
(ASCII)

CODING INFORMATION

CRT Video Display-Controller
Video Generator VDACTM

WIDE GRAPHICS MODE

THIN GRAPHICS MODE
C7 C6 C5 C4 C3.C2 Cl C0 BF

RQ

R0

Rl

Rl

R2

R2

R3

R3~~~~r7~~~

R4

R4

R5

R5h~-T

R6

R6

R7~~~~~~~~

R7

R8

R8

f.L.....4....L..-r

R9

ATTRIBUTES
Underline

Blink Rate

Underline will be a single horizontal line at R11

The character blink rate is 1.875 Hz

Cursor

Strlke-Thru

Cursor will be.a blinking reverse video block,
blinking at 3.75 Hz

The strike-thru will be a double line at
rows R5 and R6

344

CRT 8002-018
(5 X 7 ASCII)
CODING INFORMATION

CRT Video Display-Controller
Video Generator VDACTM

THIN GRAPHICS MODE

WIDE GRAPHICS MODE

R0

RI

Rl

Rl
R2
R3

~rf--H~~~

R2
R3

R4

R5
R6

R4

f+~~~~~8

R5
R6

R7

R7

RS

RS

R9

R9

~~~~.£.£~4-

Rl0

A11~R15 are

Al1

Note:

R12
R13

always filled with ones

R11

R12
R13

R14

R14

R15

R15

ATTRIBUTES
Blink Rate
The character blink rate is 1.875 Hz
Strlke-Thru
The strike-thru will be a single horizontal line at R4

Underline
Underline will be a double horizontal line at R7 and R8
Cursor
Cursor will be a reverse video block

345

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

346

---

~.-~--~~--------------------------

CRT8002H
/LPCFAMILY

CRT Video Display Attributes Controller
Video Generator
VDACTM
FEATURES

PIN CONFIGURATION

o On chip character generator (mask programmable)
o
o
o
o
o
o

o
o
o
o
o

VIDEO

128 Characters (alphanumeric and graphic)
7 x 11 Dot matrix block
On chip video shift register
Maximum shift register frequency 25 MHz
ROM Access time 310 ns
On chip horizontal and vertical retrace video blanking
No descender circuitry required
Four modes of operation (intermixable)
Internal character generator (ROM)
Wide graphics
Thin graphics
External inputs (fonts/dot graphics)
On chip attribute logic-character, field
Reverse video
Character blank
Character blink
Underline
Strike-thru
On chip cursor
Programmable character blink rate
Programmable cursor blink rate
Subscriptable
Expandable character set
External fonts
Alphanumeric and graphic
RAM, ROM, and PROM

LD/SH

2

28 RETBL
27 CURSOR

VDC
A0

3
4

26 MS~
25 MS1

A1

5

24 BLINK

AZ

6

23 V SYNC

A3

7

A4

8

22 CHABL
21 REVID

A5 9
A6 10

20 UNDLN
19 STKRU

A7 11

18 ATTBE

Vee 12

17 GND

R2 13
R3 14

16 R~
15 R1

o On chip address buffer
o On chip attribute buffer
o +5 volt operation
o TTL compatible
ON-channel COPLAMOS® Titanium
Disilicide Process
Compatible with CRT 5027/37 VTAC®

o

General Description
The SMC CRT 8002H Video Display Attributes Controller
(VDAC) is an n-channel COPLAMOS® MaS/LSI device. It contains a 7X11X128 character generator ROM,
a wide graphics mode, a thin graphics mode, an external
input mode, character address/data latch, field and/or
character attribute logic, attribute latch, four cursor
modes, two programmable blink rates, and a high speed
video shift register. The CRT 8002H VDAC is a companion chip to SMC's CRT 5027/37 VTAC®. Together
these two chips comprise the circuitry required for the
display portion of a CRT video terminal.
The CRT 8002H video output may be connected directly
to a CRT monitor video input. The CRT 5027/37 blanking
output can be connected directly to the CRT 8002H
retrace blank input to provide both horizontal and
vertical retrace blanking of the video output.
The CRT 8002H attributes include: reverse video, character blank, blink, underline, and strike-thru. The
character blink rate is -mask programmable from 7.5 Hz
to 1.0 Hz and has a duty cycle of 75/25. The underline

and strike-thru are similar but independently controlled
functions and can be mask programmed to any number
of raster lines at any position in the character block.
These attributes are available in all modes.
In the wide graphic mode the CRT 8002H produces a
graphic entity the size of the character block. The
graphic entity contains 8 parts, each of which is associated with one bit of a graphic byte, thereby providing
for 256 unique graphic symbols. Thus, the CRT 8002H
can produce either an alphanumeric symbol ora graphic
entity depending on the mode selected. The mode can
be changed on a per character basis.
The thin graphic mode enables the user to create single
line drawings and forms.
The external mode enables the user to extend the onchip ROM character set and/or the on-chip graphics
capabilities by inserting external symbols. These external symbols can come from either RAM, ROM or
PROM.

347
-----.~-~-~-~----~

MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range ...............................................................O'C to + 70'C
Storage Temperature Range .............................................................. -55'C to + 150'C
Lead Temperature (soldering, 10 sec.) ................................................................ +325'C
Positive Voltage on any Pin, with respect to ground ............................................. , ...... +8.0V
Negative Voltage on any Pin, with respect to ground .................................................... -0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies
exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on and off.
In addition, voltage transients on the AC power line may appear on the DC output. If this possibility
exists it is suggested that a clamp circuit be used.

ELECTRICAL CHARACTERISTICS (TA=O'C to 70'C, Vcc= +5V ±5%, unless otherwise noted)
Parameter

Min.

D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, V"
High-level, V'H
INPUT VOLTAGE LEVELS-CLOCK
Low-level, V'l
High-level, V'H
OUTPUT VOLTAGE LEVELS
Low-level, VOL
High-level, VOH
INPUT CURRENT
Leakage, Il (Except CLOCK)
Leakage, IL (CLOCK Only)
INPUT CAPACITANCE
Data
LD/SH
CLOCK
POWER SUPPLY CURRENT
Icc

Typ.

Comments

Max.

Unit

0.8

V
V

excluding VDC
excluding VDC

0.8

V
V

See Figure 6

V
V

IOl =0.4 mA, 74LSXX load
IOH=-20",A

2.0

4.3
0.4
2.4
10
50

fJA

O:SV'N:SV CC

/J.A

o:SV,N:SVcc

10
20
25

pF
pF
pF

@IMHz
@IMHz
@IMHz

100

mA

A.C. CHARACTERISTICS
See Figure 6, 7

SYMBOL

PARAMETER

MIN.

MAX.

UNITS

1.0

25

MHz

VDC

Video Dot Clock Frequency

PWH

VDC-High Time

11.0

ns
ns

PWL

VDC- Low Time

11.0

tCY

LD/SH cycle time

310

t" tf

Rise, fall time

ns

9

ns

tSET-UP

Input set-up time

2:0

ns

tHOLD

Input hold time

15

ns

15

tPDI. tPDD

Output propagation delay

t,

LD/SH set-up time

5

ns

t2

LD/SH hold time

5

ns

348

27

ns

ROW ADDRESS
R0-R3

I

I

I

I

I

BLOCK

DIAGRAM

~

I

~

ADDRESS!DATA
INPUTS
~ ADDRESS!
DATA
LATCH
CURS OR
RETRA CE BLANK

-.

ATTRI BUTE ENABLE
MODE SELECT¢ MODE SELECT1 _

UNDERLINE
SELECT

~

I

I
I

I

-l

~
LOGIC

I
I
I

I
"

"DECODER

J=)

I
~

STRIK E T H R U _

I

GRAPHIC
LOGIC

-~

7x11x12B
ROM

C6
V_ A7

C~

N1';?~

'-.. . /

ATTRIBUTE
LOGIC

LOGIC

j::J

LOGIC

I
D
CP
SR¢

VIDEO DOT CLOCK
LOAD! SHIFT

-I

~

~F

Jz~
A0

~
V
""
-N

I

I

I
I

LOGIC

.

_tJ

LINE
DECODER

v

~

REVER SE VIDEO CHAR ACTER BLANKATTRIBUTE
UNDE RLiNE _
LATCH
BLINK

STRIKE-THRU
SELECT

I

A7

SHIFT
REGISTER
8 BIT

Q

SR7

VIDE o

CURSOR RATE

LOGIC

I CHARACTER RATE

4.3V
VDC
O.BV

2.0V
LD!SH

~\----------!""'f
1

:

II

:

~.....- - - - - - - O.BV

t!
ALL INPUTS
(exceptVDC,LD/SH)

'

all//////////////~~~

'~:

~2'OV

'/////////////////1J".'i-ll------________--+:__--!
~

~ "0,"-

.O.BV

tsn.up
I

VIDEO
OUTPUT

__

~X~

FIGURE 7
AC TIMING DIAGRAM

~

I

_ _+i;~X'---~X.----2.0V'
I

I. ""

1PDO

349

-

·1

' - - - - - - - O.4V

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

SYMBOL

INPUTI
OUTPUT

NAME

1

VIDEO

Video Output

0

2

LO/SH

Load/Slilll

I

3
4-11

VDC
NJ-A7

Video Dot Clock
Address/Data

I
I

Power Supply
Row Address
Ground
Attribute Enable

PS
I
GND
I

12
Vee
13,14,15,16 R2,R3,Rl,R0
17
GND
18
AITBE

19

STKRU

Strike-Thru

I

20

UNDLN

Underline

I

21

REVID

Reverse Video

I

22

CHABL

Character Blank

I

23

V SYNC

V SYNC

I

24

BUNK

Blink

I

25
26

MSl
MSjil

Mode Select 1
Mode Select 0

I
I

MSl

MSIil

MODE

1
1
0
0

1
0
1
0

Alphanumeric
Thin Graphics
E>----'

I_

I

'--------

I,,,

356

-I

' - - - - - - - O.4V

MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range ........................................................... O°C to + 70°C
Storage Temperature Range .......................................................... -55°C to +150°C
Lead Temperature (soldering, 10 sec.) ........................................................... +325° C
Positive Voltage on any Pin, with respect to ground ................................................. +8.0V
Negative Voltage on any Pin, with respect to ground ................................................ -0.3V
*Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or at any other condition above those indicated in the
operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies
exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on and off.
In addition, voltage transients on the AC power line may appear on the DC output. If this possibility
exists it is suggested that a clamp circuit be used.

ELECTRICAL CHARACTERISTICS (TA =
Parameter

Min.

D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, V,L
High-level, V,H
INPUT VOLTAGE LEVELS-CLOCK
Low-level, V,L
High-level, V'H
OUTPUT VOLTAGE LEVELS
Low-level, VOL
High-level, VOH
INPUT CURRENT
Leakage, Ie (Except CLOCK)
Leakage, IL (CLOCK Only)
INPUT CAPACITANCE
Data
LD/SH
CLOCK
POWER SUPPLY CURRENT
Icc
A.C. CHARACTERISTICS
See Figure 6, 7

SYMBOL

ooe to 70 oe, Vcc =
Typ.

Max.

+5V ±5%, unless otherwise noted)
Unit

Comments

0.8

V
V

excluding VDC
excluding VDC

0.8

V
V

See Figure 7

V
V

10L = 0.4 mA, 74LSXX load
IOH=-20JiA

2.0

4.3
0.4
2.4

JiA
JiA

o"9J'N"9Jee
o"9J'N"9Jee

10
20
25

pF
pF
pF

@1 MHz
@1 MHz
@1 MHz

100

mA

10
50

CRT 8021

PARAMETER
MIN.
1.0

UNITS
MAX.

VDC

Video Dot Clock Frequency

PWH

VDC-High Time

15.0

20

MHz
ns

PWL

VDC-LowTime

15.0

ns

tey

LD/SH cycle time

400

t" tf

Rise, fall time

tSET-UP

I nput set-up time

ns
10

ns
ns

;:::0

tHOLD

I nput hold time

15

tpOI, tPDO

Output propagation delay

15

t,

LD/SH set-up time

10

ns

t,

LD/SH hold time

5

ns

357

ns
50

ns

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

SYMBOL

INPUT/
OUTPUT
0

1

VIDEO

NAME
Video Output

2

LD/SH

Load/Shift

I

3
4-11

VDC
A0-A7

Video Dot Clock
Address/Data

I
I

Power Supply
Row Address
Ground
Attribute Enable

PS
I
GND

12
Vee
13,14,15,16 R2,R3,Rl,R0
17
GND
ATTBE
18

I

19

STKRU

Strike-Thru

I

20

UNDLN

Underline

I

21

REVID

Reverse Video

I

22

CHABL

Character Blank

I

23

V SYNC

V SYNC

I

24

BLINK

Blink

I

25
26

MSl
MS0

Mode Select 1
Mode Select 0

I
I

FUNCTION
The video output contains the dot stream for the selected row of the wide graphic, thin
graphic, or external character after processing by the attribute logic, and the retrace
blank and cursor inputs.
The timing of the Load/Sti17i pulse will determine the number of additional (- -,
zero to N) backfill zeros (or ones if in REVID) shifted out. See figure 4.
When the next Load/Shift pulse appears the next character via the attribute logic, is
parallel loaded into the shift register and the cycle repeats.
The 8 bit shift-register parallel-in load or serial-out shift modes are established by
the Load/Shift input. When low, this input enables the shift register for serial
shifting with each Video Dot Clock pulse. When high, the shift register parallel
(broadside) data inputs are enabled and synchronous loading occurs on the next
Video Dot Clock pulse. During parallel loading, serial data flow is inhibited. The
Address/Data inputs (All-A?) are latched on the negative transition of the
Load/Shift input. See timing diagram, figure.l.
Frequency at which video is shifted.
In the External Mode, A0-A7 is used to insert an 8 bit word from a user defined
external ROM, PElOM or RAM into the on-chip Attribute logic. In the wide Graphic
Mode A0-A7 is used to define one of 256 graphic entities. In the thin Graphic
Mode A0-A2 is used to define the 31ine segments.
+5 volt power supply.
These 4 binary inputs define the row address in the current character block.
Ground
A positive level on this input enables data from the Reverse Video, Character Blank,
Underline, Strike-Thru, Blink, Mode Select 0, and Mode Select 1 inputs to be strobed
into the on-chip attribute latch at the negative transition of the Load/Shift pulse.
The latch loading is disabled when this input is low. The latched attributes will remain
fixed until this input becomes high again. To facilitate attribute latching on a character
by character basis, tie ATTBE high. See timing diagram, figure 1'.
When this input is high and RETBL = 0, the parallel inputs to the shift register are
forced high (SR0-SR7), providing a solid line segment throughout the character
block. The operation of strike-thru is modified by Reverse Video (see table 1). The
strike-thru is a double line on rows R5 and R6 for the CRT 8021 and a single line on
row R4 for the CRT 8021-003.
When this input is high and RETBL = 0, the parallel inputs to the shift register are
forced high (SRIl-SR7). providing a solid line segment throughout the character
block. The operation of underline is modified by Reverse Video (see table 1). The
underline is a single line of Rll for the CRT 8021 and a single line on R8 for the
CRT 8021-003.
When this input is low and RETBL = 0, data into the Attribute Logic is presented
directly to the shift register parallel inputs. When reverse video is high data into the
Attribute Logic is inverted and then presented to the shift register parallel inputs.
This operation reverses the data and field video. See table 1.
When this input is high, the parallel inputs to the shift register are all set low, providing a blank character line segment. Character blank will override blink. Theoperation
of Character Blank is modified by the Reverse Video input. See table 1.
This input is used as the clock input for the two on-chip blink rate dividers.
The cursor blink rate (50/50 duty cycle) will be twice the character blink rate
(75/25 duty cycle).
When this input is high and RETBL = 0 and CHABL = 0, the character will blink at
the character blink rate. Blinking is accomplished by blanking the character
block with the internal Character Blink clock. The character blink rate is 1.875 Hz
when V SYNC = 60 Hz.
These 2 inputs define the three modes of operation of the CRT 8002 as follows:
Illin_~!l!ptfics Mode-In this mode A0-A2, (A3-A7 = X) will be loaded into the thin
graphic logic along with the row addresses. This logic will define the segments
of a graphic entity as defined in figure 6.

MSl

MS0

1

0

Thin Graphics

MODE

0
0

1
0

Character Mode
Wide Graphics

27

CURSOR

Cursor

I

28

RETBL

Retrace Blank

I

Character Mode-In this mode the inputs A0-A7 go directly from the character latch
into the sh ilt register via the attribute logic. Thus the user may define external character fonts or graphic entities in an external PROM, ROM or RAM. See figure 3.
Wide Grap-hics Mode-In this mode the inputs A0-A7 will define a graphic entity as
described in figure5; Each line of the graphic entity is determined bythewidegraphic
logic in conjunction with the row inputs R0 to R3. In this mode each segment of the
entity is defined by one of the bits of the 8 bit word. Therefore, the 8 bits can defineany
1 of the 256 possible graphic entities. These entities can butt up against each other to
form a contiguous pattern orcan be interspaced with alphanumeric characters. Each
of the entities occupies the space of 1 character block and thus requires 1
byte of memory.
These 3 modes can be intermixed on a per character basis.
When this input is enabled the cursor will be activated. The cursor will be a blinking(at
3.75 Hz when V SYNC =60 Hz) reversevideoblock.lh this mode the Character Block is
set to reverse video at the cursor blink rate. The Character Block will alternate between
normal video and reverse video.
When this input is latched high, the shift register parallel inputs are unconditionally
cleared to all zeros and loaded into the shilt register on the next Load/SFiTii pulse. This
blanks the video, independent of all attributes, during horizontal and vertical retracetime.

358

TABLE 1
CURSOR
X
0
0

RETBL
1
0
0

REVID
X
0
0

CHABL
X
0
0

UNDLN'
X
0
1

0
0
0

0
1
1

1
0
0

X
0
1

0
0
0

FUNCTION
(S.R.)All
(S.R.)All
(S.R.)'
(S.R.) All others
(S.R.)All
(S.R.) All
(s.R.)'
(S.R.) All others
(S.R.) All

"0"
D
"1"
D

"0"

5

"0"

5

0
1
1
X
"1"
0
0
0
0
0
Blink" REVID Block
1
Blink" REVID Block
0
0
0
Blink" REVID Block
0
0
1
X
{ Al(",." N"m.1 V'doo/REVID
Blink" REVID Block
0
1
0
0
At Cursor Blink Rate
1
Blink" REVID Block
0
1
0
1
1
Blink" REVID Block
0
X
'At Selected Row Decode
"At Cursor Blink Rate
Note: If Character is Blinking at Character Rate, Cursor will change it to Cursor Blink Rate

FIGURE 2
TYPICAL CHARACTER MODE BLOCK FORMATS

ROWS R3 R2 R1 R(J

CRT 8021
(ALL ZEROS) __ 0 0 0 0 0 0 0 0 0 100000000 10 0 0 0 0 0 0 0 :0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 01 0 0 0 0 0 0 0 o 10 0 0 0 0 0 0 oI0 0 0 0 0 0 0 o 1I 0 0 0 0 0 0 0 010 0 0 0 0 0 0 010 0 0 0 0 0 0 010 0 0 0 0 0 0 -

r--------------,

TTT:TrT =
o

{ALL ZEROS} { :

o

0
0

0
0

0
0

0
0

0
0

0
0

0
0

C7 C6 C5 C4 C3 C2 C1 Cel

-

-

R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15

-

-

-

\L-

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

-

COLUMN 7 IS SHIFTED OUT FIRST

CRT 8021-003
0 0 0 0 0 0 0 0
0 1 0 0 0 0 01 0 0
o : 0 0 0 0 0: 0 0
010 0 0 0 0 0 0
0 1 0 0 0 001 0 0
010 0 0 001 0 0
o : 0 0 0 0 010 0
o LQ __O__ Q._Q __O_J 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
C7 C6 C5 C4 C3 C2 C1 Cil

r-----------,

I

EXTENDED ZEROS (BACK
FILL) FOR INTERCHARACTER
SPACING (NUMBER
CONTROLLED BY LD/SH,
VDCTIMING)

Note: Dotted line shows typical character display area.

FIGURE 3
CHARACTER MODE
MS0 = 1 MS1= 0
C7
RD-R15

I A71

C6

C5

A61 A5

C3

C4

I A41

C2

C1

A31 A21 A1

C0

BF

I All I A71

BF = back fill

359
~--~

.-~~------------

BF

...

A71

...

I

FIGURE 4. TYPICAL VIDEO OUTPUT-CHARACTER MODE
VDC

1----1----

1
r--I
'900T1
ISDcifl
LD/SH ----.J
IL-____~--------..JLf~~~ l~~~.Li____________..iI£&!:.~L_lf!§b.~

VIDEO DATA
8 DOT FIELD
VIDEO DATA
9 DOT FIELD

FIGURE 5
WIDE GRAPHICS MODE
MS0= 0 MS1 = 0
ROW ADDRESS

0000

I

3UNES·

5 BITS"

I

N BITS H

A7

I

CRT 8021

A3

CRT 8021-003

3UNES

C7 C6 C5 C4 C3 C2 C1 elf

3UNES
3UNES

RlJ
R,

RlJ
R,

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7404

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74160
DOT
COUNTER
(+N)
CP

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CARRY

I

CHARACTER CLOCK

DCC
S

BI-DIRECTIONAL DATA BUS

7404

CHIP SELECT

PAGE

~

DB0-7

V SYNC

A0-3

C SYNC

4

ADDRESS BUS

VIDEO DOTCLOCK

H SYNC

CS

DATA STROBE

VTAC
CRT 5027

BL

-I

o

VERT. SYNC

o

:n
-I

COMPOSITE
SYNC

s:

BLANKING

:::;

oz
o

VI

OS

MICROPROCESSOR

n

ADDRESS BUS
CONTROL BUS

~

r;-i;
ASCii
DATA

~t ADDRESS
L-

f---->-

.t>
L RAM
& ROM
(FOR "PI

W1Dfi

"2-PORT RAM
1Kx8 TO 4KxB
CHARACTER
FRAME
BUFFER

RG-3
4

rTl
I

CHARACTER
ROM

I

VII;lEO DATA

S

J

:xl

I
VAC
CRT 8021

VIDEO DOT
CLOCK

7

c

RASTER SCAN COUNTER

1

U:!J

CRV I------ 0

en

0

:xl

-n

r

1_

r-Ci

"OR 1 PORT RAM
WITH BI-DIRECT
PORT

I A

I

T

I ~ -.II
L.. __

ATTRIBUTES

»

Gl

RETRA<2§
BLANK.ING

SERIAL
OUTPUT

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CRT 9006-135
CRT 9006-83
J1PC FAMilY

Single Row Buffer
SRB
PIN CONFIGURATION

FEATURES:

o Low Cost Solution to CRT Memory Contention Problem
o Provides Enhanced Processor Throughput for CRT
Display Systems
o Provides 8 Bit Wide Variable Length Serial Memory
o Permits Active Video on All Scan Lines of Data Row
o Dynamically Variable Number of Characters per Data Row... 64,80, 132, ... up to a Maximum of 135
o Cascadable for Data Rows Greater than 135 Characters
o Stackable for Invisible Attributes or Character
Widths of Greater than 8 Bits
o Three-State Outputs
o 3.3MHz Typical Read/Write Data Rate
o Static Operation
o Compatible with SMC CRT 5037, CRT 9007, and other
CRT Controllers
024 Pin Dual In Line Package
0+5 Volt Only Power Supply
TTL Compatible Inputs and Outputs
Available in 135 Byte Maximum Length (CRT 9006-135)
or 83 Byte Maximum Length (CRT 9006-83)

DOUT3

GND

DOUT2

DOUT4

DOUT1

DOUT5

DOUT0

DOUT6

ClK

DOUT7

WREN

6E

ct:RCNT

OF

CKEN

DIN?

DIN0

DIN6

DIN1

DIN5

DIN2

DIN4

DIN3

+5V
Package: 24-pin D.I.P.

APPLICATIONS:

o CRT Data Row Buffer
o Block-Oriented Buffer
o Printer Buffer
o Synchronous Communications Buffer
o Floppy Disk Sector Buffer

o
o

GENERAL DESCRIPTION
The SMC Single Row Buffer (SRB) provides a low cost solution to memory contention between the system processor and
CRT controller in video display systems.
The SRB is a RAM-based buffer which is loaded with character
data from system memory during the first scan line of each
data row. While data is being written into the RAM it is also
being output through the multiplexer onto the Data Ouput

Cl'

(DOUT) Lines. During subsequent scan lines in the data row,
the system will disable Write Enable (WREN) and cause data
to be read out from the internal RAM for CRT screen refresh,
thereby releasing the system memory for processor access
for the remaining N-1 scan lines where N is the number of
scan lines per data row. The SRB enhances processor throughput and permits a flicker-free display of data.

o.

ADDl

CKEN
ADDRESS

COUNTER

:
I

I

I

!
AODO

3-STATE

OCTAL
2 TO 1
MU'

VII'Am

, T
~~~~NA
U C
"

363

0,
U A
T T

8

>-------"'.

'c r-----v
~ H

U
DOUT7-(l

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

NAME

SYMBOL

1-4

DATA OUTPUTS

DOUT3-DOUT0
ClK

5

CLOCK

6

WRITE ENABLE

7

CLEAR COUNTER

8

CLOCK ENABLE

9-12
13
14-17

FUNCTION

DATA INPUTS
POWER SUPPLY
DATA INPUTS

Data Outputs from the internal output latch.
Character clock. The negative-going edge of ClK clocks the
latches. When CKEN (pin 8) is high, ClK will increment the
address counter.

WREN

When WREN is low, data from the input latch is transferred directly
to the output latch and simultaneously written into sequential
locations in the RAM.

ClRCNT

A negative transition on ClRCNT clears the RAM addresscounter.
ClRCNT is normally asserted low near the beginning of each
scan line.

CKEN

When CKEN is high, ClK will clock the address counter. The
combination of CKEN high and WREN low will allow the writing
of data into the RAM.

DINIIJ-DIN3

Data Inputs from system memory.
+5 Volt supply.

Vee
DIN4-DIN7

Data Inputs from system memory.

;8

OVERFLOW FLAG

OF

This output goes high when the RAM address counter reaches its
maximum count. If cascaded operation of multiple CRT9006's is
desired for more than 135 bytes, OF may be used to drive the
CKEN input of the second row buffer chip.

19

OUTPUT ENABLE

OE

When OE is low, the data outputs DOUTIIJ-DOUT7 are enabled.
When OE is high, DOUT0-DOUT7 present a high impedance
state.

20-23
24

DATA OUTPUTS
GROUND

DOUT7-DOUT4
GND

Data Outputs from the internal output latch.
Ground.

OPERATION
For CRT operation, the Write Enable (WREN) signal is
made active for the duration of the top scan line of each
data row. Clear Counter (ClRCNT) typically occurs at
the beginning of each scan line (HSYNC may be used as
input to ClRCNT). Data is continually clocked into the
input latch by ClK. When Clock Enable (CKEN) occurs,
the data in the input latch (Write Data) is written into the
first location of RAM. At the negative-going edge of the
next clock, the address counter is incremented, the next
input data is latched into the input latch, and the new data
is then written into the RAM. loading the RAM continues
until one clock after CKEN goes inactive or until the

RAM has been fully loaded (135 bytes). While data is
being written into the RAM, it is also being output through
the multiplexer onto the Data Output (DOUT) lines. Each
byte is loaded into the output latch one clock time later
than it is written into the RAM. Output of the data during
the first scan line permits the Video Display Controller
(such as the CRT 8002) to display video on the first scan
line. During subsequent scan lines in the data row, thesystem will disable Write Enable (WREN) andcausedata to be
read out from the internal RAM, thereby freeing the system memory for processor access for the remaining N-1
scan lines where N is the number of scan lines per data row.
364

----~

-~-~----

. .----~-.---

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range .................................................................... 0° C to + 70° C
Storage Temperature Range ..................................................................... -55° C to + 150° C
Lead Temperature (soldering, 10 sec.) .................................................................... +325° C
Positive Voltage on any Pin, with respect to ground ......................................................... +8.0V
Negative Voltage on any Pin, with respect to ground ......................................•................... -0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.

ELECTRICAL CHARACTERISTICS (TA = 0° C to 70° C, Vcc = +5 ±5%, unless otherwise noted)
PARAMETER

MIN

TYP

MAX

UNITS

0.8

V
V

0.4
10

V
V
JlA

10
10

JlA
JlA

45
15

pF
pF

115
100

mA
mA

COMMENTS

DC CHARACTERISTICS
Input Voltage Levels
Low Level VIL
High Level VIH
Output Voltage Levels
Low Level VOL
High Level VOH
Input Current
Leakage, IlL
Output '1' Leakage
Output '0' Leakage
(Off State)
Input Capacitance
CLK
All other inputs
Power Supply Current
Icc (SRB-135)
Icc (SRB-83)

2.0

2.4

30
10

IOL=2mA
IOH = -100JlA
0:::; VIN:::; Vcc

I

AC CHARACTERISTICS

Icy
(SRB135)
(SRB83)
tCKL
(SRB135)
(SRB83)
tCKH
(SRB135)
(SRB83)
lcKR
(SRB135)
(SRB83)
IcKF
(SRB135)
(SRB83)
tDSET
tDHOLD
tENCKP
tENCKN
(SRB135)
(SRB83)
ENHOLD
WRCKN
(SRB135)
(SRB83)
WENHLD

DOUT
TSON
TSOFF
OFON
CLRS
(SRB135)
(SRB83)
CLRH

300
400

250
330

240
320

190
250

ns
ns
DC
DC

ns
ns

5000
5000

ns
ns

10
10

ns
ns

tCKH = 28ns
IcKH = 34ns

10
10

tCKL =240ns
tCLK = 320ns

65
5
0

ns
ns
ns
ns
ns

100
125
0

ns
ns
ns

100
125
0

ns
ns
ns
ns
ns
ns
ns

28
34

175
175
175
175
100
125
0

ns
ns
ns
365

CL=50pF

CL=30pF

FIGURE 1: AC CHARACTERISTICS

ClK

IENHOLD

CKEN

i5E

__________

~-----------J

OF __- , , -______~-------'

ClRCNT

___J=--Ioc,,t---

, - - - - - - - -_ _

FIGURE 2: SINGLE ROW BUFFER READ TIMING
ClK

~~A~ ~?~~T~EE CHAR) ==X:AgD~D~R!iM~A5X>C::BH02::::=><=J!H:!:1=>C:::::EH![2=>C:::::EH@:3=>C:)
WArn
CKEN

CLRCNT
ADDRESS GOUNTER

(INTERNAL)

Notes. N = 134 FOR CRT9006-135
N 82 FOR GRT9006-83
teLR = 1 elK PERIOD (min)

=

~~¢~R~~l~

Ul7

ONE

! 1

i(~7n~)-y

~ j

I"',:'
~

~1/711/
ADDRGl

___________

n _ n __

\, _____________ _

~~
ADDR1

ADDR2

AOOR N

ADDR N+

(LAST AODR)

====><________

-"R"DO"--______~

~

Doun-o IZZZZZ1ZZZZZZZZ~

t=x DATA N-1X DATAr-~
{LAST DATA

~~

OF

FIGURE 3: SINGLE ROW BUFFER WRITE TIMING

DIN7-Cl ==:::>C==XJ:D§ATj'iAijoDOD2tA\j'TAITlX]D2tAITTAIT2X]D2tA\j'TAiQ:3~
~ ~~>-'O~N~E~--,----------------------------~I ~l--_{L{-----------------------------CKEN

i- (~1~) {-------------------------------l!

<-l---.c-,_--_-_-_-_--_-_-_--_-_--_---__

~~ligR~'ft) ==i>C==::>C==X~W!lD!5.i.CX~WQDI:':::>C~WQD2CXJ ~

!-tCLR-:

A~~:~:: ~~11117DlJlJll/l//1lII,
COUNTER
(INTERNAL)

?v77711Zl1Z1ZZ1l7Z/l,

7VTlTTliitiiIiiit~ODR~ ~ ~
(LAST AD DR)

Doun-o WfllllllJmil£)- THREE ~
~

D

DATA N-l X DATA N ) ~HR~:
(LAST DATA)

TA

Notes: N = 134 FOR CRT9006-135
N = 82 FOR CRT90Q6-83
teLR = 1 elK PERIOD (min.)

OF--------------------------------------~

366
--------

- - -

~--~--

PROCESSOR
HLDAj--

JiP/JiC

ADDR

A

A
~

~

HS}~

INT

T

RST

I

,oem,. oe, ••. ,

•

CRT CONTROLLER

CBLANK

•

VSI

Iv I

~II

Vl
Ol

V

-..j

B
U

S

ORB

VLT

'I-

z:;;
:::;t-

SL3 SL2
, SLl
, SL0CURS
,
,

I I I I I I II
A3

WREN

R2

RII CURSOR

~DIN7-0

DOUT7_0~1j"""~~
OE

VSYNC RETBL

LO/SHI-~

...

CRT
9006
SINGLE
ROW BUFFER

~

CqLKI

&

UIUI

z
ti):J
a:
u:
 DIN7-0

1516)273·3100 TWX'SlO'227-S898

~

~

P

'o'mJ

ROW BUFFER
B

DIN7-0

OF

r--

OE p--OV

CRT 9006-135

Circuit diagrams utilizing SMC products are included as a means of Illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

368

CRT9007A
CRT9007B
CRT9007C
IlPC FAMILY

CRT Video Processor and Controller
VPACTM
FEATURES

PIN CONFIGURATION

o Fully Programmable Display Format
o

o

o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o

Characters per Data Row (8-240)
Data Rows per Frame (2-256)
Raster Scans per Data Row (1-32)
Programmable Monitor Sync Format
Raster Scans/Frame (4-2048)
Front Porch-Horizontal (Negative or Positive)
-Vertical
Sync Width- Horizontal (1-128 Character Times)
- Vertical (2-256 Scan Lines)
Back Porch - Horizontal
-Vertical
Direct Outputs to CRT Monitor
Horizontal Sync
Vertical Sync
Composite Sync
Composite Blanking
Cursor Coincidence
Binary Addressing of Video Memory
Row-Table Driven or Sequential Video Addressing Modes
Programmable Status Row Position and Address Registers
Bidirectional Partial or Full Page Smooth Scroll
Attribute Assemble Mode
Double Height pat a Row Mode
Double Width Data Row Mode
Programmable DMA Burst Mode
Configurable with a Variety of Memory'Contention
Arrangements
Light Pen Register
Cursor Horizontal and Vertical Position Registers
Maskable Processor Interrupt Line
I nternal Status Register
Three-state Video Memory Address Bus
Partial or Full Page Blank Capability
Two Interlace Modes: Enhanced Video and Alternate
Scan Line

VA21
VA102
VA33
VAl14
VA125
VA46
VA137
VA5 B
VA69
VA710
VLT 11
\7512
RS 13
cGO< 14
ORB15
V0716
V0617
V0518
V0419
V0320

40GNO
39VA9
3BVAl
37VAB
36VAO
35 CBLANK
34 CURS
33 ACKffSC
32 CSYNCILPSTB
31 SLO/SLO
30 SLGISLl
29 WBENISL21CSi'NC
280MARISL3IVBLANK
271NT
26RST
25CS
24\1bo
23 VOl
22V02
21 +5V

o Ability to Delay Cursor and Blanking with respect to
Active Video
o Programmable for Horizontal Split Screen Applications
o Graphics Compatible
o Ability to Externally Sync each Raster Line, each Field
o Single +5 Volt Power Supply
o TTL Compatible on All Inputs and Outputs
o VT-100 Compatible
o RS-170 Interlaced Composite Sync Available

GENERAL DESCRIPTION

The CRT 9007 VPAC,M is a next generation Video processor!
controller-an MOS LSI integrated circuit which supports either
sequential or row-table driven memory addressing modes. As
indicated by the features above, the VPAC" provides the user
with a wide range of programmable features permitting low cost
implementation of high performance CRT systems. Its 14 address
lines can directly address up to 16K of video memory. This is
equivalent to eight pages of an 80 character by 24 line CRT display. Smooth or jump scroll operations may be performed anywhere within the addressable memory. In addition, status rows
can be defined anywhere on the screen.
In the sequential video addressing mode, a Table Start Register
points to the address of the first character of the first data row on
the screen. It can be easily changed to produce a scrolling effect
on the screen. By using this register in conjunction with two auxiliary address registers and two sequential break registers, a screen
roll can be produced with a stable status row held at either the first
or last data row position.

369

In the row-taqle driven video addressing mode, each row in the
video display is designated by its own address. This provides the
user with greater flexibility than sequential addressing since the
rows of characters are linked by pointers instead of residing in
sequential memory locations. Operations such as data row
insertion, deletion, and replication are easily accomplished by
manipulating pointers instead of entire lines. The row table itself
can be stored in memory in a linked list or in a contiguous format.
The VPAC" works with a variety of memory contention schemes
including operation with a Single Row Buffer such as the CRT 9006,
a Double Row Buffer such as the CRT 9212, or no buffer at all, in
which case character addresses are output during each displayable scan line.
User accessable internal registers provide such features as light
pen, interrupt enabling, cursor addressing, and VPAC,M status.
Ten of these registers are used for screen formatting with the ability to define over 200 characters per data row and up to 256 data
rows per frame. These 10 registers contain the "vital screen
parameters".

CURSOR, BLANK SKEW
CHAR/DATA ROW

DATAROWS,FRAME

HORJZOELAY
HORJZSYNCWJDTH

w

VD7 0

SCANLJNES,FRAME

<==:"'====--'::~======~=:::;-~::m!fuj~===--=~---;:=~==::;;:::==:;~==:::;~=--=:)

CURS

csvNc.

LPSTB
14 BIT ADDRESS BUS

TIMING

AND

CONTROL
~

_ _ _ _ _ _ _...J

CBLANK
INT
SL3IDMAR,VBLANK
SL2iWBEN'CSVNC
SL1/grn
SLeISLO

FiST

VLT

___~________-pmm~B____~
CCLK

FIGURE 1: CRT 9007 BLOCK DIAGRAM

DESCRIPTION OF PIN FUNCTIONS
PROCESSOR INTERFACE:
PINNa.
NAME
7,5,4,2,39, Video Address
37,10,9,8,6, 13·0
3,1,38,36

SYMBOL
VA13-VAO

16,17,18,19, Video Data 7-0
20, 22, 23,24

VD7-VDO

25

Chip strobe

CS

26

Reset

RST

27

Interrupt

INT

FUNCTION
These 14 signals are the binary address presented to the video memory by the CRT 9007.
The function depends onthe particular CRT 9007 mode of operation. VA13-6 are outputs
only. VA5-0 are bidirectionaL
-Double Row Buffer Configuration:
VA 13-0 are active outputs for the DMA operations and are in their high impedance state at
all othertimes ..
-Single Row Buffer Configuration:
.
VA 13-0 are active outilUtS during the first scan line of each data row and are in their high
impedance state at all other times,
-Repetitive Memory Addressin~ Configuration:
VA 13-0 are active outputs at a I times except during horizontal and vertical retrace at which
.
time they are in their high Impedance state.
If row table addressing is used for either single row buffer or repetitive memory addressing
modes, VA 13-0 are active outputs during·the horizontal retrace at each data row boundary to
allow the CRT 9007 to retrieve the row table address. For processor read/write operations
VA5-0 are inputs that select the appropriate internal register.
Bidirectional video data bus: during processor Readlwrite operations data is transferred via
VD7-VDO when chip strobe (CS) is active. These lineS are in their hillh impedance state
when CS is inactive. During CRT 9007 DMA operations, data from video memory is input via
VD7-VDO when a new row table address is being retrieved or when the attribute latch is being
updated in the attribute assemble mode. VD7-VDO are outputs when the external row buffer
is updated with a new attribute in the attribute assemble mode.
Input; this signal when active low, allows the processor to read or write internal CRT 9007
registers. When reading from an internal CRT 9007 register, the chip strobe (CS) enables the
output drivers. When writing to an internal CRT 9007 register, the trailing edge of this signal
latches the incoming data. Figure 2 shows all processor read/write timing.
Input; this active low sigr)g/Jiuts the CRT 9007 into a known, inactive state and insures
that the horizontal sync (HS) output is inactive. Activating this Input has the same effect as a
RESET command. After initialization, a START command causes normal CRT 9007 operation. See processor addressable registers section, Register 16 for the reset state definition.
Output; an interrupt to the processor from the CRT 9007 occurs when this signal is active
high. The interrupt returns to its inactive low state when the status register is read.

370

DESCRIPTION OF PIN FUNCTIONS CONT'D
CRT INTERFACE:

PIN NO.
11

NAME
Visible Line Time

SYMBOL
VLT

12

Vertical Sync

VS

13

Horizontal Sync

HS

14

Character Clock

CCLK

15

Data Row
Boundary

34

Cursor

35

Composite Blank

ORB

CURS

CBLANK

FUNCTION
Output; this signal is active high during all visible scan lines and during the horizontal trace
times at vertical retrace. This signal can be used to gate the character clock (CCLK) when
supplying data to a character generator from a single or double row buffer.
Open drain output; this signal determines the vertical position of displayed text by initiating a
vertical retrace. Its position and pulse width are user programmable. The open drain allows
the vertical frame rate to be synchronized to the line frequency when using monitors with DC
coupled vertical amplifiers. If the VS output is pulled active low externally before the CRT
9007 itself initiates a vertical synwhe CRT 9007 will start its own vertical sync at the next
leading edge of horizontal sync (HS).
O~en drain output; this signal determines the horizontal position of displayed text by initiating
a orizontal retrace. Its position and pulse width are user programmable. During hardware
and software reset, this signal is inactive high. The open drain allows the horizontal scan rate
to be synchronized to an external source. If the HS output is pulled low externally before the
CRT 9007 itself initiates a horizontal sync, the CRT 9007 will start its own horizontal sync on
the next character clock (CCLK).
InRut; this signal defines the character rate of the screen and is used by the CRT 9007 for
al internal timing. A minimum high voltage of 4.3V must be maintained for proper
chip operation.
Output: this signal is active low for one full scan line (from VLT trailing edge to VLT trailing
edge) at the top scan line of each new data row. This signal can be used to swap buffers in
the double row buffer mode. It indicates the particular horizontal retrace time that the CRT
9007 outputs addresses (VA 13·VAO) for single row buffer operation. There will always
be one extra ORB signal which will become active during the first scan line of the vertical
retrace interval.
Output; this signal marks the cursor position on the screen as specified by the horizontal and
vertical cursor registers. The signal is active for one character time at the particular character
position for all scan lines within the data row. For double height or width characters, this sig'
nal is active for 2 consecutive CCLK's in every scan line within the data row. For double
height characters, this signal can be programmed to be active at the proper position for 2
consecutive data rows.
CURS is also used to signal either a double height or double width data row by becoming
active during the horizontal retrace (CBLANK active) prior to a double height or double width
scan line. The time of activation and deactivation is a function of the addressing mode, buffer
configuration and the scan line number. See section of Double height/width for details.
Output. This signal when active high, indicates that a retrace (either horizontal or vertical) will
be performed. The signal remains active for the entire retrace interval as programmed. It is
used to blank the video to a CRT.

USER SELECTABLE PINS: (see Tables 4 and 5)

PIN NO.
28,29,30,31

NAME
Scan Line 3·
Scan Line 0

SYMBOL
SL3·SLO

28

Direct Memory
Access Request

DMAR

28
29

VBLANK
WBEN

29or32

Vertical Blank
Write Buffer
Enable
Composite Sync

30

Scan Line Gate

SLG

31

Scan Line Data

SLD

32

Light Pen Strobe

LPSTB

33

Acknowledge

ACK

33

Three State
Control

TSC

CSYNC

FUNCTION
Output; these 4 signals are the direct scan line counter outputs, in binary form, that indicate
to the character generator the current scan line. These signals continue to be updated
during the vertical retrace interval. SL3 and SL0 are the most and least significant
bits respectively.
Output; this signal is the DMA request issued by the CRT 9007. It will only become active if
the acknowledge (ACK) input is inactive. It remains active high throughout the entire
DMA operation.
Output; this signal is active high only during the vertical retrace period.
Output; this active hi~h signal is used to gate the clock feeding the write buffer in a double
row buffer configuration.
Output; this signal provides a true RS·170 composite sync waveform with equalization pulses
and vertical serrations in both interlace and noninterlace formats. Figure 3 illustrates the
CSYNC output in both interlaced and noninterlaced formats.
Output; this active low signal is used as a clock gate. It captures the correct 5 or 6 CCLK's
and, in conjunction with SLD (pin 31), allows scan line information to be loaded serially into
an external shift register.
Output; this signal allows one to load an external shift register with the current scan 1i0!!.count. The count is presented least significant to most significant bit during the 5 or 6 CCLK's
framed by SLG. With this form of scan line representation, it is possible to define up to 32
scan lines per data row.
The external shift register must be at least 5 bits in length. Even though 6 shifts can occur
one should on~ use the 5 last bits shifted to define the scan line count. The extra shift occurs
in interlace or ouble height character mode to allow the scan line count to be adjusted to its
proper value. Figures 4 and 5 illustrate the serial scan line timing.
Input; this signal strobes the current row/column position into the light pen register at its posi·
tive transition.
Input; this active high signal acknowledges a DMA request. It indicates that the processor
bus has entered its high impedance state and the CRT 9007 may access video memory. It is
not recommended to deactivate this signal during a CRT 9007 DMA cycle because the CRT
9007 will not shut down in a predictable amount of time.
Input; this signal, when active low, places VA13·VA0 in their high impedance state.

371

OPERATION MODES

Single Row Buffer Operation
The CRT 9007 configured with a CRT 9006 Single Row
Buffer is shown in figure 6. The use of the CRT 9006 Single
Row Buffer requires that the buffer be loaded at the video
painting rate during the top scan line of each data row. However, after the CRT 9006 is loaded, the CRT 9007 address
lines enter their high impedance state for the remaining N1 scan lines of the data row, thereby permitting full proces-

sor access to memory during these scan lines. The percentage of total memory cycles available to the processor
is approximately [(N-1 )/N] x 100 where N is the total number of scan lines per data row. For a typical system with 12
scan lines per data row this percentage is 92%. Figure 7
illustrates typical timing for the CRT 9007 used with the CRT
9006 Single Row Buffer.

--

INTR

PROCESSOR

/,P:IIC
ACK

ADOR

DMilRQ~

DATA

III

=

RSf T5V GND

VPAC'M

MEMORY

C BLANK

ROM
RAM

VIDEO RAM

f--

vs

,

,

};

CIs

CRT 9007

VA13-0

ADDRESS BUS

'NT

o

VOl-!)

L::

VLT

Sl3 SL2 SLl SUl

T

~

[

B
U

S

L'

R3

WREN CLRCNTCKEN elK

DOUT7-0

~

CRT 9006
SINGLE
ROW BUFFER
DIN 7-0

R

I

RB

0
A

A

nn

CURS

or

==u:;

~-

R2

Rl

R(l

r-

CURSOR VSYNC

F,ETBL
LD SH

ATTRIBUTES
CRT 8002
VDAC'

VDC

CHAAACTERiA TTRIBUTES

AHl

GENERATOR
VIDEO

-_.

f

CLOCK
GENERATOR

~-----~M

TO
ONiTOR

FIGURE 6: CRT 9007 CONFIGURATION WITH SINGLE ROW BUFFER

---,L-..l,-----___ ___ ...

HS

VLT

I~l---------""'L-L~_-~= =~_

~J

- .IL.._ _ _ _ _---lr-----------~l~\----------_.L-_ _ _ _ _-!

TSC

VA13·0

I~I

IMP~I;A~CE !

iil~jl

0 0:: 0

I~

:

I

:

5 CLOCKS

IF2x'Hl'

F

5 CLOCKS

C~6CKd

I

0 0; 0

CURS
I
,
(NO SKEW) ~-J--6RSL3-0

\

I~I-

~~m~I~1

'"" i mt:
I

I

t:

•n. . . . CURSOR AT

2XW
STABLE COUNT

5t
1

3 CLOCKS
I 5 CLOCKS
CHARACTER POSITION
IF 2XH OR
5 CLOCKS ,
2XW
'-----I

:----:1......

b---=-fl

l!-~--------..:.':..'-..;:.';;;:-r------------

u

II

STABLE COUNT

FIGURE 7: CRT 9007 SINGLE ROW BUFFER TIMING (32 CHARACTERS PER DATA ROW)

372

Double Row Buffer Operation

the delay between each DMAR-ACK sequence, via the DMA
CONTROL REGISTER (RA). If 8 DMA operations are
performed for each ACK received, 10 such DMAR-ACK
sequences must be performed to completely fill the write
buffer. The programmed delay allows the user to evenly
distribute the DMA operations so as not to hold up the processor for an excessive length of time. This feature also
permits other DMA devices to be used and allows the processor to respond to real time events. In addition, the user
has the ability to disable the CRT 9007 DMA mechanism.
Figure 9 illustrates typical timing for the CRT 9007 used with
the CRT 9212 Double Row Buffer.

Figure 8 shows the CRT 9007 used in conjunction with a
CRT 9212 Double Row Buffer. The Double Row Buffer has
a read buffer which is read at the painting rate of the CRT
during each scan line in the data row. While the read buffer
is being read and supplying data to the character generator
for the current displayed data row, the write buffer is being
loaded with the next data row to be displayed. This
arrangement allows for relaxed write timing to the write buffer
as it may be filled in the time it takes for N scan lines on the
CRT to be painted where N is the number of scan lines per
data row. Used in this configuration, the CRT 9007 takes
advantage of the relaxed write buffer timing by stealing
memory cycles from the processor to fill the write buffer
(Direct memory access operation). The CRT 9007 sends
the DMAR (DMA request) signal, awaits an ACK (acknowledge) signal and then drives out on VA13-VAO the address
at which the next video data resides. The CRT 9007 then
activates the WBEN (write buffer enable) signal to write the
data into the buffer. If for example there are 80 characters
per data row, the CRT 9007 performs 80 DMA operations.
The user has the ability to program the number of DMA cycles
performed during each DMAR-ACK sequence, as well as

Since the CRT 9212 Double Row Buffer has separate inputs
for read and write clocks (RCLK, WCLK), it is possible to
display proportional character widths (variable number of
dots per character) by reading out the buffer at a character
clock rate determined by the particular character. The writing of the buffer can be clocked from a different and constant character clock. Figure 10 illustrates the CRT 9007
used with two double row buffers and a CRT 9021 Video
Attributes Controller chip to provide proportional character
display.

INTR

PROCESSOR
/lPpC

ACK
OMARQ

ArJIlR

DATA

OMAR

MEMORY
ROM

ACK

I I !

RST

-5V

GND

'NT

T

VA13-Q

ADDRESS GUS

CRT 9007
VPAC'M

RAM

}

RO

VIDEO RAM

CBLANK

V07-"

-

'JS
WBEN DI'lB

VCT

SLO

A
B
U

IL
~

I"'"

1

.",c'"

L

'ccCFH9212

1

III

U(",,·

'"

LDISH

ATTRIBUTES

~

=JS

CRT8002
VDAC'~

A7-rJ

VDC

CHARACTERIATIRtBUTES
GENERATOR
VIDEO

FIGURE 8: CRT 9007 CONFIGURATION WITH DOUBLE ROW BUFFER

373

rlD~
I

I I

M

o

,N
T

o
R

I

R3 R2 R1 RD CURSOR VSYNC RETBL

'"''

DOUBLE
ROW BUFFER

CITK

CURS

,_ I
W,,43:'~
! II I
YI

~

T

5

SLG

o

CLOCK
GENERATOR

I

II
TO
MO NITOR

vcr~~________~r-----------~U~----------~~
DRB--'~

______~

______________________________________~

DMAR
ACK --U-~

-----~~~~~~~~~~----------_tlliWilillillilliWilliliiliWlli~~------------ti~~-------------------

VA13-0

WBEN

CURS

FIGURE 9: CRT 9007 DOUBLE ROW BUFFER TIMING (32 CHARACTERS PER DATA ROW)

INTR

I ADD~

PROCESSOR

MEMORY
ROM

RAM

ACKf--------,

DATA DMARQ11------,

il 1

~::::::AD;:;D::;;R~ES~S:::B=US~::::=~~I

VAno

CM'~

'"

:f------} ~~~NITOR

'"

CRT 9007-VPAC'"

~'--'"-'"n_----~~--------~----~

VIDEO RAM

I"

.. ___

SLG

BUFFER
CONTROLS

cCTi\

SLD

IY"'

SHIFT
REGISTER

L

DATA

BUS

~

----v

r--''---'''''''''C'''''&j(,l'''''~. A;~

CHA~~~TER

DIN; 0
CRT 9212 ODUTi·U

A~

I
SCAN LINE DATA

k

CHARACTER

f-::==~'!

WIDTH

~

I

CLOCK
~ GENERATOR

I

DOUBLE ROW BUFFER

CHAR

CRT 9212

CODE

~ DOUBLE ROW BUFFER

~

DIN7·0

~

A"i

0

CRT 9021
\DC~

~

noun 0 f----'C"-H"'AC;RA:;oC"-TE=:.R:...:A:.:.TT'-'R""B"'U"'TE"'S'-_-"J ATTFllllUTE~

SHLD~

VIOE-~ -&~-- 4 2 - - - - - - - - - - - 1

6 -€O>----- 6
-

7 -€O>----- 7::-

(0) NON·INTERLACE

--------5

4 _-_--_-_-_-_-_-_--_. 3

-------- 6
!--:".:.
_____ 7

6 __________ 7

---------- 5

Even
Odd Even
Odd
Field
Field Field
Field
Ib) ENHANCED
Ie) NORMAL VIDEO
VIDEO INTERLACE
INTERLACE

FIGURE 21: CRT 9007 INTERLACE MODES

382
- ..

-------_.

__._-

-

----

- - - - - - - _ .._ - - - - - - - - - - _ . _ - - -

TABLE START REGISTER (Re AND RD)

AUXILIARY ADDRESS REGISTER 1 (RE and RF)

This 16 bit write only register contains a 14 bit address which
is used in a variety of ways depenqing on the addressing
mode chosen; the 2 remaining bits define the addressing
mode. Register C contains the lower 8 bits of the 14 bit
address: The 6 least significant bits of register D contain
the upper 6 bits of the 14bit address. The 2 most significant
bits of register D define four addressing modes as follows:

This 16 bit write only register contains a 14 bit address. The
6 least significant bits of REGISTER F conta,in the upper
order6 bits of the 14 bit address and REGISTER E contains
the 8 lower order bits of the 14 bit address. When the current data row equals the value programmed in SEQUENTIAL BREAK REGISTER 1 (R1 0) the remainder of the screen
is addressed sequentially starting at the 14 bit address
specified in this register. This sequential break overrides
any row driven addressing mode used prior to the sequential break.
.

Register D bits 7, 6:
= 00; (Sequential addressing mode)-The CRT 9007
will address video memory in a sequential fashion
starting with the 14 bit address contained in REGISTER D bits 5-0 and REGISTER C bits 7-0. 2
sequential breaks are allowed as defined by
SEQUENTIAL BREAK 1 (R10) using AUXILIARY
ADDRESS REGISTER 1 (RE and RF) and
SEQUENTIAL BREAK 2 (R12) using AUXILIARY
ADDRESS REGISTER 2 (R13 and R14).
= 01; (Sequential roll addressing mode)-The CRT
9007 will ~ddress video memory in a sequential
fashion starting with the 14 bit address contained in
REGISTER D bits 5-0 and REGISTER C bits 7-0.
SEQUENTIAL BREAK REGISTER 1 and AUXilIARY ADDRESS REGISTER 1 can be used to cause
one sequential break as described in the sequential
addressing mode. A second break in the sequential
addressing can be defined by SEQUENTIAL BREAK
REGISTER 2 (R12) and AUXILIARY ADDRESS
REGISTER 2 (R13and R14) permitting upto 3separate sequentially addressed screens to be painted.
= 10; (Contiguous row table mode)-The CRT 9007
will address vid~o memory according to the contiguous row table format. The 14 address bits contained in REGISTER D bits 5-0 and REGISTER C
bits 7-0 define an address that points to the beginning of the contiguous row table.
= 11; (tinked list rowtable mode)-The CRT 9007 will
address video memory according to the linked list
row table format. The 14 address bits contained in
REGISTER D bits 5-0 and REGISTER C bits 7~0
define the address at which the second row table
entry and the first data row reside.

SEQUENTIAL BREAK REGISTER 1 (R10)
This 8 bit write only register defines the data row number in
which a new sequential video address begins as specified
by AUXILIARY ADDRESS REGISTER 1 (RE and RF). To
disable the use of this break, the register should be loaded
with a data row count greater than the number of display.
able data rows on the screen.

DATA ROW START REGISTER (R11)
This 8 bit write only register defines the first data row number at which a page blank or smooth scroll operation will
begin. Bit 6 of the CONTROL REGISTER determines if a
page blank or smooth scroll operation will occur.

DATA ROW END/SEQUENTIAL BREAK
REGISTER 2 (R12)
This 8 bit write only register has a dual function depending
on the addressing mode used. For row driven addressing
(contiguous or linked list as specified by the 2 most significant bits of the TABLE START REGISTER) this register

The 2 most significant bits of REGISTER F allow one to
attach double height and/or double width characteristics to
every data row in this sequentially addressed area in the
following way:
For Double row buffer or attribute assemble mode REGISTER F Bits 7, 6
= 00; single height single width
= 01; single height double width
= 10; even data rows are double height double width
top half odd data rows are df.!~ble height double
width bottom half
= 11; odd data rows are double height double width
top half even data rows are double height double width bottom half

For Single row buffer or repetitive memory addressing mode
REGISTER F Bits 7,6
= 00; single height single width
= 01; single height double width
= 10; odd data rows are double height double width
top half even data rows are double height doupie width bottom half
= 11; even data rows are double height double width
top half
odd data rows are double height double width
.
bottom half

defines the data row number which ends either a page blank
or smooth scroll operation. The row numerically one less
than the row defined by this register is the last data row on
which the page blank or smooth scroll will occur. To use the
page blank feature to blank a portion of the screen that
includes the last displayed data row, this register must be
programmed to zero. For sequential addressing, this register can cause a break in the sequential addressing at the
da,ta row number specified and a new sequential addressing sequence begins at the address contained in AUXllIARYADDRESS REGISTER 2.

AUXILIARY ADDRESS REGISTER 2 (R13 and R14)
This 16 bit write only register contains a 14 bit address. The
6 least signific13nt bits of REGISTER 14 contain the upper
order 6 bits of the 14 bit address and REGISTER 13 contains the 8 lower order bits of the 14 bit address. In the row
driven addressing mode, this register is automatically loaded
by the CRT 9007 with the current table address. The two
most significant bits of REGISTER 14 specify one of four
combinations of row attributes (for example double height

383

double width) on a row by row basis. Refer to the section
entitled Double Height/Double Width operation for the
meaning of these 2 bits. In the sequential addressing mode.
this register can be loaded by the processor with a 14 bit
address and a 2 bit row attributes field. The bit positions are
identical for the row driven addressing mode. When the
current data row equals the value programmed in DATA ROW
END/SEQUENTIAL BREAK REGISTER 2 (R12). the
remainder of the screen is addressed sequentially starting
at the location specified by the programmed 14 bit address.
The 2 most significant bits of register 14 allow one to attach
double height and or double width characteristics to every
data row in this sequentially addressed area. The bit definitions take on the same meaning as the 2 most significant
bits of AUXILIARY ADDRESS REGISTER 1 and affect the
display in an identical manner.

START COMMAND (R15)
After all vital screen parameters are loaded, a START command can be initiated by addressing this dummy register
location within the CRT 9007. A START command must be
issued after the DMA mechanism is enabled (DMA CONTROL REGISTER bit 7).

of a double height data row stand alone in Single Row Buffer
Mode by programming the scrolled data row as double height
top half and loading R17 with the proper value.

VERTICAL CURSOR REGISTER (R18 or R38)
This 8 bit read/write register specifies the data row in which
the cursor appears. To write into this register it is addressed
as R18 and to read from this register it is addressed as R38.

HORIZONTAL CURSOR REGISTER (R19 or R39)
This 8 bit read/write register specifies the character position in which the cursor appears. To write into this register
it is addressed as R19 and to read from this register it is
addressed as R39.
It should be noted that the vertical and horizontal cursor is
programmed in an X-Y format with respect to the screen
and not dependant upon a particular location in video
memory. The cursor will remain stationary during all scroll
operations.

INTERRUPT ENABLE REGISTER (R1A)
This 3 bit write only register allows each of the three CRT
9007 interrupt conditions to be individually enabled or disabled according to the following definition:
Bit 6 (Vertical retrace interrupt)-This bit, when set to a logic
one, will cause the CRT 9007 to activate the INT signal when
a vertical retrace (Le., the start of the vertical blanking interval)
begins.
Bit 5 (Light pen interrupt)-This bit, when set to a logic one,
will cause the CRT 9007 to activate the INT signal when the
LIGHT PEN REGISTER (R3B, R3C) captures an X-Y coordinate. This interrupt, which occurs at the beginning of vertical
retrace, reflects the occurrence of a LPSTB input on the
frame or field just painted. This interrupt need not be enabled when other CRT 9007 interrupt conditions are enabled
since the STATUS REGISTER (R3A) will flag the occurance of a light pen update and servicing qln be done off of
other interrupts.
Bit a (Frame timer)-This bit, when set to a logic one, allows
the CRT 9007 to activate the INT signal once every frame
orfield at a time when a potential smooth scroll update may
occur. In this way the user can use the frame timer interrupt
as both a real time clock and can service smooth scroll
updates and other frame oriented operations by using the
appropriate status bits. This interrupt will occur after the last
row table entry is read by the CRT 9007. In single row buffer
operation, this will occur one data row before the start of
vertical retrace. In double row buffer operation, this will occur
two data rows before the start of vertical retrace.

RESET COMMAND (R16)
The CRT 9007 can be reset via software by addressing this
dummy location. Activation of the RST input pin or initiating
this software command will effect the CRT 9007 in an identical manner. The reset state of the CRT 9007 is defined as
follows:
CRT 9007 outputs
Reset state
VA13-0
High impedance
VD7-0
High impedance
HS
High
VS
High
High
CBLANK
Low
CURS
VLT
Low
ORB
High
Low
INT
Pin28
Low
Low
Pin 29
Pin30
Low
Pin31
Low
Low
Pin32

SMOOTH SCROLL OFFSET REGISTER (R17)
This register is loaded with the scan line offset number to
allow a smooth scroll operation to occur. The offset register
causes the scan line counter output of the CRT 9007 to start
at the programmed value rather than zero for the data row
that starts the smooth scroll interval. The start is specified
in the DATA ROW START REGISTER (R11). Typically, this
register is updated every frame and it ranges from zero (no
offset) to a maximum of the programmed scan lines per data
row (maximum offset). For example, if 12 scan lines per data
row are programmed (scan line a to scan line 11) an offset
of zero will cause all unscrolled display. An offset of one will
cause a display starting at scan line 1 and ending at scan
line 11 (eleven scan lines total). An offset of eleven will cause
a display starting at scan line eleven.

STATl!S REGISTER (R3A)
Thi~ 5 bit register flags the various conditions that can

The next scan line will be zero, starting the subsequent data
row. To allow smooth scroll of double height rows, the programmed range of the register is from zero to twice the programmed scan lilles per data row. Whenever the offset
register if greater than the programmed scan lines per data
row, bit 7 of the register must be set to a logic 1 (offset overflow). It must be set to a logic zero at all other times. The 6
bit offset value occupies bits 6 through 1. Bit a must always
be programmed with a logic zero. By setting the offset overflow (bit 7) to a logic 1, it is possible to have the bottom half
384

potentially cause an interrupt regardless of whether the
corresponding condition is enabled for interrupt. In this way
some or all of the conditions can be reported to the processor via the STATUS REGISTER. If some of the conditions
are enabled for interrupt, the processor, in response to an
interrupt, simply has to read the STATUS REGISTER to
determine the cause of the interrupt. The bit definition of the
STATUS REGISTER is as follows:
Bit 7 (Interrupt Pending)-This bit will set when any other
status bit, having its corresponding interrupt enabled,
experiences a a to 1 transition. In this manner, when the
processor services a potential CRT 9007 interrupt, it only
has to test the interrupt pending bit to determine if the CRT
9007 caused the interrupt. If it did, the individual bits can
then be tested to determine the details of the CRT 9007
interrupt. Any noninterruptable status change (corresponding interrupt enable bit reset to a logic 0) will not be
reflected in the interrupt pending bit and must be polled by

the processor in order to provide service. The interrupt
pending bit is reset when the status register is read. All other
bits except Light Pen Update are reset to a logic a at the
end of the vertical retrace interval. The light pen update bit
is reset to a logic a when the HORIZONTAL LIGHT PEN
REGISTER is read.

Bit a (Frame timer occurred)-This bit becomes a logic 1
either one or two data rows before the start of vertical retrace.
Since this bit is set when the CRT has finished reading the
row table for the frame or field just painted, it permits row
table manipulation to start at the earliest possible time.

Bit 6 (Vertical Retrace)-A logic 1 indicates that a vertical
retrace interval has begun.

This 8 bit read only register contains the vertical coordinate
captured at the time the CRT 9007 received a light pen strobe
signal (LPSTB).

Bit 5 (Light Pen Update)-A logic 1 indicates that a new
coordinate has been strobed into the LIGHT PEN REGISTER.lt is reset to a logic zero when the HORIZONTAL LIGHT
PEN REGISTER is read. The light pen coordinates may have
to be modified via software depending on light pen characteristics.
Bit 2 (odd/even)-For a normal video interlaced display, this
bit is a logic 1 when the field about be painted is an odd field
and is a logic zero when the field about be painted is an
even field.

FIELD
ONE
INTERLACED

VERTICAL LIGHT PEN REGISTER (R3B)

HORIZONTAL LIGHT PEN REGISTER (R3e)
This 8 bit read only register contains the horizontal coordinate captured at the time the CRT 9007 received a light pen
strobe signal. When a coordinate is captured, the appropriate status bit is set and further transitions on LPSTB are
ignored until this register is read. The reading of this register will reset the light pen status bit in the STATUS REGISTER. The captured coordinate may have to be modified
in software to allow for light pen response.

I

HS
CSYNC

VS------------------------~------------IL--------------------

f.- 3 SCAN LINES BEFORE VS ~ PROG. VSYNC WIDTH ----j.- 3 SCAN LINES AFTER vs----i

FIELD

INTETR~~CED

I

HS

CSYNC

VS-----------------------5------------~--------------------

NON·
INTERLACED

I

CSY::

VS------------------------~------------~--------------------

FIGURE 3: TYPICAL SYNC WAVEFORMS FOR INTERLACED AND NON-INTERLACED MODES

CCLK
:

I"

I. .
5 CLOCKS

:

~I------------------------~I---

~I----------------------~I-----

I

I

V~~

VLTl

I

I

I

~1,,~-6-C-L-O-C-K-S--~~r___

I

5 CLOCKS . ,

I
I
I"

~I

5 CLOCKS

.:

I

SLD

I

SLD
FIGURE 5: SERIAL SCAN LINE TIMING: INTERLACE
OR DOUBLE HEIGHT DATA ROWS

FIGURE 4: SERIAL SCAN LINE TIMING: NON INTERLACE
.
OR SINGLE WIDTH CHARACTERS

385
------- - - - - - - - - - - - - - - -

I

MAXIMUM GUARANTEED RATINGS'
Operaling Temperalure Range. . . . . . .

r~o;~f:~~~fa~~~~U[;o~~~~~, ;6 sec)

. ........... 0' 10 + 70'C

.. ... .. ...

- 55'C 10.! 1~g:g

. . , + BV
. . ~ O.3V

Positive Voltage on any Pin, with respect to ground ".
Negative Voltage on any Pin, with respect to ground . .

·Stresses above those listed may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or at any other
DC ELECTRICAL CHARACTERISTICS TA

V1H2

PARAMETER
Inpul voltage
Low
High
High

VOL
VOH

Oulpul voltage
Low
High

V"

V1H1

condition above those indicated in the operational sections of this specification is
not implied.
NOTE: When powering this device from laboratory or system power supplies, it is
important that the Absolute Maximum Ratings not be exceeded or device failure
can result. Some power supplies exhibit voltage spikes or "glitches" on their
outputs when the AC power is switched on and off. In addition, voltage transients
on the AC power line may appear on the DC output. If this possibility exists it is
suggested that a clamp circuit be used.

O'C 10 + 70'C Vee ~ 50V +- 5%
MIN
TYP

~

MAX

UNITS

0.8

V
V
V

~UIS excepl ceo<

004

V
V

10L ~ 1.6mA
10H ~ lOOI'A

10
50
-300

I'A
I'A
I'A

~,: ~I~~;~c;;.~uding ceo<

pF
pF

~UIS excepl CCIR
L inpul

2.0
4.3

204

Input leakage current
I"
1L2

Input capacitance

CIN1
CIN2

10
25

COMMENTS

L input; see note 4

Y'N ~ OV; lor CCIR

Power supply current
100

Icc

AC ELECTRICAL CHARACTERISTICS'; TA

~

PARAMETER
Clock
Clock period

lev

Clock low
Clock high

tCKl
tCKH
tCKR
tCKF

170

mA

MAX

UNITS

1200
1200
1200
1200
1200
1200

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

"-T"""~OO~

CRT9007A/B
CRT9007C
CRT9007A/B
CRT9007C
CRT9007A/B
CRT9007C
CRT9007A/B
CRT9007C
CRT9007 A } measured 10 Ihe 2.3V
CRT9007B or 0.5V level on
CRT9007C VAI3-VAO

185
185
240
185
240
240
185
240
300
310

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

CRT9007A
CRT9007B/C

140
189
85
400
410

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

115

ns

O°C 10 + 70°C, Vee ~ 5.0V ± 5%

MIN

TYP

290
330
400
270
300
400
90
150

Clock rise time

15
10

Clock fait lime

COMMENTS

CRT9007B
CRT9007C
CRT9007 A
CRT9007B
CRT9007C

or attribule assemble
all olher operalion
modes

measured from 0.8V 10 3.5V level
measured from 90% to 10% points

Oulpul Delay' :
150
240
150
240
150
200
150
200
100
115
125
500
185
200
185
200
185
240

ID1
ID2
I D,
I D,
25
25
25

IVA

tOSL
ID5
IDS

toSY
50
55
60
10

tvos
tVDH
tvoo
tSlG
tsLO
ID7
IDB

CRT9007A/B
CRT9007C
CRT9007A/B
CRT9007C
CRT9007A1B
CRT9007C
CRT9007 A} valid for loading auxiliary
CRT9007B address regisler 2 or
CRT9007C attribule lalch
CL ~ 50pF
CRT9007A/B
CRT9007C
CRT9007A/B
CRT9007C

cursor skew of zero
CRT9007A/B} cursor skew of one
CRT9007C
Ihrough five
CRT9007A/B
CRT9007C

Processor Read/Write2:
100
110
0
165
650
100
0

lAS
IAH
lew

tCSH
tpos
tpOH
tpOA

10

IpDO
tlAR

CRT9007A/B
CRT9007C
CRT9007A/B
CRT9007C

Miscellaneous Timing:
tATS

25

I RW

41cy

ns

measured from the OAV level of ACK or TSC falling
edge
measured from Ihe OAV level falling edge 10 OAV

tAKw
tAKS

50
50

ns
ns

see figure 24
see figure 24

level rising edge

NOTE: 1. Timing measured from Ihe 1.5V level of the rising edge of CCIR to Ihe
2AV (high) or OAV (low) vollage level of Ihe oulpul unless olherwise

noted.

2. Reference poinls are 2AV high and OAV low.
3. Loading on all outputs is 30 pF except where noted.
4. This level musl be reached before Ihe nexl falling edge of CCIR.

386

tCKF

<~~ ~

te"

r

I

tCKH

'--------'

I

I

too

,/
to'

"

VLT, WBEN

i

too

I

Ie,

"

jf

to.

){

VA13·0

t"

X

SL3·0

tDSL
CSYNC, DMAR
CBLANK

'l!,

Jf

to.

to,

l

"i
losy

t,oo

I
){

VD7·0

ATTRIBUTE OR

ROW TABLE DATA IN

~

r~~

~"~t"~-"

ATTRIBUTE

DATA OUT

SLG
ISlG

~

SLD

( +5V

tSLD

~390n

)[

CURS

tm

teo

To CCLK
Input

1

INT
EONLYI

,FIGURE 22: CRT 9007 TIMING PARAMETERS: OUTPUT SIGNALS

ACK,

74S04 or equivalent

FIGURE 25: RECOMMENDED CCLK
DRIVER CIRCUIT

TSC
HIGH IMPEDANCE

ACTIVE

VA13-0

---+--_--./

'1

tNT (failing edge only)

' VDC frequency
1e", VDC low
teKH VDC high
teKR VDC rise time
teKF VDC fall time
LD/SH
t CY2
tso
tH,
INPlJT SETUP AND HOLD
ts ,
tH,
MISCELLANEOUS TIMING
tpD
tDW

10.0
10.0
10
10

290
315
7
0

ns
ns
ns
ns

35
0

ns
ns
35

tCY2

1-These parameters are Preliminary.

396

ns

CRT 9021A; see note 1
CRT 9021B

Measured from 10% to 90% points
Measured from 90% to 10% points
CRT 9021 A; see note 1
CRT9021B

CL = 15 pf

VDC

_ 1,,__

_1,,, _

\

1112 - ,

tS2

ALL INPUTS
(EXCEPT VDC. LD SH)

"

V

\

LD SH

}.

>-

ICY:!

VDC

VIDEO OR
INTOUT

RETBL

CURSOR
(FOR DOUBLE WIDTH)

FIGURE 5: CRT 9021 INPUT/OUTPUT TIMING

X

SLD _ _ _ _.J\,._.I\_ _I'----"'-......J'--I~_:_I''--

FIGURE 6: SERIAL SCAN LINE MODE TIMING

Lnnnnn.r~1J

I

SL11SLG

,

:

I

1
I

~I-I- - - + - - - - - Hi I~~
i
I'
I~

I

I

,

:--:-7)

"

Ii

I

l~

,

Ir-

STABLEI~

SET SERIAL
SCAN LINE MODE

SET PARALLEL
SCAN L!NE MODE

FIGURE 7: SERIAL/PARALLEL SCAN LINE MODE SELECTION TIMING

397

-------------------------------------------

TABLE 2
WIDE GRAPHICS MASK PROGRAMMING OPTIONS
OPTION

CHOICES

Height of graphic block'
D7 and D3
D6and D2
D5 and D1
D4and DO

any scan
any scan
any scan
any scan

line(s)
line(s)
line(s)
line(s)

STANDARD CRT 9021
RO, R1, R2
R3, R4, R5
R6, R7, R8
R~R1~R11,R12,R13,R14,R15

Width of D7, D6, D5, D4"
Width of D3, D2, D1, DO"

any number of dots 0 to 8
C7, C6, C5, C4
any number of dots 0 to 8
C3, C2, C1, CO, BF
, Any graphic block pair can be removed by programming for zero scan lines.
" Total number of dots for both must be equal to the total dots per character with no overlap.

TABLE 3
THIN GRAPHICS MASK PROGRAMMING OPTIONS
CHOICES

STANDARD CRT 9021

Backfill
Horizontal position for

C1 or CO

CO

D2 and D3
D4
D5
Horizontal length for

any scan line(s) RO-R15
any scan line(s) RO-R15
any scan line(s) RO-R15

R5
RO
R11

OPTION

C7-C3
C3-BF

any continuous dots C7-CO, BF
D2'
all dots not covered by D2
D3'
Blanked dots for serrated horizontal lines
D2
D3
D4 and D5

any dot(s) C7-CO, BF
any dot(s) C7-CO, BF
any dot(s) C7-CO, BF

none
none
none

any dot(s) C7-CO, BF
any dot(s) C6-CO, BF
any dot(s) C7-CO

C3
BF
C7

Vertical position for
DO and D1
D6'
D7'
Vertical length for
DO
D1
D6
D7

any scan line(s)
all scan lines not used by DO
no choice; always RO-R15
no choice; always RO-R15
1-D7 must always come before D6 with no overlap; otherwise D6 is lost.
2-D2 and D3 must always overlap by one and only one dot.

RO
R6
RO
RO

to
to
to
to

R5
R15
R15
R15

TABLE 4
MISCELLANEOUS MASK PROGRAMMING OPTIONS
OPTION

CHOICES
C7 orCO

STANDARD CRT 9021

Backfill in character mode
Character blink rate
(division of VSYNC frequency)

8 to 60; divisible by 4
(7.5 Hz to 1 Hz)'

Cursor blink rate'

Twice the character
blink rate

32
(1.875 Hz)'
16
(3.75 Hz)'
R11

character underline position

any scan line(s) RO·R15

cursor underline 3

any scan line(s) RO·R15
underline
Blinking underline
Reverse video block
Blinking reverse video block

cursor format'
1
2
3
4

- Assumes VSYNC input frequency of 60 Hz.
- Valid only if the cursor is formatted to blink.
- Valid only if the cursor is formatted for underline.
- Valid for the parallel scan line mode only.

398

C7

not applicable
Blinking reverse video block

~

THREE
STATE
DRIVER
OE p...,

,.--,

L
A

~
/

V

I--

61--

J
H

~

OR
SL3-SLO

~

BUFFER

FROM
CRT
CONTROLLER

OR

CHARACTER
ROM

~

'" 7' ....
...)

~

VSYNC
RETBL
CURSOR

I

I

07-00

CRT 9021
VAC
~

DOUBLE ROW
BUFFER

..

-

A..

SYSTEM RAM

SINGLE ROW

OE

SL3-SLO
VSYNC
RETBL
CURSOR
MSO
MSI
BLINK
CHABL
INTIN
REVID
ATTEN
LD/SH
VDC

IIGENERATOR
CLOCK ~
FIGURE 8a: CRT 9021 SYSTEM CONFIGURATION IN PARALLEL
SCAN LINE MODE

r---

VIDEO
INTOUT

f-_

M

I
X
ER

L....--

VIDEO
TO MONITOR

r--

~
V

L
A

THREE
STATE
DRIVER

ICK
7
4
3
7
8

SYSTEM RAM

o

o

SINGLE ROW
BUFFER
OR
DOUBLE ROW
BUFFER

P+

OE

I+-

V

CHARACTER
ROM

V

"".

O7-DO

'"

CRT 9021
VAC

,/

r+D

OR
.j>.

OE

----

,6
-- ~
/
H
V

f-

T"
w

:::;;

:::

1i!l5g
"- is
U

t

SLG
SLD
VSYNC
RETBL
CURSOR

SLD

VSYNC
RETBL

CURSOR

I

I

I

CLOCK
GENERATOR

VIDEO
INTOUT

MSO
MSI
BLINK
CHABL
INTIN
REVID
ATTEN
LD/SH
VDC

I

BKC

;----.J

FORMAT

I

FIGURE 8b: CRT 9021 SYSTEM CONFIGURATION IN
SERIAL SCAN LINE MODE

BLC

I

VIDEO
TO MONITOR

CRT 9028

CRT 9128
PRELIMINARY

VTLC
Video Terminal Logic Controller
PIN CONFIGURATION

FEATURES

o BUilt-in High Frequency (4-14 MHz) Oscillator

o Built-in Video Shift Register
o Built-in Character Generator
OBi-Directional Smooth Scroll Capability
o Visual Attributes Include Reverse Video, Intensity
Control, Underline and Character Blank
o Separate HSYNC, VSYNC and VIDEO Outputs
o Composite Sync (RS 170 Compatible) Output
o Absolute (RAM address) Cursor Addressing
o MASK Programmable Video Parameters:

o
o
o

DA8
DA9
DA10
GND
XTAL2
XTALl
VIDEO
INTOUT
DWR
000
001
002
003
004
005
006
007
HSYNC
VSYNC
CSYN

Dots Per Character Block (6-8)
Raster Scans Per Daia Row (8-12)
Characters Per Data Row (32, 48, 64, 80)
Data Rows Per Page (8,10,12,16,20,24 or 25)
Horizontal Blanking (8- 64 Characters)
Horizontal Sync Front Porch (0-7 Characters)
Horizontal Sync Duration (1-64 Characters)
Horizontal Sync Polarity
Two Values of Vertical Blanking
Two Values of Vertical Sync Front Porch (0-63 Scan
Lines)
Two Values of Vertical Sync Duration (1-16 Scan
Lines)
Vertical Sync Polarity
Internal 128 Character 5x8 Dot Font
Character/Cursor Underline Position
Scan Rowand Column for Thin Graphics Entity
Segments
Scan Rows and Columns for Wide Graphics Entity
Elements
Software Enabled Non-Scrolling 25th Data Row Available with 25 Data .Row /Page Display
Non-Interlace Display Format
Separate Display Memory Bus Eliminates Contention

'-'
2
4
5

8

(
(
(
(
[

10
90
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

DA7
DA6
DA5
DA4
DA3
bA2
DAl
DAO
DB7
DB6
DB5
DB4
DB3
DB2
DBl
DBO
AID

..

..
vcc

CAT 9028

CAT 9128

Pin 23 AD
Pin 22 WR

Pin23 DS
Pin22 A/W

Problems

o Fill (Erase) Screen Capability
o Standard 8-bit Data Bus Microprocessor Interface

o Wide Graphics with Six Independently Addressable
Segments Per Character Space

o Thin Graphics with Four Independently Addressable
Segments Per Character Space

o Single + 5V Supply
o COPLAMOS® n-Channel Silicon Gate Technology
o TTL Compatible

GENERAL DESCRIPTION
similar microprocessors or microcomputers. The CRT 9128
regulates the data flow with a data strobe (OS) and read/
write (R/W) enable signals for use with the 6500, Z8'", 68000
and similar microprocessors or microcomputers.

The CRT 9028 VTLC and CRT 9128 VTLC are mask programmable 40 pin COPLAMOS® n-channel MOS/LSI Video
Display Controller Chips that combine video timing, video
attributes, alphanumeric and graphics generation, smooth
scroll and screen buffer interface functions.
The VTLC incorporates many of the features (previously
requiring a number of external components) required in
building a low cost yet versatile display interface. An internal mask programmable 128 character font provides for a
full ASCII character set. Wide graphics allow plotting and
graphing capabilities while thin graphics and visual attributes can make the display of forms straight-forward.
Two pinout configurations enhance the versatility of the
VTLC. The CRT 9028 controls data flow over the processor
system data bus through separate read (RD) and write (WR)
strobes for use with the 8085, 8051, Z80®, 8086, and
'Z80 is a registered trademark of Zilog Corporation.
Z8 is a trademark of Zilog Corporation.

401

The VTLC provides two independent data buses; one bus
that interfaces to the processor and one that interfaces to
the display memory. Data is transferred to the display memory from the processor through the VTLC eliminating contention problems and the need for a separate row buffer.
The VTLC has an internal crystal oscillator requiring only
an external crystal to operate. Masked constants for critical
video timing simplify programming, operation and improve
reliability. A separate non-scrolling status line (enabled or
disabled by the processor) is available for displaying system status.

I

CHARACTER
CLOCK

om

CLOCK

W

DISPLAY
MEMORY

_·sv

-

GND

FIGURE 1. VTLC FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

SYMBOL

I/O

3-1,40-33

DA10-0

0

NAME

DESCRIPTION

Display
Address

11 bit address bus to display memory

4

GND

Ground

Ground Connection

5,6

XTAL2,1

I

Crystal 2,1

External Crystal
An external TTL level clock may be used to drive XTAL 1 (in
which case XTAL2 is left floating).

7

VIDEO

0

Video Output

This output is a digital TTL waveform used to develop the
VIDEO and composite VIDEO signals to the monitor. The
polarity of this signal is: HIGH = BLACK
LOW = WHITE

8

INTOUT

0

Intensity
Output

This pin is the intensity level modification attribute bit (synchronized with the video data output).

9

DWR

0

Display
Write

Write strobe to display memory

17-10

007-0

I/O

Display
Data

8-bit bidirectional data bus to display memory

18

HSYNC

0

Horizontal
Sync

Horizontal sync signal to monitor

19

VSYNC

0

Vertical
Sync

Vertical sync signal to monitor

20

CSYNC

0

Composite
Sync

This output is used to generate an RS170 compatible composite VIDEO signal for output to a composite VIDEO monitor.

21

V"

5.0 V power connection

Power

CRT 9028
22

WR

I

Write Strobe

Causes data on the microprocessor data bus to be strobed into
theVTLC

23

RD

I

Read Strobe

Causes data from the VTLC to be strobed onto the microprocessor data bus

22

R/W

I

Read/Write
Select

Determines whether the processor is reading data from or writing data into the VTLC (high for read, low for write)

23

OS

I

Data Strobe

Causes data to be strobed into or out of the VTLC from the
microprocessor data bus depending on the state of the R/W
signal

24

A/D

I

Register
Select

The state. of this input pin will determine whether the data is
being read from, or written to, the address or status register, or
a data register.

32-25

DB7-0

I/O

Processor
Data Bus

8-bit bi-directional processor data bus

CRT9128

402

DESCRIPTION OF OPERATION*
THE VTLC INTERNAL REGISTERS

CHARACTER register. This bit is used to synchronize data
transfers between the processor and the VTLC. The VTLC
will set the DONE bit to a logic one after completing a byte
transfer command or a FILL operation. The DONE bit is set
to a logic zero by reading from, or writing to, the CHARACTER register. The processor must wait until the DONE
bit is 1 before attempting to change the CURSOR
ADDRESS, in order to write a character to, or read a character from, the CHARACTER register.

CRT 9028

Addressing of the internal VTLC data registers of the
CRT 9028 is accomplished through the use of the AID
select input qualified by the RD and WR strobes.
AID RD WR

0
0

1
0

0
1
0

0

REGISTER OPERATION
WRITE TO DATA REGISTER
READ DATA REGISTER
WRITE TO ADDRESS REGISTER
READ STATUS REGISTER

STATUS REGISTER
DB7

o
o

o
o
o
o

o
o

X

DONE

CRT 9128
Addressing of the internal VTLC data regJ?ters of!b.e CRT
9128 is accomplished through use of the AID and RIW select
inputs qualified by the OS strobe.
AID OS R/W

DB6 DB5 DB4 DB3 DB2 DB1 DBO

X

X

REGISTER OPERATION

To access one of the seven eight-bit registers, the processor must first load the Address Register with the threebit address of the selected data register. The next read or
write to a data register will then cause the data register
po.lDted to by the Address Register to be accessed. The Line
AID controls whether writing is occurring to the Address
Register or to a data register. When a read operation is performed, AID controls access to either the Status Register
or to the data register selected by the Address Register.

REGISTER DESCRIPTION
ADDRESS REGISTER

Writing a byte to the ADDRESS register will select the
specified register the next time the processor writes to or
reads the VTLC data registers. The data register addresses
are as follows:

FILADD REGISTER
X

ADDRESS

DA 10 DA9 DAB DA 7 DA6 DA5 DA4

TYPE

REGISTER

Write
Write
Write
Write
Write
Write
RDIWR
Write

CHIP RESET
TOSADD
CURLO
CURHI
FILADD
ATTDAT
CHARACTER
MODE REGISTER

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO

X
X
X
X
X
X
X
X

0
1
1
1
1
1
1
1

1
0
0
0
0
1
1
1

1
0
0
1
1
0
0
1

0
0
1

0
1
0
1
0

(X = don't care)
'NOTE: Chip Reset is required before starting operation.

X

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO

STATUS REGISTER
When reading the STATUS register, the DONE bit (DB7
of STATUS Register) will represent the current status of the

X
X
X
X
X
X
X
X

X

DATA REGISTERS
FILADD (Fill Address) This register contains the RAM
address of the character following the last
address to be filled. Writing to this register will
enable the VTLC "fill" circuitry. The FILL operation will then be triggered by the next processor
write to the CHARACTER register. The FILL
operation will write the character in the CHARACTER register to every location in display
memory starting with the address specified in
the CURLO and CURHI registers through the
location preceeding the address specified in the
FILADD register. The cursor position is not
changed after a FILL operation. Note that the
address bits DA3-DAO are internally forced to 0
forcing the FILADD address to be 00, 16, 32, etc.
to 1920. The CURLO and CURHI registers will
not be changed by this operation. Writing to the
CHARACTER register will cause the VTLC to
reset DB? of the STATUS register to "0". Bit 7
will be set to 1 after the VTLC has filled the last
memory location specified.

The contents of the seven processor programmable registers located in the upper left hand side of the Functional
Block Diagram of figure 1 indicate the memory locations
from which screen data is to be fetched and displayed as
well as the selected modes of display operation. These registers are addressed indirectly via the Address Register.

X
X
X
X
X
X
X
X

X

DONE = 1 signifies that external processor is allowed to
access cursor ADDRESS andlor
CHARACTER registers.
DONE = (i) signifies that external processor must wait
until VTLC completes transfer of data
between display memory and CHARACTER
register.

WRITE TO DATA REGISTER
READ DATA REGISTER
WRITE TO ADDRESS REGISTER
READ STATUS REGISTER

X
X
X
X
X
X
X
X

X

403

I

Changing the Attribute register will change the
attribute of every "tagged" character on the
screen. The functions of the remaining bits in the
ATTDAT register are not affected by the display
character's TAG bit.

TOSADD (Top of Screen Address) This register contains
the RAM address of the first character displayed
at the top of the video monitor screen. In addition, this register controls selection of either of
two mask programmable vertical scan rates.
TOSADD REGISTER
DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
TIM DA10 DA9 DAB DA? DA6 DA5 DA4
Note that address bits DA3-DAO are internally
forced to 0 forcing the first address at the beginning of each row to be 00, 16,32, etc. to 1920.
The most significant bit of this register (TIM)
is used to select between the two mask programmed sets of vertical retrace parameters
(scan A and scan B). This allows software
selection of, for example, 50/60 HZ.
TIM = 0 enable raster scan A (60 Hz)
TIM = 1 enable raster scan B (50 Hz)
CURLO

(Cursor Low) This register contains the eight
lower order address bits of the RAM cursor
address. All FILL screen and character transfer
operations begin at the memory location pointed
to by this address.

There are two display modes, "alphanumerics" and
"graphics". In the alphanumeric mode, visual attributes may
be selected by the TAG bit. In the graphics mode, a tagged
character will be a normal alphanumeric character. This
allows a screen to display a mix of graphic and alphanumeric characters or visually attributed alphanumeric characters. The display variations of the alphanumerics and
graphics modes are summarized by the following:
ATTDAT REGISTER
DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
DB?

MODE
SELECT

DB? = 1

DB? = 0

DB6

CURSOR
SUPPRESS

DB6 = 1

CURLO REGISTER
DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
DA? DA6 DA5 DA4 DA3 DA2 DA 1 DAO
CURHI

(Cursor High) This register contains the three
higher address bits of the RAM cursor address
(DA10, DA9, DAB). All FILL screen and character transfer operations begin at the memory
location pointed to by this address. In addition,
this register contains the Smooth Scroll Offset
Values SS3-SS0 which determine the number
of scan lines that the data is shifted on the
screen. The MSB of this register (SLE-status line
enable) is the enable for the non-scrolling status
line (this feature is available only on a part programmed for 25 data rows).

DB6 = 0

DB5

CURSOR
DISPLAY

DB5 = 1
DB5 = 0

CURHI REGISTER
DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
SLE SS3 SS2 SS1 SSO DA10 DA9 DAB
SLE = 1 enables non-scrolling 25th
status line
SLE = 0 disables and blanks nonscrolling status line
SS3-SS0 Smooth Scroll Offset Value
ATTDAT

(Attribute Data) This register specifies the visual attributes of the video data and the cursor
presentation. The visual attributes specified in
the ATTDAT register (DB3-DBO) are enabled or
disabled by a TAG bit that is appended to the
ASCII character written to the CHARACTER
register. Every character on the screen with its
TAG bit set is displayed with the same attribute.
404

DB4

SCREEN

DB4 = 1

DB4 = 0

enables graphics
mode display (No
attributes allowed)
enables alpha
mode display
inhibits VIDEO display at cursor time
by forcing the
VIDEO output to
background level
during cursor displaytime
enables VIDEO
display at cursor
time
Note: a blinking
cursor display can
be achieved by
toggling this bit
under processor
control.
enables underline
cursor display
enables block cursordisplay
Note: An underline
cursor in an underline character
attribute field will
be dashed.
for white screen
and black
characters
for black screen
and white
characters
Note: this is a
screen attribute
(versus character
attribute) bit and
sets the default
Video background
level.

DB3

CHARACTER DB3 = 1
SUPPRESS
DB3 = 0

to enable Video
suppress
to inhibit Video
suppress
This bit allows
character blinking
and blanking under
processor control

DB2

INTENSITY

DB2 = 1

allows the INTOUT
output pin to go
high for the charactertime
inhibits the
INTOUT output pin
from going high

I-

iD
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~

fn
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co
en



SCAN LINE 0

->

0

SCAN LINE 1

->

0

C7

SCAN LINE 2

->

0

SCAN LINE 3

->

0

SCAN LINE 4

->

0

SCAN LINES

->

0

SCAN LINE 6

->

0

SCAN LINE 7

->

0

SCAN LINE 8

->

0

SCAN LINE 9

->

0

SCAN LINE 10

->

SCAN LINE 11

->

will remain stationary at the bottom of the screen and will
not move up the screen when the remainder of the display
data is scrolled. Otherwise, VIDEO data on the status line
may be manipulated as though it were normal display data.
The smooth scroll offset will not function properly when the
status line is enabled. The memory address of the characters on the status line are always characters 1920-1999.
NOTE: If the part is programmed for 25 data rows an additional mask option must be specified which makes the 25th
data row either fixed (always displayed) or a status row
(enabled/disabled by the SLE bit).

CHIP RESET
The CRT 9028 and CRT 9128 Chip Reset requires two
steps. The system processor firstwrites the reset address
to the address register of the VTLC. The system processor
then writes a dummy character to the VTLC Data register.
Writing to the Data register resets the chip. The only state
affected by the reset function is the setting of the DONE bit
in the STATUS register.

ROM CHARACTER BLOCK FORMAT
C6
CS
C4
C3

o

o

o

o

C2

C1

co

o

o
o

o

o

0

o

o

o
o
o
o
o
o
o
o

o

MASK PROGRAMMABLE
CHARACTER BLOCK
(FONT)
SX8

0

o
o

o
o

o
o

o
o

0

o

o

o

o

o
o
o

0

0
0
0
0

o
o
o

Mask programmable options-The ROM character block format above shows the SX8 mask programmable character font
within the character cell as defined by dots C7 through CO and scan lines 0 through 11.
Dots/Character: 6 dots/character cell
7 dots/character cell
8 dots'character cell

= > C7 - C2 displayed
= > C7 - C1 displayed
= > C7 - CO displayed

Column dots CO and C1 will be the same as column dot C7 when more than 6 dots 'character cell are specified
when generating alpha-numerics.
NOTE: The maximum dot clock crystal frequency is dependent on the dots character programmed:
DOTS/CHARACTER

MAX XTAL FREQ
1O.S MHz max'
12.2S MHz max'
14.0 MHz max'

6 dots
7 dots
8 dots
*These values are preliminary

Scan Lines per Character:

8 scan
9 scan
10 scan
11 scan
12 scan

lines
lines
lines
lines
lines

character = Co
character = :'
character = "
character ='character = '.

SLO - SL7 displayed
SLO - SL8 displayed
SLO SL9 displayed
SLO· SL 10 displayed
SLO . SL 11 displayed

Thin and Wide Graphics: Dots mask programmed for vertical column C2 will be the same as backfill Columns 0 and 1
when generating wide and thin graphics.

407

MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range .......................................... '" .......................... O°C to + 70°C
Storage Temperature Range ..................................... , ................................... - 55°C to + 150°C
Lead Temperature (soldering, 10 sec.) ............................................................... + 325°C
posiiive Voltage on any Pin, with respect to ground ................................................. + B.OV
Negative Voltage on any Pin, with respect to ground ............ ; ................................... ~ O.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the devic~ at these or at any other condition above those indicated in the operational sections of ihis
specification is not implied.
NOTE: When powering this device from laboratory or sysiem power supplies, it is important that the Absolute Maximum Ratings not be .exceeded or device failure can result. Some power supplies exhibit vOltage spikes or "glitches"
on their outputs when the AC power is switched on and off. In addition, voltage transients on the AC power line may
appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
ELECTRIC~L CHARACTERISTICS (TA =O°C to 70°C, Vee =

+ 5V

± 5%, unless otherwise noted.)

PARAMETER
Address.Hold Time
tAHT
Output Hold From Address Change
tOH
Address Access Time
tAA
PROCESSOR TIMING
Address Read/Write Set-up
tARWS
'
Write Pulse Width
twpw
Write Hold Time
tWHT
Read Set-up Time
t RST
R~ad Data Valid
T Rov
Read Pulse Width
t~pw
Data Write Falling Set-up
10wFs
Data Write Rising Set-up
i owRs

MIN

TYP

MAX

UNIT

25

ns

15

ns

250

ns

160

ns

160

ns

15

ns

200

COMMENTS

ns

0

ns

2qO

ns

120

ns

160

ns

Crystal specification (Applies for 4-14 MHz):
Series Resonant
50 ohms max series resistance
1.5 pflyp parallel capacitance
Operation below 4 MHz requires external crystal oscillator

DA10·0

ADDRESS

ADDRESS

DWR

READ DATA
FROM RAM

007·000

VTLCINPUT
FROM RAM
NOTE: DISPLAY ADDRESS BUS DA10·DAO MUST NOT CHANGE WHILE DWR IS LOW

FIGURE 2. DISPLAY MEMORY TIMING

DB7·0
PROCESSOR WRITES
TOVTLC

(1) If set·up time is not met, screen may glitch when cursor or attribute
registers are changed during active video time.
(2) Minimum set·up time toensure valid data into VTLC internal registers.

FIGURE 3.

P~OCESSOR

409

TIMING.,;!

READ DATA
FROM RAM

VERTICAL
SYNC
I DURATION I

VERTICAL TIMING

I

VSYNC~
VSYNC

1<

>1

I

I

I

I+--

i (-----\\.. __I'--__--IIf-I_______,

DELAY

I
I

I

V BLANKING _ _ _ _ _...11

\

1/

I
I

I

r--

/1

I~I

I+- NUMBER OF BLANKED -+I

14-- ~Ys"I.~~~~; ~

SCAN LINES

DATA ROWS

HORIZONTAL
SYNC
DURATION

HORIZONTAL TIMING

~

I

I

I

HSYNC _
I+I
I
DELAY
I
I
I
I
HSYNC _ _ _ _--'I'----'t---....f-_ _--'-I _ _ _--IIf-I _______'

I

II

I
H BLANKING

II--~----------\

-------'~

r--

II
Ir---I

NUMBER OF ----.j

cJk~ZC"f~RS

I+-

~y~P~~~~;

----.;

CHARACTERS
NOTE: Video parameters above are mask programmable

FIGURE 4. VERTICAL AND HORIZONTAL SYNC TIMING

HSYNC~

n

VSYNC

I

n

I
I

I

I
I
I
I

I
I

-i-

H-----I
I--HI2-o.l
I

n

I
I

I
I
I
I
I

I

I

n

n

I
I
I
I

I

CSYNC
NCJTE: Delays between pulse edges and pulse width values may vary due to mask programmable features.
'H represents horizontal interval

HSYNC

~

HSYNC

Ji'---_ __

CSYNC

-1j d t<---

CSYNC

______~rl~_____
_______
~~d~r_--------

U

d = HSYN Delay -CSYN Delay

OUTSIDE OF VERTICAL
SYNC PULSE TIME

WITHIN VERTICAL SYNC
PULSE TIME

FIGURE 5. VIDEO SIGNAL TIMING

ro"7-0 XXXXXXXXX

xxxxxxxxxxxxxxxx

ASCII CHARACTER

PROCESSOR
BUS

~----------------~

PROCESSOR WRITES CHARACTER
VTLC CHARACTER REGISTER

(CAUSES DONE BIT RESET)

\'--____----'1

'DONE
(DB7 OF STATUS
REGISTER)

JDD7-0
DISPLAY
_ _ _- /
BUS

DISPLAY
CHARACTER

DISPLAY
CHARACTER

'--------1

~WR----------------------------;
DONE = 1 SIGNIFIES THAT PROCESSOR MAY ACCESS CHARACTER REGISTER
DONE = 0 SIGNIFIES THAT PROCESSOR MAY NOT ACCESS CHARACTER REGISTER

ASCII CHARACTER

VTLCWRITES
CHARACTER REGISTER
TO DISPLAY MEMORY

FIGURE 6. TYPICAL PROCESSOR TO DISPLAY MEMORY TRANSFER

410

TYPICAL DISPLAY TIMING
TIME:
DA10-0

DWR

.!II

DISPLAY MEMORY READ

READ AND WRITE DISPLAY MEMORY TIMING
TIME:
DA10-0

DWR

ll/

----------------~\
\

,~-------I
~

/

______ _'
HIGH FOR READ~ I
LOW FOR WRITE
II

!!I

VTLC WRITES/READS
TO/FROM DISPLAY MEMORY

,---------------------------~

.j:>.

.....

;ANKING

PROCESSOR WRITES/READS TO/FROM
CHARACTER REGISTER

--I hi:'

LL
17

CHARACTER

Ih

DI~P~AY

-: I

FILL DISPLAY MEMORY COMMAND
TIME:
DA10-0
DWR

,-----h~

PROCESSOR WRITES TO FILADD REGISTER
FOLLOWED BY WRITE TO CHARACTER REGISTER

,

H

~TO
LAST LOCATION

(
DONE
(DB7 OF STATUS
REGISTER)

~

~7

DD7-0

NOTE:

"N CHARACTERSIDATA ROW

FIGURE 7. VTLC DISPLAY MEMORY ACCESS TIMING

(LAST LOCATION
FILLED)

~1

m

APPENDIX-STANDARD PARTS-CRT 9028-000/CRT 9128-000
I. ROM CHARACTER BLOCK FORMAT:
COLUMN DOT
SCAN LINE

- .

a

SCAN LINE 1
SCAN LINE 2
SCAN LINE 3
SCAN LINE 4
SCAN LINE 5
SCAN LINE 6
SCAN LINE 7

-,'

SCAN LINE 8
SCAN LINE 9

II.

-

.. '

C7

C6

C5

C4

C3

C2

C1

a
a
a
a
a
a
a
a
a
a

a

a

a

a

a

a
a
a
a
a
a
a
a
a
a

CHARACTER BLOCK
5 8 CELL

x

a

DOTS PER CHARACTER:
DOT CLOCK XTAL FREQUENCY (MHz):
HORIZONTAL TIMING (IN CHARACTER TIMES):
CHARACTERS PER DATA ROW:
HORIZONTAL BLANKING:
HORIZONTAL SYNC DELAY:
HORIZONTAL SYNC PULSE WIDTH:
HORIZONTAL SYNC POLARITY:

a

a

a
7
10.92

80
20
4
8
NEGATIVE ACTIVE

I+----HORIZ BLANKING---..J
,
. I

ACTIVE VIDEO

VIDEO

a

---------1

ACTIVE VIDEO

L.I_______-_

HSYNC
HORIZ SYNC DELAY

III.

IV.

-I. .1 ..

HORIZ SYNC--.l
PULSE WIDTH

VERTICAL TIMING:
CHARACTER ROWS:
SCAN LINES PER CHARACTER:
TOTAL VISIBLE SCAN LINES:
VERTICAL SYNC POLARITY:

24
x10

240
NEGATIVE ACTIVE

VERTICAL SYNC TIMING (IN SCAN LINES):
60 Hz VERTICAL BLANKING:
60 Hz VERTICAL SYNC DELAY:
60 Hz VERTICAL SYNC PULSE WIDTH:
ALTERNATE (50 Hz) VERTICAL BLANKING:
ALTERNATE (50 Hz) VERTICAL SYNC DELAY:
ALTERNATE (50 Hz) VERTICAL SYNC PULSE WIDTH:
ACTIVE VIDEO

VIDEO
VSYNC

20
4
8
72
30
10

L...- VERTICAL BLANKING --.I

I

,-

--------1

ACTIVE VIDEO

,--I_____-__-_-_

--\V~S;YNNCr.nD~E~LA~Y~=414;:~·~1~4--VERTSYNC~
PULSE WIDTH

412

V.

COMPOSITE SYNC OUTPUT (IN CHARACTER TIMES):
COMPOSITE SYNC DELAY:
COMPOSITE SYNC PULSE WIDTH:

2
8

ACTIVE VIDEO

VIDEO

ACTIVE VIDEO

--------,

,--------

CSYN

CSYN DELAY -

I-----J.-tl

...
~f--_
.....
, ..

VI.

UNDERLINE ATTRIBUTE AND CURSOR LINE:

VII.

WIDE GRAPHICS FIGURE DEFINITION:
COLUMN

->

C7

C6

C5

CSYN PULSE WIDTH

SCAN LINE 9

C4

C3

C2

C1

SCAN LINE 0 ->
SCAN LINE 1 ->

SEGMENT 6

SEGMENT 3

SEGMENT 5

SEGMENT 2

SEGMENT 4

SEGMENT 1

SCAN LINE 2 ->
SCAN LINE 3 ->
SCAN LINE 4 ->
SCAN LINE 5 ->
SCAN LINE 6 ->
SCAN LINE 7 ->
SCAN LINE 8 ->
SCAN LINE 9 ->

VIII. THIN GRAPHICS FIGURE DEFINITION:
COLUMN DOT ->

C7

C6

C5

SCAN LINE 0 ->

C4

-

SCAN LlNE3 ->

S
E
G
M
E
N
T

SCAN LlNE4 ->

3

SCAN LINE 1 ->
SCAN LlNE2 ->

SCAN LINE 5 ->

I

SEGMENT 4

SCAN LINE 7 ->
SCAN LINE 8 ->
SCAN LINE 9 ->

-

SCAN LINE 5; C7, C6, C5, C4
C4; SCAN LINES 0, 1, 2, 3, 4, 5
SCAN LINE 5; C4, C3, C2, C1
C4; SCAN LINES 5, 6, 7, 8, 9

413

C2

C1

SEGMENT 2
S
E
G
M
E
N
T
1

SCAN LlNE6 ->

SEGMENT 4 =
SEGMENT 3 =
SEGMENT 2 =
SEGMENT 1 =

C3

I

KEYBOARD
CONN

;;;f D~I'!

OPTIONAL
SERIAL
EEROM

XTAL 1

XTAL 1 XTAL2
INTO

...---aINT1

XTAL2

CS

P2.3
P2.2

SK

P2.1

DI

P2.0

DO

LS24G'
VSYNCP~.~--------~

HSYNC b-------j'-----j

I P25

PO.l-PO.O

K.

)j DB7-DB.B'

8051
OR
EQUIVALENT

~
-l>-

::>

DWRP~------------,

CRT 9028

T - I P'6

:>

•

I

DISPLAY MEMORY

IRxD

K. ADDRESS BUS .Il A1,ff-AG

PRINTER 1488
CONN
~

'Q--I----OI P'5

:~t

£:
CRT 9028
TYPICAL APPLICATION

2KX8
STATIC RAM
\.

DATA BUS

}

'HORIZONTAL SYNC

I~

INTOUTI
f------il TxD

~

680 VIDEO
I~
3900

~Io
VIDEO

COMM
CONN

VERTICAL SYNC

~ D7-DG'

TO MONITOR

LS241t
VSYNC p-1It-'- - - - - - I
HSYNC b'""'.~--+----1

HORIZONTAL SYNC
TO MONITOR

I~

VIDEO 10

I~

INTOUTI
DB7-DBl!'

,VERTICAL SYNC) }

=
DWR

CRT 9128
DISPLAY MEMORY
DA HI'-DAll'

AID
DS

DD7-DD0~

R/iN

CRT 9128

TYPICAL APPLICATION

A tff-M

ADDRESS BUS

2KX8
STATIC RAM
DATA BUS

:i

D7-Dl!'

N

.
(\,)

ex>

1
1

~'--~--~~--~~--~~--

X

CHARN

X

•

1

1

1

1

"'-_ _ _"'-_ _--:1

1

I

I

I

X

I

1

CHARN/2X

X

X

:

1

0111-010
(DOUBLE)
WIDTH

---!...---......
X
CHAR N/2

:

X

X

X

'
1
I

I

1

1

I

I

I

I

r

I

CHAR 3
:

CHAR 0

X

:

CHAR 1

I

I

X CHAR 2
.

1

BLANKING

\.. _ _~ _ _-J

!'

INT(N-2)

X

_______________

ATTRIBUTE IN'
( DOUBLE)
WIDTH
ATTRIBUTE OUT'
DOUBLE)
(
WIDTH

1

I

VIDEO
( DOUBLE) VIDEO (N/2-1)
WIDTH
!'
ATTRIBUTE IN'
( NORMAL)
WIDTH
ATTRIBUTE OUT'
( NORMAL)
WIDTH

1

I

:

VIDEO (N-2)

1

CHAR 0

I

,

I

I

I
I

,
I

X

1

~

X

I

----{, r----\

I

~r---"I

X

_ _ _---if

0111-010
(NORMAL)
WIDTH

VIDEO
(NORMAL)
WIDTH

1-

~I

X
1I

I

I

I

I

I

I

~

------------~
X

X

"

X

X

1-Attributes include MSO, MSI, BLINK, CHABL, HINT, BOLD, REVIO and XCURS

FIGURE 5: CRT 9041 FUNCTIONAL I/O TIMING

I

ATTO

X'---A-'-;T-1---',[

I

I

I

PROGRAM OPTIONS
The CRT 9041 has a variety of mask programmed options. Tables 8 and 9 illustrate the range of these options for the wide
and thin graphics modes respectively. Table 10 illustrates the range of the miscellaneous other mask programmed options.
In addition, Tables 8, 9 and 10 show the mask programmed options for the CRT 9041-004.

TABLE 8: WIDE GRAPHICS
MASK PROGRAMMING OPTIONS

OPTION

CRT 9041-004

CHOICES

Height of Graphic
block*
011 ANO 07
010 ANO 06
09 ANO 05
08 ANO 04

any
any
any
any

line(s)
line(s)
line(s)
line(s)

RO,R1,R2
R3,R4
R5,R6
R7 thru R15

Width of graphic
block**
011,010,09,08

any consecutive
dots
C11 thru CO

C11 thru C7

all remaining dots
not specified above

C6 thru CO
plus SF

07,06,05,04

scan
scan
scan
scan

•Any graphic block pair can be removed by programming for zero scan
lines.
"Total number of dots for both must be equal to the total dots per character with no overlap. 011,010,09 and 08 must always be to the left
of 07-04.

WIDE GRAPHICS
SL3-SLO ROW# C11
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

RO
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

CO

BF

BF ...

T
011

07

010

06

09

05

08

04

1..-'--w1-----+----wO-------+l·1
HO, H1. H2, H3, WOo W1, are mask programmable.
The values shown are for the CRT 9041-004.

429

H3

+H2

+

t
I

TABLE 9: THIN GRAPHICS
MASK PROGRAMMING OPTIONS

OPTION

STANOARO CRT 9041-004

CHOICES

Backfill

Horizontal position for
06 and 07
08
09
Horizontal length for
06(1)
07(1)

any dot(s) within the programmed 07 range to the right
of the programmed column(s)
for011.

CO

any scan line(s) RO-R15
any scan line(s) RO-R15
any scan line(s) RO-R15

R5
RO
R9

any consecutive dots
all dots not covered by 06 with
one dot overlapping.
Blanked dots for serrated horizontal lines
06
any dot(s), BF programmed
07
any dot(s), BF programmed
08,09
any dot(s), BF programmed
Vertical position for:
04 and 05
010(2)
011 (2)

any dot(s) C11-CO,BF
any dot(s) C1 O-CO,BF
any dot(s) C11-CO

Vertical length for:
04
05
010
011

any scan line(s)
any scan lines not in 04
no choice; always RO thru R15
no choice; always RO thru R15

C11 thru C7
C7thru BF
none
none
none
C7
C3
Cl1
ROthru R5
R6 thru R15
ROthru R15
ROthruR15

(1) 06 and 07 must always overlap by 1 dot. This overlap may be blanked by specifying the proper column(s) in the serration
program line. 07 must always be to the right of 06.
(2) 011 must always come before 010 with no overlap: otherwise 010 is lost.

THIN GRAPHICS

SL3-SLO ROW# Cll
0000
0001
0010
0011

aIDa

0101
0110
0111
1000
1001
1010
lOll
1100
1101
11 10
1111

RO
Rl
R2
R3
R4
R5
R6
R7
R8
R9
Rl0
Rll
R12
R13
R14
RIS

Cl0

C9 CB

C7

C6

C5

C4

C3

08
OIl

04

010

C2

Cl

co

BF

BF.
VERTICAL HEIGHT

==:::JI
I

__ ..J
06

07
05

I

==:J

09

--"

--....j
I

04
05
010
011

RO-R5
R6-RIS
RO-RI5
RO-R1SHORIZONTAL LENGTH

06
07
08
09

C11-C7
C7-BF
Cll-BFCl1-BF'

-

The height of 04 and OS, lhe length of 06 AND 07, and the position of
04-011 are mask programmable. The values shown are for the CRT 9041-004.
*These values are fixed

430

HORIZONTAL POSITION
PROGRAMMABLE
PROGRAMMABLE
PROGRAMMABLE
PROGRAMMABLE
VERTICAL POSITION
PROGRAMMABLE
PROGRAMMABLE
PROGRAMMABLE
PROGRAMMABLE

TABLE 10: MISCELLANEOUS MASK PROGRAMMING OPTIONS
"STANDARD" CRT 9041-004

CHOICES

OPTION
Backfill in character mode

C11 or CO

C11

Character blink rate
(division of VSYNC frequency)

7.5 Hz to 0.5 Hz (1) (1)

1.25Hz (1)

Cursor blink rate (2)

same as, half, or twice the character blink rate

2.50 Hz (1)

Character blink duty cycle
Cursor blink duty cycle

50/50 or 75/25
50/50 or 75/25

50/50
50/50

Character underline 1 position

any scan line(s) RO thru R15

R8

Character underline 2 position

any scan line(s) RO thru R15

R10

Cursor underline position

any scan line(s) RO thru R15

R9

Extra cursor underline position

any scan line(s) RO thru R15

R11

Cursor format (3)

underline
blinking underline
reverse video block
blinking reverse video block

blinking reverse
video block

Extra cursor format (3)

underline
blinking underline
reverse video block
blinking reverse video block

blinking
underline

Blink table

Table 1
Table 2
Table 3

Table 3

CURSOR or XCURSOR effect on
BOLDO and HINTO

no effect or force to zero at cursor
position

force to zero at cursor position.

(1) Assumes VSYNC input frequency of 60 HZ.
(2) Valid only if the cursor is formatted to blink.
(3) Valid for the parallel scan line mode only.
r---

V:=;1

~.1~~ifr--

r-

I.~f-

hH

OEi-J

----'"

011·00.DST

CHARACTER
ROM
SYSTEM RAM

OR
SINGLE ROW
BUFFER

F~g~
(()~H10ll[f1

1,l2

SL3-SLO

VsvNC

VSYNC
RETBL
CURSOR

RETBL

CURSOR

OR

CRT 9041
VAC

VIDEO
HINTO
BOLDO

MSO
MSI

DOUBLE ROW
BUFFER

~
Ix

~1

BUNK
CHABL
HINTI

BOLD I
RS
XCURS/GPll
UL2 1 GP21
REVID
ATTEN
LO SH
VDC

I
CLOCK =:jl
GENERATOR

FIGURE 6a: CRT 9041 SYSTEM CONFIGURATION IN
PARALLEL SCAN LINE MODE

431

f-.GPlO
f - . GP2O

VIDEO
TO MONITOR

,--

"
V

l
A
T
C
H

V

I

t--

7

7
8
.... D

OOUBLEROW
BUFFER

ffu~
0

()

CHARACTER
ROM

SLG

7 "011-00.0ST

"

CRT 9041

V

VAC

t

OR

~~g

OE I-

y

3

OR

~

rcK

SYSTEM RAM

~

t--

t--

4

SINGLE ROW
BUFFER

I--

----ill.P-

-

"

THREE
STATE

DRIVER

SlG
SlD
VSYNC
RETBL
CURSOR

SLD

VSYNC
RETBL

CURSoR

MSO
MSI
BLINK
CHABL
HINTI
BOLD I
RS
XCURS/GP11
UL2/GP21
REVIO
ATTEN
WISH
VDC

I

I

VIDEO
HINTO
BOLDO

CLOCK
GENERATOR

I

BKC

VIDEO
TO MONITOR

-GP10
-GP20

BlC

P~g~~~~~62 I.---J
FORMAT

;[J-

1

I

FIGURE 6b: CRT 9041 SYSTEM CONFIGURATION IN
SERIAL SCAN LINE MODE

STANDARD MICROSVSTEMS
CORPORATION
3, Marcus B/vd Hauppauge NY 11188
151612733100 TWX-510'2neegs

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor appliGations; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any ttme in order to improve design and supply the best product possible.

432

CRT 9053
CRT 9153
PRELIMINARY

EVTLC
Enhanced Video Terminal Logic Controller
PIN CONFIGURATION

FEATURES
D Built-in High Frequency (4-18.7 MHz) Oscillator
D Built-in Video Shift Register

DA8
DA9
DA10
GND
XTAL2
XTAL1
VIDEO
INTOUT
DWR
DDO
DOl
002
DD3
004
005
DD6
007
HSYNC
VSYNC
CSYN

D Built-in Character Generator (128 Characters,
7x11 Dot Font)

.

D Bi-Directional Smooth Scroll Capability
D Visual Attributes Include Reverse Video, Intensity
Control, Underline, and Character Blank and Blink
D Separate HSYNC, VSYNC and VIDEO Outputs
D Composite Sync (RS170 Compatible) Output
D Absolute (RAM address) Cursor Addressing
D MASK Programmable Video Parameters:
Dots Per Character Block (8-9)
Raster Scans Per Data Row (11,13)
Characters Per Data Row (32,48,64,80)
Data Rows Per Page (8,10,12,16,20,24 or 25)
Horizontal Blanking (8-64 Characters)
Horizontal Sync Front Porch (0-7 Characters)
Horizontal Sync Duration (1-64 Characters)
Horizontal Sync Polarity
Two Values of Vertical Blanking
Two Values of Vertical Sync Front Porch (0-63 Scan
Lines)
Two Values of Vertical Sync Duration (1-16 Scan
Lines)
Vertical Sync Polarity
Internal 128 Character 7x11 Dot Font
Character/Cursor Underline Position
Character/Cursor Blink Rate
Scan Rowand Column for Thin Graphics Entity
Segments
Scan Rows and Columns for Wide Graphics Entity
Elements
D Software Enabled Non-Scrolling 25th Data Row Available with 25 Data Row/Page Display
D Non-Interlace Display Format

'-'

10
90
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

P

P
P

DA7
DA6
DA5
DA4
DA3
DA2
DAl
DAO
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DBO
AD

..
..

VCC

CRT 9053

CRT9153

Pin23
Pin 22

Pin23
Pin 22

RD

WR

OS
Rill

D Embedded Attribute or Tag Bit Attribute Capability
D Separate Display Memory Bus Eliminates Contention
Problems

D Fill (Erase) Screen Capability
D Standard 8-bit Data Bus Microprocessor Interface
D Wide Graphics with Six Independently Addressable
Segments Per Character Space

D Thin Graphics with Four Independently Addressable
Segments Per Character Space

D Single + 5V Supply

D COPLAMOS® n-Channel Silicon Gate Technology
D TTL Compatible

GENERAL DESCRIPTION
(WR) strobes for use with the 8085, 8051, Z80®, 8086, and
similar microprocessors or microcomputers. The CRT 9153
regulates the data flow with a data strobe (OS) and read/
write (R/W) enable signals for use with the 6500, Z8'M, 68000
and similar microprocessors or microcomputers.
The EVTLC provides two independent data buses; one
bus that interfaces to the processor arid one that interfaces
to the display memory. Data is transferred to the display
memory from the processor through the EVTLC eliminating
contention problems and the need for a separate row buffer.

The CRT 9053 EVTLC and CRT 9153 EVTLC are mask
programmable 40 pin COPLAMOS® n-channel MOS/LSI
Video Display Controller Chips that combine video timing,
video attributes, alphanumeric and graphics generation,
smooth scroll and screen buffer interface functions.
The EVTLC incorporates many of the features (previously requiring a number of external components) required
in building a low cost yet versatile display interface. An
internal mask programmable 128 character font provides
for a full ASCII character set. Wide graphics allow plotting
and graphing capabilities while thin graphics and visual
attributes can make the display of forms straight-forward.

The EVTLC has an internal crystal oscillator requiring only
an external crystal to operate. Masked constants for critical
video timing simplify programming, operation and improve
reliability. A separate non-scrolling status line (enabled or
disabled by the processor) is available for displaying system status.

Two pinout configurations enhance the versatility of the
EVTLC. The CRT 9053 controls data flow over the processor system data bus through separate read (RD) and write
'Z80 is a registered trademark of Zilog Corporation.
Z8 is a trademark of Zilog Corporation.

433

em

CLOCK

CHARACTER

CLOCK

FIGURE 1. EVTLC FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION OF PIN FUNCTIONS
PINNa.

SYMB.OL

1/0

3-1,40-33

DA10-0

a

Display
Address

11 bit address bus to display memory

NAME

DESCRIPTION

4

GND

Ground

Ground Connection

5,6

XTAL2,1

I

Crystal 2, 1

External Crystal
An external TTL level clock may be used to drive XTAL 1 (in
which case XTAL2 is left floating).

7

VIDEO

a

Video Output

This output is a digital TTL waveform used to develop the
VIDEO and composite VIDEO signals to the monitor. The
polarity of this signal is: HIGH = BLACK
LOW = WHITE

8

INTOUT

a

Intensity
Output

This pin is the intensity level modification attribute bit (synchronized with the video data output).

9

DWR

a

Display
Write

Write strobe to display memory

17-10

007-0

1/0

Display
Data

8-bit bidirectional data bus to display memory

.'

18

HSYNC

a

Horizontal
Sync

Horizontal sync signal to monitor

19

VSYNC

a

Vertical
Sync

Vertical sync signal to monitor

20

CSYNC

a

Composite
Sync

This output is usee! to generate an RS170 compatible composite VIDEO signal for output to a composite VIDEO monitor.

21

Vee

Power

5.0 V power connection
CRT 9053

22

WR

I

Write Strobe

Causes data on the microprocessor data bus to be strobed into
the EVTLC

23

RD

I

Read Strobe

Causes data from the EVTLC to be strobed onto the microprocessor data bus

22

RIW

I

ReadlWrite
Select

Determines whether the processor is reading data from or writihg data into the EVTLC (high for read, low for write)

23

OS

I

Data Strobe

Causes data to be strobed into or out of the EVTLC from the
microprocessor data bus depending on the state of the R/W
signal

24

AID

I

Register
.Select

The state of this input pin will determine whether the data is
being read from, or written to, the address or status register, or
a data register.

32-25

DB7-0

1/0

Processor
Data Bus

8-bit bi-directional processor data bus

CRT9153

434

DESCRIPTION OF OPERATION
THE EVTLC INTERNAL REGISTERS

bit is set to a logic zero by reading from, or writing to, the
CHARACTER register. The processor must wait until the
DONE bit is 1 before attempting to change the CURSOR
ADDRESS, in order to write a character to, or read a character from, the CHARACTER register.

CRT 9053
Addressing of the internal EVTLC data registers of the
CRT 9053 is accomplished thrQ':!.9..h the use of the AID select
input qualified by the RD and WR strobes.

AID RD WR

o
o

1
0
1

STATUS REGISTER

REGISTER OPERATION

0

WRITE TO DATA REGISTER
READ DATA REGISTER
WRITE TO ADDRESS REGISTER
READ STATUS REGISTER

o

o

o
o

0

0

o
o
o

o

REGISTER OPERATION
WRITE TO DATA REGISTER
READ DATA REGISTER
WRITE TO ADDRESS REGISTER
READ STATUS REGISTER

The contents of the eight processor programmable registers located in the upper left hand side of the Functional
Block Diagram of figure 1 indicate the memory locations
from which screen data is to be fetched and displayed as
well as the selected modes of display operation. These registers are addressed indirectly via the Address Register.
To access one of the eight eight-bit registers, the processor must first load the Address Register with the threebit address of the selected data register. The next read or
write to a data register will then cause the data register
pO.!£1ted to by the Address Register to be accessed. The Line
AID controls whether writing is occurring to the Address
Register 00.0 a data register. When a read operation is performed, NO controls access to either the Status Register
or to the data register selected by the Address Register.

REGISTER DESCRIPTION

ADDRESS

,, , , ,
,,, , ,, ,
, , ,
,, ,, ,, ,

X

X

X

X

TYPE

REGISTER

Write
Write
Write
Write
Write
Write
RD/WR
Write
Write

CHIP RESET
TOSADD
CURLO
CURHI
FILADD
ATTDAT
CHARACTER
MODE' REGISTER
MODE2 REGISTER

X

X

X

X

X

X

DATA REGISTERS
FILADD (Fill Address) This register contains the RAM
address of the character following the last
address to be filled. Writing to this register will
enable the EVTLC "fill" circuitry. The FILL operation will then be triggered by the next processor
write to the CHARACTER register. The FILL
operation will write the character in the CHARACTER register to every location in display
memory st.arting with the address specified in the
CURLO and CURHI registers through the location preceding the address specified in the
FILADD register. The cursor position is not
changed after a FILL operation. Note that the
address bits DA3-DAO are internally forced to 0
forcing the FILADD address to be 00,16,32, etc.
to 1920. The CURLO and CURHI registers will
not be changed by this operation. Writing to the
CHARACTER register will cause the. EVTLC to
reset DB7 of the STATUS register to "0". Bit 7
will be set to 1 after the EVTLC has filled the last
memory location specified.
FILADD REGISTER

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO

ADDRESS REGISTER
Writing a byte to the ADDRESS register will select the
specified register for the next time the processor writes to
or reads the EVTLC data registers. The data register
addresses are as follows:
DB7 DB6 DB5 DB4 DB3 DB2 DB' DBa
x x x x a
a
a
a
X X X X
a
X
X X
X
a
a
a
X
X
X
X
a
X
X
X
X
a
X
X
X
a
a
X
X
X
X
X
a
a
X
X
X
X

x

DONE

DONE = 1 signifies that external processor is allowed to
access CURSOR ADDRESS andlor
CHARACTER registers.
DONE = 0 signifies that external processor must wait
until EVTLC completes transfer of data
between display memory and CHARACTER
register.

CRT9153
Addressing of the internal EVTLC data registers of the
~RT 9153 is accomplished thro~ use of the AID and RI
W select inputs qualified by the OS strobe.

AID OS R/iN

DB6 DB5 DB4 DB3 DB2 DB1 DBO

DB7

X

DA 10 DA9 DAB DA7 DA6 DA5 DA4

TOSADD (Top of Screen Address) This register contains
the RAM address olthe first character displayed
at the top of the video monitor screen. In addition, this register controls selection of either of
two mask programmable vertical scan rates.
TOSADD REGISTER
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
TIM DA10 DA9 DAB DA7 DA6 DA5 DA4
Note that address bits DA3-DAO are internally
forced to 0 forcing the first address at the beginning of each row to be 00, 16, 32, etc. to 1920.
The most significant bit of this register (TIM)
is used to select between the two mask programmed sets of vertical retrace parameters
(scan A and scan B). This allows software
selection of, for example, 50/60 HZ.
TIM = 0 enable raster scan A (60 Hz)
TIM = 1 enable raster scan B (50 Hz)

(X - don t care) NOTE. Chip Reset IS required before starling operallon.

STATUS REGISTER
When reading the STATUS register, the DONE bit (DB7
of STATUS Register) will represent the current status ofthe
CHARACTER register. This bit is used to synchronize data
transfers between the processor and the EVTLC. The
EVTLC will set the DONE bit to a logic one after completing
a byte transfer command or a FILL operation . .The DONE

435

CURLO

affected by the display character's TAG bit.
NOTE: All 8 bits are valid for the 9x28 mode. In
the 9x53 mode the only bits that are recognized
are DB6, 5 and 4.

(Cursor Low) This register contains the eight
lower order address bits of the RAM cursor
address. All FILL screen and character transfer
operations begin at the memory location pointed
to by this address.
CURLO REGISTER
DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
DA? DA6 DA5 DA4 DA3 DA2 DA 1 DAO

CURHI

ATTDAT REGISTER

(Cursor High) This register contains the three
higher address bits of the RAM cursor address
(DA10, DA9, DA8). All FILL screen and character transfer operations begin at the memory
location pointed to by this address. In addition,
this register contains the Smooth Scroll Offset
Values SS3-SS0 which determine the number
of scan lines that the data is shifted on the
screen. The MSB of this register (SLE-status line
enable) is the enable for the non-scrolling status
line.

DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
DB?(1) MODE
SELECT

DB?
DB?

CURHI REGISTER
DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
SLE SS3 SS2 SS1 SSO DA10 DA9 DA8

DB6

SLE = 1 enables non-scrolling 25th
status line
SLE = J5 disables and blanks nonscrolling status line

CURSOR
SUPPRESS

SS3-SS0 Smooth Scroll Offset Value
ATTDAT

DB6

DB6

(Screen Attribute Data) Two attribute modes are
provided. In the "tag bit" attribute mode, the MSB
of each character is used to "tag" those characters which are to be enhanced with the attribute specified by the ATTDAT register. This allows
individual characters to be attributed, but with the
limitation that only one attribute style may be
enabled for a specific screen. This is compatible
with the CRT9028/9128, and is specified as the
9x28 operation mode. In the "embedded attribute" mode, multiple attributes may be displayed
on one screen. This is specified as the 9x53
operation mode ..See "MODE 2" register for
selection of 9x28 and 9x53 modes.

DB5

The ATTDAT register specifies the visual attributes of the video data, in 9x28 operation mode,
and the cursor presentation. The visual attributes specified in the ATTDAT register (DB3DBO) are enabled or disabled by a TAG bit that
is appended to the ASCII character written to the
CHARACTER register. Every character on the
screen with its TAG bit set is displayed with the
same attribute. Changing the Attribute register
will change the attribute of every "tagged" character on the screen. Character attributes in the
9x53 mode are determined by specific attribute
characters embedded in the character data
stream as explained below in the section titled
CHARACTER SETS. The functions of the
remaining bits in the ATTDAT register are not

DB4

CURSOR
DISPLAY

SCREEN

mode display (No
attributes allowed)
= 0 enables alpha
mode display
Note: See CHARACTER SETS for
definition of characters available in
each mode.
= 1 inhibits VIDEO dis-

play at cursor time
by forcing the
VIDEO output to
background level
during cursor displaytime
= 0 enables VIDEO
display at cursor
time
Note: A blinking
cursor display can
be achieved by
toggling this bit
under processor
control.

DB5

= 1 enables underline

DB5

=

DB4

=

DB4

436

= 1 enables graphics

cursor display
0 enables block cursor display
Note: An underline
cursor in an underline character
attribute field will
be dashed.

1 for white screen
and black
characters
= 0 for black screen
and white
characters
Note: This is a
screen attribute
(versus character
attribute) bit and
sets the default
video background
level.

~---~---------"

~----------------~

DB3(1) CHARACTER DB3= 1 to enable Video
SUPPRESS
suppress
DB3 = 0 to inhibit Video
w
suppress
o
Note: This bit allows
o
:2:
character blinking
and blanking under
processor control

~
o

MODE 2

~

I-

m DB2(1)
o
;:5

INTENSITY

DB2= 1 allows the INTOUT
output pin to go
high for the charactertime
DB2= 0 inhibits the
INTOUT output pin
from going high

in
o

W

-I

co

ffi

MODE 2 REGISTER
DB? DB6 DB5 DB4 DB3 DB2 DB1
X

is
cause the chara: DB1(1) UNDERLINE DB1 = 1 will
acterto be
o
underlined

o
W

X

X



SCAN LlNEO

->

SCAN LINE 1

->

SCAN LINE 2

->

SCAN LINE 3

->

SCAN LINE 4

->

SCAN LINE 5

->

SCAN LlNE6

C8

C7

C6

C5

C4

C3

C2

C1

CO

Dots/Character: 8 dots/character cell ,= > C8 - C1 displayed
9 dots/character cell = > CB - CO displayed
Column dot CO will be the same as column dot CB when more
than 8 dots/character cell are specified when generating alpha-numerics.
NOTE: The maximum dot clock crystal frequency is dependent on"the
dots/character programmed:
MASK PROGRAMMABLE
CHARACTER BLOCK
(FONT)
7X 11

'These values are preliminary

SCAN LINE 7

->

SCAN LlNE8

->

Scan Lines per Character:
11 scan lines/character =

SCAN LINE 9

->

12 scan lines/character ~
13 scan lines/character ~

> SLO-SL 10 displayed

> SLO·SL 11
>

displayed
SLO·SL 12 displayed

SCAN LINE 10

Thin and Wide Graphics: Dots mask programmed for vertical column C1
will be the same as backfill Columns 0 when
generating wide and thin graphics.

SCAN LINE 11
SCAN LINE 12

->

Mask programmable options-The ROM character block format above shows the 7X11 mask
programmable character font within the character cell as defined by dots C8 through CO and
scan lines 0 through 12.

439

._----------------

------

--.~--.

MAXIMUM GUARANTEED RATINGS*
O'perating Temperature Range .................... , ..................................................ooe;:; to + 70°C
Storage Temperature Range ......... ; ................................. ; ............................. - 55°C to + 150°C
Lead Temperature (soldering. 10 sec.) ............................................................ .' .. + 325°C
Positive Voltage on any Pin. with respect to ground ............. , ................................... + S.OV
Negative Voltage on any Pin. with respect to grourid ..................... , ........................ ,. - 0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above thoSE! indicated in the operational sections of this
specification is not implied.
NOTE: When powering this device from laboratory or system power supplies. ii is important that the Absolute Maximum Ratings not be exceeded or device failure can result. SomE{ power supplies exhibit voltage spikes or "glitches"
on their outputs when the AC power is switcl:Jed on and off. In addition. voltage transients on the AC power line may
appear onthe PC output. If this possibility exists. it is suggested that a clamp circuit be used.

ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C. V"= +5V ±5%. unless otherwise noted.)

DC CHARACTERISTICS
INPUT VO'LTAGE LEVELS
Low-level. Vii
High-Level. Vih
O'UTPUT VO'LTAGE LEVELS
Low-level. Vol

O.S
2.2
0.4

Low-level. Vol

0.4

V

High-level. Voh

2.4

V

High-level. Voh

2.4

V

INPUT LEAKAGE CURRENT
High-Ievel.llh

Ali outputs except
VIDEO'. CSYNC.
INTO'UT. HSYNC,
VSYNC; 101 = 1.6 mA
VIDEO'. CSYNC,
INTO'UT. HSYNC.
VSYNC; 101 = 0.4 mA
All outputs except
VIDEO'. CSYNC.
INTO'UT, HSYNC.
VSYNC; loh =
-40f,la
VIDEO', CSYNC.
INTO'UT, HSYNC.
VSYNC; loh =
-20f1A

10

f,lA

All inputs; Vin = Vcc

Low-level. III

-10

f,lA

All inputs
except WR. RD.
DS. R/Vi]; Vin = O.4V

LOW-level. III

-200

f,lA

WR.RD.
OS. R/Vi]; Vin = O.4V

15

pF

15
100

pF
pF

INPUT CAPACITANCE
All inputs. Cin
O'UTPUT LO'AD
CL
CL
PO'WER SUPPLY CURRENT
Icc
AC CHARACTERISTICS

125

CLO'CKFREQUENC~fin

1.0

DISPLAY MEMO'RY TIMING
Address Set-up Time
t AS
Write Strobe Set-up Time
t WST
Data Set-up Time
tST
Data Hold Time
tOH

1S.7

MHz

20

ns

10.0

ns

SO

ns

10
440

mA

50

ns

Except DB7-0
DB7-0

PARAMETER

MIN

Addre~$ ~pld Time
tAHT
Output Hold From Address Change
tOH
Address Access Time
tAA
PROCESSOR TIMING
Address Read/Write Set-up
tARwS
Write Pulse Width
twpw
Write Hold Time
tWHT
Read Set-up Time
t RST
Read Data Valid
T Rov
Read Pulse Width
t RPw
Data Write F

SCAN LINE 0

->

0

SCAN LINE 1

->

0

0

SCAN LINE 2

->

0

0

SCAN LINE 3

->

0

0

SCAN LINE 4

->

0

0

SCAN LINE 5

->

0

C8 C7 C6 C5 C4 C3 C2 C1 CO
0

-

-

0

0

0

0

0

0

0
CHARACTER BLOCK
7X11 CELL

SCAN LINE 6

->

0

SCAN LINE 7

->

0

0

SCAN LINE 8

->

0

0

SCAN LINE 9

->

0

0

SCAN LINE 10

->

0

0

SCAN LINE 11

->

0

0

DOTS PER CHARACTER:
DOT CLOCK XTAL FREQUENCY (MHz):
HORIZONTAL TIMING (IN CHARACTER TIMES):
CHARACTERS PER DATA ROW:
HORIZONTAL BLANKING:
HORIZONTAL SYNC DELAY:
HORIZONTAL SYNC PULSE WIDTH:
HORIZONTAL SYNC POLARITY:

VIDEO

0

ACTIVE VIDEO
- - - - -

0

9
17.1072
80
19

4
8
NEGATIVE ACTIVE

I+-HORIZ BLANKING~

I

ACTIVE VIDEO

1

--I

1
....._-_-_-_-_-_-_-_-_

HSYNC
HORIZ SYNC DELAY

III.

IV.

-I.

~..

HORIZSYNC~

PULSE WIDTH

VERTICAL TIMING:
CHARACTER ROWS:
SCAN LINES PER CHARACTER:
TOTAL VISIBLE SCAN LINES:
VERTICAL SYNC POLARITY:

25

x 12
300
NEGATIVE ACTIVE

VERTICAL SYNC TIMING (IN SCAN LINES):
60 Hz VERTICAL BLANKING:
60 Hz VERTICAL SYNC DELAY:
60 Hz VERTICAL SYNC PULSE WIDTH:
ALTERNATE (50 Hz) VERTICAL BLANKING:
ALTERNATE (50 Hz) VERTICAL SYNC DELAY:
ALTERNATE (50 Hz) VERTICAL SYNC PULSE WIDTH:
ACTIVE VIDEO
VIDEO

r--

VSYNC DELAY

14

8
84
17
34

VERTICAL BLANKING-1

--------1

VSYNC

20
4

ACTIVE VIDEO

1. . .__-_-_-_-___-_
"1 4

VERT SYNC----1
PULSE WIDTH

444

V.

COMPOSITE SYNC OUTPUT (IN CHARACTER TIMES)
COMPOSITE SYNC DELAY:
COMPOSITE SYNC PULSE WIDTH:

2
8

ACTIVE VIDEO

VIDEO

ACTIVE VIDEO

--------1

1--------

CSYN

1-1--_
..
..+I..---.Jt1Jto!

CSYN DELAY -

VI.

CSYN PULSE WIDTH

BLINK RATES (@ 60 Hz VSYNC):
CHARACTERBLINK RATE:
DUTY CYCLE:

1.25 Hz

75/25

CURSORBLINK RATE:
DUTY CYCLE:
VII.

2.5 Hz

50/50

UNDERLINE ATTRIBUTE:
CHARACTER UNDERLINE:
CURSOR UNDERLINE:

SCAN LINE 11
SCAN LINE 11

VIII. WIDE GRAPHICS FIGURE DEFINITION:
COLUMN
SCAN LINE

°

->

ca C7

C6

C5 C4

C3 C2

C1

CO

->

SCAN LINE 1 ->

SEGMENT 6

SCAN LINE 2 ->

T

SEGMENT 3

H2

1

SCAN LINE 3 ->

T

SCAN LINE 4 ->
SCAN LINE 5 ->
SEGMENT 5

SCAN LINE 6 ->

SEGMENT 2

f

SCAN LINE 7 ->
SCAN LINE a ->
SCAN LINE 9 ->
SEGMENT 4

SCAN LINE 10->

IX.

W1

SEGMENT 1

.1..

H1

=

SCAN LINES 4, 5, 6, 7

HO = SCAN LINES a, 9, 10, 11
W1 = ca, C7, C6, C5, C4
wo

=

C3, C2, C1, CO

HO

1

SCAN LINE 11 ->
I.

H2 = SCAN LINES 0, 1, 2, 3

wo~

THIN GRAPHICS FIGURE DEFINITION:
COLUMN DOT ->
SCAN LINED

->

SCAN LINE 1

->

SCAN LlNE2

->

SCAN LlNE3

->

SCAN LlNE4

->

SCAN LlNE5

->

SCAN LINE 6

->

SCAN LINE 7

->

SCAN LINEa

->

SCAN LINE 9

->

ca C7

I

C6 C5 C4 C3
r-S
E
G
M
E
N
T
3

SEGMENT4

SCAN LINE 10 ->
SCAN LINE 11 ->
SEGMENT 4 = SCAN LINE 6; ca, C7, C6, C5, C4
SEGMENT 3 = C4; SCAN LINES 0,1,2,3,4,5,6

C2

C1

CO

SEGMENT 2

I

S
E
G
M
E
N
T

--..L
SEGMENT 2 = SCAN LINE 6; C4, C3. C2, C1, CO
SEGMENT 1 = C4; SCAN LINES 6,7,8,9,10,11

445

I

KEYBOARD
CONN

;;f D~I'!
XTAL 1

OPTIONAL
SERIAL
EEROM

XTAL 1

XTAL2

INTO

~INT1

P2 .3

CS

P2.2
P2 .,
P2.0

SK

XTAL2
LS24ll'
VSYNC ~....t - - - - - - I

01
DO

I~

HSYNC P
VIDEO!o

3900

I~

INTOUTI
TxD

.I>.I>-

0)

HORIZONTAL SYNC
)

I~

I P25
COMM
CONN

,VERTICAL SYNC) }

P07 -POO

DB7-DBll'

-

8051
OR
EQUIVALENT

Ys;;til

DWR
CRT 9053

P1..

~

DA1ll'-DA0t:' ADDRESS BUS

PRINTER 1488
CONN
~

'O-t---of P'5

~o

~o

DISPLAY MEMORY

RxD

P"I-I- - - - I
RD

P

WR ~

AiB

9RD

DD7-DDll'~TABUS

at WR

CRT 9053
TYPICAL APPLICATION

A1.ff-A0

2KX8
STATIC RAM
~ D7-D.Q'

TO MONITOR

KEYBOARD
CONN

OPTIONAL
SERIAL
EEROM
CS

BlTtjSK

INT1
INm

PROG

DI

INT2

PORT

DO

LS24ll'
VSYNC to~It-+'-------;

HSYNCIo"'~

PORT
. BIT IN

COMM
CONN

INTOUT I~------+----i

PORT
AD7-ADll'
Z8 fLC
OR
EQUIVALENT

BIT OUT
~

:!::j

DB7-DB0'

.=
DWR

CRT 9153

PORT
BIT IN

DISPLAY MEMORY

RXD
DA1ll'-DAll'

.PRINTER 1488
CONN
~

HDX
'O-+--

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
V~~~~~~~~~~~~~~G~

Drives Available

0

DAY11
DAY12
DAY13
DAX9
DAX8
DAX7
DAX6
DAX5
DAX4
DAX3
DAX2
DAX2
DAX1
DAXO
tbd
tbd
tbd
VDD

0

z~~uuuuuuuuuuuuuz

o Independent Display and System Buses

c.9£££££££££B£££££c.9

24 Bit x-v Display Memory Address Bus
16 Bit Address/Data Bus to System Memory

PACKAGE: 68 PIN LCC

o Separate Clocks for Display and System Buses

o Automatic and Transparent Dynamic RAM Refresh for

o DMA Master Capabinty for Interfacing to System

Display Memory

Memory

GENERAL DESCRIPTION
The CRT 97C11 Video Engine for Windows (VIEW) is a third
generation CRT controller that is designed to support twodimensional mapping of video data to a display screen. The
VIEW can be used in both bit-map and alphanumeric types
of display interfaces. It allows real time manipulation of
independent windows on the screen with a minimum of processor intervention.
The system or graphics processor communicates with the
VIEW via a window list in system memory. The size and
screen location of each window and address pointers to the
contents of each window are maintained in this list. The
VIEW generates display memory addresses by reconciling
the X and Y memory address coordinates at which the win-

dows start and end with the X and Y raster addresses. The
VIEW preprocesses and stores this information in three
internal break buffers.
As the VIEW generates the display memory addresses for
the windows, it automatically resolves priority conflicts that
arise when two or more windows overlap. Background windows are output by repetitively addressing a pattern word
which significantly optimizes the use display memory. The
VIEW can also buffer and output general purpose attribute
bits for each window that it displays as it generates that window's addresses. Automatic dynamic RAM refresh
addressing during horizontal and vertical retrace intervals
is also supported.

455

STANDARD MICROSYSTEMS ~~~~jl~~~i~r~~sa~~gz~~Tfi~~n9 fg~oc~~~t~u~fo~n~~Ur~~~e~SiSan~te~;ge~~~I~~:~~~~~ iY~~~~o~~~~f~~i~~~; b~en~~~~~~i\~
CORPORATION
checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore,
35MarcusBlVll Ho"pp;lUgl' NY1178B
15'61713311)1J

TWX

~lU

{278898

such information does not convey to the purchaser of the products described any license under the patent rights of
SMC or others. SMC reserves the right to make changes at any time in order to improve design and supply the best
product possible.
.

456

457

458

FDC765A/765A-2
FDC 7265/7265-2

Single/Double Density Floppy Disk Controller
PIN CONFIGURATION
FEATURES

o IBM Compatible in both Single and Double Density

RESET
RD
WR 3

Recording Formats (FDC765A)
o Sony (EMCA) Compatible Recording Format
(FDC7265)
Programmable Data Record Lengths: 128, 256, 512, or
1024 Bytes/Sector
Multi-Sector and Multi-Track Transfer Capability
Drive Up to 4 Floppy Disks
o Data Scan Capability-will scan a Single Sector or an
entire cylinder's worth of data fields, comparing on a
Byte by Byte Basis, data in the Processor's Memory
with data read from the Diskette
o Data Transfers in DMA or Non-DMA Mode
Parallel Seek Operations on up to four drives
Compatible with Most Microprocessors
Single Phase 8 MHz Clock
o Single + 5 Volt Power Supply
o COPLAMOS® n-Channel Silicon Gate Technology
Available in 40-Pin Dual-in-Line Package

CS

o
o
o

Ao
DBo 6
DB, 7
DB, 8
DB, 9
DB,10
DB511
DB612
DB,13
DRQ 14
DACK 15
TC 16
IDX 17
INT 18
CLK 19
GND 20

o
o
o

40
39
38,
37
36
35
34
33,
32
31
30
29
28
27
26
25
24
23
22
21

Vee

RW/SEEK
LCT/DIR
FRISTP
HDL
RDY
WP/TS
FLT/TRo
PSo
PS,
WDA
USo
US,
HD
MFM
WE
VCO
RDD
RDW
WCK

o

GENERAL DESCRIPTION
The FDC765A is an LSI floppy disk controller (FDC) chip,
which contains the circuitry and control functions for interfacing a processor to 4 floppy disk drives. It is capable of
either IBM 3740 single density format (FM), or IBM System
34 double density format (MFM) including double-sided
recording. The FDC765A provides control signals which
simplify the design of an external phase-locked loop and
write precompensation circuitry. The FDC simplifies and
handles most of the burdens associated with implementing
a floppy disk interface.

every time a data byte to be transferred. In the DMA mode,
the processor need only load the command into the FDC
and all data transfers occur under control of the FDC and
DMA controllers.

The FDC7265 is an addition to the FDC family that has been
designed specifically for the Sony Micro Floppydisk® drive.
The FDC7265 is pin-compatible and electrically equivalent
to the 765A but utilizes the Sony recording formal. The
FDC7265 can read a diskette that has been formatted by
the FDC765A.

Read Data
Read 10
Specify
Read Track
Scan Equal
Scan High or Equal
Scan Low or Equal

There are 15 commands which the FDC765A/FDC7265 will
execute. Each of these commands requires multiple 8-bit
bytes to fully specify the operation which the processor
wishes the FDC to perform. The following commands are
available:

Each of these devices is also available in a -2 version. The
-2 versions represent a reduction from 4-micron to 3-micron
design rule. Functionally is the same. Minor differences
between the two versions are detailed in the AC Characteristics table. The -2 versions are only available in the plastic
package at this time.

Read Deleted Data
Write Data
Format Track
Write Deleted Data
Seek
Recalibrate
Sense Interrupt Status
Sense Drive Status

Address mark detection circuitry is internal to the FDC
which simplifies the phase-locked loop and read electronics. The track stepping rate, head load time, and head
unload time are user-programmable. The FDC765A/
FDC7265 offers additional features such as multi-track and
mUlti-side read and write commands and single and double
density capabilities.

Hand-shaking signals are provided in the FDC765A/
FDC7265 which make DMA operation easy to incorporate
with the aid of an external DMA controller chip. The FDC
will operate in either the DMA or non-DMA mode. In the nonDMA mode the FDC generates interrupts to the processor

459
----------------------------------

ORO

6ACi<

READY
WRITE PROTECT/TWO SIDE
FAULT/TRACK 0

RESET

UNITSELECT 1
MFM MODE
AWISEEK
HEAD LOAD
HEADSELECT

Vee

LOW CURRENT/DIRECTION
FAULT RESET/STEP

BLOCK DIAGRAM

8080 SYSTEM BUS

D80-7

AO

MEMR

080-7

TCi'R

AD

MEMW

We

lOW

CS

CS

INT

HRO

RESET

HLDA

READ

ORO

OMA
CONTROLLER

FDC 765
FDC 7265
TC
TERMINAL
COUNT

SYSTEM CONFIGURATION

160

DESCRIPTION OF PIN FUNCTIONS
PIN
SYMBOL
RST

2

Reset

INPUT/
OUTPUT
Input

CONNECTION
TO
Processor

RD

Read

InputCD

Processor

3

WR

Write

InputCD

Processor

4

CS

Chip Select

Input

Processor

5

Ao

Data/Status Reg
Select

InputCD

Processor

DBo-DB,

Data Bus

Processor

14

DRQ

15

DACK

Data DMA
Request
DMA
Acknowledge

InputCD
Output
Output
Input

DMA

16

TC

Terminal Count

Input

DMA

17

lOX

Index

Input

FDD

18

INT

Interrupt

Output

Processor

19

CLK

Clock

Input

20
21

GND
WCK

Ground
Write Clock

Input

22

ROW

Input

Phase Lock Loop

23

ROD

Read Data
Window
Read Data

Input

FDD

24

VCO

VCO Sync

Output

Phase Lock Loop

25
26

WE
MFM

Write Enable
MFM Mode

Output
Output

FDD
Phase Lock Loop

27

HD

Head Select

Output

FDD

28,29
30
31,32

US" USo
WDA

Unit Select
Write Data
Precompensation
(pre-shift)

Output
Output
Output

FDD
FDD
FDD

33

FLTITRo

FaultlTrack 0

Input

FDD

34

WP/TS

Write Protect/
Two-Side

Input

FDD

NO.
1

6-13

PS" PSo

NAME

DMA

461

FUNCTION
Places FDC in idle state. Resets
output lines to FDD to "0" (low).
Does not effect SRT, HUT or HLT
in Specify command. If ROY pin is
held high during Reset, FDC will
generate interrupt 1 .024 ms later.
To clear this interrupt use Sense
Interrupt Status command.
Control signal for transfer of data
from FDC to Data Bus, when
"O"(low).
Control signal for transfer of data to
FDC via Data Bus, when "0" (low).
IC selected when~' (low),
allowing RD and WR to be
enabled.
Selects Data Reg (Ao = 1) or
Status Reg (Ao = 0) contents of
the FDC to be sent to Data Bus.
Bi-Directional 8-Bit Data Bus.
DMA Request is being made by
FDC when DRW = "1'.
DMA cycle is active when "0" (low)
and Controller is performing DMA
transfer.
Indicates the termination of a DMA
transfer when "1" (high). It
terminates data transfer during
Read/Write/Scan command in
DMA or interrupt mode.
Indicates the beginning of a disk
track.
Interrupt Request Generated by
FOC.
Single Phase 8 MHz Squarewave
Clock.
D.C. Power Return.
Write data rate to FDD. FM = 500
kHz, MFM = 1 MHz, with a pulse
width of 250 ns for both FM and
MFM.
Generated by PLL, and used to
sample data from FDD.
Read data from FDD, containing
clock and data bits.
Inhibits VCO in PLL when "0"
(low), enables VCO when "1."
Enables write data into FDD.
MFM mode when "1," FM mode
when "0."
Head 1 selected when "1" (high).
Head 2 selected when "0" (low).
FDD Unit Selected.
Serial clock and data bits to FDD.
Write precompensation status
during MFM mode. Determines
early, late, and normal times.
Senses FDD fault condition, in
Read/Write mode; and Track 0
condition in Seek mode.
Senses Write Protect status in
Read/Write mode; and Two Side
Media in Seek mode.

I

DESCRIPTION OF PIN FUNCTIONS
PIN
SYMBOL

NO.

INPUTI
OUTPUT

NAME

CONNECTION
TO

35

RDY

Ready

Input

FDD

36

HDL

Head Load

Output

FDD

37

FRISTP

Fit Reset/Stop

Output

FDD

38

LCT/DIR

Low Current/
Direclion

Output

FDD

39

RW/SEEK

Read Write/SEEK

Output

FDD

40

Vee

+5V

FUNCTION
Indicates FDD is ready to send or
receive data.
Command which causes readl
write head in FDD to contact
diskette.
Resets fault F.F. in FDD in Readl
Write mode, contains stop pulses
to move head to another cylinder in
Seek mode.
Lowers Write current on inner
tracks in Read/Write mode,
determines direction head will stop
in Seek mode. A fault reset pulse is
issued at the beginning of each
Read or Write command prior to
the occurrence of the Head Load
signal.
When "1" (high) Seek mode
selected and when "0" (low) Read/
Write mode selected.
DC Power.

Note: (j) Disabled when CS = 1.

DESCRIPTION OF INTERNAL REGISTERS

facilitate the transfer of data between the processor and

The FDG765A/7265 contains two registers which may be
accessed by the main system processor; a Status Register
and a Data Register. The 8-bit Main Status Register contains the status information of the FDG, and may be
accessed at any time. The 8-bit Data Register (actually
consists of several registers in a stack with only one register
presented to the data bus at a time), which stores data,
commands, parameters, and FDD status information. Data
bytes are read out of, or written into, the Data Register in
order to program or obtain the results after a particular command. The Status Register may only be read and used to

The relation~ between the Status/Data registers and the
signals RD, WR, and Ao is shown below.

FOG.

Ao
0
0
0
1
1
1

RD
0
1
0
0
0
1

WR
1
0
0
0
1
0

FUNCTION
Read Main Status Register
Illegal
Illegal
Illegal
Read from Data Register
Write into Data Register

The bits in the Main Status Register are defined as follows:
BIT NUMBER
DBo

NAME
FDDO Busy

SYMBOL
DoB

DB,

FDD 1 Busy

D,B

DB,

FDD2 Busy

D,B

DB,

FDD3 Busy

D,B

DB4

FDC Busy

CB

DBs

Execution Mode

EXM

DB6

Data Input/Output

DIO

DB,

Request for Master

RaM

DESCRIPTION
FDD number 0 is in the Seek mode. If any of the bits is set
FDC will not accept read or write command.
FDD number 1 is in the Seek mode. If any of the bits is set
FDC will not accept read or write command.
FDD number 2 is in the Seek mode. If any of the bits is set
FDC will not accept read or write command.
FDD number 3 is in the Seek mode. If any of the bits is set
FDC will not accept read or write command.
A read or write command is in process. FDC will not accept
any other command.
This bit is set only during execution phase in non-DMA mode.
When DBs goes low, execution phase has ended, and result
phase was started. It operates only during NON-DMA mode
of operation.
Indicates direction of data transfer between FDC and Data
Register. "DIO = "1" then transfer is from Data Register to
the Processor. " DIO = "0", then transfer is from the
Processor to Data Register.
Indicates Data Register is ready to send or receive data to or
from the Processor. Both bits DIO and RaM should be used
to perform the hand-shaking functions of "ready" and
"direction" to the processor.

The 010 and RaM bits in the Status ~ister indicate when Data is ready and in which direction data will be transferred on the Data
Bus. The max time between the last RD or WR during command or result phase and 010 and RaM getting set or reset is 12 fLuor
this reason every time Main Status Register is read the CPU should wait 12 fLS. The max time from the trailing edge of the last RD in
the result phase to when DB, (FDC Busy) goes low is 12 fLS.

462

COMMAND SEQUENCE
Out FDC and Into Processor
Data In/Out

1010)

L

Oul Processor and Into FoC

Request for Master
(ROM)

I

!:
rn
I I i r:
HiHI:~III!1

Ready

1111 Not 1 1

:~
I

I

1

i L4

i

I

I

I

I I

I

I

I I

I

WR-h~~1
-

L...l i i i

i

RO~:

I A I 8I

A

181

A

I c I 0 I c 10181 A I

Notes: ~ -Data register ready to be written into by processor

rID -Data register not ready to be written into by processor

@] -Data register ready for next data byte to be read by the processor
[Q] -Data register not ready for next data byte to be read by processor

The FOC is capable of performing 15 difierent commands.
Each command is initiated by a mUlti-byte transfer from the
processor, and the result after execution of the command
may also be a multi-byte transfer back to the processor.
Because of this multi-byte interchange of information
between the FOC and the processor, it is convenient to consider each command as consisting of three phases:
Command Phase:
The FOC receives all information
required to perform a particular
operation from the processor.
Execution Phase:
The FOC performs the operation
it was instructed to do.
Result Phase:
After completion of the operation,
status and other housekeeping
information are made available to
the processor.

COMMAND SYMBOL DESCRIPTION
SYMBOL

NAME

A,

Address Line 0

C

Cylinder Number

D
0 7 -0 0

Data
Data Bus

DTL

Data Length

EOT

End of Track

GPL

Gap Length

H
HD

Head Address
Head

HLT

Head Load Time

HUT

Head Unload Time

MF
MT

FM or MFM Mode
Multi-Track

N
NCN

Number
New Cylinder Number

NO
PCN
R
R/W
SC
SK
SRT

Non-DMA Mode
Present Cylinder
Number
•
Record
Read/Write
Sector
Skip
Step Rate Time

STO
STI
ST2
ST3

Status 0
Status 1
Status 2
Status 3

STP
USO, US1

Unit Select

DESCRIPTION

Ao controls selection of Main Status Register (Ao = 0) or Data Register
(Ao = 1).
C stands for the current/selected Cylinder (track) number 0 through 76 of
the medium.
o stands for the data pattern which is going to be written into a Sector.
B-bit Data Bus, where 0, stands for a most significant bit, and Do stands for a
least significant bit.
When N is defined as 00, DTL stands for the data length which users are
going to read out or write into the Sector.
EOT stands for the final Sector number on a Cylinder. During Read or Write
operation FDC will stop data transfer after a sector # equal to EOT.
GPL stands for the length of Gap 3. During Read/Write commands this value
determines the number of bytes that VCOs will stay low after two CRC bytes.
During Format command it determines the size of Gap 3.
H stands for head number 0 or 1, as specified in ID field.
HD stands for a selected head number 0 or 1 and controls the polarity of pin
2.7. (H = HD in all command words.)
HLT stands for the head load time in the FDD (2 to 254 ms in 2 ms
increments).
HUT stands for the head unload time after a read or write operation has
occurred (16 to 240 ms in 16 ms increments).
If MF is low, FM mode is selected, and if it is high, MFM mode is selected.
If MT is high, a multi-track operation is to be performed. If MT = 1" after
finishing Read/Write operation on side 0 FDC will automatically start
searching for sector 1 on side 1.
N stands for the number of data bytes written in a Sector.
NCN stands for a new Cylinder number, which is going to be reached as a
result of the Seek operation. Desired position of Head.
NO stands for operation in the Non-DMA Mode.
PCN stands for the Cylinder number at the completion of SENSE
INTERRUPT STATUS Command. Position of Head at present time.
R stands for the Sector number, which will be read or written.
R/W stands for ei.ther Read (R) or Write (W) signal.
SC indicates the number of Sectors per Cylinder.
SK stands for Skip Deleted Data Address Mark.
SRT stands for the Stepping Rate for the FDD. (1 to 16 ms in 1 ms
increments.) Stepping Rate applies to all drives, (F = 1 ms, E = 2 ms, etc.).
ST 0-3 stand for one of four registers which store the status information after
a command has been executed. This information is available during the
result phase after command execution. These registers should not be
confused with the main status register (selected by Ao = 0). ST 0-3 may be
read only after a command has been executed and contain information
relevant to that particular command.
During a Scan operation, if STP = 1, the data in continguous sectors is
compared byte by byte with data sent from the processor (or DMA); and if
STP= 2, then alternate sectors are read and compared.
US stands for a selected drive number 0 or 1.

463

I

INSTRUCTION SET  R), and the scan operation is continued. The scan operation continues until one
of the following conditions occur; the conditions for scan are
met (equal, low, or high), the last sector on the track is
reached (EaT), or the terminal count signal is received.

467

If the conditions for scan are met then the FDC sets the SH
(Scan Hit) flag Status Register 2 to a 1 (high), and terminates the Scan Command. If the conditions for scan are not
met between the starting sector (as specified by R) and the
last sector on the cylinder (EaT), then the FDC sets the SN
(Scan Not Satisfied) flag of Status Register 2 to a 1 (high),
and terminates the Scan Command. The receipt of a TERMINAL COUNT signal from the Processor or DMA Controller during the scan operation will cause the FDC to
complete the comparison of the particular byte which is in
process, and then to terminate the command. Table 4 shows
the status of bits SH and SN under various conditions of
SCAN.
COMMAND
Scan Equal

STATUS REGISTER 2
BIT2 = SN BIT3 = SH

a

1

1

Scan Low or
Equal

a
a

Scan High or
Equal

a
a

'=*

DpROCESSOR

DFOO

i

DFOo

DpROCESSOA

DFDD

DpROCESSOR

1

a
a

1

DFDD

a
a
a

1

COMMENTS

=
<
DFOO >
DFOO =
DFDo >
DFOD <

DpRocEssoR

DpROCESSOR

DpRocEssOR
DpROCESSOR

DpROCESSOR

Table 4
If the FDC encounters a Deleted Data Address Mark on one
of the sectors (and SK = 0), then it regards the sector as
the last sector on the cylinder, sets CM (Control Mark) flag
of Status Register 2 to a 1 (high) and terminates the command. If SK = 1, the FDC skips the sector with the Deleted
Address Mark, and reads the next sector. In the second case
(SK = 1), the FDC sets the CM (Control Mark) flag of Status Register 2 to a 1 (high) in order to show that a Deleted
Sector had been encountered.
When either the STP (contiguous sectors = 01, or alternate sectors = 02 sectors are read) or the MT (Multi-Track)
are programmed, it is necessary to remember that the last
sector on the track must be read. For example, if STP = 02,
MT = 0, the sectors are numbered sequentially 1 through
26, and we start the Scan Command at sector 21 ; the following will happen. Sectors 21,23 and 25 will be read, then
the next sector (26) will be skipped and the Index Hole will
be encountered before the EaT value of 26 can be read.
This will result in an abnormal termination of the command.
If the EOT has been set at 25 or the scanning started at
sector 20, then the Scan Command would be completed in
a normal manner.
During the Scan Command data is supplied by either the
processor or DMA Controller for comparison against the
data read from the diskette. In order to avoid having the OR
(Over Run) flag set in Status Register 1, it is necessary to
have the data available in less than 27 flos (FM Mode) or 13
flos (MFM Mode). If an Overrun occurs the FDC ends the
command with bits 7 and 6 of Status Register 0 set to 0 and
1, respectively.

Seek
The read/write head within the FDD is moved from cylinder
to cylinder under control of the Seek Command. FDC has
four independent Present Cylinder Registers for each drive.
They are clear only after Recalibrate command. The FDC
compares the PCN (Present Cylinder Number) which is the
current head position with the NCN (New Cylinder Number), and if there is a difference performs the following
operation:
PCN < NCN: Direction signal to FDD set to a 1 (high),
and Step Pulses are issued. (Step In.)
PCN> NCN: Direction signal to FDDsettoaO (low), and
Step Pulses are issued. (Step Out.)

The rate at which Step Pulses are issued is controlled by
SRT (Stepping Rate Time) in the SPECIFY Command. After
each Step Pulse is issued NCN is compared against PCN,
and when NCN = PCN, then the SE (Seek End) flag is set
in Status Register 0 to a 1 (high), and the command is terminated. At this paint FDC interrupt goes high. Bits DBoDB3 in Main Status Register are set during seek operation
and are cleared by Sense Interrupt Status command.
During the Command Phase of the Seek operation the FDC
is in the FDC BUSY state, but during the Execution Phase
it is in the NON BUSY state. While the FDC is in the NON
BUSY state, another Seek Command may be issued, and
in this manner parallel seek operations may be done on
up to 4 Drives at once. No other command could be issued
for as long as FDC is in process of sending Step Pulses to
any drive.
If an FDD is in a NOT READY state at the beginning of the
command execution phase or during the seek operation,
then the NR (NOT READY) flag is set in Status Register 0
to a 1 (high), and the command is terminated after bits 7
and 6 of Status Register 0 are set to 0 and 1 respectively.
If the time to write 3 bytes of seek command exceeds 150
flos, the timing between first two Step Pulses may be shorter
than set in the Specify command by as much as 1 ms.

Recalibrate
The function of this command is to retract the read/write
head within the FDD tothe Track 0 position. The FDC clears
the contents of the PCN counter, and checks the status of
the Track 0 signal from the FDD. As long as the Track 0 signal is low, the Direction signal remains 0 (low) and Step
Pulses are issued. When the Track 0 signal goes high, the
SE (SEEK END) flag in Status Register 0 is set to a 1 (high)
and the command is terminated. If the Track 0 signal is still
low after 77 Step Pulses have been issued, the FDC sets
the SE (SEEK END) and EC (EQUIPMENT CHECK) flags
of Status Register 0 to both 1s (highs), and terminates the
command after bits 7 and 6 of Status Register 0 is set to 0
and 1 respectively.
The ability to do overlap RECALIBRATE Commands to
multiple FDDs and the loss of the READY signal, as
described in the Seek Command, also applies to the
RECALIBRATE Command.

Sense Interrupt Status
An Interrupt signal is generated by the FDC for one of the
following reasons:
1. Upon entering the Result Phase of:
a. Read Data Command
b. Read a Track Command
c. Read 10 Command
d. Read Deleted Data Command
e. Write Data Command
f. Format a Cylinder Command
g. Write Deleted Data Command
h. Scan Commands
2. Ready Line of FDD changes state
3. End of Seek or Recalibrate Command
4. During Execution Phase in the NON-DMA Mode
Interrupts caused by reasons 1 and 4 above occur during
normal command operations and are easily discernible by
the processor. During an execution phase in NON-DMA
Mode, DB5 in Main Status Register is high. Upon entering
Result Phase this bit gets clear. Reason 1 and 4 does not
require Sense Interrupt Status command. The interrupt is
cleared by reading/writing data to FDC. Interrupts caused
by reasons 2 and 3 above may be uniquely identified with
the aid of the Sense Interrupt Status Command. This com-

468
----,----

mand when issued resets the interrupt signal and via bits
5, 6, and 7 of Status Register 0 identifies the cause of the
interrupt.
SEEK
END
BITS5

a

INTERRUPT
CODE
BIT6
BIT7
1
1

1

a

a

1

1

a

CAUSE
Ready Line changed state, either
polarity
Normal Termination of Seek or
Recalibrate Command
Abnormal Termination of Seek or
Recalibrate Command

ms in increments of 2 ms (01 = 2 ms, 02 = 4 ms, 03 = 6
ms ... 7F = 254 ms).
The time intervals mentioned above are a direct function of
the clock (ClK on pin 19). Times indicated above are for an
8 MHz clock, if the clock was reduced to 4 MHz (mini-floppy
application) then all time intervals are increased by a factor
of 2.
The choice of OMA or NON-OMA operation is made by the
NO (NON-OMA) bit. When this bit is high (NO = 1) the NONOMA mode is selected, and when NO = 0 the OMA mode
is selected.

Sense Drive Status

TableS
Neither the Seek or Recalibrate Command have a Result
Phase. Therefore, it is mandatory to use the Sense Interrupt Status Command after these commands to effectively
terminate them and to provide verification of where the head
is positioned (PCN).
Issuing Sense Interrupt Status Command without interrupt
pending is treated as an invalid command.

Specify
The Specify Command sets the initial values for each of the
three internal timers. The HUT (Head Unload Time) defines
the time from the end of the Execution Phase of one of the
ReadlWrite Commands to the head unload state. This timer
is programmable from 16 to 240 ms in increments of 16 ms
(01 = 16 ms, 02 = 32 ms ... OF = 240 ms).The SRT (Step
Rate Time) defines the time interval between adjacent step
pulses. This timer is programmable from 1 to 16 ms in increments of 1 ms (F = 1 ms, E = 2 ms, 0 = 3 ms, etc.). The
HlT (Head load Time) defines the time between when the
Head load signal goes high and when the Read/Write
operation starts. This timer is programmable from 2 to 254

This command may be used by the processor whenever it
wishes to obtain the status of the FOOs. Status Register 3
contains the Drive Status information stored internally in
FOC registers.

Invalid
If an invalid command is sent to the FOC (a command not
defined above), then the FOC will terminate the command
after bits 7 and 6 of Status Register 0 are set to 1 and 0
respectively. No interrupt is generated by the FOC765A
during this condition. Bit 6 and bit 7 (010 and RQM) in the
Main Status Register are both high ("1") indicating to the
processor that the FOC is in the Result Phase and the contents of Status Register 0 (STO) must be read. When the
processor reads Status Register 0 it will find an 80 hex indicating an invalid command was received.
A Sense Interrupt Status Command must be sent after a
Seek or Recalibrate Interrupt, otherwise the FOC will consider the next command to be an Invalid Command.
In some applications the user may wish to use this command as a No-Op command, to place the FOC in a standby
or no operation state.

STATUS REGISTER IDENTIFICATION
NO.

07

BIT
NAME
Interrupt Code

SYMBOL
IC

06

DESCRIPTION

07

= a and 0, = a

Normal Termination of Command, (NT). Command was completed
and properly executed.
0 7 = and 0, = 1
Abnormal Termination of Command, (AT).
Execution of Command was started, but was not successfully
completed.
0 7 = 1 and 0, =
Invalid Command issue, (IC). Command which was issued was
never started.
0 7 = 1 and 0, = 1
Abnormal Termination because during command execution the
ready signal from FOO changed state.
When the FOC completes the SEEK Command, this flag is set to
1 (high).
If a fault Signal is received from the FOO, or if the Track Signal
fails to occur after 77 Step Pulses (Recalibrate Command) then this
flag is set.
When the FOO is in the not-ready state and a read or write
command is issued, this flag is set. If a read or write command is
issued to Side 1 of a single sided drive, then this flag is set.
This flag is used to indicate the state of the head at Interrupt.

a

a

Os

Seek End

SE

0,

Equipment Check

EC

03

Not Ready

NR

0,
0,
00

Head Address
Unit Select 1
Unit Select

a

HO
US 1

usa

a

These flags are used to indicate a Orive Unit. Number at Interrupt.

469

I

BIT
NAME

NO.

0,

End of Cylinder

06
05

Data Errror

04

OverRun

03
0,

No Data

0,

Not Writable

Do

Missing Address Mark

0,
06

Control Mark

05
04

Data Error in Data Field
Wrong Cylinder

03

Scan Equal Hit

0,

Scan Not Satisfied

0,

Bad Cylinder

Do

Missing Address Mark
in Data Field

0,

Fault

0,

Write Protected

05

Ready

04

Track 0

03

Two Side

0,

Head Address

0,

Unit Select 1

Do

Unit Select 0

DESCRIPTION
SYMBOL
STATUS REGISTER 1 (CO NT.)
When the FDC tries to access a Sector beyond the final Sector of a
EN
Cylinder, this flag is set.
Not used. This bit is always 0 (low).
When the FDC detects a CRC error in either the 10 field or the data
DE
field, this flag is set.
If the FDC is not serviced by the main-systems during data
OR
transfers, within a certain time interval, this flag is set.
Not used. This bit always 0 (low).
During execution of READ DATA, WRITE DELETED DATA or
NO
SCAN Command, if the FDC cannot find the Sector specified in the
lOR Register, this flag is set.
During executing the READ 10 Command, if the FDC cannot read
the 10 field without an error, then this flag is set.
During the execution of the READ A Cylinder Command, if the
starting sector cannot be found, then this flag is set.
During execution of WRITE DATA, WRITE DELETED DATA or
Format A Cylinder Command, if the FDC detects a write protect
signal from the FDD, then this flag is set.
If the FDC cannot detect the 10 Address Mark after encountering
MA
the index hole twice, then this flag is set.
If the FDC cannot detect the Data Address Mark or Deleted Data
Address Mark, this flag is set. Also at the same time, the MD
(Missing Address Mark in Data Field) of Status Register 2 is set.
STATUS REGISTER 2
Not used. This bit is always 0 (low).
During executing the READ DATA or SCAN Command, if the FDC
CM
encounters a sector which contains a Deleted Data Address Mark,
this flag is set.
If the FDC detects a CRC error in the data field then this flag is set.
DO
This bit is related with the NO bit, and when the contents of C on the
WC
medium is different from that stored in the lOR, this flag is set.
During execution, the SCAN Command, if the condition of "equal"
SH
is satisfied, this flag is set.
During executing the SCAN Command, if the FDC cannot find a
SN
Sector on the cylinder which meets the condition, then this flag
is set.
This bit is related with the NO bit, and when the content of C on the
BC
medium is different from that stored in the lOR and the content of C
is FF, then this flag is set.
When data is read from the medium, if the FDC cannot find a Data
MD
Address Mark or Deleted Data Address Mark, then this flag is set.
STATUS REGISTER 3
This bit is used to indicate the status of the Fault signal from
FT
the FDD.
This bit is used to indicate the status of the Write Protected signal
WP
from the FDD.
This bit is used to indicate the status of the Ready signal from
RY
theFDD.
TO
This bit is used to indicate the status of the Track 0 signal from
theFDD.
This bit is used to indicate the status of the Two Side signal from
TS
the FDD.
This bit is used to indicate the status of Side Select Signal
HD
to the FDD.
This bit is used to indicate the status of the Unit Select 1 signal
US1
to the FDD.
This bit is used to indicate the status of the Unit Select 0 signal
usa
to the FDD.
NW

470

PROCESSOR INTERFACE
During Command or Result Phases the Main Status Register (described earlier) must be read by the processor
before each byte of information is written into or read from
the Data Register. After each byte of data read or written to
Data Register, CPU should wait for 12 fLs before reading
MSR. Bits 06 and 07 in the Main Status Register must be
in a 0 and 1 state, respectively, before each byte of the command word may be written in the FOC. Many of the commands require multiple bytes, and as a result the Main Status
Register must be read prior to each byte.transfer to the FOC.
On the other hand, during the Result Phase, 06 and 07 in
the Main Status Register must both be 1's (06 = 1 and 07
= 1) before reading each byte from the Data Register. Note,
this reading of the Main Status Register before each byte
transfer to the FOC is required in only the Command and
Result Phases, and NOT during the Execution Phase.
During the Execution Phase, the Main Status Register need
not be read. If the FOC is in the NON-OMA Mode, then the
receipt of each data byte (if FOC is reading data from FOO)
is indicated by an Interrupt sigm!1 on pin 18 (INT = 1). The
generation of a Read signal (RO = 0) or Write signal (WR
= 0) will reset the Interrupt as well as output the Data onto
the Data bus. If the processor cannot handle Interrupts fast
enough (every 13 fLS) for MFM and 27 fLs for FM mode, then
it may poll the Main Status Register and then bit 07 (ROM)
functions just like the Interrupt signal. If a Write Command
is in process then the WR signal performs the reset to the
Interrupt signal.
If the FOC is in the OMA Mode, no Interrupts are generated
during the Execution Phase. The FOC generates ORa's
(OMA Requests) when each byte of data is available. The
OMA Controller responds to this remest with both a OACK
= 0 (OMA Acknowledge) and a RO = 0 (Read signal).
When the OMA Acknowledge signal goes low (OACK = 0)
then the OMA Request is reset (ORO = 0). If a Write Command has been programmed then a WR signal will appear
instead of RD. After the Execution Phase has been completed (Terminal Count has occurred) or EaT sector was
read/written, then an Interrupt will occur (INT = 1). This signifies the beginning of the Result Phase. When the first byte
of data is read during the Result Phase, the Interrupt is
automatically reset (INT = 0).

It is important to note that during the Result Phase all bytes
shown in the Command Table must be read. The Read Data
Command, for example has seven bytes of data in the Result
Phase, All seven bytes must be read in order to successfully complete the Read Data Command. The FOC will not
accepta new command until all seven bytes have been read.
Other commands may require fewer bytes to be read during
the Result Phase.
The FOC contains five Status Registers. The Main Status
Register mentioned above may be read by the processor at
any time. The other four Status Registers (STO, ST1, ST2,
and ST3) are only available during the Result Phase, and
may be read only after completing a command. The particular command which has been executed determines how
many of the Status Registers will be read.
The bytes of data which are sent to the FOC to form the
Command Phase, and are read out of the FOC in the Result
Phase, must occur in the order shown in the Command
Table. That is, the Command Code must be sent first and
the other bytes sent in the prescribed sequence. No foreshortening of the Command or Result Phases are allowed.
After the last byte of data in the Command Phase is sent to
the FOC, the Execution Phase automatically starts. In a
similar fashion, when the last byte of data is read out in the
Result Phase, the command is automatically ended and the
FOC is ready for a new command.

POLLING FEATURE OF THE FDC765A/7265
After the Specify command has been sent to the FOC, the
Unit Select line USO and US1 will automatically go into a
polling mode. In between commands (and between step
pulses in the SEEK command) the FOC polls all four FOO's
looking for a change in the Ready line from any of the drives.
If the Ready line changes state (usually due to a door opening or closing) then the FOC will generate an interrupt. When
Status Register 0 (STO) is read (after Sense Interrupt Status is issued), Not Ready (NR) will be indicated. The polling
of the Ready line by the FOC occurs continuously between
commands, thus notifying the processor which drives are
on or off line. Each drive is polled every 1.024 ms except
during the Read/Write commands.

AC TEST CONDITION
INPUT/OUTPUT

CLOCK

2.4V

3.0V----,.

O.3V _ _ _J

0.45V

ACTESTING
Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0." Timing measurements are made at 2.0V for a logic "1" and O.8V for a logic "0,"
Clocks are driven at 3.OV for a logic "1" and O.3V for a logic "0." Timing measurements are made at 2.4V for a logic "1" and O.65V for a logic "0."

471

TIMING DIAGRAMS

Fi:>D WR.iiE OPERATION

PROCESSOR READ OPERATION

f--To
I
WRITE CLOCK

1 1'\ 1

"~~TF,
TR ....:

WRITE ENABLE

I

.. ' I

I--'-TCy----j

:-+-r---""'-i'r-.:.I----"-~--__,

L

~:

1 1

~

I

t--TCP

~----""!E'"
.
V
PRESHIFT 0 OR '-.A'----_T>t::;
..._:;I:.;. . .__..JX\,.·
...-_ _I
L--I

1
WRITE DATA

I
1

I

00

I

1

I

~

~TWDD

I

~ I '>0 I 1_ _ ¢Cy----.J

"R~~'~"
I

~TCO

~~?F

I

PRESHIFTO

WRITE CLOCK

NORMAL

0

LATE

,
,

,
,
0

0

EARLY

eLK

INVALID

PRESHrFT 1

0

ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS'
Operating Temperature. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . .. . . . . .. . . . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. - 10°C to + 70°C
Storage Temperature ........... , .............................................................................. - 55°c to + 150°C
All Output Voltages ............................................................................................ - 0.5 to + 7 Volts
All Input Voltages ............................................................................................. - 0.5 to + 7 Volts
Supply Voltage Vee ........................................... , ................................................ - 0.5 to + 7 Volts
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ....................... , ............................................. 1 Watt
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditiDns fDr extended periods may affect device reliability.

DC CHARACTERISTICS Ta

= O°C to + 70oe; Vcc = + 5V

PARAMETER
Input Low Voltage
Input High Voltage
Output low Voltage
Output High Voltage
Input low Voltage
(ClK + WR Clock)
Input High Voltage
(ClK + WR Clock)
Vee Supply Current

SYMBOL
Vile
V,H

VOL
VOH

± 5% unless otherwise specified.

MIN
-0.5

LIMITS
TYPeD

2.b

V1L(dJ)

2.4
-0.5

VIH(~»)

2.4

V

Vee

0.5

150
10
-10
10
-10

III

ILOH

High level Output leakage Current
low level Output leak<;lge Current

+

Vee + 0.5
0.45

Icc

Input load Current
(All Input Pins)

Vee
0.65

UNIT
V
V
V
V
V

MAX
O.S

ILOl

mA
[LA
[LA
[LA
fJ-A

TEST
CONDITIONS

10L = 2.0 mA
10H = - 200 [LA

ViN

=

Vee

V,N = OV

VOUT

=

VOUT =

Vee

+ 0.45V

NOTE: eDTypical values for T, = 25°C and nominal supply voltage.

CAPACITANCE Ta = 25°C; fe = 1 MHz; Vcc = OV
PARAMETER
Clock Input CapaCitance
Input Capacitance
Output CapaCitance

SYMBOL

MIN

C'N1,bl
C'N
COUT

472

LIMITS
TYP

MAX
20
10
20

UNIT
pF
pF
pF

TEST
CONDITIONS
All Pins Except Pin
Under Test Tied to
ACGround

AC CHARACTERISTICS T, = -10°C to + 70°C; Vee = + 5V ± 5% unless otherwise specified,
LIMITS
PARAMETER
Clock Period
Clock Active (High, low)
Clock Rise Time
Clock Fall Time
Aa, CS, iSACR Set Up Time to RD

SYMBOL


RCLK

AO

RG

A1

LATE

EARLY

CS
C

WD

Ai"

0
M
P
U
T
E
R

0

MR

P
P
Y

10K
WG

FLOPPY DISK

CONTROLLER!

I
N
T
E
R
F
A
C
E

F
L

+5

WE:

D
I
S
K

WPRT

FORMATTER

WF/'iJF"Q'E

+5V

t

D
R
I
V
E

IP
TROQ

10K>

;

READY

(>'0K

$

DRO

TG43

STEP

INTRO

DIRe

ClK

+5V

SYSTEM BLOC K DIAGRAM

'IDDEN

HlD

1

HLT
GND

Voo

v"

+12

+5V

,. 1 t t
478

f---e

;
+5V

-l

ONE SHOT
(IF USED)

I

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

NAME

SYMBOL

FUNCTION

1

NO CONNECTION

NC

This pin is internally connected to the substrate bias generator and
must be left open.

20

GROUND

Vss

Ground

21

POWER SUPPLY

Vee

+5V

40

POWER SUPPLY

Voo

+12V

19

MASTER RESET

MR

A logic low on this input resets the device and loads HEX 03 into
the command regislli.L.The Not Ready (Status Bit 7) is reset during
MR ACTIVE. When MR is brought to a logic high a Restore
Command is executed, regardless of the state of the Ready signal
from the drive. Also, HEX 01 is loaded into the sector register.

COMPUTER INTERFACE:
2

WRITE ENABLE

WE

A logic low onJhis input gates data on the DAL into the selected
register when CS is low.

3

CHIP SELECT

CS

A logic low on this input selects the chip and the parallel
data bus (DAL).

4

READ ENABLE

RE

A logic low on this input controls the placement of data from a
selected register on DALIif-DAL7 when CS is low.

5,6

7-14

REGISTER SELECT
LINES

DATA ACCESS LINES

AO, A1

DALODAL7

These inputlielect the register to
lines under RE and WE control:
A1
AO
RE
0
Status Reg
0
0
1
Track Reg
1
0
Sector Reg
1
1
Data Reg

receive/transfer data on the DAL
WE
Command Reg
Track Reg
Sector Reg
Data Reg

Eight bit Bidirectional bus used for trans.fgLof data, control, and
status, This...ill!s is a receiver enabled by WE or a transmitter
enabled by RE. The Data Bus is inverted on the FDC 1791, FDC 1792
and FOC 1795.

24

CLOCK

CLK

This input requires a free-running square wave clock for internal
timing reference, 2 MHz for 8" drives, 1 MHz for 5'1<" drives,

38

DATA REQUEST

DRQ

This open drain output indicates that the DR contains assembled
data in Read operations, or the DR is empty in Write operations,
This signal is reset when serviced by the computer through reading
or loading the DR in Read or Write operations, respectively, Use a
10K pull-up resistor to +5V.

39

INTERRUPT REQUEST

INTRQ

This open drain output is set at the completion or termination
of any operation and is reset when a new command is loaded into
the command register or the status register is read. Use a 10K
pull-up resistor to +5V.

FLOPPY DISK INTERFACE:
15

STEP

STEP

Step and direction motor control. The step output contains a pulse
for each step.

16

DIRECTION

DIRC

Direction Output is active high when stepping in, active low when
stepping out.

17

EARLY

EARLY

Indicates that the write data pulse occurring while Early is active
(high) should be shifted early for write precompensation.

18

LATE

LATE

Indicates that the write data pulse occurring while Late is active
(high) should be shifted late for write precompensation.

22

TEST

TEST

This input is used for testing purposes only and should be tied to
+5V or left open by the user unless interfacing to voice coil
actuated motors.

23

HEAD LOAD TIMING

HLT

When a logic high is found on the HLT input the head is assumed
to be engaged.

---

479

I

SYMBOL

FUNCTION

RG

A high level on this output indicates to the data separator circuitry
that a field of zeros (or ones) has been encountered, and is used
for synchronization.

SSO

The logic level of the Side Select Output is directly controlled by
the'S' flag in Type II or III commands. When S=1, SSO is set to
a logic 1. When S =0, SSO is set to a logic O. The Side Select Output
is only updated at the beginning of a Type II or III command. It is
forced to a logic 0 upon a MASTER RESET condition.

REAP CLOCK

RCLK

A nominal square-wave clock signal derived from the data stream
must be provided to this input. Phasing (i.e. RCLK transitions)
relative to RAW READ is important but polarity (RCLK high or low)
is not.

27

RAW READ

RAW
READ

The data input signal directly from the drive. This input shall be a
negative pulse for each recorded flux transition.

28

HEAD LOAD

HLD

The HLD output controls the loading of the Read-Write head
against the media.

29

TRACK GREATER
THAN 43

TG43

This output informs the drive that the Read/Write head is positioned
between tracks 44-76. This output is valid only during Read and
Write Commands.

30

WRITE GATE

WG

This output is made valid before writing is to be performed
on the diskette.

31

WRITE DATA

WD

A 250 ns (MFM) or 500 ns (FM) pulse perflux transition. WD contains
the unique Address marks as well as data and clock in both FM and
MFM formats.

32

READY

READY

This input indicates disk readiness and is sampled for a logic high
before Read or Write commands are performed. If Ready is low the
Read or Write operation is not performed and an interrupt is
generated. Type I operations are performed regardless of the state
of Ready. The Ready input appears in inverted format as Status
Register bit 7.

33

WRITE FAULTI
VFO ENABLE

WFIVFOE

This is a bi-directional signal used to signify writing faults at the
drive, and to enable thtlxternal PLO data separator. When WG=1,
Pin 33 functions as a WF input. If WF=O, any write command will
immediately be terminated. When WG=O, Pin 33 functions as a
VFOE output. VFOE will go low during a read operation after the
head has loaded and settled (HLT=1). On the 1795/7, it will remain
low until the last bit of the second CRC byte in the ID field. VFOE
will then go high until 8 bytes (MFM) or 4 bytes (FM) before the
Address Mark. It will then go active until the last bit of the second
CRC byte of the Data Field. On the 1791/3, VFOE will remain low
until the end of the Data Field.

34

TRACK 00

35

INDEX PULSE

36

WRITE PROTECT

WPRT

This input is sampled whenever a Write Command is received.
A logic low terminates the command and sets the Write Protect
Status bit.

37

DOUBLE DENSITY

DDEN

This pin selects either single or double densi~ration. When
DDEN=O, double density is selected. When DDEN=1, single
density is selected. This line must be left open on the 1792/4.

PIN NO.

NAME

25

READ GATE (1791/3)

25

SIDE SELECT OUTPUT
(1795, 1797)

26

TROO
IP

This input informs the FDC179X that the ReadIWrite head is
positioned over Track 00.
This input informs the FDC179X when the index hole is encountered
on the diskette.

480

FUNCTIONAL DESCRIPTION
The FDC 179X-02 major functional blocks are as follows:
Data Shift Register- This a-bit register assembles serial
data from the Read Data input (RAW READ) during
Read operations and transfers serial data to the Write
Data output during Write operations.
Data Register- This a-bit register is used as a holding
register during Disk Read and Write operations. In Disk
Read operations the assembled data byte is transferred
in parallel to the Data Register from the Data Shift
Register. In Disk Write operations information is transferred in parallel from the Data Register to the Data
Shift Register.
When executing the Seek command the Data Register
holds the address of the desired Track position. This
register is loaded from the DAL and gated onto the DAL
under processor control.
Sector Register (SR) - This 8-bit register holds the
address of the desired sector position. The contents
of the register are compared with the recorded sector
number in the ID field during disk Read or Write operations. The Sector Register contents can be loaded from
or transferred to the DAl. This register should not be
loaded when the device is busy.

This register can be read onto the DAL, but not loaded
from the DAL.
CRC Logic- This logic is used to check or to generate
the 16-bit Cyclic Redundancy Check (CRC). The polynomial is: G(X)=X16+X'2+X5+1.
Track Register-This a-bit register holds the track
number of the current Read/Write head position. It is
incremented by one every time the head stepped in
(towards track 76) and decremented by one when the
head is stepped out (towards track 00). The contents
of the register are compared with the recorded track
number in the ID field during disk Read, Write, and
Verify operations. The Track Register can be loaded
from or transferred to the DAL. This Register should not
be loaded when the device is busy.
The CRC includes all information starting with the
address mark and up to the CRC characters. The CRC
register is preset to ones prior to data being shifted
through the circuit.
Arithmetic/Logic Unit (ALU)- The ALU is a serial
comparator, incrementer, and decrementer and is used
for register modification and comparisons with the disk
recorded ID field.
Timing and Control-All computer and Floppy Disk
Interface controls are generated through this logic. The
internal device timing is generated from an external
crystal clock.
AM Detector-The address mark detector detects ID,
data and index address marks during ready and
write operations.

Command Register (CR)- This 8-bit register holds the
command presently being executed. This register should
not be loaded when the device is busy unless the new
command is a Force Interrupt. The command register
can be loaded from the DAL, but not read onto the DAl.
Status Register (STR)- This a-bit register holds device
Status information. The meaning of the Status bits is a
function of the type of command previously executed.

OPERATION
provided by some drives but if not, it may be derived
externally by Phase lock loops, one shots, or counter
techniques. In addition, a Read Gate Signal is provided
as an output (Pin 25) which can be used to inform phase
lock loops when to acquire synchronization. When
reading from the media in FM, RG is made true when
2 bytes of zeroes are detected. The FDC179X must find
an address mark within the next 10 bytes; otherwise RG
is reset and the search for 2 bytes of zeroes begins all
over again. If an address mark is found within 10 bytes,
RG remains true as long as the FDC179X is deriving any
useful information from the data stream. Similarly for
MFM, RG is made active when 4 bytes of "00" or "FF" are
detected. The FDC179X must find an address mark
within the next 16 bytes, otherwise RG is reset and
search resumes.
During read operations (WG=O), the VFOE (Pin 33) is
provided for phase lock loop synchronization. VFOE
will go active when:
a) Both HLT and HLD are True
b) Settling Time, if programmed, has expired
c) The 179X is inspecting data off the disk
If WFIVFOE is not used, leave open or tie to a 10K
resistor to +5.
On Disk Read operations the Data Request is activated
(set high) w'hen an assembled serial input byte is

FDC 1791, FDC 1793, FDC 1795 and FDC 1797 have two
modes of operation according to the state of DDEN
(Pin 37). When DDEN=1, single density is selected. In
either case, the CLK input (Pin 24) is at 2 MHz. However,
when interfacing with the mini-floppy, the CLK input is
set at 1 MHz for both single density and double density.
When the clock is at 2 MHz, the stepping rates of 3, 6,10,
and 15 ms are obtainable. When CLK equals 1 MHz these
times are doubled.
DDEN must be left open forthe FDC 1792 and FDC 1794.
Disk Read Operation
Sector lengths of 128, 256, 512 or 1024 are obtainable
in either FM or MFM formats. For FM, DDEN should be
placed to logical "1." For MFM formats, 5Ii'EN should
be placed to a logical "0." Sector lengths are determined
at format time by a special byte in the "ID" field. If this
Sector length byte in the ID field is zero, then the sector
length is 128 bytes. If 01 then 256 bytes. If 02, then
512 bytes. If 03, then the sector length is 1024 bytes.
The number of sectors per track can be from 1 to 255
sectors. The number of tracks is from 0 to 255 tracks.
For read operations, the FDC 179X requires RAW READ
Data (Pin 27) signal which is a 250 ns pulse per flux
transition and a Read clock (RCLK) signal to indicate
flux transition spacings. The RCLK (Pin 26) signal is
481

~---~~~~~~~~~~~~~~~~~-

I

and 250 ns pulses in MFM (DDEN=O). Write Data provides the unique address marks in both formats.
Also during write, two additional signals are provided
for write precompensation. These are EARLY (Pin 17)
and LATE (Pin 18). EARLY is active true when the WD
pulse appearing on (Pin 30) is to be written early. LATE
is active true when the WD pulse is to be written LATE.
If both EARLY and LATE are low when the WD pulse is
present, the WD pulse is to be written at nominal. Since
write precompensation values vary from disk manufacturer to disk manufacturer, the actual value is
determined by several one shots or delay lines which are
located external to the FDC179X. The write precompensation signals EARLY and LATE are valid for the duration
of WD in both FM and MFM formats.

transferred in parallel to the Data Register. This bit
is cleared when the Data Register is read by the processor. If the Data Register is read after one or more
characters are lost by having new data transferred into
the register prior to processor readout, the Lost Data bit
is set in the Status Register. The Read operation continues until the end of sector is reached.
Disk Write Operation
When writing is to take place on the diskette the Write
Gate (WG) output is activated, allowing current to flow
into the Read/Write head. As a precaution against
erroneous writing the first data byte must be loaded into
the Data Register in response to a Data Request from the
FDC179X before the Write Gate signal can be activated.
Writing is inhibited when the Write Protect input is a
logic low, in which case any Write command is immediately terminated, an interrupt is generated and the Write
Protect status bit is set. The Write Fault input, when
activated, signifies a writing fault condition detected
in disk drive electronics such as failure to detect write
current flow when the Write Gate is activated. On detection of this fault the FDC179X terminates the current
command, and sets the Write Fault bit (bit 5) in the Status
Word. The Write Fault input should be made inactive
when the Write Gate output becomes inactive.
Por write operations, the FDC179X provides Write Gate
(Pin 30) and Write Data (Pin 31) outputs. Write data
consists of a series of 500 ns pulses in FM (DDEN=1)

On Disk Write operations the Data Request is activated
when the Data Register transfers its contents to the
Data Shift Register, and requires a new data byte. It is
reset when the Data Register is loaded with new data by
the processor. If new data is not loaded at the time the
next serial byte is required by the Floppy Disk, a byte
of zeroes is written on the diskette and the Lost Data
bit is set in the Status Register.
At the completion of every command an INTRa is
generated. INTRa is reset by either reading the status
register or by loading the command register with a new
command. In addition, INTRa is generated if a Force
Interrupt command condition is met.

COMMAND WORDS
The FDC179X will accept eleven commands. Command
words should only be loaded in the Command Register
when the Busy status bit is off (Status bit 0). The one
exception is the Force Interrupt command. Whenever
a command is being executed, the Busy status bit is set.
When a command is completed, an interrupt is generated and the Busy status bit is reset. The Status Register
indicates whether the completed command encountered
an error or was fault free. For ease of discussion,
commands are divided into four types. Commands and
types are summarized in Table 1.

Type I Commands
The Type I Commands are Restore, Seek, Step, Step-In,
and Step-Out. Each of the Type I Commands contains a
rate field (ror,), which determines the stepping motor
.
rate as defined in Table 2.
The Type I Commands contain a head load flag (h) which
determines if the head is to be loaded at the beginning
of the command. If h = 1, the head is loaded at the
beginning of the command (HLD output is made active).
If h =0, HLD is deactivated. Once the head is loaded,
the head will remain engaged until the FDC179X receives
a command that specifically disengages the head. If
the FDC179X is idle (busy=O) for 15 revolutions of the
disk, the head will be automatically disengaged (HLD
made inactive).
The Type I Commands also contain a verification (V)
flag which determines if a verification operation is to
take place on the destination track. If V = 1, a verification
is performed, if V=O, no verification is performed.
During verification, the head is loaded and after an
internal 15 ms delay, the HLT input is sampled. When
HLT is active (logic true), the first encountered ID field
if read off the disk. The track address of the ID field is
then compared to the Track Register; if there is a match
and a valid ID CRC, the verification is complete, an
interrupt is generated and the Busy status bit is reset. If
there is not a match butthereisvalid ID CRC, an interrupt

Table 1; Command Summary
COMMAND
TYPE
Restore
I
Seek
I
Step
I
Step In
I
Step Out
I
Read Sector
II
Write Sector
II
Read Address
III
Read Track
III
Write Track
III
Force Interrupt IV

7
0
0
0
0
0
1
1

1
1

1
1

6
0
0
0
1
1
0
0
1
1
1
1

5
0
0
1
0
1
0
1
0
1
1
0

BITS
4 3
0 h
1 h
u h
u h
u h
m F2
m F2
0 0
0 0
1 0
1 b

2 1 0
V r, ro
V r, ro
V r, ro
V r, ro
V r, ro
E F, 0
E F, ao
E 0 0
E 0 0
E 0 0
12 I, 10

482

is generated, and Seek Error Status bit (Status bit 4) is
set and the Busy status bit is reset. If there is a match but
not a valid CRC, the CRC error status bit is set (Status
bit 3), and the next encountered 10 field is read from the
disk for the verification operation. If an 10 field with a
valid CRC cannot be found after four revolutions of the
disk, the FDC179X terminates the operation and sends
an interrupt (INTRQ).
The Step, Step-In, and Step-Out commands contain an
Update flag (u). When u = 1, the track register is updated
by one for each step. When u=O, the track register is
not updated.
On the FDC 1795/7 devices, the SSO output is not
affected during Type 1 commands, and an internal side
compare does not take place when the (V) Verify Flag
is on.

Step-Out
Upon receipt of this command, the FDC179X issues one
stepping pulse in the direction towards track O. If the
u flag is on, the Track Register is decremented by one.
After a delay determined by the r,ro field, a verification
takes place if the V flag is on. The h bit allows the head to
be loaded at tlie start of command. An interrupt is
generated at the completion of the command.
Head Positioning
The period of each positioning step is specified by the
r field in bits 1 and 0 of the command word. After the
last directional step an additional 15 milliseconds of
head settling time takes place if the Verify flag is set in
Type I commands. Note that this time doubles to 30 ms
for a 1 MHz clock. If TEST=O, there is zero settling time.
There is also a 15 ms head settling time if the E flag is set
in any Type II or III command.
The rates (shown in Table 2) can be applied to a StepDirection Motor through the device interface.
Step-A 21JS (MFM) or 41JS (FM) pulse is provided as an
output to the drive. For every step pulse issued, the
drive moves one track location in a direction determined
by the direction output.
Direction (DIRC)- The Direction signal is active high
when stepping in and low when stepping out. The Direction signal is valid 12 p.s before the first stepping pulse
is generated.
When a Seek, Step or Restore command is executed an
optional verification of Read-Write head position can be
performed by setting bit 2 (V= 1) in the command word
to a logic 1. The verification operation begins at the end
of the 15 millisecond settling time after the head is
loaded against the media. The track number from the
first encountered ID Field is compared against the
contents of the Track Register. If the track numbers
compare and the 10 Field Cyclic Redundancy Check
(CRC) is correct, the verify operation is complete and an
INTRQ is generated with no errors. The FDC179X must
find an 10 field with correct track number and correct
CRC within 5 revolutions of the media; otherwise the
seek error is set and an INTRQ is generated.

Restore (Seek Track 0)
Upon receipt of this command the Track 00 (TROO)
input is sampled. if TROO is active low indicating the
Read-Write head is positioned over track 0, the Track
Register is loaded with zeroes and an interrupt is generated. If TROO is not active low, stepping pulses (pins 15
to 16+Fit rate specified by the r,ro field are issued until
the
0 input is activated. At this time the Track
Register is loaded with zeroes and an interrupt is generated. If the TROO input does not go active low after 255
stepping pulses, the FDC179X terminates operation,
interrupts, and sets the Seek error status bit. A verification
operation takes place if the V flag is set. The h bit allows
the head to be loaded at the start of command. Note that
the Restore command is executed when MR goes from
an active to an inactive state.

0

Seek
This command assumes that the Track Register contains
the track number of the current position of the ReadWrite head and the Data Register contains the desired
track number. The FDC179X will update the Track
register and issue stepping pulses in the appropriate
direction until the contents of the Track register are
equal to the contents of the Data Register (the desired
track location). A verification operation takes place if the
V flag is on. The h bit allows the head to be loaded at the
start of the command. An interrupt is generated at the
completion of the command.

Table 2. Stepping Rates

elK:
DDEN:

Step
Upon receipt of this command, the FDC179X issues one
stepping pulse to the disk drive. The stepping motor
direction is the same as in the previous step command.
After a delay determined by the r,ro field, a verification
takes place if the V flag is on. If the u flag is on, the Track
Register is updated. The h bit allows the head to be
loaded at the start of the command. An interrupt is
generated at the completion of the command.

2 MHz
0

2MHz
1

1 MHz
0

1 MHz
1

2 MHz
X

1 MHz
X

r,

ro TEST=l TEST=l TEST=l TEST=? TEST=O TEST=O

0
0
1
1

0
1
0
1

3 ms
Sms
10ms
15ms

3ms
S ms
10 ms
15ms

S ms
12 ms
20 ms
30 ms

Sms
12 ms
20 ms
30ms

184ps

190ps
198ps

208ps

3S8ps
380l's
396l's
41Sps

The Head Load (HLD) output controls the movement of
the read/write head against the media. HLD is activated
at the beginning of a Type I command if the h flag is
set (h=1), at the end of the Type I command if the verify
flag (V=1), or upon receipt of any Type II orlll command.
Once HLD is active it remains active until either a Type I
command is received with (h=O and V=O); or if the
FDC179X is in an idle state (non-busy) and 15 index
pulses have occurred.
Head Load Timing (HLT) is an input to the FDC179X
which is used for the head engage time. When HLT= 1,
the FDC179X assumes the head is completely engaged.

Step-In
Upon receipt of this command, the FDC179X issues one
stepping pulse in the direction towards track 76. If the
u flag is on, the Track Register is incremented by one.
After a delay determined by the r,ro field, a verification
takes place if the V flag is on. The h bit allows the head to
be loaded at the start of the command. An interrupt is
generated at the completion of the command.

483

- _... _ - - - - - - - - - - - - - - - - - - _ .

is a match, the Sector Number of the ID field is compared
with the Sector Register. If there is not a Sector match,
the next encountered ID field is read off the disk and
comparisons again made. If the ID field CRC is correct,
the data field is then located and will be either written
into, or read from depending upon the command. The
FDC179X must find an ID field with a Track number,
Sector number, side number, and CRC within four
revolutions of the disk; otherwise, the Record not found
status bit is set (Status bit 3) and the command is terminated with an interrupt.
Each of the Type II Commands contains an (m) flag
which determines if multiple records (sectors) are to be
read or written, depending upon the command. If m =0,
a single sector is read or written and an interrupt is
generated at the completion of the command. If m=1,
multiple records are read or written with the sector
register internally updated so that an address verification
can occur on the next record. The FDC179X will read
or write multiple records starting with the sector presently
in the sector register. The FDC179X will continue to read
or write multiple records and update the sector register
until the sector register exceeds the number of sectors
on the track or until the Force Interrupt command is
loaded into the Command Register, which terminates
the command and generates an interrupt.
If the Sector Register exceeds the number of sectors on
the track, the Record-Not-Found status bit will be set.
The Type II commands also contain side select compare
flags. When C=O, no side comparison is made. When
C=1, the LSB of the side number is read off the ID
Field of the disk and compared with the contents of
the (S) flag. If the S flag compares with the side number
recorded in the ID field, the 179X continues with the ID
search. If a comparison is not made within 5 index
pulses, the interrupt line is made active and the RecordNot-Found status bit is set.
The FDC1795/7 READ SECTOR and WRITE SECTOR
commands include a 'b' flag. The 'b' flag, in conjunction
with the sector length byte of the ID Field, allows different
byte lengths to be implemented in each sector. For IBM
compatability, the 'b' flag should be set to a one. The
's' flag allows direct control over the SSO Line (Pin 25)
and is set or reset at the beginning of the command,
dependent upon the value of this flag.

The head engage time is typically 30 to 100 ms depending on drive. The low to high transition on HLD is
typically used to fire a one shot. The output of the one
shot is then used for HLT and supplied as an input to
the FDC179X.

HLDJr---'

-I

1--50 TO lOOmS--I

f- - j

1-1------

HLT (FROM ONE SHOT)

Head Load Timing

When both HLD and HLT are true, the FDC179Xwilithen
read from or write to the media. The "and" of HLD and
HLT appears as a status bit in Type I status.

TYPE I COMMANDS FLAG SUMMARY
h = Head Load Flag (Bit 3)
h=1, Load head at beginning
h=O, Unload head at beginning
V=Verifyflag (Bit2)
V= 1, Verify on destination track
V=O, No verify
r1 ro= Stepping motor rate (Bits 1-0)
Refer to Table 2 for rate summary
u=Updateflag (Bit4)
u=1, Update Track register
u=O, No update

Type II Commands
The Type II Commands are the Read Sector and Write
Sector commands. Prior to loading the Type II Command
into the Command Register, the system must load the
Sector Register with the desired sector number. Upon
receipt of the Type II command, the busy status Bit is
set. If the E flag=1 (this is the normal case) HLD is made
active and HLT is sampled until true after a 15 msecdelay.
If the E flag is 0, HLD is made active and HLT is sampled
with no delay until true. The ID field and Data Field
format are shown below.
When an ID field is located on the disk, the FDC179X
compares the Track Number on the ID field with the
Track Register. If there is not a match, the next encountered
ID field is read and a comparison is again made. If there

Sector Length Table (1791/2/3/4 only)
Sector Length
Number of Bytes
Field (hex)
in Sector (decimal)
00
128
01
256
02
512
03
1024

Field Format
GAP 1 ID 1 TRACK 'I
SIDE. 1 SECTOR 1 SECTOR 1 CRC 1CRC 1GAPI DATA
ICRCICRC
III
AM NUMBER NUMBER NUMBER LENGTH
1
2
II
AM DATA FIELD
1
2
ID FIELD
DATA FIELD
In MFM only, IDAM and DATA AM are preceded by three bytes of A1 with clock transition between bits4and5 missing.
484
~~-------~------

Read Sector
Upon receipt of the Read Sector command, the head is
loaded, the Busy status bit set, and when an 10 field
is encountered that has the correct track number,
correct sector number, correct side number, and correct
CRC, the data field is presented to the computer. The
Data Address Mark of the data field must be found within
30 bytes in single density and 43 bytes in double density
of the last 10 field CRC byte; if not, the Record-NotFound status bit is set and the operation is terminated.
When the first character or byte of the data field has
been shifted through the DSR, it is transferred tothe DR,
and ORO is generated. When the next byte is accumulated in the DSR, it is transferred to the DR and another
ORO is generated. If the Computer has not read the
previous contents of the DR before a new character is
transferred that character is lost and the Lost Data
Status bit is set. This sequence continues until the complete data field has been inputted to the computer. If
there is a CRC error at the end of the data field, the
CRC error status bit is set, and the command is terminated (even if it is a multiple record command).
At the end of the Read operation, the type of Data
Address Mark encountered in the data field is recorded
in the Status Register (Bit 5) as shown below:
STATUS
BIT 5
1

Write Sector
Upon receipt of the Write Sector command, the head
is loaded (HLD active) and the Busy status bit is set.
When an 10 field is encountered that has the correct
track number, correct sector number, correct side
number, and correct CRC, a ORO is generated. The
FDC179X counts off 11 bytes in single density and 22
bytes in double density from the CRC field and the Write
Gate (WG) output is made active if the ORO is serviced
(i.e., the DR has been loaded by the computer). If ORO
has not been serviced, the command is terminated and
the Lost Data status bit is set. If the ORO has been serviced, the WG is made active and six bytes of zeros in
single density and 12 bytes in double density are then
written on the disk. At this time the Data Address Mark
is then written on the disk as determined by the ao field
of the command as shown below:

o

The FDC179X then writes the data field and generates
ORa's to the computer. If the ORO is not serviced in
time for continuous writing the Lost Data Status Bit is
set and a byte of zeros is written on the disk. The command is not terminated. After the last data byte has been
written on the disk, the two-byte CRC is computed
internally and written on the disk followed by one byte
of logic ones in FM or in MFM. The WG output is
then deactivated.

Deleted Data Mark
Data Mark

o

Data Address Mark (Bit 0)
Deleted Data Mark
Data Mark

ao
1

BIT
7 6151413121110
10101m1F.IEIFdo
1 OlllmlF.IEIFdao

COMMAND
READ SECTOR
WRITE SECTOR

L

rO=Write hex FB (data) into Data Address Mark field
DATA ADD RESS MARK (ao) -"1..1
= Write hex F8 (deleted data) into Data AM field
rO=S!de number not tested
F, (179113) SIDE COMPARE FLAG (C) L1=S,de
number tested
SSO to 0
F, (179517) SIDE SELECT FLAG (S) --C0=UPdate
l=Update SSO to 1
[1l=No delay between HLD activation and HLT Sampling
DELAY (E) ~1=15 ms delay between HLD activating and HLT Sampling
r-

F. (179113) SIDE SELECT FLAG (S)

-C0=compare for side 0
l=Compare for side 1
Sector Length Field
00
01
10
11

'- F. (179517) SECTOR LENGTH FLAG (b)C01""_

256
128

512
256

1024 128
512 1024

(or Write) Single Sectors
MULTIPLE SECTORS (m)SO=Read
~1 = Read (or Write) Multiple Sectors

Figure 1. Type II and III Flag Summary

485

error status bit is set if there is a CRC error. The Track
Address of the 10 field is written into the sector register.
At the end of the operation an interrupt is generated and
the Busy Status is reset.

Type III Commands
There are three Type III Commands:
• READ ADDRESS-Read the next 10 field (6 bytes)
into the FDC.
• READ TRACK - Read all bytes of the entire track,
including gaps.
• WRITE TRACK-Write all bytes to the entire track,
including gaps.

Read Track

Upon receipt of the Read Track command, the head is
loaded and the Busy Status bit is set. Reading starts
with the leading edge of the first encountered index
pulse and continues until the next index pulse. As each
byte is assembled it is transferred to the Data Register
and the Data Request is generated for each byte. No
CRC checking is performed. Gaps are included in the
input data stream. The accumulation of bytes is synchronized to each Address Mark encountered. Upon completion of the command, the interrupt is activated. RG
is not activated during the Read Track Command. An
internal side compare is not performed during a
Read Track.

Read Address

Upon receipt of the Read Address command, the head is
loaded and the Busy Status Bit is set. The next encountered 10 field is then read in from the disk, and the
six data bytes of the ID field are assembled and transferred to the DR, and a ORO is generated for each byte.
The six bytes of the 10 field are shown below:

Write Track

Upon receipt of the Write Track command, the head is
loaded and the Busy Status bit is set. Writing starts
with the leading edge of the first encountered index
pulse and continues until the next index pulse, at which

Although the CRC characters are transferred to the
computer, the FDC179X checks for validity and the CRC

IP _ _-

U

1-DATA
FIELD 1

GAP
3

COMPLETE SECTOR

ID
FIELD 2

GAP

--I
DATA
FIELD 2

SINGLE SIDED:
DOUBLE SIDED,
DOUBLE SIDED,

SECTOR NO.

BYTES/SECTOR
FM
MFM

01-1A
01-0F

128
256

256
512

01-08

512

1024

SECTOR LENGTH

00= 128
01 = 256
02= 512
03= 1024

'OR=F5 WRITE 3 TIMES MFM ONLY

Figure 2. IBM Compatible Sector/Track Format

486

GAP
3

Type IV Commands

time the interrupt is activated. The Data Request is
activated immediately upon receiving the command,
but writing will not start until after the first byte has been
loaded into the Data Register. If the DR has not been
loaded by the time the index pulse is encountered the
operation is terminated making the device Not Busy, the
Lost Data Status Bit is set, and the Interrupt is activated.
If a byte is not present in the DR when needed, a byte of
zeros is substituted. Address Marks and CRC characters
are written on the disk by detecting certain data byte
patterns in the outgoing data stream as shown in the
table below. The CRC generator is initialized when any
data byte from Fa to FE is about to be transferred from
the DR to the DSR in FM or by receipt of F5 in MFM.
Disk formatting (initialization) is accomplished by the
Write Track command. Each byte for the entire track
must be provided for proper formatting. This includes
gap as well as data bytes.
The sequence required to format a diskette begins with
positioning the Read/Write head at the desired track.
Once this has been done, it is necessary to perform a
Write Track command to store all the information on a
track. The Write Track command uses ORO to request
each byte from the system MPU, starting with the byte at
the beginning of the physical Index Pulse and ending
with the last gap bytes at the end of the track. Figure 2
illustrates the IBM standard for track formatting.
Normally, each data byte stored on the diskette must
be generated by the system MPU and passed into the
FDC Data Register. However, there are exceptions to
this rule. If a data byte of hex F5 through FE is entered
into the Data Register, then the FDC recognizes this as
an AM with missing clocks or CRC generation code.
Consequently, F5 through FE must not be used in gaps,
data fields, or 10 fields, as this will disrupt normal operation of the FDC during formatting.

1

1

BIT

17 16 15 14 1 3 1 2 1 1 1
11 11 10 11 1 I, 1 b 1 I, 1

0
10

1
1

L
_

Force Interrupt is the only Type IV command. This
command permits the MPU to terminate (abort) any
command in progress. Figure 3 tabulates the Type IV
command option bits.
The four bits, la-b, are used to select the condition of the
interrupt occurrence. Regardless of which bit is set, any
command currently being executed is immediately
terminated and the Busy status bit is cleared, indicating
"Not Busy". Then, when the condition is met, INTRO
goes high, causing the required interrupt.
If la-b are all" 0", no interrupt occurs, but any currently
executing command is immediately terminated. If more
than one condition is selected, then the interrupt occurs
when any of the conditions is met.
To clear the interrupt, it is necessary to read the Status
Register or to write the Command Register. An exception,
however, is for b= 1 (Immediate Interrupt). For this case,
the interrupt is cleared with another Force Interrupt
command with la-b all low.
Status Register

The Status Register permits the MPU to monitor a variety
of conditions in the FDC. For each command, the
individual status bits have their own meaning. When a
command is initiated (except for the Force Interrupt
command). the Busy status bit is set and the others are
cleared or updated. If the Force Interrupt command is
entered when another command is in progress, the
Busy status bit is cleared, but the others remain
unaffected. However, if the Force Interrupt command
is initiated when there is not another command in progress, the other status bits are cleared or updated and
represent the Type I Command status. Figure4 illustrates
the meaning of the status bits for each command.

1
COMMAND
FORCE INTERRUPT

1
1

READY TRANSITION 1 0 = No effect
L1 = Forces INTRa when READY input goes low-to-high
NOT-READY TRANSITION

iO=No effect
. .
L1
= Forces INTRa when READY Input goes hlgh-to-Iow

INDEX PULSE 10=No Effect
L1 = Forces INTRa on next INDEX pulse input
10=No effect
IMMEDIATE-LJ = Forces INTRa immediately

Figure 3. Force Interrupt Command Flags

487

I

Figure 4A. Status Register Summary
STATUS BIT
4

COMMAND
ALL TYPE I

Not
Not
Not

READ SECTOR
WRITE SECTOR
READ ADDRESS
READ TRACK

Not
Not

WRITE TRACK

Not

7
Ready
Ready
Ready
Ready
Ready
Ready

6
Write Protect
0
Write Protect
0
0
Write Protect

5
Head Loaded
Record Type
Write Fault
0
0
Write Fault

3

2

1

Seek Error

CRC Error

Track 0

Rec not Found
Rec not Found

CRC Error
CRC Error
CRC Error

Index
ORO
ORO
ORO

Busy
Busy
Busy

ORO
ORO

Busy
Busy

Rec not Found
0
0

0
0

Lost
Lost
Lost
Lost

Data
Data
Data
Data

Lost Data

0
Busy

Figure 48. Status Description for Type I Commands
BIT

NAME

MEANING

S7

NOT READY

This bit when set indicates the drive is not ready. When reset it indicates that the drive is
ready. This bit is an inverted copy of the Ready input and logically 'ored' with MR.

S6

PROTECTED

When set, indicates Write Protect is activated. This bit is an inverted copy of WRPT input.

S5

HEAD LOADED

When set, it indicates the head is loaded and engaged. This bit is a logical "and" of HLD
and HLT signals.

S4

SEEK ERROR

When set, the desired track was not verified. This bit is reset to 0 when updated.

S3

CRC ERROR

CRC encountered in 10 field.

S2

TRACK 00

S1

INDEX

When set, indicates Read/Write head is positioned to Track O. This bit is an inverted copy
of the TROO input.
'!'{hen set, indicates index mark detected from drive. This bit is an inverted copy of the
IP input.

SO

BUSY

When set command is in progress. When reset no command is in progress.

Figure 4C. Status Description for Type II and III Commands
BIT
S7

NAME
NOT READY

MEANING
This bit when set indicates the drive is not ready. When reset, it indicates that the drive
is ready. This bit is an inverted copy of the Ready input and 'ored' with MR. The Type II
and III Commands will not execute unless the drive is ready.

S6

WRITE PROTECT

On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates a Write
Protect. This bit is reset when updated.

S5

RECORD TYPE/
WRITE FAULT

On Read Record: It indicates the record-type code from data field address mark.
1=Deleted Data Mark. O=Data Mark. On any Write: It indicates a Write Fault. This bit is
reset when updated.

S4

RECORD NOT
FOUND (RNF)

When set, it indicates that the desired track, sector, or side were not found. This bit is reset
when updated.

S3

CRC ERROR

If S4 is set, an error is found in one or more 10 fields; otherwise.it indicates error in data
field. This bit is reset when updated.

S2

LOST

S1

DATA REQUEST

This bit is a copy of the DRQ output. When set, it indicates the DR is full on a Read Operation
or the DR is empty on a Write operation. This bit is reset to zero when updated.

SO

BUSY

When set, command is under execution. When reset, no command is under execution.

DAT~

When set, it indicates the computer did not respond to DRQ in one byte time. This bit is
reset to zero when updated.

488

Write Data Timing:
SYMBOL

MIN.

TYP.

MAX.

UNITS

CONDITIONS

Write Data Pulse Width

Twp

450
150

550
250

Write Gate to Write Data

Twg

Write
Early
Early
Write
Write

Tbc
Ts
Th

500
200
2
1
2,3, or 4

nsec
nsec
/lsec
/lsec
/lsec
nsec
nsec

FM
MFM
FM
MFM
±CLK Error
MFM
MFM

/lsec
/lsec
nsec
nsec
nsec
nsec

FM
MFM
CLK=1 MHZ
CLK=2 MHZ
CLK=1 MHZ
CLK=2 MHZ

PARAMETER

data cyle Time
(Late) to Write Data
(Late) From
Data
Gate off from WD

125
125
2
1

Twf

WD Valid to Clk

TWdl

WD Valid after Clk

Twd2

100
50
100
30

These values are doubled when CLK=1 MHz.

Write Data Timing
WRITE GATE

-.J
--l

L
Twg

- l Twp
~I Twl I11...__---'11...__--111'--___
I---Tbc

1-01
.

-

-

-

..

WRITE DATA _ _ _.....

elK
(1MHZ)

I-

' - - - - 5 0 0 ns

1 . ._______-'

WD _ _ _ _

---II"'~I

L

L~LLLLLL~
TWd1~
~125

elK
(2MHZI

1

I

125~

-----'1

L -_ _ _ _ _ _

----..l.W0L..L...L..L:...L..~L.LJ

WD _ _ _

TWd1~
WAITE DATA/CLOCK RELATIONSHIP
(DDEN~O)

489

!---T d2
W

I

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range .......................................................... O°C to +70°C
Storage Temperature Range ........................................................ -SsoC to +1S0°C
lead Temperature (soldering, 10 sec.) ........................................................ +32SoC
Positive Voltage on any Pin, with respect to ground ............................................... +1SV
Negative Voltage on any Pin, with respect to ground ............................................. -0.3V
*Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute
Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes
or "glitches" on their outputs when the AC power is switched on and off. In addition, voltage transients on the
AC power line may appear on the DC output. If this possibility exists it is suggested that a clamp circuit be used.
ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C, Vcc=+SV±S%, Voo=+12V±S% unless otherwise noted)
SYMBOL

PARAMETER
DC CHARACTERISTICS
Input Voltage levels
low level, VIL
High level, VIH
Output Voltage levels
low level VOL
High level VOH
Output leakage, ILO
Input leakage, IlL
Output Capacitance
Input Capacitance
Power Dissipation
AC CHARACTERISTICS
Processor Read Timing
Address Setup Time
Address Hold Time
~ Pulse Width (CL=SOpF)
D a Reset Time
INTRa Reset Time
Data Delay Time (CL =SOpF)
Data Hold Time (CL=SOpF)
Microprocessor Write Timing
Address Setup Time
Address Hold Time
WE Pulse Width
ORO Reset Time
INTRa Reset Time
Data Setup Time
Data Hold Time
Disk Input Data Timing
RAWREAD Pulse Width
Clock Setup Time
Clock Hold Time for MFM
Clock Hold Time for FM
RAWREAD Cycle Time
RClK High Pulse Width
RClK low Pulse Width
RClK Cycle Time

MIN

TYP

MAX

UNIT

0.8

V
V

O.4S

SOO

V
V
JiA
JiA
pf
pf
mW

SOO
3000*
3S0
1S0

ns
ns
ns
ns
ns
ns
ns

Figure
Figure
Figure
Figure
Figure
Figure
Figure

S
S
S
S
S
S
S

ns
ns
ns
ns
ns
ns
ns

Figure
Figure
Figure
Figure
Figure
Figure
Figure

6
6
6
6
6
6
6

2.6

2.8
10
10
S
10

tSETR
tHLOR
tRE
tORR
tlRR
tOACC
tOOH

SO
10
400

tSElW
tHLOW
tWE
tORR
tlRR
tos
tOH

SO
10
3S0

t pw
td
ted
tcs
tbe

100*
40
40
40
1S00
0.8
0.8
0.8
0.8

MFM
FM
MFM
FM
MFM
FM

ta
tb

SOO*
SO

SOO*
2S0
70

te

Miscellaneous Timing
ClK low Pulse Width
ClK High Pulse Width

tCOl
tC02

MFM
STEP Pulse Width
FM
DIRC Setup Time
MR Pulse Width
IP Pulse Width
WF Pulse Width
ClK Cycle Time
*: These Values are doubled when ClK=1

tSTP
tOIR
tMR
tiP
tWF
tCYC
MHz.

230
200
2*
4*

-----~~-

200

ns
ns
ns
ns
ns
JiS
Jis
Jis
Jis
JiS
JiS

1*
2*
1*
2*
2*
4'
2S0
2S0
12

SO*
10*
10*
O.S*

490
~~-

SOO
3000*

20000
20000

ns
ns
JiS
Jis
Jis
Jis
JiS
f.1s
f.1s

COMMENTS

IOL=1.6 mA
IOH=100 JiA
VOUT=VOO
VIN=VOO

Figure 7, See Note
Figure 7 See Note
Figure 7
Figure 7
1800 at 70°C, Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure

8
8
8
8
8
8
8
8
8

Figure 5.
Microprocessor
Read Timing

---i

,I

ORO

r-

16~s
TORR

32~

• (MFM) or

1

~T"':::::::l

I -jTHWC~
I
TIS----:x:::
I
I X- ---- -- I

INTRO---.l
Ao,A,
_
RE

-I

• (FM)

- - - - - ------

~T"'t-T,,-j

~

t= I
c:::o

T""-1
DALo-OAL7

-lTOOH~

Figure 6.
Microprocessor
Write Timing

II

ORO

r-~
16~s

-l

3~s

• (MFM) or

-I

• (FM)

TORR

1

T"'=:::l

I --j

INTRO---.l

I
CS"----X

AoA.

I
-

-

I
-

-

-

~T"'+Tw'--j
"'---l

WE

}

THWe-:-

r------------I

--j T" f-

Figure 7.
Disk Input
Timing

---1

~·~t~

RAWREAO

r-

CI:)

DALo-OAL7

TOH

-I

tOo

U

~~=j

-l~

I

RCLK

U

~T.

I

=1

I

I

-I-

To

To

Note: Pulse width on RAW READ (pin 27) is norr ,ally 10-30'J ns. However, pulse may be any Width if pulse is entirely
within Window. If pulse occurs in both windows, then pulse width must be less than 300 ns for MFM at CLK=2 MHz and
600 ns for FM at 2 MHz. Times double for 1 MHz.

Figure 8.
Miscellaneous
Timing

iP

I

WF

I

I
f--T"~

I

f--Tw,----j

MR

I

I

~T,w-l f - - T " , - - j

CLK~

1+~
Teo2

I~

OIRc--..l STEP IN
rT"-i
STEP

n

I-T"'~

I-T'"

"
491

n

~T5TP

DISK FORMATS
Disks may be formatted in IBM 3740 or System 34
formats with sector lengths of 128, 256, 512, or
1024 bytes.
IBM 3740 Format
This single-density (FM) format utilizes 128 bytes/
sector. The bytes to be generated by the system
MPU for use in the execution of the Write Track
command are shown in Figure 9.
IBM System 34 Format
This double-density (MFM) format utilizes 256
bytes/sector. The bytes to be generated by the
system MPU for use in the execution of the Write
Track command are shown in Figure 10.
Non-IBM Formats
Unique (non-IBM) formats are permissible providing the following restrictions are understood.
• Sector length may only be 128, 256, 512, or
1024 bytes.
• Gap sizes must conform to Figure 11.

DATA
BYTE
(hex)

NO. OF
BYTES

4E

00

-

ONE
SECTOR

-



DRIVE

765 (8272)

r-

WP/TS

r

FLT/TR0

t

~

G1

G2

2SIDED
WPRT
TRK00
FAULT

~

RW/SEEK
D0D7

C

DB0DB7

FRISTP

~

LCT/DIR

~

N T _ INT

US1

CS
RD
WR
A0

US0

CSRD_
WR _
M_

DR O _ DRO
DAC K _ DACK

r---oE

I

FDC9229

r-----

T C _ TC
ET _ _
RST
RES

r

WDA
PS0
PS1
RDW

EARLY
LATE
-SEPCLK DSKD

RDD

SEPD

CLK

I
I

~
aA
D

DRSEL4

C
0
D
E
R
0.....-

DRSEL3
DRSEL2
DRSEL1

HLD

TEST
FDCSEL
WDOUT
WDIN

MFM
WCK

WDATA

~

P2

~g:: -

r--

MINI

,...--

DENS
CLKOUT

P1

~~

HLTiCLK
CLKIN

P0

~~~

---\

-4

RDY

RDY

IDY
WE

IDX
WE

SIDESEL

-v'

RAW
READ

-~

•

16 MHz
TTL INPUT

LATCH

D0-D7

~

HDL
RDY ~RDY
IDX ~ IDX
WE I-----WE
HD
SIDE SEL
+5V

FAULT
RST
STEP
LOW CUR
DIR

SIDE

MOTOR
ON
/\

---.I
'The FDC9229/B, as all other NMOS integrated circuits, presents a high
impedance on all inputs.
To avoid soft errors caused by transmission line effects and noise where
there is long cabling between the floppy disk drive and the controller board, the
use of a (non-invertin9LII!- schmidt-trigger input gate or bus transceiver is
recommended at the DSKD input to the FDC9229/B.

503

I

TYPICAL SYSTEM IMPLEMENTATION-179X FOC
DRIVE
179X

TRK00
WPRT

TR00
WPRT
I.p.

INDEX
READY
DIR
STEP

READY
DIR
STEP

WRITE
GATE

WG

00-07

<=>

INT

RO _ _ _

___
oRO
RE _ _ _
WE _ _ _

CS
Al
A0
ET
RES

__
___
___
___

HLD

DALODAL7

L

HLD
FDC-9229

HLD

INTREO
ORO
RE
WE
CS
Al
A0

RAWRD
HLT

SEPD
HLTiCLK

DSKD
SEPCLK FDCSEL

RCLK
DDEN
WD
EARLY
LATE
TG43

MR

DENS
~ MINI
WDIN
EARLY
LATE

WDOUT
TEST
P2
Pl

CLKOUT
CLKIN

CLK

.!

PO

<8~ RAW READ

h

~V-

WDATA

~~.-

t2E

.':'

l6MHz
TTL INPUT
LATCH
LCUR

"D,

=:)

MOTOR ON
SIDE
SEL3
SEL2
SELl

A

--.J
'The FDC9229/B, as all other NMOS integrated circuits, presents a high
impedance on all inputs.
To avoid soft errors caused by transmission line effects and noise where
there is long cabling between the floppy disk drive and the controller board, the
use of a (non-invertin9lliL schmidt-trigger input gate or bus transceiver is
recommended at the DSKD input to the FDC9229/B.

STANDARD MICROSYSTEMS
CORPORATION (~iiiiiiiii~
35M.!rcusBI,dHJupp;lUqeNY11788
1510,2133100 iWXSro2i.78S<}8

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications. consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such Information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible

504

FDC92C36
PRELIMINARY

CMOS Floppy Disk Data Separator

FEATURES

PIN CONFIGURATION

o High Performance Digital Data Separator

o Pin Replacement for FDC9216
o Performs complete data separation function for floppy
disk drives
o Eliminates all adjustments normally associated with
high performance data separators
o Single + 5 Volt Supply

DSKD
SEPCLK
REFCLK
GND

DSJ
2
3
4

7 ]
6 ]
5 ]

Vee
SEPD
CD1
CDO

o Fully TTL compatible

o Fabricated in power saving CMOS
o Compatible with 3.5", 5.25" and 8" drives and data

PACKAGE: 8-pin DIP

rates up to 500 KBs

o 16-Bit half Cell Divide Algorithm greatly improves
performance over conventional digital designs

FUNCTIONAL DESCRIPTION
The FDC 92C36 is a CMOS integrated circuit. It incorporates a high performance, synthetic phase locked loop digital data separator inone 0.3 inch wide 8 pin package.
The use of a high performance synthetic phase locked loop
allows the system designer to replace a costly and board
consuming analog data separator (and the tuning normally

505

required with an analog design) with a cost effective, single
chip digital circuit
The FDC 92C36 is available in two versions: the FDC 92C36
are intended for 5 1/4" drives using data rates of 250KBs
and the FDC 92C36B for 3 1/2", 5 1/4", and 8" drives using
data rates of 500KBs_

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

NAME

FUNCTION

SYMBOL

1

Disk Data

OSKO

Data input signal direct from disk drive. Contains combined clock and data
waveform.
Clock signal output from the FOOS derived from floppy disk drive serial bit stream.

2

Separated Clock

SEPCLK

3

Reference Clock

REFCLK

Reference clock input

4

Ground

GNO

Ground

5,6

Clock Divisor

COO and COl control the internal clock divider circuit. Refer to Table 1.

7

Separated Data

COO,
COl
SEPO

SEPO is the data output of the FOOS

8

Power Supply

VDD

+ 5 volt power supply

OPERATION
A reference clock (REFCLK) of 8 or 16 MHz is divided by
the FDDS to provide an internal clock. The division ratio is
selected by inputs CDO and CD1. The reference clock and
division ratio should be chosen per table 1.
The FDDS detects the leading edges of the disk data pulses
and adjusts the phase of the internal clock to provide the
SEPARATED CLOCK output.

Separate short and long term timing correctors assure
accurate clock separation.
The SEPCLK frequency is nominally %2 the internal clock
frequency. Depending on the internal timing correction, the
duration of any SEPCLK half-cycle may vary from a nominal of 16 to a minimum of 12 and a maximum of 21 internal
clock cycles.

TABLE 1
CD1

COO

a
a

a
a

8MHzREFCLK

16MHz REFCLK

not used

51/4" SO

8"SO
51/4"00

8"00

DIVISOR
f(REFCLK)/f(INTCLK)

4

2

8"SO

51/4" SO

51/4" DO

Illegal

Illegal

Illegal

~SLfUUULf1.J"lJL

INTCLK

I,',

II

!I

\

I

\

I

!:

1

r----------J--i-!----i
i
SEPCLK~
,,~------r-~I--~
I

I

aIways 2
internal
clock
cycles

\

I!

i

i

:

I::
I

: : :

i;,

j~

~

! I
:~~:--~--------~LJ~:
------------------~LJr:-----:

1

,

:

:

i - I always 4 internal clock cycles

-l ]--

f

J

FIGURE 2
506

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range .............................................................................. O°C to + 70°C
Storage Temperature Range ........................................................................... - 55°C to + 150°C
Lead Temperature (soldering, 10 sec.) ............................................................................ + 300°C
Positive Voltage on any 1/0 Pin, with respectto ground ............................................................. + 7.0V
Negative Voltage on any 1/0 Pin, with respect to ground ........................................................... - 0.3V
Power Dissipation ..................................................................................................... 0.75W
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device. from laboratory or system power supplies, it is important that the Absolute Maximum
Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their
outputs when the AC power is switched on and off. In addition, voltage transients on the AC power line may appear on
the DC output. If this possibility exists it is suggested that a clamp circuit be used.

ELECTRICAL CHARACTERISTICS (TA = ooe to 70 oe, V DD = + 5V ± 5%, unless otherwise noted)
Parameter
SYMBOL
Min.
Max.
T
D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low Level V,L
High Level V,H
OUTPUT VOLTAGE LEVELS
Low Level VOL
High Level VOH
INPUT CURRENT
Leakage I'L
INPUT CAPACITANCE
All Inputs
POWER SUPPLY CURRENT

0.8

V
V

0.4

V
V

10

fLA

10

pF

TBD

mA

8.1
16.2.
100

MHz
MHz
ns

2.0
2.4

100

IOL=1.6mA
IOH = -100 fLA
O

eha!1ge"'

Except XTAUClKIN

lOl = 1.6 ma, except ClK
lOl = 0.4 ma, ClK only
lOH = -1OOfLa, except ClK
lOH = - 400fLa, ClK only

TBD
TBD
TBD
(All times assume XTAUClKIN = 16 MHz unless
otherwise specified)

ClKIN Frequency

3.95
3.95

ClKIN Duty Cycle

40

TCLKOH

90

ClK

~~~------4~0~MHZ----;r----~

W C l 4 = TelKoH

"

CONDITION

2.4

POWER SUPPLY CURRENT
I"
INPUT lEAKAGE CURRENT
III
INPUT CAPACITANCE
C'N
AC ELECTRICAL
CHARACTERISTICS

~]J
,,;"MI1\I41t~'

, "Some

+5V ±5%)

16.2
B.1
60

%

125

140

ns

XTAl
16MHz
16MHz
16MHz
16MHz
BMHz
BMHz
BMHz
BMHz

==1''----

FDC 923BB/BT
FDC923BIT

MHz
MHz

16
B.O

Inputs
DISK
CD,
CDo DATA RATE
a
a 250KHz
1
a 500KHz
a
1
125KHz
250KHz
1
1
a
a 125KHz
1
a 250KHz
a
1
Not
1
1
Not

ClK

WClK

ENCODING

BMHz
BMHz
4MHz
4MHz
4MHz
4MHz
Used
Used

500KHz
1MHz
250KHz
500KHz
250KHz
500KHz

FM
MFM
FM
MFM
FM
MFM

TABLE 1

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications:

consequently complete information sufficient for construction purposes is not necessarily given. The information
has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed fur inac-

curacies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described
any license under the patent rights of SMC or others. SMC reserves the right to make changes at any time in order
to improve design and supply the best product possible.

512

FDC 9239/92398
9239T/92398T
PRELIMINARY

ENHANCED FLOPPY DISK INTERFACE CIRCUIT
FEATURES

PIN CONFIGURATION

o Digital Data Separator
Performs complete data separation function
for floppy disk drives
Separates FM and MFM encoded data
No critical adjustments necessary
3%",5%" and 8" compatible

o Variable Write Precompensation
o Internal Crystal Oscillator Circuit
o Track-Selectable Write Precompensation
o Retriggerable Head-Load Timer
o Fully compatible with FOC 179X, FOC 765A and

DSKD

1

FDCSEL

2

19 P2

MINI

3

18 P1

DENS

4

17 PO

SEPCLK

5

16.XTAL2

SEPD

6

15 HLD

WDOUT

7

14 LATE

\J

20 Vee

HLT/CLK 8
CLKOUT

FOC 7265

13 EARLY

9

12 WDIN

GND 10

o 16-8it Cell Divide Algorithm Improves Performance
o Fabricated in Low Power CMOS
o Single + 5 Volt Supply
o TTL Compatible; Fully Compatible with the FOC 9229

11 XTAL 1/CLKIN

PACKAGE: 20-pin D.I.P.

()
io~()
~~~~~~~
25242322212019
N/C [ 26

lBO N/C

P, [ 27

17~ EARLY

16~
15p
14/J
13/J
12p

Vee: [ 2B
OSKD [ 1
FDCSEL [ 2
MINI [ 3
N/C [ 4

WOIN
XTAL,
VSS
CLKOUT
N/C

5 6 7 B 9 1011

~~~~::~~
-Z....Ja...::)-l-zWOUJOO z
oa..U)o~

~

;!:I

PACKAGE: 28-pin PLCC

FUNCTIONAL DESCRIPTION
The FOC 9239 is a CMOS integrated circuit designed to
complement either the 179X or 765 (8272) type of floppy
disk controller chip. It incorporates a digital data separator,
write precompensation logic, and a head-load timer in one
O.3-inch wide 20-pin package. A single pin will configure
the chip to work with either the 179X or 765 type of controller. The FOC 9239 provides a number of different dynamically selected precompensation values so that different

values may be used when writing to the inner and outer
tracks of the floppy disk drive. The FOC 9239 operates from
a + 5V supply.
The FOC 9239 is available in four versions: the FOC 92391
T which is intended for 5%" drives and the FOG 92398/T
for 3%", 5%" and 8" drives. (The IT versions require a TTL
clock input.)

513

DESCRIPTION OF PIN FUNCTIONS
PIN NO.
1

SYMBOL
DSKD

110

2

FDCSEL

I

3

MINI

I

4

DENS

I

5
6

SEPCLK
SEPD

0
0

7
8

WDOUT
HLT/CLK

0
0

The precompensated WRITE DATA stream to the drive.
When in the 765 mode (FDCSEL high), this output is the master clock to
the floppy disk controller. When in the 179X mode, this signal goes high
after the head load delay has occured following the HLD input going high.
This output is retriggerable. (See fig. 3.)

9

CLKOUT

0

10
11

GND
XTAL 1/CLKIN

This signal is the write clock to the floppy disk controller. Its frequency is
determined by the state of the MINI, DENS and FDCSEL input pins.
(See fig. 3.)
Ground

I

This input is for direct connection to a 16 MHz or 8 MHz single-phase
TTL-level clock, or one lead from an 8 MHz or 16 MHz crystal.

12
13

WDIN
EARLY

I
I

14

LATE

I

15

HLD

I

16

XTAL2

I

The write data stream from the floppy disk controller.
When this input is high, the current WRITE DATA pulse will be written
early to the disk.
When this input is high, the current WRITE DATA pulse will be written late
to the disk.
When both EARLY and LATE are low, the current WRITE DATA pulse will
be written at the nominal position.
This input is only used in 179X mode. A high level at this input causes a
high level on the HLT/CLK output after the specified head-load time delay
has elapsed. The delay is selected by the state MINI output. (See fig. 3.)
In 765 mode this pin should be grounded.
The second lead from an 8 MHz or 16 MHz crystal is connected to this
pin. In those applications, using a TTL clock, this pin should be left
floating.

17
18
19

PO
P1
P2

I
I

20

Vee

I

DESCRIPTION
This input is the raw read data received from the drive. (This input is
active low.)
This input signal. when low, programs the FDC 9239 for a 179X type of
LSI controller. When FDCSEL is high, the FDC 9239 is programmed for a
765 (8272) or 7265 floppy disk controller. (See fig. 4.)
The state of this input determines whether the FDC 9239 is configured
to support 8" or 5%" floppy disk drive interfaces. It is used in conjunction with the DENS input to prescale the clock for the data separator.
The state of this input also alters the CLKOUT frequency, the
precompensation value, the head load delay time (when in 179X mode)
and the HLT/CLK frequency (when in 765 mode). See figs. 2, 3, and 4.)
The state of this input determines whether the FDC 9239 is configured to
support single density (FM) or double density (MFM) floppy disk drive
interfaces. It is used in conjunction with the MIN I input to prescale the
clock for the data separator. The state of this input also alters the
CLKOUT frequency when in the 765 mode. (See figs. 2, 3, and 4.)
A square-wave window clock signal output derived from the DSKD input.
This output is the regenerated data pulse derived from the raw data input
(DSKD). This signal may be either active low or active high as
determined by FDCSEL (pin 2).

P2-PO select the amount of precompensation applied to the write data.
(See fig. 2.)

I
+5 VOLT SUPPLY

514

OPERATION
Data Separator
The ClKIN input clock is internally divided by the FDC 9239
to provide an internal clock. The division ratio is selected by
the FDCSEl, MINI and DENS inputs depending on the type
of drive used. (See fig. 1.)

INPUTS
FDCSEl DENS

0
0
0
0
1
1
1
1

The FDC 9239 detects the leading (negative) edges of the
disk data pulses and adjusts the phase of the internal clock
to provide the SEPClK output.
Separate short- and long-term timing correctors assure
accurate clock separation.
The SEPClK frequency is nominally '/32 the internal clock
frequency. Depending on the internal timing correction, the
duration of any SEPClK half-cycle may vary from a nominal of 16 to a minimum of 12 and a maximum of 21 internal
clock cycles.

INTClK

I!
I

0
0
1
1
0
0
1
1

MINI

0
1
0
1
0
1
0
1·

DIVISOR
f(ClKIN)/f(INTClK)
1

2
2
4
2
4
1

2

i!

!i

l

I:
~~'-----~-+!--~:

1

s~c~

t

!

I

I

I

i l l

H

H

SEPD---------~i

always 2
1
internal i
clock
i
cycles

I

~,---~------------~

H

L -__________________________~

L -_________

!

~

I

1---1 always 4 internal clock cycles

f--_+-__+-____________-I-_____

--[CLKOUT

.--_ _ _ _ _ _ _ _- I_ _ _ _ _--1HLTCLK

L--_ _ _ _ _ _ _ _ _ _ _ _ _ _--I WOOUT

9239

BLOCK DIAGRAM

515

OPERATION (CONT'D)
Precompensation
The desired precompensation delay is determined by the
state of the PO, P1 and P2 inputs of the FDC 9239 as per
fig. 2. Logic levels present on these pins may be changed
dynamically as long as the inputs are stable during the time
the floppy disk controller is writing to the drive and the inputs
meet the minimum setup time with respect to the write data
from the floppy disk controller.

Head Load Timer
The head load time delay is either 40 ms or 80 ms, depending on the state of MINI. (See fig. 3.) The purpose of this
delay is to ensure that the head has enough time to engage
properly. The head load timer is only used in the 179X mode;
it is non-functional in the 765 or 7265 mode.
The FDC 179X initiates the loading of the floppy disk drive
head by setting HLD high. The controller then waits the programmed amount of time until the HLT signal from the FDC
9239 goes high before starting a read or write operation.

MINI

P2

P1

PO

PRECOMP VALUE

0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1

o ns
62.5 ns
125 ns
187.5 ns
250 ns
250 ns
o ns
125 ns
250ns
375ns
500 ns
500ns
625 ns
625 ns

NOTE: All values shown are obtained with a 16 MHz reference
clock. Multiply pre-comp values by two for 8 MHz
operation.

FIG. 2 WRITE PRECOMPENSATION
VALUE SELECTION

INPUTS
FDCSEL DENS
0
0
0
0

OUTPUTS
MINI

CLKOUT HLT/CLK

16 MHZ INPUT CLOCK

8 MHZ INPUT CLOCK

CONTROLLER

0
0
1
1

0
1
0
1

2MHz
1 MHz
2MHz
1 MHz

40 ms'
80 ms'
40ms*
80ms*

8" Double Density
5'14" Double Density
8" Single Density
5%" Single Density

5%" Double Density
Not Permitted
5W' Single Density
Not Permitted

179X
179X
179X
179X

0
0
1
1

0
1
0
1

500KHz
250 KHz
1 MHz
500KHz

8MHz
4MHz
8MHz
4MHz

8" Single Density
5W' Single Density
8" Double Density
5%" Double Density

5%" Single Density
Not Permitted
5%" Double Density
Not Permitted

765 (8272)
765 (8272)
765 (8272)
765 (8272)

NOTE: 3%" drive users should consult drive specifications to determine if drive data rate equals 5.25" or 8" standards.
*NOTE: All values shown are obtained with a 16 MHz reference clock. Divide all frequencies and multiply all periods by
two for 8 MHz operation.

FIG. 3 CLOCK/HEAD LOAD TIME DELAY AND
FLOPPY DISK DRIVE/CONTROLLER SELECTION

516

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range .................................................................................. O°C to + 70°C
Storage Temperature Range ................................................................................. - 55° to + 150°C
lead Temperature (soldering, 10 sec.) ................................................................................ + 300°C
Positive Voltage on any 1/0 Pin, with respect to ground .................................................................. + 7.0V
Negative Voltage on any 1/0 Pin, with respect to ground ................................................................. - 0.5V
Power Dissipation ...................................................................................................... 0.25W
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not
be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power
is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is
suggested that a clamp circuit be used.

DC CHARACTERISTICS
INPUT VOLTAGE
-0.3
2.0

0.8

V
V

-0.3
3.2

1.5

V
V

0.4

V

OUTPUT VOLTAGE
low level VOL
High level VOH

2.4

Except ClKIN

V

I

SUPPLY CURRENT
20

mA

lEAKAGE CURRENT
10
CAPACITANCE
TBD

AC ELECTRICAL
CHARACTERISTICS
ClKIN frequency
ClKIN DUTY CYCLE
tClkOh

twdo

'tt"

dNEC
WdE

3.95
3.95
40
465
215
90
150
50
0
500

16
8
500
250
125
312.5

562.5

t"'<.IN
tWdL

1.0

517

16.2
8.1
60
515
265
140
350
400
400

MHz
MHz

FDC9239B
FDC9239

%

ns
ns
ns
ns
ns
ns
ns

FDCSEl = low; MINI = high
FDCSEl = low; MINI = low
FDCSEl = high
Time Doubles with MINI-1

9 clock times ± 1 clock time
See fig. 2
See fig. 2

AC TIMING CHARACTERISTICS
HLT/CLK (765 MODE)

WDOUT PULSE WIDTH

~1-"'---4-J!a ----tl~~--

-}=tWDO=f-

MHz

CLKOUT VS. WDIN TIMING
t79X MODE
CLKOUT

WDIN

~'}

1

\'--_---1
\~--------------t. 2, or 4 flsec.

765 (8272) MODE
CLKOUT

WDIN

SET-UP TIME P0, P1 AND P2 TO WDIN
P0, Pt, P2

CLKOUT

)

WDIN

t,

CLKOUT
(179X)

CLKOUT
(765)

t------I""' ------.-1

WDOUT (EARLY)

WOOUT (NOMINAL) _ _- ;_ _ _JI

PRECOMPENSATION
WDOUT (LATE)

_ _ _:l------\
--A'
'\..
Ref. to Fig. 2 for
Ip (precompensation)
value

518

TYPICAL SYSTEM IMPLEMENTATION-765 (8272) FDC OR 7265 FDC

r-f>

DRIVE

!

7265 or
765 (8272)
G1

r-

WP'TS

C

FLT,TRO

C

DBODB7

2 SIDED
WPRT
TRK00

--11-

RWISEEK

D0D7

G2

FAULT

FAULT
RST
STEP
LOW CUR

L ~
1-

FRISTP
LCT/DIR

DIR

'i)"""'
E

DRSEL4

I N T _ INT

US1

C
0

DRSEL3

C S - - CS
RD _ _
RD
W R _ WR

USO

D
E
R

DRSEL1

HDL
RDY ~RDY
IDX
IDX

A O _ AO
DAC K _ DACK
TC _ _
TC
RES

ET _ _

WE
HD

WE
r----r----- SIDE +5V
SEL

WDA

FDCSEL
WDOUT
WDIN

PSCl
PS1
RDW

EARLY
LATE
-SEPCLK DSKD

RDD

SEPD

RST

MFM
WCK
CLK

II

r--

DENS
CLKOUT

P1

XTAL1

P0
XTAL2

!

!

16 MHz XTAL
OR
TTL INPUT
(XTAL 1 ONLY)

LATCH

~

~

HLD

"""

~

RAW
READ

~" 0~r-

~
O-r_ 0-~

RDY

RDY

IDY
WE

IDX
WE

SIDESEL

-Y

WDATA

~ O-rP2

MINI

HLT/CLK

D0-D7

l

FOe 9239

I---

DR O _ DRO

DRSEL2

SIDE

MOTOR
ON
A

---.J
'The FDC9239/B, as all 01her NMOS integrated circuits, presents a high
impedance on all inputs.
To avoid soft errors caused by transmission line effects and noise where
there is long cabling between the floppy disk drive and the controller board, the
use of a (nOn-invertin~JTL schmidt-trigger input gate or bus transceiver is
recommended at the
KD input to the FDC9239/B.

519

I

TYPICAL SYSTEM IMPLEMENTATION-179X FOC OR 979X FOC
DRIVE
179X

TROO
WPRT

TRKOO
WPRT

I.p.

INDEX
READY
DIR
STEP

READY
DIR
STEP

WRITE
GATE

WG

DO-D7

\=)

HLD

DALODAL7

INTRO _ _ _ INTREO
oRO _ _ _ DRO
RE~ RE
WE~ WE
CS _ _ _
CS
Al _ _ _ Al
A(JJ _ _ _
AO
ET _ _ _
RES
MR

RAWRD
HLT
RCLK
DDEN
WD
EARLY
LATE
TG43

L

---

HLD
FDC 9239
HLD
SEPD
DSKD
HLT CLK
SEPCLK FDCSEL
DENS
MINI
WDIN
EARLY
LATE

WDOUT

P2
Pl

CLK

CLKOUT
XTAL 1

PO
XTAL2

~16MHJ

~

<8!-

:--i»--

RAW READ

WDATA

~~
~~

~~ -::-

OR
TTL INPUT
(XTAL 1 ONLY)

LATCH

LCUR
MOTOR ON
SIDE
SEL3

DO-D7 - - - \

-v'

SEL2
SELl

A

---1
'The FDC9239/B, as all olher CMOS inlegrated circuits, presents a high
impedance on all inputs.
To avoid soft errors caused by transmission line eliects and noise where
there is long cabling between the floppy disk drive and the controller board, the
use of a (nOn-inverting~TKTL schmidt-trigger input gate or bus transceiver is
recommended at the D 0 input to the FDC9239/B.

STANDARD MICROSYSTEMS
CORPORATION
35M.ln:usfll,dHau~NYIll8a

15161U3-3!OO

TWX 510 221-B89B

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications:. consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However. no responsibility IS
assumed for inaccuracies. Furthermore. such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible

520

STANDARD MICROSYSTEMS
CORPORATION

FDC92C49
PRELIMINARY

Analog Floppy Disk Data Separator
(AFDDS)
PRELIMINARY
PIN CONFIGURATION

FEATURES

o Analog Data Separator performs complete data
separation for floppy disk drives
Separates FM and MFM encoded data
3-1/2",5-1/4" and 8" compatible

WOIN
EARLY
lATE
XTAL1
XTAl2
WCK
ROD
ROW
ROIN
PDOUT
RBT
GND

o No critical adjustments necessary
o Variable Write Precompensation
o Internal Crystal Oscillator
o Fully compatible with FDC765A
o High Performance Analog Pase Locked Loop
o Fabricated in Low Power CMOS
o TTL Compatible I/O

VCC
P1
PO
WOOUT
ClK
MINI
MFM
AVCC
lPIN
VREF
lPOI
AGND

o Single + 5V Supply

GENERAL DESCRIPTION
The FDC92C49 CMOS Analog Floppy Disk Data Separator (AFDDS) performs high performance analog data separation on data from a floppy disk drive. The FDC92C49 is
compatible with 3.5", 5.25" and 8" floppy disk drives, and
provides all clocks required by the industry standard
FDC765A and FDC7265 floppy disk controllers.
The FDC92C49 incorporates all the active components
necessary to implement analog floppy disk data separation, eliminating the need for discrete transistors. Only a

521

crystal and a few external resistors and capacitors are
required. Using the FDC92C49 and a floppy disk controller
chip, a system designer can build a highly reliable, cost efficient double or single density floppy disk data subsystem
requiring no tuning adjustments.
Six different user selectable values for write precompensalion assure reliable positioning of data when writing to
disk.

I

I

~~~~I~r~~~~g~sa~~~Z~~?fi~~n~ fg~~~~~\~u~To~n~~r~~e~si:n~le~;6e~!~I:~:~~~~~ i>'~i~~o~~~~i~~ih~~; b~en~~~~:'~1:~

checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore,
such information does not convey to the purchaser of the products described any license under the patent rights of
SMC or others. SMC reserves the right to make changes at any time in order to improve design and supply the best
product possible.

522

FDC9266

Single/Double Density Enhanced Floppy Disk
Controller
PIN CONFIGURATION
FEATURES

o Combination Floppy Disk Controller and Floppy Disk Interface
o Software compatible with industry standard FDC 765A
o On chip digital data separator
o
o
o
o
o

o

o
o

o

eliminates critical analog
adjustments
On-chip drive control logic
reduces component count.
IBM compatible in both single
and double density recording
formats
Programmable data record
lengths: 128,256, 512, or 1024
bytes/sector
Multi-sector and rl,lulti-track
transfer capability
Controls up to 4 floppy disk drives
Data Scan Capability-will scan a
single sector or entire track's
worth of data fields, comparing
on a byte by byte basis, data in
the processor's memory with the
data read from the diskette
Data transfers in DMA or nonDMAmode
Single 8 MHz TTL clock input
Single + 5 Volt power supply

RESET
RD
WR

3
4
Ao 5
WE
DBo 6
Po
DB, 7
iSSlDRT DB, 8
8MHz
DB, 9
MINI
DB, 10
NC
DB511
vss
DB,12
TEST
DB,13
INT
ORO 14
lOX
DACK 15
TC
TC 16
lOX 17
INT 18
TEST 19
GND 20

CS

HDl
FRISTP
lCTIDIE
RWISEEK
Vee
NC
RST
RD
WR

3938373635343332313029
40
28
27
26
25
24
23

CS

3
4
5

A0

6

7 8 9 1011 12 13 14 15 16 17

18

PACKAGE: 44-pin PlCC

o Parallel Seek operations on up to
o

four drives
Compatible with most
microprocessors

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

Vee
RWISEEK
lCTIDIR
FRISTP
HDl
ROY
WPiTS
FlTITRo
P2
P1
WDOUT
uSo
US,
HD
MFM
WE
P0
DSKD
ClK
MINI

PACKAGE: 4o-pin D.!'P.

o GOPLAMOS' n-channel silicon
gate technology
o Available in 40-pin Dual-in-Line
package and 44-pin PLCC

GENERAL DESCRIPTION
The FDC 9266 is a monolithic combination of the industry
standard FDC 765A Floppy Disk Controller and the FDC
9229 Floppy Disk Interface Circuit. It preserves all of the
processor hardware and software interfaces to the FOG
765A, and contains on-chip circuitry to simplify drive
interfacing.
These on-chip enhancements include a digital data
separator, compatible with 5.25" and 8" drives. The data
separator separates both FM (Single Density) and MFM
(Double Density) encoded data, and requires no external
adjustments.
The FDC 9266 also allows variable write precompensation,
which is track selectable.
These enhancements greatly reduce the number of components required to interface floppy disks to a microprocessor system.
There are 15 separate commands which the FOG 9266 will
execute. Each of these commands requires multiple 8-bit

bytes to fully specify the operation which the processor
wishes the FOG to perform. The following commands are
available:
Read Data
Read 10
Read Deleted Data
Read a Track
Scan Equal
Scan High or Equal
Scan Low or Equal
Specify

Write Data
Format a Track
Write Deleted Data
Seek
Recalibrate (Restore to Track 0)
Sense Interrupt Status
Sense Drive Status

Address mark detection circuitry is internal to the FDC
which simplifies the read electronics. The track stepping
rate, head load time, and head unload time may be programmed by the user. The FOG 9266 offers many additional features such as multiple sector transfers in both read
and write with a single command, and full IBM compatibility
in both single and double density modes.
523

-

.~~~

. .-

..

~~~~~~~~~~~---~~~~-

REGISTERS

OBO_7

_____ DSK DATA
DATA
SEPARATOR

SERIAL
INTERFACE
CONTROLLER

COUNT

ORa

~

AND
PRECOMP
LOGIC

DACi<

WDOUT

_PO
_P1
_P2

WRITE PROTECT/TWO SIDE

AD

FAULT/TRACK 0
MINI

UNIT SELECT 0
UNIT SELECT 1

eLK
Vee

R'WISEEK
HEAO LOAD
HEADSELECT

GNO

LOW CURRENT/DIRECTlON
FAULT RESET/STEP

BLOCK DIAGRAM

DRIVE

~§~~~~~~~~~~

FOC 9266

~==========:~ FLT
RST
STEP
~

RW/SEEKI-_...._ - '

r~=~~=======:~ LOW
DIR CUR

WP/TS~~~~~~~~~JJ

FLTiTRO
FR/STEP
LCTIDIR

P0l-_ _ _ _ _ _ _

~

Pl ~--------l.-<>

OBO·
DB?

PRECOMPENSATION
SELECT

P2~-------_1~

RDY
IDX
WE
HD

WPRT

2
SIDED
TRK
00
FAULT

RDY
IDX
WE

SIDE SEL
HDL~----------------------~~HLD

INT

INT

o

CS
R5

cs

US1~---------~

RD

USO~---------~

WR

Wii

AO

AO

DRO
OACK

TC
RESET

E

C

o

~

R
DSKD~

~-----------I

~===========:l
-c

__________________

RAW READ

DRO
DACK WDOUT~-----------------~ :><>----01
TC
MINII-----------f-i
RDY
RST
MFM
IDX
WE
LATCH
SIDE SEL

r-__________
oBO-087

TYPICAL APPLICATION

524

DRSEL4
oRSEL2
oRSEL 1
DRSEL3

WDATA
RDY
IDX
WE
SIDE

~MOTORON

DESCRIPTION OF PIN FUNCTIONS
PIN
SYMBOL
RST

2

Reset

INPUT/
OUTPUT
Input

CONNECTION
TO
Processor

RD

Read

InputCD

Processor

3

WR

Write

InputCD

Processor

4

CS

Chip Select

Input

Processor

5

Ao

Data/Status Reg
Select

InputCD

Processor

DBa-DB,

Data Bus

Processor

14

DRQ

DMA

15

DACK

DataDMA
Request
DMA
Acknowledge

InputCD
Output
Output
Input

DMA

16

TC

Terminal Count

Input

DMA

17

IDX

Index

Input

FDD

18

INT

Interrupt

Output

Processor

19

TEST

Test

Input

20
21

GND
MINI

Ground
Mini

Input

22

GlK

8MHz
TTL Glock
Raw Data
Pre compensation
Select

Input
Input
Input

FDD
Processor

NO.
1

6-13

23
24,31,32

DSKD
PO,Pl,P2

NAME

Processor

25
26

WE
MFM

Write Enable
MFMMode

Output
Output

FDD

27

HD

Head Select

Output

FDD

US" USa
WDOUT
FlT!TRo

Unit Select
Write Data Out
Fau It!Track 0

Output
Output
Input

FDD
FDD
FDD

WP/TS

Write Protect!
Two-Side

Input

FDD

28,29
30
33

34

525

FUNCTION
Places FDC in idle state. Resets
output lines to FDD to "0" (low).
Does not effect SRT, HUT or HlT
in Specify command. If RDY pin is
held high during Reset, FDC will
generate interrupt 1 .024 ms later.
To clear this interrupt use Sense
Interrupt Status command.
Control signal for transfer of data
from FDC to Data Bus, when
"0" (low).
Control signal for transfer of data to
FDC via Data Bus, when "0" (low).
IC selected when~' (low),
allowing RD and WR to be
enabled.
Selects Data Reg (Ao = 1) or
Status Reg (Ao = 0) contents of
the FDC to be sent to Data Bus.
Bi-DirectionaI8-Bit Data Bus.
DMA Request is being made by
FDC when DRW = "1 '.
DMA cycle is active when "0" (low)
and Controller is performing DMA
transfer.
Indicates the termination of a DMA
transfer when "1" (high). It
terminates data transfer during
Read/Write/Scan command in
DMA or interrupt mode.
Indicates the beginning of a disk
track.
Interrupt Request Generated by
FDC.
This pin is for test purposes only.
Should be left tied high in normal
operation.
D.C. Power Return.
This input, when set to "1" (high),
configures the FDG for operation
with 5.25" floppies. If reset to "0"
(low), then the FDG is configured
for 8" drive operation.
Device clock.
Raw data from drive.
These pins select the amount of
precompensation applied to the
write data.
Enables write data into FDD.
MFM mode when "1;' FM mode
when "0:'
Head 1 selected when "1" (high).
Head 2 selected when "0" (low).
FDD Unit Selected.
Serial clock and data bits to FDD.
Senses FDD fault condition, in
Read/Write mode; and Track 0
condition in Seek mode.
Senses Write Protect status in
Read/Write mode; and Two Side
Media in Seek mode.

DESCRIPTION OF PIN FUNCTIONS
NO.
35

PIN
SYMBOL
ROY

NAME
Ready

INPUTI
OUTPUT
Input

FOO

36

HOL

Head Load

Output

FOO

3?

FRISTP

Fit Reset/Stop

Output

FDO

38

LCT/OIR

Low Currentl
Direction

Output

FOO

39

RW/SEEK

Read Write/SEEK

Output

FOO

40

Vee

CONNECTION
TO

+5V

Note: CD Disabled when CS

FUNCTION

Indicates FOO is ready to send or
receive data.
Command which causes readl
write head in FOO to contact
diskette.
Resets fault F.F. in FOO in Readl
Write mode, contains stop pulses
to move head to another cylinder in
Seek mode.
Lowers Write current on inner
tracks in Read/Write mode,
determines direction head will stop
in Seek mode. A fault reset pulse is
issued at the beginning of each
Read or Write command prior to
the occurrence of the Head Load
signal.
When "1" (high) Seek mode
selected and when "0" (low) Readl
Write mode selected.
DC Power.

= 1.

DESCRIPTION OF INTERNAL REGISTERS

facilitate the transfer of data between the processor and
FDG9266.

The FDG 9266 contains two registers which may be accessed by the main system processor; a Status Register
and a Data Register. The 8-bit Main Status Register contains the status information of the FDG, and may be
accessed at any time. The a-bit Data Register (actually
consists of several registers in a stack with only one register
presented to the data bus at a time), which stores data,
commands, parameters, and FDD status information. Data
bytes are read out of, or written into, the Data Register in
order to program or obtain the results after a particular command. The Status Register may only be read and used to

The relation§bjQ between the Status/Data registers and the
signals RD, WR, and Ao is shown below.

A,

RD

0
0
0

0

1
1
1

1

0
0
0
1

WR
1

0
0
0
1

0

FUNCTION
Read Main Status Register
Illegal
Illegal
Illegal
Read from Data Register
Write into Data Register

The bits in the Main Status Register are defined as follows:
BIT NUMBER
OBo

--

NAME
FDOO Busy

SYMBOL
OoB

DB,

FOO 1 Busy

O,B

DB,

F002 Busy

O,B

OB3

F003 Busy

03B

DB,

FOC Busy

CB

OBs

Execution Mode

EXM

DB,

Data InputlOutput

010

DB,

Request for Master

ROM

DESCRIPTION
FOO number 0 is in the Seek mode. If any of the bits is set
FOC will not accept read or write command.
FOO number 1 is in the Seek mode. If any of the bits is set
FOC will not accept read or write command.
FOO number 2 is in the Seek mode. If any of the bits is set
FOC will not accept read or write command.
FOO number 3 is in the Seek mode. If any of the bits is set
FOC will not accept read or write command.
A read or write command is in process. FOC will not accept
any other command.
This bit is set only during execution phase in non-OMA mode.
When OBs goes low, execution phase has ended, and result
phase was started. It operates only during NON-OMA mode
of operation.
Indicates direction of data transfer between FOC and Data
Register. If 010 = "1" then transfer is from Data Register to
the Processor. If 010 = "0", then transfer is from the
Processor to Data Register.
Indicates Data Register is ready to send or receive data to or
from the Processor. Both bits 010 and ROM should be used
to perform the hand-shaking functions of "ready" and
"direction" to the processor.

The 010 and ROM bits in the Status ~ister indicate when Data is ready and in which direction data will be transferred on the Data
Bus. The max time between the last RD or WR during command or result phase and 010 and ROM getting set or reset is 12 fLuor
this reason every time Main Status Register is read the CPU should wait 12 fLS. The max time from the trailing edge of the last RD in
the result phase to when DB, (FDC Busy) goes low is 12 fLS.
526

COMMAND SEQUENCE
Out
DalalnOut
(010)

Foe and Into Processor

L

Out Processor and In\o FOe
Ready

Reques\ for Masler
(ROM)

:

I
I

~

Ready

---I I:
WR

I 1

~:

::

:

~

I

r I l r-J
,4--J
1
I
\
I
\

I

:

:

I I _. r-I ~
I

1

I: I

AD
1

1
Notes

I

:

0

I

AlB

I

1

I

I

I

,

I

AlB 1 Ale 1 ole

I

I I

I

BI A 1

The FOG 9266 is capable of performing 15 different commands. Each command is initiated by a multi-byte transfer
from the processor, and the result after execution of the
command may also be a multi-byte transfer back to the processor. Because of this multi-byte interchange of information between the FOG 9266 and the processor, it is
convenient to consider each command as consisting of three
phases:
GommandPhase:

1D 1

-Oala register ready to be written Inlo by processor

[[] -Data register not ready to be written Inlo by processor

Execution Phase:

@]-Data register ready lor next data byte to be read by the processor

[QJ -Data register not ready lor next data byte to be mad by processor

Result Phase:

COMMAND SYMBOL DESCRIPTION
SYMBOL
Ao

NAME
Address Line 0

C

Cylinder Number

D
D7- DO

Data
Data Bus

DTL

Data Length

EaT

End of Track

GPL

Gap Length

H
HD

Head Address
Head

HLT

Head Load Time

HUT

Head Unload Time

MF
MT

FM or MFM Mode
Multi-Track

N
NCN

Number
New Cylinder Number

NO
PCN
R
R/W
SC
SK
SRT

Non-DMA Mode
Present Cylinder
Number
Record
Read/Write
Sector
Skip
Step Rate Time

STO
ST1
ST2
ST3

Status 0
Status 1
Status 2
Status 3

STP

USO, US1

Unit Select

DESCRIPTION
Ao controls selection of Main Status Register (Ao = 0) or Data Register
(Ao = 1).
C stands for the current/selected Cylinder (track) number 0 through 76 of
the medium.
o stands for the data pattern which is going to be written into a Sector.
8-bit Data Bus, where 0 7stands for a most significant bit, and Do stands for a
least significant bit.
When N is defined as 00, DTL stands for the data length which users are
going to read out or write into the Sector.
EaT stands for the final Sector number on a Cylinder. During Read or Write
operation FDC will stop date transfer after a sector # equal to EaT.
GPL stands for the length of Gap 3. During Read/Write commands this value
determines the number of bytes that vcas will stay low after two CRC bytes.
During Format command it determines the size of Gap 3.
H stands for head number 0 or 1, as specified in 10 field.
HD stands for a selected head number 0 or 1 and controls the polarity of pin
27. (H = HD in all command words.)
HLT stands for the head load time in the FDD (2 to 254 ms in 2 ms
increments).
HUT stands for the head unload time after a read or write operation has
occurred (16 to 240 ms in 16 ms increments).
If MF is low, FM mode is selected, and if it is high, MFM mode is selected.
If MT is high, a multi-track operation is to be performed. If MT = 1 after
finishing Read/Write operation on side 0 FDC will automatically start
searching for sector 1 on side 1.
N stands for the number of data bytes written in a Sector.
NCN stands for a new Cylinder number, which is going to be reached as a
result of the Seek operation. Desired position of Head.
NO stands for operation in the Non-DMA Mode.
PCN stands for the Cylinder number at the completion of SENSE
!NTERRUPT STATUS Command. Position of Head at present time.
Rstands for the Sector number, which will be read or written.
R/W stands for either Read (R) or Write (W) signal.
SC indicates the number of Sectors per Cylinder.
SK stands for Skip Deleted Data Address Mark.
SRT stands for the Stepping Rate for the FDD. (1 to 16 ms in 1 ms
increments.) Stepping Rate applies to all drives, (F = 1 ms, E = 2 ms, etc.).
ST 0-3 stand for one of four registers which store the status information after
a command has been executed. This information is available during the
result phase after command execution. These registers should not be
confused with the main status register (selected by Ao = 0). ST 0-3 may be
read only after a command has been executed and contain information
relevant to that particular command.
During a Scan operation, if STP = 1, the data in continguous sectors is
compared byte by byte with data sent from the processor (or DMA); and if
STP = 2, then alternate sectors are read and compared.
US stands for a selected drive number 0 or 1.

527
- - - - - - - - - - - - - - ------

The FOG receives all information
required to perform a particular
operation from the processor.
The FOG performs the operation
it was instructed to do.
After completion of the operation,
status and other housekeeping
information are made available to
the processor.

I

INSTRUCTION SET CD ®

I

DATA BUS

PHASE

DO

I
I

L
REMARKS

REMARKS

READ DATA
Command

READ A TRACK

W

MT

MF

SK

0

W

X

X

X

X

w

====H====

w

w
w
w
iN
w

HO

USl

usa

=====E~T=====

to Command execution. The

4 byle$ are commanded against
header on Floppy Di$k.

====~p~====

Data-transfer between the
FDD and main-system
R

R

R

2
===5T5T 1====
=
===C=====
---------5TO~--------

W

w
w
w
w
w
w
w
w

Sector 10 information prior

---------DTL.----------

Execution

Result

Command

Command Codes

X

I

DATA BUS

PHASE

o

MF

SK

a

a

a

X

X

X

HD

Command Codes
USl

usa
Sector 10 information prior
to Command execution

~~~;=~-====

DTL--------Data-transfer between I he
FOD and main-system. FDC
reads all data fieldS
from index hole to Ear.

Execution

Status information after
Command execution

--------5TO-----------------5Tl----------

Result
Sector to information after

~5~2'--====

Command execution

Status information after
Command execution
Sector 10 information after
Command el R), and the scan operation is continued. The scan operation continues until one
of the following conditions occur; the conditions for scan are
met (equal, low, or high), the last sector on the track is
reached (EaT), or the terminal count signal is received.

I

If the conditions for scan are met then the FDC sets the SH
(Scan Hit) flag Status Register 2 to a 1 (high), and terminates the Scan Command. If the conditions for scan are not
met between the starting sector (as specified by R) and the
last sector on the cylinder (EOT), then the FDC sets the SN
(Scan Not Satisfied) flag of Status Register 2 to a 1 (high),
and terminates the Scan Command. The receipt of a TERMINAL COUNT signal from the Processor or DMA Controller during the scan operation will cause the FDC to
complete the comparison of the particular byte which is in
process, and then to terminate the command. Table 4 shows
the status of bits SH and SN under various conditions of
SCAN.
COMMAND
Scan Equal
Scan Low or
Equal
Scan High or
Equal

STATUS REGISTER 2
COMMENTS
BIT2 = SN BIT3 = SH
1
0
DFDo = DpROCESSOR
1
0
DFOo cf=. DpROCESSOR

>

0
0

1

0
0

1

0
0

1

0
0

1

DFDo =

DpROCESSOR

DF~D

DpROCESSOR

DFDD

DpRocEssoR

<
>
DFOo =
DFOo >
DFDO <

DpROCESSOR

DpRocEssoR
DpRocEssoR

Table 4
If the FDC encounters a Deleted Data Address Mark on one
of the sectors (and SK = 0), then it regards the sector as
the last sector on the cylinder, sets CM (Control Mark) flag
of Status Register 2 to a 1 (high) and terminates the command. If SK = 1, the FDC skips the sector with the Deleted
Address Mark, and reads the next sector. In the second case
(SK = 1), the FOC sets the CM (Control Mark) flag of Status Register 2 to a 1 (high) in order to show that a Deleted
Sector had been encountered.
When either the STP (contiguous sectors = 01, or alternate sectors = 02 sectors are read) or the MT (Multi-Track)
are programmed, it is necessary to remember that the last
sector on the track must be read. For example, if STP = 02,
MT = 0, the sectors are numbered sequentially 1 through
26, and we start the Scan Command at sector 21; the following will happen. Sectors 21,23 and 25 will be read, then
the next sector (26) will be skipped and the Index Hole will
be encountered before the EaT value of 26 can be read.
This will result in an abnormal termination of the command.
If the EaT has been set at 25 or the scanning started at
sector 20, then;the Scan Command would be completed in
a normal manner.
During the Scan Command data is supplied by either the
processor or DMA Controller for comparison against the
data read from the diskette. In order to avoid having the OR
(Over Run) flag set in Status Register 1, it is necessary to
have the data available in less than 27 fLs (FM Mode) or 13
fLS (MFM Mode). If an Overrun occurs the FDC ends the
command with bits 7 and 6 of Status Register 0 set to 0 and
1, respectively.

The rate at which Step Pulses are issued is controlled by
SRT (Stepping Rate Time) in the SPECIFY Command. After
each Step Pulse is issued NCN is compared against PCN,
and when NCN = PCN, then the SE (Seek End) flag is set
in Status Register 0 to a 1 (high), and the command is terminated. At this point FDC interrupt goes high. Bits DBoDB3 in Main Status Register are set during seek operation
and are cleared by Sense Interrupt Status command.
During the Command Phase of the Seek operation the FDC
is in the FDC BUSY state, but during the Execution Phase
it is in the NON BUSY state. While the FDC is in the NON
BUSY state, another Seek Command may be issued, and
in this manner parallel seek operations may be done on
up to 4 Drives at once. No other command could be issued
for as long as FDC is in process of sending Step Pulses to
any drive.
If an FDD is in a NOT READY state at the beginning of the
command execution phase or during the seek operation,
then the NR (NOT READY) flag is set in Status Register 0
to a 1 (high), and the command is terminated after bits 7
and 6 of Status Register 0 are set to 0 and 1 respectively.
If the time to write 3 bytes of seek command exceeds 150
fLS, the timing between first two Step Pulses may be shorter
than set in the Specify command by as much as 1 ms.

Recalibrate
The function of this command is to retract the read/write
head within the FDD to the Track 0 position. The FDC clears
the contents of the PCN counter, and checks the status of
the Track 0 signal from the FDD. As long as the Track 0 signal is low, the Direction signal remains 0 (low) and Step
Pulses are issued. When the Track 0 signal goes high, the
SE (SEEK END) flag in Status Register 0 is set to a 1 (high)
and the command is terminated. If the Track 0 signal is still
low after 77 Step Pulses have been issued, the FDC sets
the SE (SEEK END) and EC (EQUIPMENT CHECK) flags
of Status Register 0 to both 1s (highs), and terminates the
command after bits 7 and 6 of Status Register 0 is set to 0
and 1 respectively.
The ability to do overlap RECALIBRATE Commands to
multiple FDDs and the loss of the READY signal, as
described in the Seek Command, also applies to the
RECALIBRATE Command.

Seek
The read/write head within the FDD is moved from cylinder
to cylinder under control of the Seek Command. FDC has
four independent Present Cylinder Registers for each drive.
They are clear only after Recalibrate command. The FDC
compares the PCN (Present Cylinder Number) which is the
current head position with the NCN (New Cylinder Number), and if there is a difference performs the following
operation:
PCN < NCN: Direction signal to FDD set to a 1 (high),
and Step Pulses are issued. (Step In.)
PCN > NCN: Direction signal to FDD set to a 0 (low), and
Step Pulses are issued. (Step Out.)
532

Sense Interrupt Status
An Interrupt signal is generated by the FDC for one of the
following reasons:
1. Upon entering the Result Phase of:
a. Read Data Command
b. Read a Track Command
c. Read 10 Command
d. Read Deleted Data Command
e. Write Data Command
f. Format a Cylinder Command
g. Write Deleted Data Command
h. Scan Commands
2. Ready Line of FDD changes state
3. End of Seek or Recalibrate Command
4. During Execution Phase in the NON-DMA Mode
Interrupts caused by reasons 1 and 4 above occur during
normal command operations and are easily discernible by
the processor. During an execution phase in NON-DMA
Mode, DB5 in Main Status Register is high. Upon entering
Result Phase this bit gets clear. Reason 1 and 4 does not
require Sense Interrupt Status command. The interrupt is
cleared by reading/writing data to FDC. Interrupts caused
by reasons 2 and 3 above may be uniquely identified with
the aid of the Sense Interrupt Status Command. This com-

mand when issued resets the interrupt signal and via bits
5, 6, and 7 of Status Register 0 identifies the cause of the
interrupt.
SEEK
END
81TS5

a

INTERRUPT
CODE
BIT6
BIT7
1
1

1

a

a

1

1

a

CAUSE
Ready Line changed state, either
polarity
Normal Termination of Seek or
Recalibrate Command
Abnormal Termination of Seek or
Recalibrate Command

ms in increments of 2 ms (01 = 2 ms, 02 = 4 ms, 03 = 6
mS ... 7F = 254 ms).
The time intervals mentioned above are a direct function of
the clock (ClK on pin 19). Times indicated above are for an
8 MHz clock, if the clock was reduced to 4 MHz (mini-floppy
application) then all time intervals are increased by a factor
of 2.
The choice of OMA or NON-OMA operation is made by the
NO (NON-OMA) bit. When this bit is high (NO = 1) the NONOMA mode is selected, and when NO = 0 the OMA mode
is selected.

Sense Drive Status

Table 5
Neither the Seek or Recalibrate Command have a Result
Phase. Therefore, it is mandatory to use the Sense Interrupt Status Command after these commands to effectively
terminate them and to provide verification of where the head
is positioned (PCN).
Issuing Sense Interrupt Status Command without interrupt
pending is treated as an invalid command.

Specify
The Specify Command sets the initial values for each of the
three internal timers. The HUT (Head Unload Time) defines
the time from the end of the Execution Phase of one of the
ReadlWrite Commands to the head unload state. This timer
is programmable from 16 to 240 ms in increments of 16 ms
(01 = 16 ms, 02 = 32 ms ... OF = 240 ms). The SRT (Step
Rate Time) defines the time interval between adjacent step
pulses. This timer is programmable from 1 to 16 ms in increments of 1 ms (F = 1 ms, E = 2 ms, 0 = 3 ms, etc.). The
HlT (Head load Time) defines the time between when the
Head load signal goes high and when the Read/Write
operation starts. This timer is programmable from 2 to 254

This command may be used by the processor whenever it
wishes to obtain the status of the FOOs. Status Register 3
contains the Drive Status information stored internally in
FOC registers.

Invalid
If an invalid command is sent to the FOC (a command not
defined above), then the FOC will terminate the command
after bits 7 and 6 of Status Register 0 are set to 1 and 0
respectively. No interrupt is generated by the FOC 9266
during this condition. Bit 6 and bit 7 (010 and ROM) in the
Main Status Register are both high ("1") indicating to the
processor that the FOC 9266 is in the Result Phase and the
contents of Status Register 0 (STO) must be read. When
the processor reads Status Register 0 it will find an 80 hex
indicating an invalid command was received.
A Sense Interrupt Status Command must be sent after a
Seek or Recalibrate Interrupt, otherwise the FOC will consider the next command to be an Invalid Command.
In some applications the user may wish to use this command as a No-Op command, to place the FOC in a standby
or no operation state.

STATUS REGISTER IDENTIFICATION
NO.
D7

BIT
NAME
Interrupt Code

SYMBOL
IC

D,

D5

Seek End

SE

D,

Equipment Check

EC

D3

Not Ready

NR

D,
D,
Dc

Head Address
Unit Select 1
Unit Select a

HD
US 1

usa

DESCRIPTION
D7 = a and D, = a
Normal Termination of Command, (NT). Command was completed
and properly executed.
D7 = a and D, = 1
Abnormal Termination of Command, (AT).
Execution of Command was started, but was not successfully
completed.
D7 = 1 and D, = a
Invalid Command issue, (IC). Command which was issued was
never started.
D7 = 1 and D, = 1
Abnormal Termination because during command execution the
ready signal from FDD changed state.
When the FDC completes the SEEK Command, this flag is set to
1 (high).
If a fault Signal is received from the FDD, or if the Track a Signal
fails to occur after 77 Step Pulses (Recalibrate Command) then this
flag is set.
When the FDD is in the not-ready state and a read or write
command is issued, this flag is set. If a read or write command is
issued to Side 1 of a single sided drive, then this flag is set.
This flag is used to indicate the state of the head at Interrupt.
These flags are used to indicate a Drive Unit. Number at Interrupt.

533

I

BIT
NAME

NO.

0,

End of Cylinder

Dc

05

Data Errror

0,

OverRun

03
O2

No Data

0,

Not Writable

Do

Missing Address Mark

0,
06

Control Mark

05
0,

Data Error in Data Field
Wrong Cylinder

03

Scan Equal Hit

0,

Scan Not Satisfied

0,

Bad Cylinder

Do

Missing Address Mark
in Data Field

07

Fault

06

Write Protected

05

Ready

0,

Track 0

03

Two Side

0,

Head Address

0,

Unit Select 1

Do

Unit Select 0

SYMBOL
DESCRIPTION
STATUS REGISTER 1 (CO NT.)
EN
When the FDC tries to access a Sector beyond the final Sector of a
Cylinder, this flag is set.
Not used. This bit is always 0 (low).
DE
When the FDC detects a CRC error in either the 10 field or the data
field, this flag is set.
If the FDC is not serviced by the main·systems during data
OR
transfers, within a certain time interval, this flag is set.
Not used. This bit always 0 (low).
NO
During execution of READ DATA, WRITE DELETED DATA or
SCAN Command, if the FDC cannot find the Sector specified in the
lOR Register, this flag is set.
During executing the READ 10 Command, if the FDC cannot read
the 10 field without an error, then this flag is set.
During the execution of the READ A Cylinder Command, if the
starting sector cannot be found, then this flag is set.
During execution of WRITE DATA, WRITE DELETED DATA or
NW
Format A Cylinder Command, if the FDC detects a write protect
signal from the FDD, then this flag is set.
MA
If the FDC cannot detect the 10 Address Mark after encountering
the index hole twice, then this flag is set.
If the FDC cannot detect the Data Address Mark or Deleted Data
Address Mark, this flag is set. Also at the same time, the MD
(Missing Address Mark in Data Field) of Status Register 2 is set.
STATUS REGISTER 2
Not used. This bit is always 0 (low).
During executing the READ DATA or SCAN Command, if the FDC
CM
encounters a sector which contains a Deleted Data Address Mark,
this flag is set.
If the FDC detects a CRC error in the data field then this flag is set.
DO
This bit is related with the NO bit, and when the contents of C on the
WC
medium is different from that stored in the lOR, this flag is set.
SH
During execution, the SCAN Command, if the condition of "equal"
is satisfied, this flag is set.
During executing the SCAN Command, if the FDC cannot find a
SN
Sector on the cylinder which meets the condition, then this flag
is set.
This bit is related with the NO bit, and when the content of C on the
BC
medium is different from that stored in the lOR and the content of C
is FF, then this flag is set.
When data is read from the medium, if the FDC cannot find a Data
MD
Address Mark or Deleted Data Address Mark, then this flag is set.
STATUS REGISTER 3
FT
This bit is used to indicate the status of the Fault signal from
the FDD.
This bit is used to indicate the status of the Write Protected signal
WP
from the FDD.
RY
This bit is used to indicate the status of the Ready signal from
the FDD.
TO
This bit is used to indicate the status of the Track 0 signal from
the FDD.
This bit is used to indicate the status of the Two Side signal from
TS
the FDD.
This bit is used to indicate the status of Side Select signal
HD
to the FDD.
This bit is used to indicate the status of the Unit Select 1 signal
US1
to the FDD.
This bit is used to indicate the status of the Unit Select 0 Signal
usa
to the FDD.

534

PROCESSOR INTERFACE
Ouring Command or Result Phases the Main Status Register (described earlier) must be read by the processor
before each byte of information is written into or read from
the Oata Register. After each byte of data read or written to
Oata Register, CPU should wait for 12 /Ls before reading
MSR. Bits 06 and 07 in the Main Status Register must be
in a 0 and 1 state, respectively, before each byte of the command word may be written in the FOC 9266. Many of the
commands require multiple bytes, and as a result the Main
Status Register must be read prior to each byte transfer to
the FOC 9266. On the other hand, during the Result Phase,
06 and 07 in the Main Status Register must both be 1's (06
= 1 and 07 = 1) before reading each byte from the Oata
Register. Note, this reading of the Main Status Register
before each byte transfer to the FOC 9266 is required in
only the Command and Result Phases, and NOT during the
Execution Phase.
Ouring the Execution Phase, the Main Status Register need
notbe read. If the FOC 9266 is inthe NON-OMAMode, then
the receipt of each data byte (if FOC 9266 is reading data
from FOO) is indicated by an Interrupt signal on pin 18 (INT
= 1). The generation of a Read signal (RO = 0) or Write
signal (WR = 0) will reset the Interrupt as well as output the
Oata onto the Oata bus. If the processor cannot handle
Interrupts fast enough (every 13 /Ls) for MFM and 27 /Ls for
FM mode, then it may poll the Main Status Register and then
bit 07 (ROM) functions just like the Interrupt signal. If a Write
Command is in process then the WR signal performs the
reset to the Interrupt signal.
If the FOC 9266 is in the OMA Mode, no Interrupts are generated during the Execution Phase. The FOC 9266 generates ORO's (OMA Requests) when each byte of data is
available. The OMA Controller responds to this request with
both a OACK = 0 (OMA Acknowledge) and a RO = 0 (Read
sl9..o.£l). When the OMA Acknowledge signal goes low
(OACK = 0) then the OMA Request is reset (ORO = 0). If
a Write Command has been programmed then a WR signal
will appear instead of RO. After the Execution Phase has
been completed (Terminal Count has occurred) or EaT
sector was read/written, then an Interrupt will occur (INT =
1). This signifies the beginning of the Result Phase. When
the first byte of data is read during the Result Phase, the
Interrupt is automatically reset (INT = 0).

It is important to note that during the Result Phase all bytes
shown in the Command Table must be read. The Read Oata
Command, for example has seven bytes of data in the Result
Phase. All seven bytes must be read in order to successfully complete the Read Oata Command. The FOC 9266
will not accept a new command until all seven bytes have
been read. Other commands may require fewer bytes to be
read during the Result Phase.
The FOC 9266 contains five Status Registers. The Main
Status Register mentioned above may be read by the processor at any time. The other four Status Registers (STO,
ST1, ST2, and ST3) are only available during the Result
Phase, and may be read only after completing a command.
The particular command which has been executed determines how many of the Status Registers will be read.
The bytes of data which are sent to the FOC 9266 to form
the Command Phase, and are read out of the FOC 9266 in
the Result Phase, must occur in the order shown in the
Command Table. That is, the Command Code must be sent
first and the other bytes sent in the prescribed sequence.
No foreshortening of the Command or Result Phases are
allowed. After the last byte of data in the Command Phase
is sent to the FOC 9266, the Execution Phase automatically
starts. In a similar fashion, when the last byte of data is read
out in the Result Phase, the command is automatically
ended and the FOC 9266 is ready for a new command.

POLLING FEATURE OF THE FDC 9266
After the Specify command has been sent to the FOC 9266,
the Unit Select line USO and US1 will automatically go into
a polling mode. In between commands (and between step
pulses in the SEEK command) the FOC 9266 polls all four
FOO's looking for a change in the Ready line from any of
the drives. If the Ready line changes state (usually due to
a door opening or closing) then the FOC 9266 will generate
an interrupt. When Status Register 0 (STO) is read (after
Sense Interrupt Status is issued), Not Ready (NR) will be
indicated. The polling of the Ready line by the FOC 9266
occurs continuously between commands, thus notifying the
processor which drives are on or off line. Each drive is polled
every 1.024 ms except during the Read/Write commands.

AC TEST CONDITION
INPUT/OUTPUT

CLOCK
3.0V _ _____,

2.4V

O.3V _ _ _J

0.45V

ACTESTING
Inputs are driven at 2.4V for a logic "1" and OA5V for a logic "0." Timing measurements are made at 2.0V for a logic "1" and O.BV for a logic "0:
Clocks are driven at 3.0V for a logic "1" and O.3V for a logi,c "0," Timing measurements are made at 2.4V for a logic "1" and O.65V for a logiC "0,"

535

PRECOMPENSATION
The desired precompensation delay is determined by the
state of the PO, Pi and P2 inputs. logic levels present on
these pins may be changed dynamically as long as the
inputs are stable during the time the floppy disk controller
is writing to the drive,

P2

P1
PO
PRECOMP VALUE
0
0
,ONS
0
1
125 NS
1
0
2sbNS,
1
1
375 NS'
1
0
0
500 NS'
WRITE PRECOMPENSATICN VALUE SELECTION

o
o
o
o

'NOTE: Precomp values of 375 ns and 500 ns are valid only with 5'14' drives,

DATA SEPARATOR
The FDC 9266 detects the leading (negative) edges of the The SEPClK frequency is nominally '116 the ClK frequency,
disk data pulses and adjusts the phase of the internal clock Depending on the internal timing correction, the duration of
any SEPClK half-cycle may vary from a nominal of 8 to a
to provide the internal SEPClK signal.
Separate short- and long-term timing correctors assure minimum of 6 and a maximum of 11 internal clock cycles,
accurate clock separation,
ClK
SEPClK'~r---------IL

SEPO' - - - - - - - ,

LJ

I

____________S-----------------~L-

I

W

_______

...._ _ _ _ _ _ _ _ _""'1

W

~I always two internal clock cycles

'internal signals to FOC 9266

ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS'
Operating Temperature, , . , , , .. , , , .. , , , . , , , , , , . , .. ' , , , , ' , , , , .. , , , , ' , ' , , , ' , ' , ' , ' , , , .. , , , , .. , , . ' , ' , , , ' , . , , . ' , , , ., - 10°C to + 70°C
Storage Temperature, ' . ' .. ' , ' , , , , , .. , , , , ' .... , ' . ' , ' , , , , .. ' .. , ' .. , , , .. , , , .. , , , , , , , , , , , , , .. , , . , , . , , , , , . , , . , , . ,. - 55°C to + 150°C

~:: ~~~u0~~~~2:s :::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: : : ~:~:~ : ; ~~::~

Supply Voltage Vee ...... ' , ' , .. , , .. , , , , . , , , , .. , , . , , , , , , , , , , . , , , . , , , , . , , , , , , , , .. , , , ' , ' .. , , , , , , , , , , ' , , . , , . , , , , , " - 0,5 to + 7 Volts
Power Dissipation , , , , , , , , , . , ' , , . , , , , , , , , , ... , , .. , , , , , , , . , , . , , , . , , , , . , , .. , , , , , , .. , , , , , ' .. , , , , , .. , , , , , , , . , , , , , , .. , , . , , , ' , " 1 Watt
To = 25°C
'COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device, This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied, Exposure to absolute maximum rating conditions ior extended periods may affect device
reliability,
DC CHARACTERISTICS Ta = -10°C to
PARAMETER
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Voltage
(CLK + WR Clock)
Input High Voltage
(CLK + WR Clock)
Vee Supply Current

+ 70°C; Vec = + 5V ± 5% unless otherwise specified.
SYMBOL
V,l
V,H
Val
VaH

MIN
-0,5
2,0

LIMITS
TYPCD

VIL(~J)

2.4
-0,5

MAX
0,8
Vee + 0,5
0.45
Vee
0,65

UNIT
V
V
V
V
V

V1H(q)

2.4

Vee + 0,5

V

200
10
-10
10
-10

mA
/LA
/LA
/LA
/LA

Icc

Input Load Current
(All Input Pins)

III

High Level Output Leakage Current
Low Level Output Leakage Current

iLOH
iLOL

TEST
CONDITIONS

10l
10H

= 2,0 mA
=

-

200 /LA

VIN = Vee
V,N = OV
VOUT = Vee
VOUT = + 0.45V

NOTE: CDTYPlcal values for To = 25°C and nominal supply voltage,
DC CHARACTERISTICS Ta = 25°C; fe = 1 MHz; Vce = OV
PARAMETER
Clock Input Capacitance
Input Capacitance
Output Capacitance

SYMBOL
GIN ')
C'N

MIN

COUT

536

LIMITS
TYP

MAX
20
10
20

UNIT
pF
pF
pF

TEST
CONDITIONS
All Pins Except Pin
Under Test Tied to
ACGround

ACCHARACTERISTICSTa

=

-10°C to +70°C;Vcc

PARAMETER
Clock Period
Clock Active (High, Low)
Clock Rise Time
Clock Fall Time
A a, CS, DACK Set Up Time to RD I
A a, CS, DACK Hold Time from RD 1
RDWidth
Data Access Time from RD I
DB to Float Delay Time from RD 1
Aa, CS, DACK Set Up Time to WR I
Aa, CS, DACK Hold Time to WR 1
WRWidth
Data Set Up Time to WR 1
Data Hold Time from WR 1
INT Delay Time from RD 1
INT Delay Time from WR 1
ORa Cycle Time
ORa Delay Time from DACK I
TCWidth
Reset Width
USa. Hold Time to RW/SEEK 1
SEEK/RW Hold Time to LOW
CURRENTIDIRECTION 1
LOW CURRENT/DIRECTION Hold
Time to FAULT
RESET/STEP 1
USa. Hold Time from FAULT RESET/
STEP 1
STEP Active Time (High)
STEP Cycle Time
FAULT RESET Active Time (High)
USa. Hold Time After SEEK
Seek Hold Time from DIR
DIR Hold Time after STEP
Index Pulse Width
RD I Delay from ORa
WR 1 Delay from ORa
WE or RD Response Time
from ORa 1

SYMBOL

ey

lOST

1.0

fLS

TSTU

5.0

fLS

TSTP

6.0
33
8.0
15
30
24
10
800
250

TAST
Tus
TSD

TEST
CONDITIONS

C L = 100 pF
C L = 100pF

(Vey

fLS
fLS

8 MHz Clock Period

Tsc
T'R
Tsu

TDs

TSTD
T1DX
TMR
TMw

TMRW

7.0

©

©
10

fLS
fLS
fLS
fLS
fLS
fLS

8 MHz Clock Period

CY
ns
ns
12

8 MHz Clock Period

fLS

NOTES: CD Typical values for Ta = 25°C and nominal supply voltage.
© Under Software Contra\. The range is from 1 ms to 16 ms for 8" floppies, and 2 to 32 ms for 51/." floppies.

537

TIMING DIAGRAMS

PROCESSOR WRITE OPERATION

PROCESSOR READ OPERATION

CLOCK
elK

SEEK OPERATION

USa, 1

RW/SEEK

~

I

j\--!I----

X----;:-----

_'DSr-

-----X

1

STEP
________

f----

tsc----._I

FL T RESET

FILE UNSAFE RESET

OR AD

~S_TD----~I~1

--1

f - I.....- - -

FAULTRESET=

WR

t - -~TU---i

--1
'STP

aRa

I

:1\:1

----11

'DST

DMA OPERATION

--i 'su r-

--i'SDt--

DIRECTION

t'l.,-----

STABLE

--j,usf--II

I

I

:

I

~
~TFR~

TERMINAL COUNT

INDEX

~
I
I
I
TIDX

1

TC

TIDX

H~

RESET

H

For more information, please consult:
Technical Note 6-1 (Digital Data Separation)

RESET

---'!
--I

+--

I-- TRST

Circuit diagrams utilizing SMC products are inc.luded as a means of illustrating typical semiconducto~ applications; consequently complete information suffIcient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility IS
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under.the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve desIgn and supply the best product possible.

538

Foe 9267
PRELIMINARY

Single/Double Density· Floppy Disk Controller
With High Performance Analog Data Separator
PIN CONFIGURATION

FEATURES

D IBM Compatible in both Single and Double Density

Vee

RESET
RO
WR
CS
AO
OBO
OB1
OB2
OB3
OB4
OB5
OB6

Recording Formats

D High Performance self tuning Analog Data Separator

D Software compatible with Industry Standard FDC
765A

D Programmable Data Record Lengths: 128,256,512,
or 1024 Bytes/Sector

D Multi-Sector and Multi-Track Transfer Capacity
D Drive Up to 4 Floppy Disks

RW/SEEK
LCT/OIR
FRISTP
HOL
ROY
WP/TS
FLT/TRO
MINI
PO
VCOCLK

usa

DB?

US1
HO
WOOUT
WE
PU
ROIN
CLK(16 MHz)
PO

ORQ
OACK
TC

D Data Scan Capability - will scan a Single Sector or an
entire cylinder's worth of data fields, comparing on a
Byte to Byte Basis, data in the Processor's Memory
with data read from the Diskette

lOX
INT
P1
GNO

D Data Transfer in DMA or Non-DMA Mode

PACKAGE: 40-pin O.LP.

D Parallel Seek Operations on up to four drives
D Compatible with Most Microprocessors

()

- t: t:

t--

::>
0

:z:

0

oa...~o~Uo(fJu)OlJ..
a:~lLa...a...Z3:=:I:::JI~

D Single Phase 16 MHz Clock
D Single + 5 Volt Power Supply

HDL
FAISTP

D Available in 40-Pin Dual-in-Line Package

LeT/DIE
AWISEEK
v~

D COPLAMOS®n-Channel Silicon Gate Technology

NC
AST

AD
WA

cs
AD

3938373635343332313029
28
27
26
25
24
23
22
21
20
5
19
18
6
7891011121314151617

40
41
42

""

-

'" '" "'0

'" '"

....

WE
Po
OS/ORT

BMHz
MINI
NC
VSS
TEST
INT
IDX
TC

01:::.:::

~~~~~z~~~~~
Cl

PACKAGE: 44-pin PLCC

GENERAL DESCRIPTION
The FOC 9267 is an enhanced floppy disk controller that
integrates the SMC 765A Floppy Disk Controller with a high
performance data separator. The controller portion contains the circuitry for interfacing a micro-processor to four
floppy disk drives. The high performance, self tuning analog data separator is capable of recovering data with 2fLS,
4fLS and 8fLS bit cells. This allows the device to be used in
systems with 3.5", 5.25" or 8" drives that are single or double sided using FM or MFM encoding.
The FDC 9267 is 100% software compatible with the industry standard SMC FDC 765A. This ensures full diskette and
system level compatibility.
The FDC 9267 provides hand-shaking signals for DMA
purposes. It will operate in OMA or non-DMA mode. In non539

DMA mode an interrupt is generated each time a byte is
available.
There are 15 commands the FDC 9267 is capable of performing. Each command requires multiple byte transfers to
specify the operation. The following commands are
available:
Read Data
Write Data
Read 10
Format Track
Write Deleted Data
Read Deleted Data
Seek
Read Track
Scan High or Equal
Scan Equal
Scan Low or Equal
Sense Drive Status
Specify Sense
Interrupt Status
Recalibrate

TYPICAL APPLICATION

t 5VREF

C1
0.0022111

.5,

PMPDWN{H)

,5,
R8
1K

-,-PM::::.P..:::UP-,,(l"-)_ _- [ 2N~~04

ANALOG DATA SEPARATOR SCHEMATIC

RS
20011

i%

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

NAME

SYMBOL

1

RESET

RESET

2

READ

RD

3

WRITE

WR

4

CHIP SELECT

CS

5

ADDRESS 0

AO

6,7,8,9,10,11,
12,13
14

DATA BUS 0-7

DBO-7

DMA REQUEST

DRQ

15

DACK

16

DMA
ACKNOWLEDGE
TERMINAL COUNT

TC

17

INDEX

lOX

18

INTERRUPT

INT

19
20
21
22
23
24
25
26

PRECOMP 1
GROUND
PUMPDOWN
CLOCK
RAW DATA IN
PUMP UP
WRITE ENABLE
WRITE DATA OUT

P1
GND
PO
CLK
RDIN
PU
WE
WDOUT

27

HEAD SELECT

HD

28,29
30

UNIT SELECT
VCO CLOCK

US1-0
VCOCLK

31
32

PRECOMP 0
MINI

PO
MINI

DESCRIPTION
This input, when high, places the FDC 9267 into an idle state and
forces the output signals to the floppy drive low. Reset does not
affect SRT, HUT or HLT in Specify command. If the ROY pin is held
high during reset, the FDC 9267 will generate an interrupt 1.024ms
later. To clear this interrupt use the Sense Interrupt Status
Command.
This input, when low, allows data to transfer from the FDC 9267 to
the data bus.
This input, when low, allows data to transfer from the data bus to the
FDC 9267.
This input, when low, selects the FDC 9267 thus enabling RD and
WR.
This input, when high, allows the data register to be read or written.
When low, it allows the status register to be read.
Bi-directional 8 bit data bus.
This output, when high, indicates that the FDC 9267 is requesting a
DMA transfer. To allow easier system interfacing, and to insure full
compatibility, DRQ is typically active 1 fLs prior to the data byte being
available (during disk read operations).
This input, when low, indicates to the FDC 9267 that a DMA request
is being acknowledged.
When high, this input indicates the termination of a DMA, polled, or
interrupt driven transfer. It terminates data transfer during READ/
WRITE/SCAN command in DMA or interrupt mode.
This input, when high, informs the FDC 9267 of the beginnning of
the disk track.
This output, when high, indicates the FDC 9267 is requesting an
interrupt.
Input used to select desired precompensation value. Refer to table 6.
This output, when high, causes the VCO frequency to decrease.
This input is a 16mhz square wave ciock.
This input is the raw read data from the floppy drive.
This output, when low, causes the VCO frequency to increase.
This output, when high, enables the floppy disk drive to write data.
This output is the precompensated serial data signal to the floppy
disk drive.
When high, this outputs selects head 1. When low, head 2 is
selected.
These two outputs are the encoded form of unit select 0 thru 3.
This input is the VCO signal from the VCO. The VCO frequency is
nominally 2 mHz.
Input used to select desired precompensation value. Refer to table 6.
This input, when high, configures the FDC 926,7 for operation with
floppy disk data rates of 125 Kbs or 250 Kbs.

540

DESCRIPTION OF PIN FUNCTIONS
NAME
FAULT/TRACK 0

SYMBOL
FLT/TRO
WP/TS

35

WRITE PROTECT
TWO SIDED
READY

36

HEAD LOAD

HDL

37

FAULT RESET/STEP

FR/STP

38

LOW CURRENT/
DIRECTION

LCT/DIR

39

READ WRITE/SEEK

RW/SEEK

40

POWER

Vcc

PIN NO.
33
34

ROY

DESCRIPTION
This input senses floppy disk drive fault conditions in read/write
mode; and track 0 in seek mode.
This input senses write protect status in the read/write mode; and
two sided media in the seek mode.
When high, this input indicates the floppy disk drive is ready for
transfers.
When high, this output causes the floppy disk read/write head to
contact the disk.
:
When high and in the read/write mode this output will reset the fault
flip flop. In the seek mode this output is used to step the head.
In the read/write mode, this output lowers the write current when
writing on the inner tracks. In the seek mode, this output determines
the direction the head will step. A fault reset pulse is issued at the
beginning of each read or write command prior to the occurance of
the head load signal.
When this output is high the seek mode is selected. When low, the
read/write mode is selected.

NOTE: For optimum performance, stray capacitance (on the printed
circuit board) must be minimized between the PUMPDOWN and

the PUMPUP pins. Printed circuit board traces to these pins
should be as short and as symetrical as possible.

DESCRIPTION OF INTERNAL REGISTERS

Status Register may only be read and used to facilitate
the transfer of data between the processor and FDC.
The relationship~etween the Status Data Registers
and the signals ~D, WR, and Ao is shown below.

The FDC 9267 contains two registers which may be
accessed by the main system processor; a Status
Register and a Data Register. The a-bit Main Status
Register contains the status information of the FDC,
and may be accessed at any time. The a-bit Data Register (actually consists of several registers in a stack
with only one register presented to the data bus at a
time), which stores data, commands, parameters, and
FDD status information. Data bytes are read out of, or
written into, the Data Register in order to program or
obtain the results after a particular command. The

AD
0
0
0
1
1
1

RD
0
1
0
0
0
1

WR
1
0
0
0
1
0

FUNCTION
Read Main Status Register
Illegal
Illegal
Illegal
Read from Data Register
Write into Data Register

The bits in the Main Status Register are defined as follows:
BIT NUMBER
DBD

NAME
FDD 0 Busy

SYMBOL
DDB

DB,

FDD 1 Busy

D,B

DB,

FDD 2 Busy

D,B

DB,

FDD 3 Busy

D,B

DB4

FDC Busy

CB

DB5

Execution Mode

EXM

DB,

Data Input/Output

010

DB,

Request for Master

ROM

010 and ROM bits in the Status Register indicate when
Data is ready and in which direction data will be transferred on the Data Bus. When MINI is low, the max
time between the iast RD or WR during command or
result phase and 010 and ROM getting set or reset is

DESCRIPTION
FDD number 0 is in the Seek mode. If any of the bits
are set. FDC will not accept read or write command.
FDD number 1 is in the Seek mode. If any of the bits
are set FDC will not accept read or write command.
FDD number 2 is in the Seek mode. If any of the bits
are set FDC will not accept read or write command.
FDD number 3 is in the Seek mode. If any of the bits
are set FCC will not accept read or write command.
A read or write command is in process. FDC will not
accept any other command.
This bit is set only during execution phase in non-DMA
mode. When DB5 goes low, execution phase has ended,
and result phase was started. It operates only during
NON-DMA modeof operation.
Indicates direction of data transfer between FDC and
Data Register. If 010 = "1" then transfer is from Data
Register to the Processor. If 010 = "0", then transfer is
from the Processor to Data Register.
Indicates Data Register is ready to send or receive data
to or from the Processor. Both bits 010 and ROM should
be used to perform the hand-shaking functions of
"ready" and "direction" to the processor.

I

12f1s. For this reason, every time Main Status Register'
is read the CPU should wait J1p.s. The max time from
the trailing edge of the last RD in the phase to when
DB4 (FDC Busy) goes low is 12f1s. These times must
be doubled (to 24f1s) when MINI is high.

541
- - - - - - - - - - - - - - -..

--------.-~

....... - - - - -...-

...

COMMAND SEQUENCE
Out FDC and Into Processor
Data In Out

L
:-l. I I r;--l Il: 11
~
~
f----! !-+-J !
Out Processor and Inlo FOC

(010)

1I

_~

Request for Master
(ROM)

-

I
I

Ready

:

::

I

1

[ A

[ S [

1
' I

1
11:111111
::
I
1
:
I! I
I

~~
----:Lr ---:-w I I : 1 : \: :
RD~I
Notes:

0

I

I

A

I

lsi

I

I

I

A [ C [ D [ C

I I

I

[D[S[ A

I

[

-Data reglsler ready to be written into by processor

[[] -Data register not ready to be written into by processor

~ -Data register ready for next data byte to be read by the processor

@J -Data register not ready for next data byte to be road by processor

The FOC is capable of performing 15 different commands.
Each command is initiated by a multi-byte transfer from the
processor, and the result after execution of the command
may also be a mUlti-byte transfer back to the processor.
Because of this multi-byte interchange of information
between the FOC and the processor, it is convenient to consider each command as consisting of three phases:
Command Phase:
The FOC receives all information
required to perform a particular
operation from the processor.
Execution Phase:
The FOC performs the operation
it was instructed to do.
Result Phase:
After completion of the operation,
status and other housekeeping
information are made available to
the processor.

COMMAND SYMBOL DESCRIPTION
Ao

SYMBOL

NAME
Address Line 0

C

Cylinder Number

D
D7-DO

Data
Data Bus

DTL

Data Length

EOT

End ofTrack

GPL

Gap Length

H
HD

Head Address
Head

HLT

Head Load Time

HUT

Head Unload Time

MF
MT

FM or MFM Mode
Multi-Track

N
NCN

Number
New Cylinder Number

ND
PCN
R
R/W
SC
SK
SRT

Non-DMA Mode
Present Cylinder
Number
Record
Read/Write
Sector
Skip
Step Rate Time

STO
ST 1
ST2
ST3

Status 0
Status 1
Status 2
Status 3

STP

USO, US1

Unit Select

DESCRIPTION
Ao controls selection of Main Status Register (Ao = 0) or Data Register
(Ao = 1).
C stands for the current/selected Cylinder (track) number 0 through 76 of
the medium.
D stands for the data pattern which is going to be written into a Sector.
8-bit Data Bus, where D, stands for a most significant bit, and Do stands for a
least significant bit.
When N is defined as 00, DTL stands for the data length which users are
going to read out or write into the Sector.
EOT stands for the final Sector number on a Cylinder. During Read or Write
operation FDC will stop data transfer after a sector # equal to EOT.
GPL stands for the length of Gap 3. During ReadlWrite commands this value
determines the number of bytes that VCOs will stay low after two CRC bytes.
During Format command it determines the size of Gap 3.
H stands for head number 0 or 1, as specified in ID field.
HD stands for a selected head number 0 or 1 and controls the polarity of pin
27. (H = HD in all command words.)
HLTstands for the head load time in the FDD (2 to 254 ms in 2 ms
increments).
HUT stands for the head unload time after a read or write operation has
occurred (16 to 240 ms in 16 ms increments).
If MF is low, FM mode is selected, and if it is high, MFM mode is selected.
If MT is high, a multi-track operation is to be performed. If MT = 1 after
finishing Read/Write operation on side 0 FDC will automatically start
searching for sector 1 on side 1.
N stands for the number of data bytes written in a Sector.
NCN stands for a New Cylinder Number, which is going to be reached as a
result of the Seek operation. Desired position of Head.
ND stands for operation in the Non-DMA Mode.
PCN stands for the Cylinder number at the completion of SENSE
INTERRUPT STATUS Command. Position of Head at present time.
R stands for the Sector number, which will be read or written.
R/W stands for either Read (R) or Write (W) signal.
SC indicates the number of Sectors per Cylinder.
SK stands for Skip Deleted Data Address Mark.
SRT stands for the Stepping Rate for the FDD. (1 to 16 ms in 1 ms
increments.) Stepping Rate applies to all drives, (F = 1 ms, E = 2 ms, etc.).
ST 0-3 stand for one of four registers which store the status information after
a command has been executed. This information is available during the
result phase after command execution. These registers should not be
confused with the main status register (selected by Ao = 0). ST 0-3 may be
read only after a command has been executed and contain information
relevant to that particular command.
During a Scan operation, if STP = 1, the data in contiguous sectors is
compared byte by byte with data sent from the processor (or DMA); and if
STP = 2, then alternate sectors are read and compared.
US stands for a selected drive number 0 or 1.

542

INSTRUCTION SET CD @

I

I

DATA BUS

L

PHASE

REMARKS

READ DATA
Command

J

DATA BUS

REMARKS

W

MT

MF

W

w
w
w
w
w
w
w

SK

0

X

X

READ A TRACK

HD

usa

USl

w
w
w
w
w
w

to Command e~eculion. The
4 bytes are commanded against

---------'OT--------- - - - - - - - - GPL-----------------OTL.----------

--------STO----------ST;'====

header on Floppy Disk.

Data-transfer belweer, the
FOD and main-system

W

w
w

Sector 10 mlormatlon prior

Execution

Result

Command

Command Code$

X

o

MF

SK

0

0

0

X

X

X

X

HD

Command Codes
US1

usa

~N~
--------'OT---------=

Sector 10 information prior
to Command execution

====GPL---------

Dn--------

Data-transfer between t he
FDD and main-system. FOC

Execution

reads aU data fields

Status Inform~tlon after
Command ellecullOn

from mdex hole to ear .

--------5T ~

--------STO-=========

Result

Sector 10 mformatlon  R), and the scan operation is continued. The scan operation continues until one
of the following conditions occur; the conditions for scan are
met (equal, low, or high), the last sector on the track is
reached (EaT), or the terminal count signal is received.
546

If the conditions for scan are met then the FDC sets the SH
(Scan Hit) flag Status Register 2 to a 1 (high), and terminates the Scan Command. If the conditions for scan are not
met between the starting sector (as specified by R) and the
last sector on the cylinder (EaT), then the FDC sets the SN
(Scan Not Satisfied) flag of Status Register 2 to a 1 (high),
and terminates the Scan Command. The receipt of a TERMINAL COUNT signal from the Processor or DMA Controller during the scan operation will cause the FDC to
complete the comparison of the particular byte which is in
process, and then to terminate the command. Table 4 shows
the status of bits SH and SN under various conditions of
SCAN.
COMMAND
Scan Equal
Scan Low or
Equal
Scan High or
Equal

STATUS REGISTER 2
BIT2 = SN BIT3 = SH
0
1
0
0
1
0
0
1

1
0
1
0
0
1
0
0

COMMENTS
DFDo =

DpRocEssoR

DFDD

DpRocEssoR

~

DFOO = DpRocEssoR

DFDo <

DpRocEssoR

DFOo

DpROCESSOR

>

DFOO = DpRocEssoR
DFOo

DFOo

>
<

OPROCESSOR

DpRocEssoR

Table 4
If the FDC encounters a Deleted Data Address Mark on one
of the sectors (and SK = 0), then it regards the sector as
the last sector on the cylinder, sets CM (Control Mark) flag
of Status Register 2 to a 1 (high) and terminates the command. If SK = 1, the FDC skips the sector with the Deleted
Address Mark, and reads the next sector. In the second case
(SK = 1), the FDC sets the CM (Control Mark) flag of Status Register 2 to a 1 (high) in .order to show that a Deleted
Sector had been encountered.
When either the STP (contiguous sectors = 01, or alternate sectors = 02 sectors are read) or the MT (Multi-Track)
are programmed, it is necessary to remember that the last
sector on the track must be read. For example, if STP = 02,
MT = 0, the sectors are numbered sequentially 1 through
26, and we start the Scan Command at sector 21; the following will happen. Sectors 21,23 and 25 will be read, then
the next sector (26) will be skipped and the Index Hole will
be encountered before the EaT value of 26 can be read.
This will result in an abnormal termination of the command.
If the EaT has been set at 25 or the scanning started at
sector 20, then the Scan Command would be completed in
a normal manner.
During the Scan Command data is supplied by either the
processor or DMA Controller for comparison against the
data read from the diskette. In order to avoid having the OR
(Over Run) flag set in -Status Register 1, it is necessary to
have the data available in less than 27 fls (FM Mode) or 13
fls (MFM Mode)'. If an Overrun occurs the FDC ends the
command with bits 7 and 6 of Status Register 0 set to 0 and
1, respectively.

Seek
The read/write head within the FDD is moved from cylinder
to cylinder under control of the Seek Command. FDC has
four independent Present Cylinder Registers for each drive.
They are clear only after Recalibrate command. The FDC
compares the PCN (Present Cylinder Number) which is the
current head position with the NCN (New Cylinder Number), and if there is a difference performs the following
operation:
PCN < NCN: Direction signal to FDD set to a 1 (high),
and Step Pulses are issued. (Step In.)
PCN> NCN: Direction signal to FDDsettoaO (low), and
Step Pulses are issued. (Step Out.)

The rate at which Step Pulses are issued is controlled by
SRT (Stepping Rate Time) in the SPECIFY Command. After
each Step Pulse is issued NCN is compar!3d against PCN,
and when NCN = PCN, then the SE (Seek End) flag is set
in Status Register 0 to a 1 (high), and the command is terminated. At this point FDC interrupt goes high. Bits DBoDB3 in Main Status Register are set during seek operation
and are cleared by Sense Interrupt Status command.
During the Command Phase of the Seek operation the FDC
is in the FDC BUSY state, but during the Execution Phase.
it is in the NON BUSY state. While the FDC is in the NON
BUSY state, another Seek Command may be issued, and
in this manner parallel seek operations may be done on
up to 4 Drives at once. No other command cOlJld be issued
for as long as FDC is in process of sending Step Pulses to
any drive.
If an FDD is in a NOT READY state at the beginning of the
command execution phase or during the seek operation,
then the NR (NOT READY) flag is set in Status Register 0
to a 1 (high), and the command is terminated after bits 7
and 6 of Status Register 0 are set to 0 and 1 respectively.
If the time to write 3 bytes of seek command exceeds 150
fls, the timing between first two Step Pulses may be shorter
than set in the Specify command by as much as 1 ms.

Recalibrate
The function of this command is to retract the read/write
head within the FDD to the Track 0 position. The FDC clears
the contents of the PCN counter, and checks the status of
the Track 0 signal from the FDD. As long as the Track 0 signal is low, the Direction signal remains 0 (low) and Step
Pulses are issued. When the Track 0 signal goes high, the
SE (SEEK END) flag in Status Register 0 is set to a 1 (high)
and the command is terminated. If the Track 0 signal is still
low after 77 Step Pulses have been issued, the FDC sets
the SE (SEEK END) and EC (EQUIPMENT CHECK) flags
of Status Register 0 to both 1s (highs), and terminates the
command after bits 7 and 6 of Status Register 0 is set to 0
and 1 respectively.
The ability to do overlap RECALIBRATE Commands to
multiple FDDs and the loss of the READY signal, as
described in the Seek Command, also applies to the
RECALIBRATE Command.

I

Sense Interrupt Status
An Interrupt signal is generated by the FDC for one of the
following reasons:
1. Upon entering the Result Phase of:
a. Read Data Command
b. Read a Track Command
c. Read 10 Command
d. Read Deleted Data Command
e. Write Data Command
f. Format a Cylinder Command
g. Write Deleted Data Command
h. Scan Commands
2. Ready Line of FDD changes state
3. End of Seek or Recalibrate Command
4. During Execution Phase in the NON-DMA Mode
Interrupts caused by reasons 1 and 4 above occur during
normal command operations and are easily discernible by
the processor. During an execution phase in NON-DMA
Mode, DB5 in Main Status Register is high. Upon entering
Result Phase this bit gets clear. Reason 1 and 4 does not
require Sense Interrupt Status command. The interrupt is
cleared by reading/writing data to FOC. Interrupts caused
by reasons 2 and 3 above may be uniquely identified with
the aid of the Sense Interrupt Status Command. This com-

'Time refers to 8" mode (MINI = low). When using 5.25" mode, these times are doubled.
547

I

mand when issued resets the interrupt signal and via bits
5, 6, and 7 of Status Register 0 identifies the cause of the
interrupt.
SEEK
END
BITS 5

a

INTERRUPT
CODE
BIT6
BIT7
1
1

1

a

a

1

1

a

CAUSE
Ready Line changed state, either
polarity
Normal Termination of Seek or
Recalibrate Command
Abnormal Termination of Seek or
Recalibrate Command
TableS

Neither the Seek or Recalibrate Command have a Result
Phase. Therefore, it is mandatory to use the Sense Interrupt Status Command after these commands to effectively
terminate them and to provide verification of where the head
is positioned (PCN).
Issuing Sense Interrupt Status Command without interrupt
pending is treated as an invalid command.

Specify
The Specify Command sets the initial values for each of the
three internal timers. The HUT (Head Unload Time) defines
the time from the end of the Execution Phase of one of the
ReadlWrite Commands to the head unload state. This timer
is programmable from 16 to 240 ms in increments of 16 ms
(01 = 16 ms, 0 = 32 mS ... OF = 240 ms). The SRT (Step
Rate Time) defines the time interval between adjacent step
pulses. This timer is programmable from 1 to 16 ms in increments of 1 ms (F = 1 ms, E = 2 ms, D = 3 ms, etc.). The
HLT (Head Load Time) defines the time between when the
Head Load signal goes high and when the Read/Write

operation starts. This timer is programmable from 2 to 254
ms in increments of 2 ms (01 = 2 ms, 02 = 4 ms, 03 = 6
ms ... 7F = 254ms).
The time interval mentioned above is a direct function of the
MINI (pin 32). Times indicated above are for MINI set to O.
In a mini floppy application all time intervals are increased
by a factor of 2.
The choice of DMA or NON-DMA operation is made by the
ND (NON-DMA) bit. When this bit is high (ND = 1) the NONDMA mode is selected, and when ND = 0 the DMA mode
is selected.

Sense Drive Status
This command may be used by the processor whenever it
wishes to obtain the status of the FDDs. Status Register 3
contains the Drive Status information stored internally in
FDC registers.

Invalid
If an invalid command is sent to the FDC (a command not
defined above), then the FDC will terminate the command
after bits 7 and 6 of Status Register 0 are set to 1 and 0
respectively. No interrupt is generated by the FDC 9267
during this condition. Bit 6 and bit 7 (DIO and ROM) in the
Main Status Register are both high ("1 ") indicating to the
processor that the FDC 9267 is in the Result Phase and the
contents of Status Register 0 (STO) must be read. When
the processor reads Status Register 0 it will find an 80 hex
indicating an invalid command was received.
A Sense Interrupt Status Command must be sent after a
Seek or Recalibrate Interrupt, otherwise the FDC will consider the next command to be an Invalid Command.
In some applications the user may wish to use this command as a No-Op command, to place the FDC in a standby
or no operation state.

STATUS REGISTER IDENTIFICATION
NO.
D7

BIT
NAME
Interrupt Code

SYMBOL
IC

D6

D,

Seek End

SE

D4

Equipment Check

EC

D3

Not Ready

NR

D2
D,
Do

Head Address
Unit Select 1
Unit Select a

HD
US 1

usa

DESCRIPTION
D7 = a and D6 = a
Normal Termination of Command, (NT). Command was completed
and properly executed.
D7 = a and D6 = 1
Abnormal Termination of Command, (AT).
Execution of Command was started, but was not successfully
completed.
D7 = 1 and D6 = a
Invalid Command issue, (IC). Command which was issued was
never started.
D7 = 1 and D6 = 1
Abnormal Termination because during command execution the
ready signal from FDD changed state.
When the FDC completes the SEEK Command, this flag is set to
1 (high).
If a fault Signal is received from the FDD, or if the Track a Signal
fails to occur after 77 Step Pulses (Recalibrate Command) then this
flag is set.
When the FDD is in the not-ready state and a read or write
command is issued, this flag is set. If a read or write command is
issued to Side 1 of a single sided drive, then this flag is set.
This flag is used to indicate the state of the head at Interrupt.
These flags are used to indicate a Drive Unit. Number at Interrupt.

548

BIT
NAME

NO.

0,

End of Cylinder

0,
05

Data Errror

04

Over Run

03
0,

No Data

0,

Not Writable

Do

Missing Address Mark

0,
0,

Control Mark

05
0,

Data Error in Data Field
Wrong Cylinder

03

Scan Equal Hit

0,

Scan Not Satisfied

0,

Bad Cylinder

Do

Missing Address Mark
in Data Field

0,

Fault

0,

Write Protected

05

Ready

0,

Track 0

03

Two Side

0,

Head Address

0,

Unit Select 1

0,

Unit Select 0

SYMBOL
DESCRIPTION
STATUS REGISTER 1 (CO NT.)
EN
When the FDC tries to access a Sector beyond the final Sector of a
Cylinder, this flag is set.
Not used. This bit is always 0 (low).
DE
When the FDC detects a CRC error in either the 10 field or the data
field, this flag is set.
OR
If the FDC is not serviced by the main-systems during data
transfers, within a certain time interval, this flag is set.
Not used. This bit always 0 (low).
NO
During execution of READ DATA, WRITE DELETED DATA or
SCAN Command, if the FDC cannot find the Sector specified in the
lOR Register, this flag is set.
During executing the READ 10 Command, if the FDC cannot read
the 10 field without an error, then this flag is set.
During the execution of the READ A Cylinder Command, if the
starting sector cannot be found, then this flag is set.
NW
During execution of WRITE DATA, WRITE DELETED DATA or
Format A Cylinder Command, if the FDC detects a write protect
signal from the FDD, then this flag is set.
MA
If the FDC cannot detect the ID Address Mark after encountering
the index hole twice, then this flag is set.
If the FDC cannot detect the Data Address Mark or Deleted Data
Address Mark, this flag is set. Also at the same time, the MD
(Missing Address Mark in Data Field) of Status Register 2 is set.
STATUS REGISTER 2
Not used. This bit is always 0 (low).
CM
During executing the READ DATA or SCAN Command, if the FDC
encounters a sector which contains a Deleted Data Address Mark,
this flag is set.
DO
If the FDC detects a CRC error in the data field then this flag is set.
WC
This bit is related with the NO bit, and when the contents of C on the
medium is different from that stored in the lOR, this flag is set.
SH
During execution, the SCAN Command, if the condition of "equal"
is satisfied, this flag is set.
SN
During executing the SCAN Command, if the FDC cannot find a
Sector on the cylinder which meets the condition, then this flag
is set.
BC
This bit is related with the NO bit, and when the content of C on the
medium is different from that stored in the lOR and the content of C
is FF, then this flag is set.
MD
When data is read from the medium, if the FDC cannot find a Data
Address Mark or Deleted Data Address Mark, then this flag is set.
STATUS REGISTER 3
FT
This bit is used to indicate the status of the Fault signal from
the FDD.
WP
This bit is used to indicate the status of the Write Protected signal
from the FDD.
RY
This bit is used to indicate the status of the Ready signal from
the FDD.
TO
This bit is used to indicate the status of the Track 0 signal from
the FDD.
TS
This bit is used to indicate the status of the Two Side signal from
the FDD.
HD
This bit is used to indicate the status of Side Select signal
to the FDD.
US1
This bit is used to indicate the status of the Unit Select 1 signal
to the FDD.
usa
This bit is used to indicate the status of the Unit Select 0 signal
to the FDD.

549
-~~

..

--------

I

PROCESSOR INTERFACE
During Command or Result Phases the Main Status Register (described earlier) must be read by the processor
before each byte of information is written into or read from
the Data Register. After each byte of data read or written to
Data Register, CPU should wait for 12 fts before reading
MSR. Bits 06 and 07 in the Main Status Register must be
in a 0 and 1 state, respectively, before each byte ofthe command word may be written in the FOC 9267. Many of the
commands require multiple bytes, and as a result the Main
Status Register must be read prior to each byte transfer to
the FOC 9267. On the other hand, during the Result Phase,
06 and 07 in the Main Status Register must both be 1's (06
= 1 and 07 = 1) before reading each byte from the Oata
Register. Note, this reading of the Main Status Register
before each byte transfer to the FOC 9267 is required in
only the Command and Result Phases, and NOT during the
Execution Phase.
During the Execution Phase, the Main Status Register need
not be read. If the FOC 9267 is in the NON-OMA Mode, then
the receipt of each data byte (if FOC 9267 is reading data
from FOO) is indicated by an Interrupt signg!on pin 18 (INT
= 1). The generation of a Read signal (RO = 0) or Write
signal (WR = 0) will reset the Interrupt as well as output the
Data onto the Data bus. If the processor cannot handle
Interrupts fast enough (every 13 /Jos) for M FM and 27 fts for
FM mode, then it may poll the Main Status Register and then
bit 07 (ROM) functions just like the Interrupt signal. If a Write
Command is in process then the WR signal performs the
reset to the Interrupt signal.
If the FOC 9267 is in the OMA Mode, no Interrupts are generated during the Execution Phase. The FOC 9267 generates ORa's (OMA Requests) when each byte of data is
available. The OMA Controller responds to this request with
both a OACK = 0 (OMA Acknowledge) and a RO = 0 (Read
signal). When the OMA Acknowledge signal goes low
(OACK = 0) then the OMA Request is reset (ORO = 0). If
a Write Command has been programmed then a WR signal
will appear instead of RD. After the Execution Phase has
been completed (Terminal Count has occurred) or EaT
sector was read/written, then an Interrupt will occur (INT =
1). This signifies the beginning of the Result Phase. When
the first byte of data is read during the Result Phase, the
Interrupt is automatically reset (INT = 0).

It is 'important to note that during the Result Phase all bytes
shown in the Command Table must be read. The Read Data
Command, for example has seven bytes of data in the Result
Phase. All seven bytes must be read in order to successfully complete the Read Data Command .. The FOC 9267
will not accept a new command until all seven bytes have
been read. Other commands may require fewer bytes to be
read during the Result Phase.
The FOC 9267 contains five Status Registers. The Main
Status Register mentioned above may be read by the processor at any time. The other four Status Registers (STO,
ST1, ST2, and ST3) are only available during the Result
Phase, and may be read only after completing a command.
The particular command which has been executed determines how many of the Status Registers will be read.
The bytes of data which are sent to the FOC 9267 to form
the Command Phase, and are read out of the FOC 9267 in
the Result Phase, must occur in the order shown in the
Command Table. That is, the Command Code must be sent
first and the other bytes sent in the prescribed sequence.
No foreshortening of the Command or Result Phases are
allowed. After the last byte of data in the Command Phase
is sent to the FOC 9267, the Execution Phase automatically
starts. In a similar fashion, when the last byte of data is read
out in the Result Phase, the command is automatically
ended and the FOC 9267 is ready for a new command.

POLLING FEATURE OF THE FDC9267
Afterthe Specify command has been sent to the FOC 9267,
the Unit Select line USO and US1 will automatically go into
a polling mode. In between commands (and between step
pulses in the SEEK command) the FOC 9267 polls all four
FOO's looking for a change in the Ready line from any of
the drives. If the Ready line changes state (usually due to
a door opening or closing) then the FOC 9267 will generate
an interrupt. When Status Register 0 (STO) is read (after
Sense Interrupt Status is issued), Not Ready (NR) will be
indicated. The polling of the Ready line by the FOC 9267
occurs continuously between commands, thus notifying the
processor which drives are on or off line. Each drive is polled
every 1.024 ms except during the Read/Write commands.

AC TEST CONDITION
INPUT/OUTPUT

CLOCK

2.4V

3.0V----..

0.45V

O.3V _ _--.J

ACTESTING
Inputs are driven at 2.4V for a logic "1" and OASV for a logic "0," Timing measurements are made at 2.0V for a logic "1" and O.BV for a logic "0,"
Clocks are driven at 3.0V for a logic "1" and O.3V for a logic "0." Timing measurements are made a12.4V for a logic "1" and O.65V for a logic "0,"

550

PRECOMPENSATION
TIMING DIAGRAMS

The desired precompensation delay is determined by the
state of the MINI, PO and P1 inputs. Logic levels present on
these pins may be changed dynamically as long as the
inputs are stable during the time the floppy disk controller
is writing to the qrive.

PROCESSOR READ OPERATION
AO

Cs

X. . .___

~

OACK

T AR~

NOTE: The duration of the write pulse from pin 26 (WDOUTj is to be a
minimum of 250ns. for all precomp values.

1...-

RO~TRR
t..--..--.-I
I

TAD.l-

DATA-------1r

------.J :_ TRA
_ _"

---I

I~TDF
I

!~------

-----------""''l
~TRI.....,.J

MINI
0
0
0
0
1
1
1
1

P1
0
0
1
1
0
0
1
1

PO
0
1
0
1
0
1
0
1

PRECOMP
O.Ons
62.5ns
125.0ns
187.5ns
O.Ons
125.0ns
250.0ns
375.0ns

INT

CLOCK

TABLE 6
WRITE PRECOMPENSATION VALUE SELECTION

FIGURE 1: VCOCLK TIMING

PO.Pl

USO. USl

1.5V--

-

J -------- ... --

~-----

1.5V- - - - - - - - - - - -

~I\

-----+

T"

r---

~

T"

t-

FIGURE 2: PRECOMP VALUE TIMING

--

PD

-~

--1.5V

- - - --1.5V

FIGURE 3: PUMPUP TO PUMPDOIJIIN TIMING

PD

-13-'"

__--II

--

-

1.5V

TpAES

FIGURE 4: PUMPDOWN TO PUMPUP TIMING

551

I

ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS'
Operating Temperature .......................................................................................... O"C to + 70"C
Storage Temperature ........................................................................................ - 55"C to + 150"C
All Output Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5 to + 7 Volts
All Input Voltages ............................................................................................. - 0.3 to + 7 Volts
Supply Voltage Vee ........................................................................................... , - 0.3 to + 7 Volts
Power Dissipation ........................................................................................................ 1 Watt
T. = 25°C
·COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

DC CHARACTERISTICS Ta

= DOC to + 7DoC; Vee =

PARAMETER
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Voltage
(CLK)
Input High Voltage
(CLK)
Vee Supply Current

SYMBOL
Vil
V,H
VOL
VOH

+5V ±5% unless otherwise specified.
MIN
-0.3
2.0

V'L(q,)

2.4
-0.3

V,H ).)

2.4

LIMITS
TYPCD

Vee
0.65
Vee

III

High Level Output Leakage Current
Low Level Output Leakage Current

ilOH
ILOL

+ 0.5

200
10
-10
10
-10

Icc

Input Load Current
(All Input Pins)

MAX
0.8
Vee + 0.5
0.45

UNIT
V
V
V
V
V

TEST
CONDITIONS

10L = 2.0 mA
10H = -200 f1A

V
mA
f1A
f1A
f1A
f1A

V1N = Vee
V,N = OV

VOUT = Vee
VOUT =

+ 0.45V

NOTE: CDTypical values for T. = 25"C and nominal supply voltage.

DC CHARACTERISTICS Ta
PARAMETER
Clock Input Capacitance
Input Cap,!citance
Output Capacitance

= 25°C; fe = 1 MHz; Vee = DV
SYMBOL

LIMITS
TYP

MIN

GIN ()
C 'N
COUT

552

MAX
20
10
20

UNIT
pF
pF
pF

TEST
CONDITIONS
All Pins Except Pin
Under Test Tied to
ACGround

AC CHARACTERISTICS Ta = O°C to + 70°C; V" =
PARAMETER

Clock period
Clock Active (High. Low)
Clock Rise Time
Clock Fall Time
AD. CS, DACK Set Up Time to RD
AD, CS, DACK Hold Time from RD
RDWidth
Data Access Time from RD t
DB to Float Delay Time from RD

SYMBOL

1

r

r
A.a. CS, DACK Set Up time to WRl
AD, CS, DACK Hold Time to WR r
WRWidth
Data Set Up Time to WR r
Data Hold Time from WR r
INT Delay Time from RD t
INT Delay Time from WR r

<1>ey
<1>0
<1>,
<1>,
TAR
TAA
TRR
T Ro
TOF

DRQ Cycle Time

TAw
TWA
Tww
Tow
Two
TAl
TWI
T MCY

DRQ Delay Time from DACK L
TCWidth
Reset Width

TAM
TTC
T AST

+ 5V ± 5% unless otherwise specified.
MIN

58
40%

LIMITS
TYPey
<1>ey
ns

RDD Active Time (High)

TROD

Window Cycle Time

Twcy

Window Hold Time to/from RDD

TRow

15

ns

US. Hold Time to RW/SEEK t

Tus

12

""s

Tso

7

""s

TOST

1.0

,,"5

TSTU

5.0

T STP

6.0
33

2.0
1.0

,,"5

MFM
MFM

=0
=1

TWRD

SEEK RW Hold Time to LOW
CURRENTIDIRECTION t
LOW CURRENT DIRECTION Hold
Time to FAULT
RESET/STEP i
US. Hold Time from FAULT RESET/
STEP
Step Active Time (High)
Step Cycle Time
FAULT RESET Active Time (High)
Write Data Width (WDOUT)
US, Hold Time After SEEK
Seek Hold Time from DIR

r

DIR Hold Time after STEP
Index Pulse Width
WRt, Delay from DRQ
WE or RD Response Time from DRQt
VCOCLK Period
Rise and Fall Times
Unit Select to Valid PRECOMP Value
Pump Reset Time
Rise and Fall Times

Tse
TFR
Twoo

,,"5

7.0

TSTD

T lox
TMw

20
250

""s
,,"5

8.0
250
15
30
24

Tsu
Tos

16 MHz Clock Period
MINI pin = 0

10

,,"5

ns
,,"5

fLs
fLs
<1>ey
ns

T MRW

12
.56
10

,,"5

16 MHz Clock Period
MINI pin = 0

16MHz Clock Period
MINI pin = 0

Tp,

100

ns

Figure 1
Figure 1
Figure 2

Tp,",

20
10

ns
ns

Figure 3
Figure 3

Top

NOTES: (j) Typical values for T, - 25'C and nominal supply
voltage
® The former value of 2 and 1 are applied to Stand·
ard Floppy, and the latter value of 4 and 2 are
applied to Mini-floppy

.46

.5

""s
ns

@ Sony microfloppy 3'12' drive (8" compatible).
@) Sony microfloppy 3'12' drive (5'14' compatible).

553

TIMING DIAGRAMS
DMA OPERATION

PROCESSOR WRITE OPERATION
DRQ

WR

OR

AD

SEEK OPERATION

=:=>t

USO,1

~'-_ _ _ __

STABLE

--i ISU r-

---jIUS/--

RWISEEK

---.X"

X_,..:_____

_ItDS~

--jISDj--

IDST

j - -~TU--l

--l

_______~S-TD----~I~

STEP

ISTP

f---

--l

FAULT RESET"

I

:

I

~

TFR

TERMINAL COUNT

INDEX

~
I
I

~

FILE UNSAFE RESET

I

It""~>----- tsc -----<.-11

FLT RESET
I

I

X"";"--i-:-----

~

DIRECTION _ _ _ _ _

T,DX 1

~

~

T,OX

TC

1

f----l

FDD READ OPERATION

READ DATA

-1\_________n~1______
-:

: - - TROD

:-TWRD-j

.IX

~,'

H

YL-

READ DATA WINDDW _ _ _ _ _ _ _ _

Note: Either polarity data window is valid.

RESET

:--TRDW-]

II

RESET
_---TWCy

.. :

t -.
1 .

~
~

+----

I--TRST

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; con·
sequently complete information sufficient for construction purposes is not necessarily given. The information has been
carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under
the patent rights of SMC or others. SMC reserves the right to make changes at any time in order to improve design and
supply the best product possible.

554

FDC9268
PRELIMINARY

Integrated Single/Double Density
Floppy Disk Controller
PIN CONFIGURATION

FEATURES

D Combination Floppy Disk Controller and Floppy Disk
Interface

Vee
RW/SEEK
LCTIDIR
FRISTP
HOL
ROY
WP/TS
FLTITRo
P,
P,
WDOUT
USo
US,
HD
MFM
WE
Po
DSKD
CLK
MINI

RESET
RD
WR

D Software compatible with industry standard FDC765A
D On chip digital data separator eliminates critical analog

cs

Ao

adjustments

OBo
OB,
OB,
DB,
DB,
DBs
DB,
DB,
DRO
DACK
TC
IDX
INT
TEST
GND

D IBM compatible in both single and double density
recording formats

D Programmable data record lengths: 128, 256, 512, or
1024 bytes/sector

D Multi-sector and multi-track transfer capability
D Controls up to 4 floppy disk drives
D Data Scan Capability-will scan a single sector or entire
track's worth of data fields, comparing on a byte to byte
basis, data in the processors memory with the data
read from the diskette

D Data transfer in DMA or non-DMA mode

PACKAGE: 4D-pin D.I.P.

D Single 16 MHz TTL clock input
D Parallel seek operations on up to 4 drives
D Compatible with most microprocessors
D COPLAMOS/n-channel silicon gate technology
D Available in 40-pin Dual-In-Line and 44-pin PLCC

0
(J)a:

I-

:::>

go_:E

>-~S
~'$: (i ({' cL ~ $: ~ ~ ~ ~
HDL
FRISTP
LCTIDIE
RW/SEEK

packages

V"
NC
RST
RD
WR

CS
AO

3938373635343332313029
40
28
41
27
42
26
25
24
23
22
3
21
4
20
5
19
18
6
7 8 91011121314151617

WE
Po
Ds/DRT
8MHz
MINI
NC
VSS
TEST
INT
IDX
TC

GENERAL DESCRIPTION
The FDC9268 is a monolithic combination of the industry
standard FDC765A Floppy Disk Controller and the
FDC9239 Enhanced Floppy Disk Interface Circuit. It preserves all of the processor hardware and software interfaces to the 765A, and contains on-chip circuitry to simplify
drive interfacing.
These on-chip enhancements include a digital data separator, compatible with 3.5", 5.25" and 8" floppy disk drives.
The FDC9268 separates both FM (Single Density) and MFM
(Double Density) encoded data. The FDC uses a high per555

formance 16-bit cell divide algorithm which produces significant improvements in soft error rates over existing
designs. The FDC9268's high performance is achieved
without any external adjustments.
The FDC9268 also allows variable write precompensation,
which is track selectable.
These enhancements greatly reduce the number of components required to interface floppy disks to a microprocessor system.

active, the FDC9268 uses the maximum precomp available in that mode (i.e. 375 nsec in the 5-1/4" mode and
187.5 nsec in the 8" mode).

There are 15 commands which the FDC9268 will execute.
Each of these commands requires multiple 8-bit bytes to
fully specify the operation which the processor wishes the
FDC to perform. The following commands are available:

MINI

Scan High or Equal
Read Data
Sense Drive Status
Format a Track
Read 10
Read a Track
Write Deleted Data
Recalibrate
Scan Equal
Scan Low or Equal
Sense Interrupt Status
Write Data
Read Deleted Data
Specify
Seek
Address mark detection circuitry is internal to the FDC which
simplifies the read electronics. The track stepping rate, head
load time, and head unload time may be programmed by
the user. The FDC9268 offers many additional features such
as multiple sector transfers in both read and write with a
single command, and full IBM compatibility in both single
and double density modes.

P,

P,

Po

0

0

0

0

0

0

1

125.0

0

0

PRECOMP VALUE (nsec)

250.0
375.0

0
0

0

375.0

0

375.0

375.0

0

375.0

1

1

0

0

0

0

0

0

0

0

1

62.5

0

0

FDC9266 COMPATIBILITY

0

0

1

The FDC9268 is software and hardware compatible with
the FDC9266 with the following qualifications pertaining to
Precomp and clock input.
-A 16 MHz clock is used on the FDC9268.
- The precomp specifications for the FDC9267 and
FDC9266 can be used for the FDC9268 with the following
qualification. Whenever the precomp select line P2 is

0

1

0

0
0
0

0

125.0
187.5

0

187.5
187.5

0
0

187.5
187.5

Write Precompensation Value Selection

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The information has been
carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthetmore, such information does not convey to the purchaser of the semiconductor devices described any license under
the patent rights of SMC or others. SMC reserves the right to make changes at any time in order to improve design and
supply the best product possible.

556

FOC 9791
FOe 9793
Foe 9795
Foe 9797

Floppy Disk
Controller/Formatter
FDC

f-LPC FAMILY

PIN CONFIGURATION

FEATURES
0+5 VOLT ONLY VERSION OF FDC179X-02
SOFT SECTOR FORMAT COMPATIBILITY
o AUTOMATIC TRACK SEEK WITH VERIFICATION
ACCOMMODATES SINGLE AND DOUBLE
DENSITY FORMATS
IBM 3740 Single Density (FM)
IBM System 34 Double Density (MFM)
o READ MODE
Single/Multiple Sector Read with Automatic Search
or Entire Track Read
Selectable 128 Byte or Variable Length Record
WRITE MODE
Single/Multiple Sector Write with Automatic Sector
Search
Entire Track Write for Diskette Initialization
PROGRAMMABLE CONTROLS
Selectable Track to Track Stepping Time
Side Select Compare
o SYSTEM COMPATIBILITY
Double Buffering of Data 8 Bit Bi-Directional Bus for
Data, Control and Status
DMA or Programmed Data Transfers
All Inputs and Outputs are TTL Compatible
On-chip Track and Sector Registers/Comprehensive
Status Information
WRITE PRECOMPENSATION (MFM AND FM)
o SIDE SELECT LOGIC (FDC 9795, FOC 9797)
o WINDOW EXTENSION (IN MFM)

o
o

~

NC
WE

Cs

FiE [

Ao
A,
DALO'
DAL l'
DAL2'
DAL3'
DAL4'
DAL5'
DAL6'
DAL7'
STEP
DIRC
EARLY
LATE
MR
GND

o
o

2
3
4
5

10
9
0
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

NC
INTRa
ORO
DDEN"
WPRT

D iP

P TROO

P WF

READY
WD
WG
TG43
HLD
RAW READ
RCLK
RG/SSQ
CLK
HLT
TEST
+5V

'INVERTED BUS FOR FDC 9791. FOC 9795
PACKAGE: 40 pin D.I.P.

o

o

o

o
o

INCORPORATES ENCODINGIDECODING
AND ADDRESS MARK CIRCUITRY
COMPATIBLE WITH FDC 179X-02
COPLAMOS® n-CHANNEL MOS TECHNOLOGY
COMPATIBLE WITH THE FDC 9216 FLOPPY DISK
DATA SEPARATOR

GENERAL DESCRIPTION

The FDC 979X is an MOS/LSI device which performs the
functions of a Floppy Disk Controller/Formatter in a single chip implementation. The basic FDC 979X chip design
has evolved into four specific parts: FDC 9791, FDC 9793,
FOC 9795, and the FDC 9797.

mode (MFM). The FDC 9791 contains enhanced features necessary to read/write and format a double
density diskette. These include address mark detection,
FM and MFM encode and decode logic, window extension, and write precompensation.

This FDC family performs all the functions necessary
to read or write data to any type of floppy disk drive.
Both 8" and 5%" (mini-floppy) drives with single or double
density storage capabilities are supported. These nchannel MOS/LSI devices will replace a large amount of
discrete logic required for interfacing a host processor to
a floppy disk.

The FDC 9793 is identical to the FDC 9791 except the
DAL lines are TRUE for systems that utilize true data
busses.

The FDC 9791 is IBM 3740 compatible in single density
mode (FM) and System 34 compatible in double density

The FDC 9795 adds side select logic to the FDC 9791.
The FDC 9797 adds the side select logic to the FDC 9793.
The processor interface consists of an 8 bit bidirectional
bus for data, status, and control word transfers. This family of controllers is configured to operate on a multiplexed
bus with other bus-oriented devices.
557

OAL

FDC 979X BLOCK DIAGRAM

'----------------<

RCLK

WG

ORO

TG43

INTRQ

WI'R'r
~

WFNFOE
~

CS

TROO

~

COMPUTER
INTERFACE
CONTROL

WE
AD
AI

PLA
CONTROL
(230 x 16)

CONTROL

CONTROL

DISK

READY

INTERFACE
CONTROL

STEP

DIRe
EARLY
LATE

eLK

RG/ssa

ODEN

HLO
HLT

K,

RAW READ

)

DATA (8)

ACLK

~

AD

RG

AI

LATE

CS

EARLY
WO

C

fiE

M
P

WE

0

MA

P
P
y

a

u
T
E
A

L
10K
WG

FLOPPY OISK
CONTROLLER!
FORMATTER

I
N
T
E
A
F
A
e
E

F

+5

0
I
S
K

WPAT

WF/\TF'l5t

+5V

t

0

jp

A
I

v

TROO

E

:

10K?

~

10K

READY
TG43

~

ORO

STEP

INTRQ

DIRe

eLK

+5V

SYSTEM BLOC K DIAGRAM

HLO

~

l~

ODEN

1

HLT

Vee

GNO

1

~

+5V

558

f---e

t

+5V

~

ONE SHOT
(IF USED)

I

DESCRIPTION OF PIN FUNCTIONS
-----

~~----

_.-

--~

-- --

--.

-------------- ----- .. --- __________ . _0- ___________ .. ____________ - - - ' - - - ' - ' -

NAME

PIN NO.

SYMBOL

1-------1

--f------- -

NO CONNECTION

- - - - r-------------

20

GROUND

21

POWER SUPPLY

40

NO CONNECTION

NC

- - - - - f------

--

----~----

- - - - - - - - - - - - - - - - - - - - - - - - - - - - --

---

15V

Vee

- - - - -1 - - - - - - - - - - - - - - - - - --- - - -

------------

NC

This pin is not connected.

MR

A logic low on this input resets the device and loads HEX 03 into
the command regis~The Not Ready (Status Bit 7) is reset during
MR ACTIVE. When MR is brought to a logic high a Restore
Command is executed. regardless of the state of the Ready signal
from the drive. Also, HEX 01 is loaded into the sector register.

----

--

19

-----

Ground

Vss

----.--

FUNCTION
---------.----.----~-----------

This pin is internally connected to the substrate bias generator and
must be left open.

MASTER RESET

COMPUTER INTERFACE:
2

WRITE ENABLE

WE

A logic 'Iow on..!.!J.is input gates data on the DAL into the selected
register when CS is low.

3

CHIP SELECT

CS

A logic low on this input selects the chip and the parallel
data bus (DAL).

4

READ ENABLE

RE

A logic low on this input controls the placement of data from a
selected register on DAL0-DAL7 when CS is low.

5,6

7-14

REGISTER SELECT
LINES

DATA ACCESS LINES

AO, A1

These inputlielect ~register to
lines under RE and WE control:
A1
AO
RE
Status Reg
0
0
0
1
Track Reg
1
0
Sector Reg
1
1
Data Reg

DALODAL7

receive/transfer data on the DAL
WE
Command Reg
Track Reg
Sector Reg
Data Reg

Eight bit Bidirectional bus used for transfer of data, control, and
status. ThisQ,lJS is a receiver enabled by WE or a transmitter
enabled by RE. The Data Bus is inverted on the FDC 9791, FDC 9792
and FDC 9795.

-

24

CLOCK

CLK

This input requires a free-running square wave clock for internal
timing reference, 2 MHz for 8" drives, 1 MHz for 5'/,' drives.

38

DATA REQUEST

DRQ

This open drain output indicates that the DR contains assembled
data in Read operations, or the DR is empty in Write operations.
This signal is reset when serviced by the computer through reading
or loading the DR in Read or Write operations, respectively. Use a
10K pull-up resistor to +5V.

39

INTERRUPT REQUEST

INTRQ

This open drain output is set at the completion or termination
of any operation and is reset when a new command is loaded into
the command register or the status register is read. Use a 10K
pull-up resistor to + 5V,

--

~--.------

FLOPPY DISK INTERFACE:
STEP

STEP

Step and direction motor control. The step output contains a pulse
for each step.

16

DIRECTION

DIRC

Direction Output is active high when stepping in, active low when
stepping out.

17

EARLY

EARLY

Indicates that the write data pulse occurring while Early is active
(high) should be shifted early for write precompensation.

18

LATE

LATE

Indicates that the write data pulse occurring while Late is active
(high) should be shifted late for wnte precompensation.

TEST

TEST

15

--

t-----.

---------

--

-- - - - - - -

1-----

22

1------23

_ . _ - - - ---

HEAD LOAD TIMING

---

----

HLT

---

------- -

--

_

..•

----

---------

---------

-------

This input is used for testing purposes only and should be tied to
+5V or left open by the user unless interfacing to voice coil
actuated motors.
-- ---- - - - - -

-

--.

- ----

When a logic high is found on the HLT Input the head
to be engaged

559

IS

assumed

I

SYMBOL

FUNCTION

RG

A high level on this output indicates to the data separator circuitry
that a field of zeros (or ones) has been encountered, and is used
for synchronization.

SSO

The logic level of the Side Select Output is directly controlled by
the'S' flag in Type II or III commands. When S=1, SSO is set to
a logic 1. When S=O, SSO is set to a logic O. The Side Select Output
is only updated at the beginning of a Type II or III command. It is
forced to a logic a upon a MASTER RESET condition.

READ CLOCK

RCLK

A nominal square-wave clock signal derived from the data stream
must be provided to this input. Phasing (i.e. RCLK transitions)
relative to RAW READ is important but polarity (RCLK high or low)
is not.

27

RAW READ

RAW
READ

The data input signal directly from the drive. This input shall be a
negative pulse for each recorded flux transition.

28

HEAD LOAD

HLD

The HLD output controls the loadirig of the Read-Write head
against the media.

29

TRACK GREATER
THAN 43

TG43

This output informs the drive that the Read/Write head is positioned
between tracks 44-76. This output is valid only during Read and
Write Commands.

30

WRITE GATE

WG

This output is made valid before writing is to be performed
on the diskette.

31

WRITE DATA

WD

A 250 ns (MFM) or 500 ns (FM) pulse perflux transition. WD contains
the unique Address marks as well as data and clock in both FM and
MFM formats.

32

READY

READY

This input indicates disk readiness and is sampled for a logic high
before Read or Write commands are performed. If Ready is low the
Read or Write operation is not performed and an interrupt is
generated. Type I operations are performed regardless af the state
of Ready. The Ready input appears in inverted format as Status
Register bit 7.

33

WRITE FAULT/
VFO ENABLE

WFIVFOE

This is a bi-directional signal used to signify writing faults at the
drive, and to enable the external PLO data separator. When WG = 1,
Pin 33 functions as a WF input. If WF = 0, any write command will
immediately be terminated. When WG = 0, Pin 33 functions as a
VFOE output. VFOE will go low during a read operation after the
head has loaded and settled (HLT= 1). On the 9795/7, it will remain
low until the last bit of the second CRC byte in the ID field. VFOE
will then go high until 8 bytes (MFM) or 4 bytes (FM) before the
Address Mark. It will then go active until the last bit of the second
CRC byte of the Data Field. On the 9791/3, VFOE will remain low
until the end of the Data Field.

34

TRACK 00

35

INDEX PULSE

36

WRITE PROTECT

WPRT

This input is sampled whenever a Write Command is received.
A logic low terminates the command and sets the Write Protect
Status bit.

37

DOUBLE DENSITY

DDEN

This pin selects either single or double densi~ation. When
DDEN = 0, double density is selected. When DDEN = 1, single
density is selected.

PIN NO.

NAME

25

READ GATE (979113)

25

SIDE SELECT OUTPUT
(9795,9797)

26

TROO
IP

This input informs the FDC 979X that the Read/Write head is
positioned over Track 00.
This input informs the FDC 979X when the index hole is encountered
on the diskette.

560

FUNCTIONAL DESCRIPTioN
This register can be read onto the PAL, but not loaded
from the DAl.
CRCLogic- This logic is used to check or to generate
the 16-bit Cyclic Redundancy Check (CRC). The polynomial is: G(X)=X '6 +X 12 +x 5 +l
Track Register-This a-bit register holds the track
number of the current Read/Write head position. It is
incremented by one every time the head stepped in
(towards track 76) and decremented by one when the
head is stepped out (towards track 00). The contents
of the regisier are compared with the recorded track
number in the I D field during disk Read, Write, and
Verify operations. The Track Register can be loaded
from or transferred to the DAl. This Register should not
be loaded when the device is busy.
The CRC includes all information starting with ihe
address mark and up to the CRC characters. The CRC
register is preset to ones prior to data being shifted
through the circuit.
Arithmetic/Logic Unit (ALU) - The AlU is a serial
comparator, incrementer, and decrementer and is used
for register modification and comparisons with the disk
recorded IP field.
Timing and Control-All computer and Floppy Disk
Interface controls are generated through this logic. The
internal device timing is generated from an external
crystal clock.
AM Detector-The address mark detector detects ID,
data and index address marks during ready and
wriie operations.

The FDC 979X major functional blocks are as follows:
Data Shill Register- This 8-bit register asserr.bles serial
data from the Read Data input (RAW REAP) during
Read operations and transfers serial data to the Write
Data output during Write operations.
Data Register- This 8-bit register is used as a holding
register during Disk Read and Write operations. In Disk
Read operations the assembied data byte is transferred
in parallel to the Data Register from the Data Shift
Register. In Disk Write operations information is transferred in parallel from the Data Register to the Data
Shift Register.
When executing the Seek command the Daia Register
holds the address of the desired Track position. This
register is loaded from the PAL and gated onto the DAl
under processor control.
Sector Register (SR) - This 8-bit register holds the
address of the desired sector position. The contents
of the register are compared with the recorded sector
number in the ID field during disk Read or Write operations. The Sector Register contents can be loaded from
or transferred to the PAL. This register should not be
loaded when the device is busy.
Command Register (CR)- This 8-bit register holds the
command presently being executed. This register should
not be loaded when the device is busy unless the new
command is a Force Interrupt. The command register
can be loaded from the DAl, but not read onto the DAL.
Status Register (STR)- This.8-bit register holds device
Status information. The meaning of the Status bits is a
function of the type of command previously executed.

OPERATION
FDC 9791, FDC 9793, FDC 9795 and FDC 9797 have two
modes of operation according to the state of DDEN (Pih
37). When DDEN = 1, single density is selected. In either
case, the ClK input (Pin 24) is at 2 MHz. However, when
interfacing with the mini-floppy, the ClK input is set at 1
MHz for both single density and double density. When the
clock is at 2 MHz, the stepping rates of 3,6,10 and 15 ms
are obtainable. When ClK equals 1 MHz these times are
doubled.
Disk Read Operation
Sector lengths of 128, 256, 512 or 1024 are obtainable in
either FM or MFM formats. For FM, DDEN should be
placed to logical "1". For MFM formats, DDEN should be
placed to a logical "0". S,ector lengths are determined at
format time by a special byte in the "ID" field. If this Sector length byte in the ID field is zero, then the sector length
is 128 bytes. If 01 then 256 bytes. If 02, then 512 bytes. If
03, then the sector length is 1024 bytes. The number of
sectors per track can be from 1 to 255 sectors. The number of tracks is from 0 to 255 tracks.
For read operations, the FDC 979X requires RAW READ
Data (Pin 27) signal which is a 250 ns pulse per flux transition and a Read clock (RClK) signal to indicate flux
transition spacings. The RClK (Pin 26) signal is
561

provided by some drives but if not, it may be derived
externally by Phase lock loops, one shots, or counter
techniques. In addition, a Read Gate Signal is provided
as an output (Pin 25) which can be used to inform phase
lock loops when to acquire synchronization. When reading from the media in FM, RG is made true when 2 bytes
of zeroes are detected. The FDC 979X must find an
address mark within the next 10 bytes; otherwise RG is
reset and the search for 2 bytes of zeroes begins allover
again. If an address mark is found within 10 bytes, RG
remains true as long as the FDC 979X is deriving any
useful information from the data stream. Similarly for
MFM, RG is made active when 4 bytes of "00" of "FF" are
detected. The FDC 979X must find an address mark
within the next 16 bytes, otherwise RG is reset and
search resumes.
During read operations (WG = 0), the VFOE (Pin 33) is
provided for phase lock loop synchronization. VFOE will
go active when:
a) Both HlT and HlD are True
b) Settling Time, if programmed, has expired
c) The 979X is inspecting data off the disk
IfWFIVFOE is not used,leave open ortieto a 10K resistor
to +5.
On Disk Read operations the Data Request is activated
(set high) when an assembled serial input byte is

I

and 250 ns pulses in MFM (DDEN=O). Write Data provides the unique address marks in both formats.
Also during write, two additional signals are provided
for write precompensation. These are EARLY (Pin 17)
and LATE (Pin 18). EARLY is active true when the WD
pulse appearing on (Pin 30) is to be written early. LATE
is active true when the WD pulse is to be written LATE.
If both EARLY and LATE are low when the WD pulse is
present, the WD pulse is to be written at nominal. Since
write precompensation values vary from disk manufacturer to disk manufacturer, the actual value is
determined by several one shots or delay lines which are
located external to the FDC 979X. The write precompensation signals EARLY and LATE are valid for the duration
of WD in both FM and MFM formats.

transferred in parallel to the Data Register. This bit
is cleared when the Data Register is read by the processor. If the Data Register is read after. one or more
characters are lost by having new data transferred into
the register prior to processor readout, the Lost Data bit
is set in the Status Register. The Read operation continues until the end of sector is reached.

Disk Write Operation
When writing is to take place 0;' the diskette the Write
Gate (WG) output is activated, allowing current to flow
into the Read/Write head. As a precaution against
erroneous writing the first data byte must be loaded into
the Data Register in response to a Data Request from the
FDC 979X before the Write Gate signal can be activated.
Writing is inhibited when the Write Protect input is a
logic low, in which case any Write command is immediately terminated, an interrupt is generated and the Write
Protect status bit is set. The Write Fault input, when
activated, signifies a writing fault condition detected
in disk drive electronics such as failure to detect write
current flow when the Write Gate is activated. On detection of this fault the FDC 979X terminates the current
command, and sets the Wr.ite Fault bit (bit 5) in the Status
Word. The Write Fault input should be made inactive
when the Write Gate output becomes inactive.
For write operations, the FDC 979X provides Write Gate
(Pin 30) and Write Data (Pin 31) outputs. Write data
consists of a series of 500 ns pulses in FM (DDEN = 1)

On Disk Write operations the Data Request is activated
when the Data Register transfers its contents to the
Data Shift Register, and requires a new data byte. It is
reset when the Data Register is loaded with new data by
the processor. If new data is not loaded at the time the
next serial byte is required by the Floppy Disk, a byte
of zeroes is written on the diskette and the Lost Data
bit is set in the Status Register.
At the completion of every command an INTRQ is
generated. INTRQ is reset by either reading the status
register or by loading the command register with a new
command. In addition, INTRQ is generated if a Force
Interrupt command condition is met.

COMMAND WORDS
Type I Commands

The FDC 979X will accept eleven commands. Command
words should only be loaded in the Command Register
when the Busy status bit is off (Status bit 0). The one
exception is the Force Interrupt command. Whenever
a command is being executed, the Busy status bit is set.
When a command is completed, an interrupt is generated and the Busy status bit is reset. The Status Register
indicates whether the completed command encountered
an error or was fault free. _For ease of discussion,
commands are divided into four types. Commands and
types are summarized in Table 1.

The Type I Commands are Restore, Seek, Step, Step-In,
and Step-Out. Each of the Type I Commands contains a
rate field (ror,), which determines the stepping motor
rate as defined in Table 2.
The Type I Commands contain a head load flag (h) which
determines if the head is to be loaded at the beginning
of the command. If h = 1, the head is loaded at the
beginning of the command (HLD output is made active).
If h=O, HLD is deactivated. Once the head is loaded,
the head will remain engaged until the FDC 979X receives
a command that specifically disengages the head. If
the FDC 979X is idle (busy = 0) for 15 revolutions of the
disk, the head will be automatically disengaged (HLD
made inactive).
The Type I Commands also contain a verification (V)
flag which determines if a verification operation is to
take place on the destination track. If V = 1, a verification
is performed, if V=O, no verification is performed.
During verification, the head is loaded and after an
internal 15 ms delay, the HLT input is sampled. When
HLT is active (logic true), the first encountered 10 field
if read off the disk. The track address of the 10 field is
then compared to the Track Register; if there is a match
and a valid 10 CRC, the verification is complete, an
interrupt is generated and the Busy status bit is reset. If
there is not a match but there is valid 10 CRC, an interrupt

Table 1. Command Summary
COMMAND
TYPE
Restore
I
Seek
I
Step
I
Step In
I
Step Out
I
Read Sector
II
Write Sector
II
Read Address
III
Read Track
III
Write Track
III
Force Interrupt
IV

7
0
0
0
0
0
1
1
1
1
1
1

6
0
0
0
1
1
0
0
1
1
1
1

5
0
0
1
0
1
0
1
0
1

1
0

BITS
4 3
0 h
1 h
u h
u h
u h
m F2
m F2
0 0
0 0
1 0
1 b

1

0

V r,
V r,
V r,
V r,
V r,
E F,
E F,
E 0
E 0
E 0
12 I,

ro
ro
ro
ro
ro

2

0
ao

0
0
0
10

562
---------_._-_.

--------------

.-

------

.

__

._-------

is generated, and Seek Error Status bit (Status bit 4) is
set and the Busy status bit is reset. If there is a match but
not a valid CRC, the CRC error status bit is set (Status
bit 3), and the next encountered I D field is read from the
disk for the verification operation. If an ID field with a
valid CRC cannot be found after four revolutions of the
disk, the FDC 979X terminates the operation and sends
an interrupt (INTRQ).
The Step, Step-In, and Step-Out commands contain an
Update flag (u). When u = 1, the track register is updated
by one for each step. When u =0, the track register is
not updated.
On the FDC 9795/7 devices, the SSO output is not
affected during Type 1 commands, and an internal side
compare does not take place when the (V) Verify Flag
is on.

Step-Out
Upon receipt of this command, the FDC 979X issues one
stepping pulse in the direction towards track O. If the
u flag is on, the Track Register is decremented by one.
After a delay determined by the r, ro field, a verification
takes place if the V flag is on. The h bit allows the head to
be loaded at the start of command. An interrupt is
generated at the completion of the command.
Head Positioning
The period of each positioning step is specified by the
r field in bits 1 and 0 of the command word. After the
last directional step an additional 15 milliseconds of
head settling time takes place if the Verify flag is set in
Type I commands. Note that this time doubles to 30 ms
for a 1 MHz clock. If TEST=O, there is zero settling time.
There is also a 15 ms head settling time if the E flag is set
in any Type II or III command.
The rates (shown in Table 2) can be applied to a StepDirection Motor through the device interface.
Step-A 2 J.ls (MFM) or 4 J.IS (FM) pulse is provided as an
output to the drive. For every step pulse issued, the
drive moves one track location in a direction determined
by the direction output.
Direction (DIRC)- The Direction signal is active high
when stepping in and low when stepping out. The Direction signal is valid 12 J.ls before the first stepping pulse
is generated.
When a Seek, Step or Restore command is executed an
optional verification of Read-Write head position can be
performed by setting bit 2 (V = 1) in the command word
to a logic 1. The verification operation begins at the end
of the 15 millisecond settling time after the head is
loaded against the media. The track number from the
first encountered ID Field is compared against the
contents of the Track Register. If the track numbers
compare and the ID Field Cyclic Redundancy Check
(CRC) is correct, the verify operation is complete and an
INTRQ is generated with no errors. The FDC 979X must
find an ID field with correct track number and correct
CRC within 5 revolutions of the media; otherwise the
seek error is set and an INTRQ is generated.

Restore (Seek Track 0)
Upon receipt of this command the Track 00 (TROO)
input is sampled. if TROO is active low indicating the
Read-Write head is positioned over track 0, the Track
Register is loaded with zeroes and an interrupt is generated. If TROO is not active low, stepping pulses (pins 15
to 16) at a rate specified by the r,ro field are issued until
the TROO input is activated. At this time the Track
Register is loaded with zeroes and an interrupt is generated. If the TROO input does not go active low after 255
stepping pulses, the FDC 979X terminates operation,
interrupts, and sets the Seek error status bit. A verification
operation takes place if the V flag is set. The h bit allows
the head to be loaded at the start of command. Note that
the Restore command is executed when MR goes from
an active to an inactive state.
Seek
This command assumes that the Track Register contains
the track number of the current position of the ReadWrite head and the Data Register contains the desired
track number. The FDC 979X will update the Track
register and issue stepping pulses in the appropriate
direction until the contents of the Track register are
equal to the contents of the Data Reg ister (the desired
track location). A verification operation takes place if the
V flag is on. The h bit allows the head to be loaded at the
start of the command. An interrupt is generated at the
completion of the command.

Table 2. Stepping Rates

elK:

2 MHz
2 MHz
1 MHz
1 MHz
2 MHz
1 MHz
X
X
DDEN:
1
0
1
0
r, ro TEST=1 TEST=1 TEST=1 TEST=1 TEST=O TEST=O

Step
Upon receipt of this command, the FDC 979X issues one
stepping pulse to the disk drive. The stepping motor
direction is the same as in the previous step command.
After a delay determined by the r,ro field, a verification
takes place if the V flag is on. If the u flag is on, the Track
Register is updated. The h bit allows the head to be
loaded at the start of the command. An interrupt is
generated at the completion of the command.

0
0
1
1

0
1
0
1

3
6
10
15

ms
ms
ms
ms

3
6
10
15

ms
ms
ms
ms

6 ms
12 ms
20 ms
30 ms

6
12
20
30

ms
ms
ms
ms

1B4}JS
190}JS
19B}JS
20B}JS

36B}JS
380}JS
396}JS
416}JS

The Head Load (HLD) output controls the movement of
the read/write head against the media. HLD is activated
at the beginning of a Type I command if the h flag is
set (h= 1), at the end of the Type I command if the verify
flag (V= 1), or upon receipt of any Type II or III command.
Once HLD is active it remains active until either a Type I
command is received with (h=O and V=O); or if the
FDC 979X is in an idle state (non-busy) and 15 index'
pulses have occurred.

Step-In
Upon receipt of this command, the FDC 979X issues one
stepping pulse in the direction towards track 76. If the
u flag is on, the Track Register is incremented by one.
After a delay determined by the r,ro field, a verification
takes place if the V flag is on. The h bit allows the head to
be loaded at the start of the command. An interrupt is
generated at the completion of the command.

Head Load Timing (HLT) is an input to the FDC 979X
which is used for the head engage time. When HLT = 1,
the FDC 979X assumes the head is completely engaged.

563

I
_

The head engage time is typically 30 to 100 ms depending on drive. The low to high transition on HLD is
typically used to fire a one shot. The output of the one
shot is then used for HLT and supplied as an input to
the FDC 979X.

HLDJ~--...J

;...1------

*"---1

1--50 TO 100mS-l

~

HLT (FROM ONE SHOT)

Head Load Timing

When both HLD and HLT are true, the FDC 979X will then
read from or write to the media. The "and" of HLD and
HLT appears as a status bit in Type I status.

TYPE I COMMANDS FLAG SUMMARY
h = Head Load Flag (Bit 3)
h=1, Load head at beginning
h=O, Unload head at beginning
V= Verify flag (Bit 2)
V= 1, Verify on destination track
V=O, No verify
r, ro= Stepping motor rate (Bits 1-0)
Refer to Table 2 for rate summary
u= Update flag (Bit4)
u= 1, Update Track register
u=O, No update

Type II Commands
The Type II Commands are the Read Sector and Write
Sector commands. Prior to loading the Type II Command
into the Command Register, the system must load the
Sector Register with the desired sector number. Upon
receipt of the Type II command, the busy status Bit is
set. If the E flag =1.(this is the normal case) HLD is made
active and HLT is sampled until true after a 15 msec delay.
If the E flag is 0, HLD is made active and HLT is sampled
with no delay until true. The 10 field and Data Field
format are shown below.
When an 10 field is located on the disk, the FDC979X
compares the Track Number on the 10 field with the
Track Register. If there is not a match, the next encountered
10 field is read' and a comparison is again made. If there

is a match, the Sector Number of the 10 field is compared
with the Sector Register. If there is not a Sector match,
the next encountered 10 field is read off the disk and
comparisons again made. If the 10 field CRC is correct,
the data field is then located and will be either written
into, or read from depending upon the command. The
FDC 979X must find an 10 field with a Track number,
Sector number, side number, and CRC within four
revolutions of the disk; otherwise, the Record not found
status bit is set (Status bit 3) and the command is terminated with an interrupt.
Each of the Type II Commands contains an (m) flag
which determines if multiple records (sectors) are to be
read or written, depending upon the command. If m=O,
a single sector is read or written and an interrupt is
generated at the completion of the command. If m = 1,
multiple records are read or written with the sector
register internally updated so that an address verification
can occur on the next record. The FDC 979X will read
or write multiple records starting with the sector presently
in the sector register. The FDC 979X will continue to read
or write multiple records and update the sector register
until the sector register exceeds the number of sectors
on the track or until the Force Interrupt command is
loaded into the Command Register, which terminates
the command and generates an interrupt.
If the Sector Register exceeds the number of sectors on
the track, the Record-Not-Found status bit will be set.
The Type II commands also contain side select compare
flags. When C=O, no side comparison is made. When
C=1, the LSB of the side number is read off the 10
Field of the disk and compared with the contents of
the (S) flag. If the S flag compares with the side number
recorded in the 10 field, the 979X continues with the 10
search. If a comparison is not made within 5 index
pulses, the interrupt line is made active and the RecordNot-Found status bit is set.
The FDC 9795/7 READ SECTOR and WRITE SECTOR
commands include a 'b' flag. The 'b' flag, in conjunction
with the sector length byte of the 10 Field, allows different
byte lengths to be implemented in each sector. For IBM
compatability, the 'b' flag should be set to a one. The
's' flag allows direct control over the SSO Line (Pin 25)
and is set or reset at the beginning of the command,
dependent upon the value of this flag.

Sector Length Table (9791/3 only)
Sector Length
Number of Bytes
Field (hex)
in Sector (decimal)
00
128
01
256
02
512
03
1024

Field Format

I

GAP 110 I TRACK I SIDE I SECTOR I SECTOR I CRC I CRC GAPI DATA
ICRCICRC
III
AM NUMBER NUMBER NUMBER LENGTH
1
2
II
AM
DATA FIELD
1
2
10 FIELD
DATA FIELD
In MFM only, lOAM and DATA AM are preceded by three bytes of A 1 with clock transition between bits4and 5 missing.

564

Read Sector

Write Sector

Upon receipt of the Read Sector command, the head is
loaded, the Busy status bit set, and when an 10 field
is encountered that has the correct track number,
correct sector number, correct side number, and correct
CRC, the data field is presented to the computer. The
Data Address Mark of the data field must be found within
30 bytes in single density and 43 bytes in double density
of the last 10 field CRC byte; if not, the Record-NotFound status bit is set and the operation is terminated.
When the first character or byte of the data field has
been shifted through the DSR, it is transferred to the DR,
and ORO is generated. When the next byte is accumulated in the DSR, it is transferred to the DR and another
ORO is generated. If the Computer has not read the
previous contents of the DR before a new character is
transferred that character is lost and the Lost Data
Status bit is set. This sequence continues until the complete data field has been inputted to the computer. If
there is a CRC error at the end of the data field, the
CRC error status bit is set, and the command is terminated (even if it is a multiple record command).
At the end of the Read operation, the type of Data
Address Mark encountered in the data field is recorded
in the Status Register (Bit 5) as shown below:

Upon receipt of the Write Sector command, the head
is loaded (HLD active) and the Busy status bit is set.
When an 10 field is encountered that has the correct
track number, correct sector number, correct side
number, and correct CRC, a ORO is generated. The
FDC 979X counts off 11 bytes in single density and 22
bytes in double density from the CRC field and the Write
Gate (WG) output is made active if the ORO is serviced
(i.e., the DR has been loaded by the computer). If ORO
has not been serviced, the command is terminated and
the Lost Data status bit is set. If the ORO has been serviced, the WG is made active and six bytes of zeros in
single density and 12 bytes in double density are then
written on the disk. At this time the Data Address Mark
is then written on the disk as determined by the ao field
of the command as shown below:

STATUS
BIT 5
1

o

The FDC 979X then writes the data field and generates
ORO's to the computer. If the ORO is not serviced in
time for continuous writing the Lost Data Status Bit is
set and a byte of zeros is written on the disk. The command is not terminated. After the last data byte has been
written on the disk, the two-byte CRC is computed
internally and written on the disk followed by one byte
of logic ones in FM or in MFM. The WG output is
then deactivated.

Deleted Data Mark
Data Mark

o

Data Address Mark (Bit 0)
Deleted Data Mark
Data Mark

ao
1

BIT
716151413121110

COMMAND

1 1 1 1m 1F21 ElF, 1
1Jo111m1F21EIF,Jao

READ SECTOR
WRITE SECTOR

°°

°

L

rO=Write hex FB (data) into Data Address Mark field
DATA ADD RESS MARK (ao) ~1
= Write hex F8 (deleted data) into Data AM field
number not tested
F, (9791/3) SIDE COMPARE FLAG (C) -C0=side
l=Slde number tested
F, (9795/7) SIDE SELECT FLAG (S)
DELAY (E)

r

rO=Update SSO to 0
L.J=Update SSO to 1

-C

0=NO delay between HLD activation and HLT Sampling
1 = 15 ms delay between HLD activating and HLT Sampling

F2 (9791/3) SIDE SELECT FLAG (S)

°

JO=Compare for side
-U=Compare for side 1

Sector Length Field
00
01
10
11
L...

F2 (9795/7) SECTOR LENGTH FLAG (b)C01=_-

256
128

512
256

1024 128
512 1024

MULTIPLE SECTORS (m) 5 0= Read (or Write) Single Sectors
L1 = Read (or Write) Multiple Sectors

Figure 1. Type II and III Flag Summary
565

error status bit is set if there is a CRC error. The Track
Address of the 10 field is written into the sector register.
At the end of the operation an interrupt is generated and
the Busy Status is reset.
Read Track
Upon receipt of the Read Track command, the head is
loaded and the Busy Status bit is set. Reading starts
with the leading edge of the first encountered index
pulse and continues until the next index pulse. As each
byte is assembled it is transferred to the Data Register
and the Data Request is generated for each byte. No
CRC checking is performed. Gaps are included in the
input data stream. The accumulation of bytes is synchronized to each Address Mark encountered. Upon completion of the command, the interrupt is activated. RG
is not activated during the Read Track Command. An
internal side compare is not performed during a
Read Track.
Write Track
Upon receipt of the Write Track command, the head is
loaded and the Busy Status bit is set. Writing starts
with the leading edge of the first encountered index
pulse and continues until the next index pulse, at which

Type III Commands
There are three Type III Commands:
• READ ADDRESS-Read the next ID field (6 bytes)
into the FDC.
• READ TRACK-Read all bytes of the entire track,
including gaps.
• WRITE TRACK-Write all bytes to the entire track,
including gaps.
Read Address
Upon receipt of the Read Address command, the head is
loaded and the Busy Status Bit is set. The next encountered ID field is then read in from the disk, and the
six data bytes of the ID field are assembled and transferred to the DR, and a DRO is generated for each byte.
The six bytes of the ID field are shown below:

Although the CRC characters are transferred to the
computer, the FDC979X checks for validity and the CRC

iP----..u

1--

COMPLETE SECTOR

--I

OATA

GAP

to

GAP

DATA

GAP

FIELD 1

3

FielD 2

2

FiElD 2

3

SINGLE SIDED:
DOUBLE SIDED,
DOUBLE SIDED,

SECTOR NO
01-1A
Ot-OF
01-08

BYTES/SECTOR
FM
MFM

128
256
512

SECTOR LENGTH

256
512
1024

00= 128
Ot=- 256

02= 512
03=1024

'DA=:F5 WRITE 3 TIMES MFM ONLY

Figure 2. IBM Compatible Sector/Track Format

566

time the interrupt is activated. The Data Request ·is
activated immediately upon receiving the command,
but writing will not start until after the first byte has been
loaded into the Data Register. If the DR has not been
loaded by the time the index pulse is encountered the
operation is terminated making the device Not Busy, the
Lost Data Status Bit is set, and the Interrupt is activated.
If a byte is not present in the DR when needed, a byte of
zeros is substituted. Address Marks and CRC characters
are written on the disk by detecting certain data byte
patterns in the outgoing data stream as shown in the
table below. The CRC generator is initialized when any
data byte from F8 to FE is about to be transferred from
the DR to the DSR in FM or by receipt of F5 in MFM.
Disk formatting (initialization) is accomplished by the
Write Track command. Each byte for the entire track
must be provided for prope~ formatting. This includes
gap as well as data bytes.
The sequence required to format a diskette begins with
positioning the ReadIWrite head at the desired track.
Once this has been done, it is necessary to perform a
Write Track command to store all the information on a
track. The Write Track command uses ORO to request
each byte from the system MPU, starting with the byte at
the beginning of the physical Index Pulse and ending
with the last gap bytes at the end of the track. Figure 2
illustrates the IBM standard for track formatting.
Normally, each data byte stored on the diskette must
be generated by the system MPU and passed into the
FDC Data Register. However, there are exceptions to
this rule. If a data byte of hex F5 through FE is entered
into the Data Register, then the FDC recognizes this as
an AM with missing clocks or CRC generation code.
Consequently, F5 through FE must not be used in gaps,
data fields, or 10 fields, as this will disrupt normal operation of the FDC during formatting.

L

BIT

1

1111 1011 1bib I I, I

10

I

Force Interrupt is the only Type IV command. This
command permits the MPU to terminate (abort) any
command in progress. Figure 3 tabulates the Type IV
command option bits.
The four bits, 10 -10, are used to select the condition of the
interrupt occurrence. Regardless of which bit is set, any
command currently being executed is immediately
terminated and the Busy status bit is cleared, indicating
"Not Busy". Then, when the condition is met, INTRO
goes high, causing the required interrupt.
If 10 -10 are all" 0", no interrupt occurs, but any currently
executing command is immediately terminated. If more
than one condition is selected, then the interrupt occurs
when any of the conditions is met.
To clear the interrupt, it is necessary to read the Status
Register or to write the Command Register. An exception,
however, is for 10= 1 (Immediate Interrupt). For this case,
the interrupt is cleared with another Force Interrupt
command with 10 -10 all low.
Status Register

The Status Register permits the MPU to monitor a variety
of conditions in the FDC. For each command, the
individual status bits have their own meaning. When a
command is initiated (except for the Force Interrupt
command). the Busy status bit is set and the others are
cleared or updated. If the Force Interrupt command is
entered when another command is in progress, the
Busy status bit is cleared, but the others remain
unaffected. However, if the Force Interrupt command
is initiated when there is not another command in progress, the other status bits are cleared or updated and
represent the Type I Command status. Figure 4 illustrates
the meaning of the status bits for each command.

1

COMMAND
FORCE INTERRUPT

L

READY TRANSITION

-

Type IV Commands

I
I

-C

O= No effect
1 = Forces INTRa when READY input goes low-to-high

10=No effect
= Forces INTRa when READY input goes high-to-Iow
NOT-READY TRANSITIONU
INDEX PULSE iO=No Effect
= Forces INTRa on next INDEX pulse input

L1

IMMEDIATE

- [0= No effect
1 = Forces INTRa immediately

Figure 3. Force Interrupt Command Flags

567

Figure 4A. Status Register Summary
STATUS BIT

COMMAND

WRITE SECTOR

7
Not Ready
Not Ready
Not Ready

READ ADDRESS

Not Ready

READ TRACK

Not Ready

WRITE TRACK

Not Ready

ALL TYPE I
READ SECTOR

4

3

2

1

0

Seek Error
Rec not Found

CRC Error
CRC Error

Track 0

Index

Busy

0
Write ProteCt

5
Head Loaded
Record Type
Write Fault

Lost Data

DRO

Busy

Rec not Found

CRC Error

Lost Data

DRO

Busy

0

0

Rec not Found

CRC Error

Lost Data

DRO

Busy

0

0

0

0

Lost Data

DRIJ

Busy

Write Protect

Write Fault

0

0

Lost Data

DRO

Busy

6
Write Protect

Figure 4B. Status Description for Type I Commands
BIT
87

MEANING

NAME
NOT READY

This bit when set indicates the drive is not ready. When reset it indicates that the drive is
ready. This bit is an inverted copy of the Ready input and logically 'ored' with MR.

86

PROTECTED

When set, indicates Write Protect is activated. This bit is an inverted copy of WRPT input.

85

HEAD LOADED

When set, it indicates the head is loaded and engaged. This bit is a logical "and" of HLD
and HLT signals.

84

8EEK ERROR

When set, the desired track was not verified. This bit is reset to 0 when updated.

83

CRC ERROR

CRC encountered in 10 field.

82

TRACK 00

81

INDEX

When set, indicates Read/Write head is positioned to Track O. This bit is an inverted copy
of the TROO input.
~hen set, indicates index mark detected from drive. This bit is an inverted copy of the
IP input.

80

BU8Y

When set command is in progress. When reset no command is in progress.

Figure 4C. Status Description for Type II and III Commands
BIT
87

NAME
NOT READY

MEANING
This bit when set indicates the drive is not ready. When reset, it indicates that the drive
is ready. This bit is an inverted copy of the Ready input and 'ored' with MR. The Type II
and III Commands will not execute unless the drive is ready.

86

WRITE PROTECT

On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates a Write
Protect. This bit is reset when updated.

85

RECORD TYPE/
WRITE FAULT

On Read Record: It indicates the record-type code from data field address mark.
1= Deleted Data Mark. 0= Data Mark. On any Write: It indicates a Write Fault. This bit is
reset when updated.

84

RECORD NOT
FOUND (RNF)

When set, it indicates that the desired track, sector, or side were not found. This bit is reset
when updated.

83

CRC ERROR

If 84 is set, an error is fOlJnd in one or more 10 fields; otherwise it indicates error in data
field. This bit is reset when updated.

82

LOST DATA

When set, it indicates the computer·did not respond to ORO in one byte time. This bit is
reset to zero when updated.

S1

DATA REOUEST

This bit is a copy of the ORO output. When set, it indicates the DR is full on a Read Operation
or the DR is empty on a Write operation. This bit is reset to zero when updated.

80

BUSY

When set, command is under execution. When reset, no command is under execution.

568

Write Data Timing:
PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNITS

CONDITIONS

Write Data Pulse Width

Twp

450
150

550
250

Write Gate to Write Data

Twg

Write
Early
Early
Write
Write

Tbc
Ts
Th

500
200
2
1
2,3, or 4

nsec
nsec
/lsec
/lsec
/lsec
nsec
nsec

FM
MFM
FM
MFM
±CLK Error
MFM
MFM

/lsec
/lsec
nsec
nsec
nsec
nsec

FM
MFM
CLK=1 MHZ
CLK=2 MHZ
CLK=1 MHZ
CLK=2 MHZ

data cyle Time
(Late) to Write Data
(Late) From
Data
Gate off from WD

125
125
2
1

Twf

WD Valid to Clk

TWdl

WD Valid after Clk

Twd2

100
50
100
30

These values are doubled when CLK=1 MHz.

Write Data Timing
WRITE GATE

--1
--l

WRITE DATA

L
Twg

I---Tbc

----l Twp f-I. . .- - -....~~I

f-

Twl

11. . __---'11. . __---'11. . ___

l---soo os - - - - 1__
./

eLK
(1MHZ)

I-

L

IL-_______-'

WD _ _ _ _ _

L~LLLL~~

~TWd2

TWdl~

~125

elK
(2MHZ)

I

IL_______-.JI

WD-------~~~~~~
Tdl---i
W

WRITE DATA/CLOCK RELATIONSHIP
(ODEN=O}

569
- - - - - - - - - - - - - - - - - - - - - _ .....

_-.._ .

125---1

~TWd2

I

I

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range ......................................................................... O°C to + 70°C
Storage Temperature Range ...................................................................... - SsoC to + 1S0°C
Lead Temperature (soldering, 10 sec.) ....................................................................... + 32SoC
Positive Voltage on Pin 40, with respect to ground ............................................................ + lSV
Positive Voltage on any other Pin, with respect to ground ...................................................... + 8V
Negative Voltage on any Pin, with respect to ground ........................................................ - 0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute
Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes
or "glitches" on their outputs when the AC power is switched on and off. In addition, voltage transients on the
AC power line may appear on the DC output. If this possibility exists it is suggested that a clamp circuit be used.
ELECTRICAL CHARACTERISTICS (TA ';" O°C to 70°C, Vee
SYMBOL

PARAMETER
DC CHARACTERISTICS
Input Voltage levels
low level, V,L
High level, V,H
Output Voltage Levels
low Level VOL
High Level VOH
Output leakage, ILO
Input Leakage, I,L
Output Capacitance
Input Capacitance
Supply Current
AC CHARACTERISTICS
Processor Read Timing
Address Setup Time
Address Hold Time
RE Pulse Width (CL=SOpF)
ORO Reset Time
INTRa Reset Time
Data Delay Time (CL=SOpF)
Data Hold Time (CL=SOpF)
Microprocessor Write Timing
Address Setup Time
Address Hold Time
WE Pulse Width
ORO Reset Time
INTRa Reset Time
Data Setup Time
Data Hold Time
Disk Input Data Timing
RAWREAD Pulse Width
Clock Setup Time
Clock Hold Time for MFM
Clock Hold Time for FM
RAWREAD Cycle Time
RClK High Pulse Width
RClK Low Pulse Width
RClK Cycle Time

=

+ SV
TYP

± S%, unless otherwise noted)

MAX

UNIT

0.8

V
V

O.4S

V
V

2.0

2.4

MFM
FM
MFM
FM
MFM
FM

tSETR
tHLoR
tRE
tORR
t'RR
toAcc
tOOH

SO
10
400

tSETW
tHLOW
tWE
tORR
t'RR
tos
tOH

SO
10
3S0

t pw
td
tCd
tos
tbC
ta

100'
40
40
40
1S00
0.8
0.8
0.8
0.8

tb

SO

SOO'

tSTP

DIRC Setup Time
tOIR
MR Pulse Width
tMR
IP Pulse Width
tiP
WF Pulse Width
tWF
ClK Cycle Time
tCYC
* These Values are doubled when ClK = 1 MHz.

230
200
2*
4*

160

pf
pf
mA

SOO
3000'
3S0
1S0

ns
ns
ns
ns
ns
ns
ns

Figure
Figure
Figure
Figure
Figure
Figure
Figure

S
S
S
S
S
S
S

ns
ns
ns
ns
ns
ns
ns

Figure
Figure
Figure
Figure
Figure
Figure
Figure

6
6
6
6
6
6
6

SOO
3000'

ns
ns
ns
ns
ns

l'
2'
1*
2*
2*
4*

f.J.s
f.J.s
f.J.s
f.J.s
f.J.s
f.J.s

20000
20000

ns
ns
f.J.S
f.J.s

12
SO*
10*
10*
0.5*
570

f.J.A

200

2S0
2S0

IOL=1.6 mA
IOH=100 f.J.A
0.4 ~ 3.SV
0.4 ~ 3.SV

f.J.A

2S0
70

tc
tco,
tC02

MFM
FM

SOO'

COMMENTS

10
10
S
10

Miscellaneous Timing
ClK low Pulse Width
ClK High Pulse Width
STEP Pulse Width

MIN

f.J.S
f.J.S
f.J.S
f.J.s
f.J.s

Figure 7, See Note
Figure 7 See Note
Figure 7
Figure 7
1800 at 70°C, Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure

8
8
8
8
8
8
8
8
8

Figure 5.
Microprocessor
Read Timing

I-

t-

- j To,"

1
~T''"===:l
I
t
I -jTH'£_____________

I

DRO

p,

'6#5 • (MFM) or 32". • (FM)

INTRO~

cs----±
Ao.A,
___ _ __ I

~T"'+T"-1

fiE

"----J.

T""
DAlo-DAL7

-1

t;:: I

CO

-jTOOHf--

Figure 6.
Microprocessor
Write Timing

I-

r~T.AA===i

'6". • (MFM) or 32#5 • (FM)

-j

I

DRO

cs---- x I

-

-

I

-

-

-

I

~T"'+Tw'-1

WE

1

'-1}
TH"t-=

INTRO~
Ao,A.

p'

To""

_

y------------I

"---l
--jT"f-

CD

DALc-OAL7

Figure 7.
Disk Input
Timing

-1TOH~

-l·f-t~

RAWREAD

-I

t~

U

U

too
-l t, ~Io~
I

I

RCLK

~T.

I

I
T'=1

-IT,

Note: Pulse width on AAWAEAD (Pin 27) IS normally 10-300 ns. However, pulse may be any width if pulse Isenlirely
within wmdow. If pulse occurs in both windows, then pulse width must be less than 300 ns for MFM at ClK=2 MHz and
600 ns for FM at 2 MHz. Times double for 1 MHz.

Figure 8.
Miscellaneous
Timing

il'

I

I

I--T"--l

WF

I

I

f---Tw.---l
I
I
f-T",--j f--TM'---l

MR

CLK~

1+~
STEP IN
Teol

I~

DIRC~

\.To,,~

rToo-j f--T,,,
STEP

n

U

571

n

~TSTP

DISK FORMATS
Disks may be formatted in IBM 3740 or System 34
formats with sector lengths of 128, 256, 512, or
1024 bytes.
IBM 3740 Format
This single-density (FM) format utilizes 128 bytes/
sector. The bytes to be generated by the system
MPU for use in the execution of the Write Track
command are shown in Figure 9.
IBM System 34 Format
This double-density (MFM) format utilizes 256
bytes/sector. The bytes to be generated by the
system MPU for use in the execution of the Write
Track command are shown in Figure 10.
Non-IBM Formats
Unique (non-IBM) formats are permissible providing the following restrictions are understood.
• Sector length may only be 128, 256, 512, or
1024 bytes.
• Gap sizes must conform to Figure 11.

DATA
BYTE
(hex)

NO.OF
BYTES

4E

r-

ONE
SECTOR -

CD

00
F6
FC
4E
OO

FF
00
FC
FF

-

ONE
SECTOR


Bit
Counter

TEST

BDONE
EN

cp

~----+--- BClR

NRZ

---++ro---~::---Ql--l ;:........,1--- DOUT

ClK

_-+....-,

8Bit
Shift Register

DOO D01 D02 D03 D04 D05 D06 D07

573

I

DESCRIPTION OF PIN FUNCTIONS
PIN NUMBER

SYMBOL

NAME

FUNCTION

1

CLK

CLOCK

2
3

NC
BCLR

NO CONNECTION
BYTE CLEAR

4
5-9,11-13
10
14

TEST
DOO-D07
Vss
SHFCLK

TEST INPUT
DATAO-DATA7
GROUND
SHIFT CLOCK

15

BDONE

BYTE DONE

16

DOUT

DATA OUT

17

ST

START

18

NRZ

NRZDATA

19

EN

ENABLE

20

Vee

Vee

NRZ data is entered into the 8-bit shift register on the
low-to-high transition of clock.
No connection. This pin is to be left open by the user.
When this line is at a logic 0, the BDONE (pin 15) line is
held reset.
This pin must be left open by the user.
8 bit parallel data outputs.
Ground.
Inverted copy of CLOCK (pin 1) which is active when
EN (pin 19) is at a logic 1.
This signal is forced to a logic 1 signifying 8 bits of data
have been assembled. BDONE remains in a logic 1
state until reset by a logic 0 on the BCLR (pin 3) line.
Serial Data Output from the 8th stage of the internal
shift register. DOUT is in a high impedance state
whenever EN (pin 19) is at a logic O.
This line enables the byte counter and is used for
synchronization. It must be held to a logic 1 prior to first
data bit on the NRZ (Pin 18) line.
NRZ serial data is entered on this pin and clocked by
the low to high transition of CLK (pin 1).
When this signal is at a logic 0, DOUT, SHFCLK, and
BDONE outputs are in a high impedance state.
+ 5V power supply input.

OPERATION
Prior to shifting data through the device, the HOC 1100-01
must be synchronized to the data stream. The ST line (Pin
17 high) is used to hold the internal bit counter in a cleared
state until valid data (NRZ) and clocks (ClK) are entered.
The ST line is a synchronous input and therefore requires
one full cycle of the ClK line (Pin 1) to occur in order to accept
a ST condition. After this happens, the device is ready to
perform serial to parallel conversions.
Data is entered on the NRZ line and clocked into the a-bit
shift register on the low-to-high transition of ClK. The ST
line must be set low during the low time of ClK. Data is
accepted on low-to-high transition of the clock while the highto-low transition of ClK increments the bit counter. After a
data bits have been entered the final high-to-Iow transition
of ClK sets an internal latch tied to the BOONE line (Pin
15). At the same time, the contents of the shift register are
parallel loaded into an a bit register making the parallel data
available on the 000-007 outputs. BOONE will remain in a
latched state until the BClR is set to a logic 0, clearing off
the BOONE signal. BClR is a level triggered input and must
be set back to a logic 1 before the next a bits are shifted
through the register. BClR has no effect on the serial shifting process. When the next ~ bits are received, BOONE will
again be set and the operation continues.

When interfacing to a microprocessor, BOONE is used to
indicate a parallel byte is ready to be read. As the processor
reads the data out of the 000-007 lines, the BClR line
should be strobed to clear off BOONE in anticipation of the
next assembled byte. An address decode signal generated
at the host may be used for this purpose. During a powerup condition, the state of BOONE is indeterminant. It is recommended that BClR be strobed low after power-up to
insure that BOONE is cleared.
The serial output line from the last stage of the shift register
is available on the DOUT pin. An inverted copy of ClK is
available on the SHFClK pin. Both DOUT (Pin 16) and
SHFClK (Pin 14) can be used to drive another shift register
external to the device.
The three signals BOONE, DOUT, and SHFClK can be
placed in a high impedance state by setting EN (Pin 19) to
a logic O. Likewise, EN must be at a logic 1 in orderforthese
signals to be active.
The TEST pin is internally OR'ed with the ST line to inhibit
the bit counter. It is recommended that TEST be left open
by the user. An internal pull-up resistor is tied to this pin to
satisfy the appropriate logic level required internally for
proper device operation.

574

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range ................................................................................. O'C to + 50'C
Storage Temperature Range ................................................................................ - 55' to + 150'C
lead Temperature (soldering, 10sec.) ............................................................................. +300'C
Positive Voltage on any I/O Pin, with respect to ground. . . .. . . . . .... . . . .. .. .. .. . . .. .. . ..... .... ....................... + 7.0V
0.2V
Negative Voltage on any I/O Pin, with respectto ground ............................. ~II.~

.. ' ................... 'St:o~:~ ~~::att~:~ 'Ii'~t~~ ~~; ~~~~~ ·~~;~~~~·~t·~~~~~~ 't~';~~ '~~~;~~.' ~~i~' ~'~;r~h~ .Sorn~:r(Jh~!4f/N.·· .. ··:'~~·~f~~~
is'

device at these or at any other condition above those indicated in the operational sections of thl"

= O'C to 50'C; Vee =

DC ELECTRICAL CHARACTERISTICS: TA
SYMBOL
VIL
V,H
Va
VOH
Vee
Icc

PARAMETER
Input low Voltage
Input High Voltage
Output low Voltage
Output High Voltage
Supply Voltage
Supply Current

AC ELECTRICAL CHARACTERISTICS: TA

SYMBOL
teL
t LS
t HS
tos
tVB
t RS
tBW
tse
tes
tso
tFo
toH

MIN
-0.2
2.4

=.

= OV

MAX
0.8

TYP'

0.4
2.4
4.5

5.0

= O'C to 50'C; Vee = 5V
MIN
0
0
0
15
65

PARAMETER
ClK FREQUENCY
J ClKtoST
1 ClKtoST
Data set-up to 1 ClK
BDONE valid from 1 ClK
BDONE reset from BClR
BClR Pulse Width
1 ClK to J SHFClK
J ClK to 1 SHFClK
Data delay from 1 SHFClK
Enable to DOUT ACT!VE
Data Hold w.r.t. 1 ClK

NOTES: 1. Typical Values are for TA

+ 5V ± 10%, Vss

5.5
100

± 10%, Vss

= OV

TYP'

MAX
5.25

110
110

50
90
100
55
90
25

25'C and Vee

=

~,.tq9!irni~~J;~~%'tf~~"
"Qe. . . .

UNIT
V
V
V
V
V
mA

UNIT
MHZ
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec

CONDITION

10L
10H

= 3.2 mA
= -200jJ.A

All Outputs Open

CONDITION
ST
ST

=
=

1 (min 200nsec)
1 (min 200nsec)

EN
EN
EN
EN
EN
EN

=
=
=
=
=
=

1
1
1
1
1
1

I

+ 5.0V

elK
tLs

-----J : :..- t

I : ---..:

'

tel:"--

______~'~I~:___H_S_____to_S__.~:-,~~--tD-H~'-4-+~----,----:-------------------------NRZ
DOX
BDONE

--.J

,
----'

,

~,-------Tt-r--~
......- IRS

BClR

I

I

, ,
~ :..-tsc
Ics ............

DOUT

-

,

L.-tSD

~_--A,~~~~~~~A-~~~'-~~~~-A~-A~-A
~ ;'-'tFO

EN

~~-----------------------------------

575

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applica·
tions: consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices.described any license under the patent rights of SMC or others. S~C reserves the right to make changes
at any time in order to Improve design and supply the best product possible

p76

HDC 1100=12

STANDARD MICROSYSTEMS

PRELIMINARY

Hard Disk Improved MFM Generator
FEATURES

PIN CONFIGURATION

o Single + 5 Volt Power Supply
o Write Precompensation
o Address Mark Generation
o 5 Mbit Data Rate
o Converts NRZto MFM
020 Pin DIP
On-Channel COPLAMOS®Silicon Gate Technology

NRZ

1

20 Vee

SKPEN

2

19 AO

WCLK

3

18 A1

WCLK

4

17 MR

RWC

5

16 MFM

CS

6

15 INTRO

DROCLK

7

14 DRO

INTCLK

8

13 EARLY

2XDR

9

12 LATE

Vss 10

11 NOM

GENERAL DESCRIPTION
The HOC 1100-12 "improved" MFM Generator converts
serial NRZ data into an MFM (Modified Frequency Modulated) data stream. The MFM signal may be used to record
information on a Winchester Disk.
In addition, the HOC 1100-12 generates Write Precompen-

sation signals required to compensate for bit shift effects
on the recording medium.
The HOC 1100-12 has the ability to delete clock pulses in
the outgoing data stream in order to record Address Marks.

RWC

DROCLK
DRO

NRZ
WCLK

WCLK

4BIT
SHIFT
REG.

WRITE
PRECOMP
GEN.
MFMGEN

EARLY
NOM
LATE
INTCLK
INTRO
MFM

AO
A1

DECODE
LOGIC

CS
SKPEN

MR

MFM GENERATOR

INTERRUPT CONTROLLER

577

DESCRIPTION OF PIN FUNCTIONS

2

SKPEN

NAME
NON-RETURN-TO
ZERO
SKIP ENABLE

3
4

WCLK
WCLK

WRITE CLOCK
WRITE CLOCK

5

RWC

9

2xDR

REDUCED WRITE
CURRENT
2 TIMES DATA RATE

10

Vss
NOM

Vss

11
12

LATE

LATE

13

EARLY

EARLY

16

MFM

MFM DATA

6

CS

CHIP SELECT

8

INTCLK

7

DRQCLK

15

INTRQ

INTERRUPT
REQUEST CLOCK
DATA REQUEST
CLOCK
INTERRUPT
REQUEST

14

DRQ

DATA REQUEST

17

MR

MASTER RESET

Ao, A,

ADDRESS 1, 0

Vee

Vee

PIN NUMBER
1

18,19

20

SYMBOL
NRZ

FUNCTION
NRZ data input that is strobed into the MFM generator
byWCLK(I).
This input arms the SKIP logic for recording Address
Marks when set to a logic 1.
Complimentary clock inputs. NRZ data is clocked into
the MFM Generator on the high-to-Iow transition of
WCLK (pin 3).
This signal when high, enables EARLY, LATE and
NOM outputs.
This input is used to latch EARLY, LATE, NOM and
MFM outputs.
Ground.

Output signal from the Write Precompensation Logic
used to signify that data is to be written nominal.
Output signal from the Write Precompensation Logic
used to signify that data is to be shifted LATE before
writing.
Output signal from the Write Precompensation Logic
used to signify that data is to be shifted EARLY before
writing.
This outRut contains the MFM encoded data derived
from the NRZ (pin 1) line.
Low input signal used to enable the Address decode
logic.
A high-to-Iow transition on this line will latch the INTRQ
(pin 15) at a logic O.
A high-to-Iow transition on this line will latch the DRQ
(pin 14) at a logic O.
This output is latched at a logic 0 when INTCLK (pin 8)
makes a high-to-Iow transition while the decode logic is
disabled.
This output is latched at a logic 0 when DRQCLK (pin
7) makes a high-to-Iow transition while the decode
logic is disabled.
A low level on this line causes DRQ and INTRQ to set
at a logic 1.
When CS is low and the address lines are high, INTRQ
is cleared; if the address lines are low then DRQ gets
cleared. (i.e. set at a logic 1).
+ 5V power supply input.

NOMINAL

OPERATION
The HDC 1100-12 is divided into two sections: MFM Generator and Interrupt Logic. The MFM Generator converts
NRZ data into MFM data and provides Write Precompensation signals. The Interrupt Logic may be used to generate
Interrupt signals. The two sections of the device are isolated and have no common input or output signals.
Prior to entering data, the SKPEN line must be set to a logic

logic is enabled. As long as zeroes are being shifted into
the NRZ line, the device generates normal MFM data. On
receipt of the first non-zero bit (typically the MSB of the A 1
16) the skip logic begins to count WCLK cycles. When the
MFM generator tries to produce a clock between data bits
2 and 3, the skip logic disables the MFM generator during
that time. The result for A 1 '6 data is a clock pattern of OA '6
instead of OE'6' Although other data patterns may be used,

oto enable only clocks in the data stream. Data is entered

on the NRZ line and strobed on the high-toclow transition of
WCLK. The encoded NRZ data appears on the MFM (pin
16) output lagging by one clock cycle.
Write Precompensation signals EARLY, LATE, and NOM are
generated as each data or clock pulse becomes available
at the input when RWC is logic 1.
The SKPEN signal is used to record a unique data/clock
pattern as an Address Mark, using A 1 data with OA clock.
This pattern is used for synchronization prior to data or ID
fields that are read from the disk.

X

When the SKPEN signal is set to a logic 1, the internal skip

578

MR

A,

Ao

CS

DRQ

0

X

X

X

H

H

1

X

X

1

QN

QN

1

0

0

0

H

QN

1

1

1

0

QN

H

1

1

0

0

QN

QN

1

0

1

0

QN

QN

= Don't care

QN

INTRQ

= remains at previous state

INTERRUPT REQUEST LOGIC TABLE

the MSB of the pattern .nust be a 1 (80'6 or higher) in order
to enable the skip logic at the proper time. After the skip
logic has performed, it then disables itself and MFM data is
recorded normally starting with the succeeding byte. To reenable the skip logic again, the SKPEN line must be strobed.
The Interrupt Logic is used to clear Data Requests (ORa)

and Interrupt Requests (INTRa) ~selecting CS (pin 6) in
combination with AO and A 1. The MR (Master Reset) signal
is used to clear both ORa and INTRa simultaneously. ORa
and INTRa can be set to a logic 0 only by a low level or
ORaCLK and INTCLK respectively. The signal will remain
at a logic 0 until cleared by a MR or proper address selection via CS, A 1 and AO.

TO BE SENT

LAST DATA SENT
X

SENDING

NEXT

EARLY

1

0

H

LATE
L

NOM
L
L

1

X

0

1

1

L

H

0

0

0

1

H

L

L

1

0

0

0

L

H

L

L

L

H

ANY OTHER PATTERN

WRITE PRECOMPENSATION LOGIC TABLE

MAXIMUM GUARANTEED RATINGS·
Operaling Temperature Range ............................................................. .
. .............. O·C to + 50·C
Storage Temperalure Range .............................................................. .
. ....... -55· to + 150·C
Lead Temperature (soldering, 10 sec.) ................................................... .
. .......... +300·C
Positive Vollage on any I/O Pin, with respect 10 ground ................... , ............... .
. ....... +7.0V
Negative Vollage on any I/O Pin, with respecl 10 ground ................................... .
. ... -0.2V
Power Dissipation ............................................................................. .
watt
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
device al Ihese or al any other condilion above those indicaled in the operational sections of Ihis specification
DC ELECTRICAL CHARACTERISTICS: T. = O·C to 50·C; Vee = + 5V ± 10%; Vs• = OV
Inpul Low Vollage
High Voltage
Low Voltage
High Voltage
Voltage
Currenl

10L = 3.2mA
10H =-200 ....A

0.4
2.4
4.5

5.0

5.5
100

All

AC ELECTRICAL CHARACTERISTICS: T. = O·C to 50·C; Vee = + 5V ± 10%; Vs• = OV
SYMBOL
IFR
los
10H
IMF
IFM
tWN
IWE
IWL
IMR
IMo
IMI
loa
t,a
too
til
t.o
t.,
leo

Ie,
tRN
tTE
tTN
tTL

PARAMETER
WCLK FREQUENCY
Data Selup w.r.t. I WCLK
Data hold w.r.t. I WCLK
I WCLK to IMFM delay
I WCLK to I MFM delay
Data delay to NOM from
IWCLK
Data delay to EARLY from
IWCLK
Dala delay to LATE from
IWCLK
Master reset pulse width
I MRto I DRQ
IMR 10 IINTRQ
DRQCLK pulse width
INTCLK pulse width
I DRQCLK to DRQ
IINTCLK 10 INTRQ
IAXtolDRQ
I AXt011NTRQ
ICSt01 DRQ
I CS to 11NTRQ
I RWClolNOM
12XDR to 1 EARLY
I 2XDR to 1 NOM
I 2XDR to 1 LATE

MIN

TYP'

MAX

UNIT

5.25
210
230
240

MHZ
nsec
nsec
nsec
nsec
nsec

230

nsec

230

nsec

10
25

50
150
150
50
50
120
120
145
160
145
180
145
75
75
75

Notes: 1. Typical Values are for T. = 25·C and Vee = + 5.0V.

579

nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec

CONDITION

Pin1 LOW
Pin 1 LOW

2

0

3

4

5

6

7

WCLK
NRZ

a 1...;....._
....
.......

0

MFM

-I

2XOR

, ,
,-,

tWE - - , .

I,

--t

14--

tTE

/C1L----------------:~_r:-------'~tcl~---+-----­

EARLY

'l

: - - - , : . - tTN

NOM

,
tWN---:

tI

,

-'

I

!-+- tWL

I

---.J:..-tTL
I.

,
------~--~~------------~~~------~~
I
I

LATE

r----------------r--"i

I

tRN---l

,--

RWC

MFM GENERATOR TIMING

-

--ooj

tMR

I+-

CSorAX~ __

MR~--

ORO

--l -

-1J

t MO

~ .... tMI

--

INTRO~

___ --I

too

tcoort Ao
ORO

__

INTRO

--"'1

i

STANDARD MICROSYSTEMS
CORPORATION

...... _tCl
~--

I---u-I

___ --I

t-

DROCLK~

ORO

I I --

INTCLK

too

INTRO ---+l

t,O

tIl

Circuit diagrams utilizing SMC products are included as a means 01 Illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the nght to make changes
at any time in order to improve design and supply the best product possible

580

HDC 1100-03
PRELIMINARY

Hard Disk Address Mark Detector
FEATURES

PIN CONFIGURATION

D Single + 5 Volt Power Supply
D Decodes A 1-0A

RClK 1

D Synchronous Clock/Data Outputs

DIN 2

D 5 MBit Data Rate
D Address Mark Detection

D 20 Pin DIP
D n-Channel COPlAMOS® Silicon Gate Technology

20 Vee
19 RST

RClK 3

18 CP

ClKIN 4

17 NC

DOUT 5

16 AMDET

NC 6

15 AMDET

NC 7

14 QOUT

TEST1

8

ENDET 9
Vss 10

13 NC
12 DClK
11 TEST2

GENERAL DESCRIPTION
The HOC 1100-03 Address Mark Detector Provides an efficient means of detecting Address Mark Fields in an MFM
(NRZ) data stream. MFM clocks and data are fed to the
device along with a window clock generated by an external
data separator. The HOC 1100-03 searches the data stream

CP
RST

:

DIN
RClK

HV

for a DATA = Ai, ClK = OA pattern and produces and AM
DET signal when the pattern has been found. NRZ data is
output from the device for driving aseriallparaliel converter.
An uncommitted latch is also provided for use by the data
separator circuitry if required.

C
R

I

ryQI

r-------------~.~ QOUT

Q 1-------1- DOUT

D
8BIT
SHIFT REG

, . - - - - TEST1

r-'--'--...L...L......J--'--'--'If-_ _ DClK
1-------1- AMDET

ENDET

r--t--l,-r'-"rT-r,--,-t~----AMDET
' - - - - - TEST 2

R
ClK IN ----!---ID

8BIT
SHIFT REG

RClK ----t-QC

581

I

Q

DESCRIPTION OF PIN FUNCTIONS
PIN NUMBER
1
3
2

RCLK
RCLK

READ CLOCK
READ CLOCK

inputs used to clock DIN and
CLK IN into the AM detector.

DIN

DATA INPUT

4

CLKIN

CLOCK INPUT

MFM data pulses from the external Data Separator are
connected on this line.
MFM clock pulses from the external Data Separator
are connected on this line.

5

DOUT

DATA OUTPUT

Data Output from the internal Data Shift register,
synchronized with DCLK.

6,7,13,17
8
11
9

NC
TEST 1
TEST 2
ENDET

No Connection

To be left open by the user.

SYMBOL

FUNCTION

NAME
Com~mentary clock

TEST 1
TEST 2
ENABLE
DETECTION

To be left open by the user.
A logic 1 on this line enables the detection logic to
search for a data A 1" and clock.
GROUND.
Clock output that is synchronized with DATA OUT (Pin

10
12

Vss

Vss

DCLK

DATA CLOCK

14
15

aOUT
AMDET

LATCH OUTPUT

16

AMDET

ADDRESS MARK
DETECT

18

CP

CLOCK PULSE

19

RST

RESET

20

Vee

Vee

5).
Signal output from the uncommitted latch.

ADDRESS MARK
DETECT

Complimentary Address Mark Detector output. These
signals will go active when a Data = A 1" Clock = OA"
pattern is detected in the data stream.
A low-to-high transition on this line will cause the
aOUT (Pin 14) to be latched at a logic O.
A logic 0 on this line will cause the aOUT (Pin 14)
signal to be set at a logic 1.
+ 5V power supply input.

OPERATION
Prior to shifting data through the device, the internal logic
must be initialized. While the ENDET (Pin 9) line is at a logic
0, shifting of data will be inhibited and AMDET, AMDET,
DClK, and DATA OUT will remain inactive.
When ENDET is ~ogic 1, shifting is enabled. NRZ data
is entered on the DIN line (Pin 2) and shifted on the highto-low transition of RClK (Pin 1). NRZ clocks are entered
on the ClK IN line, and shifted on the high-to-Iow transition
of RClK (Pin 3). The DOUT line (Pin 5) is tied to the last
stage of the Internal Data Shift register and will reflect information clocked into the DIN line delayed by 8 bits.
While each bit is being shifted, a 16 bit comparator is continuously checking the parallel contents of the shift registers for the DATA = A 1'6 ClK = OA'6 pattern. When this
pattern is detected, AMDET will be set to a logic 0 and
AMDET will be set to a logic 1. AMDET and AMDET will
remain latched until the device is re-initialized by forcing

ENDET to a logic O.
When an AM is detected, DClK will begin to toggle. Data
present on the DOUT line may then be clocked into an
external serial/parallel converter. DClK will remain inactive
when ENDET is held at a logic O.
An uncommitted edge-triggered flip/flop has been provided
to facilitate the detection of high-frequency by the data separator, but may be used for any purpose. The low-to-high
transition of CP (Pin 18) will set the QOUT (Pin 14) to a logic
O. QOUT may be reset back to a logic 1 by a low level on
the RST line (Pin 19).
TEST1 and TEST2 are output lines. TEST1 is an active low
pulse when an A 1'6 is detected, and TEST2 is an active low
pulse when a OA'6 is detected. These signals are used for
test points and therefore should be left open by the user if
not required.

582

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range ................................................................................. O°C to + 50°C
Storage Temperature Range ................................................................................ -55°to + 150°C
Lead Temperature (soldering, 10 sec.) ............................................................................... + 300°C
Positive Voltage on any I/O Pin, with respect to ground .................................................................. + 7.0V
Negative Voltage on any I/O Pin, with respect to ground ................................... ,"'" ..................... - 0.2V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . .::;~8~
0.75W
'Stresses above those listed may cause permanent damage to the device. This is a stress rat': ..D:>::·'No·~l;/~,~'
ration of the
device at these or at any other condition above those indicated in the operational sections of ,.:' ~P:;~zv.;~'!.rr(/~t~lJ'

"': "..............
. .:-..

DC ELECTRICAL CHARACTERISTICS: TA = O°C to 50°C; Vee = +5V ± 10%, Vss = OV
SYMBOL

PARAMETER
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Supply Voltage
Supply Current

V"
V'H
VOL
VOH
Vee
Icc

MIN
-0.2
2.4

TYP'

MAX
0.7

5.0

CONDI~~·;~i::;

UNIT
V
V
V
V
V
mA

0.4
2.4
4.5

., .'. '.'

'*N':~n,;.ii!'~"~'"
·~Io/I;.""tJ:!:~iloii::.'·f.:\

5.5
100

10L = 3.2mA
10H = -200,...A
All Outputs Open

AC ELECTRICAL CHARACTERISTICS: TA = O°C to 50°C; Vee = + 5V ± 10%, Vss = OV
SYMBOL
tRe
tST
tHT
too
tRO
tRA
tRM
tRO
tEA
tRO
tRW
tew
tea

PARAMETER
RCLK Frequency
Data Setup time
Data Hold time
DOUTto DCLK DELAY
! RCLK to t DCLK
! RCLKto tAMDET
! RCLK to! AMDET
! RCLK to DOUT
! ENDETto ! AMDET
! RST to t aOUT
Pulse width of RST
CP Pulse width
tCPto! aOUT

MIN

MAX
5.25

TYP'

CONDITION

UNIT
MHZ
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec

40
10
110
120
115
125
135
130
110
50
90
106

ENDET
RCLK
DIN

____

__

1ST.......

~

I tHT

__ __ __ __

: . - tRO

~~~~O ~~O ~ ~ ~~~:_1 ~------~:------

RCLK
I

CLKIN

i, ____________
~'.

1
a
1
a I
~~~~--~---OA ______________

TEST 1

:La

(AIDET)

TEST 2

~

--~==---------------------------------,~r.w:~----~----(OADET)
:.tAM-;J

AMDET

I

I

I,
IRA

'

~

I

L -______L -___

AMDET

: -+:r=F~----~----------------------------------------------"T.-,__.u starlof A1

DOUT

----------------~~~

'""~:•

too ----'

DCLK

L.-

--------------------------------------------~I~

583

0

I
I

-

Circuit diagrams utilizing SMC products are included as a means of itlustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However. no responsibility is
assumed for inaccuracies. Furthermore, such mformation does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

584

HDC 1100-04
PRELIMINARY

Hard Disk CRC Checker/Generator
FEATURES

PIN CONFIGURATION

o Single + 5 Volt Power Supply
o Generates/Checks CRC
o Latched Error Outputs
o CCITT-16 CRC
o Automatic Preset

DIN

D20PinOlP
On-Channel COPLAMOS®Silicon Gate Technology

1

DOCK 2

19 NC

SHFCLK 3

18 NC

NC 4

17 NC

NC 5

16 CRCOK

CWE 6

15 TIMCLK

DaCE 7

14 WCLK

CRCIZ 8

13 CRCOK

NC 9

12 SKPCLK

Vss 10

11 DOUT

GENERAL DESCRIPTION
The HOC 1100-04 CRC Checker/Generator generates a
Cyclic Redundancy Checkword from a serial data stream,
and checks for the proper CRC in a received serial data

stream. In addition to the transmitted CRC output, compJimentary latched "CRCOK" outputs are provided to indicate
CRC errors in the check mode.

CRCIZ - - - - - ,

1-.......- - - - - - SKPCLK

-~-----1 ])

DaCE

POLYNOMIAL GEN
x16 + x12 + x5 + 1

Q

-----I

DOCK - - - - - ( j

Xl-WCLK ..
----I

.;. 16

1 - - - - - - - 0..- TIMCLK

585
--~~~----------

CRCOK
CRCOK

DESCRIPTION OF PIN FUNCTIONS
PIN NUMBER
1

SYMBOL
DIN

NAME
DATA INPUT

FUNCTION
Active low serial input data stream is used to generate/
check the 2 byte CRC word.
After a byte of data has been transferred, in, this input
signal is used to latch the state of DOCE in an internal
D flop with a high to low transition.
The falling edge shifts data bits into the CRC
generator/checker. It also transfers the CRC check
word to DOUT in the write mode (DOCE = LOW). The
rising edge also activates the CRCOK lines in the read
mode when no error is found.

2

DOCK

DATAORCRC
WORD CLOCK

3

SHFCLK

SHIFT CLOCK

6

N.C.
CWE

NO CONNECTION
CHECK WORD
ENABLE

7

DOCE

DATAORCRC
ENABLE

a

CRCIZ

CYCLIC
REDUNDANCY
CHECK INITIALIZE

9
10
11

N.C.
Vss
DOUT

NO CONNECTION
GROUND
DATA OUTPUT

12

SKPCLK

SKIP CLOCK

13

CRCOK

CYCLIC
REDUNDANCY
CHECK OKAY

14

WCLK

WRITE CLOCK

This input clock is divided by 16 to produce TIMCLK
(pin 15) and has no effect on the rest of the internal
circuitry.

15
16

TIMCLK

TIMING CLOCK
CYCLIC
REDUNDANCY
CHECK OKAY

See above.
Complementary output version of CRCOK (pin 13).

4,5

17-19
20

CRCOK

This active low output indicates that the CRC
checkword is being output on the DOUT line. When
CWE is high, data is being output on DOUT.
Initially, this input line is held high to direct input data
(pin 1) to the output data (pin 11). After the next to the
last BYTE is transmitted but before the last BYTE
occurs DOCE must be low to direct the 2 CRC check
bytes to DOUT (pin 11).
DOCE must be maintained low for a minimum of 2 byte
times. DOCE is used only in the write mode.
When this line is at a logic 0, the SKPCLK output line is
held high and the CRC generator is held preset to hex
"FFFF."
NO CONNECTION
GROUND.
In the write mode, this line outputs the unmodified data
stream along with the 2 byte CRC word appended to
the end of the stream.
The first high-to-Iow transition on DIN (pin 1) resets
SKPCLK low and enables the CRC to either generate
or check the CRC word.
In the read mode, after the 2 byte CRC word is entered
on DIN and no error has been detected, this line is set
high to indicate no errors have occurred. This line will
then remain high as long as DIN is maintained high.

N.C.

NO CONNECTION

Vee

Vee

+ 5V power supply input.

OPERATION
Prior to shifting data thru the device (either in the read or
write modes) the CRC generator/checker is initialized by
strobing the CRCIZ (pin 8) low. This forces the SKPCLK (pin
illiine to the high state. The first low going transition on
DIN (pin 1), namely the most significant bit of an address
mark, resets the SKPCLK line. The HDC 110-04 has now
been properly initialized and is ready to generate/check the
CRC bytes. The CRCOK and CRCOK lines should be set
to their inactive states.
In the write mode, initially the DOCE (pin 7) is held high and
a pseudo DOCK is produced by supplying a string of zeros
before the address mark. This ensures the proper state of
the internal D flip flip to gate input data to the output line
DOUT (pin 11). As shown in the block diagram the CWE

(pin 6) will be set high. Sometime between the next to the
last and the last DOCK that indicates the end of the data
stream, DOCE (pin 7) is lowered to ensure the smooth transition of the 2 byte CRC checkword to the output line DOUT
(pin 11).
DOCE must be maintained low for a minimum of 2 byte
times. After the CRC word is generated, DOUTwill produce
a string of zeros (i.e., held high). This portion of the circuitry
is dormant in the read mode.
After proper initialization, input data is entered on DIN (pin
1) along with the 2 byte CRC word for the read mode of
operation. At the end of the data stream, if no errors were
detected the CRCOK (pin 13) is set high. Accordingly the

586

complementary output (pin 16) is set low. These output
states will be maintained as long as DIN is held high and
CRCIZ (pin 8) is not strobed. If the CRCOK lines do not
become active, an error has been detected and a re-try
is in order. If successive re-tries fail, an error flag may be

set to determine a further course of action as desired by
the user.
WCLK is divided by 16 to produce TIMCLK which may be
used as a buffered step clock for SA1000 compatible drives.

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range ................................................................................. O°C to + 50°C
Storage Temperature Range ................................................................................ - 55° to + 150°C
Lead Temperature (soldering, 10 sec.) ............................................................................... +300°C
Positi~e Voltage on any 110 Pin, wit~ respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .....
. ... '.' ............... + 7.0V
Negative Voltage on any 110 Pin, with respect to ground ................................... .-/l!!tt~
0.2V

.............. 'St:::::~::!at~:~~ 'Ii'~t~~ ~~; ~~.~~~ '~~;~~~~~t'~~~~~~ ~~.;~~ .~~~;~~ .. ;~i~' i~ ~'~;r~'~~ ~~;i: _·l>o~~~//I,f~ .......~. ~f~~:t
device at these or at any other condition above those indicated in the operational sections of this sl'''_

~."';':::Iaoa",/i.;',oPec;,.
' - '.......~
. .....
it

. OUb/ecI

{call"".

DC ELECTRICAL CHARACTERISTICS: T. = O°C to 50°C; Vee = +5V ± 10%, Vss = OV
SYMBOL
V"
V,H
VOL
VOH
Vee
Icc

PARAMETER
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Supply Voltage
Supply Current

MIN
-0.2
2.4

MAX
0.8

TYP'

0.4
2.4
4.5

5.0

5.5
100

UNIT
V
V
V
V
V
mA

o~"iJe,

10L = 3.2mA
10H = -2OOI1A
All Out uts Open

AC ELECTRICAL CHARACTERISTICS: T. = O°C to 50°C; Vee = + 5V ± 10%. Vss = OV
SYMBOL
twr
tWR
tzs
tZK
tBS
tBH
too

SYMBOL
toK
tow
tiC
tae
tse
tSR
tse
tiN

PARAMETER

MIN

MAX
95
85
120

90
20

UNIT
nsec
nsec
nsec
nsec
nsec

40

nsec

TYP'

1 WCLK to 1 TIMCLK
i WCLK to lTIMCLK
1 CRCIZ to 1 SKPCLK
CRCIZ pulse width
DOCE set up time w.r.t.
1 DOCK
DOCE hold time w.r.t.
1 DOCK
DIN to DOUT delay

PARAMETER
miN to 1 SKPCLK
DIN P.w. to reset SKPCLK
1 DOCK to 1 CWE
1 DOCK to 1 CWE
SHFCLK frequency
i SHFCLK to 1 CRCOK
1 SHFCLK to 1 CRCOK
1 DOCK to 1 DIN

MIN

TYP'

105

nsec

MAX
120

UNIT
nsec
nsec
nsec
nsec
MHZ
nsec
nsec
nsec

50
120
120
5.25
85
90
90

Notes: 1. Typical values are forT. = 25°C and Vee = +5.0V

-C R C
1--1
IZ-o--I t-- tzs

SKPCLK~
_

tOK

DIN~

Initialize

587

CONDITION

CWE set high

CONDITION

too ~ "'--

~:.-

tiN

r----------------,~

----~:r----;~
I

,

I I

1

n '" last data byte

.., ...- - - - - tBH------..,t:··--tBS~ :
I Remains low~bvt;-rn;S

DaCE

_____

t

~_n-t--I------------

,:1-----------CRCbytes

__________
• 1....-.-

____---

wrllemode

tSR~I~

',,

:r

CRCOK

tsc ---..:

~

CRCOK ------------------------------------~!LI__________ _
I

1--

Write Mode

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

588

HDCi100-05
PRELIMINARY

Hard Disk Parallel to Serial Converter
FEATURES

PIN CONFIGURATION

o Single + 5 Volt Power Supply
o Double Buffered
o Byte Strobe Outputs
o 5 Mbit Data Rate
o Paralielln/Serial Out
020 Pin DIP
On-Channel COPLAMOS® Silicon Gate Technology

00 1

20 Vee

01

2

19 EN

02 3

18 NC

03 4

17 TEST

04 5

16 BOONE

05

1500UT

6

06 7

14 SHFCLK

07 8

13 LO

SHFCLK 9

12 WCLK

Vss 10

11 OCLK

GENERAL DESCRIPTION
The HDC 1100-05 converts bytes of parallel data to a serial
data stream for writing to disk memories or other serial
devices. Parallel data is entered via the DO-D7Iines. A synchronous byte counter is used to signify that 8 bits of data

8
DO-D7

D

/

8BIT
LATCH

C

a

/

~

~

have been shifted out and that the 8 bit latch is ready to be
reloaded. The double buffering of the data permits another
byte to be loaded while the previous byte is in the process
of being shifted.

8
I

8 BIT SHIFT
REG
C

I

L

+5

+LVD

D
_
BYTE
C COUNTER Q

a--p.- DOUT

D

I

r- SHFCLK

A

p--- SHFCLK

R

a

C

LD

EN

Y

T

~ BDONE
LD

589

I

DESCRIPTION OF PIN FUNCTIONS
PIN NUMBER
1-8
9

SYMBOL
DO-D7
SHFCLK

NAME
DATA O-DATA 7
SHIFT CLOCK

10
11

Vss

DCLK

GROUND
DATA CLOCK

12

WCLK

WRITE CLOCK

13

LD

LOAD

14

SHFCLK

SHIFT CLOCK

15
16

DOUT
BDONE

DATA OUT
BYTE DONE

17
18
19

TEST
NC
EN

TEST INPUT
No Connection
ENABLE

20

Vee

Vee

FUNCTION
8 bit parallel data inputs (bit 7 = MSB).
Inverted copy of WCLK (pin 12) which is active when
ENABLE (pin 19) is at a logic O.
GROUND.
Active low input signal resets the BDONE (pin 16)
latch. The low-to-high (trailing edge) clocks the input
data into the internal 8 bit latch.
The high-to-Iow Wedge of this clock signal is used to
shift the data out serially. The low-to-high (j) edge is
used to update the internal byte counter (modulo 8).
This active low signal indicates that the' Byte Counter is
being preset to 1. Normally left open by the user.
Delayed copy of WCLK (pin 12) which is active when
EN (pin 19) is at a logic O.
Serial data output enabled by EN (pin 19).
This output signal is forced to a logic 1 whenever 8 bits
of data have been shifted out. BDONE remains in this
state unless reset by the loading of another byte of
data.
This pin must be left open by the user.
NO CONNECTION
This active low signal enables DOUT, SHFCLK,
SHFCLK, and BDONE outputs. When high, these
output signals are in a high impedance state.
+ 5 power supply input.

OPERATION
Prior to loading the HOC 1100-05, it is recommended that
OOH (or FF) be loaded into the input buffers to ensure that
OOUT is at a fixed level. EN (pin 19) is set to a logic 0 to
enable the device outputs.
Oata is entered on the 00-07 input lines and is strobed into
the data latches on the rising edge of OCLK (pin 11). OCLK
also resets BCONE (pin 16). The first BOONE that comes
up simply means that the HOC 1100-05 is ready to accept
another byte of data and that the previous byte entered is
in the process of being shifted out. If the BOONE is serviced
prior to every 8th WRITE CLOCK pulse the output data will
represent a contiguous block of the bytes entered. Oue to
the asynchronous nature of the HOC 1100-05, the input data
will be available in serial form at the output anywhere from
8 to 16 write clock cycles later.
Oata is shifted out on the high-to-Iow transition of the WCLK
(pin 12). The low-to-high transition of WCLK increments a
byte counter which in turn sets the BOONE signal high after
8 bits of data have been shifted out. The low-to-high tran-

sition of BOONE also causes the loading of the data buffer
into the shift register. The data buffer is now ready to be
reloaded with the next byte.
The loading of the next byte automatically clears the BOONE
signal. The entire process as outlined above is repeated.
BOONE always needs to be serviced within 8 WCLK cycles
unless the next byte to be transmitted is the same as the
previous byte.
Four signals, BOONE, OOUT, SHFCLK, and SHFCLK, can
be placed in a high imj:Jedance state of setting EN (pin 19)
to a logic 1. Likewise, EN must be at a logic 0 in order for
these signals to drive any external device.
The TEST pin is internally OR'd with the counter output to
produce the LO (pin 13) signal. This is used to inhibit the bit
counter by external means for test purposes. It is recommended that TEST be left open by the user. An internal
pullup register is tied to this pin to satisfy the appropriate
logic level required for proper device operation.

590

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range ................................................................................. O°C to + 50°C
StorageTemperatureRange ................................................................................ -55°to + 150°C
Lead Temperature (soldering, 10 sec.) ............................................................................... + 300°C
Positive Voltage on any 1/0 Pin, with respectto ground ................ , ..... .. . . .. ...... ..... . ... . .................... + 7.0V
0.2V
Negative Voltage on any 1/0 Pin, with respectto ground .................................. .•

J:;IlI!. ................... -

'St::::~ ~:;!at~:~ 'Ii'~t~'~ ~~; ~~.~~~ .~~;~~~~.~; ~~~~.~~ ~~. ;~~ .~~~;~~~ ;~i~' i'~ ~'~;r~~~ ;~;i:_~;,7t~(l
DC ELECTRICAL CHARACTERISTICS: TA = O°C to 50°C; Vee =
SYMBOL
VIL
VOH
VOL
VOH
Vee
Icc

PARAMETER
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Supply Voltage
Supply Current

SYMBOL
twe
tow
tos
tOH
tOB
too
tSH
t HS
tWB
t ES
IeL

,
--.:

TYP'

MAX
0.8

5.0

5.5
100

UNIT
V
V
V
V
V
mA

0.4

NOTES: 1. Typical Values are for TA = 25°C and Vee =

"1

11""tSQ!~'

+ 5V

MIN

10L = 3.2mA
10H =-2OOfLA
All Outputs Open

± 10%, Vss = OV

TYP'

UNIT

MAX
5.25

130
130
75
70
180
25

MHZ
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec

50

nsec

50
30
30

75

CONDITllJ ..

CONDITION

EN
EN
EN
EN

= 0
= 0
= 0
= 0

+ 5.0V

I
l'4-IWC

4:

5!

6
I

'

I

I

------~LJ--.-'~--~'--------~LJr--~--~--------~
I I

I

BONE

)€3(

, ,

'eL
'ES

.:~~----7,--------,~

~

I

I

:1

' 1...__........___--'
.......'

---1'-

r:-,'
.r---------+-----,U
l..!..-.J

'ws

:

I

I:

-..; ;..-bO

,

'I ,I

: I

SHFELK

~

I

Y -; [ "
~----I I

----;:~

DOUT

I

tOH

.--_-='o:.:,s=---'::;
...........
..-{4D7-DO

INVALID DATA

DO

,, ,'

L-_--L-l

591

D7

D6

D5

I

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applica~
tions: consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked 'and is believed to be entirely relIable. However, no responsibility is
assumed for inaccuracies. Furthermore. such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve deSIgn and supply the best product possible.

592

HDC7261D
PRELIMINARY

Hard Disk Controller
FEATURES

PIN CONFIGURATION

o Flexible interface to various types of Hard Disk Drives
o Programmable Track Format
o Controls up to B Drives
o Parallel Seek Operation Capability
o Multi-sector and Multi-track Transfer Capability
o Data Scan and Data Verify Capability
o High Level Commands, Including:

o
o
o
o
o
o
o
o

READ DATA
SEEK (Normal or Buffered)
READ ID
RECALIBRATE (Normal or Buffered)
WRITE DATA READ DIAGNOSTIC (SMD Only)
SPECIFY
WRITE ID
SCAN DATA
SENSE INTERRUPT STATUS
VERIFY DATA SENSE DRIVE STATUS
DETECT ERROR
VERIFY ID
CHECK
NRZ, FM, or MFM Data Format
Maximum Data Transfer Rate: 12MHz
Error Detection and Correction Capability
Simple 110 Structure: Compatible with Most
Microprocessors
All Inputs and Outputs except Clock Pins are TTLCompatible (Clock Pins Require Pull-up)
Single + 5V Power Supply
40-Pin Dual-in-line Package
COPLAMOS® n-Channel Silicon Gate Technology

SYNC
RWOATA
RWClK
RESET
INT
OREQ

1
2
3
4

'fC
CS

7
8
9
10
11
12
13
14
15
16
17
18
19
20

RO
WR
AO
DO
01
02
03
04
05
06
07
GNO

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

Vee
BT1
BTO
ClK
INDEX
SCT
USTG
SSTG
BOIR
TG3
TG2
TG1
BT2
BT3
BT4
BT5
BT6
BT7
BT8
BT9

(RGATE)
(WGATE)

(PCl)
(PCE)
(OSO)
(SKC)
(TRKO)
(READY)
(WFlT)
(OSO)
(OS1)
(HSO)
(HS1)
(HS2)
(RWC)
(SITP)
(OIR)

PACKAGE: 40-pin D.i.P.

Note: Signals shownin parentheses are used when the HDC7261
is in the floppy~ like mode.

GENERAL DESCRIPTION
The HDC7261 Hard Disk Controller is an intelligent microprocessor peripheral designed to control a number of different types of disk drives. It is capable of supporting either
hard-sector or soft-sector disks and provides all control signals that interface the controller with either SMD disk interfaces or Seagate floppy-like drives. Its sophisticated
instruction set minimizes the software overhead forthe host
microprocessor. By using the DMA controller, the microprocessor needs only to load a few command bytes into the
HDC7261 and all the data transfers associated with read,

write, or format operations are done by the HDC7261 and
the DMA controller. Extensive error reporting, verify commands, ECC, and CRC data error checking assure reliable
controller operation. The HDC7261 provides internal
address mark detection, ID verification, and CRC or ECC
checking and verification. An eight-byte FIFO is used for
loading command parameters and obtaining command
results. This makes the structuring of software drivers a
simple task. The FIFO is also used for buffering data during
DMA read/write operations.

593

I

594

HDC9223
PRELIMINARY

High Performance
Analog Data Separator Support Circuit
(ADSSC)
For Hard Disk

FEATURES

PIN CONFIGURATION

o Significantly reduces component count in hard
disk systems

o Completely compatible with the HOC 9226 Hard

Disk Data Separator and the HOC 9224 Universal
Disk Controller

o Simplifies design and improves performance of ST506
Hard Disk Controller sUb-system

o Eliminates costly critical "tune up" adjustments
o Space saving 14 pin package
o Monolithic analog solution reduces critical pc
board layout

o Single + 12V power supply
o Printed Circuit Board Artwork available to facilitate
prototyping and evaluation

GENERAL DESCRIPTION
The HOC 9223 Analog Data Separator Support Circuit
(ADSSC) is a 14 pin device, which when used with the HOC
9224 Universal Disk Controller and the HOC 9226 Hard Disk
Data Separator significantly simplifies the design of a high
performance hard disk data separator.
The HOC 9223, combined with the HOC 9226 and a few

resistors and capacitors, forms a phase locked loop which
performs phase and frequency locking onto either the MFM
or FM data stream output by ST506 or ST 412 type drives.
By reducing the number of critical discrete components to
a minimum and eliminating all critical adjustments, the HOC
9223 and HOC 9226 simplify the task of the designer.

595
._.

_ _ ._-_.. _ - - - - - - - - - - -

r-------

+12V

-------------1
I

I

I

f.

9

r-------'-(

I

I C2
1.22 fL f

I

I

IIAGNDT
10

4~

l-b

fL
.22
MLC

I

AGND

PMPUP
PMPDWN

4xVCO

I

I

_---1

FIGURE 1: HOC 9223 BLOCK DIAGRAM
DESCRIPTION OF PIN FUNCTIONS
PINNa.
1

NAME

SYMBOL

Read Gate

RDGATE

This active high input controls the gain of the loop. A high level
decreases the gain and a low level increases the gain.

DESCRIPTION

This active low input causes the VCO to increase its frequency.

2

Pump Up

PMPUP

3

Pump Down

PMPDWN

4

Digital Ground

GND

5

Four Times VCO

4xVCO

6

External Capacitor
Connection 1

CX1

7

External Capacitor
Connection 2

CX2

8

External
Resistor Connect

R1

A 3.01K 1% resistor is connected from this pin to Analog Ground.

9

External Filter
Cap Connection 1

C1

A .22fJ.f MLC capacitor is connected from this pin to Analog Ground.

10

External Filter
Cap Connection 2

C2

A .22fJ.f MLC capacitor is connected from this pin to Analog Ground.

11

Analog Ground

AGND

12

External Filter
Connection 1

F1

A filter network should be connected to this pin as shown in Figure 4.

13

External Filter
Connection 1

F2

A filter network should be connected to this pin as shown in Figure 4.

12V

Connect the power supply to this pin. A .22fJ.f bypass capaCitor should
also be connected from this pin to Analog Ground.

14

+ 12 Volts

This active low input causes the VCO to decrease its frequency.
This is the ground connection for the digital circuitry within the
HDC9223.
This is the VCO output. It will vary from 18 to 22 MHz as a function of
the PMPUP and PMPDWN input signals.

An 8.2 pf external NPO capaCitor is connected across pins 6 and 7.

This is the ground connection for the analog circuitry within the
HDC9223.

596

DESCRIPTION OF OPERATION
The functional block diagram of the HOC 9223 is shown in
Figure 1. The major functional blocks within the HOC 9223
are a voltage controlled oscillator (VCO), an active loop filter, and a pulse amplifier. The gain of the pulse amplifier is
controlled by the RDGATE logic input.
The voltage controlled ocsillator generates the 4xVCO output (nominally 20 MHz). The frequency of this output is
determined by the signals on the PMPUP and PMPDWN
inputs to the HOC 9223. Since the half bit time for data from

the disk is 100ns, the HDC 9226 divides the frequency of
the 4xVCO signal in half, and compares the phase and frequency of the resulting 10 MHz signal to that of the incoming data. The HOC 9226 then varies the pulse width on the
PMPUP and PMPDWN lines to adjustthe outputfrequency
of the VCO on the HOC 9223, closing the loop.
A voltage regulator and bandgap voltage reference ensure
power supply rejection and stable VCO operation.

MAXIMUM GUARANTEED RATINGS
Operating Temperature Range .................................................................................. 0 to 70 C
Storage Temperature Range ............................................................................ - 55 to + 150 C
Lead Temperature (soldering, 10 sec) ........................................................................... + 300 C
Positive Voltage on any Pin, with respect to Ground ......................................................... Vcc +0.5V
Negative Voltage on any Pin, with respect to Ground ........................... " .............................. " - 0.5V
Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or
any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies. it is important that the "Maximum Guaranteed Ratings" not be exceeded.
or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when AC power is switched off. In addition. voltage
transients on the AC power line may appear on the DC output. If this possibly exists it is suggested that a clamp circuit be used.

DC ELECTRICAL SPECIFICATIONS
(TA = OCt070C, Vee = 12.0V ± 5%)
SUPPLY CURRENT
Icc
SUPPLY VOLTAGE
V

50
11.4

INPUT VOLTAGE
V'L
V'H
OUTPUT VOLTAGE
VOL
VOH
INPUT CURRENT
I'L

mA

12.6

V

12V±5%

2.4

V
V

10L = 2.0mA

1.2

V
V

3.6

4.1
-10
40

AC ELECTRICAL CHARACTERISTICS
(TA = OC to 70C, Vee = 12.0V ± 5%)
PMPUP, PMPDWN pulse width
PMPUP, PMPOWN rise time
PM PUP, PMPDWN fall time

ns
22

MHz

4xVCO rise time

15

ns

4xVCO fall time

15

ns

Output Frequency
(when locked)

4xVCO pulse width high
4xVCO Ise width low

18

ns
ns

16
16
597

Measured at 50% amplitude (Fig. 2)
Measured between 0.6 and 1.8V
Measured between 0.6 and 1.8V

Measured between 1.5 and 3.0V;
Cload = 10pf (Fig. 3)
Measured between 1.5 and 3.0V;
Cload = 10pf (Fig. 3)
. 3 Measured at 2.5V
. 3 Measured at 2.5V

FIGURE 3: 4xVCO TIMING

FIGURE 2:
=PM=P=-U=P/PMPDWN TIMING

FIGURE 4: TYPICAL CIRCUIT CONFIGURATION

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications:
consequently complete information sufficient for construction purposes is not necessarily given. The Information
has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described
any license under the patent rights of SMC or bthers. SMC reserves the right to make changes at any time in order
to Improve design and supply the best product possible.

598

HDC9224

Universal Disk Controller
FEATURES

PIN CONFIGURATION

Programmable Disk Drive Interface
and Formats
Seagate (ST506) or user definable
Hard Disk Formats
I~a:~~
IBM Compatible Single or Double
((l.
32K x8

WE

WE

DE

DE

STATIC RAM

Fftc k:h-L-CS
ADDR

I'P

ADOR

r

OB7-0

<

HOC
9225
A014-0

~

SEN

LS244

087-0

"V

G>

LS245

~

Vt"

DIA

t--

CD

EN OIR

ENfA

CS

BUS OIR

l

~CD

~

DIP

LSOB

OE

~
v

G>
~

/-

?-

y-

?-

~
~
~

LS245

P~

y...

AW
SYSR

W

WAIT
WAIT

DMACLK

r--£L-

C

RESET

58
SYSDS

IJP elK

ECCTM

-"

IlelKIN

/

INTACK

HDCDS

SECTOR INTERRUPT ACK
SECTOR INTERRUPT
INT

svs
(

RESET

HDC INTERRUPT

616

HDCRW

I

-

AB?
AB6
AB5
AB4
AB3

I
I

I

I AB?

lS
244

lOX

SEEK COMPLETE

~

AB1
ABO

I-

TRKOQ

WRITE PROTECT

WR PROT

READY

OIR
STEP

WRITE FAULT

'll'

AB3
I AB2
I AB1

I ABO

INDEX
TRACK 000

AB2

I ABe
I AB5
I AB4

DRIVE STATUS

-

r--

AB7

-~

=
OUTPUT 1

0
0

ORSEll

Q

LS374

AB3
AB2
AB1
ABO

Q

0

Q

,r

r - - MO
GNO

-~
QB.!:{E

ORSEL 1

DRSELO

0
0
0
0

r - - RDATA

LSQ4

0

AB6
AB5
AB4

WG
WQATA

MOlQRON

Q

SINGLE DENSITY

lOX
SEEK COMP

AB?
AB6
AB5

AB2
AB1
ABO

I

Cs
CD

Vcc

Lt

STs f - GNO

ti

-

EC
EB
EA

C
B
S1
sof---- A
WGATE

DB?
I

I

WDATA

02
01
00

Q

0

0

0

Q

STEP

HEAD 81T3
HEAD BIT 2

Q

0
0

Q

0

Q

,-

I

HEAD 2

r

K

+MFM

WRITE DATA
MFM
A

LATE

,L

RDGATE

I-lA9637

HOC 9226

~I--

RST

HO DATA

I--w

2C2 -----<

Ri5ATA

2Y 2Cl

RCLK

1Y

Os
RW

- I-- RDATA

~

~1OMH'
XTAL

XTAL 2

RClK

I--

1C11--'
lCO
A B
DRSEL1

SEPARATOR
XTAL 1

RAW
RD

I ~ROATA

I

RCLK

-=-

FDC9216

I
8MHzCLK

617

I

V

READ DATA

MFM

r
-

WDOUT
DMACLK

+MFM

100i1I-

1

EARLY

ACK

I~T

I

flA9638

ClK

ECCTM

QBDLE

~L-

OB2
OB1
DBa

WG
GND
HARD DISK

5T83

1C3r--

I
i

HEAD 2

5T82
ST81
STBO

I

I

HEAD 2

-=

OB3

DMAR

I

STEP
HEAD 2

""

OB6
OB5

!

I

LOWCUR
OIR

l..!'
r-... LY
I/"f'lr-... V
LY ?406

HEAD BIT 1

HEAD BIT 0

I OB4
I

DRSEL 1

J'),.

V r-....
I'>. I/'
V I'>.:
LY

OIR

0

L-T

0710
0610
0510

lS13804P
03

READY

RED WR CUR

LS374

AB3

5V

WR FLT
OUTPUT 2

0
0
0

AB4
DIP

TRKQOO

-=-

-

HDC 9224

CO~
C01

GND
HARD DISK
DRIVE

TAPE SPEED:

The UDC will issue a normal interrupt (with the command termination code set to 0-0) when the RAMP UP
or RAMP DOWN timer has expired.
4. BACK-UP WRITE. The user will first request the UDC
to perform a disk READ TRACK command, with the
TRANSFER ENABLE bit in the command word reset.
This will cause the UDC to transfer only the ID field
information to memory.
The TAPE BACKUP command will then be issued
causing the UDC to write this ID information to the tape
as a tape mark (typically 96 bytes for a drive formatted
with a 3 byte/sector ID field or 128 bytes for a drive formatted with a four byte/sector ID field. The data fields
should then be transferred to the tape in a similar
manner.
The UDC may be used with either "Streaming" or "Start/
Stop" type tape drives. This is illustrated by the following examples:
A. START/STOP TAPE DRIVE:
typically transfers % or 1 disk track at a time as illustrated by the following flow chart:

STOPPED

/

IL

DRIVE SEL
1. tape motion on
2. write enable on
(write) or off
(read)

L

DRIVESEL
1. tape motion off
2. write enable off
(write or read)

WRITE BLOCK FROM MEMORY TO TAPE
STOP TAPE DRIVE

Control of a streaming tape drive is similar to thClt of a
start/stop drive. The tape is started at the beginning
of the data transfer and stopped after the last block is
written tothe tape. The tape is not stopped in between
blocks. The UDC will however turn the Write Gate signal on when it is writing data and off when it is not so
that gaps will be written (with external hardware) on
the tape between the data blocks.

STOP TAPE DRIVE
When controlling a start/stop tape drive, the UDC will
write the data "block by block". The system will issue
a Drive Select command to the UDC with the Tape
Motion, Motor On and Write Enable bits set to start
and write data to the tape.
The UDC will interrupt the system after the completion of the Ramp Up Delay indicating that the tape drive
is up to speed. This interrupt is distinguished by the
Command Termination Code of 0-0 (normal completion of command).
The System then outputs the Write command (for a
long or short block) and waits for the command termination interrupt. The UDC will write the Sync mark
and tape mark or data block on the tape.
When the System receives the interrupt indicating
completion of the Write command, it will issue another
drive select command with the Motor On and Write
Enable bits set to stop the drive. The UDC will interrupt the system after completion of the Ramp Down
Delay indicating that the tape has stopped moving.
The UDC will turn the Write Gate signal on when it is
writing data and off when it is not, without regard to
the tape motion. The Write Gate signal is used to generate "gaps" on the tape between the data blocks. This
is done by externally forcing the two Data outputs with
the Write Gate signal such that the Data + signal is
high and the Data - signal is low when the UDC is
not writing data to the tape (Write Gate is off):

5. BACK-UP READ. The data is read from the tape (in
either start/stop or streamer mode) and buffered in
memory. The disk track is then reconstructed from
the data.
The start/stop drive typically has a track (or half a track)
of disk data stored as a block. It is therefore expedient
to read in the data "block by block". When reading data
from a streamer drive use can be made of the SECTOR
COUNT register and a track's worth of data blocks may
be read from the tape before generating the track on
the disk.
Tape motion control is similar to that described above
except that the Write Enable Bit is off to inhibit writing to
the tape. The UDC reads the tape until it detects a sync
mark. After detecting a sync mark the UDC will transfer
the data found on the tape to memory.
6. The search count is used when reading the tape. It
specifies a maximum number of blocks of 128 bytes
between adjacent data blocks. If the search count
expires before sync is detected, the command is
terminated.
For example, if a search count of two is specified by
loading the Desired Sector register with FD (hex), the
UDC will search for 256 byte times before terminating
the command. This will prevent the UDC from accidentally skipping a block. The search count is typically about
the size of one block length. In the following figure, TM1
and TM2 are two tape marks and DB1, DB2, DB3 etc.
are their associated Data Blocks:

[ DRIVE STOPPED
GAP

8ACKUP
1. read or write
2. long or short block

READ DATA FROM DISK TO MEMORY

WRITE BLOCK FROM MEMORY TO TAPE

'TAPE MARK AND/OR DATA 8LOCK ,

STOPPED
RAMP DOWN DELAY

START TAPE DRIVE

START TAPE DRIVE

GAP

\
-

B. STREAMING TAPE DRIVE:
typically transfers 1 sector at a time as illustrated
by the following flow chart:

READ DATA FROM DISK TO MEMORY

[ DRIVE STOPPED

TAPE AT SPEED
RAMP UP DELAY

,'--_ __

WRITE GATE:

LJ

TM1

D81

D82

D83

D84

TM2

D81

f-----1

f-----1

f-----1

f-----1

f-----1

f-----1

f-----1

search count

618

ing of bytes of 00 as per figure 2 of the UDC spec (this
is required to synchronize the data separator when
reading the tape). The Tape Mark and Data Block
(including CRC or ECC bytes) are followed by a "postamble" consisting of one byte of 00.
Note that the postamble is not included in the Floppy
Disk formats. The GAP sizes are dependent on the type
of drive (start/stop or streamer) and the specific
mechanical tape drive specifications.
10. Use can be made of the Sector Count register when
doing a "file" (versus a "mirror image") backup on a
start/stop tape drive. Instead of transferring the entire
disk track to the tape in one long block, the data is moved
file by file.
If, for example, it is desired to back up a file consisting
of five 256 byte long Hard Disk sectors, a 2048 byte long
Data Block would have to be used for an image backup
(the Data Block size is specified as 2 n * 128 restricting
blocks to 128, 256, 512 etc.). This would result in a lot
of wasted space on the tape.
If file backup is used and the Sector Count is set to five,
256· byte long Data Blocks can be used. Gaps will be
generated on the tape corresponding to the time
required to get thedata from the disk drive (corresponding to DMA delays and the disk interleave factor).
The tape will not be stopped until the entire file is transferred. When using sector count, the UDC internal programming will create inter-block gaps of about 30 to 32
bytes on the tape in both single (FM) and double (MFM)
density modes.

7. 16 BYTE DELAY. Provision is made to shift the RDGATE
pulse in the event that it coincides with the data block
sync mark. If a tape cannot be read (sync is never
detected) the tape can be re-read with the 16 byte delay
enabled.
DATA

GAP

DATA

GAP

RDGATE without delay:

L

miss sync mark detect

RDGATE with delay:

8. The DRIVE STATUS bits may be used by the tape drive
if they are enabled (on the drive) by DRIVE SELECT 3.
The ready change interrupt is especially handy for
detecting start of tape (SOT) and end of tape (EOT) as
a UDC command can be terminated by a change in state
of the READY input.
9. The DATA FORMAT is as follows:
PRE TMSYNC' TAPE MARK 'P'OST GAP' PRE DBSYNC DATA BLOCK POST GAP

The Tape Mark sync mark (TMSYNC) is composed of
three bytes of A1 (Hex) followed by one byte of FE (Hex).
The Data Block sync mark (DBSYNC) is composed of
three bytes of A 1 (Hex) followed by one byte of FB (Hex).
A1 (Hex) is encoded with the standard missing clock
pattern.
The sync mark is preceeded by a "preamble" consist-

SYSTEM CONFIGURATION NOTES
A simplified UDC schematic is shown in Schematic 1. The
following notes may be helpful in implementation olthe UDC.

interface circuits (including floppy disk data inputs and
outputs) may be 74LS series devices.

1. In systems using a private memory area, it is important
to know when the buffer needs servicing from the host
processor. A second interrupt signal (INT2) signals the
processor that servicing is needed. INT2 is generated by
externally ANDING the ECCTM signal with STB1 signal.
(The STB1 signal is active when the UDC.J§.putputing
the DMA address data, and occurs when STB is active
(low), SO is active (high) and S1 is inactive (low)).
This "interrupt" occurs only when the UDC needs the
system processor to either read from or write to the buffer
memory. When reading from the disk, the system processor should empty the memory buffer each time this
signal becomes active. (If an ECC error is detected, and
error correction is enabled, this signal will not become
active until the UDC has attempted to correct the error.)
When writing data to the disk, the system processor must
fill the buffer each time this signal becomes active.
2. The DIP (DMA in Progress) signal is used to isolate the
buffer memory from the main system memory. If 74LS244
and 74LS245 address buffers are used in the memory
addressing circuits, then this signal should be used to
enable or disable the address buffers, as required. This
eliminates the possibility of memory contention problems.
3. Write precompensation (for floppy disks) is handled
internally by the UDC. For hard disks, the LATE and
EARLY signals are connected to a multiplexer which, in
turn is connected to a 24 ns delay line. The EARLY and
LATE signals will toggle in response to the data pattern
being written. This will allow the data being written to the
shifted ± 12 ns from the nominal 12 ns delay specified
by hard disk manufacturers.
4. The interface to the hard disk drive data inputs and outputs requires RS-422 data tranceivers. Other disk drive

5. Since the UDC uses its Aux Bus for multiple functions,
the system designer must be able to determine which
function is occuring on the Aux Bus at any given time.
The SO and S1 signals, when combined with STB signal
are decoded (using a 74LS138 or equivalent) to provide
STBO-3 signals.
These generated signals and their respective functions
are:
STBO
STB1
STB2
STB3

Drive Status Input Time Slot
External DMA Address Counters Time Slot
Output 1 Time Slot
Output 2 Time Slot

6. The clocks required by the UDC are not TTL-level compatible. Pullup resistors (typically 390 ohms) should be
used with Schottky drivers to insure that the clock signals
reach the proper Input (high) level, with acceptable rise
and fall times.
7. The UDC features a built-in DMA controller that requires
connection to external counters. These counters are
configured so that they are incremented after each byte
is transferred. (The UDC's internal DMA circuits transfer
the starting memory address for each read or write operation.) 74LS161 Counters are typically used in this area.
8. The DMACLK input should be tied to the master system
clock, through a bus buffer. It is important to remember
that three DMACLK periods are required for each DMA
transfer.
9. The system design may be simplified, and costs reduced,
by using the FDC 9216B Floppy Disk Data Separator, to
separate raw data from the floppy disk drive into RDATA
and RCLK.
619

-----_._-----------

ERROR CHECKING AND CORRECTION CIRCUIT (ECC)
OPERATING PRINCIPLES
The UDC will automatically detect and correct errors in the
data read from the disk. Error checking may be done using
industry standard CRC or ECC encoding. Error correction
may be done using either internal or external ECC encoding. This section will explain ECC operation, as implemented on the UDC.
The UDC contains two 16-bit registers used by the CRC/
ECC circuits. CRC logic uses only one of these registers,
while the logic for ECC uses both registers, implementing
a full 32-bit algorithm.
These registers may be preset to either one or zero, using
the CRC PRESET bit in the INTERRUPT/COMMAND
TERMINATION register. (This allows compatibility with
existing disk controllers and extemal ECC chips.) Both ECC
and CRC are calculated beginning with the sync mark of
the address (CRC) or data (ECC) field.
CRC/ECC GENERATION
The UDC uses the following industry standard polynomials
in computing the CRC and ECC check bytes:
CRC: X '6 + X'2 + x5 + 1
ECC: X32 + X23 + X21 + x" + X2 + 1
As the UDC writes data to the disk drive, it first passes this
data thru the CRC (and, if enabled, ECG) registers. After all
data has been written, the remaining two (CRC) or four
(ECC) bytes remaining in these registers are written to the
appropriate address or data field.
CRC/ECC CHECKING
When CRC or ECC checking is initiated, the internal CRC/
ECC registers are set to either zero or one, as required by
the CRC PRESET bit in the INTERRUPT/COMMAND
TERMINATION REGISTER. Data read from the disk is
simultaneously shifted thru the CRC/ECC registers, and
transferred to external memory.
After the CRC or ECC check bytes have been shifted thru
the CRC/ECC registers, the remainder in these registers
should be zero, else an error has occurred in the address
or data block.
If CRC or ECC (without correction) is enabled, automatic
retry (if enabled) orcommand termination will occur. If internal ECC with automatic correction is enabled, the correction algorithm will be executed. If the internal ECC algorithm
is unable to correct the error (in one attempt), then automatic retry (if enabled) or command termination will occur.
ECC CORRECTION
Error Correction consists of three distinct parts:
1. The CRC/ECC regIsters are normalized by shifting zeros
thru the register. This sets up a data block which is 42,987
bits long, which corresponds to the "natural message
length" of the generation polynomial. The actual number
of zeros shifted through the registers depends on the difference between the natural message length of the generator polynomial and the actual length of the data block

being checked. The longest data block that can be corrected (using the internal ECC algorithm) is 4K bytes.
2. The data input to the CRC/ECC registers is then disabled and the DMA counters are re-initialized to the
starting address for this data block. The contents of the
CRC/ECC registers are then "ring-shifted" until 21 consecutive zeros are detected. The remaining bits in the
CRC/ECC registers compose the error syndrome. As the
CRC/ECC registers are shifted, the UDC generates DS
signals, causing the external DMA counters to be incremented. When the 21 consecutive zeros are detected,
the DMA counters are pointing to the corrupt data.
If the error syndrome is not found within the data block
the error is judged to be uncorrectable and the correction
algorithm is terminated. (The data block is the length of
the data field in the sector and the 4 ECC bytes. A format
with a sector size of 256 bytes would have a data block
size of 260 bytes.)
3. When the error syndrome is detected, the UDC will enable its ECCTM output, read the next byte from memory,
exclusive-or it with the first byte of the three byte error
syndrome, disable the ECCTM output and write the corrected byte back to memory. The correction process is
then repeated for the next two bytes in memory.
When using internal ECC (with correction enabled), the
ECCTM output is used by the external DMA counters to
inhibit the counters from incrementing their addresses
when correcting the erroneous bytes. When using external ECC, the ECCTM output goes active (low) when the
UDC is requesting the ECC Check Bytes from the external ECC chip prior to writing them to the disk.
After a correction is completed, the UDC will then attempt
to read the next sector on the disk (if the SECTOR
COUNT register is still greater than zero). Anytime ECC
correction has been attempted, (even if unsuccessful),
the CORRECTION ATTEMPTED bit in the CHIP STATUS register will be set.
The maximum time required for one ECC Correction Cycle
(using the internal algorithm) is:
1) (Natural Message Length [Bits])+ 4 = ECC Cycle Time
8
(in Byte times)
2) Maximum ECC Time = ECC Cycle Time + 30 byte times
Since the internal algorithm has a natural message length
of 42,987 bits the ECC Cycle time is 5,377 byte times. Since
a period of about 30 byte times must be allowed for the readmodify-write operations, the Maximum ECC Time equals
5,407 byte times.
One byte time equals the amount of time required to read
one byte for the type of drive selected. For Hard Disks, this
is about 1 microsecond. This equates to approximately 1
revolution (maximum) for either 8" floppy disk (running in
double density) or 5.25" hard disk.
During the entire operation, the RDGATE signal is kept
active.

620

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range ............................................................................. 0 to + 70 C
Storaqe Temperature Range ....................................................................... - 55 C to + 150 C
Lead Temperature (soldering, 10 sec.) ........................................................................ + 325 C
Positive Voltage on any Pin, with respect to ground ......... , ..................... , ....... , ...................... + 8 V
Negative Voltage on any Pin, with respect to ground ...................................... , .................... - 0.3 V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this
specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches"
on their outputs when the AC power is switched off. In addition, voltage transients on the AC power line may appear
on the DC output. If this possibility exists it is suggested that a clamp circuit be used.

DC ELECTRICAL CHARACTERISTICS Ta = 0 C to

VOLl
VOHl

PARAMETER
Input Voltage
Low
High
High
Output Voltage
Low
High

VOL2
VOH2

Low
High

V'L
V ,H1
V,H2

VOL3
V OH3
IL
ILc

MIN

Low
High
Input Leakage Current

+ 70 C, Vcc = 5.0V

TYP

MAX

UNIT

0.8

V
V
V

2.0
4.2

004
204

V
V

004

V
V

±10
-600

uA
f,LA

25

pf

200

ma

204

(Clock)
Input Capacitance

C'N

V
V

0.5
2.7

"IISlIIlll11l\'
So"uJ:ptu,:lhts/$'
No liee ·

± 5%

~.Iinal
.~~.~
1are

COMMENTS

,

ft

'"

:

~1J~:d:f''Cd~!~~",,:

' t!?Ch~~9~

all inputs except CLK and DMACLK
CLK and DMACLK input
all outputs except WDATA,
Early and Late. (Drive 1
TTL load into 50 pf)
WDATA, EARLY and LATE
outputs. (Will drive 1
Schottky load into 15 pf.)
DMARand INT
DMARand INT
OAVto 3.5V

lOll

=

1.6 mA

IOHl

=

40f,LA

IOL2

=

2mA

IOH2
IOL3
IOH3

= 50f,LA
= 004 mA
= 20f,LA

I

OV

Power Supply Current
Icc

AC ELECTRICAL CHARACTERISTICS Ta = 0 C to
PARAMETER

+ 70 C, Vcc =

SYMBOL

MIN

5.0V ± 5%
TYP

MAX

UNIT

COMMENTS

PROCESSOR WRITE CYCLE
C/Q, R/Y'l, CS Setup time to DSl
CID, R/W, CS Hold time to DSj
DS Pulse Width
DS Pulse High Time
_
Data Bus In Setup time to DS!
Data Bus In Hold time to DSj

TosB
TosB
TosL
TosH
TOIB
TolA

110
0
150
850
100
0

ns
ns
ns
ns
ns
ns

FIGURE3

PROCESSOR READ CYCLE
Data Access time from DSl
Data Hold time from DS!

TooB
TooA

75
10

ns
ns

FIGURE3

UDC TO MEMORY TIMING
(BUS MASTER)
(based on 10 Mhz DMACLK Input)
Write Setup time to DSl
Write Data Strobe Width
Write Hold time from DSj
Data Strobe Falling Edge
Data Strobe Rising Ed9L
Write Data Valid before DSL
Write Data Hold time after DS!
Memory Access Time

TWB
Twos
TWA
TosF
TosR
TwoB
TWoA
Tw

110
180
110

ns
ns
ns
ns
ns
ns
ns
ns

FIGURE4

15
20
90
10
200
621

PARAMETER

SYMBOL

Read Setup time to D~
Read Hold time after D
Read Data Strobe Pulse idth
Read Data Setup time to D i
Read Data Hold time from D i
DMACLKf to DS !
DMACLK to DS,

tv

MIN

TYP

MAX

UNIT

FIGURE4

100
100

ns
ns
ns
ns
ns
ns
ns

FIGURE 7

100

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

FIGURE2

FIGURE9

COMMENTS

TAB
TAA
T ADS
TADB
TADA
TDDD
TDDA

110
110
180
50
0

SO, S1, AND STB TIMING
STB Width
SO, S1 Hold time after STBi
Data In Setup time to
Data In Hold time after ST i
SO, S1 Setup time to S~
Aux Bus Setup time to S~
Aux Bus Hold time after ST i

Tsw
TSD
T D1S
TDIH
TSST1
TSST2
T SST3

800
100
700
0
100
100

INPUT CLOCK TIMING (10 MHz Input)
Clock Rise Time
Clock Fall Time
Clock Cycle High Time
Clock Cycle Low Time
Clock Cycle Time

TAT
TAF
TCH
TCl
Tcyc

40
40
95

TpB

0

ns

TpB

50

ns

FLOPPY INPUT DATA TIMING
Window Setup time to RDCLK
Window Hold time from RDDATA i

TFAB
TFAA

50
50

ns
ns

FIGURE 10

HARD DISK INPUT DATA TIMING
Data Setup time to RDCLKl
Data Hold time after RDCLK!
Clock Setup time to RDCLKf
Clock Hold time from RCLK

THAB
THAA
T HCB
T HCA

60
10
60
10

ns
ns
ns
ns

FIGURE 10

ECCTIM TIMING
ECCTM Setup to D~
ECCTM Hold after D i

T EDS
TEDH

50
100

ns

1

fLs

sm

PRECOMPENSATION TIMING
Early, Late Setup time
(Before WDATAj)
Early, Late Hold Time
(after WDATA1)

10
10

RESET TIMING
RST Pulse Width

622

100

105

FIGURE 10

ABO-7

•

DISK DRIVE
STATUS

••
•

OUTPUT 1
'REQUIRED
FOR STANDARD
UDC!HARD DISK
INTERFACE

o

D

Q i---=~=-=:":"""*--+- DRSEL3

III

TAPE DRIVE
STATUS

o
III

LS374

OUTPUT 2
D
Q

} TAPE MOTION CTL

DRSEL3

WRITE ENABLE
LS374

TRACK #

4

/\
STB2

I
I

STB3
STBO

WGATE
DATA +
WD
DATA LS74

-=-

SCHEMATIC 2: UDC/TAPE DRIVE INTERFACE CIRCUIT

623

l+SV
~

I+----Tcyc---~

390n

-----i~....----'----\./'"'

74S04

TO ClK INPUT
or DMAClK
INPUT

ClK

or
equivalent
RECOMMENDED ClK DRIVER CIRCUIT

FIGURE 1: RECOMMENDED CLK/DMACLK INPUT

FIGURE 2: INPUT CLOCK TIMING (10MHz)

\'-_ _......,1

CD

i=-r--~~--~~---~)(~------------------

os

T DOA

VALID
OUT

DB7-0

PROCESSOR WRITE CYCLE

PROCESSOR READ CYCLE

FIGURE 3: SYSTEM PROCESSOR TO UDC TIMING

1·---Tw----+l·1
...
Riiii

~+-_~fr-~T,,_ _
I'--~T-~~--------:--T----1wJ

--T,'---<"+,=i--+-r--

OB7-0
(WRITES)

OB7-0
(READS)

FIGURE 4: UDC TO MEMORY TIMING (BUS MASTER)

624

DMACLK

DMAR

"

ACK

"", ,

~--------------~----~------~\--------------~--~~{~:------~~

--?

:

,,

1

\

\

\

I

/

~

\

/
I

DIP

I
I

I

I
BYTE
READY

I

\
\

"

1,

R/W

TRISTATE \

I

\

>'>.l

TRISTATE

I

\

\
\

i5S

DB 7-0

TRISTATE

\

TRISTATE

----------------------~(~

r--

~

_____D_AT_A_O_U_T_____

MAX BYTE RATE 1.6"s

---j
UDC DMA MEMORY TIMING FOR HARD DISK
(BURST MODE)

FIGURE 5: UDC DMA MEMORY TllinlNG FOR HARD DISK (BURST MODE)

DMACLK

)
\)

I

DMAR

I

I
1

I
I

ACK

\

DS

DIP
DB7-0
(OUT)
DB7-0
(IN)

1

I

I

7

)

RIW

'-----,

__~TR~I~ST~A~T~E________~V~------~----

Y

n 000

I~
TRISTATE
TRISTATE

\

\

\ 0
~
----------------~(~------~--~
DATA OUT
)--,

--------'/.

1

I

(

~

DATA IN

)UDC DMA TIMING FOR
FLOPPY DISK (1 BYTE AT A TIME)

FIGURE 6: UDC DMA TIMING FOR FLOPPY DISK (1 BYTE AT A TIME)

625

I

81,80

8TS

AS 7-0

FIGURE 7: 50, 51, 5TB TIMING

BIT

I

7

I

6

I

5

I

4

I I I IoI
2

3

1

7

I

6

I

5

I

4

I

3

I

2

I

o

I

ClK

WDATA

Tn
0

I"

0

o

0

, ADDRESS MARK

MISSING CLOCK
0
1

1

-I"

0
DATA "FE"

FIGURE 8: UDC DATA WRITE TIMING

TWR

1\

WDATA

-----

\+- TpB

I-- T pA -

r-

/K

l ...

EARLY,

LATE

T

DRIVE TYPE

T(typ)
200NS

Tw< (typ)
100NS

8" FM FLOPPY

21-'s
-

300 NS
300 NS

5'/4' MFM FLOPPY

41-'s

300 NS

HARD DISK
8" MFM FLOPPY

5WFM FLOPPY

-

300 NS

FIGURE 9: PRECOMPEN5ATION TIMING

626

-I

DATA
BIT

I

I

0

0

I

I..

I

o

o

I

I

0

1

I

1

1

1

1

1

1

1

-I

ADDRESS MARK

I

1

1

1

I

o 1 o

1

I

I

MFM
READ DATA

READ CLOCK

RDATA

OS
INTERNAL
COMPARE

o
Al, 0A COMPARE

ECCTM

IL

TeoH

SYNC BYTE

RDCLK

HARD DISK INPUT DATA TIMING
(HARD DISK BIT=1)

FLOPPY INPUT DATA TIMING
(HARD DISK BIT = 0)

I

FIGURE 10

nIL...-_ _ _.!.-_
I - - - - - - - - - - R E p E A T E D N TIMES - - - - - - - - -..·-ll
rL
_ _ _ _ _ _ _ _-::::-_ _ _--,-_ _ _---'L...-_ _ _ _ _.....I

INDEX --1

I~t:,~ I ~~

H~t~~ I ~~ IFCTKI ~ I ~ I ~ I~ I ~ I?t:,~ I~~~gl ~! 1
~

INDEX AM

L

10 AM

128O"a byl"

ICRCII CRC2

~;~r I~:i.:F NOMINAL

I

OATA AM

-

FLOPPY DISK FORMAT; SINGLE DENSITY

ECCTM
2 bytes

INDE~L-____________L_~I~·_-_-_-_-_-_-~_-~_-~_-_-_-_-~_-_-_-_-~:_R_E_P_E_AT_E_D_N__TI_M_E_S======================:'~I______~nL
80x4E
12xOO 13 XC2 IFe I GAP
50x4EI I SYNC
12)(00 13xAI
0 1SYNC
I GAP

L\NDEXAM

II1
FE

I

22x4E21 SYNC
12xOQ 1 3xAI
~~ 1
I ci SIZE 1CRGI 1CRC2 1GAP
FB

TK SIDE SE

L1DAM

256 data byles

r..·------------

n

GAP 4
S9Sx4E

1

~ECCTM

LOATAAM

-i r-

FLOPPY DISK FORMAT; DOUBLE DENSITY

,,~
IND~

31
54x4E
ICRCIICRC21GAP

2 bytes

n

REPEATED N T I M E S - - - - - - - - - - - - - 1 .1

1L--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--.J1 L
GAP 1
16X4E

GAP4
340x4E

512 dala bytes

~ECCTM
HARD DISK FORMAT

FIGURE 11: DISK FORMATS

627

--i

r-

2 bytes

I

IL

INDEX

10

I

I I

G21 SYNC

DATA

G31 SYNC

:

110

I

I

AM AM FOUND

f

t

I101

G21 SYNC I

I

DATA

I

256byles

I

G31 SYNCIIDIG8jSYNCIDATAI G31G41

I

~16ByleSr__

I

AM FOUND

DATA IG31 SYNC

i--------,

RDG
3

LOOKING FOR'

I

58YTES~

I

ROGATE

G21 SYNC

AM NOT FOUND ,

AM FOUND

I

+

AM NOT FOUND

AM

I
t AM FOUND

FOUND~

(SINGLE DENSITY) ___ FE ----!I--FB -t-FE----ft-----------t-FB-----l-FE__+_ FB-I-FE ___
(DOUSLEDENSJTY) _ _ A1FE _ _ _II-_A1FB-t-A1FE _ _ _ _ _ _ _ _ _ _ _ _ _+-A1FB _ _ _- , I - A 1 F E - + A1FS+ A1FE _ __
(HARD DISK)

- - - A1FE---II--A1F8-+ AIFE

-------------+_

A1F8

- - - - j - A1FE

--t

A1F8

+

A1FE - - -

"8 bytes for Single denSlly
"'128 by\es for srngle.densrty

FIGURE 12A: RDGATE DURING DISK READ

INDEX

-D~

______________

~

__________________________

I

I

I

I

IGO SYNCIIN,PJxIGlISYNcl,DIG,1 SYNC IDATA IG3ISYNcl'DIG'ISYNcl DATAIG31 SYNC I 10 G'I SYNC I DATA G31 SYNC 1'0 G'I SYNC I DATA I G31
:
RDG3~ t....-L16 Bytes

RDGATE

------JillH

:

WRGATE

_______
W_RG_'.:.I....JI

II

--1--'1

n..F-'BY-'OO

......,}-- t
WDG,] I

AM FOUND

AM NOT FOUND

t

AM FOUND

~

I

AM FOUND

.----"'"'IL-

FIGURE 12B: RDGATE AND WRITE GATE TIMING

STANDARD FORMAT PARAMETERS
PARAMETER

HARD DISK

SINGLE DEN. FLOPPY

DOUBLE DEN. FLOPPY

GAP e;) *

a

40

80

GAP 1 *

16

26

50

GAP2*

3

11

22

GAP3*

18

27

54

SYNC SIZE *

13

6

12

SECTOR COUNT *

user selectable

user selectable

user selectable

SECT. SIZE MULT *

user selectable

user selectable

user selectable

RDG1

16

73

NA

RDG2

6

13

24

RDG3

25

27

24

WDG2

5

11

23

WDG3

3

11

3

*

=

PARAMETER USED BY FORMAT COMMAND

TABLE 1: STANDARD FORMAT PARAMETERS

628
~--~

--------

-

G4

~nL

I

-----_.,,----------------

REGISTER BIT DEFINITIONS
7

4
3
LOW ORDER BYTE OF DMA BUFFER
MEMORY STARTING ADDRESS

5

6

0

2

DMA 7-0
(REGISTER 0)

(MSB)

DMA 15-8
(REGISTER 1)

(MSB)

MIDDLE ORDER BYTE OF DMA BUFFER
MEMORY STARTING ADDRESS

(LSB)

DMA 23-16
(REGISTER 2)

(MSB)

HIGH ORDER BYTE OF DMA BUFFER
MEMORY STARTING ADDRESS

(LSB)

DESIRED SECTOR
(REGISTER 3)

(MSB)

DESIRED SECTOR NUMBER

(LSB)

DESIRED HEAD
(REGISTER 4)

HIGH ORDER BITS OF
DESIRED CYLINDER
(MSB)

(LSB)

DESIRED HEAD NUMBER
(MSB)

(LSB)

DESIRED CYLINDER
(REGISTER 5)

(MSB)

LOW ORDER BITS OF DESIRED CYLINDER

(LSB)

SECTOR COUNT
(REGISTER 6)

(MSB)

NUMBER OF SECTORS TO BE OPERATED ON BY COMMAND

(LSB)

RETRY COUNT
(REGISTER 7)
MODE
(REGISTER 8)

RETRY COUNT (1 'S COMPLEMENT)

CRCIECC

PROGRAMMABLE OUTPUTS

ENABLE

STEP

RATE

SELECT

INTERRUPTI
COMMAND TERM.
(REGISTER 9)

DATAIDELAY
(REGISTER A)
CURRENT HEAD
(READ REGISTER 4)

HEAD LOAD DELAY MULTIPLE IS LOADED INTO THIS REGISTER
DATA IS LOADED TO OR READ FROM THIS REGISTER
CURRENT HEAD NUMBER

HIGH ORDER BITS OF
CURRENT CYLINDER
(MSB)

CURRENT CYLINDER
(READ REGISTER 5)

LOW ORDER BITS OF CURRENT CYLINDER NUMBER

(LSB)

(LSB)

~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

CHIP STATUS
(READ REGISTER 8)

DRIVE STATUS
(READ REGISTER 9)

INTERRUPT
STATUS
(COMMAND READ)

(LSB)

COMMAND TERMINATION
CODE

TABLE 2: REGISTER BIT MAPS

629

UDC WRITE REGISTERS (APPLIES DURING TAPE BACKUP ONLY)
REGISTER

DB7

DMA 7-0
(REGISTER 0)

(MSB)

DB6

DB5

DB4

DMA BEGINNING ADDRESS BUTE (LOW ORDER BITS)

(LSB)

DMA 15-8
(REGISTER 1)

(MSB)

DMA BEGINNING ADDRESS BYTE (MIDDLE ORDER BITS)

(LSB)

DMA23-16
(REGISTER 2)

(MSB)

DMA BEGINNING ADDRESS BYTE (HIGH ORDER BITS)

DESIRED
SECTOR
(REGISTER 3)

(MSB)

MAXIMUM SEARCH COUNT (IN 1'S COMPLEMENT) (1)

DB3

DB2

DB1

DBO

(LSB)

(LSB)

DESIRED
HEAD
(REGISTER 4)
DESIRED
CYLINDER
(REGISTER 5)

SECTOR COUNT
(REGISTER 6)

ALWAYS
1

ECC TYPE

TAPE MARK BLOCK SIZE
(IN 2'S COMPLEMENT + 1)
(MODULO 256) (2)

OR

DATA BLOCK SIZE

DATA BLOCK COUNT
(IN 1'S COMPLEMENT)
(3)

RETRY COUNT
(REGISTER 7)

USER DEFINED OUTPUTS

MODE
(REGISTER 8)

INTERRUPTI
COMMAND
TERMINATOR
(REGISTER 9)

FLAG
WRITE
FAULT
NOTES: (1) The maximum search count is composed of:
130 byte inner loop (RDGATE high 128,2 byte times)
times the number programmed (maximum of 33,150 byte times
(2) Tape mark operation
(3) Data block operation

TABLE 3: TAPE BACKUP REGISTER BIT MAPS

630

UDC READ REGISTERS (APPLIES TAPE BACKUP ONLY)

REGISTER

DB7

DMA 7-0
(REGISTER 0)

(MSB)

DMA BEGINNING ADDRESS BYTE (LOW ORDER BITS)

(LSB)

DMA 15-8
(REGISTER 1)

(MSB)

DMA BEGINNING ADDRESS BYTE (MIDDLE ORDER BITS)

(LSB)

DMA 23-16
(REGISTER 2)

(MSB)

DMA BEGINNING ADDRESS BYTE (HIGH ORDER BITS)

(LSB)

DESIRED
SECTOR
(REGISTER 3)

(MSB)

MAXIMUM SEARCH COUNT (IN 1'S COMPLEMENT)

CURRENT
HEAD
(REGISTER 4)

X

X

X

X

X

X

X

X

CURRENT
CYLINDER
(REGISTER 5)

X

X

X

X

X

X

X

X

DB6

DB5

DB4

DB3

DB2

DB1

DBO

(LSB)

CHIP
STATUS
(REGISTER 8)

PRESENT
DRIVE
SELECTED

DRIVE
STATUS
(REGISTER 9)
DATA
(REGISTER A)

READ DATA

INTERRUPT
STATUS
(COMMAND READ)

COMMAND
TERMINATION
CODE (1)

NOTES: (1) Command termination bits set to:
11 for data transfer error
10 for sync error
00 for successful termination
X Don't care

TABLE 4: TAPE BACKUP REGISTER BIT MAPS

631

COMMAND BIT DEFINITIONS
7

5

6

4

3

2

RESET

Q)

DESELECT
DRIVES

RESTORE
DRIVE

Q)

STEP IN
1 CYLINDER

Q)

Q)

Q)

Q)

Q)

Q)

Q)

Q)

o

o

Q)

STEP OUT
1 CYLINDER

o

o

1 - BUffe. red
Seek
Normal
Seek

I

Q) ~

Q)

1 - Buffered
Seek
Normal
Seek

I

Q) ~

1~
o~

Buffered
Seek
Normal
Seek

I

POLL
DRIVES

SELECT
DRIVE

I

I

1 ~ Head Load
Delay Enabled
Q) ~ Delay
Disabled

o

TYPE OF DRIVE

I

DRIVE UNIT SELECTED

I

SET REGISTER
POINTER

SEEK/READ ID

READ SECTORS
PHYSICAL

0

0

Q)

READ
TRACK

0

0

0

READ SECTORS
LOGICAL

0

1

1

1

FORMAT
TRACK

1

Transfer

11 -

o~

1
Q)

En~

0

~

Q) ~

Bad Sector
Bypass
Bad
Sector
Terminate

PRECOMPENSATION
VALUE

WRITE SECTORS
PHYSICAL

PRECOMPENSATION
VALUE

WRITE SECTORS
LOGICAL
1

1 - Bad
Sector
Bypass
a ~ Bad
Sector
Terminate

1

Write
Deleted
Data

Write With
Reduced
Current

TAPE
BACKUP

TABLE 5: COMMAND WORD BIT MAPS

632

PRECOMPENSATION
VALUE

Transfer Alii
Transfer ID

Enable
Transfer

SECTOR SIZE FIELD BITS
DB2 DB1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

DBO
0
1
0
1
0
1
0
1

IBM FD FORMAT
128 bytes/sector
256 bytes/sector
512 bytes/sector
1024 bytes/sector
not used
not used
not used
not used

HD FORMAT
128 bytes/sector
256 bytes/sector
512 bytes/sector
1024 bytes/sector
2048 bytes/sector
4096 bytes/sector
8192 bytes/sector
16,384 bytes/sector

FORMAT ECC TYPE FIELD
DB? DB6 DB5 DB4

o
1
1
1
note

0
1
1
1
1: WITH

HD FORMAT

0
0 4 ECC bytes generated/checked
1
1 5 ECC bytes generated/checked (1)
1
0 6 ECC bytes generated/checked (1)
0
1? ECC bytes generated/checked (1)
EXTERNAL ECC

IBM FLOPPY DISK FORMAT:
ID FIELD
CYLINDER
HEAD
SECTOR
SECTOR SIZE

DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
track number
side number
sector number

sector size
(2 bits)

HARD DISK FORMAT: ST506 PC FORMAT (512 BYTES)
ID FIELD
CYLINDER
HEAD
SECTOR

DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
cylinder number (8 LSB's)
bad cyl #cyl #cyl # hd # hd # hd # hd #
sector bit 10 bit 9 bit 8 bit 3 bit 2 bit 1 bit 0
flag
sector number

HARD DISK FORMAT: (USER SELECTABLE SECTOR SIZE)
ID FIELD
CYLINDER
HEAD
SECTOR
SECTOR SIZE

DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
cylinder number (8 LSB's)
bad cyl #cyl #cyl # hd # hd # hd # hd #
sector bit 10 bit 9 bit 8 bit 3 bit 2 bit 1 bit 0
flag
sector number
ECC type
X
sector size
(3 bits)

DISK FORMATS
TABLE 6

633

For additional information, please consult the
following:
Technical Note 6-2 (9224 Overview)
Technical Note 6-4 (Using the HOC 9226 HARD
DISK DATA SEP.)
Technical Note 6-5 (Programmer's Reference
Manual)
HOC 9225 Data Sheet
HOC 9226 Data Sheet
HOC 9224 Programmer's Quick Reference Card

STANDARD MICROSYSTEMS
CORPORATION
35 Miwcus EIivd H~uppauge NY 11788
15151273-3100 TWXSI0227889

DATA
BUS

'<-7
ADDR
lMfl
·YYV-

22pf ~

WE OE

IT

" G;;J.

DATA

32KX8 RAM
ARRAY

Dt-I-t-...,

XTAll
XTAl2
HDC 9225
XTAl CONNECTION

o

D~

~=~+==========J.+-----l1 c/o
ADDR~::::::::::::::~~:;:;::::::~
BUS-

~

>~a:

~

L..T-r--r-r--_.....

OJ

RESET INT

AB?-O'

BUSDIR

~

CS

....
AB?-O

INTACK
INT
HOC
SYSR/W
SYSDS
WAIT
SEN

~

TODjfl/O ..

DBMU TYPICAL 8-BIT APPLICATION

DB?-O

1-

HDC
INTERRUPT
RESET

!

tEE BELa,
XTAL 1
fl-PCLKIN

fl-CLKIN

XTAL2

TO DRIVE 1'0

RESET

D ..

...

~ DECODE

AB7-0

HDCCS

INTACK
SECTOR
INTERRUPT
R/W
DS
WAIT

INTACK
INT
SYSR/W

L~

"

't

RAMEN

CLOCKOUT
DMACLK

AB7-0
CLK
DIP

~

STB
LDADD

138

HDCDS
HDCRIW
AD14-1 WE OE

ADl'l BUSDIR

w

I
QJiJ

HOC 9224

ADDR
BUS
DATA A DO-D7
BUS
LOW "I

"

~t> r

A0

I:"

. [h

AO-A13

~~

"

.A

•

---'

...

DIR EN

...

~

a
~~
-=-

22pl -:'

I

XTAL 1
XTAL21
HDC 9225

XTAL CONNECTION

""

7'

AO-A13
22 pI

...

I ~~r:r ~m<

~

t

'I>V

or 
... EN DIR

I>
11<1"1

DATA .A D8-D15
BUS (
HIGH "I

C/o

LOGIC

""

WE DE HilLa DO-D7 D8-D15

16 KX 16 RAM
ARRAY

DBMU TYPICAL 16-BIT APPLICATION

...

EN DIR

t;>/L-

vs.'<-

~

ECCTM

>~

STB
SO
S1
DS
RW

en
'l

RESET INT

DMACLK

OBMU
DIP
HOC 9225 ECCTM

SYSDS
WAIT
SEN

CS

IT'
0

I-

DESCRIPTION OF PIN FUNCTIONS
PIN. NO.
1,2

NAME
Crystal 1
Crystal 2

SYMBOL
XTAL 1
XTAL2

34

Processor
Select
of
Hard
Oisk
Controller
RAM
Enable

HOCCS

31

RAMEN

41

Wait

WAIT

37

System
Read/Write
HOC
Read/Write

SYSR/W

33

39
29
38
3

Output
Enable
Strobe
Write
Enable
ECC
Time

HOCR/W

OE
STB
WE
ECCTM

30

System
Data Strobe

SYSOS

35

HOC
Oata Strobe

HOCOS

24

Ground

GNO

4-7,
20-23

Auxiliary
Bus
7-0

AB 7-0

8-19,
25-27

Address
Bus
14-0

AO 14-0

36

OMAIN
PROGRESS

OIP

OESCRIPTION
An external 10 MHz crystal is connected to these two pins. If an external
10 MHz TTL clock is used, it should be connected to XTAL 1 with a 300
ohm pull-up resistor and XTAL 2 left floating.
This input signal is generated by the host processor and informs the
OBMU that the host processor wants to read or write to the HOC 9224.
The processor should not access the HOC 9224 while it is executing a
previous command.

This input signal is generated by the host processor to indicate to the
OMBU that it wants to access the dual ported ram buffer controlled by the
OBMU. If the HOC 9224 is currently using the buffer, the WAIT signal will
go active, forcing the host processor into a wait state.
This output signal is used to wait-state the host processor when the HOC
9224 and the host processor attempt to access the disk buffer at the
same time.
This input signal from the host processor is used for host processor read/
write control of the HOC 9224 and the dual ported disk buffer.
This pin is used as both an input and output. When the host processor is
either reading or writing to the HOC 9224, this pin outputs the signal presented on SYSR/w' When the HOC 9224 is performing disk I/O, an input
to this pin is used to generate the appropriate RAM control signal.
This output is used to control the output enable lines of the memory used
in the dual ported RAM disk buffer.
This input is connected to the Strobe output on the HOC 9224 and is used
to decode the multiplexed Aux Bus.
This output is used to control the write enable lines of the memory used in
the dual ported RAM disk buffer.
This input pin serves a dual purpose. When the HOC 9224 is performing
error correction, an active (low) input (from the HDC 9224) to this pin
inhibits the internal address counters from incrementing. This allows the
HOC 9224 to correct the error using read-modify-write cycles.
When the HOC 9224 is performing a multiple sector read operation, an
active (low) input on this pin, and an active (low) input on the LOAOO signal to the OBMU indicates that a good sector transfer has occurred.
This input signal is the data strobe generated by the system processor,
and is used to synchronize all processor initiated memory cycles. This
signal is passed through the OBMU to the HOC 9224 via HOCOS if the
processor desires to read or write any of the HOC 9224 internal registers.
This bidirectional pin performs two functions. When the host processor is
accessing the HOC 9224, this output is a "pass through" of the SYSOS
input.
When the HOC is performing memory cycles this signal becomes.2.Q,
!!:!Qut and uses the DS signal from the HOC 9224 to generate the WE or
OE signals to the buffer memory.
System Ground
These 8 inputs are connected directly to the AB7-0 outputs of the HOC
9224. The HOC 9224 will initialize the OBMU's internal 15 bit counter at
each disk sector boundary by loading the start address in a byte serial
fashion (high order byte first). The information is accepted upon the
LOAOO signal gOing active (low).
Ouring HOC 9224 memory cycles, these output pins point to the memory
address for the data passing through the HOC 9224. This address is
automatically incremented at the trailing edge of HOCOS. This bus is in a
high impedance state whenever the system processor is performing
memory cycles or working with the internal registers of the HOC 9224.
This input is generated by the HOC 9224 and informs the OBMU that the
HOC 9224 is about to perform a memory cycle.

638

-------~-----------------------

DESCRIPTION OF PIN FUNCTIONS (continued)

I PIN NO I

NAME

I SYMBOL I

43

LOAD
ADDRESS

LDADD

40

CPU CLOCK
IN
+5V
Interrupt

/LCLKIN

Interrupt
Acklowledge
Bus
Direction
System
Bus
Enable
DMA
Clock

INTACK

48
46

45
32
42

28

47
44

Clock
Out
Reset

-

Vee
INT

BUSDIR
SEN

DMACLK

CLOCK
OUT
RESET

DESCRIPTION
This input is,used to clock the data (appearing on AB7-0) into the internal
15 bit address counter.
The HOC 9224 pulls this pin active (low) simultaneous with the ECCTM
signal when a sector of valid data is in the buffer. The OBMU may be proqrammed to produce an interrUQI on this condition.
This input should be connected to the CPU Clock and must be at least 4
MHz.
+5 Volts
This output pin is used to interrupt the system processor. The OBMU may
be programmed to produce this interrupt after a (programmed) number of
sectors are successfully transferred through the DBMU.
This input is generated by the processor when acknowledging a OBMU
generated interrupt and will reset the INT output to its inactiveJlow~ state.
This output signal controls the flow of data through an external bidirectional tristate bus driver.
This output enables the system processor data bus when the DBMU
allows the processor access to the RAM buffer memory.
This output signal normally runs at a frequency of 5 MHz and feeds the
HOC 9224 to control the timing of all HOC 9224 memory cycles. When
the HOC 9224 is accessing the RAM buffer, the low portion of this signal
is stretched to slow down the HOC 9224 memory cycle and allow processor access to the RAM buffer.
This pin provides the 10 MHz clock required by the HOC 9224. This signal
conforms to the clock input specifications of the HOC 9224.
This input pin resets the DBMU into a known state. Additionally, the INT
output is reset to lQ9ic O.

DESCRIPTION OF OPERATION
DBMU INTERRUPT GENERATION
The DBMU allows the system to empty the RAM buffer while
the HOC 9224 is still filling the buffer. This can significantly
improve system throughput. If the processor instructs the
HOC 9224 to read multiple sectors (N) from the disk, the
DBMU can be programmed to interrupt the processor after
N sectors have been successfully transferred to the buffer.
The value (N) is loaded into the 3 least significant bits of the
upper most OMA address register in the HOC 9224 (Write
Register 2), and transferred to the DBMU when the OMA
address is output by the HOC 9224. (This does not cause
a conflict as the DBMU only uses the lower most 15 bits of
address output by the HOC 9224).
After each successful sector transfer an internal counter
(in the DBMU) is incremented, and when coincidence with
N is met, the DBMU issues an interrupt to the system
processor.

nals when the system processor needs access to the RAM
buffer, while HDCDS indicates that the HOC 9224 needs
access to the buffer.
During each byte transfer initiated by the HOC 9224, a window is set up which will allow processor cycles to occur. If
RAMEN becomes active in this window, it will be granted
immediate access to the buffer. Otherwise, the OBMU will
put the processor in a wait state. This window is open for a
certain percentage (described below) of every byte time,
and will insure that at least one processor cycle is allowed
per byte time.
When the HOC 9224 is not accessing the RAM buffer, the
processor window is open 100% of the time. During multiple sector transfers from the HOC 9224, the window is open
for 100% of the time between sectors.

In the case when these 3 bits = "000", an interrupt is generated after each sector is successfully transferred. If these
3 bits = "111" then an interrupt is generated after every 8
sectors are transferred correctly.

During hard disk operations, where one byte time equals
1600 ns, the processor window is open for 500 ns during
each byte time, except when the HOC 9224 is loading a new
OMA start address to the DBMU. This normally only occurs
on sector boundaries, and in these cases, the window is
open for 400 ns.

MEMORY CONTENTION
The DBMU serves as an arbitrator between the HOC 9224
and the system processor whenever both request access
to the RAM buffer memory. The DBMU input RAMEN sig-

For floppy disk operation, where byte times equal 16 us, 32
us, or 64 us, the window is open for approximately 75% of
each byte time. Once again, when the HOC 9224is loading
a new DMA start address to the DBMU, this window time
drops to 400 ns.

639

The window will be open 100% of the time following the successful transfer of a sector.

formed, the OMACLK is always stretched-even if no contention el(ists. The OBMU address bus A014-0 is put into
the high impedance state when the output SEN is active
and is incremented at the next rising edge of the HOCOS
signal.
.

WAIT OUTPUT TIMING
Due to the asynchronous nature of the RAMEN input with
respect to the internal 10 MHz clock, the generation of WAIT
may vary by approximately 50 ns. For this reason, the user
has the option of selecting either an "early" WAIT or a "late"
WAIT output. If "late" WAIT is selected, the WAIT signal will
become active only if a wait state is needed and it will be
synchronized to the 10 MHz internal clock.

SYSTEM TO HOC ACCESS
When the system processor wants to access the registers
in the HOC 9224, it informs the OBMU via the HOCCS input.
This input is simply a decode of the system processor
address bus lines reserved forthe HOC register addresses.

If "early" WAIT is selected, the WAIT signal will be output
for every RAMEN generated and if a wait state is not needed,
the signal will be reset on the next rising edge of UPCLK.
The selection of "early" or "late" WAIT is programmed via
bit 3 of the most significant OMA Address byte (loaded into
write register 2 of the HOC 9224.) When this bit is set to a
logic 1, the "late" WAIT is selected, while if this bit is reset
to a logic 0, an "early" WAIT is selected: (Upon RESET,
"early" WAIT is selected.)
Note that when an HOC 9224 memory cycle is being per- .

When this signal is active, the BUSOIR signal will be activated to the state which will direct data into or out of the
HOC 9224 as of a function of the SYSR/W input. It should
be noted that there is no way to produce wait states during
system to HOC data transfers. Because of this, it is important to remember that the system must only access the HOC
9224 only after it receives an interrupt from the HOC 9224.
This will ensure that all data transfers between the RAM
buffer and the HOC have concluded as a result of the DONE
bit (in the HOC 9224) being set.'

MAXIMUM GUARANTEED RATINGS
Operating Temperature Range ., ... , ... , ...... , ....... , ............... , ............. , , ... , ...................... 0 to 70 C
Storage Temperature Range .......................................................................... - 55 C to + 150 C
Lead Temperature (soldering, 10 sec) ..... , ..................... ', ....... , .......... , .. , .... ' .. ,' ............... +300 C
Positive Voltage on any Pin, with respect to Ground ....... ' ........... , .... , ........................ ' ... ' , .. , ., ... + 7 V
Negative Voltage on any Pin, with respect to Ground ..... , .. , , .. , ........... , ... , .. , , ....... , .. , ....... , ........ - 0,3 V
Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other condition above those indicated in the operational sections of this spec'
ification is not implied.
NOTE: When powering this device from laboratory or system power,supplies, it is important that the "Maximum Guaranteed Ratings" not be exceeded, or device failure can result. Some power supplies exhibit voltage spikes or "glitches"
on their outputs when AC power is switched off. In addition, voltage transients on the AC power line may appear on the
DC 0!-ltput. If this possibility exists it is suggested that a clamp circuit be used.

640

DC ELECTRICAL SPECIFICATIONS (TA=O Cto 70 C, Vcc=5.0V, ± 5%)

20
OUTPUT VOLTAGE
VOH (1)
V oH (2)

mA

2.4
4.3

V
V

IOH=400 uA
10H = 400 uA (DMACLK and CLKOUT only)

0.4

VOL
V
INPUT VOLTAGE
V,H

10H = 2 mA for outputs except $EN
=4mAforSEN

2.0
0.8

V
V

10
10

uA
uA

CURRENT

AC ELECTRICAL CHARACTERISTICS (TA=O C to

T pD1
T pD2
T pD3

TpD4A
T pD4B

TpD5A
T pD5B
T pD6A
T pD6B
TpD7
Tzx
Txz
T pDs
T pD9
T pD10
T pD11

18
18

TpD12
T pD13

TpD14
T pD15
T pD16
T pD17
TpD1S

20
20
10
10

TpD19
T pD20
T pD21
TW1
TW2
TW3
TW4
TW5
TW6
TW7
Tp

TCH
TCl
TSl
THl
TS2

TH2
,Tws

TW9

+ 70 C, Vcc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

60
130
70
60
45
50
40
60
45
100
45
45
40
40
45
40
100
40
50
50
55
45
50
50
40
40

150
300
500
500
650
650
100
100
50
50
50
50
50
50
200
750

= 5.0V, ± 5%)

CL = 15pf; figure 1a
CL = 15pf; figure 1b
CL = 15pf; figure 2
CL = 15pf; figure 3
CL = 15pf; figure 3A
CL = 15pf; figure 4
CL = 15pf; figure 4A
CL = 15pf; figure 4A
CL = 15pf; figure 4
CL=30pf; figure 5
CL = 30pf; figure 6
CL = 30pf; figure 6
CL = 15pf; figure 7
CL = 25pf; figure 8
CL = 25pf; figure 8
CL = 15pf; figure 9
CL=15pf;figure10
CL = 15pf; figure 11
CL= 15pf; figure 12
CL = 15pf; figure 12
CL = 15pf; figure 12
CL = 15pf; figure 12
CL = 1Opf; figure 13
CL = 1Opf; figure 13
CL = 30pf; figure 13
CL = 30pf; figure 13
Figure 14
Figure 14
Figure 15
Figure 15
Figure 16
Figure 16
Figure 17
Figure 18
Figure 18
Figure 18
Figure 19
Figure 19
Figure 19
Figure 19
Figure 20
Figure 21

641

.. _..

__

....

_------------------

Note: All propagation delays are measured from the 1.5V level
of the input signal to the 1.5V level of the output

~Tffi'-r

RAMEN

WAIT
(early)

~

RAMEN

WAIT
(late)

\

t:r-

I

FIGURE 1A

FIGURE 1B

_T,, 1

V

UPCLK
J

WAIT

FIGURE 2

SYSDS,

HDCDS\

V

i\
T pD4A

V
i\

T pD2A

I
T pD48

T pD48
OE

r

\

i\

OE

J

/

\
FIGURE3A

FIGURE3B

T pD6A

I

\
~

V

/

1\

J
T pD5A

WE

HDCDS""\

V

SysUi'
~

r-

\

T pD58
WE

J

FIGURE4A

T pD68

"r\
FIGURE4B

642

I

/

HDCDS

I

SEN

v

\

-

Tzx

I-

~

ADO

\
J

AD14-0
AD14

FIGURE5

10MHZ~

SEN

~
J

"
FIGURE6

SYSDS~

II

II
r-..

- T'O'r

~

T pD10

T pD9
HDCDS

V--

\
j

r-...

FIGURE 7

FIGURES

LDADDl

SYSR/W

•
HDCR/W

/

T pD12

V

INT

FIGURE9

j

FIGURE 10

INTACK

,
~

INT

- Tffi"}:
FIGURE 11

643

.1

I

I

HDCCS--.....\
~

j

\

HDCR/W
ORSYSR/W

II
~

j
T pD16

T pD1•

I

BUSDIR

j

J

v

FIGURE 12

V
10 MHz
(internal)

-+

II

\

J

J
T pD12

___-+_____~_-+I+____'Tp"""D1........
'"

1-~

V

,

DMACLK---+--11

1\

V

ZXCLK

I
......-TpD21 -

FIGURE 13
Note: all measurements referenced to the 1.SV level.

FIGURE 14

RAMEN,
SYSDs'l
{
HDCDS,
~_ _ _ __

HDCCS

}-

....--Tw1---~ ......-----Tw2,----~

FIGURE 15

FIGURE 16

644

RESET,

INTACK

1

r

TW7

UPCLK

tTc<1T"~

FIGURE 17

\V
J~

\1

AB7-0

J 1\

-

LDADD

ECCTM

FIGURE 18

t

TS1

\

\.

I-TH1 -

I

J

T

_T<;_{

"-

FIGURE 19

ADCR/VV
SYSR/VV

RAMEN

f

TWB

~

FIGURE 20

\
\.

SYSDS

If

/
TW9

FIGURE 21

645

I

10M Hz

DMACLK

STB

WINDOW
HDCDS

(input)
RAMEN

SYSDS

SEN
OE orWE

HOC

"CLKIN

WAIT (early)

WAIT (late)

N+2

AB14-0

FIGURE A-PROCESSOR

HDCCS

, - U - \~____________~r--

I

\

HDCDS
(output)

(outpUI)

HDC9224 CONTENTION TIMING FOR HARD DISK

\

SYSRW~

HDC R W

+

11

,l

I

I

II

I

\

\

~

BUSDIR

I--- PROCESSOR WRITE 9224 CYCLE ----1

~

PROCESSOR READ 9224 CYCLE

---l

FIGURE B-PROCESSOR TO 9224 ACCESS CYCLES

STANDARD MICROSVSTEMS
CORPORATION
35t.bwsBlvd,~,NYn768

1516)273-3100 TWX·510·227·1!-B96

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semicond~ctor applications; consequently complete Information su!ficient for construction purposes is not necessanly give~. The
information has been carefully checked and IS believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

646

HOC 9226

STANDARD MICROSYSTEMS

FEATURES

HIGH PERFORMANCE
HARD DISK DATA SEPARATOR
"HODS" PIN CONFIGURATION

o Significantly reduces component count in hard disk
systems
RCLK
RDATA
EARLY
LATE
WDATA
10MHZOUT
10MHz/XTAL1
XTAL2
5MHZOUT
WRGATE
RDGATE

o Completely compatible with the HOC 9224 Universal
Disk Controller

o Simplifies design and improves performance of ST506
Hard Disk Controller sUb-system

o Built-in write precompensation logic
o Eliminates costly critical "tune up" adjustments

GND

o Space saving 24 pin package saves board space and

Vee
DLY30
DLY40
NC
NC
XDL
DLY50
PUMPUP
PUMPDWN
4XVCO
RDIN
L.~_ _~~r_WDOUT

PACKAGE: 24·pin D.I.P.

reduces critical layout problems.

~~6-J
~
1~15
~~~
()~D()?J::J::J

o Printed Circuit Board Artwork available to facilitate
prototyping and evaluation

>oxzoa..o...
DLY40
DLY30
Vee
NC
RCLK
RDATA
EARLY

25242322212019
18
26
17
27
16
28
15
14
13
12
4
7
8
9
10
11
5 6

4XVCO
RDIN
WDOUT
NC
GND
RDGATE
WRGATE

w«I-0....r.J1-

~~6z;5;56
s:N

XXN

:::

:::

I

~

I

"'

PACKAGE: 28·pin PLCC

GENERAL DESCRIPTION
The HOC 9226 Hard Disk Data Separator (HODS) is a 24
pin CMOS/LSI device, which when used with the HOC 9224
Universal Disk Controller significantly simplifies the design
of a high performance hard disk data separator.
The HOC 9226, combined with a few discrete components,
form a phase locked loop which performs phase and fre-

quency locking onto either the FM or MFM data stream output by ST506/ST412 type drives.
By reducing the number of critical discrete components to
a minimum and eliminating all critical adjustments, the HOC
9226 simplifies the task of the designer.

647

f::J

oo

'"
HOC 9226
BLOCK DIAGRAM

HODS 9226
RCLK

RCLK
RDATA

RDATA

EARLY

EARLY

LATE

LATE

WDATA

WDATA

CLK

10MHZOUT

¢v;;::::-l

HOC
9224

22pf

H-L
~

<0

¢v22Pfl.

10MHZ/XTAL 1

D

1

Vee 1--+5V
DLY30

~
'"

a

::J

en
0

DLY40
NC r-(NC)
NC f--(NC)

m

r

~

I

XDL
DLY50

FILTER
VCO

PMPUP
XTAL2

PMPDWN

DMACLK

5MHZOUT

WGATE

WRGATE

RDIN

RDGATE

RDGATE

WDOUT

SEE
SCHEMATIC
#1

4XVCO

-

To
0 RIVE

r

*GND

11

CONTROL/STATUS

4>-

-",
v

TYPICAL CIRCUIT CONFIGURATION

648

-

DESCRIPTION OF PIN FUNCTIONS
PIN. NO.
1
2
3
4
5

6
7,8

9
10

11

12
13
14

15

16
17
18

19

20,21
22
23
24

DESCRIPTION
Read clock output with nominal frequency of 5 MHz which defines the
half bit boundaries of the RDATA output.
This output is the regenerated raw read data from the drive. This signal
Read Data
RDATA
conforms to all timing requirements of the UDC.
EARLY
This input is connected to the HOC 9224, and causes the HODS to send
Early
out the write data early.
This input is connected to the HOC 9224, and causes the HODS to send
Late
LATE
out the write data late.
This input is connected to the HOC 9224, and is the MFM encoded write
Write Data
WDATA
data signal. This signal is passed through the HODS and is delayed
according to the write precompensation inputs EARLY and LATE.
10 Mhz Out 10MHZOUT This output is normally, connected to the CLK input on the HOC 9224.
A 10 Mhz crystal may be connected between these two inputs. If a TTL
Crystal 1 ,2
XTAL 1,2
signal is used in place of a crystal, the TTL signal (with pullup) should be
connected to the XTAL 1 and the XTAL 2 input should be left open.
5MHZOUT This output is normally tied to the HOC 9224 DMACLK pin in systems that
5 Mhz Out
do not use the HOC 9225 Disk Buffer Management Unit.
Write Gate
WRGATE
This input is connected to the WRGATE output of the HOC 9224. When low
the RDIN input is selected and is output to the delay line via the XDL pin.
When in write mode (WRGATE active), the WDATA input is selected and
output to the delay line via the XDL pin for precompensation.
Read Gate
RDGATE
This input signal, when active, allows the external VCO to begin locking
on the incoming data from the drive. When this signal is inactive, the VCO
will lock on to the 5 MHz output signal.
Ground
GND
This is the ground pin for the device
Write Data
WDOUT
This output is the precompensated version of the WDATA input. This outOut
put is normally connected to the write data signal of the hard disk drive.
Read Data
RDIN
This input is normally connected to the Disk Data output of the drive. The
In
leading edge of this input arms the internal phase comparator, and then
also asserts the PMPUP output 50 ns later.
4 TimesVCO
4XVCO
This input is connected to the external VCO and runs at a frequency of 4
times the data rate with RDGATE asserted. This signal is inte~
divided by 2 and feeds the phase comparator to generate the PMPDN
signal. 4XVCO is also divided by four and output as the RCLK signal.
Pump Down
PMPDN
When active (low) this output will decrease the frequency of the VCO.
Pump Up
When active (low) this output will increase the frequency of the VCO.
PMPUP
Delay 50 ns
This is the 50 ns delay of the XDL signal. The 50 ns tap is used to arm the
DLY50
phase detector and create a reciocked version of the raw read data from
the drive.
Excite
XDL
During write operations, when WRGATE is active, this output is identical
Delay
to WDATA, and is output to the delay line, creating precise delays which
Line
are used to perform write precompensation.
When WRGATE is inactive, this output is the image of the raw read data
the RDIN input. XDL is output to the delay line and is used to provide
proper arming for the phase comparator and clocking for the data recovery circuitry.
No Connect
NC
No connection should be made to these pins.
DLY40
Delay 40
These inputs are delays of 30 and 40 ns of the XDL signal, and come
from the external delay line. These signals are used for the nominal, late
Delay 30
DLY30
and early positioning of the databits in the WDOUT data stream.
+ 5V supply connected to this pin.
Vee
Vee
NAME
Read Clock

SYMBOL
RCLK

649

I
I

DESCRIPTION OF OPERATION
DATA SEPARATION
The HOC 9226, in conjunction with an external VCO, tapped
delay line and filter, allows the system designer to implement a high performance phase locked loop circuit to perform phase and frequency locking onto either an MFM or
FM encoded data stream (from an ST-S06 style disk drive.)

In most applications, the data on the hard disk is recorded
in double density (MFM). In MFM mode, an input pulse on
ROIN indicates not a 1 or 0 but rather a flux transition on the
media and (by definition) these flux transitions may be
spaced at T, 1.ST or 2T time intervals, where T equals the
inverse of the bit data rate. For the standard ST-S06 drive,
these time intervals are 200 ns, 300 ns, and 400 ns.
Oue to the nature of magnetic storage phenomena, the bit
spacing found on the hard disk is not constant, but instead
will modulate due to magnetic effects and drive rotational
speed variations. The HOC 9226 compensates for these
shifts in the ROIN signal coming from the drive and regenerates ROATA and RCLK.
The RCLK signal is derived from the VCO which changes
its period as a function of the variations in the raw disk data
and permits the data from the drive to be correctly clocked
into the HOC 9224 Universal Oisk Controller, independent
of the bit spacing variations found in the raw data coming
from the drive.
The VCO nominally runs at 20 Mhz. Since the half bit time
(for data from the disk) is 100 ns, the HOC 9226 divides the
4XVCO signal in half and compares the phase and frequency of the VCO with the incoming data. The read data
signal is regenerated by the HOC 9266 and is placed cor-

rectly within the RCLK window so as to satisfy the input timing requirements of the HOC 9224 Universal Oisk Controller.
WRITE PRECOMPENSATION GENERATOR
The HOC 9226 also performs write precompensation which
is needed because of tendency of written data to "re-align"
itself on the magnetic media.
Certain bit patterns, when written, and later read back, will
cause a phenomena known as "peak" or "bit" shift. Since
this shifting is predictable, it is common when writing to
magnetic media to intentionally pre-shift when these bits
are to be written. This intentional "pre-shifting" minimizes
the amount of shifting which occurs when the data is read
back, and facilitates proper data recovery.
The HOC 9224 recognizes those patterns which require
"pre-shifting" or precompensation, and outputs EARLY and
LATE signals to alert the HOC 9226 to the need for
precompensation.
Typical ST-S06 applications may require "pre-shifting" the
data bits by approximately 10 ns (either early or late). Three
taps of the delay line (OLY30, OLY40, OLYSO) are normally
used to implement precompensation. The HOC 9226 then
outputs the precompensated data via the WOOUT pin.
PERFORMANCE SPECIFICATIONS
Complete performance specifications and specification
definitions are contained in Technical Note 6-4, which is
available from SMC Sales Offices and sales representatives. Technical Note 6-4 also contains full size PC board
drawings and a complete bill of materials, useful in the prototyping of designs using the HDC 9226.

6S0

MAXIMUM GUARANTEED RATINGS
Operating Temperature Range ........................................................................... " ..... 0 to 70 C
Storage Temperature Range .......................................................................... - 55 C to + 150 C
Lead Temperature (soldering, 10 sec) .......................................................................... +325 C
Positive Voltage on any Pin, with respect to Ground ......................................................... Vee + 0.5V
Negative Voltage on any Pin, with respect to Ground ............................................................ - 0.5 V
Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the "Maximum Guaranteed Ratings" not be exceeded, or device failure can result. Some power supplies exhibit voltage spikes or "glitches"
on their outputs when AC power is switched off. In addition, voltage transients on the AC power line may appear on
the DC output. If this possibility exists it is suggested that a clamp circuit be used.

DC ELECTRICAL SPECIFICATIONS (TA = 0 C to 70 C, Vee = 5.0V, ± 5%)
Parameter
Min.
Max.
Units
SUPPLY CURRENT
mA
30
lee
OUTPUT VOLTAGE
VOH (1)
2.4
V
VOH (2)
4.3
V
V
0.4
VOL
INPUT VOLTAGE
2.0
V
V'H(3)
0.8
V
V'L (3)
V,H (4)
3.5
V
V
1.5
V'L 4
INPUT CURRENT
10
uA
I'H
2.0
mA
I'L
Notes:
(1) For all outputs except 10MHzOUT and 5MHzOUT
(2) For 10MHzOUT and 5MHzOUT
(3) For all inputs except XTAL 1 and 4XVCO
(4) For XTAL 1 and 4XVCO

IOH=400 uA
IOH=400 uA
IOL=2.0 mA

V,H = 2.0V
V'L = O.4V

I

AC ELECTRICAL CHARACTERISTICS (TA=O Cto +70 C, Vee = 5.0V, ± 5%)
Symbol
T,
T2
T3
T.
T5
T6
T7
T8
T9
TlO
T"
T'2
T'3
T,.
T'5
T'6
T17
T'8
T'9
T 20
T2,
T22

Min.

45

Typ.

50
50
50

Max.

Unit

70
80
65
70
100
100
35
35
60
70
65
65
65
65
45
45
45
55

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

6
50
651

figure 1
figure 1
figure 2
figure 2
figure 3
figure 3
figure 4
figure 4
figure 4
figure 4
figure 5
figure 5
figure 5
figure 5
figure 6
figure 7
figure 8
figure 9
figure 10
figure 11
figure 12
figure 12

RDGATE~

WRGATE~

DLY50

\'-----

WDATA

4XVCO
RDIN

PMPUP

XDL

PMPDN

t,.,

FIGURE 1

RDGATE

FIGURES

-.I

'''~k

WDOUT
RCLK

t"

FIGURE2

FIGURE6

RDGATE~

"''''~
WDOUT

(

t"

FIGURE3

FIGURE 7

FIGURE4

FIGURES

652

4XV~~'-~=~r
FIGURE 9

FIGURE 10

EARLY
LATE

DLY50-{

-----'

WDATA

FIGURE 12

FIGURE 11
;;;

All

1
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:s

~

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0

A5

a:

2700

13

74lS04 Ul

~
~

12

I

1K

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ii'

1;'
e3
1K
A4

270(}

C8
Q.22uf

MLC

A2

o

1K

~

5VREF

lc6

~O.22Uf
SINGLE POINT GROUND
PLANE CONNECTION
(NEAR HODS CHIP GROUND PIN)

Analog Gnd

0-

Digital Ground

SCHEMATIC 1
RECOMMENDED CHARGE PUMP
LOOP FILTER AND VCO

653

PC 1

PC 2

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0

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0

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0

0

0
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0000

0

0
0
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0
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0

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PC4
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C2

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CI

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CI
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R2

MICROSYSTEMS CORP
veo

R4

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+rl~3"g~~ ~:::'7gW~ U2
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CIRCUIT SIDE

NOTE: The printed circuit board artwork shown above is included for illustration only. Camera ready artwork is available at no charge.
Contact your SMC representative or regional sales office, and ask for Technical Note TN 6-4.
Blank PC boards (based on the illustrations above) are also available to facilitate evaluation and design. Contact your SMC representative or regional sales office for more information.

STANDARD MICROSVSTEMS
CORPORATION
3SM;o-ws8/¥d..~.NY11788

(5161273-3100

TWX·510·221-8898

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently ·complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices des~ribed any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time In order to improve design and supply the best product possible.

654

HDC9227
PRELIMINARY

High Performance
Dual (Hard/Floppy Disk) Data Separator
DDS

FEATURES

PIN CONFIGURATION

D Single chip combines high performance analog hard
disk data separator and high resolution digital floppy
disk data separator

coo
CD,
RCLK
RDATA
EARLY
LATE
WDATA
10MHZOUT
20MHzlXTAL,
XTAL,
5MHZOUT
WRGATE
RDGATE
GND

D Significantly reduces component count in hard disk and
floppy systems

D Completely compatible with the HDC 9224 Universal
Disk Controller

D Eliminates all tuning and tweaking normally required by
analog data separators

D Built-in hard disk write precompensation logic
D Fabricated in CMOS technology
D Single + 5V supply
D TTL Compatible

2XRDCLK
RESET
Vee
DLY30
DLY40
VCOOUT
DLYDAT
XDL
DLY50
PMPUP
PMPDWN
4XVCO
RDIN
WDOUT

PACKAGE: 2B-pin DIP

GENERAL DESCRIPTION
The HDC 9227 Universal Disk Data Separator (UDDS) is a
28 pin CMOS/LSI device, which when used with the HDC
9224 Universal Disk Controller significantly simplifies the
design of the hard disk/floppy disk sub-system.
Internally, a precision floppy disk digital data separator is

combined with the digital portion of a high performance, self
tuning analog hard disk data separator.
By reducing the number of critical discrete components to
a minimum and eliminating all critical adjustments, the HDC
9227 simplifies the task of the system designer.

655

z

is

cr:

SYN.

OSC

Pll

MUX

HDC 9227 BLOCK DIAGRAM
SCHEMATIC 1

.--

HDC
9224

;!

AB4-AB7

'"
'3

r-oC!J

HDDS9227

f. UJo
a:g;~,,1+
C!J

CDc

(J)m

CD,

'--

~~8gl--

'----

RCLK

RCLK
RDATA

RDATA

+12V
Vee -+5V
DLY30

~

EARLY

LATE

LATE
WDATA

WDATA

NC -(NC)
NC -(NC)
XDL

10MHzOut

2XCLK

---1

0V

~~ ~

22pf

0V

--j

<0

22pf I r

--r

10MHz/XTAL,

XTAL,

DLY50

HDC
9223

'"

DLY40
EARLY

n

.

0
r

m

'"

8.2pf
NPO

12V

...c--

ex,

L........

CX,

Y

I~

GND

Fl

~OPfMLC

F2

illfO/~=_

RDGATE

Rl

PMPUP

PMPUP

C2

PMPDWN

PMPDN

C3

4XVCO

AGND

DMACLK

5MHzOut

4XVCO

WGATE

WRGATE

RDIN

_499il
MLC

470pf

~/
~T

. . FRDATA
RDGATE

RDGATE

~

WDOUT

GND

M
U
X

. . HRDATA
H/F

r--'D
E
M
U
X

'----

TYPICAL CIRCUIT CONFIGURATION
SCHEMATIC 2

656

\

FWDATA
HWDATA

'12~f /

MLC . .

DESCRIPTION OF PIN FUNCTIONS
PIN#
1,2

SYMBOL

DESCRIPTION

CDo, CD,

CDo and CD, control the internal clock divider circuit and hard/
floppy mode. See table 1.

3

NAME
CLOCK DIVISOR
OAND 1
READ CLOCK

RCLK

For hard disks this clock has a nominal frequency of 5 MHz and
defines the half bit boundaries of the RDATA output. For floppy
disks it is the clock derived from the floppy disk drive serial
bit stream.

4

READ DATA

RDATA

This output is a regenerated version of the raw read data from
the drive, either hard or floppy, which satisfies the timing of the
HDC9224.

5

EARLY

EARLY

This input is generated by the Hard Disk Controller. In the hard
disk mode it causes the data separator to output WDOUT early
with respect to WDATA. In the floppy mode this input has no
effect, as floppy precompensation is provided by the HDC 9224.

6

LATE

LATE

This input is generated by the Hard Disk Controller. In the hard
disk mode it causes the data separator to output WDOUT
late with respect to WDATA. In the floppy mode this input has no
effect, as floppy precompensation is provided by the HDC 9224.

7

WRITE DATA

WDATA

This input is the write waveform generated by the Hard Disk
Controller. In the hard disk mode this waveform is passed
through the data separator and is delayed according to the write
precompensation inputs EARLY and LATE. When in the floppy
mode precompensation is handled by the HDC 9224.

8

10 MHz OUTPUT

10MHzOUT

This output is a 10 MHz signal derived from XTAL, and XTAL,. It
is typically used as a 10 MHz clock for the HDC 9224.

9,10

CRYSTAL 1, 2

20MHz/XTAL,
XTAL,

A 20 MHz crystal may be connected between these two pins. If a
TTL signal is used in place of a crystal, the TTL signal should be
connected to the 20 MHz/XTAL, input and the XTAL, output
should be disconnected.

11

5MHzOUTPUT

5MHzOUT

This output is the 10 MHz output divided by two. It is normally
connected to the HDC 9224 DMACLK input when the HDC 9225
chip is not being used.

12

WRITE GATE

WRGATE

This is the WRITE GATE input generated by the Hard Disk
Controller. When low, the Signal at the RDIN input is selected
and output to the delay line via the XDL pin. When high (write
mode), the signal at the WDATA input is selected and output to
the delay line via the XDL pin for precompensation purposes
(hard disk mOde).

13

READ GATE

RDGATE

In hard disk mode, this active-high input signal, upon assertion,
will permit the VCO to begin locking on the incoming data from
the drive. When RDGATE is low, the VCO will lock on to a 5 MHz
signal (20 MHz/4).

14

GROUND

GND

This is the ground pin for the device.

15

WRITE DATA
OUT

WDOUT

This output is the precompensated WDATA signal. This output is
the write data signal connected to the hard or floppy drive.

16

READ DATA IN

RDIN

This input receives data from the drive.

17

4XVCO

4XVCO

This signal is the output of the external VCO and runs at a
frequency equal to four times the hard disk data rate. This signal
is divided by two and then feeds the phase comparator to generate the PMPUP and PMPDWN signal. It is also divided by four
and output as the RCLK signal when in the hard disk mode.

18

PUMP DOWN

PMPDWN

When asserted low, this output will decrease the frequency of
theVCO.

19

PUMP UP

PMPUP

When asserted low, this output will increase the frequency of
theVCO.

20

DELAY50

DLY50

This input is a 50ns delay of the XDL signal. The 50ns tap is
used to arm the phase detector and to create a reclocked version
of the raw read data from the hard disk drive. This input is also
used (in conjunction with DLY40 and DLY30) to generate the
hard disk precompensation delays.

657

DESCRIPTION OF PIN FUNCTIONS
PIN#

NAME

SYMBOL

DESCRIPTION

21

XDL

XDL

22
23
24,25

TEST OUTPUT
TEST OUTPUT
DELAY40
DELAY30

DLYDAT
VCOOUT
DLY 40,
DLY30

26
27
28

5 VOLTS
RESET
2XRDCLK

+5V
RESET
2XRDCLK

During write operations when WGATE is asserted, this output is
identical to WDATA. XDL is output to the delay line thus creating
precise delays which are used during write precompensation.
When WGATE is not asserted, this output is the raw read data
on the RDIN input. XDL is output to the delay line and is used to
provide proper arming for the phase comparator and clocking for
the reclocking circuitry.
Leave disconnected.
Leave disconnected.
These inputs are delays of 40 and 30ns of the XDL signal. The
40, 50 and 30ns delays are used respectively for nominal, late
and early positioning of the bits respectively in the WDOUT
signal when in the hard disk mode.
This pin is the + 5V power pin for the device.
For test only. Connect to + 5V or leave disconnected.
When in the HARD DISK mode this output is nominally 10 MHz.
When in the FLOPPY mode this output is nominally 250KHz,
500KHz or 1 MHz depending on the selected transfer rate.
NOTE: This output is undefined when switching between data
rates, modes and during "LOCK TIME" associated with the
switching of RDGATE.

DESCRIPTION OF OPERATION
The HDC 9227 contains a complete, high performance,
digital data separator for floppy disk use as well as the digital portion of an analog data separator for hard disk use.

HARD DISK MODE
(Selected when BOTH CDo and CD, = 0 )
When in the hard disk mode, the HDC 9227, in conjunction
with the HDC 9223, an external tapped delay line and filter
(shown in Schematic 2) allows a system designer to implement a phase locked loop to perform phase and frequency
locking onto MFM encoded data from a Winchester hard
disk.
In MFM format a pulse on RDIN corresponds not to a 1 or
a 0 but to a flux transition on the media. These flux transitions can be spaced at T, 1.5T, or 2T, time intervals where
the data transfer bit rate is T = 1IFreq. For the ST 506 drive,
Freq. = 5MHz and the flux transitions may be spaced at
200, 300 or 400 nanoseconds.
Due to the phenomena of magnetic storage, the bit spacing
is not constant but instead will vary due to magnetic effects
and drive rotational speed variation. To compensate for this,
the HDC 9227 takes the Read Data from the drive and generates two signals, RDATA and RCLK. The RCLK signal,
derived from the VCO, changes period as a function of the
variations in the disk data, permitting the data from the drive
to be correctly clocked into the HDC 9224 independent of
bit spacing variations on the media.
The VCO runs nominally at 20 MHz since the bit spacing
can change in 100 ns increments and the oscillator must
have the ability to adjust its frequency at this interval. The
HDC 9227 divides 4XVCO by 2 and compares the phase
of this signal to the incoming data. The positive edge of RDIN
arms the phase detector for sampling the phase of the two
signals. The positive edge of 4XVCO/2 asserts PMPDN.
The positive edge of DLY50 asserts PMPUP. Sampling is
terminated when PMPUP and PMPDN are both asserted.
The signal RCLK is generated by dividing 4XVCO by four.
When the HDC 9224 wants to read data from the disk, it
asserts RGATE. This signal tells the phase locked loop to
acquire bit synchronization. If Read Gate is inactive, the VCO
will be locked to a crystal controlled signal of 5 MHz.
658

The HDC 9227 also performs hard disk write precompensation. Certain bit patterns, when written and then read
back, are shifted either late or early depending on the bit
pattern. Since this "bit" or "peak shift" is predictable, intentionally writing these bits late or early will compensate for
the shift during read back.
The HDC 9224 recognizes these patterns, and in addition
to producing the write data waveform, will generate the signals EARLY or LATE to allow the HDC 9227 to write the bits
at the appropriate time. Typically, bits are written early or
late by 10 ns. The last 3 taps ofthe delay line allow the HDC
9227 to implement the precompensation as a function of
the EARLY and LATE signals. The final output write waveform is presented to the drive on the WDOUT pin.

FLOPPY DISK MODE
(Selected when either CDo or CD, = 1)
When in the floppy mode the high performance digital data
separator will accept data from the drive at 125K, 250K, or
500K data rates and output the appropriate regenerated
clock and data signals.
The heart of the digital floppy disk data separator section is
a synthetic oscillator phase locked loop. One half-bit cell of
the incoming data stream corresponds to one cycle of the
synthetic oscillator. Each oscillator cycle consists nominally of 20 phase slices. The circuit therefore needs a phase
slice clock with a frequency of 20 times the half-bit cell time.
Detection of an input pulse away from the center "slot" of
the half-bit cell causes a phase correction to be applied to
the synthetic oscillator, bringing the center of the half-bit cell
closer to the pulse.
A short history of input pulse detections (which induce phase
corrections by the HDC 9227) is kept. This history is used
to allow subsequent phase corrections to request upward
or downward changes in center frequency, and helps compensate.for drive speed variations.
Since the HDC 9227 provides a precompensated WDOUT
(write data output) for floppy disks, this signal can be tied
directly to the floppy drive and contains the precompensated write data required by the drive.

MAXIMUM GUARANTEED RATINGS
Operating Temperature Range ..................................................................................... 0 to 70 C
Storage Temperature Range ............................................................................. - 55 C to + 150 C
Lead Temperature (soldering, 10 sec) .............................................................................. +300 C
Positive Voltage on any Pin, with respect to Ground ............................................................ Vee + 0.5V
Negative Voltage on any Pin, with respect to Ground ................................................................ - 0.5V
Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the "Maximum Guaranteed
Ratings" not be exceeded, or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs
when AC power is switched off. In addition, voltage transients on the AC power line may appear on the DC output If this possibility
exists it is suggested that a clamp circuit be used.

DC ELECTRICAL SPECIFICATIONS (TA
Parameter
SUPPLY CURRENT
Icc
OUTPUT VOLTAGE
VOH
VOH
VOL
INPUT VOLTAGE
V'H
V'L
V'H
V'L
INPUT CURRENT
I'H
I'L

Min.

Max.

=

0 C to 70 C, Vee

=

5.0V, ± 5%)

Units
mA

2.4
4.3

= 400uA (All outputs except 10MHzOUT and 5MHzOUT)
= 400 uA (10MHzOUT and 5MHzOUT)
= 2.0mA

V
V
V

10H
10H
10L

1.5

V
V
V
V

(For all inputs except XTAL, and 4XVCO)
(For all inputs except XTAL, and 4XVCO)
(For XTAL, and 4XVCO)
(For XTAL, and 4XVCO)

10
10

fLA
fLA

V'H
V'L

0.4
2.0
0.8
3.5

= 2.0V
= O.4V

AC ELECTRICAL CHARACTERISTICS (TA = OCto +70C, Vee = 5.0V, ±5%)
Symbol
T,
T2
T3
T4
T5
T6
T"
T'2
T'3
T'4
T'5
T'6
T17
T'8
T'9
T20
T2,
T22
T23
T24
T25
T26
T27
T28
T29

Min.

Typ.

45
25
25
6
50
25

50

Max.
70
80
65
70
100
100
65
65
65
65
45
45
45
55

100

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

659

Comments
figure 1
figure 1
figure 3
figure 3
figure 5
figure 5
figure 2
figure 2
figure 2
figure 2
figure 4
figure 6
figure 8
figure 9
figure 10
figure 11
figure 12
figure 12
figure 12
figure 7
figure 7
figure 7
figure 7
figure 7
figure 7

/

\~-----

~

RDGATE

WRGATE

DLY50

WDATA

4XVCO

RDIN

XDL

t"

FIGURE 1

FIGURE2

RDGATE/

"'' Ok

WDOUT

RCLK

too

FIGURE3

FIGURE4

"'''"~

RDGATE /

WDOUT

RDATA

(

t,&

FIGURE5

FIGURE 6

XTAL,

1\

10MHzOUT -----..111

TII~I T --+II""--T
T
26

2'1

5MHzOUT

-=:(1.

25

/

27

-----+-'

T

'

26

r

I\~I_,-=--=--=--=--=--=--=--T-,,==--=--=--=-------f.
T25

FIGURE7

660

\'--__----'r-

- - - - - ---------------

"1~

DLY50

I

WDOUT

1

--

4xv9.

~

t'8

r--

t17

FIGURES

RDIN - {

t'9

111

\

r

FIGURE9

}-

DLY50--{

t20

FIGURE 10

FIGURE 11

W

EARLY
LATE

'V-

J~

WDATA

---

JI\--

\V

\1/

11\

11\

t2, t - t23

-

t22 f--

FIGURE 12

CD,

COD

Clock Rate

Data Rate

0
0
1
1

0
1
0
1

10 MHz
20 MHz
10 MHz
5MHz

5Mbs
500 Kbs
250 Kbs
125 Kbs

TABLE 1.

661

Drive Type and Mode
Hard Disk, MFM
Floppy, MFM
Floppy, FM or MFM
Floppy, FM

t-

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications;
consequently complete information sufficient for construction purposes is not necessarily given. The information has

~~~~~~~~~~YS~~h1~f~r~a~ibsn ~e~~~~~tt~~~v~~t~~e~h~e~i~r~Jha~~~f~~~ ~~~i~g~d~~~~~t~~~i~~~ude~~r~g~~~~~ul~~~~esse

under the patent rights of SMC or others. SMC reserves the right to make changes at any time in order to improve design
and supply the best product possible.

662

Keyboard Encoder

663

664
-------------

STANDARD MICROSYSTEMS

KR9600
KR9601
KR9602

CORPORATION

Keyboard Encoder Read Only Memory
KEM
PIN CONFIGURATION*

FEATURES

o On-chip "caps" lock (KR960t, KR9602)
o On-chip auto repeat (KR960t, KR9602)
[j Contact bounce protection
o N Key Rollover or Lockout operation
o Hysteresis on keyboard matrix inputs
o Tri-state TTL compatible data outputs

o Serial output (on KR9602 only)

o Quad Mode (Normal, shift, control,
shift-control)

o High frequency clock input
o Pin-compatible with KR3600 (KR9600)
o Static charge protection on all inputs

o

and outputs
+ 5 volt supply

EXTERNALLY SELECTABLE
OPTIONS ON KR9600 AND KR9601

o Pulse or level data ready output signal
o External clock input

o On chip masterlslave oscillator
o All to output bits available
o Lockout/Rollover external selection
o Chip enable external selection
o Data complement control
o Any Key Down output
o Selectable Auto-Repeat rate

KR9600lKR960t

FUNCTION

see "pin
OPTION {
OPTION
assignment
OPTION
chart"
OPTION
OPTION
OPTION
(B9 on KR9600)
data output B8
data output B7
data output B6
data output B5
data output B4
data output B3
data output B2
data output B1
Gnd
data ready
yO
~

y2
y3

o Prograrnmable Auto-Repeat rate

x1
x2
x3
x4
x5
x6
x7
x8

delay node
Vee
shift input
control input
caps lock (NC on KR9600)
y9
y8
y7
y6
y5
y4

KR9602-XX

FUNCTION

X3
X2
X1
XO
Scan clock
Serial clock
Gnd
Serial output
yO
y1
y2
y3
y4
y5

xO

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20'-_ _ _---'

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

X4
X5
X6
X7
X8
Delay node
Vee
Shift
Control
Caps Lock
y9
y8
y7
y6

'PLCC (J LEAD QUAD PACK) also available.

GENERAL DESCRIPTION
The KR9600/t/2 is a keyboard encoder that contains all the
logic necessary to debounce and encode SPST keyswitches into a fully decoded data output of up to 10 bits.
The KR9600/1/2 contains a 3600 bit ROM, 9 stage and 10
stage ring counters, a 10 bit comparator, timing circuitry, a
90 bit memory to store the location of encoded keys for N
key rollover operation, an externally controllable delay net-

work for eliminating the effect of contact bounce, an output
data buffer and TTL compatible output drivers.
The KR9600 and the KR9601 provide a parallel data output
in a 40 pin configuration with pin selectable options, while
the KR9602 provides a serial asynchronous output in a 28
pin configuration with mask programmable options. (Ref.
KR9600/1/2 custom coding information sheet).

665

- - - - - - - - - - - - - - - - - - - - - - - - _...._ - - - - - - -

Yo YI Y2 Y3 Y4 Ys V6 V7 VB Y9

tf"nr"

..-.,.......-C\lNNNNNN...... _ _ _ _ _ _ _ _ _ _ _ _ _

1----I

GND

~

GND

30+

+5V

..

SCALER

Vcc-l"~---

I

10 BIT COMPARATOR

I

-----

~
I
l

I--""V'~

I

CLOCK
CONTROL

GN~D",

ARD
ARO
RRt

"

" ,'v,

ENCODED
KEY
MEMORY

10 STAGE RING
COUNTER

I

l~~"
T

0I

DATA
READY
STROBE

v

I
I

CO NT

N

III

r-

o(")

DELAY

C"

"

I'

C

:;

IGND
1

(j)
(j)
(j)

Ii)

I

::0

I.!.?
29 < ....------,
SHIFT
CONTROL

MODE
DECODE

3600 BIT ROM

39
38
37
36
35
34

9
STAGE
RING
COUNTER

I
I

I
GND

L_____

"
::0
(0

(j)

o
o

~

OUTPUT DATA
BUFFER

VI Y2 Y3 Y4 Y5 Y6 Y7 VB Y9

90 SPST
KEYBOARD
SWITCHES
~~

L----,t----DOWN (OPTION)
TTL
COMPATIBLE
OUTPUT DRIVERS

BloBgBsB7B6BS 8 4 8 3 8 2 8,

.. Not Available on KR9600

"T1

o

::0
(0

(j)

COMPLEMENT
CONTROL
(OPTION) 1

s:

::0

Yo

~,

'1

X2
X3
X4
X5
X6

~

CAPS
I
LOCK .....~.~~,~----I

1

Xl

~T

tr-X7

(10 X 90 X 4)
BITS KEYS MODES

.. 271

»

XO

I

CHIP
ENABLE (OPTION)

I-----Lo/Ro (OPTION)

_ ______________ J

Note: Refer to OPTION SELECTION TABLE for OPTION PIN SELECTION
'R, (tOOK) C, (45 pF) provide approx. 50 KHz Clock Freq.
"c, (300 ns Delay/C oe ) R, supplied internally
'''Diodes necessary for complete n Key Rollover operation

o
....

Yo y, y, y, y, y, y, y, y., y,,
•

r-----

I
GND

Vee

",2

~N

~

,

"

v

~;! ~~ ~~

------ -------------,

GND

..7+
;2+

SCALER

+5V

*

I

11

10 BIT COMPARATOR

J

t
CLOCK
CONTROL

I

I
I

ENCODED
KEY
MEMORY

10 STAGE RING
COUNTER

IGND

I

-..j

211

~

SHIFT
CONTROL

1

MODE
DECODE

20 T)~

I I,,'

I

GND

CAPS
LOCK

1

MAIN

I

CLOCK
16 X
BRCLK

I

TIMING
CKT

123
IR,T
.:' 'I

OJ

r-

STROBE

o(")

lDELAY

"c

c ..

I'

II

~

-=-

GNDI

G)

::D

»

I

I).,.

Cl'l
Cl'l

J

15

rElr
t

I

I

1

L

-~

3600 BIT ROM

f--

...J

0

a:

13

9
STAGE
RING
COUNTER

2
1
28
27
26
25
24

(10 x 90 x 4)
BITS KEYS MODES

xo
X1
X2
X3
X4
X5
X6
X7
X8

==

"T1

... fi;i-

o

::D

DF

-I
::I:

m

"
::D
CD
Cl'l

f-

z

T

0
0

f::

LL

1

I

OUTPUT DATA
BUFFER

I

(f)

10

987654321

PARALLEL/SERIAL
CONVERTER

L_~

1

HUtHt"

I

START/STOP
PARITY
BIT GEN.

,

I

1

I
I
18

TRANSMITTER

Note:

Y, Yl V3 y~

..

y~

SERIAL
OUT

"c, (300 ns Delay/Co') R, supplied internally
'''Diodes necessary for complete n Key Rollover operation

o
I\)

Y6 Y, Ya Y9

90 SPST
KEYBOARD
SWITCHES

I

I
!
A~~~ _ _ _ ~ _ _ _ _ _ _
I _______ J

____

Yo

,

I

DESCRIPTION OF PIN FUNCTIONS
KR9600
PIN#

KR9601
PIN#

KR9602
PIN#

XO-X8

40-32

40-32

4-1
28-24

YO-Y9

17-26

17-26

9-18

1

5

SYMBOL

NAME
X OUTPUTS

YINPUTS
EXTERNAL CLOCK
(see note)
SERIAL CLOCK
,-

...

...

1

...

...

7-14

7-14

8

6

DATA OUTPUTS

B8-B1

DATA READY

DR

16

16

N/A

DELAY NODE
INPUT

DELAY

31

31

23

SHIFT INPUT

SHIFT

29

29

21

CONTROL INPUT

CNTRL

28

28

20

CAPS LOCK

CAPS

see
note

27

19

POWER SUPPLY
GROUND

Vee
Gnd

30
15
see
note

30
15

22
7

1-6

N/A

OPTION PINS

FUNCTION
External outputs from the 9-stage ring
counter to the keyboard to form X-V
matrix with the keyboard switches as
the crosspoints.
External inputs from the keyboard X- Y
matrix.
External clock input.
Serial output Baud rate clock, for
KR9602.
Data outputs B1-B8. Parallel outputs
for the KR9600/9601, serial output for
the KR9602.
This output, which can be a level or a
pulse, signals that a key closure has
been detected and that data is
available at the output port.
Externally controllable delay network
for eliminating the effect of switch
contact bounce.
This input is used to select the shift
mode data.
This input is used to select the control
mode data. Simultaneous assertion of
shift and control inputs will place the
encoder into the shift-control mode.
This input "ANDed" with bit B9 of the
ROM will cause a mode shift. See
"programming options".
+ 5V power supply.
Ground.
See option selection table for pin
assignment.

Note: Caps Lock and Auto-Repeat are not available on KR9600.
See option selection table for pin assignment.

DESCRIPTION OF OPERATION
The main clocks for the KR9600 and KR9601 are derived
from either an external clock source orthe Internal oscillator. The KR9602 requires an external clock. The external clock is routed to a divider with a mask programmable
division rate from 1 to 63 to generate the internal clock,
The keys are scanned in a nine output by ten input matrix,
each key having a unique input-output combination connected to it. The inputs all go selectively to a level detector which has logically variable (1's and O's) levels and
hysteresis, The outputs are enabled one at a time from
output XO towards X8, at a rate of 10-1 OOKHz, through a
9 stage ring counter. The 10 inputs are searched one at
a time from YO to Y9, through a 10 stage ring counter,
each time one of the outputs is enabled. The output and
input pins all have pullups to Vee and are precharged each
clock even if the scan is stopped at one key. When a level
on the selected path to the comparator matches a level
on the corresponding comparator input from the 10 stage
ring counter and the key has not been encoded, the switch
bounce delay network is enabled. The key down stroke
is examined, without advance to the next key location,
until the key has been stable for the length of the DELAY
CAP pin to discharge. The code for the depressed key is
transferred to the output data buffer and the data ready
signal appears,

The scan has two modes as determined by the LOckout!
Rollover option. Once a key is determined to be down the
scan will not advance if in the LOckout mode. Consequentlya new key closure is not detected until the previously depressed key is released. The scan sequence
will resume upon key release and the output data buffer
stores the code of the last key encoded. In the Rollover
mode a "1" is stored in the encoded key memory and the
scan sequence is resumed and the code for the last
encoded key remains in the data output buffer. Each
depressed key is encoded regardless of the state of the
previously depressed keys. The internal keyboard ROM
is 10 bits wide. Bits 1-8 are output via data outputs B1B8. Bits 9 and 10 may be output as data and/or utilized
respectively for Caps-lock and Auto-repeat select. This
allows mask programmable selection of which keys will
have caps-lock and auto-repeat. When selected, the auto
repeat will commence with a "long" delay after key
depression followed by "short" delays. The duration of
the delays varying with the clock frequency and the state
of the ARD, ARO, and AR1 signals.
A Chip Enable input is available to enable the parallel
output buffer. Data Ready can be put in the high-impedance state with Chip Enable (CE) or can be open drain
as a mask programmable option to facilitate wire-oring
as an interrupt.
668

In the serial output version of KR9602, when a key is
debounced and then called valid, the serial shift register
is loaded with the data (8 bits B1-B8) from the ROM, the
data from the parity generator, and the data from the start
and stop bits generator. Bits B9 and B10 are internally
used respectively for Caps-lock and Auto-repeat select.
The data register is then allowed to shift data out at the
rate of one bit per 16 clocks of the baud rate clock pin, on
the negative edge of that clock. If the baud rate clock is
too slow with respect to the internal clock, and the keyboard were allowed to continue scanning when the data
register is loaded, then new data could be loaded on top
of shifting-out data.
To avoid this, if a new key is depressed before the previous data is fully shifted out of the device, including the
stop bits, the delay cap will be allowed to decay but the
internal logic will delay its effect until the shift out of the
previous data is completed. If the new key is released
before the end of the extended delay time it will not be
encoded.

_ _P,-I:.:...N=1
1
2
2
3
3
4
4
5
5
6

FUNCTION in ut unless noted
Ext clock (opt. internal divisor of 1-63)**
Pin 1 of Internal oscillator.
Pin 2 of Internal oscillator.
Lo/Ro CC CE ARD** ARO** AR1**
Pin 3 of Internal oscillator.
Lo/Ro CC CE ARD** ARO** AR1 **
AKO output
Lo/Ro CC CE ARD** ARO** AR1 **
AKO or B1 0 output
Lo/Ro CC CE ARD** ARO** AR1 **
B9 or AKO** output

Options Available for the KR9602:
The following options can be obtained on the KR9602
only with a mask program, and are not pin selectable:
Lo/Ro, CC, AUTO-REPEAT, LONG
DELAY, SHORT DELAY,
CLOCK DIVISOR 1,2,4,8,16,32,63; PARITY,
1 OR 2 STOP BITS.

Legend
CC = COMPLEMENT

OPTION SELECTION TABLE
Since the selected coding of each key and all the options
are defined during the manufacture of the chip, the coding and options can be changed to fit any particular
application of the keyboard. Up to 360 codes of up to ten
bits can be programmed into the KR9600/KR9601 ROM
covering most popular codes such as ASCII, EBCDIC,
SELECTRIC etc. as well as many specialized codes:

Pin Assignment for KR9600/KR9601
The chip pins from pin #1 thru pin #6 are optionally connected to differing logic functions. Many of the functions
are available on more than one pin.

PROGRAMMING OPTIONS
The various options on the KR9600 and KR9601 are user
selectable via externally programmable pins, but they are
fixed, internally mask programmed, for the KR9602.

Oscillator:
The main clocks are derived from either an external clock
source or from the Internal oscillator. The resultant signal is then routed to a divider with a mask programmable
division rate from 2 to 63. If no division is required then
the divider is bypassed. The external clock requires one
pin (pin #1), while the Internal oscillator needs three pins
(pins #1, 2, 3) for frequency selection via an external
resistor and capacitor.

Lockout/Rollover: LOIRO
This option selects the operation of the key scan when a
new key is detected. In Lockout the scan stops as long
as the key is down. In Rollover the scan stops till the new
key is debounced by the DELAY CAP and the key code
is output. Then the key position is marked as down and
the scan continues until another new key is seen. The
option is selected either by an external pin or internally
mask programmed, fixed in either state. The external
LOckout selection is optionally hi or low active. A pulldown resistor to ground is optional.

AKO = ANY KEY DOWN
CE = CHIP ENABLE
CONTROL
B10 = B10 (DATA)
Lo,Ro = LOCKOUTI
OUTPUT
ROLLOVER
B9 = B9 (DATA) OUTPUT
INTERNAL CLOCK = SELF CONTAINED OSCILLATOR
(Not available in KR9602)
EXTERNAL CLOCK = EXTERNAL FREQUENCY
SOURCE
ARD = INITIAL AUTO-REPEAT DELAY
ARO, AR1 = SECONDARY AUTO-REPEAT DELAY, OR
NO AUTO-REPEAT WHEN BOTH ARE FALSE.

*Contact local sales office for custom coding sheet.
**Not available on the KR9600.
PUTS and can optionally additionally invert the logic true
state of the DATA READY pin. The option can 'be internally fixed as true or false where true will output a high
logic level. When externally selected the option can be
either input high or low active true. The pulldown to
ground is optional.

Data Ready:
The data ready pin is optionally either a pulse or level
upon an output state ready to transfer. This transfer
occurs when a new key is encoded or when the current
key is repeating via the repeat logic. This output is individually capable of being disabled via CE or inverted via
CC. To invert DATA READY is to have the pulse go logic
low or the level fall to logic low active when the output is
allowed to drive out of the chip.

Any Key Down: AKO output
The AKO output is an indicator to tell that there is at least
one key determined to be depressed. The output is
optionally logic high or low true. The CE can be separately used to set the output in the high impedance mode.
AKO will reset one full keyboard scan time after the last
key is released. AKO cannot be inverted by CC (complement control).

Complement Control: CC

Chip Enable: CE

This option inverts the logic true state of the DATA OUT-

The chip enable option can be internally fixed to true or

669

consist of a programmable number of scan frequency
time clocks varying from 2 to 131071 clock times.
This option is masked programmable and dependent on
the programming of the data bit 10 of the ten data outputs
to be true for the resultant key code (after lock logic) and
upon whether any repeat action should occur at all.
There are three optional pins associated with the auto
repeat logic: ARO, AR1, and ARD. Each of these can
individually optionally have a pulldown resistor to ground.
ARD controls the selection of the initial repeat delay count
code, while the combination of ARO and AR1 controls
the selection of the short delays as shown below. If no
external pins are desired then those functions can be
mask programmed.

can be externally selected. When an external pin is used
the true level is only low true. The true state means that
the outputs connected to CE will go to the driven state
from the high-impedance condition. Output pins 81-810
are always affected by Chip Enable (CE), optional for
Data Ready and Any Key Down. A pulldown to ground is
optional.

Shift Control Lock: S C L
These three pins determine what will be output in
response to a new key being detected. The Caps Lock
pin is optional on the KR9601 and KR9602 but it is not
available on the KR9600. All three pins have optional
pulldown resistors to ground. The Lock option is allowed
if data bit nine of the ten data bits is programmed as true.
In other words the Rom is read with no lock logic allowed,
but with the full influence of the Shift and Control pins.
This determines the 89 output which is used to see if this
key can be shifted (be it a control code or not) by modifying the effect of the Shift upon a second read of the
rom. The operation of the allowed Lock follows this table:
L 99
F F
F F
F F
F F

S
F
F
T
T

C Result
F
N
T
C
S
F
T
SC

F
F
F
F

T
T
T
T

F
F
T
T

F
T
F
T

N
C
S
SC

T
T
T
T

F
F
F
F

F
F
T
T

F
T
F
T

N
C
S
SC

T

T

F

F

T
T

T
T

F
T

T
F

T

T

T

T

TYPICAL INITIAL REPEAT DELAY COUNTS
ARD = hi 80000 clock times
ARD = low 40000 clock times
The repeat delays are selected by a two bit code where
one decode is used to disable the repeat operation
completely.

L = CAPS LOCK
99 = DATA OUTPUT 99
N = NORMAL
S = SHIFT
C = CONTROL
SC = SHIFT and CONTROL

TYPICAL SECONDARY REPEAT COUNTS
ARO
AR1 Count
0
All Auto-Repeat Disabled
1
6250
1
0
3125
1250
1
1

o
o

Typical Example:
One typical approach would be to mask program ARD
for only one long delay value and mask ARO to ground.
This way one can save two option pins for ARD and ARO
and still be able to select or disable auto-repeat via AR1
and have the option of having one fixed short delay value.

allow shift
(iem->M)
shift of Control
SC ForceC->SC
'SIN Opt Force S->N allow reverse
(ieM->m)
remove shift in
'SC/C Opt Force
Shift-Control
SC->C
S

ForceN->S

ROM Data:
The actual programming data is in 10 bit wide characters
with four function codes for each key position. There are
90 key positions organized as 9 "X" outputs with 10 "Y"
inputs. The four functions as previously defined are Control, Shift, Normal, and Shift-Control.
The use of the optional Lock requires the programming
of the 89 data bit. The use of the optional Auto-Repeat
requires the programming of the 810 data bit. If the 89
or 810 outputs are used then these will show the result
of the contents of the "corrected" key function data bits.
The "corrected" function is the possibly changed Normal to Shift etc. etc. so that the output is that of the 'Shifted
key code' NOT that of the initial key code.

'The mask programmable option for the removal of the shift is
coded as either ON for all keys or OFF. Note that the 99 DATA
outpul{and all the others) is the code of the second decode. Note
that shift only occurs when both the lock is true and the unmodified code gives a 99 ROM output as true.

Repeat: ARD ARO AR1
When the Auto-repeat option is selected and a key is
pressed, either of two delays can be selected. Typically
a long initial delay after the key is pressed, and short
delays afterwards ifthe key is still pressed. These delays

Minimum Switch Closure:
T = Switch bounce + (90 x 1/f) + Strobe delay + Strobe width

I

maximum
expected

I

I

determined
determined
by frequency by external
of operation capacitance

I

minimum time
required by
external circuitry

670

CONDITIONS:
The clock divider is 1 so that elkl is "same as clock IN".
A key is pressed down at XOYO but the delay cap has not timed out.
Data Ready is high true and we have already had another key.
DataRP = Data Ready as a Pulse
DataRL = Data Ready as a Level
Clkl

XO
X1

X2

I

------------~:~--r_~\ I
l

Y

1

ur-----------------------I

I
I
------------~I~--+_~--~I

l

I
I

I

L-.J

I
I

I

DataRP

I

I

I

Delay Cap

I

I

--------~~~II~----------------

DataRL

B1-B10

_____________ ~\c-------------------------

Condition: Test mode autorepeat at divide by 4 and keep key down
Clkl

XO

I
I

I
X1

X2

DelayCap

I

I

I
I

I

------------~I-L--~~~_rl~

I

I

II

I
I

I

I

I
I

I
I

I

L--.J

I

DataRP

I

--------~_HHII
I I
I

DataRL

I

~+41~.

...

I
I

I

I

I

I
I
I

I I

I

I

LlJ

1_ _ longdelay

B1-B10

I
I

1..

IlL

I I

~

shortdelay ~ _____ _

--------------~~~----------------------

671

ELECTRICAL CHARACTERISTICS: KR9600, KR9601, KR9602
MAXIMUM GUARANTEED RATINGS
Operating Temperature Range** ....................................................................... O°C to + 70°C
Storage Temperature Range ...................................................................... - 55°C to + 150°C
Lead Temperature (soldering, 10sec.) ....................................................................... +325°C
Positive Voltage on any Pin, with respect to ground ........................................................... + 8.0V
Negative Voltage an allY Pin, with respect to ground .......................................................... - 0.3V
ELECTRICAL CHARACTERISTICS (TA
PARAMETER
D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low Level
High Level

YINPUTS
High Level
Low Level
INPUT CURRENT
Leakage
Input with PUll-down resistor
selected as option
Yinputs
OUTPUT VOLTAGE LEVELS
Low Level
High Level
X output voltage
TRI-STATE LEAKAGE
~NPUT CAPACITANCE
All inputs
POWER SUPPLY CURRENT
A.C. CHARACTERISTICS
CLOCK FREQUENCY*
16X CLOCK FREQUENCY
Chip enable access time
SWITCH CHARACTERISTICS
Min switch closure
Contact closure resistance

=

O°Cto 70°C, Vee = +5V ± 5%, unless otherwise noted)

SYMBOL

V'L
V,H
VYIH
VYIL

MIN

TYP

UNIT

COMMENTS

0.8

V
V
V

All inputs
Except Y + 16X CLK
16XCLKonly

0.8

V
V

Yinput
Yinput

10.0

fLA

All inputs except Y
V,N = 5V

220
-500

fLA
fLA

V,N = 5V
VYIL = 1 volt
Y inputs only

0.4

V
V

2.0
2.2
2.8

IL

IYIL

75
-100

VOL
VOH

2.4

VOL
VOH

3.4

C'N
Icc
Icc
F'N

MAX

-400

TCE

fLA

10
40
35

pF
mA
mA

Except Y inputs
KR9600101
KR9602

4
0.1
640
250

MHz
MHz
KHz
ns

KR9601/02
KR9600
KR9602

0.4
4.0

20
15
0.01
0.01
DC

10

10L = 1.6 mA
10H = 100 fLA
Except X outputs
600 fLA
clock high
10H = 10 fLA
81-810

V
V

see timing
diagram
Zcc
Zcc

300

ohms

1 x 107

NOTE: The KR9600 is a direct replacement forthe KR3600. Please note that due to the logic level of the KR9600, when
replacing the KR3600 in a N-Key rollover system where diodes are utilized, the polarity of the diodes must be
reversed.
* Divisor on ~R9601/02 must be selected such that the resulting internal scan frequency is 10 KHz min to 100 KHz max.
** Parts optionally available in extended temperature ranges in hermetic packages. Inquire at factory.

672

KR9600-PRO DESCRIPTION
The KR9600 PRO is a MaS/LSI device intended to simplify the interface of a microprocessor to a keyboard
matrix. Like the other KR9600 parts, the KR9600 PRO
contains all of the logic to de-bounce and encode keyswitch closures, while providing either a 2-key or N-key
rollover.
The output of the KR9600 PRO is a simple binary code
which may be converted to a standard information code
by a PROM or directly by a microprocessor. This permits
a user maximum flexibility of key layout with simple field
programming.
The code in the KR9600 is shown in Table I. The format
is simple: output bits, 9, 8, 7, 6, 5, 4 and 1 are a binary
sequence. The count starts at XO, YO and increments
through XOY1, XOY2 ... X8Y9. Bit 9 is the LSB; bit 1 is the
MSB.

Bits 2 and 3 indicate the mode as follows:
Bit 2
Bit3
Normal
0
Shift
o
1
1
0
Control
1
1
Shift Control
For maximum ease of use and flexibility, an internal
scanning oscillator is used, with pin selection of N-key
lockout (also known as 2-key rollover) and N-key rollover.
An "any-key-down" output is provided for such uses as
repeat oscillator keying.
Figure 1 shows a PROM-encoded 64 key, 4 mode application, using a 256 x 8 PROM, and Figure 2 a full 90 key,
4 mode application utilizing a 512 x 8 PROM.
If N-key rollover operation is desired, it is recommended
that a diode be inserted in series with each switch as
shown. This prevents "phantom" key closures from
resulting if three or more keys are depressed
simultaneously.

FIGURE 1
KR9600 PRO TYPICAL APPLICATION
64 KEY, 4 MODE

.5

FIGURE 2
KR9600 PRO TYPICAL APPLICATION
90 KEY, 4 MODE

NC

·5

ROllover

.,--/~,
LOCkout

o

NC

Any Key Down

Any Key Do ... "

DalaReady

DalaReady

';~
C!J

~O 40

X139
X238

X238

)(3 37

)(3 37

)(4 36

),4 36

"f----i~

X5 35
)(6 34

r--2

33

~

32

)(6 34

I,\i-}(j-

0

g:

----.£

+-+--+-+-+-1-+--+-+--",'1'0 17
13!","---"'l
7~
+-+--+-+-+-I-+--+-+--"lYI 18 C) 12!","---"'l ~ B~ ~
Y2
+-+--+-+-+-I-+--+-+--"i 19
11 84
A23
$
9~ ti
Y3 20 ~ 10 85
+-1-+--+--t-i-++-t-4
AJ 4
;; 11 ~ ~
+-+--+-+-+-1-+--+-+--9'1'4 21 ~ 9 86
~ 12r-- u
-I-H-++-H-+-t--"'lY5 22
1<1
13~

-I-H-++-IH+t--"'lYJ 20 ~
Y4 21 ~
-I-H-++-IH+t--'-1
'1'5

lyp,cals ... tch

typlcalsw,tch

iN-keyrallover!

(2-keyrollovefl

22

lO,O"O _ _--"'lA5

~

6~

7~

A1 19

'1'724
V8 2S

25

I

=» tt IC)Iyp,calswllch
IN'key'Oliover)

-",

673

Iyp'eals.... ,tel'l
rOllover)

(2·~ey

B~
'5

9~

~g ~ 11~

1"'-_ _~A6 18

'1'6 23

1\ "~'~1
=»': tt': c,r
'1'8

g:

r-'~2~
14F"_ _-"1AO

:s

14~

'1'724

0

+-+-+-+-+-11-+--+-+--4'1'0 ,1
13 82
+-+-+-+-+-11-+--+-+--'1'1'1 180 12 83
+-+-+-+-+-11-+--+-+--'1'1'2 19
.11 84

:s

-I-H-++-H-+-t--"'lY6 23

33

~ 32

6~

14 !!..-NC

;!

12f2L-.
13~

14~

I

TABLE 1
KR9600-PRO CODING SHEET AND OPTIONS
XV
00
01
02
03
04
05
06
07
08
09
10
11

12
13
14
15
16
17

18
19
20

21
22
23
24
25
26

27
28
29
30
31
32
33
34
35
36
37
38

39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
SO
51
52
53
54
65
SS
67

sa

59
70
71

72
73
74
75
7S
77
78
79
80
81
82
83
84
85

as

87
88
89

Normal

Shift

Control

Shift/Control

8·12345678910
000000000
000000001

8-12345678910
001000000
001000001

8-12345678910
010000000
010000001
010000010
010000011
010000100
010000101
010000110
010000111
010001000
010001001
010001010
010001011
010001100
01000,,01
010001110
010001111
010010000
010010001
010010010
010010011
010010100
010010101
010010110
010010111
010011000
010011001
010011010
010011011
010011100
010011101
010011110
010011111
010100000
010100001
010100010
010100011
010100100
010100101
010100110
010100111
010101000
010101001
010101010
010101011
010101100
010101101
010101110
010101111
010110000
010110001
010110010
010110011
010110100
010110101
010110110
010110111
010111000
010111001
010111010
010111011
010111100
010111101
010111110
010111111
110000000
110000001
110000010
110000011
110000100
110000101
110000110
110000111
110001000
110001001
110001010
110001011
110001100
110001101
110001110
110001111
110010000
110010001
110010010
110010011
110010100
110010101
110010110
110010111
11001lDOO
110011001

8-12345678910
011000000
011000001

000000010
000000011

001000010
001000011

000000100
000000101
000000110
000000111
000001000
000001001
000001010
000001011
000001100
000001101

001000100
001000101
00;000110
001001000
001001001
001001010
001001011
001001100
001001101

000001110
000001111
000010000
000010001
000010010
000010011
000010100
000010101
000010110
000010111
000011000
000011001
000011010
000011011
000011100
000011101
000011110
000011111
000100000
000100001
000100010
000100011
000100100
000100101
000100110
000100111
000101000
000101001
000101010
000101011
000101100
000101101
000101110
000101111
000110000
000110001
000110010
000110011
000110100
000110101
000110110
000110111
000111000
000111001
000111010
000111011
000111100
000111101
000111110
000111111
100000000
100000001
100000010
100000011
100000100
100000101
100000110
100000111
100001000
100001001
100001010
100001011
100001100
100001101
100001110
100001111
100010000
100010001
100010010
100010011
100010100
100010101
100010110
100010111
100011000
100011001

001001110
001001111
001010000
001010001
001010010
001010011
001010100
001010101
001010110
001010111
001011000
001011001
001011010
001011011
001011100
001011101
001011110
001011111
001100000
001100001
001100010
001100011
001100100
001100101
001100110
001100111
001101000
001101001
001101010
001101011
001101100
001101101
001101110
00110',11
001110000
001110001
001110010
001110011
001110100
001110101
001110110
001110111
001111000
001111001
001111010
001111011
001111100
001111101
001111110
001111111
101000000
101000001
101000010
101000011
101000100
101000101
101000110
101000111
101001000
10100lDOl
101001010
101001011
101001100
101001101
101001110
101001111
101010000
101010001
101010010
101010011
101010100
101010·101
101010110
101010111
101011000
101011001

OPTIONS:
Internal Oscillator (Pins 1, 2, 3)
Lockout/Rollover (Pin 4)
Internal Resistor to GND
Lockout is Logic 1

001000111

011000010

0,,000011
011000100
011000101

011000110
011000111

011001000
011001001
011001010
011001011
011001100
0,,001101
011001110
011001111
011010000
011010001
011010010
011010011
011010100
011010101
011010110
011010111
011011000
011011001
011011010
011011011
011011100
011011101
011011110
011011111
011100000
011100001
011100010
011100011
011100100
011100101
011100110
011100111
011101000
011101001
011101010
011101011
011101100
011101101
011101110
011101111
01.1110000
011110001
011110010
011110011
011110100
011110101
011110110
011110111
011111000
011111001
011111010
011111011
011111100
011111101
011111110
011111111
111000000
111000001
111000010
" 100001 1
111000100
111000101
111000110
111000111
111001000
111001001
111001010
111001011
111001100
111001101
111001110
111001111
111010000
111010001
111010010
11'010011
111010100
111010101
111010110
111010111
111011000
111011001

Pulse Data Ready
Any Key Down (Pin 5) Positive Output
Internal Resistor to GND on Shift
and Control Pins

674

CODING FOR KR9600-STD
XV
00
01
02
03
04
05
06
07
08
09
10

11
12
13
14
15
16
17
lB
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
3B
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
5B
59
60
61
62
63
64
65
66
67
68
69
70
71

72
73
74
75
76

77
78
79
80
81
82
83
84
85
86
87
88
89

Normal
8-12345678910
1 1000111001
1000110101
1000010101
0101110101
HT 1001000001
H 0001000101
+ 1101011001
SO 0111001001
P 0000110101
1 1000111001
2 0100111001
w 1110110101
1100110101
0001110101
RS 0111100001
% 1010011001
m 1011010101
SI 1111000001
n 0111010101
2 0100111001
3 1100111001
e 1010010101
d 0010010101
1100010101
- 1111100100
$ 0010011001
L 0011000101
US 1111100001
6 0110111001
k 1101010101
4 0010111001
r 0100110101
I 0110010101
SP 0000011000
CAN 0001101000
CR 1011000001
1101111101
1101000000
1110111001
~ 0100011001
5 1010111001
1 0010110101
1110010101
0110110101
ETX 1100000001 .
I 1011111101
? 1111111001
- 1011011001
I 1001011001
SP 0000011001
6 0110111001
Y 1001110101
h 0001010101
b 0100010101
0101111001
> 0111111001
1101111001
NUL 0000000001
0101011001
! 1000011001
7 1110111001
u 1010110101
j 0101010101
n 0111010101
1011111000
< 0011111001
P 0000110101
0 0000111001
& 0110011001
# 1100011001
8 0001111001
; 1001010101
k 1101010101
m 1011010101
I 1111011001
1110011001
LF 0101000000
1011111001
0011001001
FF
( 0001011001
9 1001111001
0 1111010101
I 0011010101
0011011001
0111011001
1101111001
1011100101
1011011001
0 0000111001
9 1001111001

~,

,,

,

vi
~

~

~

i

OPTIONS:
Internal Oscillator (Pins 1, 2, 3)
Any Key Down (Pin 4) Positive Output
N-Key Rollover only
Pulse Data Ready signal

Shift
8-12345578910

<
0

0011111001
1000100101
A 1000000101
Z 0101100101
HT 1001000001
H 0001000101
+ 1101011001
> 0111111001
@ 0000000101
I 1000011001
(ii, 0000000101
W 1110100101
S 1100100101
X 0001100101
RS 0111100001
% 1010011001
1011100101
1111000001
0111100101
0100011001
# 1100011001
E 1010000101
D 0010000101
C 1100000101
- 1111100100
$ 0010011001
L 0011000101
US 1111100001
& 0110011001
( 1101100101
S 0010011001
R 0100100101
F 0110000101
SP 0000011000
( 0001011000
CR 1011000001
1101111101
1101000000
1110011001
0100011001
% 1010011001
T 0010100101
1110000101
0110100101
ETX 1100000001
1011111101
1111111001
1011111001
1001011001
0000011001
> 0111111001
Y 1001100101
H 0001000101
~ 0100000101
0101011001
> 0111111001
+ 1101011001
NUL 0000000001
0101011001
! 1000011001
& 0110011001
U 1010100101
J 0101000101
N 0111000101
1011111000
< 0011111001
P 0000100101
1001011001
I
& 0110011001
1100011001
~ 0101011001
I 1001000101
K 1101000101
M 1011000101
? 1111111001
0100011001
LF 0101000000
+ 1101011001
< 0011111001
( 0001011001
0001011001
1111000101
L 0011000101
0011011001
0111011001
0101111001
1101100101
- 1111100101
0 0000111001
1001011001
I

sl

vi

e

1
-

S~

~

d
i

Control
8-12345678910
1

1000111011

q 1000111111
a 1000011111

,

0101111111

HT 1001000001
H 0001000101
+ 1101011001
SO 0111000001
NUL 0000000001
SOH 1000000001
2 0100111011
w 1110111111
1100111111
0001111111
RS 0111100001
% 1010011001
CR 1011000001
SI 1111000001
SO 0111000001
STX 0100000001
3 1100111011
e 1010011111
d 0010011111
1100011111
- 1111100100
$ 0010011001
L 0011000101
US 1111100001
ACK 0110000001
DEL 1111111101
4 0010111011
r 0100111111
1 0110011111
SP 0000011000
CAN 0001100000
CR 1011000001
( 1101111111
VT 1101000000
BE~ 1110000001
0100011001
5 1010111011
1 0010111111
G 1110011111
0110111111
ETX 1100000001
I tOl1111111
? 1111111011
- 1011011001
1001011001
0000011001
6 0110111011
Y 1001111111
h 0001011111
b 0100011111
0101111011
> 0111111011
1101111011
NUL 0000000001
0101011001
! 1000011001
7 1110111011
u 1010111111
j 0101011111
n 0111011111
1011111010
< 0011111011
P 0000111111
0 0000111011
& 0110011001
# 1100011001
8 0001111011
; 1001011111
k 1101011111
m 1011011111
I 1111011001
1110011001
LF 0101000000
= 1011111001
FF 0011000001
( 0001011001
9 1001111011
0 1111011111
I 0011011111
0011011001
0111011001
1101111001
1011100101
1011011001
0 0000111001
1001000001
HT

,,

,

,

S~

~

i

Shift Control

8·12345678910
SUB
OLE
(iiJ
P
I
H

0101100001

0000100001

0000000101
0000100101
1001000101
0001000111
+ 1101011011
SO 0111000011
NUL 0000000001
SOH 1000000001
ETB 1110100001
0011100101
A 1000000101
0 1000100101
FS 0011100001
% 1010011011
CR 1011000001
SI 1111000011
SO 0111000001
STX 0100000001
NAK 1010100001
DC3 1100100001
B 0100000101
R 0100100101
0111100100
$ 0010011011
L 0011000111
US 1111100011
ACK 0110000001
DEL 1111111101
DC4 0010100001
ENO 1010000001
C 1100000101
SP 0000011000
BS 0001000000
M 1011000101
K 1101000101
VT 1101000010
BEL 1110000001
0100011011
STX 0100000001
EOT 0010000001
D 0010000101
S 1100100101
ETX 1100000001
N 0111000101
[ 1101100101
- 1011011011
I 1001011011
SP 0000011011
SOH 1000000001
DCl 1000100001
E 1010000101
T 0010100101
SYN 0110100001
Z 0101100101
Y 1001100101
NU~ 0000000001
0101011011
I 1000011011
ETX 1100000001
BEL 1110000001
F 0110000101
U 1010100101
0111111100
W 1110100101
J 0101000101
DC2 0100100001
& 0110011011
# 1100011011
ESC 1101100001
ACK 0110000001
G 1110000101
~ 0110100101
1110011001
0100011001
GS 1011100000
+ 1101011001
FF 0011000011
( 0001011011
EM 1001100001
I 1011100101
X 0001100101
0011011011
0111011011
0101111001
1101100101
- 1111100101
0 0000111001
HT 1001000001
~

i

Internal Resistor to GND on Shift and
Control Pins
KR9600-STD outputs provides ASCII
bits 1-6 on B1-B6, and bit 7 on B8

675

I

CODING FOR KR9601 AND KR9602 STD

XV
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
'37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89

Normal

Shift

Control

Shift/Control

8·12345678910
00000001 00
0000001001
0000001101
0000010001
0000010101
0000011001
00000111 01
0000100001
0000100001
0000100101
0000101001
0000101101
0000110001
0000110001
00001101 01
0000111001
00001111 01
0001000001
00010001 01
0001001001
0001001111
0001010011
00010101 11
0001011011
0001011111
0001100011
0001100111
0001101011
00011011 11
0001110011
0001110101
0001111001
0001111101
0001111101
0010000001
0010000101
0010001001
0010001101
0010010001
0010010101
0010011011
0010011111
0010100011
00101001 11
0010101011
00101011 11
0010110011
0010110111
0010111011
0010111011
0010111101
0011000001
00110001 01
0011000101
0011001001
0011001101
0011010001
0011010100
0011011001
0011011101
0011100011
00111001 11
0011101011
00111011 11
0011110011
0011110111
0011111011
0011111111
00111111 11
00111111 11
0100000001
0100000101
0100001001
0100001101
0100010001
0100010101
0100011001
0100011101
0100100001
0100100101
0100101001
0100101101
0100110001
0100110101
0100111001
0100111101
0101000001
0101000101
0101001001
0101001101

8-12345678910
0101010100
0101011001
0101011101
0101100001
0101100101
0101101001
0101101101
0101110001
0101110001
0101110101
0101111001
0101111101
0110000001
0110000001
01100001 01
0110001001
0110001101
0110010001
0110010101
0110011001
0110011111
0110100011
01101001 11
0110101011
01101011 11
0110110011
0110110111
0110111011
01101111 11
0111000011
0111000101
0111001001
0111001101
0111001101
0111010001
0111010101
0111011001
0111011101
0111100001
0111100101
0111101011
0111101111
0111110011
0111110111
0111111011
0111111111
1000000011
10000001 11
1000001011
1000001011
10000011 01
1000010001
1000010101
1000010101
1000011001
1000011101
1000100001
1000100100
1000101001
1000101101
1000110011
1000110111
1000111011
1000111111
1001000011
10010001 11
1001001011
10010011 11
1001001111
10010011 11
1001010001
1001010101
1001011001
1001011101
1001100001
1001100101
1001101001
1001101101
1001110001
1001110101
1001111001
1001111101
1010000001
1010000101
1010001001
1010001101
1010010001
1010010101
1010011001
1010011101

8·12345678910
1010100100
1010101001

8·12345678910
1010100100
1010101001

OPTIONS FOR THE KR9601-STD:
INTERNAL OSCILLATOR [Input clock divisor = 1]
PINS 1, 2, 3
PIN 4
CE [Active Low]
PIN 5
AR 1 [ARO fixed at Lo = 0]
[FIXED LONG DELAY OF 40000 CLOCK TIMES]
[FIXED SHORT DELAY OF 6250 CLOCK TIMES]
PIN 6
AKO [positive true]
Pulsed DATA READY signal
N-KEY ROLLOVER
Pull-down resistor to ground at the following pins:
_SHIFT
_CONTROL
_ CAPS-LOCK
_ARO

676

1010101101

1010101101

1010110001
1010110101
1010111001
1010111101
1011000001
1011000001
1011000101
1011001001
1011001101
1011010001
1011010001
1011010101
1011011001
1011011101
1011100001
1011100101
1011101001
10111011 11
1011110011
1011110111
1011111011
1011111111
1100000011
11000001 11
1100001011
11000011 11
1100010011
1100010101
1100011001
1100011101
1100011101
1100100001
1100100101
1100101001
1100101101
1100110001
1100110101
1100111011
11001111 11
1101000011
1101000111
1101001011
11010011 11
1101010011
11010101 11
11010110 11
1101011011
1101011101
1101100001
1101100101
1101100101
1101101001
1101101101
1101110001
1101110100
1101111001
1101111101
1110000011
11100001 11
1110001011
1110001111
1110010011
11100101 11
1110011011
11100111 11
1110011111
1110011111
1110100001
1110100101
1110101001
1110101101
1110110001
1110110101
1110111001
1110111101
1111000001
1111000101
1111001001
1111001101
1111010001
1111010101
1111011001
1111011101
1111000001
1111000101
1111101001
1111101101

1010110001
1010110101
1010111001
1010111101
10110000 01
1011000001
1011000101
1011001001
1011001101
1011010001
1011010001
1011010101
1011011001
1011011101
1011100001
1011100101
1011101001
1011101111
1011110011
1011110111
1011111011
1011111111
11000000 11
1100000111
1100001011
~100001111

1100010011
1100010101
1100011001
1100011101
1100011101
1100100001
1100100101
1100101001
1100101101
1100110001
1100110101
1100111011
1100111111
1101000011
1101000111
1101001011
1101001111
1101010011
1101010111
1101011011
1101011011
1101011101
1101100001
1101100101
1101100101
1101101001
1101101101
1101110001
1101110100
1101111001
1101111101
1110000011
11100001 11
1110001011
11100011 11
1110010011
1110010111
1110011011
1110011111
11100111 11
11100111 11
1110100001
1110100101
1110101001
1110101101
1110110001
1110110101
1110111001
1110111101
1111000001
1111000101
1111001001
1111001101
1111010001
1111010101
1111011001
1111011101
1111100001
1111100101
1111101001
1111101101

OPTIONS FOR THE KR9602-STD:
N-KEY ROLLOVER
AUTO-REPEAT
(FIXED LONG DELAY OF 40000 CLOCK TIMES)
(FIXED SHORT DELAY OF 6250 CLOCK TIMES)
1 STOP bit.
No PARITY bit.
Input clock divisor of 63
Pull-down resistor to ground at the following pins:
-SHIFT
-CONTROL
-CAPS-LOCK

OSCILLATOR FREQUENCY vs
C1 FOR KR9600/KR9601

STROBE DELAY vs C2 FOR KR9600/1/2

,o33,--.,----.----,---,-----,_----,
R == lOOK!!

I--H--I~O~I~:~ 5UPPLY-

,0221---I--+---+:'7'"/9/----1I----l

VOLTAGE

,01 1--+-"7''''/'---1--+--+-...,

V

,0051-----.'1-_+-_-+_-+_-1_---1

I

,003

.002

r"

/

=25 0

\

c

NOMINAL VOLTAGE : _

II

DELAY =,3000SEC,/CPF

\

,001 ttIL--+--I--l---t--+----t

\

-

20 1--1----11----1..........
--=~o:::::--l

DElAY (mSI

0~0-~2~0--4~0--6~0-~BO~~,00
FREQUENCY (KHz)

KEYBOARD LAYOUT FOR KR9601/9602-STD

[m
YO

rm
YO

rru

[ill
Y6
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y7
YB
Y9
Y4
Y5
~@Y]~[ru~~~~lliJrnJffi]illJ[m

[ill
Y4

Y6

[ill
YO
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YB
Y9
Y9
YB
lli]@TI@U@U[ill@I][ill[ill[lli@1]~[;

@]] ~ [ru[ill
[ill
@lJ [ill [ru [mffi][illWJlill~[illlliJ[ill~~[N] @1] ffiJ lliJ
~ [ill ~~ ffiJillJillJ@;J [m [lli[lli[llilliJ lliJlliJ [ill~ lliJ [ru [ill
@U [ill
[ill [ill
[ill I
~

[ill
Y2 [ill
Y1

Y7

Y5

Y4

Y6

Y5

Y2

Y4

Y3

Y5

Y1

Y7

Y2

Y1

Y2

Y1

Y3

Y2

YO

YO

YO

YO

Y1

Y1

Y2

Y2

Y3

Y3

Y4

Y4

Y5

Y5

Y6

Y6

XB
Y6

Y7

Y7

YB

Y7

Y9

YB

Y9

Y9

YB

Y6

Y9

677

Y5

YB

Y7

Y4

Circuit diagrams utilizing SMC products are included as a means of Illustrating typical semiconductor applica-

tions, consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However. no responsibility is

assumed for inaccuracies. Furthermore, such information does not convey tothe purchasero1the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time In order to improve design and supply the best product possible.

678
.. _ - _ . _ - - _ . _ - - - - -

679

------------------

----------_.--

680

SR 501S-XXX
SR 5015-80
SR 5015-81
SR 5015-133

Quad Static Shift Register
FEATURES
D COPLAMOS@ N Channel Silicon Gate
Technology
D Variable Length-Single Mask
Programmable-1 to 134 bits
D Directly TTL-compatible on all inputs,
outputs, and clock
D Clear function
D Operation guaranteed from DC to 1.0 MHz
D Recirculate logic on-chip
D Single +5.0V power supply
D Low clock input capacitance
D 16 pin ceramic DIP Package
D Pin for Pin replacement for AMI S2182, 83, 85

PIN CONFIGURATION
INPUT A

1~16 ) OUTPUT A

RECABC

2

15 )

RID

CLEAR

3

14

OUTPUTD

INPUTB

4

13

INPUTD

OUTPUTB

5

12

RECD

GND

6

11

NC

Vee

7

10

INPUTC

OUTPUTC

.8

9

CLOCK

APPLICATIONS
D Memory Buffering
D Unique Buffering Lengths
D Terminals
BLOCK DIAGRAM
OUTPUT A

OUTPUTe

REG CONTROL ABC >-~J---l----l

INPUT A

_t----<:.

>--l----f

INPUT C

1------< RECIRC. INPUT 0

,-J-_-C REC. CONTROL 0
INPUT B

INPUT 0

CLOCK

681

CLEAR

General Description
The SMC SR S01S-XXX is a quad static shift register family fabricated using SMC's COPLAMOS® N channel silicon gate
process which provides a higher functional density and speed on a monolithic chip than conventional MOS technology. The
COPLAMOS® process provides high speed operation,low power dissipation,low clock input capacitance, and single +S volt
power supply operation.
These shift registers can be driven by either PL circuits or by MOS circuits and provide driving capability to MOS or PL
circuits. This device consists of four separate static shift registers with independent input and output terminals and logic for
loading, recirculating or shifting information. The SR S01S-80, SR S01S-81, and SR S01S-133 are respectively 80,81, and
133 bit quad shift registers.
Th.e recirculate control pin is common for registers A, B, and C. Register D has an independent recirculate control pin as
well as a recirculate input pin.
A clear pin has been provided that will cause the shift register to be cleared when the pin is at Vcc. A single PL clock is
required for operation.
The transfer of data into the register is accomplished on the low-to-high transition of the clock with the recirculate control
low. For long term data storage the clock may be stopped and held in either logic state. Recirculate occurs when the
recirculate control is high. Output data appears on the low-to-high transition of the clock pulse.
Bits 81 and 133 are available for flag storage.
This device has been designed to be used in high speed buffer storage systems and small recirculating memories.
Special custom configurations are achieved via single mask programming in lengths of 1 to 134 bits.
MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range ................................................................O°C to + 70°C
Storage Temperature Range ...............................................................- SsoC to + 1S0°C
Lead Temperature (soldering, 10 sec.) ............................................................... + 32SoC
Positive Voltage on any Pin, with respect to ground ...................................................... +8.0V
Negative Voltage on any Pin, with respectto ground ..................................................... -0.3V
·Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this
specification is not implied.
ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C, Vcc= +SV±S%, unless otherwise noted)
Parameter
D.C. Characteristics
INPUT VOLTAGE LEVELS
Low Level, VIL
High Level, VIH
OUTPUT VOLTAGE LEVELS
Low Level, VOL
High Level, VOH
INPUT LEAKAGE CURRENT
CLOCK, CLEAR
All Other
POWER SUPPLY CURRENT
A.C. Characteristics
CLOCK
PWH
PWL
Transition, tr, tl
Repetition Rate, 1fT
tDelay
INPUT DATA
to, set-up
to, hold
PWo
OUTPUT DATA
to,ACC
RECIRCULATE CONTROL
tR, set-up
tR, hold
PWR
CLEAR
PWeLEAR

Min.

Typ.

Vce-1.S

Vee-1.S

Max.

Unit

0.8
Vee

V
V

0.4

V
V

1.0

JLa

2S
10
80

pf
pf
ma

4.0

Comments

IOL=1.6ma
IOH=100JLa
VIN=Vce

TA=+2SoC
300
600
0.02
0
300

1.0
1.0

100
200
300

ns
ns
JLs
MHz
ns
ns
ns
ns

200

3S0

ns

200
300
SOO

ns
ns
ns

20

JLS

682

TIMING DIAGRAMS

I '

Clock

i pw~ I
-r-t:nI

PWo

10, set-up

InpulDala

tD. hold

-----~~

Ouipul Dala -

I~~),--'--~

_ _ _ _ _ _-:--:-~.

~.

_ _ __

----JL-

Recirculate
Control

IR sel·up

1-J:ij- IR hold
PWR

PW clear

.1

Clear~'"

Description of Pin Functions
PinNa.

Symbol

Name

Function

A

Input A

2

RECABC

Recirculate ABC

3

ClR

Clear

4
5
6

7
8
9

B
Oa
GNO
Vcc
Oc
ClK

Input B
Output B
GNO
+5 Volt
OutputC
Clock Input

10
11
12

C
NC
RECO

Input C
NC
Recirculate
Control 0

Input signal which is either high or low depending on what
word is to be loaded into shift register.
Input signal when high disconnects inputs from registers
and connects outputs to inputs, thus recirculating
data. Recirculates only A, B, C outputs.
Input signal when high forces outputs to a low state
immediately and clears all the registers.
Input signal for B register.
Output signal for B register.
Power supply Ground.
5 volt power supply.
Output signal for C register.
Input signal which is normally low and pulses high to
shift data into the registers. The data is clocked in on
low to high edge of clock.
Input signal for C register.

13
14
15

0

00

16

OA

Input 0
Output 0
Recirculate
Input 0
Output A

RID

Input signal which is normally low and, when goes high,
disconnects Input 0 to register and connects
Recirculate Input 0 to register.
Input signal for 0 register.
Output signal for 0 register.
Input signal which is the input to the 0 register
when Recirculate Control 0 is high: RECO=1.
Output signal for A register.

683

I

APPLICATIONS
Line Buffer for CRT Display . .. 80 Characters per line.
CLK

'-f

SRS015-80

D

,....-1
D,

V'''.CIo,"

J
D,

t--~

}-

J

r-

D,

PAGE
MEMORY
D,

I-

H

r-

so

SMC
CG5004L·1

[)f

~~
D.

~J~

Serial Data Output
To Monitor Electronics

D,
L,

f-I
CURSOR
MEMORY

L2

L4

La

CURr

D.

~
SASOI5-80

RECIRCULATE

C'K

DECODER

'--'<
I-- ~

I

A

BCD

SCAN
COUNTER

E,' 'ILt

I

CI,,"

Line Buffer for Matrix Printer . .. 132 Characters per line.
elK

-1

SR5015-133

D,

f.-..I
D,

J
CHARACTER
GENERATOR
ROM(s}
SMC CG4100
SERIES

D,

f.-..I
D,

INTERFACE
OR
MEMORY

f.-..I

~~

D.

~
D,

~
D,

t>'' '"-'
.

Solenoid Drivers

~
D.

f-I

End of Lme

. .t

SR5015-133

elK
REC

~

From System Timing

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

684

SR 5017
SR5018
Quad Static Shift Right/Shift Left Shift Register
Last In First Out Buffer
LIFO
FEATURES
D COMPLAMOS® N-Channel Silicon
Gate Technology.
D Quad 81 bit or Quad 133 bit
D Directly Compatible with PL, MOS
D Operation Guaranteed from DC to
1.0MHz
D Recirculate logic on-chip
D Single +5.0V power supply
D Low clock input capacitance
D Single phase clock at PL levels
D Clear function
D 16-pin Ceramic DIP Package
APPLICATIONS
D Bi-Directional Printer
D Computers-Push Down
Stack-LIFO
D Buffer data storage-memory buffer
D Delay lines-delay line processing
D Digital filtering

PIN CONFIGURATION
INPUTD

I 1 \...../16

I2
OUTPUTD I 3
CLEAR I 4
OUTPUT A I 5
URCON I 6
INPUT A I 7
RID

CLOCK

RECD

15

GND

14

OUTPUTC

13

INPUTC

12 ~

INPUTB

11

OUTPUTB

10

RECABC

[8

9

VCC

D Telemetry Systems
D Terminals
D Peripheral Equipment

BLOCK DIAGRAM
OUTPUT A

OUTPUTe

REC CONTROL ABC ) -.......t-t~

r-.---<.

INPUT A >-+--l~

INPUT C

/---<. RECIRC. INPUT D

'--.t-......- c REC. CONTROL D

'---J---<'

INPUT B ) - - - - (
URCONTROL

>--------.......t--r"l::!~~!.J
CLOCK

685

CLEAR

INPUT D

General Description
The SMC SR 5017 and SR 5018 are quad 133 (SR 5017) and quad 81 (SR 5018) bit static shift registers utilizing SMC's
COPLAMOS® N channel silicon gate process. The COPLAMOS® process provides high speed operation, low power
dissipation, low clock input capacitance, and requires only a single +5 volt power supply.
These shift registers can be driven by either FL circuits or by MOS circuits and provide driving capability to MOS to FL
circuits.
This device consists of four separate static shift registers with independent input and output terminals and logic for
loading, recirculating or shifting information right or left. This shift left/shift right (LiR Control) control input is common to all
registers.
The recirculate control input is common for registers A, B, and C. Register D has an independent recirculate control input
as well as a Recirculate Input.
A Clear input has been provided that will cause the shift register to be cleared when the input is at Vee. A single FL clock
input is required for operation.
The transfer of data into the register is accomplished on the low-to-high transition of the clock with the recirculate control
low. For long term data storage the clock may be stopped and held in either logic state. Recirculate occurs when the
recirculate control is high. Output data appears on the low-to-high transition of the clock pulse.
Bits 81 or 133 are available for flag storage.

MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range ...............................................................O°C to + 70°C
Storage Temperature Range ............................................................... -55°C to + 150°C
Lead Temperature (soldering, 10 sec.) .. , ............................................................ +325°C
Positive Voltage on any Pin, with respect to ground ..................................................... +8.0V
Negative Voltage on any Pin, with respect to ground .................................................... -0.3V
*Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this
specification is not implied.
ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C, Vee= +5V±5%, unless otherwise noted)
Parameter
D.C. Characteristics
INPUT VOLTAGE LEVELS
Low Level, VIL
High Level, VIH
OUTPUT VOLTAGE LEVELS
Low Level, VOL
High Level, VOH
INPUT LEAKAGE CURRENT
CLOCK, CLEAR
All Other
POWER SUPPLY CURRENT
A.C. Characteristics
CLOCK
PWH
PWL
Transition, tr, tf
Repetition Rate, 1/T
t Delay
INPUT DATA
to, set-up
to, hold
PWo
OUTPUT DATA
to,ACC
RECIRCULATE CONTROL
tA, set-up
tA, hold
PWA
CLEAR
PWeLEAA

Min.

Typ.

Vee-1.5

Vee-1.5

Max.

Unit

0.8
Vee

V
V

0.4

V
V

1.0
25
10
100

/La

4.0

Comments

IOL=1.6ma
IOH=100/La
VIN=Vee

pi
pf
ma
TA=+25°C

300
600
0.02
0
500

1.0
1.0

ns
ns
/Ls
MHz
ns
ns
ns
ns

150
150
300
200

350

ns

200
300
500

ns
ns
ns

20

/LS

686
- - - - --------

---

------, ---

------

'--

Ti,ning Diagram

I'

~I

Clock

pWo

~

to, set-up

to, hold

Input Data - - - - - - /

fO.ACi
/i------'--~

Output Data - - -_ _ _ _ _ _---'.

Recirculate
Control

~
I-J:.j,JtR set-up

tR hold

PWR

R______

'~~~

PWclear

I.

.1

Clear~'"

Description of Pin Functions
Symbol

Name

D
RID

Input D
Recirculate
InputD
Output D
Clear

OD
CLR
OA
URCON

Pin
2
3
4

A

Output A
Shift Left/Shift
Right Control
Input A

7

CLK

Clock Input

8

Vee
RECABC

5 Volt
Recirculate
ABC

9
10

09

Output B
Input B
Input C
OutputC
GND
Recirculate
Control D

11
12
13
14
15
16

B
C
Oc
GND
RECD

5
6

Function
Input Signal for D register.
Input signal which is the input to the D register when recirculate
control D is high: RECD = 1.
Output signal for D register.
Input Signal when high forces outputs to a low state immediately
and clears all the registers.
Output signal for A register.
Input Signal which is low for loading data and for shifting right.
When UR CON is high, the register will shift left.
Input signal which is either high or low depending on what word
is to be loaded into shift register.
Input signal which is normally low and pulses high to shift data
into the registers. The data is clocked in on low to high
edge of clock.
5 volt power supply.
Input signal when high disconnects inputs from registers and
connects outputs to inputs, thus recirculating data. Recirculates
only A, B, C outputs.
Output signal for B register.
Input signal for B register.
Input signal for C register.
Output signal for C register.
Ground.
Input signal which is normally low and, when goes high,
disconnects Input D to register and connects RECIRCULATE
INPUT D to register.

687

Logic Diagram

REC

ABC'>-~--"-'

UR
CON

APPLICATION
Line Buffer for Bidirectional Matrix Printer ..• 80/132 characters per line
ClK
'SA 50i71SR,5018

D,

L

r-I---f

D,

CHARACTER
GENERATOR
ROM(s)
SMC CG4100
SERIES

D3
.... !--I

D,
.... !--I

INTERFACE
OR
MEMORY

h>

To Print Head
Solenoid Drivers

D,

I--i

t-Lf/=

I--i

I

D,

D,

I--i
D,
End of line

1--1

. . ..1

SR S017/SR 5018

ClK

DATA ENTRY
AND LOOP CONTROL
LOGIC
~

R~

STANDARD MICROSVSTEMS
CORPORATION
35t.wcusBlv
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