1986_Storage_Management_Products_Handbook 1986 Storage Management Products Handbook

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1986
Storage Management
Products Handbook

Corita Kent, the cover artist, is an American whose work presents an optimistic, yet philosophical view of the
world we live in. A former Catholic nun and teacher, Corita now devotes her life and energies to her artwork
and the "human needs she feels transcend national and religious barriers." A true "citizen of the world," Corita's
philosophy positions her "on the positive side of hope." Her depiction of the Western Digital mission ... "Making
the leading edge work for you" ... dramatizes the spectrum of solutions we provide our customers.

Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western
Digital Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from Its use. No license is
granted by Implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the
right to change specifications at any time without notice.
COPYRIGHT © 1984, 1985, 1986 WESTERN DIGITAL CORPORATION
ALL RIGHTS RESERVED
This document Is protected by copyright, and contains Information proprietary to Western Digital Corporation. Any copying, adaptation, distribution,
public performance, or public display of this document without the express written consent of Western Digital Corporation is strictly prohibited.
The receipt or possesion of this document does not convey any rights to reproduce or distribute its contents, or to manufacture, use, or sell anything
that It may describe, in whole or in part, without the specific written consent of Western Digital Corporation.

ii

Making the Leading Edge
Work for You
This handbook is designed for you, the engineer. It's intended
to be a useful tool, enabling you to make a preliminary evaluation of our products and later, with samples in hand, design
our products into your own systems.
The data in these pages have been reviewed by our Marketing,
Engineering, Manufacturing, and Quality groups. Now we
would like you to review the information we've provided and
tell us how we can improve it. Please feel free to suggest any
changes, additions, or clarifications that occur to you. And
don't hesitate to call to our attention any sins of omission or
commission we may have made.
We're eager to help upgrade the quality of information our
industry provides to its customers. So, please, help us. Direct
your comments to:
WESTERN DIGITAL CORPORATION
Literature Department
2445 McCabe Way
Irvine, CA 92714
(714) 863-0102

iii

WESTERN
COR

P

0

DIGITAL
o

RAT

N

Regional and District Sales Offices

NORTHEASTERN
UNITED STATES/EASTERN CANADA

SOUTHERN
UNITED STATES

WESTERN
UNITED STATES/WESTERN CANADA

Corporate Place 1·95
100 Corporate Place
Suite 302
Peabody, MA 01960
(617) 535·5914

3483 Satellite Blvd.
Suite 221
Duluth, GA 30136
(404) 476·7704

2302 Martin Street
Suite 325
Irvine, CA 92714
(714) 851·1221

2300 W. Meadowview Road
Suite 209
Greensboro, NC 27407
(919) 299·6733

5743 Corsa Avenue
Suite 201
Westlake Village, CA 91361
(818) 991·2556

2611 Westgrove Drive
Suite 113
Carrollton, TX 91361
(214) 248·6785

201 San Antonio Circle
Building E, Suite 172
Mountain View, CA 94040
(415) 941·0216

111 Madison Avenue
Morristown, NJ 07960
(201) 292·1490
NORTH CENTRAL
UNITED STATES

3600 West 80th Street
Bloomington, MN 55431
(612) 835·1003
1827 Walden Office Sq.
Suite 308
Schaumburg, IL 60195
(312) 397·3111

AMTEC CENTER
6405 Congress Avenue
Suite 110
Boca Rotan, FL 33431
(305) 994·6900

INTERNATIONAL OFFICES

Western Digital (U.K.) Ltd.
55 East Street
Epsom, Surrey KT17 1BP
United Kingdom
(03727) 42955

Western Digital Corp.
12 Rue Auber
75009 Paris, France
(01) 266·1020

Western Digital Deutschland GmbH
Prinzregentenstr. 120
0·8000 Muenchen 80
Federal Republic of Germany
(089) 470·7021

Western Digital Japan Ltd.
8th Floor Dai-44 Kowa Bldg
1·2·7, Higashiyama, Meguro·Ku
Tokyo 153 Japan
(03) 791·2001

WESTERN DIGITAL
CORPORATION

2445 McCabe Way
Irvine, CA 92714

(714) 863-0102

iv

Table of Contents
Functional Index ........................................................................
Numerical Index ........................................................................
System Product Quality/Reliability .........................................................
Quality/Reliability to Leading Edge Technology ..............................................
Announcing Burn-In Program AvailabilitylWarranties ..........................................
Hi-Rei UK" Testing Program ...............................................................
Floppy Disk Controller Devices ............................................................
Floppy Disk Support Devices .............................................................
Winchester Disk Controller Devices ........................................................
Winchester Disk Support Devices ..........................................................
SCSI-Bus Interface Controller .............................................................
Winchester Board Products ...............................................................
Tape Drive Controller Products ............................................................
Main Memory Devices ...................................................................
Integrated Drive Electronics ...............................................................
Ordering Information ................................................................... ~
Package Diagrams ........................................................... " .........
Terms and Conditions ...................................................................

Data Sheets with the Heading below:
Advance Information: This product has not been produced in volume and is subject to functional and timing revisions. Prior to designing with the product, it is necessary to contact Western Digital Corporation
for current information.

v

vii
ix
1
5
11
13
1-1
2-1
3-1
4-1
5-1
6-1
7-1
8-1
9-1
10-1
11-1
11-5

vi

Functional Index
STORAGE MANAGEMENT PRODUCTS
FLOPPY DISK CONTROLLER DEVICES

WD177X-00
WD177X-00
WD1772-02
WD1772-02
FD179X-02
FD179X-02
WD279X-02
WD279X-02

Floppy Disk Formatter/Controller .....................................
Appl Notes .......................................................
Floppy Disk Formatter/Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Appl Notes .......................................................
Floppy Disk Formatter/Controller Family ..............................
Appl Notes .......................................................
Floppy Disk Formatter/Controller Family ..............................
Appl Notes .......................................................

1-1
1-25
1-27
1-51
1-53
1-77
1-91
1-117

FLOPPY DISK SUPPORT DEVICES

WD1691
WD16C92
WD2143-03
WD9216-00/01
WD92C32-00

Floppy Support Logic ..............................................
Floppy Disk Read/Write Support .....................................
Four Phase Clock Generator ........................................
Floppy Disk Data Separator .........................................
Floppy Digital Data Separator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

2-1
2-9
2-13
2-17
2-21

WINCHESTER DISK CONTROLLER DEVICES

WD1010-05
WD1010-05
WD1050
WD1050
WD1100
WD1100-01
WD1100-03
WD1100-04
WD1100-05
WD1100-06
WD1100-07
WD1100-09
WD1100-12
WD2010-05

Winchester Disk Controller ..........................................
Appl Notes .......................................................
SMD Controller/Formatter ...........................................
Appl Notes .......................................................
Series Winchester Controller Chips ...................................
Serial/Parallel Converter ............................................
AM Detector ......................................................
CRC Generator/Checker ............................................
Parallel/Serial Converter ............................................
ECC/CRC Logic ...................................................
Host Interface Logic ...............................................
Data Separator Support Logic .......................................
Improved MFM Generator ...........................................
Winchester Disk Controller ..........................................

3-1
3-25
3-31
3-61
3-69
3-71
3-75
3-79
3-83
3-87
3-93
3-97
3-101
3-107

WINCHESTER DISK SUPPORT DEVICES

WD10C20-05
WD1014
WD1015
WD1100-21
WD11COO-13
WD11COO-17

Self-Adjusting Data Separator .......................................
Error Detection/Support Logic Device .................................
Buffer Manager Control Processor ...................................
Buffer Manager Support Device ......................................
ECC Support Device ...............................................
PC/XT Host Interface Logic Device .. ', ................................

4-1
4-15
4-27
4-31
4-37
4-45

SCSI-BUS INTERFACE CONTROLLER

WD33C92193

SCSI-Bus l':1terface Controller ........................................ 5-1

vii

WINCHESTER BOARD PRODUCTS

WD1002-05
WD1002-HDO
WD1002-SHD
WD1002-SAS
WD1002-WX1
WD1002S-SHD
WD1002C-WX2
WD1002S-WX2
WD1002-WAH
WD1002-WA2
WD1003-SCS
WD1003-WA2
WD1003-WAH

Winchester/Floppy Controller ........................................
Winchester Controller ..............................................
Winchester Disk Controller ..........................................
Winchester/Floppy Disk Controller ....................................
Winchester Disk Controller ..........................................
Winchester Disk Controller ..........................................
Winchester Controller Board ........................................
Winchester Controller Board ........................................
Winchester Disk Controller ..........................................
Winchester Disk Controller ..........................................
Winchester Disk Controller ..........................................
Winchester Disk Controller ..........................................
Winchester Disk Controller ..........................................

6-1
6-11
6-19
6-31
6:49
6-51
6-89
6-91
6-119
6-137
6-157
6-173
6-175

TAPE DRIVE CONTROLLER PRODUCTS

WD2401
WD2404
WD24C02
WD1036R-SHD
WD1036S-WX2

Buffer Management Tape Controller ..................................
Tape Data Separator Module ........................................
ReadlWrite Formatter ..............................................
Streaming Tape Controller ..........................................
Streaming Tape Controller ..........................................

7-1
7-17
7-21
7-25
7-35

MAIN MEMORY DEVICE

WD8206

Error Detection and Correction Unit .................................. 8-1

INTEGRATED DRIVE ELECTRONICS

WD93020

Integrated Drives .................................................. 9-1

viii

Numerical Index
Part Number

Page

WD1002-05 .............................................................................
WD1002-HDO ...........................................................................
WD1002-SAS ...........................................................................
WD1002-SHD ...........................................................................
WD1002-WAH ..........................................................................
WD1002-WA2 ...........................................................................
WD1002-WX1 ...........................................................................
WD1002S-SHD ..........................................................................
WD1002C-WX2 ............................... " .........................................
WD1002S-WX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WD1003-SCS ...........................................................................
WD1003-WAH ..........................................................................
WD1003-WA2 ...........................................................................
WD1010-05 .............................................................................
WD1014 ...............................................................................
WD1015 .............................................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WD1036R-SHD ..........................................................................
WD1036S-WX2 ..........................................................................
WD1050 ...............................................................................
WD10C20-05 ............................................................................
WD1100 ...............................................................................
WD1100-01 ........................................-.....................................
WD1100-03 .............................................................................
WD1100-04 .............................................................................
WD1100-05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WD1100-06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WD1100-07 .............................................................................
WD1100-09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WD1100-12 .............................................................................
WD1100-21 ......................... , ...................................................
WD11COO-13 ............................................................................
WD11 COO-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WD1691 ...............................................................................
WD16C92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WD177X-00 .............................................................................
WD1772-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
FD179X-02 .............................................................................
WD2010-05 .............................................................................
WD2143-03 .............................................................................
WD2401 ...............................................................................
WD2404 ...............................................................................
WD24C02 ..............................................................................
WD279X-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
WD33C9213 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WD8206 ...............................................................................
WD9216-00101 .......................................................................... ,
WD92C32 ..............................................................................
WD93020 ..............................................................................

6-1
6-11
6-31
6-19
6-119
6-137
6-49
6-51
6-89
6-91
6-157
6-175
6-173
3-1
4-15
4-27
7-25
7-35
3-31
4-1
3-69
3-71
3-75
3-79
3-83
3-87
3-93
3-97
3-101
4-31
4-37
4-45
2-1
2-9
1-1
1-27
1-53
3-107
2-13
7-1
7-17
7-21
1-91
5-1
8-1
2-17
2-21
9-1

ix

x

WESTERN

DIGITAL

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System Product Quality/Reliability
QUALITY PROGRAM DESCRIPTION

DESIGNING FOR RELIABILITY

The Quality Organization shown on the attached
organization chart (Figure 2) reports directly to the
President of Western Digital. It assures compliance
to design control, quality, and reliability specifications
pursuant to corporate policy. Quality assurance provisions are derived in part from MIL-Q-9858, as applied
to high grade commercial products.

The premise upon which board and system manufacturing operations are based is that quality is planned
and designed-in, not screened-in or selected. A welltested, high-quality design is far more reliable than
a marginal design with any amount of burn-in or fixes.
To assure top quality design, Western Digital maintains one of the most experienced board/system
design staffs in the industry. A tightly controlled
design review team comprising members from Quality
Assurance, Marketing, Manufacturing and several
experienced design engineers, provides review of
each new design several times during its development
to ensure widest possible performance margins. The
production release procedure assures a checklist for:

CORPORATE QUALITY POLICY

It is the policy of Western Digital Corporation that
every employee be committed to quality excellence
in producing products/processes which conform to
acceptable requirements. The total quality program
is managed and monitored by the quality assurance
organization. Quality assurance is chartered to review
marketing product requirements, qualify hardware and
software designs, certify manufacturing operations
and monitor performance/control conformance to product specifications.
Primary responsibility for execution of the quality program rests with functional organizations to design,
produce, and market high quality and high reliability
products specified to our customers.

Ci1' Test Method/Program Qualifications
Ci1' Characterization Report
Ci1' Field Test (Beta Test) Report
Ci1' Product Qualification Audit
Ci1' Documentation Package Release for
Document Control
Ci1' SoftwarelDiagnostics Qualification

MAINTAINING QUALITY/RELIABILITY IN PRODUCTION

The Quality Control Testing Flow Chart shown on
Figure 1 defines the exact stages contained in the
production process. Internally manufactured LSI components undergo 100% testing at maximum specified
operating temperatures as well as strict quality controls defined to assure high quality and reliability.
Components not designed and manufactured by
Western Digital are also 100% screened during
incoming inspection at 70°C. The tests performed
include selective active component burn-in performed
at 125°C for 160 hours to insure guaranteed levels of
reliability. This 125°C accelerated testing eliminates
defects that cannot effectively be accelerated by
burning-in boards and systems which have
temperature limitations. Key quality control procedures include:
'
Incoming Inspection Procedure
In-Process Travel Card Traceability
[g Workmanship Standards
[g Quality Corrective Action Notice/MRS Procedure
[g Quality Audit Procedure
[g
[g

PRODUCT FINAL TEST/CORRECTIVE ACTION

All boards are 100% in-circuit tested and 100% functional tested for acceptable performance according
to applicable test specifications on testers qualified
by QA. Products are tested at maximum specified
temperature and voltage margins using diagnostic
software to ensure greater performance margins.
Failures are logged on a travel card specifically
designed to insure traceability to manufacturing steps
and to maintain failure records for QA corrective
action.
If the board is designed to perform in a Host system,
further diagnostics are performed in an environment
configured to actual customer requirements.
PRODUCT ACCEPTANCE

Upon completing the final test, the board/system
undergoes QC final workmanship standards inspection and selective samples are audited to the functional product specification to guarantee quality at
specified operating margins to the customer.

2

Receiving Inspection
• 100% Bare Board Testing
• 100% lSI Test (max. temp.)
• 100% IC Test at 70·C
• Power Supply Inspections
• Mechanical/visual Inspections

Selective Static/Dynamic Burn·in
(Active components)

Mainframe Mechanical
Assembly

P.C. Board Assembly

Travel Card Traceability
Assembly Test (Bed of Nalls)
• Shorts/Opens
• Orientation

Assembly Outgoing Inspection
Test Incoming/Travel Card
Traceability
Functional Test
• Voltage Margins
• Temperature Margins
• Diagnostic Software

Mainframe Inspection

Final Inspection
• Revision Control
System Configuration
Functional Test
• Temp. Margins
• Diagnostic Software
Functional Audit
Travel Card Review
Final Inspection

Ship System
Ship Board Product

o

LEGEND:
Mfg. Operation

D

Mfg. Inspection Gate

Figure 1. QUALITY CONTROL TESTING FLOW CHART

3

'WaCGate

WESTERN DIGITAL CORPORATION
CHIEF EXECUTIVE

• Systems Quality
• New Product
Qualification
• System Test
Qualification
• Software
Qualification

• LSI Qualification
• Burn·ln/Stress
Requirements
• Reliability Monitor
Data
• Reliability Testing

•
•
•
•

Document Control
Wafer Defects Control
Subsidiary/Offshore QC
Process Qualification

•
•
•
•
•
•
•
•
•

Incoming QC
Vendor Quality
LSI Burn·ln
LSI Package Monitors
Precap Visuals (883 optional)
100% Test Audit
Failure Analysis
Package Qualification
Calibration Control

'---------'11'----_11'----_ _ _-----'
"Systems Design
Control"

"LSI Design Control"

"Manufacturing Assurance"

Figure 2. QUALITY ORGANIZATION

4

WESTERN

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Quality/Reliability To Leading Edge Technology
Defect control within the process assures the
highest levels of built-in reliability.

QUALITY ASSURANCE PROGRAM HIGHLIGHTS

•

LSI manufacturing assurance provisions are
derived in part from MIL-M-38510 and MILSTD-883B as applied to high grade commerical
components.

•

All process raw materials used in the Mask/Wafer
fabrication and assembly operations are
monitored by Material Assurance.

•

Material Assurance maintains a thorough control
of incoming material and has developed unique
"use/stress tests" (look ahead sample build acceptance) which critical material must pass before
acceptance.

•

The product assurance Department continuously
monitors the internal and external manufacturing
flow (shown in Figure 1) and issues process control reports displaying detailed data and trends for
the associated areas.
Document control is an integral part of Product
Assurance. All specifications are issued and
controlled by this activity.
- The Western Digital Malaysian assembly
operation uses specifications and quality control provisions controlled by Document Control.
Indicators of Malaysia quality are reviewed
weekly.
Purchased FAB and assembly operations are
individually qualified and are certified against
standard specifications during vendor
qualification and monitored against reliability
criteria.

•

Quality audits and gates are located throughout
the manufacturing process in order to assure a
stable process and thus, a quality product to our
customers. Figure 1 illustrates the manufacturing/screeninglinspection flow diagram and identifies the steps as they relate to the production
of LSI devices.

•

Testing assures quality margins through 100%
testing by manufacturing and, in addition, all products must pass a specified AQL sample test performed by QA at maximum operating temperature
as follows:
Outgoing Quality Levels
SUBGROUPS

INSPECTION LEVEL

Subgroup 1-Final 100% Electrical
0.5 AQL
Audit @ Max °C
Subgroup 2-Visual (Marking, Lead
Integrity, Package, Verify customer
1.0 AQL
shipper)
Subgroup 3-Shipping Visual Audit 1.0 AQL
"The double sampling techniques used allow considerably better AQL's in most all cases.
•

5

LSI devices are 100% tested on industry standard
test systems. Quality outgoing testing (auditing)
is done on the Fairchild Sentry Series 20 where
possible to allow better correlation with
customers.

•

PROGRAMS TO ASSURE OPTIMUM RELIABILITY

Improved levels of reliability are available under custom reliability programs using static and dynamic burn-in
to further improve reliability. These programs focus on MOS failure mechanisms as follows:
FAILURE MECHANISMS IN MOS
FAILURE
MECHANISM
Slow Trapping
Contamination
Surface Charge
Polarization
Electromigration
Microcracks
Contacts
Oxide Defects
Electron Injection

EFFECT ON
DEVICE

ESTIMATED
ACTIVATION ENERGY

Wearout
Wearoutl
Infant
Wearout
Wearout
Wearout
Random
Wearout/
Infant
Infant
Random
Wearout

1.0 eV
1.4 eV

Static Burn-In
Static Burn-In

0.5-1.0 eV
1.0 eV
1.0 eV

Static Burn-In
Static Burn-In
Dynamic Burn-in
100% Temp. Cycling
Dynamic Burn-in

0.3 eV

Dynamic Burn-In
at max. voltage
Low Temp. Voltage
Operating Life.

-

Temperature Acceleration of Failure

SCREENING
METHOD

,----------------------

The Arrhenius Plot defines a failure rate proportional to exp (- Ea/kt) where Ea is the activation
energy for the failure mechanism. The figure on
the right indicates that lower activation energy
failures are not effectively accelerated by
temperature alone; hense, maximum voltage
operation is selectively applied to optimize the
burn-in process.

10"
10'
10'

.<
o

o

TYPE COMMAND
I Restore
I Seek
I Step
I Step-in
I Step-out
II Read Sector
II Write Sector
III Read
Address
III Read Track
III Write Track
IV Force
Interrupt

TYPE II & III COMMANDS (Continued)

7
0
0
0
0
0
1
1

6

5

0
0
0
1
1
0
0

0
0
1
0
1
0
1

BITS
4
3
0 h
1 h
u h
u h
u h
m hIs
m hIs

1
1
1

1
1
1

0
1
1

0 hlo E 0 0
0 hlo E 0 0
1 hlo E PIO 0

1

1

0

1

13

2 1
V r1
V r1
V r1
V r1
V r
E O/C
E PIC

12

11

FLAG SUMMARY
TYPE I COMMANDS

h

= Motor On Flag (Bit 3) (1770/2).

h = 0, Enable Spin-up Sequence
1, Disable Spin-up Sequence
h
V = Verify Flag (Bit 2) (1770/2/3)

=

V = 0, No Verify
V = 1, Verify on Destination Track
r1' ro

=

Stepping Rate (Bits 1,0)
WD177o-00
WD1772-00
r1
ro
WD1773-00
o 0
6 ms
6 ms
o 1
12 ms
12 ms
0
20 ms
2 ms
1
1
1
30 ms
3 ms
u
Update Flag (Bit 4) (1770/2/3)
u = 0, No Update
1, Update Track Register
u

=

=

TYPE II & III COMMANDS
m = Multiple Sector Flag (Bit 4) (1770/2/3)
m = 0, Single Sector
1, Multiple Sector
m
H = Motor on Flag (Bit 3) (1770/2)

=

=

H
0, Enable Spin-up Sequence
1, Disable Spin-up Sequence
H
S = Side Compare Flag (Bit 3) (1773 only)

=

S = 0, Compare for side 0
S = 1, Compare ;for side 1
For all Type III commands bit 3 must be O.
ao

So

= Data Address Mark (Bit 0) (1770/213)
= 0, Write Normal Data Mark

So = 1, Write Deleted Data Mark

1-6

0
ro
ro
ro
ro
ro
0

So

10

E = 30ms Settling Delay (Bit 2) (1770/2/3)
E = 0, No Delay
E
1, Add 30ms Delay (1772 Add 15ms Delay*
C = Side Compare Flag (Bit 1) (1773 only)

=

C = 0, Disable Side Compare
C
1, Enable Side Compare
For all Type III commands bit 1 must be O.
P = Write Precompensation (Bit 1) (1770/2/3)
P
O,Enable Write Precomp
P = 1,Disable Write Precomp

=

=

TYPE IV COMMANDS
13-1 0 Interrupt Condition (Bits 3-0)
10 = Not Used (WD1770-00, WD1772-00)
Not Ready to Ready Transition (WD1773-00)
11 = Not Used (WD1770-00, WD1772-00)
Ready to Not Ready Transition (WD1773-00)
12 = Interrupt on Index Pulse
13 = Immediate Interrupt
13-10 = Terminate without interrupt
TYPE I COMMANDS
The Type I Commands include the Restore, Seek,
Step, Step-in, and Step-Out Commands. Each of the
Type I Commands contains a rate field (rO,r1)' which
determines the stepping motor rate.
A 4 /-lsec (MFM) or 8 /-lsec (FM) pulse is provided as
an output to the drive. For every step pulse issued,
the drive moves one track location in a direction determined by the direction output. The chip steps the drive
in the same direction it last stepped unless the command changes the direction.
The Direction signal is active high when stepping in
and low when stepping out. The Direction signal is
valid 24 /-lsec before the first stepping pulse is
generated.
After the last directional step an additional *30 msec
of head settling time takes place if the Verify flag is
set in Type I Commands. There is also a *30 msec
head settling time if the E flag is set in any Type II
or III Command.
When a Seek, Step or Restore Command is executed,
an optional verification of Read/Write head position
can be performed by setting bit 2 (V = 1) in the command word to a logic 1. The verification operation
begins at the end of the *30 msec settling time after
the head is loaded against the media. The track
number from the first encountered 10 Field is compared against the contents of the Track Register. If
the track numbers compare and the 10 Field CRC is
correct, the verify operation is complete and an INTRQ
is generated with no errors. If there is a match but not

Floppy Disk Controller Devices

a valid CRC, the CRC error status bit is set (Status
Bit 3), and the next encountered ID Field is read from
the disk for the verification operation.
The WD177X·00 finds an ID Field with correct track
number and correct CRC within 5 revolutions of the
media, or the seek error is set and an INTRQ is
generated. If V = 0, no verification is performed.
On the WD1770·00 and WD1772-00 only, all com·
mands, except the Force Interrupt Command, are pro·

grammed via the h Flag to delay for spindle motor
start up time. If the h Flag is not set and the MO
signal is low when a command is received, the
WD1770/2-00 forces MO to a logic 1 and waits 6
revolutions before executing the command. At 300
RPM, this guarantees a one second spindle start up
time. If after finishing the command, the device
remains idle for 9 revolutions, the MO signal goes
back to a logic O. If a command is issued while MO

TYPE I COMMAND FLOW

TYPE I COMMAND FLOW

Floppy Disk Controller Devices

1-7

is high, the command executes immediately,
defeating the 6 revolution start up. This feature allows
consecutive Read or Write commands without waiting
for motor start up each time; the WD1770/2-00
assumes the spindle motor is up to speed.
RESTORE (SEEK TRACK 0)

Upon receipt of this command, the Track 00
(TROO) input is sampled. If TROO is active low
indicating the ReadlWrite head is positioned over
track 0, the Track Register is loaded with zeroes and
an interrupt is generated. If TROO is not active low,
stepping pulses at a rate specified by the r1,rO field
are issued until the TROO input is activated.
At this time, the Track Register is loaded with zeroes
input
and an interrupt is generated. If the TROO
does not go active low after 255 stepping pulses, the
WD177X.QO terminates operation, interrupts, and sets
the Seek Error status bit, providing the V flag is set.

A verification operation also takes place if the V flag
is set. The h bit allows the Motor On option at the
start of a command.
SEEK

This command assumes that the Track Register contains the track number of the current position of the
ReadjWrite head and the Data Register contains the
desired track number. The WD177X-00 updates the
Track Register and issues stepping pulses in the
appropriate direction until the contents of the Track
Register are equal to the contents of the Data
Register (the desired track location). A verification
operation takes place if the V flag is on. The h bit
allows the Motor On option at the start of the command. An interrupt is generated at the completion of
the command. Note: When using multiple drives, the
Track Register is updated for the drive selected before
seeks are issued.
STEP

Upon receipt of this command, the WD177X.QO issues
one Stepping Pulse to the disk drive. The stepping
motor direction is the same as in the previous step
command. After a delay determined by the r1,rO field,
a verification takes place if the V flag is on. If the U
flag is on, the Track Register is updated. The h bit
allows the Motor On option at the start of the command. An interrupt is generated at the completion of
the command.

VERIFY
SEQUENCE

STEP-IN

Upon receipt of this command, the WD177X.QO issues
one Stepping Pulse in the direction towards track 76.
If the U flag is on, the Track Register is incremented
by one. After a delay determined by the r1,rO field, a
verification takes place if the V flag is on. The h bit
allows the Motor On option at the start of the command. An interrupt is generated at the completion of
the command.
STEP-OUT

SET
CRC
ERROR

INTRO
RESET BUSY

TYPE I COMMAND FLOW

1-8

Upon receipt of this command, the WD177X-OO issues
one stepping pulse in the direction towards track O.
If the;U flag is on, the Track Register is decremented
by one. After delay determined by the r1,rO field, a
verification takes place if the V flag is on. The h bit
allows the Motor On option at the start of the command. An interrupt is generated at the completion of
the command.
TYPE II COMMANDS
The Type II Commands are the Read Sector and Write
Sector commands. Prior to loading the Type II Command into the Command Register, the computer
loads the Sector Register with the desired sector
number. Upon receipt of the Type II command, the
Busy Status bit is set. If the E flag = 1 the command
executes after a 30 msec delay.
When an ID field is located on the disk, the
WD177X-00 compares the Track Number on the ID
field with the Track Register. If there is not a match,
the next encountered ID field is read and a comparison is again made. If there is a match, the Sec-

Floppy Disk Controller Devices

Each of the Type II Commands contains an m flag
which determines if multiple records (sectors) are read
or written', depending upon the command. If m = 0,
a single sector is read or written and an interrupt is
generated at the completion of the command. If m
= 1, multiple records are read or written with the Sector Register internally updated so that an address
verification occurs on the next record. The WD177X{)()
continues to read or write multiple records and
updates the Sector Register in numerical ascending
sequence until the Sector Register exceeds the
number of sectors on the track or until the Force Interrupt Command is loaded into the Command Register,
which terminates the command and generates an
interrupt.
For example: If the WD177X-OO is instructed to read
sector 27 and there are only 26 on the track, the Sector Register exceeds the number available. The
WD177X{)() searches for 5 disk revolutions, interrupts
out, resets Busy, and sets the Record Not Found
Status Bit.
READ SECTOR
SETMO
WAIT
61NDEX PULSES

INTRQ, RESET BUSY
SET WRITE PROTECT

Upon receipt of the Read Sector Command, the Busy
Status Bit is set, then when an ID field is encountered
that has the correct track number, correct sector
number, and correct CRC, the data field is presented
to the computer. The Data Address Mark of the data
field is found with 30 bytes in single density and 43
bytes in double density of the last ID field CRC byte.
If not, the ID field is searched for and verified again
followed by the Data Address Mark search. If, after
five revolutions the DAM is not found, the Record Not
Found Status Bit is set and the operation is terminated. When the first character or byte of the data
field is shifted through the DSR, it is transferred to
the DR, and DRa is generated. When the next byte
is accumulated in the DSR, it is transferred to the DR
and another DRa is generated. If the computer has
not read the previous contents of the DR before a new
character is transferred that character is lost and the
Lost Data Status Bit is set. This sequence continues
until the complete data field is inputted to the computer. If there is a CRC error at the end of the data
field, the CRC Error Status bit is set, and the command is terminated (even if it is a multiple record
command).
At the end of the Read operation, the type of Data
Address Mark encountered in the data field is
recorded in the Status Register (Bit 5) as shown:
STATUS BIT 5

TYPE II COMMAND

tor Number of the ID field is compared with the
Sector Register. If there is no Sector match, the next
encountered ID field is read off the disk and comparisons again made. If the ID field CRC is correct,
the data field is located and is either written into, or
read from, depending upon the command. The
WD177X{)() finds an ID field with a Track number, Sector number, and CRC within four revolutions of the
disk, or, the Record Not Found Status bit is set (Status
Bit 4) and the command is terminated with an INTRa.

Floppy Disk Controller Devices

1

o

Deleted Data Mark
Data Mark

WRITE SECTOR

Upon receipt of the Write Sector Command, the Busy
Status Bit is set. When an ID field is encountered that
has the correct track number, correct sector number,
and correct CRC, a DRa is generated. The WD177X{)()
counts off 11 bytes in single density and 22 bytes in
double density from the CRC field and the WG

1-9

INTRO, RESET BUSY
SET RECORD-NOT FOUND

NO

NO

NO

BRING IN SECTOR LENGTH FIELD
STORE LENGTH IN INTERNAL
REGISTER

SET CRC
STATUS ERROR

TYPE II COMMAND

output is made active if the ORO is serviced (Le., the
DR is loaded by the compute~. If ORO is not serviced,
the command is terminated and the Lost Data Status
Bit is set. If the ORO Is serviced, the WG is made
active and six bytes of zeroes in single density and
12 bytes in double density are written on the disk. The
Data Address Mark is then written on the disk as determined by the Cia field of the command as shown:

1-10

80

DATA ADDRESS MARK (BIT 0)

1

Deleted Data Mark
Data Mark

o

The WD177X-OO writes the data field and generates
ORa's to the computer. If the ORO is not serviced
in time for continuous writing the Lost Data Status

Floppy Disk Controller Devices

READ SECTOR
SEQUENCE

NO

SET DATA
LOST

INTRQ, RESET BUSY
SET CRC ERROR
INTRQ RESET BUSY

TYPE II COMMAND

Floppy Disk Controller Devices

1-11

SEQUENCE

SET DATA LOST
WRITE BYTE
OF ZEROES

NO

TYPE II COMMAND

1-12

Floppy Disk Controller Devices

Bit is set and a byte of zeroes is written on the disk.
The command is not terminated. After the last data
byte is written on the disk, the two-byte CRC is computed internally and written on the disk fOllowed by
one byte of logic ones in FM or in MFM. The WG output is then deactivated. INTRa sets 24 I-lsec (MFM)
after the last CRC byte is written. For partial sector
writing, the proper method is to write data and fill the
balance with zeroes.
TYPE III COMMANDS
Read Address

Upon receipt of the Read Address Command, the
Busy Status Bit is set. The next encountered ID field
is then read in from the disk, and six data bytes of
the ID field are assembled and transferred to the DR,
and a DRa is generated for each byte. The six bytes
of the ID field are shown:
TRACK
SIDE
SECTOR SECTOR CRC
ADDR NUMBER AD DR LENGTH
1
1

2

3

4

5

CRC
2
6

Although the CRC characters are transferred to the
computer, the WD177X-OO checks for validity and the
CRC error status bit is set if there is a CRC error. The
Track Address of the ID field is written into the sector register so that a comparison can be made by the
user. At the end of the operation an interrupt is
generated and the Busy Status is reset.
Read Track
Upon receipt of the Read Track Command, the head
is loaded and the Busy Status bit is set. Reading
starts with the leading edge of the first encountered
index pulse and continues until the next index pulse.
All Gap, Header, and data bytes are assembled and
transferred to the data register and DRa's are
generated for each byte. The accumulation of bytes
is synchronized to each address mark encountered.
An interrupt is generated at the completion of the
command.
This command has several characteristics which
make it suitable for diagnostic purposes. They are:
no CRC checking is performed; gap information is

DATA PATTERN
I IN DR (HEX)
00 thru F4
F5
F6
F7
F8 thru FB
FC
FD
FE
FF

--

included in the data stream; and the Address Mark
Detector is on for the duration of the command.
Because the AM detector is always on, write splices
or noise may cause the chip to look for an AM.
The ID AM, ID field, ID CRC bytes, DAM, Data, and
Data CRC Bytes for each sector are correct. The Gap
Bytes may be read incorrectly during write-splice time
because of synchronization.
WRITE TRACK FORMATTING THE DISK
(Refer to section on TYPE III commands for flow
diagrams.)
Data and gap information are provided at the computer interface. Formalling the disk is accomplished
by positioning the R/W head over the desired track
number and issuing the Write Track Command.
Upon receipt of the Write Track Command, the Busy
Status Bit is set. Writing starts with the leading edge
of the first encountered Index Pulse and continues
until the next Index Pulse, at which time the interrupt
is activated. The Data Request is activated
immediately upon receiving the command, but writing
does not start until after the first byte is loaded into
the Data Register. If the DR is not loaded within three
byte times, the operation is terminated making the
device Not Busy, the lost Data Status Bit is set, and
the interrupt is activated. If a byte is not present in
the DR when needed, a byte of zeroes is substituted.
This sequence continues from one Index Pulse to the
next. Normally whatever data pattern appears in the
Data Register is written on the disk with a normal
clock pattern. However, if the WD177X-00 detects a
data pattern of F5 through FE in the Data Register,
this is interpreted as Data Address Marks with missing clocks or CRC generation.
The CRC generator is initialized when any data byte
from F8 to FE is transferred from the DR to the DSR
in FM or by receipt of F5 in MFM. An F7 pattern
generates two CRC characters in FM or MFM. As a
consequence, the patterns F5 through FE do not
appear in the gaps, data field, or ID fields. Also, CRC's
are generated by an F7 pattern.
Disks are formatted in IBM 3740 or System 34 formats
with sector lengths of 128, 256, 512, or 1024 bytes.

--

IN FM (DDEN = 1)
IN MFM (DDEN = 0)
Write 00 thru F4, in MFM
Write 00 thru F4 with ClK = FF
Not Allowed
Write A1* in MFM, Present CRC
Write C2** in MFM
Not Allowed
Generate 2 CRC bytes
Generate 2 CRC bytes
Write F8 thru FB, ClK = C7, Preset CRC Write F8 thru FB, in MFM
Write FC in MFM
Write FC with ClK = D7
Write FD with ClK = FF
Write FD in MFM
Write FE in M FM
Write FE, ClK = C7, Preset CRC
Write FF in MFM
Write FF with ClK = FF

*Missing clock transition between bits 4 and 5.
**Missing clock transition between bits 3 and 4.

Floppy Disk Controller Devices

1-13

DELAY 6
INDEX PULSES

NO

SETINTRQ
LOST DATA
RESET BUSY

TYPE III COMMAND WRITE TRACK

1-14

Floppy Disk Controller Devices

WRITE 2 CRC
CHARS. ClK
FF

=

WRITE FC
ClK = 07

WRITE FO, FE OR
F8·F9, ClK
C7
INITIALIZE CRC

=

WRITE
BYTE OF ZEROES
SET OAT A lOST

WRITE A1 IN MFM
WITH MISSING
CLOCK INITIALIZE
CRC

WRITE C2 IN MFM
WITH MISSING
CLOCK

WRITE 2 CRC
CHARS.

TYPE III COMMAND WRITE TRACK

Floppy Disk Control/er Devices

1-15

TYPE IV COMMANDS
The Forced Interrupt Command is used to terminate
a multiple sector read or write command or to insure
Type I status in the Status Register. This command
is loaded into the Command Register at any time. If
there is a current command under execution (Busy
Status Bit set) the command is terminated and the
Busy Status Bit reset.

The Busy Bit in the status may be monitored with a
user program to determine when a command is complete, in lieu of using the INTRa line. When using the
INTRa, a Busy Status check is not recommended
because a read of the Status Register to determine
the condition of busy resets the INTRa line.
The format of the Status Register is shown below:
(BITS)

The lower four bits of the command determine the
conditional interrupt as follows:

7

= Not used (WD1770-00, WD1772-00), Not Ready

S7

10

11 =

=

12
13 =

To Ready Transition (WD1773-00)
Not Used (WD1770-00, WD1772-00), Ready To
Not Ready Transition (WD1773-00)
Every Index Pulse
Immediate Interrupt

The conditional interrupt is enabled when the corresponding bit positions of the command (13-10) are
set to a 1. When the condition for interrupt is met the
INTRa line goes high signifying that the condition
specified has occurred. If 13-10 are all set to zero (Hex
DO), no interrupt occurs but any command presently
under execution is immediately terminated. When using the immediate interrupt condition (13
1) an interrupt is immediately generated and the current
command terminated. Reading the status or writing
to the Command Register does not automatically
clear the interrupt. The Hex DO is the only command
that enables the immediate interrupt (Hex D8) to clear
on a subsequent load Command Register or Read
Status Register operation. Follow a Hex 08 with DO
command.
Wait 16 Ilsec (double density) or 32 Ilsec (single density) before issuing a new command after issuing a
forced interrupt. Loading a new command sooner
than this nullifies the forced interrupt.

=

Forced interrupt stops any command at the end of
an internal micro-instruction and generates INTRa
when the specified condition is met. Forced interrupt
waits until ALU operations in progress are complete
(CRC calculations, compares, etc.).
Status Register
Upon receipt of any command, except the Force Interrupt Command, the Busy Status Bit is set and the rest
of the status bits are updated or cleared for the new
command. If the Force Interrupt Command is received
when there is a current command under execution,
the Busy Status Bit is reset, and the rest of the status
bits are unchanged. If the Force Interrupt Command
is received when there is not a current command
under execution, the Busy Status Bit is reset and the
rest of the status bits are updated or cleared. In this
case, Status reflects the Type I commands.
The user has the option of reading the Status Register
through program control or using the ORO line with
DMA or interrupt methods. When the Data Register
is read the ORO bit in the Status Register and the
ORO line are automatically reset. A write to the Data
Register also causes both ORa's to reset.

1-16

I

I

6
S6

I

I

5
S5

I

4

131

I

2

1

I

0

I S4 I S3 I S2 I S1 I SO

Because of internal sync cycles, certain time delays
are observed when operating under programmed I/O,
as shown.
Delay Req'd_
FM
MFM

Operation

Next Operation

Write to
Command Reg.

Read Busy Bit
(Status Bit 0)

48J.lsec 24J.lsec

Write to
Command Reg.

Read Status
Bits 1-7

64J.lsec 32J.lsec

Write
Register

Read Same
Register

321lsec 16J.lsec

RECOMMENDED - 128 BYTES/SECTOR
The recommended single-density format with 128
bytes/sector is shown. In order to format a diskette,
the user issues the Write Track Command, and loads
the Data Register with the following values. For every
byte to be written, there is one Data Request.
NUMBER
OF BYTES

~
6
1

HEX VALUE OF BYTE WRITTEN
FF (or 00)
00
FE (10 Address Mark)
Track Number
Side Number (00 or 01)
Sector Number (1 thru 10)
00 (Sector Length)
F7 (2 CRC's written)
FF (or 00)
00
FB (Data Address Mark)
Data (IBM uses E5)
F7 (2 CRC's written)
FF (or 00)
FF (or 00)

1
1
1
1
1
11
6
1
128
1
10
369**
*Write bracketed field 16 times.
* *Continue writing until WD177X-00 interrupts out.
Approx. 369 bytes.

Floppy Disk Controller Devices

.g!!
~

o

Cii"
~

g
a

~~~~~

~

n

I.

____ _

REPEATED
FOR EACH SECTOR

-I

~

~"

m

~---------ID

FIELD--------------'

~------DATA

FIELD------"

-L __

WRITEGATE

SINGLE DENSITY FORMAT

INDEX
PULSE

_ _ _ _

I"

_

~I

REPEATED
FOR EACH SECTOR

USER DATA
256 BYTES
~-----------------IDFIELD----------------~

L-__________

DATA FIELD------------'

WRITE GATE - - - - -....

DOUBLE DENSITY FORMAT

"t

~

OO·xLL~aM

256 BYTES/SECTOR
Shown below is the recommended dual-density format with 256 bytes/sector. In order to format a
diskette the user issues the Write Track Command
and loads the Data Register with the following values.
For every byte to be written, there is one data request.
NUMBER
OF BYTES

~

12

3
1
1
1
1
1
1

22
12

3
1
256
1
24
668**

HEX VALUE OF BYTE WRITTEN
4E

00
F5 (Writes A1)
FE (10 Address Mark)
Track Number (0 thru 4C)
Side Number (0 or 1)
Sector Number (1 thru 10)
01 (Sector Length)
F7 (2 CRC's written)
4E
00
F5 (Writes A 1)
FB (Data Address Mark)
DATA
F7 (Data Address Mark)
4E
4E

*Write bracketed field 16 times.
**Continue Writing until WD177X-00 interrupts out.
Approx. 668 bytes.

1. Non-Standard Formats

Variations in the recommended formats are possible
to a limited extent if the following requirements are
met:
1) Sector size must be 128, 256, 512 of 1024 bytes.
2) Gap 2 cannot be varied from the recommended
format.
3) 3 bytes of A 1 must be used in MFM.
In addition, the Index Address Mark is not required
for operation by the WD177X-00. Gap 1, 3 and 4
lengths are as short as 2 bytes for WD177X-OO operation, however PLL lock up time, motor speed variation, write-splice area, etc. adds more bytes to each
gap to achieve proper operation. For highest system
reliability use the recommended format.

Gap I
Gap II
*

FM
16 bytes FF
11 bytes FF
6 bytes 00

Gap 111**

10 bytes FF
4 bytes 00

Gap IV

16 bytes FF

32
22
12
3
24
8
3
16

MFM
bytes
bytes
bytes
bytes
bytes
bytes
bytes
bytes

4E
4E
00
A1
4E
00
A1
4E

* Byte counts must be exact.
**Byte counts are minimum, except exactly 3 bytes
of A 1 must be written.

STATUS REGISTER DESCRIPTION (WD1770-00 and WD1772-00 only)
BIT NAME
S7 MOTOR ON
S6 WRITE PROTECT
S5 RECORD
TYPE/SPIN-UP
S4 RECORD NOT
FOUND (RNF)
S3 CRG ERROR
S2 LOST DATAl
BYTE
S1 DATA REQUEST
INDEX

SO BUSY

1-18

MEANING
This bit reflects the status of the Motor On output.
On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates
a Write Protect. This bit is reset when updated.
When set, this bit indicates that the Motor Spin-Up sequence has completed
(6 revolutions) on Type I commands. Type 2 & 3 commands, this bit indicates
record Type. 0
Data Mark. 1
Deleted Data Mark.
When set, it indicates that the desired track, sector, or side were not found. This
bit is reset when updated.
If S4 is set, an error is found in one or more 10 fields; otherwise it indicates
error data field. This bit is reset when updated.
When set, it indicates the computer did not respond to DRQ in one byte time.
This bit is reset to zero when updated. On Type I commands, this bit reflects the
status of the TROO signal.
This bit is a copy of the DRQ output. When set, it indicates the DR is full on a
Read Operation or the DR is empty on a Write operation. This bit is reset to zero
when updated. On Type 1 commands, this bit indicates the status of the IP
signal.
When set, command is under execution. When reset, no command is under
execution.

=

=

F/oppy Disk Controller Devices

STATUS REGISTER SUMMARY (WD1773-00 only)
BIT
S7
S6
S5
S4
S3
S2
S1
SO

ALL TYPE I
COMMANDS
NOT READY
WRITE
PROTECT
HEAD LOADED
SEEK ERROR
CRC ERROR
TRACK 0
INDEX PULSE
BUSY

READ
ADDRESS
NOT READY
0
0
RNF
CRC ERROR
LOST DATA
DRO
BUSY

READ
SECTOR
NOT READY
0

READ
TRACK
NOT READY
0

RECORD TYPE
RNF
CRC ERROR
LOST DATA
LOST
DRO
DRO
BUSY
BUSY

0
0
0
DATA

WRITE
SECTOR
NOT READY
WRITE
PROTECT
WRITE FAULT
RNF
CRC ERROR
LOST DATA
DRO
BUSY

WRITE
TRACK
NOT READY
WRITE
PROTECT
WRITE FAULT
0
0
LOST DATA
DRO
BUSY

STATUS FOR TYPE I COMMANDS (WD1773-00 only)
BIT NAME
S7 NOT READY

MEANING
This bit when set. indicates the drive is not ready. When reset it indicates that the
drive is ready. This bit is an inverted copy of the Ready input and logically "ORed"
with MR.

S6 PROTECTED

When set, indicates Write Protect is activated. This bit is an inverted copy of WRPT
input.

S5 HEAD LOADED

When set, it indicates the head is loaded and engaged. This bit is a logical "and"
of HLD and HLT signals.
When set, the desired track was not verified. This bit is reset to 0 when updated.
CRC encountered in ID field.
When set, indicates Read/Write head is positioned to Track O. This bit is an inverted
copy of the TROO input.
WheJlset, indicates index mark detected from drive. This bit is an inverted copy of
the IP input.
When set, command is in progress. When reset no command is in progress.

S4 SEEK ERROR
S3 CRC ERROR
S2 TRACK 00
S1 INDEX
SO BUSY

STATUS FOR TYPE II AND III COMMANDS (WD1773-00 ONLy)
BIT NAME
S7 NOT READY

MEANING
This bit when set indicates the drive is not ready. When reset, it indicates that the
drive is ready. This bit is an inverted copy of the Ready input and "ORed" with MR.
The Type II and III Commands will not execute unless the drive is ready.

S6 WRITE PROTECT

On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates a
Write Protect. This bit is reset when updated.
On Read Record: It indicates the record-type code from data field address mark.
1 = Deleted Data Mark. 0 = Data Mark. On any Write: Forced to a Zero.
When set, it indicates that the desire track, sector, or side were not found. This bit
is reset when updated.
If S4 is set, an error is found in one or more ID fields; otherwise it indicates error
in data field. This bit is reset when updated.
When set, it indicates the computer did not respond to DRO in one byte time. This
bit is reset to zero when updated.
This bit is a copy of the DRO output. When set, it indicates the DR is full on a Read
Operation or the DR is empty on a Write operation. This bit is reset to zero when
updated.
When set, command is under execution. When reset, no command is under execution.

S5 RECORD TYPE
S4 RECORD NOT
FOUND (RNF)
S3 CRC ERROR
S2 LOST DATA
S1 DATA REOUEST

SO BUSY

Floppy Disk Controller Devices

1-19

=E
c....
.....
.....
>.<

o
o

NOTE

DC ELECTRICAL CHARACTERISTICS

Maximum limits indicate where permanent device
damage occurs. Continuous operation at these limits
is not intended and should be limited to those conditions specified in the DC Operating Characteristics.

MAXIMUM RATINGS
Storage Temperature ............. 55°C (67°F) to
+ 125°C (257°F)
Operating Temperature............0oC (32°F) to
70°C (158°F) Ambient
Maximum Voltage to Any Input
with Respect to Vss ................ + 7V to -0.5V
DC OPERATING CHARACTERISTICS
TA

= 0°C(32°F) to 70°C (158°F), Vss = OV, Vee = +5V
SYMBOL
IlL
IOL
V IH
V IH
V OH
VOL
Po
Rpu
lee

CHARACTERISTIC

± .25V
MAX

MIN

Input Leakage
Output Leakage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Power Dissipation
Internal Pull-Up
Supply Current

UNITS

10
10

JJA
JJA
V
V
V
V
W
JJA
rnA

2.0
0.8
2.4

100
75(Typ)

0.40
.75
1700
150

CONDITIONS

= Vee
= Vee

VIN
VOUT

=

10
-100 JJA
10 = 1.6 mA
VIN

= OV

AC TIMING CHARACTERISTICS
TA

= OOC (32°F) to 70°C (158°F), vss = OV, vCC = + 5V

± .25V

g~LS ___________--;___~x

~'DV_1
R/W _ _

X'-____

VALID

r-'DOH~

--J/~I-~I\\.....----

cs ----~I~~\- tRE- - 7 . ) - 1 - - - - .......f - - - - - - - - t O R R - - - - - - - . - t · 1
ORQ

\'--READ ENABLE TIMING

READ ENABLE TIMING - RE such that: R/W
SYMBOL
tRE
tORR
tov
tOOH

CHARACTERISTIC
RE Pulse Width of CS
ORO Reset from RE
Data Valid from RE
Data Hold from RE
INTRa Reset from RE

= 1, CS = O.
MIN

TYP

MAX

UNITS

CONDITIONS

200
100

300
200
150
8

nsec
nsec
nsec
nsec
JJsec

= 50 pf
CL = 50 pf
CL = 50 pf

200

20

CL

Note: ORO and INTRa reset are from rising edge (lagging) of RE, whereas resets are from falling edge
(leading) of WE. Worst ease service time for ORO is 23.5 JJsec for MFM and 47.5 JJsec for FM.

1-20

Floppy Disk Controller Devices

X

DALS
0-7

i

I

X

VALID

~'DS±'DH~

~

Cs

'SET=j
'\

RiiN

t

AS

-1
I

tWE

;{'

~

1'-

tAH1

AO,A1

tDRW

""-

Y

t

~

ORO

I

/;='HLD

'\

WRITE ENABLE TIMING

WRITE ENABLE TIMING - WE such that: R/W
SYMBOL
t AS
tSET
tAH
tHLD
tWE
tORW
tos
tOH

CHARACTERISTIC
Setup ADDR to CS
Setup RIW to CS _
Hold ADDR from CS
Hold RlW from CS
WE Pulse Width
ORO Reset from WE
Data Setup to WE
Data Hold from WE
I NTRO Reset from WE

= 0, CS = O.
MIN

TYP

MAX

50
0
10
0
200
100

UNITS

CONDITIONS

8

nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
J.lsec

MAX

UNITS

CONDITIONS

3
3

J.lsec

MFM
FM

200

150
0

READ DATA TIMING:
CHARACTERISTIC

MIN

Raw Read Pulse Width

.200
.400

Raw Read Cycle Time

3

Floppy Disk Controller Devices

TYP

J.lsec

1-21

WRITE DATA TIMING:

:E
c
.....
.......

SYMBOL

CHARACTERISTIC

Write Gate to Write Data

.......

><
6

Write Data Cycle Time
Write Gate off from WD

o

twp

1-22

Write Data Pulse Width

MIN

TYP

4
2
4,6,8
4
2
820
690
570
1.38

MAX

UNITS

CONDITIONS

p,sec
p,sec
p,sec
p,sec
p,sec
nsec
nsec
nsec
p,sec

FM
MFM
FM
MFM
Early MFM
Nominal MFM
Late MFM
FM

Floppy Disk Controller Devices

I I----------1f

...c......=E......

VIH

~IIP~
MR

>.<

Ir-----------#t.$

~lr---------""I

o
o
VIH

J.-IMR~
ClK

DIRC

______---'1

STEP IN

STEP

MISCELLANEOUS TIMING

MISCELLANEOUS TIMING:
SYMBOL

CHARACTERISTIC

tC01
tC02
t STP

Clock Duty (low)
CLock Duty (high)
Step Pulse Output

tOIR

Dir Setup to Step

tMR
tiP

Master Reset Pulse Width
Index Pulse Width

Floppy Disk Controller Devices

MIN

TYP

50
50

67
67
4
8
24
48

50
20

MAX

UNITS

nsec
nsec
Jlsec
Jlsec

CONDITIONS

MFM
FM
MFM
FM

Jlsec
Jlsec

1-23

1-24

Floppy Disk Controller Devices

WESTERN
COR

PO

DIGITAL

RAT

ION

WD177X-OO Floppy Disk Formatter/Controller Family
Application Notes
INTRODUCTION

To meet the demand for a low cost compact lSI Floppy Disk Controller device, Western Digital has
developed the WD177X-OO. The WD177X-OO is a NMOS
Floppy Disk Controller device that incorporates the
FD179X, a digital data separator and write
precompensation circuitry all in a single chip. The
device offers soft sector formatting, selectable stepping rates, automatic track seek with verify, and
variable sector lengths. The FD177X-OO comes in a
28-pin dual-in-line package or quad pack and operates
from a single 5 volt only power supply.

During Direct Memory Access (DMA) data transfers
between the WD177X-OO and Host Memory, the Data
Request (DRa) line is used in Data Transfer Control.
This signal also appears as status bit 1 during
Read/Write operations. On Disk Read operations the
DRa is active when an assembled byte is present in
the Data Register, then reset when read by the Host.
If the Host fails to read the Data Register before the
following byte is assembled in the Data Register, the
lost data bit is set in Status Register.
At the completion of every command INTRa is
asserted. INTRa is de-asserted by either reading the
status or by loading the Command Register.

APPLICATIONS

The Mini-Floppy Controller is targeted for the low cost
sector of the disk drive market, where digital data
separation is preferred over analog phase lock loop.
Included in this market are Personal Computers, Portable Computers and Small Business Computers.
FOLLOW ON DEVICES
WD1772-02

The device is the same as the WD1772-00 except for
an enhanced digital data separator.
HOST INTERFACING

Interfacing to a Host processor is accomplished
through the eight bit bi-clirectional Data Access Lines
(DAl) and associated control lines. The DAl is used
to transfer data, status and control words out of or
into WD177X-OO. The DAl having three states enabled
as an output when Chip Select (CS) is active low and
Read/Write (R/W) is high or as input receiver when CS
and R/W is low. When transfer of data with the device
is required by the Host CS is made low. The address
bits AO and A 1 combined with the R/W line select the
register and the direction of data.

Floppy Disk Controller Devices

DISKETTE DRIVE INTERFACING

The WD177X-OO has two modes of operation depending on the state of DDEN, regardless of the state of
DDEN the ClK input remains at 8 MHz. Disk Reads
with sector lengths of 128, 256, 512 and 1024 byte sector in both FM or MFM diskettes is accomplished via
the internal digital data separator. Disk Write operation in MFM on inner tracks may require write
precompensation. Write precompensation is enabled when bit 1 = 0, in the Write command and a
precompensation value of 125 nsec is produced.
The diskettes spindle motor is controlled by bit 3 of
any Type I, II or III command, upon receiving a command with bit 3 = 0, the spin up sequence is
enabled.
GENERAL INFORMATION

A + 5 volt supply ± 5% is used as Vce , and the
clock input requires a free running 50% duty cycle
at 8 MHz ±O.1 %.

1-25

1-26

Floppy Disk Controller Devices

WESTERN
COR

P

0

DIGITAL
o

RAT

N

WD1772-02 Floppy Disk Formatter/Controller
FEATURES

•
•
•

28 PIN DIP
SINGLE 5V SUPPLY
HIGH PERFORMANCE DPLL BUILT-IN DIGITAL DATA
SEPARATOR

•

BUILT·IN WRITE PRECOMPENSATION,
INCREASED TO 187 MS

•
•
•

SINGLE AND DOUBLE DENSITY
MOTOR CONTROL
128, 256, 512 OR 1024 SECTOR LENGTHS

•
•
•

TTL COMPATIBLE
8·BIT BI·DIRECTIONAL DATA BUS
100% PIN COMPATIBLE WITH WD1770·00 AND
WD1772·00
ENHANCED STEP/RATES 2,3,6,12 MS

•

DESCRIPTION
The WD1772·02 is a MOS/LSI device which performs
the functions of a Floppy Disk Formatter/Controller.
It is similar to its predecessor, the FD179X, but also
contains a digital data separator and write
precompensation circuitry. The drive side of the interface needs no additional logic except for buffers/receivers. Designed for single (FM) or double
(MFM) density operation, the device contains a programmable Motor On signal.
The WD1772"()2 is implemented in NMOS silicon gate
technology and is available in a 28 pin dual-in·line.
The WD1772-02 is a low cost version of the FD179X
Floppy Disk Controller/Formatter. It is similar to the
FD179X, but has a built-in digital data separator and
write precompensation circuits.

F/oppy Disk Controller Devices

INTRa
DRO
DDEN

CS
RiW
AO
A1
DAlO
DAl1
DAl2
DAl3
DAl4
DAl5
DAl6
DAl7

WPFff
iP

TRoD
WD
WG
MO

AD

MR

ClK
DIRC
STEP

GND

vcc

PIN DESIGNATION

A single read line (RD, Pin 19) is the only input
required to recover serial FM of MFM data from the
disk drive. The device is designed for control of floppy
disk drives with data rates of 125 KBits/Sec (single
density) and 250 KBits/Sec (double density). In addition, write precompensation of 187 nsec from nominal
is enabled at any point through simple software com·
mands. Another programmable feature, Motor On,
enables the spindle motor automatically prior to
operating a selected drive.
The WD1772"()2 offers stepping rates of 2, 3, 6 and
12 msec. The processor interface consists of an 8-bit
bi-directional bus for transfer of status, data, and commands. All Host communication with the drive occurs
through these lines. They are capable of driving one
standard TTL load or three LS loads.

1-27

C

PIN
NUMBER

......
......

1

CS

•

2

3,4

=E

MNEMONIC

SIGNAL NAME

I/O

FUNCTION

CHIP SELECT

I

RIW

READ/WRITE

I

AO,A1

ADDRESS 0,1

I

A logic low on this input selects the chip and enables
Host communication with the device.
A logic high on this input controls the placement of
data on the DO-D7 lines from a selected register, while
a logic low causes a write operation to a selected
register.
These two inputs select a register to Read/Write data:

...I.

N
0
N

=

5-12

1-28

DAlO-DAl7

DATA ACCESS
LINES
o THROUGH 7
MASTER RESET

I/O

13

MR

14
15
16

Vcc
STEP

GROUND
POWER SUPPLY
STEP

I
0

17

DIRC

DIRECTION

0

18

ClK

CLOCK

I

19

RD

READ DATA

I

20

MO

MOTOR ON

0

21

WG

WRITE GATE

0

22

WD

WRITE DATA

23

TROO

TRACK 00

I

24

iP

INDEX PULSE

I

25

WPRT

WRITE PROTECT

I

GND

=

CS A1 AO
R/W
1
R/W
0
Command Reg
Status Reg
0
0
0
Track Reg
1
Track Reg
0
0
Sector Reg
Sector Reg
0
1
0
Data Reg
1
Data Reg
0
1
Eight-bit bi-directional bus used for transf~f data,
control, or status. This bus is enabled by CS and
RIW. Each line will drive one TTL load.
A logic low pulse on this line resets the device and
initializes the Status Register (internal pull-up).
Ground.
+ 5V ± 5% power supply input.
The Step output contains a pulse for each step of the
drive's RIW head.
The Direction output is high when stepping in towards
the center of the diskette, and low when stepping out.
This input requires a free-running 50% duty cycle clock
(for internal timing) at 8 MHz ±0.1 %.
This active low input is the raw data line containing
both clock and data pulses from the drive.
Active high output used to enable the spindle motor
prior to read, write or stepping operations.
This output is made valid prior to writing on the
diskette.
FM or MFM clock and data pulses are placed on this
line to be written on the diskette.
This active low input informs the WD1772-02 that
the drive's RIW heads are positioned over Track
zero.
This active low input informs the WD1772-02 when the
physical index hole has been encountered on the
diskette.
This input is sampled whenever a Write Command is
received. A logiC low on this line will prevent any Write
Command from executing (internal pull-up).

Floppy Disk Controller Devices

PIN
NUMBER

MNEMONIC

SIGNAL NAME

I/O

FUNCTION
This input pin selects either single (FM) or double
(MFM) density. When DDEN = 0, double density is
selected (internal pull-up).
This active high output indicates that the Data Register
is full (on a Read) or empty (on a Write operation).
This active high output is set at the completion of any
command, is reset by a read of the Status Register.

26

DDEN

DOUBLE
DENSITY
ENABLE

I

27

DRQ

DATA REQUEST

0

28

INTRQ

INTERRUPT
REQUEST

0

5'/4"

H

0
S
T

0

I
N

P
P
Y

T
E
A

D

F

F
L

A

A

I
V

C

E

E

WD1772-02 SYSTEM BLOCK DIAGRAM
ARCHITECTURE
The primary sections of the Floppy Disk Formatter are
the parallel processor interface and the Floppy disk
interface.
Data Shift Register - This 8-bit register assembles
serial data from the Read Data input (RD) during
Read operations and transfers serial data to the Write
Data output during Write operations.
Data Register - This 8-bit register is used as a holding
register during Disk Read and Write operations. In
disk Read operations, the assembled data byte is
transferred in parallel to the Data Register from the
Data Shift Register. In Disk Write operations, information is transferred in parallel from the Data
Register to the Data Shift Register.
When executing the Seek Command, the Data
Register holds the address of the desired Track position. This register is loaded from the DAL and gated
onto the DAL under processor control.

ped in and decremented by one when the head is
stepped out (towards track 00). The contents of the
register are compared with the recorded track number
in the ID field during disk Read, Write, and Verify
operations. The Track Register can be loaded from
or transferred to the DAL This Register is not loaded
when the device is busy.
Sector Register (SR) - This 8-bit register holds the
address of the desired sector position. The contents
of the register are compared with the recorded sector number in the ID field during disk Read or Write
operations. The Sector Register contents can be
loaded from or transferred to the DAL. This register
is not loaded when the device is busy.
Command Register (CR) - This 8-bit register holds the
command presently being executed. This register is
not loaded when the device is busy unless the new
command is a forced interrupt. The Command
Register is loaded from the DAL, but not read onto
the DAL.
Status Register (STR) - This 8-bit register holds device
Status information. The meaning of the Status bits
is a function of the type of command previously
executed. This register is read onto the DAL, but not
loaded from the DAL.
CRC Logic - This logic is used to check or to generate
the 16-bit Cyclic Redundancy Check (CRG). The
polynomial is:
G(x)

=

X

16

+

X

12

+

x5

+ 1.

The CRC includes all information starting with the
address mark and up to the eRC characters. The CRC
Register is preset to ones prior to data being shifted
through the circuit.
Arithmetic/Logic Unit (ALU) - The ALU is a serial comparator, incrementer, and decrementer and is used
for register modification and comparisons with the
disk recorded ID field.

Track Register - This 8-bit register holds the track
number of the current Read/Write head position. It
is incremented by one every time the head is step-

Floppy Disk Controller Devices

1-29

(DAL)

:ec

.....

"o"•
N
N

DRQ

WG

INTRQ

WPRT

MR

TP

~

II

R/W

COMPUTER
INTERFACE
CONTROL

AO

CONTROL

PLA
CONTROL
(240 X 19)

..

CONTROL
II

DISK
INTERFACE
CONTROL

A1

TROO
STEP
DIRC
(MOTOR ON)

CLK(S-MHZ)

cmrn
FIGURE 1. WD1772-o2 BLOCK DIAGRAM

Timing and Control - All computer and Floppy Disk
interface controls are generated through this logic.
The internal device timing is generated from an external crystal clock. The WD1772-02 has two different
modes of operation according to the state of
DDEN.
When DDEN = 0, double density (MFM) is enabled.
1, single density is enabled.
When DDEN
AM Detector - The address mark detector detects ID,
data, and index address marks during read and write
operations.

=

Data Separator - A digital phase lock loop (DPLL) of
type 2, second order performs the data separator
function. DPLL has a filter transfer function used to
remove jitter effects thereby achieving adequate window margin. The algorithm used gives performance
equal to second order analog deSigns.
DPLL performance specifications are as follows:

1-30

Fc capture range ± 6% (min)
TI lock response 4 bytes OOH (max)
Wt window tolerance 50% for 10E-9 error rate
PROCESSOR INTERFACE

The interface to the processor is accomplished
through the eight Data Access Lines (DAL) and
associated control signals. The DAL are used to
transfer Data, Status, and Control words out of, or
into the WD1772-02. The DAL are three state buffers
that are enabled as output drivers when CS and
R/W = 1 are active or act as input receivers when CS
and RW = 0 are active.
When transfer of data with the Floppy Disk Controller
is required by the Host processor, the device address
is decoded and CS is made low. The address bits A 1
and AO, combined with the signal R/W during a
Read operation or Write operation are interpreted as
selecting the following registers:

Floppy Disk Controller Devices

A1 - AO READ (R/W = 1)
0
0 Status Register
0
1 Track Register
1
0 Sector Register
1
1 Data Register

WRITE (RlW = 0)
Command Register
Track Register
Sector Register
Data Register

After any register is written to, the same register cannot be read from until 16 J..Lsec in MFM or 32 J..Lsec in
FM have elapsed.
During Direct Memory Access (DMA) types of data
transfers between the Data Register of the WD1772-02
and the processor, the Data Request (DRa) output
is used in Data Transfer control. This signal also
appears as status bit 1 during Read and Write
operations.
On Disk Read operations, the Data Request bit is activated (set high) when an assembled serial input byte
is transferred in parallel to the Data Register. This bit
is cleared when the Data Register is read by the processor. If the Data Register is read after one or more
characters are lost, by having new data transferred
into the register prior to processor readout, the lost
Data bit is set in the Status Register. The Read operations continue until the end of sector is reached.
On Disk Write operations, the Data Request bit is activated when the Data Register transfers its contents
to the Data Shift Register, and requires a new data
byte. It is reset when the Data Register is loaded with
new data by the processor. If new data is not loaded
at the time the next serial byte is required by the Floppy Disk, a byte of zeroes is written on the diskette
and the lost Data bit set in the Status Register.
At the completion of every command, an INTRa is
generated. INTRa is reset by either reading the Status
Register or by loading the Command Register with
a new command. In addition, INTRa is generated if
a Force Interrupt Command condition is met.
The WD1772-02 has two modes of operation according to the state DDEN. When DDEN = 1, single
density is selected. In either case, the ClK input is
at 8 MHz.
GENERAL DISK READ OPERATIONS
Sector lengths of 128, 256, 512 or 1024 are obtainable
in either FM or MFM formats. For FM. DDEN
is placed to logical 1. For MFM formats, DDEN is
placed to a logical O. Sector lengths are determined
at format time by the fourth byte in the ID field.
SECTOR LENGTH TABLE
SECTOR LENGTH
NUMBER OF BYTES
FIELD (HEX)
IN SECTOR (DECIMAL)
00
01
02
03

Floppy Disk Controller Devices

The number of sectors per track for the WD1772-02
are from 0 to 244. The number of tracks for the
WD1772-02 are 0 to 244.
GENERAL DISK WRITE OPERATION
When writing on the diskette, the WG output is activated, allowing current to flow into the Read/Write
head. As a precaution to erroneous writing, the first
data byte is loaded into the Data Register in response
to a Data Request from the device before the WG is
activated.
Writing is inhibited when the WPRT input is asserted, in which case any Write Command is
immediately terminated, an interrupt is generated and
the Write Protect Status bit is set.
For Write operations, the WD1772-02 provides WG to
enable a Write condition, and WD which consists of
a series of active high pulses. These pulses contain
both Clock and Data information in FM and MFM. WD
provides the unique missing clock patterns for recording Address Marks.
On the WD1772-02, the Precomp Enable bit in Write
Commands allows automatic Write precompensation
to take place. The outgoing Write Data stream is
delayed or advanced from nominal by 187 nsec according to the following table:
PATTERN
1
1
0
1
0
0
0
1
0
0

X
X

0
1
1
0

MFM

FM

Early
late
Early
late

N/A
N/A
N/A
N/A

t_ Next Bit to be sent
- - - Current Bit sendmg
' - - - - - Previous Bits sent

L........l

I

Precompensation is typically enabled on the innermost tracks where bit shifts usually occur and bit
density is at its maximum.
COMMAND DESCRIPTION
The WD1772-02 accepts 11 commands. Command
words are only loaded in the Command Register when
the Busy Status bit is off (Status bit 0). The one exception is the Force Interrupt Command. Whenever
a command is being executed, the Busy Status bit
is set. When a command is completed, an interrupt
is generated and the Busy status bit is reset. The
Status Register indicates whether the completed
command encountered an error or was fault free.
Commands are divided into four types and are summarized in the following pages.

128
256
512
1024

1-31

COMMAND SUMMARY

TYPE COMMAND
I
I
I
I
I

Restore
Seek
Step
Step-in
Step-out
Read Sector
Write Sector
Read
Address
Read Track
Write Track
IV Force
Interrupt

"
'""
''""

7

6

5

0
0
0
0
0
1
1

0
0
0

0
0
1
0

0
0

0

1
1
1

1

0

1
1

1
1

1

1

0

1
1

1
1

BITS
4 3

2

1

0
1
u
u
u
m
m

h
h
h
h
h
h
h

V
V
V
V
V
E
E

r1
r1
r1
r1
r
0
P

ao

0
0

1

h
h
h

E
E
E

0
0
P

0
0
0

1

13

12

11

10

TYPE IV COMMANDS

FLAG SUMMARY

= Motor On Flag (Bit 3)

h
h

= 1, Disable Spin-up Sequence

=

0, Enable Spin-up Sequence

WD1772-Q2

1

1

u
u
u

o
1
o
1

= Update Flag (Bit 4)
= 0, No Update
= 1, Update Track Register

TYPE" & III COMMANDS
m
m
m
H
H
H

=

Multiple Sector Flag (Bit 4)

=

1, Multiple Sector

= 0, Single Sector

= Motor On Flag (Bit 3)
= 0, Enable Spin Up Sequence

= 1, Disable Spin Up Sequence
ao = Data Address Mark (Bit 0)
ao
ao
E
E
E
P
P
P

1-32

=
=

Write Normal Data Mark
1, Write Deleted Data Mark

= 15ms Settling Delay (Bit 2)
=
=
=
=

0, No Delay
1, Add 15ms Delay
Write Precompensation (Bit 1)
O,Enable Write Precomp

= 1,Disable Write Precomp

12

=
=
=

13

=

10
11

13-10

1, Not Used
1, Not Used
1, Interrupt on Index Pulse
1, Immediate Interrupt

=

0, Terminate without interrupt

TYPE I COMMANDS
The Type I Commands include the Restore, Seek,
Step, Step-in, and Step-Out Commands. Each of the
Type I Commands contains a rate field (rO,r1), which
determines the stepping motor rate.

The Direction signal is active high when stepping in
and low when stepping out. The Direction signal is
valid 24 ",sec before the first stepping pulse is
generated.

= Verify Flag (Bit 2)
V = 0, No Verify
V = 1, Verify on Destination Track
r1' ro = Stepping Rate (Bits 1,0)
V

o
o

ro
ro
ro
ro
ro
0

13-1 0 Interrupt Condition (Bits 3-0)

A 4 ",sec (MFM) or 8 ",sec (FM) pulse is provided as
an output to the drive. For every step pulse issued,
the drive moves one track location in a direction determined by the direction output. The chip steps the drive
in the same direction it last stepped unless the command changes the direction.

TYPE I COMMANDS

h

°

6 ms
12 ms
2 ms
3 ms

After the last directional step, an additional 15 msec
of head settling time takes place if the Verify flag is
set in Type I Commands. There is also a 15 msec
head settling time if the E flag is set in any Type II
or III Command.
When a Seek, Step, or Restore Command is executed,
an optional verification of Read/Write head position
can be performed by setting bit 2 (1/ = 1) in the command word to a logic 1, The verification operation
begins at the end of the 15 msec settling time after
the head is loaded against the media. The track
number from the first encountered ID Field is com·
pared against the contents of the Track Register. If
the track numbers compare and the ID Field CRC is
correct, the verify operation is complete and an INTRQ
is generated with no errors. If there is a match but
not a valid CRC, the CRC error status bit is set (Status
Bit 3), and the next encountered ID Field is read from
the disk for the verification operation.
The WD1772-02 finds an ID Field with correct track
number and correct CRC within 5 revolutions of the
media, or the seek error is set and an INTRQ is
generated. If V = 0, no verification is performed.
On the WD1772-02, all commands, except the Force
Interrupt Command, are programmed via the h Flag
to delay for spindle motor start up time. If the h Flag
is not set and the MO signal is low when a command
is received, the WD1772-02 forces MO to a logic 1 and
waits 6 index pulses before executing the command.
At 300 RPM, this guarantees a one second spindle
start up time. If after finishing the command, the
device remains idle for 9 revolutions, the MO

Floppy Disk Controller Devices

signal goes back to a logic O. If a command is issued
while MO is high, the command executes
immediately, defeating the 5 revolution start up. This
feature allows consecutive Read or Write commands
without waiting for motor start up each time; the
WD1n2'{)2 assumes the spindle motor is up to speed.

RESTORE (SEEK TRACK 0)

Upon receipt of this command, the Track 00 (TROO)
input is sampled. If TROO is active low, indicating
the Read/Write head is positioned over track 0, the
Track Register is loaded with zeroes and an interrupt
is generated. If TROO is not active low, stepping
pulses at a rate specified by the r1,rO field are issued
until the TROO input is activated.

SET DIRECTION

-HOTA

OTOTR

NO

TYPE I COMMAND FLOW

Floppy Disk Controller Devices

TYPE I COMMAND FLOW

1-33

At this time, the Track Register is loaded with
zeroes and an interrupt is generated. If the TROO
input does not go active low after 255 stepping pulses,
the W01772-02 terminates operation, interrupts, and
sets the Seek Error status bit, providing the V flag
is set. A verification operation also takes place if the
V flag is set. The h bit allows the Motor On option
at the start of a command.
SEEK

This command assumes that the Track Register contains the track number of the current position of the
ReadlWrite head and the Oata Register contains the
desired track number. The W01772-02 updates the
Track Register and issues stepping pulses in the
appropriate direction until the contents of the Track
Register are equal to the contents of the Oata
Register (the desired track location). A verification
operation takes place if the V flag is on. The h bit

VERIFY
SEQUENCE

allows the Motor On option at the start of the command. An interrupt is generated at the completion of
the command. Note: When using multiple drives, the
Track Register is updated for the drive selected before
seeks are issued.
STEP

Upon receipt of this command, the W01772-02 issues
one Stepping Pulse to the disk drive. The stepping
motor direction is the same as in the previous step
command. After a delay determined by the r1,rO field,
a verification takes place if the V flag is on. If the U
flag is on, the Track Register is updated. The h bit
allows the Motor On option at the start of the command. An interrupt is generated at the completion of
the command.
STEP-IN

Upon receipt of this command, the W01772-02 issues
one Stepping Pulse in the direction towards the inner most track. If the U flag is on, the Track Register
is incremented by one. After a delay determined by
the r1,rO field, a verification takes place if the V flag
is on. The h bit allows the Motor On option at the start
of the command. An interrupt is generated at the completion of the command.
STEP-OUT

Upon receipt of this command, the W01772-02 issues
one stepping pulse in the direction towards track o.
If the U flag is on, the Track Register is decremented
by one. After delay determined by the r1,rO field, a
verification takes place if the V flag is on. The h bit
allows the Motor On option at the start of the command. An interrupt is generated at the completion of
the command.
TYPE" COMMANDS

The Type II Commands are the Read Sector and Write
Sector commands. Prior to loading the Type II Command into the Command Register, the computer
loads the Sector Register with the desired sector
number. Upon receipt of the Type II command, the
Busy Status bit is set. If the E flag
1, the command
executes after a 15 msec delay.

=

SET

cRe
ERROR

INTRQ
RESET BUSY

TYPE I COMMAND FLOW.

1-34

(When an 10 field is located on the disk, the
W01772-02 compares the Track Number on the 10
field with the Track Register. If there is not a match,
the next encountered 10 field is read and a comparison is again made). If there is a match, the Sector Number of the 10 field is compared with the Sector
Register. If there is no Sector match, the next
encountered 10 field is read off the disk and comparisons again made. If the 10 field CRC is correct,
the data field is located and is either written into, or
read from, depending upon the command.

Floppy Disk Controller Devices

generated at the completion of the command. If m
= 1, multiple records are read or written with the Sector Register internally updated so that an address
verification occurs on the next record. The WD1772-02
continues to read or write multiple records and
updates the Sector Register in numerical ascending
sequence until the Sector Register exceeds the
number of sectors on the track or until the Force Interrupt Command is loaded into the Command Register,
which terminates the command and generates an
interrupt.
For example: If the WD1772-02 is instructed to read
sector 27 and there are only 26 on the track, the Sector Register exceeds the number available. The
WD1772-02 searches for 5 disk revolutions, interrupts
out, resets Busy, and sets the Record Not Found
Status Bit.
READ SECTOR

SETMO
WAIT
61NDEX PULSES

4

INTRQ, RESET BUSY
SET WRITE PROTECT

Upon receipt of the Read Sector Command, the Busy
Status Bit is set, then when an ID field is encountered
that has the correct track number, correct sector
number, and correct CRC, the data field is presented
to the computer. The Data Address Mark of the data
field is found with 30 bytes in single density and 43
bytes in double density of the last ID field CRC byte.
If not, the ID field is searched for and verified again
followed by the Data Address Mark search. If, after
five revolutions the DAM is not found, the Record Not
Found Status Bit is set and the operation is terminated. When the first character or byte of the data
field is shifted through the DSR, it is transferred to
the DR, and DRo is generated. When the next byte
is accumulated in the DSR, it is transferred to the DR
and another DRo is generated. If the computer has
not read the previous contents of the DR before a new
character is transferred, that character is lost and the
Lost Data Status Bit is set. This sequence continues
until the complete data field is inputted to the computer. If there is a CRC error at the end of the data
field, the CRC Error Status bit is set, and the command is terminated (even if it is a multiple record
command).
At the end of the Read operation, the type of Data
Address Mark encountered in the data field is
recorded in the Status Register (Bit 5) as shown:
STATUS BIT 5

1

TYPE II COMMAND

The WD1772-02 finds an ID field with a Track number,
Sector number, and CRC within 5 revolutions of the
disk, or, the Record Not Found Status bit is set (Status
Bit 4) and the command is terminated with an INTRa.
Each of the Type II Commands contains an m flag
which determines if multiple records (sectors) are read
or written, depending upon the command. If m = 0,
a single sector is read or written and an interrupt is

Floppy Disk Controller Devices

o

Deleted Data Mark
Data Mark

WRITE SECTOR

Upon receipt of the Write Sector Command, the Busy
Status Bit is set. When an ID field is encountered that
has the correct track number, correct sector number,
and correct CRC, a DRo is generated. The WD1772-02
counts off 11 bytes in single density and 22 bytes in
double density from the CRC field and the WG

1-35

INTRa, RESET BUSY
SET RECORD·NOT FOUND

NO

NO

NO

SET CRC
STATUS ERROR

READ

TYPE II COMMAND

ouput is made active if the ORO is serviced (Le., the
DR is loaded by the computer). If ORO is not serviced,
the command is terminated and the Lost Data Status
Bit is set. If the ORO is serviced, the WG is made
active and six bytes of zeroes in single density and
12 bytes in double density are written on the disk. The
Data Address Mark is then written on the disk as determined by the
field of the command as shown:

ao

1-36

80

1

o

DATA ADDRESS MARK (BIT 0)

Deleted Data Mark
Data Mark

The WD1772-02 writes the data field and generates
ORO's to the computer. If the ORO is not serviced
in time for continuous writing, the Lost Data Status

Floppy Disk Controller Devices

READ SECTOR
SEQUENCE

NO

SET DATA
LOST

INTRO, RESET BUSY
SET CRC ERROR
INTRO RESET BUSY

TYPE II COMMAND

Floppy Disk Controller Devices

1-37

WRITE
SEQUENCE

SET DATA LOST
WRITE BYTE
OF ZEROES

NO

TYPE II COMMAND

138

Floppy Disk Controller Devices

Bit is set and a byte of zeroes is written on the disk.
The command is not terminated. After the last data
byte is written on the disk, the two·byte CRC is computed internally and written on the disk fOllowed by
one byte of logic ones in FM or in MFM. The WG output is then deactivated. INTRa sets 24 ",sec (MFM)
after the last CRC byte is written. For partial sector
writing, the proper method is to write data and fill the
balance with zeroes.
TYPE III COMMANDS
Read Address

Upon receipt of the Read Address Command, the
Busy Status Bit is set. The next encountered ID field
is then read in from the disk, and six data bytes of
the ID field are assembled and transferred to the DR,
and a DRa is generated for each byte. The six bytes
of the ID field are shown:
TRACK
SIDE
SECTOR SECTOR CRC
ADDR NUMBER ADDR LENGTH
1
1

2

4

3

5

CRC
2
6

Although the CRC characters are transferred to the
computer, the WD1772-02 checks for validity and the
CRC error status bit is set if there is a CRC error. The
Track Address of the ID field is written into the sector register so that a comparison can be made by the
user. At the end of the operation, an interrupt is
generated and the Busy Status is reset.
Read Track
Upon receipt of the Read Track Command, the head
is loaded and the Busy Status bit is set. Reading
starts with the leading edge of the first encountered
index pulse and continues until the next index pulse.
All Gap, Header, and data bytes are assembled and
transferred to the data register and DRa's are
generated for each byte. The accumulation of bytes
is synchronized to each address mark encountered.
An interrupt is generated at the completion of the
command.
This command has several characteristics which
make it suitable for diagnostic purposes. These
characteristics are: no CRC checking is performed;
DATA PATTERN
IN DR (HEX)
00 thru F4
F5
F6
F7
F9 thru FB
FC
FD
FE
FF

--

gap information is included in the data stream; and
the Address Mark Detector is on fer the duration of
the command. Because the AM detector is always
on, write splices or noise may cause the chip to look
for an AM.
The ID AM, ID field, ID CRC bytes, DAM, Data, and
Data CRC Bytes for each sector are correct. The Gap
Bytes may be read incorrectly during write-splice time
because of synchronization.
WRITE TRACK FORMATTING THE DISK
Data and gap information are provided at the computer interface. Formatting the disk is accomplished by positioning the head over the desired track
number and issuing the Write Track Command.
Upon receipt of the Write Track Command, the Busy
Status Bit is set. Writing starts with the leading edge
of the first encountered Index Pulse and continues
until the next Index Pulse, at which time the interrupt
is activated. The Data Request is activated im-·
mediately upon receiving the command, but writing
does not start until after the first byte is loaded into
the Data Register. If the DR is not loaded within three
byte times, the operation is terminated making the
device Not Busy, the lost Data Status Bit is set, and
the interrupt is activated. If a byte is not present in
the DR when needed, a byte of zeroes is substituted.
This sequence continues from one Index Pulse to the
next. Normally, whatever data pattern appears in the
Data Register is written on the disk with a normal
clock pattern. However, if the WD1772-02 detects a
data pattern of F5 through FE in the Data Register,
this is interpreted as Data Address Marks with missing clocks or CRC generation.
The CRC generator is initialized when any data byte
from F8 to FE is transferred from the DR to the DSR
in FM or by receipt of F5 in MFM. An F7 pattern
generates two CRC characters in FM or MFM. As a
consequence, the patterns F5 through FE do not appear in the gaps, data field, or ID fields. Also, CRC's
are generated by an F7 pattern.
Disks are formatted in IBM 3740 or System 34 formats
with sector lengths of 128, 256, 512, or 1024 bytes.

IN FM (DDEN = 1)
Write 00 thru F4 with ClK = FF
Not Allowed
Not Allowed
Generate 2 CRC bytes
Write F8 thru FB, ClK = C7, Preset
CRC
Write FC with ClK = D7
Write FD with ClK = FF
Write FE, ClK = C7, Preset CRC
Write FF with ClK = FF

--

IN MFM (DDEN = 0)
Write 00 thru F4, in MFM
Write A1 * in MFM, Present CRC
Write C2** in MFM
Generate 2 CRC bytes
Write
Write
Write
Write
Write

F8 thru FB, in MFM
FC in MFM
FD in MFM
FE in MFM
FF in MFM

*Missing clock transition between bits 4 and 5.
**Missing clock transition between bits 3 and 4.

Floppy Disk Controller Devices

1-39

...=E.....c
.....
N

o•
N

=E
....c
......
......

N

o•
N

DELAY 6
INDEX PULSES

NO

SETINTRQ
LOST DATA
RESET BUSY

TYPE III COMMAND WRITE TRACK

1-40

Floppy Disk Controller Devices

:E

c
.....
......
......
N

o•
N

WRITE 2 CRC
CHARS. ClK
FF

=

WRITE FC
ClK :: 07

WRITE FD, FE OR
FB·F9, ClK :: C7
INITIALIZE CRC

WRITE
BYTE OF ZEROES
SET DATA lOST

WRITE A1 IN MFM
WITH MISSING
CLOCK INITIALIZE
CRC

WRITE C2 IN MFM
WITH MISSING
CLOCK

WRITE 2 CRC
CHARS.

TYPE III COMMAND WRITE TRACK

Floppy Disk Controller Devices

1-41

TYPE IV COMMANDS
The Forced Interrupt Command is used to terminate
a multiple sector read or write command or to ensure
Type I status in the Status Register. This command
is loaded into the Command Register at any time. If
there is a current command under execution, (Busy
Status Bit set), the command is terminated and the
Busy Status Bit reset.
The lower four bits of the command determine the
conditional interrupt as follows:

=
=

10
11
12 =
13 =

Not used
Not Used
Every Index Pulse
Immediate Interrupt

The conditional interrupt is enabled when the cor·
responding bit positions of the command (1 3-1 0) are
set to a 1. When the condition for interrupt is met,
the INTRa line goes high signifying that the condition specified has occurred. If 13-1 0 are all set to zero
(Hex ~O), no interrupt occurs but any command
presently under execution is immediately terminated.
When using the immediate interrupt condition (13 =
1), an interrupt is immediately generated and the current command terminated. Reading the status or
writing to the command register does not
automatically clear the interrupt. The Hex DO is the
only command that enables the immediate interrupt
(Hex 08) to clear on a subsequent load Command
Register or Read Status Register operation. Follow
a Hex 08 with DO command.
Wait 16 J-Isec (double density) or 32 J-Isec (single density) before issuing a new command after issuing a
forced interrupt. Loading a new command sooner
than this nullifies the forced interrupt.
Forced interrupt stops any command at the end of
an internal micro-instruction and generates INTRa
when the specified condition is met. Forced interrupt
waits until ALU operations in progress are complete
(CRC calculations, compares, etc.).
Status Register
Upon receipt of any command, except the Force Interrupt Command, the Busy Status Bit is set and the rest
of the status bits are updated or cleared for the new
command. If the Force Interrupt Command is received
when there is a current command under execution,
the Busy Status Bit is reset, and the rest of the status
bits are unchanged. If the Force Interrupt Command
is received when there is not a current command
under execution, the Busy Status Bit is reset and the
rest of the status bits are updated or cleared. In this
case, Status reflects the Type I commands.
The user has the option of reading the Status Register
through program control or using the ORa line with
OMA or interrupt methods. When the Data Register
is read, the ORa bit in the Status Register and the
ORa line are automatically reset. A write to the Data
Register also causes both ORa's to reset.

user program to determine when a command is complete, in lieu of using the INTRa line. When using the
INTRa, a Busy Status check is not recommended
because a read of the Status Register to determine
the condition of busy resets the INTRa line.
The format of the Status Register is shown below:
(BITS)
7
S7

1 6 -r 5 1 4 1 3 I 2 I 1 I 0
I S6 I S5 I S4 I S3 I S2 I S1 I SO

Because of internal sync cycles, certain time delays
are observed when operating under programmed I/O,
as shown.
Delay Req'd.
MFM
FM

Operation

Next Operation

Write to
Command Reg.

Read Busy Bit
(Status Bit 0)

48J-1sec 24J-1sec

Write to
Command Reg.

Read Status
Bits 1-7

64J-1sec 32J-1sec

Write
Register

Read Same
Register

32J-1sec 16J-1sec

RECOMMENDED· 128 BYTES/SECTOR
The recommended single-density format with 128
bytes/sector is shown below. In order to format a
diskette, the user issues the Write Track Command,
and loads the Data Register with the following values.
For every byte to be written, there is one Data
Request.
NUMBER
OF BYTES
~

6
1
1
1
1
1
1
11
6
1
128
1
~

369* *

HEX VALUE OF BYTE WRITTEN
FF (or 00)
00
FE (10 Address Mark)
Track Number
Side Number (00 or 01)
Sector Number (1 thru 1A)
00 (Sector Length)
F7 (2 CRC's written)
FF (or 00)
00
FB (Data Address Mark)
Data (IBM uses E5)
F7 (2 CRC's written)
FF (or 00)
FF (or 00)

*Write bracketed field 16 times.
**Continue writing until W01772-02 interrupts out.
Approx. 369 bytes.

The Busy Bit in the status may be monitored with a

1-42

Floppy Disk Control/er Devices

:n

.g
~

o
~

g
:::J

aiji=
..,

n

~J~~

~

____ _

I"

REPEATED
FOR EACH SECTOR

_I

:So

o

40 BYTES 6 BYTES
'FF'
'00'

m

ID
'FE'

TRACK

SIDE

1#

1#

SECTOR LENGTH

1#

1#
---

CRC
1

CRC
2

11 BYTES
'FF'

6 BYTES
'00'

DATA
ADR
MARK

USER DATA
128 BYTES

CRC
1

10 BYTES
'FF'

CRC
2

- -

~-------------------IDFIELD--------------------~

~-----------DATA

FIELD--------.........

WRITE GATE

-

L __

SINGLE DENSITY FORMAT

INDEX
PULSE

____ _

REPEATED
FOR EACH SECTOR

14

I

60 BYTES 12 BYTES 3 BYTES ID TRACK
#
'00'
'A1'
'FE'
'4E'

I

SIDE
#

_I

SECTOR LENGTH CRG GRG 22 BYTES 12 BYTES 3 BYTES ID
'FB'
#
'00'
'A1'
'4E'
1
#
2

InC'CI n

I

I

USER DATA
256 BYTES
nATA

~Ir-I

r""\_

GRG
1

GRG
2
--

24 BYTES
'4E'

!

WRITE GATE - - - - - - - '

DOUBLE DENSITY FORMAT
......

t

~O-~ll~aM

256 BYTES/SECTOR

1. Non-Standard Formats

Shown above is the recommended dual-density format with 256 bytes/sector. In order to format a
diskette, the user issues the Write Track Command
and loads the Data Register with the following values.
For every byte to be written, there is one data request.

Variations in the recommended formats are possible
to a limited extent if the following requirements are
met:
1) Sector size must be 128, 256, 512 of 1024 bytes.
2) Gap 2 cannot be varied from the recommended
format.
3) 3 bytes of A1 must be used in MFM.

NUMBER
OF BYTES

,.§!)
12

3
1
1
1
1
1
1
22
12

3
1
256
1
24
668**

HEX VALUE OF BYTE WRITTEN
4E
00
F5 (Writes A 1)
FE (10 Address Mark)
Track Number (0 thru 4C)
Side Number (0 or 1)
Sector Number (1 thru 1A)
01 (Sector Length)
F7 (2 CRC's written)
4E
00
F5 (Writes A1)
FB (Data Address Mark)
DATA
F7 (Data Address Mark)
4E
4E

*Write bracketed field 16 times.
* *Continue Writing until WD1772-02 interrupts out.
Approx. 668 bytes.

In addition, the Index Address Mark is not required
for operation by the WD1772-02. Gap 1, 3 and 4
lengths are as short as 2 bytes for WD1772-02 operation, however PLL lock up time, motor speed variation, write-splice area, etc. adds more bytes to each
gap to achieve proper operation. For highest system
reliability, use the recommended format.

Gap I
Gap II
*

FM
16 bytes FF
11 bytes FF
6 bytes 00

Gap 111**

10 bytes FF
4 bytes 00

Gap IV

16 bytes FF

MFM
32 bytes 4E
22 bytes 4E
12 bytes 00
3 bytes A1
24 bytes 4E
8 bytes 00
3 bytes A1
16 bytes 4E

* Byte counts must be exact.
**Byte counts are minimum, except exactly 3 bytes
of A 1 must be written.

STATUS REGISTER DESCRIPTION
BIT NAME

MEANING

S7 MOTOR ON
S6 WRITE PROTECT

This bit reflects the status of the Motor On output.
On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates
a Write Protect. This bit is reset when updated.

S5 RECORD
TYPE/SPIN-UP

When set, this bit indicates that the Motor Spin·Up sequence has completed
(5 revolutions) on Type I commands. Type 2 & 3 commands, this bit indicates record
Type. 0 = Data Mark. 1 = Deleted Data Mark.
When set, it indicates that the desired track, sector, or side were not found. This
bit is reset when updated.
If S4 is set, an error is found in one or more 10 fields; otherwise it indicates
error data field. This bit is reset when updated.
When set, it indicates the computer did not respond to DRQ in one byte time.
This bit is reset to zero when updated. On Type I commands, this bit reflects the
status of the TROO signal.
This bit is a copy of the DRQ output. When set, it indicates the DR is full on a
Read Operation or the DR is empty on a Write operation. This bit is reset to zero
when updated. On Type 1 commands, this bit indicates the status of the IP
signal.
When set, command is under execution. When reset, no command is under
execution.

S4 RECORD NOT
FOUND (RNF)
S3 CRC ERROR
S2 LOST DATN
BYTE
S1 DATA REQUEST
INDEX

SO BUSY

1-44

Floppy Disk Controller Devices

NOTE

DC ELECTRICAL CHARACTERISTICS

Maximum limits indicate where permanent device
damage occurs. Continuous operation at these limits
is not intended and should be limited to those con·
ditions specified in the DC Operating Characteristics.

MAXIMUM RATINGS
Storage Temperature .......... - 55°C( - 67°F) to
+ 125°C (257°F)
Operating Temperature ............. OOC(32°F) to
70°C (158°F) Ambient
Maximum Voltage to Any Input
with Respect to Vss ........... + 7V to - 0.5V

DC OPERATING CHARACTERISTICS

TA = 0°C(32°F) to 70°C (158°F), Vss = OV, Vcc = +5V ± .25V
CHARACTERISTIC

SYMBOL

IlL
10L
VIH
VIH
VOH
VOL
Po
Rpu
Icc

Input Leakage
Output Leakage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Power Dissipation
Internal Pull·Up
Supply Current

MIN

MAX

UNITS

CONDITIONS

10
10

J.LA
J.LA
V
V
V
V
W
J.LA
rnA

VIN = Vcc
VOUT = Vcc

2.0
0.8
2.4

100
75(fyp)

0.40
.75
1700
150

10 = ·100 J.LA
10 = 1.6 rnA
VIN = OV

DPLL SPECIFICATION

Fe Capture Range ± 6% (min)
TI Lock Response 4 bytes 00 hex (max)
WT Window Tolerance 50% for 10E·9 Error Rate (min)

Floppy Disk Controller Devices

1-45

AC TIMING CHARACTERISTICS
TA

= OOC (32°F) to 70°C (158°F), vss = OV, vCC = + 5V

± .25V

g~LS ___________---::---__~X

X'-___

VALID

~IDV_1

r-IDOH~

1I

I\~--

R/W _ _- - - - - J

~----------~I~:==_IRE==~~7~---------

ORO

..

~If_-------IORR-------~·I

----------------------------------------~

\'---READ ENABLE TIMING

READ ENABLE TIMING - RE such that: RIW
SYMBOL
tRE
tORR
tov
tOOH

CHARACTERISTIC
RE Pulse Width of CS
ORO Reset from RE
Data Valid from RE
Data Hold from RE
INTRO Reset from RE

= 1, CS = O.
MIN

TYP

MAX

UNITS

300
200
150
8

nsec
nsec
nsec
nsec
Il sec

200
200
100
20

CONDITIONS

= 50 pf
CL = 50 pf
C L = 50pf

CL

Note: Worst case service time for ORO is 23.5 Ilsec for MFM and 47.5 Ilsec for FM.

1-46

Floppy Disk Controller Devices

X

DALS
0-7

~'DS

I

Cs

'SET~

'\

R/W

t

AS

-1
I

~

N

,,'HLD

tAH1

AO,Al

tDRW

.......

N

o•

*Y

~

I

=E

c
....
.......

tDH---.1

tWE

DRO

X

VALID

L

\

WRITE ENABLE TIMING

WRITE ENABLE TIMING - WE such that: R1W
SYMBOL

t AS
tSET
tAH
t HLO
tWE
tORW
tos
tOH

CHARACTERISTIC

Setup ADDR t~S
Setup RIW to CS
Hold AD DR from CS
Hold RIW from CS
WE Pulse Width
ORa Reset from WE
Data Setup to WE
Data Hold from WE
INTRa Reset from WE

= 0, CS = O.
MIN

TYP

MAX

50

CONDITIONS

8

nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
J1sec

MAX

UNITS

CONDITIONS

3
3

J.tsec

MFM
FM

a

10

a

200
100

UNITS

200

150

a

READ DATA TIMING:
CHARACTERISTIC

MIN

Raw Read Pulse Width

.200
.400

Raw Read Cycle Time

3

Floppy Disk Control/er Devices

TYP

J1sec

1-47

WRITE DATA TIMING:
SYMBOL

CHARACTERISTIC

Write Gate to Write Data
Write Data Cycle Time
Write Gate off from WD
twp

Write Data Pulse Width

MIN

TYP

4
2
4,6,8
4
2
820
690
570
1.38

MAX

UNITS

CONDITIONS

",sec
",sec
",sec
",sec
",sec
nsec
nsec
nsec
",sec

FM
MFM
FM
MFM
Early MFM
Nominal MFM
Late MFM
FM

WRITE DATA TIMING

1-48

Floppy Disk Controller Devices

iP

f

I

I

:E

VIH

C
.....
......

......

r--IIP~

MR

5

NI
0
N

5

I

I

VIH

~IMR---1

~tCYc..J
CLK

LSL

~

( ' - tC0 2

I

~~

STEPIN

OIRC

4 - R1 RO·'-"

~tOIR~ ISTP J ..

"IISTP

n

STEP

14--

r-

tOIA

~ tSPT

b---

~r--1L-

MISCELLANEOUS TIMING

MISCELLANEOUS TIMING:
SYMBOL

CHARACTERISTIC

tC01
tC02
t STP

Clock Duty (low)
CLock Duty (high)
Step Pulse Output

tOIR

Dir Setup to Step

tMR
tiP

Master Reset Pulse Width
Index Pulse Width

Floppy Disk Controller Devices

MIN

TYP

50
50

67
67

nsec
nsec

4
8
24
48

J1sec

50
20

MAX

UNITS

J1sec

CONDITIONS

MFM
FM
MFM
FM

J1sec
J1sec

1-49

1-50

Floppy Disk Control/er Devices

WESTERN
COR

P

0

DIGITAL

RAT

ION

WD1772-02 Floppy Disk Formatter/Controller
Family Application Notes
INTRODUCTION

To meet the demand for a low cost compact lSI
Floppy Disk Controller device, Western Digital has
developed the WD1772-02. The WD1772-02 is a NMOS
Floppy Disk Controller device that incorporates the
FD179X, a digital data separator and write
precompensation circuitry all in a single chip. The
device offers soft sector formatting, selectable stepping rates, automatic track seek with verify, and
variable sector lengths. The WD1772-02 comes in a
28-pin dual-in-line package or quad pack and operates
from a single 5 volt only power supply.

During Direct Memory Access (DMA) data transfers
between the WD1772-02 and Host Memory, the Data
Request (DRO) line is used in Data Transfer Control.
This signal also appears as status bit 1 during
Read/Write operations. On Disk Read operations the
DRO is active when an assembled byte is present in
the Data Register, then reset when read by the Host.
If the Host fails to read the Data Register before the
following byte is assembled in the Data Register, the
lost data bit is set in Status Register.
At the completion of every command INTRa is
asserted. INTRa is de-asserted by either reading the
status or by loading the Command Register.

APPLICATIONS

The Mini-Floppy Controller is targeted for the low cost
sector of the disk drive market, where digital data
separation is preferred over analog phase lock loop.
Included in this market are Personal Computers, Portable Computers and Small Business Computers.
HOST INTERFACING

Interfacing to a Host processor is accomplished
through the eight bit bi-directional Data Access Lines
(DAl) and associated control lines. The DAl is used
to transfer data, status and control words out of or
into WD1772-02. The DAl having three states enabled
as an output when Chip Select (CS) is active low and
Read/Write (RIW) is high or as input receiver when CS
and RIW is low. When transfer of data with the device
is required by the Host CS is made low. The address
bits AO and A 1 combined with the RIW line select the
register and the direction of data.

DISKETTE DRIVE INTERFACING

The WD1772-02 has two modes of operation depending on the state of DDEN, regardless of the state
DDEN the ClK input remains at 8 MHz. Disk Reads
with sector lengths of 128, 256, 512 and 1024 byte sector in both FM or MFM from diskettes is
accomplished via the internal digital data separator.
Disk Write operation in MFM on inner tracks may
require write precompensation. Write precompensation is enabled when bit 1 = 0, in the Write command
and a precompensation value of 187 nsec is
produced.
The diskettes spindle motor is controlled by bit 3 of
any Type I, II or III command, upon receiving a command with bit 3 = 0, the spin up sequence is enabled.

GENERAL INFORMATION

A +5 volt supply ±5% is used as Vec, and the
clock input requires a free running 50% duty cycle
at 8 MHz ± 0.1 %.

Floppy Disk Controller Devices

1-51

1-52

Floppy Disk Controller Devices

WESTERN

c

o

R

p

o

DIGITAL

R

o

T

A

N

"T1

C

..a.

FD179X-02 Floppy Disk Formatter/Controller Family

.......

CD

><
I

o
FEATURES

•
•
•
•
•

•

•

•

•

TWO VFO CONTROL SIGNALS· RG & VFOE
SOFT SECTOR FORMAT COMPATIBILITY
AUTOMATIC TRACK SEEK WITH VERIFICATION
ACCOMMODATES SINGLE AND DOUBLE
DENSITY
FORMATS
IBM 3740 Single Density (FM)
I BM System 34 Double Density (M FM)
Non IBM Format for Increased Capacity
READ MODE
Single/Multiple Sector Read with Automatic
Search or Entire Track Read
Selectable 128, 256, 512 or 1024 Byte Sector
Lengths
WRITE MODE
Single/Multiple Sector Write with Automatic Sector Search
Entire Track Write for Diskette Formatting
SYSTEM COMPATIBILITY
Double Buffering of Data 8 Bit Bi-Directional Bus
for Data, Control and Status
DMA or Programmed Data Transfers
All Inputs and Outputs are TIL Compatible
On-Chip Track and Sector Registers/Comprehensive Status Information

PROGRAMMABLE CONTROLS
Selectable Track to Track Stepping Time
Side Select Compare
INTERFACES TO WD1691 DATA SEPARATOR
WINDOW EXTENSION
INCORPORATES ENCODINGIDECODING AND
ADDRESS MARK CIRCUITRY
FD1792/4 IS SINGLE DENSITY ONLY
FD1795/7 HAS A SIDE SELECT OUTPUT

•
•
•
•
•

179X-02 FAMILY CHARACTERISTICS
FEATURES

1791 1792 1793 1794 1795 1797

X
X

Single Density (FM)
Double Density (MFM)
True Data Bus
Inverted Data Bus
Write Precomp
Side Selection Output

X
X

X

X
X
X

X
X
X

X

X
X
X

X

X
X
X

X
X

X
X

X

APPLICATIONS

8" FLOPPY AND 5 1/4" MINI FLOPPY CONTROLLER
SINGLE OR DOUBLE DENSITY
CONTROLLER/FORMATIER

~K~O=A=TA-18)~>r-------~~R~AW~R~EA~O~-----,
AO

~S~

CS

~~EARLY

WE
··OAlO
FLOPPY DISK

OAL2

CONTROllER

DAn

FORMATTER

I

OAL"

N

OAl5

T

r;m

i

13

27

RAWREAb

WF7VFOE
WPRT

WG

+511

E
R
F

L

p
p
Y

+S'OK

'79X

BAIl

F

o

WO

RE

TROO
'OK

READY

A

TG43

C
E

STEP

INTRO

DIRC

ClK

=

·179113 RG
179517
··179317 TRUE BUS
•• ·1792/4 OPEN

=SSO

PIN DESIGNATION

r:~
DDEN

~

HLDC
IISS

liDO

IICC

1 I I
+12

J

HL T

ONE SHOT
(IF USED)

I

T

+511

+511

FD179X SYSTEM BLOCK DIAGRAM

Floppy Disk Controller Devices

1-53

I\l

PIN OUTS
"T1

......

PIN
NUMBER

X

1

NO CONNECTION

19

MASTER RESET

20

POWER SUPPLIES

C

....L

(0

0•

I\)

PIN NAME

21
40

SYMBOL
NC
-

FUNCTION
Pin 1 is internally connected to a back bias generator
and must be left open by the user.

MR

A logic low (50 microseconds min.) on this input resets
the device and loads HEX 03 into the command
register. The Not Ready (Status Bit 7) is reset during
MR ACTIVE. When MR is brought to a logic high a
RESTORE Command is executed, regardless of the
state of the Ready signal from the drive. Also, HEX
01 is loaded into sector register.

Vss

Ground

Vee
VDD

+5V ±5%
+ 12V±5%

COMPUTER INTERFACE:
2

WRITE ENABLE

3

CHIP SELECT

4

READ ENABLE

5,6

REGISTER SELECT LINES

-

WE

-

CS

-

A logic low on this input gates data on the DAL into
the selected register when CS is low.
A logic low on this input selects the chip and enables
computer communication with the device.

RE

A logic low on this input controls the placement of
data from a selected register on the DAL when CS
is low.

AO,A1

These inputs select the register to receive/transfer
data on the DAL lines under RE and WE control:

-

CS
0
0
0
0

7-14

1-54

A1
0
0
1
1

AO
0
1
0
1

RE
Status Reg
Track Reg
Sector Reg
Data Reg

WE
Command Reg
Track Reg
Sector Reg
Data Reg

DATA ACCESS LINES

DALO-DAL7

Eight bit bi-directional bus used for transfer of data,
control, and status. This bus is receiver enabled by
WE or transmitter enabled by RE. Each line will
drive 1 standard TTL load.

24

CLOCK

CLK

This input requires a free-running 50% duty cycle
square wave clock for internal timing reference, 2 MHz
± 1 % for 8" drives, 1 MHz ± 1 % for mini-floppies.

38

DATA REQUEST

DRQ

This open drain output indicates that the DR contains
assembled data in Read operations, or the DR is
empty in Write operations. This signal is reset when
serviced by the computer through reading or loading
the DR in Read or Write operations, respectively. Use
10K pull-up resistor to + 5.

39

INTERRUPT REQUEST

INTRQ

This open drain output is set at the completion of any
command and is reset when the STATUS register is
read or the command register is written to. Use 10K
pull-up resistor to + 5.

Floppy Disk Controller Devices

PIN
NUMBER

PIN NAME

SYMBOL

FUNCTION

FLOPPY DISK INTERFACE:
15
16

STEP
DIRECTION

STEP

17

EARLY

EARLY

18

LATE

LATE

22

TEST

23

HEAD LOAD TIMING

HLT

25

READ GATE
(1791,1792,1793,1794)

RG

SIDE SELECT OUTPUT
(1794,1797)

SSO

26

READ CLOCK

RCLK

27

RAW READ

RAW READ

28

HEAD LOAD

HLD

The HLD output controls the loading of the Read-Write
head against the media.

29

TRACK GREATER
THAN 43

TG43

This output informs the drive that the Read / Write
head is positioned between tracks 44-76. This output
is valid only during Read and Write Commands.

30

WRITE GATE

WG

This output is made valid before writing is to be performed on the diskette.

31

WRITE DATA

WD

A 50ns (MFM) or 500 ns (FM) output pulse per flux transition. WD contains the unique Address marks as well
as data and clock in both FM and MFM formats.

25

Floppy Disk Controller Devices

DIRC

-TEST

The step output contains a pulse for each step.
Direction Output is active high when stepping in,
active low when stepping out.
Indicates that the WRITE DATA pulse occuring while
Early is active (high) should be shifted early for write
precompensation.
Indicates that the write data pulse occurring while
Late is active (high) should be shifted late for write
precompensation.
This input is used for testing purposes only and should
be tied to + 5V or left open by the user unless interfacing to voice coil actuated steppers.
When a logic high is found on the HLT input the head
is assumed to be engaged. It is typically derived from
a 1 shot triggered by HLD.
This output is used for synchronization of external
data separators. The output goes high after two Bytes
of zeroes in single density, or 4 Bytes of either zeroes
or ones in double density operation.
The logic level of the Side Select Output is directly
controlled by the'S' flag in Type II or III commands.
When U = 1, SSO is set to a logic 1. When U = 0,
SSO is set to a logic O. The SSO is compared with
the side information in the Sector 10 Field. If they do
not compare Status Bit 4 (RNF) is set. The Side Select
Output is only updated at the beginning of a Type II
or III command. It is forced to a logic 0 upon a
MASTER RESET condition.
A nominal square-wave clock signal derived from the
data stream must be provided to this input. Phasing
(Le., RCLK transitions) relative to RAW READ is important but polarity (RCLK high or low) is not.
The data input signal directly from the drive. This input
shall be a negative pulse for each recorded flux
transition.

1-55

PIN
NUMBER
32

PIN NAME
READY

SYMBOL
READY

33

WRITE FAULT

34

TRACK 00

35

INDEX PULSE

36

WRITE PROTECT

WPRT

37

DOUBLE DENSITY

DDEN

WFNFOE
VFO ENABLE

-TROO

-

IP

GENERAL DESCRIPTION
The FD179X are N-Channel Silicon Gate MOS LSI
devices which perform the functions of a Floppy Disk
Formatter/Controller in a single chip implementation.
The FD179X, which can be considered the end result
of both the FD1771 and FD1781 designs, is IBM 3740
compatible in single density mode (FM) and System
34 compatible in Double Density Mode (MFM). The
FD179X contains all the features of its predecessor
the FD1771, plus the added features necessary to
ReadlWrite and format a double density diskette.
These include address mark detection, FM and MFM
encode and decode logic, window extension, and
write precompensation. In order to maintain compatibility, the FD1771, FD1781, and FD179X designs
were made as close as possible with the computer
interface, instruction set, and I/O registers being identical. Also, head load control is identical. In each case,
the actual pin assignments vary by only a few pins
from anyone to another.
The processor interface consists of an 8-bit bit directional bus for data, status, and control word transfers.

1-56

FUNCTION
This input indicates disk readiness and is sampled
for a logic high before Read or Write commands are
performed. If Ready is low the Read or Write operation is not performed and an interrupt is generated.
Type I operations are performed regardless of the
state of Ready. The Ready input appears in inverted
format as Status Register bit 7.
This is a bi-directional signal used to signify writing
faults at the drive, and to enable the external PLO
data separator. When WG = 1, Pin 33 functions as
a WF input. If WF = 0, any write command will immediately be terminated. When WG = 0, Pin 33 function as a VFOE output. VFOE will go low during a read
operation after the head has loaded and settled (H LT
= 1). On the 1795/7, it will remain low until the last
bit of the second CRC byte in the ID field. VFOE will
then go high until 8 bytes (MFM) or 4 bytes (FM)
before the Address Mark. It will then go active until
the last bit of the second CRC byte of the Data Field.
On the 1791/3, VFOE will remain low until the end
of the Data Field. This pin has an internal100K Ohm
pull-up resister.
This input informs the FD179X that the Read / Write
head is positioned over Track 00.
This input informs the FD179X when the index hole
is encountered on the diskette.
This input is sampled whenever a Write Command
is received. A logic low terminates the command and
sets the Write Protect Status bit.
This input pin selects either single or double density
operation. When DDEN = 0, double density is
selected. When DDEN = 1, single density is selected. This line must be left open on the 179214.
The FD179X is set up to operate on a multiplexed bus
with other bus-oriented devices.
The FD179X is TTL compatible on all inputs and outputs. The outputs will drive ONE TTL load or three
LS loads. The 1793 is identical to the 1791 except the
DAL lines are TRUE for systems that utilize true data
busses.
The 1795/7 has a side select output for controlling
double sided drives, and the 1792 and 1794 are "Single
Density Only" versions of the 1791 and 1793 respectively. On these devices, DDEN must be left open.
ORGANIZATION
The Floppy Disk Formatter is illustrated in the block
diagram. The primary sections include the parallel
processor interface and the Floppy Disk Interface.
Data Shift Register - This 8-bit register assembles
serial data from the Read Data input (RAW READ)
during Read operations and transfers serial data to
the Write Data output during Write operations.

Floppy Disk Controller Devices

Data Register - This 8-bit register is used as a holding
register during Disk Read and Write operations. In
Disk Read operations the assembled data byte is
transferred in parallel to the Data Register from the
Data Shift Register. In Disk Write operations information is transferred in parallel from the Data Register
to the Data Shift Register.
When executing the Seek command the Data Register
holds the address of the desired Track position. This
register is loaded from the DAL and gated onto the
DAL under processor control.
Track Register - This 8-bit register holds the track
number of the current Read/Write head position. It
is incremented by one every time the head is stepped in (towards track 76) and decremented by one
when the head is stepped out (towards track 00). The
contents of the register are compared with the
recorded track number in the 10 field during disk
Read, Write, and Verify operations. The Track Register
can be loaded from or transferred to the DAL. This
Register should not be loaded when the device is
busy.
Sector Register (SR) - This 8-bit register holds the
address of the desired sector position. The contents
of the register are compared with the recorded sector number in the 10 field ,during disk Read or Write
operations. The Sector Register contents can be
loaded from or transferred to the DAL. This register
should not be loaded when the device is busy.
Command Register (CR) - This 8-bit register holds the
command presently being executed. This register

should not be loaded when the device is busy unless
the new command is a force interrupt. The command
register can be loaded from the DAL, but not read
onto the DAL.
Status Register (STR) - This 8-bit register holds device
Status information. The meaning of the Status bits
is a function of the type of command previously
executed. This register can be read onto the DAL, but
not loaded from the DAL.
CRC Logic - This logic is used to check or to generate
the 16-bit Cyclic Redundancy Check (CRG). The
polynomial is:G(x) = x 16 + X 12 + x6 + 1.
The CRC includes all information starting with the
address mark and up to the CRC characters. The CRC
register is preset to ones prior to data being shifted
through the circuit.
Arithmetic/Logic Unit (ALU) - The ALU is a serial comparator, incrementer, and decrementer and is used
for register modification and comparisons with the
disk recorded 10 field.
Timing and Control - All computer and Floppy Disk
interface controls are generated through this logic.
The internal device timing is generated from an external crystal clock.
The FD179X has two different modes of operation
according to the state of DDEN. When DDEN = 0
double density (MFM) is assumed. When DDEN
= 1, single density (FM) is assumed. 1792 & 1794 are
single density only.

-~

FD179X BLOCK DIAGRAM

Floppy Disk Controller Devices

1-57

AM Detector - The address mark detector detects ID,
data and Index address marks during read and write
operations.
PROCESSOR INTERFACE

The interface to the processor is accomplished
through the eight Data Access Lines (DAL)
and
associated control signals. The DAL are used to
transfer Data, Status, and Control words out of, or
into the FD179X. The DAL are three state buffers
that are enabled as output drivers when Chip Select
(CS) and Read Enable (RE) are active (low logic
state) or act as input receivers when CS and Write
Enable (WE) are active.
When transfer of data with the Floppy Disk Controller
is required by the host processor, the device address
is decoded and CS is made low. The address bits A1
and AO, combined with the signals RE during a
Read operation or WE during a Write operation are
interpreted as selecting the following registers:

-

A1 - AO READ (RE)
0
0
1
1

0
1
0
1

Status Regiser
Track Register
Sector Register
Data Register

The 179X has two modes of operation according to
the state of DDEN (Pin 37). When DDEN
= 1,
single density is selected. In either case, the CLK
Input (Pin 24) is at 2 MHz. However, when interfacing with the mini-floppy, the CLK input is set at 1 MHz
for both single density and double density.
GENERAL DISK READ OPERATIONS

Sector lengths of 128, 256, 512 or 1024 are obtainable
in either FM or MFM formats. For FM, DDEN
should be placed to logical "1." For MFM formats,
DDEN should be placed to a logical "0." Sector
lengths are determined at format time by the fourth
byte in the "ID" field.
Sector Length Table*

WRITE (WE)
Command Register
Track Register
Sector Register
Data Register

During Direct Memory Access (DMA) types of data
transfers between the Data Register of the DF179X
and the processor, the Data Request (DRa) output
is used in Data Transfer control. This signal also
appears as status bit 1 during Read and Write
operations.
On Disk Read operations the Data Request is
activated (set high) when an assembled serial input
byte is transferred in parallel to the Data Register. This
bit is cleared when the Data Register is read by the
processor. If the Data Register is read after one or
more characters are lost, by having new data transferred into the register prior to processor readout, the
Lost Data bit is set in the Status Register. The Read
operation continues until the end of sector is reached.
On Disk Write operations the data Request is
activated when the Data Register transfers its contents to the Data Shift Register, and requires a new
data byte. It is reset when the Data Register is loaded
with new data by the processor. If new data is not
loaded at the time the next serial byte is required by
the Floppy Disk, a byte of zeroes is written on the
diskette and the Lost Data bit is set in the Status
Register.

1-58

At the completion of every command an INTRa is
generated. INTRa is reset by either reading the status
register or by loading the command register with a
new command. In addition, INTRa is generated if a
Force Interrupt command condition is met.

Sector Length
Field (hex)

Number of Bytes
in Sector (decimal)

00
01
02
03

128
256
512
1024

*1795/97 may vary - see command summary.
The number of sectors per track as far as the FD179X
is concerned can be from 1 to 255 sectors. The
number of tracks as far as the FD179X is concerned
is from 0 to 255 tracks. For IBM 3740 compatibility,
sector lengths are 128 bytes with 26 sectors per track.
For System 34 compatibility (MFM), sector lengths are
256 bytes/sector with 26 sectors/track; or lengths of
1024 bytes/sector with 8 sectors/track. (See Sector
Length Table.)
For read operations in 8" double density the FD179X
requires RAW READ Data (Pin 27) signal which is a
200 ns pulse per flux transition and a Read clock
(RCLK) signal to indicate flux transition spacings. THE
RCLK (Pin 26) signal is provided by some drives but
if not it may be derived externally by Phase lock loops,
one shots, or counter techniques. In addition, a Read
Gate Signal is provided as an output (Pin 25) on
1791/92193/94 which can be used to inform phase lock
loops when to acquire synchronization. When reading
from the media in FM. RG is made true when

Floppy Disk Controller Devices

For write operations, the FD179X provides Write Gate
(Pin 30) and Write Data (Pin 31) outputs. Write data
consists of a series of 500 ns pulses in FM (DDEN
= 1) and 200 ns pulses in MFM (DDEN = 0).
Write Data provides the unique address marks in both
formats.

2 bytes of zeroes are detected. The FD179X must find
an address mark within the next 10 bytes; otherwise
RG is reset and the search for 2 bytes of zeroes
begins all over again. If an address mark is found
within 10 bytes, RG remains true as long as the
FD179X is deriving any useful information from the
data stream. Similarly for MFM, RG is made active
when 4 bytes of "00" or "FF" are detected. The
FD179X must find an address mark within the next
16 bytes, otherwise RG is reset and search resumes.

Also during write, two additional Signals are provided
for write precompensation. These are EARLY (Pin 17)
and LATE (Pin 18). EARLY is active true when the WD
pulse appearing on (Pin 30) is to be written EARLY.
LATE is active true when the WD pulse is to be written LATE. If both EARLY and LATE are low when the
WD pulse is present, the WD pulse is to be written
at nominal. Since write precompensation values vary
from disk manufacturer to disk manufacturer, the
actual value is determined by several one shots or
delay lines which are located external to the FD 179X.
The write precompensation signals EARLY and LATE
are valid for the duration of WD in both FM and MFM
formats.

During read operations (WG = 0), the VFOE (Pin
33) is provided for phase lock loop synchronization.
VFOE will go active low when:
a) Both H LT and H LD are True
b) Settling Time, if programmed, has expired
c) The 179X is inspecting data off the disk
If WFVFOE is not used, leave open or tie to a 10K
resistor to + 5.
GENERAL DISK WRITE OPERATION

READY

When writing is to take place on the diskette the Write
Gate (WG) output is activated, allowing current to flow
into the Read / Write head. As a precaution to
erroneous writing the first data byte must be loaded
into the Data Register in response to a Data Request
from the FD179X before the Write Gate signal can be
activated.

Whenever a Read or Write command (Type II or III)
is received the FD179X samples the Ready input. If
this input is logic low the command is not executed
and an interrupt is generated. All Type I commands
are performed regardless of the state of the Ready
input. Also, whenever a Type II or III command is
received, the TG43 signal output is updated.

Writing is inhibited when the Write Protect input is
a logic low, in which case any Write command is
immediately terminated, an interrupt is generated and
the Write Protect status bit is set. The Write Fault
Input, when activated, signifies a writing fault condition detected in disk drive electronics such as failure
to detect write current flow when the Write Gate is
activated. On detection of this fault the FD179X terminates the current command, and sets the Write
Fault bit (bit 5) in the Status Word. The Write Fault
Input should be made inactive when the Write Gate
output becomes inactive.

COMMAND DESCRIPTION
The FD179X will accept eleven commands. Command
words should only be loaded in the Command
Register when the Busy status bit is off (Status bit
0). The one exception is the Force Interrupt command.
Whenever a command is being executed, the Busy
status bit is set. When a command is completed, an
interrupt is generated and the Busy status bit is reset.
The Status Register indicates whether the completed
command encountered an error or was fault free. For
ease of discussion, commands are divided into four
types. Commands and types are summarized in
Table 1.

TABLE 1. COMMAND SUMMARY

A. Commands for Models: 1791, 1792, 1793, 1794
Type Command
I
I
I
I
I
II
II
III
III
III
IV

Restore
Seek
Seek
Step-in
Step-out
Read Sector
Write Sector
Read Address
Read Track
Write Track
Force Interrupt

7

6

5

Bits
4

0
0
0
0
0
1
1
1
1
1
1

0
0
0
1
1
0
0
1
1
1
1

0
0
0
0
1
0
1
0
1
1
0

0
1
1
T
T
m
m
0
0
1
1

Floppy Disk Controller Devices

3

2

1

0

h
h
h
h
h
S
S
0
0
0
13

V
V
V
V
V
E
E

r1
r1
r1
r1
r1
C
C
0
0
0
11

ro
ro
ro
ro
ro
0

E
E
E
12

ao
0
0
0
10

B. Commands for Models: 1795, 1797
Bits
7
5
4
3
2
1
6
0
0
0
0
0
0
1
1
1
1
1
1

0
0
0
1
1
0
0
1
1
1
1

0
0
1
0
1
0
1
0
1
1
0

0
1
T
T
T
m
m
0
0
1
1

h
h
h
h
h
L
L
0
0
0
13

V
V
V
V
V
E
E
E
E
E
12

r1
r1
r1
r1
r1
U
U
U
U
U
11

ro
ro
ro
ro
ro
0
ao
0
0
0
10

1-59

TABLE 2. FLAG SUMMARY
"TI

C
.....

FLAG SUMMARY

CO

Command
Type

Bit
No(s)

•

I

0, 1

I

2

v

I

3

h = Head Load Flag

h = 1,Load head at beginning
h = 0 Unload head at beginning

I

4

T = Track Update Flag

T = O,No update
T = 1,Update track register

"

0

ao = Data Address Mark

ao = O,FB(DAM)
ao = 1,F8(deleted DAM)

"

1

C = Side Compare Flag

C = O,Disable side compare
C = 1,Enable side compare

,,& III

1

U = Update SSO

U = O,Update SSO to 0
U = 1,Update SSO to 1

,,& "I

2

E = 15 MS Delay

E = O,No 15 MS delay
E = 1,15 MS delay

"

3

S = Side Compare Flag

S = O,Compare for side 0
S = 1,Compare for side 1

"

3

L = Sector Length Flag

......
X

0

I\)

"

4

IV

0-3

Description
r1rO = Stepping Motor Rate
See Table 3 for Rate Summary
= Track Number Verify Flag

m = Multiple Record Flag

Ix
10
11
12
13
13-10

=
=
=
=
=
=

V = O,No verify
V = 1,Verify on destination track

LSB's Sector Length in ID Field
00
01
10
11
L= 0

256

512

1024

128

L= 1

128

256

512

1024

m = O,Single record
m = 1,Multiple records

Interrupt Condition Flags
1 Not Ready To Ready Transition
1 Ready To Not Ready Transition
1 Index Pulse
1 Immediate Interrupt, Requires A Reset
0 Terminate With No Interrupt (INTRQ)

NOTE: See Type IV Command Description for further information.

1-60

Floppy Disk Controller Devices

TYPE I COMMANDS
The Type I Commands include the Restore, Seek,
Step, Step-in, and Step-Out commands. Each of the
Type I Commands contains a rate field (ro r1), which
determines the stepping motor rate as defined in
Table 3.
A 2J1-s (MFM) or 4J1-s (FM) pulse is provided as an output to the drive. For every step pulse issued, the drive
moves one track location in a direction determined
by the direction output. The chip will step the drive
in the same direction it last stepped unless the command changes the direction.
The Direction signal is active high when stepping in
and low when stepping out. The Direction Signal is
valid 12J1-s before the first stepping pulse is generated.
The rates (shown in Table 3) can be applied to a StepDirection Motor through the device interface.

Type II or III command. Once HLD is active it remains
active until either a Type I command is received with
(h = a and V = 0); or if the FD179X is in an idle state
(non-busy) and 15 index pulses have occurred.
Head Load Timing (HLD is an input to the FD179X
which is used for the head engage time. When HLT
= 1, the FD179X assumes the head is completely
engaged. The head engage time is typically 30 to 100
ms depending on drive. The low to high transition on
HLD is typically used to fire a one shot. The output
of the one shot is then used for HLT and supplied
as an input to the FD179X.

HLD

tl-----'

sf- - - -

i

~50T0100mS_____1

,..------

TABLE 3. STEPPING RATES
HL T (FROM ONE SHOT)

ClK
DO EN

2 MHz

2 MHz

0

1 MHz

1 MHz

2 MHz

1 MHz

0

1

X

X

R1 RO TEST = 1TEST= 1 TEST = 1 TEST = 1 TEST = OTEST=O
0 0

3 ms

3 ms

6 ms

6 ms

1851"s

3681"s

0 1

6 ms

6 ms

12 ms

12 ms

19O1"s

38Ol"s

1 0

10 ms

10 ms

20 ms

20 ms

1981"s

3961"s

1 1

15 ms

15 ms

30 ms

30 ms

2081"s

4161"s

After the last directional step an additional 15
milliseconds of head settling time takes place if the
Verify flag is set in Type I commands. Note that this
time doubles to 30 ms for a 1 MHz clock. If TEST
= 0, there is zero settling time. There is also a 15
ms head settling time if the E flag is set in any Type
II or III command.
When a Seek, Step or Restore command is executed
an optional verification of Read-Write head position
can be performed by setting bit 2 (V
1) in the command Word to a logic 1. The verification operation
begins at the end of the 15 millisecond settling time
after the head is loaded against the media. The track
number from the first encountered ID Field is compared against the contents of the Track Register. If
the track numbers compare and the ID Field Cyclic
Redundancy Check (CRG) is correct, the verify operation is complete and an INTRa is generated with no
errors. If there is a match but not a valid CRC, the
CRC error status bit is set (Status bit 3), and the next
encountered ID field is read from the disk for the
verification operation.

=

The FD179X must find an ID field with correct track
number and correct CRC within 5 revolutions of the
media; otherwise the seek error is set and an INTRa
is generated. If V = 0, no verification is performed.
The Head Load (HLD) output controls the movement
of the read / write head against the media. HLD is
activated at the beginning of a Type I command if
the h flag is set (h = 1), at the end of the Type I command if the verify flag (V
1), or upon receipt of any

=

Floppy Disk Cqntro/ler Devices

HEAD LOAD TIMING
When both HLD and HLT are true, the FD179X will
then read from or write to the media. The "and" of
HLD and HLT appears as status Bit 5 in Type I status.

a

In summary for the Type I commands: if h =
and
0, HLD is reset. If h
1 and V
0, HLD is set
V
at the beginning of the command and HLT is not
sampled nor is there an internal 15 ms delay. If h =
a and V 1, HLD is set near the end of the command, an internal 15 ms occurs, and the FD179X waits
for HLT to be true. If h
1 and V
1, HLD is set
at the beginning of the command. Near the end of
the command, after all the steps have been issued,
an internal 15 ms delay occurs and the FD 179X then
waits for HLT to occur.

=

=

=

=

=

=

For Type II and III commands with E flag off, HLD
is made active and HLT is sampled until true. With
E flag on, HLD is made active, an internal 15 ms delay
occurs and then HLT is sampled until true.
RESTORE (SEEK TRACK 0)
Upon receipt of this comand the Track 00
(TROD) input is sampled. If TROD is active low indicating the ReadlWrite head is positioned over track
0, the Track Register is loaded with zeroes and an
interrupt is generated. If TROO is not active low,
stepping pulses (pins 15 to 16) at a rate specified by
the r1rO field are issued until the TROO input is activated. At this time the Track Register is loaded with
zeroes and an interrupt is generated. If the TROO
input does not go active low after 255 stepping pulses,
the FD179X terminates operation, interrupts, and sets
the Seek error status bit, providing the V flag is set.
A verification operation also takes place if the V flag
is set. The h bit allows the head to be loaded at the
start of command. Note that the Restore command
is executed when MR goes from an active to an
inactive state and that the DRa pin stays low.

1-61

."

o

-"
......

CO

><•

o

N

TYPE I COMMAND FLOW

TYPE I COMMAND FLOW

SEEK

STEP

This command assumes that the Track Register contains the track number of the current position of the
ReadlWrite head and the Data Register contains
the desired track number. The FD179X will update the
Track register and issue stepping pulses in the
appropriate direction until the contents of the Track
register are equal to the contents of the Data Register
(the desired track location). A verification operation
takes place if the V flag is on. The h bit allows the
head to be loaded at the start of the command. An
interrupt is generated at the completion of the command. An interrupt is generated at the completion of
the command. Note: When using multiple drives, the
register must be updated for the drive selected before
seeks are issued.

Upon receipt of this command, the FD179X issues
one stepping pulse to the disk drive. The stepping
motor direction is the same as in the previous step
command. After a delay determined by the r1rO field,
a verification takes place if the V flag is on. If the U
flag is on, the Track Register is updated. The h bit
allows the head to be loaded at the start of the command. An interrupt is generated at the completion of
the command.

1-62

STEP-IN

Upon receipt of this command, the FD179X issues
one stepping pulse in the direction towards track 76.
If the U flag is on, the Track Register is incremented
by one. After a delay determined by the r1rO field, a
verification takes place if the V flag is on. The h bit
allows the head to be loaded at the start of the

Floppy Disk Controller Devices

command. An interrupt is generated at the completion of the command.
STEP-OUT
Upon receipt of this command, the F0179X issues
one stepping pulse in the direction towards track O.
If the U flag is on, the Track Register is decremented
by one. After a delay determined by the r1rO field, a
verification takes place if the V flag is on. The h bit
allows the head to be loaded at the start of the command. An interrupt is generated at the completion of
the command.
EXCEPTIONS
On the 1795/ 7 devices, the SSO output is not
affected during Type I commands, and an internal
side compare does not take place when the M Verify
Flag is on.

VERIFY
SEQUENCE

NOTE:

I1lTrr = 0, THERE IS NO
ir ~ = 1 AND eLK = t

load the Sector Register with the desired sector
number. Upon receipt of the Type II command, the
busy status Bit is set. If the E flag = 1 (this is the
normal case) HLO is made active and HLT is sampled
after a 15 msec delay. If the E flag is 0, the head is
loaded and HLT sampled with no 15 msec delay.
When an 10 field is located on the disk, the F0179X
compares the Track Number on the 10 field with the
Track Register. If there is not a match, the next
encountered 10 field is ready and a comparison is
again made. If there was a match, the Sector Number
of the 10 field is compared with the Sector Register.
If there is not a Sector match, the next encountered
10 field is read off the disk and comparisons again
made. If the 10 field CRC is correct, the data field is
then located and will be either written into, or read
from depending upon the command. The F0179X
must find an ID field with a Track number, Sector
number, side number, and CRC within four revolutions
of the disk; otherwise, the Record Not Found status
bit is set (Status bit 3) and the command is terminated
with an interrupt.

15MS DELAY
MHz, THERE IS A JOM$ DELAY

TYPE I COMMAND FLOW
TYPE II COMMANDS
The Type II Commands are the Read Sector and Write
Sector commands. Prior to loading the Type II Command into the Command Register, the computer must

Floppy Disk Controller Devices

TYPE II COMMAND

1-63

"T1

C

-""

co
"""
X

o•

I\)

-n
C
......

.......

co

><
I

o

I\)

Each of the Type II Commands contains an (m) flag
which determines if multiple records (sectors) are to
be read or written, depending upon the command. If
m = 0, a single sector is read or written and an interrupt is generated at the completion of the command.
If m = 1, multiple records are read or written with
sector register internally updated so that an address
verification can occur on the next record. The WD179X
will continue to read or write multiple records and
update the sector register in numerical ascending
sequence until the sector register exceeds the
number of sectors on the track or until the Force Interrupt command is loaded into the Command Register,
which terminates the command and generates an
interrupt.
For example: If the FD 179X is instructed to read sector 27 and there are only 26 on the track, the sector
register exceeds the number available. The FD179X
will search for 5 disk revolutions, interrupt out, reset
busy, and set the Record Not Found status bit.
The Type II commands for 1791-94 also contain side
select compare flags. When C = 0 (Bit 1) no side
comparison is made. When C = 1, the LSB of the
side number is read off the ID field of the disk and
compared with the contents of the (S) flag (Bit 3). If
the S flag compares with the side number recorded
in the ID field, the FD179X continues with the ID
search. If a comparison is not made within 5 index
pulses, the interrupt line is made active and the
Record Not Found status bit is set.

TYPE II COMMAND

1-64

The Type II and III commands contain a side select
flag (Bit 1). When U = 0, SSO is updated to o. Similarly, U = 1 updates SSO to 1. The chip compares the
SSO to the ID field. If they do not compare within 5
revolutions the interrupt line is made active and the
RNF status bit is set.
The 1795/7 READ SECTOR and WRITE SECTOR
commands include a 'L' flag. The 'L' flag, in conjunction with the sector length byte of the ID Field, allows
different byte lengths to be implemented in each sector. For IBM compatability. the 'L' flag should be set
to a one.
READ SECTOR

Upon receipt of the Read Sector command, the head
is loaded, the Busy status bit set, and when an ID
field is encountered that has the correct track number,
correct sector number, correct side number, and correct eRe, the data field is presented to the computer.
The Data Address Mark of the data field must be
found within 30 bytes in single density and 43 bytes
in double density of the last ID field eRe byte; if not,
the ID filed is searched for and verified again followed
by the Data Address Mark search. If after 5 revolutions the DAM cannot be found, the Record Not
Found status bit is set and the operation is terminated. When the first character or byte of the
READ SECTOR
SEQUENCE

TYPE II COMMAND

Floppy Disk Controller Devices

WRITE SECTOR
SEQUENCE

STATUS
BIT 5
1

o

Deleted Data Mark
Data Mark

WRITE SECTOR

Upon receipt of the Write Sector command, the head
is loaded (HLD active) and the Busy status bit is set.
When an ID field is encountered that has the correct
track number, correct sector number, correct side
number, and correct eRe, a DRO is generated. The
FD179X counts off 11 bytes in single density and 22
bytes in double density from the eRe field and the
Write Gate 0NG) output is made active if the DRO is
serviced (i.e., the DR has been loaded by the computer). If DRO has not been serviced, the command
is terminated and the Lost Data status bit is set. If
the DRO has been serviced, the WG is made active
and six bytes of zeroes in single density and 12 bytes
in double density are then written on the disk. At this
time the Data Address Mark is then written on the
disk as determined by the aO field of the command
as shown below:
ao

Data Address Mark (Bit 0)

1

Deleted Data Mark
Data Mark

o

The FD179X then writes the data field and generates
DRO's to the computer. If the DRO is not serviced
in time for continuous writing the Lost Status Data
Bit is set and a byte of zeroes is written on the disk.
The command is not terminated. After the last data
byte has been written on the disk, the two-byte eRe
is computed internally and written on the disk
followed by one byte of logic ones in FM or in MFM.
The WG output is then deactivated. For a 2 MHz clock
the INTRa will set 8 to 12f-tsec after the last eRe byte
is written. For partial sector writing, the proper
method is to write the data and fill the balance with
zeroes. By letting the chip fill the zeroes, errors may
be masked by the lost data status and improper eRe
Bytes.

NO

TYPE II COMMAND

data field has been shifted through the DSR, it is
transferred to the DR, and DRO is generated. When
the next byte is accumulated in the DSR, it is transferred to the DR and another DRO is generated. If the
computer has not read the previous contents of the
DR before a new character is transferred that
character is lost and the Lost Data Status bit is set.
This sequence continues until the complete data field
has been input to the computer. If there is a eRe error
at the end of the data field, the eRe error status bit
is set, and the command is terminated (even if it is
a multiple record command).
At the end of the Read operation, the type of Data
Address Mark encountered in the data field is
recorded in the Status Register (Bit 5) as shown:

Floppy Disk Controller Devices

TYPE III COMMANDS
READ ADDRESS

Upon receipt of the Read Address command, the head
is loaded and the Busy Status Bit is set. The next
encountered ID field is then read in from the disk, and
the six data bytes of the ID field are assembled and
transferred to the DR, and a DRO is generated for
each byte. The six bytes of the ID field are shown
below:

TRACK
ADDR
1

SIDE
SECTOR SECTOR CRC CRC
NUMBER ADDRESS LENGTH 1
2
2

3

4

5

6

Although the eRe characters are transferred to the
computer, the FD179X checks for validity and the eRe
error status bit is set if there is a eRe error. The Track
Address of the ID field is written into the sector

1-65

."

C
....
......

co

~

o

I\)

register so that a comparison can be made by the
user. At the end of the operation an interrupt is
generated and the Busy Status is reset.
READ TRACK
Upon receipt of the READ track command, the head
is loaded, and the Busy Status bit is set. Reading
starts with the leading edge of the first encountered
index pulse and continues until the next index pulse.
All Gap, Header, and data bytes are assembled and
transferred to the data register and DRO's are
generated for each byte. The accumulation of bytes
is synchronized to each address mark encountered.
An interrupt is generated at the completion of the
command.

This command has several characteristics which
make it suitable for diagnostic purposes. They are:
the Read Gate is not activated during the command;
no CRC checking is performed; gap information is
included in the data stream; the internal side compare is not performed; and the address mark detector is on for the duration of the command. Because
the AM. detector is always on, write splices or noise
may cause the chip to look for an AM. If an address
mark does not appear on schedule the Lost Data
status flag is set.
The ID AM., ID field, ID CRC bytes, DAM, Data, and
Data CRC Bytes for each sector will be correct. The
Gap Bytes may be read incorrectly during write-splice
time oecau!'>e of synchronization.

·10 liS IF CLOCK
.1MHz

TYPE III COMMAND WRITE TRACK

1-66

TYPE III COMMAND WIRTE TRACK

Floppy Disk Controller Devices

CONTROL BYTES FOR INITIALIZATION
DATA PATIERN
IN DR (HEX)
00 thru F4
F5
F6
F7
F8 thru FB
FC
FD
FE
FF

=
=

=

=

*Missing clock transition between bits 4 and 5.
WRITE TRACK FORMATTING THE DISK
(Refer to section on Type III commands for flow
diagrams.)
Formatting the disk is a relatively simple task when
operating programmed I / 0 or when operating under
DMA with a large amount of memory. Data and gap
information must be provided at the computer interface. Formatting the disk is accomplished by positioning the R / W head over the desired track number
and issuing the Write Track command.
Upon receipt of the Write Track command, the head
is loaded and the Busy Status bit is set. Writing starts
with the leading edge of the first encountered index
pulse and continues until the next index pulse, at
which time the interrupt is activated. The Data
Request is activated immediately upon receiving the
command, but writing will not start until after the first
byte has been loaded into the Data Register. If the
DR has not been loaded by the time the index pulse
is encountered the operation is terminated making
the device Not Busy, the lost Data Status Bit is set,
and the interrupt is activated. If a byte is not present
in the DR when needed, a byte of zeroes is
substituted.
This sequence continued from one index mark to the
next index mark. Normally, whatever data pattern
appears in the data register is written on the disk with
a normal clock pattern. However, if the FD179X
detects a data pattern of F5 through FE in the data
register, this is interpreted as data address marks with
missing clocks or CRC generation.
The CRC generator is initialized when any data byte
from F8 to FE is about to be transferred from the DR
to the DSR in FM or by receipt of F5 in MFM. An F7
pattern will generate two CRC characters in FM or
MFM. As a consequence, the patterns F5 through FE
must not appear in the gaps, data fields, of 10 fields.
Also, CRC's must be generated by an F7 pattern.
Disks may be formatted in IBM 3740 or System 34
formats with sector lengths of 128, 256, 512, or 1024
bytes.
TYPE IV COMMANDS
The Forced Interrupt command is generally used to
terminate a multiple sector read or write command

Floppy Disk Controller Devices

~

IN MFM (DDEN
0)
Write 00 thru F4,in MFM
Write A 1* in MFM, Present CRC
Write C2** in MFM
Generate 2 CRC bytes
Write F8 thru FB, in MFM
Write FC in MFM
Write FD in MFM
Write FE in MFM
Write FF in MFM

FF
Write 00 thru F4 with ClK
Not Allowed
Not Allowed
Generate 2 CRC bytes
Write F8 thru FB, ClK
C7, Preset CRC
Write FC with ClK
07
Write FD with ClK
FF
Write FE, ClK
C7, Preset CRC
Write FF with ClK
FF

=
=
=
=

"T1
C

FD179~NTERPRETATION

FD179X INTERPRETATION
IN FM (DDEN
1)

........
CD

><
I

o

I\,)

* *Missing clock transition between bits 3 and 4.
or to insure Type I status in the status register. This
command can be loaded into the command register
at any time. If there is a current command under
execution (busy status bit set) the command will be
terminated and the busy status bit reset.
The lower four bits of the command determine the
conditional interrupt as follows:
10
11
12
13

=
=
=
=

Not-Ready to Ready Transition
Ready to Not-Read Transition
Every Index Pulse
Immediate Interrupt

The conditional interrupt is enabled when the corresponding bit positions of the command 13-1 0) are
set to a 1. Then, when the condition for interrupt is
met, the INTRQ line will go high signifying that the
condition specified has occurred. If 13-10 are all set to
zero (HEX DO), no interrupt will occur but any command presently under execution will be immediately
terminated. When using the immediate interrupt condition (13
1) an interrupt will be immediately
generated and the current command terminated.
Reading the status or writing to the command register
will not automatically clear the interrupt. The HEX DO
is the only command that will enable the immediate
interrupt (HEX 08) to clear on a subsequent load command register or read status register operation. Follow
a HEX 08 with DO command.

=

Wait 8 micro sec (double density) or 16 micro sec
(single density) before issuing a new command after
issuing a forced interrupt (times double when clock
= 1 MHz). loading a new command sooner than this
will nullify the forced interrupt.
Forced interrupt stops any command at the end of
an internal micro-instruction and generates INTRQ
when the specified condition is met. Forced interrupt
will wait until AlU operations in progress are complete (CRC calculations, compares, etc.).
More than one condition may be set at a time. If for
example, the READY TO NOT-READY condition (11 =
1) and the Every Index Pulse (1 2 = 1) are both set, the
resultant command would be HEX "DA". The "OR"
function is performed so that either a READY TO
NOT-READY or the next Index Pulse will cause an interrupt condition.

1-67

READ TRACK
SEQUENCE

"......
c......

co
XI

o

I\)

INTRQ
RESET BUSY

SET INTRQ
RESET BUSY

YES

READ
ADDRESS

°11 TEST= f, NO DELAY
IITEST=l and ClK=l MHZ~ 30 MS DELAY

TYPE III COMMAND

Read Track / Address

1-68

Floppy Disk Controller Devices

STATUS REGISTER
READ ADDRESS
SEQUENCE

RESET BUSY
SET INTRO
SET RNF

Upon receipt of any command, except the Force Interrupt command, the Busy Status bit is set and the rest
of the status bits are updated or cleared for the new
command. If the Force Interrupt Command is received
when there is a current command under execution,
the Busy status bit is reset, and the rest of that status
bits are unchanged. If the Force Interrupt command
is received when there is not a current command
under execution, the Busy Status bit is reset and the
rest of the status bits are updated or cleared. In this
case, Status reflects the Type I commands.
The user has the option of reading the status register
through program control or using the DRO line with
DMA or interrupt methods. When the Data register
is read the DRO bit in the status register and the DRO
line are automatically reset. A write to the Data
register also causes both DRO's to reset.
The busy bit in the status may be monitored with a
user program to determine when a command is complete, in lieu of using the INTRO line. When using the
INTRO, a busy status check is not recommended
because a read of the status register to determine
the condition of busy will reset the INTRO line.
The format of the Status Register is shown below:
BITS
7

6

5

4

3

2

1

0

S7

S6

S5

S4

S3

S2

S1

SO

Status varies according to the type of command
executed as shown in Table 4.
Because of internal sync cycles, certain time delays
must be observed when operating under programmed
1/ O. They are: (times double when clock = 1 MHz)
Operation

Next Operation

Read Busy Bit
Write to
Command Reg. (Status Bit 0)
Write to
Read Status
Command Reg. Bits 1-7
Write Any
Read From Ditt.
Register
Register

Delay Req'd.
FM
MFM
12p.s
6p.s
28p.s

14p.s

0

0

IBM 3740 FORMAT - 128 BYTES / SECTOR

TYPE III COMMAND

Read Track / Address

Floppy Disk Controller Devices

Shown below is the IBM single-density format with
128 bytes / sector. In order to format a diskette, the
user must issue the Write Track command, and load
the data register with the following values. For every
byte to be written, there is one Data Request.

1-69

IBM 3740 FORMAT· 128 BYTES / SECTOR

".....c......

co
XI
o

N

Shown below is the IBM single-density format with
128 bytes / sector. In order to format a diskette, the
user must issue the Write Track command, and load
the data register with the following values. For every
byte to be written, there is one Data Request.
NUMBER
OF BYTES
40
6
1
26
6
1
1
1
1
1
1
11
6
1
128
1
27
247**

*

HEX VALUE OF
BYTE WRITTEN
FF (or 00)1
00
FC (Index Mark)
FF (or 00)1
00
FE (10 Address Mark)
Track Number
Side Number (00 or 01)
Sectdr Number (1 thru 1A)
00 (Sector Length)
F7 (2 CRC's written)
FF (or OO)ses E5)1
00
FB (Data Address Mark)
Data (IBM uses E5)
F7 (2 CRC's written)
FF (or 00)1
FF (or 00)1

*Write bracketed field 26 times.
* *Continue writing until FD179X interrupts out.
Approx. 247 bytes.
1-0ptional '00' on 1795/7 only.

Shown below is the IBM dual-density format with 256
bytes / sector. In order to format a diskette the user
must issue the Write Track command and load the
data register with the following values. For every byte
to be written, there is one data request.
NUMBER
OF BYTES
80
12

3
*

1
50
12

3
1
1
1
1
1
1
22
12

3
1
256
1
54
598**

HEX VALUE OF
BYTE WRITTEN
4E
00
F6 (Writes C2)
FC (Index Mark)
4E
00
F5 (Writes A 1)
FE (10 Address Mark)
Track Number (0 thru 4C)
Side Number (0 or 1)
Sector Number (1 thru 1A)
01 (Sector Length)
F7 (2 CRC's written)
4E
00
F5 (Writes A 1)
FB (Data Address Mark)
DATA
F7 (2 CRC's written)
4E
4E

*Write bracketed field 26 times.
**Continue writing until FD179X interrupts out.
Approx. 598 bytes.

,,,,"''' .. OfrllYIDAMANOOATA ... W

AIIIE .... ECEOEO.TTHAEE.TTESOF
AI WItH CLOCK TAAN$ITIONIfTWEEN

8,TS.ANO$"tSSlNG

•• .. rSSIHGCLOCI(TAANSITIOH

IETWEEN"TS1AND.

IBM TRACK FORMAT

1-70

Floppy Disk Controller Devices

1. NON·IBM FORMATS
Variations in the IBM formats are possible to a limited
extent if the following requirements are met:

1-------- -

'6' OR 32'

"T1

c

-I

"s _ _ _ _---I

1) Sector size must be 128, 256, 512, 1024 bytes.

-I.

.......
VOH

2) Gap 2 cannot be vaired from the IBM format.

I

3) 3 bytes of A1 must be used in MFM.
'NTRO

Gap I

16 bytes FF

32 bytes 4E

Gap II

11 bytes FF

22 bytes 4E

*
*

6 bytes 00

12 bytes 00
3 bytes A1

Gap 111**

10 bytes FF
4 bytes 00

24 bytes 4E
8 bytes 00
3 bytes A1

Gap IV

16 bytes FF

N

f---;---+--------,
VOL

'R[

MFM

---+---,

10AU - - - - - - 1 t - - - - i

NOTE

1

Cs MAl' BE

PERMANENTLY TIED lOW IF DESIREO

"TIME DOUBLES wHEN CLOCK·
t SERVICE (WORST CASE I

"FM 275 uS
°MFM
135 uS

16 bytes 4E

ORO RISING EDGE: INDICATES THAT THE DATA REGISTER HAS ASSEMBLED
DATA
ORO FALliNG EDGE: INDICATES THAT THE DATA REGISTER WAS READ
INTRO RISING EDGE, OCCURS AT END OF COMMAND

* Byte counts must be exact.
* *Byte counts are minimum, except exactly 3 bytes
of A 1 must be written.

INTRO FALLING EDGE INDICATES THAT THE STATUS REGISTER WAS READ

READ ENABLE TIMING

TIMING CHARACTERISTICS
TA

= OOC to 70°C, VDD = +12V±.6V, Vss

OV, Vcc

+5V ± .25V

READ ENABLE TIMING
SYMBOL
TSET
THLD
TRE
TDRR
TIRR
TDACC
TDOH

CHARACTERISTIC

MIN.

Setup ADDR & CS to RL
Hold ADDR & CS from RE
RE Pulse Width
DRO Reset from RE
INTRa Reset from RE
Data Access from RE
Data Hold From RE

50
10
400

TYP.

MAX.

UNITS

400
500

500
3000
350
150

nsec
nsec
nsec
nsec
nsec
nsec
nsec

TYP.

MAX.

UNITS

50

CONDITIONS

C L = 50 pf
See Note 5
C L = 50 pf
C L = 50 pf

WRITE ENABLE TIMING (See Note 6, Page 21)
SYMBOL
TSET
THLD
TWE
TDRR
TIRR
TDS
TDH

CHARACTERISTIC
Setup ADDRS & CS TO WE
Hold ADDR & CS from WE
WE Pulse Width
DRO Reset from WE
I NTRO Reset from WE
Data Setup to WE
Data Hold from WE

Floppy Disk Controller Devices

><

0
T'RR'---l

-In addition, the Index Address Mark is not required
for operation by the FD179X. Gap 1, 3, and 4 lengths
can be as short as 2 bytes for FD179X operation,
however PLL lock up time, motor speed variation,
write-splice area, etc. will add more bytes to each gap
to achieve proper operation. It is recommended that
the IBM format be used for highest system reliability.
FM

co

MIN.
50
10
350

400
500
250
70

500
3000

nsec
nsec
nsec
nsec
nsec
nsec
nsec

CONDITIONS

See Note 5

1-71

'''I

I

Ipw---j
RAW READ

'XI

-j
RClK

~

I-

U

LJ

I=='XI-J

I~T'

,-

.I, .

I

Tb

----f

•I

Te

NOMINAL
DISKETTE
8"
8"
5"
5"

NOTE 1 CS MAY BE PERMANENTL Y TIED LOW IF DESIRED
2 WHEN WRITING DATA INTO SECTOR TRACK OR DATA
REGISTER USER CANNOT READ THIS REGISTER UNTIL
AT LEAST 4 ... SEC IN MFM AFTER THE RISING EDGE OF WE
WHEN WRITING INTO THE COMMAND REGISTER STATUS
1 SERVICE tWORST CASEI
IS NOT VALID UNTIL SOME 26 .uSEC IN FM 14 .uSEC IN MFM
'fM 235 uS
LATER
THESE TIMES ARE DOUBLED WHEN CLK
1 MHz
'MFM
11 ~uS
'TlME DOUBLES WHEN CLOCK
1MHz

MODE
MFM
FM
MFM
FM

ORa RISING EDGE INDICATES THAT THE DATA REGISTER IS EMPTY
ORO FALLING EDGE INDICATES THAT THE DATA REGISTER IS LOADED
INTRQ RISING EDGE INDICATE THE END OF A COMMAND
INTRa FALlIttG EDGE INDICATES THAT THE COMMAND REGISTER
IS WRITIEN TO

DDEN

0

1
0

1

eLK
2 MHz
2 MHz
1 MHz
1 MHz

T.

Tb

Tc

1 ~s

1 ~s

2 ~s
4 ~s
4 ~s
8 ~s

2 ~s

2~s

2~s

2~s

4

~s

4

~s

INPUT DATA TIMING

WRITE ENABLE TIMING
INPUT DATA TIMING:
SYMBOL
Tpw
Tsc
TCK
TX1
TX2

CHARACTERISTIC
Raw Read Pulse Width
Raw Read Cycle Time
RClK Cycle Time
RClK hold to Raw Read
Raw Read hold to RClK

MIN.

TYP.

100
1500
1500
40
40

200
2000
2000

WRITE DATA TIMING:(All TIMES DOUBLE WHEN elK
SYMBOL
Twp

CHARACTERISTICS
Write Data Pulse Width

Twg

Write Gate to Write DATA

Tbc
Ts
Th
Twf

Write Data Cycle Time
Early (late) to Write Data
Early (late) From
Write Data
Write Gate off from WD

Twdl

WD Valid Clk

Twd2

WD Valid after ClK

1-72

MIN.

UNITS

CONDITIONS

nsec
nsec
nsec
nsec
nsec

See Note 1
1800 ns @ 70°C
1800 ns @ 70°C
See Note 1
See Note 1

1 MHz)
TYP.

MAX.

UNITS

500
200
2
1
2,3,or 4

650
350

nsec
nsec
JLsec
JLsec
JLsec
nsec
nsec

CONDITIONS
FM
MFM
FM
MFM
± ClK Error
MFM
MFM

JLsec
JLsec
nsec
nsec
nsec
nsec

FM
MFM
ClK
1 MHz
ClK = 2 MHz
ClK
1 MHZ
ClK = 2 MHz

125
125
2
1
100
50
100
30

MAX.

=
=

Floppy Disk Controller Devices

r--250NS----I~...

1

ClK
(2MHZ)

---,
...

~IWM

WD

Twdl

--1 1 r--

r-I

ClK
(2MHZ)

L

,

1_________""'.

DDEN= 1

Twd2

125

~r

125-1

---,
,'-_ _ _ _ _ _ _ _- - '

(DDEN = 0)

WD
Twdl

--.j

~

Twd2

WD MUST HAVE RISING EDGE IN FIRST SHADED AREA AND TRAILING
EDGE IN SECOND SHADED AREA.
WRITE DATA/CLOCK RELATIONSHIP

WRITE DATA TIMING
MISCELLANEOUS TIMING: (Times Double When Clock
SYMBOL
TCD 1
TCD 2
TSTP
TDIR
TMR
TIP

TWF

CHARACTERISTIC
Clock Duty (low)
Clock Duty (high)
Step Pulse Output
Dir Setup to Step
Master Reset Pulse Width
Index Pulse Width
Write Fault Pulse Width

Floppy Disk Controller Devices

= 1MHz)

MIN.

TYP.

MAX.

UNITS

230
200
2 or 4

250
250

20000
20000

nsec
nsec
ILsec
ILsec
ILsec
ILsec
ILsec

12
50
10
10

CONDITIONS

See Note 5
± ClK ERROR
See Note 5

1-73

NOTES:
iP

5

I

j

I

1. Pulse width on RAW READ (Pin 27) is normally
100-300 ns. However, pulse may be any width if
pulse is entirely within window. If pulse occurs in
both windows, then pulse width must be less than
300 ns for MFM at CLK = 2 MHz and 600 ns for
FM at 2 MHz. Times double for 1 MHz.
2. A PPL Data Separator is recommended for 8"
MFM.
3. tbc should be 2Jls, nominal in MFM and 4Jls
nominal in FM. Times double when CLK = 1 MHz.
4. RCLK may be high or low during RAW READ
(Polarity is unimportant).
5. Times double when clock = 1 MHz.
6. Output timing readings are at VOL
0.8v and
VOH
2.0v.

V"

r--"P--I
w,

I

I

I

I

J

VIH

1_''1'1' --I

.. l

5 VI ..

~

1- 'M"--j

LJL
~'co,r·

--J 1-

=

TC02

STEP

MISCELLANEOUS TIMING
"FROM STEP RATE TABLE

Table 4. STATUS REGISTER SUMMARY
BIT
S7
86
S5
84
S3
S2
81
SO

ALL TYPE I
COMMANDS
NOT READY
WRITE
PROTECT
HEAD LOADED
SEEK ERROR
CRC ERROR
TRACK a
INDEX PULSE
BUSY

READ
ADDRESS
NOT READY

READ
SECTOR
NOT READY

RNF
CRC ERROR
LOST DATA
ORO
BUSY

RECORD TYPE
RNF
CRC ERROR
LOST DATA
LOST DATA
ORO
ORO
BUSY
BUSY

a
a

a

READ
TRACK
NOT READY

a
a
a
a

WRITE
SECTOR
NOT READY
WRITE
PROTECT
WRITE FAULT
RNF
CRC ERROR
LOST DATA
ORO
BUSY

WRITE
TRACK
NOT READY
WRITE
PROTECT
WRITE FAULT

a
a

LOST DATA
ORO
BUSY

STATUS FOR TYPE I COMMANDS
BIT NAME
87 NOT READY
S6
85
84
S3
82
81
80

MEANING
This bit when set indicates the drive is not ready. When reset it indicates that the drive
is ready. This bit is an inverted copy of the Ready input and logically "ored" with MR.
PROTECTED
When set, indicates Write Protect is activated. This bit is an inverted copy of WRPT
input.
HEAD LOADED When set, it indicates the head is loaded and engaged. This bit is a logical "and" of HLD
and HLT signals.
When set, the desired track was not verified. This bit is reset to a when updated.
SEEK ERROR
CRC ERROR
CRC encountered in 10 field.
TRACK 00
When set, indicates Read / Write head is positioned to Track O. This bit is an inverted
copy of the TROO input.
INDEX
When set, indicates index mark detected from drive. This bit is an inverted copy of the IP
input.
BUSY
When set, command is in progress. When reset no command is in progress.

1-74

Floppy Disk Controller Devices

STATUS FOR TYPE II AND III COMMANDS
BIT NAME
S7 NOT READY

S6 WRITE PROTECT
S5 RECORD TYPE
WRITE FAULT
S4 RECORD NOT
FOUND (RNF)
S3 CRC ERROR
S2 LOST DATA
S1 DATA REQUEST

SO BUSY

MEANING
This bit when set indicates the drive is not ready. When reset, it indicates that the
drive is ready. This bit is an inverted copy of the Ready input and "ORed" with MR.
The Type II and III Commands will not execute unless the drive is ready.
On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates a
Write Protect. This bit is reset when updated.
On Read Record: It indicates the record-type code from data field address mark. 1
= Deleted Data Mark. 0 = Data Mark. On any Write: It indicates a Write Fault. This
bit is reset when updated.
When set, it indicates that the desire track, sector, or side were not found. This bit
is reset when updated.
If S4 is set, an error is found in one or more ID fields; otherwise it indicates error in
data field. This bit is reset when updated.
When set, it indicates the computer did not respond to DRQ in one byte time. This
bit is reset to zero when updated.
This bit is a copy of the DRQ output. When set, it indicates the DR is full on a Read
Operation or the DR is empty on a Write operation. This bit is reset to zero when
updated.
When set, command is under execution. When reset, no command is under execution.
CIN & COUT = 15 pF max with all pins grounded
except one under test.
Operating temperature = ooe to 700 e
Storate temperature = -55°e to + 125°C

ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Voo with respect to Vss(ground): + 15 to -0.3V
Voltage to any input with respect to Vss = + 15
to -0.3V
Icc = 60 MA (35 MA nominal)
100 = 15 MA (10 MA nominal)

OPERATING CHARACTERISTICS (DC)
TA = OOC to 70°C, Voo = + 12V ± .6V, Vss = OV, Vee =
SYMBOL
IlL
10L
V1H
V1L
VOH
VOL
Po

CHARACTERISTIC
Input Leakage
Output Leakage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Power Dissipation

MIN.

+ 5V ± .25V
MAX.

UNITS

10
10

p.A
p.A
V
V
V
V
W

2.6
0.8
2.8
0.45
0.6

CONDITIONS
VIN = Voo **
VOUT = Voo

10 = -100J-LA
10 = 1.6mA

*1792 and 1794 10 = 1.0 rnA
**Leakage conditions are for input pins without internal pull-up resistors. Pins 22, 23, 33,36, and 37 have pullup resistors.

Floppy Disk Controller Devices

1-75

1-76

Floppy Disk Controller Devices

WESTERN

c

o

R

p

o

R

DIGITAL
A

o

T

N

FD179X Application Notes
INTRODUCTION

SYSTEM DESIGN

Over the past several years, the Floppy Disk Drive has
become the most popular on-line storage device for
mini and microcomputer systems. Its fast access
time, reliability and low cost-per-bit ratio enables the
Floppy Disk Drive to be the solution in mass storage
for microprocessor systems. The drive interface to the
Host system is standardized, allowing the OEM to
substitute one drive for another with minimum hardware/software modifications.

The first consideration in Floppy Disk DeSign is to
determine which type of drive to use. The choice
ranges from single-density single sided mini-floppy
to the 8" double-density double-sided drive. Figure 2
illustrates the various drive and data capacities
associated with each type. Although the 8" doubledensity drive offers twice as much storage, a more
complex data separator and the addition of Write
Precompensation circuits are mandatory for reliable
data transfers. Whether to go with 8" double-density
or not is dependent upon PC board space and the
additional circuitry needed to accurately recover data
with extreme bit shifts. The byte transfer time defines
the nominal time required to transfer one byte of data
from the drive. If the CPU used cannot service a byte
in this time, then a DMA scheme will probably be
required. The 179X also needs a few microseconds
for overhead, which is subtracted from the transfer
time. Figure 3 shows the actual service times that the
CPU must provide on a byte-by-byte basis. If these
times are not met, bytes of data will be lost during
a read or write operation. For each byte transferred,
the 179X generates a DRO (Data Request) Signal on
Pin 38. A bit is provided in the Status Register which
is also set upon receipt of a byte from the Disk. The
user has the option of reading the status register
through program control or using the DRO Line with
DMA or interrupt schemes. When the data register
is read, both the Status Register DRO bit and the ORO
Line are automatically reset. The next full byte will
again set the DRO and the process continues until
the sector(s) are read. The Write operation works
exactly the same way, except a WRITE to the Oata
Register causes a reset of both ORa's.

Since Floppy Disk Data is stored and retrieved as a
self-clocking serial data stream, some means of
separating the clock from the data and assembling
this data in parallel form must be accomplished. Data
is stored on individual Tracks of the media, requiring control of a stepper motor to move the ReadlWrite
head to a predetermined Track. Byte synchronization
must also be accomplished to ensure that the parallel
data is properly assembled. After all the design considerations are met, the final controller can consist
of 40 or more TTL packages.
To alleviate the burden of Floppy Disk Controller
design, Western Digital has developed a Family of
LSI Floppy Disk controller devices. Through its own
set of macro commands, the FD179X Controller
Family will perform all the functions necessary to read
and write data to the drive. Both the 8" standard and
5 %" mini-floppy are supported with Single or double density recording techniques. The FD179X is compatible with the IBM 3740 (FM) data format, or the
System 34 (M FM) standards. Provisions for nonstandard formats and variable sector lengths have
been included to provide more storage capability per
track. Requiring standard + 5, + 12 power supplies,
the FD179X is available in a standard 40-pin dual-inline package.
The FD179X Family consists of 6 devices. The differences between these devices is summarized in
Figure 1. The 1792 and 1794 are "single density only"
devices, with the Double Density Enable pin
(DDEN) left open by the user. Both True and inverted
Data Bus devices are available. Since the 179X can
only drive one TTL Load, a true data bus system may
use the 1791 with external inverting buffers to arrive
at a true bus scheme. The 1795 and 1797 are identical to the 1791 and 1793, except a side select output has been added that is controlled through the
Command Register.

F/oppy Disk Controller Devices

RECORDING FORMATS

The FD179X accepts data from the disk in a
Frequency- Modulated (FM) or Modified-FrequencyModulated (MFM) Format. Shown in Figures 4A and
4B are both these Formats when writing a hexidecimal byte of '02.' In the FM mode, the 8 bits of
data are broken up into "bit cells." Each bit cell begins
with a clock pulse and the center of the bit cell
defines the data. If the data bit = 0, no pulse is written; if the data
1, a pulse is written in the center
of the cell. For the 8" drive, each clock is written 4
microseconds apart.

=

1-77

."
C

......
......
co

><

In the MFM mode, clocks are decoded into the data
stream. The byte is again broken up into bit cells, with
the data bit written in the center of the bit cell if data
= 1. Clocks are only written if both surrounding data
bits are zero. Figure 4B shows that this occurs only
once between bit cell 4 and 5. Using this encoding
scheme, pulses can occur 2, 3 or 4 microseconds
apart. The bit cell time is now 2 microseconds; twice
as much data can be recorded without increasing the
Frequency rate due to the encoding scheme.

The Ao, A1, Lines used for register selections can be
configured at the CPU in a variety of ways. These lines
may actually tie to CPU address lines, in which case
the 179X will be memory-mapped and addressed like
RAM. They may also be used under Program Control
by tying to a port device such as the 8255, 6820, etc.
As a diagnostic tool when checking out the CPU interface, the Track and Sector registers should respond
like "RAM" when the 179X is idle (Busy = INTRa =
0).

The 179X was designed to be compatible with the IBM
3740 (FM) and System 34 (MFM) Formats. Although
most users do not have a need for data exchange with
IBM mainframes, taking advantage of these well
studied formats will ensure a high degree of system
performance. The 179X will allow a change in gap
fields and sector lengths to increase usable storage
capacity, but variations away from these standards
is not recommended. Both IBM standards are softsector format. Because of the wide variation in
address marks, the 179X can only support softsectored media. Hard sectored diskettes have continued to lose popularity, mainly due to the
unavailability of a standard and the limitation of sector lengths imposed by the physical sector holes in
the diskette.

Because of internal synchronization cycles, certain
time delays must be introduced when operating under
Programmed I/O. The worst case delays are:

PROCESSOR INTERFACE
The Interface of the 179X to the CPU consists of an
8-bit Bi-directional bus, read/write controls and
optional interrupt lines. By selecting the device via
the CHIP SELECT Line, each of the five internal
registers can be accessed.
Shown below are the registers and their addresses:
PIN 3 PIN 6 PIN 5
CS
A1
Ao
0
0
0
0
1

0
0
1
1
X

0
1
0
1
X

PIN 4
RE=O

PIN 2
WE= 0

STATUS REG
TRACK REG
SECTOR REG
DATA REG
H1-Z

COMMAND
REG
TRACK REG
SECTOR REG
DATA REG
H1-Z

OPERATION

NEXT
OPERATION

WRITE TO
READ STATUS
COMMAND REG REGISTER

DELAY REa'D
MFM = 14J..l s*
FM = 28J..l s

WRITE TO
READ FROM A NO DELAY
ANY REGISTER DIFFERENTREG
*NOTE: Times Double when ClK = 1MHz (5%"
drive).
Other CPU interface lines are ClK, MR and DDEN.
The ClK line should be 2 MHz (8" drive) or 1 MHz
(5 %" drive) with a 50% duty cycle. Accuracy should
be + 1 % (crystal source) since all internal timing,
including stepping rates, are based upon this clock.
The MR or Master Reset Line should be strobed a
minimum of 50 microseconds upon each power-on
condition. This line clears and initializes all internal
registers and issues a Restore Command (Hex '03')
on the rising edge. A quicker stepping rate can be
written to the Command Register after a MR,
in
which case the remaining steps will occur at the
faster programmed rate. The 179X will issue a maximum of 255 stepping pulses in an attempt to expect
the TROO line to go active low. This line should be
connected to the drive's TROO sensor.
The DDEN line causes selection of either single
density (DDEN = 1) or double density operation.
DDEN should not be switched during a read or
write operation.

Each time a command is issued to the 179X, the Busy
Bit is set and the INTRa (Interrupt Request) Line is
reset. The user has the option of checking the Busy
Bit or use the INTRa Line to denote command completion. The Busy Bit will be reset whenever the 179X
is idle and awaiting a new command. The INTRa Line,
once set, can only be reset by a READ of the Status
Register or issuing a new command. The MR (Master
Reset) Line does not affect INTRa.

1-78

Floppy Disk Controller Devices

FLOPPY DISK INTERFACE

The Floppy Disk Interface can be divided into three
sections: Motor Control, Write Signals and Read
Signals. All of these lines are capable of driving one
TIL load and not compatible for direct connection
to the drive. Most drives require an open-collector TIL
interface with high current drive capability. This must
be done on all outputs from the 179X. Inputs to the
179X may be buffered or tied to the drive's outputs,
providing the appropriate resistor termination networks are used. Undershoot should not exceed -0.3
volts, while integrity of V1H and VOH levels should be
kept within spec.
MOTOR CONTROL

Motor Control is accomplished by the STEP and DIRC
Lines. The STEP Line issues stepping pulses with a
period defined by the rate field in all Type I commands. The DIRC Line defines the direction of steps
(DIRC
1 STEP IN/DIRC
0 STEP OUn.

=

=

Other Control Lines include the fP or Index Pulse.
This Line is tied to the drives Index L.E.D. sensor and
'makes an active transition for each revolution of the
diskette. The TROO Line is another L.E.D. sensor
that informs the 179X that the stepper motor is at its
furthest position, over Track 00. The READY Line can
be used for a number of functions, such as sensing
"door open," Drive motor on, etc. Most drives provide
a programmable READY Signal selected by option
jumpers on the drive. The 179X will look at the ready
signal prior to executing READIWRITE commands.
READY is not inspected during any Type I commands.
All Type I commands will execute regardless of the
Logic Level on this Line.
WRITE SIGNALS

Writing of data is accomplished by the use of the WD,
WG, WF, TG43, EARLY and LATE Lines. The WG or
Write Gate Line is used to enable write current at the
drive's R/W head. It is made active prior to writing data
on the disk. The WF or WRITE FAULT Line is used
to inform the 179X of a failure in drive electronics.
This signal is multiplexed with the VFOE Line and
must be logically separated if required. Figure 5
illustrates three methods of demultiplexing.
The TG43 or "TRACK GREATER than 43" Line is used
to decrease the Write Current on the inner tracks,
where bit densities are the highest. If not required on
the drive, TG43 may be left open.
WRITE PRECOMPENSATION

The 179X provides three signals for double density
Write Precompensation use. These signals are WRITE
DATA, EARLY and LATE. When using single density
drives (eighter 8" or 5 1/4"), Write Precompensation
is not necessary and the WRITE DATA line is
generally TIL Buffered and sent directly to the drive.
In this mode, EARLY and LATE are left open.
For double density use, Write Precompensation is a
function of the drive. Some manufacturers recommend Precompensating the 5 1/4" drive, while others
do not.

Floppy Disk Controller Devices

With the 8" drive, Precompensation may be specified
from TRACK 43 on, or in most cases, all TRACKS.
If the recommended Precompensation is not
specified, check with the manufacturer for the proper configuration required.
The amount of Precompensation time also varies. A
typical value will usually be specified from 100-300ns.
Regardless of the parameters used, Write Precompensat ion must be done external to the 179X. When
DDEN is tied low, EARLY or LATE will be activated
at least 125ns. before and after the Write Data pulse.
An Algorithm internal to the 179X decides whether
to raise EARLY or LATE, depending upon the previous
bit pattern sent. As an example, suppose the recommended Precomp value has been specified at 150ns.
The following action should be taken:
EARLY

LATE

o
o

o

1

1

o

ACTION TAKEN

delay WD by 150 ns (nominal)
delay WD by 300ns (2X value)
do not delay WD

There are two methods of performing Write
Precompensation:
1)
2)

External Delay elements
Digitally

Shown in Figure 6 is a Precomp circuit using the
Western Digital 2143 clock generator as the delay element. The WD pulse from the 179X creates a strobe
to the 2143, causing subsequent output pulses on the
01, 02 and 03 signals. The 5K Precomp adjust sets
the desired Precomp value. Depending upon the condition of EARLY and LATE, 01 will be used for EARLY,
02 for nominal (EARLY
LATE
0), and 03 for LATE.
The use of "one-shots" or delay line in a Write
Precompensation scheme offers the user the ability
to vary the Precomp value. The 04 output resets the
74LS175 Latch in anticipation of the next WD pulse.
Figure 7 shows the WD-EARLY/LATE relationship,
while Figure 8 shows the timing of this write Precomp
scheme.

=

=

Another method of Precomp is to perform the function digitally. Figure 9 illustrates a relationship between the WD pulse and the CLK pin, allowing a digital
Precomp scheme. Figure 10 shows such a scheme
with a preset Write Precompensation value of 250ns.
The synchronous counter is used to generate 2 MHz
and 4 MHz clock Signals. The 2MHz clock is sent to
the CLK input of the 179X and the 4 MHz is used by
the 4-bit shift register. When a WD pulse is not present, the 4 MHz clock is shifting "ones" through the
shift register and maintaining Q D at a zero level.
When a WD pulse is present, a zero is loaded at either
A, B, or C depending upon the states of LATE, EN
PRECOMP and EARLY. The zero is then shifted by
the 4 MHz clock until it reaches the Q D output. The
number of shift operations determines whether the
WRITE DATA pulse is written early, nominal or late.
If both FM and MFM operations is a system requirement, the output of this circuit should be disabled
and the WD pulse should be sent directly to the drive.

1-79

"T1

C
......

......

(0

><

DATA SEPARATION

".....c
~

-_-"\,;'V\,.-------+--1~7 $>W

.114

PRECOMP.
ADJUST

FIGURE 6. 179X WRITE PRE·COMP

1-84

Floppy Disk Controller Devices

'TI
C

.....

~

-..j

~

2. 4"s

!;

500 NS

!;

co
""""

><

CLK TOL

50

WD

WD

I

I

-------------~

EARLY
OR LATE

EARLY
OR LATE

n

DOUBLE TIMES FOR 5· (MINI-FLOPPY)

250 NS MIN.

450 NS MIN.

125 NS MIN. VALID
FOR DURATION OF
WD PULSE

DOUBLE TIMES FOR 5· (MINI-FLOPPY)

VALID BEFORE LEADING EDGE OF WD

WRITE PRE-COMP TIMING FOR MFM

WRITE PRE-COMP TIMING FOR FM

FIGURE 7. WRITE PRE·COMP TIMING

BIT CELL 0

"

I

BIT CELL 1

I

t

we: .JclL....-__...,jQ

BIT

~ELL 2

I

BIT

~ELL 3

I

BIT CELL 4

I ~ 200NS
> 1~1oo>1f-_ _ _--'g

EARLY _ _ _ _ _ _ _ _

BIT CELL 5

9

I

BIT'IELL 7

rcI

. . _________'n
n

n

n

n

I

BIT CELL 8

~

P

I
rct

BIT CELL 9

"

n
n

____________~r_l~___________

C-LATE
C-NOMINAL

BIT 1ELL 6

~n

LATE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J

C-EARLY

I

n

.~L....-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____'

FIGURE 8. PRE·COMP TIMING FOR CIRCUIT IN FIGURE 6

Floppy Disk Controller Devices

1-85

"TI
C

SOOns

-.L

CLK
@1MHz

........
CD

><

SOOns

l

I
I

I
I

~

WD
(DDEN - 0)

,

•
!

~
/

\

~100ns

~100ns

2SOn$

CLK
@2MHz

250ns

Ii

1250s

I
WD
(DDEN - 0)

~SOns

:o3Ons

FIGURE 9. WD/CLK RELATIONSHIP FOR WRITE PRECOMP USE

7415181

'ern

3

A

•

B

•

C

~ ~
9

I5

----------0

0.1-".:..,.3

(TO 1791)

WRITE
DATE
rrODAIVE)

Wii
(FROM 179t)

0-----1

LATE
(FAOMt791)

TG43 (EN PRECQMP)

EARLY
(FROM 1791)

....-----<-~

FIGURE 10. DIGITAL WRITE PRECOMP CIRCUIT

(PROVIDED COURTESY OF MPI, OKLAHOMA CITY, OK 73112)

1-86

Floppy Disk Controller Devices

+5

R

R.

C = 150 NS

:!:

50

74123

RAW READ
FROM DRIVE

27

RAWREAD

1791/1793

26

+5

>--"""'---'-',..1 A
B

Oo/-'-----i

N.U.

RCLK

RG

C

o
4

CO

74LS74
CU
C

DDEN

+5
_14_ _

74LS193

CRYCLK
TYPE

CRYCLK

8" FM

8 MHz

5" MFM

8 MHz

5" FM

4 MHz

FIGURE 11. COUNTER / SEPARATOR

Floppy Disk Controller Devices

1-87

X6l~a:l

~

I

-:u:0
0

~

0

m

0

C
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m

en
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tb"

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S
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OB
00

o:xJ

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03

05

-ul>
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06

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_en l>
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07

-len

0

02

0 .....
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mm

:;:,

01

04

OX

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01

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cri

01

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DATA

00

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ADDRESS

05

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»
s:
»

02
03
04

14

05

15

06
07
08
09
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---.!!...

OB

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RETARD BY 2 COUNTS
27

RAW READ

ADVANCE BY 2 COUNTS

RE~~g~TA

)

.

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26

DRIVE
ADVANCE BY 1 COUNT

RCLK

01

12
13

17

NONE
RETARD BY 1 COUNT

00

11

16

ACTION TAKEN

OC

lA

0

+5

745288 PROGRAMMING TABLE

0

0

OC
OE

FREE RUN

+5
179X·Ol

+5

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9.
~

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1600

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1300~F

2%

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VR2

101ffi
1%

5.6V
5%

+5
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R19
2.2Kn

3.431<0

CR2
IN914

1%

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oG)
o§

STEERING 1

em
~

+ 12o--IVr---.....--......,

~ R21

R12
B060
1%

::D

~

R16
10KO

Rll
1400

+5

~
:::s

~.

.....

R23
1.2Kn

+5

6

-",

R32

m~

2.2Kn

~;E

R33

U3

3.4BKn
1%

VFO CLK

Or-

STEERING 2

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IN914
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II

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RAWREAD

(E) 1

EN PRE-COMP

(G) 1

VFOE

»0
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4

~

,~74S112

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o~
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CLK

a

2 K

+5

......

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TG43

~
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~

~ 200 NS:!: 25

-

~ RAW READ

RAWDATA-U
FROM DRIVE

+5
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SINGLE
DENSITY
DOUBLE

~DENSITYI

FD179X

~

+5V

,~

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i5

c
m
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Cl

tj

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r-

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74S124 I 2
FC
47K

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lOOK
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The internal device timing is generated from an external crystal clock.

WRITE DATA
(TO DISK)

AM Detector· The address mark detector detects ID,
data and Index address marks during read and write
operations.
Write Precompensation • enables write precompensation to be performed on the Write Data ouput.

WRITE
PRECOMP

PLA
CONTROL
1230 X 16)

__

0151<

CONTROL

1~~~RTfRAG

E

--~

Figure 2. WD279X BLOCK DIAGRAM
Data Separator - a high performance Phase-Lock-Loop
Data Separator with on-chip VCO and phase comparator allows adjustable frequency range for 5 %"
or 8" Floppy Disk interfacing.
PROCESSOR INTERFACE
The Interface to the processor is accomplished
through the eight Data Access Lines (DAL) and
associated control signals. The DAL are used to
transfer Data, Status, and Control words out of, or
into the WD279X. The DAL are three state buffers that
are enabled as output....Qrivers when Chip Select
(CS) and Read Enable (RE) are activL(low logic
state) or act as input receivers when CS and Write
Enable (WE) are active.
When transfer of data with the Floppy Disk Controller
is required by the host processor, the device address
is decoded and CS is made low. The address bits A 1

1-96

and AO, combined with the signals RE during a
Read operation or WE during a Write operation are
interpreted as selecting the following registers:
A1

AD

0
0
1
1

0
1
0
1

-

READ (RE)
Status Regiser
Track Register
Sector Register
Data Register

WRITE (WE)
Command Register
Track Register
Sector Register
Data Register

During Direct Memory Access (DMA) types of data
transfers between the Data Register of the WD279X
and the processor, the Data Request (DRO) output
is used in Data Transfer control. This Signal also
appears as status bit 1 during Read and Write
operations.

Floppy Disk Controller Devices

"
On Disk Read operations the Data Request is
activated (set high) when an assembled serial input
byte is transferred in parallel to the Data Register. This
bit is cleared when the Data Register is read by the
processor. If the Data Register is read after one or
more characters are lost, by having new data transferred into the register prior to processor readout, the
lost Data bit is set in the Status Register. The Read
operation continues until the end of sector is reached.
On Disk Write operations the Data Request is
activated when the Data Register transfers its contents to the Data Shift Register, and requires a new
data byte. It is reset when the Data Register is loaded
with new data by the processor. If new data is not
loaded at the time the next serial byte is required by
the Floppy Disk, a byte of zeroes is written on the
diskette and the lost Data bit is set in the Status
Register.
At the completion of every command an INTRQ is
generated. INTRQ is reset by either reading the status
register or by loading the command register with a
new command. In addition, INTRQ is generated if a
Force Interrupt command condition is met.
The WD279X has two modes of operation according
to the state of DDEN (Pin 37). When DDEN = 1,
Single Density (FM) is selected. When DDEN = 0,
Double Density (MFM) is selected. In either case, the
ClK input (Pin 24) is set at 2 MHz for 8" drives or 1
MHz for 5 1/4" drives.
On the WD2791IWD2793, the ENMF input (Pin 25)
can be used for controlling both 5 1/4" and 8" drives
with a single 2 MHz clock. When ENMF = 0, an
internal -;- 2 of the ClK is performed. When ENMF
= 1, no divide takes place. This allows the use of
a 2 MHz clock for both 5 1/4" and 8" configurations.
The internal VCO frequency must also be set to the
proper value. The 5/8 input (Pin 17) is used to select
data separator operation by internally dividing the
Read Clock. When 5/8 = 0, 5 1/4" data separation
is selected; when 5/8 = 1, 8" drive data separation
is selected.
CLOCK (24)
2 MHz
2 MHz
1 MHz

ENMF

(25)

5/8 (17)

DRIVE

1

8"
5%
5%

1

a
1

a
a

In addition to the WD179X, the WD279X contains an
internal Data Separator and Write precompensation
circuit. The TEST (Pin 22) line is used to adjust both
data separator and precompensation. When
TEST = 0, the WD (Pin 31) line is internally connected
to the output of the write precomp one-shot. Adjustment of the WPW (Pin 33) line can then be
accomplished.
A second one-shot tracks the precomp setting at
approximately 3:1 to insure adequate Write Data pulse
widths.
Similarly, Data separation is also adjusted with TEST
= O. The TG43 (Pin 29) line is Internally connected
to the output of the read data one-shot, which is
adjusted via the RPW (Pin 18) line. The DIRC (Pin 16)
line contains the Read Clock output (.5 MHz for 8"
drives). The VCO Trimming capacitor (Pin 26) is
adjusted for center frequency.
Internal timing signals are used to generate pulses
during the adjustment mode so that these
adjustments can be made while the device is incircuit. The TEST line also contains a pull-up resistor,
so adjustments can be performed simply by grounding the TEST pin, overriding the pull-up. The TEST
pin cannot be used to disable stepping rates during
operation as its function is quite different from the
WD179X.
Other pins on the device also include pull-up resistors
and may be left oBen to satisfy a lo~ondition.
These are: ENP, 5/8, ENMF, WPRT, DDEN, HlT,
TEST, and MR.
GENERAL DISK READ OPERATIONS
Sector lengths of 128, 256, 512 or 1024 are obtainable in either FM or MFM formats. For FM, DDEN
should be placed to logical "1." For MFM formats,
DDEN should be placed to a logical "a". Sector
lengths are determined at format time by the fourth
byte in the "10" field.
Sector length Table *
Sector length
Field (hex)

Number of Bytes
in Sector (decimal)

00
01
02
03

128
256
512
1024

FUNCTIONAL DESCRIPTION

*2795/97 may vary - see command summary.

The WD279X-02 is software compatible with the
FD179X-02 series of Floppy Disk Controllers. Commands, status, and data transfers are performed in
the same way. Software generated for the 179X can
be transferred to a 279X system without modification.

The WD279X recognizes tracks and sectors numbered
OQ-FF Hex. However, due to programming restrictions,
only tracks and sectors 00 through F4 can be
formatted.

Floppy Disk Controller Devices

1-97

:ec
N

......

CD

~

o

N

GENERAL DISK WRITE OPERATION

READY

When writing is to take place on the diskette the Write
Gate ~G) output is activated, allowing current to flow
into the ReadlWrite head. As a precaution to
erroneous writing the first data byte must be loaded
into the Data Register in response to a Data Request
from the WD279X before the Write Gate signal can
be activated.

Whenever a Read or Write command (Type II or III)
is received the WD279X samples the Ready input. If
this Input is logic low, the command is not executed
and an interrupt is generated. All Type I commands
are performed regardless of the state of the Ready
input. Also, whenever a Type II or III command is
received, the TG43 signal output is updated. TG43
may be tied to ENP to enable write precompensation
on tracks 44-76.

Writing is inhibited when the Write Protect input is
a logic low, in which case any Write command is
immediately terminated, an interrupt is generated and
the Write Protect status bit is set.
For write operations, the WD279X provides Write Gate
(Pin 30) and Write Data (Pin 31) outputs. Write data
consists of a series of pulses set to a width approximately three times greater then the precomp adjustment. Write Data provides the unique address marks
in both formats.

1-98

COMMAND DESCRIPTION

The WD279X will accept eleven commands. Command words should only be loaded in the Command
Register when the Busy status bit is off (Status bit
0). The one exception is the Force Interrupt command.
Whenever a command is being executed, the Busy
status bit is set. When a command is completed, an
interrupt is generated and the Busy status bit is reset.
The Status Register indicates whether the completed
command encountered an error or was fault free. For
ease of discussion, commands are divided into four
types. Commands and types are summarized in
Table 1.

Floppy Disk Controller Devices

TABLE 1. COMMAND SUMMARY

B. Commands for Models: WD2795, WD2797

A. Commands for Models: WD2791, WD2793
Type Command
I
I
I
I
I
II
II
III
III
III
IV

Bits

3

2

a a a a h
a a a 1 h
a a 1 T h
a 1 a T h
a 1 1 T h
1
a a m S
1
a 1 m S
1
1
a a a
1
1
1
a a
1
1
1
1
a
1
1
a 1 '3

V
V
V
V
V
E

7

Restore
Seek
Step
Step-in
Step-out
Read Sector
Write Sector
Read Address
Read Track
Write Track
Force Interrupt

Bits
5
4

6

E
E
E
E
'2

1
r1
r1
ro
r1
r1
C
C

6

5

3

2

a a a a h
a a a 1 h
a a 1 T h
a 1 a T h
a 1 1 T h
a 1 a a m L
aO
1
a 1 m L
a a 1 1 a 0 a
a a 1 1 1 0 a
a a 1 1 1 1 a
'1
'a 1 1 a 1 '3

V
V
V
V
V
E
E
E
E
E
'2

0
ro
ro
ro
ro
ro

7

4

1
r1
r1
r1
r1
r1
U
U
U
U
U
'1

0
ro
ro
ro
ro
ro

a

aO

a
a
a
'a

TABLE 2. FLAG SUMMARY

Command
Type

Bit
No(s)

I

0, 1

I

2

V

= Track Number Verify Flag

I

3

h

= Head Load Flag

I

4

T

II & III

a

= Track Update Flag
ao = Data Address Mark

II

1

C

= Side Compare Flag

II & III

1

U

= Update SSO

II & III

2

E

= 15 MS Delay

II

3

S

= Side Compare Flag

II

3

L

= Sector Length Flag

II

4

IV

0-3

Description

=

r1 rO
Stepping Motor Rate See
Table 3 for Rate Summary

m

= Multiple Record

Flag

= O,No verify
= 1,Verify on destination track
= O,Unload head at beginning
= 1,Load head at beginning
T = O,No update
T = 1,Update track register
aO = O,FB(DAM)
aO = 1,F8(deleted DAM)
C = O,Disable side compare
C = 1,Enable side compare
U = O,Update SSO to a
U = 1,Update SSO to 1
E = O,No. 15 MS delay
E = 1,15 MS delay (30 MS for 1 Mhz)
S = O,Compare for side a
S = 1,Compare for side 1
V
V
h
h

LSB's Sector Length in ID Field
00
01
10
11
L
L
m
m

512
= a 256
256
= 1 128
= O,Single record
= 1,Multiple records

1024
512

128
1024

= Interrupt Condition Flags
'1 = 1 Ready To Not Ready Transition
'2 = 1 Index Pulse
'3 = 1 Immediate Interrupt, Requires A Reset"
'3-'0 = a Terminate With No Interrupt (INTRQ)
'x

'a = 1 Not Ready To Ready Transition

NOTE: See Type IV Command Description for further information.

Floppy Disk Controller Devices

1-99

WRITE PRECOMPENSATION

When operating in Double Density mode (DDEN = 0),
the WD279X has the capability of providing a userdefined precompensation value for Write Data. An
external potentiometer (10K) tied to the WPW signal
(Pin 33) allows a setting of 100 to 300 ns from nominal.
Setting the Wr.i1e.precomp value is accomplished by
forcing the TEST line (Pin 22) to a logic O. A stream
of pulses can then be seen on the Write Data (Pin
31) line. Adjust the WPW Potentiometer for the desired
pulse width. This adjustment may be performed..ln:
circuit since Write Gate (Pin 30) is inactive while TEST
=0.

response of the VCP to bit-shifted data (jitter) as well
as the response to normal frequency shift, i.e., the
lock-up time. A balance must be accomplished between the two conditions to inhibit overresponsiveness to jitter and to prevent an extremely
wide lock-up response, leading to PUMP runaway. The
filter affects these two reactions in mutually opposite
directions.
The following Filter Circuit is recommended for 8"
FM/MFM:
PUMP
(PIN 23)

~

DATA SEPARATION

The WD279X can operate with either an external data
separator or its QWDJnternal recovery circuits. The
condi1i2n of the TEST line (Pin 22) in conjunction
with MR (Pin 19) will select internal or external mode.
To program the 279X for extem.al VCO, a MR
pulse must be applied while TEST = O. A clock
equivalent to eight times the data rate (e.g., 4.0 MHz
for 8" Double Density) is applied to the VCO input
(Pin 26). The feedback reference voltage is available
on the Pump output .(Ein.23) for external integration
to control the VCO. TEST is returned to a logic 1
for normal operation.
Note: To maintain this mode, TEST must be held
low whenever MR is applied.
For internal VCQQperation, the TEST line must be
high during the MR pulse, then set to a logic 0 for
the adjustment procedure.
A 50K Potentiometer tied to the RPW input (Pin 18)
is used to set the internal Read Data pulse for proper phasing. With a scope on Pin 29 (TG 43), adjust
the RPW pulse (250 ns for 8" Double Density). An external variable capacitor of C-60 pf is tied to the VCO
input (Pin 26). It is highly recommended to use at least
a negative 3500 PPM Temperature coefficient trimmer capacitor. With a frequency counter on Pin 16
(DIRC) adjust the trimmer cap to yield the appropriate
Data....Ba1e. (500 KHz for 8" Double .Density).
The DDEN line must be low while the 5/8 line is
held high or the adjustment times above will be
doubled.
After adjustments have been made, the TEST pin
is returned to a logic 1 and the device is ready for
operation. Adjustments may be made in-circuit since
the DIRe and TG43 lines may toggle without affecting the drive.
The PUMP output (Pin 23) consists of positive and
negative pulses, which their duration is equivalent to
the phase difference of incoming Data vs. VCO frequency. This signal is intemally connected to the VCO
input, but a filter is needed to connect these pulses
to a slow moving DC voltage.
The internal phase-detector is unsymmetrical for a
random distribution of data pulses by a factor of two,
in favor of a PUMP UP condition. Therefore, it is
desirable to have a PUMP DOWN twice as responsive to prevent run-away during a lock attempt.
A first order lag-lead filter can be used at the PUMP
output (Pin 23). This filter controls the instantaneous

1-100

.1~fh

lKQP

IN914

Since 5114" Drives operate at exactly one-half the data
rate (250 Kb/sec) the above capacitor should be
doubled to .2 or .22 ",f.
NOTE 1: A Diode with the lowest on resistance will
enhance PUMP response.
NOTE 2: It is recommended to replace the 1K resistor
with a 1K (nominal at 25°c) thermister (approximating
400 ohms at 50°c and approximatley 2.8K ohms at
OOc) to improve capture range.
TYPE I COMMANDS

The Type I Commands include the Restore, Seek,
Step, Step-in, and Step-Out commands. Each of the
Type I Commands contains a rate field (ro r1), which
determines the stepping motor rate as defined in
Table 3.
A q,s (MFM) or 4",s (FM) pulse is provided as an output to the drive. For every step pulse issued, the drive
moves one track location in a direction determined
by the direction output. The chip will step the drive
in the same direction it last stepped unless the command changes the direction. .
The direction signal is active high when stepping in
and low when stepping out. The direction signal is
valid before the first stepping pulse is generated. The
rates (shown in Table 3) can be applied to a StepDirection Motor through the device interface.
TABLE 3. STEPPING RATES

ClK
R1
0
0
1
1

RO
0
1
0
1

2 MHz
TEST= 1
3 ms
6 ms
10 ms
15 ms

1 MHz
TEST
1
6 ms
12 ms
20 ms
30 ms

=

After the last directional step, an additional 15
milliseconds of head settling time takes place if the
Verify flag is set in Type I commands. Note that this
time doubles to 30 ms for a 1 MHz clock. There is
also a 15 ms head settling time if the E flag is set
in any Type" or '" command.

Floppy Disk Controller Devices

When a Seek, Step, or Restore command is executed
an optional verification of Read-Write head position
can be performed by setting bit 2 (1/
1) in the command word to a logic 1. The verification operation
begins at the end of the 15 millisecond settling time
after the head is loaded against the media. The track
number from the first encountered ID Field is compared against the contents of the Track Register. If
the track numbers compare and the ID Field Cyclic
Redundancy Check (CRG) is correct, the verify operation is complete and an INTRQ is generated with no
errors. If there is a match but not a valid CRC, the
CRC error status bit is set (Status bit 3), and the next
encountered ID field is read from the disk for the
verification operation.
The WD279X must find an ID field with correct track
number and correct CRC within 5 revolutions of the
media; otherwise the seek error is set and an INTRQ
is generated. If V = 0, no verification is performed.
The Head Load (HLD) output controls the movement
of the read/write head against the media. HLD is
activated at the beginning of a Type I command if
the h flag is set (h = 1), at the end of the Type I command if the verify flag (1/ = 1), or upon receipt of any
Type II or III command. Once HLD is active it remains
active until either a Type I command is received with
(h = and V = 0); or if the WD279X is in an idle state
(non-busy) and 15 index pulses have occurred.
Head Load timing (HLT) is an input to the WD279X
which is used for the head engage time. When HLT
= 1, the WD279X assumes the head is completely
engaged. The head engage time is typically 30 to 100
ms depending on drive. The low to high transition on
HLD is typically used to fire a one shot. The output
of the one shot is then used for H LT and supplied
as an input to the WD279X.

=

RESTORE (SEEK TRACK 0)

Upon receipt of this command the Track OO(TROO)
input is sampled. If TROO is active low indicating the
Read- Write head is positioned over track 0, the Track
Register is loaded with zeroes and an interrupt is
generated. If TROO is not active low, stepping pulses
at a rate specified by the r1 rO field are issued until
the TROO input is activated. At this time the Track
Register is loaded with zeroes and an interrupt is
generated. If the TROO input does not go active low
after 255 stepping pulses, the WD279X terminates
operation, interrupts, and sets the Seek error status
bit. A verification operation also takes place if the V
flag is set. The h bit allows the head to be loaded
at the start of command. Note that the Restore command is executed when MR goes from an active to
an inactive state.
SEEK
T~is command assumes that the Track Register contains the track number of the current position of the
Read/Write head and the Data Register contains
the desired tr~ck num~er. The WD279X will update
the Track register and Issue stepping pulses in the

°

HLD~

t----;I
HLT (FROM ONE SHOTI

HEAD LOAD TIMING

When both HLD and HLT are true, the WD279X will
then read from or write to the media. The "and" of
HLD and HLT appears as status Bit 5 in Type I status.
In summary for the Type I commands: if h = and
V = 0, HLD is reset. If h = 1 and V = 0, HLD is set
at the beginning of the command and HLT is not
sampled nor is there an internal 15 ms delay. If h
and V = 1, HLD is set near the end of the command, an internal 15 ms occurs, and the WD279X
waits for HLT to be true. If h = 1 and V = 1, HLD
is set at the beginning of the command. Near the end
of the command, after all the steps have been issued
an internal 15 ms delay occurs and the WD279X the~
waits for HLT to occur.
For Type II and III commands with E flag off, HLD
is made active and HLT is sampled until true. With
E flag on, HLD is made active, an internal 15 ms delay
occurs and then HLT is sampled until true.

°

°

F/oppy Disk Controller Devices

=

TYPE I COMMAND FLOW

1-101

~

C

VERIFY
SEQUENCE

N

......

,co

,~

o

N

NOTE'MHI THERE I" A

'\()M..,

OEt A'f

TYPE I COMMAND FLOW

TYPE I COMMAND FLOW

appropriate direction until the contents of the Track
register are equal to the contents of the Data Register
(the desired track location). A verification operation
takes place if the V flag is on. The h bit allows the
head to be loaded at the start of the command. An
interrupt is generated at the completion of the command. Note: When using multiple drives, the track
register must be updated for the drive selected before
seeks are issued.

An interrupt is generated at the completion of the
command.

STEP

Upon receipt of this command, the WD279X issues
one stepping pulse to the disk drive. The stepping
motor direction is the same as in the previous step
command. After a delay determined by the r1 rO field,
a verification takes place if the V flag is on. If the T
flag is on, the Track Register is updated. The h bit
allows the head to be loaded at the start of the
command.

1-102

STEP-IN

Upon receipt of this command, the WD279X issues
one stepping pulse in the direction away from track
zero. If the T flag is on, the Track Register is
incremented by one. After a delay determined by the
r1 rO field, a verification takes place if the V flag is on.
The h bit allows the head to be loaded at the start
of the command. An interrupt is generated at the completion of the command.
STEP-OUT

Upon receipt of this command, the WD279X issues
one stepping pulse in the direction towards track O.
If the T flag is on, the Track Register is decremented
by one. After a delay determined by the r1 rO field, a

Floppy Disk Controller Devices

verification takes place if the V flag is on. The h bit
allows the head to be loaded at the start of the command. An interrupt is generated at the completion of
the command.
EXCEPTIONS

On the W02795/7 devices, the SSO output is not
affected during Type I commands, and an internal
side compare does not take place when the M Verify
Flag is on.
TYPE II COMMANDS

The Type II Commands are the Read Sector and Write
Sector commands. Prior to loadng the Type II Command into the Command Register, the computer must
load the Sector Register with the desired sector
number. Upon receipt of the Type II command, the
busy status Bit is set. If the E flag = 1 (this is the
normal case) HLO is made active and HLT is sampled
after a 15 msec delay. If the E flag is 0, the head is
loaded and HLT sampled with no 15 msec delay.

TYPE II COMMAND

TYPE II COMMAND

Floppy Disk Controller Devices

When an 10 field is located on the disk, the W0279X
compares the Track Number on the 10 field with the
Track Register. If there is not a match, the next encountered 10 field is ready and a comparison is again
made. If there was a match, the Sector Number of
the 10 field is compared with the Sector Register. If
there is not a Sector match, the next encountered 10
field is read off the disk and comparisons again made.
If the 10 field CRC is correct, the data field is then
located and will be either written into, or read from
depending upon the command. The W0279X must
find an 10 field with a Track number, Sector number,
side number, and CRC within 5 revolutions of the disk;
otherwise, the Record Not Found status bit is set
(Status bit 4) and the command is terminated with
an interrupt.
Each of the Type II Commands contains an (m) flag
which determines if multiple records (sectors) are to
be read or written, depending upon the command. If
m = 0, a single sector is read or written and an interrupt is generated at the completion of the
command.

1-103

WRITE SECTOR
SEQUENCE

READ SECTOR
SEQUENCE

NO

TYPE II COMMAND

TYPE II COMMAND

If m = 1, multiple records are read or written with
sector register internally updated so that an address
verification can occur on the next record. The WD279X
will continue to read or write multiple records and
update the sector register in numerical ascending
sequence until the sector register exceeds the
number of sectors on the track or until the Force Interrupt command is loaded into the Command Register
which terminates the command and generates a~
interrupt.
For example: If the WD279X is instructed to read sector 27 and there are only 26 on the track the sector
register exceeds the number available. The WD279X
will search for 5 disk revolutions, interrupt out, reset
busy, and set the Record Not Found status bit.
The Type II commands for WD2791-93 also contain side
select compare flags. When C 0 (Bit 1) no side comparison is made. When C = 1, the LSB of the side
number is read off the ID field of the disk and compared
with the contents of the (S) flag (Bit 3). If the S flag compares with the side number recorded in the ID field,

the WD279X continues with the ID search. If a comparison is not made within 5 index pulses, the interrupt line is made active and the Record-Not-Found
status bit is set.
The Type" and III for the WD2795-97 contain a side
select flag (Bit 1). When U
0, SSO is updated to
O. Similarly, U = 1 updates SSO to 1. The chip compares the SSO to the ID field. If they do not compare
within 5 revolutions the interrupt line is made active
and the RNF status bit is set.
The WD279517 READ SECTOR and WRITE SECTOR
~omm~nds include a "L' flag. The "L' flag, in conjunction with the sector length byte of the ID field allows
different byte lengths to be implemented in e~ch sector. For IBM compatibility. the "L' flag should be set
to one.

=

1-104

=

READ SECTOR

Upon receipt of the Read Sector command, the head
is loaded, the Busy status bit set, and when an ID

Floppy Disk Controller Devices

field is encountered that has the correct track number,
correct sector number, correct side number, and correct CRC, the data field is presented to the computer.
The Data Address Mark of the data field must be
found within 30 bytes in single density and 43 bytes
in double density of the last ID field CRC byte; if not,
the ID field search is repeated.
When the first character or byte of the data field has
been shifted through the DSRj it is transferred to the
DR, and DRO is generated. When the next byte is accumulated in the DSR, it is transferred to the DR and
another DRO is generated. If the computer has not
read the previous contents of the DR before a new
character is transferred that character is lost and the
Lost Data Status Bit is set. This sequence continues
until the complete data field has been inputted to the
computer. If there is a CRC error at the end of the
data field, the CRC error status bit is set, and the command is terminated (even if it is a multiple sector
command).
At the end of the Read operation, the type of Data
Address Mark encountered in the data field is
recorded in the Status Register (Bit 5) as shown:
STATUS
BIT 5
1

o

Deleted Data Mark
Data Mark

TYPE III COMMANDS
READ ADDRESS

Upon receipt of the Read Address command, the head
is loaded and the Busy Status Bit is set. The next
encountered ID field is then read in from the disk, and
the six data bytes of the ID field are assembled and
transferred to the DR, and a DRO is generated for
each byte. The six bytes of the ID field are shown
below:
TRACK
SIDE
SECTOR SECTOR CRC k:;RC
2
1
ADDR NUMBER AD DR LENGTH
1

WRITE SECTOR

Upon receipt of the Write Sector command, the head
is loaded (HLD active) and the Busy status bit is set.
When an ID field is encountered that has the correct
track number, correct sector number, correct side
number, and correct CRC, a DRO is generated. The
WD279X counts off 11 bytes in single density and 22
bytes in double density from the CRC field and the
Write Gate ~G) output is made active if the DRO is
serviced (Le., the DR has been loaded by the computer). If DRO has not been-serviced, the command
is terminated and the Lost Data status bit is set. If
the DRO has been serviced, the WG is made active
and six bytes of zeroes in single density and 12 bytes
in double density are then written on the disk. At this
time the Data Address Mark is then written on the
disk as determined by the aO field of the command
as shown below:

aO

Data Address Mark (Bit 0)

1

Deleted Data Mark
Data Mark

o

The WD279X then writes the data field and generates
DRO's to the computer. If the DRO is not serviced
in time for continuous writing the Lost Data Status
Bit is set and a byte of zeroes is written on the disk.
The command is not terminated. After the last data
byte has been written on the disk, the tWO-byte CRC
is computed internally and written on the disk
followed by one byte of FE in FM or in MFM. The WG
output is then deactivated. For a 2 MHz clock the
INTRa will set 8 to 1211sec after the last CRC byte
is written. For partial sector writing, the proper
method is to write the data and fill the balance with
zeroes. By letting the chip fill the zeroes, errors may
be masked by the lost data status and improper CRC
Bytes.

Floppy Disk Controller Devices

2

3

4

5

6

Although the CRC characters are transferred to the
computer, the WD279X checks for validity and the
CRC error status bit is set if there is a CRC error. The
Track Address of the ID field is written into the sector register so that a comparison can be made by the
host. At the end of the operation an interrupt is
generated and the Busy Status is reset.
READ TRACK

Upon receipt of the READ track command, the head
is loaded, and the Busy Status bit is set. Reading
starts with the leading edge of the first encountered
index pulse and continues until the next index pulse.
All Gap, Header, and data bytes are assembled and
transferred to the data register and DRO's are
generated for each byte. The accumulation of bytes
is synchronized to each address mark encountered.
An interrupt is generated at the completion of the
command.
This command has several characteristics which
make it suitable for diagnostic purposes. They are:
no CRC checking is performed; gap information is

1-105

included in the data stream; the internal side compare is not performed; and the address mark detector is on for the duration of the command. Because
the AM. detector is always on, write splices or noise
may cause the chip to look for an AM. If an address
mark does not appear on schedule the Lost Data
status flag will be set.
The ID AM., ID field, ID CRC bytes, DAM, Data and
Data CRC Bytes for each sector will be correct. The
Gap Bytes may be read incorrectly during write-splice
time because of synchronization.
Because these synchronization problems almost
always occur in the Data Area, this command will not
function as a Track Copy and should be used only
as a Diagnostic Program to test the ability to read
addresses.
WRITE TRACK FORMATTING THE DISK

(Refer to section on Type III commands for flow
diagrams.)
Formatting the disk is a relatively simple task when
operating programmed 1/0 or when operating under
DMA with a large amount of memory. Data and gap
information must be provided at the computer interface. Formatting the disk is accomplished by positioning the RNJ head over the desired track number
and issuing the Write Track command.
Upon receipt of the Write Track command, the head
is loaded and the Busy Status bit is set. Writing starts
with the leading edge of the first encountered index
pulse and continues until the next index pulse, at
which time the interrupt is activated. The Data
Request is activated immediately upon receiving the
command, but writing will not start until after the first
byte has been loaded into the Data Register. If the
DR has not been loaded by (within three byte times)
the operation is terminated making the device Not
Busy, the Lost Data Status Bit is set, an the interrupt
is activated. If a byte is not present in the DR when
needed, a byte of zeroes is substituted.
This sequence continues from one index mark to the
next index mark. Normally, whatever data pattern
appears in the data register is written on the disk with
a normal clock pattern. However, if the WD279X
detects a data pattern of F5 through FE in the data
register, this is interpreted as data address marks with
missing clocks or CRC generation.

TYPE III COMMAND WRITE TRACK

The CRC generator is initialized when any data byte
from Fa to FE is about to be transferred from the DR
to the DSR or by receipt of F5 in MFM. An F7 pattern will generate two CRC characters in FM or MFM

1-106

Floppy Disk Controller Devices

or by receipt of F5 in MFM. An F7 pattern will
generate two CRC characters in FM or MFM. As a
consequence, the patterns F5 through FE must not
appear in the gaps, data fields, or ID fields. Also,
CRC's must be generated by an F7 pattern.
Disks may be formatted in IBM 3740 or System 34
formats with sector lengths of 128, 256, 512, or 1024
bytes.
TYPE IV COMMANDS
The Forced Interrupt command is generally used to
terminate a multiple sector Read or Write Command
or to insure Type I status in the Status Register. This
command can be loaded into the command register
at any time. If there is a current command under ex·
ecution (busy status bit set) the command will be ter·
minated and the busy status bit reset.
The lower four bits of the command determine the
conditional interrupt as follows:
10 = Not-Ready to Ready Transition
11 = Ready to Not-Read Transition
12
Every Index Pulse
13 = Immediate Interrupt
The conditional interrupt is enabled when the corresponding bit positions of the command (13 .I0) are
set to a 1. Then, when the condition for interrupt is
met, the INTRQ line will go high signifying that the
condition specified has occurred. If 13 .10 are all set
to zero (HEX DO), no interrupt will occur but any command presently under execution will be immediately
terminated. When using the immediate interrupt condition (13 = 1), an interrupt will be immediately
generated and the current command terminated.
Reading the status or writing to the command register
will not automatically clear the interrupt. The HEX DO
is the only command that will enable the immediate
interrupt (HEX D8) to clear on a subsequent load command register or read status register operation. Follow
a HEX D8 with DO command.
Wait 8 micro sec (double density) or 16 micro sec
(single density) before issuing a new command after
issuing a forced interrupt (times double when clock
= 1 MHz). loading a new command sooner than this
will nullify the forced interrupt.
Forced interrupt stops any command at the end of
an internal micro-instruction and generates INTRQ
when the specified condition is met. Forced interrupt
will wait until AlU operations in progress are comTYPE III COMMAND WRITE TRACK
plete (CRC calculations, compares, etc.).
CONTROL BYTES FOR INITIALIZATION
DATA PATTERN
WD279X INTERPRETATION
WD279X INTERPRETATION
IN DR (HEX)
IN MFM (DDEN
O)
IN FM (DDEN
1)
00 thru F4
FF
Write 00 thru F4, in MFM
Write 00 thru F4 with ClK
Write A1* in MFM, Preset CRC
F5
Not Allowed
Write C2** in MFM
F6
Not Allowed
F7
Generate 2 CRC bytes
Generate 2 CRG bytes
F8 thru FB
Write F8 thru FB, ClK
C7, Preset CRC Write F8 thru FB, in MFM
FC
Write FC in MFM
Write FC with ClK
D7
FD
Write FD in MFM
Write FD with ClK
FF
FE
Write FE, ClK
C7, Preset CRC
Write FE in MFM
Write FF in MFM
FF
FF
Write FF with ClK

=

=
=

=
=
=
=

*Missing clock transition between bits 4 and 5.

Floppy Disk Controller Devices

=

=

**Missing clock transition between bits 3 and 4.

1-107

:E
cI\,)
......

CD

><
I

o

I\,)

More than one condition may be set at a time. If for
example. the READY TO NOT·READY condition (11
= 1) and the Every Index Pulse (12 = 1) are both set,
the resultant command would be HEX "DA." The
"OR" function is performed so that either a READY
TO NOT-READY or the next Index Impulse will cause
an interrupt condition.
STATUS REGISTER

command. If the Force Interrupt Command is received when there is a current command under execution, the Busy status bit is reset, and the rest of the
status bits are unchanged. If the Force Interrupt Command is received when there is not a current command under execution, the Busy Status bit is reset
and the rest of the status bits are updated or cleared.
In this case, Status reflects the Type I commands.

Upon receipt of any command, except the Force Interrupt command, the Busy Status bit is set and the rest
of the status bits are updated or cleared for the new

The user has the option of reading the Status Register
through program control or using the DRO line with
DMA or interrupt methods. When the Data Register

TYPE III COMMAND

Read Track/Address

1-108

Floppy Disk Controller Devices

Operation
Write to
Command Reg.
Write to
Command Reg.

READ ADDRESS
SEQUENCE

Write Any
Register

Next Operation

Delay Req'd.
FM
MFM

Read Busy Bit
(Status Bit 0)

121-'s

61-'s

Read Status
Bits 1·7

281-'s

141-'s

0

0

Read From Ditt.
Register

IBM 3740 FORMAT - 128 BYTES/SECTOR

Shown below is the IBM single density·format with
128 bytes/sector. In order to format a diskette, the
user must issue the Write Track Command, and load
the Data Register with the following values. For every
byte to be written, there is one Data Request.
HEX VALUE OF
BYTE WRITTEN

NUMBER
OF BYTES

40

6
1
126
~

1
1
1
1

TYPE 111 COMMAND

1
1
11

Read Track/Address

6
1

is read the ORa bit in the Status Register and the
ORa line are automatically reset. A write to the Data
register also causes both ORa's to reset.
The busy bit in the status may be monitored with a
user program to determine when a command is com·
plete, in lieu of using the INTRa line. When using the
INTRa, a busy status check is not recommended
because a read of the status register to determine
the condition of busy will reset the INTRa line.
The format of the Status Register is shown below:
BITS
7
S7

I

I

6
S6

I

5

I

4

I

3

I

I S5 I S4 I S3 I

2
S2

I

I

1
S1

I

I

0
SO

Status varies according to the type of command
executed as shown in Table 4.
Because of internal sync cycles, certain time delays
must be observed when operating under programmed
I/O. They are: (times double when clock = 1 MHz)

Floppy Disk Controller Devices

128
1
27
2472

FF (or 00)3
00
FC (Index Mark)
FF (or 00)
00
FE (10 Address Mark)
Track Number
Side Number (00 or 01)
Sector Number (1 thru 1A)
00 (Sector Length)
F7 (2 CRC's written)
FF (or 00)
00
FB (Data Address Mark)
Data (I BM uses E5)
F7 (2 CRC's written)
FF (or 00)
FF (or 00)

1. Write bracketed field 26 times.
2. Continue writing until 279X interrupts out.
Approx. 247 bytes.
3. A '00' option is allowed.
IBM SYSTEM 34 FORMAT
256 BYTES/SECTOR

Shown below is the IBM dual·density format with 256
bytes/sector. In order to format a diskette the user
must issue the Write Track Command and load the
Data Register with the following values. For every byte
to be written, there is one Data Request.

1-109

1. NON·IBM FORMATS

:ec

NUMBER
OF BYTES

.....

80
12
3
1
*50

I\)

.

CO

><

o

I\)

'l2
3
1
1
1
1
1
1
22
12
3
1
256
1
54
598**

HEX VALUE OF
BYTE WRITTEN

Variations in the IBM formats are possible to a limited
extent if the following requirements are met:
1. Sector size must be 128, 256, 512, of 1024 bytes.

4E
00
F6 (Writes C2)
FC (Index Mark)
4E
00
F5 (Writes A 1)
FE (ID Address Mark)
Track Number (0 thru 4C)
Side Number (0 or 1)
Sector Number (1 thru 1A)
01 (Sector Length)
F7 (2 CRC's written)
4E
00
F5 (Writes A 1)
FB (Data Address Mark)
DATA
F7 (2 CRC's written)
4E
4E

2. Gap 2 cannot be vaired from the IBM format.
3. 3 bytes of A1 must be used in MFM.
In addition, the Index Address Mark is not required
for operation by the WD279X. Gap 1, 3, and 4 lengths
can be as short as 2 bytes for WD279X operation,
however PLL lock up time, motor speed variation,
write splice area, etc. will add more bytes to each gap
to achieve proper operation. It is recommended that
the IBM format be used for highest system reliability.

Gap I
Gap II
*
*
Gap 111**
Gap IV

*Write bracketed field 26 times.
* *Continue writing until 279X interrupts out.
Approx. 598 bytes.

FM
16 bytes FF
11 bytes FF
6 bytes 00
10 bytes FF
4 bytes 00
16 bytes FF

MFM
32 bytes 4E
22 bytes 4E
12 bytes 00
3 bytes A1
24 bytes 4E
8 bytes 00
3 bytes A1
16 bytes 4E

*Byte counts must be exact.
* * Byte counts are minimum, except exactly 3 bytes
of A 1 must be written.

IN IoI~M O""lV ,0"'''' "''''0 OAT .........
AA(PAECEOEOBYTHA£E8YTfSDF
... 'WIT .. CLOCKH' .... SOT'ONBnw(fti

IBM TRACK FORMAT

1-110

Floppy Disk Controller Devices

ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Voltage to any input with
respect to VSS = + 7 to -0.5V
Operating Temperature: + 15°C to + 50°C (NPO
Capacitor, Pin 26)
+ 5°C to + 60°C (minimum, Neg. 3500 TC
capacitor, Pin 26)
OoC to + 70°C (minimum, Neg. 3500 TC capacitor,
Pin 26 and a thermistor in pump circuit)
Storage temperature

NOTE: Maximum limits indicate where permanent
device damage occurs. Continuous operation at these
limits is not intended and should be limited to those
conditions specified in the DC Operating
characteristics.

= -55°C to + 125°C

OPERATING CHARACTERISTICS (DC)
TA

= See Electrical Characteristics

SYMBOL
IlL
10L
V IH
V IL
V OH
VOL
VOHP
V OLP
Po
Rpu
Icc

MIN_

CHARACTERISTIC
Input Leakage
Output Leakage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output High PUMP
Output Low PUMP
Power Dissipation
Internal Pull-Up*
Supply Current

TYP.

MAX.

UNITS

10
10

JiA
JiA
V
V
V
V
V
V
W
JiA
mA

2.0
0.8
2.4
0.45
2.2

100
70

0.2
.75
1700
150

CONDITIONS
vlN
vOUT

= VCC
= VCC

= -100JiA
= 1.6mA
lOp = -1.0 mA
lOp = + 1.0 mA
All Outputs Open
vlN = OV
10
10

All Outputs Open

*Internal Pull-up resistors on PINS 1, 17, 19, 22, 36, 37 and 40. Also pin 25 on WD2791 and 3.
TIMING CHARACTERISTICS
TA See Electrical Characteristics

Vss

= OV,V cc = +5 ±.25V

READ ENABLE TIMING (See Note 2.)
SYMBOL

CHARACTERISTIC

TSET
T HLO
TRE
TORR
TIRR
T OACC
TOOH

Setup ADDR & CS to RL
Hold ADDR & CS from RE
RE Pulse Width
ORO Reset from RE
INTRa Reset from RE
Data Valid from RE
Data Hold From RE

MIN.

MAX.

UNITS

CONDITIONS
See Note 3

100
500
100

200
3000
200
150

nsec
nsec
nsec
nsec
nsec
nsec
nsec

TYP.

MAX.

UNITS

CONDITIONS

nsec
nsec
nsec
nsec
nsec
nsec
nsec

See Note 3

TYP.

50
10
200

20

CL

= 50 pf

See Fig. 3
C L 50 pf
CL 50 pf

=
=

WRITE ENABLE TIMING (See Note 2)
SYMBOL
TSET
T HLO
TWE
TORR
TIRR
Tos
TOH

CHARACTERISTIC
Setup ADDRS & CS TO WE
Hold ADDR & CS from WE
WE Pulse Width
ORO Reset from WL
INTRa Reset from WE
Data Setup to WE
Data Hold from WE

Floppy Disk Controller Devices

MIN.
50
10
200

100
500
150
50

200
3000

See Fig. 4

1-111

16° OR 32° uS _ _ _ _ _...
'""I1

:ec

I'\)

L -_ _ _ _ _ _ _ _ _ _ _ _...JVOl

......

co

VOH

_TIAA'-~

XI
o

INTRQ

~-:----t_------__,

I'\)

RE

1i5ili

- - - + -....

-----+---4

~OTE

1

CS

NOTE I CS MAY BE PERMANENTLY TIED LOW IF DESIRED
2 WHEN WRITING DATA INTO SECTOR TRACK OR OATA
REGISTER USER CANNOT READ THIS REGISTER UNTI.
AT LEAST •• SEC IN MFM AFTER THE RISING EDGE Of' WE
WHEN WRITING INTO THE ~D REGISTER STATUS
I SERVICE ,WORST CASEI
IS NOT VALlO UNTIL SOME 2I.SEC IN FM o 1. "SEC IN MFM
°FM: 23~uS
LATER. THESE TIMES ARE DOUBLED WHEN CLl( - 1 MH.
'MFM 11 ~us
·TIME DOUBLES WHEN CLOCK • , - '

MAY BE PERMA~ENlL y TIED lOw If DESIRED

'TIME DOUBLES WHEN CLOCK

I SERVICE (WORST CASEI
'FM 275 uS
'MFM

'J~ uS

ORO RISING EDGE. INDICATES THAT THE DATA REGISTER HAS ASSEMBLED

DAQ ~'SlNG EDGE; ONOfCAT!S THAT THE OATA REGISTEA IS EMI'TY
DAQ 'ALLING EDGE: INOfCATEI THAT THE DATA MOIITEA IS LOADeD
INTAG AISING EDGE: INOfCA TE THE END OF A COM ...... D
INTAG 'ALLING EDGE: INOfCATES THAT THE COMMAND "EGISTER
II WAITTEN TO

OArA
ORa FALLING EDGE INDICATES THAT THE OArA REGISTER WAS READ
INTRa RISING EOGE OCCURS AT END OF COMMANO
INTRa FALLING EDGE INDICATES THAT THE STATUS REGISTER WAS REAO

FIGURE 3. READ ENABLE TIMING

FIGURE 4. WRITE ENABLE TIMING

INPUT DATA TIMING
SYMBOL

Tpw
T BC

CHARACTERISTIC

MIN.

TYP.

Raw Read Pulse Width
Raw Read Cycle Time

100
1500

200
2000

WRITE DATA TIMING: (All TIMES DOUBLE WHEN ClK
SYMBOL

CHARACTERISTIC

Twp

Write Data Pulse Width

TWG

Write Gate to Write Data

TWF

Write Gate off from WD

1-112

MAX.

UNITS

CONDITIONS

nsec
nsec

1 MHzXNO WRITE PRECOMPENSATION)

MIN.

TYP.

MAX.

UNITS

CONDITIONS

400
200

500
250
2
1
2
1

600
300

nsec
nsec
J1sec
J-lsec
J-lsec
J-lsec

FM
MFM
FM
MFM
FM
MFM

Floppy Disk Controller Devices

MISCELLANEOUS TIMING:
SYMBOL
TC01
TC02
T STP
TOIR
TMR
TIP

RPW

WPW
WPW
VCO

CHARACTERISTIC

MIN.

TYP.

MAX.

UNITS

Clock Duty (low)
Clock Duty (high)
Step Pulse Output
Dir Setup to Step
Master Reset Pulse Width
Index Pulse Width
Read Window Pulse Width

230
230
2 or 4

250
250

20000
20000

nsec
nsec

Precomp. Adjust
Write Data Pulse Width

Jisec
Jisec
Jisec
Jisec

12
50
10
120
240
100

700
1400
300

nsec
nsec
nsec

200

300

400

nsec

600
6.0

900

1200

nsec
MHz
MHz

Write Data Pulse Width
Free Run Voltage Controlled
Oscillator. Adjustable by
ext. capacitor on Pin 26
Pump Up + 25%

VCO

Pump Down -25%

VCO
Cext

5 % Change Vcc
TA
75°C
Adjustable external capacitor

=

4.0

MHz

5.0

3.8
3.5
6

25

3.0

MHz

4.2

MHz
MHz
pf

60

:E

CONDITIONS

c

N
"'-I

c.o

See Notes 1 & 2
± ClK ERROR
See Notes 1 & 2
Input 0-5V
MFM
FM±15%
MFM
Precomp
100 nsec
MFM
Precomp
300 nsec
MFM
Cext
0
Cext
35 pf

=
=

=

=

= 2.2V
= 35 pf
= 0.2V
= 35 pf
= 35 pf
= 35 pf
= 4.0 MHz

PU
Cext
PO
Cext
Cext
Cext
VCO

nom

RClK

PUIDON

Derived read clock
VCO + 8, 16, 32

VCO

=

-

PU/PD time on
(pulse width)

Floppy Disk Controller Devices

500

KHz

250

KHz

250

KHz

125

KHz
250
500

ns
ns

= 4.0 MHz
=0
=1
=0
=0
=1
=1
=1
=0

DDEN
5/8
DDEN
5/8
DDEN
5/8
DDEN
5/8
MFM
FM

1-113

XI

o

N

iP

:e0

J

5

NOTES:
1. Times double when clock = 1 MHz.
2. Output timing readings are at VOL = O.Bv and V OH
= 2.0v.
3. TSET may be reduced to a nsec if TRE and TWE are
increased the same amount.

VI>

r--T1P--1

I\)

w-

........

><

J

I

I

CD

VIH

I~Tw,-~

I

0

MR

I\)

~

~

I

I

VIH

-.J

1- T. .R---l

~TWp

WD~---~

I-Tc:vc-i

-.:

: . -TWG

WG~:

~ TWF

.......:

----~

WRITE DATA TIMING

I"

TBC---I·~I

re-

U

RCAD-U
DATA

--.J

Tpw

MISCELLANEOUS TIMING
*FROM STEP RATE TABLE
READ DATA TIMING
Table 4. STATUS REGISTER SUMMARY
BIT
S7
S6
S5
S4
S3
S2
S1
SO

ALL TYPE I
COMMANDS
NOT READY
WRITE
PROTECT
HEAD LOADED
SEEK ERROR
CRC ERROR
TRACK
INDEX PULSE
BUSY

a

READ
ADDRESS
NOT READY

READ
SECTOR
NOT READY

RNF
CRC ERROR
LOST DATA
ORO
BUSY

RECORD TYPE
RNF
CRC ERROR
LOST DATA
LOST DATA
ORO
ORO
BUSY
BUSY

a
a

a

READ
TRACK
NOT READY

a
a
a
a

WRITE
SECTOR

WRITE
TRACK

NOT READY
WRITE
PROTECT

NOT READY
WRITE
PROTECT

RNF
CRC ERROR
LOST DATA
ORO
BUSY

LOST DATA
ORO
BUSY

a

a
a
a

STATUS FOR TYPE I COMMANDS
BIT NAME
S7 NOT READY

MEANING
This bit when set indicates the drive is not ready. When reset, it indicates that the
drive is ready. This bit is an inverted copy of the Ready input and logically "ORed"
with MR.

S6 PROTECTED

When set, indicates Write Protect is activated. This bit is an inverted copy of WRPT
input.

S5 HEAD LOADED When set, it indicates the head is loaded and engaged. This bit is a logical "and" of
HLD and HLT signals.
S4 SEEK ERROR
When set, the desired track was not verified. This bit is reset to when updated.
S3 CRC ERROR
CRC encountered in 10 field.

a

S2 TRACK 00

When set, indicates Read/Write head is positioned to Track O. This bit is an inverted
copy of the TROO input.

S1 INDEX

When set, indicates index mark detected from drive. This bit is an inverted copy of
the IP input.

SO BUSY

When set command is in progress. When reset no command is in progress.

1-114

Floppy Disk Controller Devices

STATUS FOR TYPE II AND III COMMANDS
BIT NAME

MEANING

S7 NOT READY

This bit when set indicates the drive is not ready. When reset, it indicates that the
drive is ready. This bit is an inverted copy of the Ready input and "ORed" with MR.
The Type II and III Commands will not execute unless the drive is ready.
S6 WRITE
On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates a
PROTECT
Write Protect. This bit is reset when updated.
S5 RECORD TYPE On Read Record: It indicates the record·type code from data field address mark. 1
Deleted Data Mark. 0
Data Mark. On any Write: Forced to a zero.
S4 RECORD NOT
When set, it indicates that the desired track, sector, or side were not found. This bit is
FOUND (RNF)
reset when updated.
S3 CRC ERROR
If S4 is set, an error is found in one or more ID fields; otherwise it indicates error in data
field. This bit is reset when updated.
S2 LOST DATA
When set, it indicates the computer did not respond to DRO in one byte time. This bit is
reset to zero when updated.
S1 DATA REOUEST This bit is a copy of the ORO output. When set, it indicates the DR is full on a Read
Operation or the DR is empty on a Write operation. This bit is reset to zero when
updated.
SO BUSY
When set, command is under execution. When reset, no command is under execution.

=

=

SUMMARY OF ADJUSTMENT PROCEDURE

WRITE PRECOMPENSATION

1)
2)
3)
4)
5)
6)

Set TEST (Pin 22) to a logic high.
Strobe MR (Pin 19).
Set TEST (Pin 22) to a logic low.
Observe pulse width on WD (Pin 31).
Adjust WPW (Pin 33) for desired pulse width (Precomp Value).
Set TEST (Pin 22) to a logic high.

DATA SEPARATOR

1)
2)
3)
4)
5)
6)
7)

Set TEST (Pin 22) to a logic high.
__
Strobe MR (Pin 19). Insure that 5 /8, and DDEN are set properly.
Set TEST (Pin 22) to a logic low.
Observe Pulse Width on TG43 (Pin 29).
Adjust RPW (Pin 18) for (205ns for 8" DD 450ns for 5 1/4" DD, etc.).
Observe Frequency on DIRC (Pin 16).
Adjust variable capacitor on VCO pin for Data Rate (500 KHz for 8" DD, 250 KHz for 5 1/4" DD,
etc.)._
8) Set TEST (Pin 22) to a logic high.
NOTE: To maintain internal VCO operation, insure that TEST = 1 whenever a master reset pulse is applied.

Floppy Disk Controller Devices

1-115

:E
c
I\)

'".

co

X
o

I\)

1-116

Floppy Disk Controller Devices

WESTERN
COR

PO

DIGITAL

RAT

ION

WD279X-02 Floppy Disk Formatter/Controller
Family Application Notes
INTRODUCTION
In an effort to simplify Floppy Diskette interfacing,
Western Digital has been constantly improving the
lSI Controller/Formatter, the most recent of which is
the WD279X Family of lSI controller devices, incorporating advanced technology to include controller,
Write Compensation and Analog Phase lock loop
in a single 40·pin dual·in·line package. With this
package we can now offer the designer the simplest
ever interfacing option.
The family consists of four members: WD2791,
WD2793, WD2795 and WD2797. WD2791 and WD2793
offer internal clock divide in true and inverted data
bus. The WD2795 and WD2797 offer internal side
select. The family supports both 5 1/4" and 8" Diskette
Drives and both single and double density.
HOST INTERFACING
The lSI Diskette Controller has been developed to
ease the interfacing of Processor to Disk Device. The
Host interfacing with WD279X Family is
accomplished with minimum external devices via an
8·bit bi-directional bus, read/write controls, register
select lines and optional control line for chip select,
5 1/4" or 8" select, enable mini floppy, double den·
sity enable. The basic operation at the controller is
accomplished by selecting the device via (CS) chip
select line, enabling selection of one of the five internal registers (Figure 1).
A1 - AO

READ (RE)

WRITE (WE)

0
0
1
1

Status Regiser
Track Register
Sector Register
Data Register

Command Register
Track Register
Sector Register
Data Register

0
1
0
1

FIGURE 1.
Each time a command is issued to the WD279X, the
busy bit is set and INTRa (Interrupt Request) line is
reset. The user has the option of testing for the busy
bit or polling INTRa to determine if command has
been completed.
The busy bit will be reset whenever the WD279X is
idle and awaiting a new command. The INTRa line
once set, can only be reset by reading of the status
register or issuing a new command.
The Ao, A1 Lines used for register selections can be
configured at the CPU in a variety of ways. These lines
may actually tie to CPU addressed like RAM. They

Floppy Disk Controller Devices

may also be used under Program Control by tying to
a port device such as the 8255, 6250, etc. As a
diagnostic tool when checking out the CPU interface,
the Track and Sector registers should respond like
"RAM" when the WD279X is idle (Busy
INTRa
0).

=

=

Because of internal synchronization cycles, certain
time delays must be introduced when operating under
Programmed I/O. The worst case delays are:
OPERATION

NEXT
OPERATION

DELAY
FM

REQ'D.
MFM

Write to
Command Reg.

Read Busy Bit
(Status Bit 0)

12f.1s

6f.1s

Write to
Command Reg.

Read Status
Bits 1·7

28f.1s

14f.1s

Write Any
Register

Read From Ditt.
Register

0

0

Other CPU interface lines are elK, MR and DDEN.
The ClK line should be 2 MHz (8" drive) or 1 MHz (5
1/4" drive) with 50% duty cycle. Accuracy should be
+ 1 % (crystal source) since all internal timing,
including stepping rates, are based upon this clock,
or a single 2 MHz ClK on WD2791 and WD2793 since
ENMF line will internally divide ClK.
The Master Reset Line should be strobed a minimum
of 50 microseconds upon each power·on condition.
This line clears and initializes all internal registers and
issues a restore command (Hex '03') on the riSing
edge. A quicker stepping rate can be written to the
command register after a MR, in which case the
remaining steps will occur at the faster programmed
rate. The WD179X will issue a maximum of 255 step·
ping pulses in an attempt to expect the TROO line
to go active low. This line should be con·
nected to the drive's TROO sensor.
The DDEN line causes selection of either single den·
sity (DDEN = 1) or double density operation. DDEN
should not be switched during a read or write
operation.
The 5/8 Line selects internal VCO frequency to be
used with 5 1/4" or 8" drives.
FLOPPY DISK INTERFACE
The Floppy Disk Interface can be divided into three
sections: Motor Control, Write Signals and Read
Signals. All of these lines are capable of driving one
TTL load and not compatible for direct connection

1-117

to the drive. Most drives require an open-collector TIL
interface with high current drive capability. This must
be done on all outputs rom the WD279X. Inputs to
the WD279X may be buffered or tied to the Drives'
outputs, providing the appropriate resistor termination networks are used. Undershoot should not
exceed -0.3 volts, while integrity of V1H and VOH
levels should be kept within spec.
MOTOR CONTROL

Motor Control is accomplished by the STEP and DIRC
Lines. The STEP Line issues stepping pulses with
period defined by the rate field in all Type I commands. The DIRC Line defines the direction of steps
(DIRC = 1 STEP IN/DIRC = 0 STEP OUl).
Other Control Lines include the TP or Index Pulse.
This Line is tied to the drives' Index L.E.D. sensor that
informs the WD279X that the stepper motor is at is
furthest position, over Track 00. The READY Line can
be used for a number of functions, such as sensing
"door open," Drive motor on, etc. Most drives provide
a programmable READY Signal selected by option
jumpers on the drive. The WD279X will look.at the
ready Signal prior to executing READIWRITE commands. READY is not inspected during any Type 1
commands. All Type 1 commands will execute
regardless of the Logic Level on this Line.
GENERAL DISK WRITE OPERATION

When writing is to take place on the diskette the Write
Gate rt'/G) output is activated, allowing current to flow
into the ReadlWrite head. As a precaution to
erroneous writing the first data byte must be loaded
into the Data Register in response to a Data Request
from the WD279X before the Write Gate signal can
be activated.
Writing is inhibited when the Write Protect input is
a logic low, in which case any Write command is
immediately terminated, an interrupt is generated and
the Write Protect status bit is set.
RESTORE (SEEK TRACK 0)

Upon receipt of this command the Track 00 (TROO)
input is sampled. If TROO is active low indicating the
Read-Write head is positioned over track 0, the Track
Register is loaded with zeroes and an interrupt is
generated. If TROO is not active low, stepping pulses
(pins 15 to 16) at a rate specified by the r1 ro field are
issued until the TROO input is activated. At this time
the Track Register is loaded with zeroes and an interrupt is generated. If the TROD input does not go active
low after 255 stepping pulses, the WD279X terminates
operations, interrupts, and sets the Seek error status
bit. A verification operation also takes place if the V
flag is set. The h bit allows the head to be loaded
at the start of command. Note that the Restore command is executed when MR goes from an active to
an inactive state.

1-118

SEEK

This command assumes that the Track Register contains the track number of the current position of the
ReadlWrite head and the Data Register contains the
desired track number. The WD279X will update the
Track register and issue stepping pulses in the
appropriate direction until the contents of the Track
register are equal to the contents of the Data Register
(the desired track location). A verification operation
takes place if the V flag is on. The h bit allows the
head to be loaded at the start of the command. An
interrupt is generated at the completion of the command. Note: When using multiple drives, the track
register must be updated for the drive selected before
seeks are issued.
STEP

Upon receipt of this command, the WD279X issues
one stepping pulse to the disk drive. The stepping
motor direction is the same as in the previous step
command. After a delay determined by the r1rO field,
a verification takes place if the V flag is on. If the T
flag is on, the Track Register is updated. The h bit
allows the head to be loaded at the start of the command. An interrupt is generated at the completion of
the command.
STEP-IN

Upon receipt of this command, the WD279X issues
one stepping pulse in the direction away from track
o. If the T flag is on, the Track Register is decremented
by one. After a delay determined by the r1 ro field, a
verification takes place if the V flag is on. The h bit
allows the head to be loaded at the start of the command. An interrupt is generated at the completion of
the command.
EXCEPTIONS

On the WD2795/7 devices, the SSO output is not
affected during Type I commands, and an internal
side compare does not take place when the (V) Verify
Flag is on.
For write operations, the WD279X provides Write Gate
(Pin 30) and Write Data (Pin 31) outputs. Write data
consists of a series of pulses set to a width approximately three times greater than the precomp adjustment. Write Data provides the unique address marks
in both formats.
READY

Whenever a Read or Write command (Type II or III)
is received the WD279X samples the Ready input. If
this input is logic low the command is not executed
and an interrupt is generated. All Type I commands
are performed regardless of the state of the Ready
input. Also, whenever a Type II or III command is
received, the TG43 Signal output is updated. TG43
may be tied to ENP to enable write precompensation
on tracks 44-76.

Floppy Disk Controller Devices

COMMAND DESCRIPTION

The WD279X will accept eleven commands. Command words should only be loaded in the Command
Register when the Busy status bit is off (Status bit
0). The one exception is the Force Interrupt command.
Whenever a command is being executed, the Busy
status bit is set. When a command is completed, and

interrupt is generated and the Busy status bit is reset.
The Status Register indicates whether the completed
command encountered an error or was fault free. For
ease of discussion, commands are divided into four
types. Commands and types are summarized in Table
1 and Table 2.

TABLE 1. COMMAND SUMMARY

A. Commands for Models: 2791, 2793

B. Commands for Models: 2795, 2797

Type Command

7

6

Bits
5

I Restore
I Seek
I Step
I Step·in
I Step-out
II Read Sector
II Write Sector
III Read Address
III Read Track
III Write Track
IV Force Interrupt

0
0
0
0
0
1
1
1
1
1
1

0
0
0
1
1
0
0
1
1
1
1

0
0
1
0
1
0
1
0
1
1
0

Floppy Disk Controller Devices

4

3

2

0
1
T
T
T
m
m
0

h
h
h
h
h
S
S
0
0
0
13

V
V
V
V
V
E
E
E
E
E
12

0
1
11

1
r1
r1
r1
r1
r1

0
rO
rO
rO
rO
rO

C
C
0
0
0
11

0
aO
0
0
0
10

Bits
3

7

6

5

4

0
0
0
0
0
1
1
1
1
1
1

0
0
0
1
1
0
0
1
1
1
1

0
0

0
1
T
T
T
m
m
0
0
1
1

1

0
1
0
1

0
1
1
0

h
h
h
h
h

L
L
0
0
0
13

2
V
V
V
V
V
E
E
E
E
E
12

1
r1
r1
r1
r1
r1

0
rO
rO
rO
rO
rO

U
U
U
U
U
11

0
aO
0

0
0
10

1-119

TABLE 2. FLAG SUMMARY

=E
c

N
.......
CD

Command
Type

Bit
No(s)

I

0,1

r1 rO
Stepping Motor Rate
See Table 3 for Rate Summary

I

2

I

3

I

4

"

0

= Track Number Verify Flag
h = Head Load Flag
T = Track Update Flag
aO = Data Address Mark

,,& III

1

C

= Side Compare Flag

,,& III

1

U

= Update SSO

11&111

2

E

= 15 MS Delay

"
"

3

S

= Side Compare Flag

3

L

= Sector Length Flag

>.<
o

N

Description

=

V

= O,No verify
= 1,Verify on destination track
= O,Load head at beginning
= 2,Unload head at beginning
= O,No update
= 1,Update track register
= O,FB(DAM)
= 1,F8(deleted DAM)
C = O,Disable side compare
C = 1,Enable side compare
U = O,Update SSO to 0
U = 1,Update SSO to 1
E = O,No 15 MS delay
E = 1,15 MS delay (30 MS for 1 MHz)
S = O,Compare for side 0
S = 1,Compare for side 1

V
V
h
h
T
T
aO
aO

LSB's Sector Length in ID Field
01
11
00
10
256
512
=0
128
256
L =1
m = O,Single record
m = 1,Multiple records
L

"

4

IV

0-3

m

= Multiple Record Flag

1024

128

512

1024

= Interrupt Condition Flags
= 1 Not Ready To Ready Transition
= 1 Ready To Not Ready Transition
= 1 Index Pulse
= 1 Immediate Interrupt, Requires A Reset*
= 0 Terminate With No Interrupt (INTRQ)

'x
'0
'1
'2
'3
'3-'0

*NOTE: See Type IV Command Description for further information.

1-120

Floppy Disk Controller Devices

WESTERN
COR

0

P

DIGITAL

RAT

o

N

WD1691 Floppy Support Logic (F.S.L)
FEATURES

GENERAL DESCRIPTION

•
•
•
•
•
•
•
•
•

The WD1691 F.S.L. has been designed to minimize
the external logic required to interface the 179X
Family of Floppy Disk Controllers to a drive. With the
use of an external VCO, the WD1691 will generate the
RCLK signal for the WD179X, while providing an
adjustment pulse (PUMP) to control the VCO
frequency. VFOE/WF de·multiplexing is also
accomplished and Write Precompensation signals
have been included to interface directly with the
WD2143 Clock Generator.

DIRECT INTERFACE TO THE FD179X
ELIMINATES EXTERNAL FDC LOGIC
DATA SEPARATION / RCLK GENERATION
WRITE PRECOMPENSATION SIGNALS
VFOE/WF DEMULTIPLEXING
PROGRAMMABLE DENSITY
8" OR 5.25" DRIVE COMPATIBLE
ALL INPUTS AND OUTPUTS TTL COMPATIBLE
SINGLE + 5V SUPPLY

The WD1691 is implemented in N·MOS silicon gate
technology and is available in a plastic or ceramic
20 pin dual·in·line package.

RCLK

veo
PU

WDIN

20

VCC

l2

2

19

l4

l3

3

18

LATE

11

4

17

EARLY

STB

5

16

VCO

WDOUT

6

15

DDEN

WG

7

14

PO

VFOE/WF

8

13

PU

9

12

RCLK

10

11

ROD

PO

ADO

VSS

T043

WD1691

li
l2

VFOE
fWF

~

li
WQ

EARLY

WDIN

LATE
WOOUl

STB

Figure 1. WD1691 PIN DESIGNATION

Floppy Disk Support Devices

Figure 2. WD1691 SLOCK DIAGRAM

2-1

NAME

PIN

FUNCTION

SYMBOL

1

WRITE DATA
INPUT

WDIN

Ties directly to the FD179X WD pin.

2,3,4,19

PHASE
2,3,1,4

020301 04

4 Phase inputs to generate a desired Write Precompensation delay. These signals tie directly to the WD2143
Clock Generator.

5

STROBE

STB

Strobe output from the 1691. Strobe will latch at a high
level on the leading edge of WDIN and reset to a low
level on the leading edge of 04.

6

WRITE DATA
OUTPUT

WDOUT

Serial, pre-compensated Write data stream to be sent
to the disk drive's WD line.

7

WRITE GATE

WG

Ties directly to the FD179X pin.

8

VFO ENABLE/ VFOE/WF
WRITE FAULT

Ties directly to the FD179X VFOE/WF pin.

9

TRACK 32

TG43

Ties directly to the FD179X TG43 pin, If Write
Precompensation is required on TRACKS 44-76.

10

Vss

Vss

Ground

11

READ DATA

RDD

Composite clock and data stream input from the drive.

12

READ CLOCK

RCLK

RCLK signal generated by the WD1691, to be tied to
the FD179X RCLK pin.

13

PUMP UP

PU

Tri-state output that will be forced high when the
WD1691 requires an increase in VCO frequency.

14

PUMP DOWN

PD

Tri-state output that will be forced low when the
WD1691 required a decrease in VCO frequency.

15

Double Density
Enable

DDEN

Double Density Select input. When Inactive (High), the
VCO frequency is internally divided by two.

16

Voltage
Controlled
Oscillator

VCO

A nominal 4.0 MHz (8" drive) or 2.0 MHz (5.25" drive)
master clock input.

17,18

EARLY
LATE

EARLY
LATE

EARLY and LATE signals from the FD179X, used to
determine Write Precompensation.

Vcc

Vcc

20

+

5V ± 10% power supply

Table 1. PIN DEFINITIONS

2-2

Floppy Disk Support Devices

RCLK

---ms:
::
I

ROD

L

--~

-PU---Pl5---

I

:

I

I

I

:: :
U
I

The signals, DDEN, TG43, and RDD have internal
pull-up resistors and may be left open if a logic 1 is
desired on any of these lines.

I

HI·Z

I

I

I

I
I

I
I

I

I

I

I

I

----:-!-IU :
:

:

I

I

:

I

I

HI·Z

I

HI·Z

:

iLl
!
I

VFOE/WF

ROD

PU+PO

1
0
0
0

X
1
0
0

X
X
1
0

HI-Z
HI-Z
HI-Z
Enable

Figure 4 DATA RECOVERY LOGIC

HI·Z

!

Figure 3 PUMP SIGNAL TIMING DIAGRAM
DEVICE DESCRIPTION

The WD1691 is divided into two sections:
1. Data Recovery Circuit
2. Write Precompensation Circuit
The Data Separator or Recovery Circuit has four
inputs: DDEN, VCO, RDD, and VFOE/WF;
and
three outputs: PU, PD, and RCLK. The VFOE/WF
input is used in conjunction with the Write Gate signal
to enable the Data recovery circuit. When Write Gate
is high, a write operation is taking place, and the data
recovery circuits are disabled, regardless of the state
on any other inputs.
The Write Precompensation circuit has been designed
to be used with the WD2143-03 clock generator. When
the WD1691 is operated in a "single density only"
mode, write precompensation as well as the
WD2143-03 is not needed. In this case, 01,02,03,04,
and STB should be tied together, DDEN left open,
and TG43, WDIN, Early, and Late tied to ground.
In the double-density mode (DDEN = 0), the signals
Early and Late are used to select a phase input
(01 - 04) on the leading edge of WDIN. The STB line is
latched high when this occurs, causing the
WD2143-03 to start its pulse generation. 02 is used
as the write data pulse on nominal (Early Late 0)
01 is used for ec!!:!y, and 03 is used for late. The
leading edge of 04 resets the STB line in anticipation
of the next write data pulse. When TG43 = 0 or
DDEN = 1, Precompensation is disabled and any transitions on the WDIN line will appear on the WDout
line. If write precompensation is desired on all tracks,
leave TG43 open (an internal pull-up will force a Logic
1) while DDEN = O.

=

Floppy Disk Support Devices

WG
HI·Z

=

When VFOE/WF and WRITE GATE are low. the
data recovery circuit is enabled. When the RDD
line goes Active Low, the PU or PD signals will become active. See Figure 4. If the RDD line has
made its transition in the beginning of the RCLK window, PU will go from a HI-Z state to a Logic 1,
requesting an increase in VCO frequency. If the
RDD line has made its transition at the end of the
RCLK window, PU will remain in a HI-Z state while PD
will go to a logic zero, requesting a decrease in VCO
frequency. When the leading edge of RDD occurs
in the center of the RCLK window, both PU and PD
will remain tri-stated, indicating that no adjustment
of the VCO frequency is needed. See Figure 3. The
RCLK signa~divide-by-16 (DDEN = 1)
or
a
divide-by-8 (DDEN = 0) of the VCO frequency.
The minimum Voh level on PU is specified at 2.4V,
sourcing 200ua. During PUMP UP time, this output
will 9QJrom a tri-state to .4V minimum. By typing PU
and PD together, a PUMP signal is created that will
be forced low for a decrease in VCO frequency and
forced high for an increase in VCO frequency. To
speed up rise times and stabilize the output voltage,
a resistor divider can be used to set the tri-state level
to approximately 1.4V. This yields a worst case swing
of + 1V; acceptable for most VCO chips with a linear
voltage-to-frequency characteristic.
Both PU and PO signals are affected by the width
of the RAW READ (RDD) pulse. The wider the RAW
READ pulse, the longer the PU or PO signal (depending upon the phase relationship to RCLK) will
remain active. If the RAW READ pulse exceeds 250ns,
(VCO
4 MHz, DDEN
0), or 500 n~CO
2
MHz, DDEN = 1), then both a PU and PD will occur in the same window. This is undesirable and
reduces the accuracy of the external integrator or lowpass filter to convert the PUMP signals into a slow
moving D.C. correction voltage.

=

=

=

Eventually, the PUMP signals will have corrected the
VCO input to exactly the same frequency multiple as
the RAW READ Signal. The leading edge of the RAW
READ pulse will then occur in the exact center of the
RCLK window, an ideal condition for the FD179X
internal recovery circuits.

2-3

Storage Temperature
Ceramic-65°C (-85°F) to + 150°C (302°F)
Plastic-55°C (-67°F) to + 125°C (257°F)

SPECIFICATIONS

:ec
.....
en
co
.....

ABSOLUTE MAXIMUM RATINGS

Ambient Temperature
under Bias ....... -25°C (-13°F) to 70°C (158°F)
Voltage on any pin with respect
to Ground (Vss) ................. -0.2 to + 7V
Power Dissipation ......................... 1W

NOTE: Maximum limits indicate where permanent
device damage occurs. Continuous operation at these
limits is not intended and should be limited to those
conditions specified in the DC Electrical
Characteristics.

DC ELECTRICAL CHARACTERISTICS

TA

= OOC (32°F) to 70°C (158°F); Vcc = 5.0V

+ 10%;Vss

SYMBOL

PARAMETER

MIN

VIL
VIH
VOL
VOH
Vcc
Icc

Input Low Voltage
Input High Voltage
Output Low Voltage
High Level Output Voltage
Supply Voltage
Supply Current

-0.2
2.0

= OV

TYP

MAX

UNIT

+0.8

V
V
V
V
V
MA

0.45
2.4
4.5

5.0
40

5.5
100

CONDITIONS

10L
IOH

= 3.2 MA
= -200iJ a

A" outputs open

NOTE: For AC and functional testing purposes, a Logic '0' is measured at 0.8V, and a Logic '1' at 2.0V.
AC ELECTRICAL CHARACTERISTICS

TA

= OOC (32°F) to 70°C (158°F);Vcc = 5V

SYMBOL

PARAMETER

FIN

VCO Input Frequency

Rpw
Wei
Pon
Wpi
Inr

RDD Pulse Width
EARLY (LATE) to WDIN
PUMP UP/DN Time
WDIN to WDOUT
Internal Pull-up Resistor

+ 10%; Vss

= OV

MIN.

TYP.

MAX.

UNITS

.5
.5
100
100
0

4
2
200

6
6

MHz
MHz
ns.
ns.
ns.
ns.

4.0

6.5

250
80
10 K

TEST CONDITIONS

DDEN
DDEN

=0
=1

DDEN

=1

I

FIN

Vee

PINS
1 - - - - + - - - - - + - - - - 8 , 9, 11, 15
only

~

VCO

u-

u

ROD

I

---. I

RCu< _ _~

I
I 4-

Rpw

'-----.. . .1

........- - - Voo + 16---!...
~

Figure 5. INTERNAL PULL-UP RESISTOR

2-4

Figure 6. ROD AND RCLK PULSE DIAGRAMS

Floppy Disk Support Devices

WDIN

Wei

.--ll

~I

1-

n

----.

n
I

EARLY

..-

n

Wpw

n

LATE

@1

iD2

00
~

STS

WDOUT
NOM

EARLY

LATE

NOM

TG43 = "1"
DDEN = "0"

Figure 7. WRITE DATA TIMING (MFM)

~

WDIN

WDOUT

4--

Wpw

~nL--_---In~
I

1

II
II

~II_

____~:n

:n~

II

__

__________
Wpi

TG43 = "0"
DDEN = "1"

Figure 8. WRITE DATA TIMING (FM)

Floppy Disk Support Devices

2-5

=E

C
.....

RAW
DATA

CD

1771-01

.....

CO

25
XTDS
1691
RDD

-

11
74LS08

RCLK

12

27

26

FDDATA

FDCLOCK

DDEN 15
N.C.
EARLY LATE:vFOE
17

Figure 9. WD1691 to FD1771-o1 INTERFACE
TYPICAL APPLICATIONS

Figure 9 illustrates the WD1691 to FD1771-01 floppy
disk controller. The RCLK signal is used to gate the
RAW data pulses which are inverted by the 74LS04
inverter. Since RLCK will be high during data and low
during clock a 74LS08 is used to switch the proper
clock or data pulse to the FD1771_
Shown in Figure 10 is a Phase-Lock Loop data
separator and the support logic for a single and
double-density 8" drive. The raw data (both clock and
data bits) are fed to the WD1691 and FD179X. The
WD1691 outputs its PU or PD signal, which is
integrated by the .33uf capacitor and 330hm resistor
to form a control voltage for the 74S124 VCO device_
The 4.0 MHz nominal output of the VCO then feeds
back to the WD1691 completing the loop. The
WD2143-03 is also used, providing write precompensation when in double-density, from tracks 44-77. The
DDEN line can either be controlled by a toggle switch
or a logic level from the host system.
ALIGNMENT

To adjust write precompensation, issue a command
to the FD179X so that write data pulses are present.
This can be done with a 'WRITE TRACK' command
and the iP line open, or a continuous 'WRITE
SECTOR' operation. With a scope on pin 4 of the
WD1691, adjust the precomp pot for the desired value.
This will range from 100 to 300 ns typically.
The pulse width set on pin 4 (01) will be the desired
precomp delay from nominal.
Th~ ~arator must be adjusted with the RDD
or VFOEjWF line at Logic 1. Adjust the bias voltage

2-6

potentiometer for 1.4V on pin 2 of the 74S124. Then
adjust the range control to yield 4.0 MHz on pin 7 of
the 74S124.
SUBSTITUTING VCO'S

There are other VCO circuits available that may be
substituted for the 74S124. The specifications
required are:
1) The VCO must free run at 4.0 MHz with a 1.4V control signal. The WD1691 will force this voltage 1
Volt in either direction (Le., .4V = decrease frequencY,2.4V = increase frequency). If a + 15%
capture range is desired, then a 1 Volt change on
the VCO input should change the frequency by
15%. Capture range should be limited to about
+ 25%, to prevent the VCO from breaking into
oscillation and/or losing lock because of noise
spikes (causing abnormally quick adjustments of
the VCO frequency). Jitter in the VCO output frequency may further be reduced by increasing the
integration capaCitor/resistor, but this will also
decrease the final capture range and lock-up time.
2) The sink output current of the WD1691 is 3.2ma
minimum. The source output current is -200ua.
Therefore, source current is the limiting factor.
Insure that the input circuitry of the VCO does not
require source current in excess of -200ua.
Another alternative is to use a voltage follower/level
shifter circuit to match the input requirements of the
VCO chosen. A more complex filter can be used to
convert the PUMP UP/PUMP DOWN pulses to the
varying DC voltage signal required by the VCO,
achieving an optimum condition between lock-up time
and high frequency rejection.

Floppy Disk Support Devices

!!
Q

:g
-.:::

~

~ 200 NS :!: 25

-

NOTE 4

;;.;-

LJ

C/)

RAW DATA
FROM DRIVE

-§
"0

~

271 RAW READ
+5

Q

I
.l>
. 'f

~

0

CD

s.

(')

CD

C/)

I

"c

DOUBLE
-LDENSITY

lB·
Q

?

~

~

C/J

Z

C)

14

r-

~

+5

R2

WE,RE,CS

VCC
WDOUT

C1

~VCO

4.0MHZ

C2

11

F2

C
III

r-

m
c
m

47K

z
C/J
=i

lOOK
BIAS VOLTAGE
ADJ

+5V
13

ROD

I

RCLK

WDIN
EARLY

PU

TG43

5 STB

VFOE

0

04 03 02 01
191 31 ? 14 1

"'tI
"'tI

-<
Z
-t
m

6

15

DDEN

12

RCLK
WG

1

WD

17

EARLY

18

LATE

9

I

8

TG43
VFOElWF

10

47K

r-

CPU
INTERFACE

r--

7

WD1691 WG

l~PD

"T1

DDEN

LATE

-<

I~

~TO ~

WPRT

36



m

IINTRQ~AQ....A,)

20 '(

4

1_1

+5V

0

0

FD179X

+5V

....

!!!
c

SINGLE
DENSITY

1) ALL RESISTORS V.W :!: 5%
2) SPECIFICATIONS =
CAPTURE RANGE: :!:20%
LOCK·UP TIME: 251o'5ec
(ALL ONE'S PATTERN, MFM)
3) FOR 5 1/4" __
8_

.6810'1

san

2K

IP

Vee 18 +5

WD2143·03
Vss

16

9

-=-

/I

15

DIRC

STEP

TROO

READY

35
FROM
34

DRIVE

32

PRECOMPADJ
10K

.3310'1
330

82PI
47PI
4) ROD = ONE EIGHTH RCLK WIDTH MAXIMUM
250n5 lor 4MHz
500n5 lor 2MHz

~

.......

~69~aM

2-8

Floppy Disk Support Devices

WESTERN

c

o

R

p

o

R

DIGITAL
A

o

T

N

WD16C92 Floppy Read/Write Circuit Device
FEATURES

DESCRIPTION

•
•
•
•
•
•
•
•

The WD16C92 is a 40-pin CMOS custom LSI device
with full TIL level compatibility on input and output.
It is intended to replace a number of discrete components needed with the NEC765A Floppy Disk Controller. The WD16C92 handles four primary functions:
• PLL Logic
• Clock Generation
• Write Precompensation
• Interrupt/DMA timing PC/PC AT Bus
This floppy support device augments the 765A controller while it reduces overall cost.

Compatible with NEC 765A Floppy Disk Controller
CMOS
TIL Compatible
Single + 5V Supply
Phase Detector and Pulse shaping for Read Data
Write Data Precompensation
Floppy Controller Read/Write Clock Generation
IBM PC/PC AT Bus Timing Compatible
Vee

L
FOATA
VCOEN
OSC

2

XTl

2

SOB
DRV
lDFCR
MR

2

FFDDATA

FRO DET
PHASE DET
VCO SELECT
PULSE SHAPE

VCOEN
UP
ON

CLOCK/REF GEN
DATA RATE SELECT

24MHZ

1 OF 4 DATA RATE
OPT 2 SPEED DRIVE
XTAlOSC
FOC ClKS

WDA
WE
PSO

FOClK

PLL LOGIC

FREP
FWClK
WROATA

WRITE PRECOMP LOGIC

FINT

DACK

Iv55
40 PIN DIP/44 PIN PLCC

Floppy Disk Support Devices

Vee
ORO
IDACK
FOMAEN
FINT
FIRO
FORO

FORO
SOB1
SOBO
lOFCR
OSC1
OSC2

FORO

VCOEN1

FIRO

VCOEN2
FREP
FFOOATA

INT/DMA

PC BUS TIMING

FWCLK
ORV

ONOO

~

FOCLK

PS1

ORO
FDMAEN

2
4
4

FORO

VCOEN
PSO
PS1

30

ON01
UP01
ON02

28

UP02

26

ON03
UP03
XTL

WOA
WE
WROATA
GNO

1

MR

2-9

SIGNAL DESCRIPTION
PIN

MNEMONIC

DESCRIPTION

1

FWCLK

2

DRV

WRITE CLOCK - TTL output, clock for write data.
DRIVE TYPE - TTL input with internal pullup resistor. Low level indicates special drive.

3

FDRO

SPEED SELECT - TTL output, latched image SDBO. (effective only on dual speed drives.)

4

SDB1

DATA BUS BIT 1 - TTL input, of data bus bit 1.

5

SDBO

DATA BUS BIT 0 - TTL input, of data bus bit O.

6

LDFCR

LOAD FLOPPY CONTROL REGISTER - TTL input causes SDBO and SDB1 to be latched
internally.

7

OSC1

OSCILLATOR 1 - TTL input, for 500 Kbs, 250 Kbs and 125 Kbs data rates (nominally
2.0 MHz)

8

OSC2

OSCILLATOR 2 - TTL input for 300 Kbs data rate (nominally 2.4 MHz)

9

FDCLK

READ DATA CLOCK - TTL output, provides window for floppy read data pulse.

10

VCOEN1

VCO ENABLE 1 - TTL output, enables VCO for 300 Kbs data rate.

11

VCOEN2

VCO ENABLE 2 - TTL output, enables VCO for 500, 250 and 125 Kbs data rates.

12

FREP

CLOCK OUTPUT - TTL output, provides clock signal for the JAPD765A.

13

FFDDATA

READ DATA - TTL output, floppy read data pulses.

14

VCOEN

VCO ENABLE - TTL input, from the JAPD765A when high enables reading from the floppy
disk.

15

PSO

PRECOMP BIT 0 - TTL input, decodes for precompensation.of write data.

16

PS1

PRECOMP BIT 1 - TTL input, decodes for precompensation of write data.

17

WDA

WRITE DATA - TTL input, write floppy data from the JAPD765A.

18

WE

WRITE ENABLE - TTL input, from the JAPD765A to enable writing data on the floppy disk.

19

WRDATA

WRITE DATA - TTL output, precompensated data from the WD16C92 to be written on
the floppy drive.

20

GND

GROUND

21

MR

MASTER RESET - TTL input, clears all internal conditions to be reset. WD16C92 will
default to the 500 Kbs data rate following a MR.

22

FDATA

READ DATA - TTL input, raw read data from the floppy drive.

23

24MCLK

24 MHz CLOCK TEST POINT - TTL output, for test monitoring only; NOT to be used
to drive any external circuitry.

24

XTL

CRYSTAL RETURN - TTL output, return for 24 MHz crystal when used; otherwise not
connected.

25

XTL

CRYSTAL INPUT - TTL input connection for 24 MHz crystal. Can optionally be used for
24 MHz TTL level square wave clock input.

26

UP03

UP PUMP 3 - Open drain output, provides up pump for 125 Kbs data rate.

27

DN03

DOWN PUMP 3 - Open drain output, provides down pump for 125 Kbs data rate.

28

UP02

UP PUMP 2 - Open drain output, provides up pump for 250 Kbs data rate.

29

DN02

30

UP01

UP PUMP 1 - Open drain output, provides up pump for 300 Kbs data rate.

31

DN01

DOWN PUMP 1 - Open drain output, provides down pump for 300 Kbs data rate.

32

UPOO

UP PUMP 0 - Open drain output, provides up pump for 500 Kbs data rate.

33

2-10

DNOO

DOWN PUMP 2 - Open drain output, provides down pump for 250 Kbs data rate.

DOWN PUMP 0 - Open drain output, provides down pump for 500 Kbs data rate.

Floppy Disk Support Devices

SIGNAL DESCRIPTION (cont.)
PIN

MNEMONIC

34

FDRQ

:ec

DESCRIPTION
DELAYED DATA REQUEST - TTL TRI-STATE output, is the DRQ delayed by 2 j.As and
enabled by FDMAEN.

35

FIRQ

INTERRUPT REQUEST - TTL TRI-STATE output, generates an interrupt request on the
PC/AT compatible bus and is gated by FDMAEN.

36

FINT

FLOPPY INTERRUPT - TTL input from j.APD765A to generate bus interrupt request.

37

FDMAEN

FLOPPY DMA ENABLE - TTL input to gate FIRQ and FDRQ onto the PC/AT compatible
bus.

-DACK

DATA ACKNOWLEDGE - TTL input, data acknowledge signal from the PC/AT
compatible bus.

39

DRQ

DATA REQUEST - TTL input, from the j.APD765A to request a data transfer between the
data bus.

40

VCC

+5

38

volt ± 5% power supply input.

Floppy Disk Support Devices

2-11

.....
0')

(')

co

N

2-12

Floppy Disk Support Devices

WESTERN
COR

0

P

DIGITAL
o

RAT

N

WD2143-03 Four Phase Clock Generator
FEATURES,

GENERAL DESCRIPTION

•
•
•
•
•
•
•
•
•
•

The WD2143-03 Four·Phase Clock Generator is a
MOS/LSI device capable of generating four phase
clocks. The ouput pulse widths are controlled by tying
an external resistor to the proper control inputs. All
pulse widths may be set to the same width by tying
the ~PW line through an external resistor. Each pulse
width can also be individually programmed by tying
a resistor through the appropriate ~1PW·~4PW con·
trol inputs.

IMPROVED VERSION OF WD2143-01
TRUE AND INVERTED OUTPUTS
SINGLE 5 VOLT SUPPLY
TTL COMPATABLE
ON CHIP OSCILLATOR
TTL CLOCK INPUT
TTL CLOCK OUTPUT
PROGRAMMABLE PULSE WIDTHS
PROGRAMMABLE PHASE WIDTHS
NO EXTERNAL CAPACITOR

4

cppw

CP3
CP3

CP4PW

CP2
cp2

CP2PW

CP3PW

cp2PW

CP1PW

CPl
cpl

NC

GND

NC

STBIN

PIN DESIGNATION

cp3PW

CP4PW

CPPW

Figure 1. WD2143-03 BLOCK DIAGRAM
DEVICE OPERATION

Each of the phase outputs can be controlled
individually by tying an external resistor from ~1 PW~4PW to a + 5V supply. When it is desired to have
~1 through ~4 outputs the same width, the ~1 PW~4PW inputs should be left open and an external

Floppy Disk Support Devices

resistor tied from the ~PW (Pin 17) input to + 12V.
STROBE IN (pin 11) is driven by a TTL square wave.
Each of the four phase outputs provide both true and
inverted signals, capable of driving 1 TTL load each.

2-13

=E

c
N

....
:::.

w
o
I

W

PIN NUMBER

DESCRIPTION

SYMBOL

1,3,5,7

+1-~4

Four phase clock outputs. These outputs are inverted (active low).

2,4,6,8

¢1-4>4

Four Phase clock outputs. These outputs are true (active high).

9

GND

Ground.

10

NC

No connection.

11

STB IN

Input signal to initiate four-phase clock outputs.

12

NC

No connection.

13-16

¢1PW-4>4PW

17
18

¢PW
Vee

External resistor inputs to control the individual pulse widths of each output.
These pins can be left open if ¢PW is used.
External resistor input to control all phase outputs to the same pulse widths.
+ 5V ± 5% power supply input.
Table 1. PIN DESCRIPTIONS

TYPICAL APPLICATIONS

'-,

01

•

7

01

02

2

5

02

03

3

3

03

~

'04

04

VD1691

-

WD2143-03
STBIN

STB
17

0PN

J,

2K

"\
\

,,

l

11

STBIN

7400

WD2143-03

,

,
\

+12~
10K

Figure 3. TTL SQUARE WAVE OPERATION

Figure 2. WRITE PRECOMP OPERATION
WITH F.S.L. WD1691

+5
+12

~

11
13

11

2K

STB IN

WD2143-03 <1>1
10K

17

STBIN

I1J1PW

<1>1

I1J2PW

<1>2

8
<1>1

8
<1>1

<1>2

<1>2

<1>3

<1>3

14

<1>PW

6

<1>2

WD2143-03
<1>4

15

I1J3PW

<1>3

I1J4PW

<1>4

4

<1>3

<1>4
16

2

<1>4

10K

Figure 4. EQUAL PULSE WIDTH OUTPUTS

2-14

Figure 5. INDIVIDUAL PULSE WIDTH OUTPUTS

Floppy Disk Support Devices

WD
TO

l

IS

-Jt;

ST.

~
Ct.)

0•

tpw
;;;I

Ct.)

"'--/

179X

rc

-----------~~----------I
.'.2

"'--/

-<

Q'W 1 - - -_ _

----------------~~------I
~---------------------------------------I~
~
Figure 6. WRITE PRECOMP FOR FLOPPY DISK

M _________________

~

Figure 7. WD2143-03 TIMING DIAGRAM

SPECIFICATIONS
Absolute Maximum Ratings
Operating
Temperature ...... 0oC (32°F) to + 70°C (15S°F)
Voltage on any pin with
-0.5 to + 7V
respect to Ground*
Power Dissipation

1 Watt

Storage Temperature
plastic ........ -55°C (-67°F) to
ceramic ....... -65°C (-S5°F) to

Note: Maximum ratings indicate limits beyond which
permanent damage may occur. Continuous operation
at these limits is not intended and should be limited
to the DC electrical characteristics specified.
·Pin 27 = -D.5V to + 12V. Increasing voltage on Pin
17 will decrease Tpw.

+ 125°C (257°F)
+ 150°C (302°F)

DC ELECTRICAL CHARACTERISTICS

Vcc

=

5V ± 5%, GND

SYMBOL
VOL
VOH
V 1L
V1H
Icc

=

OV, TA

=

PARAMETER
TTL low level output
TTL high level output
STS in low voltage
STS in high voltage
Supply Current

OOC (3~F) to 70°C (15S°F).
MIN

MAX

UNITS

0.4

V
V
V
V
rnA

2.0
O.S
2.4
SO

CONDITIONS
10L
10H

= 1.6 rnA
= -100IJ A

All outputs open

Table 2. DC ELECTRICAL CHARACTERISTICS

Floppy Disk Support Devices

:E
cI\)
.....

2-15

:e

c
N
:::.
w
...&.

SWITCHING CHARACTERISTICS
Vee

=

5V ± 5%, GND

SYMBOL
t po
tpw
t pR
tpF
fs
t owp

I

o

W

= OV, TA = OOC (3~F) to 70°C (158°F)

CHARACTERISTIC

MIN.

STB IN to cf>1
Pulse Width (any output)
Rise Time (any output)
Fall Time (any output)
STROBE PULSE WIDTH
Pulse Width Differential

100

MAX.

UNITS

CONDITIONS

140
300
30
25
1.0
±10

ns
ns
ns
ns
ns
%

CL
30pf
CL
30pf
CL
30pf
combined tpw
400 ns
Referenced to cf> 1, 100-300 ns

=
=
=

=

Table 3. SWITCHING CHARACTERISTICS

Note: Tpw measured at 50% VOH Point; VOL

2-16

= O.BV, VOH = 2.0V.

Floppy Disk Support Devices

WESTERN
COR

PO

DIGITAL

RAT

ION

WD9216·00IWD9216·01
Floppy Disk Data Separator FEATURES
• PERFORMS COMPLETE DATA SEPARATION
FUNCTION FOR FLOPPY DISK DRIVES
• SEPARATES FM OR MFM ENCODED DATA
FROM ANY MAGNETIC MEDIA
• ELIMINATES SEVERAL SSI AND MSI DEVICES
NORMALLY USED FOR DATA SEPARATION
• NO CRITICAL ADJUSTMENTS REQUIRED
• COMPATIBLE WITH WESTERN DIGITAL 179X,
176X AND OTHER FLOPPY DISK CONTROLLERS
• SMALL 8-PIN DUAL-IN-LiNE PACKAGE
• +5 VOLT ONLY POWER SUPPLY
• TTL COMPATIBLE INPUTS AND OUTPUTS

:E

c

c.o

FDDS

N

""'C')"

o•

o

GENERAL DESCRIPTION
The Floppy Disk Data Separator provides a low cost
solution to the problem of converting a single stream
of pulses from a floppy disk drive into separate Clock
and Data Inputs for a Floppy Disk Controller.
The FDDS consists primarily of a clock divider, a longterm timing corrector, a short-term timing corrector,
and reclocking circuitry. Supplied in an 8-pin Dualin-Line package to save board real estate, the FDDS
operates on + 5 volts only and is TTL compatible on
all inputs and outputs.
The WD9216 is available in two versions; the
WD9216-00, which is intended for 51/4" disks and
the WD9216-01 for 5 1 /4" and 8" disks.

VCC
SEPD
CD1

CDO

PIN CONFIGURATION

REFCLK~

CDO---.

- +5V

CLOCK
DIVIDER

-GND

CD1-'

DATA/CLOCK
SEPARATION
LOGIC

DSKD-.

PULSE
REGENERATIO
LOGIC

SEPCLK
SEPD

EDGE
DETECTION
LOGIC

FLOPPY DISK DATA SEPARATOR BLOCK DIAGRAM

Floppy Disk Support Devices

2-17

ELECTRICAL CHARACTERISTICS

:ec
co

N
.....
0')
o•

o

MAXIMUM RATINGS·
Operating Temperature Rnge ...... 0oC to + 70°C
Storage Temperature Range ....... -55°C TO 1250
Positive Voltage on any Pin,
with respect to ground ............... + 8.0V
Negative Voltage on any Pin,
with respect to ground ................. -0.3V

NOTE: When powering this device from laboratory or
system power supplies, it is important that the
Absolute Maximum Ratings not be exceeded or
device failure can result. Some power supplies exhibit
voltage spikes or "glitches" on their outputs when
the AC power is switched on and off. In addition,
voltage transients on the AC power line may appear
on the DC output. If this possibility exists it is suggested that a clamp circuit be used.

·Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these or at any
other condition above those indicated in the operational sections of this specification is not implied.
OPERATING CHARACTERISTICS (fA = OOC to 700 C, Vcc = ± 5%, unless otherwise noted.)
PARAMETER

MIN.

D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low Level VIL
High Level VIL
OUTPUT VOLTAGE LEVELS
Low Level VOL
High Level VOH
INPUT CURRENT
Leakage IlL
INPUT CAPACITANCE
All Inputs
POWER SUPPLY CURRENT
100
A.C. CHARACTERISTICS
Symbol
REFCLK Frequency
fCY
REFCLK Frequency
fCY
REFCLK High Time
tCKH
REFCLK Low Time
tCKL
REFCLK to SEPD "ON" Delay
tSOON
REFCLK to SEPD "OFF" Delay
tSOOFF
t SPCK
REFCLK to SEPCLK Delay
DSKD Active Low Time
tOLL
DSKD Active High Time
tOLK

TYP.

MAX.

UNITS

0.8

V
V

0.4

V
V

10L = 1.6 rnA
10H = -100 A

10

p.A

o<

10

pF

50

rnA

4.3
8.3
2500
2500

MHz
MHz
ns
ns
ns
ns
ns
P.s
P.s

2.0
2.4

0.2
0.2
50
50
100
100
100
0.1
0.2

100
100

COMMENTS

VIN < Voo

WD9216-00
WD9216-01

REFCLK

SEPO,

SEPCLK ------~----:----------

DSKD.

Figure 3. AC CHARACTERISTICS

2-18

Floppy Disk Support Devices

DESCRIPTION OF PIN FUNCTIONS

PIN
NUMBER

PIN NAME

SYMBOL

FUNCTION

1

Disk Data

DSKD

Data input signal direct from disk drive. Contains combined
clock and data waveform.

2

Separated Clock

SEPCLK

Clock signal output from the FDDS derived from floppy disk
drive serial bit stream.

3
4

Referenced Clock REFLCK

Reference clock input.

Ground

GND

Ground.

Clock Divisor

CDO,CD1

CDO and CD1 control the internal clock divider circuit. The
internal clock is a submultiple of the REFCLK according to
the following table:
CD1
CDO
Divisor
0
1
0
1
2
0
1
0
4
1
1
8

7

Separated Data

SEPD

SEPD is the data output of the FDDS.

8

Power Supply

Vcc

+5

5,6

volt power supply.

4 MHz CRYSTAL
OSCILLATOR

REFCLK
FLOPPY
DISK
DRIVE

DISK DATA

I
.,

SEPo

+4

1

COO

COl

SEPCLK

~

REGENERATED DATA

DSKD
WD9216·00,Ol

lMHz

J

DERIVED CLOCK

CLK

RAW READ
WD179X, 176X or Equiv.
FLOPPY DISK
CONTROLLER
RCLK

+ GND
+

GND

Figure 1. TYPICAL SYSTEM CONFIGURATION
(5 1 / 4" Drive, Double Density)
OPERATION
A reference clock (REFCLK) of between 2 and 8 MHz
is divided by the FDDS to provide an internal clock.
The division ratio is selected by inputs CDO and CD1.
The reference clock and division ratio should be
Ichosen per Table 1.
The FDDS detects the leading edges of the disk data
pulses and adjusts the phase of the internal clock
to provide the SEPARATED CLOCK output.

Floppy Disk Support Devices

Separate short and long term timing correctors assure
accurate clock separation.
The internal clock frequency is nominally 16 times
the SEPCLK frequency. Depending on the internal timing correction, the internal clock may be a minimum
of 12 times to a maximum of 22 times the SEPCLK
frequency.
The reference clock (REFCLK) is divided to provide
the internal clock according to pins CDO and CD1.

2-19

Table 1. CLOCK DIVIDER SELECTION TABLE
DRIVE

DENSITY
(DO or SO)

REFCLK
MHz

CD1

COO

REMARKS

8
8
8

00
SO
SO

8
8
4

0
0
0

0
1
0

Select either one

5 1/4
5 1/4

00
00

8
4

0
0

1
0

5 1/4
5 1/4
5 1/4

SO
SO
SO

8
4
2

1
0
0

0
1
0

(8" or 5 1 / 4'')

Select either one
Selecct anyone

INTCLK
SEPCLK ---.J

SEPD---------~~----:--------~~~------------------~LJ~--------------I

I

W

always two Internal clock cycles

Figure 2. REFERENCE CLOCK TIMING

2-20

Floppy Disk Support Devices

WESTERN

DIGITAL

c

A

o

R

p

o

R

T

o

N

=E
o

CD

WD92C32 Floppy Disk Digital Data Separator

I\)

()
(,.)
I\)
I

FEATURES

GENERAL DESCRIPTION

•

The WD92C32 digital data separator has been
designed to address the high performance 5 %" or
8" floppy disk drive market. It is pin function compatible with the WD9216, although it provides superior
performance in terms of available bit jitter window
margins. The WD92C32 is designed to operate at data
rates of 125, 250 and 300, and 500 Kb/s.

•
•
•
•
•
•

HIGH PERFORMANCE DIGITAL DATA
SEPARATOR (Low error rates)
NO ADJUSTMENTS
8 PIN DIP
TTL COMPATIBLE
CMOS
SINGLE 5V SUPPLY
PIN FUNCTION COMPATIBLE WITH THE WD9216

The WD92C32 is a CMOS LSI product with TTL compatible I/O which operates from a single 5 volt supply.
Packaged as an 8 pin DIP, the WD92C32 represents
a significant cost savings when compared to the cost
of the analog components required to achieve equal
performance.
The device contains an internal power-up reset along
with all of the necessary logic to achieve classical
2nd order phase locked loop performance.
Implemented digitally this design does not require any
external adjustments or any additional logic to perform the data separation.

PIN CONFIGURATION

DESCRIPTIONS OF PIN FUNCTIONS
PIN NUMBER

MNEMONIC

FUNCTION

SIGNAL NAME

1

-DSKD

Disk Data

Data input signal from the floppy drive containing both clock
and data information.

2

SEPCLK

Separated Clock

Resultant clock recovered from the disk serial bit stream.
Sometimes called RCLK.

3

REFCLK

Reference Clock

Reference clock input from a crystal oscillator.

4

Vss

Ground

Ground

5
6

COO,
CD1

Clock Divisor

Encoded bits which are used to select 1 of 4 reference clock
division factors.

SEPD

Separated Data

Sometimes called RDATA, this is still the encoded serial
bit stream, but which has been re-synchronized to the phase
of Recovered Clock.

Vee

Power Supply

+ 5V

7

8

--

Floppy Disk Support Devices

power supply

2-21

o
o

2-22

Floppy Disk Support Devices

WESTERN

c

o

R

p

o

R

DIGITAL
A

o

T

N

:E
c
""""
0
""""
0

WD1010-05 Winchester Disk Controller

I

0

CJ1

FEATURES

•

ST506-SA1000 COMPATIBLE

•

MULTIPLE SECTOR READ/WRITE

vcc
RCLK
RG
RO
BORQ
BROY
ORUN
RWC
SC
TKOOO
WF
INOEX
OROY
STEP
OIRIN
WCLK
WG
EARLY
LATE
WO

INTRQ
NC

•

UP TO 5 MBITS/SEC DATA RATE

•

UNLIMITED SECTOR INTERLEAVE

•

AUTOMATIC FORMATTING

WE

•

CRC/ECC CAPABILITY WITH EXTERNAL ECC
GENERATOR/CHECKER

AO

•

PROGRAMMABLE RETRIES

•

VARIABLE SECTOR SIZE

•

SINGLE +5V SUPPLY

MR

RE
Cs
A1
A2

07
06
05
04
03
02
01

DESCRIPTION

00

vss

The WD1010-05 is a MOS/LSI device which performs
the functions of a Winchester Disk Controller/Formatter. It is compatible with the Seagate ST506 and the
Shugart Associates SA1000 drives, as well as all other
5 %" and 8" products utilizing the same type of interface. On the host side, an 8-bit bi-directional bus
accepts all commands, data, and status bytes. The
Western Digital WD1000 series of board level controllers are software compatible with the WD1 01 0-05.

PIN DESIGNATION

Operating from a single 5 volt supply, the WD1010-05
is implemented in NMOS silicon gate technology and
is available in a 40-pin dual-in-line and aSM package.
ARCHITECTURE·

The WD1010-05 Winchester Disk Controller provides
the necessary link between an 8-bit, parallel processor
and a Winchester disk drive. The WD1010-05 may be
programmed to either automatically retry errors, or
to terminate the command. The internal architecture
of the WD1010-05 is shown in Figure 1. Its major functional blocks are:

NC

WG
EARLY
LATE
WD

RG
RCLK
Vee

BCS

Vss

BCR
INTRQ

00

NC
NC

02
03
04

01

NC

PLA Controller

The PLA interprets commands and provides all control functions. It is synchronized with WCLK.

MRWCAAADDDN

R E E S 0 1 2 7 6 5 C

QUAD PIN DESIGNATION
Magnitude Comparator

A 10-bit magnitude comparator is used for calculation of drive step, direction, present and desired
cylinder position.

Winchester Disk Controller Devices

3-1

PIN DESCRIPTION

:E
c
.....
o

PIN
NUMBER

o

1

BCS

BUFFER CHIP SELECT

2

BCR

BUFFER COUNTER
RESET

3

INTRQ

INTERRUPT REQUEST

4
5

NC
MR

NO CONNECTION
MASTER RESET

6

-RE

READ ENABLE

7

WE

WRITE ENABLE

8

CS

CHIP SELECT

9
10
11

AO
A1
A2
07
thru
DO

ADDRESS 0
ADDRESS 1
ADDRESS 2

.....
I

o
en

12
thru
19
20
21

3-2

SIGNAL NAME

MNEMONIC

FUNCTION
Active low output used to enable reading or writing
of the external sector buffer.
Active low output that is strobed by the WD1010-05
prior to read/write operations. This pin is strobed
whenever BCS changes state.
INTRQ is an output asserted upon completion of
a command and de-asserted when the Status
Register is read or a new command is written into
the Command Register. This signal can be programmed to occur with BDRQ and DRQ during
Read Command.
A logic low in this input will initialize all internal
logic.
Tri-state bi-directional line used as an input for
reading the task register and an output when the
WD1010-05 is reading the buffer.
Tri-state bi-directional line used as an input for
writing into the task register and as an output when
the WD1010-15 is writing to the buffer.
AJogic low on this input enables both WE and
RE signals.
These three inputs select the register to receiveltransmit data on 00-07.
8-bit tri-state bi-directional bus used for transfer of
commands, status, and data.

Vss
WD

DATA 7
thru
DATA 0
GROUND
WRITE DATA

22
23

LATE
EARLY

LATE
EARLY

Precompensation outputs used to delay the WD
pulses externally.

24

WG

WRITE GATE

This output is set to a logic high before writing is
to be performed on the disk.

25

WCLK

WRITE CLOCK

26

DIRIN

DIRECTION IN

27

STEP

STEP PULSE

28

DRDY

DRIVE READY

29

INDEX

INDEX PULSE

30

WF

WRITE FAULT

31

TKOOO

TRACK 000

4.34 or 5.0 MHz clock input used to derive all internal write timing.
This output determines the direction the stepping
motor will move the heads. High
in, Low
out.
This output generates a pulse for stepping the drive
motor.
This input must be at a logic high in order for commands to execute.
A rising edge on this input informs the WD1 01 0-05
when the index hole has been encountered.
An error input to the WD1010-05 which indicates
a fault condition at the drive.
An input to the WD1010-05 which indicates positioning over track 000.

Ground.
This output contains the MFM clock and data
pulses to be written on the disk.

=

=

Winchester Disk Controller Devices

PIN DESCRIPTION (Continued)
PIN
NUMBER

:E
MNEMONIC

SIGNAL NAME
SEEK COMPLETE

FUNCTION
A rising edge on this input informs the WD1010-05
when head settling time has expired. In the Format Command, it is used to extend the gap.
This output can be programmed to reduce write
current on a selected starting cylinder.
This input informs the WD1010-05 when a field of
ones or zeroes have been detected.
The rising edge of this input informs the controller
that the Sector Buffer is full or empty.

32

SC

33

RWC

REDUCED WRITE
CURRENT

34

DRUN

DATA RUN

35

BRDY

BUFFER READY

36

BDRQ

BUFFER DATA
REQUEST

3?

RD

READ DATA

38

RG

READ GATE

39

RCLK

READ CLOCK

40

Vcc

+5 VOLT

BORA and ORQ (Bit 3 Status Register) are asserted
when the Buffer is to be read from or written to,
by the Host. BDRQ can be used by a OMA controller or by the Host during Programmed 1/0. DRQ
must be polled by the Host if used during programmed 1/0.
Data input from the Drive. Both MFM clocks and
data pulses are entered on this pin.
This output is set to a logic high when data is
being inspected from the disk.
A nominal square wave clock input derived from
the external data recovery circuits.
+5V

00-07

WD
WCLK
MAGNITUDE
COMPARATOR
RE
WE

i
I
1

.
I

A2-AO

RCLK

INTRa
MR
RD

es

PLA
CONTROLLER

BCR
BRDY
BORa

BUFFER
IFC

DRDY
WF

BCS

Vec
Vss

STEP
DIRIN
EARLY
LATE

TKOOO
INDEX

---.

se

---.

RWC
WG
RG
DRUN

FIGURE 1.
WD1 01 0 BLOCK DIAGRAM

Winchester Disk Controller Devices

3-3

c-"

o
-"
o
o•

(J1

=E
c

""""
o
""""
o
I

o

(J1

CRC Logic

Drive IFC

Generates and checks the cyclic redundancy check
characters appended to the ID and data fields. The
polynomial is X16 + X12 + X5 + 1.

This logic controls and monitors all lines from the
drive, with the exception of read and write data.

MFM Encode/Decode

The drive side of the WD1 01 0-05 controller requires
three sections of external logic. These are buffers/receivers, data separator, and write precompensation. Figure 2 illustrates a drive side interface.
The buffer/receivers condition the control lines to be
driven down the cable to the drive. The control lines
are typically single-ended, resistor terminated TTL
levels. The data lines to and from the drive also
require buffering, but are differential RS-422 levels.
The interface specification to the drive can be found
in the manufacturers' OEM manual. The WD1010-05
supplies TTL compatible signals, and will interface
to most buffer/driver devices.
The data recovery circuits consist of a phase-lock
loop data separator and associated components. The
WD1010-05 interacts with the data separator through
the DRUN and RG signals. The block diagram of the

DRIVE INTERFACE

Encodes and decodes MFM data to be written/read
from the drive. The MFM encoder operates from
WCLK; a clock having a frequency equivalent to the
bit rate. The MFM decode operates from RCLK; a bit
rate clock generated from the external data separator.
RCLK and WCLK need not be synchronized.
AM Detect

The address mark detector checks the incoming
data stream for a unique missing clock pattern
(Data
A1 hex, Clock
OA hex) used in each
ID and data field.

=

Host/Buffer IFC

This logic contains all of the necessary circuitry
to communicate with the 8-bit host processor.

RG
DRUN
RD
RClK

DATA
SEPARATOR

WD1010

HOST (

DATA/CTRl

'J

t\)

V

WD

EARlY

CAfE
RWC

WRITE
PRECOMPENSATION
AND
SYNCHRONIZATION

DISK
DRIVE

STEP
DIRIN
DRDY
WF
TKOOO
INDEX

BUFFERI
RECEIVERS

SC
WG

FIGURE 2. DRIVE INTERFACE BLOCK DIAGRAM

RETRIGGERABlE
ONE·SHOT

DRUN

RD
WD1010
RClK
RG

I-------t

WClK

FIGURE 3. DATA RECOVERY CIRCUIT

3-4

Winchester Disk Controller Devices

=E

....co
....
o

.

o
en

YES

FIGURE 4. PLL CONTROL SEQUENCE FOR 10 FIELD

Winchester Disk Controller Devices

3-5

data separator circuit is shown in Figure 3. Read data
from the drive is presented to the RD input of the
WD1010·05, the reference multiplexor, and a retrig·
gerable one shot. The read gate output will be low
when the WD101()'()5 is not inspecting data. The PLL
at this time should remain locked to the reference
clock.

=E
c
.....

o.....
o
o•

(J1

When any ReadlWrite command is initiated and a
search for address marks begins, the DRUN input is
examined. The DRUN one·shot is set for slightly
greater than one bit time, allowing it to retrigger constantly on a field of ones and zeroes. An internal
counter times out to see that DRUN is high for 2 byte
times. Read gate is set by the WD1010-05, switching
the data separator to lock onto the incoming data
stream. If DRUN falls prior to 7 bytes times, RG is
lowered and the process is repeated. Read gate will
remain active high until a non-zero, non-address mark
byte is detected. It then will lower read gate for 2 byte
times (to allow the PLL to lock back on the reference
clock) and start the DRUN search over again. If an
address mark is detected, read gate will be held high
and the command will continue searching for the proper ID field. This sequence is shown in the flow chart
of Figure 4.
The write precompensation logic is controlled by the
signals RWe, EARLY and LATE. The cylinder in
which the RWe line becomes active is controlled by
a register in the Task File. It can be used to turn on
the precomp circuitry on a predetermined cylinder.
If the write precomp register value is FF, then RWe
will always be low.
The signals EARLY and LATE are used to tell the
precomp how much delay is required on the write
data pulse about to be sent. The amount of delay is
determined externally through a digital~line
or equivalent circuitry. Since the signal EARLY occurs after the fact, write data should be delayed one
interval when both EARLY and LATE are deasserted; two intervals when LATE is asserted; and no
delay when EARLY is asserted. An interval, for
or
example, is 12-15 ns. on the ST506. EARLY
LATE will be active slightly ahead of the write data
pulse; EARLY and LATE will never be asserted at
the same time. The EARLY LATE signals function
independently of the content of the RWe register.
Examples for all three of the above circuits can be
found in the WD1010 Application Note.
HOST INTERFACE

FIGURE 4. (CO NT.)
PPL CONTROL SEQUENCE FOR DATA FIELD

3-6

The primary interlace between the host processor and
the WD1010-05 is through an 8-bit bi-directional bus.
This bus is used to transmit/receive data to both the
WD1010-05 and a sector buffer. The sector buffer is
constructed with either FIFO memory or static RAM
and a counter. Since the WD101().()5 will make the bus
active when accessing the sector buffer, a transceiver
must be used to isolate the host during this time.
Figure 5 shows a typical connection to a sector buffer implemented with RAM memory.

Winchester Disk Controller Devices

buffer is full. (BRDY is a rising edge activated signal).
The BGS is then asserted, disconnecting the host
through the transceivers, and the RE and WE lines
become outputs from the WD1010-05 to allow it
access to the buffer. When the WD1 01 0-05 is done
using the buffer, it disables BGS which again
allows host access to this local bus. The read sector commands operate in a similar manner, except
the buffer is loaded by the W01010-05 instead of the
host.

Whenever the WD1 01 0-05 is not using the sector buffer, the BCS is de-asserted. This allows the host to
access the WD1010's Task File, and to set up
parameters prior to issuing a command. It also allows
the host to access the RAM buffer. A decoder is used
to generate a chip select when Ao- A2 are '000'; an
unused address in the WD1010-05. A binary counter
is enabled whenever RE or WE goes active and incremented on the trailing edge of the chip select. This
allows the host to access sequential bytes within the
RAM. The decoder also generates another chip select
when Ao-A2 '000'; allowing access to the
WD1010-05's internal registers while keeping the RAM
tri-stated.

Another control signal called BORa can be connected
to a OMA controller in the Host, or can be polled by
the Host for programmed 110. For further explanation,
refer to the description of the individual commands
and the A.G. Timing Specifications. In a read command; an interrupt may be specified to occur either
at the end of the command or when BDRa is
activated. The INTRa is cleared either by reading the
status register or by writing a new command in the
command register.

During write sector commands, the processor sets
up data in the Task File and issues the command.
The WD1010 then generates a status to inform the
host it may load the buffer with the data to be written. When the counter reaches its maximum count,
the BRDY signal is made active (by the "carry" out
of the counter), informing the WD1010-05 that the

~

-RE

-

RE

L-L-

-WE

DATA

l-1;~

-

~

DATA BUS (8)

,
I

>CK

~
~

MR

.
:

Al

SEL

3f

DATA _
RE

_

~ •
~:

:~:

TC ax r--- AX
-r-

0
E
C

AO-2

"

:r--:

00-07

I

~

I

II

~ ----;;-. rr--

HOST
PROCESSOR

I

-WE

-BCR

rWD1010

WE---

cs

Q

ry-L

-BCS

-CS
3/
I

1

a

CP
RST

,

AO-2
BROY

0
N_U_-

BORa

.I

FIGURE 5.

HOST INTERFACE

Winchester Disk Controller Devices

3-7

:E
c......

o
......
o
I

o

01

TASK FILE

=E

c
......
o
......

The Task File is a bank of nine registers used to hold
parameter information pertaining to each command.
These registers and their addresses are:

oI
o

READ

WRITE

0 0 0
0 0 1

(Bus Tri-Stated)
Error Flags

0
0
1
1
1
1

Sector Count
Sector Number
Cylinder Low
Cylinder High
SDH
Status Register

(Bus Tri-Stated)
Write Precomp
Cylinder
Sector Count
Sector Number
Cylinder Low
Cylinder High
SDH
Command
Register

A2 A1 Ao

CJ1

1
1
0
0
1
1

0
1
0
1
0
1

NOTE: Registers are not cleared by master reset (MR).
ERROR REGISTER
This read-only register contains specific error status
after the completion of a command. These bits are
defined as follows:

I

7654321
BB

0

ICRC I - I ID I - I AC I TK I DM I

Bit 7 - Bad Block Detect
This bit is set when an ID field has been encountered
that contains a bad block mark. Used for bad sector
mapping.
Bit 6 - CRC Data Field
This bit is set when a CRC error occurs in the data
field. With Retry enabled, ten more attempts are made
to read the sector correctly. If none of these attempts
are successful, the Error Status is set also (bit 0 in
the Status Register). If one of the attempts is successful, this bit remains set to inform the Host that
a marginal condition exists. However, the Error Status
bit is not set. Even if errors exist, the data can be read.
Bit 5 - Reserved
Not used; forced to a zero.
Bit 4 - ID Not Found
This bit is set to indicate that the correct cylinder,
head, sector number or sector size parameter could
not be found, or that a CRC error occurred on the ID
field. This bit is set on the first failure and remains
set even if the error is recovered on a Retry. When
recovery is unsuccessful, the Error Status bit is set
also (bit 0 in the Status Register).
Bit 3 - Reserved
Not used; forced to a zero.
Bit 2 - Aborted Command
This bit is set if a command was issued while the
DRDY is de-asserted or the WF is asserted. The
aborted command bit will also be set if an undefined
command code is written into the command register,
but an implied seek will be executed.

3-8

Bit 1 - Track Zero Error
This bit is set only by the restore command. It
indicates that the TKOOO has not gone active after the
issuance of 1024 stepping pulses .
Bit 0 - Data Address Mark Not Found
This bit is set during a read sector command if the
data address mark is not found after the proper sector ID is read.
WRITE PRECOMP CYLINDER
This register is used to define the cylinder number
where the RWC is to be asserted:

765
432
CYLINDER NUMBER .;- 4

0

The value OO-FF loaded into this register is internally
multiplied by 4 to specify the actual cylinder where
RWC is asserted. Thus, a value of 01 hex will cause
RWC to activate on cylinder 4; 02 hex on cylinder 8,
and so on. Switching points are then 0, 4, 8, ... The
RWC will be asserted when the present cylinder is
equal to 4 times or more than the value in this register.
For example, the ST506 requires precomp on cylinder
128 (80 hex) and above. Therefore, the write precomp
cylinder register should be loaded with 32 (20 hex).
A value of FF hex will always cause RWC to be low,
no matter what the cylinder number values are.
SECTOR COUNT
This register holds the number of sectors that are to
be transferred to the buffer.

7

6

5

4

3

2

o

# OF SECTORS
This register is used during a multiple sector R/W
command. The written value is decremented after
each sector is transferred to the sector buffer. A zero
represents a 256 sector transfer, a 1 = one sector
transfer, etc. This register is a "don't care" when
single sector commands are specified.
SECTOR NUMBER
This register holds the sector number of a desired
sector:

7

6

5

432

o

SECTOR NUMBER
During a multiple sector command, this register
specifies the first sector in the transfer. It is internally
incremented after each transfer of data to the sector buffer. The sector number register may contain
any value from 0 to 255.
CYLINDER NUMBER LOW
This register holds the least significant eight bits of
the desired cylinder number.

Winchester Disk Controller Devices

6

7

5

4

3

2

o

1

LS BYTE OF CYLINDER NUMBER
It is used with the cylinder number high register to
specify a range of 0 to 1023.
CYLINDER NUMBER HIGH

This register defines the two most significant bits of
the cylinder number desired:
765

I

X

I

X

I

X

4

3

2

X

X

X

o
(8)

(9)

Internal to the WD1010-05 is another pair of registers
that hold the actual position number where the R/W
heads are located. The cylinder number high and Ikow
registers can be considered the cylinder destination
for seeks and other commands. After these com·
mands are executed, the internal cylinder position
registers' contents are equal to the cylinder high/low
registers. If a drive number change is detected on a
new command, the WD1010-05 automatically reads
an 10 field to update its internal cylinder position
registers. This affects all commands except a Restore.

SOH BYTE

This register contains the desired sector size, drive number, and head number parameters. The format is:

76543210

6
0
0
1
1

5

0
1
0
1

SECTOR SIZE
256
512
1024
128

4
0

0
1
1

3

0
1
0
1

-- ----

DRIVE#
DSEL1
DSEL2
DSEL3
DSEL4

2
0
0

0
0
1
1
1
1

Both head number and sector size is compared
against the disks' 10 field. Head select and drive
select lines are not available as outputs from the
WD1010-05, and must be generated externally. Figure
6 shows the logic to implement these select lines.
Bit 7, the extension bit, is used to extend the data
field by seven bytes when using ECC codes. CRC is
not appended to the data field when EXT = 1; the
data field becomes "sector size + 7" bytes long. CRC
is checked on the 10 field regardless of the state of
the extention bit. Note that the sector size bits are
written to the 10 during a format command. The

1

0
0
1
1
0
0
1
1

HEAD #
HSELO
HSEL1
HSEL2
HSEL3
HSEL4
HSEL5
HSEL6
HSEL7

0
0
1
0
1
0
1
0
1

SOH byte written into the 10 field is different than the
SOH register contents. The recorded SOH byte does
not have the drive number written but does have bad
block mark written. The format is:

7

SIZE

o

o

6 5

4

3

HEAD#

2

0

DO

~----------~~--------------~01

~--------~~~--------------~02
BUS

TRANSCEIVER

~--------~~~---------------I 03

04

~-------+~~~--------------~05
~-------+~H-~--------------~06
~-------+~H-~--------------~07

WE)----___.

>-------+__.

AO
Al >---DoD---~
A2

DO L 01
01 A 02
02 T 03
C 04
H 05

L...-_ _~03
L...-_ _-I04

HSEL 0
HSEL 1
HSEL 2

CS ) - - - - - - - . - /

WD1D1D

o

DSEL 1

o

DSEL 4

~

>--0<>------.:...-

~

g~~t;

'--_ _---.J

FIGURE 6.
DRIVE/HEAD SELECT LOGIC

Winchester Disk Controller Devices

3-9

:E
c
""""
o
""""
o
I

o

CJ1

~

C

-L

o-L
o
I

o

C1I

STATUS REGISTER

COMMAND REGISTER

The status register is a read-only register which
informs the host of certain events performed by the
WD1010 as well as reporting status from the drive
control lines. The term INTRa, if set, will be cleared
when the status register is read. The format is:
765
4
3
2
1
0

This write-only register is loaded with desired
command:
7
6
543
2
o

I BSY

ROY

WF

SC

ORa

CIP

ERR

I

Bit 7 - Busy
This bit is set whenever the WD1010-05 is accessing
the disk. Commands should not be loaded into the
command register while busy is set. Busy is made
active when a command is written into the WD1 01 0-05
and is deactivated at the end of all commands except
the read sector. While executing a read sector command, busy is deactivated after the sector buffer has
been filled. When the BUSY bit is set, no other bits
in either the status or other registers are valid.
Bit 6 - Ready

COM

INSTRUCTION SET
The WD1010 will execute six commands. Prior to
loading the command register, the host must first set
up the task file with the proper information needed
for the command. Except for the command byte, the
other registers may be loaded in any order. Any subsequent writes to the command register will be ignored
until execution is completed indicated by the resetting of the CIP bit in the status register.

Bit 4 - Seek Complete
This bit reflects that state of the SC. When a seek
has been initiated by a command, it will pause until
the seek is completed.
Bit 3 - Data Request
This bit reflects the state of the BORa. It is set when
the sector buffer should be loaded with data or read
by the host, depending upon the command.
DRalBORa remains high until BRDY is sensed,
indicating the operation is completed. The BRDa
signal can be used in DMA interfacing or Programmed
1/0, while the ORa bit can be used only for programmed 1/0 transfers.
Bit 2 - Reserved
Not used. This bit is always forced to a zero.
Bit 1 - Command In Progress
When this bit is set, a command is being executed
and a new command should not be loaded until reset.
Although a command may be executing, the sector
buffer is still available for access by the host. When
0) the status register
the WD1010 is not busy (bit 7
may be read. If other registers are read while CIP, the
status register contents are returned.

=

Bit 0 - Error
This bit indicates that a non-recoverable error has
occurred. When the Host reads the status and finds
this bit set, it must then read the Error Register to
determine the type of error. This bit is reset when a
new command is written into the command register.

3-10

COMMAND SUMMARY
COMMAND

This bit reflects the state of the WF. Whenever the
WF bit goes high, an interrupt will be generated.

0

The command begins to execute immediately upon
loading. This register should not be loaded while the
Busy or CIP bits are set in the status register. The
INTRa, if set, will be cleared by a write to the command register.

This bit reflects the state of DRDY.
Bit 5 - Write Fault

MAN

RESTORE
SEEK
READ SECTOR
WRITE SECTOR
SCAN 10
WRITE FORMAT

7
0
0
0
0
0
0

6
0
1
0
0
1
1

5
0
1
1
1
0
0

4 3 2 1
1 R3 R2 R1
1 R3 R2 R1
0 I M 0
1 0 M 0
0 0 0 0
1 0 0 0

0
Ro
Ro
T
T
T
0

R3-Ro Rate Field
For 5 MHz WCLK:
R3-Ro = 0000 - 35 IJs.
0001 - .5 ms.
0010 - 1.0 ms.
0011 - 1.5 ms.
0100 - 2.0 ms.
0101 - 2.5 ms.
0110 - 3.0 ms.
0111 - 3.5 ms.
1000 - 4.0 ms.
1001 - 4.5 ms.
1010 - 5.0 ms.
1011 - 5.5 ms.
1100 - 6.0 ms.
1101 - 6.5 ms.
1110 - 7.0 ms.
1111 - 7.5 ms.
Bit 0, ("T") Read Sector, Write Sector Commands
T = 0 Enable retries
T = 1 Disable retries

=

M
Multiple Sector Flag
M = 0 Transfer 1 sector
M
1 Transfer multiple sectors

=

= Interrupt Enable
= 0 Interrupt at BORa time
= 1 Interrupt at end of command

Winchester Disk Controller Devices

(

RESTORE

l

out a rising edge of seek complete, the W01010 will
switch to sensing the level of the SC line. If after 1,024
stepping pulses, the TKOOO lines do not go active, the
W01010-05 will set the Track Zero error bit in the error
register and terminate with an INTRa. An interrupt
will also occur if the write fault goes active or the
OROY goes inactive during execution.

)

RESET INTRa,
ERRORS,
SET BUSY, CIP

The rate field specified (R3-RO) is stored in an internal register for future use in commands with implied
seeks.
SEEK COMMAND

RESET RWC
SET DIRECTION
= OUT
STORE STEP RATE

PULSE BCR
SET AC, INTRa
RESET BSY, CIP

Since except for the SCAN 10 all commands feature
an implied seek, the seek command is primarily used
for overlap seek operations on multiple drives. The
actual step rate used is taken from the rate field,
which is also stored in an internal register for future
use. If OROY goes inactive or WF goes active, the
command is terminated and an INTRa is generated.
The direction and number of step pulses needed are
calculated by comparing the contents of the cylinder
register highllow to the cylinder position number
stored internally. After all steps have been issued, the
internal cylinder pOSition register is updated and the
command is terminated. Seek complete is not
checked at the beginning or end of the command.
If an implied seek was performed, the W01010-05 will
wait until a rising edge of SC is received. If 10 revolutions occur before the rising edge of SC, the W01010
will switch to level sensing of SC.
READ SECTOR

The read sector command is used to transfer one or
more sectors of data from the disk to the sector buffer. Upon receipt of this command, the W01010-05
checks the cylinder registers against its internal cylinder position register to see if they are the same. If
not, the direction and number of steps calculation is
performed and seek takes place. If an implied seek
was performed, the W01010-05 will search until a rising edge of seek complete is received. Write Fault and
OROY lines are checked throughout the command.

ISSUE A
STEP PULSE

RESTORE COMMAND

The restore command is usually used on a power-up
condition. The actual stepping rate used for the
restore is determined by Seek Complete time. A step
pulse is issued and the W01010-05 waits for a rising
edge on the seek complete line before issuing the
next pulse. If 10 index pulses are received with-

Winchester Disk Controller Devices

After seek complete is found to be true (with or
without an implied seek), the search for an 10 field
occurs. The W01 01 0-05 must find an 10 with the correct cylinder, head, sector size, and CRC within 10
revolutions if T bit of command is zero, and within
2 revolutions if T = 1; else the appropriate error bits
will be set and the command terminated if T = 1.
Both the Read and Write sector commands feature
a "simulated completion" to ease programming.
ORa/BORa will be generated upon detecting an error
condition. This allows the same program flow for successful or unsuccessful completion of a command.
If T = 0, an automatic scan 10 is performed to obtain
cylinder position information and then, if necessary,
a seek is performed. The search for the correct 10 field
is continued for 10 more disk rotations.

3-11

:E
c
...".

o
o
o•

...".

(J1

:E
c

..L

o
..L
oI
o
c.n

RESET INTRQ,
ERRORS,
SET BUSY, CIP
STORE STEP RATE

YES

NO

SET ABORTED
COMMAND BIT

3-12

Winchester Disk Controller Devices

:E
c
....
o
....
o
o•

(J1

RESET INTRO,
ERRORS,
SET BSY, CIP

SEARCH
FORID
FIELD

NO

PULSE~

SETINTRO,AL
RESET BSY, CIP, BCS

*lfT bit of command

= 1 then dashed path is taken after 2 index pulses.

Winchester Disk Controller Devices

3-13

:ec
-'"

o
-'"
o
o•
CJ'1

YES

DEACTIVATE BCS
PULSE ~
SET BDRQ
RESET BSY

=

* If T bit of command
1 then dashed path is taken.
* * If T bit of command = 1 then test is for 2 index pulses.

3-14

Winchester Disk Controller Devices

When the data address mark is found, the WD1010-05
is ready to transfer data to the buffer. After the sector data has been transferred, the I flag is checked.
If the I flag is 0, the INTRO is made active coincident
with BDRO, indicating a transfer of data is required
by the host. If I = 1, the INTRO will occur at the end
of the command (Le., after the buffer is unloaded by
the host).
An optional M flag may be set for multiple sector
transfers. When M = 0, one sector is transferred and
the sector count register is ignored. When M = 1,
multiple sectors are enabled. After each sector is
transferred, the WD1010-05 decrements the sector
count register and increments the sector number
When M

For the WD1010 to make multiple sector transfers to
the buffer, the BRDY line must be toggled low to high
for each sector. The sector transfers will continue
until the sector count register equals zero. If the sector count register is non·zero (indicating more sectors are to be transferred but the buffer is full), BDRO
will be made active and the host must unload the buffer. Once this occurs, the buffer will again be free to
accept the next sector in this multiple sector read
command.

= 0 (Single Sector Read)

( 1)
( 2)
( 3)
( 4)
( 5)
( 6)
( 7)
( 8)
( 9)
(10)
When M

register. The next logical sector will be transferred,
regardless of the interleave. Sectors are numbered
at format time by a byte in the ID field.

Host:
1010:
1010:
1010:
1010:
1010:
Host:
1010:
1010:
Host:

Sets up parameters; issues read sector command.
Strobes BCR; sets BCS = 0 (On).
_
Finds sector specified; transfers data to buffer (by WE strobes).
1 (Off).
Strobes BCR; sets BCS
Sets BDRO = 1; sets DRO flag.
If I bit = 1 then (9).
_
Reads out contents of buffer (by strobing RE).
Waits for BRDY then sets INTRO
1; End.
Sets INTRO
1.
Reads out contents of buffer (by strobing RE); End.

=

=

=

1 (Multiple Sector Read)

( 1)
( 2)
( 3)
( 4)
( 5)
( 6)
(7)
( 8)
( 9)
(10)
(11)

Host:
1010:
1010:
1010:
1010:
1010:
Host:
Buffer:
1010:
1010:
1010:

Sets up parameters; issues read sector command.
Strobes BCR; sets BCS = 0 (On).
_
Finds sector specified; transfers data to buffer (by WE strobes).
Decrements sector count register; increments sector number register.
Strobes BCR; sets BCS = 1 (Off).
Sets BDRO = 1; DRO flag = 1._
Reads out content of buffer (by RE strobes).
Indicates data has been transferred by asserting BRDY.
When BRDY is asserted, go to (11) if sector count
O.
Go to Step (2).
Activates I NTRO.

WRITE SECTOR

=

fact that a bit cell can extend from 295ns to 315ns
during a write cycle. If retries are disabled and if the
ID field cannot be found within 2 revolutions, the ID
not found bit is set and the command is terminated.

The write sector command is used to write one or
more sectors of data to the disk. Upon receipt of this
command, the WD1010-05 checks the cylinder
registers against its internal cylinder position register
to see if they are the same. If not, the direction and
number of steps are calculated and a seek command
takes place. Write fault and DRDY lines are checked
throughout the command.

If retries are enabled, and the ID field cannot be tound
within 10 revolutions, an automatic scan ID and seek
commands are performed. The ID Not Found error bit
is set if the ID field is not found after 10 more
revolutions.

After Seek complete is found to be true (with or
without an implied seek), the BDRO signal is made
active and the host proceeds to load the buffer. When
the WD1010-05 senses the BRDY line going high, the
ID field with the specified cylinder, head, and sector
size is searched for. Once found, the write gate signal
is raised and the data is written to the disk. It is
necessary to resynchronize the write data due to the

During a multiple sector write operation (M flag =
1), the sector number is incremented and the sector
count register is decremented. If the BRDY lines is
asserted after the first sector is read out of the buffer, the WD1010-05 will continue to read data out of
the buffer for the next sector. If BRDY is inactive, the
WD1010-05 will raise BRDO and wait for the host to
place more data in the buffer.

Winchester Disk Controller Devices

3-15

=E

c...a.

o
...a.
o
o•
c.n

:ec
-"

o
o
o•

-"
01

INCREMENT SECTOR
NUMBER; DECREMENT
SECTOR COUNT

3-16

SEARCH.
FORID
FIELD

SET ABORTED
COMMAND
BIT

*If retries disabled then dashe~ path is
taken after 2 index pulses.

PULSE BCR
SETINTRQ
RESET BSY, CIP
DEACTIVATE SC"S

Winchester Disk Controller Devices

In summary then, the write sector operation is as follows:
(
(
(
(
(
(
(
(
(

1)
2)
3)
4)
5)
6)
7)
8)
9)

Host:
1010:
Host:
1010:
1010:
1010:
1010:
1010:
1010:

....:E
o

Sets up parameters; issues write sector command.
Sets BORQ = 1, ORO flag
1.
Loads buffer with data (by WE strobes).
Waits for BROY = low to high.
Finds specified 10 field, write out sector.
If M = 0, then interrupt; End.
Increments sector number, decrements sector count.
If sector count = 0, then interrupt; End.
Go to (2).

-=--

o

oI

o

CJ1

recorded in any interleave factor desired. The remaining memory in the sector buffer may be filled with
any value; its purpose is only to generate a BROY to
tell the W01010-05 to begin formatting the track.

SCAN 10
The scan 10 command is used to update the head,
sector size, sector number and cylinder registers.
The ready and write fault lines are checked
throughout the command. When the first 10 field is
encountered, the 10 information is loaded into the
SOH, cylinder, and sector number registers. The internal cylinder position register is also updated. If a bad
block is detected, the bad block bit will also be set.
CRC is checked and if an error is found, the
W01010-05 will retry up to 10 revolutions to find an
error-free 10 field. There is no implied seek with this
command and the buffer is left undisturbed.

An implied seek is also in effect on this command.
As in other commands, if the drive number has
changed, an 10 field will be scanned for cylinder position information before the implied seek is performed.
If no 10 field can be read (because the track had been
erased or because an incompatible format had been
used), an 10NF error will result and the Format command will be aborted. This can be avoided by issuing a Restore command before formatting.
The sector count register is used to hold the total
number of sectors to be formatted, while the sector
number register holds the number of bytes minus 3
to be used for Gap 1 and Gap 3. For instance, if the
sector count register value is 2 and the sector number
register value is 0, then 2 sectors are written and 3
bytes of 4E hex are written for Gap 1 and Gap 3. The
data fields are filled with FF hex, and CRC is
automatically generated and appended. The sector
extension bit of the SOH register should not be set.
After the last sector is written, 4E hex is filled until
index.

FORMAT
The format command is used to format one track
using the task file and the sector buffer. During this
command, the sector buffer is used for additional
parameter information instead of sector data. Shown
in Figure 7 is the contents of the sector buffer for a
32 sector track format with an interleave factor of two.
Each sector requires a two byte sequence. The first
byte designates whether a bad block mark is to be
recorded in the sector's 10 field. A 00 is normal; an
80 hex indicates a bad block mark for that sector. In
the example of Figure 7, sector 04 will get a bad block
mark recorded.

The Gap 3 value is determined by the drive motor
speed variation, data sector length, and the interleave
factor. The interleave factor is only important when
1:1 interleave is used. The formula for determining

The second byte indicates the logical sector number
to be recorded. Using this scheme, sectors may be

DATA
AOOR
00
08
10
18
20
28
30
38
40

0
00
00
80
00
00
00
00
00
FF

1
00
02
04
06
08
OA
OC
OE
FF

2
00
00
00
00
00
00
00
00
FF

3
10
12
14
16
18
1A
1C
1E
FF

4
00
00
00
00
00
00
00
00
FF

5
01
03
05
07
09
OB
00
OF
FF

6
00
00
00
00
00
00
00
00
FF

7
11
13
15
17
19
1B
10
1F
FF

FO

FF

FF

FF

:
FF

FF

FF

FF

FF

FIGURE 7.
FORMAT COM,MAND BUFFER CONTENTS

Winchester Disk Controller Devices

3-17

the minimum Gap 3 value is:

=E

c
....
o
....
o
o•

CJ1

Gap 3 = 2*M*S + K + E
M = motor speed variation (e.g., .03 for ± 3%)
S
sector length in bytes
K = 25 for interleave factor of 1
K = 0 for any other interleave factor
E. = 7 if the sector is to be extended

C')

o..w

«-t
C!l

1----4 -- ,.-(J)

W
1-0

>-0

Like all commands, a write fault or not ready condition will terminate the command. Figure 8 shows the
format that the WD1010-05 will write on the Disk.

10

RESET INTRQ,
ERRORS
SET CIP, BSY

u.oo

a:
SETINTRQ,AC
RESET BSY, CIP

oI-

U

«~

W

(J)

:x:
U

«
W
a:

ou.
o

W

1----4--

~

(J)

W

W

0..
W

~8

a:

10C')

Ua:UN
Ua:U~

o

...J

W

u::

:X:W«O

Q

II

o

US

r

II
'#:
(,)
Q)

en

-OWZI-

....

«~

* If retries are disabled, path

is taken after 2 index pulses.
FIGURE 8.
FORMAT

3-18

Winchester Disk Controller Devices

=E
c
......

o
......

o

6

RESET INTRa,
ERRORS,
SET CIP, BSY
ACTIVATE BDRa

CJ1

WRITE GAP 1
OR GAP 3

Nq

EXTEND
GAP

DECREMENT
SECTOR COl!NT

SEEK TO
DESIRED CYL

WRITE
SECTOR

WRITE4E'S
UNTIL INDEX

YES

SET ABORTED
COMMAND BIT

Winchester Disk Controller Devices

RESETW~m
PULSE B(;R
SET INTRa
RESET BSY, CIP

3-19

ELECTRICAL CHARACTERISTICS

~

c
.....

Q

.....

Q

o
c.n

NOTE: Maximum ratings indicate operation where
permanent device damage may occur. Continuous
operations at these limits is not intended and should
be limited to those conditions specified in the DC
operating characteristics.

MAXIMUM RATINGS
Vcc with respect to Vss (Ground) .......... + 7V
Max Voltage on any Pin with
respect to Vss ............... -0.5V to + 7.0V
Operating Temperature ............. 0oC to 70°C
Storage Temperature .......... -55°C to + 125°C
DC Operating Characteristics TA
SYMBOL

= OOC to 70°C; Vss

CHARACTERISTIC

MIN

V IH
V IL
VOH
VOL
VOL
Icc

Input Leakage
Output Leakage (Tristate & Open
Drain)
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Low Voltage(Pins 21-23)
Supply Current

V IH
V IL
TRS
C IN

Input High Voltage
Input Low Voltage
Rise and Fall Time
Input Capacitance

IlL
10L

OV, Vcc

= + 5V

± .25V

MAX

UNITS

±10

~A

VIN

± 10

~A

VOUT

200

V
V
V
V
V
mA

10
- 100~A
10
1.6mA
10
4.8mA See Note 10
All Outputs Open

0.5
30
15

V
V
nsec
pF

2.0
0.8

204
004
0045

CONDITIONS

= A to Vcc

= A to Vcc

=
=
=

For Pins 25, 34, 39:

AC Timing Characteristics TA

4.6

OOC to 50°C; Vss

= OV, Vcc

.9V to 4.2V points

+5V ±.25V

HOST READ TIMING
HOST READ TIMING WD1 01 0-05 WC
SYMBOL
TASE
T OAC
TRE
TOOH
T HLO
TRDR
TCSE

3-20

5 MHZ

CHARACTERISTIC
ADDR Setup to RE
Data Valid from RE
Read Enable Pulse Width
Data Hold from RE:
ADDR, CS, Hold from RE
Read Recovery Time
CS Setup to RE

MIN

MAX

100

A
20
0
300
0

375
10
200

UNITS

CONDITION

nsec
nsec
~sec

nsec
nsec
nsec
nsec

See Note 8

Winchester Disk Controller Devices

ADDR

-==><0

:E

c.....

Y

Ao. Al. A2 STABLE

I------------------------------~~---------

I

TAHW--"

CS ~i

I

I

~TSEW~

-.!

I

TWER~_._

ri.-TCHW

I

o

'--

(J1

I

~

WE

o.....
o

F--~

.-~,

TWE

~ ~TDH

i

:4--TDS~ I

DBO-7

><><><2><.

HOST WRITE TIMING
HOST WRITING TIMING WD1 01 0-05
SYMBOL

TSEW
Tos
TWE
TOH
TAHW
TWER
TCHW

CHARACTERISTIC

ADDR, CS Setup to~E
Data Bus Setup to WE
Write Enable Pulse Width
Data Bus Hold from WE
ADDR Hold from WE
Write Recovery Time
CS Hold Time from WE

MIN

MAX

UNITS

0
_2
.2
10
30
1.0
0

10
10
10

fJ.sec
fJ.sec
fJ.sec
nsec
nsec
fJ.sec

CONDITION

See Note 1
See Note 9

BUFFER READ TIMING
BUFFER READ TIMING (WRITE SECTOR CMD) WD1 01 0-05 WC
SYMBOL

T REV
TREB
TROS
TRR
TRF
THRE

CHARACTERISTIC
-

-

RE Float to RE Valid
RE Output Pul~Width
Data Setup to RE
RE Repetition Rate
RE Float from BCS
Data Hold from RE

Winchester Disk Controller Devices

MIN

15
300
140
1.2
0

=

5MHZ

TYP

MAX

UNIT

400

100
500

nsec
nsec
nsec
fJ.sec
nsec
nsec

1.6

2.0
100

CONDITIONS

CL = 50 pf
See Note 4

CL

= 50 pf

3-21

:E

c.....
o
.....

BCS

oI
o

~~~:~---T-W-EV------------------------------------------~I~

WE---I(OUTPUn

CJ1

. TVWE
DB0-7

~

~p---"";;""'~"- : I

-.!

1:40~ ~ THWE
11_-----.;

--------------4-(~~

DATA VALID

')>------__~(

DATA VALID

)-fIt---

T R R - - - - - I..
~,

,..

BUFFER WRITE TIMING

BUFFER WRITE TIMING (READ SECTOR CMD) WD1 01 0-05 WC
SYMBOL

TWEV
TWRS
TVWE
T HWE
TRR
TWF

MIN

CHARACTERISTIC

15
300

WE Float to WE Valid
WE Output Pulse Width
Data Valid from WE
Data Hold from WE
WE Repetition Rata
WE Float from BCS

'"

RO/

60
1.2
15

= 5 MHZ

TYP

MAX

UNIT

400

100
500
150

nsec
nsec
nsec
nsec
f-Isec
nsec

1.6

/."

2.0
100

CONDITIONS

CL = 50 pf
See Note 4

See Note 2
CL = 50 pf

:'-TRO--':

~------

I

I

~

I

______________________-J.

/

I

I
I
~ TX1...,. TX2

1

+l

1 - - - -......

.-------'""" I

RCLK _ _-.J

ORUN _________________________________________________
""-

TORN

~

/

READ DATA TIMING
READ DATA TIMING WD1010-05 WC
SYMBOL

T RCP
TX1
TX2
TRD
T DRN
T RCF

3-22

CHARACTERISTIC

RCLK Pulse Width
RD from RCLK Transition
RD to RCLK Transition
RD Pulse Width
DRUN Pulse Width
RCLK Frequency

5 MHZ
MIN

95
0
20
40
30
.250

TYP

MAX

UNIT

2000

nsec
nsec
nsec
nsec
nsec
MHz

TRCP
TRCP
TRCP

5.25

CONDITIONS

50% Duty Cycle

See Note 6

Winchester Disk Controller Devices

A==;BRY~

,

BRDY

~.WE

~
I

,

""TRO.'

BDRO

~

~TMR~MRW.J
I

MR
BGR

I
~

BGR

TMRB~

WGLK
FWG

STEP

,

RGLK
I

INDEX

.-

I

•

.'

FRG

I

MISCELLANEOUS TIMING

MISCELLANEOUS TIMING
MISCELLANEOUS TIMING
SYMBOL

T RO
TSCR
TSTP
T 1DX
TMR
Fwd· 05)
F Rd·05)
T SRY
T MRS
T MRW

CHARACTERISTIC

MIN

BORQ Reset from BROY
Buffer Counter Reset Pulse
Width
Step Pulse Width
Index Pulse Width
Master Reset Pulse Width
Write Clock Frequency
Read Clock Frequency
BROY Pulse Width
-MR Trailing to BCR
MR Trailing to Host Write

=

Winchester Disk Controller Devices

MAX

UNIT

200

nsec
J-Isec

1.6

1.B

B.3

B.4

B.7

500
24
.25
.25

5.0
5.0

5.25
5.25

3.2

6.4

BOO
1.6
6.4

NOTES:
1. AC timing measured at VOH
2.0V, VOL
O.BV,
CL
50 pf.
2. Based on WCLK = 5.0 MHz.
3. 24 WCLK periods (4.B J-Isec at 5.0 MHz).
4. 2 WCLK ± 100 nsec.
5. To drive a OMA controller, BROY must be >4 J-Isec
or a spurious BORQ pulse may exist for up to 4
J-Isec after riSing edge of BROY.

=

TYP

40
1.4

=

J-Isec
nsec
WC
MHz
MHz
nsec
J-Isec
J-Isec

CONDITIONS

See Note 2
See Note 2
See Note 3
50% Duty Cycle
See Note 6
See Note 5
See Note 2
See Note 2

6. T RCF = TWCF ± 15%.
7. 2 WCLK ± 50 nsec.
B. RE may precede CS if CS plus RE meets the
TRE width.
9. WE may precede CS if CS plus WE meets
the TWE width.
10. Pins 21-23 should be loaded with a 1K pull-up
resistor.

3-23

~
C
......
0
......
0
0•

(J'1

:ee

TWO-..!

.....
0
.....

I
I
I
I

WO

0
0•

,1I

-+4

I

WCLK - f r . T W C

C11

_

I..

LATE\,

~
TWCF

,
,

l+-

TWO~

I

\

I

\.

.I

14-

TWO

I

I

t

t.

\

.'
/

I
I

I
~

EARLY

~TWLE
I
I
I
I

1.

I
I
~
I

'-r+-TELW
I

I
I

t

~

WRITE DATA TIMING
WRITE DATA TIMING WD1010-05 WC
SYMBOL
I

TwC
Two
TWLE
T ELW
TWCF

3-24

=

5 MHZ

CHARACTERISTIC

WClK Pulse Width
Propagation Delay WClK
to WD
WClK to leading Early/late
WClK to Trailing Early/late
WClK Frequency

MAX

UNIT

95
10

2000
65

nsec
nsec

10
10
.250

65
65
5.25

nsec
nsec
MHz

MIN

TYP

CONDITIONS

See Note 6

Winchester Disk Controller Devices

WESTERN

c

o

R

PO

R

DIGITAL
A

T

o

N

:E

c
......

WD1010 Application Notes
FLEXIBLE CONTROLLER MATES WITH POPULAR
WINCHESTER DRIVES

To take advantage of the growing demand for Seagate
Technology-type 5 1/4-in. Winchester disk drives in
personal computers, electronic work stations, and
small-business systems, designers need an
appropriate controller that is inexpensive. In fact,
today's designs must implement the control link between a Host CPU and a disk drive at far lower cost
than the drive itself. That requires a single-chip controller rather than discrete, gate-array-intensive circuits that take up valuable board space in ever
smaller computer equipment.
Such a device is now available in the form of an LSI
single-chip Winchester controller-formatter. The chip
incorporates 80% of the circuitry required for Winchester control, eliminating between 50 and 75 SSI
and MSI devices used in earlier designs.
A controller that claims Seagate compatibility must
be sufficiently flexible to meet not only the company's
original ST506 specifications, but also the various
deviations from them. The basic specifications
include a data rate of 5.0 Mbits/s and open-collector
outputs and differential signal inputs for the separate
control and data interface cables. The recording format is modified frequency modulation (MFM), but
more importantly, the structure of the format defines
both specific address-mark bytes and ID fields. These
are fixed speCifications, but manufacturers of
Seagate-type drives sometimes make other changes.
For example, the track density on high-capacity drives
may be greater than that in the original ST506
specification. Also, the number of sectors and bytes
per sector on each cylinder can vary according to the
application. In each case, a compatible controller
must be able to handle the original specifications plus
the deviations.
The ST506 interface is a spinoff of the Shugart
Associates SA1000 drive, first introduced in 1979. Two
important differences between the interfaces are the
data rates and a timing·clock differential signal on
the SA1000. The latter operates at 4.34 Mbits/s vs 5
Mbits/s for the ST506, but the remaining signals have
enough similarity to permit a single controller design
to run either an B-in. SA1000 drive or the 5 1/4-in. ST506
drive. The advantage of the WD1010 Winchester
controller-formatter is that it works with either and
with other manufacturers' variations as well.
Operation of the drive begins when a Host processor
initiates a command after first loading a set of internal task registers called the task file. Information such

Winchester Disk Controller Devices

o
......
o

as cylinder, sector, and head number is written to
these registers, which are selected by address lines.
The memory-mapped register scheme allows
Individual accesses to each register. Thus, the Host
need not waste valuable time reading all the registers
to obtain a specific parameter.
The WD1010, which comes in a 40-pin DIP or 44-pin
QSM, is run by an internal microcontroller - a PLA
(programmable logic array) serving as a state machine
(Fig. 1). This logic controls the flow of data throughout
the chip, recognizes and processes commands, and
formats the data.
WRITING AND READING DATA

During a write operation, parallel data is read from
the data bus and written to a specific sector. But first
the cylinder and sector must be located on the
requested disk drive. The WD1010's microcontroller
accesses its internal cylinder-position data and compares it with the requested cylinder number. If
necessary, a seek is performed automatically to position the head assembly over the desired cylinder.
If the drive requested Is changed before a Seek Command is executed, the WD1010 enables its read logic
and searches for an ID field on the currently selected
drive. Then it reads the cylinder number for the new
ID field and determines whether to seek in or out to
find the requested cylinder. This so-called implied
seek is a feature of all commands (see "Macro Commands Provide Multiple Options").
After the WD1010 finds an ID field that matches the
cylinder, head, sector, sector size and CRC (cyclic
redundancy check) value, it writes a field of Os and
a new address mark - later these two fields will be
used for synchronization during a read operation. The
chip then reads parallel data in from the data bus,
serializes it, and converts it into the MFM format.
Next, a new CRC value is calculated for the incoming data and is appended to the data field (after the
last byte). If the original command specifies multiple
sectors, the next logical sector must be searched for
and the process repeated. After the last sector is written, the WD1010 gives the bus back to the Host and
waits for the next command.
Although the chip does not generate an error correction signal, an optional command bit can be set to
disable cyclic redundancy checks of the data field.
The sector is extended by seven bytes to allow the
Host to write its 56-bit error detection and correction
code. Later, during a read operation, these seven
bytes are transferred back to the Host to permit it to
identify a syndrome and correct any errors that were
encountered. For systems that require such operations, the WD1014 error detection and correction and

3-25

WD1015 buffer controller chips are available.

:ec
.....

Reading is similar to writing except that data is sent
out on the data bus and written into the sector

buffer at the Host. MFM data is entered on the RD
pin along with a synchronous clock (RCLK) generated
from an external data separator (Figure 2).

o
.....

o

RE

-.I

WE

I
I

A2- AO 3
IRO

MAGNITUDE
COMPARATOR

...I
HOST
INTERFACE

MR

cs
MICROCONTROLLER

SCR
BRDY
BORO

DRIVE
INTERFACE

(PLA)

BUFFER
INTERFACE

BCS
VCC----'
PHASE-LOCKED
LOOP INTERFACE

VSS----.

Figure 1.

The architecture of the WD1010 Winchester controller-formatter chip is designed to reduce a Host processor's
overhead burden. An internal microcontroller (PLA) manages data flow, incoming commands, and formatting.
Since the data rate is relatively high, the data
separator must instruct the controller to lock on to
the incoming data stream only during a field of 1s
and Os. A Data Run (DRUN) signal to the WD1010
indicates such an occurrence. When DRUN is active,
the WD1010 counts off 16 bits - 2 byte time - sets
the Read Gate (RG) Signal, and starts to search the
data stream for an address mark.

r-==~=-----tRD

t-----4DRUN
t----~RG
t----~WCLK

WD1010

IMPLEMENTING THE
PRECOMPENSATION ALGORITHM
ALREADY
SENT

SENDING

TO BE
SENT

SHIFT
REQUIRED

X
X

1

1

0

Early

0

1

1

Late

0

0

0

1

Early

1

0

0

0

Late

NOTE: All other patterns produce no shift.

3-26

Figure 2.

A separate IC - the WD1012 - performs the data
separation for the WD1010. The data separator sends
a DRUN signal to the controller when it encounters
a data field (1s and Os).

Winchester Disk Controller Devices

An address mark is a unique pattern of clock and data
bits that does not appear in any place that normal
MFM data appears. If an address mark is not detected
within nine bytes or if a non-O pattern is detected
within nine bytes, RG is turned off and the search is
repeated. Since the data fields within. sectors can contain Os or all1s, the DRUN algorithm is also triggered
in these cases. But the address mark will not be
detected, preventing erroneous data from being
transferred.
After the ID field is compared and verified, a search
begins for the address mark. Resynchronization
occurs and the data is transferred to an internal MFMto-NRZ converter. Data is then shifted through a
double-buffered shift register and placed on the data
bus for loading to the buffer. Either the cyclic redundancy code at the end of the data field is checked
or the error detection and correction bytes are
transferred in parallel to the host, depending on which
option is used. Then the host processor can read the
data from its local buffer.
Like all magnetic recording media, Winchester disks
are not immune to the effects of bit shifts at high
recording densities. The WD1010 uses an algorithm
that informs external delay circuits when to shift outgoing data. A register within the task file specifies
which cylinder receives reduced write current and if
precompensation is needed. Typically, both occur on
the same cylinder about half way down the disk
surface.
The WD1010's precompensation signals are called
Early and Late. Depending on the bit pattern leaving
the device, data will be shifted early, late, or not at
all. The WD1011 data separator implements the
precompensation delay network (Figure 2).

Since the Early signal and the current data (or
clock) bits leaving the WD1010 have already occurred, the WD1.Q1Lperforms no delay function on
Early. If both Early and Late are inactive, the
WD1011 inserts a 12-ns delay; if only Late is active, it inserts a 24-ns delay. The result is a ± 12-ns
shift of the data from its nominal position. An inactive Reduced Write Current (RWC) signal from the
WD1010 disables the WD1011. The WD1010 then furnishes precompensation signals independent of current cylinder position.
INTERFACING WITH CABLES AND BUSES
The remaining function on the drive side is to provide sufficient buffers to drive the cables between the
chip and the interface connectors. Single-ended opencollector signals are used for the control cable, and
differential receiver-drivers are used for the data cable
(Figure 3). Each line must have such buffers, since
the controller is deSigned to drive one TIL load on
all inputs and outputs.
At a 5-Mbitls data transfer rate to the host interface,
a byte of data must be read every 1.6 fLs - in 8-bit
parallel form. Few microprocessors can access a port
and check status within this period. Consequently,
a design objective of the WD1010 is compatibility with
a programmed 1/0 environment, as well as the support of off-line error detection and correction.
Moreover, the chip can transfer multiple sectors on
one command. To achieve such performance within
the constraints of a 4(}pin package, the WD1010 relies
on a unique approach to the traditional peripheral
interface.
Three modes of communication can exist at the host
interface: between the host and the WD1010, between
the host and the buffer, and between the WD1010 and
the buffer. For the host-WD1010 communication the

~--------------~+
TO DRIVE INPUTS

7438

a_------a

TO DRIVE INPUTS

COMMON
WD1010

WD1010

+5V

51

220
FROM DRIVE

......-~~--a OUTPUTS

51

~--4--""'-------O

+

FROM DRIVE OUTPUTS

+5V

(A)

(8)

Figure 3.
Buffering circuits from the WD1010 to the control cable (A) and the data cable (B) must be used because the
controller has a rather limited drive capability (one TIL load each on inputs and outputs).

Winchester Disk Controller Devices

3-27

=E

c
.....

o
.....
o

:E
c
....
o

....

chip, like many microprocessors, talks over an 8-bit
bi-directional bus, plus Read, Write and chip select
lines (Figures 4,5). Three address lines access
registers within the chip.

o

In host-buffer or WD101Q-buffer communications
(Figures 4,5), when the chip reads or writes to the buffer, the Buffer Chip Select (BSC) line is pulled low.
This signal should be used to disconnect the host
data bus and Read and Write lines from the WD1010 .

ADO~----------+-~+-----+---------------------------~~
A~
A~

~
~

~

~

DBO-DB7

HOST
PROCESSOR

WD1010

'-------t--t---tBCR
JW t--------t-t
WR

>--t+-==----------------------+-+---tR'E
WE

BUSY

BCS

Figure 4.

Communications between a host and the WD1010 can be effected with the static RAM and binary counter circuitry shown in Figure 4. These devices form a sector buffer that stores data sent from the host or the controller. This hardware handles both read and write operations on multiple sectors.

ADOr-----------~~~----------------------------------~AO

AD1
AD2

A1
A2

~

~

DBO-DB7

HOST
PROCESSOR

DATA BUS (8)

~;'T5~O

MR J - - - - - - D C t--------I BCR
FIFO
WD1010
BUFFER
EMPTY
)-----------t BDRY
FULL

RDr-------+-t>---~+----------;_--------~------------~~

WE

WR

BITSYr-------~-L--~--_.-------_+~----~r+------------~BCS

Figure 5.

A variation on the circuit of Figure 4. uses a WD1510 FIFO buffer to replace the counter-RAM circuitry. The
scheme works well at high throughput rates since the buffer need not be filled to transfer data supplied by
the WD1 01 0 to the host.

3-28

Winchester Disk Controller Devices

The Read (RE) and Write (WR) lines become outputs from the WD1010 and are strobed as each byte
is placed on the bus.
The sector buffer in Figure 4 is implemented with a
binary counter and a static RAM. With each RE or
WE probe, the counter is incremented so that the
following byte can be read from or written to the next
sequential location in the RAM. After all memory locations are written to, a carry Signal from the counter
goes to the Buffer Ready (BRDY) line of the WD1010.
This signal informs the controller that the counter has
rolled over and that the buffer is either full or empty,
depending on the command.
During multiple-sector transfers, the RAM can be as
large as the available sectors on each cylinder. The
controller continues to load the RAM with data when
a sector is being read. When no more memory is
available, BRDY Signals the WD1010. The command
will then pause, wait for the host to dump the
memory, and then begin filling the RAM again. This
scheme permits both read and write operations on
multiple sectors.
Signals for host and buffer control include the Buffer Counter Reset (BCR) line, which is pulsed when
BCS makes an active transition. BCR resets the
binary counter before a read or write operation. Since
address location 000 does not exist in the WD1010,
a decoder can be used to make this address location enable the RAM and simulate a data register. For
DMA applications, the Buffer Data Request (BRDQ)
line is activated when data is available for host use.
Numerous other methods can be used with these
same control signals. For example, a first-in, first-out
buffer (Figure 5) can replace the counter-RAM. In this
scheme, the host can dump data before the WD1010
fills the buffer. With sufficient throughput, the FIFO
buffer need not have the storage capacity of an entire sector if the host can empty it quickly enough
with a burst mode. In that case, the BRDY signal
becomes the OR function of the Empty and Full
Signals from the FIFO buffer.
MACRO COMMANDS PROVIDE MULTIPLE OPTIONS
Each of the WD1010 Winchester controller-formatter's
six macro commands contains several option flags.
These flags allow the selection of stepping rates,
multiple-sector transfers, and interrupt timing. The
WD1010's task file contains additional options that
are programmed before the command is actually
issued. The operations of each command are as
follows:
Restore causes the readlwrite head assembly to move
to track 000. The stepping rate is determined by the
state of Seek Complete (pin 32), which is activated
by the drive to indicate its readiness. The stepping
rate specified in the Restore Command is not actually
used but retained internally for an implied track later
on.
Activation of Seek causes a seek operation for any
desired cylinder. The selected cylinder is loaded into

Winchester Disk Controller Devices

the cylinder register. Then the controller decides
which way to seek and how many steps to use. The
Seek Complete line is not checked, making possible
overlapping seek operations on several drives.
The actual transfer of data from the WD1010 to sector buffer is performed under the Read Sector command. This command also causes a search for the
specified cylinder, drive, head, and sector. Multiple
sectors are specified and enabled through the sector count register. If the multiple-option flag is set,
the number of sectors specified are transferred to the
buffer.
Data in the sector buffer is written on the disk under
the Write Sector command. Like the Read Sector
command, it specifies and enables multiple drives
through the sector count register.
Both the Read and Write Sector commands will retry
up to eight times before automatically performing a
restore operation. After a restoration, the controller
seeks out the marginal sector and tries to determine
whether an error condition was caused by a mispositioning of the head or a problem in the actuator.
The Format command is used to initialize a track with
ID fields, gaps, and all information necessary for
subsequent read and write operations. The sector buffer plays a unique role in this command, since it provides information on error mapping and interleaving
rather than data from a sector. The order in which
each sector is to be recorded is specified in the buffer, together with information indicating whether a
sector contains a bad block or an error flag. Gap sizes,
number of sectors, and other information are
specified in the task file to allow further control over
the format. By incrementing the cylinder number
register, an entire surface can be formatted by
accessing just two registers.
THE WD1010'S MACRO COMMANDS
CODE
1 0
3 2
7
6 5 4
0 0 0 1 R3 R2 R1 Ro
Restore
0 1 1 1 R3 R2 R1 Ro
Seek
0 0 1 0 1 M 0 0
Read Sector
0 0 1 1 0 M 0 0
Write Sector
0 1 0 0 0 0 0 0
Scan ID
0 1 0 1 0 0 0 0
Write Format
M

= Multiple Sector Flag

M = 0 - transfer 1 sector
M = 1 - transfer multiple sectors

= Interrupt Enable
= 0 - interrupt at BDRQ time
= 1 - interrupt at end of command

3-29

A MULTIPLE-DRIVE SYSTEM

the status register to determine whether any bits are
set in the error register.

For multiple drive-head configurations, the WD1010's
sector-drive-head (SDH) register is decoded at address
110 to produce individual, latched drive-selection
signals whenever the host writes to this address location. Binary head selection does not require a
separate decoder, since one is located at the drive.

Bit 0 of the status register is set if any of 5 bits in
the 8-bit error register are set - bit 0 establishes the
logical OR of the status register. Other error indicators
include a Bad Block Detect bit, which is activated
when an ID field contains a bad block mark, and an
ID Not Found bit, which is set when the desired
cylinder, head, sector, or size parameter is not found
after 16 revolutions of the disk. The latter is also set
if the data address mark of the data field is incorrect
when a read is executed.

When the WD1010 senses a change in drive number,
it automatically reads a cylinder. This takes place
before the execution of the current command. The
chip records the new cylinder number it has read and
stores it internally as a reference for future seek
operations on the current drive.
After the execution of any command, the WD1010
informs the host processor of any errors encountered
during execution. On-board status and error registers
report error conditons and signal status from the
drive. To eliminate tedious error detection procedures,
the host processor need only check the error bit in

~

A

....
TO
HOST

DO
01
02
03
04
05
06
07
WE
AO

(
"(

,

..

(

A1

(

A2

..,

~

.,

(

TO
DRIVE

HEAD SELECT 0

00

DO

HEA o SELECT 1

01

01

HEAD SELECT 2

02

02.- I-~

03

03'-1-

DRIV ESELECT 1 . - Yo

A

DRIV ESELECT2.- Y1

041-

DR IV E SELECT 3 . . - Y2

Lr°4

-----

DRIV E SELECT 4..- Y3

B

CP

LATCH

1~7
I~

~

IY

I~

BCS

WD1010

2·TO·4·LlNE
DECODER

Figure 6.

Four Winchester drives can be controlled by the WD1010 using an external latch and a 2-to-4-line decoder. If
the drive being accessed changes, the controller performs an automatic read operation. It records the cylinder
number of the read for future seeks.

3-30

Winchester Disk Controller Devices

WESTERN

DIGITAL

c

A

o

R

p

o

R

T

o

N

:E
c-'"

WD1050 SMD Controller/Formatter

o
01
o

CJ)

FEATURES
•
•
•
•
•
•
•
•

~

C

16 BIT HOST INTERFACE
9.677 MBITS/SEC DATA RATE
SINGLE/MULTIPLE SECTOR TRANSFERS
FIXED SECTOR FROMAT
TTL COMPATIBLE INPUT/OUTPUT
68 PIN JEDEC TYPE C CHIP CARRIER PACKAGE
COMPATIBLE WITH SMD, MMD, FHT, LMD, AND
CMD FAMILIES
SINGLE +5V SUPPLY

NC

CPO
CP1
CP2
CP3
GP4
CP5
CP6
CP7
CPB

DESCRIPTION
The WD1050 SMD Controller/Formatter is an
MOS/LSI device designed to interface an SMD compatible rigid disk drive to a Host processor. The device
is compatible with all rigid disk drives adhering to
Control Data Corporation's flat cable interface for
SMD, MMD, FHT, FMD, LMD and CMD families (CDC
specification 64712400 Rev H). It is TTL compatible
on most inputs and outputs, with interface capability
for 8 or 16 bit data buses.
The WD1050 contains a powerful set of Macro Cernmands for ReadIWrite and control functions. An internal 16 bit task file is used to process a selected
command based upon parameter information in the
file.

cpg

US3
US2
US1

usa
45

TAG3
TAG2

PIN DESIGNATION

The WD1050 operates from a single + 5V supply and
is available in a 68 pin JEDEC Type C chip-carrier
package.

Winchester Disk Control/er Devices

3-31

:E
c
.....

PIN
NUMBER

o
en
o

en
c

3:

2

Vcc
NO CONNECTION

Vcc
NC

3

READ ENABLE

RE

Tri-state bi-directional line, used as an input when
reading the task file and an output when the WD1050
is reading from the buffer.

4

WRITE ENABLE

WE

Tri-state bi-directional line used as an input when
writing to the task file and an output when the
WD1050 Is writing to the buffer_

5

CHIP SELECT

CS

A logic low on this input enables both WE andRE
signals as inputs.

6-8

ADDRESS 0-2

AoA2

These three inputs select a task file register to
receive/transmit data.

NO CONNECTION

NC

DATA BUS 0-15

00-015

Sixteen bit bi-directional bus used for transfer of
commands, status, and data.

26

WRITE DATA

WD

Open drain, NRZ data output which is synchronized
to the Servo Clock Input.

27

READ CLOCK

RCLK

Input clock from the drive which is synchronized
with the Read Data input.

28

SERVO CLOCK

SCLK

A nominal 9.6n MHz clock input from the drive. This
clock must be valid when Unit Ready (Pin 31) is
active and Fault (Pin 34) is inactive.

29

READ DATA

RD

NRZ data input from the drive which must be synchronized to the Read Clock (Pin 25) input.

30

INDEX PULSE

IP

Active high input used to monitor the Index signal
from the drive.

31

SECTOR

SEC

Active high input used to monitor sector pulses from
the drive.

32

UNIT SELECTED

USEL

Active high input used to verify the selected drive.

33

UNIT READY

URDY

Active high input used to inform the WD1050 of a
ready condition on a selected drive. If this line is
made inactive during any command, command
execution is terminated.

34

UNIT BUSY

UBSY

Active high input used to monitor drive status during a unit selection. If the unit had previously been
selected and/or reserved prior to issuing a USTAG,
the UBSY must be made active within one microsecond of the USTAG selection. This signal is used
for dual-channel access applications and should be
tied to ground when not used.

35

GROUND
FAULT

Vss
FAULT

Ground.

36

9
10-25

3-32

DESCRIPTION

SYMBOL

NAME

+ 5V ± 5%

1

power supply input

Active high input used to detect a fault condition
at the drive. Command execution is terminated if
Fault is made active during any command. Only the
Fault Clear Command may be issued while this line
is asserted.

Winchester Disk Controller Devices

PIN
NUMBER

NAME

SYMBOL

DESCRIPTION

::E
c
~

37

SEEK ERROR

SKERR

Active high input used to detect a seek error at the
drive.

o
c.n
o

38

ON CYLINDER

ONCYL

Active high input used to inform the WD1050 when
the heads are settled and positioned over a cylinder.

39

WRITE PROTECT

WPROT

Active high input used to monitor the Write Protect
signal from the drive.

en
~
c

40

NO CONNECTION

NC(TP)

Test Point.

41

NO CONNECTION

NC

42

UNIT SELECT TAG

USTAG

Active high output used for selection of a unit on
USO-US3 lines.

43-45

TAG1-TAG3

TAG1-TAG3

Active high outputs used to strobe specific data out
on the Control Port Lines. Tag definitions are:
TAG1 _ Cylinder address
TAG2 _ Head/Volume select
TAG3 _ Control Tag

46-49

UNIT SELECT 0-3

USO-US3

These four outputs reflect the contents of the unit
address field of the task file and are used to select
one of 16 drives.

50-59

CONTROL PORT
BITS 9-0

CP9-CPO

Ten bit output bus used to issue tag parameters to
the selected drive.

60

NO CONNECTION

NC

61

NO CONNECTION

NC(TP)

Test Point.

62

BUFFER CHIP
SELECT

BCS

Active low output used to enable reading or writing
to the e:------I~ SECTOR COUNT

RESET RG

YES

YES

NO

8

Winchester Disk Controller Devices

3-47

:ec
......
o

9

CJ1

o

CJ)

:is:

c

COMPARE 10 SYNC
CYLINDER, AND
HEAD 10 FIELD,
BYTES FROM DISK

YES

COMPARE SECTOR
10 FIELD BYTE
FROM DISK

NO

3-48

SETIDCE

Winchester Disk Controller Devices

=E

c.....

o
CJ1
o
CJ)

s:
c

YES

NO

NO

YES

NO

NO

YES
YES

NO

Note: If the R Flag is not set, 8 additional bytes are included in the Data Field for appended ECC.

Winchester Disk Controller Devices

3-49

:ec
.....

o
CJ1
o

en

s:
c

YES

YES
WRITE PAD, SYNC,
DATA & CRC (IF
ENABLED) TO DISK

YES

YES

NO

RESET CP1

~

______________

~.~,

12

(READ GATE)

3-50

Winchester Disk Controller Devices

=E

c
-""

o
(J'1
o

(J)

~

c

INCREMENT
SECTOR ADDRESS
DECREMENT
SECTOR COUNT

INCREMENT
SECTOR ADDRESS

RESETBDRQ
PULSE BCR
SETBCS

Note: if the R flag is not set, 8 additional E5 bytes are included in the Data Field for ECC extension.

Winchester Disk Controller Devices

3-51

:e
c
...t.

o
U1
o

en
~
c

WRITE:
SYNC BYTE
E5 DATA FIELD
TO DISK

RESET CPO
(WRITE GATE)
NO

14

NO

• Abort upon loss of URDY or USEL, or receipt of UBSY (all commands).
Abort upon receipt of FLT (all commands except Fault Clear).

3-52

Winchester Disk Controller Devices

:ec
-"

o
en
o

(J)

s:
c

YES

RESET TAG 3
RESET USTAG
FREEZE STATUS
REGISTER

FREEZE
STATUS REGISTER

PULSE Cpg

RESET TAG 3
RESETSCS
PULSE SCR

RESET USTAG

YES

RESET BORQ

PULSE BCR
SET BORQ

SETINTR

• Abort upon loss of URDY or USEL, or receipt of UBSY (all
commands).
Abort upon receipt of FLT (all commands except Fault Clear).

Winchester Disk Controller Devices

3-53

ELECTRICAL CHARACTERISTICS

NOTE:

ABSOLUTE MAXIMUM RATINGS

Maximum limits Indicate where permanent device
damage occurs. Continuous operation at these limits
is not Intended and should be limited to those conditions specified In the DC Electrical characteristics.

Vee with respect to Vss (Ground) .......... + 7V
Max Voltage on any Pin with
respect to Vss ................. -0.5V to + 7V
Operating Temperature ... OOC(3~F) to 70°C(158°F)
Storage Temperature ............. -55°C(-6?OF) 50
+ 125°C(257°F)
DC Operating Characteristics TA
SYMBOL

MIN

~

MAX

UNITS

IlL

10

~

IOL
VIH

Output Leakage

10

~
V

VIL
VOH

Input Low Voltage
Output High Voltage

VOL

Output Low Voltage

0.4

V

Icc

Supply Current

200

rnA

2.0
0.8

± .25V
CONDITIONS

.

VIN

= Vee
= Vee

Your

V
V

2.4

10
10

= 1oo~

= 1.6 rnA

All Outputs Open

FOR PINS 25, 26,27:
VIH
VIL

See Note 1

Input High Voltage

V

Vee
Vss +

Input Low Voltage

V

~0.4V

AC Timing Characteristics TA

= OOC to 70°C; Vss = OV, Vee = +5V

~
ADDR

I

i

:_TSET1~

1

TSET2-":

RE

I

......- - -

I

I

~

THLD!

:v.

:-

'r

I

TRC

" - __ _

I-+--TRDR~

L

I

---!
........
TDOH
-;
I

I
r-TDACC-.:

DO-15

±.25V

X

AO,A1,A2STABLE

•

cs

I

-------------<.~:,...-D-AT-A-V-AL-ID-:...>>---HOST READ TIMING

HOST READ TIMING
SYMBOL

CHARACTERISTIC

MIN

tSET 1

ADDR, Set up to RE

80

tSET 2

CS Set up to RE

0

tDACC

Data Valid from RE

tRC

Read Enable Pulse Width

tOOH

Data Hold from RE

tHLD

ADDR. CS, Hold from RE \

tRDR

Read Recovery Time

3-54

.375

c

t:

Input Leakage
Input High Voltage

t

c
c;
(j

= OOC to 70°C; Vss = OV, Vee = + 5V

CHARACTERISTIC

...

MAX

UNITS

CONDITIONS

nsec
nsec
375

nsec

5.0

",sec

150

nsec

0

nsec

·500

nsec

CL

=100pF

Winchester Disk Controller Devices

AOOR

~

yo

AO,A1,A2STABLE

:E
c

--./'k---=--------""I'f', - a....-TSET1""""':
,
"'I
.'1

:\.

TSET2~

...&.

•

~

o
CJ'1
o

~

l¥

THL01,2

I, ..

:..

en

s:
c

;t.

~..._ _- T W E - - -....

---------"!~ I.... ToH

\. Jc+---

OOc:t i

TOH..... . . .
DATA VALID •

'"OL
___J/~S~

...!

&..-TVWE

DATA VALID

I. .

I 1.

I!'I

I

~~1------

T R R - - - - -..
~I

I

I

BUFFER WRITE TIMING
BUFFER WRITE TIMING (READ SECTOR CMD)
CHARACTERISTIC

tWRB

WE Output Pulse Width

4

SC

See Note 2

tVWE

Data Set up to WE

4

SC

See Note 2

4

SC

See Note 2

16

SC

See Note 2

tDH

Data Hold from WE

tRR

WE

tWF

WE Float from BCS

Repetition

Winchester Disk Controller Devices

MIN

Rate

TYP

MAX

0

UNIT

CONDITIONS

SYMBOL

nsec

3-55

I

=e
o

.cs~
~
~------------------------------------------~s TAF~
~

.....
o
CJ1
o

AE

~I

\..~TAEB~!
-

(OUTPUT)

en
s:
o

I

I

I

I

I

• I I

I"

I

'~- -/

,----§~

~Ii\""

;.a .... TOOH

TAOS

I

I I

~--------_TAA--------~

BUFFER READ TIMING
BUFFER READ TIMING (WRITE SECTOR CMD)
SYMBOL

CHARACTERISTIC

MIN

tREB

RE output Pulse Width

tRDS

Data Setup to RE

MAX

UNIT

4

RE Repetition Rate

tDOH

Data Hold From RE

tRF

RE Float from BCS

CONDITIONS

SC

140

tRR

TAG3

TYP

See Note 2

nsec
SC

16

See Note 2*

nsec

80
0

nsec

~J
~TIS

~

IPORSEC

TICI~

CPI (RGATE)

lJ.
I

I

I
RD(RDATA)

........- - - - - - - - - - - - - - - - - - - - - - -

I
I

I

1

t -I.
I

.iTf.

10

I~

I

TDC~

I-

DATA

1£
T

~I

/wRITE)

H
1

'-- T,SW

I
~

\

•

--..l

' -

________ ___

I_TCW~I

CPO (WGATE)

CPO (WGATE)

(READ)

\:

1

~'------

1,.__---------""

I
, - - T R C _ I_ _ TCp~

,-,- - I

I--~~----~-----------~r~'------

DISK R/W CONTROL TIMING
DISK R/W CONTROL TIMING (SCLK = 9.677 MHZ)
SYMBOL

CHARACTERISTIC

tiS

Index/Sector Pulse Width

tiC

MIN

TYP

MAX

UNIT

.2

1.25

3.0

",sec

CONDITIONS

Index/Sector to CP1 High

60

tRC

CP1 Low from Read Data

56

SC

See Note 3

tcp

CP1 Low to CP1 High

12

SC

See Note 3

SC

See Note 3

tDC

Last Read Data to CP1 Low

16

SC

See Note 3

tcw

CPO High from Read Data

60

SC

See Note 3

tsw

Index/Sector High to CPO
High on FORMAT

3-56

250

nsec

Winchester Disk Controller Devices

US3-USO

ZZZX~

_____

VAL1D
____

I

C~

--..1

I

I

__________

~XZZZZZZ

I.... TUH

I
I

I

~i-----J~.TCG~: ~_________~~!~~~-T-S-H------------a.---- TSG - - - . :

~r--------

I

__ ___________________
I

~

USTAG

UNIT SELECT TIMING

=

UNIT SELECT TIMING (SCLK
SYMBOL

9.677 MHZ)

CHARACTERISTIC

MIN

TYP

MAX

UNIT

CONDITIONS

tSG

US3-USO Setup to USTAG

tCG

CPS Setup to USTAG

4

ClK

See Note 4

tUH

CPS Hold Time from
USTAG

4

ClK

See Note 4

tSH

c~-cpo

1.0

llsec

1.0

US3-USO Hold Time from
USTAG

llsec

ZZZZXI'-_____ ------'III'XZZZ
/f•.
-l\
:
V_ALI__
D

a....-TCT--+-:

I

TAG 1,2

:....-TTC---.J

- - - - - T G W - - -..

I

TAG 3

CP4, 6, 9

----------------------~~--------------------------------------------------------------------T:.- TCP~l''''------.

CP TAG TIMING
CP TAG TIMING 9SCLK
SYMBOL

= 9.677 MHZ)

CHARACTERISTIC

tCT

CP9-CPO Set up to
TAGS 1, 2, or 3

t6GW
tTC
tcp

MIN

TYP

MAX

UNIT

CONDITIONS

5

ClK

See Note 4

TAGS 1 & 2 Pulse Width

4

ClK

See Note 4

CP9-CPO Hold Time from
TAG 1, 2 low

2

ClK

See Note 4

CP4, 6, 9 Pulse Width
During TAG 3 True

4

ClK

See Note 4

Winchester Disk Controller Devices

=E
c

""""
o
CJ'1
o
en

s:
c

:E
c
.....

,..........----- TAF-----....~,

o
o

•

(J1

en
S
c

•

".

AD_>¢;

·

'"",-i: _ _-J/

/

:...- TAA--..t. .:.:.:.:.:.-T-A-H::~--I
..
...I:

ACLK - . - /

~

~----_>C

READ DATA TIMING
READ DATA TIMING
SYMBOL
tRF
tRR
tRH

MIN

TYP

MAX

UNIT

RCLK Frequency

1.0

9.677

10.1

MHZ

Read Data Setup to
RCLK Low

35

nsec

Read Data Hold Time
from RCLK Low

0

nsec

CHARACTERISTICS

CONDITIONS

----TSF-----......~I
I
,,~ _ _ ___..J)-!l-----"_____

I1
...........

SCLK

-A

r

f4 Tws+l

~r---------------------><~

WIT

_____________________

WRITE DATA TIMING
WRITE DATA TIMING
SYMBOL

CHARACTERISTIC

MIN

TYP

MAX

UNIT

tSF

Servo Clock Frequency

1.0

9.677

10.1

MHZ

tws

WD Valid from Servo
Clock High

85

nsec

3-58

CONDITIONS

=

CL
15 pf.
See Note 5

Winchester Disk Controller Devices

=E
c-'"

TCF------~

I.
I

o
U1
o

ClK

en
3:
c
..... TRS

-y

I TBCR I

BCR---~~

SC
RC
RD

MISCELLANEOUS TIMING

MISCELLANEOUS TIMING

MISCELLANEOUS TIMING
SYMBOL

CHARACTERISTIC

tCF
t MR

Master Clock Frequency

t BCR

BCR Pulse Width

t BRQ
tRS

BDRa Reset from BRDY

Master Reset Pulse Width

MIN

TYP

MAX

UNIT

2.0

2.5

MHZ

50% Duty Cycle

JJsec

ClK Active

ClK

See Notes 4&7

12
4
50

Rise of Fall Time

600

nsec

15

nsec

CONDITIONS

See Note 1

t BDBR

BRDY High from
BDRa High

4

See Note 8

tBRDY

BRDY Pulse Width

4

See Note 8

NOTES:
1. It is recommended to buffer the line receiver stage with a TTL or Schottky TTL stage on pins 27, 28 and
29. A current sink capability of.,48 mA with a 100 ohm pull-up resistor will provide both the required rise
and fall times and also the required voltage swing. It is recommended to locate these buffers physically
near the WD 1050 to minimize inductive ringing.
2. Timing is a function of the Servo Clock (SClK) frequency. The number of negative SClK transitions plus
400 nsec. SClK periods is specified. (Disregard "TYP" in this case).
3. Timing is a function of the Servo Clock (SClK) frequency. The number of negative SClK transitions plus
400 nsec. max. is specified. (Disregard the "TYP" in this case).
4. Timing is a function of the Master Clock (ClK) frequency. The number of ClK periods is specified. (Disregard
the "TYP" in this case).
5. WD is an open drain output and requires an external 1K ohm pull-up to Vcc. This pin is inverted relative
to the SMD interface cable. It is recommended that this output go to the 'D' input of a 74S74 flip-flop that
is clocked by the SClK buffer described in Note 1. The 74S74 a output may then connect to the interface
line driver. It is recommended that the 74S74 be located physically near the Wd1050.
6. All AC timing is measured at VOL = 0.8 V, VOH = 2.0V.
7. Certain occurrences of BCR can have variable pulse widths. Deactivation of BCR is dependent upon the
next occurance of INDX or SCTR for these instances.
8. Timing is a function of the Master Clock (ClK) frequency. The number of ClK periods, plus 100 nsec. min.
is specified.

Winchester Disk Controller Devices

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3-60

Winchester Disk Controller Devices

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WD1050 SMD Controller/Formatter Application Notes
INTRODUCTION

Prior to the introduction of 5% and 8 inch Winchester
disks drives in the late 1970's, minicomputers and
mainframes were the only systems that utilized rigid
disks. These drives were relatively expensive;
sometimes as high as $200 per megabyte. They
offered the minicomputer deSigner a fixed or
removable drive with capacities from 10 to 300
megabytes. Initially, there was no need for interface
standards. IBM Corporation was the predominant
leader in the marketplace, and anyone else who
decided to build drives were IBM compatible units.
But as competition increased, more and more companies began producing lower cost units with
increased capacity. Minicomputer companies were
being formed, offering complete systems that were
non-IBM compatible. The disk drive race was on.
In order to standardize a common interface and to
prevent product obsolescence, Control Data Corporation developed an intelligent interface called the
Storage Module Device or SMD. This interface
allowed a variety of drives to use the same hardware
signals, even though their capacities and physical
sizes differed. Variations of the SMD were also
introduced. Some of these are the CMD (Cartridge
Module Drive) and the MMD (Memory Module Drive).
The SMD interface began to gain acceptance in the
marketplace as competitive manufacturers offered
"SMD-compatible" drives as well. The SMD was well
on its way to becoming a defacto standard in the
industry. Its longevity has been proved by over 10
years worth of product based on this "intelligent"
interface.
With today's smaller diameter low cost drives, where
does SMD stand? Oddly enough, the higher capacity
5% and 8 inch Winchesters are reviving the SMD protocol. Because the SMD interface offers several
advantages over the ST506 type interface in the high
capacity arena (such as parallel seek instead of serial
step pulses), several manufacturers are planning to
offer the SMD on their traditional small system disk
drives. The SMD, however, is not a trivial interface
when it comes down to designing a controller.
A LOOK AT THE SMD

Figure 1 illustrates the electrical Signals of the SMD.
Two separate cables are used: one for control and

o
CJ'1
o

one for data. The control cable (commonly referred
to as the "A" cable) is responsible for all head movement, status reportings and issuing commands. The
data cable (or "B" cable) is used for reading and
writing NRZ data to a particular sector on the drive.
Note that all lines on both cables are differential
signals; they require a differential driver/receiver at
both ends.
Primary control over the "A" cable is based upon a
10 bit bus called the Tag Bus. These 10 lines send
particular information to the driver and initiate a command. Three Tag lines (Tag 1-3) are used to tell the
drive what the bus contains during the strobing of the
Tags. For example, Tag 1 tells the drive that the Tag
bus contains a cylinder number that the head
assemblies should be moved to for reading or writing.
Tag 2 tells the drive the Head/Volume to select, while
Tag 3 is used to initiate read or write commands and
to perform special recovery routines.
Drives are selected by separate UNIT SELECT lines
on the "A" cable, which have their own strobe line
called Unit Select Tag. Other signals on the "A" cable
serve status reporting type functions. SEEK ERROR
and ON CYLINDER are examples of status lines.
The "B" cable is used to transmit serial, NRZ data
to and from the drive. Associated with the R/W lines
are clocks: Write Clock for write recovery and Read
Clock for read recovery. Additional signals aid in
determining the status of each drive on the bus.
In a multiple drive configuration, the two cables are
connected as shown in Figure 2. The "A" cable is
daisy-chained; each drive is tied together in parallel
with termination resistors on the last drive. The "B"
cable is radial-connected; a separate cable from each
drive connects to the controller.
It is probably obvious by now that a great deal of control is necessary to perform even a simple Read or
Write operation on the SMD Bus. The drive controller
must perform simultaneous operations on both
cables, as well as monitoring status signals to determine successful execution of operation. A typical
SMD controller can consist of 150 SSIjMSllntegrated
Circuits and a local microprocessor or bit-slice to perform the necessary functions. SMD controller
designers of today can take advantage of a new LSI
chip that will reduce the number of I.C.'s to well under

40.

Winchester Disk Controller Devices

3-61

en
S
o

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c
.....

CONTROLLER

A CABLE

o
(J1
o

UNIT
UNIT
UNIT
UNIT
UNIT

en
c

S

TAG 1
TAG 2
TAG 3
BITO
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT6
BIT 7
BIT 8
BIT9
OPEN CABLE DETECTOR
INDEX

-~

---..

"

SELECT TAG
SELECT 20
SELECT 21
SELECT 22
SELECT 23

SECTOR
FAULT
SEEK ERROR
ON CYLINDER
UNIT READY
ADDRESS MARK FOUND
WRITE PROTECTED
PICK
HOLD
BUSY
NOT USED (SPARE)

DRIVE

- ""+"

22,52
23,53
24,54

26,56
27,57
1,31

~
~
~

2,32
3,33
4,34
5,35
6,36
7,37

fA

~

fA

~

ffi

h\
&

8,38
9,39
10,40
11,41
12,42
13,43
14,44
18,48
25,55
15,45
16,46

It\
fA

17,47
19,49

~ffi

20,50

~

&&

28,58
29
59

fA

~
~
~
~

fA
i2\

11\

&

:

..
..

•

}ONE1WISTED PAIA

21,51

30,60

NOT E: 60 Position
30 Twisted pair-straight flat cable
Maximum Length-100 ft. (30.48 meters)
Special signal, not a balanced transmission signal
2
Gated by unit selected
3
Not interpreted, is Daisy chained, no driver connection within the LMD
4
Not activated, is Daisy chained, always a logic zero output if unit is selected
5
Not generated, is Daisy chained, no driver connection within the LMD
Figure 1(A). Tag Bus I / 0 Interface ("A" Cable)

3-62

Winchester Disk Controller Devices

CONTROLLER

"B"CABLE

DRIVE

- , +

:E.
o-'"

820
7
6 19
18
2 14
1
3 16
15
5,17
4
1023
229
21
1224
11
1326
25

WRITE DATA
GROUND
WRITE CLOCK
GROUND
SERVO CLOCK
GROUND
READ DATA
GROUND
READ CLOCK
GROUND
SEEK END
UNIT SELECTED
GROUND
INDEX
GROUND
SECTOR
GROUND

o
(1'1
o

CJ)

s:
o

NOTES:
1. 26 conductor flat cable.
Maximum Length-50 ft. (15.24 meters)
2. No signals gated by "A" cable unit select
Figure 1 (B). "B" Cable Interface

NOTES:
1. Maximum individual A cable lenghts
2. Maximum individual 8 cable lenghts

100 feet (30.48 meters)
50 feet (15.24 meters)

DAISY CHAINED SYSTEM
SYSTEM
GROUND 1
A

CONTROLLER 1

B

B

B

B

NOTES:
1. Termination of "A" cable lines are required at controller and the last unit of the Daisy chain or each unit
in a radial configuration.
2. Termination of "8" cable receiver lines are required at the controller and are on the unit, receiver cards.
3. Maximum cumulative "A" cable length per controller = 100 feet (30.48 meters) maximum individual "8" cable
lenght
50 feet (15.24 meters).

=

Figure 2. Daisy Chained System

Winchester Disk Controller Devices

3-63

WD1050 SMD CONTROLLER CHIP

:ec

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s:

Western Digital Corporation offers an LSI controller
chip for the SMD protocol. This device, called the
WD1050, has been designed to interface an SMD rigid
disk drive to a 16-bit Host processor. A set of
macrocommands allows the Host to request a
specific operation such as seek, read, etc., in which
all Tag and control lines on the drive interface per·
form their appropriate signaling. By using this device,
the designer is free to concentrate on operating
system software intervention, rather than meeting
electrical requirements of the drive protocol. Figure
3 shows the Block Diagram of the WD1050. Data or
commands are entered in 16-bits through the Data
I/O Buffers. This information is stored in the Task File
and tells the device parameters about a specific com·
mand. This could be a cylinder address, a sector
number to search for, a particular drive that should
be selected, etc. After this information is loaded, a
command is issued. The Control Unit instructs the
various pins on the drive interface to generate their
proper signals. Upon completion of a command, the
WD1050 interrupts the Host and reports via the status

00015

register if any errors were encountered. The device
is then ready for the next command.
Figure 4 illustrates the Task File and its contents. The
Host processor generates the three address lines
shown, then performs a read or write operation to the
selected 16·bit register. All registers can be read or
written to with the exception of the Command/Status
Register. Since both of these registers share a com·
mon address location, a "write" will cause a com·
mand to execute, while a "read" will cause the status
to be fetched from the device. This memory mapped
architecture allows the Host to randomly access any
location in the Task File without disrupting or
reloading the data in other registers.
The Instruction Set of the WD1050 is shown in Figure
5. Return to Zero, and Seek Cylinder commands are
used for head movement, while the remaining
commands are responsible for reading or writing data.
Each Read/Write command also contains an
"Implied Seek" feature. This allows the Host pro·
cessor to issue a read or a write function even though
the heads are sitting over the wrong cylinder. The
WD1050 will perform an automatic seek operation

DATA
I/O
BUFFER

CONTROL
PORT

CPO-

UNIT SEL
PORT

USOUS3

RDS
AO-A2

RDH

CP9

RC
RD

cs
RE

WE
BCS
BCR
BRDY
BDRQ
INTRQ

WDH
~----------~~~WD

HOST!
BUFFER
CONTROL

WDS

CONTROL
UNIT
DRIVE
CONTROL
PORT

~

__________

SC
TAG 1TAG 3
INDEX
SECTOR
FAULT
SKER
ONCYL
URDY
WPROT
UBUSY
USEL
USTAG
J-~_ECC

FIGURE 3. WD1050 BLOCK DIAGRAM

3-64

Winchester Disk Controller Devices

before the actual read or write. Because of this, the
head movement commands (Return to Zero and Seek
Cylinders) are usually restricted for use in overlap
seeks. This is the ability to perform seek operations
on several drives simultaneously.
After a command has finished execution, the WD1050
will report to the Host through its Status Register
(shown in Figure 6) how successful a command
execution was. Many commands will not execute if
certain conditions are not met. For example, a FAULT
condition, shown by status bit 6, will prevent all commands except Fault Clear from executing.
Read / Write commands will not execute if the "On
Cylinder" bit is false, either. In summary, the Host
must examine the various bits to determine what
action to take next.
HOST SECTOR BUFFER
Because of the high data rates used on the SMD protocol (9.677 Mbits / sec.), even a fast micro- processor
will have trouble keeping up in a Programmed I/O
environment. For this reason, the WD1050 has been
designed to use a sector buffer.
Figure 7 shows a Host Interface to the device using
a low cost Static RAM and a binary counter. Since
the WD1050 will be transferring data directly to the
RAM, a transceiver will be needed to isolate the Host
from the RAM / WD1050 logic. This transceiver, as
shown in Figure 7, is disabled by Buffer Chip Select
(BCS). Whenever BCS is active, the WD1050 is reading
or writing to the RAM. During this condition, the Host
cannot read status or any other registers. When the
data transfer is over, the device disables BCS and
enables Buffer Data Request (BDRQ). This tells the
Host that the buffer is now available for use. If a read
command had been issued, the sector buffer would
have filled the data requested.
During this process, the WD1050 takes control over
Write Enable (WE) by making it an output. It places
its first data word on the bus and strobes WE.
This causes a write operation to the RAM and
increments the binary counte~at is tied to the
RAM's address lines. Another WE strobe then
occurs, increments the counter again, and the process continues until the sector is transferred. If a
single sector operation was requested, the WD1050's
use of the sector buffer is completed. However, multiple sectors may be transferred as an option within
the command. In this case, the Buffer Ready (BRDY)
input to the device is examined. If false, the WD1050
assumes there is more RAM available and transfers
the next sector of data. The BRDY signal is normally
generated by a "carry" or overflow out of the binary
counter. If BRDY has gone active but the device still

Winchester Disk Controller Devices

has more sectors to transfer, BDRQ will be made
active to allow the Host to unload the data in the
RAM, making room for the additional sectors. The
WD1050 will then resume its operation of finding a
sector and writing the data to the buffer. After all the
data has been transferred, the command will terminate. To complete the scheme, a signal called Buffer Counter Reset (BCR) is used to zero the counters
before the Host or device starts a transfer. A BCR
'Pulse is generated whenever BCS makes a transition.
By using this buffer scheme, the designer has the
ability with one command to transfer the maximum
number of sectors specified by the Sector Counter
in the SDH Register.
CONCLUSION
Using the WD1050 as the basis for an SMD controller
design, can reduce the complexity of the design effort
considerably. However, challenges still remain in
interfaCing the device to maximize the efficiency of
the interface. The buffer control signals, for example,
can be changed to accomodate a DMA controller for
higher throughput. ECC can be appended to the buffer for data correction purposes. A local microprocessor dedicated on the SMD controller board
could even be used to emulate existing SMD / Host
software routines.
Regardless of the application, the WD1050 signifies
a trend in the semiconductor industry to not only
replace logic in a discrete design, but to offer complete functions in large scale integration. This device
is certainly not the first to offer an LSI functional
building block, and will not be the last.
A2

A1

0
0

0
1
0
1
1

1
1

1

AD REGISTER SELECTED
0
0
0
0
1

Head Number/Sector Address
Sector Count/Length/Unit Address
16 Bit Cylinder Register
Command Register (Write Only)
Status Register (Read Only)

Figure 4_ WD10S0 Task File

3-65

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o

COMMAND

o
C11
o

Fault Clear

1

Return to Zero

1

Seek Cylinder

1

Read 10 Field

c-"

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c

COMMAND REGISTER BITS

LSB

=E

15

11

10

0

0

1

V

1

0

0

1

14

13

12

0

0

0

0

0

1

MSB
4

3

2

1

0

0

0

U

S

E

L

0

M

U

S

E

L

H

M

U

S

E

L

C

H

M

U

S

E

L
L

9

8

7

6

0

0

I

0

0

L

0

I

0

0

V

L

0

I

Z

C

1

R

L

0

I

Z

5

Read Sector

1

1

0

0

R

~

0

I

Z

C

H

M

U

S

E

Write Sector

1

1

0

1

R

L

0

I

Z

C

H

M

U

S

E

L

Format

1

1

1

0

R

P

0

I

Z

C

H

M

U

S

E

L

Verify

1

1

1

1

R

P

0

I

Z

C

H

M

U

S

E

L

FLAG SUMMARY
V = Verify
R
CRC Enable
L
Logical Sectoring
P = Programmable Sectors
o = On Cylinder
E
Priority Release/Early
L = Unit Deselect/Late

=

I = Interrupt Enable
Z = Volume/Head change
C
Cylinder Address
H
Head Selection
M
Marginal Data Recovery
U
Unit Sel/Servo Minus
S = Priority Sel/Servo Plus

=

Figure 5. WD1050 Instruction Set

BIT

NAME

DESCRIPTION

0

ID Field Not Found
(I DIN F)

Set if the sync character preceding the 10 Field or 10 Field contents read
from the disk do not match the respective Task File contents.

1

ID CRC Error (IDCE)

Set if the CRC calculation on the ID Field read from the disk is in error.

2

Data Field Not Found
(DFNF)

Set if the Data Field sync pattern following the 10 Field does not match
the sync character.

3

Data Field CRC Error (DFCE) Set if the CRC Calculation on the Data Field read from the disk is in error.

4

Not Used

5

Buffer Data Request (BDRQ) Reflects the Buffer Data Request output.

6

Fault (FLT)

Reflects the status of the Fault (FLT) input.

7

Buffer Chip Select (BCS)

This bit is an inverted copy of the Buffer Chip Select (BCS) output.

8
9

Seek Error (SKER)

Reflects the status of the Seek Error (SKER) input.

On Cylinder (OCYL)

Reflects the status of the On Cylinder (OCYL) input.

10

Unit Ready (URDY)

Reflects the status of the Unit Ready (URDY) input.

11

Write Protect (WPRT)

Reflects the status of the Write Protect (WPRT).

12

Unit Selected (USEL)

Reflects the status of the Unit Selected (USEL) input.

13

Unit Busy (UBSy)

Reflects the status of the Unit Busy (UBSy) input.

14

CIP

Set when a command is in progress.

15

Buffer Chip Select
(BCS)

This bit is an inverted copy of the Buffer Chip Select (BCS)
This bit also appears in STATUS Bit 7.

This bit is not used; it is forced to a zero.

output.

Figure 6. WD1050 Status Register

3-66

Winchester Disk Control/er Devices

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~

OATA BUS (16)

o
01
o

00- 0 15

CJ)

I I

"'--roo~

i)--

RAMSEL

-

S

c

RAM
BUFFER

/11111
BINARY
COUNTER

WD1050

I

BCR
BROY

HOST
INTERFACE

11"""')
BCS

AD
WR

,....

RE

,....
WE

OATA REQ

BORQ

CS

CHP SEL

AO-A2

AOOR

Figure 7. WD10S0 Host Interface

Winchester Disk Controller Devices

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Winchester Disk Controller Devices

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WD1100 Series Winchester Controller Chips
DESCRIPTION

FEATURES

The WD1100 Chip series provides a low cost alternative for developing a Winchester Controller. These
devices have been designed to read and convert an
MFM data stream into 8-bit parallel bytes. During a
write operation, parallel data is converted back into
MFM to be written on the disk. Address Marks are
generated and detected while CRC bytes can be
appended and checked on the data stream. The
WD1100 is fabricated in N-channel silicon gate
technology and is available in a 20-pin Dual-In-Line
package.

• SA1000/ST506 COMPATIBLE
• SINGLE 5V SUPPLY
• TRI-STATE DATA LINES
• 5 MBITS/SEC TRANSFER RATE
• SIMPLIFIED INTERCONNECT

•
•
•
•
•
•
•
•
•

WD1100-01 SER/PARALLEL CONVERTER
WD1100-02 MFM GENERATOR
WD1100-12 IMPROVED MFM GENERATOR
WD1100-03 AM DETECTOR
WD1100-04 CRC GENERATOR/CHECKER
WD1100-05 PAR/SERIAL CONVERTER
WD1100-06 ECC/CRC LOGIC
WD1100-07 HOST INTERFACE LOGIC
WD1100-09 DATA SEPARATION SUPPORT LOGIC

ClK

Vce

NC

EN

NRl

Vee

SKPEN

AO

APPLICATIONS
Winchester Controllers for:
• SHUGART ASSOCIATES
• SEAGATE TECHNOLOGY
• QUANTUM CORP.
• TANDON MAGNETICS
• MINISCRIBE
• RMS
• CMI ... AND OTHERS

NRZ

Vee
AO

SKPEN

BClR

NRl

WClK

Al

WCLK

Al

TEST

Sf

WClK

MR

WCCK

MR

000

DOUT

RWC

MFM

Cs

001

BOONE

002

SHFClK

003

007

004

006

NC

lATE

VSS

005

Vss

NOM

INTRa

5i'i'QC[i(

ORO

INTClK

EARLY

WD11 00-01

WD11 00-02

SERIAUPARALLEL
CONVERTOR

MFM GENERATOR

RWC

CS

DiN

CP

RClK

NC

ClKIN

AMDET

INTRQ

NC

AMDET

ORO

NC

EARLY

ffiTi

2XOR

LATE

ENDET

Vss

NOM

VSS

INTCLK

RST

DOUT

MFM

OROCLK

Vee

RClK

WD1100-12
IMPROVED MFM
GENERATOR

OOUT
NC
DClK
TEST 2

WD1100-03
AM DETECTOR

Vee

DO

Vee

RIW

VCC

NC

01

EN

RCP

WBS

SHFClK

NC

02

NC

WCP

RBS

RESET

cs

NC

NC

D3

fEST

RDAT

DCSS

CSAEN

WAEN

NC

CRCOK

D4

BOONE

WDAT

EDOUT

AMDET

MODE

CWE

TlMClK

D5

DOUT

DOUT

TlMClK

RBS

WClK

D6

SHFClK

CRCOK

D7

iJi

DiN
DOcK

DOCE
CRCll
NC

Vss

SKPClK
DOUT

WD1100-04
CRC
GEN ERATO RICH ECKER

SEl

R56

Vee
WClK

WR6

ECCll

FBD

RClK

NC

CSE

INDEX

CSAC

BS

WR3

WAIT

RWCP

Vss

LlNDEX

SHFClK

WClK

ECCEN

Vss

DClK

VSS

AMOiJ't

WD11 00-05

WD11 00-06

WD11 00-07

PARALLEUSERIAL
CONVERTER

ECC/CRC
LOGIC

HOST INTERFACE

Winchester Disk Controller Devices

LOGIC

3-69

3-70

Winchester Disk Controller Devices

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....
o

WD110o-01 Serial/Parallel Converter

o
o•

The WD11()()'()1is implemented in NMOS silicon gate
technology and is available in a 20 pin plastiC or
ceramic dual-in-line package.

DESCRIPTION
The WD1100-01 Serial/Parallel Converter allows the
user to convert NRZ (non-return to zero) data from a
Winchester disk drive into a-bit parallel form. Additional inputs are provided to Signal the start of the
parallel process, as well as Byte Strobes to signify
the end of the conversion. The device contains two
sets of 8-bit registers; one register may be read (in
parallel), while data is being shifted into tile other
register. This double-buffering allows the Host to read
data from the disk drive at one-eighth the actual data
rate.

FEATURES

+ 5V

•

SINGLE

SUPPLY

•

DOUBLE BUFFERING

•

BYTE STROBE OUTPUTS

•

5MBITS/SEC SHIFT RATE

•

SERIAL IN/SERIAL-PARALLEL OUT

•

20 PIN DIP PACKAGE

Sf ~-----.
+5V
S
8

a'----ob

BOONE

Bit
Counter

EN

cp

ClK

vcc

NC

NRZ

TEST

ST

OOUT

B Bit
Shift Register

elK

BClR

OOUT

000
15

BOONE

002

14

SHFcLi<

003

13

007

004

12

006

11

005

001

vSS

a

NRZ

EN

10

cp

B Bit Register

000 001 002 003 004 005 006 007

Figure 1.
WD1100-01 Pin Connections

Winchester Disk Controller Devices

Figure 2.
WD1100-01 Block Diagram

3-71

....

:E
o

PIN
NUMBER

...L
...L

o
oI
o
...L

SYMBOL

NAME

ClK

CLOCK

NRZ data is entered into the 8-bit shift register on the
low-to-high transition of clock.

2
3

NC
BClR

NO CONNECTION
BYTE CLEAR

4

No connection. This pin is to be left open by the user.
When this line is at a logic 0, the BOONE (Pin 15) line
is held reset.
This pin must be left open by the user.
8 bit parallel data outputs.

5·9
11·13
10
14

TEST
000-007

TEST INPUT
OATAO-OATA 7

Vss
SHFClK

GROUND
SHIFT CLOCK

15

BOONE

BYTE DONE

16

OOUT

DATA OUT

17

ST

START

18

NRZ

NRZ DATA

19

EN

ENABLE

20

Vcc

Vcc

DEVICE DESCRIPTION
Prior to shifting data through the device, the
W01100-01 must be synchronized to the data stream.
The ST line (Pin 17 high) is used to hold the internal
bit counter in a cleared state until valid data (NRZ)
and clocks (ClK) are entered. The ST line is a synchronous input and therefore requires one full cycle
of the ClK line (Pin 1) to occur in order to accept a ST
condition. After this happens, the device is ready to
perform serial to parallel conversions.
Data is entered on the NRZ line and clocked into the
8-bit shift register on the low-te-high transition of ClK.
The ST line must be set low during the low time of
ClK. Data is accepted on low-te-high transition of the
clock while the high-to-Iow transition of ClK
increments the bit counter. After 8 data bits have been
entered the final high-to-Iow transition of ClK sets
an internal latch tied to the BOONE line (Pin 15). At
the same time, the contents of the shift register are
parallel loaded into an 8 bit register making the
parallel data available on the 000-007 outputs.
BOONE will remain in a latched state until the BClR
is set to a logic 0, clearing off the BOONE signal.
BClR is a level triggered input and must be set
back to a logic 1 before the next 8 bits are shifted
through the register. BClR has no effect on the serial
shifting process. When the next 8 bits are received,

3-72

FUNCTION

1

Ground.
Inverted copy of CLOCK (pin 1) which is active when EN
(pin 19) is at a logic 1.
This signal is forced to a logic 1 signifying 8 bits of data
have been assembled. BOONE remains in a logic 1 state
until reset by a logic 0 on the BClR (pin 3) line.
Serial Data Output from the 8th stage of the internal shift
register. OOUT is in a high impedance state whenever
EN (pin 19) is at a logic O.
This line enables the byte counter and is used for synchronization. It must be held to a logic 1 prior to first
data bit on the NRZ (pin 18) line.
NRZ serial data is entered on this pin and clocked by
the low to high transition of ClK (pin 1).
When this signal is at a logic 0, OOUT, SHFClK,
and BOONE outputs are in a high impedance state.
+ 5V ± 10% power supply input.

BOONE will again be set and the operation continues.
When interfacing to a microprocessor, BOONE is
used to indicate a parallel byte is ready to be read.
As the processor reads the data out of the 000-007
lines, the BClR line should be strobed to clear of
BOONE in anticipation of the next assembled byte.
An address decode Signal generated at the host may
be used for this purpose. During a power-up condition, the state of BOONE is indeterminant. It is recommended that BClR be strobed low after power-up
to insure that BOONE is cleared.
The serial output line from the last stage of the shift
register is available on the OOUT pin. An inverted copy
of ClK is available on the SHFClK pin.
Both
OOUT (Pin 16) and SHFClK (Pin 14) can be· used
to drive another shift register external ,to the device.
The three Signals BOONE, OOUT, and SHFClK can
be placed in a high impedance state by setting EN (Pin
19) to a logic O. Likewise, EN must be at a logic 1 in
order for these Signals to be active.
The TEST pin is internally OR'ed with the ST line to
inhibit the bit counter. It is recommended that TEST
be left open by the user. An internal pull-up resistor is
tied to this pin to satisfy the appropriate logic level
required internally for proper device operation.

Winchester Disk Controller Devices

SPECIFICATIONS

:E

ABSOLUTE MAXIMUM RATINGS
Ambient Temperature
under Bias ......... 0oC (3~F) to 50°C (12~F)
Voltage on any pin
with respect to Vss ....p • • • • • • - 0.2V to + 7.0V
Power Dissipation ...................... 1 Watt
STORAGE TEMPERATURE
PLASTIC ... - 55°C (- 67°F) to + 125°C (257°F)
CERAMIC .. - 55°C (- 6~F) to + 150°C (30~F)
DC Electrical Characteristics TA
SYMBOL
Vil
V IH
Vo
VOH
Vee
lee
IIH
III

SYMBOL
fel
t lS
t HS
tos
tve
t RS
tew
tse
tes
tso
t FO
tOH
teo
tOF

Maximum ratings Indicate operation where
permanent device damage may occur. Continuous operations at these limits is not
intended and should be limited to those conditions specified in the DC electrical
characteristics.

= OOC (3~F) to 50°C (12~F); Vce = +

PARAMETER
Input low Voltage
Input High Voltage
Output low Voltage
Output High Voltage
Supply Voltage
Supply Current
Input High
Input low

AC Electrical Characteristics TA

NOTE:

MIN

TYP

-0.2
2.0

5V ± 10%, Vss

MAX

UNIT

0.8

V
V
V
V
V
rnA
llA
llA

0.4
2.4
4.5

5.0

5.5
125
<10
<10

= OOC (32°F) to 50°C (122°F), Vee = 5V

PARAMETER
ClK FREQUENCY
~ClK to ST
tClK to ST
Data set-up to t ClK
BOONE valid from ~ ClK
BOONE reset from BClR
BClR Pulse Width
t ClK to ~ SHFClK
~ ClK to t SH FClK
Data delay from t SHFClK
Enable to DOUT ACTIVE
Data Hold w.r.t. t ClK
t ClK to DOUT ACTIVE
Enable to DOUT disable

NOTE: 1. Typical Values are for TA

Winchester Disk Controller Devices

UNITS

0
0
0
15

5.25

65

140
135

MHZ
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec

TYP

50

90
90
55

90
45

= 25°C (77°F) and Vee

145

90

CONDITION

10l
10H

= 3.2mA
= 20011A

All Outputs Open
VIN
.4 to Vee
VIN
.4 to Vee

=
=

± 10%, Vss

MAX

MIN

= OV

= OV
CONDITION

ST = 1 (min 200nsec)
ST = 1 (min 200nsec)
EN
EN
EN
EN
EN
EN

=1
=1
=1
=1
=1
=1

= +5V± 10%

3-73

c-'"
-'"

o
o

o•

-'"

:E
C
.....
.....
0
0
0

ClK
ST

•

.....

NRZ
DOX
BOONE
BClR

~~---p-ow-e-r-.o-n--D-AT-A-/--b~-e--n-.l----~~

b~e

, :.-IRS
'

-,

------iU

~!:~w

SHFClK

',:

Isc

,-...J I .......

1 or n

u

Ic~:~:
I

:----

t CO~!I

': __
150

DOUT
-.,1

EN

: lFO

I~

t OF

:

-.,

~r!--------------------~i~

:-4---

______________

FIGURE 3. WD1100-01 FUNCTIONAL TIMING

3-74

Winchester Disk Controller Devices

WESTERN

c

o

R

P

o

DIGITAL

R

A

o

T

N

~.

c
....

....o

WD1100-03 AM Detector

o
o•
w

DESCRIPTION
The WD11QO-03 Address Mark Detector provides an
efficient means of detecting Address Mark Fields in
an MFM (NRZ) data stream. MFM (NRZ) clocks and
data are fed to the device along with a window clock
generated by an external data separator. The
WD1100-03 searches the data stream for a DATA =
A1, ClK = OA pattern and produces an AM DET
signal when the pattern has been found. NRZ data
is an output from the device, which can be used to
drive a serial/parallel converter. An uncommitted latch
is also provided for by the data separator circuitry,
if required.

CP

RSf

RcLK

20

Vee

BiN

19

RST

RClK

18

ClK IN

17

NC

DOUT

16

AMDET

NC

15

AMDET

NC

1"

QoUr

FEATURES
•
•
•
•
•

+5V];]

:

DIN

SINGLE +5V SUPPLY
5 MBITS/SEC DATA RATE
DECODES A1 16 OA 16
SYNCHRONOUS CLOCK/DATA OUTPUTS
20 PIN DIP PACKAGE

NC

ENDET

12

DClK

000'f

DOUT

8 err
SHIFT REG

RClK

C

'fEffi
DClK
ENDET

13

..

a

D

CP

fEsi"1
Vss

The WD1100-03 Address Mark Detector is fabricated
in NMOS silicon gate technology and is available in
a 20 pin dual-in-Iine package.

R

DETECT A1
DETECTOA

AMDET
AMDET

10

11

Tffi2.

TEsT2
ClK IN

D

RClK

C

Figure 1.
WD1100-o3 Pin Connections

Winchester Disk Controller Devices

8 err
SHIFT REG

a

Figure 2.
WD1100-03 Block Diagram

3-75

:ec

.....
.....

PIN
NUMBER

1

FUNCTION

Complimentary clock inputs used to clock DIN and ClK IN
into the AM detector.

DIN

DATA INPUT

MFM data pulses from the external Data Separator are connected on this line.

4

ClKIN

CLOCK INPUT

MFM clock pulses from the external Data Separator are connected on this line.

5

DOUT

DATA OUTPUT

Data Output from the internal Data Shift register, synchronized
with DClK.

o
o

3
2

w

NAME

READ CLOCK
READ CLOCK

·0

•

SYMBOL

RClK
RClK

6,7,13,17

-

NC

No Connection

To be left open by the user.

8
11

TEST 1
TEST 2

TEST 1
TEST 2

To be left open by the user.

9

ENDET

ENABLE
DETECTION

10
12

Vss
DClK

Vss
DATA CLOCK

A logic 1 on this line enables the detection logic to search
or a data A 116 and clock.
Ground ..

14

QOUT

LATCH OUTPUT

Signal output from the uncommitted latch.

15

AMDET

16

AMDET

ADDRESS MARK
DETECT
ADDRESS MARK
DETECT

Complimentary Address Mark Detector output. These Signals will
go active when a Data = A116 Clock
OA 16 pattern is detected
in the data stream.

18

CP

CLOCK PULSE

A low-to-high transition on this line will cause the QOUT (Pin 14)
to be latched at a logic O.

19

RST

RESET

A logic 0 on this line will cause the QOUT (Pin 14) signal to be
set at a logic 1.

20

Vcc

Vcc

+ 5V ±

Clock output that is synchronized with DATA OUT (Pin 5).

=

10% power supply input.

DEVICE DESCRIPTION

Prior to shifting data through the device, the internal
logic must be initialized. While the ENDET (Pin 9) line
is at a logic 0, shifting of data will be inhibited and
AMDET, AMDET, ClK, and DATA OUT will remain
inactive.
When ENDET is at a logic 1, shifting is enabled. NRZ
data is entered on the DIN line (Pin 2) and shifted
on the high-to-Iow transition of RClK (Pin 1). NRZ
clocks are entered on the ClK IN line, and shifted
on the high-to-Iow transition of RClK (Pin 3). The
DOUT line (Pin 5) is tied to the last stage of the
internal Data Shift register and will reflect information clocked into the DIN line delayed by 8 bits.
While each bit is being shifted, a 16 bit comparator is
continuously checking the parallel contents of the
shift registers for the DATA = A1 16 , ClK = OA 16 pattern. When this pattern is detected, AMDET will be
set to a logic 0 and AMDET will be set to a logic 1.
AMDET and AMDET will remain latched until the device is reinitialized by forcing ENDET to a logic O.

3-76

When an AM is detected, DClK will begin to toggle.
Data present on the DOUT line may then be clocked
into an external serial/parallel converter. DClK will
remain inactive when ENDET is held at a logic O.
An uncommitted edge-triggered flip / flop has been
provided to facilitate the detection of high frequency
by the data separator, but may be used for any purpose. The low-to-high transition of CP (Pin 18) will set
the QOUT (Pin 14) to a logic o. QOUT may be reset
back to a logic 1 by a low level on the RST line
(Pin 19).
TEST 1 and TEST 2 are output lines. TEST 1 is an
active low pulse when an A 116 is detected, and
TEST 2 is active low pulse when a OA16 is detected. These signals are used for test points and
therefore should be left open by the user if not
required.

Winchester Disk Controller Devices

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under
bias ............ 0oC (32°F) to 50°C (122°F)
Voltage on any pin with
respect to Vss .................. -0.2 to + 7.0V
Power Dissipation ...................... 1 Watt

DC Electrical Characteristics TA
SYMBOL
VIL
VIH
VOL
VOH
Vcc
Icc
IIH
IlL

SYMBOL
f RC
tST
tHT
tRD
tEM
tRA
tRM
t RO
tEA
t RO
tRW
tcw
tco

NOTE:

Maximum ratings indicate operation where
permanent device damage may occur. iContinuous operations at these limits is not
intended and should be limited to those conditions specified in the DC electrical
characteristics.

= OoC (32°F) to 50°C (12~F), Vcc = + 5V

PARAMETER

MIN

Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Supply Voltage
Supply Current
Current Input High
Current Input Low

AC Electrical Characteristics TA

STORAGE TEMPERATURE
PLASTIC .................... -55°C to + 125°C
CERAMiC ................... -55°C to + 150°C

TYP

-0.2
2.0

5.0

= OOC (32°F) to 50°C (122°F), Vcc

PARAMETER

MIN

RCLK FREQUENCY
Data, CLKIN, RCLK Setup Time
Data, ClKIN, RCLK Hold Time
~ RCLK to t DCLK
ENDET set to AMDET, DOUT,
DCLK
~ RCLK to t AMDET
~ RCLK to ~ AMDET
~ RCLK to DOUT
t ENDET to AMDET, DOUT, DCLK
~ RST to t QOUT
Pulse width of RST
CP Pulse width
t CP to ~ QOUT

NOTE: 1. Typical Values are for TA

Winchester Disk Controller Devices

MAX

UNIT

0.7

V
V
V
V
V
rnA
uA
uA

0.4
2.4
4.5

TYP

± 10%, Vss

5.5
125
10
10

= + 5V

UNIT

5.25

MHz
nsec
nsec
nsec
nsec

140
100
115
125
135
190
110
50
90
120

CONDITION

10L
10H

= 3.2 rnA
= -200 A

All Outputs Open
VIN
.4 to Vcc
Vw
.4 to Vcc

=
=

± 10%, Vss = OV

MAX

40
40

= OV

CONDITION

nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec

= 25°C and Vcc = +5V.

3-77

:E

c
.....
.....

o
o
o•

CAl

~---------------------------------4S~

, ,
,

--,

________________

I

:-tEM

--tRD

,
,,,
,

,
:LiJ
"
I'

~:I

Ir.--------~-----

,

I

: tRM

:

I

:

~~~'--------------------------'I:
I'~:~----~----L-'--..J
:

I --

:

tEA

:

::tRA:'
~iL--------r---~S~
: r----i -'I~
r-----7----4S~:
I

i

-----------------------------.tR~£_~~I~~~startofA'

!~

, ,

Figure 3.'WD1100·03 Functional Timing

3-78

Winchester Disk Controller Devices

WESTERN

c

o

R

.P

o

R

DIGITAL
A

T

o

N

WD1100-04 CRC Generator/Checker
DESCRIPTION

FEATURES

The WD110004 CRC Generator / Checker is designed
to generate a Cyclic Redundancy Checkword from a
serial data stream, and to check a data stream
against a known CRC word. Complimentary latched
"CRCOK" outputs are provided to indicate CRC errors
in check mode. Additional logic has been included
to shift the CRC checkword out of the device by
signals generated on other WD1100 family devices.

• GENERATES / CHECKS CRC
• SINGLE + 5V SUPPLY
• LATCH ED ERROR OUTPUTS
16
• X
+ X12 + X 5 1(CCITT-16)
• AUTOMATIC RESET
• 20 PIN DIP PACKAGE

The WD1100-04 is fabricated in NMOS silicon gate
technology and is available in a 20 pin dual-in-line
package.

Figure 1.
WD1100·04 Pin Connections

Winchester Disk Controller Devices

Figure 2.
WD1100·04 Block Diagram

3-79

:ec

PIN
NUMBER

SYMBOL

NAME

FUNCTION

......
......

1

DIN

DATA INPUT

Active low serial input data stream is used to
generate/check the 2 byte CRC word.

~

2

DOCK

DATA OR CRC
WORD CLOCK

After a byte of data has been transfel'jed in, this
input signal is used to latch the state of DOCE in
an internal D flop with a high to low transition.

3

SHFCLK

SHIFT CLOCK

The falling edge shifts data bits into the CRC
generator/checker. It also transfers the CRC check
word to DOUT in the write mode (DDCE = LOW).
The rising edge also activates the CRCOK lines in
the read mode when no error is found.

o
oI
o

I

4,5

N.C.

NO CONNECTION

6

CWE

CHECK WORD
ENABLE

This active low output indicates that the CRC
line.
checkword is being output on the DOUT
When CWE is high, data is being output on DOUT.

7

DOCE

DATA OR CRC
ENABLE

Initially, this input line is held high to direct input
data (pin 1) to the output data (pin 11). After the next
to the last BYTE is transmitted but before the last
BYTE occurs DOCE must be low to direct the 2 CRC
check bytes to DOUT (pin 11).
DOCE must be maintained low for a minimum of
2 byte times. DOCE is used only in the write mode.

3-80

a

CRCIZ

CYCLIC
REDUNDANCY
CHECK INITIALIZE

9

N.C.

NO CONNECTION

10

Vss

GROUND

GROUND.

11

DOUT

DATA OUTPUT

In the write mode, this line outputs the unmodified
data stream along with the 2 byte CRC word
appended to the end of the stream.

12

SKPCLK

SKIP CLOCK

The first hieh-to-IOW transition on DIN c!fin 1) resets SKPC K low and enables the CR to either
generate or check the CRC word.

13

CRCOK

CYCLIC
REDUNDANCY
CHECK OKAY

In the read mode, after the 2 byte CRC word is
entered on DIN and no error has been detected,
this line is set high to indicate no errors have
occurred. This line will then remain high as long as
DIN is maintained high.

14

WCLK

WRITE CLOCK

This input clock is divided by 16 to produce TIMCLK
(pin 15) and has no effect on the rest of the internal
circuitry.

15

TIMCLK

TIMING CLOCK

See WCLK (pin 14).

16

CRCOK

CYCLIC
REDUNDANCY
CHECK OKAY

Complementary output version of CRCOK (pin 13).

17-19

N.C.

NO CONNECTION

20

Vcc

Power Supply

When this line is at a logic 0, the SKPCLK output
line is held high and the CRC generator is held
preset to hex "FFFF."

+5v ± 10% power supply.

Winchester Disk Controller Devices

DEVICE DESCRIPTION
Prior to shifting data through the device (either in the
read or write modes) the CRC generator/checker is
initialized by strobing the CRCll (pin 8) low. This
forces the SKPCLK (pin 12) line to the high state. The
first low going transition on DIN (pin 1), namely the
most significant bit of an address mark, resets the
SKPCLK line. The WD1100-04 has now been properly
initialized and is ready to generate/check the CRC
bytes. The CRCOK and CRCOK lines should be set
to their inactive states.
In the write mode, initially the DOCE (pin 7) is held
high and pseudo DOCK is produced by supplying a
string of zeros before the address mark. This ensures
the proper state of the internal D flip flop to gate input
data to the output line DOUT (pin -11). As shown in
the block diagram the CWE (pin 6) will be set high.
Sometime between the next to the last and the last
DOCK that indicates the end of the data stream,
DOCE (pin 7) is lowered to ensure the smooth transition of the 2 byte CRC checkword to the output line
DOUT (pin 11).
DOCE must be maintained low for a minimum of 2
byte times. After the CRC word is generated, DOUT
will produce a string of zeroes (Le., held high). This
portion of the circuitry is dormant in the read mode.
After proper initialization, input data is entered on DIN
(pin 1) along with the 2 byte CRC word for the read

mode of operation. At the end of the data stream, if
no errors were detected the CRCOK (pin 13) is set
high. Accordingly the complimentary output (pin 16)
is set low. These output states will be maintained as
long as DIN is held high and CRCll (pin 8) is not
strobed. If the CRCOK lines do not become active,
an error has been detected and a retry is in order. If
successive re-tries fail, an error flag may be set to
determine a further course of action as desired by
the user.
WCLK is divided by 16 to produce TIMCLK which may
be used as a buffered step clock for SA1000 compatible drives.
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under
Bias ............ 0oC (32°F) to 50°C (122°F)
Voltage on any pin
with respect to Vss ............. -0.2V to + 7.0V
Power Dissipation ...................... 1 Watt
STORAGE TEMPERATURE
PLASTIC ..... -55°C (-67°F) to + 125°C (257°F)
CERAMIC .... -55°C (-67°F) to + 150°C (302°F)
NOTE:

Maximum ratings indicate operation where
permanent device damage may occur. Continuous operations at these limits is not
intended and should be limited to those conditions specified in the DC electrical
characteristics.

DC Electrical Characteristics TA = OoC (32°F) to 50°C (122°F); Vce = +5V ± 10%, Vss = OV
SYMBOL
VIL
VIH
VOL
VOH
Vee
Icc
IIH
IlL

PARAMETER
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Supply Voltage
Supply Current
Current Input High
Current Input Low

MIN

TYP1

-0.2
2.0

MAX

UNIT

0.8

V
V
V
V
V
rnA
uA
uA

0.4
2.4
4.5

5.0

5.5
125
<10
<10

CONDITIONS

10L = 3.2 rnA
IOH = -200J.LA
All Outputs Open
VIN = .4 to Vee
VIN = .4 to Vee

AC Electrical Characteristics TA = OoC (32°F) to 50°C (122°F); Vee = 5V ± 10%, Vss = OV
SYMBOL
twr
tzs
tZK
t BS
tBH
too

PARAMETER

t WCLK to ! TIMCLK
CRCll ! to t SKPCLK
CRCll pulse width
DOCE set up time w.r.t.
! DOCK
DOCE hold time w.r.t.
! DOCK
DIN to DOUT delay

Winchester Disk Controller Devices

MIN_

TYP1

MAX.

UNITS

140
120
90
20

nsec
nsee
nsec
nsec

40

nsec
105

nsee

CONDITION

CWE set high

3-81

:ec
-.I.
-.I.

o
oI

0..a:::..

=E

c-"
-"

o
o

o•

~

SYMBOL

PARAMETER

DIN to ~ SKPCLK
DIN P.W. to reset SKPCLK
~ DOCK to t CWE
SHFCLK to DOUT
~DOCK to tCWE
SHFCLK frequency
t SHFCLK to t CRCOK
tSHFCLK to ~ CRCOK
~ DOCK to ~ DIN

MIN.

TYP1

MAX.

120

~

tOK
tow
tiC
tso
tac
fsc
tSR
tsc
tiN

CONDITION

UNITS

nsec
nsec
nsec
nsec
nsec
MHz
nsec
nsec
nsec

50
120
150
120
5.25
85
90
90
+5.0V

NOTE: 1. Typical Values are for TA
- : fsc:___ I

SHFCLK

i

-; :....!oo -: !___t IN

~r------------------------~~

DaCE

:·---------leH--------

n = last data byte

les--::

-------'--------------------------1,IRemains low-';:"2 !;te times
, ,
-I

lI~tlC

, il

tSD _ ' ' - : - , - - - - - - - -

- - - - - - - --------------:-.-CRC bytes

CRCOK

----------------------------------------~,

Isc_: , -

ii

CRCaK

L

__________

~ ",d

mod,

I

Figure 3.
WD1100-04 Write Mode

Figure 4.
WD1100-04 Initialize

3-82

Winchester Disk Controller Devices

WESTERN

DIGITAL

c

A

o

p

R

o

R

o

T

N

=E

c
......
......

WD110o-05 Parallel/Serial Converter

o
oI

o
DESCRIPTION

FEATURES

The WD1100-05 Parallel/Serial Converter allows the
user to convert a byte of data to a serial stream when
writing to a disk or any serial device. Parallel data is
entered via the DO-D7 lines on the rising edge of
DCLK. A synchronous BYTE counter is used to signify that a-bits of data have been shifted out and that
the a-bit latch is ready to be reloaded. The double
buffering of the data permits another byte to be
loaded while the previous byte is in the process of
being shifted.

•
•
•
•
•
•
•

01

SINGLE + 5V SUPPLY
DOUBLE BUFFERING
BYTE STROBE OUTPUTS
5 M BITS/SEC SHIFT RATE
TRI-STATE OUTPUT CONTROL
PARALLEL IN/SERIAL OUT
20 PIN DIP PACKAGE

"cc
EN

DO
01

The WD11()(}()5 is implemented in NMOS silicon gate
technology and is available in a 20-pin plastic or
ceramic dual-in-line package.

02

NC

03

TEST

04

BOONE

05

OOUT

06

SHFCLK

07

CD

SHFCLK

WCLK

"ss

OCLK

Figure 1.
WD1100-0S Pin Connections

00-07

,/8

/8

Q

0

/8

I

8BfT
LATCH

Q~~j:>--. OOUT

0

I

C

8 BfT SHIFT
REG
C

I
+5V
Lo

+Lo
BYTE
COUNTER

C

a

C

1
R

a
-rn~

LO

'i

1---+

SHFCLK

P--+-

SHFCLK

p--.

BOONE

Y
-~

iJ5

Figure 2.
WD1100-0S Block Diagram

Winchester Disk Controller Devices

.'3-83

c
.....
.....

PIN NUMBER
1-8
9

01

10
11

Vss
DCLK

GROUND
DATA CLOCK

12

WCLK

WRITE CLOCK

~
o
oI
o

13

SYMBOL
00-07
SHFCLK

NAME
DATA O-DATA 7
SHIFT CLOCK

-

LD

LOAD

14

SHFCLK

SHIFT CLOCK

15
16

DOUT
BOONE

DATA OUT
BYTE DONE

17
18
19

TEST
NC
EN

TEST INPUT
No Connection
ENABLE

20

Vcc

Vcc

FUNCTION
8-bit parallel data inputs (bit 7 = MSB).
Inverted copy of WCLK (pin 12) which is active when
ENABLE (pin 19) is at a logic O.
GROUND.
Active low input signal resets the BOONE (pin 16) latch.
The low-to-high (trailing edge) clocks the input data into
the internal 8-bit latch.
The high-to-Iow (~) edge of this clock signal is used to
shift the data out serially. The low-to-high (t) edge is used
to update the internal byte counter (module 8).
This active low signal indicates that the Byte Counter
is being preset to 1. Normally left open by the user.
Delayed copy of WCLK (pin 12) which is active when
EN (pin 19) is at a logic O.
Serial data output enabled by EN (pin 19).
This output signal is forced to a logic 1 whenever 8
bits of data have been shifted out. BOONE remains in
this state unless reset by the loading of another byte of
data.
This pin must be left open by the user.
This active low Signal enables DOUT, SHFCLK,
SHFCLK, and BOONE outputs. When high, these output
signals are in a high impedance state.
+ 5 ± 10% power supply input.

DEVICE DESCRIPTION

transmitted is the same as the previous byte.

Prior to loading the WD1100-05, it is recommended
that OOH (or FF) be loaded into the inru!t buffers to
ensure that DOUT is at a fixed level. EN (pin 19) is
set to a logic 0 to enable the device outputs.

Four signals, BOONE, DOUT, SHFCLK, and SHFCLK,
can be placed in a high impedance..§1ate by setting
EN (pin 19) to a logic 1. Likewise, EN must be at a
logiC 0 in order for these signals to drive any external device.

Data is entered on the 00-07 input lines and is
strobed into the data latches on the rising edge of
DCLK (pin 11). DCLK also resets BOONE (pin 16).
The first BOONE that comes up simply means that
the WD110005 is ready to accept another byte of data
and that the previous byte entered is in the process
of being shifted out. If the BOONE is serviced prior
to every 8th WRITE CLOCK pulse the output data will
represent a contiguous block of the bytes entered.
Due to the asynchronous nature of the WD1100-05,
the input data will be available in serial form at the
output anywhere from 8 to 16 write clock cycles later.
Data is shifted out on the high-to-Iow (~) transition of
the WCLK (pin 12). The low-to-high (t) transition of
WCLK increments a byte counter which in turn sets
the BOON E signal high after 8 bits of data have been
shifted out. The low-to-high transition of BOONE also
causes the loading of the data buffer into the shift
register. The data buffer is now ready to be reloaded
with the next byte.
The loading of the next byte automatically clears the
BOONE Signal. The entire process as outlined above
is repeated. BOONE always needs to .be serviced
within 8 WCLK cycles unless the next byte to be

3-84

The TEST pin is internIDlY OR'ed with the counter
output to produce the LD (pin 13) signal. This is
used to inhibit the bit counter by external means for
test purposes. It is recommended that TEST
be
left open by the user. An internal pull-up resistor is
tied to this pin to satisfy the appropriate logic level
required for proper device operation.
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature
under Bias ......... OOC (32°F) to 50°C (122°F)
Voltage on any pin
with respect to Vss ............ -0.2V to + 7.0V
Power Dissipation ........................ 1 Watt
STORAGE TEMPERATURE
PLASTIC ........ -55°C (-67°F) to + 125°C (257°F)
CERAMICS ...... -55°C (-67°F) to + 150°C (302°F)
NOTE: Maximum ratings indicate operation where permanent device damage may occur. Continuous operation at these limits is not intended and should be limited
to those conditions specified in the DC electrical
characteristics.

Winchester Disk Controller Devices

= OOC (32°F) to 50°C (122°F), Vcc = ± 5V

DC Electrical Characteristics: TA
SYMBOL
VIL
VIH
VOL
VOH
Vce
lee
IIH
IlL

PARAMETER

MIN

Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Supply Voltage
Supply Current
Current Input High
Current Input Low

-0.2
2.0

SYMBOL

tCL

UNIT

0.8

V
V
V
V
V
mA
IlA
IlA

0.4
2.4
4.5

PARAMETER

MIN

WCLK frequency
OCLK pulse width
Data set-up w.r.t. t OCLK
Data hold time w.r.t. t OCLK
! OCLK to ! BOONE
! WCLK to OOUT
! WCLK to ! SH FCLK
t WCLK to t SH FCLK
t WCLK to t BOONE
! EN to BOONE, OOUT
SH FCLK ACTIVE
t WCLK to! LO

5.0

5.5
125
<10
<10

TYP1

tD~:~DH

=
=

5 ± 10% Vss

UNIT

90

MHZ
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec

150

nsec

1:

-1 ~s
---1 :,
,

= OV

CONDITION
50% duty cycle

EN
EN
EN
EN
EN

=0
=0
=0
=0
=0

~I

LJ

:

~

~

CJ1

All Ouputs Open
VIN
.4 to Vee
VIN
.4 to Vee

I

I

'

~~------~-------------~
tws

'--------tD- S- :
r-----..-----'-'-If--

~

o
oI
o

l--!.DW

~_ _ _ _ _ ,

BONE

:ec

= 3.2 mA
= 200 IlA

------~LJ~'----~----------~LJ

07-00

OV

CONDITION

10L
10H

5.25

160
130
75
70
180

=

-I.
-I.

MAX

50
30
50

± 10%, Vss

= 25°C (77°F) and Vee = + 5.0V

NOTES: 1. Typical Values are for TA

__I

MAX

= OOC (32°F) to 50°C (12~F); Vee = +

AC Electrical Characteristics: TA

WC
tow
tos
tOH
tOB
too
tSH
tHS
tWB
tES

TYP1

I

____~~

1

~

:

1

I

____~----~l~ri------------~~____
-I

1--

I

I

teL....,

~

'IW-J

1

II

LJ

1

__ : :.-!DO

;I~~,------------~I~I------------------~----------------------------r'
1 :

DOUT

INVALID DATA
I 1

tSH

--, !--

: I
--

I,

t HS

1--

S H FC L K "----_-LJ-I
SHFELK

'----_.L..J

Figure 3.
WD1100-05 Functional Timing Diagram

Winchester Disk Controller Devices

3-85

3-86

Winchester Disk Controller Devices

WESTERN

DIGITAL

c

A

o

R

P

0

R

o

T

N

:E
c

WD1100-06 ECC/CRC Logic

~
~

o
o
o•

FEATURES

C')

•

32-BIT COMPUTER SELECTED POLYNOMIAL

•

DATA TRANSFER RATES TO 5.25 M BITS/SEC

•

SINGLE BURST CORRECTION TO 8 BITS

•

SERIAL CHECK/SYNDROME BIT PROCESSING

•

MULTIPLE BURST DETECTION

•

•

PROGRAMMABLE CORRECTION/DETECTION SPAN·

SINGLE

•

CRC OR ECC SOFlWARE SELECTABLE

•

TTL, MOS COMPATIBLE

•

20 PIN DIP PACKAGE

128,256,512 BYTE SECTOR SIZES

+ 5V

SUPPLY

DESCRIPTION

The WD1100-06 ECG/GRG logic chip gives the user
of the WD1100 series of chips easy EGG or GRG
implementation. With proper software, it will provide
single burst correction up to 8 bits and double burst

detection. The computer selected polynomial has
been optimized for Winchester 5 1/4" and 8" drives
with sector sizes up to 512 bytes.

SEL.---------------------------~

ECCIZ .----------------------,
DCSS __-------------~
R/W .....- - - - .

RCP

MUX

CONTROL

R/W

20

vCC

RCP

19

WBS

WCP

DOUT
EDOUT

RBS

RDAT

CSE

WDAT

BS

WOP
RDAT

DCSS

4

EDOUT

WDAT
SEL

DOUT

6

FBD

ECCIZ
NC

8

ECCEN

9

vss

RBS

ECCEN

WBS

FBD

CSE

Em
11

RWCP

RWCP

S
SHIFT REGISTER
DO

Figure 1.
WD1100-06 CONNECTIONS

Winchester Disk Controller Devices

031

Figure 2.
WD1100-06 BLOCK DIAGRAM

3-87

WD1100-06 ECC/CRC DEVICE PIN DESCRIPTION

:E
c......

PIN
NUMBER

PIN NAME

SYMBOL

o
o
o•

1

READjWRITE

RjW

Input line used to select the data, clock and CRC/ECC
strobe during read/write operations. When low input
signals WDAT, WCP, and WBS are selected. When high
input signals RDAT, RCP, and RBS are selected.

2

READ CLOCK
PULSE

RCP

Input pulse used by the internal shift registers to
compute the 4 syndrome bytes.

3

WRITE CLOCK
PULSE

WCP

Input pulse used by the internal shift registers to
compute the 4 check bytes.

4

READ DATA

RDAT

Serial data input during a read operation.

5

WRITE DATA

WDAT

Serial data input during a write operation.

6

SELECT

SEL

This input is used to select either the CRC or the ECC
polynomial for error detection/correction. SEL
0 ECC
polynomial selected. SEL
1 CRC polynomial selected.

......
0)

FUNCTION

=

3-88

=

7

ECC INITIALIZE

ECCIZ

Input used to preset all the internal shift registers. Output lines FBD, EDOUT, DOUT, and CSE will be in their
inactive high states. The first low going edge of either
RDAT or WDAT signals the activation of all internal
circuitry.

8

NO CONNECTION

N/C

No connection.

9

ECC ENABLE

ECCEN

When low, the ECC/CRC process is enabled. When high,
this output Signal indicates that the process is disabled.

10

GROUND

vSS

Ground.

11

READLWRITE
CLOCK PULSE

RWCP

Output clock pulse during read or write operations. The
input clock pulses RCP and WCP are multiplexed on
this output line for use by any support logic.
'

12

BYTE SYNC

BS

The input signals RBS and WBS are gated with the
appropriate clocks and multiplexed as an output on the
byte sync line. Normally not used by the user.

13

CLOCK SELECT
ENABLE

CSE

When high, this output indicates that the device is in
the process of computing the check/syndrome bytes and
that EDOUT and DOUT lines contain data information.
When low, the device puts CRC or ECC check/syndrome
bits on the output data lines.

14

FEEDBACK

FBD

The feedback line to the shift registers is brought out as
an output line for test purposes. Normally left open by
the user.

15

DATA OUTPUT

DOUT

Output data line carries data or CRC/ECC information
depending upon the state of DCSS.

16

EARLY DATA

EDOUT

Unlatched output data line available 1 clock period earlier
than DOUT.

Winchester Disk Controller Devices

WD1100-06 ECC/CRC PIN DESCRIPTION (CONTINUED)
PIN
NUMBER
17

:E

PIN NAME

SYMBOL

DATA/CHECK
SYNDROME SELECT

DCSS

FUNCTION

Data or check/syndrome select input line. When high,
data Is output on the data lines; when low, CRC or check
syndrome bits are output depending upon which
polynomial selected. DCSS goes low sometime between
the last and the next to the last data byte transferred
to/from the disk provided all set-up and hold-times have
been met. DCSS must stay low for at least 2-byte times
when the CRC polynomial selected and it must stay low
for at least 4 byte times if the ECC polynomial Is selected.

18

READ BYTE

RBS

19

WRITE BYTE

WBS

Input used to latch the state of DCSS during the write
mode.

20

+5V

vcc

+5V±10%

DEVICE DESCRIPTION

To ensure correct operation of the WD11()(}()6 device,
the ECCIZ line is strobed to preset the polynomial
generator shift register, and reset the Data/CheckSyndrome select flip-flop. The 32-bit shift register
string is preset to avoid all zero check bytes. The
DCSS line is held high and appropriate Signals are
then applied to the rest of the inputs. Since most disk
media use an Address mark of A1 (or M.S.B. set),
advantage is taken of this feature to start off the
ECC/CRC calculation on the data/ID fields
automatically. The first active low going edge on the
input data lines releases the internal SET Flip-Flop.
The ECCEN output line is set low indicating that the
internal circuitry is ready to begin the computation
of the ECC/CRC bytes. Immediately following the
Address mark, data is supplied in a serial fashion.
Sometime before the last byte of data and after the
next to the last byte of data is transferred through
this device, the DCSS line is set low. Since data is
generally serialized/deserialized before/after processing by the WD1100-06 device, the byte-sync pulses
can be easily obtained from those devices marking
the byte boundaries. The byte-sync pulses are internally ANDED with the RWCP line to ensure
the smooth transition of checks/syndrome bytes on
the DOUT output line only after the last bit of data
has been entered into the device. A one bit time delay
through a D Flip-Flop has been added on the DOUT
line to deglitch this output line.
During a WRITE operation, the inRut data stream is
divided by the polynomial X 32 + X28 + X26 + X19 +
X17 + X10 + X~ + 1 and the 32-bit remainder
obtained is used as the 4 check syndrome bytes. If
the syndrome is zero, no errors occurred. Otherwise,
the non-zero syndrome is used by a software
algorithm to compute the displacement and the error
vector within the bad sector. To protect the integrity

Winchester Disk Controller Devices

Input used to latch the state of DCSS during the read
mode.

of the ID field only a CRC check should be performed
over this field. No attempt ought to be made to correct data in the ID field. The CRC polynomial
implemented is the standard CCITT (X16 + X12 + X5
+ 1.) Although either polynomial may be used for
both fields, the use of the CRC polynomial for the ID
fields is recommended since it only requires 2 bytes
instead of 4.
POLYNOMIAL SELECTION

For disk media, polynomial selection has a significant influence on data accuracy. Fire code
polynomials have been widely used on OEM disk controllers, but provide less accuracy than properly
selected computer generated codes.
For fixed, guaranteed correction and detection spans,
data accuracy may be highly dependent on
polynomial selection. Some polynomials, fire codes
for example, are particularly susceptible to miscorrection on common disk type errors, while others,
computer generated polynomials for example, can be
selected to be less susceptible. Computer generated
codes do not have the pattern sensitivity of the fire
code and the miscorrection patterns are more random in nature.
More than 20,000 computer generated random
polynomials of degree 32, each with 8 feedback terms,
were evaluated in order to find the polynomial
described in this specification.
SELECTING THE CORRECTION SPAN

The code described in this document can be used to
correct up to a-bits.
Any correction span from 1 to 8 may be selected.
However, for best data accuracy, the lowest correction span should be used that meets the correction
requirements for the disk drives supported.

3-89

...c...

.

o
o

o

0)

=E
c
.....
.....
o
oI

o

en

For most Winchester media, a 5-bit correction span
is adequate.
The correction span may have to be longer if the drive
uses a read/write modulation method that maps a
single media bit in error into several decoded bits in
error. Examples of read/write modulation methods of
this type would be GCR and 2,7 code.
PROPERTIES OF THE POLYNOMIAL

The following polynomial was computer selected for
insensitivity to short double bursts, good detection
span and 8 feedback terms.
Forward polynomial is:
X32 + X28 + X26 + X19

X17

+

X10

+

X6

+

X2

+

Reciprocal polynomial is:
X32 + X30 + X26 + X22 + X15
Xc.

+

X13

+

X6

+

X4

+

+

O.

SOFTWARE REQUIREMENTS

The software algorithm, developed by the user, uses
the syndrome to detect an error, generate a correction pattern and a displacement vector or to determine if uncorrectable. In the correction algorithm, a
simulated shift register is used to implement the
reciprocal polynomial. The simulated shift register is
loaded with the syndrome and shifted until a correctable pattern is found or the error is determined to
be uncorrectable. Both forward and reverse
displacements are computed.
Either the serial or the parallel algorithm may be
implemented by the user. In almost all cases the
serial software algorithm is the most applicable. Additionally, 1K of table space is required if the parallel
software algorithm is selected. It is assumed that the
highest order bit of a byte is serialized and
deserialized first.
CORRECTION TIME PERFORMANCE

Properties *
1. Maximum record length (r) = 526x8-bits (including check bits)
2. Maximum correction span (b) = 8-bits
3. Degree of polynomial (m) = 32
4. Single burst detection span without correction =
32 bits.(Detection span when the code is used for
detection only)
5. Single burst detection span with correction (d) (Detection span when the code is used for
correction)
19 bits for b
5 and r
526x8
14 bits for b
8 and r
526x8
20 bits for b
5 and r
270x8
= 14 bits for b = 8 and r + 270x8
6. Double burst detection span without correction (Double burst detection span when code is used
for correction)
3 bits for b
5 and r
526x8
2 bits for b
8 and r
526x8
4 bits for b
5 and r
270x8
2 bits for b
8 and r
270x8
7. Non-detection probability = 2.3E-10.
8. Miscorrection probability 1.57 E-5 for b
5 and r
526x8
1.25 E-4 for b
8 and r
526x8
8.00 E-6 for b
5 and r
270x8
6.40 E-5 for b
8 and r
270x8

=
=
=

=
=
=

=
=
=

=
=
=
=

=
=
=
=

=
=
=
=

=
=
=
=

=
=
=
=

=
=
=
=

All real time operations are performed with error correction hardware. The software algorithms used get
involved only after an error has been detected.
The following correction times are for a serial type
algorithm such as that used on the WD1001:
a) Standard microprocessor
30 to 60 milliseconds
b) Bit slice = 6 to 12 milliseconds
c) 8X300 (used on WD1001) = 15 to 30 milliseconds

=

DATA ACCURACY

ERP (Error Recovery Procedure) strategies have a
significant influence on data accuracy. An ERP
strategy requires data to be re-read before applying
correction and results in much better data accuracy.
The WD1001 employs such a strategy. This strategy
reduces the possibility of passing undetected
erroneous data by rereading until the error goes away,
or until there has been a consistant error syndrome
over two previous rereads.
Another technique that can be used to give data a
higher probability of recovery is write check: read back
after write. Since write check affects performance, it
should be optional. Alternate sector assignment and
defect skipping are some of the other techniques that
may be implemented by the user if so desired.

NOTE:*
You should not use this polynomial for a record length
of correction span beyond the maximum specific
above.

3-90

Winchester Disk Controller Devices

SELF-CHECKING WITH MICROCODE

Periodic microcode and/or software checking is
another approach that can be used to limit the
amount of undetected erroneous data transferred in
case of an ECC circuit failure. Microcode or software
diagnostics could be run on subsystem power up and
during idle times. These diagnostics would force ECC
errors and check for the proper syndrome and proper decoding of the syndrome by the correction
routine· of the operational microcode.
To do this, simply use a long bit in the READ and
WRITE commands to the disk. This bit can then be
used to suppress the transfer of check/syndrome
bytes on the output data line by letting the DCSS line
stay high during ECC TIME. The complete procedure
is summarized below.
1. WRITE: Pass all data to the disk and generate 4
check bytes at the end of the data field.
2. READ LONG: Do not generate the syndrome,
instead copy the 4 check bytes as data and pass
them unaltered to the Host. Now the Host may
induce errors anywhere in the data stream as long
as the induced error does not exceed the correction span of the polynomial generator.

Winchester Disk Controller Devices

3. WRITELONG: Write the data and check bytes supplied by the Host to the disk. Prevent WD1100-06
from generating check bits by not asserting DCSS
during transfer. No check bytes will be recorded.
4. READ: Read data and generate the syndrome in
a normal manner. The software algorithm can now
be invoked to correct the induced error.
To aid in detection of certain hardware failures, it is
desirable to have non-zero check bytes for an all zeros
record. This feature has been incorporated into the
circuit defined in this specification.

Ambient Temperature under Bias .... OoC (32°F) to
50°C (122°F)
Voltage on any pin with
respect to Vss ............... -O.2V to + 7.0V
Power Dissipation ...................... 1 Watt
Storage Temperature
Plastic ...' .... -550 C (-67°F) to + 125°C (257°F)
Ceramic ...... -55°C (-67°F) to + 150°C (302°F)

3-91

=E

c.....
.....
o
oI

o

0')

SPECIFICATIONS

:ec
......
......

o
o
I

o

0')

ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under Bias .... OOC (3~F) to
50°C (122°F)
Voltage on any pin with
respect to Vss ............... -0.2V to + 7.0V
Power Dissipation ...................... 1 Watt
Storage Temperature
Plastic ....... -55°C (-67°F) to + 125°C (257°F)
Ceramic ...... -55°C (-67°F) to + 150°C (302°F)
DC Operating Characteristics TA
SYMBOL

V,L
V,H
VOL
VOH
Vcc
Ice
I'H
I,L

NOTE:
Maximum ratings indicate operation where permanent device damage may occur. Continuous operations at these limits is not intended and should be
limited to those conditions specified in the DC
operating characteristics.

= OOC (32°F)to 50°C (122°F), Vcc = +5V

PARAMETER

Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Supply Voltage
Supply Current
Current Input High
Current Input Low

MIN

TYP1

-0.2
2.0

MAX

UNIT

0.8

V
V
V
V
V
rnA
uA
uA

0.4
2.4
4.5

5.0
75

5.5
150
<10
<10

= OV

± 10%, Vss

CONDITIONS

10L
IOH

= 3.2 rnA
= -200~A

All Outputs Open
.4 to Vee
.4 to Vee

Y,N
Y,N

=
=

ECCIZ PULSE WIDTH
R/W

><==

J<_______

H_'G_H_FO_R_R_E_A_D__________L_O_W_F_O_R_W_R_'T_E_________________

ECCIZ~tIZ
-.j
~
ECCEN

tiE

~~----------~-----------------------------------------

RDAT _ _ _ _ _ _---,
WDAT

tST

I

~ ---.~
i

I

I

RCP
WCP

AC Electrical Characteristics TA
SYMBOL

= OOC (32°F) to 50°C(122°F), Vee = +5V

PARAMETER

fep
t,Z
tie
tST

Clock Frequency
ECCIZ Pulse Width
ECCIZ~ to ECCEN t
R/WDAT Setup Time

tHT

R/WDAT Hold Time

3-92

MIN

TYP1

MAX

UNIT

5.25

MHz
nsec
nsec
nsec

100
100
0

± 10%, Vss

100
1 Clock
Period

= OV
CONDITIONS

nsec

Winchester Disk Controller Devices

WESTERN

c

o

R

P

0

DIGITAL

R

A

o

T

N

:E

c
.....
.....

WD1100-07 Host Interface Logic

o

o
o
I

........

FEATURES

DESCRIPTION

•

SINGLE +5V SUPPLY

•

WAIT SIGNAL GENERATION

•

TIMING CLOCK GENERATION

The WD110D-07 Host Interface Logic chip simplifies
the design of a Winchester Hard Disk Controller using
the WD1100 chip series. It does this by performing
logic functions that would otherwise require considerable discrete logic. Additionally, there are signals
provided for ECC implementation.

•

INDEX PROPAGATION

•

CARD ACCESS CONTROL

•

COMPLIMENTS ECC ARCHITECTURE

•

20 PIN DIP PACKAGE

The WD110Q-07 is implemented in NMOS silicon gate
technology and is available in a 20-pin plastic or
ceramic Dual-in-Line package.

RD6

...

WR6

...

WAEN
Welj

VCC

WCl2

WCLK

RESET
SACEN

WHEN
RCP

RCLK
INDEX
LlNR
VSS

SACEN

CS

AMDET
TIMCLK

CS

WCLK

RBS
AMOUT

-

~

....

-

...
...

....

~

-

-

~

-;- 16

...

-u

:

INDEX

-

CSAC

-"""

TIMCLK

...

LlNDEX

~

A

CSAC

LlNDEX

-"'"

0

...

~

--

"

~

RESET
WR3

WAIT

,.,
CONTROL
LOGIC

r-- D

...
".

~

...

S
LATCH

a

R

-

RCLK ,.

...
.-

---

-

BYTE COUNTER
AND
DELAY

~

....I-

....

I-

--......
--..
---

RSS
RCP
'

AMOUT

9

Figure 1_
WD110D-07 PIN CONNECTIONS

Winchester Disk Controller Devices

Figure 2_
WD1100-07 BLOCK DIAGRAM

3-93

:E
c......

PIN
NUMBER

......

o
o
o•

.......

PIN NAME

SYMBOL

1

WCL1

2

WAIT CLEAR 2

WCL2

3

RESET

RESET

An input used to set TIMCLK & reset WAIT, AMOUT
and RBS.

4

SELECT ADDRESS
ENABLE

SACEN

This is an input signal that is used to enable card
select for host access.

5

ADDRESS MARK
DETECT

AMDET

An input that must go active when a DATA=A1(HEX)
or clock = OA(H EX) pattern is detected in the data
stream.

6

TIMING CLOCK

TIMCLK

An output used to provide reference timing signals to
SA100 type drives.

7

READ CLOCK

RCLK

This input, the same as used to clock in d~locks
to the AM detector, is used to produce AMOUT.

8

INDEX PULSE

INDEX

This input is provided by the drive once each revolution
of the disk.

9
10
11

LlNDEX RESET
GROUND
LATCHED INDEX

LlNR
Vss
LlNDEX

An input used to reset LlNDEX.
Ground.
An output that is INDEX delayed by one clock time.

WAIT

This output goes true when controller is internally
accessing data or has not accepted data from the host
during a WRITE.

12

WAIT

This input presets
t~on on the falling
This input presets
tion on the falling

a WAIT latch to a non-WAIT condiedge.
a WAIT latch to a non-WAIT condiedge.

13

CARD SELECT
ADDRESS

CSAC

An output that is the result of CS
SACEN.

14

ADDRESS MARK
DELAYED OUTPUT

AMOUT

This output is a delayed version of AMDET.

15

READ BYTE STROBE

RBS

This output strobes once for each byte of READ data.
Initialized by AMDET.

16

READ CLOCK PULSE

RCP

This output is delayed from RCLK through propagation.
Not normally used.

17

WAIT ENABLE

WAEN

An input that is used to enable the internal WAIT
circuitry.

qualified

with

18

CARD SELECT

CS

An input from host that selects controller.

19

WRITE CLOCK

WCLK

This input is used to produce TIMCLK on low to high
transitions.

20

+5VDC

Vcc

+5V±10%.

DEVICE DESCRIPTION
Upon power up or reset, WAIT, AMOUT, and RBS
are reset and TIMCLK is set. This is the only interactive signal between the four sections of the chip. Each
section will be described separately.
Control Logic
This section provides WAIT (pin 12) and CSAC (pin
13). WAIT is set in its active low state when WAEN
(pin 17) is active low by the falling edge of CS (pin
18). WAIT is reset by the falling edge of either WCL1

3-94

FUNCTION

WAIT CLEAR 1

or WCL2 depending on whether in a read or write
mode. CSAC (pin 13) is enabled by setting SACEN
(pin 4) low after WAIT has been enabled. CSAC is
reset by WCL1 or WCL2.
Timing Clock
TIMCLK (pin 6) is a divided by sixteen version of
WCLK (pin 19). It is used with SA1000 type drives.
Index Pulse
Lindex (pin 11) is a delayed version of INDEX (pin
8). It remains high until reset by LlNR (pin 9).

Winchester Disk Controller Devices

Read Byte Sync

SPECIFICATIONS

RBS (pin 15) will go true on the eighth negative going transition of RCLK (pin 7) after AMDET (pin 5)
goes true. RBS will remain true for one clock cycle.

ABSOLUTE MAXIMUM RATINGS

Read Clock Pulse
RCP (pin 16) is a delayed version of RCLK and is normally left open by the user.
Address Mark Delayed Output

Ambient Temperature
under Bias ........
(32°F) to 50°C (122°F)
Voltage on any pin
with respect to Vss .............. -0.2V to + 7.0V
Power Dissipation ...................... 1 Watt
Storage Temperature
Plastic .... -55°C (-67°F) to + 125°C (257°F)
Ceramic ... -55°C (-67°F) to + 150°C (302°F)

ooe

AM OUT (pin 14) is the same as AMDET delayed by
two clock times.

NOTE:

These circuits were developed to work with the other
chips in the WD1100 series. They are used on the
WD1001 the timing relationships must be observed.

Maximum ratings indicate operation where permanent device damage may occur. Continuous operation at these limits is not intended and should be
limited to those conditions specified in the DC electrical characteristics.

DC Electrical Characteristics TA
SYMBOL
VIL
V IH
VOL
VOH
Vcc
Icc
IIH
IlL

PARAMETER

SYMBOL
WCLK
es~ to
WCLH
WAEN

tAM

AMDET~

TYP1

-0.2
2.0

UNIT

0.8

V
V
V
V
V
rnA
uA
uA

0.4
2.4
4.5

5.0

FREQUENCY
WAin
or WCL2~ to WAiTt
Setup Time
SACEN~ to CSACt

WCL1~orWCL2~CSAC~

WCLKt to TIMCLKt
INDEX~ to LlNDEXt
LlNR~ to LlNDEX~
RCLK~ to RCP~
AMDET Setup Time

MIN

5.5
125
<10
<10

MAX

UNIT

50
170

5.25
160
195

MHz
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec

50
5
45
50
30
30
30
2 CLOCK
CYCLES

to RBS~
RBS Period

8 CLOCK
CYCLES
+165
1 CLOCK
CYCLE

70
155
250
100
100
75
50
2 CLOCK
CYCLES
+45
8 CLOCK
CYCLES

90

= OV
CONDITIONS

10L
10H

= 3.2 rnA
= -200J.lA

All Outputs Open
VIN
.4 to Vee
VIN
.4 to Vce

± 10%; Vss

TYP1

to AMOUn

RCLK~

± 10%, Vss

MAX

= O°C (32°F) to 50°C (122°F); Vce = 5V

PARAMETER

fwc
tew
tws
tsu
tsc
tcs
twr
tu
tLW
t pc
tRA

1NOTE:

MIN

Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Supply Voltage
Supply Current
Current Input High
Current Input Low

AC Electrical Characteristics TA

t BS
tRB

= O°C (32°F) to 50°C (122°F); Vcc = +5V

=
=
= OV

CONDITIONS

WAIT TRUE
WAIT TRUE

nsec

nsec
nsec

Typical Values are for TA = 25°C (77°F) and Vcc = + 5V

Winchester Disk Controller Devices

3-95

:E
c
.....
.....

o
o
o•

......

:E
c
.....
.....
0
0
I
0

WAEN

"""

CS

tsu-+1 ~

I

tcw --.J
t+----------~~1

f.-

tws-.i

__________~1----~1----------------------

WAIT

:
I

U

WCL1orWCL2

I
I

I
I

SACEN

I

tsc -..:I

tcs -..J

I

1"4I

:.I

CSAC'

WCLK

twr-..J

I
~

~

I

fWC

~

TIMCLK

tu....!I

I

I~

LlNDEX
~

u
I

RCP

RCLK

tRA":

"

J..-

~i~I----~I~-------------------------------------------------------------~tAM~

!
I

I

l

~I---------------------------------------------------------------

LJ

~:~~-----------------tBs---------------------'·~I~·tRB-1

3-96

Winchester Disk Controller Devices

DIGITAL

WESTERN

c

o

R

P

0

o

RAT

N

WD1100-09 Data Separator Support Logic
The WD1100-09 is fabricated in NMOS silicon gate
technology and is available in a 20 pin plastic or
ceramic package.

GENERAL DESCRIPTION

The WD1100-9 Data Separator Support Logic, when
used with the other chips in the WD1100 series,
greatly reduces the external discrete logic required
to design a Winchester hard disk data separator. The
chip provides the pump signals to an external error
amplifier, control signals to an internal bus and a
special drive selection signal also to an internal bus.

FEATURES

•
•
•
•

--...
-

-

DATA

1

VCC

REF

2

RGATE

DIN

3

DMR

OSC

4

DRS4

DRS1

5

WRITE

HIFRQ

6

DRS3

DRS2

7

OS

DRUN

8

WDAT

DOUT

9

DOWN

VSS

10

DIN
OSC

DMR
DATA
RGATE

UP
WDAT
WRITE
REF

Figure 1.
WD1100-o9 Pin Connections

Winchester Disk Controller Devices

SINGLE + 5V SUPPLY
DRUN GENERATION
DATA SEPARATION CONTROL SIGNALS
20 PIN DIP PACKAGE

,.

-

,....

,..

-

PUMP
LOGIC

"'

----

UP
DOWN

I

--...-

OS

.r"I

-...
--

--...

---

DRIVE
SELECTED
LOGIC

DATA
SEPARATOR
CONTROL
LOGIC

,.

...

-.., -

...
-- -

DRUN
DOUT
HIFRQ

Figure 2.
WD1100-o9 Block Diagram

3-97

=E
c

PIN
NUMBER

PIN NAME

SYMBOL

....L
....L

1
2

READ DATA
REFERENCE

DATA
REF

(0

3

DELAYED DATA IN

DIN

4

OSCILLATOR

OSC

DRIVE SELECT 1DRIVE SELECT 4
HIGH FREQUENCY

DRS1DRS4
HIFRQ

8

DATA RUNNING

DRUN

9

DATA OUT

DOUT

10
11

GROUND
UP PUMP

Vss
UP

12

DOWN PUMP

DOWN

13
14

WRITE DATA
DRIVE SELECTED

WDATA
DS

16

WRITE MODE

WRITE

18

DMR

19

DATA MASTER
RESET
READ GATE

20

+5V DC

Vcc

o
oI
o

5,7,
15,17
6

RGATE

FUNCTION
Input that is used in DRUN generation.
An input that is 2 times the data rate that keeps the VCO
on center frequency during non-read times.
This input is a delayed version of DOUT. An external delay
line is used. The signals are compared to provide pumps.
An input from the external VCO that is used in pump
development.
Input signals indicating which drive has been selected.
Output to controller microprocessor that indicates 16
ones or zeroes have been entered on the DATA line.
Output that indicates to the controller microprocessor the
completion of 16 ones or zeroes on the data line. Used
to switch from REF to DATA via firmware.
Output data line. Can be REF or DATA or WDATA depending on the condition of WRITE, DME and RGATE.
Ground.
An output that indicates REF is leading DATA. Goes to
error amp. Open collector.
An output that indicates DATA is leading REF. Goes to
error amp. Open collector.
MFM Write data input. Output appears at DOUT.
An output that indicates that one of four drives have been
selected.
This input is active during a write operation and enables
WDAT.
This input is used to provide time-out for DRUN and HIFRQ
in the event that 16 ones or zeroes are not present.
This input, usually provided by the controller microprocessor, places chip in read mode.
+5VDC = 10%.

DEVICE DESCRIPTION

Data Separator Control Logic

The WD1100-09 is divided into three sections. Each
section will be described separately.

Read Mode

Drive Select Logic
DS (pin 14) will go active high if any input DSR1
through DRS4 (pins, 5, 7, 15, 17) are active low.
Pump Logic
Internal logic causes the UP (pin 11) and the DOWN
(pin 12) to be set, initially to their inactive states. DIN
(pin 3) is the delayed data developed by passing DOUT
through a delay line. OSC (pin 4) is the output of the
data separator VCO. Whichever reaches the pump
logic first will determine whether UP PUMP or DOWN
PUMP is produced. These signals are then sent to
an external error amplifier and used for VCO correction. During a write, the DIN must be locked to a
crystal oscillator clock and will hold the VCO on
frequency.

3-98

In order to prevent the external VCO from locking onto
a harmonic of its operating frequency, REF (pin 2) is
provided with a signal twice the data rate that is
crystal controlled. With WRITE (pin 6) and RGATE
(pin 19) inactive, this signal will appear at DOUT (pin
9). This signal is applied to the pump logic (see above).
The switching function is initiated immediately after
RGATE goes true. DMR (pin 18) will be set active as
a result of high frequency pulses applied to an external one shot whose pulse width is such that its output is a single stretched pulse. The high frequency
pulses are applied to the DATA (pin 1) line and after
16 consecutive pulses, DRUN (pin 8) and HIFRQ

Winchester Disk Controller Devices

(pin 6) go true. At this point REF is switched out and
the DATA stream is switched in and appears at DOUT.
DRUN is reset when RGATE goes inactive and HIFRQ
goes inactive when DMR goes inactive.

SPECIFICATIONS

:E

ABSOLUTE MAXIMUM RATINGS
Ambient Temperature
under Bias ......... OOC (32°F) to 50°C (122°F)
Voltage on any pin with
respect to Vss ................ -0.2V to + 7.0V
Power Dissipation ...................... 1 Watt
STORAGE TEMPERATURE

WRITE MODE
When WRITE (pin 16) goes active, REF is switched
out and WDAT (pin 13) will appear at DOUT. Since
WDAT is a crystal controlled signal (usually the MFM
write data); the VCO is held locked and will not drift.

Plastic ........ -55°C (-67°F) to
Ceramic ....... -55°C (-67°F) to

+
+

125°C (257°F)
150°C (302°F)

NOTE: Maximum ratings indicate operation where
permanent device damage may occur. Continuous
operations at these limits is not intended and shou Id
be limited to those conditions specified in the DC
Electrical Characteristics.
DC Operating Characteristics TA
SYMBOL
VIL
VIH
VOL
VOH
Vcc
lee
IIH
IlL

= OOC (32°F) to 50°C (122°F), Vec = + 5V 10%, Vss = OV

PARAMETER

MIN

Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Supply Voltage
Supply Current
Current Input High
Current Input Low

-0.2
2.0

TYP1

MAX

UNIT

0.8

V
V
V
V
V
rnA
J.LA
J.LA

0.4
2.4
4.5

5.0

5.5
125
<10
<10

CONDITION

10L
10H

= 3.2mA
= -200J.LA

All Outputs Open
VIN
.4 to Vee
VIN
.4 to Vee

=
=

NOTE: UP and DOWN are open collector outputs and provide 12mA 10L @ .5V.

Winchester Disk Controller Devices

3-99

c.....

.....
o
o

6

c:o

:E
C

READ MODE

-"
-"

DMR~

(.0

DATA

0
0I
0

p------

~--~,s

DRUN

RGATE~
-----~fS~--------

HIFRQ

I

------l.~l~ REF
DOUT

-.;

truiIulJl

~tRE

WRITE

WRITE MODE
DMR

DATA
DRUN

HIFRQ

WRITE

DOUT

AC Electrical Characteristics TA

SYMBOL

3-100

= OOC (32°F) to 50°C (122°F); Vee = 5V

PARAMETER

too
tOR
tHO

DATA to DRUN
RGATE to DRUN
DMR to HIFRQ

tRE

REF frequency

MIN

TYP1

2 TIMES
DATA RATE

± 10%; Vss

MAX

UNIT

170

90
90

nsec
nsec
nsec

10

MHz

= OV
CONDITION

Winchester Disk Control/er Devices

WESTERN
G

0

R

P

0

DIGITAL

R

A

o

T

N

WD110D-12 Improved MFM Generator
DESCRIPTION

The WD1100-12 is fabricated in NMOS silicon gate
technology and Is available In a 20-pln plastic or
ceramic dual·ln·line package.

The WD1100-12 Improved MFM Generator converts
NRZ data into an MFM (Modified Frequency Modulated) data stream. The derived MFM signal containing both clocks and data can then be used to record
information on a Winchester Disk Drive utilizing this
recording technique. In addition to an MFM output,
the device generates first level Write Precompensation signals for use with inner track densities. A
unique feature of the WD11 00-12 is the ability to delete a clock pulse in the outgoing MFM stream in
order to record Address Marks.

FEATURES

•
•
•
•

SINGLE +5V SUPPLY
5M BIT/SEC DATA RATE
WRITE PRECOMPENSATION
ADDRESS MARK GENERATION

RWC ~------------,

---CI

NRZ ....

WCLK ....- - - - a

4BIT
SHIFT
REG.

WRITE
PRECOMP
GEN.

WCLK ....- - - - I

EARLY
NOM
LATE

MFM

VCC
AD
WCLK

A1

~

MR

RWC
CS

SKPEN

------1

WD1100-12
Figure 2. Block Diagram MFM Generator

MFM
INTRa
ORa
EARLY

DRaCLK ....- - - - - - - - - . . . . ,

LATE
VSS

NOM

AD
A1

CS
MR __---------~-~

Figure 1.
WD110o-12 Pin Connections

Winchester Disk Controller Devices

Figure 3.
WD110o-12 Block Diagram Interrupt Control logic

3-101

PIN
NUMBER

SYMBOL

NAME

1

NRZ

2

SKPEN

NON·RETURN·TO
ZERO
SKIP ENABLE

3

WCLK

WRITE CLOCK

4
5

WCLK
RWC

9

2XDR

10
11

Vss
NOM

WRITE CLOCK
REDUCED WRITE
CURRENT
2 TIMES
DATA RATE
Vss
NOMINAL

12

LATE

LATE

13

EARLY

EARLY

16

MFM

MFM DATA

6

CS

CHIP SELECT

8

INTCLK

7

DRQCLK

15

INTRQ

14

DRQ

INTERRUPT
REQUEST CLOCK
DATA REQUEST
CLOCK
INTERRUPT
REQUEST
DATA REQUEST

17
18,19

20

-

MR

MASTER RESET

Ao,A1

ADDRESS 0,1

Vcc

Vcc

DEVICE DESCRIPTION
The WD1100·12 is divided into two sections: MFM
Generator and Interrupt Logic. The MFM Generator
converts NRZ data into MFM data and provides Write
Precompensation signals. The Interrupt Logic is used
specifically on the WD1000 Winchester Controller
Board and may be used in similar designs to generate
Interrupt signals. The two sections of the device are
isolated and have no common input or output signals.

3-102

FUNCTION
NRZ data input that is strobed into the MFM
generator by WCLK(~).
This input arms the SKIP logic for recording
Address Marks when set to a logic 1.
Complimentary clock inputs. NRZ data is
clocked into the MFM Generator on the high·
to·low transition of WCLK
(pin 3).
This signal when high, enables EARLY, LATE
and NOM outputs.
This input is used to latch EARLY, LATE, NOM
and M FM outputs.
Ground.
Output signal from the Write Precompensation
Logic used to signify that data is to be written
nominal.
Output signal from the Write Precompenstion
Logic used to signify that data is to be shifted
LATE before writing.
Output signal from the Write Precompensation
Logic used to signify that data is to be shifted
EARLY before writing
This output contains the MFM encoded data
derived from the NRZ (pin 1) line.
Low input signal used to enable the Address
decode logic.
A low on this line will latch the INTRQ (pin 15)
at a logic O.
A low on this line will latch the DRQ (pin 14) at
a logic O.
This output is latched at a logic 0 when INTCLK
(pin 8) goesl is low.
This output is latched at a logic 0 when
DRQCLK (pin 7) goesl is low.
A low level on this line causes DRQ and INTRQ
to set at a·logic 1.
When CS is low and the address lines go high,
INTRQ is cleared; if the address lines go low
then DRQ gets cleared. (i.e. set at a logic 1).
+ 5V 2 10% power supply input.

Prior to entering data, the SKPEN line must be set
to a logic 0 to enable only clocks in the data stream.
Data is entered on the NRZ line and strobed on the
high·to·low transition of WCLK. The encoded NRZ
data appears on the MFM (pin 16) output lagging by
one clock cycle.
Write Precompensation signals EARLY, LATE, and
NOM are generated as each data or clock pulse
becomes available at the input when RWC is logic 1.'

Winchester Disk Controller Devices

LAST DATA SENT

SENDING

TO BE SENT
NEXT

EARLY

LATE

NOM

H

L

L

:E

c
......

......

X

1

1

0

X

1

1

L

H

L

0

0
0

o
o

0

1

H

L

L

r\l

1

0

0

0

L

H

L

L

L

H

ANY OTHER PATTERN

.!J..

DEVICE DESCRIPTION (CONTINUED)

When the SKPEN signal is set to a logic 1, the internal skip logic is enabled. As long as zeroes are being
shifted into the NRZ line, the device generates normal MFM data. On receipt of the first non-zero bit
(typically the MSB of the A1 16 the skip logic begins
to count WCLK cycles. When the MFM generator tries
to produce a clock between data bits 2 and 3, the skip
logic disables the MFM generator during that time.
The result for A1 16 data is a clock pattern of OA 16
instead of OE16. Although other data paterns may be
used, the MSB of the pattern must be a 1 (8016 or
higher) in order to enable the skip logic at the proper
time. After the skip logic has performed, it then
disables itself and MFM data is recorded normally
starting with the succeeding byte. To re-enable the
skip logic again, the SKPEN line must be strobed.

Ao

CS

0

A1
X

X

X

H

H

1

X

X

1

aN

a
a
a
a

aN
H

MR

The SKPEN signal is used to record a unique
data / clock pattern as an Address Mark, using AI 16
data with OA 16 clock. This pattern is used for synchronization prior to data or ID fields that are read
from the disk.

X

1

0

0

1

1

1

1

1

0

1

0

1

DRa

aN
aN
aN

INTRa

aN
H
aN
a

= Don't care

ON = remains at previous state
DRO and INTRa can be set to a logic 0 only by a low
level or DROCLK and INTCLK respectively. The signal
will remain at a logic 0 un.!!!.. cleared by a MR or proper address selection via CS, A1 , and A:;.

The Interrupt Logic is used to clear Data Requests
(DRa) and Interrupt Requests (INTRa) by selecting
CS (pin 6) in combination with Ao and A1• The MR
(Master Reset) Signal is used to clear both DRa
and INRa Simultaneously.

Winchester Disk Controller Devices

3-103

NOTE:

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature
under Bias ......... 0oC (32°F) to 50°C (122°F)
Voltage on any pin
with respect to Vss ........... -0.2V to + 7.0V
Power Dissipation ...................... 1 Watt

Maximum ratings indicate operation when
permanent device damage may occur. Con·
tinuous operation at these limits is not
intended and should be limited to those
conditions specified in the DC Electrical
Characteristics.

STORAGE TEMPERATURE:
PLASTIC ..... -55°C (-67°F) to + 125°C (257°F)
CERAMIC .... -55°C (-67°F) to + 150°C (302°F)
DC Electrical Characteristics TA = OOC (32°F) to 50°C (122°F); Vcc = + 5V ± 10%; Vss = OV
SYMBOL
VIL
VIH
VOL
VOH
Vcc
Icc
IIH
IlL

PARAMTER
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Supply Voltage
Supply Current
Current Input High
Current Input Low

MIN

TYP1

-0.2
2.0

MAX

UNIT

0.8

V
V
V
V
V
rnA
JlA
JlA

0.4
2.4
4.5

5.0

5.5
125
<10
<10

CONDITION

IOL=3.2mA
10H = -200JlA
All outputs open
VIN = .4 to Vcc
VIN = .4 to Vcc

AC Electrical Characteristics TA = OOC (32°F) to 50°C (122°F); Vcc = +5V ± 10%; Vss = OV
SYMBOL
tFR
tos
tOH
tTM
tMR
t Mo

3-104

PARAMTER
WCLK FREQUENCY
Data Setup w.r.UWCLK
Data hold w.r.UWCLK
t2XDR to t M FM
Master reset pulse width
~MR to tDRQ

MIN

TYP1

MAX

UNIT

5.25

MHZ
nsec
nsec
nsec
nsec
nsec

10
25
115
50
150

CONDITION
"Per
"Per
"Per
"Per
"Per

Figure
Figure
Figure
Figure
Figure

4"
4"
4"
5"
5"

Winchester Disk Controller Devices

SYMBOL

tMI
too
tlO
too
til
tAO
tAl
tco
tCI
tRN
tTE
tTN
tTL

PARAMTER

MIN

Typ1

~MR

to tlNTRO
OROCLK pulse width
INTCLK pulse width
~ORQCLK to ORO
~INTCLK to INTRO
~AX to tORO
t AX to tl NTRO
~CS to tORO
~CS to tlNTRO
tRWC to ~NOM
t2XOR to tEARLY
t2XOR to t NOM
t2XOR to t LATE

150

nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec

120
120
145
160
145
180
145
115
115
115

=

o

NRZ

UNIT

50
50

NOTES: 1. Typical Values are for TA 25°C (77°F) and Vcc

WCLK

MAX

2

3

o~o

"Per
"Per
"Per
"Per
"Per
"Per

Figure
Figure
Figure
Figure
Figure
Figure

5"
7"
8"
7"
8"
6"

"Per
"Per
"Per
"Per
"Per
"Per

Figure
Figure
Figure
Figure
Figure
Figure

6"
6"
4"
4"
4"
4"

:E

c
......
......
o
o

.!..
N

= + 5.0V.
5

4

6

7

t
~1__ •t-tOH
____________~D~S_~~

o

CONDITION

o

o

I

o

1

I

t

11

r;::,
~
n
L..JCL-...J0U I

r·-~
I

MFM

-- Icl
I

I

rcl

EARLY

..

-::-tTN

u

NOM

LATE

tRN~

.

U

:-tTE

I

u-uII

-,~tTL

IcI

I
.-

~

RWC

Figure 4. WD1100·12 MFM GENERATOR TIMING

Winchester Disk Controller Devices

3-105

=E
c
.....
.....
o
o

.!r.
N

FigureS

--.ttoo I-OROCLK~
-ORO ~rtoo
Figure 7

3-106

I

Flgure6

INTRO
Figure 8

Winchester Disk Controller Devices

WESTERN

c

o

R

P

0

DIGITAL
o

RAT

N

:E
cI\)

WD2010-05 Winchester Disk Controller

o
oI
o
en
~

FEATURES

•
•
•
•
•
•
•
•
•
•
•
•

BCS

COMPATIBLE WITH MOST MICROPROCESSORS
VIA AN 8-BIT DATA BUS
DATA RATE OF 5 MBS
MULTIPLE SECTOR READ AND WRITE
COMMANDS
FORMATTING AND SECTOR INTERLEAVE
CAPABILITY
SEEK COMBINED WITH READ AND WRITE
COMMANDS
SINGLE OR MULTIPLE SECTOR BUFFER USING
FIFO OR RAM/COUNTER
BUFFER ACCESS VIA PROGRAMMED I/O OR
DMA
32-BIT ECC OR 16-BIT CRC SELECTED BY
SOFTWARE
SECTOR LENGTH OF 128, 256, 512,1024 BYTES
SELECTED BY SOFTWARE
PROGRAMMABLE RETRY ALGORITHM
CAPABLE OF CORRECTING ERRORS WHEN A
SECTOR BUFFER IS USED
5 OR 11 BIT CORRECTION SPAN SELECTED BY
PROGRAM

The WD2010 has three possible alternatives in handling an error during a Read operation:
A. It may be directed to correct the data in the Sector Buffer automatically, providing the Host with
good data.

RD

MR
RE

BDRQ

WE

DRUN
RWC

BRDY

AO
31
30
29

A1
A2
D7

28

D6
D5

SC
TKOOO

WF
INDEX
DRDY
STEP

25

DIRIN
WCLK

24

WG

D4

D3
D2
D1
DO

21

VSS

DIP PIN DESIGNATION

The WD2010 Winchester Disk Controller is a single
chip device designed for use with the Shugart
Associates SA1000 and Seagate Technology ST506
8" and 5.25" disk drives. The WD2010-05 is software
compatible with the WD1010-05 and reads or writes
at a rate of 5 Mbits.

The WD2010 generates counter control signals to
minimize external gating, and hand shake signals to
control DMA operation for multiple sector transfers.
A 32-bit ECC (Error Correction Code) polynomial or
a 16-bit CRC are selectable.

SDHLE

CS

DESCRIPTION

The WD2010 operates with an external buffer such
as WD1510 128X9 FIFO memory or a combination of
a 256X8 static RAM and an 8-bit resettable counter,
or a DMA controller. Data bytes are transferred to and
from the buffer every 1.6 J.lsec. Transfers from the buffer to the CPU are made via programmed I/O or DMA.

INTRQ

VCC
RCLK
RG

BCR

BD
~
~DS?W
RRR
0
DRTRC
DUWSOWEDEI L
Y N C. C 0 F X Y P N K

BORQ
RO

NC

RG
RCLK
Vee

EARLY
LATE

WG

WO

BCS
BCR
INTRQ
SOHLE

Vss

DO
01
02
03

NC
NC

04

MR

R we

A A ADD D N
EES012765C

QUAD PIN DESIGNATION

B. Supply the Host with the error location and pattern, allowing the Host to correct the error.
C. Take no action other than setting the error flag
and letting the Host do the entire error correction
process.

Winchester Disk Controller Devices

The WD2010 is a TTL compatible 40 pin DIP or 44 pin
QUAD NMOS device requiring a single\ + 5V supply.

3-107

PIN DESCRIPTION

=e

c
I\)

PIN
NUMBER

MNEMONIC

110

FUNCTION

BUFFER CHIP
SELECT

o

BUFFER
COUNTER RESET

o

INTERRUPT
REQUEST

o

SOH

o

5

LATCH
ENABLE
MASTER RESET

6

READ ENABLE

I/O

When asserted it enables reading or writing the
external Sector Buffer as well as controlling bus
switching.
BCR is asserted prior to read and write
functions and at the completion of a command.
BCR is not used if the Sector Buffer is a FIFO.
INTRQ is asserted upon completion of a command and remains that way until the Status
Register is read or a new command is written into
the Command Register. This signal may be programmed by a Read Command to occur with
BDRQ and DRQ.
SDHLE is asserted when the SDH Register is to
be written into by the Host. (See Figure 3.)
When asserted MR initializes all internal logic
except Task File.
Tri-state, bi-directional signal. RE is an input
when reading the Task File, and an output when
reading the Sector Buffer.

7

WRITE ENABLE

I/O

Tri-state, bi-directional Signal. Used as an input
when writing to the WD2010 Task File. Used as
an output when the WD2010 is writing to the Sector Buffer.

B

CHIP SELECT

I

ADDRESS 0
thru
ADDRESS 2
DATA 7
thru
DATA 0
GROUND
WRITE DATA

I

CS must be asserted to read from or write to the
WD2010 Task File.
Provide the address of the register within the Task
File that is to transmit or receive on the data bus.

o
...a.
o
o

BCS

SIGNAL NAME

I

CJ1

2
3

INTRQ

4

9

AO

thru
11
12
thru

thru
A2

D7
thru

19

DO

20
21

Vss
WD

I

I/O

o

22

o

23

o

24

WG

WRITE GATE

o

25

WCLK

26

DIRIN

WRITE CLOCK
DIRECTION IN

o

3-108

I

B-bit, tri-state, bi-directional bus used for the
transfer of commands, status, and data.
Ground
WD is the MFM data to be written to the disk. The
frequency is controlled internally by WCLK and
should be stabilized further externally by a D flip
flop clocked at twice the WCLK frequency. The
output has an active pullup and pulldown that can
sink 6.0ma.
This signal is used in the Write Precompensation
circuitry along with EARLY to control the delay
of WD.
This signal is used in the Write Precompensation
circuitry along with LATE to control the delay
of WD.
WG is asserted when valid data is to be written.
It enables write current to the head and is
immediately de-asserted if a Write Fault (WF) is
detected.
A 5 MHz clock used internally to control WD.
This signal determines the direction of the
read/write heads when stepped. Asserted moves
them in; de-asserted, out.

Winchester Disk Controller Devices

PIN DESCRIPTION (cont.)
PIN
NUMBER
27

MNEMONIC
STEP

SIGNAL NAME
STEP PULSE

::e

1/0

FUNCTION

0

This signal is used for pulsing the stepping motor.
(See Stepping Rate Description.)

28

DRDY

DRIVE READY

I

DRDY must be asserted to execute any drive related
commands.

29

INDEX

INDEX PULSE

I

The leading edge of this signal indicates that the
index mark has been detected.

30

WF

WRITE FAULT

I

When asserted, indicates a write error at the drive.
This halts all write, read, and stepping commands.

31

TKOOO

TRACKOOO

I

This signal is asserted when the read/write heads
are positioned over track 0 (cyI.OOO). It is used to
verify proper completion of a restore command.

32

SC

SEEK COMPLETE

I

The leading edge of SC indicates that the drive has
settled down after stepping. It is static tested if the
rising edge has not been received within 10 revolutions after the stepping pulses.

33

RWC

REDUCE WRITE
CURRENT

0

RWC can be programmed to reduce the write current starting at a selected cylinder. (See Write
Precomp Cylinder Register.)

34

DRUN

DATA RUN

I

DRUN informs the WD2010 when a field of all ones
or zeros has been detected. (See Drive Interface.)

35

BRDY

BUFFER READY

I

When asserted, the Sector Buffer is full or empty.

36

BDRQ

BUFFER DATA
REQUEST

0

BDRQ represents the same state as DRQ (bit 3 of
the Status Register). This signal is asserted when
the Sector Buffer is to be read from or written to
by the Host. BDRQ can be used for DMA or Programmed 110. If DRQ is used it must be polled by
the Host during Programmed I/O.

37

RD

READ DATA

I

MFM data and clocks are received from the drive.
The clocks and data are separated internally.

38

RG

READ GATE

0

RG is asserted when a search for an address mark
is initiated. It remains asserted until the end of the
ID or data field. (See Drive Interface.)

39

RCLK

READ CLOCK

I

This clock is generated by a VCO, phase locked to
data read from the disk.

40

Vcc

+5V

+5 Volts

"ARCHITECTURE
The WD2010 provides the necessary interface control between the Host processor and a 5.25" or 8" Winchester disk drive. The controller is made up of seven
major building blocks connected to the processor via
a Host interface on one side and a drive interface on
the other. Figure 1 illustrates the major sections and
how they relate to each other.

Winchester Disk Controller Devices

The WD2010 timing is controlled by two clock input
signals, RCLK and WCLK. RCLK is used for MFM
decoding and is a 5 Mbitlsec data rate. WCLK is used
for MFM encoding at the same rate as reading, PLA
Controller, Host Interface, and Buffer Control.

3-109

cI\)
o
.....
oI
o

C1I

:E

00-07

C
N
0

~

0
0•
CJ1

WD
WCLK
MAGNITUDE
COMPARATOR

RE

WE
A2-AO
RCLK
INTRQ
MR
CS

PLA
CONTROLLER

STEP
DIRIN

,.

BCR
BRDY
BDRQ
BCS
VCC
VSS

EARLY
LATE

BUFFER
IFC
L------tI~
.. 1

..

DRDY
DRIVE
IFC

WF
TKOOO

•

RWC
WG
RG
DRUN

FIGURE 1. WD2010 BLOCK DIAGRAM
Programmable Logic Array (PLA) Controller
The Command Register, is the last of the Task File
Registers to be written into, and starts the PLA con·
trol. The PLA controller, synchronized by WCL.K, interprets the command, generates control signals, and
operates in a hand shake mode when communicating
with the MFM encoding block.
Magnitude Comparator
The magnitude (number of steps) and direction
required to move the heads from their present cylinder
to their desired cylinder is performed by an 11-bit comparator. It compares the cylinder number recorded in
the Task File (it's desired location) with the Present
Cylinder Position Register recorded internally. From
this, the direction and number of steps that must be
performed to place the head on the desired track is
calculated.
A separate high speed equivalence comparator is
used to compare 10 field bytes when searching for
a sector 10 field.
CRC and ECC Generator and Checker.
The CRC mode of the operation, defined by the SOH
(Sector Size, Head, drive select) Register (Bit 7 = 0),

3-110

provides a means of verifying the accuracy of the data
read from the disk but does not attempt to correct it.
The CRC generator computes and checks cyclic
redundancy check characters that are to be written
to, and read from the disk following the 10 and data
fields. The polynomial used is X 16 + X12 + X 5 + 1. The
CRC Register is preset to all one's before computation starts.
The 10 field always has a 2-byte CRC character
appended to it, while the data field may have either
a 2-byte CRC (SOH 7 = 0) or a 4-byte ECC character
(SOH 7 = 1).
If the CRC character being generated while reading
the data does not equal the one previously written,
an error exists. If there is a CRC failure in the 10 field,
an 10 not found is indicated by bit 4 of the Error
Register being set. If the failure is in the data field,
bit 6 of the Error Register is set.
The ECC mode of operation (SOH 7 = 1) is only
applicable to the data field. This feature built into the
W02010 provides the user with the ability to detect
and correct errors in the data field automatically.

Winchester Disk Controller Devices

A summary of the parameters to be considered when
ECC is desired are:
1. SDH Register bit 7.
2. Read Command bit 0 (1).
3. Read and Write Command bit 1 (L).
4. Compute Correction Command.
5. Set Parameter Command.
6. Error correction successful, bit 2 of the Status
Register.
7. Error occurred, bit 0 of the Status Register.
S. Uncorrectable error, bit 6 of the Error Register.

and Read commands, a diagnostic routine may be
developed to test the accuracy of the error correction process.
MFM Encoding and Decoding

When T = 1, and an error is detected, no attempt is
made to correct it and bit 0 of the Status Register
and bit 6 of the Error Register is set. The user now
has two choices:

The MFM encoder receives its data one byte at a time
from an S-Bit parallel-to-serial register, and with the
frequency of WCLK, develops the MFM WD. Depending on the bit pattern of the data, EARLY or
LATE may be asserted. External circuitry uses
these Signals to compensate for the shift caused by
the influence one bit has over another. The WD2010
examines three bits, the last one written, the one
being written, and the next one to be written. From
this, EARLY or LATE is asserted. Since the bit leaving the WD2010 has already occurred, it is too late
to make it early, therefore the external delay circuit
must be as follows.
EARLY (asserted) and LATE (de-asserted)
no
delay
EARLY (de-asserted) and LATE (de-asserted)
one
unit delay
two
EARLY (de-asserted) and LATE (asserted)
units delay
These signals are not dependent upon the Write
Precomp Cylinder register (RWC). Figure 6 illustrates
one method of using these signals.

1. Ignore the error and make no attempt to correct it.
2. Use the Compute Correction Command to determine the pattern and location of the error, and correct it within the user's program.

The MFM decode operates from RCLK, a bit rate
clock generated from the external Data Separator.
RCLK and WCLK need not be synchronized.
Address Mark (AM) Detection

When the Compute Correction Command is
implemented, it should be done before executing any
command that can alter the content of the ECC
Register. The Read, Write, Scan, and Format commands alter the syndrome and correction is impossible. The Compute Correction Command determines
that the error is uncorrectable, at which point the error
bits in the Status Register and Error Register are set.

An address mark is comprised of two unique bytes
preceding both the ID field and the data field. The first
byte is used for resynchronization. The second byte
indicates whether it is an ID field or a data field.

The SDH register bit 7 must be equal to one to change
from the CRC mode to the ECC mode.
The T bit (bit 0) within the Read Command controls
whether or not error correction is to be attempted.
When T = 0 and an error is detected, the WD2010
tries up to 10 times to correct the error. If successful,
bit 2 of the Status Register is set. The Host can interrogate the Status Register and detect that a problem
does exist, but was corrected. If the error is not correctable, bit 6 of the Error Register is set. The Host
can read the data, even though errors do exist.

Although ECC generation starts with the first bit of
the FS byte in the data ID field, the actual ECC bytes
produced for the sector are the same as if the A 1 byte
was included.
The ECC polynomial used is,
X32+X28+X26+X19+X17 +X10+X6+X2+ 1.
For auto correction the external data buffer must be
implemented with a static RAM and counter, not a
FIFO memory.
The Set Parameter Command is used to select a 5
or 11-bit correction span.
Read and Write Commands, with the L bit (bit 1) equal
to one, are referred to as Readlong and Writelong
Commands. With these commands, no ECC or CRC
characters are generated or checked by the WD2010.
In effect, the 4 ECC bytes are handled as an additional 4 bytes of data which pass through the data
buffer.
With proper use of the Write, Readlong, Writelong,

Winchester Disk Controller Devices

The first byte, A 1 hex, normally has a clock pattern
of OE hex. However, one clock pulse has been suppressed, making it QA hex. With this pattern, the
detector knows it is looking at an address mark. It
now examines the next byte to determine if it is an
ID or data field. If bits 7 thru 2 are 1111X1XX, it is an
ID field (bits 3, 1, and 0 are the high order cyl.#bits).
If the second byte is FS, it is a data field.
Host Interface
The primary interface between the Host processor
and the WD2010 is an S-bit bi-directional bus. This
bus is used to transmit and receive data for both the
WD2010 and the Sector Buffer. The Sector Buffer consists of either a FIFO memory, or a static RAM and
counter. Since the WD2010 makes the bus active
when accessing the Sector Buffer, a transceiver must
be used to isolate the Host during this time. Figure
2 illustrates a typical interface with a Sector Buffer,
implemented with a RAM memory. Whenever the
WD2010-05 is not using the Sector Buffer,it turns control of the Sector Buffer and data bus over to the Host
by de-asserting its output term, BCS. This de-selects
the Sector Buffer and switches the data bus
transceivers.

3-111

=E
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o
-I.
o
o
I

C1I

:E
c

I\)

....

o
o

o•

01

When the Host wants to access the Sector Buffer it
produces an address of zero (AO thru A2 ::f= 0). A
decoder recognizing AO thru A2::f= 0 asse~a BCS
of its own. The Host then asserts WE or RE
for
the counter, at the leading edge, the location within
the Sector Buffer addressed by the counter is
accessed, at the trailing edge the counter advances
to the next count. The decoder asserts CS to the
WD2010 any time the address does not equal zero
(AO thru A2 ::f= 0).
During Write Sector commands the Host sets up data
in the Task File and issues the command. The
WD2010 asserts BCR to zero the counter. It then
generates a status to inform the Host it can load the
Sector Buffer with the data to be written. When the
counter reaches its maximum count, BRDY is
asserted by the carry out of the counter, informing
the WD2010 that the Sector Buffer is full. (BRDY is
asserted with a rising edge and is ignored if asserted
before the WD2010 asserts BCR.) BCS is then asserted, disconnecting the Host through the
transceivers, and RE and WE become outputs from
the WD2010 to allow access to the Sector Buffer.
When the WD2010 is done using the Sector Buffer,
it de-asserts BCS which again allows the Host to
access this local bus.

The Read Sector Command operates in a similar manner, except that the Sector Buffer is loaded by the
WD2010 instead of the Host.
When BDRa is used, it can either be connected to
a DMA controller or used for programmed 110. In either
case it Signals that the WD2010 is ready to receive
or transmit data. DRa status bit, if used, must be
polled by the Host, therefore is limited to programmed
liD.
When INTRa is asserted, the Host is signaled that
a command has terminated (either a normal termination or an aborted command). In the case of the Read
Command, INTRa can be programmed by bit 3 to be
asserted upon termination as the other commands,
or at the same time BDRa is asserted. In either case,
INTRa remains asserted until the Host reads the
Status Register to determine the result of the termination, or writes a new command into the Command
Register.
The WD2010 asserts SDHLE to the Host whenever
the SDH register is being written into. This makes it
possible to store the same information in an external register for decoding. Figure 3 illustrates one
method.

~-4------------------------------~~r----; ~
~-+------------------------------t1~r----;~

DO·D7

WD2010

~---+--~--4---------

~

______6 -_ _

~BCS

.....I~

b----+--~--4----------------------AO·2

l-:t---4·----------+___~--+-------------+...1AO'2

1----------......

1

-------4

BRDY
BDRQ
INTRQ

DMA
CONTROLLER

FIGURE 2. HOST INTERFACE

3-112

Winchester Disk Control/er Devices

Drive Interface

'

arator circuit is illustrated in Figure 4. Data read from
the drive is presented to the RD input of the WD2010,
the reference multiplexor, and a retriggerable one
shot. The RG is de-asserted when the WD2010 is not
inspecting data. The PLL at this time should remain
locked to the reference clock.

The drive side of the WD2010 controller requires
three sections of external logic. These are interface/
Sector Buffers, data separator, and write precompensation. Figure 3A illustrates the drive interface.
The control lines are buffered, single-ended, and
resistor terminated at TTL levels. The data lines to
and from the drive also require buffering, and are terminated with RS-422 drivers. The interface specification for the drive can be found in the manufacturer's
OEM manual. The WD2010 supplies TTL compatible
signals, and interfaces with most driver devices.

When any Read or Write Command is initiated and
a search for an address mark begins, DRUN is
examined. The DRUN one-shot is set slightly longer
than one bit time, allowing it to retrigger constantly
on a field of all ones or all zeros. An internal counter
times out to see that DRUN is asserted for 2 byte
times. RG is asserted by the WD2010 switching the
data separator to lock onto the incoming data stream.
If DRUN is de-asserted prior to 7 byte times, RG is
de-asserted and the process is repeated. RG remains
asserted until a non-zero, address mark is detected.
It then de-asserts RG for two byte times (to allow the
PLL to lock back on the reference clock) and starts
the DRUN search over again. If an address mark is

When the SDH Register is written into, the Head and
Drive select signals are latched externally by the
latch enable signal SDHLE. See Figure 38.
The data recovery circuits consist of a phase lock
loop, data separator, and associated components.
The WD2010 interacts with the data separator through
DRUN and RG. The block diagram of the data sep-

.-__________
00·04

J~\r--a.-------- HSELO

_

J

.------------.y

0

~

Q

T

Q

~

Q

HSEL1
HSEL2

I---

o

f---

E

OSEL 1
OSEL2

C

o
o

-OSEL3

E
-

RG

1----_1

ORUN

1.-----1
1. .- - - - 1
1.-----1

RO
RCLK

OSEL4

DATA
SEPARATOR

W02010

HOST

00·07

~

WO
EARLY
LATE

OATA/CTRLI

1----.1
1-----.1
1-----.1

RWC t--~~

STEP

WRITE
PRECOMPENSATION
AND
SYCHRONIZATION

DISK
DRIVE

t------I~I

OIRIN t------I~I
OROY ~---l
WF
TKOOO
INDEX

..----l
..----l

INTERFACE/
BUFFER

I.--------J

SC

WG

FIGURE 3A_ DRIVE INTERFACE BLOCK DIAGRAM

Winchester Disk Controller Devices

3-113

:E
cI\)
o
o
o

~

I

(J1

:ec

I\)

o
.....

.

o
o
c.n

detected, RG remains asserted and the command
continues searching for the proper ID field. This
sequence is illustrated in Figure 5.
The Write Precompensation circuitry is designed to
reduce the shift in the data caused by the effect one
bit has over another. The Write precompensation logic
is divided into two areas: RWC and Early or Late
writing of the bits. A block diagram of the Write
Precomp circuit is illustrated in Figure 6.
RWC is controlled by the Write Precomp Cylinder

CS

------4.,

WE

------(~~

Register in the Task File. This register is written into
by the Host. When a cylinder is called for that is equal
to, or greater than the content of this register, the
write current will be reduced, thus lessening the effect
one bit can have over another.
Shift may also be caused by the bit pattern. With cer·
tain combinations of ones and zeros some of the bits
can drift far enough apart to become difficult to read
without error. This phenomenon can be minimized by
using EARLY and LATE as described under MFM
Encoder.

AD - - - - - - ( : - 1 1

A 1 ----c~---<
A2

---t)IU---<'~

COMMAND-IN-PROGRESS ---DO---<~

FIGURE 3B. LATCH ENABLE SIGNAL

250 NSEC
RETRIGGERABlE
ONE-SHOT

1-------------4~ DRUN

5MBITS

MFM
RD

DISK
DATA

WD2010

RClK
~--------------------~

RG

~------------1L_=~~r----------~~WClK

FIGURE 4. DATA SEPARATOR CIRCUIT

3-114

Winchester Disk Controller Devices

YES

FIGURE 5. PLL CONTROL SEQUENCE FOR ID FIELD

Winchester Disk Controller Devices

3-115

:ec
N

o
.....

~
en

FIGURE SA. PLL CONTROL SEQUENCE FOR DATA FIELD

3-116

Winchester Disk Controller Devices

:E
WD

D

EARLY

D

I

Q

L
A
T

DELAY LINE

l

Q

C

-

LATE

D

Q~

H

r-- C

I
I I:
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1
SO

3

V

WD2010
WD2010-05

=

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WDTODRIVE

S1,./'"

10 MHz OSC

{»-

RWC

-if

TO DRIVE

FIGURE 6. WRITE PRECOMPENSATION CIRCUIT
TASK FILE

BIT 7 - BAD BLOCK DETECT

The Task File is a bank of nine, a-bit registers used
to hold status information indicating the success or
failure of an operation, as well as the parameters
under which the drive is to operate. They are
addressed by AO through A2 lines. AO through A2 =
o is unused by the W02010 and when received, puts
its bus in the tri-stated condition isolating it from the
bus.

This bit is set when an 10 field has been encountered
that contains a Bad Block Mark. It is used for bad
sector mapping.

ERROR REGISTER (A2 thru AD = 1 READ)
This register contains specific error status pertaining to the completion of a command. These bits are
defined as follows:

7

6

5

4

3

2

1

D

BB

CRC/ECC

0

10

0

AC

TK

OM

BIT 6 - CRC/ECC DATA FIELD ERROR
CRC mode of operation (SOH 7 = 0): this bit is set
when a CRC error occurs in the data field. When Retry
is enabled, ten more attempts are made to read the
sector correctly. If none of these attempts are successful, bit zero in the Status Register is set also. If
one of the attempts is successful, this bit remains
set to inform the Host that a marginal condition
exists. However, the zero status bit is not set. No
attempt is made to correct the error.

TASK FILE

ADDRESS
REAO ONLY

I

WRITE ONLY

A2

A1

AO

0

0

0

0

0

1

0

1

0

Sector Count

BUS TRI-STATED
Error Register

J

Write Precomp Cylinder

0

1

1

Sector Number

1

0

1

0

0
1

Cylinder Low
Cylinder High

1

1

0

1

1

1

SOH Register
Status Register

I

Command Register

NOTE: These registers are not cleared by MR being asserted

Winchester Disk Controller Devices

3-117

=

ECC mode of operation (SOH 7
1). This bit is set
when the first non-zero syndrome is detected. When
Retry is enabled, up to ten attempts are made to correct the error. If successful, this bit remains on.
However, bit 2 of the Status Register is set to inform
the Host that the error has been corrected. If unsuccessful, this bit remains on and bit zero of the Status
Register is set also. When Retry is disabled no
attempt is made to correct the error.
The data may be read even if errors do exist.
Note: If the Long Mode bit is set in the Read or Write
command, no error checking is performed.
Bit 5-Reserved
Not used, forced to zero.
Bit 4-10 Not Found
This bit is set to indicate that the correct cylinder,
head, sector, or size parameter could not be found,
or a CRC error occurred on the 10 field. This bit is
set on the first failure and remains set even if the error
is recovered on a retry. When recovery is unsuccessful, the Error Status bit is set also.
For a Scan 10 Command with retry enabled (T = 0),
the Error Status bit is set after ten unsuccessful
attempts have been made to find the correct 10. With
1) only two attempts are made
Retry disabled (T
before setting the Error Status.
For a Read and Write Command with Retry enabled
(T
0), ten attempts are made to find the correct 10
field. If there is still an error on the tenth try, an autoscan and auto-seek are performed. Then, ten more
tries are made before setting the Error Status. When
the Retry is disabled (T = 1) only two tries are made,
and no auto-scan or auto-seek operations are
performed.
Bit 3-Reserved
Not used, forced to zero.
Bit 2-Aborted Command
The command is aborted and this bit set if, DRDY has
not been asserted, WF is asserted, or the command
issued had an undefined command code.
Bit 1-Track Zero Error
This bit is set during a Restore Command when
TKOOO input has not indicated that the head has
reached track zero by 2047 steps.
Bit 0- Data Address Mark Not Found
This bit is set during a Read Sector Command if the
Data Address Mark is not found following the proper
sector 10.
WRITE PRECOMP CYLINDER (A2 thru AO = 1 write)
This register is used to define the cylinder number
where the RWC output signal is to be asserted.

=

The value OO-FF loaded into this register is internally
multiplied by four to specify the actual cylinder
where RWC is to be asserted. Thus a value of 9C
Hex causes the RWC to be asserted on cylinder 270
Hex, 90 Hex on cylinder 274 Hex, etc. RWC is
asserted when the present cylinder is equal to, or
greater than the value of this register. For example,
the ST506 requires precomp 80 Hex (128 dec.) and
above. Therefore, the write precomp cylinder should
be loaded with 20 Hex (32 dec.).
A value of FF Hex causes RWC to remain de-asserted,
regardless of the cylinder number values.

=

SECTOR COUNT (A2 thru AO
2)
In a muliple sector operation, this register contains
the number of sectors involved with Read Seector,
Write Sector, and Format commands.
I

7

I6 I5 I4 I3 I2 I1

1

°1

The value written into this register is decremented
by one after each sector is transferred to or from the
Sector Buffer. A zero represents a 256 sector transfer,
a 1 = one sector, etc. This register is disregarded
when a single sector command is specified.
SECTOR NUMBER (A2 thru AO
3)
This reigister holds the number of the desired sector.

=

=

76151413121
CYLINDER NUMBER + 4

3-118

0

1

7

I

6

I

.

5 I 4 I 3 I 2
SECTOR NUMBER

I

1

101
.

This is the starting sector in a multiple sector command. It is incremented by one after each sector has
been transferred to or form the Sector Buffer. The
register can contain any value from 0 to 255.
This register also specifies the minimum GAP 3
length, minus 3, during a Format Command.
CYLINDER NUMBER LOW (A2 thru AO
4)
This register holds the least significant 8 bits of the
desired cylinder number.

=

I7

I

6

I

5

I

4

I

3

I

2

I

1

It is used in conjunction with the Cylinder Number
High Register to specify a range of 0 to 2047.
CYLINDER NUMBER HIGH (A2 thru AO
5)
This register contains the three most significant bits
of the desired cylinder number.

=

I

~

I

:

I

~ ~
I

I

;

I

;

I

:

I

~

I

Winchester Disk Controller Devices

These registers determine where the RIW heads are
to be positioned. The Host writes the desired cylinder
number into these registers. Internal to the WD2010
is another pair of registers pointing to where the
heads are presently located. When any command,
other than a Restore, is executed these registers are
compared. The difference between them results in
DIRIN and STEP signaling the drive how many
cylinders to move the heads and in which direction.

A SCAN 10 Command reads the cylinder number from
the track on which the heads are presently located,
and writes this into the Present Cylinder Position
Register.
When a different drive is selected just prior to a Read,
Format, Write, or Seek command, the WD2010 issues
-an auto-scan 10 command. This updates the Present
Cylinder Position Register to reflect the position of
the heads on this drive.

The Present Cylinder Position Register is updated to
equal the cylinder Number Register at the completion of the seek.
When a Restore Command is executed, the Present
Cylinder Position Register is reset to zero, while DIRIN
and STEP move the heads to track zero.
SOH REGISTER (A2 thru AO = 6)
This register contains the desired sector size, drive
number, and head number parameters.
7

65

43

21 0

EXT

SIZE

DRIVE

HEAD

6

5

SECTOR SIZE

4

3

DRIVE #

2

o
o

o

o

o

o
o

1
1

256
512
1024
128

DSEL1
DSEL2
DSEL3
DSEL4

0
0
0
0
1
1
1
1

1

1

1
1

1

o
1

NOTE:
Drive select and head select lines must be generated
externally. Figure 3 represents one method of achieving this.

0
0
1
1
0
0

0

HEAD #

0
1
0
1
0
1
0
1

HSELO
HSEL1
HSEL2
HSEL3
HSEL4
HSEL5
HSEL6
HSEL7

As shown below, the SOH byte written in the 10 field
during the Format Command is not the same as the
contents of the SOH Register.
Bit 7 - One selects the ECC mode for the data field.
Zero selects the CRC mode for the data field.

I

BA~

7

6

5

4

BSY

ROY

WF

SC

3

2

ORa DWC

1

0

CIP

ERR

Bit 7 - Busy

B.

65

43

21 0

SIZE

o 0

HEAD

STATUS REGISTER (A2 thru AO = 7 READ)
The Status Register is used to inform the Host of certain events performed by the WD2010 as well as reporting status from the drive control lines. Reading the
Status Register de-asserts INTRa.

Winchester Disk Controller Devices

BUSY is asserted when a command is written into
the Command Register and, except for the Read Command, it is de-asserted at the end of the comand.
When executing a Read Sector Command, BUSY is
de-asserted when the Sector Buffer is full. Commands
should not be loaded into the Command Register
when this bit is set. When the BUSY bit is set, no
other bits in the Status or Error Register are valid.

3-119

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Bit 6 - Ready
This bit reflects the status of DRDY. When this bit
equals zero, the command is aborted and the status
of this bit is latched.
Bit 5 - Write Fault
This bit reflects the status of WF. When this bit equals
one, the command is aborted, INTRa is asserted, and
the status of this bit is latched.
Bit 4 - Seek Complete
This bit reflects the status of SC. When a seek or
implied seek has been initiated by a command, it
pauses until the seek is complete, This bit is latched
after an "aborted command" error.
Bit 3 - Data Request
DRa reflects the same status as BDRa. It is asserted
when the data Sector Buffer must be written into, or
read from. DRa and BDRa remain asserted until
BRDY indicates that the Sector Buffer has been filled
or emptied, depending upon the command. DRa is
used during Program Interrrupt and must be interrogated by the Host to determine that the WD2010
is ready. BDRa operates through a DMA controller
for data transfers.
Bit 2 - Data Was Corrected
When a one, this bit indicates an error has been
detected during the ECC mode of operation and the
data in the Sector Buffer has been corrected. This provides the user with an indication that there may be
a marginal condition within the drive before the errors
become uncorrectable. This bit is forced to zero when
not in the ECC mode of operation.

Bit 1 - Command in Progress (CIP)
When this bit is set, a command is being excuted and
a new command should not be loaded. Although a
command is being executed the Sector Buffer is still
available for access by the Host. When WD2010 is
no longer busy, (bit 7
0) the Status Register can
be read. An attempt to read the other registers results
in reading the status.

=

Bit 0 - Error
This bit indicates that a non-recoverable error has
occurred. When the Host reads the status and finds
this bit set, it must then read the Error Register to
determine what type of error it was.
COMMAND REGISTER (A2 thru AO = 7 write)
The command to be executed is written into this
register.

I

7

I

6

I

5

I

I

4
3
COMMAND

I

2

I1

o

The command asserts BUSY and CIP, and begins to
exec4te as soon as it is written into this register.
Therefore, all necessary information should be loaded
into the Task File prior to entering the command. Any
attempt to write into these registers is ignored until
the command has terminated, as indicated by the CIP
status. INTRa is de-asserted if it 'is still active at the
time the command is written.

COMMAND SUMMARY·
BIT
COMMAND
RESTORE
SEEK
READ SECTOR
WRITE SECTOR
SCAN ID
WRITE FORMAT
COM PUTE CORRECTION
SET PARAMETER

7
0
0
0
0
0
0
0
0

6

5

4

0
1
0
0
1
1
0
0

0
1
1
1
0
0
0
0

1
1
0
1
0
1
0
0

3
R3
R3
I
0
0
0
1
0

2
R2
R2
M
M
0
0
0
0

1

R1
R1
L
L
0
0
0
0

0
RO,
RO
T
T
T
0
0
S

Stepping Rate Field R3-RO
For 5 MHz WCLK:
1010-5.0msec
R3-RO = 0000-351lsec
0001-.5msec
1011-5.5msec
0010-1.0msec
1100-6.0msec
0011-1.5nsec
1101-6.5msec
0100-2.0msec
1110-3.2Ilsec
0101-2.5msec
1111-161lsec
0110-3.0msec STEP PULSE WIDTH
0111-3.5msec
1.6llsec at 3.2llsec rate
1000-4.0msec
8.0llsec at all others.
1001-4.5msec

=

3-120

Winchester Disk Controller Devices

I - Interrupt Control

I = 0

:E

INTRa occurs with BDRa/DRa
indicating the Sector Buffer is full (valid
only when M = 0).
INTRa occurs when the command is
completed and the Host has read the
Sector Buffer.

M - Multiple Sector Flag

M

0 Transfer one sector (the sector count is
ignored)

M

1 Transfers multiple sectors

L - Long Mode

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RESET INTRO.
ERRORS.
SET BUSY. CIP

RESETRWC
SET DIRECTION
= OUT
STORE STEP RATE

L = 0 Normal mode, normal CRC or ECC functions are performed.
L

=1

Long mode, no CRC or ECC bytes are
developed or error checking performed
on the data field. The WD2010 appends
the four additional bytes supplied by the
Host or disk to the data field.

PULSE BCR
SET AC. INTRO
RESET BSY. CIP

T - Retry Flag

T

=0

Enable Retry

T

=1

Disable Retry

S - Error Correction Span

S = 0 5-bit span
S = 1 11-bit span
RESTORE COMMAND

The Restore command is used to position the
read/write heads over track zero. It is usually issued
by the Host when a drive has just been turned on.
The stepping rate used for the restore is determined
by SC. The WD2010 issues a Step pulse and then
waits for the leading edge of SC before starting
another step. If the leading edge of SC is not seen
within 10 revolutions (index pulses) the WD2010 switches to sensing the level of SC. If after 2047 Stepping pulses TKOOO is not asserted, the WD2010 sets
the Track Zero error bit, asserts INTRa and terminates
the operation. An interrupt also occurs if WRITE
FAULT is asserted or DRDY is de-asserted during
execution.
The stepping rate field is stored in an internal register
for future use by commands with implied seeks.
SEEK COMMAND

ISSUEA
STEP PULSE

By not testing SC, the Seek Command is capable of
overlapping seeks on multiple drives. R3 through RO
controls the stepping rate, as well as being written
into an internal register for use by those commands
with implied seek capability.
FIGURE 7. RESTORE COMMAND

Winchester Disk Controller Devices

3-121

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RESET INTRQ,
ERRORS,
SET BUSY, CIP
STORE STEP RATE

YES

NO

SET ABORTED
COMMAND BIT

FIGURE 8. SEEK COMMAND

3-122

Winchester Disk Controller Devices

The direction and number of step pulses needed are
calculated by comparing the contents of the cylinder
number in the Task File to the present cylinder position number stored internally. After all the steps have
been issued, the present position cylinder number is
updated, INTRa asserted and the command terminated. if OROY is de-asserted or WF is asserted
during the execution of the command, INTRa is
asserted, and the command aborts setting the AC
error.
If an implied seek is performed, the stepping rate for
all but the last step is controlled by R3 through RO.
On the last step the seek continues until the leading
edge of SC is detected.
READ SECTOR
The Read Sector command is used to transfer one
or more sectors of data from the disk to the Sector
Buffer. Upon receipt of this command, the W02010
compares the cylinder number in the Task File with
the Present Cylinder Position Register. From this, the
direction and number of steps required for the seek
are calculated. As stated in the Seek Command, if
an implied seek is performed, the stepping rate for
all but the last step is controlled by R3 through RO.
On the last step the seek continues until the leading
edge of SC is detected.
If the W02010 detects a change in the drive number
since the last Read Command, an Auto Scan 10 is
performed. This updates the Present Cylinder Position Register to reflect the current drive before the
seek begins.
After the W02010 senses SC (with or without an
implied seek) it must find an 10 field with the correct
cylinder, head, sector size, and CRC. With Retry
enabled (T
0), ten attempts are made to find the
correct 10 field. If there is still an error on the tenth
try, an auto-scan and auto-seek are performed. Then,
ten more tries are made before setting the 10 Not
Found Error. When Retry is disabled (T = 1) only two
tries are made, and no auto-scan or auto-seek operations are performed.
When the Oata Address Mark is found the W02010
is ready to transfer data into the Sector Buffer (if after
successfully reading the correct 10 field the Oata
Address Mark is not found a OAM error is set). When
the disk has filled the Sector Buffer, the W02010
asserts BORa and ORO and then checks the I flag.
If the flag is 0, INTRa is asserted also, signaling the
Host to read the content of the Sector Buffer. If the
I flag is 1, INTRa occurs after the Host has read the
Sector Buffer and terminated the command.
An optional M flag can be set for multiple sector
transfers. When M = 0, one sector is transferred and
the sector count is ignored. When M = 1, multiple
sectors are enabled. After each sector is transferred,
the W02010 decrements the sector count and
increments the sector number. The next logical sector is transferred, regardless of the interleave. Sectors are numberd by a byte in the 10 field during the
Format Command.

=

Winchester Disk Controller Devices

For the W02010 to make multiple sector transfers to
the Sector Buffer, the BROY signal must toggle from
low to high for each sector. The sector transfers continue until the sector count equals zero. If the sector
count is not zero ( indication more sectors are to be
read) and the Sector Buffer is full, BORa is asserted
and the Host must unload the Sector Buffer. Once
this occurs, the Sector Buffer is free to accept the
next sector.
WF and OROY are monitored throughout the command. If WF becomes asserted, or OROY de-asserted,
the command terminates and the AC error flag is set.
For a description of the error checking procedure on
the data field see the explanation under CRC and ECC
Generator and Checker. Both the Read and Write
commands feature a simulated completion to ease
programming. BORa, ORO, and INTRa are generated
in a normal manner upon detecting an error condition. This allows the same program flow for successful or unsuccessful completion of a command.
When M = 0 (Single Sector Read)
(1)
Host: Sets up parameters; issues Read
Sector command.
(2)
2010: Finds sector specified; asserts
BCR and BCS. Sector Buffer data
transfer via WE.
(3)
2010: Asserts BCR de-asserts BCS.
(4)
2010: Asserts BORa and ORO flag.
(5)
2010: If 1 bit = 0 then (8).
(6)
Host: Reads conten12...of Sector Buffer
(by asserting RE).
(7)
2010: Waits for BROY the asserts
INTRa; End.
(8)
2010: Asserts INTRa.
(9)
Host: Reads conten12...of Sector Buffer
(by asserting RE);End.
When M = 1 (Multiple Sector Read)
(1)
Host: Sets up parameters; issues Read
Sector command.
(2)
2010: Finds sector specified; asserts
BCR and BCS. Sector Buffer data
transfer via WE.
(3)
2010: Asserts BCR; de-asserts BCS.
(4)
2010: Asserts BORa and ORO flag.
(5)
Host: Reads conten12...of Sector Buffer
(by asserting RE).
(6)
Sector Indicates data has been transferBuffer: red by asserting BROY.
(7)
2010: When BROY is asserted,
decrements
sector
count;
increments sector number, go to
(9) if sector count = O.
(8)
2010: Go to Step (2).
(9)
2010: Asserts I NTRO; End.

3-123

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*If T bit of command = 1 then dashed path is taken
after 2 index pulses.
• * If T bit of command = 1 then test is for 2 Index
Pulses.

FIGURE 9. READ COMMAND

3-124

Winchester Disk Controller Devices

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(J1

YES

SET ERROR IN
STATUS REGISTER
(BITO)

til T bit 01 command
• ·11 T bit 01 command
Pulses.

= 1 then dashed path is taken .
= 0 then test is lor 2 Index

PULSE BeR
DE·ASSERT CIP

FIGURE 9. READ COMMAND (Continued)

Winchester Disk Controller Devices

3-125

WRITE SECTOR

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The Write Sector Command is used to write one or
more sectors of data from the Sector Buffer to the
disk. Upon receipt of this command, the WD2010 compares the cylinder number in the Task File with the
present position cylinder number. From this, the direction and number of steps required for the seek are
calculated. As stated in the Seek Command, if an
implied seek is performed, the stepping rate is controlled by R3 through RO. After the last step the
WD2010 waits until the leading edge of SC is received.
If the WD2010 detects a change in the drive number
since the last Write Command, an auto-Scan ID takes
place. This updates the Present Cylinder Position
Register to reflect the current drive before the seek
begins.
After the WD2010 senses SC (with or without an
implied seek), BDRa and DRa signals are asserted
and the Host proceeds filling the Sector Buffer. When
BRDY is asserted, a search for an ID with the
specified cylinder, head, sector size, and CRC is
initiated. If the ID is not found and Retry is enabled
(T = 0), ten attempts are made to find the correct ID
field. If there is still an error on the tenth try, an autoscan and auto-seek is performed. Then ten more tries
are made before setting the Error Status bit. (The ID
Not Found error is set on the first failure). When Retry
is disabled (T
1). Only two tries are made and no
auto-scan or auto-seek operations are performed.

=

When the correct ID is found, WG is asserted and
data is written to the disk. When SDH 7 bit is zero,
WD2010 generates a two byte CRC character to be
appended to the data. When SDH 7 bit is one, four
ECC bytes replaces the CRC character. When the L
bit within the Write Command is one, the polynomial
generation of the data is inhibited, and neither CRC
or ECC bytes are generated. Instead, four bytes of
data supplied by the Host is written.

Summary of a write sector operation:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)

Host: Sets up parameters; issues write
sector command.
2010: Asserts BDRa and DRa.
Host: Loads Sector Buffer with data (by
asserting WE) .
2010: Waits for leading edge of BRDY.
2010: Finds specified ID field, write to
sector.
2010: If M = 0, assert INTRa; End.
2010: Increments sector number,
decrements sector count.
2010: If sector count = 0, assert INTRa;
End.
2010: Go to (2).

SCANID

The Scan ID Command is used to update the head,
sector size, sector number, and cylinder registers.
When the first ID field is encountered, the ID information is loaded into the SDH cylinder, and sector
number registers in the Task File. The Present Position Cylinder Register is also updated. If this is an
Auto- Scan caused by a change in drive numbers, only
the present position cylinder number is altered.
If the ID field is not found and Retry is enabled (T = 0),
ten attempts are made to read it. If Retry is disabled
(T = 1), only two tries are made. There is no implied
seek in this command and the Sector Buffer remains
unchanged. When DRDY is de-asserted or WF
asserted the command aborts and the appropriate
error flags are asserted.

During a multiple sector write operation (M flag =
1), the sector number is incremented and sector count
decremented. If BRDY is asserted after the first sector is read from the Sector Buffer, WD2010 continues
to read data from the Sector Buffer for the next sector. If BRDY is de- asserted, WD2010 asserts BDRa
and waits for the Host to place data in the Sector
Buffer.

3-126

Winchester Disk Controller Devices

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* If retries disabled then dashed

path is taken after 2 Index Pulses.

FIGURE 10. WRITE COMMAND

Winchester Disk Controller Devices

3-127

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DE-ASSERT: INTRQ,
ERRORS
ASSERT: Clp, BSY

en

NO

YES

NO

UPDATESDH,
CYL, SECTOR,
CYL POS, REG'S

YES

* If retries are disabled, path

is taken after 2 index pulses.
YES

NO

PULSEBCR
ASSERT INTRQ
DE-ASSERT BSY, CIP

FIGURE 11. SCAN 10 COMMAND

3-128

Winchester Disk Controller Devices

FORMAT

The Format Command is used to format one track
using the Task File and Sector Buffer. During this
command the Sector Buffer contains additional
parameter information instead of data. Figure 12
shows the contents of the Sector Buffer for a 32 sector track format with an interleave factor of two.
Each sector requires a two byte sequence. The first
byte designates if a Bad Block Mark is to be recorded in the ID field. A 00 is normal; an 80 Hex is a
Bad Block Mark. In the example of Figure 12, sector
04 gets a Bad Block Mark recorded. The second
byte indicates the logical sector number to be recorded. Using this scheme, sectors can be recorded
in any interleave factor desired. The rest of the Sector Buffer is filled with any value, BRDY is asserted,
and the WD2010 begins formatting the track.
The Sector Count Register holds the total number of
sectors to be formatted, while the Sector Number
Register holds the number of bytes, minus three, to

be used for Gap 1 and Gap 3. For instance, if the
Sector Count value is 2 and the Sector Number
value is 3, then 2 sectors are written and 6 bytes of
4E Hex are written for Gap 1 and Gap 3. The data
fields are filled with FF Hex, and the CRC or ECC is
generated as specified by the related coding.
The Gap 3 value is determined by the drive motor
speed variation, data sector length, and the interleave
factor. The interleave factor is only important when
1:1 interleave is used. The formula for determining the
minimum Gap 3 is:
Gap 3 = 2 X M X S
M =
S =
K =
K =

+ K

motor speed variation (e.g ..03 for ± 3%)
sector length in bytes
18 for an interleave factor of 1
0 for any other interleave factor

When WF is asserted or DRDY de-asserted the command terminates and the AC error is asserted. Figure
13 shows the format that is written on the disk.

DATA
ADDR

0

1

2

3

4

5

6

7

00
08
10
18
20
28
30
38
40

00
00
80
00
00
00
00

00
00
00
00
00
00
00
00
FF

10
12
14
16
18
1A
1C
1E
FF

00
00
00
00
00
00
00
00
FF

01
03
05
07
09
OB
OD
OF
FF

00

FF

00
02
04
06
08
OA
OC
OE
FF

00
00
00
00
00
FF

11
13
15
17
19
1B
1D
1F
FF

FO

FF

FF

FF

FF

FF

FF

FF

FF

00

00
00

FIGURE 12. FORMAT COMMAND BUFFER CONTENTS

Winchester Disk Controller Devices

3-129

=E

c

N

o
.....
o
o

.

U1

REPEATED FOR EACH SECTOR

:E
c
I\)
o
.....

~

oI
o

)"".

(J1

4E

GAPI
4E
(1)

r-

r-IDFIELD~

I
14 BYTES
'00'

A
1

I
D
E
N

C
Y
L

L

0
W

T
I
I
I
I

H
E
A
D

S
E
C'
#

C
R
C
1

C
R
C
2

3 BYTES
00'

,
I

I
WRITE GATE

,,

I

,

I

DRUN~ !I&'~$I/!l]

F
8

USER DATA

2CRC
OR
4ECC

,,
,,

II'

, I:

~I

,

,,
..

I,

'00'

,
I

I

I

I

,

GAP31)
4E
(1)

I

L-

I
I

I

4~

1If

2 BYTES

I

I
I

READGATE~2

A
1

12 BYTES
'00'

DATAFIELD~

fLlOiLmlM

~

I
I
I

,
I

6'1 _ -

________

71

FIGURE 13. FORMAT

ID FIELD
A1 = A 1 Hex with

OA Hex clock
IDENT = Bits 3,1,0 = Cylinder High
FE = 0·255 Cylinders
FF = 256·511 Cylinders
FC = 512·767 Cylinders
FD = 768·1023 Cylinders
F6 = 1024·1279 Cylinders
F7
1280·1535 Cylinders
F4 = 1536-1791 Cylinders
F5 = 1792·2047 Cylinders
HEAD = Bits 0,1,2 = Head Number
Bits 3,4 = 0
Bits 5,6 = Sector Size
00 = 256
01
512
10 = 1024
11 = 128
Bit 7 = Bad Block Mark
Sec#

3-130

= Logical Sector Number

DATA FIELD

A 1 = A 1 hex with OA hex clock
F8 = Data Address Mark; Normal Clock
USER = Data Field 128 to 1024 Bytes
NOTES:

1. GAP 1 and 3 length determined by Sector Number
Register contents during formatting.
2. The decision to assert RG is made 2 bytes after
the start of DRUN.
3. RG de-asserted:
• If DRUN does not last until A1
•

When any part of ID does not match the one
expected.

•

After CRC if correct ID has been read.

4. Write splice recorded on disk by asserting WG.
5. RG is suppressed until after write splice.
6. Not a proper A 1 or F8, set DAM error.
7. Sector size as stated in ID field, plus two for CRC
or 4 for ECC.

Winchester Disk Controller Devices

:E
c
N
o
-.I.
o

6
(J1

FIGURE 14. FORMAT COMMAND

Winchester Disk Controller Devices

3-131

COMPUTE CORRECTION

=E

cI\)
o
o
o

.

...L

C11

The Compute Correction Command determines the
location and pattern of a single burst error, but does
not correct it. The Host, using the data provided by
the WD2010, must perform the actual correction. The
Compute Correction Command is used following a
data field ECC Error. The command initiating the read
operation must specify no Retry. (T = 1).
The Compute Correction Command first writes the
four syndrome bytes from the internal ECC Register
to the Sector Buffer then the ECC Register is clocked.
With each clock, a counter is incremented and the
pattern examined. If the pattern is correctable, the procedure is stopped and the count and patten are written to the Sector Buffer, following the syndrome. The
process is also stopped if the count exceeds the sector size before a correctable pattern is found.

WRITE4
SYNDROME
BYTES TO
SECTOR BUFFER

When the command terminates the Sector Buffer contains the following data:
Syndrome
Syndrome
Syndrome
Syndrome
Error Pattern Offset
Error Pattern Offset
Error Pattern
Error Pattern
Error Pattern

MSB

YES

ASSERT ERROR
(BIT 0 STATUS REG.)
AND ECC ERROR
(BIT 6 ERROR REG.)

LSB

As an example, when the Error Pattern Offset is zero
the following procedure may correct the error. The
first data byte of the sector is eclusive OR'ed with
the MSB of the Error Pattern. , the second byte of data
with the second byte of the Error Pattern, and the third
byte of data with the LSB of the Error Pattern.
If the Sector Buffer count exceeds the sector size,
or the burst is greater than that selected buy the Set
Parameter Command, the ECC/CRC error (bit 6) and
the Error Status bit (bit 0) is set.

WRITE TWO
OFFSET BYTES
TO SECTOR
BUFFER

WRITE THREE
ERROR PATIERN
BYTES TO SECTOR
BUFFER

The WD2010 defaults to a 5-bit correction span if a
Set Parameter Command has not been executed
since the last MR.
SET PARAMETER

This command selects the correction span to be used
by the error correction process. A 5-bit span is
selected when bit zero of the command equals 0, and
11-bit span when 1. The WD2010 defaults to a five bit
span following a Master Reset.
ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS
Vee with respect to Vss (Ground)........... + 7V
Max Voltage on any Pin with
respect to Vss.................-0.5V to + 7V
Operating Temperature..0°C(32°F) to 70 oC(158 oF)
Storage Temperature..-55°C(-67 oF) to + 125°C
(257°F)

3-132

FIGURE 15. COMPUTE CORRECTION COMMAND

Winchester Disk Controller Devices

NOTE:
Maximum limits indicate where permanent device
damage occurs. Continuous operation at these limits

is not intended and should be limited to those conditions specified in the DC Operating characteristics.

=E

c

I\)

DC Operating Characteristics TA
SYMBOL

= 0 °C (32°F) to 70°C(158°F); Vss = OV, Vee = + 5V

CHARACTERISTIC

MIN

MAX

UNIT

....

o
o
o

.

± .25V
CONDITION

(11

= .4 to Vee
= .4 to Vee

IlL

Input Leakage

± 10

IJA

VIN

10L

Output Leakage
(Tristate & Open Drain)

± 10

IJA

VOUT

V IH

Input High Voltage

V IL

Input Low Voltage

VOH

Output High Voltage

V

2.0
0.8

V
V

10

VOL

Output Low Voltage

0.4

V

10

VOL

Output Low Voltage (Pins 21-23)

0.45

V

10
See Note 10

lee

Supply Current

220

rnA

V IH

Input High Voltage

VIL

Input Low Voltage

0.5

V

TRS

Rise and Fall Time

30

nsec

CIN

Input Capacitance

15

pF

2.4

= -1001JA
= 1.6mA
= 6.0mA

All Outputs Open

For Pins 25, 34, 37, 39:
4.6

--J>4"

V

X"-----

Ao. Al. A2 STABLE

AOORESS _ _

.1
I

r+-TASE

-----

I

THLo--..11

F'"

~TeSE~
I
"--------~I~----------------~I~
I
1

~

~
' " ' - - - __

TROR

Y, I .
4 i
)>-----

T R E - - -....

~TOAC~
OB0-7

.9V to 4.2V

TOOH.

------------~

OATAVALIO

HOST READ TIMING
HOST READ TIMING WD2010-05 WC
SYMBOL

= 5 MHz

CHARACTERISTIC

t ASE

Address Setup to RE

t oAe

Data Valid from RE

-

MIN

MAX

UNIT

350

nsec

nsec

100

tRE

Read Enable Pulse Width

.4

10

IJsee

tOOH
t HLO

Data Hold from RE

20

200

nsec

Address CS hold from RE

0

nsec

t ROR

Read Recovery time

300

nsec

tesE

CS Setup to RE

0

nsec

Winchester Disk Controller Devices

CONDITION

See Note 8

3-133

=e
c

AOOR

===>'_______Ao._A_l._A_2S_r._~B_L_E

______

:

----'.......",'-e- +t

N

o
o
o•
en

tSEW

...A.

tAHW

I

pl:;.===t.:tW::E:::R-=~=::; __

~

I

,,~

~tCHW

y.\
~
""",MuSTs.vALIi 1XXX><

tWE

~

I
,..--tos

I

OB0-7

i

X----

~------+--«

1......I-------tRR

/

"" _ _ _ _..1

~~i
• ,
'+--

DATA VALID

H

J....- - - -

-------I.~I

BUFFER WRITE TIMING
BUFFER WRITE TIMING (READ SECTOR CMD) WD2010-o5 WC
SYMBOL

CHARACTERISTIC

MIN

TYP

tWEV

WE float to WE'Valid

tWRB

WE Output

0
300

400

tVWE

Data Valid from WE

tHWE

Data Hold from WE

tRR

WE Repetition Rate

tWF

WE Float from BCS

3-134

Pulse Width

60
1.2
0

1.6

= 5MHz
MAX

100
500
150
200
2.0
100

CONDITION

UNiT
nsec
nsec

C l = 50 pf
See Note 4

nsec
nsec

J.lsec
nsec

Cl

= 50 pf

Winchester Disk Controller Devices

=E

c

N

o
.....

oI
o

RE
(OUTPUT)

CJ1

BUFFER READ TIMING

BUFFER READ TIMING (WRITE SECTOR CMD) WD2010-05 WC
SYMBOL

tREY
tREB
tROS
tRR
tRF
tHRE

DRUN

MIN

CHARACTERISTIC

RE float to RE Valid
RE Output Pulse Width
Data Setup to RE
RE Repetition Rate
RE Float from BCS
Data Hold from RE

0
300
140
1.2

-

=

5MHz

TYP

MAX

UNIT

400

100
500

nsec
nsec
nsec
JAsec
nsec
nsec

1.6

2.0
100

0

--------------------------------------------------~

CONDITION

CL = 50 pf
See Note 4

CL = 50 pf

~tDRN./'

,-------

READ DATA TIMING
READ DATA TIMING WD2010-05WC
SYMBOL

=

5 MHz

CHARACTERISTIC

MIN

TYP

MAX

UNIT

CONDITION

95

2000

nsec

50% Duty Cycle

t RCP

RCLK Pulse Width

tX1

RD from RCLK Transition

0

tX2

RD to RCLK Transition

20

t RCP
t RCP

nsec

t RCP

nsec

tRO

RD Pulse Width

40

tORN
t RCF

DRUN Pulse Width

30

RCLK Frequency

Winchester Disk Controller Devices

.250

nsec

nsec
5

5.25

MHz

See Note 6

3-135

two --.j

I

=E

wo

c

I

N

o
......

oI
o

(J1

I

- - - - ,...
WCLK

I...--

'-0--: Jfr~~----~~~____________________________~!~~~------~,,~______
I
I •

I

~

I I

~two

tWC::a:~

I

lj;:

t---\~_..Jt,~--',
-

tWCF ----.....~!

LATE \ ' -____________

I

I

--J/~------------- --.l

_____if
-l

: - 'WLE
I

EAR~ ----------------------------------------~\L~

_____________

..J

WRITE DATA TIMING
WRITE DATA TIMING WD2010-05WC = 5 MHz
SYMBOL

CHARACTERISTIC

MIN

TYP

MAX

UNIT

CONDITION

50% Duty Cycle

twc

WCLK Pulse Width

95

2000

nsec

two

Propagation Delay
WCLK to WD

10

65

nsec

tWLE

WCLK to Leading
EARLY/LATE

10

65

nsec

tELW

WCLK to Trailing
EARLY/LATE

10

65

nsec

t WCF

WCLK Frequency

.250

5.25

MHz

3-136

5

See Note 6

Winchester Disk Controller Devices

R

BRDY

I

L..J
I

I

~.
,.

~tMR ~MRW.J

MR

~
tBCR~

WCLK

rtlDX~

RCLK

FRC

I

MISCELLANEOUS TIMING

MISCELLANEOUS TIMING
MISCELLANEOUS TIMING WD2010-05
SYMBOL

CHARACTERISTIC

MIN

TYP

MAX

UNIT

CONDITION

BORO Reset from BROY

20

200

nsec

Buffer Counter Reset
Pulse Width

1.4

1.6

1.8

""sec

Step Pulse Width

1.4
7.8

1.6
8.0

8.2
8.2

""sec

tlDX

Index Pulse Width

500

tMR

Master Reset Pulse

24

WC

See Note 3

t BRy

BROY Pulse Width

400

nsec

See Note 5

tMRB

MR Trailing to BCR

o

tMRW

MR TraUing to Host Write

6.4

See Note 2

nsec

3.2

6.4

""sec
""sec

NOTES:

1. AC timing measured at VOH = 2.0V, VOL = 0.8V,
C L = 50 pf.
2. 1.6 ""sec. is typical pulse for a step rate of 32
""sec/step. 8.0 ""sec typical pulse for all other step
rates. Last step pulse at 3.2 ""sec/step rate up to
8.2 ""sec.
3. 24 WCLK periods (4.8 ""sec at 5.0 MHz)

7. 2 WCLK ± 50 ns.
8. RE may precede CS if CS plus RE meets the
tRE width.
9. WE may precede CS if CS plus RE meets the
tWE width.
10. It may be desirable to connect a 1 K Q pullup
resistor to pins 21-23.

4. 2 WCLK ± 100 ns.
5. The true to false transition of BROY should not
come sooner than 2 WCLK from true to false transition of BORO.

6. t RCF = tWCF ± 15%.

Winchester Disk Controller Devices

N

•

~ tMRB~

I
I.

=E

C

0
...r.
0

I

BCR

FtSTP~

STEP

INDEX

cs.~

~tRQ"

BDRQ

BCR

ItBRY=\l...

3-137

0
U'I

3-138

Winchester Disk Controller Devices

WESTERN
COR

P

0

DIGITAL
o

RAT

N

WD10C20-05 Self-Adjusting Data Separator
FEATURES

•
•
•
•
•

•

PROCESSES ALL SENSITIVE READIWRITE DATA
SIGNALS
CMOS TECHNOLOGY
DESIGNED FOR ST506/ST412 AND WD10101
WD2010 INTERFACE
HIGHLY STABLE LC TYPE VOLTAGE
CONTROLLED OSCILLATOR
SELF ADJUSTING VCO COMPENSATES FOR
COMPONENT, TEMPERATURE, VOLTAGE, AND
AGING VARIATIONS
FREQUENCY DETECTION ON CRYSTAL
REFERENCE AND DATA SYNCHRONIZATION
FIELD, ELIMINATES 180 DEGREE LOCK DUE TO
DRIVE ASYMMETRY, AND ELIMINATES
HARMONIC LOCK FROM WP.ITE SPLICES

•

ZERO PHASE STARTUP PROVIDES FASTER,
MORE PREDICATABLE LOCK ACQUISITION

•

LOCKS TO CRYSTAL REFERENCE WHILE IDLE

•

ADJUST

IPUMP

Vss

VCOOUT

WGATE

VCOIN

RGATE

PUMP

WPCEN

VCC

LATE

RCLK

EARLY

RDATA

WDATA

TLATE

WCLK

THALFWIN

XTALIN

TEARLYZP

XTALOUT

DLYDR
TNOMINAL

DRUN

WMFM

DRUNRC
RMFM

TFULLWIN

T
H

A

DUAL GAIN: HIGH FOR FASTER ACQUISITION
LOW FOR MORE JITTER
REJECTION WHILE TRACKING

•

E

A

T

L

R

D

L

F

L

V

C

A

A

W

Y

L
K

T

T

I

Z

A

E

N

P

R
P
U

T

EXTERNAL PUMP CURRENT CONTROL

M

C

•

AVAILABLE IN 28-PIN DIP OR QSM PACKAGE

P

C

•

INTEGRATED CRYSTAL OSCILLATOR

•

ACCOMMODATES OTHER DATA RATES
THROUGH SELECTION OF EXTERNAL
COMPONENTS

25 24

Z}

R

22 21 20 19

VCOIN

1B

DLYDR

VCOOUT

17

TNOMINAL

IPUMP

16

WMFM

ADJUST

15

TFULLWIN

VSS

14

RMFM

WGATE

13

DRUNRC

12

DRUN

RGATE

5

6

7

B

9

10 11

~ I~E ~ ~ ~ :
E

L

T

N

Y

A

K

:

L

L

I

0

N

U
T

PIN DESIGNATION

Winchester Disk Support Devices

4-1

DESCRIPTION

:E
c

...&.

o

(')
I\)

o

The WD10C20-05 is an LSI device implemented in 3
micron high-speed CMOS, designed to be compatible with the WD1010 and WD2010 Winchester Disk
Controllers and ST506/ST412 disk drives. In a typical
application, it handles all sensitive read/write signals
between a WD1010/WD2010 and the data
drivers/receivers. Read data corresponds to previous
write data, with added phase, frequency, and write
splice noise. The WD1OC2Q..05 removes these sources
of noise and presents a clean, digital read signal to
the WD10101WD2010.
While reading, the WD10C20-05 performs phaselocked loop data synchronization on data read from
the drive. An on-board Sync Field detector
automatically switches the PLL from the stable
crystal reference to the read data. Zero-phase startup results when the VCO is halted and restarted in
phase with the data to eliminate initial acquisition in
the wrong frequency direction. Frequency-phase
detection is used at the beginning of the Sync Field
to quickly and reliably acquire lock to the data. Use
of this technique eliminates susceptibility to harmonics and asymmetry. The WD10C20-05 then switches to phase-only detection to complete the phase
acquisition before the end of the Synch Field and to
enable tracking of random MFM read data. When
switching to phase detection, the WD10C20-05
reduces the error amplifier gain for better rejection
of drive jitter. A precisely aligned detector samples
the data at twice the underlying data rate to remove
the phase jitter. The regenerated signal, along with
a fixed-phase synchronous clock, are output to the
WD1010IWD2010 digital circuits.

4-2

While writing, the WD10C20-05 conditions the write
data to the drive. MFM data from the WD1 01 01WD201 0
is precisely clocked, with a Signal at twice the data
frequency, to minimize digital phase noise. If
precompensation is enabled, early, nominal, and late
taps on an external delay line are multiplexed through
matched delay paths to produce synchronized,
precompensated write data, which is sent directly to
the drive's write circuits.
The WD1OC2Q..05 is designed to work at the 5 Mbitlsec
data rate of the ST506/ST412 interface. Other data
rates may be accommodated through the proper
selection of external components.
NOTE: To assure reliable operation of the
WD10C20-05, it is recommended that the
WD10C20-05 KIT, number 77-000014 be used.
If the user elects to not use the kit, the external components as shown in Figure 1, must
be selected from the parts listed in the
WD10C2Q..05 Application Note. The placement
of these components must conform to the
layout illustrated in the Application Note. (The
Application Note is available through your
Western Digital field representative.)

Winchester Disk Support Devices

+5V

+ 12

•
I

.. ~ R101
.. ~

;~

11101

+e", te",

FERRITE BEAD

R102
AAA

24

28

t

TAS.

......
R104

ADJUST
U101
WD10C20

"""
AAA

1

VCC

IPUMP

PUMP

25

4e",

ie,,,

R106
AAA

CR102

r----.t ~-~

...

I
I
I
I
I
I

.. ~

1

•••

""J--

111""1

:;::: : : C111
13

DRUNRC

e,"

:;::: ;::: C112

18

~

?

~

R107

:;:::~ C110

12

VCOIN

24

::: r:: C113

36
GND 60
DELAY
96
LINE

12

19

4

17

10

21

6

20

8

T

15

~

:::r:

C109

DLYDR
26

t

U102

VCC

R103

... ~
CR101

TEARLYZP
TNOMINAL

VCOOUT

27

R105
AAA

102
L

1

vvv

T

t

TLATE
THALFWIN
TFULLWIN

11

C108

XTALOUT

22
12
23
9
4
WD~01O

WD2010

3

~* ~
6
7

RDATA

Y101

DRUN

XTALIN

10

+e,~

RCLK
WCLK
RGATE

JOI
I
I

~

WGATE
WPCEN
LATE

C105

14

EARLY

RMFM

8
WDATA
WMFM

16

GND

D
R
I
V
E

~
'RWC CONNNECTS TO WPCEN IF REDUCED WRITE CURRENT IS TO START AT THE
SAME TIME AS WRITE PRECOMP. THE WD1002S·WX2 USES LS/DIRlWPC.

FIGURE 1. EXTERNAL COMPONENTS

Winchester Disk Support Devices

4-3

=E
c....

RMFM

o

I

o

SYNC FIELD

I\)

DETECTOR

o

DRUN

,'"

,

J

RGATE

J

WGATE

~

t

+ +

T

STEERING
CONTROL

II

WCLK

I

'~"
~
,~

WDATA
WPCEN
EARLY
LATE

I

I

PLL "UX

Y

I

PHASE
FREQUENCY
DETECTOR

•J

FILTER

t

I
I

VCO

t

VCOOUT

,..

-

VCOIN1'.

t

+
WRITE
DATA
CONDITIONER

~

t

I
I

-

PUMP ~

CHARGE
PUMPS

ZERO PHASE
STARTUP

ADJUST

SELF·ADJUST
CIRCUIT

1

I

CRYSTAL
OSCILLATOR
AND CLOCK
GENERATOR

.

POWER·ON
RESET

PRECOMPENSATION
MUX

I
I

WMFM

DLYDR

t
TEARLYZP
DELAY
AND
PULSE
FORMER

TNOMINAL
TLATE

II

THALFWIN

READ DATA
DETECTOR

I

RDATA
RCLK

I--

I

FIGURE 2. WD10C20 BLOCK DIAGRAM

4-4

Winchester Disk Support Devices

PIN DESCRIPTION

PIN
NUMBER
1
2
3

MNEMONIC
ADJUST
VSS
WGATE

SIGNAL NAME
ADJUST
GROUND
WRITE GATE

4

RGATE

READ GATE

I

5

WPCEN

WRITE
PRECOMP
ENABLE

I

6

LATE

LATE

I

7

EARLY

EARLY

I

8

WDATA

WRITE DATA

I

9

WCLK

WRITE CLOCK

a

10

XTALIN

XTALIN

I

11

XTALOUT

XTALOUT

a

12

DRUN

DATA RUN

a

13

DRUNRC

DRUNRC

I

14

RMFM

READ MFM
DATA

I

15

TFULLWIN

TFULLWINDOW

I

16

WMFM

a

17

TNOMINAL

WRITE MFM
DATA
TNOMINAL

Winchester Disk Support Devices

1/0

a
I

I

FUNCTION
Provides self calibration of the PLL.
WGATE is asserted when the controller writes on the
disk.
RGATE is asserted when the controller intends to read
from the disk. RGATE causes the WD10C20-05 to
remain locked onto the incoming data stream.
WPCEN is asserted to enable the EARLY
and
LATE signals from the controller. WPCEN may be
connected to the Reduce Write Current (RWC)
available from the WD1010IWD2010 if Write Precomp
is to occur at the same time as the Reduced Write
Current, or to an independent source if they start at
different times.
Asserted by the Controller to delay the writing of a
bit to the disk.
Asserted by the Controller to advance the writing of
a bit to the disk.
Non-Synchronized and Non-Precompensated MFM
data from the controller to be written on the disk via
WMFM.
WCLK is equal to XTALIN -+- 2 and is used by the controller to generate the data to be written.
XTALIN is a crystal controlled oscillator input used
by a number of internal control functions. Divided by
2 it develops WCLK. XTALIN may also be driven by
an external driver in which case XTALOUT is left open.
The input level of this pin is not TTL and must be
guaranteed by the clock source.
XTALOUT is the crystal controlled oscillator output.
When an external frequency source is used, this pin
is left open.
DRUN is a signal that discriminates between frequencies on RMFM. It goes low for low frequencies and
high for high frequencies. Its nominal threshold is set
to 1-3/8 bit times using DRUNRC. DRUN remains
asserted for a continuous stream of one's or zero's.
ie: Sync Field.
Connected to an external RC circuit for the generation of DRUN.
MFM Data received from the drive. A nominal4K ohm
internal pullup resistor allows tri-state multiplexing
of the driver's data receivers.
Delay line tap for generating full window RMFM
pulses.
Preconditioned WDATA ready to be written on the
disk. WMFM is held low when WGATE is low.
Delay line tap for uncompensated write data.

4-5

PIN DESCRIPTION (Continued)

=E

c

o

PIN
NUMBER

N

18

DYLDR

DELAY LINE
DRIVER

0

Drives an external delay line.

19

TEARLYZP

TEARLY ZERO
PHASE TIMING

I

Delay line tap for early precompensated write data and
for zero phase startup of the VCO.

20

THALFWIN

THALFWINDOW

I

Delay line tap for generating the enable phase delay
when in phase detection mode.

-"

o

o

MNEMONIC

SIGNAL NAME

I/O
\

21

TLATE

TLATE

I

Delay line tap for late precompensated write data.

22

RDATA

READ DATA

0

RDATA is RMFM synchronized to RCLK. The clock is
removed from the RM FM by the controller.

23

RCLK

READ CLOCK

0

RCLK is equal to one half of VCO and is synchronized
to RDATA during a read operation and to WCLK while
in an idle state.

24

VCC

25

PUMP

POWER SUPPLY
PUMP

I
1/0

26

VCOIN

VOLTAGE
CONTROL
OSCILLATOR
INPUT

I

Input to the VCO gain stage. VCOIN is clamped low,
and then released during zero phase startup.

27

VCOOUT

VOLTAGE
CONTROL
OSCILLATOR
OUTPUT

0

Output from the VCO gain stage.

28

IPUMP

IPUMP

I

An external resistor connected to IPUMP establishes
the magnitude of the charge pump current and
ADJUST current.

ARCHITECTURE
The WD10C20-05, with the necessay external components, provides the data interface between the
WD1010 or WD2010 and an ST506/ST412 compatible
drive. There are eight major functional sections within
the WD10C20-05:
•
•
•

•
•
•
•
•

FUNCTION

Synchronized Field Detector
Steering Control
Phase-locked Loop (PLL)
Phase-frequency Detector
Charge Pumps
Filter
Voltage Controller Oscillator (VCO)
Zero Phase Startup Circuit
Self Adjustment Circuit
Read Data Detector
Crystal Oscillator
Write Data Conditioner
Delay And Pulse Former
Power-on Reset

+ 5V

Power Supply.

Charge PUMP to the PLL filter. Also a voltage input
to the self-adjust sensing circuitry.

frequency data immediately preceding these fields.
The criterion used is pulse period discrimination on
the RMFM data. The external resistor and capacitor
connected to DRUNRC sets the nominal detection
threshold of 1-3/8 bit times. DRUN goes low for long
periods and high for short periods.
STEERING CONTROL
This logic controls the sequencing of events when
the WD10C20-05 is switching between read, write and
idle modes. When switching, the Steering Control
disables the Phase-Frequency Detector and Charge
Pumps, switches the MUX source, invokes zero-phase
startup, selects the velocity lock mode of the PhaseFrequency Detector, and high gain on the Charge
Pump. After the zero-phase startup is complete, the
Phase-Frequency Detector and Charge pumps are
enabled. If the device is in read or write mode, after
four byte times the Steering Control switches to phase
detection, and the charge pumps are set to low gain.
PHASE-LOCKED LOOP

SYNCHRONIZATION FIELD DETECTOR

Phase-Frequency Detector

The Synchronization Field Detector discriminates between the OO's of a Synchronization Field and the low

The Phase-Frequency Detector operates in one of two
modes: velocity lock mode or phase-only detection.

4-6

Winchester Disk Support Devices

Velocity lock mode is used for acquisition when the
PLL is switched to read or write data or when the PLL
is following the reference crystal oscillator.
The Steering Control logic switches to the Phase-only
mode when frequency and phase acquisition is nearly
complete. Internal delay paths have been carefully
matched to minimize introduction of a phase error due
to switching. The phase-only mode must be used to
lock to the MFM following the Sync Field, since that
contains the three MFM frequencies.
In either mode, the Phase-Frequency detector converts a phase difference between the VCO and the
input to a pulse width equal to the phase difference.
The polarity of the phase error determines whether
a Signal is directed to the pump up or pump down
circuitry in the Charge Pump section.
Charge Pumps
The Charge Pump circuit converts the widths received
from the Phase-Frequency Detector to proportional
amounts of charge, into or out of the filter. The gain
of the Charge Pumps is set by the input current of
the IPUMP signal. This current is set by an external
resistor connected to the VCC.
Filter
The Filter converts the current pulses from the Charge
Pumps to a voltage ouptut to the VCO. It also peforms
the sample-and-hold function necessary for an edge
locked PLL, and is also necessary during the zero
phase startup period. As shown in Figure 1, one of
the filter's capacitors (C110) is also part of the VCO's
series resonant oscillator.
The filter must meet the specific requirements .of
acquisition time, capture range, and jitter ejection,
and within the context of its effect on VCO operation. The filter functions to block high frequency
signals due to RMFM read data jitter, and passes the
low frequency Signals of the RMFM.
Voltage Controlled Oscillator:
The VCO is a series resonant LC oscillator. The active
gain element that provides the energy to sustain
oscillation is within the WD10C20-05, between the
VCOIN and VCOOUT pins. An inexpensive varactor
controls and tunes the VCO. The filter connects to
the anode of the varactor and provides the voltage
for loop operation of the PLL. Higher voltages at the
VCO input correspond to lower frequencies, and lower
voltages correspond to higher frequencies. The selfadjustment circuit connects to the cathode of the
varactor. The voltage bias at this point determines the
location of the VCO's V-F characteristic curve, and
is set for a favorable VCO input voltage at the nominal
frequency of the VCO.
Zero Phase Startup Circuit
The VCOIN connects to the Zero Phase Startup Circuit, which contains the logic necessary to turn a
clamp on or off. This clamp, in turn, enables or

Winchester Disk Support Devices

disables the VCO gain stage. When the WD10C20-05
changes the PLL input signal, the clamp is turned on
for a minimum of one input data period. This stops
the VCO gain and removes the AC energy from the
passive VCO components. The VCO is now in a
known state, and the time between the release of the
clamp and the time the first edge of the VCO reaches
the Phase Frequency Detector can be predicted. This
event is made to coincide with the arrival of a data
pulse by the delay between TEARLYZP and
THALFWIN.
Self Adjustment Circuit
The Self Adjustment Circuit (SAC) serves to slowly
maintain the VCO's input voltage near the sense level.
It performs compensation for component variations
in much the same way as manual adjustments, as
well as dynamic variations such as temperature,
voltage and aging. Another advantage of this circuit
is the heavy RC filtering of the + 12 volt supply. The
SAC tunes the VCO so that its nominal output frequency of twice the data rate corresponds to an input
voltage favorable to the Charge Pumps. This voltage
is approximately half of the VCC, and centers the capture range. The PUMP Signal connects to an internal
comparator and senses the VCO input voltage to
determine whether it is above or below the threshold
voltage (VSENSE).
The comparator is sampled at a low frequency derived
from the crystal. The output is used as the up / down
control to a six-bit counter. At power-on, this counter
is set to half scale. The least significant two bits are
for noise immunity only. The most significant four bits
connect to a digital-to-analog converter (DAC) that
controls the current-sinking ability of the ADJUST
signal. To convert the ADJUST signal current to a
voltage, it is connected externally through a resistor
to the + 12V. To filter the DAC steps and transients,
the ADJUST is connected to two capacitors. A resistor
from the ADJUST signal to the cathode of the VCO
varactor completes the circuit. Refer to Figure 1.
READ DATA DETECTOR
The Read Data Detector produces RCLK and RDATA.
RCLK is a square wave equal to one half of the VCO
frequency. During data tracking, RCLK mirrors the
slowly varying frequency of the RMFM. RDATA is a
regenerated form of the RMFM, with the jitter
removed and one-half bit-time pulse widths, and is
exactly synchronous with RCLK. RCLK edges occur
nominally in the center of RDATA to allow sufficient
setup and hold time for the digital circuits in the
WD1010 / WD2010 using these signals.
CRYSTAL OSCILLATOR
The Crystal Oscillator is designed to operate in the
parallel resonant mode, with an external crystal and
two capacitors. It generates the WCLK Signal used
externally. Internally, various divisions of it are used
by the Write Data Conditioner, PLL, and SAC.

4-7

:ec
.....

o

(')
I\)

o

:ec
-"

o

o

N

o

When an externally generated clock is desired, the
crystal and capacitors are omitted. The XTALIN pin
is connected to the clock source, and XTALOUT is
left disconnected. The input levels of XTALIN are not
TTL and must be guaranteed by the clock source.
WRITE DATA CONDITIONER

The Write Data Conditioner samples and precisely
synchronizes WDATA, EARLY, and LATE on the
leading and trailing edges of WCLK. When WGATE
is asserted, the DLYDR signal is a direct derivative
of WDATA and is connected to the input of the delay
line. It returns to the WD10C20-05 via the TEARLYZP,
TNOMINAL, and TLATE input signals. When WPCEN
is de- asserted, WMFM follows the TNOMINAL signal.
When WPCEN is asserted, the EARLY and LATE
signals select the TEARLYZP and TLATE inputs,
respectively. The differential delay between
TEARLYZP and TNOMINAL at the delay line defines
the amount of early precompensation, and similarly,
the differential delay between TNOMINAL to TLATE
defines the amount of late precompensation.
When WGATE is asserted, one of the initial MFM
pulses is suppressed to create an interval of two bit
times. This ensures that DRUN will go low at the
beginning of a Sync Field preceding a data field, so
that zero phase startup and velocity lock are executed
properly. When WGATE is de-asserted. WMFM is held
low.

DELAY AND PULSE FORMER

The Delay And Pulse Former includes the external
delay line as well as logic internal to the WD10C20-05.
In response to rising edges, it produces positive
pulses slightly longer than one detection window,
which is half of one bit time. The taps are also used
for write precompensation, zero-phase startup, and
defining the enable window for phase detection.
Depending on the mode of operation, its input is
either RMFM,' synchronized WDATA, or WCLK.
POWER·ON RESET

This integrated function is used to reliably set flipflops to a predictable state during the application of
the VCC. It is used by the Steering Control and SAC
sections.
DATA SEPARATOR CIRCUIT PERFORMANCE
SPECIFICATIONS

The following specifications apply when the external
components are selected as specified and operate
within the following ranges:
Vcc = + 5V ± .25V with ::s 100 mV ripple, 0 to 30 KHz
+ 12V + 12V ± 1.2V with::S 200 mV ripple, 0 to 30
KHz
Temperature 0° to 70°C (32° to 158°F)

=

=

PHASE·LOCKED LOOP:

•
•
•
•
•

•

•

Acquisition Time ................................... < 12.8 usec (16 usec from DRUN high)
Capture Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. > ± 2.2% (± 1 % drive ±.1 % crystal Osc.)
Jitter Rejection .................................... >40 db at 2.5 MHz
Damping Factor ................................... min.7 typo 1 max 1.4 Velocity Lock
min.5 typo .7 max 1.1 Phase Detection
KD Error Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. min 2 rnA
Velocity Lock
Gain
typ 6 rnA
Operating Range
max 10 rnA
VSENSE ± 1060 mv
min 1 rnA
Phase Detection
Operating Range
typ 4.3 rnA
max 6.8 rnA
VSENSE ± 950 mV
Error Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. max 2:1
Phase Detection
Balance Ratio
Operating Range
VSENSE ± 950 mV
Phase: ± 5 to
± 40 nsec
Ko VCO Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. min 4.5% per volt
typ 5% per volt
max 7.5% per volt

FREQUENCY DETECTOR

DRUN must be high in response to RMFM rising edge
to rising edge periods less than 250 nsec. DRUN must
be low for periods greater than 300 nsec.
CRYSTAL OSCILLATOR
The operational frequency must be within ±.1 % of
10 MHz.
PHASE DETECTOR/CHARGE PUMPS

Phase Decision Points

4-8

While in the phase detection mode, the phase difference from null (zero pump current) to the decision
points must be no less than ± 40 nsec.
VCO GAIN

Over the VCO input voltage range, VSENSE nominal
± 1060 mV, the VCO gain must be within the range
of 4.5% to 7.5% per volt. There must be no interruptions in its characteristic V-F curve over the input
voltage range.

Winchester Disk Support Devices

WD10C20-0S ELECTRICAL CHARCTERISTICS
MAXIMUM RATINGS
Vcc with respect to Vss .................................................................. + 5.5 Volts
Max Voltage range on any pin ...................................................... -O.5V to O.5V > Vcc
(except ADJUSn with respect to Vss
Max Voltage Range on ADJUST with respect to Vss ....................................... -D.5V to + 13.2V
Operating Temperature ........................................................ OOC(32°F) to 70°C(158°F)
Storage Temperature ....................................................... -65°C(-85°F) to 150°C(302°F)
NOTE
Maximum limits indicate where permanent device damage occurs. Continuous operation at these limits is not intended and should be limited
to those conditions specified in the DC Operating Characteristics
DC OPERATING CHARACTERISTICS
TA
OOC (32°F) to 70°C (158°F)
Vcc = + 5V ± .25V

=

Input signals:
TEARLYZP, TNOMINAL, TLATE, THALFWIN, TFULLWIN, RGATE,
WGATE, WPCEN, WDATA, EARLY, LATE, RMFM
SYMBOL
V IH
V IL

CHARACTERISTIC
Voltage Input High
Voltage Input Low

MIN

TYP

MAX

UNIT

.8

V
V

MAX

UNIT

±10

jJA

MAX

UNIT

+ 10

-4

jJA
mA

MAX

UNIT

+10
-2

jJA
mA

3.0

CONDITION

Input signals:
TEARLYZP, TNOMINAL, TLATE, THALFWIN, TFULLWIN,
RGATE, WGATE, XTALlN, VCOIN (Clamp off)
SYMBOL

CHARACTERISTIC

MIN

TYP

Input leakage

liN

CONDITION
VIN

= GND to Vcc

V IH
V IL

= 3.4 V*
= .45 V*

VIH
V IL

= 3.4 V*
= .4 V*

Input signals: WDATA, EARLY, LATE
SYMBOL

CHARACTERISTIC

MIN

TYP

Current Input High
Current Input Low

IIH
IlL

CONDITION

Input signal: WPCEN
SYMBOL
IIH
IlL

CHARACTERISTIC
Current Input High
Current Input Low

MIN

TYP

CONDITION

*These inputs mayor may not have an internal pullup resistor.
In either case, if IIH and IlL meet these specs, the inputs will be driven correctly.

Winchester Disk Support Devices

4-9

=E
c.....
o
o

I\)

o

Input signal: RMFM

:E
c
....
o

C')
I\)

SYMBOL

CHARACTERISTIC

MIN

TYP

Current Input High
Current Input Low

IIH
IlL

MAX

UNIT

0
-2.5

rnA
rnA

MAX

UNIT

.6

V
V

MAX

UNIT

.4
10
10

V
V
nsec
nsec

MAX

UNIT

.2
30
30

V
V
nsec
nsec

o

CONDITION
VIH = 3.4 V
VIL = .4 V
Internal pullup resistor

Input signal: XTALIN
SYMBOL
VIH
V IL

CHARACTERISTIC
Voltage Input High
Voltage Input Low

MIN

TYP

3.6

CONDITION

Output signals: WCLK**, WMFM, DLYDR
SYMBOL
VOH
VOL
TRISE
TFALL

CHARACTERISTIC
Voltage Output High
Voltage Output Low
Rise Time .8 to 2.0 V
Fall Time 2.0 to .8 V

MIN

TYP

2.4

CONDITION
10H
10L
CL
CL

= -1 rnA
= 4 rnA
= 30 pf
= 30 pf

10H
10L
CL
CL

= -100 pA
= 1 rnA
= 30 pf
= 30 pf

Output signal: WCLK* *
SYMBOL
VOH
VOL
TRISE
TFALL

CHARACTERISTIC
Voltage Output High
Voltage Output Low
Rise Time .9 to 4.2 V
Fall Time 4.2 to .9 V

MIN

TYP

4.6

CONDITION

**WCLK has two requirements. It must be able to drive special WD1010 / WD2010 inputs,
as well as a buffer at TTL levels. In any application, the total capacitance of the
WD1010 / WD2010, buffer, and PC board, must not be more than 30 pf. The total input
current of the WD1010 / WD2010 and buffer at the different input voltages must not
exceed the above specification.
Output signals: RCLK, RDATA, DRUN
SYMBOL
VOH
VOL
TRISE
TFALL

4-10

CHARACTERISTIC
Voltage Output High
Voltage Output Low
Rise Time .9 to 4.2 V
Fall Time 4.2 to .9 V

MIN

TYP

MAX

UNIT

.2
30
30

V
V
nsec
nsec

4.65

CONDITION
10H
IOL
CL
CL

= -20 pA
= 20 p,A
= 20 pf
= 20 pf

Winchester Disk Support Devices

Self Adjust, Pump, and Power
SYMBOL

CHARACTERISTIC

MIN

TYP

.4

2.4
±6
±4.5
.6

VSENSE Threshold
ACQUISITION PUMP Current
TRACKING PUMP Current
ADJUST Max Current
ADJUST Min Current
Power Supply Current

Vs
IA
IT
IJMX
IJMN
Icc

MAX

1.0
±10

40

UNIT
V
rnA
rnA
rnA
",A
rnA

CONDITION
3.57K on IPUMp···
3.57K on IPUMp···
3.57K on IPUMp···
3.57K on IPUMP, 5MHz

···Depending upon the application, there are specific requirements upon the pump currents and their relation·
ship to VSENSE. This document is written for 5 Mbitlsec, WD1010IWD2010, ST506/ST412 drive.
AC OPERATING CHARACTERISTICS
Timing on signals RDATA, RCLK, WCLK, and DRUN are measured at the voltage halfway between the
WD1010IWD2010's VIH and VIL: 2.55 Volts. All other signals are measured from the 1.4 volt transition. All timing
is measured with the load capacitance, CL
50 pf.

=

RMFM

\ _______1

/

\-----

_---I

1-

11 - - 1 -

---l

12

FIGURE 3. DISK DRIVE READ DATA, PULSE FORMING
TABLE 1. DISK DRIVE READ DATA, PULSE FORMING

SYMBOL

CHARACTERISTIC
RMFM Pulse Width High
RMFM Pulse Width Low

t1
t2

TYP

MIN

f--\

20
25

EARLY

--l "
~'a..j

~TE

-----------I~----'a-I----I-'af__------~\

MAX

UNIT

150

nsec
nsec

CONDITION

-------1', f - b
----V-:-"'at---~-----'a f--l 'a f-------1 "
1-',--1 1

' ......_ _ _J..J
----1 "

I

f__ f--"

-..j

;---

----1 " ~-..j

I

"

l-

'a f__

FIGURE 4. WRITE SETUP/OLD
TABLE 2. WRITE SETUP/HOLD

SYMBOL
t7
t8
t9

CHARACTERISTIC
Hold Time
Setup Time
WCLK Pulse Width

MIN
5
20
95

TYP

MAX

UNIT

105

nsec
nsec
nsec

CONDITION

Setup and Hold time is independent of the application of the WD10C20·05.

Winchester Disk Support Devices

4-11

:ec

\~/

......
o

o

N

o
FIGURE 5. DRUN

TABLE 3. DRUN

SYMBOL

MIN

CHARACTERISTIC

MAX

30

DRUN Low Pulse Width

t11

TYP

CONDITION

UNIT

nsec

*

*No requirement on DRUN pulse width high.

RCLK

J

I

\

I

RDATA

118~
119

\

/-114

-I·

115-1

/

\

/

119-1

l-

I

\
---l

I--

118

\

1=1

16

-I-

'-I

117~

FIGURE 6. RCLK, RDATA TIMING
TABLE 4. RCLK, RDATA TIMING
SYMBOL

t14
t 15
t 16
t17
t 18

t19

CHARACTERISTIC

RCLK High Pulse Width
RCLK Low Pulse Width
RDATA High Pulse Width
RDATA Low Pulse Width
RCLK Edge to RDATA
Rising Edge
RDATA Rising Edge To
RCLK Edge

MIN

93
93
93
93
30
30

TYP

MAX

UNIT

108
108
108
108

nsec
nsec
nsec
nsec
nsec

CONDITION

Max is implicit in t19min

nsec

Max is implicit in t 18 min

t14 and t 15 each define an MFM detection window. The rising edge of RDATA must occur within the window.
t14 + t 15 = the current bit cell time.

4-12

Winchester Disk Support Devices

IDLYDR

=E
c
.....

\

I

TFULLWIN

0
(')

---l

120

I

I\,)

\

0

FIGURE 7. DLYDR, TFULLWIN TIMING
TABLE 5. DLYDR, TFULLWIN TIMING

SYMBOL
t 20

CHARACTERISTIC

MIN

TYP

MAX

UNIT

36

nsec

12

DLYDR Shutoff Time

CONDITION

PACKAGE DIAGRAMS

;~: 0;:

1(

.J:t

1S49t 38

~}O~

1630t76

1- ~.

~LCS)

I
LOCATING
CHAMFER

1905

050 TYP
1270

012tOO3

3OlO8

~
12.446% .38

28 LEAD PLASTIC PH
490 015
12.446%.38

170 015
4.3181381

-

~"~"

-

~TYP
1270

28 LEAD PLASTIC QUAD JH

Winchester Disk Support Devices

4-13

4-14

Winchester Disk Support Devices

WESTERN
COR

P

0

DIGITAL

RAT

o

N

WD1014 Error Detection/Support Logic Device
FEATURES

•

32-BIT ECC POLYNOMIAL

•

BURST CORRECTION TO 11-BITS

•

MULTIPLE ERROR BURST DETECTION

•

DATA TRANSFER RATE OF 5-MBITS/SECOND

•

PROCESSES CHECK/SYNDROME BITS IN 2-BIT
SERIAL FASHION

•

SECTOR SIZES = 128, 256, 512, & 1024 BYTE
DATA FIELDS

•

SUPPORT READ/WRITE SHORT/LONG
FEATURES

•

ON-CHIP STORAGE OF SYNDROME/CHECK
BYTES

•

8-BIT I/O DATA BUS

•

SOFTWARE ADDRESSABLE REGISTERS &
!:ATCHES

•

ON-CHIP LOGIC FOR EXTERNAL BUFFER
CONTROL

•

40 PIN, DUAL-IN-L1NE, N-MOS DEVICE

•

TTL, MOS COMPATABILITY

•

SINGLE SOURCE +5 VDC SUPPLY

OSB1
HO/FO
AO
07
06
05
04
03
02
01
00
HSC
HBC
A2
A1
cso
CS1
BCS
llB
vSS

vcc
OSB2
SOH2
SOH1
SOHO
INTRa
MR
SC128
CMR
ORa
WAUP
CINC
SBEF
WE
RE
ClK
HOCS
RCS
BCR
lUB

PIN DESIGNATION

DESCRIPTION

The WD1014 EDS logiC chip provides the WD1002-05
Winchester Floppy Disk Controller (WFC) board with
ECC and support logic. The EDS chip is a single chip
device specifically deSigned to add error correction
capabilities to a 5.25" and 8" Winchester disk drive.
It also contains three 8-bit registers, three counters,
and several latches that enhance the capability of the
WFC on-board Control Processor (CP) chip WD1015
for control functions in real time operation. The EDS
4O-pin device replaces approximately 35 standard TTL
packages consisting of shift registers, flip-flops, and
logic gates.
The ECC polynomial selected is the same as the one
implemented in the WD1100-06 ECC/CRC logiC

Winchester Disk Support Devices

except that the current design is a 2-bit serial
implementation of the polynomial for faster operation.
The ECC polynomial selected is a computer
generated code optimized for sector sizes of 128, 256,
512, and 1024 byte data fields. The four ECC bytes
appended by this chip enable corection of a single
burst of up to 11 bits. It can also simultaneously
detect a single burst of up to 20 bits and a double
burst of up to 4 bits. The computer generated code
has been selected over a comparable fire code since
the fire codes suffer from pattern sensitivity problem.
The WD1014 EDS device is fabricated using Nchannel silicone gate technology, and is available in
a 40-pin, ceramic, dual-in-line package.

4-15

PIN DESCRIPTION

=E
c
.....
o
.....

PIN
NUMBER

1

MNEMONIC
DSB1

PIN NAME
DRIVE SELECT BIT 1

2

HD/FD

3

AO

HARD OR FLOPPY
DISK SELECT
ADDRESS BIT a

4
Thru
11
12

07
thru
DO

DATA 7
thru
DATA a

HSC

HOST STATUS
CONTROL

~

13

HOST BUS CONTROL

14
15
16
17
18

A2
A1
CSO
CS1

ADDRESS BIT
ADDRESS BIT
CHIP SELECT
CHIP SELECT

BCS

BUFFER CHIP SELECT

19

LLB

LOAD LOWER BYTE

20

GROUND

21

LOAD UPPER BYTE

=

=

This input along with CSO
1 and CSI
a is
used to address the WD 1014 registers.
8-bit bi-directional data bus. Data is output only when
the check / syndrome register or the command
register is read.
This output when low, enables the WFC status onto
the data lines making them available to the Host processor, if WAUP = O.
This output when low, enables the Host to communicate to the WFC and set up all task files, if WAUP
= a and HSC = 1.
These 2 inputs along with CSO = 1 and CS1 =
are used to address the WD1014 registers.

a

CSO = 1 and CS1 = a selects the WD1014, for
other combinations see the chart under task files.
This input line indicates that an external device wants
to access the buffer. The ECC check / syndrome computation is also enabled at this time.
The rising edge of this output line is used to load the
lower byte of address into the external buffer counter.
Ground.
The rising edge of this output line is used to load the
upper byte of address into the external buffer counter.

22

BCR

BUFFER COUNTER
RESET

This input indicates that an external device wants to
reset the external buffer counters. The internal
overflow counters are also cleared.

23

RCS

RAM CHIP SELECT

This output line is used to select external RAM when
BCS is active low or when the CP or the Host is
accessing the RAM. This output is disabled when
SBEF = 1.
This output line is used to enable the WD1010 when
the Host is accessing its task files except the Error,
Status and Command registers.
The rising edge of CLK is used to shift the ECC
polynomial and the falling edge is used to count
exactly 4 shifts.
Strobes used in conjunction with CSO = 1, CS1
= 0, A2-AO to access registers.

24

HARD DISK CHIP
SELECT

25

CLK

CLOCK

26
27

RE
WE

READ ENABLE
WRITE ENABLE

28

SBEF

SECTOR BUFFER
EMPTY OR FULL

29

4-16

2
1
BIT a
BIT 1

FUNCTION

This output is encoded with DSB2 to select one of
three Winchester Drives or one of four floppy drives
depending upon the state of HD / FD.
When high, hard disk drives are selected and when
low, floppy disk drives are selected.

COUNTER INCREMENT

Output signal used to indicate the sector buffer has
been filled or emptied.
The rising edge of this output signal increments an
external address counter. This output is enabled only
if the RAM is being accessed and SBEF = O.

Winchester Disk Support Devices

PIN DESCRIPTION
PIN
NUMBER

MNEMONIC

PIN NAME

FUNCTION

30

WAUP

WAKEUP

This output signal is made active by the Host issuing a command and filling the sector buffer. It
indicates that a command is being executed by the
CP on the WFC board. The Host now cannot communicate with the WFC until the command has been
completed. MR also sets WAUP.

31

DRQ

DATA REQUEST

The data request line is activated whenever the sector buffer contains data to be read by the Host, or is
awaiting data to be loaded by the Host. This line is
reset whenever the sector buffer has been filled or
emptied.

32

CMR

COUNTER MASTER
RESET

This output signal resets the external address
counters whenever a MR or a command has been
issued by the Host, or when BCS is asserted.

33

SC128

SECTOR COUNT OF
128 BYTES

34

MR

This input signal is used in conjunction with the SDH
register to indicate that the buffer has overflowed.

MASTER RESET

Used to initialize internal logic. All internal buffer
overflow counters are reset, the ORQ and INTRQ flipflops are cleared and BUSY is set.

35

INTRQ

INTERRUPT REQUEST

This output line is activated whenever a command has
been completed. It is reset to the inactive state when
the status register is read, or a new command is
loaded via the DAL lines, or MR is asserted.

36
37
38

SDH2
SDH1
SDSH2

DRIVE SELECT, AND
HEAD SELECT BITS

The 3 least significant bits of the internal SDH register
are available as outputs. The SDH register is updated
whenever the Host writes to it.

39

DSB2

DRIVE SELECT BIT 2

This output is encoded with DSB1 to select one of
three Winchester Drives or one of~ur floppy drives
depending upon the state of HO/FD.

40

Vee

POWER SUPPLY

+ 5V Power Source

TASK FILES
WAKE UP, CS1, CSO, A2-AO, RE and WE are used to select various registers as shown below:
WAKE UP

X

a
1
1

X

CS1

CSO

1
1
1

1

a
a

a
a
1

a

Winchester Disk Support Devices

A2-AO

X
X
X
X
X

EFFECT
Idle - Nothing selected.
Host to WFC and WD1010 files.
CP to WD1010 + RAM access.
CP to WD1014.
Illegal condition.

4-17

:E
c
.....

o
.....

WD1 01 0 REGISTERS

WD1014 REGISTERS
A2

A1

AO

0

0

0

0
0
0
1
1
1
1

0
1
1
0
0
1
1

0
1
0
1
0
1

~

RE

WE

o

O+CHECKj
SYN bytes

1

SLEEP
Clear OVF/CNTRS

Clear Mult Mode
O+Command'

RE

+ CH ECK bytes

Set ECC
0+ LLB2
0+ LUB 2
Set DRO
Set Read Latch
Set Mult Mode
0+ Error Reg.

'Data bus contains valid information. Except as
indicated in " the Host and onboard CP(WD1015)
can access the registers in the WD1010. The registers
in the WD1014 can only be accessed by the WD1015.
For the registers not referred to in " the data bus
need not contain valid information.

WE

RAM

RAM

Error Req. "
Sector Count
Sector Number
Cyl i nder Low
Cylinder High
S.D.H.
Status Reg. "

Write Precomp
Sector Count
Sector Number
Cylinder Low
Cylinder High
S.D.H.
Command Reg. "

"The Host does not access these registers in the
WD1010 (or WD2797). The content of these registers
must be off loaded to an intermediate register for
access by the Host.

BITS
COMMAND

7

6

5

4

3

2

1

0

READ
WRITE
FORMAT

0
0
0

0
0
1

1
1
0

0
1
1

I

0
0

M
M
0

L
L
0

0
0
0

COMMAND CODES

For the implementation of parts of the controls, the
following command codes are pertinent:

protocol described can be used in any new designs.

WD1 014 ARCHITECTURE

The WD1014 consists of a 2 bit serial polynomial
generator (that produces 4 bytes of check/syndrome)
an 8 bit data buffer and deserializer, two 8 bit
registers, namely a Command/Error register and a
SDH register, and control logic consisting of 3
counters, 6 latches, and a host of combinatorial logic.
The addressable registers and latches are accessed
as shown in the block diagram below.

The WD1014 Chip was specifically designed for the
WFC board to extend the capabilities of the Control
Processor (WD1015) to handle real time functions. As
designed, the WD1014 is not a stand alone general
purpose device unless, of course, almost all of the

Each major functional block will be described essen·
tially independent of one another. Some overlap and
references to the WFC board are unavoidable and,
in fact, they aid in presenting a clearer picture of the
device.

The control logic only decodes bits 7·4 and uses bit
1 (long bit) in its internal logic. The rest of the com·
mand codes and bits are not used by the WD1014.
For a complete description of the commands or the
task files refer to the WD1002·05 WFC data sheet.

4-18

Winchester Disk Support Devices

boo
00-07

DATA
BUFFER

ECC
POLYNOMIAL
GENERATOR
CHECKER
EVEN
ODD

EVEN

DE-SERIALIZER

00-07

. - - - - - - - - - - - -__ SCHO-2
.--------------l~ DSB1-2

HDiFiS

MA

HSC
HBC

CSO
CS1

ITB

AO
A1
A2
BCS
CLK

CONTROL
LOGIC

INTERNAL
REGISTERS

RE

WE
SC128

DECODE
LOGIC

LUB
HDCS
SBEF
CINC
WAUP
ORa
CMR
INTRa

WD1014 BLOCK DIAGRAM
THE ECC POLYNOMIAL GENERATOR
The 4 byte check / syndrome generator consists of
two 16 bit shift registers each of which has 8 feedback terms implemented with XOR gates, and control gates for the feedback and data paths.
The leading two bytes of the data field are not
recognized by the WD1014. Therefore, in order to
maintain compatibility with the devices that do, the
polynomial is preset to what would have been
calculated if the AIF8 had been read_(B517894A)
EGG computations are made whenever the external
sector buffer is being accessed. The data present on
the system data bus is accepted by the input data
buffer and processed along with the gated data from
the last stages of the shift register strings. The direction of shift within the EGG polynomial is from the
LS.B. to the M.S.B. After the last byte of data has been
accessed from the sector buffer, the internal counter
overflow register is set. This in turn sets a feedback
inhibit register after the last byte has been processed
by the EGG polynomial. At this point, the feedback
terms are forced to zero and only the data path to
the LS.B. is enabled. This feature is convenient to
store the 4 check / syndrome bytes internally so that
RLONG and WLONG commands can be supported

Winchester Disk Support Devices

without the use of an external buffer.
During a write operation, the input data stream is
divided by the polynomial and the 32 bit remainder
obtained after buffer overflow is used as the 4 check
bytes. The 4 check bytes are gated out of the WD1014
even though RGS = 1 since the internal RBGS is
still active. In a READ operation, the check bytes are
recomputed and compared to the recorded check
bytes to generate the 4 syndrome bytes. The syndrome bytes are stored internally in the shift registers
until the GP is ready to use them. Otherwise, the nonzero syndrome is used by the software algorithm to
compute the displacement and the error vector within
the bad sector.
To support RLONG and WLONG (L = 1) features of
the WD1002-05, shift register strings are used as
storage elements. After the last byte of data, the Host
can write or read the 4 additional bytes which serve
as check bytes for the data transmitted to the buffer. In this mode the feedback terms and the outputs
from M.S.B. of the shift registers are disabled so that
only data is accepted and stored. This enables the
user to alter the check bits / or data to verify the
operation of the Error detection logic.

4-19

SOH REGISTER

This register can be written into by either the Host
or WD1015. The bits are decoded as follows.
BIT

6

7

5

4

3

2

1

0

CRC
FUNCTION

Bit?

Bit 6-5

+

SECTOR

ECC

SIZE

DRIVE

HEAD/DRIVE

SELECT SELECT

should be set to a 1 whenever a Winchester
disk is selected "and" ECC is to be utilized.
It must be set to 0 for floppy disks.
as shown below specify the sector size.

SDH6

SDH5

1

1

o
o

o

1

o

SECTOR SIZE IN BYTES

1

128
256
512
1024

The decoded bits are used in conjunction with a 3
bit counter which has SC128 as its clock. The falling
edge of this input is used to set a counter overflow
latch for sector sizes 256, 512 and 1024. The rising
edge of this input sets counter overflow latch when
the sector size is 128. The counter overflow is
available on the output as SBEF and is used internally to set the buffer overflow latch and various other
control logic as required by system operation. This
counter and associated logic is cleared upon MR,
any new command, or can be directly cleared by
CLROVF.
Bits 4·0 are used for drive and head selection and
are decoded in the following manner.
Winchester
HD/FD = 1 = SDH4 + SDH3 + SDH4'SDH3
DSB1 = 1 SDH3 decoded off chip for one of three
DSB2 = 1 = SDH4 drives.
SDH2-0 =SDH2-0 decoded off chip for one of eight
heads.

=

Floppy
HD/FD = 0 = SDH4'SDH3
DSB1 = 1 = SDH1 decoded off chip for one of four
DSB2 = 1 = SDH2 drives.
SDH2-0 = Not used.
Side select is controlled by the WD1015 via
the WD2?9?
COMMAND/ERROR REGISTER

This 8 bit register intercepts and holds the command
issued by the Host. When a command is issued:

(b)
(c)
(d)
(e)

the external counters are cleared via CMR
the read command latch is cleared
INTRQ is reset
bit 1 (the long bit) is used by the ECC polynomial
to implement the READLONG and WRITELONG
command. The CP can also read this latch so that
it can execute the command.
(f) WAKEUP is set immediately if the command is
a RESTORE, SEEK, or READ. For a WRITE or a
FORMAT command, WAUP is set after counter
overflow (COVF) occurs or an additional four RAM
accesses have occured (SYN4), depending upon
the long bit L = 0 or L = 1.

At the completion of a command, this register is reused to hold error information that can be read by the
Host. This is necessary since error information from
two sources has to be manipulated by the CP and
reported to the Host in real time when requested to
do so.
ERROR DETECTION LOGIC

The error detection logic consists of an input data buffer and deserializer, two 16-bit shift registers to
generate the ECC bytes, and associated control logic
consisting of two 3-bit counters and integrated logic.
INPUT DATA BUFFER AND DESERIALIZER

This section is designed to accept a byte of data on
the riSing edge of RE or WE under the following
conditions:
1. The ECC polynomial is selected as implied by
SDH? = 1.
2. A valid RBCS is generated
the counter overflow

regardless

of

3. If the syndrome is to be read by the C.P. after an
overflow condition has occurred (i.e., the syndrome
is not saved after it has been read by the C.P.).
Valid data presented to the WD1014 device is
accepted by the data buffer and the ECC shift
registers on the rising edge of RE or WE input
strobes. These strobes are synchronized internally by
the falling edge of the input clock so that shifting can
begin on the riSing edge of the clock. Data is serialized
and shifted in a 2-bit parallel mode until the internal
bit counter reaches the count of 3. This process is
repeated for every byte of data until the counter
overflow occurs plus an additional 4 bytes have been
processed. Under the worst case conditions, a byte
of data will be processed within 4 clock cycles after
the RE or WE strobes are terminated.

(a) the sector counter and associated overflow latches are cleared.

4-20

Winchester Disk Support Devices

MULTIPLEXER

The multiplexer is used to channel data to the I/O
pins 07-00 when one of the following conditions
occur.

2. Any command is received
3. The output signal HCS is activated.

2. The error register is read

As in the case of ORO, the true condition of INTRa
can only be sampled by external circuitry if WAUP
= O.

3. The check bytes are read

MISCELLANEOUS CONTROL SIGNALS

4. The syndrome bytes are read

The rest of the output signals are purely combinatorial
in nature and are best described by Boolean expressions.

1. The command register is read

The RE strobe gating with the above control signals is designed to keep the hold time on the output
data bus to less than 100 n.s. and the data access
time to be no more than 200 n.s.

1. HSC = BUSY.CSO.A2.A1.AO.RE

WAKEUP

2. HBC = BUSY.CSO.HSC

This signal alerts the external CP that a command
has been received and is internally referred to as the
busy signal.

3. LUB

WAUP will go high when MR is asserted or a
command other than WRITE or FORMAT has been
received. In the case of a WRITE or FORMAT command WAUP will go high when SBEF = 1 and L =
0, or when an additional four bytes have been
accepted by the W01014 when L = 1.
For proper operation, the READ command latch must
be set by the CP whenever that command has been
received. Also the Multiple Mode latch is set by the
CP in order to execute the same command a multiple number of times. This latch must be reset if
executing a REAO or a WRITE command only once,
or if the last sector of a multiple sector transfer is
being processed.
WAKEUP can only be reset by asserting SLEEP.

4. LLB = CS1.A2.A1.AO.WE
5. RCS = COVF(CSO.A2.A 1.AO
6. HOCS = (BUSY.A2.A1.AO.
+ CSO)

+ BCS)

+ BUSY.. A2.A1.RE

HOCS is active only if the Host is not accessing the
error, status or the command registers of the W01010
device, and CSO is asserted.

= COVF.RSC(WE + RE)
8. eMR = MR + eST where eST

7. CINC

= BUSY.eso

.A2.A1.AO.WE(Any cmd written)
9. SBEF = eOVF
ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS
Ambient Temperatures
under bias .......... 0oC (32°F) to 70°C (158°F)

DATA REQUEST

The true condition of the ORO latch can oly be
sampled by external circuitry if WAUP = O.
This latch can be set by either the CP, or whenever
a WRITE or FORMAT command is written into the
W01014. It is reset by COVF
1 (SBEF) when L
0, or until an additional 4 bytes have been accepted
by the W01014 when L
1.

=

= CS1.A2.A1.AO.WE

=

=

INTERRUPT REQUEST

Two latches are provided to handle interrupts. The
programmed I/O interrupt (PINl) latch is set whenever
an interrupt is desired at the start of data transmission to the Host. The OMA interrupt (OINl) latch is
set whenever an interrupt is desired at the end of data
transmission to the Host.

Voltage on any pin
with respect to Vss .......... -0.2V to + 7.0V
Power dissipation ..................... 1.5 Watt
STORAGE TEMPERATURE
Plastic .......... -55°C(-67°F) to
Ceramic ......... -55°C(-67°F) to

+ 125°C(257°F)
+ 1500 C(302°F)

NOTE:

Maximum ratings indicate operation where permanent device damage may occur. Continuous operations at these limits is not intended and should be
limited to those conditions specified in the OC electrical characteristics.

Both latches are reset when:
1. A MR occurs

Winchester Disk Support Devices

4-21

TABLE 1. DC Electrical Characteristics TA

:ec

.....
o
.....
~

SYMBOL
VIL
VIH
VOL
VOH
VCC
ICC

= OOC (32°F) to 70°C (158°F), Vee = +5V
MIN

CHARACTERISTIC
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Supply Voltage
Supply Current

TYP

-0.2
2.0

MAX

UNIT

0.8

V
V
V
V
V
rnA

.04
2.4
4.75

5.0
200

5.25
250

± .25V, Vss

= OV

CONDITIONS

IOL = 1.6 rnA
IOH = -100 rnA
All outputs open

TIMING PARAMETERS
A2-A0

8

____---'X

~

-lIAS!+-

-jIAHI-

cs -----,

r-I

----~~__:_-'

r 1. r--ICH
R"E----,
ICSj

ISp

07-00----<

I
I

r

WAUPI

r

-l

-l IIV I-

1-:

liS
r-----~(~
INTRO.----J
.
~
!,

-l 10V f-

-l lOR f-

II

DRG---1

L

rr

FIGURE 1. DATA READ CYCLE
TABLE 2. DATA READ CYCLE TIMING
SYMBOL
fcp
t AS

MIN

TYP

MAX

UNIT

6.0

5.0

MHZ

Address Setup to CS
Address Hold from CS

100
50

70

nS

20

nS

tcs

Chip Selects Setup to
RE

100

70

nS

tCH

Chip Selects Hold from
RE

50

20

nS

tRE
tsp

RE pulsewidth

150

120

tAH

4-22

CHARACTERISTIC
Input Clock Freq.

RE Strobes period
(rising edge)

tOA

Data Access after RE
active

tOH

Data Hold after RE
inactive

tos

Data Setup to RE
inactive

tlV

Interrupt Request valid

tiS
tov
tOR

nS

4

50

CONDITIONS

CP
100

150

nS

50

100

nS

10

reading

nS

INTRa Reset
Data Request Valid

50
200
100
50

100
250
200
100

nS
nS
nS
nS

ORO Reset

100

200

nS

Prog. 1/0 INT
DMA INT

Winchester Disk Support Devices

AC ELECTRICAL CHARACTERISTICS

A2-AO,B<_____-:-~~'--_ _ _ _X
-ltASICS

-JtAHI-

1

I

i . t-tCH

tCS--j

tsP--=----.l

WE------~

~---

-+jtOSr-

07-00-----<=="J------+-C=:::)
WAUP~~________________________-+,__~:-----

-l tlV I-

-.\ tiS ~:

---------,1 :

INTRQ~.--------------i(If-1

~tov~

~~ltO--R--r--II

ORG-----.J

L

If

FIGURE 2_ DATA WRITE CYCLE
TABLE 3. DATA WRITE CYCLE TIMING
SYMBOL

fcp
tAS
tAH

CHARACTERISTIC

Input Clock Freq.
-Address Setup to CS
-Address Hold from CS

tcs

Chip Selects Setup to
WE

tCH

Chip Selects Hold from
WE

tWE
tsp

WE pulsewidth
WE Strobes period
(rising edge)

tOHW

Data Hold after WE
inactive
Data Setup to WE'
inactive

tos
tlv

MIN

TYP

MAX

UNIT

6.0
70
20
70

5.0

MHZ

100
50
100
50

20

nS

150

120

nS
CP

0

30

nS

50

10

nS

50
tiS

INTRa Reset

tov

Data Request Valid

tOR

DRa Reset

Winchester Disk Support Devices

nS
nS
nS

4

Interrupt Request valid

50
200
100
50
100

CONDITIONS

100
250
200
100
200

nS
nS

writing

Prog. 1/0 INT
DMA INT

nS
nS
nS

4-23

,(
....'
1

[:tsc

1
1
I

I
1

/

I
-+I

BC
II t t

RBC--........... I

I
I
-+I

t=t CI

y

CINC--~:~~~____~
I

itBRj
SBEF
1

:1

--:

CMR
YVAUP

'"

~-~-------

f-tCM

_---'__'y-----L. . "'. ________

______--_~:_tw_RL

FIGURE 3. OUTPUT SIGNALS W.R.T. RE

TABLE 4. OUTPUT SIGNAL (W.R.T.) RE TIMING
SYMBOL

tCI
t Hs
tsc
tHB
t BC
tBR
tCM
tWR

4-24

CHARACTERISTIC

RE to Count Increm.
RE to Status Strobe
RE to HSC inactive
CSO to Host bus str
CSO to HBC inact.
RE to cir SBEF
RE to counter reset
RE to WAUP reset

MIN

TYP

MAX

UNIT

50
130
130
70
80
250
200
100

100
200
200
200
200
300
300
200

nS
nS
nS
nS
nS
nS
nS
nS

CONDITIONS

rising edges

--

active if HSC off
active if HSC off
using CLROVF strobe
using CLROVF strobe
using SLEEP strobe

Winchester Disk Support Devices

WE~

,t{"

I '-------' I

-I1,...--_
tSOI_ __

I

I

---;-------'>KI

SOH2·0

VALID

:-tSE-j
osx--~------")K
I

__ _

tLF-:

VALID

I

I-

--:

f-tLR

LLB/LUB~
I

1

~tCI
CINC~
:

-

I

1

I
I
I

I
I
1

SBEF---~:----~~

---'I ttcc
I
I

CMR--..../

I

\

1

_

tSWr-

i-twW--Y-

WAUP

FIGURE 4. OUTPUT SIGNALS W.R.T. WE
TABLE 5. OUTPUT SIGNAL (W.R.T.) WE TIMING
SYMBOL

tso
tSE
tLF
tLR
tCI
tcc
tsw
tww

CHARACTERISTIC

WE Inactive to SDHX
output
WE Inactive to DSX
output _ _ _
WE to LLB/LUB
WE to LLB/LUB
WE to Count Increm.
WE to Counter Reset
SBEF to WAUP set
WE to WAUP set

Winchester Disk Support Devices

MIN

TYP

MAX

UNIT

150

200

nS

175

200

nS

70
80
50
150
50
175

150
150
100
200
200
200

nS
nS
nS
nS
nS
nS

CONDITIONS

falling edges
rising edges
rising edges

Command written

4-25

t--tMR-\

.

MR'BCR~
-:
CMR

:-tMC

!~

---+--';
--I

"---

jtMB

SBEF~

1''------

--....: i--tws

WAUP~

SC128~
SBEF

tSR

~

n _____ ~

A2.AO,CSO~
'----~

FIGURE 5. MISCELLANEOUS TIMINGS
TABLE 6. MISCELLANEOUS TIMING
SYMBOL

tMR
t MC
tMB
tws
tSR
tSF
tHO
tHR
t RC
tRR
t BC
tBH

4-26

CHARACTERISTIC

Master reset/Buffer
counter reset width
MR/BCR to counter reset
MR/BCR to SBEF rst
MR to WAUP reset
Rising Edge of SC128 to
SBEF
Falling Edge of SC128 to
SBEF
CSO to HDCS
CSO to HDCS rising to
CMR
CSO to RCS active
CSO to RCS high
BCS to RCS active
BCS to RCS high

MIN

TYP

100

50

MAX

UNIT

CONDITIONS

nS

60
130
100
100

100
200
200
200

nS
nS
nS
nS

BCR has no effect
128 byte sector

150

200

nS

all other sectors

·70
80

150
150

nS
nS

(or address lines)

90
100
50
60

150
150
100
100

nS
nS
nS
nS

(or address lines)

Winchester Disk Support Devices

WESTERN

DIGITAL

COR

A

paR

a

T

N

WD1015 Buffer Manager Control Processor
FEATURES

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

SINGLE + 5V POWER SUPPLY
COMPLETE BUFFER MANAGER
PROGRAMMABLE SECTOR SIZES - 128, 256,
512, or 1024 BYTES
ECC BURST ERROR CORRECTION UP TO 5
BITS ON HARD DISK DATA
8-BIT MULTIPLEXED ADDRESS/DATA I/O BUS
FLOPPY DISK COMMAND TRANSLATION
SUPPORTS MOTOR ON OR HEAD LOAD
DRIVES
SUPPORTS 250 OR 500 KBS FLOPPIES
BUFFERED SEEKS WITH FLOPPIES AND
WINCHESTERS
16 POPULAR STEPPING RATES AVAILABLE
AUTOMATIC RETRIES ON ALL ERRORS WITH
SIMULATED COMPLETION
POWER-ON DIAGNOSTICS INCLUDED
10 MHZ CLOCK RATE
40 PIN DIP PACKAGE
44 PIN aSM PACKAGE

WAUP
XTAL1
XTAL2
MR
TST5
INTFD
VSS2

m:

TST9
WE
LAD
DO
D1
D2
D3
D4
D5
D6
D7

Winchester Disk Support Devices

VCC2
TST25
TST24
TST23
TST22
TST21

VSS1

DESCRIPTION

The WD1015 is a complete Control Processor (CP)
that is used to handle all aspects of buffer management, in conjunction with the EDS (WD1014) device,
for the Winchester/Floppy Controller board
(WD1002-05). It executes all of the commands used
by the WD1002-05 and does all of the control required
except for real time processing, which is done by the
WD1014. Throughout this specification this device will
be referred to as the WD1015, or BMAC (buffer
manager and controller), or simply as the CP (control processor). The WD1015 is programmed to control the transfer of information within the WFC and
it maintains the necessary copies of the task files
(TSF) found on both drives. Host access to the WFC
causes the CP to access task file information in the
TSF after a command is issued. Depending on the
command, the CP will make the buffer accessible to
the host or the WD1010 or 2797 controllers. The CP
also controls the operation of the Error Correcting
logic. During the transfer of data from the Host to the
WD1010, the EDS monitors the data bus, if so
enabled, to compute a 4 byte ECC which is appended
to the data transferred to the WD1010 and recorded
on the disk. During data transfers from the WD1010
to the host the CP uses the ECC to validate the data.
If data is corrupted the CP envokes recovery techniques such as retries and correction. A maximum of
8 retries are attempted if two consecutive syndroms
do not match. Correction is attempted only if two consecutive syndromes match. If the error is uncorrectable, the operation is terminated. The CP is also used
to handle data transfers from or to the SF for the

VCC1
DRQFD
ERR
CORRD
BRDY
FMO
DIR
STEP
MOM
TST31
SBEF
TROQ
HD/FD
INTHD

PIN DESIGNATION

H I
TON V

R I

o
o

T

C

0 0

2

F H C

BROY
CORRO
ERR
ORQFO
VCC1

T5T25
T5T24
T5T23
T5T22
T5T21

NC
WAUP

V551

NC

XTAL1
XTAL2
MR

07
06

T5T5

04

05

I

V R T W N L DOD 0

~ ~ E ~ E C A 0 1 2 3
F 2

o

9

0

QSM DESIGNATION

4-27

WD2797 and the current EDS status into a form con·
sistant with established WD1010 error reporting. This
consolidated status is then presented to the Host. The
WD1015 is fabricated using HMOS technology and
is available in a 40 pin DIP package and 44 pin QSM
package.

floppy disk controller, which only uses CRC check
bytes for its data fields. Two commands, RESTORE
and SEEK, are directly executed by the CP rather than
the WD2797 floppy disk controller. During status
reads by the Host, the CP consolidates the normal
completion status from the WD1010, the
PIN DESCRIPTION
PIN
NUMBER

SIGNAL NAME

FUNCTION

MNEMONIC

1

WAKEUP

WAUP

This input is used by the BMAC to poll a command from the Host.
The BUSY status bit is set immeditately execpt in case of a
WRITE/FORMAT command. In that case, WAUP and BUSY, are
set only after the sector buffer has been filled by the Host. WAUP
is reset when the command has been executed.

2

CRYSTAL 1

XTAL1

One side of crystal input for internal oscillator. Also input for
external source.

3

CRYSTAL 2

XTAL2

Other side of crystal/external source input.. Frequency should
be 10 MHz.

4

MASTER RESET

MR

This input is used to initialize the internal logic of the processor.

5

TEST 5

TST5

This input is to be left open by the user. Internal pull·up 300K ohm.

6

FLOPPY DISK
INTERRUPT

INTFD

Initiates an interrupt if interrupt is enabled; disabled on reset.

7

VSS2

VSS2

This input is to be left open by the user. Internal pull·up 10M
ohm.

8

READ ENABALE

9

-

RE

Output strobe activated during a BUS read. Can be used to enable
data onto the BUS from an external device.

TEST 9

TST9

This output is left open by the user.

10

WRITE

WE

Output strobe during a BUS write. Used as write strobe to an
external device. Signifies that valid data has been put on the BUS.

11

ADDRESS LATCH

LAD

This output signal occurs once during each instruction cycle. The
negative edge of LAD strobes address into an external latch, used
to communicate to the WD1010, WD2797, and the WD1014 chips.

DATA BUS

D7·DO

True I/O bi·directional BUS which can be written to or read syn·
chronously using RE, WE, strobes. Also contains the address
and data during an external access to or from port devices, under
control of LAD, RE, and WE.

12·19

20

GROUND

VSS1

Ground.

TEST 21·25

TST21·25

Unused pins to be left open by the user.

26

VCC2

VCC2

+ 5V

27

HARD DISK
INTERRUPT

INTHD

This input is polled to sense an interrupt from the WD1010,
indicating completion of command issued to it by the BMAC.

28

HARD DISK/FLOPPY HD/FD
DISK

This input is used to sense hard disk operation when high, and
floppy disk operation when low.

29

TRACK 00

TROO

This input indicates that the RIW heads of the selected floppy
drive are positioned over the outermost cylinder.

30

SECTOR BUFFER
EMPTY/FULL

SBEF

This input to the BMAC is set high whenever a sector of data
has been written to or read from the Sector Buffer.

31

TEST 31

TST31

Normally left open by the user.

21·25

4-28

during operation.

Winchester Disk Support Devices

PIN DESCRIPTION (cont.)
PIN
NUMBER

SIGNAL NAME

MNEMONIC

32

MOTOR MODE

MOM

33

STEP

STEP

34

DIRECTION

DIR

35

FLOPPY MOTOR-ON FMO

36

BUFFER READY

37

CORRECTED DATA CORRD

38

ERROR

ERR

39

DATA REQUEST

DRQFD

40

VCC1

VCC1

BRDY

Winchester Disk Support Devices

:e

c
.....

FUNCTION

Input used to select motor-on or head load timings for floppies.
This line should be left open for motor-on type drives such as
the mini floppies. A delay of 1 second will be observed before
FMO is activated.
For head load type drives like the standard floppies, this input
should be grounded. A delay of 40 mS, will be observed before
FMO is activated, thereby improving the overall performance
when accessing the floppies.
The STEP output is pulsed once for each cylinder to be stepped
on the floppies. The step pulse period is normally determined
by the stepping rate selected. On a RESTORE for the floppies,
however, a stepping rate of 8 mS, is used if the specified stepping rate is faster than 8 mS.
This output is used by the floppy drive to determine the direction of a seek operation. A low defines direction as out and a
high specifies direction as in.
This output is used to turn the motor on, on all floppy drives supported by the WD1002 WFC board. The drives must be configured
such that the heads are loaded when this signal is activated.
When the floppies are being accessed for the first time, a delay
as determined by MOM, is observed before activating FMO.
Motor on is turned off after - 3 seconds, if no further floppy
accesses are made.
This output signal indicates the sector buffer is ready to be
accessed by an external device such as the WD1010.
This output status indicates to the Host that the BMAC has successfully corrected a data error in the data buffer, at least once.
To determine if more than one correction has taken place during a multisector read, each sector specified must be reread by
the Host on an individual basis.
Output status bit indicates that the BMAC encountered an error
during the execution of a command.The error reg, on the WFC
board must be read by the Host to determine the type of error
that occurred.
This input indicates to the BMAC that the WD2797 has a byte
of data available to be read from the disk, or requires a byte of
data to be written to the floppy disk.
Main power supply. +5V ±5%

4-29

o
.....
en

4-30

Winchester Disk Support Devices

WESTERN
COR

P

0

DIGITAL
o

RAT

N

:ec
...a.
...a.

WD1100-21 Buffer Manager Support Device

o
o

•

~

...a.

FEATURES
•
•
•
•
•
•
•
•
•

6-BIT AUTO-INCREMENTING ADDRESS BUS
128, 256, 512, OR 1024 BYTES PER SECTOR
DETECTOR
SELECTS UP TO 4 DISK DRIVES
SELECTS UP TO 8 HEADS PER DRIVE
PROVIDES A RAM CHIP ENABLE AND READY
SIGNAL
TTL, MOS COMPATIBLE
40 PIN DIP PACKAGE
NMOS TECHNOLOGY
SINGLE + 5 VDC SUPPLY

DESCRIPTION
The WD1100-21 Buffer Manager Support Device is
designed to interface up to four disk drives and eight
heads per drive, to a WD1010-05 and Sector Buffer.
The WD1100-21 accepts the SOH Register information (Sector Size, Drive, Head) and selects the
appropriate drive and head. It receives the data from
the disk and develops RD and DRUN (Read Data and
Data Run) suitable for the WD1010-05. The WD1100-21
also selects the Sector Buffer and provides six of the
address lines. The other four address lines must be
implemented externally. The WD1100-21 signals BRDY
(Buffer Ready) when the buffer counter reaches the
value stored in the SOH Register.

Winchester Disk Support Devices

OROl
OR02
OR03
OR04

Vcc
Al0
All
A12
A13
A14
A15
RCE
BClR
06
05
04
03
02
01
DO
AO
Al

ORH
ORl
H02
HOl
HOO
MR
BCS
BCR
RO
BROY'
ORUN
CS

WE
REORTIM

A2
ROTIM

VSS

PIN DESIGNATION

4-31

PIN DESCRIPTION

:E

c.....
.....

PIN
NUMBER

o
oI

J\),
.....

1/0

FUNCTION

1

DRD1

READ DATA 1

I

This signal is data read from disk drive 1. It
is shaped and placed on output pin 13.

2

DRD2

READ DATA 2

I

This signal is data read from disk drive 2. It
is shaped and placed on output pin 13.

3

DRD3

READ DATA 3

I

This signal is data read from disk drive 3. It
is shaped and placed on output pin 13.

4

DRD4

READ DATA 4

I

This signal is data read from disk drive 4. It
is shaped and placed on output pin 13.

5

DRH

DRIVE SELECT
HIGH

I

Most significant bit of the drive select
number. Must be encoded externally.

6

DRL

DRIVE SELECT
LOW

I

Least significant bit of drive select number.
Must be encoded externally.

7

HD2

HEAD SELECT 2

I

Bit 2 of the head select number. Must be
encoded externally.

8

HD1

HEAD SELECT 1

I

Bit 1 of the head select number. Must be
encoded externally.

9

HDO

HEAD SELECT 0

I

10

MR

MASTER RESET

I

Bit 0 of the head select number. Must be
encoded externally.
Asserted, it initializes all internal logic
including the SDH Register.

11

BCS

BUFFER CHIP
SELECT

I

Asserted, this signal asserts RCE.

12

BCR

I

This signal resets the buffer address counter
to zero making A10 thru A15
O.

13

RD

BUFFER COUNTER
RESET
READ DATA

0

This is the MFM data read from the disk,
shaped and made compatible with the
WD1010-05.

14

BRDY

BUFFER READY

0

This signal is asserted when the buffer
counter (A10 thru A15) has reached the sector size specified in the SDH Register, 128,
256, 512, or 1024.

15

DRUN

DATA RUN

0

16

CS

CHIP SELECT

I

This signal is asserted when a field of ones
or zeroes has been detected.
'Must be asserted to write into the SDH
Register, increment.....!lJ§ Buffer Address
Counter, and assert RCE.

WE

READ ENABLE

I

Must be asserted to write into the SDH
Register. WE or RE must be asserted to increment the Buffer Address Counter.

18

RE

READ ENABLE

I

RE or WE must be asserted to increment
the Buffer Address Counter.

19

DRTIM

DRUN TIMING

I

An external load used to adjust DRUN to
nominal pulse width of 250 nsec.

20

Vss
RDTIM

GROUND

I

Ground.

RD TIMING

I

An external load for adjusting the pulse width
of RD. 1K ohms creates approx. 90 nsec.

A2
thru
AO

ADDRESS 2
thru
ADDRESS 0

I

A2 thru AO are used to address the SDH
6) and increment the BufRegister (A2-AO
fer Address Counter (A2-AO
0).

17

21
22
thru
24

4-32

MNEMONIC

-

PIN NAME

=

=

=

Winchester Disk Support Devices

PIN DESCRIPTION (Continued)
PIN
NUMBER
25
thru
31
32

MNEMONIC

PIN NAME

1/0
I

DO
thru
D6
BClR

DATA 0
thru
DATA 6
BU FFER CLEAR

33

RCE

RAM CHIP ENABLE

0

34
thru
39
40

A10
thru
A15

BUFFER ADDRESS
10 thru 15

0

Vcc

POWER SOURCE

0

FUNCTION
7-Bit data bus used to write into the SDH
Register.
Asserted, this signal indicates that the Buffer Address Counter has been cleared.
Asserted by BCS, or CS and AO thru A2 equal
to zero. Used to enable access to the data
buffer.
Buffer Address Counter. Used to address the
Data Buffer.

+ 5V

Power Supply

ARCHITECTURE
The WD1100-21 is composed of a 7-Bit SDH Register
(the extension bit, bit 7 is not included), 11-Bit Sector Buffer Counter, and miscellaneous control signals.
The content of the SDH Register is used to select the
drive and head, and limit the Sector Buffer Counter
to the size decoded by bits 5 and 6.

BCS------------------~
AO-A2 ------r------1
CS

Figure 1 is a block diagram illustrating the relationship of the timing and control Signals with the SDH
Register and Sector Buffer Counter.

~~------------------------------------~RCE

----,r--~----100 nsec, RST initializes the controller.
-Used with 1/0, CID, and REO to indicate type
of transfer. For example, during the Message
Byte Transfer Phase, one byte of zeros is sent
to the Host to indicate the command is
complete.
An asserted signal gives control of the bus to
the address (0 through 7) which is selected by
jumpering at location RN2.
--Used with 1/0, MSG, and REO to indicate type
of transfer.
Indicates to the Host that the controller is ready
for data transfer.

-

DO
thru
D7

SIGNAL NAME

---

DATA 0
thru
DATA 7

NOT
CONNECTED
--

BSY

-MSG

-

SEL

-

CID

-REO

1/0

--

RESET

I

MESSAGE

0

SELECT

I

CONTROL/DATA

0

REOUEST

0

--

INPUTIOUTPUT

0

Identifies the direction of transfers between
the Host and WD1002-SAS. I asserted
input
to Host; 0 asserted
output to controller.

=

=

*The 1/0 column is in relation to the WD1002-SAS and not the Host.
HOST INTERFACE BUS OPERATION
The timing sequence for bus operations includes
five phases:

6-34

1. Reset Phase. Occurs when RESET is asserted.
Used by the Host to force the controller(s)
on the bus to the same state it was in following
a power on condition.

Winchester Board Products

2. Bus Free Phase. Occurs between the completion
of one transaction (Bus Release Phase) and
the initiation of the next transaction (Target
Selection Phase). Also occurs during the time
in which no unit has control of the bus. All
eight control lines and eight data lines are
de-asserted.
3. Target Selection Phase. Occurs when the Host
QlQges a target address on the bus and asserts
SEL. and the addressed controller asserts
BSY. The Host then de-asserts SEL before completing the phase.
The target address consists of one asserted and
seven de-asserted DO through 07 signals. The
controller's default address of 0 corresponds to
an asserted DO, which may be changed to any
address by jumpering. Two controllers may not
use the same address.
4. Information Transfer Phase. Used to transfer one
or more bytes on th_e bu.§. The tYRe of transfer is
determined by the 1/0, C/O, and MSG
signal
codes on the lines (providing five valid
combinations) as shown in Table 3, and as
qualified by request. A valid combination indicates to the Host the types of byte transfers that
are to follow.
The following are used to transfer information:
• Command Block Transfer Phase. Used to send a
block of command bytes from the Host to the controller, specifying the operation to be performed
(e.g. Format Disk).
•

•

Data Block Transfer Phase. Used primarily to send
one or more sectors of data either from or to the
Host. Also used to send a block of parameters to
the controller or to the Host.
Status Byte Transfer Phase. During this phase, one
byte is sent to the Host indicating the status of
the operation.

•

Message Byte Transfer Phase. One byte of zeros is
sent to the Host to indicate the command is
complete.
For each byte transferred, the following operations
occur in sequence to perform the asynchronous
handshake:

•
•
•
•

Controller asserts REO
Host asserts ACK
Controller de-asserts REO
Host de-asserts ACK
For controller-to-Host transfers, the eight bits
are valid on the bus at least 100 nsec before REO
is asserted. Host-to-controller transfers are
valid on the bus no later than 250 nsec after ACK
is asserted. It is recommended that before asserting ACK, make sure the data is valid. (Note: For
debugging, bytes are valid on the bus when REO
is de-asserted during any transfer.)
5. Bus Release Phase. Occurs when BSY is
deasserted. This phase signals the Host that the current transaction has terminated and the
associated selected target is no longer controlling the bus.
BUS PHASE SEOUENCING
A Reset Phase may occur any time and is followed
by the Bus Free Phase. In the absence of a Reset
Phase, the bus alternates between the Bus Free
Phase and one transaction. A transaction always consists of the following:
1. One Target Selection Phase
2. One Command Block Transfer Phase
3. Zero or more Data Block Transfer Phase(s) - Type
and number determined by the preceding Command Block Transfer Phase
4. One Status Byte Transfer Phase
5. One Message Byte Transfer Phase
6. One Bus Release Phase
During a transaction, all Data Block Transfer Phases
are the same size and are sent in the same direction.
DRIVE INTERFACES
WINCHESTER DRIVE CONTROL CONNECTOR
The Winchester drive control connector, a 34 pin
printed circuit card edge connector, is a low- speed
bus daisy-chained to each Winchester drive in the
system. To terminate the control signals on the
WD1002-SAS properly, the last drive in the daisy-chain
must have a 220/330 ohm resistor pack installed. The
pin description and control signals are provided in
Table 4.

TABLE 3. INFORMATION TRANSFER PHASE
SIGNAL MNEMONIC
1/0

CID

1
1
0
0
0

0
1
1
0
0

MSG
1
1
1
1
0

Winchester Board Products

TRANSFER TYPE
Command Block
Data Out Block
Data In Block
Status Byte
Message Byte

NUMBER OF BYTES
6
3, 8, 128, 256, 260, 512, 516, or 1024
1,4, 128, 256, 260, 512, 516, or 1024
1
1

6-35

TABLE 4. WINCHESTER DRIVE CONTROL CONNECTOR (P2) PIN DESCRIPTION

=E
c......
o
o

SIG.
GND

SIGNAL
MNEMONIC

SIGNAL NAME

110

FUNCTION

2

RWC

REDUCE WRITE
CURRENT

o

RWC is asserted when the cylinder specified
by the Set Parameters Command is reached.

3

4

HS2

HEAD SELECT 2

o

HS2 is one of three Head Select signals
decoded by the drive to select one of eight RIW
heads.

5

6

WG

WRITE GATE

o

WG is asserted when valid data is to be written
on disk. WD1002-SAS de-asserts this signal when
a WF is detected. Special circuitry is included
to ensure the output does not glitch during power
on.

7

8

SC

SEEK COMPLETE

SC informs the WD1002-SAS the head of a
selected drive reached the desired cylinder and
has stabilized.

9

10

TKOOO

TRACK 000

The drive asserts this signal when the RIW heads
are positioned over the outermost cylinder,
cylinder O.

11

12

WF

WRITE FAULT

WF is asserted by the selected drive when a
write error occurs. The command in progress
aborts and no other disk command can be executed while this signal is asserted.

13

14

15

16

17

18

HS1

HEAD SELECT 1

19

20

INDEX

INDEX PULSE

This signal indicates the start of a track. It is
used as a synchronization point during formatting and as a time-out mechanism for
retries. This signal pulses once for each disk
revolution.

21

22

DRDY

DRIVE READY

Informs the controller that the drive motor is up
to speed.

23

24

STEP

STEP PULSE

o

25
27

26

DSELO

DRIVE SELECT 0

28

DSEL1

DRIVE SELECT 1

o
o

I\)

~
en

SIG.
PIN

29
thru
32
33

6-36

HEAD SELECT 0

o

HSO is one of three Head Select signals
decoded by the drive to select one of eight RIW
heads.

o

HS1 is one of three Head Select signals
decoded by the drive to select one of eight RIW
heads.

NOT CONNECTED

STEP, together with DIRIN, positions the heads
to the desired cylinder. STEP pulses once for
each step. DIRIN determines the step direction.
DSELO is used to select drive O.
DSEL 1 is used to select drive 1.

NOT CONNECTED

34

DIRIN

DIRECTION IN

o

DIRIN determines the direction the RIW heads
take when the step line is pulsed. De-asserted
= out; asserted = in.

Winchester Board Products

WINCHESTER DRIVE DATA CONNECTORS

TABLE 5.
WINCHESTER DRIVE DATA CONNECTOR - J2,J3

Connectors J2 and J3 allow data transfer between
the controller and each drive. The data lines are differential in nature and must be connected to each
drive with its own cable, i.e., drive 0 to J2 and drive
1 to J3. Each drive is radially connected with a maximum cable length of 10 feet. Each data connector
is a 20·pin vertical header on 0.1 inch center. Data
connector pin descriptions and signals are given in
Table 5.

SIG.
GND

SIG.
PIN
1

SIGNAL NAME
NC
GND
NC
GND
NC
GND
NC
GND
NC
NC
GND
GND
+ MFM Write Data
-MFM Write Data
GND
GND
+ M FM Read Data
-MFM Read Data
GND
GND

1/0

2
3
4
5
6
7

FLOPPY DRIVE CONTROL AND DATA CONNECTOR

8

The Floppy drive control signals function in a manner similar to the Winchester except both the control and data signals are transmitted on the same
connector. The connector is daisy-chained to each
drive. To properly terminate each TTL level output
signal from the WD1002-SAS, the last drive in the
daisy·chain must have line terminations installed as
specified by the drive manufacturer. A flat ribbon
cable, or twisted-pair, of less than 10 feet should be
used. The connector is a 34-pin vertical header on 0.1
inch center. Pin description and signals are given in
Table 6.

9
10
11
12
13
14

0
0

17
18

I
I

15
16
19
20

TABLE 6. FLOPPY DRIVE CONTROL AND DATA CONNECTOR (J4) PIN DESCRIPTION
SIG.
GND

SIG.
PIN

1 thru 4
5

6

7

9

SIGNAL
MNEMONIC

---

SIGNAL NAME

DSELO

DRIVE SELECT 0

0

8

INDEX

INDEX PULSE

I

10

DSEL1

DRIVE SELECT 1

0

11 thru 14

FUNCTION

I/O

NOT CONNECTED

---

DSELO is used to select drive
SA450, this is drive 4.)

o.

(Note: On an

This signal indicates the start of a track. It is
used as a synchronization point during formatting and as a time-out mechanism for
retries. This signal pulses once for each disk
revolution.

--

DSEL 1 is used to select drive 1.

NOT CONNECTED

15

16

MO

MOTOR ON

0

17

18

DIRIN

Directly controls the Floppy drive's power-on of
the spindle motor. A 1-second delay occurs
after the motor is on.

DIREC liON IN

0

DIRIN determines the direction the RIW heads
take when the step line is pulsed. De-asserted
out; asserted
in.

19

20

STEP

STEP PULSE

0

21

22

WD

STEP, together with DIRIN, positions the heads
to the desired cylinder. STEP pulses once for
each step. DIRIN determines the step direction.

WRITE DATA

0

23

24

WG

Provides data to be written on the diskette and
is enabled by WG asserted.

WRITE GATE

0

WG is asserted when valid data is to be written
on disk. It is used by the drive to enable the
write current to the head.

--

Winchester Board Products

=

=

6-37

:E
c
......
o
o

I\.)

en
»
en

TABLE 6. FLOPPY DRIVE CONTROL AND DATA CONNECTOR (J4) PIN DESCRIPTION (CONTINUED)
SIG
GND

SIG
PIN

SIGNAL
MNEMONIC

25

26

TROO

27

28

29

I/O

DESCRIPTION

TRACK 00

I

WPRT

WRITE PROTECT

I

30

RD

READ DATA

I

31

32

SS

SIDE SELECT

0

The drive asserts this signal when the RIW
heads are positioned over the outermost cylinder.
Indicates to the controller a write·protected
diskette is installed. When WPRT is asserted,
no data is written to the diskette.
Provides raw data (clock and data combined)
as detected by the drive circuitry.
SS determines the side of the diskette to be
used. Asserted = select side 0; de-asserted =
select side 1.

33

34

--

SIGNAL NAME

NOT CONNECTED

POWER CONNECTOR

Command Class

A 4'pin amp connector P1 provides power input to the
WD1002-SAS:

Designates whether the command is used in opera·
tion (class 0) or for diagnostic (class 7}. Command
classes 1 through 6 are reserved for future use.

SIG
GND

SIG.
PIN

OP Code

SIGNAL NAME

1

An operation code is used in each command class
to identify the function of the commands, e.g., read
and write.

NOT CONNECTED
GND
GND
+ 5V Regulated

2
3
4

Logical Unit Number

WD1002-SAS COMMAND BLOCK
A transaction is initiated by the Host, instructing the
controller to execute a command. During the Command Block Transfer Phase, six bytes of information
specifying the command are transferred to the con·
troller. Figure 2 defines the contents of each byte in
the Command Block. These parameters are sent to
the WD1002-SAS by the Host to perform specific transactions.

BYTE
0
1

7

I

6

I

5

COMMAND
CLASS
LOGICAL
UNIT NUMBER

BITS
4 I 3

I

2

I

1

I

OP CODE
LOGICAL SECTOR
ADDRESS
(BITS 20 THRU 16)

2

LOGICAL SECTOR ADDRESS
(BITS 15 TH RU 8)

3

LOGICAL SECTOR ADDRESS
(BITS 7 THRU 0)

4

INTERLEAVE OR BLOCK COUNT

5

CONTROL BYTE

FIGURE 2. COMMAND BLOCK DESCRIPTION

6-38

0

There are 8 logical unit numbers. For example, logical
unit numbers 0 and 1, respectively. The Floppy logical
unit numbers are 4 and 5.
Logical Sector Address
This address is a 21-bit unsigned integer specifying
a unique physical sector. The following equation
shows the one-to·one ratio between the set of logical
sector addresses and the set of physical sectors:
Logical Sector Address = (((Cylinder Number*
Number of Heads) + Head Number)* Number of
Sectors per Track) + Sector Number
Each format command begins operation at the beginning of the track containing the specified sector.
Interleave or Block Count
The interleave factor is used by format commands.
The 3:1 ratio is the minimum operational interleave;
however, the disk also may be formatted at a 1:1 ratio.
The maximum interleave is equal to the sectors·pertrack minus one. Block count specifies the number
of sectors to be used for each data transfer command. The block count is an unsigned, no-zero
integer. A block count of all zeros equals 256 sectors.
Control Byte
The descriptions and contents of the Control Byte for
both the Winchester and Floppy drives are shown in
Table 7.

Winchester Board Products

TABLE 7. CONTROL BYTE DESCRIPTION
BIT

WINCHESTER CONTENTS

0
thru
3
4

Step Option. Unsigned 4·bit integers corres·
ponding to stepping rates in Table 8.

Reserved for future use. Must be O.

MSB
Bit 5

LSB
Bit 4

0
0
1
1

0
1
0
1

Format Data:
o = 6C Hex
1 = Contents of Sector Buffer (Data is pro·
vided by the Write Sector Buffer Command)
Error Correction:
o = Correction After Two Identical Syndromes
1 = Correction After One Syndrome
Error Retry:
o = Enable Retry
1 = Disable Retry

5

6

7

FLOPPY CONTENTS

Step Option. Unsigned 4·bit integers corres·
ponding to stepping rates in Table 8.

Sector Size
128
256
512
1024

bytes/sector
bytes/sector
bytes/sector
bytes/sector

Not used. Must be O.

Not used. Must be O.

TABLE 8. STEP OPTIONS

OPTION

0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F

WINCHESTER STEP RATE·

3 msec per step * *
Half-step for Seagate ST506 (MLC2); fast step for Texas Instruments drives
3 msec per step
Half-step for Seagate ST506 (MLC2); fast-step for Texas Instruments drives
200 J-lsec per step (appropriate for buffered-steps on drives manufactured by Computer Memories Inc. and Rotating Memories Inc.)
70 J-lsec per step
3 J-lsec per step
15 J-lsec per step
2 msec per step for Olivetti-561
3 msec per step
3 msec per step
3 msec per step
3 msec per step
3 msec per step
3 msec per step
3 msec per step

FLOPPY
STEP RATE

15 J-lsec
1 msec
2 msec
3 msec
4 msec
5 msec
6 msec
8 msec
10 msec
12 msec
14 msec
16 msec
18 msec
20 msec
25 msec
40 msec

* For the Seek Command, buffered-seeks(Options 4 through 7) do not wait for seek completion. All other seeks
wait for seek completion.
* *This is the preferred 3 msec step rate.

Winchester Board Products

6-39

COMMAND DESCRIPTIONS

:e
g

The WD1002-SAS commands are summarized in Table 9. Each command is listed with its Command Block
contents.

I\,)

TABLE 9. SUMMARY OF COMMANDS

o
o

~

CONTROL BYTE

en

I lSB
I
IMSB
SS
SS STEP

CLASS

OP
CODE

lUN
(W/F)

lSA

INT/BlK

R

TEST DRIVE
READY

0

00

V\'N)

n

n

n

n

n

n

n

n

RECALIBRATE

0

01

V\'N)
V(F)

n
n

n
n

V
n

V
n

n
n

n
n

n
n

V
V

REQUEST
STATUS

0

03

V\'N/F)

n

n

n

n

n

n

n

n

FORMAT
DRIVE

0

04

V\'N)

V*

V(INT)

V

V

V

n

n

V

CHECK TRACK
FORMAT

0

05

V\'N)

V*

V(INT)

V

V

V

n

n

V

FORMAT
TRACK

0

06

V\'N)
V(F)

V*
V*

V(INT)
V(INT)

V
n

V
n

V
n

n
V

n
V

V
V

FORMAT BAD
TRACK

0

07

V\'N)

V*

V(INT)

V

V

V

n

n

V

READ
SECTOR

0

08

V\'N)
V(F)

V
V

V(BLK)
V(BLK)

V
n

V
n

V
n

n
V

n
V

V
V

WRITE
SECTOR

0

OA

V\'N)
V(F)

V
V

V(BLK)
V(BLK)

V
n

V
n

V
n

n
V

n
V

V
V

SEEK

0

OB

V\'N)
V(F)

V*
V*

n
n

V
n

V
n

V
n

n
V

n
V

V
V

SET
PARAMETERS

0

OC

V\'N/F)

n

n

n

n

n

n

n

n

RETURN LAST
CORRECTED
BURST
LENGTH

0

OD

V\'N)

n

n

n

n

n

n

n

n

FORMAT
ALTERNATE
TRACK

0

OE

V\'N)

V*

V(INT)

V

V

V

n

n

V

WRITE
SECTOR
BUFFER

0

OF

n\'N)

n

n

n

n

n

n

n

n

READ SECTOR
BUFFER

0

10

n\'N)

n

n

n

n

n

n

n

n

RAM
DIAGNOSTIC

7

00

n\'N/F)

n

n

n

n

n

n

n

n

DRIVE
DIAGNOSTIC

7

03

V\'N)

n

n

V

V

V

n

n

V

CONTROLLER
DIAGNOSTIC

7

04

n\'N/F)

n

n

n

n

n

n

n

n

READ LONG

7

05

V\'N)

V

V(BLK)

V

V

V

n

n

V

WRITE LONG

7

06

V(W)

V

V(BLK)

V

V

V

n

n

V

COMMAND

6-40

I

C

I

F

Winchester Board Products

LEGEND:
Must be a valid parameter
Not used (should be 0 for future compatibility).
LUN(W/F)Logical Unit Number of Winchester drives
I NT
Interleave factor.
BLK
Block Count.
R
Error Retry. Bit 7 of the Control Byte for Winchester drives.
C
Error Correction. Bit 6 of the Control Byte
for Winchester drives.
V
n

Each Wd1002-SAS command is described briefly
in the following paragraphs. Refer to Table 9 for
their parameter contents.
1. TEST DRIVE READY (CLASS 0, OP CODE 00)
This command reads the drive's status. For
Winchester drives supporting buffered-seeks, this
command is useful for determining the first drive
to reach its selected track.
This command is not used for the Floppy drives.

F

Format Dat6a. Bit 5 of the Control Byte for
Winchester Drives.
MSB SS Most Significant Bit Sector Size. Bit 5 of the
Control Byte for Floppy drives.
LSB SS Least Significant Bit Sector Size. Bit 4 of the
Control Byte for Floppy drives.
S T E P Stepping Rate. Bits 0 through 3 of the Control Byte as defined in Table 8 for Winchester and Floppy drives.

BYTE
0
1

No Error
Write Fault
Drive Not Ready
Buffered-Seek in Progress
Invalid Command

2. RECAUBRATE (CLASS O. OP CODE 01)
This command positions the R/W heads over the
outer most cylinder, cylinder O.
Possible Error Codes

00
03
04
06
32

No Error
Write Fault
Drive Not Ready
Track 0 Not Found
Invalid Command

3. REQUEST STATUS (CLASS 0, OP CODE 03)
This command sends the Host four status bytes of
error information (as shown in Figure 3) for the
specified drive.

I

6

I

5

AVF! 0 !
LOGICAL
UNIT NUMBER

I

BITS
4 I 3 I 21 1 1 0
ERROR CODE
LOGICAL SECTOR
ADDRESS
(BITS 20 THRU 16)

2

LOGICAL SECTOR ADDRESS
(BITS 15 THRU 8)

3

LOGICAL SECTOR ADDRESS
(BITS 7 THRU 0)

Possible Error Codes

00
03
04
08
32

7

AVF
Address valid flag. Indicates that the Logical Sector
Address fields are valid.
FIGURE 3_ FOUR STATUS BYTES
The information sent by the controller to the Host via
the Request Status Command includes these
conditions:
% If the most recent non-Request-Status Command
to the specified drive requires a logical sector
address, then the address valid flag is 1.
% If an error has occurred on the preceding command and the address valid flag is 1, then the
logical sector address indicates the record on
which the error occurred.

% If no error has occurred on the preceding command to format the track, format the drive, or format the alternate track, then the logical sector
address indicates one track beyond the last track
accessed.
% If no error has occurred and the command is to
check the track format, format the bad track, or
is not a format command, then the logical sector
address indicates the last track or sector

Winchester Board Products

6-41

Possible Error Codes

:E
c

...L

00

32

The WD1002-SAS error code descriptions are summarized in Table 10_

No Error
Invalid Command

o
o

TABLE 10. ERROR CODE DESCRIPTIONS

~
I

~
en

ERROR
CODE

ERROR NAME

TYPE OF ERROR

00
03

No Error
Write Fault

Disk Drive
Disk Drive

04

Drive Not
Ready
Track 0
Not Found

Disk Drive

06

Disk Drive

08

Buffered-Seek
in Progress

Disk Drive

10

Write
Protected
CRC Error

Controller

Address Mark
Not found
Uncorrectable
Data Error

Controller

Data
Address Mark
Not Found
Seek Error

Controller

24

Error Burst
Corrected

Controller

25

Bad Track

Controller

26

Format Error

Controller

28

Illegal (Direct)
Access to an
Alternate Track

Controller

11
12

17

18

21

6-42

Controller

Controller

Controller

DESCRIPTION
No error has occurred_
Indicates write..J!llrrent occurred when WG is deasserted, or a ~is not asserted and a drive is
selected while WG is asserted.
The selected drive's DRDY is de-asserted. Indicates
the motor of the selected drive is not up to speed.'
This code is returned by the Recalibrate Command.
Indicates the TKOOO or TROO from the selected
drive was not asserted after the maximum number of
steps (up to 1024 for the Winchester; up to 256 for
the Floppy) toward cylinder O.
This code is returned by the Test Drive Ready Command, indicating the selected drive (Winchester supporting buffered-seeks) is busy performing a
buffered-seek.
This code is returned by Floppy drives when write-protect tab is detected on the diskette.
Indicates a CRC error in the data field is detected during a Floppy command execution after eight retries.
This code is returned when address is not found during
Floppy command execution after eight retries.
For a Floppy drive, this code indicates a CRC error in
the data field. For a Winchester drive, this code indicates one or more error bursts in the data field are
beyond the ECC's ability to correct. Data for the sector in error is not sent to the Host.
This code is returned by Winchester drives. Indicates
the selected sector's header is found, but its Address
Mark is not detected.
Indicates the controller cannot locate the specified
address on the disk.
A code returned by Winchester drives. Indicates the
ECC successfully corrected an error. The corrected sector data is sent to the Host (Note: This is the only error
condition in which sector data is sent to the Host.)
Usually indicates access of a formatted bad track. Also
indicates a formatted Bad-Track-With-Alternate is faulty
and multiple, duplicate pointers to the Alternate Track
cannot be read.
This code is returned by the Check Track Format Command. Indicates a track is not formatted, a track is not
formatted with the specified interleave factor, or at least
one sector header is unreadable. This code is also
returned by the drive diagnostic, indicating a Bad-TrackWith-Alternate does not contain a valid pointer to the
Alternate Track.
The specified address is not a valid address for an
Alternate Track.

Winchester Board Products

TABLE 10. ERROR CODE DESCRIPTIONS (CONTINUED)
ERROR
CODE

ERROR NAME

TYPE OF ERROR

DESCRIPTION

29

Alternate
Track
Already Used

Controller

This code is returned by the Format Alternate Track
Command. Indicates the specified Alternate Track is
already an alternate or bad track.

30

Alternate Track
Not Marked
as Alternate

Controller

Indicates access of a Bad-Track-With-Alternate caused
access to an Alternate Track not marked as an Alternate Track.

31

Alternate
Track Equals
Bad Track

Controller

This code is returned by the Format Alternate Track
Command. Indicates the same track is specified as
the Bad Track and the Alternate Track.

32

Invalid
Command

Command

Indicates an invalid command class, operation code,
logical unit number, interleave factor, or step number.

33

Invalid
Sector Address

Command

Indicates the specified address has reached the file
device's given range, exceeding capacity.

48

RAM Failure

Miscellaneous

Indicates the external RAM failed.

49

ROM Failure

Miscellaneous

Indicates ROM checksum does not match the calculated checksum.

4. FORMAT DRIVE (CLASS 0, OP CODE 04)
This command formats from the specified track to
the end of the disk. The previous contents of the formatted tracks are ignored.
This command is not used for the Floppy drives.
Possible Error Codes
00
No Error
03
Write Fault
a4 Drive Not Ready
21
Seek Error
32
Invalid Command
33
Invalid Sector Address
5. CHECK TRACK FORMAT (CLASS 0, OP CODE 05)
This command verifies whether the specified track
is formatted with the specified interleave factor. It
does not read the sector data fields.
This command is not used for the Floppy drives.
Possible Error Codes
00
No Error
03
Write Fault
a 4 Drive Not Ready
21
Seek Error
26
Format Error
32
Invalid Command
33
Invalid Sector Address
6. FORMAT TRACK (CLASS 0, OP CODE 06)
This command formats the specified track, ignoring
the current contents. For Floppy drives, 5E Hex is written in the data field.
Possible Error Codes
00
No Error
a3 Write Fault
a4 Drive Not Ready

Winchester Board Products

21
Seek Error
32
Invalid Command
33
Invalid Sector Address
7. FORMAT BAD TRACK (CLASS 0, OP CODE 07)
This command formats the specified track with a Bad
Block Mark in each sector header, ignoring the
previous contents. The contents of a bad track are
not accessible.
This command is not used for the Floppy drives.
Possible Error Codes
00
No Error
03
Write Fault
a4 Drive Not Ready
32
Invalid Command
33
Invalid Sector Address
8. READ SECTORS (CLASS 0, OP CODE 08)
Beginning with the specified sector, this command
reads the specified number of consecutive sectors.
Possible Error Codes
00
No Error
a3 Write Fault
04
Drive Not Ready
CRC Error
11
12
Record Not Found
17
Un correctable Data Error
18
Address Mark Not Found
21
Seek Error
24
Error Burst Corrected
25
Bad Track
28
Illegal (Direct) Access to an Alternate Track
30
Alternate Track Not Marked as Alternate
32
Invalid Command
33
Invalid Sector Address

6-43

9. WRITE SECTORS (CLASS 0, OP CODE OA)

:ec

Beginning with the specified sector, this command
writes the specified number of consecutive sectors.

o
o

Possible Error Codes

-'-

N
I

~

en

00
No Error
03
Write Fault
04
Drive Not Ready
10
Write-Protected
12
Record Not Found
18
Address Mark Not Found
21
Seek Error
25
Bad Track
28
Illegal (Direct) Access to an Alternate Track
30
Alternate Track Not Marked as Alternate
32
Invalid Command
33
Invalid Sector Address
10. SEEK (CLASS 0, OP CODE OB)
This command moves the read/write head to the
specified cylinder. It does not read any sector header
to verify start or end position.

0
1
2
3
4
5
6
7

Number of
Number of
Bits 4 thru
Bits 0 thru
Start RWC
Start RWC
Start Write
MSByte
Start Write
LSByte
Bits 4 thru
Bits 0 thru

Cylinders MSByte
Cylinders LSByte
7
Must be 0
3
Numbers of Heads
Cylinder Number MSByte
Cylinder Number LSByte
Precomp Cylinder Number

=
=

Precomp Cylinder Number
\

7
3

= Must be 0
= Maximum Length of
Error Burst To Be
Corrected

For Floppy Drives, power up or reset sets the
parameters to the following defaults:

PARAMETER

Possible Error Codes

00
No Error
03
Write Fault
04
Drive Not Ready
32
Invalid Command
33
Invalid Sector Address
11. SET PARAMETERS (CLASS 0, OP CODE OC)
For Winchester Drives, the following parameters are
set to their respective default values upon power up
or reset:
PARAMETER
Number of Cylinders
Number of Heads
Starting RWC Cylinder: The specified
number for this parameter is rounded
down to the nearest integer in multiples of four. For example, 0,4,8,12, ...
... ,. .. ,1020.
Starting Write Precomp Cylinder
Maximum Length of Error Burst To
Be Corrected: For most applications,
the maximum length of error burst
to be corrected should be approximately 5 because correcting longer
bursts increases the chance of
miscorrecting.

DESCRIPTION

BYTE

DEFAULT
VALUE
153
4
128

Number of Cylinders
Number of Heads
Tracks Per Inch Flag for 96 tpi
Diskette

40
2
0

Floppy Parameter Block

The parameters sent by the Host to the WD1002-SAS
in the following format replace the default values
shown above:
BYTE

DESCRIPTION

0
1
2

Number of Cylinders MSByte
Number of Cylinders LSByte
Must be 0
Bits 4 thru 7
Bits 0 thru 3
Number of Heads
If 48 or 96 Tracks Per Inch diskette is
0
used in a drive with the same TPI
If 48 Tracks Per Inch diskette is used in
a 96 TPI drive
1
Zeros
Zeros
Zeros
Zeros

3

64
11

DEFAULT
VALUE

=
=

=

=

4
5
6
7

Possible Error Codes

00
32

No Error
Invalid Command

Winchester Parameter Block
The parameters sent by the Host to the WD1002-SAS
in the following format replace the default values
shown above:

6-44

Winchester Board Products

12. RETURN LAST CORRECTED BURST LENGTH
(CLASS 0, OP CODE OD)
This command sends the Host one byte of data con·
taining the length of the most recently corrected error
burst. If no error burst has been corrected since the
last power·up or reset, then Error Burst Length Block
of zero is sent to the Host.
This command is not used for the Floppy drives.
Possible Error Codes

00

No Error

This command formats the specified track as a Bad·
Track·With·Alternate. Then it formats the specified
Alternate Track with the specified interleave factor.
The alternate Track is specified by the Host by sen·
ding the following Alternate Sector Address Block to
the WD1002-SAS after the device Control Byte:

7

I

6

I

This command is not used for the Floppy drives.
Possible Error Codes

00

No Error

16. RAM DIAGNOSTIC (CLASS 7,OP CODE 00)

13FORMAT ALTERNATE TRACK (CLASS 0, OP
CODE OE)

BYTE

15. READ SECTOR BUFFER (CLASS 0, OP CODE 10)
This command sends current contents of the
WD1002- SAS Sector Buffer the Host. The Host
accepts as many bytes as there are in a sector on
Logical Unit O.

5

BITS
4 I 3 I 2 I 1 I
LOGICAL SECTOR
ADDRESS
(BITS 20 THRU 16)

a

This command writes and reads various patterns into
the Sector Buffer to test. This command also destroys
the previous contents of the Sector Buffer.
Possible Error Codes

00
48

no Error
RAM Failure

17. DRIVE DIAGNOSTIC (CLASS 7,OP CODE 03)
This command recalibrates the selected drive, then
scans the ID on each track. This command does not
write to the disk or send any sector data to the Host.

This command is not used for the Floppy drives.

The drive diagnostic is used to verify that at least one
sector header can be read on each track. When a
track formatted as bad Track, Bad·Track· With·
Alternate, or Alternate Track is encountered, an error
is not reported. However, an error is reported when
a Bad·Track·With·Alternate is encountered with the
Alternate Track Not Marked as an Alternate. If no
pointer to the Alternate Track can be read from a Bad·
Track·With·Alternate then a Bad Track error is
reported.

Possible Error Codes

This command is not used for the Floppy drives.

a

a

1

LOGICAL SECTOR ADDRESS
(BITS 15 THRU 8)

2

LOGICAL SECTOR ADDRESS
(BITS 7 TH RU 0)

00
a3
a4
21
29
31
32
33

No Error
Write Fault
Drive Not Ready
Seek Error
Alternate Track Already Used
Alternate Track Equals Bad Track
Invalid Command
Invalid Sector Address

14. WRITE SECTOR BUFFER (CLASS O,OP CODE OF)

Possible Error Codes

00

a3
a4
21
25
3a
32

No Error
Write Fault
Drive Not Ready
Seek Error
Bad Track
Alternate Track Not Marked as Alternate
Invalid Command

18. CONTROLLER DIAGNOSTIC (CLASS 7,OP CODE
04)

This command writes data from the Host to the
WD1002-SAS Sector Buffer. The Host sends as many
bytes as there are in a sector on Logical Unit O. This
data is not written to any disk. The Write Sector Buf·
fer Command provides the data used by format com·
mands having bit 5 of the Control Byte = 1.

This command calculates a checksum for the ROM
program, and tests the microprocessor and Sector
Buffer. This command does not access any disk drive
but destroys the previous contents of the Sector
Buffer.

This command is not used for the Floppy drives.

Possible Error Codes

Possible Error Codes

00

No Error

Winchester Board Products

00
48
49

No Error
RAM Failure
ROM Failure

6-45

19. READ LONG (CLASS 7,OP CODE 05)

COMMAND STATUS BYTE

Beginning with the specified sector, this command
reads the specified number of consecutive sectors
and an additional four ECC data bytes per sector provided by the controller.

After each command is executed, the WD1002-SAS
sends a Command Status Byte to the Host to determine whether the command is completed successfully. The logical unit number returned represents
the contents of the logical unit field in the drive control block.

This command is not used for the Floppy drives.
Possible Error Codes

00
03
·04
18
21
25
28
30
32
33

No Error
Write Fault
Drive Not Ready
Address Mark Not Found
Seek Error
Bad Track
Illegal (Direct) Access to an Alternate Track
Alternate Track Not Marked as Alternate
Invalid Command
Invalid Sector Address

20. WRITE LONG (CLASS 7,OP CODE 06)
Beginning with the specified sector, this command
writes the specified number of consecutive sectors.
Following each sector, the Host sends the
WD1002-SAS an additional four ECC data bytes
(unaltered by the controller) which are written to the
disk as ECC bytes for the sector. This command is
useful for diagnostic purposes.

BITS

7

LUN
E

I

6
LUN

I

5

I
I

4

I

0

1

3
0

12 I
0 I
1

1
E

I
I

0
0

Logical Unit Number
Error Flag:
o = No Error
1 = Error

COMMAND COMPLETION BYTE

Immediately following each Command Status Byte,
the WD1002-SAS sends a Command Completion Byte
containing all zeros to the Host while MSG is asserted. This byte indicates to the Host that BSY will
be de-asserted, the bus is available for the next
command.

This command is not used for the Floppy drives.
Possible Error Codes

00
03
04
18
21
25
28
30
32
33

6-46

No Error
Write Fault
Drive Not Ready
Address Mark Not Found
Seek Error
Bad Track
Illegal (Direct) Access to an Alternate Track
Alternate Track Not Marked ,as Alternate
Invalid Command
Invalid Sector Address

Winchester Board Products

HOST INTERFACE TIMING

Timing diagrams are shown in Figures 4 through 6
and their values are given in Tables 11 and 12.

~
C
......
o
o

I\)

en
»
en

00 TERMINATES COMMAND

BUSy-----,

~--------------~I

REQ - - - - - - _ - ,

ACK---------~-~I

UO - - - - - - - - - - - -______________________

~~~~

~

r

~D---------~,,~_________________________J;f
MSG------------------------------------------------~

FIGURE 4. TYPICAL HOST·CONTROLLER BUS TRANSFER TIMING

Winchester Board Products

6-47

:ec
.....

o

I. . .

N

REQ----~I~

o

~

t----tCy

________

1
..
____~

-----4·~1

· f - - - - - - t C y - - - - . - ,..
~1

~

I

REQ----~LI
I

tRAL

-.J
I

I
tRAH
I
"1"~ltARLI

~tARH

I I I

tRAL tARH tRAH
. . . . . . . . . . . . . . II

I

L

I

ACK

~K----~~I

I~-------------

I

I

I

tADV

....,tSUR~

HtRDHr.-

DO-D7W11/1//$IIff/l~

X---

-+j

tRDH

~

~D7~______________~_______

FIGURE 5: HOST-TO-CONTROLLER TIMING

FIGURE 6: CONTROLLER-TO-HOST TIMING

TABLE 11HOST-TO-CONTROLLER TIMING PARAMETERS

TABLE 12.
CONTROLLER-TO-HOST TIMING PARAMETERS

txx
tCY *
tRALt
tARH
tRAHtt
tARL

MIN(nsec)

txx

1152

tCY *

a

tRALt

600

840

tARH

a

tRAHtt

200

488
375

tADv
TRDH

MAX(nsec)

a

=

*It conditions in t and tt are met, then tCY (typ)
1200 nsec and tCY max
1248 nsec.
tit tRAL =::; 89 nsec, then no wait states are inserted.
ttlt tRAH =::; 97 nsec, then no wait states are inserted.

=

One wait state

6-48

= 200 nsec.

MIN(nsec)

MAX(nsec)

1152

a
448

200

a

tARL

200

tSUR

125

tRDH

152

848

=

*It conditions in t and tt are met, then tCy(typ)
1200 nsec and tCY max
1248 nsec.
tit tRAL =::; 497 nsec, then no wait states are
inserted.
ttlt tRAH =::; 200 nsec, then no wait states are
inserted.

=

Winchester Board Products

WESTERN
c

o

R

P

0

DIGITAL

RAT

o

N

WD1002-WX1 Winchester Disk Controller
FEATURES

•

4.95" x 3.85" HALF-SLOT FORM FACTOR

•

•

IBM XT WINCHESTER CONTROLLER EMULA·
TION, IBM PC HOST INTERFACE

DIAGNOSTIC READS AND WRITES FOR CHECKING ERROR CORRECTION

•

AUTOMATIC FORMATIING

•

WD10C20 SELF·ADJUSTING DATA SEPARATOR

•

512 BYTES PER SECTOR

•

DATA RATES UP TO 5 MBITS/SEC

•

SECTOR INTERLEAVE CAPABILITY

•

CONTROLS UP TO 2 DRIVES USING SEAGATE
TECHNOLOGY ST506

•

MULTIPLE SECTOR READS AND WRITES

•

INTERNAL DIAGNOSTICS

•
•

SUPPORTS DRIVES OF ANY CONFIGURATION
UP TO 1024 CYLINDERS AND 16 R/W HEADS

•

DMA TRANSFER CAPABILITY

32·BIT ECC POLYNOMIAL FOR ERROR DETEC·
TION AND CORRECTION

•

AUTO-CONFIGURABLE BIOS ROM

•

COMPATIBLE WITH WD1002S·WX2

DESCRIPTION

The WD1002·WX1 Winchester Controller is a half·slot
sized IBM XT compatible board designed to interface
up to two hard disk drives. The drive interface is based
upon the Seagate Technology ST506. The drives need
not be of the same capacity or configuration. All
necessary receivers and drivers are included on the
board to allow direct connection to the drive(s).
The WD1002-WX1 interfaces directly with the Host I/O
bus via several interface buses. Data transfer to or
from the Controller can be either programmed I/O or
DMA.
The WD1002·WX1 is based on the WD1010A·05 Win·
chester Controller/Formatter, the WD1015 Control Processor, the WD110CO·17 Logic Array, and WD10C20
Data Separator.
Monitoring of the disk drive status lines is a major
function of the WD1010A·05. The WD1010A·05 also
controls passage of read and write data between the
WD10C20 Data Separator and the other major com·
ponents of the WD1002-WX1.

Winchester Board Products

The WD1015 controls and coordinates the activity of
the disk drive, WD1010A·05, and WD11COO·17. The
WD1002·WX1 receives and sends commands or
status information over the 8-bit multiplexed
address/data bus, ADO through AD7. Drive control
signals select the proper drive and head when
enabled by the WD1015.
The WD11COO·17 Logic Array incorporates several
functions in a single package. Implementation of
these functions occurs by combining random logic
and specialized circuits. The WD11COO·17 contains
the following circuits
Status ports
Read and write ports
Sector Buffer RAM addressing and control
Disk I/O Control
ECC
Reset Timing
The WD10C20 is a monolithic CMOS Data Separator.
This component interfaces the WD1010A·05 to a Win·
chester disk drive.

6-49

:ec
.....

0
0

~

=s

><
.....

--,H

...

..

ADDR.

T

I

/\.

~

S

-..

DATA

...

P

-

">

WD
11COO-1?

LOGIC
ARRAY

.

>---

CONTROL

RA

.')
RAM

R/W

~

D

ADO-AD?

r--

.....

~

f'

WDATA

RDATA
~

RWC

\)

\/

WD
10C20

I
.A

L{~
.....

D
I
S

•

K DATA/TIMING)

S
K

STATUS

-

0
T

CONTROL

D

,..--

>H

DATA

DECODE

CONFIG.

-

.....
BUFF.

...

ROM

0
S

..)

BIOS

K

WD

DATA

WD

1010A-05

SEPARATOR

1015

-...-

=>
DISK

,

-

•

---.

CLOCK

CONTROL

CONTROL

.

..:> '--

PROCESSOR

CONTROLLER

r

t
RESET

WD1002-WX1 BLOCK DIAGRAM

6-50

Winchester Board Products

WESTERN
COR

0

P

DIGITAL

RAT

o

N

:ec

WD10028-SHD Winchester Disk Controller

-'"

o
o

I\l

en

en

FEATURES

DESCRIPTION

•

SASI HOST INTERFACE

•

BAD TRACK MAPPING CAPABILITY

•

MULTIPLE SECTOR READS AND WRITES

The WD1002S-SHD is a stand alone, general purpose
Winchester Disk Controller Board, incorporating the
latest state-of-the-art surface mount technology and
designed to interface up to two Winchester Disk
Drives to a Host Processor. The Winchester Drive
signals are based upon the Seagate Technology
ST506 interface and other compatible drives. All
necessary receivers and drivers are included on the
board to allow direct connection to the drive.

•

SUPPORTS REMOVABLE MEDIA DRIVES

•

AUTOMATIC FORMATTING

•

ADJUSTMENT FREE DATA SEPARATOR

•

IMPLIED SEEKS

•

OVERLAPPED SEEKS

•

3 1/2 INCH FORM FACTOR

•

32-BIT ECC FOR WINCHESTER DATA
CORRECTION

•

256 OR 512 BYTES PER SECTOR

•

CONTROL FOR EITHER ONE OR TWO
WINCHESTER DRIVES, WITH UP TO SIXTEEN
READIWRITE HEADS EACH

•

DIAGNOSTIC READS AND WRITES FOR
CHECKING ERROR CORRECTION

•

SELECTABLE INTERLEAVE

•

BUILT-IN WRITE PRECOMPENSTION

•

SUPPORTS UP TO 16 HEADS

Communication to and from the Host are made via
a separate computer access port. This port conforms
to the Shugart Associates System Interface (SASI)
and consists of control signals and an 8-bit, bidirectional bus. All data to be written to or read from
the disk, status information, and command
parameters are transferred via this bus. An on-board
Sector Buffer allows bus transfers to be executed
independently of the actual data transfer of the drive.
ARCHITECTURE
The WD1002S-SHD Winchester Disk Controller is
based upon a Western Digital proprietary chip set
consisting of a: WD1010A-05, WD10C20, WD1015, and
the WD11COO-16, all specifically designed for Winchester disk control.

TABLE 1. WD10025-SHD INTERFACE CONNECTORS
REFERENCE DESIGNATION

INTERFACE FUNCTION

P1

POWER

J1

HOST (SASI BUS)

AMP88379-8
50-pin vertical header

J2-J3

DRIVE DATA

AMP88377-4
20-pin vertical header

J4

DRIVE CONTROL

Winchester Board Products

MATING CONNECTOR
AMP1-480424-0 (Housing)
AM P350078-4
4-pin connector

AMP88373-3
34-pin PC card edge connector

6-51

::r:

c

:ec
.....

WDllCOO-16
ECC
GENERATOR
& CHECKER

WDllCOO-16'
ADDRESS
COUNTER ,

o
o
N

WDIOIOA-OS

WDIOC20

WINCHESTER
DISK
CONTROLLER

DATA
SEPARATION
& WRITE
PRECOMP

DRIVERS AND
RECEIVERS

WINCHESTER
DISK DRIVES

en
en
I

:J:
C

SASI DATA
TRANSCEIVER

WDllCOO-16
DRIVERS AND
RECEIVER

SENSE
SIGNALS

WD11COO-16
SASI
BUS
CONTROLLER

WDIO'S·12

CONTROL
PROCESSOR

CLOCK
SIGNALS

CONTROL
SIGNALS

WDIOC20

CLOCK GENERATOR

WDllCOO-16
RESET CIRCUIT
AND WRITE GATE
D~GLlTCHER

FIGURE 1. WD1002S-SHD WINCHESTER DISK CONTROLLER BLOCK DIAGRAM

6-52

Winchester Board Products

SPECIFICATIONS
HOST INTERFACE

Type
Max Cable Length
(Total Daisy Chain)
Termination
Addressing

SASI
4.5 meters (15 ft.)
Socketed 220/330 ohm resistor pack
Jumper selectable 0 to 7

DRIVE INTERFACES

Encoding Method
Cylinders per Track
Bytes per Sector
Sectors per Track
Max Heads
Drive Selects
Stepping Rates/Algorythms
Data Transfer Rate
Write Precomp Time
Max Cable Length:
Control (Total Daisy-Chain)
Data (Radial-each)

MFM
Programmable
Jumper selectable (256 or 512)
32 (256 bytes/sector)
17 (512 bytes/sector)
16
2
Programmable
5 Mbits/sec
12 nsec
6 Meters (20 ft.)
6 Meters (20 ft.)

POWER

Voltage
Current
Ripple

+5 VDC ± 5% and +12 VDC ± 5%
800 rna typical (1.0 amps max)
0.1 to 25 mv (0.1 VDC max)

DATA SEPARATOR

Read Margin
Asymmetry

± 16 nsec
30 nsec measured over 5 MHZ
Raw MFM periods of 185, 215, nsec

PHYSICAL

Length
Width
Height (max. including board,
components & leads)
MTBF
MTTR

5.75 inches
4.00 inches
0.75 inches
10,000 POH
30 Minutes

ENVIRONMENTAL

Ambient Temperature
Relative Humidity
Altitude
Air Flow

Winchester Board Products

OOC (32~ to 55°C (131°F)
10% to 90% non-condensing
o to 10,000 Feet (3,048 meters)
150 linear feet per minute at 1/4 inch from compotent surfaces.

6-53

HOST INTERFACE

The WD1oo2S-SHD Winchester Disk Controller is
designed to interface with the Shugart Associates
System Interface (SASI) Bus. All interfacing is done
through the SASI connector (J1). The Host and seven

other SASI compatible devices can be daisy-chained
to this bus. The last device in the daisy-chain must
be terminated with a standard 220/330 ohm resistor
pack.

TABLE 2. HOST INTERFACE CONNECTOR (J1) PIN DESCRIPTIONS
SIG.
GND.

SIG.
PIN

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

MNEMONIC

DO
thru
D7

1/0

FUNCTION

DATA 0
thru
DATA 7

1/0

8-Bit, bi-directional bus used for the transfer
of commands, status and data

SIGNAL NAME

17 thru 34

Spare

35

36

BSY

BUSY

0

Falling edge acknowledges receipt of SEL
and address. Rising edge indicates transaction complete.

37

38

ACK

ACKNOWLEDGE

I

Handshake for byte transfers (both edges
used).

39

40

RST

RESET

I

Asserted for 100 nsec.

41

42

MSG

MESSAGE

0

Indicates type of bus transfer (see information
Transfer Phase).

43

44

SEL

SELECT

I

Asserted, gives control of bus to addressed
target.

45

46

CID

CONTROUDATA

0

Indicates type of bus transfer (see information
Transfer Phase).

47

48

REQ

REQUEST

0

Handshake for byte transfers (both edges
used).

49

50

ilo

INIOUT

110

L = Input to the Host
H = Output from Host
(See information Transfer Phase)

6-54

Winchester Board Products

DRIVE CONTROL INTERFACE
The control signals are common to both drives and
are daisy chained from a single 34-pin PC card edge
connector (J4). To terminate the control signals

properly, the last drive in the daisy-chain must not
be more than 20 feet from the controller, and have
a 220/330 ohm resistor pack installed.

:ec
...".

o
o

J\)

TABLE 3. DRIVE CONTROL CONNECTOR (J4) PIN DESCRIPTIONS

en
en
I

SIG.
GND.
1

SIG.
PIN
2

MNEMONIC
RWC
HS3
CHANGE
CART

SIGNAL NAME

:I:
C

I/O

FUNCTION

REDUCE
WRITE CURRENT

0

RWC is asserted when the Present Cylinder
Number Register is equal to or greater than
the content programmed in the Write Precomp
Register. It is used by the drive to reduce drift
caused by greater bit density on the inner
cylinders.

HEAD SELECT 3

0

HS3 is an optional Head Select line that
allows the selection of eight additional heads.

CHANGECART

0

CHANGECART when activated, will stop the
spindle motor.
(Removable Media Drives only)

3

4

HS2

HEAD SELECT 2

0

HS2 is one of three Head Select signals
encoded by the drive to select one of eight
RIW heads.

5

6

WG

WRITE GATE

0

WG is asserted when valid data is to be
written. It is used by the drive to enable the
write current to the head. WD1002S-SHD deasserts this signal when WF is asserted.
WD1002S-SHD prevents WG from being
asserted at power up, allowing the drive to
remain ON while cycling the Controller ON or
OFF.

7

8

SC

SEEK COMPLETE

I

SC, when asserted, infonns the WD10028-SHD
that the selected head has reached the desired
cylinder and has stabilized.

9

10

TKOOO

TRACK 000

I

11

12

WF

The drive asserts TKOOO when the heads are
positioned over the outermost cylinder
(Track 0).

WRITE FAULT

I

WF is asserted by the drive when a write error
occurs.

13

14

HSO

HEAD SELECT

0

HSO is one of three Head Select signals
encoded by the drive to select one of eight
RIW heads.

15

16

RECOVER

RECOVERY MODE

17

18

HS1
WRTSERVO

HEAD SELECT 1

0

HS1 is one of three Head Select signals
encoded by the drive to select on of eight RIW
heads.

WRITE SERVO

0

WRTSERVO is used to write servo infonnation
on a new cartridge.

Winchester Board Products

Not Used.

6-55

TABLE 3. DRIVE CONTROL CONNECTOR (J4) PIN DESCRIPTIONS (CONT'D.)
SIG.
GND.

SIG.
PIN

1/0

FUNCTION

19

20

INDEX

INDEX PULSE

I

This signal indicates start of a track. It is used
as a synchronization point during formatting
and as a time out mechanism for retries. This
signal pulses once for each revolution of the
disk.

21

22

DRDY

DRIVE READY

I

The drive asserts DRDY when selected and
the motor is up to speed.

23

24

STEP

STEP PULSE

0

STEP, with DIRIN, positions the heads to
the desired cylinder.

25

26

DSELO

DRIVE SELECT 0

27

28

DSEL1

DRIVE SELECT 1

0
0

Not Connected

MNEMONIC

SIGNAL NAME

29

30

NC

31

32

NC

Not Connected

33

34

DIRIN

DIRECTION IN

0

DSELO is used to select drive 1.
DSEL1 is used to select drive 2.

DIRIN determines the direction the R/W heads
take when stepped.
Asserted
IN.
De-asserted
OUT.

=

=

DRIVE DATA INTERFACE

The data is differential and must be connected to
each drive with its own cable (J2, J3). It should be
a flat ribbon cable, or twisted pair, less than 20 feet

long. The connector is a 20-pin vertical header on a
0.1" center.

TABLE 4. DRIVE DATA CONNECTORS (J2,J3) PINS
SIGNAL
GROUND

SIGNAL
PIN

-

1

2

-

1/0

3

0

5

I

4

6

-

7

8
9
10
11
12

I
I

13
14

0
0

17

I
I

15
16
18
19
20

6-56

SIGNAL NAME

Not Connected
Ground
Reinitialize
Ground
Write Protected
Ground
Not Connected
Ground
Cartridge Changed
Cartridge In
Ground
Ground
+ M FM Write Data
- MFM Write Data
Ground
Ground
+ M FM Read Data
- M FM Read Data
Ground
Ground

Winchester Board Products

POWER CONNECTOR

A 4·pin AMP connector (P1) provides power input to
the WD1002S· SHD Controller.

:E
c
.....
o
o

I\)

TABLE 5. POWER CONNECTOR (P1) PIN DESCRIPTIONS
SIGNAL
PIN

SIGNAL
GROUND

en
en
:::c
c

SIGNAL NAME

+ 12 Volts

1

(regulated)
Ground
Ground
+ 5 Volts (regulated)

2
3
4
DISK DRIVE CONFIGURATION
PARAMETERS

Table 6 lists the variable parameters for the major
drives supported by the WD1002S·SHD Winchester
Disk Controller.

TABLE 6. DISK DRIVE CONFIGURATION PARAMETER VARIATIOINS

MFGR

CMI
CMI
CMI
Oll
Oll
RMS
RMS
RMS
SEA
SEA
TAN
TAN
TAN
TI
RO
RO
RO
RO
RO
RO
RO
RO
MS
MS
DMA
SYQ

MODEL #

CYLINDERS

HEADS

REDUCED WRITE
CURRENT CYL.

WRITE PRECOMPENSATION
CYLINDER

256 (100)
256 (100)
256 (100)
180 (84)
180 (84)
153 (99)
153 (99)
153 (99)
153 (99)
306 (132)
153 (99)
153 (99)
230 (E6)
153 (99)
192 (CO)
192 (CO)
192 (CO)
192 (CO)
321 (141)
321 (141)
321 (141)
321 (141)
306 (132)
306 (132)
306 (132)
306 (132)

2
4
6
2
2
2
4
8
4
4
4
6
6
4
2
4
6
8
2
4
6
8
2
4
2
2

56 (100)
256 (100)
256 (100)
128 (80)
128 (80)
77 (48)
77 (48)
77 (48)
128 (80)
128 (80)
128 (80)
128 (80)
128 (80)
64 (40)
96 (60)
96 (60)
96 (60)
96 (60)
132 (84)
132 (84)
132 (84)
132 (84)
153 (99)
153 (99)
153 (99)
153 (99)

256 (100)
256 (100)
256 (100)
180 (84)
180 (84)
77 (48)
77 (48)
77 (48)
64 (40)
64 (40)
153 (99)
153 (99)
128 (80)
64 (40)
0(0)
0(0)
o (0)
0(0)
0(0)
0(0)
0(0)
0(0)
0(0)
0(0)
o (0)
0(0)

CM·5205
CM·5410
CM·5616
HD561
HD562
503
506
512
ST506
ST412
TM602S
TM603S
TM603SE
5 1/4+
101
102
103
104
201
202
203
204
1·006
1·012
360
312RO

Winchester Board Products

6-57

DRIVE MANUFACTURES ABBREVIATIONS:
Computer Memories Inc.
Oliveti
Rotating Memory Systems Inc.
Seagate Technology Inc.
Tandon Inc.
Texas Instruments
Rodime Ltd.
Miniscribe
DMA Systems
Syquest Corp.

CMI
OLi
RMS
SEA
TAN
TI
RO
MS
DMA
Sya

COMMANDS

a summary of the supported commands and their
parameters. It also includes information about data
transfers required during execution. All other SASI
command codes are reserved.

The WD1002S-SHD Winchester Disk Controller Board
supports 26 different SASI commands; 21 operation
commands and 5 diagnostic commands. Table 7 is

TABLE 7. WD10028-SHD SUPPORTED COMMAND SUMMARY

COMMAND
NAME
Test Drive
Ready
Restore to
Track
Req. Status
Frmt Drive
Chk Tr Frmt
Format Track
Frmt Bad Trk
Read
Stop Drive
Write
Seek
Set
Parameters
Last
Corrected
Burst
Length
Frmt Alt Trk
Wr Set Bfr
Rd Set Bfr
Write Servo

°

6-58

CLASS,
OPCODE

LUN

0,00

W

0,01
0,03
0,04
0,05
0,06
0,07
0,08
0,13
O,OA
O,OB

W
W
W
W
W
W
W
W
W
W

O,OC

O,OD
O,OE
O,OF
0,10
6,00

LOGICAL
SECTOR
ADDRESS

-

-

INTERLEAV
OR BLOCK
COUNT

-

-

CONTROL
BYTE
OPTIONS

--

L*
L*
L*
L*
L

- - I
I
I
I
B

- -

--

L
L*

B

-

W

- -

- -

--

W
W

- -

--

L*

I

- R,P,S,Z

--

- -

--

W

- -

--

- -

-

-

-

-- -

--

- R,P,S,Z
R,S
R,P,S,Z
R,P,S,Z
R,A,S
- R,S
R,S

- -

--

#SASI
DATA
BLOCK
TRNSFRS

°
°
°°
°°
°
°
1

D.B.
SIZE
- -

-

-

4

- To Host

--

--

-

-

DIRECTION

B

- -- SCTR

--

--

B

SCTR

To CTLR

--

--

1

8

To CTLR

1
1
1
1

1
3
SCTR
SCTR
- -

To Host
To CTLR
To CTLR
To Host
- -

°

- -

-- To Host

Winchester Board Products

TABLE 7. WD10025-SHD SUPPORTED COMMAND SUMMARY (CONT'D)

COMMAND
NAME

CLASS,
OPCODE

LUN

Reinitialize
Cartridge
RAM Diag
Drive Diag
CTLR Diag
RD Long

6,02
7,00
7,03
7,04
7,05

W

WR Long

7,06

W
L·
L
I
B
R
A
S
P
Z

LOGICAL
SECTOR
ADDRESS

-

INTERLEAV
OR BLOCK
COUNT

HSASI
DATA
BLOCK
TRNSFRS

CONTROL
BYTE
OPTIONS

-

--- -

W

L

B

R,S

0
0
0
0
B

W

L

B

R,S

B

W

-

-

-

-

-

-

-

-

-

-

R,S

-

-

D.B.
SIZE

DIRECTION

-

---- SECT
+4
SECT
+4

-

-

-

-

-

To Host
To CTLR

Winchester
Logical sector address used only to specify track
Logical sector address
Interleave
Block count
Retry enable/disable
Attempt immediate ECC enable/disable
Stepping algorithm
Used with Format commands for determining data field patterns function should be performed.
Used with Format commands for determining if a Write Servo function should be performed .

. COMMAND BLOCKS
A transaction is initiated by the Host to instruct the
WD10028- SHD Winchester Disk Controller to execute
a given command. During the Command Block

Transfer Phase, six bytes of information specifying
the command are transferred to the WD1oo2S-SHD
Winchester Disk Controller. This is the Command
Block and is illustrated in Figure 2.
BITS

BYTES

7

I

6

I

5

4

I

I

3

2

I

1

0

Command Class

Operation Code

1

Logical Unit Num

Logical Sector Address(High)

2

Logical Sector Address (Middle)

3

Logical Sector Address (Low)

4

Interleave or Block Count

5

Control Byte

I

0

FIGURE 2. COMMAND BLOCK FORMAT

Winchester Board Products

6-59

=E
c
.....
o
o
N

en

en

:I:
C

Byte 0 is transferred first and must be specified for
all commands. Depending upon the value of Byte 0,
each parameter in bytes 1 through 5 may require
specification.
LOGICAL UNIT NUMBER (LUN)
The LUN is contained in the three MSBits of Byte 1.
The allowed values are 0 and 1. The designators in
the command table are: Drive 0 (LUN = 0) or Drive
1 (LUN = 1).
LOGICAL SECTOR ADDRESS
The Logical Sector Address (High, Middle, and Low)
is a 21-bit field contained in Bytes 1, 2, and 3. It is
computed from the Cylinder Addres (C), Head Address
(H), and Sector Address (S), as well as the drive
parameters Heads per Cylinder (HC) and Sectors per
Track (S1):
L = ([(C x HC)

+

H) x S1)

+

S

C, H, and S can be derived from L, HC and ST
as follows:

This field specifies a sector (or beginning sector) for
the Read and Write drive commands. It specifies a
track for the Format and Seek commands (indicated
by L * in Table 7). When only a track specification is
required, the sector number implied by the Logical
Sector Address is ignored.
INTERLEAVE OR BLOCK COUNT
The Interleave or Block Count comprise Byte 4. The
Interleave ratio (I in Table 7) is specified in the five
Format commands. The maximum ratio is equal to
the Sector-per-Track minus 1.
The Block Count (B in Table 7) is specified in the
Read, Write, Read Long, and Write Long commands.
B specifies the number of Logical Sectors to be
transferred.
Both Interleave ratio and Block Count use all 8-bits
to specify their respective parameters.
CONTROL BYTES
Table 8 defines the Control Byte fields:

S = L Modulo ST
H = [(L-S) 1ST] Modulo HC
C = ([(L-S 1ST] -H) IHC

TABLE 8. CONTROL BYTE FIELDS
FIELD

BIT (S)

FUNCTION

STEP

0-3

Used in all commands that contain code corresponding to seek stepping
algorithm. See Fast Step Options.

Z

4

Write Servo Information

P

5

Format Data (P) is used in the Format commands. If P= 0, the WD1002SSHD fills the data field with 6C Hex. If P= 1, data field is filled with the pattern in the Sector Buffer.

A

6

Immediate ECC (A) is used in the Read command. If A = 0, no immediate
ECC is performed. If A = 1, immediate ECC is performed.

R

7

Retry (R) is used in all commands that read the ID field. If R = 0, (normal),
a maximum of 3 non-restore retries are performed, then Restore, Seek, and
1 more read is performed. If R = 1 Retry is disabled then no retries are
performed.

NOTE

FAST STEP OPTIONS

If one or more of the above fields are required for
a command, then all other fields in that Control Byte
must be set to O. If none of the above are required,
all bits in the Control Byte are interpreted as 'don't
care' bits (X).

The Fast Step Option field contains an unsigned
3-bit integer. These integers correspond to the Fast
Step Algorithms listed in Table 9.

6-60

Winchester Board Products

TABLE 9. FAST STEP OPTION ALGORITHMS
OPTION
0
1
2
3

4
5

6
7

8
9-F

ALGORITHM
Default: 3 msec. per step
Reserved
Reserved
Reserved
200 usec. per step. This is appropriate for buffered steps on drives made by
Computer Memories Inc. and Rotating Memories Inc.
70 usec. per step
30 usec. per step
15 usec. per step
12J.t's per step
Spare (3 msec. per step)

COMMAND STATUS BYTE

COMMAND COMPLETION BYTE

At the completion of any command execution, a Command Status Byte is sent by the WD10028-SHD to the
Host, whether the command was successful or
aborted_ The LUN returned is the contents of the LUN
field in the drive control block. For those commands
that do not use LUN as an input parameter, the LUN
returned in the Command Status Byte is meaningless.
Figure 3 illustrates the contents of the Command
Status Byte.

The Command Completion Byte is an all zero byte
sent by the WD10028-SHD Winchester Disk Controller
to the Host immediately following each Command
Status Byte. It indicates to the Host that the
WD1002S-SHD has freed the SASI Bus.

BITS

7

6
LUN

=

EF (Error Flag): 0
no error
1 = error
P (Write Protected) = 1
(Removable Media Only)
CC (Cartridge Changed) = 1
= Default
1 = CC

o

FIGURE 3. COMMAND STATUS BYTE

Winchester Board Products

6-61

COMMAND DESCRIPTIONS

:E

c-"
o
o

I\)

en

en

:::c
c

TEST DRIVE READY
(CLASS O,OP CODE 00)

This command selects a drive and verifies that it is
ready. The following is the Test Drive Ready command block format:

BITS
BYTES

7

6

0

Command Class 0

1

LUN

5

4

3

2

1

0

Operation Code 00

X

X

X

X

X

2

X

X

X

X

X

X

X

X

3

X

X

X

X

X

X

X

X

4

X

X

X

X

X

X

X

X

5

X

X

X

X

X

X

X

X

Possible Error Codes

No Error, Invalid Command, No Seek Complete, Drive Not Ready, or Write Fault.

Action

Select the drive and determine if it is ready. For a Winchester drive, read its
status register and test the ready bit and the busy bit. For Winchester drives
supporting buffered seeks, this command is useful for determining the first
drive to reach its target track.

6-62

Winchester Board Products

RESTORE TO TRACK 0
(CLASS 0, OPCODE 01)

=E
c
.....

This command positions the read/write heads to
Track O.

o
o

I\)

en

en

BITS
BYTES

7

6

0

Command Class 0

1

LUN

5

3

4

2

1

0

::I:
C

Operation Code 01

X

X

X

X

X

2

X

X

X

X

X

X

X

X

3

X

X

X

X

X

X

X

X

4

X

X

X

X

X

X

X

X

5

X

0

0

0

X

X

X

X

Possible Error Codes

No Error, Invalid Command,Track 0 Not Found, Drive Not Found, or write Fault.

Action

Position the read/write heads to track O.

REQUEST STATUS
(CLASS 0, OPCODE 03)

The Host must send this command immediately after
it detects an error. The command causes the
WD1002S-SHD Winchester Disk Controller to return
four bytes of drive and Controller status. When an
error occurs during a multiple sector data transfer
(read or write), the Request Status command returns
the Logical Sector Address of the failing sector in
bytes 1, 2, and 3. If the Request Status command is

issued after any of the format commands of the
Check Track Format command, then the Logical Sector Address points to one sector beyond the last track
formatted or checked if there was no error. If there
was an error, then the Logical Address returned points
to the track in error. The following is the Request
Status command block format:

BITS
BYTES

7

6

0

Command Class 0

1

LUN

5

4

3

2

1

0

Operation Code 03

X

X

X

X

X

2

X

X

X

X

X

X

X

X

3

X

X

X

X

X

X

X

X

4

X

X

X

X

X

X

X

X

5

X

X

X

X

X

X

X

X

Possible Error Codes

No Error or Invalid Command.

Action

Send the Host 4 bytes; the error byte and a 3-byte Logical Sector Address for
the specified drive.

Winchester Board Products

6-63

ERROR/STATUS RESPONSE TO HOST

=E

c
......
o
o

The following non·drive error codes are treated as
Drive 0 errors: RAM Failure (30); ROM Failure (31), ECC
Hardware Failure (33). If the RAM Diagnostic

command or Controller Diagnostic command detects
an error, then status for Drive 0 should be
requested.

I\)

en

en
J:

BITS

c

BYTES

7

6

0

LSA

0

5

I

I

3

I

2

Logical Sector Address Bits 8·15

3

Logical Sector Address Bits 0-07

1

J

0

D. MISCELLANEOUS ERROR CODES

A. DISK DRIVE ERROR CODES
00
No Error
03 = Write Fault
04 = Drive Not Ready
06 = Track 0 Not Found
07 = Write Protected
09 = Function Not Supported By Drive

=

B. CONTROLLER ERROR CODES
01, 02, 10/14
Not used because the
WD1010A-05 groups CRC
with other errors in ID field
as ID not found. During
implied seeks, these are
called SEEK errors,
Code 15.
11
Uncorrectable Data Error
12 = Address Mark Not Found
15
Seek Error
18
Error Burst Corrected
19
Bad Track
Format Error
1A
1C
Illegal (Direct) Access to an Alternate
Track
1D
Alternate Track Already Used
1E
Alternate Track Not Marked as Alternate
1F
Alternate Track Equals Bad Track

=

=
=
=
=
=
=
=
=
=

C. COMMAND ERROR CODES

=
=
=

1

Logical Sector Address Bits 16-20

2

ERROR CODES

OA
Controller Not Initialized
20
Invalid Command
21 = Invalid Sector Address
22
Illegal Parameter

6-64

4

Error Codes

LUN

1

J

=
=

30
RAM Failure
31 = ROM Failure
32
ECC Hardware Failure
If the most recent non·request·status command to the
specified drive required a Logical Sector Address,
then the LSA flag is 1; otherwise it is 0 and the Logical
Sector Address is meaningless.
ERROR CODE DESCRIPTIONS
No Error (00)

No error detected during the previous operation.
Write Fault (03)

Indicates that there is Write Current to the head when
WG is deasserted. This is a very serious problem and
should be remedied immediately.
Drive Not Ready (04)

The drive does not respond with a Drive Ready signal
after being selected by the WD1002S·SHD.
\

Track 0 Not Found (06)

This error is only returned by the Restore To Track
ocommand. It indicates that Track 0 status from the
drive was not asserted within the maximum number
of steps towards cylinder O.
Write Protected (07)
Function Not Supported By Drive (09)

Winchester Board Products

Controller Not Initialized (OA)

Alternate Track Not Marked as an Alternate (1 E)

This occurs when user fails to issue Initialize Format
command before issuing any command that
accesses the drive.

This error code indicates that access of a bad-trackwith-alternate caused access to an alternate track
that was not marked as an alternate.

Uncorrectable Data Error (11)

Alternate Track Equals Bad Track (1 F)

This error indicates that one or more error bursts
within the data field (Winchester) were beyond the
Error Correction capabilities of the WD1002S-SHD.
The sector data for this sector is not sent to the Host.

This error code is returned only by the Format Alternate Track command. It indicates that the same track
was specified as the bad track and the alternate track.
Invalid Command (20)

Address Mark Not Found (12)

This error indicates that the header for the Target Sector was found, but its Address Mark was not detected.

This error code indicates that the Command Code,
Interleave Factor, or Fast Step Option was invalid.
Invalid Sector Address (21)

Seek Error (15)

The WD1002S-SHD detects an incorrect cylinder or
track, or both.

This error code indicates that the WD1002S-SHD
detected a sector address beyond the maximum
range.

Error Burst Corrected (18)

Illegal Parameter (22)

Indicates that ECC was used to successfully correct
an error.The corrected sector data is sent to the Host.

When Controller detects an invalid parameter or
invalid combination of parameters.

Bad Track (19)

RAM Failure (30)

This error usually indicates access of a track that was
formatted as a bad track. However, there is a very
small chance that it indicates that a track formatted
as a bad track with alternate is so faulty that none
of the multiple, duplicate pointers to the alternate
track can be read.

This error code indicates one of the following
conditions:
1. The program memory RAM checksum does not
match the calculated checksum.
2. ,The RAM in the Control Processor failed.
3. The Control Processor CPU failed.

Format Error (1 A)

ROM Failure (31)

This error code is returned by the Check Track Format command. It indicates that the track is not formatted with the specified interleave factor, or at least
one sector header is unreadable. This error code is
returned by the Drive Diagnostic command to indicate
that bad-track-with-alternate does not contain valid
pointer to the alternate track.

This error code indicates that a ROM checksum error
occurred during internal diagnostics.
ECC Hardware Failure (32)

This error code indicates that the ECC Support Device
failed during internal diagnostics.

Illegal (Direct) Access to an Alternate Track (1 C)
Alternate Track Already Used (1 D)

This error code is only returned by the Format Alternate Track command. It indicates that the specified
alternate track is already an alternate, or bad track.

Winchester Board Products

6-65

FORMAT DRIVE
(CLASS 0, OPCODE 04)

This command formats all sectors with 10 and data
fields according to the selected interleave factor. This
command also writes 6C Hex into the data fields. The
starting address is passed into the Control Byte which

is read by the WD1002S-SHD Winchester Disk Controller. The Controller then formats from this address
to the end of the disk. The following is the Format
Drive command block format:

BITS
BYTES

7

I

6

I

5

4

I

I

3

2

I

1

I

0

Command Class 0

Operation Code 04

1

LUN

Logical Sector Address Bits 16-20

2

Logical Sector Address Bits 8-15

3

Logical Sector Address Bits 0-07

4

Interleave Factor

5

R Retry Disable:

R

o=
1

P Format Data:
Z Write Servo:

0

I

p

z

I

Fast Step Option

No Disable

= Disable

o=
1

I

0

6C Hex

= Contents of Sector Buffer

o=

Do Not Write Servo
1 = Write Servo Information

NOTE

This is used only for removable media drives that
implement the Write Servo function.
Possible Error Codes

No Error, Invalid Command, Invalid Sector Address,
Drive Not Ready, Seek Error, or Write Fault.
Action
Format from the specified track to the end of the disk.
The previous contents of the formatted tracks are
ignored.

6-66

Winchester Board Products

CHECK TRACK FORMAT
(CLASS O,OPCODE 05)
This command checks the format on the specified
track for correct ID and interleave. The command does
not read the data field. The following is the Check
Track Format command block format:

BITS
BYTES

7

I

6

I

5

4

J

J

3

2

I

1

I

0

Command Class 0

Operation Code 05

1

LUN

Logical Sector Address Bits 16·20

2

Logical Sector Address Bits 8-15

3

Logical Sector Address Bits 0-07

4

Interleave Factor
R

5
R Retry Disable:

o=
1

I

0

I

0

0

I

0

Fast Step Option

No Disable

= Disable

Possible Error Codes
No Error, Invalid Command, Invalid Sector Address,
Seek Error,Format Error, Drive Not Ready, or Write
Fault.
Action
Verify that the specified track is formatted with the
specified interleave factor. Do not read the sector data
fields.

Winchester Board Products

6-67

:ec
....o
o

N

FORMAT TRACK
(CLASS 0, OPCODE 06)

This comand formats a specified track and can be
used to clear bad·sector flags in all sectors on the
specified track that was previously formatted with the

Format Bad Track command. The command writes
6C Hex into all data fields specified. The following
is the Format Track command block format:

cp
en

BITS

:x:
c

BYTES

7

I

6

I

5

4

I

I

3

2

I

1

I

0

Command Class 0

Operation Code 06

1

LUN

Logical Sector Address Bits 16·20

2

Logical Sector Address Bits 8·15

3

Logical Sector Address Bits 0-07

4

Interleave Factor

5
R Retry Disable:

R

o=
1

P Format Data:
Z Write Servo:

0

I

p

z

I

Fast Step Option

No Disable

= Disable

o=
1

J

0

6C Hex

= Contents of Sector Buffer

o=

Do not Write Servo
1 = Write Servo Information

Possible Error Codes

No Error, Invalid Command, Invalid Sector Address,
Drive Not Ready, Seek Error, or Write Fault.
Action

Format the specified track, ignoring the previous
contents.

6-68

Winchester Board Products

FORMAT BAD TRACK
(CLASS 0, OPCODE 07)
This command formats the specified track and sets
the bad-sector flag in the ID fields. It does not write

to the data fields. The following illustrates the Bad
Track command block format.

:e

c
.....

o
o

I\)

~

BITS
BYTES

7

I

6

I

5

4

I

I

3

2

I

1

I

0

Command Class 0

Operation Code 07

1

LUN

Logical Sector Address Bits 16-20

2

Logical Sector Address Bits 8-15

3

Logical Sector Address Bits 0-07

4

Interleave Factor
R

5

R Retry Disable:

I

0

I

0

z

I

::I:
C

0

Fast Step Option

o = No Disable
1 = Disable

Z Write Servo:

o=
1

Do not Write Servo

= Write Servo Information

Possible Error Codes

No Error, Invalid Command, Invalid Sector Address,
Drive Not Ready, or Write Fault.
Action
Format the specified track with a bad block mark in
each sector header, ignoring the previous contents.
The contents of a bad track are not accessible.

Winchester Board Products

6-69

:ec
..L

o
o

READ
(CLASS 0, OPCODE 08)
This command reads the specified number of sectors,
starting with the initial Sector Address contained

in the Control Byte. The following is the Read com·
mand block format:

N

~

BITS

:I:
C

BYTES

I

7

6

I

5

4

I

I

3

2

I

1

I

0

Command Class 0

Operation Code 08

1

LUN

Logical Sector Address Bits 16·20

2

Logical Sector Address Bits 8·15

3

Logical Sector Address Bits 0-07

4

Interleave Factor

5

R

R Retry Disable:

o=

A Attempt ECC

o = No

I

A

I

0

0

I

0

Fast Step Option

No Disable
1 = Disable
1

Immediate Correction

= Immediate ECC

Possible Error Codes

No Error, Invalid Command, Invalid Sector Address,
Drive Not Ready, Seek Error, Bad Track, Illegal (direct)
Access To Alternate Track, Alternate Track Not
Marked As Alternate, Address Mark Not Found, Error
Burst Corrected, Uncorrectable Data Error, or Write
Fault.
Action
Read the specified number of consecutive sectors
beginning with the specified Sector Address con·
tained in the Control Byte.

6-70

Winchester Board Products

WRITE
(CLASS 0, OPCODE OA)
This command writes the specified number of sectors, beginning with the initial sector address

contained in the Control Byte. The following is the
Write command block format:

BITS
BYTES

7

I

6

I

5

4

I

I

3

2

I

1

I

0

Command Class 0

Operation Code OA

1

LUN

Logical Sector Address Bits 16-20

2

Logical Sector Address Bits 8-15

3

Logical Sector Address Bits 0-07

4

Interleave Factor

5
R Retry Disable:

R

I

0

I

0

0

I

0

Fast Step Option

=

0
No Disable
1 = Disable

Possible Error Codes

Action

No Error, Invalid Command, Invalid Sector Address,
Drive Not Ready, Seek Error, Bad Track, Illegal (direct)
Access to Alternate Track, Alternate Track Not
Marked As Alternate, Address Mark Not Found, or
Write Fault.

Write the specified number of sectors beginning with
the specified Sector Address contained in the Control Byte.

Winchester Board Products

6-71

SEEK
(CLASS 0, OPCODE OB)
This command initiates a seek to the track specified
in the Control Byte. The drive must be formatted.

The following is the Seek command block format:

BITS
BYTES

7

6

5

4

3

I

2

I

1

I

0

Command Class 0

Operation Code OB

1

LUN

Logical Sector Address Bits 16·20

2

Logical Sector Address Bits 8·15

3

Logical Sector Address Bits 0-07

4

X

X

X

X

5

R

0

0

0

R Retry Disable:

o=
1

X

I

X

I

X

I

0

X

Fast Step Option

No Disable

= Disable

Possible Error Codes

No Error, Invalid Command, Invalid Sector Address,
Drive Not Ready, or Write Fault.
Action
Move the read/write head to the specified cylinder.
Do not read any sector header to verify start or end
position.

6-72

Winchester Board Products

SET PARAMETERS
(CLASS 0, OPCODE OC)
This command enables the Host to configure the
WD1002S-SHD Winchester Disk Controller to work
with drives that have different capacities and
characteristics. However, both Drive 0 and Drive 1

must be of the same manufacturer and model
number. The following is the Set Parameters command block format:

=E

....oc
o

N

cp
en

::I:

C

BITS
BYTES

7

6

0

Command Class 0

1

LUN

5

4

3

2

1

0

Operation Code OC
X

X

X

X

X

2

X

X

X

X

X

X

X

X

3

X

X

X

X

X

X

X

X

4

X

X

X

X

X

X

X

X

5

X

X

X

X

X

X

X

X

Possible Error Codes
If parameters are out of range, an Invalid Command
error will be set.
Action
Set the following parameters for both Winchester
drives (LUN 0 and 1): Number of cylinders, Number
of heads; Starting Reduced Write Current cylinder,
Starting Write Precompensation cylinder, and the
maximum length of an error burst to be corrected.
These parameters are sent by the Host to the
WD1002S-SHD Winchester Disk Controller in a
parameter block with the following format:

Winchester Board Products

6-73

:ec
..a.

o
o
I\)

PARAMETER BLOCK
After the Host sends the Set Parameters command
block to the WD1002S-SHD Winchester Disk Controller, it then sends an 8-byte block of data that contains the required drive parameters. Some parameters

occupy two bytes; all two-byte parameters are
transferred with the Most Significant Byte first. The
following is the 8-byte Parameter block format:

Z!

BITS

:::t
C

BYTES

7

I

6

I

I

5

4

I

3

J

2

0

MSByte of Number of Cylinders

1

LSByte of Number of Cylinders

2

0

I

0

I

I

0

0

I

J

MSByte of Starting RWC Cylinder

4

LSByte of Starting RWC Cylinder

5

MSByte of Starting Write Precomp Cylinder

6

LSByte of Starting Write Precomp Cylinder
0

RD (Removable Media Drive)

I

0

I

I

0

o

= Fixed
1 = Removable

The following parameter defaults are set by Power-UP
and Reset:
Number of cylinders
Number of heads
Starting Reduced Write
Current Cylinder
Starting Write Precompensation
Cylinder
Maximum length of an error burst to
be corrected

=
=

153
4

=

128

= 64
=

11

RD

I

J

0

Number of Heads

3

7

1

Max ERR Burst Corrected

The acceptable ranges of the following parameters are
as follows:
Number of cylinders
Number of heads
Starting Reduced Write
Current Cylinder
Starting Write Precompensation
Cylinder
Maximum length of an error
burst to be corrected

=

1 - 1024

= 1 - 16

= 1 - 1023
=

0 - 1023

= 1 - 11

If one of the parameters is out of range, then all
parameters up to, but not including the parameter in
error, are set for Drive 0 and no parameteres are set
for Drive 1. The error code for this error is Invalid
Command.
Starting Reduced Write Current Cylinder
The specified starting Reduced Write Current cylinder
number is reduced to the nearest integer multiple of
four (Le., 0, 4, 8, 12,... 1020).
Maximum Length of Error Burst To Be Corrected
For practically all applications,the maximum length
of the error burst to be corrected should be five. Correcting longer burst greatly increases the chance of
miscorrecting.

6-74

Winchester Board Products

LAST CORRECTED BURST LENGTH
(CLASS 0, OPCODE 00)

This byte is valid only after a correctable ECC error
(18).

This command transfers one byte to the Host containing the values of the ECC burst length detected
by the WD1002S-SHD during the last Read command.

:E

c
.....

o
o

N

~

BITS

::I:
BYTES

7

5

6

0

Command Class 0

1

LUN

2

3

4

1

0

C

Operation Code OD
X

X

X

X

X

2

X

X

X

X

X

X

X

X

3

X

X

X

X

X

X

X

X

4

X

X

X

X

X

X

X

X

5

X

X

X

X

X

X

X

X

Possible Error Codes

No Error.
Action

Send the Host one byte of data containing the length
of the most recently corrected error burst. If no error
burst has been corrected since the last Power-UP or
Reset, then a byte of zeros is sent to the Host.

BITS
BYTES

7

0

I

6

I

5

I

4

I

3

I

2

I

1

I

0

Number of bits in Last Corrected Error Burst
FIGURE 4. ERROR BURST LENGTH BLOCK

Winchester Board Products

6-75

:e

FORMAT ALTERNATE TRACK (CLASS 0, OPCODE OE)

c
.....

BITS

o
o

BYTES

N

~
:J:
C

7

J

6

1

5

I

4

I

3

2

I

1

I

0

Command Class 0

Operation Code OE

1

LUN

Logical Sector Address Bits 16-20

2

Logical Sector Address Bits 8-15

3

Logical Sector Address Bits 0-07

4

Interleave Factor

5

R

R Retry Disable:

o = No

P Format Data:

o = 6C

Z Write Servo:

o=

I

0

I

p

z

I

0

Fast Step Option

Disable
1 = Disable
Hex
1 = Contents of Sector Buffer

1

Do not Write Servo

= Write Servo Information

Possible Error Codes

Action

No Error, Invalid Command, Invalid Sector Address,
Drive Not Ready, Seek Error, Alternate Track Already
Used, Alternate Track Equals Bad Track, or Write
Fault.

Format the specified track as a bad-track-withalternate. Format the specified alternate track with
the specified interleave factor. The Bad Block Mark
is written in each sector header with the alternate
address block written into each sector data field. This
is done to all sectors of the track. It is not known to
the user which sector of the track might be bad. The
alternate track is specified by the Host by sending
an alternate sector address block to the WD1002SSHD after the command block. The alternate track
is formatted after the bad track-with-alternate is formatted. Once the alternate is formatted, the bad track
to alternate seeking is transparent to the user.

BITS
BYTES

7

6

5

0

0

0

0

4

I

3

I

2

1

1

l

0

Logical Sector Address Bits 16-20

1

Logical Sector Address Bits 8-15

2

Logical Sector Address Bits 0-07
FIGURE 5. ALTERNATE SECTOR ADDRESS BLOCK

6-76

Winchester Board Products

WRITE SECTOR BUFFER (CLASS 0, OPCODE OF)

==
C
.....

BITS
BYTES

7

6

0

Command Class 0

1

LUN

5

3

4

2

1

°

Operation Code OF

X

X

X

X

X

2

X

X

X

X

X

X

X

X

3

X

X

X

X

X

X

X

X

4

X

X

X

X

X

X

X

X

5

X

X

X

X

X

X

X

X

3

2

1

0

No Errors.
Action

Write data from the Host to the WD1002S-SHD Winchester Disk Controller Sector Buffer. The Host must
send as many bytes as there are in a sector on Drive
O. These data are not written to any drive. This command is used to initialize the format data optionally
used by the Format commands.
READ SECTOR BUFFER (CLASS 0, OPCODE 10)
BITS

7

6

0

Command Class 0

1

LUN

5

4

Operation Code 10

X

X

X

X

X

2

X

X

X

X

X

X

X

X

3

X

X

X

X

X

X

X

X

4

X

X

X

X

X

X

X

X

5

X

X

X

X

X

X

X

X

Possible Error Codes

No Error.
Action

Send the Host the present contents of the WD1002SSHD Winchester Disk Controller Sector Buffer. The
Host must accept as many bytes as there are in a
sector on Drive O.

Winchester Board Products

N

cp
en

:I:
C

Possible Error Codes

BYTES

o
o

6-77

=E
c

~

o
o

N

cp
en

STOP DRIVE
(CLASS 0, OPCODE 13)
This command causes a removable cartridge disk
drive to spin down and stop so the user can change
the cartridge. After the cartridge is changed, the drive
must be started by external means. Software can

check for completion of the cartridge change by using
the Test Drive Ready command. The format for the
Stop Drive command is as follows:

:I:
C

BITS
BYTES

7

6

0

Command Class 0

1

LUN

5

3

4

2

1

0

Operation Code 13

X

X

X

X

X

2

X

X

X

X

X

X

X

X

3

X

X

X

X

X

X

X

X

4

X

X

X

X

X

X

X

X

5

X

X

X

X

X

X

X

X

Possible Error Codes
Function Not Supported By Drive.

Action
Spins down drive to allow user to change removable
cartridge.

WRITE SERVO
(CLASS 6, OPCODE 00)
The Write Servo command completely erases the
existing servo information and all other data on the
disk, then rewrites the servo information. This provides optimum alignment between cartridge and drive

(and may enhance seek performance) as each cartridge can be servo written by the drive in which it
is to be used.

BITS
BYTES

6

7

0

Command Class 6

1

LUN

5

4

3

2

1

0

Operation Code 00

X

X

X

X

X

2

X

X

X

X

X

X

X

X

3

X

X

X

X

X

X

X

X

4

X

X

X

X

X

X

X

X

5

X

X

X

X

X

X

X

X

Possible Error Codes
Function Not Supported By Drive.

6-78

Winchester Board Products

REINITIALIZE CARTRIDGE
(CLASS 6, OPCODE 02)
This command provides a servo reinitialization cycle
wherin track location and disk runout information are
reprogrammed in the drive microprocessor. This

function may be employed by the Host system to
improve Seek error rate, and is automatically provided
on a power·UP sequence or after a cartridge change.
BITS

BYTES

7

6

0

Command Class 6

1

LUN

5

4

3

2

1

0

Operation Code 02

X

X

X

X

X

2

X

X

X

X

X

X

X

X

3

X

X

X

X

X

X

X

X

4

X

X

X

X

X

X

X

X

5

X

X

X

X

X

X

X

X

Possible Error Codes
Function Not Supported By Drive.
RAM DIAGNOSTIC
(CLASS 7, OPCODE 00)
This command performs a data pattern test on the
Sector Buffer. The Host does not preserve the

contents of the Sector Buffer.The following is the
RAM Diagnostic command block format:
BITS

BYTES

7

6

0

Command Class 7

1

LUN

5

4

3

2

1

0

Operation Code 00

X

X

X

X

X

2

X

X

X

X

X

X

X

X

3

X

X

X

X

X

X

X

X

4

X

X

X

X

X

X

X

X

5

X

X

X

X

X

X

X

X

Possible Error Codes

Action

No Error or RAM failure.

Test the Sector Buffer by writing and reading various
patterns into it.

Winchester Board Products

6-79

=e

....c
o
o

N

~

DRIVE DIAGNOSTIC
(CLASS 7, OPCODE 03)

This command tests both the drive and the drive-toController interface. The WD1002S-SHD Winchester
Disk Controller sends Restore to Track 0 and Seek
commands to the selected drive and verifies Sector
o of all tracks on the disk. The WD1002S-SHD

Winchester Disk Controller does not perform any write
operations during this command; the disk is
understood to be previoulsy formatted. The following
is the Drive Diagnostic command block format:

:t:
C

BITS
BYTES

7

6

0

Command Class 7

1

LUN

5

3

4

2

1

0

Operation Code 03

X

X

X

X

X

2

X

X

X

X

X

X

X

X

3

X

X

X

X

X

X

X

X

4

X

X

X

X

X

X

X

X

5

R

0

0

0

Fast Step Option

Possible Error Codes

No Error, Invalid Command, Drive Not Ready, Seek
Error, Format Error, or Write Fault.
Action

Recalibrate the target drive, then scan ID on each
track. This command does not write to the disk, nor

does it send any sector data to the Host. The effect
of the Drive Diagnostic command is to verify that at
least one sector header can be read on each track.
It does not report an error when it encounters a track
that has been formatted as a 'Bad Track', 'Bad-TrackWith-Alternate', or 'Alternate Track'.

CONTROLLER DIAGNOSTIC
(CLASS 7, OPCODE 04)

This command initiates the WD1002S-SHD self-test
diagnostic routine. The WD1002S-SHD tests its Control Processor, Sector Buffer, ECC circuitry, Winchester Controller/Formatter, and the checksum of the

Program Memory. The WD1002S-SHD does not
access the drive during this command. The following is the Controller Diagnostic command block
format.
BITS

BYTES

7

6

0

Command Class 7

1

LUN

5

4

3

2

1

0

Operation Code 04

X

X

X

X

X

2

X

X

X

X

X

X

X

X

3

X

X

X

X

X

X

X

X

4

X

X

X

X

X

X

X

X

5

X

X

X

X

X

X

X

X

Possible Error Codes

Action

No Error, ROM Failure, RAM Failure, or ECC Hardware Failure.

Calculate a checksum for the program ROM, test the
Control Processor, test the Sector Buffer, and test the
ECC hardware. This command does not access any
disk drive.

6-80

Winchester Board Products

READ LONG
(CLASS 7, OPCODE 05)
This command transfers the target sector and four
bytes of data ECC to the Host. If an ECC error occurs
during Read, the WD1002S- SHD does not attempt to
correct the data field. The command is useful in

recovering data from a sector that contains an uncorrectable ECC error. It is also useful during diagnostic
operations.

7

I

6

I

5

~

I

4

3

I

2

I

1

I

0

Command Class 7

Operation Code 05

1

LUN

Logical Sector Address Bits 16-20

2

Logical Sector Address Bits 8-15

3

Logical Sector Address Bits 0-07

4

Sector Count

5
R Retry Disable:

R

I

0

I

0

I

0

0

Fast Step Option

0 = No Disable
1 = Disable

Possible Error Codes

Action

No Error, Invalid Command, Invalid Sector Address,
Drive Not Ready, Seek Error, Bad Track, Illegal (direct)
Access To An Alternate Track, Alternate Track Not
Marked As Alternate, Address Mark Not Found, or
Write Fault.

Read the specified number of consecutive sectors
and their ECC bytes beginning with the specified sector contained in the Control Byte. There are four ECC
bytes per sector. This command is only useful for
diagnostic purposes.

WRITE LONG
(CLASS 7, OPCODE 06)
This command transfers a sector of data and four
appended ECC bytes to the disk drive. During this
write operation, the Host supplies the four ECC bytes
instead of the usual hardware generated ECC bytes.

This command is useful only for diagnostic routines.
The following is the Write Long command block
format:

BITS
BYTES

7

I

6

I

5

4

I

3

I

2

1

1

1

0

Command Class 7

Operation Code 06

1

LUN

Logical Sector Address Bits 16-20

2

Logical Sector Address Bits 8-15

3

Logical Sector Address Bits 0-07

4

Sector Count

5
R Retry Disable:

R

I

0

I

0

0

I

0

Fast Step Option

o=

No Disable
1 = Disable

Winchester Board Products

N

::I:
C

BITS
BYTES

=E

c
......
o
o

6-81

=e
c

-"

o
o

N

~

Possible Error Codes

Action

No Error, Invalid Command, Invalid Sector Address,
Drive Not Ready, Seek Error, Bad Track Illegal (direct)
Access To Alternate Track, Alternate Track Not
Marked As Alternate, Address Mark Not Found, or
Write Fault.

Write the specified number of consecutive sectors
beginning with the specified sector. Following each
sector, the Host sends four ECC bytes to the
WD1002S-SHD Winchester Disk Controller to be written to the disk as the ECC bytes for the sector. This
command is useful for diagnostic purposes. It allows
the generation of a sector containing a correctable
ECC error.

:t
C

TIMING

Figure 6 illustrates a typical Host-Controller bus
transfer, complete with Controller selection.
00 TERMINATES COMMAND
#2

#3

#4

#5

7

#6

DATA

IF COMMAND HAS A DATA TRANSFER IT HAPPENS HERE
SEL

~--------------~I
REO

ACK

r

1/0

CID

\ "'---------/

MOO
FIGURE 6. TYPICAL HOST-CONTROLLER BUS TRANSFER TIMING

6-82

Winchester Board Products

HOST/CONTROLLER SELECTION TIMING

Prior to either command or data transfer, the Host
must perform a handshake operation in selecting the
Controller. The Host first asserts SEL and places
the Controller address bit on the bus (the address bit
is preset to DBO at the factory but can be any bit from
DBO to· DB? in a multiple-Controller environment).
After the controller recognizes its address bit and
SEL being asserted, it then asserts BUSY. During
this selection phase, the Host takes full control of
the data bus by asserting 0 (I/O). Once the Controller has asserted BUSY, the selection process is
complete. SEL must be de-asserted by the Host at
or before the first Command byte to the Controller.
Figure 7 illustrates the Controller Select Timing.
Figure 8 illustrates the Controller Select Timing Flow.

=E

c
....
o
o

N

cp
en

ISSUE

:I:
C

(OPTIONAL)
RESET

SEND SELECT BIT

SEND CONTROLLER ADDRESS BIT

NOTE

No restriction on sequence of SEL and DADR fal·
ling edges. Both must be low to ensure controller
selection.

CONTROLLER SHOULD GO BUSY WITHIN
520 nsec.

IL..-_ _~I

I

I
I

DADR

----,I!

BUsY

- - - - - : . . . 1_ _ _-,

260 N;

I

I
I

I... coS20NS .1L..-_ _ _ _ _ __

NOTE:

No restriction on sequence of SEL and DADR failing edges. Both must be low to ensure controller
selection.

FIGURE 8.
CONTROLLER SELECT FLOW DIAGRAM

FIGURE 7. CONTROLLER SELECT TIMING

Winchester Board Products

6-83

=e
c

""'o"
o

N

~
:J:
C

COMMAND MODE

After Controller selection, the Host can transmit its
first command. The Controller receives a command
form the Host using a sequence of handshake
recognition signals. The Controller asserts C (CID)
to notify the Host that it is ready to receive a command and assets 0 (1/0) to indicate that the direction is from the Host to the Controller. At this time,
MSG is in the de-asserted state.
The Controller asserts REO within 10 usec. After
asserting 0 (1/0), C (CIO), and MSG is in the deasserted state. The Host then answers by asserting
ACK when it is ready to send a command byte to
the Controller. The command byte must be stable on
the bus within 250 nsec. of ACK being asserted
and remain stable until the Controller de-asserts
REO. After the Controller de-asserts REO, the Host
de-asserts ACK completing the handshake sequence
for the first command byte. The complete handshake
sequence must be repeated for each successive command byte from the Host. Table 9 lists the relationships of 1/0, CIO, and MSG.

~I·~----~Y----~·~I

REO

-----~I

________~

I

I

I

tRAL

~

I

I

tRAH

I...... tARH ~ l.- tARL
I ~

ACK ----~~

I

I

I

~
oo:D7

I

IADV

~..:

I......

IRDH

Wl/$#!I//J/!I$'--_-JX\.-__
FIGURE 9.
HOST-TO-CONTROLLER
DATA TRANSFER TIMING

TABLE 10.
HOST-TO-CONTROLLER
TIMING PARAMETERS

TABLE 9. HOST BUS SIGNAL STATUS

..

MIN·

The Controller receives a
command from the Host.

tRALt

0

1

The Controller receives
data from the Host.

tRAHtt

1

1

The Controller sends data
to the Host.

0

0

1

The Controller sends an
error status byte to the
Host.

0

0

0

The Controller informs the
Host that it has completed
the command in process.

PARAMETER
I/O

CID

MSG

BUS STATUS

1

0

1

1

1

0

DATA TRANSFER

tCY

tARH
tARL

600

840

0
200

448
375

tADV
tRDH

MAX·

1152

0

LEGEND:

nsec
•• If conditions in t and tt are met, then tCytyp =
1200 nsec and tCY max = 1248 nssec.
t If tRAL < 89 nsec, then no wait states are inserted.
tt If tRAH < 97 nsec, then no wait states are inserted.

Figures 9 and 10 illustrate the required timing for
Host-to-Controller and Controller-to-Host data
transfers respectively. These diagrams include the
required handshake signals. Tables 10 and 11 provide
the timing parameters for these diagrams.

6-84

Winchester Board Products

STATUS BYTES

_

I_

ICY

-,

r--------.I'-___

REO - - - ,

IRAL

IRAH

I ~"·IIARH

ACK

------~II~--------------ISUR

~

r-~

IRDH

After every command, the Controller sends two status
bytes to the Host. The first byte of information con·
tains the error status code for that command and the
second byte contains all zeros, indicating that the
command has been completed. Figure 11 illustrates
the timing sequence for Command Termination.
Figure 12 illustrates the timing flow for sending and
terminating a command, and Figure 13 illustrates
Status Request Timing Flow.

r

DO-D7~~____________~~_____

FIGURE 10.
CONTROLLER-TO-HOST
DATA TRANSFER TIMING

TABLE 11.
CONTROLLER-TO-HOST
TIMING PARAMETERS
PARAMETER

tCY **
tRALt
tARH
tRAHtt
tRAL
tSUR
tRDH

MIN*

1152
0
200
0
200
125
152

MAX*

448
848

LEGEND:

nsec
** If conditions in t and tt are met, then tCytyp

=

=

120 nsec and tCY max
1248 nsec.
t If tRAL < 497 nsec, then no wait states are
inserted.
tt If tRAH < 200 nsec, then no wait states are
inserted.

Winchester Board Products

6-85

=E
C
.....

BUSY

0
0

N

~

::z:

iio

C

~\\\\\\\\\\\
I"
·1

TYP

WD1002-SHD 1.65 MS

I

REO

ACK

U

1,.

440
I'S.

r
p

IU
I
I
I

U:

---.1 j.-

U
26OI'S

WD1002S-SHD

MSG

_--JX

LASTDATA BYTE

X

STATUS BYTE

X~ir~ XlIIIZZIII!

FIGURE 11. COMMAND TERMINATION TIMING

6-86

Winchester Board Products

:E
c
.....

SEND REQUEST SENSE STATUS COMMAND

SEND (NON-DATA TRANSFER) COMMAND

o
o
N

SELECT CONTROLLER

SELECT CONTROLLER

C(>

en

::I:

SET 6-BYTE COMMAND COUNTER

C

NO

READ IN 4 SENSE BYTES
REQUEST, CID = C, 1/0 =0

(WAIT FOR REQUEST EACH TIME)

I

READ COMMAND STATUS AND MESSAGE BYTES

SEND COMMAND BYTE TO CONTROLLER

DECREMENT BYTE COUNTER

FIGURE 13.
REQUEST STATUS COMMAND
TIMING FLOW DIAGRAM
MISCELLANEOUS TIMING
The following is a list of specific timing parameters
that must be met for proper operation of the
WD1002S-SHD:

READ IN STATUS BYTE

REQUEST, CID - C, 1/0MESSAGE
MESSAGE
READ A BYTE
IF SIB = 0
COMMAND COMPLETED

FIGURE 12.
COMMAND SEQUENCE
TIMING FLOW DIAGRAM

Winchester Board Products

A. CONTROLLER RESET - Power-On-Reset (POR) is
less than 120 msec. and Reset (RSn is less
than 120 usec. During either of these periods, the
Host is inhibited from selecting the Controller. If
selection is attempted, the Controller does not
assert BUSY.
B. SELECT TO CID - After RST or POR, the Controller runs its internal diagnostic routines until it
is selected by the Host, at which point the Con·
troller exits the diagnostic routine being run. While
in the diagnostic loop, the controller can take as
long as 340 msec. After it asserts BUSY, before
asserting C (CID). However, once the Controller
has left the diagnostic loop, no more than 80 usec.
is required for the Controller to assert C (CI D)
after BUSY is asserted.
C. C/D TO FIRST REQ TIMING PULSE - When the
Controller first asserts C (C/D) until the first
REQ pulse is asserted is typically 120 usec.
D. WAIT STATE - One wait state equals 200 nsec.
NOTE
All SASI protocol must be adhered to (Le., a
RE/ACK handshake must precede every byte
transferred).

6-87

6-88

Winchester Board Products

WESTERN
COR

P

0

DIGITAL

R

A

T

o

N

:E

c
.....

WD1002C-WX2
Winchester Controller Board

o
o

N

o

:e><

FEATURES
•

IBM XT WINCHESTER CONTROLLER
EMULATION, IBM PC HOST INTERFACE.

•

EITHER 50 PIN EXTERNAL CONNECTOR
OR 62 PIN EXTERNAL CONNECTOR.

•

SUPPORTS MULTIPLE STEPPING
INCLUDING 18 USEe.

•

•

AUTOMATIC FORMATIING.

•

WD10C20-05 SELF·ADJUSTING LSI DATA
SEPARATOR.

•

SECTOR INTERLEAVE CAPABILITY.

•

OVERLAPPED SEEK CAPABILITY ON
BUFFERED-STEP DRIVES.

DYNAMICALLY CONFIGURABLE BIOS ROM

•

•

SUPPORTS TWO ST506 TYPE DRIVES WITH UP
TO 1024 CYLINDERS AND 16 RIW HEADS.

SUPPORTS IMPLIED SEEKS ON ALL
COMMANDS.

•

DMA TRANSFER CAPABILITY.

•

ERROR DETECTION AND CORRECTION ON
DATA FIELD USING 32·BIT ECC POLYNOMIAL

RATES,

N

DESCRIPTION
The WD1002C-WX2 is an IBM XT compatible Winchester controller board based on the design of the
WD1002S-WX2. The WD1002C-WX2 is a 10 inch x 3.90
inch board and includes either a 50 pin external connector or a 62 pin external connector. The connector
allows the user to configure a system easily with
external Winchester drives. The board contains one
internal connector and one external connector and
a maximum of 2 drives can be attached. The 50-pin
external connector will control one external drive configured as Drive 0 or Drive 1. The 62 pin connector carries all the signals required to control up to two
external drives. In either case, the maximum number
of drives supported is two, so if the 62 pin connector
has 2 drives attached, no drive may be attached to
the internal connector.

Winchester Board Products

The WD1002C-VYX2 supports drives with up to 16
heads and supports the following stepping rates: 3
msec, 18lJsec, 30 IJsec, 45lJsec, 60 IJsec, 75IJsec and
210 IJsec.
The WD1002C-WX2 interfaces directly to the Host 1/0
via the IBM PC bus. Data transfer to and from the controller can be either programmed 1/0 or DMA.
The BIOS is dynamically configurable at the time of
formatting the drive. The user has two options: to use
a resident set of drive tables, or to define through the
keyboard a new set of customized tables.

6-89

6-90

Winchester Board Products

WESTERN
COR

P

0

DIGITAL

RAT

o

N

WD1002S-WX2 Winchester Disk Controller
FEATURES

DESCRIPTION

The WD1002S-WX2 is a stand-alone, general purpose
Winchester Disk Controller. The WD1002S-WX2 interfaces up to two Winchester disk drives and a Host
Processor, e.g. an IBM XT.

•

8-BIT BI-DIRECTIONAL BUS HOST INTERFACE.

•

IBM XT WINCHESTER CONTROLLER
EMULATION, IBM PC HOST INTERFACE

•

WD10C20 WINCHESTER DATA SEPARATOR AND
WRITE PRECOMPENSATION DEVICE

•

WD11COO-17 LOGIC ARRAY

•

DATA RATES UP TO 5 MBITS/SEC

•

CONTROLS UP TO 2 DRIVES USING SEAGATE
TECHNOLOGY ST506/ST412

•

SUPPORTS DRIVES OF ANY CONFIGURATION
UP TO 1024 CYLINDERS AND 16 R/W HEADS
WITH THE WD1015-24 OR 8 R/W HEADS WITH
THE WD1015-14

•

THE CONTROLLED DRIVES NEED NOT BE OF
THE SAME CAPACITY OR CONFIGURATION

•

ERROR CORRECTION ON DATA FIELD ERRORS,
CRC 10 FIELD VERIFICATION

•

32-BIT ECC POLYNOMIAL FOR ERROR
DETECTION AND CORRECTION

•

READ AND WRITE LONG COMMANDS FOR
CHECKING ERROR CORRECTION CIRCUITRY

•

SELECTABLE AUTOMATIC RETRIES ON ALL
ERRORS

•

AUTOMATIC RESTORE AND RE-SEEK ON ALL
SEEK ERRORS

•

AUTOMATIC FORMATTING

•

512 BYTES PER SECTOR

•

SECTOR INTERLEAVE CAPABILITY

The Winchester interface conforms to the Seagate
Technology ST506/ST412 interface. All necessary
receivers and drivers are included on the board, allowing direct connection to the disk drive(s).
A separate computer access port enables communications between the Host and disk controller.
An 8-bit bi-directional bus and appropriate control
signals comprise this port. Disk read or write data,
status information, and command parameters are
transferred via this bus. An on-board data buffer
allows bus transfers to be executed independently
of the drive's data transfer.
ARCHITECTURE

The WD1002S-WX2 architecture is based on a proprietary chip set consisting of the WD11 COO-17,
WD1010A-05, WD10C20, and WD1015. As illustrated
in Figure 1, the WD1002S-WX2 consists of the following components:
Bi-directional ControllData Bus
Address Decoding Logic
Configuration Switches
Basic Input/Output System (BIOS) ROM
WD11COO-17
WD10C20
Sector Buffer RAM
WD1010A-05
WD1015
Reset Logic

•

MULTIPLE SECTOR READS AND WRITES

•

OVERLAPPED SEEK CAPABILITY ON
BUFFERED-STEP DRIVES

•

SUPPORTS IMPLIED SEEKS ON ALL
COMMANDS

•

INTERNAL DIAGNOSTICS

•

DMA TRANSFER CAPABILITY

•

SUPPORTS INTERRUPTS, INTERRUPT
REQUESTS, AND DMA REQUEST SHARING

•

INCLUDES SOCKET FOR USER SUPPLIED 2716,
2732, OR 2764 ROM

CONFIGURATION JUMPERS

BIOS AVAILABLE

These jumpers configure the WD1002S-WX2 for different disk drive capacities.

•

Winchester Board Products

BI-DIRECTIONAL CONTROL/DATA BUS

The 8-bit, bi-directional bus transmits addresses, commands, data, and status information. This bus links
the WD1002S-WX2 to the Host. Specifically, this bus
transmits data between the Host and Sector Buffer
RAM.
ADDRESS DECODING LOGIC

The purpose of this logic is to decode a valid device
address from the Host.

6-91

=E

c
.....

o
o

N

~

><
N

..;:

BIOS

-

ROM

BUFF.

po

1\

•

H

...

0
S
T

ADDR.

CONTROL

P..

=>

WD
l1COO-17

~

S
T

.

RAM

D

V

10C20

I

'2

v

WD

r--

...

WDATA

RDATA

~

:> ......

.)

R/W

ADO·AD7

=r

..

CONTROL

D

4;-

D
I
S

K DATA/TIMING)

S
K

STATUS

-

H

DATA

K

LOGIC
ARRAY

D

~

0

DECODE

RA

-

:>

r

ICONFIG.

-

.....
DATA

K

WD

DATA

1010A-OS

SEPARATOR

t

;>

,
DISK

WD
101S

CLOCK

CONTROL

:>
~

CONTROL
PROCESSOR

CONTROLLER

t
RESET

FIGURE 1. WD10025-WX2 FUNCTIONAL BLOCK DIAGRAM

6-92

Winchester Board Products

BIOS ROM
The Host, after powering up, interrogates its ports to
determine what devices are connected. The Host uses
information supplied by the BIOS ROM to perform an
install operation. Then, during normal operation, the
BIOS operates much like a driver that is resident in
the Host's memory space. The BIOS ROM is
addressed at Host memory locations CBOOO • CBFFF.
The BIOS is addressed by the AO through A19 bus.
Outputs to the Host are via the Intraboard Com·
mand/Status bus (BDO through BD7) and Host Inter·
face Data/Command bus (DO through D7).
WD11COo-17
The WD11COO·17 incorporates several functions in a
single package. Implementation of these functions
occurs by combining random logic and specialized
circuits. The WD11COO-17 contains the following
circuits:
Status ports
Read and write ports
Sector Buffer RAM addressing and control
ECC
Reset liming
The WD11C00-17 connects directly to the Host Inter·
face Data/Command and Intraboard Command/Data
(ADO-AD7) buses.
WD10C20
The WD10C20 performs phase-locked loop data synchronization on read data from the Winchester drives.
This device also conditions write data to be recorded
on the disk. The WD10C20 includes both frequency
and phase detection. Zero phase error start-up circuitry eliminates problems due to asymmetry. The

WD10C20 requires no adjustments and contains all
data synchronization and write precompensation circuitry in a single device.
SECTOR BUFFER RAM
The Sector Buffer RAM is a 2K x B RAM. The Sector
Buffer allows Host data transfers independent of the
actual drive data transfer rate. The Sector Buffer temporarily stores the following information:
Sector data during Read and Write Commands
Disk format information during a Format
Command
Drive characteristics during a Set Parameters
Command
WD1010A-05
The primary function of the WD1010A-05 is to control data transfers between the disk and the Sector
Buffer. Data transfers take place after the WD1015
Buffer Manager Control Processor positions the
selected head over the desired track. The WD1010A-D5
receives the parameters and commands from the
WD1015 via the ADO through AD7 bus. The
WD1010A-05 interprets the parameter or command,
determines which sectors are involved, and whether
a read, write, or format function is required.
WD1015
The WD1015 manages and controls all commands
and communications between the Host and
WD1010A-05. The WD1015 controls ECC and CRC
functions.
There are two versions of the WD1015. Table 1
describes the differences between the two versions
of the WD1015. The acronym WD1015 refers to both
versions. When a specific reference is made to a
specific version, the appropriate acronym is used.

Table 1. WD1015 DESCRIPTION
FUNCTION

WD1015-14

WD1015-24

REMARKS

Execution of automatic
self-test after Reset
command or power-up

Yes

No

Supports 16 heads

No

Yes

The WD1015-14 sup~orts u~ to eight heads. The
WD1015-14 uses the REDUCED WRITE CURRENT
(RWC) Signal. The WD1015-24 su~s up to 16
heads. The WD1015-24 uses the RWC pin on J1
as HEAD SELECT 3 (HS3). Refer to Table 10 for
further details.

3.5 seconds time-out on
single track steps

No

Yes

3.5 time-out allows removable/servo drives time to
create servo map. WD1015-14 allows 1 second.

Valid

Don't care

Bit 4 of opcode in
Command Control

Refer to Figure 2 for further details.

Step rates

Refer to Table B for further details.

Format Bad Track

Refer to Command Section for further details.

Winchester Board Products

6-93

RESET LOGIC

=E
c
.....

o
o

I\)

en

:ex

The Reset Logic initializes the internal circuitry of the
WD1002S-WX2 during the power-up process or
a low voltage condition. The Reset Logic also disables
the WRITE GATE signal. Disabling WRITE GATE
prevents writing spurious data to the disk drive during power up, power down or a low voltage conditon.

control signals at the second drive from
the WD1002S-WX2 (no more than a total
length of 10 feet or 3 meters) are terminated with a 220 ohm resistor to + 5V
and a 330 ohm resistor to ground.
J2,J3

INTERFACE CONNECTIONS

I\)

The WD1002S-WX2 has four on-board connectors for
user application.
P1

Host interface: 62-pin IBM PC compatible
card edge connector.

J1

Drive control: 34-pin dual row header connector daisy-chained to two drives. The

Drive data: 2D-pin dual row header connectors, radially connected each to its own
drive.

HOST INTERFACE
Connector P1 pins A 1 through A31 are on the component side of the board and B1 through 831 are on
the artwork side. Table 2 describes the Host interface
Connector, P1.

TABLE 2. HOST INTERFACE CONNECTOR (P1) PIN DESCRIPTION
PIN
NUMBER

MNEMONIC

A1
A2
thru
A9

D7
thru
DO

DATA 7
thru
DATA 0

A11

AEN

NOT CONNECTED
ADDRESS ENABLE

A12
thru
A31

A19
thru
AO

ADDRESS BUS
A19 thru AO

A10

B1

GND

GROUND

B2

RST

RESET

B3

+5VDC
IRQ2

B4

B5
thru
B8
B9
B10
B11

6-94

SIGNAL NAME

I/O

FUNCTION

110

a-Bit, tri-state, bi-directional bus. It is used to
transmit data between the Host and Sector Buffer,
and Command Block to the WD1015, status and
drive configuration to the Host. The BIOS transmits
parameter information and commands to the Host
via this bus.

I

AEN is asserted during a DMA mode of operation
making the 1/0 ports 320 hex thru 323 hex inaccessible to the Host. Data transfers and intrabus control is initiated by asserting DACK3. The BIOS
ROM can still be addressed via AO-A19.

I

AO thru A9 are used during programmed 1/0 mode
of operation to address ports 320 hex thru 323 hex.
They are inhibited during DMA by AEN. AO thru A19
addresses the BIOS ROM regardless of the state
of AEN.

I

When asserted, RST places the WD1002S-WX2 into
its initial power-up state.

0

The WD1002S-WX2 asserts IRQ2 to interrupt the
Host upon the completion of a command. Use of
IRQ2 is jumper selectable. Use of IRQ5 is standard.
Refer to Table 10 for further details on jumper selectable options.

NOT CONNCECTED

+5VDC
INTERRUPT
REQUEST
LEVEL 2

+5VDC

NOT CONNECTED

+ 12VDC
GND

+ 12VDC
GROUND

+ 12VDC

NOT CONNECTED

Winchester Board Products

TABLE 2. HOST INTERFACE CONNECTOR (P1) PIN DESCRIPTION (CONT'D.)
PIN
NUMBER
812

MNEMONIC
MEMR

SIGNAL NAME
MEMORY READ

:E
c.....

110

FUNCTION

I

The Host, to read the 810S ROM places the address
on AO thru A19, asserts MEMR and receives the
data via DO thru D7 data bus.

813

lOW

1/0 WRITE

I

The Host or DMA controller asserts lOW when a
data byte is to be written to the WD1002S-WX2.

814

lOR

1/0 READ

I

The Host or DMA controller asserts lOR when a
data or status byte is to be read from the
WD1002S-WX2.

815

DACK3

DMA
ACKNOWLEDGE
CHANNEL 3

I

The DMA controller asserts DACK3 in response
to DRQ3 sent by the WD1002S-WX2. DACK3 enabies DMA data transfer, bypassing port 320 which
was disabled by AEN.

816

DRQ3

DMA
REQUEST
CHANNEL 3

0

WD1002S-WX2 asserts DRQ3 to inform the DMA
controller that data is available for transfer.

0

The WD1002S-WX2 asserts IRQ5 to interrupt the
Host upon the completion of a command.

817
thru
822
823

NOT CONNECTED

IRQ5

824
thru
828
829

NOT CONNECTED

+5VDC

830
831

INTERRUPT
REQUEST
LEVEL 5

+5VDC

+5VDC

NOT CONNECTED
GND

GROUND

DRIVE INTERFACE
DRIVE CONTROL
Control signals are common to all drives and are
daisy-chained to the drives from a single connector,

Winchester Board Products

J1. To terminate the control signals properly, the last
drive in the daisy-chain must have a 220/330 ohm
resistor pack installed. Table 3 describes the drive
control connector, J1.

6-95

o
o

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en

~

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TABLE 3. DRIVE CONTROL CONNECTOR (J1) PIN DESCRIPTION

:E
c
.....

o
o

I\)

SIG.
GND.

SIG.
PIN

MNEMONIC

SIGNAL NAME

I/O

DESCRIPTION

1

2

RWC/HS3

REDUCE
WRITE
CURRENT/HEAD
SELECT 3

0

The WD1015·14 allows this pin to be used as the RWC
pin. The WD1015·24 uses this pin as HS3. Refer to
Table 10 for further details. RWC is used by the drive
to reduce the write current on the inner cylinders. This
lessens the bit shift caused by the greater bit density
on these cylinders. RWC is asserted when the speci·
fied cylinder is reached. HS3 is one of four Head
Select signals decoded by the drive to select one of
16 RIW heads.

3

4

HS2

HEAD
SELECT 2

0

HS2 is one of three (or four) Head Select signals de·
coded by the drive to select one of eight (or 16) RIW
heads.

5

6

WG

WRITE GATE

0

WG is asserted when valid data is to be written. It is
used by the drive to enable the write current to the head.
WD1002S·WX2 de·asserts this signal when a WF is
detected. Circuitry is included to ensure the output does
not glitch during power on, power down or power
failure.

7

8

SC

SEEK
COMPLETE

I

SC informs the WD1002S·WX2 that the selected head
has reached the desired cylinder and has stabilized.
Since SC is not checked after a Seek Command,
overlapped seeks are allowed.

9

10

TKOOO

TRACK 000

I

The drive asserts this signal when the heads are posi·
tioned over the outermost cylinder, cylinder O.

11

12

WF

WRITE FAULT

I

WF is asserted by the drive when a write error
occurs. The command in progress aborts and no other
comand can be executed while this signal is asserted.

13

14

HSO

HEAD
SELECT 0

0

HSO is one of three (or four) Head Select signals de·
coded by the drive to select one of eight (or 16) RIW
heads.

GND

GROUND

en

=e

><

I\)

15
16

NOT CONNECTED

17

18

HS1

HEAD
SELECT 1

0

HS1 is one of three (or four) Head Select signals
decoded by the drive to select one of eight (or 16) RIW
heads.

19

20

INDEX

INDEX PULSE

I

This signal indicates the start of a track. It is used as
a sychronization point during formatting and as a time
out mechanism for retries. This signal pulses once for
each revolution of the disk.

21

22

DRDY

DRIVE READY

I

The drive asserts this signal when the motor is up to
speed. No Read or Write commands can be performed
if this signal is not asserted.

6-96

Winchester Board Products

TABLE 3. DRIVE CONTROL CONNECTOR (J1) PIN DESCRIPTION (CONT'D.)
SIG.
GND.

SIG.
PIN

MNEMONIC

SIGNAL NAME

1/0

DESCRIPTION

23

24

STEP

STEP PULSE

0

STEP along with DIRIN positions the heads to the
desired cylinder. STEP pulses the stepping motor at
the rate specified by the SP bits in the Command
Block and is controlled by the WD1015. DIRIN specifies the direction.

25

26

DSEL 0

DRIVE SELECT 0

0

DSEL 0 is the decoded output of the SDH Register
within the WD1010A-05, latched and sent to the drive
by the WD1015 to select drive O.

27

28

DSEL 1

DRIVE SELECT 1

0

DSEL 1 is the decoded output of the SDH Register
within the WD1010A-05, latched and sent to the drive
by the WD1015 to select drive 1.

29,
31

30,
32

33

34

0

DIRIN determines the direction the RIW heads take
when stepped. Asserted
in, de-asserted
out.

NOT CONNECTED
DIRECTION IN

DIRIN

DRIVE DATA CONNECTOR
The data is differential in nature and must be connected to each drive with its own cable, drive 0 to J2
and drive 1 to J3. It should be a flat ribbon cable,

=

=

or twisted pair, less than 3 meters (10 feet) in length.
The connector is a 20·pin vertical header on 0.25 cen·
timeter (0.1 inch) center. Table 4 describes the drive
data connectors, J2 and J3.

TABLE 4. DRIVE DATA CONNECTORS - J2, J3
SIG.
GND.

SIG.
PIN

1/0

1
2
3
4

5
6
7
8
9
10
11
12
13
14

0
0

17
18

I
I

15
16

19
20

SIGNAL NAME
NC
GND
NC
GND
NC
GND
NC
GND
NC
NC
GND
GND
+ M FM Write Data
- MFM Write Data
GND
GND
+ M FM Read Data
- MFM Read Data
GND
GND

COMMAND DESCRIPTION
This section provides a detailed description of the
Command Block format and function of the 19 commands supported by the WD1002S-WX2.

Winchester Board Products

Fourteen of the commands are operational and five
are diagnostic. Table 5 lists a summary of the
commands.

6-97

TABLE 5. COMMAND SUMMARY
COMMAND

PARAMETERS (Refer to Figure 2)
OP CODE

DRV

HD

CYL

SEC

BLK/INT

R1

R2

STEP

TEST DRIVE READY

00

V

n

n

n

n

n

n

n

RECALIBRATE

01

V

n

n

n

n

V

n

n

READ STATUS OF
LAST OPERATION

03

V

n

n

n

n

n

n

n

FORMAT DRIVE

04

V

V

V

DR

V(INl)

V

n

V

VERIFY SECTORS

05

V

V

V

V

V(BLK)

V

V

V

FORMAT TRACK

06

V

V

V

DR

V(INl)

V

n

V

FORMAT BAD TRACK

07

V

V

V

DR

V(INl)

V

n

V

READ SECTOR

08

V

V

V

V

V(BLK)

V

V

V

WRITE SECTORS

OA

V

V

V

V

V(BLK)

V

n

V

SEEK

OB

V

V

V

DR

n

V

n

V

INITIALIZE DRIVE
PARAMETERS

OC

V

n

n

n

n

n

n

n

READ ECC BURST
ERROR LENGTH

OD

V

n

n

n

n

n

n

n

READ SECTOR BUFFER

OE

n

n

n

n

n

n

n

n

WRITE SECTOR BUFFER

OF

n

n

n

n

n

n

n

n

EXECUTE SECTOR
BUFFER DIAGNOSTIC

EO

n

n

n

n

n

n

n

n

EXECUTE DRIVE
DIAGNOSTIC

E3

V

n

n

n

n

V

n

V

EXECUTE CONTROLLER
DIAGNOSTIC

E4

n

n

n

n

n

n

n

n

READ LONG

E5

V

V

V

V

V(BLK)

V

n

V

WRITE LONG

E6

V

V

V

V

V(BLK)

V

n

V

LEGEND:

I/O PORT DESCRIPTION

V
DR

There are four contiguous I/O ports addressed 320
hexidecimal through 323 hexidecimal. Each port is
bi-directional. The functions of the I/O ports are listed
in Table 6. These ports are used for all communication between the Host and Controller.

Must be a valid parameter
Not used but must be within a valid parameter
range
Not used (should be 0 for future compatibility)
Interleave
Block Count

n
INT
BLK

TABLE 6. I/O PORT DESCRIPTIONS
ADDRESS

READ PORT FUNCTION

WRITE PORT FUNCTION

320

READ DATA

WRITE DATA

321

READ WD1002S·WX2 HRDWR STATUS

WD1002S-WX2 RESET*

322

READ DRIVE CONFIGURATION INFO

WD1002S-WX2 SELECT

323

~ot Used

WRITE DMA AND INTERRUPT MASK
REGISTER

*NOTE
The WD1015·14 automatically executes self·tests after either a Reset command or upon power-up. The WD1015-24
DOES NOT automatically execute self·test after either a Reset command or upon power·up. A WD BIOS performs
an Execute Controller Diagnostic command as part of the install sequence after power-up regardless of the version
of WD1015 on·board. If the Host software interrogates WD1015-24 after a Reset; the WD1015-24 returns good status.
The Host must issue an Execute Controller Diagnostic command to perform the WD1015-24 self-test.

6-98

Winchester Board Products

PORT 320
This is a bi·directional path over which data, com·
mands, parameters, and status are passed.
PORT 321
The Host reads this port to interrogate the hardware
status. This status byte can be read at any time,
including command execution. The status bits are
identified in Table 7.
TABLE 7. HARDWARE STATUS

6
d

7
d

BIT
5
4
3
2
IRQ DRO BSY CID

1
I/O

0
REO

d

Not used

IRQ

Interrupt Request. Assertion (set to 1)
signifies that an interrupt is pending.

DRO DMA request bit. Assertion (set to 1)
signals the Host that the WD1002S·WX2 is
ready for a DMA transfer to take place. The
direction of the transfer is defined by the
1/0 bit.
BSY

Busy bit. Assertion (set to 1) signals the
Host that the WD1002S·WX2 is busy
executing a command and is unable to
accept another command.

CID

ControllData. Tells the Host which type of
transfer the WD1002S·WX2 is expecting. 1
command or status byte. 0
data.

1/0

Input/Output. Identifies the direction of
transfers between the Host and WD1002S·
WX2. The terms input and output are
relative to the Host. 1 = input, 0 = output.

=

=

REO Request bit. A handshake signal for data
transfers between the Host and WD1002S·
WX2. The WD1002S·WX2 asserts (sets to 1)
this bit when it is ready for data to be
transferred between it and the Host. REO
must be valid for every byte transferred to
the Host.

The Host writes to this port to generate a MR (Master
Reset) on the WD1002S·WX2. When writing to this
port, the data byte is ignored.
Resetting a WD1002S·WX2 with a WD1015-14 causes
automatic execution of a self·test. Automatic execu·
tion of self·test does not occur with the WD1015-24.
If the Host software interrogates WD1015-24 after a
Reset; the WD1015-24 returns good status. The Host
must issue an Execute Controller Diagnostic com·
mand to perform the WD1015-24 self·test.
PORT 322
Reading Port 322 returns a 4-bit drive configuration
code in bits 0 through 3. The two least significant bits
correspond to drive 0, the two most significant bits

Winchester Board Products

to drive 1. The configuration of these bits is
established with jumpers on the controller at SW1.
Western Digital sets the configuration jumpers to one.
Table 11 shows how to set them up for a specific
drive.
The two bits associated with each drive is capable
of addressing one of four different configuration
tables. Both drives can address the same or different
tables. The table required by the drive is determined
by its formatted capacity. Table 0 = 5MB, 1 = 24MB,
2 = 15MB,3 = 10MB (default table) with 62-00004201 and 62..()()()()42-11 WD BIOS. Table 0 = 20MB, Table
10MB, Table 2
20MB, Table 3
10MB with
1
62-000042-12 WD BIOS.

=

=

=

The parameters established by these tables are:
Number Of Cylinders
Number Of Heads
The Starting Cylinder For RWC (Reduced
Write Current).
The Starting Cylinder For Write Precomp
Maximum Correctable Error Burst Length
Retries Allowed, Stable or Immediate ECC
Correction, Step Rate
Writing to port 322 selects the WD1002S·WX2, sets
the Busy bit in the Status Register and prepares it
to receive a command. When writing to port 322, the
data byte is ignored.
PORT 323
Reading this port has no function.
Writing to this port controls the enabling of the inter·
rupt and DMA request signals to the Host. The bits
in this port are defined as follows:
BIT
7

d

6
d

5
d

4
d

3
d

2
1
0
d IROEN DROEN

IROEN

Interrupt Request Enable. When asserted
(set to one), enables interrupts to the Host.

DROEN

DMA Request Enable. When asserted (set
to one), enables DMA requests to the Host.

COMMAND BLOCK
The Host first selects the WD1002S·WX2 by asser·
ting IIOW while at the same time addressing port
322 with the AO through A19 address bus. The
WD1002S·WX2 then asserts the BSY (BUS.Yl....Qit in the
Status Register. The Host by asserting lIaR and
addressing port 321 reads the status, finding REO
asserted transmits the first byte of the six byte Com·
mand Block to the WD1015. REQ is de·asserted at
the end of the first byte transfer. REQ must be reo
asserted for the second byte of the Command Block
transfer. Assertion and de·assertion of REO must
occur for each byte transferred. Figure 2 defines the
bytes within the Command Block.

6-99

:ec

BITS

....
o

BYTE

I

7

6

I

5

I

o

N

1

~

2

en

><

N

I

4

3

I

2

0

D

0

CYL NUMBER MSB

I

0

I
I

0

I

1

I

0

I

SP

HEAD NUMBER
SECTOR NUMBER

3

CYLINDER NUMBER LSB

4

BLOCK COUNT OR INTERLEAVE

5

I

OP CODE

0

R1

I

R2

I

0

I

0

I

0

I

SP

I

SP

FIGURE 2. COMMAND BLOCK DESCRIPTION
OP Code:

Operation Code identifies the type and function of the command. Bits 7, 6, and 5 designate
whether the command is operational (0) or diagnostic (5). Bits 4 through 0 select the function of the command, i.e. Read, Write, etc.

NOTE
The WD1015-24 firmware ignores bit four of byte 0 (op code).
D

Drive number, selects one of two drives zero or one.

Head Number

Designates the head to be used on the selected drive. 0 through 15. Selection of heads
8 through 15 requires WD1015-24.

Cylinder Number
MSB and LSB

Designates the cylinder containing the sector(s) to be used by the command. 0 through
1024.

Sector Number

Specifies the starting sector used by the command.

Block Count or
Interleave

Block count specifies the number of sectors to be used by a Read, Write, Read Long,
or Write Long command. A block count of zero equals 256 sectors. Interleave is used
by the Format commands. The maximum int~rleave is equal to the sectors-per-track minus
one.

R1

General disk error retry disable bit. R1 controls the retry for all errors except a Data ECC
error. With R1 asserted, the WD1002S-WX2 makes no attempt to retry an error operation.
Instead, it aborts the command and sets the appropriate status in the Status Register.
Because the disk is soft sectored, an ID field error may cause the WD1002S-WX2 to perform two retries. With R1 de-asserted, the WD1002S-WX2 retries the operation approximately ten times before aborting the command and setting the status bit. In the case
of an ID Not Found Error, the WD1002S-WX2 does a restore to track zero and seeks back
to the desired track after the first ten tries and then makes ten more tries before aborting and setting the error status.

R2

ECC Error retry bit. With R2 = 1, an attempt is made to correct the error on the first
syndrome. R2 = 0 there must be two consecutive like syndromes before an attempt is
made to correct the error.

SP

The Step Code is used to select the rate at which step pulses are issued to the drive.
Table 8 defines the rates corresponding to each step pulse code.

6-100

Winchester Board Products

TABLE 8. STEPPING RATE CODES

2
0
0
0
0
1
1
1
1

BITS
1
0
0
1
1
0
0
1
1

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STEPPING RATES
0
0
1
0
1
0
1
0
1

3
3
3
3
200
70
3
3

WD1015-24
3 msec. per step *
45 /-lsec. per step
60 /-lsec. per step
18 /-lsec. per step
210/-lsec. per step
75 /-lsec. per step
30 /-lsec. per step
18 /-lsec. per step

WD1015·14
msec. per step*
msec. per step
msec. per step
msec. per step
/-lsec. per step
/-lsec. per step
msec. per step
msec. per step

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*This is the preferred 3 msec. step code.
TEST DRIVE READY (OP CODE 00)
This command selects the drive specified by the
DRV bit in the Command Block and interrogates the
bRDY, WF, and SC signals returned by that drive. If
WF and SC are de-asserted and DRDY asserted,
the command returns an error code of 00 No Error
Detected.
POSSIBLE ERROR CODES
03
Write Fault
04
Drive Not Ready
08
Drive Still Seeking
RECALIBRATE (OP CODE 01)
This command moves the ReadlWrite heads to track
O. The SC signal from the drive controls the stepping
rate of this command. Therefore, this command is
slower than commands that implement the implied
seek and make use of the stepping rate designated
by the SP bits in the Command Block.
NOTE
Timeout on each step during a Recalibrate command
is 1 second with a WD1015-14. Timeout on each step
during a Recalibrate is 3.5 seconds with a WD1015-24.
The 3.5 second timeout supports removable Winchesters.
POSSIBLE ERROR CODES
03
Write Fault
04
Drive Not Ready
06
Track Zero Not Found

READ STATUS OF LAST OPERATION (OP CODE 03)
Upon termination of a command the WD1002S-WX2
develops a Command Completion Byte, de-asserts
the BSY bit, if IROEN had been enabled, asserts IR05.
If IROEN had not been asserted, it is the responsibility
of the Host to read port 321 to determine that a
WD1002S-WX2 is no longer busy. Once the Host
determines that a command has terminated, it must
read the Command Completion Byte to learn which
drive has terminated and whether an error had occurred. To do this, the Host reads port 320. The format
of the Command Completion Byte is as follows:

=

BYTE

BITS
7

6

0

AV

0

1

0

0

2

=

D
Number of the drive terminating. 0
drive O.
1 = drive 1
E = 1 if an error occurred
If the Command Completion Byte indicates the
occurence of an error, issue a Read Status command
for the drive indicating the error. Preformance of a
Read Status command before any other command
execution prevents loss of the error status. When a
Read Status of the last operation is written to port
320, the WD1002S-WX2 responds with four bytes of
status as shown in Figure 3.

CYL NUMBER MSB

3

5
D

I

4

I

I
I

0

I

I

3

2

I

1

I

0

ERROR CODE
0

HEAD NUMBER
SECTOR NUMBER

CYLINDER NUMBER LSB

AV Address valid bit.
Indicates that the Head, Cylinder, and Sector fields are valid.
Error Codes are shown in Table 9
All other bits are the same as those defined in the Command Block definitions.
FIGURE 3. FOUR STATUS BYTES

Winchester Board Products

6-101

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When an error occurs during a multiple sector data
transfer (read or write), this command returns the
address of the failing sector. If the Read Status command is issued after any of the format commands
or the Verify Desired Sectors command, the address

TABLE 9. CONTROLLER RETURNED ERROR CODES

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returned by the WD1002S-WX2 points one sector
beyond the last track formatted or blocked, if there
was no error. If there was an error, then the address
returned points to the track in error.

HEX
CODE
00
02
03

04
06
08
11
12
15
18

19

20
21

30
31
32

DEFINITION
No error detected.
No SC signal from the drive. The WD1002S-WX2 has not received a SC from the drive within one
second (3.5 seconds with WD1015-24) following the last step pulse of a non-buffered seek operation.
Write Fault signal received from the drive. This error is reported when the WD1002S-WX2 detects WF
asserted by a drive either at the completion of a Sector Data Transfer or after initially selecting
a drive and the drive indicates ready.
Drive Not Ready. The WD1002S-WX2 reports this error when DRDY is not received from the drive
at the time selection is attempted, or is de-asserted after the drive has been selected.
Track 0 Not Found. This error is reported during a Recalibrate command if TKOOO is not received from the drive before stepping the ReadlWrite Heads 1024 steps.
Drive Still Seeking. This status is returned in response .!Q..a Test Drive Ready command when a
drive performing a buffered seek has not yet asserted SC.
Uncorrectable Data Error. The ECC logic detected an error burst greater than its correction
capabilities. The data in the Sector Buffer is not sent to the Host.
Data Address Mark Not Found. The proper Sector ID was read by the drive but failed to detect
the Data Address Mark.
Seek Error. The desired Sector ID field could not be found on the selected track, or a CRC error
occurred on the ID field.
Correctable Data Error. An error occurred in the data field that was within the tolerance of the
ECC logic and was corrected. The data in the Sector Buffer is transmitted to the Host. This status
is set as a warning to the Host that a marginal condition may exist.
Track Is Flagged Bad. A sector had been encountered that has the Bad Block Mark set in the ID
Field. The Format Bad Track command records this bit in all sectors of the designated flagging
them all as bad. No retries are attempted in response to this error.
Invalid Command. The WD1002S-WX2 has received a command with an invalid class or Op code,
Interleave Factor.
Illegal Sector Address. This error is asserted when a command attempts to address a sector beyond
the capacity of the drive. This could be at the time the command is issued, or in the case of a
multiple sector transfer, after the last available sector has been used.
Sector Buffer Error. An error occurred while preforming Sector Buffer Diagnostics (Command Code
EO and E4). A disk drive is not involved in this test.
Controller ROM Checksum Error. A ROM checksum error was detected during the Controller
Diagnostic command (E4).
ECC Polynomial Error. During the Controller Diagnostic command (E4), the hardware ECC generator
(WD11COO-17) failed its test.

FORMAT DRIVE STARTING AT DESIRED TRACK
(OP CODE 04)
The WD1002S-WX2 first positions the ReadlWrite
heads to track zero. Using the parameters specified
in the Command Block, the WD1002S-WX2 positions
the heads to the desired track. Formatting always
starts with the first sector of the track, regardless of
the value of SEC. Even so, SEC must be within the
allowable limits. A sample of what is recorded in

6-102

each sector is shown in Figure 4. The data recorded
in the Data Field is defaulted to whatever is in the
Sector Buffer at the time. The logical sector numbering is specified by the interleave value (INT) included
in the Command Block. If a hard error occurs while
formatting a track, the WD1002S-WX2 stops the format operation and returns an error code.

Winchester Board Products

REPEATED FOR EACH SECTOR

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GAP.
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BYTES
'00'

A
I

I
0
E
N

C

L

y

0
L W

T

I

H
E
A
0

S
E

.

C

C
R
C
I

C
R

3 SYTES
'00'

C

I
I
WRITE GATE

ORUN~

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I

12 BYTES
00'

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8

USEROI.TA

36YlES

HCC

'00'

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NOTES:

10 FIELD

A1

IDENT

HEAD =

Sec#

1. GAP 1 and 3 length equals 22 bytes.

A1 Hex with
OA Hex clock
Bits 1,0 = Cylinder High
FE = 0-255 Cylinders
FF = 256-511 Cylinders
FC = 512=767 Cylinders
FD = 768-1023 Cylinders
Bits 0,1,2 = Head Number
Bits 3,4, = 00
Bits 5,6, = Sector Size (10)
Bit 7 = Bad Block Mark
Logical Sector Number

A1
F8
USER

2. The decision to assert RG is made 2 bytes after
the start of DRUN.
3. RG de-asserted:
• If DRUN does not last until A1
• When any part of 10 does not match the one
expected.
• After CRC if correct 10 has been read.

4. Write splice recorded on disk by asserting WG.
5. RG is suppressed until after write splice.
6. Not a proper A 1 or F8, set DAM error.
7. Sector size as stated in 10 field, plus four for ECC.

DATA FIELD
A1 Hex with OA Hex clock
Data Address Mark; Normal
Clock
Data Field 512 Bytes

FIGURE 4. FORMAT

Winchester Board Products

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DATA FIELD

6-103

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INTERLEA VING

When physically sequential sectors on the disk are
to be read, each sector reaches the read/write head
before a read or write operation can be set up. The
disk must then make a complete rotation to pick up
the next sector. When an attempt is made to read all
17 sectors on a particular track, 17 rotations or
approximately one fourth of a second per 8K bytes
are required. This performance can be significantly
improved by interleaving, a technique that allows the
system to read or write more than one sector per rotation.

For a system requiring less than two sector times to
proccess the data it has read and to set up for the
next read operation, the second logical sector is
physically placed three sectors away from the first.
The controller can now read the second sector with
minimal delay. This three-to-one interleave factor
allows a potential reading of the entire track in less
than three rotations. In the example given, the
throughput is increased by a factor of 5.6.

1
OB

INDEX

PULSE

00

FIGURE 5. 17 SECTORS WITH A 3:1 INTERLEAVE

6-104

Winchester Board Products

The simplest way to determine the optimum interleave
for any particular system is through experimentation.
If the system maintains its directories or virtual
memory-swapping areas in a certain place of the disk,
it sometimes makes sense to have more than one
interleave.
To simplify driver software, the WD1002S-WX2
automatically writes the logical sector number of
each sector in its 10 field. Figure 5 is an example of
an interleave table for a 17-sector track with 3:1
interleave. The WD1002S-WX2 accepts any interleave
value between zero and one less than the number of
sectors per track. An interleave of zero is
automatically converted to one, and a value out of
range results in an error code 20, Invalid Command
Error.

VERIFY SECTORS (OP CODE 05)

This command reads from 1 to 256 sectors, as
specified by BlK in the Command Block, beginning
at the sector specified by H 0 CYl and SEC. If an error
occurs during a multiple sector read, the heads
remain positioned at the track containing the error.
The Host then issues a Read Status of last Disk
Operation command to determine the error code. To
continue the operation, the Host calculates the difference between the number of sectors desired and
the number of sectors completed and issues another
Seek command to access the remaining sectors.
POSSIBLE ERROR CODES

02
03
04
06
12
15
19
21

No Seek Complete
Write Fault
Drive Not Ready
Track Zero Not Found
Data Address Mark Not Found
Seek Error
Track Flagged Bad
Illegal Disk Address

FORMAT TRACK (OP CODE 06)

This command is identical to the Format Drive command, except that only the track specified by the command is formatted. This command can be used to
clear the Bad Track Flag, or reformat individual tracks.

Winchester Board Products

6-105

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FORMA T BAD TRACK (OP CODE 07)

WRITE SECTORS (OP CODE OA)

This command is the same as the Format Track command, except that the Bad Track Flag is set in the
ID field.

This command writes from 1 to 256 sectors as
specified by BlK in the Command Block. The multiple sector transfer scheme works the same as the
Read command. Error code 06 can only be asserted
if the R1 bit is 0 and ten consecutive attempts have
failed to read the ID Field. This causes the WD1002SWX2 to recalibrate the heads and seek back to the
desired track. If track zero is not detected within 1024
steps, Error Code 06 is set. If R1 is 1, the WD1002SWX2 aborts the command on the first failure to read
an 10 Field. Therefore, no attempt to position the
heads to track zero is made.

(J)

READ SECTORS (OP CODE 08)

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This command reads from 1 to 256 sectors as specified by BlK in the Command Block, beginning at the
sector defined by CYl SEC and Head. An uncorrectable error during a multiple sector read causes the
operation to terminate at the error sector. The Host
then issues a Read Status of last Disk Operation
command to determine the type of error. To continue
the operation, the Host calculates the difference
between the number of sectors desired and the
number of sectors completed, then issues another
Read commend to access the remaining sectors. Error code 06 can only be asserted if the R1 bit = 0 and
ten consecutive attempts have failed to read the ID
Field. This causes the WD1 002S-WX2 to recalibrate
the heads and seek back to the desired track. If track
zero is not detected within 1024 steps, Error Code
06 is set. If R1 = 1, the WD1002S-WX2 aborts the
command after a maximum of two tries to read the ID
field. Therefore no attempt is made to position the
heads to track zero.

POSSIBLE ERROR CODES

02
03
04
06
12
15
19
21

No Seek Complete
Write Fault
Drive Not Ready
Track Zero Not Found
Data Address Mark Not Found
Seek Error
Track Flagged Bad
Illegal Disk Address

POSSIBLE ERROR CODES

02
03
04
06
11
12
15
18
19
21

No Seek Complete
Write Fault
Drive Not Ready
Track Zero Not Found
Uncorrectable ECC Error
Data Address Mark Not Found
Seek Error
Correctable ECC Error
Track Flagged Bad
Illegal Sector Address

6-106

Winchester Board Products

SEEK (OP CODE OB)

INITIALIZE DRIVE PARAMETERS (OP CODE OC)

This command selects the head and initiates a seek
to the track specified by HD and CYL in the Command
Block. The SC signal line is sampled to allow
buffered seeks. The cylinder must be in range. The
drive must be formatted. Drives employing buffered
steps can be issued step pulses at a high speed, freeing the WD1002S-WX2 for other operations. The
WD1002S-WX2 does not wait for the drive to complete
the seek to return a Command Completion Status.
If the return status shows no error, the seek was
issued correctly. If there is an error, the seek was not
issued. After transferring the status, another command can be issued to either drive. If the WD1002SWX2 receives a command other than Test Drive Ready
for a drive that is still seeking, it asserts BSY and
waits for SC to be asserted before executing the
command. If the command is a Test Drive Ready, it
executes and returns an 08 Drive Still Seeking Error.
The time-out for non-buffered seeks is 1 second for
a WD1002S-WX2 with a WD1015-14. A WD1002S-WX2
with a WD1015-24 times out for 3.5 seconds for nonbuffered seeks. For buffered seeks, the WD1015
checks SC before a Read or Write (next command).

The WD1002S-WX2 is capable of controlling two
drives with different formatted capacity. The BIOS
contains four Winchester parameter tables. The configuration jumpers address the proper Winchester
parameter table during the BIOS install cycle at power
up. Refer to Table 11 for details on these jumper settings. When the Host reads port 322 and discovers
a change in drives, it issues this command, followed
by the 8-byte block of drive parameters listed below:

The rate at which the Step Pulses are issued to the
drive is controlled by the SP bits in the Command
Block. The drive buffers these pulses and steps at
its own rate. This allows the WD1002S-WX2 to continue about its own business, possibly starting the
other drive seeking to a new track, without having to
wait for the SC from the first drive. Refer to Table
8 for the available stepping rates.

Maximum Number of Cylinders (2 bytes, 1024
max.)
Maximum Number of Heads (1 byte, 8 or 16 heads)
Starting Reduced Write Current Cylinder (2 bytes,
1024 max.)
Starting Write Precompensation Cylinder (2 bytes,
1024 max.)
Maximum ECC Data Burst Length (I byte, max.)
A typical set of parameters for a 10MB drive is as
follows:
306 cylinders
4 heads
RWC at cylinder 153
Write Precomp at cylinder 153
11-bit burst error length (Western Digital Corp.
recommends using a maximum ECC burst
length of five or less to ensure optimum
integrity of data recovered).
For the exact parameters, it is necessary to refer to
the specifications for the BIOS in use on the specified
board.

POSSIBLE ERROR CODES

03 Write Fault
04 Drive Not Ready
15 Seek Error

Winchester Board Products

6-107

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READ ECC BURST ERROR LENGTH
(OP CODE 00)

This command is only valid following' a correctable
ECC error. It transfers one byte indicating the length
of the error. The error length is determined by counting the first through last bit in the error.
READ SECTOR BUFFER (OP CODE OE)

This command transfers the 512 bytes of data currently residing in the Sector Buffer to the Host.
WRITE SECTOR BUFFER (OP CODE OF)

This command writes 512 bytes of data from the Host
into the WD1002S-WX2 Sector Buffer.
EXECUTE SECTOR BUFFER DIAGNOSTIC
(OP CODE EO)

This command executes a 9-pass test that uses a
O-byte pattern (0,1,2,4,8,10,20,40, and 80 hex) that
is written to the Sector Buffer, then read back. After
each successful completion, the whole pattern is
shifted one byte postition and repeated.
NOTE

The WD Format Drive Utility in the WD BIOS executes
this command before physical formatting of the drive.
Thus, the data fields are formatted with this 0, 1, 2,
4, 8, 10, 20, 40, and 80 hex pattern.

6-108

POSSIBLE ERROR CODES

30 Data error
EXECUTE DRIVE DIAGNOSTIC
(OP CODE E3)

This command tests both the drive and the drive-toWD1002S-WX2 interface. The WD1002S-WX2 sends
Recalibrate and Seek commands to the selected drive
and reads sector zero of each track verifying both 10
and data fields. The WD1002S-WX2 does not perform
any write operations.
5.19.1 POSSIBLE ERROR CODES

02
03
04
06
12
15

No Seek Complete
Write Fault
Drive Not Ready
Track Zero Not Found
Data Address Mark Not Found
Seek Error

EXECUTE CONTROLLER DIAGNOSTICS
(OP CODE E4)

Regardless of the version of the WD1015 on the
WD1002S-WX2, the WD1002S-WX2 executes this command when the Host issues a command code of E4
hex to the GGB. The WD1015-14 automatically
executes this command after system Reset (RST on
connector P1 82 asserted), write to port 321 Hex, or
power-up. The WD1015-24 only automatically
executes this command when an on-board WD BIOS
performs an install sequence after power-up.

Winchester Board Products

Once started, this command continues to run until
an error occurs, or the Host selects the WD10028-WX2
by writing to port 322. If an error occurs when this
command has been started at power up, an error code
is output at pins 27, 28, and 29 of the WD1015. These
are the Head Select 0, 1, and 2 signals and can be
monitored at the Drive Control Connector J1 pins 14,
18, and 4. The error codes generated under this condition are not the same as those reported by a Read
Status command.
1
2
3
4
5

- WD1 01 OA-05 Error
- WD11C00-17 ECC Error
- Sector Buffer Error
- WD1015 RAM Error
- WD1015 ROM Error

SECTOR BUFFER TEST

The hex pattern 00, 01, 02, 04, 08,10,20,40,80 is written throughout the entire Sector Buffer and then read
to make sure it is correct. The entire contents of the
Sector Buffer is then shifted one byte position and
read again. This procedure is repeated nine times verifying that every bit in the Sector Buffer can be set
and reset.
The WD11COO-17 is enabled during the read functions
to verify the operability of that device.
WD1015 RAM TEST

This tests the 100 bytes of internal RAM in the same
manner as the Sector Buffer test.

WD1 01 OA-05 TEST

WD1015 ROM TEST

A pattern is written to and read from the
WD1010A-05's Sector Count and Sector Number
Registers.

This test verifies the ability to address and read all
2K bytes of internal ROM, using an add and rotate
algorithm to generate a single byte result. This result
is then compared with the Sumcheck located in the
last page of memory.

WD11 COO-17 ECC TEST

The WD11C00-17 is enabled during the read portion
of the Sector Buffer Test. After the contents of the
Sector Buffer have been read, the ERR (pin 1) of the
WD11COO-17 is monitored, it should be asserted
indicating non-zero Check Bytes. The internal check
pattern is then fed back into the chip and pin 1
monitored again. This time it should not be asserted,
indicating a Check Byte pattern of zero.

Winchester Board Products

POSSIBLE ERROR CODES

30 Sector Buffer Error
31 ROM Sumcheck Error
3 ECC Error

6-109

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READ LONG (OP CODE ES)

INSTALLATION

The Host first performs a normal Write command,
writing known data, that produces a predictable ECC
character, then performs a Read Long command. This
command reads the data from the disk without
generating a ECC bytes of its own. Instead, it reads
the four ECC bytes from the disk, as though reading
data, resulting in 512 plus 4 for a total of 516 bytes
of data. The Host, knowing what the data and ECC
bytes are supposed to be, can now determine whether
any errors that have occurred are a result of a data
or ECC failure.

HARDWARE AND SOFTWARE INSTALLATION

POSSIBLE ERROR CODES

02
03
04
06
12
15
19
21

No Seek Complete
Write Fault
Drive Not Ready
Track Zero Not Found
Data Address Mark Not Found
Seek Error
Track Flagged Bad
Illegal Disk Address

WRITE LONG (OP CODE E6)

After performing the Write normal/Read Long routine
to determine that the WD1002S-WX2 is able to write
data and generate correct ECC bytes, the Host can
execute a Write Long and Read normal routine. This
verifies the ability of the WD1002S-WX2 to read the
data correctly and generate 4-zero ECC bytes or if an
error was forced, correct it. The Write Long command
does not generate ECC bytes, instead the Host supplies them along with a known data pattern. Then,
performing a normal Read command, the Host can
determine whether non-zero ECC bytes are caused
by a Read failure or ECC generation failure. (This
procedure could be performed prior to the Write
normal/Read Long).
POSSIBLE ERROR CODES

02
03
04
06
12
15
19
21

No Seek Complete
Write Fault
Drive Not Ready
Track Zero Not Found
Data Address Mark Not Found
Seek Error
Track Flagged Bad
Illegal Disk Address

6-110

This section briefly describes installation of the
WD1002S-WX2 in an IBM PC or IBM-compatible
computer.
1. Ensure system power is off.
2. Insert WD1002S-WX2 in computer chassis and
connect drive cables.
(J1
control cable, J2
drive 0 cable, J3
drive
1 cable)
3. Power up the system.
4. Insert IBM PCDOS 2.0 or IBM PCDOS 2.1 diskette.

=

=

=

CAUTION

Performing steps 5 through 9 destroys any data
presently on the disk.
5. Load DEBUG utility by typing "debug" and ENTER
after the DOS prompt.
6. Initiate the WX2FMT (format) program by typing
the following command line: g = cBOO:5
7. Press "y" to begin formatting drive 0 (logical
drive C.)
B. To format drive 1 or second drive in a daisy chain,
reload DEBUG utility. Type "RAX" and ENTER.
Prompt returns "AX 0000". Type "0103", ENTER
which defines relative drive number and interleave
factor (01
relative drive number; 03
interleave
factor). Type "G CBOO:5", ENTER, and type "y"
to begin formatting drive 1 (logical drive D).
9. Run standard DOS utilities, FDISK and FORMAT.

=

=

=

JUMPER INSTALLATION AND LOCATIONS

The WD1002S-WX2 is configured for the standard IBM
PC XT with jumper plugs installed at W3, W4, and W6.
No jumpers are required at W5 and W7. To change
the configuration, a jumper plug can be installed in
the appropriate block. Installation of jumpers on W5
and W7 requires carefully cutting an etch and placing a jumper plug onto the Jumpered position. To
restore the standard setting, move the jumper plug
to the Standard position. Table 10 describes these
jumpers and options. Table 11 describes the drive
configuration jumpers and an INTERRUPT REQUEST
(IRQ) jumper in SW1. Figure 6 illustrates the locations
of W1 through W7 and SW1.

Winchester Board Products

TABLE 10 JUMPER SELECTABLE OPTIONS (W1 THROUGH W5)
JUMPER

W1,W2
W3
W4

FUNCTION

Standard:
Standard:
Jumpered:

:E
c.....

PIN

DESCRIPTION

1-2
1-2
2-3
1-2

For Western Digital Manufacturing use only.
Closed by etch or jumper. Enables BIOS ROM
Open. Disables BIOS ROM.
Selects primary port 320 Hex.
Selects secondary port 324 Hex. Requires
custom BIOS.
NOTE

The WD1002S-WX2 provides two sets of 1/0
ports. The primary port addresses are 320
through 323 Hex. The secondary port
addresses are 324 through 327 Hex. However,
secondary ports on the WD1002S-WX2 are
NOT supported by many versions of DOS.
W5

Standard:
Jumpered:

1-2
2-3

W6

Standard:
Jumpered:

2-3
1-2

W7

Standard:
Jumpered:

1-2
2-3

Winchester Board Products

Selects 2732 or 2764 BIOS ROM size.
Selects 2716 BIOS ROM size. W5 pin 1-2 etch
must be cut.
8 head configuration, RWC used.
16 head configuration, RWC not used, requires
custom BIOS ROM and WD1015-24.
Selects IR05.
Selects IR02. SW1 position 5 must also be
jumpered (closed) and W7 pin 1-2 etch must
be cut.

6-111

o
o

I\)

en

:iE
X

I\)

TABLE 11 SW1 JUMPER BLOCK DESCRIPTION

WD BIOS 62-000042-01 (ROM) or 62-000042-11 (EPROM)
BIOS
TABLE

FORMATIED
CAPACITY

3

10MB

11

11

ST412
Seagate

4

306

0
None

2

15MB

o1

01

ST419
Seagate

6

306

256
RWC= 128

1

26MB

10

10

5820
Evotek

8

375

0
None

0

5MB

00

00

ST506
Seagate

2

306

0
None

POSITION
12
34
DRIVE 1
DRIVE 0

DRIVE
TYPE

HEADS

NUMBER OF PRE-COMP
CYLINDERS
RWC

WD BIOS 62-000042-12 (EPROM)
3

10MB

11

11

ST412
Seagate

4

306

0
None

2

20MB

o1

o1

ST225
Seagate

4

612

128
None

1

10MB

10

10

3012
MiniScribe

2

612

128
RWC= 128

0

20MB

00

00

HH725
Microscience

4

612

None
None

Factory sets jumper for BIOS Table 3. Position 5 of SW1 select IR05 (factory setting) or IR02. 1 = IR05. 0
= IR02. Positions 6, 7, and 8 of SW1 are reserved.
LEGEND: 1 = no jumper installed, ties input to

6-112

+ 5vdc.

0 = jumper installed, ties input to ground.

Winchester Board Products

J3

Jl

J2

SWl

U9

FIGURE 6. JUMPER LOCATIONS
7.3 BIOS ROM INSTALLATION

2764 JEDEC EPROM. Figure 7 illustrates the standard
connections for the 2732 or 2764. These connections
can be modified to support a 2716. Perform the following steps to modify the standard connections:

The WD1002S-WX2 firmware driver routines, supplied
by Western Digital Corporation, reside in a 4KB x 8
bit EPROM. This BIOS ROM is available in three sizes
as follows:

1.
2.
3.
4.

2716 2KB x 8 bit
2732 4KB x 8 bit (standard from the factory)
2764 8KB x 8 bit
The WD1002S-WX2 provides a 28 pin DIP socket for
the BIOS ROM. This socket accomodates a 2732 or

1
2

28
27

3
4

26
25

5

7

24
23
22

8
9

20

6

Cut the etch between pads 1 and 2 on W5
Jumper pad 3 to pad 2
Wire pin 20 and 26 as shown.
Plug BIOS in the socket. Pin 1 of the 2716 BIOS
should be in position 3 of the socket.

I-----Vee
E2(A11)

21
t----

VSS

0

E3 (Vee)

FIGURE 7. BIOS ROM SOCKET CONNECTIONS

Winchester Board Products

6-113

SPECIFICATIONS

=E
c-"
o
o

N

en

~

><

N

This section contains th.e overall specifications for
the WD1002S-WX2 Winchester Disk Controller.
ELECTRICAL
HOST INTERFACE

Type
Host Interface Connector

IBM PC
P1 connects directly to Host motherboard with a 62-pin card edge
connector

DRIVE INTERFACE

Encoding Method
Cylinders per Drive
Sectors per Track
Bytes per Sector
Heads
Drive Selects
Stepping Rates

Data Transfer Rate
Write Precomp Time
Sectoring
CRC Polynomial
ECC Polynomial
Reciprocal ECC Polynomial
Miscorrection Prob.
Non-detection Prob.
Correction Span
Max Cable Length:
Control (Total Daisy 3 Meters
(10 ft.) Chain)
Data (Radial-each)

MFM
Up to 1024
17
512
8 with WD1015-14
16 with WD1015-24
2
70 /-isec, 200 /-isec, 3 msec (WD1015-14)
18 /-isec, 30 /-isec, 45 /-isec, 60/-isec,
75 /-isec, 210 /-isec, 3 msec (WD1015-24)
5 Mbits/sec (ST506)
12 nsec
Soft
16
X
+ X 12 + x5 + 1
32
X
+ X 28 + X26 + x19 +
X 17 + X 10 + x6 + x2 + 1
x32 + x30 + x26 + x22 +
X 15 + X 13 + x6 + X4 + 1
5-bit correction = <1.6 E- 5
<2.3 E-10
Up to II-bit burst
3 Meters (10ft.)
3 Meters (10 f1.)

WD10C20

Acquisition Time
Capture Range
Bit Jitter Tolerance
Asymmetry Tolerance

< or = 12.8 /-is
± 2.2% to 1ns after 12.8 /-is acquisition
± -34ns (min. of 40 db after acquisition)
± -34ns (write precompensation turned off; as measured over constant RCLK pattern)

POWER

Voltage
Current
Ripple
Voltage
Current

6-114

5V ±5%
0.8 amps max.
0.1 volts max., 25 mV typical
+12 ± 10%
10 rnA. max.

Winchester Board Products

PHYSICAL

IBM
20.6
9.78
1.27

Form factor
Length
Width
Height (max including board,
components, & leads)

PC
centimeters (8.1 inches)
centimeters (3.85 inches)
centimeters (0.50 inches)

ENVIRONMENTAL

OOC (32°F) to 55°C (131°F)
10% to 95% non-condensing
o to 3000 meters (10,000 ft)
100 lin ft/min. at 0.5" from component surfaces.
10,000 POH
30 Minutes

Ambient Temperature
Relative Humidity
Altitude
Air Flow
MTBF
MTTR
INTERFACE TIMING

Timing diagrams are shown in Figures 8 through 11
and their values are listed in Tables 12 through 15
respectively. Since the Controller 1/0 ports can be
accessed by either the Host system DMA Controller
or the Host processor, timing is given for both cases.

The processor executes 1/0 and memory reads from
the ports and the on-board BIOS ROM, and writes to
the ports. The DMA is used for data transfers between
the data 1/0 port and the Host RAM.

:~~AO'-----<:~__________________A_OD_R_ES_S__WI_l_l_B_E_V_A_l_IO________________--J:><:~

______

I
I

lOR , MEMR - - - - - - -.....
I
I

~tASl ~I"
07 - DO

I

I"

<

tOE

(
tACC(BIOS)

~tDH1....J

"I
DATA MUST
BE VALID

~I

2

~

FIGURE 8. HOST 1/0 OR BIOS READ TIMING

TABLE 12. HOST 1/0 OR BIOS READ TIMING

UNITS IN NSEC.
SYMBOL

CHARACTERISTIC

MIN

MAX

t AS1

Address Setup Time

t ACC

Address Access Time

250

tOE

Output Enable Time

175

tOH1

Data Hold Time

Winchester Board Products

50

0

6-115

~

c
....
o

OACK3 ~~______________________________________________~

o

N

CJ)

:iE

ORQ3

><

I. ...I-----I·~I- tOORQ
~I____________~~

N

lOR

I
I

j...- t RSU - ·......1..------- tOOE

--.J

·1

j.- t OH3
y~--~~--~(--~)~~,

07 - 00

---------4-,-_- - - - - - - - - - <

DATA MUST BE VALID

~

~

--=

7

FIGURE 9. DMA I/O READ TIMING

TABLE 13. DMA I/O READ TIMING

UNITS IN NSEC.
SYMBOL

CHARACTERISTIC

MIN.

MAX.
45

tOORQ

DRQ3 De·assert Delay

20

t RSU

Read Setup Time

7

tOOE

Data Output Enable

t OH3

Data Hold Time

6-116

175

0

Winchester Board Products

__
------------

AA1E9N-AO,-<'-__________________________________________
-------JX~---~
ADDRESS WIll BE VALID
_ _

I. . .

tASU2-tjr--...t - - -...• ... - - - - - - t w P ---------I~~I
lOW

07 -

I

~I

I..
tosu ----I~~I. . .I---I~~I~ tOH2
OO----------~<

N

=E
c
......

o
o

OACK3

~~________________________________________________~

I- - t

N

en

:e><

ORQ3

: .,

tOORQ2

~I___~_________________~I

J.-twsu--t·~I......t-------- twp--------...~I

N

lOW

I

~I-----------

...I-..----tos
_14 t OH4 -.J
07 - 00-------------4~------FIGURE 11. DMA 1/0 WRITE TIMING

TABLE 15. DMA 1/0 WRITE TIMING

UNITS IN NSEC.
SYMBOL

CHARACTERISTIC

MIN.

MAX.

45

tDDRQ

DRQ3 De·assert Delay

20

t wsu

Write Setup Time

7

twp

Write Pulse Width

100

t DS

Data Setup Time

50

tDH4

Data Hold Time

0

6-118

Winchester Board Products

DIGITAL

WESTERN
COR

P

0

RAT

o

N

WD1002-WAH WINCHESTER DISK CONTROLLER
FEATURES

•

PC AT COMPATIBLE WINCHESTER
CONTROLLER

•

CONTROLS UP TO TWO WINCHESTER
DRIVES (16 RIW HEADS EACH)

•

HARDWARE DESIGN ALLOWS TWO
WD1002·WAH CONTROLLERS IN ONE
SYSTEM

•

8·BIT, BI·DIRECTIONAL BUS HOST
INTERFACE (FOR CONTROL AND
STATUS TRANSFERS)

•

16·BIT, HIGH·SPEED PIO DATA
TRANSFERS

•

32·BIT ECC FOR WINCHESTER ERROR
DETECTION AND CORRECTION

•

MULTIPLE SECTOR READIWRITE
COMMANDS (MAY CROSS HEAD AND
CYLINDER BOUNDARIES)

•

IMPLIED AND BUFFERED SEEK
COMMANDS

•

READIWRITE DIAGNOSTIC AND VERIFY
COMMANDS

•

PROGRAMMABLE FORMAT AND ERROR
RECOVERY ALGORITH MS

•

WD10C20 SINGLE CHIP DATA SEPARATOR

DESCRIPTION

The WD1002·WAH is an IBM PC AT bus compatible
Winchester controller board designed to interface up
to two drives. The drive interface is based upon the
Seagate Technology ST506. The drives need not be
of the same capacity or configuration. All necessary
receivers and drivers are included on the board to
allow direct connection to the drive(s).
ARCHITECTURE

The WD1002·WAH is based on the WD1014·01 Error
Detection/Support Logic device, WD1015-03 Buffer
Manager Control Processor, WD1010A-05 Winchester
Disk Controller, and WD10C20 Data Separator. The
WD1002·WAH also uses two 2K x 8 static RAM
memory devices as a Sector Buffer.
The WD1014·01 provides error correction for the
WD1002·WAH. The WD1014·01 generates four ECC
bytes and appends these bytes to the sector data
field. The maximum error correction span is 5·bits.
The WD1014·01 sets the error correction span. The
WD1014·01 also selects the proper drive and head.
The WD1015·03 is an 8·bit microprocessor that con·
trois and coordinates the activity of the disk drives,
WD1010A·05, and WD1014·01. The WD1015·03
receives and sends command or status information
over the internal WD1002·WAH mUltiplexed

Winchester Board Products

address/data bus, HDO through HD7. Controlling firm·
ware resides in the WD1015·03's 2K internal ROM.
The WD1010A·05 controls all data transfers between
the Sector Buffer and the drives. The WD1010A-05 per·
forms multiple sector ReadlWrite, Implied and Buf·
fered Seek commands. The WD1010A·05 also
executes programmable format and error recovery
algorithms. All commands are executed through the
seven Task Files of the WD1010A·05 after limited
intervention by the WD1015·03 and WD1014·01.
The WD1 OC20 performs phase·locked loop data syn·
chronization on read data from the Winchester drives.
This device also conditions write data to be recorded
on the disk. The WD10C20 includes both frequency
and phase detection. Zero phase error start·up cir·
cuitry eliminates problems due to asymmetry. The
WD10C20 requires no adjustments and contains all
data separation circuitry in a single device.
The Sector Buffer is two 2KB x 8 RAMs. Since the
WD1010A·05, WD1014·01, and WD1015·03 are 8·bit
devices, two RAMs are used because the Host pro·
vides data in 16·bit words. An onboard PAL selects
the proper RAM. The Sector Buffer RAMs never con·
tain more than 512 bytes.
Figure 1 is a block diagram of the WD1002·WAH.

6-119

..,Sf
I/QIUS

I---':""~!..!.~'----- } (0

FIGURE 1. WD1002-WAH BLOCK DIAGRAM

INTERFACE CONNECTORS

HOST INTERFACE CONNECTORS

The W01002-WAH has five interface connectors:

The W01002-WAH Controller interfaces with the
16-bit, bi-directional data bus by means of the two
card edge connectors P1 and P2. The pin descriptions
for P1 are given in Table 1 and for P2, in Table 2.

P1-62-pin card edge connector
Component side -Pins A1 through A31
Conductor side -Pins 81 through 831
P2-36-pin card edge connector
Component side -Pins C1 through C18
Conductor side -Pins 01 through 018
J1- control cable connector
J2- drive 0 data cable connector
J3- drive 1 data cable connector
The pin description of the connectors are given in
Tables 1 through 4.

6-120

Winchester Board Products

TABLE 1. HOST INTERFACE CONNECTOR (P1) PIN DESCRIPTION
PIN
NUMBER

MNEMONIC

SIGNAL NAME

110

FUNCTION

110

Bi-dlrectional, 8-bit data bus for data and status
communication between the controller and the
Host.

ADDRESS
ENABLE

I

When AEN is asserted, the DMA controller
assumes control of the Host address bus, control
bus, and data bus. 110 port addresses are no longer
generated for 110 port access.

SA9
thru
SAO

ADDRESS
BITS A9
thru AO

I

A 10-bit address bus for 110 addressing by the Host.

B1,B10
B31

GND

Ground

B2

RST

RESET

I

When asserted, RST forces the WD1002-WAH board
into the initial power-up state.

+5VDC

+5VDC

+5VDC

+ 12VDC

+ 12VDC

+ 12VDC

A1,A10,
A12
thru
A21

NC

A2
thru
A9

SD7
thru
SDO

DATA BIT 7
thru
DATA BIT 0

A11

AEN

A22
thru
A31

B3,B29
B9
B4
thru
B8,B11,
B12

NC

B13

lOW

110 WRITE

I

Assertion causes the WD1002·WAH to read a data,
status or control byte from the Host data bus.

B14

lOR

110 READ

I

Assertion causes the WD1002-WAH to drive data
unto the Host data bus.

B15
thru
B27,B30

NC

B28

ALE

ADDRESS
LATCH
ENABLE

I

Assertion enables the WD1002-WAH to latch a valid
board address from the Host address bus.

Winchester Board Products

6-121

TABLE 2. HOST INTERFACE CONNECTOR (P2) PIN DESCRIPTION
PIN
NUMBER

MNEMONIC

C1
thru
C10

NC

C11
thru
C18

D8
thru
DO

D1
D2

D3
thru
D6
D7
D8
thru
D18

1/0

FUNCTION

110

Bi-directional, 8-bit data bus for data tranfers only
between the controller and the Host.

110 16 BIT
CHIP
SELECT

I

Assertion signals the system board that the current data transfer is a 1 wait-state, 16-bit 110 cycle,
derived from an address decode.

INTERRUPT
REQUEST 14

0

Assertion indicates that the WD1002-WAH request
execution of the Host interrupt service routine.

SIGNAL NAME

DATA BIT 8
thru
DATA BIT 15

NC
1I0CS16

NC

IRQ14
NC

DRIVE CONTROL CONNECTOR J1

chain must have a 220/330 ohm resistor
pack installed. Pin descriptions and control signals
for the drive control connector J1 are given in Table 3.

The drive control connector is a 34-pin printed circuit
card edge connector daisy-chained to each drive in
the system. To terminate the control signals on the
WD1002-WAH properly, the last drive on the daisy

TABLE 3. DRIVE CONTROL CONNECTOR (J1) PIN DESCRIPTION
SIGNAL

1/0

FUNCTION

HEAD
SELECT 3
REDUCE
WRITE
CURRENT

0

HS2

HEAD
SELECT 2

0

6

WG

WRITE
GATE

0

The WD1002-WAH uses HS3 to select one of 16
R/W heads. RWC is not used with 16 head drives.
RWC is used by drives with 8 R/W heads. RWC
reduces the write current on the inner cylinders.
This lessens the bit shift caused by greater density on these cylinders.
HS2 is one of the head select signals decoded
by the drive to select one of eight (or 16) R/W heads.
WG is asserted when valid data is to be written
on disk. The WD1002-WAH de-asserts WG when
WF is detected. Special circuitry is included to
ensure the system output is free of glitches during power-on.

8

SC

SEEK
COMPLETE

GND.

PIN

1

2

HS3/RWC

3

4

5

7

6-122

MNEMONIC

NAME

I

SC informs the WD1002-WAH that the head of a
selected drive has reached the desired cylinder and
has stabilized.

Winchester Board Products

TABLE 3. DRIVE CONTROL CONNECTOR (J1) PIN DESCRIPTION (cont'd)
SIGNAL
GND.

PIN

9

10

TKooo

TRACK 000

11

12

WF

WRITE
FAULT

13

14

15

MNEMONIC

HSO

NAME

110

FUNCTION
TKOOO is asserted when the R/W heads are posi·
tioned over the outermost cylinder.
WF is asserted by the selected drive when a write
error occurs. While this signal is being asserted,
the command in progress aborts and no other disk
command can be executed.

HEAD
SELECT 0

0

HSO is one of the head select signals decoded by
the drive to select one of eight (or 16) R/W heads.

GND
16

NC

17

18

HS1

HEAD
SELECT 1

0

HS1 is one of the head select signals decoded by
the drive to select one of eight (or 16) R/W heads.

19

20

INDEX

INDEX
PULSE

I

INDEX indicates the start of a track. Used as a
synchronization point during formatting and as a
time-out mechanism for retries. Pulses once each
disk revolution.

21

22

DRDY

DRIVE READY

I

DRDY informs the controller that the drive motor
is up to speed.

23

24

STEP

STEP PULSE

0

STEP, with DIRIN..L...E2.sitions the heads to the
desired cylinder. STEP pulses once for each step.
DIRIN determines the step direction.

25

26

DSO

DRIVE
SELECT 0

0

DSO is used to select drive O.

27

28

DS1

DRIVE
SELECT 1

0

DS1 is used to select drive 1.

DIRECTION
IN

0

DIRIN determines the direction in which the R/W
heads move when the step line is pulsed. Deasserted
out; asserted
in.

GND

29,
31,

33
30,
32

33

34

NC
-DIRIN

Winchester Board Products

=

=

6-123

DATA CONNECTORS

The data lines between the WD1002-WAH and the two
disk drives are connected to J2 and J3. As the data
lines are not identical, J2 must be connected to the
cable from drive 0, and J3 to the cable from drive 1.
Each drive is radially connected with a maximum

cable length of 3 meters (10 feet). Each data connector is a 20-pin vertical header on 0.25mm (0.01 inch)
center. Data connector pin descriptions and signals
are listed in Table 4.

TABLE 4. DRIVE DATA CONNECTORS (J2,J3) PIN DESCRIPTION
SIGNAL
GND

PIN

110

1

NC
GND
NC
GND
NC
GND

2
3
4
5
6
7

NC

8
9
10
11
12
13
14
15
16

17
18
19
20

6-124

SIGNAL NAME

0
0

GND
NC
NC
GND
GND
+ MFM Write Data
-M FM Write Data
GND
GND
+ M FM Read Data
-M FM Read Data
GND
GND

Winchester Board Products

FORMAT

The format used for Winchester disk track formatting
is shown in Figure 2. The ID and data fields on any
disk are initialized by the Format command.
REPEATED fDR EACH SECTOR

IN~

.----DATA fiElD

ID f I£LD

It

I
\
GAPI

} GAP4
4E

4[

14 BYTES
'00'

A
1

1

I
D
E
N
T

C L
y 0
L W

H
E
A
D

S
[

C

•

C
R
C
1

C
R
C
?

) BYTES
'00'

I
I

WRITE qAT[

I

I

I
DRUN

--.J

12 BYTES
'(\()'

A
1

f
B

USER DATA

GAP)
4£
1

) BYTES
'00'

4ECC

I

I

I

.j!

I

L

I I
I I

I
I

I

I

I
I

I
I

I
I
f

~
I
L_______

I

I

I

R[AD GAT[

6

I

'-1 _ _ __

ID FIELD

NOTES

1. GAP 1 and 3 length equals 22 bytes.
2, Decision to assert RG is made two bytes after the
start of DRUN,
3. RG is de·asserted:
• If DRUN does not last until A 1,
• When any part of the ID does not match
the one that is expected,
• After CRC, if correct ID has been read.
4. Write splice recorded on disk by asserting WG,
5. RG is suppressed until after write splice.
6. Not a proper A1 or F8, set DAM error.
7, Sector size as stated in ID field, plus four for ECC.

A1 = A1 hex with OA hex clock
IDENT = Bits 1,0 = Cylinder High
FE
FF
FC
FD

=
=
=
=

0-255 Cylinders
256·511 Cylinders
512-767 Cylinders
768-1023 Cylinders

HEAD = Bits 0, 1,2 = Head Number
Bits 3,4 = 0
Bits 5, 6 = Sector Size
Bit 7 = Bad Block Mark
Sec # = Logical Sector Number
DATA FIELD

A 1 = A1 hex with 01 hex clock
F8 = Data Address Mark; Normal Clock
USER = Data Field 512 Bytes
FIGURE 2. WINCHESTER DISK FORMAT

Winchester Board Products

6-125

REGISTER ADDRESS MAP
The WD1002-WAH contains seven Read/Write task file
registers in the WD1010A-05 and three hardware
registers external to the WD1010A-05. These registers
are mapped into either a primary of secondary 1/0
address. All data, control, and status information pass
between the task files and the Host.
All data transfers are word transfers except ECC
bytes in Read Longs and Write Longs. These ECC
bytes are transferred in byte-mode. Control and status bytes are also transferred between the Host in
byte mode. The? task file registers are multiplexed
with lOR and lOW to give 14 possible parts. Five of
the eight task file registers are bi-directional. Two of
the task file registers have different definitions for
read and write operation. Jumpers select the primary and secondary address. This allows two controllers in the same Host system. However, secondary ports on the WD1002-WAH are not supported by
any version of DOS.
Table 5 summarizes the WD1002-WAH 1/0 port
address map. Figure 3 summarizes the WD1010A-05
task file registers and bit aSSignments. Figure 4 summarizes the other three 1/0 registers and bit
assignments for the WD1002-WAH. Bit assignments

are with respect to the Host lower byte bus terms,
SO? through SDO. The fixed sizeldrivelhead (SOH) and
status registers in the WD1010A-05 desciptions
slightly differ from the standard descriptions in the
WD1010-05 data sheet. Please note that the SOH
register is set for the ECC option mode and 512 bytes
per track. The SOH register also limits the number
of heads to 16. Bit 2 of the WD1010A-05 status register
is designated as the Corrected Data bit. Assertion
(setting to 1) of this bit indicates the sector read from
the drive resulted in a correctable ECC error. Soft
errors do not end multiple sector transfers. Bit 1 of
the WD1010A-05 status register is designated as the
Index bit. Assertion of this bit occurs each revolution
of the currently selected drive. Refer to the WD1010-05
data sheet for a complete description of all other
WD1010A-05 bit aSSignments. Table 6 describes the
bit assignments for the other WD1002-WAH control
and status registers.
NOTE
Where differences exist, the values and descriptions
for Figure 3 take precedence over the WD1010-05 data
sheet.

TABLE 5. WD1002-WAH REGISTER ADDRESS MAP
1/0 ADDRESS

PRIMARY

SECONDARY

READ

WRITE

WD1010A-OS TASK FILE REGISTERS
1F1
1F2
1F3
1F4

171
172
173
174

1F5

175

1F6
1F7

176
177

ERROR REGISTER
SECTOR COUNT
SECTOR NUMBER
CYLINDER NUMBER
(low byte)
CYLINDER NUMBER
(high byte)
SOH REGISTER
STATUS REGISTER

WRITE PRE-COMP
SECTOR COUNT
SECTOR NUMBER
CYLINDER NUMBER
(low byte)
CYLINDER NUMBER
(high byte)
SOH REGISTER
COMMAND REGISTER

CONTROL AND STATUS REGISTERS EXTERNAL TO THE WD1 01 OA-OS

6-126

1FO

170

3F6
3F6

376
376

3F7

377

DATA REGISTER
(16 bits)

DATA REGISTER
(16 bits)
FIXED DISK REGISTER

ALTERNATE STATUS
REGISTER
DIGITAL INPUT
REGISTER

Winchester Board Products

REGISTER

7

I

6

WRITE PRE-COMP

I

I

5

4

I

3

I

2

I

1

I

0

TK

I

OM

CYLINDER NUMBER DIVIDED BY 4
BB

ERROR

I

ECC

I

0

SECTOR COUNT

I

10

I

0

I

AC
NUMBER OF SECTORS

SECTOR NUMBER

I

SECTOR NUMBER

CYLINDER NO.

CYLINDER NUMBER (LOW BYTE)

CYLINDER NO.

0

SOH

1

I

I

0
0

I
I

0

I

1

1

COMMAND

0

os

I

0

I

0

I HS3 I HS2

I CYL. NO. MSB
I HS1 I HSO

COMMAND

STATUS

BSY

I ROY I

WF

I

SC

I ORO I CRD I

lOX

I ERR

FIGURE 3. WD1 01 OA-05 TASK FILE REGISTER BIT ASSIGNMENT

7

REGISTER

6

5

4

3

2

1

0

BSY

ROY

WF

SC

ORO

CRD

lOX

ERR

DIGITAL INPUT

X

WTG

HS3/
RWC

HS2

HS1

HSO

DS2

DS1

FIXED DISK

0

0

0

0

HS3EN

RST

lEN

0

ALTERNATE STATUS

FIGURE 4. WD1002-WAH CONTROL AND STATUS REGISTERS

TABLE 6. WD1002-WAH CONTROL AND STATUS REGISTER BIT DEFINITIONS
REGISTER

ALTERNATE STATUS

DIGITAL INPUT

FIXED DISK

BIT MNEMONIC

BSY
RDY
WFT
SKC
DRO
CRD
IDX
ERR
X
WTG
HS3 (RWC)
throu9h..tiSO
DS2, DS1
HS3EN
RST

lEN

Winchester Board Products

BIT NAME

Controller Busy Flag
Ready from selected drive
Write Fault from selected drive
Seek Complete from selected drive
Data Transfer Request Flag
Corrected Data Flag from WD1015-03
Index pulse from selected drive
Error Flag from WD1015-03
Reserved. System bus signal SD07 tri-stated
Write Gate on
Drive head select or RWC (bit 5) for drives using
RWC
Drive select
Set to 1: Enables HS3
Set to 0: Enables RWC
Reset. Program controlled reset to board. This bit
maintains the WD1002-WAH logic reset as long as this
is on. This bit must be on for a .minimum of 5.0 Ilsec.
After the bit is on for the minimum time, the bit must
be turned off to complete reset function.
Interrupt Enable. Enables or disables IRQ14. This bit
does not clear the interrupt level in the disabled state.
A pending interrupt would occur when the interrupt is
enabled again. A system master reset clears the interrupt but leaves the interrupt enabled.

6-127

COMMANDS

The WD1002·WAH command set contains eight com·
mands. Five commands (Restore, Seek, Read Sector,
Write Sector, and Format Track) are executed through
the WD1010A·05 command register. (A sixth
WD1010A·05 command, Scan ID is not directly
available to the Host. Scan ID may be executed by
the WD1015·03 transparently to the Host.) The three
remaining commands (Read Verify, Diagnose, and Set
Parameters) are executed through the WD1015·03.

Table 7 describes the eight WD1002·WAH commands
and their bit assignments. The next section describes
a typical command sequence. Each command is
described following the command sequence.

TABLE 7. COMMANDS AND COMMAND CODES
COMMAND

BITS

Restore

0

Seek

0

1

Read Sector

0

0

Write Sector

0

0

Format Track

0

1

Read Verify

0

1

0

0

Diagnose

1

0

0

1

0

Set Parameters

1

0

0

1

0

0

1

R3

R2

R1

RO

1

1

R3

R2

R1

RO

1

0

0

0

L

T

1

1

0

0

L

T

0

1

0

0

0

0

0

0

0

T

0

0

0

0

0

1

0

LEGEND

R3 through RO

Step rate selection bits. Refer to
Table 8 for more detailed
information.

L

Read or Write Long bit. Set to 1
enables Read or Write Long
mode.

T

Retry bit. Set to 1 disables retries.

The stepping rates for the commands that perform
implied seeks are set in the least significant nibble
of the last executed RESTORE or SEEK command.
The stepping rate is given in Table 8.

6-128

Winchester Board Products

TABLE 8. STEPPING RATE

R3

R2

R1

RO

STEPPING
RATE

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0

0
1
0
1
0
1
0
1

35
0.5
1.0
1.5
2.0
2.5
3.0
3.5

1
1

jJsec
msec
msec
msec
msec
msec
msec
msec

R3

R2

R1

RO

1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
1

STEPPING
RATE
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5

msec
msec
msec
msec
msec
msec
msec
msec

Note: After Diagnose or reset, stepping rate defaults to 7.5 msec

COMMAND SEQUENCE DESCRIPTION
This section describes a typical command execution
sequence. This description illustrates the relationship
beween Host and the major components of the
WD1002·WAH during command execution.
In the idle state: the WD1010A·05 drive control
signals are off. The controller status indicates
ready. Drive status is valid. Controller interrupt is
enabled but not asserted. The WD1015-03 is idle
and is monitoring the WAKEUP signal input.
The Host outputs the command parameters to the
WD1010A-05 task file, the operation command
(Seek, Read or Write) and the command attributes
(Long mode, retry control, etc.). For write operations, the Host also outputs the sector or format
data.
The command byte is intercepted by the
WD1014-01 and is held for later interpretation by
~he WD1015-03.
A Read command output sets the module Wakeup
latch that causes the controller status to indicate
Busy and the WD1015-03 WAKEUP signal to be
asserted. Write and Format commands first set
the data request status signal DRO. This initiates
the Host data transfer. Completion of the data
transfer (512 or 516 bytes) sets the WD1015-03
WAKEUP signal and Busy status.
The WD1015-03 examines the command, verifies
command parameters, and passes the command
to the WD1010A-05 for execution.
The WD1010A-05 executes the command providing
drive positioning, data transfer control, error

Winchester Board Products

monitoring and completion status. The WD10C20
provides drive read and write data control for commands that require data transfers.
On command completion, the WD1010A-05 interrupts the WD1015-03. The WD1015-03 examines
the command, status, etc. for any additional
requirements. If completion is indicated, the
WD1015-03 sets the controller status to indicate
ready and interrupts the Host.
The WD1002-WAH returns to the idle state and the
Host may examine drive and controller status, read
input data, etc., as required to complete the
operation.
COMMAND DESCRIPTION
Restore
The Restore command is used to move the RIW
heads to the Track 000 position. The controller issues
step pulses to the drive until the Track 000 indicator
from the drive is asserted. If Track 000 is not asserted
within 1023 steps, the Error bit in the Status Register
is set and a Track 000 error is posted in the Error
Register. The implied seek step rate may be set up
according to Table 8 by the Restore command. The
restore step rate is established by the seek complete
signal from the drive, i.e., each step pulse is issued
only after seek complete is asserted by the drive from
the previous step. If the DRIVE READY signal is
de-asserted or WRITE FAULT is asserted, this command terminates with the error bit set in the status
register and the error register reports an aborted
command.

6-129

Seek

This command moves the RJW heads to the cylinder
specified in the task file cylinder specified in the task
file cylinder high and low registers. The implied seek
step rate is also set by this command. The lower order
four bits of the command are used to select one of
16 available step rates. An interrupt is generated at
the completion of the command. If the DRIVE READY
signal is de-asserted or WRITE FAULT is asserted,
this command is terminated with the error bit set in
the status register and the error register reports an
aborted command.
Read Sector
A number of sectors (1 - 256) can be read from the
selected drive with this command. The sector count
register in the task file determines the number of sectors to be transferred. Multiple sector reads may cross
head and cylinder boundaries.

If the Read command is issued prior to initializing a
step rate, the default value of 7.5 msec is selected
and a Recalibrate is performed prior to the Read.
If the RIW heads are not positioned over the target
track, the controller performs an implied seek to the
proper cylinder. The stepping rate used during the
implied seek is the value specified during the previous
Seek or Restore command.
The optional long bit (L set to 1 enables Read Long.)
informs the WD1002-WAH whether or not to include
the four EGG bytes. These four EGG bytes are
transferred as individual bytes, not words, as is the
data field information. The data request bit in the
status register must be valid before each byte
transferred and at least 2 ,.,.sec will pass between each
byte transferred.
Data errors up to 5 bits in length will be automatically
corrected on normal Read commands. If an uncorrectable error occurs, the data transfer will still take
place, a mUlti- sector read, however, will terminate
after the sector in error is read by the system.
The optional retry bit (T set to 1 disables retries.)
disables or enables retries. The WD1010A-05
automatically retries for ten disk revolutions when the
retry bit is enabled. The WD1010A-05 properly sets the
error and status registers if the retries are unsuccessful. Disabling retries allows only two disk revolutions before the WD1010A-05 sets the error and status
registers.
For EGC errors, eight retries are made at reading
before a soft uncorrectable error is reported. A retry
results in the reissuing of the WD1010A-05 Read Sector command. The WD1010A-05 Read Sector command attempts to verify the sector ten times, if T is
set to 1, before returning an error. ECG correctable

6-130

data errors are corrected after two consecutive matching EGG syndromes are detected. If the error is an
uncorrectable error or an error is reported by the
WD1010A-05, the command terminates.
Interrupts occur as each sector is ready to be read
by the system. No interrupt is generated at the end
of the command. If the DRIVE READY signal is deasserted or WRITE FAULT asserted, this command
terminates with the error bi't set in the status register
and the error register reports an aborted command.
Write Sector

A number of sectors (1 - 256) can be written to the
selected drive. The sector count register in the task
file determines the number of sectors to be transferred. Multiple sector writes may cross head and
cylinder boundaries.
If the Write command is issued prior to initializing a
step rate, the default value of 7.5 msec is selected
and a Recalibrate is performed prior to the Write.
If the heads are not positioned at the cylinder
specified in the cylinder high and low registers, the
controller performs an implied seek. The step rate
used is determined by the step rate field of the most
recently executed Restore or Seek command.
The optional long bit (L set to 1 enables Write Long.)
informs the WD1002-WAH whether or not to append
the Host supplied EGG bytes. These four bytes are
transferred as individual bytes, not words, as is data
field information. The data request bit in the status
register must be valid before each byte transferred
and at least 2 ,.,.sec will pass between each byte
transferred.
The optional retry bit (Tset to 1 disables retries.)
disables or enables retries. The WD1010A-05
automatically retries for ten disk revolutions when the
retry bit is enabled. The WD1010A-05 properly sets the
error and status registers if the retries are unsuccessful. Disabling retries allows only two disk revolutions before the WD1010A-05 sets the error and status
registers.
The WD1002-WAH interrupt is generated as the data
for each sector is required to be transferred into the
Sector Buffer (except the first sector) and at the end
of the command. The first sector may be written to
the buffer immediately after the command has been
sent, and the data request status is set. If the DRIVE
READY signal is de-asserted or WRITE FAULT is
asserted, this command terminates with the error bit
set in the status register and the error register reports
an aborted command.

Winchester Board Products

Format Track

The track specified by the task file is formatted with
ID and data fields according to the interleave table
transferred to the buffer. The interleave table, consists
of two bytes per sector as follows:
00 PHYSICAL SECTOR 1
00 PHYSICAL SECTOR 2
00 PHYSICAL SECTOR 3

00 PHYSICAL SECTOR 17
The data transfer must be 512 bytes even though the
table may be only 34 bytes. The sector count register
must be loaded with the number of sectors per track
before each Format Track command. The Format
Track command supports on error reporting. A bad
block may be specified by replacing a 00 table entry
with and 80 Hex. When switching between drives, a
Restore command must be executed prior to attempting a format. Command completion will leave all data
fields initialized to zeroes. The completion interrupt
is generated after each track has been formatted.
Read Verify

This command funtions similarly to a normal Read
command except that data is not output to the Host.
One of 256 sectors may be verified at one time. The
generated ECC bytes are compared with the recorded
ECC bytes for data verification. A single interrupt is
generated upon completion of the command or in the
event of an error.
If the Read Verify command is issued prior to initializing a step rate, the default value of 7.5 msec is
selected and a recalibrate is performed prior to the
Read Verify.
For ECC errors, eight retries are made at reading
before a soft uncorrectable error is reported.
A retry results in the reissuing of the WD1010A-05
Read Sector command. The WD1010A·05 Read Sector command attempts to verify the sector ten times,
if T is set to 1, before returning an error. ECC correctable data errors are corrected after two consecutive
matching ECC syndromes are detected. If the error
is an uncorrectable error or an error is reported by
the WD1010A-05, the command terminates. The
WRITE FAULT and DRIVE READY inputs are checked throughout the command's execution.
Diagnose

The Diagnose command causes the Controller to perform an onboard diagnostic and to report the result
in the Error Register. An interrupt is performed upon
completion of the command.

Winchester Board Products

The Diagnose command performs tests on the
WD1015-03's internal ROM and RAM, the WD1014-01,
WD1010A-05, and the Sector Buffer. If any component
fails, the appropriate error code is loaded into the error
register. Error codes are as follows:
01
02
03
04
05

No errors
WD1010A-05 register access error
Sector Buffer RAM data error
WD1014-01 register access error
WD1015-03 ROM checksum or
RAM data error
00,06-FF Not used. Undefined.
In addition, the Diagnose command sets the write precomp task file register to 32. This causes write precompensation to begin at cylinder 128. (Since the
write pre-comp register holds the desired value
divided by four.) The sector count register is reset to
one while the cylinder high, cylinder low, and SDH
registers are all set to zero.
Set Parameters

This command sets up the drive parameters regarding the maximum number of heads and sectors per
track. The WD1002- WAH uses these two paramenters
when performing multiple sector operations. The SDH
task file register specifies the drive affected. The sector count and SDH registers must be set up before
this command is issued. An interrupt is set at the
completion of the command_
This command must be issued before any multiple
sector operations are undertaken. By setting the SDH
register for each of the two possible drives, this command allows the WD1002-WAH to support two drives
with different characteristics.
JUMPER OPTIONS

The WD1002-WAH does not provide configuration
switches for drive parameters, interrupt selection, or
drive selection. The attached drive or drives must be
configured for drive select 1 or 2. The available jumper
options are as follows:
W 1: Primary and secondary 1/0 address jumper
allows two controllers in one chassis.
Jumpering positions 1-2 selects base
primary address 1FO. Jumpering positions
2-3 selects base secondary address 170.
W 2:

=

LATCHED status register jumper. L
latched. In this mode, the WD1002-WAH
diagnostics registers located at I/O address
BASE + 7, 3F6 Hex, and 3F7 Hex present
latched status to the Host. This mode is
IBM PC AT compatible. Drive select line is
semi-static.

6-131

NON-LATCHED NL = non-latched. This has
centain timing implications for the disk drives.
DRIVE SELECT low to status valid is 355 nsec as
measured at the drive interface. The drive select

lines are activated only when the controller is
executing a command, or reading status at 3F6
or 3F7 Hex.
Figure 5 illustrates the location of W1 and W2.

W2

J2

J1

c=J

o

Pl

Wl

FIGURE 5. WD1002-WAH JUMPER LOCATIONS

6-132

Winchester Board Products

SPECIFICATIONS
PHYSICAL
Form factor
Length
Width
Height (maximum including
board, components, and leads)

IBM
20.6
10.7
1.27

PC
centimeters (8.1 inches)
centimeters (4.2 inches)
centimeters (0.05 inches)

POWER AND ENVIRONMENT
Power
+5V ± 5%
+12V ± 10%

Current
1.5A
0.5mA

ENVIRONMENTAL
Temperature
Operating
Non-operating
Humidity
Operating
Non-operati ng
Shock and Vibration
Shock
Vibration
Altitude
Operating
Non-operating

OOC (32°F) to 55°C (131°F)
-40°C (-40°F) to 60°C (140°F)
8% to 85% non-condensing
5% to 95% non-condensing
35G/20MS square wave maximum
1G/0-600 Hz, dwell not to exceed 30 seconds at any resonance

o to 3000
o to 5000

meters maximum (10,000 Ft)
meters maximum (15,000 Ft)

RECORDING SPECIFICATIONS
Encoding method
Data rate
Sector format

Interleave
Drives supported
Heads supported
Tracks supported
Hard error rate
Soft error rate
Seek error rate

MFM
5.0Mbs
512 bytes/sector
17 sectors/track (sectors number 01 through 17)
track soft sectored format
2:1
2 maximum
16 maximum
1024 maximum
less than 1 per 10(E12) bits read
less than 1 per 10(E10) bits read
less than 1 per 10(E06) seeks

READIWRITE CONTROL SPECIFICATIONS
Maximum acquisition time
Capture range
Drive Margin
Asymmetry tolerance

Winchester Board Products

12.8 us @ 5.0Mbs
2.2%
± 16 ns (with pre-comp off)
30nsec

>±

6-133

ERROR CORRECTION SPECIFICATIONS

Method
Degree
Forward polynomial
Reciprocal polynomial
Record length (r)
Correction span (b)
Single burst detection span
with b = 0
with b == 5
Single burst detection span
with b = 0
with b = 5
Non-detection probability
Miscorrection probability

Polynomial division
32

X32 + X28 + X26 + X19 +
X17 +X10 +X06+X02 + 1
X32 + X30 + X26 + X22 +
X15 + X13+ X06+ X04 + 1
516 by 8 bits maximum
5 bits
r = 516 by 8 bits
32 bits
19 bits
r = 516 by 8 bits
> 3 bits
3 bits
2.3 (E-10), r
516 by 8, b
5
1.57 (E-5), r = 516 by 8, b = 5

=

=

TIMING

Timing diagrams are shown in Figures 6 through
8, and the timing values are given in Table 9.
·1

FAST I/O 16

SA1-SA9

SAO

FIGURE 6. 110 CHANNEL TIMING

6-134

Winchester Board Products

SoOO-SD15
(DATA REGISTER)

=E

C
......

DATA VALID
READ
DATA

SOD-SOl

DATA VALID
WRITE

DATA
DATA VALID

SOD-SOl

FIGURE 8. DATA REGISTER WRITE DATA I/O TIMING
TABLE 9. TIMING
I/O
DEFINITION

8 BIT

16 BIT

SA1-SA9·> Fast I/O 16

93 nsec max

N/A

SAO .> Fast I/O 16

73 nsec max

N/A
97 nsec min

SA1-SA9·> lOR/lOW

97 nsec min

SAO·> lOR/lOW

77 nsec min

77 nsec min

lOR/lOW Pulse Width

167 nsec min

542 nsec min

lOR/lOW·> Fast I/O 16

93 nsec max

N/A

lOR .> Data Valid

132 nsec max

498 nsec max

Data Valid .> I/OW

71 nsec min

491 nsec min

Data Hold from lOW

54 nsec min

46 nsec min

Addr Hold from lOR/lOR

47 nsec min

47 nsec min

lOR/lOW·> lOR/lOW

375 nsec min

375 nsec min

Winchester Board Products

N

;1E

»
:I:

DATA VALID

FIGURE 7. DATA REGISTER READ DATA I/O TIMING

SOOO-So15
(DATA REGISTER)

0
0

6-135

6-136

Winchester Board Products

WESTERN
C

0

R

P

0

DIGITAL

RAT

o

N

WD1002-WA2 Winchester/Floppy Disk Controller
FEATURES

•

AT COMPATIBLE WINCHESTER AND FLOPPY
CONTROLLER

•

CONTROLS UP TO TWO WINCHESTER DRIVES
(ST506/ST412, 16 RIW HEADS EACH)

•

CONTROLS UP TO TWO FLOPPY DISK DRIVES
DOUBLE-SIDED
DOUBLE DENSITY (360kB, 250kbs, MFM)
QUAD DENSITY (1.2MB, 500kbs, MFM)
FOUR DATA RATES (500kbs, 300kbs, 250kbs,
and 125kbs)
SUPPORTS 360 AND 300 RPM SPINDLE
SPEEDS

•

BASED ON INDUSTRY STANDARD WD1010A·05
WINCHESTER DISK CONTROLLER

•

8-BIT, BI·DIRECTIONAL BUS HOST INTERFACE
FOR CONTROL AND STATUS TRANSFERS

•

HIGH·SPEED, 16-BIT PIO DATA TRANSFERS

•

32·BIT ECC FOR WINCHESTER ERROR DETEC·
TION AND CORRECTION, CRC FOR 10 FIELDS

•

DIAGNOSTIC MODE FOR ERROR CHECKING

•

WRITE PRECOMPENSATION LOGIC

•

SINGLE CHIP WINCHESTER DATA SEPARATOR
(WD10C20)

•

ALLOWS CONCURRENT OPERATION OF ONE
FLOPPY AND ONE WINCHESTER DRIVE

DESCRIPTION

The WD1002·WA2 is an AT bus compatible Win·
chester/Floppy disk controller designed to interface
up to two Winchester and up to two floppy disk drives.
The board permits the concurrent operation of one
floppy and one fixed disk drive. The Winchester drive
interface is compatible to the Seagate Technology
ST506 standard interface for 5Mbs hard disk drives.
The floppy disk drive interface supports 1.2MB, 360
RPM drives as well as 360kB (SA450) drives. The
WD1002·WA2 includes all necessary receivers and
drivers to allow direct connection to the drive(s).
ARCHITECTURE

The WD1002·WA2 is based on the WD1014·01 Error
Detection/Support Logic device, WD1015·03 Buffer
Manager Control Processor, WD1010A-05 Winchester
Disk Controller, WD2293·07 Floppy Data Separator

Winchester Board Products

Control Device, WD2293-08 Floppy Clock and Support
Device, and WD10C20 Winchester Data Separator and
Write Precompensation Device. The WD1002·WA2
also uses two 2K x 8 static RAM devices as a 16·bit
wide Sector Buffer, an analog data separator with
dual VCOs for four floppy data rates, and an N EC
/JPD765A Floppy Disk Controller.
The WD1014-01 provides error correction for the
WD1002·WA2's Winchester control circuitry. The
WD1014·01 generates four ECC bytes and appends
these bytes to the sector data field. The maximum
error correction span is 5·bits. The WD1014·01 also
selects the proper drive and head.
The WD1015·03 is an 8 bit microprocessor that con·
trois and coordinates the activity of the Winchester
disk drives, WD1010A·05, and WD1014·01. The
WD1015·03 receives and sends commands or status
information over the internal WD1002·WA2
multiplexed address/data bus, HDO through HD7.
Controlling firmware resides in the WD1015·03's 2K
internal ROM.
The WD1010A·05 controls all data transfers between
the Sector Buffer and the drives. The WD1010A-05 per·
forms multiple sector Read/Write, Implied and Buf·
fered Seek commands. The WD1010A·05 also
executes programmable format and error recovery
algorithms. All Winchester commands are executed
through the seven Task Files of the WD1010A-05 after
limited intervention by the WD1015-03 and WD1014-01.
The Sector Buffer is two 2KB x 8 RAMS. Since the
WD1010A·05, WD1014·01, and WD1015·03 are 8-bit
devices, two RAMs are used because the Host provides data in 16-bit words. An on board PAL selects
the proper RAM. The Sector Buffer RAMs never con·
tain more than 512 bytes.
The WD10C20 performs phase·locked loop data synchronization on read data from the Winchester drives.
This device also conditions write data to be recorded
on the disk. The WD10C20 includes both frequency
and phase detection. Zero phase error start·up circuitry eliminates problems due to asymmetry. The
WD10C20 requires no adjustments and contains all
data separation circuitry in a single device.
The NEC /JPD765A is a floppy disk controller. Host
control over the NEC /JPD765A is complete. No on·
board processor controls the floppy controller. Floppy
transfers are made in DMA mode. All floppy com·
mands are supported.

6-137

NOTE
Refer to the NEC Microcomputer Division Catalog for
more detailed information on this device. Where dif·
ferences exist, the values and descriptions in this data
sheet take precedence over the NEC documentation.
For example, the sector size is set at 512 bytes per
sector by the AT BIOS even though the NEC controller
allows programmable sector sizes.
The WD2293-07 enables the analog floppy data
separator to switch to one of four possible data rates.
System Data Bits 0 and 1 select the floppy data
transfer rate. The WD2293-07 also controls the data
separator phase locked loop (PLL) and voltage con·
trolled oscillator (VCO).

The analog data separator for the floppy disk con·
troller consists of a phase detector, amplifier gain
control, a bandpass filter and dual VCOs. Detection
of phase error between read data and VCO input is
provided by the phase detector. Amplifier gain con·
trol throttles the speed of the VCO i.e., increases the
VCO speed if VCO lags the data and decreases the
VCO speed if VCO leads the data. The bandpass filter
adjusts the bandwidth of the data's frequency. Dual
VCOs are used for different data rates.
Figure 1 is a functional block diagram of the
WD1002-WA2 board.

The WD2293-0B controls timing of the data rate and
floppy DMA requests. Write precompensation is also
provided by the WD2293-0B. Write precompensation
time for floppy data transfers is 125 nsec.

COIITROl BUS

FIGURE 1. WD1002·WA2 BLOCK DIAGRAM

6-138

Winchester Board Products

INTERFACE CONNECTORS
The pin descriptions of the connectors are given in
Tables 1 through 5.

The WD1002-WA2 has seven interface connectors:
P1 - 62-pin card edge connector
Component side - Pins A1 through A31
Conductor side - Pins B1 through B31

HOST INTERFACE CONNECTORS
The WD1002-WA2 Controller interfaces with the 16-bit,
bi-directional data bus by means of the two card edge
connectors P1 and P1'. The pin descriptions for P1
are given in Table 1 and P1', in Table 2.

P1' - 36-pin card edge connector
Component side - Pins C1 through C18
Conductor side - Pins D1 through D18

J 5 - Winchester control cable connector

J 4 - Winchester drive 1 data cable connector
J 3 - Winchester drive 2 data cable connector

J 1 - Floppy control and data cable connector
(daisy-chai ned)

J 6 - LED Winchester drive connector

TABLE 1. HOST INTERFACE CONNECTOR (P1) PIN DESCRIPTION
PIN
NUMBER

MNEMONIC

SIGNAL NAME

110

FUNCTION

A1,A10,
A12
thru
A21

NC

A2
thru
A9

SD7
thru
SDO

DATA BUS
BITS 7
THRU 0

1/0

Bi-directional, lower 8-bit data bus for data and
status communication between the controller and
the Host.

All

AEN

ADDRESS
ENABLE

I

When AEN is asserted, the DMA controller
assumes control of the Host address bus, control
bus, and data bus. 1/0 port addresses are no longer
generated for 1/0 port access. In this mode, the 1/0
port is selected by asserting DACK2.

A22
thru
A31

A9
thru
AO

ADDRESS BUS
BITS 9 thru
0

I

A 10-bit address bus for 1/0 port addressing by the
Host.

B1,B10
B31

GND

GROUND

B2

RST

RESET

I

When asserted, RST forces the WD1002-WA2 board
into the initial power-up state.

B3,B29

+5VDC

+5VDC

+5VDC

B6

DRQ2

DMA REQUEST
CHANNEL 2

DRQ2 is asserted whenever data are available for
transfer to or from the WD1002-WA2 under DMA
control. Applies to floppy controller only.

B7

-12VDC

-12VDC

-12VDC

B9

+ 12VDC

+ 12VDC

+ 12VDC

Winchester Board Products

6-:139

TABLE 1. HOST INTERFACE CONNECTOR (P1) PIN DESCRIPTION (CONT'D)
PIN
NUMBER

MNEMONIC

84,85,
88,811,
812

NC

813

lOW

814

-

lOR

815
thru
821

NC

822

IRQ6

1/0

FUNCTION

1/0 WRITE

I

lOW is asserted when the DMA Controller or Host
writes a data, status, or control byte to the
WD1002-WA2.

1/0 READ

I

lOR is asserted when the DMA controller or Host
reads a data from the WD1002-WA2.

INTERRUPT
REQUEST 6

0

IRQ6 is asserted to interrupt the Host upon completion of a command. Applies to floppy controller
only.

SIGNAL NAME

823,B24
825

NC

826

DACK2

DMA
ACKNOWLEDGE
CHANNEL 2

0

DACK2 is asserted in response to DMA request
channel 2.

827

TIC

TERMINAL
COUNT

I

Indicates sending of the last byte in a floppy disk
transfer.

828

ALE

ADDRESS
LATCH ENABLE

I

Indicates board address is available.

829

+5V

+5V

830

NC

6-140

Winchester Board Products

TABLE 2. HOST INTERFACE CONNECTOR (P1') PIN DESCRIPTION
PIN
NUMBER

MNEMONIC

C1
thru
C10

NC

C11
thru
C18

S08
thru
S015

01

NC

02

1/0 CS
16

03
thru
06

NC

07

IRQ14

08
thru
015,017

NC

SIGNAL NAME

OATA BIT 8
thru
OATA BIT 15

1/0 16-BIT
CHIP
SELECT

1/0

FUNCTION

1/0

Bi-directional, upper 8-bit data bus for data transfers
only between the controller and the Host.

I

1/0 CS 16 signals the system board that the current data transfer is a 1 wait-state, 16-bit 1/0 cycle,
derived from an address decode.

INTERRUPT
REQUEST 14

IRQ14 signals the Host that the Winchester controller needs attention. IRQ is generated when the
IRQ line goes from low to high.

+5VOC

016

+5VOC

+5VOC

018

GNO

GROUNO

WINCHESTER DRIVE CONTROL CONNECTOR J5
The Winchester drive control cable connector is a
34-pin printed circuit card edge connector daisychained to each drive in the system. To terminate the
control signals on the W01002-WA2 properly, the last
drive on the daisy chain must have a 220/330 ohm
resistor pack installed. Pin descriptions and control
signals for the drive control connector J5 are given
in Table 3.

Winchester Board Products

6-141

TABLE 3. WINCHESTER DRIVE CONTROL CONNECTOR (J5) PIN DESCRIPTION
SIGNAL

1/0

FUNCTION

HEAD
SELECT31
REDUCE
WRITE
CURRENT

0

HS2

HEAD
SELECT2

0

WG

WRITE
GATE

0

SC

SEEK
COMPLETE

I

10

TKOOO

TRACKOOO

11

12

WF

WRITE
FAULT

13

14

HSO

HEAD
SELECTO

0

The WD1002-WA2 uses HS3 to select one of 16
RIW heads. RWC is not used by drives with
16 head drives. RWC is used by drives with 8
RIW heads. RWC reduces the write current on
the inner cylinders. This lessens the bit shift
caused by greater bit density on these cylinders.
HS2 is one of the head select signals decoded
by the drive to select one of eight (or 16) RIW
heads.
WG is asserted when valid data is to be written on disk. The WD1002-WA2 de-asserts WG
when WF is detected. Special circuitry is included to ensure the system output is free of
glitches during power-on.
SC informs the WD1002-WA2 that the head of
a selected drive has reached the desired
cylinder and has stabilized.
TKOOO is asserted when the RIW heads are
positioned over the outermost cylinder.
WF is asserted by the selected drive when a
write error occurs. While this signal is being
asserted, the command in progress aborts and
no other disk command can be executed.
HSO is one of the head select signals decoded
by the drive to select one of eight (or 16) RIW
heads.

17

16
18

NC
HS1

HEAD
SELECT1

0

19

20

INDEX

INDEX
PULSE

I

21

22

DRDY

DRIVE READY

I

23

24

STEP

STEP PULSE

0

25

26

DSO

0

27

28

DS1

DRIVE
SELECTO
DRIVE
SELECT1

HS1 is one of the head select signals decoded
by the drive to select one of eight (or 16) RIW
heads.
INDEX indicates the start of a track. Used as
a synchronization point during formatting and
as a time-out mechanism for retries. Pulses
once each disk revolution.
DRDY informs the controller that the drive motor
is up to speed.
STEP, with DIRIN. positions the heads to the
desired cylinder. STEP pulses once for each
step. DIRIN determines the step direction.
DSO is used to select drive O.

0

DS1 is used to select drive 1.

DIRECTION
IN

0

DIRIN determines the direction in which the
RIW heads move when the step line is pulsed.
De-asserted = out; asserted = in.

GND

PIN

MNEMONIC

1

2

HS3/RWC

3

4

5

6

7

8

9

-

NAME

15*

29,
31

33

GND
30,
32
34

NC
DIRIN

*Pin 15 is reserved to polarize the connector.

6-142

Winchester Board Products

WINCHESTER DATA CONNECTORS J4, J3

The data lines between the Controller and the two
Winchester disk drives are connected to J4 and J3.
As the data lines are not identical, J4 must be connected to the cable from Winchester drive 1 and J3,
to the cable from Winchester drive 2. Each drive is
radially connected with a maximum cable length of
3 meters (10 feet). Each data connector is a 20-pin
vertical header on 0.25 mm (0.01 inch) center. Data
connector pin descriptions and signals are listed in
Table 4.

TABLE 4.
WINCHESTER DRIVE DATA CONNECTORS (J3, J4)
PIN DESCRIPTION
SIGNAL
GND

PIN

110

1

SIGNAL NAME

NC
GND
NC
GND
NC
GND
NC

2
3
4
5
6
7
8*
9
10
11
12
13
14

0
0

17
18

I
I

15
16

19
20

NC
NC
GND
GND
+ MFMD Write Data
-MFMD Write Data
GND
GND
+ MFMRD Read Data
-MFMRD Read Data
GND
GND

*Pin 8 is reserved to polarize the connector

Winchester Board Products

6-143

TABLE 5. FLOPPY DRIVE CONTROL AND DATA CONNECTOR (J1) PIN DESCRIPTION
SIG
GND

SIG
PIN

SIGNAL
MNEMONIC

1

2

WCCNTRL-

1

4

NC

SIGNAL NAME

WRITECURRENTCONTROL-

1/0

FUNCTION

0

Inverted Form of SOO for read data. Selection
of 300kbs data rate asserts WCCNTRL.

5

Pin 5 is reserved to polarize the connector.
6

NC

7

8

INDEX·

INDEX·

I

Assertion indicates start of a track

9

10

MOTEN1·

MOTORENABLE1·

0

MOTEN1- (MOTEN2-) turns on the floppy disk
drive spindle.

15

16

MOTEN2-

MOTORENABLE2·

0

MOTEN1· (MOTEN2-) and the appropriate drive
select signal must be asserted at the same time.

11

12

DS2-

DRIVE·
SELECT2-

0

Assertion selects drive 2. MOTEN2· must be
asserted at the same time as OS2-.

13

14

DS1

DRIVESELECT1·

0

Assertion selects drive 1. MOTEN1- must be
asserted at the same time as DS1·.

17

18

DIR

DIRECTION

0

Assertion moves the selected read/write head
inward. De-assertion moves the selected read/rite
head outward.

19

20

STEp·

STEPPULSE-

0

Assertion moves the read/write head one track at
a time. The head moves in direction determined
by the DIR- signal.

21

22

WRT DATA-

WRITE·
DATA-

0

MFM data.

23

24

WRT EN·

0

Assertion enables the writing of data on an
unprotected diskette.

25

26

TRKO

WRITE·
DATA·
TRACKO

I

Assertion indicates that the read/write head is
over the outermost track.

27

28

WRT PROT

WRITE PROTECT

I

Assertion indicates a write protected diskette.

29

30

READ DATA

READ DATA

I

M FM Read Data.

31

32

HS1

HEAD

0

Assertion selects head 1.

33

34

DISKETTE
CHG

DISKETTE
CHANGE

I

Assertion indicates drive is not ready i.e., drive
door open, no diskette in drive, or improper asser·
tion of motor enable or drive select Signals.

6-144

Winchester Board Products

WINCHESTER FORMAT

The format used for Winchester disk track formatting
is shown in Figure 2. The ID and data fields on any
disk are initialized by the Format command.
NOTES

ID FIELD

1. GAP 1 and 3 length equals 22 bytes
2. Decision to assert RG is made two bytes after the
start of DRUN
3. RG is de·asserted:
• If DRUN does not last until A1
• When any part of the ID does not match the
one that is expected
• After CRC, if correct ID has been read.
4. Write splice recorded on disk by asserting WG.
5. RG is suppressed until after write splice.
6. Not a proper A 1 or FB, set DAM error.
7. Sector size as stated in ID field, plus four for ECC.

A1 = A1 Hex with OA Hex clock
IDENT = Bits 1,0 = Cylinder High
FE = 0·255 Cylinders
FF = 256·511 Cylinders
FC = 512·767 Cylinders
FD = 768-1023 Cylinders
HEAD = Bits 0,1,2 = Head Number
Bits 3,4 = 0
Bits 5,6 = Sector Size
Bit 7 = Bad Block Mark
Sec # = Logical Sector Number
DATA FIELD

A1 = A1 Hex with 01 Hex clock
FB = Data Address Mark: Normal Clock
USER = Data Field 512 Bytes

FIGURE 2. WINCHESTER DISK FORMAT

REPEATED FOR EACH SECTOR

I~

10 FIELD

1

DATA F I E L D -

~

() GAP'
I GAP'
41E
4E

A
1

14 BYTES

'00'

1
F

I
0
E
N
T

C
Y
L

L

0
W

H
E
A
0

S
E
C
#

C
R
C
1

I

C
R
C
2

3 BYTES 12 BYTES

'00'

READ GATE

~

Winchester Board Products

8

II

I

4ECC

I

II

III

!I~I--------------------~----~L

--1.J,
I I

I

I I

I

I

///I//$/!//////M

2

USER DATA

,

,

1

F

I
WRITE GATE

DRUN~

'00'

A
1

3 BYTES GAP3
'00'
4E
1

I

0

4

V#I//III///!1~
6

~ __________ 7....1_ _ __

6':'145

REGISTER ADDRESS MAP

The WD1002-WA2 contains seven Read/Write task file
registers in the WD1010A-05, a 16-bit Data Register,
Digital Output and Input Registers, Alternate Fixed
Disk Status Register and fixed Disk Register. The
WD2293-07 and WD2293-08 contain a 2-bit Floppy
Control Register in each device. Main Floppy Status
and Data Registers are in the NEC mPD765A. These
registers are mapped into either a primary or secondary I/O address. All Winchester data, control, and
status information pass between the task files or Data
Register and the Host. All floppy data, control, and
status information pass between the floppy registers.
All Winchester data transfers between the Host and
Data Register are word transfers except ECC bytes
in Read Longs and Write Longs. These ECC'bytes are
transferred in byte mode. Control and status bytes
are also transferred between the Host in byte mode.
The task file registers are multiplexed with 10R- and
10W- to give 14 possible ports. Five of the eight task
file registers are bi-directional. Two of the task file
registers have different definitions for read and write
operation. Jumpers select the primary and secondary
address. This allows two controllers in the same Host
system. However, secondary ports on the
WD1002-WA2 are NOT supported by any version of
DOS.
Table 6 summarizes the WD1002-WA2 I/O port
address map. Figure 3 summarizes the WD1010A-05

6-146

task file registers and bit assignments. Figure 4 summarizes the other I/O registers and bit assignments
for the WD1002-WA2. Bit assignments are with
respect to the Host lower byte bus terms, SD7 through
SDO. The fixed size/drive/head (SDH) and status
registers in the WD1010A-05 descriptions Slightly differ from the standard descriptions in the WD1010-05
data sheet. Please note that the SDH register is set
for the ECC option mode and 512 bytes per track. The
SDH register also limits the number of drives to two
and the number of heads to 16. Bit 2 of the
WD1010A-05 status register is designated as the Corrected Data bit. Assertion (setting to 1) of this bit
indicates the sector read from the drive resulted in
a correctable ECC error. Soft errors do not end mUltiple sector transfers. Bit 1 of the WD1010A-05 status
register is designated as the Index bit. Assertion of
this bit occurs each revolution of the currently
selected drive. Refer to the WD1 01 0-05 data sheet for
a complete description of all other WD1010A-05 bit
assignments. Table 7 describes the bit assignments
for the other WD1002-WA2 control and status
registers.
NOTE

Where differences exist, the values and descriptions
for Figure 3 take precedence over the WD101().{)5 data
sheet.

Winchester Board Products

TABLE 6. WD1002·WA2 REGISTER ADDRESS MAP

110 ADDRESS
READ

WRITE

PRIMARY

SECONDARY

1FO

170

1F1

171

ERROR REGISTER

WRITE PRE-COMP

1F2

172

SECTOR COUNT

SECTOR COUNT

DATA REGISTER
DATA REGISTER
(16 bits)

DATA REGISTER
(16 bits)

WD1 01 OA-QS TASK REGISTERS

1F3

173

SECTOR NUMBER

SECTOR NUMBER

1F4

174

CYLINDER NUMBER
(low byte)

CYLINDER NUMBER
(low byte)

1F5

175

CYLINDER NUMBER
(high byte)

CYLINDER NUMBER
(high byte)

1F6

176

SDH REGISTER

SDH REGISTER

1F7

177

STATUS REGISTER

COMMAND REGISTER

CONTROL AND STATUS REGISTERS
DIGITAL OUTPUT REGISTER

3F2

372

3F4

374

MAIN FLOPPY
STATUS REGISTER
(N EC u PD765A)

MAIN FLOPPY STATUS
REGISTER
N EC u PD765A)

3F5

375

FLOPPY DATA
REGISTER
NEC u765A)

FLOPPY DATA
REGISTER
(NEC u765A)

3F6

376

ALTERNATE FIXED
STATUS REGISTER

FIXED DISK

3F7

377

DIGITAL INPUT
REGISTER

FLOPPY CONTROL
REGISTER
(WD2293-07 and -08)

NOTE
All addresses in Table 6 are in Hex. A Read or Write to I/O address 1FO Hex (170 Hex) is a Read or Write for
the Sector Buffer. Therefore, the hardware for the 16-bit Data Register is the Sector Buffer.

Winchester Board Products

6-147

=E
C
.....

0
0

I'\)

;e
):II

I'\)

REGISTER
WRITE PRE-COMP
ERROR
SECTOR COUNT
SECTOR NUMBER
CYLINDER NO.
CYLINDER NO.
SDH
COMMAND
STATUS

7
BB

0
1
BSY

4
3
2
5
CYLINDER NUMBER DIVIDED BY 4
ID
0
ECC
AC
0
NUMBER OF SECTORS
SECTOR NUMBER
CYLINDER NUMBER (LOW BYTE)
0
0
0
0
0
HS3
HS2
1
DS
0
COMMAND
DRQ
CRD
RDY
WF
SC

0

6

TK

DM

CYL.
HS1

NO.MSB
HSO

IDX

ERR

FIGURE 3. WD1010A-05 TASK FILE REGISTER BIT ASSIGNMENT
7
4
3
2
1
0
5
6
X
FDSEL
X
X
MOEN2 MOEN1 FDMAEN FRST
CB
X
D1B
DOB
RQM
DIO
EXM
X
DRQ
CRD
IDX
ERR
RDY
WF
SC
BSY
HS3EN
RST
IEN0
0
0
0
0
HSODS2DS1DCHG
WTGHS3-/RWCHS2HS1SDBO
TWO BIT REGISTERS IN WD2293-07 AND -08
SDB1

REGISTER
DIGITAL OUTPUT
MAIN FLOPPY STATUS
ALTERNATE STATUS
FIXED DISK
DIGITAL INPUT
FLOPPY CONTROL

FIGURE 4. WD1002-WA2 CONTROL AND STATUS REGISTER
TABLE 7. WD1002-WA2 CONTROL'AND STATUS REGISTER BIT DEFINITIONS

REGISTER
DIGITAL OUTPUT

BIT MNEMONIC
X
MOEN2
MOEN1
FDMAEN

FRST

FDSEL

MAIN FLOPPY STATUS

X
RQM

DIO

EXM
CB
D1B
DOB

6-148

BIT NAME
Reserved
MOTOR ENABLE 2 and MOTOR ENABLE1. Controls
floppy drive motors. Setting this bit to 0 turns off the
associated drive and drive selection can not occur.
FLOPPY DISK INTERRUPT and DMA ENABLE. Setting
this bit to 1 gates floppy disk DMA and interrupt
requests to the I/O interface. Setting to 0 disables the
DMA and interrupt request drivers.
Setting to 0 resets floppy controller. Floppy reset time
is 3.5 usec. Set to 1 by Host software enables the floppy
controller.
FLOPPY DISK SELECT. Set to 0 selects drive A. Set
to 1 selects drive B. Appropriate MOTOR ENABLE bit
must be set.
Reserved
REQUEST FOR MASTER.
Set to 1 to indicate that the floppy data register is ready
for a data transfer. Used with DIO bit.
DATA INPUT/OUTPUT. Controls data transfer direction.
Set to 0 to indicate data transfer is from Host to floppy
controller. Set to 1 to indicate data transfer is to Host
from floppy controller.
EXECUTION MODE. Set to 1 only during the execution
phase in non DMA mode.
Set to 1 to indicate a Read or Write command in
process.
Set to 1 when floppy drive B is in Seek mode.
Set to 1 when floppy drive A is in Seek mode.

Winchester Board Products

TABLE 7 WD1002-WA2 CONTROL AND STATUS REGISTER BIT DEFINITIONS

REGISTER
ALTERNATE FIXED
DISK STATUS

FIXED DISK

BIT MNEMONIC
BSY
RDY
WF
SC
DRO
CRD
IDX
ERR
HS3EN
RST

IEN-

DIGITAL INPUT

DCHG
WTGHS3- (RWC-)
through HSO-

FLOPPY CONTROL

SDB1, SDBO

BIT NAME
Controller Busy Flag Ready from selected drive Write
Fault from selected drive.
Seek Complete from selected drive.
Data Transfer Request Flag Corrected Data Flag from
WD1015-03 Index pulse from selected drive.
Error Flag from WD1015-03 Index pulse from selected
drive.
Error Flag from WD1015-03 Set to 1: Enables HS3-.
Set to 0: Enables RWC-.
Reset. Program Controlled reset to board. This bit maintains the WD1002-WA2 logic reset as long as this is
on. This bit must be on for a minimum of 5.0usec. After
the bit is on for the minimum time, the bit must be
turned off to complete reset function.
Interrupt Enable. Enables or disables IR014. This bit
does not clear the interrupt level in the disabled state.
A pending interrupt would occur when the interrupt is
enabled again. A system master reset clears the interrupt but leaves the interrupt enabled.
DISKETTE CHANGE. Set to 1 if no diskette is in the
drive, drive door is open, or the drive is not ready.
Write Gate on
Drive head select or RWC- (bit 5) for drives using RWCDS2-, DS1- Drive select
The WD2293-07 and WD2293-08 each contain a two bit
Floppy Control register. These registers control the data
transfer rate between the controller and drive and the
data encoding format. The Floppy control registers bit
definitions are as follows:
SDB1 SDBO
00 500kbs MFM*
o 1 300kbs M FM
1 0 250kbs M FM
1 1 125kbs FM**

* Default data rate after Reset.
** International exchange standard for 5 1/4 inch floppy diskettes.
WINCHESTER COMMANDS
The WD1002-WA2 Winchester command set contains
eight commands. Five commands (Restore, Seek,
Read Sector, Write Sector, and Format Track) are
executed through the WD1010A-05 commmand
register. (A sixth WD1010A-05 command, Scan ID is
not directly available to the Host. Scan ID may be
executed by the WD1015-03 transparently to the Host.)
The three remaining commands (Read Verify,

Winchester Board Products

Diagnose, and Set Parameters) are executed through
the WD1015-03.
Table 8 describes the eight WD1002-WA2 Winchester
commands and their bit assignments. The next section describes a typical Winchester command
sequence. Each Winchester command is described
following the command sequence.

6-149

TABLE 8. COMMANDS AND COMMAND CODES
COMMAND

BITS

Restore
Seek
Read Sector

0
0
0

0
1
0

Write Sector
Format Track

0

0
1

Read Verify

0
0

Diagnose
Set Parameters

1
1

1

0
1
1
1

1

0
0

0
0

0
0

1
0
1

R3
R3
0

R2

R1

RO

R2
0

0

0
0

R1
L
L

RO
T
T

0

0

0

0
0

0

0

T

1
1

0
0

0
0

0
0

0
1

1

LEGEND
R3 through RO Step rate selection bits. Refer to
Table 8 for more detailed information.
L

Read or Write Long bit. Set to 1
enables Read or Write Long mode.

T

Retry bit. Set to 1 disables retries.

The stepping rates for the commands that perform
implied seeks are set in the least significant nibble
of the last executed RESTORE or SEEK command.
Table 9 describes the Winchester step rates.

TABLE 9. STEPPING RATE
R3

R2

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

R1

RO

STEPPING
RATE

R3

R2

3Susec
1
0
0
0
1
O.Smsec
1
0
0
1
1
0
1.0msec
0
1
1
1.Smsec
1
0
1
1
2.0msec
0
0
1
2.Smsec
1
1
0
1
1
1
3.0msec
0
1
1
1
1
3.Smsec
Note: After Diagnose or reset, stepping rate defaults

WINCHESTER COMMAND SEQUENCE
DESCRIPTION
This section secribes a typical Winchester command
execution sequence. The description illustrates the
relationship between Host and the major components
of the WD1002-WA2 during command execution.
In the idle state: the WD1010A-05 drive control signals
are off. The controller status indicates ready. Drive
status is valid. Controller interrupt is enabled but not
asserted. The WD1015-03 is idle and is monitoring the
WAKEUP signal input.
The Host outputs the command parameters to the
WD1010A-OS task file, the operation command (Seek,
Read or Write) and the command attributes (Long
mode, retry control, etc.). For write operations, the
Host also outputs the sector or format data.

R1

RO

0
0
1
0
1
0
1
1
0
0
1
0
1
0
1
1
to 7.S msec

STEPPING
RATE
4.0msec
4.Smsec
S.Omsec
S.Smsec
6.Omsec
6.Smsec
7.0msec
7.Smsec

asserted. Write and Format commands first set the
data request status signal DRO. This initiates the
Host data transfer. Completion of the data transfer
(S12 or S16 bytes) sets the WD1015-03 WAKEUP Signal
and Busy status.
The WD1015-03 examines the command, verifies command parameters, and passes the command to the
WD1010A-OS for execution.
The WD1010A-OS executes the command providing
drive positioning, data transfer control, error monitor·
ing and completion status. The WD10C20 provides
drive read and write data control for commands that
require data transfers.

The command byte is intercepted by the WD1014-01
and is held for later interpretation by the WD101S-03.

On command completion, the WD1010A-OS interrupts
the WD101S-03. The WD101S-03 examines the command, status etc. for any additional requirements. If
completion is indicated, the WD101S-03 sets the controller status to indicate ready and interrupts the Host.

A Read command output sets the module Wakeup
latch that causes the controller status to indicate
Busy and the WD101S-03 WAKEUP signal to be

The WD1002·WA2 returns to the idle state and the
Host may examine drive and controller status, read
input data, etc. as required to complete the operation.

6-150

Winchester Board Products

WINCHESTER COMMAND DESCRIPTION

RESTORE
The Restore command is used to move the R / W
heads to the Track 000 position. The controller issues
step pulses to the drive until the Track 000 indicator
from the drive is asserted. If Track 000 is not asserted
within 1023 steps, the Error Error bit in the Status
Register is set and a Track 000 error is posted in the
Error Register. The implied seek step rate may be set
up according to Table 8 by the Restore command. The
restore step rate is established by the seek complete
signal from the drive, i.e., each step pulse is issued
only after seek complete is asserted by the drive from
the previous step. If the DRIVE READY- signal is deasserted or WRITE FAULT- is asserted, this command
terminates with the error bit set in the status register
and the error register reports an aborted com~and.
SEEK
This command moves the R / W heads to the cylinder
specified in the task file cylinder high and low
registers. The implied seek step rate is also set by
this command. The lower order four bits of the command are used to select one of 16 available step rates.
An interrupt is generated at the completion of the
command. If the DRIVE READY- signal is de-asserted
or WRITE FAULT- is asserted, this command is terminated with the error bit set in the status register
and the error register reports an aborted command.
READ SECTOR
A number of sectors (1 - 256) can be read from the
selected drive with this command. The sector count
register in the task file determines the number of sectors to be transferred. Multiple sector reads may cross
head and cylinder boundaries.
If the Read command is issued prior to initializing a
step rate, the default value of 7.5msec is selected and
a Recalibrate is performed prior to the Read.
If the R / W heads are not positioned over the target
track, the controller performs an implied seek to the
proper cylinder. The stepping rate used during the
implied seek is the value specified during the previous
Seek or Restore command.
The optional long bit (L set to 1 enables Read Long.)
informs the WD1002-WA2 whether or not to include
the four ECC bytes. These four ECC bytes are
transferred as individual bytes, not words, as is the
data field information. The data request bit in the
status register must be valid before each byte
transferred and at least 2usec will pass between each
byte transferred.
Data errors up to 5 bits in length will be automatically
corrected on normal Read commands. If an uncorrectable error occurs, the data transfer will still take
place, a multi-sector read, however, will terminate
after the sector in error is read by the system.
The optional retry bit (T set to 1 disables retries.)
disables or enables retries. The WD1010A-05

Winchester Board Products

automatically retries for ten disk revolutions when the
retry bit is enabled. The WD1010A-05 properly sets the
error and status registers if the retries are unsuccessful. Disabling retries allows only two disk revolutions for automatic retries before the WD1010A-05
sets the error and status registers.
For ECC errors, eight Read retries are made at reading
before a soft uncorrectable error is reported. A Read
retry results in the reissuing of the WD1010A-05 Read
Sector command. The WD1010A-05 Read Sector command attempts to verify the sector ten times, if T is
set to 1 before returning an error. ECC correctable
data err~rs are corrected after two consecutive matching ECC syndromes are detected. If the error is an
uncorrectable error or an error is reported by the
WD1010A-05, the command terminates.
Interrupts occur as each sector is ready to be read
by the system. No interrupt is generated at the end
of the command. If the DRIVE READY- signal is deasserted or WRITE FAULT- asserted, this command
terminates with the error bit set in the status register
and the error register reports an aborted command.
WRITE SECTOR
A number of sectors (1 - 256) can be written to the
selected drive. The sector count register in the task
file determines the number of sectors to be transferred. Multiple sector writes may cross head and
cylinder boundaries.
If the Write command is issued prior to initializing a
step rate, the default value of 7.5msec is selected and
a Recalibrate is performed prior to the Write.
If the heads are not positioned at the cylinder
specified in the cylinder high and low registers, the
controller performs an implied seek. The step rate
used is determined by the step rate field of the most
recently executed Restore or Seek command.
The optional long bit (L set to 1 enables Write Long.)
informs the WD1002-WA2 whether or not to append
the Host supplied ECC bytes. These four bytes are
transferred as individual bytes, not words, as is data
field information. The data request bit in the status
register must be valid before each byte transferred
and at least 2usec will pass between each byte
transferred.
The optional retry bit (T set to 1 desables retries.)
disables or enables retries. The WD1010A-05 performs
up to ten automatic retries when the retry bit is
enabled. The WD1010A-05 properly sets the error and
status registers if the retries are unsuccessful. Disabling retries allows only two automatic retries before
the WD1010A-05 sets the error and status registers.
The WD1002-WA2 interrupt is generated as the data
for each sector is required to be transferred into the
Sector Buffer (except the first sector) and at the end
of the command. The first sector may be written to
the buffer immediately after the command has been
sent, and the data request status is set. If DRIVE

6-151

READY- signal is de-asserted or WRITE FAULT- is
asserted, this command terminates with the error bit
set in the status register and the error register reports
an aborted command.
FORMAT TRACK
The track specified by the task file is formatted with
10 and data fields according to the interleave table
transferred to the buffer. The interleave table, consists
of two bytes per sector as follows:
00
00
00

PHYSICAL SECTOR 1
PHYSICAL SECTOR 2
PHYSICAL SECTOR 3

00

PHYSICAL SECTOR 17

The data transfer must be 512 bytes even though the
table may be only 34 bytes. The sector count register
must be loaded with the number of sectors per track
before each Format Track command. The Format
Track sommand supports no error reporting. A bad
block may be specified by replacing a 00 table entry
with an 80 hex. When switching between drives, a
Restore command must be executed prior to attempting a format. Command completion will leave all data
fields initialized to zeroes. The completion interrupt
is generated after each track has been formatted.
READ VERIFY
This command functions similarly to a normal Read
command except that data is not output to the Host.
One to 256 sectors may be verfied at one time. The
generated ECC bytes are compared with the recorded
ECC bytes for data verification. A single interrupt is
generated upon completion of the command or in the
event of an error.
If the Read Verify command is issued prior to initializing a step rate, the default value of 7.5msec is
selected and a recalibrate is performed prior to the
Read Verify.
For ECC errors, eight Read retries are made at reading
before a soft uncorrectable error is reported. A Read
retry results in the reissuing of the WD1010A-05 Read
Sector command. The WD1010A-05 Read Sector command attempts to verify the sector ten times, if T is
set to 1, before returning an error. ECC correctable
data errors are corrected after two consecutive matching ECC syndromes are detected. If the error is an
uncorrectable error or an error is reported by the
WD1010A-05, the command terminates. The WRITE
FAULT- and DRIVE READY- inputs are checked
throughout the command's execution.

6-152

DIAGNOSE
The Diagnose command causes the Controller to perform an on-board diagnostic and to report the result
in the Error Register. An interrupt is performed upon
completion of the command.
The Diagnose command performs tests on the
WD1015-03's internal ROM and RAM, the WD1014-05,
and the Sector Buffer. If any component fails, the
appropriate error code is loaded into the error register.
Error codes are as follows:
01
02
03
04
05
00, 06-FF

No errors
WD1010A-05 register access error
Sector Buffer RAM data error
WD1014-01 register access error
WD1015-03 ROM checksum or RAM data
error
Not used. Undefined.

In addition, the Diagnose command sets the write precomp task file register to 32. This causes write precompensation to begin at cylinder 128. (Since the
write pre-comp register holds the desired value
divided by four.) The sector count register is reset to
one while the cylinder high, cylinder low, and SOH
registers are all set to zero.
SET PARAMETERS
This command sets up the drive parameters regarding the maximum number of heads and sectors per
track. The WD1002-WA2 uses these two parameters
when performing multiple sector operations. The SOH
task file register specifies the drive affected. The sector count and SOH registers must be set up before
this command is issued. An interrupt is set at the
completion of the command.
This command must be issued before any multiple
sector operations are undertaken. By setting the SOH
register for each of the two possible drives, this command allows the WD1002-WA2 to support two drives
with different characteristics.
FLOPPY COMMANDS AND FLOPPY COMMAND
SEQUENCE

The WD1002-WA2 supports all NEC uPD765A commands. Table 10 lists the NEC uPD765A commands
and command codes. Refer to the NEC Microcomputer Division Catalog for further descriptions of the
floppy disk controller commands, command protocols
and command sequence.

Winchester Board Products

TABLE 10. COMMAND CODE DESCRIPTION

COMMAND CODES

COMMAND
SDB7

SDB6

SOBS

SDB4

SDB3

SDB2

SDB1

SDBO

READ DATA·

MT

MF

SK

0

0

1

1

0

READ
DELETED DATA·

MT

MF

SK

0

1

1

0

0

WRITE DATA·

MT

MF

0

0

0

1

0

1

WRITE
DELETED DATA·

MT

MF

0

0

1

0

0

1

READ TRACK·

0

MF

SK

0

0

0

1

0

READ ID·

0

MF

0

0

1

0

1

0

FORMAT
TRACK·

0

MF

0

0

1

1

0

1

SCAN EQUAL·

MT

MF

SK

1

0

0

0

1

SCAN LOW
OR EQUAL·

MT

MF

SK

1

1

0

0

1

SCAN HIGH
OR EQUAL·

MT

MF

SK

1

1

1

0

1

0

0

0

0

0

1

0

0

SEEK·

0

0

0

0

1

1

1

1

RECALIBRATE··

0

0

0

0

0

1

1

1

SENSE
INTERRUPT
STATUS

0

0

0

0

1

0

0

0

SPECIFY

0

0

0

0

0

0

1

1

SENSE
DRIVE STATUS·

HUT

SRT

ND

HLT
INVALID

Invalid command codes: No operation - floppy controller enters standby state.

·Second byte of command code for these commands is as follows:
SDB7 through SDB3: Set to zero. SDB2: HD. SDB1: O. SDBO: 0
··Second byte of command code for Recalibrate is as follows:
SDB7 through SDBO: Set to zero.
LEGEND
MT

Multi-track

MF
SK
HD
SRT

FM/ MFM mode
Skip
Head
Step Rate
Time
Head Unload
Time
Head Load
Time
Non-DMA Mode

HUT
HLT
ND

Winchester Board Products

Set to one for multi-track operation. If set to one after execution of
Read / Write operation on side 0, floppy controller automatically searches
for sector 1, side 1.
Set to zero for FM. Set to one for MFM:
Set to one to skip deleted data address mark.
Set to one for head 1. Set to zero for head O.
1 to 16 msec in 1msec increments (Ohex
16msec, 1hex
15msec ...
Ehex = 2msec, Fhex = 1msec. Step rates apply to both drives.
16 to 240msec in 16msec increments.

=

=

2 to 254msec in 2msec increments.
Set to one for non-DMA mode.

6-153

SUPPORT OF 1.2MB AND 360KB DRIVES

INSTALLATION

The WD1002-WA2 supports 1.2MB and 360kB drives.
Diskettes written on 1.2MB drives with the 360kB density may not be readable on 360kB drives due to a
difference in track widths. High capacity drives
(1.2MB) require special media to support a recording
density of 9646 bits per inch. This special media
requires much higher write currents than 360kB drives
can produce. Thus, the special media is incompatible with the high capacity drives.

This section briefly describes the installation of the
WD1002-WA2 board in IBM PC-AT compatible
computers.
1. Ensure that system power is off.
2. Insert the WD1002-WA2 board into the computer
chassis and connect the drive cables. (J1 = floppy
drives 1 and 2 cable, J5 = Winchester control
cable, J4
Winchester drive 1 cable, J3
Winchester drive 2 cable)

=

High capacity drives rotate at 360 RPM instead of 300
RPM. A new data transfer rate of 300kbs is used to
enable the Host system to read diskettes written on
360kB media. This means that a diskette recorded at
250kbs on the 300 RPM drives reads at a 300kbs rate
in the 360 RPM drives.

The WD1002-WA2 board is configured for IBM PC-AT
compatible computers. Jumper plugs are installed at
E1 / E6 and E7 / E8. Figure 5 illustrates the
WD1oo2-WA2 jumper locations. The following jumper
options are available:

Recorded track width is determined by the
read / write head. The 1.2M B drives write tracks at a
0.16mm (0.00063 inch) width instead of the 0.33mm
(0.0130inch) track width for 360kB drives. This can
cause some incompatibilities when exchanging
media written on the high density drive at the low density rate. This type of interchange is best supported
by addition of a 360kB drive to the Host system.
Floppy write precompensation is 125 nsec at all
transfer rates over all tracks. Floppy write precompensation cannot be disabled or programmed.

Standard: E2-E3 Selects primary addresses 3F2,
3F4 / 3F7 hex for the floppy disk
drives.
E5-E6 Selects primary addresses
1FO /1 F7 hex for the Winchester
disk drives
Jumpered: E1-E2 Selects secondary addresses 372,
374 / 377 hex for the floppy disk
drives
E4-E5 Selects secondary addresses
170/177 hex for the Winchester
disk drives

Other features for the high capacity drives include
3msec track to track access time vs. 6 msec and a
motor start time of 750msec vs. 250msec. The
WD1002-WA2 supports only two drives. Data transfers
are performed over the DMA channel.

Standard: E7-E8 Jumper installed. Must be left
jumpered at all times.

E1
E2
E3

E7
J3

J4

J5

=

E8

Jl

~~ ~~

[8

_ _ _ _ _ Al

Pl

FIGURE 5. WD1002·WA2 Jumper Locations

6-154

Winchester Board Products

SPECIFICATIONS

Encoding Method:
Data Rate:
Format:
Sectoring:
Cylinders:
Heads:
Drives:
Soft Error Rate:
Head Error Rate:
Seek Error Rate:
Precompensation:
Interleave Factor:
CRC Polynomial:
ECC Polynomial:
ECC Polynomial
Reciprocal:
ID Field CRC
Polynomial:
Data Field CRC
Polynomial:
DATA SEPARATOR:

Hard Disk
MFM
5Mbs
IBM XT compatible
Soft, 512 byte by 17 per track
(Numbered 1 through 17)
1024
16 max
2
1 in 10E10 bits read
1 in 10E12 bits read
1 in 10E6 seeks
+ / - 12 nsec, single-level MFM

Floppy Disk
FM and MFM
125kbs, 250kbs, 300kbs, 500kbs
IBM PC-XT compatible
Soft, up to 15 by 512 byte sectors
per track
77 max
2 max
2
1 in 10E09 bits read
1 in 10E12 bits read
1 in 10E6 seeks
+ / - 125 nsec write precompensation for all data rates

2 to 1 min
A
A
A
x 16 + x 12 + x- 5 + 1 \
A
A
A
A
A
x 32 + x 28 + x 26 + x 19 + x 17
A
A
A
+ x 10 + x 6 + x 2 + 1
A
A
xA 32 + xA 30 + xA 26 + x 22 + x 15
A
A
A
+ x 13 + x 6 + x 4 + 1

Type:

WD10C20 self-adjusting VCO

Analog with dual R-C VCO

Features:

reference clock, 0 phase startup,
read pulse extension, DRUN generation write precompensation

single adjustment for each VCO,
automatic of adjustment

Acquisition Time:

Less than 8 bytes

Less than 8 byte times

Capture Range:

+ /-3% min

+ / -8.5% min
+ / -10 deg

Phase Error:
POWER:

Logic Supply:
Supply Ripple:

+5V+ / -5%,2.5 A max
+ / -100mV, pop

Analog Supply 1:
Supply Ripple:

+ 12V + / -10%,0.150 A max
+ / -100 mV, pop

Analog Supply 2:
Supply Ripple:

-12V + / -10%, 0.01 A max
+ / -100 mV, pop

ENVIRONMENTAL:

Temperature
Operating
Non-operating

OoC to 50°C -40°C to 60°C (32°F to
122°F) HOoF to 140°F)

Air Flow

100 LFM min constant unidirectional, measured on a plane 1 /4 in.
equidistant from PCB surface.

Winchester Board Products

6-155

Floppy Disk

Hard Disk
Humidity
Operating
Non-operating

8% to 80% non-condensing
5% to 95% non-condensing

Altitude
Operating
Non-operating

o to
o to

Vibration
Operating

6 to 600 Hz at 1.0 G

3000 meters (0 to 10000 feet)
5000 meters (0 to 16000 feet)

PHYSICAL:

Length
Width
Height

33.3 centimeters (13.1 inches)
12.2 centimeters (4.80 inches)
1.90 centimeters (0.75 inches)

HOST INTERFACE TIMING

Timing diagrams are shown in Figure 6. the timing values are given in Table 11.

SA09-01

(

)--.----------------------~

>--

5AOO - - - (

-lOR/-lOW

-IOC516

----11

\ _______

\_------------~I

READ DATA

----------------~(~----------~)~---

WRITE DATA

------------~(~------------~)~--FIGURE 6. I/O CHANNEL TIMING

6-156

Winchester Board Products

TABLE 11. TIMING
TIMING (nsec)

CHARACTERISTIC
min
-IOC816 from

8A09~01

93

-IOC816 from 8AOO

+ IOC816

from

73

+ lOR / + lOW

93

8015-00 from -IOR(16 bit I/O)

132

8007-00 from -lOR (8 bit I/O)
8015-00 to
6007-00 to

+ lOW to
+ lOW to

+ lOW (16 bit I/O)
+ lOW ( 8 bit I/O)

498
71
491

8015-00 HIZ (16 bit I/O)

54

8007-00 HIZ (8 bit I/O)

46

-lOR / -lOW Pulse Width (16 bit I/O)

160

-lOR / -lOW Pulse Width (8 bit I/O)

540

+ lOR / + lOW

375

to -lOR / -lOW

AOOR HaLO from

+ lOR / + lOW

8A09-01 to -lOR / -lOW

Winchester Board Products

max

47
97

6-157

6-158

Winchester Board Products

WESTERN
COR

P

0

DIGITAL

RAT

o

N

=E

c
.....

WD1003-SCS Winchester Disk Controller
FEATURES

•
•
•
•
•
•
•
•
•
•
•
•

SCSI COMPATIBLE BUS HOST INTERFACE
CONTROLS UP TO TWO ST506 COMPATIBLE
DRIVES
ALLOWS OVERLAPPED SEEKS
UP TO 16 HEADS AND 2,048 CYLINDERS
PROGRAMMABLE SECTOR SIZES (128,256,512,
AND 1024 BYTES PER SECTOR)
PROGRAMMABLE STEPPING RATES (3
MSEC/STEP MINIMUM)
PROGRAMMABLE GAP SIZES
USER-SELECTABLE DEVICE ADDRESS
PROGRAMMABLE 1:1 INTERLEAVE
FULLY SUSTAINED, SEQUENTIAL READfWRITE
OPERATIONS
SELF-TEST DIAGNOSTICS
32-BIT ECC FOR WINCHESTER DATA ERROR
DETECTION AND CORRECTION

DOCUMENT SCOPE

This document is intended to provide the reader with
an overview of the WD1003-SCS. For a detailed
understanding it will be necessary to refer to the
following documents:
•

WD1003·SCS Winchester Disk Controller OEM
Manual Doc. 79-000025

•

SCSI Specification ANSI X3T9.2 August 1984

•

ST-506 Winchester Disk Controller
ST506 S.M.
Seagate Technology,
Scotts Valley, Cal.

•

ST-506 Electrical Interface Specification
Seagate Technology,
Scotts Valley, Cal.

•

WD2010-05 Winchester Controller Data Sheet

•

WD10C20 Self-Adjusting Data Separator Data
Sheet

DESCRIPTION

The WD1003-SCS is a single-board Winchester Disk
Controller designed to support up to two ST506 compatible disk drives and to interface to the Small
Computer System Interface (SCSI) bus. Bus operation
is in compliance with the ANSI X3T9.2 SCSI
Specifications.

Winchester Board Products

•
•
•
•
•
•
•

•
•
•
•

o
o
w

COMMAND QUEUING
LOGICAL UNIT ADDRESSING
SCSI BUS PARITY OPTION
FULL HARDWARE COMPLIANCE WITH ANSI
SCSI X3T9.2 SPECIFICATIONS
DISCONNECT/RECONNECT
SUPPORTS
OPERATIONS
OPTIONALLY SUPPORTS RESELECTION
TIME·OUT '
SUPPORTS ALL STANDARD AND EXTENDED
COMMANDS, AND WESTERN DIGITAL'S UNIQUE
COMMANDS
SINGLE-BYTE MESSAGES
SENSE AND EXTENDED-SENSE CAPABILITY
RESERVATONS SUPPORTED TO LOGICAL UNIT
NUMBER LEVEL
SECTOR LEVEL BAD BLOCK MAPPING
CAPABILITY

Commands directed to the drives are executed by the
WD1003-SCS and all communications and data
transfers to and from the Host take place via the SCSI
bus in accordance with SCSI protocol.
The WD1003-SCS functions only as a Target device
in the SCSI environment. Because the WD1003-SCS
supports disconnect/reconnect operations, full
arbitration capability is provided. In addition, the
WD1003·SCS Controller board supports one-to-one
disk interleave, i.e., fully sustained operations on
sequential read access.
The WD1003-SCS is based on a proprietary chip set
consisting of the WD2010·05, WD11COO-19 and
WD10C20 LSI devices, designed specifically for Winchester/SCSI interface. Extensive error detection and
correction, as well as data recovery techniques for
disk errors, are incorporated within the controller's
design. This circuitry resides in the WD2010-05. The
WD11COO-19 is used to control all communications
and data transfer.
ARCHITECTURE

The WD1003-SCS architecture allows an optimum
amount of design functions to reside within the board.
This is accomplished by creating a unified internal
bus structure, whereby all major LSI devices share
the same buses.

6-159

en
(')

en

"'001 ,C/O, 1/0,115&

DP,m,m
PM'

DAlAl/O,seSIIJO
BUS
If(

A{D(SS BUS CAO-CAI!.

(CNITAOI.

~

r'"

FIGURE 1. BLOCK DIAGRAM

As illustrated in Figure 1, the WD1003-SCS contains
four major VLSI devices:
•
•
•
•

8085 microprocessor
WD2010-05 Winchester Controller
WD10C20 Self-Adjusting Data Separator
WD11COO-19 SCSI Protocol Support Device

Control Processor

The Control Processor is an 8085 microprocessor
used for the main board control, and is supported by
a 2764 (8K X 8) EPROM and a (2K X 8) 2016 static RAM
device. The WD1003-SCS Controller's unique architecture facilitates two major functions:
•
•

Support of the SCSI bus application
1:1 interleave capability

WD2010-05 Winchester Disk Controller

The primary function of the WD2010-05 is to control
data transfer between the disk and the Sector Buffer after the on-board control processor has positioned the selected head over the desired track. The
WD2010-05 receives the parameters and commands
from the control processor via the CDO through CD7
bus.

6-160

In addition, built-in Error Checking and Correction
(ECC) capability in the WD2010-05 enables error detection and correction on all data transfers from the disk.
A set of check bits are calculated and appended to
the data field when data is written to the disk.
WD10C20 Self-Adjusting Data Separator

The WD10C20 is an LSI device implemented in the
3-micron, high-speed CMOS as a read/write channel.
It performs all sensitive read/write Signal operations
between the Winchester Disk Controller and data
drivers and receivers. The device performs both phaselocked loop data synchronization on read data from
the drive and conditioning write data to the drive.
WD11 COO-19 SCSI Protocol Support Device

The WD11COO-19 is a 40-pin LSI device deSigned to
provide four major support functions:
• Address generation
• Data Transfer (read/write) control
• Arbitration
• Parity checker/generator
All SCSI commands are read, format converted, and
then issued to the WD2010-05 for execution.

Winchester Board Products

SPECIFICATIONS

:E
c
......

HOST INTERFACE
Type

SCSI

Cable length
Termination all signals

20 ft. (6 m) max.
Socketed 220/330 ohm resistor pack
220 ohms to + 5 Volts,
330 ohms to ground
Jumper selectable (0 through 7)
Default = 0

Addressing

o
o

(,.)

en

C1

CJ)

DRIVE INTERFACE
Encoding method
Cylinders per drive
Bytes per sector
Sectors per track
Heads per cylinder
Drives
Stepping rates/algorithm
Data transfer rate
Write precompensation
Sectoring
CRC polynomial
ECC polynomial
Cable length:
Control (daisy-chained)
Data (radially connected)
Termination:
Control
Data

MFM
Programmable up to 2048
Programmable (128, 256, 512, 1024)
Programmable
Programmable up to 16
2
Programmable (3 usec/step min.)
5 Mbps
12 nsec
Soft
X16+X12+X5 + 1
X32 + X28+ X26 + X19 +
X17 +X10+X6 +X2 +1
10 ft. (3 m) max.
10 ft. (3 m) max.
all signals 220 ohms to + 5 Volts,
330 ohms to ground
on last drive in chain
on WD1003-SCS

DATA SEPARATOR
The operational parameter limits of the Data Separator circuitry on the
WD1003-SCS provided here are related only to ST506 Winchester disk
operations. For the WD1003-SCS to function properly, the hard disk
drive mechanism must perform within the following specifications:
Drive margin
± 16 nsec min
Drive Asymmetry
30 nsec. measured over 5 Mhz RAWMFM
periods of 185 nsec, 215 nsec, 185 nsec.

ELECTRICAL
Voltage and Current

+5 Vdc±5% @ 1.5 amps nominal 2 amps max
+ 12 Vdc ± 10% @ 0.25 amps nominal

SCSI electrical description
When measured at the SCSI bus device connection, each signal driven by an
SCSI device has the following output characteristics:
Signal assertion = 0 to 0.5 Vdc
Minimum driver output capability = 48mA(sinking) @ 0.5 Vdc
Measured at the connector, each signal has the following input characteristics:
Signal Asserted
Maximum total input load
Signal de-asserted

Winchester Board Products

0 to 0.8 Vdc
-0.4 rnA @ 0.4 Vdc
2.0 to 5.25 Vdc

6-161

:ec
.....

o
o
w

en

o

en

PHYSICAL DIMENSIONS
Length
Width
Height (including board,
components and leads)

8 inches (20.3 cm)
5.75 inches (14.6 cm)
0.75 inches (1.9 cm)

ENVIRONMENTAL
Temperature:
Operating range
Storage range
Relative Humidity
Operating range
Storage range
Maximum wet bulb
Altitude
Operating range
Airflow

OOC (32°F) to 55°C (131°F)
-400C (-40°F) to 60°C (140°F)
8% to 80% non-condensing
5% to 95% non-condensing
24° C (75° F)

°

to 10,000 ft. (3048 m)
150 linear ftjmin @ 0.25 inches from
component sutfaces

Corrosion
Connectors, exposed contacts, and conductors are
protected to resist corrosion under all conditions of
storage and operating life.
INTERFACE ORGANIZATION
The WD1oo3-SCS is designed to be mounted directly
onto a 5.25" Winchester-type hard disk drive. It contains four vertical-header connectors, and one power
connector located along the peripheral edges of the
board:
•
•
•
•

Two Winchester drive data connectors J1, J2
Winchester drive control connector J3
Power connector J4
Host interface connector J5

The WD1003-SCS accommodates up to two Winchester hard disk drives. The control cable is daisychained to each of the two drives; and the drive data
cables, which carry differential signals, are radially
connected. Table 1 defines the WD1oo3-SCS connectors and a source for the mating connectors on the
associated cables.

TABLE 1.

CONNECTOR
J1,J2
J3
J4
J5

6-162

INTERFACE FUNCTION
Drive Data (Radially-connected)
Drive Control (Daisy-chained)
Power
Host Interface (SCSI Bus)

EQUIVALENT
MATING CONNECTOR
Burndy tfFRS20BS
Brundy tfFRS34BS
AMP 1-4840424-0
Burndy tfFRS50BS

Winchester Board Products

HOST INTERFACE CONNECTOR
The WD1003-SCS interfaces to the Host via J5, a
50-pin vertical header connector mounted on 0.1 inch
centers. The cable used should be a flat ribbon or
twisted pair cable of not more than 20 feet in length.
Cable termination is via 220/330 ohm resistor

packs in position Z1 and Z3. Each signal is terminated
to + 5 volts via 220 ohms and 330 ohms to ground.
Table 2 provides the connector pin descriptions and
its bus signals.

SIG.
PIN

1
thru
17

2
thru
18

19
thru
25

26

MNEMONIC
DBO
thru
DB? and
DBP

N.C.

SIGNAL
NAME

1/0
*

DATA BUS 0
thru
DATA BUS?
DATA BUS
PARITY

110

These signals comprise the SCSI tri-state, bidirectional data bus used to transfer commands, status and data. DBO through DB?
are used for Target device selection and
arbitration. DBP is odd parity for DBO
through DB? and is not valid during the
arbitration process.

I

Asserted by the Host to indicate a message
is ready for the WD1003-SCS. This message
is read by the WD1003-SCS at its convenience by performing a Message Out Phase.

1/0

Indicates to the Host that the SCSI bus is
busy executing a command and is unable to
accept another. When asserted, BSY
acknowledges receipt of SEL and its own
address. De-asserted indicates the transfer
is completed.
Acknowledgement for a REQ/ACK
data
transfer handshake, acknowledges to the
WD1003-SCS that the Host has accepted the
byte for data transfer.
When asserted at least 25 usec, RST
places the WD1003-SCS into its initial powerup state.

FUNCTION

Not Connected

GROUND

31

32

33

34

35

36

3?

38

39

40

41

42

43

44

-ATN

ATIENTION

GROUND
BSY

BUSY

-ACK

ACKNOWLEDGE

I

RST

-RESET

I

MSG

MESSAGE

0

Asserted during the Message Byte Transfer
Phase. Used with 1/0 and C/O to indicate the type of transfer.

SEL

---

1/0

Used by the Host to select the WD1003-SCS,
or by the WD1003-SCS to reselect the Host.
When asserted, gives control of the bus to
the DBO through DB? address selected by
the J6 jumper.

--

Winchester Board Products

SELECT

o
o

(,.)

en

GROUND

2?
thru
30

c-"

en
(')

TABLE 2. HOST INTERFACE CONNECTOR (J5) PIN DESCRIPTION
SIG.
GND.

:E

6-163

TABLE 2. HOST INTERFACE CONNECTOR (J5) PIN DESCRIPTION (cont.)

=E

c
.....

SIG.
GND.

SIG.
PIN

(,.)

45

46

o
o

SIGNAL
NAME

MNEMONIC

CONTROU
DATA

CID

en
(")

1/0

FUNCTION

*

a c/O along with 1/0 and MSG indicates to
the Host whether control or data is on the
bus.
C/O - 0 Control
-1
Data
Control is defined as a: command, status, or
message.

en

=
=

47

48

REQ

REQUEST

a

A request for a REQIACK data transfer
handshake. Indicates to the Host that the
WD1003-SCS is ready for data transfer.

49

50

I/O

INPUTI
OUTPUT

a

Indicates
Host and
1/0 - 0
-1

=
=

direction of transfer between the
the WD1003-SCS.
Input to the Host
Output from the Host

* The I/O column is in relation to the WD1003-SCS and not the Host.

WINCHESTER DRIVE CONTROL CONNECTOR
The WD1003-SCS supports the Seagate Technology
ST506 drive control protocol. The control connector
is a 34-pin vertical header mounted on a 0.1 inch
center. Control signals are common to both drives and
are daisy-chained on a single connector J3. The cable
used should be a flat ribbon or twisted-pair not more
than 10 feet in length.

The control signals are to be terminated at the last
drive in the daisy-chain with a 220/330 ohm resistor
pack. Each control signal is connected to + 5 volts
with the 220 ohm resistor and to ground with 330
ohms.
The drive control connector J3 pin description is provided in Table 3.

TABLE 3. DRIVE CONTROL (J3) PIN DESCRIPTION
SIG.
GND.

SIG.
PIN

1

2

3

4

HS2

5

6

WG

7

8

9

10

6-164

MNEMONIC

SIGNAL
NAME

1/0

*

FUNCTION

HEAD
SELECT 3
or
REDUCE WRITE
CURRENT

a

HS3 is one of four Head Select signals
decoded by the drive to select one of 16 RIW
heads. RWC is asserted when the cylinder
specified by the Inquiry Data Format command is reached. An asserted RWG allows
the 8085 to initiate RWC on succeeding
cylinders.

HEAD
SELECT 2

a

WRITE GATE

a

One of four Head Select signals decoded by
the drive to select one of 16 RIW heads.
WG is asserted when valid data is to be
written on the disk. WD1003-SCS de-asserts
this signal when a WF is detected.

SC

SEEK
COMPLETE

I

SC is asserted by the selected drive when
the head has reached the desired cylinder
and stabilized.

TKOOO

TRACK 000

I

The drive asserts this signal when the RIW
heads are positioned over the outermost
cylinder, cylinder zero.

HS3
or
RWC

-

Winchester Board Products

TABLE 3. DRIVE CONTROL (J3) PIN DESCRIPTION (cant.)
SIG.
GND.

SIG.
PIN

11

12

13

14

SIGNAL
NAME

MNEMONIC
WF

WRITE
FAULT

HSO

HEAD
SELECT 0

:ec
-a.

1/0

FUNCTION

I

WF is asserted by the selected drive when a
write error occurs. The command in progress
aborts and no other disk command can be
executed while this signal is asserted.

0

One of four Head Select signals decoded by
the drive to select one of 16 RIW heads.

15

16

N.C.

Not Connected

17

18

HS1

HEAD
SELECT 1

0

One of four Head Select signals decoded by
the drive to select one of 16 RIW heads.

19

20

INDEX

INDEX
PULSE

I

Indicates the start of a track and is used both
as a synchronization point during formatting
and a time-out mechanism for retries. This
Signal pulses once for each disk revolution.

21

22

DRDY

DRIVE
READY

I

Informs the WD1003-SCS that the drive motor
is up to speed.

23

24

STEP

STEP PULSE

0

STEP, together with DIRIN, positions the
heads to the desired cylinder. STEP
pulses once for each cylinder. DIRIN
determines the direction.

25

26

DSEL 0

DRIVE
SELECT 0

0

DSELO is used to select drive

27

28

DSEL 1

DRIVE
SELECT 1

0

DSEL 1 is used to select drive 1.

29

30

N.C.

Not Connected

--

--

31

32

N.C.

Not Connected

33

34

DIRIN

DIRECTION

IN

0

o.

--

DIRIN determines the direction the RIW
heads take when the Step signal is pulsed.
o = in, 1 = out.

WINCHESTER DRIVE DATA CONNECTOR
The data is differential in nature and must be radially
connected to each drive with its own cable, drive 0
to J1 and drive 1 to J2. It should be a flat ribbon

Winchester Board Products

cable, or twisted pair, not more than 10 ft. in length.
The connecter is a 20-pin vertical header on 0.1 inch
center.

6-165

o
o

CAl

en
(")

en

TABLE 4. DRIVE DATA CONNECTORS· J2, J3
SIG.
GND.

SIG.
PIN

SIGNAL
NAME

1/0

NC
GND
NC
GND
NC
GND
NC
GND
NC
NC
GND
GND
+ MFM Write Data
-MFM Write Data
GND
GND
+ M FM Read Data
-M FM Read Data
GND
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14

0
0

17
18

I
I

15
16

19
20
POWER CONNECTOR
A 4-pin, neoprene-type connector (J4) is provided for
power input to the WD1003-SCS board.

PIN

VOLTAGE

1
2
3

+12V
GND.
GND.
+5V

4

COMMAND DESCRIPTION
The WD1003-SCS supports 22 commands. These
commands are separated into three Groups: 15 standard commands in group 0, 4 extended commands
in group 1, and 3 diagnostic commands in group 7.

6-166

A summary of these commands, along with their
Command Description Block is illustrated in the
tables that follow.

Winchester Board Products

TABLE 5. SUMMARY OF GROUP 0 AND 7 COMMANDS

COMMAND

OP
CODE

LUN

:E

LBAI
FD,CL,DLF

INT

NOB/RSBI
NB I PLL

ERTY

TEST DRIVE READY
REZERO UNIT
REQUEST SENSE
FORMAT UNIT
REASSIGN BLOCKS
READ
WRITE
SEEK
INQUIRY DATA
FORMAT
MODE SELECT
RESERVE UNIT
RELEASE UNIT
MODE SENSE
RECEIVE DIAGNOSTIC
SEND DIAGNOSTIC

00
01
03
04
07
08
OA
OB
12

V
V
V
V
V
V
V
V

n
n
n
V(FD,CL,DLF}
n
V(LBA}
V(LBA}
V(LBA}
V(LBA}

n
n
n
V
n
n
n
n
n

n
n
V(RSB}
n
n
V(NOB}
V(NOB}
n
V(NB}

n
n
n
n
n
V
V
n
n

15
16
17
1A
1C
1D

V
V
V
V
V
V

n
n
n
n
n
n

n
n
n
n
n
n

V(PLL}
n
n
V(PLL}
n
n

n
n
n
n
n
n

READ LONG
WRITE LONG
READ DIF

E5
E6
E7

V
V
V

V(LBA}
V(LBA}
n

n
n
n

V(NOB}
V(NOB}
n

V
V
n

LEGEND:
V
Must be a valid parameter.
n
Not used (should be 0 for future compatibility).
LUN
Logical Unit Number of drives. 0 or 1 for WD1003-SCS.
LBA
Logical Block Address.
FD
Format Data bit.
CL
Complete List bit.
DLF
Defect List Format bits.
INT
Interleave factor.
NOB
Number Of Blocks.
RSB
Requested Sense Bytes.
NB
Number of Bytes.
PLL
Parameter Length List.
ERTY Error Retry bit.
GROUP 0 AND 7 COMMAND
DESCRIPTION BLOCK
The Command Description Block format used by the
15 Group 0 and 3 Group 7 commands is provided in
Figure 2.

Winchester Board Products

6-167

c......
o
o
w

en

()
CJ)

:e

c
.....

o
o
w

en
("')

BITS
BYTE

I

7

6

I

5

4

0

I

3

-1

2

I

1

I

0

OPERATION CODE

en

1

LOGICAL BLOCK ADDRESS (MSB) OR FORMAT
DATA/COMPLETE LIST/DEFECT LIST FORMAT

LUN

2

LOGICAL BLOCK ADDRESS

3

LOGICAL BLOCK ADDRESS (LSB) OR INTERLEAVE (MSB)

4

NUMBER OF BLOCKS, REQUESTED SENSE BYTES,
NUMBER OF BYTES, INTERLEAVE (LSB), OR PARAMETER LIST LENGTH

5

ERTY

I

0

I

0

0

I

0

I

0

I

0

I

0

FIGURE 2. GROUP 0 AND 7 COMMAND DESCRIPTION BLOCK
Operation Code

Number of Blocks

Bits 7-5 designates that the command is used in a
Group 0 or 7 operation.

Indicates the number of contiguous logical data
blocks to be transferred by an operation. When zero,
256 blocks are transferred. Any other value indicates
the number of blocks to be transferred.

Bits 4-0 identify the function of a command, e.g., Read
or Write, to be performed within Command Group 0
or 7.
LUN
Specifies the Logical Unit Number of the attached
drive. Must be 0 or 1.
Logical Block Address
Specifies the Logical Block Address where an operation is to begin.
Format Data, Complete List, Defect List Format
Used in conjunction with the Reassign Blocks and
Format Commands:
- Format Data. Bit 4 of byte 1.
- Complete List. Bit 3 of byte 1.
- Defect List. Bits 2, 1, and 0 of byte 1.

Requested Sense Bytes
The number of bytes indicates the length of data
allocated by the Host for the returned sense information. The count also determines the format of the
returned sense data. Sense data can be returned in
one of two supported sense byte formats: (1) standard Non-Extended Sense Byte format, and (2)
Extended Sense Byte format. A requested sense byte
count of zero results in a data transfer of four. The
requested count, but never more than eight sense
bytes, are sent on all other requested values.
Parameter List Length
The only valid length for proper operation is 30
(decimal). Zero represents a No-Operation condition.

Interleave (MSB) and (LSB)

Number of Bytes

The interleave factor is used by format commands.
The disk may be formatted at a 1:1 ratio. And the maximum interleave is equal to the sectors-per-track
minus one.

Indicates the data length allocated by the Host for
the Returned Sense data.

Byte 3 or 4 can be any interleave number from 0
through 28. If an interleave factor of 0 is used, the
WD1003-SCS uses a default interleave of 2.

6-168

ERTY
Disk error retry bit. When set, indicates a request for
a retry operation. (Used if retries are supported by a
specific command.)

Winchester Board Products

TABLE 6. SUMMARY OF GROUP 1 COMMANDS

COMMAND
READ CAPACITY
READ EXTENDED
WRITE EXTENDED
SEEK EXTENDED

:E

OP
CODE

LUN

LBA

NOB

PMI

ERTY

25
28
2A
2B

V
V
V
V

V
V
V
V

n

V

n

V
V

n
n
n

V
V
V

n

n
LUN
LBA

Must be a valid parameter.
Not used (should be 0 for future compatibility).
Logical Unit Number of drives 0 and 1.
Logical Block Address.

NOB
PMI
ERTY

o

en

Number Of Blocks.
Partial Medium Indicator bit.
Error Retry bit.

GROUP 1 COMMAND DESCRIPTION BLOCK
The Command Description Block format used by the
four Group 1 commands is provided in Figure 3.

BITS
BYTE

7

I

6

I

5

I

0

4

I

3

I

2

I

1

I

0

I

0

I

0

I

0

I

0

I

0

I

0

I

0

OPERATION CODE

I

LUN

1

0

I

0

2

LOGICAL BLOCK ADDRESS (MSB)

3

LOGICAL BLOCK ADDRESS

4

LOGICAL BLOCK ADDRESS

5

LOGICAL BLOCK ADDRESS (LSB)

6

0

I

0

I

0

I

0

I

0

I

0

7

NUMBER OF BLOCKS (MSB)

8

NUMBER OF BLOCKS (LSB) OR PMI

9

ERTY

I

0

I

0

I

0

I

0

I

0

FIGURE 3. GROUP 1 COMMAND DESCRIPTION BLOCK FORMAT
Operation Code

LUN

Bits 7-5 designates that the command is used in a
Group 1 operation.

Specifies the Logical Unit Number of the attached
drive. Must be a 0 or 1.

Bits 4-0 identify the function of a command e.g., Read
Extended, Write Extended, or Seek Extended to be
performed within Command Group 1.

Specifies the Logical Block Address where an operation is to begin.

Winchester Board Products

o
o
w

en

LEGEND:

V

c-"

Logical Block Address

6-169

:ec
...L

o
o

W
I

en
o
en

Number of Blocks

RETRY

Indicates the number of contiguous logical data
blocks to be transferred by an operation. When zero,
256 blocks are to be transferred. Any other value
indicates the number of blocks to be transferred.

Disk error retry bit. When set, indicates an error condition and a request for a retry operation. (Used if
retries are supported by a specific command.)

PMI

°

Partial Medium Indicator. Bit of byte 8 used in the
Read Capacity Command. Setting this bit to:

°=
1

=

Controller returns address of the last block on
the LUN device.
Controller returns the last block prior to a
cylinder boundary that follows the Block
Address given by the Host. For example, Block
Address results in the controller returning
Block Address 67 on a device with four heads
and is formatted with 17 sectors per track (512
bytes per sector).

°

TABLE 7. POSSIBLE COMMAND ERROR CODES
COMMAND

TEST DRIVE READY
REZERO UNIT
REQUEST SENSE
FORMAT UNIT
REASSIGN BLOCKS
READ
WRITE
SEEK
INQUIRY DATA
FORMAT
MODE SELECT
RESERVE UNIT
RELEASE UNIT
MODE SENSE
RECEIVE DIAGNOSTIC
SEND DIAGNOSTIC
READ CAPACITY
READ EXTEN DED
WRITE EXTENDED
SEEK EXTENDED
READ LONG
WRITE LONG
READ DIF

6-170

ERROR CODE

00,03,04,1 C,22
00,03,04,06,OA,1 C,21 ,22
NONE
00,03,04,1 A, 1B,1 C, 1D, 1E,22
00,03,04,1 A, 1B,1 C, 1D, 1E,22
00,03,04,06,OA,1 0,11,13,18,1 C,21 ,22,80
00,03,04,06,OA,1 0, 19,1C,21 ,22,80
00,03,04,OA,1 C,21 ,22
00,22
00,20,21,22
00,03,04,22
00,03,04,22
00,20,21,22
00,1 C,22,30,31 ,32,33,34,37
00,1 C,22,30,31 ,32,33,34,37
00,20,21,22
00,03,04,06,OA, 10, 11,13,18,19,1 C,21 ,22,80
00,03,04,06,OA,1 0,18,19,1 C,21 ,22,80
00,03,04,06,OA,1 C,21 ,22,80
00,03,04,06,OA,1 0,13,19,1 C,21 ,22,80
00,03,04,06,OA,1 0,13,19,1 C,21 ,22,80
1C,22

Winchester Board Products

TABLE 8. ERROR CODE DESCRIPTION
ERROR CODE*
(HEX)
00

ERROR NAME

=E

TYPE OF
ERROR

No Sense

c
......

DESCRIPTION
Indicates that there is no specific Sense Key information to report for a designated LUN. No error is
detected and the command is completed successfully.
Indicates write current had not occurred when WG
is de-asserted, or an SC is not asserted and a drive
is selected while WG is asserted.

03

Write Fault

Disk Drive

04

Drive Not
Ready

Disk Drive

Indicates the LUN address cannot be accessed. The
selected drive's DRDY is de-asserted. The motor of
the selected drive is not up to speed.

06

Track 0
Not Found

Disk Drive

This code is returned by the Rezero Unit Command.
Indicates TKOOO from the selected drive was not
asserted after the maximum number of steps (up to
1024) toward cylinder O.

OA

Disk Full

Operational

Insufficient medium (hard disk) capacity. Indicates the
specified address reached the file device's given range.

10

ID Error

Disk Drive

An ID CRC error.

11

Uncorrectable
Data Error

Disk Drive

Indicates an error in the data field is beyond the ECC's
correction capability. Data for the block in error is not
sent to the Host.

13

Data Address
Mark
Not Found

Disk Drive

Indicates header of a selected block is found, but its
Data Address Mark is not detected.

18

Correctable
Data Error

Disk Drive

Indicates an error in the data field is within the ECC's
correction capability and is corrected. The data block
is sent to the Host. This status serves as a warning
to the Host that a marginal condition may exist.

19

Bad Block

Operational

Indicates a formatted bad block is encountered.

1A

Bad DIF

Operational
or
Disk Drive

The Drive Information File cannot be read by the
Reassign Blocks or Format command with the Add To
DIF option selected.

1B

Cannot Read
Alternate Track
Information

Media

On all attempts to read the alternate address from the
bad track a read error occurred.

1C

Disk Not
Formatted
Correctly

Operational

This error can only occur on the first disk access after
an initial power up or a reset. Sector zero track zero
was read and found not to contain a Drive Information File.

1D

Address Of The
Defective Block
Too Large

Operational

Defective block address exceeds the size of the disk.

1E

No Alternates
Left

Operational

1. No alternate tracks were allocated and format has
been requested with Bad Track Mapping option only.
2. Not enough alternate tracks allocated to accommodate the number of bad blocks specified in the Drive
Information List.
3. No unused alternate tracks available for use during
a Reassign Blocks command.

Winchester Board Products

6-171

o
o

w

en
(")

en

TABLE 8. ERROR CODE DESCRIPTION (cont.)

=E
c

...t.

o
o

ERROR CODE·
(HEX)

w

TYPE OF
ERROR

ERROR NAME
Bad
Command

Command

Indicates an invalid Command Group, OP. Code,LUN,
Logic Block Address, ID, Interleave, Block Length, or
Partial Medium Indicator.

21

Illegal Block
Address

Operational

Not a valid address for a Logical Block or Parameter.

22

Unit Attention

30

Bad ROM

Diagnostics

Indicates the ROM checksum does not match the
calculated checksum.

31

Bad RAM

Diagnostics

Indicates the external RAM failed.

32

Bad Winchester

Diagnostics

Indicates the WD2010-05 Disk Controller failed.

33

Bad Address
Generation

Diagnostics

Address generation has failed. Indicates a WD1100-19
error.

34

Bad Instruction
Set

Diagnostics

Indicates an invalid instruction set from the 8085
microprocessor.

36

Good Pass Of
Diagnostics

Diagnostics

Diagnostics completed successfully.

Bad Bus

Diagnostics

en

(')

en

DESCRIPTION

20

37
+80

Occurs only once after reset. Indicates the removable
medium (hard disk) may have been changed or the
WD1003·SCS has been reset (by a Bus Device Reset
message or a "hard" Reset condition) since the last
command was issued to the LUN. When the error con·
dition is detected, the requested command is not performed. The Unit Attention Sense Key is reported to
all Initiators that subsequently issue a command to
the LUN. This Sense Key is cleared for the next command from the same Initiator.

Valid Address

Indicates an internal bus hardware error.
A valid address bit, indicating the Block Address fields
contain valid information.

"Error codes returned reflect only one error although multiple errors may exist. In this case, the error considered
to most severe will be reported.
+ 80 is ORed with the error code: e.g. 37

6-172

= B7

Winchester Board Products

DIGITAL

WESTERN
COR

P

0

RAT

ION

WD1003-WA2 Winchester/Floppy Disk Controller
ADVANCED INFORMATION
FEATURES

•

AT COMPATIBLE WINCHESTER AND FLOPPY
CONTROLLER

•

CONTROLS UP TO TWO WINCHESTER DRIVES
(ST506/ST412, 16 R/W HEADS EACH, 2048
CYLINDERS)

•

CONTROLS UP TO TWO FLOPPY DISK DRIVES:
DOUBLE·SIDED
DOUBLE DENSITY (360kB, 250kbs, MFM)
QUAD DENSITY (1.2MB, 500kbs, MFM)
FOUR DATA RATES (500kbs, 300kbs, 250kbs,
and 125kbs)
SUPPORTS 360 AND 300 RPM SPINDLE
SPEED

•

WD2010A·05 WINCHESTER DISK CONTROLLER

DESCRIPTION

The WD1003·WA2 is a cost reduced version of the
WD1002·WA2. The WD1003-WA2 is an IBM Person·
nal Computer AT bus compatible Winchester/Floppy
disk controller designed to interface up to two Win·
chester and up to two floppy disk drives. The board
permits the concurrent operation of one floppy and

Winchester Board Products

•

8-BIT, BI·DIRECTIONAL BUS HOST INTERFACE
FOR CONTROL AND STATUS TRANSFERS

•

HIGH·SPEED, 16-BIT PIO DATA TRANSFERS

•

32·BIT ECC OR WINCHESTER ERROR DETEC·
TION AND CORRECTION, CRC FOR ID FIELDS

•

DIAGNOSTIC MODE FOR ERROR CHECKING

•

WRITE PRECOMPENSATION LOGIC

•

WD10C20 DATA SEPARATOR AND WRITE
PRECOMPENSATION DEVICE

•

WD11COOA·22 (RMAC) AND WD16C92 FLOPPY
DISK READ/WRITE CONTROLLER (FRWC)
REDUCE POWER CONSUMPTION AND COMPO·
NENT COUNT

•

ALLOWS CONCURRENT OPERATION OF ONE
FLOPPY AND ONE WINCHESTER DRIVE

one fixed disk drive. The Winchester drive interface
is compatible to the Seagate Technology ST506 stan·
dard interface for 5Mbs hard disk drives. The floppy
disk drive interface supports 1.2MB, 360 RPM drives
as well as 360kB (SA450) drives. The WD1003·WA2
includes all necessary receivers and drivers to allow
direct connection to the drive(s}.

6-173

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WESTERN
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P

0

DIGITAL

RAT

ION

WD1003·WAH Winchester Disk Controller
ADVANCED INFORMATION
FEATURES

DESCRIPTION

•

AT COMPATIBLE WINCHESTER CONTROLLER

•

CONTROLS UP TO TWO WINCHESTER DRIVES
(ST506/ST412, 16 R/W HEADS EACH, 2048
CYLINDERS)

•

8·BIT, BI·DIRECTIONAL BUS HOST INTERFACE

•

16·BIT, HIGH SPEED PIO DATA TRANSFERS

The WD1003-WAH is a cost reduced version of the
WD1002-WAH. The WD1003·WAH is an IBM Personnal Computer AT bus compatible Winchester con·
troller board designed to interlace up to two drives.
The drive interlace is based upon the Seagate
Technology ST506. The drives need not be of the
same capacity or configuration. All necessary
receivers and drivers are included on the board to
allow direct connection to the drive(s).

•

32·BIT ECC FOR WI NCH ESTER ERROR DETEC·
TION AND CORRECTION

•

MULTIPLE SECTOR READIWRITE COMMANDS
(MAY CROSS HEAD AND CYLINDER
BOUNDARIES

•

IMPLIED AND BUFFERED SEEK COMMANDS

•

READ/WRITE
COMMANDS

•

PROGRAMMABLE FORMAT AND ERROR
RECOVERY ALGORITHMS

•

WD10C20 DATA SEPARATOR AND WRITE
PRECOMPENSATION

•

WD2010A-05 WINCHESTER DISK CONTROLLER

DIAGNOSTIC AND

Winchester Board Products

VERIFY

6-175

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WESTERN
COR

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DIGITAL
A

T

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WD2401' Buffer Management Tape Controller
FEATURES

•

40-PIN DIP

•

NMOS TECHNOLOGY

•

SINGLE

•

6 MHZ CLOCK RATE

•

SUPPORTS 1/4" STREAMING TAPE UNITS

•

SASI HOST INTERFACE

•

CONTROLS TAPE MOTION

•

STREAMING TAPE COMMAND TRANSLATION

+ 5V

POWER SUPPLY

•

SELF TEST DIAGNOSTICS

•

AUTOMATIC RETRIES ON ALL ERRORS

DESCRIPTION

The WD2401 Buffer Management Tape Controller
(BMTC) is a complete control processor for streaming tape controllers. This device executes all basic
functions for 1/4" streaming tape backup of disk
images or logical files. WD2401 firmware programs
handle all aspects of SASI Host command interpretation, tape motion control, and buffer management of
the WD24C02 ReadIWrite Formatter. Execution of
error recovery routines provide complete backup with
minimal Host intervention. The error recovery routines
attempt a maximum of 16 retries to recover most error
conditions.

Tape Drive Control/er Products

BSY
XTAL1
XTAL2
BRST
PU
INT
PO

vee
ROY
PR
RG
SPYEN
ST
BYTIN
BFROVFL
RGAP
BREa
EPT3
Ell"f2
EPTl
EPTO
Vee
NC
CLRSSY
MSG
I/O
C/O

RE
NC
WE
ALE
DO
01
02
03
04
05
06
07
Vss
PIN DESIGNATION

7-1

PIN DESCRIPTION

:ec

N

SIG.
PIN

o
.....

1

BSY

J:a,

SIGNAL NAME

FUNCTION

1/0

BUSY

I

Indicates start of SASI Command phase.

2

XTAL1

CRYSTAL1

I

External crystal for timing purposes.

3

XTAL2

CRYSTAL2

I

External crystal for timing purposes.

4

BRST

RESET

I

Initializes the internal logic of the BMTC. Starts
execution of diagnostic TEST routine.

5

PU

PULL UP

I

Tied to external one ohm pull·up resistor.

6

INT

INTERRUPT

I

Indicates the WD24C02 has started to read or write
a gap.

7

PD
RE

PULL DOWN
READ ENABLE

I

Tied to external 330 ohm pull-down resistor.
Asserted to read data from the Host or WD24C02.

9
10

-

NOT USED
WRITE ENABLE

11

ALE

ADDRESS
LATCH
ENABLE

12
thru
19

DO
thru
D7

DATA 0
thru
DATA 7

8

7-2

SIGNAL
MNEMONIC

WE

0
0
0
0

1/0

Left open.
Indicates valid data during bus write.
Strobes address into external device. Occurs once
each instruction cycle.
8-bit, tri-state, bi-directional bus. DO is the least
significant bit (LSB). D7 is the most significant bit
~B). Data is written on or read from the bus using
WE or RE strobes, respectively. Also contains the
address and data during an exter~access to or
from port devices. ALE, RE, and WE controls the
external access.

20

Vss

GROUND

21

cin

CONTROUDATA

0

Indicates whether the current byte on the SASI bus
is a control or data byte.

22

1/0

INPUTIOUTPUT

0

Indicates the direction of the current byte on the
SASI bus.

23

MSG

MESSAGE

0

Indicates a Data Message Out phase on the SASI
bus.

24

CLRBSY

CLEAR BUSY

0

Indicates release of SASI bus.

25

NC

Not Connected

-

GROUND

Tape Drive Controller Products

PIN DESCRIPTION (CONT' D.)
SIG.
PIN
26

SIGNAL
MNEMONIC

=E

SIGNAL NAME

110

c

N

FUNCTION

,J:::a.

o
.....

+ 5V power supply.

+5V

27

Vcc
EPTO

ENABLE PORT 0

28

EPT1

0

S!!9bes output data to an external latch when (5
(I/O) is asserted. Enables exte.,!!lal latch to input
data to the WD2401 when I (I/O) is asserted.

ENABLE PORT 1

0

Strobes drive control data from the WD2401 into
an external register. Refer to Table 1 for the definitions of these control data bits.

ENABLE PORT 2

0

Strobes drive control data from the WD2401 into
an external register. Refer to Table 2 for the definitions of these control data bits.

EPT3

ENABLE PORT 3

0

Assertion of this signal enables sending of the tape
drive status to the WD2401. Refer to Table 3 for the
definitions of these status bits.

31

BREQ

BUS REQUEST

0

Assertion of this signal allows the WD2401 to
request use of external bus. The WD2401 controls
external bus when RDY is asserted.

32

RGAP

RAW GAP

I

Assertion of this signal indicates the occurance of
the gap in the incoming data stream.

33

BFROVFL

BUFFER
OVERFLOW

I

Assertion indicates completion of a transfer of a
block of data between the Host and WD24C02.

34

BYTIN

BYTE IN

I

Assertion of this signal indicates the Host port on
the tape controller board is ready to transfer a byte.

35

ST

START HOST
DATA
TRANSFER

0

Asserted for Host data transfers.

36

SPYEN

ENABLE SPY
MODE

0

Asserted for spying on the SASI bus.
(Currently not implemented.)

37

RG

READ GATE

0

Asserted to switch external data separator from
reference to the incoming data bits.

38

PR

PRIME

0

Assertion of this signal initializes the WD24C02 for
data transfers to the Host.

39

RDY

READY

I

Assertion of this signal indicates the WD2401 controls external bus.

40

Vcc

+5V

29

30

-EPT2

--

Tape Drive Controller Products

---

+ 5V power supply.

7-3

TABLE 1. DRIVE CONTROL BIT DEFINITIONS (EPT1)

=e

BIT

~

0

Track bit 0 (LSB)

1

Track bit 1

2

Track bit 2

3

Track bit 3 (MSB)

4

Head Current

5

Prime spy mode

6

Spare

7

Spare'

c
N

....o

FUNCTION

NOTE: This device specifies up to 16 tracks (Track bits 0-3)
TABLE 2. DRIVE CONTROL BITS (EPT2)
BIT

FUNCTION

0

Write enable

1

Erase enable

2

Reverse direction

3

Start tape motion

4

Drive select 0

5

Threshold

6

Spare

7

SASI enable

TABLE 3. TAPE DRIVE STATUS BIT DEFINITIONS (EPT3)
BIT

7-4

FUNCTION

0

Upper tape hole

1

Lower tape hole

2

Drive selected

3

Cartridge inserted

4

Tape write enabled

5

Tachometer pulses

6

Abort command (From Host)

7

No data on tape

Tape Drive Controller Products

ARCHITECTURE

The WD2401 consists of the 1/0 interface, control
logic, 4KB ROM, 256 bytes RAM, clock, and program
counter. Figure 1 illustrates the architecture of the
WD2401.

The 256 bytes of internal RAM serve as a scratch-pad
memory for the WD2401.

Transmission and reception of data, control, and
status is the responsibility of the 1/0 interface.

The a-bit CPU follows the standard architecture of
most popular CPUs.

The control logic receives, decodes, and executes
instructions received from the 110 interface or other
internal logic.

Timing signals for the WD2401 internal logic are
derived from the clock circuitry. The WD24C02 clock
requires connection to an external crystal with a fundamental frequency of 6 MHz.

The 4KB ROM contains firmware programs. These
programs enable the control logic to handle all

aspects of SASI Host command interpretation, tape
motion control, and buffer management of WD24C02.

CONTROL
LOGIC

4KB
ROM

I/O
INTERFACE

256 BYTES
RAM

8 BIT

CPU

CLOCK
6 MHz

FIGURE 1_ WD2401 BUFFER MANAGEMENT TAPE CONTROLLER
SIMPLIFIED BLOCK DIAGRAM

Tape Drive Controller Products

7-5

WD2401 COMMAND SET
The WD2401 command set implements all the basic
functions to backup Winchester disk images or
logical files. WD2401 commands control the basic
functions of tape positioning, data transfer, and
operational modes.
Command protocol follows the SASI standard. Command descriptor blocks (CDB) consist of six bytes and
contain the following information:
Byte 0 contains the command group in bits 7
through 5 and the command op code in bits 4
through O.
Byte 1 contains the tape drive's Logical Unit
Number (LUN bits 7 through 5), and the five high
order bits of the Tape Block Number (HIGH bits
4 through 0).

HIGH along with Byte 2 (MIDDLE) and Byte 3
(LOW) make up the Tape Block Number used only
by the Read Tape Block command.
Byte 4 contains the COUNT field used by the Read
File Mark and Write File Mark commands.
Byte 5 contains the option bits.
Figure 2 illustrates the CDB format. Tables 4 and 5
summarizes command parameters and option bits,
respectively. Table 6 lists error codes and their
definitions.

BITS
BYTES

7

I

6

0
1

I

5

I

4

3

I

2

I

1

I

0

OPCODE
LUN

HIGH

2

MIDDLE

3

LOW

4

COUNT

5

OPTION BITS See Table 5
FIGURE 2. COMMAND DESCRIPTOR BLOCK FORMAT

7-6

Tape Drive Controller Products

TABLE 4. COMMAND SUMMARY

COMMAND

OP
COMMAND TYPE CODE

LUN

HIGH

MIDDLE

LOW

COUNT

OPTIONS

REWIND TO
BEGINNING OF TAPE

TAPE
POSITION

11

0

0

0

0

0

0

READ FILE MARKS

TAPE
POSITION

24

0

0

0

0

V

T

ERASE TAPE

TAPE
POSITION

26

0

0

0

0

0

0

RETENSION TAPE

TAPE
POSITION

27

D

0

0

0

0

0

FIND END OF DATA

TAPE
POSITION

28

0

0

0

0

0

0

TEST DRIVE READY

OPERATION
MODE

00

0

0

0

0

0

0

READ SENSE BYTES

DATA
TRANSFER

03

0

0

0

0

0

C

READ BLOCK BUFFER

DATA
TRANSFER

10

0

0

0

0

0

P

WRITE BLOCK
BUFFER

DATA
TRANSFER

OF

0

0

0

0

0

P

READ TAPE BLOCKS

DATA
TRANSFER

21

0

V

V

V

V

R,T,F

WRITE TAPE BLOCKS

DATA
TRANSFER

22

0

0

0

0

V

T,U,H

WRITE FILE MARK

DATA
TRANSFER

23

0

0

0

0

V

T,H

READ EXTENDED
STATUS

DATA
TRANSFER

25

0

0

0

0

0

C

BACKUP DISK IMAGE

OPERATION
MODE

40

0

0

0

0

0

T,U,H

PERFORM
CONTROLLER
DIAGNOSTICS

OPERATION
MODE

E4

0

0

0

0

0

0

DEFINE TAPE
PARAMETERS

OPERATION
MODE

OC

0

0

0

0

0

0

EXIT Spy MODE

OPERATION
MODE

41

0

0

0

0

0

U

Tape Drive Controller Products

7-7

:eC
~

g

LEGEND
D
V
T
C
P

Target drive number
Valid parameter
Threshold
Clear internal counters
Page number. External block buffer contains sixteen pages of
memory. Each page of memeory is 512 bytes.

R
F
U
H

Reposition option
Flush bit
Underrun
High current

a

Must be

a

TABLE 5. OPTION BITS SUMMARY
BITS
COMMAND

7

6

5

4

3

2

1

0

WRITE BLOCK BUFFER

0

0

0

0

P

P

P

P

READ BLOCK BUFFER

0

0

0

0

P

P

P

P

READ TAPE BLOCKS

R

F

T

0

0

0

0

0

READ FILE MARKS

0

0

T

0

0

0

0

0

WRITE TAPE BLOCKS

0

0

T

H

U

0

0

0

WRITE FILE MARKS

0

0

T

H

0

0

0

0

FIND END OF DATA

0

0

T

0

0

0

0

0

READ EXTENDED STATUS

0

0

0

0

0

C

0

0

READ SENSE BYTES

0

0

0

0

0

C

0

0

NOTE: Bits 0 through 7 in byte 5 of command block are set to zero for all other commands.
LEGEND
P Page number. External block buffer contains sixteen pages of memory. Each page of memory is 512 bytes.
R Reposition. 0 = disable. 1 = enable repositioning. Enabling repositioning requires a tape block address
in the HIGH, MIDDLE, and LOW bit positions and starts a flush.
F Flush. 1 = flush data blocks in the buffers before reading more blocks. 0 = disable flushing.
T Threshold. 0 = disable. 1 = enables threshold at read head. Eliminates data of questionable quality.
H High current. 0
disable. 1
enables increased write current for high coercivity tape, e.g. DC600A.
U Underrun. 0
stop tape motion on an underrun. 1
maintain streaming on an underrun.
C Clear internal Read CRC, Write CRC, and Underrun/Overrun counters when set to 1.

=

7-8

=

=

=

Tape Drive Controller Products

TABLE 6. ERROR CODES
HEX
CODE
04
20
30
31

DEFINITION
Drive not ready. Drive could not be selected.
Illegal command in COB.
WD2401 RAM failure.
ROM checksum error.

35

Maximum number of retries exceeded.

36
37

End of tape.
Addressed tape block not found.
Write protected.

38
39
3A

File mark not detected.
End of physical media.

3B
3C

End of recorded data.
Illegal tape structure. Missing blocks.

TAPE POSITIONING COMMANDS
Tape positioning commands (Rewind to Beginning of
Tape, Erase and Retension only) issued to the BMTC
are completed immediately, i.e., the Host issues the
command, the WD2401 stores the command in internal RAM, then the WD2401 releases the SASI bus. The
WD2401 remains connected to the SASI bus until
completion of the Read File Marks command. The
Host issues a Test Drive Ready command to the
WD2401 to determine if the positioning command has
been completed. An error condition is generated for
an uncompleted drive positioning command. Normal
completion of a drive positioning command is
assumed if no error is presented.
REWIND TO BEGINNING OF TAPE
(OP CODE 11)
This command causes the tape drive to rewind the
tape from the tape's current position to the beginning of tape (BOT) position.

ERASE TAPE
(OP CODE 26)
This command erases and retensions the entire tape.
RETENSION TAPE
(OP CODE 27)
This command causes the tape drive to rewind the
tape to the BOT positon. Next, the tape drive winds
the tape to the end of tape (EOl) position and rewinds
to the BOT position.
FIND END OF DATA
(OP CODE 28)
This command searches for the last recorded block
on tape.
DATA TRANSFER COMMANDS

READ FILE MARKS
(OP CODE 24)
The Read Fi Ie Marks command moves the tape forward to a specified file marker. This command allows
processing of multiple disk images or logical files as
individual data sets.

Tape Drive Controller Products

7-9

READ SENSE BYTES
(OP CODE 03)

WRITE FILE MARK
(OP CODE 23)

This command returns one status byte. The block
number with the error follows the status byte. A no
error condition returns the block number of the last
read or written block of data. The WD2401 returns four
bytes of data to the Host. These bytes are:

This command writes a file mark block at the current
tape postion. A file mark denotes the end of a com·
plete disk image data set or the end of a logical file.

7

6

5

4

3

2

1

0

BYTE 0

B

0

T

T

E

E

E

E

BYTE 1

D

D

D

HIGH

BYTE 2

MIDDLE

BYTE 3

LOW

READ EXTENDED STATUS
(OP CODE 25)

The Read Extended Status command allows the user
access to extensive error status information. This
command sends 20 bytes of data to the Host.
The contents of these bytes are:
7

I6 I5 I4 I3 I2 I1

BYTES 1 .

0

NUMBER OF REPOSITIONS

NOTE: B represents the block address valid bit.
1 = block address is valid. 0 = invalid.
T represents the error type.
E represents the error code.
D represents the drive number in error.

BYTES 2·

3

NUMBER OF UNDERRUNS

BYTES 4·

5

NUMBER OF OVERRUNS

BYTES 6·

7

NUMBER OF READ CRC
ERRORS

WRITE BLOCK BUFFER
(OP CODE OF)

BYTES 8·

9

NUMBER OF WRITE CRC
ERRORS

This command allows the Host to perform memory
diagnostics on the internal RAM. The controller must
be in an idle state before this command is issued.

BYTE 10

MOST RECENT ERROR CODE

BYTES 11· 13

MOST RECENT ERROR BLOCK

BYTES 14· 16

NEXT BLOCK TO BE READ OR
WRITTEN

BYTE 17

NUMBER OF BLOCKS
BUFFERED IN EXTERNAL RAM

BYTE 18

MAJOR VERSION OF FIRMWARE

BYTE 19

MINOR VERSION OF FIRMWARE

READ BLOCK BUFFER
(OP CODE 10)

This command allows the Host to perform memory
diagnostics on the internal RAM. The controller must
be in an idle state before this command can be
issued.
READ TAPE BLOCKS
(OP CODE 21)

The Read Tape Blocks command restores the data
from a streaming backup tape cartridge. This com·
mand restores both disk images and logical files. All
read data transfers must pass the data into the Host
memory.
WRITE TAPE BLOCKS
(OP CODE 22)

The Write Tape Blocks command writes data to tape
from Host memory.

7-10

Tape Drive Controller Products

OPERATIONAL MODE COMMANDS
DEFINE TAPE PARAMETERS
{OP CODE ~C)

The Host issues this command to pass hardware
parameters to the WD24C02. The Buffer Management
Tape Controller passes these parameters to the
WD24C02 in three bytes. These bytes are:

71

6

I5 I4 I3 I2 I1 I0

BYTE 0

NUMBER OF TRACKS PER DRIVE

BYTE 1

NUMBER OF RETRIES
PER COMMAND

BYTE 2

BLOCKS TO BUFFER BEFORE
STARTING TAPE

BACKUP DISK IMAGE
(OP CODE 40)

This command arms the tape controller and slaves
it to the disk controller. The WD24C02 ReadlWrite Formatter intercepts data on the SASI Bus and writes
the data to the tape. Interception of the data on the
SASI Bus is the spy mode. The WD24C02 ReadlWrite
Formatter throttles the disk controller by regulating
the ACK Signal from the Host.
PERFORM CONTROLLER DIAGNOSTICS
(OP CODE E4)

This command causes the WD2401 to execute
diagnostics and to detect errors. The user determines
the exact error code by issuing the Read Sense
Command.

EXIT SPY MODE
(OP CODE 41)

This command ends spy mode operation for short and
long terms. Normal completion of a disk image dump
or catastrophic errors require that streaming opera·
tions stop. Short term spy exits allow the Host to
intermix disk operations with other disks.
TEST DRIVE READY
(OP CODE 00)

The user issues this command to determine completion of a tape motion command. Completion of this
command with no error indicates normal execution
of the previously issued tape motion command.
Simultaneous execution of this command and a tape
motion command results in an error condition. Issuing a Read Sense Byte determines the exact state
of the tape motion command or the cause of the error
conditon.

Tape Drive Controller Products

7-11

ELECTRICAL CHARACTERISTICS

=E

C

N
~

.....

ABSOLUTE MAXIMUM RATINGS
Operating Temperature .................................................. OOC (3~F) to 70°C (158°F)
Storage Temperature ............................................. -65°C (-85°F) to + 150°C (302°F)
Volatage on any Pin with respect to ground .......................................... -0.5V to + 7V
Power Dissipation .................................................................... 1.5 Watts

NOTE:
Maximum limits indicate where permanent device damage occurs. Continuous operation at these limits is not
intended and should be limited to those conditions specified in the DC Operating Characteristics.

DC Operating Characteristics TA

SYMBOL

= OOC (32°F) to 70°C (158°F); Vss = OV, Vcc = 5V

CHARACTERISTICS

MIN

MAX

UNITS

+

10%

CONDITIONS

V 1L

Input Low Voltage (All except
BRST, XTAL 1, and XTAL2)

-0.5

0.8

V

V 1L1

Input Low Voltage (BRST,
XTAL1, and XTAL2)

-0.5

0.6

V

V 1H

Input High Voltage (All
except BRST, XTAL1, and
XTAL2)

2.0

5.0

V

V 1H1

Input High Voltage (BRST,
XTAL1, and XTAL2)

3.8

5.0

V

VOL

Output Low Voltage
(Bus)

0.45

V

IOL

= 2.0 rnA

V OL1

Oute.!:!!.. Low Voltage
(RE,WE,ALE)

0.45

V

IOL

= 1.8 rnA

V OL2

Output Low Voltage
(All other Outputs)

0.45

V

IOL

= 1.6 rnA

V OH

Output High Voltage
(Bus)

2.4

V

IOH

= -400 /-LA

VOH1

Oute.!:!!.. High Voltage
(RE,WE,and ALE)

2.4

V

IOH

= -100/-LA

VOH2

Output High Voltage
(All other Outputs)

2.4

V

IOH

= -40/-LA

7-12

Tape Drive Controller Products

DC Electrical Characteristics (Cont'd.) TA

= OOC (32°F) to 70°C (158°F); Vee = 5V

± 10%; Vss

MAX

UNITS

Input Leakage Current (ROY
and INn

±10

",A

IIL1

Input Leakage Current (Pins
21 through 38)

-500

",A

Vss + 0.45!S
VIN!S Vee

ILO

Output Leakage Current (Bus
- High Impedance State,
BSy)

±10

",A

Vss + 0.45!S
VIN!S Vee

Vee

Total Supply Current

80

rnA

SYMBOL
IlL

CHARACTERISTICS

AC CHARACTERISTICS TA

MIN

= OV
:E
c
N

CONDITIONS
Vss!S VIN ::; Vee

~

o
......

= OOC (32°F) to 70°C (158°F); Vss = OV, Vee = +5V

+

10%

~~-t-LL-~-----tCY----------·~1
ALE

J

------.L

1--1_ _ _ _ _~I

INSTRUCTION FETCH FROM EXTERNAL MEMORY TIMING
INSTRUCTION FETCH FROM EXTERNAL MEMORY TIMING
SYMBOL

CHARACTERISTICS

TYP

UNITS

tey

Cycle Time

2.5

",sec

tLL

ALE Pulse Width

413

nsec

tLA

Address Hold from ALE

126

nsec

tAL

Address Setup to ALE

223

nsec

tAD1

Address Setup to Data

1030

nsec

NOTES:

CONDITIONS (NOTE 1)
NOTE 2

NOTE 3

1. Control output load capacitance equals 80 pF. Bus load capacitance equals 150 pF.
2. Assumes 50% duty cycle on XTAL1 and XTAL2.
3. Bus high impedance load equals 20 pF.

Tape Drive Controller Products

7-13

--.J ~tLAFC
ALE

--.J~---"'"

L

WR - - - - - - - - - ,

ALE

J

~
R5------.....;
tAFC
BUS

j

tec

~

I

I
=1

~

I FLOATING

t

~

L

f.-

tCA

tOR
-F-LO-A-T-IN-G--

L:===tA02~tRO
WRITE TO EXTERNAL DATA MEMORY
SYMBOL
t LAFC

CHARACTERISTICS
ALE to Control
(WE, RE)

tcc

Control Pulse Width
(WE, RE)

tCA

Control (WE, RE)
to ALE

tow
two
tAW

NOTE:

7-14

TYP

425

READ FROM EXTERNAL DATA MEMORY
MIN

SYMBOL
t LAFC

nsec

CHARACTERISTICS
ALE to Control
(RE, WE)

tcc

Control Pulse Width
(RE, WE)

1050
126

nsec

tCA

Control to ALE
(RE, WE)

Data Setup before
WE

883

nsec

t AFC

Address float to RE

tOR

Data Hold RE

Data Hold after
WE

116

Address Setup to
WE

683

nsec

nsec
nsec

Control output load capacitance equals
80 pF. Bus output load capacitance equals
150 pF.

t RO
t A02

NOTE:

-

-

RD to Data In

Address setup to
read data

TYP

MIN

425

nsec

1050

nsec

126
293
220
746
1530

nsec
nsec
nsec
nsec
nsec

Control output load capacitance equals
80 pF. Bus output load capacitance equals
150 pF.

Tape Drive Controller Products

PACKAGE DIAGRAM

I---

I" '"

A

A"...

:ec
N

I

2060 ± .020

,~4~E(:::::::::C::::::~~rp'N"D
020

~g~~

,---------------.1], ~;:

075 ± .025
1.90 ± .64

~! !
1

.100 ± .010
2.54 ± .64

~

o
.....

-r

52.32 ± .51

645 ± 030

1638 ± .76

J
30 ± .08

J~~.150

± .020

'

3.81 ± .51
018 ± .003
46 ± .08

40 LEAD PLASTIC PL

Tape Drive Controller Products

7-15

7-16

Tape Drive Controller Products

WESTERN

DIGITAL

CORPORAT

ON

WD2404-DSM
Tape Data Separator Module
FEATURES

•

FABRICATED USING STATE-OF-THE-ART
SURFACE MOUNT TECHNOLOGY

•

SMALL FORM FACTOR (2" X 2.5")

•

INDUSTRY STANDARD OIC-36 INTERFACE

•

CONFORMS TO OIC-36 ISV, BIT JITTER AND
ASYMMETRY SPECIFICATIONS

•

COMPLETELY SELF-ADJUSTING

•

± 10% CAPTURE RANGE

• + 5V

and

+ 12V OPERATIONS

DESCRIPTION

The WD2404-DSM is a completely self-contained, self
adjusting, state-of-the-art design implemented in
Surface Mount Technology. The tape data separator
module provides a generic interface to a tape controller implementing a OIC-36 drive interface and
OIC-24 recording format for 114" streaming tape.
It requires a high speed 14.4 MHz clock and provides
7.2 MHz and 3.6 MHz clocks for system interface.
The tape data separator module consists of the
following basic functional blocks.
•

DATA SEPARATION LOGIC

•

CHARGE PUMP CIRCUITS

•

LOOP COMPENSATION CIRCUIT

•

VCO CIRCUITS

Tape Drive Controller Products

An optional delay line is included on the module
which can be disabled by the user.
There are absolutely no adjustments on the
WD2404-DSM. The module looks at Raw Data Pulse
(RDP) from the drive at Read Gate (RG) time and
generates Expect to Receive Sync (ERS) and Read
Gap (RGAP). It separates data and clock and
generates RCLK and RD signals. It also detects the
absence of data (Erased Tape) by asserting signal
NDTA. The WD2404-DSM also has the capability to
narrow the bit cell window during Read After Write
(RAW) operation for additional data integrity.
The module is easy to integrate and is fabricated
using Surface Mount Technology for high reliability.
The module requires + 5V and + 12V supply.

7-17

,,-.

-RESET

+12V

ClK (14.4 MHz)

RDP

1

PUP

RG
ERS
WEN

20
PIN

DIS
CONN.

2
4
C
0
3

7.2 MClK
WClK (3.6MHz)
DlYSEl
RGAP

RD
RClK

CHARGE
PUMP
CKT.

PDN

I

lOOP
CaMp.
CKT.

....:::!£

560NS
DTA
DlDTA

20 PIN
DIP

10

0

I~

VCO
CKT.

VCO

I

I

NOTA
,---+5V
_+12V
_GNO

--- ..

TAPE DATA SEPARATOR BLOCK DIAGRAM

PIN NO.

SIGNAL

SIGNAL FUNCTION

1
2
3
4
5

RG
CLK
7.2 MCLK
RDP
DLYSEL

6
7
8

RGAP
WCLK
DTA

9
10
11
12
13
14
15
16
17,19
18
20

RESET
DLDTA
ERS

READ GATE
14.4 MHz CLOCK
7.2 MHz CLOCK
RAW DATA PULSE
DELAY SELECT
O-EXTERNAL
1-INTERNAL
READ GAP
WRITE CLOCK 3.6 MHz
DATA FOR DELAY LINE
APPLICATION
RESET
EXTERNAL DELAYED DATA
EXPECT TO RECEIVE SYNC
RESERVED
NO DATA DETECTED
READ DATA (SYNCHRONIZED)
WRITE ENABLE
READ CLOCK (FOR CLOCKING RD)
DC GROUND
+5V DC
+ 12V DC

7-18

N/C
NDTA
RD
WEN
RCLK
GND
VCC
+12V

1/0
I
I

0
I

I

0
0
0
I
I

0
0
0
I

0

Tape Drive Controller Products

SIGNAL

FUNCTIONAL

DESCRIPTION

RG

READ GATE

Asserted whenever the tape controller is ready to read data from the
drive also asserted during tape write for read after write function.

CLK

CLOCK

14.4 MHz TTL clock all tape related timings are derived from this high
speed clock.

7.2 MCLK

7.2 MCLK

Divide by two clock for WD3600 tape controller.

RDP

RAW DATA PULSE

Incoming data pulse from OIC·36 drive after 220/330Q termination. This
signal should meet the min/max pulse width/period requirements of
OIC·36 specs.

DLYSEL

DELAY SELECT

This signal selects the internal 24C03 digital delay or external delay thru
delay line default (line floating) state is digital delay connected to GND
for delay line selection.

RGAP

READ GAP

Whenever a consecutive string of recorded one's (1's) are detected (min
32) this line is asserted and will stay asserted during the entire gap time
minimum OIC·24 gap is 125 bits.

WCLK

WRITE CLOCK

This clock is four times the bit rate of tape data transfer (divide by four
clock for WD24C02).

DTA

DATA

Data for delay line application (not to be used externally).

RESET

RESET

Master reset used to synchronize internal circuits or WD24C03.

DLDTA

EXTERNAL
DELAYED DATA

Data from delay line. (Not to be used externally).

ERS

EXPECT TO
RECEIVE SYNC

This signal is asserted by the module when a valid OIC·24 gap is verified
and the data separator is locked in a phase mode assertion of this
indicates the imminent occurence of sync mark shortly.

NDTA

NO DATA

This signal is asserted when illegal GCR pattern is encountered erased
tape will constitute illegal GCR pattern.

RD

READ DATA

True vinary data separated from clock read data is synchronized with
read clock (RCLK).

WEN

WRITE ENABLE

If asserted during a write operation this narrows the bit cell window for
read after write operation providing additional data integrity.

RCLK

READ CLOCK

Read Clock synchronized with seperated data. Data to be clocked with
rising edge of the clock.

--

-GND

GROUND

Power supply ground + 5V & 12V return.

vce

vcc

+ 5V from power supply.

+12V

+12V

+ 12V from power supply.

Tape Drive Controller Products

7-19

7-20

Tape Drive Controller Products

WESTERN

DIGITAL

CORPORATION

WD24C02 Read/Write Formatter
Advance Information
FEATURES

•

40-PIN DUAL IN-LINE PACKAGE GATE ARRAY
DEVICE

•

SINGLE +5V POWER SUPPLY

•

SUPPORTS QIC-24 REV. D TAPE FORMAT

•

READ-AFTER-WRITE VERIFICATION

•

SUPPORTS AN EXTERNAL 8 KB (16 BLOCKS)
BLOCK BUFFER

•
•
•
•

•

INTERFACES TO AN EXTERNAL BUFFER
MANAGER (E.G., WD2401)
DIRECT INTERFACE TO DATA SEPARATOR
LOGIC
HANDLES DMA REQUEST AND ACKNOWLEDGE
HANDSHAKE FOR HOST DATA TRANSFERS
BUS CONTROL AND A MULIPLEXED ADDRESS
AND DATA BUS FOR MICROPROCESSOR INTERFACE
COMMAND AND STATUS REGISTERS

REQ
ACK
INT
CLKOUT
MR
RE
WE
AD?
AD6
AD5
AD4
AD3
AD2
AD1

ADO
BRQ
RDY
WCLK
ALE
GND

1

3
4

5
6
7

8
9
10
11

12

13
14

15
16

17
18
19
20

PIN DESIGNATION

DESCRIPTION

The WD24C02 is a multifunctional gate array device.
This device performs QIC·24 read and write formatting with read-atter-write verification. (QIC is an
acronym for Quarter-Inch Compatibility). The
WD24C02 is controller by a Buffer Management Tape
Controller (WD2401) or other external microprocessor
programmed for buffer management of tape data.

bus, when required, to compensate for disk latencies.
The WD2402 also maintains the buffer addresses
(lower 9 bits) for Host or device access.

The WD24C02 DMA request and acknowledge signals
control the transfer of read and write data between
the Host and an external block buffer. (The block buffer is an external 8K byte random access memory.This
memory is divided into 16 pages. Each page is 512
bytes in length.) These signals throttle the SASI

The WD24C02 runs at a 3.6 MHz clock rate and provides a real time clock of 90 KHz for the tape drive
interface. External data separator logic directly interfaces with the WD24C02.

Tape Drive Controller Products

The Status Register represnts the current status of
the WD24C02 and is read by the buffer manager. All
read and write functions are selected by writing a
command in the Command Register.

7-21

==
C
N

SIG.
PIN

~

SIGNAL
MNEMONIC

SIGNAL
NAME

110
DESCRIPTION

1

REQ

DMA REQUEST

I

Assertion of this signal indicates the Host is ready
to access the external block buffer for a read or write.

2

ACK

DMA
ACKNOWLEDGE

0

Assertion of this signal indicates to the requesting
device that the address is available to the external
block buffer for a read or write cycle.

3

INT

INTERRUPT

0

Assertion of this signal indicates to the Host the start
of a read or write gap.

4

CLKOUT

OUTPUT CLOCK

0

Real time clock for external circuitry.

I

Assertion initializes the WD24C02.

(')

o
N

5

MR

MASTER RESET

* 6

-RE

READ ENABLE

110

* 7

WE

Bi-directional, tri-state line. Assertion as an input
writes data into the WD24C02 internal register. Assertion as an output indicates the WD24C02 is writing
data to the external block buffer.

WRITE ENABLE

110

Bi-directional, tri-state line. Assertion as an input
writes data into the WD24C02 internal registers.
Assertion as an output indicates the WD24C02 is
writing data to the external block buffer.

8
thru
15

AD7
thru
ADO

MULTIPLEXED
ADDRESS AND
DATA
BUS

110

Eight-bit, bi-directional, multiplexed data and address
bus. Addresses are input only. The bi-directional data
lines transfer command and status information.

16

BRQ

BUS REQUEST

I

Assertion indicates a request for access to the
WD24C02 internal registers.

17

RDY

READY

0

Assertion indicates to the requesting device that the
bus is available. At least one access can be made
every 11.111sec. DMA requests are not acknowledged
during this time.

18

WCLK

WRITE CLOCK

I

Internal clock for write data transfers and other internal timing purposes.

19

ALE

ADDRESS
LATCH
ENABLE

I

Assertion of this signal latches the address from the
multiplexed address and data bus.

20

GND

GROUND

21
thru
33

BFAO
thru
BFA12

BUFFER
ADDRESS
BUS

0

Address bus for external buffer RAM. BFAO is the
least significant bit (LSB).

34

BFOFL

BUFFER
OVERFLOW

0

Assertion of this signal indicates to the BMTC that
the 512 byte external RAM buffer is full. The page
pointer requires updating for the next data transfer.

35

WD-

TAPE WRITE
DATA-

0

Run length limited (RLL) encoded data.

36

WD+

TAPE WRITE
DATA +

0

Complementary data.

7-22

Ground.

Tape Drive Controller Products

SIG.
PIN

37
38

39
40

SIGNAL
MNEMONIC

RD

SIGNAL
NAME

1/0
DESCRIPTION

TAPE READ
DATA

I

RLL encoded data (from Data Separator).

EXPECT TO
RECEIVE
SYNCHRONIZATION

I

Assertion of this signal indicates to the read
sequencer the imminent occurrence of the syn·
chronization character.

RCLK

READ CLOCK

I

Extracted clock from RAW DATA PULSE (RDP).

vcc

vcc

--

ERS

--

Tape Drive Controller Products

+ 5V + 5% power supply.

7-23

7-24

Tape Drive Controller Products

WESTERN
COR

P

0

DIGITAL
o

RAT

N

:E

....c
o

WD1036R-SHD Streaming Tape Controller

CAl

en

:p

en

FEATURES

DOCUMENT SCOPE

•

SASI 8-BIT BI-DiRECTIONAL BUS HOST
INTERFACE

•

QIC-36 1/4-INCH STREAMING TAPE
DRIVE

This document is intended to provide the reader with
an overview of the WD1036R-SHD, for a detailed
understanding it will be necessary to refer to the
following documents:

•

CON FORMS TO QIC-24 FORMAT
SPECIFICATIONS

•

READ-AFTER-WRITE VERIFICATION

•

EXTENSIVE ERROR RECOVERY ABILITY

•

ON-BOARD 8K BYTE BUFFER

•

SUPPORTS TAPE DRIVES WITH A
720-K BIT DATA TRANSFER RATE

::I:

SASI™
QIC-24, QIC-36
WD1036R-SHD OEM manual document
number 79-000028
WD2401 BMTC Data sheet
WD24C02 RIW Formatter Data sheet
SASI is a trademark of Shugart Inc.
DESCRIPTION

The WD1036R-SHD is a stand-alone Streaming Tape
Controller board that interfaces to a single 114-inch
QIC-36 streaming tape drive. The WD1036R-8HD uses
industry standard QIC-24 ReadlWrite formatting.

•

90-IPS TAPE SPEED

•

START/STOP OR STREAMING
OPERATION

•

5.5 IN. X 8 IN. PCB FORM FACTOR

•

ADJUSTMENT FREE DATA
SEPARATOR

The WD1036R-SHD communicates with the Winchester disk drive controller (possibly a WD1002-SHD)
through the Host controlled SASI bus. All data, status
information, and commands are transferred via this
bus.
Figure 1 shows a typical system configuration .

- -~

\
I

.
HOST
COMPUTER

A

~

I
1\

."

r

"

WINCHESTER
DISK DRIVE
CONTROLLER

.DISK
DRIVE

ST-506

--

-

DISK
DRIVE

A

HOST
ADAPTER

V
1\

SASI BUS

~

to

\
I

V"

WD1036R-SHD

CONTROLLER

QIC-36
INTERFACE

- -..

1/4-IN
STREAMING
TAPE DRIVE

FIGURE 1. TYPICAL SYSTEM CONFIGURATION

Tape Drive Controller Products

7-25

C

ARCHITECTURE

WD24C02 ReadlWrite Formatter, an 8K byte RAM,
Data Separator, SASI interface, tape drive interface,
and misc. buffers and latches.

The WD1036R-SHD has three on-board connectors,
the power connector P1, Host connector J1, and tape
drive connector J2. Figure 2 is a block diagram
illustrating the major areas of the WD1036R-SHD.
These sections consist of a WD2401 Buffer
ManagerfTape Controller,

TWD+
TWD-

CONTROl

TAP[

DRIVE
INTERFACE
(QIC-36)

BUFFER
1Gl./
TAPE

CONTLR

PORT 0

1102401

PORT 1
PORT Z
PORT 3

RCLIt

ROF
+5VOC

CLOCKS

RG

FIGURE 2. WD1036R-SHD STREAMING TAPE CONTROLLER, BLOCK DIAGRAM

WD2401 BMTC

The WD2401-BMTC consists of an 8-bit microcontroller, 4K bytes of ROM, containing Western Digital
proprietary firmware, and 256 bytes of RAM. The
WD2401-BMTC is responsible for performing the
following functions:

•

Manage the RAM buffer and furnish the four highorder address bits (page number) to the WD24C02.

•

Initialize the Page Pointer and Command Registers
in the WD24C02 following a power up reset, or a
reset (RSl) from the initiator.

•

Receive an interpret SASI commands and pass
certain commands to the WD24C02 ReadlWrite
Formatter.

•

Perform a diagnostic routine to test the
microprocessor, RAM, and ROM at power-up or
reset from the initiator.

•

Act as the handshake controller with both SASI
interface hardware and the tape drive, and control all tape drive motion.

•

Perform error handling and maintain an error log
in it's internal RAM.

•

Periodically poll the status and sense signals from
the tape drive, then determine and initiate the
appropriate action.

7-26

Tape Drive Controller Products

WD24C02 RIW Formatter

Buffer RAM

Write formatter logic in the WD24C02 reads data from
the RAM buffer, formats it to QIC-24 requirements,
and serializes the data to be written on the tape.

The 8K-byte RAM is treated as 16 blocks of 512 bytes
each, which correspond to the block size on tape. The
four high-order address lines select the block. Bidirectional data lines are connected to SASI Bus latches and to the WD24C02 data lines. The buffer is
addressed by the WD24C02 while the WD2401 controls the reading and writing of the buffer.

Read formatter logic accepts serial data from Data
Separator logic, deserializes it, decodes GCR-coded
data, and transfers data to the RAM Buffer. This logic
also detects File Marks, strips out the gap, sync
characters, and block address, and performs the CRC
Check, generating a CRC error flag when an error
occurs. Read formatter logic also performs the Read
Check during a write operation.
The WD24C02 detects error status and passes it on
to the WD2401, which maintains an error log in its
internal RAM.
The WD24C02 maintains the nine low-order address
bits at the RAM Buffer for either Host or drive access.
The four high-order address bits - block select - are
maintained by the WD2401 but supplied to the RAM
by the WD24C02.

Data Separator
The Data Separator recognizes the data as it is read
from the tape, removes the clock pulses, and transfers
the data (RD) to the WD24C02. Handshaking with the
WD2401 is through RG and RGAP signals which
define the beginning of data. The WD2404-DSM is
initialized at power-up or by the initiator issuing
RST.
The WD2404-DSM is a self contained module requiring no adjustments. It is installed as a piggy-back card
by mating the rear entry connector J1 on the module
to J3 on the WD1036R-SHD.

Buffer arbitration is managed so that the Host does
not run over a restricted block buffer. A bad block is
not transferred to the Host during a restore operation.

Tape Drive Controller Products

7-27

SPECIFICATIONS
HOST INTERFACE

Type
Cable length (Daisy Chained)
Cable connector
Termination
Addressing

SASI
15 ft. (4.6m) max.
50 pin Berg 65610·150 or Molex 10·89·1501
Socketed 220/330 ohm resistor pack
Jumper selectable (1 through 8)
Default
2

=

DRIVE INTERFACE

Type
Cable length
Cable connector
Termination
Recording method
CRC polynomial
Cartridge Capacity

QIC·36 Rev. B Standard
10 ft. (3 m) max.
50 pin Berg 65610-150 or Molex 10·89·1501
220 ohms to + 5 volts
330 ohms to ground
QIC·24, NRZI, GCR (0,2) at 10,000 frpi.
X16 + X12 + X5 + 1
1/4 in. 9 track
DC300A
30 M Byte
DC300XL = 45 M Byte
DC600A = 60 M Byte

=

DATA SEPARATOR

Acquisition time
Capture range
Bit jitter tolerance
Asymmetry tolerance

<64 bit times
±25%
See Figure 3
See Figure 3

POWER

Cable connector
Voltage
Current
Ripple

4 pin, right angle Molex 15·24-4041
AMP 641737-1
+5 VDC ±5%
+12 VDC ±5%
1.5A max. 1.2A typo @ 5 volts
50ma max. 20ma typo @ 12 volts
0.1 volt

DIMENSIONS

Length
Width
Height (max. including board, components,
and leads)

8 inches
5.50 inches
0.5 inch

ENVIRONMENTAL

Ambient temperature
Relative humidity
Altitude
Air flow
MTBF
MTTR

7-28

OOC (32°F) to 55°C (131°F)
10% to 90% non-condensing
o to 10,000 ft (3048 m)
150 linear ftlmin @ 0.25 inches from the component
surface
10,000 hrs.
30 min.

Tape Drive Controller Products

30

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15

20

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30

35

FIGURE 3. BIT JITIER (%)

HOST INTERFACE
The SASI interface is a daisy-chained bus interconnecting the Host computer, the WD1036R-SHD, Winchester drive controller, and other peripheral or
peripheral controllers up to a total of eight. The
WD1036R-SHD is connected to the bus through a 50pin flat cable which may be as long as 15 feet. The
connector on the WD1036R-SHD is a Berg 65610-150
or Molex 10-89-1501.

Tape Drive Controller Products

The bus is terminated at the WD1036R-SHD using a
socketed resistor pack to facilitate daisy-chaining.
The WD1036R-SHD is strapped at the factory to respond to SASI address 2 but may be changed by moving a jumper to the desired address.

7-29

TABLE 1. HOST INTERFACE CONNECTOR (J1) PIN DESCRIPTION
SIG.
GND.

SIG.
PIN

MNEMONIC

SIGNAL
NAME

1

2

DO

thru
15

thru
16

thru
D7

DATA 0
thru
DATA 7

17
thru
33

18
thru
34

ABORT

ABORT

35

36

BSY

37

38

ACK

39

40

RST

41

42

MSG

43

44

45

46

1/0

FUNCTION

I/O Eight-bit, bi-directional, tri-state, bus used to transfer
commands, status, and data between the Host and
Controller and other devices on the bus.
I

Optional hardware ABORT signal. Pin selected by
movable jumper. Allows the Host to reset the
WD1036R-SHD without effecting other devices on
the bus.

o

Indicates to the Host that the WD1036R-8HD is busy
executing a command and is unable to accept
another command. The trailing edge acknowledges
receipt of SEL and indicates that the transaction
is completed.

I

ACK is an input signal when used with REQ as
a handshake signal for byte transfer. Both leading
and trailing edges are used.

I

When asserted for at least 100 nsec, RST places
the WD1036R-SHD in its initial power-up state.

MESSAGE

o

Indicates the end of the present transaction.

SEL

SELECT

I

When asserted, gives control of the bus to the
selected device address.

C/D

CONTROU
DATA

o

As an output signal, C/D along with I/O and MSG
signals the Host the type of bus transfer that is
expected by the WD1036R-SHD.
C/D - 0
Control
- 1 = Data
Control is defined as a: command, status or
message.

ACKNOWLEDGE

=

47

48

REQ

REQUEST

o

REQ is an output signal when used with ACK as
a handshake signal for data transfer between the
Host and WD1036R-SHD. Both leading and trailing
edges are used.

49

50

I/O

INPUT/
OUTPUT

o

As an output singall/O defines the direction of
the transfer:
1 = output from the Host
o = input to the Host

7-30

Tape Drive Controller Products

TAPE DRIVE INTERFACE
The WD1036R-SHD interfaces to the tape drive
through a 50-pin flat cable no more than 10 feet in
length. The interface comprises 25 lines, three of
which are reserved for future use. The 50-pin edge
connector on the WD1036R-SHD mates with a Berg
65610-150, Molex 10-89-1501, or equivalent.

The lines are terminated with 220 ohms to + 5 volts
and 330 ohms to ground. All signals to the WD1036RSHD are terminated at the WD1036R-SHD and must
be able to drive two TTL loads plus the termination.

SIG.
PIN

1

2

SIGNAL
NAME

MNEMONIC

en
c

FUNCTION

GO

0

REV

REVERSE

0

TR3

TRACK
SELECT 3

0

TR2

TRACK
SELECT 2

0

GO controls the capstan servo. GO starts thEL.!mJe
motion sequences in the direction specified by REV.
REV controls the direction of the capstan servo.
When asserted with GO, the tape motion is in the
reverse direction.
Track Select bit 3. TR3 through TRO is the binary
coded track number used by the drive to select a
designated track. (MSB)
Track Select bit 2. TR3 through TRO is the binary
coded track number used by the drive to select a
designated track.
Track Select bit 1. TR3 through TRO is the binary
coded track number used by the drive to select a
designated track.
Track Select bit O. TR3 through TRO is the binary
coded track number used by the drive to select a
designated track. (LSB)
RST is a minimum pulse of 13 usec. It starts the initialization routine and recalibration of the head to its
reference position.

GO

3

4

5

6

7

8

9

10

TR1

TRACK
SELECT 1

0

11

12

TRO

TRACK
SELECT 0

0

13

14

RST

RESET

0

15
17
19
21

16
18
20
22

DSO

23

24

HC

25

26

-

-RDP

RESERVED
RESERVED
RESERVED
DRIVE
SELECT 0

0

HIGH
CURRENT

0

READ DATA
PULSE

I

Tape Drive Controller Products

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TABLE 2. TAPE DRIVE INTERFACE CONNECTOR (J2) PIN DESCRIPTION
SIG.
GND.

::E
c

When asserted D~ermits basic tape drive operations to proceed. DSO enables the transfer of control
signals: RDP CIN USF TCH EEN. The drive acknowledges receipt of DSO by sending SLD.
When asserted, enables operation with DC GOOA tape
cartridges. Refer to ANSC Project 671 Unrecorded
Magnetic Tape Cartridge for Information Interchange,
0.250 inch (6.30mm) 6400-10000 flux-reversals per inch
(252-394 frpmm).
Serial-bit data read from tape to the WD1036R-SHD.
RDP ...!Lpresent when data passes the read head
and DSO is asserted.

7-31

TABLE 2. TAPE DRIVE INTERFACE CONNECTOR (J2) PIN DESCRIPTION
SIG.
GND.

SIG.
PIN

1/0

FUNCTION

27

28

UTH

UPPER TAPE
POSITION
HOLE

I

UTH and LTH encode information having to do with
tape position as follows:

29

30

LTH

LOWER TAPE
POSITION
HOLE

I

UTH
LTH
MEANING
Beginning of Tape
1
1
1
End of Tape
0
Warning Zone
1
0
Recording Zone
0
0
The Recording Zone is between the Load Point and the
Early Warning hole if BOT or EOT has been detected
since the last cartridge insertion (CIN). Otherwise 0 0
means the tape position is not known.

31

32

SLD

DRIVE
SELECTED

I

33

34

CIN

CARTRIDGE
IN

I

35

36

USF

UNSAFE

I

Tape drive acknowledgement to the WD1036R·SHD or
receipt of the DSO.
CIN is asserted when a tape cartridge i§.J.n place
and the WD1036R·SHD asserts DSO, and GO.
The drive asserts USF when the File Protect Plug is
not in the safe position on the cartridge and the
WD1036R·SHD asserts DSO. This state permits data
to be written and erased.

MNEMONIC

SIGNAL
NAME

-

37

38

TCH

TACH PULSE

I

TCH is present while tape is moving.

39

40

WDA·

WRITE DATA·

0

WRITE DATA+

Data to be written on tape, enabled while WEN is
asserted. System is optimized to record GCR data at
a nominal density of 10,000 frpi.
The inverse of WDA·.
Sets a percentage-qualifying voltage threshold for Read
Data. Eliminates data of marginal quality read from
tape.

41

42

43

44

WDA+
THO

THRESHOLD

0
0

45

46

HSD

HIGH SPEED

0

47

48

WEN

WRITE
ENABLE

0

49

50

EEN

ERASE
ENABLE

0

=

Asserted
90 ips tape speed. WD1036R·SHD never
de·asserts HSD.
When asserted, enables drive to write data.
Tape is erased the full width of the erase head when
the WD1036R·SHD selects track 0, and asserts DSO
and EEN.

WD103SR-SHD COMMANDS
To facilitate intergration of the WD1036R-8HD into the
system, the protocol and command structure is the
same as that of the WD1002-SHD Disk Controller.
The commands can be classified into three groups:
Tape positioning, data transfer and control mode.
Each command is characterized by a 6-byte Com·
mand Description Block. Table 3 is a summary of the
commands and Table 4 represents the Command
Description Block.

7-32

Tape Drive Controller Products

TABLE 3. COMMAND SUMMARY

COMMAND

OP
CODE

LUN

BLOCK
NO.

11
24
26
27
28

D
D
D
D
D

0
0
0
0
0

03
OF
10
21
22
23
25

D
0
0
D
D
D
D

0
0
0

0
0
0

V

V
V
V

00

D
D
0

0
0
0

COUNT

OPTIONS

0

0
T
0
0
T

Tape Position
Rewind To BOT
Read Fi Ie Marks
Erase Tape
Retension Tape
Find End of Data

V
0
0
0

Data Transfer
Read
Write
Read
Read
Write
Write
Read

Sense Bytes
Block Buffer
Block Buffer
Tape Blocks
Tapes Blocks
File Mark
Extended Status

0
0
0

0

C
P
P
RTF
UTH
TH
C

0
0
0

0
0
0

Operation Mode
Test Drive Ready
Define Tape Parameters
Diagnostics

OC
E4

TABLE 4. COMMAND DESCRIPTION BLOCK
BIT
BYTE

7

I

6

I

5

I

0
1

4

I

3

I

2

I

1

I

0

OPERATION CODE
LOGICAL UNIT
NUMBER

BITS 20 THRU 16 OF
TAPE BLOCK ADDRESS

I

2

BITS 15 THRU 8 OF TAPE BLOCK ADDRESS

3

BITS 7 THRU 0 OF TAPE BLOCK ADDRESS

4

COUNT FIELD

5

OPTION BITS (see table 5.)

Operation Code

Bits 7-5 designates a command class of 0, 1,2, or 7.
Bits 4-0 identifies the function of the command, e.g., Erase, Rentension, etc.

Logical Unit No.

Logical unit number of the target tape drive.

Tape Block Address

Used by the Read Tape Block command to locate the first block to be read within a file.

Count Field

Used by the Read File Mark command to locate the file that is to be read by a Read Tape
Block command. Used by a Write File Mark command to control the number of File Marks
to be written. Used by a ReadlWrite Tape Blocks command to control the number of blocks
to be read or written.

Option Bits

See Table 5.

Tape Drive Controller Products

7-33

TABLE 5. OPTION BITS

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BIT
COMMAND

7

6

5

4

3

2

1

0

Read Sense Bytes
Find End of Data
Write Block Buffer
Read Block Buffer
Read Tape Blocks
Read File Marks
Write Tape Blocks
Write File Marks
Read Extended Status
All other commands

0
0
0
0
R
0
0
0
0
0

0
0
0
0
F
0
0
0
0
0

0
T
0
0
T
T
T
T
0
0

0
0
0
0
0
0
H
H
0
0

0
0
P
P
0
0
U
0
0
0

C
0
P
P
0
0
0
0
C
0

0
0
P
P
0
0
0
0
0
0

0
0
P
P
0
0
0
0
0
0

LEGEND:

P - Page Number.

External block number contains sixteen 512·byte pages of memory.

R - Reposition.

o =Disable
1

= Enable. Reading starts at the tape block specified in the Command
Description Block. The Reposition option also initiates a Flush option.

F - Flush.

o = Disable
1 = Flush data blocks from buffers before reading more blocks.

U - Underrun.

o = Stop tape

T - Threshold

o = Disable

motion on underrun.
1 = Continue streaming on underrun.
1

H - High Current

o = Disable
1

C - Clear Inernal
Counters

7-34

=Enable threshold at Read Head.
= Increase Write Current for high-coercivity tape. e.g., DC600A

o = Disable
1 = Clear Read/Write CRC errors and Under/Overrun counter.

Tape Drive Controller Products

WESTERN
COR

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WD10368-WX2 Streaming Tape Controller

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FEATURES

•

3.9 X 8.1" IBM PCIXT/AT FORM FACTOR

•

EXTENSIVE ERROR RECOVERY WITH AUTOMATIC RETRIES

•

SUPPORTS ONE 1/4" BASIC TAPE DRIVE (OIC-36)

•

DMA TRANSFER CAPABILITY

•

INDUSTRY STANDARD OIC·24 RECORDING
FORMAT

•

SUPPORTS 90 IPS STREAMING OPERATION

•

•

ON BOARD WD24C02 READIWRITE FORMAT·
TER CHIP

APPLICATION SOFTWARE TO RUN UNDER IBM
PC DOS 2.0 TO EMULATE IBM'S BACKUP/
RESTORE COMMANDS

•

READ·AFTER-WRITE VERIFICATION

•

FILE-BY-FILE BACKUP/RESTORE CAPABILITY

DESCRIPTION

HARDWARE ARCHITECTURE

The WD1036S-WX2 is a single board streaming tape
controller for IBM PC/ATIXT and compatible computers. This controller supports one 1/4" cartridge
tape drive with OIC-36 interface. (OIC is an acronym
for Quarter-Inch Compatibility).

The WD1036S-WX2 is based on the WD24C02
ReadlWrite Formatter device. There are three support
modules to the WD24C02. One module buffers Host
bus Signals, decodes and translates Host bus commands into board control Signals, and builds
WD24C02 commands. Another module separates the
drive data into clocks and read data and provides
signals that indicate tape data gap times. The last
module is responsible for the drive status and control. Figure 1 is a hardware block diagram of the
WD1036S-WX2.

The two utilities TBACKUP and TRESTORE provided
with the controller enable file backup and restore from
Winchester to tape and vice versa on the IBM system
bus. These utilities require a minimum of 128KB of
memory, but achieve a higher performance with
256KB or more. The memory size determines the maximum number of blocks that can be transferred by
a single command during backup and restore operations. The command set also allows searching of
records on tape.
The recording format conforms to the OIC-24 standard. The WD1036S-WX2 performs read-after-write
verification and rewrites the data block, as required,
in case of an error. Similarly, it repositions and rereads
a record for read errors. A 16-bit cyclical redundancy
check (CRG) ensures detection of an error. The
WD1036S-WX2 automatically attempts to reread or
rewrite data up to 16 times on errors.
Application software is supplied which emulates
selective file backup and restore functions provided
by IBM PC DOS 2.0.

Tape Drive Controller Products

The PC interface and Buffer module contains bus
transceivers, address decoding circuitry, control
signal receivers, and the WD1100-18 gate array. The
WD1100-18 translates Host bus commands and
generates control Signals for the WD24C02. The
WD1100-18 also serves as a two byte DMA buffer
between the Host and WD24C02.
The Data Separation module uses a phase lock loop
that tracks incoming data pulses, generates a read
clock and read data.
The Drive Control and Status module contains a set
of registers that are loaded via Host bus commands.
These registers transmit control bits to the drive
through high current drivers. This module also buffers status lines from the drive. Issuing a Read Status
command to the WD1036S-WX2 places the status
information including the cartridge-in status unto the
Host bus.

7-35

~

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SOFTWARE ARCHITECTURE

....-----TBACKUP and TRESTORE utilities

The two stand·alone utilities TBACKUP and
TRESTORE are designed to run under IBM PC DOS
version 2.0 or later. These utilities will operate with
a 128KB memory system. But a higher performance
is achieved with 256KB or larger memory systems.

"Core" standard module - - - - - - ,

APPLICATION
LEVEL

Figure 2 illustrates the architecture of the TBACKUP
and TRESTORE programs. The Application Level is
written to interface with a common module called
Core. The Core is a high level interface between the
application code and the Tape Access Module. The
Core isolates the application program from the low
level operations of tape positioning, tape drive inter·
face timing characteristics, and data formatting con·
siderations. Thus, an application program is simplified
by not dealing with these low level operations.

COMMAND
PROCESSOR

BUFFER

MANAGER

I

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DISK
ACCESS
MODULE

TAPE
ACCESS
MODULE

The Core module contains two functional com·
ponents, a Command Processor and a Buffer
Manager. These components are compatible with
machines that differ from the IBM PC. Compatibility
is achieved by coding these functions in C and per·
forming no hardware or operating system dependent
operations in the Core.

)

DOS calls
Direct 1/0 or
DMA transfer to
WD1036S-WX2

The Application level module uses the high level com·
mand set described in the section titled Software
Commands.

FIGURE 2.
WD1036S-WX2 SOFTWARE BLOCK DIAGRAM

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TR0.3. HC. HSO. RST

E RS
o T
LE

~

I

..l

RESET

I

NJ.3

DRC'·3

f,~~
vT I

I
INTOO-6

BUSOIR

B
U
S

'5'"CR

I

i

I

I
I
I

DATA SEPARATION
MODULE

i

DRIVE CONTROL AND STATUS MODULE

Figure 1. WD1036S-WX2 HARDWARE BLOCK DIAGRAM

7-36

Tape Drive Controller Products

SPECIFICATIONS
HOST INTERFACE

Type
Cable length
Addressing
Interrupt Channel
DMA Channel Request
Memory Requirements

IBM PC/AT, PC/XT
Connects directly to the Host mother board with a
62-Pin card edge connector.
Jumper selectable (300 through 3FO) Default = 330
Jumper selectable (IRQ2 through IRQ7) Default
IRQ3
Jumper selectable (DRQ1,2 and 3) Default DRQ1.
12BK Bytes min. 256K bytes or more are
recommended.

DRIVE INTERFACE

Type
Cable length
Cable connector
Termination
Recording method
CRG polynomial
Cartridge Capacity

Tape speed

QIC-36 Rev. B Standard
10 ft. (3 m) max.
50 pin 3 M 3425-6050 at the WD1036S-WX2
3 M 3415-001 at the drive
220 ohms to + 5 volts
330 ohms to ground
QIC-24, NRZI, GCR (0,2) at
10,000 frpi.
x16 + x12 + x5 + 1
1/4 in. 9 track
DC300A = 30 M Byte
DC300XL = 45 M Byte
DC600A = 60 M Byte
90 inches per second

DATA SEPARATOR

Acquisition time
Capture range
Bit jitter tolerance
Asymmetry tolerance

< 64

Bit times.
±25%
See Figure 3
See Figure 3

POWER

Voltage
Current
Ripple

+5 VDC ±5%
+ 12 VDC ±5%
1A max. BOOma typo @ 5 volts
30 rna max. 20ma typo @ 12 volts
0.1 volt

DIMENSIONS

Length
Width
Height (max including board,
components, and leads).

Tape Drive Controller Products

B.1 inches
3.9 inches
0.5 inch

7-37

:ec
......

o

CAl

0')

en

:e:><
N

ENVIRONMENTAL

Ambient temperature
Relative humidity
Altitude
Air flow

OOC (32°F) TO 55°C (131°F)
10% to 90% non-condensing
o to 10,000 ft (3048 m)
150 linear ft/min @ 0.25 inches from the component surface
10,000 Hrs.
30 min.

MTBF
MTTR

30

25
N

:z:

0

....

«(

20

~
>
0

LAJ
LAJ
0...
Vl

15

Vl

::»

0

LoJ

:z:

....z
....
Vl
c(

RECOVERED

c(

z

10

5

o

o

5

10

15

20

25

30

35

FIGURE 3. BIT JITTER %

7-38

Tape Drive Controller Products

CONNECTORS
The WD1036S-WX2 has two on-board connectors for
interfacing to an IBM PC/ATIXf or compatible Host
and one 114" QIC-36 cartridge tape drive.
P1 -

J1 -

The Host connects to this 62-pin card edge
connector. Pins A1 through A31 are on the
component side of the board and pins B1
through B31 are on the artwork side. The
signals applied to this connector are
described in Table 1.

The Tape Drive connects to this 50-pin connector via a cable of no more than 10 feet (3m)
in length. All incoming signals are terminated
with a 220 ohm resistor to + 5V and 330 ohm
resistor to ground. The signals applied to this
connector are described in Table 2.

TABLE 1. HOST INTERFACE CONNECTOR (P1) PIN DESCRIPTION
PIN
NUMBER

MNEMONIC

A1

SIGNAL NAME

1/0

FUNCTION

I/O

8·Bit, tri-state, bi-directional bus for data and status
communication between the WD1036S-WX2 and
Host.

NOT CONNECTED

A2
thru
A9

07
thru
DO

DATA 7
thru
DATA 0

A10

I/O CH ROY

I/O CHANNEL
READY

I

This tri-state signal adds one Wait State to allow for
WD24C02 related commands.

A11

AEN

ADDRESS
ENABLE

I

AEN is asserted by the Host DMA controller.
Asserted, the DMA Controller has control of the
address, control, and data buses. Only memory I/O
operations can occur during assertion of AEN.

I

Address bus.

I

Initializes the WD1036S-WX2 during power-up or low
line voltage condition.

0

The WD1036S-WX2 asserts IRQ2 to interrupt the Host
upon the completion of a block operation. IRQ2
through IRQ7 is jumper selectable.

0

WD1036S-WX2 asserts DRQ2 to inform the DMA Controller that data is available for transfer in either direction. DRQ1,2 and 3 are jumper selectable.

NOT CONNECTED

A12
thru
A21
A22
thru
A31

A9
thru
AO

ADDRESS BIT 9
thru
ADDRESS BIT 0

B1

GND

GROUND

B2

RST

RESET DRV

B3

+5V

+5 VOLTS

B4

IRQ2

INTERRUPT
REQUEST
LEVEL 2

DRQ2

DMA REQUEST
CHANNEL 2

B5
B6

NOT CONNECTED

B7
B8
B9

+12V

+ 12 VOLTS

B10

GND

GROUND

B11
B12

NOT CONNECTED

NOT CONNECTED

Tape Drive Controller Products

7-39

TABLE 1. HOST INTERFACE CONNECTOR (P1) PIN DESCRIPTION (cont.)
PIN
NUMBER

1/0

FUNCTION

813

lOW

1/0 WRITE

I

814

lOR

110 READ

I

The Host or DMA controller asserts lOW when a
data or control byte is to be written to the
WD1036S-WX2.
The Host or DMA controller asserts lOR when a
data or status byte is to be read from the
WD1036S-WX2.

815

-DACK3

DMA
ACKNOWLEDGE
CHANNEL 3

I

The DMA Controller asserts DACK3 in response to
DRQ3 sent by the WD1036S-WX2. DACK1, 2 and "3
are jumper selectable.

816

DRQ3

0

WD1036S-WX2 asserts DRQ3 to inform the DMA Controller that data is available for transfer in either direction. DRQ1,2 and 3 are jumper selectable.

81?

-DACK1

DMA
ACKNOWLEDGE
CHANNEL 1

I

The DMA controller asserts DACK1 in response to
DRQ1 sent by the WD1036S-WX2. DACK1,2 and "3
are jumper selectable.

818

DRQ1

DMA REQUEST
CHANNEL 1

0

WD1036S-WX2 asserts DRQ1 to inform the DMA controller that data is available for transfer in either direc·
tion. DRQ1, 2 and 3 are jumper selectable.

820

CLK

SYSTEM CLOCK

I

System clock with a period of 210 nsec and 33% duty
cycle.

821

IRQ?

INTERRUPT
REQUEST
LEVEL?

0

The WD1036S-WX2 asserts IRQ? to interrupt the Host
upon the completion of a block. IRQ2 through IRQ?
is jumper selectable.

822

IRQ6

INTERRUPT
REQUEST
LEVEL 6

0

The WD1036S-WX2 asserts IRQ6 to interrupt the Host
upon the completion of a block. IRQ2 through IRQ?
is jumper selectable.

823

IRQ5

INTERRUPT
REQUEST
LEVEL 5

0

The WD1036S-WX2 asserts IRQ5 to interrupt the Host
upon the completion of a block. IRQ2 through IRQ?
is jumper selectable.

824

IRQ4

INTERRUPT
REQUEST
LEVEL 4

0

The WD1036S-WX2 asserts IRQ4 to interrupt the Host
upon the completion of a block. IRQ2 through IRQ?
is jumper selectable.

825

IRQ3

INTERRUPT
REQUEST
LEVEL 3

0

The WD1036S-WX2 asserts IRQ3 to interrupt the Host
upon the completion of a block. IRQ2 through IRQ?
is jumper selectable.

826

DACK2

DMA
ACKNOWLEDGE
CHANNEL 2

I

The DMA controller asserts DACK2 in response to
DRQ1 sent by the WD1036S-WX2. DACK1, 2 and "3
are jumper selectable.

MNEMONIC

819

NOT CONNECTED
+5V

+5VOLTS

GND

GROUND

830
831

7-40

DMA REQUEST
CHANNEL 3

NOT CONNECTED

82?
828
829

SIGNAL NAME

NOT CONNECTED

Tape Drive Control/er Products

TABLE 2. DRIVE CONNECTOR (J1) PIN DESCRIPTION
SIG.
GND.

SIG.
PIN

MNEMONIC

SIGNAL
NAME

110

FUNCTION

2

GO

GO

o

Assertion starts tape motion. The state of REV
determines the direction of tape motion.

3

4

REV

REVERSE

o

Assertion causes the tape drive to move tape in the
reverse direction. De-assertion causes the tape drive
to move tape in the forward direction. The WD1036SWX2 must assert GO to enable REV.

5

6

TR3

TRACK

o

Track Select bit 3. TR3 through TRO is the binary
coded track number used by the drive to select a
designated track. (MSB).

o

Track Select bit 2. TR3 through TRO is the binary
coded track number used by the drive to select a
designated track.

o

Track Select bit 1. TR3 through TRO is the binary
coded track number used by the drive to select a
designated track.

o

Track Select bit o. TR3 through TRO is the binary
coded track number used by the drive to select a
designated track. (LSB).

o

RST is a minimum pulse of 13 usec. It starts the
initialization routine and recalibration of the head
to its reference position.

o

When asserted DSO permits basic tape drive
operations to proceed. DSO enables the transfer
of control signals: RDP CIN USF TCH EEN. The
drive acknowledges receipt of DSO by sending
SLD.

o

When asserted, enables operation with DC 600A
tape cartridges. Refer to ANSC Project 671
Unrecorded Magnetic Tape Cartridge for Informa·
tion Interchange, 0.250 inch (6.30mm)6400-10000
flux-reversals per inch (252-394 frpmm).

I

Serial-bit data read from tape to the WD10368-WX2.
RDP ~resent when data passes the read head
and DSO is asserted.

SELECT 3

7

8

TR2

TRACK
SELECT 2

9

10

TR1

TRACK
SELECT 1

11

12

TRO

13

14

RST

TRACK
SELECT 0

15

16

RESERVED

17

18

RESERVED

19

20

21

22

RESERVED
DSO

DRiVE
SELECT 0

23

24

HC

HiGH
CURRENT

25

26

RDP

27

28

UTH

UPPER TAPE
POSITION
HOLE

I

UTH and LTH encode information having to do
with tape position as follows:

29

30

LTH

LOWER TAPE
POSITION
HOLE

I

UTH

1

o
1

o

LTH
1

1

o
o

MEANING
Beginning of Tape
End of Tape
Warning Zone
Recording Zone

The Recording Zone is between the Load Point and
the Early Warning hole if BOT or EOT has been
detected since the last cartridge insertion (CIN).
If that is not the case 0 0 means the tape position
is not known.

Tape Drive Controller Products

7-41

TABLE 2. DRIVE CONNECTOR (J1) PIN DESCRIPTION

:E

c
.....
o
w
en

en

:e><

SIG.

MNEMONIC

I/O

FUNCTION

DRIVE
SELECTED

I

Tape drive acknowledgment to the WD1036S-WX2
of receipt of the DSO.

CIN

CARTRIDGE
IN

I

CIN is asserted when a tape cartridge is in...Qlace
and the WD1036S-WX2 asserts DSO and GO.

36

USF

UNSAFE

I

The drive asserts USF when the File Protect Plug
is not in the safe position on the cartridge and the
WD1036S-WX2 asserts DSO. This state permits
data to be written and erased.

37

38

TCH

TACH PULSE

I

TCH is present while tape is moving. It is not looked
at or used by the WD1036S-WX2.

39

40

WDA-

WRITE DATA-

0

Data to be written on tape, enabled while WEN
is asserted. System is optimized to record GCR data
at a nominal density of 10,000 frpi.

GND •

SIG.
PIN

31

32

SLD

33

34

35

N

SIGNAL
NAME

41

42

WDA+

WRITE DATA+

44

THD

THRESHOLD

0
0

The inverse of WDA-

43

45

46

HSD

HIGH SPEED

0

Asserted
9O-ips tape speed. Utilities supplied by
Western Digital always asserts HSD.

47

48

WRITE
ENABLE

0

When asserted, enables drive to write data.

49

50

ERASE
ENABLE

0

Tape is erased the full width of the tape when the
WD1036S-WX2 asserts DSO and EEN.

-WEN
EEN

--

Sets a percentage-qualifying voltage threshold for
Read Data. Eliminates data of marginal quality read
from tape.

=

COMMAND SUMMARY

HARDWARE COMMANDS

The commands associated with the WD1036S-WX2
fall into one of two categories. Hardware commands,
those low level commands that communicate directly
with the WD1036S-WX2 and are implemented by the
WD1100-18 and WD24C02, and high level software
commands, those commands within the application
level module that interface between the application
program and Core.

There are a total of 16 commands recognized by the
WD1036S-WX2. Ten of these commands are the direct
responsibility of the WD1100-18 and six are performed
by the WD24C02. The WD1036S-WX2 occupies sixteen 1/0 addresses, 0 through F Hex. The base
address is jumper selectable at the time of installation to start at one of sixteen locations from 300 Hex
through 3FO Hex.
Following is a brief summary of the hardware commands. For a more indepth description, refer to the
OEM manual, DOC. number 79-000037.

7-42

Tape Drive Controller Products

TABLE 3. HARDWARE COMMAND SUMMARY
OFFSET

1/0

0

lOR

COMMAND NAME
READ STATUS

DESCRIPTION
Returns a status byte representing the state of the following
signals:
Bit
Bit
Bit
Bit

7
6
5
4

=
=
=
=

RGAP
TCH
USF
CIN

Bit
Bit
Bit
Bit

3
2
1
0

=
=
=
=

~

SLD
LTH
UTH
INT

><

N

4

lOR

START DMA PIPELINE

Two ORO DACK handshakes are completed. This writes two
data bytes into a DMA buffer in the WD11DO-18. A Write Tape
command can now be started.

8

lOR

CONTROLLER RESET

Resets all WD1100-18 internal logic, both Drive Control
registers and de-asserts MR to the WD24C02.

C

lOR

READ WD24C02 STATUS
REGISTER

Returns to the Host the state of the following signals:

Returns to the Host the block address of the last data block
read. The block address is four bytes in length. Therefore, four
consecutive Read Block Address commands must be issued.
The MSB is returned first.

Bit 7 = CBK
Bit 6-4 not used
Bit 3 = RGP

Bit 2
Bit 1
Bit 0

= FMD
= WGP
= CER

F

lOR

READ BLOCK ADDRESS

0

lOW

SET CONTROL FLlp·FLOPS This command establishes the state of the DMA enable and
Repeat Flip/Flops.
Bit 0
Bit 1
Bit 2

4

8

C

lOW

lOW

lOW

Drive Control Register 0 controls the following signals:

SET DRIVE CONTROL
REGISTER 1

Drive Control Register 1 controls the following signals:

LOAD COMMAND REGISTER

Bit
Bit
Bit
Bit

lOW

WRITE BLOCK ADDRESS
REGISTER

Tape Drive Control/er Products

7 not used
6 = Read Gate Enable
5 = Write Enable
4 = Erase Enable
7 not used
6 = Reset Drive
5 = High Speed
4 = High Current

Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit

3
2
1
0
3
2
1
0

=
=
=
=
=
=
=
=

Drive Select
Threshold
Reverse
Go
Track
Track
Track
Track

Select
Select
Select
Select

3
2
1
0

A byte\representing one of six possible commands is writ·
ten into the Command Register in the WD24C02.
Bit
Bit
Bit
Bit

F

= Set DMA Enable
= Set Repeat Write Data Command.
= Reset Repeat F/F

SET DRIVE CONTROL
REGISTER 0

Bit
Bit
Bit
Bit

7 = Abort
6 = Write File Mark
5, 4 not used
3 = Write Gap

Bit 2
Bit 1
Bit 0

==
C
.....

o
w
en

= Read Scan
= Write Data
= Read Data

The Block Address Register is four bytes in length, therefore
this command must be issued consecutively four times. The
MSB is written first.

7-43

SOFTWARE COMMANDS
The commands that comprise the Application-to-Core
Module can be divided into four categories: Tape
Access commands, Disk Access commands, Host
Buffer Manager commands and Mode commands.
Following is a brief summary of the Application-toCore command set. For a more indepth description,
refer to the OEM manual, DOC. number 79-000037.

Status Format
Returned upon completion of a command
OP.CODE

Command Format
OP. CODE

I

OPTION

I

STATUS

BYTE 1 - 2

STATUS 2

BYTE 3 - 4

STATUS 3

BYTE 5 - 6

BYTE 1 - 2

PARAMETER 2

BYTE 3 - 4

PARAMETER 3

BYTE 5 - 6

TABLE 4_ SOFTWARE COMMAND SUMMARY
COMMAND

OPTION

OP
CODE

PARAMETERS

Tape Commands
Retension

01

00 Do not erase
01 Erase

-

Read Tape

02

00 Start reading at the beginning of the tape.

-

Write Tape
Find Tape Block

03
04

01 Start reading following the last block read by a Read
Command or found with a Find Command
00 Start writing at the beginning of the present track.
01 Start writing at the end of recorded data.

00 Find Data Block "n".
01 Find Control Block "n".
02 Find File Mark Block "n".
03 Find Block Address "addr".
04 Find beginning of track "n".

Stop Tape

-

-

-

-

-

-

=
=
=

Parm 2
n
Parm 2
n
Parm 2
n
addr
Parm
2 and 3
Parm 2
n

=

=

05

00 No options

-

06

00 Disk Image

-

-

Disk Commands
Set Disk Mode

01 File Image
Read Disk

07

00 No Options

Write Disk

08

00 No Options

7-44

-

-

-

Tape Drive Controller Products

TABLE 4. SOFTWARE COMMAND SUMMARY (cant)
COMMAND

OP
CODE

Host Buffer Commands
Read Buffer
09

Write Buffer

OA

OPTION

00
01
02
03
04
05
06

Read previous page
Read current page
Read next page
Skip one page
Skip to next data block
Skip to next control block
Skip to next File Mark

00 Write a data block

01 Write a control block
02 Write a File Mark block
OB

Reserved

Write
Configuration

OC

00 Miscellaneous Status.

Read
Configuration

00

Initialize

OE

PARAMETERS

-

-

-

Mode Commands
01
02
03
04
OE
OF
10

Maximum number of tracks.
Number of pages in buffer.
Seg. of buffers' first page
Offset of first page.
Write CRC error counter.
Pointer to local buffer.
Pointer to word containing expected tape block
address
11 Pointer to word containing last tape block
address.
12 Pointer to word containing current tape track.
13 Reposition counter.

00 Miscellaneous Status.

01
02
03
04
00
OF
10

Maximum number of tracks.
Number of pages in buffer.
Seg. of buffers' first page
Offset of first page.
Read CRC error counter.
Pointer to local buffer.
Pointer to word containing expected tape
block address
11 Pointer to word containing last tape block address.
12 Pointer to word containing current tape track.
13 Reposition counter.

Data read is
returned in Stat 2

00 All (options 01 - 05)

01
02
03
04
05

Tape Drive Controller Products

Data to be written
in Parm 2

Tape portion
Core variables
Buffer Manager
Cartridge status
Controller reset

7-45

7-46

Tape Drive Controller Products

WESTERN
COR

P

0

DIGITAL
o

RAT

N

:E
c

WD8206 Error Detection and Correction Unit
FEATURES

•
•
•
•
•
•

•

DETECTS AND CORRECTS ALL SINGLE BIT
ERRORS
DETECTS ALL DOUBLE BIT AND MOST MULTIPLE BIT ERRORS
52 NSEC MAXIMUM FOR DETECTION; 67 NSEC
MAXIMUM FOR CORRECTION (16-BIT SYSTEM)
EXPANDABLE TO HANDLE 80-BIT MEMORIES
SYNDROME INPUT AND OUTPUT BUSSES - NO
TIMING STROBES REQUIRED
SUPPORTS READS WITH AND WITHOUT CORRECTION, \WRITES, PARTIAL (BYTE) WRITES,
AND READ-MODIFY-WRITES
HMOS TECHNOLOGY FOR LOW POWER

o0)

68-PIN LEADLESS JEDEC PACKAGE
SINGLE + 5V SUPPLY

GENERAL DESCRIPTION

The HMOS 8206 Error Detection and Correction Unit
is a high-speed device that provides error detection
and correction for memory systems (static and
dynamic) requiring high reliability and performance.
Each WD8206 handles 8 or 16 data bits and up to 8
check bits. WD8206's can be cascaded to provide correction and detection for up to 80-bits of data. Other
WD8206 features include the ability to handle byte
writes, memory initialization, and error logging.

16

01 0-15

STB

•
•

CD
N

_=:::r---J

CBI/SYI0-7

~......,...2__
POSO.1

,-------4

I----~

r-------1 I----_+_

16
SYO/CBO/PPOO_('-_4-_-"

ERROR
CE

DATA
CORREC·
TION

DOIW010-15

PPI/POS/NSL - + - - - " . 1

16

Mis

GNO +5V

11

Vss Vcc

WZ

BM0-1

FIGURE 1. WD8206 BLOCK DIAGRAM

Main Memory Device

8-1

TABLE 1. PIN DESCRIPTION

:E
c00

I\:)

o
en

I

8-2

PIN
NUMBER
1,68-61,
59-53
5
6
7
8
9
10
11
12
51
50
49
48
47
46
45
44
42
41
40
39
38
37
36
35
23
24
25
27
28
29
30
31
13
14

Dl0-15

1/0
I

CBIISYl o
CBI/SYI 1
CBI/SYI 2
CBI/SYI 3
CBI/SYI 4
CBI/SYI 5
CBl/SYl s
CBI/SYI 7
DOIWDl o
DOIWDI 1
DOIWDI 2
DOIWDI 3
DOIWDl 4
DOIWDI 5
DOIWDl s
DOIWDI 7
DOIWDl s
DOIWDl g
DOIWDI 1o
DOIWDI 11
DOIWDI 12
DOIWDI 13
DOIWDI 14
DOIWDI 15
SYO/CBO/PPOo
SYO/CBO/PP0 1
SYO/CBO/PP02
SYO/CBO/PP03
SYO/CBO/PP04
SYO/CBO/PP05
SYO/CBO/PPOs
SYO/CBO/PP07
PPldPOSo
PPI 1/POS 1

I
I
I
I
I
I
I
I
110
1/0
1/0
110
1/0
1/0
1/0
1/0
1/0
110
110
1/0
1/0
1/0
1/0
1/0
0
0
0
0
0
0
0
0
I
I

15
16

PPI 2/NSLo
PPI 3/NSL1

I
I

17

PPI 4/CE

110

18
19
20

PPI 5
PPl s
PPI 7

I
I
I

SYMBOL

NAME AND FUNCTION
Data In: These inputs accept a 16-bit word from
RAM for error detection and/or correction.
Check Bits InlSyndrome In: In a single WD8206
system, or in the master in a multi-WD8206 system,
these inputs accept the check bits (5 to 8) from
the RAM. In a single WD820616 bit system, CBl0-5
are used. In slave WD8206's, these inputs accept
the syndrome from the master.

Data OutiWrite Data In: In a read cycle, data
accepted by Dl0-15 appears at these outputs corrected if CRCT is low, or uncorrected if CRCT is
high. The IBM inputs must be high to enable the
output buffers during the read cycle. In a write
cycle, data to be written into the RAM is accepted
by these inputs for computing the write check bits.
In a partial-write cycle, the byte not to be modified
appears at either D00-7 if BMo is high, or DOS-15
if BM1 is high, for writing to the RAM. When WZ
is active, it causes the WD8206 to output all zeros
at D00-15' with the proper write check bits on
CBO.

Syndrome Out/Check Bits Out/Partial Parity Out: In
a single WD8206 system, or in the master in a
multi-WD8206 system, the syndrome appears at
these outputs during a read. During a write, the
write check bits appear. In slave WD8206's, the partial parity bits used by the master appear at these
outputs. The syndrome is latched (during readmodify-writes) by RJW going low.
Partial Parity In/Position: In the master in the multiWD8206 system, these inputs accept partial parity
bits 0 and 1 from the slaves. In a slave WD8206,
these inputs inform it of its position within the
system (1 to 4). Not used in a single WD8206
system.
Partial Parity In/Number of Slaves: In the master in
a multi-WD8206 system, these inputs accept partial parity bits 2 and 3 from the slaves. In a multi·
WD8206 system, these inputs are used in slave
number 1 to tell it the total number of slaves in
the system (1 to 4). Not used in other slaves or in
a single WD8206 system.
Partial Parity In/Correctable Error: In the master in
a multi·WD8206 system, this pin accepts partial
parity bit 4. In slave number 1 only, or in a single
WD8206 system, this pin outputs the correctable
error flag. CE is latched by RJW going low. Not
used in other slaves.
Partial Parity In: In the master in a multi·WD8206
system, these pins accept partial parity bits 5 to
7. The number of partial parity bits equals the
number of check bits. Not used in single WD8206
systems or in slaves.

Main Memory Device

TABLE 1. PIN DESCRIPTION (CONTINUED)
PIN
NUMBER
22

SYMBOL
ERROR

I/O
0

52

CRCT

I

2

STB

I

33
32

BMa
BM1

I
I

21

RIW

I

34

WZ

I

4

MIS

I

3

SEDCU

I

60

Vcc

I

NAME AND FUNCTION
Error: This pin outputs the error flag in a single
WD8206 system or in the master of a multi-WD8206
system. It is latched by RIW going low. Not used
in slaves.
Correct: When low, this pin causes data correction
during a read or read-modify-write cycle. When
high, it causes error correction to be disabled,
although error checking is still enabled.
Strobe: STB is an input control used to strobe data
at the DI inputs and check-bits at the CBIISYI
inputs. The signal is active high to admit the
inputs. The signals are latched by the high-to-Iow
transition of STB.
Byte Marks: When high, the Data Out pins are
enabled for a read cycle. When low, the Data Out
buffers are tristated for a write cycle. BMa controls DO()'7' while BM1 controls D08. 15. In partial
(bytes) writes, the byte mark input is low for the
new byte to be written.
Read/Wrlte: When high, this pin causes the
WD8206 to perform detection and correction (if
CRCT is low). When low, it causes the WD8206 to
generate check bits. On the high-to-Iow transition,
the syndrome is latched internally for read-modifywrite cycles.
Write Zero: When low, this input overrides the
BM()'1 and RIW inputs to cause the WD8206 to
output all zeros at DO()'15 with the corresponding
check bits at CBO a_7· Used for memory
initialization.
Master/Slave: Input tells the WD8206 whether it is
a master (high) or a slave (low).
Single EDC Unit: Input tells the master whether it
is operating as a single WD8206 (low) or as the
master in a multi-WD8206 system (high). Not used
in slaves.
Power Supply: + 5V

26

Vss

I

Logic Ground

43

Vss

I

Output Driver Ground

FUNCTIONAL DESCRIPTION

are not distinguished from errors in a word.

The WD8206 Error Detection and Correction Unit provides greater memory system reliability through its
ability to detect and correct memory errors. It is a
single chip device that can detect and correct all
single bit errors and detect all double bit and some
higher multiple bit errors. Some other odd multiple
bit errors (e.g., 5 bits in error) are interpreted as single
bit errors, and the CE flag is raised. While some even
multiple bit errors (e.g., 4 bits in eror) are interpreted
as no error, most are detected as double bit errors.
This error handling is a function of the number of
check bits used by the WD8206 (see Figure 2) and
the specific Hamming code used. Errors in check bits

A single WD8206 handles 8 or 16 bits of data, and
up to 5 WD8206's can be cascaded in order to handle data paths for 80 bits. For a single WD8206 8-bit
system, the DI8-15, DOIWDI8-15 and BM1 inputs are
grounded. See the Multi-Chip systems section for
information on 24-80-bit systems.

Main Memory Device

The WD8206 has a "flow through" architecture. It supports two kinds of error correction architecture: 1)
Flow-through, or correct-always; and 2) Parallel, or
check-only. There are two separate 16-pin busses, one
to accept data from the RAM (DI) and the other to
deliver corrected data to the system bus (DOIWDI).
The logic is entirely combinatorial during a read cycle.

8-3

=E
c00
N

oC)

This is in contrast to an architecture with only one
bus, with bi-c:lirectional bus drivers that must first read
the data and then be turned around to output the corrected data. The latter architecture typically requires
additional hardware (latches and/or transceivers) and
may be slower in a system due to timing skews of
control signals.
DATA WORD BITS

CHECK BITS

8
16
24
32
40
48
56
64
72
80

5
6
6
7
7
8
8
8
8
8

FIGURE 2. NUMBER OF CHECK BITS USED BY WD8206
READ CYCLE
With the RIW pin high, data is received from the RAM
outputs into the DI pins where it is optionally latched
by the STB signal. Check bits are generated from the
data bits and compared to the check bits read from
the RAM into the CBI pins. If an error is detected, the
ERROR flag is activated and the correctable error flag
(CE) is used to inform the system whether the error
is correctable or not. With the BM inputs high, the
word appears corrected at the DO pins if the error
is correctable, or unmodified if the error was uncorrectable.
If more than one WD8206 is being used, then the
check bits are read by the master. The slaves generate
a partial parity output (PPO) and pass it to the master.
The master WD8206 then generates and returns the
syndrome to the slaves (SYO) for correction of the
data.
The WD8206 may alternatively be used in a "check·
only" mode with the CRCT pin left high. With the cor·
rection facility turned off, the propagation delay from
memory outputs to WD8206 outputs is significantly
shortened. In this mode, the WD8206 issues an
ERROR flag to the CPU, which can then perform one
of several options: lengthen the current cycle for correction, restart the instruction, perform a diagnostic
routine, etc.

state the DO drivers. The check bits, 5 to 8 in number,
are then written to the RAM through the CBO pins
for storage along with the data word. In a multi-chip
system, the master writes the check bits using partial parity information from the slaves.
In a partial write, part of the data word is overwritten
and part is retained in memory. This is accomplished
by performing a read-modify-write cycle. The complete
old word is read into the WD8206 and corrected, with
the syndrome internally latched by RIW going low.
Only that part of the word not to be modified is output onto the DO pins, as controlled by the Byte Mark
inputs. That portion of the word to be overwritten is
supplied by the system bus. The WD8206 then
calculates check bits for the new word, using the byte
from the previous read and the new byte from the
system bus, and writes them to the memory.
READ-MODIFY-WRITE CYCLES
Upon detection of an error, the WD8206 may be used
to correct the bit in error in memory. This reduces the
probability of getting multiple-bit errors in subsequent
read cycles. This correction is handled by executing
read-modify-write cycles.
The read-modify-write cycle is controlled by the RIW
input. After (during) the read cycle, the system
dynamic RAM controller or CPU examines the
WD8206 ERROR and CE outputs to determine if a correctable error occurred. If it did, the dynamic RAM
controller or CPU forces RIW low, telling the WD8206
to latch the generated syndrome and drive the corrected check bits onto the CBO outputs. The corrected data is available on the DO pins. The DRAM
controller then writes the corrected data and corresponding check bits into memory.
The WD8206 may be used to perform read-modifywrites in one or two RAM cycles. If it is done in two
cycles, the WD8206 latches are used to hold the data
and check bits from the read cycle to be used in the
following write cycle. The WD8207 Advanced Dynamic
RAM controller allows read-modify-write cycles in one
memory cycle. See the System Environment section.
INITIALIZATION

WRITE CYCLE

A memory system operating with ECC requires some
form of initialization at system power-up in order to
set valid data and check bit information in memory.
The WD8206 supports memory initialization by the
write zero function. By activating the WZ pin, the
WD8206 will write a data pattern of zeros and the
associated check bits in the current write cycle. By
thus writing to all memory at power-up, a controller
can/set memory to valid data and check bits. Massive
memory failure, as signified by both data and check
bits all ones or zeros, will be detected as an uncorrectable error.

For a full write, in which an entire word is written to
memory, the data is written directly to the RAM,
bypassing the WD8206. The same data enters the
WD8206 through the WDI pins where check bits are
generated. The Byte Mark inputs must be low to tri-

A single WD8206 handles 8 or 16 bits of data and 5
or 6 check bits, respectively. Up to 5 WD8206's can
be cascaded for 80-bit memories with 8 check bits.

A syndrome word, five to eight bits in length and con·
taining all necessary information about the existence
and location of an error, is made available to the
system at the SY00-7 pins. Error logging may be
accomplished by latching the syndrome and the
memory address of the word in error.

8-4

MULTI-CHIP SYSTEMS

Main Memory Device

When cascaded, one WD8206 operates as a master,
and all others as slaves. As an example, during a read
cycle in a 32-bit system with one master and one
slave, the slave calculates parity on its portion of the
word - "partial parity" - and presents it to the master
through the PPO pins. The master combines the partial parity from the slave with the parity it calculated
from its own portion of the word to generate a syndrome. The syndrome is then returned by the master
to the slave for error correction. In systems with more

than one slave, the above description continues to
apply, except that the partial parity outputs of the
slaves must be XORed externally. Figure 3 shows the
necessary external logic for multi-chip systems. Write
and read-modify-write cycles are carried out
analogously. See the System Operation section for
multi-chip wiring diagrams.
There are several pins used to define whether the
WD8206 will operate as a master or a slave. Tables
2 and 3 illustrate how these pins are tied.

38. 48-Bit System

SLAVE 2
PPO

8

3b. 64-Bit System

SLAVE 3
PPO

MASTER
PPI

8

3c. aD-Bit System

MASTER
PPI

SLAVE 3
PPO

8

SLAVE 4
PPO

8

FIGURE 3_ EXTERNAL LOGIC FOR MULTI-CHIP SYSTEMS

Main Memory Device

8-5

:E
c

CD
N

o

0')

TABLE 2. MASTER/SLAVE PIN ASSIGNMENTS
PIN NO.
4
3
13
14
15
16

PIN NAME

MASTER

MIS

+5V
+5V
PPI
PPI
PPI
PPI

SEDCU
PPldPOSo
PPI 1/POS 1
PPI 2/NSLo
PPI;fNSL1

SLAVE1
Gnd
+5V
Gnd
Gnd

.

SLAVE2

SLAVE3

Gnd
+5V
+5V
Gnd
+5V
+5V

Gnd
+5V
Gnd
+5V
+5V
+5V

SLAVE4
Gnd
+5V
+5V
+5V
+5V
+5V

·See Table 3.
NOTE:
Pins 13, 14, 15, and 16 have internal pull-up resistors and may be left as N.C. where specified as connecting to + 5V.
TABLE 3. NSL PIN ASSIGNMENTS FOR SLAVE 1
NUMBER OF SLAVES
PIN

' 1

2

PPI 2/NSLo
PPI;fNSL1

Gnd
Gnd

+5V
Gnd

The timing specifications for multi-chip systems must
be calculated to take account of the external XOR
gating in 3,4, and 5-chip systems. Let tXOR be the
delay for a single external TTL XOR gate. Then the
following equations show how to calculate the relevant timing parameters for 2-chip (n = 0),3- chip (n
1), 4-chip (n
2), and 5-chip (n
2) systems:

=

=

=

=

Data-in to corrected data-out (read cycle)
TDVSV + TPVSV + TSVaV + ntXOR

=

Data-in to error flag (read cycle)
TDVSV + TPVEV + ntXOR
Data-in to correctable error flag (read cycle)
TDVSV + TPVSV + TSVCV + ntXOR

=

Write data to check-bits valid (read-mod-write cycle) =
TaVaV + TPVSV + ntXOR
Data-in to check-bits valid (read-mod-write cycle)
TDVSV + TPVSV + TSVaV + TaVaV +
TPVSV + 2ntXOR

=

Data-in to check-bits valid (non-correcting readmodify-write cycle) =
TDVaU + TaVaV + TPVSV + ntXOR
HAMMING CODE
The WD8206 uses a modified Hamming code which
was optimized for multi-chip EDCU systems. The code
is such that partial parity is computed by all WD8206's

8-6

3
Gnd
+5V

4
+5V
+5V

in parallel. No WD8206 requires more time for propagation through logic levels than any other one, and
hence no one device becomes a bottleneck in the
parity operation. However, one or two levels of external TTL XOR gates are required in systems with three
to five chips. The code appears in Table 4. The check
bits are derived from the table by XORing or XNORing together the bits indicated by oX's in each row corresponding to a check bit. For example, check bit 0
in the MASTER for data word 1000110101101011 will
be "0." It should be noted that the WD8206 will detect
the gross error condition of all lows or all highs.
Error correction is accomplished by identifying the
bad bit and inverting it. Table 4 can also be used as
an error syndrome table by replacing the oX's with '1 'so
Each column then represents a different syndrome
word, and by locating the column corresponding to
a particular syndrome the bit to be corrected may be
identified. If the syndrome cannot be located, then
the error cannot be corrected. For example, if the syndrome word is 00110111, the bit to be corrected is bit
5 in the slave one data word (bit 21).
The syndrome decoding is also summarized in Table
5, which can be used for error logging. By finding the
appropriate syndrome word (starting with bit zero, the
least significant bit), the result is either: 1) no error;
2) an identified (correctable) single bit error; 3) a double bit error; or 4) a multi-bit uncorrectable error.

Main Memory Device

50

~
50

()

(..)0.0

i

I\)

a"

6-1l)C'"

;:;:g:~
~
Il)

en

o

~

*"3 50 coen

~

_

~o
(l)

~

1l)(I)~

Il)

BYTE NUMBER
0
1
OPERATION
BIT NUMBER o 1 234 5 6 7 o 1 234 5 6 7
CBO = XX-X-XX- X--X-X-XNOR
CB1 = X-X--X-X -X-XX-XXNOR
~HECKCB2 = -XX-X-XX --X-X--X
XOR
CB3 = XXXXX--- XXX----XOR
BITS CB4 = ---XXXXX -----XXX
XOR
XOR
CB5 = -------- XXXXXXXX
CB6 = -------- -------XOR
CB7 = 1-------- -------XOR
o 0 0 0 0 0 0 0 00111 1 1 1
DATA BITS o
1 2 3 4 5 6 7 890 1 2 3 4 5
16 BIT OR MASTER

I

I

o1

2
234 567

o1

-------- -------1 1 1 1 2 2 2 2 222 2 2 2 3 3
6 7 8 901 2 3 456 7 8 901
SLAVE #1

:::T ~
(I) (I)

a@
-i
CD »
en
OJ

0. :E
(Xl
_0

XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR

-XXX-XX- -XX--X-XXX--X-X XX-----X
-XXX-XXX --XX---XX--X-XX X--XX--XX--XXXX ----X-X---XXXXX -----XXX
-------- XXXXXXXX

I

::::I

3
OPERATION
234 5 6 7

r+

::::I

0.

0

Q~

& en ><
6

en

7 "0 ::D

3
o

.....

g _':
0.::::1
_0

~~

;:;: _
en 0

I

I

ct>

en:::Tct>:::T
~ ct>
C'" ()
;::::;: OJ
~ 0
o

I

=0
2"T1
::I:

»
:s:
:s:
Z

C)
C')

0

c

Z ~

m

0.

C')

:::T.....

C')

~

"

a

0.

(I)
~ Il)
ct> g:
0)

en

OJ

=i
C)

m

0-

Z

:::T:E

m
;:tI

~ :!.

"0

»

C'":::T

::::!

;:;: Il)

0

en

Z

50

en
X

Il)Z

..... 0

O)::D
6- (1)-

en
'< ::::I
~s::
(I) Il)
3 ~
(I)

-0

"'"'J

::II

CD
_ ()
OJ ::I:
m

;:;:0.

CjO

m
~

ro
iii
~
C

3

I

BYTE NUMBER
4
5
6
8
9
7 .
OPERATION
BIT NUMBER o 1 2 3 4 5 6 7 o 1 2 345 6 7 o 1 2 3 4 5 6 7 o 1 234 5 6 7 o 1 2 3 4 5 6 7 o 1 234 5 6 7
CBO = XX-X-XX- X--X-X-- X-X-XX-- X-XX--X- -XXX-XX- -XX--X-XOR
CB1 = X-X--X-X -X-XX-X- -XX---XX XXX---X- -XXX-XXX --XX---XOR
CHECKCB2 = I-XX-X-XX --X-X--X -XXX-XX- -XX--X-- X--X-XX- -XX--X-X
XOR
CB3 = XXXXX--- XXX----- X-X--XX- XX--XX-- -XXXX--X XX--X--XOR
BITS CB4= ---XXXXX -----XXX ---XXXXX -----XXX -XX---XX XXX---XXOR
CB5 = XXXXXXXX -------- -------- XXXXXXXX X-XXXX-X ---X---X
XOR
CB6 = XXXXXXXX -------- XXXXXXXX -------- XX--XXXX ----X-XXOR
CB7 = -------- XXXXXXXX -------- XXXXXXXX -------- XXXXXXXX
XOR
3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5555666 6 6 6 6 6 6 6 7 7 777 7 7 7 7 7
DATA BITS 32 33 34 53 36 789
o 1 2 345 6 7 890 1 234 5 67890 1 2 3 456 7 8 9 0 1 2345678 9
SLAVE #2
SLAVE #3
SLAVE #4

II

co

~ ~~
- ct> 0Q

o

I

0

r-

-....I~

90lsaM

TABLE 5. SYNDROME DECODING

o0
Syndrome
Bits
6
5

7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

4

1 0
2 0
3 0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

N
CB4
CB5
D
CB6
D
D
30
CB7
D
D
63
D
78
U
D

1
0
1
0
0
0
0
0
CBO CB1
D
D
D
D
13
14
D
D
52
55
31
29
D
D
D
D
45
46
75
59
D
D
U
U
D
D
D
D
U
U

1
1
0
0
D
5
11
D
25
D
D
37
43
D
D
62
D
U
U
D

0
0
1
0
CB2
D
D
15
D
51
64
D
D
47
79
D
U
D
D
U

1
0
1
0
D
6
19
D
26
D
D
38

77
D
D
U
D
U
U
D

0
1
1
0

1
1
1
0

0
0
0
1

1
0
0
1

0
1
0
1

1
1
0
1

0
0
1
1

1
0
1
1

0
1
1
1

1
1
1
1

D
7
12
D
49
D
D
39
44
D
D
U
D
U
U
D

18
D
D
21
D
70
69
D
D
74
58
D
U
D
D
U

CB3
D
D
20
D
28
68
D
D

D
3
8
D
48
D
D
35
40
D
D
U
D
U
U
D

D
16
9
D
24
D
D
71
41
D
D
U
D
U
U
D

0
D
D
66
D
65
32
D
D
U
56
D
U
D
D
U

D
4
10
D
27
D
D
36
42
D
D
61
D
U
U
D

1
D
D
22
D
53
33
D
D
73
U
D
U
D
D
U

2
D
D
23
D
54
34
D
D
U
57
D
U
D
D
U

D
17
67
D
50
D
D
U
U
D
D
U
D
U
U
D

= No Error

N
CBX
X =
D =
U

=

SYSTEM ENVIRONMENT

= Error in Check Bit X

The WD8206 interface to a typical 32-bit memory
system is illustrated in Figure 4. For larger systems,
the partial parity bits from slaves two to four must
be XOR'ed externally, which calls for one level of XOR
gating for three WD8206's and two levels for four or
five WD8206's.

Error in Data Bit X
Double Bit Error
Uncorrectable Multi-Bit Error

OE

32-BIT
OATA
BUS

~
X

~

01

00

CHECK
BITS
7-BITS
01

DATA MEMORY
16-BITS
01

00

.

v
R

~

I--i---

t---

'"

I-I-l......-

'

~

OO/WOI

.
01

I-

CRCT
WZ
STB

CO NTROL {
L INES

PPI7
CBI7

WD8206
MASTER

R/ill
BMO
BM1

em {

MARKS

-

ERROR

II '

!1

SYOI CB1O-6
CBO
PPIO-6

..
~

ERROR
SIGNALS

00

;7'4

(11-

...

C

.,-

T

DATA MEMORY
16-BITS

.

72
60
D
76
D
D
U

h
!I

SYIO-6

....---.

.

~

OO/WOI

~~

PPOO-6

CRCT
~ WZ
~ STB
R/W
MIS I:T0+V ~
SEOCU
BMO
BM1

..

~

01

WD8206
SLAVE

CE

POSo
POS1
NSLo ~
NSL1

'4

MIS ~
PP15-7
SEOCU
SYI7

9-

0 + 5V

I

FIGURE 4. 32-BIT WD8206 SYSTEM INTERFACE

8-8

Main Memory Device

The WD8206 is designed for direct connection to the
WD8207 Advanced Dynamic RAM Controller. The
WD8207 has the ability to perform dual port memory
control and Figure 5 illustrates a highly integrated
dual port RAM implementation using the WD8206 and
WD8207. The WD8206/WD8207 combination permits

1

ACKB

ACKB

.. CMDI
PEA
CMD/PEB
ADDRB

CMD/PEA

---

A.-

CMDI

r

PEB

ADDR
RAS
CAS
WE

DYNAMIC
RAM
32·BITS +
7 CHECK BITS

....
r

K>o-o

WD8207
MUX ADRC WZ
ClK~ ClK
PSEN
CE
ERROR
DBM -

WE
01

CBI
.II

-

UX ~

--I

~DDR

ACKA

R/W
PSEl

L

R/W
+5V- STB

....-

..

001

cao

h

L ---

ERROR

ADORA
ACKA

such features as automatic scrubbing (correcting
errors in memory during refresh), extending RAS and
CAS timings for Read·Modify-Writes in single memory
cycles, and automatic memory initialization upon
reset. Together, these two chips provide a complete
dual·port, error·corrected dynamic RAM subsystem.

OIlC~'

CBO

PPI

R/W

..

~ CRCTWD8206
MASTER
BM DO/WDI

Q
i!t:

~IwjBYTE
MARK
DECODER

~

•

--+ 5V

BM DO/WDI

Q
I
~

-

....

.....

~

PORTA

PPO
STB
CRCTWD8206
SLAVE
WZ

WZ

• a..

----

~

L L'0,
CE

SYOI

~

,

~

X VR

~r

~~c~EI

-RD

PORTB

FIGURE 5. DUAL PORT RAM SUBSYSTEM WITH WD820SIWD8207 (32-BIT BUS)

Main Memory Device

8-9

:eo

00

I\)

o

C)

MEMORY BOARD TESTING

The WD8206 lends itself to straightforward memory
board testing with a minimum of hardware overhead.
The following is a description of four common test
modes and their implementation.
Mode 0 -Read and write with error correction.
Implementation: This mode is the normal
WD8206 operating mode.
Mode 1 -Read and write data with error correction
disabled to allow test of data memory.
Implementation: This mode is performed
with CRCT deactivated.
Mode 2 -Read and write check bits with error correction disabled to allow test of check bits
memory.
Implementation: Any pattern may be written into the check bits memory by
judiciously choosing the proper data word
to generate the desired check bits, through
the use of the WD8206 Hamming code.

To read out the check bits, it is first
necessary to fill the data memory with all
zeroes, which may be done by activating
WZ and incrementing memory addresses
with WE to the check bits memory held
inactive, and then performing ordinary
reads. The check bits will then appear
directly at the SYO outputs, with bits CSO
and CS1 inverted.
Mode 3 -Write data, without altering or writing check
bits, to allow the storage of bit combinations to cause error correction and
detection.
Implementation: This mode is implemented
by writing the desired word to memory with
WE to the check bits array held inactive.
PACKAGE

The WD8206 is packaged in a 68-pin, leadless JEDEC
type A hermetic chip carrier. Figure 6 illustrates the
package, and Figure 7 is the pinout.

.066

.050

(1.68)

(1.27)

rl:
.800

.960
(24.38)

(20.32)

./
PIN NO.18

PIN NO.1
.130
(3.30)

~

.960

(24.38)----~

FIGURE 6. WD8206 JEDEC TYPE A PACKAGE

8-10

Main Memory Device

~

co

i5

i5

a0

a0

TOP

i5

i5

:E

a

a0

(X)
I\)

e

l"-

~

~

~

c

~

C/) 0

0

g>1

en

Wi.
BMo
BM1

SY~[
SY03
VSS
SY02[
SYOo

PPI7[
PPI5

01 1

e

~

a::

PIN NO.1 MARK

I"-

a::

a.

iii

a.

U

BonOM

e

i5

i5

~

a0

i5

,3:

3:

3:

a0

~

co

I"-

i5

a

a0

C/) 0

Ig>

I
WZ

CRCT

BMo

01

BM1

TYO'

15 [

Dig

SY03
VSS
SY0

VCC

J

01 8

2
SYOo

ERROR
R/W
PPI
]
01 1

e

CD

i5 ~

I=>IC/)

gw i
C/)

I
E

CD

U

I I
e
a::
U a.
I"-

iii

7
PPI5

I

~

a::
a.

FIGURE 7. WD8206 PINOUT DIAGRAM

Main Memory Device

8-11

:ec

co

I\,)

o

C')

ABSOLUTE MAXIMUM RATINGS·

·NOTE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect device reliability.

Ambient Temperature Under Bias ..... OOC to 70°C
Storage Temperature .......... -65°C to + 150°C
Voltage On Any Pin
With Respect to Ground ........ -0.5V to + 7V
Power Dissipation ..................... 2.5 Watts

DC CHARACTERISTICS (TA

= OOC to 70°C, Vcc = 5.0V

SYMBOL

PARAMETER

Icc

VIL1

Power Supply Current
- Single WDS206 or Slave #1
- Master in Multi-Chip or Slaves
#2, 3, 4
Input Low Voltage

VIH 1

Input High Voltage

VOL

VOL

ILO

III

MIN.

= GND)

MAX.

UNIT

270
230

rnA
rnA

-0.5

O.S

V

2.0

Vcc +
0.5V

V

0.4
0.4

V
V

10L
10L

= SmA
= 2.0mA

V
V

10H
10H

= -2mA
= 0.4mA

Output Low Voltage
- DO
- All Others
Output Low Voltage
- DO
- All Others

± 10%, Vss

2.6
2.4

TEST CONDITIONS

I/O Leakage Current
-PPI 4/CE
-DOjWD10- 15

±20
±10

J.lA
J.lA

0.45V VI/O vcc

Input Leakage Current
- PPIQ-3, 5-7, CBI6-7, SEDCU2
- All Other Input Only Pins

±20
±10

J.lA
J.lA

OV VIN Vcc

NOTES:
1. SEDCU (pin 3) and MIS (pin 4) are device strapping options and should be tied to Vcc or GND. VIH
min = Vcc - 0.5V and VIL max = 0.5V.
2. PP1 0-7 (pins 13-20) and CB1 6_7 (pins 11, 12) have internal pull-up resistors and if left
unconnected will be pulled to VCC.

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

2.4=X. 2.0 ~ TEST <2.0)<=
./" POINTS
0.45
0.8
O.~
A.C. TESTING INPUTS ARE DRIVEN AT 2.4V FOR A
LOGIC 1 and O.45V FOR A LOGIC O. TIMING MEASUREMENTS ARE MADE AT 2.0V FOR A LOGIC 1 AND O.8V
FOR A LOGIC O.

8-12

CL INCLUDES JIG CAPACITANCE

Main Memory Device

AC CHARACTERISTICS (fA

= OOC to 70°C, Vcc = +5V ± 10%, Vss = OV, C L = 100pF; all times are in nsec.)
WDS206

SYMBOL
TRHEV
TRHCV
TRHQV
TRVSV
TDVEV
TDVCV
TDVQV
TDVSV
TBHQV
TDXQX
TBLQZ
TSHIV
TIVSL
TSLIX
TPVEV
TPVQV
TPVSV
TSVQV
TSVCV
TQVQV
TRHSX
TRLSX
TQXQX
TSVRL
TDVRL
TDVQU
TTVQV
TWLQL
TWHQX

PARAMETER
ERROR Valid from R/W
CE Valid from R/W (Single WD8206)
Corrected Data Valid from R/W
SYO/CBO/PPO Valid from R/W
ERROR Valid from Data/Check Bits In
CE Valid from Data/Check Bits In
Corrected Data Valid from
Data/Check Bits In
SYO/PPO Valid from Data/Check Bits In
Corrected Data Access Time
Hold Time from Data/Check Bits In
Corrected Data Float Delay
STB High to Data/Check Bits In Valid
Data/Check Bits In to STB Set-up
Data/Check Bits In from STB Hold
ERROR Valid from Partial Parity In
Corrected Data (Master) from Partial
Parity In
Syndrome/Check Bits Out from
Partial Parity In
Corrected Data (Slave) Valid from
Syndrome
CE Valid from Syndrome (Slave
number 1)
Check Bits/Partial Parity Out from
Write Data In
Check Bits/Partial Parity Out from
RIW, WZ Hold
Syndrome Out from RIW Hold
Hold Time from Write Data In
Syndrome Out to RIW Set-up
Data/Check Bits In to RIW Set-up
Uncorrected Data Out from Data In
Corrected Data Out from CRCl
WZ to Zero Out
Zero Out from WZ Hold

MIN.

0
0
30
5
25

MAX.

WDS206-S
MAX.

NOTES

25
44
54
42
52
70

MIN.

34
59
66
56
70
96

1
1

67
55
37

90
74
43
0

28

0
40
5
30

1
1
2

30
61

40
76

1

43

51

1

51

69

48

65

64

80

0

0

0
0
17
39

0
0
22
46

1
1

1
1
43
40
40

32
30
30
0

38

0

NOTES:
1. A.C. Test Levels for CBO and DO are 2.4V AND 0.8V.
2. TSHIV is required to guarantee output delay timings: T DVEV, T DVCV, T DVSV, TSHIV + T IVSL guarantees a min
STB pulse width of 35 nsec (45 nsec for the WD8206-8).

Main Memory Device

8-13

WAVEFORMS
READ - 16-BIT ONLY

A/W

TSHllt

TSLI:

r!
I
i I~

II

NI~---I I

r

I

8M

I

I

cg:

{
I
1

DO

i

I

!

I

I-

I

I_

8-14

-

_

I

I

I

i

:

I ~TBLQZ"-"

~TOXQX-.l

VALID

1

.
>W/##ff/d{
TOVSV

-

I
I

I

VALID

I

I

TOVQV

I-

TOVEV
TOVCV
TRHCV

~

x=

I

I
1

-;

I

•

ii l!~ )((/~7//
T~ ~
~
I"

CE

I

TRHQV

TRVSV

:

)

W /ff//A

I- 1

ERROR

VALID

I

::

Ii

I

I

I..

I I..
SYO

I

l.-TBHQV~
I

I

~

I

VALID

- :

x=
I
:

I

-I
_I

V#7//7/~/A

VALID

)C

Main Memory Device

WAVEFORMS (Continued)

:E

READ - MASTER / SLAVE

sra

N'-_________

JI{
+tTSHIV~

~

R/W

BM

I

I

II

--,...-1.I. .7,: ~
I

c~: ---(

: '\L'--_-+-_
I

TBHQVI

!

:

I rJ+--TRVSV I

VALID :

~

P:~::~:::---)(07M
I

I

I

;

I"

I4-TDXQX~

!
I

I

7U

DO(MASTER)--......;:--07$~
I

I

VALID

Main Memory Device

I

I

L.fL

I

I

VALID

I TSVQV
14

I

XI11--:-

i

1

.,

1

I

k)
I

I.TPVSV.j

SYO(MASTER)---J>V$$m
SYI (SLAVE)

X';"':--

VALID

l.-TPVQV ---+I
I

II

I

I

8-15

cCO

I\)

o

en

WAVEFORMS (Continued)

:ec

FULL WRITE - 16-81T ONLY

CO

I\)

I+--TRVSV~

0')

I

o

I

R/W---------~~_ _ _ _ ____'____/ : , . - - - - - I

•

TRLSX~

I TRHSX I
~

,,

a.-

I

I

BM

"*TBLQZ

,

~

DO/WDI

------ ,
----;------r-------'"" '
DATA OUT
~.¥
WRITE DATA IN )1>......:---~
"II
I,

I

.1----,

TaVaV ---+j

I

I

"'1

~

TaXaX-+1

,

X___
I

SYO/CBO - - - - - - S - Y - N - - - - - - - - . X 7 / / A

CB

SY_N_

FULL WRITE - MASTER/SLAVE

t----TRVSV----1

R/W------...,,~

,.......,
TBLaz

BM==X

:

I

I
I
!
I

'I

lTRHSX

~

I
I

I

I

I

_-:----1 :
I
I

~TaVaV~
,

I.+-:

DO/WDI ===D=AT.=A=O=U=T==}----{ :

I

I

I

I

I

WRITE DATA IN

,..

x=
., ,- .,
....J~,..,""""::I~~~-~,...~'T"~-rir--C-B-x=

TRLSX

SYO/CBO _ _ _ _S_YN_ _ _ _ _

J.I

'~+iELAI
---------..,...Jj
,

1~1:""----

TaXaX~

7P

PPO(SLAVE) - - - - - - - - - . . . ; . . . . . .
PPI (MASTER)

/f

:

,

VALID

TPVSV

:

I

I

8-16

Main Memory Device

WAVEFORMS (Continued)

:E
c

READ MODIFY WRITE - 16-BIT ONLY

STB

jI

t 'F-l___________

I 1••-----TIVSL-----t_~1

1.......i----TSLlX----i.~1

I+I,

I

TSHIV·-+I

R/W

I

=:?f

I

_______-----,fil----r-:--

~

, I
I
1-t1-----TovRL---~..~,I.--TRvsv___.J

I

I

I

I
I
II
__~i~:--~-------~-L-,O-r:----~:-------~
I

I

I'

,

I I

I

01
I
CBI ~

I

!.-TBHQV. . .' :

I !
I

VALID

~

I

tRHSX~

TBLQZ-+/

II

).

I t. I
1 I

I

I

I

I&.oII
..t-----TRHQV

I

I

---ti-"

I

_,

I

J

I

TOXQX....J

14-,

I I
I I

t-:_ _ _ _
TO_VQ_V--c@!?IT

1
......t - - - - - T R V S V - - -••I

I I
I~

TQXQX~

I....- TRLSX

--r----

I

:

I I

,......t-----Tovsv---~.I

Main Memory Device

~

I

--fC

I I I I
SYO/CBO

I

,

I~I------~I--~I----~~------I

OO/WOI

o

0)

I

1ooI1
..

BM

co
I\)

SYN~----~-~""-CB
I

I+--TQVQV~

8-17

WAVEFORMS (Continued)

=E

c

READ MODIFY WRITE - MASTER/SLAVE

CO
N

o

en

R/W

BM

STB

C~:

------J)i
__

'{'---------J/f
1

,

'J4-TRHSX~

!

>Krr

~

I

I

I

I

1

I
II

:

iVALID !

I

I

TDVSV~

:

:

I

I

I ~TRVSV--+I

I

I

I

TIVSL

_I

4

I
I

: ~

I
, I

ii
I ,

1 TRVSV

-I-

I 1

-I

p:::~::, =rzR~D7 {~ : VALID )(w)lg
1 TP~SV

,4 ; _,I

iK

I,

I '

I

I

(~~~~~~) ---t------...:-@:VALID
I

I

.

SYO/CBO(MASTE~ >V~
SYI (SLAVE)

I

I !PVS~ I

I

~TPVQV"""

SYN

ITSVQV
,

1

r

1 ,

I 1

~TSVRL

!

!.-TBLQZ----+l

tI

I

I

X

I

I f'+--TBHQV---+t
I
I

..../ ITsHlv
I
1'_ -I-----«

I

I

>07M
I

I

:Yhl
I

CO

k

~TQVQV~
I

~~~~------+-----------~-~--~~--~+---------~-L-ID----------~~~

8-18

Main Memory Device

WAVEFORMS (Continued)
NON·CORRECTING READ

CRCT----------------------~~~I_____________~~-----------

DO/WDI

--------------WA

WRITE ZERO

Wi -----------....."

I

I

I

I

UNCORRECTED

CORRECTED

}UNCORRECTti-

I......I----TWLQL------..~I
I
I

A----I

~
:
~~------------------~I---------~

I
I

I

I+- TQVQV(1) +t

I

I

I
I

I

I
TQVQV(2)----+i

I

DO

0'#///#////////4

~

~

I

I

I

I

I
I

I
I

~

V-

I

p:~:~~~::/W
AW/ff///#//7/M

VALID

--.J·TPVSV~

I

I

ff//P',0//7# U~/M

~
I

I

SYOICB0o/

WZ

I TRHSX

I

NOTE:

~TWHQX

I

x=
I

"AUD

(1): 16-BIT ONLY
(2): MASTER/SLAVE

Main Memory Device

8-19

8-20

Main Memory Device

DIGITAL

WESTERN

c

ORPORAT

0

N

=E

c

CD

WD93020 Integrated Drives

(,.)

o
N
o

WD93020 INTEGRATED DRIVES

BASIC CONTROLLER FEATURES:

Western Digital's initial peripheral subsystem offer·
ing, the WD93020 series of integrated disk drives,
adds all disk controller functions to a 20 megabyte
Winchester disk drive. Eliminating the requirement for
a separate controller card, the subsystem's small size
and attractive price make it economically feasible to
use Winchester disk drive technology into applica·
tions like portable personal computers or low cost
home computers. Western Digital Integrated Drive
models are configured with a popular selection of
host computer plug compatible interfaces: SCSI, IBM
PC·XT, and IBM PC·AT.

•

PLUG COMPATIBLE INTERFACES: SCSI, IBM PCXT, AND IBM PC-AT.

•

MODIFIED FREQUENCY MODULATION (MFM)
ENCODING

•

PROGRAMMABLE SECTOR INTERLEAVE FOR
CONSECUTIVE SECTOR TRANSFERS: 2:1
INTERLEAVE ON PC INTERFACES; 1:1
INTERLEAVE ON SCSI INTERFACES.

•

BUILT·IN SELF·TEST AND DIAGNOSTIC
CAPABILITIES COVERING BOTH DRIVE AND
CONTROLLER OPERATION.

BASIC DRIVE FEATURES:

•

IMPROVES DATA RELIABILITY BY INCOR·
PORATING ONBOARD DATA SEPARATION.

•

TWO·PLATTER, 3.5·INCH, FIXED MEDIA DISK
DRIVE.

•

AUTOMATIC WRITE PRECOMPENSATION.

•

A FORMATTED DATA CAPACITY OF 20
MEGABYTES.

•

ATIXT • SUPPORTS MULTIPLE TRACK/CYLINDER
READIWRITE.

•

A SINGLE PRINTED CIRCUIT BOARD ASSEMBLY.

•

SCSI· SUPPORTS BLOCK MODE TRANSFER.

•

AN AVERAGE ACCESS TIME OF 85
MILISECONDS.

•

ERROR DETECTION AND CORRECTION
CAPABILITY USING A 32·BIT POLYNOMIAL.

•

POWER DISSIPATION OF LESS THAN 12 WATTS.

•

•

UP TO 850 TRACKS PER INCH.

THE SCSI INTERFACE HAS FULL IMPLEMENTA·
TION OF THE SCSI PROTOCOL INCLUDING
DISCON N ECT/RECON N ECT.

•

A 40·PIN, SINGLE CABLE CONNECTION FOR
TH E I BM PC MODELS.

Integrated Drive Electronics

9-1

INTEGRATED DRIVE SPECIFICATIONS

=e

c

CO

w
o
N
o

TECHNOLOGICAL CHARACTERISTICS

CAPACITY - Formatted
- Unformatted
CYLINDERS
TRACK CAPACITY
NUMBER OF DISKS
MEDIA
RECORDING SURFACES
READjWRITE HEADS
HEAD POSITIONER
ENCODING METHOD

20.0 Megabytes
25.5 Megabytes
612
10,416 Bytes

2
Ferrous Oxide or Thin Film
4
4
Stepper Motor
Modified-frequency Modulation

PERFORMANCE CHARACTERISTICS

SEEK - Track to Track
- Average
- Maximum
ROTATIONAL LATENCY
HEAD SETTLING
TRANSFER RATE

15 Milliseconds
85 Milliseconds
150 Milliseconds
8.6 Milliseconds
Included in Seek Times
5.0 Megabits per Second

RELIABILITY

CORRECTED ERROR RATES - Hard
Read retries and
- Soft
ECC Enabled
- Seek
RAW ERROR RATES - Hard Errors
- Soft Errors
- Seek Errors
MTBF
PREVENTIVE MAINTENANCE
SERVICE LIFE
MTTR

1 in 10-13
1 in 10-11

NIA

1 in 10-12
1 in 10-10
1 in 10-6
15,000 Power-On-Hours
None
5 Years
30 Minutes

PHYSICAL CHARACTERISTICS

SIZE - Height
- Width
- Depth
WEIGHT
DC POWER - Input Voltage
- Maximum Start
HEAT DISSIPATION

41.0 mm. (1.614 in.)
101.0 mm. (3.976 in.)
129.5 mm. (5.100 in.)
1.2 Lbs.
+5 VDC ± 5% @0.8 Amps Typ.
+ 12 VDC ± 5% @ 0.7 Amps Typ.
2 Amps @ +5 VDC
1 Amp @ +12 VDC
12 Watts Average

ENVIRONMENTAL CHARACTERISTICS

TEMPERATURE - Operating
- Non-operating
- Gradient
RELATIVE HUMIDITY
MAXIMUM WET BULB
SHOCK - Operating
- Non-operating
VIBRATION - Operating
- Non-operating
ALTITUDE - Operating
- Non-operating

4°-50°C (40°-122°F)
-40°-60°C (-40°-140°F)
± 10°C/Hour (± 18°F/Hour)
8 - 90% No Condensation
76°F Non-condensing
10 G 10 ms Half Sine Wave
50 G 10 ms Half Sine Wave
2 - 10 Hz 0.1 in. Dbl Amplitude
10 - 500 Hz 0.5 G (O-P)
2 - 10 Hz O.4in. Dbl Amplitude
10 - 500 Hz 2.0 G (O-P)
-1,000 - 10,000 Feet
-1,000 - 50,000 Feet

Specifications and features are subject to change without notice.

9-2

Integrated Drive Electronics

:E
c

Address Bus

CO

r--'I

WD10C20A
Data Separator
and PLL

RAM

: Host
• Bus

w
o
N
o

Servo Data
Spin
Motor
WD6002

DAC

Control

---r--DAC

I
L._~

: Servo

i Drivers

WD60C01
Servo.
Control

Spindle
Motor
Control

WD93020 INTEGRATED DRIVE ELECTRONICS (TYPICAL)

Integrated Drive Electronics

9-3

9-4

Integrated Drive Electronics

ORDERING INFORMATION
OBSOLETE PACKAGE DESIGNATIONS
A
B
C
E
F
J
K
L
M
P
R
T
U
V
X
Y

40
40
24
28
28
16
16
18
18
40
28
48
20
20
20
20

Lead DIP·Ceramic
Lead DIP·Relpak
Lead DIP·Ceramic
Lead DIP·Ceramic
Lead DIP·Relpak
Lead DIP·Ceramic
Lead DIP·Plastic (Totally
Lead DIP·Ceramic
Lead DIP·Plastic (Totally
Lead DIP·Plastic (Totally
Lead DIP·Plastic (Totally
Lead DIP·Ceramic
Lead DIP·Ceramic
Lead DIP·Plastic (Totally
Ceramic KIT
Plastic KIT

CURRENT PACKAGE DESIGNATIONS
PACKAGE TYPE:
A Ceramic DIP
P Plastic DIP
C Cerdip DIP
D Ceramic QUAD
J Plastic QUAD

LEAD COUNT:
A
<14 Lead
D
18 Lead
E
20 Lead
22 Lead
F
H
28 Lead
40 Lead
L
44 Lead
M
N
48 Lead
T
68 Lead

Encapsulated)
Encapsulated)
Encapsulated)
Encapsulated)

Encapsulated)

Example of obsolete method:
WD1943MOO Where M
Single Digit
Package Designator (M = 18 Lead Plastic)

Example of current method:
WD1943PDOO Where PD
Double Digit
Package Designator (P
Plastic and D

=
=

=

= 18 Lead)

The following listing indicates the available packages for each product.

WD1010·0S

PL,

AL

WD1014·00

PL,

AL

WD101S·02,10,24

PL,

AL

WD10C20

PH,

AH

DM,

JM

DM,

JM

DH,

JH

or

WD10S0-00
WD1100·01

PE,

AE

WD1100·03

PE,

AE

WD1100-04

PE,

AE

WD1100·0S

PE,

AE

WD1100·06

PE,

AE

WD1100-07

PE,

AE

WD1100-09

PE,

AE

WD1100-12

PE,

AE

WD11COO·13

PE,

AE

WD1100-21

DH,

JH

AL

or

WD11COO·17
WD1691-00

PE,

AE,

WD16C92

PL,

AL

WD1770,72,73

PH,

AH

WD1771-01

PL,

AL

Ordering Information

QSM
QUAD SURFACE MOUNT

DIP
DUAL IN-LINE PACK.

PRODUCT

CE

DH,

JH

10·1

F0179X-02

PL,

AL

WD2010-05

PL,

AL

WD2143-03

PO,

AD,

WD2401

PL,

AL

WD24C02

PL,

AL

WD279X-02

PL,

AL

WD33C92

PN,

WD33C93

PL,

OM,

JM

AN

OM,

JM

AL

OM,

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11-3

Component Products
Terms and Conditions
1.

ACCEPTANCE: Unless otherwise provided, it is agreed that sales are made on the terms, conditions and warranties contained herein and that to
the extent of any conflict, the same take precedence over any terms or conditions which may appear on Buyer's order form. Seller shall not be
bound by Buyer's terms and conditions unless expressly agreed to in writing. In the absence of written acceptance of these terms, acceptance of
or payment for any of the articles covered hereby shall constitute an acceptance of these terms and conditions.

2.

F.O.B. POINT: All sales are made F.O.B. point of shipment. Seller's title passes to Buyer and Seller's liability as to delivery ceases upon mak·
Ing delivery of articles purchased hereunder to carrier at shipping point In good condition; the carrier acting as Buyer's agent. All claims
for damages must be filed with the carrier. Unless specific Instructions from Buyer specify which method of shipment Is to be used, the
Seller will exercise his own discretion,

3.

DELIVERY: Shipping dates are approximate only, Seller shall not be liable for any loss or expense (consequential or otherwise) Incurred by
Buyer If Seller falls to meet the specified delivery schedule because of unavoidable production or other delays. Seller may deliver the articles
In Installments, Seller shall not be liable for any delay In delivery or for non-dellvery, In whole or In part, caused by the occurrence of any
contingency beyond the control either of Seller or Seller's suppliers, Including, by way of illustration but not limitation, war (whether an actual
declaration thereof Is made or not), sabotage, Insurrection, riot or other act of civil disobedience, act of public enemy, failure or delay In transpor·
tation, act of any government or any agency or subdivision thereof, judicial action, labor dispute, accident, fire, explosion, flood, storm or
other act of God, shortage of labor, fuel, raw material or machinery or technical failure where Seller has exercised ordinary care In the prevention thereof. If any contingency occurs, Seller may allocate production and deliveries among Seller's customers.

4.

TERMS AND METHODS OF PAYMENT: Where seller has extended credit to Buyer, terms of payment shall be net thirty (30) days from date
of Invoice, The amount of credit or terms of payment may be changed or credit withdrawn by Seller at any time, If the articles are delivered
In Installments, Buyer shall pay for each Installment In accordance with the terms hereof. Payment shall be made for the articles without
regard to whether Buyer has made or may make any Inspection of the articles. If shipments are delayed by Buyer, payments are due from
the date when Seller has prepared to make shipments. Articles held for Buyer are at Buyer's sole risk and expense.

5.

TAXES: All prices are exclusive of all federal, state and local excise, sales, use, and similar taxes; when applicable to this sale or to the articles
sold, will appear as separate additional Items on the invoice unless Seller receives a properly executed exemption certificate from Buyer
prior to shipment.

6.

PATENTS: The Buyer shall hold the Seller harmless against any expense or loss resulting from infringement of patents or trademarks arising
from compliance with Buyer's designs or specifications or instructions. The sale of products by the Seller does not convey any license, by
implication, estoppel, or otherwise, under patent claims covering combinations of said products with other devices or elements. Except as
otherwise provided In the preceding paragraph, the Seller shall defend any suit or proceeding brought against the Buyer so far as based on
a claim that any product, or any part thereof, furnished under this contract constitutes an infringement of any patent of the United States,
If notified promptly in writing and given authority, Information and assistance (at the Seller's expense) for the defense of same, and the Seller
shall pay all damages and costs awarded therein against the Buyer. In case said product, or any part thereof, is In such suit held to constitute
infringement and the use of said product or part Is enjoined, the Seller, shall at its own expense, either procure for the Buyer the right to
continue using said product or part, or replace same with non-infringing product, or modify It so It becomes non- infringing, or remove said
product and refund the purchase price and the transportation and Installation costs thereof. The foregoing states the entire liability of the
Seller for patent Infringement by the said products or any part thereof.

7.

ASSIGNMENT: The Buyer shall not assign his order or any interest therein or any rights thereunder without the prior written consent of Seller.

8.

WARRANTY: Seller warrants articles of its manufacture against materials or workmanship for a period of one year from date on which Seller
delivers said articles. The liability of Seller under this warranty is limited at Seller's option, solely to repair, replacement with equivalent articles,
or an appropriate credit adjustment not to exceed the original sales price of articles returned to the Seller provided that (a) Seller is promptly
notified In writing by Buyer upon discovery of defects, (b) the defective article Is returned to Seller, transportation charges prepaid by Buyer,
and (c) Seller's examination of such article disclosed to its satisfaction that defects were not caused by negligence, misuse, improper Installation, accident, or unauthorized repair or alteration by the Buyer. In the case of equipment articles, this warranty does not include mechanical
parts falling from normal usage nor does It cover limited life electrical components which deteriorate with age. In the case of accessories,
not manufactured by Seller, but which are furnished with the Seller's equipment, Seller's liability Is limited to whatever warranty is extended
by the manufacturers thereof and transferable to the Buyer. This Warranty is expressed In lieu of all other Warranties, expressed or Implied,
including the Implied Warranty of fitness for a particular purpose, and of all other obligations or liabilities on the Seller's part, and It neither
assumes nor authorizes any other person to assume for the Seller any other liabilities. This Warranty should not be confused with or construed to Imply free preventative or remedial maintenance, calibration or other service required for normal operation of the equipment articles.
These Warranty provisions do not extend the original Warranty period of any article which has either been repaired or replaced by Seller.
In no event will Seller be liable for any incidental or consequential damages.

9.

TERMINATION: Buyer may terminate this contract In whole or from time to time In part upon 60 days written notice to Seller. In such event
Buyer shall be liable for termination charges which shall Include a price adjustment based on the quantity of articles actually delivered, and
all costs, direct and Indirect, Incurred and committed for this contract together with a reasonable allowance for pro-rated expenses and profits. Any termination or back off in scheduling will not be allowed on shipments scheduled for the month In which the request is made and
for the month following.

10. GOVERNMENT CONTRACTS: If the articles to be furnished under this contract are to be used In the performance of a Government contract
or subcontract and a Government contract number shall appear on Buyer's purchase order, those clauses of the applicable Government procurement regulation which are mandatorialy required by Federal Statute to be Included In Government subcontracts shall be incorporated
herein by reference.
11 • ORIGIN OF ARTICLES:Selier engages In off-shore production, assembly and / or proceSSing and makes no warranty or representation, expressed
or implied, that the articles delivered hereunder are United States articles or of U.S. origin for the purpose of any statute, law, rule, regulation
or case thereunder. If Buyer ships the articles hereunder out of the U.S. for assembly, then at Buyer's request in writing, Seller shall provide
information applicable to identification of any articles not of U.S. origin.

11-5

Published by Software Publishing & Packaging, Inc. 1333 East Thousand Oaks Blvd. Thousand Oaks, CA 91362 805·495·7423

11-6

~.
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