1986_TI_2 Um_CMOS_Standard_Cell_Data_Book 1986 TI 2 Um CMOS Standard Cell Data Book
User Manual: 1986_TI_2-um_CMOS_Standard_Cell_Data_Book
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SRSDOOl
~
t
CMOS
g Standard Cell
Data Book
2-p,tn
1986
•
•
TEXAS
INSTRUMENTS
General Information
L . . - . . - - ._ _ _
Definitions, Ratings, and Glossary
Product Guide
Data Sheets
Military
IEEE Symbols
Design Considerations
Mechanical Data
II
2-/Lm CMOS
Standard Cell
Data Book
SystemCellTM Series
TEXAS
INSTRUMENTS
IMPORTANT NOTICE
Texas Instruments (Til reserves the right to make changes in the
devices or the device specifications identified in this publication
without notice. TI advises its customers to obtain the latest version
of device specifications to verify, before placing orders, that the
information being relied upon by the customer is current.
TI warrants performance of its semiconductor products, including SNJ
and SMJ devices, to current specifications in accordance with TI's
standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems such testing necessary to support this
warranty. Unless mandated by government requirements, specific
testing of all parameters of each device is not necessarily performed.
In the absence of written agreement to the contrary, TI assumes no
liability for TI applications assistance, customer's product design, or
infringement of patents or copyrights of third parties by or arising from
use of semiconductor devices described herein. Nor does TI warrant
or represent that any license, either express or implied, is granted
under any patent right, copyright, or other intellectual property right
of TI covering or relating to any combination, machine, or process in
which such semiconductor devices might be or are used.
Specifications contained in this data book supersede all data for these
products published by TI in the United States before September 1986.
ISBN 0-89512-198-0
Copyright © 1986, Texas Instruments Incorporated
PREFACE
This data book contains a wealth of information to assist you in designing an Application-Specific IC (ASIC)
using TI's new, 2-flm CMOS standard cell family - called SystemCell"'. Included are; a selection guide, a crossreference guide, a definition of symbols and glossary of common terms, a section on design guidelines, detailed
mechanical data on the extensive range of SystemCell'" package options and, comprehensive, detailed data sheets
covering more than 320 cell types including:
•
SSI logic functions ("gates")
•
MSI logic functions ("macros")
•
I/O cells
•
Boolean functions
•
CompilerCell'" functions (SRAM, ROM, PLA
and Pipeline Test Register)
Fabricated in TI's advanced 2-l-'m (1.6-flm effective), double-level metal (DLM), twin-well, silicon-gate CMOS
technology, ICs designed with the SystemCell'· family can offer many significant benefits.
•
Lower system ,cost
•
Increased functionality
•
Unique, secure product designs
•
Shorter "product-to-market" times
•
Reduced package count and board space
•
Improved reliability
The advanced CMOS technology and high-volume production processes developed to support TI' s high-density
memory products provide the "driving force" behind the significant performance and density advances embodied
in the new SystemCell'" family. Using this approach, minimum feature sizes, an inverse indicator of performance
and complexity, have been successfully reduced from 3-flm used in the CircuitCeW" family to 2-flm in the
SystemCell'· family, with a 1-flm family already on the horizon!
In designing the SystemCell'" family, TI's ASIC development team was directed by the people who made TTL
an industry standard and who then went on to invent Low Power Schottkyt (LS-TTL). They were determined
that TI's standard cell products should be easier to design with, and as well specified as conventional standard
logic circuits.
Designers familiar with the industry standard SN54/74 TTL functions will immediately appreciate the easy
transition to standard cell deSign. These same popular logic functions are replicated in TI's standard cell libraries.
Wherever possible, the same function number as the standard product has been used. For example, if the 'LS244
is the function you need, simply select the' ASC244-it's the same function!
The similarity with industry standard logic functions does not end with type numbers. Each individual SystemCell'"
data sheet presents the cell data in a format similar to the corresponding standard device data sheet and contains
comprehensive, solid specifications (min's and max's over the full temperature range, not just typical values).
In fact, just like TTL and LS-TTL, TI's SystemCell'" family provides data you can depend on!
From design concept to a completed design, TI's Regional Technology Centers offer a worldwide network of
customer and design support services. Local design support capabilities also are available through TI's authorized
ASIC distributors across North America. In addition, SystemCell'" is supported on many of the popular engineering
workstations to allow maximum utilization of existing in-house design tools for those wishing to complete the
design themselves.
To learn more about TI's SystemCell'" family, the most comprehensively specified, fastest growing cell library
in the industry, please read on.
t Integrated
Schottky-Barrier diode-clamped transistor is patented by Texas Instruments, U.S. Patent Number 3,463,975
v
vi
ALPHANUMERIC INDEX
ALPHANUMERIC INDEX
PAGE
SN54ASCOO
SN54ASC02
SN54ASC04
SN54ASC08
SN54ASC10
SN54ASC11
SN54ASC20
SN54ASC21
SN54ASC27
SN54ASC30
SN54ASC32
SN54ASC74
SN54ASC75
SN54ASC85
SN54ASC86
SN54ASC109
SN54ASC137
SN54ASC138
SN54ASC139
SN54ASC151
SN54ASC153
SN54ASC155
SN54ASC157
SN54ASC158
SN54ASC161A
SN54ASC163A
SN54ASC164
SN54ASC165
SN54ASC166
SN54ASC173
SN54ASC174
SN54ASC175
SN54ASC177
SN54ASC181
SN54ASC191
SN54ASC193
SN54ASC194A
SN54ASC195A
SN54ASC244
SN54ASC245
SN54ASC251
SN54ASC257A
SN54ASC258A
SN54ASC259
SN54ASC260
SN54ASC266
SN54ASC273
SN54ASC279
SN54ASC280
SN54ASC283
SN54ASC298
SN54ASC299
SN54ASC299X
SN54ASC373
SN54ASC374
SN54ASC375
SN54ASC393
SN54ASC398
SN54ASC399
SN74ASCOO ..... ... ......
SN74ASC02 ... .... ..... " ..
SN74ASC04 ..... , .........
SN74ASC08
SN74ASC10
SN74ASC11
SN74ASC20 .. , ..... , ......
SN74ASC21
SN74ASC27
SN74ASC30
SN74ASC32
SN74ASC74 ...........
SN74ASC75 ..... ........
SN74ASC85
............
SN74ASC86 ...............
SN74ASC109 ..............
SN74ASC137 ......... ....
SN74ASC138 ..............
SN74ASC139 .. ' , ..........
............
SN74ASC151
SN74ASC153 ..............
SN74ASC155 ..............
, SN74ASC157
.........
SN74ASC158 ..............
SN74ASC161A .............
SN74ASC163A .............
SN74ASC164 ..............
SN74ASC165 ..............
SN74ASC166 ..............
SN74ASC173 ..............
SN74ASC174 ...... ........
SN74ASC175 ........... ...
SN74ASC177 ....... , ......
SN74ASC181 .... " .........
SN74ASC191
SN74ASC193 .... " .........
SN74ASC194A ....... ......
SN74ASC195A ......... ....
SN74ASC244 . . . . . . . . . . . . . .
SN74ASC245 ..............
SN74ASC251 ..............
SN74ASC257A .............
SN74ASC258A .............
SN74ASC259
.... .......
SN74ASC260 ....... .......
SN74ASC266 ...... ........
SN74ASC273 ..... . . . . . . . . .
SN74ASC279 ..............
SN74ASC280 ..............
SN74ASC283
. . . . .......
SN74ASC298 ...... .... ....
SN74ASC299 ............
SN74ASC299X .............
SN74ASC373 ..............
SN74ASC374 ..............
SN74ASC375 ..............
SN74ASC393
.... ........
SN74ASC398 ............ ..
SN74ASC399 ..... .........
"
"
"
"
"
4-3
4-7
4-11
4-15
4-19
4-23
4-27
4-31
4-35
4-37
4-39
4-43
4-55
4-59
4-65
4-67
4-71
4-77
4-81
4-85
4-89
4-93
4-97
4-101
4-105
4-113
4-121
4-127
4-133
4-141
4-147
4-151
4-155
4-161
4-169
4-177
4-185
4-191
4-197
4-201
4-207
4-211
4-215
4-219
4-225
4-227
4-229
4-233
4-235
4-239
4-245
4-251
4-257
4-263
4-267
4-271
4-277
4-281
4-285
SN54ASC590
SN54ASC593X
SN54ASC595
SN54ASC598X
SN54ASC651
SN54ASC652
SN54ASC669
SN54ASC686
SN54ASC688
SN54ASC888
SN54ASC890
SN54ASC2022
SN54ASC2024
SN54ASC2102
SN54ASC2108
SN54ASC2310
SN54ASC2311
SN54ASC2320
SN54ASC2321
SN54ASC2322
SN54ASC2325
SN54ASC2330
SN54ASC2331
SN54ASC2340
SN54ASC2341
SN54ASC2342
SN54ASC2350
SN54ASC2370
SN54ASC2371
SN54ASC2372
SN54ASC2373
SN54ASC2374
SN54ASC2401
SN54ASC2402
SN54ASC2403
SN54ASC2404
SN54ASC2405
SN54ASC2406
SN54ASC2407
SN54ASC2408
SN54ASC2500
SN54ASC2502
SN54ASC2503
SN54ASC2507
SN54ASC2508
SN54ASC2519
SN54ASC2901
SN54ASC2902
SN54ASC2904
SN54ASC2910
SN54ASC3003
SN54ASC3004
SN54ASC3005
SN54ASC3006
SN54ASC3010
SN54ASC3011
SN54ASC3103
SN54ASC3200
SN54ASC3430
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74ASC590 .....
SN74ASC593X ....
'SN74ASC595 . . . . . . . . .
SN74ASC598X
SN74ASC651
SN74ASC652
SN74ASC669
SN74ASC686
SN74ASC688
..........
SN74ASC888
.........
SN74ASC890
SN74ASC2022
SN74ASC2024
SN74ASC2102
SN74ASC2108
SN74ASC2310
SN74ASC2311
SN74ASC2320
SN74ASC2321
SN74ASC2322
SN74ASC2325 . ............
SN74ASC2330
SN74ASC2331
SN74ASC2340
SN74ASC2341
SN74ASC2342 ............ ,
. .... , .....
SN74ASC2350
SN74ASC2370 . .... " ' ......
SN74ASC2371
. ........
SN74ASC2372
SN74ASC2373 ...... " .....
SN74ASC2374 .............
SN74ASC2401 .............
SN74ASC2402 . ... , ........
SN74ASC2403 .............
..........
SN74ASC2404
.........
SN74ASC2405
..........
SN74ASC2406
SN74ASC2407
SN74ASC2408
SN74ASC2500
SN74ASC2502 .............
SN74ASC2503 .............
SN74ASC2507 .............
SN74ASC2508 .............
SN74ASC2519 .............
SN74ASC2901 . ............
SN74ASC2902 . ............
SN74ASC2904 . ............
SN74ASC2910 .............
SN74ASC3003 .............
SN74ASC3004 · ............
SN74ASC3005 · ............
SN74ASC3006 . ............
SN74ASC3010 · ............
SN74ASC3011
SN74ASC3103 .............
SN74ASC3200 ....... ....
SN74ASC3430 .............
"
PAGE
4-289
4-295
4-303
4-307
4-315
4-315
4-327
4-333
4-339
4-343
4-347
4-349
4-351
4-353
4-359
4-363
4-367
4-371
4-373
4-377
4-381
4-383
4-385
4-387
4-389
4-391
4-393
4-397
4-399
4-401
4-403
4-405
4-407
4-407
4-407
4-407
4-413
4-413
4-413
4-419
4-423
4-425
4-427
4-429
4-431
4-433
4-435
4-437
4-439
4-441
4-443
4-443
4-443
4-443
4-451
4-453
4-455
4-461
4-463
vii
'ALPHANUMERIC INDEX
PAGE
SN54ASC3800
SN54ASC4002
SN54ASC4072
SN54ASC4075
SN54ASC4078
SN54ASC5000
SN54ASC5001
SN54ASC5002
SN54ASC5003
SN54ASC5004
SN54ASC5005
SN54ASC5006
SN54ASC5007
SN54ASC5010
SN54ASC5013
SN54ASC5100
SN54ASC5103
SN54ASC5104
SN54ASC5105
SN54ASC5106
SN54ASC5107
SN54ASC5108
SN54ASC5109
SN54ASC5110
SN54ASC5111
SN54ASC5120
SN54ASC5121
SN54ASC5123
SN54ASC5124
SN54ASC5125
SN54ASC5200
SN54ASC5201
SN54ASC5202
SN54ASC5203
SN54ASC5206
SN54ASC5207
SN54ASC5217
SN54ASC5220
SN54ASC5221
SN54ASC5226
SN54ASC5227
SN54ASC5239
SN54ASC5246
SN54ASC5250
SN54ASC6002
SN54ASC6003
SN54ASC6004
SN54ASC6005
SN54ASC6006
SN54ASC6007
SN54ASC6008
SN54ASC6009
SN54ASC6012
SN54ASC6013
SN54ASC6014
SN54ASC6017
SN54ASC6018
SN54ASC6019
viii
SN74ASC3800
SN74ASC4002
SN74ASC4072
SN74ASC4075
SN74ASC4078
SN74ASC5000
SN74ASC5001
SN74ASC5002
SN74ASC5003
SN74ASC5004
SN74ASC5005
SN74ASC5006
SN74ASC5007
SN74ASC5010
SN74ASC5013
SN74ASC5100
SN74ASC5103
SN74ASC5104
SN74ASC5105
SN74ASC5106
SN74ASC5107
SN74ASC5108
SN74ASC5109
SN74ASC5110
SN74ASC5111
SN74ASC5120
SN74ASC5121
SN74ASC5123
SN74ASC5124
SN74ASC5125
SN74ASC5200
SN74ASC5201
SN74ASC5202
SN74ASC5203
SN74ASC5206
SN74ASC5207
SN74ASC5217
SN74ASC5220
SN74ASC5221
SN74ASC5226
SN74ASC5227
SN74ASC5239
SN74ASC5246
SN74ASC5250
SN74ASC6002
SN74ASC6003
SN74ASC6004
SN74ASC6005
SN74ASC6P06
SN74ASC6007
SN74ASC6008
SN74ASC6009
SN74ASC6012
SN74ASC6013
SN74ASC6014
SN74ASC6017
SN74ASC6018
SN74ASC6019
...... .......
... ...... ....
... ...... ....
.......... , ..
............
.............
........ .....
'
........
, ,
...
...... ......
.............
· ............
· ............
'
.............
...... .... ...
.... .........
.............
·............
.............
· . .- . . . . . . . . .
.... .........
.... ... ......
·.... . . .....
.. ...... .....
· ............
.
.............
.............
.............
... ...... ....
.... ... ......
......... ....
.............
.............
· ............
.............
... ...
....
... .... ... ...
....... ... ...
'"
· ............
.............
· . . . . . . . . . . -.
....... ... ...
.. ..... ......
.... .... .....
......... ....
.............
.............
.............
.............
· ............
........ .....
· ............
.............
.............
... ...... ....
.............
..... .......
...... .......
· ............
4-465
4-467
4-469
4-473
4-477
4-479
4-481
4-483
4-485
4-487
4-489
4-491
4-493
4-495
4-497
4-499
4-503
4-507
4-511
4-513
4-517
4-521
4-523
4-525
4-529
4-533
4-537
4-541
4-543
4-547
4-551
4-555
4-559
4-563
4-567
4-571
4-575
4-579
4-583
4-587
4-591
4-595
4-599
4-603
4-607
4-609
4-611
4-613
4-615
4-617
4-619
4-621
4-623
4-625
4-627
4-629
4-631
4-633
SN54ASC6022
SN54ASC6023
SN54ASC6024
SN54ASC6025
SN54ASC6026
SN54ASC6027
SN54ASC6028
SN54ASC6029
SN54ASC6032
SN54ASC6034
SN54ASC6035
SN54ASC6048
SN54ASC6049
SN54ASC6052
SN54ASC6053
SN54ASC6054
SN54ASC6055
SN54ASC6056
SN54ASC6057
SN54ASC6058
SN54ASC6059
SN54ASC6062
SN54ASC6063
SN54ASC6064
SN54ASC6065
SN54ASC6066
SN54ASC6067
SN54ASC6068
SN54ASC6069
SN54ASC6072
SN54ASC6073
SN54ASC6074
SN54ASC6075
SN54ASC6082
SN54ASC6083
SN54ASC6084
SN54ASC6088
SN54ASC6100
SN54ASC6101
SN54ASC6102
SN54ASC6103
SN54ASC6105
SN54ASC6106
SN54ASC6108
SN54ASC6110
SN54ASC6111
SN54ASC6112
SN54ASC6113
SN54ASC6115
SN54ASC6116
SN54ASC6118
SN54ASC6120
SN54ASC6121
SN54ASC6122
SN54ASC6125
SN54ASC6130
SN54ASC6131
SN54ASC6132
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74ASC6022
SN74ASC6023
SN74ASC6024
SN74ASC6025
SN74ASC6026
SN74ASC6027
SN74ASC6028
SN74ASC6029
SN74ASC6032
SN74ASC6034
SN74ASC6035
SN74ASC6048
SN74ASC6049
SN74ASC6052
SN74ASC6053
SN74ASC6054
SN74ASC6055
SN74ASC6056
SN74ASC6057
SN74ASC6058
SN74ASC6059
SN74ASC6062
SN74ASC6063
SN74ASC6064
SN74ASC6065
SN74ASC6066
SN74ASC6067
SN74ASC6068
SN74ASC6069
SN74ASC6072
SN74ASC6073
SN74ASC6074
SN74ASC6075
SN74ASC6082
SN74ASC6083
SN74ASC6084
SN74ASC6088
SN74ASC6100
SN74ASC6101
SN74ASC6102
SN74ASC6103
SN74ASC6105
SN74ASC6106
SN74ASC6108
SN74ASC6110
SN74ASC6111
SN74ASC6112
SN74ASC6113
SN74ASC6115
SN74ASC6116
SN74ASC6118
SN74ASC6120
SN74ASC6121
SN74ASC6122
SN74ASC6125
SN74ASC6130
SN74ASC6131
SN74ASC6132
· ............
.............
.............
.............
.............
. ......... ' "
.............
.............
. ...........
'
. .... , .......
. ............
. ............
.............
.............
............
'
.............
. ............
..... , .......
...... , ......
.............
.............
.............
·....... ....
. ............
.
. ............
. ............
.............
.............
.............
. ............
. ............
. ............
. ............
.............
.............
.............
. ............
.............
· .- ...........
.............
.............
.............
. ............
. ............
· ...........
. ............
.............
.............
~-
.............
. ............
. ............
.............
. ............
.............
.............
.............
PAGE
4-635
4-637
4-639
4-641
4-643
4-645
4-647
4-649
4-651
4-653
4-655
4-657
4-659
4-661
4-663
4-665
4-667
4-669
4-671
4-673
4-675
4-677
4-679
4-681
4-683
4-685
4-687
4-689
4-691
4-693
4-695
4-697
4-699
4-701
4-703
4-705
4-707
4-709
4-711
4-713
4-715
4-717
4-719
4-721
4-725
4-727
4-731
4-733
4-737
4-739
4-741
4-745
4-747
4-749
4-751
4-755
4-757
4-759
CROSS· REFERENCE INDEX
CELL CROSS·REFERENCE
CELL NAME
AMC12LH
AN210LH
AN220LH
AN240LH
AN260LH
AN310LH
AN320LH
AN340LH
AN360LH
AN410LH
AN420LH
AN440LH
AN460LH
AN510LH
AN810LH
A0220LH
A0221LH
8F001LH
BF002LH
BF003LH
8F004LH
BF005LH
8F006LH
BF007LH
BF008LH
BF009LH
BF010LH
BFOllLH
BF012LH
BF013LH
BF014LH
BF015LH
BF016LH
BF017LH
BF020LH
BF022LH
BF025LH
8F027LH
BF028LH
BF030LH
BF034LH
BF035LH
BF051LH
BF052LH
BF053LH
BF054LH
BF055LH
BF056LH
BF057LH
BF058LH
BF059LH
BF060LH
BF062LH
BF063LH
BF064LH
BF065LH
BF066LH
BF067LH
BF068LH
BF069LH
DEVICE
PAGE
ASC2519 ................... .
ASCO~ ..................... .
ASC08 ..................... .
ASC08 ........... .
ASC08 ..
ASCII .............. .
ASCII ..................... .
ASCII ........ .
ASCII ..................... .
ASC21 ............. .
ASC21 ................. .
ASC21 ..................... .
ASC21 ..................... .
ASC2024 ................... .
ASC6132 ................... .
ASC2331 ................... .
ASC2330 ..
. ............. .
ASC6017
.............. .
ASC6002
.............. .
ASC6003 . .
. ............. .
ASC6004 ................... .
ASC6005 ........... .
ASC6006 ........... .
ASC6007 ........... .
ASC6008 ............ .
ASC6009 ............ .
ASC6018 ................... .
ASC6019 ................... .
ASC6012 ................... .
ASC6013 ................ .
ASC6014 ................... .
ASC6023 ................... .
ASC6024 ................... .
ASC6026 .. .. ...
. ....... .
ASC6029 ................... .
ASC6022 . . . . . . . . . . . . . . . . . . .
ASC6025 . . ..
. ......... .
ASC6027 ................... .
ASC6028 ........... .
ASC6032 ................ .
ASC6034 ................... .
ASC6035 ................... .
ASC6048 ................... .
ASC6052 ........... .
ASC6053 ........... .
ASC6054 ........ .
ASC6055 ................... .
ASC6056 ................... .
ASC6057 ................... .
ASC6058 . . . . . . . . . . . .
ASC6059 . . .. . . .
. ........ .
ASC6049.
. ....... .
ASC6062 .....
ASC6063 ..
ASC6064 ........ .
ASC6065 ........ .
ASC6066 ........ .
ASC6067 .
ASC6068 . . . . . .
ASC6069 . . . . . . . . . . . . . . . . . . ..
4-433
4-15
4-15
4-15
4-15
4-23
4-23
4-23
4-23
4-31
4-31
4-31
4-31
4-351
4-759
4-385
4-383
4-629
4-607
4-609
4-611
4-613
4-615
4-617
4-619
4-621
4-631
4-633
4-623
4-625
4-627
4-637
4-639
4-643
4-649
4-635
4-641
4-645·
4-647
4-651
4-653
4-655
4-657
4-661
4-663
4-665
4-667
4-669
4-671
4-673
4-675
4-659
4-677
4-679
4-681
4-683
4-685
4-687
4-689
4-691
CELL NAME
BF070LH
BF071LH
BF072LH
BF075LH
BF080LH
BF081LH
BF082LH
BF088LH
BUll0LH
BU111LH
BUl12:'H
BU120LH
BU130LH
BU221LH
BU222LH
BU261 LH
BU262LH
CK4XOLH
C0212LH
C0213LH
COMPILED
COMPILED
COMPILED
COMPILED
DE210LH
DE212LH
DFB20LH
DFC20LH
DFN20LH
DFP20LH
DFY20LH
DFZ20LH
DLC10LH
DLE10LH
DTB10LH
DTC10LH
DTN10LH
DTP10LH
EN210LH
EX210LH
EX220LH
EX240LH
GM010LH
GMll0LH
GM210LH
GM310LH
GM410LH
GM510LH
GMS10LH
GS010LH
GS110LH
GS210LH
GS310LH
GS410LH
GS510LH
GSS10LH
IOEOOLH
IOE40LH
IOE41LH
IOE43LH
. TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
DEVICE
ASC6073.
. .............. .
ASC6074 ...... .
ASC6072 ................... .
ASC6075 .............. .
ASC6083 ................... .
ASC6084 ................... .
ASC6082 .............. .
ASC6088 ................... .
ASC2321 ................... .
ASC2321 ................... .
ASC2321 ................... .
ASC6120 ................... .
ASC6120 ................... .
ASC6121 .................. .
ASC6122 ................... .
ASC6121 ................... .
ASC6122 ................... .
ASC3011 ................... .
ASC2503 ................... .
ASC2503 ................... .
ASC3010 ................... .
ASC3200 ................... .
ASC3430 ................... .
ASC3800 ..
. ........... .
ASC2350 ............... .
ASC2350. . ................ .
ASC74 ... .. ..
. ........... .
ASC74 ......................
ASC74 ......................
ASC74 ......................
ASC74 . .. . ... . . . . . ...
ASC74 ......................
ASC2508 . . . . . . . . . . . . . . . . . . ..
ASC2507 . . . . . . . . . . . . . . . . . . ..
ASC74 ......................
ASC74 .. ... .. ...... ..... . .
ASC74 .. ... .. ... .. . .. ... ..
ASC74 .. . .. . . . ..... ..... .
ASC266 . . . . . . . . . . . . . . . . . . . ..
ASC86 .. . .. . .
. ..........
ASC86 ......................
ASC86 ......................
ASC6100 ....................
ASC6l01 ... . . . . . . . . . .
ASC6103 ....................
ASC6l05 ....................
ASC6106 ....................
ASC6l08 ....................
ASC6l02 ....................
ASC6ll0 ....................
ASC6l11 ....................
ASC6113 ....................
ASC6115 ....................
ASC6116 ....................
ASC6118 ....................
ASC6112 ....................
ASC5220 . . . . . . . . . . . . . . . . . . ..
ASC5200 ....................
ASC5206 . . . . . . . . . . . . . . . . . . ..
ASC5201 ....................
PAGE
4-695
4-697
4-693
4-699
4-703
4-705
4-701
4-707
4-373
4-373
4-373
4-745
4-745
4-747
4-749
4-747
4-749
4-453
4-427
4-427
4-451
4-461
4-463
4-465
4-393
4-393
4-43
4-43
4-43
4-43
4-43
4-43
4-431
4-429
4-43
4-43
4-43
4-43
4-227
4-65
4-65
4-65
4-709
4-711
4-715
4-717
4-719
4-721
4-713
4-725
4-727
4-733
4-737
4-739
4-741
4-731
4-579
4-551
4-567
4-555
ix
CROSS·REFERENCE INDEX
CELL NAME
IOE44LH
IOFOOLH
IOF01LH
IOF03LH
IOF04LH
IOF40LH
IOF41LH
IOF43LH
IOF44LH
IOF47LH
IOF48LH
IOF64LH
IOFB8LH
IOFDOLH
IOFD8LH
IPEOOLH
IPEOl LH
IPE03LH
IPE04LH
IPE05LH
IPE06LH
IPEOBLH
IPE10LH
IPFOOLH
IPF01LH
IPF02LH
IPF03LH
IPF04LH
IPF05LH
IPF06LH
IPF08LH
IPF10LH
IPF12LH
IPF13LH
IV101LH
IVll0LH
IV120LH
IV130LH
IV140LH
IV160LH
IV180LH
IV211LH
IV212LH
IV221 LH
IV222LH
IV241LH
IV242LH
JKB20LH
JKB21LH
LA810LH
LAB20LH
LAH10LH
LAH20LH
LAL20LH
MOl MPLH
M02CGLH
M04SSLH
Ml0MCLH
M88MPLH
M90MCLH
x
DEVICE
ASC5207 ....................
ASC5220 ......•.............
ASC5226 ....................
ASC5221 · ................. , '
ASC5227 ....................
ASC5200 ....................
ASC5206 ....................
ASC5201 · .............
ASC5207 .................. , '
ASC5202 ....................
ASC5203 ....................
ASC5217 ....................
ASC5239 · ...................
ASC5250 ....................
ASC5246 · ...................
ASC5000 ....................
ASC5006 ....................
ASC5001 · .... ' " ...... , .... '
ASC5007 ....................
ASC5005 · ...................
ASC5002 ....................
ASC5003 ........ , ...........
ASC5010 ........ ............
ASC5000 ....................
ASC5006 ....................
ASC5004 ....................
ASC5001 ........ " ..........
ASC5007 ....................
ASC5005 .. , ..... , ' ..........
ASC5002 · , - , . , .... " , .......
ASC5003 .............. ' " ...
ASC5010 ....................
ASC5007 ....................
ASC5013 ... , .............. , .
ASC04 ......................
ASC04 ......................
ASC04 ......................
ASC04 ......................
ASC04 ......................
ASC04 ................ .....
ASC04 .... ... ....... .... ....
ASC2310 ....................
ASC2311 ....................
ASC2310 ....................
ASC2311 ....................
ASC2310 ....................
ASC2311 ...... , .............
ASC109 ., ...................
ASC2108 ....................
ASC279 .... ..... ..... .......
ASC279 .....................
ASC75 .... ... ... ... .... .....
ASC75 ......................
ASC6125 ....................
ASC2901 ....................
ASC2902 ....................
ASC2904 ....................
ASC2910 ....................
ASC888 .....................
ASC890 .....................
PAGE
CELL NAME
4-571
4-579
4-587
4-583
4-591
4-551
4-567
4-555
4-571
4-559
4-563
4-575
4-595
4-603
4-599
4-479
4-491
4-481
4-493
4-489
4-483
4-485
4-495
4-479
4-491
4-487
4-481
4-493
4-489
4-483
4-485
4-495
4-493
4-497
4-11
4-11
4-11
4-11
4-11
4-11
4-11
4-363
4-367
4-363
4-367
4-363
4-367
4-67
4-359
4-233
4-233
4-55
4-55
4-751
4-435
4-437
4-439
4-441
4-343
4-347
MU110LH
MU210LH
MU310LH
MVFOOLH
NA210LH
NA220LH
NA230LH
NA240LH
NA260LH
NA310LH
NA320LH
NA330LH
NA340LH
NA410LH
NA420LH
NA430LH
NA510LH
NA520LH
NA810LH
NA820LH
N0210LH
N0220LH
N0230LH
N0240LH
N0310LH
N0320LH
N0330LH
N0410LH
N0420LH
N0510LH
N0520LH
N0810LH
N0820LH
OPEOOLH
OPE01LH
OPE03LH
OPE40LH
OPE41LH
OPE42LH
OPE43LH
OPE60LH
OPE61LH
OPE63LH
OPFOOLH
OPF01LH
OPF03LH
OPF40LH
OPF41LH
OPF42LH
OPF43LH
OPF60LH
OPF61LH
OPF63LH
OPFBOLH
OPFB3LH
OPFD1LH
OPFD3LH
OPFE1LH
OR210LH
OR220LH
. TEXAS.~
INSTRUMENlS .
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
DEVICE
PAGE
ASC2340 ....................
ASC2341 ....................
ASC2342 ....................
ASC2322 ................ ' .. ,
ASCOO ......................
ASCOO ........................
ASCOO ......................
ASCOO ......................
ASCOO ......................
ASC10 ......................
ASC10 ......................
ASC10 ......................
ASC10 .............. : .......
ASC20 ................ " ....
ASC20 ......................
ASC20 ......................
ASC2022 .. ' " ' ......... , .. , '
ASC2022 ............... , ' .. ,
ASC30 ......................
ASC30 ......................
ASC02 ......................
ASC02 ......................
ASC02 ......................
ASC02 . ................ , ....
ASC27 ......................
ASC27 ., ....................
ASC27 . .....................
ASC4002 · ................. , '
ASC4002 ............... " , ..
ASC260 . . . . . . . . . . . . . . . . . . . . ,
ASC260 . ....................
ASC4078 ....................
ASC4078 ....................
ASC5106 .................. :.
ASC5108 ....................
ASC5107 ...... ..............
ASC5100 ....................
ASC5109 · ...................
ASC5110 ....................
ASC5111 . ...................
ASC5103 ....................
ASC5105 ....................
ASC5104 ....................
ASC5106 ....................
ASC5108 . ...................
ASC5107 ....................
ASC5100 ....................
ASC5109 · . . . . . . , . . . . . . . . . . . .
ASC5110 .. '.' ................
ASC5111 ....................
ASC5103 ....................
ASC5105 ....................
ASC5104 ....................
ASC5120 ....................
ASC5125 ............ , .......
ASC5121 . ...................
ASC5124 ...................
ASC5123 ....................
ASC32 ......................
ASC32 ......................
'
4-387
4-389
4-391
4-377
4-3
4-3
4-3
4-3
4-3
4-19
4-19
4-19
4-19
4-27
4-27
4-27
4-349
4-349
4-37
4-37
4-7
4-7
4-7
4-7
4-35
4-35
4-35
4-467
4-467
4-225
4-225
4-477
4-477
4-513
4-521
4-517
4-499
4-523
4-525
4-529
4-503
4-511
4-507
4-513
4-521
4-517
4-499
4-523
4-525
4-529
4-503
4-511
4-507
4-533
4-547
4-537
4-543
4-541
4-39
4-39
CROSS·REFERENCE INDEX
C~lL
NAME
OR240LH
OR260LH
OR310LH
OR320LH
OR340LH
OR360LH
OR410LH
OR420LH
OR440LH
OR460LH
OR510LH
OR810LH
OSEOOLH
OSE03LH
OSE06LH
OSF02LH
PD095LH
PR005LH
PR095LH
PR250LH
PR400LH
PUCOOLH
R2401LH
R2402LH
R2403LH
R2404LH
R2405LH
R2406LH
R2407LH
R2408LH
RA416LH
RA608LH
RA70BLH
RAB04LH
RF408LH
S085LH
S137LH
S138LH
S139LH
S151LH
S153LH
S155LH
S157LH
S158LH
S161ALH
DEVICE
ASC32 .............. .
ASC32 ............. .
ASC4075 ................... .
ASC4075 ............ .
ASC4075 ................... .
ASC4075 ................... .
ASC4072 ................... .
ASC4072 .............. .
ASC4072 ................... .
ASC4072 ................... .
ASC6130 ................... .
ASC6131 ................... .
ASC2500 ................... .
ASC2502 ................... .
ASC2500 ................... .
ASC2500 ....... " .......... .
ASC2373 '" ................ .
ASC2374 ................... .
ASC2372 ................... .
ASC2371 ............ .
ASC2370 ................... .
ASC2320 ................... .
ASC2401 ................... .
ASC2402 ................... .
ASC2403 ................... .
ASC2404 ................... .
ASC2405 ................... .
ASC2406 ................... .
ASC2407 ................... .
ASC2408 ................... .
ASC3003 ................... .
ASC3004 ................... .
ASC3006 ................... .
ASC3005 ................... .
ASC3103 ................... .
ASC85 ............... '"
.. .
ASC137 .................... .
ASC138 .................... .
ASC139 .................. '"
ASC151 .................... .
ASC153 .................... .
ASC155 .................... .
ASC157 .................... .
ASC158 .................. .
ASC161A ................... .
PAGE
CELL NAME
4-39
4-39
4-473
4-473
4-473
4-473
4-469
4-469
4-469
4-469
4-755
4-757
4-423
4-425
4-423
4-423
4-403
4-405
4-401
4-399
4-397
4-371
4-407
4-407
4-407
4-407
4-413
4-413
4-413
4-419
4-443
4-443
4-443
4-443
4-455
4-59
4-71
4-77
4-81
4-85
4-89
4-93
4-97
4-101
4-105
S163ALH
S164LH
S165LH
S166LH
S173LH
S174LH
S175LH
S177LH
S181LH
S191LH
S193LH
S194ALH
S195ALH
S244LH
S245LH
S251LH
S257ALH
S258ALH
S259LH
S273LH
S280LH
S283LH
S298LH
S299LH
S299XLH.
S373LH
S374LH
S375LH
S393LH
S398LH
S399LH
S590LH
S593XLH
S595LH
S598XLH
S651LH
S652LH
S669LH
S686LH
S688LH
TA820LH
TAC20LH
TAP20LH
T0010LH
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, .TEXAS 75266
DEVICE
ASC163A .................. "
ASC164 .............. '" ... .
ASC165....
. ....... .
ASC166 ................ .
ASC173 .......... .
ASC174 ................ .
ASC175 ................ .
ASC177 ..
. ....... .
ASC181 .................... .
ASC191 .................... .
ASC193 ................... "
ASC194A ................... .
ASC195A ................... .
ASC244 ................... "
ASC245 .................... .
ASC251 .................... .
ASC257A ................... .
ASC258A ................... .
ASC259 .................... .
ASC273
............ .
ASC280 ...... " ...... '" ... .
ASC283 .................... .
ASC298 ............... .
ASC299 .................... .
ASC299X . . . . . . . . . . . . . . . . . . .
ASC373 . . . . . . . . . . . . . . . . . . . .
ASC374 .................... .
ASC375 .................... .
ASC393 ................. .
ASC398 ................. .
ASC399 ............. ' ..
ASC590 ................. .
ASC593X ................... .
ASC595 .................... .
ASC598X ................... .
ASC651 ......... .
ASC652 .................... .
ASC669 ............ , ....... .
ASC686 ............... .
ASC688 .................... .
ASC2102 ................... .
ASC2102 ................... .
ASC2102 ................... .
ASC2325 ................... .
PAGE
4-113
4-121
4-127
4-133
4-141
4-147
4-151
4-155
4-161
4-169
4-177
4-185
4-191
4-197
4-201
4-207
4-211
4-215
4-219
4-229
4-235
4-239
4-245
4-251
4-257
4-263
4-267
4-271
4-277
4-281
4-285
4-289
4-295
4-303
4-307
4-315
4-315
4-327
4-333
4-339
4-353
4-353
4-353
4-381
xi
xii
FUNCTIONAL INDEX
HDL or cell names that start with an S (i.e., SxxxLH) are SOFTWARE MACROS.
INVERTERS AND BUFFERS (Delay at 1-pF Load)
TYPICAL
DESCRIPTION
TYPE
Buffers
'ASC2321
Delay Control
'ASC250B
Delay Element
'ASC2507
'ASC04
Inverters
'ASC2310
Inverting
3-State
Buffers
'ASC2311
'ASC6120
Noninverting
Delay
'ASC6121
Buffers
'ASC6122
DELAY
(ns)
RELATIVE
HDL OR
DRIVE
CELL NAME
COMMENTS
FACTOR
3.0
BUll0LH
lX
Noninverting
4.0
BUlllLH
lX
Inverting
3.0
BUl12LH
lX
Noninverting
DLC10LH
2X
DLE10LH
lX
3.0 to
12.0
1.7
IVll0LH
lX
1.1
IV120LH
2X
0.9
IV130LH
3X
O.B
IV140LH
4X
0.7
IV160LH
6X
0.6
IV1BOLH
BX
2.3
IV101LH
lOX
2.6
IV211LH
lX
1.7
IV221LH
2X
1.3
IV241LH
4X
2.6
IV212LH
lX
1.B
IV222LH
2X
1.3
4X
1.7
IV242LH
BU120LH
1.7
BU130LH
3X
2.3
BU221LH
2X
2.0
BU261LH
6X
2.3
BU222LH
2X
2.0
BU262LH
6X
Noninverting
Active-Low Enable
Active·High Enable
2X
Delay
Active-Low Enable
Active-High Enable
POSITIVE-NAND GATES (Delay at 1-pF Load)
TYPICAL
DESCRIPTION
2-lnput NAND
3-lnput NAND
TYPE
'ASCOO
'ASC10
4-lnput NAND
'ASC20
5-lnput NAND
'ASC2022
B-Input NAND
'ASC30
DELAY
(ns)
HDL OR
CELL NAME
RELATIVE
DRIVE
FACTOR
2.0
NA210LH
lX
1.3
NA220LH
2X
3X
1.1
NA230LH
1.0
NA240LH
4X
O.B
NA260LH
6X
2.2
NA310LH
lX
1.5
NA320LH
2X
1.3
1.1
NA330LH
3X
NA340LH
4X
2.6
NA410LH
lX
1.B
NA420LH
2X
3X
1.5
NA430LH
2.7
NA510LH
lX
2.1
4.5
NA520LH
NAB10LH
2X
3.3
NAB20LH
2X
TEXAS
~
INSlRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
lX
xiii
FUNCTIONAL INDEX
POSITIVE-NOR GATES (DeIIlY lit 1-pF LOlld)
TYPICAL
DESCRIPTION
TYPE
DELAY
(ns)
2-lnput NOR
'ASC02
3-lnput NOR
'ASC27
4-lnput NOR
'ASC4002
5-lnput NOR
'ASC260
8-lnput NOR
'ASC4078
HDLOR
RELATIVE
DRIVE
CELL NAME
FACTOR
2.4
N0210LH
lX
1.5
N0220LH
2X
1.3
1.1
N0230LH
N0240LH
3X
4X
3.2
N0310LH
1X
2.1
N0320LH
2X
3X
1.8
N0330LH
'4.1
N0410LH
lX
2.6
5.0
N0420LH
2X
N0510LH
lX
3.2
N0520LH
2X
3.4
N0810LH
lX
4.9
N0820LH
2X
POSITIVE-AND GATES (DeIIlY at 1-pF Load)
TYPICAL
DESCRIPTION
TYPE
DELAY
(ns)
2-lnput AND
3-lnput AND
4-lnput AND
xiv
'ASC08
'ASC11
'ASC21
HDL OR
CELL NAME
RELATIVE
DRIVE
FACTOR
2.1
AN210LH
1X
1.9
AN220LH
2X
2.1
1.7
AN240LH
4X
AN260LH
6X
2.4
AN310LH
1X
2.2
AN320LH
2X
2.5
AN340LH
4X
1.9
AN360LH
6X
2.6
2.5
AN410LH
AN420LH
2X
2.7
AN440LH
4X
2.3
AN460LH
6X
lX
5·lnput AND
'ASC2024
2.9
AN510LH
lX
8-lnput AND
'ASC6132
3.4
AN810LH
lX
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
FUNCTIONAL INDEX
POSITIVE-OR GATES (Delay at 1-pF Load)
TYPICAL
TYPE
DESCRIPTION
DELAY
(ns)
2-lnput OR
'ASC32
3-lnput OR
'ASC4075
4-lnput OR
'ASC4072
RELATIVE
HDL DR
CELL NAME
DRIVE
FACTOR
2.3
OR210LH
1X
2.1
OR220LH
1.8
OR240LH
2X
4X
1.7
OR260LH
6X
2.7
OR310LH
1X
2.7
OR320LH
2X
2.2
OR340LH
4X
2.2
OR360LH
6X
3.1
OR410LH
1X
3.1
OR420LH
2X
2.7
OR440LH
4X
2.7
OR460LH
6X
5-lnput OR
'ASC6130
3.4
OR510LH
1X
8-lnput OR
'ASC6131
3.3
OR810LH
1X
EXCLUSIVE-OR. -NOR. -AND-OR GATES (Delay at 1-pF Load)
TYPICAL
DESCRIPTION
TYPE
DELAY
(ns)
RELATIVE
HDL OR
CELL NAME
DRIVE
COMMENTS
FACTOR
2.3
EX210LH
1X
2.0
EX220LH
2X
2.0
EX240LH
4X
2.4
EN210LH
1X
'ASC2330
2.6
A0221LH
1X
2-Wide, 2-lnput
'ASC2331
2.6
A0220LH
1X
2-Wide, 2-lnput
Exclusive-OR
'ASC86
Exclusive-NOR
'ASC266
AND-NOR
AND-OR
ANALOG FUNCTIONS
DESCRIPTION
TYPE
Crystal-Controlled
Oscillator
'ASC2500
RC Oscillator
'ASC2502
Comparator
'ASC2503
Delay Element
'ASC2507
Delay Control
'ASC2508
INPUT
OSEOOLH
Crystal
OSF02LH
Crystal
OSE06LH
RC
P-Chan
OSE03LH
C0212LH
N-Chan
C0213LH
P-Chan
N-Chan
P-Chan
N-Chan
Medium-Drive
Operational Amplifier
'ASC2519
CELL NAME
Crystal
Op-Amp
DLE10LH
DLC10LH
AMC12NH
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
xv
FUNCTIONAL INDEX
BOOLEAN FUNCTIONS (Delay at 1-pF Load)
DESCRIPTION
AND·NOR
OR-AND-NOR
AND-OR-ANONOR
OR·NANO
'ASC6002
TYPICAL
DELAY
(nsl
2.7
BF002LH
Y - Al +(Bl.B~.B~1
'ASC6003
2.6
BF003LH
Y - (Al.A2j+(Bl.B21
'ASC6004
2.8
BF004LH
Y
'ASC6005
3.0
BF005LH
Y
(A 1.A2.A3j + (Bl.B~.B31
'ASC600S
3.2
BF006LH
Y
Al +A2+(Bl.B21
'ASC6007
3.7
BF007LH
Y
Al +A2+(Bl·B2·B31
'ASC6008
3.4
BF008LH
Y
Al +(Bl·B21 +(Cl.C21
'ASCS009
3.7
BF009LH
Y
'ASC6012
3.7
BF012LH
Y
'ASC6013
4.1
BF013LH
Y - (A 1·A21 + (Bl·B2·B3) + (Cl.C2.C3)
'ASCS014
4.3
BF014LH
Y - (Al·A2·A3)+(Bl·B2·B3)+(Cl·C2·C3)
'ASC6017
2.5
BF001LH
Y - Al +(Bl·B2)
'ASC6018
3.9
BF010LH
Y - A 1 + (Bl.B2.B3) + (Cl.C2.C3)
'ASC6019
3.5
BFOllLH
Y - (Al.A2)+(Bl.B2)+(Cl.C2)
'ASC6022
3.9
BF022LH
Y
Al·A2+(Bl·B2.(Cl +C2)]
'ASC6023
3.2
BF015LH
Y
Al +]Bl.(Cl +C2)]
'ASC6024
3.4
BF016LH
Y
Al +((Bl +B2)o(Cl +C2)]
'ASC6025
3.5
BF025LH
Y
Al.A2.A3+(Bl.(Cl +C21]
'ASCS026
3.7
BF017LH
Y
Al +IB1·B2·(Cl +C2)]
'ASC6027
3.6
BF027LH
Y - Al.A2.A3+(Bl.B2.(Cl +C2)]
'ASC6028
3.6
BF028LH
Y
'ASC6029
3.4
BF020LH
Y - Al·A2+(Bl.(Cl+C21]
'ASC6032
3.9
BF030LH
Y - A1+ (B1o[Cl +(01.02)]]
'ASC6034
3.S
BF034LH
Y - (Al.A2)+(B1o[Cl +(01.02)])
'ASC6035
3.3
BF035LH
Y
'ASC6048
2.4
BF051LH
Y -- A1o(B1+B21
'ASC6049
3.8
BF060LH
Y - A1o(Bl +B2+B3)O(Cl +C2+C3)
'ASC6052
3.2
BF052LH
Y
Al.(Bl +B2+B3)
'ASC6053
2.6
BF053LH
Y
(Al +A2)o(Bl +B2)
'ASC6054
3.0
BF054LH
Y - (Al +A2).(Bl +B2+B3)
'ASC6055
3.3
BF055LH
Y - (Al +A2+A3).(Bl +B2+B3)
'ASC605S
2.9
BF056LH
Y - Al.A2·(Bl+B21
'ASC6057
3.7
BF057LH
Y
'ASC6058
3.0
BF058LH
Y - AHBl +B2)o(Cl-1'C2j
'ASC6059
3.5
BF059LH
Y - Al·(Bl +B2)o(Cl +C2+C3)
'ASC6062
4.1
BF062LH
Y
'ASCS063
4.2
BF063LH
Y
(Al +A2)o(Bl +B2+B3)o(Cl +C2+C3j
'ASC6064
4.1
BFOS4LH
Y
(Al +A2+A3)o(Bl +B2+B3).(Cl +C2+C31
TYPE
HDLOR
CELL NAME
EQUATION
(Al.A21+(Bl.B2.B31
Al +(Bl·B21+(Cl·C2·C3)
~
~
(Al·A21+(Bl.B21+(Cl·C2·C31
Al·A2·A3+(B1o(Cl +C2)o(Dl +02)]
(A 1·A2) + (Bl.((Cl.C2) +101.02)])
~
Al·A2·(Bl +B2+B3)
(Al +A2).(Bl +B2).(Cl +C2+C3)
NOTE: All have 1X drive factor.
xvi
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
FUNCTIONAL INDEX
BOOLEAN FUNCTIONS (Delay at 1-pF Load) (continued)
TYPICAL
DESCRIPTION
TYPE
DELAY
HDLOR
EQUATION
CELL NAME
(ns)
'ASC6065
2.8
BF065LH
Y
A 1o[Bl + (Cl.C2)]
'ASC6066
2.9
BF066LH
Y
A 1.[(61.B2) + (Cl.C2))
'ASC6067
3.7
BF067LH
Y
A 1o[Bl + 62 + (Cl.C2))
'ASC6068
4.0
BF06BLH
Y - A 1o[Bl + (Cl·C2l+ (01.02)]
'ASC6069
4.2
BF069LH
Y - A1o[(Bl·B21+(Cl.C2)+(Dl.D2)]
'ASC6072
3.B
BF072LH
Y = (Al +A21·[Bl +B2+(Cl.C2))
'ASC6073
2.9
BF070LH
Y - (Al +A2).[Bl +(Cl.C2)1
'ASC6074
3.1
BF071LH
Y - (Al +A21·[(Bl·B21+(Cl·C211
'ASC6075
2.5
BF075LH
Y
(Al +A2+A31.[Bl +(Cl·C211
'ASC60S2
3.S
SFOS2LH
Y
Al.((Bl.B21+[Cl.(Dl +D2111
OR-AND-OR-
'ASC60S3
3.7
SFOSOLH
Y
Al.(Bl + [C1o(Dl +D2)]}
NAND
'ASC60B4
3.9
BFOS1LH
Y
Al.(Bl +[(Cl +C2).(Dl +D2)1I
'ASC60SB
4.1
BFOS8LH
Y
(Al +A2+A3).(Bl +IC1·(Dl +D2)]}
AND-DR-NAND
NOTE: All have 1 X drive factor.
SPECIAL FUNCTIONS
DESCRIPTION
HDLOR
TYPE
Power-Up Clear
Tie-Off Cell for Buffered
Logical I/O
'ASC2320
CELL NAME
PUCOOLH
'ASC2325
T0010LH
COMMENTS
4X Drive
ESD-Protected
BUS TRANSCEIVERS
DESCRIPTION
MACRO
OUTPUT
TYPICAL
DELAY
(ns)
HDLOR
CELL NAME
COMMENTS
Octal
'ASC245
3-State
5.0
S245LH
Bidirectional
'ASC651
3-Stote
10.4
S651LH
Inverted Data
and Universal
'ASC652
3-State
10.4
S652LH
True Data
DRIVERS
TYPICAL
DESCRIPTION
MACRO
OUTPUT
DELAY
(ns)
Octal
'ASC244
3-Stote
2.4
HDLOR
CELL NAME
S244LH
TEXAS ..,
INSTRUMENlS
POST OFFICE BOX 656012 • DALLAS, TE,XAS 75265
COMMENTS
True Data
xvii
FUNCTIONAL INDEX
INPUT BUFFER CELLS (Delay at 1-pF Load)
TTL THRESHOLD
TYPICAL
DESCRIPTION
MACRO
DELAY
(nsl
'ASC5001
'ASC5003
Inverting
'ASC5005
'ASC5010
'ASC5007
Noninverting
'ASC5013
HDLOR
CELL NAME
2.1
IPE03LH
2.1
IPF03LH
7.5
IPEOBLH
B.l
IPFOBLH
2.1
IPE05LH
2.1
IPF05LH
7.5
IPE10LH
7.5
IPF10LH
2.1
IPE04LH
2.1
IPF04LH
1.6
IPF12LH
2.1
IPF13LH
RELATIVE
DRIVE
COMMENTS
FACTOR
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
With Hysteresis
With Hysteresis
With Pull-Up Tap
With Pull-Up Tap
With. Hysteresis
lind Pull-Up Tap
With Pull-Up Tap
INPUT BUFFER CELLS (Delay at 1-pF Load)
CMOS THRESHOLD
TYPICAL
DESCRIPTION
MACRO
DELAY
(nsl
'ASC5000
Inverting
'ASC5002
'ASC5004
Noninverting
NOTE:
xviii
'ASC5006
HOi. OR
CELL NAME
RELATIVE
DRIVE
COMMENTS
FACTOR
1.1
IPEOOLH
1.1
4.B
IPFOOLH
IPE06LH
IX
IX
IX
4.B
IPF06LH
IX
1.0
IPF02LH
1.9
IPE01LH
1.1
IPF01LH
IX
IX
IX
IPE = Minimum Height; IPF = Minimum Width
TEXAS ,.,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
With Hysteresis
With Hysteresis
and Pull-Up Tap
With Pull-Up Tap
FUNCTIONAL INDEX
NONINVERTING OUTPUT BUFFER CELLS (Delay at 15-pF Load)
DESCRIPTION
TYPICAL
DELAY
TYPE
(ns)
'ASC5100
'ASC5103
Push-Pull
'ASC5106
'ASC5110
'ASC5120
'ASC5104
'ASC5107
OUTPUT CURRENT
IOl(mA)
IOH(mA)
74
74
54
54
2.7
OPE40lH
3.4
4.0
-3.4
-4.0
2.7
OPF40lH
3.4
4.0
-3.4
-4.0
2.4
OPE60LH
5.1
6.0
-5.1
-6.0
2.4
OPF60LH
5.1
6.0
-5.1
-6.0
2.0
OPEOOLH
8.5
10.0
-8.5
-10.0
2.0
OPFOOLH
8.5
10.0
-8.5
-10.0
3.4
OPE42LH
3.2
4.0
-3.2
-4.0
3.4
OPF42lH
3.2
4.0
-3.2
-4.0
1.7
OPFBOlH
20.4
24.0
-10.2
-12.0
-6.0
2.7
OPE63LH
5.1
6.0
-5.1
2.7
OPF63LH
5.1
6.0
-5.1
-6.0
2.7
OPE03LH
8.5
10.0
-8.5
-10.0
-10.0
2.7
OPF03LH
8.5
10.0
-8.5
3.5
OPE43LH
3.4
4.0
-3.4
-4.0
3.5
OPF43LH
4.0
'ASC5124
2.5
OPFD3LH
3.4
37.4
44.0
-3.4
-10.2
-4.0
-12.0
'ASC5125
2.8
OPFB3LH
20.4
24.0
-10.2
-12.0
2.0
OPE61LH
5.1
6.0
-
2.0
OPF61LH
5.1
6.0
1.7
OPE01LH
8.5
10.0
1.7
OPF01LH
8.5
10.0
-
2.7
OPE41LH
3.4
3.4
4.0
-
-
4.0
37.4
40.8
44.0
-
-
48.0
-
-
3-State
'ASC5111
'ASC5105
'ASC5108
Open Drain
'ASC5109
NOTE 1. OPE
HDlOR
CEll NAME
2.7
OPF41LH
'ASC5121
1.7
OPFD1LH
'ASC5123
1.5
OPFE1LH
= Minimum
Height; OPF
=
--
Minimum Width
TEXAS ...,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
xix
FUNCTIONAL INDEX
CLOCK GENERATORS
COMMENTS
Complementary Outputs
D-TYPE FLIP-FLOPS (Delay at 1-pF Load)
DESCRIPTION
RELATIVE
MACRO
OR TYPE
f max
HDLOR
(MHzl
CELL NAME
55.B
DTB10LH
IX
'ASC74
46.3
DFB20LH
2X
59.2
DFZ20LH
2X
55.B
DTP10LH
IX
55.S
DFP20LH
69.2
DFY20LH
2X
2X
With Preset
and Clear
Preset Only
'ASC74
Clear Only
'ASC74
Neither Preset
'ASC74
nor Clear
DRIVE
COMMENTS
FACTOR
52.1
DTC10LH
IX
52.1
DFC20LH
2X
55.S
DTN10LH
IX
64.2
DFN20LH
2X
D Low
D Low
D-TYPE FLIP-FLOPS
TYPICAL
MACRO
DESCRIPTION
DELAY
(nsl
OR TYPE
HDLOR
CELL NAME
RELATIVE
DRIVE
COMMENTS
FACTOR
Quad with Q Only
'ASC173
S.O
S173LH
IX
3-State Output
Hex
Quad with Q, QZ
'ASC174
B.O
S174LH
'ASC175
5.5
S175LH
IX
IX
With Clear
Octal
'ASC273
5.0
S273LH
IX
With Clear
With Clear
TOGGLE FLIP-FLOPS, UNGATED (Delay at 1-pF Load)
DESCRIPTION
TYPE
RELATIVE
f max
HDL OR
(MHz)
CELL NAME
DRIVE
FACTOR
Preset and Clear
'ASC2102
54.2
TAB20LH
2X
Clear Only
'ASC2102
61.7
TAC20LH
2X
Preset Only
'ASC2102
65.S
TAP20LH
2X
J-K-TYPE
DESCRIPTION
FLIP-FLOPS (Delay at 1-pF Load)
TYPE
'ASC109
HDL OR
f max
(MHz)
CELL NAME
44.2
JKB20LH
RELATIVE
DRIVE
2X
Preset and Clear
'ASC210S
xx
44.2
JKB21LH
COMMENTS
FACTOR
2X
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Positive-Edge
Trigger
Negative-Edge
Trigger
FUNCTIONAL INDEX
LATCHES
TYPICAL
MACRO
DESCRIPTION
DELAY
OR TYPE
Ins}
'ASC75
D-Type
'ASC6125
Set-Reset
8-Bit D-Type
8-8it Addressable
CELL NAME
DRIVE
COMMENTS
FACTOR
2.4
LAH10LH
1X
Active-High Enable
2.0
LAH20LH
2X
Active-High Enable
3.9
LAL20LH
2X
Active-Low Enable
2.8
LAB10LH
1X
2X
'ASC279
4-Bit Bistable
RELATIVE
HDL OR
2.7
LA820LH
'ASC375
4.5
S375LH
1X
'ASC373
5.0
S373LH
1X
3-State Output
'ASC374
5.0
S374LH
1X
3-State Output
'ASC259
6.0
S259LH
1X
Active-Low- Clear
GATED S-R LATCHES (Delay at 1-pF Load)
DESCRIPTION
TYPICAL
MACRO
DELAY
OR TYPE
Ins)
RELATIVE
HDL OR
CELL NAME
DRIVE
COMMENTS
FACTOR
4-lnput
'ASC6100
2.8
GM010LH
5-lnput
'ASC6101
3.6
GM110LH
1X
5-lnput
'ASC6102
3.6
GMS10LH
1X
Separate Set
6-lnput
'ASC6103
3.6
GM210LH
1X
Separate Set/Reset
1X
Separate Reset
6-lnput
'ASC6105
3.0
GM310LH
1X
7-lnput
'ASC6106
4.0
GM410LH
1X
Separate Reset
8-lnput
'ASC6108
4.0
GM510LH
1X
Separate Set/Reset
GATED
DESCRIPTION
S-R LATCHES
MACRO
TYPICAL
OR TYPE
DELAY
(ns)
(Delay at 1-pF Load)
RELATIVE
HDLOR
CELL NAME
DRIVE
COMMENTS
FACTOR
4-lnput
5-lnput
'ASC6110
'ASC6111
2.7
3.1
GS110LH
1X
1X
Separate Reset
5-lnput
'ASC6112
3.1
GSS10LH
1X
Separate Set
6-lnput
'ASC6113
3.1
GS210LH
1X
Separate Set/Reset
6-lnput
'ASC6115
3.4
GS310LH
1X
7-lnput
'ASC6116
3.8
GS410LH
1X
Separate Reset
8-lnput
'ASC6118
4.0
GS510LH
1X
Separate Set/Reset
GS010LH
OSCILLATORS AND MULTIVIBRATORS
DESCRIPTION
TYPE
Crystal-Controlled
'ASC2500
Oscillator
HDL OR
CELL NAME
COMMENTS
OSEOOLH
5 MHz
OSF02LH
20 MHz
OSE06LH
800 kHz
CMOS RC Oscillator
'ASC2502
OSE03LH
1 MHz
Retriggerable One-Shot
'ASC2322
MVFOOLH
With Clear
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
xxi
FUNCTIONAL INDEX
4-BIT EXPANDABLE REGISTERS-POSITIVE-EDGE-TRIGGERED
DESCRIPTION
Serial Inputl
Parallel Output
OUTPUT
f max
(MHz)
CELL NAME
'ASC2401.
an
59.6
R2401LH
MACRO
OR TYPE
HDL OR
COMMENTS
Async Clear
Serial Input
'ASC2402
an, OnZ
59.6
R2402LH
Async Clear
Parallel Inputl
Parallel Output
'ASC2403
an
59.6
R2403LH
Async Clear
Parallel Input
'ASC2404
an, OnZ
59.6
R2404LH
Async Clear
4-BIT EXPANDABLE REGISTERS-POSITIVE-EDGE-TRIGGERED
DESCRIPTION
TYPICAL
MACRO
OUTPUT
OR TYPE
HDL OR
CELL NAME
DELAY
(ns)
C.OMMENTS
Async Clear
Parallel Access
'ASC195A
an
5.5
S195ALH
J-K Input
First Stage
Parallel Inputl
Parallel Output
Bidirectional
'ASC194A
an
5.0
S194ALH
Shift
Async Clear
8-BIT EXPANDABLE REGISTERS-POSITIVE-EDGE-TRIGGERED
DESCRIPTION
MACRO
OR TYPE
TYPICAL
OUTPUT
DELAY
(ns)
HDLOR
CELL NAME
COMMENTS
Async Clear
Serial Inputl
'ASC164
an
5.0
S164LH
Parallel Output
'ASC595
3-State
5.5
S595LH
Registered Outputs
S598XLH
Input Latches
Async Load
Parallel Inputl
Parallel Output
Parallel Input!
Serial Output
'ASC598X
3-State
OH,OHZ
9.8
'ASC165
OH,OHZ
8.0
S165LH
'ASC166
OH
6.0
S166LH
7.1
S299LH
Parallel or
Serial Input!
Serial Output
Universal and
'ASC299
Bidirectional
'ASC299X
300State
110
Async Clear
Sync Load
Async Clear
Sync Load
Multiplexed 110
Separate
110
5.0
S299XLH
Async Clear
Sync Load
REGISTER FILE
TYPICAL
DESCRIPTION
16-Word by 8-Bit
xxii
TYPE
ACCESS
TIME ins)
CELL NAME
COMMENTS
'ASC3103
8
RF40BLH
Typical Cycle Time - 11 ns
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TeXAS 75265
FUNCTIONAL INDEX
4-BIT COUNTERS-POSITIVE-EDGE-TRIGGERED (RIPPLE COUNT)
MACRO
DESCRIPTION
OUTPUT
OR TYPE
D-Type
Ripple Up
f max
HDL OR
(MHzl
CELL NAME
COMMENTS
'ASC2405
On
64.2
R2405LH
Async Clear
'ASC2406
On,OnZ
64.2
R2406LH
Async Clear
'ASC2407
3·State
36.3
R2407LH
Async Clear
'ASC2408
On
59.6
R2408LH
Async Clear
4-BIT COUNTERS-POSITIVE-EDGE-TRIGGERED (RIPPLE COUNT)
TYPICAL
MACRO
DESCRIPTION
OUTPUT
OR TYPE
Programmable
Divide by 2/8
Dual4-Bit
DELAY
Insl
HDLOR
CELL NAME
COMMENTS
'ASCl77
On
22
Sl77LH
Async Clear
'ASC393
Onl,On2
21
S393LH
Async Clear
SYNCHRONOUS COUNTERS- POSITIVE-EDGE-TRIGGERED
DESCRIPTION
4-Bit Binary
4-Bit U p/Down
8-Bit 8inary
TYPICAL
PARALLEL
MACRO
DELAY
LOAD
(ns)
HDL OR
COMMENTS
CELL NAME
Async Clear
'ASC161A
Sync
12.0
S161ALH
'ASC163A
Sync
9.0
S163ALH
Sync Clear
'ASC191
Async
11.5
S191LH
With Mode ContrQI
'ASC193
Async
Sync
11.5
10.0
S193LH
Dual Clock
'ASC669
S669LH
Internal Look-Ahead/Carry
'ASC590
None
10.4
S590LH
Output Registers
'ASC593X
Sync
10.0
S593XLH
Input Registers
DECODERS
DESCRIPTION
2- to 4-Line
3- to 8-Line
Dual 2- to 4-Line
MACRO
OR TYPE
TYPICAL
DELAY
Ins)
HDL OR
CELL NAME
RELATIVE
DRIVE
COMMENTS
FACTOR
2.0
DE210LH
2.5
DE212LH
1X
Active-Low Enable
'ASC137
12.0
S137LH
1X
Latches
'ASC138
7.0
S138LH
lX
'ASC139
4.0
S139LH
1X
3 Enables
1 Enable
'ASC2350
1X
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
xxiii
FUNCTIONAL INDEX
MULTIPLEXERS
TYPICAL
MACRO
DESCRIPTION
OUTPUT
OR TYPE
DELAY
(nsl
HDLOR
COMMENTS
CELL NAME
2- to l-Line
'ASC2340
Y
3.7
MUll0LH
Active-Low Enable
Dual 2- to 4-Line
'ASC155
Yln, Y2n
5.0
S155LH
Active-Low Enable
'ASC157
'ASC158
Yn
Yn
6.0
S157LH
6.2
S158LH
'ASC257A
Yn
5.0
S257ALH
3-State
'ASC258A
Yn
5.0
S258ALH
3-State
'ASC298
Qn
6.0
S298LH
'ASC398
Qn, QnZ
5.5
S398LH
'ASC399
Qn
5.0
S399LH
Quad 2- to l-Line
Storage
Latches
Storage
Latches
Storage
Latches
4- to l-Line
'ASC2341
Y
2.9
MU210LH
No Enable
Dual 4- to l-Line
'ASC153
Yn
8.0
S153LH
Strobe
'ASC151
Y,W
3-State
8.0
9.7
S151LH
Low Enable
S251LH
Low Enable
Y
4.7
MU310LH
Active-Low Enable
'ASC251
8- to 1-Line
'ASC2342
NOTE: All have 1X drive factor.
PROGRAMMABLE DELAY ELEMENTS
TYPICAL
DESCRIPTION
TYPE
Delay Element
'ASC2507
Control Element
'ASC2508
DELAY RANGE
3to12ns
CELL NAME
DLE10LH
DLC10LH
OSCILLATORS AND MUL TlVIBRATORS
DESCRIPTION
HDL OR
TYPE
Crystal-Controlled
CELL NAME
'ASC2500
Oscillator
5 MHz
OSF02LH
20 MHz
OSE06LH
CMOS RC Oscillator
Retriggerable
One-Shot
COMMENTS
OSEOOLH
'ASC2502
OSE03LH
. 'ASC2322
MVFOOLH
800 kHz
1 MHz
With Clear
MAGNITUDE COMPARATORS AND ARITHMETIC CIRCUITS
xxiv
'ASC181
4
12.0
S181LH
'ASC283
4
8.5
S283LH
'ASC280
11.0
S280LH
'ASC85
9
4
12.0
S85LH
P = Q, P
'ASC686
8
9.0
S686LH
P-Q,P>Q
'ASC688
8
7.5
S688LH
P=Q
Binary Full Adder
Parity Generator
Identity
HDLOR
CELL NAME
ALU
Comparator
TYPICAL
DELAY
{nsl
MACRO
Comparator
BIT
WIDTH
DESCRIPTION
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
COMMENTS
< Q, P > Q
FUNCTIONAL INDEX
BIT-SLICE PROCESSOR ELEMENTS
DESCRIPTION
TYPE
a-Bit Processor Slice
'ASC888
14-Bit Microsequencer
'ASC890
4-Bit Microprocessor Slice
'ASC2901
Look-Ahead Carry Generator
'ASC2902
Status and Shift Controller
'ASC2904
12-Bit Microprogram Controller
'ASC2910
(Microsequencer)
STATIC RANDOM ACCESS MEMORIES
DESCRIPTION
HDL OR
ORGANIZATION
TYPE
256-8it
16 x 16
'ASC3003
RA416LH
512-8it
64 x 8
'ASC3004
RA608LH
256 x 4
'ASC3005
RA804LH
128 x 8
'ASC3006
RA708LH
1024-8it
CELL NAME
BIDIRECTIONAL 3-STATE NON INVERTING 110 CELLS (Delay at 15-pF Load)
TYPICAL
INPUT
INV/TRUE
TYPE
DELAY
(ns)
CMOS
TTL
Inverting
'ASC5200
Inverting
'ASC5202
True
'ASC5203
True
'ASC5206
HDLOR
CELL NAME
OUTPUT CURRENT
IOL (mA)
54
74
IOH (rnA)
54
74
-3.4
3.3
IOE40LH
3.4
3.3
IOF40LH
3.4
3.6
IOF47LH
3.4
3.3
IOF48LH
3.4
3.3
IOE41LH
3.4
3.3
IOF41LH
3.4
4.0
4.0
4.0
4.0
4.0
4.0
2.9
IOEOOLH
8.5
10.0
-8.5
2.9
IOFOOLH
8.5
IOF03LH
8.5
10.0
10.0
-8.5
-4.0
-4.0
-4.0
-4.0
-4.0
-4.0
-10.0
-10.0
-10.0
8.5
10.0
8.5
10.0
Inverting
'ASC5220
Inverting
'ASC5221
2.7
True
'ASC5226
2.7
IOF01LH
Inverting
'ASC5250
1.7
IOFDOLH
3.5
IOE43LH
3.4
3.5
IOF43LH
3.5
IOE44LH
37.4 -44.0
-3.4
-3.4
-3.4
-3.4
-3.4
-8.5
-
-
4.0
-3.4
-4.0
3.4
4.0
-3.4
3.4
-3.4
-3.4
-5.1
-4.0
-4.0
-4.0
-6.0
Inverting
'ASC5201
True
'ASC5207
3.5
IOF44LH
3.4
4.0
4.0
True
'ASC5217
2.7
IOF64LH
5.1
6.0
True
'ASC5227
2.7
IOF04LH
8.5
10.0
-8.5
-10.0
True
'ASC5239
2.7
IOFB8LH
20.4
24.0
-12.0
Inverting
'ASC5246
2.5
IOFD8LH
37.4
44.0
-10.2
-10.2
-12.0
NOTE: IOE = Minimum Height; IOF = Minimum Width
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
xxv
FUNCTIONAL INDEX
INPUT/OUTPUT TERMINATING NETWORKS
DESCRIPTION
SUPPLY
HDLOR
CURRENT
CELL NAME
'ASC2370
400 pA
PR400LH
'ASC2371
200 ~A
PR250LH
Input or
~A
PR095LH
1/0 with
5~
PR005LH
Tap
~A
PD095LH
TYPE
Active Pull-Up
Active Pull-Down
'ASC2372
95
'ASC2374
'ASC2373
95
COMMENTS
CompilerCell'· MEMORIES/REGISTERS
Static Random
Access Memories
Read-Only
Memories-
TOTAL
NUMBER
WORD LENGTH
OF WORDS
IN BITS
'ASC3010
4 to 1024
4 to 32
16 to 16384
'ASC3200
8 to 2048
4 to 32
512 to 16384
'ASC3200
8 to 4096
4 to 64
512 to 65536
'ASC3430
-
4 to 32
4- to 32-X-n
TYPE
DESCRIPTION
NUMBER
OF BITS
Single Array
Read-Only
Memories-
Double Array
Pipeline
Test Register
CompilerCell'" PROGRAMMABLE LOGIC ARRAYS
DESCRIPTION
Programmable
Logic Arrays
xxvi
TYPE
INPUTS
'ASC3800
64
TEXAS
PRODUCT
TERMS
128
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
OUTPUTS
32
I
General Information
II
1-1
II
1-2
GENERAL INFORMATION
INTRODUCTION TO STANDARD CELLS
Leadership electronic solutions protect the unique value designed into your products. Using Texas Instruments
SystemCelFM standard cells, you implement simple custom semiconductor solutions for your specific market
opportunities. These custom solutions, also called Application Specific Integrated Circuits (ASICsl. lock in the
powerful combination of personalized electronics and increased system efficiency. Some benefits are
SystemCelFM
FEATURES
SYSTEM BENEFITS
Custom design
Improves your market value by
- Reducing cycle time
- Reducing product development costs
Automated design process
Improves your market execution by
- Reducing design resources
- Enhancing market entry point
Selected density and package
Simplifies your system design by
Providing optimal circuit size
Reducing package count
Controlling costs
Improving reliability
Selected performance
Enhances your market appeal by
Providing timely application solutions
Using your specific functions
Integrating Tl's custom circuits.
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Using TI's standard cells greatly simplifies custom IC implementation. The SystemCeIFM standard-cell family
not only includes a number of the familiar TTL and HCMOS logic functions, but it also provides new and higher
density standard-cell logic functions. When used in conjunction with computer-based workstations, the custom
IC schematic is electronically captured for implementation in an automated chip-layout process. This combination
is currently the most cost effective for achieving personalized, high-complexity semiconductor solutions.
Electronic workstations are the key to simplified, high-complexity IC design. Typically, the workstations
incorporate high-level design tools to simplify component selection, schematic evaluation, and functional
verification. Simulation tools, resident on most workstations, perform the equivalent of circuit breadboarding
and debugging. Once the circuit design is complete, workstation utility software supplied by TI generates data
base files containing both hardware and test descriptions. The data base is used as a source for generating
the chip'layout and testing the fabricated devices.
Custom ICs can be designed using one of many popular workstations or one of several personal computer
systems. Once you decide on a workstation, you need only place one phone call to receive a copy of the TI
documentation and software needed to begin a TI SystemCelFM design. If you decide not to invest in or use
your own workstation, you can begin your standard-cell design with a sketch, and TI can work with you to
complete the rest. Using TI's SystemCelFM family, yqu can decide how many, or how few, standard-cell design
tasks you wish to perform.
TI has defined a variety of customer support and interface programs structured specifically for the most beneficial
application of your resources. A description of these interface points is provided in the standard-cell design
overview.
TEXAS ."
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1-3
GENERAL INFORMATION
II
Customer Support
To assist you with a standard-celilC design, TI has seven North American Regional Technology Centers (RTCs)
staffed with experienced design personnel. The RTC staff can work with you to coordinate design specification
development and implementation.
Total system design support is available at the RIC. A number of electronic workstations are available with
a direct high-speed computer link to the TI design automation center in Dallas, Tex'as.
The RTC also provides assistance in the use of the TI standard-cell library, including installation, training, and
library updates.
Once you have decided on a standa.rd-cell approach, the RTC designers are available to perform the engineering
design and test development. You decide the amount of work the RTC will do and the amount you will do.
The more tasks you perform, the fewer charges there will be for nonrecurring engineering (NRE) work associated
with IC design. The RTC can perform pre-design support, such as assisting with system analysis and circuit
partitioning, as well as schematic capture and test pattern generation, Charges for these services are primarily
based on fixed-fee contracts, providing predictable and manageable ,design costs.
In addition to RTC assistance, technical sales representatives and ASIC product specialists, located in TI sales
offices, can help determine the best standard-cell IC approach.
Getting A Head Start: TI Standard-Cell Workshop
The RTC offers comprehensive training in standard-cell design using state-of-the-art design tools and software.
The RTC-210 ASIC workshop is a three-day course thilt uses numerous lab exercises and concise lectures to
introduce all phases of a standard-celilC design. A listing of the RTC-210 course work follows.
RTC-210 ASIC Course Work Outline
Characteristics and advantages of gate arrays
Characteristics and advantages of standard cells
Semicustom design technique
Schematic capture
Packaging and interface considerations
Circuit simulation and test-pattern design
Generating a design data base using a workstation
IC layout and post-layout simulation.
Another important objective of the course is to help identify interface points and communication channels that
will satisfy your specific requirements for standard-cell IC design.
The workshop is available at the nearest RTC. Or, if you have a number of designers who will be designing
with standard cells, the workshop can be conducted at your facility.
The course is open to anyone interested, and the registration fee is deductible from your first standard-cell IC
order. Contact the nearest TI Regional Technology Center (see listing in Table 1) to register f-or the workshop.
1-4
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
GENERAL INFORMATION
Table 1. Texas Instruments North American Regional Technology Centers
REGION
RTC LOCATION
West Coast - North
PHONE
Santa Clara. CA
(408) 748·2220
West Coast - South
Irvine, CA
(714) 660-8140
Mid-West - North
Arlington Heights, IL
(312) 640-2909
Mid-West - South
Dalias. TX
(214) 680-5066
East Coast -
North
Waltham, MA
(617) 895-9196
East Coast - South
Norcross. GA
(404) 662-7945
Canada
Nepean, Ontario
(613) 726-1970
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TI SystemCelJTM FAMILY
Since the IC was invented, manufacturers of electronic products have used each new advancement in integrated
circuit technology to increase functionality, decrease size, enhance performance, and reduce system costs.
This trend has led semiconductor producers from small-scale-integration (SSI), with only a few transistors per
device, to today's very-Iarge-scale-integration (VLSI), where a circuit consists of hundreds of thousands of
transistors. These high levels of integration have required major improvements in the areas of process technology
and production and fabrication techniques.
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TI's SystemCell™ standard-cell product family takes advantage of these technological advancements to bring
you high performance and functionality of custom ICs at semi-custom prices. The standard cells also offer added
benefits of short design cycle time and reduced product development costs.
The TI SystemCelFMstandard-cell library includes basic gates, buffers, I/O drivers, and high-level functions
called macros. These macros are supplied in two forms: a hard-wired form and a software form. Software macros
of familiar TTL functions can be embedded in your design with a simple label, or they can be custom modified
to enhance functionality and cost effectiveness. Hard-wired macros, providing a broad selection of predesigned
and fully characterized functions, can also be included in your design with a single label.
New standard-cell functions are being added routinely to increase the .effectiveness' of automated design
techniques. These new functions are described in the Advance Information and Product Preview sections of
this book. A goal, maintained by TI, is to provide total semiconductor solutions to your needs. Requests for
new cell designs will be carefully considered.
Other benefits available from the SystemCell™ Family are:
•
•
•
•
•
•
•
CMOS or TTL compatible inputs and outputs
Operation over VCC range of 2 V to 6 V
Specified parametrically over VCC range of 4.5 V to 5.5 V
Specified parametrically over industrial and military temperature ranges
Internal gate propagation delays of less than 1 ns
Flip-flop toggle frequencies up to 65.8 MHz
Latch-up protection up to 400 mA
Inputs and outputs designed to withstand up to 4 kV ESD, as tested using method 3015 of
MIL-STD-883.
Wide variety of package options: DIP, SOIC (D), PGA (GB) and Quad Flat-Pack.
SystemCell™ "J:echnology
SystemCell™ products are fabricated using a twin-well polysilicon self-aligned CMOS process to produce 2-l'm
gate-length versions of CMOS standard cells. In this process, polysilicon is deposited over the gate oxide prior
to the source and drain implants. After patterning the polysilicon gates, the source and drain are then implanted,
TEXAS . "
INSTRUMENlS
POST OFFICE SOX 655012 • DALLAS, TEXAS 75265
1-5
GENERAL INFORMATION
POLYSILICON
GATE
ALUMINUM
INTERCONNECTS ----------~....
PROTECTIVE OVERCOAT
N-WELL
......
P-WELL
_-------------
P-SUBSTRATE
Figure 1. Cross Section of Double-Level Metal. Twin-Well CMOS Process
using the gates as the mask. This self-aligning process, illustrated in Figure 1, permits rE1duced junction areas,
which are coupled with shallow implants to achieve several performance enhancements.
ICs created using Systell1CelFMstandard cells have speeds that meet or exceed HCMOS, Advanced HCMOS,
and all but the most advanced bipolar logic characteristics. These improved speeds are due to reduced gate
and junction capacitance.
Ring oscillator evaluations, shown in Figure 2, compare 2-/Lm CMOS gate propagation delay with 3-/Lm and
5-/Lm CMOS delays. The figure shows the technological improvements associated with high-density CMOS
processes. The data are obtained from equivalent ring oscillators in which the gates are adjacent and interconnect
capacitance is minimal.
The reduced power requirements of CMOS place its speed-power efficiency two orders of magnitude ahead
of conventional bipolar logic families. The lower power requirements are achieved because of reduced channel
lengths, more shallow junctions, smaller feature size, and lower junction capacitance of the high-density 2-/Lm
CMOS technolOgy.
Standard cell products from TI are characterized for performance over thl;l full military temperature range of
-55°C to 125°C and the industrial temperature range of -40°C to 85°C.
Cell Size and Construction
Each
SystemCelFM is a custom-designed silicon implementation of a partiCular logic function.
The SystemCen™ data sheets compare the size of each cell or macro relative to the NA21 OLH two-input NAND
gate, shown in Figure 3. This allows you to estimate the equivalent complexity of your design.
1-6
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
GENERAL INFORMATION
RING OSCILLATOR DATA - INVERTERS. F.O. = 1
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2
3
4
5
6
7 8 9 10
GATE LENGTH - I'm
Figure 2. CMOS Performance
Within a cell. aluminum Vee and ground lines run horizontally across the cell at the top and bottom as illustrated
in Figure 3(A). The polysilicon gates run at right angles to the power buses. providing access to the inputs and
outputs at both the top and bottom of the cell. The logic concept of the cell is shown in Figure 3(8).
TEXAS
,e,
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS. TEXAS 75265
1-7
GENERAL INFORMATION
INPUTS
A
OUTPUT
B
Y
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B
-
-
-
-
--
CD
--,
---{
I
I
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!!.
5"
0""3
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P-CHANNEL
FETS
~
POL Slucml"""iF=!--~
ALUMINUM
N-CHANNEL
FETS
--~
~t1++---GND---+ 1--
I
I
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L_
(8)
I
I
____ .JI
(b) LOGIC
CELL LAYOUT
Figure ·3. 2-lnput NAND
This cell structure lends itself to automated layout by providing the capability of laying cells end-to-end in a
continuous row of cells having a continuous power bus. High-density routing is I'Ichieved through the use of
a second level of metal interconnect.
.
1-8
TEXAS
..Ij~
'V
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS ')6265
GENERAL INFORMATION
THE SystemCell™ LIBRARY
Computer-Aided Design with the Library
The SystemCelFM library provides full access to the latest technological advances in computer-aided design
and state-of-the-art engineering workstations. A workstation employing the TI SystemCeIFM library provides
the familiar, simple entry for designing complex custom ICs.
The TI library can be installed on many popular workstations such as those available from OaisyTM, HewlettPackard, Mentor Graphics™, and Valid Logic Systems Incorporated™. The library can also be used on PCs that
support FutureNet® and P-CAOTM.
The engineering workstations provide generic capabilities for schematic capture, simulation, test-vector
generation, and netlist/test-vector formatting. The TI library contains five additional software programs
implementing graphic, logic, delay, and interconnect capacitance models, along with data base translators. These
programs are used to generate the layout and test-pattern files for your design and are then used directly by
the TI design-automation system to produce the cmplished as described in the following paragraphs.
as·
Dllt~base
(Phllsl! I)
Schemlltic Cllpture
Schematic capture consists of cell conveniilion and logic capture.
Cell Conversion
Each element of the given circuit is replaced with a standard-cell equivalent. This involves selecting the cells
and macros that satisfy both functional and timing requirements, including dc sink/source current requirements
of the I/O cells. Software maCrQS caniMrease lhe efficiency of cell conversion, and simple modifications can
make them custom for your current design. This is usulllly done on a workstation in cOnjunction with logiC capture.
Logic Cllpture
This is the process of representing logic on the workstlltion by calling and namingeac/,! cell and macro to be
used and by naming all input and output interconnections. A hierarchical design process permits the development
of higher-level macros composed of cells and lower-order macros. These 'super' macros and their interconnections
are also named. Within the liinits'ofthe particular workstation, this hierarchical design process is continued
until the standard-cell ic is finplemented; When cQmplet\!l~; the workstation paptures the defined logic in a
hierarchical ned,st· databa!i'e. This databasjOl is utilized by the SystemC~IlTM library !i,ute specificatjons on the schematic.
Functional lind Timing Simuilitions
The workstation utilizes the lie and dC.test vector files to verify pre-layout functionality and timing performance.
.
.
This simulation uses the standard cell's intrinsic characteristics.
Test Description LII!19u8ge (TOLl
The workstation test vfilctors used in the pre-layout simulation are translatec! into TDL automatically by the
SystemCeJITM lil:>rary 'TPl ~ranslator softwarfil. The extracted TDL patt",rns can be ev;:lIuated by prc;>grams that
simUlate faults.at every node to see how effectively the test patterns are detecting faults. Test pattern grading
is an optional procedure.
. .
. '.
,-16
TEXAS''''
INSTl~UMENTS
POST OFFICE BOX
65~012 ~ DALkAS. '~EXAS
16266
GENERAL INFORMATION
Design Specification
The blank, generic, standard-cell IC design specification forms, available from TI, can be used as a working
guideline to achieve successful pre-layout simulations. If so, most of the design specification data are captured
during Phase 0 and 1. A formalized version can then be completed for joint approval by you and TI. Upon approval,
both the design specification and data files are given to TI for Phase 2.
Successful completion of Phase 0 and Phase 1 yields the following results:
A database for the circuit description in HDl
A database for a set of test patterns expressed in TDl
A design specification.
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During this phase of your standard-celilC design, the HDLlTDl database, developed in Phase 1, is converted
into an actual device layout.
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Placement and Routing
Cells and interconnections are arranged according to your I/O design requirements. Using your HDl, a computerautomated layout is completed. Cells are first placed by the layout software, and then cell interconnections
are made using the hierarchical netlist data base.
layout Capacitance Extraction
Values of the interconnect capacitance for each network are extracted and added to cell capacitance to derive
the total capacitive loading on each circuit node.
Post-Layout Simulation
Similar to the pre-layout functional and timing simulation, post-layout simulation combines the effects of intrinsic
and interconnect capacitance and resistance values to simulate the performance based on the cell placement
and chip layout .
. Review
Results of the post-layout simulation are evaluated for conformance to design specification. Beyond conformance,
the database results are evaluated for compliance with predictable norms defined for the design-automationsystem process.
Design Specification
Based on results of the post-layout review, the design specification is confirmed and updated. Confirmation
consists of a mutual agreement to proceed to Phase 3. An update is interactive and requires approval by both
purchaser and TI. If necessary, options for the update are reviewed with the customer and specification changes,
or database changes, that will meet the design requirements are proposed.
Design Verification
The layout database is checked by the design automation system to ensure that geometric design rules are met.
Schematic Verification
The schematic verification program uses the layout database and works backward to generate a new HDl,
which is then compared to the pre-layout HDl description.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
1-17
GENERAL INFORMATION
Merge Internal Cell Structure
The post-layout verified database is merged with a tooling-structure database, resident in the design automation
system. This merge completes the tooling database.
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Tooling Database
...
The tooling database is used to extract the test programs and pattern generator (PG) files. The files are needed
to support wafer fabrication and chip testing.
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Successful completion of Phase 3 yields the following results:
...
A test-program generation (TOL) database
A wafer-fabrication tooling database.
3
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::::I
Chip Fabrication and Testing (Phase 3)
Prototypes of your standard-cell IC are fabricated and tested as described in the following paragraphs.
Photomask Tooling
The PG files are used to execute the photomask designs needed to produce the wafers containing the custom ICs.
Wafer Processing
CMOS standard-cell wafers are fabricated using a twin-well polysilicon self-aligned process (see Figure 1).
Utilization of the 2-l'm process, defined to remain a mainstream technology at TI, is based on long-term product
plan commitments for both custom and standard IC products.
Probe Test
Standard wafer-probe techniques are applied to implement cost-effective utilization of fabrication materials and
resources. A probe test ensures the assembled ICs are most likely to yield parametrically good devices.
Prototype Assembly and Test
Chips passing the probe test are used in the prototype fabrication. Prototypes are packaged in ceramic packs
or carriers as an expedient method for completing design evaluations. Class" A" prototypes are typically tested
at room temperature for functionality while being exercised at 1 MHz. Electrical characteristics of the input
cells, output cells, and static supply current are "go-no-go" tested to the design specification. These class" A"
prototypes are expedited to you for use in performing system functional testing.
AC Characterization arid Data Log
The remaining prototypes (class "B") are tested/data logged by TI in accordance with the design specification.
Typically, class "B" is tested for functionality at the rated performance range(s) over operating ranges of supply
voltage and temperature. Standard data logging is limited to "go-no-go" conformance to the design specification.
These prototypes permit the customer to perform system characterization and system prototype delivery prior
to production start-up.
Volume Production
Acceptance of the characterized "B" prototypes as conforming to the design specification is required prior to
the execution of production orders. Production quantities are packaged in accordance with the design
specification.
1-18
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
GENERAL INFORMATION
SUMMARY
The TI SystemCelFM family provides simple electronic solutions for making your products uniquely innovative.
The SystemCelFM family data sheets (see Section 3) and IC design considerations (see Section 7) provide
additional information. For assistance beyond the scope of this data book, call the following sources:
ASIC product specialist(s) at TI field sales office(s)
Design engineer(s) at the TI Regional Technology Center(s)
The TI ASIC center in Dallas.
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TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1-19
II
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1-20
Definitions, Ratings, and Glossary
2-1
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2-2
EXPLANATION OF FUNCTION TABLES
The following symbols are now being used in function tables on TI data sheets:
H
high level (steady state)
L
low level (steady state)
transition from low to high level
transition from high to low level
X
Z
a .. h
II
irrelevant (any input. including transitions)
off (high-impedance) state of a 3-state output
the level of steady-state inputs at inputs A through H. respectively
00
level of a before the indicated steady-state input conditions were established
00
complement of
an
level of a
JL =
LJ =
rOGGLE
00 or level of a before the indicated steady-state input conditions were established
before the most recent active transition indicated by t or 1
~
ca
rn
rn
o
G
"C
C
one high-level pulse
ca
one low-level pulse
each output changes to the complement of its previous level on each
If. in the input columns. a row contains only the symbols H. L. and/or X. this means the indicated output is valid whenever
the input configuration is achieved and regardless ofthe sequence in which it is achieved. The output persists so long as the
input configuration is maintained.
If. in the input columns. a row contains. H. L. and/or X together with t and/or I. this means the output is valid whenever the
input configuration is achieved but the transition(s) must occur following the achievement of the steady-state levels. If the
output is shown as illevel (H. L. 00. or
it persists so long as the steady-state input levels and the levels that terminate
indicated tninsitions are maintained. Unless otherwise indicated. input transitions in the opposite direction to those shown
br
the pulse follows the indicated input
have no effect at the output. (If the output is shown as a pulse.
transition and persists for an interval dependent on the circuit.)
00).
IL
LJ.
,;
activ~ transition indicated by t or I.
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TEXAS •
INSTRUMENTS
POST OFFICE 'BOX 65sch 2 • DAl.lAS. TEXAS 75265
2-3
EXPLANATION OF FUNCTION TABLES
Among the most complex function tables in this book are those of the shift registers. These embody most of
the symbols used in any of the function tables. plus more. Below is the function table of a 4-bit bidirectional
universal shift register. e.g .• SN74ASC194A.
.
FUNCTION TABLE
CLEAR
C
a>
-to
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en
.
L
H
H
H
H
H
H
H
MODE
CLOCK
I S1 SO
X
X
H
L
L
H
H
L
X
X
X
L
H
H
H
L
L'
,
,t
L
X
t
t
INPUTS
SERIAL
LEFT RIGHT
X
X
X
X
X
X
H
X
X
L
H
X
L
X
x
X
OUTPUTS
A
X
X
a
X
X
X
X
X
PARALLEL
B
C
X
X
X
X
b
c
X
X
X
X
X
X
X
X
X
X
D
X
X
d
X
X
X
X
X
QA
QB
QC
QD
L
L
L
L
QAO aBO aco aoo
a
b
c
d
H aAn aBn aCn
L
aAn aBn aCn
H
aBn aCn aOn
L
aBn Ocn aOn
QAn aBn Ocn aOO
The first line of the table represents a synchronous clearing of the register and says that if clear is low. all four
outputs will be reset low regardless of the other inputs. In the following lines. clear is inactive (highl and so
has no effect.
The second line shows that so long as the clock input remains low (while clear is highl. no other inpllt has any
effect and the outputs maintain the levels they assumed before the steady-state combination of clear high and
clock low was established. Since on other lines of the table only the rising transition of the clock is shown to
be active. the second line implicitly shows that no further change in the outputs will occur while the clocl<. remains
high or on the high-to-Iow transition of the clock.
The third line of the table represents synchronous parallel loading of the register ,md says that if S1 and SO
are both high then. without regard to the serial input. the data entered at A will be at output QA. data entered
at B will be at QB. and so forth. following a low-to-high clock transition.
The fourth and fifth lines represent the loading of high- and low-level data. respectively. from the shift-right
serial input and the shifting of previously entered data one bit; data previously at QA is now at QB. the' previolJs
levels of QB and QC are now at QC and QO respectively. and the data previously at QD is no longer in the
register. This entry of serial data and shift takes place on the low-to-high transition of tile clock when S 1 is
low and SO is high and the levels at inputs A through 0 have no effect.
'
The sixth and seventh lines represent the loading of high- and lOW-level data. respectively. from the shift-left
serial input and the shifting of previously entered data one bit; data previously atqB is now at QA. the previous
levels of QC and QO are now at QB and QC. respectively. and the dCltCl previously at QA is no Iqnger in tl1e
register. This entry of serial data and shift takes place on the low-to-high transition of the clock wh!"n S 1' is
high and SO is low and the levels at inputs A through 0 have no effect.
The last line shows that as long as both mode inputs are low. no other input has any effect and. as in the second
line. the outputs maintain the levels they assumed before the steady-state combination of clear high and both
mode inputs low was established.
. . . .
2-4
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS
75~e5
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Table 1. Specifications for Internal Boolean and Macro Cells
a'bsolute maximum ratings over operating free-air temperature range (unless otherwise noted)
\
Supply voltage range, vee ................................................................ -0.5 V to 7 V
Input voltage range ..................................................................... -0.5 V to 7 V
Operating free·air temperature range: SN54ASe' ............................................. -55°e to 125°e
SN74ASe' .............................................. -40 o e to B5°e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150 0 C
recommended operating conditions
SN74ASC'
SN54ASC'
Vee
Supply voltage
MIN
4.5
TA
Operating temperature range
-55
NOM
5
MAX
5.5
MIN
4.5
125
-40
NOM
'5
MAX
5.5
85
II
UNIT
V
°e
Table 2. Specifications for Input Standard Cells
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vee ................................................................ -0.5 V to 7 V
Input clamp current, 11K (VI <0 or VI>Vee) ....................................................... ±20 mA
Input voltage range ..................................................................... -0.5 V to 7 V
Operating free·air temperature range: SN54ASe' ............................................. -55°e to 125°e
SN74ASe' .............................................. -40 o e to B5°e
~
U)
Storage temperature range .............................................................. -65 °e to 1 50 0 e
'2
SN74ASC'
SN54ASC'
MIN
4.5
NOM
5
C
o
'';=
recommended operating conditions for TTL-compatible inputs
MAX
5.5
MIN
4.5
NOM
5
MAX
5.5
UNIT
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
0
Vee
0
Vee
V
tt
Input transition (rise and fall) times
0
200
0
200
ns
TA
Operating temperature range
-55
125
-40
85
°e
2
2
V
~
c
V
0.8
0.8
V
recommended operating conditions for CMOS-compatible inputs
SN54ASC'
NOM
5
SN74ASC'
MAX
5.5
MIN
4.5
Vee
VIH
High-level input voltage
3.15
VIL
Low~level
MAX
5.5
VI
Input voltage
0
Vee
0
Vee
V
tt
Input transition (rise and fall) times
0
300
0
300
ns
TA
Operating temperature range
-55
125
-40
85
°e
3.15
0.9
input voltage
TEXAS ."
INSTRUMENTS
POST OFFICE
NOM
5
UNIT
Supply voltage
MIN
4.5
eox 655012
• DALLAS. TEXAS 75265
V
V
0.9
V
2-5
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Table 3. Specifications for Output Standard Cells
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
•c
Supply voltage range; VCC ................................................................ -0.5 V to 7 V
Output clamp current. 10K (VOVCC) ............... ; ................................... ±-20 mA
Continuous output current (VO=O to VCC) ........................................................ ±25 mA
Operating free-air temperature range: SN54ASC· ............................ , ................ -55°C to 1 ~50C
SN74ASC' .............................................. -40°C to B5°C
Storage temperature range .............................................................. -65°C to 150°C
recommended operating conditions
CD
:i'
;:;
5'
::J
til
~
SN74ASC'
SN54ASC'
Vee
Supply voltage
MIN
4.5
Vo
Output voltage
0
10H
High-level output currenH
10L
Low-level output current
TA
Operating temperature range
NOM
5
MAX
5.5
MIN
4.5
NOM
5
0
VCC
As specified on individual
MAX
5.5
VCC
125
I
V
V
mA
data sheets
-55
UNIT
mA
-40
85
°C
t Applies for all except open-~ec) . '"
Operating free-air temperature range: SN54ASC' ............................................. -55°C to 125°C
SN74ASC' .............................................. -40°C to 85°C
Storage temperature range .............................................................. -65°C to 150°C
recommended operating conditions for TTL-compatible 1I0s
SN54ASC'
Vce
Supply voltage
MIN
4.5
Vo
Output voltage
0
10H
High-level output currentt
10L
Low-level output current
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
0
tt
Input transition (rise and and fall) times
TA
Operating temperature range
t Applies for all except
2-6
open~drain
NOM
5
SN74ASC'
MAX
5.5
MIN
4.5
0
Vcc
As specified on individual
NOM
5
MAX
5.5
Vcc
0.8
V
0.8
V
ns
°e
0
0
Vec
200
0
Vec
200
-55
125
-40
85
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
V
mA
2
output pells.
V
mA
data sheets
2
UNIT
V
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
recommended operating conditions for CMOS-compatible II0s
SN74ASC'
SN54ASC'
MIN
Vee
Supply voltage
4.5
Vo
Output voltage
0
IOH
High-level output currentt
IOL
Low-level output current
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
0
tt
Input transition (rise and and fall) times
TA
Operating temperature range
NOM
5
MAX
MIN
5.5
4.5
0
Vee
As specified on individual
NOM
5
MAX
5.5
Vee
V
V
mA
data sheets
mA
3.15
3.15
UNIT
0.9
V
0.9
V
ns
·e
0
0
Vee
300
0
Vee
300
-55
125
-40
85
V
•
t Applies for all except open-drain output cells.
~
fI)
C
o
'';:;
'c
=t:
CD
C
TEXAS . "
INSTRUMENTS
POST OFFICE BOX B55012 • DALLAS, TEXAS 75265
2-7
PARAMETER MEASUREMENT INFORMATION
FROM OUTPUT
UNDER TEST
----1'·.
TEST
I PARAMETER
POINT
lCl
I
I
tpd
CELLS
INTERNAL and INPUT
CL t
OpFand1pF
tpd
OUTPUTS
15 pF and 50 pF
tel includes probe and test fixture capacitance.
lOAD CIRCUIT
•
FIGURE 1. TOTEM-POLE OUTPUTS
- -....- - V C C
o
....
S·
CI)
;::;:
FROM OUTPUT _ _ _• TEST
UNDER TEST
POINT
O·
lCl-
:::J
(I)
~
50 PF t
lOAD CIRCUIT
t CL includes probe and test fixture capacitance.
FIGURE 2. OPEN-DRAIN OUTPUTS
TEST
FROM OUTPUT _ _ _P..,O.IN_T_-,\R,.,lllr--_'"
UNDER TEST
LOAD CIRCUIT
PARAMETER
ten
tdis
tpd
INTERNAL BUFFER
RL
tpZH
40 kll
tpZL
20 kll
tpHZ
40 kll
tpLZ
20 kll
~
tpHL
CL t
1 pF
1 pF
o pF
-
and
1 pF
OUTPUT OR 110
RL
1 kll
CL t
15 pF
and
50 pF
1 kll
50 pF
-
15 pF
and
50 pF
S1
S2
OPEN
CLOSED
CLOSED
OPEN
OPEN
CLOSED
CLOSED
OPEN
OPEN
OPEN
tCL includes probe and test fixture capacitance.
FIGURE 3. 3-STATE OUTPUTS
2-8
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 76265
PARAMETER MEASUREMENT INFORMATION
-..I tt!'-
.-r:=--~90~%~-1- -
INTERNAL
OUT-Of-PHASE
OUTPUT
INTERNAL
OUT-Of-PHASE 1
OUTPUT
I.
I
1
1
44%
INTERNAL
I
IN-PHASE
.
44%
OUTPUT_ _ _ _"'_
I
FIGURE 4. CMOS INPUT CELL ANO CMOS 3-STATE
BIDIRECTIONAL INPUT PROPAGATION DELAY TIME
VOLTAGE WAVEFORMS
-+l tt J4-
""''''''-'''''''9'''''0''''%''';- . - 44%
I
OUTPUT
44%
/.-tPHL...I
IN-PHASE
OUTPUT
~tPLHr.l1
_ _ _ _J
44%
I
I
1
VOL
,
en
c:
..
0)
"
CO
~1_0_%_ _ _
:
I
. 1 44%
tpHL~
INPUT
I
0
~=----o
OUT -Of-PHASE
OUTPUT
L
I 44%
1
I
-Vee
-
tPLH~
I
I
-;_..1.
FIGURE 5. TTL INPUT CELL AND TTL 3-STATE
BIDIRECTIONAL INPUT PROPAGATION DELAY TIME
VOLTAGE WAVEFORMS
1
1
OUT-Of-PHASE
o
tPLH~)t.----=-'....... - -VOH
I
~
I+-tPHL~ -----if-....I.
INPUT
- -3 V
.1 ' -_ _
~tPHL~ -
I
-
1 10%
1.3V
~tpHZ
-
-
VOL
FIGURE 6. INTERNAL TOTEM-POLE OUTPUT
PROPAGATION DELAY TIME VOLTAGE
WAVEFORMS
IN-PHASE
OUTPUT
,n
c:
o
-;:
"c.
;;::
1
~--VOH
!.tPHL+!
90%
I
-VOL
44
J
VOH
a:
tPLZ~~
!
_ 10%
:I
~"'<
CI)
C
44%
~tPZL-.I
VOL
FIGURE 7. INTERNAL 3-STATE-OUTPUT BUFFER
DISABLE AND ENABLE VOLTAGE WAVEFORMS
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-9
PARAMETER MEASUREMENT INFORMATION
I!.tr~.
I
INPUT
C
CI)
10%
CMOS/TTL
OUTPUT
5'
~
'--1- I
44%
I
I
!.-CMOS..../
tpLH
I
,,
Iii
tplH
I
I
1.3 V
Ii.- tpLH
I
VOH
50%
1.3 V
___
I
I
I
-+II
It-
-VOL
CMOS...!
tPHL
-1--
CMOS - . /
CMOS/TTL
OUTPUT
I
-VOH
I
I
I
I
j.-TTL-tI
tPLH
5'
CQ
!fl
1.3 V
VOL
FIGURE 8. CMOS/TTL OUTPUT AND 3·STATE
BIDIRECTIONAL INPUT/OUTPUT PROPAGATION
DELAY TIME VOLTAGE WAVEFORMS
I»
:::3
~
G)
0'
en
•
tf
1
1- _ _ _ _ _
en
I»
0
\t- TTL
tPHL4
r+
.
10%
j+-CMOS-..j
tPHL
. !.-TTL
I»
90%
I
I
90%
INPUT
-<
I
I
I
---VCC
I
44%
II
::+
0'
:::3
!!
90%
I
I
•-
!t-tf'"
90%
I
10%
--vcc
I
10%
0
~CMOS-,
I.-- TTL--t
tpZH
I
CMOS/TTL
OUTPUT
I
tPHZ~
VOH
"
50%
1
I
I
~tPLZ~
CMOS/TTL
OUTPUT
tpZH
- ---Hi-Z
j.-CMOS...../
tpZL
-Hi-Z
-1--
I
I
I
I
,
I
VOL
FIGURE 9. CMOS/TTL 3·STATE BIDIRECTIONAL
INPUT/OUTPUT DISABLE AND ENABLE VOLTAGE
WAVEFORMS
2-10
~
TEXAS
INSTRUMENTS
POST O.FIOS IlOX 656612 • DALLAS, texAS 76265
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
INTRODUCTION
These symbols, terms, and definitions are in accordance with those currently agreed upon by the JEOEC
Council of the Electronic Industries Association (EIA) for use in the USA and by the International
Electrotechnical Commission (lEC) for international use.
OPERATING CONDITIONS AND CHARACTERISTICS (IN SEQUENCE BY LETTER SYMBOLS)
Cpd
Power dissipation capacitance
Used to determine the no-load dynamic power dissipation per logic function (see individual circuit
pages): Po = Cpd VCC 2 f+lee Vee·
f max
Maximum clock frequency
The highest rate at which the clock input of a bistable circuit can be driven through its required
sequence while maintaining stable transitions of logic level at the output with input conditions
established that should cause changes of output logic level in accord.ance with the specification.
ICC
Supply current
The current into* the Vee supply terminal of an integrated circuit.
IIH
High-level input current
The current into * an input when a high-level voltage is applied to that input.
IlL
Low-level input current
The current into * an input when a low-level voltage is applied to that input.
IOH
High-level output current
The current into * an output with input conditions applied that, according to the product specification.
will establish a high level at the output.
IOL
•
~
co
en
en
o
S
"0
C
CO
o
C)
C
"';::
CO
a:
..
en
c
o
"2
"';::
~
Low-level output current
The current into * an output with input conditions applied that, according to the product specification,
wiU establish a low level at the outP4t.
IOZ
Off-state (high-impedance-state) output current (of a three-state output)
The current flowing into* an output having three-state capability with input conditions established
that, according to the production specification, will establish the high-impedance state at the output.
VIH
High-level input voltage
An input voltage within the more positive (less negative) of the two ranges of values used to represent
the binary variables.
NOTE: A minimum is specified that is the least-positive value of high-level input voltage for which
operation of the logic element within specification limits is guaranteed.
VIL
Low-level input voltage
An input voltage level within the less positive (more negative) of the two ranges of values used to
represent the binary variables.
NOTE: A minimum is specified that is the most-positive value of low-level input voltage for which
operation of the logic element within specification limits is guaranteed.
CD
C
*Current out of a terminal is given as a negative value.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-"
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
ID'
VOH
High-level output voltage
The voltage at an output terminal with input conditions applied that. according to product specification,.
will establish a high level at the output.
VOL
Low-Ievei output voltage
The voltage at an output terminal with input conditions applied that. according to product specification.
will establish a low level at the output.
VT+
Positive-going threshold level
The voltage level at a transition-operated input that causes operation of the logic element according
to specification as the input voltage rises from a level below the negative-going threshold voltage. VT _.
VT-
Negative-going threshold level
The voltage level at a transition-operated input that causes operation of the logic element according
to specification as the input voltage falls from a level above the positive-going threshold voltage. VT +.
ta
Access time
The time interval between the application of a specified input pulse and the availability of valid signals
at an output.
tdis
Disable time lof a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms. '
with the three-state output changing from either of the defined active levels (high or low) to a highimpedance (off) state. (tdis = tPHZ or tPLZ).
ten
Enable time lof a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms.
with the three-state output changing from a high-impedance (off) state to either of the defined active
levels (high or low). (ten = tpZH or tpzLI.
tf
Fall time
The time interval between two reference points (90% and 10% unless otherwise specified) on a
waveform that is changing from the defined high level to the defined low level.
th
Hold time
The time interval during which a signal is retained at a specified input terminal after an active transition
occurs at another specified input terminal.
NOTES: 1. The hold time is the actual time interval between two signal events and is determined
by the system in which the digital circuit operates. A minimum value is specified that
is the shortest interval for which correct operation of the digital circuit is guaranteed.
C
....5"
CD
=+
S"
::J
.til
::a
...5"
m
cotil
.
m
::J
CC)
S-
til
til
..
m
-<
2. The hold time may have a negative value in which case the minimum limit defines the
longest interval (between the release of the signal and the active transition) for which
correct operation of the digital circuit is guaranteed.
tpd
2-12
Propagation delay time
The time between ~he specified reference points on the input and output voltage waveforms with
the output changing from one defined level (high or low) to the other defined level. (tpd = tPHL or
tPLH)·
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
GLOSSARY
SYMBOLS. TERMS. AND DEFINTIONS
tPHL
Propagation delay time. high-to-Iow level output
The time between the specified reference points on the input and output voltage waveforms with
the output changing from the defined high level to the defined low level.
Disable time (of a three-state output) from high level
The time interval between the specified reference points on the input and the output voltage waveforms
with the three-state output changing from the defined high level to a high-impedance (off) state .
Propagation delay time. low-to-high-Ievel output
The time between the specified reference points on the input and output voltage waveforms with
the output changing from the defined low level to the defined high level.
Disable time (of a three-state output) from low level
The time interval between the specified reference points on the input and output voltage waveforms
with the three-state output changing from the defined low level to a high-impedance (off) state.
tpZH
Enable time (of a three-state output) to high level
The time interval between the specified reference points on the input and output voltage waveforms
with the three-state output changing from a high-impedance (off) state to the defined high level.
Enable time (of a three-state output) to low level
The time interval between the specified reference points on the input and output voltage waveforms
with the three-state output changing from a high-impedance (off) state to the defined low level.
Rise time
The time interval betWeen two reference points (10% and 90% unless otherwise specified) on a
waveform that is changing from the defined low level to the defined high level.
•
...>-
ca
II)
II)
.E
o
"C
C
ca
oCD
C
'.jj
ca
a:
oc
o
'2
'.jj
tsr
tsu
·Sense recovery time
The time interval needed to switch a memory from a write mode to a read mode and to obtain valid
data signals at the output.
;;:
Setup time
The time interval between the application of a signal at a specified input terminal and a subsequent
active transition at another specified input terminal.
NOTES: 1. The setup time is the actual time interval between two signal events and is determined
by the system in which the digital circuit operates. A minimum value is specified that
is the shortest interval for which correct operation of the digital circuit is guaranteed.
2. The setup time may have a negative value in which case the minimum limit defines the
longest interval (between the active transition and the application of the other signal)
for which correct operation of the digital circuit is guaranteed.
tt
Transition time (general)
The time interval between two reference points (10% and 90% unless otherwise specified) on a
waveform that is changing from the defined low level to the defined high level (rise time) or from
the defined high level to the defined low level (fall time).
tw
Pulse duration (width)
The time interval between specified reference points on the leading and trailing edges of the pulse
waveform.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
II)
o
2-13
II
c
CD
:::;.'r
0'
j
~
2·14
Product Guide
3-1
II...
"
o
C.
I:
(')
1+
C)
I:
is.:
CD
3-2
PRODUCT GUIDE
00
2-INPUT POSITIVE-NAND GATES
logic symbol
:==r=Y--v
tpd Ins)
CELL NAME
Cpd IpF)
CL = 0 pF
CL=lpF
0.9
0.8
0.7
0.6
0.6
2.0
1.3
1.1
1.0
0.8
NA210LH
NA220LH
NA230LH
NA240LH
NA260LH
0.51
1.00
1.51
2.06
2.98
Label: NA2nOLH A,B,Y
02
2-INPUT POSITIVE-NOR GATES
logic symbol
:=D-v
tpd Ins)
CELL NAME
Cpd IpF)
CL = 0 pF
CL = 1 pF
0.9
0.8
0.8
0.7
2.4
1.5
1.3
1.1
N0210LH
N0220LH
N0230LH
N0240LH
•
....CJ
0.33
0.52
0.80
0.98
:::I
..
"C
o
Label: N02nOLH A,B,Y;
~
04
INVERTERS
logic symbol
tpd Ins)
CELL NAME
Cpd IpF)
CL = OpF
CL=lpF
2.2
0.9
0.6
0.5
0.5
0.4
0.4
2.3
1.7
1.1
0.9
0.8
0.7
0.6
IV101LH
Iv110LH
IV120LH
IV130LH
IV140Lii
IV160LH
IV'180LH
7.22
0.44
0.80
1.29
1.61
2.39
3.16
Label: IVinOLH A,Y;
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, 'TEXAS 15265
3-3
PRODUCT GUIDE
08
2-INPUT POSITIVE-AND GATES
logic symbol
:==D-
tpd (nsl
CELL NAME
CL
AN210LH
AN220LH
AN240LH
AN260LH
=0
pF
CL
1.3
1.5
1.9
1.5
=
Cpd (pFI
1 pF
2.1
1.9
2.1
1.7
0.90
1.20
2.32
3.0B
Label: AN2nOLH A,B,Y;
•
..."tI
10
3-INPUT POSITIVE-NAND GATES
tpd (nsl
o
CELL NAME
s::::
NA310LH
NA320LH
NA330LH
NA340LH
c.
....
(')
logic symbol
CL
=0
pF
CL
O.B
0.9
O.B
O.B
=
Cpd (pFI
1 pF
2.2
1.5
1.3
1.1
0.50
0.94
1.41
1.B6
Label: NA3nOLH A,B,C,Y;
11
3-INPUT POSITIVE-AND GATES
logic symbol
)-Y
tpd (nsl
CELL NAME
CL
AN310LH
AN320LH
AN340LH
AN360LH
=0
Cpd (pFI
pF
CL = 1 pF
1.6
1.7
2.2
1.7
2.4
2.2
2.5
1.9
1.06
1.56
2.59
4.0B
Label: AN3nOLH A,B,C,Y;
20
4-INPUT POSITIVE-NAND GATES
logic symbol
tpd (nsl
CELL NAME
CL
NA410LH
NA420LH
NA430LH
=0
pF
O.B
1.0
1.0
CL
=
Cpd (pFI
1 pF
2.6
1.B
1.5
0.50
0.96
1.46
Label: NA4nOLH A,B,C,D,Y;
3-4
"!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
y
PRODUCT GUIDE
21
4-INPUT POSITIVE-AND GATES
logic symbol
tpd (nsl
CELL NAME
AN410LH
AN420LH
AN440LH
AN460LH
Cpd (pFI
CL = 0 pF
CL = 1 pF
1.8
2.0
2.4
2.1
2.6
2.5
2.7
2.3
1.18
1.72
2.77
4.58
Label: AN4nOLH A,8,C,D,Y;
•
27
3-INPUT POSITIVE-NOR GATES
logic symbol
~~y
tpd (nsl
CELL NAME
N0310LH
N0320LH
N0330LH
Cpd (pFI
CL = 0 pF
CL = 1 pF
1.1
1.1
1.0
3.2
2.1
1.8
C~
...
0.32
0.56
0.85
(J
j
Label: N03nOLH A,B,C,Y;
"C
...o
a..
30
8-INPUT POSITIVE-NAND GATES
logic
~ymbol
A
tpd (ns)
CELL NAME
NA810LH
NA820LH
B
C - -........_ _
Cpd (pFI
CL=OpF
CL=lpF
1.9
1.9
4.5
3.3
o
0.61
1.13
E
~"'---
Y
F--~
Label: NA8nOLH A,B,C,D,E,F,G,H,Y;
G
H
32
2-INPUT POSITIVE-OR GATES
logic symbol
tpd (ns)
CELL. NAME
OR210LH
OR220LH
OR240LH
OR260LH
Cpd (pF)
CL = 0 pF
CL = 1 pF
1.5
1.7
1.6
1.5
2.3
2.1
1.8
1.7
0.86
1.62
3.09
4.70
Label: OR2nOLH A,B,Y;'
TEXAS •
INSTRUMENTS
POST OFFICE
aox
655012 •
OAL.LA~,
TEXAS 75265
3-5
PRODUCT GUIDE
74
D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
logic symbol
DFB2PLH, DTB10LH
CELL NAME
fmax IMHzl
Cpd IpFI
DFB20LH
DTB10LH
46.3
55.8
3.76
2.12
Label: D
P
ClK R E
C1Z f l . a
D
ClRZ
BnOLH CLRZ,PREZ,D,CLK,O,OZ;
DFC20LH
DTC10Ll-i
52.1
52.1
3.39
2.10
•
64.2
55.8
ClKB=1 a
1D
D
az
ClRZ
R
2.71
2.21
Label: D_NnOLH D,CLK,O,OZ;
DFP20LH
DTP10LH
Label: 0
DFN20lH, OTN10lH
55.8
55.8
3.49
2.50
ClK--Fl- a
D~ az
PnOLH PREZ,D,CLK,O,OZ;
DFY20LH
69.2
4.63
OFP20lH, OTP10lH
Label: DFY20LH PREZ,CLK,O,OZ;
59.2
DFZ20LH
I
az
DFC20lH, DTC10lH
Label: D_CnOLH CLRZ,D,CLK,O,OZ;
DFN20LH
DTN10LH
1D
R
PREZEa
ClK
C1
az
4.94
I
Label: DFZ20LH CLRZ,PREZ,CLK,O,OZ;
o
10
DFY20LH
PREz-n-a
ClK~az
OFZ20LH
PREZEa
ClK
R
az
ClRZ
R
75
D-TYPE LUCHES WITH ACTIVE-HIGH ENABLE
logic symbol
tpd Insl
CELL NAME
LAH10LH
LAH20LH
Cpd IpFI
CL = 0 pF
CL = 1 pF
1.6
1.6
2.4
2.0
2.00
2.81
label: LAHnOLH D,C,O,OZ;
3-6
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
PRODUCT GUIDE
85
4-BIT MAGNITUDE COMPARATORS
logic symbol
tpd (nsl
CELL NAME
= ° pF
I
12.0
I
CL
S85LH
Cpdt (pFI
= 1 pF
CL
13.6
12.5
Label: S85LH P3,P2,P1 ,PO,03,02,01 ,OO,PGT01 ,PLTO 1,
PEOO 1,PGTOO,PLTOO,PEQOO;
}re~
PO
P1
P2
P3
PLTOI
<
PEOOI
PGTOI
00
01
>
:}-
02
03
PO
PGTOO
II
86
2-INPUT EXCLUSIVE-OR GATES
logic symbol
:=D--
tpd (nsl
CELL NAME
CL
= °pF
CL
1.8
2.0
2.4
EX210LH
EX220LH
EX240LH
= 1 pF
2.3
2.0
2.0
Cpd (pFI
.po
(,)
y
:::J
"C
...o
1.00
1.35
2.55
Q.
Label: EX2nOLH A,B,Y;
109
J-K POSITIVE-EDGE-TRIGGERED
logic symbol
FLIP-FLOPS
CELL NAME
JKB20LH
I
I
fmax (MHzl
44.2
I
I
Cod (pFI
PREZ
Q
4.81
Label: JKB20LH CLRZ,PREZ,J,KZ,CLK,O,OZ;
CLK
---;:> C1
KZ
oz
CLRZ
tThe equivalent po~er dissipation capacitance does not include interconnect capacitance.
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75266
3-7
PRODUCT GUIDE
137
3-LlNE TO 8-LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
tpd Insl
CELL NAME
S137LH
Cpdt IpFI
CL=OpF
I
CL=lpF
12.0
I
12.7
logic symbol
GLZ
YO
17.59
Label: S137LH C,B,A,GLZ,G2Z,G1,YO,Y1,Y2,Y3,Y4,Y5,
Y6,Y7;
A
Vl
B
Y2
C
V3
Y4
II...
G1
Y5
G2Z
V6
"'D
V7
o
Q.
c:
~
138
C)
3-LlNE TO 8-LINE DECODERS/DEMULTIPLEXERS
logic symbol
c:
c:CD
tpd Insl
CELL NAME
S138LH
Cpdt IpFI
CL=OpF
I
CL=lpF
7.0
I
7.7
13.77
Label: S.138LH G 1,G2AZ,G2BZ,A,B,C, YO, Y 1, Y2, Y3, Y 4,
Y5,Y6,Y7;
DMUX
A
B
C
J.~
va
Vl
V2
Y3
V4
G1
G2AZ
G2BZ
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
3-8
.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
V5
Y6
V7
PRODUCT GUIDE
139
DUAL 2-LlNE TO 4-LlNE DECODERS!
DEMULTIPLEXERS
logic symbol
tpd (nsl
CELL NAME
CL=OpF
5139LH
I CL=lpF
I
4.0
V11
B1
12.S4
4.S
V10
A1
Cpdt (pFI
V12
G1Z
Label: 5139LH Al,Bl,G1Z,A2,B2,G2Z,Vl0,Yll,Y12,
V13,Y20,Y21,Y22,Y23;
V13
V20
A2
V21
B2
V22
G2Z
V23
Q)
"C
151
·S
a-LINE TO 1-LlNE MULTIPLEXERS
5151LH
...
(J
MUX
tpd (nsl
CELL NAME
0
logic symbol
Cpdt (pFI
CL=OpF
I
CL=1pF
8.0
I
10.S
10.09
GZ
A
B
c
Label: 5151 LH GZ.A,B,C,DO,Dl,D2,D3,D4,D5.DS,D7,
y,W;
DO
:::s
EN
"C
...
0
D.
]GJ}
0
V
01
02
2
03
3
04
4
05
5
06
07
7
W
6
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
TEXAS
~
INSfRUMENlS
POST OFFICE BOX. 655012 • DALLAS, TEXAS 75265
3-9
PRODUCT GUIDE
153
DUAL 4-lINE TO 1-LINE MULTIPLEXERS
logic, symbol
tpd (ns)
CL=OpF
I
CL=1pF
8.0
I
8.7
CELL NAME
S153LH
Cpdt (pF)
A
B
8.56
label: S153LH G1Z,G2Z,A,B,C1O,C11,C12,C13,C20,
C21 ,C22,C23,Y1 ,Y2;
G1Z
C10
Y1
C11
C12
C13--~~~________~
G2Z
C20
Y2
C21
~
~
a
Q.
~
C
2
155
Ci)
C
DUAL 2-lINE TO 4-lINE DECODERSI
DEMULTIPLEXERS WITH DATA AND ENABLE LINES
c:
logic symbol
(1)
tpd (ns)
CELL NAME
CL = 0 pF
S155LH
5.0
I CL=1pF
I
5.6
CpdT IpF)
A
O} G-0
...,1 3
-
B
12.20
DMUX
Label: S155lH C1 ,G1Z,C2Z,G2Z,A,B,Y10,Y11 ,Y12,Y13,
Y20,Y21,Y22,Y23;
G1Z
r--.
C1
G4
4
G2Z
.....
C2Z
........
I"
0
Y10
1t--...
V;1
2
V12
3t--.
V13
V20
V21
~
V22
V23
tThe equivalent power dissipation capacitance does not iriclude interconnect capacitance.
3-10
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
PRODUCT GUIDE
157
QUADRUPLE 2-LlNE TO 1-LlNE NONINVERTING
MULTIPLEXERS
logic symbol
Ipd Insl
CELL NAME
CL=Oj>F
S157LH
I CL=1pF
I
6.0
Cpdt IpFI
GZ
AZ_B
7.1
9.40
A1
Label: S157LH A 1,A2,A3,A4,B1 ,B2,B3,B4,ALB,GZ,
Y1,Y2,Y3,Y4;
Y1
B1
A2
V2
B2
A3
B3
A4
B4
V3
V4
II
Q)
"'0
·S
158
QUADRUPLE 2-LlNE "to 1-LINE INVERTING
MULTIPLEXERS
e"
...
logic symbol
CJ
:::s
S158LH
.
"'0
Ipd Insl
CELL NAME
Cpdt IpFI
CL=OpF
I
CL=1pf
6.2
I
6.6
0
GZ
c..
AZ_B
12.16
Label: S151lLH A 1,A2,A3,A4,B1 ,B2,B3,B4,ALB,GZ,
Y1,Y2,Y3,Y4;
A1
B1
A2
B2
A3
B3
A4
V1
V2
V3
V4
B4
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
3-11
PROO.,CT GUIDE
161A
I
SYNCHRONOUS 4-BIT BINARY COUNTERS
WITH DIRECT CLEAR
logic symbol
CLRZ
tpd Insl
CELL NAME
CL=OpF
S161ALH
I CL=1pF
I
12.0
Cpdt IpFI
13.0
31.54
LOADZ
RCO
ENT
ENP
Label: S161ALH D,C,B,A,CLK,CLRZ,ENP,ENT,LOADZ,
OD,OC,OB,OA,RCO;
ClK
OA
A
.--....--_------08
8
[4)
[8)
C
D
oc."'D
OC
QD
163A
SYNCHRONOUS 4-BIT BINARY COUNTERS
logic symbol
C
...n
tpd Insl
CEll NAME
G')
Cl=OpF
c
S163ALH
i
9.0
Cpdt IpFI
I
Cl=1pF
I
10.0
. ClRZ
lOADZ
29.B1
RCO
ENT
Label: S163ALH D,C,B,A,CLK,CLRZ,ENP,ENT,LOADZ,
OD,OC,OB,OA,RCO;
ENP
CLK
A
OA
B
OB
C
OC
D
QD
164
a-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
logic symbol
tpd Insl
CELL NAME
CL=OpF
S164LH
5.0
I Cl=1pF
I
5.5
Cpdt IpFI
CLRZ
ClK
23.55
Label: S164LH A,B,CLK,CLRZ,OA,OB,OC,OD,OE,OF,OG,
OH;
A
B
OA
OB
OC
OD
QE
OF
QG
QH
tThe equivalent power dissipation capacitance does not incllJde interconnect capacitance.
3-12
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
PRODUCT GUIDE
165
PARALLEL-LOAD 8-81T SHIFT REGISTERS
logic symbol
tpd (nsl
CELL NAME
CL=OpF
S165LH
I CL=1pF
I
8.0
Cpdt (pFI
SH_lOZ
ClKINH
42.07
8.5
ClK
Label: S165LH A.B.C.D.E.F.G.H.CLK.CLKINH.SH_LDZ.
SER.QH.QHZ;
SER
A
10
B
10
C
0
E
F
G
QH
H
10
QHZ
II
Q)
"C
's
0
....
166
(,)
PARALLEL-LOAD 8-BIT SHIFT REGISTERS WITH
DIRECT CLEAR
-
CL=OpF
S166LH
7.5
I CL=1pF
I
...0
Q.
SRG8
tpd (nsl
CELL NAME
:::I
"C
logic symbol
Cpdt {pFI
8.4
Label: S166LH A.B.C.D.E.F.G.H.CLK.CLKINH.SER.
SH_LDZ.CLRZ.QH;
ClRZ
SH_lOZ
33.15
ClKINH
ClK
SER
A
B
2.30
C
0
E
F
G
H
QH
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
3-13
PRODUCT GUIDE
173
4-BIT D-TYPE REGISTERS WITH 3-STATE
OUTPUTS
.
logic symbol
ClR
tpd (ns)
CELL NAME
CL=OpF
S173lH
I
7.1
Cpdt (pF)
MZ
NZ
24.00
GIZ
G2Z
I CL=lpF
8.0
label: S173lH 01,02,03,04,ClK,ClR,G1Z,G2Z,MZ,NZ,
01,02,03,04;
::p
8.
C
ClK
01
02
03
01
02
03
04
04
174
HEX D-TYPE FLIP-FLOPS
...n
logic symbol
ClRZ
tpd (nsj
CEll NAME
(i)
C
Cpdt (pF)
CL=OpF
c:
CD
S174lH
8.0
ClK
I CL = 1 pF
I
8.5
01
24.44
02
03
04
label: S174lH 01 ,02,03,04,05,06,CLK,CLRZ,01,Q2,
03,04,05,06;
tl 5
06
01
02
03
04
05
06
175
QUADRUPLE 0-TYPE FLIP-FLOPS WITH
COMPLEMENTARY OUTPUTS
logic symbol
ClRZ
tpd (ns)
CELL NAME
CL=OPFI
S175lH
6.5
I
Cpdt (pF)
ClK
13.74
01
Cl=lpF
6.4
Label: S175lH 01,02,03,04,ClK,ClRZ,01.01Z,02,
02Z,Q.3,03Z,04,04Z;
02.
03
04
tThe equivalent power dissipation capacitance does not inc;lude interconnect capacitance.
3-14
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX ,661)012 • DALLAS, TeXAS 75265
01
Q1Z
Q2
02Z
03
03Z
04
04Z
PRODUCT GUIDE
177
1-BIT AND 3-BIT BINARY RIPPLE COUNTERS
logic symbol
tpd Ins)
CELL NAME
CL
S177LH
=0
pF
22.0
Cpdt IpF)
I
CL=1pF
I
22.5
lOADZ
23.56
ClRZ
Label: S1 77LH A.B.C.D.LDADZ.CLRZ.CLK 1Z.CLK2Z.QA.
QB.QC.QD;
ClK1Z
OA
A
10
•
DIV8
+
ClK2Z
}cr crt
B
C
0
OB
OC
Q)
00
"0
'5
CJ
...
181
ARfTHMETIC LOGIC UNITS/FUNCTION
GENERATORS
"0
o...
S1S1LH
D..
AlU
tpd Ins)
CELL NAME
U
::::J
logic symbol
Cpdt IpF)
CL=OpF
I
CL=1pF
13.0
I
14.6
80
81
46.68
Label: S1 S1LH A3Z.A2Z.A 1Z.AOZ.B3Z.B2Z.B1Z.BOZ.
CN.M.S3.S2.S 1.SO.F3Z.F2Z.F 1Z.FOZ.AEQB.
GZ.PZ.CNPl4;
82
83
M
CN
'}
4
PZ
M
GZ
f,
AEOB
CNPl4
C1
AOZ
[11
FOZ
[21
F1Z
141
F2Z
181
F3Z
BOZ
A1Z
B1Z
A2Z
B2Z
A3Z
B3Z
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
TEXAS .. "
INSTRUMENTS
POST OFFltE BOX 655012 • DALLAS, TEXAS 15265
3-15
PRODUCT GUIDE
191
, SYNCHRONOUS UP/DOWN BINARY COUNTERS
WITH DOWN/UP MODE CONTROL
logic symbol
CTRDIV16
tpd (ns)
CELL NAME
CL=OpF
S191LH
I CL=1pF
I
11.5
12.6
Cpdt (pF)
CTENZ
D_UZ
2(CT-O)Z6
37.26
Label: S191LH D,C,B,A,CLK,D_UZ,CTENZ,LOADZ,OD,
OC,OB,OA,RCOZ,MACMIN;
MAX_MIN
3icT-161Z6
CLK
RCOZ
LOADZ
A
(11
QA
B
C
[2J
[4J
QB
QC
D
[8J
QD
-a
(;
c.
c
n
...
193
SYNCHRONOUS 4-BIT UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
logic symbol
G)
c
is:
tpd (ns)
CELL NAME
CD
S193LH
CTRDIV 16
Cpdt (pF)
CL = 0 pF
I
CL=lpF
11.0
I
11.5
CLR
UP
34.84
Label: S193LH A,B,C,D,UP,DOWN,LOADZ,CLR,BOZ,COZ,
OA,OB,OC,OD;
CT-O
COZ
DOWN
BOZ
LOADZ
A
[2J
OB
C
(4J
QC
D
[81
QD
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
3-16
TEXAS
QA
B
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
PRODUCT GUIDE
194A
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT
REGISTERS
logic symbol
tpd (nsl
CEll NAME
S194ALH
ClRZ
Cpdt (pFI
Cl=OpF
I
Cl=1pF
5.0
I
5.9
SO
S1
25.45
ClK
Label: S194ALH A,B,C,D,SRSER,SLSER,CLK,CLRZ,S1,SO,
QA,OB,OC,OD;
SRSER
A
B
C
0
SLSER
QA
3.40
3.40
3.40
3.40
2.40
OB
OC
00
II
Q)
"'0
·S
195A
4-BIT PARALLEL-ACCESS SHIFT REGISTERS
~
...
logic symbol
(.)
tpd (nsl
CELL NAME
S195ALH
::J
"'0
SRG4
Cpdt (pFI
Cl=OpF
I
Cl=1pF
5.5
I
6.4
CLRZ
0~
SH_LOZ
a..
21.95
Label: S195ALH CLRZ,CLK,SH_LDZ,J,KZ,A,B,C,O,OA,
OB,OC,OD,ODZ;
ClK
J
KZ
A
B
C
0
QA
2,30
2,30
2,30
OB
OC
00
aDZ
tThe equivalent power dissipation capacitance does not incluqe interconnect capacitance.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
/
3-17
PRODUCT GUIDE
244
OCTAL INTERNAL 3-STATE BUS BUFFERS
logic symbol
G1Z
tpd (ns)
CELL NAME
5244LH
Cpdt (pF)
CL=OpF
I
CL=lpF
2.6
I
4.3
B.B2
Label: 5244LH A 11,A 12,A 13,A 14,G1Z.A21,A22.A23,
A24,G2Z,Yll,Y12,Y13,Y14,Y21,Y22,Y23,Y24;
Yll
All
A12
Y12
A13
Y13
A14
Y14
G2Z
o:p 245
Q.
C
OCTAL INTERNAL 3-STATE BUS TRANSCEIVERS
...n
A21
Y21
A22
YZZ
A23
Y23
AZ4
Y24
logic symbol
GZ
OIR
tpd (ns)
C)
CELL NAME
C
s:CD
5245LH
Cl = 0 pF
I
5.0
I
Cpdt (pF)
CL=lpF
6.7
81
Al
22.96
Label: 524SLH A l,A2,A3.A4.AS,A6.A 7,AB,B l,B2,B3,
B4,BS,B6,B7,BB,GZ,DIR;
A2
82
A3'
83
A4
84
A5
8S
A6
A7
86
87
A8
88
251
8-LlNE TO 1-LlNE MULTIPLEXERS WITH
3-STATE OUTPUTS
logic symbol
MUX
GZ
A
tpd (ns)
CELL NAME
CL=OpF
5251LH'
9.7
8
Cpdf (pF)
I
CL=lpF
I
11.4
C
12.BS
Label: 5251 LH GZ,A,B,C,DO,Dl,D2,D3,D4,DS,D6,D7,
Y,Wl;
DO
01
02
0
1
03
2
3
04
4
05
5
06
07
6
7
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
3-18
:}G¥
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • bALLAS, TEXAS 75265
\l
\l
Y
WZ
PRODUCT GUIDE
257A
QUADRUPLE 2-LlNE TO 1-LlNE
MULTIPLEXERS WITH 3-STATE OUTPUTS
logic symbol
tpd {nsl
CEll NAME
S257ALH
Cl=OpF
I
5.0
I
Cpdt {pFI
Cl = 1 pF
6.7
GZ
AZ_B
10.8
Label: S257ALH A 1 ,A2,A3,A4,B1 ,B2,B3,B4,GZ,AZ_B,
Y1,Y2,Y3,Y4;
A1
B1
A2
B2
A3
B3
A4
.,
'\l
Y1
Y2
Y3
Y4
B4
258A,
QUADRUPLE 2-LINE TO 1-LINE INVERTING
MULTIPLEXERS WITH 3-STATE OUTPUTS
...u
logic symbol
-6o
..
tpd {nsl
CEll NAME
S258ALH
Cl = 0 pF
I
5.0
I
Cpdt {pFI
Cl=1pF
6.7
•
a..
GZ
AZ_B
7.28
Label: S258ALH A 1 ,A2,A3,A4,B1 ,B2,B3,B4,GZ,ALB,
Y1,Y2,Y3,Y4;
A1
B1
A2
B2
Y1
Y2
A3
B3
Y3
A4
B4
Y4
tThe equivalent power dissipation capacitance does' not include interconnect capacitance.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 61:Hi012 • DALLAS, TeXAS 76265
3-19
PRODUCT GUIDE
259,
8-BIT ADDRESSABLE LATCHES
logic symbol
50
tpd Ins.)
CELL NAME
S259LH
51
Cpdt IpF)
CL=OpF
I
CL=·1pF
6.0
I
6 ..6
O}SM
2 .
52
GZ
40.59
Label: S259LH CLRZ,D,GZ,SO,S1 ,S2,QO,Q1 ,Q2,Q3,Q4,
Q5,Q6,Q7;
~
0
CLRZ
9,00
'QO
10,OR
9,10
Q1
10,lR
9,20
Q2
10JR
9,30
Q3
10JR
."
a
9,40
Q4
10,4R
Q,
...c
9,5.0
()
10;iiR
C)
10;6R
a:CD
9,70
10,7R
Q5
9,60
c
Q6
Q7
260
5-INPUT POSITIVE-NOR GATES
logic symbol
A@:
~=y-.
B
tpd Ins)
CELL NAME
N0510LH
N0520LH
Cpd (pF)
CL = 0 pF
CL = 1 pF
1.7
1.6
5.0
3.2
0.37
0.64
.
Label: N05nOLH A,B,C,D,E, Y;
266
2-INPUT EXCLUSIVE-NOR GATES
logic symbol
tpd Ins)
CELL NAME
CL = 0 pF
EN210LH
1.4
J
I
Cpd IpF)
CL = 1 pF
2.4
A~.y
B~
1.09
Label: EN210LH A,B,Y;
tThe equivalent power dissipation capacitance does not include interconnect cap~citance.
3-20
y
PRODUCT GUIDE
273
OCTAL D-TYPE FLIP-FLOPS
logic symbol
ClRZ
tpd Ins)
CELL NAME
S273LH
Cpdt IpF)
CL=OpF
I
CL=lpF
5.0
I
5.8
ClK
22.45
Label: S273LH D1,D2,D3,D4,D5,DS,D7,DB,CLK,CLRZ,
01,02,03,04,05,OS,07,08;
D1
01
02
02
03
03
04
04
05
05
06
07
06
08
as
07
279
CD
S-R LATCHES
"C
logic symbol
'5
CELL NAME
Cpd IpF)
CL=OpF
CL=lpF
2.0
2.2
2.8
2.7
~:
~~.
tpd Insl
LAB10LH
LAB20lH
II
RZ
R
2.11
3.20
Label: LABnOLH SZ,RZ,O,QZ;
CJ
...
(J
:::J
"C
0
...
Q.
280
9-BIT ODD/EVEN PARITY
GENERATORS/CHECKERS
logic symbol
2k
A
tpd Ins)
CELL NAME
S280LH
Cpdt IpF)
CL=OpF
I
CL=1pF
11.0
I
11.5
Label: S280LH A,B,C,D,E,G,H,I,EVEN,ODD;
25.80
B
C
D
EVEN
E
F
ODD
G
H
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
TEXAS ."
INSTRUMENlS
/'Otf OFFICi lox 651iOU • bAllAS, nXAS 11!:l1iG
3-21
PRODUCT GUIDE
283
4-BIT BINARY FULL ADDERS WITH FAST CARRY
tpd Ins 1
CELL NAME
S283LH
Cpdt IpFI
CL=OpF
I
CL=1pF
8.5
I
9.1
36.28
Label: S283LH A4,A3,A2,A 1,B4,B3,B2,B1 ,CO,SUM4,
SUM3,SUM2,SUM 1,C4;
logic symbol
A1
A2
A3
A4
B1
B2
B3
1:
B4
} {
}
CO
CI
CO
SUM1
SUM2
SUM3
SUM4
C4
l1li-29-8------------------------------------------------"'0
o""
c.
c
(")
QUADRUPLE 2-INPUT MULTIPLEXERS WITH
NEGATIVE-EDGE-TRIGGERED REGISTER
logic symbol
tpd Insl
r+
CELL NAME
G)
C
CL=OpF
S298LH
s:
CD
6.0
I CL=1pF
J
6.8
Label: S298LH A 1 ,A2,B1 ,B2,C1.C2,Dl,D2,
CLKZ,WS,QA,QB,QC,QD;
Cpdt IpFI
18.72
WS
ClKZ
A1
A2
B1
B2
C1
C2
01
02
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
3-22
·TEXAS ."
INSTRUMENTS
POST OFFICE BOX 865012 • DALLAS, TeXAS 15265
QA
OB
OC
00
PRODUCT GUIDE
299
8-BIT BIDIRECTIONAL UNIVERSAL
SHIFT/STORAGE REGISTERS
logic symbol
SRGS
tpd (nsl
CELL NAME
Cpdt (pFI
CL = 0 pF
S299LH
G1Z
1 CL = 1 pF
I
7.1
B.O
ClRZ
3ENS
G22
60.02
so
Label: S299LH SO,S l,G 1Z,G2Z,SL,SR,CLK,CLRZ,QAP,
QHP.A_QA,B_QB,C_QC,D_QD,E_QE,
F_QF,G_QG,H_QH;
51
elK
SR
OAP
A_OA
II
B_OB
C_QC
D_QD
CD
E_QE
"t:S
·S
F_OF
G_OG
~
H_QH
QHP
2.4D
Sl
...
U
:::J
"t:S
0
...
299X
Q.
8-BIT BIDIRECTIONAL UNIVERSAL SHIFT
REGISTERS
logiC symbol
5RG8
CLRZ
50
tpd (nsl
CELL NAME
CL
S299XLH
=0
5.0
pF
I·
I.
CL
= 1 pF
5.9
Cpdt (pFI
4B.89
Label: S299XLH A,B,C,D,E,F,G,H,SO,Sl,SL,SR,CLK,
CLRZ,QA,QB,QC,QD,QE,QF,QG,QH;
51
CLK
5R
QA
A
3,4D
8
3,4D
QS
C
QC
D
QD
E
QE
F
QF
QG
G
H
3,4D
5L
2,4D
QH
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
TEXAS .. "
INSTRUMENlS
POST OFFICE BOX 856012 • DAllAS. TEXAS 75265
3-23
PRODUCT GUIDE
373
8-BIT O-TYPE LATCHES WITH
3-STATE OUTPUTS
logic symbol
tpd (nsl
CEll NAME
Cpdt (pFI
Cl = 0 pF
S373LH
ICl = 1 pF
I
5.0
oez
e
6.7
D1
02
03
D4
05
06
07
08
17.07
Label: S373LH D1,D2,D3,D4,D5,D6,D7,DS,C,DCZ,Q1,
Q2,Q3,Q4,Q5,Q6,Q7,QS;
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
11_..----_ _ _ __
.
."
o
Q.
c
a
...
374
8-BIT O-TYPE FLIP-FLOPS WITH
3-STATE OUTPUTS
logic symbol
tpd (nsl
OCl
CELL NAME
S374LH
Cpdt (pFI
Cl=OpF
I
Cl=1pF
5.0
I
6.7
ClK
22·S0
Label: S374LH D1,D2,D3,D4,D5,D6,D7,DB,CLK,QCZ,
Q1,Q2,Q3,Q4,Q5,Q6,Q7,QS;
01
Q1
02
Q2
03
Q3
04
Q4
05
Q5
06
Q6
07
07
08
08
375
4-BIT BISTABLE LATCHES
logic symbol
01
tpd (nsl
CEll NAME
S375LH
Cpdt (pFI
Cl=OpF
I
CL=1pF
4.5
I
6.0
7.32
Label: S375LH D1 ,D2,D3,D4,C1 C2,C3C4,Q1 ,Q 1Z,Q2,
Q2Z,Q3,Q3Z,Q4,Q4Z;
C1C2
02
03
C3C4
04
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
3-24
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 15265
10
Q1
01l
Q2
Q2l
Q3
Q3l
Q4
Q4Z
PRODUCT GUIDE
393
DUAL 4-BIT RIPPLE COUNTERS
logic symbol
CTROIV16
tpd (ns)
CELL NAME
S393LH
Cpdt (pF)
CL=OpF
I
CL=lpF
21.0
I
21.5
CT-O
CLRl
16.92
Al----'==>(> +
Label: S393LH A1,CLR1,A2,CLR2,QA1,QB1,QC1,QD1,
QA2,QB2,QC2,QD2;
{
GAl
QBl
aCl
001
aA2
CLR2
aB2
aC2
A2
002
II
G)
"C
398
·S
QUADRUPLE 2-INPUT MULTIPLEXERS WITH
POSITIVE-EDGE-TRIGGERED COMPLEMENTARY
OUTPUT REGISTER
S398LH
..
"C
0
WS
Cpdt (pF)
5.5
...
(,)
j
tpd (ns)
CELL NAME
CL = 0 pF
~
logic symbol
ClK
D..
ICL=lPF
I
6.4
Al
19.42
Label: S398LH A l,A2,Bl ,B2,C1 ,C2,Dl ,D2,CLK,WS,QA,
QAZ,QB,QBZ,QC,QCZ,QD,QDZ;
GA
A2
aAZ
B1
aB
B2
aBZ
Cl
ac
C2
01
acz
00
02
aDZ
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-25
PRODUCT GUIDE
399
QUADRUPLE 2-INPUT MULTIPLEXERS ,WITH
POSITIVE-EDGE-TRIGGERED REGISTER
logic symbol
tpd Ins)
CELL NAME
S399LH
WS
Cpdt IpF)
CL=OpF
I
CL=1pF
5.0
I
5.8
ClK
17.92
A1
Label: S399LH A l.A2,B1,B2,C1,C2,D1,D2,CLK,WS,QA,
QB,QC,QD;
QA
A2
B1
B2
QB
C1
C2
QC
01
QO
02
.
."
oCo 590
C
5l
8-BIT BINARY COUNTERS WITH 3-STATE
OUTPUT REGISTERS
logic symbol
G')
GZ
C
tpd Ins)
a:CD
CELL NAME
S590LH
Cpdt IpF)
CL=OpF
I
CL=1pF
10.4
I
12,1
RCK
C2
CTR8
58.24
CCKENZ
Label: S590LH CCK,CCKENZ,RCK,CCLRZ,GZ,QA,QB,QC,
QD,QE,QF,QG,QH,RCOZ;
CCK
CCLRZ
RCOZ
QA
OB
OC
GO
r-----------~r------[====OE
OF
OG
OH
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
3-26
TEXAS . "
INSTRUMENTS
POST OFFICE BO)( 66601.2. • DALLAS. TeXAS 75265
PRODUCT GUIDE
593X
a-BIT BINARY COUNTERS WITH
INPUT REGISTERS
logic symbol
tpd (ns)
CELL NAME
S593XLH
CTR8
G1
Cpdt (pF)
CL=OpF
I
CL=lpF
10.0
I
11.7
85.86
EN5
GZ
CCLRZ
Label: S593XLH A,B,C,D,E,F,G,H,CCK,CCKEN,CCKENZ,
RCK,RCKENZ,CCLRZ,CLOADZ,G 1 ,GZ,OA,OB,OC,
OD,OE,OF,OG,OH,RCOZ;
CCKEN
CCKENZ
RCOZ
CT-255
CCK
CLOADZ
RCKENZ
RCK
II
..
CD
2D
A
3D
5<;7
QA
B
QS
C
D
OC
QD
QE
QF
QG
QH
E
F
G
H
:2
:::J
CJ
(,)
:::J
.
"0
0
0..
595
a-BIT SHIFT REGISTERS WITH
OUTPUT REGISTERS
logic symbol
GZ
tpd (ns)
CELL NAME
CL=OpF
S595LH
5.5
I CL=1pF
I
7.2
Cpdt (pF)
44.64
Label: S595LH SER,SRCK,SRCLRZ,RCK,GZ,OA,OB,QC,
QD,QE,QF,QG,QH,QHP;
RCK
SRCLRZ
SRCK
SER
QA
QS
QC
QD
QE
QF
QG
2D
3\7
OH
QHP
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
3-27
PRODUCT GUIDE
5,98X
8-BIT SHIFT REGISTERS WITH
INPUT REGISTERS
logic symbol
SRGS
tpd (ns)
CELL NAME
CL=OpF
S59SXLH
I CL=1pF
I
9.S
11.5
GZ
Cpdf (pF)
SCLRZ
SCKENZ
S2.63
SCK
Label: S59SXLH A,S,C,D,E,F,G,H,RCK,SRCK,SRCKEZ,
SRLOADZ,SRCLRZ,SERO,SER 1,DS,GZ,QA,QB,
QC,QD,QE,QF,QG,QH,QHP;
SLDZ
RCK
DS
SERO
SERl
"tI
,
a
Q.
c
(")
r+
DA
2D
3D
DS
2D
3D
Q
QA
Q
Q8
DC
DD
QC
DE
QE
QD
DF
QF
DG
QG
DH
2D
3D
Q
QH
QHP
651
8-BIT BIDIRECTIONAL UNIVERSAL
TRANSCEIVER REGISTERS
logic symbol
GBAZ
tpd (ns)
CELL NAME
S651LH
Cpdt (pF)
CL=OpF
I
CL=1pF
10.4
I
11.3
91.06
Label: S651 LH GBAZ,GAB,SBA,SAB,CBA,CAB,A 1,A2,A3,
A4,A5,A6,A 7 ,AS,B 1,B2,B3,B4,B5,86,87 ,8S;
GAB
CBA
ENI (BA]
EN2 (AB]
C4
SBA
G6
C6
CAB
SAB
G7
Bl
AI
'1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
tThe equivalent power dissipation capacitance .does n~t 'inc~ude interconnect capacitance.
3-28
PRODUCT GUIDE
652
8-BIT BIDIRECTIONAL UNIVERSAL
TRANSCEIVER REGISTERS
logic symbol
tpd (nsl
'CELL NAME
CL=OpF
S652LH
10.4
Cpdt (pFI
I
CL=lpF
I
11.3
GBAZ
EN1 [BA]
GAB
EN2 lAB)
C4
eBA
104.10
GS
SBA
Label: S652LH GBAZ,GAB,SBA,SAB,CBA,CAB,A 1,A2,A3,
A4,A5,A6,A 7 .A8,B1 ,B2,B3,B4,B5,B6,B7,B8;
C6
CAB
SAB
G7
S
A1
B1
Ii
7
7
A2
B2
A3
B3
A4
B4
AS
8S
A6
B6
A7
B7
AS
BS
II
..
CD
"C
'S
C!J
CJ
::;,
.
"C
0
a.
669
SYNCHRONOUS 4-BIT UP/DOWN 81NARY
COUNTERS WITH LOOK-AHEAD
logic symbol
tpd (nsl
Cpdt (pF)
lOADZ
30.7
U_DZ
Label: S669LH D,C,B,A,CLK,U_DZ,ENPZ,ENTZ,LOADZ,
QD,QC,QB,QA,RCOZ;
ENTZ
CELL NAME
S669LH
CL=OpF
I
CL=lpF
10.0
I
11.8
CTRDIV16
Ml (lOAD]
RCOZ
ENPZ
ClK
2,3,5,6 + IC7
2,4,5,6-
A
[1)
QA
B
[2)
QB
C
[4)
QC
0
(81
QD
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 866012 • DAUAS. TeXAS 75266
3-29
PRODUCT GUIDE
686
8-BIT MAGNITUDE COMPARATORS
, logic symbol
COMP
tpd (ns)
CELL NAME
S6B6LH
Cpdt (pF)
CL = 0 pF
I
CL=lpF
9.0
I
9.8
G1Z
G2Z
43.30
PO
Label: S6B6LH PO,P1 ,P2,P3,~4,P5,P6,P7,QO,Q1 ,Q2,
Q3,Q4,Q5,Q6,Q7,G1Z,G2Z,PEQQZ,PGTQZ;
0
PI
P2
P3
P4
P
P5
•
lP-Q
PEQaz
2P>0
PGTaz
P6
P7
7
QO
0
Ql
Q2
"'0
~.
o
Q3
Q.
C
Q
Q4
n
r+
Q5
Q6
Q7
7
688
8-BIT IDENTITY COMPARATORS
logic symbol
COMP
tpd (ns)
CELL NAME
S6BBLH
Cpdt (pF)
CL=OpF
I
CL=lpF
7.5
I
B.2
G1Z
PO
15.94
Label: S6BBLH PO,P1 ,P2,P3,P4,P5,P6,P7,QO,Q1 ,Q2,
Q3,Q4,Q5,Q6,Q7,G1Z,PEQQZ;
EN
0
PI
P2
P3
P
P4
P5
P6
P7
7
QO
0
PEQaz
Ql
Q2
Q3
Q
Q4
Q5
Q6
Q7
7
tThe equiv~lent power dissipation capacitance does not include interconnect capacitance.
3-30
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 76265
PRODUCT GUIDE
888
8-BIT PROCESSOR SLICES
•
•
•
•
•
•
•
•
Parallel a-bit ALU with expansion nodes
Signed magnitude to/from two's complement conversion
Single- and double-length normalize
Signed and unsigned divides with overflow detection; input does not need to. be prescaled
Signed, mixed, and unsigned multiples
Sign, carry out, overflow and zero-detect status capabilities
3-0perand register files allow an operation and a move instruction to be combined
3 data input/output ports maximize data throughput
functional block diagram
4
C3-CO
16 XS
REGISTER FilE
WEZ
4
A3-AO
4
CK
B3-BO
r::>-++----t_'T"'____"T"_J-~===!==::=t~:; OEBZ
S
S
OA 7-0AO I!::...~--,L-+--, ___----,
II
C\)
"CI
'S
C!'
OB7-0BO
...
(,)
j
OEAZ
EAzc>~~==~~~~7
EBO
EB1
GLN---i------r---~
SElY C>---------J
Y7·YO·
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
3-31
PRODUCT GUIDE
890
MICROSEQUENCES
• 14 bits wide-addresses up to 16,384 words of microcode with one megacell
• Selects address from one of eight sources
• Independent read pointer for aid in microcode diagnostics
• Supports read~time interrupts
• Two independent loop counters
• Supports 64 powerful instructions
functional block diagram
II...
"tI
0
RAOEZ
R80EZ
OSEl
Q.
C
...
(')
G)
C
c.:CD
ZERO
5TACK
14x9
STKWRN/RER
STACK
POINTER
3
REAO
POINTER
3
14
14
t4
CCZ
3
4
INTZ
YOEZC>----------~------------------------~~
3-32
TEXAS •
INSTRUMENlS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
MUX2-MUXO
83-80
----V
0.74
0.B3
0.56
BU111LH
Label: BU11nLH A,Y;
II
2322
RETRIGGERABLE MONOSTABLE MUL TIVIBRATORS logic symbol
CD
tpd Insl
CELL NAME
cL=oPFl CL =
MVFOOLH
I
B
1 pF
9
"C
Cpd IpFI
A
20.5
B
'S
Q
Label: MVFOOLH A,B,CLRZ,Q,QZ;
~
...
CJ
j
CLRZ
QZ
R
C,~~~~xt --4---1 CX/RX
L -_ _ _.........
..
"C
0
D..
2325
HIGH-LEVEL AND LOW-LEVEL TIE-OFF GATES
logic symbol
CELL NAME: T0010LH
~HI
~LO
• Provides de termination for high- and low-level unused inputs
Label: T0010LH LO,HI;
2330
2-WIDE, 2-INPUT AND-NOR GATES
logic symbol
tpd Ins)
CELL NAME
CL=O·pF
A0221LH
1.2
I
1
Cpd IpFI
CL=lpF
2.6
0.59
Label: A0221LH A.B,C,D,Y;
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-35
PRODUCT GUIDE
2331
2-WIDE. 2-INPUT AND-OR GATES
logic symbol
A-_..r--...
tpd (nsl
CELL NAME
CL
A0220lH
=0
pF
I
CL
I
1.7
= 1 pF
Cpd (pFI
0.90
2.6
label: A0220lH A,B,C,D,Y;
B--"'L-_"
Y
C--...r--...
D--",,-_,
2340
•
2-LINE TO 1-LlNE MULTIPLEXERS
logic symbol
tpd (nsl
CELL NAME
Cl
...
o
."
MUll0lH
=0
pF
I
Cl
I
2.3
Cpd (pFI
= 1 pF
GZ
5
3.7
0.92
A
label: MUll0lH A,B,S,GZ,Y;
Co
Y
B
c:
(')
r+
C)
2341
c:
4-LlNE TO 1-LlNE MULTIPLEXERS
c:
(ogic symbol
CD
tpd (nsl
CELL NAME
Cl
MU210lH
=0
pF
2.1
Cpd (pFI
I
CL = 1 pF
I
2.9
A
B
1.28
MUX
label: MU210lH CO,C 1 ,C2,C3,A,B, Y;
co
Cl
C2
C3
0
V
2
1..3,;...._ _ _-,
2342
8-LlNE TO 1-LlNE MULTIPLEXERS WITH
3-STA TE OUTPUTS
logic symbol
tpd (nsl
CEll NAME
Cl
MU310lH
=0
3.2
pF
I
I
CL
=
Cpd (pFI
1 pF
4.7
1.68
label: MU310lH A.B,C.DO,Dl.D2.D3,D4.D5,D6,D7.GZ.Y;
3-36
MUX
GZ
EN
A
B
C
DO
D1
02
D3
04
05
06
07
O} G-0
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2
0
1
2
3
4
5
6
7
7
"
Y
PRODUCT GUIDE
2350
2-LlNE TO 4-LlNE DECODERS/DEMULTIPLEXERS
logic symbol
DE210LH
tpd (ns)
CELL NAME
I
CL;1pF
1.0
I
2.0
2.91
2.5
2.Bl
Label: DE210LH A,B,YO,Yl,Y2,Y3;
DE212LH
1.0
XIV
YO
YO
Cpd (pF)
CL;OpF
DE210LH
DE212LH
XIV
I
A
Yl
Yl A
2
B
Label: DE212LH A,B,G,YO,Yl,Y2,Y3;
Y2
B
2
Y2
Y3
G
EN
Y3
II
2370
400-J.lA PULL-UP ACTIVE TERMINATORS
logic symbol
CELL NAME: PR400LH
UP400l'A
• Provides active termination for inputs or I/0s
~TAP
....
Label: PR400LH TAP;
(J
:::J
"C
..o
2371
200-J.lA PULL-UP ACTIVE TERMINATORS
logic symbol
CELL NAME: PR250LH
D..
UP 200 I'A
~TAP
• Provides active termination Jor inputs or I/0s
Label:PR250LH TAP;
2372
95-J.lA PULL-UP ACTIVE TERMINATORS
logic symbol
CELL NAME: PR095LH
Iup
• Provides active termination for inputs or lIas
95
j4A~TAP
Label: PR095LH TAP;
2373
95-J.lA PULL-DOWN ACTIVE TERMINATORS
logic symbol
CELL NAME: PD095LH
DIIl951'A
• Provides active
terminatio~
~TAP
for inputs or II0s
Label: PD095LH TAP;
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-37
PRODUCT GUIDE
2374
5-/lA PULL-UP ACTIVE TERMINATORS
logic symbol
CELL NAME: PR005LH
UP5p.A
• Provides
activ~
termination for inputs or II0s
~TAP
Label: PR005LH TAP;
2401
4-BIT SHIFT REGISTERS
logic symbol
CELL NAME
fmax (MHz)
Cpd (pF)
R2401LH
59.6
10.30
CLRZ
CLK---i>
Label: R2401 LH CLRZ,SERIN,CLK,QA,QB,QC,QD;
::p
o
SERIN
10
Q.
QA
QB
c:
...
(')
QC
QD
C)
c:
~
2402
4-BIT SHIFT REGISTERS
CEll NAME
R2402lH
I
I
logic symbol
fmax (MHz)
59.6
I
I
Cpd (pF)
ClRZ
12.10
ClK
Label: R2402LH CLRZ,SERIN,CLK,QA,QAZ,QB;QBZ,QC,
QCZ,QD,QDZ;
-----(:>
SERIN
QA
QAZ
QB
QBZ
QC
QCZ
QD
QDZ
3-38
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
PRODUCT GUIDE
2403
4-BIT SHIFT REGISTERS
CEll NAME
R2403lH
label: R2403LH
OC,OD;
I
logic symbol
fmax (MHz)
I
59.6
I
I
Cpd (pF)
lZ_S
11.10
ClK
SERIN.LZ~S.CLK,A,B,C,D,OA,OB,
SERIN
2D
A
1D
B
1D
OA
QB
C
QC
D
QD
2404
Q)
4-BIT SHIFT REGISTERS
CELL NAME
R2404LH
I
I
III
logic symbol
fmax (MHz)
59.6
I
I
:2
:::I
(!)
Cpd (pF)
....
LZ_S
12.10
(.)
ClK
:::I
Label: R2404LH SERIN,LZ_S,CLK,A,B,C,D,OA,OAZ,
OB,OBZ,OC,OCZ,OD,ODZ;
SERIN
QA
A
QAZ
"C
0
C-
...
QB
B
QBZ
QC
C
QCZ
QD
D
QDZ
2405
4-BIT FLIP-FLOPS/REGISTERS
CEll NAME
R2405LH
I
I
fmax (MHz)
64,2
logic symbol
I
I
CLRZ
Cpd (pF)
ClK
10.20
Label: R2405LH CLRZ,D1 ,D2,D3,D4,CLK,01 ,02,03,04;
TEXAS
D1
Q1
D2
Q2
D3
03
D4
04
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-39
PRODUCT GUIDE
2406
4-BIT FLIP-FLOPS/REGISTERS
logic symbol
'ASC2406
CELL NAME
R2406LH
I
I
fmax (MHz)
64.2
I
CLRZ
Cpd (pF)
I
CLK
11.70
Label: R2406LH CLRZ,D1 ,D2,D3,D4,CLK,01,
01 Z,02,02Z, 03,03Z,04,04Z;
01
01
01Z
02
02
02Z
03
03
03Z
04
04
..
o
."
04Z
2407
4-BIT FLIP-FLOPS/REGISTERS
c.
r::
(")
logic symbol
'A!!C2407
CELL NAME
r+
R2407LH
Q
I
I
fmax (MHz)
36.3
I
CLRZ
G
Cpd (pF)
I
11.00
CLK
Label: R2407LH CLRZ,D1 ,D2,D3,D4,CLK,G,01 ,02,
03,04;
r::
is:
01
01
02
CD
02
03
03
04
04
2408
4-BIT RIPPLE COUNTERS
CELL NAME
R240BLH
I
I
logic symbol
fmax (MHz)
59.6
I
CTRDIV16
Cpd (pF)
I
7.22
Label: R240BLH CLRZ,A,OA,OB,OC,OD;
+
A
QA
cr{
CLRZ
08
OC
00
2500
CRYSTAL-CONTROLLED OSCILLATORS
logic symbol
CELL NAME
MAXIMUM FREOUENCY
Cpd (pF)
OSEOOLH
OSF02LH
OSE06LH
5 MHz
20 MHz
BOO MHz
B.13
15.30
6.B2
G
-.n.JL
XI
Y
XO
Label: OSE03LH RC, Y;
3-40
TEXAS
.J.i1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
PRODUCT GUIDE
2502
RC OSCILLATORS
CELL NAME
OSE03LH
logic symbol
I TYPICAL FREQUENCY RANGE I cpd (pF)
I
5 to 20 MHz
I
G
JUL
2.44
Y
RC
Label: OSE03LH RC, Y;
2503
DIFFERENTIAL COMPARATORS
logic symbol
CELL NAMES: C0212LH, C0213LH
o Single 5 volt supply with ± 10% tolerance
o Inputs are ESO-protected
o Input offset voltage--50 mV max
o Common mode input voltage: C0212LH - 0 V to 3.5 V
C0213LH - 1.5 V to VCC
Q)
INZ~ OUT
"'0
·S
IN
0
...
CJ
::s
P-CHANNEL Label: C0212LH IN,INZ,OUT;
N-CHANNEL Label: C0213LH IN,INZ,OUT;
"'0
0
...
~
2507
DYNAMIC DELAY ELEMENT
logic symbol
CELL NAME: OLE 1OLH
3 to 12 ns
Label: OLE10LH A,PV,NV,Y;
I
I
Y
A
PV
n
NV
] DELAY
ADJUST
2508
CONTROL ELEMENT FOR DYNAMIC DELAY
ELEMENT
logic symbol
CELL NAME: OLC10LH
Label: OLC10LH P,N,R,CAP,PV,NV;
R
P
N
n
n
PV
NV
CAP
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-41
PRODUCT GUIDE
2519
MEDIUM-DRIVE OPERATIONAL AMPLIFIER
logic symbol
CELL NAME: AMC12NH
•
•
•
•
•
IN~OUT
Single 5-volt supply ± 10%
Internally frequency~compensated
Inputs are ESD-protect~d
Input offset voltage -50 mV typical
Output voltage swing -1 V to 4.5 V
INZ~
Label: AMC12NH, IN,INZ,OUT;
2901
4-81T MICROPROCESSOR SLICE
.
."
oQ.
C
2.
C)
e
is.:
logic symbol
CELL NAME: M01 MPLH
•
•
•
Offers full system implementation on a single chip, when used
with other members of the 2900 family
Label: M01MPLH CLK,QEZ,CN,18 ... 10,83., .BO,A3 ... AO,
D3 ... DO,Q3,QO,RAM3,RAMO,GZ,PZ,F3,
FEQO,OVR,CNPL4,Y3 ... YO;
CD
4-BIT
MICROPROCESSOR
SLICE
'ASC2901
Reduces 2901 4-bit microprocessor to a single cell
ClK
CLK
OEZ
OE
CN
0
CN
10
11
12
13
14
INSTRUCTION
SELECT
15
00
16
17
18
8
AO
0
A1
wvl:
Q3
~vlO
RAMO
ADDRESS
3
RAM3
A2
A3
BO
0
B1
B2
83
3
DO
D1.
0
D2
D3
3-42
P
PZ
G
GZ
FEOOQ
F3
OVR
F3
3
3
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
$
Cn +4
0
r$
FEQO
OVR
CNPL4
YO
Y1
Y2
$v
3
Y3
PRODUCT GUIDE
2902
LOOK-AHEAD CARRY GENERATOR
logic symbol
CELL NAME: M02CGLH
4>
• Designed to accept up to four pairs of carry-propagate and carrygenerate signals, and a carry input
•
CARRY LOOK-AHEAO
GENERATOR
'ASC2902
Provides anticipated carries across four groups of binary ALUs
Label: M02CGLH CN,G3Z,P3Z,G2Z,P2Z,G1 Z,P1 Z,GOZ,PQZ,
CNPLX,CNPL y ,CNPLZ,GZ,PZ;
CN
GOZ
Cn
Cn + x
Cn + y
Cn + z
0
G1Z
1
G2Z
2
G3Z
3
POZ
0
CNPLX
CNPLY
CNPLl
G
G
GZ
PZ
P1Z
P
P2Z
2
P3Z
3
II
CD
"C
·S
e"
...
CJ
j
..
"C
0
a..
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
3-43
PRODUCT GUIDE
2904
STATUS AND SHIFT CONTROLLER
logic symbol
CELL NAME: M04SSLH
STATUS AND
SHIFT CONTROL
UNIT
• Generates the carry-in signal to the ALU and carry look-ahead
• Serves as interconnects for the data path, the auxiliary
operations, and the ALU status flags testing
• Offers full system implementation on a single chip, when used
with other members of the 2900 family
eLK
eLK
CEMZ
CEUZ
wl~
EZZ
Label: M04SSLH CLK,CEMZ,CEUZ,EZZ,ECZ,ENZ,EOVRZ,OEYZ,
OECTZ,SEZ,CX,IZ,IC,IN,IOVR,112 ... IO,YZ,YC,YN,
YOVR,SIOO,SION,QIOO,QION,CO,CT;
'ASC2904
ECZ
ENZ
wi:
EOVRZ
OEYZ
0100
OION
5100
SION
OEeTZ
~ul ~
SEZ
..."'tI
ex
ex
IZ
Q.
C
Ie
IZ
Ie
IN
IN
o
n
r+
G')
C
c:CD
OVA
IOVR
IOVR
I.
11
12
13
14
"16
INSTRUCTION
SELECT
17
18
"
110
111
112
3-44
TEXAS ."
INSTRUMENTS
POST OFfiCE BOX 655012 • DALLAS, TEXAS 75265
12
co
eT
V1
ve
VN
YOVR
co
eT
PRODUCT GUIDE
2910
MICROPROGRAM CONTROLLER
logic svmbol
CELL NAME: M10MCLH
•
..
Supports the function of an address sequencer in controlling the
execution of microinstructions stored in microprogram memory
MICROPROGRAM
CONTROLLER
'ASC2910
• Last-in, first-out stack provides for nine levels of nesting
microsubroutines
ClK
Label: M10MCLH CLK,CI,CCZ,CCENZ,RLDZ,OEZ,13 ... 10,
011 ... DO,FULLZ,PLZ,MAPZ,VECTZ,Y11 ... YO;
FULL
ClK
Pl
CI
FULLZ
PlZ
MAPZ
CCZ
VEeT
VECTZ
CCENZ
RLDZ
OEZ
10
0
11
0
Vl
INSTRUCTION
SELECT
12
VO
V2
13
V3
II
Q)
:s!
::J
0
V6
...
02
V7
::J
03
D4
VB
V4
DO-
I
0
01
V5
VDATA)
V9
~
05
06
07
Vl0
11
V11
(J
..
"C
0
~
08
09
010
011
11
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-45
PRODUCT GUIDE
3003
STATIC 16W X 16B READ/WRITE RAMs
WITH 3-STATE OUTPUTS
logic symbol
RA416LH
RAM 16 x 16
ORGANIZATION
CELL NAME
RA416LH
WORDS
16
I
I
AO
BITS
Al
16
A2
Label: RA416LH 00,01,02,03,04,05,06,07,08,09,
010,011 ,012,013,014,P15,AO,A l,A2,A3,
EZ,WZ,GZ,OO,O 1,02,03,04,05,06,07,08,
09,010,011,012,013,014,015,TIE;
A3
}~
15
3
TIE
EZ
WZ
GZ
DO
00
01
...
02
01
02
"tJ
03
03
o
04
04
C.
05
05
06
06
I:
(')
r+
07
07
08
08
09
09
3-46
TEXAS
010
011
010
012
012
013
013
014
014
015
015
'Ii1
INSTRUM~NTS
POST OFFICE
~ox
Qll
655012 • DALLAS, TEXAS 75265
PRODUCT GUIDE
3004
STATIC 64W X 88 READ/WRITE RAMs
WITH 3-STATE. OUTPUTS
logic symbol
RA608LH
ORGANIZATION
CELL NAME
RA608LH
WORDS
64
I
I
RAM64x8
BITS
AO
AI
8
A2
Label: RA608LH 00,01 ,02,03,04,05,06,07,AO,A 1,
A2,A3,A4,A5,EZ, WZ,GZ,OO,O 1,02,03,04,
05,06,07,TIE;
A3
A4
}~
TIE
A
EZ
WZ
GZ
DO
A,20
A.4Q
00
01
01
02
02
03
03
D4
04
05
05
06
06
07
07
Q)
::2
j
e"
...
CJ
j
"C
0
...
Q.
3005
STATIC 256W X 48 READ/WRITE RAMs
WITH 3-STATE OUTPUTS
logic symbol
RA804LH
RAM 256 x 4
ORGANIZATION
CELL NAME
RA804LH
WORDS
256
I
I
AO
BITS
AI
4
A2
Label: RA804LH 00,01 ,02,03,AO,A 1,A2,A3,A4,A5,
A6,A 7,EZ,WZ,GZ,00,01 ,02,03,TIE;
0
A3
A
A4
2~5
A5
A6
3
TIE
A.4Q
00
A7
EZ
WZ
GZ
DO
A,20
01
01
02
02
03
03
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-47
PRODUCT GUlDf
3006
STATIC 128W X 88 READ/WRITE RAMs
WITH 3-STATE OUTPUTS
logic sym
RA708lH
RAM 128 x 8
AO
ORGANIZATION
CEll NAME
RA708lH
WORDS
128
I
I
AI
BITS
A2
8
A3
label: RA708LH DO,Dl,D2,D3,D4,D5,D6,D7,AO,A 1,
A2,A3,A4,A5,A6,EZ, WZ,GZ,QO,Q 1,Q2,Q3,
Q4,Q5,Q6,Q7,TIE;
A4
A5
}.:,
3
TIE
A6
EZ
WZ
GZ
00
AAQ
QO
."
""I
01
02
Q2
Q.
03
Q3
o
c
n
P+
G')
c
D4
Q4
05
Q5
06
Q6
07
Q7
a:CD
3-48
Ql
TEXAS ~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
PRODUCT GUIDE
3010
CompilerCeWM
STATIC RANDOM ACCESS MEMORIES. (SRAM)
logic symbol
SRAM Array Limits
CEll NAME
PARAMETERS
AZRMLBt
Number of words
IW;o 2n)
Word length IB ~ iI
MIN MAX
COMMENTS
4
1024 Any even number
4
32 Number of data
inputs := number
of data outputs
Total number of
bits IWxB)
ROM [WxB)
4>
'ASC3010
AO
2
~
wordlength
W-1
An
16 16384
Label t : AZRMLB DO,Dl,D2 ... Di-l,AO, . . . An,CLK1,CLK2,
ENZ,R_WZ,OO, ... 0i-1:
AZ: Identifying symbol
LB: Wordlength in bits. Topology dependent
value.
M: Number of columns multiplied into one output. A ~ 1:1. B ~ 2:1, C ~ 4:1, D ~ 8:1Topology dependent value.
R: Number of rows. Topology dependent value.
ClK1
CLOCKS
ClK2
...
(,)
j
ENZ
..o
"'C
o
DO
Oi-1
RAM
IDAT~ IDAT~
i-1
Il..
o
00
i -1
Oi-1
3011
2-PHASE CLOCK GENERATOR WITH
COMPLEMENTARY OUTPUTS
logic syinbol
4>
CLOCK GEN
CELL NAME: CK4XOLH
•
ClK---'-"'t:>
Generates 2-phase clock for compiler cell functions
• Embedded function - requires no external connection
• Can be operated from single-phase of system on-chip clock
ClK1
ClK1Z
ClK2
ClK2Z
Label: CK4XOLH,CLK,CLK1,CLK1Z,CLK2,CLK2Z;
TEXAS
~
INSTRUMENTS
POST OFF!CE BOX 655012 • DALLAS, TEXAS 75265
3-49
PRODUCT GUIDE
3103
16-WORD BY a-BIT EDGE-TRIGGERED
3-PORT REGISTER FILES
logic symbol
CELL NAME: RF40BLH
REG FILE
16 X 8
• Full parallel access with one write and two read ports
• Typical access times:
Write-then-read cycle time - 11 ns
Address access time - 8 ns
Label: RF40BLH, CLK,WZ,WO,Wl,W2,W3,RAO,RA1.RA2,RA3,
RBO,RB1,RB2,RB3,DO,Dl,D2,D3,D4,D5,D6,D7,QAO,
QA1,QA2,QA3,QA4,QA5,QA6,QA 7,QBO,QB1,QB2,
QB3,QB4,QB5,QB6,QB7;
4>
RAO
'ASCJ10J
0
A
READ
ADDRESS
RAI
RA2
RAJ
RBO
0
B
READ
ADDRESS
RBI
RB2
RBJ
..."'0
CLK
o
WO
....
W2
c.
c
(')
G')
C
s:
CD
CLK
0
WI
WRITE
ADDRESS
WJ
WZ
WRITE ENABLE
o
QAO
QAl
QA2
QA3
QA4
DO
GA5
01
\lAS
D2
QA7
OJ
04
o
QAO
05
QAl
06
QA2
07
QAJ
QA4
QA5
QAS
QA7
3-50
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
PRODUCT GUIDE
3200
CompilerCeWM
READ-ONLY MEMORIES (ROM)
logic symbol
Single Array Parameter Limits
PARAMETERS
MIN
Number of words
IW", 2 n l
Word length IB ~ il
MAX
2048
8
4
32
.
ROM [W x B[
COMMENTS
Must be multiples of 4
Even or odd
Total number of
bits IW x BI
512
16384
Number of words
IW", 2 n l
Word length IB ~ il
Total number of
bits IW x BI
MIN
8
4
512
O}
An
n
CLK1
I
CLK2
Double Array Parameter Limits
PARAMETERS
AO
4096
64
COMMENTS
A W - 1
CLOCKS
CLK2Z
MAX
'A~C3200
EN
Must be multiples of 4
II
MEM ENABLE
POWER DOWN
Must be even
0
65536
00
Label: Label and cell name are developed as a function of
IDATV
cell design.
i -1
...
Qi-1
CJ
:::l
..o
"'C
3430
D.
CompilerCel[TM
PIPELINE TEST REGISTERS (PTR)
logic symbol
Typical Modes of Operation:
+
n-BIT PIPELINE TEST REGISTER
'ASC3430
• Pseudo-Random pattern generation
• Signature analysis
• Circular shift
S1
I
I
PLD
PlO
elK1
• Local hold
• Serial or parallel load
CLK2
Label: Label and cell name are developed as a function of cell design.
80
81
CLOCKS
H
H
SO
l
H
l
H
MODE
HOLD
LOAD/HOLD
SHIFT
TEST
SUB-MODES IN MODE 3
PLD SUB-MODE
H PAR LOAD
l LOCAL HOLD
MODE
SUB-MODES IN MODE 4
BO
B1
DO
00
01
0
01
On
0
On
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS. TEXAS 75265
3-51
PRODUCT GUIDE
3800
CompilerCell™
PROGRAMMABLE LOGIC ARRAYS (PLA)
logic symbol
Maximum Parameter Values
INPUTS
I
PRODUCT TERM
I
OUTPUTS
m
I
p
128
I
n
32
64
AND
MATRIX
INPUT
BUFFERS
I>
INO
m
8<
2m X p
OR
MATRIX
OUTO
OUT1
Label: Label and cell narne are developed as a function of
cell design.
OUTn-1
OUTn
II...
""0
o
C.
I:
2
4002
C)
I:
4-INPUT POSITIVE-NOR
a:
~ATES
logic symbol
tpd (nsl
CD
CELL NAME
Cpd (pFI
CL = 0 pF
CL = 1 pF
1.4
1.2
4.1
2:6
N0410LH
N0420LH
0.35
0.55
Label: N04nOLH A,B,C,D,Y;
4072
4-INPUT POSITIVE-OR GATES
logic symbol
tpd (nsl
CELL NAME
CL
OR410LH
OR420LH
OR440LH
OR460LH
=0
pF
2.2
2.6
2.4
2.4
CL
= 1 pF
3.1
3.1
2.7
2.7
Cpd (pFI
0.92
1.83
3.46
5.48
Label: OR4nOLH A,B,C',D,Y;
3-52
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
PRODUCT GUIDE
4075
3-INPUT POSITIVE-OR GATES
logic symbol
tpd Insl
CELL NAME
Cpd IpFI
CL = 0 pF
CL = 1 pF
1.8
2.2
1.9
2.0
2.7
2.7
2.2
2.2
OR310LH
OR320LH
OR340LH
OR360LH
0.90
1.71
3.51
5.36
Label: OR3nOLH A,B,C,Y;
4078
8-INPUT POSITIVE-NOR GATES
II
logic symbol
Q)
tpd Insl
CELL NAME
Cpd IpFI
"'C
1.54
0.65
C'J
'S
CL = 0 pF 1CL=1PF
N0810LH
NOB20LH
I
2.6
2.3
3.4
4.9
...
(.)
Label: NOBnOLH A,B,C,D,E,F,G,H,Y;
j
..
"'C
o
5000
0..
CMOS-COMPATIBLE INVERTING INPUT BUFFERS
logic symbol
A~Y
tpd Ins I
CELL NAME
Cpd IpFI
CL = 0 pF
CL = 1 pF
0.7
0.7
1.1
1.1
IPEOOLH
IPFOOLH
2.00
2.00
Label: IPFOOLH A,Y; .
5001
TTL-COMPATIBLE INVERTING INPUT BUFFERS
logic symbol
tpd Insl
CELL NAME
Cpd IpFI
CL = 0 pF
CL = 1 pF
0.9
0.9
2.1
2.1
IPE03LH
IPF03LH
16.5
16.5
Label: IPF03LH A,Y;
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
3-53
PRODUCT GUIDE
5002
CMOS-COMPATIBLE INVERTING
SCHMITT-TRIGGER INPUT BUFFERS
logic symbol
TAP~~
Ipd (nsl
CELL NAME
IPEOSLH
IPFOSLH
A-----V- Y
Cpd (pFI
CL = 0 pF
CL = 1 pF
2.B
2.B
4.B
4.B
1.30
1.30
Label: IPFOSLH A,TAP,Y;
II
5003
TTL-COMPATIBLE INVERTING SCHMITT-TRIGGER
INPUT BUFFERS WITH PULL-UP TAP
."
o
TAP
Ipd (nsl
CELL NAME
C.
C
IPEOBLH
IPFOBLH
~
CL = 0 pF
CL = 1 pF
3.7
4.3
7.5
B.l
l
........ "-
A~Y
Cpd (pFI
19.00
19.00
Label: IPEOBLH A,TAP,Y;
G)
C
s:
CD
logic symbol
5004
CMOS-COMPATIBLE INVERTING INPUT BUFFERS
WITH PULL-UP TAP
logic symbol
CL=OpF
IPF02LH
I
TAP:--l
Cpd (pFI
CL = 1 pF
I
0.7
1.0
2.00
Label: IPF02LH 'A,TAP,Y;
5005
TTL-COMPATIBLE INVERTING INPUT BUFFERS
WITH PULL-UP TAP
logic symbol
Ipd (nsl
CELL NAME
IPE05LH
IPF05LH
Cpd (pFI
CL = 0 pF
CL = 1 pF
0.9
0.9
2.1
2.1
IS.00
16.00
Label: IPF05LH A,TAP,Y;
3-54
~
A-v-- Y
Ipd (nsl
CELL NAME
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
..
PRODUCT GUIDE
5006
CMOS-COMPATIBLE NONINVERTING
INPUT BUFFERS
logic symbol
A--[>----V
tpd Ins)
CELL NAME
Cpd IpFI
CL = 0 pF
CL = 1 pF
1.7
0.7
1.9
1.1
IPE01LH
IPF01LH
3.00
3.00
Label: IPF01LH A,V;
5007
TTL-COMPATIBLE NONINVERTING
INPUT BUFFERS
logic symbol
A--[>----V
tpd Ins)
CELL NAME
Cpd IpF)
CL = 0 pF
CL = 1 pF
1.8
1.8
2.1
2.1
IPE04LH
IPF04Lt-f
...
18.00
18.00
U
Label: IPF04LH A, V;
1.6
1.4
IPF12LH
II
::::I
"'0
...o
18.00
a.
Label: IPF 12LH A, V;
5010
TTL-COMPATIBLE INVERTING SCHMITT-TRIGGER
INPUT BUFFERS WITH PULL-UP TAP
logic symbol
tpd Ins)
CELL NAME
IPE10LH
IPF10LH
Cpd IpF)
CL = 0 pF
CL = 1 pF
3.7
3.7
7.5
7.5
20.00
20.00
Label: IPF10LH A,TAP,V;
5013
TTL-COMPATIBLE NON INVERTING BUFFERS
WITH PULL-UP TAP
logic symbol
TAP~~_
tpd Ins)
CELL NAME
IPF13LH
A~Y
Cpd IpF)
CL = 0 pF
I
CL=lpF
1.8
1
2.1
18.00
Label: IPF13LH A,TAP,V;
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 16265
3-55
PRODUCT GUIDE
5100
TTL-/CMOS-COMPATIBLE OUTPUT BUFFERS
"
tpd (nsl
CE~L
NAME
Cpd (pFI
CL = 15 pF
CL=50pF
2.7
2.7
4.7
4.7
OPE40LH
OPF40LH
logic svmbol
A-t>-V
9.10
10.90
Label: OPF40LH A,V;
5103
TTL-/CMOS-COMPATIBLE OUTPUT BUFFERS
logic symbol
A---[>--V
tpd (nsl
".
CELL NAME
o
Cpd (pFI
CL = 15 pF
CL=50pF
2.4
2.4
3.5
3.5
OPE60LH
OPF60LH
Co
C
...
15.50
17.30
Label: OPF60LH A,V;
()
~ 5104
s:
CD
TTL-/CMOS-COMPATIBLE 3-STATE
OUTPUT BUFFERS
logic symbol
'y'
tpd (nsl
CELL NAME
Cpd (pFI
CL = 15 pF
CL=50pF
2.7
2.7
4.0
4.0
OPE63LH
OPF63LH
17.10
19.40
GZ
Label: OPF63LH A,GZ,V;
.
5105
TTL-/CMOS-COMPATIBLE OPEN-DRAIN
OUTPUT BUFFERS
logic symbol
A---[>--V
tpd (nsl
CELL NAME
Cpd (pFI
CL = 15 pF
CL=50pF
2.0
2.0
4.0
4.0
OPE61LH
OPF61LH
3.80
4.00
Label: OPF61LH A,V;
3-56
TEXAS ."
INSfRUMENTS
POST OFFICE BOX· 655012 • DALLAS, TeXAS 75265
PRODUCT GUIDE
5106
TTL-/CMOS-COMPATIBLE OUTPUT BUFFERS
logic symbol
tpd (nsl
CELL NAME
Cpd (pFI
CL = 15 pF
CL=50pF
2.0
2.0
2.8
2.8
OPEOOLH
OPFOOLH
A-{>-V
21.80
20.10
label: OPFOOLH A,V;
5107
TTL-/CMOS-COMPATIBLE 3-STATE
OUTPUT BUFFERS
logic symbol
tpd (nsl
A---f>-V
CELL NAME
Cpd (pFI
CL = 15 pF
CL=50pF
2.7
2.7
3.7
3.7
OPE03LH
OPF03LH
GZ
19.90
23.20
II
---.-11
label: OPF03LH A,GZ,V;
5108
TTL-/CMOS-COMPATIBLE OPEN-DRAIN OUTPUT
BUFFERS
logic symbol
tpd (ns)
CELL NAME
A--t>--V
Cpd (pFI
CL = 15 pF
CL=50pF
1.7
1.7
3.0
3.0
OPE01LH
OPF01LH
5.60
5.80
label: OPF01LH A,V;
5109
TTL-/CMOS-COMPATIBLE OPEN-DRAIN OUTPUT
BUFFERS
logic symbol
tpd (nsl
CELL NAME
A--t>--V
Cpd (pFI
CL = 15 pF
OPE41LH
OPF41LH
2.7
2.7
CL=50pF
6.0
. 6.0
2.40
2.60
label: OPF41LH A,V;
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
3-57
PRODUCT GUIDE
5110
TTL-/CMOS-COMPATIBLE NON INVERTING
, 3-STATE.OUTPUT BUFFERS
logic symbol
tpd (ns)
CELL NAME
Cpd (pF)
CL = 15 pF
CL=50pF
3.4
3.4
6.2
6.2
OPE42LH
OPF42LH
8.6
10.5
Label: OPF42LH A,G,Y;
II
..
5111
TTL-/CMOS-COMPATIBLE 3-STATE OUTPUT
BUFFERS
."
A--f>--V
' tpd (ns)
(;
CELL NAME
C.
C
Cpd (pF)
CL = 15 pF
CL=50pF
3,5.
3.5
5,7
5.7
OPE43LH
OPF43LH
C")
GZ~
10.30
10.90
Label: OPF43LH A,GZ,Y;
C)
C
s:
CD
logic symbol
5120
TTL-/CMOS-COMPATIBLE OUTPUT BUFFERS
logic symbol
tpd (ns)
CELL NAME
CL = 15 pF
OPFBOLH
I CL = 50 pF
I
1.7
2.2
A-{>-Y
Cpd (pF)
32,80
Label: OPFBOLH A,Y;
5121
TTL-/CMOS-COMPATIBLE OPEN-DRAIN OUTPUT
BUFFERS
logic symbol
A---[>---V
tpd (ns)
CELL NAME
CL = 15 pF
OPFD1LH
1.7
I CL = 50 pF
I
2.2
Cpd (pF)
10.40
Label: OPFD1LH A,Y;
3-58
TEXAS
-II
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
PRODUCT GUIDE
5123
TTL-/CMOS-COMPATIBLE OPEN-DRAIN OUTPUT
BUFFERS
logic symbol
A-£>--V
tpd (ns)
CELL NAME
Cpd (pF)
CL = 15 pF
OPFE1LH
I CL = 50 pF
I
1.5
16.20
1.9
Label: OPFE1LH A,V;
5124
TTL-/CMOS-COMPATIBLE 3-STATE OUTPUT
BUFFE;RS
A---f>--V
tpd (ns)
CELL NAME
Cpd (pF)
CL = 15 pF
OPFD3LH
GZ~
ICL=50PF
I
2.5
3.0
•
logic symbol
49.00
...
Label: OPFD3LH A,GZ,V;
U
::::J
..o
5125
"0
TTL-/CMOS-COMPATIBLE 3-STATE OUTPUT
BUFFERS
logic symbol
a..
A---f>--V
tpd (ns)
CELL NAME
Cpd (pF)
CL = 15 pF
OPFB3LH
I
2.8
GZ~
I CL = 50 pF
3.7
29.00
Label: OPFB3LH A,GZ,V;
5200
3-STATE 1/0 BUFFER WITH INVERTING CMOS
INPUT AND CMOSITTL OUtPUT .
logic symbol
tpd (ns)
CELL NAME
IOE40LH
IOF40LH
A
Cpd (pF)
CL = 15 pF
CL=50pF
3.:':\
3.3
5.9
5.9
GZ---...J
12.50
12.70
Vl
V2
Label: IOF40LH A,GZ,V2,V1;
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TeXAS 76266
3-59
PRODUCT GUIDE
5201
3-STATE I/O BUFFER WITH INVERTING
TTL INPUT AND CMOSITTL OUTPUT
logic symbol
tpd Ins I
CELL NAME
IOE43LH
IOF43LH
Cpd (pFI
CL = 15 pF
CL=50pF
3.5
3.5
5.8
5.8
A;tr-Y1
GZ
13.20
13.40
Y2
Label: IOF43LH A,GZ,Y2,Yl;
•
5202
3-STATE 1/0 BUFFERS WITH INVERTING CMOS
INPUT AND CMOSITTL OUTPUT
logic symbol
TAP
tpd (nsl
CELL NAME
CL = 15 pF
IOF47LH
I CL = 50 pF
I
3.6
6.8
Cpd (pFI
A
13.10
Label: IOF47LH A,GZ,TAP,Y2,Yl;
GZ--_..J
Ci)
",--Yl
C
c:
CD
Y2--"'""C~
5203
3-STATE 1/0 BUFFERS WITH INVERTING TTL
INPUT AND CMOSITTL OUTPUT
logic symbol
A
tpd (nsl
CELL NAME
CL = 15 pF
IOF48LH
I CL = 50 pF
I
3.3
3.5
Cpd (pFI
GZ--_..J
. Yl
14.90
Y2
Label: IOF48LH A,GZ,Y2,Yl;
5206
3-STATE 1/0 BUFFER WITH NON INVERTING
CMOS INPUT AND CMOSITTL OUTPUT
logic symbol
tpd (risl
CELL NAME
IOE41LH
IOF41LH
A
Cpd (pFI
CL = 15 pF
CL=50pF
3.3
3.3
5.5
5.5
16.70
14.30
GZ--_..J
Y2
Label: IOF41LH A,GZ,Y2,Yl;
3-60
TEXAS . "
INSTRUMENTS
post OFFICE BOX 665012 • DALI.AS, TeXAS 76266
Yl
PRODUCT GUIDE
5207
3-STATE 1/0 BUFFER WITH NONINVERTING
TTL INPUT AND CMOSITTL OUTPUT
logic symbol
A;tt-"
tpd Ins)
CELL NAME
IOE44LH
IOF44LH
Cpd IpF)
CL = 15 pF
CL=50pF
3.5
3.5
5.8
5.8
14.50
14.30
GZ
Y2
Label: IOF44LH A.GZ.Y2.Yl;
5217
3-STATE 1/0 BUFFER WITH NONINVERTING
TTL INPUT AND CMOSITTL OUTPUT
logic symbol
A;tJ-"
tpd Ins)
CELL NAME
CL = 15 pF
IOF64LH
I CL = 50 pF
I
2.7
4.1
Cpd IpF)
GZ
22.40
Y2
Label: IOF64LH A.GZ.Y2.Yl;
II
CD
:2
::::I
~
...
(,)
::::I
"C
...
5220
0
3-STATE 1/0 BUFFER WITH INVERTING
CMOS INPUT AND CMOSITTL OUTPUT
tpd Ins)
A
CELL NAME
IOEOOLH
IOFOOLH
Q.
logic symbol
Cpd IpF)
CL = 15 pF
CL=50pF
2.9
2.9
3.8
3.8
GZ
31.40
25.80
Yl
Y2
Label: IOFOOLH A,GZ,Y2,Yl;
5221
3-STATE 1/0 BUFFER WITH INVERTING
TTL INPUT AND CMOSITTL OUTPUT
logic symbol
tpd Ins)
CELL NAME
CL = 15 pF
IOF03LH
2.7
I CL = 50 pF
I
3.8
Cpd IpF)
A;tJ-Vl
GZ
24.40
V2
Label: IOF03LH A,GZ,Y2,Yl;
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-61
PRODUCT GUIDE
5226
3-STATE I/O BUFFER WITI-4 NONINVE~TING
CMOS INPUT AND CMOSITTL OUTPUT
logic symbol
A~V1
tpd(nsl
CELL NAME
CL = 15 pF
IOF01LH
I CL
I
2.7
Cpd IpFI
= 50 pF
GZ
26.60
3.B
V2
Label: IOF01LH A,GZ,V2,Vl;
5227
3-STATE I/O BUFFE~ WITH NONINVERTING
TTL INPUT AND CMOS/TTL OUTPUT
.
tpd Insl
."
CELL NAME
o
c.
c
IOF04LH
CL = 15 pF
g>
I CL = 50 pF
I
2.7
Cpd IpFI
AtJ-Vl'
GZ
25.70
3.B
V2
Label: IOF04LH A,GZ,V2;Vl;
~
a:CD
logic symbol
5239
3-STATE I/O BUFFER WITH NONIIIIVERTING
TTL INPUT AND CMOS/TTL OUTPUT
logic symbol
A~V1
tpd Insl
CELL NAME
CL = 15 pF
IOFBBLH
I CL
I
2.7
Cpd IpFI
= 50 pF
3.7
GZ
2B.20
V2
Label: IOFBBLH A,GZ,V2,Vl;
5246
3-STATE I/O BUFFER WITH INVERTING
TTL INPUT AND TTL/CMOS OUTPUT
logic symbol
A
tpd Insl
CELL NAME
CL
IOFDBLH
= 15 pF
2.5
Label: IOFDBLH A,GZ,V2,Vl;
3-62
I CL = 50 pF
I
3.0
Cpd IpFI
V1
50.BO
GZ----'
Y2--'""-'!C
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
PRODUCT GUIDE
5250
OPEN-DRAIN 1/0 BUFFER WITH INVERTING
CMOS INPUT AND CMOSITTL OUTPUT
logic symbol
tpd Ins)
CELL NAME
CL = 15 pF
IOFOOLH
1 CL = 50 pF
I
1.7
2.3
Cpd IpF)
A
---i>--}
Yl
Y2~
11.60
Label: IOFOOLH A, Y2, Y 1;
6002
AND-NOR GATES, Y = A1 +(B1-B2-B3)
logic symbol
tpd Ins)
CELL NAME
CL=OpF
BF002LH
1 CL=1pF
I
1.1
2.7
Cpd IpF)
0.42
Bl3b>-
II
B2
!~
y
CD
"0
'3
Label: BF002LH A 1 ,B1 ,B2,B3,Y;
CJ
~
CJ
::::s
6003
AND-NOR GATES. Y
(A1-A2) + (B1-B2)
logic symbol
"0
2
a.
tpd Ins)
CELL NAME
CL=OpF
BF003LH
T CL=1pF
1
1.1
2.6
Cpd IpF)
0.51
Label: BF003LH A1,A2,B1,B2,Y;
6004
AND-NOR GATES. Y
(A1-A2) + (B1-B2-B3)
tpd Ins)
CELL NAME
CL=OpF
BF004LH
1.2
I CL=1pF
-r
Label: BF004LH A1,A2,B1,B2,B3,Y;
2.B
Cpd IpF)
0.53
logic symbol
~~,
Al
A2
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
3-63
PRODUCT GUIDE
6005
AND-NOR GATES,
Y = (A1 o A2 o A3)+(B1 o B2 o B3)
logic symbol
tpd (n5)
CELL NAME
BF005LH
Cpd (pI')
CL = 0 pF
I
CL = 1 pF
1.4
I
3.0
0.64
Label: BF005LH A l,A2,A3,B l,B2,B3, Y;
6006
II...
AND-NOR GATES,Y = A1 +A2+(B1 o B2)
logic symbol
tpd (ns)
CELL NAME
"0
o
BF006LH
Co
C
Cpd (pF),
CL = 0 pF
I
CL = 1 pF
1.3
I
3.2
81
0.36
B2
~
Label: BF006LH A 1,A2,B1,B2,Y;
....
c.:
CD
.
A2
(')
G)
C
Al
6007
AND-NOR GATES, Y = A1 +A2+(B1 o B2 o B3)
logic symbol
tpd (n5)
CELL NAME
CL = 0 pF
BF007LH
I
I
1.5
Al------,
~----J ~,
Cpd (pF)
CL = 1 pF
3.7
0.36
Label: BF007LH A 1,A2,B1,B2,B3,Y;
A2-.,..-------'
6008
AND-NOR GATES, Y = A1 +(B1 o B2)+(C1 o C2)
logic symbol
tpd (ns)
CELL NAME
CL = 0 pF
BFOOBLH
1.4
I CL=lpF
I
3.4
Cpd (pF)
0.44
Label: BF008LH A1,B1,B2,C1,C2,Y;
3-64
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
Y
PRODUCT GUIDE
6009
AND-NOR GATES. Y = A1+(B1-B2)+(C1-C2-C3)
logic symbol
tpd (ns)
CELL NAME
CL=OpF
BF009LH
T CL=lpF
I
1.6
3.7
Cpd (pFI
0.45
Label: BF009LH A 1.B1.B2.C1.C2.C3.Y;
6012
AND-NOR GATES.
Y= (A1-A2)+(B1-B2)+(C1-C2-C3)
logic symbol
Al
tpd (nsl
CELL NAME
CL=OpF
BF012LH
I
A2
0.56
Cl
C2
C3
CL=lpF
1
1.7
Cpd (pFI
3.7
Label: BF012LH A 1.A2.B1.B2.C1.C2.C3.Y;
CD
"C
Y
Bl
·S
e,:,
...
U
:::J
.
B2
6013
•
"C
0
Q.
logic symbol
AND-NOR GATES.
Y = (A1-A2)+(B1-B2-B3)+(C1-C2-C3)
Bl
B2
83
tpd (nsl
CELL NAME
BF013LH
Cpd (pFI
CL=OpF
I
CL = 1 pF
1.9
1
4.1
Cl
C2
C3
0.57
Label: BF013LH A 1.A2.B1.B2.B3.C1.C2.C3.Y;
Y
Al
A2
TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-65
PRODUCT GUIDE
6014
AND-NOR GATES,
V = (A1-A2-A3)+(B1-B2-B3)+(C1-C2-C3)
tpd Ins)
CELL NAME
BF014LH
Cpd IpF)
CL=OpF
I
CL=lpF
2.1
I
4.3
0.71
Label: BF014LH A'l ,A2,A3,Bl ,B2,B3,Cl ,C2,C3, Y;
logic symbol
A l - - . - -....
A2
A3----o.._'
B l - - - - r - -...
B2
B3----o.._'
Y
C l - - - - r - -...
C2
C 3 - -......_ ,
6017
...
o
AND-NOR GATES, V = A1 +(B1-B2)
• logic symbol
."
tpd Ins)
c..
CELL NAME
c
...n
BF001LH
C)
c
is:
CD
Cpd IpF)
CL=OpF
I
CL=1pF
1.0
I
2.5
:~--~-')~-~-,
A1
~Y
0.38
Label: BF001LH Al,Bl,B2,Y;
6018
AND-NOR GATES,
Y = A1 +(B1-B2-B3)+(C1-C2-C3)
logic symbol
tpd Ins)
CELL NAME
BF010LH
Cpd IpF)
CL=OpF
I
CL=lpF
1.7
I
3.9
0.45
Label: BF010LH A 1,Bl ,B2,B3,Cl ,C2,C3,Y;
ij--__~,
A1 - - - - - - .....
6019
AND-NOR GATES,
V = (A1-A2)+(B1-B2)+(C1-C2)
logic symbol
Al
tpd Ins)
CELL NAME
BF011LH
Cpd IpF)
CL=OpF
I
CL=lpF
1.5
I
3.5
Label: BF01 1LH Al,A2,Bl,B2,Cl,C2,Y;
0.52
A2
B1
Y
B2
C1
C2
3-66
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
PRODUCT GUIDE
6022
OR-AND-NOR GATES.
V = A1-A2+[B1-B2-(C1 +C2)]
logic symbol
Cl--...z--....
tpd (ns)
CELL NAME
BF022LH
Cpd (pF)
CL=OpF
I
CL=lpF
1.7
I
3.9
0.54
C2---...._~
B1-------I
B2------~~~
Label: BF022LH Al,A2,Bl,B2,Cl,C2,Y;
Y
A1------~r_~
6023
OR-AND-NOR GATES. V
= A1 +[B1-(C1 +C2))
logic symbol
II
CI)
"C
tpd (ns)
BF015LH
'S
Cpd (pF)
CELL NAME
CL = 0 pF
I
CL = 1 pF
1.3
I
3.2
CJ
...
0.36
()
Label: BF015LH Al,Bl,Cl,C2,Y;
;:,
"C
...o
6024
D..
OR-AND-NOR GATES.
V = A1 +[(B1 +B2)-(C1 +C2))
logic symbol
tpd (ns)
Cpd (pF)
CELL NAME
CL=OpF
BF016LH
ICL=1PF
I
1.4
3.4
0.42
Label: BF016LH Al,Bl,B2,Cl,C2,Y;
6025
OR-AND-NORGATES.
V = A1-A2-A3+[B1-(C1 +C2))
logic symbol
tpd Ins)
CELL NAME
BF025LH
Cpd (pF)
Cl=OpF
I
CL=1pF
1.5
I
3.5
0.64
Label: BF025LH A l,A2,A3,Bl ,Cl ,C2,Y;
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-67
PRODUCT GUIDE
6026
OR-ANO-NOR .GATES,
y = A1 +[B1.B2·(C1 +C2)]
logic symbol
81
tpd Insl
CELL NAME
Cl
BF017LH
=0
pF
I Cl = 1 pF
I
1.5
~~~82~·r--L?-
Cpd IpFI
3.7
0.40
y
A1----------------__-J.
Label: BF017LH A1,B1,B2,C1,C2,Y;
6027
OR-ANO-NOR GATES,
logic symbol
y= A1·A2·A3+[B1·B2·(C1 +C2)]
•
tpd Insl
....""0
CELL NAME
Co
BF027LH
o
CL
...c:
=0
pF
J
Cl
J
1.8
=
Cpd IpFI
1 pF
3.6
0.98
Y
B1---------------;--,
B2------------~
Label: BF027LH A 1 ,A2,A3,B1 ,B2,C1 ,C2,Y;
(')
A1----_r_-....
A2
A3--,--_
G)
C1
C2
c:
c:
CD
6028
OR-ANO-NOR GATES,
Y = A1.A2·A3+[B1.(C1 +C2)·(01 +02)]
logic symbol
D1
tpd Insl
CEll NAME
CL
BF028LH
=0
pF
I
Cl
.I
1.9
=
Cpd IpFI
1 pF
1.11
3.6
D2
B1
C1
Label: BF028LH A 1,A2,A3,B 1 ,C 1,C2,D1 ,D2,Y;
C2
A1
A2
A3
Y
6029
OR-ANO-NOR GATES,
y.= A1.A2+[B1-(C1 +C2)]
logic symbol
tpd Ins I
CELL NAME
Cl
BF020LH
=0
1.4
pF
I
CL
1
=
Cpd IpFI
1 pF
3.4
0.47
Label: BF020LH A 1,A2,B1 ,C1 ,C2,Y;
3-68
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
PRODUCT GUIDE
6032
ANO-OR-ANO-NOR GATES,
Y = A1+{B1 o [C1+(01 0 02)J}
logic symbol
01
tpd Ins)
CELL NAME
CL
BF030LH
~
0 pF
T CL ~ 1 pF
I
1.7
Cpd IpF)
02
0.80
C1
3.9
Label: BF030LH A1,B1,C1,01,02,Y;
B1
Y
A1
II
6034
ANO-OR-ANO-NOR GATES,
Y = (A1 oA2)+ {B1 o [C1 +(01 0 02)J)
logic symbol
CD
"C
01
·S
tpd Ins)
CELL NAME
CL
BF034LH
~
0 pF
1.7
I
1
Cpd IpF)
CL
~
1 pF
02
~
...
C1
3.6
0.86
(,)
B1
y
Label: BF034LH A1,A2,B1,Cl,01,02,Y;
Al
A2
::::J
..
"C
0
Q.
6035
ANO-OR-ANO-NOR GATES,
Y = (A1 oA2)+{B1 o[(C1 oC2)+(01 0 02)1)
logic symbol
tpd Ins)
CELL NAME
CL~OpF
BF035LH
1.7
I
1
02
Cpd IpF)
CL
~
1 pF
3.3
0.96
01
C2
C1
B1
Label: BF035LH A 1,A2,B1 ,C1 ,C2,01 ,02,Y;
y
A2
A1
6048
OR-NANO GATES, Y = A1o(B1 +B2)
logic symbol
tpd Ins)
CELL NAME
CL
BF051LH
~
0 pF
1.0
I CL .1 pF
T 2.4
B1~
Cpd IpF)
~
B2
0.57
Al
Y
Label: BF051LH Al,B1,B2,Y;
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-69
PRODUCT GUIDE
6049
OR-NAND GATES.
V = A1-IB1 +B2+B3)-IC1 +C2+C3)
logic symbol
81-..J"-....
B2
tpd (nsl
CELL NAME
CL=OpF
BF060LH
1.7
I
r
83,-,""",-_"
C1-..J"-....
C2
C3;-,""",-_"
Cpd (pFI
CL=1pF
3.B
0.65
Label: BF060LH A1.Bi,B2,B3,C1,C2,C3,Y;
v
A1--------'
6052
OR-NAND GATES. V = A1-IB1 +B2+B3)
logic symbol
tpd (nsl
-a
CELL NAME
c
()
Label: BF052LH A1,B1,B2,B3,V;
ac.
BF052LH
Cpd (pFI
CL=OpF
CL=1pF
1.2
3.2
0.57
r+
C)
c
r!
6053
OR-NAND GATES. V = IA1 +A2)-(B1 +B2)
logic symbol
CD
A1
tpd (nsl
CELL NAME
BF053LH
Cpd (pFI
CL=OpF
I
CL=1pF
1.1
I
2.6
A2 -
........
B1
Label: BF053LH A1,A2,B1,B2,V;
82----..__"
6054
OR-NAND GATES. V = IA1 +A2)-IB1 +B2+B3)
logic symbol
tpd (nsl
CELL NAME
Cpd (pFI
cL=oPFl CL = 1 pF
BF054LH
1.2
I
3.0
0.47
Label:,BF054LH A1,A2,B1,B2,B3,Y;
3-70
_"
~--V
0.49
,TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 866012 • DALLAS. TEXAS 75265
PRODUCT GUIDE
6055
OR-NAND GATES.
Y =(A1 +A2+A3).(B1 +B2+B3)
logic symbol
tpd Ins)
CELL NAME
Cpd IpF)
CL=OPFT CL = 1 pF
BF055LH
I
1.3
3.3
0.51
Label: BF055LH A l,A2,A3,B1.B2,B3,Y;
6056
OR-NAND GATES. Y = A1·A2·(B1+B2)
•
logic symbol
tpd Ins)
CELL NAME
CL = 0 pF
BF056LH
T CL =
I
1.2
Cpd IpF)
1 pF
2.9
0.55
Label: BF056LH Al,A2,Bl,B2,Y;
+'
CJ
j
6057
"CI
OR-NAND GATES. Y = A1.A2.(B1 +B2+B3)
~~
A2-~--- ,
tpd Ins),
CELL NAME
CL=OpF
BF057LH
I
Cpd IpF)
CL = 1 pF
1
1.5
3.7
...o
c..
logic symbol
.
0.58
Label: BF057LH A1,A2,Bl,B2,B3,Y;
6058
OR-NAND GATES. Y = A1.(B1 +B2).(C1 +C2)
logic symbol
B1
tpd Ins)
CELL NAME
CL=OpF
BF058LH
1.3
I
-r
B2
Cpd IpF)
CL = 1 pF
3.0
A1-------I
0.64
FI--Y
C1
C2
Label: BF058LH Al,B1,B2,Cl,C2,Y;
TEXAS
..II
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TeXAS 75265
3-71
PRODUCT GUIDE
6059
OR-NAND GATES, Y
= A1-(B1+B2)-(C1+C2+C3)
tpd (ns)
CELL NAME
CL=OpF
BF059LH
I
1.6
Cpd (pF)
I CL=1pF
logic symbol
C1
C2
C3
B1
3.5
0.65
Y
B2
Label: BF059LH A1,B1,B2,C1.C2,C3,Y;
A1
6062
•
OR-NAND GATES,
Y = (A1 +A2)-(B1 +B2)-(C1 +C2+C3)
logic symbol
tpd (ns)
."
CELL NAME
o
Q.
BF062LH
C
Cpd (pF)
CL=OpF
I
CL=1pF
1.9
I
4.1
A1
0.65
Label: BF062LH A1,A2,B1,B2,C1,C2,C3,Y;
(')
r+
C1
C2
C3
y
A2
B1
B2
G')
C
c:CD
6063
OR-NAND GATES,
Y = (A1 +A2)-(B1 +B2+B3)-(C1 +C2+C3)
tpd (ns)
CELL NAME
BF063LH
Cpd (pF)
CL=OpF
I
CL=1pF
2.0
I
4.2
0.64
Label: BF063LH A 1,A2,B1,B2,B3,C1 ,C2,C3,Y;
logic symbol
B1 ---'f""".......
B2
B3 ---.&.--"
C 1 - - r -.......
C2
>---~
C3
r-~--'
y
A1
A2---c"--_
6064
OR-NAND GATES,
Y = (A1+A2+A3)-(B1+B2+B3)-(CHC2+C3)
logic symbol
A1--~""'"
tpd (ns)
CELL NAME
CL=OpF
BF064LH
1.9
I CL=1pF
I
Cpd (pF)
4.1
0.70
Label: BF064LH A 1,A2,A3,B1 ,B2,B3,C 1,C2,C3,Y;
A2
A 3 - -_ _
B 1 - - r -.......
B2
B 3 - -_ _
C 1 - - _.......
C2
C 3 - -_ _
3-72
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TeXAS 75266
y
PRODUCT GUIDE
6065
AND-OR-NAND GATES,Y = A1·[B1+(C1·C2)]
tpd Ins)
CELL NAME
CL
BF065LH
=0
pF
I
CL
I
1.2
=
Cpd (pF)
1 pF
0.58
2.8
logic symbol
::~,
A1 _ _ _ _ _ _ _ _ _ _---1
_
Label: BF065LH A1,B1,C1,C2,V;
6066
AND-OR-NAND GATES,
Y = A1.[(B1.B2)+(C1.C2))
logic symbol
II
B1
tpd Ins)
CELL NAME
CL
BF066LH
=0
pF
I
CL
I
1.3
=
Cpd (pF)
B2-""I-_"
0.64
C1--'----,
Q)
1 pF
2.9
Label: BF066LH A1,B1,B2,Cl,C2,V;
V
:2
:::l
~
...
C2-""I-_"
A 1-----------------1
(J
:::l
'"CI
...
6067
0
AND-OR-NAND GATES,
Y = A1.[B1+B2+(C1.C2)]
c.
logic symbol
tpd Ins)
CELL NAME
CL
BF067LH
=0
pF
I CL = 1 pF
I
1.5
Cpd (pF)
0.57
3.7
Label: BF067LH A1,B1,B2,C1,C2,V;
6068
AND-OR-NAND GATES,
Y = A1.[B1+(C1.C2)+(D1.D2)]
logic symbol
tpd Ins)
CELL NAME
CL
BF068LH
=
0 pF
1.8
I
I
CL
=
Cpd (pF)
1 pF
4.0
Label: BF068LH A1,B1,C1,C2,D1,D2,V;
0.61
t-tpp-----J
P-v
Al-------------~·
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
, 3-73
PRODUCT GUIDE
6069
AND-DR-NAND GATES.
Y = A1-[(B1-B21+(C1-C21+(D1-D2)]
logic symbol
Bl
tpd (nsl
CELL NAME
CL=OpF
BF069LH
I CL=lpF
I
1.9
4.2
Cpd (pFI
0.66
B2
Cl
y
C2
Label: BF069LH A1,B1,B2,C1,C2,01,02,Y;
01
02
Al
..
o
6072
"'a
AND-DR-NAND GATES.
Y = (A1+A21-[B1+B2+(C1-C211
..
logic symbol
Q.
s::::
tpd (nsl
(')
CELL NAME
BF072LH
Cpd (pFI
CL=OpF
I
CL=lpF
1.8
I
3.B
0.81
Label: BF072LH A1,A2,B1.,B2,C1,C2,Y;
"~
~!
C2
y
6073
AND:DR-NAND GATES.
Y = (A1 +A21-[B1 +(C1-C2)]
logic symbol
tpd (nsl
CELL NAME
BF070LH
Cpd (pFI
CL=OpF
I
CL=lpF
1.3
J
2.9
0.53
Label: BF070LH A1.A2,Bl,C1,C2,Y;
6074
AND-DR-NAND GATES.
Y = (A1+A21-[(B1-B21+(C1-C2)]
logic symbol
Bl---Jr--tpd (nsl
CELL NAME
BF071LH
Cpd (pFI
CL=OpF
I
CL=lpF
1.5
I
3.1
Label: BF071LH A1,A2.Bl,B2,C1,C2,Y;
0.64
B2-----.'--_
Cl
C2---.L.....~
Al----------~r_~
A2
3-74
-----------1
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
y
PRODUCT GUIDE
6075
AND-OR-NAND GATES.
y = CA1+A2+A3)-[B1+CC1-C211
logic symbol
tpd (nsl
CELL NAME
BF075LH
Cpd (pFI
CL=OpF
I
CL=1pF
1.1
I
2.5
0.77
Label: BF075LH A1,A2,A3,B1,C1,C2,Y;
•
6082
OR-AND-OR-NAND GATES.
Y = A1-{CB1-B2)+[C1-CD1+D211}
logic symbol
I
CL=OpF
BFOS2LH
Cpd (pF)
CL=1pF
1
1.9
CD
02
tpd (ns)
CELL NAME
3.B
0.S7
"C
·S
01
~
...
C1
B2
Label: BFOB2LH A 1,B1 ,B2,C1.01 ,02,Y;
B1
y
U
:::J
"C
0
...
a..
6083
OR-AND-OR-NAND GATES.
Y = A1-{B1+[C1-CD1+D211}
logic symbol
tpd (nsl
CELL NAME
Cpd (pFI
CL = 0 pFI
BFOSOLH
CL = 1 pF
I
1.6
3.7
0.80
Label: BFOBOLH A 1,B1 ,C1 ,01 ,02,Y;
6084
OR-AND-OR-NAND GATES.
Y = A1-{B1+[(C1+C2)-CD1+D211}
logic symbol
tpd (nsl
CELL NAME
I CL=1pF
CL=OpF
BFOS1LH
1.9
I
3.9
Cpd (pFI
0.90
Label: BFOB1LH A1,B1,C1,C2,01,02,Y;
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TeXAS 75265
3-75
PRODUCT GUIDE
6088
OR-AND-OR-NANP GATES.
Y = (A1+A2+A3)-{B1+[C1-(D1+D2)J)
logic symbol
02
01
tpd Ins)
CELL NAME
CL=OpF
BFOBBLH
2.1
j
I
Cpd IpF)
CL=1pF
4.1
C1
0.99
B1
Label: BFOBBLH A1,A2,A3,B1,C1,01,02,Y;
y
A3
A2
A1
6100
4-INPUT GATj:D S-R LATCHES
logic symbol
"a
a
tpd Ins)
CELL NAM!,
Q.
c
n
P+
CL=OpF
GM010LH
I CL=1pF
I
1.3
2.8
Cpd IpF)
RA
R1
Q
S2
QZ
R1
Q
S2
QZ
RB
0.75
Label: GM010~H RA,RB,SA,S13:Q,QZ;
C)
c
SA
a:
CD
SB
61Q1
5-INPUT GATED S-R LATCHES
INCLUDING SEPARATE RESET
logic symbol
R
tpd Ins)
CELL NAME
GM110LH
CL=OpF
J
CL=1pF
1.3
I
3.6
Cpd IpF)
RA
0.80
RB
Label: GM110LH RA,RB.SA,SB,R,Q,QZ;
SA
SB
3-76
TEXAS •
INSTRUMENTS
POST OFFICE
~ox
655012'" DAUAS •. TEXAS 75265
PRODUCT GUIDE
6102
5-INPUT GATED S-R LATCHES
INCLUDING SEPARATE SET
logic symbol
tpd (nsl
CELL NAME
GMS10lH
Cpd (rFI
Cl=OpF
I
Cl=1pF
1.6
I
3.6
.-
0.7&
RA
a
R1
RB
label: GMS10LH RA,RB,SA,SB,S,Q,QZ;
SA
&
S2
SB
S
2
az
S2
•
6103
6-INPUT GATED S-R LATCH~S
INCLUDING SEPARATE SET AND RESET
logic symbol
·S
R
R1
RA
&.
tpd (nsl
CEll NAME
GM210LH
Cpd (pFI
Cl=OpF
I
Cl = 1 pF
1.6
1
3.6
II)
"C
~
a
R1
0.81
RB
Label: GM210LH RA,RB,SA,SB,R,S,Q,QZ;
SA
&
S2
az
R1
a
SB
S
...
(,)
~
..
"C
0
0-
S2
6105
6-INPUT GATED S-R.LATCHES
logic symbol
tpd (nsl
CEll NAME
CL=OpF
GM310LH
1.4
I Cl = 1 pF
T
3.0
Cpd (pFI
0.80
Label: GM310lH RA.RB,RC,SA,SB,SC,Q,QZ;
RA
RB
&
RC
SA
SB
S2
2
az
SC
TEXAS ."
INSTRUMENTS
POST OFfiCE BOX 855012 • DALLAS. TeXAS 75266
3-77
PRODUCT GUIDE
6106
7-INPUT GATED S-R LATCHES
INCLUDING SEPARATE RESET
logic symbol
R
tpd Ins)
CELL NAME
Cpd IpF)
CL=OpF
GM410LH
I CL =lpF
I
1.S
4.0
0.S5
RA
RB
Q
RC
Label: GM410LH RA,RS,RC,SA,SB,SC,R,Q,QZ;
SA
&
SB
S2
2
QZ
SC
B
------...
-0
o
~
...
6108
8-INPUT GATED S-R LATCHES
INCLUDING SEPARATE SET AND RESET
logic symbol
()
R
Rl
RA
&
tpd Ins)
Ci)
C
CELL NAME
s:
CD
GM510LH
Cpd IpF)
CL=OpF
I
CL=lpF
l.S
I
4.0
Rl
RB
0.S6
Q
RC
Label: GM510LH RA,RB,RC,SA,SB.SC.R.S.Q,QZ;
SA
&
SB
S2
2
QZ
SC
S
S2
6110
4-INPUT GATED
S-R LATCHES
logic symbol
tpd Ins)
CELL NAME
CL = 0 pF
GS010LH
1.3
Cpd IpF)
SAZ
0.72
SBZ
ICL=lpF
I
2.7
Sl
Q
R2
QZ
Label: GS010LH RAZ,RBZ,SAZ,SBZ,Q,QZ;
RAZ
RBZ
3-78
TEXAS ..,
INSTRUMENTS
POST OFfiCE BOX 655012 • DALLAS: TEXAS 75285
PRODUCT GUIDE
6111
5-INPUT GATED S-R LATCHES
INCLUDING SEPARATE RESET
logic symbol
tpd Ins)
CELL NAME
GSll0LH
Cpd IpF)
CL=OpF
I
CL = 1 pF
1.5
T
3.1
0.84
Label: GSll0LH RAZ,RBZ,SAZ,SBZ,RZ,Q,QZ;
6112
5-INPUT GATED S-R LATCHES
INCLUDING SEPARATE SET
tpd Ins)
CELL NAME
CL=OpF
GSS10LH
1.4
T CL
I
Cpd IpF)
= 1 pF
3.1
0.84
Label: GSS10LH RAZ,RBZ,SAZ,SBZ,SZ,Q,QZ;
6113
6-INPUT GATED S-R LATCHES
INCLUDING SEPARATE SET AND RESET
logic symbol
SZ
SAZ
SBZ
tpd Ins)
CELL NAME
Cpd IpF)
cL=opFl CL = 1 pF
GS210LH
1.5
I
3.1
0.84
S1
Q
R2
QZ
Label: GS210LH RAZ,RBZ,SAZ,SBZ,RZ,SZ,Q,QZ;
RAZ
RBZ
RZ
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 15265
3-79
. PRODUCT GUIDE
6115
6-INPUT GATED
S-R LATCHES
logic symbol
tpd (nsl
CELL NAME
CL = 0 pF
GS310LH
I CL =
I
1.5
Cpd (pFI
1 pF
0.75
3.4
Label: GS310LH RAZ,RBZ,RCZ,SAZ,SBZ,SCZ;a,az;
SAZ
saz
a
SCZ
RAZ
az
RBZ
•
..."'tI
o
Q.
RCZ
6116
7-INPUT GATED S-R LATCHES
INCLUDING SEPARATE RESET
logic symbol
I:
(')
1'+
tpd (nsl
CELL NAME
CL=OpF
GS4l0LH
J CL=1pF
I
1.7
Cpd IpFI
0.85
3.8
Label: GS410LH RAZ,RBZ,RCZ,SAZ,SBZ,SCZ,RZ,a,aZ;
SAZ
SBZ
S1
Q
SCZ
RAZ
RBZ
R2
2
QZ
RCZ
RZ
6118
8-INPUT GATED S-R LATCHES
INCLUDING SEPARATE SET AND RESET
logic symbol
SZ
tpd (nsl
CELL NAME
GS510LH
Cpd-(pFI
CL=OpF
I
CL=1pF
1.9
I
4.0
SAZ
SBZ
0.89
a
SCZ
Label: GS510LH RAZ,RBZ,RCZ,SAZ,SBZ;SCZ,RZ,SZ,a,az;
RAZ
RBZ
RCZ
RZ
3-80
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
R2
2
QZ
PRODUCT GUIDE
6120
NONINVERTING OELA Y BUFFERS
logic symbol
tpd (nsl
CELL NAME
CL
BU120LH
BU130LH
=0
pF
CL
1.1
1.4
=
Cpd (pFI
A---[>---V
1 pF
1.7
1.7
1.29
1.73
Label: BUlnOLH A,V;
6121
NONINVERTING 3-STATE BUFFERS WITH
ACTIVE-LOW ENABLE
logic symbol
tpd (nsl
CELL NAME
CL
BU221 LH
BU261LH
=0
pF
CL
1.6
1.8
II
A--I>-V
=
Cpd (pFI
GZ~
1 pF
2.3
2.0
1.62
3.29
...
Label: BU2n 1LH A,GZ, V;
(J
~
..
"C
6122
o
NONINVERTING 3-STATE BUFFERS WITH
ACTIVE-HIGH ENABLE
:==S>-V
tpd (nsl
CELL NAME
BU222LH
BU262LH
Cpd (pFI
CL = 0 pF
CL = 1 pF
1.6
1.8
2.3
2.0
0..
logic symbol
1.62
3.30
Label: BU2n2LH A,G,V;
6125
OoTYPE LATCHES WITH ACTIVE-LOW ENABLE
tpd (nsl
CELL NAME
CL = 0 pF
LAL20LH
3.2
1 CL
I
Cpd (pFI
= 1 pF
3.9
4.68
0'10
logic symbol
c--t:::.I.._
C_1_ _ _
t-a
-'~
az
Label: LALnOLH D,C,Q,QZ;
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-81
PRODUCT GUIDE
6130
5-INPUT POSITIVE-OR GATES
logic symbol
tpd Ins)
CELL NAME
OR510LH
Cpd IpFI
CL=OpF
I
CL = 1 pF
2.5
I
3.4
1.11
Label: OR510LH A,B,C,D,E,Y;
6131
8-INPUT POSITIVE-OR GATES
•.
logic symbol
tpd Insl
CELL NAME
"'D
ORS10LH
oQ.
Cpd IpFI
CL=OpF
I
CL=1pF
2.3
I
3.3
1.16
Label: ORS10LH A,B,C,D,E,F,G,H,Y;
C
...
(")
C)
C,
s:
6132
8-INPUT POSITIVE-AND GATES
CD
logic symbol
A
tpd Ins I
CELL NAME
ANS10LH
B
Cpd IpF)
CL=OpF
I
CL=1pF
2.1
I
3.4
C
1.22
0
Label: ANS10LH A,B,C,D,E,F,G,H,Y;
E
F
G
H
3-82
TEXAS ."
INSTRUMENTS
posr OFFICE 90)( 666012
• .DALLAS, TEXAS 75265
V
Data Sheets
4-1
•
4-2
SN54ASCOO, SN74ASCOO
2·INPUT POSITIVE·NAND GATES
02939. AUGUST 1986
SystemCell™
2-"m INTERNAL STANDARD CELL
logic symbol
•
Choice of Five Performance Levels
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
:==D=--V
FUNCTION TABLE
INPUTS
OUTPUT
AS
V
positive logic equation
Y=A B=A+B
H
H
L
L
X
H
X
L
H
description
The SN54ASCOO and SN74ASCOO are 2·input positive·NAND gate CMOS standard-cell functions
implementing the equivalent of one-fourth of an SN54LSOO or SN74LSOO. The standard-cell library contains
five physical implementations providing the custom IC designer a choice between five performance levels
for optimizing design. The five options are designated and called from the engineering workstation input •
using the following cell names to develop labels for the design netlist:
•
FEATURES
CELL NAME
NETLIST
TYPICAL
HDL LABEL
NA210LH
NA220LH
NA230LH
Label: NA2nOLH A.B.Y;
RELATIVE
DELAV
CELL AREA
CL - 1 pF
TO NA210LH
2 ns
1
1.3 ns
1.5
1.1 ns
2
2.5
3.5
NA240LH
1 ns
NA260LH
0.8 ns
fI)
~
CD
CD
.s::.
en
CO
.CO
~
C
The SN54ASCOO is characterized for operation over the full military temperature range of - 55 DC to 125°C.
ihe SN74ASCOO is characterized for operation from -40°C to 85 DC.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
PRODUCTION DATA do.umants contain infDrmatiDn
current as of publication data. Products conform to
specifications per the terms of TexIs Instruments
=~:~;8[::1~1i ~=::i: 1i~D=:~!O:S not
Copyright @ 1986. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
4-3
SN54ASCOO, SN74ASCOO
2·INPUT POSITIVE·NAND GATES
electrical characteristics
PARAMETER
VT
Input threshold voltage
ICC Supply current
ei
TEST CONDITIONS
I
SN54Aseoo
I SN74Aseoo
Input capacitance
Equivalent power
epd
dissipation capacitance
PARAMETER
VT
Input threshold voltage
lee
Supply current
ei
Input capacitance
epd
I
I
SN54Aseoo
SN74Aseoo
Equivalent power
dissipation capacitance
PARAMETER
VT
...C
I»
I»
en
Input threshold voltage
lee Supply current
ei
I SN54Aseoo
I SN74Aseoo
Input capacitance
Equivalent power
epd
dissipation capacitance
Vee = 5 V,
vee - 4.5 V to 5.5 V,
TA
=
TA = 25°C
VI - Vee orO,
NA220LH
TYP MAX
131
196
MIN to MAX
Vee = 5 V,
Vee - 5 V,
TA = 25°C
Vee = 5 V,
Vee - 4.5 V to 5.5 V,
TA = MIN to MAX
TA = 25°e
VI - Vee or 0,
Vee = 5 V,
Vee - 5 V,
TA = 25°C
TA = 25°C
tr - tf - 3 ns,
TA
Vee = 5 V,
Vee - 5 V,
TA = 25°C
TA
VI
= 25°e
= Vee or 0,
=
25°e
tr - tf - 3 ns,
CD
CD
...
(I)
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 865012 • DALLAS,
0.2
pF
0.51
1
pF
TYP
2.2
MAX
254
15.2
NA240LH
TYP MAX
2.2
316
19
T~XAS
75265
UII!IT
V
nA
0.39
0.54
pF
1.51
2.06
pF
NA26QLH
TEST CONDITIONS
Vee = 5 V,
Vee = 4.5 V to 5.5 V,
TA = MIN to MAX
11.7
nA
0.12
NA230LH
TEST CONDITIONS
UNIT
V
2.2
7.84
TA = 25°e
tr - tf - 3 ns,
::T
4-4
NA210LH
TYP MAX
2.2
TYP
2.2
MAX
UNIT
V
433
26
nA
0.79
pF
2.98
pF
SN54ASCOO, SN74ASCOO
2-INPUT POSITIVE-NAND GATES
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
NA210LH
PARAMETERt
tpLH
FROM
TO
TEST
(lNPUTI
(OUTPUT)
CONDITIONS
A or B
tpHL
tpLH
tpHL
~tpLH
~tpHL
A or B
A or B
Y
=
CL
CL
Y
=
0
1 pF
Y
SN54ASCOO
SN74ASCOO
MIN
TYP*
MAX
MIN
TYP*
MAX
0.7
0.8
1.4
0.8
0.5
1
1.5
0.7
0.5
1
1.3
1.4
1.2
2
4
1.2
2
3.7
1
2
4.2
1.1
2
3.7
0.5
1.2
2.7
0.5
1.2
2.5
0.5
1
2.7
0.5
1
2.3
TYP*
MAX
MIN
TYP*
MAX
0.5
0.8
1.3
0.6
0.8
1.2
0.3
0.7
1.4
0.4
0.7
1.3
0.8
1.3
0.9
0.7
1.3
1.3
2.2
UNIT
ns
ns
ns/pF
NA220LH
PARAMETERt
tpLH
tpHL
tpLH
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A or B
Y
A or B
tpHL
~tpLH
~tpHL
A or B
=
CL
Y
CL
=
0
1 pF
y
SN74ASCOO
SN54ASCOO
MIN
0.6
1.3
2.4
2.7
0.3
0.5
1.1
0.3
0.5
1
0.3
0.6
1.3
0.3
0.6
1.1
2.4
UNIT
ns
ns
ns/pF
NA230LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
~tpLH
~tpHL
II
...
CI)
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A or B
Y
A or B
y
A or B
Y
=
CL
CL
=
0
1 pF
SN74ASCOO
SN54ASCOO
MIN
TYP*
MAX
MIN
TYP*
MAX
0.4
0.7
1.3
0.5
0.7
1.3
0.2
0.6
1.4
0.3
0.6
1.3
0.7
1.1
2
0.7
1.1
1.9
0.5
1
2.3
0.5
1
2
0.2
0.4
0.4
0.2
0.2
0.4
0.4
0.7
0.3
0.8
0.9
0.8
UNIT
Q)
Q)
.c
ns
en
ns
«I
«I
...
C
ns/pF
NA240LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
~tpLH
AtpHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A or B
Y
A or B
Y
A or B
Y
=
CL
CL
=
0
1 pF
SN74ASCOO
SN54ASCOO
MIN
TYP*
MAX
MIN
TYP*
MAX
0.4
0.1
0.7
0.5
1.2
1.2
0.4
0.2
0.7
0.5
1.1
1.1
0.6
1
1.8
0.6
1
1.7
0.4
0.9
1.9
0.4
0.9
1.7
0.2
0.3
0.6
0.2
0.3
0.6
0.3
0.4
0.7
0.2
0.4
0.7
tpropagation delay times are measured from the 44% pOint of VI to the 44% point of Vo with tr
tPLH " propagation delay time, low-to-high-Ievel output
tpHL " propagation delay time, high-to-Iow-Ievel output
~tpLH " change in tpLH with load capacitance
~tpHL " change in tpHL with load capacitance
Typical values are at VCC = 5 V, T A = 25 ·C.
=
tf
=
UNIT
ns
ns
ns/pF
3 ns 110% and 90%).
*
TEXAS ."
INSTRUMENTS
POST OFf=ICE BOX 655012 • DALLAS, TEXAS 75265
4-5
SN54ASCOO. SN74ASCOO
2·INPUT POSITIVE·NAND GATES
NA260LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
JltpLH
JltpHL
FROM
TO
TEST
(INPUTI
IOUTPUT)
CONDITIONS
A or B
Y
A or B
Y
A or B
Y
CL = 0
CL
=
1 pF
SN54ASCOO
SN74ASCOO
MIN
TYP*
MAX
MIN
TYP*
MAX
0.4
0.6
0.5
1.2
0.6
1.1
1.2
0.5
0.3
0.5
1.1
0.8
1.6
0.6
0.8
1.5
0.7
1.7
0.4
0.7
1.5
0.2
0.2
0.5
0.1
0.4
0.6
0.1
0.2
0.2
0.1
0.5
0.3
0.1
0.1
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr
tpLH " propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
JltpLH '" change in tpLH with load capacitance
AtpHl :;;;; change in tpHL with load capacitance
*Typical values are at VCC = 5 V, TA = 25 DC.
= tf = 3
0.5
UNIT
ns
ns
ns/pF
ns 110% and 90%1-
DESIGN CONSIDERATIONS
II
Refer to Section 7
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
...c
C»
C»
en
::r
CD
CD
...
(I)
4-6
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ASC02. SN74ASC02
2·INPUT POSITIVE·NOR GATES
02939. AUGUST 1986
SystemCell™
2-lAm INTERNAL STANDARD CELL
logic symbol
•
Choice of Four Performance Levels
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
:=D-v
FUNCTION TABLE
INPUTS
fp;8
positive logic equations
Y=A+B =
"A.i3
OUTPUT
Y
H
X
X
H
L
L
L
H
L
description
The SN54ASC02 and SN74ASC02 are 2-input positive-NOR gate CMOS standard-cell functions
implementing the equivalent of one-fourth of the SN54LS02 or SN74LS02. The standard-cell library contains
four physical implementations providing the custom IC designer a choice between four performance levels
for optimizing designs. Each option is designated and called from the engineering workstation input using
the following cell names to develop labels for the design netlist:
FEATURES
CELL NAME
NETLIST
TYPICAL
RELATIVE
HDL LABEL
DELAY
CELL AREA
CL - 1 pF
TO NA210LH
N0210LH
2.4 ns
1
N0220LH
1.5 ns
1.5
Label: N02nOLH A.B.Y;
N0230LH
N0240LH
1.3 ns
2
1.1 ns
2.5
II
...
en
CD
CD
.c
til
...caca
C
The SN54ASC02 is characterized for operation over the full military temperature range of - 55 DC to 125 DC.
The SN74ASC02 is characterized for operation from -40 DC to 85 DC.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
PRODUCTION DATA documents oonllin information
current as of publication data. Products conform to
specifi..lio.. par Ihe term. of Tu•• Instrumenls
::~:~i~8{::I~li ~:i:;ti:r :.~o=:::~::.s
not
Copyright @ 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-7
SN54ASC02, SN74ASC02
2·INPUT POSITIVE·NOR GATES
electrical characteristics
VT
lee Supply current
ei
epd
Vee = 5 V,
Vee - 4.5 V to 5.5 V,
Input threshold voltage
I SN54Ase02
I SN 74Ase02
=
TA
Input capacitance
Equivalent power
dissipation capacitance
TA
VT
I
lee
Supply current
Input capacitance
tr
=
tf - 3 ns,
25°e
SN74Ase02
= MIN to
= 5 V,
Vee = 5 V,
TA = 25°e
TA
Equivalent power
dissipation capacitance
V
185
11.1
nA
0.24
pF
0.33
0.52
pF
N0240LH
N0230LH
TYP
MAX
TYP
MAX
UNIT
= 25°e
= Vee or 0,
2.2
= 25°e
= tf = 3 ns,
0.36
0.47
pF
0.8
0.98
pF
TA
VI
V
2.2
237
292
14.2
TA
tr
UNIT
0.11
MAX
Vee
MAX
2.2
7.71
TA"- 25°e
Vee = 5 V,
Vee = 4.5 V to 5.5 V,
I SN54Ase02
ei
epd
II
Input threshold voltage
TYP
128
VI - Vee or 0,
TEST CONDITIONS
PARAMETER
MAX
2.2
25°e
MIN to MAX
Vee - 5 V,
Vee - 5 V,
=
TYP
=
TA
N0220LH
N0210LH
TEST CONDITIONS
PARAMETER
17.5
nA
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
N0210LH
C
....I»I»
PARAMETERt
en
::r
tpHL
tPLH
tpLH
CD
CD
tPHL
....en
AtPLH
AtpHL
FROM
TO
TEST
(lNPUTI
(OUTPUTI
CONDITIONS
A or B
Y
A or B
Y
A or B
eL
CL
=0
= 1 pF
Y
SN54ASC02
Typt
MAX
SN74ASC02
TYpt
MAX
MIN
MIN
0.6
0.8
1.6
0.6
0.8
1.5
0.5
1
1.7
0.6
1
1.7
1.5
2.8
6.2
1.6
2.8
5.6
1.1
2
4.6
1.1
2
4.1
0.9
2
4.6
1
2
4.2
0.5
1
2.9
0.5
1
2.5
UNIT
ns
ns
ns/pF
N0220LH
PARAMETERt
tpLH
tpHL
tpLH
tPHL
AtpLH
AtPHL
FROM
TO
TEST
(INPUT)
(OUTPUTI
CONDITIONS
A or B
Y
A or B
Y
A or B
Y
eL
=0
eL = 1 pF
SN54ASC02
TYP*
MAX
MIN
0.6
0.8
1.3
0.6
0.8
1.2
0.3
1
0.8
1.7
1.5
3.5
0.3
1.1
0.8
1.7
3.2
0.7
1.3
2.6
0.7
1.3
2.4
0.4
0.9
2.3
0.5
0.9
2
0.3
0.6
1.1
0.4
0.6
1
tPropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr
tPLH '" propagation delay time, low·to·high-Ievel output
tpHL 5!1! propagation delay time, high-to-Iow-Ievel output
A tPLH '" change in tPLH with load capacitance
AtpHL .. change in tPHL with load capacitance
Typical values are at Vee = 5 V, TA = 25°C.
*
4-8
SN74ASC02
Typt
MAX
MIN
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
1.5
UNIT
ns
ns
ns/pF
= tf = 3 ns (10% and 90%1-
SN54ASC02. SN74ASC02
2·INPUT POSITIVE·NOR GATES
switching characteristics over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise noted) (continued)
N0230LH
PARAMETERt
tpLH
tpHL
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
TEST
SN54ASC02
CONDITIONS
CL
~
0
tPLH
tpHL
A or B
Y
dtPLH
dtpHL
A or B
Y
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
A or 8
Y
CL
~
1 pF
SN74ASC02
MIN
TYP*
MAX
MIN
TYP*
MAX
0.5
0.8
1.4
0.5
0.8
1.2
0.3
0.7
1.6
0.3
0.7
1.5
0.9
1.4
2.9
0.9
1.4
2.6
0.6
1.2
2.4
0.6
1.2
2.2
0.3
0.6
1.5
0.3
0.6
1.4
0.2
0.5
0.9
0.3
0.5
0.8
UNIT
ns
ns
ns/pF
N0240LH
.PARAMETERt
tPLH
tpHL
tpLH
tpHL
dtpLH
dtpHL
A or B
A or B
CL
Y
CL
~
~
0
1 pF
Y
SN54ASC02
SN74ASC02
MIN
TYP*
MAX
MIN
TYP*
MAX
0.5
0.7
1.3
0.5
0.7
1.2
0.2
0.6
1.4
0.2
0.6
1.3
0.7
0 ..5
1.2
1
2.4
2.1
0.8
1.2
1
0.2
0.5
1.2
0.5
1.1
0.2
0.4
0.7
0.5
0.3
0.2
2.2
1.9
0.4
0.6
UNIT
ns
ns
ns/pF
tPropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr ~ tf ~ 3 ns (10% and 90%).
tpLH '" propagation delay time, low-to-high-Ievel output
tPHL '" propagation delay time, high-to-Iow-Ievel output
d tpLH '" change in tpLH with load capacitance
il tpHL ;::: change in tpHL with load capacitance
•
...
fI)
CI)
CI)
.c
en
*Typical values are at VCC ~ 5 V, TA ~ 25°C.
...
CO
CO
DESIGN CONSIDERATIONS
C
Refer to Section 7.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-9
II
...o
I»
I»
en
:::r
CD
CD
...
o
4-10
SN54ASC04, SN74ASC04
INVERTERS
02939. AUGUST 1986
SystemCell™
2-j.lm INTERNAL STANDARD CELL
•
Choice of Seven Performance Levels
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation OVllr V CC Rangll of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
logic symbol
A~Y
FUNCTION TABLE
INPUT
OUTPUT
A
Y
positive logic equation
H
L
L
H
Y=A
description
The SN54ASC04 and SN74ASC04 are CMOS inverter standard cells implementing the equivalent of onesixth of a SN54LS04 or SN74LS04. The standard-cell library contains seven physical implementations
providing the custom IC designer a choice of seven performance levels for optimizing designs. Each of
the options are designated and called from the engineering workstation input using the following cell names
to develop labels for the design netlist:
II
...
FEATURES
NETLIST
TYPICAL
HDL LABEL
DELAY
RELATIVE
CELL AREA
CL - 1 pF
TO NA210LH
IV110LH
1.7 ns
0.75
IV120LH
1.1 ns
IV130LH
0.9 ns
1
1.25
0.8 ns
1.5
CELL NAME
IV140LH
Label: IV1 nOLH A.Y;
1I(160LH
0.7 ns
2
IV180LH
!V101LH
0.6 ns
2.3 ns
2.5
4.5
Label: IV101 LH A.V;
U)
Q)
Q)
.c
o
ca
ca
...
o
The SN54ASC04 is characterized far operation over the full military temperature range of - 55°C to 125°C.
The SN74ASC04 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
PRODUCTIOI DATA do......is .ont.in inform.tion
CURlnt I. ·at publicldiaD date. PrDducts conform tD
specificatio•• par tINt tar....f T.... InstrullllOlS
~~=i~·r:~~; ~~:~i:; :.:o:::::~::.s not
TEXAS
~
INSTRUMENTS
POST OFF1CE BOX 655012 • DALLAS, TeXAS 75265
Copyright © 1986, Texas Instruments Incorporated
4-11
SN54ASC04, SN74ASC04
INVERTERS
electrical characteristics
PARAMETER
VT
Input threshold voltage
.
Vee
I SN74Ase04
TA
lee
Supply current
Input capacitance
epd
Vee - 5 V,
I SN54Ase04
ej
Equivalent power
Vee - 5 V,
Vee - 5 V,
dissipation capacitance
TA
=
V,
VI
=
ISN74Ase04
TA
lee
ej
Input capacitance
Vee - 5 V,
TA - 25°e
Equivalent power
Vee - 5 V,
tr - tf - 3 ns,
dissipation capacitance
TA
=
=
VT
TA
Supply current
Input capacitance
epd
=
Equivalent power
dissipation capacitance
TA
=
VT
Input threshold voltage
ej
epd
ISN54Ase04
I SN74Ase04
pF
2.2
5 V,
Vee - 4.5 V to 5.5 V,
TA = MIN to MAX
=
Input capacitance
Vee
Equivalent power
Vee - 5 V,
dissipation capacitance
TA
=
IV180LH
TVP
3 ns,
5 V,
TA
MAX
2.2
247
V
306
18.4
pF
2.39
3.16
pF
IV101LH
25°e
MAX
2.2
33.2
=
25°e
tr - tf - 3 ns,
25°e
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
UNIT
V
553
VI - Vee or 0,
TA
nA
1
TYP
=
UNIT
0.74
TEST CONDITIONS
=
MAX
14.8
tf
nA
pF
25°e
25°e
Vee
11.4
1.61
VI - Vee or 0,
tr
V
190
1.29
IV160LH
=
UNIT
0.49
TVP
TA - 25°e
PARAMETER
lee Supply current
TA
MAX
2.2
0.4
MIN to MAX
Vee.- 5 V,
5 V.
Vee
IV140LH
TYP
163
VI - Vee or 0,
TEST CONDITIONS
I SN74Ase04
lee
MAX
2.2
25 0 e
25°e
Vee = 5 V,
Vee - 4.5 V to 5.5 V,
ej
pF
9.76
I SN54Ase04
Input threshold voltage
pF
0.8
MIN to MAX
PARAMETER
7.85
nA
0.44
IV130LH
=
V
131
0.24
TYP
Supply current
TA
UNIT
0.12
TEST CONDITIONS
Input threshold voltage
MAX
2.2
6.32
25°e
ISN54Ase04
IV120LH
TVP
105
Vee or 0,
TA - 25°e
tr - tf - 3 ns,
Vee = 5 V,
Vee - 4.5 V to 5.5 V,
MAX
2.2
VT
epd
4-12
TYP
TA - 25°e
= 4.5 V to 5.5
= MIN to MAX
PARAMETER
II
IVll0LH
TEST CONDITIONS
nA
0.13
pF
7.22
pF
SN54ASC04. SN74ASC04
INVERTERS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
IV110LH
PARAMETERt
tpLH
tPHL
tpLH
tpHL
AtPLH
AtpHL
FROM
(INPUT)
A
A
A
TO
(OUTPUT)
TEST
CONDITIONS
Y
CL
CL
Y
~
~
0
1 pF
Y
SN54ASC04
MIN
SN74ASC04
TYP*
O.B
MAX
MIN
TYP*
MAX
1.1
0.6
O.B
1.1
0.4
1.1
0.9
1.4
3.4
0.5
0.9
1.4
1.2
1.B
3.2
0.9
1.6
3.2
1
1.6
2.9
0.5
1
2.3
0.5
1
2.1
0.5
O.B
1.B
0.5
O.B
1.6
MAX
MIN
0.4
TYP*
0.6
1.1
0.4
0.6
1
0.2
0.6
1.2
0.2
0.6
1.1
O.B
1.2
2.1
O.B
1.2
2
0.5
1
2.1
0.6
1
2
0.3
0.5
1.1
0.3
0.5
1
0.3
0.5
0.9
0.3
0.5
0.9
0.6
1.B
UNIT
ns
ns
ns/pF
IV120LH
PARAMETERt
tpLH
tPHL
tPLH
tpHL
AtPLH
AtPHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
A
Y
CL
Y
.CL
A
Y
FROM
(INPUT)
TO
(OUTPUT)
A
Y
A
Y
A
Y
~
~
0
1 pF
SN54ASC04
MIN
SN74ASC04
TYP*
MAX
UNIT
ns
ns
ns/pF
IV130LH
PARAMETERt
tpLH
tpHL
tPLH
tpHL
AtPLH
AtPHL
II
....
en
TEST
CONDITIONS
CL
CL
~
~
0
1 pF
SN54ASC04
SN74ASC04
MIN
0.4
TYP*
0.6
MAX
1.1
MIN
0.4
TYP*
0.6
MAX
1
0.03
0.3
0.9
O.OB
0.3
O.B
0.7
1
1.B
0.7
1
1.7
0.2
0.7
1.5
0.3
0.7
1.4
0.2
0.4
O.B
0.2
0.4
0.7
0.2
0.4
0.7
0.2
0.4
0.6
TYP*
0.5
MAX
MIN
0.9
0.4
0.9
0.1
0.6
0.4
0.9
1.5
0.3
0.7
1.5
0.2
0.3
0.6
0.2
0.3
0.6
UNIT
Q)
Q)
.c
ns
ns
f/)
....asas
C
ns/pF
IV140LH
PARAMETERt
tpLH
tPHL
tpLH
tpHL
AtpLH
AtPHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Y
A
Y
A
Y
CL
CL
~
~
0
1 pF
SN54ASC04
MIN
0.4
0.1
SN74ASC04
TYP*
0.5
MAX
0.6
0.4
0.9
O.B
1.4
0.3
0.7
1.4
0.2
0.3
0.6
0.2
0.3
0.6
0.9
UNIT
ns
ns
ns/pF
tpropagation delay ti~es are measured from the 44% point of VI to the 44% point of Vo with tr ~ tf ~ 3 ns (10% and 90%).
tpLH :;;;;; propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
AiPLH '" change in tpLH with load capacitance
AtPHL '" change in tpHL with load capacitance
Typical values are at VCC ~ 5 V, T A ~ 25 ·C.
*
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-13
SN54ASC04. SN74ASC04
INVERTERS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
IV160LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
Ll.tpLH
Ll.tPHL
FROM
TO
TEST
(INPUT)
(OUTPUTI
CONDITIONS
A
A
Y
CL = 0.
CL = 1 pF
Y
A
Y
FROM
(INPUT)
TO
TEST
(OUTPUTI
CONDITIONS
SN74ASC04
SN54ASC04
MIN
TYP*
MAX
MIN
0..3
0..5
0..8
0..3
0..0.9
0..5
0..3
0..7
0..8
1.3
TYP*
0..5
MAX
0..1
0..3
0..5
0..7
0..8
.1.2
0..8
0..2
0..6
1.3
0..3
0..6
1.2
0..1
0..2
0..5
0..1
0..2
0..5
0..1
0..2
0..5
0..1
0..2
0..5
UNIT
ns
ns
ns/pF
IV180LH
PARAMETERt
tpLH
tpHL
•
C
tpLH
tPHL
Ll.tpLH
Ll.tpHL
A
A
Y
CL
Y
CL
=
=
0.
1 pF
A
Y
FROM
(INPUT)
TO
TEST
(OUTPUTI
CONDITIONS
SN54ASC04
SN74ASC04
MIN
TYP*
MAX
MIN
0..4
0..8
0..3
TYP*
0..4
MAX
0..3
0..0.8
0..3
0..8
0..1
0..3
0..7
0..4
0..6
1.1
0..4
0..6
1.1
0..2
0..1
0..5
1.1
0..2
0..5
1
0..2
0..4
0..1
0..2
0..4
0..1
0..2
0..4
0..1
0..2
0..4
TYP*
2.3
MAX
MIN
5
1.3
1
2
4.6
1
2
4.1
1.3
2.4
5.2
1.4
2.4
4.7
0..7
UNIT
ns
ns
ns/pF
IV101LH
....
CI)
CI)
PARAMETERt
en
tpLH
::r
tpHL
.~
tPLH
....
A
A
Y
Y
CL
CL
= 0.
=
1 pF
SN74ASC04
SN54ASC04
MIN
1.3
TYP*
2.3
MAX
4.5
1
2.1
4.9
1.1
2.1
4.4
60.
120.
230.
60.
120.
20.0.
30.
110.
290.
50.
110.
280.
tPropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr
tpLH '" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
Ll.tpLH '" change in tPLH with load capacitance
Ll.tpHL '" change in tPHL with load capacitance
Typical values are at VCC = 5 V, TA = 25°C.
= tf =
tpHL
(I)
Ll.tPLH
Ll.tpHL
A
Y
*
DESIGN CONSIDERATIONS
Refer to Section 7.
4-14
TEXAS ...,
INS1RUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
UNIT
ns
ns
ps/pF
3 ns (10.% and 90.%1-
SN54ASC08. SN74ASC08
2·INPUT POSITIVE·AND GATES
D2939. AUGUST 1986
SystemCell™
2'/lm INTERNAL STANDARD CELL
logic symbol
•
Choice of Four Performance levels
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
:==O--Y
FUNCTION TABLE
INPUTS
OUTPUT
A
B
Y
positive logic equations
H
H
H
Y = A.B=A+B
L
X
L
X
L
L
description
The SN54ASC08 and SN74ASC08 are 2·input positive-AND gate CMOS standard cells each implementing
the equivalent of one-fourth of an SN54LS08 or SN74LS08. The standard-cell library contains four physical
implementations providing the custom IC designer a choice between four performance levels for optimizing
designs. Each option is designated and called from the engineering workstation input using the following
cell names to develop labels for the design netlist:
II
...
FEATURES
NETLIST
CELL NAME
TYPICAL
HDL LABEL
DELAY
CELL AREA
TO NA210LH
2.1 ns
Label: AN2nOLH A.B.Y;
AN240LH
Q)
Q)
CL - 1 pF
AN210LH
AN220LH
t/)
RELATIVE
AN260LH
..&:
(J)
1.5
1.9 ns
1.75
2.1 ns
2.25
1.7 ns
3
...
CO
CO
C
The SN54ASC08 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN74ASC08 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~::~~i~8t::1~1~ ~!:~:~ti:f :IIO::~:~:t:~s~S
not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
Copyright
©
1986, Texas Instruments Incorporated
4-15
SN54ASCOB. SN74ASCOB
2·INPUT POSITIVE·AND GATES
electrical characteristics
PARAMETER
Vee ~ 5 V,
TA - 25°e
Vee - 4.5 V to 5.5 V,
VI - Vee or 0,
Input threshold voltage
lee
Supply current
ei
Input capacitance
Vee - 5 V,
TA - 25°e
Equivalent power
VCC - 5 V,
TA ~ 25°C
tr - tf -
I SN54Ase08
I SN74Ase08
~
TA
dissipation capacitance
PARAMETER
3 ns,
Vee ~ 5 V,
TA
Vee - 4.5 V to 5.5 V,
VI - Vee or 0,
~
25°e
ei
Input capacitance
Vce ~ 5 V,
TA ~ 25°e
Equivalent power
Vee - 5 V,
t r - tf - 3 ns,
dissipation capacitance
TA
~
~
V
228
13.6
pF
0.9
1.2
pF
AN260LH
MAX
2.2
TYP
MAX
2.2
MIN to MAX
381
17.2
UNIT
V
286
25°C
nA
0.13
AN240LH
Supply current
UNIT
0.13
TYP
Input threshold voltage
MAX
2.2
11.6
lec
TA
TYP
194
TEST CONDITIONS
II SN54Ase08
SN74Aseos
AN220LH
MAX
2.2
MIN to MAX
VT
epd
:.I
TYP
VT
epd
III
AN210LH
TEST CONDITIONS
22.S
nA
0.13
0.26
pF
2.32
3.0S
pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
AN210LH
c
PARAMETERt
Q)
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
r+
Q)
tPLH
en
tPHL
CD
CD
tPHL
LltpLH
UI
LltpHL
::r
A or B
V
A or B
V
tpLH
r+
A or B
~
CL
eL
~
a
1 pF
Y
SN54Aseos
Typt
MAX
SN74ASCOS
TYP'
MAX
0.6
1.2
2.S
0.6
1.2
2.5
0.8
1.3
2.8
O.S
1.3
2.6
MIN
MIN
1.1
2.2
5
1.2
2.2
4.6
1.1
1.9
4.2
1.1
1.9
3.S
0.5
1
2.3
0.5
1
2.1
0.2
0.6
1.5
0.3
0.6
1.3
SN54ASC08
Typt
MAX
MIN
UNIT
ns
ns
ns/pF
AN220LH
PARAMETERt
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A or B
Y
MIN
0.7
1.4
3.3
O.S
1.4
3
tpHL
O.S
1.5
3.1
0.9
1.5
2.S
tpLH
1
2
4.4
1.1
2
4
1
1.8
3.9
1.1
1.8
3.5
0.2
0.5
1.2
0.2
0.5
1.1
0.1
0.3
0.9
0.2
0.3
O.S
tpLH
A or B
Y
A or B
Y
tpHL
LltPLH
LltpHL
~
eL
CL
=
a
1 pF
tPropagation delay times are measured from the 44% point of VI to the 44% point of
tpLH == propagation delay time, low-to-high-Ievel output
tpHL == propagation delay time, high-to-Iow-Ievel output
~tpLH ~ change in tpLH with load capacitance
8tpHL == change in tpHL with load capacitance
'Typical values are at Vee ~ 5 V, TA ~ 25°e.
4-16
SN74ASC08
Typt
MAX
TEXAS
Vo
"'11
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
ns
ns
ns/pF
with tr == tf == 3 ns (10% and 90%).
SN54ASCOB, SN74ASCOB
2-INPUT POSITIVE-AND GATES
AN240LH
PARAMETERt
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tpHL
A or B
Y
tPLH
tpHL
A or B
Y
AtPLH
AtPHL
TEST
CONDITIONS
CL
CL
=0
=
1 pF
A or B
Y
FROM
(INPUT)
TO
(OUTPUT)
CONDITIONS
AorB
Y
CL = 0
SN54ASCOB
MIN
0.9
1
SN74ASCOB
TYP*
1.9
1.B
MAX
MIN
4.3
3.7
2.2
2
5
4.4
1
1.1
1.2
TYP*
1.9
1.B
2.2
0.3
0.2
0.7
0.7
1.2
0.1
2
0.3
0.1
0.2
1.1
1.1
0.1
0.1
MAX
3.B
3.4
UNIT
ns
4.4
4
ns
0.7
0.6
nsipF
AN260LH
PARAMETERt
tpLH
tPHL
tPLH
tpHL
AtPLI;1
AtPHL
A or B
y
A or B
Y
TEST
CL = 1 pF
SN54ASCOB
TYP* MAX
1.5
3.5
1.5
3
MIN
0.7
0.9
O.B
1
0.1
0.03
SN74ASCOB
MIN
O.B
1
TYP*
1.5
1.5
MAX
3.1
1.7
1.7
2.9
3.5
3.2
1.7
1.7
3.9
3.4
0.9
1
0.2
0.5
0.5
0.1
0.2
0.4
0.04
0.16
0.4
0.16
UNIT
ns
ns
ns/pF
tpropagation delay times are measured from the 44% point of VI to the 44% point of Va with tr = tf = 3 ns (10% and 90%).
tPLH .. propagation delay time, low-to-high-Ievel output
tPHL .. propagation delay time, high-to-Iow-Ievel output
AtpLH .. change in tpLH with load capacitance
AtpHL .. change in tpHL with load capacitance
*Typical values are at VCC = 5 V, TA = 25°C.
DESIGN CONSIDERATIONS
•
...
U)
CD
CD
.c
en
...
Refer to Section 7
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TEXAS 75285
CO
CO
o
4-17
o
I»
....
I»
en
:r
(1)
(1)
Cri
4-18
SN54ASC10, SN74ASC10
3·INPUT POSITIVE·NAND GATES
02939. AUGUST 1986
SystemCelrM
2·",m INTERNAL STANDARD CELL
logic symbol
•
Choice of Four Performance Levels
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
.Dependable Texas Instruments Quality and
Reliability
FUNCTION TABLE
INPUTS
B
C
H
H
H
L
L
X
X
H
X
L
X
H
X
X
l
Ii
positive logic equation
y = ABC =
OUTPUT
A
A+B+C
V
description
The SN54ASC1 0 and SN74ASC1 0 are 3-input positive-NAND gate CMOS standard cell, each implementing
the equivalent of one-third of an SN54LS 10 or SN7 4LS 10. The standard-cell library contains four physical
implementations providing the custom IC designer a choice between four performance levels for optimizing
design. The four options are designated and called from the engineering workstation input using the following
cell names to develop lal:Jels for the design netlist:
...en
FEATURES
CELL NAME
NETLIST
TYPICAL
RELATIVE
HDL LABEL
DELAV
CELL AREA
CL - 1 pF
TO NA210LH
.c
2.2 ns
1.25
en
1.5 ns
2
2.5
3.5
...caca
C
NA310lH
NA320lH
NA330LH
II
label: NA3nOlH A.B,C,V;
NA340lH
1.3 ns
1.1 ns
Q)
Q)
The SN54ASC10 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN74ASC10 is. characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
PRODUCTION DATA d••umant••ontain information
currant as af publication date. Products conform to
specifications par the terms of Texas Instrumel'!ts
=~:~~i~ai~:1~1. ~:~::i:r :r~o:::::~:~~s not.
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4·19
SN54ASC10, SN74ASC10
3-INPUT POSITIVE-NAND GATES
electrical characteristics
PARAMETER
VT
I SN54ASC10
I SN74ASC10
2.2
VCC = 5 V,
TA = 25°C
VCC = 4.5 V to 5.5 V,
VI = VCC or 0,
Supply current
Ci
Input capacitance
. VCC - 5 V,
Equivalent power
VCC.- 5 V,
TA = 25°C
dissipation capacitance
NA330LH
Input threshold voltage
ICC
.
Supply current
VCC = 5 V,
TA = 25°C
VCC = 4.5 V to 5.5 V, . VI = VCC orO,
TA = MIN to MAX
Ci
Input capacitance
VCC - 5 V,
TA - 25°C
Equivalent power
VCC = ..5 V,
tr = tf = 3 ns,
dissipation capacitance
TA = 25°C
I
,
0.5
TYP
15.3
2.2
nA
0.26
pF
0.94
pF
NA340LH
MAX
UNIT
V
255
9.78
VT
MAX
2.2
0.12
TA - 25°C
tr - tf = 3 ns,
TEST CONDITIONS
ISN54ASC10
SN74ASC10
NA320LH
TYP
163
TA = MIN to MAX
PARAMETER
Cpd
•
Input threshold voltage
ICC
Cpd
NA3101.!'I
TVP MAX
TEST CONDITIONS
ryp
MAX
2.2
344
V
435
20.6
UNIT
26.1
nA
0,39
0.52
pF
1.41
1.86
pF
switching characteristics dver recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
NA310LH
C
PARAMETERt
DI
r+
tpLH
DI
(/)
tpHL
:::r
tpLH
r+
~tpLH
(1)
(1)
tPHL
en
~tpHL
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
A,B,C
Y
CL = 0
A,B,C
Y
CL =1 pF
A,B,C
Y
SN54ASC10
SN74ASC10
MIN
TYP'
MAX
MIN
0.8
0.6
0.5
0.7
1.9
2.1
TYP*
0.8
MAX
0.7
0.6
0.7
1.8
1.7
1
2
4.8
1.1
2.4
5.B
1.3
2
2.4
4.4
1.1
0.5
1.2
3.1
0.5
1.2
2.9
0.6
1.4
3.8
0.7
1.4
3.2
5.1
UNIT
ns
ns
ns/pF
NA320LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
~tpLH
~tpHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A,B,C
A,B,C
A,B,C
Y
CL = 0
Y
CL = 1 pF
Y
SN54ASC10
SN74ASC10
MIN
TYP*
MAX
MIN
TYP*
MAX
0.5
0.9
1.5
0.6
0.9
1.5
0.3
0.8
1.7
0.4
0.8
1.6
0.8
0.6
1.4
2.8
0.9
1.4
2.6
1.5
3.4
0.8
1.5
3.1
0.3
0.5
1.3
0.3
0.5
1.1
0.3
0.7
1.B
0.4
0.7
1.5
t Propagation 'de)ay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf
tpLH '" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
AtPLH
== change in tpLH with load capacitance
AtPHL " change in tpHL with load capacitance
tTypical values are at VCC = 5 V, TA = 25°C.
4-20
TEXAS ...
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
=3
UNIT
ns
ns
ns/pF
ns (10% and 90%).
SN54ASC1D, SN74ASC1D
3·INPUT POSITIVE·NAND GATES
NA330LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
AtPLH
AtpHL
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONOITIONS
A,B,C
Y
A,B,C
Y
A,B,C
Y
=0
CL
CL
=
1 pF
SN54ASC10
SN74ASC10
MAX
MIN
0.8
1.5
1.7
0.7
0.8
1.2
0.6
MIN
TYP*
0.5
0.3
TYP*
MAX
0.6
0.8
1.5
0.5
0.8
1.6
2.3
0.8
1.2
2.2
1.3
2.9
0.7
1.3
2.6
0.2
0.4
0.8
0.2
0.4
0.8
0.2
0.5
1.2
0.2
0.5
1
MAX
0.5
TYP*
0.8
1.5
MIN
0.5
TYP*
0.8
MAX
1.4
0.3
0.7
1.6
0.3
0.7
1.5
0.6
1.1
2.1
0.7
1.1
2
0.4
1.1
2.5
0.5
1.1
2.2
0.2
0.3
0.7
0.2
0.3
0.6
0.2
0.4
0.9
0.2
0.4
0.8
UNIT
ns
ns
nsipF
NA340LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
AtpLH
AtPHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A,B,C
Y
A,B,C
Y
A,B,C
Y
CL
CL
=
=
0
1 pF
SN54ASC10
MIN
SN74ASC10
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf
tpLH .. propagation delay time, low·to-high-Ievel output
tpHL " propagation delay time, high-to-Iow-Ievel output
AtPLH " change in tpLH with load capacitance
AtpHL '" change in tpHL with load capacitance
Typical values are at VCC = 5 V, TA = 25°C.
=
UNIT
ns
ns
nsipF
3 ns (10% and 90%).
*
II
...
II)
CD
CD
.c
til
DESIGN CONSIDERATIONS
...
ctI
ctI
C
Refer to Section 7
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-21
c
Q)
....
Q)
en
:r
(T)
(T)
....
(II
SN54ASC11, SN74ASC11
3-INPUT POSITIVE-AND GATES
02939. AUGUST 1986
SystemCeUTM
2-/Lm INTERNAL STANDARD CELL
logic symbol
•
Choice of Four Performance Levels
•
Specified for Operation Over Vee Range of
4.5 V to 5.5 V
•
Functional Operation Over Vee Range of
2Vt06V
•
}-Y
FUNCTION TABLE
INPUTS
Dependable Texas Instruments Quality and
Reliability
B
C
Y
H
H
X
H
H
X
X
L
L
X
L
L
L
positive logic' equation
Y = ABC =
X
X
A+B+C
OUTPUT
A
L
description
The SN54ASC11 and SN74ASC11 are 3-input positive-AND gate CMOS standard cells implementing the
equivalent of one-third of an SN54LS11 or SN74LS11. The standard-cell library contains four physical
implementations providing the custom IC designer a choice between four performance levels for optimizing
designs. The four options are designated and called from the engineering workstation input using the _
following cell names to develop labels for the design netlist:
...
...
FEATURES
NETLIST
CELL NAME
TYPICAL
DELAY
CELL AREA
CL - 1 pF
TO NA210LH
AN310LH
2.4 ns
1.75
AN320LH
2.2 ns
2
2.5 ns
2.5
1.9 ns
3.5
AN340LH
HDL LABEL
fI)
RELATIVE
Label: AN3nOLH A.B,C, Y;
AN360LH
Q)
Q)
.c
en
...caca
o
The SN54ASC11 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN74ASC11 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
8.
PRODUCTION DATA documonts .ontoin information
current of publication data. Products conform to
specificatioRs per the terms of Texl. Instruments
::~::~~i~·r::I~'i ~!::i:~:: :1~O:::::t::'· not
Copyright @ 1986. Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-23
SN54ASC11. SN74ASC11
3-INPUT POSITIVE-AND GATES
electrical characteristics
PARAMETER
VT
I
SN54ASC11
SN74ASC11
I
Supply current
Ci
Input capacitance
Cpd
VCC = 5 V,
VCC - 4.5 V to 5.5 V,
Input threshold voltage
ICC
=
TA
Equivalent power
dissipation capacitance
TA
=
TA
TYP
=
I SN54ASC11
I SN74ASe11
t r - tf - 3 ns,
25°C
VCC = 5 V,
VCC - 4.5 V to 5.5 V,
TA = MIN to MAX
TA
2.2
V
249
pF
1.06
1.56
pF
AN360LH
MAX
2.2
25°C
Supply current
Vee - 5 V,
TA - 25°C
Equivalent power
Vee - 5 V,
t r - tf - 3 ns,
dissipation capacitance
TA
TYP
25°C
MAX
2.2
311
18.7
VI - VCC or 0,
Input capacitance
15
nA
0.12
AN340LH
=
UNIT
0.12
TYP
Ci
=
MAX
13.3
TA - 25°C
ICC
epd
TYP
221
TEST CONDITIONS
Input threshold voltage
AN320LH
MAX
2.2
25°C
VI - VCC or 0,
MIN to MAX
VCC - 5 V,
VCC - 5 V,
PARAMETER
VT
AN310LH
TEST CONDITIONS
UNIT
V
438
26.3
nA
0.12
0.26
pF
2.59
4.08
pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
AN310LH
c
PARAMETERt
D)
r+
tplH
tpHl
D)
(f)
-:r
tplH
CD
CD
~tplH
(I)
~tpHl
tpHl
r+
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A,B,e
A,B,e
A,B,e
Y
Cl = 0
el = 1 pF
Y
Y
SN54ASC11
SN74ASC11
MIN
TYP*
MAX
MIN
0.8
3.8
0.8
0.9
1.6
1.6
MAX
1
TYP*
1.6
1.6
3.3
1.3
2.6
6
1.4
2.6
5.4
3.3
3
1.2
2.2
4.7
1.3
2.2
4.3
0.5
1
2.3
0.5
1
2.1
0.2
0.6
1.5
0.3
0.6
1.4
UNIT
ns
ns
ns/pF
AN320LH
PARAMETERt
tPlH
tpHl
tplH
tpHl
~tplH
~tpHl
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A,B,e
A,B,e
A,B,e
Y
Cl
Y
el
=
=
0
1 pF
SN54ASC11
TYP*
MAX
MIN
TYP*
MAX
0.8
1.8
4.2
0.9
1.8
3.8
0.9
1.6
3.5
0.9
1.6
3.2
1.1
2.3
2
5.4
4.4
1.2
1.2
2.3
4.8
2
4
0.5
0.4
1.3
0.3
0.5
1.1
0.9
0.1
0.4
0.8
1.1
0.2
Y
SN74ASC11
MIN
0.1
UNIT
ns
ns
ns/pF
t Propagation delaY times are measured from the 44% point of VI to the 44% point of Va with tr = tf = 3 ns 110% and 90%).
tplH '" propagation delay time, low-to-high-Ievel output
tpHl '" propagation delay time, high-to-Iow-Ievel output
.6tpLH
~tpHL
= change in tpLH with load capacitance
.. change in tPHL with load capacitance
= 5 V, TA = 25°C.
*Typical values are at Vee
4-24
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASCll, SN74ASCll
3-INPUT POSITIVE-AND GATES
AN340LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
dtpLH
dtpHL
FROM
TO
TEST
(INPUT)
IOUTPUT)
CONDITIONS
A,B,G
y
A,B,G
y
A,B,G
Y
GL
GL
~
~
0
1 pF
SN54ASC11
Typt
MAX
MIN
SN74ASC11
Typt
MAX
MIN
1.1
2.3
5.6
1.1
2.3
4.9
1.1
2.1
4.6
1.1
2.1
4.1
1.2
2.6
6.3
1.3
2.6
5.6
1.2
2.3
5.2
1.3
2.3
4.7
0.1
0.3
0.6
0.1
0.3
0.7
0.1
0.2
0.7
0.1
0.2
0.6
SN54ASC11
Typt
MAX
MIN
UNIT
ns
ns
nsipF
AN360LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
dtpLH
dtpHL
FROM
TO
TEST
(INPUT)
IOUTPUT)
CONDITIONS
A,B,G
Y
A,B,G
Y
A,B,G
Y
GL
GL
~
~
0
MIN
SN74ASC11
Typt
MAX
0.6
1.6
4.3
0.9
1.6
3.5
0.9
0.9
1.6
3.6
1.6
3.3
4.3
1
2
4.6
1
2
1
1.6
3.9
1
1.6
3.6
0.1
0.08
0.2
0.5
0.1
0.2
0.5
0.2
0.5
0.08
0.2
0.4
1 pF
UNIT
ns
ns
nsipF
t Propagation delay times are measured from the 44% pOint of VI to the 44% point of Vo with tr ~ tf ~ 3 ns 110% and 90%).
tPLH '" propagation delay time, low-to-high-Ievel output
tPHL '" propagation delay time, high-to-Iow-Ievel output
dtpLH '" change in tpLH with load capacitance
dtpHL '" change in tpHL with load capacitance
t Typical values are at VGG ~ 5 V, T A ~ 25°G.
DESIGN CONSIDERATIONS
II
...
en
Q)
Q)
.c
en
...
CO
CO
Refer to Section 7
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
C
4-25
•
c
Q)
r+
Q)
en
:r
CD
CD
r+
VI
4-26
SN54ASt20. SN74ASC20
4·INPUT POSITIVE·NAND GATES
02939, August 1986
SystemCell™
2-j.lm INTERNAL STANDARD CELL
•
Choice of Three Performance Levels
•
Specified for Operation Over Vec Range of
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
logic symbol
5 V to 5.5 V
FUNCTION TABLE
positive logic equation
Y
OUTPUT
INPUTS
= A.B.C.D = A+B+C+D
A
B
C
D
Y
H
H
H
H
L
X
X
X
l
X
X
X
l
H
X
X
X
X
X
X
L
L
H
H
H
description
The SN54ASC20 and SN74ASC20 are four-input positive-NAND gate CMOS standard cells, each
implementing the equivalent of one-half of an SN54LS20 or SN74LS20. The standard·celilibrary contains
three physical implementations to provide the custom IC deSigner a choice from three performance levels
for optimizing designs. Each option is designated and called from the engineering workstation input using
the following cell names to develop labels for the design netlist:
'
II
FEATURES
CEll NAME
NETLIST
TYPICAL
RELATIVE
HDllABEl
DELAY
CEll AREA
Cl - 1 pF
TO NA210lH
NA410LH
NA420LH
Label: NA4nOLH A,B,C,D, Y;
NA430lH
2.6 hs
1.5
1.8 ns
2.5
1.5 ns
3.75
The SN54ASC20 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN74ASC20 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
PRODUCTION DATA documents contain information
currant as of publication data. Products conform fa
specifications par the terms of Taxas Instruments
=::~:~~i~a{::,-::Ji ~!:~::i:; :,~o::;::::£::.s
not
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DAlLAS;TEXAS 75265
4-27
SN54ASC20, SN74ASC20
4·INPUT POSITIVE·NAND GATES
electrical characteristics
PARAMETER
VT
Cj
Cpd
I SN54ASC20
TA = 25°C
VCC = 5 V,
VCC - 4.5 V to 5.5 V, VI - VCC or 0,
I SN54ASC20
TA
Input threshold voltage
ICC Supply current
=
Equivalent power
dissipation capacitance
TA
=
312
11.2
TA
=
25°C
18.7
0.27
pF
0.5
0.96
pF
25°C
NA430LH
I SN54ASC20
I SN74ASC20
TA = MIN to MAX
=
TYP
2.2
Input threshold voltage
ICC
Supply current
Cj
Input capacitance
VCC = 5 V,
TA = 25°C
Equivalel"!t power
VCC - 5 V,
TA = 25°C
t r - tf - 3 ns,
TA
nA
0.12
tr - tf - 3 ns,
VCC = 5 V,
VCC - 4.5 V to 5.5 V,
UNIT
V
187
TEST CONDITIONS
dissipation capacitance
MAX
2.2
VT
Cpd
NA420LH
TYP
2.2
MIN to MAX
VCC = 6 V,
VCC - 5 V,
Input capacitance
PARAMETER
II
NA410LH
. TYP
MAX
TEST CONDITIONS
25°C
MAX
V
441
VI - VCC or 0,
UNIT
26.4
nA
0.4
pF
1.46
pF
switching characteristics over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise noted)
NA410LH
PARAMETERt
tpLH
FROM
TO
TEST
liN PUT!
(OUTPUT!
CONDITIONS
A,B,C,D
Y
A,B,C,D
Y
tpHL
tpLH
tPHL
<1tpLH
<1tpHL
A,B,C,D
CL
CL
=
=
0
1 pF
Y
SN74ASC20
SN54ASC20
MIN
0.8
TYP*
1.1
MAX
2
MIN
0.8
TYP*
1.1
MAX
1.9
0.6
1.1
2.7
0.6
1.1
2.4
1.3
2.4
5.7
1.3
2.4
5.2
1.4
2.9
7.5
1.5
2.9
6.5
0.5
1.3
3.9
0.5
1.3
3.5
0.8
T.8
4.8
0.8
1.B
4.1
MAX
MIN
TYP*
UNIT
ns
ns
nsipF
NA420LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
<1tpLH
<1tPHL
4-28
FROM
TO
TEST
liN PUT!
(OUTPUT)
CONDITIONS
A,B,C,D
Y
CL = 0
A,B,C,D
Y
A,B,C,D
Y
CL
=
1 pF
TEXAS
SN54ASC20
SN74ASC20
MIN
TYP*
0.6
1
1.B
0.7
1
1.7
0.5
0.9
1
2.4
0.5
2.1
1.6
3.3
1
1
1.6
1.9
4.6
1
1.9
4
MAX
3
O.B
0,3
0.6
1.5
0.3
0.6
1.4
0.4
O.B
2.3
0.4
0.8
2
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
UNIT
ns
ns
nSipF
SN54ASC20, SN74ASC20
4·INPUT POSITIVE·NAND GATES
NA430LH
PARAMETERt
tpLH
tpHL
tpLH
tPHL
dtpLH
dtpHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A,B,C,D
Y
CL = 0
A,B,C,D
Y
A,B,C,D
Y
CL
=
SN54ASC20
1 pF
SN74ASC20
MAX
MIN
0.6
TYP*
1
1.9
0.6
1
1.8
0.4
1
2.3
0.5
1
2.1
0.8
1.4
2.9
0.9
1.4
2.7
0.7
1.6
3.9
0.8
1.6
3.4
MIN
TYP*
MAX
0.2
0.4
1.1
0.2
0.4
1
0.3
0.6
1.6
0.3
0.6
1.3
t Propagation delay times are measured from the 44% point of VI to the 44% point of Va with tr
tpLH '" propagation delay time, low-to-high-Ievel output
tPHL '" propagation delay time, high-to-Iow-Ievel output
= tf =
UNIT
ns
ns
ns/pF
3 ns (10% and 90%1.
.6.tpLH ;;;;;; change in tpLH with load capacitance
dtpHL '" change in tPHL with load capacitance
* Typical values are at VCC = 5 V, TA = 25 ·C.
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
a
til
+"
Q)
Q)
.c:
en
ca
ca
+"
o
TEXAS •
INSTRUMENTS
POST OFFICE BOX
6550~2
• DALLAS. TEXAS 75265
4-29
III
4-30
SN54ASC21, SN74ASC21
4·INPUT POSITIVE·AND GATES
D2939. AUGUST 1986
SystemCelllM
2'",m INTERNAL STANDARD CELL
logic symbol
•
Choice of Four Performance Levels
•
Specified for Operation Over Vee Range of
4.5 V to 5.5 V
•
Functional Operation Over Vee Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
FUNCTION TABLE
INPUTS
=-=-=-=
Y = A.B·C·D = A+B+C+D
OUTPUT
C
H
D
H
Y
H
B
H
L
X
L
L
X
X
X
L
X
X
X
X
X
X
L
L
A
positive logic equations
X
X
H
L
L
description
a...
The SN54ASC21 and SN74ASC21 are 4-input positive-AND gate CMOS standard-cells implementing the
equivalent of one-half of an SN54LS21 or SN74LS21. The standard-cell library contains four physical
implementations providing the custom IC designer a choice between four performance levels for optimizing
designs. The four options are designated and called from the engineering workstation input using the
following Gell names to develop labels for the design netlist:
en
CI)
CI)
.s::
FEATURES
CELL NAME
TYPICAL
NETLIST
HDL LABEL
AN410LH
AN420LH
AN440LH
Label: AN4nOLH A.B.C.D.Y;
AN460LH
fJ)
RELATIVE
DELAY
CELL AREA
CL - 1 pF
TO NA210LH
2.6 ns
2
2.5 ns
2.25
2.7 ns
2.75
2.3 ns
4
...
~
~
C
The SN54ASC21 is characteri2!ed for operation over the full military'temperature range of - 55 DC to 125 DC.
The SN74ASC21 is characterized for operation from - 40 DC to 85 DC.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
PRODUCTION DATA documents contain information
current as of publication data. Preducts conform to
specifications per the terms of Taxas Instruments
~'::~:~~i;8t::I~'~ ~=::i:; :'~D:::~9t::a~1 not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. !EXAS 75265
Copyright © 1986, Texas Instruments Incorporated
4-31
SN54ASC21, SN74ASC21
4-INPUT POSITIVE-AND GATES
electrical characteristics
VT
Input threshold voltage
Supply current
Ci
Cpd
II
Vec = 5 V,
TA=25°C
VCC = 4.5 V to 5.5 V,
VI = VCC or 0,
SN74ASC21
TA = MIN to MAX
TA - 25°C
Equivalent power
VCC = 5 V,
tr - tf - 3 ns,
dissipation capacitance
TA = 25°C
I
Cpd
II
= 4.5
VCC
V to 5.5 V,
SN74ASC21
TA = MIN to MAX
286
pF
1.18
1.72
pF
AN460LH
AN440LH
MAX
TYP
MAX
2.2
2.2
500
20.9
TA - 25°C
Equivalent power
VCC ~ 5 V,
tr - tf - 3 ns,
dissipation capacitance
TA
= 25°C
UNIT
V
348
VI = VCC or 0,
VCC - 5 V,
nA
30
0.12
TYP
Input capacitance
UNIT
,
V
0.12
TA = 25°C
VCC = 5 V,
MAX
2.2
256
TEST CONDITIONS
SN54ASC21
TYP
20.9
VCC - 5 V,
Input threshold voltage
AN420LH
MAX
2,2
Input capacitance
Supply current __'-
Ci
TYP
SN54ASC21
PARAMETER
VT
AN410LH
TEST CONDITIOt'lS
PARAMETER
nA
30
0.12
0.27
pF
2.77
4.58
pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
AN410LH
C
...
PARAMETERt
en
tpHL
I»
I»
tPLH
::r
tPLH
('I)
('I)
...en
tpHL
JltpLH
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A,B,C,D
Y
CL = 0
A,B,C,D
Y
CL = 1 pF
A,B,C,D
JltpHL
Y
SN74ASC21
SN54ASC21
MIN
TYP*
MAX
MIN
TYP*
MAX
0.9
1.9
4.8
1
1.9
4.2
1
1.7
3.8
1
1.7
3.4
1.4
2.9
7.1
1.5
2.9
6.3
1.3
2.3
5.3
1.3
2.3
4.7
0.5
1
2.4
0.5
1
2.2
0.2
0.6
1.5
0.3
0.6
1.4
SN54ASC21
Typt
MAX
MIN
TYP*
MAX
UNIT
ns
ns
nSipF
AN420LH
PARAMETERt
tpLH
FROM
TO
TEST
(INPUT),
(OUTPUT)
CONDITIONS
A,B,C,D
Y
CL = 0
tpHL
tpLH
A,B,C,D
Y
A,B,C,D
Y
tpHL
JltpLH
JltpHL
CL = 1 pF
MIN
SN74ASC21
1
2.1
5.5
1.1
2.1
4.8
1
1.B
4.1
1
1.8
3.7
1.3
2.7
6.7
1.4
2.7
5.9
1.2
2.2
5
1.2
2.2
4.5
0.2
0.6
1.3
0.2
0.6
1.2
0.1
0.4
1
0.1
0.4
0.9
UNIT
ns
ns
nsipF
t Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tPLH '" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
JltpLH '" change in tpLH with load capacitance
JltpHL '" change in tpHL with load capacitance
'Typical values are at VCC = 5 V, TA = 25°C.
4-32
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC21, SN74ASC21
4·INPUT POSITIVE·AND GATES
switching characteristics over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise noted)
AN440LH
PARAMETERt
tplH
tpHl
FROM
TO
TEST
(INPUT)
(OUTPUn
CONDITIONS
A,~,C,D
Y
Cl = 0
tPlH
tpHl
A,8,C,D
Y
AtPlH
AtpHl
A,8,C,D
Y
Cl = 1 pF
SN54ASC21
Typt
MAX
MIN
SN74ASC21
Typt
MAX
1.2
2.7
7.2
MIN
1.3
2.7
6.2
1.1
2.1
5.1
1.2
2.1
4.6
1.4
3
8
1.5
3
6.9
1.2
2.4
5.8
1.3
2.4
5.2
0.1
0.3
0.8
0.1
0.3
0.7
0.1
0.3
0.7
0.1
0.3
0.6
SN54ASC21
Typt
MAX
MIN
UNIT
ns
ns
ns/pF
AN460LH
PABAMETERt
tplH
tpHl
tplH
tPHl
AtplH
FROM
TO
TEST
(INPUT)
(OUTPUn
CONDITIONS
A,8,C,D
A,B,C,D
A,B,C,D
AtPHl
Y
Cl
Y
Cl
=
=
0
1 pF
Y
MIN
1
2.3
5.7
0.9
1.1
1.8
2.5
4
6.3
SN74ASC21
Typt
MAX
1.1
2.3
5
1
1.8
3.6
2.5
1.1
2
4.5
1.2
1.1
2
5.5
4.1
0.1
0.2
0.6
0.1
0.2
0.5
0.09
0.2
0.5
0.1
0.2
0.5
UNIT
ns
ns
ns/pF
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns 110% and 90%).
tplH '" propagation delay time, low-to-high-Ievel output
tpHL
=
propagation delay time, high-to-Iow-Ievel output
A tplH '" change in tplH with load capacitance
AtpHl '" change in tpHl with load capacitance
tTypical.values are at VCC = 5 V, TA = 25°C.
II
...
en
CI)
CI)
~.
en
DESIGN CONSIDERATIONS
Refer to Section 7
...
CO
CO
C
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-33
II
c
....
r.n
:::r
Q)
Q)
CD
CD
....
en
4-34
SN54ASC27, SN74ASC27
3-INPUT POSITIVE-NOR GATES
02939. AUGUST 1986
SystemCell™
2-j.lm INTERNAL STANDARD CELL
logic symbol
•
Choice of Three Performance Levels
•
Specified for Operation Over Vec Range of
4.5 V to 5.5 V
•
Functional Operation Over Vee Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
FUNCTION TABLE
INPUTS
positive logic equation
y
= A+B+C = ABC
A
B
H
OUTPUT
V
X
C
X
X
H
X
L
X
X
H
L
L
L
L
H
L
description
The SN54ASC27 and SN74ASC27 are 3-input positive-NOR gate CMOS standard cells, each implementing
the equivalent of one-third of an SN54LS27 or SN74lS27. The standard-cell library contains three physical
implementations providing the custom IC designer a choice from three performance levels for optimizing
designs. The three options are designated and called from the engineering workstation input using the
following cell names to develop labels for the design netlist:
II
...
FEATURES
CELL NAME
NETLIST
TYPICAL
RELATIVE
HDL LABEL
DELAV
CELL AREA
CL - 1 pF
TO NA210LH
3.2 ns
1.25
2.1 ns
2
1.8 ns
2.75
N0310LH
N0320LH
Label: N03nOLH A,B,e,V;
N0330LH
U)
Q)
Q)
.c:
en
...asas
C
The SN54ASC27 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN74ASC27 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
TEST CONDITIONS
N0310LH
TYP
2.2
TA = 25°C
VT Input threshold voltage
Vee = 5 V,
.lSN54Ase27 Vee - 4.5 V to 5.5 V, VI - Vee or 0,
ICC Supply currentlSN74Ase27 TA = MIN to MAX
ej Input capacitance
0.11
Vee - 5 V,
TA - 25°C
Equivalent power
tr - tf - 3 ns,
Vee - 5 V,
0.32
Cpd dissipation capacitance
TA = 25°C
=::=ir:-t::I~Je ~~-::i:; :.r-=:::~!,,::, nat
TVP
MAX
2.2
156
N0330LH
TVP
MAX
312
14
UNIT
V
2.2
233
9.33
18.7
hA
0.24
0.35
pF
0.56
0.85
pF
Copyright © 1986. Texas Instruments Incorporated
PRODUCTION DATA documents ....tai. information
current as of publication data. Products conform to
spacifications par the tarms of Taxas Instruments
N0320LH
MAX
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-35
SN54ASC27, SN74ASC27
3-INPUT POSITIVE-NOR GATES
switching characteri$tics over recommended ranges of supply voltagt and operating free-air temperjlture
(unless otherwise noted)
N0310LH
PARAMETERt
tPLH
tPHL
tpLH
tPHL
.1tpLH
.1tpHL
FROM
(INPUT)
TO
TEST
(OUTPUTI
CONDITIONS
A,B,C
y
CL = 0
A,B,C
y
CL = 1 pF
A.B.C
y
FROM
(INPUT)
TO
TEST
(OUTPUTI
CONDITIONS
liN64ASC27
MII\!- TV"* MA)!:
0.6
'2.6
1
0.1
1.2
2.1
2
9.5
4
1.3
5.9
2.4
1.4
3
1.2
0:5
6.9
3·9
SN74ASC27
MIN
0.6
0.8
2.2
1.4
TVP*
1
1.2
4
2.4
MAX
2.4
2
8.6
5.2
1.5
0.5
3
1.2
6,3
3.3
UNIT
ns
ns
n~/pF
N0320LH
PARAMETERt
tPLH
tpHL
•
o
....
tpLH
tPHL
.1tpLH
.1tpHL
A,B,C
Y
A.B.C
Y
CL'
CL
=0
= 1 pF
SN64ASC27
TVP*
1
MAX
2.1
0.5
1.1
2.4
1.7
2
5.4
3.5
1.4
0.6
3.4
1.3
1
0.6
A.B.C
Y
FROM
(INPUT)
TO
(OUTPUTI
A.B,C
y
SN74ASC27
MIN
0.6
0.4
1.6
MIN
TVP*
1
1.1
2.4
1.4
1·
1.7
0.7
0.6
0.7
0.4
1.4
0.6
MAX
1.9
1.9
4.9
3.2
3.1
1.4
UNIT
ns
ns
ns/pF
N0330LH
Q)
PARAMETERt
Q)
en
tpLH
(I)
(I)
tPHL
tpLH
(I)
tPHL
.1tpLH
.1tpHL
:r
....
A,B,C
Y
A,B,C
Y
TEST
CONDITIONS
CL =
CL
=
6
1 pF
SN64ASC27
MIl\! TVP* MJ!.X
0.6
1
2
1.9
0.4
1
1.1
0.8
2
1.5
4.3
2.9
0.4
0.3
1
0.5
2.3
1.1
t Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr
tpLH .. propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to·low-Ievel output
.1tpLH '" change in tpLH with load capacitance
.1tpHL '" change in tpHL with load capacitance
Typical values are at VCC = 5 V, T A = 25 ·C.
SN74ASC27
MIN TVP* MAX
(j.6
1
1.8
1
0.5
1.8
1.2
2
3.9
0.8
0.5
0.3
1.5
1
0.5
2.7
2.1
0.9
UNIT
ns
ns
ns/pF
= tf = 3 ns (10% and 90%1.
*
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next lev!!1 of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
4-36
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ASC30. SN74ASC30
8·INPUT POSITIVE·NAND GATES
02939. AUGUST 1986
SystemCenrM
•
•
•
•
2·,.m INTERNAL STANDARD CEll
Choice of Two Performance Levels
logic symbol
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
A
B
Functional Operation Over VCC Range of
2Vt06V
0
E
c
Y
F
Dependable Texas Instruments Quality and
Reliability
G
H
FUNCTION TABLE
positive logic equation
Y
= ABCDEFGH = A+B+C+D+E+F+G+H
INPUTS
OUTPUT
A
B
C
D
E
F
G
H
H
H
H
H
H
H
H
H
L
L
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
Y
X
X
L
X
X
X
X
X
X
X
X
L
X
H
X
X
X
L
H
L
H
•
H
H
H
H
description
The SN54ASC30 and SN74ASC30 are 8-input positive-NAND gate CMOS standard cells each implementing
the equivalent of an SN54LS30 or SN74LS30. The standard-cell library contains two physical
implementations providing the custom IC designer a choice between two performance levels for optimizing
designs. The two options are designated and called from the engineering workstation input using the
following cell names to develop labels for the design netlist:
FEATURES
CELL NAME
NA810LH
NAB20LH
NETLIST
TYPICAL
RELATIVE
HDL LABEL
DELAY
CELL AREA
CL - 1 pF
TO NA210LH
label: NABnOLH A,B,C,D,E,F,G,H,Y;
4.5 ns
2.5
3.3 ns
4.75
The SN54ASC30 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN74ASC30 is characterized for operation from - 40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
=~~:~~i~ai~:I~'Je ~!~~:~i:f ~~O::~:~:t:::'~S not
-1!1
INSTRUMENTS
Copyright © 1986, Texas Instruments Incorporated
TEXAS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-37
SN54ASC30, SN74ASC30
8·INPUT POSITIVE·NAND GATES
electrical characteristics
VT
NA810LH
TEST CONDITIONS
PARAMETER
Input threshold voltage
VCC = 5 V,
VCC = 4.5 V to 5.5 V,
II SN54ASC30
SN74ASC30
TVP
Supply current
Input capacitance
VCC= 5 V,
TA = 25°C
Equivalent power
VCC = 5 V,
tr = tf' = 3 ns,
dissipation capacitance
TA = 25°C
MAX
502
17.4
TA = MIN to MAX
UNIT
V
290
VI = VCC or 0,
ICC
TVP
2.2
2.2
TA = 25°C
Ci
Cpd
NA820LH
MAX
30.1
nA
0.12
0.22
pF
0.61
1.13
pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise notedl
NA810LH
PARAMETERt
tpLH
tpHL
II
C
tPLH
tpHL
t.tpLH
t.tpHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A thru H
V
CL = 0
A thru H
V,
CL = 1 pF
A thw H
V
SN54ASC30
SN74ASC30
MIN
TVP*
MAX
MIN
TVP*
MAX
0.9
1.8
4.2
0.9
1.8
3.7
0.8
1.6
2.3
2
6.5
0.9
2
5.6
3.6
8
5.2
1.7
3.6
7.3
5.3
2.5
5.3
13.1
0.6
1.8
4.9
0.6
1.8
4.7
1.4
3.3
8.7
1.6
3.3
7.5
MAX
MIN
1
TVP*
1.6
3.6
1
TVP*
1.6
0.9
2.1
5.8
1
2.1
5
1.5
2.6
5.7
1.6
2.6
5.3
1.8
4
10.8
2.1
4
9.3
0.4
0.8
1
1.9
2.3
5.1
0.5
0.9
1
1.9
4.4
UNIT
ns
ns
ns/pF
NA820LH
Q)
r+
Q)
PARAMETERt
en
tPLH
::r
CD
CD
tpHL
en
tPHL
tpLH
r+
t.tpLH
t.tpHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A thru H
V
CL = 0
A thru H
V
A thru H
V
CL = 1 pF
SN54ASC30
MIN
SN74ASC30
MAX
3.3
2.1
UNIT
ns
ns
ns/pF
t Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tpLH '" propagation delay time, low-to:high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
t.tpLH '" change in tPLH with load capacitance
t.tpHL '" change in tpHL with load capacitance
t Typical values are at VCC = 5 V, T A = 25°C.
DESIGN CONSIDERATIONS
Refer to Section 7
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
4-38
,TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC32.SN74ASC32
2·INPUT POSITIVE·OR GATES
02939. AUGUST 1986
SystemCell™ 2-ttm
INTERNAL STANDARD CELL
logic symbol
•
Choice of Four Performance Levels
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
FUNCTION TABLE
INPUTS
AI3
OUTPUT
Y
positive logic equation
H
X
H
X
H
H
Y=A+B=AB
L
L
L
description
The SN54ASC32 and SN74ASC32 are 2-input positive-OR gate CMOS standard cells each implementing
the equivalent of one-fourth of an SN54LS32 or SN74LS32. The standard- cell library contains four physical
implementations providing the custom IC designer a choice between four performance levels for optimizing
design. The four options are designated and called from the engineering workstation input using the following
cell names to develop labels for the design netlist:
II
...en
FEATURES
CELL NAME
NETlIST
TYPICAL
HDL LABEL
RELATIVE
DELAY
CELL AREA
CL - 1 pF
TO NA210LH
OR210LH
2.3 ns
1.5
OR220LH
2.1 ns
1.75
1.8 ns
2.6
1.7 ns
3.75
OR240LH
OR260LH
Label: OR2nOLH A,B, Y;
CD
CD
.s:
til
...
CO
CO
Q
The SN54ASC32 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN74ASC32 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
PROOUCTION'OATA documents contei. information
currant IS of publication date. Products conform to
specifications par the terms of Texas Instruments
::~:~i~a{nr:I~7e ~!:~:~ti:.n :'iO=:::~:.s not
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-39
SN54ASC32, SN74ASC32
2·INPUT POSITIVE·OR GATES
electrical characteristics
PARAMETER
VT
Input threshold voltage
ISN54ASC32
VCC = 5 V,
Vec = 4.5 V to 5.5 V,
ISN74ASC32
TA =MIN to MAX
Input capacitance
VCC - 5 V,
TA - 25°C
Equivalent power
VCC = 5 V,
TA = 25°C
tr = tf = 3 ns,
VT
ISN54ASC32
VCC = 5 V,
VCC = 4.5 V to 5.5 V,
ISN74ASC32
TA = MIN to MAX
pF
1.62
pF
TA = 25°C
Equivalent power
VCC = 5 V,
TA = 25°C
tr = tf = 3 ns,
TYP
MAX
461
18.3
UNIT
V
2.2
305
V, = VCC or 0,
VCC = 5 V,
dissipation capacitance
OR260lH
MAX
2.2
TA = 25°C
Input capacitance
nA
0.86
OR240lH
Supply current
13
0.11
TYP
ICC
UNIT
V
217
11.1
Ci
Cpd
2.2
0.11
TEST CONDITIONS
Input threshold voltage
OR220lH
TYP, MAX
185
V, = VCC or 0,
Supply current
dissipation capacitance
MAX
2.2
TA = 25°C
ICC
PARAMETER
\ill
TYP
Ci
Cpd
II
OR210lH
TEST CONDITIONS
27.7
nA
0.22
0.36
pF
3.0S
4.7
pF
switching characteristics .over recommended ranges of supply voltage and operating free·air temperature
(~nless otherwise noted)
OR210LH
c
...
CI)
PARAMETERt
CI)
tplH
en
tPHL
tpLH
::r
CD
CD
...
tPHL
atpLH
VI
atpHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A or B
Y
CL = 0
A or B
y.
A or B
y
CL = 1 pF
SN54ASC32
MIN
SN74ASC32
MAX
MIN
0.6
TYP*
1.3
2.9
0.6
O.S
1.7
3.6
1
1.7
3.3
1.1
2.3
5.2
1.2
2.3
4.8
1.2
2.3
5.2
1.3
2.3
4.6
0.5
1
2.3
0.5
1
2.1
0.2
0.6
1.6
0.3
0.6
1.4
MAX
MIN
3.4
0.8
TYP*
1.5
MAX
0.7
TYP*
1.5
1
1.8
4.2
1
1.8
3.8
TYP*
1.3
MAX
2.7
UNIT
ns
ns
ns/pF
OR220LH
PARAMETERt
tpLH
tpHL
tPLH
tpHL
atpLH
atpHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A or B
Y
CL = 0
A or B
Y
CL = 1 pF
A or B
Y
SN54ASC32
MIN
SN74ASC32
3.2
1
2
4.6
1
2
4.2
1.2
2.2
5.1
1.2
2.2
4.6
0.2
0.5
1.2
0.2
0.5
1.1
0.1
0.4
1
0.2
0.4
O.S
UNIT
ns
ns
ns/pF
tpropagation delay times are measured from the 44% point of V, to 'the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tpLH " propagation delay time, low-to-high-Ievel output
tpHL !!!! propagation delay time, high-to-Iow-Ievel output
atpLH '" change in tPLH with load capacitance
atpHL '" change in tpHL with load capacitance
Typical values are at V CC = 5 V, T A = 25°C.
*
4-40
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN54ASC32. SN74ASC32
2·INPUT POSITIVE·OR GATES
OR240LH
PARAMETERt
tpLH
tpHL
tpLH
tPHL
dtpLH
dtpHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A or B
V
CL
~
~
0
A or B
Y
A or B
Y
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
CL
1 pF
SN54ASC32
SN74ASC32
MIN
TVP*
MAX
MIN
TVP*
0.6
1.4
3.1
0.7
1.4
2.8
0.9
1.7
3.6
0.9
1.7
3.4
0.8
1
1.7
3.7
0.9
1.7
1.9
4.2
1.1
1.9
3.3
3.9
0.1
0.3
0.6
0.1
0.3
0.6
0.1
0.2
0.6
0.1
0.2
0.6
SN54ASC32
Typf
MAX
MIN
TVP*
MAX
3
3.7
0.7
1.4
2.8
0.9
1.6
3.4
3.1
MAX
UNIT
ns
ns
ns/pF
OR260LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
dtpLH
dtpHL
A or B
Y
A or B
Y
A or B
CL
CL
~
~
0
1 pF
Y
MIN
SN74ASC32
0.6
1.4
0.9
1.6
0.7
1.6
3.4
0.8
1.6
1
1.8
4.1
1
1.8
3.7
0.1
0.2
0.2
0.5
0.1
0.2
0.5
0.09
0.2
0.4
0.4
0.07
UNIT
ns
ns
ns/pF
tPropagatian delay times are measured from the 44% point of VI to the 44% point of Vo with tr ~ tf ~ 3 ns (10% and 90%1.
tpLH '" propagation delay time, law-ta-high-Ievel output
tpHL '" propagation delay time, high-to-I ow-level output
dtPLH '" change in tpLH with load capacitance
dtpHL '" change in tpHL with load capacitance
*Typical values are at Vce ~ 5 V, TA ~ 25°C.
II
...
tI)
CD
CD
..c:
til
...
CU
CU
DESIGN. CONSIDERATIONS
C
Refer to Section 7
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-41
4-42
SN54ASC74. SN74ASC74
O-TYPE POSITIVE-EOGE-TRIGGEREO FLIP-FLOPS
D2939, AUGUST 1986
SystemCell™
2-Jtm HARDWIRED MACRO CELLS
a and az
•
All Cells Provide Complementary
Outputs
•
Choice between Two Relative Output Drive
Capabilities
•
Choice of Asynchronous Inputs Provides
Custom Cell for Most Applications
•
Implements High-Speed Registers: Clock
Frequencies ... 46 to 69 MHz
FLIP-FLOP CEll CONFIGURATIONS OFFERED
DRIVE
CEll NAME
PRESET
DFB20lH
Ves
Ves
2X
DFC20lH
No
Ves
2X
DFN20lH
No
No
2X
DFP20lH
Ves
No
2X
DFV20lH
Ves
No
2X
DFZ20lH
Ves
Ves
2X
DTB10lH
Ves
Ves
1X
DTC10lH
No
Ves
1X
DTN10lH
No,
Ves
No
1X
No
1X
DTP10lH
CLEAR
lEVEL
description
The SN54ASC74 and SN74ASC74 are dedicated, hardwired st<:mdard-c<;il maCros i:nplemcn::;~;; va;icu~
D-type flip-flops. The' ASC74 cell selection offers a broad choice of flip-flop configurations, providing the
custom IC designer with specific storage elements to embed in ASICs in their most efficient form: as standalone bit-storage devices or as additions to larger synchronous functions such as registers or counters,
The DFB20LH and DTB10LH flip-flops are identical in function and sequential operation to one-half of the
'LS74, 'S74, or 'F74 packaged flip-flops.
II
...
en
Q)
Q)
The other nine cells provide the designer with flip-flop versions having either a preset or clear or no
asynchronous input.
.I:
en
The DFY20LH and DFZ20LH cells feature grounded D inputs meaning that they can simplify implementation
of flag registers that can be reset to zero with a system clock. The DFZ20LH offers asynchronous clear
and preset inputs providing an option to zero the register with either the system clock or system clear
signal, or both.
...caca
C
FEATURES
CEll NAME
NETLIST
MAXIMUM
RELATIVE
HDl lABEL
CLOCK
CEll AREA
FREQUENCY
TO NA210lH
DFB20lH
label: DFB20lH ClRZ, PREZ, D, elK, Q, QZ;
46.3 MHz
7.7
DFC20lH
label: DFC20lH ClRZ, D, ClK, Q, QZ;
52.1 MHz
7.2
DFN20lH
label: DFN20lH D, elK, Q, QZ;
DFP20lH
6.5
7
DFV20lH
label: DFP20lH PREZ, D, elK, Q, QZ;
label: DFV20lH PREZ, elK, Q, QZ;
64.2 MHz
55.8 MHz
69.2 MHz
5.7
DFZ20lH
label: DFZ20lH ClRZ, PREZ, elK, Q, QZ;
59.2 MHz
6.5
DTB10lH
label: DTB10lH ClRZ, PREZ, D, ClK, Q, QZ;
label: DTC10lH ClRZ, D, ClK, Q, QZ;
55.8 MHz
6.5
DTC10lH
52.1 MHz
6
DTN10lH
DTP10lH
label: DTN10lH D, elK, Q, QZ;
label: DTP10lH PREZ, D, elK, Q, QZ;
55.8 MHz
55.8 MHz
5.2
6
The SN54ASC74 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN74ASC74 is characterized for operation from -40°C to 85°C,
PROOUCTION DATA documents contain information
curreRt as of publicati.n data. Products ~onform to
specifications per the terms of Taxas Instruments
:'~~~:~~i~ar=l~lJe ~!sO:i~~i:; :,~D::~:::~:'~ not
Copyright
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
© 1986,
Texas Instruments Incorporated
4-43
SN54ASC74. SN74ASC74
D·TYPE POSITIVE· EDGE·TRIGGERED FLlP·FLOPS
logic symbols
FUNCTION TABLES
DFB20LH; DTB10LH
DFB20lH. DTB10lH
INPUTS
P R E Z i ], = S a
ClK .
C1
o
10
ClRZ
R
az
CLRZ
CLK
l
H
H
l
L
H
L
H
H
H
X
X
X
i
i
H
H
L
CLRZ
CLK
L
H
X
i
i
H
L
10
R .
az
H
o--U-
C/)
::T
CD
CD
az
en
H
L
L
L
H
X
00
00
L
H
H
L
L
H
00
00
OUTPUTS
0
Q
QZ
i
i
H
H
L
L
L
H
L
X
00
00
DFP20LH. DTP10LH
PREZ
CLK
L
H
X
i
i
H
L
H
OUTPUTS
Q
QZ
0
X
H
L
L
.H
L
H
X
00
00
H
l
DFY20LH
DFY20LH
INPUTS
PREZ
CLK
PREz-n-a
----t:J--
X
i
H
H
L
L
H
H
L
00
00
L
az
OUTPUTS
Q
QZ
* This configuration is nonstable; that is, it will not persist when PREZ or CLRZ returns to its inactive (high) level.
4-44
L·
OUTPUTS
Q
QZ
INPUTS
n a
ClK
C1
az
o
10
ClK
H
CLK
DFP20LH. DTP10LH
PREZ
r+
H
0
X
H
L
X
INPUTS
ClK--Fl-- a
c
l
L
L·
QZ
Q
DFN20LH.DTN10LH
DFN20LH.DTN10LH
S»
r+
S»
H
INPUTS
ClKB=1· a
ClRZ
0
X
X
X
DFC20LH.DTC10LH
DFC20LH. DTC10LH
o
OUTPUTS
PREZ
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 ,. DALLAs. TEXAS 75265
SN54ASC74. SN74ASC74
O·TYPE POSITIVE·EOGE·TRIGGEREO FLIP-FLOPS
logic symbol
FUNCTION TABLE
OFZ20lH
OFZ20lH
INPUTS
PREZEa
CLK
R
CLRZ
az
R
* This configuration is nonstable; that is, it will not
p~rsist
OUTPUTS
PREZ
ClRZ
ClK
Q
l
H
X
H
L
H
l
X
l
H
QZ
l
L
X
H
H
t
L'
l
L'
H
H
H
l
00
00
when PREZ or CLRZ returns to its inactive (high) level.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
OFB20lH
fclock
tw
Pulse duration
th
MAX
MIN
MAX
0
46.3
0
52.1
0
64.2
Setup time
Hold time
MHz
ns
10.8
9.6
CLRZ inactive
7.8
6.6
PREZ inactive
o high or low
1.2
6.6
6.6
ClRZ low
1.2
0.6
PREZ low
3
o high or low
UNIT
6.6
7.8
ClK high or low
tsu
MIN
7.2
PREZ low
OFN20lH
MAX
Clock frequency
ClRZ low
OFC20lH
MIN
ns
4.8
...ca
ctI
2.4
1.8
CI)
CI)
.s::
tJ)
ns
2.4
II
...
CI)
7.8
C
OFP20LH
fclock
MIN
MAX
0
55.8
Clock frequency
OFY20lH
MIN
MAX
0
69.2
ClRZ low
tw
Pulse duration
OFZ20lH
MIN
MAX
0
59.2
UNIT
MHz
7.2
PREZ low
7.2
7.2
7.8
9
7.2
8.4
1.2
1.2
1.2
ns
1.8
3
ns
ClK high or low
ns
CLRZ inactive
tsu
Setup time
PREZ inactive
o high
or low
6
ClRZlow
th
Hold time
PREZ low
o high
2.4
or low
3
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-45
SN54ASC74. SN74ASC74
O-TYPE POSITIVE-EOGE-TRIGGEREO FLIP-FLOPS
timing requirements over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (continued)
DTB10lH
fclock
tw
Clock frequency
Pulse duration
tsu
th
Setup time
Hold time
MAX
0
55.8
ClRZ low.
13.8
PREZ low
18.6
ClK high or low
DTC10lH
MIN
DTP10lH
MAX
MIN
MAX
MIN
MAX
0
52.1
0
55.8
0
55.8
UNIT
MHz
10.8
20.4
ClRZ inactive
9
0.6
PREZ inactive
-1.8
o high or low
3
6
ClRZ low
16.2
12.6
PREZ low
21
o high or low
DTN10lH
MIN
9.6
0.6
9
4.8
ns
9
-2.4
ns
4.2
22.2
2.4
3
2.4
ns
2.4
electrical characteristics
DFB20LH
PARAMETER
II
TEST CONDITIONS
VT
Input threshold voltage
ICC
Supply current
TA
-
Ci
PREZ
Input capacitance
0
ClK
Q)
en
::s(I)
c:
TA - 25°C
Cpd
SN74ASC74
TYP
TYP
MAX
2.2
V, - VCC or O.
0.36
VCC
= 5 V,
Equivalent power
VCC - 5 V,
dissipation capacitance
TA
= 25°C
TA
tr - tf - 3 ns,
= 25°C
MAX
2.2
934
= MIN to MAX
ClRZ
cQ)
(I)
VCC - 5 V.
VCC - 4.5 V to 5.5 V.
SN54ASC74
UNIT
V
56
nA
0.36
0.38
0.38
0.11
0.11
0.25
0.25
3.76
3.76
pF
pF
DFC20LH
PARAMETER
TEST CONDITIONS
VT
Input threshold voltage
ICC
Supply current
TA
I
Ci
Cpd
Input capacitance
VCC = 5 V,
VCC - 4.5 V to 5.5 V,
I
I
TA - 25°C
SN74ASC74
TYP
TYP
VCC
= 5 V,
= 25°C
TA
Equivalent power
VCC - 5 V,
dissipation capacitance
TA
tr - tf - 3 ns,
= 25°C
MAX
2.2
881
= MIN to MAX
ClK
MAX
2.2
V, - VCC or 0,
ClRZ
0
SN54ASC74
V
52.9
0.36
0.36
0.11
0.11
0.28
0.28
3.39
3.39
UNIT
nA
pF
pF
DFN20LH
PARAMETER
VT
Input threshold voltage
ICC
Supply current
Ci
Cpd
4-46
Input capacitance
SN54ASC74
TEST CONDITIONS
VCC = 5 V,
VCC - 4.5 V to 5.5 V,
= MIN to MAX
VCC = 5 V,
TYP
TA
= 25°C
2.2
V, - Vec or 0,
:
~lK
dissipation capacitance
VCC - 5 V,
TA = 25°C
= 25°C
- tf = 3 ns,
TA
tr
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. teXAS 15265
SN74ASC74
TYP MAX
2.2
799
TA
Equivalent power
MAX
V
47.9
0.13
0.13
0.27
0.27
2.71
2.71
UNIT
nA
pF
pF
SN54ASC74. SN74ASC74
O·TYPE POSITIVE·EOGE·TRIGGEREO FLlp·FLOPS
electrical characteristics'
DFP20LH
PARAMETER
TEST CONDITIONS
VT
Input threshold voltage
lee
Supply current
ei
epd
Input capacitance
Vee = 5 V,
TA =.25°C
Vee - 4.5 V to 5.5 V,
VI - Vee or 0,
SN54ASC74
SN74ASC74
TVP
TYP
2.2
0.35
Vee = 5 V,
TA = 25°e
I elK
Equivalent power
Vee = 5 V,
dissipation capacitance
TA = 25°e
tr = tf = 3 ns,
MAX
2.2
845
TA = MIN to MAX
I PREZ
ID
MAX
UNIT
V
50.7
r. .'~
0.35
0.13
0.13
0.26
0.26
3.49
3.49
pF
pF
DFY20LH
PARAMETER
TEST CONDITIONS
VT
Input threshold voltage
lee
Supply current
ei
epd
Vee - 5 V,
TA - 25°e
Vee - 4.5 V to 5.5 V,
VI - Vee or 0,
SN74ASC74
TYP
TYP
Vee = 5 V,
TA = 25°e
Vee = 5 V,
tr = tf = 3 ns,
dissipation capacitance
TA = 25°e
MAX
2.2
MAX
2.2
702
TA = MIN to MAX
I PREZ
I elK
Equivalent power
Input capacitance
SN54ASC74
V
42.1
0.35
0.35
0.25
0.25
4.63
4.63
UNIT
nA
pF
pF
I/)
Q)
Q)
DFZ20LH
.s::::
PARAMETER
TEST CONDITIONS
VT
Input threshold voltage
lee
Supply current
ei
Input capacitance
Vee = 5 V,
TA = 25°e
Vee - 4.5 V to 5.5 V,
VI - Vee or 0,
SN54ASC74
SN74ASC74
TYP
TYP
I
I
Vee = 5 V,
TA = 25°e
Equivalent power
Vee = 5 V,
dissipation capacitance
TA = 25°e
tr = tf = 3 ns,
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
MAX
2.2
777
0.25
elRZ
PREZ
MAX
2.2
TA = MIN to MAX
I elK
epd
•-
UNIT
V
46.6
nA
en
CO
CO
C
0.25
0.23
0.23
0.36
0.36
4.94
4.94
pF
pF
4-47
SN54ASC74, SN74ASC74
O·TYPE POSITIVE·EOGE·TRIGGERED FLlP·FLOPS
electrical characteristics
DTB10LH
PARAMETER
TEST CONOITIONS
VT
Input threshold voltage
ICC
Supply current
ej
Input capacitance
Vee = 5 V,
Vce - 4.5·V to 5.5 V,
TA = 25°C
SN74ASC74
TYP
TYP
MAX
2.2
VI - Vee or 0,
TA = MIN to MAX
0.12
0.12
0.18
0.18
0.20
0.20
0.14
0.14
2.12
2.12
Vee = 5 V,
TA = 25°C
Equivalent power
Vee - 5 V,
dissipation capacitance
TA = 25°C
tr - tf - 3 ns,
UNIT
V
41.9
PREZ
0
MAX
2.2
699
CLRZ
eLK
Cpd
SN54ASC74
nA
pF
pF
DTC10LH
PARAMETER
II
TEST CONDITIONS
VT
Input threshold voltage
ICC
Supply current
Vee - 5 V,
4.5 V to 5.5 V,
Vee
TA - 25°C
VI
Input capacitance
TYP
10
1 eLK
dissipation capacitance
MAX
2.2
0.11
Vee = 5 V,
TA = 25°C
tr - tf - 3 ns,
Vee - 5 V,
TA = 25°C
MAX
2.2
641
TA'= MIN to MAX
Equivalent power
epd
SN74ASC74
TYP
Vee or 0,
LeLRZ
ej
SN54ASC74
UNIT
V
38.5
nA
0.11
0.19
0.19
0.08
0.08
2.1
2.1
pF
pF
DTN10LH
TEST CONDITIONS
PARAMETER
VT
Input threshold voltage
Vee = 5 V,
TA = 25°C
ICC
Supply current
Vee - 4.5 V to 5.5 V,
TA = MIN to MAX
VI - Vee or 0,
ej
Input capacitance
Vee = 5 V,
TA = 25°C
Equivalent power
Vee - 5 V,
tr - tf - 3 ns,
dissipation capacitance
TA = 25°C
epd
4·48
10
I eLK
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC74
SN74ASC74
TYP
TYP
MAX
2.2
MAX
544
32.6
0.10
0.10
0.11
0.11
2.21
2.21
UNIT
V
2.2
nA
pF
pF
SN54ASC74. SN74ASC74
O·TYPE POSITIVE·EOGE·TRIGGEREO FLlp·FLOPS
DTP10LH
PARAMETER
VT
ICC
TEST CONDITIONS
Input threshold voltage
Supply current
VCC = 5 V,
VCC - 4.5 V to 5.5 V,
TA
=
TA
=
Input capacitance
tD
VCC
VI - VCC or 0,
5 V,
TA
=
25°C
Equivalent power
VCC - 5 V,
dissipation capacitance
TA
0.19
0.14
0.11
0.11
2.5
2.5
t r - tf - 3 ns,
UNIT
V
38.3
0.19
25°C
MAX
2:2
638
MIN to MAX
=
=
TVP
MAX
2.2
I ClK
Cpd
SN74ASC74
TVP
25°C
I PREZ
Ci
SN54ASC74
nA
pF
0.14
pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
DFB20LH
PARAMETERt
FROM
TO
TEST
IINPUT)
10UTPUT)
CONDITIONS
SN74ASC74
SN54ASC74
MAX
MIN
TVP*
MAX
2.1
TVP*
4.9
12.7
2.3
4.9
11.1
1.4
1.9
3.2
3.9
8.2
1.6
3.2
7.2
9.3
2
3.9
8.3
tpHl
1.1
2
4.2
1.1
2
3.8
tpLH
2.4
5.4
13.9
2.6
5.4
12.2
1.6
3.6
9.2
1.8
3.6
8.1
2.2
4.4
10.6
2.3
4.4
9.4
tplH
tpHl
tpLli
tpHi.
tPlH
tpHl
.o.tplH
.o.tpHl
ClK
Q,QZ
Cl = 0
PREZ,ClRZ
ClK
Q,QZ
Q,QZ
Cl = 1 pF
PREZ,ClRZ
Any
Q,QZ
Q,QZ
MIN
1.3
2.4
5.2
1.3
2.4
4.7
0.2
0.5
1.3
0.4
1
0.5
0.4
1.2
0.1
0.2
0.1
0.9
UNIT
ns
ns
ns
ns
nsipF
fpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns 110% and 90%),
tplH '" propagation delay time, low-to-high-Ievel output
tpHl .. propagation delay time, high-to-Iow-Ievel output
.o.tplH '" change in tPlH with load capacitance
.o.tpHl '" change in tPHl with load capacitance
*Typical values are at VCC = 5 V, TA = 25°C.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
II
...
fI)
Q)
Q)
.c:
en
...
CO
CO
C
4-49
SN54ASC74. SN74ASC74
D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
DFC20LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
tPLH
tpHL
tPLH
tpHL
dtplH
dtpHl
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
CLK
a,QZ
CLRZ
QZ
a
CLK
CLRZ
CL = 0
a,az
CL = 1 pF
az
a
SN54ASC74
TYpt MAX
MIN
a,az
FROM
TO
(OUTPUT)
4.5
10.7
1.9
3
3.5
5.7
7.2
1.9
4.5
12.2
1.4
7.9
1.8
3
3.5
2
1.5
8.1
1
1.8
3.9
1.1
1.8
3.6
2.1
5
13.4
2.3
5
11.8
1.5
3.4
8.8
1.7
3.4
7.7
2.1
4
9.3
2.2
4
8.3
1.2
2.2
0.5
4.9
1.3
1.3
0.2
2.2
0.5
4.4
0.4
1
0.1
0.4
0.8
SN54ASC74
TYpt
MAX
MIN
0.2
0.1
Any
SN74ASC74
Tvpt
MAX
MIN
1.1
UNIT
ns
ns
ns
ns
ns/p'F
DFN20LH
PARAMETERt
III
tpLH
tPHL
tplH
tpHL
dtpLH
dtpHL
(INPUT)
CLK
CLK
CLK
a,QZ
TEST
COND(TIONS
Cl
a,QZ
CL
=0
=
1 pF
a,az
MIN
1.7
SN74ASC74
TVPt
MAX
3.7
9.5-
1.8
1.2
2.6
2.6
5.9
4.2
2.1
4.2
9.4
1.4
0.2
3
0.5
6.6
10.7
7.5
1.3
1.9
1.5
6.7
0.1
0.4
3
0.5
0.4
0.9
0.2
0.1
SN54ASC74
TVpt
MAX
MIN
1.2
3.7
8.4
1.1
0.8
UNIT
ns
ns
ns/pF
DFP20LH
PARAMETERt
tpLH
tpHL
tplH
tpHL
tPlH
tPHL
tpLH
tPHL
dtplH
dtpHL
FROM
(INPUT) .
ClK
PREZ
TO
TEST
(OUTPUT)
CONDITIONS
a,QZ
a
az
ClK
a,QZ
PREZ
a
QZ
Any
a,az
CL
CL
=0
=
1 pF
MIN
SN74ASC74
TVpt
MAX
1.8
4,3
12
1.9
4.3
9.6
1.3
1.7
3
3.3
7.8
1.4
7.7
1.8
3
3.3
6.9
6.9
1.1
2
4.1
1.2
2
3.8
2
4.8
13.2
2.2
4.8
11.6
1.5
3.4
8.7
1.6
3.4
7.6
2
3.8
8.9'
2.1
3.8
7.9
1.3
0.2
0.1
2.4
0.5
5
1.3
1.3
0.2
2.4
0,5
4.5
1.1
0.4
1
0.1
0.4
0.8
UNIT
ns
ns
ns
ns
ns/pF
t Propagation delay times are measured from the 44% pOint of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tPLH .. propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
dtpLH '" change in tPlH with load capacitance
AtPHL " change in tPHL with load capacitance
*Typical values are at VCC = 5 V, TA = 25°C.
4-50
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC74, SN74ASC74
O·TVPE POSITIVE·EOGE·TRIGGEREO FLlp·FLOPS
switching characteristics over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise noted)
DFY20LH and DFZ20LH
PARAMETERt
tplH
tpHl
tplH
tpHl
tplH
tpHl
tplH
tpHl
dtplH
FROM
(INPUT)
ClK
TO
(OUTPUT I
Q,QZ
Cl
PREZ,ClRZ§
Q,QZ
ClK
Q,QZ
Cl
PREZ,ClRZ§
Q,QZ
Any
Q,QZ
FROM
(lNPUTI
TO
(OUTPUT)
SN54ASC74
TEST
CONDITIONS
~
~
a
1 pF
dtpHl
SN74ASC74
MIN
TYP*
MAX
MIN
TYP*
MAX
1.8
1.2
1.6
1.1
2
1.3
1.8
1.2
0.2
0.1
4.3
2.6
3.6
1.9
4.8
3
4.1
2.3
0.5
0.4
11.7
6.6
9.7
4.1
12.8
7.6
10.8
5.1
1.3
1
1.9
1.2
1.9
1.1
2.2
1.4
1.9
1.3
0.2
0.1
4.3
2.6
3.6
1.9
4.8
3
4.1
2.3
0.5
0.4
10.3
5.9
8.5
3.8
11.3
6.8
9.6
4.6
1.1
0.9
SN54ASC74
MIN TYP*
MAX
MIN
TYP*
MAX
1.6
1.8
2.2
0.9
2.1
2
3.1
3.5
4.2
1.4
4
3.8
2.2
2.4
2.8
1.5
2.8
2.6
0.5
0.6
0.5
0.6
4.1
4.8
5.2
2.7
5.3
4.8
1
1.3
1
1.3
0.5
0.7
1
1.3
6.8
7.9
9.1
2.7
8.3
7.9
8.9
10.6
11.2
5.4
11.3
9.9
2.2
2.9
2.2
2.8
2.1
3.1
UNIT
ns
ns
ns
ns
ns/pF
DTB10LH
PARAMETERt
tPlH
tpHl
tplH
iPHl
tpHl
tPlH
tPlH
tPHl
tplH
tpHl
tpHl
tplH
dtPlH
dtpHl
dtPlH
dtpHl
dtPlH
dtpHl
ClK
TEST
CONDITIONS
Q,QZ
Q
PREZ
ClRZ
ClK
PREZ
ClRZ
QZ
Q
~
Cl
a
QZ
Q,QZ
Q
QZ
Q
CL
~
1 pF
QZ
ClK
Q,QZ
PREZ
Q,QZ
ClRZ
Q,QZ
1.5
1.6
2.1
0.8
2
1.9
2
2.2
2.6
1.4
2.6
2.4
0.4
0.5
0.5
0.5
0.5
0.6
3.1
3.5
4.2
1.4
4
3.8
4.1
4.8
5.2
2.7
5.3
4.8
1
1.3
1
1.3
1
1.3
7.7
8.9
10.1
2.9
9.3
8.9
9.9
12
12.5
6.1
12.7
11.1
2.5
3.4
2.4
3.2
2.2
3.5
SN74ASC74
UNIT
ns
ns
ns
ns
ns
II
I/)
.....
Q)
Q)
.r:.
en
co
.....
co
C
ns
ns/pF
ns/pF
ns/pF
t Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tpLH == propagation delay time, low-to-high-Ievel output
tpHL == propagation delay time, high-to-low~level output
atpLH == change in tpLH with load capacitance
AtpHL == change in tPHL with load capacitance
'Typical values are at VCC ~ 5 V, TA ~ 25°C.
§ ClRZ does not apply for the DFY20lH.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-51
SN54ASC74,SN74ASC74
D·TYPE POSITIVE·EDGE·TRIGGERED FLlp·FLOPS
switching characteristiCs over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise noted)
DTC10LH
PARAMETERt
tPlH
tpHl
tplH
tpHl
tplH
tpHl
tplH
tpHl
AtPlH
AtpHl
AtPlH
AtPHl
II ' ' 'OLH
PARAMETERt
tPlH
tpHl
tPlH
tpHl
AtplH
AtpHl
C
...
I»
I»
tn
:r
FROM
(lNI>UTI
TO
(OUTPUTI
ClK
a,az
ClRZ,
TEST
CONDITIONS
Cl
az
a
=0
ClK
a,az
ClRZ
az
a
ClK
a,az
ClRZ
a,az
FROM
(INPUT)
·TO
(OUTPUT)
TEST
CONDITIONS
elK
a,az
Cl = 0
elK
a,az
Cl = 1 pF
ClK
a,az
FROM
(INPUT)
TO
(oUTPUT)
ClK
a,az
Cl
= 1 pF
SN54ASC74
MIN TYP* MAX
1.5
3.2
8.4
1.5
3.3
8.4
2.4
4.9
12
2.2
4.5
10.6
4.2
10.6
2
2.1 ' 4.6
11.5
2.9
5.9
14.1
2.9
6 14.3
0.5
2.4
1
0.5
1.3
3.3
0.4
1
2.2
0.7
1.5
3.7
SN74ASC74
MIN TYP* MAX
1.6
3.2
7.5
1.7
3.3
7.5
2.6
4.9
10.6
2.4
4.5
9.4
2.1
4.2
9.5
2.3
4.6
10.2
3.1
5.9
12.6
3.1
12.7
6
0.5
1
2.2
0.6
1.3
2.9
0.5
1
2
0.7
1.5
3.3
SN54ASC74
MIN TVP* MAX
1.5
3.2
8.1
1.5
3.3
8.1
2
4.2
10.3
2.1
4.6
11.1
0.4
1
2.4
0.5
1.3
3.3
SN74ASC74
MIN TVP* MAX
1.6
3.2
7.2
1.7
3.3
7.2
2.i
4.2
9.2
2.3
4.6
9.8
1
0.5
2.2
0.6
1.3
2.9
SN54ASC74
MIN TVI>* MAX
1.5
7.2
3.2
1.6
3.5
9.1
2.4
4.9
11.7
0.9
1.4
3
2
4.2
9.5
2.2
4.8
12.3
2.9
5.9
14.1
1.5
2.7
6.2
0.5
1
2.5
0.5
1.3
3.2
0.5
1
2.5
0.5
1.3
3.2
SN74ASC74
MIN TVP* MAx
1.6
3.2
6.5
1.7
3.5
8.1
2.6
4.9
10.4
0.9
1.4
2.8
2.2
4.2
8.5
2.3
4.8
10.8
3.1
5.9
12.6
5.5
1.6
2.7
0.5
1
2.3
0.6
1.3
2.8
0.5
1
2.2
0.6
1.3
2.8
UNIT
ns
ns
ns
ns
ns/pF
ns/pF
,UNIT
ns
ns
ns/pF
CD
!
en
DTP10LH
PARAMETERt
tplH
tpHl
tPlH
tpHl
tPlH
tpHl
tPlH
tpHl
AtplH
AtpHl
AtplH
AtpHl
PREZ
a
az
ClK
a,az
PREZ
a
az
ClK
a,az
PREZ
a,az
TEST
CONDITIONS
Cl = 0
Cl = 1 pF
UNIT
ns
ns
ns
ns
ns/pF
ns/pF
tpropagation,delay times are measured from the 44% point of VI to,the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tPlH .. propagation delay time, low-to-high-Ievel outpUt
tpHl '" propagation delay time, high-to-Iow-Ievel output
AtplH .. change in tplH with load capacitance
AtpHl .. change in tPHl with load capacitance
Typical values are at Vce = 5 V, TA = 25 ·C.
*
4-52
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC74, SN74ASC74
D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
DESIGN CONSIDERATIONS
interfacing the macro
Inputs and outputs of these dedicated macros are compatible for interfacing directly with cells and macros
available in the TI standard cell library. The inputs can be driven by either noninverting or inverting input
cells when interfacing off-chip for the input data. The outputs can be interfaced to drive off-chip loads
with any of the non inverting output buffers or interfaced to external bidirectional buses through a threestate input/output TTL/CMOS buffer.
designing for testability
Designs employing storage or bistable elements should consider testability of the design in its final form.
The need to preset or clear these elements should be assessed throughout the development of custom
logic circuits with these considerations extended to the end-equipment application with respect to
maintainability. Simple actions on the part of the ASIC designer can result in considerable cost savings
allowing the expense of IC testing, system testing, and system maintenance to be reduced significantly.
power-up clear/preset
Standard cell storage elements containing the capability to be asynchronously either preset or cleared may
be connected to an SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Access to the clear or preset inputs from other system signals in conjunction with the power-up clear can •
be implemented with an AND gate.
...en
G)
G)
..c
en
...asas
C
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-53
•
C
I»
r+
I»
CJ)
:::r
CD
CD
r+
UI
4-54
SN54ASC75, SN74ASC75
O-TYPE LATCHES WITH ACTIVE-HIGH ENABLE
02939, AUGUST 1986
SystemCelr
M
2-/-lm HARDWIRED MACRO CELL
•
Provides Complementary Q and QZ Outputs
•
Choice Between Two Relative Output Drive
Capabilities
•
Implements Control/Status· Registers
•
Parallel Latches to Implement Wide Word
Widths
logic symbol
0,10
1--0
C~~_C_1______~~OZ
FUNCTION TABLE
description
INPUTS
OUTPUT
0
C
0
QZ
L
H
H
L
H
H
L
H
The SN54ASC75 and SN74ASC75 are
X
L
00
00
dedicated, hard-wired standard-cell macros
'implementing D-type latches, The 'ASC75
latches offer two choices of individual latch configurations providing the custom IC designer storage
elements to embed in ASICs in their most efficient form, The LAH20LH and LAH10LH latches implement
identical function and sequential operation to one-fourth of the 'LS75 packaged latches, except that the
'ASC75 enable (C) input is individually available for custom design, The LAH20LH provides twice the drive
capability as the LAH 1OLH element.
Information present at the data input is transferred to the Q output when the enable input is high, and
the Q output will follow the data input as long as enable remains high, When enable goes low, the data
that was present at the data input at the time the transition occurred is retained at the Q output until enable
is taken high, The cells are designated and called from the engineering workstation input using the following
cell names to develop labels for the design netlist:
CELL NAME
LAH10LH
LAH20LH
NETLIST
...
CI)
CD
CD
.c
en
...caca
RELATIVE
CELL AREA
HOL LABEL
•
C
TO NA210LH
5
4.5
Label: LAHnOLH D,C,Q,QZ:
The SN54ASC75 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN74ASC75 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2,
PRODUCTION DATA documlnts contein information
currant as of publication date. Products conform to
BpIIcifil:atioRs par the terms of Taxas Instruments
:~~=~~i~'i~:I~~ ~=:~i:r :'~D=:::~;:S not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1986, Texas Instruments Incorporated
4-55
SN64ASC76, SN74ASC76
D·TYPE LATCHES WITH ACTIVE·HIGH ENABLE
timing requirements over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise noted)
LAH10LH
MIN
tw
tsu
th
LAH20LH
MIN
6
6
Pulse duration
I e high
I e low
Setup time, 0 high or low
Hold time, 0 high or low
4.8
ns
4.8
6
0
6
0
UNIT
ns
ns
electrical characteristics
LAH10LH
PARAMETER
VT
Input threshold voltage
lee
Supply current
ei
epd
Input capacitance
Ie
10
Equivalent power
dissipation capacitance
TEST CONDITIONS
Vee - 5 V,
TA - 25°e
Vee = 4.5 V to 5.5 V, VI = Vee or 0,
TA = MIN to MAX
vee
=
5 V,
Vee = ,5 V,
TA = 25°e
TA
=
25°e
tr = tf = 3 ns,
SN54ASC75
TYP
MAX
2.2
SN74ASC75
TYP
MAX
2.2
463
27.8
UNIT
V
nA
0.21
0.26
0.21
0.26
pF
2
2
pF
LAH20LH
PARAMETER
VT
Input threshold voltage
lee Supply current
ei
epd
4-56
Input capacitance
Ie
10
Equivalent power
dissipation capacitance
SN54ASC75
TEST CONDITIONS
TYP
TA = 25°C
Vee = 5 V,
Vee - 4.5 V to 5.5 V, VI - Vee or 0,
TA = MIN to MAX
= 25
Vee = 5 V,
TA
Vee = 5 V,
TA = 25°e
tr = tf = 3 ns,
0
e
TEXAS •
INSTRUMENTS
POST OFFICE BOX 856012 • DALLAS, TEXAS 75266
MAX
2.2
SN74ASC75
TYP
MAX
2.2
528
0.22 '
31.7
UNIT
V
nA
0.25
0.22
0.25
pF
2.81
2.81
pF
SN54ASC75, SN74ASC75
O·TYPE LATCHES WITH ACTlVE·HIGHENABLE
switching characteristics over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise noted)
LAH10LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tPLH
tpHL
tPLH
tPHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
6tpLH
6tpHL
FROM
TO
TEST
IINPUT)
(OUTPUTI
CONDITIONS
C
Q
C
QZ
CL
D
Q
D
QZ
C
Q
C
°
QZ
CL
0
=
=
1 pF
Q
0
QZ
Any
Q,QZ
SN54ASC75
Typt
MAX
MIN
SN74ASC75
Typt
MAX
MIN
1
2.1
4.8
1.1
1.6
4
0.7
2.1
1.6
4.3
0.6
0.9
2.1
5.1
1
2.1
4.6
1.4
2.8
6.4
1.5
2.8
5.8
0.8
1.6
3.6
0.8
1.6
3.3
1
1.6
3.6
1
1.6
3.3
1.2
2.1
4.7
1.2
2.1
4.2
1.1
2.3
5.3
1.1
2.3
4.7
3.7
1.5
3.1
7
1.7
3.1
6.3
0.9
2.2
5.5
1
2.2
4.9
1.4
3.1
7.4
1.5
3.1
6.7
1.6
3.4
7.9
1.8
3.4
7
1.3
2.6
5.9
1.4
2.6
5.3
1.2
5
7
1.3
1.8
2.2
3.1
4.5
1.7
2.2
3.1
1.3
2.9
6.8
1.4
2.9
6
0.4
1
2.3
0.5
1
2.1
0.2
0.6
1.5
0.2
0.6
1.3
6.3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns/pF
PARAMETERt
tpLH
tpHL
tPLH
tpHL
tPLH
tpHL
tPLH
tPHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tPLH
tPHL
6tpLH
6tpHL
•
...en
CD
CD
LAH20LH
FROM
TO
TEST
IINPUT)
(OUTPUTI
CONDITIONS
C
Q
C
QZ
CL =
0
Q
0
QZ
C
Q
C
QZ
°
CL = 1 pF
0
Q
0
QZ
Any
Q,QZ
SN54ASC75
Typt
MAX
MIN
MIN
SN74ASC75
Typt
MAX
0.9
1.9
4.5
1
1.9
4
0.6
1.7
4.1
0.7
1.7
3.7
1
2.4
5.9
1.1
2.4
5.3
1.3
2.8
6.6
1.4
2.8
5.9
0.7
1.5
3.5
0.8
1.5
3.2
1
1.7
3.6
1.1
1.7
3.3
1.3
2.4
5.4
1.4
2.4
4.9
1.1
2.4
5.6
1.2
2.4
5
1.2
2.4
5.6
1.3
2.4
5.1
0.8
1.2
2
0.9
1.4
2
4.5
2.9
5
7
2.9
1.4
3.1
7.4
1.6
3.1
6.3
6.7
1
2
4.6
1
2
4.2
1.2
2
4.5
1.2
2
4.1
1.6
2.9
6.5
1.7
2.9
5.9
1.3
2.7
1.4
2.7
0.2
0.5
6.4
1.2
0.2
0.5
5.8
1.1
0.1
0.3
0.9
0.1
0.3
0.8
.c
UNIT
ns
ns
CI)
...caca
C
ns
ns
ns
ns
ns
ns
ns/pF
t Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%1.
tpLH '" propagation delay time, I"w-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
6tpLH '" change in tPLH with load capacitance
6tpHL .. change in tpHL with load capacitance
tTypical values are VCC = 5 V, TA = 25°C.
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4·57
SN54ASC75, SN74ASC75
O·TYPE LATCHES WITH ACTlVE·HIGH ENABLE
DESIGN CONSIDERATIONS
interfacing the macro
Inputs and outputs of these dedicated macros are compatible for interfacing directly with cells and macros
available in the TI standard cell library. The inputs can be driven by either non inverting or inverting input
cells. The outputs can be interfaced to drive off-chip loads with any of the noninverting output buffers
or interfaced to external bidirectional buses through a three-state input/output TTL/CMOS buffer.
designing for testability
Designers employing storage or bistable elements should consider testability of the design in its final form.
The need to preset or clear these elements should be assessed throughout the development of custom
logic circuits with these considerations extended to the end equipment application with respect to
maintainability. Simple actions on the part of the ASIC designer can result in considerable cost savings,
allowing the expense of IC testing, system testing, and system maintenanc.e to be reduced significantly.
power-up clear/preset
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of the clear or preset inputs from another system signal in conjunction with the power-up Clear
can be achieved with an AND gate.
C
I»
I»
r+
t/)
:r
CD
CD
r+
(II
4-58
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC85, SN74ASC85
4·81T MAGNITUDE COMPARATORS
02939. AUGUST 1986
SystemCell™
2-Ilm SOFTWARE MACRO CELL
•
Performs Magnituda Comparison of Binary,
BCD, and Monotonic Codes
•
Weighted Cascading Inputs Accommodate
Both Serial and Parallel Expansion
•
logic symbol t
}~~
PO
P1
P2
Dependable Texas Instruments Quality and
Reliability
P3
PLTOI
<
PEOOI
description
The SN54ASC85 and SN74ASC85 are
standard-cell software macros implementing
4·bit expandable magnitude comparators. The
4-bit configuration provides the custom IC
designer a magnitude comparator to embed in
ASICs in its most efficient form. The' ASC85
implements a comparison scheme identical with
that performed by packaged. 'HC85, 'LS85 and
'F85 comparators.
PGTOI
00
01
>
}
02
03
PO
PGTOO
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
lEe Publication 617-12.
These 4-bit magnitude comparators perform comparison of straight binary and straight BCD(8-4-2-1 ) codes.
Three fully decoded decisions about two 4-bit words (P, 0) are made and are externally available at three
outputs. These devices are fully expandable to any number of bits without external gates. Words of greater
length may be compared by connecting comparators in cascade. The PGTOO, PLTOO, and PEOOO outputs
of a stage handling less significant bits are connected to the corresponding PGTOI, PLTal, and PEOOI
inputs of the next stage handling more significant bits. The stage handling the least significant bits must
have a high-level voltage applied to the PEOOI input. The cascading path of the' ASC85 is implemented
with only a two-gate-Ievel delay to reduce overall comparison times for long words. The 'ASC85 is
implemented with the standard cell functions indicated. The HDL netlist label for this software macro is
shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USED
TO NA210LH
TOTAL
TOTAL
RELATIVE
Cpd*
(pF)
SN54ASC'
CELL AREA
4
10.8
2.36
896
53.6
IV120LH
1
3
3
1.32
315
18.96
NA210LH
NA310LH
1
6
6
3.06
786
47.04
1.25
2
2.5
1
326
19.56
NA410LH
1.5
2
3
1
374
22.4
NA510LH
1.75
7
12.25
3.64
1491
89.6
5
1.22
580
34.8
42.55
13.6
4768
286
2.5
S85LH
2
26
CD
CD
..c
tn
...caca
o
SN74ASC'
2.7
TOTALS
...rn
MAXIMUM ICC
(nA)
A0221LH
NA810LH
•
Label: S85LH P3,P2,Pl ,PO,03,02,Ol ,OO,PGTOI,PLTOI,PEOOI,PGTOO,PLTOO.PEOOO;
+The equivalent power dissipation capacitance does not include interconnect capacitance.
The SN54ASC85 is characterized for operation over the full military temperature range of - 55 °C to 125°C.
The SN74ASC85is characterized for operation from -40°C to 85°C.
PRDDUCTIDI DATA documontl contain information
curront os of publication date. Products conform to
specifications par the terms af Tuas Instruments
:'':!:~~i~a~:~~,; ~=~~i:r :.r:::=~:!~ not
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
4-59
SN54ASC85, SN74ASC85
4·81T MAGNITUDE COMPARATORS
FUNCTION TABLE
COMPARING INPUTS
CASCADING INPUTS
OUTPUTS
-PEOOO
P3.03
P2.02
Pl.0l
PO. 00
PGTOI
PLTOI
PEOOI
PGTOO
PLTOO
P3 > 03
X
X
X
X
X
X
L
L
P3
<
Q3
X
X
X
X
X
X
=
=
=
=
Q3
P2 > Q2
X
X
X
X
X
Q3
P2
<
X
X
X
X
X
Q3
P2
= Q2
P1 > Q1
X
X
X
X
Q3
P2
P1
<
X
X
X
X
= Q3
= Q3
= Q3
= Q3
= Q3
= Q3
= Q3
P2
= Q2
= Q2
= Q2
= Q2
= Q2
= Q2
= Q2
= Q2
P1
= Q1
= Q1
= 0;1
= Q1
= Q1
= Q1
= Q1
PO> QO
X
X
X
PO
<
QO
X
X
X
PO
= QO
= QO
= QO
= QO
= QO
H
L
L
L
H
L
H
L
H
L
H
L
H
L
H
L
P3
H
L
H
L
H
L
H
L
H
L
X
X
L
L
H
L
H
L
H
L
L
L
H
H
P3
P3
P3
P3
P3
P3
P3
P3
P3
P3
P2
P2
P2
P2
P2
P2
Q2
P1
P1
P1
P1
P1
P1
Q1
PO
PO
PO
PO
L
L
L
L
L
L
L
L
H
L
L
L
logic diagram
•
:
A
· ::~
Qk
A
...m
NAA10Wc
V
e
m
NA810Lx
IVI....
D
D
(I)
!tn
J::aL-
e ..,
C
if
7
~
NA310Lx
G20
~
'"
C>--
P2
C>-
.......
A
:~
;!!!......
NA210Lx
.~
e
V
v
~
""
G
~
1\0221'"
P3
...
NA6,...
A
V
D
D
A
:~
NA210b
~
A
NA61OLl\'
02'
-.L.J
J::aLA
~
NAS1Clx
Pl.'"
1V12Cl.K
V
D
A
Q30
E
Pl.'"
A
.~
NA210Lx
~
~
~
~
~
....
~V
~
V
~
:~
e
D
~
~NMlOLX
D
023~
~NA5IOLX
e~
~:~.
-+-'"
e
D
E
·
e
A
•e
v
:'A4}J 1-+ ~
G28
'(~
NA310lx
G27~
~X
~
4-60
V
~
~
..
...
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
,...-.!L
iV120b
v
A
...
V
~
Pl.TOO
SN54ASC85, SN74ASC85
4-81T MAGNITUDE COMPARATORS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
TEST CONDITIONS
VT Input threshold voltage
Vee = 5 V.
ICC Supply current
Vee - 4.5 V to 5.5 V, VI - Vee or 0,
TA = MIN or MAX
Input capacitance I PQTQI, PLTQI
I All
Vee = 5 V,
Vee = 5 V,
=
MAX
2.2
3 ns,
TA = 25°C
286
0.36
0.36
0.12
0.12
0.37
0.37
13.6
13.6
UNIT
V
4768
TA = 25°C
tr = tf
MAX
2.2
others
Equivalent power
epd dissipation capacitance t
SN74ASC85
TYP
TA = 25°C
IPEQQI
ei
SN54ASC85
TYP
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of operating free-air temperature and supply voltage
(unless otherwise noted) (see Note 1)
PARAMETER*
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
tpd
Pn, Qn
tpd
Pn, Qn
tpd
PLTQI, PEQQI
tpd
PGTQI. PEQQI
PGTQO
PLTQO
tpd
PEQQI
PEQQO
Any
Any
dtpd
SN54ASC85
TYP§
MAX
MIN
12
ns
(I)
12
25.1
ns
9
19.5
ns
6
5.5
15.9
6
ns
13.2
5.5
14
11.7
3
7.6
3
6.6
0.5
1.1
0.5
1
9
0.3
ns
•
UNIT
28
21.5
PGTQO, PLTQO
PEUQO
eL = 0
SN74ASC85
TYP§
MAX
MIN
0.3
ns/pF
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tpd '" propagation delay time, low-to-high or high-to-Iow output
dtpd '" change in tpd with capacitance
§Typical values are at Vee = 5 V, TA = 25°C.
NOTE 1: ,These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
...
tn
CD
CD
.c
...caca
C
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
4-61
SN54ASC85, SN74ASC85
4·81T MAGNITUDE COMPARATORS
HDL FILE
BLOCK S85LH;
P3
@INPUT;
P2
@INPUT;
P1
@INPUT;
PO
@INPUT;
Q3
@INPUT;
Q2
@INPUT;
Q1
@INPUT;
QO
@INPUT;
PGTQI
@INPUT;
PLTQI
@INPUT;
PEQQI
@INPUT;
PGTQO
@OUTPUT;
PLTQO
@OUTPUT;
PEQQO
@OUTPUT;
•
4·62
STRUCTURE
A01
A02
A03
A04
G01
G02
G03
G04
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
END S85LH;
:A0221LH
:A0221LH
:A0221LH
:A0221LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA310LH
:NA410LH
:NA510LH
:NA510LH
:NA510LH
:NA510LH
:NA510LH
:NA510LH
:NA410LH
:NA310LH
:NA210LH
:NA810LH
:NA510LH
:NA810LH
:IV120LH
:IV120LH
:IV120LH
P3,G1 0,G1 0,Q3,A01 0;
P2,G20,G20,Q2,A020;
P1 ,G30,G30,Q1 ,A030;
PO,G40,G40,QO,A040;
P3,Q3,G10;
P2,Q2,G20;
P1,Q1,G30;
PO,QO,G40;
Q3,G10,G170;
Q2,G20,A010,G180;
Q1 ,G30,A01 0,A020,G190;
QO,G40,A010,A020,A030,G200;
A010,A020.A030,A040,PLTQI,G21 0;
A010,A020,A030,A040,PEQQI,G220;
PEQQI,A040,A030,A020,A010,G230;
A040,A030,A020,A010,PGTQI,G240;
A030.A020,A010,G40,PO,G250;
A020,A01 0,G30,P1 ,G260;
A010,G20,P2,G270;
G10,P3,G280;
G170,G170,G180,G180,G190,G200,G210,G220,G290;
A010,A020,A030,A040,PEQQI,G300;
G230,G240,G250,G260,G270,G270,G280,G280 ,G31 0;
G290,PGTQO;
G300,PEQQO;
G310,PLTQO;
TEXAS . .
INSTRUMENTS
POST OFF;ICE BOX 655012 • DALLAS. TEXAS 75265
SN54ASC85, SN74ASC85
4·81T MAGNITUDE COMPARATORS
TYPICAL APPLICATION INFORMATION
COMPARISON OF TWO N·BIT WORDS
S85LH
PO
PO
P1
P1
P2
P3
pQ
PGTOO
___o=-~:,O} a
02
03
P4
P'
P6
P .. Q·~NC
>
PGTQI
00
This application demonstrates how these magnitude
comparators can be cascaded to compare longer
words. The example illustrated shows the comparison
of two 24-bit words; however, the design is
expandable to n-bits. As an example, one S85LH
macro can be used with five of these 24-bit
comparators to expand the word length to 120-bits.
Typical comparison times for various word lengths
using the S85LH are
P2
P3
3
Q3
--
S851H
PO
P1
COMP
WORD LENGTH
1-4 bits
5-24 bits
25-120 bits
P2
P7
}p
P3
P8
04
PLTOO
PLTO)
P
P>Q
06----'''''-1
00
01 }
06----'''"'-1
02
a
07----'=1
03 3
06--=t.:~
PGTOO
:~:-:~:f--~~~~~:~fo'iICciMP--'
COMP
P1
r-_+-+_+-__
P2
P13
O'L
}p
P3
-t--'-"-i
PLTW
P
a~03~2
011
010
012
0
3}
II
...
_ _....J
S85lH
PO
TYPICAL COMPARE TIME
12.5 ns
25.0 ns
37.5 ns
P>Q
PLTOO
PEDQO
~NC
~
I
,",~,03}P
fI)
COMP
PlTQO
P
"PG"..,'T","al'y>
P-O
OO}
L-+-+____-+_...:~'"':-I
a
S85LH
P>Q
IpEDGO
~
a
0
J
013------~~~______~
P-Q
t---- P>Q
r-t---0~3~3~________
CD
CD
.c
fI)
...caca
C
586lH
=-=t----1':2{O)"--;CO'iP--l
COMP
PO
P14
P1.
P1
P16--1--!...!.j
P2
P17--I--~ } p
P3
P18-1--'-"--I
pQ PGTQO
: : 13:}0
018
-----=-e:!.-._____.....J
~~~-
S85l.t1
PO
COMP
P1
P21 --t---:=-i
P2
P22
P3 } p
P23--t---'-=-i
--+---=-1
PLTOI
PO
<
PEOW
01.=:t::~~~
PLTQO
PEQQO
PGTOO
00
020----=.j
01
021----=-i
Q2
Q22---=t
03
Q23----~eL_ _ _ _ _ _
}o
H
~
J
To high output of tie-off cell, L
~
To low output of tie-off cell, NC
~
no connection.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-63
4-64
SN54ASC86. SN74ASC86
2·INPUT EXCLUSIVE· OR GATES
02939, AUGUST 1986
SystemCell™
2-"m INTERNAL STANDARD CELL
logic symbol
•
Choice of Three Performance Levels
•
Specified for Operation Over V CC Range of
4.5 V to 5.5 V
•
Functional Operation Over
2Vt06V
•
Dependable Texas Instrument!; Quality and
Reliability
Vce
:=D--
Range of
y
FUNCTION TABLE
INPUTS
positive logic equations
Y
= AeB = AB+AB
OUTPUT
A
B
L
L
Y
L
L
H
H
H
L
H
H
H
L
description
The SN54ASC86 and SN74ASCa6 are 2-input exclusive-OR gate CMOS standard cells each implementing
the equivalent of one-fourth of an SN54LS86 or SN74LS86 device. The standard-cell library contains three
physical implementations to provide the custom IC designer a choice between three performance levels
for optimizing designs. Each option is designated and called from the engineering workstation input using
the following cell l1ames to develop labels for the design netlist:
II
...
en
FEATURES
CEll NAME
TYPICAL
RELATIVE
DELAY
CEll AREA
Cl - 1 pF
TO NA210lH
EX210LH
2.3 ns
2
2 ns
2.25
2 ns
2.5
Label: EX2nOLH A.B,Y;
EX:z20LH
CD
CD
NEnlsT
liDL LABEL
EX240LH
.s:
o
...asas
Q
The SN54ASC86 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN74ASC86 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
EX210lH
TEST CONDITIONS
PARAMETER
TYP
Vee = 5 V,
TA = 25°e
VT Input threshold voltage
.lsN54Ase86 Vee = 4.5 V to 5.5 V, V, = Vee or 0,
lee Supply current ISN74Ase~6 TA = MIN to MAX
ej
Input capacitance
Equivalent power
Cpd dissipation capacitance
Vee
=
5 V,
Vee - 5 V,
TA
=
TA
=
25°e
2.2
EX220LH
TYP
MAX
2.2
218
EX240LH
TYP
2.2
252
13.1
MAX
V
287
17,2
15.1
UNIT
nA
0·19
0.19
0.19
pF
1
1.35
2.55
pF
tr - tf - 3 ns,
25°e
PRODUCTION DATA .....ments ••ntai. information
current as of publicatiDn date. Products conform to
specifications per the terms of TaXIS ,nstruments
st..ndard warranty. Production p.r~il_!I daes not
D8Cassarily include testing ~ all param!"l'r•.
MAX
Copyright @ 1986, Texas Instruments Incorporated
'TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 •
DALLA~.
TEXAS 75265
4-65
SNs4ASC86, SN74ASC86
2-INPUT EXCLUSIVE-OR GATES
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
EX210LH
PARAMETERt
tpLH
tPHL
tpLH
tpHL
.:l.tPLH
.:l.tpHL
FROM
(INPUT)
TO
(OUTPUT)
CONDITIONS
A or B
V
CL = 0
AorB
V
A or B
V
TEST
CL = 1 pF
SN54ASC86
Typf
MAX
MIN
SN74ASC86
Typf
MAX
MIN
0.8
1.3
1.3
2.5
3.2
0.8
0.5
1.3
1.3
2.3
0.5
1.3
2.3
4.8
2.3
4.4
1
2.3
6
1.4
;.1
2.3
5.4
0.5
1
2.3
0.5
1
2.~
0.5
1
2.9
0.5
1
2.5
SN54ASC86
Typf
MAX
MIN
2.9
UNIT
ns
ns
ns/pF
EX220LH
PARAMETERt
tpLH
tpHL
•
, C
...
tpLH
tpHL
.:l.tpLH
.:l.tPHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A or B
V
CL = 0
A or B
V
CL = 1 pF
A or B
V
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
MIN
SN74ASC86
Typf
MAX
0.7
1.4
2.7
0.8
1.4
2.5
0.5
1.4
3.2
0.5
1.4
2.9
1
1.9
3.8
1.1
1.9
3.5
O.B
0.3
2.1
5
2.1
.4.5
0.5
1.2
0.9
0.3
0.5
1.1
0.3
0.7
1.9
0.3
0.7
1.7
SN54ASC86
MIN Typf
MAX
MIN
0.8
1.6
3.2
0.9
1.6
2.9
0.5
1.6
3.B
0.6
1.6
3.5
1
1.9
3.8
1.1
1.9
3.5
0.7
2
5
0.8
2
4.4
0.1
0.3
0.4
0.7
1.2
0.1
0.3
0.6
0.2
0.4
1.1
UNIT
ns
ns
ns/pF
EX240LH
C»
C»
PARAMETERt
tn
tpLH
::r
tpHL
CD
CD
...en
tpLH
tpHL
.:l.tpLH
.:l.tPHL
A or B
Y
A or B
Y
TEST
CONDITIONS
CL
CL
=0
=
1 pF
0.2
SN74ASC86
Typf
MAX
UNIT
ns
ns
ns/pF
tpropagation delay times are measured from the 44% point of VI to the 44% pOint of Vo with tr = tf = 3 ns (10% and 90%).
tpLH .. propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
.:l.tPLH '" change in tpLH with load capacitance
.:l.tpHL '" change in tpHL with load capacitance
~ Typical values are at VCC = 5 V, TA = 25
ac.
DESIGN CONSIDERATIONS
Refer to Section 7.
4-66
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 15265
SN54ASC109, SN74ASC109
J.j( POSITIVE·EDGE·TRIGGERED FLlp·FLOPS
02939. AUGUST 1986
SystemCell'"
2·llm HARDWIRED MACRO CELL
•
Provides Complementary Q and QZ Outputs
logic symbol t
•
Positive-Edge Triggered with J and KZ Data
,Inputs
PREZ
Q
J
•
CLRZ and PREZ Inputs Provide
Asynchronous Initialization
•
J and KZ Inputs Simplify Implementation of
lJ
CLK
Cl
KZ
Toggle Flip-Flops
CLRZ
description
QZ
lK
R
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
The SN54ASC109 and SN74ASC109 are
dedicated, hardwired. standard-cell macros
implementing positive-edge-triggered flip-flops.
A low level at the PREZ or CLRZ input controls
the state of the outputs regardless of the levels
.
of the other inputs. When PREZ AND CLRZ are inactive (high), data at the J and KZ inputs meeting the
setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level anq is not directly related to the rise time of the clock transition. Following
the hold time interval, data at the J and KZ inputs may be changed without affecting the levels at the
outputs. These versatile flip-flops can perform as Ootype flip-flops if J and KZ are tied together. The JK20LH
flip-flop implements the function and sequential operation identical to one-half of the 'LS109,'S109, or
'F109 packaged flip-flops. The cell is designated and called from the engineering workstation input using
the following cell name to develop labels for the design netlist:
•
...
u)
G)
G)
.c
en
...caca
FEATURES
NETLIST
CELL NAME
JKB20LH
HDL LABEL
Label: JKB20LH CLRZ.PREZ.J.KZ.CLK.O.QZ;
MAXIMUM
RELATIVE
CLOCK
CEUAREA
FREQUENCY
TO NA210LH
44.2 MHz
10
C
The SN54ASC109 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC109 is characterized for operation from -40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUTS
Q
QZ
PREZ
CLRZ
CLK
J
KZ
L
H
X
H
L
L
X
X
X
X
H
X
X
X
L
H
X
I
L
L
H*
L
H*
H
I
H
L
TOGGLE
I
L
00
I
H
X
H
H
X
00
L
L
H
H
H
H
H
H
H
H
H
H
L
H
00
L
ao
.:tThis configuration is nonstable; that is, it wili not
persist when PREZ or ClRZ return to their inactive
(high) level.
PRODUCTION DATA dilCl...onts ••ntsin infonnation
curnmt as of pahlication data. Prodvcts .onform to
_ifi..tlon. par theter... of To.as IlIItr....nts
standerd warranty. Production PIo....ing doas not
n......rily in.lude testing of .11 p.;.mlllan.
Copyright @ 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75285
4-67
SN54ASC109, SN74ASC109.
J-j{ POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
f max
Clock frequency
tw
Pulse duration
tsu
Setup time
th
MIN
0
9
9
11.4
ClRZ low
PREZ low
CK High
CK low
ns
9
3
9.6
PREZ low
J or KZ high or low
UNIT
MHz
ns
11.4
I.B
-0.4
ClRZ inactive
PREZ inactive
J or KZ low
ClRZlow
Hold time
MAX
44.2
ns
0
. . elee'''eel eha........tIco
VT
C
...
Input threshold voltage
tn
Ci
:::T
CD
CD
...en
TA
Input capacitance
PREZ or ClRZ
J
KZ
ClK
Equivalent power
Cpd
dissipation capacitance
= 5 V,
= 4.5 V to 5.5 V,
= MIN to MAX
VCC
VCC
ICC Supply current
C»
C»
SN54ASCOI9
MAX
TYP
TEST CONDITIONS
PARAMETER
VCC
=
5 V,
TA - 25°C
V, - VCC or 0,
TA
VCC = 5 V,
TA = 25°C
2.2
tr
llBl
3 ns,
70.9
0.25
0.12
0.25
0.12
0.13
= 25°C
= tf =
SN74ASC019
TYP
MAX
2.2
0.13
p.13
0.13
4.81
4.Bl
UNIT
V
nA
pF
pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETERt
tplH
tpHl
tplH
tpHl
tplH
tpHl
tplH
tpHl
.1tPlH
.1tpHl
FROM
(INPUT)
TO
(OUTPUT)
ClK
Q,QZ
TEST
CONDITIONS
Cl
PREZ,ClRZ
ClK
=0
Q,QZ
1.1
2.1
2.1
Q,QZ
Cl
PREZ,ClRZ
Q,QZ
Any
Q,QZ
=
SN54ASC109
MIN Typt MAX
1.8
13.5
5
12.2
1.9
4.5
11
2
4.2
1 pF
2.3
1.3
0.2
0.1
2.2
5.5
2.2
1.2
2.3
4.9
5.2
14.6
13.1
4.7
12.2
2.6
0.5
0.4
6.4
1.3
2.5
1.4
0.2
1.2
0.1
t Propagation delay times are measured from the 44% pOint of V, to the 44% point of Vo with tr
tplH " propagation delay time, low-to-high-Ievel output
tpHl .. propagation delay time, high-to-Iow-Ievel output
.1tplH .. change in tplH with load capacitance
.1tpHl '" change in tpHl with load capacitance
*Typical values are at VCC = 5 V, TA = 25°C.
4-68
SN74ASC109
MIN TYpt MAX
2
11.9
5
2.1
4.5
10.9
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
~
2.2
4.2
2.2
5.5
4.9
4.7
2.6
0.5
0.4
UNIT
ns
9.8
4.7
ns
13
11.7
ns
10.9
5.B
1.2
1.1
ns
ns/pF
= tf = 3 ns 110% and 90%).
SN54ASC109, SN74ASC109
J.j( POSITIVE·EDGE·TRIGGERED FLlp·FLOPS
DESIGN CONSIDERATIONS
interfacing the macro
Inputs and outputs of these dedicated macros are compatible for interfacing directly with cells and macros
available in the TI standard cell library . The inputs can be driven by either noninverting or inverting input
cells. The outputs can be interfaced to drive off-chip loads with any of the noninverting output buffers
or interfaced to external bidirectional buses through a 3-state input/output TTL/CMOS buffer.
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
designing for testability
Designs employing storage or bistable elements should consider testability of the design in its final form.
The need to preset or clear these elements should be assessed throughout the development of custom
logic circuits with these considerations extended to the end equipment application with respect to
maintainability. Simple actions on the part of the ASIC designer can result in considerable cost savings,
allowing the expense of IC testing, system testing, and system maintenance to be reduced significantly.
power-up clear/preset
Standard cell storage elements containing the capabilitY to be asynchronously preset or cleared may be
connected to the SN54ASC1 09 or SN74ASC1 09 power-up clear cell to achieve system initialization. Control
of the clear or preset inputs from another system signal in conjunction with the power-up clear can be
achieved with an AND gate.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
II
III
4-69
•
C
I»
r+
I»
en
:::T
CD
CD
r+
til
4-70
SN54ASC137, SN74ASC137
3-L1NE TO B-L1NE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
02939, AUGUST 1986
SystemCell™
2-llm SOFTWARE MACRO CELL
•
Latched Address Lines Ensure Stable Bus
Interfaces
•
Expandable Select Width
•
Parallel Decoders for Multiple-Bit Words
logic symbol t
DMUX
GLZ
description
The SN54ASC137 and SN74ASC137 are
standard-cell software macros implementing a
3-line to 8-line ,decoder/demultiplexer. The
, ASC 137 incorporates a 3-bit latch on the three
address inputs to simplify system design, as the
data selected is stored and is available until
replaced by another selection. The 'ASC 137
implements the full function table identical with
that performed by packaged ICs such as the
'LS137.
YO
l~
A
B
C
Y1
Y2
Y3
Y4
Gl
Y5
G2Z
Y6
Y7
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
II
When the latch-enable input (GLZ) is low, the
'ASC137 acts as a decoder/demultiplexer. When
GLZ goes from low to high, the address present
at the select inputs (A, B, and C) is stored in the latches, Further address changes are ignored as long
as GLZ remains high. This latching capability makes the' ASC137 ideally suited for implementing stable
decoders for strobed (stored-address) applications in bus-oriented systems.
en
~
II)
II)
.c
Also provided in the macro are output controls, G1 and G2Z, that enable and disable the outputs when
G1 is low or G2Z is high. When enabled (G1 high and G2Z low), the selected output is low, These enables
permit the' ASC 137 to be cascaded to accommodate wider multiplexers, as only the enabled 8-bit field
will contain an active data bit. The' ASC137 is implemented with standard cell functions indicated. The
HDL netlist label for this software macro is shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO, USED
TO NA210LH
TOTAL
TOTAL
RELATIVE
Cpd*
(pF)
CELL AREA
tn
CO
CO
~
o
MAXIMUM ICC
(nA)
SN54ASC'
SN74ASC'
IVll0LH
0.75
5
3.75
2.2
525
31.6
AN210lH
1.5
5.4
2.31
69.6
1
9
7
1164
N0210LH
6
7
896
54
NA420LH
2.5
8
26
20
7.68
290
149.6
39.75
17.59
TOTALS
Label: S137LH C,B,A,GLZ,G2Z,Gl ,YO,Yl ,Y2,Y3,Y4,Y5,Y6,Y6;
2875
305
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
The SN54ASC137 is characterized for operation over the full military temperature range of - 55°C to
125°C, The SN74ASC137 is characterized for operation from -40°C to 85°C.
Copyright © 1986, Texas Instruments Incorporated
PRODUCTION DATA do.uments .ontaln information
currant 8S of publication date. Preducts conform to
spacifications par tb. terms of Taxas Instruments
::=~~i~8i:I~1i =~:~ti:; fI~-=:::~::.s not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-71
SN54ASC137, SN74ASC137
3·L1NE TO B·L1NE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
FUNCTION TABLE'
INPUTS
ENABLE
SELECT
C
B
A
OUTPUTS
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
X
X
X
H
H
H
H
H
H
H
H
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
L
H
L
L
L
H
H
L
H
H
H
H
H
H
H
H
H
L
H
L
L
H
L
H
H
L
H
H
H
H
H
L
H
L
L
H
H
H
H
H
L
H
H
H
H
L
H
L
H
L
L
H
H
H
H
L
H
H
H
L
H
L
H
L
H
H
H
H
H
H
L
H
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
L
X
X
X
GLZ
X
X
G1
X
G2Z
L
L
H
H
L
H
H
H
H
Output corresponding to stored address - L
All others = H
logic diagram
•
v
V
C
...
C»
C»
v
(I)
:::T
CD
CD
...en
Y1
Y2
B
V
v
v
C
V
V
GLZ
G2Z
G1
Lx = LH
4-72
VO
A
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
Y3
V4
V5
VB
Y7
SN54ASC137, SN74ASC137
3-LlNE TO B-LlNE DECODERS/DEMULTIPLEXERS
WITH ADDRES$ LATCHES
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
TEST CONDITIONS
~
VT
Input threshold voltage
VCC ~ 5 V,
ICC
Supply current
VCC - 4.5 V to 5.5 V, VI - VCC or 0,
TA ~ MIN to MAX
Ci
Input capacitance
TA
VCC ~ 5 V,
TA
Equivalent power
tr
VCC - 5 V,
~
TYP
~
~
MAX
2.2
3 ns,
dissipation capacitance t
305
0.25
0.25
0.12
0.12
0.11
0.11
17.59
17.59
UNIT
V
2875
25·C
tf
MAX
2.2
I G2Z
Cpd
SN74ASC137
TYP
25·C
LA,8,C
I GLZ,G1
SN54ASC137
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Note 1)
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
tpd
A,B,C,GLZ
Any
tpd
G1 or G2Z
Any
Any
Any
PARAMETER:
~tpd
CL
~
SN54ASC137
TYP§
MAX
MIN
UNIT
12
25.8
12
.23.3
ns
5
12.3
5
0.7
2.3
11.3
2
ns/pF
0
0.3
SN74ASC137
TYP§ MAX
MIN
0.3
0.7
•
...
U)
ns
Q)
Q)
t Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr ~ tf ~ 3 ns (10% and 90%).
tpd '" propagation delay time, low-to-high-Ievel or high-to-Iow-Ievel output
~tpd '" change in tpd with load capacitance
§ Typical values are at VCC ~ 5 V, T A ~ 25 'c.
NOTE1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
.c
en
...caca
C
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for a reference.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-73
SN54ASC137, SN74ASC137
3·L1NE TO B·L1NE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
HDL FILE
BLOCK S 137LH;
C
@INPUT;
B
@INPUT;
A
@INPUT;
GLZ
@INPUT;
@INPUT;
G2Z
G1
@INPUT;
YO
@OUTPUT;
Y1
@OUTPUT;
Y2
@OUTPUT;
Y3
@OUTPUT;
Y4
@OUTPUT;
Y5
@OUTPUT;
Y6
@OUTPUT;
Y7
@OUTPUT;
•
...'C"
'tn"
::T
CD
CD
...
en
4-74
STRUCTURE
AN1
AN2
AN3,
AN4
AN5
AN6
INV1
INV2
INV3,
INV4
INV5
NAl
NA2
NA3
NA4
NA5
NA6
NA7
NA8
N01
N02
N03
N04
N05
N06
N07
END S137LH;
:AN210LH
:AN210LH
:AN210LH
:AN210LH
:AN210LH
:AN210LH
:IV110LH
:IV110LH
:IVll0LH
:IVll0LH
:IV110LH
:NA420LH
:NA420LH
:NA420LH
:NA420LH
:NA420LH
:NA420LH
:NA420LH
:NA420LH
:N0210LH
:N0210LH
:N0210LH
:N0210LH
:N0210LH
:N0210LH
:N0210LH
AN,GLP,LlAP;
A,GLP,LlAN;
BN,GLP,LlBP;
B,GLP,LlBN;
CN,GLP,LlCP;
C,GLP,lICN;
A,AN;
B,BN;
C,CN;
GLZ,GLP;
G1,IV50;
LOAD,LOBN,LOCN,OC, YO;
LOAP,LOBN,LOCN,OC,Y1 ;
LOAN,LOBP ,LOCN,OC, Y2;
LOAP,LOBP,LOCN,OC,Y3;
LOAN,LOBN,LOCP,OC,Y4;
LOAP,LOBN,LOCP,OC,Y5;
LOAN,LOBP,LOCP,OC, Y6;
LOAP,LOBP,LOCP,OC,Y7;
LlAP,LOAN,LOAP;
LOAP,LlAN,LOAN;
LlBP,LOBN,LOBP;
LOBP,LlBN,LOBN;
LlCP,LOCN,LOCP;
LOCP,LlCN,LOCN;
G2Z,IV50,OC;
TEXAS
..Jf
INSTRUMENTS
POST OFFICE BOX 655012 •. DALLAS, TEXAS 75266
SN54ASC137, SN74ASC137
3·L1NE TO B·L1NE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
Dedicated 2·line to 4-line decoder cells (' ASC2350) are also available in the standard cell library for
implementing small data-path decoders. Two predesigned cells, designated as the DE210LH and the
DE212LH, are offered. The DE212LH cell incorporates an enable input that can be used for expanding
the word width. Latch cells can be added at the select inputs to facilitate storage. These hardwired cells
should be considered if the decoder is in a critical path, as their performance is predetermined as specified
in their switching characteristics.
interfacing the macro
Inputs and outputs of the predesigned macro are compatible for interfacing directly with cells and macros
available in the TI standard cell library.
The inputs can be driven by either inverting or non inverting input cells. The outputs can be interfaced to
drive off-chip loads with any of the non inverting output buffers or interfaced to external bidirectional buses
through a 3-state input/output TTL/CMOS buffer.
•
...en
Q)
Q)
.c
en
...caca
C
TEXAS •
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
4·75
II
...C
I»
I»
en
::r
CD
CD
...
CIl
4-76
SN54ASC13B, SN74ASC13B
3-UNE TO B-UNE DECODERS/DEMULTIPLEXERS
02939, AUGUST 1986
SystemCell™
2-llm SOFTWARE MACRO CELL
logic symbol t
•
Three Enable Inputs for Expandability
•
Choice of an Active-High or Two ActiveLow Enables
•
DMUX
JG~
A
Parallel Decoders for Multiple-Bit Words
C
vo
VI
V2
V3
description
V4
&
The SN54ASC138 and SN74ASC138 are
standard-cell software macros implementing a
3-line to 8-line decoder/demultiplexer. The
, ASC 1 38 implements the full function table
identical with that performed by packaged ICs
such as the 'lS138, 'S138, and 'F138,
Gl
V5
G2A2
V6
G2BZ
V7
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Also provided in the macro are strobe inputs G1, G2AZ, and G2BZ, which enable and disable the inputs.
All of the outputs are high, disabled, unless G1 is high and unless G2AZ and G2BZ are low, enabling the
outputs. When enabled the selected output assumes a lOW-logic level. These strobes also permit the
'ASC 138 to be cascaded to accommodate wider multiplexers, as only the enabled 8-bit field will contain
an active data bit. The' ASC138 is implemented with the standard cell functions indicated. The HDl netlist
label for this software macro is shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USEO
TO NA210LH
TOTAL
TOTAL
RELATIVE
Cpd*
(pFI
CELL AREA
SN54ASC'
1
1
0.44
105
6.32
IV120LH
1
6
6
4.8
786
47.1
N0330LH
2.75
1
312
18.7
2.5
8
2.75
20
29.75
0.85
NA420LH
7.68
2496
149.6
13.77
3699
222
TOTALS
16
U)
CD
CD
SN74ASC'
0.75
\ill
...
MAXIMUM ICC
(nA)
IV110LH
a
.c
U)
...caca
C
Label: S 138LH G l.G2AZ,G2BZ,A,B.C, YO, Y1. Y2, Y3, Y 4, Y5, Y6, Y7;
:l:The equivalent power dissipation capacitance does not include interconnect capacitance.
The SN54ASC138is characterized for operation over the full military temperature range of - 55 °C to
125°C. The SN74ASC138 is characterized for operation from -40°C to 85°C.
PRODUCTION DATA documents contain information
currant 8S of publication data. Products conform to
specifications par the terms of TUI. Instruments
:'~:::=i~air::I~1i ~=:~~; :'~D:=:=::':' not
Copyright @ 1986. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
4-77
SN54ASC13B. SN74ASC13B
3·LlNE TO B·LlNE DECODERS/DEMULTIPLEXERS
FUNCTION TABLE
INPUTS
ENABLE
G1 G2AZ G2BZ
C
X
X
H
X
X
H
X
X
L
X
X
X
H
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
OUTPUTS
SELECT
B
X
X
X
L
L
H
H
A
X
VO
H
V1
H
V2
H
X
X
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
L
H
L
H
L
H
L
L
H
H
V3
H
H
H
H
H
H
L
V4
H
H
H
H
H
H
H
V5
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
V6
H
V7
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
logic diagram (positive logic)
A
NA420Lx
B
liliiiio :::~~--------------------------~~
C
0
Y
y
YO
001
NA420Lx
v
m
r+
y
m
rn
:s-
Y
CD
CD
VI
V2
va
r+
(I)
y
V4
Y
A
V
B
V
c
G16
Lx = LH for
4-78
2-~m
G18
standard cells.
.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
V7
SN54ASC13B, SN74ASC13B
3-LlNE TO B-LlNE DECODERS/DEMULTIPLEXERS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
TEST CONDITIONS
VT
Input threshold voltage
Vec - 5 V,
ICC
Supply current
Vce - 4.5 V to 5.5 V, VI - VCC or 0,
TA = MIN to MAX
Ci
Input capacitance
Cpd
I A,8,C
LGl
I G2AZ,G2BZ
Vec
=
Vec - 5 V,
dissipation capacitance t
TA
=
SN74ASC138
TYP
lYP
TA
=
MAX
2.2
TA - 25°C
5 V,
Equivalent power
SN54ASC138
MAX
2.2
V
222
3699
25°C
tr - tf - 3 ns,
25°C
0.24
0.24
0.12
0.12
0.35
0.35
13.8
13.8
UNIT
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Note 11
PARAMETER*
tpd
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A,B,C
(;1, (;2AZ,
tpd
Atpd
or G2BZ
Any
SN54ASC138
TYP§
MAX
MIN
Any
Any
CL
=0
Any
0.3
SN74ASC138
TYP§
MAX
UNIT
MIN
4
8.1
4
7.5
ns
7
13.2
7
12.2
ns
2.3
0.7
2
0.7
*Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr
0.3
= tf
=
nsipF
•
3 ns (10% and 90%).
tpd '" propagation delay time, low-to-high·level or high-to-Iow-Ievel output
Atpd '" change in tpd with load capacitance
§Typical values are at Vec = 5 V, TA = 25°C.
NOTE 1: These switching ·characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses aetut'l interconnect capacitance values.
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TexAs 75265
4-79
SN54ASC138. SN74ASC138
3·LlNE TO 8·LlNE DECODERS/DEMULTIPLEXERS
HDL FILE
BLOCK S138LH;
G1
@INPUT;
G2AZ
@INPUT;
G2BZ
@INPUT;
A
@INPUT;
B
@INPUT; .
C
@INPUT;
YO
@OUTPUT;
Y1
@OUTPUT;
Y2
@OUTPUT;
Y3
@OUTPUT;
Y4
@OUTPUT;
Y5
@OUTPUT;
Y6
@OUTPUT;
Y7
@OUTPUT;
STRUCTURE
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
END S138LH:
II
...C
I»
I»
(I)
::r
CD
CD
...
(I)
:NA420LH
:NA420LH
:NA420LH
:NA420LH
:NA420LH
:NA420LH
:NA420LH
:NA420LH
:IV110LH
:N0330LH
:IV120LH
:IV120LH
:IV120LH
:IV120LH
:IV120LH
:IV120LH
'
G110,G1'30,G150,G100,YO;
G120,G130,G150,G100,Y1;
G110,G140,.G150,G100,Y2;
G120,G140,G150,G100,Y3;
G110,G130,G160,G100,Y4;
G130,G160,G120,G100,Y5;
G110,G160,G140,G100,Y6;
G100,G120,G140,G160,Y7;
G1,G090;
G090,G2AZ,G2BZ,G 100;
A,G110;
G110,G120;
B,G130;
G130,G140;
C,G150;
G150,G160;
Dedicated 2·line to 4·line decoder cells (' ASC2350) are also available in the standard cell library for
implementing small, data-path decoders. Two predesigned cells, designated as the DE210LH and the
DE212LH, are offered. The DE212LH cell incorporates an enable input that can be used for expanding
the word width~ Latch cells can be added at the select inputs to implement storage. These hardwired cells
should be considered if the decoder is in a critical path, as their performance is predetermined as specified
in their switching characteristics.
interfacing the macro
Inputs and outputs of the predesigned macro are compatible for interfacing directly with cells and macros
available in the TI standard cell library.
The inputs can be driven by either inverting or non inverting input cells. The outputs can be interfaced to
drive off-chip loads with any of the noninverting output buffers or interfaced to external bidirectional buses
through a 3-state input/output TTL/CMOS buffer.
4-80
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76266
SN54ASC139, SN74ASC139
DUAL 2·UNE TO 4·UNE DECODERS/DEMULTIPLEXERS
SystemCell™
2·/lm SOFTWARE MACRO CELL
•
Enable Input Permits Expansion of Each
Decoder
•
Parallel Decoders for Multiple Bit Words
logic symbol t
Yl0
Al
Yll
Bl
description
Y12
G1Z
Y13
The SN54ASC139 and SN74ASC139 are
standard-cell software macros implementing
dual 2-line to 4-line decoders/demultiplexers.
The' ASC139 implements the full function table
identical with that performed by packaged ICs
such as the 'lS139A, 'S139, and 'F139.
Y20
A2
Y21
B2
Y22
G2Z
Y23
Also provided in the macro are two strobe inputs
G1Z and G2Z that enable and disable the
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
outputs. The four outputs of a decoder are high
lEe Publication 617-12.
when its corresponding strobe is high. When the
strobe is low, the selected output is low. These
strobes, G 1Z for decoder 1 and G2Z for decoder 2, permit the' ASC139 decoders to be cascaded to
accommodate wider multiplexers, as only the enabled 4-bit field will contain an active data bit. The' ASC139
is implemented with the standard cell functions indicated. The HDl netlist label for this software macro
is shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USED
TOTAL
TOTAL
RELATIVE
Cpd*
(pF)
CELL AREA
TO NA210LH
IV110LH
0.75
8
6
IV120LH
1
2
2
NA320LH
2
TOTALS
3.52
1.6
.s::::
fn
SN74ASC'
840
50.56
262
15.7
8
16
7.52
2040
122.4
18
24
12.64
3142
189
fI)
G)
G)
MAXIMUM ICC
InA)
SN54ASC'
....
....asas
C
Label: S139LH Al,81.G1Z.A2.B2.G2Z.Yl0,Yl1.Y12,Y13.Y20,Y21.Y22.Y23;
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
The SN54ASC139 is characterized for operation over the full military temperature range of -.55 °C to
125°C. The SN74ASC139 is characterized for operation from -40°C to 85°C.
FUNCTION TABLE
INPUTS
ENABLE
PRODUCTION DATA documaida •••tai. Infonaotio•.
• urra.t I. 01 publi..tlo. dlta. Prod.cts .onfona to
.paeili.oti••• po, tho tarm. 01 Ten. Inll,"",101I
:=il;"f.':t"::li ~,=:~ti:r ru==~ not
OUTPUTS
SELECT
GnZ
Bn
An
YnO
Yn1
Yn2
Yn3
H
X
X
H
H
H
H
L
L
L
L
H
H
L
L
L
H
H
H
H
H
L
H
H
L
H
L
H
H
H
H
H
L
L
H
Copyright @ 1986. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-81
SN54ASC139. SN74ASC139
DUAL 2·UNE TO 4·UNE DECODERS/DEMULTIPLEXERS
A NA320Lx
B
1V12Olx
Y
G1Z
C
011
Y10
Ole
A NA320lx
Y
B
C
017
Y11
A NA32Ol.x
Y
C
018
Al
A 'NA32Olx
Y
I
81
Y12
Y
Y
A
C
01.
Y13Z
G16
A NA3ZOl.x
Y
1V12Olx
O2Z
A
Y
C
021
G2e
A NA3ZOl.x
Y
B
C
027
Y20
Y21Z
A NA3ZOl.x
Y
C
...
I»
I»
en
::r
C
A2
028
A NA32Ol.x
Y
B2
Y
c
02.
CD
!.
en
4·82
Y22
Y
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Y23
SN54ASC139, SN74ASC139
DUAL 2-LlNE TO 4-LlNE DECODERS/DEMULTIPLEXERS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
VT
Input threshold voltage
ICC
Supply current
Ci
Input capacitance
I
I
Equivalent power
Cpd
TEST CONDITIONS
SN54ASC139
SN74ASC139
TYP
TYP
VCC = 5 V,
TA = 25°C
VCC - 4.5 V to 5.5 V, VI - VCC or 0,
TA = MIN to MAX
An,8n
GnZ
VC.C
=
5 V,
TA
VCC
=
5 V,
tr
=
=
MAX
2.2
MAX
2.2
V
3142
25°C
tf = 3 ns,
dissipation capacitance t
189
0.12
0.12
0.24
0.24
12.64
12.64
UNIT
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of operating free-air temperature and supply voltage
(unless otherwise noted) (see Note 1)
FROM
TO
TEST
(lNPUTI
(OUTPUT)
CONDITIONS
tpd
An or Bn
Any
tpd
GnZ
Any
.:l.tpd
Any
Any
PARAMETER*
SN54ASC139
TYP§
MAX
MIN
UNIT
ns
4
B.1
4
7.5
3
5.2
3
4.B
ns
0.6
1.8
0.6
1.5
nsipF
CL = 0
0.3
SN74ASC139
TYP§
MAX
MIN
0.3
II
....
CI)
Q)
Q)
*Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf =
3 ns (10% and 90%1.
tpd ill!! propagation delay time, low-ta-high or high-to-Iow-Ievel output
.:l.tpd '" change in tpd with load capacitance
§Typical values are at VCC = 5 V, TA = 25°C.
NOTE 1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
.c
en
....asas
C
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
The HDL for this soft macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
4-83
SN54ASC139. SN14~SC139
DUAL 2·UNE TO 4·LlNE DECODERS/DEMULTIPLEXERS
Hol FILE
BLOCK S 139LH; ': "
A1
@INPUT;
B1
@INPUT;
G1Z
@INPUT;
A2
@INPUT;
B2
@!NPUT;
G2Z
@INpUT;
Y10
@OUTPUT;
Y11
@OUTPUT;
Y12
@OUTPUT;
Y13
@OUTPUT;
Y20
@OUTPUT;
Y21
@bUTPUT;
Y22
@OUTPUT;
Y23
@OUTPUT;
STRUCTURE
Gi1
G12
G13
G14
G15
G16
G17
G18
G19
G21
G22
G23
G24
G25
G26
G27
G28
G29
END S139LH;
:IV120LH
:IV110LH
:IV110LH
:IV110LH
:IV110LH
:NA320LH
:NA320LH
:NA320LH
:NA320LH
:IV120LH
:IVl10LH
:IV110LH
:IV110LH
:IV110LH
:NA320LH
:NA320LH
:NA320LH
:NA320LH
G1Z,G110;
A1,G120;
B1,G130;
G120,G140;
G130,G150;
G120,G130,G110,Y10;
G11 O,G130,G140,Y11;
G110,G120,G150,Y12;
G11O,G140,G150,Y13;
G2Z,G210;
A2,G220;
B2,G230;
G220,G240;
G230,G250;
G220,G230,G21 0, Y20;
G210,G230,G240,Y21;
G210,G220,G250,Y22;
G210,G240,G250,Y23;
Dedicated 2-line to 4-line decoder cells (' ASC2350) are aiso available in the standard cell library for
implementing small, data-path decoders. Two predesigned cells, designated as the bE210LH and the
DE212LH, are offered. The DE212LH cell incorporates an enable input that can be used for expanding
the word width. Latch cells can be added at the select inputs to facilitate storage. These hard-wired cells
should be considered if the decoder is in a critical path, as their performance is predetermined as specified
in their switching characteristics.
interfacing the macro
Inputs and outputs Qf the predesigned macro are compatible for interfacing directly with cells and macros
available in the TI standard cell library.
The inputs can be driven by either noninverting or inverting input cells when interfacing off-chip forthe
input data words. The outputs can be interfaced to drive off-chip loads with any of the noninverting output
buffers or interfaced to external bidirectional buses through a 3-state input/output TTL/CMOS buffer.
4-84
-n-
~
It:J(AS
INSTRUMENTS
post OFFICE BOX 655012
• DALLAS, TEXAS 75265
SN54ASC151, SN74ASC151
B-L1NE TO 1-L1NE MULTIPLEXERS
D2939, AUGUST 1986
SystemCelI™
2-f.lm SOFTWARE MACRO CELL
•
Active-Low Strobe for Expandability
•
Use Parallel Multiplexers for Multiple-Bit
Words
logic symbol t
MUX
GZ
A
description
B
C
The SN54ASC151 and SN74ASC151 are
standard-cell software macros implementing
8-line to 1-line multiplexers, The 'ASC 1 51
implements a function table identical with that
performed by packaged 'HC 151, 'LS 151,
'S151, and 'F151 multiplexers.
00
y
01
02
2
03
04
3
4
05
5
w
The macro has a strobe input, GZ, that enables
6
06
and disables the inputs. The Y output is low and
07
7
the W output is high when GZ is high. When GZ
is low, the Y output assumes the level of the
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
selected input and the W output assumes the
IEC Publication 617-12.
complement of that level. This strobe permits the
macro to be employed for designing wider
multiplexers, as only the enabled 8-bit field will output an active data bit, The' ASC 151 is implemented
with standard cell functions indicated. The HDL netlist label for this software macro is shown on the last
line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USEO
TOTAL
TOTAL
RELATIVE
SN54ASC'
CELL AREA
IVll0LH
0.75
3
2.25
1.32
310
19
IV120LH
1
5
5
4
655
39.3
NA510LH
1.75
8
14
4.16
1704
102.4
NA810LH
2.5
1
2.5
0.61
290
17.4
10.09
2964
179
TO NA210LH
TOTALS
23.75
17
Label: S151 LH GZ,A,B,C,00,01,02,03,04,D5,D6,D7,Y,W;
U)
Q)
Q)
.s::
MAXIMUM ICC
(nA)
Cpd*
(pF)
III
...
fJ)
...
SN74ASC'
a:I
a:I
C
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
The SN54ASC151 is characterized for operation over the full military temperature range of - 55 DC to
125 DC. The SN74ASC151 is characterized for operation from -40 DC to 85 DC.
PRODUCTION DATA documents contein information
currant 8S of publication data. Products conform to
specifications par the terms of Texas Instruments
==~~i~ar::,~1i ~:~:~ti:r ~~o:::~9t:~~s not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1986, Texas Instruments Incorporated
4-85
SN54ASC151, SN74ASC151
8·L1NE TO 1·L1NE MULTIPLEXERS
FUNCTION TABLE
INPUTS
STROBE
SELECT
OUTPUTS
GZ
y
W
x
A
X
H
L
H
L
L
L
L
L
H
L
H
L
L
L
L
00 00
01 i5T
02 02
03 03
04 04
05 05
06 06
07 07
C
B
x
L
L
H
H
H
L
L
L
H
L
H
L
H
H
L
L
H
H
H
L
See explanation of Function Tables in Section 1.
DO, 01 .. . 07 :::: the level of the respective D
input.
logic diagram
c
g)
r+
g)
en
07
::::r
CD
CD
r+
06
en
d.
0'
0
~""-'-----;::::>W
03
02
D1
DO
GZ
INV7
4-86
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ASC151. SN74ASC151
B-LlNE TO 1-LlNE MULTIPLEXERS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
VT
'TEST CONDITIONS
Input threshold voltage
ei
Vee
=
TA
I GZ
Input capacitance
I All other inputs
Equivalent power
Cpd dissipation capacitance t
t The
=
=
Vee
ICC Supply current
4.5 V to 5.5 V, VI
TYP
=
5 V,
TA
Vee
=
5 V,
tr
=
=
3 ns,
25°C
MAX
2.2
179
0.24
0.24
0.12
0.12
10.09
10.09
UNIT
V
2964
25°C
= tf =
MAX
2.2
MIN or MAX
Vee
TA
SN74ASC151
TYP
= 25°C
= Vee or 0,
TA
5 V,
SN54ASC151
nA
pF
pF
equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Note 1)
PARAMETER*
tpd
tpd
tpd
tpd
tpd
tpd
FROM
TO
TEST
IINPUT)
IOUTPUT)
CONDITIONS
A,B,ore
AnyD
GZ
SN54ASC151
TYP§ MAX
MIN
SN74ASC151
TYP§ MAX
Y
7
16.5
7
14.B
W
B
17.5
B
15.B
4
10.1
4
8.9
4.5
11.1
4.5
9.9
5.5
12.7
5.5
11.3
Y
W
eL
=
a
Y
W
UNIT
MIN
6
13.7
6
12.3
l>tpd
Any
Y
0.6
2.6
B.7
0.6
2.6
7.5
l>tpd
Any
W
0.3
0.5
1.1
0.3
0.5
1
ns
ns
ns
ns/pF
tpropagation delay times are measured from the 44% pOint of VI to the 44% point of Vo with tr = tf = 3 ns 110% and 90%).
tpd '" propagation delay time, low-to-high or high-to·low-Ievel output
.6.tpd
change in tpd with load capacitance
§ Typical values are at Vee = 5 V, T A = 25°C.
NOTE1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
II...
U)
Q)
Q)
.s:.
en
...asas
0
=
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference,
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-87
SN54ASC151, SN74ASC151
B·LlNE TO 1·LlNE MULTIPLEXERS
. HOL FILE
BLOCK S151 LH;
GZ
@INPUT;
A
@INPUT;
B
@INPUT;
C
@INPUT;
DO
@INPUT;
01
@INPUT;
02
@INPUT;
03
@INPUT;
04
@INPUT;
05
@INPUT;
06
@INPUT
07
@INPUT;
Y
@OUTPUT;
W
@OUTPUT;
STRUCTURE
GOl
G02
G03
G04
G05
G06
G07
G08
GOS
INVl
INV2
INV3
INV4
INV5
INV6
INV7
INV8
END S151LH;
II
C
I»
r+
I»
en
::T
CD
CD
r+
(I)
:NA510LH
:NA510LH
:NA510LH
:NA510LH
:NA510LH
:NA510LH
:NA510LH
:NA510LH
:NA810LH
:IV110LH
:IV110LH
:IV110LH
:IV120LH
:IV120LH
:IV120LH
:IV120LH
:IV120LH
CZ,BZ;AZ,DO,INV70,UO;
CZ,BZ,AT,Dl ,INV70,Ul;
CZ,BT,AZ,D2,INV70,U2;
CZ,BT,AT,D3,INV70,U3;
CT,BZ,AZ,D4,INV70,U4;
CT,BZ,AT,D5,INV70,U5;
CT,BT,AZ,D6,INV70,U6;
CT,Bi,AT,D7,INV70,U7;
U7 ,U6,U5,U4,U3,U2,U 1,UO, Y;
A,AZ;
B,BZ;
C,CZ;
AZ,AT;
BZ,BT;
CZ,CT;
GZ,INV70;
Y,W;
Dedicated 8-line to l-line multiplexers (' ASC2342) are also available in the standard celi library for
implementing data-path multiplexers. The' ASC2342 cell incorporates an enable input that can be used
for expanding the word width. These hardwired celis should be considered if the multiplexer is in a critical
path, as their performance is predetermined as specified in their switching characteristics.
interfacing the macro
Inputs and outputs of the pre designed macro are compatible for interfacing directly with celis and macros
available in the TI standard celi library.
The outputs can be interfaced to drive off-chip loads with any of the noninverting output buffers or interfaced
to external bidirectional buses through a 3-state input/output TTL/CMOS buffer.
If bus interface is needed, the' ASC251 8-line to l-line multiplexer incorporates 3-state outputs capable
of driving internal data buses.
4-88
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN54ASC153, SN74ASC153
DUAL 4-LlNE TO '-LiNE MULTIPLEXERS
02939. AUGUST 1986
SystemCell™
2-"m SOFTWARE MACRO CELL
logic symbol t
•
Active-Low Strobe for Expandability
•
Use Parallel Multiplexers for Multiple-Bit
Words
A
description
B
The SN54ASC153 and SN74ASC153 are
standard-cell software macros implementing
dual 4-line to 1-line multiplexers. The' ASC 153
implements a function table identical with that
performed by packaged 'HC153, 'LS153,
'S153, and 'F153 multiplexers.
Each 4-bit half of the macro has a strobe input
that enables and disables its associated inputs.
The Yn output is low when GnZ is high. When
GnZ is low, the output assumes the level of the
selected input. These strobes permit the macro
to be employed for designing wider multiplexers,
as only the enabled 4-bit field will output an
active data bit. The 'ASC 153 is implemented
with the standard cell functions indicated. The
HDL netlist label for this software macro is
shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USED
GIZ
Cl0
VI
Cll
C12
C13
G2Z
C20
V2
C21
C22
C23
U)
TOTAL
TOTAL
RELATIVE
CELL AREA
0.75
6
4.5
2.64
630
NA410LH
1.5
8
12
4
1496
38
89.6
NA420LH
2.5
2
5
1.92
624
37.4
16
21.5
8.56
2750
165
TO NA210LH
TOTALS
Q)
Q)
~
MAXIMUM ICC
InA)
Cpd*
IpFI
IVll0LH
II
...
tThis symbol is in accordance with ANSI/IEEE SId 91-1984 and
IEC Publication 617-12.
SN54ASC'
tn
...caca
SN74ASC'
C
Label: S153LH Gl Z,G2Z,A,B,Cl O.Cll ,CI2,CI3,C20,C21 ,C22,C23, Yl.Y2;
:tThe equivalent power dissipation capacitance does not include interconnect capacitance.
The SN54ASC153 is characterized for operation over the full military temperature range of -55°C to
125°C. The SN74ASC153 is characterized for operation from -40°C to 85°C.
FUNCTION TABLE
INPUTS
SELECT
C2
OUTPUT
GnZ
Y
X
H
L
L
L
H
A
CO
X
X
X
X
X
X
L
L
L
X
X
Cl
C3
L
L
H
X
X
X
L
L
H
X
L
X
X
L
L
L
H
X
H
X
X
L
H
H
L
X
X
L
X
L
L
H
H
L
H
X
X
H
X
H
X
X
X
L
L
L
H
H
X
X
X
H
L
H
PRODUCTION DATA documents contein information
currant 81 of publication data. Producta conform to
specifications per thl terms of Taxa. Instruments
::~:~~i~a{nr:l:ri
STROBE
DATA
B
==::i:; 1i~o:.a::::t::I~S not
L
Copyright © 1986, Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-89
SN54ASC153, SN74ASC153
DUAL 4·LINE. TO 1·LlNE MULTIPLEXERS
logic diagram
1V11OLx
G1Z
A
V
INV7
C10
C11
V
V1
C12
C13
B
II
C
m
m
tn
V
A
C20
r+
C21
:::r
CD
CD
r+
en
v
C22
C23
B
1V11OLx
G2Z
C
V
A
0
INVS
4-90
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 ~ DALLAS. Tf;XAS 75265
Y2
SN54ASC153, SN74ASC153
DUAL 4-LlNE TO 1-LlNE MULTILPLEXERS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
Input threshold voltage
Vee ~ 5 V.
lee
Supply current
4.5 V to 5.5 V. VI
Vee
TA ~ MIN or MAX
ei
epd
Input capacitance
Vee - 5 V,
TA - 25°e
Equivalent power
Vee ~ 5 V,
tr
dissipation capacitance t
TA
~
tf
~
TYP
2.2
Vee or O.
~
MAX
TYP
TA ~ 25°e
VT
SN74ASC153
SN54ASC153
TEST CONDITIONS
MAX
165
2750
3 ns,
UNIT
V
2.2
nA
0.12
0.12
pF
8.56
8.56
pF
25°e
t The equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of operating free-air temperature and supply voltage
(unless otherwise noted) (See Note 1)
PARAMETER*
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
tpd
A or B
Y
tpd
Anye
Y
tpd
G1Z or G2Z
Y
Any
Y
4tpd
SN54ASC153
TYP§
MAX
MIN
UNIT
8
13.7
8
12.4
ns
4
7.1
4
6.3
ns
6.5
10.4
6.5
9.3
0.7
2.3
0.7
2
eL ~ 0
0.3
SN74ASC153
TYP§
MAX
MIN
0.3
ns
ns/pF
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr ~ tf ~ 3 ns (10%and 90%).
tpd '" propagation delay time, low-to-high or high-to-Iow-Ievel output
Atpd :;;:;; change in tpd with load capacitance
§Typical values are at Vee ~ 5 V, T A ~ 25 ce.
NOTE1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
•
...
U)
CD
CD
.c
en
...caca
C
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this soft macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS .. TEXAS 75265
4-91
SN54ASC153, SN74ASC153
DUAL 4·LlNE TO 1·LlNE MULTIPLEXERS
HDL FILE
BLOCK S 1 53LH;
G1Z
@INPUT;
G2Z
@INPUT;
A
@INPUT;
B
@INPUT;
Cl0
@INPUT;
ell
@INPUT;
C12
@INPUT;
C13
@INP\JT;
C20
@INPUT;
C2l
@INPUT;
C22
@INPUT;
C23
@INPUT;
Yl
@OUTPUT;
Y2
@OUTPUT;
STRUCTURE
GOl
G02
GQ3
G04
G05
GOB
G07
GOB
G09
Gl0
INVl
INV2
INV4
INV5
INV7
INVB
END S153LH;
C
...mm
en
:::r
CD
CD
...en.
:NA4l0LH
:NA410LH
:NA4l0LH
:NA4l0LH
:NA4l0LH
:NA4l0LH
:NA4l0LH
:NA4l0LH
:NA420LH
:NA420LH
:IV110LH
:IVll0LH
:IVll0LH
:IVll0LH
:IVll0LH
:IVll0LH
STBl Z,BZ,AZ,ClO,Ul0;
STBl Z,BZ,AT,Cll ,Ull;
STB1Z,BT,AZ,C12,U12;
STBl Z,BT,AT,C13,U13;
C20, BZ,AZ,STB2Z, U20;
C2l,BZ,AT,STB2Z,U2l;
C22,BT,AZ,STB2Z,U22;
C23,BT,ZT,STB2Z,U23;
Ul0,U11 ,U12,U13,Yl;
U20,U2l,U22,U23,Y2;
A,AZ;
B,BZ;
AZ,AT;
BZ,BT;
G1Z,STB1Z;
G2Z,STB2Z;
Dedicated 4-line to l-line multiplexers ('SC2341) are also available in the standard cell library for
implementing data-path multiplexers. These hardwirt;!d cells should be considered if the multiplexer is in
a critical path, as their performance is predeterminecl as specified in their switching characteristics.
interfacing the macro
Inputs and outputs of the predesi9ned macro are compatible for interfacing directly with cells and macros
a·vailable in the TI standard cell library.
The inputs can be driven by either inverting or nOl'1inverting input cells. The outputs can be interfaced to
drive off-chip loads with any of the noninverting output buffers or interfaced to external bidirectional buses
through a 3-state input/output TTL/CMOS buffer.
4-92
TEXAS . "
INSTRUMENTS .
POST OFFICE BOX 666012 • DALLAS. TeXAS 75265
SN54ASC155, SN74ASC155
DUAL 2·LlNE TO 4·LlNE DECODERS/DEMULTIPLEXERS
WITH DATA AND ENABLE LINES
02939. AUGUST 1986
•
SystemCell™ 2·llm SOFTWARE MACRO CELL
•
Enable Input Permits Expansion of Each
Decoder
•
Individual Data Inputs to Each 4-Line
Decoder
•
logic symbol t
O} 0
A
..,
G -
1
B
Parallel Decoders for Multiple Bit Words
3
r
DMUX
description
The SN54ASC155 and SN74ASC155 are
standard-cell software macros implementing
8-line or dual 4-line decoders/demultiplexers. The
'ASC155 implements the full function table
identical with that performed by packaged ICs
such as the 'LS 155A.
G1Z
"
Cl
G4
4
0. . .
Yl0
1
Yll
2
Y12
Y13
3
G2Z
r--
C2Z
....
~
Y20
Y21
====---
Y22
The A and B inputs are common to the two
Y23
sections of the macro and select one of the four
outputs in each section. Each section has a C
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
input ANDed with a G input and for 4·line
demultiplexer applications, a choice can be made
in the use of these inputs as strobe and data
inputs. In Section 1, when C1 is high the selected output assumes the level of G1 Z, or to view this another
way, when G 1Z is low the selected output assumes the complement of the level of C 1 . In Section 2, C2Z
and G2Z are interchangeable. When both are low, the selected output is low. When one of them is high,
all outputs are high. Because the active levels of C1 and C2Z are complementary, they can be connected
together in 3-line to 8-line decoder or 1-line to 8-line demultiplexer applications to serve as the third (C)
select line with A and B. G1 Z and G2Z are connected together as the active-low strobe or data line.
II
The' ASC155 is implemented with the standard cell functions indicated. The HDL neWst label for this
software macro is shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USED
TO NA210LH
TOTAL
TOTAL
RELATIVE
CELL AREA
Cpd*
(pFI
SN54ASC'
MAXIMUM ICC
(nAI
SN74ASC'
IV110LH
0.75
1
0.75
0.44
105
6.32
IV120LH
4
8
4
16
3.2
7.52
524
2040
31.4
NA320LH
1
2
N0220LH
1.5·
2
3
1.04
15
23.75
12.2
370
3039
TOTALS
122.4
22.2
183
Label: S155LH C1.G1Z.C2Z.G2Z.A.B.Y10.Y11.Y12.Y13.Y20.Y21.Y22.Y23;
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
The SN54ASC155 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC155 is characterized for operation from -40°C to 85°C.
PRODUCTION DATA documants contain information
currant as of publication date. Products conform to
specifications par the terms of Texas Instruments
:'~~=~~i~l{nr:I~1i ~=:i~~ti:r :.~o::::::9t::.s
not
Copyright
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
© 1986, Texas Instruments Incorporated
4-93
SN54ASC155, SN74ASC155
DUAL 2·LlNE TO 4·LlNE DECODERS/DEMULTIPLEXERS
WITH DATA AND ENABLE LINES
FUNCTION TABLES
FUNCTION TABLE
2-LlNE-TO-4-LlNE DECODER
3-LlNE-TO-B-LlNE DECODER
OR 1-LlNE-TO-4-LlIliE DEMULTIPLEXER
INPUTS
SELECT STROBE
B
DATA
Yl0
Yll
Y12
INPUTS
Y13
SELECT
OUTPUTS
STROBE
(01
(11
(21
(31
(41
(61
(71
G1Z
X
X
H
X
H
H
H
H
Ct B A
G*
L
L
L
H
L
H
H
H
X X X
H
H
H
H
H
H
H
H
H
L
H
L
H
H
L
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
H
L
H
L
L H
L
H
L
H
H
H
H
H
H
H
H
L
H
H
.H
H
L
L H L
L
H
H
L
H
H
H
H
H
X
X
X
L
H
H
H
H
L H H
L
H
H
H
L
H
H
H
H
H L
L
L
H
H
H
H
L
H
H
H
H L H
L
H
H
H
H
H
L
H
H
H H L
L
H
H
H
H
H
H
L
H
H H H
L
H
H
H
H
H
H
H
L
Cl
OUTPUTS
DATA
SELECT STROBE
B
A
G2Z
C2Z
X
X
H
X
Y20
Y21
H
H
Y22
Y23
H
H
L
L
L
L
L
H
H
H
L
H
L
L
H
L
H
H
H
L
L
L
H
H
L
H
H
H
L
L
H
H
H
L
X
X
X
H
H
H
H
H
OR DATA
Y20Y21 Y22Y23Yl0Yll Y12Y13
t C = inputs C 1 and C2Z connected together
:1:(3 = inputs G1Z and G2Z connected together
logic diagram
A NA320lx
B
C
Y10
G1Z
Y11
C1
Y12
NA3
1V120lx
A
A NA320lx
B
NA4
C
Y
Y13
A
B
B
C
Y20
Y
G2Z
NA6
C2Z
4-94
(51
A
INPUTS
•
OR 1-LINE-TO-B-LlNE DEMULTIPLEXER
OUTPUTS
B
NA7
C
A NA320lx
B
NA6
C
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Y
Y
Y21
Y22
Y23
SN54ASC155. SN74ASC155
DUAL 2·LlNE TO 4·LlNE DECODERS/DEMULTIPLEXERS
WITH DATA AND ENABLE LINES
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
VT
ICC
Ci
Cpd
VCC = 5 V.
Input threshold voltage
TA
TYP
= 25°C
TA
Input capacitance
I A, B
I Cl
I C2Z,
= 5 V,
TA
= 25°C
GnZ
= 5 V,
= 25°C
Equivalent power
VCC
dissipation capacitance t
TA
tr
TYP
MAX
183
= tf = 3 ns,
0.24
0.24
0.12
0.12
0.24
0.24
12.2
12.2
UNIT
V
2.2
3039
= MIN to MAX
VCC
MAX
2.2
VCC - 4.5 V to 5.5 V, VI - VCC or 0,
Supply current
SN74ASC155
SN54ASC155
TEST CONDITIONS
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of operating free-air temperature and supply voltage
(unless otherwise noted) (see Note 1)
PARAMETER'
FROM
TO
tpd
A or B
Any
tpd
GnZ or Cn
Any Yn
Any
Any
Ll.tpd
TEST
CONDITIONS
SN54ASC155
TYP§
MAX
MIN
4
7.5
5
B.6
0.6
1.8
CL = 0
0.3
SN74ASC155
TYP§
MAX
UNIT
4
6.9
ns
5
B.l
ns
0.6
1.5
ns/pF
MIN
0.3
II
...
CI)
tate outputs capable
of driving internal data buses.
4-100
TEXAS . "
INSTRUMENT::;
POST OFFICE BOX 655012 • DALLAS.
T~XAS
76265
SN54ASC158. SN74ASC158
QUADRUPLE 2·LlNE TO 1·LlNE INVERTING MULTIPLEXERS
02939. AUGUST 1986
SysternCell™
2·j.lm SOFTWARE MACRO CELL
•
Active-Low Strobe for Expandability
•
Use Parallel Multiplexers for Multiple-Bit
Words
logic symbol t
description
A1
The SN54ASC158 and SN74ASC158 are
standard-cell software macros implementing
four 2-line to 1-line multiplexers. The 'ASC158
implements a function table identical with that
performed by packaged 'HC158, 'lS158,
'S 158, and 'F158 multiplexers.
Y1
B1
A2
Y2
B2
A3
B3
Y3
A4
Y4
The macro has a strobe input, GZ, that enables
B4
and disables the outputs. The Y output is forced
high when GZ is high. When GZ is low, the
tTl,is symbol is in accordance with ANSI/IEEE Std 91-1984 and
output assumes the complement of the level of
lEe Publication 617·12. .
the selected input. This strobe permits the macro
to be employed for designing wider multiplexers,
as only the enabled 2-bit field will output an active data bit. The 'ASC158 is implemented with standard
cell functions indicated. The HDl netlist label for this software macro is shown on the last line of the
following table:
RELATIVE
CELL NAME
CELL AREA
NO. USEO
TO NA210LH
TOTAL
TOTAL
RELATIVE
Cpd*
(pFI
CELL AREA
MAXIMUM ICC
InA)
SN54ASC'
SN74ASC'
IVll0LH
0.75
2
1.5
0.88
210
12.64
NA210LH
1
8
8
4.08
1048
62.72
1.75
6
10.5
7.2
1368
81.6
20
12.16
2626
157
AN220LH
TOTALS
16
Label: S158LH Al ,A2,A3,A4,Bl ,B2.B3,B4,AZ
II
B,GZ,Yl,Y2,Y3,Y4;
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
The SN54ASC158 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC158 is characterized for operation from - 40°C to 85 °C.
FUNCTION TABLE
INPUTS
STROBE SELECT
GZ
H
L
PRODUCTION DATA documents contain informatio,
currant as of publication date. Products conform tl
specifications par the terms of Texas Instrument!
::':!:~~i~ai~:1~1i ~!:~::i:; ~~O::~:::::t:~~S no'
AZ
B
DATA
OUTPUT
Y
A
B
X
X
X
H
L
L
X
H
L
L
H
X
L
L
H
L
H
L
H
X
X
H
L
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-101
SN54ASC158, SN74ASC158
QUADRUPLE 2·LlNE TO 1·LlNE INVERTING MULTIPLEXERS
logic diagram
A1
81
A2
B2
A3
II
83
C
A4
I»
....
I»
0
:::r
B4
CD
CD
....en
y
GZ
1V11OLx
~_ _ _--.:A~
y
GUI
4-102
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC158, SN74ASC158
QUADRUPLE 2-LlNE TO 1-LlNE INVERTING MULTIPLEXERS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
VT
Input threshold voltage
lee
Supply current
ei
Input capacitance
epd
I AZ_B
I All others
Equivalent power
dissipation capacitance t
TEST CONOITIONS
SN54ASC158
SN74ASC158
TYP
TYP
TA ~ 25°e
Vee - 5V,
Vee - 4.5 V to 5.5 V, VI - Vee or 0,
TA ~ MIN to MAX
~
Vee
5 V,
TA
~
2.2
25°e
MAX
2.2
2626
tr ~ tf - 3 ns,
Vee - 5 V,
TA ~ 25°e
MAX
V
157
0.25
0.25
0.12
0.12
12.16
12.16
UNIT
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Note 1 )
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
tpd
Any A or B
Y
tpd
GZ or AZ_B
y
y
PARAMETER;
t.tpd
Any
eL
~
SN54ASC158
TYP§
MAX
MIN
0
0.1
tpropagation delay times are measured from the 44% point of VI to the 44% point of
tpd == propagation delay time, low-ta-high or high-to-Iow-Ievel output
2.8
6.2
5.7
12.2
0.4
1.2
Vo
SN74ASC158
TYP§
MAX
MIN
0.2
II
UNIT
2.8
6.2
5.2
11.4
ns
0.4
1.1
nsipF
ns
with tr = tf = 3 ns (10% and 90%).
dtpd ;;;;; change in tpd with load capacitance
§Typical values are at Vee ~ 5 V, TA ~ 25°e.
NOTE 1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-103
SN54ASC158, SN74ASC158
QUADRUPLE 2·UNE TO 1·UNE INVERTING MULTIPLEXERS
HDL FILE
BLOCK S158LH;
A1
@INPUT;
A2
@INPUT;
A3
@INPUT;
A4
@INPUT;
B1
@INPUT;
B2
@INPUT;
B3
@INPUT;
B4
@INPUT;
AZ_B
@INPUT;
GZ
@INPUT
Y1
@OUTPUT;
Y2
@OUTPUT;
Y3
@OUTPUT;
Y4
@OUTPUT;
STRUCTURE
G01
G02
G03
G04
G05
G06
G07
GOB
G09
G10
G11
G12
G13
G14
G15
G16
END S15BLH;
II
c
D)
r+
D)
tn
:::r
CD
CD
r+
Ul
:AN220LH
:AN220LH
:AN220LH
:AN220LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:AN220LH
:AN220LH
:IV110LH
:IV110LH
G050,G060,Y1 ;
G070,GOBO, Y2;
G090,G100,Y3;
G110,G120,Y4;
A 1 ,G130,G050;
B1,G140,G060;
A2,G130,G070;
B2,G140,GOBO;
A3,G 130,G090;
B3,G140,G100;
A4,G130,G110;
B4,G140,G120;
G150,G160,G130;
AZ_B,G160,G140;
AZ_B,G150;
GZ,G160;
Dedicated 2·line to 1-line multiplexers (' ASC2340) are also available in the standard cell library for
implementing data-path multiplexers. These hardwired cells should be considered if the multiplexer is in
a critical path, as their performance is predetermined as specified in their switching characteristics.
interfacing the macro
Inputs and outputs of the predesigned macro are compatible for interfacing directly with cells and macros
available in the TI standard cell library.
The inputs can be driven with inverting or noninverting input cells. The outputs can be interfaced to drive
off-chip loads with any of the noninverting output buffers or interfaced to external bidirectional buses through
a 3-state input/output TTL/CMOS buffer.
If bus interface is needed, the' ASC25BA 2-line to 1-line multiplexer incorporates 3-state outputs capable
of driving internal data buses.
4-104
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC161A, SN74ASC161A
SYNCHRONOUS 4-BIT BINARY COUNTERS WITH DIRECT CLEAR
02939, AUGUST 1986
SystemCell™
2-llm SOFTWARE MACRO CELL
•
Internal Look-Ahead Enhances Performance
of Cascaded Counters
•
Asynchronous Clear Initializes Sequence
Regardless of Mode
logic symbol t
CLRZ
LOADZ
•
•
Parallel Synchronously Presettable for FullCycle Modulo-N Sequences
RCO
ENT
ENP
Gated Enables and RCO Implement Local
and Global Carry Status
CLK
aA
A
description
as
[4]
The SN54ASC161A and SN74ASC161A are
c
ac
[8]
standard-cell software macros implementing
aD
o
synchronous 4-bit binary counter elements, The
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
4-bit configuration provides the custom IC
,lEe Publication 617-12.
designer a synchronous counter to embed in
ASICs in its most efficient form, and its 4-bit
length means that testability is simplified when constructing large counters, The' ASC 161 A implements
a count sequence identical with that performed by packaged 'HC161 A, 'LS 161 A, and 'F161 A counters,
S
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change
coincidentally with each other when so instructed by the count-enable inputs and other gating, This mode
of operation eliminates output counting spikes associated with asyncl"ronous (ripple) counters, The clear
and load inputs are buffered to enhance performance, and clockinglf the register occurs on the rising
(positive-going) edge of the clock waveform, The' ASC 161 A is implemR ,ted with the standard cell functions
indicated, The HDL netlist label for this software macro is shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
TO NA210LH
NO, USED
TOTAL
TOTt,L
RELATIVE
CELL AREA
Cpd+
(pr
MAXIMUM ICC
1.56
1,76
249
15
420
25,28
3.2
524
31.4
3,22
380
22,8
786
1630
47.04
97,8
1
374
22.4
1.04
426
25.6
2
1
2
IVll0LH
0.75
4
4
IV120LH
1
4
4
IV140LH
1.5
2
3
NA210LH
6
10
6
12.5
3.06
NA310LH.
1
1.25
NA410LH
1.5
2
3
NA510LH
1.75
2
3.5
R2406LH
26,25
1
26.25
11.69
2931
176
32
63.25
31,53
7720
464
TOTALS
I
CD
CD
.c
fn
...caca
SN74ASC'
AN320LH
5
en
C
(nAI
SN54ASC'
II
...
Label: 5161 ALH D,C,8,A,CLK,CLRZ,ENP,ENT,LOADZ,OD,OC,08,OA,RCO;
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
PRODUCTION DATA documents contain information
c.urrant as of publication data. Products conform to
specifications'per the terms of TaxBs Instruments
=~~:=i~8i~:I~'le ~~~:~i:; :r~o:=::,:~~
not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1986. Texas Instruments Incorporated
4-105
SN54ASC161A, SN74ASC161A
SYNCHRONOUS 4·BIT BINARY COUNTERS WITH DIRECT CLEAR
These counters are fully programmable; that is, they may be preset to any number between 0 and 15.
As presetting is synchronous, setting up a low level at the load input disables the counter and causes
the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable
inputs.
Clearing is asynchronous. A low level at the clear input sets all outputs low regardless of the levels of
the clock, load, or enable.
The carry look-ahead circuitry provides for ca~cading counters in n-bit synchronous applications without
additional gating. Instrumental in achieving this are two count-enable inputs and a ripple carry output. Both
count-enable inputs (ENP and ENT) must be high to count. ENP enables the local 4-bits and the ENT is
fed forward to globally extend the enable/disable of previous/next 4-bit cascaded counters. The ripplecarry out (RCO), when locally and globally enabled, will output a high-level pulse at maximum count that
is used to enable successive stages.
These counters feature a fully independent clock. Changes at control inputs other than the clear will have
no effect on the counter until clocking occurs. The functions of the counter are dictated solely by conditions
meeting setup, hold, and duration recommendations.
The SN54ASC161A is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC161A is characterized for operation from -40°C to '85°C .
•
C
I»
I»
r+
t/)
::r
CD
CD
r+
(II
4·106
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAs 75265
SN54ASC161A. SN74ASC161A
SYNCHRONOUS 4·BIT BINARY COUNTERS WITH DIRECT CLEAR
•Ase 161 A output sequence
Illustrated below is the following sequence:
1 . Asynchronously clear outputs to zero
2. Preset to binary twelve
3. Count to thirteen, fourteen, fifteen, zero, one, and two
4. Inhibit
CLR~
I
I
u
I
LOAD
I
I
DATA
INPUTS
A
1-I
____~----------JI
B
____~----------JI-_
1--
c.-J~~--------~,1 _- -
...-...;..--------...,,- -
D-.J
1_-
CLK
....en
ENP
.c
CI)
CI)
til
....ctIctI
ENT
I
I
OA
-,
C
-..l __
OB _
-,I
_
OUTPUTS
OD= - ;
_--.J
I
I
I
I
I
I
I
I IL _____
RCO--~----+----------J
I
I
I
: 12
14
13
I-
I
15
~
________________
2
COUNT
PRESET
+
INHIBIT
ASYNC
CLEAR
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-107
SN54ASC161A, SN74ASC161A
SYNCHRO.NOUS 4·BIT BINARY COUNTERS WITH DIRECT CLEAR
logic diagram
1V110lx
ClRZ
D-
ClK
...-...
LOADZ
A
ENP
ENT
~
lV140Lx
.j...V
A~ ~
INV1
INV>
A
r
1NV8
0
~
1V'110Lx
_~2OLx
~_"V
INV7
_"v
C
A
B
-"V
reD
'v
•
INV8
IP
IF
IJF
A
•
C
II
v
NA3
A
_"'V
K=r °50
B
C
A31
NAtl
V
INV9
Y
NAg
A NAS10Lx
B
y
C
NA7
NA3;Olx
V
NAB
B
C
V
NA10
NA210lx
A
D-
A NA310Lx
Y
B
NAt3
B
Y
'C
~
~
~
Q2
~
as
~
02
Q32
03
~
,.,.
Q1
..012
Q.
~
...........
~
~
QA
as
-C> QC
...-...
QD
'---
NA14
A~x
B
V
g
~
f1i:5
B
A
V
lNVlO
L'>
Y
NA4
NA2
NA210lx
B
A
B
C
•
C
NA6
...-...
~'
A NA310Lx
Y
NAB
A~)(y
AN1
~'
Y
NAt
A
8
~32OL'
B
"\V
...-...
B
C
'!.,.A210l.)I
VINV6
~c
NAte
D~
V
NA12
B
V
C
NA17
NA210lx
A
B
Y
NA16
A NA310Lx
B
C
NA19
Y
A NA510Lx
B
C
o
~
A
V
INV11
..u
NA20
A NA610lx
B
C
D
E
-C> RCO
~
NA2t
A
V
INV12
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation produce workstation output used
to identify and resolve each specific timing need.
4-108
TEXAS .."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC161A, SN74ASC161A
SYNCHRONOUS 4-BIT BINARY COUNTERS WITH DIRECT CLEAR
electrical characteristics
PARAMETER
VT
Input threshold voltage
ICC
Supply current
Ci
Cpd
SN54ASC161A
TEST CONDITIONS
TA
VCC = 5 V,
=
TYP
25°C
MIN to MAX
464
0.12
0.12
0.24
0.24
0.12
0.12
0.12
0.12
ENT
0.25
0.25
lOADZ
0.36
0.36
31.54
31.54
ENP
=
5 V,
Equivalent power
VCC - 5 V,
dissipation capacitance t
TA = 25°C
TA
=
25°C
t r - tf - 3 n5,
UNIT
V
7720
ClK
VCC
MAX
2.2
A,B,C,D
ClRZ
Input capacitance
=
TYP
2.2
VCC - 4.5 V to 5.5 V, V, - VCC or 0,
TA
SN74ASC161A
MAX
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of operating free-air temperature and supply voltage
(unless otherwise noted) (see Note 1)
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
tpd
ClK
RCa
12
22
12
19.8
ns
tpd
ClK
Any Q
4.5
10.4
4.5
9.4
ns
tpd
ENT
RCa
4
7.6
4
6.6
ns
tpHl
ClRZ
Any Q
5
8.3
5
7.7
ns
tpHl
ClRZ
RCO
12
19.5
12
17.9
ns
Atpd
Any
Any Q
0.3
1
2.4
0.3
1
2.1
nsipF
Atpd
Any
RCO
0.3
0.5
1.1
0.3
0.5
1
nsipF
PARAMETER*
SN54ASC161A
TYP§
MAX
MIN
Cl = 0
SN74ASC161A
TYP§
MAX
MIN
II
...
UNIT
o
G)
G)
.c
en
1: Propagation delay times are measured from the 44% point of V, to the 44% point of Va with tr = tf = 3 ns (10% and 90%).
tpd '" propagation delay time, low-to-high or high-to-Iow-Ievel output
tpHl '" propagation delay time, high-to-Iow-Ievel output
.6.tpd =: change in tpd with load capacitance
§Typical values are at VCC = 5 V, TA = 25°C.
NOTE 1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Postwlayout simulation uses actual interconnect capacitance values.
...caca
C
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
4-109
SN54ASC161A, SN74ASC161A
SYNCHRONOUS 4·BIT BINARY COUNTERS WITH DIRECT CLEAR
HDL FILE
BLOCK S161ALH;
@INPUT;
D
C
@INPUT;
B
@INPUT;
A
@INPUT;
CLK
@INPUT;
CLRZ
@INPUT;
ENP
@INPUT;
ENT
@INPUT;
LOADZ
@INPUT;
QD
@OUTPUT;
QC
@OUTPUT;
QB
@OUTPUT;
QA
@OUTPUT;
RCO
@OUTPUT;
III
..
C
I»
I»
t/)
..
::T
CD
CD
(I)
4·110
STRUCTURE
AN1
FF14
:AN320LH
:R2406LH
INV1
:lvf10LH
INV10
:IV120LH
INV11
:IV110LH
INV12
:IV120LH
INV2
:IV140LH
INV5
:IV110LH
INV6
:IV120LH
INV7
:IV110LH
INV8
:IV140LH
INV9
:IV120LH
NA1
:NA310LH
NA10
:NA310LH
NA11
:NA310LH
NA12
:NA410LH
NA13
:NA210LH
NA14
:NA310LH
NA15
:NA210LH
NA16
:NA410LH
NA17
:NA310LH
NA19
:NA310LH
NA2
:NA210LH
NA20
:NA510LH
NA21
:NA510LH
NA3
:NA310LH
NA4
:NA310LH
NA5
:NA210LH
NA6
:NA310LH
NA7
:NA310LH
NA8
:NA210LH
NA9
:NA210LH
END S161ALH;
LOADZ,ENP,ENT,AN10;
INV20,NA40,NA70,NA 140,NA 190,CLK,QA,FFA_QZ,
QB,FFB_QZ,QC,FFC_QZ,QD,FFD_QZ;
CLRZ,INV10;
FFC_QZ,INV100;
FFD_QZ110;
NA210,RCO;
INV10,INV20;
INV60,INV50;
LOADZ,INV60;
AN10,INV70;
FFA_QZ,INV80;
FFB_QZ,INV90;
QA,INV70,INV50,NA 10;
QC,NA 11 0,INV50,NA 100;
AN1 0,INV80,INV90,NA 110;
INV80,INV90,AN10,FFC_QZ,NA120;
INV60,C,NA 130;
NA100,NA130,NA120,NA140;
INV60,D,NA 150;
AN1 0,INV80,INV90,INV1 OO,NA 160;
QD,NA 160,INV50,NA 170;
NA 170,NA 150,NA200,NA 190;
AN10,FFA_QZ,NA20;
AN 10,INV80,INV90,INV1 00,FFD_QZ,NA200;
INV80,INV90,INV1 00,INV110,ENT,NA21 0;
QB,NA50,INV50,NA30;
NA 10,NA80,NA2Q,NA40;
AN10,INV80,NA50;
INV80,AN10,FFB_QZ,NA60;
NA30,NA90,NA60,NA 70;
INV60,A,NA80;
INV60,B,NA90;
TEXAS •
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TeXAS 75265
SN54ASC161A, SN74ASC161A
SYNCHRONOUS 4-BIT BINARY COUNTERS WITH DIRECT CLEAR
count definition
These counters are unidirectional with respect to count operation. Inverting the output levels will produce
a down-count sequence. Bidirectional counters are available in software macros or can be constructed
using the 'ASC2405 through 'ASC2407 4-bit predesigned registers.
designing for testability
Designs employing storage or bistable elements, especially long counters (ripple or synchronous), should
consider testability of the design in its final form. The need to preset or clear and read intermediate stages
of these elements should be assessed throughout the development of custom logic circuits with these
considerations extended to the end-equipment application with respect to maintainability. Simple actions
on the part of the ASIC designer can result in considerable cost savings, allowing the expense of IC testing,
system testing, and system maintenance to be reduced significantly.
power-up clear/preset
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of the clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an AND gate.
II...
en
Q)
Q)
.c
U)
...
CU
CU
C
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-111
II
c
....
Q)
en
::T
Q)
CD
CD
....
til
4-112
SN54ASC163A, SN74ASC163A
SYNCHRONOUS 4·BIT BINARY COUNTERS
02939, AUGUST 1986
SystemCeIrM
2-j.lm SOFTWARE MACRO CELL
•
Internal Look-Ahead Enhances Performance
of Cascaded Counters
•
Synchronous Clear Initializes Sequence
Regardless of Mode
logic symbol t
ClRZ
LOADZ
•
Parallel Synchronously Presettable for FullCycle Modulo-N Sequences
•
Gated Enables and RCO Implement Local
and Global Carry Status
RCO
ENT
ENP
ClK
description
A
QA
B
OB
c
The SN54ASC163A and SN74ASC163A are
141
OC
standard-cell software macros implementing
D
18J
QD
synchronous 4-bit binary counter elements, The
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
4-bit configuration provides the custom IC
IEC Publication 617-12,
designer a synchronous counter to embed in
ASICs in its most efficient form, and its 4-bit
length means that testability is simplified when
constructing large counters. The' ASC 163A implements a count sequence identical with that performed
by packaged 'HC163, 'LS163A, and 'F163A counters.
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change
coincidentally with each other when so instructed by the count-enable inputs and other gating. This mode
of operation eliminates output counting spikes associated with asynchronous (ripple) counters. The clear
and load inputs are bUffered to enhance performance, and clocking of the register occurs on the rising
(posi'tive-going) edge of the clock waveform.
The' ASC163 is implemented with the standard cell functions indicated. The HDL netlist label for this
software macro is shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USED
TOTAL
TOTAL
RELATIVE
Cpd*
(pF)
SN54ASC'
2
1
2
1.18
256
15.3
IVll0LH
0.75
3
2.25
1.32
315
18.96
IV120LH
IV140LH
1
1.5
3
1
3
1.5
2.4
1.61
393
190
23.55
NA210LH
1
6
6
3.06
786
47.04
NA310LH
1.25
10
12.5
5
1630
97.8
NA410LH
1.5
2
3
1
374
22.4
NA510LH
1.75
2
3.5
1.04
426
25.6
N0220LH
N0240LH
1.5
2.5
1
1
1.5
2.5
0.52
0.98
185
292
17.5
R2406LH
41
1
26.25
11.69
2931
176
T0010LH
2
1
2
177
10.6
32
66
7955
478
tOTALS
CELL AREA
29.8
....CD
CI)
CD
.c
tn
....lala
C
MAXIMUM ICC
(nA)
AN410LH
TO NA210LH
•
SN74ASC'
11.4
11.1
Label: S 163ALH D,C.8.A.CLK.CLRZ.ENP,ENT,LOADZ.QD.QC,QB,QA,RCO;
::t:The equivalent power dissipation capacitance does not include interconnect capacitance.
~ROOUCTION DATA doc.mants.ontain information
:urr~~~o~p=:~n:O~:lm"!".r~:=I:::':':n:
:&:'.rd "'.rrIRty. Production prollllling do•• not
.......rily includ. tasting of In p.r.m8l8rs.
Copyright © 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS,
TEXA~
4-113
75285
SN54ASC163A, SN74ASC163A
SYNCHRONOUS 4·B11 BINARY COUNTERS
These counters are fully programmable; that is. they may be preset to-any number between 0 and 15.
As presetting is synchronous. setting up a low level at the load input disables the counter and causes
the outputs to agree with the setup data after the next clock pulse. regardless of the levels of the enable
inputs.
Clearing is synchronous. A low level at the clear input will set all outputs low on the next positive transition
of the clock.
The carry look-ahead circuitry provides for cascading counters in n-bit synchronous applications without
additional gating. Instrumental in achieving this are two count-enable inputs and a ripple carry output. Both
count-enable inputs (ENP and ENT) must be high to count. ENP enables the local 4-bits and the ENT is
fed forward to globally extend the enable/disable of previous/next 4-bit cascaded counters. The ripplecarry out (RCO). when locally and globally enabled. will output a high-level pulse at maximum count that
is used to enable successive stages.
These counters feature a fully independent clock. Changes at control inputs. including clear, will have no
effect on the counter until clocking occurs. The functions of the counter are dictated solely by conditions
meeting setup. hold. and duration recommendations.
The SN54ASC163A is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC163A is characterized for operation from -40°C to 85°C .
•
4-114
TEXAS .."
INSTRUMENTS
POST Of::FICE BOX 655012 • DALLAS. TEXAS 75265
logic diagram (positive logic)
TOO1OLx
.... vee
1NV1~
ClK
(N)
~
ClRZ
..........
"--'
·LOAOZ
Il
~
Q
~z
-DQA
-DaB
.~ ~
~ ;o~
-CJQC
~C::~
~s::
1V12OLx
A
~1'1
Y
B
INVII
~z
~~ Ui4r
A NA310lx
p:.;Y_++-";ri
Q[)
NAll
c:n
FI'14
C
<
2
NA13 F>"-Y--f--l
n
:z:
~
:a
'"
'"'"
~
=
2c:n
=2
c:n-,="
-,=":1>
• c:n
CU'I
o
.-+---------~;~NA21
~
A
Y
INVS
II
Y
b
A NA61CL.
B
-1-
-D RCO
~
lV12CLx
;~
INIIII
f"
~
01
!!n
~Y~____~
Data Sheets
II
en
ca
_w
2:1>
:1>"
:ac:n
<2
n-,="
=:1>
C c:n
2n
-1men
:aw
c:n:l>
....
SN54ASC163A, SN74ASC163A
SYNCHRONOUS 4·B11 BINARY COUNTERS
'ASC163A outpUt sequence
Illustrated below is the following sequence: .
1. Synchronously clear outputs to zero
2. Preset to binary twelve
3. Count to thirteen, fourteen, fifteen, zero, one, and two
4. Inhibit
CLRZ~
u
LOADZ
1-A _____________________--JI_ _
1-B _____________________..JI _ _
DATA
INPUTS
~-----------------.I-
1_-
~-----------------.I-
D..J
II
-
._-
C..J
ClK
ENP
0
....
I»
I»
ENT
tn
::r-
QA
CD
CD
....
til
--,I
aB
OUTPUTS
ac
::LJ
aD
;--.1
RCO
i:
I
I
I
I
:12
13
14
n.
15
I 1.....,.----
oL-.----2-+:- - - - - - - - - - - -
COUNT
--~+N---.
INHIBIT
SYNC PRESET
CLEAR
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation produce workstation output used
to identify and resolve eath specific timing need.
4-116
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN54ASC163A, SN74ASC163A
SYNCHRONOUS 4-BIT BINARY COUNTERS
electrical characteristics
PARAMETER
VT
Input threshold voltage
ICC
Supply current
Ci
Cpd
SN54ASC163A
TEST CONDITIONS
Vec = 5 V,
TYP
Input capacitance
=
TYP
2.2
TA = 25°C
VCC - 4.5 V to 5.5 V, VI - VCC or 0,
TA
SN74ASC163A
MAX
MIN to MAX
478
0.12
0.12
elK
0.24
0.24
0.24
0.24
0.12
0.12
ENT
0.24
0.24
lOADZ
0.59
0.59
29.8
29.8
ENP
Vec
=
5 V,
Equivalent power
Vec = 5 V,
dissipation capacitance t
TA = 25°C
TA
tr
=
25°C
= tf =
3 ns,
UNIT
V
7955
A,B,C,D
ClRZ
MAX
2.2
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (See Note 1)
PARAMETER'
FROM
TO
TEST
IINPUT)
IOUTPUT)
CONDITIONS
tpd
ClK
RCO
tpd
ClK
Any Q
SN54ASC163A
TYP§
MAX
SN74ASC163A
TYP§
MAX
MIN
CL = 0
MIN
9
22.2
9
20.1
ns
5
10.6
5
9.6
ns
tpd
ENT
RCO
2
7.6
<1tpd
Any
Any Q
0.3
1
2.4
<1tpd
Any
ReO
0.3
0.5
1.1
=
II
UNIT
2
6.6
ns
0.3
1
2.1
ns/pF
0.3
0.5
1
ns/pF
=
'Propagation delay times are measured from the 44% point of VI to the 44% pOint of Vo with tr
tf
3 ns 110% and 90%).
tpd '" propagation delay time, low-to-high or high-to-Iow-Ievel output
<1tpd '" change in tpd with load capacitance
§Typical values are at VCC = 5 V, TA = 25°C.
NOTE 1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2.000 gates. Post-layout simulation uses actual interconnect capacitance values.
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs,
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-117
SN54ASC163A, SN74ASC163A
SYNCHRONOUS 4-811 BINARY COUNTERS
HDL FILE
BLOCK S163ALH;
D
@INPUT;
C
@INPUT;
B
@INPUT;
A
@INPUT;
CLK
@INPUT;
CLRZ
@INPUT;
ENP
@INPUT;
ENT
@INPUT;
LOADZ
@INPUT;
OD
@OUTPUT;
OC
@OUTPUT;
OB
@OUTPUT;
OA
@OUTPUT;
RCO
@OUTPUT;
•
...c
C»
C»
en
::r
CD
!
(I)
'4-118
STRUCTURE
AN 1
FF14
:AN41 OLH
:R2406LH
INV1
:T0010LH
INV3
:IV110LH
INV4
:IV110LH
INV5
:IV140LH
INV6
:IV120LH
INV7
:IV120LH
INV8
:IV110LH
INV9
:IV120LH
NA1
:NA310LH
NA10
:NA210LH
NA11
:NA310LH
NA12
:NA310LH
NA13
:NA310LH
NA14
:NA410LH
NA15
:NA210LH
NA16
:NA210LH
NA17
:NA410LH
NA18
:NA310LH
NA2
:NA310LH
NA20
:NA310LH
NA21
:NA510LH
NA22
:NA510LH
NA3
:NA210LH
NA5
:NA210LH
NA6
:NA210LH
NA7
:NA310LH
NA8
:NA310LH
NA9
:NA310LH
N01
:N0220LH
N02
:N0240LH
END S163ALH;
CLRZ,LOADZ,ENP,ENT,AN10;
ICLRZ,NA20,NA80,NA 1. 30,NA200,CLK,OA,OAZ,OB,OBZ,
OC,OCZ,OD,ODZ;
DUM,ICLRZ;
CLRZ,INV30;
AN10,INV40;
OAZ,INV50;
OBZ,INV60;
OCZ,INV70;
ODZ,INV80;
NA220,RCO;
OA,N01 0,INV40,NA 10;
N020,B,NA 100;'
AN10,INV60,INV50,NA110;
OC,NA 11 0,N01 O,NA 120;
NA 120,NA 150,NA 140,NA 130;
AN 10,INV50,INV60,OCZ,NA 140;
N020,C,NA 150;
N020,D,NA 160;
AN1 OlINV70,INV50,INV60,NA 170;
OD,NA 170,N01 O,NA 180;
NA 10,NA50,NA30,NA20;
NA 180,NA 160,NA210,NA200;
AN 10,INV50,INV60,INV70,ODZ,NA21 0;
INV50,INV60,INV70,INV80,ENT,NA220;
AN10,OAZ,NA30;
N020,A,NA50;
AN10,INV50,NA60;
OB,NA60,N01 O,NA 70;
NA70,NA 100,NA90,NA80;
AN10,INV50,OBZ,NA90;
INV30,N020,N010;
INV30,LOADZ,N020;
TEXAS •
INSTRUMENTS
POST OFFICI; BOX 655012 • DALLAS. TEXAS 75265
SN54ASC163A. SN74ASC163A
SYNCHRONOUS 4·BIT BINARY COUNTERS
count definition
These counters are unidirectional with respect to count operation. Inverting the output levels will produce
a down-count sequence. Bidirectional counters are available in software macros or can be constructed
using the' ASC2405 through' ASC2407 4-bit predesigned registers.
designing for testability
Designs employing storage or bistable elements, especially long counters (ripple or synchronous), should
consider testability of the design in its final form. The need to preset or clear and to read intermediate
stages of these elements should be assessed throughout the development of custom logic circuits with
these considerations extended to the end-equipment application with respect to maintainability. Simple
actions on the part of the ASIC designer can result in considerable cost savings, allowing the expense
of IC testing, system testing, and system maintenance to be reduced significantly.
power-up clear/preset
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of the clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an AND gate.
II
'1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-119
4-120
SN54ASC164, SN74ASC164
8·BIT PARALLEL·OUT SERIAL SHIFT REGISTERS
02939, AUGUST 1986
SystemCell™
2-j.lm SOFTWARE MACRO CELL
•
AND-Gated (Enable/Disable) Serial Inputs
•
Buffered Clear and Serial Inputs
logic symbol t
•
Direct Clear
•
Embedded Clock Drivers Provide Clock
Buffering
•
Dependable Texas Instruments Quality and
Reliability
ClRZ
ClK
A
QA
8
08
OC
00
OE
description
The SN54ASC164 and SN74ASC164 are
standard-cell ,softWare macros implementing
8-bit parallel-out shift registers, The 8-bit
configuration provides the custom IC designer
a register to embed in ASICs in its most efficient
form, Its 8-bit length simplifies construction of
'large counters. The 'ASC164 implements a shift
sequence identical with that performed by
packaged 'HC164, 'LS164, and 'F164 registers,
OF
OG
OH
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
These 8-bit shift registers feature AND-gated
serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit complete control over
incoming data, as a low at either input inhibits entry of new data and resets the first flip-flop to a low
level at the next clock pulse. A high-level input enables the other input, which will then determine the
state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, provided
the minimum setup time requirements are met. Clocking occurs on thelow-to-high-Ievel transition of the
clock pulse.
The' ASC 164 is implemented with the standard cell functions indicated. The HDL netlist label for this
software macro is shown on the last line of the following table:
RELATIVE
CEll NAME
CEll AREA
NO. USED
TO NA210lH
TOTAL
TOTAL
RELATIVE
Cpd*
IpFI
CELL AREA
J:
en
...
CO
CO
C
SN74ASC'
1
1.5
0.9
194
11.6
IVll0lH
0.75
1.5
1
1
0.75
1.5
0.44
1.61
105
190
6.32
11.4
39.4
2
50.5
20.6
6142
370
5
54.25
23.55
6631
400
TOTALS
fI)
Q)
Q)
InAI
SN54ASC'
1.5
IV140lH
...
MAXIMUM ICC
AN210lH
R2401lH
•
label: S164lH A,8,ClK,ClRZ,QA,QB,QC,QO,QE,QF,QG,QH;
;The equivalent power dissipation capacitance does not include interconnect capacitance.
The SN54ASC 164 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC164 is characterized for operation from - 40°C to 85 DC.
pRODUCTION DATA d••• ments .ontein information
.urrent al of publication data, Products .onlann 10
.pacificati.ns pa, Iha I.nna 01 T.... Inll......ts
:.=~i~·I::-:IO::l,; =~:~:; CJ·:::':Zt~ not
Copyright © 1986, Texas Instruments Incorporated
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-121
SN54ASC164, SN74ASC164
8·BIT PARAlLEL·OUT SERIAL REGISTERS
FUNCTION TABLE
INPUTS
OUTPUTS
ClR
ClK
A
B
QA
l
X
X
X
L
H
H
H
L
X
X
i
i
i
H
H
L
X
X
L
H
OB .. . OH
l
QAO QBO
H QAn
L
QAn
L
QAn
L
QHa
QG n
QG n
QG n
logic diagram
CLK
R2401Lx
CLK
I-"Q,,-,_ _ _-,
•
QA
4-122
as·
ac
ao
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
QE
Of
QG
QH
SN54ASC164, SN74ASC164
8-BIT PARAllEL-OUT SERIAL REGISTERS
typical clear, shift, and clear sequences
u
CLRZf.J
,
SERIAL {
L-Jl__________~--------
A
INPUTS
B--i------'
CLK---'-I---'
I
I
QA==='~I
---,
__________'
~--------+--------~----~~-------
QB ___ ~I~_ _ _ _ _ _ _ _ ___'
Qc==-~l~
QD==-~l~
---,
OUTPUTS
QE __
~I~
________________
_____________________
~~--~-------
--J
~~--------,
~
Ln'--_______
___________________________~
___________________________
,
QG===~ _______________________~~~:_____________
QF==-l~~
~
---,
QH ___ ______________________________________
~I
n'
~
~
II
____________
I
CLEAR
CLEAR
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation produce workstation output used
to identify and resolve each specific timing need.
electrical characteristics
PARAMETER
VT
lee
ej
Input threshold voltage
Supply current
Input capacitance
SN54ASC164
TEST CONDITIONS
TA
-~
elK
= 5 V,
= 4.5 V to 5.5
= MIN or MAX
Vee
Vee
Vee
=
5 V,
TA
V,
VI
TA
TYP
= 25°e
= Vee or 0,
=
25°e
eLRZ
Equivalent power
epd
dissipation capacitance t
= 5 V,
= 25°e
Vee
TA
tr
=
tf
=3
ns,
MAX
2.2
SN74ASC164
TYP
MAX
400
6631
0.13
0.13
0.48
0.48
0.12
0.12
23.55
23.55
UNIT
V
2.2
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
TE~.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-123
SN54ASC164, SN74ASC164
8·BIT PARALLEL·OUT SERIAL REGISTERS
switching characteristics over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise noted) (see Note 1)
PARAMETERt
FROM
(INPUT)
ClK
TO
(OUTPUT)
Qn
ClRZ
ClK or ClRZ
Qn
Qn
tpd
tPHl
atpd
TEST
CONDIT(ONS
SN54ASC164
MIN
Cl = 0
TYP*
5
0.3
4
0.5
SN74ASC164
MAX
11.2
7.7
MIN
1.3
0.3
TYP*
5
4
0.5
MAX
10.2
7.5
1.1
UNIT
ns
ns
ns/pF
tpropagation delay times are ,t,'easured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tpd .. propagation delay time. low-to-high- or high-to-Iow-Ievel output
tpHl '" propagation delay time. high-to-Iow-Ievel output
atpd '" change in tpd with load capacitance
*Typical values are at VCC = 5 V. T A = 25 ·C.
NOTE1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs:
...C
The HDL for this soft macro is included as a part ·of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
I»
I»
tn
::T
CD
CD
...
UI
HDL FILE
BLOCK S164LH;
A
@INPUT;
B
@INPUT;
CLK
@INPUT;
CLRZ
@INPUT;
OA
@OUTPUT;
OB
@OUTPUT;
OC
.@OUTPUT;
OD
@OUTPUT;
OE
@OUTPUT;
OF
@OUTPUT;
OG
@OUTPUT;
OH
@OUTPUT;
STRUCTURE
AN1
INV1
INV2
FF14
FF58
END S164LH;
4-124
:AN210LH
:IV110LH
:IV140LH
:R2401LH
:R2401LH
A.B,AN10;
CLRZ,INV10;
INV10,INV20;
INV20,AN10,CLK,OA,OB,OC,OD;
INV20,OD,CLK,OE,OF,OG,OH;
TEXAS . "
INSTRUMENTS
POST OF~tCE BOX 655012,. DALLAS, TeXAS 75265
SN54ASC164, SN74ASC164
8-BIT PARALLEL-OUT SERIAL REGISTERS
shift definition
These registers are unidirectional with respect to shift operations. Bidirectional registers are available in
software macros or can be constructed using the' ASC2405 through' ASC2407 4-bit pre designed registers.
designing for testability
Designers employing storage or bistable elements, especially long registers (ripple or synchronous), should
consider testability of the design in its final form. The need to preset or clear, and read intermediate stages
of these elements should be assessed throughout the development of custom logic circuits with these
considerations extended to the end-equipment application with respect to maintainability. Simple actions
on the part of the ASIC designer can result in considerable cost savings, allowing the expense of IC testing,
system testing, and system maintenance to be reduced significantly.
.
power-up clear/preset
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of the clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an AND gate.
II
...
fI)
Q)
Q)
.J:.
o
ca
ca
...
C
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
4-125
•
c
g)
r+
g)
t/)
:::T
CD
CD
r+
en
4-126
SN54ASC165, SN74ASC165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
02939, AUGUST 1986
SystemCell™
2-/Am SOFTWARE MACRO CELL
logic symbol t
•
Gated (Enablellnhibit) Clock Inputs
•
Complementary Outputs
•
Direct Overriding Load (Data) Inputs
•
Parallel-to-Serial Data Conversion
•
Clock Driver Provides Clock Buffering
•
Dependable Texas Instruments Quality and
Reliability
SRG8
SH_lOZ
ClKINH
ClK
SER
A
10
B
10
C
0
E
description
F
The SN54ASC165 and SN74ASC165 are
G
standard-cell software macros implementing
OH
H
10
8-bit parallel-in shift registers, The 8-bit
OHZ'
configuration provides the custom IC designer
a register to embed in ASICs in its most efficient
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
form, Its 8-bit length simplifies construction of
large registers, The' ASC165 implements a shift
sequence identical with that performed by packaged 'HC165 and 'LS165 registers,
The' ASC165 is an 8-bit serial shift register that, when clocked, shifts the data toward serial output QH.
Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a
low level at the SH_LDZ input, The' ASC165 also features a clock-inhibit function and a complementary
serial output QHZ. The' ASC 165 is implemented with the standard cell functions indicated. The HDL netlist
label for this software macro is shown on the last line of the following table:
•
...
U)
G)
G)
.c
(J)
...caca
C
RELATIVE
CELL NAME
CELL AREA
NO. USED
TO NA210LH
TOTAL
TOTAL
RELATIVE
Cpd*
(pF)
CELL AREA
MAXIMUM ICC
(nA)
SN54ASC'
SN74ASC'
A0221LH
2.7
1
2.7
0.59
224
DFB20LH
7.7
8
61.6
30.08
7472
448
IV140LH
1.5
2
3
3.24
380
22.8
NA210LH
1
TOTALS
13.4
16
16
8.16
2096
125.44
27
83.3
42.07
10172
610
Label: S165LH A.B,G,D,E,F,G,H,GLK,CLKINH,SH_LDZ.SER,QH,QHZ;
+The equivalent power dissipation capacitance does not include interconnect capacitance.
Copyright © 1986. Texas Ins~ruments Incorporated
PRODUCTION DATA documents .ontain information
currant as of publication data. Products conform to
specific8tioni par the tarms of Texas Instrumants
:'::::~~i~8{:~~tze ~=~~i:r :.r=~~s not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265.
4-127
•
SN54ASC165, SN74ASC165
PARALLEL·LOAD. 8·BIT SHIFT REGISTERS
Clocking is accomplished by a low-to-high transition of the ClK input while SH_lDZ is held high and ClKINH
is held,low. The functions of the ClK and ClKINH inputs are interchangeable. Since a low ClK input and
a low-to-high transition of ClKINH will also accomplish clocking, ClKINH should be changed to the high
level only while the ClK input is high. Parallel loading is inhibited when SH_lDZ is held high. The parallel
inputs to the register are enabled while SH_lDZ is low independently of the levels of ClK, ClKINH, or
SER inputs.
The SN54ASC165 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC165 is characterized for operation from -40°C to 85°C.
FUNCTION TABLE
INPUTS
SH_lDZ
ClK
ClKINH
L
X
FUNCTION
Parallel load A thru H
H
H
X
X
H
X
H
No change
H
L
i
Shift
H
i
L
Shift
No change
Shift = Content of each internal register shifts toward
serial output QH. Data at serialmput IS shifted Into first
register.
~
absolute maximum ratings and recommended operating conditions
o
See Table 1 in Section 2.
I»
Cit
timing requirements
en
:::r
CD
CD
...
en
4-128
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation produce workstation output used
to identify and resolve each specific timing need.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
logic diagram
t:
I~
Cl
'G
A"
!il
FF8
fl'C
Qti
c
OHZ
FFG
~Z
~CJJ
~~
g;or;;i
;;o c:~
~
~ I""l
!Ul-*' I
I;;Z
I
~
""1:1
>>-
:D
I"""
I"""
",
r:I"""
een
>-2
Clc:n
CD oIiIo
'>
!!en
en-
-In
=en
::;;~
-f
en
2
:D
",
....
C')oIiIo
->en en
-In
",-
f'
I
I
~
I\)
(0
Data Sheets
II
:Den
en U'I
SN54ASC165, SN74ASC165
PARALLEL·LOAD 8·81T SHIFT REGISTERS
typical shift. load. 'and inhibit sequences
ClK
ClKINH
SER
l
SH/LD-U
I
I
A~~__~______________________________
B
I l
I
I
C
D
----..J:Hl------~-------------------------------------I l
I
I
DATA
E~~______~_______________________________________
F
I l
I
I
G~~__~______________~______________
II
I
H
----.Ji";l
I
~----~---------------------------------
o
I»
QH
H
I»
QH
l
...
t/)
::r
j4-INHIBIT
CD
CD
...
H
-I~"f4f-------SERIAl SHIFT - - - - - - - - - -••
lOAD
(I)
electrical characteristics
PARAMETER
VT
Input threshold voltage
ICC Supply current
Cj
Input capacitance
A thru H
. ClK,CLKINH
SER
SH_LDZ
Equiyalent power
Cpd
dissipation capacitance t
TEST CONDITIONS
VCC - 5 V,
TA - 25°C
VCC = 4,5 V to 5.5 V, VI = VCC or 0,
TA = MIN to MAX
VCC = 5 V,
VCC - 5 V,
TA = 25°C
SN74ASC165
10172
sio
0.12
0.13
0.11
TA = 25°C
t r - tf - 3 ns,
SN54ASC165
TYP
MAX
2,2
0.12
0,13
0.75
0.11
0.75
42.07
42.07
t The equivalent power dissipation capacitance does not include interconnect capacitance.
4-130
TYP
2,2
TEXAS" .
INSTRUMENTS
~OST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MAX
UNIT
V
nA
pF
pF
SN54ASC165, SN74ASC165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SWitching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Note 1)
FROM
TO
TEST
(INPUT)
IOUTPUT)
CONDITIONS
tpd
SH_LDZ
OH,OHZ
tpd
CLK
OH,OHZ
tpd
H
OH,OHZ
Any
On
PARAMETERt
.:I.tpd
SN54ASC165
MIN
7
15.5
7
14.1
ns
8
19.5
8
17.4
ns
4
7.8
4
7.2
ns
0.5
1.3
0.5
1.2
nslpF
tPropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr
tpd " propagation delay time, low-to-high- or high-to-Iow-Ievel output
dtpd
=-
MIN
0.1
=
tf
=
TYP*
MAX
UNIT
MAX
CL = 0
0.1
SN74ASC165
TYP*
3 ns (10% and 90%).
change in tpd with load capacitance
=
=
; Typical values are at VCC
5 V, TA
25°C.
NOTE 1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
DESIGN CONSIDERATIONS
All inputs to cell must be accounted for in the netlist used to generate the next level of an ASIC design .
A tie-off cell is offered specifically for managing unused inputs.
The HDl for this software macro is included as a part of the library supplied for supported engineering
workstations 50 that a single label can be developed to apply the macro as needed. The following printout
of the HDl block definition is furnished for reference.
•
HDl FilE
BLOCK S165lH;
@INPUT;
B
@INPUT;
C
@INPUT;
D
@INPUT;
E
@INPUT;
F
@INPUT;
G
@INPUT;
H
@INPUT;
ClK
@INPUT;
ClKINH
@INPUT
SH_lDZ
@INPUT;
SER
@INPUT;
QH
@OUTPUT;
QHZ
@OUTPUT;
A
. TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-131
SN54ASC165,SN74ASC165
PARALLEL·LOAD 8·BIT ~HIFT REGISTERS
HDL FILE (Continued)
STRUCTURE
A01
FFA
FFB
FFC
FFD
FFE
FFF .
FFG
FFH
INV1
INV3
NA01
NA02
NA03
NA04
NA05
NAOS
NA07
NAOa
NA09
NA10
NA11
NA12
NA13
NA14
NA15
NA16
END S165LH;
•
o
I»
1+
I»
tn
::r
CD
CD
1+
(I)
:A0221LH
:DFB20LH
:DFB20LH
:DFB20LH
:DFB20LH
:DFB20LH
:DFB20LH
:DFB20LH
:DFB20LH
:IV140LH
:IV140LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
SH_ LDZ,CLK,SH _ LDZ,CLKINH,AO 10;
NA020,NA010,SER,INV30,FFAQ,DUM;
NA040,NA030,FFAQ,INV30,FFBQ,DUM;
NA060,NA050,FFBQ,INV30,FFCQ,DUM;
NAOaO,NA070,FFCQ,INV30,FFDQ,DUM;
NA 100,NA090,FFDQ,INV30,FFEQ,DUM;
NA 120,NA 11 0,FFEQ,INV30,FFFQ,DUM;
NA 140,NA 130,FFFQ,INV30,FFGQ,DUM;
NA 160,NA 150,FFGQ,INV30,QH,QHZ;
SH_LDZ,INV10;
A010,INV30;
A,INV1 0,NA01 0;
NA01 0,INV1 0,NA020;
B,INV10,NA030;
NA030,INV10,NA040;
C,INV10,NA050;
NA050,INV10,NA060;
D,INV10,NA070;
.
NA070,INV10,NAOaO;
E,INV10,NA090;
NA090,INV1 O,NA 100;
F,INV10,NA110;
NA 11 0,INV1 O,NA 120;
G,INV1 O,NA 130;
NA 130,INV1 O,NA 140;
H,INV1 O,NA 150;
NA 150,INV1 O,NA 160;
shift definition
These registers are unidirectional with respect to shift operations and the relationship for shifting left or
right is defined by the IC designer. Bidirectional registers are available in software macros or can be
constructed using the' ASC2405 through 'ASC2407 4-bit predesigned registers.
designing for. testability
Designers employing storage or bistable elements, especially long registers (ripple or synchronous). should
consider testability of the design in its final form. The need to preset or clear and read intermediate stages
of these elements should be assessed throughout the development of custom logic circuits with these
considerations extended to the end-equipment application with respect to maintainability. Simple actions
on the part of the ASIC designer can result in considerable cost savings, allowing the expense of Ie testing,
system testing, and system maintenance to be reduced significantly.
4-132
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC166, SN74ASC166
PARALLEL·LOAD 8·BIT SHIFT REGISTERS WITH DIRECT CLEAR
02939. AUGUST 1986
SystemCell™
2·",m SOFTWARE MACRO CELL
logic symbol t
•
Synchronous Load
•
Direct Overriding Clear
•
Parallel-to-Serial Conversion
SRGS
CLRZ
SH_LOZ
•
Direct Clear
•
Embedded Clock Drivers Provide Clock
Buffering
•
Dependable Texas Instruments Quality and
Reliability
CLKINH
CLK
SER
2.30
A
-I
~2;.;.3;.;D_ _ _
B
c
o
description
E
The SN54ASC166 and SN74ASC166 are
F
standard-cell software macros implementing
G
B-bit parallel-in shift registers. The B-bit
H
QH
configuration provides the custom IC designer
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
a register to embed in ASICs in its most efficient
IEC Publication 617-12.
form.
Its
B-bit
length
simplifies
construction of large counters. The 'ASC 166
implements a shift sequence identical with that performed by packaged 'HC 166 and 'LS 166 registers.
The' ASC 166 is an B-bit serial shift register that, when clocked, shifts the data toward serial output QH.
Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a
low level at the SH_LDZ input. The' ASC166 also features a clock inhibit function and a direct clear input.
The' ASC166 is implemented with the standard cell functions indicated. The HDL netlist label for this
software macro is shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USED
TOTAL
TOTAL
RELATIVE
MAXIMUM ICC
(nA)
CELL AREA
Cpd*
(pF)
AN221LH
2.7
8
21.6
4.72
1792
107.2
IV110LH
0.75
9
6.75
3.96
945
56.88
IV120LH
1
2
2
1.6
262
15.7
IV140LH
1
1.5
1.61
190
OR210LH
1.5
1.5
1
1.5
0.86
185
11.4
11.1
R2405LH
23.25
2
46.5
20.4
5294
318
TOTALS
23
79.85
33.15
Label: S166LH A,8,C,D,E,F,G,H,CLK,CLKINH,SER,SH _ LDZ,CLRZ,QH;
8668
521
TO NA210LH
•
SN54ASC'
SN74ASC'
:l:The equiv,slent power dissipation capacitance does not include interconnect capacitance.
PRODUCTION DATA documonts onntain inform.tion
curraat .s af publication dat•. ProduelS conform 10
.pooill••ti... par tho tarma af T_I Instrumo.ts
=~~~.[:~':.'1.; ,:::\:~~n
.ot
:.:o::::::::.::.s
Copyright @ 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
4-133
SN54ASC166, SN74ASC166
PARALLEL·LOAD 8·BIT SHIFT REGISTERS WITH DIRECT CLEAR
The parallel-in-or serial-in modes are established by the shift/load input. When high, this input enables the
serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When the shift
load input is low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the
next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the lowto-high-Ievel edge of the clock pulse through a two-input positive NOR gate permitting one input to be
used as a clock-enable or clock-inhibit function. Holding either of the clock inputs high inhibits clocking;
holding either low enables the other clock input. This allows the system clock to be free-running and the
register can be stopped on command with the other clock input. The clock-inhibit input should be changed
to the high level only when the clock input is high. A direct clear input, when taken low, overrides all other
inputs, including the clock, and resets all flip-flops to zero.
The SN54ASC166 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC166 is characterized for operation from -40°C to 85°C.
FUNCTION TABLE
INTERNAL
INPUTS
OUTPUTS
ClRZ
SH
l
H
II
c
....
lDZ
X
X
ClKINH
ClK
SER
A ... H
X
X
L
L
X
X
X
X
t
t
x
a.... h
a
H
X
t
t
L
X
H
L
L
H
H
L
H
H
L
H
X
H
OUTPUT
OH
GA
L
OB
L
L
GAo
aBo
b
aHo
h
H
aAn
aG n
X
L
aAn
X
GAO
aBO
aG n
aHo
D)
D)
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
t/)
::r
(1)
....en
(1)
timing requirements
4-134
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation produce workstation output used
to identify and resolve each specific timing need.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS; TEXAS 76265
SN54ASC166. SN74ASC166
PARALLEL· LOAD 8·BIT SHIFT REGISTERS WITH DIRECT CLEAR
logic diagram
\V11OLx
ClRZ
y
A
INV2
ClK
CLKINH
~______________~A~~1OLX>~y____________________~-,
B
OR1
SEA
SH.lOZ
A
01
Cl2
B
Q3
04
II...
C
o
Q)
Q)
.s::.
en
...caca
o
C
Q1
Cl2
Q3
..,04"'--1-____-1>
QH
G
H
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4·135
SN54ASC166, SN74ASC166
PARALLEL·LOAD 8·BIT SHIFT REGISTERS WITH DIRECT CLEAR
typical clear, shift, load, inhibit, and shift sequences
CLOCK
"'L:
!l
I
CLOCK INHIBIT
CLEAR~~I------------------~~----~I----~I~~--------------------
I
SERIAL INPUT
SHIFT/LOAD
I
I
I
~=:~~I..:~=======t::::j:=:::;-"t:;::=t:= + = = = = = = = = = = =
-+---------------------
L-ur----+I
I
I
A__~~----~----------+__+---IGiInI
I
I
B __~~________________~~----~L~I----~~-------------------I
PARALLEL
INPUTS
C __~~----------------~_+---'nnn~--_+_+--------------------I
D
I __
E
_____________________
LI
~~
~~
I
F __~~----------------~_+----~L~I----~+_----------~-------I
•
C
G __~~______~________~_+---'r.rr~---+-+--------------------I
H__rl~----------------~--~--Jr.in~--+_+_-------------------I
I
OUTPUT QH :.:~'--'--________________..J
I liII!4fo--- SERIAL SHIFT - - - - - - - . !
CLEAR
I»
....
I»
en
:::r
CD
....enCD
4·136
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DAL.LAS, TEXAS 75265
SN54ASC166, SN74ASC166
PARALLEL·LOAD S·BIT SHIFT REGISTERS WITH DIRECT CLEAR
electrical characteristics
PARAMETER
TEST CONDITIONS
VT
Input threshold voltage
ICC
Supply current
Ci
VCC - 5 V,
SN74ASC166
TYP
TYP
TA
Input capacitance
~
MAX
2.2
TA - 25°C
VCC - 4.5 V to 5.5 V, VI .- VCC or 0,
MIN to MAX
0.13
0.13
CLK,CLKINH
0.11
0.11
0.13
0.13
0.24
0.24
33.03
33.03
VCC ~ 5 V,
TA ~ 25°C
~
Equivalent power
VCC
dissipation capacitance t
TA ~ 25°C
5 V,
tr
~
tf
~
3 ns,
UNIT
V
521
A thru H
SER
MAX
2.2
8668
SH_LDZ
Cpd
SN54ASC166
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Note 1)
PARAMETER*
tpd
tpHL
Atpd
AtPHL
FROM
TO
TEST
(lNPUTI
(OUTPUT)
CONDITIONS
CLK
QH
CLRZ
QH
Any
QH
0.3
0.9
2.3
0.3
0.9
2.1
ns/pF
CLRZ
QH
0.3
0.7
1.9
0.3
0.7
1.6
ns/pF
SN54ASC166
TYP§
MAX
MIN
CL ~ 0
SN74ASC166
TYP§
MAX
MIN
UNIT
12.5
11.3
ns
7.7
7.1
ns
t Propagation delay times are measured from the 44% pOint of VI to the 44% point of Vo with tr = tf '" 3 ns (10% and 90%).
tpd :;;;;. propagation delay time, low-ta-high or high-to-Iow-Ievel output
tpHL ,. propagation delay time, high-to-Iow-Ievel output
.6.tpd == change in tpd with load capacitance
AtPHL ,. change in tpHL with load capacitance
§ Typical values are at VCC = 5 V, T A = 25°C.
NOTE1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
II
....
en
CD
.!
en
....caca
Q
4-137
SN54ASC166, SN74ASC166
PARALLEL·LOAD 8·BIT SHIFT REGISTERS WITH DIRECT CLEAR
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie·off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
HDL FILE
II
C
I»
1"+
I»
(I)
:::r
CD
CD
1"+
o
4·138
BLOCK S166LH; .
A
@INPUT;
B
@INPUT;
C
@INPUT;
D
@INPUT;
E
@INPUT;
F
@INPUT;
G
@INPUT;
H
@INPUT;
CLK
@INPUT;
CLKINH
@INPUT;
SER
@INPUT;
SH_LDZ
@INPUT;
CLRZ
@INPUT;
QH
@OUTPUT;
STRUCTURE
A01
A02
A03
A04
A05
A06
A07
A08
FF14
FF58
INV1
INV10
INV11
INVi2
IIw2
INV3
INV4
INV5
INV6
INV7
INV8
INV9
OR1
END S166LH;
:A0221LH
:A0221LH
:A0221LH
:A0221LH
:A0221 LH
:A0221LH
:A0221LH
:A0221LH
:R2405LH
:R2405LH
:IV110LH
:IV110LH
:IV110LH
:IV110LH
:IV140LH
:IV120LH
:IV120LH
:IV110LH
:IV110LH
:IV110LH
:IV110LH
:IV110LH
:OR210LH
SER,INV40,INV30,A,A010;
QA,INV40,INV30,B,A020;
QB,INV4o,INV30,C,A030;
QC,INV40,INV30,D,A040;
QD,INV40,INV30,E,A050;
OE,INV40,INV30,F,A060;
QF,INV40,INV30,G,A070;
QG,INV40,INV30,H,A080;
INV20,INV50,INV60,INV70,INV80,OR10,QA,QB,QC,QD;
INV20,INV90,INV1 OO,INV11 0,INV120,OR1 O,QE,QF,OG,QH;
CLRZ,INV1 0; .
A060,INV100;
A070,INV110;
A080,INV120;
INV10,INV20;
SH_LDZ,INV30;
INV30,INV40;
A010,INV50;
A020,INV60;
A030,INV70;
A040,INV80;
A050,INV90;
CLK,CLKINH,OR10;
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN54ASC166. SN74ASC166
PARALLEL-LOAD 8-BIT SHIFT REGISTERS WITH DIRECT CLEAR
shift definition
These registers are unidirectional with respect to shift operations. Bidirectional registers are available in
software macros or can be constructed using the' ASC2405 through' ASC2407 4-bit predesigned registers.
designing for testability
Designers employing storage or bistable elements, especially long registers (ripple or synchronous), should
consider testability of the design in its final form. The need to preset or clear and to read intermediate
stages of these elements should be assessed throughout the development of custom logic circuits with
these considerations extended to the end-equipment application with respect to maintainability. Simple
actions on the part of the ASIC designer can result in considerable cost savings, allowing the expense
of IC testing, system testing, and system maintenance to be reduced significantly.
power-up clear
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of the clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an AND gate.
II...
U)
Q)
Q)
~
UJ
...
C'O
C'O
C
TEXAS .",
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
4-139
II
o
....
I»
I»
CIl
:r
CD
....CD
(I)
4-140
SN54ASC173, SN74ASC173
4·81T O·TVPE REGISTERS WITH 3·STATE OUTPUTS
D2939, AUGUST 1986
SystemCell™
•
•
•
•
2'/-Im SOFTWARE MACRO CELL
logic symbol t
3·State Outputs Interface Internal Data
Buses Directly
ClR
Direct Clear Input Simplifies Initialization or
Pattern Length
Ml
Nl
Embedded Clock Driver Provides
Symmetrical Performance Across Long
Registers
G1l
G2l
ClK
Parallel Registers for S:Bit, 16·Bit, 32·Bit
Word Widths
01
01
02
02
03
03
04
04
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
description
The SN54ASC173 and SN74ASC173 are standard-cell software macros implementing 4-bit D-type register
elements designed specifically for interfacing internal bus lines. Their four-bit length means that testability
is simplified when constructing large registers, The' ASC173 implements a function table identical with
that performed by packaged 'HC173 and 'LS173 registers.
Gated enable inputs are provided on these macros for controlling the entry of data into the register. When
both data enable inputs, GnZ, are low, data at the D inputs are loaded on the next positive transition of
the clock input. Buffer output enable inputs, MZ and NZ, are also provided. When both are low, the normal
logic states (high or low levels) of the four outputs are impressed on the data bus, The outputs are disabled
by a high logic level at either output control input, The outputs then present a high impedance to the internal
bus. When the outputs are disabled, sequential operation of the flip-flops is not affected. The' ASC173
is iml?lemented with the standard cell functions indicated. The HDL netlist label for this software macro
is shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USED
TO NA210LH
TOTAL
TOTAL
RELATIVE
Cpd*
IpFI
CELL AREA
til
CI)
CI)
.c
CJ)
...caca
C
MAXIMUM ICC
InAI
SN54ASC'
SN74ASC'
IV120LH
1
2
2
1.6
262
15.7
IV222LH
2
4
8
3.92
972
58.4
NA210LH
1
12
12
6.12
1572
94.08
N0210PH
1
2
2
0.66
256
15.42
R2406LH
26.25
1
26.25
11.7
2931
176
21
50.25
24
5993
360
TOTALS
II
...
Label: S173LH D1.D2.D3.D4.CLK,CLR.G1 Z.G2Z.MZ.NZ,01 ,02.03.04;
:l:The equivalent power diSSipation capacitance does not include interconnect capacitance.
PRODUCTIOII DATA d.cumants contain information
currant 8S of publication data. Products conform to
specifications par the terms of Texas Instruments
::'=i~8{::I~lJi =~:~:r lIr:=::;:.~ not
Copyright © 1986, Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 665012 • DAll.AS. TEXAS 75265
4-141
SN54ASC173, SN74ASC173
4·81T O·TYPE REGISTERS WITH 3·STATE OUTPUTS
The SN54ASC173 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC173 is characterized for operation from - 40°C to 85 DC.
FUNCTION TABLE
(EACH FLIP-FLOP) (see Note 1)
INPUTS
OUTPUT
CLR
C,LK
G1Z
G2Z
H
X
L
L
X
X
L
t
t
t
t
H
X
X
X
0
X
X
X
X
H
H
L
L
L
L
L
H'
L
L
L
Q
L
00
00
00
L
H
00 = level of 0 before the indicated steadystate input conditions were established.
NOTE 1: When either MZ or NZ (or both) is
(are) high, the output is disabled to
the high-impedance state; however,
sequential operation of the flip-flops
is not affected .
•
logic diagram
CLK
C
....
I»
I»
CJ)
:::r
CD
CD
....
en
Q1
Q2
os
Q4
y
4-142
TEXAS •
INSTRUMENTS
POST'OFFlce BOX 655012 • DALLAS. TEXAS 75265
SN54ASC173, SN74ASC173
4-81T O-TYPE REGISTERS WITH 3-STATE OUTPUTS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most'
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements are made during pre-layout simulation that produce workstation output
used to identify and resolve each specific timing need.
electrical characteristics
PARAMETER
TEST CONDITIONS
VT
Input threshold voltage
ICC
Supply current
VCC - 4.5 V to 5.5 V, VI - VCC or 0,
TA
=
Input capacitance
On
=
VCC
TA
5 V,
=
25°C
MZ, NZ
OutpUt capacitance
VCC - 5 V,
TA - 25°C
Equivalent power
5 V,
VCC
TA = 25°C
tr
dissipation capacitance t
tf
MAX
2.2
5993
MINto MAX
GnZ
Cpd
TYP
MAX
2.2
ClK
Co
SN74ASC173
TYP
TA - 25°C
VCC - 5 V,
ClR
Ci
SN54ASCl73
V
360
0.24
0.24
0.24
0.24
UNIT
nA
0.12
0.12
0.11
0.11
0.11
0.11
0.33
0.33
pF
24
24
pF
3 ns,
•
pF
...
II)
Q)
Q)
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
.s::.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Notes 2 and 3)
*
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
tpd
ClK
Q
tpHl
ClR
Q
MZ,NZ
Q
Any
Q
Any
Q
PARAMETER
ten
Atpd
6.t en
CL
SN54ASC173
TYP§ MAX
MIN
SN74ASC173
TYP§ MAX
UNIT
...caca
C
MIN
7.1
15.2
7.1
13.8
ns
5.5
11.5
5.5
10.3
ns
3.9
8.2
3.9
7.4
ns
0.3
0.9
2.3
0.4
0.9
2.1
ns/pF
0.4
0.9
2.3
0.5
0.9
2.1
ns/pF
=0
rn
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%),
tpd '" propagation delay time, low-to-high or high-to-Iow output
ten e; enable time, high-impedance state to low- or high-logic-level output
tPHL '" propagation delay time, high-to-Iow output
~tpd ;;;;;; change in tpd with load capacitance
boten ;;;;; change in ten with load capacitance
§Typical values are at V CC = 5 V, TA = 25 ·C.
NOTES: 2. These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Actual performance can be evaluated at post-layout simulation.
3. Enable and delta-enable times are measured using the conditions specified for the 'ASC2311 (lV222LH).
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
4-143
SN54ASC173, SN74ASC173
4·81T O·TYPE REGISTERS WITH 3·STATE OUTPUTS
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HOL for this soft macro is included as a part of the library supplied for supported engineering workstations so that a single label can be developed to apply the macro as needed.The following printout of
the HOL block definition is furnished for reference.
HDL FILE
•
BLOCK S173LH;
01
@INPUT;
02
@INPUT;
03
@INPUT;
04
@INPUT;
CLK
@INPUT;
CLR
@INPUT;
G1Z
@INPUT;
G2Z
@INPUT;
MZ
@INPUT;
NZ
@INPUT;
Q1
@OUTPUT;
Q2
@OUTPUT;
Q3
@OUTPUT;
Q4
@OUTPUT;
STRUCTURE
G01
G02
G03
G04
INV2
INV6
NA1
NA10
NA11
NA12
NA2
NA3
NA4
NA5
NA6
NA7
NA8
NA9
N01
N02
FF14
:IV222LH
:IV222LH
:IV222LH
:IV222LH
:IV120LH
:IV120LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:N0210LH
:N0210LH
:R2406LH
QAZ,N020,Q1;
QBZ,N020,Q2;
QCZ,N020,Q3;
QOZ,N020,Q4;
CLR,INV20;
N010,INV60;
QA,INV60,NA 10;
NA30,NA40,NA 100;
NA50,NA60,NA 110;
NA70,NA80,NA 120;
N01 0,01 ,NA20;
QB,INV60,NA30;
N010,02,NA40;
QC,INV60,NA50;
N010,03,NA60;
QO,INV60,NA70;
N010,04,NA80;
NA 10,NA20,NA90;
G1Z,G2Z,N010;
MZ,NZ,N020;
INV20,NA90,NA 1OO,NA 11 O,NA 120,CLK,QA,QAZ,QB,QBZ,QC,
QCZ,QO,QOZ:
END S173LH;
4-144
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC173, SN74ASC173
4-81T O-TYPE REGISTERS WITH 3-STATE OUTPUTS
designing for testability
Designs employing storage or bistable elements, especially long registers (ripple or synchronous), should
consider testability of the design in its final form. The need to preset or clear and read intermediate stages
of these elements should be assessed throughout the development of custom logic circuits with these
considerations extended to the end-equipment application with respect to maintainability. Simple actions
on the part of the ASIC designer can result in considerable cost savings, allowing the expense of IC testing,
system testing, and system maintenance to be reduced significantly.
power-up clear/preset
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected through an inverter to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve
system initialization. Control of the clear or preset inputs from another system signal in conjunction with
the power-up clear can be achieved with an OR gate.
II
...
U)
II)
II)
.c
en
...
CO
CO
C
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-145
•
c
Q)
r+
Q)
C/)
:::r
CD
CD
r+
til
4-146
SN54ASC174, SN74ASC174
HEX OoTYPE FLIP-FLOPS
D2939, AUGUST 1986
SystemCell™
•
•
•
2-J.lm SOFTWARE MACRO CELL
logic symbol t
Six-Bit Register
Direct Clear Input Simplifies Initialization or
Pattern Length
CLRZ
CLK
Clock Buffer Provides Symmetrical
Performance Across Long Registers
description
Dl
01
D2
02
D3--
03
D4
04
05
D5
The SN54ASC174 and SN74ASC174 are
06
standard-cell software macros implementing a
D6
6-bit D-type register element for embedding in
t This symbol is in accordance with ANSI/lEEe Std 91-1984 and
ASICs in its most efficient form. Its 6-bit length
IEC Publication 617-12.
simplifies construction of large counters. The
'ASC174 implements a function table identical
with that performed by packaged 'HC174, 'LS174, and 'F174 registers. It may be customized to meet
specific systems requirements.
This software macro reduces the input loading for implementation of larger registers, as standard library
cells are used to buffer the clear and clock inputs to further enhance performance across long registers.
The' ASC174 is implemented with the standard cell functions indicated. The HDL netlist label for this
software macro is shown on the last line of the following table:
4
en
~
CELL NAME
RELATIVE
CELL AREA
TOTAL
RELATIVE
NO. USED
TO NA210LH
CELL AREA
0,75
IVll0LH
2
1.5
TOTAL
Cpd*
(pFI
0,88
SN54ASC'
210
.c
SN74ASC'
tn
12.64
IV140LH
1,5
2
3
3.22
380
22.8
DFC20LH
7,2
6
43.2
20.34
5286
317.4
10
47.7
24.44
5876
353
TOTALS
Q)
Q)
MAXIMUM ICC
(nAI
ca
ca
~
C
Label: S174LH 01 ,D2,D3,D4,D5,D6,CLK,CLRZ,Ql ,Q2,Q3,Q4,Q5,Q6;
+The equivalent power dissipation capacitance does not include interconnect capacitance.
The SN54ASC174 is characterized for operation over the full military temperature range of - 55 DC to
125 DC, The SN74ASC174 is characterized for operation from - 40 DC to 85°C.
FUNCTION TABLE
(EACH FLiP-FLOPI
INPUTS
CLRZ CLK
PRODUCTION DATA dooum~." oOR"i. inlorm.ti••
ou,ra.t .s of publlostio. data. Products co.farm to
_iliostlo•• PO' the torms of T.... Instruments
standard warranty. PrJHIuctian ~raC8lsiJta dolS not
.......rily inolude tasting 01 III poramiltar•.
OUTPUT
On
Q
L
X
X
L
H
H
t
t
H
H
L
L
H
L
X
QO
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTs
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
4-147
SN54ASC174, SN74ASC174
HEX O·TYPE FLlp·FLOPS
logic diagram
DFC201.x
r---=CK~~C1
Q
Q1
01
CLRZ
OFC201.x
Q2
02
"1V11Otx
1V1401.x
CLK
DfC201.x
Q3
03
•
OFC201.x
Q4
04
...C
I»
I»
rn
DFC20Lx
=-
CD
CD
...
D6
(I)
DFC201.x
Q6
D6
absolute"maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarc;ling pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre·layout simulation produce workstation output used
to identify and resolve each specific timing need.
4·148
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC174. SN74ASC174
HEX O·TYPE FLlp·FLOPS
electrical characteristics
PARAMETER
VT
·Iec
Ci
VCC ~ 5 V,
Input threshold voltage
SN54ASC174
SN74ASC174
TYP
TYP
TA ~ 25°C
Supply current
I
CLRZ
(
On
I
eLK
TA
Vce - 5 V,
~
25°C
tr - tf - 3 ns,
TA ~ 25°C
dissipation capacitance t
UNIT
V
353
0.12
Vee ~ 5 V,
MAX
2.2
5876
TA ~ MIN to MAX
Input capacitance
MAX
2.2
Vee - 4.5 V to 5.5 V, VI - Vee or 0,
Equivalent power
Cpd
TEST CONDITIONS
nA
0.12
0.11
0.11
0.12
0.12
24.44
24.44
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of operating free-air temperature and supply voltage
.
(unless otherwise noted) (see Note 1)
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
tpd
CLK
Q
tpHL
CLRZ
Q
<1tpd
Any
Q
PARAMETER*
SN54ASC174
TYP§
MAX
MIN
CL ~O
0.1
SN74ASC174
TYP§
MAX
UNIT
ns
MIN
8
17.4
8
15.6
5.1
9.5
5.1
8.8
0.5
1.1
0.5
1
0.1
ns
nslpF
*Propagation delay times are measured from the 44% point of VI to the 44% point c~ Vo with tr ~ tf ~ 3 ns (10% and 90%).
tpd '" propagation delay time, low-to-high-Ievel or high-to-Iow-Ievel output
tPHL '" propagation delay time, high-to-Iow output
.6.tpd 5 change in tpd with load capacitance
§ Typical values are at Vec ~ 5 V, T A ~ 25°C.
NOTE1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
.
•
....
U)
CJ)
CJ)
.c
t/)
....COCO
C
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the mitlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-149
SN54ASC174, SN74ASC174
HEX O·TYPE FLlP·FLOPS
HDL FILE
BLOCK S174LH;
D1
@INPUT;
D2
@INPUT;
D3
@INPUT;
D4
@INPUT;
05
@INPUT;
D6
@INPUT;
CLK
@INPUT;
CLRZ
@INPUT;
01
@OUTPUT;
02
@OUTPUT;
03
@OUTPUT;
04
@OUTPUT;
05
@OUTPUT;
06
@OUTPUT;
STRUCTURE
FF1
FF2
FF3
FF4
FF5
FF6
INV1
INV2
INV3
INV4
END S174LH:
III
C
I»
r+
I»
tn
::T
CD
CD
:DFC20LH
:OFC20LH
:OFC20LH
:OFC20LH
:DFC20LH
:DFC20LH
:IV110LH
:IV140LH
:IV110LH
:IV140LH
INV20,D1 ,INV40,01 ,DUM:
INV20,D2,INV40,02,DUM;
INV20,D3,INV40,03,DUM;
INV20,D4,INV40,04,DUM;
INV20,D5,INV40,05,DUM;
INV20,D6,INV40,06,DUM;
CLRZ,INV10;
INV10,INV20;
CLK,INV30;
INV30,INV40;
r+
CI)
designing for testability
Designs employing storage or bistable elements, especially long registers (ripple or synchronous), should
consider testability of the design in its final form. The need to preset or clear and read intermediate stages
of these elements should be assessed throughout the development of custom logic circuits with these
considerations extended to the end-equipment application with respect to maintainability. Simple actions
on the part of the ASIC designer can result in considerable cost savings, allowing the expense of IC testing,
system testing, and system maintenance to be reduced significantly.
power-up clear/preset
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of the Clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an AND gate.
4-150
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC175, SN74ASC175
QUADRUPLE D·TYPE FLlp·FLOPS WITH COMPLEMENTARY OUTPUTS
02939, AUGUST 1986
SystemCelr
M
2-j.lm SOFTWARE MACRO CELL
logic symbol t
•
Four-Bit Register with Complementary
Outputs
•
Direct Clear Input Simplifies Initialization or
Pattern Length
•
Embedded Clock Driver Provides Clock
Buffering
•
CLRI
CLK
01
01
011
02
02
Parallel Latches for a-Bit, 16-Bit, 32-Bit
Word Widths
021
03
03
03Z
04
04
description
04Z
The SN54ASC175 and SN74ASC175 are
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
standard-cell software macros implementing a
IEC Publication 617-12.
4-bit register element for embedding in ASICs.
Its 4-bit length simplifies construction of large
registers. The' ASC175 implements a function table identical with that performed by packaged 'HC175,
'LS175, and 'F175 registers.
This macro reduces the input loading for implementation of larger registers, as standard library cells are
used to buffer the clear input and the R2406lH register clock input is internally buffered. The' ASC175
is implemented with the standard cell functions indicated. The HDl netlist label for this software macro
is shown on the last line of the following table:
II
...
fI)
Q)
Q)
.c
RELATIVE
CELL NAME
CELL AREA
NO. USED
TO NA210LH
TOTAL
TOTAL
RELATIVE
Cpd*
(pF)
CELL AREA
SN54ASC'
...caca
SN74ASC'
IVll0LH
0.75
1
0.75
0.44
105
6.32
IV140LH
R2406LH
1.5
26.5
1
1.61
11.69
190
2931
11.4
1
1.5
26.5
3
28.5
13.74
3226
194
TOTALS
U)
MAXIMUM ICC
(nA)
C
176
Label: S175LH D1 ,D2,D3,D4,CLK,CLRZ,01 ,Q1Z,Q2,Q2Z,Q3,Q3Z,Q4,Q4Z;
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
The SN54ASC175 is characterized for operation over the full military temperature range of - 55 DC to
125°C. The SN74ASC175 is characterized for operation from -40 DC to 85°C.
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
CLRZ CLK
On
X
L
H
H
L
H
X
t
t
L
L
H
H
L
X
00
00
L
H
PRODUCTION DATA documents .o.lai. information
current as of publication data. Products conform to
spacifications per-the terms of Taxas Instruments
:'=~~i;a[::1~1e ~=::i:r :1~o::::9t::ae:s not
OUTPUTS
QZ
0
H
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1986, Texas Instruments Incorporated
4-151
•
SN54ASC175, SN74ASC175
QUADRUPLE D·TYPE FLlp·FLOPS WITH COMPLEMENTARY OUTPUTS
logic diagram
R2408Lx
CLK
>-..........~~~...............~~~.....~..........CL~K~
FQ~l~..............................~
Q,'
Q1Z
CLRZ
Q2
01
Q2Z
02
Q3
03
FF14
Q3Z
04
Q4
Q4Z
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2 .
timing requirements
III
Specific tim'ing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation produce workstation output used
to identify and resolve each specific timing need.
C
I»
pot.
I»
(/)
electrical characteristics
::r
CD
CD
pot.
rn
.
PARAMETER
VT
Input threshold voltage
lee
Supply current
ei
Input capacitance
epd
TEST CONDITIONS
SN74ASC175
TYP
TYP
I
I
On
I
elK
Equivalent power
Vee = 5 V.
dissipation capacitance t
TA = 25°e
0.12
0.13
0.13
0.24
0.24
I r =lf=3ns,
13.74
13.74
int~rconnect capacitance.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
UNIT
V
194
0.12
TA = 25°e
MAX
2.2
3226
elRZ
Vee = 5 V,
MAX
2.2
TA = 25°e
Vee = 5 V,
Vee - 4.5 V 10 5.5 V, VI - Vee or 0,
TA = MIN to MAX
t The equivalent power dissipation capacitance does not include
4-152
SN54ASC175
nA
pF
pF
SN54ASC175. SN74ASC175
QUADRUPLE D·TYPE FLlP·FLOPS WITH COMPLEMENTARY OUTPUTS
switching characteristics over recommended ranges of operating free-air temperature and supply voltage
(unless otherwise noted) (see Note 1)
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
tpd
CLK
Q
tpd
CLK
QZ
PARAMETERt
tPLH
tpHL
CLRZ
QZ
CLRZ
Q
L>tpd
CLK
Q
CL
SN54ASC175
Typt
MAX
=0
0.2
SN74ASC175
TYP*
MAX
5
10.6
5
9.6
5.5
12.5
5.5
MIN
MIN
6
10.4
6
11.3
9.4
5.4
8.3
5.4
7.7
0.9
2.3
0.9
2.1
0.3
UNIT
ns
ns
ns/pF
t Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tpd s propagation delay time. low-to-high-Ievel or high-to-Iow-Ievel output
tpLH '" propagation delay time. low-to-high-Ievel output
tpHl ;;;;; propagation delay time, high-to-Iow-Ievet output
L>tpd '" change in tpd with load capacitance
Typical values are at VCC = 5 V. T A = 25 ·C.
NOTE1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
*
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HOL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HOL block definition is furnished for reference.
rn
CD
CD
.c
en
...asas
HDL FILE
C
BLOCK S175LH;
01
@INPUT;
02
@INPUT;
03
@INPUT;
04
@INPUT;
CLK
@INPUT;
CLRZ
@INPUT;
Q1
@OUTPUT;
Q1Z
@OUTPUT;
Q2
@OUTPUT;
Q2Z
@OUTPUT;
Q3
@OUTPUT;
Q3Z
@OUTPUT;
Q4
@OUTPUT;
Q4Z
@OUTPUT;
STRUCTURE
FF14
:R2406LH
INV1
:IV110LH
:IV140LH
INV2
END S175LH:
II
...
INV20,01 ,02,03,04,CLK,Q1 ,Q1 Z,Q2,Q2Z,Q3,Q3Z,Q4,Q4Z;
CLRZ,INV10;
INV10,INV20;
TEXAS
-II
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-153
SN54ASC175, SN74ASC175
QUAORUP~E OoTYPE FLIP-FLOPS WITH COMPLEMENTARY OUTPUTS
designing for testability
Designs employing storage or bistable elements, especially long registers (ripple or synchronous), should
consider testability of the qesign in its final form. The need to preset or clear and read intermediate stages
of these eleml'lnts should be assessed throughout the development of custom logic circuits with these
considerations extended to the end-equipment application with respect to .maintainability. Simple ·actions
on the part of the ASIC qesigner can result in considerable cost savings, ~lIowing the expense of IC testing,
system testing, and system maintenance to be reduced significantly.
.
power-up clear/preset
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of the clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an AND gate.
II
4-154
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TEXAS 76265
SN54ASC177. SN74ASC177
1-BIT AND 3-BIT BINARY RIPPLE COUNTERS
D2939, AUGUST 1986
SystemCelJ1'"
2-llm SOFTWARE MACRO CELL
logic symbol t
•
Individual 1-Bit and 3-Bit Counters for
Implementing Custom Count Sequences
•
Asynchronous Clear Initializes Sequence
Regardless of Mode
•
Parallel Asynchronously Presettable for
Modulo-N Sequel"!ces
•
Performs Ripple-Count or Simple Latching
Functions
LOADZ
CLRZ
CLK1Z
OA
lD
A
description
DIVS
The SN54ASC177 and SN74ASC177 are
standard-cell software macros implementing
1-bit and 3-bit ripple counter elements. The
overall 4-bit configuration provides the custom
IC designer a multifunction counter/latch to
embed in ASICs in its most efficient form, and
its 4-bit length simplifies construction of large
counters, The 'ASC 177 implements a count
sequence identical with that performed by
packaged' ASC177 counters.
08
8
oc
C
OD
D
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and . .
IEC Publication 617-12.
. .
RELATIVE
CELL NAME
CELL AREA
NO, USED
TO NA210LH
-TOTAL
TOTAL
RELATIVE
Cpd*
IpF)
CELL AREA
SN54ASC'
CD
CD
.c
en
...caca
o
MAXIMUM ICC
InA)
SN74ASC'
AN220LH
1.75
1
1.75
1.2
228
DFB20LH
7.7
4
30.8
15.04
3736
224
IV110LH
0.75
3
2.25
1.32
315
18.96
13.6
IV140LH
1.5
1
1.5
1.61
190
11.4
NA210LH
NA310LH
1
1.25
4
4
4
2.04
524
31.36
5
2
652
39.12
N0410LH
1.5
1
1.5
0.35
177
10.6
18
46.8
23.56
5822
350
TOTALS
...
II)
These ripple counters consist of four D-type flip-flops that are interconnected to provide a divide-by-two
and a divide-by-eight counter. A divide-by-16 sequence is obtained by connecting the QA output to the
CLK2Z input, During the count operation, transfer of information to the outputs occurs on the negativegoing edge of the clock pulse. The' ASC177 is implemented with the standard cell functions indicated,
The HDL netlist label for this software macro is shown on the last line of the following table:
Label: SI77LH A,B,C,D,LDADZ,CLRZ,CLK 1Z,CLK2Z,QA,QB,QC,QD;
+The equivalent power dissipation capacitance does not include interconnect capacitance.
PRODUCTION DATA documents contain Information
.urrent as of publication datil. Products ".form 10
specifications per the lonna of Toni I••trumants
:.:=~;ai:I~I,; ~~~:l' :.:o;::::lt:~~!lot
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright @ 1986, Texas Instruments Incorporated
4-155
SN54ASC1l7, SN74ASC177
1:BIT .AND 3·B11 BINARY RIPPLE COUNTERS
The counter is fully programmable; that is, it may be preset to any number between 0 and 15. As presetting
is asynchronous, a low level at the load input disables the counter and causes the outputs to agree with
the setup data independently of the level of the clock input.
These counters may be used as 4-bit latches by using the LOADZ input as the strobe and entering data
at the data inputs. The outputs will directly follow the data inputs while LOADZ is low, but will remain
unchanged while LOADZ is high and the clock inputs are inactive.
Clearing is asynchronous. A low level at the clear input sets all outputs low regardless of the levels of
the clocks or LOADZ.
.
The SN54ASC177 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC177 is characterized for operation from -40°C to 85°C.
FUNCTION TABLE
ISee Note 11
OUTPUTS
INPUTS
II
c
....
Q)
Q)
en
::r
CD
....CD
U)
CLRZ
LOADZ
D
C
B
A
CLK1Z
OD
OC
OB
QA
L
H
L
L
L
d
c
b
a
H
H
L
L
L
H
H
H
L
L
H
L
H
H
X
X
i
i
i
i
i
i
i
t
i
t
t
i
i
L
L
X
b
X
X
X
X
X
X
X
H
X
c
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
L
H
L
L
L
H
L
H
L
H
H
L
L
H
H
L
H
H
L
L
H
L
L
H
H
L
H
L
H
L
H
H
H
H
L
L
H
H
L
H
H
H
H
X
X
H
H
X
d
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
X
H
H
H
H
H
H
H
H
H
H
H
11
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
a
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
L
L
L
L
L
00
00
00
00
See Explanation of Function Tables in Section 1.
NOTE 1: Table applies with output OA connectd to CLK2Z input.
4-156
L
t
i
i
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ASC177. SN74ASC177
1·BIT AND 3·BIT BINARY RIPPLE COUNTERS
logic diagram
IVllOLx
A
CLK1Z
A
1-~--r'")QA
LOADZ
CLRZ
1-.......---t>QB
B r">-----------++;.....!NA4
IVllOLx
CLK2Z r">-_---=A::....j
v
INV4
c
QC
a
D r">-----------++~~~
ao
en
~
Go)
Go)
.c
(J)
co
co
absolute maximum ratings and recommended operating conditions
~
C
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre·layout simulation produce workstation output used
to identify and resolve each specific timing need.
.
electrical characteristics
PARAMETER
TEST CONDITIONS
VT
Input threshold voltage
lee
Supply current
ej
Input capacitance
I
epd
r
r
SN74ASC177
TYP
TYP
Vee = 5 V.
TA = 25°e
All others
Equivalent power
Vee = 5 V,
dissipation capacitance t
TA = 25°e
tr = tf = 3 ns,
MAX
2.2
Vee = 5 V,
TA= 25°e
Vee = 4.5 V to 5.5 V, VI = Vee or 0,
TA = MIN to MAX
LOADZ
eLRZ
SN54ASC177
MAX
2.2
5822
V
350
0.13
0.13
0.25
0.25
0.12
0.12
23.56
23.56
UNIT
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-157
SN54ASC177. SN74ASC177
1·B11 AND 3·B11 BINARY RIPPLE COUNTERS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Note 1)
PARAMETERt
tpd
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
CLK1Z
OA
tpd
tpd
CLK2Z
tpd
SN54ASCl77
MIN
TYP*
SN74ASCl77
MAX
6
6
15
OB
OC
10
28.1
16
41.2
00
CL
=0
MIN
15
MAX
6
6
13.3
ns
13.3
ns
10
16
24.9
ns
36.5
ns
10.6
12,4
ns
tpd
A,B,C,D
Any
5
11.5
tpd
LOADZ
Any
7
13.9
5
7
CLRZ
Any
RCO
5,4
21.3
5,4
19.4
0.5
1.3
0.5
1.2
tpd
lltpd
Any
0.1
0.1
UNIT
TYP*
ns
no
ns/pF
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tpd '" propagation delay time, low-to-high-Ievel or high-to-Iow·level output
lltpd .. change in tpd with load capacitance
Typical values are at VCC = 5 V, TA = 25°C.
NOTE 1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
*
II
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
HDL FILE
BLOCK Sl77LH;
A
@INPUT;
B
@INPUT;
C
@INPUT;
D
@INPUT;
LOADZ
@INPUT;
CLRZ
@INPUT;
CLK1Z
@INPUT;
CLK2Z
@INPUT;
OA
@OUTPUT;
OB
@OUTPUT;
OC
@OUTPUT;
OD
@OUTPUT;
4-158
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
SN54ASC177, SN74ASC177
1-BIT AND 3-BIT BINARY RIPPLE COUNTERS
HDl (Continued)
STRUCTURE
AN1
FFA
FFB
FFC
FFD
INV1
INV2
INV3
INV4
NA1
NA3
NA4
NA5
NA6
NA7
NA8
NA9
N01
END S177lH;
:AN220lH
:DFB20LH
:DFB20lH
:DFB20LH
:DFB20lH
:IV110lH
:IV110LH
:IV140lH
:IV110lH
:NA310lH
:NA210lH
:NA310LH
:NA210LH
:NA310LH
:NA210LH
:NA310LH
:NA210LH
:N0410lH
LOADZ,ClRZ,AN10;
NA30,NA 1 0,FFAQZ,INV1 O,QA,FFAQZ;
NA50 ,NA40 ,FFBQZ,INV40 ,QB,FFBQZ;
NA 70, NA60, FFCQZ, FFBQZ, QC ,FFCQZ;
NA90,NA80,FFDQZ,FFCQZ,QD,FFDQZ;
ClK1Z,INV10;
ClRZ,INV20;
AN10,INV30;
ClK2Z,INV40;
A,N01 0,INV30,NA 10;
NA 1 0,INV30,NA30;
N010,B,INV30,NA40;
NA40,INV30,NA50;
C,N010,INV30,NA60;
NA60,INV30,NA70;
D,N010,INV30,NA80;
NA80,INV30,NA90;
INV20,INV20,INV20,INV20,N010;
•
...
II)
count definition
These counters ar~ unidirectional with respect to count operation. Inverting the output levels will produce
a down-count sequence. Bidirectional counters are available in software macros 'or can be constructed
using the' ASC2405 through' ASC2407 4-bit predesigned registers. Additional single bits can be achieved
with predesigned flip-flops offered in TI's standard cell family.
designing for testability
CD
CD
.c
CI)
...
CO
CO
C
Designers employing storage or bistable elements, especially long counters (ripple or synchronous), should
consider testability of the design in its final form. The need to preset or clear and read intermediate stages
of these elements should be assessed throughout the development of custom logic circuits with these
considerations extended to the end-equipment application with respect to maintainability. Simple actions
on the part of the ASIC designer can result in considerable cost savings, allowing the expense of IC testing,
system testing, and system maintenance to be reduced significantly.
power-up clear/preset
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of th.e clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an AND gate.
TEXAS •
INSTRUMENTSPOST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-159
c
C»
r+
C»
en
::r
CD
CD
r+
en
4-160
SN54ASC181, SN74ASC181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
02939. AUGUST 1986
SystemCell™
2-j.lm SOFTWARE MACRO CELL
logic symbol t
•
Performs Full 16-Function Arithmetic or
Boolean Combinations of Two Variables
•
Arithmetic Operating Modes:
Addition
Subtraction
Shift Operand A One Position
Magnitude Comparison
Plus Twelve Other Arithmetic Operations
•
};,
so
Sl
S2
S3
ALU
PZ
GZ
AEQB
M
Logic Function Modes:
Exclusive-OR
Comparator
AND, NAND, OR, NOR
Plus Ten Other Logic Operations
CNPL4
CI
CN
AOZ
IIJ
FOZ
[2J
FIZ
[4J
F2Z
[8J
F3Z
BOZ
AIZ
BIZ
description
A2Z
The 5N54A5C181 and 5N74A5C181 are
standard-cell software macro 4-bit arithmetic
logic units. The' A5C 181 implements a function
table identical with that performed by packaged
'L5181, '5181, and 'F181 arithmetic logic
units/function generators.
B2Z
II
A3Z
B3Z
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
The' A5C 181 performs 16 arithmetic or Boolean operations on two 4-bit binary words 'IS shown in Tables 1
and 2. Choice between the two operating modes is established by the mode control, M, and selection
of one-of-sixteen operations is accomplished at the select inputs 53, 52, 51, and 50. The' A5C181 is
implemented with the standard cell functions indicated. The HDL netlist label for this software macro is
shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USED
TOTAL
TOTAL
RELATIVE
Cpd*
(pF)
MAX[MUM ICC
InA)
SN54ASC'
SrI/74ASC'
AN210LH
1.5
9
13.5
8.1
1746
104.4
AN310LH
1.75
9
15.75
9.54
1989
119.7
AN420LH
2.25
1
2.25
1.72
286
17.2
EX210LH
4
8
4.48
EX220LH
2
2.25
4
9
6
892
1032
53.6
62
IVll0LH
0.75
8
6
3.52
840
50.56
IV120LH
1
1
1
0.8
131
7.85
NA210LH
1
4
5
2.55
655
TO NA210LH
CELL AREA
NA220LH
1.5
1
1.5
1
196
:39.2
11.7
NA310LH
NA410LH
1.25
1.5
4
2
6
5
9
3
652
1122
39.12
67.2
NA510LH
1.75
2
3.5
1.04
426
25.6
N0210LH
1
5
5
1.65
38.55
37.32
675
N0310LH
1.25
TOTALS
4
5
1.28
64Q
624
62
89.5
46.68
11231
Label: S181 LH A3Z,A2Z,A 1Z,AOZ.B3Z.B2Z.B1Z.80Z.CN,M,S3.S2.S1.S0.F3Z.F2Z.
F I Z.FOZ.AEQB.GZ.PZ.CNPL4;
tThe equivalent power dissipation capacitance does not include interconnect capacita~ce.
PRODUCTION DA fA doc.manl. contain information
current as of publication date. Products conform to
specifications per the terms of TeXIS Instruments
::=:~~;a{::I~'le =:~ti:r
lIr=::::t::::
s not
Copyright © 1986. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-161
SN54ASC181, SN14ASC181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
When the mode control input is low, the 16 arithmetic operations are accessible via the four select inputs.
The 4-bit fu'li adder incorporates both ripple and look-ahead carry circuitry, providing the capability to extend
either technique across expanded word widths when multiple' 'ASC181s are Llsed in parallel.
The 'ASC181 accommodates both active-high and active-low data'simply by redefining the designations
used to describe the data inputs and outputs. For use with active-low data, use Table 1 and the input/output
designations provided for the label developed above. For use with active-high data. use Table 2.
Note that only the relationships of A, B, and F data with respect to the carrY and look-ahead circuitry are
affected.
Subtraction is accomplished by 1's complement addition in which the 1's complement of the subtrahend
is generated internally. The resultant output is A-B-1, which ret!uires an end-around or forced carry to provide
A-B. Arithmetic operations with and without carry are shown in Tables 1 and 2.
The 'ASC181 also performs a comparison of the A and B operands. The AEOB output is decoded from
the function outputs (F3, F2, F1, and FO) so that, when two words of equal magnitude are applied at the
A and B inputs, it will assume a high level to indicate equality (A = B). The ALU must be in the subtract
mode with CN = H when performing this comparison. The AEOB output can be AND- or NAND-gated
to perform comparisons over expanded ALUs. The CNPL4 carry output can also be used to supply relative
magnitude information. Again, the ALU must be in the subtract mode by having the select inputs S3, S2,
S 1, and SO at L, H, H, L, respectively.
II
INPUT CN
OUTPUT CNPL4
ACTIVE·LOW DATA
(FIGURE 11
ACTIVE-HIGH DATA
(FIGURE 21
H
H
A",B
AsB
H
L
AB
L
H
A>B
A ~
..,
NA21Qb
·..
A'''''''',
A
...,"
au
...caca
C
.,
A NA21C1.>r y
.~
•
,
..
...
-~
~'0I..lc
c::tG88
A'
NA21CLX V
G31
>
A
,
Gall
II NA2I!lt..
•
M10Lx
A
"'"
'"'
.c
I
·""
~Y
U,"'"
CI)
CI)
~.
,
.
U)
U)
~GZIYAf¥I.'Y
7~
II
...
GOO
.
ANA2ICL~
'"
.
~
...,
:~-
·
-+Qv
""
,
... ...
~
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-171
SN54ASC191, SN74ASC191
SYNCHRONOUS. UP/DOWN BINARY COUNTERS WITH DOWN/UP MODE CONTROL
typical load, count, and inhibit sequences
Illustrated below is the following sequence:
Load (preset) to binary thirteen.
Count up to fourteen, fifteen (maximum), zero, one, and two.
Inhibit.
Count down to one, zero (minimum), fifteen, fourteen, and thirteen.
1.
2.
3.
4.
lOADZ--U
I
I
I-I
A--1
L..._
I
I
I
B
r-
,---
I
I
DATA
INPUTS
C--1
II
L..._
0--1
1
--
L..._
ClK
D-UZ - ,
I I
I I
I I
CTENZ - ,
I
I
-
I:
I i-----...
L.iJ
- -,
OB ___
'--__
--I
I I
OC -
--I
- --'
00 - --I
__ .-I
--~
MAX_MIN ___ I
I I
I
I
I I
I
I
I
I
I I
I I
II
I
II
I
I I
I
RCOZ==J
I
I I
I
I 13
I I
I
I
U~
14
U
15
I
0
COUNT UP
I
2
2
I
~I"
INHIBIT
I 2
-.t I----
lOAD
4-172
I
Il
U
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
0
15
COUNT DOWN
14
13
~I
SN54ASC191. SN74ASC191
SYNCHRONOUS UP/DOWN BINARY COUNTERS WITH DOWN/UP MODE CONTROL
absolute maximum ratings and recommended' operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation produce workstation output used
to identify and resolve each specific timing need.
electrical characteristics
PARAMETER
VT
lee
ei
epd
= 5 V,
Vee = 4.5 V to 5.5
TA = MIN to MAX
Input threshold voltage
Vee
Supply current
Input capacitance
~
SN54ASC191
TEST CONDITIONS
eTENZ
All others
Vee
=
TA
V, VI
TA
5 V,
=5
= 25
Equivalent power
Vee
V,
dissipation capacitance
TA
°e
tr
= 25°e
= Vee or 0,
2.2
TYP
MAX
2.2
3 ns,
586
0.34
0.34
0.12
0.12
37.26
37.26
UNIT
V
9763
= 25°e
= tf =
SN74ASC191
MAX
TYP
nA
pF
pF
switchiJ;lg characteristics over recommended ranges of supply voltage and operating free-air temperature.
(unless otherwise noted) (see Note 11
...
fI)
PARAMETERt
FROM
TO
TEST
CONDITIONS
SN54ASC191
Typt MAX
MIN
SN74ASC191
Typt MAX
MIN
(INPUT)
(OUTPUT)
tpd
lOADZ
Q
7.7
15
7.7
13.0
ns
tpd
A,B,C,D
Q
5.9
11.6
5.9
10A
ns
tpd
ClK
Rcaz
2.7
4.5
2.7
4.3
ns
tpd
ClK
Q
8
18
8
16
ns
tpd
ClK
MAX MIN
11.5
25.5
11.5
22.7
ns
tpd
D UZ
ReaZ
6.9
1'3.2
6.9
11.9
ns
tpd
D UZ
MAX MIN
5.9
11.2
5.9
10.1
ns
tpd
CTENZ
RCaZ
2.6
4.8
2.6
4.5
ns
dtpd
Any
Q
0.1
0.5
1.3
0.1
0.5
1.2
ns/pF
dtpd
Any
RCaZ
0.5
1.3
3.8
0.5
ns/pF
Any
MAX MIN
0.5
1.1
2.7
0.5
1.3
1.1
3.2
dtpd
2.5
ns/pF
el
=
°
G)
G)
UNIT
.c
(I)
...caca
C
tpropagation delay times are measured from the 44% point of VI to the 44% point of Va with tr = tf = 3 ns (10% and 90%).
tpd '" propagation delay time, low-to-high-Ievel or high-to-Iow-Ievel .output
dtpd '" change in tpd with load capacitance
tTypical values are at VCC = 5 V, TA = 25°C.
.
NOTE 1: These switching characteristics arS simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post·layout simulation uses actual interconnect capacitance values.
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-173
SN54ASC191, SN74ASC191
SYNCHRONOUS UP/DOWN BINARY COUNTERS WITH DOWN/UP MODE CONTROL
HDL FILE
BLOCK S191 LH;
D
@INPUT;
C
@INPUT;
B
@INPUT;
A
@INPUT;
CLK
@INPUT;
D_UZ
@INPUT;
CTENZ
@INPUT;
LOADZ
@INPUT;
QD
@OUTPUT;
QC
@OUTPUT;
QB
@OUTPUT;
QA
@OUTPUT;
RCOZ
@OUTPUT;
MAX_MIN
@OUTPUT;
•
C
m
r+
m
en
:::r
CD
CD
r+
tn
4-174
STRUCTURE
FF1
FF2
FF3
FF4
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
:DFB20LH
:DFB20LH
:DFB20LH
:DFB20LH
:IV110LH
:IV110LH
:N0210LH
:N0210LH
:NA510LH
:NA510LH
:NA210LH
:NA310LH
:NA210LH
:IV110LH
:IV110LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:IV110LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA310LH
:NA310LH
:NA210LH
:IV110LH
:NA210LH
G150,G090,G140,G440,QA,FF1QZ;
G240,G160,G230,G440,QB,FF2QZ;
G330,G250,G320,G440,QC,FF3QZ;
G420,G340,G410,G440,QD,FF4QZ;
D_UZ,G010; .
G010,G020;
G020,CTENZ,G030;
G010,CTENZ,G040;
G010,QA,QB,QC,QD,G050;
G020,FF1 QZ,FF2QZ,FF3QZ,FF4QZ,G060;
G050,G060,MAX_MIN;
G430,MAX_MIN,G100,RCOZ;
A,G450,G090;
CTENZ,G100;
G100,G110;
QA,G110,G120;
G100,FF1QZ,G130;
G120,G130,G140;
G090,G450,G150;
B,G450,G160;
G040,FF1 QZ,G170;
QA,G030,G180;
G170,G180,G190;
G190,G200;
QB,G200,G210;
G190,FF2QZ,G220;
G210,G220,G230;
G160,G450,G240;
C,G450,G250;
G040,FF1 QZ,FF2QZ,G260;
QA,QB,G030,G270;
G260,G270,G280;
G280~G290;
QC,G290,G300;
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ASC191, SN74ASC191
SYNCHRONOUS UP/DOWN BINARY COUNTERS WITH DOWN/UP MODE CONTROL
HDL FILE (Continued)
STRUCTURE (Continued)
G31
:NA210LH
G32
:NA210LH
G33
:NA210LH
G34
:NA210LH
G35
:NA410LH
G36
:NA410LH
G37
:NA210LH
G38
:IVJ 10LH
G39
:NA210LH
G40
:NA210LH
G41
:NA210LH
G42
:NA210LH
G43
:IV110LH
G44
:IV120LH
G45
:IV110LH
END S191LH;
G280,FF3QZ,G310;
G300,G310,G320;
G250,G450,G330;
D,G450,G340;
G040,FF1 QZ,FF2QZ,FF3QZ,G350;
QA,QB,QC,G030,G360;
G350,G360,G370;
G370,G380;
QD,G380,G390;
G370,FF4QZ,G400;
G390,G400,G410;
G340,G450,G420;
CLK,G430;
G430,G440;
LOADZ,G450;
II
count definition
These counters are bidirectional with respect to count operations, and the relationship for counting up or
down is defined by the D_UZ select input. Unidirectional counters are available in software macros or can
be constructed using the' ASC2405 through' ASC2407 4-bit predesigned registers. Additional single bits
can be achieved with flip-flop cells offered in TI's standard cell family.
...
U)
Q)
Q)
.c
en
designing for testability
Designers employing storage or bistable elements, especially long registers (ripple or synchronous), should
consider testability of the design in its final form. The need to preset or clear and read intermediate stages
of these elements should be assessed throughout the development of custom logic circuits with these
considerations extended to the end-equipment application with respect to maintainability. Simple actions
on the part of the ASIC designer can result in considerable cost savings, allowing the expense of IC testing,
system testing, and system maintenance to be reduced significantly.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
...caca
C
4-175
II
...c
D)
D)
en
:::r
...
CD
CD
tn
4-176
SN54ASC193, SN74ASC193
SYNCHRONOUS 4-811 UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
02939, AUGUST 1986
SystemCell™
•
•
2-",m SOFTWARE MACRO CELL
logic symbol t
Dual Clock Inputs for Sourcing Count
Direction
Fully Synchronous in Count Modes
•
•
•
CTRDIV 16
ClR
Parallel Asynchronous Load for Modulo-N
Count Sequences
CT-D
UP
2+
COZ
Gl
Asynchronous Clear
DOWN
Look-Ahead Circuitry Enhances Performance
of Cascaded Counters
1-
BOl
G2
lOADZ
A
[1]
QA
B
[2]
QB
C
[4]
QC
D
[8]
QD
tThis symbol is in accordance with ANSIIIEEE Std 91-1984 and
IEC Publication 617-12.
description
The SN54ASC193 and SN74ASC193 are standard-cell software macros implementing 4-bit up-down binary
counters, The 4-bit configuration provides the custom IC designer a bidirectional counter to embed in ASICs
in its most efficient form. Its 4-bit length means that testability is simplified when constructing large
counters. The' ASC 193 implements a count sequence identical with that performed by packaged 'HC193,
'LS193, and 'F193 counters.
The' ASC 193 is a synchronous, reversible up/down counter. Synchronous operation is provided by having
all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so
instructed by the steering logic. This mode of operation eliminates the output counting spikes normally
associated with asynchronous (ripple clock) counters. The' ASC 193 is implemented with the standard
cell functions indicated. This software macro is identified and called from the engineering workstation input
using the cell name and netlist in conjunction with a label developed as shown on the last line of the following
table:
RELATIVE
CELL NAME
CELL AREA
NO. USED
TO NA210LH
TOTAL
TOTAL
RELATIVE
cpd*
CELL AREA
(pF)
SN54ASC'
1164
442
2
2
4
2.36
512
30.6
1
4
4
1.76
420
25.28
AN410LH
IV120LH
NA210LH
1
4
4
2.04
524
31.36
NA310LH
1.25
4
5
2
652
39.12
NA520LH
N0210LH
1.75
2
4
3.5
1.04
1.32
426
512
25.6
30.84
TAB20LH
1
4
en
...caca
C
69.6
26.6
3.5
1.75
.c
SN74ASC'
5.4
2.12
9
U)
Q)
Q)
MAXIMUM ICC
(nAI
6
2
1.5
AN210lH
AN310LH
a...
3756
30.8
16.8
7.7
4
34.84
8408
32
67.8
TOTALS
Label: S193LH A.B,C,O,UP,OOWN,LOAOZ,CLR,BOZ,CQZ.QA.QB,QC,OO;
224.8
504
:t:The equivalent power dissipation capacitance does not include interconnect capacitance.
PRODUCTION DATA documents contain informatio•.
current as of publication date. Products conform to
spacificatians par the terms of TeXIs Instruments
:~~::~~i~a{::1~18 :~:~i:; ~iO=::~::"as
not
Copyright © 1982. Texas Instruments Incorporated
TEXAS . " .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-177
SN54ASC193. SN74ASC193
SYNCHR()NOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
The outputs of the four flip-flops are triggered by a low-to-high-Ievel transition of either count (clock) input
(UP or DOWN). The direclion of counting is determined by which count input is pulsed while the pther
count input is high. These counters are fully programmable; that is, they may be preset to any number
between and 15 by placing a low on the load input and entering the desired data at the data inputs.
The output will change to agree with the data inputs independently of the count pulses. This fe<;lture allows
the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.
o
A clear input has been provided that forces all outputs to the low level when a high level is applied. The
clear function is independent of the count and the load inputs ..
These counters are designed to be 'cascaded without the need for additional circuitry. The borrow output
(BOZ) produces a low-level pulse while the count is zero (all outputs low) and the count-down is low.
Similarly, the carry output (COZ) produces a low-level pulse w!lile the count is maximum (all outputs high)
and the count-up input is low. The counters are cascaded by feeding the borrow and carry outputs to
the count-down and count-up inputs, respectively, of the succeeding counter.
The SN54ASC 193 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC193 is characterized for operation from -40°C to 85°C.
4-178
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC193. SN74ASC193
SYNCHRONOUS 4-811 UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
logic diagram
,
A
NA620L
•
,
•
-",y
NA2
V
•
J
V
RZ
N01
~
B
NA7
COl
~
ANl
:
AN210LII
A
~
QA
.AN21Ot'v
....... V
r
•
.
",
~
'-"'
QZ
AN7
A NA31C1l.x
B
Q
CK
N0210lx
~
•
~
S
A
tV120Lx
A
-"'V
~
.......,
OlXy
r
N02
0;
~.
" Ff
V
AN2
~
A
•
V
NAS
A AN2101.Jc
as
~
CI)
CI)
v
.s::.
..
• AN.
en
~
C
V
C
AN0210Lx
I
V
ANa
•
A AN31Ol..x
•
N03
V
~
AN4
A
B
'1--..
.......,
A
1V12PLx
A
..b V
"V3
•
C
NAS
?
•
-"'V
..V4
C
D-
Q
CK
CLRZ
co
co
v
•
N
V
~
' - " ' QC
C
Q2
.RFFS
AN210u<
V
• AN.
~~'Q
A AN41OL.x
IV120l.x
V
NA9
NA310lx
,,"V
D
A
~
S
A AN310lx
•
II
..
CI)
Q2
Po NA31C1l.x
....... V
•
'-"'
LOAOZ
NA620LlC
eaz
v
r
1V12Ol.x
A
'NII2
CLR
A
C
D
~
'-"'
A NA310Lx
'NV1
....
NA1
•
,
:......
.......,
DOWN
,,"v
C
D
I
-
QD
~
NAZ10Lx
A
B~
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
:"ZU-Q2
A AN210Lx
Y
B
~
Y
4-179
.
".'
SN54ASC193;
SN74ASC193
,
SYNCHRONOUS 4~BIT UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
,
,
typical clear. load, and count sequences
Illustrated below is the following .sequence:
1. Clear outputs to tero.
2. Load (preset) to binary thirteen.
3. CouHi: up to fourteen, fifteen, carry, zero, one, and two.
4. Count down to one, zero, borrow, fifteen, fourteen, and thirteen.
--1l~
CLR
LOADl
________________________________
U
1 1
I 1
A -_ _
-1-1--'-'
_ _ ....J L-_
_
_1 1
I
I
B -_ _
-1-1-,L..Jr-___
_
I I
I I
_._---,-,
-
DATA
C __1_'_-,
•
UP -
DOWN -
C
...
QA
rn
::r
...
_'-1- _,_,_
I I
1 1
-1-1--1-1--'
-.- -
-
-
-
-r------------..;....-.,
_ _ I_I __ I_'_J I
I»
I»
CD
CD
L-
I 1
1 I
D -_ _
-1-1-11
-__ ' L
QB :
OUTPUTS
1 1
1 I
I
1 I
I
1
I
.JL.._I_ _~_~
~
I
1
til
QC
QD
COl
BOl
SEQUENCE
ILLUSTRATED
=~'--_-'
1
='",_--,
I
1 I
101
I
113J
r--.. ,.-t'-..
CLEAR
u
I
1
I
r-14
15
0
1
21
COUNT UP - - - - ,
LJ
1
I
1
0
I
15
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
13
1
r--COUNT DOWN~
PRESET
NOTES: A, Clear overrjdes load, data, and count inputs.
B. When counting up, count·down input must be high; when counting down, count-up input must be high.
4-180
14
SN54ASC193. SN74ASC193
SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models ar.e incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation produce workstation output used
to identify and resolve each specific timing need.
electrical characteristics
PARAMETER
TEST CONDITIONS
VT
Input threshold voltage
lee
Supply current
ei
Input capacitance
Vee = 5 V,
TA = 25°e
Equivalent power
Vee - 5 V,
tr - tf - 3 ns,
dissipation capacitance t
TA = 25°e
epd
SN54ASC193
SN74ASC193
TYP
TYP
2.2
TA - 25°e
Vee - 5 V,
Vee - 4.5 V to 5.5 V, VI = Vee or 0,
.1I A,8,e,D
All others
MAX
2.2
504
0.12
0.12
0.24
0.24
34.84
34.84
UNIT
V
8408
TA = MIN to MAX
.
MAX
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
II
...
en
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Note 1)
PARAMETER*
tpd
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
UP
eoz
tpd
DOWN
BOZ
tpd
DOWN, UP
Any Q
tpd
LOADZ
tpHL
SN54ASC193
MIN TYP§
MAX
3
SN74ASC193
MIN TYP§
MAX
5.1
3
ns
3
5.2
3
4.7
ns
24.1
11
14.5
7
21.6
13.5
ns
Any Q
11
7
eLR
Any Q
5
10.5
5
9.6
ns
Atpd
Any
Any Q
0.1
0.5
1.4
0.1
0.5
1.2
ns/pF
Atpd
Any
BOZ,eOZ
0.3
0.9
2.8
0.3
0.9
2.4
ns/pF
eL
=0
.c
o
UNIT
4.7
CD
CD
...
CO
CO
C
ns
* Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns 110% and 90%).
tpd .. propagation delay time, low-to-high or high-to-Iow-Ievel output
tpHL = propagation delay time, high-to-Iow-Ievel output
Atpd .. change in tpd with load capacitance
§ Typical values are at Vee = 5 V, TA = 25 oe.
NOTE1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-181
SN54ASC193. SN74ASC193
SYNCHRONOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
HDL FILE
BLOCK S193LH;
A
@INPUT;
B
@INPUT;
C
@INPUT;
D
@INPUT;
UP
@INPUT;
DOWN
@INPUT;
LOADZ
@INPUT;
CLR
@INPUT;
BOZ
@OUTPUT;
COZ
@OUTPUT;
QA
@OUTPUT;
QB
@OUTPUT;
QC
@OUTPUT;
QD
@OUTPUT;
•
...c
C»
C»
(I)
::r
CD
!(II
4-182
STRUCTURE
AN1
:AN210LH
:AN210LH
AN10
:AN210LH
AN2
:AN3fOLH
AN3
:AN310LH
AN4
AN5
:AN410LH
:AN410LH
ANB
AN7
:AN210LH
:AN210LH
AN8
:AN210LH
AN9
FF1
:TAB20LH
:TAB20LH
FF2
:TAB20LH
FF3
FF4
:TAB20LH
INV1
. :IV120LH
:IV120LH
INV2
:IV120LH
INV3
:IV120LH
INV4
:NA520LH
NA1
NA10
:NA210LH
:NA520LH
NA2
:NA310LH
NA3
:NA310LH
NA4
:NA310LH
NA5
:NA310LH
NAB
NA7
:NA210LH
. :NA210LH
NA8
:NA210LH
NA9
:N0210LH
N01
:N0210LH
N02
:N0210LH
N03
:N0210LH
N04
END S193LH;
INV1 S,FF1 SAN1 S;
INV3S,NA 1O,AN 10S;
QA,INV2S,AN2S;
INV1 S,FF1 S,FF2S,AN3S;
QA,QB,INV2S,AN4S;
INV1 S,FF1 S,FF2S,FF3S,AN5S;
QA,QB,QC,INV2S,ANBS;
INV3S,NA 7S,AN7S;
INV3S,NA8S,AN8S;
INV3S,NA9S,AN9S;
AN7S,NA3S,N01 S,aA,FF1S;
AN8S,NA4S,N02S,QB,FF2S;
AN9S,NA5S,N03S,QC,FF3S;
AN 1OS,NABS,N04S,QD,FF4S;
DOWN,INV1 S;
UP,INV2S;
CLR,INV3S;
LOADZ,INV4S;
INV1 S,FF1 S,FF2S,FF3S,FF4S,BOZ;
NABS,INV4S,NA 1OS;
QA,QB,QC,QD,INV2S,COZ;
A,INV4S,INV3S,NA3S;
B,INV4S,INV3S,NA4S;
C,INV4S,INV3S,NA5S;
D,INV4S,INV3S,NABS;
NA3S,INV4S,NA 7S;
NA4S,INV4S,NA8S;
NA5S,INV4S,NA9S;
INV1 S,INV2S,N01 S;
AN1 S,AN2S,N02S;
AN3S,AN4S,N03S;
AN5S,ANBS,N04S;
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
.
SN54ASC193. SN74ASC193
SYNCHRONOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
count definition
These counters are bidirectional with respect to count operations, and the relationship for counting up
or down is defined by the UP and DOWN inputs. Unidirectional counters are available in software macros
or can be constructed using the' ASC2405 through' ASC2407 4·bit predesigned registers. Additional single
bits can be achieved with pre designed flip-flops offered in TI's standard cell family.
designing for testability
Designs employing storage or bistable elements, especially long counters (ripple or synchronous), should
consider testability of the design in its final form. The need to preset or clear and to read intermediate
stages of these elements should be assessed throughout the development of custom logic circuits with
these considerations extended to the end-equipment application with respect to maintainability. Simple
actions on the part of the ASIC designer can result in considerable cost savings, allowing the expense
. of IC testing, system testing, and system maintenance to be reduced significantly.
power-up clear/preset
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of the clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an OR gate.
•
...
U)
CD
CD
.c
U)
...'"
o'"
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-183
C
I»
r+
I»
en
:r
CD
CD
r+
til
4-184
SN54ASC194A. SN74ASC194A
4-B11 BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
02939. AUGUST 1986
SystemCell™
2-/lm SOFTWARE MACRO CELL
logic symbol t
•
Parallel Inputs and Outputs
•
Four Operating Modes:
Synchronous Parallel Load
Right Shift
Left Shift
Do Nothing
ClRZ
so
SI
ClK
•
Positive Edge-Triggered Clocking
•
Embedded Clock Drivers Provide Clock
Buffering
SRSER
QA
A
OB
B
OC
C
description
o
00
The SN54ASC194A and SN74ASC194A are
2.40
SlSER
standard-cell software macros implementing
4-bit parallel-in/parallel-out bidirectional,
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
universal shift registers. The 4-bit configuration
IEC Publication 617-12.
provides the custom IC designer a register to
.
embed in ASICs in its most efficient form. Its 4-bit length simplifies construction of large registers. The
'ASC 194A implements a shift register identical with that performed by packaged 'HC 194, 'LS 194A, and
'F194 registers.
These bidirectional shift registers are designed to incorporate virtually all of the features a system designer
may want in a shift register. The circuit features parallel inputs, parallel outputs, right-shift and left-shift
inputs, operating-made-control inputs, and a direct overriding clear line. The register has four distinct modes
of operation, namely:
Inhibit clocking (do nothing)
Shift right (in the direction OA toward OD)
Shift left (in the direction OD toward OA)
Parallel (broadside load)
II
~
...
r/)
II)
II)
.c
en
...co
CO
C
The 'ASC194A is implemented with the standard cell functions indicated. The HDL netlist label for this
software macro is shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
TO NA210lH
NO. USED
TOTAL
RELATIVE
TOTAL
CELL AREA
(pF)
Cpd*
MAXIMUM ICC
(nA)
SN54ASC'
SN74ASC'
IVll0LH
0.75
1
0.75
0.44
105
6.32
IV120LH
1
4
4
3.2
524
31,.4
IV140LH
1.5
1
1.5
1.61
190
11.4
NA310LH
1.25
16
20
8
2608
156.48
1.5
4
1
6
23.25
2
748
44.8
10.2
2647
159
27
55.5
25.45
6822
410
NA410LH
R2405LH
S194ALH
23.25
TOTALS
Label: S194ALH A,8.C.O,SRSER.SLSEll.CLK,CLRZ,Sl.S0,QA.QB,QC,QO;
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
PRODUCTION DATA documants cont.i. i.fa,motio.
currant I. of publicatian data. Products conform to
specifications per the terml of Taul InstrumaRtI
:::=~i~·r::I~'1.; ~=:~I:: ~r':'''::~":t:~~ not
Copyright @ 198~. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-185
SN54ASC194A, SN74ASC194A
4-PIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control
inputs, SO and 51, high. The data are loaded into the associated flip-flops and appear at the outputs after
the positive transition of the clock input. During loading, serial data flow is inhibited.
'
Shift right is accomplished synchronously with the rising edge of the clock pulse when SO is high and,
51 is low. Serial data for this mode are entered at tne shift-right data input. When SO is low and 51 is
high, data shift left synchronously and neW data are entered at the shift-left serial input. When both mode
control inputs are low, a free-running clock will reload the present state of each flip-flop on each clock
transition to implement the do-nothing mode.
The SN54ASC194A is characterized for operation over the full military temperature range of - 55 DC to
125°C. The SN74ASC194A is characterized for operation from -40 DC to 85°C.
logic diagram
CLKc:>------------------------------------------,
c:>~
____~A~~~N~Y-------------------,
~V2
IVllOlx
IV140Lx
so
•
51
st."R
02401'-'
CU(
ao
CCRZ
QC
Q3
1
02
O.
Q4
QA
04
FF1.
A
SROER
4-186
TEXAS •
INSTRUMENTS
POST OFF!CE BOX 655012 • D.o:-LLAS. TEXAS 75285
os
SN54ASC194A. SN74ASC194A
4-BI1 BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
FUNCTION TABLE
INPUTS
CLRZ
MODE
CLK
S1
SO
X
X
X
H
X
X
H
H
H
L
H
H
H
L
H
H
H
L
H
H
L
t
t
t
t
t
H
L
L
X
L
L
OUTPUTS
SERIAL
SLSER SRSER
X
X
X
X
X
H
L
X
PARALLEL
QA
QB
QC
QD
L
L
L
L
QAO
a
QBO
b
c
d
X
X·
H
QAn
QBn
QC n
L
QAn QBn
QC n QDn
QC n QDn
QC n
A
B
C
0
X
X
X
X
X
X
X
X
X
a
b
H
X
X
X
X
QBn
X
X
X
X
X
X
X
c
X
X
X
X
X
QSn
X
X
X
X
QAO QBO QCO QDO
L
X
X
X
d
QCO QDO
H
L
See Explanation of Function Tables in Section 1.
typical clear, load, right-shift, left-shift, inhibit, and clear sequences
CLOCK
MODE {SO - CONTROL
-S1
INPUTS
J
I
I
::n.
......,r-+--------;.__________
-i_________
I
--U I
LJ
R _-:--+I_-i-In..._____~-_:_------+r-t....JI......._i_:-
CLEAR
I
SERIAL{
DATA
INPUTS
L
II
...
U)
~
.c
f/)
--r-r-__r----------T--+-'
...
C'O
C'O
C
PARALLEL
DATA
INPUTS
B
_~~--+----------~_+-------~-------_+--
~
______~~________~Irl'-------------~~
~---+--ir------'n:
OUTPUTS
:
I
I
I
i.--SHIFT RIGHT---+!
CLEAR LOAD
oH~I---INHIBIT----+I
If----SHIFT LEFT-......
CLEAR
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
"'I}
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-187
SN54ASC194A, SN74ASC194A
4·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation produce workstation output used
to identify and resolve each specific timing need.
electrical characteristics
PARAMETER
VT
lee
Ci
SN54ASC194A
TEST CONDITiolllS
=
=
TYP
Input threshold voltage
VCC
Supply current
VCC - 4.5 V to 5.5 V, VI - VCC or 0,
TA = MIN to MAX
Input capacitance
I ClK,SO,S1
I All others
Equivalent power
Cpd dissipation capacitance t
=
VCC
5 V,
TA
5 V,
TA
= 5 V,
= 2.5 o e
VCC
TA
tr
=
TYP
2.2
25°C
ns,
MAX
2.2
410
0.24
0.12
0.12
25.45
25.45
UNIT
V
6822
0.24
25°C
= tf = 3
SN74ASC194A
MAX
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance .
. . switching characteristics over recommended ranges of supply voltage and operating free-air temperature
. . (unless otherwise noted) (see Note 1)
PARAMETER;
tpd
tpHl
.:l.tpil
.:l.tpHl
FROM
TO
TEST
(lN~UTl
(OUTPUT)
CONDITIONS
ClK
ClRZ
an
an
ClK
an
ClRZ
an
SN54ASC194A
TVP§
MAX
MIN
5
10.5
!1
8.4
0.3
0.9
2.3
0.3
0.7
1.9
CL = 0
SN74ASC194A
TYP§
MAX
MIN
9.4
UNIT
5
5
7.7
ns
ns
0.3
0.9
2.1
nsJpF
0.3
0.7
1.6
nsJpF
iprol'agation delay.times are measured from the 44% point of VI to the 44% point of Vo with tr = tf .= 3 ns (10% and 90%).
tpd. '" propagation delay time, low-to-high- or high-to-Iow-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
.:l.tpd '" change in tpd with load capacitance'
.:l.tPHL " change in tpHl with load capacitance
§ Typical values are at Vec = 5 V, T A = 25°C.
NOTE1: Thes~ switching characte~istics ~re simulations of the software macro cell using interconnect capacitance values for' an array
design having 2,000 gates.
Post~layout
simulation uses actual interconnect capacitance values.
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be devl:!loped to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
4-188
TEXAS •
INSTRUM~NTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC194A, SN74ASC194A
4·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
HDL FILE
BLOCK S194ALH;
A
@INPUT;
B
@INPUT;
C
@INPUT;
D
@INPUT;
SRSER
@INPUT;
SLSER
@INPUT;
CLK
@INPUT;
CLRZ
@INPUT;
S1
@INPUT;
SO
@INPUT;
QA
@OUTPUT;
QB
@OUTPUT;
QC
@OUTPUT;
QD
@OUTPUT;
STRUCTURE
FF14
:R2405LH
INV1
:IV110LH
INV2
:IV140LH
INV5
:IV120LH
INV6
:IV120LH
INV7
:IV120LH
INV8
:IV120LH
NA1
:NA310LH
NA10
:NA310LH
NA11
:NA310LH
NA12
:NA310LH
NA13
:NA310LH
NA14
, :NA310LH
NA15
:NA310LH
NA16
:NA310LH
NA17
:NA410LH
NA18
:NA410LH
NA19
:NA410LH
NA2
:NA310LH
NA20
:NA410LH
NA3
:NA310LH
NA4
: NA31 OLH
NA5
:NA310LH
NA6
:NA310LH
NA7
:NA310LH
NA8
:NA310LH
NA9
:NA310LH
END S194ALH;
INV20,NA 170,NA 180,NA 190,NA200,CLK,QD,QC,QB,QA;
CLRZ,INV10;
INV10,INV20;
S1,INV50;
INV50,INV60;
SO,INV70;
INV70,INV80;
QD,INV50,INV70,NA 10;
QC,INV60,INV70,NA 100;
B,INV60,INV80,NA 110;
INV80,INV50,QA,NA 120;
QA,INV50,INV70,NA 130;
QB,INV60,INV70,NA 1:40;
A,INV60,INV80,NA 150;
INV80,INV50,SRSER,NA 160;
NA 10,NA20,NA30,NA40,NA 170;
NA50,NA60,NA70,NA80,NA 180;
NA90,NA 1O,NA 11 O,NA 120,NA 190;
SLSER,INV60,INV70,NA20;
NA 130,NA 140,NA 150,NA 160,NA200;
D,INV60,INV80,NA30;
INV80,INV50,QC,NA40;
QC,INV50,INV70,NA50;
QD,INV60INV70,NA60;
C,INV60,INV80,NA 70;
INV80,INV50,QB,NA80;
QB,INV50,INV70,NA90;
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 656012 • bAlLAs. TEXAS 75266
•..
en
CD
CD
.c
en
..
as
as
o
4-189
SN54ASC194A, SN74ASC194A
4·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
shift definition
These registers are bidirectional with respect to shift operations and the relationship for shifting left or
right is defined by the SO and S1 inputs. Unidirectional registers are available in software macros or can
be constructed using the' ASC2405 through' ASC2407 4·bit predesigned registers. Additional single bits
can be achieved with flip-flop cells offered in TI's standard cell family.
designing for testability
Designs employing. storage or bistable elements, especially long registers (ripple or synchronous), should
consider testability of the design in its final form. The need to preset or clear and read intermediate stages
of these elements should be assessed throughout the development of custom logic circuits with these
considerations extended to the end-equipment application with respect to maintainability. Simple actions
on the part of the ASIC designer can result in considerable cost savings, allowing the expense of IC
testing, system testing, and system maintenance to be reduced significantly.
•
power-up clear preset
•
4-190
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of the clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an AND gate .
TExAs •
INSTRUMENTS
POST OFFICE BOX-655012 • DALLAS. TeXAS 75266
SN54ASC195A, SN74ASC195A
4·81T PARALLEL·ACCESS SHIFT REGISTERS
02939, AUGUST 1986
SystemCell™
•
•
•
•
•
•
2-j.lm SOFTWARE MACRO CELL
logic symbol t
Synchronous Parallel Load
Positive-Edge-Triggered Clocking
SRG4
J and KZ Inputs to First Stage
CLRZ
SH_LDZ
Complementary Outputs from Last Stage
Embedded Clock Drivers Provide Clock
Buffering
CLK
Dependable Texas Instruments Quality and
Reliability
KZ
A
QA
2,30
2,30
2,30
B
description
C
08
ac
The SN54ASC195A and SN74ASC195A are
QD
o
standard-cell software macros implementing
aDZ
4-bit parallel-out shift registers, The 4-bit
configuration provides the custom IC designer
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
a register to embed in ASICs in its most efficient
form. The 4-bit length simplifies construction of
large counters. The' ASC 195A implements a shift sequence identical with that performed by packaged
'HC195, 'LS195A, and 'F195 registers.
These 4-bit shift registers feature parallel inputs, parallel outputs, J-KZ serial inputs, shiftlload control input,
and a direct overriding clear. The registers have two modes of operation: parallel (broadside) load, and
shift (in the direction of OA toward 00).
The' ASC 195A is implemented with the standard cell functions indicated. The HDl netlist label for this
software macro is shown on the last line of the following table:
CELL NAME
RELATIVE
CELL AREA
NO. USED
TO NA210LH
TOTAL
RELATIVE
CELL AREA
TOTAL
Cpd*
(pFI
MAXIMUM ICC
(nA)
SN54ASC'
0.75
1
0.75
0.44
105
6.32
IV120LH
1
2
2
1.6
262
15.7
IV140LH
1.5
1
1.5
1.61
190
11.4
NA210LH
1
10
10
5.1
1310
NA310LH
1.25
3.75
1.5
489
R2406LH
26.25
3
"1
78.4
29.34
26.25
11.69
2931
18
44.25
21.94
S195ALH
5,287
Label: S195ALH CLRZ,CLK,SH_LDZ.J,KZ,A,B,C,D,OA,OB,OC,OD,ODZ;
U)
CD
CD
.c
..o
en
ca
ca
SN74ASC'
IV110LH
TOTALS
•..
176
318
iThe equivalent power dissipation capacitance does not include interconnect capacitance.
Parallel loading is accomplished by applying the four bits of data and taking the shift/load control
(SH _ lDZ) input low. The data is loaded into the associated flip-flop and appears at the outputs after the
pOSitive transition of the clock (ClK) input. During loading, serial data flow is inhibited.
Copyright @ 1986, Texas Instruments Incorporated
PRODUCTION DATA documenls contain information
current as of publication date. Products conform to
specifications paf the terms of Taus Instruments
=-::~~i~·i~:I-:Ji ~~::~r Jr.-=:::':~~ not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-191
SN54ASC195A, SN74ASC195A
4·81T PARALLEL·ACCESS SHIFT REGISTERS
description (continued)
Shifting is accomplished synchronously when the shift/load control is high. Serial data for this mode is
entered at the J-KZ inputs. These inputs permit the first stage to perform as a J-K, D-, or T-type flip-flop
as shown in the function table.
The SN54ASC195A is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC195A is characterized for operation from -40°C to 85°C.
logic diagram
ClRZ
ClK C=~--~~----~~----------~~~----~~~----~
SH.LOZ C=")---..=..j
II
KZ
A
NA21OL.
C
QA
....
C»
C»
QB
01
en
B
CD
CD
c
::r
....
02
03
ao
D4
GOI
U)
0
4-192
QC
TEXAS
~
INSTRUMENTS
POST OFFlte BOX 665012 • DALLAS. TEXAS 75265
aoz
SN54ASC195A, SN74ASC195A
4·811 PARALLEL·ACCESS SHIFT
REGI~TERS
FUNCTION TABLE
INPUTS
CLRZ
SH_LDZ
CLK
L
X
H
L
X
1
H
H
H
H
H
H
H
H
H
H
OUTPUTS
SERIAL
PARALLEL
KZ
A
L
J
X
X
X
X
X
X
1
L
H
t
t
t
L
L
H
H
H
L
X
a
X
X
X
X
X
B
X
C
0
OA
OB
OC
00
X
X
L
L
L
L
H
b
c
d
a
b
c
d
dZ
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OAO
OBO
OCo
OAO
L
OAO
OBn
ODO
OC n
aDO
aC n
OAn
OBn
OC n
aC n
H
OAn
OBn
OC n
aC n
aAn
OAn
OBn
OC n
aC n
ODZ
typical clear. shift and load sequences
CLK
I
I
SERIAL {
J - - : - - -....'T"'L-------------:--~-----------
~L_ _ _ _~--------':_-~-----------
SH_LDZ--+-----~:-------------~~
INPUTS
KZ
A~----+--:_
PARALLEL
DATA
INPUTS
{
•
_---Ir.rlr
B
.
J!!
L :
CD
CD
I
r;T"I
C
L :
~
{:~~~~~l'------!iL-----------..J
~
o
I
OUTPUTS
OC:::1~----_;:-----.....
OD:~~'~----~I--------....
I
I
I
lllljef----- SERIAL SHIFT
I
-----I~
~
SERIAL SHIFT
--+
LOAD
CLEAR
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation produce workstation output used
to identify and resolve each specific timing need.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DAl.LAS, TeXAS 75265
4-193
SN54ASC195A. SN74ASC195A
4·81T PARALLEL·ACCESS SHIFT REGISTERS
electrical characteristics
PARAMETER
VT
Input threshold voltage
ICC
Supply current
Ci
Input capacitance I
Cpd
TYP
VCC
~
5 V,
TA
Equivalent power
VCC
~
5 V,
tr
dissipation capacitance t
TA
~
~
~
~
TYP
MAX
2.2
318
0.24
3 ns,
25°C
UNIT
V
5287
25°C
tf
SN74ASC195A
MAX
2.2
TA - 25°C
VCC - 5 V,
VCC ~ 4.5 V to 5.5 V, VI - VCC or 0,
TA ~ MIN to MAX
I CLK,SH_LDZ
All others
SN54ASC195A
TEST CONDITIONS
nA
0.12
0.24
0.12
pF
21.95
21.95
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of operating free-air temperature and supply voltage
(unless otherwise noted) (see Note 1)
PARAMETER*
II
FROM
(INPUT)
TO
(OUTPUT)
tpd
ClK
tpd
ClK
an
aDZ
tpHl
ClRZ
an
tPlH
:1.
....- - - - - - - - t > V2Z
B2
A3
....--------c=>V~
B3
A4
t---------c=> V4Z
B4
C
m
r+
m
en
::T
CD
CD
r+
1V11Clx
/I\1..J!J
GZ
(I)
4-216
TEXAS •
INSTRUMENTS
POST OFFICE BOX 666012 • DAUAS. TEXAS 75266
SN54ASC258A, SN74ASC258A
QUADRUPLE 2-LlNE TO '-LINE INVERTING MULTIPLEXERS
WITH 3-STATE OUTPUTS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
SN54ASC258A
TEST CONDITIONS
~
TA
~
Input threshold voltage
Vee
lee
Supply current
Vee - 4.5 V to 5.5 V, VI - Vee or 0,
TA ~ MIN to MAX
ei
Input capacitance I AZ __ B
All other inputs
Vee ~ 5 V,
TA ~ 25°e
Equivalent power
Vee - 5 V,
t r - tf - 3 ns,
dissipation capacitance t
TA ~ 25°e
I
SN74ASC258A
MAX
TVP
2.2
25°e
VT
epd
6 V.
TVP
MAX
2.2
V
2106
127
0.25
0.25
0.12
0.12
7.28
7.28
UNIT
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Notes 1 and 2)
PARAMETERt
FROM
TO
TEST
(lNPUTI
(OUTPUT 1
CONDITIONS
tpd
Any A orB
V
tpd
ALB
V
ten
GZ
V
t.tpd
Any
V
~ten
Any
V
SN54ASC258A
TVP§ MAX
MIN
SN74ASC258A
TVP§ MAX
UNIT
1.4
2.8
1.4
2.5
ns
5
10.4
5
9.5
ns
5
10.7
5
9.8
ns
0.6
1.7
4.6
0.6
1.7
4.2
ns/pF
0.7
1.7
4.8
0.7
1.7
4.4
ns/pF
eL = 0
II
...
MIN
en
Q)
Q)
..c:
tPropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf ~ 3 ns (10% and 90%1.
tpd 5: propagation delay time, low-to-high-Ievel or high-to-Iow-Ievel output
ten :5 enable time, high impedance state to low- or high-logic-level output
Lltpd 55 change in tpd with load capacitance
4ten == change in ten with load capacitance
§ Typical values are at Vee = 5 V, T A ~ 25°e.
NOTES: 1. These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post~layout simulation uses actual interconnect capacitance values.
2. Enable and delta·enable times are measured using the conditions specified for the 'ASe2311 (lV212LH).
en
...a:sa:s
o
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-217
SN54ASC258A, SN74ASC258A
QUADRUPLE 2·LlNE TO 1·LlNE INVERTING MULTIPLEXERS
WITH 3·STATE OUTPUTS
HDL FILE
BLOCK S258ALH;
A1
@INPUT;
A2
@INPUT;
A3
@INPUT;
A4
@INPUT;
B1
@INPUT;
B2
@INPUT;
B3
@INPUT;
B4
@INPUT;
GZ
@INPUT;
AZ_B
@INPUT;
Y1
@OUTPUT;
Y2
@OUTPUT;
Y3
@OUTPUT;
Y4
@OUTPUT;
STRUCTURE
:IV212LH
G01
G02
:IV212LH
G03
:IV212LH
G04
:IV212LH
G05
:IV212LH
G06
:IV212LH
G07
:IV212LH
G08
:IV212LH
G09
:AN220LH
G10
:AN220LH
G11
:IV110LH
G12
:IV110LH
END S258ALH;
...C
I»
I»
t/)
:::r
CD
CD
...
(I)
A 1,G090,Y1;
B1,G100,Y1;
A2,G090,Y2;
B2,G 100, Y2;
A3,G090,Y3;
B3,G100,Y3;
A4,G090,Y4;
B4,G100,Y4;
G110,G120,G090;
AZ_B,G120,G100;
AZ_B,G110;
GZ,G120;
Dedicated 2·line to 1-line multiplexers are also available in the standard cell library ('SC2340) for
implementing data-path multiplexers. The 'SC2340 cell incorporates an enable input which can be used
for expanding the word width. These hard-wired cells should be considered if the multiplexer is in a critical
path, as their performance is predetermined as specified in their switching characteristics.
interfacing the macro
Inputs and outputs of the predesigned macro are compatible for interfacing directly with cells and macros
available in the TI standard cell library. The 3-state outputs can interface internal bidirectional buses.
The inputs can be driven by either inverting or non inverting input cells. The outputs can be interfaced to
drive off-chip loads with any of the noninverting output buffers or interfaced to external bidirectional buses
through a 3-state I/O TTL/CMOS buffer. If bus interface is not required, the 'ASC 1 58 2-line to Hine
multiplexer provides totem-pole outputs.
4-218
TEXAS . .
INSTRUMENTS
POST OF~ICE BOX 655012 • DALLAS, TeXAS 75265
SN54ASC259, SN74ASC259
8-BIT ADDRESSABLE LATCHES
02939. AUGUST 1986
SystemCell™
2-llm SOFTWARE MACRO CELL
logic symbol t
•
Parallel-Out Register Performs Serial-toParallel Conversion with Storage
•
Expandable for N-Bit Applications
•
Enable/Disable Input Simplifies Expansion
•
Four Functional Modes:
Addressable Transparent Latch
Parallel 8-Bit Storage Latch
1-of-8 Demultiplexer
Asynchronous Parallel Clear
so
S1
S2
8M
:}
4
GZ
0
CLRZ
00
10.iiR
description
The SN54ASC259 and SN74ASC259 are
standard-cell software macros implementing
addressable 8-bit parallel latches. The 8-bit
configuration provides the custom IC designer
a fully designed addressable register/
demultiplexer to embed in ASICs in its most
efficient form, and its 8-bit length simplifies
construction of large latches. The 'ASC259
implements an addressable latch function
identical with that performed by packaged
'HC259, 'LS259, and 'F259 latches.
9,10
10,lR
01
9,20
10;2R
02
9,30
10;3R
03
9,40
•
04
10,4R
9.50
10;5R
05
9.60
1o;6R
06
9,70
10.7R
07
These 8-bit addressable latches are designed for
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617- 12.
general purpose storage applications where
demultiplexing and/or addressable bit storage
locations are useful co-functions. Some uses
include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are
multifunction macros capable of storing Single-line data in eight addressable latches or of implementing
a 1-of-N line decoder or demultiplexer with active-high outputs. The' ASC259 is implemented with the
standard cell functions indicated. The HDL netlist label for this software macro is shown on the last line
of the following table:
RELATIVE
TOTAL
TOTAL
Cpd*
(pFI
MAXIMUM ICC
(nAI
CELL AREA
TO NA210LH
AN240LH
2.25
1
2.25
2.32
286
17.2
IV110LH
0.75
2
1.5
0.88
210
12.64
IV120LH
1
6
6
4.8
786
47.1
IV140LH
1.5
1
1.5
1.61
190
11.4
NA220LH
NA310LH
1.5
1.25
8
8
12
1568
10
8
4
NA410LH
1.5
16
24
N0240LH
2.5
1
43
TOTALS
NO. USED
RELATIVE
CELL NAME
CELL AREA
SN54ASC'
SN74ASC'
1304
93.6
78.24
2992
179.2
2.5
8
0.98
292
17.5
59.75
40.59
7528
457
Label: S259LH CLRZ,D.GZ,SO.Sl,S2.00.01.02,03,04.05,06.07;
*The equivalent power dissipation capacitance does not include interconnect capacitance.
PRODUCTION DATA documents contein information
current as of p~blic8tion date. Products conform to
speCifications per the terms of Texas Instruments
:~~~:~~i~at::1~1i ~!~~:i:; :.~a:=:~:t::s~S
not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, tEXAS 75265
Copyright © 1986, Texas Instruments Incorporated
4-219
SN54ASC259, SN74ASC259
8·BIT ADDRESSABLE LATCHES
logic diagram
C
I»
r+
I»
(f)
::T
CD
CD
y
ADOR3
r+
en
Y CLEARZ
4-220
'Ii1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265..
SN54ASC259. SN74ASC259
8-BIT ADDRESSABLE LATCHES
Four distinct modes of operation are selectable by controlling the clear (CLRZ) and enable (GZ) inputs as
shown in the function table. In the addressable-latch mode, data at the data-in input D are written into
the addressed latch. The addressed latch will follow the data input with remaining unaddressed latches
retaining their previous states. In the memory mode, all latches remain in their previous states and are
not affected by changes at the data or address inputs. To preclude entering erroneous data in the latches,
enable GZ should be held high (inactive) while the address lines are changed. In the 1-of-8 decoding or
demultiplexing mode, the addressed output will follow the level at the D input with the remaining outputs
low. In the clear mode, all outputs are set low and are not affected by address and data changes.
The SN54ASC259 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC259 is characterized for operation from -40°C to 85°C.
FUNCTION TABLE
LATCH SELECTION TABLE
OUTPUT OF
ADDRESSED
OTHER
LATCH
OUTPUT
D
QiO
Addressable Latch
L
QiO
D
QiO
L
H
L
L
Clear
INPUTS
CLRZ
GZ
H
L
H
H
L
L
EACH
SELECT INPUTS
FUNCTION
LATCH
SO
S1
L
L
Memory
L
H
L
2
8-Une Demultiplexer
L
H
H
3
H
L
L
4
H
H
L
H
H
L
5
6
H
H
H
7
D = the level at the data input
QiO = the level of Qi (i = O. 1, . . . 7, as appropriate) before
the indicated steady-input conditions were established.
S2
ADDRESSED
L
L
L
H
0
1
II
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
VT
Input threshold voltage
ICC
Supply current
Ci
Input capacitance
Cpd
I SO.S1,S2
ID
I CLRZ, GZ
TEST CONDITIONS
TA = 25°C
VCC = 5 V,
VCC - 4.5 V to 5.5 V, VI - VCC or O.
TA = MIN to MAX
VCC
=
5 V,
Equivalent power
VCC - 5 V,
dissipation capacitance
TA
=
TA
tr
=
25°C
= tf
- 3 ns,
25°C
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS •. "TEXAS 75285
SN54ASC259
SN74ASC259
TYP
TYP
MAX
MAX
2.2
2.2
7528
V
457
0.24
0.24
0.13
0.13
0.6
0.6
40.59
40.59
UNIT
nA
pF
pF
4-221
SN54ASC259. SN74ASC259
8-BIT ADDRESSABLE LATCHES
switching characteristics over recommended ranges of operating free-air temperature and supply voltage
(unless otherwise noted) (see Note 1)
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONOITIONS
tpd
'50, 51. 52
an
tpd
0
an
tpd
GZ
an
tpHL
CLR
-____:..:A~
4·240
V.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 855012 • ,DALLAS, TEXAS 75285
SUM3
SN54ASC283, SN74ASC283
4·BIT BINARY FULL ADDERS WITH FAST CARRY
FUNCTION TABLE
L
L
L
L
H
L
L
H
L
H
L
L
H
L
H
L
L
H
L
L
H
H
L
H
H
L
L
H
H
H
L
L
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
L
L
L
H
H
L
L
L
H
H
L
H
H
L
H
H
H
L
L
L
H
L
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
H
H
L
H
H
H
H
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
H
H
H
H
H
H
H
II
....
U)
NOTE: Input conditions at A 1, B1, A2, B2, and CO are used to determine outputs SUM1 and SUM2 and
the value of the internal carry C2. The values at C2, A3, B3, A4, and B4 are then used to determine
outputs SUM3, SUM4, and C4.
CD
CD
.c
tJ)
absolute maximum ratings and recommended operating conditions
....caca
See Table 1 in Section 2.
C
electrical characteristics
PARAMETER
TEST CONDITIONS
~
~
VT
Input threshold voltage
VCC
ICC
Supply current
VCC - 4.5 V to 5.5 V, VI - VCC or 0,
TA ~ MIN to MAX
Ci
Cpd
I An,Bn
5 V,
TA
VCC
~
5 V,
TA
Equivalent power.
VCC
~
5 V,
tr
dissipation capacitance t
TA
Input capacitance
ICO
~
~
~
SN54ASC2B3
SN74ASC2B3
TVP
TVP
25°C
2.2
~
3 ns,
25°C
MAX
2.2
8457
0.5
0.12
0.12
36.28
36.28
UNIT
V
508
0.5
25°C
tf
MAX
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
4-241
SN54ASC283, SN74ASC283
4-B11 BINARY FULL ADDERS WITH .FAST CARRY
switching characteristics over recommended ranges of operating free-air temperature and supply voltage
(unless otherwise noted) (see Note, 1)
FROM
(INPUT)
TO
TEST
(OUTPUTI
CONDITIONS
tpd
CO
tpd
PARAMETERt
SN54ASC283
SN74ASC283
Typt
MAX
MAX
SUMn
8.5
16.5
8.5
15
ns
An, Sn
SUMn
7.5
15.5
7.5
14.3
ns
tpd
CO
C4
6
12.6
6
11.7
ns
tpd
An, Sn
C4
6
12.8
6
11.6
Any
Any
0.6
1.9
0.6
1.7
.:I.tpd
~
0
0.3
MIN
UNIT
TYP*
CL
MIN
0.3
ns
ns/pF
tpropagation delay times are measured from the 44% point of VI to the 44% point of Va with tr ~ tf.~ 3 ns (10% and 90%1.
tpd 5 propagation delay time, low-to-high-Ievel or high-to-Iow-Ievel output
Atpd ;;;;; change in tpd with load capacitance
*Typical values are at VCC ~ 5 V, TA ~ 25°C.
NOTE 1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
DESIGN CONSIDERATIONS
•
C
I»
r+
I»
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
en
HOL FILE
::r
CD
CD
r+
(II
4-242
BLOCK S283LH;
A4
@INPUT;
A3
@INPUT;
A2
@INPUT;
A1
@INPUT;
B4'
@INPUT;
B3
@INPUT;
B2
@INPUT;
B1
@INPUT;
CO
@INPUT;
SUM4
@OUTPUT;
SUM3
@OUTPUT;
SUM2
@OUTPUT;
SUM1
@OUTPUT;
C4
@OUTPUT;
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC283, SN74ASC283
4·BIT BINARY FULL ADDERS WITH FAST CARRY
HDL FILE (Continued)
STRUCTURE
EXl
EX2
EX3
EX4
INVl
INV10
INVll
INV12
INV13
INV2
I!\IV3
INV4
INV5
INV6
INV7
INV8
NAl
AN10
NA11
NA12
NA13
NA14
AN15
NA16
NA17
NA18
AN19
NA2
NA20
AN21
NA3
NA4
NA5
NA6
NA7
NA8
NA9
NOl
N02
N03
N04
N05
END S283LH;
:EX220LH
:EX220LH
:EX220LH
:EX220LH
:IVll0LH
:IVll0LH
:IV120LH
:IV110LH
:IVll0LH
:IVll0LH
:IVll0LH
:iVll0LH
:IVll0LH
:IV120LH
:IVll0LH
:IVll0LH
:NA220LH
:AN220LH
:NA220LH
:NA320LH
:NA420LH
:NA420LH
:AN220LH
:NA220LH
:NA320LH
:NA320LH
:AN220LH
:NA220LH
:AN220LH
:AN220LH
:NA220LH
:NA220LH
:NA220LH
:NA320LH
:NA420LH
:NA520LH
:NA520LH
:N0220LH
:N0220LH
:N0220LH
:N0220LH
:N0220LH
AN100,INV120,SUM4;
AN 150,INV130,SUM3;
AN190,N050,SUM2;
AN210,INV100,SUMl ;
CO,INV10;
INVl O,INVl 00;
NA90,C4;
NA 140,INV120;
NA 180,INV130;
N010,INV20;
N020,INV30;
N030,INV40;
N040,INV50;
N010,INV60;
N020,INV70;
N030,INV80;
B4,A4,NA10;
NA10,INV20,AN100;
N030,NA20,NA 110;
N040,NA20,NA30,NA 120;
NA20,NA30,NA40,INVl O,NA 130;
INV70,NA 11 O,NA 120,NA 130,NA 140;
NA20,INV30,AN150;
N040,NA30,NA 160;
NA30,NA40,INVl O,NA 170;
INV80,NA 160,NA 170,NA 180;
NA30,INV40,AN190;
. B3,A3,NA20;
NA40,INV10,NA200;
NA40,INV50,AN210;
B2,A2,NA30;
Bl ,A 1 ,NA40;
N020,NA 10,NA50;
N030,NA 10,NA20,NA60;
N040,NA 10,NA20,NA30,NA70;
NA 10,NA20,NA30,NA40,INVl 0,NA80;
INV60,NA50,NA60,NA70,NA80,NA90;
B4,A4,N010;
B3,A3,N020;
B2,A2,N030;
Bl,A 1 ,N040;
N040,AN200,N050;
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75285
II
4·243
4-244
SN54ASC298, SN74ASC298
QUADRUPLE 2-INPUT MULTIPLEXERS WITH NEGATIVE-EDGE-TRIGGERED REGISTER
02939, AUGUST 1986
SystemCeIlTM
2-llm SOFTWARE MACRO CELL
•
Selects One of Two 4-Bit Data Sources and
Stores Data Synchronously with System
Clock
•
Storage Register Loads New Data on
Negative-Going Transition
•
Implements Hexadecimal/BCD Shifter
•
Parallel Multiplexers for Wider Words
logic symbol t
ws
CLKZ -....L:"'C>
Al
QA
1,2D
A2
Bl
QB
B2
Cl
QC
C2
Dl
QD
D2
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
description
The SN54ASC298 and SN74ASC298 are standard-cell software macros implementing four 2-line to 1-line
multiplexers with storage. The 'ASC298 implements a function table identical with that performed by
packaged 'HC298, 'LS298, and 'F298 multiplexers,
When the Word-Select (WS) input is low, word one (A1, B1,C1, 01) is applied to the flip-flops. A high
WS input causes word two (A2, 82, C2, 02) to be selected. The selected word is clocked to the output
terminals on the negative-going edge of the clock pulse. The' ASC298 is implemented with standard cell
functions indicated. The HOL netlist label for this software macro is shown on the last line of the following
table:
RELATIVE
CELL NAME
CELL AREA
NO. USED
TO NA210LH
IV120LH
1
TOTAL
TOTAL
RELATIVE
Cpd*
IpFI
CELL AREA
NA210LH
1
3
12
R2405LH
23.25
I
23.25
T0010LH
1.5
1
1.5
17
39.75
TOTALS
3
12
2.4
23.55
6.12
1572
94.2
10.2
2647
159
177
10.6
4789
288
18.72
.c
CJ)
ctI
ctI
C
SN74ASC'
393
en
Q)
Q)
...
MAXIMUM ICC
(nAI
SN54ASC'
II
...
Label: S298LH A l,A2,Bl ,82,Cl ,C2,Dl ,D2,CLKZ,WS,OA,OB,OC,OD;
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
The SN54ASC298 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC298 is characterized for operation from -40°C to 85°C.
FUNCTION TABLE
INPUTS
PRODUCTION DATA documants contain information
currant as of publication data. Products conform to
specifications per the terms of Taul Instruments
::~~~~~a[::I~li =.~:~:; lIl";'~~~:;S not
OUTPUTS
WS
CLKZ
QA
OB
QC
QD
L
j
al
bl
cl
dl
H
j
a2
b2
c2
d2
X
H
~AO
aBo OCo 000
Copyright © 1986. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-245
SN54ASC298, SN74ASC298
QUADRUPLE 2·INPUT MULTIPLEXERS WITH NEGATIVE·EDGE·TRIGGERED REGISTER
logic diagram
TOO101.x
vee
INVI
1V1201.x
ClKZ
~>-
____~A~
GND
y
INI/4
R2406Lx
ClK
NA2101.x
Ql
ClR2
AI
y
WS
A2
Q2
1=-----.r~QB
01
02
03
04
D3
Q4
Ff14
81
B2
Cl
C2
0
....
01
y
C\)
C\)
tn
02
::r
CD
CD
....
0
4·246
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • CALLAS, TEXAS 752B5
QC
~----.r~0Il
SN54ASC298, SN74ASC298
QUADRUPLE 2-INPUT MULTIPLEXERS WITH NEGATIVE-EDGE-TRIGGERED REGISTER
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation produce workstation output used
to identify and resolve each specific timing need.
electrical characteristics
PARAMETER
VT
lec
TEST CONDITIONS
Input threshold voltage
Vee - 5 V.
Supply current
Vce - 4.5 V to 5.5 V. VI - Vee or O.
TA ~ MIN to MAX
Input capacitance
I WS
TYP
MAX
2.2
Vee ~ 5 V.
TA
~
~
Equivalent power
Vee
dissipation capacitance t
TA ~ 25°e
tr
5 V,
ns,
UNIT
V
4789
25°C
= tf = 3
MAX
2.2
288
0.24
nA
0.24
0.24
0.24
0.12
0.12
18.72
18.72
I All others
epd
SN74ASC298
TYP
TA - 25°e
I CLKZ
Ci
SN54ASC298
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
•
...
tI)
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Note 1)
PARAMETER
tpd
dtpd
*
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
eLKZ
On
Any
On
CL ~ 0
SN54ASC298
TYP§
MAX
MIN
0.3
6
12
0.8
2.3
SN74ASC298
TYP§
MAX
UNIT
6
11
ns
0.8
2.1
ns/pF
MIN
0.3
Q)
Q)
.c
en
...caca
C
'Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr ~ tf ~ 3 ns (10% and 90%).
tpd '" propagation delay time. low-to-high or high-to-Iow-Ievel output
..1.tpd 5 change in tpd with load capacitance
§Typical values are at Vec ~ 5 V. TA ~ 25°e.
NOTE 1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
desigri having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-247
SN54ASC298, SN74ASC298
QUADRUPLE 2-INPUT MULTIPLEXERS WITH NEGATIVE-EDGE-TRIGGERED REGISTER
HDL FILE
BLOCK S298LH;
A1
@INPUT;
A2
@INPUT;
B1
@INPUT;
B2
@INPUT;
@INPUT;
, C1
C2
@INPUT;
D1
@INPUT;
D2
@INPUT;
CLKZ
@INPUT;
WS
@INPUT
QA
@OUTPUT;
QB
@OUTPUT;
QC
@OUTPUT;
QD
@OUTPUT;
STRUCTURE
FF14
INV1
INV2
INV3
INV4
NA1
NA10
NA11
NA12
NA2
NA3
NA4
NA5
NA6
NA7
NA8
NA9
END S298LH;
...c
S»
S»
en
:::r
CD
CD
...
til
:R2405LH
:T0010LH
:IV120LH
:IV120LH
:IV120LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
:NA210LH
INVl 0,NA30,INV40,NA60,NA90,NA 120,QA,QB,QC,QD;
DUM,INV10;
WS,INV20;
INV20,INV30;
CLKZ,INV40;
A 1 ,INV20,NA 10;
INV20,Dl,NA100;
INV30,D2,NA 110;
NA100,NA110,NA120;
A2,INV30,NA20;
NA 1O,NA20,NA30;
B1,INV20,NA40;
INV30,B2,NA50;
NA40,NA50,NA60;
C1,INV20,NA70;
INV30,C2,NA80;
NA70,NA80,NA90;
Dedicated 2-line to l-line multiplexers ('ASC2340) are also available in the standard cell library for
implementing data-path multiplexers. These hard-wired multiplexers in conjunction with hard-wired registers
should be considered if the multiplexer is in a critical path, as their performance is predetermined as specified
in their switching characteristics.
interfacing the macro
Inputs and outputs of the predesigned macro are compatible for interfacing directly with cells and macros
available in the TI stan,dardcell library.
The inputs can be driven by either inverting or non inverting input cells. The outputs can be interfaced to
drive off-chip loads with any of the noninverting output buffers or interfaced to external bidirectional buses
through a 3-state input/output TTL/CMOS buffer.
4-248
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC298, SN74ASC298
QUADRUPLE 2·INPUT MULTIPLEXERS WITH NEGATIVE·EDGE·TRIGGERED REGISTER
TYPICAL APPLICATION DATA
This versatile multiplexer/register can be connected to operate as a shift register that can shift N·places
in a single clock pulse.
The following figure illustrates a BCD shift register that will shift an entire 4-bit BCD digit in one clock pulse.
PARALLEL LOAD
A
WOAD
SELECT
kr-
CLOCK
'ASC298
'ASC298
~
ws G1
Cl....
~
~
ws Gl
MUX
CLKp.,
C2
C2
ws G1
lKto,
"i
~i.20
OA
"7.20
A2 1,20
QB
B2
~
C2
QC
~
C2
----1!!.
QD
'----!!.!02
.2
02
r
-..DIGIT 1
,
C2
~'.2D
OA
OA
A2 1.20
A2 1,20
L.....-.!!.
~
BCD {
DIGIT
MUX
I
MUX
C---!!!
QB
QB
B2
QC
~
C2
QC
QD
----1!!.
QD
02
}
BCD
DIGIT
I
I
--..-
-.DiGIT3
DIGIT 2
When the word-select input is high and the registers are clocked, the contents of register 1 is transferred
(shifted) to register 2, etc. In effect, the BCD digits are shifted one position. In addition, this application
retains a parallel-load capability which means that new BCD data can be entered in the entire register with
one clock pulse. This arrangement can be modified to perform the shifting of binary data for any number
of bit locations.
Another function that can be implemented with the' ASC298 is a rgister that can be designed specifically
for supporting multiplier or division operations. The example below is a one-place/two-place shift register.
II
...
CI)
CD
CD
.c
U)
...
CO
CO
C
'ASC298
WORD SELECT
CLOCK
wsl G1 MUx
eLK
C2
A1
A2 1,20
B1 1,20
FO
'ASC181A
(ALUI
{
1=1
1!z
r-
-
.2
C1
g.
01
~
OA
QB
QC
QD
F3
'ASC298
~
WS G1
elK
MUX
C2
A1
"0
'ASC181A
IALU)
1
F1
F2
Ai" i~·20
1.20
~
1.!!3.
C1
r- QA
.r- QB
ILg
t--
QC
~
t--
QD
01
F3
When word select is low and the register is clocked, the outputs of the arithmetic/logic units (AlUs) are
shifted one place. When word select is high and the registers are clocked, the data is shifted two places.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-249
II
C
I»
....
I»
en
:::T
CD
CD
....
en
4-250
SN54ASC299, SN74ASC299
8·BIT BIDIRECTIONAL UNIVERSAL SHIFT/STORAGE REGISTERS
02939, AUGUST 1986
SystemCell™
•
2-~m SOFTWARE MACRO CELLS
logic symbol t
Ported 3-State Inputs/Outputs Simplify
Implementation of:
Single/Multiple Push/Pop Stack
Multiple/Supplementary Accumulator
Bus Storage/Shift Register
SRGS
ClRZ
G1Z
3EN5
G2Z - - ' - - - - - - - '
•
Four Operating Modes:
Synchronous Parallel Load
Right Shift
Left Shift
Do Nothing
so
Sl
CLl<
QAP
SR
LOA
•
Positive-Edge-Triggered Clocking
•
Embedded Clock Drivers Provide Clock
Buffering
C_QC
D_QD
--~.r-------I
E_~
~
I-____
__'__
QHP
2,4D
SL
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
description
The SN54ASC299 and SN74ASC299 are standard-cell software macros implementing S-bit parallelin/parallel-out bidirectional, universal shift/storage registers, The S-bit configuration provides the custom
IC designer a register to embed in ASICs in its most efficient form. The S-bit length simplifies construction
of large registers. The 'ASC299 implements an S-bit shift sequence identical with that performed by
packaged 'HC299, 'LS299, and 'F299 4-bit shift registers.
These bidirectional shift registers are designed to incorporate virtually all of the features a system designer
may want in a shift register. The circuit features parallel inputs, parallel outputs, right-shift and left-shift
inputs, operating-mode-control inputs, and a direct overriding clear line. The' ASC299 is implemented with
the standard cell functions indicated. The HDL netlist label for this software macro is shown on the last
line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USED
TO NA210LH
TOTAL
TOTAL
RELATIVE
Cpd*
(pF)
CELL AREA
SN54ASC'
1
15
0.9
194
11.6
IVll0LH
0.75
1
0.75
0.44
210
12.64
IV140LH
1.5
5
6
8.05
760
45.6
IV222LH
NA310LH
1.5
1.25
8
32
16
7.84
1944
40
16
5216
116.8
312.96
NA410LH
1.5
8
12
4
1496
89.6
N0310LH
1.25
1
1.25
.32
312
18.66
26.25
CD
CD
.s:
o
...'"
'"
C
SN74ASC'
1.5
TOTALS
U)
MAXIMUM ICC
(nAI
AN210LH
R2406LH
II
...
2
52.5
23.4
5862
352
58
181.5
60.02
15915
956
Label: S299LH 50,51 ,Gl Z,G2Z,SL,SR,CLK,CLRZ,QAP,QHP.A_ QA,8_QB,C_QC,
0
QO,E
QE,F
QF,G
QG,H_QH;
iThe equivalent power dissipation capacitance does not include interconnect capacitance.
PRDbuCTIDN DATA documants contain information
currant as of publication date. Products conform tD
specifications per the terms of Texas Instruments
=~~:~i;lr::I~lJi ~:~:~ti:r :.r:=::t:~~ not
Copyright © 1986. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST O~FICE BOX 655012 • DALLAS, TEXAS 75265
4-251
SN54ASC299. SN74ASC299
8·BIT BIDIRECTIONAL UNIVERSAL SHIFT/STORAGE REGISTERS
The 'ASC299 register has four distinct modes of operation, namely:
Parallel (broadside load)
Shift right (in the direction QA toward QH)
Shift left (in the direction QH toward QA)
Inhibit clocking (do nothing).
Synchronous parallel loading is accomplished by taking either output control input, G1 Z or G2Z, high and
applying the eight bits of data while both' mode control inputs, SO and S 1, are high. The data are loaded
into the associated flip-flops on the positive transition of the clock input. During loading, serial data flow
is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse when SO is high and
S 1 is low. Serial data for this mode is entered at the shift-right data input. When SO is low and S 1 is high,
data shifts left synchronously and new data is entered at the shift-left serial input. When both mode control
inputs are low, a free-running clock will reload the present state of each flip-flop on each clock transition
to implement the do-nothing mode.
The SN54ASC299 is characterized for operation over the full military temperature range of - 55 DC to
125 DC. The SN74ASC299 is characterized for operation from - 40 DC to 85 DC.
•
C
...
I»
I»
FUNCTION TABLE
INPUTS
ClRZ
MODE
S1
OUTPUT
CONTROLS
SO G1Z t
ClK
G2Z t
l
L
L
l
L
X
L
L
SR
X
X
X
X
X
L
H
H
X
X
:::r
(1)
H
L
L
L
L
H
X
X
L
L
L'
(1)
H
L
H
L
L
I
(I)
H
L
H
L
L
I
X
X
X
X
X
X
X
H
H
L
L
L
I
H
H
H
L
L
L
I
L
H
H
H
X
X
I
X
...
X
SL
X
X
X
X
en
l
OUTPUTS
1/0 PORTS
SERIAL
A
QA 8
Q8 C
QC 0
QD E QE
F
QF G
QG H
QH
QAP
QHP
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
L
L
OAo
OBo
OCo
000
OEo
OFo
OGo
OHo
OAo
OHo
OAo
OBo
QCo
QFo
OGo
QHo
OAn
OBn
000
OC n
QEo
H
QDn
OEn
OFn
OG n
OAo
H
OHo
OG n
L
~
X
X
X
OBn
OAn
OC n
ODn
OBn
OC n
COn
a
b
C
H
OBn
OC n
OE n '
ODn
OEn
OFn
OG n
L
OG n
OFn
OG n
OHn
H
OBn
H
OEn
d
OFn
OG n
OHn
L
OBn
e
f
9
h
a
L
h
t When one or both output controls are high, the eight input/output terminals are disabled to the high-impedance state; however,
sequential" operation or clearing of the register is not affected. a . .. h = the level of the steady-state input at inputs A through H,
respectively. These data are loaded into the flip-flops while the flip-flop outputs are isolated from the inputloutput terminals,
See explanation of Function Tables in Section 1.
.
4-252
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75285
SN54ASC299. SN74ASC299
8-BIT BIDIRECTIONAL UNIVERSAL SHIFT/STORAGE REGISTERS
logic diagram
II
...
I/)
Q)
Q)
.s:::
en
...
«J
«J
C
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-253
SN54ASC299. SN74ASC299
8-BIT BIDIRECTIONAL UNIVERSAL SHIFT/STORAGE REGISTERS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation produce workstation output used
to identify and resolve each specific timing need.
electrical characteristics
PARAMETER
VT
ICC
TEST CONDITIONS
Input threshold voltage
= 5 V,
= 4.5 V to 5.5
= MIN to MAX
VCC
Supply current
TA
VCC
TA
V, V,
= 25°C
= VCC or
Input
III
c
...
capacitance
=
VCC
5 V,
Cpd
TA = 25°C
Equivalent power
VCC - 5 V,
tr - tf - 3 ns,
dissipation capacitance
TA = 25°C
956
nA
0.48
0.24
0.24
0.62
0.62
0.45
0.45
0.12
0.12
0.33
0.33
pF
60.02
60.02
pF
A_aA ... H_aH
VCC = 5 V,
UNIT
V
15915
TA = 25°C
Output capacitance
MAX
2.2
0.48
All others
Co
TYP
MAX
O.
G1Z,G2Z
SO, S1
SN74ASC299
TYP
2.2
ClK
Ci
SN54ASC299
pF
CI)
CI)
(I)
:T
CD
CD
...
switching characteristics over recommended ran!}es of supply voltage and operating free-air temperature
(unless otherwise noted) (see Note 1)
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
tpd
ClK
tPHl
ClRZ
'pd
tPHl
ClK
aAP,aHP
ClRZ
aAP, aHP
'en
Ll.tpd
GnZ
an
Any
Any
~ten
GnZ
an
PARAMETERt
U)
SN74ASC299
SN54ASC299
UNIT
TYP~
MAX
15.2
7.1
13.8
ns
17
8.4
15.3
ns
5
10.3
5
9.4
ns
6
11.4
6
10.4
ns
6.1
13.5
6.1
12.2
ns
0.2
0.9
2.3
0.3
0.9
2.1
nsipF
0.4
0.8
2.3
0.5
0.8
2.1
nsipF
TYP~
MAX
an
7.1
an
8.4
MIN
Cl = 0
MIN
t Propagation delay times are measured from the 44% point of VI to the 44% point ofVO with tr
:;;:; tf = 3 ns (10% and 90%).
tpd ;;:;; propagation delay time, low-ta-high or high-to-Iow-Ievel output
tpHl " propagation delay time, high-to-Iow-Ievel output
ten == enable time, high-impedance state to low- or high-logic-level output
.6.tpd == change in tpd with load capacitance
aten change in ten with load capacitance
tTypicalvaluesareatVcc = 5V,TA = 25°C.
NOTE 1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post·layout simulation uses actual interconnect capacitance values. ~
=
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design,
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a'single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for a reference.
4-254
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 .'DAlLAS, :TEXAS 75265
SN54ASC299, SN74ASC299
8·BIT BIDIRECTIONAL UNIVERSAL SHIFT/STORAGE REGISTERS
HDL FILE
BLOCK S299LH;
SO
@INPUT;
Sl
@INPUT;
G1Z
@INPUT;
G2Z
@INPUT;
SL
@INPUT;
SR
@INPUT;
CLK
@INPUT;
CLRZ
@INPUT;
QAP
@OUTPUT;
QHP
@OUTPUT;
A_QA
@INOUT;
B_QB
@INOUT;
C_QC
@INOUT;
O_QO
@INOUT;
E_QE
@INOUT;
F_QF
@INOUT;
G_QG
@INOUT
H_QH
@INOUT;
STRUCTURE
AN1
INV1
INV10
INV11
INV12
INV13
INV14
INV15
INV2
INV3
INV4
INV6
INV7
INV8
INV9
NA1
NA10
NA11
NA12
NA13
NA14
NA15
NA16
NA17
NA18
NA19
NA2
NA20
NA21
NA22
:AN210LH
:IV140LH
:IV222LH
:IV222LH
:IV222LH
:IV222LH
:IV222LH
:IV222LH
:IV140LH
:IV140LH
:IV140LH
:IV110LH
:IV110LH
:IV222LH
:IV222LH
:NA310LH
:NA410LH
:NA310LH
:NA310LH
:NA310LH
:NA310LH
:NA410LH
:NA310LH
:NA310LH
:NA310LH
:NA310LH
:NA310LH
:NA410LH
:NA310LH
:NA310LH
SO,Sl,AN10;
SO,INV10;
eN,N010,C_QC;
ON,N010,0_QO;
EN,N010,E_QE;
FN,N010,F_QF;
GN,N010,G_QG;
HN,N010,H_QH;
INV10,INV20;
Sl,INV30;
INV30,INV40;
INV70,INV60;
CLRZ,INV70;
AN,N010.A_QA;
BN,N010,B_QB;
QHP,INV1 0,INV30,NA 10;
NA60,NA70,NA80,NA90,NA 100;
FP,INV1 0,INV30,NA 110;
F _QF,INV20,INV40,NA 120;
GP,INV1 0,INV40,NA 130;
INV30,INV20,EP,NA 140;
NA 11 O,NA 120,NA 130,NA 140,NA 150;
EP,INV1 0,INV30,NA 160;
E_QE,INV20,INV40,NA 170;
FP,INVl 0,INV40,NA 180;
INV30,INV20,OP,NA 190;
H_QH,INV20,INV40,NA20;
NA 160,NA 170,NA 180,NA 190,NA200;
OP,INVl 0,INV30,NA21 0;
0_QO,INV20,INV40,NA220;
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 6.55012 • DALLAS, TEXAS 75265
•
....CD
U)
CD
.c
en
....COCO
o
4·255
SN54ASC299, SN74ASC299
8-BIT BIDIRECTIONAL UNIVERSAL SHIFT/STORAGE REGISTERS
. HDL FILE (Continued)
en
::r
STRUCTURE (Continued)
NA23
:NA310LH
:NA310LH
NA24
NA25
:NA410LH
NA26
:NA310LH
NA27
:NA310LH
NA28
:NA310LH
NA29
:NA310LH
NA3
:NA310LH
NA30
:NA410LH
NA31
:NA310LH
NA32
:NA310LH
NA33
:NA310LH
NA34
:NA310LH
NA35
:NA410LH
NA36
:NA310LH
NA37
:NA310LH
NA38
:NA310LH
NA39
:NA31OLH
NA4
:NA310LH
NA40
:NA410LH
NA5
:NA410LH
:NA310LH
NA6
NA7
:NA310LH
NA8
:NA310LH
:NA310LH
NA9
NOl
:N0310LH·
FF14
:R2406LH
r+
FF58
•
0
Q)
r+
Q)
CD
CD
til
:R2406LH
EP,INV10,INV40,NA230;
INV30,INV20,CP,NA240;
NA210,NA220,NA230,NA240,NA250;
CP,INV10,INV30,NA260;
C_QC,INV20,INV40,NA270;
DP,INV10,INV40,NA280;
INV30,INV20,BP,NA290;
SL,INV10,INV40,NA30;
NA260,NA270,NA280,NA290,NA300;
BP,lNVl O,INV30,NA31 0;
B_QB,INV20,INV40,NA320;
CP,INV10,INV40,NA330;
INV30,INV20,QAP,NA340;
NA310,NA320,NA330,NA340,NA350;
QAP,INV10,INV30,NA360;
A_QA,INV20,INV40,NA370;
BP,INV10,INV40,NA380;
INV30,INV20,SR,NA390;
INV30,INV20,GP,NA40;
NA360,NA370,NA380,NA390,NA400;
NA 1O,NA20,NA30,NA40,NA50;
GP,INV10,INV30,NA60;
G_QG,INV20,INV40,NA70;
QHP,INV10,INV40,NA80;
INV30,INV20,FP,NA90;
ANl 0,G1Z,G2Z,NOl 0;
INV60,NA250,NA300,NA350,NA400,CLK,DP,DN,CP,CN,BP,
BN,QAP,AN;
INV60,NA50,NA 1OO,NA 150,NA200,CLK,QHP,HN,GP,GN,FP,
FN,EP,EN;
END S299LH;
shift definiti()n
These registers are bidirectional with respect to shift operations, and the relationship for shifting left or
right is defined by the SO and 51 inputs. Unidirectional registers are available in software macros or can
be constructed using the' ASC2405 through' ASC2407 8-bit predesigned registers. Additional single bits
; can be achieved with flip-flop cells offered in TI's standard cell family.
designing for testability
Designers employing storage or bistable elements, especially long registers (ripple or synchronous)', should
consider testability of the design in its final form. The need to preset or clear and read intermediate stages
of these elements should be assessed throughout the development of custom logic circuits with these
considerations extended to the end equipment application with respect to maintainability. Simple actions
on the part of the ASIC designer can result in considerable cost saVings, allowing the expense of IC testing,
system testing, and system maintenance to be reduced significantly.
power-up clear/preset
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achi.eve system initialization.
Control of the clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an· AND gate.
4-256
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ASC299X, SN74ASC299X
8-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
02939, AUGUST 1986
SystemCell™
2-/lm SOFTWARE MACRO CELL
logic symbol t
•
Parallel Inputs and Outputs
•
Four Operating Modes:
Synchronous Parallel Load
Right Shift
Left Shift
Do Nothing
SRG8
ClRZ
so
S1
ClK
•
Positive Edge-Triggered Clocking
•
Embedded Clock Drivers Provide Clock
Buffering
SR
description
The SN54ASC299X and SN74ASC299X are
standard-cell software macros implementing
8-bit paraliel-in/parall'el-out bidirectional,
universal shift registers. The a-bit configuration
provides the custom IC designer a register to
embed in ASICs in their most efficient form, The
a-bit length simplifies construction of large
registers. The' ASC299X implements an a-bit
shift sequence identical with that performed by
packaged 'HC194A, 'LS194A, and 'F194 4-bit
shift registers.
A
3.40
8
3.40
OA
08
C
OC
0
00
OE
OF
G
OG
H
3.40
Sl
2.40
OH
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617·12.
•
...
U)
Q)
Q)
These bidirectional shift registers are designed to incorporate virtually all of the features a system designer
may want in a shift register. The circuit features parallel inputs, parallel outputs, right-shift and left-shift
inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes
of operation, namely:
Parallel (broadside load)
Shift right (in the direction QA toward QH)
Shift left (in the direction QH toward QA)
Inhibit clocking (do nothing)
.s::
en
...
C'CI
C'CI
C
The' ASC299X is implemented with the standard cell functions indicated. The HDL netlist label for this
software macro is shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USED
TO NA210LH
TOTAL
TOTAL
RELATIVE
Cpd*
(pF)
CELL AREA
MAXIMUM ICC
(nA)
SN54ASC'
SN74ASC'
IVll0LH
0.75
1
0.75
0.44
105
IV140LH
1.5
5
7.5
8.05
950
57
NA310LH
NA410LH
1.25
32
40
16
5216
312.96
1.5
8
12
4
1496
89.6
R2405LH
23.25
2
46.5
20.4
5294
318
48
106.75
48.89
13061
784
TOTALS
6.32
Label: S299XLH A,B,C,D,E,F,G,H,SO,Sl ,SL,SR,CLK,CLRZ,QA,QB,QC,QD,QE,QF,QG,QH;
+The equivalent power dissipation capacitance does not include interconnect capacitance.
PRODUCTION DATA documants contain information
currant 8S of publication data. Products co,.form to
specifications per the tarms of Taxas Instruments
:e~~=~~i~ai~:I~Ji ~=~~ti:r :'~O:::::::t:~~S not
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DA.LLAS, TEXAS 75265
4-257
SN54ASC299X, SN74ASC299X
8-BIT BIDIRECTIONAL. UNIVERSAL SHIFT REGISTERS
description (continued)
Synchronous parallel loading is accomplished by applying the eight bits of data and taking both mode control
inputs, SO and S 1, high. The data are loaded into the associated flip-flops and appear at the outputs after
the positive transition of the clock input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse when SO is high and
S1 is low. Serial data for this mode is entered at the shift-right data input. When SO is low and S1 is high,
data shifts haft synchronously and new data is entered at the shift-left serial input. When both mode control
inputs are low, a free-running clock will reload the present state of each flip-flop on each clock transition
to implement the do-nothing mode.
The SN54ASC299X is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC299X is characterized for operation from -40°C to 85°C.
FUNCTION TABLE
INPUTS
MODE
SO
CLK
SL
SR
A
B
C
X
H
X
X
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H
L
L
t
t
t
t
t
X
X
X
X
X
X
X
X
X
X
X
b
X
X
X
X
X
X
X
H
X
X
X
X
X
H
X
X
X
X
X
L
o
...
C»
C»
L
L
X
L
OUTPUTS
PARALLEL
51
X
X
CLRZ
•
SERIAL
a
c
X
X
X
X
X
0
X
X
d
X
X
X
X
X
E
F
G
H
QA
QB
QC
QD
QE
QF
QG
QH
X
X
e
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
QEo
Q~o
f
9
X
X
X
X
X
X
X
h
X
X
X
X
X
X
X
X
X
X
QAo QBo
QCo QDo
QGo QHo
a
b
c
d
e
f
9
h
H
QAh
QBn
QCn
QDn
QEn
QFn
QGn
L
QAn
QBn
QCn
QDn
QEn
QFn
QGn
QBn
QCn
QDn
QEn
QFn
QGn
QHn
H
QBn
QCn
QDn
QEn
QFn
QGn
QHn
L
QAO
QBo
QCO QDO
QEO
QFO
QGO QHO
t/)
:r
!CD
typical clear. load. right-shift. left-shift. inhibit. and clear sequences
en
4-258
The 4-bit sequences illustrated on the 'ASC194 data sheet are applicable for similar 8-bit functions
performed by the 'ASC299X.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC299X, SN14ASC299X
8·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
logic diagram
II
...
fI)
CD
CD
.c
CI)
...asas
C
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4·259
SN54ASC299X, SN74ASC299X
8·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation produce workstation output used
to identify and resolve each specific timing need.
electrical characteristics
PARAMETER
VT
Input threshold voltage
ICC
Supply current
Ci
Input capacitance
SN54ASC299X
TEST CONDITIONS
TYP
TA - 25°C
VCC - 5 V.
VCC = 4.5 V to 5.5 V, VI = VCC or O.
TA = MIN to MAX
II
~
;-
tn
::r
Equivalent power
Cpd
dissipation capacitance t
tr = tf = 3 ns,
VCC = 5 V.
TA = 25°C
MAX
784
0.48
0.48
0.49
0.49
0.12
0.12
48.89
48.89
UNIT
V
2.2
13061
TA = 25°C
VCC = 5 V,
TYP
2.2
I ClK
LSO,S1
I All others
SN74ASC299X
MAX
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of operating free-air temperature and supply voltage
(unless otherwise noted) (see Note 1)
PARAMETER*
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONOITIONS
CD
CD
tpd
ClK
Qn
(I)
tpHl
ClRZ
Qn
.:l.tpd
ClK
Qn
.:l.tpHl
ClRZ
Qn
...
SN54ASC299X
TYP§ MAX
SN74ASC299X
TYP§
MAX
UNIT
10.5
5
9.4
ns
9.3
6.1
8.6
ns
0.9
2.1
nsipF
0.7
1.6
nsipF
MIN
Cl = 0
0.3
0.3
5
5
0.9
0.7
2.3
1.9
MIN
0.3
0.3
*Propagation delay times are measured from the 44% pOint of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tpd " propagation delay time, low-to-high-Ievel or high-to· low-level output
tpHl '" propagation delay time. high·to·low·level output
.:l.tpd '" change in tpd with load capacitance
.:l.tPHl '" change in tpHl with load capacitance
§ Typical values are at VCC = 5 V, T A '= 25°C.
NOTE1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HOl for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HOL block definition is furnished for reference.
4-260
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ASC299X, SN74ASC299X
8·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
HDL FILE
BLOCK S299XLH;
A
@INPUT;
B
@INPUT;
@INPUT;
C
@INPUT;
D
@INPUT;
E
@INPUT;
F
@INPUT;
G
@INPUT;
H
@INPUT;
SO
@INPUT;
Sl
@INPUT;
SL
@INPUT;
SR
@INPUT;
CLK
@INPUT;
CLRZ
@OUTPUT;
QA
@OUTPUT;
QB
@OUTPUT;
QC
@OUTPUT;
QD
@OUTPUT;
QE
@OUTPUT;
QF
@OUTPUT;
QG
@OUTPUT;
QH
STRUCTURE
INVl
INV2
INV3
INV4
INV5
INV6
NAl
NA10
NAll
NA12
NA13
NA14
NA15
NA16
NA17
NA18
NA19
NA2
NA20
NA21
NA22
NA23
NA24
NA25
NA26
NA27
a...
en
C1)
C1)
.s:::.
:IV140LH
:IV140LH
:IV140LH
:IV140LH
:IVll0LH
:IV140LH
:NA310LH
:NA410LH
:NA310LH
:NA310LH
:NA310LH
:NA310LH
:NA410LH
:NA310LH
:NA310Lh
:NA310LH
:NA310LH
:NA310LH
:NA410LH
:NA310LH
:NA310LH
:NA310LH
:NA310LH
:NA410LH
:NA310LH
:NA310LH
SO,INV10;
INV10,INV20;
Sl,INV30;
INV30,INV40;
CLRZ,INV50;
INV50,INV60;
QH,INVl 0,INV30,NA 10;
NA60,NA 70,NA80,NA90,NA 100;
QF,INVl 0,INV30,NA 110;
F,INV20,INV40,NA 120;
QG,INVl 0,INV40,NA 130;
INV30,INV20,QE,NA 140;
NAll0,NA120,NA130,NA140,NA150;
QE,INVl 0,INV30,NA 160;
E,INV20,INV40,NA 170;
QF,INVl 0,INV40,NA 180;
INV30,INV20,QO,NA 190;
H,INV20,INV40,NA20;
NA 160,NA 170,NA180,NA 190,NA200;
QO,INVl 0,INV30,NA21 0;
D,INV20,INV40,NA220;
QE,INV10,INV40,NA230;
INV30,INV20,QC,NA240;
NA210,NA220,NA230,NA240,NA250;
QC,INV10,INV30,NA260;
C,INV20,INV40,NA270;
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • bALLAS, TEXAS 75265
o
co
co
...
C
4·261
SN54ASC299X, SN14ASC299X
8·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
HDL FILE (continued)
STRUCTURI" (continued)
NA28
:NA310LH
NA29
:NA310LH
NA3
:NA310LH
NA30
:NA410LH
NA31
:NA310LH
NA32
:NA310LH
NA33
:NA310LH
NA34
:NA310LH
NA35
:NA410LH
NA36
:NA310LH
NA37
:NA310LH
NA38
:NA310LH
NA39
:NA310LH
NA4
:NA310LH
NA40
:NA410LH
NA5
:NA410LH
NA6
:NA310LH
NA7
:NA3iOLH
NA8
:NA310LH
NA9
:NA310LH
FF14
:R2405LH
FF58
:R2405LH
END S299XLH;
II
QD,INV10,INV40,NA280;
INV30,INV20,QB,NA290;
SL,INV10,INV40,NA30;
NA260,NA270,NA280,NA290,NA300;
QB,INV1 O,INV30,NA31 0;
B,INV20,INV40,NA320;
QC,INV10,INV40,NA330;
INV30,INV20,QA,NA340;
NA310,NA320,NA330,NA340,NA350;
QA,INV10,INV30,NA360;
A,INV20,INV40,NA370;
QB,INV10,INV40,NA380;
INV30,INV20,SR,NA390;
INV30,INV20,QG,NA40;
NA360,NA370,NA380,NA390,NA400;
NA 1O,NA20,NA30,NA40,NA50;
QG,INV10,INV30,NA60;
G,INV20,INV40,NA70;
QH,INV10,INV40,NA80;
INV30,INV20,QF,NA90;
INV60,NA250,NA300,NA350,NA400,CLK,QD,QC,QB,QA;
INV60,NA50,NA 1OO,NA 150,NA200,CLK,QH,QG,QF,QE;
shift definition
These registers are bidirectional with respect to shift operations and the relationship for shifting left or
right is defined by the SO and S 1 inputs. Unidirectional registers are available in software macros or can
be constructed using the' ASC2405 through' ASC2407 8-bit predesigned registers. Additional single bits
can be achieved with flip-flop cells offered in TI's standard cell family.
designing for testability
Designs employing storage or bistable elements, especially long registers (ripple or synchronous), should
consider testability of the design in its final form. The need to preset or clear and read intermediate stages
of these elements should be assessed throughout the development of custom logic circuits with these
considerations extended to the end-equipment application with respect to maintainability. Simple actions
on the part of the ASIC designer can result in considerable cost savings, allowing the expense of IC testing,
system testing, and system maintenance to be reduced significantly.
power-up clear/preset
Standard cell storage e.lements containing the capability to be asychronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of the clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an AND gate.
4-262
.
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
SN54ASC373.SN74ASC373
8-BIT OoTYPE LATCHES WITH 3-STATE OUTPUTS
D2939, AUGUST 1986
SystemCell™
2-/lm SOFTWARE MACRO CELL
•
3-State Outputs Interface with Internal Data
Buses Directly
•
Buffered Output Enable Simplifies System
Design
•
Full Parallel Access for Loading
•
Parallel Latches for 16-Bit. 32-Bit, 64-Bit
Word Widths
•
Dependable Texas Instruments Quality and
Reliability
logic symbol t
ocz
C
01
02
03
08
as
D4
description
The SN54ASC373 and SN74ASC373 a~
standard-cell software macros implementing
8-bit D-type latch elements designed specifically
for interfacing internal bus lines. The 8-bit length
means that testability is simplified when
constructing large latches. The 'ASC373
implements a function table identical with that
performed by packaged 'HC373, 'LS373, and
'F373 latches.
05
06
07
01
02
03
04
05
06
07
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
II
...
rn
The eight latches of the 'HC373 are transparent D-type latches. While the enable (C) is high, the Q outputs
will follow the data (D) inputs. When the enable is taken low, the Q outputs will be latched at the levels
that were set up at the D inputs. The output-control input OCl can be used to place the eight outputs
in either a normal logic state (high or low logiC levels) or a high-impedance state. When the outputs are
enabled with OCl low, the logic level at each of the eight outputs is impressed on the data bus. The outputs
are disabled by a high logic level at OCl. The outputs then present a high impedance to the internal bus.
The output control does not affect the internal operations of the latches. Old data can be retained or new
data can be entered while the outputs are off. The' ASC373 is implemented with standard cell functions
indicated. The HDL netlist label for this software macro is shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USEO
TOTAL
TOTAL
RELATIVE
Cpd*
(pF)
CELL AREA
TO NA210lH
~
(J)
...nsns
C
MAXIMUM ICC
(nA)
SN54ASC'
SN74ASC'
IV110LH
0.75
8
6
3.52
840
50.56
IV140LH
1.5
3
4.5
4.83
570
34.2
IV212LH
1.5
8
12
4
1440
86.4
A0221 LH
2.7
8
21.6
4.72
1792
107.2
27
44.1
17.07
4642
279
TOTALS
Q)
Q)
Label: S373LH 01,02,03,04,05,06,07 ,08,C,OCZ,Q1,02,03,04,05,06,07 ,08;
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
The SN54ASC373 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC373 is characterized for operation from - 40°C to 85 DC.
PRODUCTION DATA documents contain information
currant as of publication data. Products conform to
specifications par the tarms of Texas Instruments
==~~i~.r::1~1~ ~r;~:~i:: ~ID:::::::t:~~S not
.J.!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1986, Texas Instruments Incorporated
4-263
SN54ASC373. SN74ASC373
8·BIT O·TYPE LATCHES WITH 3·STATE OUTPUTS
FUNCTION TABLE
(EACH LATCH)
INPUTS
OUTPUT
OCZ
C
0
Q
L
H
H
H
L
H
L
L
L
L
X
X
X
00
H
Z
logic diagram
0,
Ql
02
Q2
II
03
C
Q3
Q)
pt.
Q)
en
::r
D4
Q4
CD
CD
pt.
en
011
07 r-~------------------~+-~H
~::.:..-----r, Q7
~~---f>Q8
c
ocz
4-264
r">--------!:'-j
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
SN54ASC373, SN74ASC373
B-BIT OoTYPE LATCHES WITH 3-STATE OUTPUTS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation produce workstation output used
to identify and resolve each specific timing need.
electrical characteristics
TEST CONOITIONS
PARAMETE'
VT
Input threshold voltage
lee
Supply current
ei
Input capacitance
t=
epd
SN74ASC373
TYP
TYP
MAX
2.2
Vee ~ 5 V,
TA = 25°e
Vee - 4.5 V to 5.5 V,
VI - Vee or 0,
2.2
~
TA
5 V,
~
25°e
Output capacitance
Vee ~ 5 V,
TA = 25°e
Equivalent power
Vee = 5 V,
tr
dissipation capacitance t
TA ~ 25°e
~
tf
~
3 ns,
UNIT
V
279
0.49
Vee
MAX
4642
TA = MIN to MAX
aez
eo
SN54ASC373
nA
0.49
0.13
0.13
0.49
0.49
pF
0.18
0.18
pF
17.07
17.07
pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Notes 1 and 2)
PARAMETERt
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
SN54ASC373
MAX
MIN TYP§
SN74ASC373
MAX
MIN TYP§
3
7.5
3
6.7
5
10.2
UNIT
ns
Q
aez
Q
5
9.2
ns
D
Q
0.6
1.7
4.6
0.6
1.7
4.2
ns/pF
fiten
Any
Q
0.7
1.7
4.8
0.7
1.7
4.4
ns/pF
eL ~ 0
Q)
Q)
.c
tn
...caca
C
a
ten
t.tpd
tpd
•
...en
t The equivalent power dissipation capacitance does not include interconnect capacitance.
tPropagation delay times are measured from the 44% pOint of VI to the 44% point of Va with tr ~ tf ~ 3 ns (10% and 90%).
tpd == propagation delay time,
low~to-high-Ievel
or high-to-Iow-Ievel output
ten 5" enable time, high-impedance state to low- or high-Iogic-Jevel output
.Mpd == change in tpd with load capacitance
l1ten == change in ten with load capacitance
§ Typical values are at Vee = 5 V, T A ~ 25°e.
NOTES: 1. These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
2. Enable and delta-enable times are measured using the conditions specified for the' ASC2407.
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS:TEXAS 76265
4-265
SN54ASC373, SN74ASC373
8·BIT D·TYPE LATCHES WITH 3·STATE OUTPUTS
HDL FILE
IIo
I»
Dr
t/)
::r
CD
CD
S
4-266
BLOCK S373LH;
01
@INPUT;
02
@INPUT;
03
@INPUT;
04
@INPUT;
05
@INPUT;
06
@INPUT;
07
@INPUT;
08
@INPUT;
C
@INPUT;
OCZ
@INPUT;
Q1
@OUTPUT;
Q2
@OUTPUT;
Q3
@OUTPUT;
Q4
@OUTPUT;
Q5
@OLiTPUT;
Q6
@OUTPUT;
Q7
@OUTPUT;
Q8
@OUTPUT;
STRUCTURE
A01
A02
A03
A04
A05
A06
A07
.
A08
INV10
INV11
INV12
INV13
INV14
INV15
INV16
INV17
INV18
INV20
INV21
INV22
INV23
INV24
INV25
INV26
INV27
INV28
INV9
END S373LH;
:A0221LH
:A0221LH
:A0221LH
:A0221LH
:A0221LH
:A0221LH
:A0221LH
:A0221LH
:IV140LH
:IV110LH
:IV110LH
:IV110LH
:IV110LH
:IV110LH
:IV110LH
:IV110LH
:IV110LH.
:IV140LH
:IV212LH
:IV212LH
:IV212LH
:IV212LH
:IV212LH
:IV212LH
:IV212LH
:IV212LH
:IV140LH
01 ,INV90,INVioO,INV11 0,A01 0;
02,INV90,INV100,INV120,A020;
03,INV90,INV100,INV130,A030;
04,INV90,INV100,INV140,A040;
05,INV90,INV100,INV150,A050;
06,INV90,INV100,INV160,A060;
07,INV90,INV100,INV170,A070;
08,INV90,INV100,INV180,A080;
C,INV100;
A010,INV110;
A020,INV120;
A030,INV130;
A040,INV140;
A050,INV150;
A060,INV160;
A070,INV170;
A080,INV180;
OCZ,INV200;
A01 O,INV200,Q1;
A020,INV200;Q2;
A030,INV200,Q3;
A040,INV200,Q4;
A050,INV200,Q6;
A060,INV200,Q6;
A070,INV200,Q7;
A080,INV200,Q8;
INV100,INV90;
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC374, SN74ASC374
8·BIT O·TYPE FLlp·FLOPS WITH 3·STATE OUTPUTS
02939. AUGUST 1986
SystemCell™
2·",m SOFTWARE MACRO CELL
•
3-State Outputs Interface with Internal Data
Buses Directly
•
Buffered Output Control Simplifies System
Design
•
Embedded Clock Drivers Provide
Symmetrical Performance Across Long
Registers
•
Parallel Latches for 16-Bit, 32-Bit, 64·Bit
Word Widths
logic symbol t
ocz
ClK
01
01
02
02
description
The SN54ASC374 and SN74ASC374 are
standard-cell software macros implementing
8-bit D-type register elements designed
specifically for interfacing internal bus lines.
The 8-bit length simplifies construction of large
registers. The' ASC374 implements a function
table identical with that performed by packaged
'HC374, 'LS374, and 'F374 latches.
03
03
D4
04
05
05
06
06
07
07
os
as
tThis symbol is in accordance with ANSI/IEEE Std 91·19B4 and
IEC Publication 617·12.
The Output-Control input OCZ can be used to place the eight outputs in either a normal logic state (high
or low logic levelsl or a high-impedance state. When the outputs are enabled with OCZ low, the logic level
at each of the eight outputs is impressed on the data bus. The outputs are disabled by a high logic level
at OCZ. The outputs then present a high impedance to the internal bus. When the outputs are disabled,
sequential operation of the flip-flops is not affected. The 'ASC374 is implemented with the standard cell
functions indicated. The HDL netlist label for this software macro is shown on the last line of the following
table:
RELATIVE
CEll NAME
CELL AREA
NO. USED
TO NA210LH
IV120LH
1
R2407LH
26.25
TOTAL
TOTAL
RELATIVE
Cpd*
(pFI
CEll AREA
1
1
a...
(I)
Q)
Q)
.c:
(I)
...
CU
CU
C
MAXIMUM ICC
(nA)
SN54ASC'
SN74ASC'
7.B5
2
52.5
6062
384
22
T0010LH
1.5
1
1.5
177
10.6
TOTALS
4
55
22.80
6370
403
label: S374lH Dl.D2.D3.D4.D5.D6.D7.DB.ClK.OCZ.01.Q2,Q3,Q4.Q5.Q6.Q7,QB;
O.B
131
:l:The eq~ivalent power dissipation capacitance does not include interconnect capacitance.
The SN54ASC374 is characterized for operation over the full military temperature range of - 55 0<;: to
125°C. The SN74ASC374 is characterized for operation from -40°C to 85°C.
PRODUCTION DATA documenls conlain informalion
current as of publication date. P,oducts conform to
specifications par the terms of Texas Instruments
::~~:~~i;ai~:I:r~ ~~:~ti:r :I~D::~::~::~
not
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-267
SN54ASC374, SN74ASC374
8·BIT O·TYPE FLlp·FLOPS WITH 3·STATE OUTPUTS
FUNCTION TABLE
(EACH FLIP-FLOP)
OUTPUT
INPUTS
OCZ
CLK
On
Q
L
H
H
L
t
t
L
L
L
L
X
QO
H
X
X
Z
logic diagram
TOO10Lx
vee
INV1
GNO
R2407Lx
01
eLK
eLK
Q2
01
III
C
....I»
I»
tJ)
:T
CD
CD
....
en
Q3
02
04
03
Q3
04
FF14
04
01
eez
Q2
INV5
05
06
07
Q3
01
02
03
04
04
FF58
08
4-268
01
Q2
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
DOD
OD
Q7
Q6
SN54ASC374, SN74ASC374
8·BIT O·TYPE FLlp·FLOPS WITH 3·STATE OUTPUTS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration. setup time. and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation produce workstation output used
to identify and resolve each specific timing need.
electrical characteristics
TEST CONDITIONS
PARAMETER
= 5 V,
= 4.5 V to 5.5
= MIN to MAX
VT
Input threshold voltage
ICC
Supply current
Ci
Input capacitance On
Co
DCZ
Output capacitance
VCC
Equivalent power
VCC
dissipation capacitance t
TA
Cpd
VCC
Vce
TA
,~
=
VCC
=
=
=
TA
V.
VI
5 V,
TA
= 25°C
= Vec or 0,
=
TA
tr
SN74ASC374
TYP
2.2
TYP
MAX
MAX
25°C
403
nA
0.4S
0.4S
0.25
0.25
0,24
pF
0,24
pF
22,S
pF
0.24
0,24
22,S
25°C
UNIT
V
2.2
6370
= 25°C
= tf = 3 ns,
5 V,
5 V,
SN54ASC374
t The equivalent power dissipation capacitance does not include interconnect capacitance.
en
switching characteristics over recommended ranges of operating free-air temperature and supply voltage
(unless otherwise noted) (see Notes 1 and 2)
FROM
(INPUT)
TO
(OUTPUT)
tnd
CLK
Q
ten
Atpd
OCZ
Q
CLK
Any
Q
Q
PARAMETER*
.t1ten
TEST
CONDITIONS
CL
=
5
11,4
5
10.4
ns
7,1
4
6.6
ns
0,6
4,6
0,6
ns
1,7
4,S
O,S
1.7
1.7
4.2
O.S
4.3
ns/pF
:5
=
tf
=
G)
G)
.c
en
...
ta
ta
UNIT
4
1,7
tpropagation delay times are measured from the 44% pOint of VI to the 44% point of Va with tr
tpd '" propagation delay time, low-to-high-Ievel or high-to-Iow-Ievel output
ten
SN74ASC374
MIN TYP§ MAX
SN54ASC374
MIN TYP§
MAX
°
II
...
o
3 ns (10% and 90%1,
enable time, high-impedance state to low- or high-logic-level output
Atpd '" change in tpd with load capacitance
~ten ;;;: change in ten with load capacitance
§ Typical values are at V CC = 5 V, T A = 25°C.
NOTES; 1. These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
'
design having, 2,000 gates. Actual performance can be ,evaluated at post-layout simulation.
2. Enable and delta-enable times are measured using the conditions specified for the' ASC2407,
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-269
SN54ASC374, SN74ASC374
8-BIT O·TYPE FLlP·FLOPS WITH 3·STATE OUTPUTS
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
HOL FILE
BLOCK S374LH;
01
@INPUT;
D2
@INPUT;
03
@INPUT;
D4
@INPUT;
D5
@INPUT;
D6
@INPUT;
D7
@INPUT;
DS
@INPUT;
CLK
@INPUT;
OCZ
@INPUT;
01
@OUTPUT;
02
@OUTPUT;
03
@OUTPUT;
04
@OUTPUT;
05
@OUTPUT;
06
@OUTPUT;
07
@OUTPUT;
08
@OUTPUT;
II
c
...
CI)
CI)
en
:::r
CD
CD
...
(II
STRUCTURE
INV1
INV5
FF14
FF5S
END S374LH;
:T0010LH
:IV120LH
:R2407LH
:R2407LH
DUM,ICLRZ;
OCZ,INV50;
ICLRZ,D1 ,D2,D3,D4,CLK,INV50,01 ,02,03,04;
ICLRZ,D5,D6,D7 ,DS,CLK,INV50 ,05,06,07 ,OS;
designing for testability
Designers employing storage or bistable elements, especially long registers (ripple or synchronous), should
consider testability of the design in its final form. The need to preset or clear and read intermediate stages
of these elements should be assessed throughout the development of custom logic circuits with these
considerations extended to the end-equipment application with respect to maintainability. Simple actions
on the part of the ASIC designer can result in considerable cost savings, allowing the expense of IC testing,
system testing, and system maintenance to be reduced significantly .
4-270
. TEXAS"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ASC375, SN74ASC375
4-BIT BISTABLE LATCHES
02939, AUGUST 1986
SystemCelllM
2-/lm SOFTWARE MACRO CELL
logic symbol t
•
Four-Bit Software Latches with
Complementary Outputs
•
Eliminates Skew and Mismatch of Long
versus Short Data Paths
•
10
01
01
01Z
C1C2
Parallel Latches for 8-Bit, 16-Bit, 32-Bit
Word Widths
02
02
02Z
03
03
03Z
C3C4
description
The SN54ASC375 and SN74ASC375 are
standard-cell software macros implementing
4-bit bistable latch elements for embedding in
ASICs, The 4-bit length simplifies construction
of large registers, The 'ASC375 implements a
function table identical with that performed by
packaged 'HC375 and 'LS375 registers.
04
04
04Z
tThis symbol is in accordance with ANSI/IEEE SId 91-1984 and
IEC Publication 617-12.
Information present at a On input is transferred to the Qn output when the Cn input is high, and the Qn
output will follow the data input as long as Cn remains high, When Cn goes low, the data (that was present
at the On input at the time the transition occurred) is retained at the Qn output until CnCn is taken high.
The' ASC375 is implemented with the standard cell functions indicated. The HOL netlist label for this
software is shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USED
TO NA210LH
TOTAL
TOTAL
RELATIVE
CELL AREA
Cpd*
(pF)
10.8
2.36
896
53.6
4
2.7
IVll0LH
0.75
4
3
1.76
420
25.28
IV120LH
1
4
4
3.2
524
31.4
12
17.8
7.32
1840
111
TOTALS
.c
U)
SN74ASC'
A0221LH
...en
CD
CD
MAXIMUM ICC
(nA)
SN54ASC'
4
...'"
o'"
Label: S375LH 01,02,D3,D4,Cl C2,C3C4,Ql,Q1Z,Q2,Q2Z,Q3,Q3Z,Q4,Q4Z;
tThe equivalent power diSSipation capacitance does not include interconnect capacitance.
The SN54ASC375 is characterized for operation over the full military temperature range of - 55 °C to
125°C. The SN74ASC375 is characterized for operation from -40°C to 85°C.
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
PRODUCTION DATA documanll .onllin information
currant as of publication data. Products conform to
specifications per the tarms of Tuas Instruments
::.:!:~~i;8r::1~7i
:3::,:.~O:=:::~~~
not
OUTPUTS
On
Cn
an
OnZ
L
H
L
H
H
H
H
L
X
L
Qno
Qno
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76266
4-271
SN54ASC375. SN74ASC375
4·BIT BISTABLE LATCHES
logic diagram
,.-------£::::::::>
01
=>"-'-....--r~
C1C2
a1Z
a1
Q2Z
02
....--£::::::::> Q2
~-'-
Q3Z
D3
•
...Cmm
Q3
EN34
Q4Z
04
en
:::r
Q4
CD
CD
...en
4-272
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TeXAS 75265
SN54ASC375, SN74ASC375
4·BIT BISTABLE LATCHES
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation, produce workstation output used
to identify and resolve each specific timing need.
electrical characteristics
PARAMETER
TEST CONDITIONS
VT
Input threshold voltage
lec
Supply current
Ci
Cpd
Vce - 5 V,
TA
~
SN54ASC375
SN74ASC375
TYP
TYP
25°C
2.2
VCC - 4.5 V to 5.5 V, VI - VCC to 0,
TA
I On
I CnCm
~
TA ~ 25°C
Equivalent power
Vee - 5 V,
t r - tf - 3 ns,
dissipation capacitance t
TA ~ 25°C
MAX
2.2
111
0.13
0.13
0.12
0.12
7.32
7.32
UNIT
V
1840
MIN to MAX
Vee ~ 5 V,
Input capacitance
MAX
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Note 1)
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
tpd
tpd
On
On
Qn
QnZ
tpd
tpd
Cn
Cn
Qn
QnZ
PARAMETERt
CL
SN54ASC375
TYP§ MAX
MIN
=0
SN74ASC375
Typ9 MAX
II
UNIT
MIN
3
2
6.4
4.8
3
2
5.8
4.8
ns
...co
5
4.5
10.2
8.7
5
4.5
9.5
8
ns
C
t.tpd
Any
Qn
0.3
0.5
1.1
0.3
0.5
1
t.tpd
Any
Qnz
0.5
1.5
4.6
0.5
1.5
4.1
CO
ns/pF
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr ~ tf ~ 3 ns (10% and 90%).
tpd :;;: propagation delay time, low-to-high-Ievel or high-to-Iow-Ievel output
t.tpd " change in tpd with load capacitance
§Typical values are at Vee ~ 5 V, TA ~ 25°C.
NOTE 1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-273
SN54ASC375, SN74ASC375
4-BIT BISTABLE LATCHES
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifica!ly for managing unused inputs.
The HOL for this software macro is iricluded as a .part of the library supplied for supported engineering
workstations so that a siQgle label can be developed to apply the macro as needed. The following printout
of the HOL block definition is furnished for reference.
HOL FILE
II
...C
I»
I»
en
:::T
CD
!en
4-274
BLOCK S375LH;
01
@INPUT;
02
@INPUT;
03
@INPUT;
04
@INPUT;
C1C2
@INPUT;
C3C4
@INPUT;
Q1
@OUTPUT;
Q1Z
@OUTPUT;
Q2
@OUTPUT;
Q2Z
@OUTPUT;
Q3
@OUTPUT;
Q3Z
@OUTPUT;
Q4
@OUTPUT;
Q4Z
@OUTPUT;
STRUCTURE
A01
A02
A03
A04
INV1
INV2
INV3
INV4
INV5
INV6
INV7
INV8
ENO S375LH;
:A0221LH
:A0221LH
:A0221LH
:A0221LH
:IV110LH
:IV120LH
:IV120LH
:IV120LH
:IV120LH
:IV110LH
:IV110LH
:IV110LH
01 ,INV60,INV1 O,Q1 ,Q1 Z;
02,INV60,INV10,Q2,Q2Z;
03,INV80,INV70,Q3,Q3Z;
04,INV80,INV70,Q4,Q4Z;
C1C2,INV10;
Q1Z,Q1;
Q2Z,Q2;
Q3Z,Q3;
Q4Z,Q4;
INV10,INV60;
C3C4,INV70;
INV70,INV80;
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS;. TEXAS 75266
SN54ASC375, SN74ASC375
4·BIT BISTABLE LATCHES
designing for testability
Designs employing storage or bistable elements, especially long registers (ripple or synchronous), should
consider testability of the design in its final form. The need to preset or clear and read intermediate stages
of these elements should be assessed throughout the development of custom logic circuits with these
considerations extended to the end-equipment application with respect to maintainability. Simple actions
on the part of the ASIC designer can result in considerable cost savings, allowing the expense of IC testing,
system testing, and system maintenance to be reduced significantly.
power-up clear/preset
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of the clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an AND gate.
II
....
CI)
CI)
CI)
.r:.
en
....caca
C
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
4-275
III
C
I»
I»
.....
en
:r
CD
CD
.....
f/)
4-276
SN54ASC393, SN74ASC393
DUAL FOUR-BIT RIPPLE COUNTERS
02939. AUGUST 1986
SystemCell™
•
•
•
2-Jlm SOFTWARE MACRO CELL
Software Dual Four-Bit Counter for Custom
IC Applications
logic symbol t
,{
CTRDIV16
Direct Clear Input Simplifies Initialization or
Cycle Length
Embedded Clock Drivers Provide
Symmetrical Performance Across Long
Counters
•
CT-O
CLRI
+
AI
QAl
aBl
aCl
aDl
Cascadable and Expandable for Full
Customization
aA2
CLR2
aB2
description
aC2
A2
aD2
The SN54ASC393 and SN74ASC393 are
standard-cell software macros implementing
dual4-bit binary counter elements. The dual 4-bit
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
configuration provides the custom IC designer
a fully designed counter element to embed in
ASICs in its most efficient form, and the 4-bit
length simplifies construction of large counters. The' ASC393 implements a count sequence identical with
that performed by packaged 'HC393 and 'LS393 counters.
This software macro reduces the input loading for implementation of larger counters, as standard library
buffer cells are used to buffer each clock and clear input to further enhance the performance across long
counters. The' ASC393 is implemented with standard cell functions indicated. The HDL netlist label for
this software is shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USED
TO NA210LH
TOTAL
TOTAL
RELATIVE
Cpd*
(pF)
SN54ASC'
210
CELL AREA
0.75
IV120LH
1
2
2
1.5
2
1.6
262
12.64
15.7
R240SLH
2S.25
2
56.5
14.44
6926
416
TOTALS
16.92.
6
60
7398
Label: S393LH Al ,CLRI ,A2,CLR2,QA 1,QSl ,QCl ,QDl ,QA2,QB2,aC2,QD2;
445
If)
Q)
Q)
.s::.
en
C
SN74ASC'
0.88
....
....C'C'OO
MAXIMUM ICC
(nA)
IV110LH
•
+The equivalent power dissipation capacitance does not include interconnect capacitance.
The SN54ASC393 is characterized for operation over the full military temperature range of - 55 DC to
125 DC. The SN74ASC393 is characterized for operation from - 40 DC to 85 DC.
Copyright © 1986, Texas Instruments Incorporated
PRODUCTIOI DATA documonts .ontoin information
of publication date. Products conform to
current
I'
specificatioRS per the terms of Texas Instruments
:=~~~8{::1~1i =~:~:; :'~D:::::9t::.s not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-277
SN5~ASC393.
SN74ASC393
DUAL FOUR·BIT RIPPLE COUNTERS
FUNCTION TABLE
(EACH COUNTER)
INPUTS
ClRn An
H
X
l
l
l
l
l
l
l
l
l
L
L
L
L
L
L
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
lI_d,ag,am
•
OUTPUTS
ODn OCn OBn OAn
l
l
l
l
H
l
l
l
l
l
H
l
l
l
H
H
l
l
l
H
H
l
H
l
l
H
H
l
H
H
H
l
H
l
l
L
H
l
L
H
H
L
H
L
H
L
H
H
H
L
L
H
Ii
H
L
H
H
H
L
H
H
H
H
H
L
L
L
L
C
a
R24081.x
A1
V
D)
en
~
CD
CD
Q.K
Q1
Q.RZ
Q.R1
Q2
I·~--------~
Q3
1NV2
0+
(II
Q4
QA1
as1
QC1
aD1
FF14
A2
Q.R2
R24081.x
V
Q.K
Q1
Q.RZ
Q2
Q3
Q4
FFIi8
4-278
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
QA2
QB2
QC2
aD2
SN54ASC393, SN74ASC393
DUAL FOUR-BIT RIPPLE COUNTERS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during.pre-Iayout simulation produce workstation output used
to identify and resolve each specific timing need.
electrical characteristics
PARAMETER
VT
Input threshold voltage
lee
Supply current
Ci
lelRn
Input capacitance An
TA
I
= 4.5 V to 5.5
= MIN to MAX
dissipation capacitance t
Vee
=
SN54ASC393
SN74ASC393
TYP
TYP
TA - 25 De
Vee - 5 V.
Vee
Equivalent power
epd
TEST CONDITIONS
V,
5 V,
VI
TA
= Vee
=
2.2
or O.
MAX
25 De
445
0.24
0.24
0.12
0.12
16.92
16.92
UNIT
V
2.2
739B
t r - tf - 3 ns,
Vee - 5 V,
TA = 25 De
MAX
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Note 1)
PARAMETER;
tpd
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
Any
tpd
SN54ASC393
TYP§
MAX
MIN
tpHl
ClRn
Q
~tpd
Any
Any Q
14.9
7
13.6
ns
14
31.5
14
2B.5
ns
4.5
8.7
4.5
B.1
ns
0.5
1.3
0.5
1.1
ns/pF
Cl = 0
0.3
UNIT
7
QA
QD
SN74ASC393
TYP§
MAX
MIN
0.3
II
...
fI)
CI,)
CI,)
.c
en
...caca
C
*Propagation delay times are measured from the 44% point of VI to the 44% pOint of Vo with t, = tf = 3 ns (10% and 90%).
tpd 5 propagation delay time, low-to-high-Ievel or high-to-Iow-Ievel output
tPHl 5 propagation delay time, high-to-Iow level output
~tpd '" change in tpd with load capacitance
§Typical values are at Vee = 5 V. T A = 25 De.
NOTE1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Actual performance can be evaluated at postMlayout simulation.
~
TEXAS
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-279
SN54ASC393, SN74ASC393
DUAL FOUR-BIT RIPPLE COUNTERS
DESIGN CONSIDERATIONS
All inputs to this 'cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for .supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
HDL FILE
•
...o
Q)
Q)
(I)
::T
CD
CD
...
(I)
BLOCK S393LH;
A1
@INPUT;
CLR1
@INPUT;
A2
@INPUT;
CLR2
@INPUT;
QA 1
@OUTPUT;
QB1
@OUTPUT;
QC1
@OUTPUT;
QD1
@OUTPUT;
QA2
@OUTPUT;
·QB2
@OUTPUT;
QC2
@OUTPUT;
QD2
@OUTPUT;
STRUCTURE
INV1
:IV110LH
INV2
:IV110LH
INV3
:IV110LH
INV4
:IV110LH
FF14
:R240BLH
:R240BLH.
FF5B
END S393LH;
A1,INV10;
CLR1,INV20;
A2,INV30;
CLR2,INV40;
INV1 O,INV20,QA 1 ,QB1 ,QC1 ,QD1;
INV30,INV40,QA2,QB2,QC2,QD2;
count definition
These counters are unidirectional with respect to count operations. Inverting the output levels will produce
a down-count sequence. Bidirectional counters are available in software macros or can be constructed
using the' ASC2405 through 'ASC2407 4-bit predesigned registers.
designing for testability
Designs employing storage or bistable elements, especially long counters (ripple or synchronous), should
consider testability of the design in its final form. The need to preset or clear and read intermediate stages
of these elements should be assessed throughout the development of custom logic circuits, with these
considerations extended to the end-equipment application with respect to maintainability. Simple actions
on the part of the ASIC designer can result in considerable cost savings, allowing the expense of IC testing,
system testing, and system maintenance to be reduced significantly.
power-up-clear/preset
Standard cell storage elements containing the capability to be asynchronously either preset or cleared may
be connected through an inverter to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve
system initialization. Access to the clear inputs from other system signals in conjunction with power-up
clear can be implemented with an OR gate.
4-2BO
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS', TeXAS 75265
SN54ASC398, SN74ASC398
QUADRUPLE 2·INPUT MULTIPLEXERS WITH POSITIVE·EDGE·
TRIGGERED COMPLEMENTARY OUTPUT REGISTER
02939, AUGUST 1986
SystemCelr 2·llm SOFTWARE
M
•
Selects One of Two 4-Bit Data Sources and
Stores Data Synchronously with System
Clock
•
Storage Register Loads New Data on
Positive-Going Transition
•
•
MACRO CELL
logic symbol t
ws
ClK
Implements Hexadecimal/BCD Shifter
Use Parallel Multiplexers for MUltiple-Bit
Words
description
The SN54ASC398 and SN74ASC398 are
standard-cell software macros implementing
four 2-line to 1-line multiplexers with storage,
The 'ASC398 implements a function table
identical with that performed by packaged
'LS398 and 'F398 multiplexers.
A1
CIA
A2
ClAZ
B1
aB
B2
aBZ
C1
ac
C2
01
acz
aD
02
aDz
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
When the word-select (WS) input is low, word 1 (A 1. B1 ,C 1, D1) is applied to the flip-flops. A high WS
input causes word 2 (A2, B2, C2, D2) to be selected. The selected word is clocked to the output terminals
on the positive-going edge of the clock pulse. The 'ASC398 is implemented with standard cell functions
indicated. The HDL netlist label for this software macro is shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
TOTAL
RELATIVE
NO. USED
TO NA210lH
CEll AREA
TOTAL
Cpd*
(pFI
IV120LH
1
2
2
1.6
262
15.7
1
12
12
6.12
1572
94.2
R2405LH
26.25
1
26.25
11.7
2931
176
T0010LH
1.5
1
1.5
10.6
16
41.75
177
4942
TOTALS
19.42
.c:
en
SN74ASC'
NA210LH
CI)
Q)
Q)
MAXIMUM ICC
(nAI
SN54ASC'
II
....
....COCO
C
297
Label: S398LH A 1.A2,B1 ,B2,Cl ,C2,D1 ,D2,ClK,WS,OA,OAZ,OB,OBZ,OC,OCZ,OD,ODZ;
:J:The equivalent power dissipation capacitance does not include interconnect capacitance.
The SN54ASC398 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC398 is characterized for operation from - 40°C to 85 DC ..
FUNCTION TABLE
INPUTS
WORD
SELECT
L
OUTPUTS§
ClK
i
H
t
X
L
CIA
aB
bl
ac
al
cl
aD
dl
a2
b2
c2
d2
OAO OBO oeO ODO
§Corresponding QnZ output is the complement
of On (shownl.
PRODUCTION DATA d.c.manls contain information
current as of publication date. Praducts conform to
spacifications per the terms af Taxas Instruments
=~~:=i~a{nr:~'li =~~~:; :.r:=::~~~s not
Copyright @ 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 650012. DALLAS. TEXAS 75265
4-281
SN54ASC398, SN74ASC398
QUADRUPLE 2·INPUT MULTIPLEXERS WITH POSITIVE·EDGE·
TRIGGERED COMPLEMENTARY OUTPUT REGISTER
logic diagram
T00101..
vec
INVl
GNO
CLK
A1
r-----i.:::J DA
r----L--> QAZ
PlL:.....r--C::> 08
p..:~
_ _ _ _--1.--> O8Z
oc
II
ocz
'-----[::J aD
'------i.:::J aDZ
D1
02
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements are made during pre-layout simulation that produce workstation output
used to identify and resolve each specific timing need.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
VT
Input threshold voltage
ICC Supply current
Cj
Input capacitance
L CLK
I WS
I
Cpd
SN54ASC398
TEST CONDITIONS
TA = 25°C
VCC = 5 V.
VCC - 4.5 V to 5.5 V, VI - VCC or 0,
TA = MIN to MAX
VCC
=
5 V,
TA
=
25~C
All others
Equivalent power
dissipation capacitance t
VCC = 5 V,
TA = 25°C
tr
= tf =
3 ns,
TVP
2.2
TEXAS . "
INSTRUMENTS
POST OFFice "BOX 655012· DALLAS. TeXAS 75265
SN74ASC398
MAX
TVP
2.2
UNIT
V
297
4942
nA
0.24
0.24
0.24
0.12
0.24
0'.12
pF
19.42
19.42
pF
. t The equivalent power dissipation capacitance does not include interconnect c;:apacitance.
4-282
MAX
SN54ASC398. SN74ASC398
QUADRUPLE 2-INPUT MULTIPLEXERS WITH POSITIVE-EDGETRIGGERED COMPLEMENTARY OUTPUT REGISTER
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Note 1)
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
tpd
elK
an
tpd
elK
OnZ
A N031Cl.x
• 1""'-
~
Ol-
DFC2Ol.II
~.~~
'""
•
v
NAO
C
Jaf;
C
o
oz
QZ
~
~x
V
C
~
~
CKftL
~'"
R FF8
V
C
10
I
NA4
l~
Q
10
Y
~
QZ
' ...
NAS
•
'FF~
~ RZ
""
00
B
~
~
~
~
~
01--
C1
~
..
=--
10
C1AZ
ACOZ
•
~v
~NA2
- f-!!-.J-
Ff2
CKCJ
ClRZ
4-290
A NA420LX
INV2
1NV7
V
v
NAB
E
A N0310l1l
•
~
v
~
o
C
~
ENA
~
Q1
~
02
D1
02
03
D3
Q4
r~
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS;TEXAS 75265
~v
NAg
OE
;!(
'Oil"
"7ir
~
SN54ASC590, SN74ASC590
8·BIT BINARY COUNTEItS WITH 3·STATE OUTPUT REGISTERS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements are made during pre-layout simulation that produce workstation output
used to identify and resolve each specific timing need.
electrical characteristics
PARAMETER
VT
ICC
TEST CONDITIONS
Input threshold voltage
Cpd
SN74ASC590
TYP
TYP
TA - 25°C
VCC - 5 V,
MAX
2.2
Supply current
0.26
CCKENZ,CCLRZ
GZ
RCK
Equivalent power
dissipation capac;:,:itance t
TA = 25°C
VCC = 5 V,
VCC = 5 V,
tr = tf = 3 ns,
TA = 25°C
UNIT
V
977
15941
TA = MIN to MAX
Input capacitance
MAX
2.2
VCC = 4.5 V to 5.5 V, VI = VCC or 0,
CCK
Ci
SN54ASC590
nA
0.26
0.12
0.12
0.24
0.48
0.24
0.48
58.24
58.24
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
tpd
CCKi
RCaZ
tpd
CCLRZl
RCOZ
tpd
RCKi
On
PARAMETERt
SN54ASC590
MIN
CL = 0
MAX
10.4
MIN
UNIT
TYP*
MAX
22.8
10.4
20.4
ns
7.4
13.5
7.4
12.3
ns
5.7
11.6
5.7
10.6
ns
3.1
6
3.1
5.6
ns
1.6
4.6
0.6
1.6
4.2
ns/pF
RCaZ
0.3
0.7
2.3
0.3
0.7
2
ns/pF
On
0.8
1.7
4.8
0.8
1.7
4.3
ns/pF
GZ!
On
Any
On
.ltpd
Any
8.t en
Any
....
Q)
Q)
J:
(/)
SN74ASC590
TYP*
0.6
ten
.ltpd
•
U)
switching characteristics over recommended ranges of operating free-air temperature and supply voltage
(unless otherwise noted) (see Notes 1 and 2)
....COCO
C
t Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%l.
tpd '" propagation delay time, low-to-high-Ievel or high-to-Iow-Ievel output
ten :!! enable time. high-impedance state to IOWH or high-logic-level output
.ltpd '" change in tpd with load capacitance
.6.ten ;;;;; change in ten with load capacitance
*Typical values are at VCC = 5 V, TA = 25°C.
NOTES: 1., These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Actual performance can be evaluated at post-layout simulation.
2. Enable and delta-enable times are measured using the conditions specified for the' ASC2407.
.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-291
SN54ASC590, SN74ASC590
8·BIT BINARY COUNTERS ""ITH 3·STATE OUTPUT REGISTERS
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block clefinitiol1 is furnished for reference.
.
HDL FILE
II
c
D)
S-
en
:r
CD
CD
...
(I)
4-292
BLOCK S590LH;
CCK
@INPUT;
CCKENZ
@INPUT;
RCK
@INPUT;
CCLRZ
@INpUT;
GZ
@INPUT;
OA
@OUTPUT;
OB
@QUTPUT;
OC
@OUTPUT;
OD
@OUTPUT;
OE
@OUTPUT
OF
@PUTPUT;
OG
@OUTPUT;
OH
@OUTPUT;
RCOZ
@OUTrUT;
STRUCTURE
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
INV1
INV2
INV5
INV6
INV7
:DFC20LH
:DFC20LH
:OFC20LH
:DFC20LH
:pI=C20LH
:DFC20LH
:DFC20LH
:DFC20LH
:IV120LH
:T0010LH
:IV110LH
:IV120LH
:IV1 tOLH
INV60,FF1 OZ,INV70,FF1 O,FFi OZ;
INV60, FF20Z, NA30, FF20, FF20Z;
INV60,FF30Z,NA40,FF30,FF30Z;
INV60 ,FF40Z, NA50, FF40, FF40Z;
INV60, FFSOZ, NA60, FF50, FF50Z;
INV60, FF60Z, NA 70, FF60,FF60Z;
INV60,FF70Z,NASO,FF70,FF70Z;
INV60, FFSOZ, NA90, FFSO,FFSOZ;
GZ,INV10;
DUM,INV20;
CCLRZ,INV50;
INV50,INV60;
NA10,INV70;
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012.• DALLAS, TEXAS 75265
SN54ASC590, SN74ASC590
8·BIT BINARY COUNTERS WITH 3·STATE OUTPUT REGISTERS
HDL FILE (Continued)
STRUCTURE (Continued)
NA 1
:NA220LH
NA10
:NA210LH
NA2
:NA420LH
NA3
:NA210LH
NA4
:NA310LH
NA5
:NA410LH
NA6
:NA310LH
NA7
:NA410LH
NAS
:NA510LH
NA9
:NA410LH
N02
:N0310LH
N03
:N0310LH
FFAD
:R2407LH
FFEH
. :R2407LH
END S590LH;
NA 1OO,CCK,NA 10;
NA 1O,CCKENZ,NA 100;
FFSQ,N030,N020,FFl Q,RCOZ;
NA 1O,FFl Q,NA30;
NA 1O,FFl Q,FF2Q,NA40;
NA 1O,FFl Q,FF2Q,FF3Q,NA50;
NA 10,N020,FFl Q,NA60;
NA 1O,FFl Q,N020,FF5Q,NA 70;
NA 1O,FFl Q,N020,FF5Q,FF6Q,NASO;
NA 1O,FFl Q,N020,N030,NA90;
FF2QZ,FF3QZ,FF4QZ,N020;
FF5QZ, FF6QZ, FF7QZ, N030;
INV20,FF 1Q,FF2Q,FF3Q,FF4Q,RCK,INVl O,QA,QB,QC,QD;
INV20, FF5Q,FF6Q,FF7Q, FFSQ,RCK, INV 10, QE, QF, QG, QH;
count defintion
These counters are unidirectional with respect to count operation. Inverting the output levels will produce
a down-count sequence. Bidirectional counters are available in software macros or can be constructed
using the' ASC2405 through' ASC2407 4-bit predesigned registers. Additional single bits can be achieved
with predesigned flip-flops offered in TI's standard cell family.
II
...
U)
G)
G)
designing for testability
Designs employing storage or bistable elements, especially long counters (ripple or synchronous), should
consider testability of the design in its final form. The need to preset or clear and read intermediate stages
of these elements should be assessed throughout the development of custom logic circuits, with these
considerations extended to the end-equipment application with respect to maintainability. Simple actions
on the part of the ASIC designer can result in considerable cost savings, allowing the expense of IC testing,
system testing, and system maintenance to be reduced significantly.
.l:
en
...caca
o
power-up-clear/preset
Standard cell storage elements containing the capability to be asynchronously either preset or cleared may
be connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Access to the clear inputs from other system signals in conjunction with the power-up clear can be
accomplished with an AND gate.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-293
•
C
I»
r+
I»
(J)
::r
(1)
(1)
r+
(I)
4-294
SN54ASC593X,SN74ASC593X
8-BIT BINARY COUNTERS WITH INPUT REGISTERS
D2939. AUGUST 1986
SystemCell™
2-/lm SOFTWARE MACRO CELL
logic symbol t
•
8-Bit Counter with Input Registers
•
Individual Positive-Edge-Triggered Clocks for
Counter and Register
•
3-State Counter Outputs Provide Parallel
Bus Interface
•
Counter Has Direct Clear and Clock Enable
•
Ripple-Carry Output Simplifies Expansion
G1
GZ
CCLRZ
CCKEN
CCKENZ
RCOZ
description
The SN54ASC593X and SN74ASC593X are
standard-cell software macros implementing
synchronous 8-bit binary counter elements. The
8-bit configuration provides the custom IC
designer a counter to embed in ASICs in its most
efficient form, and the 8-bit length simplifies
construction of large counters. The' ASC593X
implements a count sequence identical with that
performed by packaged 'HC593 and 'LS593
counters, but the common data input/output
terminals have been separated to provide
individual data inputs to the register and 3-state
outputs from the counter.
The 'ASC593X implements an 8~bit storage
register that feeds an 8-bit binary counter.
CCK---i>
CLOADZ
RCKENZ
RCK---i>
A
B
QB
C
QC
o
<;lD
E
F
QE
QF
G
QG
H
QH
I
en
.....
Q)
Q)
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
lEG Publication 617·12.
The counter has parallel 3-state outputs. Separate clocks are provided for both the binary counter am;1
storage register. The' ASC593X is implemented with the standard cell functions indicated. The HDL netlist
label for this software macro is- shown on the last line of the table on the following page.
PRODUCTION DATA documents contain information
current a. of publication date. Products conform to
specifications par the tarms of Texas Instruments
::=~~~ai~:1~1i ~r:~::i:r IIID:==~ nat
.c
U)
as
.....
as
C
Copyright © 1986. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-295
SN54ASC593X, SN74ASC593X
8·BIT BINARY COUNTERS WITH INPUT REGISHRS
CELL NAME
RELATIVE
CELL AREA
NO. USED
TOTAL
Cpd t
CELL AREA
(pF)
MAXIMUM ICC
(nA)
SN54ASC'
SN74ASC'
AN210LH
1.5
8
12
7.2
1552
92.8
DFB20LH
7.7
8
61.6
30.08
7472
448
IV110LH
0.75
4
3
1.76
420
25.28
IV120LH
IV140LH
1
1.5
2
2
1.6
262
15.7
1
1.5
1.61
190
11.4
IV212LH
1.5
8
12
4
720
86.4
NA210LH
1
19
19
9.69
2489
148.96
NA220LH
1.5
1
1.5
1
131
7.84
NA310LH
1.25
3
3.75
1.5
489
29.34
NA410LH
NA420LH
1.5
3
4.5
33.6
1
2.5
1.5
0.96
561
2.6
312
18.7
NA510LH
1.75
1
1.75
0.52
213
12.8
N0310LH
1.25
2
2.5
0.64
312
18.66
11.1
TO NA210LH
II
TOTAL
RELATIVE
OR210LH
1.5
1
1.5
~86
185
R2406LH
26.25
2
52.5
23.4
5862
352
T0010LH
1.5
1
1.5
177
10.6
-
TOTALS
183.1
86.32
21347
1324
65
Label: S593XLH A,8,C,D,E,F,G,H,CCK,CCKEN,CCKENZ,RCK,RCKENZ,CCLRZ,CLOADZ,G1,GZ,OA,OB,
OC,OO,OE,OF,OG,OH,RCOZ;
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
The binary counter features a direct clear input CCLRZ and a count enable input CCKENZ. For cascading,
a ripple-carry output RCaZ is provided. Expansion is easily accomplished by tying RCaZ of the lower stage
to CCKENZ of the higher stage, etc. Both the counter and register clocks are positive-edge-triggered. If
the user wishes to connect both clocks together, the counter state will equal the previous register contents
plus one. Internal circuitry prevents clocking from the clock enable.
The SN54ASC593X is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC593X is characterized for operation from - 40°C to 85 °C.
4-296
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DAL~S; tEXAS 75266
logic diagram
1V12OLx
& _________________________________ ,.~V
~V1
o
01
ORZ10Lx
~r_'\~y~
~
_____________________,
ACO'
QA
~
"i
~
~z
~(J)
x..,
~;;t1~
CICI
CD
~C:~
~~
::::j
~~~
iii
CCI
~!TI
l;
TQ010L1c
"
'"'"
ONO
vee
m
N
Of
:.=
<
n
Q
e
Z en
....
mZ
=
U'I
en.j:lo
:e~
n
.... U'I
::Cea
_w
2><
""CII"
een
H
D---
.... 2
m.j:lo
=""'"
1:':'_en
enn
mea
=w
en><
.... U'I
~
,:."
co
-..J
Data Sheets
II
SN54ASC593X,SN74ASC593X
8-BIT BINARY COUNTERS WITH INPUT REGISTERS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements, made during pre-layout simulation, produce workstation output used
to identify and resolve each specific timing need.
electrical characteristics
PARAMETER
VT
Input threshold voltage
ICC
Supply current
Ci
IIc
!I»
en
i"
...m
UI
SN54ASC593X
TEST CONDITIONS
TYP
0,13
CCK
0.26
0,26
CLOADZ
0.49
0,11
0.49
0,24
0.24
0.12
0.12
86,32
86.32
VCC = 5 V,
TA = 25°C
All others
Equivalent power
dissipation capacitancQ t
t The equivalent
Vce - 5 V,
TA' = 25°C
tr - tf - 3 ns,
UNIT
V
1324
0,13
Gl
MAX
21347
A,thru H
GZ
Cpd
TYP
2.2
2.2
TA - 25°C
VCC - 5 V.
VCC - 4.5 V to 5.5 V, VI - VCC or 0,
TA = MIN to MAX
Input capacitance
SN74ASC593X
MAX
nA
pF
0.11
pF
pow~r dissipation capacitance does not include interconnect capacitance,
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Notes 1 and 2)
,
FROM
(INPUT)
TO
(OUTPUT)
tpd
CCKt
Reoz
9
23.2
tpd
CCLRZ.
RCOZ
B
tpd
CCLRU
an
tpd
CCKt
an
tpd
CLOADZ
tpd
ten
Atpd
Any
an
Atpd
Any
RCaZ
Aten
Any
an
PARAMETER*
TEST
sN54ASC593X
TYP§
MAX
CONDITIONS
MIN
SN74ASC593X
TYP§
MAX
MIN
UNIT
20.7
13,B
ns
10
15
21,1
9
8
10
19
ns
9
23.1
9
20,7
ns
an
9
21,6
9
ns
CLOADZ
RCOZ
10
24,4
10
19.4
22,1
Gl or GZt
an
4
B,B
4
B.l
ns
0.6
1.6
4,6
0.6
1.6
4.2
ns/pF
0.3
O,B
0.7
2.3
0.3
0.7
2
ns/pF
1.7
4.B
0.8
1.7
4.4
ns/pF
CL = 0
ns
ns
t Propagation delay times are measured from the 44% point of VI to the 44% point of Va with tr = tf = 3 ns (10% and 90%).
tpd '" propagation delay time, low-to-high-Ievel or high-to-Iow-Ievel output
ten '" enable time, low-to-high-Ievel or high-to-Iow·level output
.6.tpd ,.. change in tpd with ·Ioad, capacitance
.t1ten !iiii change in ten with load capacitance
§ Typical values are at V CC = 5 V, T A = 25°C.
NOTES: 1. These,switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Actual performance can be evaluated at post-layout simulation.
2, Enable and delta-enable times are measured using the conditions specified for the 'ASC2407.
4-298
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS,
TE~AS
75265
S~54ASC593X, SN74ASC593X
8·BIT BINARY COUNTERS WITH INPUT REGISTERS
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
HDL FILE
BLOCK S593XLH;
@INPUT;
B
@INPUT;
C
@INPUT;
D
@INPUT;
E
@INPUT;
F
@INPUT;
@INPUT;
G
H
@INPUT;
CCK
@INPUT;
CCKEN
@INPUT;
@INPUT;
CCKENZ
RCK
@INPUT;
@INPUT;
RCKENZ
CCLRZ
@INPUT;
@INPUT;
CLOADZ
G1
@INPUT;
GZ
@INPUT;
QA
@OUTPUT;
OB
@OUTPUT;
QC
@OUTPUT;
QD
@OUTPUT;
QE
@OUTPUT
QF
@OUTPUT;
QG
@OUTPUT;
@OUTPUT;
OH
: RCOZ
@OUTPUT;
A
STRUCTURE
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
FFA
FFB
FFC
FFD
FFE
:AN210LH
:AN210LH
:AN210LH
:AN210LH
:AN210LH
:AN210LH
:AN210LH
:AN210LH
:DFB20LH
:DFB20LH
:DFB20LH
:DF!320LH
:DFB20LH
•
...
II)
CI)
CI)
.s:::
Ul
...
CIS
CIS
C
INVeO,NA30,AN20;
INV60,NA50,AN30;
INV!\O,NA70,AN40;
INV60,NA90,AN50;
INV6Q,NA 11 O,AN60;
INV60,NA 130,AN70;
INV60,NA 150,AN80;
INV60,NA 170,AN90;
AN20,NA20,FFAQZ,INV100,FFAQ,FFAQZ;
AN30,NA4Q,FFBQZ,NA 190,FFBQ,FFBQZ;
AN40,NA60;FFCQZ,NA200,FFCQ,FFCQZ;
AN50,NA80,FFDQZ,NA210,DUM,FFDQZ;
AN60,NA 1OO,FFEQZ,NA220,FFEQ,FFEQZ;
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-299
SN54ASC593X, SN74ASC593X
8·BIT BINARY COUNTERS WITH INPUT REGISTERS
HDL FILE (Continued)
II
C
r»
Dr
en
:::r
CD
CD
...
til
4-300
STRUCTURE (Continued)
:DFB20LH
FFF
FFG
:DFB20LH
FFH
:DFB20LH
INV1
:IV120LH
INV10
:IV110LH
INV11
:IV212LH
INV12
:IV212LH
INV13
:IV212LH
INV14
:IV212LH
INV15
:IV212LH
INV16
:IV212LH
INV17
:IV212LH
INV18
:IV212LH
INV2
:IV110LH
INV5
:IV110LH
INV6
:IV120LH
INV7
:IV140LH
INV8
:IV110LH
INV9
:T0010LH
NA1
:NA220LH
NA10
:NA210LH
NA11
:NA210LH
NA12
:NA210LH
NA13
:NA210LH
NA14
:NA210LH
NA15
:NA210LH
NA16
:NA210LH
NA17
:NA210LH
NA18
:NA420LH
NA19
.:NA210LH
NA2
:NA210LH
NA20
:NA310LH
NA21
:NA410Ll-i
NA22
:NA310LH
NA23
:NA410LH
NA24
:NA510LH
NA25
:NA410LH
NA26
:NA310LH
NA27
:NA210LH
NA28
:NA210LH
NA3
:NA210LH
NA4
:NA210LH
NA5
:NA210LH
NA6
:NA210LH
NA7
:NA210LH
NA8
:NA210LH
NA9
:NA210LH
N01
:OR210LH
N03
:N0310LH
N04
:N0310LH
AN70,NA 120,FFFQZ,NA230,FFFQ,FFFQZ;
AN80,NA 140,FFGQZ,NA240,DUM,FFGQZ;
AN90,NA 160,FFHQZ,NA250,FFHQ,FFHQZ;
GZ,INV10;
NA10,INV100;
FFAQZ,N010,QA;
FFBQZ,N010,QB;
FFCQZ,N010,QC;
FFDQZ,N010,QD;
FFEQZ,N010,QE;
FFFQZ,N010,QF;
FFGQZ,N010,QG;
FFHQZ,N010,QH;
CCKEN,INV20;
CCLRZ,INV50;
INV50,INV60;
CLOADZ,INV70;
NA270,RCFQZ;
DUM,CLR;
NA260,CCK,NA 1O;
INV70,F5Q,NA 10O;
INV70,F5QZ,NA 11O;
INV70,F6Q,NA 120;
INV70,FSQZ,NA 130;
INV70,F7Q,NA 140;
INV70,F7QZ,NA 150;
F8Q,INV70,NA 160;
INV70,F8QZ,NA 170;
FFHQ,N040,N030,FFQA,RCOZ;
NA 1O,FFAQ,NA 190;
INV70,F1 Q,NA20;
NA 1 0,FFQA,FFBQ,NA200;
NA 1 0,FFAQ,FFBQ,FFCQ,NA21 0;
NA 1 0,FFAQ,N030,NA220;
NA 1 0,FFAQ,N030,FFEQ,NA230;
NA 1 0,FFAQ,N030,FFEQ,FFFQ,NA240;
NA 10,FFAQ,N030,N040,NA250;
NA 10,INV20,CCKENZ,NA260;
RCK,NA280,NA270;
RCKENZ,NA270,NA280;
INV70,F1 QZ,NA30;
INV70,F2Q,NA40;
INV70;F2QZ,NA50;
INV70,F3Q,NA60;
INV70,F3QZ,NA 70;
F4Q,INV70,NA80;
INV70,F4QZ,NA90;
INV10,G1,N010;
FFBQZ,FFCQZ,FFDQZ,N030;
FFEQZ,FFFQZ,FFGQZ,N040;
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ASC593X, SN74ASC593X
8·BIT BINARY COUNTERS WITH INPUT REGISTERS
HDl FilE (Continued)
STRUCTURE (Continued)
:R2406LH
FF14
FF5S
:R2406LH
END S593XLH;
CLR,A,B,C,D ,RCFQZ,F 1 Q,F1 QZ,F2Q,F2QZ,F3Q,F3QZ,F4Q,F4QZ;
CLR,E,F,G,H,RCFQZ,F5Q,F5QZ,F6Q,F6QZ,F7Q,F7QZ,FSQ,FSQZ;
count definition
These counters are unidirectional with respect to count operation. Inverting the output levels will produce
a down-count sequence. Bidirectional counters are available in software macros or can be constructed
using the' ASC2405 through' ASC2407 4-bit predesigned registers.
designing for testability
Designs employing storage or bistable elements, especially long counters (ripple or s·ynchronous), should
consider testability of the design in its final form. The need to preset or clear and read intermediate stages
of these elements should be assessed throughout the development of custom logic circuits, with these
considerations extended to the end-equipment application with respect to maintainability. Simple actions
on the part of the ASIC designer can result in considerable cost savings, allowing the expense of IC testing,
system testing, and system maintenance to be reduced significantly.
power-up-clear/preset
Standard cell storage elements containing the capability to be asynchronously either preset or cleared may
be connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Access to the clear inputs from other system signals in conjunction with the power-up clear can be
accomplished with an AND gate.
II...
U)
Q)
Q)
.s::.
Ul
...caca
C
TEXAS . "
INSTRUMENTS
POST OFFicE BOX 655012 • DALLAS, TEXAS 75265
4-301
II
...C
I»
I»
en
::r
CD
CD
...
til
4-302
SN54ASC595, SN74ASC595
8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
02939, AUGUST 1986
SystemCell™
2-j.lm SOFTWARE MACRO CELL
•
a-Bit Serial-In, Parallel-Out Shift Registers
with- Output Storage
•
Buffered Clear and Output-Enable Inputs
logic symbol t
GZ
RCK
•
Shift Register has Direct Clear
•
Embedded Clock Drivers Provide Clock
Buffering
•
Dependable Texas Instruments Quality and
Reliability
SRCLRZ
SRCK
SER
QA
OB
OC
OD
description
OE
The SN54ASC595 and SN74ASC595 are
standard-cell software macros implementing
synchronous 8-bit parallel-out shift registers with
output storage registers, The 8-bit configuration
provides the custom IC designer a multifunction
register to embed in ASICs in its most efficient
form, The 8-bit length simplifies construction of
large registers. The' ASC595 implements a shift
sequence identical with that performed by
packaged 'HC595 and 'LS595 registers,
OF
OG
2D
3'17
OH
OHP
tThis symbol is in accordance with ANSI/IEEE Std91-1984 and
IEC Publication 617-12.
U)
These macros each contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit Ootype storage
register. The storage register has parallel 3-state outputs, Separate clocks are provided for both the shift
register and the storage register, The shift register has a'direct-overriding clear, serial input, and serial
output pins for cascading, Both the shift register and storage register clocks are positive-edge triggered.
If the user wishes to connect both clocks together, the shift-register state will always be one clock pulse
ahe?ld of the storage register, The' ASC595 is implemented with the standard cell functions indicated,
The HOL netlist label for this software macro is shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USED
TO NA210LH
TOTAL
TOTAL
RELATIVE
Cpd*
(pFI
SN54ASC'
CELL AREA
1
0.75
0.44
105
6.32
IV120LH
1
2
2
1.6
262
15.70
R2401LH
25.25
26.25
2
2
50.5
52.5
20.6
22
6142
6062
370
384
177
10.6
105.75
44.64
12748
787
-
1
TOTALS
8
en
....COCO
C
SN74ASC'
0.75
T0010LH
Q)
Q)
.c::
MAXIMUM ICC
(nAI
IV110LH
R2407LH
II
....
Label: S595LH SER,SRCK,SRCLRZ,RCK,GZ,QA,QB,QC,QD,QE,QF,QG,QH,QHP;
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
The SN54ASC595 is characterized for operation over the full military temperature range of - 55°C to
'"25°C. The SN74ASC595 is characterized for operation from -40°C to 85°C,
Copyright @ 1986, Texas Instruments Incorporated
PRODUCTION DATA documants contain information
currant 81 of publication data. Products canfarm to
:acifications par tha tarms af Texas Instruments
n'::=~i~8{::I~'li
=::i:r 1I~D:::~:,:~~ not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-303
SN54ASC595, SN74ASC595
8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
FUNCTION TABLE
SHIFT REGISTER
INPUTS
OUTPUT REGISTER
INPUTS
OUTPUTS
SRCLRZ
SRCK
SER
sQA
X
X
X
X
X
X
X
L
L
L
H
L
H
L
sQAn
sOG n
sQAn
sOG n
H
H
sQAn
sOG n
sQG n
H
X
X
X
t
t
t
t
L
L
sQAn
sQG n
sQG n
H
L
X
sQAO
sOBO
sQHo
sOHO
L
H
H
H
sOB ... sOH
X
X
X
X
OUTPUTS
sOHP
RCK
GZ
QA
X
X
X
H
Z
Z
Z
L
L
L
t
L
QAO
L
QBO
L
QHO
L
sOG n
L
L
rQAO
rOBo
rQHO
l
t
L
rQAO
sOA
rQHo
sQH
t
t
L
rOBo
sOB
sQB
sQB
sOH
sQG n
L
sOA
sQA
L
OB ..• OH
sQH
H = high level (steady state)
L = low level (steady state I
sa = shift register output,
x = irrelevant (any input, including transitions)
t = transition from low to high level.
QAO. QBo. QHO = the level of QA. OB. or QH. respectively. before the indicated steady-state input conditions
were established.
QAn. OG n = the level of QA or OG before the most-recent t transition of the clock; indicates a one-bit shift.
III09iC diagram
c
~
....
CI)
&lICk
CD
CD
lEft
en
IlAQ.RZ
....
~'~.
oz
CI)
en
::r
C:~---------------------------------------------,
01
02
Dl
D2
Q3
Q4
D3
D4
QE
C»'
QG
OH
FRi8
FFEH
OHP
4-304
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 •
D~LLAS,
TEXAS 75265
SN54ASC595, SN74ASC595
8·BIT SHIFT REGISTERS WITH 3·STATE OUTPUT REGISTERS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements, made during pre-layout simulation, produce workstation output used
to identify and resolve each specific timing need.
electrical characteristics
PARAMETER
SN54ASC595
TEST CONDITIONS
VT
Input threshold voltage
ICC
Supply current
TYP
TA - 25°C
VCC - 4.5 V to S.S'V, VI - VCC or 0,
TA
=
Ci
Input capacitance
RCK,SRCK
SRCLRZ
5 V,
TA
=
25°C
SER
Cpd
= 5 V,
= 25°C
Equivalent power
VCC
dissipation capacitance
TA
tr
= tf =
3 ns,
MAX
2.2
7B7
0.24
0.24
O.4B
0.4B
0.12
0.12
0.13
0.13
44.64
44.64
UNIT
V
1274B
MIN to MAX
=
VCC
TYP
2.2
VCC - 5 V,
GZ
SN74ASC595
MAX
nA
pF
pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Notes 1 and 2)
PARAMETERt
tpd
tpd
FROM
TO
TEST
(iNPUTI
(OUTPUTI
CONDITIONS
SRCKI
QHP
SN74ASC595
SN54ASC595
MIN
TYP*
MAX
5.5
11.3
MIN
UNIT
TYP*
MAX
5.5
10.4
ns
5.5
11.6
5.5
10.6
ns
3.6
7
3.6
6.6
ns
ten
GZ.
Qn
3.1
5.6
3.1
4.B
ns
atpd
..6.t en
Any
On
0.6
1.7
4.6
0.6
1.7
4.2
ns/pF
GZl
On
O.B
1.7
4.B
O.B
1.7
4.3
ns/pF
=0
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr
tpd '" propagation delay time, low·to·high·level or high-to-Iow-Ievel output
tpHL " propagation delay time, high-to-Iow level output
= tf
CD
CD
.s::.
Ul
CO
Qn
QHP
CL
CI)
;
RCKI
SRCLRZ
tpHL
II...
C
= 3 ns (10% and 90%1-
ten ;;;;; enable time, high-impedance state to high- or low-level output
4tpd ;:; change in tpd with load capacitance
.6.ten :; change in ten with load capacitance
*Typical values are at VCC = 5 V, TA = 25°C.
NOTES: 1. These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Actual performance can be evaluated at post-layout simulation.
2. Enable and delta-enable times are measured using the conditions specified for the' ASC2407.
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed, The following printout
of the HDL block definition is furnished for reference,
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
4-305
SN54ASC595, SN74ASC595
8·BIT SHIFT REGISTERS WITH 3·STATE OUTPUT REGISTERS
HDL FILE
BLOCK S595LH;
SER
@INPUT;
SRCK
@INPUT;
SRCLRZ
@INPUT;
RCK
@INPUT;
GZ
@INPUT;
QA
@OUTPUT;
QB
@OUTPUT;
QC
@OUTPUT;
QD
@OUTPUT;
QE
@OUTPUT
Ci.F
@OUTPUT;
QG
@OUTPUT;
QH
@OUTPUT;
QHP
@OUTPUT;
STRUCTURE
INV1
INV2
INV3
INV4
FF14
FF58
FFAD
'FFEH
END S595LH;
II
c
...
I»
I»
rJ)
::r
(1)
(1)
...en
:T0010LH
:IV120LH
:IV110LH
:IV120LH
:R2407LH
:R2407LH
:R2401LH
:R2401LH
DUM,INV10;
GZ,INV20;
SRCLRZ,INV30;
INV30,INV40;
INV10,FFAQ,FFBQ,FFCQ,FFDQ,RCK,INV20,QA,QB,QC,QD;
INV10,FFEQ,FFFQ,FFGQ,QHP,RCK,INV20,QE,QF,QG,QH;
INV40,SER,SRCK,FFAQ,FFBQ,FFCQ,FFDQ;
INV40,FFDQ,SRCK,FFEQ,FFFQ,FFGQ,QHP;
shift defintion
The:;;e registers are unidirectional with respect to shift operations and the relationship for shifting left or
right is defined by the IC designer. Bidirectional registers are available in software macros or can be .
constructed using the' ASC2405 through' ASC2407 4-bit predesigned registers.
designing for testability
Designs employing storage or bistable elements, especially long registers (ripple or synchronous), should
consider testability of the design in its final form. The need to preset or clear and to read intermediate
stages of these elements should be assessed throughout the development of custom logic circuits, with
these considerations extended to the end-equipment application with respect to maintainability. Simple
actions on the part of the ASIC designer can result in considerable cost savings, allowing the expen:;;e
of IC testing, system testing, and system maintenance to be reduced 'significantly.
power-up-clear/preset
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of the clear or preset inputs from other system signal in conjunction with the power-up clear can
be accomplished with an AND gate.
4-306
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS,
TE~AS
75265
SN54ASC598X, SN74ASC598X
8-BIT SHIFT REGISTERS WITH INPUT REGISTERS
02939, AUGUST 1986
SystemCell™
2-llm SOFTWARE MACRO CELL
•
8-Bit Serial-In, Parallel-Out Shift Registers
with Inpllt Storage
•
Buffered Clear and Output-Enable Inputs
logic symbol t
SRG8
GZ
•
Shift Register Has Direct Clear
•
Emblt
SLOZ
Dependable Texas Instruments Quality and
Reliability
RCK--l>c:21
os
SERO
description
1,50
SERl
The SN54ASC598X and SN74ASC598X are
standard-cell software macros implementing
8-bit parallel-out shift registers with input
storage registers, The 8-bit configuration
provides the custom IC designer a multifunction
register to embed in ASICs in its most efficient
form. The 8-bit length simplifies oonstruction of
large registers. The 'ASC598X implements a
count sequence identical with that performed by
packaged 'HC598 and 'LS598 registers.
OA
20
3D
08
20
3D
QS
DC
DO
QC
DE
QE
QO
OF
QF
OG
QG
20
OH
QH
3D
QHP
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
These macros each contain an 8-bit serial-in,
IEC Publication 617-12.
parallel-out shift register fed by an 8-bit D-type
input register. The shift register has parallel
3-state outputs, Separate clocks are provided for the shift register and the input register, The' ASC598X
is implemented with the standard cell functions indicated, The HDL netlist label for this software macro
is shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USED
TOTAL
TOTAL
RELATIVE
Cpd*
(pFI
MAXIMUM ICC
(nAI
SN54ASC'
SN74ASC'
AN210LH
1.5
10
15
9
1940
116.0
DFS20LH
7.7
8
61.6
30.08
7472
448
IVll0LH
0.75
3
2.25
1.32
315
18.96
IV120LH
1
1.5
1.5
1
1.5
41
-
4
4
3.2
524
31.4
1
1.5
1.61
190
11.4
8
18
12
4
1440
86.4
18
9.18
2358
141.12
1
1.5
0.86
185
11.1
2
50.5
23.38
5862
352
177
10.6
20463
1227
TO NA210LH
IV140LH
IV21;1LH
NA210LH
OR210LH
R2406LH
T0010LH
CELL AREA
-
1
TOTALS
56
166.35
82.63
Label: S598XLH DA,D8,DC,DD,DE,DF,DG,DH,RCK,SCK,SCKENZ,SLOZ,SCLRZ,SERO,SER1,DS,GZ,OA,
OB,OC,OD,OE,OF,OG,OH,OHP;
:l:The equivalent power dir;;sipation capacitance does not include interconnect capacitance.
PRODUCTIOII DATA d..,monts coatoi. iniormalipn
cumnt •• of pubUmi •• date. Products conf.rm to
spacifications par the tanns at T8QI Instruments
:'!:~~~·{::I~'l.i ~::I:~i:r l!1.=~:':~~ not
Copyright © 1986. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-307
SN54ASC598X, SN74ASC598X
8-BIT SHIFT REGISTERS WITH INPUT REGISTERS
The shift register has a direct overriding clear, multiplexed dual serial inputs, and dual serial outputs to
simplify cascading. Both the shift register and input register clocks are positive-edge triggered. If the user
wishes to connect both clocks together, the shift-register output will be half or double the previous value
of the storage register. The shift register has a clock emible associated with internal circuitry that prevents
it from triggering the clock.
'
The SN54ASC598X is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC598X is characterized for operation from -40°C to 85°C.
FUNCTION TABLE
,INPUT REGISTER
RCK
INPUTS
DA ... DH
X
X
t
L
t
X
X
X
X
X
X
X
a
X
a
X
X
X
X
X
X
X
h
X
RAO
h
a
X
X
X
X
X
CLOCK
SCLRZ
GZ
X
X
H
x
i.
L
X
X
h
H
L
H
RHO
h
H
L
L
H
L
L
X
X
X
X
X
H
L
H
L
H
RA. .. RH
X
X
a
X
X
X
X
X
SHIFT REGISTER
INPUTS
OUTPUTS
SCKENZ SCK SLDZ
X
X
X
X
X
X
t
t
L
L
L
L
H
L
H
L
OUTPUTS
SERIAL
LOAD
OS
SERO SER1
L
X
X
X
X
X
X
X
X
H
L
H
!
H
L
H
t
H
L
L
!
H
H
L
t
H
H
X
L
X
X
X
X
X
QA
QB ... QH
QHP
X
Z
Z
Z
QH
X
X
X
X
X
X
L
L
L
L
~AO
OHO QHo
RA
OBO
RB
H
QAn
OG n OG n
H
OAn
OG n
QG n
L
QAn
QG n
QG n
H
H
QAn
OG n
OG n
L
L
QAn
OG n
OG n
X
~AO
OBo
OHO OHO
RH
RH
C
I»
r+
I»
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
en
:r
CD
CD
timing requirements
r+
(II
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation produce workstation output used
to identify and resolve each specific timing need.
,
4-308
TEXAS . "
INSTRUMENTS
1:'05T OFFICE BOX 655012 • DALLAS, TEXAS 75266
SN54ASC598X, SN74ASC598X
8·BIT SHIFT REGISTERS WITH INPUT REGISTERS
logic diagram
GZ
~
os
....,
8CLRZ
NV4
1V1401..1C
A
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-
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265
~
A
V
~EINV18
"
.
SN54ASC651, SN54ASC652, SN74ASC651, SN74ASC652
8·BIT BIDIRECTIONAL UNIVERSAL TRANSCEIVER REGISTERS
logic diagram •ASC652
a
....en
Q)
Q)
.J:
en
....C1:IC1:I
C
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4·319
SN54ASC651, SN54ASC652, SN74ASC651, SN74ASC652
8·BIT BIDIRECTIONAL UNIVERSAL TRANSCEIVER REGISTERS
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the dlocked cells embedded in the software macros.
Evaluations of timing requirements made during pre-layout simulation produce workstation output used
to identify and resolve each specific timing need.
electrical characteristics
PARAMETER
TEST CONDITIONS
SN54ASC651
SN74ASC651
SN54ASC652
SN74ASC652
MAX
TYP
Input threshold voltage
VT
S651LH
Supply current
ICC
S652LH
VCC - 5 V,
2.2
TA - 25°C
II
c
C\)
...
TA = 25°C
VCC = 5 V,
TA
GBAZ, SAB,
Equivalent power
Cpd dissipation
capacitance t
S651LH
VCC = 5 V,
S652LH
TA = 25°C
tr
=
3 ns,
0.48
0,48
0.12
0.12
0.49
0.58
0.58
91.06
91.06
104.1
104.1
25°C
= tf =
1501
0.58
0.49
SBA
Output capacitance
Co
C\)
CJ)
VCC = 5 V,
V
1332
25002
CAB,CBA
Input capacitance GAB
2.2
0.58
UNIT
MAX
22186
VCC - 4.5 V to 5.5 V. VI - VCC or 0,
TA = MIN to MAX
An or Bn
Ci
TYP
nA
pF
pF
pF
t The e.quivarent power digs.ipatian capacitance does not include interconnect capacitance.
::T
!CD
o
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Notes 1 and 2)
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
tpd
CAB,CBA
tpd
A,B
PARAMETERt
SN54ASC651
SN74ASC651
SN54ASC652
SN74ASC652
TYP*
MAX
A,B
10,4
!l,A
5,4
6.6
12.3
4.7
8.7
CL
MIN
=0
UNIT
TYP*
MAX
20.9
10.4
19.1
10.1
5.4
9.4
tpd
SAB,SBA
A,B
ten
GAB,GBAZ
A,B
~tpd
Any
Any
0.3
0.9
2.3
~ten
GAB,GBAZ
Any
0,4
0.9
2,3
MIN
6.6 ' 11.8
4.7
8.3
0,4
0.9
2.1
0.5
0.9
2.1
ns
ns
ns/pF
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tpd '" propagation delay time, low-to-high-Ievel or high-to-Iow-Ievel output
ten "'enable time, high-impedance state to low- or high'iogic:level output
~tpd 8 change in tpd with load capacitance
.6.ten
5
change in ten with load capacitance
~Typical values are at VCC = 5 V, TA = 25°C.
NOTES: 1. These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation"uses actual interconnect capacitance values.
2. Enable and delta-enable times are measured using the conditions specified for the SN54ASC2311 and SN74ASC2311
(lV222LH).
4-320
TEXAS •
INSTRUMENTS
POST OFFICE soX 655012 • DALLAS! TEXAS 75265
SN54ASC651. SN54ASC652. SN74ASC651. SN74ASC652
8·BIT BIDIRECTIONAL UNIVERSAL TRANSCEIVER REGISTERS
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
HOL FILE
BLOCK S651 LH;
GBAZ
@INPUT;
@INPUT;
GAB
SBA
@INPUT;
@INPUT;
SAB
@INPUT;
CBA
@INPUT;
CAB
A1
@INOUT;
@INOUT;
A2
A3
@INOUT;
@INOUT
A4
A5
@INOUT;
@INOUT;
A6
@INOUT;
A7
@INOUT;
A8
@INOUT;
B1
@INOUT;
B2
@INOUT;
B3
@INOUT;
B4
@INOUT;
B5
B6
@INOUT;
@INOUT;
B7
@INOUT;
B8
STRUCTURE
INV1
INV10
INV11
INV2
INV20
INV21
INV22
INV23
INV24
INV25
INV26
INV27
INV3
INV36
INV37
INV38
INV39
:IV140LH
:IV222LH
:IV222LH
:IV140LH
:IV222LH
:IV222LH
:IV222LH
:IV222LH
:IV222LH
:IV222LH
:IV222LH
:IV222LH
:IV140LH
:IV222LH
:IV222LH
:IV222LH
:IV222LH
a...
en
CD
CD
.s:
en
...caca
Q
SBA,SBAZ;
SNA9,GBA,A3;
SNA 12,GBA,A4;
SBAZ,SBA1;
SNA 15,GAB1,B1;
SNA18,GAB1,B2;
SNA21 ,GAB1 ,B3;
SNA24,GAB1,B4;
SNA27,GBA,A5;
SNA30,GBA,A6;
SNA33,GBA,A 7;
SNA36,GBA,A8;
SAB,SABZ;
SNA39,GAB1,B5;
SNA42,GAB1,B6;
SNA45,GAB1,B7;
SNA48,GAB1,B8;
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-321
SN54ASC651, SN54ASC6~2, SN74ASC651, SN74ASC652
B·BIT BIDIRECTIONAL UNIVERSAL TRANSCEIVER REGISTERS
HDL FILE (Continued)
STRUCTURE (Continued)
INV4
:IV140LH
:IV110LH
INV5
INV6
:IV140LH
INV7
:IV140LH
INV8
:IV222LH
INV9
:IV222LH
NAl
:NA210LH
:NA210LH
NA10
NAll
:NA210LH
:NA210LH
NA12
NA13
:NA210LH
NA14
:NA210LH
:NA210LH
NA15
:NA210LH
NA16
NA17
:NA210LH
NA18
:NA210LH
NA19
:NA210LH
:NA210LH
NA2
NA20
:NA210LH
NA21
:NA210LH
:NA210LH
NA22
NA23
:NA210LH
NA24
:NA210LH
:NA210LH
NA25
:NA210LH
NA26
NA27
:NA210LH
NA28
:NA210LH
:NA210LH
NA29
:NA210LH
NA3
:NA210LH
NA30
NA31
:NA210LH
NA32
:NA210LH
:NA210LH
NA33
NA34
:NA210LH
NA35
:NA210LH
NA36
:NA210LH
NA!37
:NA210LH
NA38
:NA210LH
NA39
:NA210LH
NA4
:NA210LH
4-322
SABZ,SAB1;
GAB,GABZ;
GABZ,GAB1;
GBAZ,GBA;
SNA3,GBA,A 1;
SNA6,GBA,A2;
SBA 1 ,FFl ASNA 1 ;
SBA 1,FF 1D,SNA 10;
SBAZ,B4,SNA 11;
SNA 1O,SNA 11 ,SNA 12;
SABl ,FF2A,SNA 13;
SABZ,A 1 ,SNA 14;
SNA 13,SNA 14,SNA 15;
SABl ,FF2B,SNA 16;
SABZ,A2,SNA 17;
SNA 16,SNA 17 ,SNA 18;
SABl ,FF2C,SNA 19;
SBAZ,Bl,SNA2;
SABZ,A3,SNA20;
SNA 19,5NA20,SNA21;
SAB1,FF2D,SNA22;
SABZ,A4,SNA23;
SNA22,SNA23,SNA24;
SBA 1,FF3A,SNA25;
SBAZ,B5,SNA26;
SNA25,SNA26,SNA27;
SBA 1 ,FF3B,SNA28;
SBAZ,B6,SNA29;
SNA 1 ,SNA2,SNA3;
SNA28.SNA29,SNA30;
SBA 1,FF3C,SNA31;
SBAZ,B7,SNA32;
SNA31,SNA32,SNA33;
SBA 1 ,FF3D,SNA34;
SBAZ,B8,SNA35;
SNA34,SNA35,SNA36;
SAB1,FF4A,SNA37;
SABZ,A5,SNA38;
SNA37,SNA38,SNA39;
SBA 1 ,FFl B,SNA4;
TEXAS . "
INSTRUMENTS
POST OFFICE
sox 655012
• DALLAs. TexAs 75265
SN54ASC651, SN54ASC652, SN74ASC651, SN74ASC652
8·BIT BIDIRECTIONAL UNIVERSAL TRANSCEIVER REGISTERS
HDL FILE (Continued)
STRUCTURE (Continued)
NA40
:NA210LH
NA41
:NA210LH
NA42
:NA210LH
NA43
:NA210LH
NA44
:NA210LH
NA45
:NA210LH
NA46
:NA210LH
NA47
:NA210LH
NA48
:NA210LH
NA5
:NA210LH
NA6
:NA210LH
NA7
:NA210LH
NA8
:NA210LH
NA9
:NA210LH
T01
:T0010LH
FF1
:R2405LH
FF2
:R2405LH
FF3
:R2405LH
FF4
:R2405LH
END S651LH
SAB1,FF4B,SNA40;
SABZ.A6,SNA41 ;
SNA40,SNA41,SNA42;
SAB1,FF4C,SNA43;
SABZ,A7,SNA44;
SNA43,SNA44,SNA45;
SAB1,FF4D,SNA46;
SABZ,A8,SNA47;
SNA46,SNA47,SNA48;
SBAZ,B2,SNA5;
SNA4,SNA5,SNA6;
SBA 1;FF1 C,SNA7;
SBAZ,B3,SNA8;
SNA7,SNA8,SNA9;
DUM,ST01:
ST01 ,B1 ,B2,B3,B4,CBA,FF1A,FF1 B,FF1 C,FF1 D;
ST01 ,A 1 ,A2.A3,A4,CAB,FF2A,FF2B,FF2C,FF2D;
STO 1,B5,B6,B7 ,B8,CBA,FF3A,FF3B,FF3C,FF3D;
STO 1,A5,A6,A 7 ,A8,CAB,FF4A,FF4B,FF4C,FF4D;
II
...
II)
BLOCK S652LH;
GBAZ
@INPUT;
GAB
@INPUT;
SBA
@INPUT;
SAB
@INPUT;
CBA
@INPUT;
CAB
@INPUT;
A1
@INOUT;
A2
@INOUT;
A3
@INOUT;
A4
@INOUT
A5
@INOUT;
A6
@INOUT;
A7
@INOUT;
A8
@INOUT;
B1
@INOUT;
B2
@INOUT;
B3
@INOUT;B4
@INOUT;
B5
@INOUT;
B6
@INOUT;
B7
@INOUT;
B8
@INOUT;
CD
CD
.c
en
...caca
C
~
TEXAS
-INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-323
SN54ASC651, SN54ASC652, SN74ASC651, SN74ASC652
8·BIT BIDIRECTIONAL UNIVERSAL TRANSCEIVER REGISTERS
HDL FILE (Continued)
II
...0
Q)
Q)
en
::r
CD
CD
...
CIl
4-324
STRUCTURE (Continued)
INVl
:IV140LH
INV10
:IV222LH
INVll
:IV222LH
INV12
:IVll0LH
INV13
:IV110LH
INV14
:IVllOLH
INV15
:IVllOLH
INV16
:IV110LH
INV17
:IV110LH
INV18
:IVllOLH
INV19
:IVllOLH
INV2
:IV140LH
INV20
:IV222LH
INV21
:IV222LH
INV22
:IV222LH
INV23
:IV222LH
INV24
:IV222LH
INV25
:IV222LH
INV26
:IV222LH
INV27
:IV222LH
INV28
:IVllOLH
INV29
:IV110LH
INV3
:IV140LH
INV30
:IV110LH
INV31
:IV110LH
INV32
:IV110LH
INV33
:IV110LH
INV34
:IV110LH
INV35
:IV110LH
INV36
:IV222LH
INV37
:IV222LH
INV38
:IV222LH
INV39
:IV222LH
INV4
:IV140LH
INV5
:IVllOLH
INV6
:IV140LH
INV7
:IV140LH
INV8
:IV222LH
INV9
:IV222LH
NAl
:NA210LH
NA10
:NA210LH
NAll
:NA210LH
NA12
:NA210LH
NA13
:NA210LH
NA14
:NA210LH
NA15
:NA210LH
NA16
:NA210LH
NA17
:NA210LH
NA18
:NA210LH
NA19
:NA210LH
SBA,SBAl;
SNA9,GBA,A3;
SNA 12,GBA,A4;
B1,SIV12;
B2,SIV13;
B3,SIV14;
B4,SIV15;
Al,SIV16;
A2,SIV17;
A3,SIV18;
A4,SIV19;
SBAl,SBA1;
SNA 15,GABl ,Bl;
SNA 18,GABl ,B2;
SNA21 ,GABl ,B3;
SNA24,GAB1,B4;
SNA27,.GBA,A5;
SNA30,GBA,A6;
SNA33,GBA,A7;
SNA36,GBA,A8;
B5,SIV28;
B6,SIV29;
SAB,SABl;
B7,SIV30;
B8,SIV31;
A5,SIV32;
A6,SIV33;
A7,SIV34;
A8,SIV35;
SNA39,GAB1,B5;
SNA42,GAB1,B6;
SNA45,GAB1,B7;
SNA48,GAB1,88;
SABl,SABl ;
GAB,GABl;
GABl,GAB1;
GBAl,GBA;
SNA3,GBA,A 1;
SNA6,GBA,A2;
SBA 1 ,FFl Al,SNA 1;
SBA 1,FFl Dl,SNA 10;
SBAl,SIV15,SNA 11;
SNA 1O,SNA 11 ,SNA 12;
SABl ,FF2Al,SNA 13;
SABl,SIV16,SNA 14;
SNA 13,SNA 14,SNA 15;
SABl ,FF2Bl,SNA 16;
SABl,SIV17,SNA17;
SNA 16,SNA 17 ,SNA 18;
SABl ,FF2CZ,SNA 19;
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC651, SN54ASC652, SN74ASC651, SN74ASC652
8·BIT BIDIRECTIONAL UNIVERSAL TRANSCEIVER REGISTERS
HDL FILE (Continued)
STRUCTURE (Continued)
NA2
:NA210LH
NA20
:NA210LH
NA21
:NA210LH
NA22
:NA210LH
NA23
:NA210LH
NA24
:NA210LH
NA25
:NA210LH
NA2B
:NA210LH
NA27
:NA210LH
NA28
:NA210LH
NA29
:NA210LH
NA3
:NA210LH
NA30
:NA210LH
NA3l
:NA2l0LH
NA32
:NA210LH
NA33
:NA210LH
NA34
:NA2l0LH
NA35
:NA2l0LH
NA3B
:NA2l0LH
NA37
:NA2l0LH
NA38
:NA210LH
NA39
:NA210LH
NA4
:NA2l0LH
NA40
:NA210LH
NA4l
:NA210LH
NA42
:NA210LH
NA43
:NA2l0LH
NA44
:NA2l0LH
NA45
:NA210LH
NA4B
:NA210LH
NA47
:NA210LH
NA48
:NA210LH
NA5
:NA2l0LH
NAB
:NA2l0LH
NA7
:NA2l0LH
NA8
:NA2l0LH
NA9
:NA2l0LH
TOl
:TOO10LH
FFl
:R240BLH
FF2
:R240BLH
FF3
:R240BLH
FF4
:R240BLH
SBAZ,SIV12,SNA2;
SABZ,SIV18,SNA20;
SNA 19,5NA20,SNA21;
SAB1,FF2DZ,SNA22;
SABZ,SIV19,SNA23;
SNA22,SNA23,SNA24;
SBA l,FF3AZ,SNA25;
SBAZ,SIV28,SNA2B;
SNA25,SNA2B,SNA27;
SBA l,FF3BZ,SNA28;
SBAZ,SIV29,SNA29;
SNA l,SNA2,SNA3;
SNA28,SNA29,SNA30;
SBA l,FF3CZ,SNA3l;
SBAZ,SIV30,SNA32;
SNA31,SNA32,SNA33;
SBA 1 ,FF3DZ,SNA34;
SBAZ,SIV31,SNA35;
SNA34,SNA35,SNA3B;
SAB1,FF4AZ,SNA37;
SABZ,SIV32,SNA38;
SNA37,SNA38,SNA39;
SBA l,FFl BZ,SNA4;
SAB1,FF4BZ,SNA40;
SABZ,SIV33,SNA4l ;
SNA40,SNA41,SNA42;
SAB1,FF4CZ,SNA43;
SABZ,SIV34,SNA44;
SNA43,SNA44,SNA45;
SAB1,FF4DZ,SNA4B;
SABZ,SIV35,SNA47 ;
SNA4B,SNA4 7 ,SNA48;
SBAZ,SIV13,SNA5;
SNA4,SNA5,SNAB;
SBA l,FFl CZ,SNA7;
SBAZ,SIV14,SNA8;
SNA7,SNA8,SNA9;
DUM,ST01:
ST01,B1,B2,B3,B4,CBA,DUM,FF1AZ,DUM,FF1 BZ,DUM,FFl CZ,
DUM,FF1DZ;
ST01,A l.A2,A3,A4,CAB,DUM,FF2AZ,DUM,FF2BZ,DUM,FF2CZ,
DUM,FF2DZ;
STO 1,B5,BB,B7 ,B8,CBA,DUM,FF3AZ, DUM, FF3BZ,DUM,FF3CZ,
DUM,FF3DZ;
STO 1,A5,AB,A 7 ,A8 ,CAB, DU M, FF4AZ, DU M, FF4BZ, DU M, FF4CZ,
DUM,FF4DZ;
•
END SB52LH
TEXAS , . ,
INSTRUMENTS
POST OFFICE
dox
655012 • DALLAS. TeXAS 752:66
4·325
II
c
....
C\)
C\)
(J)
::r-
CD
CD
....
tn
·4-326
SN54ASC669, SN74ASC669
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH LOOK-AHEAD
02939, AUGUST 1986
SystemCell™
2-llm SOFTWARE MACRO CELL
•
Fully Synchronous Operation for Counting
and Programming
•
Internal look-Ahead for Fast Counting
•
Carry Output for n-Bit Cascading
•
Fully Independent Clock Circuit
logic symbol t
CTRDIV16
•
LOADZ
U_DZ
RCOZ
ENTZ
Buffered Outputs
ENPZ
2,3,5,6 + IC7
CLK
description
The SN54ASC669 and SN74ASC669 are
standard-cell software macros implementing
synchronous 4-bit up-down binary counter
elements. The four-bit configuration provides the
custom IC desi9ner a fully designed bidirectional
counter to embed in ASICs in its most efficient
form, and the 4-bit length simplifies construction
of large counters. The' ASC669 implements a
count sequence identical with that performed by
packaged 'lS669 counters.
2,4,5,6A
[1]
QA
B
[2]
OB
C
[4]
oc
0
[8)
00
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
These synchronous presettable counters feature an internal carry look-ahead for cascading in high-speed
counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously
so that the outputs change coincidentally with each other when so instructed by the count-enable inputs
and internal gating. This mode of operation helps eliminate the output counting spikes that are normally
associated with asynchronous (ripple-clock) counters. A buffered clock input triggers the four master-slave
flip-flops on the rising (positive-going) edge of the clock waveform. The 'ASC669 is implemented with
the standard cell functions indicated. The HDl netlist label for this software macro is shown on the last
line of the following table:
RELATIVE
CELL NAME
CELL AREA
NO. USED
TO NA210LH
AN320LH
TOTAL
TOTAL
RELATIVE
Cpd t
SN54ASC'
CELL AREA
(pF)
(nA)
(nA)
1.06
221
13.3
2
MAXIMUM ICC
SN74ASC'
2
1
A0221LH
2.7
4
10.8
2.36
896
53.6
IV110LH
0.75
7
5.25
3.08
735
44.24
IV120LH
1
3
3
2.4
393
23.55
NA210LH
1
6
6
3.06
786
47.04
97.8
NA310LH
1.25
12.5
5
1630
NA410LH
1.5
2
3
1
374
11.4
NA510LH
1.75
2
3.5
1.04
426
25.6
R2406LH
26.25
1
26.25
11.7
2931
176
T0010LH
1.5
1
1.5
177
10.6
37
73.75
8569
504
TOTALS
10
II
30.7
Label: S669LH D,C,B,A,CLK,U_DZ,ENPZ,ENTZ,LOADZ,QD,QC,Q8,QA,RCOZ;
tThe equivalent power dissipation capacitance does not include interconnect capacitance.
PRODUCTION DATA documents contain information
currant 8S of publication date. Products conform to
specifications per the terms of Texas Instruments
:::~::i~8{::,~I~ ~=:~i:; li~a:::~~~~ not
Copyright @ 1986, Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-327
SN54ASC669. SN74ASC669
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH LOOK-AHEAD
description (continued)
These counters are fully programmable; that is, they may be preset to any number between 0 and 15.
The load input circuitry allows loading with the carry-enable output of cascaded counters. As loading is
synchronous, setting up a low level at the load input disables the counter and causes the output to agree
with the data inputs after the next clock pulse.
The carry look-ahead circuitry provides for cascading counters in n-bit synchronous applications without
additional gating. Instrumental in achieving this are two count-enable inputs and a ripple carry output. Both
count-enable inputs (ENPZ and ENTZ) must be low to count. ENPZ enables the local 4-bits and the ENTZ
is fed forward to globally extend the enable/disable of previous/next 4-bit cascaded counters. The ripplecarry out RCOZ, when locally and globally enabled, will output a low-level pulse that is used to enable
successive stages. Transitions at the ENPZ and ENTZ inputs are allowed regardless of the level of the
clock input.
These counters feature a fully independent clock circuit. Changes at control inputs (ENPZ, ENTZ, LOADZ,
U _ DZ) that will modify the operating mode have no effect until clocking occurs. The function of the counter
(whether enable, disable, load, or count) will be dictated solely by the conditions meeting"the setup and
hold times.
II
The SN54ASC669 is characterized for operation over the full military temperature range of
125°C. The SN74ASC669 is characterized for operation from - 40°C to 85 °C.
typical load, count, and inhibit sequences
LOADZ~-------------------------------------
c
Q)
...
A~~=
Q)
DATA
(/)
::r
INPUTS
IT!
en
<
2
OND
6
~
e
NA3
A ~x
A NA310lx
:
L!J
r-cl
o
TOO10lx
yee ~
~
~I INY13
NA2
-=-1~B
",V
B INA8
e
NA7
L
~
B
C
AYe
'8(JJ
~ ~(JJ
pV
UAI:.
HA6
+--==-_-2B-I
1Y110lx
'll_
f:iz
~ c:~
B
~A0221LX
"-'
-l
~;;Or;;1
IBl
Y
3
A NA310lx
B
y
e
HA4
" V
A '':=-x
I
1NV7
I ~A0221LX
INYB
o
~
~'OlXV
A IVl10lx
J-...V
;
~eNAI
I
~
1NV6
c.
iii"
IQ
P~---'
:::c-
,...en
QZ
Q~
=-:~
.::ra
-1>0
W
'"
(l)
Data Sheets
II
::raen
:en
men
::raen
CI ea
SN54ASC669. SN74ASC669
SYNCHRONOUS 4·BIT UP/DOWN BINARY COUNTERS WITH LOOK·AHEAD
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements
Specific timing data regarding pulse duration, setup time, and hold time models are incorporated in most
engineering workstation libraries. These models are for the clocked ceils embedded in the software macros.
Evaluations of the timing requirements, ate made durihg pre-layout s.itnulation, produce workstation output
used to identify and resolve each specific timing need.
electrical characteristics
PARAMETER
VCC = 5 V,
ICC Supply current
VCC - 4.5 V to 5.5 V. VI - Vce or O.
TA = MIN to MAX
Input capacitance
I
CLK,LOADZ,
and U ~ DZ
I All
TA = 25°C
others
Equivalent power
Cpd dissipation capacitance t
VCC = 5 V.
TYP
2.2
MAX
tr = tf = 3 ns.
TA = 25°C
504
0.24
0.24
0.12
0.12
30.7
30.7
UNIT
v
8569
TA = 25°C
VCC = 5 V,
SN74ASC669
MAX
TYP
2.2
VT Input threshold voltage
Ci
II
SN54ASC669
TEST CONDITIONS
nA
pF
pF
t The equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Note 11
PARAMETERt
tpd
FROM
(INPUT)
TO
(OUTPUT)
eLK
ReOZ
tpd
CLK
On
tpd
ENTZ
U_DZ
RCOZ
Any
<;In
RCOZ
tpd
Atpd
Atpd
Any
TEST
CONDITIONS
CL
SN54ASC669
MIN
SN74ASC669
TYP*
MAX
TYP*
MAX
10
24.2
10
22
5
10.4
5
9.4
3
5.9
3
=0
MIN
6
14.2
6
5.3
13
0.2
0.9
2.4
0.3
0.9
2.1
0.5
1.8
5.8
0.5
1.8
5
RCOZ
tprapagatian delay times are measured from the 44% point of VI to the 44% point of Vo with tr
= tf = 3 ns (10%
UNIT
ns
ns
ns/pF
and 90%).
tpd '" propagation delay time, low-to-high or high-to-low output
Atpd '" change in tpd with load capacitance
*Typical values are at Vec = 5 V, TA = 25°C.
NOTE 1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
4-330
TEXAS . "
INSTRUMENTS
POST OFFice BOX 65501~· • DALLAs. TEXAS 75266
SN54ASC669, SN74ASC669
SYNCHRONOUS 4·BIT UP/DOWN BINARY COUNTERS WITH LOOK·AHEAD
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
HOL FILE
BLOCK S669LH;
D
@INPUT;
C
@INPUT;
B
@INPUT;
A
@INPUT;
eLK
@INPUT;
U_DZ
@INPUT;
ENPZ
@INPUT;
ENTZ
@INPUT;
LOADZ
@INPUT;
QD
@OUTPUT;
QC
@OUTPUT;
QB
@OUTPUT;
QA
@OUTPUT;
RCOZ
@OUTPUT;
STRUCTURE
AN1
A01Z
A02
AQ3
A04
INV1
INV10
INV11
INV12
INV13
INV2
INV5
INV6
INV7
INV8
INV9
NA1
NA10
NA11
NA12
NA13
NA14
NA15
NA16
NA17
II
...
CI)
CI)
CI)
.c
:AN320LH
:A0221LH
:A0221LH
:A0221LH
:A0221LH
:IV110LH
:IN110LH
:IV110LH
:INV120LH
:T0010LH
:IV110LH
:IV120LH
:IV120LH
:IV110LH
:IV110LH
:IV110LH
:NA310LH
:NA310LH
:NA310LH
:NA410LH
:NA210LH
:NA310LH
:NA210LH
:NA410LH
:NA310L.H
LOADZ,INV20,INV1 0,AN1 0;
QA,INV120,INV80,FFAQZ,A010;
QB,INV120,INV90,FFBQZ,A020;
QC,INV20 ,INV1 00,FFCQZ,A030;
QD,INV120,INV110,FFDQZ,A040;
ENTZ,INV10;
INV120,INV100;
INV120,INV110;
U_DZ,INV120;
DUM,CLRZ;
ENPZ,INV20;
LOADZ,INV50;
INV5Q,INV60;
AN10,INV70;
INV120,INV80;
INV120,INV90;
QA,INV70,INV60,NA 10;
QC,NA 11 0,INV60,NA 100;
AN1 0,A020,A01 O,NA 110;
A01 0,A020,AN1 O,FFCQZ,NA 120;
INV50,C,NA 130;
NA100,NA130,NA120,NA140;
INV50,D,NA 150;
ANl 0,A01 0,A020,A030,NA 160;
QD,NA 160,INV60,NA 170;
TEXAS.
INSTRUMENTS
POST OFfICE BOX 655012· DALLAS, TEXAS 75765
en
...coco
C
4-331
•
SN54ASC669, SN74ASC669
SYNCHRONOUS 4·BIT UP/DOWN BINARY COUNTERS WITH LOOK·AHEAD
HDL FILE (Continued)
STRUCTURE (Continued)
NA19
:NA310LH
NA2
:NA210LH
NA20
:NA510LH
NA21
:NA510LH
NA3
:NA310LH
NA4
:NA310LH
NA5
:NA210LH
NA6
:NA310LH
NA7
:NA310LH
:NA210LH
NA8
:NA210LH
NA9
FF14
:R2406ZLH
NA 170,NA 150,NA200,NA 190;
AN10,FFAQZ,NA20;
ANl O,AOl 0,A020,A030,FFDQZ,NA200;
AOl 0,A020,A030A040,INVl O,RCOZ;
QB,NA50,INV60,NA30;
NA 1 0,NA80,NA20,NA40;
ANl OAOl 0,NA50;
ANl O,AOl 0,FFBQZ,NA60;
NA30,NA90,NA60,NA70;
INV50A,NA80;
INV50,B,NA90;
CLRZ,NA40,NA70,NA 140,NA 190,CLK,QA,FFAQZ,QB,FFBQZ,
QC,FFCQZ,QD,FFDQZ;
END S669LH
count definition
These counters are bidirectional with respect to count operations and the relationship for counting up or
down is defined by the U_DZ input. Unidirectional counters are available in software macros or can be
contructed using the' ASC2405 through' ASC2407 4-bit predesigned registers. Additional single bits can
be achieved with predesigned flip-flops offered in TI's standard cell family.
designing for testability
Designers employing storage or bistable elements, especially long counters (ripple or synchronous), should
consider testability of the design in its final form. The need to preset or clear, and read intermediate stages
of these elements, should be assessed throughout the development of custom logic circuits with these
considerations extended to the end equipment application with respect to maintainability. Simple actions
on the part of the ASIC designer can result in considerable costs savings as the expense of IC testing,
system testing, and system maintenance can be reduced signi·ficantly.
power-up-clear/preset
Standard cell storage elements containing the capability to be asynchronously either preset or cleared may
be connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Access to the clear inputs from other system signals in conjunction with the power-up clear can be facilitated
with an AND gate.
4-332
".!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC686, SN74ASC686
8·BIT MAGNITUDE COMPARATORS
02939, AUGUST 1986
SystemCell""
2·",m SOFTWARE MACRO CELL
•
Performs Magnitude Comparison of Binary,
BCD, and Monotonic Codes
•
Weighted Cascaded Inputs Accomodate
Both Serial and Parallel Expansion
•
Dependable Texas Instruments Quality and
Reliability
logic symbol t
COMP
G1Z
G2Z
PO
Pl
P2
description
The SN54ASC686 and SN74ASC686 are
standard-cell software macros implementing
8-bit expandable magnitude comparators, The
8-bit configuration provides the custom IC
designer a magnitude comparator to embed in
ASICs in its most efficient form, and the 8 bit
width simplifies construction of wider
comparators, The 'ASC686 implements a
comparison scheme identical with that
performed by packaged 'HC686 and 'LS686
comparators,
P3
P4
P
P5
1P-O
p~--
PEOOZ
2P>0
p~--
PGT02
ps
P7
7
00
0
01
02
03
a
04
05
as
07
7
These 8-bit magnitude comparators perform
comparison of straight binary and straight BCD
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
(8-4-2-1), codes, Two fully decoded decisions,
lEe Publication 617-12.
P>Q or P = Q, about two eight-bit words (P,Q)
are made and are externally available at two
outputs that can be decoded with a NAND gate
to provide the P < Q decision, These devices are fully expandable to any number of bits, Words of greater
length may be compared by connecting comparators in cascade, ThePEQQZ and PGTQZ outputs of a
stage handling less-significant bits are connected to the corresponding G 1Z and G2Z inputs of the next
stage handling more-significant bits, The' ASC686 is implemented with the standard cell functions indicated,
The HDL netlist label for this software macro is shown on the last line of the following table:
RELATIVE
CELL NAME
CELL AREA
TOTAL
TOTAL
RELATIVE
CELL AREA
Cpd*
(pF)
SN54ASC'
(nA)
SN74ASC'
(nA)
4
7
6
12.25
3.6
7.42
776
1547
46.4
93.1
NO. USED
TO NA210LH
fI)
G)
G)
.c
en
...
CU
CU
C
MAXIMUM ICC
AN210LH
AN310LH
1.5
1.75
AN410LH
2
6
12
7.08
1536
91.8
EX210LH
2
8
16
8.96
1784
107.2
IV110LH
0.75
9.75
5.72
1365
82.16
IV120LH
1
5
5
4
655
39.25
NA210LH
NA310LH
1
1.25
4
4
524
31.36
3
3.75
2.04
1.5
489
29.34
NA410LH
1.5
3
4.5
1.5
561
33.6
NA420LH
2.5
1
2.5
0.96
312
18.7
N0220LH
1.5
1
1.5
0.52
185
11.1
13
II...
43.3
9734
585
TOTALS
55
77.25
Label: S686LH PO,Pl,P2,P3,P4,P5,P6,P7 ,00,01,02,03,04,05,06,07 ,Gl Z,G2Z, PEOOZ,PGTOZ;
tOoes not include interconnect capacitance.
Copyright © 1986, Texas Instruments Incorporated
PRODUCTION DATA documants contain information
current as of publication data. Products conform to
specifications per the terms of Texas Instruments
:~=~;ai~:1~1e ~:~:~ti:fn :.~o:.e:;;~~~s
not
TEXAS " "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-333
SN54ASC686, SN74ASC686
8-BIT MAGNITUDE COMPARATORS
The SN54ASC688 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC688 is characterized for operation from - 40°C to 85 DC.
FUNCTION TABLE
INPUTS
DATA
OUTPUTS*
ENABLESt
PEQOZ
PGTOZ
H
G1Z
G2Z
P=Q
L
X
L
P>Q
X
L
H
L
PQ
x
H
H
H
X
H
H
H
H
P.Q
t G1Z enables PEQQZ, and G2Z enables PGTQZ.
*The
'i'<'Q function can be generated by
applying the PEQQZ and PGTQZ outputs to a
2-input NAND gate .
•
...o
C»
C»
o:::r
...en
(I)
(I)
4-334
TEXAS . . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC686, SN74ASC686
8-BIT MAGNITUDE COMPARATORS
logic diagram
P7
Q7
PO
Q8
PO
P4
POQQZ
Q4
P,
'"
Q2
Q'
PO
ao
II...
G'Z
II)
GZZ
Q)
Q)
.s::
en
...
CtI
CtI
C
PGTaz
'1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-335
SN54ASC686. SN74ASC686
8·BIT MAGNITUDE COMPARATORS.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
VT Input threshold voltage
ICC Supply current
TEST CONDITIONS
Input capacitance
I G2Z
t The
TYP
MAX
2.2
TA = 25°C
Vee = 5 V,
tr = tf = 3 ns,
TA = 25°C
UNIT
V
585
0.12
Vee = 5 V,
MAX
2.2
9734
IAnyPorQ
Equivalent power
Cpd dissipation capacitance t
SN74ASC686
TYP
Vee = 5 V,
TA = 25°C
Vee = 4.5 V to 5.5 V, VI - Vee or 0,
TA = MIN to MAX
I GIZ
ei
SN64ASC686
nA
0.12
0.24
0.24
0.34
0.34
43.3
43.3
pF
pF
equivalent power dissipation capacitance does not include interconnect capacitance.
switching characteristics over recommended ranges of supply yoltage and operating free-air temperature
lunless otherwise noted) Isee Note 1)
II
C
....
DI
DI
t/)
::T
CD
....CDen
*
FROM
(INPUT)
TO
TEST
(OUTPUTI
CONDITIONS
tpd
Pn, Qn
Any
tpd
G1Z,G2Z
Any
Any
Any
PARAMETER
.1tpd
SN54ASC686
TYP§ MAX
MIN
9
20.6
7
15.4
0.8
2.3
eL = 0
0.3
SN74ASC686
TYP§
MAX
MIN
0.3
9
7
19.1
0.8
2
14.1
UNIT
ns
nsipF
O
x
P:_ _ _- - - - . J
cD)
at
G,Z
absolute maximum ratings and recommended operating conditiohs
See Table 1 in Section 2.
t/)
:r
g
r+
electrical characteristics
en
PARAMETER
VT Input threshold voltage
lee Supply current
ej
I G1Z
Input capacitance
I Any P or Q
Equivalent power
Cpd dissipation capacitance t
TEST CONDITIONS
SN54ASC688
SN74ASC688
TYP
TYP
TA = 25°e
Vee = 5 V.
Vee - 4.5 V to 5.5 V. VI - Vee or O.
TA = MIN to MAX
Vee
=
5 V.
Vee = 5 V.
TA = 25°e
TA
tr
=
25°e
= tf =
3 ns.
2.2
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
MAX
2.2
3677
0.12
0.22
0.22
15.94
15.94
UNIT
V
221
0.12
t The equivalent power dissipation capacitance does not include interconnect capacitance.
4·340
MAX
nA
pF
pF
SN54ASC688. SN74ASC688
8-81T IDENTITY COMPARATORS
switching characteristics over recommended ranges of operating free-air temperature and supply voltage
(unless otherwise noted) (see Note 1)
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
tpd
Pn, Qn
PEQQZ
tpd
G1Z
PEQQZ
~tpd
Any
PEQQZ
PARAMETERt
eL
SN54ASC688
MIN
SN74ASC688
TYP*
MAX
TYP*
MAX
7.5
13.6
7.5
12.3
3
4.7
3
4.4
0.7
2.3
0.7
2
=0
0.3
MIN
0.3
UNIT
ns
ns
ns/pF
tPropagation delay times are. measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tpd 5 propagation delay time, low-ta-high or high-ta-Iow output
.6.tpd == change in tpd with capacitance
*Typical values are at Vee = 5 V, TA = 25°e.
NOTE 1: These switching characteristics are simulations of the software macro cell using interconnect capacitance values for an array
design having 2,000 gates. Post-layout simulation uses actual interconnect capacitance values.
DESIGN CONSIDERATIONS
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
The HDL for this software macro is included as a part of the library supplied for supported engineering.
workstations so that a single label can be developed to apply the macro as needed. The following printout
of the HDL block definition is furnished for reference.
...
(/)
HDL FILE
CD
CD
.c
en
BLOCK S688LH;
PO
@INPUT;
P1
@INPUT;
P2
@INPUT;
P3
@INPUT;
P4
@INPUT;
P5
@INPUT;
P6
@INPUT;
P7
@INPUT;
00
@INPUT;
01
@INPUT;
02
@INPUT;
03
@INPUT;
04
@INPUT;
05
@INPUT;
06
@INPUT;
07
@INPUT;
G1Z
@INPUT;
PEOQZ
@OUTPUT;
...co
CO
C
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76266
4-341
SN54ASC688, SN74ASC688
8·BIT IDENTITY COMPARATORS
STRUCTURE
AN1
AN2
AN3
EX1
EX2
EX3
EX4
EX5
EX6
EX7
EX8
INV1
INV2
INV3
INV4
INV5
INV6
INV7
INV8
INV9
NA1
END S688LH;
C
:AN310LH
:AN310LH
:AN210LH
:EX210LH
:EX210LH
:EX210LH
:EX210LH
:EX210LH
:EX210LH
:EX210LH
:EX210LH
:IV110LH
:IV110LH
:IV110LH
:IV110LH
:IV110LH
:IV110LH
:IV110LH
:IV110LH
:IV110LH
:NA420LH
INV1 0,INV20,INV30,AN1 0;
INV40,INV50,INV60,AN20;
INV70,INV80,AN30;
P7,Q7,EX10;
P6,Q6,EX20;
P5,Q5,EX30;
P4,Q4,EX40;
P3,Q3,EX50;
P2,Q2,EX60;
P1 ,Q1 ,EX70;
PO,QO,EX80;
EX10,INV1O;
EX20,INV20;
EX30,INV30;
EX40,INV40;
EX50,INV50;
EX60,INV60;
EX70,INV70;
EX80,INV80;
G1Z,INV90;
AN10,AN20,AN30,INV90,PEQQZ;
I»
r+
I»
en
::r
CD
CD
r+
en
4·342
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TEXAS 75265
PRODUCT
PREVIEW
SN54ASC888. SN74ASC888
8·BIT PROCESSOR SLICES
D2939, AUGUST 1986
SystemCell™ COMPATIBLE MegaModule™
•
•
•
•
•
•
•
•
•
•
•
Parallel 8·Bit ALU with Expansion Nodes
•
Full Carry Look Ahead Support
13 Arithmetic and Logic Functions
•
8 Conditional Shifts (Single and Double
Length)
Sign. Carry Out. Overflow. and Zero-Detect
Status Capabilities
•
Excess-3 BCD Arithmetic
9 Instructions that Manipulate Bytes
•
ALU Bypass Path Increases Speeds of
Multiply. Divide. and Normalize Instructions
and Provides New Instructions such as Bit
Set. Bit Reset. Bit Test. Byte Subtract. Byte
Add. and Byte Logical
•
3-0perand Register Files Allow an Operation
and a Move Instruction to be Combined
•
Bit and Byte Masks are Shared with
Register Address Fields to Minimize Control
Store Word Width
•
3 Data Input/Output Ports Maximize Data
Throughput
4 Instructions that Manipulate Bits
Add and Subtract Immediate Instructions
Absolute Value Instruction
Signed Magnitude to/from Two's
Complement Conversion
Single· and Double-LlIngth Normalize
Select Functions
Signed and Unsigned Divides with Overflow
Detection; Input Does Not Need to be
Prescaled
•
Signed. Mixed. and Unsigned Multiplies
•
Three-Operand. 16-Word Register File
•
description
These 8-bit Advanced CMOS SystemCeliN compatible standard cells implement high-performance digital
computer or controller data-paths, An architecture and instruction set has been chosen that supports a
fast system clock. a narrow micro-code word width. and a high system throughput. The powerful instruction
set allows high-speed system architecture to be implemented and also allows an existing system's
performance to be upgraded while protecting software investments, These processors are designed to
be cascadable. in increments of eight bits. to any word width of 16 bits or greater.
The SN54ASC888 will be characterized for operation over the full military temperature range of - 55°C
to 125°C, The SN74ASC888 will be characterized for operation from ~40°C to 85°C.
PRODUCT PREVIEW documents contain information
on products in the formative Dr design p'hasa of
development. Charecteristic deta end other
~:.a:~i::t~:1rr::t ~-::if.=::I~r T3i::~~:::~~:S~
pnNIucts without notice.
Copyright © '986, Texas Instruments Incorporated.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-343
SN54ASC888, SN74ASC888
8-BIT PROCESSOR SLICES
node descriptions
AO
I/O
I
A1
I
A2
I
A3
I
BO
B1
I
B2
I
B3
I
CO
I
NODE NAME
•
C1
I
C2
I
Register file A port read address select IlSB
= 0)
Register file B port read address select ILSB
= 0)
Register file address select
C3
I
ClK
I
Clocks aU synchronous registers on positive edge
Cn
I
AlU carry input
CNPl8
0
AlU ripple carry output
DAO
I/O
DA1
110
DA2
110
DA3
110
DA4
110
DA5
110
DA6
110
DA7
110
DBO
110
DBl
110
DB2
110
DB3
110
DB4
110
DB5
110
DB6
110
DB7
110
EAZ
I
EBO
I
EBl
I
GZ_N
a
10
I
11
I
12
I
13
I
14
)5
I
16
I
17
I
lSC
MSC
OEAZ
4-344
I
DESCRIPTION
A port data bus. Outputs registe, data if EAZ is low, or inputs data if EAZ is high.
B port data bus. Outputs register data if OEBZ is low, or input data if
O~BZ
is high.
AlU input operand select. High state selects DA bus, and low state selects register file.
ALU input operand select. EBO and EB 1 select the source of data that the S multiplexer provides for the S bus.
Independent control of the DB bus and data-path selection allows the user to isolate the DB bus while the AlU
continues to process data.
ALU generate/negative result for most significant 8-bit slice, active low
Instruction input
)
,
I
Package position inputs
I
DA bus enable, active low
OEBZ
I
DB bus enable, active low
OEYZ
I
Y bus output enable, active low
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC888. SN74ASC888
8·BIT PROCESSOR SLICES
node descriptions (continued)
NODE NAME
SI07Z
1/0
0
110
OI07Z
110
OIOOZ
SELY
110
110
I
SSF
110
WEZ
I
YO
110
I/O
110
PZ_OVR
SIOOZ
Yl
Y2
Y3
110
Y4
110
Y5
Y7
110
110
110
ZERO
110
Y6
DESCRIPTION
AlU propagatelinstruction overflow for most significant a-bit slice, active low
Bidirectional shift pin, active low
Y bus select, active high
Expandable shift function. Used to transfer information between 8-bit slices during special instruction execution
in expanded (16-bit, 32-bitl systems
Register file (RF) write enable. Data is written into RF when WEZ is low and a low-ta-high clock transition occurs.
RF write is inhibited when WEZ is high.
Y port data bus. Outputs instruction results if OEYZ is low or input data register file if OEYZ is high.
ALU shifter zero detection, open drain. Input during certain special instructions
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
4-345
SN54ASC888, SN74ASC888
8·BlT PROCESSO~ SLICES
functional block diagram
4
C3-CO
.16 X 8
WEZ
REGISTER FILE
4
4
A3-AO
CK
83-80
OE8Z
8
8
DA7-DAO
DB7-DBO
OEAZ
EBO
EBl
PN_OVR---'-
LCS
MSCD-SSFC--
~
CD
CD
...
(I)
8
8
17-10
C>--'-
OEVZ
SELV
V7-VO
For additional detailed information refer to the SN54AS888 and the SN74AS888 data sheet, SDBS001B, and the Bit-Slice Processor
User's Guide, SDBUOOl A.
4-346
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
PRODUCT
PREVIEW
SN54ASC890, SN74ASC890
MICROSEOUENCERS
02939, AUGUST 1986
SystemCell™ COMPATIBLE MegaModule""
•
14 Bits Wide - Addresses Up to 16,384
Words of Microcode with One Megacell
•
Selects Address from One of Eight Sources
•
Independent Read Pointer for Aid in
Microcode Diagnostics
•
Supports Real-Time Interrupts
•
Two Independent Loop Counters
•
Supports 64 Powerful Instructions
•
Dependable Texas Instruments Quality and
Reliability
description
node descriptions
NODE NAME
1/0
RAOEZ
I
ORA6-0RAO
I/O
Seven lSBs of the A direct data 110 port
MUX control for the source to DRA. Low
OSEl
I
MUX2-MUXO
I
MUX control for Y output bus
RC2-RCO
I
Register/counter controls
S2-S0
I
Stack control
CCZ
I
Condition code
ClK
I
Clock
ZERO
0
0
Stack overflow. underflow/read efror flag
I/O
Seven lSBs of the B direct data I/O port
STKWRN/RER
ORB6-0RBO
The SN54ASC890 and SN74ASC890 are
Advanced CMOS standard cell microseqencers
supporting traditional bit-slice data-path
implementations.
FUNCTION
Enables ORA output. active low
selects RA. high selects stack,
Zero detect flag for register A and B
(0
=
lSBI
RBOEZ
I
DRB13-DRB7
I/O
Seven MSBs of the B direct data I/O port
INTZ
I
When low selects INT RT register to stack
Y13-YB
I/O
Six MSBs of bidirectional Y port
Y7
I/O
Seventh bit of bidirectional Y port
Enables ORB output. a,ctive low
The microsequencers select a 14-bit
YOEZ
Enables Y output bus, active low
I
microaddress from one of eight sources to
Seven LSBs of bidirectional Y port
provide the proper microinstruction sequence for
Y6-YO
I/O
(0 = lSBI
bit-slice processor megacells or other microcodeINC
I
Incrementer control
based data paths. These high-performance
DRA13-0RA7 I/O Seven MSBs of direct B data I/O port
megacells are capable of addressing 16,384
B3-BO16-way branch inputs
I
control store memory locations either
sequentially or via conditional branching
algorithms. This multiway branching capability,
coupled with a nine-word-deep FILa (first in, last out) stack, allows the microprogrammer to arrange his
code in blocks so that microprograms may be structured in the same fashion as such high-level languages
as ALGOL, Pascal, or Ada.
II
...
en
CD
CD
.c
tn
ca
ca
...
C
Both polled and real-time interrupt routines are supported by the' ASC890 to enhance system throughput
capability. Vectored interrupts may occur during any instruction, including PUSHes and POPs.
The SN54ASC890 will be characterized for operation over the full military temperature range of - 55°C
to 125 cC. The SN74ASC890 will be characterized for operation from - 40 cC to 85°C.
Copyright © 1986, Texas Instruments Incorporated
PRODUCT PREVIEW documant. contain information
on products in the formative or design phase of
development. Characteri.tic data and other
::::;~i:t:=:srr;:t dt~Si~8=::I!r T:i~::~~:~:~:~!:
products without AOticI.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-347
SN54ASC890, SN74ASC890
MICROSEQUENCERS
functional block diagram
RAOEZD----~
RBOEZ
OSELD---~
III
ZERO
STACK
POINTER
STACK
14x 9
C
C»
r+
C»
5TKWRN/RER
3
READ
POINTER
14
14
14
tn
N
T
RCZ-RCO
52-SO
CCZ
R
0
L
::T
3
3
MUX2-MUXO
~
e
fII
4
B3-BO
-------+-------------~
For additional detailed information refer to the SN54AS890 and SN74ASS90 data sheet, SOBS002, and the Bit-Slice Processor User's
Guide, SOBU001A.
4-348
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012. DALLAS. TEXAS 75265
SN54ASC2022, SN74ASC2022
5-INPUT POSITIVE-NAND GATES
D2939. AUGUST 1986
SystemCell™
2-J.tm INTERNAL STANDARD CELL
logic symbol
•
Choice of Two Performance Levels
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation Over Vce Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
FUNCTION TABLE
OUTPUT
INPUTS
positive logic equation
Y = A·B·C.D.E =
A+B+C+D+E
A
B
C
0
E
H
H
H
H
H
L
L
X
X
X
X
H
X
L
X
X
X
H
X
X
L
X
X
H
Y
X
X
X
L
X
H
X
X
X
X
L
H
description
The SN54ASC2022 and SN74ASC2022 are 5-input positive-NAND gate CMOS standard cells. The
standard-cell library contains two physical implementations providing the custom IC designer a choice
between two performance levels for optimizing designs. Each option is designated and called from the
engineering workstation input using the following cell names to develop labels for the design netlist:
NA510LH
NA520LH
CI)
CI)
en
NETLIST
TYPICAL
RELATIVE
HOL LABEL
DELAY
CELL AREA
CL - 1 pF
2.7 ns
TO NA210LH
Label: NA5nOLH A,B.e,O,E,Y;
U)
.s:
FEATURES
CELL NAME
II
....
....COCO
C
1.75
3
2.1 ns
The SN54ASC2022 is characterized for operation over the full military temperature range of - 55°C to
125°C, The SN74ASC2022 is characterized for operation from -40°C to 85°C,
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
VT
Input threshold voltage
I SN54Ase2022
I SN74Ase2022
NA510LH
TEST CONDITIONS
Vee
~
5 V,
TA
TYP
~
25°e
Supply current
ej
Input capacitance
Vee ~ 5 V,
TA ~ 25°e
Equivalent power
Vee - 5 V.
tr
dissipation capacitance
TA
epd
PRODUCTION DATA documonts contain information
currant as of publication date. Products conform to
spacifications per the terlls of Texas Instruments
:':~:=i~a{~:1~1i ~~::i::i:r lI~O::~:~~::-:S not
2.2
Vee ~ 4.5 V to 5.5 V, VI ~ Vee or 0,
lee
TA
~
~
MAX
NA520LH
TYP
213
MIN to MAX
tt' ~
3 ns,
25°e
UNIT
V
365
12.8
~
MAX
2.2
21.9
nA
0.12
0.25
pF
0.52
1.02
pF
Copyright © 1986, Texas Instruments Incorporated
TEXAS.
I~STRUMEN1S
POST OFFICE BOX 855012 • DALLAS, TeXAS 75266
4-349
SN54ASC2D22, SN74ASC2D22
5-INPUT POSITIVE-NAND GATES
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
lunlessotherwise noted)
NA510LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
J.tpLH
J.tPHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A thru E
A thru E
Y
CL
CL
Y
A thru E
Y
FROM
(INPUT)
TO
(OUTPUT)
=a
=
1 pF
SN54ASC2022
MIN
SN74ASC2022
MAX
MIN
0.8
TYP*
1.2
2.4
0.6
1.3
3.5
0.8
0.7
1.3
2.6
6.3
TYP*
1.2
MAX
2.2
1.3
3
1.4
2.6
5.8
1.6
2.7
9.2
1.7
2.7
0.5
1.4
4.3
0.5
1.4
8
3.9
0.9
2.2
5.8
1
2.2
5
UNIT
ns
ns
nsipF
NA520LH
PARAMETERt
tpLH
tpHL
tpLH
II
tpHL
J.tpLH
J.tpHL
A thru E
Y
A thru E
Y
A thru E
TEST
CONDITIONS
CL
CL
Y
=a
=
1 pF
SN54ASC2022
SN74ASC2022
TYP:I:
MAX
MIN
TYP*
MAX
MIN
0.7
1.2
2.4
0.7
1.2
2.2
0.6
1.2
2.9
0.6
1.2
2.6
3.5
1
1.9
3.9
1.1
1.9
1.1
2.2
5.7
1.2
2.2
5
0.3
0.7
1.6
0.3
0.7
1.4
0.4
1
2.8
0.5
1
2.4
t Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr
tPLH '" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high·to·low'level output
=
UNIT
ns
ns
nsipF
tf = 3 ns (10% and 90%1-
.6.tPLH ;;;;;: change in tPLH with load capacitance
J.tpHL '" change in tpHL with load capacitance
'Typical values are Vee = 5 V, TA = 25°C.
DESIGN CONSIDERATIONS
Refer to Section 7.
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
4-350
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC2024, SN74ASC2024
5-INPUT POSITIVE-AND GATES
D2939, AUGUST 1986
SystemCell™
2-/Lm INTERNAL STANDARD CEll
•
2.9 ns Typical Propagation Delay with 1-pF
Load
•
Specified for Operation Over Vee Range of
4.5 V to 5.5 V
•
Functional Operation Over Vee Range of
•
Dependable Texas Instruments Quality and
Reliability
logic symbol
2Vt06V
FUNCTION TABLE
OUTPUT
positive logic equation
Y = ABCDE = =A~+~B~+~C'--+~D=--+~E
INPUTS
A
B
C
D
E
Y
H
H
H
H
H
H
L
X
X
X
X
L
X
L
X
X
X
L
X
X
L
X
X
L
X
X
X
L
X
L
X
X
X
X
L
L
description
The SN54ASC2024 and SN74ASC2024 are 5-input positive-AND gate CMOS standard cells, Each cell
is designated and called from the engineering workstation input using the following cell name to develop
labels for the design netlist:
AN510LH
NETLIST
TYPICAL
RELATIVE
HDL LABEL
DELAY
CELL AREA
CL - 1 pF
2,9 ns
TO NA210LH
Label: AN510LH A,B,e,D,E,Y;
...
til
CD
CD
.c
FEATURES
CELL NAME
II
Ul
...caca
2,25
C
The SN54ASC2024 is characterized for operation over the full military temperature range of - 55 ac to
125 ac, The SN74ASC2024 is characterized for operation from - 40 ac to 85 ac,
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2,
electrical characteristics
PARAMETER
TEST CONDITIONS
VT
Input threshold voltage
ICC
Supply current
ei
Input capacitance
Vee - 5 V,
Equivalent power
Vee
epd
ISN54Ase2024
ISN74Ase2024
. dissipation capacitance
Vee - 5 V,
Vee = 4,5 V to 5,5 V,
TA
=
TA
VI
~
=
25°C
Vee or 0,
MIN to MAX
=
5 V,
TA - 25°C
tr
= tf =
TA = 25°C
:':~:~~i;8{::1~1e =~:i:r :.~u:a-:~:t::'S not
3 ns,
MAX
UNIT
286
17,2
nA
V
0,13
pF
1.12
pF
Copyright © 1986. Texas Instruments Incorporated
PRODUCTION DATA do.uments .ontain information
current 8S of publication date. Products conform to
specifications par the terms of Taxas Instruments
TYP
2,2
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-351
SN54ASC2024, SN74ASC2024
5·INPUT POSITIVE·AND GATES
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETERt
tpLH
tpHL
tpLH
tpHL
.:l.tpLH
.:l.tpHL
TEST
FROM
(INPUT)
TO
(OUTPUT)
CONDITIONS
A thru E
Y
CL = 0
A thru E
Y
A thru E
Y
CL = 1 pF
tpropagation delay times are measured from VI = 44% to Vo
tpLH ,'" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
.:l.tpLH '" change in tpLH with load capacitance
.:l.tpHL '" change in tpHL with load capacitance
tTypical values are VCC = 5 V, TA = 25°C.
•
SN54ASC2024
=
MIN
MAX
1
TYP*
2.4
6.1
0.7
1.7
3.9
1.6
3.4
1.1
SN74ASC2024
MIN
MAX
1.1
TYP*
2.4
0.8
1.7
3.5
8.6
1.7
3.4
7.5
2.3
5.5
1.1
2.3
4.9
0.5
1
2.5
0.5
1
2.2
0.2
0.6
1.6
0.3
0.6
1.4
44% of VCC with tr
=
tf
=
5.3
UNIT
ns
ns
ns/pF
3 ns (10% and 90%),
DESIGN CONSIDERATIONS
Refer to Section 7.
o
....
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
I»
I»
en
:T
CD
CD
....
tI)
4-352
TEXAS •
INSTRUMENT'S
POST Oi=FICE BOX 665012 • DALLAS, nXAS 75265
SN54ASC2102, SN74ASC2102
TOGGLE FLIP-FLOPS WITH PRESET/CLEAR
02939. AUGUST 1986
SystemCell™
a and az
2-j.lm HARDWIRED MACRO CELL
•
Provides Complementary
•
Choice Between Three Clocked Toggle
Flip-Flop Configurations
latch cells offered
Outputs
•
Cascadable for Implementing
Ripple Counters
•
Implements High-Speed Counters:
Clock Frequencies'. . . 54 to 65 MHz
CELL NAME
PRESET
CLEAR
TAB20LH
yes
yes
TAC20LH
TAP20LH
no
yes
yes
no
description
The SN54ASC2102 al]d SN74ASC2102 are dedicated, harclwired standard-cell macros implementing toggle
flip-flops with clear andlor preset. The 'ASC21 02 latches offer three choices of individual flip-flop
configurations providing the custom IC designer a clocked storage element to embecl in ASICs in its most
efficient form: as stand-alone bit-control devices or as additions to larger latched function.
A low level at the preset or clear input controls the state of the outputs regarclless of the levels at other
inputs. When preset and clear inputs are inactive (high) and the clock input makes a low-to-high transition,
each of the complementary outputs will toggle to its opposite state. While the clock remains high or
transitions to the low level and remains low, the outputs will remain stable. The cells are designated and
called from the engineering workstation input using the following cell names to develop labels for the design
netlist:
FEATURES
MAXIMUM
NETLIST
CELL NAME
HDL LABEL
CLOCK
CELL AREA
TO NA210LH
54.2 MHz
7.7
TAC20LH
Label: TAC20LH CLRZ.CLK.O.OZ;
61.7 MHz
7.2
TAP20LH
Label: TAP20LH PREZ,CLK,O,OZ;
65.8 MHz
7
en
.....
..c
FREQUENCY
Label: TAB20LH CLRZ.PREZ.CLK.O,OZ;
III
CD
CD
RELATIVE
TAB20LH
II
en
.....CO
CO
C
The SN54ASC2102 is characterized for operation over the full military temperature range of - 55 DC to
125°C. The SN74ASC2102 is characterized for operation from -40 0 C to 85 DC.
logic symbol t
FUNCTION TABLE
TAB20LH
TAB20LH.
~
PREZ=a;S
CLK
T
CLRZ
R
OUTPUTS
INPUTS
Q
OZ
........
'---
,t This symbol is in accordance with ANSIIIEEE Std 91·1984 and
IEC Publication 617·12.
PREZ
CLRZ
CLK
Q
L
H
H
L
H
L
L
Lt
H
Lt
00
00
00
00
L
L
H
H
X
X
X
i
H
H
L
OZ
:t: This configuration is nonstable; that is, it
will not persist when the PREZ and CLRZ
inputs return to their inactive (H) level.
PRODUCTION DATA dllt;um••ts cont.in inlormatio.
currant as af Pllblicl1:ion data. Products conform to
.cilic.tlo.s par the terms 01 TOlla. I.s!fu",••ts
standard JVI"~nty. Praduction processing duas nOt
.......ril' i.clud. lastio. 01 .n R.raDlate...
~
TEXAS
INSTRUMENTS
POST OfFICE BOX 655012. DALLAS, TEXAS 75265
Copyright © 1986. Texas Instruments Incorporated
4-353
SN54ASC2102,
S~74ASC2102
TOGGLE FLlP·FLOPS WITH PRESET/CLEAR
logic symbols t
FUNCTION TABLES
TAC20lH
ClK
ClRZ
--:-f>T
TAC20lH
r-- a
INPUTS
-Ir-- az
~L_
RR _ _
OUTPUT
ClRZ
ClK
a
l
X
L
H
H
T
Co
L
00
ao
Co
H
TAP20LH
PREZ:S
QZ
TAP20lH
J--- a
INPUTS
.Jr-- az
ClK - - - P -__
L T_ _
tThese symbols are in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
OUTPUT
PREZ
L
ClK
X
a
H
L
H
T
00
00
H
L
00
00
QZ
absoiute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
4
o
....C»C»
.
timing requirements over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
TAB20lH
SN54'
en
::r
CD
CD
a
MIN
fclock
tw
tsu
th
Clock frequency
Pulse duration
Setup ,time:, before clock
Hold time after clock
TAC20lH
SN74'
MAX
MIN
50.8
MAX
SN64'
MIN
54.2
CLRZ low
8.8
7.6
PREZ low
7.6
7.6
CLK high or low
9.8
CLRZ inactive
PREZ inactive
SN74'
MAX
MIN
54.2
61.7
7.6
7.6
9.2
9.2
8.2
7.2
6
4.8
4.8
7.2
4.8
CLRZ low
0
0
0
PREZ low
0
0
-0.8
UNIT
MAX
MHz
ns
ns
ns
TAP20lH
SN54'
MIN
fclock
Clock frequency
tw
Pulse duration
tsu
th
Setup time before clock
Hold time after clock
4·354
MAX
SN74'
MIN
58.3
UNIT
MAX
65.8
MHz
PREZ low
7.6
7.6
CLK high or low
8.5
7.6
PREZ inactive
2.4
2.4
ns
PREZ low
2.4
2.4
ns
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
ns
SN54ASC21D2, SN74ASC21D2
TOGGLE FLlp·FLOPS WITH PRESET/CLEAR
electrical characteristics
TAB20LH
PARAMETER
VT
Input threshold voltage
lee
Supply current
I
ei
epd
Input capacitance
SN54ASC2102
TEST CONDITIONS
I
elRZ
PREZ
I
elK
TYP
TA = 25°e
Vee = 5 V,
Vee - 4.5 V to 5.5 V, VI - Vee or 0,
TA = MIN to MAX
Vee
=
TA
5 V,
= 5 V,
= 25°e
Equivalent power
Vee
dissipation capacitance
TA
tr
=
25°e
= tf = 3
ns,
MAX
2.2
SN74ASC2102
TYP
MAX
56.2
939
0,25
0.25
0.36
0.36
0.29
0.29
4.2
4.2
UNIT
V
2.2
nA
pF
pF
TAC20LH
VT
Input threshold voltage
lee
Supply current
Ci
Cpd
Input capacitance
I
I
SN54ASC2102
TEST CONDITIONS
PARAMETER
elRZ
elK
TYP
TA = 25°e
Vee = 5 V,
Vee - 4.5 V to 5.5 V, VI - Vce or 0,
TA = MIN to MAX
Vee
=
= 5 V,
= 25°e
Equivalent power
Vee
dissipation capacitance
TA
=
TA
5 V,
tr
=
25°e
tf
=
3 ns,
MAX
2.2
SN74ASC2102
TYP
MAX
884
53
0.36
0.36
0.25
0.25
3.79
3.79
UNIT
V
2.2
nA
pF
pF
II
...
CI)
CI)
CI)
TAP20LH
~
VT
Input threshold voltage
lec
Supply current
Ci
epd
Input capacitance
I
PREZ
ClK
TYP
TA = 25°e
Vec = 5 V,
Vec - 4.5 V to 5.5 V, VI - Vce or 0,
=
TA
I
SN54ASC2102
TEST CONDITIONS
PARAMETER
Vec
5 V,
= 5 V,
= 25°e
Equivalent power
Vec
dissipation capacitance
TA
2.2
TA
=
25°e
t r - tf - 3 ns,
TEXAS·~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 15285
SN74ASC2102
TYP
MAX
50.8
0.35
0.35
0.26
0.26
3.59
3.59
UNIT
V
2.2
846
MIN to MAX
=
MAX
nA
til
...caca
C
pF
pF
4-355
SN54ASC2102, SN74ASC2102
TOGGLE FLIP-FLOPS WITH PRESET/CLEAR
switching characteristics over recommended ranges of supply voltage and operating free-air temperi!ture
(unless otherwise noted)
TAB20LH
PARAMETERt
tPlH
FROM
(INPUT)
ClK
TO
TEST
(OUTPUT)
CONDITIONS
SN54ASC2102
Q,QZ
tPHl
tplH
tpHl
tplH
tpHl
tplH
tpHl
6tPlH
6tpHl
MIN
TYP*
2.2
5.1
1.5
SN74ASC2102
I\IIAX
13.4
MIN
TYP*
MAX
2.4
5.1
11.8
8.4
1.6
3.3
7.4
2
3.3
4
9.7
2.1
4
8.6
2
4
9.7
2.1
4
8.6
PREZ
Q
ClRZ
QZ
PREZ
QZ
1.1
2
4.4
1.2
2
4
ClRZ
Q
1.1
2
4.4
1.2
2
4
ClK
Q,QZ
2.4
5.6
14.7
2.6
5.6
12.9
1.7
3.7
9.4
1.!j
3.7
PREZ
Q
2.3
4.5
11
2.4
4.5
ClRZ
QZ
2.3
4.5
11
2.4
4,6
8.3
9.B
9.8
=
Cl
Cl
=
0
1 pF
PREZ
QZ
1.3
2.4
5.4
1.4
ClRZ
Q
1.3
2.4
5.4
1.4
2.4
2.4
Any
Q,m
0.2
0.5
1.4
0.2
0.5
1.2
0.1
0.4
1.1
0.1
0.4
Q.9
FROM
(INPUT)
TO
TEST
(PUTPUTI
CONDITIONS
UJIIIT
ns
ns
ns
4.9
4.9
ns/pF
mTAC20LH
PARAMETERt
C
tplH
SN54ASC2102
ClK
Q,QZ
tplH
ClRZ
QZ
en
tpHl
ClRZ
Q
CD
CD-
tpHl
ClK
Q,QZ
ClRZ
QZ
ClRZ
Q
Any
Q,QZ
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
C»
C»
tpHl
r+
:r
tplH
tPlH
tpHl
6tplH
r+
en
6tpHl
=
Cl
0
TYP*
4.6
MAX
1.4
1.8
1.1
13
IIIIIN
2.1
TYP*
4.6
3.1
7.9
1.6
3.5
8.3
2
4.3
1.2
14.2
2.3
8.8
1.7
9.4
2.2
5.3
1.4
0.2
2
5.1
3.5
4
2.4
0.6
1.3
0.2
0.1
0.4
1
0.1
3.1
3.6
2
6.1
3.5
4
2.4
0.5
0.4
2.2
Cl
=
1.6
1 pF
SN74ASCal0a
MIN
1.9
2.1
1.3
MAX
11.3
7
7.4
3.9
UNIT
ns
12.5
7.7
8.4
ns
4.8
1.2
0.9
ns/pF
TAP20LH
PARAMETERt
tplH
ClK
Q,QZ
tplH
PREZ
Q
tpHl
PREZ
QZ
ClK
Q,QZ
tplH
PREZ
Q
tPHl
6tPLH
6tpHl
PREZ
QZ
Any
Q,QZ
tpHL
tpLH
SN54ASC2102
CL = 0
tpHl
CL = 1 pF
SN14....SC2102
MIN Typl
~AX
MIN
TYP*
MAX
1.9
4.5
12.5
2
1.3
3
8.2
1.8
3.4
8
1.1
2
2.1
1.5
2
1.3
0.2
0.1
4.6
10.9
1.4
3
7.2
1.9
3.4
7.1
4.1
1.2
2
3.8
5
l:P
2.3
5
12
3.4
9.1
1.6
3.4
8
3.9
2.4
9.2
2.2
3.9
8.2
5
1.3
2.4
4.6
0.5
1.3
1
0·2
0.1
0.5
0.4
0·4
1·1
0.9
UNIT
ns
ns
ns/pF
t Propagation delay times are measured from the 44% point of VI to the 44% PQint pf Vo with tr = tf = 3 ns (10% and !!O%).
tPLH '" propagation delay time, low·to-high-Ievel output
.
tpHL '" propagation delay time, high-to-Iow-Ievel output
6tpLH '" change in tpLH with load capacitance
6tpHL '" change in tpHL with load capacitance
*Typical values are at VCC = 5 V, TA = 25·C.
TEXAS . "
4-356
INSTRUMENlS
~
Po.ST OFFICE BOX 655012
~
DALLAS, TEXAS
7526~
SN54ASC21D2, SN74ASC21D2
TOGGLE FLlp·FLOPS WITH PRESET/CLEAR
DESIGN CONSIDERATIONS
interfacing the macro
Inputs and outputs of these dedicated macros are compatible for interfacing directly with cells and macros
available in the TI standard-cell library. The inputs can be driven by either noninverting or inverting input
cells. The outputs can be interfaced to drive off-chip loads with any of the noninverting output buffers
or interfaced to external bidirectional buses through a 3-state input/output TTl/CMOS buffer.
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered for managing unused inputs.
designing for testability
Designers employing storage or bistable elements should consider testability of the design in its final form.
The need to preset or clear these elements should be assessed throughout the development of custom
logic circuits with these considerations extended to the end equipment application with respect to
maintainability. Simple actions on the part of the ASIC designer can result in considerable cost savings,
allowing the expense of IC testing, system testing, and system maintenance to be reduced significantly.
power-up clear/preset
Standard-cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up/clear cells to achieve system initialization.
Control of the clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an AND gate.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
II
•
4-357
•
C
I»
r+
I»
en
::T
CD
CD
r+
til
4-358
SN54ASC210B, SN74ASC210B
J-K-TYPE NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
02939. AUGUST 1986
SystemCell™
2-llm HARDWIRED MACRO CELL
•
Provides Complementary Q and QZ Outputs
•
Negative-Edge Triggered with J and KZ
Data Inputs
•
CLRZ and PREZ Inputs Provide
Asynchronous Initialization
•
J and KZ Inputs Simplify Implementation of
logic symbol t
PREZ
J
Q
CLKZ --.&...;:,4> C1
Toggle Flip-Flops
KZ---'c.:.>.t
CLRZ---'c.:.>.t
QZ
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
description
FUNCTION TABLE
The SN54ASC2108 and SN74ASC2108 are
INPUTS
OUTPUTS
dedicated, hardwired standard-cell macros
PREZ CLRZ CLKZ J KZ
Q
QZ
implementing negative-edge-triggered flip-flops.
L
H
X
X X
H
L
A low level at the Preset or Clear input controls
H
X
X X
L
L
H
Lt
Lt
the state of the outputs regardless of the levels
L
L
X
X X
of the other inputs. When Preset and Clear are
H
H
L
L
L
H
inactive (high), data at the J and KZ inputs
H
H
L
H
TOGGLE
meeting the setup time requirements are
H
H
L
H
00 OZO
transferred to the outputs on the negative-going
H
H
H
H
L
H
edge of the clock pulse. Clock triggering occurs
H
H
L
X X
00 OZO
at a voltage level and is not directly related to
f This configuration is nonstable; that is, it will not
the fall time of the clock transition. Following the
persist when PREZ or CLRZ returns to its inactive
hold time interval, data at the J and KZ inputs
(high) level.
may be changed wihout affecting the levels at
the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J high and KZ low. They
also can perform as Ootype flip-flops if J and KZ are tied together. The JKB21 LH flip-flop implements the
identical function and sequential operation to one-half of the 'LS 109, 'S 109, or 'F1 09 packaged flip-flops
except the JKB21 LH is negative-edge triggered rather than positive-edge triggered. The cell is designated
and called from the engineering workstation input using the following cell name to develop labels for the
design netlist:
•
•
•
•
II
...
fI)
CD
CD
.c
en
...mm
C
FEATURES
CELL NAME
JKB21LH
NETLLlST
MAXIMUM
HOL LABEL
CLOCK
RELATIVE
CELL AREA
FREQUENCY
TO NA210LH
44.2 MHz
13.3
Label: JKB21 LH CLRZ.PREZ.J.KZ.CLKZ.O.OZ;
The SN54ASC21 08 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC21 08 is characterized for operation from - 40°C to 85 DC.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
PRODUCTION DATA do.umanls .ontain information
CURent as of publication data. Products conform to
spacifications per the terms of Texi. Instruments
:~~=~i;·i~:I~'li ~~:~:r lI~O=::::~:~S not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
Copyright @ 1986, Texas Instruments Incorporated
4-359
SN54ASC210B, SN74ASC210B
J-j(-TYPE NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
timing requirements over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
MIN
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time
PREZ or CLRZ low
CLKZ high or low
Hold time
UNIT
44.2
MHz
9
ns
11.4
CLRZ inactive
1.8
PREZ inactive
-0.4
J or KZ high or low
th
MAX
ns
9
CLRZ low
3
PREZ low
9.6
J or KZ high or low
ns
0
electrical characteristics
PARAMETER
VT
•
SN54ASC2108
TEST CONDITIONS
TYP
TA = 25°C
VCC = 5 V,
VCC - 4.5 V to 5.5 V, VI - VCC or 0,
Input threshold voltage
ICC Supply current
=
TA
IJ
Input capacitance
VCC
5 V,
TA
=
25°C
= 5 V,
= 25°C
Equivalent power
VCC
dissipation capacitance
TA
tr
=
tf
=
3 ns,
71.6
0.25
0.25
0.12
0.12
0.13
0.13
4.97
4.97
UNIT
V
1194
IKZ or CLKZ
Cpd
MAX
2.2
MIN to MAX,
=
TYP
2.2
I PREZ or CLRZ
Ci
SN74ASC2108
MAX
nA
pF
pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
.
PARAMETERt
tPLH
tpHL
tpLH
tpHL
FROM
UN PUT)
TO
(OUTPUT)
CLKZ
a,az
CL
PREZ,CLRZ
a,az
CLKZ
a,az
tPLH
tpHL
tpLH
tpHL
.:I.tpLH
TEST
CONDITIONS
CL
PREZ,CLRZ
a,Ol
Any
a,az
.:I.tpHL
=
=
0
1 pF
SN54ASC2108
MIN
SN74ASC2108
TYP*
MAX
MIN
TYP*
MAX
1.8
5
12.9
1.9
2
4.5
4.3
13.4
11.1
2.2
5
11.4
2
4.5
11.1
2.2
4.3
9.8
1.1
2.1
5.2
1.2
2.1
4.8
2.3
5.5
14
2.5
5.5
12.5
2.1
4.9
12.5
2.3
4.9
11.9
2.3
4.8
12.2
2.5
4.8
10.9
1.3
2.5
1.4
2.5
5.8
0.2
0.5
1.2
0.1
0.4
1.1
0.2
0.5
6.4
1.3
0.1
0.4
1.2
UNIT
ns
ns
ns
ns
ns/pF
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tptH '" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
.:I.tpLH '" change in tpLH with load capacitance
.6.tpHL ;;;;; change in tpHL with load capacitance
= 5 V, TA = 25°C.
*Typical values are VCC
4-360
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
SN54ASC2108, SN74ASC2108
J·j(·TYPE NEGATIVE·EDGE·TRIGGERED FLIP·FLOPS
DESIGN CONSIDERATIONS
interfacing the macro
Inputs and outputs of these dedicated macros are compatible for interfacing directly with cells and macros
available in the TI standard cell library. The inputs can be driven by either noninverting or inverting input
cells. The outputs can be interfaced to drive off-chip loads with any of the noninverting output buffers
or interfaced to external bidirectional buses through a 3-state input/output TTL/CMOS buffer.
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
designing for testability
Designs employing storage or bistable elements should consider testability of the design in its final form.
The need to preset or clear these elements should be assessed throughout the development of custom
logic circuits with these considerations extended to the end equipment application with. respect to
maintainability. Simple actions on the part of the ASIC designer can result in considerable cost savings,
allowing the expense of IC testing, system testing, and system maintenance to be reduced significantly.
power-up clear/preset
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of the clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an AND gate.
III
...
en
Q)
Q)
.c
tn
...
CO
CO
o
TEXAS •
INSTRUMENTS
POST OFFICE !;lOX 655012 • DALLAS, TEXAS 75265
4-361
II
4-362
SN54ASC2310, SN74ASC2310
INVERTING 3·STATE BUFFERS WITH ACTIVE·LOW ENABLE
02939, AUGUST 1986
SystemCell™
2-",m INTERNAL STANDARD CELL
logic symbol
•
Choice of Three Performance Levels
•
Active-Low Enable
•
Specified for Operation Over Vee Range of
4.5 V to 5.5 V
•
Functional Operation Over Vee Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
A-DP--
GZ~
FUNCTION TABLE
INPUTS
positive logic equation
y
= If. when
y
GZ is L
OuTPUT
GZ
L
A
H
Y
L
L
L
H
H
X
Z
description
The SN54ASC231 0 and SN74ASC231 0 are inverting 3-state internal buffer standard cells that interface
internal cells with internal buses, The standard-cell library contains three physical implementations providing
the custom IC designer a choice between three performance levels for optimizing designs. Each option
is designated and called from the engineering workstation input using the following cell names to develop
labels for the design netlist:
CELL NAME
HOL LABEL
IV211LH
IV221LH
Label: IV2nlLH A,GZ,Y:
IV241LH
TYPICAL
.c
RELATIVE
DELAY
CELL AREA
CL - 1 pF
2.6 ns
TO NA210LH
1.7 ns
1.5
2
1.3 ns
3
U)
G)
G)
FEATURES
NETLIST
II
...
til
...caca
C
The SN54ASC231 0 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC231 0 is characterized for operation from - 40°C to 85 °C.
absolute maximum ratings and recommended operl'!ting conditions
See Table 1 in Section 2.
Copyright © 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
4·363
SN54ASC2310, SN74ASC2310
INVERTING 3·STATE BUFFERS WITH ACTIVE·LOW ENABLE
electrical characteristics
PARAMETER
VT
Input threshold voltage
ICC Supply current
Ci
Co
Cpd
Input capacitance
II
TYP
TA = 25°C
VCC = 5 V,
A
TA = 25°C
VCC = 5 V,
GZ
Output capacitance
VCC = 5 V,
TA = 25°C
Equivalent power
VCC - 5 V,
t r - tf - 3 ns,
dissipation capacitance
TA = 25°C
VT
Input threshold voltage
ICC
Supply current
Ci
Input capacitance
Co
Output capacitance
0.22
0.39
pF
1
pF
pF
IV241LH
TYP
VI - VCC or 0,
SN74ASC2310
TA = MIN to MAX
MAX
TA = 25°C
359
VCC
=
5 V,
TA = 25°C
Equivalent power
VCC
=
5 V,
tr
dissipation capacitance,
TA
= tf =
C
(f)
J
CD
CD
....
(I)
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3 ns,
1
UNIT
V
2.2
21.5
VCC = 5 V,
....
nA
0.49
VCC - 4.5 V to 5.5 V,
I»
I»
4·364
14.6
0.47
0.55
SN54ASC2310
25°C
UNIT
V
244
10.8
TA = 25°C
=
MAX
2.2
0.22
0.4
VCC = 5 V,
GZ
IV221LH
TYP
180
TEST CONDITIONS
A
MAX
2.2
SN54ASC2310 VCC - 4.5 V to 5.5 V, VI - VCC or 0,
SN74ASC2310 TA = MIN to MAX
PARAMETER
Cpd
IV211LH
TEST CONDITIONS
nA
pF
0.85
0.59
pF
1.88
pF
SN54ASC2310. SN74ASC2310
INVERTING 3-STATE BUFFERS WITH ACTIVE-LOW ENABLE
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
IV211LH
PARAMETERt
tPLH
tpHL
FROM
(INPUT)
A
tpLH
A
tpHL
TO
TEST
(OUTPUT)
CONDITIONS
Y
tpZH
GZ
Y
tpZL
GZ
Y
tpHZ
GZ
Y
tpLZ
GZ
Y
AtPLH
.l.tpHL
.l.tpZH
.l.tpZL
=0
CL
Y
=
CL
SN54ASC2310
1 pF
CL-1pF,
RL
= 40klltoGND
RL
= 20klltoVcC
CL - 1 pF,
= 40
MAX
MIN
TYP*
MAX
0.6
0.9
2
0.6
1.8
0.5
0.9
2.3
0.6
0.9
0.9
1.6
2.9
6.5
1.7
2.9
5.9
1.1
2.2
5.3
1.2
2.2
4.6
1.4
2.7
5.9
1.5
2.7
5.3
ns
1.3
2.5
5.9
1.4
2.5
5.1
ns
7.5
kll to GND
Cl - 1 pF,
Y
GZ
Y
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
2
7.5
4
RL = 20 kll to V CC
A
UNIT
TYP*
CL - 1 pF,
RL
SN74ASC2310
MIN
ns
ns
ns
4
ns
0.9
2
4.6
1
2
4.2
0.6
1.3
0.6
1
2.1
3
4.8
1
1.3
2.1
2.7
4.4
0.5
1.3
3.6
0.6
1.3
3.1
SN54ASC2310
MIN TYP*
MAX
MIN
TYP*
MAX
1.9
0.6
0.9
1.7
ns/pF
ns/pF
IV221LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
A
A
GZ
tpZH
GZ
tpZL
Y
Y
Y
tpLZ
GZ
Y
.l.tpZL
A
Y
GZ
Y
=
1 pF
RL = 40klltoGND
0.9
0.4
0.9
1.9
0.4
0.9
1.7
1.1
1.9
4.1
1.1
1.9
3.8
0.8
1.5
3.5
0.8
1.5
3.1
0.7
1.5
3.2
O.B
1.5
3
ns
1
l.B
4
1.1
l.B
3.5
ns
RL = 20klltoVCC
CL - 1 pF,
RL
= 40
B.9
kll to GND
CL - 1 pF,
B.9
4.5
RL = 20 kll to VCC
4.5
2.3
0.5
1
2.1
0.3
0.7
1.7
0.4
0.7
1.5
0.6
1
2.3
0.6
1
2.1
0.2
0.7
1.8
0.3
0.7
1.5
!!!!
tf
=
ns
ns
1
=
ns
ns
0.4
tpropagation delay times are measured from the 44% pOint of VI to the 44% point of Va with tr
tPLH '" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
tpZH '" output enable time to high level
tpZL '" output enable time to low level
tPHZ '" output disable time from high level
tpLZ '" output disable time from low level
.6.tpLH 5 change in tPLH with load capacitance
.l.tPHL '" change in tpHL with load capacitance
.6.tPZH
UNIT
0.6
CL - 1 pF,
Y
GZ
.l.tPHL
.l.tpZH
CL
=0
CL - 1 pF,
Y
tPHZ
.l.tpLH
CL
SN74ASC2310
a
ns/pF
ns/pF
3 ns (10% and 90%).
change in tpZH with load capacitance
.l.tpZL '" change in tpZL with load capacitance
t Typical values are VCC = 5 V, TA = 25°C.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX
6~5012
• DALLAS, TEXAS 75265
4-365
SN54ASC2310, SN74ASC2310
INVERTING 3·STATE BUFFERS WITH ACTIVE·LOW ENABLE
switching characteristics over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise noted)
.
iV241LH
PARAMETERt
tPLH
tpHL
tpLH
tpHL
tpZH
tpZL
tpHZ
tpLZ
.:l.tpLH
.:l.tPHL
IIo
C»
;
(I)
:::r
CD
!
en
.:l.tPZH
.:l.tpZL
(lNPUTI
FROM
TO
(OUTPUT)
A
Y
A
GZ
GZ
GZ
GZ
A
GZ
TEST
CONDITIONS
CL
Y
Y
Y
Y
CL
=0
=
1 pF
CL - 1 pF,
RL
= 40 kOto GND
CL - 1 pF,
RL
= 20kOtoVCC
SN54ASC2310
= 40
MAX
MIN
TYP*
MAX
0.6
0.9
1.7
0.6
0.3
0.7
1.8
0.3
0.9
0.7
1.6
1.6
O.B
1.4
2.9
O.B
1.4
2.6
0.5
1.1
2.6
0.5
1.1
2.3
0.2
0.9
2.1
0.3
0.9
1.9
ns
0.9
1.5
3.3
0.9
1.5
2.9
ns
9.8
kO to GND
CL - 1 pF,
y
RL
=
y
9.8
4.9
20 kO to VCC
Y
UNIT
TYP*
CL - 1 pF,
RL
SN74ASC2310
MIN
ns
ns
ns
ns
4.9
0.2
0.5
1.2
0.2
0.5
1.1
0.2
0.4
0.6
0.9
1.1
0.2
0.4
0.4
0.6
O.B
0.4
0.1
0.4
1
0.1
0.4
0.8
1
ns/pF
ns/pF
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%),
tpLH .. propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
tpZH .. output enable time to high level
tpZL 2 output enable time to low level
tpHZ .. output disable time from high level
tpLZ .. output disable time from low level
.:l.tpLH '" change in tpLH with load capacitance
.:l.tpHL '" change in tpHL with load capacitance
.:l.tpZH '" change in tpZH with load capacitance
.:l.tpZL '" change in tpZL with load capacitance
*Typical values are VCC = 5 V, TA = 25°C.
DESIGN CONSIDERATIONS
Refer to Section 7.
4-366
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC2311, SN74ASC2311
INVERTING 3·STATE BUFFERS WITH ACTIVE·HIGH ENABLE
02939, AUGUST 1986
SystemCell™
2·llm INTERNAL STANDARD CELL
logic symbol
•
Choice of Three Performance Levels
•
Active·High Enable
•
Specified for Operation Over V CC Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
FUNCTION TABLE
INPUTS
positive logic equation
Y=A
OUTPUT
G
A
H
H
Y
L
H
L
H
L
X
Z
description
The SN54ASC2311 and SN74ASC2311 are inverting 3-state internal buffer standard cells that interface
internal cells with internal buses, The standard-cell library contains three physical implementations to provide
the custom IC designer a choice between three performance levels for optimizing designs. Each option
is designated and called from the engineering workstation input using the following cell names to develop
labels for the design netlist:
.J:
NETLIST
TYPICAL
RELATIVE
(J)
HDL LABEL
DELAY
CELL AREA
CL - lpF
2.6 ns
TO NA210LH
....COCO
IV212LH
IV222LH
(I)
Q)
Q)
FEATURES
CELL NAME
II
....
Label: IV2n2LH A.G, Y;
IV242LH
1.5
1.8 ns
2
1.3 ns
3
C
The SN54ASC2311 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC2311 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
Copyright © 1982, Texas Instruments Incorporated
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
:~~~~:~~ifva{~:I~~e ~!::i~~ti:f ~Io::~:::t::'s~s
not
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-367
SN54ASC2311, SN74ASC2311
INVERTING 3-STATE BUFFERS WITH ACTIVE-HIGH ENABLE
electrical characteristics
PARAMETER
VT
Input threshold voltage
ICC
Supply current
A
Ci
Input capacitance
VCC '" 5 V,
TA = 25°C
Output capacitance
VCC = 5 V,
TA = 25°C
Equivalent power
VCC = 5 V,
tr = tf = 3 ns,
dissipation capacitance
TA = 25°C
G
VT
ICC
Ci
C»
C»
en
:r-
CD
CD
Co
Cpd
2.2
UNIT
V
243
10.8
14.6
nA
0.24
0.47
0.31
0.42
0.18
0.33
pF
0.5
0.98
pF
pF
IV242LH
TYP
MAX
SN54ASC2311
VCC = 4.5 V to 5.5 V,
VI = VCC or 0,
SN74ASC2311
TA = MIN to MAX
358
21.5
VCC = 5 V,
TA = 25°C
1
Output capacitance
VCC = 5 V,
TA = 25°C
VCC ~ 5 V,
tr - tf - 3 ns,
dissipation capacitance
TA = 25°C
nA
pF
0.58
Equivalent power
UNIT
V
2.2
TA = 25°C
G
MAX
180
VCC = 5 V,
A
Input capacitance
TYP
TEST CONDITIONS
Input threshold voltage
Supply current
IV222LH
MAX
2.2
TA = 25°C
VCC = 5 V,
SN54ASC2311 VCC - 4.5 V to 5.5 V, VI - VCC or 0,
SN54ASC2311 TA = MIN to MAX
PARAMETER
r+
TYP
Co
Cpd
IIc
IV212LH
TEST CONDITIONS
0.48
pF
1.86
pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
IV212LH
PARAMETERt
tpLH
r+
en
tpHL
tPLH
FROM
TO
TEST
(INPUT)
(OUTPUTI
CONDITIONS
A
Y
CL = 0
A
Y
CL = 1 pF
tPHL
tpZH
G
Y
tpZl
G
y
G
y
tpLZ
G
y
-V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
BUll1LH
A---{>--Y
positive logic equations
BU110LH, BU112LH
BU111LH
Y=A
Y=A
description
The SN54ASC2321 and SN74ASC2321 are three internal delay buffer standard cells that provide the ASIC
designer with symmetrical delay elements. Each option is designated and called from the engineering
workstation input using the following cell names to develop labels for the design netlist:
.c
NETLIST
TYPICAL
RELATIVE
HDL LABEL
DELAY
CELL AREA
en
CL - 1 pF
3 ns
TO NA210LH
CO
2
...
4 ns
2
C
3 ns
2
BUll0LH
BUlllLH
en
Q)
Q)
FEATURES
CELL NAME
II
...
Label: BU11nLH A,V;
BUl12LH
CO
The SN54ASC2321 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC2321 is characterized for operation from -40°C to 85°C,
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
PRODUCTION DATA documonts contain intormolio.
curront .s of publicolion date, Products conform to
spacifications par th. terms of TaXIS Instruments
:'=~i~'i~:lo:,tJ,; ~~":\:;ti:;
lil":=:::1t::.s not
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-373
SN54ASC2321, SN74ASC2321
BUFFERS
electrical characteristics
PARAMETER
VT
I SN54ASC2321
I SN74ASC2321
Supply current
Ci
Input capacitance
VCC - 5 V,
Equivalent power
VCC - 5 V,
dissipation capacitance
TA
=
12.7
9
25°C
0.05
pF
0.74
0.83
pF
BU112LH
TYP
Input threshold voltage
Supply current
Ci
Input capacitance
VCC - 5 V,
TA - 25°C
Equivalent power
VCC = 5 V,
TA = 25°C
tr
VCC - 5 V,
VCC - 4.5 V to 5.5 V,
TA
dissipation capacitance
=
nA
0.05
VT
I SN54ASC2321
UNIT
V
212
TEST CONDITIONS
I SN74ASC2321
MAX
2.2
150
ICC
Cpd
BU111LH
TYP
MAX
2.2
TA - 25°C
tr - tf - 3 ns,
PARAMETER
4
TYP
VCC = 5 V,
TA = 25°C
VCC - 4.5 V to 5.5 V, VI - VCC orO,
TA = MIN to MAX
.Input threshold voltage
ICC
Cpd
BU110LH
TEST CONDITIONS
MAX
2.2
TA - 25°C
V
151
VI - VCC or 0,
9.1
MIN to MAX
= tf =
3 ns,
UNIT
nA
0.06
pF
0.56
pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
BU110LH
c
...
PARAMETERt
en
::r
tPHL
tpLH
CD
CD
tpLH
CD
CD
tpHL
,
:
Range of
Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
FUNCTION TABLE
INPUTS
positive logic equation
Y = (A.B)
+ (C.D)
OUTPUT
A
B
C
D
Y
H
H
X
X
l
X
X
H
H
l
Any other combination
H
description
The SN54ASC2330 and SN74ASC2330 are 2-wide, 2-input AND-NOR gate CMOS standard cells. Each
cell is designated and called from the engineering workstation input using the following cell name to develop
labels for the design netlist:
FEATURES
CELL NAME
NETLIST
HDl LABEL
TYPICAL
DELAY
A0221LH
label: A0221lH A,B,C,D,Y;
CL - 1 pF
2.6 ns
II
...
U)
RELATIVE
Q)
Q)
CELL AREA
.c:
TO NA210LH
CJ)
2.7
The SN54ASC2330 is characterized for operation over the full military temperature range of - 55 DC to
125 DC, The SN74ASC2330 is characterized for operation from - 40 DC to 85 DC,
...
C
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
VT
Input threshold voltage
ICC
Supply current
._._ ..
II ...... ~
-- - -
_.,-
TYP
2.2
TEST CONDITIONS
VCC - 5 V,
ISN54ASC2330
VCC - 4.5 V to 5.5 V,
ISN74ASC2330
. . . . . , . . . . . . . . . . . . . , , ......
Equivalent power
Cpd dissipation capacitance
PRODUCTION DATA documents contein informetion
current 88 of publication data. Products conform to
spacifications par the terms of Texas Instruments
:~:=~i~8i~:1~18 ~r::i:~i:r :.r::;::::~::.~s nat
13.4
IA
VCC = 5 V,
TA = 25°C
tr
=
=
,,~-
tf
i
...
=3
ns,
UNIT
V
224
VI - VCC or 0,
TA = MIN to MAX
I
MAX
nA
V.I"
I P" I
0.59
pF
Copyright © 1986. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
CO
CO
4-383
SN54ASC233D, SN74ASC233D
2·WIDE, 2·INPUT AND·NOR GATES
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETERt
tpLH
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
Any
tpHL
tpLH
Any
tpHL
dtPLH
Any
dtPHL
Y
=
CL
CL
Y
=
0
1 pF
Y
SN54ASC2330
SN74ASC2330
MIN
TYP*
MAX
MIN
TYP*
MAX
0.7
1.2
2.9
O.B
1.2
2.6
0.4
1.1
2.2
0.4
1.1
2
1.7
3.2
7.3
1.B
3.2
6.7
0.9
2
4.6
0.9
2
4.1
0.9
2
4.6
1
2
4.1
0.5
0.9
2.5
0.5
0.9
2.2
UNIT
ns
ns
ns/pF
tpropagation delay times are measured from 44% pOint of VI to the 44% pOint of Vo with tr = tf = 3 ns (10% and 90%).
tPLH '" propagation delay time, low-to-high-Ievel output
.
tPHL '" propagation delay time, high-to-Iow-Ievel output
dtPLH '" change in tPLH with load capacitance
dtpHL '" change in tpHL with load capacitance
* Typical values are VCC = 5 V, T A = 25°C.
•
C
m
r+
m
DESIGN CONSIDERATIONS
Refer to Section 7.
All inputs to this celi, as well as all cells, must be accounted for in the netlist used to generate the next
level of an ASIC design, A tie-off cell is offered specifically for managing unused inputs,
This Boolean function is a member of a series of multifunction cells designed specifically to simplify the
implementation of a broad class of higher-level logic equations such as:
rJ)
•
CD
CD
•
Exclusive-OR and exclusive-NOR functions
•
Majority decoders
•
Modulo adders
•
Carry-save adders
•
Function generators
•
Random logic
::r
r+
en
Sum of products
Other members of this class of standard-cell functions are grouped in the' ASC6000 series of type numbers,
The selection consists of four primary architectures with expandable versions offered in each:
•
Dedicated and expandable AND-NOR gates
•
Dedicated and expandable OR-AND-NOR gates
•
Expandable AND-OR-NOR gates
•
Expandable OR-NAND gates
•
Expandable AND-OR-NAND gates
•
Expandable OR-ANO-OR-NAND gates
Options are offered in each architecture from basic 2-wide functions up to expandable 3-wide functions
providing single-macro solution to most design requirements, The expandable functions can be combined
with basic gating cells and/or other Boolean cells offered in Texas Instruments SystemCell'" family to
implement application-specific solutions.
4-3B4
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC2331, SN74ASC2331
2-WIDE, 2-INPUT AND-OR GATES
02939, AUGUST 1986
SystemCelrM
•
Typical Propagation Delay:
2.6 ns with 1-pF Load
•
Specified for Operation Over
4.5 V to 5.5 V
2-pm INTERNAL STANDARD CELL
logic symbol
Vee
Vee
Range of
Range of
•
Functional Operation Over
•
Dependable Texas Instruments Quality and
Reliability
2Vt06V
A--....--...
B--'"
Y
C-----~
D---.
=
(A.B)
.~
FUNCTION TABLE
INPUTS
positive logic equation
Y
~
+ (C·D)
OUTPUT
A
B
C
D
Y
H
H
X
X
H
X
X
H
H
H
Any other combination
L
description
The SN54ASC2331 and SN74ASC2331 are 2-wide, 2-input AND-OR gate CMOS standard cells, Each
cell is designated and called from the engineering workstation input using the following cell name to develop
labels for the design netlist:
II
....
II)
FEATURES
CELL NAME
A0220LH
NETLIST
TYPICAL
Q)
Q)
RELATIVE
HDL LABEL
DELAY
CELL AREA
TO NA210LH
Label: A0220LH A,B,C,D,Y;
CL - 1 pF
2.6 ns
.c
U)
....COCO
3.1
The SN54ASC2331 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC2331 is characterized for operation from -40°C to 85°C,
0
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2,
PRODUCTION DATA d••unien" •• ntoin information
• urrent II of publication dille. P..ducts .onform 10
sp..ifications per Ih. lerm. of T.llls IlIIIrulD.nts.
standord w.",IIty. Production p......i•• do... not
._rily includ. tasting 01 .11 Pll'lIm8l8rs.
Copyright © 1986, Texas Instrumel1ts Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-385
SN54ASC2331. SN74ASC2331
2-WIDE. 2-INPUT AND·OR GATES
electrical characteristics
VT
PARAMETER
Input threshold voltage
I
ICC Supply current
Ci
TEST CONDITIONS
SN54ASC2331
LSN74ASC2331
Input capacitance
Equivalent power
Cpd
dissipation capacitance
TYP
2.2
VCC - 5 V,
VCC = 4.5 V to 5.5 V,
TA = MIN to MAX
TA - 25°C
VCC = .5 V,
VCC - 5 V,
TA = 25°C
TA - 25°C
t, - tf - 3 ns,
VI
=
MAX
V
255
15.3
VCC or 0,
UNIT
nA
0.13
pF
0.9
pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETERt
FROM
(INPUT)
TO
TEST
(OUTPUTI
CONDITIONS
tpLH
tpHL
Any
Y
CL = 0
Any
Y
CL = 1 pF
tpLH
tpHL
CLK---t>
SERIN
GA
OA
SERIN
GAZ
OB
OC
OB
00
OBZ
OC
OCZ
00
ODZ
LZ_S
LZ_S
ClK
CLK
SERIN
SERIN
20
D)
A
10
D)
B
10
en
C
OC
0
00
C
...
OA
:r
CD
CD
...
OA
A
OB
GAZ
OB
B
OBZ
OC
C
OCZ
00
(/I
0
ODZ
tThese symbols are in accordance with ANSIIIEEE Std 91-1984 and IEC Publication 617-12.
FUNCTION TABLES
•ASC2401 ••ASC2402
INPUTS
CLRZ
CLK
SERIN
L
H
X
t
i
H
L
H
•ASC2403.· ASC2404
INPUTS
OUTPUTS
OC*
L
00*
X
OB*
L
SERIN
A
B C 0
H
OAn
OC n
L
t
X
a
b
c d
a
OC*
c
L
L
OAn
QBn
Q8 n
OB*
b
00*
H
QC n
H
i
OAn
QBn
OC~
00
QO
00
00
X X X
X X X
X X X
H
X
X
X
X
L
OAn
QBn
OC n
L
LZ_S CLK
H
t
H
L
X
L
X
~The •ASC2402 and •ASC2404 QxZ output is the complement of Ox.
absolute maximum ratings an~ recommended operating conditions
See Table 1 in Section 2.
4-408
OUTPUTS
DATA
GA*
L
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
OA*
QO
no no
d
00
SN54ASC2401 THRU SN54ASC2404
SN74ASC2401 THRU SN74ASC2404
4-811 SHIFT REGISTERS
timing requirements over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
R2401lH
SN54'
fclock
tw
tsu
th
Clock frequency
r-'MIN
MAX
0
59.6
MIN
MAX
0
59.6
MIN
MAX
0
59.6
8.4
8.4
8.4
8.4
8.4
8.4
SERIN (H or L)
5.8
5.8
5.8
5.8
CLRZ inactive
-3
0.2
-3
0.2
-3
0.3
5.4
5.4
5.4
Setup time
Hold time
SERIN (H or LI
-3
0.2
after clock
ClRZ active
5.4
Setup time
before clock
Hold time
th
after clock
MIN
MAX
0
59.6
SN74'
MIN
MAX
0
59.6
SN54'
MIN
MAX
MHz
ns
ns
ns
0
59.6
SN74'
MIN
MAX
0
59.6
CLK high
8.4
8.4
8.4
8.4
ClK low
8.4
8.4
8.4
8.4
SERIN (H or LI
5.8
5·8
5.8
5.7
LZ_S (H or L)
0
0
0
0
A .. D (H or L)
5.8
5.8
5.8
5.7
SERIN (H or L)
-0.4
0
-0.3
-0.3
0
-0.4
LZ_S (H or L)
0
-0.3
0
-0.3
-0.4
-0.3
A .. D (H or L)
UNIT
R2404lH
R2403lH
SN54'
tsu
59.6
8.4
before clock
tw
0
8.4
ClK low
Clock frequency
MAX
6.6
ClK high
Pulse duration
MIN
6.6
5.4
fclock
SN74'
SN54'
5.4
ClRZ low
Pulse duration
R2402lH
SN74'
UNIT
MHz
ns
ns
•
....
U)
ns
CI)
CI)
.c
(J)
....C'C'CCII
C
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-409
SN54ASC2401 THRU SN54ASC2404
SN74ASC2401 THRU SN74ASC2404
4·81T SHIFT REGISTERS
electrical characteristics
R2401LH
TEST CONDITIONS
PARAMETER
VT
lee
ei
Input threshold voltage
Supply current
Vee = 5 V,
Vee - 4.5 V to 5.5 V,
TA = 25°e
TYP
~
SERIN
TA = 25°e
Equivalent power
dissipation capacitance
tr = tf = 3 ns,
Vee = 5 V,
TA = 25°e
TYP
MAX
2.2
1.04
Vee = 5 V,
SN74ASC2401
UNIT
V
184
3071
TA = MIN to MAX
Input capacitance
MAX
2.2
VI - Vee or 0,
elK
epd
SN54ASC2401
nA
1.04
0.13
0.13
0.24
0.24
10.3
10.3
pF
pF
R2402LH
TEST CONDITIONS
PARAMETER
VT
lee
..
..
C
t»
t»
en
::r
ei
Input threshold voltage
Supply current
Input capacitance
~
SERIN
Vee = 5V,
Vee - 4.5 V to 5.5 V,
T A = MIN to MAX
TA = 25°e
elK
Equivalent power
epd
dissipation capacitance
tr = tf = 3 ns,
Vee = 5 V,
TYP
TA = 25°e
MAX
2.2
VI - Vec or 0,
TA = 25 0 e
Vee = 5 V,
SN54ASC2402
SN74ASC2402
TYP
MAX
3355
202
1.04
1.04
0.13
0.13
0.24
0.24
12.1
12.1
UNIT
V
2.2
nA
pF
pF
R2403LH
CD
CD
PARAMETER
en
Input threshold voltage
VT
lee
ei
TEST CONDITIONS
Supply current
Input
capacit~nce
Vee = 5 V,
Vee - 4.5 V to 5.5 V,
TA = 25°e
TYP
2.2
VI - Vee or 0,
~
lZ_S
Ci:K
Equivalent power
dissipation capacitance
MAX
TA = 25°e
Vee = 5 V,
TA = 25°e
tr = tf = 3 ns,
TYP
MAX
UNIT
V
2.2
223
nA
0.19
0.19
Vee = 5 V,
SN74ASC2403
3711
TA = MIN to MAX
-D,;-"1
epd
SN54ASC2403
0.8
0.8
0.24
0.24
0.19
0.19
11.1
11.1
pF
pF
R2404LH
TEST CONDITIONS
PARAMETER
VT
Input threshold voltage
lee
Supply current
Vee = 5 V,
Vee = 4.5 V to 5.5 V,
TA = 25°e
Input capacitance
~
~
TA = 25°e
4-410
Equivalent power
Vee = 5 V,
dissipation capacitance
TA'" 25 0 e
tr - tf - 3 ns,
TEXAS •
INSTRqM~N1S
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74ASC2404
TYP
MAX
UNIT
V
2.2
240
3995
0.19
Vee = 5 V,
MAX
2.2
TA = MIN to MAX
On
epd
TYP
VI - Vee or 0,
~
ei
SN54ASC2404
nA
0.19
0.8
0.8
0.24
0.24
0.19
0.19
12.1
12.1
pF
pF
SN54ASC2401 THRU SN54ASC2404
SN74ASC2401 THRU SN74ASC2404
4·81T SHIFT REGISTERS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
R2401LH
PARAMETERt
tPlH
tPHl
tPHl
tplH
tpHl
tpHl
LltplH
LltPHl
LltpHl
FROM
(INPUT)
TO
(OUTPUT)
ClK
Q
ClRZ
Q
ClK
Q
ClRZ
Q
TEST
CONDITIONS
Cl = 0
Cl = 1 pF
ClK
Q
ClRZ
Q
FROM
(INPUT)
TO
(OUTPUT)
SN54ASC2401
SN74ASC2401
MIN
TYP~
MAX
MIN
TYP~
MAX
3.6
2.4
1.2
3.9
2.7
1.5
0.3
0.3
0.3
5.7
4.7
1.9
6.2
5.2
2.4
0.5
0.5
0.5
11.1
10.2
3.9
12.3
11.1
4.7
1.3
0.9
0.9
4.1
2.8
1.5
4.4
3.1
1.8
0.3
0.3
0.3
5.7
4.7
1.9
6.2
10.1
9.3
3.6
11.2
5.2
2.4
0.5
0.5
0.5
10
4.4
1.1
0.8
O.B
UNIT
ns
ns
ns
ns
ns/pF
ns/pF
R2402LH
PARAMETERt
tplH
tPHl
tplH
tpHl
tplH
tpHl
tplH
tpHl
tplH
tpHl
tplH
tPHl
LltPlH
LltpHl
LltplH
LltpHl
LltPlH
LltpHl
ClK
TEST
CONDITIONS
Q
ClK
QZ
ClRZ
ClRZ
QZ
Q
ClK
Q
ClK
oz
ClRZ
ClRZ
QZ
ClK
Q
ClK
QZ
ClRZ
ClRZ
QZ
Cl = 0
Cl = 1 pF
Q
Q
SN54ASC2402
SN74ASC2402
MIN
TYP~
MAX
MIN
TYP~
MAX
3.7
2.5
5.9
4.9
11.6
10.5
3.9
2.6
5.9
4.9
2.7
3.8
1.5
1.3
4
2.7
3.3
4.3
2.1
1.5
0:3
0.2
0.6
0.5
0.6
0.2
5.3
6.1
2.5
2.1
6.4
5.3
6.3
7.2
3.5
2.5
0.5
0.4
1
1.1
1
0.4
11.1
12.2
4.7
4.1
12.8
11.3
13.5
14.8
6.9
4.9
1.2
0.8
2.3
2.7
2.3
0.8
2.9
4.1
1.6
1.3
4.2
2.9
3.5
4.7
2.2
1.6
0.3
0.3
0.6
0.6
0.6
0.3
5.3
6.1
2.5
2.1
6.4
5.3
6.3
7.2
3.5
2.5
0.5
0.4
1
1.1
1
0.4
10.5
9.5
10.1
11.1
4.5
3.9
11.6
10.2
12.1
13.4
6.5
4.6
1.1
O.B
2
2.4
2
O.B
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with t- = tf
=
UNIT
ns
ns
ns
ns
ns
a...
U)
CD
CD
J:.
(/)
ns
ns
ns
...caca
C
ns/pF
ns/pF
ns/pF
ns/pF
3 ns (10% and 90%).
tplH ., propagation delay time, low-to-high-Ievel output
tpHl '" propagation delay time, high-to-Iow-Ievel output
LltplH .. change in tplH with load capacitance
AtpJ-I1
;;;5
chanoe in teul with 1('11=10
*Typical values are
at\i c-c
rSlnSlr.it::ln~~
= 5 V, TA'= 25°C.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-411
SN54ASC2401 THRU SN54ASC2404
SN74ASC2401 THRU SN74ASC2404
4·81T SHIFT REGISTERS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (continued)
R2403LH
PARAMETERt
tpLH
tPHL
tpLH
tpHL
AtPLH
AtpHL
FROM
(INPUT)
TO
(OUTPUT)
CLK
a
TEST
CONDITIONS
CL
=0
CLK
a
CLK
a
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
CL
= 1 pF
SN74ASC2403
SN54:ASC2403
MIN
MAX
MIN
TYP*
MAX
3.5
TYP*
5.4
10.2
4.6
10
3.6
2.5
5.4
4.6
9.4
2.3
3.8
6
11.5
3.9
6
10.5
2.6
5
10.8
2.8
9.8
0.3
0.5
1.3
0.3
5
0.5
0.3
0.5
0.9
0.3
0.5
0.8
9
1.1
UNIT
ns
ns
ns/pF
R2404LH
PARAMETERt
tPLH
tpHL
tpLH
•
tpHL
tpLH
tpHL
tpLH
c
tpHL
....
CI)
AtPLH
AtPHL
CI)
en
!
AtPLH
:::T
CD
til
AtPHL
CLK
a
CL
CLK
CLK
az
a
CLK
CLK
SN74ASC2404
TYP*
MAX
MIN
5.6
10.7
3.7
TYP*
5.6
MAX
3.6
2.4
4.8
10.2
2.6
4.8
9.3
9.8
2.6
5.2
10.8
2.7
5.2
9.9
3.7
5.8
11.3
3.9
5.8
10.4
3.9
6.1
11.9
4
6.1
10.8
2.6
5.2
11
2.9
5.2
10
3.2
6.2
13.1
3.4
6.2
11.9
4.2
6.9
13.9
4.5
6.9
12.7
a
0.3
0.5
1.2
0.3
0.5
1.1
0.2
0.8
2.3
0.3
0.7
0.8
az
0.4
1
0.4
0.6
1
2
0.5
1.1
2.7
0.6
1.1
2.4
CL
CLK
=a
SN54ASC2404
MIN
=
1 pF
az
UNIT
ns
ns
ns
ns
ns/pF
ns/pF
tPropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%1.
tpLH '" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
4tPlH
.=
change in tpLH with load capacitance
AtpHL '" change in tpHL with load capacitance
Typical values are at VCC = 5 V, TA = 25°C.
*
DESIGN CONSIDERATIONS
designing for testability
Designers employing storage or bistable elements should consider testability of the design in its final form.
The need to preset or clear these elements should be assessed throughout the development of custom
logic circuits with these considerations extended to the end equipment application with respect to
maintainability. Simple action on the part of the ASIC designer can result in considerable cost savings,
allowing the expense of IC testing, system testing, and system maintenance to be reduced significantly.
power-up clear/preset
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of the clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an AND gate.
4-412
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC2405 THRU SN54ASC2407
SN74ASC2405 THRU SN74ASC2407
4-BIT FLIP-FLOPS/REGISTERS
02939, AUGUST 1986
SystemCell™
2-/lm HARDWIRED MACRO CELL
•
Designed for Implementing Synchronous
Registers
•
Choice of Three Versions to Achieve Best
Design Density
•
Embedded Clock Drivers Provide
Symmetrical Performance Across Long
Registers
•
Cascable and Expandable for Full
Customization
REGISTER CONFIGURATIONS OFFERED
ASVNCHRONOUS
CELL NAME
OUTPUTS
'ASC2405
'ASC2406
Q
Q and Q
Ves
Ves
'ASC2407
Q 13-State)
Ves
CLEAR
description
The' ASC2405 thru 'ASC2407 are dedicated, hard-wired standard-cell macros implementing a three 4-bit
flip-flop register elements. The three register configurations provide the custom IC designer with 4-bit
registers to embed in ASICs in their most efficient form. Their 4-bit length means that larger blocks of
custom logic can be handled efficiently to construct large registers.
The macros each contain an embedded clock driver that buffers the clock input to a single 2-line input.
This further simplifies implementaion of longer registers, as standard library buffer cells can be used to
drive mUltiple clock inputs, which are used in the longer registers. The macro cells are identified and called
from the engineering workstation input using the cell names and netlist in conjunction with labels developed
as shown in the following table:
CELL NAME
NETLIST
CLOCK
HDL LABEL
FREQUENCV
(SN74ASC')
R2405LH
Label: R2405LH CLRZ,Dl,D2,D3,D4,CLK,Ql,Q2,Q3,Q4;
R2406LH
Label: R2406LH CLRZ,Dl ,D2,D3,D4,CLK,Ql ,Ql Z,Q2,Q2Z,Q3,Q3Z,Q4,Q4Z;
64.2 MHz
64,2 MHz
R2407LH
Label: R2407LH CLRZ,Dl ,D2,D3,D4,CLK,G,Q 1,Q2,Q3,Q4;
36,3 MHz
en
...
RELATIVE
CO
CO
CELL AREA
TO NA210LH
23.25
26,25
26,25
U)
Q)
Q)
.c
FEATURES
MAXIMUM
...
o
The R2407LH incorporates 3-state outputs for interfacing internal buses directly. When enable G is high,
the normal logic states (high or low levels) of the four outputs are impressed on the data bus. The outputs
are disabled by a low logic level at enable G. The outputs then present a high impedance to the internal
bus. While the outputs are disabled, sequential operation of the flip-flops is not affected.
The SN54ASC' cells are characterized for. operation over the full military temperature range of - 55°C
to 125°C. The SN74ASC' cells are characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
PRODUCTION DATA doc.mants contain information
current as of publication date. Products conform to
spacifications per the terms of Texas Instruments
:::=~~i~8i~:I~~i :=:~ti~n :'~D=::t:~~s
not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright @ 1986, Texas Instruments Incorporated
4-413
SN54ASC2405 THRU SN54ASC2407.
SN74ASC2405 THRU SN74ASC2407
4·81T FLlP·FLOPS/REGISTERS
logic symbols t
'ASC2405
FUNCTION TABLE
'ASC2405, 'ASC2406
ClRZ
(EACH FLIP-FLOP)
ClK
01
02
01
02
03
03
04
04
INPUTS
OUTPUTS
ClRZ
ClK
0
a
oz*
l
X
X
l
H
H
H
H
L
H
t
t
l
l
H
H
l
X
00
00
'ASC2406
t, ASC2406 only
ClRZ
ClK
01
01
01l
02
02
02l
03
03
03l
Q4
04
C
04Z
'ASC2407
Q)
r+
FUNCTION TABLE
'ASC2407
(EACH FLIP-FLOP)
ClRZ
Q)
G
en
:r
ClK
r+
01
02
02
03
Q3
04
Q4
CD
CD
(II
OUTPUT
INPUTS
01
tThese symbols are in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
a
G
CLRZ
ClK
0
H
L
X
X
l
H
H
H
H
H
H
t
t
L
l
H
H
L
X
00
L
X
X
X
Z
timing requirements over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise noted)
R2405lH
SN54ASC'
MIN
fclock
tw
Clock frequency
Pulse duration
tsu
Setup time before clock
th
Hold time after clock
4·414
MAX
R2406lH
SN74ASC'
MIN
64.2
MIN
64.2
6
6
ClK hi.gh or low
On .(high or low)
7.8
7.8
5.8
5.7
ClRZ inactive
-3
On (high or low)
CLRZ active
ClRZ low
MAX
SN54ASC'
MAX
SN74ASC'
MIN
64.2
64.2
7.8
7.8
7.8
5.7
-3
5.8
-3
0.2
0.3
-0.4
-0.3
5.4
5.4
5.4
5.4
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
7.8
-3
UNIT
MAX
MHz
ns
ns
ns
SN54ASC2405 THRU SN54ASC2407
SN74ASC2405 THRU SN74ASC2407
4-81T FLIP-FLOPS/REGISTERS
timing requirements over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
R2407lH
SN54ASC'
MIN
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time before clock
th
MAX
SN74ASC'
MIN
36.3
ClRZ low
ClK high or low
Hold time after clock
6.6
13.8
On Ihigh or low)
36.3
6.6
13.8
7.6
7.5
CLRZ inactive
-3.6
-3.6
On Ihigh or low)
-0.4
-0.3
6.6
6.6
ClRZ active
UNIT
MAX
MHz
ns
ns
ns
electrical characteristics
R2405LH
PARAMETER
VT
Input threshold voltage
ICC Supply current
Ci
Input capacitance
SN54ASC'
TEST CONOITIONS
VCC = 5 V,
VCC - 4.5 V to 5.5 V,
TA
~
On
=
TYP
TA = 25°C
VI - VCC or 0,'
Equivalent power
dissipation capacitance
2.2
=
TA
5 V,
=
25°C
= 5 V,
= 25°C
VCC
TA
= tf =
tr
3 ns,
MAX
2.2
1.08
VCC
SN74ASC'
TYP
2647
MIN to MAX
ClK
Cpd
MAX
UNIT
V
159
nA
1.08
0.13
0.13
0.24
0.24
10.2
10.2
pF
CI)
pF
fn
PARAMETER
ICC
Ci
Input threshold voltage
Supply current
Input capacitance
SN54ASC'
TEST CONDITIONS
VCC = 5 V,
VCC - 4.5 V to 5.5 V,
TA
~
On
=
VCC
TA
TYP
=
25°C
TA
5 V,
=
25°C
Equivalent power
dissipation capacitance
= 5 V,
= 25°C
VCC
TA
tr
= tf =
3 ns,
SN74ASC'
TYP
MAX
176
1.04
1.04
0.13
0.13
0.24
0.24
11.7
11.7
UNIT
V
2.2
2931
MIN to MAX
=
MAX
2.2
VI - VCC or 0,
ClK
Cpd
CD
CD
.c
R2406LH
VT
II
...
...asas
C
nA
pF
pF
R2407LH
PARAMETER
VT
Input threshold voltage
ICC Supply current
Ci
Co
Cpd
Input capacitance
-.-- ..._-
TEST CONDITIONS
VCC = 5 V,
VCC - 4.5 V to 5.5 V,
TA
=
TA
TYP
=
25°C
MAX
3031
MIN to MAX
MAX
UNIT
V
2.2
2.2
VI - VCC or 0,
_... ,-._TYP
192
nA
ClRZ
2.08
2.08
rcuzrc;-
0.25
0.25
0.24
0.24
1.4
0.24
1.4
0.24
pF
11
11
pF
ro;-
VCC
=
5 V,
TA
=
25°C
Output capacitance
VCC - 5 V,
TA - 25°C
Equivalent power
VCC - 5 V,
tr - tf - 3 ns,
dissipation capacitance
TA
=
25°C
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
pF
4-415
SN54ASC2405 THRU SN54ASC2407
SN74ASC2405 THRU SN74ASC2407
4-81T FLIP-FLOPS/REGISTERS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
R2405LH
PARAMETERt
tplH
tpHl
tpHl
tplH
FROM
(INPUT}
TO
TEST
IOUTPUT}
CONDITIONS
ClK
Q
ClRZ
Q
ClK
Q
Cl = 0
Cl = 1 pF
tpHl
tpHl
ClRZ
Q
AtplH
AtpHl
ClK
Q
AtpHl
ClRZ
Q
SN54ASC2405
MIN
SN74ASC2405
MIN
TYP*
MAX
10.5
5.1
4.4
9.4
8.9
ns
ns
3.1
2.3
4.4
10
3.3
2.5
1
1.7
3.5
1.1
1.7
3.2
3.5
6.1
12.8
3.8
6.1
11.5
2.6
5.1
11.8
2.8
5.1
10.5
1.3
2.4
5.3
1.4
2.4
0.4
1
2.3
0.5
1
4.7
'2.1
0.3
0.7
0.7
1.8
1.9
0.3
0.7
1.6
0.3
0.7
1.6
0.3
UNIT
MAX
TYP*
5.1
ns
ns
ns/pF
ns/pF
R2406LH
PARAMETERt
tplH
IIc
tpHl
tplH
tPHl
tplH
...
D)
tPHl
tpLH
D)
en
::r
FROM
TO
TEST
(INPUT)
IOUTPUT}
CONDITIONS
ClK
Q
ClK
CLRZ
tpLH
tpHL
(II
tpHL
tpLH
r+
MAX
MIN
3.1
10.5
2.3
4.5
9.9
2.4
4.8
3.4
5.8
1.1
12.3
QZ
1.4
2.4
Q
1
1.7
3.6
6.1
12.8
2.6
5.2
QZ
CLK
Q
ClK
QZ
AtPlH
AtpHl
AtpLH
AtpHl
AtpLH
AtpHl
CLRZ
ClK
ClK
ClRZ
Cl =' 0
3.3
TYP*
5.1
MAX
9.4
2.5
4.5
8.9
2.6
4.8
9.9
3.6
5.8
11.1
5.4
1.5
2.4
4.8
3.4
1.1
1.7
3.2
6.1
11.5
11.8
3.8
2.8
5.2
10.5
2.9
5.8
13.2
3.1
5.8
11.9
3.6
6.4
13.8
3.9
6.4
12.3
QZ
1.8
3.4
7.7
2
3.4
6.9
Q
1.3
2.4
5.3
1.4
2.4
4.8
0.5
1
2.4
0.5
1
2.1
0.3
0.7
1.9
0.3
0.7
1.7
0.5
1
2.3
0.5
1
2.1
0.2
0.6
1.5
0.3
0.6
1.3
Q
QZ
CL = 1 pF
QZ
0.4
1
2.3
0.5
1
2.1
Q
0.3
0.7
1.9
0.3
0.7
1.6
tpropagation delay times are measured from the 44% pOint of VI to the 44% point of Vo with tr
tplH '" propagation delay time, low-to-high-Ievel output
tpHL " propagation delay time, high-to-Iow-Ievel output
AtplH '" change in tplH with load capacitance
AtpHl '" change in tpHL with load capacitance
:I Typical values are at VCC = 5 V, T A = 25 ·C.
4-416
SN74ASC2406
TYP*
5.1
tpHl
CD
CD
SN54ASC2406
MIN
TEXAS . "
INSTRUMENTS
POST CiFFICE BOX 655012 • DALLAS, TEXAS 75265
= tf = 3
UNIT
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
ns/pF
ns 110% and 90%).
SN54ASC2405 THRU SN54ASC2407
SN74ASC2405 THRU SN74ASC2407
4·81T FLlP·FLOPS/REGISTERS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
R2407LH
PARAMETERt
tplH
tPHl
tpHl
tplH
tpHl
tpHl
FROM
(INPUT)
TO
(OUTPUT)
ClK
Q
ClRZ
Q
ClK
Q
ClRZ
Q
tpZH
G
Q
tpZl
G
Q
tpHZ
G
Q
tplZ
G
Q
Il.tplH
Il.tpHl
Il.tPHl
Il.tPZH
Il.tpZl
ClK
Q
ClRZ
Q
G
Q
TEST
CONDITIONS
Cl
Cl
~
~
0
1 pF
~ 1 pF,
1 kO to GND
Cl - 1 pF,
Rl ~ 1 kO to VCC
Cl - 1 pF,
Rl ~ 40 kO to GND
Cl ~ 1 pF,
Rl ~ 20 kO to VCC
Cl
Rl
~
SN54ASC2407
MIN TYP* MAX
3.3
5.5
11.6
4.8
11.1
2.4
1.1
2
4.4
4.3
7.5
16.1
3
14.4
6.2
1.7
7.9
3.4
ns
ns
9.4
10.5
14.4
ns
4.3
5
8.1
4.4
4
7.7
ns
9.8
9.8
5.6
1
0.6
0.6
0.9
0.8
2
1.4
1.4
2
1.4
Va
ns
5.6
4.6
3.4
3.5
4.8
3.9
1
0.6
0.7
1
0.8
2
1.4
1.4
2
1.4
ns
4.2
3
3.1
4.3
3.3
nsipF
nSipF
nsipF
with tr = tf = 3 ns (10% and 90%),
II
....
en
CD
CD
.c
en
....COCO
tpHZ " output disable time from high level
C
output disable time from low level
5
ns
14.7
tpZH " output enable time to high level
5:
ns
10.5
tpZL ;;:: output enable time to low level
tpLZ
UNIT
9.4
t Propagation delay times are measured from the 44% point of V, to the 44% point of
tpLH == propagation delay time, low~to-high-Ievel output
tpHL ;;:: propagation delay time. high-to-Iow-Ievel output
Il.tplH
SN74ASC2407
MIN TYP* MAX
3.5
5.5
10.5
2.6
4.8
9.8
1.2
2
4
4.5
7.5
14.6
3.2
6.2
12.7
3.4
1.9
7
change in tplH with load capacitance
atpHL '= change in tpHL with load capacitance
Il.tpZH " change in tpZH with load capacitance
Il.tpZl 5 change in tpZl with load capacitance
Typical values are at VCC ~ 5 V, TA ~ 25°C.
*
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-417
SN54ASC2405THRU SN54ASC2407
SN74ASC2405 THRU SN74ASC2407
4-81T FLIP-FLOPS/REGiSTERS
DESIGN CONSIDERATIONS
interfacing the macro
Inputs and outputs of these dedicated macros are compatible for interfacing directly witH cells and macros
available in the TI standard cell library. The inputs can be driven by either noninverting or inverting input
cells. The outputs can be interfaced to drive off-chip loads with any of the noninverting output buffers
or interfa~ed to external bidirectional buses through a 3-state input/output TTL/CMOS buffer.
All inputs to this cell must 6e accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
designing for testability
Designers employing storage or bistable elements should consider testability of the design ih its final form.
The need to preset or clear these elements should be assessed throughout the development of custom
logic circuits with these considerations extended to the end equipment application with respect to
maintainability. Simple actions on the part of the ASIC designer can result in considerable cost savings.
allowing the expense of IC testing. system testing. and system maintenance to be reduced significantly.
•
power-up clear/preset
C
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of the clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an AND gate.
I»
r+
I»
en
:::sCD
CD
r+
(I)
4-~18
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • CALLAS. TEXAS 75265
SN54ASC240B, SN74ASC240B
FOUR-BIT RIPPLE COUNTERS
02939, AUGUST 1986
SystemCell™
2-llm HARDWIRED MACRO CELL
logic symbol t
•
Predesigned for Implementing Custom
Counters
•
Direct Clear Input Simplifies Initialization or
Cycle Length
•
CTRDIV16
~{
CLRZ
Embedded Clock Drivers Provide Clock
Buffering
+
A
QA
QB
QC
no
description
The SN54ASC2408 and SN74ASC2408 are
dedicated, hardwired standard-cell macros
implementing a 4-bit binary counter element.
The 4-bit configuration provides the custom IC
designer a counter element to embed in ASICs
in its most efficient form, Its 4-bit length means
that larger blocks of custom logic can be handled
efficiently to construct large counters, The
'ASC2408 implements a count sequence
identical with that performed by one-half of
packaged 'HC393 and 'LS393 counters with the
exceptions that the' AS2408 clock, A, triggers
on the positive-going edge, and the clear is active
low,
tThis symbol is in accordance with ANSI/IEEE std 91-1984 and
IEC Publication 617-12.
FUNCTION TABLE
INPUTS
OUTPUTS
QD QC QB QA
CLRZ
A
L
H
X
L
L
L
L
t
t
t
t
t
t
L
L
L
H
L
L
H
L
L
L
H
H
L
H
L
L
L
H
L
H
L
H
H
L
t
t
t
t
t
t
t
L
H
H
H
H
L
L
L
UJ
H
L
L
H
H
L
H
L
H
L
H
H
CO
CO
H
H
L
L
H
H
L
H
H
H
H
H
H
H
The macros each contain an embedded clock
driver, that buffers the clock input to a single
2-line input. This further simplifies
implementaion of longer counters, as standard
library buffer cells can be used to drive multiple
clock inputs that are used in the longer collntets.
The macro cell is identified and called from the
engineering workstation input using the cell
name and netlist in conjunction with a label
developed as shown in the following table:
H
H
H
H
H
H
H
t'
H
H
H
L
H
i
H
H
H
H
H
t
L
L
L
L
II
...
tI)
Q)
Q)
.c
...
o
FEATURES
MAXIMUM
CELL NAME
NETLIST
CLOCK
HDL LABEL
FREQUENCY
RELATIVE
CELL AREA
TO NA210LH
I!;N74A!;r.',
Label: R2408LH CLRZ,A,QA,QB,QC,QO;
The SN54ASC2408 is characterized for operation over the full military temperature range of - 55 cC to
125 cC. The SN74ASC2408 is characterized for operation from - 40 cC to 85 CC.
absolutemaxiinum ratings and recommended operating conditions
See Table 1 in Section 2.
PRODUCTION DATA do.uments .ontsin information
• urlift! IS of publi.ltion dsIJ. Products .onform to
opacifi.atio•• ,Ir thl "'ml of Texal Instruments
:=~l;"[n':.':.'li ~.:l::i:; :.r;:!:':t::." not
Copyright © 1986, Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 666012 • DAI.LAS. TEXAS 75265
4-419
SN54ASC240B. SN74ASC240B
FOUR-BIT RIPPLE COUNTERS
timing requirements over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
SN54ASC2408
MIN
MAX
0
59.6
SN74ASC2408
MIN
MAX
0
59.6
UNIT
fclock
Clock frequency
tw
Pulse duration
A high or low
8.4
8.4
tsu
Setup time
CLRZ inactive
-1.2
-1.2
ns
th
Hold time
CLRZ active
4.2
4.2
ns
CLRZ low
7.8
7.8
MHz
ns
electrical characteristics
VT
II
C
....m
m
Input threshold voltage
VCC
=
TA
5 V,
VCC - 4.5 V to 5.5 V,
ICC
Supply current
Ci
LCLRZ
Input capacitance I A
Cpd
SN54ASC2408
TEST CONDITIONS
PARAMETER
TA
=
VCC
VCC
dissipation capacitance
TA
=
5 V,
TA
tr
=
MAX
2.2
3 ns,
208
1.04
1.04
0.24
0.24
7.22
7.22
UNIT
V
3463
25°C
= tf =
TYP
2.2
25°C
MIN'to MAX
=
SN74ASC2408
MAX
VI - VCC or 0,
= 5 V,
= 25°C
Equivalent power
TYP
nA
pF
pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETERt
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
en
OA
::r
tpd
CD
CD
....
til
tPHL
tpd
A
CLRZ
A
tPHL
lltpLH
CLRZ
lltpHL
Any
A
SN54ASC2408
SN74ASC2408
MIN
TYP*
MAX
MIN
2.6
5.5
12.3
2.8
TYP*
5.5
MAX
3.7
8
17.7
4
8
15.9
4.8
10.2
23.1
5.2
10.2
20.7
aD
a
5.9
12.5
28.5
6.4
12.5
25.5
1.3
2.2
4.6
1.4
2.2
4.2
OA
2.9
6
13.5
3.1
6
12.2
08
OC
CL
=0
4
8.5
18.9
4.3
8.5
17
5.1
10.7
24.3
5.5
10.7
21.8
6.2
13
29.7
6.7
13
26.6
08
OC
CL
=
1 pF
aD
a
Any
a
Any
UNIT
11.1
1.6
2.7
5.4
1.7
2.7
5
0.3
0.5
1.3
0.3
0.5
1.1
0.3
0.5
0.9
0.3
0.5
0.8
ns
ns
ns
ns
ns/pF
t Propagation delay times are measured from the 44% point of VI to the 44% point of Va with tr = tf = 3 ns (10% and 90%).
tpd '" propagation delay time, low-to-high· or high-to· low-level output
tpHL .. propagation delay time, high·to-Iow-Ievel output
lltpLH .. change in tpLH with load capacitance
lltpHL .. change in tPHL with load capacitance
'Typical values are at VCC = 5 V, TA = 25°C.
4-420
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC2408, SN74ASC2408
FOUR·BIT RIPPLE COUNTERS
DESIGN CONSIDERATIONS
interfacing the macro
Inputs and outputs of these dedicated macros are compatible for interfacing directly with cells and macros
available in the TI standard cell library. The inputs can be driven by either noninverting or inverting input
cells. The outputs can be interfaced to drive off-chip loads with any of the non inverting output buffers
or interfaced to external bidirectional buses through a 3-state input/output TTL/CMOS buffer.
count definition
Bidirectional counters are available in software macros or can be. constructed using the' ASC2405 through
'ASC2407 4-bit registers.
designing for testability
Designers employing storage or bistable elements should consider testability of the design in its final form.
The need to preset or clear these elements should be assessed throughout the development of custom
logic circuits with these considerations extended to the end equipment application with respect to
maintainability. Simple actions on the part of the ASIC designer can result in considerable cost savings,
allowing the expense of IC testing, system testing, and system maintainence to be reduced significantly.
power-up clear/preset
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of the clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an AND gate.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
a
4-421
III
...c
Q)
Q)
en
:T
CD
CD
...
U)
4-422
SN54ASC2500, SN74ASC2500
CRYSTAL·CONTROLLED OSCILLATORS
PRODUCT
PREVIEW
D2939,AUGUST1986
SystemCell™
2-j.lm HARDWIRED STANDARD CELL
•
Crystal-Contro"ed Oscillator for Generating
On-Chip Clock Signals Up to 20 MHz
•
Specified for Operation Over VCC Range of
4,5 V to 5,5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
logic symbol
G
JUL
XI
Y
XO
Dependable Texas Instruments Quality and
Reliability
description
The SN54ASC2500 and SN74ASC2500 are crystal-contro"ed CMOS oscillators for use in SystemCe"'"
designs. The input XI and the feedback output XO provide the connections for use with an external series
resonant fundamental crystal. The' ASC2500 provides three cells supporting frequencies up to 20 MHz.
Driving on-chip binary frequency dividers, a single oscillator can generate mUltiple system clocks and/or
control functions. Each option is designated and called from the engineering workstation input using the
following cell name and netlist label.
FEATURES
CELL NAME
NETLIST
MAXIMUM
HDL LABEL
FREQUENCY
OSEOOLH
Label: OSxOnLH XI,Y,XO;
OSF02LH
OSE06LH
RELATIVE
...en
CELL AREA
TO NA210LH
5 MHz
129
20 MHz
150
800 kHz
128
G)
G)
.r:.
o
The SN54ASC2500 will be characterized for operation over the full military temperature range of - 55°C
to 125°C, The SN74ASC2500 will be characterized for operation from -40°C to 85°C,
~hal8
of
development. Characteristic data aRit othar
~:;~i::t:=:Sr~:t dt~Si~a=::I~r T:i::~~:~:~::::
products without notica.
C
Copyright © 1986, Texas Instruments Incorporated
PRODUCT PREVIEW d••• mants .ontain information
on products in thl formative or design
...caca
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-423
IIo
....
I»
I»
en
::r
(1)
(1)
....
en
4-424
SN54ASC2502, SN74ASC2502
RC OSCILLATORS
ADVANCE
INFORMATION
02939. AUGUST 1986
SystemCell™
2-llm HARDWIRED STANDARD CELL
•
Single-Pin RC-Controlled Oscillator for
Generating On-Chip Clock Signals
•
Input Hysteresis Improves Response to
Analog Input Levels
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Dependable Texas Instruments Quality and
Reliability
logic symbol
G
JilL
RC
Y
description
The SN54ASC2502 and SN74ASC2502 are single-input RC-controllable CMOS oscillators for use in
SystemCell"' IC designs. Input RC serves as the external connection point for the RC frequency-determining
network. The ASC2502 has a bandwidth of 10 kHz to 1 MHz with the actual frequency dependent on
the RC time constant. The oscillator incorporates hysteresis in the RC input threshold to sharpen the oscillator
response. The cell is designated and called from the engineering workstation input using the following
cell name and netlist label.
II...
FEATURES
NETLIST
CELL NAME
OSE03LH
HOL LABEL
MAX OUTPUT
RELATIVE
FREQUENCY
CELL AREA
RANGE
TO NA210LH
1 MHz
42.2
Label: OSE03LH RC. Y;
U)
Q)
Q)
.c
The SN54ASC2502 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC2502 is characterized for operation from -40°C to 85°C.
tn
...
CO
CO
C
absolute maximum ratings and recommended operated conditions
SN54ASC2502
MIN
Cext
Rext
f out
External RC capacitor
10
External RC resistor
10
MAX
SN74ASC2502
MIN
10
100
10
1
Output frequency
MAX
UNIT
pF
100
1
k!l
MHz
Also, see Table 1 in Section 2.
electrical characteristics
TI=~T ""nl\lnITlnl\l~
PARAMFTFR
TYP
V
1.3
V
TA - 25°e
2.3
2.3
Negative-going threshold voltage
VCC ~ 5 V
TA
Vee - 5 V.
~
Vee - 4.5 V to 5.5 V.
lec
Supply Current
TA ~ MIN to MAX.
VI ~ Vee or 0
ei
Input capacitance
Vee - 5 V.
TA - 25°e
Equivalent power
Vee - 5 V.
tr - tf
dissipation capacitance
TA ~ 25°e
ADVANCE INFORMATION do.uments contain
information on new predaucts in the samplinp or
~reproduction phase 01 dauelopmenL Characteristic
data and other specifications are subject to change
without notice.
_.- ..
1.3
Vt -
epd
MAX
25°C
Vt +
TA ~ 25°C
VT-I
TYP
3.6
VCC ~ 5 V.
Vhys Hysteresis (VT +
MAX
3.6
Positive-going threshold voltage
3 ns,
1026
V
61.5
nA
2.34
2.34
pF
2.44
2.44
pF
Copyright © 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-425
SN54ASC2502, SN74ASC2502
RC OSCILLATORS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETERt
tPLH
tPHL
tPLH
tpHL
.1tPLH
.1tPHL
FROM
(INPUT)
TO
(OUTPUT)
RC
Y
CL
SN74ASC2502
TYP*
MAX
MIN
=a
6.8
14.7
4.2
TYP*
6.8
MAX
3.9
3.3
3.5
5.8
11.5
= 1 pF
5.8
7.6
12.9
4.3
16.7
3.9
7.2
16.3
4.6
4.2
7.6
7.2
14.9
14.4
0.4
0.8
2
0.4
0.8
1.8
0.6
1.4
3.4
0.7
1.4
2.9
y
RC
SNS4ASC2502
MIN
CL
.y
RC
TEST
CONDITIONS
tpropagation delay times are measured from the 50% point of VI to the 50% point of Vo with tr
tpLH '" propagation delay time, low-to-high·level output
tpHL ;a propagation delay time, high-to~low-level output
.1tpLH '" change in tpLH with capacitance
.1tpHL .. change in tpHL with capacitance
*Typical values are at VCC = 5 V, TA = 25°C.
II
UNIT
ns
ns
ns/pF
(10% and 90%).
DESIGN CONSIDERATIONS
An RC network is used to drive the oscillator input. Oscillator output stability is primarily a function of
the temperature coefficients of the components in the RC network.
TYPICAL OUTPUT FREQUENCIES
Rext (kill
f out
Coxt
100
100 Hz
0.1 ~F
100'
10 kHz
0.001 ~F
10 pF
100
VCC
700 kHz
G
..Jl...f'L
RC
>-....- i - - - Y
*On resistance = 150 (}
4-426
= tf = 3 ns
13.6
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
PRODUCT
PREVIEW
SN54ASC2503, SN74ASC2503
DIFFERENTIAL COMPARATORS
02939, AUGUST 1986
SystemCell™
± 10%
COMPATIBLE ANALOG CELL
•
Single 5-V Supply with
•
Very Low Power Consumption ... 60 ,.W
Typical
Tolerance
•
Wide Range of Common-Mode Input
Voltage Includes Ground on P-Channel
Inputs and VCC on N-Channel Inputs
•
External Voltage Reference
logic symbol
INZ~ OUT
IN
description
The C0212LH and C0213LH standard cells are medium-speed comparators and operate from a single
5-volt supply. The e0212LH standard cell is a P-channel comparator, and the e0213LH is an N-channel
comparator. The inputs are connected to ESD-protected bond pads, which are connected to an external
voltage reference and the analog input. The comparators can be configured as either inverting or non inverting
functions and are designed to drive the inputs of logic cells or buffers. The e0212LH P-chaimel comparator
can be used with input voltages between (ground) and 3.5 volts. The e0213LH N-channel comparator
can operate with input voltages between 1.5 volts and Vec. Each cell is designated and called from the
engineering workstation input using the following cell name and netlist label:
CELL NAME
DESCRIPTION
NETLIST
RELATIVE CELL
HDL LABEL
AREA TO NA210LH
5
5
C0212LH
P-C~annel
Comparator
C0212LH INZ,IN.OUT;
C0213LH
N-Channel Comparator
C0213LH INZ,IN,OUT;
II
...
U)
Q)
Q)
The SN54ASe2503 is characterized for operation over the full military temperature range of - 55 °e to
125 oe. The SN74ASC2503 is characterized for operation from - 40 °e to 85°C.
absolute maximum ratings and recommended operating conditions
.c
en
...caca
C
See Table 1 in Section 2.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature.
CL .. 1 pF
C0213LH
PARAMETER
V,O
Input offset voltage
VICR
Common-mode input voltage
MIN
ICC
VCC
product. without noli...
'
TYP
I
UNIT
MAX
50
0
mv
3.5
V
dB
94
100
104
dB
11
11.7
Supply current
=::::sr~:t d:i::.=::'!,T3i::~':::~::'~
MIN
116
97
116
Supply voltage rejection ratio at f = 1 kHz
PRODUCT PREVIEW docume.ts coatain informati.n
on products in the formltl.e or dllion ph••• of
dlvalopment. Characteristic dati anil othar
C0212LH
MAX
50
1.5
Large-signal differential voltage amplification
AVO
CMRR Common-mode rejection ratio at f - 1 kHz
i kSVR
TYP
fiR
I
p.A
Copyright @ 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-427
SN54ASC2503, SN74ASC2503
DIFFERENTIAL COMPARATORS
switching characteristics at
Vee -
PARAMETER
5
V.
TA ... 25
°e
C0213LH
TEST CONDITION
MIN
tpLH
tpHL
AtPLH
100-mV input step with 5 mV of overdrive.
Vref
= VCC/2
AtPHL
TYP
MIN
TYP
1.9
1.71
1:5
8
6
2.14
6
7
MAX
UNIT
ns
ns/pF
1.71
tpLH
tpHL
TTL-level input step 0.2 to 3 V.
AtpLH
Vref
2.06
= 1:6 V
3
7
AtPHL
•
C
m
r+
m
en
::T
CD
CD
r+
(I)
4-428
C0212LH
MAX
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 .' DALLAS, TEXAS 752,65
~s
ns/pF
SN54ASC2507, SN74ASC2507
DYNAMIC DELAY ELEMENT
PRODUCT
PREVIEW
02939. AUGUST 1986
SystemCell™
COMPATIBLE MACRO CELL
•
Provides Dynamic Delay for Custom Delay
Lines
•
Specified for Operation Over
4.5 V to 5.5 V
•
Vce
logic symbol
Range of
I
3t012"0
I
A---t
Dependable Texas Instruments Quality and
Reliability
pv
NV
n
n
~Y
r-.. JOELAY
ADJUST
description
The SN54ASC2507 and SN74ASC2507 are hardwired standard cells implementing an inverting delay buffer
preceded by a transmission gate and driven by an SN54ASC2508/SN74ASC2508 control element. This
provides a custom delay line with a typical delay tolerance range of ± 5%.
The 'ASC2508 control element uses a reference clock signal as a time-base for generating the
complimentary reference voltages, NV and PV, for controlling the data path delay output of the' ASC2507.
The reference clock signal can be supplied from either an on-chip oscillator or an external source.
CELL NAME
DLE10LH
NETLIST
HOL LABEL
Label: DLE10LH A.PV.NV,Y;
TYPICAL
RELATIVE
, DELAY
CL - 1 pF
CELL AREA
TO NA210LH
31012n.
7.41
II
The SN54ASC2507 will be characterized for operation over the full military temperature range of - 55 °C
to 125 DC. The SN74ASC2507 will be characterized for operation from - 40 DC to 85 DC.
design considerations
Data path delays are dependent on the accuracy of the time-base reference and the control block. The
custom delay line can be broken into two sections: 1) the control section and 2) the delay section. The
control section provides the NV and PV voltages for controlling the delay time through the data delay paths
(see Figure 1).
Copyright © 1986. Texas Instruments Incorporated
PRODUCT PREVIEW documonts contain information
on products in the formative or Jlesign ~hase of
davalopment. Characteristic data anll athar
:=:~:sat!=:srr;~t dte:i~a=::I~rT3i=~:~:~~=::
products without notice.
'
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-429
SN54ASC2507, SN74ASC2507
DYNAMIC DELAY ELEMENT
design considerations (continued)
IN
A1
OUT
Y1
IN
OUT
A2
OUT
IN
Yx
Ax
TIME BASE
. REFERENCE
RESET
DELAY
SECTION
Y2
CONTROL BLOCK
(INCLUDES 'ASC25081
}
CONTROL
SECTION
FIGURE 1. BLOCK DIAGRAM OF CUSTOM DELAY LINE
II
C
I»
r+
I»
en
::r
The delay section offers two methods to program line delays. either by the number of delay elements in
the data path or, by the voltage to the PV and NV lines. In Figure 2, the delay ratio between the delay
1, delay 2, and delay 3 data paths is set with the number of delay elements in each data line. Actual dehiy
times through the delay elements can be determined and changed with the PV and NV voltages that are
governed by the control block and the' ASC2508.
Figure 2 shows the basic method of providing three different delay times using six' ASC2507s controlled
by a single 'ASC2708.
CD
CD
'ASC2507
(/I
3to 12ns
r+
- ...
J
PV
FRDM
'ASC250a) NV
1------1
DELAY 1
JDELAY
ADJUST
'ASC2507
DATA
....
........b
-
'ASC2507
3 to 12 ns
3to 12n5
1------1
1------1
J DELAY
ADJUST
-
'ASC2607
'ASC2607
1------1
L.t:..
'---
'ASC2507
3 to 12 ns
3to 12nl
'---
DELAY 2
-I:::.
J DELAY
ADJUST
3 to 12 ns
1-------1
1------1
L..t:.
J DELAY
ADJUST
......t::.
JDELAY
'--ADJUST
-
]
p....- DELAY 3
DELAY
ADJUST.
FIGURE 2. THREE DELAY PATHS CONTROLLED BY A SINGLE CONTROL ELEMENT
4-430
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
SN54ASC2508, SN74ASC2508
CONTROL ELEMENT FOR DYNAMIC DELAY ELEMENT
PRODUCT
PREVIEW
02939. AUGUST 1986
SysternCell™
COMPATIBLE MACRO CELL
•
Provides Dynamic Control for Custom Delay
Lines
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Dependable Texas Instruments Quality and
Reliability
logic symbol
R
P
N
n
n
PV
NV
CAP
description
The SN54ASC2508 and SN74ASC2508 are
hardwired standard cell analog voltage control
blocks for the 'ASC2507 dynamic delay
elements, providing control voltages for the PV
and NV inputs of the delay element.
The 'ASC2508 control element uses a reference clock signal as a time-base for generating the
complimentary reference voltages, NV and PV, to control the' ASC2507 element data path delays. The
reference clock signal can be supplied from either an on-chip oscillator or an external oscillator. A single
control element can control several delay paths and each path can have a different delay time. Typical
time-base reference frequency range is from 5 MHz to 25 MHz.
NETLIST
CELL NAME
HDL LABEL
DLC10LH
Label: DLC10LH P,N,R,CAP,PV,NV;
a
•
...en
RELATIVE
CELL AREA
G)
G)
TO NA210LH
.c
7.41
o
The SN54ASC2508 will be characterized for operation over the full military temperature range of - 55°C
to 125°C. The SN74ASC2508 will be characterized for operation from -40°C to 85°C.
...caca
C
DESIGN CONSIDERATIONS
The timing reference, shown in Figure 1, is implemented with System Cell'" components to provide
temperature and voltage-compensated digital reference inputs that activate the' ASC2508, which generates
the NV and PV control voltages for the' ASC2507 delay element. The timing reference is unique for each
application. Specific timing design information is made available in conjunction with the completion of a
customer's ASIC specification.
Copyright © 1986, Texas Instruments Incorporated
PRODUCT PREVIEW do.uments .ontein i.formatio.
on products in the formative or dasign
~h.sa
of
development. Characteristic data anll othar
:::::.at:C:S
r~:t dt-:lira=::'~r T3i::~~:::~::'~
products without .oli••.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-431
SN54ASC2508, SN74ASC2508
CONTROL ELEMENT FOR DYNAMIC DELAY ELEMENT
FROM SYSTEM
INITIALIZATION
REFERENCE
ClK
n
TIMING
REFERENCE
(Information
Available from
TI design
Centerl
CAP
n
REFERENCE
PV ANALOG
OUTPUT
NV VOLTAGES
TO 'ASC2507
DlC10lH
FIGURE 1. BLOCK DIAGRAM OF TIMING REFERENCE AND CONTROL ELEMENT
FOR GENERATING ANALO~ VOLTAGES. PV AND NV
II
C
m
....m
en
:::T
CD
CD
....
(I)
4-432
. TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
PRODUCT
PREVIEW
SN54ASC2519, SN74ASC2519
MEDIUM-DRIVE OPERATIONAL AMPLIFIER
D2939. AUGUST 1986
SystemCell™
COMPATIBLE ANALOG CELL
logic symbol
•
Single 5-Volt Supply
•
Internally Frequency Compensated
•
Inputs are ESD and Latch-Up Protected
•
Medium Output Drive Capability:
10 kO and 50-pF External Load
IN~ OUT
INZ
description
The SN54ASC2519 and SN74ASC2519 standard cells are medium-speed operational amplifiers that operate
from a single 5-V supply. Their inputs and outputs are connected to ESD-protected bond pads for connection
to external circuitry. The operational amplifiers can be configured as either inverting or noninverting
amplifiers. For precision applications, a separate VCC and ground should be included in the design
specification. The cell is designated and called from the engineering workstation input using the following
cell name to develop labels for the design netlist:
NETLIST
HOL LABEL
AMC12NH IN.INZ.OUT;
The SN54ASC2519 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC2519 is characterized for operation from -40°C to 85°C.
•
....
(I)
G)
G)
absolute maximum ratings and recommended operating conditions
.c:
(J)
CL
External load capacitance
RL
External load resistance
....COCO
C
Also, see Table 1 in Section 2.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 1 pF
PARAMETER
MIN
via
Input offset voltage
VICR
Common-mode input voltage
1
YOM
Maximum peak output voltage swing
1
AVO
Large-signal differential amplification
Unity-gain bandwidth
Bl
Phase margin
, 2 V
READ
description
The SN54ASC3103 and SN74ASC3103 are
dedicated. hard-wired standard-cell macros
implementing a 3-port. high-speed register file
organized as 16 words of 8 bits each. These
devices provide cost-effective. closely coupled
working registers to support high-performance.
bus-structured processors embedded in ASICs.
Multiple 8-bit-wide register files can be used to
implement wide-word. scratch-pad memories.
ADDRESS
,
AODRESS
W",,,
CA'
DA4
The register macros contain embedded buffers
to reduce input loading. This further simplifies
implementation Of larger registers as standard
library cells can be used to interface the register
control inputs. The macro cells are designated
and called from the engineering workstation
input using the cell name and netlist in conjuction
with a label developed as shown in the following
table:
CELL NAME
3
~
D4
os
I..
"
u.
a:
a:
~
.c
.
CIl
«I
«I
C
NETLIST HOL LABEL
Label: RF408LH CLK,WZ,WO,W1,W2,W3,RAO,RA 1,RA2,RA3,RBO,RB1,RB2,RB3,
RF408LH
00.01,02.03,04,05,06.07 ,QAO,QA 1,QA2,QA3,QA4,QA5,QA6,QA 7,
QBO,QB1,QB2,QB3,QB4,Q85,Q86,QB7;
The 16-word-by-8-bit register organization is provided with a data-input port and two read ports that
incorporate dedicated address inputs. As the read mode is asynchronous at both output ports. data entry
and retrieval can occur simultaneously at all three ports. The dedicated address inputs permit full access
to any of the 16-word locations from each port.
An independent write enable. WZ. is provided to simplify implementation of the write cycle. When high.
l;'" write enailie inmolls new aata entry. When low. the write function is enabled. and a positive transition
at the clock input will store data applied at the data inputs in the register word addressed by the writeaddress inputs. WO thru W3.
The SN54ASC31 03 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC3103 is characterized for operation from -40°C to 85°C.
PRODUCTION DATA documents contain information
currant as of publicatioR date. Products conform to
specifications par the terms of TaXIS Instruments
=~:~~i~a{::1~1i ~=:~i:r :.~o:::::::.:~~ not
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1986, Texas Instruments Incorporated.
4-455
SN54ASC3103, SN74ASC3103
16·WORD BY 8·BIT EDGE TRIGGERED 3·PORT REGISTER FILES
WRITE FUNCTION TABLE
WRITE
DATA
ADDRESS
INPUTS
REGISTER
00 •. 07
ADDRESSED
·.
·.
·.
·.
·.
000 .. 070
a ·. h
ClK
WZ
WO
W1
W2
W3
X
t
t
t
t
H
X
X
X
X
X
l
L
L
L
L
a
L
H
L
L
H
L
L
a
L
L
L
a
L
H
H
L
L
a
t
L
H
H
a
X
H
X
H
L
X
X
X
X
·.
·.
OUTPUTS OF
X
h
h
Write word 1
h
Write word 2
a
h
Write word 3
a
·.
h
Write word 1 5
No change
a
h
a
h
h
No change
Write word 0
·.
·.
·.
h
X
FUNCTION
0°0 .. 070
READ FUNCTION TABLE
APORT
A PORT
B PORT
B PORT
READ ADDRESS
DATA OUTPUTS
READ ADDRESS
DATA OUTPUTS
RAO
RA1
L
L
RA2
L
H
L
L
L
L
H
L
L
H
H
L
L
H
L
L
H
H
H
Ic
..
..
RA3
OAQ •• 0A7
RBO
RB1
RB2
RB3
aBO •• OB7
L
Read word 0
H
H
H
H
Read word 15
Read word 1
L
H
H
H
Read word 14
Read word 2
H
L
H
H
Read word 13
Read word 3
L
L
H
H
Read word 12
L
Read word 7
H
L
L
L
Read word 7
H
Read word 15
L
L
L
L
Read word
C»
C»
(I)
:::r
CD
CD
(I)
°
SIGNAL DESCRIPTIONS
NODE
NAME(S)
TITLE
CLK
Clock input
DO,Dn
OAO,OAn
Data input
Data output
Data inputs
OBO,OBn
Data output
Data outputs for B port
RAO,RAn
RBO,RB'n
Read address input
WO,Wn
Write address
WZ
Write input
Read address input
FUNCTION
Data present at the data inputs are stored in the addressed locations during a positive transition
at the clock input. During steady-state (high or low) the clock is inactive.
Data outputs for A port
Read address inputs for A port
Read address inputs for B port
Write address inputs
When low, data can be clocked into the addressed locations. When high, writing is inhibited,
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2. Data stored in the register are retained if the supply voltage is not permitted
to go below 2 volts minimum. Functional characteristics other than data retention are not specified when
Vee = 2 V to 4.5 V.
4·456 '
T~XAS ~
INSTRUMENTS
POST O~FleE ~ox 655012 • bAllAS. fS)(AS 76285
SN54ASC31D3, SN74ASC31D3
16-WORD BY 8-BIT EDGE TRIGGERED 3-PORT REGISTER FILES
electrical characteristics
PARAMETER
VT
Input threshold voltage
ICC
Supply current
Ci
=
=
VCC
VCC
TA
=
5 V,
TA
4.5 V to 5.5 V, VI
MIN to MAX
=
=
TYP
TYP
2.2
25°C
4.2
0.1
0.1
0.16
0.16
VCC = 5 V,
TA
=
25°C
WZ
= 5 V,
= 25°C
Equivalent power
VCC
dissipation capacitance
TA
V
69.6
On
RBn
tr = tf = 3 ns,
UNIT
MAX
2.2
VCC or 0,
Wn
Cpd
SN74ASC3103
MAX
ClK
RAn
Input capacitance
SN54ASC3103
TEST CONOITIONS
0.14
0.14
0.14
0.14
0.14
0.14
0.23
0.23
289
289
~A
pF
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
tw
Clock pulse duration
tsu
Setup time before ClK f
th
Hold time after
elK r
High
MAX
UNIT
10.5
ns
10
low
Write address
8.5
Data
3.5
Write enable
10
Write address
0
Data
6
Write enable
1
ns
CI)
ns
tplH
tpHl
tPlH
tpHl
tpLH
tpHl
tplH
tpHl
Atpi H
FROM
(INPUT)
TO
(OUTPUT)
RAn, RBn
Any
TEST
CONDITIONS
Cl
ClK
RAn, RBn
=
0
Any
Any
ClK
Any
I"'I.lly
Mlly
Cl
=
1 pF
SN54ASC3103
SN74ASC3103
MIN TYP~
MAX
MIN
TYP~
MAX
3.3
6.3
13.4
3.6
6.3
3.7
6.2
13.6
3.9
6.2
12.1
4.7
10.3
22.4
5.1
10.3
19.9
en
...
4.2
10.2
20.6
4.6
10.2
18.3
7
3.9
4.2
7
13
7
14.7
15.1
7
13.5
5.1
11
23.7
5.5
11
21 .. 1
4.6
11
22.1
5
11
19.7
0.3
0.7
1.4
0.3
0.7
1.3
0.8
1.6
0.3
0.8
1.5
t Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr
~Typical values are at VCC = 5 V, TA = 25°C.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
I
= tf =
CO
CO
UNIT
11.8
3.6
4
I 0.3
CD
CD
.r:.
switching characteristics over recommended ranges of supply voltge and operating free-air
temperature (unless otherwise notedl
PARAMETERt
II
...
C
ns
ns
ns
ns
I
USJpr
3 ns (10% and 90%).
4-457
SN54ASC3103, SN74ASC3103
,
16-WORD BY 8-BIT EDGE TRIGGERED 3-PORT REGISTER FILES
PARAMETER MEASUREMENT INFORMATION
=:)(
WRITE
ADDRESS
)C
:
I
I
WRITE
ENABLE
I
I,
I
I
DATA
INPUT
,I
CLOCK
INPUT
1
1
~
if
:X
)(:
1
,:
I
I
I
I
1
I
1
tsu
1-1
~
~
~
tsu
~~
~It
~"
tsu
I
I I
I 1
th--.l
I
1
th--.t
I
I
~I
th
FIGURE 1. SETUP AND HOLD TIMES
II
C
\ \...--_----~/
WRITE
ENABLE
X~__________~X~___
DATA
INPUT
C»
C»
r+
en
::r
CI)
CI)
r+
CLOCK
INPUT
~1~~--~f
~
'(I)
A PORT
OUTPUTS
~
I
I
tw(L1 ---"'+I4---tw(H)--~~
It--- tpLH or t PHL '--+/
I
------~--------------~*~-I
I
B~
OUTPUTS
----------_____"'""'V"'1,..,--7'\~
__
Addresses for write and both reads are the same.
FIGURE 2. CLOCK PULSE DURATION. PROPAGATION DELAY TIMES FROM CLOCK
4-458
tEXAS •
INSTRUMENTs
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54ASC3103, SN74ASC3103
16-WORD BY 8-BIT EDGE TRIGGERED 3-PORT REGISTER FILES
PARAMETER MEASUREMENT INFORMATION
ADDRESS~
RAn
I -----------------------------------
!---tPLH or tPHL ~
OUTPUT
CAn
7'\_
---------~~----------------
ADDRESS~
RBn
~~------------------------------------------~tPLH
O~:~T
or
tPHL~
______________
_J)(~_____________________________
______________F_IG_U_R_E_3_._P_R_P_P_A_G_A_T_IO_N_D_E_L_A_Y_T_I_M_E_S_F_R_O_M_R_E_A_D_A_D_D_R_E_S_S______________
~
...en
DESIGN CONSIDERATIONS
interfacing the macro
Inputs and outputs of these dedicated macros are compatible for interfacing directly with cells and macros
available in the TI standarq cell library. The inputs can be driven by either noninverting or inverting input
cells. The outputs can be interfaced to drive off-chip loads with any of the noninverting output buffers
or interfaced to external bidirectional buses through a 3-state input/output TTL/CMOS buffer.
CD
CD
J::.
tJ)
...
CO
CO
C
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
designing for testability
Designers employing register elements should consider testability of the design in its final form. The need
to provide either direct or multiplexed input pins fQr controlling the register will enhance both testing at
the device level and troubleshooting under field maintenance conditions. Simple actions on the part of
the ASIC designer can result in considerable cost savings, allowing the expense of IC testing, system testing,
and system mqintenance to be re!duced significantly.
TEXAS.
INSTRUMENTS
POS1 OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-459
II
c
....
Q)
Q)
t/)
::r
CD
CD
....
en
4-460
PRODUCT
PREVIEW
SN54ASC3200, SN74ASC3200
CompilerCell™ READ-ONLY MEMORIES
02639. AUGUST 1986
SystemCell™
COMPATIBLE 2-/lm CompilerCell'" ROMs
logic symbol
ROM [W x BI
4>
description
The SN54ASC3200 and SN74ASC3200 are
read-only memory (ROM) CompilerCell"'. They
are compatible with TI's System Cell'" library and
can be a powerful aid to the solution of cell
design problems. They can be selected with bit
capacities between 512 and 65,536.
AO
O}
An
n
'A~C3200
A W - 1
I
ClKl
ClK2
CLOCKS
ClK2Z
EN
These ROMs are clock controlled, which permits
pre-charging of some circuit regions resulting in
speed advantages, lower power dissipation, and
optimum use of silicon. The 'ASC3200 is a
nonvolatile memory whose bit contents are
determined by the presence or absence of
transistors in the rows and columns of the ROM
matrix. The transistors are formed during the
custom patterning process defined by the user.
0
QO
IOATV
i-1
II...
Qi-l
HDL CALL
LABEL: ROM
For bit capacities up to 16K, a single array is
used. For greater capacities, a double array
offers 64K-bit capacity for only 70% more
silicon area. A choice of multiplexing ratios is
offered between the array columns and the
output word, which allows greater flexibility in
the layout of the cell.
CI)
ADO ... ADn.PHllB.PHI2,PHI2B,POWD,
CI)
CI)
OUTO ... OUTn;
..c::
o
...
CIS
CIS
o
TI Compiler Software permits rapid programmation and verification of the chosen pattern, as well as rapid
generation of the desired ROM bit organization. The possible combination of ROM organizations are shown
in Tables 1 and 2.
TABLE 1. SINGLE ARRAY PARAMETER LIMITS
PARAMETERS
Number of Words (W 2: 2n)
Word length (B = i)
Total Number of Bits (W x B)
MIN
8
MAX
2048
4
32
512
16384
COMMENTS
Must be multiple of 4
Even or Odd
TABLE 2. DOUBLE ARRAY PARAMETER LIMITS
MIN
PARAMETERS
Number of Words IW 2: 2n)
Word Length IB = i)
Total Number of Bits IW x B)
8
MAX
. 4096
4
64
512
65536
.;:.e:~::t:=:srr:Ct ~if8=::I~rT:~::'::':~:~:::
products without notice.
Must be Even
Copyright © 1986, Texas Instruments Incorporated
PRODUCT PREVIEW documents contain information
on products in the formative or design ~hase of
dBvalopmant. Characteristic data anit othar
COMMENTS
Must be multiple of 4
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-461
II
C
I»
~
I»
o
::::r
CD
CD
~
til
4-462
ADVANCE
INFORMATION
SN54ASC3430, SN74ASC3430
CompilerCeWM PIPELINE TEST REGISTERS
02939. AUGUST 1986
SystemCell™
COMPATIBLE 2-llm INTERNAL STANDARD CELL
logic symbol
•
n-BIT PIPELINE TEST REGISTER
desc~iption
'ASC3430
The SN54ASC3430 and SN74ASC3430
CompilerCeU'" Pipeline Test Registers assist the
designer in solving the problem of testing VLSI
cell designs. The large gate counts and circuit
complexities permitted by 2-ILm technologies
result in functional blocks so embedded within
the circuit that their inputs/outputs can neither
be monitored or initialized without the use of
very large test pattern sets of I/O cells assigned
specifically for test purpose.
The PTR is an n-bit register whose size is
determined by the user in the design phase
(n = 4 to 32). The principal modes of operation
are as a parallel master-slave latch for holding
and latching data buses or as a serially-loaded
unidirectional register that allows test stimuli and
results to be shifted around the circuit.
SI
I
I
PLD
PLD
eLK1
51
L
CLOCKS
CLK2
SO
H
H
SO
L
H
L
H
MODE
HOLD
LOAD/HOLD
SHIFT
TEST
SUB-MODES IN MODE 3
PLD SUB-MODE
H PAR LOAD
L LOCAL HOLD
MODE
SUB-MODES IN MODE 4
81
Dl
D
QO.
Dn
D
Qn
80
81
H
H
DO
Ql
Sections of a logic circuit may be self tested
using a pair of PTRs. The first PTR is configured
as a pseudo-random pattern generator that
delivers random values at a number of outputs over a time period. The second PTR, arranged as a signature
analyzer, takes the outputs from the circuit under the test over a number of clock cycles and condenses
them into a test signature whose value depends totally on the tested outputs over the specified time period.
At the end of the period, the signature is serially down-loaded from the PTR and compared with a known
"fault free" value in order to arrive at a pass/fail decision. The modes of operation are listed in Table 1
and described in the following paragraphs.
....en
CI)
CI)
.s::
en
....caca
o
TABLE 1. MODES OF OPERATION
MAIN MODE
SUB·MODE
51
SO
HOLD
L
L
USER FUNCTIONAL
L
H
C::::WIE:T
..
~
TEST
H
H
PLD
B1
BO
LOCAL HOLD
L
PARALLEL LOAD
H
X
X
X
X
NONE
."--.-
."v."r:
PATTERN GENERATE
X
L
L
CIRCULAR SHIFT
x
L
H
SIGNATURE ANALYZE
X
H
L
LOCAL HOLD
x
H
H
Copyright © 1986, Texas Instruments Incorporated
ADVANCE INFORMATION do.umants .ontain
~,:!:':=O:;h~~~o~r::a;'~~~~:::::=:~
_ and othar specifications are .ubject 10 change
without notice.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALl.AS, TEXAS 75286
4-463
SN54ASC3430, SN74ASC3430
CompilerCell™ PIPELINE TEST REGISTERS
Hold
AU data is retained in the registers. If all PTRs in the system have common pins, then all
data is held in all registers.
Shift
Data may be serially loaded into the register via pin DO. The data passes through a two-bit
control register whose ouputs BO and B1 determine the sub-mode.
.
User Functional
Data is parallel loaded into the register or held according to the setting of input PLD. In this
mode, each element of the register is isolated from its neighbor and acts as an independent
data latch. in sub-mode "Local Hold", data may be held in just a single register while the
remaining PTRs may be performing other tasks.
Test
In this
~ode,
there are four available sub-modes.
Sub-mode O. Pseudo-Random Pattern Generation
The outputs from the register are fed back to the input via a selected number of ExclusiveOR gates. This is a well-documented method of producing a sequence of pseudo-random
signals from a register for use as test signals for a logic circuit. A four-bit example is shown
in Figure 1.
Sub-mode 1. Circular Shift
Connection in the circular shift mode causes the last output of the PTR to be connected
to the first.
Sub-mode 2. Signature Analysis
As with Pattern Generation, the Signal Analyzer has data fed back to its first input as indicated
in Figure 2. The input of each section of the register is determined by both the preceding
output and the output from the circuit under test. A characteristic data signature is built
up on the register outputs. This signature is dependent on all of the previous output states
of the circuit under test. After a number of clock cycles, the signature of a faulty circuit
will be different from that of a gOOd one.
Sub-mode 3. Local Hold
This sub-mode permits a user to command one or more PTRs in a system to hold its data.
FIGURE 1. PTR AS A PSEUDO-RANDOM
PATTERN GENERATOR
FIGURE 2. 4-BIT PTR AS A SIGNATURE ANALYZER
4-464
TEXAS ."
INSIRUMENTS
POST OFfiCE BOX 655012 • DALLAS. TEXAS 75266
PRODuct
PREVIEW
SN54ASC3800, SN14ASC3800
CompilerCeWM PROGRAMMABLE LOGIC ARRAYS
02939, AUGUST 1986
SystemCell™
COMPATIBLE 2-l'm INTERNAL STANDARD CELL
description
functional block diagram
The SN54ASC3800 and SN74ASC3800
CompilerCeU'· logic arrays are semicustom PLAs
having many of the features of the current
packaged PLAs. The cells operate dynamically
from a system-derived clock and offer significant
power savings compared to the packaged
devices. Cell complexity is decided at the design
stage and can be tailored for the application
resulting in economical use of silicon. Texas
Instruments software generates the PLA
automatically from a library of primitive cells
according to the user's function tables or
Boolean equations. The software will also
produce an HDL description, a simulation model,
timing diagrams, and an individual data sheet.
INPUT
BUFFERS
INO
C>
AND
MATRIX
OR
MATRIX
&
,,'
2mXp
,,'
,,'
INm
m = number of inputs
n = number of outputs
p = number of product terms = qD + q 1 + ... qn - 1
qx = number of inputs to OR gate x (x = D ... n)
OUTO
OUT1
OUTn·'
OUTn
+
qn
The cells are specified by number of inputs, m, number of product terms, p, and number of outputs, n.
The internal matrix follows the usual arrangement of an AND matrix and an OR matrix, Each product term
ANDs together a specified number of inputs, and each output comes from a specified number of product
terms via an OR gate. Maximum values for the parameters are shown below:
INPUTS
PRODUCT
m
p
128
...
U)
CD
CD
.c
U)
...caca
OUTPUTS
TERMS
64
•
C
n
32
Circuit design is optimized around a 32-input X 64-product term X 32-output design that will run at a speed
of 20 MHz.
The SN54ASC3800 will be characterized for operation over the full military temperature range of - 55 DC
to 125 DC. The SN74ASC3800 will be characterized for operation from 0 DC to 70 DC.
PRODUCT PREVIEW d•• umenls .ontain information
.n products in the formative or de.ign ~h••••f
devalopmant, Chara.tari.tl. data .n~ .ther
specifications .r. design gaals. Taus Instruments
reserves the right to change ar discontinue thaSl
products without natica.
Copyright © 1986, Texas Instruments Incorporated,
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-465
III
...C
I»
I»
C/)
:::r
C'D
...
CD
til
4-466
SN54ASC4002, SN74ASC4002
4-INPUT POSITIVE-NOR GATES
02939, AUGUST 1986
SystemCell™
2-llm INTERNAL STANDARD CELL
logic symbol
•
Choice of Two Performance Levels
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
A3YB
D
FUNCTION TABLE
INPUTS
positive logic equation
Y = A+B+C+D = ABeD
description
Y
c
OUTPUT
A
B
C
D
Y
H
X
X
X
L
X
H
X
X
L
X
X
H
X
L
X
X
X
H
L
L
L
L
L
H
The SN54ASC4002 and SN74ASC4002 are 4-input positive-NOR gate CMOS standard cells that implement
the equivalent of one-half of the SN54HC4002 or SN74HC4002, The standard-cell library contains two
physical implementations to provide the custom IC designer a choice between two performance levels
for optimizing designs. Each option is designated and called from the engineering workstation input using
the following cell names to develop labels for the design netlist:
.
N0410LH
NETLIST
TYPICAL
RELATIVE
HDL LABEL
DELAY
CELL AREA
CL - 1 pF
4.1 ns
TO NA210LH
Label: N04nOLH A,B,C,D,Y;
N0420LH
2.6 ns
(I)
Q)
Q)
FEATURES
CELL NAME
•..
.c
en
..
ca
ca
1.5
2,5
C
The SN54ASC4002 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC4002 is characterized for operation from - 40°C to 85 °C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
PROPUCTION DATA do.umllft1S ...ntai. information
currant a8 !o, publication data. Products conform to
~p8Cific.tion. per the terms of Texa. Instruments
standard warranty_ Production processing
does not
.......ril' i.clude \a~1iriil of all para mete...
Copyright © 1986, Texas Instruments Incorporated
TEXAS . .
INST~UMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 75265
4-467
SN54ASC4002, SN74ASC4002
4-INPUT POSITIVE-NOR GATES
electrical characteristics
VT
Input threshold voltage
VCC
=
5 V,
TA
=
TVP
VCC - 4.5 V to 5.5 V, VI - VCC or 0,
ISN74ASC4002
TA
ICC
Supply current
Input capacitance
Equivalent power
VCC = 5 V,
VCC - 5 V,
dissipation capacitance
TA
=
=
N0420LH
MAX
TVP
MAX
2.2
2.2
25°C
ISN54ASC4002
Ci
Cpd
N0410LH
TEST CONDITIONS
PARAMETER
V
177
277
10.6
MIN to MAX
TA
=
25°C
tr - tf
=
3 ns,
25°C
UNIT
16.6
nA
0.11
0.22
pF
0.35
0.55
pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
N0410LH
PARAMETERt
tpLH
tpHL
II
C
...
I»
I»
tPLH
tpHL
tpLH
....
CIl
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONOITIONS
A
Y
CL = 0
A
Y
CL = 1 pF
A
Y
L>tPHL
SNS4ASCSOO3
Typt
MAX
MIN
SN74ASCSOO3
Typt
MAX
MIN
3
6
19
3.1
6
17
1.1
1.4
2.3
1.1
1.4
2.2
6.3
13
35
6.B
13
32
1.3
2
3.B
1.4
2
3.5
3.4
7
17
3.7
7
15
0.2
0.6
1.5
0.2
0.6
1.3
UNIT
ns
ns
ns/pF
IPF08LH
PARAMETER§
tpLH
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Y
tpHL
tPLH
tpHL
L>tPLH
L>tPHL
A
Y
A
Y
CL
CL
=
=
0
1 pF
SNS4ASCSOO3
MIN
TYPt
SN74ASCSOO3
MAX
MIN
Typt
MAX
3.5
7
18
3.7
7
17
1.1
1.5
2.3
1.1
1.5
2.2
7
14
35
7.5
14
32
1.3
2.1
3.B
1.4
2.1
3.5
3.5
7
17
3.B
7
15
0.2
0.6
1.5
0.2
0.6
1.3
UNIT
ns
ns
ns/pF
tTypical values are at VCC = 5 V, TA = 25°C.
Total input capacitance is dependent on the package type and is equal to the sum of package capacitance and intrinsic input capacitance.
The value shown includes the pull-up tap.
§ Propagation delay times times are measured from the 1.3 V point of VI (0 to 3 V) to the 44% point of Va with tr = tf = 2 ns (10% and 90%).
tPLH == propagation delay time, low-to-high-level output
tpHL == propagation delay time, high-to-Iow-Ievel output
.6.tpLH == change in tPLH with load capacitance
.6.tpHL == change in tpHL with load capacitance
:j:
4-486
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC5004, SN74ASC5004
CMOS-COMPATIBLE INVERTING INPUT BUFFERS WITH PULL-UP TAP
D2939, AUGUST 1986
SystemCell™
2-j.lm INPUT STANDARD CELL
•
ns Typical Propagation Delay with 1-pF
Load
•
Incorporates Circuitry to Protect Against
ESD and Latch-Up
logic symbol
TAP=-:1
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
~
A--y-Y
FUNCTION TABLE
INPUT
A
Dependable Texas Instruments Quality and
Reliability
OUTPUT
Y'
H
L
L
H
positive logic equation
Y=A
description
The SN54ASC5004 and SN74ASC5004 are inverting input buffer CMOS standard cells that interface
external CMOS inputs with CMOS internal cells. The cell is designated and called from the engineering
workstation input using the following cell name and netlist label:
4
...
fI)
FEATURES
NETLIST
CELL LAYOUT
HDL LABEL
ASPECT RATIO
Label: IPF02LH A,TAP.Y;
minimum width
CELL NAME
IPF02LH
G)
G)
RELATIVE
.t:.
CELL AREA
UJ
TO NA210LH
35
The cell incorporates a pull-up tap to simplify termination of the input. This tap may be used in conjunction
with an active pull-up/pull-down terminator in the 'ASC237x group or the pull-up tap may be left
unconnected. When the terminator is used it ensures that the input will be driven to a high or low logic
level, thereby avoiding exposure to a high-impedance or floating condition. Refer to Section 7 for
implementation of the pUll-Up.
...caca
C
The cell incorporates circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most common sources that can produce a latch-up condition.
The SN54ASC5004 is characterized for operation over the full military temperature range of - 55°C to
1?f1 or. Thp ~N74A~rt;n()4 i~ ,...h~r~,..,,:~ri·7I'~~ oF,:,!" 'Y::'~!"?!~~~ ~!"~~ - ~0 or: ~~ ~=
0C'.
absolute maximum ratings and recommended operating conditions
See Table 2 in Section 2.
PRODUCTION DATA documents contain information
currant as of publication data. Pradoct. conform to
spacificatiDns par the terms of Taxas Instruments
=~=~~i~8{nr:I~1e =:~i:r
:'f=::::r:::s not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright © 1986, Texas Instruments Incorporated
4-487
SN54ASC5004, SN74ASC5004
CMOS-COMPATIBLE INVERTING INPUT BUFFERS WITH PULL-UP TAP
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
SN54ASC5004
TEST CONDITIONS
TYP
VT
Input threshold voltage
Vee - 5 V,
II
Input current
VI - 0 to Vee
lee
Supply current
VI = Vee or 0
VI - 3.15 V or 0.9 V
ei
Intrinsic input c.apacitance t
Vee
TA
Equivalent power
Vee
tr
dissipation capacitance
TA
epd
TYP
2.5
TA - 25°e
= 5 V,
= 5 V,
= 25°e
SN74ASC5004
MAX
= 25°e
= tf = 3 ns,
MAX
2.5
UNIT
V
±1
±1
~A
999
4.37
60
4.14
rnA
nA
2.3
2.3
pF
2
2
pF
t Total input capacitance is dependent on the package type and is equal to the sum of package capacitance and intrinsic input capacitance.
The value shown includes the pull-up tap.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER*
tpLH
IIo
I»
r+
I»
en
:::T
CD
CD
r+
fn
tpHL
tPLH
tpHL
.l.tpLH
.l.tPHL
FROM
(INPUT)
TO
(OUTPUT)
A
Y
A
Y
A
Y
TEST
CONDITIONS
eL
eL
=0
= 1 pF
SN54ASC5004
TYP§
MAX
MIN
SN74ASC5004
TYP§
MAX
MIN
0.4
0.7
1.2
0.5
0.7
1.2
0.3
0.6
1.5
0.3
0.6
1.3
0.7
1
1.B
0.7
1
1.B
0.5
1
2.3'
0.6
1
2.1
0.2
0.2
0.3
0.7
0.2
0.3
0.6
0.4
0.9
0.2
0.4
O.B
UNIT
ns
ns
ns/pF
* Propagation delay times are measured from the 50% point of VI to the 44% pOint of Vo with tr = tf = 4 ns (10% and 90%).
tpLH '" propagation delay time, low-to-high-Ievel output
tpHL " propagation delay time, high-to-Iow-Ievel output
.l.tpLH '" change in tPlH with load capacitance
.l.tPHL '" change in tpHL with load capacitance
§Typical values are at Vee =' 5 V, TA = 25 oe.
DESIGN CONSIDERATIONS
Refer to Section 7.
4-488
'If
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75266
SN54ASC5005, SN74ASC5005
TTL-COMPATIBLE INVERTING INPUT BUFFERS WITH PULL-UP TAP
02939. AUGUST 1986
SystemCelr
M
2-lJm INPUT STANDARD CELL
•
2.1 ns Typical Propagation Delay with 1-pF
Load
•
Incorporates Circuitry to Protect Against
ESD and Latch-Up
•
logic symbol
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
FUNCTION TABLE
•
•
Functional Operation Over VCC Range of
2Vt06V
Dependable Texas Instruments Quality and
Reliability
INPUT
OUTPUT
A
V
H
L
L
H
positive logic equation
Y=A
description
The SN54ASC5005 and SN74ASC5005 are inverting input buffer CMOS standard cells that translate TTL
input voltage levels to CMOS internal-cell voltage levels. This cell function exists in two versions ("E"
and "F") with different physical implementations to allow the final IC area to be optimized. Since the
electrical performance of each version is identical, for simplicity only one version (the "F" cell) will be
contained in the engineering workstation cell libraries. Determination of the most appropriate cell version
will be made during the layout stage. The cell is designated and called from the engineering workstation
input using the following cell name to develop labels for the design netlist:
CELL NAME
IPE05LH
IPF05LH
CELL LAVOUT
HOL LABEL
ASPECT RATIO
Label: IPF05LH A.TAP.V;
28.6
31.5
(/)
o
CELL AREA
TO NA210LH
minimum width
.c
«S
«S
RELATIVE
minimum height
en
II)
II)
...
FEATURES
NETLIST
II...
These input cells incorporate a pull-up tap to simplify termination of the input. This tap may be used in
conjunction with an active pull-up/pull-down terminator from the' ASC2370 through' ASC2374 group,
otherwise the pull-up tap may be left unconnected. When the terminator is used it ensures that the input
will be driven to a high or low logic level thereby avoiding exposure to a high-impedance or floating condition.
The cells incorporate circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
"'''''''gemem lecrmiques Tor me cell 10 recover Trom exposure to nlgn currents ot up to 400 milliamperes,
thereby negating most common sources that can produce a latch-up condition.
The SN54ASC5005 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5005 is characterized for operation from -40°C to 85°C.
Copyright © 1986. Texas Instruments Incorperated
PRODUCTION DATA documonts contain information
current as of publication date. Products conform to
specifications per the terms of Taxas Instruments
:'~~:~~i~a[::1~1i ~:~::i:; :1~O::;::::~:r~':" nat
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-489
SN54ASC5005, SN74ASC5005
TTL·COMPATIBLE INVERTING INPUT BUFFERS ·WITH PULL·UP TAP
electrical characteristics over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise noted)
PARAMETER
VT
Input threshold voltage
Vee
II
Input current
lee
Supply current
VI
V,
V,
IPE05LH
V,
V,
IPF05LH
ei
Cpd
SN54ASC5005
TVP
MAX
1.3
TEST CONDITIONS
Intrinsic input
=
=
=
=
=
Vee
capacitance t
=
5 V,
TA
dissipation capacitance
25°e
Vee or 0
Vee orO
2 V or O.B V
±1
905
1.21
Vee orO
2 V or O.B V
75B
1.21
=
5 V,
TA
Vee = 5 V,
TA = 25°e
Equivaleht power
=
tr
=
25°e
= tf =
SN74ASC5005
tvp
MAX
1.3
±1
54.3
1.13
45.5
1.13
UNIT
V
~A
nA
mA
nA
mA
2.1
2.1
pF
16
16
pF
3 ns,
trotal input capacitance is dependent on the package type and is equal to the sum of package capacitance and intrinsic input capacitance.
The value shown includes the pull-up tap.
switching characteristics over recommended ranges of supply voltage and operating free-ait temperature
(unless otherwise noted)
PARAMETER*
tpLH
tpHL
tpLH
tpHL
.l.tpLH
.l.tpHL
FROM
(INPUT)
A
TO
(OUTPUT)
V
A
V
A
V
TEST
CONDITIONS
eL
eL
=0
=
1 pF
SN54ASC5005
MIN TVP§ MAX
0.6
0.9
2
MIN
0.6
0.4
1.6
O.B
1
0.3
SN14ASC5005
TVP§ MAX
0.9
2.8
1.3
1.9
1.3
0.5
6.2
2.2
4.2
0.4
0.9
1.7
0.8
1
0.3
t Propagation delay times are measured from the 1.3 V point of VII 0 to 3 VI to the 44% pOint of Vo with tr
tpLH .. propagat;on delay time, low-to-high·level output
tpHL '" propagation delay time, high-to-Iow-Ievel output
.l.tpLH '" change in tpLH with load capacitance
.l.tpHL '" change in tPHL with load capacitance
§Typical values are at Vee = 5 V, TA = 25°e.
DESIGN CONSIDERATIONS
Refer to Section 7.
4-490
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 65~O' 2 • DALLAS, TEXAS 15265
= tf
0.9
0.9
2.8
1.3
1.9
0.4
2
1.3
5.5
2
3.8
0.8
UNIT
ns
ns
ns/pF
= 2 ns (10% and 90%1.
SN54ASC5006. SN74ASC5006
CMOS-COMPATIBLE NONINVERTING INPUT BUFFERS
02939, AUGUST 1986
SystemCell'"
2-/Am INPUT STANDARD CELL
logic symbol
•
Typical Propagation Delay with 1-pF Load
1.9 ns for the IPE01LH
1.1 ns for the IPF01 LH
•
Incorporates Circuitry to Protect Against
ESD and Latch-Up
.
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
A--t>--V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Ouality and
Reliability
FUNCTION TABLE
INPUT OUTPUT
A
V
H
H
L
L
positive logic equation
Y=A
description
The SN54ASC5006 and SN74ASC5006 are noninverting input buffer CMOS standard cells that buffer
CMOS input voltage levels to CMOS internal-cell voltage levels. This cell function eixsts in two versions
("E" and "F") with different physical implementations to allow the final IC area to be optimized. Since
the electrical performance of each version is identical, for simplicity only one version (the "F" cell) will
be contained in the engineering workstation cell libraries. Determination of the most appropriate cell version
will be made during the layout stage. The cell is designated and called from the engineering workstation
input using the following cell names to develop labels for the design netlist:
IPE01LH
IPF01LH
NETllST
CELL LAVOUT
HOL LABEL
ASPECT RATIO
Label: IPF01 LH A, V;
U)
CD
CD
.c
..
(/)
CO
CO
FEATURES
CELL NAME
II
..
RELATIVE
C
CELL AREA
TO NA210LH
minimum height
31
minimum width
31.5
The cells incorporate circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most common sources that can produce a latch-up condition.
The SN54ASC5006 is characterized for operation over the full military temperature range of - 55°C to
125°C, The SN74ASC5006 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 2 in Section 2.
PRODUCTION DATA documlnts ..ntain inlormati,,~
.u"••t .s 01 publi••tion d.te, Products •••Iomi 10
specifications par the terms of Taxas Instrumen~
standard warranty,. Production proclssing daes not
necessarily i~clud. testing of all parameters.
Copyright
TEXAS . "
INSTR.UMENTS
POST OFFICE BOX 655012! DALLAS. TEXAS 75265
Cl
1986. Texas Instruments Incorporated
4-491
SN54ASC5006, SN74ASC5D06
CMOS·COMPATIBLE NONINVERTING INPUT BUFFERS
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VT
Input threshold voltage
Vee = 5 V.
II
Input current
VI - Vec or 0
lec
Ci
epd
SN54ASC5006
TEST CONDITIONS
TYP
SN74ASC5006
MAX
TYP
2.5
TA - 25°e
MAX
UNIT
V
2.5
±1
±1
pA
rnA
IPE01LH
Vce or 0
VI
VI = 3.15 V or 0.9 V
1218
2.93
73.1
2.62
IPF01LH
VI = Vce or 0
VI = 3.15 V or 0.9 V
1353
Bl.2
nA
2.95
2.62
rnA
Supply current
Intrinsic input capacitance t
Vee = 5 V.
TA = 25°C
Equivalent power
VCC = 5 V.
tr = tf = 3 ns.
dissipation capacitance
TA = 25°C
nA
2
2
pF
3
3
pF
t Total input capacitance is dependent on the package type and is equal to the sum of package capacitance and intrinsic input capacitance.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise n o t e d ) '
.
IPE01LH
IIc
PARAMETER* .
tpLH
tpHL
...
D)
tpLH
CI)
tpHL
C/)
.o.tpLH
iCD
a
.o.tpHL
.FROM
TO
TEST
(INPUT!
(OUTPUT!
CONDITIONS
A
A
A
Y
CL
Y
CL
=0
=
1 pF
Y
SN54ASC5006
TYP§
MAX
MIN
0.9
1.7
3.7
1
1.7
1
1.9
SN74ASC5006
TYP§
MAX
MIN
1
1.7
3.4
3.3
1
1.7
3.1
4.1
1.1
1.9
3.B
1.1
1.9
3.7
1.1
1.9
3.4
0.07
0.2
0.5
0.09
0.2
0.4
0.1
0.2
0.5
0.1
0.2
0.4
UN1T
ns
ns
ns/pF
IPF01LH
PARAMETER*
tpLH
tpHL
tpLH
tpHL
.o.tPLH
.o.tpHL
FROM
TO
TEST
(INPUT)
(OUTPUT!
CONDITIONS
A
A
A
Y
Y
Y
eL
CL
=0
=
1 pF
SN54ASC5006
TYP§
MAX
MIN
0.5
0.7
0.2
0.7
1.2
0.7
1.2
0.7
1.5
0.3
0.7
1.4
1.1
1.9
0.7
1.1
1.8
0.5
1.1
2.3
0.6
1.1
2.1
0.2
0.4
0.7
0.2
0.4
0.6
0.2
0.4
0.9
0.2
0.4
O.B
* Propagation delay times are measured from the 50% point of VI to the 44% point of Vo with tr
tpLH " propagation delay time. low-to-high-Ievel output
tPHL " propagation delay time. high-to-Iow-Ievel output
.o.tpLH " change in tpLH with load capacitance
.o.tpHL " change in tpHL with load capacitance
§ Typical values are at VCC = V. T A = 25°e.
DESIGN CONSIDERATIONS
Refer to Section 7.
4-492
SN74ASC5006
TYP§
MAX
MIN
0.5
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
= tf = 4
UNIT
ns
ns
ns/pF
ns (10% and 90%).
SN54ASC5007, SN74ASC5007
TTL-COMPATIBLE NONINVERTING INPUT BUFFERS
02939, AUGUST 1986
SystemCell™
2-/Am INPUT STANDARD CELL
logic symbol
•
Typical Propagation Delay with 1-pF Load
2.1 ns for the IPE04LH and IPF04LH
1.6 ns for the IPF12LH
•
Incorporates Circuitry to Protect Against
ESD and Latch-Up
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
•
A~Y
FUNCTION TABLE
Functional Operation Over VCC Range of
2Vt06V
INPUT
OUTPUT
A
Y
H
H
L
L
Dependable Texas Instruments Quality and
Reliability
positive logic equation
Y=A
description
The SN54ASC5007 and SN74ASC5007 are non inverting input buffer CMOS standard cells that translate
TTL input voltage levels to CMOS internal-cell voltage levels. This cell function exists in two versions ("E"
and "F") with different physical implementations to allow the final IC area to be optimized. Since the
electrical performance of each version is identical. for simplicity only one version (the"F" cell) will be
contained in the engineering workstation cell libraries, Determination of the most appropriate cell version
will be made during the layout stage, The options are designated and called from the engineering workstation
input using the following cell names to develop labels for the design netlist:
FEATURES
CELL NAME
IPE04LH
IPF04LH
IPF12LH
NETLIST
CELL LAYOUT
HDL LABEL
ASPECT RATIO
Label: IPF04LH A,Y;
Label: IPF12LH A, Y;
a...
II)
CD
CD
.c
en
...caca
C
RELATIVE
CELL AREA
TO NA210LH
minimum height
28,6
minimum width
31.5
37.5
minimum width
The cells incorporate circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes.
thereby negating most common sources that can produce a latch-up condition,
Th .. SN54ASC5007 is characterized for oDeration over the full military temperature range of - 55°C to
125°C, The SN74ASC5007 is characterized for operation from - 40°C to 85 DC,
absolute maximum ratings and recommended operating conditions
See Table 2 in Section 2,
PRODUCTION DATA d...manls .ontain information
currant as of publication data. Products conform to
spacifications par the tarms of TaxIs Instruments
::,':':::i~ai~:I'::l~ ~:~:~i:r :I\"::"':=~:.s not
Copyright © 1986, Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-493
SN54ASC5007, SN74ASC5007
TTL-COMPATIBLE NONINVERTING INPUT BUFFERS
electrical characteristics over r.ecommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
=
VT
Input threshold voltage
Vee
II
Input current
VI - Vce or 0
lec Supply current
SN54ASC5007
TEST CONDITIONS
TA
5 V,
=
TYP
II
:l1li
....
UNIT
V
±1
±1
pA
nA
rnA
nA
rnA
VI - Vee or 0
VI - 2 V or 0.8 V
1040
1.21
62.4.
1.13
IPF04LH
VI - Vee or 0
VI - 2 V or 0.8 V
1307
78.4
1.2
1.13
IPF12LH
VI = Vce or 0
VI - 2 V or 0.8 V
1303
78.2
nA
3
2.81
rnA
Intrinsic input capacitance t IPF04LH
Vee
=
5 V,
TA
= 5 V,
= 25°e
Equivalent power
VCC
dissipation capacitance
TA
=
25°e
tr
=
tf
=
1.9
1.9
2.2
2.2
2.8
2.8
18
18
3 ns,
pF
pF
t Total input capacitance is dependent on the package type and is equal to the sum of package capacitance and intrinsic input capacitance.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
IPE04LH and IPF04LH
C
m
m
MAX
1.3
IPE04LH
IPF12LH
Cpd
TYP
1.3
25°C
IPE04LH
ei
SN74ASC5007
MAX
PARAMETERt
rn
tpLH
CD
CD
tpLH
tpHL
::r
....
tn
tpHL
dtpLH
dtpHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Y
A
Y
A
Y
eL
CL
=0
= 1 pF
SN54ASC5007
TYP§ MAX
MIN
0.8
1.3
1.2
2.3
1
SN74ASC5007
TYP§
MAX
2.5
MIN
0.8
1.3
2.3
5.4
1.3
2.3
4.8
1.6
3.2
1
1.6
3
1.4
2.6
6.2
1.5
2.6
5.5
0.1
0.3
0.8
0.1
0.3
0.7
0.1
0.3
0.8
0.1
0.3
0.8
SN54ASC5007
TYP§ MAX
MIN
UNIT
ns
ns
nsipF
IPF12LH
PARAMETER
tpLH
tpHL
tPLH
tpHL
dtpLH
dtpHL
*
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Y
CL = 0
A
Y
CL = 1 pF
A
Y
MIN
SN74ASC5007
TYP§
MAX
0.5
1.1
2
0.6
1.1
1.9
0.8
1.6
3.5
0.9
3.1
0.7
1.4
2.7
0.7
1.6
1.4
1
1.8
4.2
1
1.8
3.7
0.1
0.3
0.7
0.1
0.3
0.7
0.1
0.2
0.7
0.1
0.2
0.6
*Propagation delay times are measured from the 1.3 V point of VI (0 to 3 V) to the 44% point of Vo with tr '= tf
tpLH '" propagation delay time, low-to-high-Ievel output
tpHL ~ propagation delay time, high-to-Iow-Ievel output
dtpLH '" change in tpLH with load capacitance
dtpHL '" change in tpHL with load capacitance
§Typical values are at Vee = V, TA = 25°C.
DESIGN CONSIDERATIONS
Refer to Section 7.
4-494
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
2.5
UNIT
ns
ns
nSipF
= 2 ns (10% and 90%).
SN54ASC5010, SN74ASC5010
TTL-COMPATIBLE INVERTING SCHMITT-TRIGGER
INPUT BUFFERS WITH PULL-UP TAP
D2939, AUGUST 1986
SystemCell""
2-/-Im INPUT STANDARD CELL
•
7.5 ns Typical Propagation Delay with 1-pF
Load
•
Incorporates Circuitry to Protect Against
ESD and Latch-Up
•
Specified for Operation Over VCC Range of
4.5 V to 5.6 V
•
Functional Operation Over VCC Range of
2Vt06V
•
logic symbol
FUNCTION TABLE
Dependable Texas Instruments Quality and
Reliability
INPUT
OUTPUT
A
Y
H
L
L
H
positive logic equation
Y=A
description
The SN54ASC5010 and SN74ASC5010 are inverting Schmitt-trigger input buffer CMOS standard cells
that translate TTL input voltage levels to CMOS internal-cell voltage levels. This cell function exists in
two versions ("E" and "F") with different physical implementations to allow the finallC area tD be optimized.
Since the electrical performance of each version is identical, for simplicity only one version (the "F" cell)
will be contained in the engineering workstation cell libraries. Determination of the most appropriate cell
version will be made during the layout stage. The cell is designated and called from the engineering
workstation input using the following cell name to develop labels for the design netlist:
II
...
U)
Q)
Q)
.c
(f)
...mm
FEATURES
CELL NAME
IPE10LH
NETLIST
CELL LAYOUT
HDL LABEL
ASPECT RATIO
Label: IPF10LH A,TAP,Y;
IPF10LH
RELATIVE
C
CELL AREA
TO NA210LH
29.4
37.5
minimum height
minimum width
These input cells incorporate a pull-up tap to simplify termination of the input. This tap may be used in
conjunction with an active pull-up/pull-down terminator from the 'ASC2370 through 'ASC2374 group,
otherwise the pull-up tap may be left unconnected, When the terminator is used it ensures that the input
will be driven to a high or low logic level thereby avoiding exposure to a high-impedance or floating condition,
The cells incorporate circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts, Guard-ring structures are employed that provide current
,.
~.
ITlctIIClyt::lllt:lll ltH,';IIIIIl.jUt";:> lUI lilt;::
••
~t::11
.
~
LV I C\.iUV t:;:r
IIVIII
t:AIJU~UIC
LV
•••
III~II
.
r
. . . ,....,..
\.oUIIOIIL;" VI UtJ LV "'TVV
__ ... _ .__ . _ ." __
1IIIIIIglll"''OI~''',
~
thereby negating most common sources that can produce a latch-up condition.
The SN54ASC5010 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5010 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
PRODUCTION DATA doc.monts contaip information
currant as of publication date. Products conform to
specifications par the tarms of Texas Instruments
:'~~::~~i~8i~r:1~1~ ~~:~:; :....:::~~::.s not
Copyright
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
© 1986.. Texas Instruments Incorporated
4-495
SN54ASC5010, SN74ASC5010
TTL-COMPATIBLE INVERTING SCHMITT-TRIGGER
INPUT BUFFERS WITH PULL-UP TAP
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
VT+ Positive-going threshold level
VT- Negative-going threshold level
Vhys Hysteresis (VT + - VT-I
Input current
II
lee
e;
epd
SN54ASC5010
MIN
TYP
SN74ASC5010
MAX
MIN
TYP
MAX
1.5
1.8
2
1.5
1.8
2
0.6
0.9
1.1
0.6
0.9
1.1
900
-
900
UNIT
V
V
mV
±1
±1
~A
IPE10LH
VI - Vee orO
VI - 2 V or 0.8 V
1125
67.5
nA
1.47
1.37
rnA
IPF10LH
VI = Vee or 0
VI - 2 V or 0.8 V
1548
92.9
nA
1.45
1.37
rnA
Supply current
Intrinsic input capacitance t
VI - Vee or 0
Equivalent power
Vee = 5 V, TA = 25°e
Vee - 5 V, tr - t1 ~ 3 ns,
dissipation capacitance
TA = 25°e
2.1
2.1
pF
20
20
pF
trotal input capacitance is dependent on the package type and is equal to the sum of package capacitance and intrins"ic input capacitance.
The value shown includes the pull-up tap.
•
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER*
...o
tpLH
D)
tpHL
D)
tpLH
tpHL
.:l.tpLH·
(f)
::::r
CD
CD
...
(I)
.:l.tpHL
FROM
(lNPUTI
A
A
A
TO
TEST
(OUTPUTI
CONDITIONS
Y
Y
y
eL = 0
eL'= 1 pF
SN54ASC5010
TYP§
MAX
MIN
2.9
6
16
SN74ASC5010
TYp§
MAX
MIN
3.1
6
14
1.1
1.4
2.2
1.1
1.4
2
6.3
1.3
13
2
33
3.6
6.8
1.4
13
29
3.3
3.4
7
18
3.7
7
'0
0.2
0.6
1.5
0.2
0.6
1.3
2
UNIT
ns
ns
ns/pF
t Propagation delay times are measured from the 1.3 V pOint of VI (0 to 3 VI to the 44% point of Vo with tr = tf = 2 ns (10% and 90%1.
tpLH '" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
.:l.tpLH '" change in tpLH with load capacitance
.:l.tpHL '" change in tpHL with load capacitance
§Typical value.s are at Vee = 5 V, TA = 25°e.
DESIGN CONSIDERATIONS
Refer to Section 7.
4-496
TEXAS . .
INSTRUMENTS
POST OFFICE SOX 655012 • DALLAS, TEXAS 75265
SN54ASC5013, SN74ASC5013
TTL-COMPATIBLE NON INVERTING
INPUT BUFFERS WITH PULL-UP TAP
02939, AUGUST 1986
SystemCell™
2-/Am INPUT STANDARD CELL
•
2.1 ns Typical Propagation Delay With 1-pF
Load
•
Incorporates Circuitry to Protect Against
ESD and Latch-Up
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
•
logic symbol
TAP~
A--v- Y
""-
FUNCTION TABLE
Functional Operation Over VCC Range of
2Vt06V
Dependable Texas Instruments Quality and
Reliability
INPUT
OUTPUT
A
Y
H
H
L
L
positive logic equation
Y=A
description
The SN54ASC5013 and SN74ASC5013 are noninverting input buffer CMOS standard cells that translate
TTL input voltage levels to CMOS internal-cell voltage levels. The cell is designated and called from the
engineering workstation input' using the following cell name to develop labels for the design netlist:
4
...
U)
FEATURES
NETLIST
HOL LABEL
CELL LAYOUT
ASPECT RATIO
Label: IPF13LH A.TAP,Y;
minimum height
CELL NAME
IPF13LH
Q)
Q)
RELATIVE
.c
CELL AREA
en
TO NA210LH
...
29.4
C'CS
This input cell incorporates a pull-up tap to simplify termination of the input. This tap may be used in
conjunction with either an active pull-up/pull-down terminator from the' ASC2370 through' ASC2374 group,
otherwise the pull-up tap may be left unconnected. When the terminator is used it ensures that the input
will be driven to a high or low logic level thereby avoiding exposure to a high-impedance or floating condition.
C'CS
C
The cell incorporates circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most common sources that can produce a latch-up condition.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
Copyright © 1986. Texas Instruments Incorporated
PRODUCTION DATA documonls contain info,mation
curfant as of publication data. Products conform to
spacifications per the tarms of Taxas Instruments
=~:~i~ai~:1~7i ~.:\::i:; :.r::::::~:~~ not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-497
SN54ASC5013, SN74ASC5013
TTL·COMPATIBLE NONINVERTING
INPUT BUFFERS WITH PULL·UP TAP
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) .
... ,
PARAMETER
SN54ASC5013
TEST CONDITIONS
VT
Input threshold voltage
Vee - 5 V,
II
Input current
VI - Vee or 0
lee
Supply current
VI - Vee or 0
VI - 2 V or 0.8 V
ei
Input capacitance t
Equivalent power
Cpd dissipation capacitance
TYP
SN74ASC5Q13
MAX
TYP
1.3
TA - 25°e
Vee - 5 V,
TA - 25°e
tr
tf
:$
UNIT
V
±1
±1
1037
62.2
1.13
1.21
l> V,
vee
TA = 25°e
N!~X
1.3
p.A
nA
2.2
2.2
rnA
pF
1B
lB
pF
ns,
tTotal input capacitance is dependeflt on the package type and is equal to t~~ sum 9f package capacitance and intrinsic input capacitanc~.
switching characteristics over recommended ranges of supply voltage and operating free-air temperatlJre
(unless otherwise noted)
.
PARAMETER;
tPLH
tPHL
•
tpLH
tpHL
l1tpLH
C
I»
r+
I»
en
::r
CD
CD
r+
l1tpHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Y
A
Y
A
Y
eL
eL
tpropagation delay times are measured from VI
tpLH
5:
propagation delay time,
=0
= 1 pF
SN54ASC5013
TYP§ MAX
MIN
O.B
1.3
2.4
O.B
1.3
2.3
1.3
2.3
5.3
1.3
4.7
1
1.6
3.2
1
2.3
1.6
1.4
2.6
6.1
1.5
2.6
5.4
0.1
0.3
0.8
0.1
0.·3
0.7
0.1
0.3
O.B
0.1
0.3
0.8
= 1.3 V to the 44% point of Vo with tr = tf = 2 ns (10%
low-to-higr-!~vel
output
tpHL .. propagation delay time, high-to-!ow-Ievel OUtput
l1tpLH '" change intpLH with load capacitance
l1tpHL .. change in tpHL with load capacitance
§Typical values are at Vee = 5 V, TA = 25°e.
til
DESIGN CONSIDERATIONS
Refer to Section 7.
4-498
SN74Ase5013
TYP§ MAX
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
MIN
2.9
and 90%1.
ns
ns
ns/pF
SN54ASC5100, SN74ASC5100
TTL-leMOS-COMPATIBLE OUTPUT BUFFERS
D2939. AUGUST 1986
SystemCell™
•
Typical Propagation Delays
2.7 ns with 15-pF load
4.7 ns with 50-pF load
•
Output Current Ratings
SN54ASC5100 IOl
IOH
SN74ASC5100 IOl
IOH
2-/lm OUTPUT STANDARD CELL
logic symbol
A-t>-V
3.4 rnA
-3.4 rnA
4mA
-4mA
FUNCTION TABLE
INPUT
•
Incorporates Circuitry to Protect Against
ESD and latc!1-Up
•
Specified for Operation Over Vee Range of
4.5 V to 5.5 V
•
Functional Operation Over Vee Ranlle of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
OUTPUT
A
V
H
L
H
L
•
positive logic equation
...
Y=A
tI)
CI)
CI)
description
The SN54ASC51 00 and SN74ASC51 00 are noninverting output buffer standard cells that interface internal
cells with TTL or CMOS external loads. This cell function exists in two versions ("E" and "F") with different
physical implementations to allow the final IC area to be optimized. Since the electrical performance of
each version is identical, for simplicity only one version (the "F" cell) will be contained in the engineering
workstation cell libraries. DeterminatiOn of the most appropriate cell version will be made during the layout
stage. The cell is designated and called from the engineering workstation input using the following cell
name to develop labels for the design netlist:
.c:
o
...a:sa:s
C
FEATURES
CELL NAME
OPE40LH
OPF40LH
NETLIST
CELL LAVOUT
HDL LABEL
ASPECT RATIO
Label: OPF40LH A,V;
minimum height
minimum width
RELATIVE
CELL AREA
TO NA210LH
31.8
39
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most common sourCIlS that can produce a latch-up condition.
These output cells have been designed to provide low-impedance drive levels for both the high- and lowlogic-level states. As a result, passive resistance has been omitted in series with the output transistors.
Shorting a high-level output to ground or a low-level output to Vee will cause current flow ab.ove that
recommended fqr normal opeation. Therefore. it is recommended that outputs not be shorted directly to
ground or Vee.
Copyright © 1986, Texas Instruments Incorporated
PRODUCTION DATA documents conlain inlo"'8lion
current 8S of publication date. Products ,!=onform to
specili""lions par Ihe lerms 01 Tex@llnslrume.ts
standard warranty. Pradu~ion .,fucesling does not
n......rily include teelillll 01 .~ parameters.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
4-499
SN54ASC5100, SN74ASC5100
TTL·/CMOS·COMPATIBLE OUTPUT BUFFERS
The dynamic drive capability of each output is specified by the delta propagation delay time parameter
included with the switching characteristics. The delta delay times provide a means for making direct
comparisons of the various output responses with changes in capacitive loading.
The SN54ASG51 00 is chatacterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5100 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended, operating conditions
See Table 3 in Section 2. The maximum high-level or low-level output current is 3.4 milliamperes for the
SN 54ASC 51 00 and 4 milliamperes for the SN 7 4ASC 51 00.
electrical characteristics over recommended ranges of .supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VT
TEST CONDITIONS
Input threshold voltage
•
!D)
lee
Supply current
ej
Input capacitance
Equivalent power
epd
U)
::T
CD
CD
...
IOL
2.2
V
3.7
V
Vee- 0.1
Vee- 0.1
0.5
0.5
V
0.1
0.1
tOPE40LH
See Note 1
IOL
Vee':" 4.5Vto5.5V,
1563
93.8
IOPF40LH
VI = Vee orO, TA = Minto Max
1988
119
lOPE40LH
dissipation capacitance IOPF40LH
Vee
=
5 V,
Vee = 5 V,
TA = 25°e
= 25°e
= tf = 3 ns,
TA
0.7
0.7
tr
9.1
9.1
10.9
10.9
NOTE 1: These limits apply when all other outputs are open.
(I)
4-500
UNIT
3.7
= 4 mA
= 3.4 mA
= 20 p.A,
IOL
VOL Low-level output voltage
SN74ASC5100
M'IN
TYP MAX
2.2
Vee
VOH High-level output voltage
c
TA = 25°e
= 5 V,
IOH = -4 mA
IOH -: ,-3.4 mA
IOH - - 20 p.A, See Note 1
SN54ASC5100
MIN
TYP MAX
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
nA
. pF
pF
SN54ASC5100, SN74ASC5100
TTL-/CMOS-COMPATIBLE OUTPUT BUFFERS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
TTL loads
PARAMETERt
tpLH
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONOITIONS
MIN
TYP*
MAX
MIN
TYP*
MAX
CL - 15 pF,
1
1.9
4.1
1.1
1.9
3.7
A
Y
RL
tPHL
tpLH
A
CL
Y
RL
tpHL
<1tpLH
A
=
=
SN54ASC5100
SN74ASC5100
00
1.8
3.7
8.7
1.9
3.7
7.8
50 pF,
1.5
2.9
6.6
1.7
2.9
5.9
=
3.3
6.9
16.2
3.7
6.9
10
30
SO
10
30
14.3
70 .
40
90
210
50
90
190
00
Y
<1tPHL
UNIT
ns
ns
ps/pF
CMOS loads
PARAMETERt
tpLH
FROM
TO
TEST
INPUT
OUTPUT
CONDITIONS
MIN
TYP*
MAX
MIN
TYP*
MAX
CL-15pF,
1.2
2.4
5.3
1.3
2.4
4.S
A
Y
tpHL
tpLH
A
Y
tPHL
<1tPLH
A
SN54ASC5100
1.6
3
7.1
1.7
3
6.3
CL - 50 pF,
2.2
4.4
9.9
2.4
4.4
9
=
2.5
5.1
12.2
2.7
5.1
10.7
30
60
130
30
60
120
30
60
150
30
60
130
RL =
RL
00
00
Y
<1tPHL
tpropagation delay times are measured from the 44% point of V, with tr = tf
at Vo = 1.3 V. For CMOS loads, the times end at the 50% point of VO.
tPLH '" propagation delay time, low-to-high-Ievel output
tPHL == propagation delay time. high-to· low-level output
<1tpLH .. change in tpLH with load capacitance
.6.tpHL
change in tpHL with load capacitance
=
UNIT
ns
ns
ps/pF
3 ns (10% and 90%). For TTL loads, the times end
=
tTypical values are atVcc = 5V, TA
SN74ASC5100
...
U)
(1)
(1)
.c
(I)
...
CO
CO
= 25°C.
C
DESIGN CONSIDERATIONS
Refer to Section 7.
TEXAS . "
INSTRUME~TS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-501
...c
Q)
Q)
en
::::r
CD
CD
...en
4-502
SN54ASC5103, SN74ASC5103
TTL-/CMOS-COMPATIBLE OUTPUT BUFFERS
D2939, AUGUST 1986
System~eIrM 2-/lm OUTPUT STANDARD CELL
•
Typical Propagation Delay
2.4 ns with 1S-pF Load
3,S ns with SO-pF Load
•
Output Current Ratings
SNS4ASCS103 IOL
IOH
SN74ASCS103 IOL
IOH
•
logic symbol
S.1 mA
-S,1 mA
6 mA
-6 mA
FUNCTIOI\I TABLE
Incorporates Circuitry to Protect Against
ESD and Latch-Up
•
Specified for Operation Over VCC Range of
4.S V to S.S V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
INPUT
OUTPUT
A
V
H
H
L
L
•
positive logic equation
...
Y=A
U)
CI)
CI)
description
The SN54ASC5103 and SN74ASC5103 are noninverting output buffer standard cells that interface CMOS
internal cells with TTL or CMOS external loads, This cell function exists in two versions ("E" and "F")
with different physical implementations to allow the final IC area to be optimized. Since the electrical
performance of each version is identical. for simplicity only one version (the "F" cell) will be contained
in the engineering workstation cell libraries. Determination of the most appropriate cell version will be made
during the layout stage, The cell is designated and called from the engineering workstation input using
the following cell name to develop labels for the design netlist:
.c
CI)
...
C
FEATURES
NETLIST
CELL NAME
OPE60LH
OPF60LH
HOL LABEL
Label: OPF60LH A,V;
CELL LAVOUT
ASPECT RATIO
RELATIVE
CELL AREA
TO NA210LH
minimum height
43
minimum width
40.5
I ne celis Incorporate CirCUlI elerTlen15 aesigneo 10 ClCllvelY Dypass ano UIS51pcne tUt:;l{;[fUSnHIC uisc;iH:::Irges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes.
thereby negating most common sources that can produce a latch-up condition.
These output cells have been designed to provide low-impedance drive levels for both the high- and lowlogic-level states. As a result. passive resistance has been omitted in series with the output transistors.
Shorting a high-level output to ground or a low-level output to Vee will cause current flow in excess of
that recommended for normal operation. Therefore. it is recommended that outputs not be shorted directly
to ground or VCC.
PRODUCTION DATA dD.umants .Dntain information
current as of publication data. Products conform to
spacifications par the terms of Texas Instruments
:'~=~~i~8i~:1~1i =:~ti:r :.r::::::~~~ not
Copyright © 1986. Texas Instruments tnc-y
GZ~
FUNCTION TABLE
Incorporates Circuitry to Protect Against
ESD and Latch·Up
INPUTS
raz---A
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vto6V
•
Dependable Texas Instruments Quality and
Reliability
OUTPUT
y
L
H
L
L
H
L
H
X
Z
•
positive logic equation
...
Y = A (when GZ is L)
U)
Q)
Q)
description
The SN54ASC51 04 and SN74ASC51 04 are noninverting3-state output buffer standard-cells that interface
internal cells with TTL or CMOS external buses, This cell function exists in two versions ("E" and "F")
with different physical implementations to allow the final IC area to be optimized. Since the electrical
performance of each version is identical. for simplicity only one version (the "F" cell) will be contained
in the engineering workstation cell libraries, Determination of the most appropriate cell version will be made
during the layout stage. The cell is designated and called from the engineering workstation input using
the following cell name to develop labels for the design netlist:
.c
en
...
CO
CO
C
FEATURES
NETLIST
CELL NAME
OPE63LH
OPF63LH
CELL LAYOUT
HDL LABEL
ASPECT RATIO
Label: OPF63LH A,GZ,Y;
minimum height
minimum width
RELATIVE
CELL AREA
fo
NA210LH
51
49.2
The cells incorporate circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-rihg structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes.
thereby negating most common sources that can produce a latch-up condition.
These output cells have been designed to provide iow-impedance drive levels for both the high- and lowlogic-level states; therefore. passive resistance has been omitted in series with the output transistors,
Shorting a high-level output to ground or a low-level output to Vce will cause current flow in excess of
that recommended for normal operation. Therefore. it is recommended that outputs not be shorted directly
to ground or VCC.
PRODUCTION DATA documants .. ntain inlormation
carrent IS af publicition data. Products conform to
spacifications par the tarms af Texas Instruments
:.~=~~;;ai~::ri
=::i:r lIi°:=~.::9t::a~s not
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE '£lOx 65501 ~ • DALLAS. TEXAS 75265
4-507
SN54ASC5104, SN74ASC5104
TTL-/~""OS-COMPATlbL~ 3-STATE OUTPUT BUFFERS
descriptil,ln (c:ontinued)
The dynamic drive capability of each output is specified by the delta propagation delay time parameter
that is included with the switching characteristics. The delta propagation delay times provide a means
fOr making direct comparispns of the various output responses with change in capacitive loading.
The SN54ASC51 04 is characterized for pperation over the full military temperature range of - 55°C to
125°C. The SN74ASC5104 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended I,lperating conditions
See Table 3 in Section 2 and the 10 test conditions shown in the electrical characteristics. The maximum
low-level Qr high-level Qutput current is 5.1 milliamperes for the SN54ASC5104 and 6 milliamperes for
the SN74ASC5104.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless "tjlerwise noted)
PARAMETER
VT
TEST CONDITIONS
Input threshold voltage
low-lev~1
output voltage
10H -
-5.1 mA
20 pA See Note 1
IOH 10l - 6 mA
IOl'- 5.1 mA .
10l - 20 pA,
10Z Off-state output current
ICC
Supply current
Ci
I~put
'Cpd
capacitance
Equivalent power
OPE63lH
OPF63lH
A
GZ
OPE63lH
diss'ipation capacitance OPF63lH
TYP
Vec - 5 V,
TA
=
=
UNIT
V
V
Vee 0.1
0.5
0.5
25°C
t r - tf - 3 ns,
25°C
V
0.1
0.1
±10
±5
3145
189
3039
182
1
1
0.7
0.7
17.1
17.1
19.4
19.4
NOTE 1: These limits apply when all other outputs are open.
4-508
MAX
3.7
See Note 1
TA
TYP
2.2
Vee 0.1
VI = VCC or 0,
TA = MIN to MAX
= ? V,
SN74ASC5104
MIN
3.7
Vo - VCC or 0
VCC .4.5 V to 5.5 V,
VCC
MAX
2.2
TA - 25°C
VCC - 5 V,
IOH - -6 mA
VOH !'iigh-Ievel output voltage
VOL
SN54ASC5104
MIN
TEXAS •
INSTRUMENTS
POST OFFiCE BOX 655012 • DALLAS, TEXAS 75265
~A
nA
pF
pF
SN54ASC5104, SN74ASC5104
TTL-/CMOS-COMPATIBLE 3-STATE OUTPUT BUFFERS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
TTL loads. CL - 15 pF
PARAMETERt
tpLH
tpHL
tpZH
tpZL
FROM
TO
TEST
IINPUTI
(OUTPUT!
CONDITIONS
A
Y
RL =
y
GZ
SN54ASC5104
SN74ASC5104
MIN
TYP*
MAX
MIN
1
1.6
2
3.3
2.8
3
4.5
1.1
7.8
1.7
6.6
1.3
7.1
1.6
00
RL - 1 kO to GND
1.2
RL - 1 kO to Vee
1.5
TYP*
2
MAX
3.3
2.8
3
6.9
4
6
6.4
UNIT
ns
ns
TTL loads. CL - 50 pF
PARAMETERt
tpLH
tpHL
tpZH
tpZL
tpHZ
tpLZ
FROM
IINPUTI
TO
(OUTPUTI
A
Y
SN74ASC5104
MIN TYP* MAX
1.4
2.7
6.3
1.5
2.7
5.6
5.2
12.7
2.6
5.2
11.1
1 kO to GND
1.5
3.5
8.4
1.7
3.5
7.6
RL - 1 kO to Vee
2.4
5.2
12.6
2.6
5.2
11
RL
=
=
=
00
1 kO to GND
10
10
RL - 1 kO to Vee
9
9
RL
Y
GZ
SN54ASC5104
MIN TYP*
MAX
2.4
RL
y
GZ
TEST
CONDITIONS
UNIT
ns
ns
ns
change in propagation delay time with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
TTL loads
PARAMETERt
--Y
FUNCTION TABLE
Incorporates Circuitry to Protect Against
ESD and Latch-Up
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
INPUT
OUTPUT
A
Y
H
H
L
L
positive logic equation
Y=A
description
The SNS4ASCS1 OS and SN74ASCS1 05 are non inverting output buffer standard cells that interface CMOS
internal cells with a passive pull-up external load. This cell function exists in two versions ("E" and "F")
with different physical implementations to allow the final IC area to be optimized. Since the electrical
performance of each version is identical, for Simplicity only one version (the "F" cell) will be contained
in the engineering workstation cell libraries. Determination of the most appropriate cell version will be made
during the layout stage. The cell is designatec;i and called from the engineering workstation input using
the following cell name to develop labels for the design netlist:
--
FEATURES
CELL NAME
OPE61LH
OPF61LH
NETLIST
CELL LAYOUT
HDL LABEL
ASPECT RATIO
Label: OPF61 LI-> A,V;
RELATIVE
CELL AREA
TO NA210LH
minimum height
31
minimum width
40
The cells incorporate circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ran!;!in!;! up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most common sources that can produce a latch-up condition.
These output cells have been designed to provide low-impedance drive levels for low-logic-level outputs
interfacing a bus having a terminated high-level drive source. As a result, passive resistance has been omitted
in series with the output transistor. Shorting the low-level output to VCC will cause current flow in excess
of that recommended for normal operation. Therefore, it is recommended that outputs not be shorted directly
to VCC.
The dynamic drive capability of each output is specified by the delta propagation delay time parameter
included with the switching characteristics. The delta delay times provide a means for making direct
comparisons of the various output responses to increased capacitive loading.
PRODUCTION DATA documonts contain information
current as of publication date. Products conform to
specifications per the terms of Taxas Instrumants
:'::~~:~~i;ai~r:I~~i ~!:t1:~i:;. :....:.~:~9t::a~s
not
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-S11
SN54ASC5105, SN74ASC5105
TTL-/CMOS-COMPATIBLE OPEN-DRAIN OUTPUT BUFFERS
description (continued)
The SN54ASC51 05 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5105 is characterized for operation from -40°C to 85°C.
absolute maximum ratings. and recommended operating conditions
See Table 3 in Section 2. Maximum low-level output current is 5.1 milliamperes for the SN54ASC51 05
and 6 milliamperes for the SN74ASC5105.
, electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
TEST CONDITIONS
PARAMETER
VT
Input threshold voltage
VOL Low-level output voltage
IOZ
Off~state
ei
Equivalent power IOPE61 LH
epd dissipation
capacitance
Vee = 5 V,
iOPF61LH TA = 25°e
MAX
UNIT
v
2.2
V
0.1
±10
±5
1192
63.8
1
1
3.8
3.8
4
4
TA = 25°e
tr = tf = 3 ns,
71.5
,
1063
IOPF61LH TA = MIN to MAX
Vee = 5 V,
TYP
0.1
Vo - Vee or 0
IOPE61LH Vee - 4.5 V to 5.5 V, VI - Vee or 0,
Input capacitance
MIN
0.5
See Note 1
output current
lee Supply current
MAX
0.5
IOL - 6 mA
IOL - 5.1 mA
IOL - 20 "A,
I
TYP
2.2
TA - 25°e
Vee - 5 V.
SN74ASC5105
SN54ASC5105
MIN
"A
nA
pF
pF
NOTE 1: These limits apply when all other outputs are open.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
TTL loads
PARAMETERt
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
eL = 15 pF.
tpZL
A
y
tpZL
A
y
tpLZ
A
AtpZL
A
y
y
RL = 1 kll to Vee
eL - 50 pF,
RL = 1 kll to Vee
SN54ASC5105
Typt
MAX
MIN
TYpt
MAX
MIN
SN74ASC5105
UNIT
1
2
4,7
1.1
2
4,2
ns
1.9
4
9.8
2,1
4
8.6
ns
130
ps/pF
8
RL - 1 kll to Vee
30
60
8
ns
150
30
SN54ASC5105
Typt
MAX
MIN
Typt
MAX
3.5
1
1.6
3,2
60
CMOS loads
PARAMETERt
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
tpZL
A
Y
tpZL
A
Y
AtpZL
A
Y
eL=15pF,
RL = 1 kllto Vee
eL - 50 pF,
RL = 1 kll to Vee
MIN
SN74ASC5105
UNIT
0.9
1.6
1,5
2.9
7
1.6
2,9
6,1
ns
20
37
100
20
37
80
ps/pF
ns
tPropagation delay times are measured from the 44% pOint of VI with tr = tf = 3 ns (10% and 90%1. For TTL loads, the times end
at Vo = 1.3 V. For eMOS loads, the times end at the 50% point of VO,
tpZL .. output enable time to low level
tPLZ '" output disable time from low level
AtpZL
5ii
change in tpZl with load capacitance
; Typical values are at Vee = 5 V, TA = 25°e.
4-512
TEXAS •
INSTRUMENTS
POS1 O!=Fice BOX. 665012 • DALLAS, TEXAS 15265
SN54ASC5106, SN74ASC5106
TTL-/CMOS-COMPATIBLE OUTPUT BUFFERS
02939, AUGUST 1986
SystemCell™
•
Typical Propagation Delays
2 ns with 15~pF Load
2,8 ns with 50-pF Load
•
Output Current Ratings
SN54ASC5106 IOL
IOH
SN74ASC5106 IOL
IOH
•
2-/Am OUTPUT STANDARD CELL
logic symbol
A---f>-V
8.5 rnA
-8.5 rnA
10 rnA
-10 rnA
FUNCTION TABLE
INPUT
Incorporates Circuitry to Protect Against
ESD and Latch-Up
•
Specified for Operation Over Vec Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2 V to 6 V
•
Dependable Texas Instruments Quality and
Reliability
OUTPUT
A
V
H
H
L
L
•
positive logic equation
...
Y=A
U)
Q)
Q)
description
The SN54ASC51 06 and SN74ASC51 06 are noninverting output buffer standard-cells that interface CMOS
internal cells with TTL or CMOS external loads. This cell function exists in two versions ("E" and "F")
with different physical implementations to allow the final IC area to be optimized. Since the electrical
performance of each version is identical, for simplicity only one version (the "F" cell) will be contained
in the engineering workstation cell libraries. Determination of the most appropriate cell version will be made
during the layout stage. The cell is designated and called from the engineering workstation input using
the following cell name to develop labels for the design netlist:
.s::.
o
...caca
C
FEATURES
CELL NAME
OPEOOLH
OPFOOLH
NETLIST
CELL LAVOUT
HDL LABEL
ASPECT RATIO
Label: OPFOOLH A,V;
minimum height
minimum width
RELATIVE
CELL AREA
TO NA210LH
47.7
42
The cells incorporates circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that proviqll current
management techniques for the cell to recover from exposure to high currents of up to 400 miiliamperes;
thereby negating most common sources that can produce a latch-up condition.
These output cells have been designed to provide low-impedance drive levels for both the high- and lowlogic-level states. As a result, passive resistance has been omitted in series with the output transistors.
Shorting a high-level output to ground or a low-level output to VCC will cause current flow in excess of
that recommended for normal operation. Therefore, it is recommended that outputs not be shQ'1ed directly
to ground or VCC.
Copyright © 1986. Texas Instruments Incorporated
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
:~~~~:~~i~ai~:I~~e ~!:~:~ti:f :.~O::;::~:~~ not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-513
SN54ASC5106, SN74ASC5106
TTL·/CMOS·COMPATIBLE OUTPUT BUFFERS
The dynamic drive capability of each output is specified by the delta propagation delay time parameter
included with the switching characteristics. The delta propagation delay times provide a hlelihS for milking
direct comparisons of the various output responses with change in capacitive loading.
The SN54ASC5106 is characterized for operation over the full military temperature range of - 55 DC to
125 DC. The SN74ASC5106 is characterized for operation from -40 DC to 85 DC.
absolute maximum ratings and recommended operating conditions
See Table 3 in Section 2 and the 10 test conditions shown in the electrical characteristics. The maximum
low-level or high-level output current is 8.5 milliamperes for the SN54ASC5106 and 10 milliamperes for
the SN74ASC5106.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VT
Input threshold voltage
Vee
=
IOH VOH I-ii~h-Ievel output voltage
•
VOL Low-level output voltage
o
C»
.....
C»
lee Supply current
ei
epd dissipation
capacitance
(D
.....
(I)
MIN
TYP
Vee = 5 V,
10I'FOOLH TA = 25°e
TYP
MAX
UNIT
V
3.7
Vee
See Note 1
V
Vee
0.1
0.1
_ 0.5
V
0.5
See Note 1
v,
VI - Vee or 0,
0.1
0.1
2933
176
2590
MAX
TA
tr
=
25°e
= tf =
3 ns,
TEXAS
155
1.4
1.4
21.8
21.8
20.1
20.1
NOTE 1: These limits apply when all other outputs are open.
4-514
SN74ASC5106
MIN
2.2
2.2
25°e
IOL - 8.5 mA
= MINto
Vee = 5 V,
MAX
3.7
8.5 mA
IOH 20 ~A.
IOH 10l. - 10 mA
IOPFOOLH TA
I
=
TA
5 V.
-10 mA
IOL - 20 ~A,
IOPEOOLH Vee - 4.5 V to 5.5
Equivalent power OPEOOLH
t/)
i"
Input capacitance
SN54ASC5106
TEST CONDITIONS
~
INSTRUM~NTS
POST OFFICE BOX 655012-· OALLAS, TEXAS 75265
nA
pF
pF
SN54ASC5106, SN74ASC5106
TTL-/CMOS-COMPATIBLE OUTPUT BUFFERS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
TTL loads
PARAMETERt
tpLH
tpHL
tpLH
tpHL
AtPLH
AtPHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
MIN
A
Y
CL - 15 pF,
RL ~ '"
CL - 50 pF
=
A
A
Y
RL
co
SN54ASC5106
SN74ASC5106
MAX
MIN
0.8
TYP*
1.5
3.2
0.9
TYP*
1.5
1.2
2.6
5.7
1.3
2.6
2.9
5.1
1.1
2
4.4
1.2
2
4
1.8
3.7
8.5
1.9
3.7
7.6
10
14
40
10
14
30
20
31
80
20
31
70
Y
MAX
UNIT
ns
ns
ps/pF
CMOS loads
PARAMETERt
tpLH
tpHL
tpLH
tpHL
AtPLH
AtPHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
MIN
TYP*
MAX
MIN
TYP*
MAX
CL - 15 pF,
0.9
1.9
4
1
1.9
3.6
RL = co
CL - 50 pF,
1.2
2.2
4.8
1.3
2.2
4.4
1.4
2.7
1.5
5.6
6.1
A
A
A
Y
Y
RL
=
co
SN54ASC5106
SN74ASC5106
1.6
3
6.2
6.8
1.7
2.7
3
10
23
60
10
23
60
10
23
60
10
23
50
Y
UNIT
ns
ns
ps/pF
tpropagation delay times are measured from the 44% point of VI with tr = tf = 3 ns (10% and 90%). For TTL loads, the times end
at Vo = 1.3 V. For CMOS loads, the times end at 50% point of VO.
tpLH '" propagation delay time, low-to-high-Ievel output
II
en
t)
CD
tpHL := propagation delay time, high-to-Iow-Ievel output
AtpLH '" change in tpLH with load capacitance
AtPHL '" change in tpHL with load capacitance
'Typical values are at VCC = 5 V, TA = 25°C.
.c
en
DESIGN CONSIDERATIONS
...caca
C
Refer to Section 7.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-515
III
4-516
SN54ASC5107, SN74ASC5107
TTL·/CMOS·COMPATIBLE 3·STATE OUTPUT BUFFERS
02939, AUGUST 1986
SystemCell™ 2·llm OUTPUT STANDARD CELL
•
Typical Propagation Delays
2,7 ns with 15-pF Load
3.7 ns with 50-pF Load
•
Output Current Ratings
SN54ASC5107 IOL
IOH
SN74ASC5107 IOL
IOH
•
logic symbol
A-----f>- Y
GZ~'
8.5 rnA
-8.5 rnA
10 rnA
-10 rnA
FUNCTION TABLE
INPUTS
Incorporates Circuitry to Protect Against
ESD and Latch-Up
Vee
•
Specified for Operation Over
4.5 V to 5.5 V
•
Functional Operation Over
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
Vec
Range of
OUTPUT
GZ
A
Y
L
H
H
L
L
L
H
X
Z
Range of
II
..
positive logic equation
Y = A (when GZ is L)
tI)
CD
CD
description
The SN54ASC51 07 and SN74ASC51 07 are non inverting 3-state output buffer standard cells that interface
CMOS internal cells with TTL or CMOS external buses. This cell function exists in two versions ("E" and
"F") with different physical implementations to allow the finallC area to be optimized. Since the electrical
performance of each version is identical, for simplicity only one version (the "F" cell) will be contained
in the engineering workstation cell libraries. Determination of the most appropriate celi version will be made
during the layout stage. The cell is designated and called from the engineering workstation input using
the following celi name to develop labels for the design netlist:
.c
..
o
CO
CO
C
FEATURES
CELL NAME
OPE03LH
OPF03LH
NETLIST
CELL LAYOUT
HOL LABEL
ASPECT RATIO
Label: OPF03LH A,GZ,Y;
minimum height
minimum width
RELATIVE
CELL AREA
TO NA210LH
54
52.4
The celis incorporate circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the celi to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most common sources that can produce a latch-up condition.
These output cells have been designed to provide low-impedance drive levels for both the high- and lowlogic-level states. As a result, passive resistance has been omitted in series with the output transistors.
Shorting a high-level output to ground or a low-level output to VCC will cause current flow in excess of
that recommended for normal operation. Therefore, it is recommended that outputs not be shorted directly
to ground or Vee.
PRODUCTION DATA do.umenll contain informetion
currant 81 of publication date. Products confarm to
specifi.ations per the tarms of Texas Instruments
=~~:~~i;;at::I:ri =:~ti:r IIr:::~9t::'S no~
Copyright @ 1986, Texas Instruments "Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 6615012 • DALLAS. TEXA~ 75265
4-517
SN54ASC5107. SN74ASC5107
TTL-/CMOS-COMPATIBLE 3-STATE OUTPUT BUFFERS
description (continued)
The'dynamic drive capability of each output is specified by the .delta propagation delay time parameter
included with the switching characteristics, The delta propagation delay times provide a means for making
direct comparisons of the various output responses with change in capacitive loading.
The SN54ASC51 07 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5107 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 3 in Section 2. The maximum low-level or high-level output current is 8.5 milliamperes for the
SN54ASC5107 and 10 milliamperes for the SN74ASC5107.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VT
Input threshold voltage
VOH High-level output voltage
II
...c
CI)
CI)
en
::r
...en
SN54ASC5107
TEST CONDITIONS
Vee
=
=
MIN
5 v,
-10 mA
TA
=
-20 pA,
See Note 1
MAX
SN74ASC5107
MIN
TYP
2.2
25°e
IOL
IOL
10Z
Off-state output current
lee
Supply current
ei
CD
CD
V
Vee- O.1
0.5
A
capacitance
GZ
epd dissipation
capacitance
2OI'A,
Vee
=
5 V,
OPE03LH Vce = 5 V,
OPF03LH TA = 25°e
V
0.5
8,5 mA
0,1
See Note 1
Vo - Vee or 0
OPE03LH Vee = 4,5 V to 5,5 V, VI
OPF03LH TA = MIN to MAX
Input
Equivalent power
=
=
UNIT
V
3,7
Vee- D,l
IOL - 10 mA
VOL Low-level output voltage
MAX
2.2
3.7
IOH IOH = -8.5 mA
IOH
TYP
=
TA
tr
Vee or 0,
=
25°e
= tf =
3 ns,
0.1
±10
±5
3483
209
3318
199
1.1
1,1
0.7
0,7
19.9
19,9
23.2
23.2
I'A
nA
pF
pF
NOTE 1: These limits apply when all other outputs are open.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
TTL loads, CL - 15 pF
PARAMETERt
tpLH
tpHL
tpZH
tpZL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
GZ
Y
y.
RL =
00
SN74ASC5107
MAX
MIN
4.8
1.2
TYP*
2.1
MAX
1.1
TYi>*
2.1
4.3
1.5
3.3
8,2
1.6
3.3
7,3
RL' = 1 kll to GND
1.2
2.8
6,8
1.3
2.8
6,2
RL - 1 kll to Vec
1.4
3.1
7.3
1.5
3.1
6.5
tpropagation delay times are measured from the 44% point of VI with tr
at Vo = 1.3 V,
tpLH '" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-,o-Iow-Ievel output
tpZH '" output enable time to high level
tpLZ " output disable time from low level
* Typical values are at VCC = 5 V, T A = 25°C.
4-518
SN54ASC5107
MIN
= tf =
UNIT
ns
ns
3 ns (10% and 90%1. For TTL loads, the times end
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC5107. SN74ASC5107
TTL-/CMOS-COMPATIBLE 3-STATE OUTPUT BUFFERS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (continued)
.
TTL loads, CL = 50 pF
PARAMETERt
tpLH
tpHL
tpZH
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Y
GZ
Y
RL
=
SN54ASC5107
00
SN74ASC5107
MIN
TYP*
MAX
MIN
TYP*
MAX
1.4
2.7
6.5
1.5
2.7
5.7
2.2
4.7
11.6
2.4
4.7
10.3
RL - 1 kG to GND
1.5
3.5
8.5
1.7
3.5
7.6
Vee
2.2
4.7
11.2
2.4
4.7
10
=
tpZL
RL
tpHZ
RL - 1 kG to GND
10
10
Vee
8
8
tpLZ
GZ
y
RL
=
1 kG to
1 kG to
UNIT
ns
ns
ns
change in propagation delay time with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
PARAMETERt
.:I.tpLH
.:I.tpHL
.:I.tpZH
.:I.tpZL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
GZ
SN54ASC5107
SN74ASC5107
MIN
TYP*
MAX
MIN
TYP*
MAX
10
17
50
10
17
40
20
40
100
20
40
90
10
20
50
10
20
40
20
46
110
20
46
100
Y
Y
UNIT
ps/pF
ps/pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
CMOS loads, CL
PARAMETERt
tpLH
tpZH
tpZL
CMOS loads, CL
PARAMETERt
tpLH
tpHL
tpZH
tpZL
....
U)
G)
G)
= , 5 pF
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Y
GZ
Y
tpHL
•
SN54ASC5107
.c
SN74ASC5107
MIN
TYP*
MAX
MIN
TYP*
MAX
1.2
2.5
5.9
1.3
2.5
5.3
1.5
2.9
7.1
1.5
2.9
6.3
RL - 1 kG to GND
1.7
3.3
7.6
1.8
3.3
6.8
Vee
1.3
2.6
6.1
1.4
2.6
5.5
RL
RL
=
=
00
1 kG to
tn
UNIT
....COCO
ns
C
ns
50 pF
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Y
GZ
Y
SN54ASC5107
SN74ASC5107
MIN
TYP*
MAX
MIN
TYP*
MAX
1.7
3.5
8.3
1.9
3.5
7.4
1.9
3.9
9.6
2
3.9
8.5
RL - 1 kO to GND
2.2
4.3
10.1
2.3
4.3
9.1
Vee
1.9
3.8
9
2
,3.8
8
RL =
00
RL - 1 kG to
UNIT
ns
ns
TPropagation delay times are measured from the 44% point of VI with tr = tf = 3 ns (10% and 90%). For TTL loads, the times end at
Va = 1.3 V. For eM as loads, the times end at the 50% point of Va.
tpLH = propagation delay time, low-to-high-Ievel output
.:I.tpLH = change in tpLH with load capacitance
tpHL = propagation delay time, high-to-Iow-Ievel output
dtpHL == change in tpHL with load capacitance
tpZH = output enable time to high level
.:I.tpZH = change in tpZH with load capacitance
tpZL == output enable time to low level
AtpZL ;;;;: change in tpZL with load capacitance
tpHZ
output disable time from high level
tPLZ == output disable time from low level
'Typical values are at Vee = 5 V, TA = 25 ce.
=
TEXAS
l!1
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
4-519
SN54ASC5107, SN74ASC5107
TTL·/CMOS·COMPATIBLE 3·STATE OUTPUT BUFFERS
change in propagation delay time with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
CMOS loads
PARAMETERt
.1tpLH
AtpHL
.1tPZH
.1tpZL
FROM
(INPUT)
TO
(OUTPUT)
A
Y
GZ
TEST
CONDITIONS
y
tpropagation delay times are measured from the 44% pOint of VI with tr
at the 50% point of VO .
.1tpLH .. change in tpLH with load capacitance
.1tpHL '" change in tpHL with load capacitance
.1tpZH '" change in tpZH with load capacitance
.1tpZL '" change in tpZL with load capacitance
*Typical values are at VCC = 25°C, T A = 25°C.
III
SN54ASC5107
TYP*
MAX
MIN
TYP*
MAX
10
29
10
29
70
70
10
10
29
29
60
10
29
'70
10
29
70
20
34
80
20
34
70
= tf = 3
DESIGN CONSIDERATIONS
Refer to Section 7.
II)
II)
en
:::r
...en
CD
CD
TEXAS •
INSTRUMENTS
post OFFICE
70
UNIT
ps/pF
ps/pF
ns (10% and 90%). For CMOS loads, the times end
...c
4-520
SN74ASC5107
MIN
BOX 65.6012 • OAb.b.AS, TEXAS 75266
SN54ASC5108. SN74ASC5108
TTL-/CMOS-COMPATIBLE OPEN-DRAIN OUTPUT BUFFERS
D2939. AUGUST 1986
SystemCeIrM
•
Typical Propagation Delays
1.7 ns with 15-pF load
3 ns with 50-pF load
•
Output Current Ratings
SN54ASC5108 IOl = 8.5 mA
SN74ASC5108 lOt = 10 mA
2-/Am OUTPUT STANDARD CELL
logic symbol
A--I>-V
•
FUNCTION TABLE
INPUT
Incorporates Circuitry to Protect Against
ESD and latch-Up
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
OUTPUT
A
V
H
H
L
l
positive logic equation
Y=A
a...
en
description
The SN54ASC51 08 and SN74ASC51 08 are noninverting output buffer standard-cells that interface CMOS
internal cells with a passive pull-up external load. This cell function exists in two versions ("E" and "F")
with different physical implementations to allow the final IC area to be optimized. Since the electrical
performance of each version is identical, for simplicity only one version (the "F" cell) will be contained
in the engineering workstation cell libraries. Determination of the most appropriate cell version will be made
during the layout stage. The cell is designated and called from the engineering workstation input using
the following cell name to develop labels for the design netlist:
Q)
Q)
.c
en
!CO
o
FEATURES
CELL NAME
OPEOl lH
OPF01 lH
NETlIST
CELLLAVOUT
HOl LABEL
ASPECT RATIO
label: OPFOl lH A.V;
RELATIVE
CELL AREA
TO NA210LH
minimum height
31.8
minimum width
42
The cells incorporate circuit elements designed to actively bypass and dissipate electrostatic discharges
.... ,i+h ..... ,,+ ......... +; .... 1.................. : .............. + .... A 1,:'..., ...... ,-4- ....
.. .." .. ..J .. : ...........
...... .." ............ "..-.. ..... , ............ ..4 +1-. .... +
.. '"' ••
-. ...... ,,_+
-.. _..
'-";;;:1"';::1
-r..
- - - , ........ :;, ......
'f"" .... , ................ ,.. ........ ""''-'
................ " ..
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most common sources that can produce a latch-up condition.
~
r---~.'-.-.-
-~
~"'~.~.-~.
+~."....,+.,
u
~
:....I~
........ _ .... • . . . . . . . . . . . . . . . . . . . . . . . . .
These output cells have been designed to provide low-impedance drive levels for low-logic-level outputs
interfacing a bus having a terminated high-level drive source. As a result, passive resistance has been omitted
in series with the output transistor. Shorting the low-level outpu't to VCC will cause current flow in excess
of that recommended for normal operation. Therefore, it is recommended that outputs not be shorted directly
to VCe.
The dynamic drive capability of each output is specified by the delta propagation delay time parameter
included with the switching characteristics. The delta propagation delay times provide a means for making
direct comparisons of the various output responses with change in capacitive loading.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~ai~:1~1e ~!~~~~ti~fn :llo::~:~9t:~~s not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1986, Texas Instruments Incorporated
4-521
SN54ASC51 08i .SN74ASC511J8
TIL·/CMOS·COMPATIBLE OPEN·bRAIN OUTPUT BUFFERS
The SN54ASC51 Of! ill Characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5108 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 3 in SeCtion 2 and the 10 test conditions shown in the electrical characteristics. Maximum lowlevel ou~put current is 8.5 milliamperes for the SN54ASC510S and 10 milliamperes for the SN74ASC51 OS.
electrical characteristics over recommended ranges of suply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VT
Input threshold voltage
VCC ~ 5 V.
TA
~
SN74ASC5108
SN54ASC5108
TEST CONDITIONS
MIN
TYP
MAX
MIN
2.2
25°C
TYP
See Note 1
•
C
m
m
...
tn
:r
CD
CD
...en
Equivalent powerlOPEOl LH
Cpd dissipation
capacitance
0.1
±10
±5
1302
78.1
1193
71.6
VCC
~
5 V,
TA = 25°C
1.4
1.4
VCC
~
5 V,
tr = tf = 3 ns,
5.6
5.6
5.S
5.S
IOPF01 LH TA = 25°C
NOTE 1: These limits apply when
V
0.1
Vo - VCC or 0
10Z Off-state output current
IOPE01LH VCC - 4.5 V to 5.5 V, VI - VCC or 0,
Supply
current
ICC
IOPF01LH TA = MIN to MAX
Input capacitance
V
0.5
10L - 8.5 rnA
10L - 20 ~A,
Ci
UNIT
0.5
IOL - 10 rnA
VOL Low-level output voltage
MAX
2.2
~A
nA
pF
pF
ail other outputs are open.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
TTL loads
PARAMETERt
FROM
(INPUT(
TO
TEST
(OUTPUT)
CONDITIONS
SN54ASC51OS
CL - 15 pF,
tPZL
A
Y
tpZL
A
y
tpLZ
dtpZL
A
y
A
Y
FROM
(INPUT(
TO
TEST
(OUTPUTI
CONDITIONS
CL - 15 pF,
RL = 1 kll to Vcc
CL - 50 pF,
RL = 1 kll to
RL = 1 kll to
Vct
Vcc
SN74ASC510S
UNIT
MIN
TYP*
MAX
MIN
TYP*
MAX
0.9
1.7
3.7
0.9
1.7
3.3
ns
3
6.S
1.5
3
6
ns
80
ps/pF
1.4
7.2
10
7.2
37
90
20
ns
37
CMOS loads
PARAMETERt
tpZL
A
y
tpZL
A
y
dtpZL
A
Y
RL = 1 kO to Vec
CL - 50 pF,
RL
=
1 kO to VCC
tpropagation delay times are measured from· the 44% point of V, with tr = tf
at Vo = 1.3 V. For CMOS loads, the times end at the 50% pOint of VO.
tPZL '" output enable time to low level
tpLZ ~ output disable time from low level
dtpzL '" change in tpZL with load capacitance
* Typical values are at VCC = 5 V, T A ~ 25°C.
4-522
SN54ASC510B
SN74AsC51OS
UNIT
MIN
TYP*
MAX
MIN
TYP*
MAX
O.S
1.4
2.9
O.S
1.4
2.S
1.2
2.2
5
1.:i
2.2
4.5
ns
10
23
so.
10
23
50
pslpF.
=3
ns
ns (10% and 90%), For TTL loads, the times end
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 6550'2 • DALLAS, tEXAS 75265
SN54ASC5109, SN74ASC5109
TTL-/CMOS-COMPATIBLE OPEN-DRAIN OUTPUT BUFFERS
D2939, AUGUST 1986
SystemCell™
logic symbol
•
Typical Propaglltion Delay
2.7 ns with 15-pF Load
6 ns with 50-pF Load
•
Output Current Ratings
SN54ASC5109 IOL - 3.4 mA
SN74ASC5109 IOL - 4 mA
•
2-,..m OUTPUT STANDARD CELL
A---t>-V
FUNCTION TABLE
INPUT
Incorporates Circuitry to Protect Agllinst
ESD arid Latch-Up
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
OUTPUT
A
V
H
H
L
L
positive logic equation
Y = A
description
a...
fI)
The SN54ASC51 09 and SN74ASC51 09 are noninverting output buffer standard cells that interface CMOS
internal cells with a passive pull-up external load. This cell function exists in two versions ("E" and "F")
with different physical implementations to allow the final IC area to be optimized. Since the eillctrical
performance of each version is identical, for simplicity only qne versjo[1 (the "F" cell) will be contained
in the engineering workstation cell libraries, Determination of the mOllt appropriate cell version will be made
during the layout stClge. The cell is designated and called from the engineering workstation input using
the following cell name to develop labels for the design netlist:
CD
CD
.c
en
...caca
C
FEATURES
CELL NAME
OPE41LH
NETLIST
CELL LAVOUT
HDL LABEL
ASPECT RATIO
Label: OPF41 LH A, V;
OPF41LH
RELATIVE
CELL AREA
TO NA210LH
27.8
39
minimum height
minimum width
The cells incorporate circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts, Guard-ring structures are employed that provide current
management tecrmiques Tor me cell to recover Hom exposure to "'gn currents OT up to 4UU milliamperes,
thereby '1eg!!ting most common sources thilt can produce a latch-up condition.
These OLjtput cells have been designed to provide low-impedance drive levels for low-logic-level outputs
interfacing a bus having a terminated high-level drive source, As a reSUlt, passive resistilnce has been omitted
in series with the outP\.lt transistor. Shorting the low-level output to VCC will cause current flow in excess
of that recommended for normal operation. Therefore, it is recommended that outputs not be shorted directly
to VCC.
The dynamic drive capability of each output is specified by the delta propagation delay time PClrameter
included with the switching characteristics. The delta propagation delClY times provide a means for making
direct comparisons of the various output responses with change in capacitive loading.
PRODUCTION DATA do.....n...oniain information
Gurrent as 01 publiution dita. Products .0.lorm to
per \_ terms· sf rexas Instruments
i:: :'i:;:::::':~~
==:i~ai~:1~7i
sp.&:ifi~tionl
t:g::
nDt
. T~XAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright ©
i 986,
Texas Instruments Incorporated
4-523
SN54ASC5109, SN74ASC5109
TTL-/CMOS-COMPATIBLE OPEN-DRAIN OUTPUT BUFFERS
description (continued)
The SN54ASC51 09 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5109 is characterized for operation from -40°C to 85°C.
.
absolute maximum ratings and recommended operating conditions .
See Table 3 in Section 2. Maximum low-level output current is 3.4 milliamperes for the SN54ASC51 09
and 4 milliamperes for the SN74ASC5109.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VT
SN54ASC5109
TEST CONDITIONS
Input threshold voltage
Vee
10L
VOL Low-level output voltage
= 5 V,
= 4 mA
MIN
TYP
Equivalent powerlOPE41LH
epd dissipation
capacitance
See Note 1
Vee
=
5 V,
TA
Vee
=
5 V,
tr
=
MAX
2.2
UNIT
V
0.5
10L - 3.4 mA
IOPF41 LH TA
TYP
0.5
=
0.1
±10
±5
1052
63.1
1037
25°e
= tf =
V
0.1
Vo = Vee or 0
10Z OffRstate output current
IOPE41LH Vee - 4.5 V to 5.5 V, VI - Vee or 0,
lee Supply current
iOPF41LH TA = MIN to MAX
Input capacitance
MIN
2.2
TA - 25°e
IOL - 20 pA,
ei
SN74ASC5109
MAX
3 ns,
25°e
62.2
0.7
0.7
2.4
2.4
2.6
2.6
pA
nA
pF
pF
NOTE 1: These limits apply when all other outputs are open.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
.
(unless otherwise noted I
TTL loads
PARAMETERt
tpZL
FROM
(INPUT)
A
TO
(OUTPUT)
SN54ASC5109
TEST
CONDITIONS
eL - 15 pF,
Y
RL
= 1 kll to V CC
CL - 50 pF,
tpZL
tpLZ
A
Y
AtpZL
A
Y
PARAMETERt
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
tpZL
A
Y
RL
=
SN74ASC5109
MIN
TYP*
MAX
MIN
TYP*
1.3
2.7
2.8
6
6.5
1.4
2.7
5.7
14.5
3.1
6
12.5
230
50
9.6
1 kll to V CC
40
90
MAX
9.6
90
200
UNIT
ns,
ns
ps/pF
CMOS loads
tpZL
A
Y
AtpZL
A
y
CL
RL
=
=
SN54ASC5109
15 pF,
1 kll to VCC
CL - 50 pF,
RL
=
1 kll to VCC
tpropagation delay times are measured from the 44% point of VI with tr = tf
at Vo = 1.3 V. For CMOS loads, the times end at the 50% point of Vo.
tPZL '" output enable time to low level
tPLZ '" output disable time from low level
AtpZL '" change in tpZL with load capacitance
*Typical values are at VCC = 5 V, TA = 25°C.
4-524
TEXAS
SN74ASC5109
MIN
TYP*
MAX
MIN
TYP*
MAX
1.1
2
4.8
1.2
2
4.3
UNIT
ns
2.1
4
10
2.2
4
8.7
ns
30
57
150
30
57
130
ps/pF
=
3 ns (10% and 90%). For TTL loads, the times end
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN54ASC511D, SN74ASC511D
TTL·/CMOS·COMPATIBLE NONINVERTING 3·STATE OUTPUT BUFFERS
D2939. AUGUST 1986
SystemCelr
M
2'/lm OUTPUT STANDARD CELL
•
Typical Propagation Delay
3.4 ns with 15-pF Load
6.2 ns with 50·pF Load
•
Incorporates Circuitry to Protect Against
ESD and Latch-Up
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
•
logic symbol
:=£>-v
FUNCTION TABLE
INPUTS
OUTPUT
Functional Operation Over VCC Range of
2 V to 6 V
G
A
Y
H
H
H
Dependable Texas Instruments Quality and
Reliability
H
L
L
X
Z
L
positive logic equation
Y = A (when G is H)
Y is at a high impedance when G is low.
description
•
The SN54ASC5 1 10 and SN74ASC51 10 are non inverting 3-state output buffer standard cells that interface
internal cells with TTL or CMOS external loads. This cell function exists in two versions ("E" and "F")
with different physical implementations to allow the final IC area to be optimized. Since the electrical
performance of each version is identical, for simplicity only one version (the "F" cell) will be contained
in the engineering workstation cell libraries. Determination of the most appropriate cell version will be made
during the layout stage. The cell is designated and called from the engineering workstation input using
the following cell name to develop labels for the design netlist:
FEATURES
NETLIST
HOL LABEL
CELL NAME
OPE42LH
OPF42LH
Label: OPF42LH A,G, Y;
CELL LAYOUT
ASPECT RATIO
....asas
C
RELATIVE
CELL AREA
TO NA210LH
minimum height
38.1
minimum width
45
The cell incorporates circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most common sources that can' produce a latch-up condition.
PRODUCTION DATA d••umanls contain informat,on
currant a. of publication data. Product. conform to
spacifications par the terms of Texas Instruments
:=~i~li~:1~1i ~!::\::i:fn lI~O:::::~:~~ not
Copyright © 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4·525
SN54ASC5110, SN74ASC5110
TTL-/CMOS-COMPATIBLE NONINVERTING 3-STATE OUTPUT BUFFERS
These output cells have been designed specifically to provide low-impedance drive levels for both the highand low-logic-level states. Therefore, passive resistance has been omitted in series with the output
transistors. Shorting of a high-level output to ground or a. low-level output to Vcc will cause current flow
in excess of that recommended for normal operation. Therefore, it is recommended that outputs not be
shorted directly to ground or VCC.
The dynamic drive capability of each output is specified by the delta propagation delay time parameter
included with the switching characteristics. The delta delay times provide a means for making direct
comparisons of the various output responses with change in capacitive loading.
The SN54ASC511 0 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5110 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 3 in Section 2 and the 10 test conditions shown in the electrical characteristics. The maximum
high-level or low-level output current is 3.2 milliamperes for the SN54ASC511 0 and 4 milliamperes for
the SN74ASC5110.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
II
c
D)
r+
VT
Input threshold voltage
IOH VOH High-level output voltage
r+
IOH
5 V,
TA
=
MIN
VOL Low-level o'utput voltage
=
IOZ
lee
ei
Supply current
Input capacitance
Equivalent power
epd
OPF42LH
A
G
OPE42LH
dissipation capacitance OPF42LH
VI
=
Vee
5 V,
Vee = 5 V,
TA = 25°e
UNIT
V
V
Vee· 0-. 1
0.4
V
0.4
See Note 1
TA
tr
=
25°e
= tf =
3 ns,
0.1
0.1
±10
±5
1962
2317
118
139
0.6
0.6
0.5
0.5
8.6
8.6
10.5
10.5
NOTE 1: These limits apply when all other outputs are open.
4-526
MAX
3.7
Vee or 0
=
TYP
2.2
Vee 0.1
Vo - Vee or 0
OPE42LH
SN74ASC5110
MIN
3.7
IOL - 3.2 mA
Off-state output current
MAX
2.2
25°e
-3.2 mA
IOL - 20 ~A,
(I)
TYP
-4 mA
IOH - -20 ~A, See Note 1
IOL - 4 mA
(J)
CD
CD
=
Vce
D)
::r
SN54ASC5110
TEST CONDITIONS
PARAMETER
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
~A
nA
pF
ns
SN54ASC5110, SN74ASC5110
TTL-/CMOS-COMPATIBLE NONINVERTING 3-STATE OUTPUT BUFFERS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
TTL loads, CL
~
PARAMETERt
tpLH
tpHL
tpLH
tpHL
tpZH
tpZL
tpHZ
tpLZ
TO
TEST
(OUTPUT)
CONDITIONS
G
tpZL
PARAMETERt
FROM
liN PUT)
A
tpZH
TTL loads, CL
15 pF
~
1.3
TYP*
2.3
MAX
MIN
1.4
2.4
TYP*
2.3
MAX
4
2.2
4.5
4.4
8.8
4.5
7.8
1 k[J to GND
1.3
2.4
4.5
1.4
2.4
4.1
RL - 1 k[J to Vcc
2.7
5.2
10.4
2.9
5.2
9
TEST
CONDITIONS
MIN
SN54ASC5110
TYP;
MAX
MIN
Y
RL
RL
y
SN74ASC5110
SN54ASC5110
MIN
=
= '"
UNIT
ns
ns
50 pF
FROM
IINPUT)
A
G
G
TO
(OUTPUT)
Y
RL = '"
y
Y
SN74ASC5110
TYP; MAX
1.9
3.7
7.2
2
3.7
6.5
4.3
8.8
17.2
4.7
8.8
15
RL - 1 k[J to GND
1.9
3.8
7.4
2
3.8
6.6
RL - 1 k[J to V CC
RL - 1 k[J to GND
4.8
9.8
20
5.3
9.8
17.2
RL
10
10
10
10
1 k[J to Vee
UNIT
ns
ns
ns
change in propagation delay time with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
PARAMETERt
Ll.tPLH
Ll.tPHL
Ll.tpZH
Ll.tPZL
IINPUT)
FROM
TO
(OUTPUT)
A
Y
G
TEST
CONDITIONS
y
UNIT
...
ps/pF
.c
U)
SN74ASC5110
SN54ASC5110
MIN
TYP*
MAX
MIN
TYP;
MAX
20
40
80
20
40
70
60
123
240
70
123
212
20
40
80
20
40
70
60
131
270
70
131
230
Q)
Q)
en
...
CO
CO
ps/pF
tPropagation delay times are measured from the 44% pOint of VI with tr = tf = 3 ns (10% and 90%). For TTL loads, the times end
at Va = 1.3 V.
tpLH '" propagation delay time, low-to· high· level output
Ll.tpLH '" change in tpLH with load capacitance
tpHL '" propagation delay time, high-to-Iow·level output
Ll.tpHL '" change in tpHL with load capacitance
tpZH '" output enable time to high level
Ll.tpZH '" change in tpZH with load capacitance
tPZL " output enable time to low level
Ll.tpZL '" change in tpZL with load capacitance
tpHZ " output disable time from high level
tpLZ '" output disable time from low level
*Typical values are at Vec = 5 V, T A = 25°C.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
II
C
4-527
SN54ASC5110, SN74ASC5110
TTL·/CMOS·COMPATIBLE NONINVERTING 3·STATE OUTPUT BUFFERS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
CMOS loads, CL - 15 pF
PARAMETERt
tPLH
tpHL
tpZH
tpZL
FROM
(INPUT)
TO
(OUTPUT)
A
Y
G
TEST
CONDITIONS
TYP*
SN74ASC5110
MAX
MIN
TYP*
MAX
1.5
3
5.8
1.6
3
5.2
3.8
3.2
7.9
2
RL - 1 kll to GND
1.9
1.6
6
1.7
3.8
3.2
5.4
1 kll to Vee
2
4.4
9.3
2.1
4.4
8.2
RL =
y
SN54ASC5110
MIN
RL
00
7
UNIT
ns
ns
CMOS loads, CL - 50 pF
PARAMETERt
tpLH
FROM
(INPUT)
A
tpHL
tpZH
tpZL
II
~
C
-y
Gz--1l.
FUNCTION TABLE
INPUTS
Incorporates Circuitry to Protect Against
ESD and Latch-Up
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
OUTPUT
GZ
A
Y
L
H
H
L
L
L
H
X
Z
•
positive logic equation
...
tn
Y = A (when GZ is L)
CD
CD
description
.c
The SN54ASC5111 and SN74ASC5111 are noninverting 3-state output buffer standard cells that interface
CMOS internal cells with TTL or CMOS external buses. This cell function exists in two versions ("E" and
"F") with different physical implementations to allow the finallC area to be optimized. Since the electrical
performance of each version is identical, for simplicity only one version (the "F" cell) will be contained
in the engineering workstation cell libraries. Determination of the most appropriate cell version will be made
during layout stage. The cell is designated and called from the engineering workstation input using the
following cell name to develop labels for the design netlist:
FEATURES
NETLIST
CELL NAME
OPE43LH
OPF43LH
HOL LABEL
Label: OPF43LH A. GZ. Y;
RELATIVE
CELL LAYOUT
ASPECT RATIO
CELL AREA
TO NA210LH
minimum height
38
minimum width
45
I ne celis Incorporate circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most common sources that can produce a latch-up condition.
These output cells have been designed to provide low-impedance drive levels for both the high- and lowlogic-level states; therefore, passive resistance has been omitted in series with the output transistors.
Shorting a high-level output to ground or a low-level output to VCC will cause current flow in excess of
that recommended for normal operation. Therefore, it is recommended that outputs not be shorted directly
to ground or VCC.
PRODUCTION DATA documonts contain information
current 8S of publication date. Products conform to
specifications per the terms of Texas Instruments
:'::~:~~i~ai~:1~7i ~:~:~ti:; lIiO;::::::t:~~S not
Copyright @ 1986, Texas Instruments Incorporated
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-529
C/)
...
CO
CO
C
SN54ASC5'1',SN74ASC51"
TTL·/CMOS·COMPATIBLE 3·STATE OUTPUT BUFFERS
description (continued)
The dynamic drive capability of each output is specified by the delta propagation delay time parameter
included with the switching characteristics. The delta propagation delay times provide a means for making
direct comparisons of the various output responses with change in capacitive loading.
The SN54ASC5111 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5111 is characterized for operation from - 40°C to 85 DC.
absolute maximum ratings and recommended operating conditions
See Table 3 in Section 2 and the 10 test conditions shown in the electrical characteristics. The maximum
low-level or high-level output current is 3.4 milliamperes for the SN54ASC51 1'1 and 4 milliamperes for
the SN74ASC5111.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
.
PARAMETER
VT
II
Input threshold voltage
VOH High-level output voltage
Vee
10H
10H
= 5 V,
= -4 mA
= -3.4 mA
10H -
lee
ei
Supply current
10L
Input capacitance
Equivalent power
epd dissipation
capacitance
OPE43LH
OPF43LH
= 5 V,
=
UNIT
V
V
Vee- O.I
0.5
See Note 1
= vee
V
0.1
0.1
±10
±5
119
1982
or 0,
2334
TA
5 V,
tr
= 25°e
= tl =
3 ns,
25°e
NOTE I: These limits apply when all other outputs are open.
4-530
2.2
Vee- O.1
= MIN to MAX
Vee
TA
MAX
0.5
TA
=
TYP
3.7
OPF43LH
Vee
SN74ASC5111
MIN
2.2
See Note ·1
-20 pA,
Vo = Vee or 0
vee = 4.5 V to 5.5 V,V,
G2
MAX
3.7
OPE43LH
A
TYP
TA = 25°e
10L - 20 pA,
Off-state output current
MIN
= 4 mA
= 3.4 mA
10L
VOL Low-level output voltage
102
SN64ASC6111
TEST CONDITIONS
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALl.AS, TEXAS 75265
140
0.6
0.6
0.4
0.4
10.3
10.3
10.9
10.9
pA
nA
pF
pF
SN54ASC5111, SN74ASC5111
TTL·/CMOS·COMPATIBLE 3·STATE OUTPUT BUFFE~S
switching characteristics over recommended ranges of supply voltage and operating free·air telT!perature
(unless otherwise noted)
,
TTL loads. CL
PARAMETERt
tpLH
tpHL
tpZH
tpZL
TTL loads. CL
PARAMETERt
tpLH
a
15 pF
FROM
TO
TEST
(lNPUTI
(OUTPUT)
CONDITIONS
A
Y
GZ
Y
SN54ASC5111
TYP*
MAX
MIN
TYP*
MAX
1.3
2.4
5.6
1.4
2.4
5
4.5
11.3
3.3
8
2.2
1.6
4.5
1 kg to GND
2.1
1.5
3.3
10
7.2
RL - 1 kg to Vec
2
4.5
11.6
2.2
4.5
10.2
RL
RL
~
~ 00
tpZL
tPHZ
tpLZ
UNIT
ns
ns
50 pF
FROM
(lNPUTI
TO
A
Y
GZ
Y
SN54ASC5111
Typt
MAX
TEST
CONDITIONS
(OUTPUT)
RL
~
MIN
00
tPHL
tpZH
SN74ASC5111
MIN
GZ
1.8
3.5
8.5
1.9
3.5
7.6
3.8
8
19.7
4.2
8
17.3
2
4.4
10.9
2.1
4.4
9.8
3.9
8.3
21
4.2
8.3
18.2
RL - 1 kg to GND
Y
SN74ASC5111
MIN TYpt
MAX
RL
~
1 kg to Vee
RL
~
1 kg to GND
11
11
RL - 1 kg to Vec
10
10
UNIT
ns
ns
ns
change in propagation delay times with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
PARAMETERt
IItPLH
IItpHL
IItpZH
IItpZL
FROM
(INPUTI'
TO
(OUTPUT)
A
Y
GZ
y
TEST
SN54ASC5111
CONDITIONS
MIN
tpropagation delay times are measured from the 44% point of VI with tr
at Vo ~ 1.3 V.
.
tpLH == propagation delay time, low-to-high-Ievel output
tPHL '" propagation delay time, high-to-Iow-Ievel output
tPZH '" output enable time to high level
tpZL !!5 output enable time to low level
tpHZ '" output disable time from high level
tpLZ 55 output disable time from low level
*Typical values are at Vee ~ 5 V, TA ~ 25°e.
.atpLH
iii
~
tf
TYP*
MIN
TYP*
10
31
80
20
31
!\IIAX
70
50
100
240
50
100
210
10
31
80
20
31
70
50
lQ9
280
60
109
230
~
....CD
U)
SN74ASC5111
MAX
a
UNIT
CD
.c
ps/pF
(/)
....asas
ps/pF
3 ns (10% and 90%). For TTL loads, the times end
0
change in tpLH with load capacitance
IItPHL '" change in tpHL with load capacitance
IItpZH " change in tpZH with load capacitance
.a~PZL == change in tpZL with load capacitance
~
TEXAS
INSTRUM~NTS
POST OFF!CE BOX 655012 • OAl,.lAS, TEXAS 75265
4-53'1
•
SN54~SC5111, SN74ASC5111
TTL-/CMOS-COMPATIBLE 3-STATE OUTPUT BUFFERS
switching ciharacteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
CMOS loads. CL - 15 pF
PARAMETERt
tp~H
tpHL
tpZH
tpZL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Y
GZ
Y
SN54ASC5111
SN14ASC5111
1.5
3
MAX
' 7.1
3,7
9,3
RL - 1 kO to GND
1.8
2
4
9.3
1.9
2.2
= 1 kO to V CC
1.7
3.6
9.2
1.9
RL
RL
= 00
MIN
TYP*
MAX
MIN
1.6
3
6.3
3.7
4
8.3
8,3
3.6
8,2
TYP*
UNIT
ns
ns
CMOS loads. CL - 50 tlF
PARAMETERt
tpLH
tpHL
tpZH
tpZL
'.
FROM
(INPUT)
A
GZ
TO
(OUTPUT)
Y
Y
TEST
CONDiTIONS
RL =
00
SN54ASC5111
MIN
TYP*
2.5
5
SN74ASC5111
MAX
11.9
MIN
2.7
TYP*
5
MAX
10.6
2.9
6
6
3.1
3,2
13.4
3
15.3
14,2
6
RL - 1 kO to GND
6
12.7
Ri. - 1 kO to V CC
2.9
6
15.6
3.1
6
13.7
UNIT
ns
ns
change in propagation delay times with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
:l1li
PARAMETERt
C
&»
....
&»
en
::r
:
....
rn
AtpLH
AtpHL
AtPZH
AtpZL
FROM
TO
TEST
'(INPUT)
(OUTPUT)
CONDITIONS
A
Y
GZ
Y
SN54ASC5111
MIN
SN74ASC5111
TYP*
57
MAX
MIN
TYP*
MAX
130
30
57
120
170
30
66
150
30
66
57
130
130
69
180
30
40
57
30
69
160
30
30
UNIT
ps/pF
ps/pF
t Propagation delay times are measured from the 44% point of VI with tr = tf = 3 n5 (10% and 90%). For CMOS loads, the times end
at 50% point of Va.
tPLH '" propagation delay time, low-to-high-Ievel output
.1tpLH '" change in tPLH with load capacitance
.1tpHL '" change in tpHL with load capacitance
tpHL '" propagation delay time, high-to-Iow-Ievel output
tpZH '" output enable time to high level
.1tpZH '" change in tpZH with load capacitance
tpZL '" output enable time to low level
.1tpZL '" change in tPZL with load capacitance
* Typical values are at V CC = 5 V, TA = 25°C.
DESIGN CONSIDERATIONS
Refer to Section 7.
4-532
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TI;XAS 75265
ADVANCE
INFORMATION
SN54ASC5120. SN74ASC5120
TTL-/CMOS-COMPATIBLE OUTPUT BUFFERS
02939. AUGUST 1986
SystemCelrM
•
Typical Propagation Delay
1 .7 ns with 15-pF Load
2.2 ns with 50-pF Load
•
Output Current Ratings
SN54ASC5120 IOL
IOH
SN74ASC5120 IOL
IOH
2-j.lm OUTPUT STANDARD CELL
logic symbol
A-[>-V
•
20.4 mA
-10.2 mA
24mA
-12 mA
FUNCTION TABLE
INPUT
Incorporates Circuitry to Protect Against
ESD and Latch-Up
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
OUTPUT
A
V
H
H
L
L
II
...
positive logic equation
Y
=A
U)
II)
II)
description
The SN54ASC5120 and SN74ASC5120 are noninverting output buffer standard cells that interface CMOS
internal cells with TTL or CMOS external loads. The cell is designated and called from the engineering
workstation input using the following cell name to develop labels for the design netlist:
OPFBOLH
NETLIST
CELL LAVOUT
HOL LABEL
ASPECT RATIO
Label: OPFBOLH A.V;
minimum width
en
...caca
C
FEATURES
CELL NAME
.c
RELATIVE
CELL AREA
TO NA210LH
63
The cell incorporates circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are. employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most common sources that can produce a latch-up condition.
-;-i,,,,,,, uU'llUL ""jj" j,,,v,, U""" ,j":;ign,,,j to provloe low-Impeoance arlve levelS tor both the high- and lowlogic-level states. As a result, passive resistance has been omitted in series with the output transistors.
Shorting a high-level output to ground or a low-level output to VCC will cause current flow in excess of
that recommended for normal operation. Therefore, it is recommended that outputs not be shorted directly
to ground or VCC.
ADVANCE INFORMATION documenls cO.lai.
informatioR on new pradoucts in the 88mplinp or
IKap.oduotio. ph... tit development. Cha.actllriSlic
~ata a.d otho. spacificatio.. a.a subjlcllo cha.ge
without notice.
Copvrigh~ @ 1986, Texas Instrument.s Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-533
SN54ASC5120, SN74ASC5120
TTL-/CMOS-COMPATIBLE OUTPUT BUFFERS
description (continued)
The dynamic drive capability of each output is specified by the delta propagation delay time parameter
included with the switching characteristics. The delta propagation delay times provide a means for making
direct comparisons of the various output responses with change in capacitive loading.
The SN54ASC5120 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5120 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 3 in Section 2. The maximum high-level output current is -10.2 milliamperes for the
SN54ASC5120 and -12 milliamperes for the SN74ASC5120. The maximum low-level output current
is 20.4 milliamperes for the SN54ASC5120 and 24 milliamperes for the SN74ASC5120.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VT
•
Input threshold voltage
VOH High-level output voltage
Vee
IOH
IOH
IOH
IOL
C
...
I»
I»
en
:r
CD
CD
....
VOL Low-level output voltage
IOL
IOL
ICC
Supply current
ej
Input capacitance
Equivalent power
epd dissipation
capacitance
til
SN54ASC5120
TEST CONDITIONS
= 5 V.
= -12 rnA
= -10.2 rnA
= -20.pA,
= 24 rnA
= 20.4 rnA
= 20 pA,
TA
TYP
MIN
=
= MIN to
Vee = 5 V,
= 5 V,
= 25°C
Vee
TA
TYP
MAX
2.2
UNIT
V
3.7
3.7
See Note 1
V
Vee- D. 1
Vee- D. 1
0.5
V
0.5
See Note 1
MAX
TA
tr
=
25°C
= tf =
3 ns,
0.1
0.1
4207
252
nA
2.7
2.7
pF
32.8
32.8
pF
NOTE 1: These limits apply when all other outputs are open.
4-534
SN74ASC5120
MIN
2.2
25°C
Vee - 4.5 V to 5.5 V, VI - Vee or 0,
TA
MAX
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC5120. SN74ASC5120
TTL-/CMOS-COMPATIBLE OUTPUT BUFFERS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
TTL loads
PARAMETERt
tpLH
FROM
TO
TEST
(lNPUTI
(OUTPUT)
CONDITIONS
A
tPHL
tpLH
A
tpHL
Ll.tpLH
Ll.tpHL
A
CL
Y
=
RL
CL
Y
=
RL
SN54ASC5120
Typt
MAX
MIN
1.3
15 pF,
=
SN74ASC5120
Typt
MAX
MIN
1.3
2
2
50 pF,
1.7
1.7
=
2.6
2.6
11
11
17
17
00
00
Y
UNIT
ns
ns
psipF
CMOS loads
PARAMETERt
tpLH
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Y
tpHL
tpLH
tpHL
Ll.tPLH
Ll.tpHL
A
A
Y
CL
=
RL
CL
=
RL
SN54ASC5120
Typt
MAX
MIN
SN74ASC5120
Typt
MAX
MIN
15 pF,
1.6
1.6
=
00
1.8
1.8
50 pF,
2.1
2.1
=
2.2
2.2
14
14
11
11
00
Y
UNIT
ns
ns
psipF
tpropagation delay times are meas·ured from the 44% point of VI with tr = tf = 3 ns (10% and 90%). For TTL loads, the times end
at Vo = 1.3 V. For CMOS loads, the times end at the 50% point of Va.
tpLH := propagation delay time, low;to-high level output
tpHL == propagation delay time, high-ta-Iow level output
AtpLH == change in tpl.H with load capacitance
..1tpHL == change in tpHL with load capacitance
*Typical values are at VCC = 5 V, TA = 25°C.
II
...
rn
CU
CU
.c
en
...
ctI
ctI
DESIGN CONSIDERATIONS
C
Refer to Section 7.
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-535
4-536
PRODUCT
PREVIEW
SN54ASC5121, SN74ASC5121
TTL-/CMOS-COMPATIBLE OPEN-DRAIN OUTPUT BUFFERS
02939. AUGUST 1986
SystemCelrM 2-lAm
''lgic symbol
•
Typical Propagation Delays
1 .7 ns with 15-pF Load
2.2 ns with 50-pF Load
•
Output Current Ratings
SN54ASC5121 IOL - 37.4 mA
SN74ASC5121 IOL = 44 mA
•
OUTPUT STANDARD CELL
A-[>--V
FUNCTION TABLE
INPUT
Incorporates Circuitry to Protect Against
ESD and Latch-Up
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
OUTPUT
A
V
H
H
L
L
II
...
positive logic equation
Y=A
U)
description
The SN54ASC5121 and SN74ASC5121 are noninverting output buffer standard cells that interface CMOS
internal cells with a passive pull-up external load. The cell is designated and called from the engineering
workstation input using the following cell name to develop labels for the design netlist:
FEATURES
CELL NAME
OPFD1LH
NETLlst
CELL LAVOUT
HOL LABEL
ASPECT RATIO
Label: OPFD1 LH A.V;
minimum width
G)
G)
.c
en
...caca
C
RELATIVE
CELL AREA
TO NA210LH
54
The cell incorporates circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to' 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes, .
thereby negating most common sources that can produce a latch-up condition.
These output cells have been designed to provide low-impedance drive levels for low-logic-level outputs
interfacing a bus having a terminated high-level drive source. As a result, passive resistance has been omitted
in series with the output transistor. Shortino the low-level outout to Vr:r: will,,,,,,,,,, r.llrrp.nt flow in ''''''P.''''
of that recommended for normal operation. Therefore, it is recommended that outputs not be shorted directly
to Vec.
PRODUCT PREVIEW documents contain infurmation
an products in the formative or design phala of
development. Characteristic data and other
i: t:::
dt-:iX'a=::I~rT3i~::~a:u':~:=
products without notice.
:r::t srrgr:t
Copyright © 1986, Texas Instruments Incorporated
.. TEXAS'"
INSTRUMENts
POST OFFICE BOX 655012 • DALLAS, T-EXAS 75265
4-537
SN54A~~5121, SN74ASC5121
TTL-/CMOS-COMPATIBLE OPEN-DRAIN, OUTPUT BUFFERS
description (continued)
The dynamic drive capability of each output is specified by the delta propagation delay time parameter
included with the switching characteristics. The delta propagation delay times provide a means for making
direct comparisons of the various output responses with change in capacitive loacjing.
The SN54ASC5121 is charactElrized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5121 is characterized for operation from -40°C to 85°C .
. absolute maximum ratings and recomrrended operating conditions
See Table 3 in Section 2. The maximum low-level output current is 37.4 milliamperes for the SN54ASC5121
and 44 milliamperes for the SN74ASC5121.
electrical charaoteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
. .
PARAMETER
VT
Input threshold voltage
SN54ASC5121
TEST CONDITIONS
VCC
=
TA
5 V,
MIN
=
TYP
MAX
2.2
25°e
SN74ASC5121
MIN
TYP
2.2
II
C
...
I»
I»
...en
=
IOZ Off·state output current
lee supply current
Ci
Input capacitance
Equivalent power
epd dissipation capacitance
0.5
0.1
37A mA
IOL - 20 ~A,
f/)
:r
--V
FUNCTION TABLE
INPUT
Incorporates Circuitry to Protect Against
ESD and Latch-Up
•
Specified for Operation Over VCC Range of
4.S V to S.S V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
OUTPUT
A
Y
H
H
L
L
positive logic equation
II
V=A
description
The SN54ASC5123 and SN74ASC5123 are non inverting output buffer standard-cells that interface CMOS
internal cells with a passive pull-up external load. The cell is designated and called from the engineering
workstation input using the following cell name to develop labels for the design netlist:
FEATURES
CELL NAME
OPFE1LH
NETLIST
CELL LAYOUT
HDL LABEL
ASPECT RATIO
Label: OPFE1 LH A,Y;
minimum width
RELATIVE
CELL AREA
TO NA210LH
69
The cell incorporates circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most common sources that can produce a latch-up condition.
These output cells have been designed to provide low-impedance drive levels for the lOW-logic-level outputs
interfacing a bus having a terminated high-level drive source. As a result, passive resistance has been omitted
in series with the output transistor. Shorting the low-level output to VCC will cause current flow in excess
of that recommended for normal operation. Therefore, it is recommended that outputs not be shorted directly
to VCC.
The dynamic drive capability of each output is specified by the delta propagation delay time parameter
included with the switching characteristics. The delta propagation delay times provide a means for making
direct comparisons of the various output responses with change in capacitive .loading.
The SN54ASC5123 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5123 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 3 in Section 2. The maximum low-level output current is 40.8 milliamperes for the
SN54ASC5123 and 48 milliamperes for the SN74ASC5123.
Copyright © 1986, Texas Instruments Incorporated
ADVANCE INFORMATION documenlS contain
=':::~~:~r.'!: Jr::..-:.!~:~:::::~':rst~~
data and other .pacifications are ••bjact to change
without notice.
TEXAS •
INSTRUMENTS
POST OFFice sox 655012 • DALLAS, TEXAS 75266
4-541
SN54ASC5123. SN74ASC5123
TTL-/CMOS-COMPATlBLE OPEN-DRAIN OUTPUT BUFFERS
electrical characteristics over recorrimended ranges of supply voltage and operating free-air temperature
(unless otherll!'ise noted)
PARAMETER
VT
SN54ASC5123
TEST CONDITIONS
Input threshold voltage
MIN
MAX
SN74ASC5123
MIN
2.2
TA = 25°C
Vee = 5 V,
TYP
TYP
IOL - 40.8 pA,
IOL - 20 ~A,
See Note 1
IOZ
Off-state output current
Vo - Vee or 0
Vee - 4.5 V to 5.5 V,
ICC
Supply current
VI = Vee or 0,
TA = MIN to MAX
ei
Input capacitance
Vee = 5 V,
TA = 25°C
Equivalent power
Vee - 5 V,
TA = 25°C
tr - tf - 3 ns,
epd
dissipation capacitance
UNIT
V
0.5
IOL - 48 mA,
VOL Low-level output voltage
MAX
2.2
V
0.5
0.1
0.1
±10
±5
pA
3171
190
nA
1.8
1.8
pF
16.2
16.2
pF
NOTE 1: These limits apply when all other outputs are open.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
~ TTL loads
PARAMETERt
C
m
FROM
TO
TEST
(lNPUTI
(OUTPUT)
CONDITIONS
r+
tpZL
A
y
rn
::r
tpZL
A
y
tPLZ
t.tpZL
A
Y
A
y
m
CD
CD
r+
(II
SN54ASC5123
Typf
MAX
SN74ASC5123
Typf
MAX
UNIT
1.5
1.5
ns
1.9
1.9
ns
9
9
11
11
ps/pF
SN74ASC5123
Typf
MAX
UNIT
1.3
1.3
ns
1.7
1.7
ns
11
11
ps/pF
MIN
eL = 15 pF,
RL = 1 k!l to Vee
eL - 50 pF,
RL = 1 k!l to Vee
RL = 1 k!l to Vee
MIN
ns
CMOS loads
PARAMETERt
tpZL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
y
SN54ASC5123
Typf
MAX
MIN
eL - 15 pF,
RL = 1 k!l to Vee
tpZL
A
Y
t.tPZL
A
y
eL - 50 pF,
RL = 1 k!l to Vee
t Propagation delay times are measured from the 44% point of VI with tr
at Va = 1.3 V. For CMOS loads, the times end at 50% pOint of VO·
tpZL .. output enable time to low level
tpLZ .. output disable time from low level
t.tpZL .. change in tpZL with load capacitance
fTypical values are at Vee = 5 V, TA = 25°C.
;=
tf
=
3 ns 110% and 90%). For TTL loads, the times end
DESIGN CONSIDERATIONS
Refer to Section 7,
4-542
MIN
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
ADVANCE
INFORMATION
SN54ASC5124, SN74ASC5124
TTL·/CMOS·COMPATIBLE 3·STATE OUTPUT BUFFERS
02939, AUGUST 1986
SystemCell™
•
Typical Propagation Delays
2,5 ns with 15-pF Load
3 ns with 50-pF Load
•
Output Current Ratings
SN54ASC5124 IOL
IOH
SN74ASC5124 IOL
IOH
•
2-l"m OUTPUT STANDARD CELL
logic symbol
A~Y
GZ~
37.4 mA
-10,2 mA
44mA
-12 mA
FUNCTION TABLE
INPUTS
Incorporates Circuitry to Protect Against
ESD and -Latch-Up
•
Specified for Operation Over VCC Range of
4,5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
OUTPUT
GZ
A
Y
L
H
L
L
H
L
H
X
Z
a...
positive logic equation
Y
=A
(when GZ is L)
fI)
G)
G)
description
The SN54ASC5124 and SN7 4ASC5124 are noninverting 3-state output buffer standard cells that interface
CMOS internal cells with TTL or CMOS external buses. The cell is designated and called from the engineering
workstation input using the following cell name to develop labels for the design netlist:
FEATURES
CELL NAME
OPF03LH
NETLIST
CELL LAYOUT
HOL LABEL
ASPECT RATIO
Label: OPF03LH A,GZ, Y;
minimum width
RELATIVE
.z:.
en
...'"
o'"
CELL AREA
TO NA210LH
93
The cell incorporates circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most common sources that can produce a latch-up condition.
Thp.c:::p nllt~llt r.p.1I1=:
h;=:j\lA
hj:lp,n ri':::&c::i~nprl tn !""rn\liria In\AI_irn:-'Qrt~n""Q riri\lc IC\Jpl~ f"r hnth t+~",=, ~i~~_?!,,~ 1':',.11.,-
logic-level states. As a result, passive resistance has been omitted in series with the output transistors,
Shorting a high-level output to ground or a low-level output to VCC will cause current flow in excess of
that recommended for normal operation. Therefore, it is recommended that outputs not be shorted directly
to ground or VCC,
The dynamic drive capability of each output is specified by the delta propagation delay time parameter
included with the switching characteristics. The delta propagation delay times provide a means for making
direct comparisons of the various output responses with change in capacitive loading.
The SN54ASC5124 is characterized for operation over the full military temperature range of - 55°C to
125°C, The SN74ASC5124 is characterized for operation from -40°C to 85°C.
ADVANCE INFORMATION d••uments •• ntain
~=:3~~~::h~~= o~r3!-:~~~~:ec~::~~Pst1!
IIBIa and othar specifications are subject to changa
without notics.
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-543
SN54ASC5124, SN74ASC5124
TTL-/CMOS-COMPATIBLE 3-STATE OUTPUT BUFFERS
absolute maximum ratings and recommended operating conditions
See Table 3 in Section 2. The maximum high-level output current is 10.2 milliamperes for the,
SN54ASC5124 and 12 milliamperes for the SN74ASC5124. The maximum low-level output current is
37.4 milliamperes for the SN54ASC5124 and 44 milliamperes for the SN74ASC5124.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VT
SN54ASC5124
TEST CONDITIONS
Input threshold voltage
VOH High-level output voltage
= 5 V,
10H = -12 mA
IOH - -10.2 mA
20 pA,
IOH
Vee
TA
=
TYP
MIN
MAX
SN74ASC5124
MIN
TYP
2.2
25°e
2.2
V
Vee
Vee 0.1
0.1
0.5
0.5
IOL - 20 ~A,
•
IOZ
Off-state output current
lee
Supply. current
ei
Input
capacitance
I
I
GZ
Equivalent power
epd
C
I»
r+
I»
dissipation capacitance
See Note 1
Vo - Vee or 0
Vee - 4.5 V to 5.5 V, V,
TA
A
= MIN
Vee
=
V
3.7
See Note 1
= 37.4 mA
IOL
UNIT
3.7
IOL - 44 mA
VOL Low-level output voltage
MAX
Vee or 0,
to MAX
5 V,
TA
Vee - 5 V,
TA = 25°e
=
25°e
= tf =
tr
V
0.1
3 ns,
0.1
±10
±5
pA
6320
379
nA
1.8
1.8
1.4
1.4
49
49
pF
pF
NOTE 1: These limits apply when all other outputs are open.
en
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
CD
CD
TTL loads. CL - 15 pF
:::r
r+
(I)
PARAMETERt
tpLH
tpHL
tpZH
tpZL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Y
GZ
Y
RL
SN54ASC5124
MIN
RL = 00
= 1 kO to GND
RL - 1 kO to Vee
TYP*
2.2
MAX
SN74ASC5124
MIN
TYP*
2.2
2.5
2.5
3
3
2.1
2.1
MAX
UNIT
ns
ns
t Propagation delay times are measured from the 44% point of V, with tr = tf = 3 ns (10% and 90%). For TTL loads, the times end
at Vo = 1.3 V.
.
tpLH '" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
tpZH '" output enable time to high level
tpZL '" output disable time from low level
~Typical values are at Vee = 5 V, TA = 25°e.
4-544
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 656012 .. DALLAS, TEXAS 75285
SN54ASC5124, SN14ASC5124
TTL-ICMOS-COMPATIBLE 3-STATE OUTPUT BUFFERS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (continued)
TTL loads, CL = 50 pF
PARAMETERt
tpLH
TO
TEST
(OUTPUT)
CONDITIONS
A
Y
GZ
Y
RL
tPHL
tpZH
tpZL
tpHZ
SN54ASC5124
FROM
(INPUT)
GZ
RL
=
=
MIN
TYP*
00
1 kll to GND
RL = 1 kll to GND
Y
RL
=
SN74ASC5124
MIN
2.8
3
3.6
2.8
10
9
RL - 1 kll to Vee
tPLZ
MAX
1 kll to Vee
TYP*
MAX
2.8
3
3.6
2.8
10
9
UNIT
ns
ns
ns
change in propagation delay time with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
TTL loads
PARAMETERt
Ll.tpLH
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Ll.tpHL
Ll.tpZH
Ll.tpZL
GZ
SN54ASC5124
MIN
TYP*
MAX
SN74ASC5124
MIN
17
14
Y
Y
TYP*
17
17
14
17
20
20
MAX
UNIT
ps/pF
ps/pF
II
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
CMOS loads, CL - 15 pF
PARAMETERt
tpLH
tpHL
tpZH
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Y
GZ
Y
tpZL
CMOS loads, CL
PARAMETERt
tpLH
tpHL
RL
=
=
TYP*
MAX
SN74ASC5124
MIN
00
1 kll to GND
RL - 1 kll to Vee
TYP*
MAX
2.7.
2.2
3.4
1.8
2.7
2.2
3.4
1.8
UNIT
ns
ns
50 pF
SN54ASC5124
FROM
TO
TEST
liN PUT)
(OUTPUT)
CONDITIONS
A
Y
U£
Y
MIN
TYP*
MAX
SN74ASC5124
MIN
TYP*
3.6
2.q
3.6
2.6
~~In
44
AA
RL - 1 kll to Vee
2.4
2.4
RL =
R, _ 1 kO
tp7J-1
tpZL
RL
SN54ASC5124
MIN
00
tn
MAX
UNIT
ns
ns
tPropagation delay times are measured from the 44% point of VI with tr = tf = 3 ns (10% and 90%1. For TTL loads. the times end at
Vo = 1.3 V. For eMOS loads. the times end at the 50% point of VO.
tPLH '" propagation delay time. low-to-high-Ievel output
i!.tPLH·'" change in tpLH with load capacitance
tPHL '" propagation delay time. high-to-Iow-Ievel output
Ll.tpHL '" change in tpHL with lo~d capacitance
tpZH '" output enable time to high level
Ll.tpZH '" change in tpZH with loap capacitance
tpZL '" output enable time to low level
Ll.tpZL '" change in tpZL with load capacitance
tpHZ '" output disable time from high level
tpLZ == output disable time ,from low level
tTypical values are at Vee = 5 V, TA = 25°C.
. TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-545
SN54ASC5124, SN74ASC5124
,
TTL-/CMOS-COMPATIBLE 3-STATE t)UTPUT BUFnRS
change in propagation delay time with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
CMOS loads
PARAMETERt
a.tPLH
a.tpHL
a.tpZH
a.tpZL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
GZ
SN54ASC5124
MiN
TYP*
26
Y
y
MAX
SN74ASC5124
MIN
TYP*
26
11
11
29
29
17
17
MAX
UNIT
pslpF
pslpF
tPropagation delay times are measured from the 44% point 0.1 VI with tr = tf = 3 ns (10% and 90%). For CMOS loads, the times end
at the 50% point of VO.
a.tpLH .. change in tPLH with load capacitance
a.tpHL '" change in tPHL with load capacitance
a.tpZH ., change in tpZH with load capacitance
atpZL ., change in tpZL with load capacitance
*Typical values are at VCC = 5 V, T A = 25
ac.
•
DESIGN CONSIDERATIONS
Refer to Section 7.
c
...
C»
C»
(I)
:r
...
CD
CD
en
4-546
..tj
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. r·EXAS 762.65
SN54ASC5125, SN74ASC5125
TTL-/CMOS-COMPATIBLE 3-STATE OUTPUT BUFFERS
ADVANCE
INFORMATION
02939, AUGUST 19B6
SystemCell™
•
Typical Propagation Delays
2.8 ns with 15-pF load
3.7 ns with 50-pF load
•
Output Current Ratings
SN54ASC5125 IOl
IOH
SN74ASC5125 IOl
IOH
•
2-llm OUTPUT STANDARD CELL
logic symbol
A~Y
GZ
20.4 mA
-10.2 mA
24 mA
-12 mA
--.11
FUNCTION TABLE
INPUTS
Incorporates Circuitry to Protect Against
ESD and latch-Up
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
GZ
A
L
H
OUTPUT
Y
H
L
L
L
H
X
Z
•
positive logic equation
...
Y = A (when GZ is l)
II)
Q)
Q)
description
The SN54ASC5125 and SN74ASC5125 are noninverting 3-state output buffer standard cells that interface
CMOS internal cells with TTL or CMOS external buses. The cell is designated and called from the engineering
workstation input using the following cell name to develop labels for the design netlist:
OPFB3LH
NETLIST
CELL LAYOUT
HOL LABEL
ASPECT RATIO
Label: OPFB3LH A,GZ,Y;
minimum width
en
...caca
C
FEATURES
CELL NAME
.s:
RELATIVE
CELL AREA
TO NA210LH
64
The cell incorporates circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most common sources that can produce a latch-up condition.
These output cells have been designed to provide low-impedance drive levels for both the high- and lowlogic-level states. As a result, passive resistance has been omitted in series with the output transistors.
Shorting a high-level output to ground or a low-level output to VCC will cause current flow in excess of
that recommended for normal operation. Therefore, it is recommended that outputs not be shorted directly
to ground or VCC.
The dynamic drive capability of each output is specified by the delta propagation delay time parameter
included with the switching characteristics. The delta propagation delay times provide a means for making
direct comparisons of the various output responses with change in capacitive loading.
The SN54ASC5125 is characterized for operation over the full military temperature range of - 55 DC to
125 DC. The SN74ASC5125 is characterized for operation from -40°C to 85°C.
Copyright © 1986, Texas Instruments Incorporated
ADVANCE INFORMATION documonto contain
::':3!:rO::h~~= o,r:!~r~~~n\~~~:::::::Pst~!
~ata and other opacifications ora subjact to chango
without notice.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-547
SN54ASC5125, SN74ASC5125
TTL-/CMOS-COMPATIBLE 3-STATE OUTPUT BUFFERS
absolute maximum ratings and recommended operating conditions
See Table 3 in Section, 2, The maximum high-level output current is 10,2 milliamperes for the
SN54ASC5125 and 12 milliamperes for the SN74ASC5125, The maximum low-level output current is
20.4 milliamperes for the SN54ASC5125 and 24 milliamperes for the SN74ASC5125,
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VT
Input threshold voltage
Vce
10H
VOH High-level output voltage
10H
= 5 V,
= -12 mA
= -10,2 mA
= -20 pA,
TA
VOL Low-level output voltage
•
10Z
Off-state output current
ICC
Supply current
ei
Input capacitance
10l
=
10l
~
Equivalent power
dissipation capacitance
2Soe
TYP
MAX
SN74ASC5125
MIN
2,2
TYP
2,2
MAX
UNIT
V
3,7
V
Vee- D,1
Vee- D. l
O,S
O,S
°
~
Vee or 0,
MAX
TA
=
V
0,1
See Note 1
\(0 - Vee or
Vee = 4,5 V to S,5 V, VI
= MIN to
Vee = S V,
Vee = 5 V,
TA = 25°C
=
See Note 1
2004 mA
20 pA,
TA
MIN
3,7
10H
IOL - 24 mA
epd
SN54ASC5125
TEST CONDITIONS
25°C
0,1
±10
±S
pA
4009
241
nA
1,1
1.1
pF
29
29
pF
tr :::: tf :::: 3 ns,
NOTE 1: These limits apply when all other outputs are open.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
TTL loads, CL = 15 pF
PARAMETERt
tPlH
tpHl
tpZH
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Y
Rl
Y
GZ
tPZl
SN74ASC5125
Typt
MAX
UNIT
3,2
2,3
3,2
ns
1 k!l to GND
2,7
2,7
1 k!l to Vee
3
3
Rl
Rl
=
=
=
SN54ASC5125
Typt
MAX
MIN
2,3
00
MIN
ns
t Propagation delay times are measured from the 44% point of VI with tr :::: tf :::: 3 ns (10% and 90%), For TTL loads, the times end
at Vo = 1,3 V,
tpLH ;;;;: propagation delay time, low-to-high-Ievel output
tpHl " propagation delay time, high-to-Iow-Ievel output
tpZH E output enable time to high level
tpZL ;;;: output disable time from low level
+Typical values are at Vee
4-548
=
5 V, TA
=
25°C,
TEXAS
"11
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC5125, SN74ASC5125
TTL-/CMOS-COMPATIBLE 3-STATE OUTPUT BUFFERS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (continued)
TTL loads, CL
=
PARAMETERt
50 pF
FROM
(INPUT)
TO
(OUTPUT)
A
Y
tpLH
tpHL
tpZH
tpZL
tpHZ
tpLZ
GZ
Y
GZ
Y
TEST
CONOITIONS
RL
SN54ASC5125
MIN
~ 00
TYP*
MAX
SN74ASC5125
MIN
TYP*
2.9
4.3
4.3
2.9
RL
~
1 kll to GND
3.4
3.4
RL
RL
~
1 kll to Vce
1 kll to GND
4.2
4.2
8.5
8.5
RL ~ 1 kll to Vee
8.2
8.2
~
MAX
UNIT
ns
ns
ns
change in propagation delay time with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
TTL loads
PARAMETERt
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
A
Y
atpLH
atpHL
atpZH
GZ
atpZL
SN54ASC5125
MIN
TYP*
y
MAX
SN74ASC5125
MIN
TYP*
17
17
31
31
20
20
34
34
MAX
UNIT
ps/pF
ps/pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
CMOS loads, CL
PARAMETERt
=
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Y
tpLH
tpZH
GZ
tPZL
CMOS loads, CL
PARAMETERt
tpLH
tpHL
tpZH
. --
fn..,.,
15 pF
FROM
tpHL
=
a
RL
SN54ASC5125
MIN
~ 00
RL - 1 kg to GND
Y
RL
~
1 kll to Vee
TYP*
2.7
MAX
SN74ASC5125
MIN
TYP*
2.7
2.9
3.2
3.2
2.6
2.6
MAX
UNIT
ns
2.9
ns
50 pF
FROM'
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
A
Y
GZ
Y
RL
SN54ASC5125
MIN
~ 00
TYP*
3.7
MAX
SN74ASC5125
MIN
TYP*
3.7
3.7
3.7
RL - 1 kg to GND
4.2
4.2
R,
3.5
3.5
- 1 kO to V,..r--
MAX
UNIT
ns
ns
tpropagation delay times are measured from the 44% point of VI with tr ~ tf ~ 3 ns (10% and 90%). For TTL loa'ds. the times end at
Va ~ 1.3 V. For eMOS loads, the times end at the 50% point of Va.
tpLH '" propagation delay time, low-to-high-Ievel output
atpLH '" change in tPLH with load capacitance
tpHL '" propagation delay time. high-to-Iow-Ievel output
atpHL '" change in tpHL with load capacitance
tpZH '" output enable time to high level
atpZH '" change in tpZH with load capacitance
tpZL '" output enable time to low level
atpZL .. change in tpZL with load capacitance
tPHZ '" output disable time from high level
tpLZ '" output disable time from low level
*Typical values are at Vee = 5 V. TA = 25°e.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-549
SN54ASC5125, SN74ASC5125
TTL-/CMOS-COMPATIBLE 3-STATE OUTPUT BUFFERS
change in propagation delay time with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
CMOS loads
PARAMETERt
IltPLH
IltpHL
IltpZH
IltpZL
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
A
Y
GZ
Y
tpropagation delay times are measured from the 44% point of VI with tr
at the 50% point of Va.
IltpLH '" change in tpLH with load capacitance
IltpHL .. change in tpHL with load capacitance
IltpZH .. change in tpZH with load capacitance
IltpZL '" change in tpZL with load capacitance
*Typical values are at VCC = 5 V, T A = 25°C.
SN54ASC5125
MIN
=
tf
=
TYP*
TYP*
23
29
29
26
26
29
MAX
UNIT
ps/pF
ps/pF
3 ns (10% and 90%). For TTL loads, the times end
Refer to Section 7.
D)
D)
en
:r
..
CD
CD
U)
4-550
SN74ASC5125
MIN
29
23
DESIGN CONSIDERATIONS
IIc
..
MAX
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC5200, SN74ASC5200
J·STAH 1/0 BUFFER WITH
INVERTING CMOS INPUT AND CMOSITTL OUTPUT
D2939, AUGUST 1986
SystemCell™
•
Typical Propagation Delays
3.3 ns with 15·pF load
5.9 ns with 50-pF load
•
Output Current Ratings:
SN54ASC5200 IOl
IOH
SN74ASC5200 IOl
IOH
2·/Am OUTPUT STANDARD CELL
logic symbol
A
•
3.4mA
-3.4 mA
4mA
-4 mA
GZ--_...J
Y2
Incorporates Circuitry to Protect Against
ESD and latch-Up
FUNCTION TABLE
INPUTS
•
•
•
Yl
OUTPUTS
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
A
GZ
Yl
Yl
Y2
L
L
L
L
H
Functional Operation Over VCC Range of
2Vt06V
H
L
H
H
L
X
H
L
Z
H
X
H
H
Z
L
Dependable Texas Instruments Quality and
Reliability
II
positive logic equations
Y1
=
A
Y2 =
VI
description
The SN54ASC5200 and SN74ASC5200 are three-state input/output buffer standard cells that interface
CMOS internal cells with TTL or CMOS bidirectional bus lines. The input buffer responds to CMOS threshold
levels imposed on the I/O bus regardless of the state of the internal 3-state control GZ, This cell function
exists in two versions ("E" and "F") with different physical implementations to allow the final IC area
to be optimized. Since the electrical performance of each version is identical, for simplicity only one version
(the "F" cell) will be contained in the engineering workstation cell libraries, Determination of the most
appropriate cell version will be made during the layout stage, The cell is designated and called from the
engineering workstation input using the following cell name and netlist label:
FEATURES
NETLIST
CELL NAME
IOE40LH
IOF40LH
HDL LABEL
Label: IOF40LH A,GZ,Y2,Yl;
CELL LAYOUT
ASPECT RATIO
RELATIVE
CELL AREA
TO NA210LH
minimum height
44.5
minimum width
49.5
The cells incorporate circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most common sources that can produce a latch-up condition.
These output cells have been designed to provide low-impedance drive levels for both the high- and lowlogic-level states. As a result, shorting a high-level output to ground or a low-level output to VCC will cause
current flow in excess of that recommended for normal operation. Therefore, it is recommended that outputs
not be shorted directly to ground or V CC,
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
:~~~~:~~i~ai~:1~1e ~!::i~~ti:r :I~o::~:~:t:~~s
not
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 752tl5
Copyright
© 1986, Texas Instruments Incorporate
4-551
SN54ASC5200, SN74ASC5200
3·STATE 1/0 BUFFER WITH
INVERTING CMOS INPUT AND CMOSITTL OUTPUT
description (continued)
The dynamic drive capability of each output is specified by the delta propagation delay time parameter
included with the switching characteristics. The delta propagation delay times provide a means for making
direct comparisons of the various outputs response with change in capacitive loading.
The SN54ASC5200 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5200 is characterized for operation from -'40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 4 in Section 2. The maximum high-level or maximum low-level output current is 3.4 milliamperes
for the SN54ASC5200 and 4 milliamperes for the SN74ASC5200.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VT
TEST CONDITIONS
~
Input threshold voltage V 1
VOH High-level output voltage
II
Vee = 5 V,
SN54ASC5200
MIN
TYP
MIN
TYP
Off-state output current
V
2.5
3.7
V
Vee- O. l
Vee- O.l
0.5
0.5
10L = 3.4 mA
10L - 20 ~A,
10Z
UNIT
3.7
10L - 4 mA
VOL Low·level output voltage
MAX
2.2
2.2
2.5
TA = 25°e
10H = -4 mA
10H - -3.4 mA
10H = -20 ~A, See Note 1
SN74ASC5200
MAX
See Note 1
Vo - Vee or 0
V
0.1
0.1
±10
±5
~A
NOTE 1: These limits apply when all other outputs are open.
IOE40LH
. PARAMETER
lee
Supply current
ei
Input capacitance
TEST CONDITIONS
Equivalent power
TYP
VI - Vee or 0
VI - 3.15 V or 0.9 V
~
GZ
dissipation capaCitance
MAX
TA = 25°e
Vee = 5 V,
TA = 25°e
tr = tf = 3 ns,
SN74ASC5200
2373
MAX
142
4.33
4.1
0.61
Vee = 5 V,
Yl t
epd
SN54ASC5200
TYP
UNIT
nA
mA
0.61
0.4
0.4
3.84
3.84
12.5
12.5
pF
pF
IOF40LH
PARAMETER
lee
Supply current
ei
Input capacitance
TEST CONDITIONS
Equivalent power
TYP
~
GZ
Vee = 5 V,
TA = 25°C
dissipation capaCitance
Vee = 5 V,
tr = tf = 3 ns,
TA = 25°e
MAX
SN74ASC5200
TYP
2592
4.29
VI =. Vee or 0
VI - 3.15 V or 0.9 V
Yl t
epd
SN54ASC5200
MAX
155
4.06
0.59
0.59
0.47
0.47
4.38
4.38
12.7
12.7
UNIT
nA
mA
pF
'pF
tTotal input capacitance is dependent on the package type and is equal to the sum of package capacitance and intrinsic input capacitance.
4-552
TEXAS •
INSTRUMENTS
POST OFFICE 'BOX 655012 • DALLAS. tEXAS 75265
SN54ASC5200, SN74ASC5200
3·STATE I/O BUFFER WITH
INVERTING CMOS INPUT AND CMOS/TTL OUTPUT
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
TTL loads. CL = 15 pF
PARAMETERt
FROM
(INPUT)
TO
(OUTPUT)
tpLH
tpHL
A
Yl
tpZH
tpZL
GZ
TEST
CONDITIONS
SN74ASC5200
TYP*
MAX
MIN
TYP*
MAX
1.3
2.1
2.5
4.5
5.9
11.6
1.4
2.3
2.5
4.5
10.4
RL - 1 k!l to GND
1.5
3.4
8.4
1.6
3.4
7.6
RL - 1 k!l to Vee
2.1
4.6
11.8
2.2
4.6
10.5
RL =
Yl
SN54ASC5200
MIN
00
5.3
UNIT
ns
ns
TTL loads. CL = 50 pF
PARAMETERt
tpLH
tpHL
tpZH
tpZL.
tpHZ
tpLZ
FROM
(INPUT)
A
GZ
GZ
TO
(OUTPUT)
TEST
CONDITIONS
MAX
MIN
3.6
8.8
2
TYP*
3.6
MAX
1.8
3.9
8.2
19.8
4.3
8.2
17.4
1 k!l to GND
2
4.5
11.3
2.1
4.5
10.2
RL = 1 k!l to Vee
RL - 1 k!l to GND
4
8.5
20.8
4.3
8.5
18.1
RL
RL
Yl
SN74ASC5200
TYP*
Yl
Yl
SN54ASC5200
MIN
RL
=
=
=
00
1 k!l to Vee
11
11
10
10
7.8
UNIT
ns
ns
ns
change in propagation delay times with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
PARAMETERt
Ll.tpLH
Ll.tpHL
Ll.tpZH
Ll.tpZL
FROM
(INPUT)
TO
(OUTPUT)
A
Yl
GZ
Yl
TEST
CONDITIONS
SN54ASC5200
MIN
TYP*
SN74ASC5200
TYP* MAX
MAX
MIN
10
31
80
20
31
80
50
106
230
50
106
210
10
31
80
20
31
60
50
111
260
60
111
240
a
....en
UNIT
G)
G)
ps/pF
.c
en
ps/pF
....caca
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
C
CMOS loads. CL = 15 pF
PARAMETERt
tpLH
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Yl
GZ
Yl
tPHL
tpZH
tpZL
RL =
RL
RL
=
SN54ASC5200
SN74ASC5200
MIN
TYP*
MAX
MIN
1.5
1.8
3.1
3.7
7.5
9.7
1.7
2
00
TYP*
3.1
MAX
3.7
8.6
6.7
1 k!l to GND
2
4
9.8
2.2
4
8.8
1 k!l to Vee
1.8
3.7
9.4
1.9
3.7
8.4
t Propagation delay times are measured from the 44% point of VI with tr = tf
at Vo = 1.3 V. For CMOS loads, the times end at the 50% point of VO.
tpLH == propagation delay time, low-to-high-Ievel output
.6.tpLH
tpHL == propagation delay time, high-to-Iow-Ievel output
..:ltpHL =:
tpZH ;;;;;: output enable time to high level
LltpZH ==
tpZL == output enable time to low level
.6.tpZL ==
tpHZ == output disable time from high level
tpLZ i5! output disable time from low level
Typical values are at Vee = 5 V, TA = 25°C.
=
UNIT
ns
ns
3 ns (10% and 90%1. For TTL loads, the times end
= change in tpLH with load capacitance
change in tpHL with load capacitance
change in tpZH with load capacitance
change in tPZL with load capacitance
*
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4·553
SN54ASC5200,SN74ASC5200
3·STATE 1/0 BUFFER WITH
INVERTING CMOS INPUT AND CMOSITTL OUTPUT
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
CMOS loads. CL = 50 pF
PARAMETERt
tpLH
FROM
!INPUT)
TO
(OUTPUT)
A
VI
tpZL
GZ
VI
SN54ASC5200
TVPt
MAX
MIN
SN74ASC5200
TVpt
MAX
MIN
2.6
5.2
2.9
6.2
12.1
15.5
2.8
3.2
5.2
6.2
10.8
13.7
RL - 1 kll to GND
3.1
6.2
14.6
3.3
6.2
13
RL - 1 kll to VCC
2.9
6.2
15.7
3.2
6.2
13.8
RL =
tpHL
tpZH
TEST
CONDITIONS
00
UNIT
ns
ns
change in propagation delay times with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless othinwise noted)
PARAMETERt
.:l.tpLH
FROM
(INPUT)
A
TO
(OUTPUT)
SN54ASC5200
TVPt
MAX
TEST
MIN
CONDITIONS
VI
.:l.tpHL
.:l.tpZH
•
o
GZ
VI
.:l.tpZL
SN74ASC52000
TVpt MAX
MIN
30
60
140
30
60
120
30
69
170
30
69
150
30
63
140
30
63
130
30
71
190
40
71
160
UNIT
ps/pF
ps/pF
input buffer switching characteristics over recommended ranges of supply voltage arid operating free-air
temperature (unless otherwise noted)
PARAMETER§
!Q)
tpLH
tpHL
tJ)
::r
tPLH
tpHL
....o
.:l.tpHL
CD
CD
.:l.tpLH
FROM
TO
TEST
(INPUT)
10UTPUT)
CONDITIONS
VI
V2
VI
V2
VI
V2
CL
CL
=0
=
SN54ASC5200
TYpt
MAX
MIN
MIN
1 pF
SN74ASC52000
TVpt MAX
0.4
0.7
1.2
0.4
0.7
1.2
0.2
0.7
1.5
0.3
0.7
1.3
0.7
1
1.8
0.1
1
1.8
0.5
1.1
2.3
0.6
1.1
2.1
0.2
0.3
0.7
0.2
0.3
0.7
0.2
0.4
0.9
0.2
0.4
0.8
UNIT
ns
ns
ns/pF
t Propagation delay times are measured from the 44% point of VI with tr = tf = 3 ns 110% and 90%). For CMOS loads, the times end
at the 50% pOint of Vo.
tpLH '" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
tpZH '" output enable time to high le\lel
tpZL '" output enable time to low level
tTypical values are at VCC = 5 V, TA = 25°C.
§ Input propagation delay times are measured from the 50% pOint of
.:l.tpLH
.:l.tpHL
.:l.tPZH
.:l.tPZL
"
'"
'"
"
change in ipLH with load capacitance
change in tpHL with load capacitance
change in tpZH with load capacitance
change in tpZL with load capacitance
VI to the 44% point of Vo with tr
DESIGN CONSIDERATIONS
Refer to Section 7.
4-554
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, T!:XAS 7526~
= tf = 4
ns.
SN54ASC52D1, SN74ASC52D1
3·STATE I/O BUFFER WITH
INVERTING TTL INPUT AND CMOS/TTL OUTPUT
02939. AUGUST 1986
SystemCell11\1
logic symbol
•
Typical Propagation Delays
3.5 ns with 15-pF Load
5.8 ns with 50-pF Load
•
Output Current Ratings
SN54ASC5201 IOL - 3.4 rnA
IOH - -3.4 rnA
SN74ASC520110L - 4 rnA
IOH - -4 rnA
•
A;tt-Vl
GZ
V2
FUNCTION TABLE
Incorporates Circuitry to Protect Against
ESD and Latch-Up
•
Specified for Operation Over Vee
Range of 4.5 V to 5.5 V
•
Functional Operation Over VCC
Rangeof2Vt06V
•
2-~m OUTPUT STANDARD CELL
INPUTS
OUTPUTS
A
GZ
Vl
Vl
L
L
L
L
H
L
H
H
L
X
X
H
L
Z
H
H
H
Z
L
V2
H
Dependable Texas Instruments Quality and
Reliability
II
...
positive logic equations
Yl
=A
en
description
The SN54ASC5201 and SN74ASC5201 are 3-state input/output buffer standard-cells that interface CMOS
internal cells with TTL or CMOS \:lidirectional bus lines. The input buffer responds to TTL threshold levels
imposed on the I/O bus regardless of the state of the internal 3-state control GZ. This cell function exists
in two versions ("E" and "F") with different physical implementations to allow the final IC area to be
optimized. Since the electrical performance of each version is identical, for simplicity only one version (the
"F" cell) will be containec! in the engineering workstation cell libraries. Determination of the most appropriate
cell version will be made during the layout stage. The cell is designated and called from the engineering
workstation input using the following cell name and netlist label:
CD
CD
.c
en
...asas
C
FEATURES
NETLIST
CELL NAME
IOE43LH
IOF43LH
CELL LAVOUT
HDL LABEL
Label: IOF43LH A,GZ.Y2,Yl;
RELATIV~
ASP!,CT RATIO
CELL AREA
TO NA210LH
minimum height
47.7
minimum width
50.9
The cells incorporate circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guarc!-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most r;ommon sources that can produce a' latch-up condition.
These output cells have been designed to provide low-impedance drive l\3vels for both the high- and lowlogic-level states. As a result, passive resistance has been omitted in series with the output transistors.
Shorting a high-level output to' ground or a low-level output to V CC will cause current flow in excess of
that recommended for normal operation. Therefore, it is recommended that outputs not be shorted directly
to ground or VCC.
PRODUCTION DATA doouments oontain inform.tl,"
ourrent .. of publio.tion d.te. Products' oonform to
.pecifications por the terms of T.... Instruments
atandard werrenty. Prad.olion prtioassing dQIS Dot
n......ril' inolu..e testing of
p.remate"" '
.,1
"'!1
TEXAS
INSTRUMENTS
POST OFFICE
~OX
655012
~
DALl.AS, TEXAS 75265
Copyright © 1986. Texas Instruments Incorporated
4-555
SN54ASC5201. SN74ASC5201
3-STATE I/O BUFFER WITH
INVERTING TTL INPUT AND CMOS/TTL OUTPUT
description (continued)
The dynamic drive capability of each output is specified by the delta propagation delay time parameter
included with the switching characteristics. The delta propagation delay times provide a means for making
direct comparisons of the various output responses to change in capacitive loading.
The SN54ASC5201 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5201 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 4 in Section 2. The maximum high-level or maximum low-level output current is 3.4 milliamperes
for the SN54ASC5201 and 4 milliamperes for the SN74ASC5201.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VT
II
TEST CONDITIONS
,~
Input threshold voltage Yl
VOH High-level output voltage
v,
Dr
en
:::r
...
SN74ASC5201
MAX
MIN
TYP
1.3
10Z
Off-state output current
UNIT
v
1.3
3.7
-20 ~A,
See Note 1
V
Vee- O. 1
Vee- O. 1
0.5
10L = 4 mA
VOL Low-level output voltage
MAX
2.2
3.7
V
0.5
10L = 3.4 mA
See Note 1
10L - 20 pA,
I»
TYP
2.2
TA = 25°e
10H = -4 mA
10H = -3.4 mA
10H -
C
CD
CD
Vee = 5
SN54ASC5201
MIN
Vo = Vee or 0
0.1
0.1
±10
±5
~
NOTE 1: These limits apply when all other outputs are open.
IOE43LH
(I)
PARAMETER
lee
Supply current
ei
Input capacitance
TEST CONDITIONS
Equivalent power
TYP
VI - Vee or 0
VI = 2 V or 0.8 V
~
Vee = 5 V,
TA = 25°e
Yl t
epd
SN54Ase5201
dissipation capacitance
Vee = 5 V,
TA = 25°e
tr = tf = 3 ns,
MAX
SN74ASC5201
TYP
MAX
UNIT
2500
150
nA
1.2
1.12
mA
0.62
0.62
0.41
0.41
4.34
4.34
13.2
13.2
pF
pF
IOF43LH
PARAMETER
Ice
Supply current
ei
Input capacitance
'TEST CONDITIONS
Equivalent power
TYP
~
Vee = 5 V,
TA = 25°e
dissipation capacitance
Vee'= 5 V,
tr = tf = 3 ns,
TA = 25°e
MAX
SN74ASC5201
TYP
2588
1.21
VI = Vee or 0
VI = 2 V or O.B V
Y1
epd
SN54ASC5201
0.59
0.59
0.47
0.47
4.26
4.26
13.4
13.4
MAX
UNIT
155
nA
1.13
mA
pF
pF
tTotal input capacitance is dependent on the package type and is equal to the sum of package capacitance and intrinsic input capacitance.
4-556
TEXAS . "
INSTRUMENTS .
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC5201, SN74ASC5201
3-STATE 110 BUFFER WITH
INVERTING TTL INPUT AND CMOS/TTL OUTPUT
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise notedl
TTL loads. CL - 15 pF
PARAMETERt
tpLH
tpHL
tpZH
tpZL
fROM
(INPUT)
TO
(OUTPUT)
A
Yl
GZ
Yl
TEST
CONOITIONS
RL
RL
RL
=
=
=
00
SN54ASC5201
SN74ASC5201
MIN
TYP*
MAX
MIN
1.3
2.5
4.5
6
11.2
1.4
2.2
2.1
TYP*
2.5
MAX
4.5
9.9
5.4
1 kO to GND
1.5
3.5
8.5
1.6
3.5
7.8
1 kO to Vee
2
4.4
11.2
2.2
4.4
9.8
UNIT
ns
ns
TTL loads. CL - 50 pF
PARAMETERt
tpLH
tpHL
tPZH
tpZL
tpHZ
tpLZ
FROM
(INPUT)
TO
(OUTPUT)
A
Yl
GZ
Yl
GZ
Yl
TEST
CONDITIONS
RL
RL
RL
=
=
=
=
SN74ASC5201
MIN TYP*
MAX
1.8
3.6
9
2
3.6
8
3.7
8
20.2
4
8
17.7
1 kO to GND
2
4.6
11.4
2.2
4.6
10.4
1 kO to Vee
3.7
8
21.7
4
8
18.7
RL
RL
SN54ASC5201
MIN TYP*
MAX
=
00
1 kO to GND
11
10
1 kO to Vee
11
10
UNIT
ns
ns
ns
change in propagation delay time. with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted I
PARAMETERt
AtPLH
AtpHL
AtpZH
AtpZL
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
A
Yl
GZ
Y1
tPropagation delay times are measured from the 44% point of VI with tr = tf
at VO. = 1.3 V.
tpLH '" propagation delay time, low-to-high-Ievel output
AtpLH '"
tpHL '" propagation delay time, high-to-Iow-Ievel output
AtpHL "
tpZH '" output enable time to high level
AtpZH '"
tpZL '" output enable time to low level
AtpZL "
tPHZ '" output disable time from high level
tpLZ '" output disable time from low level
*Typical values are at Vee = 5 V, TA = 25°e.
SN74ASC5201
SN54ASC5201
MAX
10
TYP*
31
50
100
10
50
MIN
=
TYP*
31
MAX
80
MIN
20
260
50
100
220
31
90
20
31
80
103
300
50
103
250
70
II
...
U)
UNIT
CI)
CI)
ps/pF
.r:.
en
ps/pF
3 ns (10% and 90%). For TTL loads, the times end
...caca
C
change in tpLH with load capacitance
change in tPHL with load capacitance
change in tpZH with load capacitance
change in tpZL with load capacitance
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-557
SN54ASC5201, SN74ASC5201
3-STATE I/O BUFFER WITH
INVERTING TTL INPUT AND CMOS/TTL OUTPUT
switching characteristics over'recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
CMOS loads, CL - 15 pF
PARAMETERt
tpLH
tpHL
tpZH
tpZL
FROM
TO
TEST
(lNPUTI
(OUTPUT)
CONDITIONS
A
Y1
GZ
SN74ASC5201
TYP*
3,1
MAX
7,7
MIN
1,7
1,8
3.5
9.2
RL - 1 kll to GND
2.1
RL - 1 kllto Vcc
1.7
4
3,3
10
8,7
1.9
2.2
TEST
CONDITIONS
MIN
RL =
Y1
SN54ASC5201
MIN
1,5
00
1.8
TYP*
3.1
3,5
MAX
4
8.9
3.3
7.7
6,8
8,1
UNIT
ns
ns
CMOS loads, CL - 50 pF
PARAMETERt
tpLH
tpHL
tpZH
tpZL
FROM
(INPUT)
TO
{OUTPUT!
A
Y1
GZ
SN74ASC5201
MIN TYP*
MAX
2.7
11
5.2
MAX
2.5
TYP*
5,2
2.8
5,6
15.4
3
5.6
13.4
RL = 1 kO to GND
3,1
6.1
14,8
3.3
6,1
13.2
RL - 1 kO to Vcc
2.8
5.6
15,6
3
5.6
13,6
RL =
Y1
SN54ASC5201
00
12,3
UNIT
ns
ns
,
IIo
change in propagation delay time with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
PARAMETERt
AtPLH
AtPHL
Q)
r+
Q)
en
:r
CD
CD
r+
AtPZH
AtpZL
FROM
TO
TEST
(INPUT!
(OUTPUT!
CONDITIONS
A
Y1
GZ
Y1
SN54ASC5201
SN74ASC5201
MIN
TYP*
MAX
MIN
TYP*
MAX
30
60
130
30
60
120
30
30
60
60
180
140
30
30
60
60
150
120
30
66
200
30
66
170
UNIT
ps/pF
ps/pF
input buffer switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) ,
"
(I)
PARAMETER§
tpLH
tpHL
tpLH
tpHL
AtpLH
AtPHL
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
Y1
Y2
CL = 0
Y1
Y2
CL = 1 pF
Y1
SN54ASC5201
MIN
0.6
TYP*
1
MAX
2,2
0.5
0.9
1,4
1.6
2.9
1,3
6,2
0.8
0.9
0,3
Y2
SN74ASC5201
MAX
MIN TYP*
0,6
1
1,9
0,5
1,7
0.9
1.4
5,6
0,8
1.3
1.9
2.2
4,1
1
1.9
2.1
3,7
0.4
0.9
0,3
0.4
0.8
2.9
UNIT
ns
ns
ns/pF
tpropagation delay times are measured from the 44% point of VI with tr = tf = 3 ns (10% and 90%). For CMOS loads, the times end
at the 50% point of Va,
tpLH '" propagation delay time, low-to-high-Ievel output
AtpLH '" change in tpLH with load capacitance
tpHL "'propagation delay time, high-to-Iow-Ievel output
AtPHL '" change in tpHL with load capacitance
tpZH '" output enable time to high level
AtpZH .. change in tpZH with load capacitance
tpZL '" output enable time to low level
AtpZL .. change in tpZL with load capacitance
*Typical values are at VCC = 5 V, TA = 25°C.
§ Input propagation delay times are measured from the 1.3 V point of VI to the 44% point of Va with tr = tf = 2 ns.
4-558
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC5202, SN74ASC5202
3-STATE I/O BUFFER WITH
INVERTING CMOS INPUT AND CMOS/TTL OUTPUT
02939, AUGUST 1986
SystemCell™
•
•
2-j.lm OUTPUT STANDARD CELL
logic symbol
Typical Propagation Delays
3.6 ns with 15-pF Load
6,8 ns with 50-pF Load
Output Current Ratings
SN54ASC5202 IOL
IOH
SN74ASC5202 IOL
IOH
TAP
A
3.4 rnA
-3.4 rnA
4mA
-4mA
GZ----I
•
Incorporates Circuitry to Protect Against
ESD and Latch-Up
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
•
,,---Yl
YZ--~~
FUNCTION TABLE
OUTPUTS
INPUTS
Functional Operation Over VCC Range of
2Vt06V
A
Dependable Texas Instruments Quality and
Reliability
GZ Yl
Yl
Y2
L
L
L
L
H
H
L
H
H
L
X
H
L
Z
H
X
H
H
Z
L
II
...
positive logic equations
Y = A
Y2
= Y1
en
description
The SN54ASC5202 and SN74ASC5202 are 3-state input/output buffer standard cells that interface CMOS
internal cells with TTL or CMOS bidirectional bus lines, The Schmitt-trigger input buffer, providing additional
noise-rejection with its hysteresis loop, responds to CMOS threshold levels imposed on the I/O bus regardless
of the state of the internal 3-state control GZ, The cell is designated and called from the engineering
workstation input using the following cell name and netlist label:
Q)
Q)
.c
en
...caca
C
FEATURES
NETLIST
CELL LAYOUT
HOL LABEL
ASPECT RATIO
Label: IOF47LH A,GZ,TAP,Y2,Yl;
minimum width
CELL NAME
IOF47LH
RELATIVE
CELL AREA
TO NAZ10LH
55.4
The cell incorporates circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
+h~
.. ""h ...... "' .... .,,+; ..................... + ...................................................... +1-. ............ _ _ ~ ... -' •• _ _ _ 1......... 1-
-- . _ . - - I
••
_~
_ _ . . . .,.
,_ • _ _ _ _ _ . . . . . . . . . . . . . . . "" ....... ""' . . . . . . . . . . . . . . . . . . . .
•• _ _ _ _ -1: ... : __ _
,.... .........................................................
L"'.... .
The IOF47LH incorporates a pull-up tap to simplify termination of the I/O, This tap may be used in conjunction
with an active pull-up/pull-down terminator in the 'ASC237x group or the pull-up tap may be left
unconnected, When the terminator is used it ensures that the input will be driven to a high Dr low logic
level thereby avoiding exposure to a high-impedance or floating condition. Refer to Section 7 for
implementation of the pUll-Up.
PRODUCTION DATA documants .ontain information
current .s of public.tlon date. Products conform to
spacifications par th. terms of TaXIS Instruments
:'~~~:=i~.i~r:1~1i ~~=:~ti:r ~~D:::::~~~ not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1986, Texas Instruments Incorporated
4-559
SN54ASC5202, SN74ASC5202
3·STATE I/O BUFFER WITH
INVERTING CMOS INPUT AND CMOS/TTL OUTPUT
description (continued)
These output cells have been designed to provide low-impedance drive levels for both the high- and lowlogic-level states. As a result, passive resistance has been omitted in series with the output transistors.
Shorting a high-level output to ground or a low-level output to VCC will cause current flow in excess of
that recommended for normal operation. Therefore, it is recommended that outputs not be shorted directly
to ground or VCC.
The dynamic drive capability of each output is specified by the delta propagation delay time parameter
included with the switching characteristics. The delta propogation delay times provide a means for making
direct comparisons of the various output responses with change in capacitive loading.
The SN54ASC5202 is characterized for operation over the full military temperature range of .,. 55 DC to
125°C. The SN74ASC5202 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended. operating conditions
See Table 4 in Section 2. The maximum high-level or maximum low-level output current is 3.4 milliamperes
for the SN54ASC5202 and 4 milliamperes for the SN74ASC5202.
•
C
I»
....
I»
en
:r
CD
CD
....
en
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VT
TEST CONDITIONS
Input threshold voltage
at A. GZ
Positive-going threshold
VT+
level (Vll
Negative-going threshold
VTlevel (Vl)
=
Vee
5 V.
TA
=
SN54ASC5202
MIN
TYP
MAX
4mA
- -3.4 mA
20 pA. See Note 1
- 4 mA
- 3.4 mA
See Note 1
10L = 20 ~A.
VOL
10Z
Low-level output voltage
Off-state output
curre~t
Supply current
ei
IA
Input capacitance I GZ
3.5
2.9
3.2
3.5
V
1.5
1.7
1.9
1.5
1.7
1.9
V
=
5 V.
TA
=
3.7
V
Vee 0.1
Vee- O.1
0.5
0.5
0.1
25°e
Equivalent power
dissipation capacitance
Vee - 5 V.
TA = 25°e
tr - tf - 3 ns.
V
0.1
±10
±5
pA
3005
2.44
leO
1.23
nA
rnA
0.55
0.44
0.55
0.44
4.5
4.5
13.1
13.1
ITAPorVl t
epd
V
1.5
3.7
Vo - Vee or 0
Vee
v
3.2
VI - Vee or 0
VI = 3.5 V or 0.9 V
lee
UNIT
2.9
1.5
IOH
10H
10L
10L
MAX
2.t
10H -
High-level output voltage
TVP
2:2
25°e
Hysteresis (VT + - VT-)
Vhys
at Vl
VOH
SN74ASC5202
MIN
pF
pF
tTotal input capacitance is dependent on the package type and is equal to the sum of package capacitance and intrinsic input capacitance.
NOTE 1: These limits apply when all other outputs are open.
4-560
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC5202, SN74ASC5202
3-STATE I/O BUFFER WITH
INVERTING CMOS INPUT AND CMOS/TTL OUTPUT
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
TTL loads, CL - 15 pF
PARAMETERt
tpLH
tpHL
tpZH
tpZL
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
A
Yl
GZ
Yl
SN54ASC5202
SN74ASC5202
MIN
TYP*
MAX
MIN
TYP*
MAX
1.3
2.5
5.7
1.4
2.5
5
2.3
4.8
10
1.5
3.4
2.5
1.6
4.8
RL - 1 kG to GND
11.3
8.2
3.4
7.4
RL - 1 kG to Vee
2.3
4.8
11.4
2.5
4.8
10.1
SN54ASC5202
TYpl'
MAX
MIN
RL
=
00
UNIT
ns
ns
TTL loads, CL - 50 pF
PARAMETERt
tpLH
tpHL
FROM
(INPUT)
A
Yl
GZ
Yl
SN74ASC5202
TYpl' MAX
1.8
3.6
8.5
1.9
3.6
7.5
3.9
8.1
19.1
4.2
8.1
16.8
1 kG to GND
2
4.5
11
2.2
4.5
9.9
RL = 1 kG to Vee
RL - 1 kG to GND
4
8.3
20.1
4.3
8.3
17.5
RL
tPHZ
tpLZ
MIN
CONDITIONS
RL
tpZH
tpZL
TEST
TO
(OUTPUT)
RL
=
=
=
00
1 kG to Vee
11
11
10
10
UNIT
ns
ns
change in propagation delay time with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
PARAMETERt
Ll.tPLH
Ll.tPHL
Ll.tpZH
Ll.tpZL
FROM
(INPUT)
TO
(OUTPUT)
A
Y1
GZ
SN54ASC5202
TEST
CONDITIONS
MIN
TYP*
Yl
SN74ASC5202
MAX
TYP*
31
MAX
70
10
31
80
MIN
10
50
94
230
SO
94
200
10
31
80
20
31
70
SO
100
2S0
SO
100
210
II
..
..
tI)
UNIT
CI)
CI)
.s:.
ps/pF
CI)
ps/pF
as
as
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
C
CMOS loads, CL = 15 pF
PARAMETERt
tpLH
tpHL
tpZH
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Yl
GZ
MAX
7.2
1.7
3.1
6.4
9.4
2.2
4
8.4
4
9.S
2.2
4
3.9
9.2
2.2
3.9
8.S
8.2
1.6
3.1
2
4
1 kG to GND
2.1
RL - 1 kG to Vee
2
RL
Yl
TYP*
MAX
=
=
00
SN74ASC5202
MIN
TYP*
RL
tpZL
SN54ASC5202
MIN
UNIT
ns
ns
tpropagation delay times are measured from the 44% point of VI with tr = tf = 3 ns (10% and 90%). For TTL loads, the times end
at Vo = l.;j v. ~or CMOS loads, the times end at the SO% point of VO.
tPLH '" propagation delay time, low-to-high-Ievel output
Ll.tpLH '" change in tpLH with load capacitance
tPHL '" propagation delay time, high-to-Iow-Ievel output
Ll.tpHL '" change in tpHL with load capacitance
tpZH ;;;;:: output enable time to high level
6.tpZH
tpZL '" output enable time to low level
tPHZ '" output disable time from high level
tpLZ '" output disable time from low level
Typical values are at Vee = S V, TA = 2Soe.
Ll.tpZL '" change in tpZL with load capacitance
!!!
change in tpZH with load capacitance
*
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-561
SN54ASC5202, SN74ASC5202
3-STATE I/O BUFFER WITH
INVERTING CMOS INPUT AND CMOS/TTL OUTPUT
switching characteristics over recommended ranges of supply voltage and operating' free-air temperature
(unless otherwise noted) (continued)
CMOS loads, CL - 50 pF
PARAMETERt
tpLH
tpHL
tpZH
tpZL
FROM
(INPUT)
A
GZ
TO
(OUTPUT)
Vl
TEST
CONDITIONS
RL =
Vl
00
SN54ASC5202
MIN
2.5
TVP*
5.1
SN74ASC5202
MAX
MIN
TVP*
11.7
2.7
5.1
10.4
MAX.
3.1
6.3
15
3
6.1
14.1
3.3
3.3
6.3
6.1
13.3
RL - 1 kll to GND
RL - 1 kll to V CC
3.1
6.3
15.2
3.4
6.3
13.4
12.6
UNIT
ns
ns
change in propagation delay time with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
CMOS loads
PARAMETERt
dtpLH
dtpHL
•
c
....
CI)
AtPZH
dtpZL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Vl
GZ
SN54ASC5202
MIN
Vl
SN74ASC5202
MAX
MIN
30
TVP*
57
TVP*
MAX
130
30
66
160
30
57
110
30
66
30
60
140
130
30
60
120
30
69
170
30
69
150
UNIT
pSipF
psipF
input buffer switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETERS§
CI)
tpLH
fn
tPHL
::r
tPLH
tpHL
CD
CD
....
dtPLH
dtpHL
(I)
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
Yl
Yl
Yl
Y2
Y2
V2
CL
CL
=
=
0
1 pF
SN54ASC5202
MIN
2.1
TVP*
2.6
MAX
4.3
SN74ASC5202
MIN
2.1
TVP*
2.6
MAX
4.1
2.1
2.9
5.4
2.1
2.9
4.9
3
4.4
8.4
3.1
4.4
7.8
3.1
5
10.9
3.2
5
9.6
0.9
1.8
4.1
0.9
1.8
3.7
0.9
2.1
5.5
1.1
2.1
4.7
UNIT
ns
ns
nsipF
tPropagation delay times are measured from the 44% point of VI with tr = tf = 3 ns 110% and 90%). For CMOS loads. the times end
at the 50% point of VO.
tpLH '" propagation delay time. low-to-high-Ievel output
AtPLH '" change in tpLH with load capacitance
dtPHL '" change in tPHL with load capacitance
tpHL '" propagation delay time. high-to-Iow-Ievel output
tpZH '" output enable time to high level
dtPZH '" change in tpZH with load capacitance
tpZL '" output enable time to low level
AtpZL '" change in tpZL with load capacitance
*Typical values are at VCC = 5 V. TA = 25°C.
§ Input propagation delay times are measured from the 50% point of VI to the 44% point of Vo with tr = tf = 4 ns.
DESIGN CONSIDERATIONS
Refer to Section 7.
4-562
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 ": DALLAS, TEXAS 75265
SN54ASC5203, SN74ASC5203
3·STATE 110 BUFFER WITH
INVERTING TTL INPUT AND CMOS/TTL OUTPUT
02939, AUGUST 1986
SystemCell™
•
Typical Propagation Delays
3.3 ns with 15-pF Load
5.5 ns with 50-pF Load
•
Output Current Ratings
SN54ASC5203 IOL
IOH
SN74ASC5203 IOL
IOH
•
logic symbol
A
3.4mA
-3.4 mA
4mA
-4mA
GZ _ _ _..J
Specified for Operation Over VCC
Range of 4.5 V to 5.5 V
•
Functional Operation Over VCC
Ranglilof2Vt06V
Y1
Y2
Incorporates Circuitry to Protect Against
ESD and Latch-Up
•
•
2·",m OUTPUT STANDARD CELL
FUNCTION TABLE
INPUTS
Dependable Texas Instruments Quality and
Reliability
A
GZ
Y1
OUTPUTS
Y1
Y2
L
L
L
L
H
L
H
H
L
X
H
L
Z
H
X
H
H
Z
L
H
positive logic equations
Y1 = A
Y2
= VI
description
The SN54ASC5203 and SN74ASC5203 are three-state input/output buffer standard-cells that interface
CMOS internal cells with TTL or CMOS bidirectional bus lines. The input buffer responds to TTL threshold
levels imposed on the I/O bus regardlel>5 of the state of the internal 3-state control GZ. The cell is designated
and called from the engineering workstation input using the following cell name and netlist label:
•
FEATURES
NETLIST
CELL NAME
IOF48LH
HDL LABEL
Label: IOF48LH A,GZ,Y2,Yl;
CELL LAYOUT
ASPECT RATIO
minimum width
RELATIVE
CELL AREA
TO NA210LH
45,2
The cell incorporates circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most common sources that can produce a latch-up condition.
These output cells have been designed to provide low-impedance drive levels for both the high- and lowlogic-level states. As a reSUlt, passive resistance has been purposely omitted in series with the output
transistors. Shorting a high-level output to ground or a low-level output to VCC will cause current flow
in excess of that recommended for normal operation. Therefore, it is recommended that outputs not be
shorted directly to ground or VCC.
The dynamic drive capability of each output is specified by the delta delay propagation time parameter
included with the switching characteristics. The delta delay times provide a means for making direct
comparisons of the various outputs response to change in capacitive loading.
The SN54ASC5203 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5203 is characterized for operation from -40°C to 85°C.
PRODUCTION DATA ....um.nts .ontllin inform.tio.
ourr.nt al of publicatio. dalO. Preducts co.form to
=IiCationl per !hi t..... of To.a. Instrum.nts
n"~~::i~at::I':.'li ~:~:~:; :'l"=:~:~ .ot
Copyright © 1986,· Texa·~ Instruments Incorporate
TEXAS •
INSTR,l..JMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-563
SN54ASC5203, SN74ASC5203
3·STATE I/O BUFFER WITH
INVERTING TTL INPUT AND CMOS/TTL OUTPUT
absolute maximum ratings and recommended operating conditions
See Table 4 in Section 2. Maximum high-level or maximum low-level output current is 3.4 milliamperes
for the SN54ASC5203 and 4 milliamperes for the SN74ASC5203.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VT
,~
Input threshold voltage VI
VOH High-level output voltage
VOL Low-level output voltage
=
Vee
TA
5 V.
=
MIN
25°e
4mA
10H 10H - -3.4 mA
2O/LA. See Note 1
10H 10L - 4 mA
TYP
Off·state output current
=
SN74ASC5203
MAX
MIN
TYP
2.2
2.2
1.3
1.3
MAX
3.7
V
Vee 0.1
Vee- O.1
0.5
0.5
See Note 1
2O/LA,
UNIT
V
3.7
10L - 3.4 mA
10L
10Z
SN54ASC5203
TEST CONDITIONS
Vo - Vee or 0
V
0.1
0.1
±10
±5
/LA
NOTE 1: These limits apply when all other outputs are open.
•
IOF48LH
PARAMETER
o
....
ICC
Supply current
Ci
Input capacitance
C\)
C\)
(I)
:::T
CD
CD
....
en
tfu
VI
Cpd
SN54ASC5203
TEST CONDITIONS
TYP
VI = Vec or 0 V
VI - 2 V or 0.8 V
Vce
=
5 V,
TA
=
25°e
t
= 5 V,
= 25°C
Equivalent power
VCC
dissipation capacitance
TA
tr
= tf =
3 ns,
MAX
SN74ASC5203
TYP
MAX
UNIT
2795
168
nA
1.43
1.32
mA
0.63
0.63
0.41
0.41
4.5
4.5
14.9
14.9
pF
pF
tTotal input capacitance for Y1 is dependent on the package type and is equal to the sum of package capacitance and intrinsic input
capacitance.
4-564
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75285
SN54ASC5203, SN74ASC5203
3-STATE I/O BUFFER WITH
INVERTING TTL INPUT AND CMOS/TTL OUTPUT
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
TTL loads, CL
PARAMETERt
tPLH
tpHL
tpZH
tpZL
=
15 pF
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
GZ
Yl
RL
Yl
~
SN54ASC5203
Typt
MAX
MIN
co
1.3
2.4
SN14ASC5203
Typt
MAX
MIN
5.7
1.4
2.4
5.1
2.1
4.2
10
2.2
4.2
8.9
RL - 1 kO to GND
1.5
3.3
8.1
1.6
3.3
7.3
RL - 1 kO to Vee
2
4.2
9.9
2.2
4.2
8.7
SN54ASC5203
Typt
MAX
MIN
UNIT
ns
ns
TTL loads, CL = 50 pF
PARAMETER t
tPLH
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
A
Yl
GZ
Yl
MIN
1.8
3.6
8.5
1.9
3.6
7.6
3.7
7.5
18
4
7.5
16
RL - 1 kO to GND
2
4.5
11
2.2
4.5
9.9
RL ~ 1 kO to Vee
3.7
7.7
19
4
7.7
16.3
RL
~
co
tPHL
tPZH
tpZL
tpHZ
tpLZ
GZ
Yl
SN74ASC5203
Typt
MAX
RL - 1 kO to GND
11
11
1 kO to Vee
10
10
RL
UNIT
ns
ns
ns
change in propagation delay time with load capacitance over recommended ranges of supply voltage •
and operating free-air temperature (unless otherwise noted)
PARAMETERt
<1tPLH
<1tpHL
<1tpZH
<1tpZL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Yl
GZ
SN54ASC5203
Typt
MAX
MIN
Yl
tpropagation delay times are measured from the 44% point of VI with tr ~
at Vo ~ 1.3 V.
tPLH '" propagation delay time, low-to-high-Ievel output
<1tpLH
tPHL '" propagation delay time, high-to-Iow-Ievel output
<1tpHL
tPZH '" output enable time to high level
<1tpZH
tpZL '" output enable time to low level
<1tpZL
tpHZ .. output disable time from high level
tpLZ 5i output disable time from low level
tTypical values are at Vee = 5 V, TA = 25°e.
SN74ASC5203
TYpt
MAX
MIN
10
34
80
20
34
70
50
94
220
50
94
190
10
54
80
20
54
70
50
100
250
50
100
210
ps/pF
CD
CD
~
U)
ps/pF
tf ~ 3 ns (10% and 90%). For TTL loads, the times end
'"
"
"
'"
...
U)
UNIT
...
CO
CO
C
change in tpLH with load capacitance
change in tpHL with load capacitance
change in tpZH with load capacitance
change in tpZL with load capacitance
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
4-565
SN54ASC5203, SN74ASC5203
3-STATE I/O BUFFER WITH
INVERTING TTL INPUT AND CMOS/TTL OUTPUT
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
CMOS loads, CL = 15 pF
PARAMETERt
tpLH
tpHL
tpZH
tpZL
FROM
(INPUT)
TO
(OUTPUT)
A
Y1
GZ
TEST
CONDITIONS
TYP*
MAX
1.S
3.1
1.8
3.S
RL - 1 kO to GND
2.1
RL - 1 kO to Vcc
1.7
RL =
Y1
SN74ASCS203
SNS4ASCS203
MIN
ex>
MIN
TYP*
MAX
7.3
1.6
3.1
6.S
8.2
1.9
3.5
7.3
4
9.5
2.2
4
8.4
3.3
7.8
1.8
3.3
6.9
UNIT
ns
ns
CMOS loads, CL - 50 pF
PARAMETERt
tpLH
tpHL
tpZH
tpZL
TO
(OUTPUT)
A
Y1
GZ
Y1
TEST
CONDITIONS
RL =
ex>
SN54ASC5203
SN74ASCS203
MAX
MIN
TYP*
MAX
2.5
TYP*
5.1
11.8
2.7
5.1
10.6
2.8
5.6
13.6
3
5.6
12
MIN
RL - 1 kO to GND
3
6.1
14.2
3.3
6.1
12.7
RL = 1 kO to Vcc
2.8
5.6
13.7
3
5.6
12
UNIT
ns
ns
change in propagation delay time with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
•
PARAMETERt
AtPLH
AtPHL
C
...
AtpZH
I»
I»
t/)
i'
...
AtpZL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
GZ
SNS4ASC5203
MIN
Y1
30
30
Y1
30
30
SN74ASCS203
TYP*
57
MAX
MIN
TYP*
MAX
130
30
57
120
60
150
30
60
130
60
65
130
170
30
60
65
120
30
150
UNIT
ps/pF
ps/pF
input switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
CD
(I)
FROM
(INPUT)
PARAMETER§
tPLH
tpHL
tpLH
tpHL
AtpLH
AtpHL
FROM
(INPUT)
Y1
Y1
Y1
TO
(OUTPUT)
Y2
Y2
Y2
TEST
CONDITIONS
CL
CL
=
=
0
1 pF
SNS4ASCS203
MIN
SN74ASCS203
MAX
MIN
TYP*
MAX
3
TYP*
6
14.6
3.2
1.1
1.4
2.2
1.1
6
1.4
13.6
2.1
6.5
13
32
7
13
29
2
3.7
1.4
2
3.4
7
17.3
0.6,
1.5
3.7
7
15.2
0.2
0.6
1.4
1.3
3.4
0.2
UNIT
ns
ns
ns/pF
t Propagation delay times are measured from the 44% point of VI with tr = tf = 3 ns (10% and 90%). For CMOS loads, the times end
at the SO% point of VO.
tpLH .. propagation delay time, low-to-high-Ievel output
AtPLH '" change in tpLH with load capacitance
tpHL '" propagation delay time, high-to-Iow-Ievel output
AtPHL .. change in tPHL with load capacitance
tPZH " output enable time to high level
AtpZH .. change in tpZH with load capacitance
AtpZL '" change in tpZL with load capacitance
tpZL '" output enable time to low level
*Typical values are at VCC = 5 V, TA = 2SoC.
§ Input propagation delay times are measured from the 1.3 V point of VI and the times end at the 44% point of Vo with tr = tf = 2 ns.
DESIGN CONSIDERATIONS
Refer to Section 7.
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
4-566
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC5206, SN74ASC5206
3-STATE I/O BUFFER WITH
NONINVERTING CMOS INPUT AND CMOS/TTL OUTPUT
02939. AUGUST 1986
SystemCell™
•
Typical Propagation Delays
3.3 ns with 15-pF Load
5.5 ns with 50-pFLoad
•
Output Current Ratings
SN54ASC5206 IOL
IOH
SN74ASC5206 IOL
IOH
•
•
•
•
2-",m OUTPUT STANDARD CELL
logic symbol
A
3.4 mA
-3.4 mA
4mA
-4 mA
GZ---..J
Yl
Y2
Incorporates Circuitry to Protect Against
ESD and Latch-Up
FUNCTION TABLE
INPUTS
Specified for Operation Over VCC
Range of 4.5 V to 5.5 V
Functional Operation Over VCC
Rangeof2Vt06V
Dependable Texas Instruments Quality and
Reliability
OUTPUTS
A
GZ
Yl
Yl
L
L
L
L
L
H
L
H
H
H
X
X
H
L
Z
L
H
H
Z
H
Y2
positive logic equations
Y1 = A
Y2 = Y1
...
fI)
description
The SN54ASC5206 and SN74ASC5206 are three-state input/output buffer standard-cells that interface
CMOS internal cells with TTL or CMOS bidirectional bus lines. The input buffer responds to CMOS threshold
levels imposed on the 110 bus regardless of the state of the internal 3-state control GZ. This cell function
exists in two versions ("E" and "F") with different physical implementations to allow the final IC area
to be optimized. Since the electrical performance of each version is identical, for simplicity only one version
(the "F" cell) will be contained in the engineering workstation cell libraries. Determination of the most
appropriate cell version will be made during the layout stage. The cell is designated and called from the
engineering workstation input using the following cell name and netlist label:
CD
CD
.c
(I)
...
CO
CO
C
FEATURES
NETLIST
CELL NAME
IOE41LH
IOF41LH
HDL LABEL
Label: IOF41 LH A,GZ, Y2, Y1;
CELL LAYOUT
ASPECT RATIO
RELATIVE
CELL AREA
TO NA210LH
minimum height
49.2
minimum width
49.4
The cells incorporate circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most common sources that can produce a latch-up condition.
These output cells have been designed to provide low-impedance drive levels for both the high- and lowlogic-level states. As a result, passive resistance has been omitted in series with the output transistors.
Shorting a high-level output to ground or a low-level output to VCC will cause current flow in excess of
that recommended for normal operation. Therefore, it is recommended that outputs not be shorted directly
to ground or VCC.
PRODUCTION DATA documents contain information
current as of publication data. Products conform to
specifications per the tarms of Taxas Instruments
::n.:!:=i~a{::1~1~ ~~~:~ti:; ~~D:::~9t~:'s~S not
~
. TEXAS
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
Copyright © 1986, Texas Instruments Incorporate
4-567
SN54ASC5206, SN74ASC5206
3·STATE I/O BUFFER WITH
NONINVERTING CMOS INPUT AND CMOS/TTL OUTPUT
description (continued)
The dynamic drive capability of each output is specified by the delta propagation delay time parameter
included with the switching characteristics. The delta propagation delay times provide a means for making
direct comparisons of the various outputs response to change in capacitive loading.
The SN54ASC5206 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5206 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 4 in Section 2. The maximum high-level or maximum low-level output current is 3.4 milliamperes
for the SN54ASC5206 and 4 milliamperes for the SN74ASC5206.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VT
,~
Input threshold voltage VI
VOH High-level output voltage
•
SN54ASC5206
TEST CONDITIONS
VCC
=
5 V,
TA
10H = -4 rnA
10H = -3.4 rnA
10H - -20 ~A,
=
MIN
25°C
TYP
SN74ASC5206
MAX
MIN
TVP
2.2
2.2
2.5
2.5
C
=
10l
3.7
See Note 1
V
Vee- O.1
Vce- O.1
0.5
0.5
3.4 rnA
10l - 20 ~A,
See Note 1
...m
m
NOTE 1: These limits apply when all other outputs are open.
~
IOE41LH
10Z
Off~state
CD
CD
...
output current
Vo
=
PARAMETER
ICC
Supply current
Ci
Input capacitance
Equivalent power
Cpd
VCC or 0
TVP
VI - VCC or 0
VI
~
GZ
VI t
dissipation capacitance
=
VCC
3.5 V or 0.9 V
=
5 V,
VCC = 5V,
TA = 25°C
TA
=
25°C
= tf =
tr
3 ns,
V
0.1
0.1
±10
±5
SN54ASC5206
TEST CONDITIONS
(I)
UNIT
V
3.7
10l - 4 rnA
VOL low-level output voltage
MAX
MAX
SN74ASC5206
TYP
MAX
~A
UNIT
2755
165
nA
3.26
2.86
rnA
0.6
0.6
0.42
0.42
4.09
4.09
16.7
16.7
pF
, pF
IOF41LH
ICC
Supply current
Ci
Input capacitance
SN54ASC5206
TEST CONDITIONS
PARAMETER
VI
VI
.~
GZ
= VCC
= 3.15
VCC
=
TVP
Equivalent power
dissipation capacitance
SN74ASC5206
TYP
MAX
UNIT
or 0
2579
155
nA
V or 0.9 V
2.96
2.58
rnA
5 V,
TA
=
25°C
Vlt
Cpd
MAX
VCC = 5 V,
TA = 25°C
tr
= tf =
3 ns,
0.62
0.62
0.44
0.44
3.83
3.86
14.3'
14.3
pF
pF
tTotal input capacitance for Y1 is dependent on the package type and is equal to the sum of package capacitance and intrinsic input
capacitance.
4-568
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN54ASC5206. SN74ASC5206
3·STATE I/O BUFFER WITH
NONINVERTING CMOS INPUT AND CMOS/TTL OUTPUT
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
TTL loads. CL = 15 pF
PARAMETERt
tpLH
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
MIN
TYP*
MAX
MIN
TYP*
MAX
=
2.5
6
10.2
1.4
2.5
4.3
5.3
00
1.3
2.1
9.1
1 k[J to GND
1.5
3.5
8.4
1.6
3.5
7.6
1 k[J to vee
2
4.2
10.4
2.2
4.2
9.2
A
Vl
tpZH,
GZ
Yl
RL
tpZL
GZ
Yl
RL
tpHL
RL
=
=
SN54ASC5206
4.3
SN74ASC5206
2.3
UNIT
ns
ns
TTL loads. CL - 50 pF
PARAMETERt
tpLH
tpHL
tpZH
tpZL
tpHZ
tpLZ
FROM
(INPUT)
TO
(OUTPUT)
A
Yl
GZ
Yl
GZ
RL
RL
RL
RL
=
=
=
=
SN74ASC5206
MIN TYP*
MAX
1.9
3.7
8.9
2
3.7
7.9
3.7
7.6
18.4
4
7.6
16.1
1 k[J to GND
2.1
4.6
11.4
2.2
4.6
10.3
1 k[J to Vee
1 k[J to GND
3.7
7.8
19.6
4
7.8
17
RL
y1
SN54ASC5206
MIN TYP*
MAX
TEST
CONDITIONS
=
00
1 k[J to Vee
11
11
10
10
UNIT
ns
ns
ns
change in propagation delay time with load capacitance over recommended ranges of supply voltage • .
and operating free-air temperature (unless otherwise noted)
PARAMETERt
lltpLH
lltpHL
lltpZH
lltpZL
FROM
(INPUT)
A
GZ
TO
(OUTPUT)
TEST
SN54ASC5206
CONDITIONS
Y1
V1
·SN74ASC5206
MIN
TYP*
MAX
MIN
TYP*
MAX
20
33
90
20
33
80
50
98
230
50
98
200
10
31
90
20
31
80
50
105
260
50
105
220
...
UJ
UNIT
CD
CD
ps/pF
.c
C/)
ps/pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
...caca
C
CMOS loads. CL - 15 pF
PARAMETERt
tpLH
tPHL
tpZH
tpZL
FROM
(INPUT)
A
GZ
TO
TEST
(OUTPUT)
CONDITIONS
SN74ASC5206
TYP*
MAX
MIN
3.3
7.6
1.7
3.5
8.4
1.9
3.5
6.8
7.4
RL - 1 k[J to GND
1.6
1.8
'2.1
4.2
9.8
2.3
4.2
8.8
RL - 1 kll to Vee
1.7
3.4
8.2
1.8
3.4
7.3
Yl
RL
Y1
SN54ASC5206
MIN
=
00
TYP*
3.3
MAX
UNIT
ns
ns
·r Propagation delay times are measured from the 44% point of VI with tr = tf = 3 ns (10% and 90%). For TTl loads, the times end
AT Vo = 1.3 V. For eMOS loads, the times end at the 50% point of VO·
tpLH " propagation delay time, low-to-high-Ievel output
lltpLH " change in tpLH with load capacitance
tpHL == propagation delay time, high-to-Iow-Ievel output
tpZH .. output enable time to high level
tpZL .. output enable time to low level
tpHZ " output disable time from high level
tpLZ .. output disable time from low level
*Typical values are at Vee = 5 V, TA = 25°e.
.6.tpHL == change in tpHL with load capacitance
lltpZH " change in tpZH with load capacitance
lltpZL " change in tpZL with load capacitance
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-569
•
SN54ASC5206, SN74ASC5.~06
3-STATE I/O BUFFER WJTH
NONINVERTING t:MOS INPUT AND CMOS/TTL OUTPUT
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
CMOS loads, CL - 50 pF
PARAMETERt
tpLH
tpHL
tpZH
FROM
(INPUT)
TO
(OUTPUT)
A
Yl
GZ
. TEST
CONDITIONS
RL =
00
RL = 1 kll to GND
Yl
RL - 1 kll to Vce
tPZL
SN~4ASC5206
SN74ASC5206
MIN
TYP*
MAX
MIN
TYP*
MAX
2.6
2.B
5.3
5.B
12.5
14.1
2.8
5.3
5.8
11.2
3
3.1
2.8
6.3
15.1
3.3
6.3
13.5
5.8
14.3
3
5.8
12.5
12.4
UNIT
ns
ns
change in propagation delay time with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
PARAMETERt
AtpLH
AtpHL
AtpZH
AtpZL
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
A
Yl
GZ
Yl
SN54ASC5206
MIN
TYP*
SN74ASC5206
MAX
MIN
MAX
30
57
150
30
TYP*
67
30
30
66
160
30
66
140
60
160
30
60
140
30
69
180
30
69
150
130
UNIT
ps/pF
ps/pF
input buffer switching cllaracteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER§
tpLH
tpHL
tpLH
tpHL
AtpLH
AtpHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
Yl
Y2
CL = 0
Yl
y2
Yl
Y2
CL = 1 pF
SN54ASC5206
MIN
SN74ASC5206
MAX
4.1
MIN
0.9
TYP*
1.8
1
1.8
3.4
1
2
1.1
2
0.1
0.1
1
TYP*
1.8
MAX
3.7
1.1
1.8
3.2
4.5
1.1
2
4
3.8
1.2
2
3.6
0.2
0.5
0.1
.0.2
0.4
0.2
0.5
0.1
0.2
0.4
UNIT
ns
ns
ns/pF
t Propagatio~ delay 'times are measured frorn the 44% point of VI with tr = tf = 3 ns (10% and 90%). For CMOS loads, the times end
at the 50% point of VO.
tPLH '" propagation delay time, low-to-high-Ievel output
AtpLH .. change in tpLH with load capacitance
tpHL '" propagation delay time, high-to-Iow-Ievel output
AtpHL '" ch~nge in tpHL with load capacitance
AtpZH '" change in tpZH with load capacitance
tPZH '" output enable time to high level
AtpZL '" change in tpZL with load capacitance
tpZL '" output enable time to low level
*Typical values are at VCC = 5 V, TA = 25°C.
§ Input propagation delay times are measured from the 50% point of VI to the 44% point of Va with tr = tf = 4 ns.
DESIGN CONSIDERATIONS
Refer to Section 7.
4-570
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 ,. DALLAS, TeXAS 75265
SN54ASC5207, SN74ASC5207
3-STATE I/O BUFFER WITH
NON INVERTING TTL INPUT AND CMOS/TTL OUTPUT
02939. AUGUST 1986
SystemCell™
•
Typical Propagation Delays
3.5 ns with 15-pF Load
5.8 ns with 50-pF Load
•
Output Current Ratings
SN54ASC5207 IOL
IOH
SN74ASC5207 IOL
IOH
2-llm OUTPUT STANDARD CELL
logic symbol
A~Yl
3.4 rnA
-3.4 rnA
4mA
-4mA
GZ
Y2
•
Incorporates Circuitry to Protect Against
ESD and Latch-Up
•
Specified for Operation Over VCC
Range of 4.5 V to 5.5 V
•
•
FUNCTION TABLE
INPUTS
A
Functional Operation Over VCC
Range of 2 V to 6 V
GZ
Yl
OUTPUTS
Yl
Y2
L
L
L
L
L
H
L
H
H
H
X
X
H
L
Z
L
H
H
Z
H
Dependable Texas Instruments Quality and
Reliability
positive logic equations
Y1 = A
Y2 = Y1
•
...
U)
description
Q)
Q)
The SN54ASC5207 and SN74ASC5207 are three-state input/output buffer standard-cells that interface
CMOS internal cells with TTL or CMOS bidirectional bus lines. The input buffer responds to TTL threshold
levels imposed on the I/O bus regardless of the state of the internal 3-state control GZ. This cell function
exists in two versions ("E" and "F") with different physical implementations to allow the final IC area
to be optimized. Since the electrical performance of each version is identical, for simplicity only one version
(the "F" cell) will be contained in the engineeririg workstation cell libraries. Determination of the most
appropriate cell version will be made during the layout stage. The cell is designated and called from the
engineering workstation input using the following cell name and netlist label:
.c
o
...a:sa:s
C
FEATURES
NETLIST
CEll NAME
IOE44LH
IOF44LH
CEll LAYOUT
ASPECT RATIO
HDllABEl
Label: IOF44LH A,GZ, Y2, Y1;
RELATIVE
CEll AREA
TO NA210lH
minimum height
49.2
minimum width
52.4
The cells incorporate circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby negating most common sources that can produce a latch-up condition.
These output cells have been designed to provide low-impedance drive levels for both the high- and lowlogic-level states. As a result, passive resistance has been omitted in series with the output transistors.
Shorting a high-level output to ground or a low-level output to VCC will cause current flow in excess of
that recommended for normal operation. Therefore, it is recommended that outputs not be shorted directly
to ground or VCC.
PRODUCTION DATA do.ument••ontein information
currant .s of publication date. Products conform to
specifications par
~h.
:.~=~;a[::I~~
tarms of
tl18S
Instruments
=:l::i:.n lI~D::;::lt::.~ not
TEXAS
~
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS. TEXAS 75265
Copyright ~ 1986. Texas Instrur:nents Incorp~lrateq
4-571
SN54ASC52D7, SN74ASC52D7
3-STATE I/O BUFFER WITH
NONINVERTING TTL INPUT AND CMOS/TTL OUTPUT
description (continued)
The dyn;lmic drive capability of each output is specified by the delta propagation delay time parameter
included with the switching characteristics. The delta propagation delay times provide a means for making
direct comparisons of the various outputs response to change in capacitive loading.
The SN54ASC5207 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5207 is characterized for operation from - 40°C to 85 DC.
absolute maximum ratings and recommended operating conditi.ons
See Table 4 in Section 2. The maximum high-level or maximum low-level output current is 3.4 milliamperes
for the SN54ASC5207 and 4 milliamperes for the SN74ASC5207.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VT
,~
Input threshold voltage VI
Vee
IOH
VOH High-level output voltage
•
VOL Low-level output voltage
C
CI)
Off-state output current
=
=
=
TA
5 V.
=
MIN
TYP
2.2
25°C
TYP
MAX
2.2
1.3
UNIT
V
1.3
3.7
3.7
V
Vee- O.1
See Note 1
Vee- 0.1
0.5
0.5
IOL - 3.4 rnA
Vo
SN74ASC5207
MIN
MAX
-4 rnA
-3.4 rnA
IOH
IOH - -20 ~A.
IOL = 4 rnA
IOL
IOZ
SN54ASC5207
TEST CONDITIONS
= 20 ~A,
= Vce or 0
See Note 1
V
0.1
0.1
±10
±5
~A
pot.
CI)
NOTE 1: These limits apply when all other outputs are open.
(/)
:r
IOE44LH
CD
CD
pot.
PARAMETER
en
ICC
Supply current
ei
Input capacitance
SN54ASC5207
TEST CONDITIONS
TYP
V, = Vee or 0
V, - 2 V'or 0.8 V
~
Vee
=
5 V,
TA
=
25°C
Vlt
epd
Equivalent power
dissipation capacitance
Vee = 5 V,
TA = 25°C
tr
= tf = 3
ns,
MAX
SN74ASC5207
TYP
MAX
2611
157
1.17
1.1
0.6
0.6
0.42
0.42
4.17
4.17
14.5
14.5
UNIT
nA
rnA
pF
pF
IOF44LH
PARAMETER
ICC
Supply current
ei
Input capacitance
epd
SN54ASC5207
TEST CONDITIONS
TYP
V, = Vee or 0
V, = 2 V or 0.8 V
~
GZ
VI t
Equivalent power
dissipation capacitance
Vee = 5 V,
Vee = 5 V,
TA = 25°C
tr = tf = 3 ns,
TA = 25°C
MAX
SN74ASC5207
TYP
MAX
UNIT
2725
163
nA
1.2
1.12
rnA
0.6
0.6
0.48
0.48
4.23
4.23
14.3
14.3
pF
pF
tTotal input capaciatance for the Y1 input is dependent on the package type and is equal to the sum of package capacitance and intrinsic
input capacitance.
4-572
'
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 65501'2 • DALLAS. TEXAS 75265
SN54ASC5207, SN74ASC5207
3-STATE I/O BUFFER WITH
NON INVERTING TTL INPUT AND CMOS/TTL OUTPUT
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
TTL loads, CL - 15 pF
PARAMETERt
tPLH
tpHL
tpZH
tpZL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
GZ
TVP*
MAX
MIN
TVP*
MAX
5.9
1.4
5.2
9.9
00
1.3
2.1
2.5
4.5
11.1
2.2
2.5
4.5
1 kO to GND
1.5
3.4
8.4
1.7
3.4
7.6
RL - 1 kO to Vee
2
4.4
11.3
2.2
4.4
9.9
SN54Ase5207
MIN TVP*
MAX
8.9
1.9
3.7
MIN
RL
Vl
RL
Vl
SN74ASC5207
SN54ASC5207
MIN
~
~
UNIT
ns
ns
TTL loads, CL - 50 pF
PARAMETERt
tpLH
tpHL
tpZH
FROM
(INPUT)
A
GZ
GZ
CONDITIONS
Vl
RL
RL -
Vl
RL
tpZL
tPHZ
tpLZ
TEST
TO
(OUTPUT)
Vl
~
~ 00
SN74ASC5207
MAX
TVP*
2
3.7
7.9
3.7
8
20.3
4
B
17.7
1 kO to GND
2.1
4.6
11.4
2.2
4.6
10.2
1 kO to Vec
3.7
B
21.B
4.1
B
18.B
RL -
1 kO to GND
RL -
1 kO to Vee
11
10
11
10
UNIT
ns
ns
ns
change in propagation delay time with load capacitance over recommended ranges of supply voltage . and operating free-air temperature (unless otherwise noted)
_
PARAMETERt
tpLH
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Yl
GZ
Yl
MpHL
f>tpZH
f>tpZL
SN54ASC5227
Typt
MAX
MIN
SN74ASC5227
Typt
MAX
MIN
10
17
50
10
17
40
20
40
100
20
40
so
10
20
50
10
20
40
20
43
110
20
43
90
UNIT
ps/pF
ps/pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
tpLH
tpHL
tpZH
tpzL
CMOS loads, CL
PARAMETERt
tpLH
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Yl
GZ
tpZL
!
SN74ASC5227
Typt
MAX
MIN
1.3
2.5
5.9
1.4
2.5
5.2
1.5
3
6.8
1.6
3
6.1
RL - 1 kll to GND
1.7
3.3
7.6
1.8
3.3
6.8
RL - 1 kll to VCC
1.4
2.7
6.1
1.5
2.7
5.5
SN54ASC5227
Typt
MAX
MIN
RL
Yl
SN54ASC5227
Typt
MAX
MIN
~ 00
..c
UNIT
en
ns
+or
C'CS
C'CS
C
ns
50 pF
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
Yl
GZ
Yl
tPHL
tpZH
f/)
+or
Q)
Q)
CMOS loads. CL = 15 pF
PARAMETERt
II
RL
~
MIN
1.8
3.6
2
00
SN74ASC5227
Typt
MAX
1.9
3.6
7.5
4
8.3
9.3
2.1
4
8.3
RL
~
1 kll to GND
2.2
4.4
10.2
2.4
4.4
9.1
RL
~
1 kll to Vee
2
3.8
8.9
2.1
3.8
8
UNIT
ns
ns
Propagation delay times are measured from the 44% point of VI with tr = tf = 3 ns (10% and 90%). For TTL loads, the times end
at Vo ~ 1.3 V. For eM OS loads, the times end at the 50% point of Vo.
tpLH '= propagation delay time, low-to-high-Ievel output
L'ltpLH == change in tpLH with load capacitance
tpHL := propagation delay time. high-to-Iow-Ievel output
tpZH '= output enable time to high level
tpZL =: output enable time to low level
tpHZ = output disable time from high level
tplZ == output disable time from low level
tTypical values are at Vee ~ 5 V, TA ~ 25°e.
~tpHL =:
change in tpHL with load capacitance
LltpZH == change in tpZH with load capacitance
LltpZL == change in tpZl with load capacitance
TEXAS
-1.!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-593
SN54ASC5227, SN74ASC5227
3·STATE 1/0 BUFFER WITH
NONINVERTING TTL INPUT AND CMOS/TTL OUTPUT
change in propagation delay time with load capacitance over recommended ranges of supply voltage
and oPerating free·air temperature (unless otherwise noted)
PARAMETERt
4tpLH
4tpHL
4tpZH
4tPZL
FROM
(INPUT)
TO
(OUTPUT)
A
Y1
GZ
Y1
TEST
CONDITIONS
SN54ASC5227
SN74ASC5227
MIN
TYP*
. MAX
10
31
70
10
29
70
10
31
70
20
31
70
20
31
80
20
31
79
MIN
20
10·
TYP*
MAX
31
60
29
60
UNIT
ps/pF
ps/pF
input buffer switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER§
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
tPLH
tpHL
Y1
Y2
CL = 0
tPLH
tpHL
Y1
Y2
CL = 1 pF
4tpLH
4tpHL
Y1
Y2
SN54ASC5227
SN74ASC5227
MAX
2.6
M(N
O.B
TYP*
1.4
0.9
TYP*
1.4
1.3
2.6
5.9
1.4
2.6
2.4
5.3
3.1
MIN
MAX
1
1.7
3.3
1
1.7
1.5
2.9
6.8
1.6
2.9
6
0.,
0.3
0.8
0.1
0.3
0.7
0.2
0.3
0.9
0.2
0.3
O.B
UNIT
ns
ns
ns/pF
tpropagation delay times are measured from the 44% point of VI with tr = tf = 3 ns (10% and 90%). For CMOS loads, the times end
at the 50% point of VO.
tpLH '" propagation delay time, low-to-high-Ievel output
4tPHL '" change in tpHL with load capacitance
4tpZH .. change in tpZH with load capacitance
tPHL '" propagation delay time, high-to-Iow-Ievel output
4tpLH .. change in tpLH with load capacitance
4tpZL .. change in tpZL with load capacitance
*Typical values are at VCC = 5 V, TA '" 25°C.
§ Input propagation delay times are measured from the 1.3 V point of VI to the 44% point of Vo with tr = tf = 2 ns.
DESIGN CONSIDERATIONS
Refer to Section 7.
4-594
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC5239, SN74ASC5239
3-STATE I/O BUFFER WITH
NONINVERTING TTL INPUT AND CMOS/TTL OUTPUT
ADVANCE
INFORMATION
02939, AUGUST 1986
SystemCell™
•
Typical Propagation Delays
2,7 ns with 15-pF Load
3,7 ns with 50-pF Load
•
OutPUt Current Ratings
SN54ASC5239 IOL
IOH
SN74ASC5239 IOL
IOH
2-/lm OUTPUT STANDARD CELL
logic symbol
A;tJ-Vl
20.4 mA
-10.2 mA
24mA
-12 mA
GZ
V2
•
Incorporates Circuitry to Protect Against
ESD and !-atch-Up
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
•
FUNCTION TABLE
INPUTS
A
Functional Operation Over VCC Range of
2Vt06V
GZ V1
OUTPUTS
V1 V2
l
l
l
l
l
H
l
H
H
H
X
H
l
Z
l
X
H
H
Z
H
Dependable Texas Instruments Quality and
Reliability
positive logic equations
Y1 = A
Y2 = Y1
•
...
CI)
description
The SN54ASC5239 and SN74ASC5239 are 3-state input/output buffer standard-cell functions that
interface CMOS internal cells with TTL or CMOS bidirectional bus lines, The input buffer responds to TTL
threshold levels imposed on the 110 bus regardless of the state of the internal 3-state cOritrol GZ, The cell
is designated and called from the engineering workstation input using the following cell name and netlist
label:
Q)
Q)
.c
(fJ
...'"
C'"
FEATURES
CELL NAME
IOFB8lH
NETLIST
CELL LAVOUT
HOL LABEL
ASPECT RATIO
label: IOFB8lH A,GZ,V2,Vl;
minimum width
RELATIVE
CELL AREA
TO NA210LH
73.4
The cell incorporates circuit elements designed to actively bypass and dissipate electrostatic discharges
with potentials ranging up to 4 kilovolts. Guard-ring structures are employed that provide current
management techniques for the cell to recover from exposure to high currents of up to 400 milliamperes,
thereby nA~atin~ mo!C;t r.nmmnn ~nllrr.AC:: th~t I""~n :-,rnf.ll.II"O ~ I~-t:':"~-I_~~ ~':"~~~'!:~~~_
These output cells have been designed to provide low-impedance drive levels for both the high- and lowlogic-level states. As a result, passive resistance has been omitted in series with the output transistors,
Shorting a high-level output to ground or a low-level output to VCC will cause current flow in excess of
that recommended for normal operation. Therefore, it is recommended that outputs not be shorted directly
to ground or VCC,
The dynamic drive capability of each output is specified by the delta propagation delay time parameter
included with the switching characteristics. The delta propagation delay times provide a means for making
direct comparisons of the various output responses with change in capacitive loading.
ADVANCE INFORMATION do.uments .ontein
information DR new rroduets in the sampling or
~"",roduction ph... 0 davelopmont, Characteristics
iIota and other spacifications ar. subject to change
without notice.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
Copyright © 1986, Texas Instruments Incorporated
4-595
S1II54ASC5~39r SN74ASC5239
3-STATE lib IiUFFER WITH
NONINVERTING tTL INPUT AND CMOS/TTL OUTPUT
description (continued)
The SN54ASC5239 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC5239 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 4 in Section 2. The maximum high-level output current is 10.2 milliamperes for the
SN54ASC5239 and 12 milliamperes for the SN74ASC5239. The maximum low-level output current is
20.4 milliamperes for the SN54ASC5239 and 24 milliamperes for the SN74ASC5239.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VT
SN54ASC5239
TEST CONDITIONS
Input threshold
I A,GZ
voltage
I Y1
=
Vee
TA
5 V,
=
MIN
TYP
2.2
25°C
IOH =
IOH - -10.2 mA
MAX
High-level output voltage
1.3
•
c
....
en
:::r
ur
3.7
V
Vee- O.1
Vee- D.1
0.5
lal - 20.4 mA
IOl
C»
C»
(1)
(1)
low-level output voltage
=
20 pA,
0.5
See Note 1
IOZ
Off·state output current
Vo - Vee or 0
ICC
Supply current
VI - Vee or 0
Vi = 2 V or 0.8 V
ei
IA
Input capacitance I GZ
Vee
=
5 V,
Equivalent power
dissipation capacitance
Vee = 5 V,
TA = 25°C
TA
tr
V
0.1
0.1
±10
±5
~A
4538
272
nA
1.12
mA
1.2
=
25°C
I Y1 t
epd
UNIT
V
1.3
Idl - 24 mA
VOL
MAX
3.7
- 20 pA, See Note 1
IOH -
TYP
2.2
-12 mA
VOH
SN74ASC5239
MIN
= tf =
3 ns,
1.18
0.89
1.18
0.89
7.39
7.39
28.2
28.2
pF
pF
tTotal input capacitance is dependent on the package type and is equal to the sum of package capacitance and intrinsic input capacitance.
NOTE 1: These limits apply when all other outputs are open.
4-596
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC5239. SN74ASC5239
3-STATE I/O BUFFER WITH
NON INVERTING TTL INPUT AND CMOS/TTL OUTPUT
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
TTl loads, CL = 15 pF
PARAMETERt
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
tpLH
tpHL
tpZH
tpZL
TTl loads, CL
PARAMETERt
A
V1
GZ
V1
RL
=
SN54ASC5239
MIN
TVP*
MAX
SN74ASC5239
MIN
2.3
3.2
00
TVP*
2.3
MAX
ns
3.2
RL - 1 kO to GND
2.7
2.7
RL - 1 kO to Vee
3
3
UNIT
ns·
50 pF
FROM
(INPUT)
tpLH
tpHL
tpZH
tpZL
tpHZ
A
V1
GZ
V1
GZ
tPLZ
TO
(OUTPUT)
TEST
CONDITIONS
RL
VI
=
SN54ASC5239
MIN TVP*
MAX
00
SN74ASC5239
MIN
2.9
TVP*
2.9
4.2
4.2
RL - 1 kO to GND
3.4
3.4
RL = 1 kO to Vee
RL - 1 kO to GND
4.2
4.2
10
10
RL - 1 kO to Vee
9
9
MAX
UNIT
ns
ns
ns
change in propagation delay time with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
PARAMETERt
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
V1
GZ
V1
LitpLH
LitPHL
LitpZH
LitpZL
SN54ASC5239
MIN
TVP*
MAX
SN74ASC5239
MIN
17
TVP*
17
29
29
20
20
34
34
MAX
...
II)
UNIT
CD
CD
ps/pF
.c
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
CMOS loads, CL
PARAMETERt
tpLH
tpHL
tpZH
tpZL
=
en
ca
ca
...
ps/pF
C
15 pF
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
V1
GZ
V1
RL
RL
=
RL -
=
SN54ASC5239
MIN
00
TVP*
2.7
MAX
SN74ASC5239
MIN
TVP*
2.7
2.8
2.8
1 kO to GND
3.2
3.2
1 kO to Vee
2.6
2.6
tPrnn&:l'2'~tinn rlAI~~1 tirnp.~ ~rJ:> rTH"::I~lIrp.rI frorn th", 4.dOh ~t'lin1' nf ": .... i-th
1',_ "..,. ... ~
at Vo = 1.3 V. For eMOS loads, the times end at the 50% pOint of VO.
tpLH '" propagation delay time, low-to-high-Ievel output
LitpLH
tpHL '" propagation delay time, high-to-Iow-Ievel output
LitpHL
tpZH '" output enable time to high level
LitpZH
tPZL " output enable time to low level
LitpZL
tpHZ .. output disable time from high level
tpLZ '" output disable time from low level
Typical values are at Vee = 5 V, T A = 25°e.
'"
'"
'"
'"
MAX
UNIT
ns
ns
-.~ ne> ~1not. <>"~ Qnot.~ t:,.. .. TTl I...... ~~ ... h ..... i ..... """"
"" ......
change in tpLH with load capacitance
change in tpHL with load capacitance
change in tpZH with load capacitance
change in tpZL with load capacitance
*
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-597
SN54ASC5239, SN74ASC5239
3-STATE I/O BUFFER WITH
NONINVERTING TTL INPUT AND CMOS/TTL OUTPUT
switching charac;:teristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (continued)
CMOS loads, CL
PARAMETERt
tpLH
tPHL
tpZH
=
50 pF
FROM
(INPUT)
TO
(OUTPUT)
A
VI
GZ
tpZL
TEST
CONDITIONS
=
RL
VI
SN54ASC5239
MIN
TVP*
3.7
00
MAX
SN74ASC5239
MIN
TVP*
MAX
3.7
3.6
RL -' 1 kll to GND
4.2
3.6
4.2
RL - 1 kll to Vcc
3.5
3.5
UNIT
ns
ns
change in propagation delay time with load capacitance over recommended ranges of supply voltage
and operating free-air temperature (unless otherwise noted)
PARAMETERt
-.
Range of
Range of
FUNCTION TABLE
positive logic equation
Y = (A 1.A2)
INPUTS
+ (81.82)
OUTPUT
AI
A2
BI
B2
H
H
X
X
L
X
X
H
H
L
Y
Any other
H
combination
description
The SN54ASC6003 and SN74ASC6003 are 2-wide. 2-input AND-OR gate CMOS standard cells. The cells
are designated and called from the engineering workstation input using the following cell name to develop
labels for the design netlist:
CELL NAME
BF003LH
TYPICAL
.c
RELATIVE
HDL LABEL
DELAY
CELL AREA
TO NA210LH
Label: BF003LH Al,A2,Bl,B2,Y;
CL - I pF
2,6 ns
o
CI)
CI)
FEATURES
NETLIST
II
....
en
....CISCIS
1.75
Q
The SN54ASC6003 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC6003 is characterized for operation from - 40°C to 85 °C,
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
Equivalent power
Vee - 5 V,
voltage
ISN54Ase6003
ISN74ASe6003
Cpd dissipation capacitance
PRODUCTION DATA do.omants contain information
currant B~ of publication date. Products conform to
.pacifications per the tarms of Taxas Instruments
standard warranty. Production ~rocessing d~s not
nac8ISsri.y iflcluda testing of all paramat!fS.
TVP
TEST CONDITIONS
Input capacitance
thres~old
ICC Supply current
ei
I
I
= 5 V,
= 4.5 V to 5.5 V,
TA = MIN to MAX
Vee = 5 V,
I VT Input
Vee
Vee
TA
=
TA
VI
= 25°C
= Vee or 0,
MAX
2.2
:lLU
13.2
TA = 25°C
t r - tf - 3 ns,
25°C
I UNIT I
I V I
nA
0.13
pF
0.51
pF
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-609
SN54ASC6003, SN74ASC6003
AND·NOR GATES
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETERt
tpLH
FROM
(INPUT)
tpHL
tltpLH
tltpHL
TEST
CONDITIONS
Any
Y
Any
Y
tpHL
tpLH
TO
(OUTPUT)
Any
CL
CL
~
~
0
1 pF
Y
SN54ASC6003
SN74ASC6003
MIN
TYP*
MAX
MIN
TYP*
MAX
0.7
1.2
2.7
0.7
1.2
2.5
0.3
1
2
0.4
1
1.9
1.6
3.2
2
7.2
1.7
4.5
0.9
3.2
2
6.6
0.9
0.9
2
4.6
1
2
4.2
0.5
0.9
2.5
0.5
0.9
2.2
t Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr ~ tf
tpLH '" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
tltPLH '" change in tpLH with load capacitance
tltpHL '" change in tpHL with load capacitance
*Typical values are at VCC = .5 V, TA ~ 25°C.
DESIGN CONSIDERATIONS
III
Refer to the 'ASC60 1 7 data sheet and Section 7.
C
...
I»
I»
en
:::r
CD
CD
...
(II
4-610
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 6!l5Qi 2 • DALLAS. TEXAS 15265
=3
4
UNIT
ns
ns
ns/pF
ns (10% and 90%1.
SN54ASC6004. SN74ASC6004
AND·NOR GATES
v = (A1.A2) + (81·82.83)
02939, AUGUST 1986
SystemCeIrM
2-/-Im INTERNAL STANDARD CELL
•
2,8 ns Typical Propagation Delay with 1-pF
Load
•
Specified for Operation Over Vee Range of
4,5 V to 5,5 V
•
Functional Operation Over Vee Range of
logic symbol
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
FUNCTION TABLE
INPUTS
positive logic equation
+ (81·82·83)
Y = (A1.A2)
OUTPUT
A1
A2
B1
B2
B3
Y
H
H
X
X
X
L
X
X
H
H
H
l
H
Any other combination
description
The SN54ASC6004 and SN74ASC6004 are 2-wide, 2-3-input AND-NOR gate CMOS standard cells, The
cell is designated and called from the engineering workstation input using the following cell name to develop
labels for the design netlist:
FEATURES
CELL NAME
BF004lH
NETLIST
TYPICAL
RELATIVE
HDL LABEL
DELAY
CELL AREA
U)
TO NA210LH
CL - 1 pF
label: BF004LH A 1,A2,B1 ,B2,B3,Y;
2.8 ns
II
..
CD
CD
1.75
.c
The SN54ASC6004 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC6004 is characterized for operation from - 40°C to 85 DC.
en
..
ca
ca
C
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2,
electrical characteristics
PARAMETER
TEST CONDITIONS
VT Input threshold voltage
I SN54ASe6004
ICC Supply current
SN74ASe6004
Vec - 5 V,
4.5 V to 5.5 V,
Vec
I
Cj
TA
Input capacitance
.-
.
..
.
.... '-I .... 'vc" ..... ~ t-'V." ... ,
Cpd dissipation capacitance
I
PRODUCTION DATA documents contain information
carnnt as of publication data. Products conform to
specificatioos per the terms of Texas Instruments
=:~:=i~ai~:r.~~ ~!:~:~:; :'~U:::::~:'8
~
Vee
not
.......
\'-TA
~
TYP
5 V,
""
V
nA
14.2
MIN to MAX
~
UNIT
237
Vee or 0,
VI
MAX
2.2
TA - 25°C
.
TA
"
~
25°C
"
25°C
~
pF
0.13
""
I
0.53
I
p~
I
Copyright © 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICI: BOX 655012 • DALLAS, TEXAS 75265
4-611
SN54ASC6004, SN74ASC6004
AND·NOR GATES
switching characteristics over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise rioted)
PARAMETERt
tpLH
FROM
TO
TEST
UNPUT)
(OUTPUT)
CONDITIONS
Any
y
tPHL
tPLH
tpHL
.l.tpLH
.l.tpHL
Any
Y
Any
Y
SN74ASC6004
TYP*
MAX
MIN
=0
0.6
1'.3
2.7
0:7
TYP*
1.3
0.4
1
2.1
1.9
= 1 pF
3.3
2.2
6.4
0.4
1.7
1
1.6
3.3
2.2
5.9
4.4
0.9
2
3.8
2
3.5
0.5
1.2
3
1.2
2.6
CL
CL
SN54ASC6004
MIN
0.9
5
tpropagation delay times are measured from the 44% point of VI to the 44% point ~f Vo with tr
tpLH '" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
.l.tPLH = change in tpLH with load capacitance
.l.tpHL .. change in tpHL with load capaCitance
Typical values are at VCC = 5 V, TA = 25°C.
*
DESIGN CONSIDERATIONS
II
4-612
Refer to the' ASC6017 data sheet and Section 7.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1
1
0.5
= tf =
MAX
2.5
UNIT
ns
ns
ns/pF
3 ns (10% and 90%).
SN54ASC6005. SN74ASC6005
AND·NOR GATES
v == (A1·A2·A3)+(B1.B2.B3)
02939. AUGUST 1986
SystemCell™
2-llm INTERNAL STANDARD CELL
•
3 ns Typical Propagation Delay with 1-pF
Load
•
Specified for Operation Over
4.5 V to 5.5 V
•
Functional Operation Over
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
Vee
Vee
logic symbol
~:---t-_>-'
Range of
Range of
FUNCTION TABLE
positive' logic equation
Y
=
(A 1·A2·A3)
INPUTS
+ (81·82.83)
OUTPUT
A1
A2
Al
B1
B2
H
H
H
X
X
X
X
X
H
H
B3
X
H
Any other combination
Y
L
L
H
description
The SN54ASC6005 and SN74ASC6005 are 2·wide, 3-input AND-NOR gate CMOS standard cells. The
cell is designated and called from the engineering workstation input using the following cell name to develop
labels for the design netlist:
FEATURES
NETLIST
TYPICAL
RELATIVE
HDL LABEL
DELAY
CELL AREA
CL - 1 pF
3 ns
TO NA210LH
Label: BF005LH Al.A2,Al,B1.B2.Bl.Y;
CELL NAME
BF005LH
•
2
The SN54ASC6005 is characterized for operation over the full military temperature range of - 55 DC to
125 DC. The SN74ASC6005 is characterized for operation from -40 DC to 85 DC.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
TEST CONDITIONS
VT Input threshold voltage
SN54Ase6005
lee Supply current
! SN74ASC6005
Vee - 5
I
ej
Input capacitance
I
Equivalent power
Cpd dissipation capacitance
TYP
TA - 25°e
Vee = 4.5 V to 5.5 V.
TA = MIN to MAX
VI
= 5 V.
Vee = 5 V.
TA = 25°e
TA
Vee
PRODUCTION DATA d...mants contain imarmati ••
currant I. of publication data. Products co.form ta
opacifications par tho torms of T.... Instruments
:'=~~i~·ir,::r.'li ~::~~:r :II"::~~:'~ lot
v,
=
MAX
2.2
V
266
Vee or O.
15.9
tr
= 25°e
= tf = 3 ns.
UNIT
nA
0.13
pF
0.64
pF
J
Copyright © 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFl=ICE
sox 656012
• DALLAS, .TEXAS 76266
4-613
SN54ASC6005, SN74ASC6005
AND-NOR GATES
switching charac~eristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
,
PARAMETERt
tpLH
FROM
(INPUT)
Any
tpHL
.tpLH
tpHL
AtPLH
AtpHL
Any
Any
TO
TEST
(OUTPUT)
CONDITIONS
Y
Y
=
CL
CL
=
°
1 pF
V
SN54ASC6005
SN74ASC6005
MIN
0,7
TVP*
1,5
MAX
3,3
MIN
0,7
TVP*
1,5
MAX
0,5
1.2
3,5
2,4
1,6
7,1
0,5
1,7
1.2
3,5
2.1
6,5
1,1
2.5
5,2
1,2
2.5
4.5
0,9
2
1,3
3,B
1
0,6
2
1,3
3,5
0.6
3
3,1
2,5
UNIT
ns
ns
nsipF
t Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%1.
tPLH " propagation delay time, low-to-high-Ievel output
tpHL " propagation delay time, high-to-Iow-Ievel output
AtPLH " change in tpLH with load capacitance
AtpHL " change in tpHL with load capacitance
Typical values are at VCC = 5 V, T A = 25 DC.
*
DESIGN CONSIDERATIONS
II
Refer to the 'ASC6017 data sheet and Section 7,
C
m
m
....
t/)
:::T
CD
CD
....
(I)
4-614
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC6006, SN74ASC6006
AND-NOR GATES
Y
=
A1 +A2+(B1.B2)
02939. AUGUST 1986
SystemCell™
2-~m INTERNAL STANDARD CEL~
•
Typical Propagation Delay with 1-pF Load
3 ns from Any A
3.2 ns from Any B
•
Specified for Operation Over
4.5 V to 5.5 V
•
Functional Operation Over
2Vt06V
•
Vee
logic symbol
B1
Range of
B2
A1
~
.
Y
A2
Vee
Range of
FUNCTION TABLE
INPUTS
Dependable Texas Instruments Quality and
Reliability
positive logic equation
Y = A1 +A2+(B1·B2)
OUTPUT
A1
A2
B1
B2
Y
H
X
X
X
L
X
H
X
X
L
X
X
H
H
L
L
L
L
X
H
L
L
X
L
H
description
The SN54ASC6006 and SN74ASC6006 are expandable 1-1-2-input AND-NOR gate CMOS standard cells. •
The cells are designated and called from the engineering workstation input using the following cell name
:.
to develop labels for the design netlist:
CELL NAME
BF006LH
...
II)
RELATIVE
NETLIST
CD
CD
CELL AREA
HDL LABEL
TO NA210LH
.c
1.75
Label: BF006LH A1.A2.B1,B2,V;
U)
The SN54ASC6006 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC6006 is characterized for operation from - 40°C to 85 DC.
...
CU
CU
C
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
TEST CONDITIONS
Vee = 5 V.
Vee - 4.5 V to 5.5 V,
VT Input threshold voltage
ISN54Ase6006
lee Supply Current
ISN74ASe6006
I::'
TA
.
.
-'.
"'I-' ... L ..... "" ....... L""' .......
=
'"''
Vee
Equivalent power
Cpd dissipation capacitance
TA
=
25°C
-
"
- 5 V.
13.3
T.
_ ..,c:or-
:.~~~:~~;ar::1~1~ =:~ti;; :I~o:=::~~~s
not
UNIT
V
222
VI - Vee or 0,
nA
roo , ?
~O
0.36
pF
.~
tr - tf - 3 ns,
25°e
Copyright © 1986, Texas Instruments Incorporated
PRODUCTION DATA documonts contain informotion
current as of publication date. Products conform to
specifications par the terms of Tuas Instruments
MAX
2.2
MIN to MAX
0:'"
=
TYP
TA
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-615
SN54ASC6006, SN74ASC6006
AND-NOR GATES
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted~'
PARAMETERt
tPLH
tpHL
tpHL
tPLH
tpHL
tpHL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
Any
Y
Y
Y
Y
Y
Y
y
Any A
Any B
Any
Any A
Any B
dtpLH
Any
dtpHL
Any A
dtpHL
Any B
CL = 0
CL = 1 pF
Y
Y
SN54ASC6006
TYP:):
MAX
MIN
SN74ASC6006
TYP:):
MAX
MIN
0.8
1.5
4.1
0.8
1.5
3.7
0.2
1.6
0.3
0.8
1.6
0.4
0.8
1
2
11
0.5
2.3
1
4.5
1.9
9.9
2.2
4.5.
0.7
1.4
3
0.8
1.4
2.8
0.9
1.9
4.6
1
1.9
4
6.3
1.4
3
7
1.5
3
0.4
0.6
1.4
0.4
0.6
1.2
0.5
0.9
2.6
0.5
0.9
2.2
UNIT
ns
ns
ns/pF
tpropagation delay times are measured from the 44% point of VI to the 44% pOint of Va with tr = tf = 3 ns (10% and 90%1.
tPLH " propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
dtpLH " change in tpLH with load capacitance
dtpHL '" change in tpHL with load capacitance
:):Typical values are at VCC = 5 V, TA = 25°C .
•
C
DESIGN CONSIDERATIONS
Refer to the 'ASC60 1 7 data sheet and Section 7.
I»
r+
I»
rn
::::r-
CD
.CD
r+
'en
4·616
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DAL.LAS, TEXAS 75265
SN54ASC6007. SN74ASC6007
AND-NOR GATES
Y == A1+A2+(B1.B2.B3)
02939, AUGUST 1986
SystemCell''''
2-",m INTERNAL STANDARD CELL
•
Typical Propagation Delay with '-pF Load
3,2 ns from Any A
3,7 ns from Any B
•
Specified for Operation Over
4.5 V to 5.5 V
•
Functional Operation Over
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
Vee
Vee
logic symbol
rp--
A1------,
~d
Range of
A2------..J
Range of
FUNCTION TABLE
INPUTS
positive logic equation
Y = A1 +A2+(B1.B2.B3)
OUTPUT
A1
A2
B1
B2
B3
Y
H
X
X
X
X
L
X
H
X
X
X
L
X
X
H
H
H
L
L
L
L
X
X
H
L
L
X
L
X
H
L
L
X
X
L
H
description
The SN54ASC6007 and SN74ASC6007 are expandable 1-1-3-input AND-NOR gate CMOS standard cells.
The cells are designated and called from the engineering workstation input using the following cell name
to develop labels for the design netlist:
CELL NAME
BF007LH
~
CELL AREA
HDL LABEL
...caca
TO NA210LH
1.75
Label: BF007LH A 1,A2,B1,B2,B3,Y;
U)
CD
CD
RELATIVE
NETLIST
a...
The SN54ASC6007 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC6007 is characterized for operation from - 40°C to 85 DC.
C
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
I VT
~~.-
ICC Supply current
Cj
TYP
TEST CONDITIONS
Input threshold voltage
..... .-,. ...........
I
-.......
!
\,
I;~;;~;;~~~;
TA
~
Vee ~ 5 V,
Equivalent power
Vee - 5 V,
Cpd dissipation capacitance
TA
PRODUCTION DATA do•• mants oontaln information
currant as of publicatian date. Products conform to
specificaliaDs per the terms of TaxBI Instruments
=~:=i~ai:,~7e ~1~~~; :UD=:~;:S
not
~
14.4
tr - tf - 3 ns,
25°C
UNIT
v
240
MIN to MAX
Input capacitance
MAX
2.2
nA
0.13
pF
0.36
pF
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-617
SN54ASC6007, SN74ASC6007
GATES
switching characteristics over recommended ranges of supj:lly voltage and operating free-air temperature
(unless otherwise noted)
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
tpLH
Any
Y
tpHL
Any A
tpHL
Y
y
tpLH
Any B
Any.
tpHL
Any A
tPHL
t.tPLH
t.tpHL
Any B
Any A
t.tPHL
Any B
PARAMETERt
Any
Y
Y
Y
y
CL
CL
~
~
0
1 pF
Y
Y
SN54ASC6007
MIN
SN74ASC6007
MAX
MIN
0.7
TYP*
1.8
MAX
0.7
TYP*
1.8
0.3
0.9
5
1.6
0.3
0.9
1.6
0.4
2.2
1.2
4.8
2.7
11.8
0.5
2.3
1.2
2.4
10.7
0.7
1.5
3.1
0.8
1.5
2.8
1.1
2.5
6.2
1.2
2.5
5.4
6.3
4.8
UNIT
4.5
1.4
3
6.9
1.5
3
0.4
0.6
1.5
0.4
0.6
1.2
0.6
1.3
3.6
0.7
1.3
3.1
ns
ns
nsipF
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr ~ tf ~ 3 ns (10% and 90%l.
tpLH '" propagation delay time, low-to-high-Ievel output
tpHL .. propagation delay time, high-to-Iow-Ievel output
t.tPLH '" change in tpLH with load capacitance
t.tPHL .. change in tpHL with load capacitance
*Typical values are lit VCC ~ 5 V, TA ~ 25°C .
•
DESIGN CONSIDERATIONS
C
Refer to the' ASC6017 data sheet and Section 7.
I»
fit
en
::r
CD
CD
....
en
4-618
TEXAS
.Jj:~
INSTRUMENTS
POST OFFIcE BOX 66/5012 .. DALLAS. TEXAS 75265
SN54ASC6008, SN74ASC6008
AND·NOR GATES
v = A1 + (81·82)+ (C1.C2)
02939, AUGUST 1986
SystemCell™
2-j.lm INTERNAL STANDARD CELL
•
3.4 ns Typical Propagation Delay with 1-pF
Load
•
Specified for Operation Over
4.5 V to 5,5 V
Vee
logic symbol
..r-,
Bl _ _
Range of
B2---...._,
Al-------~
Vee
•
Functional Operation Over
2Vt06V
Range of
•
Dependable Texas Instruments Quality and
Reliability
Cl
Y
---r--,
C2----...._,
FUNCTION TABLE
INPUTS
positive logic equation
Y = A1 +(81.82) + (C1.C2)
OUTPUT
111
X
B2
Cl
C2
Y
X
X
X
L
H
H
X
X
L
X
X
H
H
L
Any other combination
H
Al
H
X
X
RELATIVE
•
(/)
description
The SN54ASC6008 and SN74ASC6008 are expandable 1-2-2 input AND-NOR gate CMOS standard cells.
The cells are designated and called from the engineering workstation input using the following cell name
to develop labels for the design netlist:
...
II)
G)
G)
FEATURES
CELL NAME
BF008LH
TYPICAL
NETLIST
HDL LABEL
DELAY
CELL AREA
TO NA210LH
Label: ElF008LH A 1,81 ,B2,C1 ,C2,Y;
CL - 1 pF
3,4 ns
.c
...
CO
CO
2
The SN54ASCB008 is characterized for operation over the full military temperature range of - 55°C to
125°C, The SN74ASC6008 is characterized for operation from -40°C to 85°C.
C
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2,
electrical characteristics
PARAMETER
_................................
~1\1I="A~r-C!,..."O
ICC Supply current
ISN74ASC6008
TA - 25°C
VCC = 5 V,
......
·\.A..
"
•
"....
VCC = 5 V,
Equivalent power
VCC - 5 V,
Cpd. dissipation capacitance
TA = 25°C
PRODUCTION DATA documanlo contain information
currant as of publication data. Producq conform to
opaciflcati.ns par tho termo Taxn Instruments
:'=~i;a{::I~'l,; ~r;:I:~i:; lr:"::::::':~~' not
0'
,
w
L_
~
....
f':' r:" , .
.,.....
w,
'0
MAX
2.2
.. \..1.,. ........ ,
14.9
TA = 25°C
t r - tf - 3 ns,
UNIT
V
-~~
TA = MIN to MAX
Input capacitance
Cj
TYP
TEST CONDITIONS
VT Input threshold voltage
nA
0.13
pF
0.44
pF
Copyright @ 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. • DALLAS. TEXAS 752.65
4-619
SN54ASC6008, SN74ASC6008
AND-NOR GATES
switching characteristics over recommended ranges Qf supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETERt
FROM
(INPUT)
tpLH
Any
tpHL
tpHL
A1
Any e, C
tpLH
Any
tpHL '.
tpHL
atpLH
atpHL
atpHL
A1
Any e, C
TO
(OUTPUT)
Y
Y
TEST
CONDITIONS
CL = 0
CL
=
1 pF
Any
y
A1
Any
e,
C
SN54ASC6008
SN74ASC6008
MIN
TYP*
MAX
MIN
TYP*
MAX
0.9
I.B
5.3
0.9
I.B
4.7
0.4
1
0.4
1
1.7
0.3
1
0.4
2.5
1
4.B
2.1
2.3
4.B
1.7
2.3
12.1
O.B
1.6
3.2
0.9
1.6
2.9
O.B
2
4.B
0.9
2
4.2
6.3
1.4
3
6.9
1.5
3
0.6
1.5
0.4
0.6
1.3
0.5
1
2.6
0.5
1
2.2
*
II
DESIGN CONSIDERATIONS
Refeno the' ASC6017 data sheet and Section 7.
C
...
I»
I»
C/)
:r
CD
CD
...
tn
4-620
TEXAS
-II
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
=
ns
10.9
0.4
tPropagation delay times are m~sured from the 44% point of VI to the 44% point of Vo with tr = tf
tpLH " propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
atpLH '" change in tpLH with load capacitance
atpHL '" change in tpHL with load capacitance
Typical values are at VCC = 5 V, T A = 25 DC.
UNIT
ns
ns/pF
3 ns (10% and 90%).
SN54ASC6009. SN74ASC6009
AND-NOR GATES
Y = A1 +(B1.B2)+(C1·C2·C3)
02939. AUGUST 1986
SystemCell™
2-/Am INTERNAL STANDARD CELL
•
3.7 ns Typical Propagation Delay with l-pF
Load
•
Specified for Operation Over
4.5 V to 5.5 V
•
Functional Operation Over
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
Vee
Vee
'Iogic symbol
Range of
Range of
FUNCTION TABLE
INPUTS
positive logic equation
Y = A 1 + (81·82)
+ (C1.C2.C3)
OUTPUT
A1
B1
B2
C1
C2
C3
Y
H
X
X
X
X
X
L
X
H
H
X
X
X
L
X
X
X
H
H
H
Any other combination
L
H
description
The SN54ASC6009 and SN74ASC6009 are expandable 1-2-3-input AND-NOR gate CMOS standard cells.
The cells are designated and called from the engineering workstation input using the following cell name
to develop labels for the design netlist:
CELL NAME
BFOO9LH
TYPICAL
HDl LABEL
DELAY
...
fI)
.c
RELATIVE
en
CELL AREA
...
CO
CO
TO NA210LH
CL - 1 pF
Label: BF009LH A 1.B1.B2,C1 ,C2.C3.Y;
3.7 ns
:ill
G)
G)
FEATURES
NETLIST
II
2
The SN54ASC6009 is characterized for operation over the full military temperature range of - 55 DC to
125 DC. The SN74ASC6009 is characterized for operation from - 40 DC to 85 DC.
C
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
'1
PARAMETER
I VT
lee Supply current
ej
TYP
TEST CONDITIONS
= 5 V.
Vec = 4.5 V to 5.5
TA = MIN to MAX
Input threshold voltage
Vee
rISN54ASe6009
SN74ASe6009
Input capacitance
Vee - 5 V.
Equivalent power
Vee
Cpd dissipation capacitance
TA
PRODUCTION DATA documo.ts •••toi. i.f.rmati••
currant as of publication date. Products conform to
spacificatioDs par the terms of Taxas Instruments
===i~8;'::I~'i ~:~~~i:: :.~u:::::.::.~s
not
= 5 V.
= 25°e
---_
.. _-
TA
V.
VI
= 25°C
= Vce or
MAX
2.2
266
O.
15.9
TA - 25°C
tr - tf - 3 ns.
I UNIT
I v
nA
0.13
pF
0.45
pF
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-621
SN54ASC6009, SN74ASC6009
AND-NOR GATES
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETERt
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
tpLH
Any
V
tpHL
Al
Any B, C
V
tpHL
CL
=0
V
SN54ASC6009
SN74ASC6009
MIN
TYP*
MAX
MIN
TVP*
MAX
0.9
2
6.1
0.9
2
5.5
0.4
1
1.8
0.5
1
1.7
0.3
2.3
1.2
0.4
1.2
2.7
5
3
12.9
2.5
5
11.7
0.8
1.6
3.2
0.9
1.6
2.9
2.4
6.6
1
2.4
5.7
6.3
tpLH
Any
V
tpHL
Al
V
tpHL
Any B, C
0.9
AtPLH
AtpHL
Any
V
V
1.4
3
6.9
1.5
3
A1
Any 8, C
Y
Y
0.4
0.6
1.5
0.4
0.6
1.3
0.5
1.2
3.6
0.5
1.2
3.1
AtPHL
CL
= 1 pF
UNIT
ns
ns
ns/pF
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tpLH '" propagation delay time, low·to·high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
AtpLH '" change in tpLH with load capacitance
AtpHL '" change in tPHL with load capacitance
Typical values are at VCC = 5 V, TA = 25°C .
*
•
DESIGN CONSIDERATIONS
Refer to the' ASC6017 data sheet and Section 7.
4-622
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
=
Y
SystemCell™
3.7 ns Typical Propagation Delay with 1-pF
Load
•
Specified for Operation Over
4.5 V to 5.5 V
•
Functional Operation Over
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
Vee
02939, AUGUST 1986
2-l'm INTERNAL STANDARD CELL
•
Vee
SN54ASC6012, SN74ASC6012
AND-NOR GATES
(A1.A2) + (81.82) + (C1.C2·C3)
logic symbol
A1--...r"'-.....
Range of
A2--_L_"
C1---I""-'"
C2
C3 ---L_--"
B1 _ _. J " -.....
Range of
---1...._-"
B2
positive logic equation
Y = (A 1·A2)
Y
FUNCTION TABLE
+ (81.82) + (C1.C2.C3)
OUTPUT
INPUTS
A1
A2
B1
B2 C1
C2
C3
Y
H
H
X
X
X
X
X
l
X
X
H
H
X
X
X
l
X
H
H
X
X
X
Any other combination
H
l
H
description
The SN54ASC6012 and SN74ASC6012 are 3-wide, 2-2-3-input AND-NOR gate CMOS standard cells,
The cells are designated and called from the engineering workstation input using the following cell name
to develop labels for the design netlist:
a
FEATURES
NETLIST
TYPICAL
RELATIVE
HDllABEl
DELAY
CEll AREA
TO NA210lH
Label: BF012lH A 1,A2,B1,B2,C1,C2,C3,Y;
Cl - 1 pF
3.7 ns
CEll NAME
BF012lH
...co
CO
2.5
C
The SN54ASC6012 is characterized for operation over the full military temperature range of - 55 DC to
125 DC, The SN74ASC6012 is characterized for operation from -40 DC to 85 DC.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
"I
:" ....... ~
TEST CONDITIONS
~;,'<;i.,;'U;...; vu;i.a!::t~
vee =
0
v,
Cj
Input capacitance
= 4.5 V to 5.5
TA = MIN 10 MAX
VCC = 5 V,
C
Equivalent power
VCC - 5 V,
ICC Supply current
ISN54ASC6012
ISN74ASC6012
pd dissipation capacitance
PRODUCTION OATA do•• monts contoin information
currant as of publication data. Products conform to
specifications par the terms of Taxas Instruments
=~:~ri~8i~:,-:li ~::\~:i:r ~D::::'::~~ nat
VCC
TA
=
TYP
V,
MAX
2.2
= 25°C
= tf = 3 ns,
0.13
pF
0.56
pF
VI
V
312
18.7
TA
I,
UNIT
= ;'0"(;
= VCC 0' 0,
'A
25°C
nA
Copyright @ 1986. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-623
SN54ASC6012, SN74ASC6012
AND-NOR GATES
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETERt
tpLH
tpHL
tpLH
tpHL
.1tpLH
.1tpHL
FROM
UNPUT}
Any
Any
Any
TO
(OUTPUT)
y
Y
TEST
CONDITIONS
CL
CL
=0
=
1 pF
Y
SN54ASC6012
SN74ASC6012
MIN
TYP*
MAX
MIN
TYP*
MAX
0.9
2.1
0.9
2.1
6.3
0.3
1.2
'0.4
1.2
2.8
2.3
0.9
5.1
2.5
5.1
12.5
2.3
0.9
2.3
5.8
1.4
3
1.5
3
6.2
0.5
1.1
7
3.2
13.8
6.7
6.9
3.5
0.5
1.1
3.1
UNIT
ns
ns
ns/pF
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tpLH " propagation delay time. low-to-high-Ievel output
tpHL '" propagation delay time. high-to-Iow-Ievel output
.1tpLH " change in tpLH with load capacitance
.1tpHL·" change in tpHL with load capacitance
Typical values are at VCC = 5 V. TA = 25°C.
*
·DESIGN CONSIDERATIONS
II
4-624
Refer to the' ASC6017 data sheet and Section 7.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
v=
SystemCenr
M
4.1 ns Typical Propagation Delay with 1-pF
Load
•
Specified for Operation Over
4.5 V to 5.5 V
•
Functional Operation Over
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
Vee
02939. AUGUST 1986
2-j.lm INTERNAL STANDARD CELL
•
Vee
SN54ASC6013, SN74ASC6013
AND·NOR GATeS
(A1.A2)+(B1.B2.B3)+(C1.C2.C3)
logic symbol
B1 _ _,...._
Range of
B2
B3---t...._"
C1 _ _.r--....
Range of
C2
C3---t....-"
Y
A1
A2--"'----_'
positive logic equation
Y = (A 1·A2)
FUNCTION TABLE
+ (81.82.83) + (C1.C2.C3)
INPUTS
description
The SN54ASC6013 and SN74ASC6013 are
3-wide, 2-3-3-input AND-NOR gate CMOS
standard cells. The cell is designated and called
from the engineering workstation input using the
following cell name to develop labels for the
design netlist:
OUTPUT
A1
A2
B1
B2
B3
C1
C2
C3
Y
H
H
X
X
X
X
X
X
X
H
H
H
X
X
X
X
X
X
L
X
X
X
H
H
H
L
L
HDL LABEL
DELAY
CELL AREA
•
TO NA210LH
CI)
Label: BF013LH A 1.A2.B1.B2,B3,C1 ,C2,C3, Y;
CL - 1 pF
4.1 ns
2.5
....caca
H
Any other combination
....enCD
FEATURES
NETLIST
CELL NAME
BF013LH
TYPICAL
RELATIVE
CD
.c
The SN54ASC6013 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC6013 is characterized for operation from -40°C to 85°C.
C
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
VT Input threshold voltage
SN54Ase6013
lee Supply current
SN74Ase6013
TEST CONDITIONS
Vee = 5 V,
TA = 25°C
Vee = 4.5 V to 5.5 V.
T. = MIN to MAX
VI = Vee or 0,
Input capacitance
Vee = 5 V,
TA = 25°e
EquivalE;mt power
Cpd dissipation capacitance
Vee - 5 V,
TA= 25°C
t r = tf = 3 ns.
"1
r
ej
PRODUCTIOI DATA ....uinanll ••ntain information
currant as of pulllicolilll dlla. Products c.nform ta
.pacificati.ns par tho terms of TUis IIWu188m
:.:.=~m~:I':.'li ~~::i:l' lil":::':~ not
TYP
_2.2
MAX
UNIT
V
330
19.8
nA
1 0 . 13
pF
0.57
pF
Copyright © 1986. Texas Instruments Incorporated
.
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-625
SN54ASC6013. SN74ASC6013
AND·NOR GATES
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETERt
tpLH
FROM
(INPUT)
Any
TO
(OUTPUT)
TEST
CONDITIONS
V
CL = 0
tPHL
tpLH
tpHL
dtpLH
dtPHL
Any
Any
CL = 1 pF
V
Y
SN54ASC6013
TYP*
MAX
MIN
TYP*
MAX
1
2.5
7.9
1.1
2.5
7.1
0.4
1.3
3.4
0.4
1.3
3
2.5
5.5
2.6
5.5
13.2
0.9
2.6
14.6
7
1
2.6
6
1.4
3
1.3
6.9
1.5
3
6.3
3.7
0.5
1.3
3.2
0.5
tProp~gation delay times are measured from the 44% pOint of VI to the 44% point of Vo with tr
tpLH '" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
atpLH 3!5 change in tpLH with load capacitance
dtpHL '" change in tpHL with load capacitance
Typical values are at VCC = 5 V, TA = 25°C.
*
DESIGN CONSIDERATIONS
II
4-62.6
SN74ASC6013
MIN
Refer to the' ASC6017 data sheet and Section 7.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALl.AS. T~XAS 75265
= tf =
UNIT
ns·
ns
ns/pF
3 ns (10% and 90%1.
Y
=
SN54ASC6014, SN74ASC6014
AND-NOR GATES
(A1.A2.A3l+ (81·82·83) + (C1.C2.C3)
02939. AUGUST 1986
SystemCell™
2-llm INTERNAL STANDARD CELL
•
4.3 ns Typical Propagation Delay with l-pF
Load
•
Specified for Operation Over
4.5 V to 5.5 V
•
Functional Operation Over
2Vt06V
•
Vee
Vee
logic symbol
A1--..J!'"-....
A2
A 3 - -....._ '
Range of
Range of
B1---r--,
B2
B 3 - -....._ '
Dependable Texas Instruments Quality and
Reliability
Y
C 1 - - - r - -....
C2
C3---1.._"
positive logic equation
Y = (A 1.A2·A3)
FUNCTION TABLE
+ (81·82·83) + (C1.C2.C3)
INPUTS
A2 ~3
H
H
A1
H
OUTPUT
B1
B2
B3 C1
C2 C3
X
X
X
X
X
X
L
L
X
X
X
H
H
H
X
X
X
X
X
X
X
X
X
H
H
H
Y
L
Any other combination
H
description
•
The SN54ASC6014 and SN74ASC6014 are 3-wide, 3-input AND-NOR gate CMOS standard cells. The
cells are designated and called from the engineering workstation input using the following cell name to
develop labe!s for the design netlist:
II)
~
CD
.:
FEATURES
CELL NAME
BF014lH
NETLIST
TYPICAL
RELATIVE
HDllABEl
DELAY
CEll AREA
Cl = 1 pF
TO NA210lH
4.3 ns
2.75
Label: BF014LH A 1,A2,A3,B1.B2,B3,C1,C2,C3,Y;
tn
....COCO
C
The SN54ASC6014 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC6014 is characterized for operation from - 40°C to 85 DC.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
V1
TA = 25°C
Input capacitance
Vce = 5 V.
TA = 25°C
Equivalent power
Vec = 5 V.
TA = 25°e
tr
ICC Supply current
ej
=:I---TYP
TEST CONOITIONS
VCC = 5 V.
Vee = 4.5 V to 5.5 V,
TA = MIN to MAX
UlfJUl mresnolO VOltage
ISN54Ase6014
iSN74ASC6014
Cpd dissipation capacitance
PRODUCTION DATA documents cont.in inform.tion
cur(8nt 8S of publication date. Products conform to
.pacifications per the terms of Texas Instruments
=~:=i:8i~:r.:li ~:~:~i:r :.r::;:::~:~~ not
VI = Vee or 0,
= tf
=
3 ns,
MAX
I UNIT I
363
21.8
nA
2.2
V
0.13
pF
0.71
pF
Copyright © 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS· 75265
4-627
" .. P i ! . '
,
~.
':..
.
SN54ASC6014, SN74ASC6D14
~ND-NOR GATES
_switching t:haracten~tics over recommended ranges of supply voltage and operating free-air temperature'
lunle~s other,wise hoted)
,
PARAMETERt
tPL:i-I
tpHL
tpLH
tpHt.
AtpLH
AtpHL
FROM
(lIllPUT)
Any
Any
Any
TO
(OUTPUT)
TEST
CONDITIONS
Y
=0
CL
Y
CL
= 1 pF
\
Y
SN54ASC6014
TYP;
MAX
MIN
1.1
2.8
0.4
1.4
!!.4
3.9
0.5
1.4
3.4
2.5
5.8
16
2.6
5.8
14.5
7.5
6.5
6.8
1.2
1.5
2.8
3
3
6.2
0.6
1.4
3.7
0.6
1.4
3.1
= change in tPLH with load capacitance
Refer to the 'ASC60 1 7 data sheet and Section 7.
...C
I»
I»
tI)
::r
CD
CD
...
(I)
.
8.4
2.8
DESIGN CONSIDERATIONS
4-628
2.8
1.1
AtPHL '" chaMge in tPHL with load capacitance
tTypical values are at VCC = 5 V, TA = 25°C.
•
1.1
1.4
tprilpagation delay times are measured frOrri the 44% point of VI to the 44% point of Va with tr
tpu-i " propagation delay time, low-to-high-Ievel output
tpHL .. propagation delay time, high-to-Iow-Ievel output
AtpLH
SN74ASC6014
TYP;
MAX
MIN
TEXAS'"
INSTRUMENTs
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
= tf
UNIT
ns
ns
ns/pF
= 3 ns 110% and 90%1.
SN54ASC6017, SN74ASC6017
AND-NOR GATES
V - A1 +(81.82)
02939. AUGUST 1986
SystemCell™
2-llm INTERNAL STANDARD CELL
•
2.5 ns Typical Propagation Delay with '-pF
Load
•
Specified for Operation Over Vee Range of
4.5 V to 5.5 V
•
•
logic symbol
__
:~-----r--~:>~ ~~
A1
Functional Operation Over Vee Range of
2Vt06V
~Y
FUNCTION TABLE
INPUTS
Dependable Texas Instruments Quality and
Reliability
OUTPUT
AI
B2
BI
Y
H
X
X
H
X
L
L
L
L
X
H
L
X
L
H
positive logic equation
Y = A1 +(61.62)
H
description
The SN54ASC6017 and SN74ASC6017 are expandable 1-2-input AND-NOR gate CMOS standard cells.
The cells are designated and called from the engineering workstation input using the following cell name
to develop labels for the design netHst:
FEATURES
CELL NAME
BF001LH
NETLIST
TYPICAL
HDL LABEL
DELAY
CELL AREA
CL-lpF
2.5 ns
TO NA210LH
Label: BFOOI LH A I.B1.B2.Y;
RELATIVE
II
....
U)
CD
CD
.c
1.5
en
The SN54ASC6017 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC6017 is characterized for operation from -40°C to 85°C.
....caca
C
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
TEST CONDITIONS
VT Input threshold voltage
lee Supply current
ej
I. (,,;pd
ISN54Ase6017
Vee - 5 V.
Vee - 4.5 V to 5.5 V.
ISN74ASe60 17
TA
=
Vee
EmlivRIp.nt nn\lI/p.r
\/,..,., _ c::
dissipation 'capacitance
I
PRODUCTIOI DATA docam..ts contain information
cUmIIIl IS 01 publication data. Products conlorm 10
spacificatiDns par the terms of TeXIS Instruments
=~ai~r:1~7i
:::::i:r :.r:::::~:.~ not
TA
=
5 V.
\I
MAX
2.2
11.2
TA
-,
-
=
25°e
+.
~I
-
25°e
~ -•• _,
I
UNIT
V
187
VI - Vee or O.
MIN to MAX
=
Input capacitance
--
TYP
TA - 25°e
nA
0.13
pF
0.38
I I
pF
Copyright @ 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-629
SN54ASC6017, SN74ASC6017
AND-NOR GATES
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETERt
tPLH
tPHL
tpLH
tPHL
dtpLH
FROM
(INPUT)
TO
TEST
{OUTPUTI
CONDITIONS
Any
Y
CL = 0
Any
y
Any
y
CL = 1 pF
dtPHL
SN54ASC6017
SN74ASC6017
MIN TYP~
MAX
TVP~
MAX
0.6
1.1
2.4
0.6
1.1
0.2
0.9
1.9
0.3
0.9
1.7
1.6
0.7
3.1
6.9
1.7
3.1
6.3
1.8
4.3
0.8
1.8
3.8
0.9
2
4.6
1
2
4.2
0.4
0.9
2.5
0.4
0.9
2.1
MIN
t Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr
tpLH '" propagation delay time, low·to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
dtpLH 55 change in tpLH with load capacitance
dtpHL '" change in tpHL with load capacitance
tTypical values are at VCC = 5 V, TA = 25°C.
= tf =
2.2
UNIT
ns
ns
ns/pF
3 ns 110% and 90%1-
DESIGN CONSIDERATIONS
III
Refer to Section 7.
All inputs to this cell. as well as all cells. must be accounted for in the netlist used to generate the next
level of an ASIC design. A tie-off cell is offered specifically for managing unused inputs.
This Boolean function is a member of a series of multifunction cells designed to simplify the implementation
of a broad class of higher-level logic equations such as:
•
Sum of products
•
Exclusive-OR and exclusive-NOR functions
•
Majority decoders
•
Modulo adders
•
Carry-save adders
•
Function generators
•
Random logic
The members of this class of standard-cell functions are grouped in the' ASC6000 series of type numbers.
The selection consists of four primary architectures with expandable versions offered in each:
•
Dedicated and expandable AND-NOR gates
•
Dedicated and expandable OR-AND-NOR gates
.• Expandable AND-OR-NOR gates
•
Expandable OR-NAND gates
•
Expandable AND-OR-NAND gates
•
Expandable OR-AND-OR-NAND gates
Options are offered in each architecture from basic 2-wide functions up to expandable 3-wide functions
providing single-macro solutions to most design requirements. The expandable functions can 'be combined
with basic gating cells and/or other Boolean cells offered in Texas Instruments standard-cell family to
implement the application-specific solutions.
4-630
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
v=
SN54ASC6018, SN74ASC6018
AND-NOR GATES
A1 +(B1.B2.B3)+(C1·C2·C3)
D2939. AUGUST 1986
SystemCell™
2-/tm INTERNAL STANDARD CELL
•
3.9 ns Typical Propagation Delay with 1-pF
Load
•
Specified for Operation Over Vee Range of
4.5 V to 5.5 V
•
Functional Operation Over Vee Range of
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
logic symbol
~_j____~_...J
Y
FUNCTION TABLE
positive logic equation
INPUTS
Y = A 1 + (81.82·83) + (C1·C2.C3)
OUTPUT
A1
B1
B2
B3
C1
C2
C3
H
X
X
X
X
X
X
L
X
H
H
H
X
X
X
L
X
X
X
H
H
H
X
Any other combination
Y
L
H
description
The SN54ASC6018 and SN74ASC6018 are expandable 1-3-3-input AND-NOR gate CMOS standard cells.
The cells are designated and called from the engineering wor~station input using the following cell name
to develop labels for the design netlist:
II
FEATURES
NETLIST
TYPICAL
RELATIVE
HDL LABEL
DELAY
CEll AREA
CL - 1 pF
3.9 ns
TO NA210LH
Label: BF010LH A l,Bl,B2,B3,Cl,C2,C3,Y;
CELL NAME
BF010LH
2
The SN54ASC6018 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC6018'is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
\/~
ICC Supply current
Cj
TEST CONDITIONS
-
- .,
VCC - 4,5 V to 5,5 V,
ISN74ASC6018
TA
Input capacitance
Equivalent power
Cpd dissipation capacitance
PRODUCTION DATA doc.mant. contain information
conant as at publication data. Products conform to
.pacifil:ations per tbe tarml of Taxas Instruments
::~:~~i~8i~~1~1i
-
ISN54ASC6018
Innll1' i'kriCloC!hnlri \lnl+ ........
=:I::i:r lrr::~:::~:'1 nat
'~~
= MIN to
VCC = 5 V,
VCC = 5V;
TA = 25°C
'
-- -
"
-.-
VI - VCC or 0,
301
18,1
MAX
= 25°C
= tf = 3 ns,
TA
tr
nA
0,13
pF
0.45
pF
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-631
SN54ASC6018, SN74ASC6018
AND-NOR GATES
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETERt
FROM
(INPUT)
tpLH
Any
tpHL
A1
tpHL
Any S, e
tPLH
tpHL
Any
tpHL
Any S, e
AtPLH
Any
AtpHL
A1
AtpHL
Any S, e
TEST
CONDITIONS
Y
CL
=0
= 1 pF
SN54ASCS018
MIN
SN74ASCS018
MAX
MIN
TYP*
0.8
TYP*
2.1
6.S
0.9
2.1
MAX
6
0.3
0.8
1.5
0.3
0.8
1.5
0.5
1.3
2.3
5.1
3
13.4
0.5
2.4
1.3
5.1
2.6
12.2
0.7
1.4
2.9
0.8
1.4
2.7
1.1
2.6
6.6
1.3
2.6
5.7
1.4
3
0.6
6.7
1.5
3
6.3
0.4
1.4
0.4
0.6
1.2
0.6
1.3
3.7
0.6
1.3
3.2
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr
tpLH '" propagation delay time, low:to-high-Ievel output
tPHL '" propagation delay time, high-to-Iow-Ievel output
AtpLH '" change in tPLH with load capacitance
AtpHL '" change in tpHL with load capacitance
tTypical values are at Vee = 5 V, TA = 25°e.
= tf =
II
..
..
C
A1
TO
(OUTPUT!
Y
eL
Y
DESIGN CONSIDERATIONS
Refer to the 'ASC6017 data sheet and Section 7,
m
m
C/)
:T
CD
CD
en
4-632
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
UNIT
ns
ns
ns/pF
3 ns 110% and 90%).
SN54AsC6019. SN74ASC6019
AND·NORGATES
V"" (A1·A2)+(B1.B2)+(C1.C2)
02939. AUGUST 1986
SystemCell™
2-ttm INTERNAL STANDARD CELL
•
3.5 ns Typical Propagation Delay with 1-pF
Load
•
Specified for Operation Over
4.5 V to 5.5 V
•
Functional Operation Over
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
Vee
Vee
I.ogic symbol
A 1 - - - r - -....
Range of
A2---t..._"
B 1 - - - r - -....
Range of
Y
B 2 - -_ _"
C 1 - - - r -......
C2
--""1._-'
positive logic equation
Y = (A 1.A2)
FUNCTION TABLE ,
+ (81.82) + (C1.C2)
INPUTS
A1
B1
H
H
X
X
X
X
L
X
X
H
H
X
X
L
X
X
X
H
H
X
82
C1
C2
OUTPUT
Y'
A2
L
Any othe.r combination
H
description
The SN54ASC6019 and SN74ASC6019 are 3-wide, 2-input AND-NOR gate CMOS standard cells. The
cells are designated and called from the engineering workstation input using the followin9 cell name to
develop labels for the design netlist:
BF011LH
U)
iQ)
.c
en
ca
FEAtURES
CELL NAME
•
NETLIST
tyPICAL
RELATIVE
HDL LABEL
DELAY
CELL AREA
«;
TO NA~10LH
C
CL - 1 pF
Label: BF011LH A1,A2,B1,B2,C1,C2.Y;
3.5 ns
2.76
The SN54ASC6019 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC6019 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
0
TEST CONDITIONS
t"AKAMt.II:H
VT
Input threshold voltage
lee Supply current
ISN54Ase6019
ISN74Ase6019
Vet - 5 V.
Vee = 4.5 V to 5.6 V,
TYP
TA - 25°e
TA = MIN to MAX
19.1
Vee - 5 V,
TA - 25°e
Equivalent power
Cpd dissipation capacitance
Vee - 5 V,
t r - tf - 3 ns,
PROOUCTIOI DATA documants contain information
currant as of publication date. Products conform to
spacHications par the terms of Texas Instruments
:'~~~:=i~ai~:I~J~ =:~:r lIr:~::::~:~~ not
TA = 25°e
UNIT
V
319
VI = Vee or 0,
Input capacitance
ej
MAX
2.2
nA
0.13
pF
0.52
pF
Copyright @ 1986, Texas Instrums(lts Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TI:X~S 76265
4-633
SN54ASC6019, SN74ASC6019
AND·NOR GATES
switching characteristics over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise noted)
PARAMETERt
tpLH
tpHL
tPLH
tpHL
.1tPLH
.1tPHL
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
Any
Y
CL = 0
Any
Y
CL = 1 pF
Any
SN54ASC6019
MIN TYP*
MAX
0.9
0.3
2.4
0.9
1.4
Y
0.5
2
1
5
2
3
1
6
2.4
12.8
5
6.9
2.6
SN74ASC6019
MIN
TYP*
MAX
1
0.4
2.5
0.9
1.5
0.5
2
1
5
2
3
1
~.4
2.2
11.6
4.4
6.3
2.3
UNIT
ns
ns
ns/pF
tpropagation delay times are m~asured from the 44% point of VI to the 44% point of Va with ti = tf = 3 ns (10% and 90%).
tpLH '" propagation delay time, low-to-high-Ievel output
tPHL '" propagation delay time, high-to-Iow-Ievel output
.1tpLH '" change in tpLH with load capacitance
.1tpHL .. change in tpHL with load capacitance
'Typical values are at VCC =5 V, TA = 25°C.
DESIGN CONSIDI;RATIONS
Refer to the' ASC6017 data sheet and Section 7.
II
4-634
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALlAS, TEXAS 75265
SN54ASC6022. SN74ASC6022
OR·AND·NOR GATES
Y .. A1.A2+[B1.B2.(C1 +C211
02939, AUGUST 1986
SystemCell™
•
2-j.lm INTERNAL STANDARD CELL
logic symbol
Typical Propagation Delay with 1-pF Load
3.3 ns from Any A
3 ns from Any B
3.9 ns from Any e
Vee
C1--..r-...
C2---c.._"
•
Specified for Operation Over
4.5 V to 5,5 V
Range of
•
Functional Operation Over
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
B1=====L)
B2
Y
Vee
A1-----------~--~
Range of
A2-----------~___ '
FUNCTION TABLE
INPUTS
positive logic equation
Y = Al.A2+[Bl·B2·(Cl +C2)]
OUTPUT
A1
A2
B1
B2
C1
C2
Y
H
H
X
X
X
X
L
X
X
H
H
H
X
X
X
H
L
H
H
X
Any other combination
L
H
description
The SN54ASC6022 and SN74ASC6022 CMOS standard-cell Boolean macros are 2-wide 2-3-input sumof-products AND-NOR gates with a dedicated 2-input OR, 3-input AND product term. Two available inputs
to the 3-input AND gate and two to the other 2-input AND gate provide expandability for implementing
customized product terms. The cells are designated and called from the engineering workstation input using
the following cell name to develop labels for the design netlist:
BF022LH
en
CELL AREA
HDL LABEL
....asas
TO NA210LH
Label: BF022LH A1 ,A2,B1 ,B2,C1.C2,Y:
en
CD
CD
.c
RELATIVE
NETLIST
CELL NAME
II
....
2.25
C
The SN54ASC6022 is characterized for operation over the full military temperature range of - 55°C to
125°C, The SN74ASC6022 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
TEST CONDITIONS
VT Input threshold voltage
SN54ASC6022
ICC Supply current
SN74ASC6022
Ci Input capacitance
I
I
C. Equivalent power
pd diSSipation capacitance
PRODUCTIOI DATA documonts contain information
currant as of. publication data. Products conform to
:r:ifications par the terms of Taxas Instruments
ne~=~~i~a{::I~~~ ~!=:~ti:: :'~D::::!\:~ not
VCC
~
TYP
TA ~ 25°(:
5 V,
VCC - 4.5 V to 5.5 V,
TA ~ MIN to MAX
VI - VCC or 0,
VCC - 5 V,
5 V,
VCC
TA - 25°C
TA
~
MAX
2.2
V
282
16.9
t r - tf
25°C
-III
tEXAS
INSTRUMENTS
POST OFFICE BOX 65B012 • DALLAS, TEXAS 75265
UNIT
--~-------
3 ns,
nA
0.13
pF
0.54
pF
Copyright © 1986, Texas Instruments Incorporated
4-635
SN64ASC6022, SN74ASC6022
OR-A~D:NOR GATES
",
o\{ ..
switchin~ characteristics over re~ommende~ ran!)e$ of supply voltage and operating free-air temperature
(un!eSS otherwili"l)otlldl
PARi\.N!ETERt
tplH
tPHL
tpLH
.
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONDITIONS
Any A
Y
CL ~ 0
Any A
Y
Any B
Y
CL
~
1 pF
tPHL
tPLH
tpHL
tpLH
Any B
Y
Any C
Y
tpHL
,tPLH
CL
CL
~
CL
~O
1 pF
~
0
tPt-iL
tPLH
tpHL
Y
CL
~
1 pF
4A
1.7
11.2
4.2
3.2
2.8
7.7
6.5
1.1
1.9
0.4
0.9
2.5
0.9
4.9
1.8
0.7
1.3
0.7
1.3
1.7
3.3
1.3
2.7
1.1
0.5
2.2
1.2
5A
2.9
2.5
5.2
12.2
1.1
2.5
6.5
1.4
3
6.9
atPHL
0.5
0.9
2.5
aWLH
AtPHL
0.9
0.6
2
1.4
4.6
3.6
1.4
3
6.9
0.6
1.3
3.6
4tPLH
.
Any C
SN64ASC6022
MIN, 'TVP'
MAX
AtPLH
Any A
Any'S
Any C
Y
Y
Y
4t pI-\L
SN74ASC6022
MIN
1.1
OA
2.7
1
0.7
0.8
1.8
lA
1.1
0.5
2.7
1.2
1.5
0.5
TVP'
MAX
1.9
4
0.9
1.7'
4.9
10.2
1.8
3.8
1.3
2.9
1.3
2.5
3.3
7
2.7
5.6
2.2
1.2
4.9
5.2
11
2.5
5.6
3
6.3
2.5
0.9
2.2
4.2
0.6
2
1.4
1.5
3
6.2
0.6
1.3
3.1
1
3.1
UNIT
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
ns/pF
tPrQPa~ati()n qelay times are measured from the 44% point of VI to the 44% point of Va with tr ~ tf ~ 3 ns (10% and 90%).
tpLH '" proPagation delay time, low-to-high-Ievel output
tpHL .. prOpagation ejelay time, high-to·low·level output
AtPLH .. change in tpLH with load capacitance
AtPIjL .. c~an~e in tPHL with load capacitance
tTypi~arvalues are at Vce ~ 5 V, TA ~ 25°C.
DESIGN CONSIDERATIONS
Refer to the' ASC6017 data sheet and Section 7.
4'1536
TEXAS . "
INSTRUMf.:NTS
PqST OFFICE BOx 665012 • DALLAS.
TEXJ\S 75265
SN54ASC6023. SN74ASC6023
OR·AND·NOR GATES
V = A1 +[81·(C1 +C2))
D2939, AUGUST 1986
SystemCell™
•
2·J.lm INTERNAL STANDARD CELL
logic symbol'
Typical Propagation Delay with 1-pF Load
2,9 ns from A 1
2.5 ns from B1
3.2 ns from Any
e
Vee
•
Specified for Operation Over
4.5 V to 5.5 V
•
Functional Operation Over
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
Vee
Range of
FUNCTION TABLE
Range of
INPUTS
positive logic equation
Y
=
A1 + [B1o(C1 +C2)]
OUTPUT
A1
B1
C1
C2
Y
H
X
X
X
L
X
H
H
X
L
X
H
X
H
L
L
L
X
X
H
L
X
L
L
H
description
•
The SN54ASC6023 and SN74ASC6023 CMOS standard-cell Boolean macros are 2-input sum-of-products
NOR gates with a dedicated 2-input OR, 2-input AND product term. One available input to the 2-input
AND gate and the 2-input NOR gate provides expandability for implementing customized product terms.
The cells are designated and called from the engineering workstation input using the following cell name
to develop labels for the design netlist:
Q)
Q)
.J:
en
CELL AREA
HDL LABEL
BF015LH
C/)
RELATIVE
NETLIST
CELL NAME
...
TO NA210LH
Label: BF015LH A1,B1,C1,C2,Y;
...
ctI
ctI
1.75
C
The SN54ASC6023 is characterized for operation over the full military temperature range of - 55 DC to
125 DC, The SN74ASC6023 is characterized for operation from -40 DC to 85 DC.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
VT
I,::
Cj
TEST CONDITIONS
Input threshold voltage
c::"'nnl,, .... "rro:on-t
VCC
I SN54ASC6023
VCC
I SN74ASC6023
TA
=
=
=
TYP
5 V,
TA
4.5 V to 5.5 V,
VI
VCC - 5 V,
TA
VCC - 5 V,
tr
=
~
~
25°C
tf - 3 ns,
25°C
current as of publication date. Products conform to
~~~~~:~~i~ai~:1~1e ;!:~:~ti:: :'IO::~:~:t::s~S
not
I
"'
0.13
pF
0.36
pF
I
Copyright © 1986, Texas Instruments Incorporated
PRODUCTION DATA documents contain information
specifications per the terms of Texas Instruments
218
0,
UNIT
V
13.1
Equivalent power
TA
MAX
2.2
MIN to MAX
Input capacitance
Cpd dissipation capacitance
= 25°C
= VCC or
TEXAS
-1.1}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-637
SN54ASC6023, SN74ASC6023
OR·AND·NOR GATES
switching characteristics over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise noted)
PARAMETERt
tpLH
tpHL
tpLH
tpHL
tpLH
tPHL
tpLH
tpHL
tpLH
tPHL
tpLH
tpHL
v,
Vee = 4.5 V to 5.5 V,
ISN74Ase6055
TA = MIN to MAX
TA = 25°e
15.9
Vee = 5 V,
TA = 25°e
Equivalent power
Cpd dissipation capacitance
Vee = 5 V,
tr = tf = 3 ns,
PRODUCTION DATA do.uments .ontein inlormation
•• r....t as 01 publi.ation date. Prodoets .onfarm 10
tbase .pacillCltions l1li" tho tarms 01 Ta.a.
Instrlmantl standaril warranty. Production
pr.....i.g dOlI .ot n......rily include teating of all
p.ramlt.....
266
VI = Vee or 0,
Input capacitance
ei
MAX
2.2
TA = 25°e
I UNIT I
V
nA
0.13
pF
0.51
pF
Copyright © 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
4-667
SN54ASC6055, SN74ASC6055
OR·NAND GATES
switching characteristics over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise noted)
.
PARAMETERt
tpLH
FROM
(INPUT)
Any
tPHL
tpLH
tpHL
Ll.tpLH
Ll.tPHL
Any
Any
TO
(OUTPUT)
Y
Y
TEST
CONDITIONS
CL
CL
=
=
0
1 pF
Y
SN54ASC6055
SN74ASC6055
MIN
TYP*
MAX
MIN
TYP*
MAX
O.B
1.6
4.5
O.B
1.6
4.1
0.3
1
2.6
0.4
1
2.4
2.2
4.6
2.4
4.6
10.3
O.B
2
11.3
5.1
O.S
2
4.5
1.4
3
7
1.5
3
6.3
0.5
1
2.6
0.5
1
2.2
tPropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr
tpLH '" propagation delay time, low-to-high-Ievel output .
tpHL '" propagation delay time, high-to-Iow-Ievel output
Ll.tpLH '" change in tpLH with load capacitance
Ll.tpHL '" change in tpHL with load capacitance
t Typical values are at VCC = 5 V, T A = 25°C.
DESIGN CONSIDERATIONS
II
4·668
Refer to the' ASC6017 data sheet and Section 7.
TEXAS
~
IN~UMENlS
POST OFFICE BOX 655012 • OA~LAS. TEXAS 75265
= tf =
UNIT
ns
ns
ns/pF
3 ns (10% and SO%).
SN54ASC6056, SN74ASC6056
OR-NAND GATES
V = A1.A2.(81 + 82)
02939, AUGUST 1986
SystemCelr
M
2-j.lm INTERNAL STANDARD CELL
logic symbol
•
Typical Propagation Delay with '-pF Load
2.2 ns from Any A
2.9 ns from Any B
•
Specified for Operation Over
4.5 V to 5.5 V
•
Functional Operation Over
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
Vee
Vee
Range of
Range of
FUNCTION TABLE
positive logic equation
Y
OUTPUT
INPUTS
= Al.A2.(Bl +B2)
V
A1
A2
B1
B2
H
H
H
X
L
H
H
X
H
L
L
X
X
X
H
X
L
X
X
H
X
X
L
L
H
description
The SN54ASC6056 and SN74ASC6056 are 3-wide. 1-1-2-input OR-NAND gate CMOS standard-cell •
functions. The cell is designated and called from the engineering workstation input using the following
cell name to develop labels for the design netlist:
CEll NAME
BF056LH
....CD
fI)
RELATIVE
NETLIST
CELL AREA
HDllABEl
CD
.c
TO NA210lH
en
1.75
Label: BF056LH A 1.A2,Bl,B2.Y;
~
The SN54ASC6056 is characterized for operation over the full military temperature range of - 55 DC to
125 DC. The SN74ASC6056 is characterized for operation from _40DC to 85°C.
....asas
o
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
VT
PARAMETER
Input threshold voltage
~
TA
5 V,
~
25°C
Vee - 4.5 V to 5.5 V.
TA ~ MIN to MAX
V, - Vee or O.
Input capacitance
Vee ~ 5 V.
TA - 25°C
Equivalent power
Vee - 5 V.
TA ~ 25°C
ICC Supply current
Il:j
I SN54Ase6056
I SN74ASe6056
TVP
TEST CONDITIONS
Vee
Cpd dissipation capacitance
PRODUCTION DATA documents contain information
currant as of publication date. Products conform to
specifications per the terms of Texas Instruments
::=~~i~a{::1~1e ~=~~i:r l!~o:.'::::9t:~~s not
--
MAX
220
13.2
tr - tf - 3 ns.
UNIT
V
2.2
nA
1 0 . 13
pF
0.55
pF
Copyright @ 1986, Texas Instruments Incorporated
TEXAS ...,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, rEXAS 75265
4-669
SN54ASC6056, SN74ASC6056
OR-NAND GATES
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETERt
tPLH
FROM
liN PUT)
Any A
TO
(OUTPUT)
Y
tPHL
tpLH
tPHL
tpLH
Any A
Any B
y
y
tPHL
tPLH
Any B
Y
Any A
Y
tPHL
~tpLH
~tpHL
~tpLH
~tpHL
Any B
TEST
CONDITIONS
CL
CL
=
CL
CL
=a
1 pF
=a
=
1 pF
Y
SN54ASC6056
TYP*
MAX
MIN
TYP*
MAX
0.6
0.9
1.6
0.6
0.9
1.5
0.7
1.2
2.4
0.7
1.2
2.2
1.1
1.9
2.5
3.8
1.2
1.9
3.5
5.9
1.4
2.5
5.1
1.4
3.2
0.9
1.4
2.9
1.3
0.8
0.4
1
2.4
0.4
1
2.2
1.8
3.4
7.7
1.9
3.4
7
1
2.3
5.9
1.1
2.3
5.1
2.1
0.5
1
2.3
0.5
1
0.6
1.3
3.5
0.6
1.3
3
0.9
2
4.6
2
4.1
0.6
1.3
3.5
1
,0.6
1.3
3
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr
tpLH 5; propagation delay time, low·to-high-Ievel output
tpHL a propagation delay time, high-to-Iow-Ievel output
~tpLH '" change in tpLH with load capacitance
~tpHL '" change in tpHL with load capacitance
*Typical values are at VCC = 5 V, T A ' = 25°C.
•
DESIGN CONSIDERATIONS
C
m
r+
m
Refer to the 'ASC60 1 7 data sheet and Section 7.
en
::r
CD
CD
r+
(I)
4-670
SN74ASC6056
MIN
TEXAS •
INSTRUMENTS
PriST OFFICE BOX 655012 • DALLAS, TEXAS 75265
= tf =
UNIT
ns
ns
ns
ns
ns/pF
ns/pF
3 ns (10% and 90%1.
SN54ASC6057. SN74ASC6057
OR·NAND GATES
= A1.A2.(81 + 82 + 83)
v
SystemCell™
2-Ilm INTERNAL STANDARD CELL
•
Typical Propagation Delay with 1-pF Load
2.8 ns from Any A
3.7 ns from Any 8
•
Specified for Operation Over Vee Range of
4,5 V to 5.5 V
•
Functional Operation Over Vee Range of
logic symbol
2Vt06V
•
02939, AUGUST 1986
FUNCTION TABLE
Dependable Texas Instruments Quality and
Reliability
INPUTS
positive logic equation
Y = A1·A2·(B1 +B2+B3)
OUTPUT
A1
A2
B1
B2
B3
H
H
H
X
X
L
H
H
X
H
X
L
Y
H
H
X
X
H
L
L
X
X
X
X
H
X
L
X
X
X
H
X
X
L
L
L
H
description
II
...
The SN54ASC6057 and SN74ASC6057 are 3-wide, 1-1-3-input OR-NAND gate CMOS standard-cell
functions. The cell is designated and called from the engineering workstation input using the following
cell name to develop labels for the design netlist:
BF057LH
RELATIVE
NETLIST
CELL NAME
CI)
Q)
Q)
.c
CELL AREA
HDL LABEL
TO NA210LH
CI)
1.75
a:J
a:J
Label: BF057LH A 1 ,A2,B1 ,B2,B3,Y;
...
The SN54ASC6057 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC6057 is characterized for operation from -40°C to 85°C.
C
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
TEST CONDITIONS
PARAMETER
I VT Input threshold voltage
I
! ~~C ~:..;;:;::.; ;::..;;-;-.:;-.: SN54ASe6057
SN74ASe6057
I
ej
Input capacitance
Equivalent power
Cpd dissipation capacitance
= 5 V,
Vee = 4.5 V to 5.5
TA = MIN to MAX
Vee = 5 V,
V,
Vee - 5 V,
TA
=
TYP
TA
Vee
VI
= 25°e
= Vr.r. or 0,
TA
=
25°e
t r - tf - 3 ns,
25°e
=~=~~i~at~:I~'li ~:~~:i:; :Ir::::~:~~s not
UNIT
I
237
14.2
I
V
nA
0.13
pF
0.58
pF
I
I
Copyright © 1986. Texas Instruments Incorporated
PRODUCTION DATA doc.mants contain inlormation
current 88 of publication date. Products conform to
spacifications per the terms of Texas Instruments
MAX
2.2
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-671
SN54ASC6057. SN74ASC6057
OR-NAND GATES
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETERt
tpLH
tpHL
tpLH
tpHL
tpLH
FROM
(INPUT)
Any A
Any A
Any 8
tpHL
tpLH
Any 8
TO
(OUTPUT)
Y
Y
Y
Y
tpHL
---- Y
positive logic equation
Y=A
description
The SN54ASC6120 and SN74ASC6120 are two internal delay buffer standard cells that provide the ASIC
designer with symmetrical delay elements that can be used to implement signal path delay-line management
techniques needed to ensure timing integrity. Each option is designated and called from the engineering
workstation input using the following cell names to develop labels for the design netlist:
....II)
I/)
FEATURES··CELL NAME
BU120LH
BU130LH
REI.·\~
NETLIST
TYPICAL
HDL LABEL
DELAY
CElio AREA
CL - 1 pF
TO r(,\210LH
1.7 ns
1.5
., 75
Label: BU 1 nOLH A, Y;
1,7 ns
II)
.c
CJ)
....caca
C
The SN54ASC6120 is characterized for operation over the full milil:lry temperature range of - 55°C to
125°C. The SN74ASC6120 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
VT
Input threshold voltage
.....::.B:.::U...:1-=2-=:OL==H~t-,=B=:=U:-:1c::3:.::0-=:LH:::-:---l1 UNIT
-::
TEST CONDITIONS
Vee
~
Vee
~
5 V,
. ..
TA ~ 25°e
TA
ej
Input capacitance
Vee - 5 V,
TA - 25°e
Equivalent power
Vee ~ 5 V.
tr
Cpd dissipation capacitance
TA
~
~
4.5 V to 5.5 V, VI
MIN to MAX
~
ISN54Ase6120
lee Supply current I SN74Ase6120
~~~~~:~~i~8[::1~1~ ~!::i~~ti:f :,iO::~:::t:~~S not
2.2
. .. .......,.....
2.2
187
Vee or 0,
~
tf
~
3 ns.
25°e
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
12.9
nA
0.13
0.13
pF
1.29
1.73
pF
Copyright
I
V
214
11.2
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
.............
© 1986, Texas Instruments Incorporated
4-745
•
SN54ASC&120; SN74ASC6120
NON INVERTING DELAY BUFFERS
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
BU120LH
PARAMETERt
tpLH
tpHL
tPLH
tPHL
dtpLH
FROM
(INPUT)
TO
(OUTPUT)
SN84ASC6120
MIN
A
Y
CL = 0
0.4
0.8
A
Y
CL = 1 pF
0·7
1
TYP*
0.9
1.2
1.6
0.2
0.1
A
Y
PARAMETERt
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tpHL
A
Y
dtpHL
TEST
CONDITIONS
MAX
2.3
2.8
1.7
3.4
3.6
0.5
0.3
1.2
0.8
SN74ASC6120
MIN
0.5
0.9
0.8
1.1
0.2
0.1
TYP*
0.9
1.2
1.6
1.7
MAX
2.1
2.6
3.1
0.5
1.1
0.7
0.3
3.3
UNIT
ns
ns
ns/pF
BU130LH
tPLH
tpHL
dtpLH
dtpHL
A
Y
A
Y
TEST
CONDITIONS
CL
CL
=0
=
1 pF
SN54ASC6120
MIN
0.6
SN74ASC6120
MIN
0.6
0.9
0.8
1
TYP*
1.3
1.5
1.6
1.8
MAX
2.6
3.2
3.4
3.B
0.9
0.8
1.1
0.1
0.1
0.3
0.3
0.8
0.7
0.2
0.1
TYP*
1.3
1.5
MAX
2.4
1.6
1.8
2.9
3.1
3.5
0.3
0.3
0.6
0.8
UNIT
ns
ns
ns/pF
t Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tPLH " propagation delay time, low-to-high-Ievel output
tpHL .. propagation delay time, hlgh-to-Iow-)evel output
.6.tpLH
iiii
change in tpLH with load capacitance
dtpHL .. change in tpHL with load capacitance
Typical values are at VCC = 5 V, TA = 25°C.
*
DESIGN CONSIDERATIONS
Refer to Section 7.
4-746
TEXAS""
INSTRUMENTS
POST OFFICE BOX 656012 • OALLAS, TEXAS 76265
SN54ASC6121, SN74ASC6121
NONINVERTING 3·STATE BUFFERS
WITH ACTIVE·LOW ENABLE
02939, AUGUST 1986
SystemCell™
•
2·llm INTERNAL STANDARD CELL
logic symbol
Choice of Two Performance Levels
•
Active Low Enable
•
Specified for Operation Over
4,5 V to 5.5 V
•
Functional Operation Over
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
Vee
Vee
A----{>--Y
Range of
GZ~
Range of
FUNCTION TABLE
INPUTS
positive logic equation
Y=A
OUTPUT
GZ
A
Y
L
H
H
L
L
L
H
X
Z
description
The SN54ASC6121 and SN74ASC6121 are noninverting 3-state internal buffer standard cells that interface
internal cells with internal buses, The standard-cell library contains two physical implementations providing
the custom IC designer a choice from two performance levels for optimizing designs. Each option is
designated and called from the engineering workstation input using the following cell names to develop
labels for the design netlist:
FEATURES
NETLIST
HDL LABEL
CELL NAME
BU221LH
BU261LH
Label: BU2nl LH A,GZ,Y;
II
...
tI)
TYPICAL
DELAY
RELATIVE
CELL AREA
CL - 1 pF
TO NA210LH
2.3 ns
2.75
2 ns
4.75
G)
G)
.c
en
...asas
The SN54ASC6121 is characterized for operation over the full military temperature range of - 55°C to
125°C, The SN74ASC6121 is chara.cterized for operation from -40°C to 85°C.
C
absolute maximum ratings and recommended .operating conditions
See Table 1 in Section 2,
electrical characteristics
PARAMETER
TEST CONDITIONS
I v~ __I_n_p~u_t_t_hr_e_sh_o_ld_v_oTlt~a~ge07~~~-r-,v7c~c~--.5.V~'77~~~7T~A~-~2_5_0~C__~_T-1_2_._2__~~r-_2_.2__~~;-!__V__~
lee Supply current
Ci
SN54Ase6121
Vee - 4.5 V to 5.5 V, VI - Vee or 0,
328
562
SN74Ase6121
TA = MIN to MAX
19.7
33.7
A
Input capacitance rG:':Z:--------I
Equivalent power
Cpd dissipation capacitance
8.
Vee
=
5 V,
tr - tf - 3 ns,
~:c'!=~i~.{::,~l~ ~=:~i:; lI~D::;::A!~~ not
0.28
0.32
0.28
1.62
3.29
nA
pF
pF
Copyright © 1986, Texas Instruments Incorporated
PRODUCTION DATA documonts contain information
currant of publication data. Praducts conform to
specifications par the terms of Taxas Instrumants
0.14
TEXAS •
INSTRUMENTS
POST OFFICE t!OX 655012 • DALLAS, TEXAS 75265
4-747
SN54ASC6121, SN74ASC6121
NONINVERTING 3·STATE BUFFERS
WITH ACTIVE· LOW ENABLE
switching characteristics over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise noted)
BU221LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
TO
TEST
(OUTPUTI
CONDITIONS
A
Y
A
Y
tpZH
GZ
Y
tpZL
GZ
y
tPHZ
GZ
y
tpLZ
GZ
y
A.tpLH
t.tpHL
A.tPZH
A.tpZL
•
FROM
(lNPUTI
A
Y
GZ
Y
CL
SN54ASC6121
=0
= 1 pF
CL
CL - 1 pF,
RL
= 40klltoGND
RL
= 20 kll to VCC
MAX
MIN
TYP*
MAX
0.6
3.6
0.7
1.5
3.2
1
1.6
3.4
1.6
3.1
RL
= 20 kll to VCC
1.1
2.5
5.8
2.5
5.3
2.1
4.6
1.2
2.1
4.2
0.7
1.4
2.9
0.7
1.4
2.7
ns
1
1.6
3.4
1
1.6
3.1
ns
10
GND
1 pF,
CL
ns
1.2
CL - 1 pF,
= 40 kll to
UNIT
1
1.2
CL - 1 pF,
RL
SN74ASC6121
TYP*
1.5
MIN
10
5.3
ns
ns
5.3
ns
0.5
1
2.3
0.5
1
2.1
0.2
0.0
1.3
0.2
0.5
1.1
0.5
0.9
2.2
0.2
0.5
1.3
0.5
0.2
0.9
0.5
2
1.2
nsipF
SN74ASC6121
TVP;
MAX
UNIT
nsipF
BU261LH
o
PARAMETERt
~
tpLH
tpHL
en
tpLH
:r
tpHL
CD
CD
....tn
FROM
to
TEST
(lNPUTI
(OUTPUT)
CONDITIONS
Y
A
Y
CL
CL - 1 pF,
tpZH
GZ
y
tpZL
GZ
y
tPHZ
GZ
y
tpLZ
GZ
Y
A.tpLH
A.tpHL
A.tpZH
A.tpZL
=0
A
A
y
GZ
y
CL
= 1 pF
RL
= 40klltoGND
RL
= 20klltoVCC
CL - 1 pF,
SN54ASC6121
MIN
TYP*
MAX
MIN
0.7
1.5
3.3
1.2
2
4.1
0.8
1.2
= 40 kll to GND
RL
= 20 kll to V CC
CL
2.9
2
3.8
ns
0.8
1.7
3.8
0.9
1.7
3.4
1.3
2.2
4.6
1.3
2.2
4.2
1.2
2.2
4.8
1.2
2.2
4.3
ns
1.1
2
4.4
1.1
2
4
ns
CL - 1 pF,
RL
1.5
1 pF,
ns
16
16
ns
7.4
7.4
ns
0.1
0.1
0.2
0.5
0.1
0.2
0.5
0.2
0.6
0.1
0.1
0.2
0.5
0.1
0.2
. 0.2
0.5
0.5
0.1
0.2
0.7
0.1
0.2
0.6
nsipF
nsipF
tPropagation delay times are measured from,the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tpLH '" propagation delay time, low-to-high-Ievel output
A.tPLH '" change in tpLH with load capacitance
A.tpHL '" change in tpHL with load capacitance
tpHL '" propagation delay time, high-to-Iow-Ievel output
tpZH .. output enable time to high level
A.tpZH '" change in A.tpZH with load capacitance
tpZL '" output enable time to low level
A.tpZL '" change in A.tpZL with load capacitance
tpHZ '" output disable time from high level
tPLZ '" output disable time from low level
Typical values are at VCC = 5 V, TA = 25°C.
*
DESIGN CONSIDERATIONS
Refer to Section 7.
4-748
TEXAS . "
,INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC6122. SN74ASC6122
NONINVERTING 3-STATE BUFFERS
WITH ACTIVE-HIGH ENABLE
02939, AUGUST 1986
SystemCell™
2-jlm INTERNAL STANDARD CELL
•
Choice of Two Performance Levels
•
Active-High Enable
•
Specified for Operation Over VCC Range of
4.5 V to 5.5 V
•
Functional Operation Over VCC Range of
2Vt06V
•
logic symbol
:=S>-y
FUNCTION TABLE
Dependable Texas Instruments Quality and
Reliability
INPUTS
positive logic equation
Y=A
OUTPUT
G
A
Y
H
H
H
H
L
L
L
X
Z
description
The SN54ASC6122 and SN74ASC6122 are noninverting 3-state internal buffer standard cells that interface
internal cells with internal buses. The standard-cell library contains two physical implementations providing
the custom IC designer a choice from two performance levels for optimizing designs. Each option is
designated and called from the engineering workstation input using the following cell names to develop
labels for the design netlist:
...
FEATURES
CELL NAME
BU222LH
BU262LH
U)
NETLIST
TYPICAL
RELATIVE
HDL LABEL
DELAY
CELL AREA
CL - 1 pF
TO NA210LH
2.3 ns
2.75
2 ns
4.75
Label: BU2n2LH A,G,Y:
II
Q)
Q)
.s=
(/)
...
ftS
ftS
The SN54ASC6122 is characterized for operation over the full military temper\lture range of - 55°C to
125°C. The SN74ASC6122 is characterized for operation from -40°C to 85°C .
C
. absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
• I
.........
"'''''UL
LIII"'~I'UI""
"
....... , .. ""l;t ...
lee Supply current
"l.l.
~
TYP
-- ..,r:-n,...
..-,'
... '"
''''
_.~
~
~
~
ISN54Ase6122
vee = 4.5 V to 5.5 V, VI = Vee or 0,
328
562
I SN74ASe6122
TA = MIN to MAX
19.7
33.7
Input capacitance
Vee - 5 V,
TA - 25°e
Equivalent power
Cpd dissipation capacitance
Vee = 5 V,
tr = tf = 3 ns,
ej
I BU262LH
MAX I TYP MAX
BU222LH
TEST CONDITIONS
TA = 25°e
PRODUCTION DATA documonts cont.in information
currant .s .1 public.tion data. Products c••form to
spacifications par the terms of rexas Instruments
::=:~~a[::,-::18 ~!:~:~ti:; :.r::::::~::.~
not
UNIT
"
nA
0.14
0.28
pF
1.62
3.3
pF
Copyright © 1986, Texas Instruments Incorporated"
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-749
SN54ASC6122. SN74ASC6122
NONINVERTING 3·STATE BUFFERS
WITH ACTIVE·HIGH ENABLE
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
BU222LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
tpZH
tpZL
tPHZ
tpLZ
AtPLH
AtpHL
II
AtpZH
AtpZL
FROM
TO
TEST
(INPUT)
(OUTPUT)
CONDITIONS
A
V
G
v
G
G
G
A
1.6
1.5
2.6
5.9
1.2
2.6
5.3
1.2
2
4.5
1.2
2
4.1
CL - 1 pF,
= 40 kO to G ND
0.8
1.8
4.2
0.9
1.8
3.8
CL - 1 pF,
RL = 20 kO to V CC
0.4
1.1
2.5
0.4
1.1
2.3
RL
=
=
=
0
1 pF
0.6
1 pF,
11
40 kO to GND
CL - 1 pF,
RL
=
FROM
(INPUT)
TO
(OUTPUT)
A
V
0.5
1
0.2
0.4
0.4
3
11
4.5
20 kO to V CC
Y
y
MAX
0.7
1
CL
G
TYP*
3.6
3.3
RL
V
SN74ASC6122
MIN
1.6
1.5
CL
V
MAX
1
1.1
=
CL
V
TYP*
3.3
V
A
SN54ASC6122
MIN
UNIT
ns
ns
ns
ns
ns
ns
4.5
2.1
2.3
0.5
1
0.5
1.3
0.2
0.5
1.1
1.1
2.4
0.5
1.1
2.2
0.6
1.3
0.4
0.6
1.1
SN54ASC6122
MAX
TYP*
MIN
nsipF
nsipF
BU262LH
PARAMETERt
tpLH
tpHL
tpLH
tpHL
tPZH
A
Y
G
V
tpZL
G
y
tpHZ
G
V
tpLZ
AtpLH
AtPHL
AtpZH
AtpZL
G
V
A
Y
G
y
TEST
CONDITIONS
CL
=
0
CL
=
1 pF
C..:
=
1 pF,
RL = 40kOtoGND
C~
- 1 pF,
RL = 20 kO to V CC
CL - 1 pF,
RL
=
MIN
0.7
1.5
3.3
0.8
1.5
3
1.2
2
4.1
1.2
2
3.8
0.8
1.7
3.8
0.9
1.7
3.4
1.3
2.2
4.6
1.3
2.2
4.2
0.6
1.5
3.4
0.7
1.5
3
0.9
2.3
5.6
1
2.3
5
40 kO to GND
CL - 1 pF,
RL
=
SN74ASC6122
MAX
TYP*
20 kO to V CC
UNIT
ns
ns
ns
ns
16
16
ns
8
8
ns
0.1
0.2
0.5
0.1
0.2
0.5
0.1
0.2
0.6
0.1
0.2
0.5
0.1
0.2
0.6
0.1
0.2
0.5
0.1
0.2
0.7
0.1
0.2
0.6
nsipF
nsipF
tpropagation delay times are measured from the 44% point of VI to the 44% point of Va with tr = tf = ,3 ns (10% and 90%1.
AtpLH '" change in tpLH with load capacitance
tPLH '" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
AtpHL '" change in tpHL with load capacitance
tpZH '" output enable time to high level
AtpZH '" change in AtpZH with load capacitance
tpZL '" output enable time to low level
AtPZL '" change in AtpZL with load capacitance
tpHZ '" output disable time from high level
tpLZ '" output disable time from low level
*Typical values are at VCC = 5 V, TA = 25°C.
4-750
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54ASC6125, SN74ASC6125
OoTYPE LATCHES WITH ACTIVE-LOW ENABLE
02939, AUGUST 1986
SystemCell™
2-/lm HARDWIRED MACRO CELL
•
Provides Complementary Q and QZ Outputs
•
Transparent When Enable Is Low
•
Implements Control/Status Registers
•
Parallel Latches to Implement Wide Word
Widths
logic symbol t
Jt=:
:~
..'_CD_l_ _ _
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
description
The SN54ASC6125 and SN74ASC6125 are
dedicated, hardwired standard-cell macros
implementing bistable latches. The 'ASC6125
latches provide an active-low enable, C, with a
transparent storage element to embed in ASICs
in its most efficient form, The 'ASC6125 latches
implement identical function and sequential
operation to one-fourth of the 'LS75 packaged
latches except the' ASC125 enable is active-low
and available on each individual latch.
FUNCTION TABLE
INPUTS
OUTPUT
0
L
C
Q
OZ
L
L
H
H
X
L
H
L
H
00
OZO
Information present at the data (0) input is transferred to the Q output when the enable input is low, and
the Q output will follow the data input as long as enable remains low. When enable goes high, the data
(that was present at the data input at the time the transition occurred) are retained at the Q output until
the enable is again taken low. The cells are designated and called from the engineering workstation input
using the following cell name to develop labels for the design netlist:
RELATIVE
NETLIST
CELL NAME
TO NA210LH
Label: LALnOLH D,C,a,az;
LAL20LH
CI)
Q)
Q)
.s::::
en
....caca
CELL AREA
HDL LABEL
II
..
C
4.25
The SN54ASC6125 is characterized for operation over the full military temperature range of - 55°C to
'125°C. The SN74ASC6125 is characterized for operation from -40°C to 85°C.
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
timing requirements over recommended ranges of supply voltage and operating free-air temperature
..
\Uliitliii:.:.
..
.
U'lla.vv.~'CJ
IIUL'CiiUI
MIN
tw
Pulse duration
tsu
Setup
th
Hold time
tim~
I
C low
0 high or low
9
10.8
I
0 high or low
0
I
PRODUCTION DATA documents contain informadon
currant IS of publication data. Products conform to
specifications par tha terms of Taxas Instrumants
:::::i;·i~r:I~~~ ~:~::i:: :.r:=::::~::.~ nat
MAX
UNIT
ns
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-751
SN64ASC6126, SN74ASC6125
O·TYPE LATCHES WITH ACTIVE· LOW ENABLE
electrical characteristics
PARAMETER
VT
Input threshold voltage
ICC
Supply current
ei
epd
SN54ASC6125
TEST CONDITIONS
Input Capacitance
I
TYP
TA
e
Equivalent power
dissipation capacitance
=
Vee
TA
5 V,
Vee = 5 V,
TA = 25°C
tr
=
3 ns,
30.3
0.27
0.27
0.28
0.28
4.68
4.68
UNIT
V
505
25°C
= tf =
MAX
2.2
MIN to MAX
=
TYP
2.2
TA - 25°C
Vee - 5 V,
Vee - 4.5 V to 5.5 V, VI - Vee or 0,
0
SN74ASC6125
MAX
nA
pF
pF
switching characteristics over recommended ranges of supply volatge and operating free-air temperature
(unless otherwise noted)
PARAMETERt
tpLH
tpHL
tpLH
tpHL
tpLH
II
tpHL
tPLH
tpHL
tpLH
tpHL
tpLH
tPHL
tpLH
tpHL
tpLH
tpHL
.:1tpLH
.:1tpHL
FROM
(INPUT)
TO
TEST
(OUTPUTI
CONDITIONS
0
Q
0
QZ
CL
e
Q
e
QZ
0
Q
0
QZ
eL
e
Q
e
QZ
Any
=0
=
1 pF
Q,QZ
SN54ASC6125
MIN
SN74ASC6125
MAX
MIN
10.7
1.9
TYP*
4.2
MAX
1.8
TYP*
4.2
1.3
2.5
5.9
1.4
2.5
5.3
9.5
2
4
10
2.1
4
8.9
1.1
2.8
6.9
1.2
2.8
6.2
2.1
4
9.4
2.2
4
8.4
1.5
2.6
5.7
1.6
2.6
5.2
2.1
4.1
9.7
2.3
4.1
8.7
1.5
2.5
5.8
1.6
2.5
5.2
2
4.7
11.8
2.2
4.7
10.5
1.5
7
2.2
3
4:5
11.1
1.6
2.4
3
4.5
6.3
9.9
1.3
3.2
3.2
7.2
4.5
8
10.5
1.5
2.3
2.4
4.5
9.4
1.7
3
6.8
1.8
3
6.2
2.4
4.6
10.8
2.5
4.6
9.6
1.7
6.9
1.1
1.8
0.2
3
0.2
3
0.5
0.5
6.2
1
0.1
0.5
1.1
0.2
0.5
1
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
nsipF
tpropagation delay times are measured from the 44% point of VI to the 44% pOint of Vo with tr = tf = 3 ns (10% and 90%1.
tpLH .. propagation delay time, low-to-high·level output
tPHL '" propagation delay time, high-to-Iow-Ievel output
.:1tpLH '" change in tpLH with load capacitance
.:1tpHL '" change in tPHL with load capacitance
Typical values are at Vee = 5 V. TA = 25°C.
*
4-752
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
SN54ASC6125, SN74ASC6125
O·TVPE LATCHES WITH ACTIVE·LOW ENABLE
DESIGN CONSIDERATIONS
interfacing the macro
Inputs and outputs of these dedicated macros are compatible for interfacing directly with cells and macros
available in the TI standard cell library. The inputs can be driven by either noninverting or inverting input
cells. The outputs can be interfaced to drive off-chip loads with any of the noninverting output buffers
or interfaced to external bidirectional buses through a 3-state input/output TTL/CMOS buffer.
designing for testability
Designers employing storage or bistable elements should consider testability of the design in its final form.
The need to preset or clear these elements should be assessed throughout the development of custom
logic circuits with these considerations extended to the end equipment application with respect to
maintainability. Simple actions on the part of the ASIC designer can result in considerable cost savings,
allowing the expense of IC testing, system testing, and system maintenance to be reduced significantly.
power-up clear/preset
Standard cell storage elements containing the capability to be asynchronously preset or cleared may be
connected to the SN54ASC2320 or SN74ASC2320 power-up clear cell to achieve system initialization.
Control of the clear or preset inputs from another system signal in conjunction with the power-up clear
can be achieved with an AND gate.
II
...
en
Q)
Q)
.t:
U)
...caca
C
TEXAS .."
INSTRUMENTS
, POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-753
•
c
Q)
r+
Q)
en
':r
CD
CD
r+
en
4-754
SN54ASC6130, SN74ASC6130
5-INPUT POSITIVE-OR GATES
D2939, AUGUST 1986
SystemCell™
2-l-Im INTERNAL STANDARD CELL
•
3.4 ns Typical Propagation Delay With
1-pF Load
•
Specified for Operation Over
4.5 V to 5.5 V
•
Functional Operation Over
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
Vee
Vee
logic symbol t
Range of
Range of
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
positive logic equation
FUNCTION TABLE
Y = A+B+C+D+E
INPUTS
OUTPUT
A
B
C
D
E
Y
H
X
X
X
X
H
description
The SN54ASC6130 and SN74ASC6130 are
5-input positive-OR gate CMOS standard cells.
Each cell is designated and called from the
engineering workstation input using the
following cell names to develop labels for the
design netlist:
X
H
X
X
X
H
X
X
X
H
X
X
X
H
X
X
H
H
X
X
X
X
H
H
L
L
L
L
L
L
II
...
II)
CD
CD
FEATURES
NETLIST
CELL NAME
TYPICAL
DELAY
CELL AREA
(J)
CL - 1 pF
TO NA210LH
3.4 ns
2.25
CO
CO
HDL LABEL
OR510LH
.c
RELATIVE
Label: OR510LH A,B,e,D,E,Y;
...
The SN54ASC6130 is characterized for operation over the full military temperature range of - 55°C to
125°C, The SN74ASC6130 is characterized for operation from -40°C to 85°C,
C
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
Input threshold voltage
!
lee Supply current
ej
~pd
I
C::~~511.A_~~,=~~~
TYP
TEST CONDITIONS
PARAMETER
I VT
!
I
SN74Ase6130
."...
TA =
~
-
...
,..
...... w
"
po
......
............
v,
MIN to MAX
Input capacitance
Vee = 5 V,
Equivalent power
Vee - 5 V,
dissipation capacitance
TA = 25°e
"'
-
·v·(;C
:=ir,a[::I~'li ~~":\:~~r :.\o=:::~:;.~ not
UI
MAX
UNIT
V
2.2
v,
LOO
15.3
TA - 25°e
tr - tf - 3 ns,
PRODUCTIOII DATA documents conloln 'info,motion
currant as of publi.ation dall!. P'oducts conform to
spacificltiaDS per tha terms of Taxas Instrumanli
I
TA - 25°e
Vee - 5 V,
nA
0.11
pF
1.11
pF
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-755
SN54ASC6130, SN14ASC61.30
5-INPUT POSITIVE-OR GATES
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETERt
tpLH
tpHL
tpLH
tPHL
dtpLH
dtpHL
FROM
UN PUT)
A thru E
A thru E
A thru E
TO
(OUTPUT)
SN54ASC6130
TEST
CONDITIONS
Y
CL = 0
CL = 1 pF
Y
Y
SN74ASC6130
MAX
MIN
TYP*
MAX
0.9
TYP*
1.8
4
1
1.8
3.6
1.4
3.1
9.1
1.4
3.1
8.2
1.4
6.3
1.5
2.8
5.7
1.7
2.8
4
11.3
1.9
4
0.4
1
2.4
0.5
1
10
2.2
0.3
0.9
2.2
0.4
0.9
1.9
MIN
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr
tpLH '" propagation delay time. 10w-!0-highClevel output
tpHL '" propagation delay time. high-to-Iow-Ie"el output
4tpLH = change in tplH with load capacitance
dtpHL '" change in tpHL with load capacitance
Typical values are at VCC = 5 V. TA = 25°C.
=
tf
=
UNIT
ns
ns
ns/pF
3 ns (10% and 90%).
*
DESIGN CONSIDERATIONS
II
4-756
Refer to Section 7.
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
TEXAS •
INSTRUMENTS
POST OFFICE
aox
655012 • DALLAS. TEXAS 76265
SN54ASC6131, SN74ASC6131
8-INPUT POSITIVE-OR GATES
D2939. AUGUST 1986
SystemCell™
2-/Am INTERNAL STANDARD CELL
•
3.3 ns Typical Propagation Delay with '-pF
Load
•
Specified for Operation Over
4.5 V to 5.5 V
•
Functional Operation Over
2Vt06V
•
Dependable Texas Instruments Quality and
Reliability
Vee
Vee
logic symbol
Range of
Range of
FUNCTION TABLE
positive logic equation
=
Y
INPUTS
A B C 0
ABCDEFGH
A+B+C+D+E+F+G+H
description
The SN54ASC6131 and SN74ASC6131 are
8-input positive-OR gate CMOS standard cells.
Each cell is designated and called from the
engineering workstation input using the
following cell name to develop labels for the
design netlist:
OUTPUTS
E F G H
Y
H X X X X X X X
H
X
X
X
X
X
X
X
H X X X X X X
H
H X X X X X
H
X
X
X
X
X
H X X X X
H
X
X
X
X
H X X X
H
X H X X
X X H X
X X X H
H
H
l
l
l
l
X
X
X
X
X
X
L l
l
l
II
...
H
l
rn
NETLIST
CELL NAME
OR810lH
Q)
Q)
FEATURES
TYPICAL
RELATIVE
HDL LABEL
label: OR810lH A.8.C.D.E.F.G,H,Y;
DELAY
CELL AREA
CL - 1 pF
3.3 ns
TO NA210lH
J:.
en
...caca
3.25
The SN54ASC6131 is characterized for operation over the full military temperature range of - 55°C to
125°C. The SN74ASC6131 is characterized for operation from -40°C to 85°C.
C
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
VT
PARAMETER
Input threshold voltage
lec
Supply current
Cj
Cpd
TEST CONDITIONS
VCC
Vee
-;-A -
= 5 V,
= 4.5 V
Input capacitance
Vee
=
Equivalent power
Vec - 5 V,
TA = 25°e
1 SN54ASC6131
... , . , ....." ................ ,
...... ,~"
A ................ ~
dissipation capacitance
PRODUCTION DATA documents contein information
currant 8S of publication date. Products conform to
specifications par the terms of Taxas Instruments
=~~i~Bi~=i =:~:r :.~o::::::9t:~~
not
:v~;;~
LU
TYP
TA - 25°C
to 5.5 V, VI
= Vee
UNIT
V
384
or 0,
;V~M~
5 V,
MAX
2.2
nA
~".I
TA
=
25°e
t r - tf - 3 ns,
-iii
INSTRUMENTS
TEXAS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
0.11
pF
1.16
pF
Copyright © 1986. Texas Instruments Incorporated
4-757
SN54ASC6131, SN74ASC6131
8-INPUT POSITIVE-OR GATES
switching characteristics over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted)
PARAMETERt
tpLH
tpHL
tpLH
tpHL
dtpLH
dtpHL
TEST
FROM
(INPUT)
TO
(OUTPUT)
CONDITIONS
A thru H
Y
CL = 0
A thru H
Y
A thru H
Y
CL = 1 pF
SN54ASC6131
SN74ASC6131
MAX
MIN
0.8
TYP*
1.7
3.9
1.3
2.9
7.4
1.3
2.7
6.1
1.8
3.9
0.4
0.4
MIN
TYP*
MAX
0.8
1.7
3.5
1.4
2.9
6.6
2.7
5.5
10.2
1.4
1.9
3.9
9
1
2.3
0.5
1
2.1
1
2.8
0.5
1
2.4
UNIT
ns
ns
nsipF
tpropagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns (10% and 90%).
tpLH " propagation delay time. low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
.6.tPLH
5"
change in tPLH with load capacitance
dtpHL " change in tpHL with load capacitance
Typical values are at VCC = 5 V, TA =25°C.
*
DESIGN CONSIDERATIONS
II
o
I»
Refer to Section 7.
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design.
A tie-off cell is offered specifically for managing unused inputs.
....
I»
C/)
::T
CD
CD
....
(I)
4-758
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXA..S 75265
SN54ASC6132, SN74ASC6132
8-INPUT POSITIVE-AND GATES
D2939, AUGUST 1986
SystemCell™
2-",m INTERNAL STANDARD CELL
logic symbol
•
3.4 ns Typical Propagation Delay
•
Specified for Operation Over Vee Range of
4.5 V to 5.5 V
A
B
C
•
•
Functional Operation Over Vee Range of
2Vt06V
D
Y
E--"'L._""
Dependable Texas Instruments Quality and
Reliability
F
G
H
positive logic equations
= ABC
Y
D EFGH
=-~~~~~~-=
= A+B+C+D+E+F+G+H
FUNCTION TABLE
INPUTS
description
The SN54ASC6132 and SN74ASC6132 are
8-input positive-AND gate CMOS standard cells.
Each cell is designated and called from the
engineering workstation input using the
following cell name to develop labels for the
design netlist:
OUTPUT
A B C D E F G H
Y
H H H H H H H H
H
Any other combination
l
•
FEATURES
NETLIST
HDllABEl
TYPICAL DELAY
Label: AN810LH A,B,e,D,E,F,G,H,Y;
3.4 ns
CEll NAME
AN810LH
Cl - 1 pF
....
U)
RELATIVE
Q)
Q)
CEll AREA
.c
TO NA210lH
til
3.25
The SN54ASC6132 is characterized for operation over the full military temperature range of - 55 DC to
125 DC. The SN74ASC6132 is characterized for operation from _40DC to 85 DC.
....caca
C
absolute maximum ratings and recommended operating conditions
See Table 1 in Section 2.
electrical characteristics
PARAMETER
Input threshold voltage
TEST CONDITIONS
TYP
2.2
ICC
Supply current
C;
Input capacitance
TA = 25°C
Vce = 5 V,
VCC - 4.5 V to 5.5 V, VI - VCC or 0,
TA = MIN to MAX
Vr-,.. = 5 V.
Til = 'nor.
Equivalent power
VCC - 5 V,
dissipation capacitance
TA
VT
Cpd
LSN54ASC6132
I SN74ASC6132
PRODUCTION DATA documant. contain information
currant a. of publication date. Products conform to
'SPIIclficatians per the terms of Taxal Instruments
:=:~~i;8i:I~7e ~!=::i~n lIID::;::::':~~ not
=
t r - tf - 3 ns,
25°C
MAX
V
403
24.2
n
UNIT
nA
1~
~~
1.22
pF
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-759
SN54ASC6132, SN74ASC6132
a·INPUT POSITIVE·AND GATES
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETERt
tpLH
tpHL
tpLH
tpHL
AtpLH
AtPHL
FROM
(INPUT)
A thru H
A thru H
A thru H
TO
(OUTPUT)
Y
Y
TEST
CONDITIONS
CL = 0
CL = 1 pF
Y
SN54ASC6132
Typt MAX
MIN
0.9
2.2
5.3
0.8
1.9
3.9
1.9
4.2
9.8
1.1
2.5
5.4
0.9
2
4.6
0.2
0.6
1.6
SN74ASC6132
Typt MAX
MIN
1
0.8
2.2
4.7
1.9
3.6
2
1.1
1
0.3
4.2
8.8
2.5
4.9
2
4.2
0.6
1.4
UNIT
ns
ns
ns/pF
t Propagation delay times are measured from the 44% point of VI to the 44% point of Vo with tr = tf = 3 ns 110% and 90%).
tPLH '" propagation delay time, low-to-high-Ievel output
tPHL '" propagation delay time, high-to-Iow-Ievel output
AtPLH '" change in tpLH with load capacitance
AtpHL '" change in tpHL with load capacitance
iTypical values are at VCC = 5 V, TA =25°C.
DESIGN CONSIDERATIONS
•
Refer to Section 7 .
All inputs to this cell must be accounted for in the netlist used to generate the next level of an ASIC design,
A tie-off cell is offered specifically for managing unused inputs.
C
DI
pot.
DI
en
::r
CD
CD
pot.
til
4-760
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 .. DALLAS. TEXAS 75265
Military
5-1
5-2
TEXAS INSTRUMENTS MILITARY-QUALIFIED STANDARD CELL PRODUCTS
The System Cell"' product family offered by Texas Instruments has been designed to operate over the full
military temperature range of - 55 DC to + 125 DC. All cells have been characterized for this extended
temperature range performance and the military TI software library contains this information, allowing for
engineering workstation simulation at both temperature extremes. For military and other high-reliability
applications, these standard cells are manufaCtured in compliance with the requirements of JEDEC
Publication 111 (JEDEC's rewrite of Method 50; 0 of MIL-STD-883). When required, full qualification
processing is available in accordance with the standards set forth in MIL-STD-883.
•
The extensive Texas Instruments military semiconductor experience and resources are utilized to supply
high-reliability military-qualified standard cell devices. All wafers are processed in facilities that have DESCcertified product flows. Prototypes are available in JEDEC-Standard ceramic packages and may be supplied
after testing over the full military temperature range. When production devices are required, TI offers
complete capabilities to fabricate, assemble, and test standard cell devices within the continental United
States, allowing for compliance with complete-domestic program requirements. TI's offshore production
facilities are also available to provide cost-effective military-processed devices.
MILITARY HIGH-RELIABILITY STANDARD CELL INTEGRATED CIRCUITS
The Texas Instruments military standard cell program offers several production options designed to meet
system cost, reliability, leadtime, and contract requirements. The following are the key features of the
options available for MIL-M-3851 0 and MIL-STD-883 Class B applications and can be produced either onor offshore.
MIL-STD-883, Level B Screening
•
•
•
•
•
Produced under MIL-STD-883 guidelines
with all chips manufactured in facilities with
DESC-certified product flows
All production devices assembled and tested
in a certified facility
Fully tested as per MIL-STD-883
Method 5004/5005
Electrical specification limits to be jointly
agreed upon by the customer and TI
Each lot shipment includes a Certificate of
Conformance and Group A summary report
883/JEDEC Custom/Semicustom Screening
•
•
•
•
•
Produced under MIL-STD-883 guidelines
with all chips manufactured in facilities with
DESC-certified product flows
All production devices assembled and tested
in a certified facility
Fully tested as per MIL-STD-883
Method 5010 or JEDEC Publication 111
Electrical specification limits to be jointly
agreed upon by the customer and TI
•
~
CO
:i
:2:
Each lot shipment includes a Certificate of
Conformance and Group A summary report
TEXAS •
INSTRUMENTS
fJOST OFFICE BOX 655012 • DALLAS, TEXAS 76265
5-3
MILITARY SCRE!=NING AND LOT CONFORMANCE-CLASS B.
SCREEN
METHOD
REQUIREMENT
METHOD
METHOD
5010 or
5004/5005
JEDEC 111
Internal Visual (Precap)
2010, Note 1
100%
Backside· Symbol
Diffusion lot identified by code year and week of seal
100%
100%
Stabilization Bake
1008,24 Hr Min, 150°C Max, Condition C
100%
100%
Temperature Cycle
1010, Condition C, Note 1
100%
100%
COl1stant Acceleration
2001, V1 Only, Condition E, Note 2
100%
100%
Overvoltage Test
100%
As per device specification at manufacturer's option,
may.be performed at Probe, Note 1
100%
100%
As per device specification, 25°C
100%
Burn-In
1015, 160 Hr at 125°C (Min). Condition A, Note 5
100%
100%
100%
Post-Bum-In Test
As per deyice specification, 25 oCr DC
100%
100%
100%
100%
Pre-Burn-In Test
Final Electrical Test
Seal
(A) Fine
As per device specification, - 55°C, 125°C; and 25°C
switching
(BI Gross
1014, Note 2 Condition B
Limit = 5 x 10 - 8 Condition C
Quality Conformance
5005, Class B
100%
100%
LTf>D
(Note 6)
Inspection Group A (Note 4)
(A) Static
(Subgroup 1)
2
3
(B) Switching 25°C
(Subgroups 2 and 3)
(Subgroup 9)
(C) Functional 25°C
(Subgroup 7)
2
5
Customer
Customer
(1) 25°C
(2) Temp
•
Groups B, C, D, and E
2
(Note 3)
Option
,
5
7
5
Option
(Note 7)
S
-.
;-<
5-4
External Visual Inspection
NOTES:
100%
2009
100%
1. Overvoltage test conditions. limits, and application will be identified by Texas Instruments upon compleiion of design
characterization and will apply when the alternate screening procedure of Method 5004, Paragraph 3.3, is performed.
2. For device packages with 84 pins or less. For" larger pa~kages, test condition may require modification.
3. Available options depend on package type and size. Details of Groups B, C, D, and E testing and sampling plan to be negotiated.
4. If lot size is too small to meet LTPD requirements, 100% testing is acceptable.
5. T A may need to be reduced to prevent "maximurT! junction temperature from being exceeded.
6. Group A may be performed on QA in-line monitor program.
7. Extensive use of process control and test circuits for reduced cost.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • OAi..L~S, TEXAS 75265
IEEE Symbols
-6-1
m
m
m
(J)
-<
3
co
'fij
6-2
Explanation of Logic Symbols
F. A. Mann
Contents
Title
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYMBOL COMPOSITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QUALIFYING SYMBOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
General Qualifying Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Qualifying Symbols for Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . .
3.3
Symbols Inside the Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DEPENDENCY NOTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
General Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
G, AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
Conventions for the Application of Dependency Notation in General ....
4.4
V, OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
N, Negate (Exclusive-OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6
Z, Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7
X, Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8
C, Control ............' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9
S, Set and R, Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 EN, Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 M, Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 2 A, Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BISTABLE ELEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CODERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USE OF A CODER TO PRODUCE AFFECTING INPUTS . . . . . . . . . . . . . . . . . . . .
USE OF BINARY GROUPING TO PRODUCE AFFECTING INPUTS ............
SEQUENCE OF INPUT LABELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SEQUENCE OF OUTPUT LABELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Page
6-5
6-5
6-7
6-7
6-7
6-11
6-11
6-11
6-12
6-13
6-14
6-14
6-15
6-16
6-17
6-18
6-18
6-19
6-21
6-23
6-24
6-26
6-26
6-27
6-28
en
'0
.a
E
>
tn
W
W
W
If you have questions on this Explanation
of Logic Symbols, please contact:
Texas Instruments Incorporated
F.A. Mann, MS 49
P.O. Box 655012
Dallas, Texas 75265
IEEE Standards may be purchased from:
Institute of Electrical and Electronics Engineers, Inc.
IEEE Standards Office
345 East 47th Street
New York, N.Y. 10017
... I __ .... _~ ... _ _ L._:
r-,... \
__ I
,... _ _ _ : __ : _ _
I I
••. , .............. , ... , . . . . . . . . , ..................................... '
......... ' •• , ••• ,;,.;,0."" ••
, ......... ,
I _ ... _~ _ _ ... : _ _ _ I
Telephone (214) 995-2659
•
publications may be purchased from:
American National Standards Institute, Inc.
1430 Broadway
New York, N.Y. 10018
Copyright
© 1984, Texas Instruments Incorporated
6-3
List of Tables
Table
I
II
III
IV
Title
General Qualifying Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Qualifying Symbols for Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Symbols Inside the Outline .........................................
Summary of Dependency Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Page
6-8
6-9
6-10
6-23
List of Illustrations
Figure
1
2
3
4
-
m
m
m
C/)
'<
3
0'"
o
0'
5
6
7
8
9
10
11
12
13
14
1.5
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
6-4
Title
Symbol Composition .............................................
Common-Control Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Common-Output Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
G Dependency Between Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
G Dependency Between Outputs and Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . ..
G Dependency with a Dynamic Input ... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ORed Affecting Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Substitution for Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
V (OR) Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
N (Negate/Exclusive-OR) Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Z (Interconnection) Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
X (Transmission) Dependency. . . . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS Transmission Gate Symbol and Schematic . . . . . . . . . . . . . . . . . . . . . . ..
Analog Data Selector (Multiplexer/Demultiplexer) . . . . . . . . . . . . . . . . . . . . . . . ..
C (Control) Dependency . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . ..
S (Set) and R (Reset) Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
EN (Enable) Dependency ...........................................
M (Mode) Dependency Affecting Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Type of Output Determined by Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
An Output of the Common-Control Block . . . . . . . . . . . . . .. . . . . . . . . . . . . . ..
Determining an Output's Function ...................................
Dependent Relationships Affected by Mode ............................
A (Address) Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AFray of 16 Sections of Four Transparent Latches with 3-State Outputs
Comprising a 16~Word x 4-Bit Random-Access Memory. . . . . . . . . . . . . . . . . ..
Four Types of Bistable Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Coder .General Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
An X/V Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
An X/Octal Code Converter ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Producing Various Types of Dependencies .............................
Producing One Type of Dependency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Use of Binary Grouping Symbol .....................................
Input Labels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Factoring Input Labels .... ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Placement of 3-State Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Output Labels ..................................................
Factoring Output Labels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Page
6-6
6-6
6-7
6-12
6-13
6-13
6-13
6-14
6-14
6-1 5
6-1 5
6-16
6-16
6-16
6-17
6-18
6-19
6-20
6-20
6-21
6-21
6-21
6-22
6-23
6-24
6-24
6-25
6-26
6-26
6-26
6-27
6-27
6-28
6-28
6-28
6-29
1.0
INTRODUCTION
The International Electrotechilical Commission (lEC) has been developing a very powerful
symbolic language that can show the relationship of each input of a digital logic circuit to each
output without showing explicitly the internal logic. At the heart of the system is dependency
notation, which will be explained in Section 4.
The system was introduced in the USA in a rudimentary form in IEEE/ANSI Standard
Y32. 14-1973. Lacking at that time a complete development of dependency notation, it offered
little more than a substitution of rectangular shapes for the familiar distinctive shapes for
representing the basic functions of AND, OR, negation, etc. This is no longer the case.
Internationally, Working Group 2 of IEC Technical Committee TC-3 has prepared a new
document. (Publication 61 7 -1 2) that consolidates the original work started in the mid 1960's
and published in 1972 (Publication 117-15) and the amendments and supplements that have
followed. Similarly for the USA, IEEE Committee see 11.9 has revised the publication IEEE
Std 91/ANSI Y32.14. Now numbered simply IEEE Std 91-1984, the IEEE standard contains
all of the lEe work that has been approved, and also a small amount of material sti!1 under
international consideration. Texas Instruments is participating in the work of both organizations
and this document introduces new logic symbols in accordance with the neW standards. When
changes are made as the standards develop, future editions will take those changes into account.
tn
"0
The following explanation of the new symbolic language is necessarily brief and greatly
condensed from what the standards publications now contain. This is not intended· to be
sufficient for those people who will be developing symbols for new devices. It is primarily
intended to make possible the understanding of the symbols used in various data books and
the comparison of the symbols with logic diagrams, functional block diagrams, and/or function
tables to fur~her help that understanding.
2.0
.Q
E
r.n>
ttl
~
SYMBOL COMPOSITION
A symbol comprises an outline or a combination of outlines together with one or more qualifying
symbols. The shape of the symbol is not significant. As shown in Figure 1, general qualifying
symbols are used to tell exactly what logical operation is performed by the elements. Table I
shows general qualifying symbols defined in the new standards. Input lines are pl§Ged on the
ito; L clllU outPUt iines are placea on me ngnt. vvnen an exception is made to that convention,
the direction of signal flow is indicated by an arrow as shown in Figure 11.
All outputs of a single, unsubdivided element always have identical internal logic states
determined by the function of the element except when otherwise indicated by an associated
qualifying symbol or label inside the element.
6-5
OUTLINE
GENERAL QUALIFYING
SYMBOL
I ··..
..~
..
INPUT
LINES
OUTPUT
LINES
·Possible positions for qualifving symbols relating to inputs and outputs
Figure 1. Symbol Composition
The outlines of elements may be abutted or embedded in which case the following conventions
apply. There is no. logic connection between the elements when the line common to their outlines
is in the direction of signal flow. There is at least one logic connection between the elements
when the line common to their outlines is perpendicular to the direction of signal flow. The
number of logic connections between elements will be clarified by the use of qualifying symbols
and this is discussed further under that topic. If no indications are shown on either side of
the common line, it is assumed there is only one connection .
.....
m
m
m
t/)
<
3
When a circuit has one or more inputs that are common to more than one element of the circuit,
the common-control block may be used. This is the only distinctively shaped outline used in
the lEe system. Figure 2 shoWs that unless otherwise qualified by dependency notation, an
input to the common-control block is an input to each of the elements below the commoncontrol block.
Sen
•
COMMON~ONTROLBLOCK
a
a
b
b
c
d
c
d
Figure 2. Common-Control Block
6-6
A common output depending on all elements of the array can be shown as the output of a
common-output element. Its distinctive visual feature is the double line at its top. In addition
the common-output element may have other inputs as shown in Figure 3. The function of the
common-output element must be shown by use of a general qualifying symbol.
COMMON-OUTPUT
E L EME NT
:§; _
a
----------.
(must, like other elements,
have a qualifying symbol to
denote its logic function)
f-~---d
c
b
h-f-ot--- e
g
g
c--~---i
Figure 3. Common-Output Element
3.0
QUALIFYING SYMBOLS
3.1
General Qualifying Symbols
Table I shows general qualifying symbols defined by IEEE Standard 91. These characters are
placed near the top center or the geometric center of a symbol or symbol element to define
the basic function of the device represented by the symbol or of the element.
3.2
General Qualifying Symbols for Inputs and Outputs
I/)
15
..c
E
>
en
w
W
Qualifying symbols for inputs and outputs are shown in Table II and many will be familiar to W
most users, with the possible exception of the logic polarity and analog signal indicators. The . older logic negation indicator means that the external 0 state produces the internal 1 state.
The internal 1 state means the active state. Logic negation may be used in pure logic diagrams;
•
in order to tie the external 1 and 0 logic states to the levels H (high) and L (low), a statement
of whether positive logic (1 = H, 0 = L) or negative logic (1 = L,O "" H) is being used, is
required or must be assumed. Logic polarity indicators eliminate the need for calling out the
logic convention and are used in various data books in the symbology for actual devices. The
presence of the triangular polarity indicator indicates that the L logic level will produce the
produce the external L level. Note how the active direction of transition for a dynamic input
is indicated in positive logic, negative logic, and with polarity indication.
The internal connections between logic elements abutted together in a symbol may be indicated
by the symbols shown in Table II. Each logic connection may be shown by the presence of
qualifying symbols at one or both sides of the common line and if confusion can arise about
the number of connections, use can be made of one of the internal connection symbols.
6-7
Table I. General Qualifying Symbols
SYMBOL
DESCRIPTION
&
AND gate or function.
2::1
OR gate
~r
function. The symbol was chosen to indicate that at least
one active input is needed to activate the output.
=1
Exclusi)le OR. One and only one input must be active to activate the
output.
Logic identity. All inputs must stand at the same state.
2k
2k
An even number of inputs must be active.
+
An odd number pf inputs must be active.
1
The one input must be active.
I>
or
U)
Input for digital signals (on an analog symbol) (see Figure 141.
W
Internal connection. 1 state on left produces 1 state on right.
•
#1
----r-_. __9____
----~-
r--
Negated internal connection. 1 state on left produces 0 state on right.
Dynamic internal connection. Transition from 0 to 1 on left produces transitory 1 state on right.
Internal input (virtual input). It always stands at its internal 1 state unless affected by an overriding
dependency relationship.
W
W
Internal outout {virtual QutnutL Its effect on an internal inout to which it is connected is indicated bv
dependency notation.
The internal (virtual) input is an input originating somewhere else in the circuit and is not
connected directly to a terminal. The internal (virtual) output is likewise not connected directly
to a terminal. The application of internal inputs and outputs requires an understanding of
dependency notation, which is explained in Section 4.
6-9
Table III. Symbols Inside the Outline
-+-
Postponed output lof a pulse-triggered flip-flop). The output changes when input initiating change
le.g., a C input) returns to its initial external state or level. See § 5.
----1.lT
Bi-threshold input !input with hYsteresis)
~f-
N-P-N open-collector or similar output that can supply a relatively
low-impedance L level when not turned off. Requires external
pull-up. Capable of positive-logic wired-AND connection.
~f-
Passive-pull-up output is similar to N-P-N open-collector output
but is supplemented with a bUilt-in passive pull-up.
0~
N-P-N open-emitter or similar output that can supply a relatively
low-impedance H level when not turned off. Requires external pulldown. Capable of positive-logic wired-OR connection.
~~
Passive-pull-down output is similar to N-P-N open-emitter output
but is supplemented with a built-in passive pull-down.
V'f-
3-state output.
t>f-
Output with more than usual output capability Isymbol is oriented in the direction of signal flow).
-----j EN
Enable input
When at its internal 1-state, all outputs are enabled.
When at its internal O-state, open-collector and open-emitter outputs are off, three-state
outputs are in the high-impedance state, and all other outputs Ii.e., totem-poles) are at the
,internal O-state.
-mm
m
(f)
<
3
C'"
0
'{jj
J, K, R, S
----I>
Toggle input causes internal state of output to change to its complement.
T
-1 0
-1- -1-1m
II D:}
-j+m
--1CT: 15
CT: 9f-
WJ
"1"~
6-10
Usual meanings associated with flip-flops le.g., R = reset to 0, S = set to 1).
Data input to a storage element equivalent to:
m
Shift right lIeft} inputs, m = 1, 2, 3, etc. If m = 1, it. is usually not shown.
m
Counting up Idown} inputs, m
=
1, 2, 3, etc. If m
=
1, it is usually not shown
Binary grouping. m is highest power of 2.
The contents"setting input, when active, causes the content of a register to take on the indicated
value.
The content output is active if the content of the register is as indicated.
Input line grouping ... indicates two or more terminals used to implement a single logic input.
e.g., The paired expander inputs of SN7450. ;=:jJE
Fixed-state output always stands at its internal 1 state. For example, see SN74185.
In an array of elements, if the same general qualifying symbol and the same qualifying symbols
associated with inputs and outputs would appear inside each of the elements of the array,
then these qualifying symbols are usually shown only in the first element. This is done to reduce
clutter and to save time in recognition. Similarly, large identical elements that are subdivided
into smaller elements may each be represented by an unsubdivided outline. The SN54HC242
or SN54LS440 symbol illustrates this principle.
3.3
Symbols Inside the Outline
Table III shows some symbols used inside the outline. Note particularly that open-collector
(open-drain), open-emitter (open-source), and 3-state outputs have distinctive symbols. An
EN input affects all the external outputs of the element in which it is placed, plus the external
outputs of any elements shown to be influenced by that element. It has no effect on inputs.
When an enable input affects only certain outputs, affects outputs located outside the indicated
influence of the element in which the enable input is placed, and/or affects one or more inputs,
a form of dependency notation will indicate this (see 4.10). The effects of the EN input on
the various types of outputs are shown.
It is particularly important to note that a D input is always the data input of a storage element.
At its internal 1 state, the D input sets the storage element to its 1 state, and at its internal
o state it resets the storage element to its 0 state.
The binary grouping symbol will be explained more fully in Section 8. Binary-weighted inputs
are arranged in order and the binary weights of the least-significant and the most-significant
lines are indicated by numbers. In this document weights of input and output lines will be
represented by powers of two usually only when the binary grouping symbol is used, otherwise
decimal numbers will be used. The grouped inputs generate an internal number on which a
mathematical function can be performed or that can be an identifying number for dependency
notation (Figure 28). A frequent use is in addresses for memories.
en
.c
'0
E
>
o
w
w
W
Reversed in direction, the binary grouping symbol can be used with outputs. The concept is analogous to that for the inputs and the weighted outputs will indicate the internal n u m b e r .
assumed to be developed within the circuit.
•
Other symbols are used inside the outlines in accordance with the IEC/IEEE standards but are
not shown here. Generally these are associated with arithmetic operations and are selfexplanatory.
\A!~,?n n0~C?,!?nt:f.?rt:li'74?'ti infnrrn~tinn ic: c:hn\l'tln inc:irl,:. ~n nlltlinj:!] it i~ 11~1I::IlIy 'Anr.:ln!=:p.ti in ~~IHUP.
brackets [like thesel. The square brackets are omitted when associated with a nonlogic input,
which is indicated by an X superimposed on the connection line outside the symbol.
4.0
DEPENDENCY NOTATION
4.1
General Explanation
Dependency notation is the powerful tool that sets the lEG symbols apart from previous systems
and makes compact, meaningful, symbols possible. It provides the means of denoting the
relationship between inputs, outputs, or inputs and outputs without actually showing all the
6-11
elements and interconnections involved. The information provided by dependency notation
supplements that provided by the qualifying symbols for an element's function.
In the convention for the dependency notation, use will be made of the terms "affecting" and
"affected." In cases where it is not evident which inputs must be considered as being the
affecting or the affected ones (e.g., if they stand in an AND relationship), the choice may be
made in any convenient way.
So far, eleven types of dependency have been defined and all of these are used in various TI
data books. X dependency is used mainly with CMOS circuits. They are listed below in the
order in which they are presented and ~re summarized in Table IV· following 4.12.
Section Dependency TYPe or Other Subject
4.2
G,AND
General Rules for Dependency Notation
4.3
4.4
V,OR
N, Negate (Exclusive-OR)
4.5
4.6
Z, Interconnection
4.7
X, Transmission
4.8
C, Control
4.9
S, Set and R, Reset
4.10 EN, Enable
4.11
M, Mode
4.12 A, Address
-
m
m
m
en
'<
3
C"
o
0'
II
4.2
G (AND) Dependency
A common relationship between two signals is to have them ANDed together. This has
traditionally been shown by explicitly drawing an AND gate with the signals connected to the
inputs of the gate. The 1972 IEC publication and the 1973 IEEE/ANSI standard showed several
ways to show this AND relationship using dependency notation. While ten other forms of
dependency have since been defined, the ways to invoke AND dependency are now reduced
to one ..
In Figure 4 input b is ANDed with input a and the complement of b is ANDed with c. The letter
G has been chosen to indicate AND relationships and is placed at input b, inside the symbol.
A number considered appropriate by the symbol designer (1 has been used here) is placed after
the letter G and also at each affected input. Note the bar over the 1 at input c.
a
b
c
={ -1
Gl
,.
~=$I--
c~
Figure 4. G Dependency Between Inputs
In Figure 5, output b affects input a with an AND relationship. The lower example shows that
it is the internal logic state of b, unaffected by the negation sign, that is ANDed. Figure 6 shows
input a to be ANDed with a dynamic input b.
6-12
~---.L
aLI
__~T-b
_' Bj&f_--_--_,1-r- b
~
_
a
rD-{_--_r b
~ ~
b aE!--r b
alGI
b aru--}-rB-I
--t---r---=
-
'=
__
Figure 5. G Dependency Between Outputs and Inputs
Figure 6. G Dependency with a Dynamic Input
The rules for G dependency can be su":,marized thus:
When a Gm input or output (m is a number) stands at its internal 1 state, all inputs and
outputs affected by Gm stand at their normally defined internal logic states. When the
Gm input or output stands at its 0 state, all inputs and outputs affected by Gm stand
at their internal 0 states.
II)
4.3
Conventions for the Application of Dependency Notation in
"0
.Q
,~eneral
E
The rules for applying dependency relationships in general >lIow the same pattern as was
illustrated for G dependency.
w
Application of dependency notation is accomplished by:
1) labeling the input (or output) affecting otherinputf',r outputs with the letter symbol
2)
en>
w
w
indicating the relationship involved (e.g., G for AND) /(lilowed by an identifying number,
appropriately chosen, and
labeling each input or output affected by that affecting input (or output) with that
same number.
II
If it is the complement of the internal logic state of the affec',,;1g input or output that does
::::',::::::- !~::: ::!::::-;~;!'i;~ii ;-,i.,;;-ii~oi-~ t .. ~ ~:-I~ o;~'ca... \.t;;U ;11"'Ui.~ UJ UUlPU-(:S
(Figure 4).
thp ~ffp,.."tin~. "!:h~~ ~ ~~~ ~~ ~!~~:~
If two affecting inputs or outputs have the same letter and the same identifying number, they
stand in an OR relationship to each other (Figure 7).
b
&
a~1
c
Figure 7. ORed Affecting Inputs
6-13
If the affected input or output requires a label to denote its function (e.g., "0"), this label will
be prefixed by the identifying number of the affecting input (Figure 15).
If an input or output is affected by more than one affecting input, the identifying numbers of
each of the affecting inputs will appear in the label of the affected one, separated by commas.
The normal reading order of these numbers is the same as the sequence of the affecting
relationships (Figure 15).
If the labels denoting the functions of affected inputs or outputs must be numbers (e.g., outputs
of a coder), the identifying numbers to be associated with both affecting inputs and affected
inputs or outputs will be replaced by another character selected to avoid ambiguity, e.g., Greek
letters (Figure 8).
a
b
c
_=i
0
Go
;;;
a
b
c
~1Gl
--
T
Figure 8. Substitution for Numbers
4.4
V (OR) Dependency
The symbol denoting OR dependency is the letter V (Figure 9).
-mm
m
tJ)
<
3
C"
o
=t: = 3i}: - ~:
Cii
Figure 9. V (OR) Dependency
When a Vm input or output stands at its internal 1 state, all inputs and outputs affected by
Vm stand at their internal 1 states. When the Vm input or output stands at its internal 0 state,
all inputs and outputs affected by Vm stand at their normally defined internal logic states.
4.5
N (Negate) (Exclusive-OR) Dependency
The symbol denoting negate dependency is the letter N (Figure 10). Each input or output affected
by an Nm input or output stands in an Exclusive-OR relationship with the Nm input or output.
6-14
If a ~ 0, then c ~ b
If a ~ 1, then c ~ Ii
Figure 10. N (Negate) (Exclusive-OR) Dependency
When an Nm input or output stands at its internal 1 state, the internal logic state of each input
and each output affected by Nm is the complement of what it would otherwise be. When an
Nm input or output stands at its internal 0 state, all inputs and outputs affected by Nm stand
at their normally defined internal logic states.
4.6
Z (Interconnection) Dependency
The symbol denoting interconnection dependency is the letter Z.
Interconnection dependency is used to indicate the existence of internal logic connections
between inputs, outputs, internal inputs, and/or internal outputs.
The internal logic state of an input or output affected by a Zm input or output will be the same
as the internal logic state of the Zm input or output, unless modified by additional dependency
notation (Figure 11).
at~]-b
E=z}--a
-
E~~a
-
a~lt-c
bIll
-
'W'
W·
where
-B-- =-{>-
tn
'0
.c
E
>U)
W
W
W
-
where
-cJ-=-<}-
II
i[hft--a
LcJj
:~'
Figure 11. Z (Interconnection) Dependency
6-15
4.7
X (Transmission) Dependency
The symbol denoting transmission dependency is the letter X.
Transmission dependency is used to indicate controlled bidirectional connections between
affected input/output ports (Figure 12).
t-+-+-- b
8-
XI
I/lt-+-+-It--+-+--d
If a = 1. there is a bidirectional
connection between band c.
If a
= 0, there is a bidirectional
connection between c and d.
Figure 12. X (Transmission) Dependency
When an Xm input or output stands at its internal 1 state, all input-output ports affected by
this Xm input or output are bidirectionallY connected together and stand at the same internal
logic state or analog signal level. When an Xm input or output stands at its internal 0 state,
the connection associated with this set of dependency notation does not exist.
~
a-1I I-b
t.n
-<
I
m
3
0"
-
o
p
Figure 13. CMOS Transmission Gate Symbol and Schematic
( I)
#
#
MUXDMUX
O} 0
I
X3
011/2/3
Figure ,14: Analog Data Selector (Multiplexer/Demultiplexer)
Although the transmission paths represented by X dependency are inherently bidirectional,
use is not always made of this property. This is analogous to a piece of wire, which may be
constrained to carry current in only one direction. If this is the case in a particular application,
then the directional arrows shown in Figures 12, .13, and 14 are omitted.
6-16
4.8
C (Control) Dependency
The symbol denoting control dependency is the letter C.
Control inputs are usually used to enable or disable the data (0, J, K, R, or S) inputs of storage
elements. They may take on their internal 1 states (be active) either statically or dynamically.
In the latter case the dynamic input symbol is used as shown in the third example of Figure 15.
a-fc7
b--r O
a~l
b
C2
1.~
c
/
'=
-
af~
b
lC2
20
-
a~&
sb
&
=
c
c
.
R
-
Note AND relationship of a and b
~
c
a
b
-
b
&
& S
a~-
Gl
1.20
C2
af
c
& R
II)
b
11.2D
i'0
a~"1
_
&
& S
c
Gl
b
d
C2
d
c
&
'0
..0
E
>(J)
R
-
W
W
W
Input c selects which of a or b is stored when d goes low.
-
Figure 15. C (Control) Dependency
Whe':l a Cm input or output stands at its internal 1 state, the inputs affected by Cm have their
normally defined effect on the function of the element, i.e., these inputs are enabled. When
a Cm input or output stands at its internal 0 state, the inputs affected by Cm are disabled and
have no effect on the function of the element.
II
6-17
4.9
The symbol denoting set dependency is
the letter S. The symbol denoting reset
dependency is the letter R.
Set and reset dependencies are used if it
is necessary to specify the effect of the
combination R =S = 1 on a bistable
element. Case 1 in Figure 16 does not use
S or R dependency.
.
When an Sm input is at its internal 1 state,
outputs affected by the Sm input will
react, regardless of the state of an R input,
as they normally would react to the
combination S = 1, R =O. See cases 2, 4,
and 5 in Figure 16.
iii
m
m
CASE 1
S (Set) and R (Reset) Dependencies
When an Am input is at its internal 1 state,
outputs affected by the Rm input will
react, regardless of the state of an S input,
as they normally would react to the
combination S =0, R = 1. See cases 3, 4,
and 5 in Figure 16.
s~:
S
0
0
R
0
1
1
0
Q Q
nc nc
1
0
1
0
1
?
?
s-Fl-:
R-ti-O
s-rl-o
S
0
0
R
0
Q
Q
nc
nc
1
0
1
1
1
0
1
1
1
0
0
S
0
0
R
0
Q Q
nc nc
1
0
1
1
1
0
1
0
1
a
1
R-U-0
CASE 2
CASE 3
R-LJ-O
CASE 4
s-Fl-:
3
g-
en
When an Sm or Rm input is at its internal
o state, it has no effect.
Note that the noncomplementary output
patterns in cases 4 and 5 are only pseudo
stable. The simultaneous return of the
inputs to S = R = 0 produces an
unforeseeable stable and complementary
output pattern.
S
0
0
R~O
1
1
R
Q
Q
0
nc
nc
1
a
1
a
1
1
1
R
Q
Q
a
nc
a
nc
1
1
0
a
1
CASE 5
(I)
-<
1
s-F1-:0
R-Uo = external
nc
0 state
= no change
S
0
a
1
1
1
a
1
a a
1 = external 1 state
?
= unspecified
Figure 16. S (Set) and R (Reset) Dependencies
4.10 EN (Enable) Dependency
The symbol denoting enable dependency is the combination of letters EN.
An ENm input has the same effect on outputs as an EN input, see 3.3, but it affects only those
outputs labeled with the identifying number m. It also affects those inputs labeled with the
identifying number m. By contrast, an EN input affects all outputs and no inputs. The effect
of an ENm input on an affected input is identical to that of a Cm input (Figure 17).
6-18
When an ENm input stands at its internal 1 state, the inputs affected by ENm have their normally
defined effect on the function of the element and the outputs affected by this input stand at
their normally defined internal logic states, i.e., these inputs and outputs are enabled.
a_--~
d
If a = 0, b is disabled and d = c
If a = " c is disabled and d = b
Figure 17. EN (Enable) Dependency
When an ENm input stands at its internal 0 state, the inputs affected by ENm are disabled
and have no effect on the function of the element, and the outputs affected by ENm are also
disabled. Open-collector outputs are turned off, three-state outputs stand at their normally
defined internal logic states by externally exhibit high impedance, and all other outputs (e.g.,
totem-pole outputs) stand at their internal 0 states.
4.11 M (MODE) Dependency
en
The symbol denoting mode dependency is the letter M.
'0
Mode dependency is used to indicate that the effects of particular inputs and outputs of an
element depend on the mode in which the element is operating.
If an input or output has the same effect in different modes of operation, the identifying numbers
of the relevant affecting Mm inputs will appear in the label of that affected input or output
between parentheses and separated by solidi (Figure 22).
.Q
E
>
o
w
w
w
4.11.1 M Dependency Affecting Inputs
M dependency affects inputs the same as C dependency. When an Mm input or Mm output
stands at its internal 1 state, the inputs affected by this Mm input or Mm output have their
normally defined effect on the function of the element, i.e., the inputs are enabled.
When an Mm input or Mm output stands at its internal 0 state, the inputs affected by this
It.,., . . . .
1\..11_ : _ _ .....
I.U'6
__ "''' _ _ ..... _ ........... _ •• _ _ _ _ z.z, __ .... __
IV.",
1 1Il,0l v .... II ........
VII
VI
v"" ... ..,"" . .
,.'"'v . .
........ _
z. ...__ ... : __ _ L
... L _ _ 1 _ _ _ _ _ ...
........
lUI ,\,,0 ",.VI 1 VI
................. 111..."
....
\A'L _ _ _ _ _ .1..1. _ _ ... _-1
" " ....... ,
"-III
UII1Wii ....... u U
input has several sets of labels separated by solidi (e.g., C4/2-/3+), any set in which the
identifying number of the Mm input or Mm output appears has no effect and islo be ignored.
This represents disabling of some of the functions of a multifunction input.
6-19
The circuit in Figure 18 has two inputs, band c, that control which one of four modes (0, 1, 2,
or 3) will exist at any time. Inputs d, e, and fare D inputs subject to dynamic control (clocking)
by the a input. The numbers 1 and 2 are in the series chosen to indicate the modes so inputs
e and f are only enabled in mode 1 (for parallel loading) and input d is only enabled in mode 2
(for serial loading). Note that input a has three functions. It is the clock for entering data.
In mode 2, it causes right shifting of data, which means a shift away from the control block.
In mode 3, it causes the contents of the register to be incremented by one count.
Note that all operations are synchronous.
In MODE 0 (b = 0, c = 0), the outputs
remain at their existing states as none
of the inputs has an effect.
In MODE 1 (b = 1, c = 0), parallel loading
takes place thru inputs e and f.
In MODE 2 (b = 0, c = 1), shifting down
and serial loading thru input d take place.
In MODE 3 (b = c = 1), counting up by
increment of 1 per clock pulse takes place.
Figure 18. M (Mode) Dependency Affecting Inputs
4.11.2 M Dependency Affecting Outputs
m
m
m
en
-<
3
o
C"
When an Mm input or Mm output stands at its internal 1 state, the affected outputs stand
at their normally defined internal logic states, i.e., the outputs are enabled.
°
When an Mm input or Mm output stands at its internal state, at each affected output any
set of labels containing the identifying number of that Mm input or Mm output has no effect
and is to be ignored. When an output has several different sets of labels separated by solidi
(e.g., 2,4/3,5), only those sets in which the identifying number of this Mm input or Mm
output appears are to be ignored.
Ui
Figure 19 shows a symbol for a device
whose output can behave as either a
3-state output or an open-collector
output depending on the signal applied
to input a. Mode 1 exists when input
a stands at its internal 1 state and, in
that case, the three-state symbol
applies and the open-element symbol
has no effect. When a = 0, mode 1
does not exist so the three-state symbol
has no effect and the open-element
symbol applies.
6-20
t>
'a
M1
b
EN
1'V/1Q
d
Figure 19. Type of Output Determined by Mode
In Figure 20, if input a stands at its internal
1 state establishing mode 1 , output b will
stand at its internal 1 state only when the
content of the register equals 9. Since
output b is located in the common-control
block with no defined function outside of
mode 1, the state of this output outside
of mode 1 is not defined by the symbol.
In Figure 21, if input a stands at its
internal 1 state establishing mode 1,
output b will stand at its internal 1 state
only when the content of the register
equals 15. If input a stands at its internal
o state, output b will stand at its internal
1 state only when the content of the
r.egister equals O.
a-1Ml
,
lCT=9
~b
I
I
I
I
I
?
~
Figure 20. An Output of the Common-Control Block
a
l
Ml
,,
,
(
I~T=15r-b
lCT=O
,I
I
S
Figure 21. Determining an Output's Function
In Figure 22 inputs a and b are binary
weighted to generate the numbers 0, 1,
2, or 3. This determines which one of the
four modes exists.
U)
Figure 22. Dependent Relationships
At output e the label set causing negation
Affected by Mode
(if c = 1) is effective only in modes 2 and
3. In modes 0 and 1 this output stands
>at its normally defined state as if it had
no labels. At output f the label set has
W
effect when the mode is not 0 so output
W
e is negated (if c = 1) in modes 1, 2, and
3. In mode 0 the label set has no effect so the output stands at its normally defined state. •
In this example 0,4 is equivalent to (1/2/3)4. At output 9 there are two label sets. The first
set, causing negation (if c = 1), is effective only in mode 2. The second set, subjecting 9 to
•
AND dependency on d, has effect only in mode 3.
"0
E
en
!:!:!
Note that in mode 0 none of the dependency relationships has any effect on the outputs, so
e, f, and 9 will all stand at the same state.
The symbol denoting address dependency is the letter A.
Address dependency provides a clear representation of those elements, particularly memories,
that use address controi inputs to select specified sections of a multildimen!!ional array. Such
a section of a memory array is usually called a word. The purpose of address dependency is
to allow a symbolic presentation of the entire array. An input of the array shown at a particular
6-21
element of this general section is common to the corresponding elements of all selected sections
of the array. An output of the array shown at a particular element of this general section is
the result of the OR function of the outputs of the corresponding elements of selected sections.
Inputs that are not affected by any affecting address input have their normally defined effect
on all sections of the array, whereas inputs affected by an address input have their normally
defined effect only on the section selected by that address input.
An affecting address input is labeled with th~ letter A followed by an identifying number that
corresponds with the address of the particular section of the array selected by this input. Within
the general section presented by the symbol, inputs and outputs affected by an Am input are
labeled with the letter A, which stands for the identifying numbers, i.e., the addresses, of the
particular sections.
a
b
a
AI
A2
d
e
9
c
ENI
EN2
EN3
d
CA
b
c- A3
-
CA
f
h
e
9
-mm
m
t/)
'<
3
0'"
o
0'
II
h
Figure 23. A (Address) Dependency
Figure 23 shows a 3-word by 2-bit memory having a separate address line for each word and
uses EN dependency to explain the operation. To select word 1, input a is taken to its 1 state,
which establishes mode 1 . Data can now be clocked into the inputs marked" 1,40." Unless
words 2 and 3 are also selected, data cannot be clocked in at the inputs marked "2,40" and
"3,40." The outputs will be the OR functions of the selected outputs, i.e., only those enabled
by the active EN functions.
The identifying numbers of affecting address inputs correspond with the addresses of the
sections selected by these inputs. They need not necessarily differ from those of other affecting
dependency-inputs (e.g., G, V, N, ... ), because in the general section presented by the symbol
they are replaced by the letter A.
If there are several sets of affecting Am inputs for the purpose of independent and possibly
simultaneous access to sections of the array, then the letter A is modified to 1A,
2A, .... Since they have access to the same sections of the array, these sets of A inputs
may have the same identifying numbers. The symbols for 'HC170 or SN74LS170 make use
of this.
Figure 24 is another illustration of the concept.
6-22
RAM 16 X 4
EN
:}A;\
Cl
Figure 24. Array (If 16 Secti(lns (If F(lur Transparent Latches with 3-State Outputs
Comprising a 16-Word x 4-Bit Random-Access Memory
Table IV. Summary of Dependency Notation
TYPE OF
DEPENDENCY
Address
Control
LETTER
SYMBOL*
A
C
AFFECTING INPUT
AT ITS l-STATE
Permits action (address selected)
Permits action
AFFECTING INPUT
AT ITS O-STATE
Prevents action (address not selected)
Prevents action
Prevents action of inputs
outputs off
\J outputs at external high impedance,
no change in internal logic state
Other outputs at internal 0 state
Imposes 0 state
Prevents action (mode not selected)
No effect
o
Enable
EN
Permits action
AND
Mode
Negate (Ex-OR)
G
M
N
Permits action
Permits action (mode selected)
Complements state
Affected output reacts as
it would to S = 0, R = 1
Affected output reacts as
it would to S = 1, R = 0
Imposes 1 state
Bidirectional connection exists
Imposes 1 state
Reset
R
Set
S
OR
Transmission
Interconnection
X
V
Z
II)
'0
.Q
e>
No effect
CJ)
No effect
W
W
W
-
•
Permits action
Bidirectional connection does not exist
Imposes 0 state
• These letter symbols appear at the AFFECTING input lor output) and are followed by a number. Each input lor outputl AFFECTED
by that input is labeled with that same number. When the labels EN, R, and S appear at inputs without the following numbers,
the descriptions above do not apply. The action of these inputs is described under "Symbols Inside the Outline," see 3.3.
5.0
BISTABLE ELEMENTS
Thp. rlyn~mir. in!"lIt ~~/mhnl. thg :",n~T~0~'='~ ~':.~!~I-.!,!: ~~/~~':'!. ~~~ ~~~~~~e~~',' ~!::~::'!:::::!":
;:=-=",::==
the tools to differentiate four main types of bistable elements and make synchronous and
asynchronous inputs easily recognizable (Figure 25). The first column shows the essential
distinguishing features; the other columns show examples.
Transparent latches have a level-operated control input. The D input is active as long as the
C input is at its internal 1 state. The outputs respond immediately. Edge-triggered elements
accept data from D, J, K, R, or S inputs on the active transition of C. Pulse-triggered elements
6-23
require the setup of data before the start of the control pulse; the C input is considered static
since the data must be maintained as long as C is at its 1 state. The output is postponed until
C returns to its 0 state. The data-lock-out element is similar to the pulse-triggered version except
that the C input is considered dynamic in that shortly after C goes through its active transition,
the data inputs are disabled and data does not have to be held. However, the output is still
postponed until the C input returns to its initial external level.
Notice that synchronous inputs can be readily recognized by their dependency labels (1 D, 1J,
1 K, 15, 1 R) compared to the asynchronous inputs (5, R), which are not dependent on the C
inputs.
r- --,
I
I
-1
r-
Cm
,
I
L __ .J
TRANSPARENT
LATCHES
fl
o
Cl
C2
2D
1/2 SN7475
r---'
-t
~
cm
J
Cl
lK
R
I ___ .JI
L
EDGE-TRIGGERED
-mm
1/2 SN7474
r--.,
I
I
Cl
lK
R
Cm
en
IL ___ JI
-<
3
PULSE-TRIGGERED
o
-+cm~~
1/2 SN74LS107
1J
l -'r-
m
fi
SN74L71
1/2 SN74107
SN74110
1/2 SN74111
r - --,
0-
Cii
I
I
L ___ .J
DATA-LOCK·OUT
Figure 25. Four Types of Bistable Circuits
6.0
CODERS
The general symbol for a coder or code
converter is shown in Figure 26. X and Y
may be replaced by appropriate
indications of the code used to represent
the information at the inputs and at the
outputs, respectively.
6-24
Figure 26. Coder General Symbol
Indication of code conversion is based on the following rule:
Depending on the input code, the internal logic states of the inputs determine an internal
value. This value is reproduced by the internal logic states of the outputs, depending on
the output code.
The indication of the relationships between the internal logic states of the inputs and the internal
value is accomplished by:
1)
2)
labeling the inputs with numbers. In this case the internal value equals the sum of
the weights associated with those inputs that stand at their internal 1-state, or by
replacing X by an appropriate indication of the input code and labeling the inputs with
characters that refer to this code.
The relationships between the internal value and the internal logic states of the outputs
. are indicated by:
1)
2)
labeling each output with a list of numbers representing those internal values that
lead to the internal 1-state of that output. These numbers shall be separated by solidi
as in Figure 27. This labeling may also be applied when Y is replaced by a letter
denoting a type of dependency (see Section 7). If a continuous range of internal values
produces the internal 1 state of an output, this can be indicated by two numbers
that are inclusively the beginning and the end of the range, with these two numbers
separated by three dots (e.g., 4 ... 9 = 4/5/6/7/8/9) or by
replacing Y by an appropriate indiction of the output code and labeling the outputs
with characters that refer to this code as in Figure 28.
Alternatively, the general symbol may be used together with an appropriate reference to a table
in which the relationship between the inputs and outputs is indicated. This is a recommended
way to symbolize a PROM after it has been programmed.
TRUTH TABLE
INPUTS
XIV
a
b
c
1
2
4
1/4
2J3
3/4
d
e
9
c
b
0
0
0
0
1
1
0
0
1
1
0
0
I;
•0
1
0
1
0
1
•
0
0
0
0
0
0
OUTPUTS
f
0
0
0
1
1
0
•0
0
1
1
0
0
d
0
1
0
0
1
0
II)
'0
..Q
E
>
en
W
W
!:!:!
•
~I~~~~I
Figure 27. An X/V Code Converter
6-25
TRUTH TABLE
INPUTS
XlGeT
d
e
a
b
c
Z
4
f
9
h
c
b
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
OUTPUTS
•0
1
0
1
0
1
0
1
i
I
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
h
B
f
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
•
d
0
0
1
0
0
0
0
0
0
1
0
0
0
Q
0
0
Figure 28. An X/Octal Code Converter
7.0
USE OF A CODER TO PRODUCE AFFECTING INPUTS
It often occurs that a set of affecting
inputs for dependency notation is
produced by decoding the signals on
certain inputs to an element. In such a
case use can be made of the symbol for
a coder as an embedded symbol
(Figure 29).
-mm
If all affecting inputs produced by a coder
are of the same type as their identifying
numbers shown at the outputs of the
coder, V (in the qualifying symbol XIV)
may be replaced by the letter denoting the
type of dependency. The indications of
the affecting inputs should then be
omitted (Figure 30).
m
o
<
3
cr
o
tii
II
6-26
8.0
X/V
o
GI
1 GZ
2
V4
V3 N5
C3
Figure 29. Producing Various Types of
Dependencies
=[J
IM
I
2
--
0
1
2
,I
D
/V
=
I
2
--
0 MO
1
MI
2
M2
,
I
Figure 30. Producing One Type
of Dependency
USE OF BINARY GROUPING TO PRODUCE AFFECTING INPUTS
If all affecting inputs produced by a coder are of the same type and have consecutive identifying
numbers not necessarily corresponding with the numbers that would have been shown"at the
outputs of the coder, use can be made of the binary grouping symbol. k external lines effectively
generate 2k internal inputs. The bracket is followed by the letter denoting the type of
dependency followed by m 11m2. The m 1 is to be replaced by the smallest identifying number
and the m2 by the largest one, as shown in Figure 31.
x/v
AO
Al
2 A2
J AJ
4 A4
A5
A6
A7
0
I
X/V
G5
G6
G7
G8
Figure 31. Use of the Binary Grouping Symbol
9.0
SEQUENCE OF INPUT LABELS
If an input having a single functional effect is affected by other inputs, the qualifying symbol
(if there is any) for that functional effect is preceded by the labels corresponding to the affecting
inputs. The left-to-right order of these preceding labels is the order in which the effects or
modifications must be applied. The affected input has no functional effect on the element if
the logic state of anyone of the affecting inputs, considered separately, would cause the affected
input to have no effect, regardless of the logic states of other affecting inputs.
If an input has several different functional effects or has several different sets of affecting inputs,
depending on the mode of action, the input may be shown as often as required. However,
there are cases in which this method of presentation is not advantageous. In those cases the
input may be shown once with the different sets of labels separated by solidi (Figure 32). No
meaning is attached to the order of these sets of labels. If one of the functional effects of
an input is that of an unlabeled input to the element, a solidus will precede the first set of labels
shown.
If all inputs of a combinational element are
disabled (caused to have no effect on the
function of the element). the internal logic
states of the outputs of the element are
not specified by the symbol. If all inputs
_z- ____ .. ___
VI
U
-'-~_I
_1 _ _ _
•
'"
•••••
.;;n;;;"tU"'IILIQI ult:Olll'tiIIL a l e Ulo:)aUltllU,
Lllt:\ii
content of this element is not changed and
the outputs remain at their existing
internal logic states.
Labels may be factored using algebraic
techniques (Figure 33).
8=[1--b
G2
c
1~/~.~~
8
h
=f ----
U)
'0
.c
E
>w
w
w
fn
•
G2
')/rt
[~--Figure 32. Input Labels
6-27
Figure 33. Factoring Input Labels
10.0
SEQUENCE OF OUTPUT LABELS
If an output has a number of different labels, regardless of whether they are identifying numbers
of affecting inputs or outputs or not, these labels are shown in the following order:
1)
2)
3)
m
m
m
en
<
3
0"
o
;-
II
If the postponed output symbol has to be shown, this comes first, if necessary
preceded by the indications of the inputs to which it must be applied
Followed by the labels indicating modifications of the internal logic state of the output,
such that the left-to-right order of these labels corresponds with the order in which
their effects must be applied
Followed by the label indicating the effect of the output on inputs and other outputs
of the element.
Symbols for open-circuit or 3-state
outputs, where applicable, are placed just
inside the outside boundary of the symbol
adjacent to the output line (Figure 34)~
If an output needs several different sets
Figure 34. Placement of 3-State Symbols
of labels that represent alternative
functions (e.g., depending on the mode
of action), these sets may be shown on
different output lines that must be
connected outside the outline. However, there are cases in which this method of presentation
is not advantageous. In those cases the output may be shown once with the different sets
of labels separated by solidi (Figure 35).
Two adjacent identifying numbers of affecting inputs in a set of labels that are not already
separated by a nonnumeric character should be separated by a comma.
If a set of labels of an output not
containing a solidus contains the
identifying number of an affecting Mm
input standing at its internal 0 state, this
set of labels has no effect on that output.
Labels may be factored using algebraic
techniques (Figure 36).
at~-_~~~=~~~~:tb = ai~~-~~~:~tb
Figure 35. Output Labels
Figure 36. Factoring Output Labels
If you have questions on this Explanation
of Logic Symbols, please contact:
Texas Instruments Incorporated
F.A. Mann, MS 49
P.O. Box 655012
Dallas, Texas 75265
Telephone (214) 995-2659
IEEE Standards may be purchased from:
Institute of Electrical and Electronics Engineers, Inc.
I EEE Standards Office
345 East 47th Street
New York, N.Y. 10017
International Electrotechnical Commission (IEC)
publications may be purchased from:
American National Standards Institute, Inc.
1430 Broadway
New York, N.Y. 10018
ri)
(5
.c
E
en>
w
w
w
-
•
6-29
;;;
m
m
en
'<
3
o
0"
0'
6-30
n.o~i,..n
_ _ _ _ ;::,_ _
(",..
.. ~ ... :...,.
..... -_ _ I..... .eo.:,..,..
_ . _ _ .......
loWI
7-1
c
(1)
UI
cC'
::J
n
o
::J
UI
c.:
...I»
(1)
r+
0'
::J
UI
7-2
DESIGN CONSIDERATIONS
DESIGN CONSIDERATIONS
Logic Evaluation
To begin your standard celilC design, you should prepare a functional description, a timing diagram, and a logic
design. A complete definition of the circuit performance must be specified. Waveform diagrams or test vectors
may be a TO GATES
fI)
C
o
"+0
-=
ca
~
GND
Figure 5. Schematic of Input Protection
Q)
"C
"iii
c
o
(.)
c
OJ
"iii
..
Q)
C
II!II
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
7-15
DESIGN CONSIDERATIONS
Vee
FROM
GATE
0..---
OUTPUT
PAD
-= GND
Figure 6. Schematic of Output Protection
cCD
fI)
cEo
:J
(')
o
:J
fI)
a:CD
...m...ci"
:J
fI)
•
7-16
TEXAS ~
IN STRUM
ENTS
POST OFFICE BOX 655012 • DALI.AS. TEXAS 76265
Mechanical Data
8-1
8-2
MECHANICAL DATA
Electrical characteristics presented in this data book, unless otherwise noted, apply to standard cells prior
to interconnect routing and packaging. Characteristics and effects of routing, cell layout, and interconnection
of a completed ASIC design are covered in the. post-layout simulation software. The capacitive loading
effects of the package bond wire(s) and terminals(s) are assumed to be a portion of the 15 pF or 50 pF
switching-characteristics load shown for the output and 1/0 cells. Typically, the packaging bond-wire and
terminal capacitance values range from 1 to 2 pF. Consult Tl's design-center personnel for further assistance
in choosing and specifying ASIC packaging options.
package selection
Outline drawings presented in this section are for both conventional through-hole and surface-mount
packages. The following classes of packages are covered.
Dual-in-line (DIP), plastic and ceramic
Pin-grid-array (PGA), ceramic
Small-outline (SO), plastic
Ceramic leadless chip carriers (LCC)
Plastic leaded chip carriers (PLCC)
Ceramic quad flatpacks
These packages are recommended as a representative selection which satisfies a wide range of ASIC
applications. TI will review and consider supplying package requirements other than those shown.
ordering instructions
Implementation of semiconductor solutions using SystemCell'" components normally results in an applicationspecific integrated circuit. Total specifications, including packaging and ordering instructions, are developed
as a part of this Design Specification described in. Section 1. Contact your TI representative for further
information on getting started with an ASIC design.
...
CIS
CIS
C
ca
(,)
'2
CIS
.c
(,)
CD
:E
II
TEXAS ~
INSTRUMENTS
POST .OFFICE BOX 655012 • OALLAS, TEXAS 75265
8-3
8-4
MECHANICAL DATA
o
plastic "small outline" packages
Each of these "small outline" packages consists of a circuit mounted on a lead frame and encapsulated
within a plastic compound. The compound will withstand soldering temperature with no deformation, and
circuit performance characteristics will remain stable when operated in high-humidity conditions. Leads
require no additional cleaning or processing when used in soldered assembly.
a·PIN D PACKAGE
f
6,20 (0.2441
3,81 10.150)
4
-*--1jt;:.:;;li=j:r::nI
F-L= r""P~ACESNOM
0,50 (0.020)
1,75 (0.0691
1.35
0.2510.010)
,4
0.20~J-
0,102 (0.0041
0,79 10.031)
0,2810.011)
-
j
l
"hi
x 45"........
5.21 10.205)
4,60 (0'181)J
F
0.45710.0181
0.35610.0141
\~~
:1\.-..,. NOM0
4 PLACES
0,22910.0090)
0,190 10.0075)
Lr
4° ± 4°
1,12 (0.044)
0,51 10.020)
PIN SPACING
1.27 (0.050)
(Sse Note A)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES:
A. Body dimensions do not include mold flash or protrusion.
B. Mold flash or protrusion shall not exceed 0,15 10.0061.
Leads are within 0,25 (0.010) radius of true position at maximum material dimension.
D. Lead tips to be planar within ±O,051 10:0021 exclusive of solder.
c.
...co
CO
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16
.~
s::
CO
.s::
(J
Q)
:!:
II
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
8-5
MECHANICAL DATA
o plastic "small outline" packages
Each of these "small outline" packages consists of a circuit mounted on a lead frame and encapsulated
within a plastic compound. The compound will withstand soldering temperature with no deformation, and
circuit performance characteristics will remain stable when operated in high-humidity conditions. Leads
require no additional cleaning or processing when used in soldered assembly.
16-PIN D PACKAGE
r
10'00(0'394)~
9.80 (0.388)
rot-----i1cn- _ _
_ _
r-
6.20 (0.2441
I
5.80 (0.2281
4.00 (0.1571
3.8iTo:15oi
L-~t;::;:;:;:;::;::;:::::;:;=;::;:;:;Y
1.75 (0.0691 '
1,35 (0.053)
j
'7"NOM
4 PLACES
jl~
0,356 (0.014)
PIN SPACING
1.27 (0.0501
(See Note A)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A.
B.
C.
D.
Body dimensions do not include mold flash or protrusion.
Mold flash or protrusion shall not exceed 0.15 (0.006),
Leads are within 0,25 (O.010) radius of true position at maximum material dimension.
Lead tips to be planar within ±0.051 10.002) exclusive of solder.
II
8-6
TEXAS . "
INSTRUMENlS
pos-r: OFFICE BOX
655012 • DALLAS. TEXAS 76265
MECHANICAL DATA
OW plastic "small outline" packages
Each of these "small outline" packages consists of a circuit mounted on a lead frame and encapsulated
within a plastic compound. The compound will withstand soldering temperature with no deformation, and
circuit performance characteristics will remain stable when operated in high-humidity conditions. leads
require no additional cleaning or processing when used in soldered assembly.
20-PlN OW PACKAGE
r
r=--:::~:::::---'
rrm-A AA - AAAAI
10,6510.4191
10.1510.4001
20
"
7,55 (0.2971
7'~~~G)~1~;;~;;~~:;~~~~~1:0~
~70NOM
4 PLACES
'.27(0.1]601 I I
O,'iii'iQ.ijiij-lt--"f
0,785 (0.0311
~
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A.
B.
C.
D.
Body dimensions do not include mold flash or protrusion.
Mold flash or protrusion shall not exceed 0,15 (0.0061.
Leads are within 0,25 (0.010) radius of true position at maximum material dimension.
Lead tips to be planar within ±0.051 (0.002) exclusive of solder.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
...co
CO
o
8-7
MECHANICAL DATA
OW plastic "small outline" packages
. Each of these "small outline" packages consists of a circuit mounted on a lead frame and encapsulated
within a plastic compound. The compound will withstand soldering temperature with no deformation, and
circuit performance characteristics will remain stable when operated in high-humidity conditions. Leads
require no additional cleaning or processing when used in soldered assembly.
24·PIN DW PACKAGE
1S.51.0.610.';;;J
15,310.802}
-
- - -
13
0,78510.031\
~
U
1,27(0.0501 TP
ALL LINEAR DIMENSIDNS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A.
B.
C.
D.
Body dimensions do not include mold flash or protrusion.
Mold flash or protrusion shall not exceed 0,15 10.006),
Leads are within 0,25 (0.0101 radius of true position at maximum material dimension.
Lead tips to be planar within ±O,051 (O.002) exclusive of solder.
II
8-8
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MECHANICAL DATA
FK ceramic chip carrier packages
Each of these hermetically sealed chip carrier packages has a three-layer ceramic base with a metal lid
and braze seal. The packages are intended for surface mounting on solder lands on 1,27 (O.050-inch)
centers. Terminals require no additional cleaning or processing when used in soldered assembly.
FK package terminal assignments conform to JEDEC Standards 1, 2, and 11.
FK CERAMIC CHIP CARRIER
(28·terminal package shown)
CERAMIC CHIP CARRIERS
JEOEC
OUTLINE
DESIGNATION-
MS004CB
NO. OF
TERMINALS
20
MSOO4CC
28
MSOO4CD
44
MSOO4CF
88
MSOO!1oCG
8'
A
C
M'N
MAX
MAX
M'N
B,89
9.09
1,63
2.03
(0.342)
'0.358)
9.09
(0,3581
'0.084)
10.080)
",23
'1,63
(0.458)
16,78
11.63
1,63
2.03
(0.458)
14.22
10.560)
21,89
(O.Q641
10.OBO)
3,05
10.1201
10.8&2)
1.75.
(0.069)
2,08
(0.082)
27,06
11.0651
10.0821
CD.422)
16.26
10.640)
28,83
10.938)
28.83
11.1351
IO.6~1
24,43
10.9621
29.59
11.185)
2.0lf
MAX
~.O5
10.1201
3,05
(0.120)
• All dimensions and notes for the specified JEDEC outline apply.
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.~
,..
C6
.s:::.
(,)
CD
I I
J+-
0.71 (0.0281
0,56 (0.0221 -+j
:E
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS ANO PARENTHETICALlY IN INCHES
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
II
8-9
MECHANICAL DATA
FN plastic chip carrier package
Each of these chip carrier packages consists of a circuit mounted on a lead frame and encapsulated within
an electrically nonconductive plastic compound. The compound withstands soldering temperatures with
no deformation. and circuit performance characteristics remain stable when the devices are operated in
high-humidity conditions. The packages are intended for surface mounting on solder lands on 1.27 (0.050)
centers. Leads require no additional cleaning or processing when used in soldered assembly.
FN PLASTic CHIP CARRIER
(28-terminal packalie used for illustration)
Ii' .
122 (0 048)
X45°
1,07 (0.042)
V
0
25
h
6
24
D
7
23
5
u~:
4
3
2
1
28
27
26
22
21
2.
19
12
13
14
15
16
17
I
18
.I~I' 0,25 (0.010)
B
14-_ _ _ _ _ A_(S_e_e_N_o_te_A_)_~..
I!'
JEDEC
OUTLINE
MO-047AA
NO. OF
TERMINALS
20
MO-047AB
28
MO·047AC
44
MO-047AE
68
Mb-047AF
84
3 PLACES
C
8
A
9.78
10.3851
(0.3951
12.32
12.57
MIN
8.89
(0.3501
11.43
(0.4851
17.40
(0.6851
(0.4951
(0.4501
17.65
(0.6951
16.66
(0.6561
25.02
(0.9851
30.10
2 •• 27
(0.9951
30.35
16.51
(0.6501
24.13
(0.9501
(1.1851
11.1951
29.21
11.1501
29,41
MIN
I
MAX
10,03
SEATING PLANE
(See Note C)
R MAX
MAX
9.04
(0.3561
11.58
(0.4561
24.33
(0.956)
(1.1581
MIN
MAX
7.87
(0.3101
10.41
(0.4101
15,49
(0.6101
8.38
(0.3301
23.11
(0.9101
27.69
11.0901
23.62
0.81 (O.032)--f'-+I
0.66 (0.026)
~T
'1,52 (0.060) MIN
10.92
(0.4301
16.00
(0.6301
(0.9301
l.-l
I ;;;64 (0.025) MIN
0,51 (0.020) ->I I ~
0,36 (0.014)
LEAD DETAIL
I
28.70
11.1301
All dimensions and notes for the specified JEDEC outline apply.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
A. Centerline of center pin each side is within 0,10 (0.004) of package centerline as determined by dimension B.
B. Location of each pin is within 0,127 (0.005) of true position with respect to center pin on each side.
C. The lead contact points are planar within 0,10 (0.004).
8-10
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 76265
MECHANICAL DATA
GB pin-grid-array ceramic package
This is a hermetically sealed package with metal cap and gOld-plated pins.
58-PIN G8
r - 2 9 . S (1.1601
27.4 (1.0801
INDEX CORNERt
I
l
29.5 (1.1601
~JM"
4 95 (0 1951
1.52 (0.0601
2:54(o:1001~1
I
=====L-.-"
jl.02(0.0401
2.54 (0.1001 T.P.
(See Note A)
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1
2
3
4
5
6
7
8
9
10 11
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
L - - -_ _ _ _ _ - - - ' - '
t Index mark may appear on top or bottom depending on package vendor.
:t Not featured on single level ceramic packages.
NOTE A: Pins are located within 0,13 (0.005) radius of true position relative to each other at maximum material condition and within
0,25 10.010) radius relative to the center of the ceramic.
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
8-11
••
MECHANICAL DATA
GB pin-grid-array ceramic package (Form 1)
This is a hermetically sealed package with metal cap and gold-plated pins.
84·PIN GB (FORM 1)
r--.
I
FOR MILITARY PARTS ONLY
25.7 (1.010)-----,
25.2 (0.990)
I
INOEX CORNER
3 99 (0 157)
1.65 (0.065)
';"";''''rm=n=ni--"~~L'fUO"""
j
3.30 ( 0 . 1 3 0 ) F l L 0 2 0 ) II
2.79 (0.110)
0.406 (0.016)--.J~
(84 PLACES)
2.54 (0.100) T.P.,
j
.
L
22.86 (0.900) REF
C
...
as
I»
II
r--
1.575 (0.062)
1.473 (0.058)
0
2.54 (0.100) T.P.
K 0®®0®®0000
J
DIA
0®0®®®00®®h
H ®®®®®®00001
G 0®®
F ® ® ®
000
0 0 0
E®00
0®®
o
®0®
0®®
I
c®®000®®®®0
80®®000®0®0
A
®®®®®®®000
1
2
3
4
5
6
7
8
9 10
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Pins are located within 0.13 (0.005) radius of true position relative to each other at maximum material condition and within
0.25 (0.010) radius relative to the center of the ceramic.
8-12
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXA.S 75265
MECHANICAL DATA
GB pin-grid-array ceramic package (Form 2)
This is a hermetically sealed package with metal cap and gold-plated pins.
r
84-PIN GB IFORM 21
INDEX CORNER
30.0 11.1801----,
27.4 11.0801
I
4.95 10.195)
2'5410.100)~1
1.40 10.055)
11.1410.045)
I
.~"".it.llL~U ij ij ~tt,,,~.,,.
2.5410.100)
0.40610.016)
(84 PLACES)
DIA 14 PLACES)
2.54 10.100) T.P.
2.5410.100) T.P.
ISee Note A)
I~G
LK
25.411.000) REF
F
L~
00000000000
00000000000
00
000
00
00
00
000
000
000
000
~8G
00
EXTRAPIN
/
0®®
00
00(2f 000
00
00000000000
00000000000
1
2
3
4
5
6
7
8
9,10 11
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Pins are located within 0.13 (0.005) radius of true position relative to each other at maximum material condition and within
0.25 (0.010) radius relative to the center of the ceramic.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
...asas
o
Cii
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as
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(,)
Q)
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•
8-13
MECHANICAL DATA
GB pin-grid-array ceramic package
This is a hermetically sealed package with metal cap and gold-plated pins.
100-PiN GB
35.1 (1.3801
32.5 (1.2801
I~
INDEX CORNER
...
l
1
4.95 (0.1951
2.54 (0. 1001
- -
I
I
35.1 (1.3801
32.5 (1.2801
1.40 (0.0651
(0.0451
~1.14
<~ ",~FL...a-vff~- V-C~0.1" " t~~.u"'---""-~
" "'8 ~ ~~~ -v->r'~tt·" "'~, ~.
2.54 (0.1001
2.54 (0.1001 T'P'1
I
OIA (4 PLACESI
2.54 (0.1001 T.P.
(So. Note Ai
0 -0-0"--0-0-0--0-0---:-0-0~0
N~: ri0-0+-0"""'0-00
00000000000001
00
000
00
00
00
00
00
30.5 (1.2001 REF H 000
0'00
G 00'0
000
F 000
000
E 00/EXTRAPIN
00
D 00
00
c00 0
000
00
80000000000000
"-----A ~00000000000e
1 2 3 4 5 6 7 8 9 10 11 12 13
...C
I»
I»
•
I
0.406 (0.0161
(100 PLACESI
ALL'LlNEAR D(MENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Pins are located within 0,13 (0.0051 radius of true position relative to each other at maximum material condition and within
0,25 (0.0101 radius relative to the center of the ceramic.
8-14
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MECHANICAL DATA
GB pin-grid-array ceramic package
This is a hermetically sealed package with metal cap and gold-plated pins.
108-PIN G8
30.8 (1.2121----,
30.0 (1.1801
I
INDEX CORNER
'
4.95 (0.1951
2.54 (0'1001~.
I
f J.50t"(~r-.0" 1+7,11 (0.280)
6,81 (0.2601
2,0 (O.080) NOM
0,25 fO.010) NOM
-SEATING
20 PLACES - . \ \ - - : : :
PlANE----I:--.--
~:::~~:
20 PLACES
(See Note HI
J~~ ., .,
(0.076'
~ 1,02 (0.040)
4 PLACes
VIEW A
Parts may be supplied in accordance
with the alternate side view at the
option of
TI.
European-manufactured
parts may have pin 1 ilIlshown in
view A. Altllrnate-side-view parts
manufactured outside of the USA
may have a maximum package length
of 26,7 (1.050).
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0,25 (0.0101 of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.0201 above seating
plane.
II
8-28
TEXAS ..,
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
MECHANICAL DATA
24-PIN NT PLASTIC, 0.300-INCH ROW SPACING
31,8 (1.250)
~------------~28~,6~(1~.1~2~5Ii------------~
•
'"~: :'.~" '~ i~: '::=i!:::: vvvvvV
•
I
i<---->i-t--7,l (0.280) MAX
I.....,
r---:-r
0,38 (0.015)
CD 0 0 0 CD ~
f"6\ 0) CD fii\@t;";'I
t;2\
~
\:.:.I I..:.:J
f---2,O (0.080) NOM
r l M I N-01 1.--- 1,78 (0.070) 24 PLACES
~-~rT1~1__~l,_14_(~0_.0_4~5)____________________- ,
~i
! =-
O,25 10.010) NOM 5,08(0.200)
MAX
105'
-SEATING PLANE
go'
~
24 PLACES
ir
lV
j
T
~
I..--- 0,38 (0.014)
0.25 (0.010)
24 PLACES
(See Not. B)
406 (0 160)
3'17 (0'125)
•
16 (0 085)
0:71 (0:028)
- ~
I
I
~
--I ~ 1.14 (0.045) MIN
24 PLACES
--I f.--- 0,533 (0.021)
2
4 PLACES
PIN SPACING 2.54 (0.100) T.P.
0.381 (0.015)
24 PLACES
(See Not. B)
(See Note A)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0,25 (0.0101 of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 10.020) above seating
plane.
...co
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:E
II
TEXAS "
INSfRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
8-29
MECHANICAL DATA
NW PLASTIC
(28-PIN PACKAGE SHOWN)
14------36.611.440) MAX------o{
~
DIM
24
28
40
48
A ±0.25
15.24
15.24
15.24
15.24
(0.0101
(0.6001
(0.600)
(0.6001
0.6001
8 (MAX)
C ±0.51
(0.020)
32:8
36.6
.53.1
62.2
11.290)
(1.440)
(2.090)
(2.451
1.91
1.27
1.91
1.40
(0.0751
(0.0501
(0.075)
(0.055)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Each pin centerline is located within 0.25 (0.010) of its true longitudinal position.
C
...
AS
AS
II
8-30
. TEXAS'"
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MECHANICAL DATA
P plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on an 8-lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation and circuit
performance characteristics remain stable when operated in high-humidity conditions. The package is
intended for insertion in mounting-hole rows on 7,62-mm (0.300) centers (see Note A). Once the leads
are compressed and inserted, sufficient tension is provided to secure the package in the board during
soldering. Solder-plated leads require no additional cleaning or processing when used in soldered assembly.
a·PIN P PLASTIC
'i.
rII
'62 (0,3001 T.P.]'i.
(0000
(See Note AI
rt7
6,36 ± 0.026
(0.250 ± 0.0101
1\1
MAX
-*--SEATING
PLANE~-~- ~
, . GAUGE PLANE
I L0,76 (0.0301
0,00 (0.000)
\
J~~
0.28
±
I
0,08
(0.011 ± 0.003)
8 PLACES
3,17(0.12511
MIN
~
2,54 (0.100) T.P.
6 PLACES
(See Note AI
---l J.- 0,457 ± 0,076
(0.018 ± 0.003)
8 PLACES
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Each pin centerline is located within 0,25 (0.0101 of its true longitudinal position.
...caca
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II
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
8-31
C
I»
I»
II
8-32
TI Sales Offices
ALABAMA, Hunlaville (205)837-7530.
TI Regional
Techriology Centers
ARIZONA: Phoenix (602) 995-1007;
llIcson (602) 624-3276.
CAUFORNIA: Irvine (714) 660-8187;
Sacramento (916) 929-1521; San Diego (619) 278-9601;
Santa Clara (408) 980-9000; Torrance (213) 217-7010;
Woodland Hills (818) 704-n59.
CAUFORNIA: Irvine (714) 660-8140,
Santa Clara (408) 748-2220.
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ILLINOIS: Arlington Heights (312) 640-2909.
COLORADO: Aurora (303) 368-8000.
MASSACHUSETIS: Waltham (617) 895-9197.
CONNEC'nCUT: Wallingford (203) 269-0074.
TEXAS: Richardson (214) 680-5066.
FLORIDA: Ft. Lauderdale (305) 973-8502;
Maitland (305) 660-4600; Tampa (813) 870-6420.
GEORGIA: Norcross (404)662-7900.
ILUNOIS: Arlington HeIghts (312) 640-2925.
INDIANA: Ft. Wayne (219) 424-5174;
TIASIC
Distributors
CANADA: Napean, OntariO (613) 726-1970
ENGLAND: BedfOrd 44 234 67466
TI AUTHORIZED ASIC DISTRIBUTORS
IN USA
Arrow Electronics
Wyle Laboratories
TI AUTHORIZED ASIC DISTRIBUTORS
IN CANADA
Arrow Electronics Canada
FRANCE: Paris 33 3 946 9712
HONG KONG: Hong Kong 852 3 722 1223
ALABAMA: Huntsville: Arrow (205) 837-6955.
Indianapolis (317) 248-8555.
ITALY: Milan 39 2 253 2451; Rletl39 746 6941
IOWA: Cedar Rapids (319) 395-9550.
JAPAN: Tokyo 81 34982111
:::!~:~~~~roo=2~~~~ 968-4800;
MARYLAND: BaHlmore (301) 944-8600.
WEST GERMANY: Hannover 49 511 648021
CALIFORNIA: Los Angeies'
MASSACHUSETTS: WalthaM (617) 895-9100.
MICHIGAN: Farmington Hills (313) 553-1500;
Grand Rapids (616) 957-4200.
MINNESOTA: Eden Prairie (612) 828-9300.
::.S~~S~~1~~;~7~. (816) 523-2500;
Customer
Response Center
NEW JERSEY: Iselin (201) 750-1050.
NEW MEXICO: Albuquerque (505) 345-2555.
TOLL FREE: (BOO) 232-3200
~~~~:d7~~~~I~~:'1~11~ ~-)9l:J:S600;
OUTSIDE USA: (214) 995-6611
(8:00 a.m.-5:00 p.m. CST)
Plttaford (716) 385..f)770;
Poughkeepsie (914) 473-2900.
~~Y;1~)~:2~~1~r;;.~W~r~~~II~~) 838-5422;
~~:n~~~r:I;~!7;:l_~~s6~53*;
Wyle (916) 638--5282; San Diego: Arrow (619) 565-4800;
Wyle (619) 565-9171; San Francisco Bay Area:
Arrow (408) 745-6600,* (415) 487-4600; Santa Clara:
Wyle (408) 727-2500.*
COLORADO: Aurora: Arrow (303) 696-1111; Thornton:
Wyle (303) 457-9953.*
CONNECTICUT: Wallingford: Arrow (203) 265-7741.
FLORIDA: Ft. lauderdale: ArroN (305) 429-8200;
Orlando: Arrow (305) 725-1480;
Tampa: Arrow (813) 57tMJ995.
GEORGIA: Norcross: Arrow (404) 449-8252.
NORTH CAROLINA: CharioUe (704) 527-0930;
Raleigh (919) 876-2725.
ILLINOIS: Schaumburg: Arrow (312) 397-3440.
OHIO: Beachwood (216) 464-6100;
Dayton (513) 258-3877.
INDIANA: Indianapolis: Arrow (317) 243-9353.
IOWA: Cedar Rapids: Arrow (319) 395-7230.
OREGON: Beaverton (503) 643-6758.
KANSAS: Kansas City: Arrow (913) 541-9542.
PENNSYLVANIA: Ft. Washington (215) 643-6450;
Coraopolis (412) 771·8550.
MARYLAND: Columbia: Arrow (301) 995-0003.
PUERTO RICO: Hato Ray (809) 753-8700
MASSACHUSETTS: Woburn: Arrow (617) 933-8130.
TEXAS: Austin (512) 250-7655;
Houston (713) 778-6592; Richardson (214) 680-5082;
San Antonio (512) 496-1779.
MICHIGAN: Detroit: Arrow (313) 971-8220;
Grand Rapids: Arrow (616) 243-0912.
MINNESOTA: Edina: Arrow (612) 830-1800.
UTAH: Murray (801) 266-8972.
MISSOURI:
VIRGINIA: Fairfax (703) 849-1400.
St. Louis: Arrow (314) 567-6BBB.
~:a~~~~PSHIRE: Manchester: ArrrY'N (603)
WASHINGTON: Redmond (206) 881-3080.
WISCONSIN: Brookfield (414) 785-7140.
NEW JERSEY: Fairfield: Arrow (201) 575-5300;
Marlton: (609) 596-8000.
~~:,~~~';:~~~~~6~6:l~~~11;970;
NEW MEXICO: Albuquerque: Arrow (505) 243-4566.
St. Laurent, Quebee (514) 335-8392.
~~;;V~!:~~:p~~:r:~:'oo~~516) 231-1000;
Syracuse: Arrow (315) 652-1000; Melville: Arrow
(516) 694-6800.*
NORTH CAROLINA: Raleigh: Arrow (919) 876-3132;
Winston Salem: (919) 725-8711OHIO: Cleveland: Arrow (216) 248-3990;
Columbus: Arrow (614) 885-8362;
Dayton: Arrow (513) 435-5563.
OKLAHOMA: liIlsa: Arrow (918) 665-7700.
~l~~~~) ~~~~~~row (503) 684-1690;
PENNSYLVANIA: Monroeville: Arrow (412) 856-7000;
Marlton: (215) 928-1800.
RHODE ISLAND: E. Providence: Arrow
(401) 431-0980.
TEXAS: Austin: Arrow (512) 835-4180;
Wyle (512) 834-9957; Dallas: Arrow (214) 380-6464;
Wyle (214) 235-9953*; Houston: Arrow (713) 530-4700;
Wyle (713) 879-9953.
UTAH: Sait lake City: Arrow (801) 972-0404;
Wyle (801) 974·9953.
WASHINGTON: Bellevue: Arrow (206) 643-4800;
Wyle (206) 453-8300.
WISCONSIN: Brookfield: Arrow (414) 792-0150,
TEXAS
INSTRUMENTS
CANADA: Montreal: Arrow Canada (514) 735-5511;
Ottawa: Arrow Canada (613) 226-6903;
Quebec City: Arrow Canada (418) 687-4231;
Toronto: Arrow Canada (416) 661-0220.
• Design Center
TI Worldwide
Sales Offices
ALABAMA: Hunl,vil": 500 Wynn Drive, Suite 514,
Huntsville, AL 35805, (205) 837-7530.
ARIZONA: Phoenix: 8825 N. 23rd Ave., Phoenix,
AZ 85021, (602) 995·1007.
CALIFORNIA: Irvine: 17891 cartwright Rd., Irvine.
~~~~~~::~~~P~t'1~~i~'t')~~W York Or.,
Coraopplls: 420 Rouser Rd., 3 Airport Office Park,
CoraopoliS, PA 15108, (412) 771·8550.
PUERTO RICO: Hato Ray: Mercantil Plaza Bldg.,
Suite 505, Hato Rey, PR 00919, (609) 753-8700,
TEXA~: Austin: P.O. Box 2909, Austil), TX 78769,
~1~~ar~~~fkR~=IOn: 1001 E. Campbell Rd.,
(214) 680-5082; Houst~: 9100 Southwest Frwy.,
Suite 237, Houston, TX 77036, (713) 778-6592;
San Antonio: 1000 Central Parkway South,
San Antonio, TX 78232, (512) 496·1779.
CA 92114, (714) 660-8187; Sacramento: 1900 Point
~~~~~,MJr"a~gr'(J,~u~9e;2~
~J~~ 9~~~:lb~~"o~~..,~~~3 (~~e:) 2~~B:ote.,
VIRGINIA: Fairfax: 2750 Prosperity, Fairfax, VA
22031, (703) 849-1400.
West Way. Suite 171, Sacramento, CA $5815,
~~,~~;: =-~~Vo~~:.~r6gga~~~~~~~, CA
Torrance, CA 90502, (213) 217·7010;
Woodland HIIII: 21220 Erwin St., Woodland 'HillS,
CA 91367, (818) 704-7759.
COLORADO: Aurora: 1400 S. Potomac Ave.,
Suite 101, Aurora, CO 80012, (303) 368-8000.
CONNECTICUT: Wallingford: 9 Barnes Industrial
Park Rd., Barnes Industrial Park, Wallingford,
CT 06492, (203) 269-0074.
'
FLORIDA: Ft. Lauderdale: 2765 N.W. 62nd St.,
Ft. Lauderdale, FL 33309, (305) 973-8502;
Maitland: 2601 Maitland Center Parkway,
Maitland, FL 32751, (305) 660-4600;
Tampa: 5010 W. Kennedy Blvd., Suite 101,
Tampa, FL 33609, (813) 870-8420.
SE, Suite 200,
WASHINGTON: Redmond: 5010 148th NE, Bldg B,
Suite 107, Redmontt, WA 98052, (206) 881·3080.
WISCONSIN: "'rook.lald: 450 N. Sunny Slope,
Suite 150, BrOOkfield, WI 53005, (414) 785·7140.
CANADA: Nepa.n: 301 Moodie Drive, Mallom
Center, Nepean, Ontario, Canada, K2H9C4,
(613) 726·1970. Richmond Hili: 280 Centre St. E.,
Richmond Hili L4C1B1, OntarlQ, Canada
(416) 884·9181; St. Laurent: Ville SI. Laurent Quebec,
~~~aJ!a~:s~~nt~~1~)1~5~9~~urent,
Quebec,
~~r:::n~~F~~t~~~I:f3~:~:~~~:Frasse
1,
D.arH\O Frelsing, 8161 +80-4591; Kurtuerstendamm
1951196,0·1000 Bertin 15, 30+882·7365; III, Hagen
431Kibbelstrasse, .19, 0-4300 Essen, 201·24250;
, Frankfurter Allee 6-8, 0-6236 Eschborm 1,
06196+8010; Hamburgerstrasse 11, 0·2000 Hamburg
76, 040+22().1154, Kirchhorsterstr~se 2, D'~
~~~~vg~~11'd;!~ 2~~~~~~"~'~~~~~; ",
~~~~~:'~~:Ms, ~=t~sebu1rl. ~~+:~~I~~';
261 +35044.
HONG KONG (+ PEOPLES REPUBLIC OF CHINA):
Texas Instruments Asia Ltd., 8th Floor, World
Shipping Ctr., Harbour City, 7 Canton Rd., Kowloon,
Ho~g Kdng, 3 + 722·1223.
IRELAND: Texas Instruments (Ireland) Limited:
Brewery Ad., Stillorgan, County Dublin, Eire,
1831311.
ITALY: Texas Instruments Semiconduttorl Italia Spa:
Viale Delle SClenze, 1,02015 Ciltaducale (Rleti),
Italy, 746 694.1; Via Salarla KM 24 (Palazzo Cosma),
Monte
), Italy, 6+9003241; Vlale
no Monzese (Milano),
0100 Torino, limy,
Cors
Via J. Barozzi 6, 40100 Bologna, Italy, 51
355851,
JAPAN: Texas Instruments Asia Ltd.: 4F Aoyama
Full Bldg., 6·12, Kite Aoyama 3-Chome, Mlnato.ku,
Tokyo, Japan 107, 3-498-2111; Osaka Branch, 5F,
~:~=~j!~~ 8~~~, ~~~~~i~:2~~';1;
Nagoya
Branch, 7F Dalnl Toyota West Bldg., 10-27, Meleki
4·Chome, Nakamura·ku Nagoya, Japan
450, 52·583-8691,
GEORGIA: Norcross: 5515 Spalding Drive, Norcross,
GA 30092, (404) 662-7900
ARGENTINA: Texas Instruments Argentina
S.A.l.e,F.: E8mer~lda 130, 15th Floor, 1035 Buenos
Aires, Argentina, 1 +394-3008.
!:"r~il~g~~~: ~!\~t~~~LH=~: (~~:) ~t~R~~.qUin,
AUSTRALIA (6 NEW ZEALAND): Texas Instruments
Australia Ltd,: 6·10 Talavera Rd., North Ryde
:~~~~: (~~'9~:J~~:~~
~~d~~~1 ~~ 5~~u~~~~4~~ :t~S~~:~ ~~~:
MEXICO: Texas Instruments de Mexico S.A.: Mexico
g~~: ~f~~m5~!$oo~~ - 10th Floor, Mexico,
8 + 255-2066.
MIDDLE EAST: Texas Instruments: No. 13, 1st Floor
Inwood Or" Ft. Wayne:
Indianapolis: 2346 S. Lynhurst, Suite J-400,
Indianapolis, IN 46241, (317) 248-8555,
IOWA: Cedar Rapids: 373 Collins Rd, NE, Suite 200,
Cedar Rapids, IA 52402, (319) 395·9550.
MARYLAND: aaltlmore: , Rutherford Pl.,
7133 Rutherford Rd., Baltimore, MD 21207,
(301) 944-8600.
MASSACHUSETTS: Waltham: 504 Totten Pond Rd.,
Waltham, MA 02154, (61'7) 895·9100,
Melbourne, Victoria, Australia 3004, 3 + 267-4677;
171 Philip Highway, Elizabeth, South Australia 5112,
AUSTRIA: Texas Instruments Ges.m.b.H.:
Industriestrabe B116, A·2345 8runnf(lebirge,
2236-846210,
~~~;J~Mde~~:~ ~~~~~rr::~~:R:18~u~ ~u~e,
=~~':T~r,~~':d~~'~o':~~~ (~o~s: PB106,
~~~~~~~: ~~~I~t~~~I,I(1;i)7~~~5M. Mile Ad"
DENMARK: Texas Instruments AlS, Mairelundvej
46E, DK·2730 Herlev, Denmark, 2 • 91 74 00.
~i\~~~R~:4~f:.ia~~1~3~yvard
FINLAND: Texas Instruments Finland OY:
Teollisuuskatu 19000511 Helsinki 51, Finland, (90)
701·3133.
FRANCE: Texas Instruments France: Headquarters
and Prod. Plant, BP 05, 06270 Vilieneuve·Loubet,
~~r:~~~~I;nr:rls Office, BP 67 8-10 Avenue
~~~I;~¥,1(5~~i~~;.g~&tP?iS~:c.~, ~~~~~~'St.,
Pittsford, NY 14534, ~'6) 385·6770;
~,=r,;(~':~)~i3-~~~ Rd., Poughkeepsie,
NORTH CAROLlt;l4: Charlotte: 8 Woodlawn Green,
Woodlawn Rd., Chartotte, NC 28210, (704) 527-0930;
~~aJ¥:~:'~~~iB~":'~7::' Blvd., Suite 100, Raleigh,
OHIO: Beachwood: 23408 Commerce Pari< Rd.,
Beachwood, OH 44122, (216) 464-6100;
g-:r':~~~(§f1)Y2:~\'7i.124 linden Ave., Dayton,
OREGON: Beaverton: 6700 SW 105th St., Suite 110,
Beaverton, OR 97005, (50;1) 643-6758.
~:!tl~~e~~~!~i~,d~hig~:rn::~f.. g;~f;
PORTUGAL: Texas Instruments Equipamento
G:~t~~~ (:~:W:IBaL~aala~~~7~n~.f!~~r~~~al,
2·948-1003.
'~A~t:3:: 4:x=?~:tr~~~rse:!~~ ~:~~Sl~;ong
Bak~ Batu, Unit 01·02, Kolam Ayer Industrial Estate,
Republic of Singapore, 747·2255.
SPAIN: Texas Instruments Espana, S.A.: CfJose
Lazaro Galdiano No.6, Madrid 16, 1f458.14.58.
~~~A~~~~~u~~b~~U;~~~:, f:£"~4~~~~3~ent Pkwy
~:::CJ!!~~:ye;-;~~3~~~~9r;ollamer Dr., East,
Endicott: 112 Nanticoke Ave., P.O. Box 618, Endicott,
NY 13760, (607) 754·3900; Malvilla: 1 Huntington
~:~~aB~~r.?~~I~~~f~~ ~~~ :7~·+~~~~35,
NETHERLANDS: Texas Instruments Holland B.V.,
P.O. Box 12995, (Bullewijk) 1100 CB Amsterdam,
Zuid·Oost, Holland 20 + 5602911.
PHILIPPINES: Texas Instruments Asia Ltd.: 14th
MINNESOTA: Edan Pralrla: 11000 W, 78th $t.,
Eden Prairie, MN 55344' (612) 828·9300.
NEW JERSEY: Isalln: 485E U.S, Route 1 South,
Parkway Towers, Iselin, NJ 08830 (201) 750·1050
~~g~~:?~O~~~S:4e~~fangnam.ku,
1130 Brussels, Belgium, 21720.80.00.
BRAZIL: Texas Instruments Electronicos do Brasil
Ltda.: Rua Paes Leme, 524·7 Andar Pinheiros, 05424
Sao Paulo, Brazil, 0815-6166.
PkWY" Kansas
St. Louis: 11816 Borman Drive, SI. Louis,
MO 63148, (314) 589-7600.
KOREA: Texas Instruments Supply Co.: 3rd Floor,
3, Quai Kleber, 67055 Strasbourg Cedex,
SWEDEN: Texas Instruments InternationaJ Trade
Corporation (Sverigefilialen): Box 39103, 10054
Stockholm, Sweden, 8 . 235480.
Le Peripole-2, Chemin du Plgeonnler de la Caplere,
31100 Toulouse, (61) 44·18-19; Marseille Sales Office,
~~11~7~~38~s-146 Rue Paradis, 13006 Marseille,
SWITZERLAND: Texas Instruments, Inc., Reidstrasse
6, CH·8953 Dielikon (ZueriCh) Switzerland,
1-7402220,
~s:l~2~:~6~s~~e~1'~:~; ~~I~~~u~:I~~?~~e,
•
TEXAS
INSTRUMENTS
~~~~~~~:~SR~~¥~~~~~~~gl~~~~ ~~~,903,
Taiwan, Republic of China, 2 + 521-9321 .
UNITED KINGDOM: Texas Instruments limited:
Manton Lane, Bedford, MK41 7PA, England, 0234
~~:cs:~~~, JS~e~R~~Esn~I~~,Ii~~~~~'~~2~orth,
8M
."
986-100
Printed in U.S.A.
TEXAS
INSTRUMENTS
SRSDOO1
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